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// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module vfabric_return(clock, resetn,
i_returnin, i_returnin_valid, o_returnin_stall,
i_dataa, i_dataa_valid, o_dataa_stall,
i_datab, i_datab_valid, o_datab_stall,
i_datac, i_datac_valid, o_datac_stall, i_datad, i_datad_valid, o_datad_stall,
o_kernel_done, i_start, i_counter_value, i_settings, i_counter_reset,
o_counter_value, o_return_data, o_return_valid);
parameter DATA_WIDTH = 1;
parameter RETURN_DATA_WIDTH = 32;
parameter CONFIG_WIDTH = 4;
parameter FIFO_DEPTH = 64;
input clock, resetn;
input [RETURN_DATA_WIDTH-1:0] i_returnin;
input [DATA_WIDTH-1:0] i_dataa, i_datab, i_datac, i_datad;
input i_dataa_valid, i_datab_valid, i_datac_valid, i_datad_valid, i_returnin_valid;
output o_dataa_stall, o_datab_stall, o_datac_stall, o_datad_stall, o_returnin_stall;
output [DATA_WIDTH-1:0] o_kernel_done;
output reg [RETURN_DATA_WIDTH-1:0] o_return_data;
output reg o_return_valid;
input i_start;
input [31:0] i_counter_value;
input [CONFIG_WIDTH-1:0] i_settings;
input i_counter_reset;
output [31:0] o_counter_value;
wire is_fifo_stalled;
wire is_returnin_valid, thread_finished;
wire data_to_count, data_to_count_valid;
wire [RETURN_DATA_WIDTH-1:0] returnin;
reg [31:0] counter_val;
wire fifo_a_valid, fifo_b_valid, fifo_c_valid, fifo_d_valid;
wire is_fifo_a_valid, is_fifo_b_valid, is_fifo_c_valid, is_fifo_d_valid;
vfabric_counter_fifo fifo_a( .clock(clock), .resetn(resetn),
.i_counter_reset(i_counter_reset),
.i_datain_valid(i_dataa_valid), .o_datain_stall(o_dataa_stall),
.o_dataout_valid(fifo_a_valid), .i_dataout_stall(is_fifo_stalled));
vfabric_counter_fifo fifo_b( .clock(clock), .resetn(resetn),
.i_counter_reset(i_counter_reset),
.i_datain_valid(i_datab_valid), .o_datain_stall(o_datab_stall),
.o_dataout_valid(fifo_b_valid), .i_dataout_stall(is_fifo_stalled));
vfabric_counter_fifo fifo_c( .clock(clock), .resetn(resetn),
.i_counter_reset(i_counter_reset),
.i_datain_valid(i_datac_valid), .o_datain_stall(o_datac_stall),
.o_dataout_valid(fifo_c_valid), .i_dataout_stall(is_fifo_stalled));
vfabric_counter_fifo fifo_d( .clock(clock), .resetn(resetn),
.i_counter_reset(i_counter_reset),
.i_datain_valid(i_datad_valid), .o_datain_stall(o_datad_stall),
.o_dataout_valid(fifo_d_valid), .i_dataout_stall(is_fifo_stalled));
assign is_fifo_a_valid = fifo_a_valid | ~i_settings[0];
assign is_fifo_b_valid = fifo_b_valid | ~i_settings[1];
assign is_fifo_c_valid = fifo_c_valid | ~i_settings[2];
assign is_fifo_d_valid = fifo_d_valid | ~i_settings[3];
// this fifo buffers up the returnin data
vfabric_buffered_fifo fifo_ret ( .clock(clock), .resetn(resetn),
.data_in(i_returnin), .data_out(returnin), .valid_in(i_returnin_valid),
.valid_out( is_returnin_valid ), .stall_in(is_fifo_stalled),
.stall_out(o_returnin_stall) );
defparam fifo_ret.DATA_WIDTH = RETURN_DATA_WIDTH;
defparam fifo_ret.DEPTH = 2048;
defparam fifo_ret.IMPLEMENTATION_MODE = "RAM";
assign thread_finished = i_start & is_fifo_a_valid &
is_fifo_b_valid & is_fifo_c_valid & is_fifo_d_valid & is_returnin_valid;
assign is_fifo_stalled = ~(is_fifo_a_valid & is_fifo_b_valid & is_fifo_c_valid
& is_fifo_d_valid & is_returnin_valid);
always@(posedge clock or negedge resetn)
begin
if(~resetn)
begin
counter_val <= {CONFIG_WIDTH{1'b0}};
end
else
begin
if (i_counter_reset)
counter_val <= {CONFIG_WIDTH{1'b0}};
else if (thread_finished)
counter_val <= counter_val + 1;
end
end
always@(posedge clock or negedge resetn)
begin
if(~resetn)
begin
o_return_data <= {RETURN_DATA_WIDTH{1'b0}};
o_return_valid <= 1'b0;
end
else
begin
if (i_counter_reset)
begin
o_return_data <= {RETURN_DATA_WIDTH{1'b0}};
o_return_valid <= 1'b0;
end
else
begin
o_return_data <= returnin;
o_return_valid <= thread_finished;
end
end
end
assign o_kernel_done = (i_start && !i_counter_reset && (counter_val == i_counter_value)) ? {DATA_WIDTH{1'b1}} : {DATA_WIDTH{1'b0}};
assign o_counter_value = counter_val;
endmodule
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module VCC (output V);
assign V = 1'b1;
endmodule // VCC
module GND (output G);
assign G = 1'b0;
endmodule // GND
/* Altera Cyclone IV (E) devices Input Buffer Primitive */
module cycloneive_io_ibuf
(output o, input i, input ibar);
assign ibar = ibar;
assign o = i;
endmodule // fiftyfivenm_io_ibuf
/* Altera Cyclone IV (E) devices Output Buffer Primitive */
module cycloneive_io_obuf
(output o, input i, input oe);
assign o = i;
assign oe = oe;
endmodule // fiftyfivenm_io_obuf
/* Altera Cyclone IV (E) 4-input non-fracturable LUT Primitive */
module cycloneive_lcell_comb
(output combout, cout,
input dataa, datab, datac, datad, cin);
/* Internal parameters which define the behaviour
of the LUT primitive.
lut_mask define the lut function, can be expressed in 16-digit bin or hex.
sum_lutc_input define the type of LUT (combinational | arithmetic).
dont_touch for retiming || carry options.
lpm_type for WYSIWYG */
parameter lut_mask = 16'hFFFF;
parameter dont_touch = "off";
parameter lpm_type = "cycloneive_lcell_comb";
parameter sum_lutc_input = "datac";
reg [1:0] lut_type;
reg cout_rt;
reg combout_rt;
wire dataa_w;
wire datab_w;
wire datac_w;
wire datad_w;
wire cin_w;
assign dataa_w = dataa;
assign datab_w = datab;
assign datac_w = datac;
assign datad_w = datad;
function lut_data;
input [15:0] mask;
input dataa, datab, datac, datad;
reg [7:0] s3;
reg [3:0] s2;
reg [1:0] s1;
begin
s3 = datad ? mask[15:8] : mask[7:0];
s2 = datac ? s3[7:4] : s3[3:0];
s1 = datab ? s2[3:2] : s2[1:0];
lut_data = dataa ? s1[1] : s1[0];
end
endfunction
initial begin
if (sum_lutc_input == "datac") lut_type = 0;
else
if (sum_lutc_input == "cin") lut_type = 1;
else begin
$error("Error in sum_lutc_input. Parameter %s is not a valid value.\n", sum_lutc_input);
$finish();
end
end
always @(dataa_w or datab_w or datac_w or datad_w or cin_w) begin
if (lut_type == 0) begin // logic function
combout_rt = lut_data(lut_mask, dataa_w, datab_w,
datac_w, datad_w);
end
else if (lut_type == 1) begin // arithmetic function
combout_rt = lut_data(lut_mask, dataa_w, datab_w,
cin_w, datad_w);
end
cout_rt = lut_data(lut_mask, dataa_w, datab_w, cin_w, 'b0);
end
assign combout = combout_rt & 1'b1;
assign cout = cout_rt & 1'b1;
endmodule // cycloneive_lcell_comb
/* Altera D Flip-Flop Primitive */
module dffeas
(output q,
input d, clk, clrn, prn, ena,
input asdata, aload, sclr, sload);
// Timing simulation is not covered
parameter power_up="dontcare";
parameter is_wysiwyg="false";
reg q_tmp;
wire reset;
reg [7:0] debug_net;
assign reset = (prn && sclr && ~clrn && ena);
assign q = q_tmp & 1'b1;
always @(posedge clk, posedge aload) begin
if(reset) q_tmp <= 0;
else q_tmp <= d;
end
assign q = q_tmp;
endmodule // dffeas
/* Cyclone IV E altpll clearbox model */
(* blackbox *)
module cycloneive_pll
(inclk,
fbin,
fbout,
clkswitch,
areset,
pfdena,
scanclk,
scandata,
scanclkena,
configupdate,
clk,
phasecounterselect,
phaseupdown,
phasestep,
clkbad,
activeclock,
locked,
scandataout,
scandone,
phasedone,
vcooverrange,
vcounderrange);
parameter operation_mode = "normal";
parameter pll_type = "auto";
parameter compensate_clock = "clock0";
parameter inclk0_input_frequency = 0;
parameter inclk1_input_frequency = 0;
parameter self_reset_on_loss_lock = "off";
parameter switch_over_type = "auto";
parameter switch_over_counter = 1;
parameter enable_switch_over_counter = "off";
parameter bandwidth = 0;
parameter bandwidth_type = "auto";
parameter use_dc_coupling = "false";
parameter lock_high = 0;
parameter lock_low = 0;
parameter lock_window_ui = "0.05";
parameter test_bypass_lock_detect = "off";
parameter clk0_output_frequency = 0;
parameter clk0_multiply_by = 0;
parameter clk0_divide_by = 0;
parameter clk0_phase_shift = "0";
parameter clk0_duty_cycle = 50;
parameter clk1_output_frequency = 0;
parameter clk1_multiply_by = 0;
parameter clk1_divide_by = 0;
parameter clk1_phase_shift = "0";
parameter clk1_duty_cycle = 50;
parameter clk2_output_frequency = 0;
parameter clk2_multiply_by = 0;
parameter clk2_divide_by = 0;
parameter clk2_phase_shift = "0";
parameter clk2_duty_cycle = 50;
parameter clk3_output_frequency = 0;
parameter clk3_multiply_by = 0;
parameter clk3_divide_by = 0;
parameter clk3_phase_shift = "0";
parameter clk3_duty_cycle = 50;
parameter clk4_output_frequency = 0;
parameter clk4_multiply_by = 0;
parameter clk4_divide_by = 0;
parameter clk4_phase_shift = "0";
parameter clk4_duty_cycle = 50;
parameter pfd_min = 0;
parameter pfd_max = 0;
parameter vco_min = 0;
parameter vco_max = 0;
parameter vco_center = 0;
// Advanced user parameters
parameter m_initial = 1;
parameter m = 0;
parameter n = 1;
parameter c0_high = 1;
parameter c0_low = 1;
parameter c0_initial = 1;
parameter c0_mode = "bypass";
parameter c0_ph = 0;
parameter c1_high = 1;
parameter c1_low = 1;
parameter c1_initial = 1;
parameter c1_mode = "bypass";
parameter c1_ph = 0;
parameter c2_high = 1;
parameter c2_low = 1;
parameter c2_initial = 1;
parameter c2_mode = "bypass";
parameter c2_ph = 0;
parameter c3_high = 1;
parameter c3_low = 1;
parameter c3_initial = 1;
parameter c3_mode = "bypass";
parameter c3_ph = 0;
parameter c4_high = 1;
parameter c4_low = 1;
parameter c4_initial = 1;
parameter c4_mode = "bypass";
parameter c4_ph = 0;
parameter m_ph = 0;
parameter clk0_counter = "unused";
parameter clk1_counter = "unused";
parameter clk2_counter = "unused";
parameter clk3_counter = "unused";
parameter clk4_counter = "unused";
parameter c1_use_casc_in = "off";
parameter c2_use_casc_in = "off";
parameter c3_use_casc_in = "off";
parameter c4_use_casc_in = "off";
parameter m_test_source = -1;
parameter c0_test_source = -1;
parameter c1_test_source = -1;
parameter c2_test_source = -1;
parameter c3_test_source = -1;
parameter c4_test_source = -1;
parameter vco_multiply_by = 0;
parameter vco_divide_by = 0;
parameter vco_post_scale = 1;
parameter vco_frequency_control = "auto";
parameter vco_phase_shift_step = 0;
parameter charge_pump_current = 10;
parameter loop_filter_r = "1.0";
parameter loop_filter_c = 0;
parameter pll_compensation_delay = 0;
parameter lpm_type = "cycloneive_pll";
parameter phase_counter_select_width = 3;
input [1:0] inclk;
input fbin;
input clkswitch;
input areset;
input pfdena;
input [phase_counter_select_width - 1:0] phasecounterselect;
input phaseupdown;
input phasestep;
input scanclk;
input scanclkena;
input scandata;
input configupdate;
output [4:0] clk;
output [1:0] clkbad;
output activeclock;
output locked;
output scandataout;
output scandone;
output fbout;
output phasedone;
output vcooverrange;
output vcounderrange;
endmodule // cycloneive_pll
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/main/ip/sopc/components/primitives/altera_std_synchronizer/altera_std_synchronizer.v#8 $
// $Revision: #8 $
// $Date: 2009/02/18 $
// $Author: pscheidt $
//-----------------------------------------------------------------------------
//
// File: altera_std_synchronizer_nocut.v
//
// Abstract: Single bit clock domain crossing synchronizer. Exactly the same
// as altera_std_synchronizer.v, except that the embedded false
// path constraint is removed in this module. If you use this
// module, you will have to apply the appropriate timing
// constraints.
//
// We expect to make this a standard Quartus atom eventually.
//
// Composed of two or more flip flops connected in series.
// Random metastable condition is simulated when the
// __ALTERA_STD__METASTABLE_SIM macro is defined.
// Use +define+__ALTERA_STD__METASTABLE_SIM argument
// on the Verilog simulator compiler command line to
// enable this mode. In addition, define the macro
// __ALTERA_STD__METASTABLE_SIM_VERBOSE to get console output
// with every metastable event generated in the synchronizer.
//
// Copyright (C) Altera Corporation 2009, All Rights Reserved
//-----------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_std_synchronizer_nocut (
clk,
reset_n,
din,
dout
);
parameter depth = 3; // This value must be >= 2 !
parameter rst_value = 0;
input clk;
input reset_n;
input din;
output dout;
// QuartusII synthesis directives:
// 1. Preserve all registers ie. do not touch them.
// 2. Do not merge other flip-flops with synchronizer flip-flops.
// QuartusII TimeQuest directives:
// 1. Identify all flip-flops in this module as members of the synchronizer
// to enable automatic metastability MTBF analysis.
(* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name SYNCHRONIZER_IDENTIFICATION FORCED; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON "} *) reg din_s1;
(* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg [depth-2:0] dreg;
//synthesis translate_off
initial begin
if (depth <2) begin
$display("%m: Error: synchronizer length: %0d less than 2.", depth);
end
end
// the first synchronizer register is either a simple D flop for synthesis
// and non-metastable simulation or a D flop with a method to inject random
// metastable events resulting in random delay of [0,1] cycles
`ifdef __ALTERA_STD__METASTABLE_SIM
reg[31:0] RANDOM_SEED = 123456;
wire next_din_s1;
wire dout;
reg din_last;
reg random;
event metastable_event; // hook for debug monitoring
initial begin
$display("%m: Info: Metastable event injection simulation mode enabled");
end
always @(posedge clk) begin
if (reset_n == 0)
random <= $random(RANDOM_SEED);
else
random <= $random;
end
assign next_din_s1 = (din_last ^ din) ? random : din;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_last <= (rst_value == 0)? 1'b0 : 1'b1;
else
din_last <= din;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_s1 <= (rst_value == 0)? 1'b0 : 1'b1;
else
din_s1 <= next_din_s1;
end
`else
//synthesis translate_on
generate if (rst_value == 0)
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_s1 <= 1'b0;
else
din_s1 <= din;
end
endgenerate
generate if (rst_value == 1)
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_s1 <= 1'b1;
else
din_s1 <= din;
end
endgenerate
//synthesis translate_off
`endif
`ifdef __ALTERA_STD__METASTABLE_SIM_VERBOSE
always @(*) begin
if (reset_n && (din_last != din) && (random != din)) begin
$display("%m: Verbose Info: metastable event @ time %t", $time);
->metastable_event;
end
end
`endif
//synthesis translate_on
// the remaining synchronizer registers form a simple shift register
// of length depth-1
generate if (rst_value == 0)
if (depth < 3) begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
dreg <= {depth-1{1'b0}};
else
dreg <= din_s1;
end
end else begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
dreg <= {depth-1{1'b0}};
else
dreg <= {dreg[depth-3:0], din_s1};
end
end
endgenerate
generate if (rst_value == 1)
if (depth < 3) begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
dreg <= {depth-1{1'b1}};
else
dreg <= din_s1;
end
end else begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
dreg <= {depth-1{1'b1}};
else
dreg <= {dreg[depth-3:0], din_s1};
end
end
endgenerate
assign dout = dreg[depth-2];
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_nios2_gen2_0_cpu_debug_slave_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
(** * Types: Type Systems *)
Require Export Smallstep.
Hint Constructors multi.
(** Our next major topic is _type systems_ -- static program
analyses that classify expressions according to the "shapes" of
their results. We'll begin with a typed version of a very simple
language with just booleans and numbers, to introduce the basic
ideas of types, typing rules, and the fundamental theorems about
type systems: _type preservation_ and _progress_. Then we'll move
on to the _simply typed lambda-calculus_, which lives at the core
of every modern functional programming language (including
Coq). *)
(* ###################################################################### *)
(** * Typed Arithmetic Expressions *)
(** To motivate the discussion of type systems, let's begin as
usual with an extremely simple toy language. We want it to have
the potential for programs "going wrong" because of runtime type
errors, so we need something a tiny bit more complex than the
language of constants and addition that we used in chapter
[Smallstep]: a single kind of data (just numbers) is too simple,
but just two kinds (numbers and booleans) already gives us enough
material to tell an interesting story.
The language definition is completely routine. The only thing to
notice is that we are _not_ using the [asnum]/[aslist] trick that
we used in chapter [HoareList] to make all the operations total by
forcibly coercing the arguments to [+] (for example) into numbers.
Instead, we simply let terms get stuck if they try to use an
operator with the wrong kind of operands: the [step] relation
doesn't relate them to anything. *)
(* ###################################################################### *)
(** ** Syntax *)
(** Informally:
t ::= true
| false
| if t then t else t
| 0
| succ t
| pred t
| iszero t
Formally:
*)
Inductive tm : Type :=
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm
| tzero : tm
| tsucc : tm -> tm
| tpred : tm -> tm
| tiszero : tm -> tm.
(** _Values_ are [true], [false], and numeric values... *)
Inductive bvalue : tm -> Prop :=
| bv_true : bvalue ttrue
| bv_false : bvalue tfalse.
Inductive nvalue : tm -> Prop :=
| nv_zero : nvalue tzero
| nv_succ : forall t, nvalue t -> nvalue (tsucc t).
Definition value (t:tm) := bvalue t \/ nvalue t.
Hint Constructors bvalue nvalue.
Hint Unfold value.
Hint Unfold extend.
(* ###################################################################### *)
(** ** Operational Semantics *)
(** Informally: *)
(**
------------------------------ (ST_IfTrue)
if true then t1 else t2 ==> t1
------------------------------- (ST_IfFalse)
if false then t1 else t2 ==> t2
t1 ==> t1'
------------------------- (ST_If)
if t1 then t2 else t3 ==>
if t1' then t2 else t3
t1 ==> t1'
-------------------- (ST_Succ)
succ t1 ==> succ t1'
------------ (ST_PredZero)
pred 0 ==> 0
numeric value v1
--------------------- (ST_PredSucc)
pred (succ v1) ==> v1
t1 ==> t1'
-------------------- (ST_Pred)
pred t1 ==> pred t1'
----------------- (ST_IszeroZero)
iszero 0 ==> true
numeric value v1
-------------------------- (ST_IszeroSucc)
iszero (succ v1) ==> false
t1 ==> t1'
------------------------ (ST_Iszero)
iszero t1 ==> iszero t1'
*)
(** Formally: *)
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_IfTrue : forall t1 t2,
(tif ttrue t1 t2) ==> t1
| ST_IfFalse : forall t1 t2,
(tif tfalse t1 t2) ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
(tif t1 t2 t3) ==> (tif t1' t2 t3)
| ST_Succ : forall t1 t1',
t1 ==> t1' ->
(tsucc t1) ==> (tsucc t1')
| ST_PredZero :
(tpred tzero) ==> tzero
| ST_PredSucc : forall t1,
nvalue t1 ->
(tpred (tsucc t1)) ==> t1
| ST_Pred : forall t1 t1',
t1 ==> t1' ->
(tpred t1) ==> (tpred t1')
| ST_IszeroZero :
(tiszero tzero) ==> ttrue
| ST_IszeroSucc : forall t1,
nvalue t1 ->
(tiszero (tsucc t1)) ==> tfalse
| ST_Iszero : forall t1 t1',
t1 ==> t1' ->
(tiszero t1) ==> (tiszero t1')
where "t1 '==>' t2" := (step t1 t2).
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_IfTrue" | Case_aux c "ST_IfFalse" | Case_aux c "ST_If"
| Case_aux c "ST_Succ" | Case_aux c "ST_PredZero"
| Case_aux c "ST_PredSucc" | Case_aux c "ST_Pred"
| Case_aux c "ST_IszeroZero" | Case_aux c "ST_IszeroSucc"
| Case_aux c "ST_Iszero" ].
Hint Constructors step.
(** Notice that the [step] relation doesn't care about whether
expressions make global sense -- it just checks that the operation
in the _next_ reduction step is being applied to the right kinds
of operands.
For example, the term [succ true] (i.e., [tsucc ttrue] in the
formal syntax) cannot take a step, but the almost as obviously
nonsensical term
succ (if true then true else true)
can take a step (once, before becoming stuck). *)
(* ###################################################################### *)
(** ** Normal Forms and Values *)
(** The first interesting thing about the [step] relation in this
language is that the strong progress theorem from the Smallstep
chapter fails! That is, there are terms that are normal
forms (they can't take a step) but not values (because we have not
included them in our definition of possible "results of
evaluation"). Such terms are _stuck_. *)
Notation step_normal_form := (normal_form step).
Definition stuck (t:tm) : Prop :=
step_normal_form t /\ ~ value t.
Hint Unfold stuck.
(** **** Exercise: 2 stars (some_term_is_stuck) *)
Example some_term_is_stuck :
exists t, stuck t.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** However, although values and normal forms are not the same in this
language, the former set is included in the latter. This is
important because it shows we did not accidentally define things
so that some value could still take a step. *)
(** **** Exercise: 3 stars, advanced (value_is_nf) *)
(** Hint: You will reach a point in this proof where you need to
use an induction to reason about a term that is known to be a
numeric value. This induction can be performed either over the
term itself or over the evidence that it is a numeric value. The
proof goes through in either case, but you will find that one way
is quite a bit shorter than the other. For the sake of the
exercise, try to complete the proof both ways. *)
Lemma value_is_nf : forall t,
value t -> step_normal_form t.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional (step_deterministic) *)
(** Using [value_is_nf], we can show that the [step] relation is
also deterministic... *)
Theorem step_deterministic:
deterministic step.
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################################### *)
(** ** Typing *)
(** The next critical observation about this language is that,
although there are stuck terms, they are all "nonsensical", mixing
booleans and numbers in a way that we don't even _want_ to have a
meaning. We can easily exclude such ill-typed terms by defining a
_typing relation_ that relates terms to the types (either numeric
or boolean) of their final results. *)
Inductive ty : Type :=
| TBool : ty
| TNat : ty.
(** In informal notation, the typing relation is often written
[|- t \in T], pronounced "[t] has type [T]." The [|-] symbol is
called a "turnstile". (Below, we're going to see richer typing
relations where an additional "context" argument is written to the
left of the turnstile. Here, the context is always empty.) *)
(**
---------------- (T_True)
|- true \in Bool
----------------- (T_False)
|- false \in Bool
|- t1 \in Bool |- t2 \in T |- t3 \in T
-------------------------------------------- (T_If)
|- if t1 then t2 else t3 \in T
------------ (T_Zero)
|- 0 \in Nat
|- t1 \in Nat
------------------ (T_Succ)
|- succ t1 \in Nat
|- t1 \in Nat
------------------ (T_Pred)
|- pred t1 \in Nat
|- t1 \in Nat
--------------------- (T_IsZero)
|- iszero t1 \in Bool
*)
Reserved Notation "'|-' t '\in' T" (at level 40).
Inductive has_type : tm -> ty -> Prop :=
| T_True :
|- ttrue \in TBool
| T_False :
|- tfalse \in TBool
| T_If : forall t1 t2 t3 T,
|- t1 \in TBool ->
|- t2 \in T ->
|- t3 \in T ->
|- tif t1 t2 t3 \in T
| T_Zero :
|- tzero \in TNat
| T_Succ : forall t1,
|- t1 \in TNat ->
|- tsucc t1 \in TNat
| T_Pred : forall t1,
|- t1 \in TNat ->
|- tpred t1 \in TNat
| T_Iszero : forall t1,
|- t1 \in TNat ->
|- tiszero t1 \in TBool
where "'|-' t '\in' T" := (has_type t T).
Tactic Notation "has_type_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "T_True" | Case_aux c "T_False" | Case_aux c "T_If"
| Case_aux c "T_Zero" | Case_aux c "T_Succ" | Case_aux c "T_Pred"
| Case_aux c "T_Iszero" ].
Hint Constructors has_type.
(* ###################################################################### *)
(** *** Examples *)
(** It's important to realize that the typing relation is a
_conservative_ (or _static_) approximation: it does not calculate
the type of the normal form of a term. *)
Example has_type_1 :
|- tif tfalse tzero (tsucc tzero) \in TNat.
Proof.
apply T_If.
apply T_False.
apply T_Zero.
apply T_Succ.
apply T_Zero.
Qed.
(** (Since we've included all the constructors of the typing relation
in the hint database, the [auto] tactic can actually find this
proof automatically.) *)
Example has_type_not :
~ (|- tif tfalse tzero ttrue \in TBool).
Proof.
intros Contra. solve by inversion 2. Qed.
(** **** Exercise: 1 star, optional (succ_hastype_nat__hastype_nat) *)
Example succ_hastype_nat__hastype_nat : forall t,
|- tsucc t \in TNat ->
|- t \in TNat.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################################### *)
(** ** Progress *)
(** The typing relation enjoys two critical properties. The first is
that well-typed normal forms are values (i.e., not stuck). *)
Theorem progress : forall t T,
|- t \in T ->
value t \/ exists t', t ==> t'.
(** **** Exercise: 3 stars (finish_progress) *)
(** Complete the formal proof of the [progress] property. (Make sure
you understand the informal proof fragment in the following
exercise before starting -- this will save you a lot of time.) *)
Proof with auto.
intros t T HT.
has_type_cases (induction HT) Case...
(* The cases that were obviously values, like T_True and
T_False, were eliminated immediately by auto *)
Case "T_If".
right. inversion IHHT1; clear IHHT1.
SCase "t1 is a value". inversion H; clear H.
SSCase "t1 is a bvalue". inversion H0; clear H0.
SSSCase "t1 is ttrue".
exists t2...
SSSCase "t1 is tfalse".
exists t3...
SSCase "t1 is an nvalue".
solve by inversion 2. (* on H and HT1 *)
SCase "t1 can take a step".
inversion H as [t1' H1].
exists (tif t1' t2 t3)...
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced (finish_progress_informal) *)
(** Complete the corresponding informal proof: *)
(** _Theorem_: If [|- t \in T], then either [t] is a value or else
[t ==> t'] for some [t']. *)
(** _Proof_: By induction on a derivation of [|- t \in T].
- If the last rule in the derivation is [T_If], then [t = if t1
then t2 else t3], with [|- t1 \in Bool], [|- t2 \in T] and [|- t3
\in T]. By the IH, either [t1] is a value or else [t1] can step
to some [t1'].
- If [t1] is a value, then it is either an [nvalue] or a
[bvalue]. But it cannot be an [nvalue], because we know
[|- t1 \in Bool] and there are no rules assigning type
[Bool] to any term that could be an [nvalue]. So [t1]
is a [bvalue] -- i.e., it is either [true] or [false].
If [t1 = true], then [t] steps to [t2] by [ST_IfTrue],
while if [t1 = false], then [t] steps to [t3] by
[ST_IfFalse]. Either way, [t] can step, which is what
we wanted to show.
- If [t1] itself can take a step, then, by [ST_If], so can
[t].
(* FILL IN HERE *)
[]
*)
(** This is more interesting than the strong progress theorem that we
saw in the Smallstep chapter, where _all_ normal forms were
values. Here, a term can be stuck, but only if it is ill
typed. *)
(** **** Exercise: 1 star (step_review) *)
(** Quick review. Answer _true_ or _false_. In this language...
- Every well-typed normal form is a value.
- Every value is a normal form.
- The single-step evaluation relation is
a partial function (i.e., it is deterministic).
- The single-step evaluation relation is a _total_ function.
*)
(** [] *)
(* ###################################################################### *)
(** ** Type Preservation *)
(** The second critical property of typing is that, when a well-typed
term takes a step, the result is also a well-typed term.
This theorem is often called the _subject reduction_ property,
because it tells us what happens when the "subject" of the typing
relation is reduced. This terminology comes from thinking of
typing statements as sentences, where the term is the subject and
the type is the predicate. *)
Theorem preservation : forall t t' T,
|- t \in T ->
t ==> t' ->
|- t' \in T.
(** **** Exercise: 2 stars (finish_preservation) *)
(** Complete the formal proof of the [preservation] property. (Again,
make sure you understand the informal proof fragment in the
following exercise first.) *)
Proof with auto.
intros t t' T HT HE.
generalize dependent t'.
has_type_cases (induction HT) Case;
(* every case needs to introduce a couple of things *)
intros t' HE;
(* and we can deal with several impossible
cases all at once *)
try (solve by inversion).
Case "T_If". inversion HE; subst.
SCase "ST_IFTrue". assumption.
SCase "ST_IfFalse". assumption.
SCase "ST_If". apply T_If; try assumption.
apply IHHT1; assumption.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced (finish_preservation_informal) *)
(** Complete the following proof: *)
(** _Theorem_: If [|- t \in T] and [t ==> t'], then [|- t' \in T]. *)
(** _Proof_: By induction on a derivation of [|- t \in T].
- If the last rule in the derivation is [T_If], then [t = if t1
then t2 else t3], with [|- t1 \in Bool], [|- t2 \in T] and [|- t3
\in T].
Inspecting the rules for the small-step reduction relation and
remembering that [t] has the form [if ...], we see that the
only ones that could have been used to prove [t ==> t'] are
[ST_IfTrue], [ST_IfFalse], or [ST_If].
- If the last rule was [ST_IfTrue], then [t' = t2]. But we
know that [|- t2 \in T], so we are done.
- If the last rule was [ST_IfFalse], then [t' = t3]. But we
know that [|- t3 \in T], so we are done.
- If the last rule was [ST_If], then [t' = if t1' then t2
else t3], where [t1 ==> t1']. We know [|- t1 \in Bool] so,
by the IH, [|- t1' \in Bool]. The [T_If] rule then gives us
[|- if t1' then t2 else t3 \in T], as required.
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 3 stars (preservation_alternate_proof) *)
(** Now prove the same property again by induction on the
_evaluation_ derivation instead of on the typing derivation.
Begin by carefully reading and thinking about the first few
lines of the above proof to make sure you understand what
each one is doing. The set-up for this proof is similar, but
not exactly the same. *)
Theorem preservation' : forall t t' T,
|- t \in T ->
t ==> t' ->
|- t' \in T.
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################################### *)
(** * Aside: the [normalize] Tactic *)
(** When experimenting with definitions of programming languages in
Coq, we often want to see what a particular concrete term steps
to -- i.e., we want to find proofs for goals of the form [t ==>*
t'], where [t] is a completely concrete term and [t'] is unknown.
These proofs are simple but repetitive to do by hand. Consider for
example reducing an arithmetic expression using the small-step
relation [astep]. *)
Definition amultistep st := multi (astep st).
Notation " t '/' st '==>a*' t' " := (amultistep st t t')
(at level 40, st at level 39).
Example astep_example1 :
(APlus (ANum 3) (AMult (ANum 3) (ANum 4))) / empty_state
==>a* (ANum 15).
Proof.
apply multi_step with (APlus (ANum 3) (ANum 12)).
apply AS_Plus2.
apply av_num.
apply AS_Mult.
apply multi_step with (ANum 15).
apply AS_Plus.
apply multi_refl.
Qed.
(** We repeatedly apply [multi_step] until we get to a normal
form. The proofs that the intermediate steps are possible are
simple enough that [auto], with appropriate hints, can solve
them. *)
Hint Constructors astep aval.
Example astep_example1' :
(APlus (ANum 3) (AMult (ANum 3) (ANum 4))) / empty_state
==>a* (ANum 15).
Proof.
eapply multi_step. auto. simpl.
eapply multi_step. auto. simpl.
apply multi_refl.
Qed.
(** The following custom [Tactic Notation] definition captures this
pattern. In addition, before each [multi_step] we print out the
current goal, so that the user can follow how the term is being
evaluated. *)
Tactic Notation "print_goal" := match goal with |- ?x => idtac x end.
Tactic Notation "normalize" :=
repeat (print_goal; eapply multi_step ;
[ (eauto 10; fail) | (instantiate; simpl)]);
apply multi_refl.
Example astep_example1'' :
(APlus (ANum 3) (AMult (ANum 3) (ANum 4))) / empty_state
==>a* (ANum 15).
Proof.
normalize.
(* At this point in the proof script, the Coq response shows
a trace of how the expression evaluated.
(APlus (ANum 3) (AMult (ANum 3) (ANum 4)) / empty_state ==>a* ANum 15)
(multi (astep empty_state) (APlus (ANum 3) (ANum 12)) (ANum 15))
(multi (astep empty_state) (ANum 15) (ANum 15))
*)
Qed.
(** The [normalize] tactic also provides a simple way to calculate
what the normal form of a term is, by proving a goal with an
existential variable in it. *)
Example astep_example1''' : exists e',
(APlus (ANum 3) (AMult (ANum 3) (ANum 4))) / empty_state
==>a* e'.
Proof.
eapply ex_intro. normalize.
(* This time, the trace will be:
(APlus (ANum 3) (AMult (ANum 3) (ANum 4)) / empty_state ==>a* ??)
(multi (astep empty_state) (APlus (ANum 3) (ANum 12)) ??)
(multi (astep empty_state) (ANum 15) ??)
where ?? is the variable ``guessed'' by eapply.
*)
Qed.
(** **** Exercise: 1 star (normalize_ex) *)
Theorem normalize_ex : exists e',
(AMult (ANum 3) (AMult (ANum 2) (ANum 1))) / empty_state
==>a* e'.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star, optional (normalize_ex') *)
(** For comparison, prove it using [apply] instead of [eapply]. *)
Theorem normalize_ex' : exists e',
(AMult (ANum 3) (AMult (ANum 2) (ANum 1))) / empty_state
==>a* e'.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################################### *)
(** ** Type Soundness *)
(** Putting progress and preservation together, we can see that a
well-typed term can _never_ reach a stuck state. *)
Definition multistep := (multi step).
Notation "t1 '==>*' t2" := (multistep t1 t2) (at level 40).
Corollary soundness : forall t t' T,
|- t \in T ->
t ==>* t' ->
~(stuck t').
Proof.
intros t t' T HT P. induction P; intros [R S].
destruct (progress x T HT); auto.
apply IHP. apply (preservation x y T HT H).
unfold stuck. split; auto. Qed.
(* ###################################################################### *)
(** ** Additional Exercises *)
(** **** Exercise: 2 stars (subject_expansion) *)
(** Having seen the subject reduction property, it is reasonable to
wonder whether the opposity property -- subject _expansion_ --
also holds. That is, is it always the case that, if [t ==> t']
and [|- t' \in T], then [|- t \in T]? If so, prove it. If
not, give a counter-example. (You do not need to prove your
counter-example in Coq, but feel free to do so if you like.)
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 2 stars (variation1) *)
(** Suppose, that we add this new rule to the typing relation:
| T_SuccBool : forall t,
|- t \in TBool ->
|- tsucc t \in TBool
Which of the following properties remain true in the presence of
this rule? For each one, write either "remains true" or
else "becomes false." If a property becomes false, give a
counterexample.
- Determinism of [step]
- Progress
- Preservation
[]
*)
(** **** Exercise: 2 stars (variation2) *)
(** Suppose, instead, that we add this new rule to the [step] relation:
| ST_Funny1 : forall t2 t3,
(tif ttrue t2 t3) ==> t3
Which of the above properties become false in the presence of
this rule? For each one that does, give a counter-example.
[]
*)
(** **** Exercise: 2 stars, optional (variation3) *)
(** Suppose instead that we add this rule:
| ST_Funny2 : forall t1 t2 t2' t3,
t2 ==> t2' ->
(tif t1 t2 t3) ==> (tif t1 t2' t3)
Which of the above properties become false in the presence of
this rule? For each one that does, give a counter-example.
[]
*)
(** **** Exercise: 2 stars, optional (variation4) *)
(** Suppose instead that we add this rule:
| ST_Funny3 :
(tpred tfalse) ==> (tpred (tpred tfalse))
Which of the above properties become false in the presence of
this rule? For each one that does, give a counter-example.
[]
*)
(** **** Exercise: 2 stars, optional (variation5) *)
(** Suppose instead that we add this rule:
| T_Funny4 :
|- tzero \in TBool
]]
Which of the above properties become false in the presence of
this rule? For each one that does, give a counter-example.
[]
*)
(** **** Exercise: 2 stars, optional (variation6) *)
(** Suppose instead that we add this rule:
| T_Funny5 :
|- tpred tzero \in TBool
]]
Which of the above properties become false in the presence of
this rule? For each one that does, give a counter-example.
[]
*)
(** **** Exercise: 3 stars, optional (more_variations) *)
(** Make up some exercises of your own along the same lines as
the ones above. Try to find ways of selectively breaking
properties -- i.e., ways of changing the definitions that
break just one of the properties and leave the others alone.
[]
*)
(** **** Exercise: 1 star (remove_predzero) *)
(** The evaluation rule [E_PredZero] is a bit counter-intuitive: we
might feel that it makes more sense for the predecessor of zero to
be undefined, rather than being defined to be zero. Can we
achieve this simply by removing the rule from the definition of
[step]? Would doing so create any problems elsewhere?
(* FILL IN HERE *)
[] *)
(** **** Exercise: 4 stars, advanced (prog_pres_bigstep) *)
(** Suppose our evaluation relation is defined in the big-step style.
What are the appropriate analogs of the progress and preservation
properties?
(* FILL IN HERE *)
[]
*)
(* $Date: 2013-07-17 16:19:11 -0400 (Wed, 17 Jul 2013) $ *)
|
/*
* Synchronous read 1r1w content addressable memory module.
* Each entry has a tag and a data associated with it, and can be
* independently cleared and set
*
* This module is similar to bsg_cam_1r1w_sync, except it allows for an
* external replacement scheme
*/
`include "bsg_defines.v"
module bsg_cam_1r1w_sync_unmanaged
#(parameter `BSG_INV_PARAM(els_p)
, parameter `BSG_INV_PARAM(tag_width_p)
, parameter `BSG_INV_PARAM(data_width_p)
, parameter safe_els_lp = `BSG_MAX(els_p,1)
)
(input clk_i
, input reset_i
// Synchronous write/invalidate of a tag
// one or zero-hot
, input [safe_els_lp-1:0] w_v_i
, input w_set_not_clear_i
// Tag/data to set on write
, input [tag_width_p-1:0] w_tag_i
, input [data_width_p-1:0] w_data_i
// Metadata useful for an external replacement policy
// Whether there's an empty entry in the tag array
, output [safe_els_lp-1:0] w_empty_o
// Asynchronous read of a tag, if exists
, input r_v_i
, input [tag_width_p-1:0] r_tag_i
, output logic [data_width_p-1:0] r_data_o
, output logic r_v_o
);
// Latch the read request for a synchronous read
logic [tag_width_p-1:0] r_tag_r;
logic r_v_r;
bsg_dff
#(.width_p(1+tag_width_p))
r_tag_reg
(.clk_i(clk_i)
,.data_i({r_v_i, r_tag_i})
,.data_o({r_v_r, r_tag_r})
);
// Read from asynchronous unmanaged CAM
bsg_cam_1r1w_unmanaged
#(.els_p(safe_els_lp)
,.tag_width_p(tag_width_p)
,.data_width_p(data_width_p)
)
cam
(.clk_i(clk_i)
,.reset_i(reset_i)
,.w_v_i(w_v_i)
,.w_set_not_clear_i(w_set_not_clear_i)
,.w_tag_i(w_tag_i)
,.w_data_i(w_data_i)
,.w_empty_o(w_empty_o)
,.r_v_i(r_v_r)
,.r_tag_i(r_tag_r)
,.r_data_o(r_data_o)
,.r_v_o(r_v_o)
);
endmodule
`BSG_ABSTRACT_MODULE(bsg_cam_1r1w_sync_unmanaged)
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module dma_if # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36,
parameter C_M_AXI_DATA_WIDTH = 64
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [2:0] pcie_max_payload_size,
input [2:0] pcie_max_read_req_size,
input pcie_rcb,
output [7:0] hcmd_prp_rd_addr,
input [44:0] hcmd_prp_rd_data,
output hcmd_nlb_wr1_en,
output [6:0] hcmd_nlb_wr1_addr,
output [18:0] hcmd_nlb_wr1_data,
input hcmd_nlb_wr1_rdy_n,
output [6:0] hcmd_nlb_rd_addr,
input [18:0] hcmd_nlb_rd_data,
output dev_rx_cmd_wr_en,
output [29:0] dev_rx_cmd_wr_data,
input dev_rx_cmd_full_n,
output dev_tx_cmd_wr_en,
output [29:0] dev_tx_cmd_wr_data,
input dev_tx_cmd_full_n,
output tx_prp_mrd_req,
output [7:0] tx_prp_mrd_tag,
output [11:2] tx_prp_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_prp_mrd_addr,
input tx_prp_mrd_req_ack,
input [7:0] cpld_prp_fifo_tag,
input [C_PCIE_DATA_WIDTH-1:0] cpld_prp_fifo_wr_data,
input cpld_prp_fifo_wr_en,
input cpld_prp_fifo_tag_last,
output tx_dma_mrd_req,
output [7:0] tx_dma_mrd_tag,
output [11:2] tx_dma_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_dma_mrd_addr,
input tx_dma_mrd_req_ack,
input [7:0] cpld_dma_fifo_tag,
input [C_PCIE_DATA_WIDTH-1:0] cpld_dma_fifo_wr_data,
input cpld_dma_fifo_wr_en,
input cpld_dma_fifo_tag_last,
output tx_dma_mwr_req,
output [7:0] tx_dma_mwr_tag,
output [11:2] tx_dma_mwr_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_dma_mwr_addr,
input tx_dma_mwr_req_ack,
input tx_dma_mwr_data_last,
input pcie_tx_dma_fifo_rd_en,
output [C_PCIE_DATA_WIDTH-1:0] pcie_tx_dma_fifo_rd_data,
output hcmd_cq_wr0_en,
output [34:0] hcmd_cq_wr0_data0,
output [34:0] hcmd_cq_wr0_data1,
input hcmd_cq_wr0_rdy_n,
input cpu_bus_clk,
input cpu_bus_rst_n,
input dma_cmd_wr_en,
input [49:0] dma_cmd_wr_data0,
input [49:0] dma_cmd_wr_data1,
output dma_cmd_wr_rdy_n,
output [7:0] dma_rx_direct_done_cnt,
output [7:0] dma_tx_direct_done_cnt,
output [7:0] dma_rx_done_cnt,
output [7:0] dma_tx_done_cnt,
input dma_bus_clk,
input dma_bus_rst_n,
input pcie_rx_fifo_rd_en,
output [C_M_AXI_DATA_WIDTH-1:0] pcie_rx_fifo_rd_data,
input pcie_rx_fifo_free_en,
input [9:4] pcie_rx_fifo_free_len,
output pcie_rx_fifo_empty_n,
input pcie_tx_fifo_alloc_en,
input [9:4] pcie_tx_fifo_alloc_len,
input pcie_tx_fifo_wr_en,
input [C_M_AXI_DATA_WIDTH-1:0] pcie_tx_fifo_wr_data,
output pcie_tx_fifo_full_n,
input dma_rx_done_wr_en,
input [20:0] dma_rx_done_wr_data,
output dma_rx_done_wr_rdy_n
);
wire w_pcie_rx_cmd_wr_en;
wire [33:0] w_pcie_rx_cmd_wr_data;
wire w_pcie_rx_cmd_full_n;
wire w_pcie_tx_cmd_wr_en;
wire [33:0] w_pcie_tx_cmd_wr_data;
wire w_pcie_tx_cmd_full_n;
wire w_dma_tx_done_wr_en;
wire [20:0] w_dma_tx_done_wr_data;
wire w_dma_tx_done_wr_rdy_n;
dma_cmd
dma_cmd_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_rcb (pcie_rcb),
.hcmd_prp_rd_addr (hcmd_prp_rd_addr),
.hcmd_prp_rd_data (hcmd_prp_rd_data),
.hcmd_nlb_wr1_en (hcmd_nlb_wr1_en),
.hcmd_nlb_wr1_addr (hcmd_nlb_wr1_addr),
.hcmd_nlb_wr1_data (hcmd_nlb_wr1_data),
.hcmd_nlb_wr1_rdy_n (hcmd_nlb_wr1_rdy_n),
.hcmd_nlb_rd_addr (hcmd_nlb_rd_addr),
.hcmd_nlb_rd_data (hcmd_nlb_rd_data),
.dev_rx_cmd_wr_en (dev_rx_cmd_wr_en),
.dev_rx_cmd_wr_data (dev_rx_cmd_wr_data),
.dev_rx_cmd_full_n (dev_rx_cmd_full_n),
.dev_tx_cmd_wr_en (dev_tx_cmd_wr_en),
.dev_tx_cmd_wr_data (dev_tx_cmd_wr_data),
.dev_tx_cmd_full_n (dev_tx_cmd_full_n),
.tx_prp_mrd_req (tx_prp_mrd_req),
.tx_prp_mrd_tag (tx_prp_mrd_tag),
.tx_prp_mrd_len (tx_prp_mrd_len),
.tx_prp_mrd_addr (tx_prp_mrd_addr),
.tx_prp_mrd_req_ack (tx_prp_mrd_req_ack),
.cpld_prp_fifo_tag (cpld_prp_fifo_tag),
.cpld_prp_fifo_wr_data (cpld_prp_fifo_wr_data),
.cpld_prp_fifo_wr_en (cpld_prp_fifo_wr_en),
.cpld_prp_fifo_tag_last (cpld_prp_fifo_tag_last),
.pcie_rx_cmd_wr_en (w_pcie_rx_cmd_wr_en),
.pcie_rx_cmd_wr_data (w_pcie_rx_cmd_wr_data),
.pcie_rx_cmd_full_n (w_pcie_rx_cmd_full_n),
.pcie_tx_cmd_wr_en (w_pcie_tx_cmd_wr_en),
.pcie_tx_cmd_wr_data (w_pcie_tx_cmd_wr_data),
.pcie_tx_cmd_full_n (w_pcie_tx_cmd_full_n),
.dma_tx_done_wr_en (w_dma_tx_done_wr_en),
.dma_tx_done_wr_data (w_dma_tx_done_wr_data),
.dma_tx_done_wr_rdy_n (w_dma_tx_done_wr_rdy_n),
.hcmd_cq_wr0_en (hcmd_cq_wr0_en),
.hcmd_cq_wr0_data0 (hcmd_cq_wr0_data0),
.hcmd_cq_wr0_data1 (hcmd_cq_wr0_data1),
.hcmd_cq_wr0_rdy_n (hcmd_cq_wr0_rdy_n),
.cpu_bus_clk (cpu_bus_clk),
.cpu_bus_rst_n (cpu_bus_rst_n),
.dma_cmd_wr_en (dma_cmd_wr_en),
.dma_cmd_wr_data0 (dma_cmd_wr_data0),
.dma_cmd_wr_data1 (dma_cmd_wr_data1),
.dma_cmd_wr_rdy_n (dma_cmd_wr_rdy_n),
.dma_rx_direct_done_cnt (dma_rx_direct_done_cnt),
.dma_tx_direct_done_cnt (dma_tx_direct_done_cnt),
.dma_rx_done_cnt (dma_rx_done_cnt),
.dma_tx_done_cnt (dma_tx_done_cnt),
.dma_bus_clk (dma_bus_clk),
.dma_bus_rst_n (dma_bus_rst_n),
.dma_rx_done_wr_en (dma_rx_done_wr_en),
.dma_rx_done_wr_data (dma_rx_done_wr_data),
.dma_rx_done_wr_rdy_n (dma_rx_done_wr_rdy_n)
);
pcie_rx_dma
pcie_rx_dma_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_max_read_req_size (pcie_max_read_req_size),
.pcie_rx_cmd_wr_en (w_pcie_rx_cmd_wr_en),
.pcie_rx_cmd_wr_data (w_pcie_rx_cmd_wr_data),
.pcie_rx_cmd_full_n (w_pcie_rx_cmd_full_n),
.tx_dma_mrd_req (tx_dma_mrd_req),
.tx_dma_mrd_tag (tx_dma_mrd_tag),
.tx_dma_mrd_len (tx_dma_mrd_len),
.tx_dma_mrd_addr (tx_dma_mrd_addr),
.tx_dma_mrd_req_ack (tx_dma_mrd_req_ack),
.cpld_dma_fifo_tag (cpld_dma_fifo_tag),
.cpld_dma_fifo_wr_data (cpld_dma_fifo_wr_data),
.cpld_dma_fifo_wr_en (cpld_dma_fifo_wr_en),
.cpld_dma_fifo_tag_last (cpld_dma_fifo_tag_last),
.dma_bus_clk (dma_bus_clk),
.dma_bus_rst_n (dma_bus_rst_n),
.pcie_rx_fifo_rd_en (pcie_rx_fifo_rd_en),
.pcie_rx_fifo_rd_data (pcie_rx_fifo_rd_data),
.pcie_rx_fifo_free_en (pcie_rx_fifo_free_en),
.pcie_rx_fifo_free_len (pcie_rx_fifo_free_len),
.pcie_rx_fifo_empty_n (pcie_rx_fifo_empty_n)
);
pcie_tx_dma
pcie_tx_dma_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_max_payload_size (pcie_max_payload_size),
.pcie_tx_cmd_wr_en (w_pcie_tx_cmd_wr_en),
.pcie_tx_cmd_wr_data (w_pcie_tx_cmd_wr_data),
.pcie_tx_cmd_full_n (w_pcie_tx_cmd_full_n),
.tx_dma_mwr_req (tx_dma_mwr_req),
.tx_dma_mwr_tag (tx_dma_mwr_tag),
.tx_dma_mwr_len (tx_dma_mwr_len),
.tx_dma_mwr_addr (tx_dma_mwr_addr),
.tx_dma_mwr_req_ack (tx_dma_mwr_req_ack),
.tx_dma_mwr_data_last (tx_dma_mwr_data_last),
.pcie_tx_dma_fifo_rd_en (pcie_tx_dma_fifo_rd_en),
.pcie_tx_dma_fifo_rd_data (pcie_tx_dma_fifo_rd_data),
.dma_tx_done_wr_en (w_dma_tx_done_wr_en),
.dma_tx_done_wr_data (w_dma_tx_done_wr_data),
.dma_tx_done_wr_rdy_n (w_dma_tx_done_wr_rdy_n),
.dma_bus_clk (dma_bus_clk),
.dma_bus_rst_n (dma_bus_rst_n),
.pcie_tx_fifo_alloc_en (pcie_tx_fifo_alloc_en),
.pcie_tx_fifo_alloc_len (pcie_tx_fifo_alloc_len),
.pcie_tx_fifo_wr_en (pcie_tx_fifo_wr_en),
.pcie_tx_fifo_wr_data (pcie_tx_fifo_wr_data),
.pcie_tx_fifo_full_n (pcie_tx_fifo_full_n)
);
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD3_1_V
`define SKY130_FD_SC_LS__CLKDLYINV3SD3_1_V
/**
* clkdlyinv3sd3: Clock Delay Inverter 3-stage 0.50um length inner
* stage gate.
*
* Verilog wrapper for clkdlyinv3sd3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__clkdlyinv3sd3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__clkdlyinv3sd3_1 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__clkdlyinv3sd3 base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__clkdlyinv3sd3_1 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__clkdlyinv3sd3 base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV3SD3_1_V
|
(** * UseAuto: Theory and Practice of Automation in Coq Proofs *)
(* $Date: 2013-07-17 16:19:11 -0400 (Wed, 17 Jul 2013) $ *)
(* Chapter maintained by Arthur Chargueraud *)
(** In a machine-checked proof, every single detail has to be
justified. This can result in huge proof scripts. Fortunately,
Coq comes with a proof-search mechanism and with several decision
procedures that enable the system to automatically synthesize
simple pieces of proof. Automation is very powerful when set up
appropriately. The purpose of this chapter is to explain the
basics of working of automation.
The chapter is organized in two parts. The first part focuses on a
general mechanism called "proof search." In short, proof search
consists in naively trying to apply lemmas and assumptions in all
possible ways. The second part describes "decision procedures",
which are tactics that are very good at solving proof obligations
that fall in some particular fragment of the logic of Coq.
Many of the examples used in this chapter consist of small lemmas
that have been made up to illustrate particular aspects of automation.
These examples are completely independent from the rest of the Software
Foundations course. This chapter also contains some bigger examples
which are used to explain how to use automation in realistic proofs.
These examples are taken from other chapters of the course (mostly
from STLC), and the proofs that we present make use of the tactics
from the library [LibTactics.v], which is presented in the chapter
[UseTactics]. *)
Require Import LibTactics.
(* ####################################################### *)
(** * Basic Features of Proof Search *)
(** The idea of proof search is to replace a sequence of tactics
applying lemmas and assumptions with a call to a single tactic,
for example [auto]. This form of proof automation saves a lot of
effort. It typically leads to much shorter proof scripts, and to
scripts that are typically more robust to change. If one makes a
little change to a definition, a proof that exploits automation
probably won't need to be modified at all. Of course, using too
much automation is a bad idea. When a proof script no longer
records the main arguments of a proof, it becomes difficult to fix
it when it gets broken after a change in a definition. Overall, a
reasonable use of automation is generally a big win, as it saves a
lot of time both in building proof scripts and in subsequently
maintaining those proof scripts. *)
(* ####################################################### *)
(** ** Strength of Proof Search *)
(** We are going to study four proof-search tactics: [auto], [eauto],
[iauto] and [jauto]. The tactics [auto] and [eauto] are builtin
in Coq. The tactic [iauto] is a shorthand for the builtin tactic
[try solve [intuition eauto]]. The tactic [jauto] is defined in
the library [LibTactics], and simply performs some preprocessing
of the goal before calling [eauto]. The goal of this chapter is
to explain the general principles of proof search and to give
rule of thumbs for guessing which of the four tactics mentioned
above is best suited for solving a given goal.
Proof search is a compromise between efficiency and
expressiveness, that is, a tradeoff between how complex goals the
tactic can solve and how much time the tactic requires for
terminating. The tactic [auto] builds proofs only by using the
basic tactics [reflexivity], [assumption], and [apply]. The tactic
[eauto] can also exploit [eapply]. The tactic [jauto] extends
[eauto] by being able to open conjunctions and existentials that
occur in the context. The tactic [iauto] is able to deal with
conjunctions, disjunctions, and negation in a quite clever way;
however it is not able to open existentials from the context.
Also, [iauto] usually becomes very slow when the goal involves
several disjunctions.
Note that proof search tactics never perform any rewriting
step (tactics [rewrite], [subst]), nor any case analysis on an
arbitrary data structure or predicate (tactics [destruct] and
[inversion]), nor any proof by induction (tactic [induction]). So,
proof search is really intended to automate the final steps from
the various branches of a proof. It is not able to discover the
overall structure of a proof. *)
(* ####################################################### *)
(** ** Basics *)
(** The tactic [auto] is able to solve a goal that can be proved
using a sequence of [intros], [apply], [assumption], and [reflexivity].
Two examples follow. The first one shows the ability for
[auto] to call [reflexivity] at any time. In fact, calling
[reflexivity] is always the first thing that [auto] tries to do. *)
Lemma solving_by_reflexivity :
2 + 3 = 5.
Proof. auto. Qed.
(** The second example illustrates a proof where a sequence of
two calls to [apply] are needed. The goal is to prove that
if [Q n] implies [P n] for any [n] and if [Q n] holds for any [n],
then [P 2] holds. *)
Lemma solving_by_apply : forall (P Q : nat->Prop),
(forall n, Q n -> P n) ->
(forall n, Q n) ->
P 2.
Proof. auto. Qed.
(** We can ask [auto] to tell us what proof it came up with,
by invoking [info_auto] in place of [auto]. *)
Lemma solving_by_apply' : forall (P Q : nat->Prop),
(forall n, Q n -> P n) ->
(forall n, Q n) ->
P 2.
Proof. info_auto. Qed.
(* The output is: [intro P; intro Q; intro H;] *)
(* followed with [intro H0; simple apply H; simple apply H0]. *)
(* i.e., the sequence [intros P Q H H0; apply H; apply H0]. *)
(** The tactic [auto] can invoke [apply] but not [eapply]. So, [auto]
cannot exploit lemmas whose instantiation cannot be directly
deduced from the proof goal. To exploit such lemmas, one needs to
invoke the tactic [eauto], which is able to call [eapply].
In the following example, the first hypothesis asserts that [P n]
is true when [Q m] is true for some [m], and the goal is to prove
that [Q 1] implies [P 2]. This implication follows direction from
the hypothesis by instantiating [m] as the value [1]. The
following proof script shows that [eauto] successfully solves the
goal, whereas [auto] is not able to do so. *)
Lemma solving_by_eapply : forall (P Q : nat->Prop),
(forall n m, Q m -> P n) ->
Q 1 -> P 2.
Proof. auto. eauto. Qed.
(** Remark: Again, we can use [info_eauto] to see what proof [eauto]
comes up with. *)
(* ####################################################### *)
(** ** Conjunctions *)
(** So far, we've seen that [eauto] is stronger than [auto] in the
sense that it can deal with [eapply]. In the same way, we are going
to see how [jauto] and [iauto] are stronger than [auto] and [eauto]
in the sense that they provide better support for conjunctions. *)
(** The tactics [auto] and [eauto] can prove a goal of the form
[F /\ F'], where [F] and [F'] are two propositions, as soon as
both [F] and [F'] can be proved in the current context.
An example follows. *)
Lemma solving_conj_goal : forall (P : nat->Prop) (F : Prop),
(forall n, P n) -> F -> F /\ P 2.
Proof. auto. Qed.
(** However, when an assumption is a conjunction, [auto] and [eauto]
are not able to exploit this conjunction. It can be quite
surprising at first that [eauto] can prove very complex goals but
that it fails to prove that [F /\ F'] implies [F]. The tactics
[iauto] and [jauto] are able to decompose conjunctions from the context.
Here is an example. *)
Lemma solving_conj_hyp : forall (F F' : Prop),
F /\ F' -> F.
Proof. auto. eauto. jauto. (* or [iauto] *) Qed.
(** The tactic [jauto] is implemented by first calling a
pre-processing tactic called [jauto_set], and then calling
[eauto]. So, to understand how [jauto] works, one can directly
call the tactic [jauto_set]. *)
Lemma solving_conj_hyp' : forall (F F' : Prop),
F /\ F' -> F.
Proof. intros. jauto_set. eauto. Qed.
(** Next is a more involved goal that can be solved by [iauto] and
[jauto]. *)
Lemma solving_conj_more : forall (P Q R : nat->Prop) (F : Prop),
(F /\ (forall n m, (Q m /\ R n) -> P n)) ->
(F -> R 2) ->
Q 1 ->
P 2 /\ F.
Proof. jauto. (* or [iauto] *) Qed.
(** The strategy of [iauto] and [jauto] is to run a global analysis of
the top-level conjunctions, and then call [eauto]. For this
reason, those tactics are not good at dealing with conjunctions
that occur as the conclusion of some universally quantified
hypothesis. The following example illustrates a general weakness
of Coq proof search mechanisms. *)
Lemma solving_conj_hyp_forall : forall (P Q : nat->Prop),
(forall n, P n /\ Q n) -> P 2.
Proof.
auto. eauto. iauto. jauto.
(* Nothing works, so we have to do some of the work by hand *)
intros. destruct (H 2). auto.
Qed.
(** This situation is slightly disappointing, since automation is
able to prove the following goal, which is very similar. The
only difference is that the universal quantification has been
distributed over the conjunction. *)
Lemma solved_by_jauto : forall (P Q : nat->Prop) (F : Prop),
(forall n, P n) /\ (forall n, Q n) -> P 2.
Proof. jauto. (* or [iauto] *) Qed.
(* ####################################################### *)
(** ** Disjunctions *)
(** The tactics [auto] and [eauto] can handle disjunctions that
occur in the goal. *)
Lemma solving_disj_goal : forall (F F' : Prop),
F -> F \/ F'.
Proof. auto. Qed.
(** However, only [iauto] is able to automate reasoning on the
disjunctions that appear in the context. For example, [iauto] can
prove that [F \/ F'] entails [F' \/ F]. *)
Lemma solving_disj_hyp : forall (F F' : Prop),
F \/ F' -> F' \/ F.
Proof. auto. eauto. jauto. iauto. Qed.
(** More generally, [iauto] can deal with complex combinations of
conjunctions, disjunctions, and negations. Here is an example. *)
Lemma solving_tauto : forall (F1 F2 F3 : Prop),
((~F1 /\ F3) \/ (F2 /\ ~F3)) ->
(F2 -> F1) ->
(F2 -> F3) ->
~F2.
Proof. iauto. Qed.
(** However, the ability of [iauto] to automatically perform a case
analysis on disjunctions comes with a downside: [iauto] may be
very slow. If the context involves several hypotheses with
disjunctions, [iauto] typically generates an exponential number of
subgoals on which [eauto] is called. One major advantage of [jauto]
compared with [iauto] is that it never spends time performing this
kind of case analyses. *)
(* ####################################################### *)
(** ** Existentials *)
(** The tactics [eauto], [iauto], and [jauto] can prove goals whose
conclusion is an existential. For example, if the goal is [exists
x, f x], the tactic [eauto] introduces an existential variable,
say [?25], in place of [x]. The remaining goal is [f ?25], and
[eauto] tries to solve this goal, allowing itself to instantiate
[?25] with any appropriate value. For example, if an assumption [f
2] is available, then the variable [?25] gets instantiated with
[2] and the goal is solved, as shown below. *)
Lemma solving_exists_goal : forall (f : nat->Prop),
f 2 -> exists x, f x.
Proof.
auto. (* observe that [auto] does not deal with existentials, *)
eauto. (* whereas [eauto], [iauto] and [jauto] solve the goal *)
Qed.
(** A major strength of [jauto] over the other proof search tactics is
that it is able to exploit the existentially-quantified
hypotheses, i.e., those of the form [exists x, P]. *)
Lemma solving_exists_hyp : forall (f g : nat->Prop),
(forall x, f x -> g x) ->
(exists a, f a) ->
(exists a, g a).
Proof.
auto. eauto. iauto. (* All of these tactics fail, *)
jauto. (* whereas [jauto] succeeds. *)
(* For the details, run [intros. jauto_set. eauto] *)
Qed.
(* ####################################################### *)
(** ** Negation *)
(** The tactics [auto] and [eauto] suffer from some limitations with
respect to the manipulation of negations, mostly related to the
fact that negation, written [~ P], is defined as [P -> False] but
that the unfolding of this definition is not performed
automatically. Consider the following example. *)
Lemma negation_study_1 : forall (P : nat->Prop),
P 0 -> (forall x, ~ P x) -> False.
Proof.
intros P H0 HX.
eauto. (* It fails to see that [HX] applies *)
unfold not in *. eauto.
Qed.
(** For this reason, the tactics [iauto] and [jauto] systematically
invoke [unfold not in *] as part of their pre-processing. So,
they are able to solve the previous goal right away. *)
Lemma negation_study_2 : forall (P : nat->Prop),
P 0 -> (forall x, ~ P x) -> False.
Proof. jauto. (* or [iauto] *) Qed.
(** We will come back later on to the behavior of proof search with
respect to the unfolding of definitions. *)
(* ####################################################### *)
(** ** Equalities *)
(** Coq's proof-search feature is not good at exploiting equalities.
It can do very basic operations, like exploiting reflexivity
and symmetry, but that's about it. Here is a simple example
that [auto] can solve, by first calling [symmetry] and then
applying the hypothesis. *)
Lemma equality_by_auto : forall (f g : nat->Prop),
(forall x, f x = g x) -> g 2 = f 2.
Proof. auto. Qed.
(** To automate more advanced reasoning on equalities, one should
rather try to use the tactic [congruence], which is presented at
the end of this chapter in the "Decision Procedures" section. *)
(* ####################################################### *)
(** * How Proof Search Works *)
(* ####################################################### *)
(** ** Search Depth *)
(** The tactic [auto] works as follows. It first tries to call
[reflexivity] and [assumption]. If one of these calls solves the
goal, the job is done. Otherwise [auto] tries to apply the most
recently introduced assumption that can be applied to the goal
without producing and error. This application produces
subgoals. There are two possible cases. If the sugboals produced
can be solved by a recursive call to [auto], then the job is done.
Otherwise, if this application produces at least one subgoal that
[auto] cannot solve, then [auto] starts over by trying to apply
the second most recently introduced assumption. It continues in a
similar fashion until it finds a proof or until no assumption
remains to be tried.
It is very important to have a clear idea of the backtracking
process involved in the execution of the [auto] tactic; otherwise
its behavior can be quite puzzling. For example, [auto] is not
able to solve the following triviality. *)
Lemma search_depth_0 :
True /\ True /\ True /\ True /\ True /\ True.
Proof.
auto.
Abort.
(** The reason [auto] fails to solve the goal is because there are
too many conjunctions. If there had been only five of them, [auto]
would have successfully solved the proof, but six is too many.
The tactic [auto] limits the number of lemmas and hypotheses
that can be applied in a proof, so as to ensure that the proof
search eventually terminates. By default, the maximal number
of steps is five. One can specify a different bound, writing
for example [auto 6] to search for a proof involving at most
six steps. For example, [auto 6] would solve the previous lemma.
(Similarly, one can invoke [eauto 6] or [intuition eauto 6].)
The argument [n] of [auto n] is called the "search depth."
The tactic [auto] is simply defined as a shorthand for [auto 5].
The behavior of [auto n] can be summarized as follows. It first
tries to solve the goal using [reflexivity] and [assumption]. If
this fails, it tries to apply a hypothesis (or a lemma that has
been registered in the hint database), and this application
produces a number of sugoals. The tactic [auto (n-1)] is then
called on each of those subgoals. If all the subgoals are solved,
the job is completed, otherwise [auto n] tries to apply a
different hypothesis.
During the process, [auto n] calls [auto (n-1)], which in turn
might call [auto (n-2)], and so on. The tactic [auto 0] only
tries [reflexivity] and [assumption], and does not try to apply
any lemma. Overall, this means that when the maximal number of
steps allowed has been exceeded, the [auto] tactic stops searching
and backtracks to try and investigate other paths. *)
(** The following lemma admits a unique proof that involves exactly
three steps. So, [auto n] proves this goal iff [n] is greater than
three. *)
Lemma search_depth_1 : forall (P : nat->Prop),
P 0 ->
(P 0 -> P 1) ->
(P 1 -> P 2) ->
(P 2).
Proof.
auto 0. (* does not find the proof *)
auto 1. (* does not find the proof *)
auto 2. (* does not find the proof *)
auto 3. (* finds the proof *)
(* more generally, [auto n] solves the goal if [n >= 3] *)
Qed.
(** We can generalize the example by introducing an assumption
asserting that [P k] is derivable from [P (k-1)] for all [k],
and keep the assumption [P 0]. The tactic [auto], which is the
same as [auto 5], is able to derive [P k] for all values of [k]
less than 5. For example, it can prove [P 4]. *)
Lemma search_depth_3 : forall (P : nat->Prop),
(* Hypothesis H1: *) (P 0) ->
(* Hypothesis H2: *) (forall k, P (k-1) -> P k) ->
(* Goal: *) (P 4).
Proof. auto. Qed.
(** However, to prove [P 5], one needs to call at least [auto 6]. *)
Lemma search_depth_4 : forall (P : nat->Prop),
(* Hypothesis H1: *) (P 0) ->
(* Hypothesis H2: *) (forall k, P (k-1) -> P k) ->
(* Goal: *) (P 5).
Proof. auto. auto 6. Qed.
(** Because [auto] looks for proofs at a limited depth, there are
cases where [auto] can prove a goal [F] and can prove a goal
[F'] but cannot prove [F /\ F']. In the following example,
[auto] can prove [P 4] but it is not able to prove [P 4 /\ P 4],
because the splitting of the conjunction consumes one proof step.
To prove the conjunction, one needs to increase the search depth,
using at least [auto 6]. *)
Lemma search_depth_5 : forall (P : nat->Prop),
(* Hypothesis H1: *) (P 0) ->
(* Hypothesis H2: *) (forall k, P (k-1) -> P k) ->
(* Goal: *) (P 4 /\ P 4).
Proof. auto. auto 6. Qed.
(* ####################################################### *)
(** ** Backtracking *)
(** In the previous section, we have considered proofs where
at each step there was a unique assumption that [auto]
could apply. In general, [auto] can have several choices
at every step. The strategy of [auto] consists of trying all
of the possibilities (using a depth-first search exploration).
To illustrate how automation works, we are going to extend the
previous example with an additional assumption asserting that
[P k] is also derivable from [P (k+1)]. Adding this hypothesis
offers a new possibility that [auto] could consider at every step.
There exists a special command that one can use for tracing
all the steps that proof-search considers. To view such a
trace, one should write [debug eauto]. (For some reason, the
command [debug auto] does not exist, so we have to use the
command [debug eauto] instead.) *)
Lemma working_of_auto_1 : forall (P : nat->Prop),
(* Hypothesis H1: *) (P 0) ->
(* Hypothesis H2: *) (forall k, P (k+1) -> P k) ->
(* Hypothesis H3: *) (forall k, P (k-1) -> P k) ->
(* Goal: *) (P 2).
(* Uncomment "debug" in the following line to see the debug trace: *)
Proof. intros P H1 H2 H3. (* debug *) eauto. Qed.
(** The output message produced by [debug eauto] is as follows.
<<
depth=5
depth=4 apply H3
depth=3 apply H3
depth=3 exact H1
>>
The depth indicates the value of [n] with which [eauto n] is
called. The tactics shown in the message indicate that the first
thing that [eauto] has tried to do is to apply [H3]. The effect of
applying [H3] is to replace the goal [P 2] with the goal [P 1].
Then, again, [H3] has been applied, changing the goal [P 1] into
[P 0]. At that point, the goal was exactly the hypothesis [H1].
It seems that [eauto] was quite lucky there, as it never even
tried to use the hypothesis [H2] at any time. The reason is that
[auto] always tries to use the most recently introduced hypothesis
first, and [H3] is a more recent hypothesis than [H2] in the goal.
So, let's permute the hypotheses [H2] and [H3] and see what
happens. *)
Lemma working_of_auto_2 : forall (P : nat->Prop),
(* Hypothesis H1: *) (P 0) ->
(* Hypothesis H3: *) (forall k, P (k-1) -> P k) ->
(* Hypothesis H2: *) (forall k, P (k+1) -> P k) ->
(* Goal: *) (P 2).
Proof. intros P H1 H3 H2. (* debug *) eauto. Qed.
(** This time, the output message suggests that the proof search
investigates many possibilities. Replacing [debug eauto] with
[info_eauto], we observe that the proof that [eauto] comes up
with is actually not the simplest one.
[apply H2; apply H3; apply H3; apply H3; exact H1]
This proof goes through the proof obligation [P 3], even though
it is not any useful. The following tree drawing describes
all the goals that automation has been through.
<<
|5||4||3||2||1||0| -- below, tabulation indicates the depth
[P 2]
-> [P 3]
-> [P 4]
-> [P 5]
-> [P 6]
-> [P 7]
-> [P 5]
-> [P 4]
-> [P 5]
-> [P 3]
--> [P 3]
-> [P 4]
-> [P 5]
-> [P 3]
-> [P 2]
-> [P 3]
-> [P 1]
-> [P 2]
-> [P 3]
-> [P 4]
-> [P 5]
-> [P 3]
-> [P 2]
-> [P 3]
-> [P 1]
-> [P 1]
-> [P 2]
-> [P 3]
-> [P 1]
-> [P 0]
-> !! Done !!
>>
The first few lines read as follows. To prove [P 2], [eauto 5]
has first tried to apply [H2], producing the subgoal [P 3].
To solve it, [eauto 4] has tried again to apply [H2], producing
the goal [P 4]. Similarly, the search goes through [P 5], [P 6]
and [P 7]. When reaching [P 7], the tactic [eauto 0] is called
but as it is not allowed to try and apply any lemma, it fails.
So, we come back to the goal [P 6], and try this time to apply
hypothesis [H3], producing the subgoal [P 5]. Here again,
[eauto 0] fails to solve this goal.
The process goes on and on, until backtracking to [P 3] and trying
to apply [H2] three times in a row, going through [P 2] and [P 1]
and [P 0]. This search tree explains why [eauto] came up with a
proof starting with [apply H2]. *)
(* ####################################################### *)
(** ** Adding Hints *)
(** By default, [auto] (and [eauto]) only tries to apply the
hypotheses that appear in the proof context. There are two
possibilities for telling [auto] to exploit a lemma that have
been proved previously: either adding the lemma as an assumption
just before calling [auto], or adding the lemma as a hint, so
that it can be used by every calls to [auto].
The first possibility is useful to have [auto] exploit a lemma
that only serves at this particular point. To add the lemma as
hypothesis, one can type [generalize mylemma; intros], or simply
[lets: mylemma] (the latter requires [LibTactics.v]).
The second possibility is useful for lemmas that need to be
exploited several times. The syntax for adding a lemma as a hint
is [Hint Resolve mylemma]. For example, the lemma asserting than
any number is less than or equal to itself, [forall x, x <= x],
called [Le.le_refl] in the Coq standard library, can be added as a
hint as follows. *)
Hint Resolve Le.le_refl.
(** A convenient shorthand for adding all the constructors of an
inductive datatype as hints is the command [Hint Constructors
mydatatype].
Warning: some lemmas, such as transitivity results, should
not be added as hints as they would very badly affect the
performance of proof search. The description of this problem
and the presentation of a general work-around for transitivity
lemmas appear further on. *)
(* ####################################################### *)
(** ** Integration of Automation in Tactics *)
(** The library "LibTactics" introduces a convenient feature for
invoking automation after calling a tactic. In short, it suffices
to add the symbol star ([*]) to the name of a tactic. For example,
[apply* H] is equivalent to [apply H; auto_star], where [auto_star]
is a tactic that can be defined as needed. By default, [auto_star]
first tries to solve the goal using [auto], and if this does not
succeed then it tries to call [jauto]. Even though [jauto] is
strictly stronger than [auto], it makes sense to call [auto] first:
when [auto] succeeds it may save a lot of time, and when [auto]
fails to prove the goal, it fails very quickly.
The definition of [auto_star], which determines the meaning of the
star symbol, can be modified whenever needed. Simply write:
Ltac auto_star ::= a_new_definition.
]]
Observe the use of [::=] instead of [:=], which indicates that the
tactic is being rebound to a new definition. So, the default
definition is as follows. *)
Ltac auto_star ::= try solve [ auto | jauto ].
(** Nearly all standard Coq tactics and all the tactics from
"LibTactics" can be called with a star symbol. For example, one
can invoke [subst*], [destruct* H], [inverts* H], [lets* I: H x],
[specializes* H x], and so on... There are two notable exceptions.
The tactic [auto*] is just another name for the tactic
[auto_star]. And the tactic [apply* H] calls [eapply H] (or the
more powerful [applys H] if needed), and then calls [auto_star].
Note that there is no [eapply* H] tactic, use [apply* H]
instead. *)
(** In large developments, it can be convenient to use two degrees of
automation. Typically, one would use a fast tactic, like [auto],
and a slower but more powerful tactic, like [jauto]. To allow for
a smooth coexistence of the two form of automation, [LibTactics.v]
also defines a "tilde" version of tactics, like [apply~ H],
[destruct~ H], [subst~], [auto~] and so on. The meaning of the
tilde symbol is described by the [auto_tilde] tactic, whose
default implementation is [auto]. *)
Ltac auto_tilde ::= auto.
(** In the examples that follow, only [auto_star] is needed. *)
(* ####################################################### *)
(** * Examples of Use of Automation *)
(** Let's see how to use proof search in practice on the main theorems
of the "Software Foundations" course, proving in particular
results such as determinism, preservation and progress. *)
(* ####################################################### *)
(** ** Determinism *)
Module DeterministicImp.
Require Import Imp.
(** Recall the original proof of the determinism lemma for the IMP
language, shown below. *)
Theorem ceval_deterministic: forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2.
generalize dependent st2.
(ceval_cases (induction E1) Case); intros st2 E2; inversion E2; subst.
Case "E_Skip". reflexivity.
Case "E_Ass". reflexivity.
Case "E_Seq".
assert (st' = st'0) as EQ1.
SCase "Proof of assertion". apply IHE1_1; assumption.
subst st'0.
apply IHE1_2. assumption.
Case "E_IfTrue".
SCase "b1 evaluates to true".
apply IHE1. assumption.
SCase "b1 evaluates to false (contradiction)".
rewrite H in H5. inversion H5.
Case "E_IfFalse".
SCase "b1 evaluates to true (contradiction)".
rewrite H in H5. inversion H5.
SCase "b1 evaluates to false".
apply IHE1. assumption.
Case "E_WhileEnd".
SCase "b1 evaluates to true".
reflexivity.
SCase "b1 evaluates to false (contradiction)".
rewrite H in H2. inversion H2.
Case "E_WhileLoop".
SCase "b1 evaluates to true (contradiction)".
rewrite H in H4. inversion H4.
SCase "b1 evaluates to false".
assert (st' = st'0) as EQ1.
SSCase "Proof of assertion". apply IHE1_1; assumption.
subst st'0.
apply IHE1_2. assumption.
Qed.
(** Exercise: rewrite this proof using [auto] whenever possible.
(The solution uses [auto] 9 times.) *)
Theorem ceval_deterministic': forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
(* FILL IN HERE *) admit.
Qed.
(** In fact, using automation is not just a matter of calling [auto]
in place of one or two other tactics. Using automation is about
rethinking the organization of sequences of tactics so as to
minimize the effort involved in writing and maintaining the proof.
This process is eased by the use of the tactics from
[LibTactics.v]. So, before trying to optimize the way automation
is used, let's first rewrite the proof of determinism:
- use [introv H] instead of [intros x H],
- use [gen x] instead of [generalize dependent x],
- use [inverts H] instead of [inversion H; subst],
- use [tryfalse] to handle contradictions, and get rid of
the cases where [beval st b1 = true] and [beval st b1 = false]
both appear in the context,
- stop using [ceval_cases] to label subcases. *)
Theorem ceval_deterministic'': forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
introv E1 E2. gen st2.
induction E1; intros; inverts E2; tryfalse.
auto.
auto.
assert (st' = st'0). auto. subst. auto.
auto.
auto.
auto.
assert (st' = st'0). auto. subst. auto.
Qed.
(** To obtain a nice clean proof script, we have to remove the calls
[assert (st' = st'0)]. Such a tactic invokation is not nice
because it refers to some variables whose name has been
automatically generated. This kind of tactics tend to be very
brittle. The tactic [assert (st' = st'0)] is used to assert the
conclusion that we want to derive from the induction
hypothesis. So, rather than stating this conclusion explicitly, we
are going to ask Coq to instantiate the induction hypothesis,
using automation to figure out how to instantiate it. The tactic
[forwards], described in [LibTactics.v] precisely helps with
instantiating a fact. So, let's see how it works out on our
example. *)
Theorem ceval_deterministic''': forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
(* Let's replay the proof up to the [assert] tactic. *)
introv E1 E2. gen st2.
induction E1; intros; inverts E2; tryfalse.
auto. auto.
(* We duplicate the goal for comparing different proofs. *)
dup 4.
(* The old proof: *)
assert (st' = st'0). apply IHE1_1. apply H1.
(* produces [H: st' = st'0]. *) skip.
(* The new proof, without automation: *)
forwards: IHE1_1. apply H1.
(* produces [H: st' = st'0]. *) skip.
(* The new proof, with automation: *)
forwards: IHE1_1. eauto.
(* produces [H: st' = st'0]. *) skip.
(* The new proof, with integrated automation: *)
forwards*: IHE1_1.
(* produces [H: st' = st'0]. *) skip.
Abort.
(** To polish the proof script, it remains to factorize the calls
to [auto], using the star symbol. The proof of determinism can then
be rewritten in only four lines, including no more than 10 tactics. *)
Theorem ceval_deterministic'''': forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
introv E1 E2. gen st2.
induction E1; intros; inverts* E2; tryfalse.
forwards*: IHE1_1. subst*.
forwards*: IHE1_1. subst*.
Qed.
End DeterministicImp.
(* ####################################################### *)
(** ** Preservation for STLC *)
Module PreservationProgressStlc.
Require Import StlcProp.
Import STLC.
Import STLCProp.
(** Consider the proof of perservation of STLC, shown below.
This proof already uses [eauto] through the triple-dot
mechanism. *)
Theorem preservation : forall t t' T,
has_type empty t T ->
t ==> t' ->
has_type empty t' T.
Proof with eauto.
remember (@empty ty) as Gamma.
intros t t' T HT. generalize dependent t'.
(has_type_cases (induction HT) Case); intros t' HE; subst Gamma.
Case "T_Var".
inversion HE.
Case "T_Abs".
inversion HE.
Case "T_App".
inversion HE; subst...
(* (step_cases (inversion HE) SCase); subst...*)
(* The ST_App1 and ST_App2 cases are immediate by induction, and
auto takes care of them *)
SCase "ST_AppAbs".
apply substitution_preserves_typing with T11...
inversion HT1...
Case "T_True".
inversion HE.
Case "T_False".
inversion HE.
Case "T_If".
inversion HE; subst...
Qed.
(** Exercise: rewrite this proof using tactics from [LibTactics]
and calling automation using the star symbol rather than the
triple-dot notation. More precisely, make use of the tactics
[inverts*] and [applys*] to call [auto*] after a call to
[inverts] or to [applys]. The solution is three lines long.*)
Theorem preservation' : forall t t' T,
has_type empty t T ->
t ==> t' ->
has_type empty t' T.
Proof.
(* FILL IN HERE *) admit.
Qed.
(* ####################################################### *)
(** ** Progress for STLC *)
(** Consider the proof of the progress theorem. *)
Theorem progress : forall t T,
has_type empty t T ->
value t \/ exists t', t ==> t'.
Proof with eauto.
intros t T Ht.
remember (@empty ty) as Gamma.
(has_type_cases (induction Ht) Case); subst Gamma...
Case "T_Var".
inversion H.
Case "T_App".
right. destruct IHHt1...
SCase "t1 is a value".
destruct IHHt2...
SSCase "t2 is a value".
inversion H; subst; try solve by inversion.
exists ([x0:=t2]t)...
SSCase "t2 steps".
destruct H0 as [t2' Hstp]. exists (tapp t1 t2')...
SCase "t1 steps".
destruct H as [t1' Hstp]. exists (tapp t1' t2)...
Case "T_If".
right. destruct IHHt1...
destruct t1; try solve by inversion...
inversion H. exists (tif x0 t2 t3)...
Qed.
(** Exercise: optimize the above proof.
Hint: make use of [destruct*] and [inverts*].
The solution consists of 10 short lines. *)
Theorem progress' : forall t T,
has_type empty t T ->
value t \/ exists t', t ==> t'.
Proof.
(* FILL IN HERE *) admit.
Qed.
End PreservationProgressStlc.
(* ####################################################### *)
(** ** BigStep and SmallStep *)
Module Semantics.
Require Import Smallstep.
(** Consider the proof relating a small-step reduction judgment
to a big-step reduction judgment. *)
Theorem multistep__eval : forall t v,
normal_form_of t v -> exists n, v = C n /\ t || n.
Proof.
intros t v Hnorm.
unfold normal_form_of in Hnorm.
inversion Hnorm as [Hs Hnf]; clear Hnorm.
rewrite nf_same_as_value in Hnf. inversion Hnf. clear Hnf.
exists n. split. reflexivity.
multi_cases (induction Hs) Case; subst.
Case "multi_refl".
apply E_Const.
Case "multi_step".
eapply step__eval. eassumption. apply IHHs. reflexivity.
Qed.
(** Our goal is to optimize the above proof. It is generally
easier to isolate inductions into separate lemmas. So,
we are going to first prove an intermediate result
that consists of the judgment over which the induction
is being performed. *)
(** Exercise: prove the following result, using tactics
[introv], [induction] and [subst], and [apply*].
The solution is 3 lines long. *)
Theorem multistep_eval_ind : forall t v,
t ==>* v -> forall n, C n = v -> t || n.
Proof.
(* FILL IN HERE *) admit.
Qed.
(** Exercise: using the lemma above, simplify the proof of
the result [multistep__eval]. You should use the tactics
[introv], [inverts], [split*] and [apply*].
The solution is 2 lines long. *)
Theorem multistep__eval' : forall t v,
normal_form_of t v -> exists n, v = C n /\ t || n.
Proof.
(* FILL IN HERE *) admit.
Qed.
(** If we try to combine the two proofs into a single one,
we will likely fail, because of a limitation of the
[induction] tactic. Indeed, this tactic looses
information when applied to a predicate whose arguments
are not reduced to variables, such as [t ==>* (C n)].
You will thus need to use the more powerful tactic called
[dependent induction]. This tactic is available only after
importing the [Program] library, as shown below. *)
Require Import Program.
(** Exercise: prove the lemma [multistep__eval] without invoking
the lemma [multistep_eval_ind], that is, by inlining the proof
by induction involved in [multistep_eval_ind], using the
tactic [dependent induction] instead of [induction].
The solution is 5 lines long. *)
Theorem multistep__eval'' : forall t v,
normal_form_of t v -> exists n, v = C n /\ t || n.
Proof.
(* FILL IN HERE *) admit.
Qed.
End Semantics.
(* ####################################################### *)
(** ** Preservation for STLCRef *)
Module PreservationProgressReferences.
Require Import References.
Import STLCRef.
Hint Resolve store_weakening extends_refl.
(** The proof of preservation for [STLCRef] can be found in chapter
[References]. It contains 58 lines (not counting the labelling of
cases). The optimized proof script is more than twice shorter. The
following material explains how to build the optimized proof
script. The resulting optimized proof script for the preservation
theorem appears afterwards. *)
Theorem preservation : forall ST t t' T st st',
has_type empty ST t T ->
store_well_typed ST st ->
t / st ==> t' / st' ->
exists ST',
(extends ST' ST /\
has_type empty ST' t' T /\
store_well_typed ST' st').
Proof.
(* old: [Proof. with eauto using store_weakening, extends_refl.]
new: [Proof.], and the two lemmas are registered as hints
before the proof of the lemma, possibly inside a section in
order to restrict the scope of the hints. *)
remember (@empty ty) as Gamma. introv Ht. gen t'.
(has_type_cases (induction Ht) Case); introv HST Hstep;
(* old: [subst; try (solve by inversion); inversion Hstep; subst;
try (eauto using store_weakening, extends_refl)]
new: [subst Gamma; inverts Hstep; eauto.]
We want to be more precise on what exactly we substitute,
and we do not want to call [try (solve by inversion)] which
is way to slow. *)
subst Gamma; inverts Hstep; eauto.
Case "T_App".
SCase "ST_AppAbs".
(* old:
exists ST. inversion Ht1; subst.
split; try split... eapply substitution_preserves_typing... *)
(* new: we use [inverts] in place of [inversion] and [splits] to
split the conjunction, and [applys*] in place of [eapply...] *)
exists ST. inverts Ht1. splits*. applys* substitution_preserves_typing.
SCase "ST_App1".
(* old:
eapply IHHt1 in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'... *)
(* new: The tactic [eapply IHHt1 in H0...] applies [IHHt1] to [H0].
But [H0] is only thing that [IHHt1] could be applied to, so
there [eauto] can figure this out on its own. The tactic
[forwards] is used to instantiate all the arguments of [IHHt1],
producing existential variables and subgoals when needed. *)
forwards: IHHt1. eauto. eauto. eauto.
(* At this point, we need to decompose the hypothesis [H] that has
just been created by [forwards]. This is done by the first part
of the preprocessing phase of [jauto]. *)
jauto_set_hyps; intros.
(* It remains to decompose the goal, which is done by the second
part of the preprocessing phase of [jauto]. *)
jauto_set_goal; intros.
(* All the subgoals produced can then be solved by [eauto]. *)
eauto. eauto. eauto.
SCase "ST_App2".
(* old:
eapply IHHt2 in H5...
inversion H5 as [ST' [Hext [Hty Hsty]]].
exists ST'... *)
(* new: this time, we need to call [forwards] on [IHHt2],
and we call [jauto] right away, by writing [forwards*],
proving the goal in a single tactic! *)
forwards*: IHHt2.
(* The same trick works for many of the other subgoals. *)
forwards*: IHHt.
forwards*: IHHt.
forwards*: IHHt1.
forwards*: IHHt2.
forwards*: IHHt1.
Case "T_Ref".
SCase "ST_RefValue".
(* old:
exists (snoc ST T1).
inversion HST; subst.
split.
apply extends_snoc.
split.
replace (TRef T1)
with (TRef (store_Tlookup (length st) (snoc ST T1))).
apply T_Loc.
rewrite <- H. rewrite length_snoc. omega.
unfold store_Tlookup. rewrite <- H. rewrite nth_eq_snoc...
apply store_well_typed_snoc; assumption. *)
(* new: in this proof case, we need to perform an inversion
without removing the hypothesis. The tactic [inverts keep]
serves exactly this purpose. *)
exists (snoc ST T1). inverts keep HST. splits.
(* The proof of the first subgoal needs not be changed *)
apply extends_snoc.
(* For the second subgoal, we use the tactic [applys_eq] to avoid
a manual [replace] before [T_loc] can be applied. *)
applys_eq T_Loc 1.
(* To justify the inequality, there is no need to call [rewrite <- H],
because the tactic [omega] is able to exploit [H] on its own.
So, only the rewriting of [lenght_snoc] and the call to the
tactic [omega] remain. *)
rewrite length_snoc. omega.
(* The next proof case is hard to polish because it relies on the
lemma [nth_eq_snoc] whose statement is not automation-friendly.
We'll come back to this proof case further on. *)
unfold store_Tlookup. rewrite <- H. rewrite* nth_eq_snoc.
(* Last, we replace [apply ..; assumption] with [apply* ..] *)
apply* store_well_typed_snoc.
forwards*: IHHt.
Case "T_Deref".
SCase "ST_DerefLoc".
(* old:
exists ST. split; try split...
destruct HST as [_ Hsty].
replace T11 with (store_Tlookup l ST).
apply Hsty...
inversion Ht; subst... *)
(* new: we start by calling [exists ST] and [splits*]. *)
exists ST. splits*.
(* new: we replace [destruct HST as [_ Hsty]] by the following *)
lets [_ Hsty]: HST.
(* new: then we use the tactic [applys_eq] to avoid the need to
perform a manual [replace] before applying [Hsty]. *)
applys_eq* Hsty 1.
(* new: we then can call [inverts] in place of [inversion;subst] *)
inverts* Ht.
forwards*: IHHt.
Case "T_Assign".
SCase "ST_Assign".
(* old:
exists ST. split; try split...
eapply assign_pres_store_typing...
inversion Ht1; subst... *)
(* new: simply using nicer tactics *)
exists ST. splits*. applys* assign_pres_store_typing. inverts* Ht1.
forwards*: IHHt1.
forwards*: IHHt2.
Qed.
(** Let's come back to the proof case that was hard to optimize.
The difficulty comes from the statement of [nth_eq_snoc], which
takes the form [nth (length l) (snoc l x) d = x]. This lemma is
hard to exploit because its first argument, [length l], mentions
a list [l] that has to be exactly the same as the [l] occuring in
[snoc l x]. In practice, the first argument is often a natural
number [n] that is provably equal to [length l] yet that is not
syntactically equal to [length l]. There is a simple fix for
making [nth_eq_snoc] easy to apply: introduce the intermediate
variable [n] explicitly, so that the goal becomes
[nth n (snoc l x) d = x], with a premise asserting [n = length l]. *)
Lemma nth_eq_snoc' : forall (A : Type) (l : list A) (x d : A) (n : nat),
n = length l -> nth n (snoc l x) d = x.
Proof. intros. subst. apply nth_eq_snoc. Qed.
(** The proof case for [ref] from the preservation theorem then
becomes much easier to prove, because [rewrite nth_eq_snoc']
now succeeds. *)
Lemma preservation_ref : forall (st:store) (ST : store_ty) T1,
length ST = length st ->
TRef T1 = TRef (store_Tlookup (length st) (snoc ST T1)).
Proof.
intros. dup.
(* A first proof, with an explicit [unfold] *)
unfold store_Tlookup. rewrite* nth_eq_snoc'.
(* A second proof, with a call to [fequal] *)
fequal. symmetry. apply* nth_eq_snoc'.
Qed.
(** The optimized proof of preservation is summarized next. *)
Theorem preservation' : forall ST t t' T st st',
has_type empty ST t T ->
store_well_typed ST st ->
t / st ==> t' / st' ->
exists ST',
(extends ST' ST /\
has_type empty ST' t' T /\
store_well_typed ST' st').
Proof.
remember (@empty ty) as Gamma. introv Ht. gen t'.
induction Ht; introv HST Hstep; subst Gamma; inverts Hstep; eauto.
exists ST. inverts Ht1. splits*. applys* substitution_preserves_typing.
forwards*: IHHt1.
forwards*: IHHt2.
forwards*: IHHt.
forwards*: IHHt.
forwards*: IHHt1.
forwards*: IHHt2.
forwards*: IHHt1.
exists (snoc ST T1). inverts keep HST. splits.
apply extends_snoc.
applys_eq T_Loc 1.
rewrite length_snoc. omega.
unfold store_Tlookup. rewrite* nth_eq_snoc'.
apply* store_well_typed_snoc.
forwards*: IHHt.
exists ST. splits*. lets [_ Hsty]: HST.
applys_eq* Hsty 1. inverts* Ht.
forwards*: IHHt.
exists ST. splits*. applys* assign_pres_store_typing. inverts* Ht1.
forwards*: IHHt1.
forwards*: IHHt2.
Qed.
(* ####################################################### *)
(** ** Progress for STLCRef *)
(** The proof of progress for [STLCRef] can be found in chapter
[References]. It contains 53 lines and the optimized proof script
is, here again, half the length. *)
Theorem progress : forall ST t T st,
has_type empty ST t T ->
store_well_typed ST st ->
(value t \/ exists t', exists st', t / st ==> t' / st').
Proof.
introv Ht HST. remember (@empty ty) as Gamma.
induction Ht; subst Gamma; tryfalse; try solve [left*].
right. destruct* IHHt1 as [K|].
inverts K; inverts Ht1.
destruct* IHHt2.
right. destruct* IHHt as [K|].
inverts K; try solve [inverts Ht]. eauto.
right. destruct* IHHt as [K|].
inverts K; try solve [inverts Ht]. eauto.
right. destruct* IHHt1 as [K|].
inverts K; try solve [inverts Ht1].
destruct* IHHt2 as [M|].
inverts M; try solve [inverts Ht2]. eauto.
right. destruct* IHHt1 as [K|].
inverts K; try solve [inverts Ht1]. destruct* n.
right. destruct* IHHt.
right. destruct* IHHt as [K|].
inverts K; inverts Ht as M.
inverts HST as N. rewrite* N in M.
right. destruct* IHHt1 as [K|].
destruct* IHHt2.
inverts K; inverts Ht1 as M.
inverts HST as N. rewrite* N in M.
Qed.
End PreservationProgressReferences.
(* ####################################################### *)
(** ** Subtyping *)
Module SubtypingInversion.
Require Import Sub.
(** Consider the inversion lemma for typing judgment
of abstractions in a type system with subtyping. *)
Lemma abs_arrow : forall x S1 s2 T1 T2,
has_type empty (tabs x S1 s2) (TArrow T1 T2) ->
subtype T1 S1
/\ has_type (extend empty x S1) s2 T2.
Proof with eauto.
intros x S1 s2 T1 T2 Hty.
apply typing_inversion_abs in Hty.
destruct Hty as [S2 [Hsub Hty]].
apply sub_inversion_arrow in Hsub.
destruct Hsub as [U1 [U2 [Heq [Hsub1 Hsub2]]]].
inversion Heq; subst...
Qed.
(** Exercise: optimize the proof script, using
[introv], [lets] and [inverts*]. In particular,
you will find it useful to replace the pattern
[apply K in H. destruct H as I] with [lets I: K H].
The solution is 4 lines. *)
Lemma abs_arrow' : forall x S1 s2 T1 T2,
has_type empty (tabs x S1 s2) (TArrow T1 T2) ->
subtype T1 S1
/\ has_type (extend empty x S1) s2 T2.
Proof.
(* FILL IN HERE *) admit.
Qed.
(** The lemma [substitution_preserves_typing] has already been used to
illustrate the working of [lets] and [applys] in chapter
[UseTactics]. Optimize further this proof using automation (with
the star symbol), and using the tactic [cases_if']. The solution
is 33 lines, including the [Case] instructions (21 lines without
them). *)
Lemma substitution_preserves_typing : forall Gamma x U v t S,
has_type (extend Gamma x U) t S ->
has_type empty v U ->
has_type Gamma ([x:=v]t) S.
Proof.
(* FILL IN HERE *) admit.
Qed.
End SubtypingInversion.
(* ####################################################### *)
(** * Advanced Topics in Proof Search *)
(* ####################################################### *)
(** ** Stating Lemmas in the Right Way *)
(** Due to its depth-first strategy, [eauto] can get exponentially
slower as the depth search increases, even when a short proof
exists. In general, to make proof search run reasonably fast, one
should avoid using a depth search greater than 5 or 6. Moreover,
one should try to minimize the number of applicable lemmas, and
usually put first the hypotheses whose proof usefully instantiates
the existential variables.
In fact, the ability for [eauto] to solve certain goals actually
depends on the order in which the hypotheses are stated. This point
is illustrated through the following example, in which [P] is
a predicate on natural numbers. This predicate is such that
[P n] holds for any [n] as soon as [P m] holds for at least one [m]
different from zero. The goal is to prove that [P 2] implies [P 1].
When the hypothesis about [P] is stated in the form
[forall n m, P m -> m <> 0 -> P n], then [eauto] works. However, with
[forall n m, m <> 0 -> P m -> P n], the tactic [eauto] fails. *)
Lemma order_matters_1 : forall (P : nat->Prop),
(forall n m, P m -> m <> 0 -> P n) -> P 2 -> P 1.
Proof.
eauto. (* Success *)
(* The proof: [intros P H K. eapply H. apply K. auto.] *)
Qed.
Lemma order_matters_2 : forall (P : nat->Prop),
(forall n m, m <> 0 -> P m -> P n) -> P 5 -> P 1.
Proof.
eauto. (* Failure *)
(* To understand why, let us replay the previous proof *)
intros P H K.
eapply H.
(* The application of [eapply] has left two subgoals,
[?X <> 0] and [P ?X], where [?X] is an existential variable. *)
(* Solving the first subgoal is easy for [eauto]: it suffices
to instantiate [?X] as the value [1], which is the simplest
value that satisfies [?X <> 0]. *)
eauto.
(* But then the second goal becomes [P 1], which is where we
started from. So, [eauto] gets stuck at this point. *)
Abort.
(** It is very important to understand that the hypothesis [forall n
m, P m -> m <> 0 -> P n] is eauto-friendly, whereas [forall n m, m
<> 0 -> P m -> P n] really isn't. Guessing a value of [m] for
which [P m] holds and then checking that [m <> 0] holds works well
because there are few values of [m] for which [P m] holds. So, it
is likely that [eauto] comes up with the right one. On the other
hand, guessing a value of [m] for which [m <> 0] and then checking
that [P m] holds does not work well, because there are many values
of [m] that satisfy [m <> 0] but not [P m]. *)
(* ####################################################### *)
(** ** Unfolding of Definitions During Proof-Search *)
(** The use of intermediate definitions is generally encouraged in a
formal development as it usually leads to more concise and more
readable statements. Yet, definitions can make it a little harder
to automate proofs. The problem is that it is not obvious for a
proof search mechanism to know when definitions need to be
unfolded. Note that a naive strategy that consists in unfolding
all definitions before calling proof search does not scale up to
large proofs, so we avoid it. This section introduces a few
techniques for avoiding to manually unfold definitions before
calling proof search. *)
(** To illustrate the treatment of definitions, let [P] be an abstract
predicate on natural numbers, and let [myFact] be a definition
denoting the proposition [P x] holds for any [x] less than or
equal to 3. *)
Axiom P : nat -> Prop.
Definition myFact := forall x, x <= 3 -> P x.
(** Proving that [myFact] under the assumption that [P x] holds for
any [x] should be trivial. Yet, [auto] fails to prove it unless we
unfold the definition of [myFact] explicitly. *)
Lemma demo_hint_unfold_goal_1 :
(forall x, P x) -> myFact.
Proof.
auto. (* Proof search doesn't know what to do, *)
unfold myFact. auto. (* unless we unfold the definition. *)
Qed.
(** To automate the unfolding of definitions that appear as proof
obligation, one can use the command [Hint Unfold myFact] to tell
Coq that it should always try to unfold [myFact] when [myFact]
appears in the goal. *)
Hint Unfold myFact.
(** This time, automation is able to see through the definition
of [myFact]. *)
Lemma demo_hint_unfold_goal_2 :
(forall x, P x) -> myFact.
Proof. auto. Qed.
(** However, the [Hint Unfold] mechanism only works for unfolding
definitions that appear in the goal. In general, proof search does
not unfold definitions from the context. For example, assume we
want to prove that [P 3] holds under the assumption that [True ->
myFact]. *)
Lemma demo_hint_unfold_context_1 :
(True -> myFact) -> P 3.
Proof.
intros.
auto. (* fails *)
unfold myFact in *. auto. (* succeeds *)
Qed.
(** There is actually one exception to the previous rule: a constant
occuring in an hypothesis is automatically unfolded if the
hypothesis can be directly applied to the current goal. For example,
[auto] can prove [myFact -> P 3], as illustrated below. *)
Lemma demo_hint_unfold_context_2 :
myFact -> P 3.
Proof. auto. Qed.
(* ####################################################### *)
(** ** Automation for Proving Absurd Goals *)
(** In this section, we'll see that lemmas concluding on a negation
are generally not useful as hints, and that lemmas whose
conclusion is [False] can be useful hints but having too many of
them makes proof search inefficient. We'll also see a practical
work-around to the efficiency issue. *)
(** Consider the following lemma, which asserts that a number
less than or equal to 3 is not greater than 3. *)
Parameter le_not_gt : forall x,
(x <= 3) -> ~ (x > 3).
(** Equivalently, one could state that a number greater than three is
not less than or equal to 3. *)
Parameter gt_not_le : forall x,
(x > 3) -> ~ (x <= 3).
(** In fact, both statements are equivalent to a third one stating
that [x <= 3] and [x > 3] are contradictory, in the sense that
they imply [False]. *)
Parameter le_gt_false : forall x,
(x <= 3) -> (x > 3) -> False.
(** The following investigation aim at figuring out which of the three
statments is the most convenient with respect to proof
automation. The following material is enclosed inside a [Section],
so as to restrict the scope of the hints that we are adding. In
other words, after the end of the section, the hints added within
the section will no longer be active.*)
Section DemoAbsurd1.
(** Let's try to add the first lemma, [le_not_gt], as hint,
and see whether we can prove that the proposition
[exists x, x <= 3 /\ x > 3] is absurd. *)
Hint Resolve le_not_gt.
Lemma demo_auto_absurd_1 :
(exists x, x <= 3 /\ x > 3) -> False.
Proof.
intros. jauto_set. (* decomposes the assumption *)
(* debug *) eauto. (* does not see that [le_not_gt] could apply *)
eapply le_not_gt. eauto. eauto.
Qed.
(** The lemma [gt_not_le] is symmetric to [le_not_gt], so it will not
be any better. The third lemma, [le_gt_false], is a more useful
hint, because it concludes on [False], so proof search will try to
apply it when the current goal is [False]. *)
Hint Resolve le_gt_false.
Lemma demo_auto_absurd_2 :
(exists x, x <= 3 /\ x > 3) -> False.
Proof.
dup.
(* detailed version: *)
intros. jauto_set. (* debug *) eauto.
(* short version: *)
jauto.
Qed.
(** In summary, a lemma of the form [H1 -> H2 -> False] is a much more
effective hint than [H1 -> ~ H2], even though the two statments
are equivalent up to the definition of the negation symbol [~]. *)
(** That said, one should be careful with adding lemmas whose
conclusion is [False] as hint. The reason is that whenever
reaching the goal [False], the proof search mechanism will
potentially try to apply all the hints whose conclusion is [False]
before applying the appropriate one. *)
End DemoAbsurd1.
(** Adding lemmas whose conclusion is [False] as hint can be, locally,
a very effective solution. However, this approach does not scale
up for global hints. For most practical applications, it is
reasonable to give the name of the lemmas to be exploited for
deriving a contradiction. The tactic [false H], provided by
[LibTactics] serves that purpose: [false H] replaces the goal
with [False] and calls [eapply H]. Its behavior is described next.
Observe that any of the three statements [le_not_gt], [gt_not_le]
or [le_gt_false] can be used. *)
Lemma demo_false : forall x,
(x <= 3) -> (x > 3) -> 4 = 5.
Proof.
intros. dup 4.
(* A failed proof: *)
false. eapply le_gt_false.
auto. (* here, [auto] does not prove [?x <= 3] by using [H] but
by using the lemma [le_refl : forall x, x <= x]. *)
(* The second subgoal becomes [3 > 3], which is not provable. *)
skip.
(* A correct proof: *)
false. eapply le_gt_false.
eauto. (* here, [eauto] uses [H], as expected, to prove [?x <= 3] *)
eauto. (* so the second subgoal becomes [x > 3] *)
(* The same proof using [false]: *)
false le_gt_false. eauto. eauto.
(* The lemmas [le_not_gt] and [gt_not_le] work as well *)
false le_not_gt. eauto. eauto.
Qed.
(** In the above example, [false le_gt_false; eauto] proves the goal,
but [false le_gt_false; auto] does not, because [auto] does not
correctly instantiate the existential variable. Note that [false*
le_gt_false] would not work either, because the star symbol tries
to call [auto] first. So, there are two possibilities for
completing the proof: either call [false le_gt_false; eauto], or
call [false* (le_gt_false 3)]. *)
(* ####################################################### *)
(** ** Automation for Transitivity Lemmas *)
(** Some lemmas should never be added as hints, because they would
very badly slow down proof search. The typical example is that of
transitivity results. This section describes the problem and
presents a general workaround.
Consider a subtyping relation, written [subtype S T], that relates
two object [S] and [T] of type [typ]. Assume that this relation
has been proved reflexive and transitive. The corresponding lemmas
are named [subtype_refl] and [subtype_trans]. *)
Parameter typ : Type.
Parameter subtype : typ -> typ -> Prop.
Parameter subtype_refl : forall T,
subtype T T.
Parameter subtype_trans : forall S T U,
subtype S T -> subtype T U -> subtype S U.
(** Adding reflexivity as hint is generally a good idea,
so let's add reflexivity of subtyping as hint. *)
Hint Resolve subtype_refl.
(** Adding transitivity as hint is generally a bad idea. To
understand why, let's add it as hint and see what happens.
Because we cannot remove hints once we've added them, we are going
to open a "Section," so as to restrict the scope of the
transitivity hint to that section. *)
Section HintsTransitivity.
Hint Resolve subtype_trans.
(** Now, consider the goal [forall S T, subtype S T], which clearly has
no hope of being solved. Let's call [eauto] on this goal. *)
Lemma transitivity_bad_hint_1 : forall S T,
subtype S T.
Proof.
intros. (* debug *) eauto. (* Investigates 106 applications... *)
Abort.
(** Note that after closing the section, the hint [subtype_trans]
is no longer active. *)
End HintsTransitivity.
(** In the previous example, the proof search has spent a lot of time
trying to apply transitivity and reflexivity in every possible
way. Its process can be summarized as follows. The first goal is
[subtype S T]. Since reflexivity does not apply, [eauto] invokes
transitivity, which produces two subgoals, [subtype S ?X] and
[subtype ?X T]. Solving the first subgoal, [subtype S ?X], is
straightforward, it suffices to apply reflexivity. This unifies
[?X] with [S]. So, the second sugoal, [subtype ?X T],
becomes [subtype S T], which is exactly what we started from...
The problem with the transitivity lemma is that it is applicable
to any goal concluding on a subtyping relation. Because of this,
[eauto] keeps trying to apply it even though it most often doesn't
help to solve the goal. So, one should never add a transitivity
lemma as a hint for proof search. *)
(** There is a general workaround for having automation to exploit
transitivity lemmas without giving up on efficiency. This workaround
relies on a powerful mechanism called "external hint." This
mechanism allows to manually describe the condition under which
a particular lemma should be tried out during proof search.
For the case of transitivity of subtyping, we are going to tell
Coq to try and apply the transitivity lemma on a goal of the form
[subtype S U] only when the proof context already contains an
assumption either of the form [subtype S T] or of the form
[subtype T U]. In other words, we only apply the transitivity
lemma when there is some evidence that this application might
help. To set up this "external hint," one has to write the
following. *)
Hint Extern 1 (subtype ?S ?U) =>
match goal with
| H: subtype S ?T |- _ => apply (@subtype_trans S T U)
| H: subtype ?T U |- _ => apply (@subtype_trans S T U)
end.
(** This hint declaration can be understood as follows.
- "Hint Extern" introduces the hint.
- The number "1" corresponds to a priority for proof search.
It doesn't matter so much what priority is used in practice.
- The pattern [subtype ?S ?U] describes the kind of goal on
which the pattern should apply. The question marks are used
to indicate that the variables [?S] and [?U] should be bound
to some value in the rest of the hint description.
- The construction [match goal with ... end] tries to recognize
patterns in the goal, or in the proof context, or both.
- The first pattern is [H: subtype S ?T |- _]. It indices that
the context should contain an hypothesis [H] of type
[subtype S ?T], where [S] has to be the same as in the goal,
and where [?T] can have any value.
- The symbol [|- _] at the end of [H: subtype S ?T |- _] indicates
that we do not impose further condition on how the proof
obligation has to look like.
- The branch [=> apply (@subtype_trans S T U)] that follows
indicates that if the goal has the form [subtype S U] and if
there exists an hypothesis of the form [subtype S T], then
we should try and apply transitivity lemma instantiated on
the arguments [S], [T] and [U]. (Note: the symbol [@] in front of
[subtype_trans] is only actually needed when the "Implicit Arguments"
feature is activated.)
- The other branch, which corresponds to an hypothesis of the form
[H: subtype ?T U] is symmetrical.
Note: the same external hint can be reused for any other transitive
relation, simply by renaming [subtype] into the name of that relation. *)
(** Let us see an example illustrating how the hint works. *)
Lemma transitivity_workaround_1 : forall T1 T2 T3 T4,
subtype T1 T2 -> subtype T2 T3 -> subtype T3 T4 -> subtype T1 T4.
Proof.
intros. (* debug *) eauto. (* The trace shows the external hint being used *)
Qed.
(** We may also check that the new external hint does not suffer from the
complexity blow up. *)
Lemma transitivity_workaround_2 : forall S T,
subtype S T.
Proof.
intros. (* debug *) eauto. (* Investigates 0 applications *)
Abort.
(* ####################################################### *)
(** * Decision Procedures *)
(** A decision procedure is able to solve proof obligations whose
statement admits a particular form. This section describes three
useful decision procedures. The tactic [omega] handles goals
involving arithmetic and inequalities, but not general
multiplications. The tactic [ring] handles goals involving
arithmetic, including multiplications, but does not support
inequalities. The tactic [congruence] is able to prove equalities
and inequalities by exploiting equalities available in the proof
context. *)
(* ####################################################### *)
(** ** Omega *)
(** The tactic [omega] supports natural numbers (type [nat]) as well as
integers (type [Z], available by including the module [ZArith]).
It supports addition, substraction, equalities and inequalities.
Before using [omega], one needs to import the module [Omega],
as follows. *)
Require Import Omega.
(** Here is an example. Let [x] and [y] be two natural numbers
(they cannot be negative). Assume [y] is less than 4, assume
[x+x+1] is less than [y], and assume [x] is not zero. Then,
it must be the case that [x] is equal to one. *)
Lemma omega_demo_1 : forall (x y : nat),
(y <= 4) -> (x + x + 1 <= y) -> (x <> 0) -> (x = 1).
Proof. intros. omega. Qed.
(** Another example: if [z] is the mean of [x] and [y], and if the
difference between [x] and [y] is at most [4], then the difference
between [x] and [z] is at most 2. *)
Lemma omega_demo_2 : forall (x y z : nat),
(x + y = z + z) -> (x - y <= 4) -> (x - z <= 2).
Proof. intros. omega. Qed.
(** One can proof [False] using [omega] if the mathematical facts
from the context are contradictory. In the following example,
the constraints on the values [x] and [y] cannot be all
satisfied in the same time. *)
Lemma omega_demo_3 : forall (x y : nat),
(x + 5 <= y) -> (y - x < 3) -> False.
Proof. intros. omega. Qed.
(** Note: [omega] can prove a goal by contradiction only if its
conclusion is reduced [False]. The tactic [omega] always fails
when the conclusion is an arbitrary proposition [P], even though
[False] implies any proposition [P] (by [ex_falso_quodlibet]). *)
Lemma omega_demo_4 : forall (x y : nat) (P : Prop),
(x + 5 <= y) -> (y - x < 3) -> P.
Proof.
intros.
(* Calling [omega] at this point fails with the message:
"Omega: Can't solve a goal with proposition variables" *)
(* So, one needs to replace the goal by [False] first. *)
false. omega.
Qed.
(* ####################################################### *)
(** ** Ring *)
(** Compared with [omega], the tactic [ring] adds support for
multiplications, however it gives up the ability to reason on
inequations. Moreover, it supports only integers (type [Z]) and
not natural numbers (type [nat]). Here is an example showing how
to use [ring]. *)
Module RingDemo.
Require Import ZArith.
Open Scope Z_scope.
(* Arithmetic symbols are now interpreted in [Z] *)
Lemma ring_demo : forall (x y z : Z),
x * (y + z) - z * 3 * x
= x * y - 2 * x * z.
Proof. intros. ring. Qed.
End RingDemo.
(* ####################################################### *)
(** ** Congruence *)
(** The tactic [congruence] is able to exploit equalities from the
proof context in order to automatically perform the rewriting
operations necessary to establish a goal. It is slightly more
powerful than the tactic [subst], which can only handle equalities
of the form [x = e] where [x] is a variable and [e] an
expression. *)
Lemma congruence_demo_1 :
forall (f : nat->nat->nat) (g h : nat->nat) (x y z : nat),
f (g x) (g y) = z ->
2 = g x ->
g y = h z ->
f 2 (h z) = z.
Proof. intros. congruence. Qed.
(** Moreover, [congruence] is able to exploit universally quantified
equalities, for example [forall a, g a = h a]. *)
Lemma congruence_demo_2 :
forall (f : nat->nat->nat) (g h : nat->nat) (x y z : nat),
(forall a, g a = h a) ->
f (g x) (g y) = z ->
g x = 2 ->
f 2 (h y) = z.
Proof. congruence. Qed.
(** Next is an example where [congruence] is very useful. *)
Lemma congruence_demo_4 : forall (f g : nat->nat),
(forall a, f a = g a) ->
f (g (g 2)) = g (f (f 2)).
Proof. congruence. Qed.
(** The tactic [congruence] is able to prove a contradiction if the
goal entails an equality that contradicts an inequality available
in the proof context. *)
Lemma congruence_demo_3 :
forall (f g h : nat->nat) (x : nat),
(forall a, f a = h a) ->
g x = f x ->
g x <> h x ->
False.
Proof. congruence. Qed.
(** One of the strengths of [congruence] is that it is a very fast
tactic. So, one should not hesitate to invoke it wherever it might
help. *)
(* ####################################################### *)
(** * Summary *)
(** Let us summarize the main automation tactics available.
- [auto] automatically applies [reflexivity], [assumption], and [apply].
- [eauto] moreover tries [eapply], and in particular can instantiate
existentials in the conclusion.
- [iauto] extends [eauto] with support for negation, conjunctions, and
disjunctions. However, its support for disjunction can make it
exponentially slow.
- [jauto] extends [eauto] with support for negation, conjunctions, and
existential at the head of hypothesis.
- [congruence] helps reasoning about equalities and inequalities.
- [omega] proves arithmetic goals with equalities and inequalities,
but it does not support multiplication.
- [ring] proves arithmetic goals with multiplications, but does not
support inequalities.
In order to set up automation appropriately, keep in mind the following
rule of thumbs:
- automation is all about balance: not enough automation makes proofs
not very robust on change, whereas too much automation makes proofs
very hard to fix when they break.
- if a lemma is not goal directed (i.e., some of its variables do not
occur in its conclusion), then the premises need to be ordered in
such a way that proving the first premises maximizes the chances of
correctly instantiating the variables that do not occur in the conclusion.
- a lemma whose conclusion is [False] should only be added as a local
hint, i.e., as a hint within the current section.
- a transitivity lemma should never be considered as hint; if automation
of transitivity reasoning is really necessary, an [Extern Hint] needs
to be set up.
- a definition usually needs to be accompanied with a [Hint Unfold].
Becoming a master in the black art of automation certainly requires
some investment, however this investment will pay off very quickly.
*)
|
// This is a component of pluto_servo, a PWM servo driver and quadrature
// counter for emc2
// Copyright 2006 Jeff Epler <[email protected]>
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
module pluto_servo(clk, led, nConfig, epp_nReset, pport_data, nWrite, nWait, nDataStr,
nAddrStr, dout, din, quadA, quadB, quadZ, up, down);
parameter QW=14;
input clk;
output led, nConfig;
inout [7:0] pport_data;
input nWrite;
output nWait;
input nDataStr, nAddrStr, epp_nReset;
wire do_tristate;
reg[9:0] real_dout; output [9:0] dout = do_tristate ? 10'bZZZZZZZZZZ : real_dout;
input [7:0] din;
input [3:0] quadA;
input [3:0] quadB;
input [3:0] quadZ;
wire[3:0] real_up; output [3:0] up = do_tristate ? 4'bZZZZ : real_up;
wire[3:0] real_down; output [3:0] down = do_tristate ? 4'bZZZZ : real_down;
reg Zpolarity;
wire [2*QW:0] quad0, quad1, quad2, quad3;
wire do_enable_wdt;
wire pwm_at_top;
wdt w(clk, do_enable_wdt, pwm_at_top, do_tristate);
// PWM stuff
// PWM clock is about 20kHz for clk @ 40MHz, 11-bit cnt
reg [10:0] pwmcnt;
wire [10:0] top = 11'd2046;
assign pwm_at_top = (pwmcnt == top);
reg [15:0] pwm0, pwm1, pwm2, pwm3;
always @(posedge clk) begin
if(pwm_at_top) pwmcnt <= 0;
else pwmcnt <= pwmcnt + 11'd1;
end
wire [10:0] pwmrev = {
pwmcnt[4], pwmcnt[5], pwmcnt[6], pwmcnt[7], pwmcnt[8], pwmcnt[9],
pwmcnt[10], pwmcnt[3:0]};
wire [10:0] pwmcmp0 = pwm0[14] ? pwmrev : pwmcnt;
// wire [10:0] pwmcmp1 = pwm1[14] ? pwmrev : pwmcnt;
// wire [10:0] pwmcmp2 = pwm2[14] ? pwmrev : pwmcnt;
// wire [10:0] pwmcmp3 = pwm3[14] ? pwmrev : pwmcnt;
wire pwmact0 = pwm0[10:0] > pwmcmp0;
wire pwmact1 = pwm1[10:0] > pwmcmp0;
wire pwmact2 = pwm2[10:0] > pwmcmp0;
wire pwmact3 = pwm3[10:0] > pwmcmp0;
assign real_up[0] = pwm0[12] ^ (pwm0[15] ? 1'd0 : pwmact0);
assign real_up[1] = pwm1[12] ^ (pwm1[15] ? 1'd0 : pwmact1);
assign real_up[2] = pwm2[12] ^ (pwm2[15] ? 1'd0 : pwmact2);
assign real_up[3] = pwm3[12] ^ (pwm3[15] ? 1'd0 : pwmact3);
assign real_down[0] = pwm0[13] ^ (~pwm0[15] ? 1'd0 : pwmact0);
assign real_down[1] = pwm1[13] ^ (~pwm1[15] ? 1'd0 : pwmact1);
assign real_down[2] = pwm2[13] ^ (~pwm2[15] ? 1'd0 : pwmact2);
assign real_down[3] = pwm3[13] ^ (~pwm3[15] ? 1'd0 : pwmact3);
// Quadrature stuff
// Quadrature is digitized at 40MHz into 14-bit counters
// Read up to 2^13 pulses / polling period = 8MHz for 1kHz servo period
reg qtest;
wire qr0, qr1, qr2, qr3;
quad q0(clk, qtest ? real_dout[0] : quadA[0], qtest ? real_dout[1] : quadB[0], qtest ? real_dout[2] : quadZ[0]^Zpolarity, qr0, quad0);
quad q1(clk, quadA[1], quadB[1], quadZ[1]^Zpolarity, qr1, quad1);
quad q2(clk, quadA[2], quadB[2], quadZ[2]^Zpolarity, qr2, quad2);
quad q3(clk, quadA[3], quadB[3], quadZ[3]^Zpolarity, qr3, quad3);
// EPP stuff
wire EPP_write = ~nWrite;
wire EPP_read = nWrite;
wire EPP_addr_strobe = ~nAddrStr;
wire EPP_data_strobe = ~nDataStr;
wire EPP_strobe = EPP_data_strobe | EPP_addr_strobe;
wire EPP_wait; assign nWait = ~EPP_wait;
wire [7:0] EPP_datain = pport_data;
wire [7:0] EPP_dataout; assign pport_data = EPP_dataout;
reg [4:0] EPP_strobe_reg;
always @(posedge clk) EPP_strobe_reg <= {EPP_strobe_reg[3:0], EPP_strobe};
wire EPP_strobe_edge1 = (EPP_strobe_reg[2:1]==2'b01);
// reg led;
assign EPP_wait = EPP_strobe_reg[4];
reg[4:0] addr_reg;
reg[7:0] lowbyte;
always @(posedge clk)
if(EPP_strobe_edge1 & EPP_write & EPP_addr_strobe) begin
addr_reg <= EPP_datain[4:0];
end
else if(EPP_strobe_edge1 & !EPP_addr_strobe) addr_reg <= addr_reg + 4'd1;
always @(posedge clk) begin
if(EPP_strobe_edge1 & EPP_write & EPP_data_strobe) begin
if(addr_reg[3:0] == 4'd1) pwm0 <= { EPP_datain, lowbyte };
else if(addr_reg[3:0] == 4'd3) pwm1 <= { EPP_datain, lowbyte };
else if(addr_reg[3:0] == 4'd5) pwm2 <= { EPP_datain, lowbyte };
else if(addr_reg[3:0] == 4'd7) pwm3 <= { EPP_datain, lowbyte };
else if(addr_reg[3:0] == 4'd9) begin
real_dout <= { EPP_datain[1:0], lowbyte };
Zpolarity <= EPP_datain[7];
qtest <= EPP_datain[5];
end
else lowbyte <= EPP_datain;
end
end
reg [31:0] data_buf;
always @(posedge clk) begin
if(EPP_strobe_edge1 & EPP_read && addr_reg[1:0] == 2'd0) begin
if(addr_reg[4:2] == 3'd0) data_buf <= quad0;
else if(addr_reg[4:2] == 3'd1) data_buf <= quad1;
else if(addr_reg[4:2] == 3'd2) data_buf <= quad2;
else if(addr_reg[4:2] == 3'd3) data_buf <= quad3;
else if(addr_reg[4:2] == 3'd4)
data_buf <= {quadA, quadB, quadZ, din};
end
end
// the addr_reg test looks funny because it is auto-incremented in an always
// block so "1" reads the low byte, "2 and "3" read middle bytes, and "0"
// reads the high byte I have a feeling that I'm doing this in the wrong way.
wire [7:0] data_reg = addr_reg[1:0] == 2'd1 ? data_buf[7:0] :
(addr_reg[1:0] == 2'd2 ? data_buf[15:8] :
(addr_reg[1:0] == 2'd3 ? data_buf[23:16] :
data_buf[31:24]));
wire [7:0] EPP_data_mux = data_reg;
assign EPP_dataout = (EPP_read & EPP_wait) ? EPP_data_mux : 8'hZZ;
assign do_enable_wdt = EPP_strobe_edge1 & EPP_write & EPP_data_strobe & (addr_reg[3:0] == 4'd9) & EPP_datain[6];
assign qr0 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd0);
assign qr1 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd1);
assign qr2 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd2);
assign qr3 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd3);
assign led = do_tristate ? 1'BZ : (real_up[0] ^ real_down[0]);
assign nConfig = epp_nReset; // 1'b1;
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// d_parallel_FFM_gate_GF12.v for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: BCH Page Decoder
// Module Name: d_parallel_FFM_gate_GF12
// File Name: d_parallel_FFM_gate_GF12.v
//
// Version: v2.0.2-GF12tB
//
// Description:
// - parallel Finite Field Multiplier (FFM) module
// - 2 polynomial form input, 1 polynomial form output
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v2.0.2
// - minor modification for releasing
//
// * v2.0.1
// - re-factoring
//
// * v2.0.0
// - based on partial multiplication
// - fixed GF
//
// * v1.0.0
// - based on LFSR
// - variable GF by parameter setting
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module d_parallel_FFM_gate_GF12
(
input wire [11: 0] i_poly_form_A, // input term A, polynomial form
input wire [11: 0] i_poly_form_B, // input term B, polynomial form
output wire [11: 0] o_poly_form_result // output term result, polynomial form
);
///////////////////////////////////////////////////////////
// CAUTION! CAUTION! CAUTION! CAUTION! CAUTION! CAUTION! //
// //
// ONLY FOR 12 BIT POLYNOMIAL MULTIPLICATION //
// //
// CAUTION! CAUTION! CAUTION! CAUTION! CAUTION! CAUTION! //
///////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////
// CAUTION! CAUTION! CAUTION! CAUTION! CAUTION! CAUTION! //
// //
// PRIMITIVE POLYNOMIAL //
// P(X) = X^12 + X^7 + X^4 + X^3 + 1 //
// //
// CAUTION! CAUTION! CAUTION! CAUTION! CAUTION! CAUTION! //
///////////////////////////////////////////////////////////
wire [11: 6] w_p_A1; // partial term A1
wire [ 5: 0] w_p_A0; // partial term A0
wire [11: 6] w_p_B1; // partial term B1
wire [ 5: 0] w_p_B0; // partial term B0
wire [16: 6] w_p_r_A1_B0; // partial multiplication result A1*B0
wire [10: 0] w_p_r_A0_B0; // partial multiplication result A0*B0
wire [22:12] w_p_r_A1_B1; // partial multiplication result A1*B1
wire [16: 6] w_p_r_A0_B1; // partial multiplication result A0*B1
wire [22: 0] w_p_r_sum; // multiplication result
assign w_p_A1[11: 6] = i_poly_form_A[11: 6];
assign w_p_A0[ 5: 0] = i_poly_form_A[ 5: 0];
assign w_p_B1[11: 6] = i_poly_form_B[11: 6];
assign w_p_B0[ 5: 0] = i_poly_form_B[ 5: 0];
// multipliers for partial multiplication
d_partial_FFM_gate_6b p_mul_A1_B0 (
.i_a(w_p_A1[11: 6]),
.i_b(w_p_B0[ 5: 0]),
.o_r(w_p_r_A1_B0[16: 6]));
d_partial_FFM_gate_6b p_mul_A0_B0 (
.i_a(w_p_A0[ 5: 0]),
.i_b(w_p_B0[ 5: 0]),
.o_r(w_p_r_A0_B0[10: 0]));
d_partial_FFM_gate_6b p_mul_A1_B1 (
.i_a(w_p_A1[11: 6]),
.i_b(w_p_B1[11: 6]),
.o_r(w_p_r_A1_B1[22:12]));
d_partial_FFM_gate_6b p_mul_A0_B1 (
.i_a(w_p_A0[ 5: 0]),
.i_b(w_p_B1[11: 6]),
.o_r(w_p_r_A0_B1[16: 6]));
// sum partial results
assign w_p_r_sum[22:17] = w_p_r_A1_B1[22:17];
assign w_p_r_sum[16:12] = w_p_r_A1_B1[16:12] ^ w_p_r_A0_B1[16:12] ^ w_p_r_A1_B0[16:12];
assign w_p_r_sum[11] = w_p_r_A0_B1[11] ^ w_p_r_A1_B0[11];
assign w_p_r_sum[10: 6] = w_p_r_A0_B1[10: 6] ^ w_p_r_A1_B0[10: 6] ^ w_p_r_A0_B0[10: 6];
assign w_p_r_sum[ 5: 0] = w_p_r_A0_B0[ 5: 0];
// reduce high order terms
assign o_poly_form_result[11] = w_p_r_sum[11] ^ w_p_r_sum[16] ^ w_p_r_sum[19] ^ w_p_r_sum[20] ^ w_p_r_sum[21];
assign o_poly_form_result[10] = w_p_r_sum[10] ^ w_p_r_sum[15] ^ w_p_r_sum[18] ^ w_p_r_sum[19] ^ w_p_r_sum[20] ^ w_p_r_sum[22];
assign o_poly_form_result[ 9] = w_p_r_sum[ 9] ^ w_p_r_sum[14] ^ w_p_r_sum[17] ^ w_p_r_sum[18] ^ w_p_r_sum[19] ^ w_p_r_sum[21];
assign o_poly_form_result[ 8] = w_p_r_sum[ 8] ^ w_p_r_sum[13] ^ w_p_r_sum[16] ^ w_p_r_sum[17] ^ w_p_r_sum[18] ^ w_p_r_sum[20];
assign o_poly_form_result[ 7] = w_p_r_sum[ 7] ^ w_p_r_sum[12] ^ w_p_r_sum[15] ^ w_p_r_sum[16] ^ w_p_r_sum[17] ^ w_p_r_sum[19] ^ w_p_r_sum[22];
assign o_poly_form_result[ 6] = w_p_r_sum[ 6] ^ w_p_r_sum[14] ^ w_p_r_sum[15] ^ w_p_r_sum[18] ^ w_p_r_sum[19] ^ w_p_r_sum[20] ^ w_p_r_sum[22];
assign o_poly_form_result[ 5] = w_p_r_sum[ 5] ^ w_p_r_sum[13] ^ w_p_r_sum[14] ^ w_p_r_sum[17] ^ w_p_r_sum[18] ^ w_p_r_sum[19] ^ w_p_r_sum[21] ^ w_p_r_sum[22];
assign o_poly_form_result[ 4] = w_p_r_sum[ 4] ^ w_p_r_sum[12] ^ w_p_r_sum[13] ^ w_p_r_sum[16] ^ w_p_r_sum[17] ^ w_p_r_sum[18] ^ w_p_r_sum[20] ^ w_p_r_sum[21];
assign o_poly_form_result[ 3] = w_p_r_sum[ 3] ^ w_p_r_sum[12] ^ w_p_r_sum[15] ^ w_p_r_sum[17] ^ w_p_r_sum[21] ^ w_p_r_sum[22];
assign o_poly_form_result[ 2] = w_p_r_sum[ 2] ^ w_p_r_sum[14] ^ w_p_r_sum[19] ^ w_p_r_sum[22];
assign o_poly_form_result[ 1] = w_p_r_sum[ 1] ^ w_p_r_sum[13] ^ w_p_r_sum[18] ^ w_p_r_sum[21] ^ w_p_r_sum[22];
assign o_poly_form_result[ 0] = w_p_r_sum[ 0] ^ w_p_r_sum[12] ^ w_p_r_sum[17] ^ w_p_r_sum[20] ^ w_p_r_sum[21] ^ w_p_r_sum[22];
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2017 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file constants_mem.v when simulating
// the core, constants_mem. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module constants_mem(
clka,
addra,
douta
);
input clka;
input [9 : 0] addra;
output [7 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(10),
.C_ADDRB_WIDTH(10),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(1),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(1),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("constants_mem.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(1024),
.C_READ_DEPTH_B(1024),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(1),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(1024),
.C_WRITE_DEPTH_B(1024),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:15:08 08/27/2015
// Design Name:
// Module Name: Tenth_Phase
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Tenth_Phase
//Module Parameters
/***SINGLE PRECISION***/
// W = 32
// EW = 8
// SW = 23
/***DOUBLE PRECISION***/
// W = 64
// EW = 11
// SW = 52
# (parameter W = 32, parameter EW = 8, parameter SW = 23)
// # (parameter W = 64, parameter EW = 11, parameter SW = 52)
(
//INPUTS
input wire clk, //Clock Signal
input wire rst, //Reset Signal
input wire load_i,
input wire sel_a_i, //Overflow/add/subt result's mux's selector
input wire sel_b_i, //underflow/add/subt result's mux's selector
input wire sign_i, //Sign of the largest Operand
input wire [EW-1:0] exp_ieee_i, //Final Exponent
input wire [SW-1:0] sgf_ieee_i,//Final Significand
//OUTPUTS
output wire [W-1:0] final_result_ieee_o //Final Result
);
//Wire Connection signals
wire [SW-1:0] Sgf_S_mux;
wire [EW-1:0] Exp_S_mux;
wire Sign_S_mux;
wire [W-1:0] final_result_reg;
wire overunder;
wire [EW-1:0] exp_mux_D1;
wire [SW-1:0] sgf_mux_D1;
//////////////////////////////////////////////////////////
assign overunder = sel_a_i | sel_b_i;
Mux_3x1 #(.W(1)) Sign_Mux (
.ctrl({sel_a_i,sel_b_i}),
.D0(sign_i),
.D1(1'b1),
.D2(1'b0),
.S(Sign_S_mux)
);
Multiplexer_AC #(.W(EW)) Exp_Mux (
.ctrl(overunder),
.D0(exp_ieee_i),
.D1(exp_mux_D1),
.S(Exp_S_mux)
);
Multiplexer_AC #(.W(SW)) Sgf_Mux (
.ctrl(overunder),
.D0(sgf_ieee_i),
.D1(sgf_mux_D1),
.S(Sgf_S_mux)
);
/////////////////////////////////////////////////////////
generate
if(W == 32) begin
assign exp_mux_D1 =8'hff;
assign sgf_mux_D1 =23'd0;
end
else begin
assign exp_mux_D1 =11'hfff;
assign sgf_mux_D1 =52'd0;
end
endgenerate
////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
RegisterAdd #(.W(W)) Final_Result_IEEE (
.clk(clk),
.rst(rst),
.load(load_i),
.D({Sign_S_mux,Exp_S_mux,Sgf_S_mux}),
.Q(final_result_ieee_o)
);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module s_axi_top # (
parameter C_S0_AXI_ADDR_WIDTH = 32,
parameter C_S0_AXI_DATA_WIDTH = 32,
parameter C_S0_AXI_BASEADDR = 32'h80000000,
parameter C_S0_AXI_HIGHADDR = 32'h80010000,
parameter C_M0_AXI_ADDR_WIDTH = 32,
parameter C_M0_AXI_DATA_WIDTH = 64,
parameter C_M0_AXI_ID_WIDTH = 1,
parameter C_M0_AXI_AWUSER_WIDTH = 1,
parameter C_M0_AXI_WUSER_WIDTH = 1,
parameter C_M0_AXI_BUSER_WIDTH = 1,
parameter C_M0_AXI_ARUSER_WIDTH = 1,
parameter C_M0_AXI_RUSER_WIDTH = 1,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
////////////////////////////////////////////////////////////////
//AXI4-lite slave interface signals
input s0_axi_aclk,
input s0_axi_aresetn,
//Write address channel
input [C_S0_AXI_ADDR_WIDTH-1:0] s0_axi_awaddr,
output s0_axi_awready,
input s0_axi_awvalid,
input [2:0] s0_axi_awprot,
//Write data channel
input s0_axi_wvalid,
output s0_axi_wready,
input [C_S0_AXI_DATA_WIDTH-1 :0] s0_axi_wdata,
input [(C_S0_AXI_DATA_WIDTH/8)-1:0] s0_axi_wstrb,
//Write response channel
output s0_axi_bvalid,
input s0_axi_bready,
output [1:0] s0_axi_bresp,
//Read address channel
input s0_axi_arvalid,
output s0_axi_arready,
input [C_S0_AXI_ADDR_WIDTH-1:0] s0_axi_araddr,
input [2:0] s0_axi_arprot,
//Read data channel
output s0_axi_rvalid,
input s0_axi_rready,
output [C_S0_AXI_DATA_WIDTH-1:0] s0_axi_rdata,
output [1:0] s0_axi_rresp,
output dev_irq_assert,
output pcie_user_logic_rst,
input nvme_cc_en,
input [1:0] nvme_cc_shn,
output [1:0] nvme_csts_shst,
output nvme_csts_rdy,
output [8:0] sq_valid,
output [7:0] io_sq1_size,
output [7:0] io_sq2_size,
output [7:0] io_sq3_size,
output [7:0] io_sq4_size,
output [7:0] io_sq5_size,
output [7:0] io_sq6_size,
output [7:0] io_sq7_size,
output [7:0] io_sq8_size,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq1_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq2_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq3_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq4_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq5_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq6_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq7_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq8_bs_addr,
output [3:0] io_sq1_cq_vec,
output [3:0] io_sq2_cq_vec,
output [3:0] io_sq3_cq_vec,
output [3:0] io_sq4_cq_vec,
output [3:0] io_sq5_cq_vec,
output [3:0] io_sq6_cq_vec,
output [3:0] io_sq7_cq_vec,
output [3:0] io_sq8_cq_vec,
output [8:0] cq_valid,
output [7:0] io_cq1_size,
output [7:0] io_cq2_size,
output [7:0] io_cq3_size,
output [7:0] io_cq4_size,
output [7:0] io_cq5_size,
output [7:0] io_cq6_size,
output [7:0] io_cq7_size,
output [7:0] io_cq8_size,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq1_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq2_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq3_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq4_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq5_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq6_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq7_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq8_bs_addr,
output [8:0] io_cq_irq_en,
output [2:0] io_cq1_iv,
output [2:0] io_cq2_iv,
output [2:0] io_cq3_iv,
output [2:0] io_cq4_iv,
output [2:0] io_cq5_iv,
output [2:0] io_cq6_iv,
output [2:0] io_cq7_iv,
output [2:0] io_cq8_iv,
output hcmd_sq_rd_en,
input [18:0] hcmd_sq_rd_data,
input hcmd_sq_empty_n,
output [10:0] hcmd_table_rd_addr,
input [31:0] hcmd_table_rd_data,
output hcmd_cq_wr1_en,
output [34:0] hcmd_cq_wr1_data0,
output [34:0] hcmd_cq_wr1_data1,
input hcmd_cq_wr1_rdy_n,
output dma_cmd_wr_en,
output [49:0] dma_cmd_wr_data0,
output [49:0] dma_cmd_wr_data1,
input dma_cmd_wr_rdy_n,
input pcie_mreq_err,
input pcie_cpld_err,
input pcie_cpld_len_err,
////////////////////////////////////////////////////////////////
//AXI4 master interface signals
input m0_axi_aclk,
input m0_axi_aresetn,
// Write address channel
output [C_M0_AXI_ID_WIDTH-1:0] m0_axi_awid,
output [C_M0_AXI_ADDR_WIDTH-1:0] m0_axi_awaddr,
output [7:0] m0_axi_awlen,
output [2:0] m0_axi_awsize,
output [1:0] m0_axi_awburst,
output [1:0] m0_axi_awlock,
output [3:0] m0_axi_awcache,
output [2:0] m0_axi_awprot,
output [3:0] m0_axi_awregion,
output [3:0] m0_axi_awqos,
output [C_M0_AXI_AWUSER_WIDTH-1:0] m0_axi_awuser,
output m0_axi_awvalid,
input m0_axi_awready,
// Write data channel
output [C_M0_AXI_ID_WIDTH-1:0] m0_axi_wid,
output [C_M0_AXI_DATA_WIDTH-1:0] m0_axi_wdata,
output [(C_M0_AXI_DATA_WIDTH/8)-1:0] m0_axi_wstrb,
output m0_axi_wlast,
output [C_M0_AXI_WUSER_WIDTH-1:0] m0_axi_wuser,
output m0_axi_wvalid,
input m0_axi_wready,
// Write response channel
input [C_M0_AXI_ID_WIDTH-1:0] m0_axi_bid,
input [1:0] m0_axi_bresp,
input m0_axi_bvalid,
input [C_M0_AXI_BUSER_WIDTH-1:0] m0_axi_buser,
output m0_axi_bready,
// Read address channel
output [C_M0_AXI_ID_WIDTH-1:0] m0_axi_arid,
output [C_M0_AXI_ADDR_WIDTH-1:0] m0_axi_araddr,
output [7:0] m0_axi_arlen,
output [2:0] m0_axi_arsize,
output [1:0] m0_axi_arburst,
output [1:0] m0_axi_arlock,
output [3:0] m0_axi_arcache,
output [2:0] m0_axi_arprot,
output [3:0] m0_axi_arregion,
output [3:0] m0_axi_arqos,
output [C_M0_AXI_ARUSER_WIDTH-1:0] m0_axi_aruser,
output m0_axi_arvalid,
input m0_axi_arready,
// Read data channel
input [C_M0_AXI_ID_WIDTH-1:0] m0_axi_rid,
input [C_M0_AXI_DATA_WIDTH-1:0] m0_axi_rdata,
input [1:0] m0_axi_rresp,
input m0_axi_rlast,
input [C_M0_AXI_RUSER_WIDTH-1:0] m0_axi_ruser,
input m0_axi_rvalid,
output m0_axi_rready,
output pcie_rx_fifo_rd_en,
input [C_M0_AXI_DATA_WIDTH-1:0] pcie_rx_fifo_rd_data,
output pcie_rx_fifo_free_en,
output [9:4] pcie_rx_fifo_free_len,
input pcie_rx_fifo_empty_n,
output pcie_tx_fifo_alloc_en,
output [9:4] pcie_tx_fifo_alloc_len,
output pcie_tx_fifo_wr_en,
output [C_M0_AXI_DATA_WIDTH-1:0] pcie_tx_fifo_wr_data,
input pcie_tx_fifo_full_n,
output dma_rx_done_wr_en,
output [20:0] dma_rx_done_wr_data,
input dma_rx_done_wr_rdy_n,
input pcie_user_clk,
input pcie_user_rst_n,
input dev_rx_cmd_wr_en,
input [29:0] dev_rx_cmd_wr_data,
output dev_rx_cmd_full_n,
input dev_tx_cmd_wr_en,
input [29:0] dev_tx_cmd_wr_data,
output dev_tx_cmd_full_n,
input [7:0] dma_rx_direct_done_cnt,
input [7:0] dma_tx_direct_done_cnt,
input [7:0] dma_rx_done_cnt,
input [7:0] dma_tx_done_cnt,
input pcie_link_up,
input [5:0] pl_ltssm_state,
input [15:0] cfg_command,
input [2:0] cfg_interrupt_mmenable,
input cfg_interrupt_msienable,
input cfg_interrupt_msixenable
);
wire w_m0_axi_bresp_err;
wire w_m0_axi_rresp_err;
s_axi_reg # (
.C_S_AXI_ADDR_WIDTH (C_S0_AXI_ADDR_WIDTH),
.C_S_AXI_DATA_WIDTH (C_S0_AXI_DATA_WIDTH),
.C_S_AXI_BASEADDR (C_S0_AXI_BASEADDR),
.C_S_AXI_HIGHADDR (C_S0_AXI_HIGHADDR)
)
s_axi_reg_inst0 (
////////////////////////////////////////////////////////////////
//AXI4-lite slave interface signals
.s_axi_aclk (s0_axi_aclk),
.s_axi_aresetn (s0_axi_aresetn),
//Write address channel
.s_axi_awaddr (s0_axi_awaddr),
.s_axi_awready (s0_axi_awready),
.s_axi_awvalid (s0_axi_awvalid),
.s_axi_awprot (s0_axi_awprot),
//Write data channel
.s_axi_wvalid (s0_axi_wvalid),
.s_axi_wready (s0_axi_wready),
.s_axi_wdata (s0_axi_wdata),
.s_axi_wstrb (s0_axi_wstrb),
//Write response channel
.s_axi_bvalid (s0_axi_bvalid),
.s_axi_bready (s0_axi_bready),
.s_axi_bresp (s0_axi_bresp),
//Read address channel
.s_axi_arvalid (s0_axi_arvalid),
.s_axi_arready (s0_axi_arready),
.s_axi_araddr (s0_axi_araddr),
.s_axi_arprot (s0_axi_arprot),
//Read data channel
.s_axi_rvalid (s0_axi_rvalid),
.s_axi_rready (s0_axi_rready),
.s_axi_rdata (s0_axi_rdata),
.s_axi_rresp (s0_axi_rresp),
.pcie_mreq_err (pcie_mreq_err),
.pcie_cpld_err (pcie_cpld_err),
.pcie_cpld_len_err (pcie_cpld_len_err),
.m0_axi_bresp_err (w_m0_axi_bresp_err),
.m0_axi_rresp_err (w_m0_axi_rresp_err),
.dev_irq_assert (dev_irq_assert),
.pcie_user_logic_rst (pcie_user_logic_rst),
.nvme_cc_en (nvme_cc_en),
.nvme_cc_shn (nvme_cc_shn),
.nvme_csts_shst (nvme_csts_shst),
.nvme_csts_rdy (nvme_csts_rdy),
.sq_valid (sq_valid),
.io_sq1_size (io_sq1_size),
.io_sq2_size (io_sq2_size),
.io_sq3_size (io_sq3_size),
.io_sq4_size (io_sq4_size),
.io_sq5_size (io_sq5_size),
.io_sq6_size (io_sq6_size),
.io_sq7_size (io_sq7_size),
.io_sq8_size (io_sq8_size),
.io_sq1_bs_addr (io_sq1_bs_addr),
.io_sq2_bs_addr (io_sq2_bs_addr),
.io_sq3_bs_addr (io_sq3_bs_addr),
.io_sq4_bs_addr (io_sq4_bs_addr),
.io_sq5_bs_addr (io_sq5_bs_addr),
.io_sq6_bs_addr (io_sq6_bs_addr),
.io_sq7_bs_addr (io_sq7_bs_addr),
.io_sq8_bs_addr (io_sq8_bs_addr),
.io_sq1_cq_vec (io_sq1_cq_vec),
.io_sq2_cq_vec (io_sq2_cq_vec),
.io_sq3_cq_vec (io_sq3_cq_vec),
.io_sq4_cq_vec (io_sq4_cq_vec),
.io_sq5_cq_vec (io_sq5_cq_vec),
.io_sq6_cq_vec (io_sq6_cq_vec),
.io_sq7_cq_vec (io_sq7_cq_vec),
.io_sq8_cq_vec (io_sq8_cq_vec),
.cq_valid (cq_valid),
.io_cq1_size (io_cq1_size),
.io_cq2_size (io_cq2_size),
.io_cq3_size (io_cq3_size),
.io_cq4_size (io_cq4_size),
.io_cq5_size (io_cq5_size),
.io_cq6_size (io_cq6_size),
.io_cq7_size (io_cq7_size),
.io_cq8_size (io_cq8_size),
.io_cq1_bs_addr (io_cq1_bs_addr),
.io_cq2_bs_addr (io_cq2_bs_addr),
.io_cq3_bs_addr (io_cq3_bs_addr),
.io_cq4_bs_addr (io_cq4_bs_addr),
.io_cq5_bs_addr (io_cq5_bs_addr),
.io_cq6_bs_addr (io_cq6_bs_addr),
.io_cq7_bs_addr (io_cq7_bs_addr),
.io_cq8_bs_addr (io_cq8_bs_addr),
.io_cq_irq_en (io_cq_irq_en),
.io_cq1_iv (io_cq1_iv),
.io_cq2_iv (io_cq2_iv),
.io_cq3_iv (io_cq3_iv),
.io_cq4_iv (io_cq4_iv),
.io_cq5_iv (io_cq5_iv),
.io_cq6_iv (io_cq6_iv),
.io_cq7_iv (io_cq7_iv),
.io_cq8_iv (io_cq8_iv),
.hcmd_sq_rd_en (hcmd_sq_rd_en),
.hcmd_sq_rd_data (hcmd_sq_rd_data),
.hcmd_sq_empty_n (hcmd_sq_empty_n),
.hcmd_table_rd_addr (hcmd_table_rd_addr),
.hcmd_table_rd_data (hcmd_table_rd_data),
.hcmd_cq_wr1_en (hcmd_cq_wr1_en),
.hcmd_cq_wr1_data0 (hcmd_cq_wr1_data0),
.hcmd_cq_wr1_data1 (hcmd_cq_wr1_data1),
.hcmd_cq_wr1_rdy_n (hcmd_cq_wr1_rdy_n),
.dma_cmd_wr_en (dma_cmd_wr_en),
.dma_cmd_wr_data0 (dma_cmd_wr_data0),
.dma_cmd_wr_data1 (dma_cmd_wr_data1),
.dma_cmd_wr_rdy_n (dma_cmd_wr_rdy_n),
.dma_rx_direct_done_cnt (dma_rx_direct_done_cnt),
.dma_tx_direct_done_cnt (dma_tx_direct_done_cnt),
.dma_rx_done_cnt (dma_rx_done_cnt),
.dma_tx_done_cnt (dma_tx_done_cnt),
.pcie_link_up (pcie_link_up),
.pl_ltssm_state (pl_ltssm_state),
.cfg_command (cfg_command),
.cfg_interrupt_mmenable (cfg_interrupt_mmenable),
.cfg_interrupt_msienable (cfg_interrupt_msienable),
.cfg_interrupt_msixenable (cfg_interrupt_msixenable)
);
m_axi_dma # (
.C_M_AXI_ADDR_WIDTH (C_M0_AXI_ADDR_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M0_AXI_DATA_WIDTH),
.C_M_AXI_ID_WIDTH (C_M0_AXI_ID_WIDTH),
.C_M_AXI_AWUSER_WIDTH (C_M0_AXI_AWUSER_WIDTH),
.C_M_AXI_WUSER_WIDTH (C_M0_AXI_WUSER_WIDTH),
.C_M_AXI_BUSER_WIDTH (C_M0_AXI_BUSER_WIDTH),
.C_M_AXI_ARUSER_WIDTH (C_M0_AXI_ARUSER_WIDTH),
.C_M_AXI_RUSER_WIDTH (C_M0_AXI_RUSER_WIDTH)
)
m_axi_dma_inst0(
////////////////////////////////////////////////////////////////
//AXI4 master interface signals
.m_axi_aclk (m0_axi_aclk),
.m_axi_aresetn (m0_axi_aresetn),
// Write address channel
.m_axi_awid (m0_axi_awid),
.m_axi_awaddr (m0_axi_awaddr),
.m_axi_awlen (m0_axi_awlen),
.m_axi_awsize (m0_axi_awsize),
.m_axi_awburst (m0_axi_awburst),
.m_axi_awlock (m0_axi_awlock),
.m_axi_awcache (m0_axi_awcache),
.m_axi_awprot (m0_axi_awprot),
.m_axi_awregion (m0_axi_awregion),
.m_axi_awqos (m0_axi_awqos),
.m_axi_awuser (m0_axi_awuser),
.m_axi_awvalid (m0_axi_awvalid),
.m_axi_awready (m0_axi_awready),
// Write data channel
.m_axi_wid (m0_axi_wid),
.m_axi_wdata (m0_axi_wdata),
.m_axi_wstrb (m0_axi_wstrb),
.m_axi_wlast (m0_axi_wlast),
.m_axi_wuser (m0_axi_wuser),
.m_axi_wvalid (m0_axi_wvalid),
.m_axi_wready (m0_axi_wready),
// Write response channel
.m_axi_bid (m0_axi_bid),
.m_axi_bresp (m0_axi_bresp),
.m_axi_bvalid (m0_axi_bvalid),
.m_axi_buser (m0_axi_buser),
.m_axi_bready (m0_axi_bready),
// Read address channel
.m_axi_arid (m0_axi_arid),
.m_axi_araddr (m0_axi_araddr),
.m_axi_arlen (m0_axi_arlen),
.m_axi_arsize (m0_axi_arsize),
.m_axi_arburst (m0_axi_arburst),
.m_axi_arlock (m0_axi_arlock),
.m_axi_arcache (m0_axi_arcache),
.m_axi_arprot (m0_axi_arprot),
.m_axi_arregion (m0_axi_arregion),
.m_axi_arqos (m0_axi_arqos),
.m_axi_aruser (m0_axi_aruser),
.m_axi_arvalid (m0_axi_arvalid),
.m_axi_arready (m0_axi_arready),
// Read data channel
.m_axi_rid (m0_axi_rid),
.m_axi_rdata (m0_axi_rdata),
.m_axi_rresp (m0_axi_rresp),
.m_axi_rlast (m0_axi_rlast),
.m_axi_ruser (m0_axi_ruser),
.m_axi_rvalid (m0_axi_rvalid),
.m_axi_rready (m0_axi_rready),
.m_axi_bresp_err (w_m0_axi_bresp_err),
.m_axi_rresp_err (w_m0_axi_rresp_err),
.pcie_rx_fifo_rd_en (pcie_rx_fifo_rd_en),
.pcie_rx_fifo_rd_data (pcie_rx_fifo_rd_data),
.pcie_rx_fifo_free_en (pcie_rx_fifo_free_en),
.pcie_rx_fifo_free_len (pcie_rx_fifo_free_len),
.pcie_rx_fifo_empty_n (pcie_rx_fifo_empty_n),
.pcie_tx_fifo_alloc_en (pcie_tx_fifo_alloc_en),
.pcie_tx_fifo_alloc_len (pcie_tx_fifo_alloc_len),
.pcie_tx_fifo_wr_en (pcie_tx_fifo_wr_en),
.pcie_tx_fifo_wr_data (pcie_tx_fifo_wr_data),
.pcie_tx_fifo_full_n (pcie_tx_fifo_full_n),
.dma_rx_done_wr_en (dma_rx_done_wr_en),
.dma_rx_done_wr_data (dma_rx_done_wr_data),
.dma_rx_done_wr_rdy_n (dma_rx_done_wr_rdy_n),
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.dev_rx_cmd_wr_en (dev_rx_cmd_wr_en),
.dev_rx_cmd_wr_data (dev_rx_cmd_wr_data),
.dev_rx_cmd_full_n (dev_rx_cmd_full_n),
.dev_tx_cmd_wr_en (dev_tx_cmd_wr_en),
.dev_tx_cmd_wr_data (dev_tx_cmd_wr_data),
.dev_tx_cmd_full_n (dev_tx_cmd_full_n)
);
endmodule |
/*
* University of Illinois/NCSA
* Open Source License
*
* Copyright (c) 2007-2014,The Board of Trustees of the University of
* Illinois. All rights reserved.
*
* Copyright (c) 2014 Matthew Hicks
*
* Developed by:
*
* Matthew Hicks in the Department of Computer Science
* The University of Illinois at Urbana-Champaign
* http://www.impedimentToProgress.com
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated
* documentation files (the "Software"), to deal with the
* Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute,
* sublicense, and/or sell copies of the Software, and to permit
* persons to whom the Software is furnished to do so, subject
* to the following conditions:
*
* Redistributions of source code must retain the above
* copyright notice, this list of conditions and the
* following disclaimers.
*
* Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the
* following disclaimers in the documentation and/or other
* materials provided with the distribution.
*
* Neither the names of Sam King, the University of Illinois,
* nor the names of its contributors may be used to endorse
* or promote products derived from this Software without
* specific prior written permission.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE CONTRIBUTORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS WITH THE SOFTWARE.
*/
`include "or1200_defines.v"
`define OR1200_OPCODE_MASK 32'hFC000000
`define OR1200_TARGET_MASK 32'h03E00000
`define OR1200_K_MASK 32'h000007FF
`define OR1200_EXCEPTION_VECTOR_UNMASK 32'hFFFFF0FF
module BakedInAssertions(
clk, rst, enable,
ex_pc, ex_insn, spr_dat_ppc, spr_dat_npc,
eear, sr,esr, epcr,
immu_sxe, immu_uxe, immu_en,
gpr_written_to, gpr_written_addr, gpr_written_data,
dcpu_adr_o, dcpu_dat_i, operand_b,
checkersFired
);
input clk;
input rst;
input enable;
input [31:0] ex_pc;
input [31:0] ex_insn;
input [31:0] spr_dat_ppc;
input [31:0] spr_dat_npc;
input [31:0] eear;
input [`OR1200_SR_WIDTH-1:0] sr;
input [`OR1200_SR_WIDTH-1:0] esr;
input [31:0] epcr;
input immu_sxe;
input immu_uxe;
input immu_en;
input gpr_written_to;
input [4:0] gpr_written_addr;
input [31:0] gpr_written_data;
input [31:0] dcpu_adr_o;
input [31:0] dcpu_dat_i;
input [31:0] operand_b;
output [31:0] checkersFired;
// Checker 1 - IPage priv matches execution mode of the processor
wire checker_1_1;
wire checker_1_2;
wire checker_1_3;
wire checker_1_4;
wire checker_1_5;
wire checker_1 = (checker_1_1 | checker_1_2) & (checker_1_3 | checker_1_4) & checker_1_5;
ovl_always_wrapped oaw_1_1(
.clk(clk),
.rst(rst),
.enable(enable),
.test_expr(sr[`OR1200_SR_SM] == 1'b1),
.prevConfigInvalid(1'b0),
.out(checker_1_1)
);
ovl_always_wrapped oaw_1_2(
.clk(clk),
.rst(rst),
.enable(enable & immu_en),
.test_expr(immu_sxe == 1'b1),
.prevConfigInvalid(1'b0),
.out(checker_1_2)
);
ovl_always_wrapped oaw_1_3(
.clk(clk),
.rst(rst),
.enable(enable),
.test_expr(sr[`OR1200_SR_SM] == 1'b0),
.prevConfigInvalid(1'b0),
.out(checker_1_3)
);
ovl_always_wrapped oaw_1_4(
.clk(clk),
.rst(rst),
.enable(enable & immu_en),
.test_expr(immu_uxe == 1'b1),
.prevConfigInvalid(1'b0),
.out(checker_1_4)
);
ovl_always_wrapped oaw_1_5(
.clk(clk),
.rst(rst),
.enable(enable),
.test_expr(immu_en == 1'b0),
.prevConfigInvalid(1'b0),
.out(checker_1_5)
);
// Checker 3 - Corrcet backup of registers on exception
wire checker_3_1;
wire checker_3_2;
wire checker_3_3a;
wire checker_3_3b;
reg checker_3_3b_1;
wire checker_3_3c;
wire checker_3_4;
wire checker_3_5;
wire checker_3_5b;
wire checker_3_6;
wire checker_3_7;
wire checker_3 = checker_3_1 | checker_3_2 | (checker_3_3a & checker_3_3b_1 & checker_3_3c) | ((checker_3_4 | (checker_3_5 & checker_3_5b)) & (checker_3_6 | checker_3_7));
reg [31:0] checker_3_counter;
reg [31:0] insn_counter;
always @(posedge clk)begin
if(rst == `OR1200_RST_VALUE)begin
insn_counter <= 32'h0;
checker_3_counter <= 32'h0;
end
else if(enable)begin
insn_counter <= insn_counter + 1'h1;
checker_3_counter <= checker_3 ? checker_3_counter + 1'h1 : checker_3_counter;
end
end
// Verify that the correct EEAR is saved
// Need an assertion for each different class (wrt EEAR value source) of exception
// Page faults not implemented, so no need to protect those
// I/D TLB misses need protection
// Address of first insn in a basic block is unknowable at the isa level = false positives
ovl_always_on_edge_wrapped oaoew3_1(
.clk(clk),
.rst(rst),
.enable(enable),
.sampling_event(ex_pc == 32'h00000A00),
.test_expr(eear == spr_dat_npc),
.prevConfigInvalid(1'b0),
.out(checker_3_1)
);
/* Needs micro-arch access
ovl_always_on_edge_wrapped oaoew3_2(
.clk(clk),
.rst(rst),
.enable(enable),
.sampling_event(ex_pc == 32'h00000900),
.test_expr(eear == dcpu_adr_o),
.prevConfigInvalid(1'b0),
.out(checker_3_2)
);*/
assign checker_3_2 = 0;
// Verify that ESR takes the correct value given SR
always @(posedge clk)begin
if(rst == `OR1200_RST_VALUE)begin
checker_3_3b_1 <= 1'b0;
end else begin
checker_3_3b_1 <= checker_3_3b;
end
end
ovl_always_on_edge_wrapped oaoew3_3a(
.clk(clk),
.rst(rst),
.enable(enable),
.sampling_event((ex_pc & `OR1200_EXCEPTION_VECTOR_UNMASK) == 32'h0),
.test_expr(1'b0),
.prevConfigInvalid(1'b0),
.out(checker_3_3a)
);
ovl_always_wrapped oaw3_3b(
.clk(clk),
.rst(rst),
.enable(enable),
.test_expr(sr[0] == 1'b1),
.prevConfigInvalid(1'b0),
.out(checker_3_3b)
);
ovl_always_wrapped oaw3_3c(
.clk(clk),
.rst(rst),
.enable(enable),
.test_expr(esr[0] == 1'b0),
.prevConfigInvalid(1'b0),
.out(checker_3_3c)
);
// Verify that EPCR gets the correct (delay slot dependant) PC
ovl_always_wrapped oaw_3_4(
.clk(clk),
.rst(rst),
.enable(enable),
.test_expr(sr[`OR1200_SR_DSX] == 1'b0),
.prevConfigInvalid(1'b0),
.out(checker_3_4)
);
// Fires when EPCR != next PC
ovl_always_on_edge_wrapped oaoew3_5(
.clk(clk),
.rst(rst),
.enable(enable),
.sampling_event((ex_pc & `OR1200_EXCEPTION_VECTOR_UNMASK) == 32'h0),
.test_expr(epcr == spr_dat_ppc+32'h4),
.prevConfigInvalid(1'b0),
.out(checker_3_5)
);
ovl_always_on_edge_wrapped oaoew3_5b(
.clk(clk),
.rst(rst),
.enable(enable),
.sampling_event(ex_pc == 32'h00000A00),
.test_expr(epcr == spr_dat_npc),
.prevConfigInvalid(1'b0),
.out(checker_3_5b)
);
ovl_always_wrapped oaw_3_6(
.clk(clk),
.rst(rst),
.enable(enable),
.test_expr(sr[`OR1200_SR_DSX] == 1'b1),
.prevConfigInvalid(1'b0),
.out(checker_3_6)
);
// Fires when EPCR != previous PC
ovl_always_on_edge_wrapped oaoew3_7(
.clk(clk),
.rst(rst),
.enable(enable),
.sampling_event((ex_pc & `OR1200_EXCEPTION_VECTOR_UNMASK) == 32'h0),
.test_expr(epcr == spr_dat_ppc),
.prevConfigInvalid(1'b0),
.out(checker_3_7)
);
// Checker 5 - Data from bus is stored in reg
wire checker_5_1;
wire checker_5_2;
reg [31:0] spec_xor_reg;
wire [31:0] spec_xor_comb = gpr_written_data ^ dcpu_dat_i;
wire spec_xor_comb_one = |spec_xor_comb;
wire spec_xor_reg_one = |spec_xor_reg;
wire spec_xor_small = spec_xor_reg_one & spec_xor_comb_one;
wire checker_5 = checker_5_1 & checker_5_2;
always @(posedge clk)begin
spec_xor_reg <= gpr_written_data ^ dcpu_dat_i;
end
// load
ovl_always_on_edge_wrapped oaoew5_1(
.clk(clk),
.rst(rst),
.enable(enable),
.sampling_event((ex_insn & 32'hF0000000) == 32'h80000000),
.test_expr(~spec_xor_small),
.prevConfigInvalid(1'b0),
.out(checker_5_1)
);
// kick out add immediate signed
ovl_always_wrapped oaw5_2(
.clk(clk),
.rst(rst),
.enable(enable),
.test_expr((ex_insn & `OR1200_OPCODE_MASK) == 32'h8C000000),
.prevConfigInvalid(1'b0),
.out(checker_5_2)
);
// Checker 8
wire checker_8_1;
wire checker_8_2;
wire checker_8 = checker_8_1 & checker_8_2;
ovl_always_on_edge_wrapped oaoew8_1(
.clk(clk),
.rst(rst),
.enable(enable),
.sampling_event(sr[`OR1200_SR_SM]),
.test_expr(rst != 0),
.prevConfigInvalid(1'b0),
.out(checker_8_1)
);
ovl_always_on_edge_wrapped oaoew8_2(
.clk(clk),
.rst(rst),
.enable(enable),
.sampling_event(sr[`OR1200_SR_SM]),
.test_expr((ex_pc & `OR1200_EXCEPTION_VECTOR_UNMASK) == 32'h0),
.prevConfigInvalid(1'b0),
.out(checker_8_2)
);
// Checker 9
wire checker_9_1;
wire checker_9_2;
wire checker_9 = checker_9_1 | checker_9_2;
ovl_always_on_edge_wrapped oaoew9_1(
.clk(clk),
.rst(rst),
.enable(enable),
.sampling_event((ex_insn & `OR1200_OPCODE_MASK) == {`OR1200_OR32_RFE, 26'h0}),
.test_expr(sr[`OR1200_SR_SM] == esr[`OR1200_SR_SM]),
.prevConfigInvalid(1'b0),
.out(checker_9_1)
);
ovl_always_on_edge_wrapped oaoew9_2(
.clk(clk),
.rst(rst),
.enable(enable),
.sampling_event((ex_insn & (`OR1200_OPCODE_MASK | `OR1200_K_MASK)) == {`OR1200_OR32_MTSPR, 15'h0, `OR1200_SPR_SR}),
.test_expr(sr[`OR1200_SR_SM] == operand_b[`OR1200_SR_SM]),
.prevConfigInvalid(1'b0),
.out(checker_9_2)
);
// Checker 13 - Verify control flow
wire checker_13_1;
wire checker_13_2;
reg checker_13_2_1;
reg checker_13_2_2;
wire checker_13_3;
reg checker_13_3_1;
reg checker_13_3_2;
wire checker_13_4;
reg checker_13_4_1;
reg checker_13_4_2;
wire checker_13_5;
reg checker_13_5_1;
wire checker_13_6;
wire checker_13 = checker_13_1 & checker_13_2_1 & checker_13_3_1 & checker_13_4_1 & checker_13_5 & checker_13_6;
// continuous control flow
ovl_delta_wrapped #(
.width(32),
.limit_width(4)
) odw_13_1(
.clk(clk & enable),
.rst(rst),
.min(4'd0),
.max(4'd4),
.test_expr(ex_pc),
.prevConfigInvalid(1'b0),
.out(checker_13_1)
);
// Need to save last two micro assertion results
// One due to to transition, one extra for delay slot
always @(posedge clk)begin
if(rst == `OR1200_RST_VALUE)begin
checker_13_2_1 <= 1'b0;
checker_13_2_2 <= 1'b0;
checker_13_3_1 <= 1'b0;
checker_13_3_2 <= 1'b0;
checker_13_4_1 <= 1'b0;
checker_13_4_2 <= 1'b0;
checker_13_5_1 <= 1'b0;
end else if(enable) begin
checker_13_2_1 <= checker_13_2;
checker_13_2_2 <= checker_13_2_1;
checker_13_3_1 <= checker_13_3;
checker_13_3_2 <= checker_13_3_1;
checker_13_4_1 <= checker_13_4;
checker_13_4_2 <= checker_13_4_1;
checker_13_5_1 <= checker_13_5;
end
end
// jump
ovl_always_wrapped oaw_13_2(
.clk(clk),
.rst(rst),
.enable(enable),
.test_expr(ex_insn[31:28] == 4'h0),
.prevConfigInvalid(1'b0),
.out(checker_13_2)
);
// jump register
ovl_always_wrapped oaw_13_3(
.clk(clk),
.rst(rst),
.enable(enable),
.test_expr(ex_insn[31:28] == 4'h4),
.prevConfigInvalid(1'b0),
.out(checker_13_3)
);
// branch
ovl_always_wrapped oaw_13_4(
.clk(clk),
.rst(rst),
.enable(enable),
.test_expr(ex_insn[31:26] == 6'h04),
.prevConfigInvalid(1'b0),
.out(checker_13_4)
);
// rfe
ovl_always_wrapped oaw_13_5(
.clk(clk),
.rst(rst),
.enable(enable),
.test_expr(ex_insn[31:26] == 6'h09),
.prevConfigInvalid(1'b0),
.out(checker_13_5)
);
// exception
// syscall, trap
ovl_proposition_wrapped opw_13_6(
.rst(rst),
.enable(enable),
.test_expr((ex_pc & `OR1200_EXCEPTION_VECTOR_UNMASK) == 32'h0),
.prevConfigInvalid(1'b0),
.out(checker_13_6)
);
// Checker 15 - RFE updates SPRs correctly
wire checker_15_1;
wire checker_15_2;
wire checker_15_3;
wire checker_15 = checker_15_1 | (checker_15_2 & checker_15_3);
ovl_always_on_edge_wrapped oaoew15_1(
.clk(clk),
.rst(rst),
.enable(enable),
.sampling_event((ex_insn & `OR1200_OPCODE_MASK) == 32'h24000000),
.test_expr(sr == esr),
.prevConfigInvalid(1'b0),
.out(checker_15_1)
);
// TLB miss on address or data at address in EPCR breaks this
ovl_next_wrapped onw15_2(
.clk(clk),
.rst(rst),
.enable(enable),
.num_cks(3'd1),
.start_event((ex_insn & `OR1200_OPCODE_MASK) == 32'h24000000),
.test_expr(ex_pc == epcr),
.prevConfigInvalid(1'b0),
.out(checker_15_2)
);
// Check for exception, note that EPCR will not be updated as we expect
ovl_always_wrapped oaw15_3(
.clk(clk),
.rst(rst),
.enable(enable),
.test_expr((ex_pc & `OR1200_EXCEPTION_VECTOR_UNMASK) == 32'h0),
.prevConfigInvalid(1'b0),
.out(checker_15_3)
);
// Checker 16 all use clk
wire checker_16_1;
wire checker_16_2;
wire checker_16_3;
wire checker_16_4;
wire checker_16_5;
wire checker_16_6;
wire checker_16_7;
wire checker_16 = ((checker_16_1 & checker_16_2 & checker_16_3) | checker_16_4) & (checker_16_5 | (checker_16_6 & checker_16_7));
// Look for GPR writes when the insn does not have a target
ovl_always_on_edge_wrapped oaoew16_1(
.clk(clk),
.rst(rst),
.enable(1'b1),
.sampling_event(gpr_written_to),
.test_expr((ex_insn & 32'hC0000000) == 32'h80000000),
.prevConfigInvalid(1'b0),
.out(checker_16_1)
);
ovl_always_on_edge_wrapped oaoew16_2(
.clk(clk),
.rst(rst),
.enable(1'b1),
.sampling_event(gpr_written_to),
.test_expr((ex_insn & `OR1200_OPCODE_MASK) == 32'h18000000),
.prevConfigInvalid(1'b0),
.out(checker_16_2)
);
ovl_always_on_edge_wrapped oaoew16_3(
.clk(clk),
.rst(rst),
.enable(1'b1),
.sampling_event(gpr_written_to),
.test_expr((ex_insn & `OR1200_OPCODE_MASK) == 32'hE0000000),
.prevConfigInvalid(1'b0),
.out(checker_16_3)
);
// Look for when the instruction updated is not the target of the instruction
ovl_always_on_edge_wrapped oaoew16_4(
.clk(clk),
.rst(rst),
.enable(1'b1),
.sampling_event(gpr_written_to),
.test_expr((ex_insn & `OR1200_TARGET_MASK) == {6'h0, gpr_written_addr, 21'h0}),
.prevConfigInvalid(1'b0),
.out(checker_16_4)
);
// Jump and link writes to LR which is GPR9
ovl_always_on_edge_wrapped oaoew16_5(
.clk(clk),
.rst(rst),
.enable(1'b1),
.sampling_event(gpr_written_to),
.test_expr(gpr_written_addr == 5'h9),
.prevConfigInvalid(1'b0),
.out(checker_16_5)
);
ovl_always_wrapped oaw16_6(
.clk(clk),
.rst(rst),
.enable(1'b1),
.test_expr((ex_insn & `OR1200_OPCODE_MASK) == 32'h04000000),
.prevConfigInvalid(1'b0),
.out(checker_16_6)
);
ovl_always_wrapped oaw16_7(
.clk(clk),
.rst(rst),
.enable(1'b1),
.test_expr((ex_insn & `OR1200_OPCODE_MASK) == 32'h48000000),
.prevConfigInvalid(1'b0),
.out(checker_16_7)
);
// Checker 18 - Unmasked maskable exception implies exception vector, at least 14
wire checker_18_1;
wire checker_18_2;
wire checker_18 = checker_18_1 | checker_18_2;
ovl_next_wrapped onw18_1(
.clk(clk),
.rst(rst),
.enable(enable),
.num_cks(3'd1),
.start_event((ex_insn & 32'hFFFF0000) == 32'h20000000),
.test_expr(ex_pc == 32'h00000C00),
.prevConfigInvalid(1'b0),
.out(checker_18_1)
);
ovl_next_wrapped onw18_2(
.clk(clk),
.rst(rst),
.enable(enable),
.num_cks(3'd1),
.start_event((ex_insn & 32'hFFFF0000) == 32'h21000000),
.test_expr(ex_pc == 32'h00000E00),
.prevConfigInvalid(1'b0),
.out(checker_18_2)
);
// Exception reg checker gated by continuous control flow checker
wire checker_19 = checker_3 & checker_13_1;
assign checkersFired = {12'b0, checker_19, checker_18, 1'b0, checker_16, checker_15, 1'b0, checker_13, 3'b0, checker_9, checker_8, 2'b0, checker_5, 1'b0, checker_3, 1'b0, checker_1, 1'b0};
reg [31:0] checkersFired_reg;
always @(posedge clk)
checkersFired_reg <= checkersFired;
endmodule // BakedInAssertions
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns / 1ps
//`define ENABLE_VCD
`define TEST_SOMETRANSFERS
//`define TEST_RANDOMTRANSFERS
module tb_hpdmc();
/* 100MHz system clock */
reg clk;
initial clk = 1'b0;
always #5 clk = ~clk;
/* DQS clock is phased out by 90 degrees, resulting in 2.5ns delay */
reg dqs_clk;
always @(clk) #2.5 dqs_clk = clk;
wire sdram_cke;
wire sdram_cs_n;
wire sdram_we_n;
wire sdram_cas_n;
wire sdram_ras_n;
wire [3:0] sdram_dqm;
wire [12:0] sdram_adr;
wire [1:0] sdram_ba;
wire [31:0] sdram_dq;
wire [3:0] sdram_dqs;
ddr sdram1(
.Addr(sdram_adr),
.Ba(sdram_ba),
.Clk(clk),
.Clk_n(~clk),
.Cke(sdram_cke),
.Cs_n(sdram_cs_n),
.Ras_n(sdram_ras_n),
.Cas_n(sdram_cas_n),
.We_n(sdram_we_n),
.Dm(sdram_dqm[3:2]),
.Dqs(sdram_dqs[3:2]),
.Dq(sdram_dq[31:16])
);
ddr sdram0(
.Addr(sdram_adr),
.Ba(sdram_ba),
.Clk(clk),
.Clk_n(~clk),
.Cke(sdram_cke),
.Cs_n(sdram_cs_n),
.Ras_n(sdram_ras_n),
.Cas_n(sdram_cas_n),
.We_n(sdram_we_n),
.Dm(sdram_dqm[1:0]),
.Dqs(sdram_dqs[1:0]),
.Dq(sdram_dq[15:0])
);
reg rst;
reg [13:0] csr_a;
reg csr_we;
reg [31:0] csr_di;
wire [31:0] csr_do;
reg [25:0] fml_adr;
reg fml_stb;
reg fml_we;
wire fml_ack;
reg [7:0] fml_sel;
reg [63:0] fml_di;
wire [63:0] fml_do;
hpdmc dut(
.sys_clk(clk),
.dqs_clk(dqs_clk),
.sys_rst(rst),
.csr_a(csr_a),
.csr_we(csr_we),
.csr_di(csr_di),
.csr_do(csr_do),
.fml_adr(fml_adr),
.fml_stb(fml_stb),
.fml_we(fml_we),
.fml_ack(fml_ack),
.fml_sel(fml_sel),
.fml_di(fml_di),
.fml_do(fml_do),
.sdram_cke(sdram_cke),
.sdram_cs_n(sdram_cs_n),
.sdram_we_n(sdram_we_n),
.sdram_cas_n(sdram_cas_n),
.sdram_ras_n(sdram_ras_n),
.sdram_dqm(sdram_dqm),
.sdram_adr(sdram_adr),
.sdram_ba(sdram_ba),
.sdram_dq(sdram_dq),
.sdram_dqs(sdram_dqs),
.dqs_psen(),
.dqs_psincdec(),
.dqs_psdone(1'b1)
);
task waitclock;
begin
@(posedge clk);
#1;
end
endtask
task waitnclock;
input [15:0] n;
integer i;
begin
for(i=0;i<n;i=i+1)
waitclock;
end
endtask
task csrwrite;
input [31:0] address;
input [31:0] data;
begin
csr_a = address[16:2];
csr_di = data;
csr_we = 1'b1;
waitclock;
$display("Configuration Write: %x=%x", address, data);
csr_we = 1'b0;
end
endtask
task csrread;
input [31:0] address;
begin
csr_a = address[16:2];
waitclock;
$display("Configuration Read : %x=%x", address, csr_do);
end
endtask
real reads;
real read_clocks;
task readburst;
input [31:0] address;
integer i;
begin
$display("READ [%x]", address);
fml_adr = address;
fml_stb = 1'b1;
fml_we = 1'b0;
i = 0;
while(~fml_ack) begin
i = i+1;
waitclock;
end
$display("%t: Memory Read : %x=%x acked in %d clocks", $time, address, fml_do, i);
fml_stb = 1'b0;
reads = reads + 1;
read_clocks = read_clocks + i;
for(i=0;i<3;i=i+1) begin
waitclock;
$display("%t: (R burst continuing) %x", $time, fml_do);
end
waitclock;
end
endtask
real writes;
real write_clocks;
task writeburst;
input [31:0] address;
integer i;
begin
$display("WRITE [%x]", address);
fml_adr = address;
fml_stb = 1'b1;
fml_we = 1'b1;
fml_sel = 8'hff;
fml_di = {$random, $random};
i = 0;
while(~fml_ack) begin
i = i+1;
waitclock;
end
$display("%t: Memory Write : %x=%x acked in %d clocks", $time, address, fml_di, i);
fml_stb = 1'b0;
writes = writes + 1;
write_clocks = write_clocks + i;
for(i=0;i<3;i=i+1) begin
waitclock;
fml_di = {$random, $random};
$display("%t: (W burst continuing) %x", $time, fml_di);
end
waitclock;
end
endtask
integer n, addr;
always begin
`ifdef ENABLE_VCD
$dumpfile("hpdmc.vcd");
`endif
/* Reset / Initialize our logic */
rst = 1'b1;
csr_a = 14'd0;
csr_di = 32'd0;
csr_we = 1'b0;
fml_adr = 26'd0;
fml_di = 64'd0;
fml_sel = 8'd0;
fml_stb = 1'b0;
fml_we = 1'b0;
waitclock;
rst = 1'b0;
waitclock;
/* SDRAM initialization sequence. */
/* The controller already comes up in Bypass mode with CKE disabled. */
/* Wait 200us */
#200000;
/* Bring CKE high */
csrwrite(32'h00, 32'h07);
/* Precharge All:
* CS=1
* WE=1
* CAS=0
* RAS=1
* A=A10
* BA=Don't Care
*/
csrwrite(32'h04, 32'b00_0010000000000_1011);
waitnclock(2);
/* Load Extended Mode Register:
* CS=1
* WE=1
* CAS=1
* RAS=1
* A=Value
* BA=01
*
* Extended mode register encoding :
* A12-A2 reserved, must be 0
* A1 weak drive strength
* A0 DLL disable
*/
csrwrite(32'h04, 32'b01_0000000000000_1111);
waitnclock(2);
/* Load Mode Register, DLL in Reset:
* CS=1
* WE=1
* CAS=1
* RAS=1
* A=Value
* BA=00
*
* Mode register encoding :
* A12-A7 = 000000 Normal operation w/o DLL reset
* 000010 Normal operation in DLL reset
* A6-A4 = 010 CL2
* A3 = 0 Sequential burst
* A2-A0 = 011 Burst length = 8
*/
csrwrite(32'h04, 32'b00__000010_010_0_011__1111);
waitnclock(200);
/* Precharge All */
csrwrite(32'h04, 32'b00_0010000000000_1011);
waitnclock(2);
/* Auto Refresh
* CS=1
* WE=0
* CAS=1
* RAS=1
* A=Don't Care
* BA=Don't Care
*/
csrwrite(32'h04, 32'b00_0000000000000_1101);
waitnclock(8);
/* Auto Refresh */
csrwrite(32'h04, 32'b00_0000000000000_1101);
waitnclock(8);
/* Load Mode Register, DLL enabled */
csrwrite(32'h04, 32'b00__000000_010_0_011__1111);
waitnclock(200);
/* SDRAM initialization completed */
`ifdef ENABLE_VCD
/* Now, we want to know what the controller will send to the SDRAM chips */
$dumpvars(0, dut);
`endif
/* Bring up the controller ! */
csrwrite(32'h00, 32'h04);
`ifdef TEST_SOMETRANSFERS
/*
* Try some transfers.
*/
writeburst(32'h00);
writeburst(32'h20);
//writeburst(32'h40);
readburst(32'h00);
readburst(32'h20);
/*readburst(32'h40);
writeburst(32'h40);
readburst(32'h40);*/
`endif
`ifdef TEST_RANDOMTRANSFERS
writes = 0;
write_clocks = 0;
reads = 0;
read_clocks = 0;
for(n=0;n<500;n=n+1) begin
addr = $random;
if($random > 32'h80000000) begin
writeburst(addr);
//writeburst(addr+32'h20);
//writeburst(addr+32'h40);
end else begin
readburst(addr);
//readburst(addr+32'h20);
//readburst(addr+32'h40);
end
end
$display("");
$display("=======================================================");
$display(" Tested: %.0f reads, %.0f writes ", reads, writes);
$display("=======================================================");
$display(" Average read latency: %f cycles", read_clocks/reads);
$display(" Average write latency: %f cycles", write_clocks/writes);
$display("=======================================================");
$display(" Average read bandwidth: %f MBit/s @ 100MHz", (4/(4+read_clocks/reads))*64*100);
$display(" Average write bandwidth: %f MBit/s @ 100MHz", (4/(4+write_clocks/writes))*64*100);
$display("=======================================================");
`endif
$finish;
end
endmodule
|
//======================================================================
//
// adder32.v
// ---------
// 32bit adder with carry in / carry out
//
//
// Author: Peter Magnusson
// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module adder32(
input [31 : 0] a,
input [31 : 0] b,
input carry_in,
output wire [31 : 0] sum,
output wire carry_out);
reg [32 : 0] adder_result;
assign sum = adder_result[31:0];
assign carry_out = adder_result[32];
always @(a, b, carry_in)
adder_result = {1'b0, a} + {1'b0, b} + {32'b0, carry_in};
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Read Data Response Down-Sizer
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// r_downsizer
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_dwidth_converter_v2_1_8_r_downsizer #
(
parameter C_FAMILY = "none",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_AXI_ID_WIDTH = 1,
// Width of all ID signals on SI and MI side of converter.
// Range: >= 1.
parameter integer C_S_AXI_DATA_WIDTH = 64,
// Width of s_axi_wdata and s_axi_rdata.
// Range: 64, 128, 256, 512, 1024.
parameter integer C_M_AXI_DATA_WIDTH = 32,
// Width of m_axi_wdata and m_axi_rdata.
// Assume always smaller than C_S_AXI_DATA_WIDTH.
// Range: 32, 64, 128, 256, 512.
// S_DATA_WIDTH = M_DATA_WIDTH not allowed.
parameter integer C_S_AXI_BYTES_LOG = 3,
// Log2 of number of 32bit word on SI-side.
parameter integer C_M_AXI_BYTES_LOG = 2,
// Log2 of number of 32bit word on MI-side.
parameter integer C_RATIO_LOG = 1
// Log2 of Up-Sizing ratio for data.
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_valid,
input wire cmd_split,
input wire cmd_mirror,
input wire cmd_fix,
input wire [C_S_AXI_BYTES_LOG-1:0] cmd_first_word,
input wire [C_S_AXI_BYTES_LOG-1:0] cmd_offset,
input wire [C_S_AXI_BYTES_LOG-1:0] cmd_mask,
input wire [C_M_AXI_BYTES_LOG:0] cmd_step,
input wire [3-1:0] cmd_size,
input wire [8-1:0] cmd_length,
output wire cmd_ready,
input wire [C_AXI_ID_WIDTH-1:0] cmd_id,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_S_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Read Data Ports
input wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for MI-side word lanes on SI-side.
genvar word_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// .
localparam [24-1:0] C_DOUBLE_LEN = 24'b0000_0000_0000_0000_1111_1111;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Sub-word handling.
reg first_word;
reg [C_S_AXI_BYTES_LOG-1:0] current_word_1;
reg [C_S_AXI_BYTES_LOG-1:0] current_word;
wire [C_S_AXI_BYTES_LOG-1:0] current_word_adjusted;
wire [C_RATIO_LOG-1:0] current_index;
wire last_beat;
wire last_word;
wire new_si_word;
reg [C_S_AXI_BYTES_LOG-1:0] size_mask;
// Sub-word handling for the next cycle.
wire [C_S_AXI_BYTES_LOG-1:0] next_word;
// Burst length handling.
reg first_mi_word;
reg [8-1:0] length_counter_1;
reg [8-1:0] length_counter;
wire [8-1:0] next_length_counter;
// Loading of new rresp data.
wire load_rresp;
reg need_to_update_rresp;
reg [2-1:0] S_AXI_RRESP_ACC;
// Detect start of MI word.
wire first_si_in_mi;
wire first_mi_in_si;
// Throttling help signals.
wire word_completed;
wire cmd_ready_i;
wire pop_si_data;
wire pop_mi_data;
wire si_stalling;
// Internal MI-side control signals.
wire M_AXI_RREADY_I;
// Internal SI-side control signals.
reg [C_S_AXI_DATA_WIDTH-1:0] S_AXI_RDATA_II;
// Internal signals for SI-side.
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID_I;
reg [C_S_AXI_DATA_WIDTH-1:0] S_AXI_RDATA_I;
reg [2-1:0] S_AXI_RRESP_I;
wire S_AXI_RLAST_I;
wire S_AXI_RVALID_I;
wire S_AXI_RREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Handle interface handshaking:
//
//
/////////////////////////////////////////////////////////////////////////////
// Generate address bits used for SI-side transaction size.
always @ *
begin
case (cmd_size)
3'b000: size_mask = C_DOUBLE_LEN[8 +: C_S_AXI_BYTES_LOG];
3'b001: size_mask = C_DOUBLE_LEN[7 +: C_S_AXI_BYTES_LOG];
3'b010: size_mask = C_DOUBLE_LEN[6 +: C_S_AXI_BYTES_LOG];
3'b011: size_mask = C_DOUBLE_LEN[5 +: C_S_AXI_BYTES_LOG];
3'b100: size_mask = C_DOUBLE_LEN[4 +: C_S_AXI_BYTES_LOG];
3'b101: size_mask = C_DOUBLE_LEN[3 +: C_S_AXI_BYTES_LOG];
3'b110: size_mask = C_DOUBLE_LEN[2 +: C_S_AXI_BYTES_LOG];
3'b111: size_mask = C_DOUBLE_LEN[1 +: C_S_AXI_BYTES_LOG]; // Illegal setting.
endcase
end
// Detect when MI-side word is completely assembled.
assign word_completed = ( cmd_fix ) |
( cmd_mirror ) |
( ~cmd_fix & ( ( next_word & size_mask ) == {C_S_AXI_BYTES_LOG{1'b0}} ) ) |
( ~cmd_fix & last_word );
// Pop word from SI-side.
assign M_AXI_RREADY_I = cmd_valid & (S_AXI_RREADY_I | ~word_completed);
assign M_AXI_RREADY = M_AXI_RREADY_I;
// Indicate when there is data available @ SI-side.
assign S_AXI_RVALID_I = M_AXI_RVALID & word_completed & cmd_valid;
// Get MI-side data.
assign pop_mi_data = M_AXI_RVALID & M_AXI_RREADY_I;
// Get SI-side data.
assign pop_si_data = S_AXI_RVALID_I & S_AXI_RREADY_I;
// Signal that the command is done (so that it can be poped from command queue).
assign cmd_ready_i = cmd_valid & pop_si_data & last_word;
assign cmd_ready = cmd_ready_i;
// Detect when MI-side is stalling.
assign si_stalling = S_AXI_RVALID_I & ~S_AXI_RREADY_I;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Keep track of data extraction:
//
// Current address is taken form the command buffer for the first data beat
// to handle unaligned Read transactions. After this is the extraction
// address usually calculated from this point.
// FIX transactions uses the same word address for all data beats.
//
// Next word address is generated as current word plus the current step
// size, with masking to facilitate sub-sized wraping. The Mask is all ones
// for normal wraping, and less when sub-sized wraping is used.
//
// The calculated word addresses (current and next) is offseted by the
// current Offset. For sub-sized transaction the Offset points to the least
// significant address of the included data beats. (The least significant
// word is not necessarily the first data to be extracted, consider WRAP).
// Offset is only used for sub-sized WRAP transcation that are Complete.
//
// First word is active during the first MI-side data beat.
//
// First MI is set during the first MI-side data beat.
//
// The transaction length is taken from the command buffer combinatorialy
// during the First MI cycle. For each generated MI word it is decreased
// until Last Beat is reached.
//
// Last word is determined depending as the last MI-side word generated for
// the command (generated from the AW translation).
// If burst aren't supported all MI-side words are concidered to be the last.
//
/////////////////////////////////////////////////////////////////////////////
// Select if the offset comes from command queue directly or
// from a counter while when extracting multiple MI words per SI word
always @ *
begin
if ( first_word | cmd_fix )
current_word = cmd_first_word;
else
current_word = current_word_1;
end
// Calculate next word.
assign next_word = ( current_word + cmd_step ) & cmd_mask;
// Calculate the word address with offset.
assign current_word_adjusted = current_word + cmd_offset;
// Get the ratio bits (MI-side words vs SI-side words).
assign current_index = current_word_adjusted[C_S_AXI_BYTES_LOG-C_RATIO_LOG +: C_RATIO_LOG];
// Prepare next word address.
always @ (posedge ACLK) begin
if (ARESET) begin
first_word <= 1'b1;
current_word_1 <= 'b0;
end else begin
if ( pop_mi_data ) begin
if ( M_AXI_RLAST ) begin
// Prepare for next access.
first_word <= 1'b1;
end else begin
first_word <= 1'b0;
end
current_word_1 <= next_word;
end
end
end
// Select command length or counted length.
always @ *
begin
if ( first_mi_word )
length_counter = cmd_length;
else
length_counter = length_counter_1;
end
// Calculate next length counter value.
assign next_length_counter = length_counter - 1'b1;
// Keep track of burst length.
always @ (posedge ACLK) begin
if (ARESET) begin
first_mi_word <= 1'b1;
length_counter_1 <= 8'b0;
end else begin
if ( pop_mi_data ) begin
if ( M_AXI_RLAST ) begin
first_mi_word <= 1'b1;
end else begin
first_mi_word <= 1'b0;
end
length_counter_1 <= next_length_counter;
end
end
end
// Detect last beat in a burst.
assign last_beat = ( length_counter == 8'b0 );
// Determine if this last word that shall be extracted from this SI-side word.
assign last_word = ( last_beat );
// Detect new SI-side data word.
assign new_si_word = ( current_word == {C_S_AXI_BYTES_LOG{1'b0}} );
/////////////////////////////////////////////////////////////////////////////
// Simple AXI signal forwarding:
//
// LAST has to be filtered to remove any intermediate LAST (due to split
// trasactions).
//
/////////////////////////////////////////////////////////////////////////////
assign S_AXI_RID_I = cmd_id;
// Handle last flag, i.e. set for SI-side last word.
assign S_AXI_RLAST_I = M_AXI_RLAST & ~cmd_split;
/////////////////////////////////////////////////////////////////////////////
// Handle the accumulation of RRESP.
//
// The accumulated RRESP register is updated for each MI-side response that
// is used in an SI-side word, i.e. the worst status for all included data
// so far.
//
/////////////////////////////////////////////////////////////////////////////
// Detect first SI-side word per MI-side word.
assign first_si_in_mi = cmd_mirror |
first_mi_word |
( ~cmd_mirror & ( ( current_word & size_mask ) == {C_S_AXI_BYTES_LOG{1'b0}} ) );
// Force load accumulated RRESPs to first value or continously for non split.
assign load_rresp = first_si_in_mi;
// Update if more critical.
always @ *
begin
case (S_AXI_RRESP_ACC)
C_RESP_EXOKAY: need_to_update_rresp = ( M_AXI_RRESP == C_RESP_OKAY |
M_AXI_RRESP == C_RESP_SLVERROR |
M_AXI_RRESP == C_RESP_DECERR );
C_RESP_OKAY: need_to_update_rresp = ( M_AXI_RRESP == C_RESP_SLVERROR |
M_AXI_RRESP == C_RESP_DECERR );
C_RESP_SLVERROR: need_to_update_rresp = ( M_AXI_RRESP == C_RESP_DECERR );
C_RESP_DECERR: need_to_update_rresp = 1'b0;
endcase
end
// Select accumultated or direct depending on setting.
always @ *
begin
if ( load_rresp || need_to_update_rresp ) begin
S_AXI_RRESP_I = M_AXI_RRESP;
end else begin
S_AXI_RRESP_I = S_AXI_RRESP_ACC;
end
end
// Accumulate MI-side RRESP.
always @ (posedge ACLK) begin
if (ARESET) begin
S_AXI_RRESP_ACC <= C_RESP_OKAY;
end else begin
if ( pop_mi_data ) begin
S_AXI_RRESP_ACC <= S_AXI_RRESP_I;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Demultiplex data to form complete data word.
//
/////////////////////////////////////////////////////////////////////////////
// Registers and combinatorial data MI-word size mux.
generate
for (word_cnt = 0; word_cnt < (2 ** C_RATIO_LOG) ; word_cnt = word_cnt + 1) begin : WORD_LANE
// Generate extended write data and strobe.
always @ (posedge ACLK) begin
if (ARESET) begin
S_AXI_RDATA_II[word_cnt*C_M_AXI_DATA_WIDTH +: C_M_AXI_DATA_WIDTH] <= {C_M_AXI_DATA_WIDTH{1'b0}};
end else begin
if ( pop_si_data ) begin
S_AXI_RDATA_II[word_cnt*C_M_AXI_DATA_WIDTH +: C_M_AXI_DATA_WIDTH] <= {C_M_AXI_DATA_WIDTH{1'b0}};
end else if ( current_index == word_cnt & pop_mi_data ) begin
S_AXI_RDATA_II[word_cnt*C_M_AXI_DATA_WIDTH +: C_M_AXI_DATA_WIDTH] <= M_AXI_RDATA;
end
end
end
// Select packed or extended data.
always @ *
begin
// Multiplex data.
if ( ( current_index == word_cnt ) | cmd_mirror ) begin
S_AXI_RDATA_I[word_cnt*C_M_AXI_DATA_WIDTH +: C_M_AXI_DATA_WIDTH] = M_AXI_RDATA;
end else begin
S_AXI_RDATA_I[word_cnt*C_M_AXI_DATA_WIDTH +: C_M_AXI_DATA_WIDTH] =
S_AXI_RDATA_II[word_cnt*C_M_AXI_DATA_WIDTH +: C_M_AXI_DATA_WIDTH];
end
end
end // end for word_cnt
endgenerate
/////////////////////////////////////////////////////////////////////////////
// SI-side output handling
/////////////////////////////////////////////////////////////////////////////
assign S_AXI_RREADY_I = S_AXI_RREADY;
assign S_AXI_RVALID = S_AXI_RVALID_I;
assign S_AXI_RID = S_AXI_RID_I;
assign S_AXI_RDATA = S_AXI_RDATA_I;
assign S_AXI_RRESP = S_AXI_RRESP_I;
assign S_AXI_RLAST = S_AXI_RLAST_I;
endmodule
|
module SensorFSM (
input Reset_n_i,
input Clk_i,
input In0_i,
input In1_i,
input In2_i,
input In3_i,
input In4_i,
input In5_i,
input In6_i,
input In7_i,
input In8_i,
input In9_i,
output Out0_o,
output Out1_o,
output Out2_o,
output Out3_o,
output Out4_o,
output Out5_o,
output Out6_o,
output Out7_o,
output Out8_o,
output Out9_o,
input CfgMode_i,
input CfgClk_i,
input CfgShift_i,
input CfgDataIn_i,
output CfgDataOut_o
);
wire [9:0] Input_s;
wire [9:0] Output_s;
wire ScanEnable_s;
wire ScanClk_s;
wire ScanDataIn_s;
wire ScanDataOut_s;
TRFSM #(
.InputWidth(10),
.OutputWidth(10),
.StateWidth(5),
.UseResetRow(0),
.NumRows0(5),
.NumRows1(5),
.NumRows2(5),
.NumRows3(5),
.NumRows4(5),
.NumRows5(0),
.NumRows6(0),
.NumRows7(0),
.NumRows8(0),
.NumRows9(0)
) TRFSM_1 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.Input_i(Input_s),
.Output_o(Output_s),
.CfgMode_i(CfgMode_i),
.CfgClk_i(CfgClk_i),
.CfgShift_i(CfgShift_i),
.CfgDataIn_i(CfgDataIn_i),
.CfgDataOut_o(CfgDataOut_o),
.ScanEnable_i(ScanEnable_s),
.ScanClk_i(ScanClk_s),
.ScanDataIn_i(ScanDataIn_s),
.ScanDataOut_o(ScanDataOut_s)
);
assign Input_s = { In9_i, In8_i, In7_i, In6_i, In5_i, In4_i, In3_i, In2_i, In1_i, In0_i };
assign Out0_o = Output_s[0];
assign Out1_o = Output_s[1];
assign Out2_o = Output_s[2];
assign Out3_o = Output_s[3];
assign Out4_o = Output_s[4];
assign Out5_o = Output_s[5];
assign Out6_o = Output_s[6];
assign Out7_o = Output_s[7];
assign Out8_o = Output_s[8];
assign Out9_o = Output_s[9];
assign ScanEnable_s = 1'b0;
assign ScanClk_s = 1'b0;
assign ScanDataIn_s = 1'b0;
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : arb_select.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Based on granta_r and grantc_r, this module selects a
// row and column command from the request information
// provided by the bank machines.
//
// Depending on address mode configuration, nCL and nCWL, a column
// command pipeline of up to three states will be created.
`timescale 1 ps / 1 ps
module mig_7series_v2_3_arb_select #
(
parameter TCQ = 100,
parameter EVEN_CWL_2T_MODE = "OFF",
parameter ADDR_CMD_MODE = "1T",
parameter BANK_VECT_INDX = 11,
parameter BANK_WIDTH = 3,
parameter BURST_MODE = "8",
parameter CS_WIDTH = 4,
parameter CL = 5,
parameter CWL = 5,
parameter DATA_BUF_ADDR_VECT_INDX = 31,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DRAM_TYPE = "DDR3",
parameter EARLY_WR_DATA_ADDR = "OFF",
parameter ECC = "OFF",
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2,
parameter nCS_PER_RANK = 1,
parameter CKE_ODT_AUX = "FALSE",
parameter nSLOTS = 2,
parameter RANKS = 1,
parameter RANK_VECT_INDX = 15,
parameter RANK_WIDTH = 2,
parameter ROW_VECT_INDX = 63,
parameter ROW_WIDTH = 16,
parameter RTT_NOM = "40",
parameter RTT_WR = "120",
parameter SLOT_0_CONFIG = 8'b0000_0101,
parameter SLOT_1_CONFIG = 8'b0000_1010
)
(
// Outputs
output wire col_periodic_rd,
output wire [RANK_WIDTH-1:0] col_ra,
output wire [BANK_WIDTH-1:0] col_ba,
output wire [ROW_WIDTH-1:0] col_a,
output wire col_rmw,
output wire col_rd_wr,
output wire col_size,
output wire [ROW_WIDTH-1:0] col_row,
output wire [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr,
output wire [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr,
output wire [nCK_PER_CLK-1:0] mc_ras_n,
output wire [nCK_PER_CLK-1:0] mc_cas_n,
output wire [nCK_PER_CLK-1:0] mc_we_n,
output wire [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address,
output wire [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank,
output wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n,
output wire [1:0] mc_odt,
output wire [nCK_PER_CLK-1:0] mc_cke,
output wire [3:0] mc_aux_out0,
output wire [3:0] mc_aux_out1,
output [2:0] mc_cmd,
output wire [5:0] mc_data_offset,
output wire [5:0] mc_data_offset_1,
output wire [5:0] mc_data_offset_2,
output wire [1:0] mc_cas_slot,
output wire [RANK_WIDTH-1:0] rnk_config,
// Inputs
input clk,
input rst,
input init_calib_complete,
input [RANK_VECT_INDX:0] req_rank_r,
input [BANK_VECT_INDX:0] req_bank_r,
input [nBANK_MACHS-1:0] req_ras,
input [nBANK_MACHS-1:0] req_cas,
input [nBANK_MACHS-1:0] req_wr_r,
input [nBANK_MACHS-1:0] grant_row_r,
input [nBANK_MACHS-1:0] grant_pre_r,
input [ROW_VECT_INDX:0] row_addr,
input [nBANK_MACHS-1:0] row_cmd_wr,
input insert_maint_r1,
input maint_zq_r,
input maint_sre_r,
input maint_srx_r,
input [RANK_WIDTH-1:0] maint_rank_r,
input [nBANK_MACHS-1:0] req_periodic_rd_r,
input [nBANK_MACHS-1:0] req_size_r,
input [nBANK_MACHS-1:0] rd_wr_r,
input [ROW_VECT_INDX:0] req_row_r,
input [ROW_VECT_INDX:0] col_addr,
input [DATA_BUF_ADDR_VECT_INDX:0] req_data_buf_addr_r,
input [nBANK_MACHS-1:0] grant_col_r,
input [nBANK_MACHS-1:0] grant_col_wr,
input [6*RANKS-1:0] calib_rddata_offset,
input [6*RANKS-1:0] calib_rddata_offset_1,
input [6*RANKS-1:0] calib_rddata_offset_2,
input [5:0] col_channel_offset,
input [nBANK_MACHS-1:0] grant_config_r,
input rnk_config_strobe,
input [7:0] slot_0_present,
input [7:0] slot_1_present,
input send_cmd0_row,
input send_cmd0_col,
input send_cmd1_row,
input send_cmd1_col,
input send_cmd2_row,
input send_cmd2_col,
input send_cmd2_pre,
input send_cmd3_col,
input sent_col,
input cs_en0,
input cs_en1,
input cs_en2,
input cs_en3
);
localparam OUT_CMD_WIDTH = RANK_WIDTH + BANK_WIDTH + ROW_WIDTH + 1 + 1 + 1;
reg col_rd_wr_ns;
reg col_rd_wr_r = 1'b0;
reg [OUT_CMD_WIDTH-1:0] col_cmd_r = {OUT_CMD_WIDTH {1'b0}};
reg [OUT_CMD_WIDTH-1:0] row_cmd_r = {OUT_CMD_WIDTH {1'b0}};
// calib_rd_data_offset for currently targeted rank
reg [5:0] rank_rddata_offset_0;
reg [5:0] rank_rddata_offset_1;
reg [5:0] rank_rddata_offset_2;
// Toggle CKE[0] when entering and exiting self-refresh, disable CKE[1]
assign mc_aux_out0[0] = (maint_sre_r || maint_srx_r) & insert_maint_r1;
assign mc_aux_out0[2] = 1'b0;
reg cke_r;
reg cke_ns;
generate
if(CKE_ODT_AUX == "FALSE")begin
always @(posedge clk)
begin
if (rst)
cke_r = 1'b1;
else
cke_r = cke_ns;
end
always @(*)
begin
cke_ns = 1'b1;
if (maint_sre_r & insert_maint_r1)
cke_ns = 1'b0;
else if (cke_r==1'b0)
begin
if (maint_srx_r & insert_maint_r1)
cke_ns = 1'b1;
else
cke_ns = 1'b0;
end
end
end
endgenerate
// Disable ODT & CKE toggle enable high bits
assign mc_aux_out1 = 4'b0;
// implement PHY command word
assign mc_cmd[0] = sent_col;
assign mc_cmd[1] = EVEN_CWL_2T_MODE == "ON" ?
sent_col && col_rd_wr_r :
sent_col && col_rd_wr_ns;
assign mc_cmd[2] = ~sent_col;
// generate calib_rd_data_offset for current rank - only use rank 0 values for now
always @(calib_rddata_offset or calib_rddata_offset_1 or calib_rddata_offset_2) begin
rank_rddata_offset_0 = calib_rddata_offset[5:0];
rank_rddata_offset_1 = calib_rddata_offset_1[5:0];
rank_rddata_offset_2 = calib_rddata_offset_2[5:0];
end
// generate data offset
generate
if(EVEN_CWL_2T_MODE == "ON") begin : gen_mc_data_offset_even_cwl_2t
assign mc_data_offset = ~sent_col ?
6'b0 :
col_rd_wr_r ?
rank_rddata_offset_0 + col_channel_offset :
nCK_PER_CLK == 2 ?
CWL - 2 + col_channel_offset :
// nCK_PER_CLK == 4
CWL + 2 + col_channel_offset;
assign mc_data_offset_1 = ~sent_col ?
6'b0 :
col_rd_wr_r ?
rank_rddata_offset_1 + col_channel_offset :
nCK_PER_CLK == 2 ?
CWL - 2 + col_channel_offset :
// nCK_PER_CLK == 4
CWL + 2 + col_channel_offset;
assign mc_data_offset_2 = ~sent_col ?
6'b0 :
col_rd_wr_r ?
rank_rddata_offset_2 + col_channel_offset :
nCK_PER_CLK == 2 ?
CWL - 2 + col_channel_offset :
// nCK_PER_CLK == 4
CWL + 2 + col_channel_offset;
end
else begin : gen_mc_data_offset_not_even_cwl_2t
assign mc_data_offset = ~sent_col ?
6'b0 :
col_rd_wr_ns ?
rank_rddata_offset_0 + col_channel_offset :
nCK_PER_CLK == 2 ?
CWL - 2 + col_channel_offset :
// nCK_PER_CLK == 4
CWL + 2 + col_channel_offset;
assign mc_data_offset_1 = ~sent_col ?
6'b0 :
col_rd_wr_ns ?
rank_rddata_offset_1 + col_channel_offset :
nCK_PER_CLK == 2 ?
CWL - 2 + col_channel_offset :
// nCK_PER_CLK == 4
CWL + 2 + col_channel_offset;
assign mc_data_offset_2 = ~sent_col ?
6'b0 :
col_rd_wr_ns ?
rank_rddata_offset_2 + col_channel_offset :
nCK_PER_CLK == 2 ?
CWL - 2 + col_channel_offset :
// nCK_PER_CLK == 4
CWL + 2 + col_channel_offset;
end
endgenerate
assign mc_cas_slot = col_channel_offset[1:0];
// Based on arbitration results, select the row and column commands.
integer i;
reg [OUT_CMD_WIDTH-1:0] row_cmd_ns;
generate
begin : row_mux
wire [OUT_CMD_WIDTH-1:0] maint_cmd =
{maint_rank_r, // maintenance rank
row_cmd_r[15+:(BANK_WIDTH+ROW_WIDTH-11)],
// bank plus upper address bits
1'b0, // A10 = 0 for ZQCS
row_cmd_r[3+:10], // address bits [9:0]
// ZQ, SRX or SRE/REFRESH
(maint_zq_r ? 3'b110 : maint_srx_r ? 3'b111 : 3'b001)
};
always @(/*AS*/grant_row_r or insert_maint_r1 or maint_cmd
or req_bank_r or req_cas or req_rank_r or req_ras
or row_addr or row_cmd_r or row_cmd_wr or rst)
begin
row_cmd_ns = rst
? {RANK_WIDTH{1'b0}}
: insert_maint_r1
? maint_cmd
: row_cmd_r;
for (i=0; i<nBANK_MACHS; i=i+1)
if (grant_row_r[i])
row_cmd_ns = {req_rank_r[(RANK_WIDTH*i)+:RANK_WIDTH],
req_bank_r[(BANK_WIDTH*i)+:BANK_WIDTH],
row_addr[(ROW_WIDTH*i)+:ROW_WIDTH],
req_ras[i],
req_cas[i],
row_cmd_wr[i]};
end
if (ADDR_CMD_MODE == "2T" && nCK_PER_CLK == 2)
always @(posedge clk) row_cmd_r <= #TCQ row_cmd_ns;
end // row_mux
endgenerate
reg [OUT_CMD_WIDTH-1:0] pre_cmd_ns;
generate
if((nCK_PER_CLK == 4) && (ADDR_CMD_MODE != "2T")) begin : pre_mux
reg [OUT_CMD_WIDTH-1:0] pre_cmd_r = {OUT_CMD_WIDTH {1'b0}};
always @(/*AS*/grant_pre_r or req_bank_r or req_cas or req_rank_r or req_ras
or row_addr or pre_cmd_r or row_cmd_wr or rst)
begin
pre_cmd_ns = rst
? {RANK_WIDTH{1'b0}}
: pre_cmd_r;
for (i=0; i<nBANK_MACHS; i=i+1)
if (grant_pre_r[i])
pre_cmd_ns = {req_rank_r[(RANK_WIDTH*i)+:RANK_WIDTH],
req_bank_r[(BANK_WIDTH*i)+:BANK_WIDTH],
row_addr[(ROW_WIDTH*i)+:ROW_WIDTH],
req_ras[i],
req_cas[i],
row_cmd_wr[i]};
end
end // pre_mux
endgenerate
reg [OUT_CMD_WIDTH-1:0] col_cmd_ns;
generate
begin : col_mux
reg col_periodic_rd_ns;
reg col_periodic_rd_r;
reg col_rmw_ns;
reg col_rmw_r;
reg col_size_ns;
reg col_size_r;
reg [ROW_WIDTH-1:0] col_row_ns;
reg [ROW_WIDTH-1:0] col_row_r;
reg [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr_ns;
reg [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr_r;
always @(col_addr or col_cmd_r or col_data_buf_addr_r
or col_periodic_rd_r or col_rmw_r or col_row_r
or col_size_r or grant_col_r or rd_wr_r or req_bank_r
or req_data_buf_addr_r or req_periodic_rd_r
or req_rank_r or req_row_r or req_size_r or req_wr_r
or rst or col_rd_wr_r)
begin
col_periodic_rd_ns = ~rst && col_periodic_rd_r;
col_cmd_ns = {(rst ? {RANK_WIDTH{1'b0}}
: col_cmd_r[(OUT_CMD_WIDTH-1)-:RANK_WIDTH]),
((rst && ECC != "OFF")
? {OUT_CMD_WIDTH-3-RANK_WIDTH{1'b0}}
: col_cmd_r[3+:(OUT_CMD_WIDTH-3-RANK_WIDTH)]),
(rst ? 3'b0 : col_cmd_r[2:0])};
col_rmw_ns = col_rmw_r;
col_size_ns = rst ? 1'b0 : col_size_r;
col_row_ns = col_row_r;
col_rd_wr_ns = col_rd_wr_r;
col_data_buf_addr_ns = col_data_buf_addr_r;
for (i=0; i<nBANK_MACHS; i=i+1)
if (grant_col_r[i]) begin
col_periodic_rd_ns = req_periodic_rd_r[i];
col_cmd_ns = {req_rank_r[(RANK_WIDTH*i)+:RANK_WIDTH],
req_bank_r[(BANK_WIDTH*i)+:BANK_WIDTH],
col_addr[(ROW_WIDTH*i)+:ROW_WIDTH],
1'b1,
1'b0,
rd_wr_r[i]};
col_rmw_ns = req_wr_r[i] && rd_wr_r[i];
col_size_ns = req_size_r[i];
col_row_ns = req_row_r[(ROW_WIDTH*i)+:ROW_WIDTH];
col_rd_wr_ns = rd_wr_r[i];
col_data_buf_addr_ns =
req_data_buf_addr_r[(DATA_BUF_ADDR_WIDTH*i)+:DATA_BUF_ADDR_WIDTH];
end
end // always @ (...
if (EARLY_WR_DATA_ADDR == "OFF") begin : early_wr_data_addr_off
assign col_wr_data_buf_addr = col_data_buf_addr_ns;
end
else begin : early_wr_data_addr_on
reg [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr_ns;
reg [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr_r;
always @(/*AS*/col_wr_data_buf_addr_r or grant_col_wr
or req_data_buf_addr_r) begin
col_wr_data_buf_addr_ns = col_wr_data_buf_addr_r;
for (i=0; i<nBANK_MACHS; i=i+1)
if (grant_col_wr[i])
col_wr_data_buf_addr_ns =
req_data_buf_addr_r[(DATA_BUF_ADDR_WIDTH*i)+:DATA_BUF_ADDR_WIDTH];
end
always @(posedge clk) col_wr_data_buf_addr_r <=
#TCQ col_wr_data_buf_addr_ns;
assign col_wr_data_buf_addr = col_wr_data_buf_addr_ns;
end
always @(posedge clk) col_periodic_rd_r <= #TCQ col_periodic_rd_ns;
always @(posedge clk) col_rmw_r <= #TCQ col_rmw_ns;
always @(posedge clk) col_size_r <= #TCQ col_size_ns;
always @(posedge clk) col_data_buf_addr_r <=
#TCQ col_data_buf_addr_ns;
if (ECC != "OFF" || EVEN_CWL_2T_MODE == "ON") begin
always @(posedge clk) col_cmd_r <= #TCQ col_cmd_ns;
always @(posedge clk) col_row_r <= #TCQ col_row_ns;
end
always @(posedge clk) col_rd_wr_r <= #TCQ col_rd_wr_ns;
if(EVEN_CWL_2T_MODE == "ON") begin
assign col_periodic_rd = col_periodic_rd_r;
assign col_ra = col_cmd_r[3+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH];
assign col_ba = col_cmd_r[3+ROW_WIDTH+:BANK_WIDTH];
assign col_a = col_cmd_r[3+:ROW_WIDTH];
assign col_rmw = col_rmw_r;
assign col_rd_wr = col_rd_wr_r;
assign col_size = col_size_r;
assign col_row = col_row_r;
assign col_data_buf_addr = col_data_buf_addr_r;
end
else begin
assign col_periodic_rd = col_periodic_rd_ns;
assign col_ra = col_cmd_ns[3+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH];
assign col_ba = col_cmd_ns[3+ROW_WIDTH+:BANK_WIDTH];
assign col_a = col_cmd_ns[3+:ROW_WIDTH];
assign col_rmw = col_rmw_ns;
assign col_rd_wr = col_rd_wr_ns;
assign col_size = col_size_ns;
assign col_row = col_row_ns;
assign col_data_buf_addr = col_data_buf_addr_ns;
end
end // col_mux
endgenerate
reg [OUT_CMD_WIDTH-1:0] cmd0 = {OUT_CMD_WIDTH{1'b1}};
reg cke0;
always @(send_cmd0_row or send_cmd0_col or row_cmd_ns or row_cmd_r or col_cmd_ns or col_cmd_r or cke_ns or cke_r ) begin
cmd0 = {OUT_CMD_WIDTH{1'b1}};
if (send_cmd0_row) cmd0 = row_cmd_ns;
if (send_cmd0_row && EVEN_CWL_2T_MODE == "ON" && nCK_PER_CLK == 2) cmd0 = row_cmd_r;
if (send_cmd0_col) cmd0 = col_cmd_ns;
if (send_cmd0_col && EVEN_CWL_2T_MODE == "ON") cmd0 = col_cmd_r;
if (send_cmd0_row) cke0 = cke_ns;
else cke0 = cke_r ;
end
reg [OUT_CMD_WIDTH-1:0] cmd1 = {OUT_CMD_WIDTH{1'b1}};
generate
if ((nCK_PER_CLK == 2) || (nCK_PER_CLK == 4))
always @(send_cmd1_row or send_cmd1_col or row_cmd_ns or col_cmd_ns or pre_cmd_ns) begin
cmd1 = {OUT_CMD_WIDTH{1'b1}};
if (send_cmd1_row) cmd1 = row_cmd_ns;
if (send_cmd1_col) cmd1 = col_cmd_ns;
end
endgenerate
reg [OUT_CMD_WIDTH-1:0] cmd2 = {OUT_CMD_WIDTH{1'b1}};
reg [OUT_CMD_WIDTH-1:0] cmd3 = {OUT_CMD_WIDTH{1'b1}};
generate
if (nCK_PER_CLK == 4)
always @(send_cmd2_row or send_cmd2_col or send_cmd2_pre or send_cmd3_col or row_cmd_ns or col_cmd_ns or pre_cmd_ns) begin
cmd2 = {OUT_CMD_WIDTH{1'b1}};
cmd3 = {OUT_CMD_WIDTH{1'b1}};
if (send_cmd2_row) cmd2 = row_cmd_ns;
if (send_cmd2_col) cmd2 = col_cmd_ns;
if (send_cmd2_pre) cmd2 = pre_cmd_ns;
if (send_cmd3_col) cmd3 = col_cmd_ns;
end
endgenerate
// Output command bus 0.
wire [RANK_WIDTH-1:0] ra0;
// assign address
assign {ra0, mc_bank[BANK_WIDTH-1:0], mc_address[ROW_WIDTH-1:0], mc_ras_n[0], mc_cas_n[0], mc_we_n[0]} = cmd0;
// Output command bus 1.
wire [RANK_WIDTH-1:0] ra1;
// assign address
assign {ra1, mc_bank[2*BANK_WIDTH-1:BANK_WIDTH], mc_address[2*ROW_WIDTH-1:ROW_WIDTH], mc_ras_n[1], mc_cas_n[1], mc_we_n[1]} = cmd1;
wire [RANK_WIDTH-1:0] ra2;
wire [RANK_WIDTH-1:0] ra3;
generate
if(nCK_PER_CLK == 4) begin
// Output command bus 2.
// assign address
assign {ra2, mc_bank[3*BANK_WIDTH-1:2*BANK_WIDTH], mc_address[3*ROW_WIDTH-1:2*ROW_WIDTH], mc_ras_n[2], mc_cas_n[2], mc_we_n[2]} = cmd2;
// Output command bus 3.
// assign address
assign {ra3, mc_bank[4*BANK_WIDTH-1:3*BANK_WIDTH], mc_address[4*ROW_WIDTH-1:3*ROW_WIDTH], mc_ras_n[3], mc_cas_n[3], mc_we_n[3]} =
cmd3;
end
endgenerate
generate
if(CKE_ODT_AUX == "FALSE")begin
assign mc_cke[0] = cke0;
assign mc_cke[1] = cke_ns;
if(nCK_PER_CLK == 4) begin
assign mc_cke[2] = cke_ns;
assign mc_cke[3] = cke_ns;
end
end
endgenerate
// Output cs busses.
localparam ONE = {nCS_PER_RANK{1'b1}};
wire [(CS_WIDTH*nCS_PER_RANK)-1:0] cs_one_hot =
{{CS_WIDTH{1'b0}},ONE};
assign mc_cs_n[CS_WIDTH*nCS_PER_RANK -1 :0 ] =
{(~(cs_one_hot << (nCS_PER_RANK*ra0)) | {CS_WIDTH*nCS_PER_RANK{~cs_en0}})};
assign mc_cs_n[2*CS_WIDTH*nCS_PER_RANK -1 : CS_WIDTH*nCS_PER_RANK ] =
{(~(cs_one_hot << (nCS_PER_RANK*ra1)) | {CS_WIDTH*nCS_PER_RANK{~cs_en1}})};
generate
if(nCK_PER_CLK == 4) begin
assign mc_cs_n[3*CS_WIDTH*nCS_PER_RANK -1 :2*CS_WIDTH*nCS_PER_RANK ] =
{(~(cs_one_hot << (nCS_PER_RANK*ra2)) | {CS_WIDTH*nCS_PER_RANK{~cs_en2}})};
assign mc_cs_n[4*CS_WIDTH*nCS_PER_RANK -1 :3*CS_WIDTH*nCS_PER_RANK ] =
{(~(cs_one_hot << (nCS_PER_RANK*ra3)) | {CS_WIDTH*nCS_PER_RANK{~cs_en3}})};
end
endgenerate
// Output rnk_config info.
reg [RANK_WIDTH-1:0] rnk_config_ns;
reg [RANK_WIDTH-1:0] rnk_config_r;
always @(/*AS*/grant_config_r
or rnk_config_r or rnk_config_strobe or req_rank_r or rst) begin
if (rst) rnk_config_ns = {RANK_WIDTH{1'b0}};
else begin
rnk_config_ns = rnk_config_r;
if (rnk_config_strobe)
for (i=0; i<nBANK_MACHS; i=i+1)
if (grant_config_r[i]) rnk_config_ns = req_rank_r[(RANK_WIDTH*i)+:RANK_WIDTH];
end
end
always @(posedge clk) rnk_config_r <= #TCQ rnk_config_ns;
assign rnk_config = rnk_config_ns;
// Generate ODT signals.
wire [CS_WIDTH-1:0] col_ra_one_hot = cs_one_hot << col_ra;
wire slot_0_select = (nSLOTS == 1) ? |(col_ra_one_hot & slot_0_present)
: (slot_0_present[2] & slot_0_present[0]) ?
|(col_ra_one_hot[CS_WIDTH-1:0] & {slot_0_present[2],
slot_0_present[0]}) : (slot_0_present[0])?
col_ra_one_hot[0] : 1'b0;
wire slot_0_read = EVEN_CWL_2T_MODE == "ON" ?
slot_0_select && col_rd_wr_r :
slot_0_select && col_rd_wr_ns;
wire slot_0_write = EVEN_CWL_2T_MODE == "ON" ?
slot_0_select && ~col_rd_wr_r :
slot_0_select && ~col_rd_wr_ns;
reg [1:0] slot_1_population = 2'b0;
reg[1:0] slot_0_population;
always @(/*AS*/slot_0_present) begin
slot_0_population = 2'b0;
for (i=0; i<8; i=i+1)
if (~slot_0_population[1])
if (slot_0_present[i] == 1'b1) slot_0_population =
slot_0_population + 2'b1;
end
// ODT on in slot 0 for writes to slot 0 (and R/W to slot 1 for DDR3)
wire slot_0_odt = (DRAM_TYPE == "DDR3") ? ~slot_0_read : slot_0_write;
assign mc_aux_out0[1] = slot_0_odt & sent_col; // Only send for COL cmds
generate
if (nSLOTS > 1) begin : slot_1_configured
wire slot_1_select = (slot_1_present[3] & slot_1_present[1])?
|({col_ra_one_hot[slot_0_population+1],
col_ra_one_hot[slot_0_population]}) :
(slot_1_present[1]) ? col_ra_one_hot[slot_0_population] :1'b0;
wire slot_1_read = EVEN_CWL_2T_MODE == "ON" ?
slot_1_select && col_rd_wr_r :
slot_1_select && col_rd_wr_ns;
wire slot_1_write = EVEN_CWL_2T_MODE == "ON" ?
slot_1_select && ~col_rd_wr_r :
slot_1_select && ~col_rd_wr_ns;
// ODT on in slot 1 for writes to slot 1 (and R/W to slot 0 for DDR3)
wire slot_1_odt = (DRAM_TYPE == "DDR3") ? ~slot_1_read : slot_1_write;
assign mc_aux_out0[3] = slot_1_odt & sent_col; // Only send for COL cmds
end // if (nSLOTS > 1)
else begin
// Disable slot 1 ODT when not present
assign mc_aux_out0[3] = 1'b0;
end // else: !if(nSLOTS > 1)
endgenerate
generate
if(CKE_ODT_AUX == "FALSE")begin
reg[1:0] mc_aux_out_r ;
reg[1:0] mc_aux_out_r_1 ;
reg[1:0] mc_aux_out_r_2 ;
always@(posedge clk) begin
mc_aux_out_r[0] <= #TCQ mc_aux_out0[1] ;
mc_aux_out_r[1] <= #TCQ mc_aux_out0[3] ;
mc_aux_out_r_1 <= #TCQ mc_aux_out_r ;
mc_aux_out_r_2 <= #TCQ mc_aux_out_r_1 ;
end
if((nCK_PER_CLK == 4) && (nSLOTS > 1 )) begin:odt_high_time_4_1_dslot
assign mc_odt[0] = mc_aux_out0[1] | mc_aux_out_r[0] | mc_aux_out_r_1[0];
assign mc_odt[1] = mc_aux_out0[3] | mc_aux_out_r[1] | mc_aux_out_r_1[1];
end else if(nCK_PER_CLK == 4) begin:odt_high_time_4_1
assign mc_odt[0] = mc_aux_out0[1] | mc_aux_out_r[0] ;
assign mc_odt[1] = mc_aux_out0[3] | mc_aux_out_r[1] ;
end else if(nCK_PER_CLK == 2) begin:odt_high_time_2_1
assign mc_odt[0] = mc_aux_out0[1] | mc_aux_out_r[0] | mc_aux_out_r_1[0] | mc_aux_out_r_2[0] ;
assign mc_odt[1] = mc_aux_out0[3] | mc_aux_out_r[1] | mc_aux_out_r_1[1] | mc_aux_out_r_2[1] ;
end
end
endgenerate
endmodule
|
//-----------------------------------------------------------------------------
//-- Divisor de reloj
//-- Señal de periodo igual al indicado
//-- El ancho del pulso positivo es de 1 ciclo de reloj
//--
//-- (c) BQ. September 2015. written by Juan Gonzalez (obijuan)
//-----------------------------------------------------------------------------
//-- GPL license
//-----------------------------------------------------------------------------
`include "divider.vh"
//-- ENTRADAS:
//-- -clk: Senal de reloj del sistema (12 MHZ en la iceStick)
//
//-- SALIDAS:
//-- - clk_out. Señal de salida para lograr la velocidad en baudios indicada
//-- Anchura de 1 periodo de clk. SALIDA NO REGISTRADA
module dividerp1(input wire clk,
output wire clk_out);
//-- Valor por defecto de la velocidad en baudios
parameter M = `T_100ms;
//-- Numero de bits para almacenar el divisor de baudios
localparam N = $clog2(M);
//-- Registro para implementar el contador modulo M
reg [N-1:0] divcounter = 0;
//-- Contador módulo M
always @(posedge clk)
divcounter <= (divcounter == M - 1) ? 0 : divcounter + 1;
//-- Sacar un pulso de anchura 1 ciclo de reloj si el generador
assign clk_out = (divcounter == 0) ? 1 : 0;
endmodule
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
/*
* Copyright (c) 2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This program checks that conbinational UDPs with x outputs are
* properly executed.
*/
module main;
wire Y;
reg A, B, S;
muxx1 MUX2 ( Y, S, A, B ) ;
initial begin
S = 0;
A = 0;
B = 0;
#1 if (Y !== 1'b0) begin
$display("FAILED -- Y is %b", Y);
$finish;
end
B = 1;
#1 if (Y !== 1'b0) begin
$display("FAILED -- Y is %b", Y);
$finish;
end
S = 1;
#1 if (Y !== 1'b1) begin
$display("FAILED -- Y is %b", Y);
$finish;
end
B = 1'bx;
#1 if (Y !== 1'bx) begin
$display("FAILED -- Y is %b", Y);
$finish;
end
B = 1;
S = 1'bx;
#1 if (Y !== 1'bx) begin
$display("FAILED -- Y is %b", Y);
$finish;
end
B = 0;
#1 if (Y !== 1'b0) begin
$display("FAILED -- Y is %b", Y);
$finish;
end
$display("PASSED");
end // initial begin
endmodule
primitive muxx1(Q, S, A, B);
output Q;
input S, A, B;
table
// S A B Q
0 0 ? : 0 ;
0 1 ? : 1 ;
0 x ? : x ; // problem line
1 ? 0 : 0 ;
1 ? 1 : 1 ;
1 ? x : x ; // problem line
x 0 0 : 0 ;
x 1 1 : 1 ;
endtable
endprimitive
|
/*
* Copyright (C) 2011 Kiel Friedt
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
//authors Kiel Friedt, Kevin McIntosh,Cody DeHaan
module ForwardUnit(EX_RS, EX_RT, MEM_RD, WB_RD, MEM_WB, WB_WB, Forward_A, Forward_B);
input MEM_WB, WB_WB;
input [4:0] EX_RS, EX_RT, MEM_RD, WB_RD;
output [1:0] Forward_A, Forward_B;
reg [1:0] Forward_A, Forward_B;
always @(EX_RS or EX_RT)
begin
//Forward A Register
if (WB_WB && WB_RD && MEM_RD != WB_RD && WB_RD == EX_RS)
begin
assign Forward_A = 2'b01;
end
else if (MEM_WB && MEM_RD && MEM_RD == EX_RS)
begin
assign Forward_A = 2'b10;
end
else
begin
assign Forward_A = 2'b00;
end
//Forward B Register
if (WB_WB && WB_RD && MEM_RD != WB_RD && WB_RD == EX_RT)
begin
assign Forward_B = 2'b01;
end
else if (MEM_WB && MEM_RD && MEM_RD == EX_RT)
begin
assign Forward_B = 2'b10;
end
else
begin
assign Forward_B = 2'b00;
end
end
//initial begin
// assign Forward_A = 2'b00;
//assign Forward_B = 2'b00;
//end
endmodule |
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate the ? operator
module main;
reg globvar;
reg [3:0] bvec,var1,var2,var3;
reg cond, a,b,out1,out2;
reg error;
initial
begin
error = 0;
bvec = 4'bzx10 ;
for(var1 = 0; var1 <= 3; var1 = var1 + 1)
for(var2 = 0; var2 <= 3; var2 = var2 + 1)
for(var3 = 0; var3 <= 3; var3 = var3 + 1)
begin
cond = bvec[var1];
a = bvec[var2];
b = bvec[var3];
out1 = cond ? a: b ;
if(cond) out2 = a ;
else out2 = b;
if(out1 != out2)
begin
$display("FAILED - %b %b %b %b %b",cond,a,b,out1,out2);
error = 1;
end
end
if(error == 0)
$display("PASSED");
end
endmodule // main
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
integer j;
reg [63:0] cam_lookup_hit_vector;
integer hit_count;
always @(/*AUTOSENSE*/cam_lookup_hit_vector) begin
hit_count = 0;
for (j=0; j < 64; j=j+1) begin
hit_count = hit_count + {31'h0, cam_lookup_hit_vector[j]};
end
end
integer hit_count2;
always @(/*AUTOSENSE*/cam_lookup_hit_vector) begin
hit_count2 = 0;
for (j=63; j >= 0; j=j-1) begin
hit_count2 = hit_count2 + {31'h0, cam_lookup_hit_vector[j]};
end
end
integer hit_count3;
always @(/*AUTOSENSE*/cam_lookup_hit_vector) begin
hit_count3 = 0;
for (j=63; j > 0; j=j-1) begin
if (cam_lookup_hit_vector[j]) hit_count3 = hit_count3 + 32'd1;
end
end
reg [127:0] wide_for_index;
reg [31:0] wide_for_count;
always @(/*AUTOSENSE*/cam_lookup_hit_vector) begin
wide_for_count = 0;
for (wide_for_index = 128'hff_00000000_00000000;
wide_for_index < 128'hff_00000000_00000100;
wide_for_index = wide_for_index + 2) begin
wide_for_count = wide_for_count+32'h1;
end
end
// While loop
integer w;
initial begin
while (w<10) w=w+1;
if (w!=10) $stop;
while (w<20) begin w=w+2; end
while (w<20) begin w=w+99999; end // NEVER
if (w!=20) $stop;
end
// Do-While loop
integer dw;
initial begin
do dw=dw+1; while (dw<10);
if (dw!=10) $stop;
do dw=dw+2; while (dw<20);
if (dw!=20) $stop;
do dw=dw+5; while (dw<20); // Once
if (dw!=25) $stop;
end
always @ (posedge clk) begin
cam_lookup_hit_vector <= 0;
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
cam_lookup_hit_vector <= 64'h00010000_00010000;
end
if (cyc==2) begin
if (hit_count != 32'd2) $stop;
if (hit_count2 != 32'd2) $stop;
if (hit_count3 != 32'd2) $stop;
cam_lookup_hit_vector <= 64'h01010010_00010001;
end
if (cyc==3) begin
if (hit_count != 32'd5) $stop;
if (hit_count2 != 32'd5) $stop;
if (hit_count3 != 32'd4) $stop;
if (wide_for_count != 32'h80) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
//----------------------------------------------------------------------
// Copyright 2007-2010 Mentor Graphics Corporation
// Copyright 2007-2010 Cadence Design Systems, Inc.
// All Rights Reserved Worldwide
//
// Licensed under the Apache License, Version 2.0 (the
// "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of
// the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in
// writing, software distributed under the License is
// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See
// the License for the specific language governing
// permissions and limitations under the License.
//----------------------------------------------------------------------
//This is dummy DUT.
module dut_dummy(
input wire ubus_req_master_0,
output reg ubus_gnt_master_0,
input wire ubus_req_master_1,
output reg ubus_gnt_master_1,
input wire ubus_clock,
input wire ubus_reset,
input wire [15:0] ubus_addr,
input wire [1:0] ubus_size,
output reg ubus_read,
output reg ubus_write,
output reg ubus_start,
input wire ubus_bip,
inout wire [7:0] ubus_data,
input wire ubus_wait,
input wire ubus_error);
bit[2:0] st;
// Basic arbiter, supports two masters, 0 has priority over 1
always @(posedge ubus_clock or posedge ubus_reset) begin
if(ubus_reset) begin
ubus_start <= 1'b0;
st<=3'h0;
end
else
case(st)
0: begin //Begin out of Reset
ubus_start <= 1'b1;
st<=3'h3;
end
3: begin //Start state
ubus_start <= 1'b0;
if((ubus_gnt_master_0==0) && (ubus_gnt_master_1==0)) begin
st<=3'h4;
end
else
st<=3'h1;
end
4: begin // No-op state
ubus_start <= 1'b1;
st<=3'h3;
end
1: begin // Addr state
st<=3'h2;
ubus_start <= 1'b0;
end
2: begin // Data state
if((ubus_error==1) || ((ubus_bip==0) && (ubus_wait==0))) begin
st<=3'h3;
ubus_start <= 1'b1;
end
else begin
st<=3'h2;
ubus_start <= 1'b0;
end
end
endcase
end
always @(negedge ubus_clock or posedge ubus_reset) begin
if(ubus_reset == 1'b1) begin
ubus_gnt_master_0 <= 0;
ubus_gnt_master_1 <= 0;
end
else begin
if(ubus_start && ubus_req_master_0) begin
ubus_gnt_master_0 <= 1;
ubus_gnt_master_1 <= 0;
end
else if(ubus_start && !ubus_req_master_0 && ubus_req_master_1) begin
ubus_gnt_master_0 <= 0;
ubus_gnt_master_1 <= 1;
end
else begin
ubus_gnt_master_0 <= 0;
ubus_gnt_master_1 <= 0;
end
end
end
always @(posedge ubus_clock or posedge ubus_reset) begin
if(ubus_reset) begin
ubus_read <= 1'bZ;
ubus_write <= 1'bZ;
end
else if(ubus_start && !ubus_gnt_master_0 && !ubus_gnt_master_1) begin
ubus_read <= 1'b0;
ubus_write <= 1'b0;
end
else begin
ubus_read <= 1'bZ;
ubus_write <= 1'bZ;
end
end
endmodule
|
// generates a command impulse (length one clock period) if command changes
module command_decoder(
// INPUTS
clk,
reset_n,
command,
//go_step_test_ack,
//request_clear_mem_ack,
//test_abort_ack,
// OUTPUTS
request_clear_mem,
go_step_tck,
go_step_sxr,
go_step_test,
test_halt,
test_abort
);
`include "parameters_global.v"
input clk;
input reset_n;
input [`command_width-1:0] command;
output reg request_clear_mem;
//input request_clear_mem_ack;
output reg go_step_tck;
output reg go_step_sxr;
output reg go_step_test;
output reg test_halt;
output reg test_abort;
//input go_step_test_ack;
reg [`command_width-1:0] command_previous;
always @(posedge clk or negedge reset_n)
begin
if (~reset_n)
begin
request_clear_mem <= #`DEL 1'b0;
go_step_tck <= #`DEL 1'b0;
go_step_sxr <= #`DEL 1'b0;
go_step_test <= #`DEL 1'b0;
test_halt <= #`DEL 1'b0;
test_abort <= #`DEL 1'b0;
command_previous <= #`DEL cmd_null;
end
else
begin
command_previous <= #`DEL command;
// if command changes, evaluate command
// if no change, evaluate acknowledge signals and clear command output flag
if (command_previous != command)
begin
case (command) // synthesis parallel_case
cmd_clear_ram:
begin
request_clear_mem <= #`DEL 1'b1;
test_abort <= #`DEL 1'b1;
end
cmd_step_tck:
begin
go_step_tck <= #`DEL 1'b1;
test_abort <= #`DEL 1'b0;
end
cmd_step_sxr:
begin
go_step_sxr <= #`DEL 1'b1;
test_abort <= #`DEL 1'b0;
end
cmd_step_test:
begin
go_step_test <= #`DEL 1'b1;
test_abort <= #`DEL 1'b0;
end
cmd_null:
begin
request_clear_mem <= #`DEL 1'b0;
go_step_tck <= #`DEL 1'b0;
go_step_sxr <= #`DEL 1'b0;
go_step_test <= #`DEL 1'b0;
test_abort <= #`DEL 1'b0;
end
cmd_test_halt:
begin
test_halt <= #`DEL 1'b1;
end
cmd_test_abort:
begin
test_abort <= #`DEL 1'b1;
end
default:
begin
request_clear_mem <= #`DEL 1'b0;
go_step_tck <= #`DEL 1'b0;
go_step_sxr <= #`DEL 1'b0;
go_step_test <= #`DEL 1'b0;
test_halt <= #`DEL 1'b0;
test_abort <= #`DEL 1'b0;
end
endcase
end
else
begin
request_clear_mem <= #`DEL 1'b0;
go_step_tck <= #`DEL 1'b0;
go_step_sxr <= #`DEL 1'b0;
go_step_test <= #`DEL 1'b0;
test_halt <= #`DEL 1'b0;
test_abort <= #`DEL 1'b0;
end
end
end
endmodule
|
/***********************************************************************
*
* Copyright (C) 2011 Adrian Wise
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*
***********************************************************************
*
* This is a testbench exercising gate-level modelling of DTL gates,
* distilled down (as a test-case) from a much larger design.
* The gates can only pull down strongly to ground and have a weak
* pull-up.
*
* This illustrates a problem in the git master branch as of 24 December
* 2011, where a gate that does not pull-up strongly cannot drive a bit
* of a bus (to either logic level), but can drive a single-bit wire
* correctly.
*
* This is an extended version of the test case provided with the
* bug report, to cover part selects with a non-zero base, and to
* make the error checking a bit more robust.
**********************************************************************/
`timescale 1 ns / 100 ps
module dtl_inv (op, in1);
output op;
input in1;
not (strong0, pull1) #16 not1 (op, in1);
endmodule // dtl_inv
module top;
reg d;
wire w;
wire [1:0] b;
reg pass;
dtl_inv u_1 (.op(w), .in1(d));
dtl_inv u_2 (.op(b[0]), .in1(d));
dtl_inv u_3 (.op(b[1]), .in1(b[0]));
initial begin
pass = 1'b1;
d = 1'b0;
# 100;
if ((w !== 1'b1) || (b[0] !== 1'b1) || (b[1] !== 1'b0)) begin
$display("Failed (w !== b[0]): d = %b, w = %b, b = %b", d, w, b);
pass = 1'b0;
end
d = 1'b1;
# 100;
if ((w !== 1'b0) || (b[0] !== 1'b0) || (b[1] !== 1'b1)) begin
$display("Failed (w !== b[0]): d = %b, w = %b, b = %b", d, w, b);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule // top
|
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * INRIA, CNRS and contributors - Copyright 1999-2018 *)
(* <O___,, * (see CREDITS file for the list of authors) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
Require Import Bool NAxioms NSub NPow NDiv NParity NLog.
(** Derived properties of bitwise operations *)
Module Type NBitsProp
(Import A : NAxiomsSig')
(Import B : NSubProp A)
(Import C : NParityProp A B)
(Import D : NPowProp A B C)
(Import E : NDivProp A B)
(Import F : NLog2Prop A B C D).
Include BoolEqualityFacts A.
Ltac order_nz := try apply pow_nonzero; order'.
Hint Rewrite div_0_l mod_0_l div_1_r mod_1_r : nz.
(** Some properties of power and division *)
Lemma pow_sub_r : forall a b c, a~=0 -> c<=b -> a^(b-c) == a^b / a^c.
Proof.
intros a b c Ha H.
apply div_unique with 0.
generalize (pow_nonzero a c Ha) (le_0_l (a^c)); order'.
nzsimpl. now rewrite <- pow_add_r, add_comm, sub_add.
Qed.
Lemma pow_div_l : forall a b c, b~=0 -> a mod b == 0 ->
(a/b)^c == a^c / b^c.
Proof.
intros a b c Hb H.
apply div_unique with 0.
generalize (pow_nonzero b c Hb) (le_0_l (b^c)); order'.
nzsimpl. rewrite <- pow_mul_l. f_equiv. now apply div_exact.
Qed.
(** An injection from bits [true] and [false] to numbers 1 and 0.
We declare it as a (local) coercion for shorter statements. *)
Definition b2n (b:bool) := if b then 1 else 0.
Local Coercion b2n : bool >-> t.
Instance b2n_proper : Proper (Logic.eq ==> eq) b2n.
Proof. solve_proper. Qed.
Lemma exists_div2 a : exists a' (b:bool), a == 2*a' + b.
Proof.
elim (Even_or_Odd a); [intros (a',H)| intros (a',H)].
exists a'. exists false. now nzsimpl.
exists a'. exists true. now simpl.
Qed.
(** We can compact [testbit_odd_0] [testbit_even_0]
[testbit_even_succ] [testbit_odd_succ] in only two lemmas. *)
Lemma testbit_0_r a (b:bool) : testbit (2*a+b) 0 = b.
Proof.
destruct b; simpl; rewrite ?add_0_r.
apply testbit_odd_0.
apply testbit_even_0.
Qed.
Lemma testbit_succ_r a (b:bool) n :
testbit (2*a+b) (succ n) = testbit a n.
Proof.
destruct b; simpl; rewrite ?add_0_r.
apply testbit_odd_succ, le_0_l.
apply testbit_even_succ, le_0_l.
Qed.
(** Alternative caracterisations of [testbit] *)
(** This concise equation could have been taken as specification
for testbit in the interface, but it would have been hard to
implement with little initial knowledge about div and mod *)
Lemma testbit_spec' a n : a.[n] == (a / 2^n) mod 2.
Proof.
revert a. induct n.
intros a. nzsimpl.
destruct (exists_div2 a) as (a' & b & H). rewrite H at 1.
rewrite testbit_0_r. apply mod_unique with a'; trivial.
destruct b; order'.
intros n IH a.
destruct (exists_div2 a) as (a' & b & H). rewrite H at 1.
rewrite testbit_succ_r, IH. f_equiv.
rewrite pow_succ_r', <- div_div by order_nz. f_equiv.
apply div_unique with b; trivial.
destruct b; order'.
Qed.
(** This caracterisation that uses only basic operations and
power was initially taken as specification for testbit.
We describe [a] as having a low part and a high part, with
the corresponding bit in the middle. This caracterisation
is moderatly complex to implement, but also moderately
usable... *)
Lemma testbit_spec a n :
exists l h, 0<=l<2^n /\ a == l + (a.[n] + 2*h)*2^n.
Proof.
exists (a mod 2^n). exists (a / 2^n / 2). split.
split; [apply le_0_l | apply mod_upper_bound; order_nz].
rewrite add_comm, mul_comm, (add_comm a.[n]).
rewrite (div_mod a (2^n)) at 1 by order_nz. do 2 f_equiv.
rewrite testbit_spec'. apply div_mod. order'.
Qed.
Lemma testbit_true : forall a n,
a.[n] = true <-> (a / 2^n) mod 2 == 1.
Proof.
intros a n.
rewrite <- testbit_spec'; destruct a.[n]; split; simpl; now try order'.
Qed.
Lemma testbit_false : forall a n,
a.[n] = false <-> (a / 2^n) mod 2 == 0.
Proof.
intros a n.
rewrite <- testbit_spec'; destruct a.[n]; split; simpl; now try order'.
Qed.
Lemma testbit_eqb : forall a n,
a.[n] = eqb ((a / 2^n) mod 2) 1.
Proof.
intros a n.
apply eq_true_iff_eq. now rewrite testbit_true, eqb_eq.
Qed.
(** Results about the injection [b2n] *)
Lemma b2n_inj : forall (a0 b0:bool), a0 == b0 -> a0 = b0.
Proof.
intros [|] [|]; simpl; trivial; order'.
Qed.
Lemma add_b2n_double_div2 : forall (a0:bool) a, (a0+2*a)/2 == a.
Proof.
intros a0 a. rewrite mul_comm, div_add by order'.
now rewrite div_small, add_0_l by (destruct a0; order').
Qed.
Lemma add_b2n_double_bit0 : forall (a0:bool) a, (a0+2*a).[0] = a0.
Proof.
intros a0 a. apply b2n_inj.
rewrite testbit_spec'. nzsimpl. rewrite mul_comm, mod_add by order'.
now rewrite mod_small by (destruct a0; order').
Qed.
Lemma b2n_div2 : forall (a0:bool), a0/2 == 0.
Proof.
intros a0. rewrite <- (add_b2n_double_div2 a0 0). now nzsimpl.
Qed.
Lemma b2n_bit0 : forall (a0:bool), a0.[0] = a0.
Proof.
intros a0. rewrite <- (add_b2n_double_bit0 a0 0) at 2. now nzsimpl.
Qed.
(** The specification of testbit by low and high parts is complete *)
Lemma testbit_unique : forall a n (a0:bool) l h,
l<2^n -> a == l + (a0 + 2*h)*2^n -> a.[n] = a0.
Proof.
intros a n a0 l h Hl EQ.
apply b2n_inj. rewrite testbit_spec' by trivial.
symmetry. apply mod_unique with h. destruct a0; simpl; order'.
symmetry. apply div_unique with l; trivial.
now rewrite add_comm, (add_comm _ a0), mul_comm.
Qed.
(** All bits of number 0 are 0 *)
Lemma bits_0 : forall n, 0.[n] = false.
Proof.
intros n. apply testbit_false. nzsimpl; order_nz.
Qed.
(** Various ways to refer to the lowest bit of a number *)
Lemma bit0_odd : forall a, a.[0] = odd a.
Proof.
intros. symmetry.
destruct (exists_div2 a) as (a' & b & EQ).
rewrite EQ, testbit_0_r, add_comm, odd_add_mul_2.
destruct b; simpl; apply odd_1 || apply odd_0.
Qed.
Lemma bit0_eqb : forall a, a.[0] = eqb (a mod 2) 1.
Proof.
intros a. rewrite testbit_eqb. now nzsimpl.
Qed.
Lemma bit0_mod : forall a, a.[0] == a mod 2.
Proof.
intros a. rewrite testbit_spec'. now nzsimpl.
Qed.
(** Hence testing a bit is equivalent to shifting and testing parity *)
Lemma testbit_odd : forall a n, a.[n] = odd (a>>n).
Proof.
intros. now rewrite <- bit0_odd, shiftr_spec, add_0_l.
Qed.
(** [log2] gives the highest nonzero bit *)
Lemma bit_log2 : forall a, a~=0 -> a.[log2 a] = true.
Proof.
intros a Ha.
assert (Ha' : 0 < a) by (generalize (le_0_l a); order).
destruct (log2_spec_alt a Ha') as (r & EQ & (_,Hr)).
rewrite EQ at 1.
rewrite testbit_true, add_comm.
rewrite <- (mul_1_l (2^log2 a)) at 1.
rewrite div_add by order_nz.
rewrite div_small by trivial.
rewrite add_0_l. apply mod_small. order'.
Qed.
Lemma bits_above_log2 : forall a n, log2 a < n ->
a.[n] = false.
Proof.
intros a n H.
rewrite testbit_false.
rewrite div_small. nzsimpl; order'.
apply log2_lt_cancel. rewrite log2_pow2; trivial using le_0_l.
Qed.
(** Hence the number of bits of [a] is [1+log2 a]
(see [Pos.size_nat] and [Pos.size]).
*)
(** Testing bits after division or multiplication by a power of two *)
Lemma div2_bits : forall a n, (a/2).[n] = a.[S n].
Proof.
intros. apply eq_true_iff_eq.
rewrite 2 testbit_true.
rewrite pow_succ_r by apply le_0_l.
now rewrite div_div by order_nz.
Qed.
Lemma div_pow2_bits : forall a n m, (a/2^n).[m] = a.[m+n].
Proof.
intros a n. revert a. induct n.
intros a m. now nzsimpl.
intros n IH a m. nzsimpl; try apply le_0_l.
rewrite <- div_div by order_nz.
now rewrite IH, div2_bits.
Qed.
Lemma double_bits_succ : forall a n, (2*a).[S n] = a.[n].
Proof.
intros. rewrite <- div2_bits. now rewrite mul_comm, div_mul by order'.
Qed.
Lemma mul_pow2_bits_add : forall a n m, (a*2^n).[m+n] = a.[m].
Proof.
intros. rewrite <- div_pow2_bits. now rewrite div_mul by order_nz.
Qed.
Lemma mul_pow2_bits_high : forall a n m, n<=m -> (a*2^n).[m] = a.[m-n].
Proof.
intros.
rewrite <- (sub_add n m) at 1 by order'.
now rewrite mul_pow2_bits_add.
Qed.
Lemma mul_pow2_bits_low : forall a n m, m<n -> (a*2^n).[m] = false.
Proof.
intros. apply testbit_false.
rewrite <- (sub_add m n) by order'. rewrite pow_add_r, mul_assoc.
rewrite div_mul by order_nz.
rewrite <- (succ_pred (n-m)). rewrite pow_succ_r.
now rewrite (mul_comm 2), mul_assoc, mod_mul by order'.
apply lt_le_pred.
apply sub_gt in H. generalize (le_0_l (n-m)); order.
now apply sub_gt.
Qed.
(** Selecting the low part of a number can be done by a modulo *)
Lemma mod_pow2_bits_high : forall a n m, n<=m ->
(a mod 2^n).[m] = false.
Proof.
intros a n m H.
destruct (eq_0_gt_0_cases (a mod 2^n)) as [EQ|LT].
now rewrite EQ, bits_0.
apply bits_above_log2.
apply lt_le_trans with n; trivial.
apply log2_lt_pow2; trivial.
apply mod_upper_bound; order_nz.
Qed.
Lemma mod_pow2_bits_low : forall a n m, m<n ->
(a mod 2^n).[m] = a.[m].
Proof.
intros a n m H.
rewrite testbit_eqb.
rewrite <- (mod_add _ (2^(P (n-m))*(a/2^n))) by order'.
rewrite <- div_add by order_nz.
rewrite (mul_comm _ 2), mul_assoc, <- pow_succ_r', succ_pred
by now apply sub_gt.
rewrite mul_comm, mul_assoc, <- pow_add_r, (add_comm m), sub_add
by order.
rewrite add_comm, <- div_mod by order_nz.
symmetry. apply testbit_eqb.
Qed.
(** We now prove that having the same bits implies equality.
For that we use a notion of equality over functional
streams of bits. *)
Definition eqf (f g:t -> bool) := forall n:t, f n = g n.
Instance eqf_equiv : Equivalence eqf.
Proof.
split; congruence.
Qed.
Local Infix "===" := eqf (at level 70, no associativity).
Instance testbit_eqf : Proper (eq==>eqf) testbit.
Proof.
intros a a' Ha n. now rewrite Ha.
Qed.
(** Only zero corresponds to the always-false stream. *)
Lemma bits_inj_0 :
forall a, (forall n, a.[n] = false) -> a == 0.
Proof.
intros a H. destruct (eq_decidable a 0) as [EQ|NEQ]; trivial.
apply bit_log2 in NEQ. now rewrite H in NEQ.
Qed.
(** If two numbers produce the same stream of bits, they are equal. *)
Lemma bits_inj : forall a b, testbit a === testbit b -> a == b.
Proof.
intros a. pattern a.
apply strong_right_induction with 0;[solve_proper|clear a|apply le_0_l].
intros a _ IH b H.
destruct (eq_0_gt_0_cases a) as [EQ|LT].
rewrite EQ in H |- *. symmetry. apply bits_inj_0.
intros n. now rewrite <- H, bits_0.
rewrite (div_mod a 2), (div_mod b 2) by order'.
f_equiv; [ | now rewrite <- 2 bit0_mod, H].
f_equiv.
apply IH; trivial using le_0_l.
apply div_lt; order'.
intro n. rewrite 2 div2_bits. apply H.
Qed.
Lemma bits_inj_iff : forall a b, testbit a === testbit b <-> a == b.
Proof.
split. apply bits_inj. intros EQ; now rewrite EQ.
Qed.
Hint Rewrite lxor_spec lor_spec land_spec ldiff_spec bits_0 : bitwise.
Ltac bitwise := apply bits_inj; intros ?m; autorewrite with bitwise.
(** The streams of bits that correspond to a natural numbers are
exactly the ones that are always 0 after some point *)
Lemma are_bits : forall (f:t->bool), Proper (eq==>Logic.eq) f ->
((exists n, f === testbit n) <->
(exists k, forall m, k<=m -> f m = false)).
Proof.
intros f Hf. split.
intros (a,H).
exists (S (log2 a)). intros m Hm. apply le_succ_l in Hm.
rewrite H, bits_above_log2; trivial using lt_succ_diag_r.
intros (k,Hk).
revert f Hf Hk. induct k.
intros f Hf H0.
exists 0. intros m. rewrite bits_0, H0; trivial. apply le_0_l.
intros k IH f Hf Hk.
destruct (IH (fun m => f (S m))) as (n, Hn).
solve_proper.
intros m Hm. apply Hk. now rewrite <- succ_le_mono.
exists (f 0 + 2*n). intros m.
destruct (zero_or_succ m) as [Hm|(m', Hm)]; rewrite Hm.
symmetry. apply add_b2n_double_bit0.
rewrite Hn, <- div2_bits.
rewrite mul_comm, div_add, b2n_div2, add_0_l; trivial. order'.
Qed.
(** Properties of shifts *)
Lemma shiftr_spec' : forall a n m, (a >> n).[m] = a.[m+n].
Proof.
intros. apply shiftr_spec. apply le_0_l.
Qed.
Lemma shiftl_spec_high' : forall a n m, n<=m -> (a << n).[m] = a.[m-n].
Proof.
intros. apply shiftl_spec_high; trivial. apply le_0_l.
Qed.
Lemma shiftr_div_pow2 : forall a n, a >> n == a / 2^n.
Proof.
intros. bitwise. rewrite shiftr_spec'.
symmetry. apply div_pow2_bits.
Qed.
Lemma shiftl_mul_pow2 : forall a n, a << n == a * 2^n.
Proof.
intros. bitwise.
destruct (le_gt_cases n m) as [H|H].
now rewrite shiftl_spec_high', mul_pow2_bits_high.
now rewrite shiftl_spec_low, mul_pow2_bits_low.
Qed.
Lemma shiftl_spec_alt : forall a n m, (a << n).[m+n] = a.[m].
Proof.
intros. now rewrite shiftl_mul_pow2, mul_pow2_bits_add.
Qed.
Instance shiftr_wd : Proper (eq==>eq==>eq) shiftr.
Proof.
intros a a' Ha b b' Hb. now rewrite 2 shiftr_div_pow2, Ha, Hb.
Qed.
Instance shiftl_wd : Proper (eq==>eq==>eq) shiftl.
Proof.
intros a a' Ha b b' Hb. now rewrite 2 shiftl_mul_pow2, Ha, Hb.
Qed.
Lemma shiftl_shiftl : forall a n m,
(a << n) << m == a << (n+m).
Proof.
intros. now rewrite !shiftl_mul_pow2, pow_add_r, mul_assoc.
Qed.
Lemma shiftr_shiftr : forall a n m,
(a >> n) >> m == a >> (n+m).
Proof.
intros.
now rewrite !shiftr_div_pow2, pow_add_r, div_div by order_nz.
Qed.
Lemma shiftr_shiftl_l : forall a n m, m<=n ->
(a << n) >> m == a << (n-m).
Proof.
intros.
rewrite shiftr_div_pow2, !shiftl_mul_pow2.
rewrite <- (sub_add m n) at 1 by trivial.
now rewrite pow_add_r, mul_assoc, div_mul by order_nz.
Qed.
Lemma shiftr_shiftl_r : forall a n m, n<=m ->
(a << n) >> m == a >> (m-n).
Proof.
intros.
rewrite !shiftr_div_pow2, shiftl_mul_pow2.
rewrite <- (sub_add n m) at 1 by trivial.
rewrite pow_add_r, (mul_comm (2^(m-n))).
now rewrite <- div_div, div_mul by order_nz.
Qed.
(** shifts and constants *)
Lemma shiftl_1_l : forall n, 1 << n == 2^n.
Proof.
intros. now rewrite shiftl_mul_pow2, mul_1_l.
Qed.
Lemma shiftl_0_r : forall a, a << 0 == a.
Proof.
intros. rewrite shiftl_mul_pow2. now nzsimpl.
Qed.
Lemma shiftr_0_r : forall a, a >> 0 == a.
Proof.
intros. rewrite shiftr_div_pow2. now nzsimpl.
Qed.
Lemma shiftl_0_l : forall n, 0 << n == 0.
Proof.
intros. rewrite shiftl_mul_pow2. now nzsimpl.
Qed.
Lemma shiftr_0_l : forall n, 0 >> n == 0.
Proof.
intros. rewrite shiftr_div_pow2. nzsimpl; order_nz.
Qed.
Lemma shiftl_eq_0_iff : forall a n, a << n == 0 <-> a == 0.
Proof.
intros a n. rewrite shiftl_mul_pow2. rewrite eq_mul_0. split.
intros [H | H]; trivial. contradict H; order_nz.
intros H. now left.
Qed.
Lemma shiftr_eq_0_iff : forall a n,
a >> n == 0 <-> a==0 \/ (0<a /\ log2 a < n).
Proof.
intros a n.
rewrite shiftr_div_pow2, div_small_iff by order_nz.
destruct (eq_0_gt_0_cases a) as [EQ|LT].
rewrite EQ. split. now left. intros _.
assert (H : 2~=0) by order'.
generalize (pow_nonzero 2 n H) (le_0_l (2^n)); order.
rewrite log2_lt_pow2; trivial.
split. right; split; trivial. intros [H|[_ H]]; now order.
Qed.
Lemma shiftr_eq_0 : forall a n, log2 a < n -> a >> n == 0.
Proof.
intros a n H. rewrite shiftr_eq_0_iff.
destruct (eq_0_gt_0_cases a) as [EQ|LT]. now left. right; now split.
Qed.
(** Properties of [div2]. *)
Lemma div2_div : forall a, div2 a == a/2.
Proof.
intros. rewrite div2_spec, shiftr_div_pow2. now nzsimpl.
Qed.
Instance div2_wd : Proper (eq==>eq) div2.
Proof.
intros a a' Ha. now rewrite 2 div2_div, Ha.
Qed.
Lemma div2_odd : forall a, a == 2*(div2 a) + odd a.
Proof.
intros a. rewrite div2_div, <- bit0_odd, bit0_mod.
apply div_mod. order'.
Qed.
(** Properties of [lxor] and others, directly deduced
from properties of [xorb] and others. *)
Instance lxor_wd : Proper (eq ==> eq ==> eq) lxor.
Proof.
intros a a' Ha b b' Hb. bitwise. now rewrite Ha, Hb.
Qed.
Instance land_wd : Proper (eq ==> eq ==> eq) land.
Proof.
intros a a' Ha b b' Hb. bitwise. now rewrite Ha, Hb.
Qed.
Instance lor_wd : Proper (eq ==> eq ==> eq) lor.
Proof.
intros a a' Ha b b' Hb. bitwise. now rewrite Ha, Hb.
Qed.
Instance ldiff_wd : Proper (eq ==> eq ==> eq) ldiff.
Proof.
intros a a' Ha b b' Hb. bitwise. now rewrite Ha, Hb.
Qed.
Lemma lxor_eq : forall a a', lxor a a' == 0 -> a == a'.
Proof.
intros a a' H. bitwise. apply xorb_eq.
now rewrite <- lxor_spec, H, bits_0.
Qed.
Lemma lxor_nilpotent : forall a, lxor a a == 0.
Proof.
intros. bitwise. apply xorb_nilpotent.
Qed.
Lemma lxor_eq_0_iff : forall a a', lxor a a' == 0 <-> a == a'.
Proof.
split. apply lxor_eq. intros EQ; rewrite EQ; apply lxor_nilpotent.
Qed.
Lemma lxor_0_l : forall a, lxor 0 a == a.
Proof.
intros. bitwise. apply xorb_false_l.
Qed.
Lemma lxor_0_r : forall a, lxor a 0 == a.
Proof.
intros. bitwise. apply xorb_false_r.
Qed.
Lemma lxor_comm : forall a b, lxor a b == lxor b a.
Proof.
intros. bitwise. apply xorb_comm.
Qed.
Lemma lxor_assoc :
forall a b c, lxor (lxor a b) c == lxor a (lxor b c).
Proof.
intros. bitwise. apply xorb_assoc.
Qed.
Lemma lor_0_l : forall a, lor 0 a == a.
Proof.
intros. bitwise. trivial.
Qed.
Lemma lor_0_r : forall a, lor a 0 == a.
Proof.
intros. bitwise. apply orb_false_r.
Qed.
Lemma lor_comm : forall a b, lor a b == lor b a.
Proof.
intros. bitwise. apply orb_comm.
Qed.
Lemma lor_assoc :
forall a b c, lor a (lor b c) == lor (lor a b) c.
Proof.
intros. bitwise. apply orb_assoc.
Qed.
Lemma lor_diag : forall a, lor a a == a.
Proof.
intros. bitwise. apply orb_diag.
Qed.
Lemma lor_eq_0_l : forall a b, lor a b == 0 -> a == 0.
Proof.
intros a b H. bitwise.
apply (orb_false_iff a.[m] b.[m]).
now rewrite <- lor_spec, H, bits_0.
Qed.
Lemma lor_eq_0_iff : forall a b, lor a b == 0 <-> a == 0 /\ b == 0.
Proof.
intros a b. split.
split. now apply lor_eq_0_l in H.
rewrite lor_comm in H. now apply lor_eq_0_l in H.
intros (EQ,EQ'). now rewrite EQ, lor_0_l.
Qed.
Lemma land_0_l : forall a, land 0 a == 0.
Proof.
intros. bitwise. trivial.
Qed.
Lemma land_0_r : forall a, land a 0 == 0.
Proof.
intros. bitwise. apply andb_false_r.
Qed.
Lemma land_comm : forall a b, land a b == land b a.
Proof.
intros. bitwise. apply andb_comm.
Qed.
Lemma land_assoc :
forall a b c, land a (land b c) == land (land a b) c.
Proof.
intros. bitwise. apply andb_assoc.
Qed.
Lemma land_diag : forall a, land a a == a.
Proof.
intros. bitwise. apply andb_diag.
Qed.
Lemma ldiff_0_l : forall a, ldiff 0 a == 0.
Proof.
intros. bitwise. trivial.
Qed.
Lemma ldiff_0_r : forall a, ldiff a 0 == a.
Proof.
intros. bitwise. now rewrite andb_true_r.
Qed.
Lemma ldiff_diag : forall a, ldiff a a == 0.
Proof.
intros. bitwise. apply andb_negb_r.
Qed.
Lemma lor_land_distr_l : forall a b c,
lor (land a b) c == land (lor a c) (lor b c).
Proof.
intros. bitwise. apply orb_andb_distrib_l.
Qed.
Lemma lor_land_distr_r : forall a b c,
lor a (land b c) == land (lor a b) (lor a c).
Proof.
intros. bitwise. apply orb_andb_distrib_r.
Qed.
Lemma land_lor_distr_l : forall a b c,
land (lor a b) c == lor (land a c) (land b c).
Proof.
intros. bitwise. apply andb_orb_distrib_l.
Qed.
Lemma land_lor_distr_r : forall a b c,
land a (lor b c) == lor (land a b) (land a c).
Proof.
intros. bitwise. apply andb_orb_distrib_r.
Qed.
Lemma ldiff_ldiff_l : forall a b c,
ldiff (ldiff a b) c == ldiff a (lor b c).
Proof.
intros. bitwise. now rewrite negb_orb, andb_assoc.
Qed.
Lemma lor_ldiff_and : forall a b,
lor (ldiff a b) (land a b) == a.
Proof.
intros. bitwise.
now rewrite <- andb_orb_distrib_r, orb_comm, orb_negb_r, andb_true_r.
Qed.
Lemma land_ldiff : forall a b,
land (ldiff a b) b == 0.
Proof.
intros. bitwise.
now rewrite <-andb_assoc, (andb_comm (negb _)), andb_negb_r, andb_false_r.
Qed.
(** Properties of [setbit] and [clearbit] *)
Definition setbit a n := lor a (1<<n).
Definition clearbit a n := ldiff a (1<<n).
Lemma setbit_spec' : forall a n, setbit a n == lor a (2^n).
Proof.
intros. unfold setbit. now rewrite shiftl_1_l.
Qed.
Lemma clearbit_spec' : forall a n, clearbit a n == ldiff a (2^n).
Proof.
intros. unfold clearbit. now rewrite shiftl_1_l.
Qed.
Instance setbit_wd : Proper (eq==>eq==>eq) setbit.
Proof. unfold setbit. solve_proper. Qed.
Instance clearbit_wd : Proper (eq==>eq==>eq) clearbit.
Proof. unfold clearbit. solve_proper. Qed.
Lemma pow2_bits_true : forall n, (2^n).[n] = true.
Proof.
intros. rewrite <- (mul_1_l (2^n)). rewrite <- (add_0_l n) at 2.
now rewrite mul_pow2_bits_add, bit0_odd, odd_1.
Qed.
Lemma pow2_bits_false : forall n m, n~=m -> (2^n).[m] = false.
Proof.
intros.
rewrite <- (mul_1_l (2^n)).
destruct (le_gt_cases n m).
rewrite mul_pow2_bits_high; trivial.
rewrite <- (succ_pred (m-n)) by (apply sub_gt; order).
now rewrite <- div2_bits, div_small, bits_0 by order'.
rewrite mul_pow2_bits_low; trivial.
Qed.
Lemma pow2_bits_eqb : forall n m, (2^n).[m] = eqb n m.
Proof.
intros. apply eq_true_iff_eq. rewrite eqb_eq. split.
destruct (eq_decidable n m) as [H|H]. trivial.
now rewrite (pow2_bits_false _ _ H).
intros EQ. rewrite EQ. apply pow2_bits_true.
Qed.
Lemma setbit_eqb : forall a n m,
(setbit a n).[m] = eqb n m || a.[m].
Proof.
intros. now rewrite setbit_spec', lor_spec, pow2_bits_eqb, orb_comm.
Qed.
Lemma setbit_iff : forall a n m,
(setbit a n).[m] = true <-> n==m \/ a.[m] = true.
Proof.
intros. now rewrite setbit_eqb, orb_true_iff, eqb_eq.
Qed.
Lemma setbit_eq : forall a n, (setbit a n).[n] = true.
Proof.
intros. apply setbit_iff. now left.
Qed.
Lemma setbit_neq : forall a n m, n~=m ->
(setbit a n).[m] = a.[m].
Proof.
intros a n m H. rewrite setbit_eqb.
rewrite <- eqb_eq in H. apply not_true_is_false in H. now rewrite H.
Qed.
Lemma clearbit_eqb : forall a n m,
(clearbit a n).[m] = a.[m] && negb (eqb n m).
Proof.
intros. now rewrite clearbit_spec', ldiff_spec, pow2_bits_eqb.
Qed.
Lemma clearbit_iff : forall a n m,
(clearbit a n).[m] = true <-> a.[m] = true /\ n~=m.
Proof.
intros. rewrite clearbit_eqb, andb_true_iff, <- eqb_eq.
now rewrite negb_true_iff, not_true_iff_false.
Qed.
Lemma clearbit_eq : forall a n, (clearbit a n).[n] = false.
Proof.
intros. rewrite clearbit_eqb, (proj2 (eqb_eq _ _) (eq_refl n)).
apply andb_false_r.
Qed.
Lemma clearbit_neq : forall a n m, n~=m ->
(clearbit a n).[m] = a.[m].
Proof.
intros a n m H. rewrite clearbit_eqb.
rewrite <- eqb_eq in H. apply not_true_is_false in H. rewrite H.
apply andb_true_r.
Qed.
(** Shifts of bitwise operations *)
Lemma shiftl_lxor : forall a b n,
(lxor a b) << n == lxor (a << n) (b << n).
Proof.
intros. bitwise.
destruct (le_gt_cases n m).
now rewrite !shiftl_spec_high', lxor_spec.
now rewrite !shiftl_spec_low.
Qed.
Lemma shiftr_lxor : forall a b n,
(lxor a b) >> n == lxor (a >> n) (b >> n).
Proof.
intros. bitwise. now rewrite !shiftr_spec', lxor_spec.
Qed.
Lemma shiftl_land : forall a b n,
(land a b) << n == land (a << n) (b << n).
Proof.
intros. bitwise.
destruct (le_gt_cases n m).
now rewrite !shiftl_spec_high', land_spec.
now rewrite !shiftl_spec_low.
Qed.
Lemma shiftr_land : forall a b n,
(land a b) >> n == land (a >> n) (b >> n).
Proof.
intros. bitwise. now rewrite !shiftr_spec', land_spec.
Qed.
Lemma shiftl_lor : forall a b n,
(lor a b) << n == lor (a << n) (b << n).
Proof.
intros. bitwise.
destruct (le_gt_cases n m).
now rewrite !shiftl_spec_high', lor_spec.
now rewrite !shiftl_spec_low.
Qed.
Lemma shiftr_lor : forall a b n,
(lor a b) >> n == lor (a >> n) (b >> n).
Proof.
intros. bitwise. now rewrite !shiftr_spec', lor_spec.
Qed.
Lemma shiftl_ldiff : forall a b n,
(ldiff a b) << n == ldiff (a << n) (b << n).
Proof.
intros. bitwise.
destruct (le_gt_cases n m).
now rewrite !shiftl_spec_high', ldiff_spec.
now rewrite !shiftl_spec_low.
Qed.
Lemma shiftr_ldiff : forall a b n,
(ldiff a b) >> n == ldiff (a >> n) (b >> n).
Proof.
intros. bitwise. now rewrite !shiftr_spec', ldiff_spec.
Qed.
(** We cannot have a function complementing all bits of a number,
otherwise it would have an infinity of bit 1. Nonetheless,
we can design a bounded complement *)
Definition ones n := P (1 << n).
Definition lnot a n := lxor a (ones n).
Instance ones_wd : Proper (eq==>eq) ones.
Proof. unfold ones. solve_proper. Qed.
Instance lnot_wd : Proper (eq==>eq==>eq) lnot.
Proof. unfold lnot. solve_proper. Qed.
Lemma ones_equiv : forall n, ones n == P (2^n).
Proof.
intros; unfold ones; now rewrite shiftl_1_l.
Qed.
Lemma ones_add : forall n m, ones (m+n) == 2^m * ones n + ones m.
Proof.
intros n m. rewrite !ones_equiv.
rewrite <- !sub_1_r, mul_sub_distr_l, mul_1_r, <- pow_add_r.
rewrite add_sub_assoc, sub_add. reflexivity.
apply pow_le_mono_r. order'.
rewrite <- (add_0_r m) at 1. apply add_le_mono_l, le_0_l.
rewrite <- (pow_0_r 2). apply pow_le_mono_r. order'. apply le_0_l.
Qed.
Lemma ones_div_pow2 : forall n m, m<=n -> ones n / 2^m == ones (n-m).
Proof.
intros n m H. symmetry. apply div_unique with (ones m).
rewrite ones_equiv.
apply le_succ_l. rewrite succ_pred; order_nz.
rewrite <- (sub_add m n H) at 1. rewrite (add_comm _ m).
apply ones_add.
Qed.
Lemma ones_mod_pow2 : forall n m, m<=n -> (ones n) mod (2^m) == ones m.
Proof.
intros n m H. symmetry. apply mod_unique with (ones (n-m)).
rewrite ones_equiv.
apply le_succ_l. rewrite succ_pred; order_nz.
rewrite <- (sub_add m n H) at 1. rewrite (add_comm _ m).
apply ones_add.
Qed.
Lemma ones_spec_low : forall n m, m<n -> (ones n).[m] = true.
Proof.
intros. apply testbit_true. rewrite ones_div_pow2 by order.
rewrite <- (pow_1_r 2). rewrite ones_mod_pow2.
rewrite ones_equiv. now nzsimpl'.
apply le_add_le_sub_r. nzsimpl. now apply le_succ_l.
Qed.
Lemma ones_spec_high : forall n m, n<=m -> (ones n).[m] = false.
Proof.
intros.
destruct (eq_0_gt_0_cases n) as [EQ|LT]; rewrite ones_equiv.
now rewrite EQ, pow_0_r, one_succ, pred_succ, bits_0.
apply bits_above_log2.
rewrite log2_pred_pow2; trivial. rewrite <-le_succ_l, succ_pred; order.
Qed.
Lemma ones_spec_iff : forall n m, (ones n).[m] = true <-> m<n.
Proof.
intros. split. intros H.
apply lt_nge. intro H'. apply ones_spec_high in H'.
rewrite H in H'; discriminate.
apply ones_spec_low.
Qed.
Lemma lnot_spec_low : forall a n m, m<n ->
(lnot a n).[m] = negb a.[m].
Proof.
intros. unfold lnot. now rewrite lxor_spec, ones_spec_low.
Qed.
Lemma lnot_spec_high : forall a n m, n<=m ->
(lnot a n).[m] = a.[m].
Proof.
intros. unfold lnot. now rewrite lxor_spec, ones_spec_high, xorb_false_r.
Qed.
Lemma lnot_involutive : forall a n, lnot (lnot a n) n == a.
Proof.
intros a n. bitwise.
destruct (le_gt_cases n m).
now rewrite 2 lnot_spec_high.
now rewrite 2 lnot_spec_low, negb_involutive.
Qed.
Lemma lnot_0_l : forall n, lnot 0 n == ones n.
Proof.
intros. unfold lnot. apply lxor_0_l.
Qed.
Lemma lnot_ones : forall n, lnot (ones n) n == 0.
Proof.
intros. unfold lnot. apply lxor_nilpotent.
Qed.
(** Bounded complement and other operations *)
Lemma lor_ones_low : forall a n, log2 a < n ->
lor a (ones n) == ones n.
Proof.
intros a n H. bitwise. destruct (le_gt_cases n m).
rewrite ones_spec_high, bits_above_log2; trivial.
now apply lt_le_trans with n.
now rewrite ones_spec_low, orb_true_r.
Qed.
Lemma land_ones : forall a n, land a (ones n) == a mod 2^n.
Proof.
intros a n. bitwise. destruct (le_gt_cases n m).
now rewrite ones_spec_high, mod_pow2_bits_high, andb_false_r.
now rewrite ones_spec_low, mod_pow2_bits_low, andb_true_r.
Qed.
Lemma land_ones_low : forall a n, log2 a < n ->
land a (ones n) == a.
Proof.
intros; rewrite land_ones. apply mod_small.
apply log2_lt_cancel. rewrite log2_pow2; trivial using le_0_l.
Qed.
Lemma ldiff_ones_r : forall a n,
ldiff a (ones n) == (a >> n) << n.
Proof.
intros a n. bitwise. destruct (le_gt_cases n m).
rewrite ones_spec_high, shiftl_spec_high', shiftr_spec'; trivial.
rewrite sub_add; trivial. apply andb_true_r.
now rewrite ones_spec_low, shiftl_spec_low, andb_false_r.
Qed.
Lemma ldiff_ones_r_low : forall a n, log2 a < n ->
ldiff a (ones n) == 0.
Proof.
intros a n H. bitwise. destruct (le_gt_cases n m).
rewrite ones_spec_high, bits_above_log2; trivial.
now apply lt_le_trans with n.
now rewrite ones_spec_low, andb_false_r.
Qed.
Lemma ldiff_ones_l_low : forall a n, log2 a < n ->
ldiff (ones n) a == lnot a n.
Proof.
intros a n H. bitwise. destruct (le_gt_cases n m).
rewrite ones_spec_high, lnot_spec_high, bits_above_log2; trivial.
now apply lt_le_trans with n.
now rewrite ones_spec_low, lnot_spec_low.
Qed.
Lemma lor_lnot_diag : forall a n,
lor a (lnot a n) == lor a (ones n).
Proof.
intros a n. bitwise.
destruct (le_gt_cases n m).
rewrite lnot_spec_high, ones_spec_high; trivial. now destruct a.[m].
rewrite lnot_spec_low, ones_spec_low; trivial. now destruct a.[m].
Qed.
Lemma lor_lnot_diag_low : forall a n, log2 a < n ->
lor a (lnot a n) == ones n.
Proof.
intros a n H. now rewrite lor_lnot_diag, lor_ones_low.
Qed.
Lemma land_lnot_diag : forall a n,
land a (lnot a n) == ldiff a (ones n).
Proof.
intros a n. bitwise.
destruct (le_gt_cases n m).
rewrite lnot_spec_high, ones_spec_high; trivial. now destruct a.[m].
rewrite lnot_spec_low, ones_spec_low; trivial. now destruct a.[m].
Qed.
Lemma land_lnot_diag_low : forall a n, log2 a < n ->
land a (lnot a n) == 0.
Proof.
intros. now rewrite land_lnot_diag, ldiff_ones_r_low.
Qed.
Lemma lnot_lor_low : forall a b n, log2 a < n -> log2 b < n ->
lnot (lor a b) n == land (lnot a n) (lnot b n).
Proof.
intros a b n Ha Hb. bitwise. destruct (le_gt_cases n m).
rewrite !lnot_spec_high, lor_spec, !bits_above_log2; trivial.
now apply lt_le_trans with n.
now apply lt_le_trans with n.
now rewrite !lnot_spec_low, lor_spec, negb_orb.
Qed.
Lemma lnot_land_low : forall a b n, log2 a < n -> log2 b < n ->
lnot (land a b) n == lor (lnot a n) (lnot b n).
Proof.
intros a b n Ha Hb. bitwise. destruct (le_gt_cases n m).
rewrite !lnot_spec_high, land_spec, !bits_above_log2; trivial.
now apply lt_le_trans with n.
now apply lt_le_trans with n.
now rewrite !lnot_spec_low, land_spec, negb_andb.
Qed.
Lemma ldiff_land_low : forall a b n, log2 a < n ->
ldiff a b == land a (lnot b n).
Proof.
intros a b n Ha. bitwise. destruct (le_gt_cases n m).
rewrite (bits_above_log2 a m). trivial.
now apply lt_le_trans with n.
rewrite !lnot_spec_low; trivial.
Qed.
Lemma lnot_ldiff_low : forall a b n, log2 a < n -> log2 b < n ->
lnot (ldiff a b) n == lor (lnot a n) b.
Proof.
intros a b n Ha Hb. bitwise. destruct (le_gt_cases n m).
rewrite !lnot_spec_high, ldiff_spec, !bits_above_log2; trivial.
now apply lt_le_trans with n.
now apply lt_le_trans with n.
now rewrite !lnot_spec_low, ldiff_spec, negb_andb, negb_involutive.
Qed.
Lemma lxor_lnot_lnot : forall a b n,
lxor (lnot a n) (lnot b n) == lxor a b.
Proof.
intros a b n. bitwise. destruct (le_gt_cases n m).
rewrite !lnot_spec_high; trivial.
rewrite !lnot_spec_low, xorb_negb_negb; trivial.
Qed.
Lemma lnot_lxor_l : forall a b n,
lnot (lxor a b) n == lxor (lnot a n) b.
Proof.
intros a b n. bitwise. destruct (le_gt_cases n m).
rewrite !lnot_spec_high, lxor_spec; trivial.
rewrite !lnot_spec_low, lxor_spec, negb_xorb_l; trivial.
Qed.
Lemma lnot_lxor_r : forall a b n,
lnot (lxor a b) n == lxor a (lnot b n).
Proof.
intros a b n. bitwise. destruct (le_gt_cases n m).
rewrite !lnot_spec_high, lxor_spec; trivial.
rewrite !lnot_spec_low, lxor_spec, negb_xorb_r; trivial.
Qed.
Lemma lxor_lor : forall a b, land a b == 0 ->
lxor a b == lor a b.
Proof.
intros a b H. bitwise.
assert (a.[m] && b.[m] = false)
by now rewrite <- land_spec, H, bits_0.
now destruct a.[m], b.[m].
Qed.
(** Bitwise operations and log2 *)
Lemma log2_bits_unique : forall a n,
a.[n] = true ->
(forall m, n<m -> a.[m] = false) ->
log2 a == n.
Proof.
intros a n H H'.
destruct (eq_0_gt_0_cases a) as [Ha|Ha].
now rewrite Ha, bits_0 in H.
apply le_antisymm; apply le_ngt; intros LT.
specialize (H' _ LT). now rewrite bit_log2 in H' by order.
now rewrite bits_above_log2 in H by order.
Qed.
Lemma log2_shiftr : forall a n, log2 (a >> n) == log2 a - n.
Proof.
intros a n.
destruct (eq_0_gt_0_cases a) as [Ha|Ha].
now rewrite Ha, shiftr_0_l, log2_nonpos, sub_0_l by order.
destruct (lt_ge_cases (log2 a) n).
rewrite shiftr_eq_0, log2_nonpos by order.
symmetry. rewrite sub_0_le; order.
apply log2_bits_unique.
now rewrite shiftr_spec', sub_add, bit_log2 by order.
intros m Hm.
rewrite shiftr_spec'; trivial. apply bits_above_log2; try order.
now apply lt_sub_lt_add_r.
Qed.
Lemma log2_shiftl : forall a n, a~=0 -> log2 (a << n) == log2 a + n.
Proof.
intros a n Ha.
rewrite shiftl_mul_pow2, add_comm by trivial.
apply log2_mul_pow2. generalize (le_0_l a); order. apply le_0_l.
Qed.
Lemma log2_lor : forall a b,
log2 (lor a b) == max (log2 a) (log2 b).
Proof.
assert (AUX : forall a b, a<=b -> log2 (lor a b) == log2 b).
intros a b H.
destruct (eq_0_gt_0_cases a) as [Ha|Ha]. now rewrite Ha, lor_0_l.
apply log2_bits_unique.
now rewrite lor_spec, bit_log2, orb_true_r by order.
intros m Hm. assert (H' := log2_le_mono _ _ H).
now rewrite lor_spec, 2 bits_above_log2 by order.
(* main *)
intros a b. destruct (le_ge_cases a b) as [H|H].
rewrite max_r by now apply log2_le_mono.
now apply AUX.
rewrite max_l by now apply log2_le_mono.
rewrite lor_comm. now apply AUX.
Qed.
Lemma log2_land : forall a b,
log2 (land a b) <= min (log2 a) (log2 b).
Proof.
assert (AUX : forall a b, a<=b -> log2 (land a b) <= log2 a).
intros a b H.
apply le_ngt. intros H'.
destruct (eq_decidable (land a b) 0) as [EQ|NEQ].
rewrite EQ in H'. apply log2_lt_cancel in H'. generalize (le_0_l a); order.
generalize (bit_log2 (land a b) NEQ).
now rewrite land_spec, bits_above_log2.
(* main *)
intros a b.
destruct (le_ge_cases a b) as [H|H].
rewrite min_l by now apply log2_le_mono. now apply AUX.
rewrite min_r by now apply log2_le_mono. rewrite land_comm. now apply AUX.
Qed.
Lemma log2_lxor : forall a b,
log2 (lxor a b) <= max (log2 a) (log2 b).
Proof.
assert (AUX : forall a b, a<=b -> log2 (lxor a b) <= log2 b).
intros a b H.
apply le_ngt. intros H'.
destruct (eq_decidable (lxor a b) 0) as [EQ|NEQ].
rewrite EQ in H'. apply log2_lt_cancel in H'. generalize (le_0_l a); order.
generalize (bit_log2 (lxor a b) NEQ).
rewrite lxor_spec, 2 bits_above_log2; try order. discriminate.
apply le_lt_trans with (log2 b); trivial. now apply log2_le_mono.
(* main *)
intros a b.
destruct (le_ge_cases a b) as [H|H].
rewrite max_r by now apply log2_le_mono. now apply AUX.
rewrite max_l by now apply log2_le_mono. rewrite lxor_comm. now apply AUX.
Qed.
(** Bitwise operations and arithmetical operations *)
Local Notation xor3 a b c := (xorb (xorb a b) c).
Local Notation lxor3 a b c := (lxor (lxor a b) c).
Local Notation nextcarry a b c := ((a&&b) || (c && (a||b))).
Local Notation lnextcarry a b c := (lor (land a b) (land c (lor a b))).
Lemma add_bit0 : forall a b, (a+b).[0] = xorb a.[0] b.[0].
Proof.
intros. now rewrite !bit0_odd, odd_add.
Qed.
Lemma add3_bit0 : forall a b c,
(a+b+c).[0] = xor3 a.[0] b.[0] c.[0].
Proof.
intros. now rewrite !add_bit0.
Qed.
Lemma add3_bits_div2 : forall (a0 b0 c0 : bool),
(a0 + b0 + c0)/2 == nextcarry a0 b0 c0.
Proof.
assert (H : 1+1 == 2) by now nzsimpl'.
intros [|] [|] [|]; simpl; rewrite ?add_0_l, ?add_0_r, ?H;
(apply div_same; order') || (apply div_small; order') || idtac.
symmetry. apply div_unique with 1. order'. now nzsimpl'.
Qed.
Lemma add_carry_div2 : forall a b (c0:bool),
(a + b + c0)/2 == a/2 + b/2 + nextcarry a.[0] b.[0] c0.
Proof.
intros.
rewrite <- add3_bits_div2.
rewrite (add_comm ((a/2)+_)).
rewrite <- div_add by order'.
f_equiv.
rewrite <- !div2_div, mul_comm, mul_add_distr_l.
rewrite (div2_odd a), <- bit0_odd at 1. fold (b2n a.[0]).
rewrite (div2_odd b), <- bit0_odd at 1. fold (b2n b.[0]).
rewrite add_shuffle1.
rewrite <-(add_assoc _ _ c0). apply add_comm.
Qed.
(** The main result concerning addition: we express the bits of the sum
in term of bits of [a] and [b] and of some carry stream which is also
recursively determined by another equation.
*)
Lemma add_carry_bits : forall a b (c0:bool), exists c,
a+b+c0 == lxor3 a b c /\ c/2 == lnextcarry a b c /\ c.[0] = c0.
Proof.
intros a b c0.
(* induction over some n such that [a<2^n] and [b<2^n] *)
set (n:=max a b).
assert (Ha : a<2^n).
apply lt_le_trans with (2^a). apply pow_gt_lin_r, lt_1_2.
apply pow_le_mono_r. order'. unfold n.
destruct (le_ge_cases a b); [rewrite max_r|rewrite max_l]; order'.
assert (Hb : b<2^n).
apply lt_le_trans with (2^b). apply pow_gt_lin_r, lt_1_2.
apply pow_le_mono_r. order'. unfold n.
destruct (le_ge_cases a b); [rewrite max_r|rewrite max_l]; order'.
clearbody n.
revert a b c0 Ha Hb. induct n.
(*base*)
intros a b c0. rewrite !pow_0_r, !one_succ, !lt_succ_r. intros Ha Hb.
exists c0.
setoid_replace a with 0 by (generalize (le_0_l a); order').
setoid_replace b with 0 by (generalize (le_0_l b); order').
rewrite !add_0_l, !lxor_0_l, !lor_0_r, !land_0_r, !lor_0_r.
rewrite b2n_div2, b2n_bit0; now repeat split.
(*step*)
intros n IH a b c0 Ha Hb.
set (c1:=nextcarry a.[0] b.[0] c0).
destruct (IH (a/2) (b/2) c1) as (c & IH1 & IH2 & Hc); clear IH.
apply div_lt_upper_bound; trivial. order'. now rewrite <- pow_succ_r'.
apply div_lt_upper_bound; trivial. order'. now rewrite <- pow_succ_r'.
exists (c0 + 2*c). repeat split.
(* - add *)
bitwise.
destruct (zero_or_succ m) as [EQ|[m' EQ]]; rewrite EQ; clear EQ.
now rewrite add_b2n_double_bit0, add3_bit0, b2n_bit0.
rewrite <- !div2_bits, <- 2 lxor_spec.
f_equiv.
rewrite add_b2n_double_div2, <- IH1. apply add_carry_div2.
(* - carry *)
rewrite add_b2n_double_div2.
bitwise.
destruct (zero_or_succ m) as [EQ|[m' EQ]]; rewrite EQ; clear EQ.
now rewrite add_b2n_double_bit0.
rewrite <- !div2_bits, IH2. autorewrite with bitwise.
now rewrite add_b2n_double_div2.
(* - carry0 *)
apply add_b2n_double_bit0.
Qed.
(** Particular case : the second bit of an addition *)
Lemma add_bit1 : forall a b,
(a+b).[1] = xor3 a.[1] b.[1] (a.[0] && b.[0]).
Proof.
intros a b.
destruct (add_carry_bits a b false) as (c & EQ1 & EQ2 & Hc).
simpl in EQ1; rewrite add_0_r in EQ1. rewrite EQ1.
autorewrite with bitwise. f_equal.
rewrite one_succ, <- div2_bits, EQ2.
autorewrite with bitwise.
rewrite Hc. simpl. apply orb_false_r.
Qed.
(** In an addition, there will be no carries iff there is
no common bits in the numbers to add *)
Lemma nocarry_equiv : forall a b c,
c/2 == lnextcarry a b c -> c.[0] = false ->
(c == 0 <-> land a b == 0).
Proof.
intros a b c H H'.
split. intros EQ; rewrite EQ in *.
rewrite div_0_l in H by order'.
symmetry in H. now apply lor_eq_0_l in H.
intros EQ. rewrite EQ, lor_0_l in H.
apply bits_inj_0.
induct n. trivial.
intros n IH.
rewrite <- div2_bits, H.
autorewrite with bitwise.
now rewrite IH.
Qed.
(** When there is no common bits, the addition is just a xor *)
Lemma add_nocarry_lxor : forall a b, land a b == 0 ->
a+b == lxor a b.
Proof.
intros a b H.
destruct (add_carry_bits a b false) as (c & EQ1 & EQ2 & Hc).
simpl in EQ1; rewrite add_0_r in EQ1. rewrite EQ1.
apply (nocarry_equiv a b c) in H; trivial.
rewrite H. now rewrite lxor_0_r.
Qed.
(** A null [ldiff] implies being smaller *)
Lemma ldiff_le : forall a b, ldiff a b == 0 -> a <= b.
Proof.
cut (forall n a b, a < 2^n -> ldiff a b == 0 -> a <= b).
intros H a b. apply (H a), pow_gt_lin_r; order'.
induct n.
intros a b Ha _. rewrite pow_0_r, one_succ, lt_succ_r in Ha.
assert (Ha' : a == 0) by (generalize (le_0_l a); order').
rewrite Ha'. apply le_0_l.
intros n IH a b Ha H.
assert (NEQ : 2 ~= 0) by order'.
rewrite (div_mod a 2 NEQ), (div_mod b 2 NEQ).
apply add_le_mono.
apply mul_le_mono_l.
apply IH.
apply div_lt_upper_bound; trivial. now rewrite <- pow_succ_r'.
rewrite <- (pow_1_r 2), <- 2 shiftr_div_pow2.
now rewrite <- shiftr_ldiff, H, shiftr_div_pow2, pow_1_r, div_0_l.
rewrite <- 2 bit0_mod.
apply bits_inj_iff in H. specialize (H 0).
rewrite ldiff_spec, bits_0 in H.
destruct a.[0], b.[0]; try discriminate; simpl; order'.
Qed.
(** Subtraction can be a ldiff when the opposite ldiff is null. *)
Lemma sub_nocarry_ldiff : forall a b, ldiff b a == 0 ->
a-b == ldiff a b.
Proof.
intros a b H.
apply add_cancel_r with b.
rewrite sub_add.
symmetry.
rewrite add_nocarry_lxor.
bitwise.
apply bits_inj_iff in H. specialize (H m).
rewrite ldiff_spec, bits_0 in H.
now destruct a.[m], b.[m].
apply land_ldiff.
now apply ldiff_le.
Qed.
(** We can express lnot in term of subtraction *)
Lemma add_lnot_diag_low : forall a n, log2 a < n ->
a + lnot a n == ones n.
Proof.
intros a n H.
assert (H' := land_lnot_diag_low a n H).
rewrite add_nocarry_lxor, lxor_lor by trivial.
now apply lor_lnot_diag_low.
Qed.
Lemma lnot_sub_low : forall a n, log2 a < n ->
lnot a n == ones n - a.
Proof.
intros a n H.
now rewrite <- (add_lnot_diag_low a n H), add_comm, add_sub.
Qed.
(** Adding numbers with no common bits cannot lead to a much bigger number *)
Lemma add_nocarry_lt_pow2 : forall a b n, land a b == 0 ->
a < 2^n -> b < 2^n -> a+b < 2^n.
Proof.
intros a b n H Ha Hb.
rewrite add_nocarry_lxor by trivial.
apply div_small_iff. order_nz.
rewrite <- shiftr_div_pow2, shiftr_lxor, !shiftr_div_pow2.
rewrite 2 div_small by trivial.
apply lxor_0_l.
Qed.
Lemma add_nocarry_mod_lt_pow2 : forall a b n, land a b == 0 ->
a mod 2^n + b mod 2^n < 2^n.
Proof.
intros a b n H.
apply add_nocarry_lt_pow2.
bitwise.
destruct (le_gt_cases n m).
now rewrite mod_pow2_bits_high.
now rewrite !mod_pow2_bits_low, <- land_spec, H, bits_0.
apply mod_upper_bound; order_nz.
apply mod_upper_bound; order_nz.
Qed.
End NBitsProp.
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_custom_add(clock, enable, resetn, dataa, datab, result);
input clock, enable, resetn;
input [31:0] dataa;
input [31:0] datab;
output [31:0] result;
// Total Latency = 12.
acl_fp_custom_add_core core(
.clock(clock),
.resetn(resetn),
.dataa(dataa),
.datab(datab),
.result(result),
.valid_in(),
.valid_out(),
.stall_in(),
.stall_out(),
.enable(enable));
defparam core.HIGH_LATENCY = 1;
defparam core.HIGH_CAPACITY = 0;
defparam core.FLUSH_DENORMS = 0;
defparam core.ROUNDING_MODE = 0;
defparam core.FINITE_MATH_ONLY = 0;
defparam core.REMOVE_STICKY = 0;
endmodule
|
// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
// --
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_mc.v
//
// Description:
// To handle AXI4 transactions to external memory on Virtex-6 architectures
// requires a bridge to convert the AXI4 transactions to the memory
// controller(MC) user interface. The MC user interface has bidirectional
// data path and supports data width of 256/128/64/32 bits.
// The bridge is designed to allow AXI4 IP masters to communicate with
// the MC user interface.
//
//
// Specifications:
// AXI4 Slave Side:
// Configurable data width of 32, 64, 128, 256
// Read acceptance depth is:
// Write acceptance depth is:
//
// Structure:
// axi_mc
// axi_register_slice_d1
// USE_UPSIZER
// upsizer_d2
// axi_register_slice_d3
// WRITE_BUNDLE
// axi_mc_aw_channel_0
// axi_mc_cmd_translator_0
// rd_cmd_fsm_0
// axi_mc_w_channel_0
// axi_mc_b_channel_0
// READ_BUNDLE
// axi_mc_ar_channel_0
// axi_mc_cmd_translator_0
// rd_cmd_fsm_0
// axi_mc_r_channel_0
// USE_CMD_ARBITER
// axi_mc_cmd_arbiter_0
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
module mig_7series_v4_0_axi_mc #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// FPGA Family. Current version: virtex6.
parameter C_FAMILY = "virtex6",
// Width of all master and slave ID signals.
// Range: >= 1.
parameter integer C_S_AXI_ID_WIDTH = 4,
// Width of S_AXI_AWADDR, S_AXI_ARADDR, M_AXI_AWADDR and
// M_AXI_ARADDR for all SI/MI slots.
// Range: 32.
parameter integer C_S_AXI_ADDR_WIDTH = 30,
// Width of WDATA and RDATA on SI slot.
// Must be <= C_MC_DATA_WIDTH
// Range: 32, 64, 128, 256.
parameter integer C_S_AXI_DATA_WIDTH = 32,
// Memory controller address width, range 28-32
parameter integer C_MC_ADDR_WIDTH = 30,
// Width of wr_data and rd_data.
// Range: 32, 64, 128, 256.
parameter integer C_MC_DATA_WIDTH = 32,
// Memory controller burst mode,
// values "8", "4" & "OTF"
parameter C_MC_BURST_MODE = "8",
// Number of memory clocks per fabric clock
// = 2 for DDR2 or low frequency designs
// = 4 for DDR3 or high frequency designs
parameter C_MC_nCK_PER_CLK = 2,
// Indicates whether to instatiate upsizer
// Range: 0, 1
parameter integer C_S_AXI_SUPPORTS_NARROW_BURST = 1,
// C_S_AXI_REG_EN0[00] = Reserved
// C_S_AXI_REG_EN0[04] = AW CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN0[05] = W CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN0[06] = B CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN0[07] = R CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN0[08] = AW CHANNEL UPSIZER REGISTER SLICE
// C_S_AXI_REG_EN0[09] = W CHANNEL UPSIZER REGISTER SLICE
// C_S_AXI_REG_EN0[10] = AR CHANNEL UPSIZER REGISTER SLICE
// C_S_AXI_REG_EN0[11] = R CHANNEL UPSIZER REGISTER SLICE
parameter C_S_AXI_REG_EN0 = 20'h00000,
// Instatiates register slices after the upsizer.
// The type of register is specified for each channel
// in a vector. 4 bits per channel are used.
// C_S_AXI_REG_EN1[03:00] = AW CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN1[07:04] = W CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN1[11:08] = B CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN1[15:12] = AR CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN1[20:16] = R CHANNEL REGISTER SLICE
// Possible values for each channel are:
//
// 0 => BYPASS = The channel is just wired through the
// module.
// 1 => FWD = The master VALID and payload signals
// are registrated.
// 2 => REV = The slave ready signal is registrated
// 3 => FWD_REV = Both FWD and REV
// 4 => SLAVE_FWD = All slave side signals and master
// VALID and payload are registrated.
// 5 => SLAVE_RDY = All slave side signals and master
// READY are registrated.
// 6 => INPUTS = Slave and Master side inputs are
// registrated.
// 7 => ADDRESS = Optimized for address channel
// A A
// RRBWW
parameter C_S_AXI_REG_EN1 = 20'h00000,
parameter C_RD_WR_ARB_ALGORITHM = "RD_PRI_REG",
// Indicates the Arbitration
// Allowed values - "TDM", "ROUND_ROBIN",
// "RD_PRI_REG", "RD_PRI_REG_STARVE_LIMIT"
parameter C_ECC = "OFF"
// Output RMW if ECC is on.
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// AXI Slave Interface
// Slave Interface System Signals
input wire aclk ,
input wire aresetn ,
// Slave Interface Write Address Ports
input wire [C_S_AXI_ID_WIDTH-1:0] s_axi_awid ,
input wire [C_S_AXI_ADDR_WIDTH-1:0] s_axi_awaddr ,
input wire [7:0] s_axi_awlen ,
input wire [2:0] s_axi_awsize ,
input wire [1:0] s_axi_awburst ,
input wire [0:0] s_axi_awlock ,
input wire [3:0] s_axi_awcache ,
input wire [2:0] s_axi_awprot ,
input wire [3:0] s_axi_awqos ,
input wire s_axi_awvalid ,
output wire s_axi_awready ,
// Slave Interface Write Data Ports
input wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_wdata ,
input wire [C_S_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb ,
input wire s_axi_wlast ,
input wire s_axi_wvalid ,
output wire s_axi_wready ,
// Slave Interface Write Response Ports
output wire [C_S_AXI_ID_WIDTH-1:0] s_axi_bid ,
output wire [1:0] s_axi_bresp ,
output wire s_axi_bvalid ,
input wire s_axi_bready ,
// Slave Interface Read Address Ports
input wire [C_S_AXI_ID_WIDTH-1:0] s_axi_arid ,
input wire [C_S_AXI_ADDR_WIDTH-1:0] s_axi_araddr ,
input wire [7:0] s_axi_arlen ,
input wire [2:0] s_axi_arsize ,
input wire [1:0] s_axi_arburst ,
input wire [0:0] s_axi_arlock ,
input wire [3:0] s_axi_arcache ,
input wire [2:0] s_axi_arprot ,
input wire [3:0] s_axi_arqos ,
input wire s_axi_arvalid ,
output wire s_axi_arready ,
// Slave Interface Read Data Ports
output wire [C_S_AXI_ID_WIDTH-1:0] s_axi_rid ,
output wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_rdata ,
output wire [1:0] s_axi_rresp ,
output wire s_axi_rlast ,
output wire s_axi_rvalid ,
input wire s_axi_rready ,
// MC Master Interface
//CMD PORT
output wire mc_app_en ,
output wire [2:0] mc_app_cmd ,
output wire mc_app_sz ,
output wire [C_MC_ADDR_WIDTH-1:0] mc_app_addr ,
output wire mc_app_hi_pri ,
input wire mc_app_rdy ,
input wire mc_init_complete ,
//DATA PORT
output wire mc_app_wdf_wren ,
output wire [C_MC_DATA_WIDTH/8-1:0] mc_app_wdf_mask ,
output wire [C_MC_DATA_WIDTH-1:0] mc_app_wdf_data ,
output wire mc_app_wdf_end ,
input wire mc_app_wdf_rdy ,
input wire mc_app_rd_valid ,
input wire [C_MC_DATA_WIDTH-1:0] mc_app_rd_data ,
input wire mc_app_rd_end ,
input wire [2*C_MC_nCK_PER_CLK-1:0] mc_app_ecc_multiple_err
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam integer P_AXSIZE = (C_MC_DATA_WIDTH == 32) ? 3'd2 :
(C_MC_DATA_WIDTH == 64) ? 3'd3 :
(C_MC_DATA_WIDTH == 128)? 3'd4 :
(C_MC_DATA_WIDTH == 256)? 3'd5 :
(C_MC_DATA_WIDTH == 512)? 3'd6 : 3'd7;
// C_D?_REG_CONFIG_*:
// 0 => BYPASS = The channel is just wired through the module.
// 1 => FWD = The master VALID and payload signals are registrated.
// 2 => REV = The slave ready signal is registrated
// 3 => FWD_REV = Both FWD and REV
// 4 => SLAVE_FWD = All slave side signals and master VALID and payload are registrated.
// 5 => SLAVE_RDY = All slave side signals and master READY are registrated.
// 6 => INPUTS = Slave and Master side inputs are registrated.
localparam integer P_D1_REG_CONFIG_AW = 0;
localparam integer P_D1_REG_CONFIG_W = 0;
localparam integer P_D1_REG_CONFIG_B = 0;
localparam integer P_D1_REG_CONFIG_AR = 0;
localparam integer P_D1_REG_CONFIG_R = 0;
// Upsizer
localparam integer P_USE_UPSIZER = ( C_S_AXI_DATA_WIDTH < C_MC_DATA_WIDTH) ? 1'b1
: C_S_AXI_SUPPORTS_NARROW_BURST;
localparam integer P_D2_REG_CONFIG_AW = P_USE_UPSIZER ? 1 : C_S_AXI_REG_EN0[8];
localparam integer P_D2_REG_CONFIG_W = C_S_AXI_REG_EN0[9];
localparam integer P_D2_REG_CONFIG_AR = P_USE_UPSIZER ? 1 : C_S_AXI_REG_EN0[10];
localparam integer P_D2_REG_CONFIG_R = C_S_AXI_REG_EN0[11];
// localparam integer P_D3_REG_CONFIG_AW = (C_S_AXI_DATA_WIDTH < C_MC_DATA_WIDTH)?
// (C_S_AXI_REG_EN0[4] ? 1 : C_S_AXI_REG_EN1[ 0 +: 4]) : 1;
// localparam integer P_D3_REG_CONFIG_W = C_S_AXI_REG_EN0[5] ? 2 : C_S_AXI_REG_EN1[ 4 +: 4];
// localparam integer P_D3_REG_CONFIG_B = C_S_AXI_REG_EN0[6] ? 7 : C_S_AXI_REG_EN1[ 8 +: 4];
// // AR channel must always have a register slice.
// localparam integer P_D3_REG_CONFIG_AR = (C_S_AXI_DATA_WIDTH < C_MC_DATA_WIDTH)? 0 : 1;
// localparam integer P_D3_REG_CONFIG_R = C_S_AXI_REG_EN0[7] ? 6 : C_S_AXI_REG_EN1[16 +: 4];
localparam integer P_D3_REG_CONFIG_AW = 0;
localparam integer P_D3_REG_CONFIG_W = 0;
localparam integer P_D3_REG_CONFIG_B = 0;
localparam integer P_D3_REG_CONFIG_AR = 0;
localparam integer P_D3_REG_CONFIG_R = 0;
localparam integer P_UPSIZER_PACKING_LEVEL = 2;
localparam integer P_SUPPORTS_USER_SIGNALS = 0;
// Set this parameter to 1 if data can be returned out of order
localparam integer P_SINGLE_THREAD = 0;
// BURST LENGTH
// In 4:1 mode the only burst mode that is supported is BL8.
// The BL8 in 4:1 mode will be treated as BL4 by the shim.
// In 2:1 mode both the burst modes BL4 & BL8 are supported.
localparam integer C_MC_BURST_LEN = (C_MC_nCK_PER_CLK == 4) ? 1:
(C_MC_BURST_MODE == "4") ? 1 : 2;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
// AXI Slave signals from Reg Slice, Upsizer, at MC data width, internal signals
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
///////////////////////////////////////////////////////////////////////////////
// First reg slice slave side output/inputs
wire [C_S_AXI_ID_WIDTH-1:0] awid_d1 ;
wire [C_S_AXI_ADDR_WIDTH-1:0] awaddr_d1 ;
wire [7:0] awlen_d1 ;
wire [2:0] awsize_d1 ;
wire [1:0] awburst_d1 ;
wire [1:0] awlock_d1 ;
wire [3:0] awcache_d1 ;
wire [2:0] awprot_d1 ;
wire [3:0] awqos_d1 ;
wire awvalid_d1 ;
wire awready_d1 ;
wire [C_S_AXI_DATA_WIDTH-1:0] wdata_d1 ;
wire [C_S_AXI_DATA_WIDTH/8-1:0] wstrb_d1 ;
wire wlast_d1 ;
wire wvalid_d1 ;
wire wready_d1 ;
wire [C_S_AXI_ID_WIDTH-1:0] bid_d1 ;
wire [1:0] bresp_d1 ;
wire bvalid_d1 ;
wire bready_d1 ;
wire [C_S_AXI_ID_WIDTH-1:0] arid_d1 ;
wire [C_S_AXI_ADDR_WIDTH-1:0] araddr_d1 ;
wire [7:0] arlen_d1 ;
wire [2:0] arsize_d1 ;
wire [1:0] arburst_d1 ;
wire [1:0] arlock_d1 ;
wire [3:0] arcache_d1 ;
wire [2:0] arprot_d1 ;
wire [3:0] arqos_d1 ;
wire arvalid_d1 ;
wire arready_d1 ;
wire [C_S_AXI_ID_WIDTH-1:0] rid_d1 ;
wire [C_S_AXI_DATA_WIDTH-1:0] rdata_d1 ;
wire [1:0] rresp_d1 ;
wire rlast_d1 ;
wire rvalid_d1 ;
wire rready_d1 ;
// Upsizer slave side outputs/inputs
wire [C_S_AXI_ID_WIDTH-1:0] awid_d2 ;
wire [C_S_AXI_ADDR_WIDTH-1:0] awaddr_d2 ;
wire [7:0] awlen_d2 ;
wire [2:0] awsize_d2 ;
wire [1:0] awburst_d2 ;
wire [1:0] awlock_d2 ;
wire [3:0] awcache_d2 ;
wire [2:0] awprot_d2 ;
wire [3:0] awqos_d2 ;
wire awvalid_d2 ;
wire awready_d2 ;
wire [C_MC_DATA_WIDTH-1:0] wdata_d2 ;
wire [C_MC_DATA_WIDTH/8-1:0] wstrb_d2 ;
wire wlast_d2 ;
wire wvalid_d2 ;
wire wready_d2 ;
wire [C_S_AXI_ID_WIDTH-1:0] bid_d2 ;
wire [1:0] bresp_d2 ;
wire bvalid_d2 ;
wire bready_d2 ;
wire [C_S_AXI_ID_WIDTH-1:0] arid_d2 ;
wire [C_S_AXI_ADDR_WIDTH-1:0] araddr_d2 ;
wire [7:0] arlen_d2 ;
wire [2:0] arsize_d2 ;
wire [1:0] arburst_d2 ;
wire [1:0] arlock_d2 ;
wire [3:0] arcache_d2 ;
wire [2:0] arprot_d2 ;
wire [3:0] arqos_d2 ;
wire arvalid_d2 ;
wire arready_d2 ;
wire [C_S_AXI_ID_WIDTH-1:0] rid_d2 ;
wire [C_MC_DATA_WIDTH-1:0] rdata_d2 ;
wire [1:0] rresp_d2 ;
wire rlast_d2 ;
wire rvalid_d2 ;
wire rready_d2 ;
// Registe Slice 2 slave side outputs/inputs
wire [C_S_AXI_ID_WIDTH-1:0] awid_d3 ;
wire [C_S_AXI_ADDR_WIDTH-1:0] awaddr_d3 ;
wire [7:0] awlen_d3 ;
// AxSIZE hardcoded with static value
// wire [2:0] awsize_d3 ;
wire [1:0] awburst_d3 ;
wire [1:0] awlock_d3 ;
wire [3:0] awcache_d3 ;
wire [2:0] awprot_d3 ;
wire [3:0] awqos_d3 ;
wire awvalid_d3 ;
wire awready_d3 ;
wire [C_MC_DATA_WIDTH-1:0] wdata_d3 ;
wire [C_MC_DATA_WIDTH/8-1:0] wstrb_d3 ;
wire wlast_d3 ;
wire wvalid_d3 ;
wire wready_d3 ;
wire [C_S_AXI_ID_WIDTH-1:0] bid_d3 ;
wire [1:0] bresp_d3 ;
wire bvalid_d3 ;
wire bready_d3 ;
wire [C_S_AXI_ID_WIDTH-1:0] arid_d3 ;
wire [C_S_AXI_ADDR_WIDTH-1:0] araddr_d3 ;
wire [7:0] arlen_d3 ;
// AxSIZE hardcoded with static value
// wire [2:0] arsize_d3 ;
wire [1:0] arburst_d3 ;
wire [1:0] arlock_d3 ;
wire [3:0] arcache_d3 ;
wire [2:0] arprot_d3 ;
wire [3:0] arqos_d3 ;
wire arvalid_d3 ;
wire arready_d3 ;
wire [C_S_AXI_ID_WIDTH-1:0] rid_d3 ;
wire [C_MC_DATA_WIDTH-1:0] rdata_d3 ;
wire [1:0] rresp_d3 ;
wire rlast_d3 ;
wire rvalid_d3 ;
wire rready_d3 ;
// AW/AR module outputs to arbiter.
wire wr_cmd_en ;
wire wr_cmd_en_last ;
wire [2:0] wr_cmd_instr ;
wire [C_MC_ADDR_WIDTH-1:0] wr_cmd_byte_addr ;
wire wr_cmd_full ;
wire rd_cmd_en ;
wire rd_cmd_en_last ;
wire [2:0] rd_cmd_instr ;
wire [C_MC_ADDR_WIDTH-1:0] rd_cmd_byte_addr ;
wire rd_cmd_full ;
wire aresetn_int ;
wire cmd_wr_bytes;
reg areset_d1;
reg mc_init_complete_r;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
///////////////////////////////////////////////////////////////////////////////
assign aresetn_int = aresetn & mc_init_complete_r;
always @(posedge aclk)
areset_d1 <= ~aresetn_int;
always @(posedge aclk)
mc_init_complete_r <= mc_init_complete ;
mig_7series_v4_0_ddr_axi_register_slice #
(
.C_FAMILY ( C_FAMILY ) ,
.C_AXI_ID_WIDTH ( C_S_AXI_ID_WIDTH ) ,
.C_AXI_ADDR_WIDTH ( C_S_AXI_ADDR_WIDTH ) ,
.C_AXI_DATA_WIDTH ( C_S_AXI_DATA_WIDTH ) ,
.C_AXI_SUPPORTS_USER_SIGNALS ( P_SUPPORTS_USER_SIGNALS ) ,
.C_AXI_AWUSER_WIDTH ( 1 ) ,
.C_AXI_ARUSER_WIDTH ( 1 ) ,
.C_AXI_WUSER_WIDTH ( 1 ) ,
.C_AXI_RUSER_WIDTH ( 1 ) ,
.C_AXI_BUSER_WIDTH ( 1 ) ,
.C_REG_CONFIG_AW ( P_D1_REG_CONFIG_AW ) ,
.C_REG_CONFIG_W ( P_D1_REG_CONFIG_W ) ,
.C_REG_CONFIG_B ( P_D1_REG_CONFIG_B ) ,
.C_REG_CONFIG_AR ( P_D1_REG_CONFIG_AR ) ,
.C_REG_CONFIG_R ( P_D1_REG_CONFIG_R )
)
axi_register_slice_d1
(
.ACLK ( aclk ) ,
.ARESETN ( aresetn_int ) ,
.S_AXI_AWID ( s_axi_awid ) ,
.S_AXI_AWADDR ( s_axi_awaddr ) ,
.S_AXI_AWLEN ( s_axi_awlen ) ,
.S_AXI_AWSIZE ( s_axi_awsize ) ,
.S_AXI_AWBURST ( s_axi_awburst ) ,
.S_AXI_AWLOCK ( {1'b0, s_axi_awlock}) ,
.S_AXI_AWCACHE ( s_axi_awcache ) ,
.S_AXI_AWPROT ( s_axi_awprot ) ,
.S_AXI_AWREGION( 4'b0 ) ,
.S_AXI_AWQOS ( s_axi_awqos ) ,
.S_AXI_AWUSER ( 1'b0 ) ,
.S_AXI_AWVALID ( s_axi_awvalid ) ,
.S_AXI_AWREADY ( s_axi_awready ) ,
.S_AXI_WDATA ( s_axi_wdata ) ,
.S_AXI_WID ( {C_S_AXI_ID_WIDTH{1'b0}} ) ,
.S_AXI_WSTRB ( s_axi_wstrb ) ,
.S_AXI_WLAST ( s_axi_wlast ) ,
.S_AXI_WUSER ( 1'b0 ) ,
.S_AXI_WVALID ( s_axi_wvalid ) ,
.S_AXI_WREADY ( s_axi_wready ) ,
.S_AXI_BID ( s_axi_bid ) ,
.S_AXI_BRESP ( s_axi_bresp ) ,
.S_AXI_BUSER ( ) ,
.S_AXI_BVALID ( s_axi_bvalid ) ,
.S_AXI_BREADY ( s_axi_bready ) ,
.S_AXI_ARID ( s_axi_arid ) ,
.S_AXI_ARADDR ( s_axi_araddr ) ,
.S_AXI_ARLEN ( s_axi_arlen ) ,
.S_AXI_ARSIZE ( s_axi_arsize ) ,
.S_AXI_ARBURST ( s_axi_arburst ) ,
.S_AXI_ARLOCK ( {1'b0, s_axi_arlock}) ,
.S_AXI_ARCACHE ( s_axi_arcache ) ,
.S_AXI_ARPROT ( s_axi_arprot ) ,
.S_AXI_ARREGION( 4'b0 ) ,
.S_AXI_ARQOS ( s_axi_arqos ) ,
.S_AXI_ARUSER ( 1'b0 ) ,
.S_AXI_ARVALID ( s_axi_arvalid ) ,
.S_AXI_ARREADY ( s_axi_arready ) ,
.S_AXI_RID ( s_axi_rid ) ,
.S_AXI_RDATA ( s_axi_rdata ) ,
.S_AXI_RRESP ( s_axi_rresp ) ,
.S_AXI_RLAST ( s_axi_rlast ) ,
.S_AXI_RUSER ( ) ,
.S_AXI_RVALID ( s_axi_rvalid ) ,
.S_AXI_RREADY ( s_axi_rready ) ,
.M_AXI_AWID ( awid_d1 ) ,
.M_AXI_AWADDR ( awaddr_d1 ) ,
.M_AXI_AWLEN ( awlen_d1 ) ,
.M_AXI_AWSIZE ( awsize_d1 ) ,
.M_AXI_AWBURST ( awburst_d1 ) ,
.M_AXI_AWLOCK ( awlock_d1 ) ,
.M_AXI_AWCACHE ( awcache_d1 ) ,
.M_AXI_AWREGION( ) ,
.M_AXI_AWPROT ( awprot_d1 ) ,
.M_AXI_AWQOS ( awqos_d1 ) ,
.M_AXI_AWUSER ( ) ,
.M_AXI_AWVALID ( awvalid_d1 ) ,
.M_AXI_AWREADY ( awready_d1 ) ,
.M_AXI_WID ( ) ,
.M_AXI_WDATA ( wdata_d1 ) ,
.M_AXI_WSTRB ( wstrb_d1 ) ,
.M_AXI_WLAST ( wlast_d1 ) ,
.M_AXI_WUSER ( ) ,
.M_AXI_WVALID ( wvalid_d1 ) ,
.M_AXI_WREADY ( wready_d1 ) ,
.M_AXI_BID ( bid_d1 ) ,
.M_AXI_BRESP ( bresp_d1 ) ,
.M_AXI_BUSER ( 1'b0 ) ,
.M_AXI_BVALID ( bvalid_d1 ) ,
.M_AXI_BREADY ( bready_d1 ) ,
.M_AXI_ARID ( arid_d1 ) ,
.M_AXI_ARADDR ( araddr_d1 ) ,
.M_AXI_ARLEN ( arlen_d1 ) ,
.M_AXI_ARSIZE ( arsize_d1 ) ,
.M_AXI_ARBURST ( arburst_d1 ) ,
.M_AXI_ARLOCK ( arlock_d1 ) ,
.M_AXI_ARCACHE ( arcache_d1 ) ,
.M_AXI_ARPROT ( arprot_d1 ) ,
.M_AXI_ARREGION( ) ,
.M_AXI_ARQOS ( arqos_d1 ) ,
.M_AXI_ARUSER ( ) ,
.M_AXI_ARVALID ( arvalid_d1 ) ,
.M_AXI_ARREADY ( arready_d1 ) ,
.M_AXI_RID ( rid_d1 ) ,
.M_AXI_RDATA ( rdata_d1 ) ,
.M_AXI_RRESP ( rresp_d1 ) ,
.M_AXI_RLAST ( rlast_d1 ) ,
.M_AXI_RUSER ( 1'b0 ) ,
.M_AXI_RVALID ( rvalid_d1 ) ,
.M_AXI_RREADY ( rready_d1 )
);
generate
if (P_USE_UPSIZER) begin : USE_UPSIZER
mig_7series_v4_0_ddr_axi_upsizer #
(
.C_FAMILY ( C_FAMILY ) ,
.C_AXI_ID_WIDTH ( C_S_AXI_ID_WIDTH ) ,
.C_AXI_ADDR_WIDTH ( C_S_AXI_ADDR_WIDTH ) ,
.C_S_AXI_DATA_WIDTH ( C_S_AXI_DATA_WIDTH ) ,
.C_M_AXI_DATA_WIDTH ( C_MC_DATA_WIDTH ) ,
.C_M_AXI_AW_REGISTER ( P_D2_REG_CONFIG_AW ) ,
.C_M_AXI_W_REGISTER ( P_D2_REG_CONFIG_W ) ,
.C_M_AXI_AR_REGISTER ( P_D2_REG_CONFIG_AR ) ,
.C_S_AXI_R_REGISTER ( P_D2_REG_CONFIG_R ) ,
.C_AXI_SUPPORTS_USER_SIGNALS ( P_SUPPORTS_USER_SIGNALS ) ,
.C_AXI_AWUSER_WIDTH ( 1 ) ,
.C_AXI_ARUSER_WIDTH ( 1 ) ,
.C_AXI_WUSER_WIDTH ( 1 ) ,
.C_AXI_RUSER_WIDTH ( 1 ) ,
.C_AXI_BUSER_WIDTH ( 1 ) ,
.C_AXI_SUPPORTS_WRITE ( 1 ) ,
.C_AXI_SUPPORTS_READ ( 1 ) ,
.C_PACKING_LEVEL ( P_UPSIZER_PACKING_LEVEL ) ,
.C_SUPPORT_BURSTS ( 1 ) ,
.C_SINGLE_THREAD ( P_SINGLE_THREAD )
)
upsizer_d2
(
.ACLK ( aclk ) ,
.ARESETN ( aresetn_int ) ,
.S_AXI_AWID ( awid_d1 ) ,
.S_AXI_AWADDR ( awaddr_d1 ) ,
.S_AXI_AWLEN ( awlen_d1 ) ,
.S_AXI_AWSIZE ( awsize_d1 ) ,
.S_AXI_AWBURST ( awburst_d1 ) ,
.S_AXI_AWLOCK ( awlock_d1 ) ,
.S_AXI_AWCACHE ( awcache_d1 ) ,
.S_AXI_AWPROT ( awprot_d1 ) ,
.S_AXI_AWREGION( 4'b0 ) ,
.S_AXI_AWQOS ( awqos_d1 ) ,
.S_AXI_AWUSER ( 1'b0 ) ,
.S_AXI_AWVALID ( awvalid_d1 ) ,
.S_AXI_AWREADY ( awready_d1 ) ,
.S_AXI_WDATA ( wdata_d1 ) ,
.S_AXI_WSTRB ( wstrb_d1 ) ,
.S_AXI_WLAST ( wlast_d1 ) ,
.S_AXI_WUSER ( 1'b0 ) ,
.S_AXI_WVALID ( wvalid_d1 ) ,
.S_AXI_WREADY ( wready_d1 ) ,
.S_AXI_BID ( bid_d1 ) ,
.S_AXI_BRESP ( bresp_d1 ) ,
.S_AXI_BUSER ( ) ,
.S_AXI_BVALID ( bvalid_d1 ) ,
.S_AXI_BREADY ( bready_d1 ) ,
.S_AXI_ARID ( arid_d1 ) ,
.S_AXI_ARADDR ( araddr_d1 ) ,
.S_AXI_ARLEN ( arlen_d1 ) ,
.S_AXI_ARSIZE ( arsize_d1 ) ,
.S_AXI_ARBURST ( arburst_d1 ) ,
.S_AXI_ARLOCK ( arlock_d1 ) ,
.S_AXI_ARCACHE ( arcache_d1 ) ,
.S_AXI_ARPROT ( arprot_d1 ) ,
.S_AXI_ARREGION( 4'b0 ) ,
.S_AXI_ARQOS ( arqos_d1 ) ,
.S_AXI_ARUSER ( 1'b0 ) ,
.S_AXI_ARVALID ( arvalid_d1 ) ,
.S_AXI_ARREADY ( arready_d1 ) ,
.S_AXI_RID ( rid_d1 ) ,
.S_AXI_RDATA ( rdata_d1 ) ,
.S_AXI_RRESP ( rresp_d1 ) ,
.S_AXI_RLAST ( rlast_d1 ) ,
.S_AXI_RUSER ( ) ,
.S_AXI_RVALID ( rvalid_d1 ) ,
.S_AXI_RREADY ( rready_d1 ) ,
.M_AXI_AWID ( awid_d2 ) ,
.M_AXI_AWADDR ( awaddr_d2 ) ,
.M_AXI_AWLEN ( awlen_d2 ) ,
.M_AXI_AWSIZE ( awsize_d2 ) ,
.M_AXI_AWBURST ( awburst_d2 ) ,
.M_AXI_AWLOCK ( awlock_d2 ) ,
.M_AXI_AWCACHE ( awcache_d2 ) ,
.M_AXI_AWPROT ( awprot_d2 ) ,
.M_AXI_AWREGION( ) ,
.M_AXI_AWQOS ( awqos_d2 ) ,
.M_AXI_AWUSER ( ) ,
.M_AXI_AWVALID ( awvalid_d2 ) ,
.M_AXI_AWREADY ( awready_d2 ) ,
.M_AXI_WDATA ( wdata_d2 ) ,
.M_AXI_WSTRB ( wstrb_d2 ) ,
.M_AXI_WLAST ( wlast_d2 ) ,
.M_AXI_WUSER ( ) ,
.M_AXI_WVALID ( wvalid_d2 ) ,
.M_AXI_WREADY ( wready_d2 ) ,
.M_AXI_BID ( bid_d2 ) ,
.M_AXI_BRESP ( bresp_d2 ) ,
.M_AXI_BUSER ( 1'b0 ) ,
.M_AXI_BVALID ( bvalid_d2 ) ,
.M_AXI_BREADY ( bready_d2 ) ,
.M_AXI_ARID ( arid_d2 ) ,
.M_AXI_ARADDR ( araddr_d2 ) ,
.M_AXI_ARLEN ( arlen_d2 ) ,
.M_AXI_ARSIZE ( arsize_d2 ) ,
.M_AXI_ARBURST ( arburst_d2 ) ,
.M_AXI_ARLOCK ( arlock_d2 ) ,
.M_AXI_ARCACHE ( arcache_d2 ) ,
.M_AXI_ARPROT ( arprot_d2 ) ,
.M_AXI_ARREGION( ) ,
.M_AXI_ARQOS ( arqos_d2 ) ,
.M_AXI_ARUSER ( ) ,
.M_AXI_ARVALID ( arvalid_d2 ) ,
.M_AXI_ARREADY ( arready_d2 ) ,
.M_AXI_RID ( rid_d2 ) ,
.M_AXI_RDATA ( rdata_d2 ) ,
.M_AXI_RRESP ( rresp_d2 ) ,
.M_AXI_RLAST ( rlast_d2 ) ,
.M_AXI_RUSER ( 1'b0 ) ,
.M_AXI_RVALID ( rvalid_d2 ) ,
.M_AXI_RREADY ( rready_d2 )
);
end
else begin : NO_UPSIZER
assign awid_d2 = awid_d1 ;
assign awaddr_d2 = awaddr_d1 ;
assign awlen_d2 = awlen_d1 ;
assign awsize_d2 = awsize_d1 ;
assign awburst_d2 = awburst_d1 ;
assign awlock_d2 = awlock_d1 ;
assign awcache_d2 = awcache_d1 ;
assign awprot_d2 = awprot_d1 ;
assign awqos_d2 = awqos_d1 ;
assign awvalid_d2 = awvalid_d1 ;
assign awready_d1 = awready_d2 ;
assign wdata_d2 = wdata_d1 ;
assign wstrb_d2 = wstrb_d1 ;
assign wlast_d2 = wlast_d1 ;
assign wvalid_d2 = wvalid_d1 ;
assign wready_d1 = wready_d2 ;
assign bid_d1 = bid_d2 ;
assign bresp_d1 = bresp_d2 ;
assign bvalid_d1 = bvalid_d2 ;
assign bready_d2 = bready_d1 ;
assign arid_d2 = arid_d1 ;
assign araddr_d2 = araddr_d1 ;
assign arlen_d2 = arlen_d1 ;
assign arsize_d2 = arsize_d1 ;
assign arburst_d2 = arburst_d1 ;
assign arlock_d2 = arlock_d1 ;
assign arcache_d2 = arcache_d1 ;
assign arprot_d2 = arprot_d1 ;
assign arqos_d2 = arqos_d1 ;
assign arvalid_d2 = arvalid_d1 ;
assign arready_d1 = arready_d2 ;
assign rid_d1 = rid_d2 ;
assign rdata_d1 = rdata_d2 ;
assign rresp_d1 = rresp_d2 ;
assign rlast_d1 = rlast_d2 ;
assign rvalid_d1 = rvalid_d2 ;
assign rready_d2 = rready_d1 ;
end
endgenerate
mig_7series_v4_0_ddr_axi_register_slice #
(
.C_FAMILY ( C_FAMILY ) ,
.C_AXI_ID_WIDTH ( C_S_AXI_ID_WIDTH ) ,
.C_AXI_ADDR_WIDTH ( C_S_AXI_ADDR_WIDTH ) ,
.C_AXI_DATA_WIDTH ( C_MC_DATA_WIDTH ) ,
.C_AXI_SUPPORTS_USER_SIGNALS ( P_SUPPORTS_USER_SIGNALS ) ,
.C_AXI_AWUSER_WIDTH ( 1 ) ,
.C_AXI_ARUSER_WIDTH ( 1 ) ,
.C_AXI_WUSER_WIDTH ( 1 ) ,
.C_AXI_RUSER_WIDTH ( 1 ) ,
.C_AXI_BUSER_WIDTH ( 1 ) ,
.C_REG_CONFIG_AW ( P_D3_REG_CONFIG_AW ) ,
.C_REG_CONFIG_W ( P_D3_REG_CONFIG_W ) ,
.C_REG_CONFIG_B ( P_D3_REG_CONFIG_B ) ,
.C_REG_CONFIG_AR ( P_D3_REG_CONFIG_AR ) ,
.C_REG_CONFIG_R ( P_D3_REG_CONFIG_R )
)
axi_register_slice_d3
(
.ACLK ( aclk ) ,
.ARESETN ( aresetn_int ) ,
.S_AXI_AWID ( awid_d2 ) ,
.S_AXI_AWADDR ( awaddr_d2 ) ,
.S_AXI_AWLEN ( awlen_d2 ) ,
.S_AXI_AWSIZE ( P_AXSIZE[2:0] ) ,
.S_AXI_AWBURST ( awburst_d2 ) ,
.S_AXI_AWLOCK ( awlock_d2 ) ,
.S_AXI_AWCACHE ( awcache_d2 ) ,
.S_AXI_AWPROT ( awprot_d2 ) ,
.S_AXI_AWREGION( 4'b0 ) ,
.S_AXI_AWQOS ( awqos_d2 ) ,
.S_AXI_AWUSER ( 1'b0 ) ,
.S_AXI_AWVALID ( awvalid_d2 ) ,
.S_AXI_AWREADY ( awready_d2 ) ,
.S_AXI_WID ( {C_S_AXI_ID_WIDTH{1'b0}} ) ,
.S_AXI_WDATA ( wdata_d2 ) ,
.S_AXI_WSTRB ( wstrb_d2 ) ,
.S_AXI_WLAST ( wlast_d2 ) ,
.S_AXI_WUSER ( 1'b0 ) ,
.S_AXI_WVALID ( wvalid_d2 ) ,
.S_AXI_WREADY ( wready_d2 ) ,
.S_AXI_BID ( bid_d2 ) ,
.S_AXI_BRESP ( bresp_d2 ) ,
.S_AXI_BUSER ( ) ,
.S_AXI_BVALID ( bvalid_d2 ) ,
.S_AXI_BREADY ( bready_d2 ) ,
.S_AXI_ARID ( arid_d2 ) ,
.S_AXI_ARADDR ( araddr_d2 ) ,
.S_AXI_ARLEN ( arlen_d2 ) ,
.S_AXI_ARSIZE ( P_AXSIZE[2:0] ) ,
.S_AXI_ARBURST ( arburst_d2 ) ,
.S_AXI_ARLOCK ( arlock_d2 ) ,
.S_AXI_ARCACHE ( arcache_d2 ) ,
.S_AXI_ARPROT ( arprot_d2 ) ,
.S_AXI_ARREGION( 4'b0 ) ,
.S_AXI_ARQOS ( arqos_d2 ) ,
.S_AXI_ARUSER ( 1'b0 ) ,
.S_AXI_ARVALID ( arvalid_d2 ) ,
.S_AXI_ARREADY ( arready_d2 ) ,
.S_AXI_RID ( rid_d2 ) ,
.S_AXI_RDATA ( rdata_d2 ) ,
.S_AXI_RRESP ( rresp_d2 ) ,
.S_AXI_RLAST ( rlast_d2 ) ,
.S_AXI_RUSER ( ) ,
.S_AXI_RVALID ( rvalid_d2 ) ,
.S_AXI_RREADY ( rready_d2 ) ,
.M_AXI_AWID ( awid_d3 ) ,
.M_AXI_AWADDR ( awaddr_d3 ) ,
.M_AXI_AWLEN ( awlen_d3 ) ,
// AxSIZE hardcoded with static value
// .M_AXI_AWSIZE ( awsize_d3 ) ,
.M_AXI_AWSIZE ( ) ,
.M_AXI_AWBURST ( awburst_d3 ) ,
.M_AXI_AWLOCK ( awlock_d3 ) ,
.M_AXI_AWCACHE ( awcache_d3 ) ,
.M_AXI_AWPROT ( awprot_d3 ) ,
.M_AXI_AWREGION( ) ,
.M_AXI_AWQOS ( awqos_d3 ) ,
.M_AXI_AWUSER ( ) ,
.M_AXI_AWVALID ( awvalid_d3 ) ,
.M_AXI_AWREADY ( awready_d3 ) ,
.M_AXI_WID ( ) ,
.M_AXI_WDATA ( wdata_d3 ) ,
.M_AXI_WSTRB ( wstrb_d3 ) ,
.M_AXI_WLAST ( wlast_d3 ) ,
.M_AXI_WUSER ( ) ,
.M_AXI_WVALID ( wvalid_d3 ) ,
.M_AXI_WREADY ( wready_d3 ) ,
.M_AXI_BID ( bid_d3 ) ,
.M_AXI_BRESP ( bresp_d3 ) ,
.M_AXI_BUSER ( 1'b0 ) ,
.M_AXI_BVALID ( bvalid_d3 ) ,
.M_AXI_BREADY ( bready_d3 ) ,
.M_AXI_ARID ( arid_d3 ) ,
.M_AXI_ARADDR ( araddr_d3 ) ,
.M_AXI_ARLEN ( arlen_d3 ) ,
// AxSIZE hardcoded with static value
// .M_AXI_ARSIZE ( arsize_d3 ) ,
.M_AXI_ARSIZE ( ) ,
.M_AXI_ARBURST ( arburst_d3 ) ,
.M_AXI_ARLOCK ( arlock_d3 ) ,
.M_AXI_ARCACHE ( arcache_d3 ) ,
.M_AXI_ARPROT ( arprot_d3 ) ,
.M_AXI_ARREGION( ) ,
.M_AXI_ARQOS ( arqos_d3 ) ,
.M_AXI_ARUSER ( ) ,
.M_AXI_ARVALID ( arvalid_d3 ) ,
.M_AXI_ARREADY ( arready_d3 ) ,
.M_AXI_RID ( rid_d3 ) ,
.M_AXI_RDATA ( rdata_d3 ) ,
.M_AXI_RRESP ( rresp_d3 ) ,
.M_AXI_RLAST ( rlast_d3 ) ,
.M_AXI_RUSER ( 1'b0 ) ,
.M_AXI_RVALID ( rvalid_d3 ) ,
.M_AXI_RREADY ( rready_d3 )
);
// AW/W/B channel internal communication
wire w_ignore_begin;
wire w_ignore_end;
wire w_cmd_rdy;
wire awvalid_int;
wire [3:0] awqos_int ;
wire w_data_rdy ;
wire b_push;
wire [C_S_AXI_ID_WIDTH-1:0] b_awid;
wire b_full;
mig_7series_v4_0_axi_mc_aw_channel #
(
.C_ID_WIDTH ( C_S_AXI_ID_WIDTH ),
.C_AXI_ADDR_WIDTH ( C_S_AXI_ADDR_WIDTH ),
.C_MC_ADDR_WIDTH ( C_MC_ADDR_WIDTH ),
.C_DATA_WIDTH ( C_MC_DATA_WIDTH ),
.C_AXSIZE ( P_AXSIZE ),
.C_MC_nCK_PER_CLK ( C_MC_nCK_PER_CLK ),
.C_MC_BURST_LEN ( C_MC_BURST_LEN ),
.C_ECC ( C_ECC )
)
axi_mc_aw_channel_0
(
.clk ( aclk ) ,
.reset ( areset_d1 ) ,
.awid ( awid_d3 ) ,
.awaddr ( awaddr_d3 ) ,
.awlen ( awlen_d3 ) ,
.awsize ( P_AXSIZE[2:0] ) ,
.awburst ( awburst_d3 ) ,
.awlock ( awlock_d3 ) ,
.awcache ( awcache_d3 ) ,
.awprot ( awprot_d3 ) ,
.awqos ( awqos_d3 ) ,
.awvalid ( awvalid_d3 ) ,
.awready ( awready_d3 ) ,
.cmd_en ( wr_cmd_en ) ,
.cmd_instr ( wr_cmd_instr ) ,
.cmd_byte_addr ( wr_cmd_byte_addr ) ,
.cmd_full ( wr_cmd_full ) ,
.cmd_en_last ( wr_cmd_en_last ) ,
.w_ignore_begin ( w_ignore_begin ) ,
.w_ignore_end ( w_ignore_end ) ,
.w_cmd_rdy ( w_cmd_rdy ) ,
.awvalid_int ( awvalid_int ) ,
.awqos_int ( awqos_int ) ,
.w_data_rdy ( w_data_rdy ) ,
.cmd_wr_bytes ( cmd_wr_bytes ) ,
.b_push ( b_push ) ,
.b_awid ( b_awid ) ,
.b_full ( b_full )
);
mig_7series_v4_0_axi_mc_w_channel #
(
.C_DATA_WIDTH ( C_MC_DATA_WIDTH ),
.C_AXI_ADDR_WIDTH ( C_S_AXI_ADDR_WIDTH ),
.C_MC_BURST_LEN ( C_MC_BURST_LEN ),
.C_ECC ( C_ECC )
)
axi_mc_w_channel_0
(
.clk ( aclk ) ,
.reset ( areset_d1 ) ,
.wdata ( wdata_d3 ) ,
.wstrb ( wstrb_d3 ) ,
.wvalid ( wvalid_d3 ) ,
.wready ( wready_d3 ) ,
.awvalid ( awvalid_int ) ,
.w_ignore_begin ( w_ignore_begin ) ,
.w_ignore_end ( w_ignore_end ) ,
.w_cmd_rdy ( w_cmd_rdy ) ,
.cmd_wr_bytes ( cmd_wr_bytes ) ,
.mc_app_wdf_wren ( mc_app_wdf_wren ) ,
.mc_app_wdf_mask ( mc_app_wdf_mask ) ,
.mc_app_wdf_data ( mc_app_wdf_data ) ,
.mc_app_wdf_last ( mc_app_wdf_end ) ,
.mc_app_wdf_rdy ( mc_app_wdf_rdy ) ,
.w_data_rdy ( w_data_rdy )
);
mig_7series_v4_0_axi_mc_b_channel #
(
.C_ID_WIDTH ( C_S_AXI_ID_WIDTH )
)
axi_mc_b_channel_0
(
.clk ( aclk ) ,
.reset ( areset_d1 ) ,
.bid ( bid_d3 ) ,
.bresp ( bresp_d3 ) ,
.bvalid ( bvalid_d3 ) ,
.bready ( bready_d3 ) ,
.b_push ( b_push ) ,
.b_awid ( b_awid ) ,
.b_full ( b_full ) ,
.b_resp_rdy ( awready_d3 )
);
// AR/R channel communication
wire r_push ;
wire [C_S_AXI_ID_WIDTH-1:0] r_arid ;
wire r_rlast ;
wire r_data_rdy ;
wire r_ignore_begin;
wire r_ignore_end ;
wire arvalid_int ;
wire [3:0] arqos_int ;
mig_7series_v4_0_axi_mc_ar_channel #
(
.C_ID_WIDTH ( C_S_AXI_ID_WIDTH ),
.C_AXI_ADDR_WIDTH ( C_S_AXI_ADDR_WIDTH ),
.C_MC_ADDR_WIDTH ( C_MC_ADDR_WIDTH ),
.C_DATA_WIDTH ( C_MC_DATA_WIDTH ),
.C_AXSIZE ( P_AXSIZE ),
.C_MC_nCK_PER_CLK ( C_MC_nCK_PER_CLK ),
.C_MC_BURST_LEN ( C_MC_BURST_LEN )
)
axi_mc_ar_channel_0
(
.clk ( aclk ) ,
.reset ( areset_d1 ) ,
.arid ( arid_d3 ) ,
.araddr ( araddr_d3 ) ,
.arlen ( arlen_d3 ) ,
.arsize ( P_AXSIZE[2:0] ) ,
.arburst ( arburst_d3 ) ,
.arlock ( arlock_d3 ) ,
.arcache ( arcache_d3 ) ,
.arprot ( arprot_d3 ) ,
.arqos ( arqos_d3 ) ,
.arvalid ( arvalid_d3 ) ,
.arready ( arready_d3 ) ,
.cmd_en ( rd_cmd_en ) ,
.cmd_instr ( rd_cmd_instr ) ,
.cmd_byte_addr ( rd_cmd_byte_addr ) ,
.cmd_full ( rd_cmd_full ) ,
.cmd_en_last ( rd_cmd_en_last ) ,
.r_push ( r_push ) ,
.r_arid ( r_arid ) ,
.r_rlast ( r_rlast ) ,
.r_data_rdy ( r_data_rdy ) ,
.r_ignore_begin ( r_ignore_begin ) ,
.r_ignore_end ( r_ignore_end ) ,
.arvalid_int ( arvalid_int ) ,
.arqos_int ( arqos_int )
);
mig_7series_v4_0_axi_mc_r_channel #
(
.C_ID_WIDTH ( C_S_AXI_ID_WIDTH ),
.C_DATA_WIDTH ( C_MC_DATA_WIDTH ),
.C_AXI_ADDR_WIDTH ( C_S_AXI_ADDR_WIDTH ),
.C_MC_BURST_MODE ( C_MC_BURST_MODE ),
.C_MC_BURST_LEN ( C_MC_BURST_LEN )
)
axi_mc_r_channel_0
(
.clk ( aclk ) ,
.reset ( areset_d1 ) ,
.rid ( rid_d3 ) ,
.rdata ( rdata_d3 ) ,
.rresp ( rresp_d3 ) ,
.rlast ( rlast_d3 ) ,
.rvalid ( rvalid_d3 ) ,
.rready ( rready_d3 ) ,
.mc_app_rd_valid ( mc_app_rd_valid ) ,
.mc_app_rd_data ( mc_app_rd_data ) ,
.mc_app_rd_last ( mc_app_rd_end ) ,
.mc_app_ecc_multiple_err ( |mc_app_ecc_multiple_err ) ,
.r_push ( r_push ) ,
.r_data_rdy ( r_data_rdy ) ,
.r_arid ( r_arid ) ,
.r_rlast ( r_rlast ) ,
.r_ignore_begin ( r_ignore_begin ) ,
.r_ignore_end ( r_ignore_end )
);
// Arbiter
mig_7series_v4_0_axi_mc_cmd_arbiter #
(
.C_MC_ADDR_WIDTH ( C_MC_ADDR_WIDTH ) ,
.C_MC_BURST_LEN ( C_MC_BURST_LEN ) ,
.C_RD_WR_ARB_ALGORITHM ( C_RD_WR_ARB_ALGORITHM )
)
axi_mc_cmd_arbiter_0
(
.clk ( aclk ) ,
.reset ( areset_d1 ) ,
// Write commands from AXI
.wr_cmd_en ( wr_cmd_en ) ,
.wr_cmd_en_last ( wr_cmd_en_last ) ,
.wr_cmd_instr ( wr_cmd_instr ) ,
.wr_cmd_byte_addr ( wr_cmd_byte_addr ) ,
.wr_cmd_full ( wr_cmd_full ) ,
// Read commands from AXI
.rd_cmd_en ( rd_cmd_en ) ,
.rd_cmd_en_last ( rd_cmd_en_last ) ,
.rd_cmd_instr ( rd_cmd_instr ) ,
.rd_cmd_byte_addr ( rd_cmd_byte_addr ) ,
.rd_cmd_full ( rd_cmd_full ) ,
// Next Command info
.arvalid ( arvalid_int ) ,
.arqos ( arqos_int ) ,
.awvalid ( awvalid_int ) ,
.awqos ( awqos_int ) ,
// To MC
.mc_app_en ( mc_app_en ) ,
.mc_app_cmd ( mc_app_cmd ) ,
.mc_app_size ( mc_app_sz ) ,
.mc_app_addr ( mc_app_addr ) ,
.mc_app_hi_pri ( mc_app_hi_pri ) ,
.mc_app_rdy ( mc_app_rdy )
);
endmodule
`default_nettype wire
|
(** Semantics of the “one-varmap” intermediate language.
*)
Require psem one_varmap.
Import Utf8.
Import all_ssreflect.
Export one_varmap.
Import psem var.
Import low_memory.
Require Import arch_decl arch_extra.
Set Implicit Arguments.
Unset Strict Implicit.
Unset Printing Implicit Defensive.
Local Unset Elimination Schemes.
Local Open Scope vmap_scope.
(** Semantics of programs in which there is a single scope for local variables.
Function arguments and returns are passed by name:
the caller puts the arguments in the right variables and read them from the right variables.
Also the instructions may be annotated with variables that are known to be free:
this semantics explicitly kills these variables before executing the corresponding instruction.
The semantics also ensures some properties:
- No for loop
- Calls to “rastack” functions are annotated with free variables
- The sp_rsp local variable always hold the pointer to the top of the stack
- The sp_rip local variable is assumed to hold the pointer to the static global data
- The var_tmp local variable is free at the beginning of export functions
The semantic predicates are indexed by a set of variables which is *precisely* the set of variables that are written during the execution.
*)
Section ASM_EXTRA.
Context {reg xreg rflag cond asm_op extra_op} {asm_e : asm_extra reg xreg rflag cond asm_op extra_op}.
Definition get_pvar (e: pexpr) : exec var :=
if e is Pvar {| gv := x ; gs := Slocal |} then ok (v_var x) else type_error.
Definition get_lvar (x: lval) : exec var :=
if x is Lvar x then ok (v_var x) else type_error.
Definition kill_var (x: var) (vm: vmap) : vmap :=
vm.[x <- pundef_addr (vtype x)].
End ASM_EXTRA.
Notation kill_vars := (Sv.fold kill_var).
Section ASM_EXTRA.
Context {reg xreg rflag cond asm_op extra_op} {asm_e : asm_extra reg xreg rflag cond asm_op extra_op}.
Lemma kill_varE vm y x :
((kill_var x vm).[y] = if x == y then pundef_addr (vtype y) else vm.[y])%vmap.
Proof.
by rewrite /kill_var Fv.setP; case: eqP => // ?; subst y.
Qed.
Lemma kill_varsE vm xs x :
((kill_vars xs vm).[x] = if Sv.mem x xs then pundef_addr (vtype x) else vm.[x])%vmap.
Proof.
rewrite Sv_elems_eq Sv.fold_spec.
elim: (Sv.elements xs) vm => // {xs} f xs ih vm /=.
rewrite ih {ih} inE kill_varE eq_sym.
by case: eqP => //= ->; case: ifP => // _; case: vm.[_] => // _; case: pundef_addr.
Qed.
Lemma kill_vars_uincl vm xs :
wf_vm vm ->
vm_uincl (kill_vars xs vm) vm.
Proof.
move => hwf x; rewrite kill_varsE.
case: ifP => // _.
case: vm.[x] (hwf x)=> // [v | e].
+ by move=> _; apply eval_uincl_undef.
case: e => //; case: (vtype x) => //.
Qed.
Section SEM.
Context
(p: sprog)
(extra_free_registers: instr_info -> option var)
(var_tmp: var)
(callee_saved: Sv.t).
Local Notation gd := (p_globs p).
Definition kill_extra_register_vmap ii (vm: vmap) : vmap :=
if extra_free_registers ii is Some x
then if vm.[x] is Ok _ then vm.[x <- pundef_addr (vtype x) ] else vm
else vm.
Definition kill_extra_register ii (s: estate) : estate :=
with_vm s (kill_extra_register_vmap ii s.(evm)).
Remark kill_extra_register_vm_uincl ii s :
vm_uincl (kill_extra_register ii s).(evm) (evm s).
Proof.
rewrite /= /kill_extra_register_vmap.
case: extra_free_registers => // x y.
case hx: (evm s).[x] => [ v | ] //; case: (x =P y).
+ move => <- {y}; rewrite hx Fv.setP_eq; apply: eval_uincl_undef; exact: subtype_refl.
by move => /eqP x_ne_y; rewrite Fv.setP_neq.
Qed.
Let vgd : var := vid p.(p_extra).(sp_rip).
Let vrsp : var := vid p.(p_extra).(sp_rsp).
#[local] Notation magic_variables := (magic_variables p).
#[local] Notation extra_free_registers_at := (extra_free_registers_at extra_free_registers).
Definition ra_valid fd ii (k: Sv.t) (x: var) : bool :=
match fd.(f_extra).(sf_return_address) with
| RAstack _ =>
extra_free_registers ii != None
| RAreg ra =>
[&& (ra != vgd), (ra != vrsp) & (~~ Sv.mem ra k) ]
| RAnone => true
end.
Definition ra_undef_none (ss: saved_stack) (x: var) :=
Sv.union (Sv.add x (sv_of_flags rflags)) (savedstackreg ss).
Definition ra_undef_vm_none (ss: saved_stack) (x: var) vm : vmap :=
kill_vars (ra_undef_none ss x) vm.
Definition ra_undef_vm fd vm (x: var) : vmap :=
kill_vars (ra_undef fd x) vm.
Definition saved_stack_valid fd (k: Sv.t) : bool :=
if fd.(f_extra).(sf_save_stack) is SavedStackReg r
then [&& (r != vgd), (r != vrsp) & (~~ Sv.mem r k) ]
else true.
Definition efr_valid ii i : bool :=
if extra_free_registers ii is Some r
then [&& r != vgd, r != vrsp, vtype r == sword Uptr &
if i is Cwhile _ _ _ _ then false else true]
else true.
Definition top_stack_aligned fd st : bool :=
(fd.(f_extra).(sf_return_address) == RAnone)
|| is_align (top_stack st.(emem)) fd.(f_extra).(sf_align).
Definition set_RSP m vm : vmap :=
vm.[vrsp <- ok (pword_of_word (top_stack m))].
#[global] Arguments set_RSP _ _%vmap_scope.
Definition valid_RSP m (vm: vmap) : Prop :=
vm.[vrsp] = ok (pword_of_word (top_stack m)).
Remark valid_set_RSP m vm :
valid_RSP m (set_RSP m vm).
Proof. by rewrite /valid_RSP Fv.setP_eq. Qed.
Inductive sem : Sv.t → estate → cmd → estate → Prop :=
| Eskip s :
sem Sv.empty s [::] s
| Eseq ki kc s1 s2 s3 i c :
sem_I ki s1 i s2 →
sem kc s2 c s3 →
sem (Sv.union ki kc) s1 (i :: c) s3
with sem_I : Sv.t → estate → instr → estate → Prop :=
| EmkI ii k i s1 s2:
efr_valid ii i →
sem_i ii k (kill_extra_register ii s1) i s2 →
disjoint k magic_variables →
sem_I (Sv.union (extra_free_registers_at ii) k) s1 (MkI ii i) s2
with sem_i : instr_info → Sv.t → estate → instr_r → estate → Prop :=
| Eassgn ii s1 s2 (x:lval) tag ty e v v' :
sem_pexpr gd s1 e = ok v →
truncate_val ty v = ok v' →
write_lval gd x v' s1 = ok s2 →
sem_i ii (vrv x) s1 (Cassgn x tag ty e) s2
| Eopn ii s1 s2 t o xs es:
sem_sopn gd o s1 xs es = ok s2 →
sem_i ii (vrvs xs) s1 (Copn xs t o es) s2
| Eif_true ii k s1 s2 e c1 c2 :
sem_pexpr gd s1 e = ok (Vbool true) →
sem k s1 c1 s2 →
sem_i ii k s1 (Cif e c1 c2) s2
| Eif_false ii k s1 s2 e c1 c2 :
sem_pexpr gd s1 e = ok (Vbool false) →
sem k s1 c2 s2 →
sem_i ii k s1 (Cif e c1 c2) s2
| Ewhile_true ii k k' krec s1 s2 s3 s4 a c e c' :
sem k s1 c s2 →
sem_pexpr gd s2 e = ok (Vbool true) →
sem k' s2 c' s3 →
sem_I krec s3 (MkI ii (Cwhile a c e c')) s4 →
sem_i ii (Sv.union (Sv.union k k') krec) s1 (Cwhile a c e c') s4
| Ewhile_false ii k s1 s2 a c e c' :
sem k s1 c s2 →
sem_pexpr gd s2 e = ok (Vbool false) →
sem_i ii k s1 (Cwhile a c e c') s2
| Ecall ii k s1 s2 ini res f args xargs xres :
mapM get_pvar args = ok xargs →
mapM get_lvar res = ok xres →
sem_call ii k s1 f s2 →
sem_i ii k s1 (Ccall ini res f args) s2
with sem_call : instr_info → Sv.t → estate → funname → estate → Prop :=
| EcallRun ii k s1 s2 fn f args m1 s2' res :
get_fundef (p_funcs p) fn = Some f →
ra_valid f ii k var_tmp →
saved_stack_valid f k →
top_stack_aligned f s1 →
valid_RSP s1.(emem) s1.(evm) →
alloc_stack
s1.(emem)
f.(f_extra).(sf_align)
f.(f_extra).(sf_stk_sz)
f.(f_extra).(sf_stk_extra_sz)
= ok m1 →
mapM (λ x : var_i, get_var s1.(evm) x) f.(f_params) = ok args →
all2 check_ty_val f.(f_tyin) args →
let vm1 := ra_undef_vm f s1.(evm) var_tmp in
sem k {| emem := m1; evm := set_RSP m1 vm1; |} f.(f_body) s2' →
mapM (λ x : var_i, get_var s2'.(evm) x) f.(f_res) = ok res →
all2 check_ty_val f.(f_tyout) res →
valid_RSP s2'.(emem) s2'.(evm) →
let m2 := free_stack s2'.(emem) in
s2 = {| emem := m2 ; evm := set_RSP m2 s2'.(evm) |} →
let vm := Sv.union (ra_vm f.(f_extra) var_tmp) (saved_stack_vm f) in
sem_call ii (Sv.union k vm) s1 fn s2.
Variant sem_export_call_conclusion (m: mem) (fd: sfundef) (args: values) (vm: vmap) (m': mem) (res: values) : Prop :=
| SemExportCallConclusion (m1: mem) (k: Sv.t) (m2: mem) (vm2: vmap) (res': values) of
saved_stack_valid fd k &
Sv.Subset (Sv.inter callee_saved (Sv.union k (Sv.union (ra_vm fd.(f_extra) var_tmp) (saved_stack_vm fd)))) (sv_of_list fst fd.(f_extra).(sf_to_save)) &
alloc_stack m fd.(f_extra).(sf_align) fd.(f_extra).(sf_stk_sz) fd.(f_extra).(sf_stk_extra_sz) = ok m1 &
all2 check_ty_val fd.(f_tyin) args &
sem k {| emem := m1 ; evm := set_RSP m1 (ra_undef_vm_none fd.(f_extra).(sf_save_stack) var_tmp vm) |} fd.(f_body) {| emem := m2 ; evm := vm2 |} &
mapM (λ x : var_i, get_var vm2 x) fd.(f_res) = ok res' &
List.Forall2 value_uincl res res' &
all2 check_ty_val fd.(f_tyout) res' &
valid_RSP m2 vm2 &
m' = free_stack m2.
Variant sem_export_call (gd: @extra_val_t _ progStack) (m: mem) (fn: funname) (args: values) (m': mem) (res: values) : Prop :=
| SemExportCall (fd: sfundef) of
get_fundef p.(p_funcs) fn = Some fd &
fd.(f_extra).(sf_return_address) == RAnone &
disjoint (sv_of_list fst fd.(f_extra).(sf_to_save)) (sv_of_list v_var fd.(f_res)) &
~~ Sv.mem vrsp (sv_of_list v_var fd.(f_res)) &
∀ vm args',
wf_vm vm →
mapM (λ x : var_i, get_var vm x) fd.(f_params) = ok args' →
List.Forall2 value_uincl args args' →
valid_RSP m vm →
vm.[vgd] = ok (pword_of_word gd) →
sem_export_call_conclusion m fd args' vm m' res.
(*---------------------------------------------------*)
Variant ex3_3 (A B C : Type) (P1 P2 P3: A → B → C → Prop) : Prop :=
Ex3_3 a b c of P1 a b c & P2 a b c & P3 a b c.
Variant ex6_14 (A B C D E F : Type) (P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 : A → B → C → D → E → F → Prop) : Prop :=
| Ex6_14 a b c d e f of P1 a b c d e f & P2 a b c d e f & P3 a b c d e f & P4 a b c d e f & P5 a b c d e f & P6 a b c d e f & P7 a b c d e f & P8 a b c d e f & P9 a b c d e f & P10 a b c d e f & P11 a b c d e f & P12 a b c d e f & P13 a b c d e f & P14 a b c d e f.
(*---------------------------------------------------*)
(* Small inversion principles *)
Lemma semE k s c s' :
sem k s c s' →
match c with
| [::] => k = Sv.empty ∧ s = s'
| i :: c => ex3_3
(λ ki kc _, k = Sv.union ki kc)
(λ ki _ si, sem_I ki s i si)
(λ _ kc si, sem kc si c s')
end.
Proof. by case => // {k s c s'} ki kc s si s' i c; exists ki kc si. Qed.
Lemma sem_IE k s i s' :
sem_I k s i s' →
let: MkI ii r := i in
∃ k',
[/\
efr_valid ii r,
sem_i ii k' (kill_extra_register ii s) r s',
disjoint k' magic_variables &
k = Sv.union (extra_free_registers_at ii) k' ].
Proof. by case => {k s i s'} ii k i s1 s2 ???; exists k. Qed.
Lemma sem_iE ii k s i s' :
sem_i ii k s i s' →
match i with
| Cassgn x tag ty e =>
k = vrv x ∧
exists2 v', sem_pexpr gd s e >>= truncate_val ty = ok v' & write_lval gd x v' s = ok s'
| Copn xs t o es => k = vrvs xs ∧ sem_sopn gd o s xs es = ok s'
| Cif e c1 c2 =>
exists2 b, sem_pexpr gd s e = ok (Vbool b) & sem k s (if b then c1 else c2) s'
| Cwhile a c e c' =>
∃ kc si b,
[/\ sem kc s c si, sem_pexpr gd si e = ok (Vbool b) &
if b then ex3_3 (λ k' krec _, k = Sv.union (Sv.union kc k') krec) (λ k' _ sj, sem k' si c' sj) (λ _ krec sj, sem_I krec sj (MkI ii (Cwhile a c e c')) s') else si = s' ∧ kc = k ]
| Ccall ini res f args =>
exists2 xargs,
mapM get_pvar args = ok xargs &
exists2 xres,
mapM get_lvar res = ok xres &
sem_call ii k s f s'
| Cfor _ _ _ => false
end.
Proof.
case => { ii k s i s' }; eauto.
- move => _ s s' x _ ty e v v' -> /= ->; eauto.
- move => ii k k' krec s1 s2 s3 s4 a c e c' exec_c eval_e exec_c' rec; exists k, s2, true; split; try eexists; eauto.
by move => ii k s1 s2 a c e c' exec_c eval_e; exists k, s2, false.
Qed.
Lemma sem_callE ii k s fn s' :
sem_call ii k s fn s' →
ex6_14
(λ f _ _ _ _ _, get_fundef (p_funcs p) fn = Some f)
(λ f _ _ k' _ _, ra_valid f ii k' var_tmp)
(λ f _ _ k' _ _, saved_stack_valid f k')
(λ f _ _ _ _ _, top_stack_aligned f s)
(λ _ _ _ _ _ _, valid_RSP s.(emem) s.(evm))
(λ f m1 _ _ _ _, alloc_stack s.(emem) f.(f_extra).(sf_align) f.(f_extra).(sf_stk_sz) f.(f_extra).(sf_stk_extra_sz) = ok m1)
(λ f _ _ _ args _, mapM (λ x : var_i, get_var s.(evm) x) f.(f_params) = ok args)
(λ f _ _ _ args _, all2 check_ty_val f.(f_tyin) args)
(λ f m1 s2' k' _ _,
let vm := ra_undef_vm f s.(evm) var_tmp in
sem k' {| emem := m1 ; evm := set_RSP m1 vm; |} f.(f_body) s2')
(λ f _ s2' _ _ res, mapM (λ x : var_i, get_var s2'.(evm) x) f.(f_res) = ok res)
(λ f _ _ _ _ res, all2 check_ty_val f.(f_tyout) res)
(λ _ _ s2' _ _ _, valid_RSP s2'.(emem) s2'.(evm))
(λ f _ s2' _ _ _,
let m2 := free_stack s2'.(emem) in
s' = {| emem := m2 ; evm := set_RSP m2 s2'.(evm) |})
(λ f _ _ k' _ _,
k = Sv.union k' (Sv.union (ra_vm f.(f_extra) var_tmp) (saved_stack_vm f))).
Proof.
case => { ii k s fn s' } /= ii k s s' fn f args m1 s2' res => ok_f ok_ra ok_ss ok_sp ok_RSP ok_alloc ok_args wt_args exec_body ok_RSP' ok_res wt_res /= ->.
by exists f m1 s2' k args res.
Qed.
(*---------------------------------------------------*)
Lemma sv_of_flagsE x l : Sv.mem x (sv_of_flags l) = (x \in map (fun r => to_var r) l).
Proof. exact: sv_of_listE. Qed.
Lemma sv_of_flagsP x l : reflect (Sv.In x (sv_of_flags l)) (x \in map (fun r => to_var r) l).
Proof. exact: sv_of_listP. Qed.
(*---------------------------------------------------*)
(* Induction principle *)
Section SEM_IND.
Variables
(Pc : Sv.t → estate → cmd → estate → Prop)
(Pi : Sv.t → estate → instr → estate → Prop)
(Pi_r : instr_info → Sv.t → estate → instr_r → estate → Prop)
(Pfun : instr_info → Sv.t → estate → funname → estate → Prop).
Definition sem_Ind_nil : Prop :=
∀ (s : estate), Pc Sv.empty s [::] s.
Definition sem_Ind_cons : Prop :=
∀ (ki kc: Sv.t) (s1 s2 s3 : estate) (i : instr) (c : cmd),
sem_I ki s1 i s2 → Pi ki s1 i s2 →
sem kc s2 c s3 → Pc kc s2 c s3 →
Pc (Sv.union ki kc) s1 (i :: c) s3.
Hypotheses
(Hnil: sem_Ind_nil)
(Hcons: sem_Ind_cons)
.
Definition sem_Ind_mkI : Prop :=
∀ (ii : instr_info) (k: Sv.t) (i : instr_r) (s1 s2 : estate),
efr_valid ii i →
sem_i ii k (kill_extra_register ii s1) i s2 →
Pi_r ii k (kill_extra_register ii s1) i s2 →
disjoint k magic_variables →
Pi (Sv.union (extra_free_registers_at ii) k) s1 (MkI ii i) s2.
Hypothesis HmkI : sem_Ind_mkI.
Definition sem_Ind_assgn : Prop :=
∀ (ii: instr_info) (s1 s2 : estate) (x : lval) (tag : assgn_tag) ty (e : pexpr) v v',
sem_pexpr gd s1 e = ok v →
truncate_val ty v = ok v' →
write_lval gd x v' s1 = ok s2 →
Pi_r ii (vrv x) s1 (Cassgn x tag ty e) s2.
Definition sem_Ind_opn : Prop :=
∀ (ii: instr_info) (s1 s2 : estate) t (o : sopn) (xs : lvals) (es : pexprs),
sem_sopn gd o s1 xs es = ok s2 →
Pi_r ii (vrvs xs) s1 (Copn xs t o es) s2.
Definition sem_Ind_if_true : Prop :=
∀ (ii: instr_info) (k: Sv.t) (s1 s2 : estate) (e : pexpr) (c1 c2 : cmd),
sem_pexpr gd s1 e = ok (Vbool true) →
sem k s1 c1 s2 → Pc k s1 c1 s2 → Pi_r ii k s1 (Cif e c1 c2) s2.
Definition sem_Ind_if_false : Prop :=
∀ (ii: instr_info) (k: Sv.t) (s1 s2 : estate) (e : pexpr) (c1 c2 : cmd),
sem_pexpr gd s1 e = ok (Vbool false) →
sem k s1 c2 s2 → Pc k s1 c2 s2 → Pi_r ii k s1 (Cif e c1 c2) s2.
Definition sem_Ind_while_true : Prop :=
∀ (ii: instr_info) (k k' krec: Sv.t) (s1 s2 s3 s4 : estate) a (c : cmd) (e : pexpr) (c' : cmd),
sem k s1 c s2 → Pc k s1 c s2 →
sem_pexpr gd s2 e = ok (Vbool true) →
sem k' s2 c' s3 → Pc k' s2 c' s3 →
sem_I krec s3 (MkI ii (Cwhile a c e c')) s4 →
Pi krec s3 (MkI ii (Cwhile a c e c')) s4 →
Pi_r ii (Sv.union (Sv.union k k') krec) s1 (Cwhile a c e c') s4.
Definition sem_Ind_while_false : Prop :=
∀ (ii: instr_info) (k: Sv.t) (s1 s2 : estate) a (c : cmd) (e : pexpr) (c' : cmd),
sem k s1 c s2 →
Pc k s1 c s2 →
sem_pexpr gd s2 e = ok (Vbool false) →
Pi_r ii k s1 (Cwhile a c e c') s2.
Hypotheses
(Hasgn: sem_Ind_assgn)
(Hopn: sem_Ind_opn)
(Hif_true: sem_Ind_if_true)
(Hif_false: sem_Ind_if_false)
(Hwhile_true: sem_Ind_while_true)
(Hwhile_false: sem_Ind_while_false)
.
Definition sem_Ind_call : Prop :=
∀ (ii: instr_info) (k: Sv.t) (s1 s2: estate) ini res fn args xargs xres,
mapM get_pvar args = ok xargs →
mapM get_lvar res = ok xres →
sem_call ii k s1 fn s2 →
Pfun ii k s1 fn s2 →
Pi_r ii k s1 (Ccall ini res fn args) s2.
Definition sem_Ind_proc : Prop :=
∀ (ii: instr_info) (k: Sv.t) (s1 s2: estate) (fn: funname) fd args m1 s2' res,
get_fundef (p_funcs p) fn = Some fd →
ra_valid fd ii k var_tmp →
saved_stack_valid fd k →
top_stack_aligned fd s1 →
valid_RSP s1.(emem) s1.(evm) →
alloc_stack s1.(emem) fd.(f_extra).(sf_align) fd.(f_extra).(sf_stk_sz) fd.(f_extra).(sf_stk_extra_sz) = ok m1 →
mapM (λ x : var_i, get_var s1.(evm) x) fd.(f_params) = ok args →
all2 check_ty_val fd.(f_tyin) args →
let vm1 := ra_undef_vm fd s1.(evm) var_tmp in
sem k {| emem := m1; evm := set_RSP m1 vm1; |} fd.(f_body) s2' →
Pc k {| emem := m1; evm := set_RSP m1 vm1; |} fd.(f_body) s2' →
mapM (λ x : var_i, get_var s2'.(evm) x) fd.(f_res) = ok res →
all2 check_ty_val fd.(f_tyout) res →
valid_RSP s2'.(emem) s2'.(evm) →
let m2 := free_stack s2'.(emem) in
s2 = {| emem := m2 ; evm := set_RSP m2 s2'.(evm) |} →
let vm := Sv.union k (Sv.union (ra_vm fd.(f_extra) var_tmp) (saved_stack_vm fd)) in
Pfun ii vm s1 fn s2.
Hypotheses
(Hcall: sem_Ind_call)
(Hproc: sem_Ind_proc)
.
Fixpoint sem_Ind (k: Sv.t) (s1 : estate) (c : cmd) (s2 : estate) (s: sem k s1 c s2) {struct s} :
Pc k s1 c s2 :=
match s in sem k s1 c s2 return Pc k s1 c s2 with
| Eskip s0 => Hnil s0
| @Eseq ki kc s1 s2 s3 i c s0 s4 =>
@Hcons ki kc s1 s2 s3 i c s0 (@sem_I_Ind ki s1 i s2 s0) s4 (@sem_Ind kc s2 c s3 s4)
end
with sem_i_Ind (ii: instr_info) (k: Sv.t) (e : estate) (i : instr_r) (e0 : estate) (s : sem_i ii k e i e0) {struct s} :
Pi_r ii k e i e0 :=
match s in sem_i ii k s1 i s2 return Pi_r ii k s1 i s2 with
| @Eassgn ii s1 s2 x tag ty e1 v v' h1 h2 h3 => @Hasgn ii s1 s2 x tag ty e1 v v' h1 h2 h3
| @Eopn ii s1 s2 t o xs es e1 => @Hopn ii s1 s2 t o xs es e1
| @Eif_true ii k s1 s2 e1 c1 c2 e2 s0 =>
@Hif_true ii k s1 s2 e1 c1 c2 e2 s0 (@sem_Ind k s1 c1 s2 s0)
| @Eif_false ii k s1 s2 e1 c1 c2 e2 s0 =>
@Hif_false ii k s1 s2 e1 c1 c2 e2 s0 (@sem_Ind k s1 c2 s2 s0)
| @Ewhile_true ii k k' krec s1 s2 s3 s4 a c e1 c' s0 e2 s5 s6 =>
@Hwhile_true ii k k' krec s1 s2 s3 s4 a c e1 c' s0 (@sem_Ind k s1 c s2 s0) e2 s5 (@sem_Ind k' s2 c' s3 s5) s6
(@sem_I_Ind krec s3 (MkI ii (Cwhile a c e1 c')) s4 s6)
| @Ewhile_false ii k s1 s2 a c e1 c' s0 e2 =>
@Hwhile_false ii k s1 s2 a c e1 c' s0 (@sem_Ind k s1 c s2 s0) e2
| @Ecall ii k s1 s2 ini res fn args xargs xres hargs hres exec =>
@Hcall ii k s1 s2 ini res fn args xargs xres hargs hres exec (@sem_call_Ind ii k s1 fn s2 exec)
end
with sem_I_Ind (k: Sv.t) (s1 : estate) (i : instr) (s2 : estate) (s : sem_I k s1 i s2) {struct s} : Pi k s1 i s2 :=
match s in sem_I k e1 i0 e2 return Pi k e1 i0 e2 with
| @EmkI ii k i s1 s2 nom exec pm => @HmkI ii k i s1 s2 nom exec (@sem_i_Ind ii k _ i s2 exec) pm
end
with sem_call_Ind (ii: instr_info) (k: Sv.t) (s1: estate) (fn: funname) (s2: estate) (s: sem_call ii k s1 fn s2) {struct s} : Pfun ii k s1 fn s2 :=
match s with
| @EcallRun ii k s1 s2 fn fd args m1 s2' res ok_fd ok_ra ok_ss ok_sp ok_rsp ok_args wt_args ok_m1 exec ok_res wt_res ok_rsp' ok_s2 =>
@Hproc ii k s1 s2 fn fd args m1 s2' res ok_fd ok_ra ok_ss ok_sp ok_rsp ok_args wt_args ok_m1 exec (@sem_Ind k _ _ _ exec) ok_res wt_res ok_rsp' ok_s2
end.
End SEM_IND.
End SEM.
End ASM_EXTRA.
|
// This is a modified version of the primitive.v of the verilog to routing project:
https://github.com/verilog-to-routing/vtr-verilog-to-routing.
Therefore this file is under MIT License.
//Overivew
//========
//This file contains the verilog primitives produced by VPR's
//post-synthesis netlist writer.
//
//K-input Look-Up Table
module LUT_K #(
//The Look-up Table size (number of inputs)
parameter K = 6,
//The lut mask.
//Left-most (MSB) bit corresponds to all inputs logic one.
//Defaults to always false.
parameter LUT_MASK={2**K{1'b0}}
) (
input [K-1:0] in,
output out
);
assign out = LUT_MASK[in];
endmodule
//D-FlipFlop module
module DFF #(
parameter INITIAL_VALUE=1'b0
) (
input clock,
input D,
output reg Q
);
initial begin
Q <= INITIAL_VALUE;
end
always@(posedge clock) begin
Q <= D;
end
endmodule
//D-FlipFlop module
module DFF_RESET #(
parameter INITIAL_VALUE=1'b0
) (
input clock,
input D,
input reset,
output reg Q
);
initial begin
Q <= INITIAL_VALUE;
end
always@(posedge clock or posedge reset) begin
if (reset == 1'b1) begin
Q <= INITIAL_VALUE;
end else begin
Q <= D;
end
end
endmodule
//Routing fpga_interconnect module
module fpga_interconnect(
input datain,
output dataout
);
assign dataout = datain;
endmodule
//2-to-1 mux module
module mux(
input select,
input x,
input y,
output z
);
assign z = (x & ~select) | (y & select);
endmodule
|
//*****************************************************************************
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//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:%version
// \ \ Application: MIG
// / / Filename: mig_7series_v2_3_poc_top.v
// /___/ /\ Date Last Modified: $$
// \ \ / \ Date Created:Tue 15 Jan 2014
// \___\/\___\
//
//Device: Virtex-7
//Design Name: DDR3 SDRAM
//Purpose: Phaser out calibration top.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v2_3_poc_top #
(parameter MMCM_SAMP_WAIT = 10,
parameter PCT_SAMPS_SOLID = 95,
parameter POC_USE_METASTABLE_SAMP = "FALSE",
parameter TCQ = 100,
parameter CCENABLE = 0,
parameter SCANFROMRIGHT = 0,
parameter SAMPCNTRWIDTH = 8,
parameter SAMPLES = 128,
parameter TAPCNTRWIDTH = 7,
parameter TAPSPERKCLK =112)
(/*AUTOARG*/
// Outputs
psincdec, poc_error, poc_backup, psen, rise_lead_right,
rise_trail_right, mmcm_edge_detect_done, mmcm_lbclk_edge_aligned,
// Inputs
use_noise_window, rst, psdone, poc_sample_pd, pd_out,
ninety_offsets, mmcm_edge_detect_rdy, ktap_at_right_edge,
ktap_at_left_edge, clk
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input clk; // To u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v, ...
input ktap_at_left_edge; // To u_poc_meta of mig_7series_v2_3_poc_meta.v, ...
input ktap_at_right_edge; // To u_poc_meta of mig_7series_v2_3_poc_meta.v, ...
input mmcm_edge_detect_rdy; // To u_poc_meta of mig_7series_v2_3_poc_meta.v
input [1:0] ninety_offsets; // To u_poc_meta of mig_7series_v2_3_poc_meta.v
input pd_out; // To u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v
input poc_sample_pd; // To u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v
input psdone; // To u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v
input rst; // To u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v, ...
input use_noise_window; // To u_poc_meta of mig_7series_v2_3_poc_meta.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output poc_backup; // From u_poc_meta of mig_7series_v2_3_poc_meta.v
output poc_error; // From u_poc_cc of mig_7series_v2_3_poc_cc.v
output psincdec; // From u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v
// End of automatics
/*AUTOwire*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [TAPCNTRWIDTH-1:0] fall_lead_center; // From u_edge_center of mig_7series_v2_3_poc_edge_store.v
wire [TAPCNTRWIDTH-1:0] fall_lead_left; // From u_edge_left of mig_7series_v2_3_poc_edge_store.v
wire [TAPCNTRWIDTH-1:0] fall_lead_right; // From u_edge_right of mig_7series_v2_3_poc_edge_store.v
wire [TAPCNTRWIDTH-1:0] fall_trail_center; // From u_edge_center of mig_7series_v2_3_poc_edge_store.v
wire [TAPCNTRWIDTH-1:0] fall_trail_left; // From u_edge_left of mig_7series_v2_3_poc_edge_store.v
wire [TAPCNTRWIDTH-1:0] fall_trail_right; // From u_edge_right of mig_7series_v2_3_poc_edge_store.v
wire [TAPCNTRWIDTH-1:0] rise_lead_center; // From u_edge_center of mig_7series_v2_3_poc_edge_store.v
wire [TAPCNTRWIDTH-1:0] rise_lead_left; // From u_edge_left of mig_7series_v2_3_poc_edge_store.v
wire [TAPCNTRWIDTH-1:0] rise_trail_center; // From u_edge_center of mig_7series_v2_3_poc_edge_store.v
wire [TAPCNTRWIDTH-1:0] rise_trail_left; // From u_edge_left of mig_7series_v2_3_poc_edge_store.v
wire [TAPCNTRWIDTH-1:0] run; // From u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v
wire run_end; // From u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v
wire run_polarity; // From u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v
wire [SAMPCNTRWIDTH:0] samples; // From u_poc_cc of mig_7series_v2_3_poc_cc.v
wire [SAMPCNTRWIDTH:0] samps_hi_held; // From u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v
wire [SAMPCNTRWIDTH:0] samps_solid_thresh; // From u_poc_cc of mig_7series_v2_3_poc_cc.v
wire [TAPCNTRWIDTH-1:0] tap; // From u_poc_tap_base of mig_7series_v2_3_poc_tap_base.v
// End of automatics
output psen;
output [TAPCNTRWIDTH-1:0] rise_lead_right;
output [TAPCNTRWIDTH-1:0] rise_trail_right;
output mmcm_edge_detect_done;
output mmcm_lbclk_edge_aligned;
mig_7series_v2_3_poc_tap_base #
(/*AUTOINSTPARAM*/
// Parameters
.MMCM_SAMP_WAIT (MMCM_SAMP_WAIT),
.POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP),
.SAMPCNTRWIDTH (SAMPCNTRWIDTH),
.TAPCNTRWIDTH (TAPCNTRWIDTH),
.TAPSPERKCLK (TAPSPERKCLK),
.TCQ (TCQ))
u_poc_tap_base
(/*AUTOINST*/
// Outputs
.psen (psen),
.psincdec (psincdec),
.run (run[TAPCNTRWIDTH-1:0]),
.run_end (run_end),
.run_polarity (run_polarity),
.samps_hi_held (samps_hi_held[SAMPCNTRWIDTH:0]),
.tap (tap[TAPCNTRWIDTH-1:0]),
// Inputs
.clk (clk),
.pd_out (pd_out),
.poc_sample_pd (poc_sample_pd),
.psdone (psdone),
.rst (rst),
.samples (samples[SAMPCNTRWIDTH:0]),
.samps_solid_thresh (samps_solid_thresh[SAMPCNTRWIDTH:0]));
mig_7series_v2_3_poc_meta #
(/*AUTOINSTPARAM*/
// Parameters
.SCANFROMRIGHT (SCANFROMRIGHT),
.TAPCNTRWIDTH (TAPCNTRWIDTH),
.TAPSPERKCLK (TAPSPERKCLK),
.TCQ (TCQ))
u_poc_meta
(/*AUTOINST*/
// Outputs
.mmcm_edge_detect_done (mmcm_edge_detect_done),
.mmcm_lbclk_edge_aligned (mmcm_lbclk_edge_aligned),
.poc_backup (poc_backup),
// Inputs
.clk (clk),
.ktap_at_left_edge (ktap_at_left_edge),
.ktap_at_right_edge (ktap_at_right_edge),
.mmcm_edge_detect_rdy (mmcm_edge_detect_rdy),
.ninety_offsets (ninety_offsets[1:0]),
.rise_lead_center (rise_lead_center[TAPCNTRWIDTH-1:0]),
.rise_lead_left (rise_lead_left[TAPCNTRWIDTH-1:0]),
.rise_lead_right (rise_lead_right[TAPCNTRWIDTH-1:0]),
.rise_trail_center (rise_trail_center[TAPCNTRWIDTH-1:0]),
.rise_trail_left (rise_trail_left[TAPCNTRWIDTH-1:0]),
.rise_trail_right (rise_trail_right[TAPCNTRWIDTH-1:0]),
.rst (rst),
.run (run[TAPCNTRWIDTH-1:0]),
.run_end (run_end),
.run_polarity (run_polarity),
.use_noise_window (use_noise_window));
/*mig_7series_v2_3_poc_edge_store AUTO_TEMPLATE "edge_\(.*\)$" (
.\(.*\)lead (\1lead_@@"vl-bits"),
.\(.*\)trail (\1trail_@@"vl-bits"),
.select0 (ktap_at_@_edge),
.select1 (1'b1),)*/
mig_7series_v2_3_poc_edge_store #
(/*AUTOINSTPARAM*/
// Parameters
.TAPCNTRWIDTH (TAPCNTRWIDTH),
.TAPSPERKCLK (TAPSPERKCLK),
.TCQ (TCQ))
u_edge_right
(/*AUTOINST*/
// Outputs
.fall_lead (fall_lead_right[TAPCNTRWIDTH-1:0]), // Templated
.fall_trail (fall_trail_right[TAPCNTRWIDTH-1:0]), // Templated
.rise_lead (rise_lead_right[TAPCNTRWIDTH-1:0]), // Templated
.rise_trail (rise_trail_right[TAPCNTRWIDTH-1:0]), // Templated
// Inputs
.clk (clk),
.run (run[TAPCNTRWIDTH-1:0]),
.run_end (run_end),
.run_polarity (run_polarity),
.select0 (ktap_at_right_edge), // Templated
.select1 (1'b1), // Templated
.tap (tap[TAPCNTRWIDTH-1:0]));
mig_7series_v2_3_poc_edge_store #
(/*AUTOINSTPARAM*/
// Parameters
.TAPCNTRWIDTH (TAPCNTRWIDTH),
.TAPSPERKCLK (TAPSPERKCLK),
.TCQ (TCQ))
u_edge_left
(/*AUTOINST*/
// Outputs
.fall_lead (fall_lead_left[TAPCNTRWIDTH-1:0]), // Templated
.fall_trail (fall_trail_left[TAPCNTRWIDTH-1:0]), // Templated
.rise_lead (rise_lead_left[TAPCNTRWIDTH-1:0]), // Templated
.rise_trail (rise_trail_left[TAPCNTRWIDTH-1:0]), // Templated
// Inputs
.clk (clk),
.run (run[TAPCNTRWIDTH-1:0]),
.run_end (run_end),
.run_polarity (run_polarity),
.select0 (ktap_at_left_edge), // Templated
.select1 (1'b1), // Templated
.tap (tap[TAPCNTRWIDTH-1:0]));
wire not_ktap_at_right_edge = ~ktap_at_right_edge;
wire not_ktap_at_left_edge = ~ktap_at_left_edge;
/*mig_7series_v2_3_poc_edge_store AUTO_TEMPLATE "edge_\(.*\)$" (
.\(.*\)lead (\1lead_@@"vl-bits"),
.\(.*\)trail (\1trail_@@"vl-bits"),
.select0 (not_ktap_at_right_edge),
.select1 (not_ktap_at_left_edge),)*/
mig_7series_v2_3_poc_edge_store #
(/*AUTOINSTPARAM*/
// Parameters
.TAPCNTRWIDTH (TAPCNTRWIDTH),
.TAPSPERKCLK (TAPSPERKCLK),
.TCQ (TCQ))
u_edge_center
(/*AUTOINST*/
// Outputs
.fall_lead (fall_lead_center[TAPCNTRWIDTH-1:0]), // Templated
.fall_trail (fall_trail_center[TAPCNTRWIDTH-1:0]), // Templated
.rise_lead (rise_lead_center[TAPCNTRWIDTH-1:0]), // Templated
.rise_trail (rise_trail_center[TAPCNTRWIDTH-1:0]), // Templated
// Inputs
.clk (clk),
.run (run[TAPCNTRWIDTH-1:0]),
.run_end (run_end),
.run_polarity (run_polarity),
.select0 (not_ktap_at_right_edge), // Templated
.select1 (not_ktap_at_left_edge), // Templated
.tap (tap[TAPCNTRWIDTH-1:0]));
mig_7series_v2_3_poc_cc #
(/*AUTOINSTPARAM*/
// Parameters
.CCENABLE (CCENABLE),
.PCT_SAMPS_SOLID (PCT_SAMPS_SOLID),
.SAMPCNTRWIDTH (SAMPCNTRWIDTH),
.SAMPLES (SAMPLES),
.TAPCNTRWIDTH (TAPCNTRWIDTH),
.TCQ (TCQ))
u_poc_cc
(/*AUTOINST*/
// Outputs
.poc_error (poc_error),
.samples (samples[SAMPCNTRWIDTH:0]),
.samps_solid_thresh (samps_solid_thresh[SAMPCNTRWIDTH:0]),
// Inputs
.clk (clk),
.fall_lead_center (fall_lead_center[TAPCNTRWIDTH-1:0]),
.fall_lead_left (fall_lead_left[TAPCNTRWIDTH-1:0]),
.fall_lead_right (fall_lead_right[TAPCNTRWIDTH-1:0]),
.fall_trail_center (fall_trail_center[TAPCNTRWIDTH-1:0]),
.fall_trail_left (fall_trail_left[TAPCNTRWIDTH-1:0]),
.fall_trail_right (fall_trail_right[TAPCNTRWIDTH-1:0]),
.ktap_at_left_edge (ktap_at_left_edge),
.ktap_at_right_edge (ktap_at_right_edge),
.mmcm_edge_detect_done (mmcm_edge_detect_done),
.mmcm_lbclk_edge_aligned (mmcm_lbclk_edge_aligned),
.psen (psen),
.rise_lead_center (rise_lead_center[TAPCNTRWIDTH-1:0]),
.rise_lead_left (rise_lead_left[TAPCNTRWIDTH-1:0]),
.rise_lead_right (rise_lead_right[TAPCNTRWIDTH-1:0]),
.rise_trail_center (rise_trail_center[TAPCNTRWIDTH-1:0]),
.rise_trail_left (rise_trail_left[TAPCNTRWIDTH-1:0]),
.rise_trail_right (rise_trail_right[TAPCNTRWIDTH-1:0]),
.rst (rst),
.samps_hi_held (samps_hi_held[SAMPCNTRWIDTH:0]),
.tap (tap[TAPCNTRWIDTH-1:0]));
endmodule // mig_7series_v2_3_poc_top
// Local Variables:
// verilog-library-directories:(".")
// verilog-library-extensions:(".v")
// End:
|
`include "minsoc_bench_defines.v"
`include "minsoc_defines.v"
`include "or1200_defines.v"
`include "timescale.v"
module minsoc_bench();
`ifdef POSITIVE_RESET
localparam RESET_LEVEL = 1'b1;
`elsif NEGATIVE_RESET
localparam RESET_LEVEL = 1'b0;
`else
localparam RESET_LEVEL = 1'b1;
`endif
reg clock, reset;
//Debug interface
wire dbg_tms_i;
wire dbg_tck_i;
wire dbg_tdi_i;
wire dbg_tdo_o;
wire jtag_vref;
wire jtag_gnd;
//SPI wires
wire spi_mosi;
reg spi_miso;
wire spi_sclk;
wire [1:0] spi_ss;
//UART wires
wire uart_stx;
reg uart_srx;
//ETH wires
reg eth_col;
reg eth_crs;
wire eth_trst;
reg eth_tx_clk;
wire eth_tx_en;
wire eth_tx_er;
wire [3:0] eth_txd;
reg eth_rx_clk;
reg eth_rx_dv;
reg eth_rx_er;
reg [3:0] eth_rxd;
reg eth_fds_mdint;
wire eth_mdc;
wire eth_mdio;
//
// TASKS registers to communicate with interfaces
//
reg design_ready;
reg uart_echo;
`ifdef UART
reg [40*8-1:0] line;
reg [12*8-1:0] hello;
reg new_line;
reg new_char;
reg flush_line;
`endif
`ifdef ETHERNET
reg [7:0] eth_rx_data [0:1535]; //receive buffer ETH (max packet 1536)
reg [7:0] eth_tx_data [0:1535]; //send buffer ETH (max packet 1536)
localparam ETH_HDR = 14;
localparam ETH_PAYLOAD_MAX_LENGTH = 1518;//only able to send up to 1536 bytes with header (14 bytes) and CRC (4 bytes)
`endif
//
// Testbench mechanics
//
reg [7:0] program_mem[(1<<(`MEMORY_ADR_WIDTH+2))-1:0];
integer initialize, ptr;
reg [8*64:0] file_name;
integer firmware_size; // Note that the .hex file size is greater than this, as each byte in the file needs 2 hex characters.
integer firmware_size_in_header;
reg load_file;
initial begin
reset = ~RESET_LEVEL;
clock = 1'b0;
eth_tx_clk = 1'b0;
eth_rx_clk = 1'b0;
design_ready = 1'b0;
uart_echo = 1'b1;
`ifndef NO_CLOCK_DIVISION
minsoc_top_0.clk_adjust.clk_int = 1'b0;
minsoc_top_0.clk_adjust.clock_divisor = 32'h0000_0000;
`endif
uart_srx = 1'b1;
eth_col = 1'b0;
eth_crs = 1'b0;
eth_fds_mdint = 1'b1;
eth_rx_er = 1'b0;
eth_rxd = 4'h0;
eth_rx_dv = 1'b0;
//dual and two port rams from FPGA memory instances have to be initialized to 0
init_fpga_memory();
load_file = 1'b0;
`ifdef INITIALIZE_MEMORY_MODEL
load_file = 1'b1;
`endif
`ifdef START_UP
load_file = 1'b1;
`endif
//get firmware hex file from command line input
if ( load_file ) begin
if ( ! $value$plusargs("file_name=%s", file_name) || file_name == 0 ) begin
$display("ERROR: Please specify the name of the firmware file to load on start-up.");
$finish;
end
// We are passing the firmware size separately as a command-line argument in order
// to avoid this kind of Icarus Verilog warnings:
// WARNING: minsoc_bench_core.v:111: $readmemh: Standard inconsistency, following 1364-2005.
// WARNING: minsoc_bench_core.v:111: $readmemh(../../sw/uart/uart.hex): Not enough words in the file for the requested range [0:32767].
// Apparently, some of the $readmemh() warnigns are even required by the standard. The trouble is,
// Verilog's $fread() is not widely implemented in the simulators, so from Verilog alone
// it's not easy to read the firmware file header without getting such warnings.
if ( ! $value$plusargs("firmware_size=%d", firmware_size) ) begin
$display("ERROR: Please specify the size of the firmware (in bytes) contained in the hex firmware file.");
$finish;
end
$readmemh(file_name, program_mem, 0, firmware_size - 1);
firmware_size_in_header = { program_mem[0] , program_mem[1] , program_mem[2] , program_mem[3] };
if ( firmware_size != firmware_size_in_header ) begin
$display("ERROR: The firmware size in the file header does not match the firmware size given as command-line argument. Did you forget bin2hex's -size_word flag when generating the firmware file?");
$finish;
end
end
`ifdef INITIALIZE_MEMORY_MODEL
// Initialize memory with firmware
initialize = 0;
while ( initialize < firmware_size ) begin
minsoc_top_0.onchip_ram_top.block_ram_3.mem[initialize/4] = program_mem[initialize];
minsoc_top_0.onchip_ram_top.block_ram_2.mem[initialize/4] = program_mem[initialize+1];
minsoc_top_0.onchip_ram_top.block_ram_1.mem[initialize/4] = program_mem[initialize+2];
minsoc_top_0.onchip_ram_top.block_ram_0.mem[initialize/4] = program_mem[initialize+3];
initialize = initialize + 4;
end
$display("Memory model initialized with firmware:");
$display("%s", file_name);
$display("%d Bytes loaded from %d ...", initialize , firmware_size);
`endif
// Reset controller
repeat (2) @ (negedge clock);
reset = RESET_LEVEL;
repeat (16) @ (negedge clock);
reset = ~RESET_LEVEL;
`ifdef START_UP
// Pass firmware over spi to or1k_startup
ptr = 0;
//read dummy
send_spi(program_mem[ptr]);
send_spi(program_mem[ptr]);
send_spi(program_mem[ptr]);
send_spi(program_mem[ptr]);
//~read dummy
while ( ptr < firmware_size ) begin
send_spi(program_mem[ptr]);
ptr = ptr + 1;
end
$display("Memory start-up completed...");
$display("Loaded firmware:");
$display("%s", file_name);
`endif
//
// Testbench START
//
design_ready = 1'b1;
$display("Running simulation: if you want to stop it, type ctrl+c and type in finish afterwards.");
fork
begin
`ifdef UART
`ifdef ETHERNET
`ifdef TEST_ETHERNET
$display("Testing Ethernet firmware, this takes long (~15 min. @ 2.53 GHz dual-core)...");
$display("Ethernet firmware encloses UART firmware, testing UART firmware first...");
test_uart();
test_eth();
$display("Stopping simulation.");
$finish;
`endif
`endif
`ifdef TEST_UART
$display("Testing UART firmware, this takes a while (~1 min. @ 2.53 GHz dual-core)...");
test_uart();
$display("Stopping simulation.");
$finish;
`endif
`endif
end
begin
`ifdef ETHERNET
`ifdef TEST_ETHERNET
get_mac();
if ( { eth_rx_data[ETH_HDR] , eth_rx_data[ETH_HDR+1] , eth_rx_data[ETH_HDR+2] , eth_rx_data[ETH_HDR+3] } == 32'hFF2B4050 )
$display("Ethernet firmware started correctly.");
`endif
`endif
end
join
end
//
// Modules instantiations
//
minsoc_top minsoc_top_0(
.clk(clock),
.reset(reset)
//JTAG ports
`ifdef GENERIC_TAP
, .jtag_tdi(dbg_tdi_i),
.jtag_tms(dbg_tms_i),
.jtag_tck(dbg_tck_i),
.jtag_tdo(dbg_tdo_o),
.jtag_vref(jtag_vref),
.jtag_gnd(jtag_gnd)
`endif
//SPI ports
`ifdef START_UP
, .spi_flash_mosi(spi_mosi),
.spi_flash_miso(spi_miso),
.spi_flash_sclk(spi_sclk),
.spi_flash_ss(spi_ss)
`endif
//UART ports
`ifdef UART
, .uart_stx(uart_stx),
.uart_srx(uart_srx)
`endif // !UART
// Ethernet ports
`ifdef ETHERNET
, .eth_col(eth_col),
.eth_crs(eth_crs),
.eth_trste(eth_trst),
.eth_tx_clk(eth_tx_clk),
.eth_tx_en(eth_tx_en),
.eth_tx_er(eth_tx_er),
.eth_txd(eth_txd),
.eth_rx_clk(eth_rx_clk),
.eth_rx_dv(eth_rx_dv),
.eth_rx_er(eth_rx_er),
.eth_rxd(eth_rxd),
.eth_fds_mdint(eth_fds_mdint),
.eth_mdc(eth_mdc),
.eth_mdio(eth_mdio)
`endif // !ETHERNET
);
`ifdef VPI_DEBUG
dbg_comm_vpi dbg_if(
.SYS_CLK(clock),
.P_TMS(dbg_tms_i),
.P_TCK(dbg_tck_i),
.P_TRST(),
.P_TDI(dbg_tdi_i),
.P_TDO(dbg_tdo_o)
);
`else
assign dbg_tdi_i = 1;
assign dbg_tck_i = 0;
assign dbg_tms_i = 1;
`endif
//
// Firmware testers
//
`ifdef UART
task test_uart();
begin
@ (posedge new_line);
$display("UART data received.");
hello = line[12*8-1:0];
//sending character A to UART, B expected
$display("Testing UART interrupt...");
uart_echo = 1'b0;
uart_send(8'h41); //Character A
@ (posedge new_char);
if ( line[7:0] == "B" )
$display("UART interrupt working.");
else
$display("UART interrupt failed. B was expected, %c was received.", line[7:0]);
uart_echo = 1'b1;
if ( hello == "Hello World." )
$display("UART firmware test completed, behaving correctly.");
else
$display("UART firmware test completed, failed.");
end
endtask
`endif
`ifdef ETHERNET
task test_eth();
begin
eth_tx_data[ETH_HDR+0] = 8'hBA;
eth_tx_data[ETH_HDR+1] = 8'h87;
eth_tx_data[ETH_HDR+2] = 8'hAA;
eth_tx_data[ETH_HDR+3] = 8'hBB;
eth_tx_data[ETH_HDR+4] = 8'hCC;
eth_tx_data[ETH_HDR+5] = 8'hDD;
$display("Sending an Ethernet package to the system and waiting for the data to be output through UART...");
send_mac(6);
repeat(3+40) @ (posedge new_line);
$display("Ethernet test completed.");
end
endtask
`endif
//
// Regular clocking and output
//
always begin
#((`CLK_PERIOD)/2) clock <= ~clock;
end
`ifdef WAVEFORM_OUTPUT
initial begin
$dumpfile("../results/minsoc_wave.lxt2");
$dumpvars();
end
`endif
//
// Functionalities tasks: SPI Startup and UART Monitor
//
//SPI START_UP
`ifdef START_UP
task send_spi;
input [7:0] data_in;
integer i;
begin
i = 7;
for ( i = 7 ; i >= 0; i = i - 1 ) begin
spi_miso = data_in[i];
@ (posedge spi_sclk);
end
end
endtask
`endif
//~SPI START_UP
//UART
`ifdef UART
localparam UART_TX_WAIT = (`FREQ_NUM_FOR_NS / `UART_BAUDRATE);
task uart_send;
input [7:0] data;
integer i;
begin
uart_srx = 1'b0;
#UART_TX_WAIT;
for ( i = 0; i < 8 ; i = i + 1 ) begin
uart_srx = data[i];
#UART_TX_WAIT;
end
uart_srx = 1'b0;
#UART_TX_WAIT;
uart_srx = 1'b1;
end
endtask
//UART Monitor (prints uart output on the terminal)
// Something to trigger the task
initial
begin
new_line = 1'b0;
new_char = 1'b0;
flush_line = 1'b0;
end
always @ (posedge clock)
if ( design_ready )
uart_decoder;
task uart_decoder;
integer i;
reg [7:0] tx_byte;
begin
new_char = 1'b0;
new_line = 1'b0;
// Wait for start bit
while (uart_stx == 1'b1)
@(uart_stx);
#(UART_TX_WAIT + (UART_TX_WAIT/2));
for ( i = 0; i < 8 ; i = i + 1 ) begin
tx_byte[i] = uart_stx;
#UART_TX_WAIT;
end
//Check for stop bit
if (uart_stx == 1'b0) begin
//$display("* WARNING: user stop bit not received when expected at time %d__", $time);
// Wait for return to idle
while (uart_stx == 1'b0)
@(uart_stx);
//$display("* USER UART returned to idle at time %d",$time);
end
// display the char
if ( uart_echo )
$write("%c", tx_byte);
if ( flush_line ) begin
line = "";
flush_line = 1'b0;
end
if ( tx_byte == "\n" ) begin
new_line = 1'b1;
flush_line = 1'b1;
end
else begin
line = { line[39*8-1:0], tx_byte};
new_char = 1'b1;
end
end
endtask
//~UART Monitor
`endif // !UART
//~UART
//
// TASKS to communicate with interfaces
//
//MAC_DATA
//
`ifdef ETHERNET
reg [31:0] crc32_result;
task get_mac;
integer conta;
reg LSB;
begin
conta = 0;
LSB = 1;
@ ( posedge eth_tx_en);
repeat (16) @ (negedge eth_tx_clk); //8 bytes, preamble (7 bytes) + start of frame (1 byte)
while ( eth_tx_en == 1'b1 ) begin
@ (negedge eth_tx_clk) begin
if ( LSB == 1'b1 )
eth_rx_data[conta][3:0] = eth_txd;
else begin
eth_rx_data[conta][7:4] = eth_txd;
conta = conta + 1;
end
LSB = ~LSB;
end
end
end
endtask
task send_mac; //only able to send up to 1536 bytes with header (14 bytes) and CRC (4 bytes)
input [31:0] length; //ETH_PAYLOAD_MAX_LENGTH 1518
integer conta;
begin
if ( length <= ETH_PAYLOAD_MAX_LENGTH ) begin
//DEST MAC
eth_tx_data[0] = 8'h55;
eth_tx_data[1] = 8'h47;
eth_tx_data[2] = 8'h34;
eth_tx_data[3] = 8'h22;
eth_tx_data[4] = 8'h88;
eth_tx_data[5] = 8'h92;
//SOURCE MAC
eth_tx_data[6] = 8'h3D;
eth_tx_data[7] = 8'h4F;
eth_tx_data[8] = 8'h1A;
eth_tx_data[9] = 8'hBE;
eth_tx_data[10] = 8'h68;
eth_tx_data[11] = 8'h72;
//LEN
eth_tx_data[12] = length[7:4];
eth_tx_data[13] = length[3:0];
//DATA input by task caller
//PAD
for ( conta = length+14; conta < 60; conta = conta + 1 ) begin
eth_tx_data[conta] = 8'h00;
end
gencrc32(conta);
eth_tx_data[conta] = crc32_result[31:24];
eth_tx_data[conta+1] = crc32_result[23:16];
eth_tx_data[conta+2] = crc32_result[15:8];
eth_tx_data[conta+3] = crc32_result[7:0];
send_rx_packet( 64'h0055_5555_5555_5555, 4'h7, 8'hD5, 32'h0000_0000, conta+4, 1'b0 );
end
else
$display("Warning: Ethernet packet is to big to be sent.");
end
endtask
task send_rx_packet;
input [(8*8)-1:0] preamble_data; // preamble data to be sent - correct is 64'h0055_5555_5555_5555
input [3:0] preamble_len; // length of preamble in bytes - max is 4'h8, correct is 4'h7
input [7:0] sfd_data; // SFD data to be sent - correct is 8'hD5
input [31:0] start_addr; // start address
input [31:0] len; // length of frame in Bytes (without preamble and SFD)
input plus_drible_nibble; // if length is longer for one nibble
integer rx_cnt;
reg [31:0] eth_tx_data_addr_in; // address for reading from RX memory
reg [7:0] eth_tx_data_data_out; // data for reading from RX memory
begin
@(posedge eth_rx_clk);
eth_rx_dv = 1;
// set initial rx memory address
eth_tx_data_addr_in = start_addr;
// send preamble
for (rx_cnt = 0; (rx_cnt < (preamble_len << 1)) && (rx_cnt < 16); rx_cnt = rx_cnt + 1)
begin
eth_rxd = preamble_data[3:0];
preamble_data = preamble_data >> 4;
@(posedge eth_rx_clk);
end
// send SFD
for (rx_cnt = 0; rx_cnt < 2; rx_cnt = rx_cnt + 1)
begin
eth_rxd = sfd_data[3:0];
sfd_data = sfd_data >> 4;
@(posedge eth_rx_clk);
end
// send packet's addresses, type/length, data and FCS
for (rx_cnt = 0; rx_cnt < len; rx_cnt = rx_cnt + 1)
begin
eth_tx_data_data_out = eth_tx_data[eth_tx_data_addr_in[21:0]];
eth_rxd = eth_tx_data_data_out[3:0];
@(posedge eth_rx_clk);
eth_rxd = eth_tx_data_data_out[7:4];
eth_tx_data_addr_in = eth_tx_data_addr_in + 1;
@(posedge eth_rx_clk);
end
if (plus_drible_nibble)
begin
eth_tx_data_data_out = eth_tx_data[eth_tx_data_addr_in[21:0]];
eth_rxd = eth_tx_data_data_out[3:0];
@(posedge eth_rx_clk);
end
eth_rx_dv = 0;
@(posedge eth_rx_clk);
end
endtask // send_rx_packet
//CRC32
localparam [31:0] CRC32_POLY = 32'h04C11DB7;
task gencrc32;
input [31:0] crc32_length;
integer byte, bit;
reg msb;
reg [7:0] current_byte;
reg [31:0] temp;
begin
crc32_result = 32'hffffffff;
for (byte = 0; byte < crc32_length; byte = byte + 1) begin
current_byte = eth_tx_data[byte];
for (bit = 0; bit < 8; bit = bit + 1) begin
msb = crc32_result[31];
crc32_result = crc32_result << 1;
if (msb != current_byte[bit]) begin
crc32_result = crc32_result ^ CRC32_POLY;
crc32_result[0] = 1;
end
end
end
// Last step is to "mirror" every bit, swap the 4 bytes, and then complement each bit.
//
// Mirror:
for (bit = 0; bit < 32; bit = bit + 1)
temp[31-bit] = crc32_result[bit];
// Swap and Complement:
crc32_result = ~{temp[7:0], temp[15:8], temp[23:16], temp[31:24]};
end
endtask
//~CRC32
`endif // !ETHERNET
//~MAC_DATA
//Generate tx and rx clocks
always begin
#((`ETH_PHY_PERIOD)/2) eth_tx_clk <= ~eth_tx_clk;
end
always begin
#((`ETH_PHY_PERIOD)/2) eth_rx_clk <= ~eth_rx_clk;
end
//~Generate tx and rx clocks
//
// TASK to initialize instantiated FPGA dual and two port memory to 0
//
task init_fpga_memory;
integer i;
begin
`ifdef OR1200_RFRAM_TWOPORT
`ifdef OR1200_XILINX_RAMB4
for ( i = 0; i < (1<<8); i = i + 1 ) begin
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.ramb4_s16_s16_0.mem[i] = 16'h0000;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.ramb4_s16_s16_1.mem[i] = 16'h0000;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.ramb4_s16_s16_0.mem[i] = 16'h0000;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.ramb4_s16_s16_1.mem[i] = 16'h0000;
end
`elsif OR1200_XILINX_RAMB16
for ( i = 0; i < (1<<9); i = i + 1 ) begin
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.ramb16_s36_s36.mem[i] = 32'h0000_0000;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.ramb16_s36_s36.mem[i] = 32'h0000_0000;
end
`elsif OR1200_ALTERA_LPM
`ifndef OR1200_ALTERA_LPM_XXX
$display("Definition OR1200_ALTERA_LPM in or1200_defines.v does not enable ALTERA memory for neither DUAL nor TWO port RFRAM");
$display("It uses GENERIC memory instead.");
$display("Add '`define OR1200_ALTERA_LPM_XXX' under '`define OR1200_ALTERA_LPM' on or1200_defines.v to use ALTERA memory.");
`endif
`ifdef OR1200_ALTERA_LPM_XXX
$display("...Using ALTERA memory for TWOPORT RFRAM!");
for ( i = 0; i < (1<<5); i = i + 1 ) begin
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.altqpram_component.mem[i] = 32'h0000_0000;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.altqpram_component.mem[i] = 32'h0000_0000;
end
`else
$display("...Using GENERIC memory!");
for ( i = 0; i < (1<<5); i = i + 1 ) begin
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.mem[i] = 32'h0000_0000;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.mem[i] = 32'h0000_0000;
end
`endif
`elsif OR1200_XILINX_RAM32X1D
$display("Definition OR1200_XILINX_RAM32X1D in or1200_defines.v does not enable FPGA memory for TWO port RFRAM");
$display("It uses GENERIC memory instead.");
$display("FPGA memory can be used if you choose OR1200_RFRAM_DUALPORT");
for ( i = 0; i < (1<<5); i = i + 1 ) begin
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.mem[i] = 32'h0000_0000;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.mem[i] = 32'h0000_0000;
end
`else
for ( i = 0; i < (1<<5); i = i + 1 ) begin
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.mem[i] = 32'h0000_0000;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.mem[i] = 32'h0000_0000;
end
`endif
`elsif OR1200_RFRAM_DUALPORT
`ifdef OR1200_XILINX_RAMB4
for ( i = 0; i < (1<<8); i = i + 1 ) begin
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.ramb4_s16_0.mem[i] = 16'h0000;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.ramb4_s16_1.mem[i] = 16'h0000;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.ramb4_s16_0.mem[i] = 16'h0000;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.ramb4_s16_1.mem[i] = 16'h0000;
end
`elsif OR1200_XILINX_RAMB16
for ( i = 0; i < (1<<9); i = i + 1 ) begin
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.ramb16_s36_s36.mem[i] = 32'h0000_0000;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.ramb16_s36_s36.mem[i] = 32'h0000_0000;
end
`elsif OR1200_ALTERA_LPM
`ifndef OR1200_ALTERA_LPM_XXX
$display("Definition OR1200_ALTERA_LPM in or1200_defines.v does not enable ALTERA memory for neither DUAL nor TWO port RFRAM");
$display("It uses GENERIC memory instead.");
$display("Add '`define OR1200_ALTERA_LPM_XXX' under '`define OR1200_ALTERA_LPM' on or1200_defines.v to use ALTERA memory.");
`endif
`ifdef OR1200_ALTERA_LPM_XXX
$display("...Using ALTERA memory for DUALPORT RFRAM!");
for ( i = 0; i < (1<<5); i = i + 1 ) begin
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.altqpram_component.mem[i] = 32'h0000_0000;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.altqpram_component.mem[i] = 32'h0000_0000;
end
`else
$display("...Using GENERIC memory!");
for ( i = 0; i < (1<<5); i = i + 1 ) begin
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.mem[i] = 32'h0000_0000;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.mem[i] = 32'h0000_0000;
end
`endif
`elsif OR1200_XILINX_RAM32X1D
`ifdef OR1200_USE_RAM16X1D_FOR_RAM32X1D
for ( i = 0; i < (1<<4); i = i + 1 ) begin
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_0.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_1.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_2.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_3.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_4.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_5.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_6.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_7.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_0.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_1.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_2.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_3.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_4.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_5.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_6.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_7.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_0.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_1.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_2.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_3.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_4.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_5.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_6.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_7.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_0.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_1.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_2.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_3.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_4.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_5.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_6.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_7.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_0.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_1.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_2.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_3.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_4.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_5.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_6.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_7.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_0.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_1.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_2.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_3.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_4.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_5.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_6.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_7.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_0.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_1.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_2.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_3.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_4.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_5.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_6.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_7.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_0.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_1.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_2.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_3.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_4.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_5.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_6.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_7.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_0.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_1.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_2.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_3.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_4.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_5.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_6.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_7.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_0.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_1.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_2.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_3.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_4.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_5.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_6.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_7.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_0.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_1.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_2.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_3.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_4.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_5.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_6.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_7.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_0.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_1.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_2.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_3.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_4.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_5.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_6.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_7.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_0.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_1.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_2.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_3.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_4.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_5.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_6.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_7.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_0.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_1.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_2.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_3.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_4.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_5.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_6.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_7.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_0.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_1.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_2.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_3.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_4.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_5.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_6.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_7.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_0.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_1.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_2.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_3.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_4.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_5.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_6.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_7.mem[i] = 1'b0;
end
`else
for ( i = 0; i < (1<<4); i = i + 1 ) begin
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_2.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_3.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_4.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_5.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_6.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_7.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_2.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_3.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_4.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_5.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_6.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_7.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_2.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_3.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_4.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_5.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_6.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_7.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_2.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_3.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_4.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_5.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_6.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_7.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_2.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_3.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_4.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_5.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_6.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_7.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_2.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_3.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_4.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_5.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_6.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_7.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_2.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_3.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_4.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_5.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_6.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_7.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_2.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_3.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_4.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_5.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_6.mem[i] = 1'b0;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_7.mem[i] = 1'b0;
end
`endif
`else
for ( i = 0; i < (1<<5); i = i + 1 ) begin
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.mem[i] = 32'h0000_0000;
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.mem[i] = 32'h0000_0000;
end
`endif
`endif
end
endtask
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
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//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : pcie_gtx_v6.v
// Version : 1.7
//-- Description: GTX module for Virtex6 PCIe Block
//--
//--
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module pcie_gtx_v6 #
(
parameter NO_OF_LANES = 8, // 1 - x1 , 2 - x2 , 4 - x4 , 8 - x8
parameter LINK_CAP_MAX_LINK_SPEED = 4'h1, // 1 - Gen1, 2 - Gen2
parameter REF_CLK_FREQ = 0, // 0 - 100 MHz , 1 - 125 MHz , 2 - 250 MHz
parameter PL_FAST_TRAIN = "FALSE"
)
(
// Pipe Per-Link Signals
input wire pipe_tx_rcvr_det ,
input wire pipe_tx_reset ,
input wire pipe_tx_rate ,
input wire pipe_tx_deemph ,
input wire [2:0] pipe_tx_margin ,
input wire pipe_tx_swing ,
// Pipe Per-Lane Signals - Lane 0
output wire [ 1:0] pipe_rx0_char_is_k ,
output wire [15:0] pipe_rx0_data ,
output wire pipe_rx0_valid ,
output wire pipe_rx0_chanisaligned ,
output wire [ 2:0] pipe_rx0_status ,
output wire pipe_rx0_phy_status ,
output wire pipe_rx0_elec_idle ,
input wire pipe_rx0_polarity ,
input wire pipe_tx0_compliance ,
input wire [ 1:0] pipe_tx0_char_is_k ,
input wire [15:0] pipe_tx0_data ,
input wire pipe_tx0_elec_idle ,
input wire [ 1:0] pipe_tx0_powerdown ,
// Pipe Per-Lane Signals - Lane 1
output wire [ 1:0] pipe_rx1_char_is_k ,
output wire [15:0] pipe_rx1_data ,
output wire pipe_rx1_valid ,
output wire pipe_rx1_chanisaligned ,
output wire [ 2:0] pipe_rx1_status ,
output wire pipe_rx1_phy_status ,
output wire pipe_rx1_elec_idle ,
input wire pipe_rx1_polarity ,
input wire pipe_tx1_compliance ,
input wire [ 1:0] pipe_tx1_char_is_k ,
input wire [15:0] pipe_tx1_data ,
input wire pipe_tx1_elec_idle ,
input wire [ 1:0] pipe_tx1_powerdown ,
// Pipe Per-Lane Signals - Lane 2
output wire [ 1:0] pipe_rx2_char_is_k ,
output wire [15:0] pipe_rx2_data ,
output wire pipe_rx2_valid ,
output wire pipe_rx2_chanisaligned ,
output wire [ 2:0] pipe_rx2_status ,
output wire pipe_rx2_phy_status ,
output wire pipe_rx2_elec_idle ,
input wire pipe_rx2_polarity ,
input wire pipe_tx2_compliance ,
input wire [ 1:0] pipe_tx2_char_is_k ,
input wire [15:0] pipe_tx2_data ,
input wire pipe_tx2_elec_idle ,
input wire [ 1:0] pipe_tx2_powerdown ,
// Pipe Per-Lane Signals - Lane 3
output wire [ 1:0] pipe_rx3_char_is_k ,
output wire [15:0] pipe_rx3_data ,
output wire pipe_rx3_valid ,
output wire pipe_rx3_chanisaligned ,
output wire [ 2:0] pipe_rx3_status ,
output wire pipe_rx3_phy_status ,
output wire pipe_rx3_elec_idle ,
input wire pipe_rx3_polarity ,
input wire pipe_tx3_compliance ,
input wire [ 1:0] pipe_tx3_char_is_k ,
input wire [15:0] pipe_tx3_data ,
input wire pipe_tx3_elec_idle ,
input wire [ 1:0] pipe_tx3_powerdown ,
// Pipe Per-Lane Signals - Lane 4
output wire [ 1:0] pipe_rx4_char_is_k ,
output wire [15:0] pipe_rx4_data ,
output wire pipe_rx4_valid ,
output wire pipe_rx4_chanisaligned ,
output wire [ 2:0] pipe_rx4_status ,
output wire pipe_rx4_phy_status ,
output wire pipe_rx4_elec_idle ,
input wire pipe_rx4_polarity ,
input wire pipe_tx4_compliance ,
input wire [ 1:0] pipe_tx4_char_is_k ,
input wire [15:0] pipe_tx4_data ,
input wire pipe_tx4_elec_idle ,
input wire [ 1:0] pipe_tx4_powerdown ,
// Pipe Per-Lane Signals - Lane 5
output wire [ 1:0] pipe_rx5_char_is_k ,
output wire [15:0] pipe_rx5_data ,
output wire pipe_rx5_valid ,
output wire pipe_rx5_chanisaligned ,
output wire [ 2:0] pipe_rx5_status ,
output wire pipe_rx5_phy_status ,
output wire pipe_rx5_elec_idle ,
input wire pipe_rx5_polarity ,
input wire pipe_tx5_compliance ,
input wire [ 1:0] pipe_tx5_char_is_k ,
input wire [15:0] pipe_tx5_data ,
input wire pipe_tx5_elec_idle ,
input wire [ 1:0] pipe_tx5_powerdown ,
// Pipe Per-Lane Signals - Lane 6
output wire [ 1:0] pipe_rx6_char_is_k ,
output wire [15:0] pipe_rx6_data ,
output wire pipe_rx6_valid ,
output wire pipe_rx6_chanisaligned ,
output wire [ 2:0] pipe_rx6_status ,
output wire pipe_rx6_phy_status ,
output wire pipe_rx6_elec_idle ,
input wire pipe_rx6_polarity ,
input wire pipe_tx6_compliance ,
input wire [ 1:0] pipe_tx6_char_is_k ,
input wire [15:0] pipe_tx6_data ,
input wire pipe_tx6_elec_idle ,
input wire [ 1:0] pipe_tx6_powerdown ,
// Pipe Per-Lane Signals - Lane 7
output wire [ 1:0] pipe_rx7_char_is_k ,
output wire [15:0] pipe_rx7_data ,
output wire pipe_rx7_valid ,
output wire pipe_rx7_chanisaligned ,
output wire [ 2:0] pipe_rx7_status ,
output wire pipe_rx7_phy_status ,
output wire pipe_rx7_elec_idle ,
input wire pipe_rx7_polarity ,
input wire pipe_tx7_compliance ,
input wire [ 1:0] pipe_tx7_char_is_k ,
input wire [15:0] pipe_tx7_data ,
input wire pipe_tx7_elec_idle ,
input wire [ 1:0] pipe_tx7_powerdown ,
// PCI Express signals
output wire [ (NO_OF_LANES-1):0] pci_exp_txn ,
output wire [ (NO_OF_LANES-1):0] pci_exp_txp ,
input wire [ (NO_OF_LANES-1):0] pci_exp_rxn ,
input wire [ (NO_OF_LANES-1):0] pci_exp_rxp ,
// Non PIPE signals
input wire sys_clk ,
input wire sys_rst_n ,
input wire pipe_clk ,
input wire drp_clk ,
input wire clock_locked ,
output wire gt_pll_lock ,
input wire [ 5:0] pl_ltssm_state ,
output reg phy_rdy_n ,
output wire TxOutClk
);
parameter TCQ = 1; // clock to out delay model
wire [ 7:0] gt_rx_phy_status_wire ;
wire [ 7:0] gt_rxchanisaligned_wire ;
wire [127:0] gt_rx_data_k_wire ;
wire [127:0] gt_rx_data_wire ;
wire [ 7:0] gt_rx_elec_idle_wire ;
wire [ 23:0] gt_rx_status_wire ;
wire [ 7:0] gt_rx_valid_wire ;
wire [ 7:0] gt_rx_polarity ;
wire [ 15:0] gt_power_down ;
wire [ 7:0] gt_tx_char_disp_mode ;
wire [ 15:0] gt_tx_data_k ;
wire [127:0] gt_tx_data ;
wire gt_tx_detect_rx_loopback ;
wire [ 7:0] gt_tx_elec_idle ;
wire [ 7:0] gt_rx_elec_idle_reset ;
wire [NO_OF_LANES-1:0] plllkdet;
wire RxResetDone;
reg local_pcs_reset;
reg local_pcs_reset_done;
reg [3:0] cnt_local_pcs_reset;
reg [4:0] phy_rdy_pre_cnt;
reg [5:0] pl_ltssm_state_q;
wire plm_in_l0 = (pl_ltssm_state_q == 6'h16);
wire plm_in_rl = (pl_ltssm_state_q == 6'h1c);
wire plm_in_dt = (pl_ltssm_state_q == 6'h2d);
wire plm_in_rs = (pl_ltssm_state_q == 6'h1f);
gtx_wrapper_v6 #(
.NO_OF_LANES(NO_OF_LANES),
.REF_CLK_FREQ(REF_CLK_FREQ),
.PL_FAST_TRAIN(PL_FAST_TRAIN)
)
gtx_v6_i (
// TX
.TX(pci_exp_txp[((NO_OF_LANES)-1):0]),
.TX_(pci_exp_txn[((NO_OF_LANES)-1):0]),
.TxData(gt_tx_data[((16*NO_OF_LANES)-1):0]),
.TxDataK(gt_tx_data_k[((2*NO_OF_LANES)-1):0]),
.TxElecIdle(gt_tx_elec_idle[((NO_OF_LANES)-1):0]),
.TxCompliance(gt_tx_char_disp_mode[((NO_OF_LANES)-1):0]),
// RX
.RX(pci_exp_rxp[((NO_OF_LANES)-1):0]),
.RX_(pci_exp_rxn[((NO_OF_LANES)-1):0]),
.RxData(gt_rx_data_wire[((16*NO_OF_LANES)-1):0]),
.RxDataK(gt_rx_data_k_wire[((2*NO_OF_LANES)-1):0]),
.RxPolarity(gt_rx_polarity[((NO_OF_LANES)-1):0]),
.RxValid(gt_rx_valid_wire[((NO_OF_LANES)-1):0]),
.RxElecIdle(gt_rx_elec_idle_wire[((NO_OF_LANES)-1):0]),
.RxStatus(gt_rx_status_wire[((3*NO_OF_LANES)-1):0]),
// other
.GTRefClkout(),
.plm_in_l0(plm_in_l0),
.plm_in_rl(plm_in_rl),
.plm_in_dt(plm_in_dt),
.plm_in_rs(plm_in_rs),
.RxPLLLkDet(plllkdet),
.ChanIsAligned(gt_rxchanisaligned_wire[((NO_OF_LANES)-1):0]),
.TxDetectRx(gt_tx_detect_rx_loopback),
.PhyStatus(gt_rx_phy_status_wire[((NO_OF_LANES)-1):0]),
.TXPdownAsynch(~clock_locked),
.PowerDown(gt_power_down[((2*NO_OF_LANES)-1):0]),
.Rate(pipe_tx_rate),
.Reset_n(clock_locked),
.GTReset_n(sys_rst_n),
.PCLK(pipe_clk),
.REFCLK(sys_clk),
.DRPCLK(drp_clk),
.TxDeemph(pipe_tx_deemph),
.TxMargin(pipe_tx_margin[2]),
.TxSwing(pipe_tx_swing),
.local_pcs_reset(local_pcs_reset),
.RxResetDone(RxResetDone),
.SyncDone(SyncDone),
.TxOutClk(TxOutClk)
);
assign pipe_rx0_phy_status = gt_rx_phy_status_wire[0] ;
assign pipe_rx1_phy_status = (NO_OF_LANES >= 2 ) ? gt_rx_phy_status_wire[1] : 1'b0;
assign pipe_rx2_phy_status = (NO_OF_LANES >= 4 ) ? gt_rx_phy_status_wire[2] : 1'b0;
assign pipe_rx3_phy_status = (NO_OF_LANES >= 4 ) ? gt_rx_phy_status_wire[3] : 1'b0;
assign pipe_rx4_phy_status = (NO_OF_LANES >= 8 ) ? gt_rx_phy_status_wire[4] : 1'b0;
assign pipe_rx5_phy_status = (NO_OF_LANES >= 8 ) ? gt_rx_phy_status_wire[5] : 1'b0;
assign pipe_rx6_phy_status = (NO_OF_LANES >= 8 ) ? gt_rx_phy_status_wire[6] : 1'b0;
assign pipe_rx7_phy_status = (NO_OF_LANES >= 8 ) ? gt_rx_phy_status_wire[7] : 1'b0;
assign pipe_rx0_chanisaligned = gt_rxchanisaligned_wire[0];
assign pipe_rx1_chanisaligned = (NO_OF_LANES >= 2 ) ? gt_rxchanisaligned_wire[1] : 1'b0 ;
assign pipe_rx2_chanisaligned = (NO_OF_LANES >= 4 ) ? gt_rxchanisaligned_wire[2] : 1'b0 ;
assign pipe_rx3_chanisaligned = (NO_OF_LANES >= 4 ) ? gt_rxchanisaligned_wire[3] : 1'b0 ;
assign pipe_rx4_chanisaligned = (NO_OF_LANES >= 8 ) ? gt_rxchanisaligned_wire[4] : 1'b0 ;
assign pipe_rx5_chanisaligned = (NO_OF_LANES >= 8 ) ? gt_rxchanisaligned_wire[5] : 1'b0 ;
assign pipe_rx6_chanisaligned = (NO_OF_LANES >= 8 ) ? gt_rxchanisaligned_wire[6] : 1'b0 ;
assign pipe_rx7_chanisaligned = (NO_OF_LANES >= 8 ) ? gt_rxchanisaligned_wire[7] : 1'b0 ;
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
assign pipe_rx0_char_is_k = {gt_rx_data_k_wire[1], gt_rx_data_k_wire[0]};
assign pipe_rx1_char_is_k = (NO_OF_LANES >= 2 ) ? {gt_rx_data_k_wire[3], gt_rx_data_k_wire[2]} : 2'b0 ;
assign pipe_rx2_char_is_k = (NO_OF_LANES >= 4 ) ? {gt_rx_data_k_wire[5], gt_rx_data_k_wire[4]} : 2'b0 ;
assign pipe_rx3_char_is_k = (NO_OF_LANES >= 4 ) ? {gt_rx_data_k_wire[7], gt_rx_data_k_wire[6]} : 2'b0 ;
assign pipe_rx4_char_is_k = (NO_OF_LANES >= 8 ) ? {gt_rx_data_k_wire[9], gt_rx_data_k_wire[8]} : 2'b0 ;
assign pipe_rx5_char_is_k = (NO_OF_LANES >= 8 ) ? {gt_rx_data_k_wire[11], gt_rx_data_k_wire[10]} : 2'b0 ;
assign pipe_rx6_char_is_k = (NO_OF_LANES >= 8 ) ? {gt_rx_data_k_wire[13], gt_rx_data_k_wire[12]} : 2'b0 ;
assign pipe_rx7_char_is_k = (NO_OF_LANES >= 8 ) ? {gt_rx_data_k_wire[15], gt_rx_data_k_wire[14]} : 2'b0 ;
assign pipe_rx0_data = {gt_rx_data_wire[ 15: 8], gt_rx_data_wire[ 7: 0]};
assign pipe_rx1_data = (NO_OF_LANES >= 2 ) ? {gt_rx_data_wire[31:24], gt_rx_data_wire[23:16]} : 16'h0 ;
assign pipe_rx2_data = (NO_OF_LANES >= 4 ) ? {gt_rx_data_wire[47:40], gt_rx_data_wire[39:32]} : 16'h0 ;
assign pipe_rx3_data = (NO_OF_LANES >= 4 ) ? {gt_rx_data_wire[63:56], gt_rx_data_wire[55:48]} : 16'h0 ;
assign pipe_rx4_data = (NO_OF_LANES >= 8 ) ? {gt_rx_data_wire[79:72], gt_rx_data_wire[71:64]} : 16'h0 ;
assign pipe_rx5_data = (NO_OF_LANES >= 8 ) ? {gt_rx_data_wire[95:88], gt_rx_data_wire[87:80]} : 16'h0 ;
assign pipe_rx6_data = (NO_OF_LANES >= 8 ) ? {gt_rx_data_wire[111:104], gt_rx_data_wire[103:96]} : 16'h0 ;
assign pipe_rx7_data = (NO_OF_LANES >= 8 ) ? {gt_rx_data_wire[127:120], gt_rx_data_wire[119:112]} : 16'h0 ;
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
assign pipe_rx0_elec_idle = gt_rx_elec_idle_wire[0];
assign pipe_rx1_elec_idle = (NO_OF_LANES >= 2 ) ? gt_rx_elec_idle_wire[1] : 1'b1 ;
assign pipe_rx2_elec_idle = (NO_OF_LANES >= 4 ) ? gt_rx_elec_idle_wire[2] : 1'b1 ;
assign pipe_rx3_elec_idle = (NO_OF_LANES >= 4 ) ? gt_rx_elec_idle_wire[3] : 1'b1 ;
assign pipe_rx4_elec_idle = (NO_OF_LANES >= 8 ) ? gt_rx_elec_idle_wire[4] : 1'b1 ;
assign pipe_rx5_elec_idle = (NO_OF_LANES >= 8 ) ? gt_rx_elec_idle_wire[5] : 1'b1 ;
assign pipe_rx6_elec_idle = (NO_OF_LANES >= 8 ) ? gt_rx_elec_idle_wire[6] : 1'b1 ;
assign pipe_rx7_elec_idle = (NO_OF_LANES >= 8 ) ? gt_rx_elec_idle_wire[7] : 1'b1 ;
assign pipe_rx0_status = gt_rx_status_wire[ 2: 0];
assign pipe_rx1_status = (NO_OF_LANES >= 2 ) ? gt_rx_status_wire[ 5: 3] : 3'b0 ;
assign pipe_rx2_status = (NO_OF_LANES >= 4 ) ? gt_rx_status_wire[ 8: 6] : 3'b0 ;
assign pipe_rx3_status = (NO_OF_LANES >= 4 ) ? gt_rx_status_wire[11: 9] : 3'b0 ;
assign pipe_rx4_status = (NO_OF_LANES >= 8 ) ? gt_rx_status_wire[14:12] : 3'b0 ;
assign pipe_rx5_status = (NO_OF_LANES >= 8 ) ? gt_rx_status_wire[17:15] : 3'b0 ;
assign pipe_rx6_status = (NO_OF_LANES >= 8 ) ? gt_rx_status_wire[20:18] : 3'b0 ;
assign pipe_rx7_status = (NO_OF_LANES >= 8 ) ? gt_rx_status_wire[23:21] : 3'b0 ;
assign pipe_rx0_valid = gt_rx_valid_wire[0];
assign pipe_rx1_valid = (NO_OF_LANES >= 2 ) ? gt_rx_valid_wire[1] : 1'b0 ;
assign pipe_rx2_valid = (NO_OF_LANES >= 4 ) ? gt_rx_valid_wire[2] : 1'b0 ;
assign pipe_rx3_valid = (NO_OF_LANES >= 4 ) ? gt_rx_valid_wire[3] : 1'b0 ;
assign pipe_rx4_valid = (NO_OF_LANES >= 8 ) ? gt_rx_valid_wire[4] : 1'b0 ;
assign pipe_rx5_valid = (NO_OF_LANES >= 8 ) ? gt_rx_valid_wire[5] : 1'b0 ;
assign pipe_rx6_valid = (NO_OF_LANES >= 8 ) ? gt_rx_valid_wire[6] : 1'b0 ;
assign pipe_rx7_valid = (NO_OF_LANES >= 8 ) ? gt_rx_valid_wire[7] : 1'b0 ;
assign gt_rx_polarity[0] = pipe_rx0_polarity;
assign gt_rx_polarity[1] = pipe_rx1_polarity;
assign gt_rx_polarity[2] = pipe_rx2_polarity;
assign gt_rx_polarity[3] = pipe_rx3_polarity;
assign gt_rx_polarity[4] = pipe_rx4_polarity;
assign gt_rx_polarity[5] = pipe_rx5_polarity;
assign gt_rx_polarity[6] = pipe_rx6_polarity;
assign gt_rx_polarity[7] = pipe_rx7_polarity;
assign gt_power_down[ 1: 0] = pipe_tx0_powerdown;
assign gt_power_down[ 3: 2] = pipe_tx1_powerdown;
assign gt_power_down[ 5: 4] = pipe_tx2_powerdown;
assign gt_power_down[ 7: 6] = pipe_tx3_powerdown;
assign gt_power_down[ 9: 8] = pipe_tx4_powerdown;
assign gt_power_down[11:10] = pipe_tx5_powerdown;
assign gt_power_down[13:12] = pipe_tx6_powerdown;
assign gt_power_down[15:14] = pipe_tx7_powerdown;
assign gt_tx_char_disp_mode = {pipe_tx7_compliance,
pipe_tx6_compliance,
pipe_tx5_compliance,
pipe_tx4_compliance,
pipe_tx3_compliance,
pipe_tx2_compliance,
pipe_tx1_compliance,
pipe_tx0_compliance};
assign gt_tx_data_k = {pipe_tx7_char_is_k,
pipe_tx6_char_is_k,
pipe_tx5_char_is_k,
pipe_tx4_char_is_k,
pipe_tx3_char_is_k,
pipe_tx2_char_is_k,
pipe_tx1_char_is_k,
pipe_tx0_char_is_k};
assign gt_tx_data = {pipe_tx7_data,
pipe_tx6_data,
pipe_tx5_data,
pipe_tx4_data,
pipe_tx3_data,
pipe_tx2_data,
pipe_tx1_data,
pipe_tx0_data};
assign gt_tx_detect_rx_loopback = pipe_tx_rcvr_det;
assign gt_tx_elec_idle = {pipe_tx7_elec_idle,
pipe_tx6_elec_idle,
pipe_tx5_elec_idle,
pipe_tx4_elec_idle,
pipe_tx3_elec_idle,
pipe_tx2_elec_idle,
pipe_tx1_elec_idle,
pipe_tx0_elec_idle};
assign gt_pll_lock = &plllkdet[NO_OF_LANES-1:0] | ~phy_rdy_pre_cnt[4];
// Asserted after all workarounds have completed.
always @(posedge pipe_clk or negedge clock_locked) begin
if (!clock_locked) begin
phy_rdy_n <= #TCQ 1'b1;
end else begin
if (~&plllkdet[NO_OF_LANES-1:0])
phy_rdy_n <= #TCQ 1'b1;
else if (local_pcs_reset_done && RxResetDone && phy_rdy_n && SyncDone)
phy_rdy_n <= #TCQ 1'b0;
end
end
// Handle the warm reset case, where sys_rst_n is asseted when
// phy_rdy_n is asserted. phy_rdy_n is to be de-asserted
// before gt_pll_lock is de-asserted so that synnchronous
// logic see reset de-asset before clock is lost.
always @(posedge pipe_clk or negedge clock_locked) begin
if (!clock_locked) begin
phy_rdy_pre_cnt <= #TCQ 5'b11111;
end else begin
if (gt_pll_lock && phy_rdy_n)
phy_rdy_pre_cnt <= #TCQ phy_rdy_pre_cnt + 1'b1;
end
end
always @(posedge pipe_clk or negedge clock_locked) begin
if (!clock_locked) begin
cnt_local_pcs_reset <= #TCQ 4'hF;
local_pcs_reset <= #TCQ 1'b0;
local_pcs_reset_done <= #TCQ 1'b0;
end else begin
if ((local_pcs_reset == 1'b0) && (cnt_local_pcs_reset == 4'hF))
local_pcs_reset <= #TCQ 1'b1;
else if ((local_pcs_reset == 1'b1) && (cnt_local_pcs_reset != 4'h0)) begin
local_pcs_reset <= #TCQ 1'b1;
cnt_local_pcs_reset <= #TCQ cnt_local_pcs_reset - 1'b1;
end else if ((local_pcs_reset == 1'b1) && (cnt_local_pcs_reset == 4'h0)) begin
local_pcs_reset <= #TCQ 1'b0;
local_pcs_reset_done <= #TCQ 1'b1;
end
end
end
always @(posedge pipe_clk or negedge clock_locked) begin
if (!clock_locked)
pl_ltssm_state_q <= #TCQ 6'b0;
else
pl_ltssm_state_q <= #TCQ pl_ltssm_state;
end
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
endmodule
|
/*
Copyright (C) {2014} {James Thomas} <[email protected]>
Copyright (C) {2014} {Ganesh Ajjanagadde} <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
///////////////////////////////////////////////////////////////////////////////////////////////////
// a simple module for mapping hcount and vcount to address in bram
// the math:
// bram is 320*240 = 76800 lines, 320 columns, and 240 rows
// each line of bram corresponds to one pixel
// currently, each line is 12 bits (4 pixels r, 4 pixels g, 4 pixels b)
// hcount and vcount are in the 640x480 space
// Thus, the desired address is: 320*(vcount/2) + (hcount/2)
// = (128 + 32)vcount + hcount/2
///////////////////////////////////////////////////////////////////////////////////////////////////
module addr_map(input[9:0] hcount,
input[9:0] vcount,
output[16:0] addr);
assign addr = (vcount[9:1] << 8) + (vcount[9:1] << 6) + (hcount >> 1);
endmodule
|
//wb_fpga_nes.v
/*
Distributed under the MIT license.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
Self Defining Bus (SDB)
Set the Vendor ID (Hexidecimal 64-bit Number)
SDB_VENDOR_ID:0x800000000000C594
Set the Device ID (Hexcidecimal 32-bit Number)
SDB_DEVICE_ID:0x0000000F
Set the version of the Core XX.XXX.XXX Example: 01.000.000
SDB_CORE_VERSION:00.000.001
Set the Device Name: (19 UNICODE characters)
SDB_NAME:wb_fpga_nes
Set the class of the device (16 bits) Set as 0
SDB_ABI_CLASS:0
Set the ABI Major Version: (8-bits)
SDB_ABI_VERSION_MAJOR:0x0F
Set the ABI Minor Version (8-bits)
SDB_ABI_VERSION_MINOR:0x02
Set the Module URL (63 Unicode Characters)
SDB_MODULE_URL:http://www.example.com
Set the date of module YYYY/MM/DD
SDB_DATE:2015/01/07
Device is executable (True/False)
SDB_EXECUTABLE:True
Device is readable (True/False)
SDB_READABLE:True
Device is writeable (True/False)
SDB_WRITEABLE:True
Device Size: Number of Registers
SDB_SIZE:15
*/
module wb_fpga_nes (
input clk,
input rst,
//Add signals to control your device here
//Wishbone Bus Signals
input i_wbs_we,
input i_wbs_cyc,
input [3:0] i_wbs_sel,
input [31:0] i_wbs_dat,
input i_wbs_stb,
output reg o_wbs_ack,
output reg [31:0] o_wbs_dat,
input [31:0] i_wbs_adr,
//master control signal for memory arbitration
output mem_o_we,
output mem_o_stb,
output mem_o_cyc,
output [3:0] mem_o_sel,
output [31:0] mem_o_adr,
output [31:0] mem_o_dat,
input [31:0] mem_i_dat,
input mem_i_ack,
input mem_i_int,
//This interrupt can be controlled from this module or a submodule
output reg o_wbs_int
//Nes Interface
);
//Local Parameters
localparam CONTROL = 32'h00000000;
localparam STATUS = 32'h00000001;
localparam USER_INPUT = 32'h00000002;
localparam HCI_OPCODE_COUNT = 32'h00000003;
localparam HCI_OPCODE_ADDR = 32'h00000004;
localparam HCI_OPCODE = 32'h00000005;
localparam HCI_OPCODE_DATA = 32'h00000006;
localparam DMA_STATUS = 32'h00000007;
localparam REG_MEM_0_BASE = 32'h00000008;
localparam REG_MEM_0_SIZE = 32'h00000009;
localparam REG_MEM_1_BASE = 32'h0000000A;
localparam REG_MEM_1_SIZE = 32'h0000000B;
localparam REG_IMAGE_WIDTH = 32'h0000000C;
localparam REG_IMAGE_HEIGHT = 32'h0000000D;
//Control
localparam CONTROL_HCI_RESET = 0;
localparam CONTROL_CONSOLE_RESET = 1;
localparam CONTROL_ENABLE_DMA = 2;
//Status
localparam STATUS_CLOCK_LOCKED = 0;
localparam STATUS_HCI_READY = 1;
localparam STATUS_HCI_NEW_STATUS = 2;
localparam STATUS_HCI_S_BOT = 16;
localparam STATUS_HCI_S_TOP = STATUS_HCI_S_BOT + 15;
//Local Registers/Wires
//wire clk_locked;
//wire nes_clk;
wire [31:0] status;
reg [31:0] control;
wire [3:0] dma_status;
//DMA Transfer Registers
wire w_enable_dma;
reg [31:0] r_memory_0_base;
reg [31:0] r_memory_0_size;
wire [31:0] w_memory_0_count;
reg r_memory_0_ready;
wire w_memory_0_finished;
wire w_memory_0_empty;
wire [31:0] w_default_mem_0_base;
reg [31:0] r_memory_1_base;
reg [31:0] r_memory_1_size;
wire [31:0] w_memory_1_count;
reg r_memory_1_ready;
wire w_memory_1_finished;
wire w_memory_1_empty;
wire [31:0] w_default_mem_1_base;
wire w_write_finished;
wire w_rfifo_ready;
wire w_rfifo_activate;
wire w_rfifo_strobe;
wire [31:0] w_rfifo_data;
wire [23:0] w_rfifo_size;
wire w_captured;
wire w_busy;
//NES Wires
wire w_console_reset;
//NES Controls
wire [3:0] w_mute_control;
reg [7:0] r_jp1_state; //State of joypad 1
reg [7:0] r_jp2_state; //State of joypad 2
//Audio
wire w_audio;
//Video Interface
wire [9:0] w_image_width;
wire [9:0] w_image_height;
wire w_hsync;
wire w_vsync;
wire [2:0] w_red;
wire [2:0] w_green;
wire [1:0] w_blue;
//HCI Interface
wire w_hci_reset;
reg [7:0] r_hci_opcode;
reg r_hci_opcode_strobe;
wire [15:0] w_hci_opcode_status;
reg [15:0] r_hci_opcode_status;
wire w_hci_opcode_ack;
reg r_hci_opcode_new_status;
reg [15:0] r_hci_address;
reg [31:0] r_hci_count;
reg r_hci_din_strobe;
wire w_hci_sm_ready;
reg [7:0] r_hci_din;
wire w_hci_dout_strobe;
reg r_hci_host_ready;
wire [7:0] w_hci_dout;
wire w_flush_memory;
wire w_memory_ready;
//Submodules
image_to_ppfifo proc (
.clk (clk ),
.rst (rst ),
.i_enable (w_enable_dma ),
.i_hsync (w_hsync ),
.i_vsync (w_vsync ),
.i_red (w_red ),
.i_green (w_green ),
.i_blue (w_blue ),
.o_frame_finished (w_flush_memory ),
.o_rfifo_ready (w_rfifo_ready ),
.i_rfifo_activate (w_rfifo_activate ),
.i_rfifo_strobe (w_rfifo_strobe ),
.o_rfifo_data (w_rfifo_data ),
.o_rfifo_size (w_rfifo_size )
);
wb_ppfifo_2_mem p2m(
.clk (clk ),
.rst (rst || !w_console_reset ),
//.debug (debug ),
//Control
.i_enable (w_enable_dma ),
.i_flush (w_flush_memory ),
.i_memory_0_base (r_memory_0_base ),
.i_memory_0_size (r_memory_0_size ),
.o_memory_0_count (w_memory_0_count ),
.i_memory_0_ready (r_memory_0_ready ),
.o_memory_0_finished (w_memory_0_finished ),
.o_memory_0_empty (w_memory_0_empty ),
.o_default_mem_0_base (w_default_mem_0_base ),
.i_memory_1_base (r_memory_1_base ),
.i_memory_1_size (r_memory_1_size ),
.o_memory_1_count (w_memory_1_count ),
.i_memory_1_ready (r_memory_1_ready ),
.o_memory_1_finished (w_memory_1_finished ),
.o_memory_1_empty (w_memory_1_empty ),
.o_default_mem_1_base (w_default_mem_1_base ),
.o_write_finished (w_write_finished ),
//master control signal for memory arbitration
.o_mem_we (mem_o_we ),
.o_mem_stb (mem_o_stb ),
.o_mem_cyc (mem_o_cyc ),
.o_mem_sel (mem_o_sel ),
.o_mem_adr (mem_o_adr ),
.o_mem_dat (mem_o_dat ),
.i_mem_dat (mem_i_dat ),
.i_mem_ack (mem_i_ack ),
.i_mem_int (mem_i_int ),
//Ping Pong FIFO Interface (Read)
.i_ppfifo_rdy (w_rfifo_ready ),
.o_ppfifo_act (w_rfifo_activate ),
.i_ppfifo_size (w_rfifo_size ),
.o_ppfifo_stb (w_rfifo_strobe ),
.i_ppfifo_data (w_rfifo_data )
);
/*
nes_clkgen clkgen (
.clk (clk ),
.rst (rst ),
.locked (clk_locked ),
//.phy_out_clk (phy_out_clk ),
.out_clk (nes_clk )
);
*/
nes_top nes(
// .clk (nes_clk ),
.clk (clk ),
.rst (rst ),
//.RXD (rxd ),
//.TXD (txd ),
.i_console_reset (w_console_reset ),
.i_mute_control (w_mute_control ),
.i_jp1_state (r_jp1_state ),
.i_jp2_state (r_jp2_state ),
.o_audio (w_audio ),
.o_image_width (w_image_width ),
.o_image_height (w_image_height ),
.o_hsync (w_hsync ),
.o_vsync (w_vsync ),
.o_red (w_red ),
.o_green (w_green ),
.o_blue (w_blue ),
//HCI Interface
.i_hci_reset (w_hci_reset ),
.i_hci_opcode (r_hci_opcode ),
.i_hci_opcode_strobe (r_hci_opcode_strobe ),
.o_hci_opcode_status (w_hci_opcode_status ),
.o_hci_opcode_ack (w_hci_opcode_ack ),
.i_hci_address (r_hci_address ),
.i_hci_count (r_hci_count ),
.i_hci_data_strobe (r_hci_din_strobe ),
.o_hci_sm_ready (w_hci_sm_ready ),
.i_hci_data (r_hci_din ),
.o_hci_data_strobe (w_hci_dout_strobe ),
.i_hci_host_ready (r_hci_host_ready ),
.o_hci_data (w_hci_dout )
);
//Asynchronous Logic
//assign status[STATUS_CLOCK_LOCKED] = clk_locked;
assign status[STATUS_CLOCK_LOCKED] = 1'b0;
assign status[STATUS_HCI_READY] = w_hci_sm_ready;
assign status[STATUS_HCI_NEW_STATUS] = r_hci_opcode_new_status;
assign status[STATUS_HCI_S_TOP:STATUS_HCI_S_BOT] = r_hci_opcode_status;
assign status[15:3] = 0;
assign dma_status[3:0] = {
(r_memory_1_size == 0),
(r_memory_0_size == 0),
w_memory_1_finished,
w_memory_0_finished
};
assign w_memory_ready = (!w_memory_0_empty) || (!w_memory_1_empty);
assign w_hci_reset = control[CONTROL_HCI_RESET];
assign w_console_reset = control[CONTROL_CONSOLE_RESET];
assign w_enable_dma = control[CONTROL_ENABLE_DMA];
assign w_mute_control = 4'h0;
//Synchronous Logic
always @ (posedge clk) begin
if (rst || !w_enable_dma || o_wbs_int) begin
o_wbs_int <= 0;
end
else begin
if (w_memory_0_finished || w_memory_1_finished) begin
o_wbs_int <= 1;
end
else if (!w_memory_0_finished && !w_memory_1_finished) begin
o_wbs_int <= 0;
end
end
end
always @ (posedge clk) begin
if (rst) begin
o_wbs_dat <= 32'h0;
o_wbs_ack <= 0;
//HCI
r_hci_address <= 0;
r_hci_count <= 0;
r_hci_opcode_status <= 0;
r_hci_opcode <= 0;
r_hci_opcode_strobe <= 0;
r_hci_din_strobe <= 0;
r_hci_din <= 0;
//Control
control <= 0;
r_jp1_state <= 0;
r_jp2_state <= 0;
//DMA Controller
//Default base, user can change this from the API
r_memory_0_base <= w_default_mem_0_base;
r_memory_1_base <= w_default_mem_1_base;
//Nothing in the memory initially
r_memory_0_size <= 0;
r_memory_1_size <= 0;
r_memory_0_ready <= 0;
r_memory_1_ready <= 0;
end
else begin
r_hci_opcode_strobe <= 0;
r_hci_din_strobe <= 0;
r_hci_host_ready <= 0;
r_memory_0_ready <= 0;
r_memory_1_ready <= 0;
//when the master acks our ack, then put our ack down
if (o_wbs_ack && ~i_wbs_stb)begin
o_wbs_ack <= 0;
if (i_wbs_adr == STATUS) begin
r_hci_opcode_new_status <= 0;
end
end
if (i_wbs_stb && i_wbs_cyc) begin
//master is requesting somethign
if (!o_wbs_ack) begin
if (i_wbs_we) begin
//write request
case (i_wbs_adr)
CONTROL: begin
control <= i_wbs_dat;
o_wbs_ack <= 1;
end
//STATUS
USER_INPUT: begin
//Need to make the 32-bit values to joypad locations
r_jp1_state <= i_wbs_dat[7:0];
r_jp2_state <= i_wbs_dat[15:8];
o_wbs_ack <= 1;
end
HCI_OPCODE_COUNT: begin
r_hci_count <= i_wbs_dat;
o_wbs_ack <= 1;
end
HCI_OPCODE_ADDR: begin
r_hci_address <= i_wbs_dat;
o_wbs_ack <= 1;
end
HCI_OPCODE: begin
r_hci_opcode <= i_wbs_dat;
r_hci_opcode_strobe <= 1;
o_wbs_ack <= 1;
end
HCI_OPCODE_DATA: begin
r_hci_din <= i_wbs_dat[7:0];
if (w_hci_sm_ready) begin
r_hci_din_strobe <= 1;
o_wbs_ack <= 1;
end
end
REG_MEM_0_BASE: begin
r_memory_0_base <= i_wbs_dat;
o_wbs_ack <= 1;
end
REG_MEM_0_SIZE: begin
r_memory_0_size <= i_wbs_dat;
if (i_wbs_dat > 0) begin
r_memory_0_ready <= 1;
end
o_wbs_ack <= 1;
end
REG_MEM_1_BASE: begin
r_memory_1_base <= i_wbs_dat;
o_wbs_ack <= 1;
end
REG_MEM_1_SIZE: begin
r_memory_1_size <= i_wbs_dat;
if (i_wbs_dat > 0) begin
r_memory_1_ready <= 1;
end
o_wbs_ack <= 1;
end
default: begin
o_wbs_ack <= 1;
end
endcase
end
else begin
//read request
case (i_wbs_adr)
CONTROL: begin
o_wbs_dat <= control;
o_wbs_ack <= 1;
end
STATUS: begin
o_wbs_dat <= status;
o_wbs_ack <= 1;
end
//USER_INPUT
HCI_OPCODE_COUNT: begin
o_wbs_dat <= r_hci_count;
o_wbs_ack <= 1;
end
//Host Controller Interface
HCI_OPCODE_ADDR: begin
o_wbs_dat <= r_hci_address;
o_wbs_ack <= 1;
end
HCI_OPCODE: begin
o_wbs_dat <= r_hci_opcode;
o_wbs_ack <= 1;
end
HCI_OPCODE_DATA: begin
r_hci_host_ready <= 1;
if (w_hci_dout_strobe) begin
o_wbs_dat <= {24'h000000, w_hci_dout};
o_wbs_ack <= 1;
end
end
//DMA Registers
DMA_STATUS: begin
o_wbs_dat <= {28'h0000000, dma_status};
if (w_memory_0_finished) begin
$display ("Reset size 0");
r_memory_0_size <= 0;
end
if (w_memory_1_finished) begin
$display ("Reset size 1");
r_memory_1_size <= 0;
end
o_wbs_ack <= 1;
end
REG_MEM_0_BASE: begin
o_wbs_dat <= r_memory_0_base;
o_wbs_ack <= 1;
end
REG_MEM_0_SIZE: begin
o_wbs_dat <= w_memory_0_count;
o_wbs_ack <= 1;
end
REG_MEM_1_BASE: begin
o_wbs_dat <= r_memory_1_base;
o_wbs_ack <= 1;
end
REG_MEM_1_SIZE: begin
o_wbs_dat <= w_memory_1_count;
o_wbs_ack <= 1;
end
REG_IMAGE_WIDTH: begin
o_wbs_dat <= w_image_width;
o_wbs_ack <= 1;
end
REG_IMAGE_HEIGHT: begin
o_wbs_dat <= w_image_height;
o_wbs_ack <= 1;
end
default: begin
o_wbs_ack <= 1;
end
endcase
end
end //!o_wbs_ack
end
if (w_hci_opcode_ack) begin
r_hci_opcode_status <= w_hci_opcode_status;
end
end
end
endmodule
|
//-----------------------------------------------------
// Design Name : uart
// File Name : uart.v
// Function : Simple UART
// Coder : Deepak Kumar Tala
//-----------------------------------------------------
module uart (
reset ,
txclk ,
ld_tx_data ,
tx_data ,
tx_enable ,
tx_out ,
tx_empty ,
rxclk ,
uld_rx_data ,
rx_data ,
rx_enable ,
rx_in ,
rx_empty
);
// Port declarations
input reset ;
input txclk ;
input ld_tx_data ;
input [7:0] tx_data ;
input tx_enable ;
output tx_out ;
output tx_empty ;
input rxclk ;
input uld_rx_data ;
output [7:0] rx_data ;
input rx_enable ;
input rx_in ;
output rx_empty ;
// Internal Variables
reg [7:0] tx_reg ;
reg tx_empty ;
reg tx_over_run ;
reg [3:0] tx_cnt ;
reg tx_out ;
reg [7:0] rx_reg ;
reg [7:0] rx_data ;
reg [3:0] rx_sample_cnt ;
reg [3:0] rx_cnt ;
reg rx_frame_err ;
reg rx_over_run ;
reg rx_empty ;
reg rx_d1 ;
reg rx_d2 ;
reg rx_busy ;
// UART RX Logic
always @ (posedge rxclk or posedge reset)
if (reset) begin
rx_reg <= 0;
rx_data <= 0;
rx_sample_cnt <= 0;
rx_cnt <= 0;
rx_frame_err <= 0;
rx_over_run <= 0;
rx_empty <= 1;
rx_d1 <= 1;
rx_d2 <= 1;
rx_busy <= 0;
end else begin
// Synchronize the asynch signal
rx_d1 <= rx_in;
rx_d2 <= rx_d1;
// Uload the rx data
if (uld_rx_data) begin
rx_data <= rx_reg;
rx_empty <= 1;
end
// Receive data only when rx is enabled
if (rx_enable) begin
// Check if just received start of frame
if (!rx_busy && !rx_d2) begin
rx_busy <= 1;
rx_sample_cnt <= 1;
rx_cnt <= 0;
end
// Start of frame detected, Proceed with rest of data
if (rx_busy) begin
rx_sample_cnt <= rx_sample_cnt + 1;
// Logic to sample at middle of data
if (rx_sample_cnt == 7) begin
if ((rx_d2 == 1) && (rx_cnt == 0)) begin
rx_busy <= 0;
end else begin
rx_cnt <= rx_cnt + 1;
// Start storing the rx data
if (rx_cnt > 0 && rx_cnt < 9) begin
rx_reg[rx_cnt - 1] <= rx_d2;
end
if (rx_cnt == 9) begin
rx_busy <= 0;
// Check if End of frame received correctly
if (rx_d2 == 0) begin
rx_frame_err <= 1;
end else begin
rx_empty <= 0;
rx_frame_err <= 0;
// Check if last rx data was not unloaded,
rx_over_run <= (rx_empty) ? 0 : 1;
end
end
end
end
end
end
if (!rx_enable) begin
rx_busy <= 0;
end
end
// UART TX Logic
always @ (posedge txclk or posedge reset)
if (reset) begin
tx_reg <= 0;
tx_empty <= 1;
tx_over_run <= 0;
tx_out <= 1;
tx_cnt <= 0;
end else begin
if (ld_tx_data) begin
if (!tx_empty) begin
tx_over_run <= 0;
end else begin
tx_reg <= tx_data;
tx_empty <= 0;
end
end
if (tx_enable && !tx_empty) begin
tx_cnt <= tx_cnt + 1;
if (tx_cnt == 0) begin
tx_out <= 0;
end
if (tx_cnt > 0 && tx_cnt < 9) begin
tx_out <= tx_reg[tx_cnt -1];
end
if (tx_cnt == 9) begin
tx_out <= 1;
tx_cnt <= 0;
tx_empty <= 1;
end
end
if (!tx_enable) begin
tx_cnt <= 0;
end
end
endmodule
|
/*
Copyright 2015, Google Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module wb_trng (
input wb_clk,
input wb_rst,
input [31:0] wb_adr_i,
input [7:0] wb_dat_i,
input wb_we_i,
input wb_cyc_i,
input wb_stb_i,
input [2:0] wb_cti_i,
input [1:0] wb_bte_i,
output [7:0] wb_dat_o,
output reg wb_ack_o,
output wb_err_o,
output wb_rty_o
);
wire valid = wb_cyc_i & wb_stb_i;
trng trng_inst (
.clk(wb_clk),
.en(valid),
.R(wb_dat_o)
);
always @(posedge wb_clk)
begin
wb_ack_o <= 0;
if(valid)
wb_ack_o <= 1;
end
assign wb_err_o = 0;
assign wb_rty_o = 0;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_IO__TOP_POWER_HVC_WPADV2_PP_BLACKBOX_V
`define SKY130_FD_IO__TOP_POWER_HVC_WPADV2_PP_BLACKBOX_V
/**
* top_power_hvc_wpadv2: A power pad with an ESD high-voltage clamp.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_io__top_power_hvc_wpadv2 (
P_PAD ,
AMUXBUS_A ,
AMUXBUS_B ,
OGC_HVC ,
DRN_HVC ,
SRC_BDY_HVC,
P_CORE ,
VDDIO ,
VDDIO_Q ,
VDDA ,
VCCD ,
VSWITCH ,
VCCHIB ,
VSSA ,
VSSD ,
VSSIO_Q ,
VSSIO
);
inout P_PAD ;
inout AMUXBUS_A ;
inout AMUXBUS_B ;
inout OGC_HVC ;
inout DRN_HVC ;
inout SRC_BDY_HVC;
inout P_CORE ;
inout VDDIO ;
inout VDDIO_Q ;
inout VDDA ;
inout VCCD ;
inout VSWITCH ;
inout VCCHIB ;
inout VSSA ;
inout VSSD ;
inout VSSIO_Q ;
inout VSSIO ;
endmodule
`default_nettype wire
`endif // SKY130_FD_IO__TOP_POWER_HVC_WPADV2_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21O_0_V
`define SKY130_FD_SC_LP__A21O_0_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog wrapper for a21o with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a21o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a21o_0 (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a21o_0 (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21O_0_V
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 8.1 Build 163 10/28/2008 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2008 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll (
inclk0,
c0,
c2,
locked);
input inclk0;
output c0;
output c2;
output locked;
wire [5:0] sub_wire0;
wire sub_wire3;
wire [0:0] sub_wire6 = 1'h0;
wire [2:2] sub_wire2 = sub_wire0[2:2];
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire c2 = sub_wire2;
wire locked = sub_wire3;
wire sub_wire4 = inclk0;
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
altpll altpll_component (
.inclk (sub_wire5),
.clk (sub_wire0),
.locked (sub_wire3),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 1,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk2_divide_by = 10,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 13,
altpll_component.clk2_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.gate_lock_signal = "NO",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone II",
altpll_component.invalid_lock_multiplier = 5,
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.valid_lock_multiplier = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "300.000"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "65.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "10"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "13"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_waveforms.html FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_wave*.jpg FALSE FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
// megafunction wizard: %LPM_CLSHIFT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_CLSHIFT
// ============================================================
// File Name: SHIFT.v
// Megafunction Name(s):
// LPM_CLSHIFT
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module SHIFT (
data,
direction,
distance,
result);
input [15:0] data;
input direction;
input [3:0] distance;
output [15:0] result;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: LPM_SHIFTTYPE NUMERIC "0"
// Retrieval info: PRIVATE: LPM_WIDTH NUMERIC "16"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: lpm_widthdist NUMERIC "4"
// Retrieval info: PRIVATE: lpm_widthdist_style NUMERIC "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: PRIVATE: port_direction NUMERIC "2"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_SHIFTTYPE STRING "LOGICAL"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CLSHIFT"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHDIST NUMERIC "4"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
// Retrieval info: USED_PORT: direction 0 0 0 0 INPUT NODEFVAL "direction"
// Retrieval info: USED_PORT: distance 0 0 4 0 INPUT NODEFVAL "distance[3..0]"
// Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL "result[15..0]"
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @direction 0 0 0 0 direction 0 0 0 0
// Retrieval info: CONNECT: @distance 0 0 4 0 distance 0 0 4 0
// Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL SHIFT.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL SHIFT.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL SHIFT.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL SHIFT.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL SHIFT_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL SHIFT_bb.v TRUE
|
`include "../mem/im.v"
`include "../RF/reg_file2.v"
`include "../ALU/alu.v"
`include "../lib/mux5bit_2to1_2.v"
`include "../lib/mux32bit_4to1.v"
`include "../lib/mux32bit_2to1.v"
`include "../lib/mux32bit_2to1_2.v"
`include "../lib/sign_extend.v"
`include "../control/control2.v"
`include "../ALU/alu_control2.v"
`include "../mem/dm.v"
`include "../lib/shift_left_2.v"
`include "../lib/jump_addr.v"
module cpu(input clk,
output [31:0] alu_output, data, nxt_pc);
reg [31:0] pc;
wire [31:0] readData1, readData2, b;
wire regDest0, regDst1, regWrite, aluSrc, zero, memToReg0, memToReg1;
wire memRead, memWrite, branch, branch_ne, s_branch, jump;
wire [31:0] sExtended, alu_output, memData, writeData, j_addr, mux3_output, mux4_output;
wire [3:0] alu_ctrl;
wire [2:0] alu_op;
wire [4:0] writeReg;
wire [31:0] fa1_output, ex_shifted, pc_4;
initial pc <= 32'd0;
im i_mem(.clk(clk),
.data(data),
.addr(pc));
mux5bit_4to1 mux0(.i0(data[20:16]),
.i1(data[15:11]),
.i2(5'd31),
.s({regDst1, regDst0}),
.z(writeReg));
reg_file rf(.readReg1(data[25:21]),
.readReg2(data[20:16]),
.writeReg(writeReg),
.clk(clk),
.regWrite(regWrite),
.readData1(readData1),
.readData2(readData2),
.writeData(writeData));
sign_extend se(.a(data[15:0]), .b(sExtended));
mux32bit_2to1 mux1(.i0(readData2),
.i1(sExtended),
.s(aluSrc),
.z(b));
alu main_alu(.op(alu_ctrl), .a(readData1), .b(b), .z(alu_output), .zero(zero));
alu_control ac (.funct(data[5:0]), .alu_op(alu_op), .aluctrl(alu_ctrl));
control c(.op(data[31:26]),
.alu_op(alu_op),
.regDst0(regDst0),
.regDst1(regDst1),
.aluSrc(aluSrc),
.memToReg0(memToReg0),
.memToReg1(memToReg1),
.regWrite(regWrite),
.memRead(memRead),
.memWrite(memWrite),
.branch(branch),
.branch_ne(branch_ne),
.jump(jump));
dm mem(.clk(clk), .addr(alu_output), .writeData(readData2), .memWrite(memWrite), .memRead(memRead), .readData(memData));
mux32bit_4to1 mux2(.i0(alu_output), .i1(memData), .i2(pc_4), .s({memToReg1, memToReg0}), .z(writeData));
shift_left_2 sll2(.a(sExtended), .b(ex_shifted));
//alu fa1(.op(4'd2), .a(pc_4), .b(ex_shifted), .z(fa1_output));
alu fa1(.op(4'd2), .a(pc_4), .b(sExtended), .z(fa1_output));
wire int0, int1;
and (int0, branch, zero);
and (int1, branch_ne, ~zero);
or (s_branch, int0, int1);
wire jr;
and and1(jr , ~data[5], ~data[4], data[3], ~data[2], ~data[1], ~data[0]
, ~data[26], ~data[27],~data[28], ~data[29], ~data[30], ~data[31] );
//always @(*) jr = ~data[26] & ~data[27] & data[28] & ~data[29] & ~data[30] & ~data[31];
jump_addr ja(.inst(data[25:0]), .pc_4(pc_4[31:28]), .j_addr(j_addr));
//mux32bit_2to1 mux3(.i0(pc_4), .i1(fa1_output), .s(s_branch), .z(nxt_pc));
mux32bit_2to1_2 mux3(.i0(pc_4), .i1(fa1_output), .s(s_branch), .z(mux3_output));
mux32bit_2to1_2 mux4(.i0(mux3_output), .i1(j_addr), .s(jump), .z(mux4_output));
mux32bit_2to1_2 mux5(.i1(readData1), .i0(mux4_output), .z(nxt_pc), .s(jr));
//mux32bit_2to1 mux4(.i1(j_addr), .i0(mux3_output), .z(nxt_pc), .s(jump));
alu fa2(.op(4'd2), .a(pc), .b(32'd1), .z(pc_4));
always @(posedge clk) begin
pc <= nxt_pc;
end
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: AXI Splitter
// Each transfer received on the AXI handshake slave port is replicated onto
// each of the master ports, and is completed back to the slave (S_READY)
// once all master ports have completed.
//
// M_VALID is asserted combinatorially from S_VALID assertion.
// Each M_VALID is masked off beginning the cycle after each M_READY is
// received (if S_READY remains low) until the cycle after both S_VALID
// and S_READY are asserted.
// S_READY is asserted combinatorially when the last (or all) of the M_READY
// inputs have been received.
// If all M_READYs are asserted when S_VALID is asserted, back-to-back
// handshakes can occur without bubble cycles.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// splitter
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_9_splitter #
(
parameter integer C_NUM_M = 2 // Number of master ports = [2:16]
)
(
// Global Signals
input wire ACLK,
input wire ARESET,
// Slave Port
input wire S_VALID,
output wire S_READY,
// Master Ports
output wire [C_NUM_M-1:0] M_VALID,
input wire [C_NUM_M-1:0] M_READY
);
reg [C_NUM_M-1:0] m_ready_d;
wire s_ready_i;
wire [C_NUM_M-1:0] m_valid_i;
always @(posedge ACLK) begin
if (ARESET | s_ready_i) m_ready_d <= {C_NUM_M{1'b0}};
else m_ready_d <= m_ready_d | (m_valid_i & M_READY);
end
assign s_ready_i = &(m_ready_d | M_READY);
assign m_valid_i = {C_NUM_M{S_VALID}} & ~m_ready_d;
assign M_VALID = m_valid_i;
assign S_READY = s_ready_i;
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: O.40d
// \ \ Application: netgen
// / / Filename: chipscope_vio_tochip.v
// /___/ /\ Timestamp: Thu May 19 17:37:45 2011
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog D:/Documents/Projects/xilinx_fpgaminer/ipcore_dir/tmp/_cg/chipscope_vio_tochip.ngc D:/Documents/Projects/xilinx_fpgaminer/ipcore_dir/tmp/_cg/chipscope_vio_tochip.v
// Device : xc6slx150t-fgg676-3
// Input file : D:/Documents/Projects/xilinx_fpgaminer/ipcore_dir/tmp/_cg/chipscope_vio_tochip.ngc
// Output file : D:/Documents/Projects/xilinx_fpgaminer/ipcore_dir/tmp/_cg/chipscope_vio_tochip.v
// # of Modules : 1
// Design Name : chipscope_vio_tochip
// Xilinx : F:\Xilinx\13.1\ISE_DS\ISE\
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module chipscope_vio_tochip (
CLK, CONTROL, SYNC_OUT
)/* synthesis syn_black_box syn_noprune=1 */;
input CLK;
inout [35 : 0] CONTROL;
output [255 : 0] SYNC_OUT;
// synthesis translate_off
wire N0;
wire N1;
wire \U0/I_VIO/GEN_UPDATE_OUT[511].UPDATE_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[0].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[0].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[1].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[1].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[2].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[2].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[3].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[3].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[4].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[4].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[5].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[5].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[6].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[6].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[7].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[7].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[8].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[8].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[9].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[9].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[10].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[10].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[11].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[11].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[12].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[12].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[13].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[13].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[14].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[14].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[15].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[15].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[16].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[16].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[17].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[17].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[18].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[18].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[19].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[19].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[20].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[20].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[21].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[21].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[22].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[22].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[23].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[23].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[24].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[24].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[25].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[25].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[26].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[26].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[27].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[27].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[28].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[28].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[29].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[29].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[30].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[30].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[31].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[31].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[32].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[32].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[33].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[33].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[34].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[34].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[35].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[35].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[36].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[36].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[37].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[37].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[38].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[38].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[39].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[39].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[40].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[40].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[41].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[41].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[42].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[42].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[43].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[43].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[44].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[44].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[45].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[45].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[46].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[46].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[47].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[47].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[48].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[48].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[49].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[49].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[50].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[50].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[51].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[51].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[52].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[52].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[53].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[53].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[54].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[54].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[55].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[55].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[56].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[56].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[57].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[57].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[58].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[58].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[59].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[59].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[60].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[60].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[61].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[61].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[62].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[62].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[63].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[63].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[64].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[64].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[65].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[65].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[66].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[66].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[67].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[67].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[68].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[68].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[69].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[69].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[70].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[70].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[71].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[71].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[72].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[72].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[73].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[73].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[74].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[74].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[75].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[75].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[76].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[76].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[77].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[77].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[78].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[78].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[79].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[79].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[80].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[80].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[81].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[81].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[82].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[82].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[83].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[83].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[84].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[84].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[85].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[85].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[86].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[86].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[87].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[87].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[88].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[88].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[89].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[89].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[90].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[90].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[91].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[91].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[92].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[92].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[93].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[93].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[94].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[94].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[95].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[95].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[96].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[96].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[97].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[97].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[98].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[98].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[99].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[99].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[100].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[100].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[101].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[101].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[102].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[102].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[103].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[103].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[104].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[104].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[105].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[105].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[106].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[106].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[107].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[107].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[108].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[108].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[109].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[109].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[110].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[110].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[111].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[111].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[112].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[112].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[113].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[113].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[114].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[114].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[115].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[115].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[116].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[116].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[117].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[117].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[118].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[118].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[119].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[119].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[120].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[120].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[121].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[121].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[122].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[122].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[123].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[123].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[124].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[124].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[125].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[125].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[126].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[126].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[127].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[127].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[128].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[128].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[129].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[129].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[130].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[130].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[131].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[131].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[132].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[132].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[133].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[133].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[134].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[134].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[135].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[135].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[136].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[136].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[137].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[137].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[138].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[138].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[139].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[139].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[140].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[140].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[141].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[141].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[142].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[142].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[143].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[143].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[144].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[144].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[145].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[145].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[146].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[146].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[147].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[147].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[148].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[148].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[149].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[149].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[150].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[150].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[151].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[151].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[152].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[152].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[153].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[153].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[154].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[154].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[155].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[155].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[156].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[156].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[157].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[157].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[158].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[158].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[159].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[159].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[160].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[160].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[161].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[161].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[162].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[162].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[163].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[163].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[164].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[164].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[165].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[165].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[166].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[166].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[167].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[167].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[168].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[168].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[169].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[169].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[170].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[170].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[171].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[171].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[172].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[172].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[173].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[173].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[174].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[174].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[175].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[175].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[176].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[176].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[177].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[177].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[178].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[178].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[179].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[179].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[180].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[180].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[181].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[181].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[182].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[182].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[183].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[183].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[184].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[184].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[185].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[185].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[186].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[186].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[187].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[187].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[188].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[188].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[189].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[189].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[190].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[190].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[191].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[191].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[192].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[192].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[193].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[193].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[194].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[194].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[195].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[195].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[196].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[196].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[197].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[197].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[198].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[198].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[199].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[199].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[200].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[200].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[201].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[201].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[202].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[202].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[203].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[203].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[204].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[204].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[205].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[205].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[206].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[206].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[207].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[207].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[208].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[208].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[209].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[209].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[210].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[210].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[211].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[211].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[212].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[212].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[213].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[213].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[214].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[214].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[215].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[215].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[216].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[216].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[217].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[217].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[218].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[218].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[219].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[219].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[220].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[220].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[221].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[221].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[222].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[222].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[223].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[223].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[224].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[224].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[225].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[225].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[226].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[226].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[227].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[227].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[228].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[228].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[229].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[229].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[230].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[230].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[231].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[231].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[232].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[232].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[233].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[233].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[234].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[234].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[235].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[235].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[236].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[236].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[237].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[237].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[238].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[238].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[239].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[239].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[240].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[240].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[241].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[241].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[242].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[242].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[243].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[243].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[244].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[244].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[245].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[245].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[246].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[246].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[247].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[247].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[248].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[248].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[249].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[249].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[250].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[250].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[251].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[251].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[252].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[252].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[253].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[253].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[254].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[254].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[255].SYNC_OUT_CELL/out_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT[255].SYNC_OUT_CELL/SHIFT_OUT_temp ;
wire \U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/arm_dly1 ;
wire \U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/arm_dly2 ;
wire \U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/cnt_reset ;
wire \U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/cnt_ce ;
wire \U0/I_VIO/GEN_TRANS.U_ARM/din_latched ;
wire \U0/I_VIO/GEN_TRANS.U_ARM/iCLR ;
wire \U0/I_VIO/DATA_DOUT ;
wire \U0/I_VIO/ARM_pulse ;
wire \U0/I_VIO/STAT_DOUT ;
wire \U0/I_VIO/U_STATUS/TDO_next ;
wire \U0/I_VIO/U_STATUS/CFG_CE_n ;
wire \U0/I_VIO/U_STATUS/U_SMUX/U_CS_MUX/I4.U_MUX16/Mmux_O2 ;
wire \U0/I_VIO/U_STATUS/U_SMUX/U_CS_MUX/I4.U_MUX16/Mmux_O21_1647 ;
wire \U0/I_VIO/U_STATUS/U_SMUX/U_CS_MUX/I4.U_MUX16/Mmux_O22_1648 ;
wire \U0/I_VIO/U_STATUS/U_SMUX/U_CS_MUX/I4.U_MUX16/Mmux_O23_1649 ;
wire \U0/I_VIO/U_STATUS/U_SMUX/U_CS_MUX/I4.U_MUX16/Mmux_O24_1650 ;
wire \U0/I_VIO/U_STATUS/U_SMUX/U_CS_MUX/I4.U_MUX16/Mmux_O25_1651 ;
wire \U0/I_VIO/U_STATUS/U_SMUX/U_CS_MUX/I4.U_MUX16/Mmux_O26_1652 ;
wire \U0/I_VIO/U_STATUS/U_SMUX/U_CS_MUX/I4.U_MUX16/Mmux_O27_1653 ;
wire \U0/I_VIO/U_STATUS/U_SMUX/U_CS_MUX/I4.U_MUX16/Mmux_O28_1654 ;
wire \NLW_U0/I_VIO/reset_f_edge/I_H2L.U_DOUT_Q_UNCONNECTED ;
wire [1 : 0] \U0/I_VIO/reset_f_edge/iDOUT ;
wire [1 : 0] \U0/I_VIO/GEN_TRANS.U_ARM/iDIN ;
wire [1 : 0] \U0/I_VIO/GEN_TRANS.U_ARM/iDOUT_dly ;
wire [255 : 0] \U0/I_VIO/UPDATE ;
wire [511 : 1] \U0/I_VIO/OUTPUT_SHIFT ;
wire [3 : 0] \U0/I_VIO/addr ;
wire [7 : 0] \U0/I_VIO/U_STATUS/iSTAT ;
wire [7 : 0] \U0/I_VIO/U_STATUS/iSTAT_CNT ;
wire [7 : 0] \U0/I_VIO/U_STATUS/U_STAT_CNT/D ;
wire [7 : 1] \U0/I_VIO/U_STATUS/U_STAT_CNT/CI ;
wire [7 : 0] \U0/I_VIO/U_STATUS/U_STAT_CNT/S ;
wire [3 : 0] \U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/COUNT/D ;
wire [3 : 1] \U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/COUNT/CI ;
wire [3 : 0] \U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/COUNT/S ;
VCC XST_VCC (
.P(N0)
);
GND XST_GND (
.G(N1)
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[0].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(CONTROL[1]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[0].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[0].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[0].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[0].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [1])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[1].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [1]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[1].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[1].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[1].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[1].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [2])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[2].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [2]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[2].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[2].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[2].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[2].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [3])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[3].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [3]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[3].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[3].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[3].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[3].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [4])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[4].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [4]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[4].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[4].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[4].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[4].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [5])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[5].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [5]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[5].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[5].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[5].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[5].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [6])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[6].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [6]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[6].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[6].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[6].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[6].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [7])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[7].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [7]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[7].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[7].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[7].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[7].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [8])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[8].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [8]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[8].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[8].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[8].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[8].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [9])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[9].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [9]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[9].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[9].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[9].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[9].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [10])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[10].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [10]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[10].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[10].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[10].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[10].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [11])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[11].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [11]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[11].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[11].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[11].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[11].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [12])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[12].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [12]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[12].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[12].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[12].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[12].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [13])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[13].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [13]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[13].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[13].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[13].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[13].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [14])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[14].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [14]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[14].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[14].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[14].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[14].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [15])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[15].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [15]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[15].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[15].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[15].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[15].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [16])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[16].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [16]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[16].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[16].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[16].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[16].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [17])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[17].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [17]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[17].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[17].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[17].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[17].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [18])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[18].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [18]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[18].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[18].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[18].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[18].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [19])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[19].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [19]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[19].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[19].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[19].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[19].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [20])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[20].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [20]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[20].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[20].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[20].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[20].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [21])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[21].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [21]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[21].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[21].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[21].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[21].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [22])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[22].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [22]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[22].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[22].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[22].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[22].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [23])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[23].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [23]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[23].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[23].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[23].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[23].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [24])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[24].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [24]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[24].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[24].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[24].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[24].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [25])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[25].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [25]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[25].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[25].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[25].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[25].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [26])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[26].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [26]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[26].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[26].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[26].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[26].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [27])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[27].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [27]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[27].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[27].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[27].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[27].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [28])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[28].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [28]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[28].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[28].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[28].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[28].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [29])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[29].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [29]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[29].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[29].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[29].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[29].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [30])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[30].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [30]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[30].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[30].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[30].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[30].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [31])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[31].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [31]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[31].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[31].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[31].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[31].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [32])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[32].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [32]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[32].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[32].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[32].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[32].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [33])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[33].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [33]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[33].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[33].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[33].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[33].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [34])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[34].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [34]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[34].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[34].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[34].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[34].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [35])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[35].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [35]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[35].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[35].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[35].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[35].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [36])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[36].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [36]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[36].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[36].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[36].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[36].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [37])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[37].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [37]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[37].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[37].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[37].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[37].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [38])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[38].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [38]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[38].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[38].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[38].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[38].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [39])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[39].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [39]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[39].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[39].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[39].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[39].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [40])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[40].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [40]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[40].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[40].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[40].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[40].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [41])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[41].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [41]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[41].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[41].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[41].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[41].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [42])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[42].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [42]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[42].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[42].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[42].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[42].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [43])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[43].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [43]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[43].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[43].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[43].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[43].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [44])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[44].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [44]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[44].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[44].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[44].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[44].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [45])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[45].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [45]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[45].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[45].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[45].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[45].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [46])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[46].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [46]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[46].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[46].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[46].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[46].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [47])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[47].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [47]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[47].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[47].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[47].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[47].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [48])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[48].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [48]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[48].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[48].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[48].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[48].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [49])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[49].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [49]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[49].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[49].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[49].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[49].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [50])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[50].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [50]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[50].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[50].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[50].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[50].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [51])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[51].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [51]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[51].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[51].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[51].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[51].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [52])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[52].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [52]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[52].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[52].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[52].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[52].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [53])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[53].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [53]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[53].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[53].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[53].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[53].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [54])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[54].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [54]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[54].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[54].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[54].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[54].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [55])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[55].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [55]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[55].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[55].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[55].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[55].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [56])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[56].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [56]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[56].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[56].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[56].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[56].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [57])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[57].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [57]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[57].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[57].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[57].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[57].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [58])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[58].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [58]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[58].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[58].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[58].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[58].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [59])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[59].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [59]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[59].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[59].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[59].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[59].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [60])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[60].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [60]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[60].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[60].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[60].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[60].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [61])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[61].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [61]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[61].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[61].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[61].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[61].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [62])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[62].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [62]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[62].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[62].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[62].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[62].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [63])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[63].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [63]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[63].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[63].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[63].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[63].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [64])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[64].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [64]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[64].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[64].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[64].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[64].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [65])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[65].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [65]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[65].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[65].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[65].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[65].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [66])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[66].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [66]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[66].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[66].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[66].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[66].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [67])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[67].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [67]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[67].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[67].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[67].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[67].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [68])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[68].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [68]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[68].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[68].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[68].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[68].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [69])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[69].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [69]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[69].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[69].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[69].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[69].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [70])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[70].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [70]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[70].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[70].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[70].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[70].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [71])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[71].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [71]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[71].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[71].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[71].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[71].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [72])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[72].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [72]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[72].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[72].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[72].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[72].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [73])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[73].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [73]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[73].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[73].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[73].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[73].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [74])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[74].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [74]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[74].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[74].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[74].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[74].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [75])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[75].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [75]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[75].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[75].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[75].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[75].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [76])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[76].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [76]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[76].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[76].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[76].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[76].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [77])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[77].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [77]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[77].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[77].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[77].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[77].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [78])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[78].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [78]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[78].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[78].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[78].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[78].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [79])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[79].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [79]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[79].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[79].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[79].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[79].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [80])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[80].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [80]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[80].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[80].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[80].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[80].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [81])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[81].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [81]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[81].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[81].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[81].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[81].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [82])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[82].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [82]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[82].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[82].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[82].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[82].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [83])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[83].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [83]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[83].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[83].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[83].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[83].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [84])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[84].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [84]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[84].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[84].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[84].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[84].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [85])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[85].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [85]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[85].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[85].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[85].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[85].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [86])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[86].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [86]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[86].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[86].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[86].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[86].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [87])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[87].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [87]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[87].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[87].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[87].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[87].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [88])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[88].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [88]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[88].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[88].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[88].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[88].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [89])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[89].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [89]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[89].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[89].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[89].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[89].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [90])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[90].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [90]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[90].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[90].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[90].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[90].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [91])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[91].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [91]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[91].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[91].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[91].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[91].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [92])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[92].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [92]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[92].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[92].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[92].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[92].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [93])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[93].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [93]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[93].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[93].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[93].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[93].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [94])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[94].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [94]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[94].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[94].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[94].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[94].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [95])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[95].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [95]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[95].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[95].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[95].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[95].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [96])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[96].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [96]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[96].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[96].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[96].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[96].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [97])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[97].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [97]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[97].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[97].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[97].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[97].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [98])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[98].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [98]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[98].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[98].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[98].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[98].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [99])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[99].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [99]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[99].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[99].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[99].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[99].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [100])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[100].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [100]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[100].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[100].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[100].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[100].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [101])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[101].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [101]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[101].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[101].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[101].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[101].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [102])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[102].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [102]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[102].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[102].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[102].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[102].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [103])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[103].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [103]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[103].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[103].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[103].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[103].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [104])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[104].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [104]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[104].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[104].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[104].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[104].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [105])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[105].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [105]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[105].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[105].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[105].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[105].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [106])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[106].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [106]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[106].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[106].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[106].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[106].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [107])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[107].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [107]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[107].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[107].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[107].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[107].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [108])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[108].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [108]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[108].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[108].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[108].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[108].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [109])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[109].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [109]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[109].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[109].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[109].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[109].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [110])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[110].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [110]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[110].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[110].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[110].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[110].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [111])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[111].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [111]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[111].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[111].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[111].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[111].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [112])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[112].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [112]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[112].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[112].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[112].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[112].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [113])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[113].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [113]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[113].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[113].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[113].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[113].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [114])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[114].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [114]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[114].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[114].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[114].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[114].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [115])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[115].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [115]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[115].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[115].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[115].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[115].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [116])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[116].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [116]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[116].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[116].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[116].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[116].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [117])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[117].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [117]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[117].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[117].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[117].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[117].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [118])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[118].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [118]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[118].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[118].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[118].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[118].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [119])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[119].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [119]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[119].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[119].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[119].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[119].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [120])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[120].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [120]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[120].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[120].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[120].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[120].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [121])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[121].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [121]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[121].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[121].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[121].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[121].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [122])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[122].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [122]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[122].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[122].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[122].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[122].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [123])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[123].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [123]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[123].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[123].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[123].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[123].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [124])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[124].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [124]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[124].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[124].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[124].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[124].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [125])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[125].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [125]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[125].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[125].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[125].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[125].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [126])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[126].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [126]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[126].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[126].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[126].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[126].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [127])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[127].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [127]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[127].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[127].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[127].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[127].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [128])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[128].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [128]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[128].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[128].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[128].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[128].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [129])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[129].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [129]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[129].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[129].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[129].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[129].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [130])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[130].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [130]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[130].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[130].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[130].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[130].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [131])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[131].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [131]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[131].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[131].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[131].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[131].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [132])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[132].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [132]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[132].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[132].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[132].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[132].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [133])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[133].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [133]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[133].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[133].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[133].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[133].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [134])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[134].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [134]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[134].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[134].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[134].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[134].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [135])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[135].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [135]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[135].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[135].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[135].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[135].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [136])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[136].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [136]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[136].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[136].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[136].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[136].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [137])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[137].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [137]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[137].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[137].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[137].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[137].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [138])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[138].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [138]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[138].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[138].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[138].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[138].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [139])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[139].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [139]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[139].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[139].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[139].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[139].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [140])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[140].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [140]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[140].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[140].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[140].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[140].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [141])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[141].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [141]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[141].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[141].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[141].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[141].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [142])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[142].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [142]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[142].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[142].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[142].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[142].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [143])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[143].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [143]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[143].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[143].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[143].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[143].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [144])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[144].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [144]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[144].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[144].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[144].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[144].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [145])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[145].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [145]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[145].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[145].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[145].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[145].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [146])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[146].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [146]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[146].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[146].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[146].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[146].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [147])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[147].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [147]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[147].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[147].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[147].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[147].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [148])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[148].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [148]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[148].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[148].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[148].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[148].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [149])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[149].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [149]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[149].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[149].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[149].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[149].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [150])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[150].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [150]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[150].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[150].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[150].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[150].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [151])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[151].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [151]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[151].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[151].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[151].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[151].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [152])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[152].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [152]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[152].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[152].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[152].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[152].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [153])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[153].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [153]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[153].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[153].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[153].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[153].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [154])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[154].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [154]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[154].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[154].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[154].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[154].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [155])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[155].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [155]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[155].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[155].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[155].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[155].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [156])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[156].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [156]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[156].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[156].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[156].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[156].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [157])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[157].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [157]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[157].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[157].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[157].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[157].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [158])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[158].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [158]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[158].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[158].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[158].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[158].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [159])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[159].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [159]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[159].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[159].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[159].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[159].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [160])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[160].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [160]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[160].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[160].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[160].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[160].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [161])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[161].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [161]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[161].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[161].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[161].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[161].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [162])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[162].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [162]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[162].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[162].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[162].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[162].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [163])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[163].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [163]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[163].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[163].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[163].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[163].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [164])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[164].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [164]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[164].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[164].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[164].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[164].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [165])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[165].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [165]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[165].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[165].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[165].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[165].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [166])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[166].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [166]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[166].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[166].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[166].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[166].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [167])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[167].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [167]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[167].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[167].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[167].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[167].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [168])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[168].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [168]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[168].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[168].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[168].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[168].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [169])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[169].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [169]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[169].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[169].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[169].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[169].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [170])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[170].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [170]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[170].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[170].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[170].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[170].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [171])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[171].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [171]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[171].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[171].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[171].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[171].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [172])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[172].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [172]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[172].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[172].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[172].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[172].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [173])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[173].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [173]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[173].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[173].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[173].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[173].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [174])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[174].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [174]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[174].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[174].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[174].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[174].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [175])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[175].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [175]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[175].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[175].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[175].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[175].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [176])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[176].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [176]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[176].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[176].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[176].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[176].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [177])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[177].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [177]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[177].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[177].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[177].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[177].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [178])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[178].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [178]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[178].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[178].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[178].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[178].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [179])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[179].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [179]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[179].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[179].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[179].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[179].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [180])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[180].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [180]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[180].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[180].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[180].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[180].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [181])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[181].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [181]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[181].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[181].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[181].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[181].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [182])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[182].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [182]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[182].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[182].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[182].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[182].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [183])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[183].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [183]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[183].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[183].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[183].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[183].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [184])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[184].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [184]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[184].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[184].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[184].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[184].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [185])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[185].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [185]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[185].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[185].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[185].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[185].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [186])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[186].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [186]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[186].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[186].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[186].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[186].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [187])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[187].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [187]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[187].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[187].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[187].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[187].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [188])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[188].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [188]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[188].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[188].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[188].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[188].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [189])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[189].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [189]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[189].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[189].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[189].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[189].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [190])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[190].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [190]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[190].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[190].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[190].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[190].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [191])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[191].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [191]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[191].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[191].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[191].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[191].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [192])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[192].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [192]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[192].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[192].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[192].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[192].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [193])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[193].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [193]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[193].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[193].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[193].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[193].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [194])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[194].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [194]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[194].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[194].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[194].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[194].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [195])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[195].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [195]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[195].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[195].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[195].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[195].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [196])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[196].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [196]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[196].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[196].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[196].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[196].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [197])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[197].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [197]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[197].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[197].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[197].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[197].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [198])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[198].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [198]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[198].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[198].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[198].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[198].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [199])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[199].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [199]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[199].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[199].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[199].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[199].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [200])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[200].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [200]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[200].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[200].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[200].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[200].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [201])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[201].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [201]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[201].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[201].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[201].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[201].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [202])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[202].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [202]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[202].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[202].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[202].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[202].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [203])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[203].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [203]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[203].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[203].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[203].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[203].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [204])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[204].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [204]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[204].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[204].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[204].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[204].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [205])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[205].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [205]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[205].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[205].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[205].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[205].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [206])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[206].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [206]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[206].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[206].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[206].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[206].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [207])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[207].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [207]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[207].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[207].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[207].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[207].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [208])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[208].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [208]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[208].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[208].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[208].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[208].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [209])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[209].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [209]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[209].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[209].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[209].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[209].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [210])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[210].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [210]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[210].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[210].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[210].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[210].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [211])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[211].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [211]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[211].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[211].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[211].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[211].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [212])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[212].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [212]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[212].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[212].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[212].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[212].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [213])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[213].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [213]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[213].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[213].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[213].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[213].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [214])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[214].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [214]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[214].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[214].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[214].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[214].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [215])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[215].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [215]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[215].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[215].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[215].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[215].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [216])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[216].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [216]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[216].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[216].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[216].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[216].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [217])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[217].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [217]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[217].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[217].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[217].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[217].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [218])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[218].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [218]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[218].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[218].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[218].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[218].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [219])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[219].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [219]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[219].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[219].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[219].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[219].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [220])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[220].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [220]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[220].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[220].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[220].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[220].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [221])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[221].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [221]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[221].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[221].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[221].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[221].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [222])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[222].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [222]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[222].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[222].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[222].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[222].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [223])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[223].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [223]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[223].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[223].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[223].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[223].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [224])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[224].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [224]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[224].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[224].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[224].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[224].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [225])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[225].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [225]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[225].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[225].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[225].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[225].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [226])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[226].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [226]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[226].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[226].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[226].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[226].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [227])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[227].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [227]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[227].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[227].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[227].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[227].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [228])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[228].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [228]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[228].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[228].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[228].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[228].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [229])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[229].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [229]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[229].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[229].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[229].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[229].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [230])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[230].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [230]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[230].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[230].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[230].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[230].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [231])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[231].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [231]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[231].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[231].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[231].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[231].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [232])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[232].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [232]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[232].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[232].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[232].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[232].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [233])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[233].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [233]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[233].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[233].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[233].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[233].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [234])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[234].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [234]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[234].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[234].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[234].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[234].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [235])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[235].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [235]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[235].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[235].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[235].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[235].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [236])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[236].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [236]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[236].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[236].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[236].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[236].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [237])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[237].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [237]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[237].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[237].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[237].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[237].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [238])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[238].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [238]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[238].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[238].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[238].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[238].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [239])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[239].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [239]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[239].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[239].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[239].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[239].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [240])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[240].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [240]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[240].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[240].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[240].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[240].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [241])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[241].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [241]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[241].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[241].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[241].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[241].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [242])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[242].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [242]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[242].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[242].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[242].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[242].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [243])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[243].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [243]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[243].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[243].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[243].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[243].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [244])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[244].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [244]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[244].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[244].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[244].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[244].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [245])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[245].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [245]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[245].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[245].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[245].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[245].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [246])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[246].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [246]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[246].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[246].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[246].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[246].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [247])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[247].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [247]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[247].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[247].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[247].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[247].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [248])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[248].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [248]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[248].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[248].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[248].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[248].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [249])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[249].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [249]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[249].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[249].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[249].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[249].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [250])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[250].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [250]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[250].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[250].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[250].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[250].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [251])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[251].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [251]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[251].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[251].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[251].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[251].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [252])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[252].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [252]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[252].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[252].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[252].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[252].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [253])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[253].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [253]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[253].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[253].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[253].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[253].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [254])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[254].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [254]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[254].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[254].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[254].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[254].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [255])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\U0/I_VIO/GEN_SYNC_OUT[255].SYNC_OUT_CELL/I_SRL_T2.U_SRL (
.A0(\U0/I_VIO/addr [0]),
.A1(\U0/I_VIO/addr [1]),
.A2(\U0/I_VIO/addr [2]),
.A3(\U0/I_VIO/addr [3]),
.CE(CONTROL[5]),
.CLK(CONTROL[0]),
.D(\U0/I_VIO/OUTPUT_SHIFT [255]),
.Q(\U0/I_VIO/GEN_SYNC_OUT[255].SYNC_OUT_CELL/out_temp ),
.Q15(\U0/I_VIO/GEN_SYNC_OUT[255].SYNC_OUT_CELL/SHIFT_OUT_temp )
);
LUT2 #(
.INIT ( 4'h8 ))
\U0/I_VIO/GEN_SYNC_OUT[255].SYNC_OUT_CELL/LUT_OUT (
.I0(CONTROL[5]),
.I1(\U0/I_VIO/GEN_SYNC_OUT[255].SYNC_OUT_CELL/SHIFT_OUT_temp ),
.O(\U0/I_VIO/OUTPUT_SHIFT [256])
);
LUT2 #(
.INIT ( 4'h2 ))
\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/LUT_OUT (
.I0(\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/arm_dly2 ),
.I1(\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/arm_dly1 ),
.O(\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/cnt_reset )
);
LUT4 #(
.INIT ( 16'h7FFF ))
\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/LUT_CE (
.I0(\U0/I_VIO/addr [0]),
.I1(\U0/I_VIO/addr [1]),
.I2(\U0/I_VIO/addr [2]),
.I3(\U0/I_VIO/addr [3]),
.O(\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/cnt_ce )
);
LUT2 #(
.INIT ( 4'h2 ))
\U0/I_VIO/GEN_TRANS.U_ARM/U_CLEAR (
.I0(\U0/I_VIO/GEN_TRANS.U_ARM/iDOUT_dly [1]),
.I1(CONTROL[6]),
.O(\U0/I_VIO/GEN_TRANS.U_ARM/iCLR )
);
LUT3 #(
.INIT ( 8'hCA ))
\U0/I_VIO/U_DOUT (
.I0(\U0/I_VIO/STAT_DOUT ),
.I1(\U0/I_VIO/DATA_DOUT ),
.I2(CONTROL[7]),
.O(CONTROL[3])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/reset_f_edge/U_DOUT0 (
.C(CONTROL[0]),
.CE(N0),
.D(CONTROL[7]),
.Q(\U0/I_VIO/reset_f_edge/iDOUT [0])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/reset_f_edge/U_DOUT1 (
.C(CONTROL[0]),
.CE(N0),
.D(\U0/I_VIO/reset_f_edge/iDOUT [0]),
.Q(\U0/I_VIO/reset_f_edge/iDOUT [1])
);
FDR #(
.INIT ( 1'b0 ))
\U0/I_VIO/reset_f_edge/I_H2L.U_DOUT (
.C(CONTROL[0]),
.D(\U0/I_VIO/reset_f_edge/iDOUT [1]),
.R(\U0/I_VIO/reset_f_edge/iDOUT [0]),
.Q(\NLW_U0/I_VIO/reset_f_edge/I_H2L.U_DOUT_Q_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[256].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [256]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [257])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[256].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [257]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [0])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[257].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [257]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [258])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[257].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [258]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [1])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[258].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [258]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [259])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[258].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [259]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [2])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[259].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [259]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [260])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[259].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [260]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [3])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[260].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [260]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [261])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[260].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [261]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [4])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[261].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [261]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [262])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[261].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [262]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [5])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[262].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [262]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [263])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[262].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [263]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [6])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[263].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [263]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [264])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[263].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [264]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [7])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[264].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [264]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [265])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[264].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [265]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [8])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[265].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [265]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [266])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[265].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [266]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [9])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[266].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [266]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [267])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[266].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [267]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [10])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[267].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [267]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [268])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[267].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [268]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [11])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[268].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [268]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [269])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[268].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [269]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [12])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[269].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [269]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [270])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[269].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [270]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [13])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[270].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [270]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [271])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[270].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [271]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [14])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[271].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [271]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [272])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[271].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [272]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [15])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[272].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [272]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [273])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[272].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [273]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [16])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[273].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [273]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [274])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[273].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [274]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [17])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[274].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [274]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [275])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[274].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [275]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [18])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[275].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [275]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [276])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[275].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [276]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [19])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[276].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [276]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [277])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[276].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [277]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [20])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[277].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [277]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [278])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[277].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [278]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [21])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[278].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [278]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [279])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[278].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [279]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [22])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[279].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [279]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [280])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[279].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [280]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [23])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[280].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [280]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [281])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[280].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [281]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [24])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[281].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [281]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [282])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[281].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [282]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [25])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[282].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [282]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [283])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[282].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [283]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [26])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[283].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [283]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [284])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[283].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [284]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [27])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[284].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [284]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [285])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[284].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [285]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [28])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[285].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [285]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [286])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[285].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [286]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [29])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[286].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [286]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [287])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[286].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [287]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [30])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[287].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [287]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [288])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[287].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [288]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [31])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[288].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [288]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [289])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[288].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [289]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [32])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[289].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [289]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [290])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[289].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [290]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [33])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[290].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [290]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [291])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[290].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [291]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [34])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[291].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [291]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [292])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[291].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [292]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [35])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[292].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [292]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [293])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[292].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [293]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [36])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[293].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [293]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [294])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[293].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [294]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [37])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[294].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [294]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [295])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[294].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [295]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [38])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[295].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [295]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [296])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[295].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [296]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [39])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[296].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [296]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [297])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[296].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [297]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [40])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[297].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [297]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [298])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[297].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [298]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [41])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[298].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [298]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [299])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[298].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [299]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [42])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[299].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [299]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [300])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[299].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [300]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [43])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[300].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [300]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [301])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[300].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [301]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [44])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[301].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [301]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [302])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[301].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [302]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [45])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[302].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [302]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [303])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[302].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [303]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [46])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[303].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [303]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [304])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[303].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [304]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [47])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[304].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [304]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [305])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[304].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [305]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [48])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[305].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [305]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [306])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[305].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [306]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [49])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[306].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [306]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [307])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[306].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [307]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [50])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[307].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [307]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [308])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[307].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [308]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [51])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[308].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [308]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [309])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[308].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [309]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [52])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[309].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [309]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [310])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[309].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [310]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [53])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[310].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [310]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [311])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[310].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [311]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [54])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[311].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [311]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [312])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[311].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [312]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [55])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[312].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [312]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [313])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[312].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [313]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [56])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[313].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [313]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [314])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[313].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [314]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [57])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[314].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [314]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [315])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[314].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [315]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [58])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[315].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [315]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [316])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[315].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [316]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [59])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[316].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [316]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [317])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[316].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [317]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [60])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[317].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [317]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [318])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[317].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [318]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [61])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[318].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [318]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [319])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[318].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [319]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [62])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[319].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [319]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [320])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[319].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [320]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [63])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[320].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [320]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [321])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[320].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [321]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [64])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[321].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [321]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [322])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[321].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [322]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [65])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[322].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [322]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [323])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[322].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [323]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [66])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[323].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [323]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [324])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[323].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [324]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [67])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[324].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [324]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [325])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[324].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [325]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [68])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[325].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [325]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [326])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[325].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [326]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [69])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[326].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [326]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [327])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[326].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [327]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [70])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[327].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [327]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [328])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[327].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [328]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [71])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[328].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [328]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [329])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[328].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [329]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [72])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[329].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [329]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [330])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[329].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [330]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [73])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[330].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [330]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [331])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[330].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [331]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [74])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[331].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [331]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [332])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[331].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [332]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [75])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[332].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [332]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [333])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[332].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [333]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [76])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[333].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [333]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [334])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[333].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [334]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [77])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[334].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [334]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [335])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[334].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [335]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [78])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[335].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [335]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [336])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[335].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [336]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [79])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[336].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [336]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [337])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[336].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [337]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [80])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[337].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [337]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [338])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[337].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [338]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [81])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[338].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [338]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [339])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[338].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [339]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [82])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[339].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [339]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [340])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[339].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [340]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [83])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[340].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [340]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [341])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[340].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [341]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [84])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[341].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [341]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [342])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[341].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [342]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [85])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[342].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [342]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [343])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[342].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [343]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [86])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[343].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [343]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [344])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[343].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [344]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [87])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[344].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [344]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [345])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[344].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [345]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [88])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[345].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [345]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [346])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[345].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [346]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [89])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[346].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [346]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [347])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[346].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [347]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [90])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[347].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [347]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [348])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[347].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [348]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [91])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[348].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [348]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [349])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[348].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [349]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [92])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[349].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [349]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [350])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[349].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [350]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [93])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[350].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [350]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [351])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[350].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [351]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [94])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[351].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [351]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [352])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[351].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [352]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [95])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[352].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [352]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [353])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[352].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [353]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [96])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[353].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [353]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [354])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[353].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [354]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [97])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[354].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [354]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [355])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[354].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [355]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [98])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[355].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [355]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [356])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[355].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [356]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [99])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[356].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [356]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [357])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[356].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [357]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [100])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[357].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [357]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [358])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[357].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [358]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [101])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[358].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [358]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [359])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[358].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [359]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [102])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[359].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [359]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [360])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[359].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [360]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [103])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[360].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [360]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [361])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[360].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [361]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [104])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[361].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [361]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [362])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[361].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [362]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [105])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[362].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [362]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [363])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[362].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [363]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [106])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[363].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [363]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [364])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[363].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [364]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [107])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[364].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [364]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [365])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[364].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [365]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [108])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[365].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [365]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [366])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[365].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [366]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [109])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[366].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [366]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [367])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[366].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [367]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [110])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[367].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [367]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [368])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[367].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [368]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [111])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[368].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [368]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [369])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[368].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [369]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [112])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[369].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [369]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [370])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[369].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [370]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [113])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[370].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [370]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [371])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[370].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [371]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [114])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[371].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [371]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [372])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[371].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [372]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [115])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[372].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [372]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [373])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[372].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [373]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [116])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[373].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [373]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [374])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[373].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [374]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [117])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[374].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [374]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [375])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[374].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [375]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [118])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[375].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [375]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [376])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[375].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [376]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [119])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[376].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [376]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [377])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[376].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [377]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [120])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[377].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [377]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [378])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[377].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [378]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [121])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[378].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [378]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [379])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[378].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [379]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [122])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[379].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [379]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [380])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[379].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [380]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [123])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[380].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [380]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [381])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[380].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [381]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [124])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[381].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [381]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [382])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[381].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [382]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [125])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[382].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [382]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [383])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[382].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [383]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [126])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[383].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [383]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [384])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[383].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [384]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [127])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[384].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [384]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [385])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[384].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [385]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [128])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[385].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [385]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [386])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[385].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [386]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [129])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[386].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [386]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [387])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[386].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [387]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [130])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[387].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [387]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [388])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[387].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [388]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [131])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[388].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [388]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [389])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[388].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [389]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [132])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[389].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [389]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [390])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[389].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [390]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [133])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[390].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [390]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [391])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[390].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [391]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [134])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[391].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [391]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [392])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[391].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [392]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [135])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[392].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [392]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [393])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[392].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [393]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [136])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[393].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [393]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [394])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[393].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [394]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [137])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[394].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [394]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [395])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[394].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [395]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [138])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[395].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [395]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [396])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[395].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [396]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [139])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[396].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [396]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [397])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[396].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [397]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [140])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[397].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [397]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [398])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[397].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [398]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [141])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[398].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [398]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [399])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[398].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [399]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [142])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[399].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [399]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [400])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[399].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [400]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [143])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[400].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [400]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [401])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[400].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [401]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [144])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[401].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [401]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [402])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[401].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [402]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [145])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[402].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [402]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [403])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[402].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [403]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [146])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[403].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [403]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [404])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[403].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [404]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [147])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[404].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [404]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [405])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[404].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [405]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [148])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[405].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [405]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [406])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[405].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [406]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [149])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[406].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [406]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [407])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[406].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [407]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [150])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[407].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [407]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [408])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[407].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [408]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [151])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[408].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [408]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [409])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[408].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [409]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [152])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[409].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [409]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [410])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[409].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [410]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [153])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[410].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [410]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [411])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[410].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [411]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [154])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[411].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [411]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [412])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[411].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [412]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [155])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[412].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [412]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [413])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[412].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [413]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [156])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[413].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [413]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [414])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[413].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [414]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [157])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[414].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [414]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [415])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[414].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [415]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [158])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[415].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [415]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [416])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[415].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [416]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [159])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[416].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [416]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [417])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[416].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [417]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [160])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[417].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [417]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [418])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[417].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [418]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [161])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[418].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [418]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [419])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[418].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [419]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [162])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[419].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [419]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [420])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[419].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [420]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [163])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[420].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [420]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [421])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[420].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [421]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [164])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[421].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [421]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [422])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[421].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [422]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [165])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[422].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [422]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [423])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[422].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [423]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [166])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[423].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [423]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [424])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[423].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [424]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [167])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[424].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [424]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [425])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[424].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [425]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [168])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[425].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [425]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [426])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[425].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [426]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [169])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[426].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [426]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [427])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[426].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [427]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [170])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[427].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [427]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [428])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[427].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [428]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [171])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[428].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [428]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [429])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[428].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [429]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [172])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[429].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [429]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [430])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[429].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [430]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [173])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[430].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [430]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [431])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[430].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [431]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [174])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[431].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [431]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [432])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[431].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [432]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [175])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[432].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [432]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [433])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[432].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [433]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [176])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[433].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [433]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [434])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[433].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [434]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [177])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[434].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [434]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [435])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[434].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [435]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [178])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[435].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [435]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [436])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[435].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [436]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [179])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[436].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [436]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [437])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[436].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [437]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [180])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[437].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [437]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [438])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[437].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [438]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [181])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[438].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [438]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [439])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[438].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [439]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [182])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[439].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [439]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [440])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[439].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [440]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [183])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[440].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [440]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [441])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[440].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [441]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [184])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[441].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [441]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [442])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[441].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [442]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [185])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[442].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [442]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [443])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[442].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [443]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [186])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[443].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [443]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [444])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[443].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [444]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [187])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[444].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [444]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [445])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[444].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [445]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [188])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[445].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [445]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [446])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[445].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [446]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [189])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[446].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [446]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [447])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[446].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [447]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [190])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[447].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [447]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [448])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[447].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [448]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [191])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[448].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [448]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [449])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[448].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [449]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [192])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[449].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [449]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [450])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[449].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [450]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [193])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[450].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [450]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [451])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[450].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [451]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [194])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[451].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [451]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [452])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[451].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [452]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [195])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[452].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [452]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [453])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[452].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [453]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [196])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[453].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [453]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [454])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[453].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [454]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [197])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[454].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [454]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [455])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[454].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [455]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [198])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[455].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [455]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [456])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[455].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [456]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [199])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[456].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [456]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [457])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[456].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [457]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [200])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[457].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [457]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [458])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[457].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [458]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [201])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[458].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [458]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [459])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[458].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [459]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [202])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[459].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [459]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [460])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[459].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [460]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [203])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[460].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [460]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [461])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[460].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [461]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [204])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[461].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [461]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [462])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[461].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [462]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [205])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[462].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [462]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [463])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[462].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [463]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [206])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[463].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [463]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [464])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[463].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [464]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [207])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[464].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [464]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [465])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[464].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [465]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [208])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[465].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [465]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [466])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[465].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [466]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [209])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[466].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [466]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [467])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[466].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [467]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [210])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[467].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [467]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [468])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[467].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [468]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [211])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[468].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [468]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [469])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[468].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [469]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [212])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[469].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [469]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [470])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[469].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [470]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [213])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[470].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [470]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [471])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[470].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [471]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [214])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[471].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [471]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [472])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[471].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [472]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [215])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[472].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [472]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [473])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[472].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [473]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [216])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[473].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [473]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [474])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[473].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [474]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [217])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[474].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [474]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [475])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[474].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [475]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [218])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[475].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [475]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [476])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[475].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [476]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [219])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[476].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [476]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [477])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[476].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [477]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [220])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[477].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [477]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [478])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[477].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [478]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [221])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[478].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [478]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [479])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[478].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [479]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [222])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[479].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [479]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [480])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[479].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [480]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [223])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[480].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [480]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [481])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[480].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [481]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [224])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[481].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [481]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [482])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[481].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [482]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [225])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[482].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [482]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [483])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[482].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [483]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [226])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[483].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [483]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [484])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[483].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [484]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [227])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[484].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [484]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [485])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[484].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [485]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [228])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[485].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [485]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [486])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[485].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [486]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [229])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[486].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [486]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [487])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[486].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [487]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [230])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[487].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [487]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [488])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[487].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [488]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [231])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[488].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [488]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [489])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[488].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [489]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [232])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[489].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [489]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [490])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[489].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [490]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [233])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[490].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [490]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [491])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[490].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [491]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [234])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[491].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [491]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [492])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[491].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [492]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [235])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[492].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [492]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [493])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[492].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [493]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [236])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[493].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [493]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [494])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[493].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [494]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [237])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[494].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [494]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [495])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[494].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [495]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [238])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[495].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [495]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [496])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[495].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [496]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [239])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[496].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [496]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [497])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[496].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [497]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [240])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[497].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [497]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [498])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[497].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [498]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [241])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[498].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [498]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [499])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[498].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [499]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [242])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[499].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [499]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [500])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[499].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [500]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [243])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[500].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [500]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [501])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[500].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [501]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [244])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[501].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [501]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [502])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[501].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [502]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [245])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[502].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [502]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [503])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[502].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [503]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [246])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[503].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [503]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [504])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[503].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [504]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [247])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[504].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [504]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [505])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[504].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [505]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [248])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[505].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [505]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [506])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[505].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [506]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [249])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[506].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [506]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [507])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[506].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [507]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [250])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[507].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [507]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [508])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[507].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [508]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [251])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[508].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [508]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [509])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[508].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [509]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [252])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[509].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [509]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [510])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[509].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [510]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [253])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[510].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [510]),
.Q(\U0/I_VIO/OUTPUT_SHIFT [511])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[510].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/OUTPUT_SHIFT [511]),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [254])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[511].UPDATE_CELL/SHIFT_REG (
.C(CONTROL[0]),
.CE(CONTROL[5]),
.D(\U0/I_VIO/OUTPUT_SHIFT [511]),
.Q(\U0/I_VIO/GEN_UPDATE_OUT[511].UPDATE_CELL/out_temp )
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_UPDATE_OUT[511].UPDATE_CELL/GEN_CLK.USER_REG (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.D(\U0/I_VIO/GEN_UPDATE_OUT[511].UPDATE_CELL/out_temp ),
.R(CONTROL[5]),
.Q(\U0/I_VIO/UPDATE [255])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[0].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [0]),
.D(\U0/I_VIO/GEN_SYNC_OUT[0].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[0])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[1].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [1]),
.D(\U0/I_VIO/GEN_SYNC_OUT[1].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[1])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[2].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [2]),
.D(\U0/I_VIO/GEN_SYNC_OUT[2].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[2])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[3].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [3]),
.D(\U0/I_VIO/GEN_SYNC_OUT[3].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[3])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[4].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [4]),
.D(\U0/I_VIO/GEN_SYNC_OUT[4].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[4])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[5].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [5]),
.D(\U0/I_VIO/GEN_SYNC_OUT[5].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[5])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[6].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [6]),
.D(\U0/I_VIO/GEN_SYNC_OUT[6].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[6])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[7].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [7]),
.D(\U0/I_VIO/GEN_SYNC_OUT[7].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[7])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[8].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [8]),
.D(\U0/I_VIO/GEN_SYNC_OUT[8].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[8])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[9].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [9]),
.D(\U0/I_VIO/GEN_SYNC_OUT[9].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[9])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[10].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [10]),
.D(\U0/I_VIO/GEN_SYNC_OUT[10].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[10])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[11].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [11]),
.D(\U0/I_VIO/GEN_SYNC_OUT[11].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[11])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[12].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [12]),
.D(\U0/I_VIO/GEN_SYNC_OUT[12].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[12])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[13].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [13]),
.D(\U0/I_VIO/GEN_SYNC_OUT[13].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[13])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[14].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [14]),
.D(\U0/I_VIO/GEN_SYNC_OUT[14].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[14])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[15].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [15]),
.D(\U0/I_VIO/GEN_SYNC_OUT[15].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[15])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[16].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [16]),
.D(\U0/I_VIO/GEN_SYNC_OUT[16].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[16])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[17].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [17]),
.D(\U0/I_VIO/GEN_SYNC_OUT[17].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[17])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[18].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [18]),
.D(\U0/I_VIO/GEN_SYNC_OUT[18].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[18])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[19].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [19]),
.D(\U0/I_VIO/GEN_SYNC_OUT[19].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[19])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[20].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [20]),
.D(\U0/I_VIO/GEN_SYNC_OUT[20].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[20])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[21].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [21]),
.D(\U0/I_VIO/GEN_SYNC_OUT[21].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[21])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[22].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [22]),
.D(\U0/I_VIO/GEN_SYNC_OUT[22].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[22])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[23].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [23]),
.D(\U0/I_VIO/GEN_SYNC_OUT[23].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[23])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[24].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [24]),
.D(\U0/I_VIO/GEN_SYNC_OUT[24].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[24])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[25].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [25]),
.D(\U0/I_VIO/GEN_SYNC_OUT[25].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[25])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[26].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [26]),
.D(\U0/I_VIO/GEN_SYNC_OUT[26].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[26])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[27].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [27]),
.D(\U0/I_VIO/GEN_SYNC_OUT[27].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[27])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[28].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [28]),
.D(\U0/I_VIO/GEN_SYNC_OUT[28].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[28])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[29].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [29]),
.D(\U0/I_VIO/GEN_SYNC_OUT[29].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[29])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[30].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [30]),
.D(\U0/I_VIO/GEN_SYNC_OUT[30].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[30])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[31].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [31]),
.D(\U0/I_VIO/GEN_SYNC_OUT[31].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[31])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[32].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [32]),
.D(\U0/I_VIO/GEN_SYNC_OUT[32].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[32])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[33].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [33]),
.D(\U0/I_VIO/GEN_SYNC_OUT[33].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[33])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[34].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [34]),
.D(\U0/I_VIO/GEN_SYNC_OUT[34].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[34])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[35].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [35]),
.D(\U0/I_VIO/GEN_SYNC_OUT[35].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[35])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[36].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [36]),
.D(\U0/I_VIO/GEN_SYNC_OUT[36].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[36])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[37].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [37]),
.D(\U0/I_VIO/GEN_SYNC_OUT[37].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[37])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[38].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [38]),
.D(\U0/I_VIO/GEN_SYNC_OUT[38].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[38])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[39].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [39]),
.D(\U0/I_VIO/GEN_SYNC_OUT[39].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[39])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[40].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [40]),
.D(\U0/I_VIO/GEN_SYNC_OUT[40].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[40])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[41].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [41]),
.D(\U0/I_VIO/GEN_SYNC_OUT[41].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[41])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[42].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [42]),
.D(\U0/I_VIO/GEN_SYNC_OUT[42].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[42])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[43].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [43]),
.D(\U0/I_VIO/GEN_SYNC_OUT[43].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[43])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[44].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [44]),
.D(\U0/I_VIO/GEN_SYNC_OUT[44].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[44])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[45].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [45]),
.D(\U0/I_VIO/GEN_SYNC_OUT[45].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[45])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[46].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [46]),
.D(\U0/I_VIO/GEN_SYNC_OUT[46].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[46])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[47].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [47]),
.D(\U0/I_VIO/GEN_SYNC_OUT[47].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[47])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[48].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [48]),
.D(\U0/I_VIO/GEN_SYNC_OUT[48].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[48])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[49].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [49]),
.D(\U0/I_VIO/GEN_SYNC_OUT[49].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[49])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[50].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [50]),
.D(\U0/I_VIO/GEN_SYNC_OUT[50].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[50])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[51].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [51]),
.D(\U0/I_VIO/GEN_SYNC_OUT[51].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[51])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[52].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [52]),
.D(\U0/I_VIO/GEN_SYNC_OUT[52].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[52])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[53].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [53]),
.D(\U0/I_VIO/GEN_SYNC_OUT[53].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[53])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[54].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [54]),
.D(\U0/I_VIO/GEN_SYNC_OUT[54].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[54])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[55].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [55]),
.D(\U0/I_VIO/GEN_SYNC_OUT[55].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[55])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[56].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [56]),
.D(\U0/I_VIO/GEN_SYNC_OUT[56].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[56])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[57].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [57]),
.D(\U0/I_VIO/GEN_SYNC_OUT[57].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[57])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[58].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [58]),
.D(\U0/I_VIO/GEN_SYNC_OUT[58].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[58])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[59].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [59]),
.D(\U0/I_VIO/GEN_SYNC_OUT[59].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[59])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[60].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [60]),
.D(\U0/I_VIO/GEN_SYNC_OUT[60].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[60])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[61].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [61]),
.D(\U0/I_VIO/GEN_SYNC_OUT[61].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[61])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[62].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [62]),
.D(\U0/I_VIO/GEN_SYNC_OUT[62].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[62])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[63].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [63]),
.D(\U0/I_VIO/GEN_SYNC_OUT[63].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[63])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[64].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [64]),
.D(\U0/I_VIO/GEN_SYNC_OUT[64].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[64])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[65].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [65]),
.D(\U0/I_VIO/GEN_SYNC_OUT[65].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[65])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[66].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [66]),
.D(\U0/I_VIO/GEN_SYNC_OUT[66].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[66])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[67].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [67]),
.D(\U0/I_VIO/GEN_SYNC_OUT[67].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[67])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[68].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [68]),
.D(\U0/I_VIO/GEN_SYNC_OUT[68].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[68])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[69].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [69]),
.D(\U0/I_VIO/GEN_SYNC_OUT[69].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[69])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[70].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [70]),
.D(\U0/I_VIO/GEN_SYNC_OUT[70].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[70])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[71].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [71]),
.D(\U0/I_VIO/GEN_SYNC_OUT[71].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[71])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[72].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [72]),
.D(\U0/I_VIO/GEN_SYNC_OUT[72].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[72])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[73].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [73]),
.D(\U0/I_VIO/GEN_SYNC_OUT[73].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[73])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[74].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [74]),
.D(\U0/I_VIO/GEN_SYNC_OUT[74].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[74])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[75].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [75]),
.D(\U0/I_VIO/GEN_SYNC_OUT[75].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[75])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[76].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [76]),
.D(\U0/I_VIO/GEN_SYNC_OUT[76].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[76])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[77].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [77]),
.D(\U0/I_VIO/GEN_SYNC_OUT[77].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[77])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[78].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [78]),
.D(\U0/I_VIO/GEN_SYNC_OUT[78].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[78])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[79].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [79]),
.D(\U0/I_VIO/GEN_SYNC_OUT[79].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[79])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[80].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [80]),
.D(\U0/I_VIO/GEN_SYNC_OUT[80].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[80])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[81].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [81]),
.D(\U0/I_VIO/GEN_SYNC_OUT[81].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[81])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[82].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [82]),
.D(\U0/I_VIO/GEN_SYNC_OUT[82].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[82])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[83].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [83]),
.D(\U0/I_VIO/GEN_SYNC_OUT[83].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[83])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[84].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [84]),
.D(\U0/I_VIO/GEN_SYNC_OUT[84].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[84])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[85].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [85]),
.D(\U0/I_VIO/GEN_SYNC_OUT[85].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[85])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[86].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [86]),
.D(\U0/I_VIO/GEN_SYNC_OUT[86].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[86])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[87].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [87]),
.D(\U0/I_VIO/GEN_SYNC_OUT[87].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[87])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[88].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [88]),
.D(\U0/I_VIO/GEN_SYNC_OUT[88].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[88])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[89].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [89]),
.D(\U0/I_VIO/GEN_SYNC_OUT[89].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[89])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[90].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [90]),
.D(\U0/I_VIO/GEN_SYNC_OUT[90].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[90])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[91].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [91]),
.D(\U0/I_VIO/GEN_SYNC_OUT[91].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[91])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[92].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [92]),
.D(\U0/I_VIO/GEN_SYNC_OUT[92].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[92])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[93].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [93]),
.D(\U0/I_VIO/GEN_SYNC_OUT[93].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[93])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[94].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [94]),
.D(\U0/I_VIO/GEN_SYNC_OUT[94].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[94])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[95].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [95]),
.D(\U0/I_VIO/GEN_SYNC_OUT[95].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[95])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[96].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [96]),
.D(\U0/I_VIO/GEN_SYNC_OUT[96].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[96])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[97].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [97]),
.D(\U0/I_VIO/GEN_SYNC_OUT[97].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[97])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[98].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [98]),
.D(\U0/I_VIO/GEN_SYNC_OUT[98].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[98])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[99].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [99]),
.D(\U0/I_VIO/GEN_SYNC_OUT[99].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[99])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[100].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [100]),
.D(\U0/I_VIO/GEN_SYNC_OUT[100].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[100])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[101].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [101]),
.D(\U0/I_VIO/GEN_SYNC_OUT[101].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[101])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[102].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [102]),
.D(\U0/I_VIO/GEN_SYNC_OUT[102].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[102])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[103].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [103]),
.D(\U0/I_VIO/GEN_SYNC_OUT[103].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[103])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[104].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [104]),
.D(\U0/I_VIO/GEN_SYNC_OUT[104].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[104])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[105].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [105]),
.D(\U0/I_VIO/GEN_SYNC_OUT[105].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[105])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[106].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [106]),
.D(\U0/I_VIO/GEN_SYNC_OUT[106].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[106])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[107].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [107]),
.D(\U0/I_VIO/GEN_SYNC_OUT[107].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[107])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[108].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [108]),
.D(\U0/I_VIO/GEN_SYNC_OUT[108].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[108])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[109].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [109]),
.D(\U0/I_VIO/GEN_SYNC_OUT[109].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[109])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[110].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [110]),
.D(\U0/I_VIO/GEN_SYNC_OUT[110].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[110])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[111].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [111]),
.D(\U0/I_VIO/GEN_SYNC_OUT[111].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[111])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[112].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [112]),
.D(\U0/I_VIO/GEN_SYNC_OUT[112].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[112])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[113].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [113]),
.D(\U0/I_VIO/GEN_SYNC_OUT[113].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[113])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[114].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [114]),
.D(\U0/I_VIO/GEN_SYNC_OUT[114].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[114])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[115].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [115]),
.D(\U0/I_VIO/GEN_SYNC_OUT[115].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[115])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[116].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [116]),
.D(\U0/I_VIO/GEN_SYNC_OUT[116].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[116])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[117].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [117]),
.D(\U0/I_VIO/GEN_SYNC_OUT[117].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[117])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[118].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [118]),
.D(\U0/I_VIO/GEN_SYNC_OUT[118].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[118])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[119].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [119]),
.D(\U0/I_VIO/GEN_SYNC_OUT[119].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[119])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[120].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [120]),
.D(\U0/I_VIO/GEN_SYNC_OUT[120].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[120])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[121].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [121]),
.D(\U0/I_VIO/GEN_SYNC_OUT[121].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[121])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[122].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [122]),
.D(\U0/I_VIO/GEN_SYNC_OUT[122].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[122])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[123].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [123]),
.D(\U0/I_VIO/GEN_SYNC_OUT[123].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[123])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[124].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [124]),
.D(\U0/I_VIO/GEN_SYNC_OUT[124].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[124])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[125].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [125]),
.D(\U0/I_VIO/GEN_SYNC_OUT[125].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[125])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[126].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [126]),
.D(\U0/I_VIO/GEN_SYNC_OUT[126].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[126])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[127].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [127]),
.D(\U0/I_VIO/GEN_SYNC_OUT[127].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[127])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[128].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [128]),
.D(\U0/I_VIO/GEN_SYNC_OUT[128].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[128])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[129].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [129]),
.D(\U0/I_VIO/GEN_SYNC_OUT[129].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[129])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[130].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [130]),
.D(\U0/I_VIO/GEN_SYNC_OUT[130].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[130])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[131].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [131]),
.D(\U0/I_VIO/GEN_SYNC_OUT[131].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[131])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[132].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [132]),
.D(\U0/I_VIO/GEN_SYNC_OUT[132].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[132])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[133].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [133]),
.D(\U0/I_VIO/GEN_SYNC_OUT[133].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[133])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[134].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [134]),
.D(\U0/I_VIO/GEN_SYNC_OUT[134].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[134])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[135].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [135]),
.D(\U0/I_VIO/GEN_SYNC_OUT[135].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[135])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[136].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [136]),
.D(\U0/I_VIO/GEN_SYNC_OUT[136].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[136])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[137].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [137]),
.D(\U0/I_VIO/GEN_SYNC_OUT[137].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[137])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[138].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [138]),
.D(\U0/I_VIO/GEN_SYNC_OUT[138].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[138])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[139].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [139]),
.D(\U0/I_VIO/GEN_SYNC_OUT[139].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[139])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[140].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [140]),
.D(\U0/I_VIO/GEN_SYNC_OUT[140].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[140])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[141].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [141]),
.D(\U0/I_VIO/GEN_SYNC_OUT[141].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[141])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[142].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [142]),
.D(\U0/I_VIO/GEN_SYNC_OUT[142].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[142])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[143].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [143]),
.D(\U0/I_VIO/GEN_SYNC_OUT[143].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[143])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[144].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [144]),
.D(\U0/I_VIO/GEN_SYNC_OUT[144].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[144])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[145].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [145]),
.D(\U0/I_VIO/GEN_SYNC_OUT[145].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[145])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[146].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [146]),
.D(\U0/I_VIO/GEN_SYNC_OUT[146].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[146])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[147].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [147]),
.D(\U0/I_VIO/GEN_SYNC_OUT[147].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[147])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[148].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [148]),
.D(\U0/I_VIO/GEN_SYNC_OUT[148].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[148])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[149].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [149]),
.D(\U0/I_VIO/GEN_SYNC_OUT[149].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[149])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[150].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [150]),
.D(\U0/I_VIO/GEN_SYNC_OUT[150].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[150])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[151].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [151]),
.D(\U0/I_VIO/GEN_SYNC_OUT[151].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[151])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[152].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [152]),
.D(\U0/I_VIO/GEN_SYNC_OUT[152].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[152])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[153].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [153]),
.D(\U0/I_VIO/GEN_SYNC_OUT[153].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[153])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[154].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [154]),
.D(\U0/I_VIO/GEN_SYNC_OUT[154].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[154])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[155].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [155]),
.D(\U0/I_VIO/GEN_SYNC_OUT[155].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[155])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[156].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [156]),
.D(\U0/I_VIO/GEN_SYNC_OUT[156].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[156])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[157].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [157]),
.D(\U0/I_VIO/GEN_SYNC_OUT[157].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[157])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[158].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [158]),
.D(\U0/I_VIO/GEN_SYNC_OUT[158].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[158])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[159].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [159]),
.D(\U0/I_VIO/GEN_SYNC_OUT[159].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[159])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[160].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [160]),
.D(\U0/I_VIO/GEN_SYNC_OUT[160].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[160])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[161].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [161]),
.D(\U0/I_VIO/GEN_SYNC_OUT[161].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[161])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[162].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [162]),
.D(\U0/I_VIO/GEN_SYNC_OUT[162].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[162])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[163].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [163]),
.D(\U0/I_VIO/GEN_SYNC_OUT[163].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[163])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[164].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [164]),
.D(\U0/I_VIO/GEN_SYNC_OUT[164].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[164])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[165].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [165]),
.D(\U0/I_VIO/GEN_SYNC_OUT[165].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[165])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[166].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [166]),
.D(\U0/I_VIO/GEN_SYNC_OUT[166].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[166])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[167].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [167]),
.D(\U0/I_VIO/GEN_SYNC_OUT[167].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[167])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[168].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [168]),
.D(\U0/I_VIO/GEN_SYNC_OUT[168].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[168])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[169].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [169]),
.D(\U0/I_VIO/GEN_SYNC_OUT[169].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[169])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[170].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [170]),
.D(\U0/I_VIO/GEN_SYNC_OUT[170].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[170])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[171].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [171]),
.D(\U0/I_VIO/GEN_SYNC_OUT[171].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[171])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[172].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [172]),
.D(\U0/I_VIO/GEN_SYNC_OUT[172].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[172])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[173].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [173]),
.D(\U0/I_VIO/GEN_SYNC_OUT[173].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[173])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[174].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [174]),
.D(\U0/I_VIO/GEN_SYNC_OUT[174].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[174])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[175].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [175]),
.D(\U0/I_VIO/GEN_SYNC_OUT[175].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[175])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[176].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [176]),
.D(\U0/I_VIO/GEN_SYNC_OUT[176].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[176])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[177].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [177]),
.D(\U0/I_VIO/GEN_SYNC_OUT[177].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[177])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[178].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [178]),
.D(\U0/I_VIO/GEN_SYNC_OUT[178].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[178])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[179].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [179]),
.D(\U0/I_VIO/GEN_SYNC_OUT[179].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[179])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[180].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [180]),
.D(\U0/I_VIO/GEN_SYNC_OUT[180].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[180])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[181].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [181]),
.D(\U0/I_VIO/GEN_SYNC_OUT[181].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[181])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[182].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [182]),
.D(\U0/I_VIO/GEN_SYNC_OUT[182].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[182])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[183].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [183]),
.D(\U0/I_VIO/GEN_SYNC_OUT[183].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[183])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[184].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [184]),
.D(\U0/I_VIO/GEN_SYNC_OUT[184].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[184])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[185].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [185]),
.D(\U0/I_VIO/GEN_SYNC_OUT[185].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[185])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[186].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [186]),
.D(\U0/I_VIO/GEN_SYNC_OUT[186].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[186])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[187].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [187]),
.D(\U0/I_VIO/GEN_SYNC_OUT[187].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[187])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[188].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [188]),
.D(\U0/I_VIO/GEN_SYNC_OUT[188].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[188])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[189].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [189]),
.D(\U0/I_VIO/GEN_SYNC_OUT[189].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[189])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[190].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [190]),
.D(\U0/I_VIO/GEN_SYNC_OUT[190].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[190])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[191].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [191]),
.D(\U0/I_VIO/GEN_SYNC_OUT[191].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[191])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[192].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [192]),
.D(\U0/I_VIO/GEN_SYNC_OUT[192].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[192])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[193].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [193]),
.D(\U0/I_VIO/GEN_SYNC_OUT[193].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[193])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[194].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [194]),
.D(\U0/I_VIO/GEN_SYNC_OUT[194].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[194])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[195].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [195]),
.D(\U0/I_VIO/GEN_SYNC_OUT[195].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[195])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[196].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [196]),
.D(\U0/I_VIO/GEN_SYNC_OUT[196].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[196])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[197].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [197]),
.D(\U0/I_VIO/GEN_SYNC_OUT[197].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[197])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[198].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [198]),
.D(\U0/I_VIO/GEN_SYNC_OUT[198].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[198])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[199].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [199]),
.D(\U0/I_VIO/GEN_SYNC_OUT[199].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[199])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[200].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [200]),
.D(\U0/I_VIO/GEN_SYNC_OUT[200].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[200])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[201].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [201]),
.D(\U0/I_VIO/GEN_SYNC_OUT[201].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[201])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[202].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [202]),
.D(\U0/I_VIO/GEN_SYNC_OUT[202].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[202])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[203].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [203]),
.D(\U0/I_VIO/GEN_SYNC_OUT[203].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[203])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[204].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [204]),
.D(\U0/I_VIO/GEN_SYNC_OUT[204].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[204])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[205].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [205]),
.D(\U0/I_VIO/GEN_SYNC_OUT[205].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[205])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[206].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [206]),
.D(\U0/I_VIO/GEN_SYNC_OUT[206].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[206])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[207].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [207]),
.D(\U0/I_VIO/GEN_SYNC_OUT[207].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[207])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[208].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [208]),
.D(\U0/I_VIO/GEN_SYNC_OUT[208].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[208])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[209].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [209]),
.D(\U0/I_VIO/GEN_SYNC_OUT[209].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[209])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[210].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [210]),
.D(\U0/I_VIO/GEN_SYNC_OUT[210].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[210])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[211].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [211]),
.D(\U0/I_VIO/GEN_SYNC_OUT[211].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[211])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[212].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [212]),
.D(\U0/I_VIO/GEN_SYNC_OUT[212].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[212])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[213].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [213]),
.D(\U0/I_VIO/GEN_SYNC_OUT[213].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[213])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[214].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [214]),
.D(\U0/I_VIO/GEN_SYNC_OUT[214].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[214])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[215].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [215]),
.D(\U0/I_VIO/GEN_SYNC_OUT[215].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[215])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[216].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [216]),
.D(\U0/I_VIO/GEN_SYNC_OUT[216].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[216])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[217].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [217]),
.D(\U0/I_VIO/GEN_SYNC_OUT[217].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[217])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[218].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [218]),
.D(\U0/I_VIO/GEN_SYNC_OUT[218].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[218])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[219].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [219]),
.D(\U0/I_VIO/GEN_SYNC_OUT[219].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[219])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[220].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [220]),
.D(\U0/I_VIO/GEN_SYNC_OUT[220].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[220])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[221].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [221]),
.D(\U0/I_VIO/GEN_SYNC_OUT[221].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[221])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[222].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [222]),
.D(\U0/I_VIO/GEN_SYNC_OUT[222].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[222])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[223].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [223]),
.D(\U0/I_VIO/GEN_SYNC_OUT[223].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[223])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[224].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [224]),
.D(\U0/I_VIO/GEN_SYNC_OUT[224].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[224])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[225].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [225]),
.D(\U0/I_VIO/GEN_SYNC_OUT[225].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[225])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[226].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [226]),
.D(\U0/I_VIO/GEN_SYNC_OUT[226].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[226])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[227].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [227]),
.D(\U0/I_VIO/GEN_SYNC_OUT[227].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[227])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[228].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [228]),
.D(\U0/I_VIO/GEN_SYNC_OUT[228].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[228])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[229].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [229]),
.D(\U0/I_VIO/GEN_SYNC_OUT[229].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[229])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[230].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [230]),
.D(\U0/I_VIO/GEN_SYNC_OUT[230].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[230])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[231].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [231]),
.D(\U0/I_VIO/GEN_SYNC_OUT[231].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[231])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[232].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [232]),
.D(\U0/I_VIO/GEN_SYNC_OUT[232].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[232])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[233].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [233]),
.D(\U0/I_VIO/GEN_SYNC_OUT[233].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[233])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[234].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [234]),
.D(\U0/I_VIO/GEN_SYNC_OUT[234].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[234])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[235].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [235]),
.D(\U0/I_VIO/GEN_SYNC_OUT[235].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[235])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[236].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [236]),
.D(\U0/I_VIO/GEN_SYNC_OUT[236].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[236])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[237].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [237]),
.D(\U0/I_VIO/GEN_SYNC_OUT[237].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[237])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[238].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [238]),
.D(\U0/I_VIO/GEN_SYNC_OUT[238].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[238])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[239].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [239]),
.D(\U0/I_VIO/GEN_SYNC_OUT[239].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[239])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[240].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [240]),
.D(\U0/I_VIO/GEN_SYNC_OUT[240].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[240])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[241].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [241]),
.D(\U0/I_VIO/GEN_SYNC_OUT[241].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[241])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[242].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [242]),
.D(\U0/I_VIO/GEN_SYNC_OUT[242].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[242])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[243].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [243]),
.D(\U0/I_VIO/GEN_SYNC_OUT[243].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[243])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[244].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [244]),
.D(\U0/I_VIO/GEN_SYNC_OUT[244].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[244])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[245].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [245]),
.D(\U0/I_VIO/GEN_SYNC_OUT[245].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[245])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[246].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [246]),
.D(\U0/I_VIO/GEN_SYNC_OUT[246].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[246])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[247].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [247]),
.D(\U0/I_VIO/GEN_SYNC_OUT[247].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[247])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[248].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [248]),
.D(\U0/I_VIO/GEN_SYNC_OUT[248].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[248])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[249].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [249]),
.D(\U0/I_VIO/GEN_SYNC_OUT[249].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[249])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[250].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [250]),
.D(\U0/I_VIO/GEN_SYNC_OUT[250].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[250])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[251].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [251]),
.D(\U0/I_VIO/GEN_SYNC_OUT[251].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[251])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[252].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [252]),
.D(\U0/I_VIO/GEN_SYNC_OUT[252].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[252])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[253].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [253]),
.D(\U0/I_VIO/GEN_SYNC_OUT[253].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[253])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[254].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [254]),
.D(\U0/I_VIO/GEN_SYNC_OUT[254].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[254])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT[255].SYNC_OUT_CELL/USER_REG (
.C(CLK),
.CE(\U0/I_VIO/UPDATE [255]),
.D(\U0/I_VIO/GEN_SYNC_OUT[255].SYNC_OUT_CELL/out_temp ),
.Q(SYNC_OUT[255])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/DLY1_REG (
.C(CLK),
.CE(N0),
.D(\U0/I_VIO/ARM_pulse ),
.Q(\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/arm_dly1 )
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/DLY2_REG (
.C(CLK),
.CE(N0),
.D(\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/arm_dly1 ),
.Q(\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/arm_dly2 )
);
FDCE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_TRANS.U_ARM/U_TFDRE (
.C(CONTROL[0]),
.CE(CONTROL[6]),
.CLR(\U0/I_VIO/GEN_TRANS.U_ARM/iCLR ),
.D(CONTROL[6]),
.Q(\U0/I_VIO/GEN_TRANS.U_ARM/din_latched )
);
FDR #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_TRANS.U_ARM/U_DOUT (
.C(CLK),
.D(\U0/I_VIO/GEN_TRANS.U_ARM/iDIN [0]),
.R(\U0/I_VIO/GEN_TRANS.U_ARM/iDIN [1]),
.Q(\U0/I_VIO/ARM_pulse )
);
FDCE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_TRANS.U_ARM/U_RFDRE (
.C(CLK),
.CE(\U0/I_VIO/ARM_pulse ),
.CLR(\U0/I_VIO/GEN_TRANS.U_ARM/iCLR ),
.D(\U0/I_VIO/ARM_pulse ),
.Q(\U0/I_VIO/GEN_TRANS.U_ARM/iDOUT_dly [0])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_TRANS.U_ARM/U_GEN_DELAY[1].U_FD (
.C(CLK),
.CE(N0),
.D(\U0/I_VIO/GEN_TRANS.U_ARM/iDOUT_dly [0]),
.Q(\U0/I_VIO/GEN_TRANS.U_ARM/iDOUT_dly [1])
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/U_DATA_OUT (
.C(CONTROL[0]),
.CE(N0),
.D(N1),
.Q(\U0/I_VIO/DATA_DOUT )
);
LUT4 #(
.INIT ( 16'h0101 ))
\U0/I_VIO/U_STATUS/F_STAT[0].I_STAT.U_STAT (
.I0(\U0/I_VIO/U_STATUS/iSTAT_CNT [0]),
.I1(\U0/I_VIO/U_STATUS/iSTAT_CNT [1]),
.I2(\U0/I_VIO/U_STATUS/iSTAT_CNT [2]),
.I3(\U0/I_VIO/U_STATUS/iSTAT_CNT [3]),
.O(\U0/I_VIO/U_STATUS/iSTAT [0])
);
LUT4 #(
.INIT ( 16'hD109 ))
\U0/I_VIO/U_STATUS/F_STAT[1].I_STAT.U_STAT (
.I0(\U0/I_VIO/U_STATUS/iSTAT_CNT [0]),
.I1(\U0/I_VIO/U_STATUS/iSTAT_CNT [1]),
.I2(\U0/I_VIO/U_STATUS/iSTAT_CNT [2]),
.I3(\U0/I_VIO/U_STATUS/iSTAT_CNT [3]),
.O(\U0/I_VIO/U_STATUS/iSTAT [1])
);
LUT4 #(
.INIT ( 16'h2100 ))
\U0/I_VIO/U_STATUS/F_STAT[2].I_STAT.U_STAT (
.I0(\U0/I_VIO/U_STATUS/iSTAT_CNT [0]),
.I1(\U0/I_VIO/U_STATUS/iSTAT_CNT [1]),
.I2(\U0/I_VIO/U_STATUS/iSTAT_CNT [2]),
.I3(\U0/I_VIO/U_STATUS/iSTAT_CNT [3]),
.O(\U0/I_VIO/U_STATUS/iSTAT [2])
);
LUT4 #(
.INIT ( 16'h0610 ))
\U0/I_VIO/U_STATUS/F_STAT[3].I_STAT.U_STAT (
.I0(\U0/I_VIO/U_STATUS/iSTAT_CNT [0]),
.I1(\U0/I_VIO/U_STATUS/iSTAT_CNT [1]),
.I2(\U0/I_VIO/U_STATUS/iSTAT_CNT [2]),
.I3(\U0/I_VIO/U_STATUS/iSTAT_CNT [3]),
.O(\U0/I_VIO/U_STATUS/iSTAT [3])
);
LUT4 #(
.INIT ( 16'h0000 ))
\U0/I_VIO/U_STATUS/F_STAT[4].I_STAT.U_STAT (
.I0(\U0/I_VIO/U_STATUS/iSTAT_CNT [0]),
.I1(\U0/I_VIO/U_STATUS/iSTAT_CNT [1]),
.I2(\U0/I_VIO/U_STATUS/iSTAT_CNT [2]),
.I3(\U0/I_VIO/U_STATUS/iSTAT_CNT [3]),
.O(\U0/I_VIO/U_STATUS/iSTAT [4])
);
LUT4 #(
.INIT ( 16'h0000 ))
\U0/I_VIO/U_STATUS/F_STAT[5].I_STAT.U_STAT (
.I0(\U0/I_VIO/U_STATUS/iSTAT_CNT [0]),
.I1(\U0/I_VIO/U_STATUS/iSTAT_CNT [1]),
.I2(\U0/I_VIO/U_STATUS/iSTAT_CNT [2]),
.I3(\U0/I_VIO/U_STATUS/iSTAT_CNT [3]),
.O(\U0/I_VIO/U_STATUS/iSTAT [5])
);
LUT4 #(
.INIT ( 16'h0000 ))
\U0/I_VIO/U_STATUS/F_STAT[6].I_STAT.U_STAT (
.I0(\U0/I_VIO/U_STATUS/iSTAT_CNT [0]),
.I1(\U0/I_VIO/U_STATUS/iSTAT_CNT [1]),
.I2(\U0/I_VIO/U_STATUS/iSTAT_CNT [2]),
.I3(\U0/I_VIO/U_STATUS/iSTAT_CNT [3]),
.O(\U0/I_VIO/U_STATUS/iSTAT [6])
);
LUT4 #(
.INIT ( 16'h0010 ))
\U0/I_VIO/U_STATUS/F_STAT[7].I_STAT.U_STAT (
.I0(\U0/I_VIO/U_STATUS/iSTAT_CNT [0]),
.I1(\U0/I_VIO/U_STATUS/iSTAT_CNT [1]),
.I2(\U0/I_VIO/U_STATUS/iSTAT_CNT [2]),
.I3(\U0/I_VIO/U_STATUS/iSTAT_CNT [3]),
.O(\U0/I_VIO/U_STATUS/iSTAT [7])
);
INV \U0/I_VIO/U_STATUS/U_CE_n (
.I(CONTROL[4]),
.O(\U0/I_VIO/U_STATUS/CFG_CE_n )
);
FDE #(
.INIT ( 1'b0 ))
\U0/I_VIO/U_STATUS/U_TDO (
.C(CONTROL[0]),
.CE(N0),
.D(\U0/I_VIO/U_STATUS/TDO_next ),
.Q(\U0/I_VIO/STAT_DOUT )
);
XORCY \U0/I_VIO/U_STATUS/U_STAT_CNT/G[0].U_XORCY (
.CI(N0),
.LI(\U0/I_VIO/U_STATUS/U_STAT_CNT/S [0]),
.O(\U0/I_VIO/U_STATUS/U_STAT_CNT/D [0])
);
MUXCY_L \U0/I_VIO/U_STATUS/U_STAT_CNT/G[0].GnH.U_MUXCY (
.CI(N0),
.DI(N1),
.S(\U0/I_VIO/U_STATUS/U_STAT_CNT/S [0]),
.LO(\U0/I_VIO/U_STATUS/U_STAT_CNT/CI [1])
);
XORCY \U0/I_VIO/U_STATUS/U_STAT_CNT/G[1].U_XORCY (
.CI(\U0/I_VIO/U_STATUS/U_STAT_CNT/CI [1]),
.LI(\U0/I_VIO/U_STATUS/U_STAT_CNT/S [1]),
.O(\U0/I_VIO/U_STATUS/U_STAT_CNT/D [1])
);
MUXCY_L \U0/I_VIO/U_STATUS/U_STAT_CNT/G[1].GnH.U_MUXCY (
.CI(\U0/I_VIO/U_STATUS/U_STAT_CNT/CI [1]),
.DI(N1),
.S(\U0/I_VIO/U_STATUS/U_STAT_CNT/S [1]),
.LO(\U0/I_VIO/U_STATUS/U_STAT_CNT/CI [2])
);
XORCY \U0/I_VIO/U_STATUS/U_STAT_CNT/G[2].U_XORCY (
.CI(\U0/I_VIO/U_STATUS/U_STAT_CNT/CI [2]),
.LI(\U0/I_VIO/U_STATUS/U_STAT_CNT/S [2]),
.O(\U0/I_VIO/U_STATUS/U_STAT_CNT/D [2])
);
MUXCY_L \U0/I_VIO/U_STATUS/U_STAT_CNT/G[2].GnH.U_MUXCY (
.CI(\U0/I_VIO/U_STATUS/U_STAT_CNT/CI [2]),
.DI(N1),
.S(\U0/I_VIO/U_STATUS/U_STAT_CNT/S [2]),
.LO(\U0/I_VIO/U_STATUS/U_STAT_CNT/CI [3])
);
XORCY \U0/I_VIO/U_STATUS/U_STAT_CNT/G[3].U_XORCY (
.CI(\U0/I_VIO/U_STATUS/U_STAT_CNT/CI [3]),
.LI(\U0/I_VIO/U_STATUS/U_STAT_CNT/S [3]),
.O(\U0/I_VIO/U_STATUS/U_STAT_CNT/D [3])
);
MUXCY_L \U0/I_VIO/U_STATUS/U_STAT_CNT/G[3].GnH.U_MUXCY (
.CI(\U0/I_VIO/U_STATUS/U_STAT_CNT/CI [3]),
.DI(N1),
.S(\U0/I_VIO/U_STATUS/U_STAT_CNT/S [3]),
.LO(\U0/I_VIO/U_STATUS/U_STAT_CNT/CI [4])
);
XORCY \U0/I_VIO/U_STATUS/U_STAT_CNT/G[4].U_XORCY (
.CI(\U0/I_VIO/U_STATUS/U_STAT_CNT/CI [4]),
.LI(\U0/I_VIO/U_STATUS/U_STAT_CNT/S [4]),
.O(\U0/I_VIO/U_STATUS/U_STAT_CNT/D [4])
);
MUXCY_L \U0/I_VIO/U_STATUS/U_STAT_CNT/G[4].GnH.U_MUXCY (
.CI(\U0/I_VIO/U_STATUS/U_STAT_CNT/CI [4]),
.DI(N1),
.S(\U0/I_VIO/U_STATUS/U_STAT_CNT/S [4]),
.LO(\U0/I_VIO/U_STATUS/U_STAT_CNT/CI [5])
);
XORCY \U0/I_VIO/U_STATUS/U_STAT_CNT/G[5].U_XORCY (
.CI(\U0/I_VIO/U_STATUS/U_STAT_CNT/CI [5]),
.LI(\U0/I_VIO/U_STATUS/U_STAT_CNT/S [5]),
.O(\U0/I_VIO/U_STATUS/U_STAT_CNT/D [5])
);
MUXCY_L \U0/I_VIO/U_STATUS/U_STAT_CNT/G[5].GnH.U_MUXCY (
.CI(\U0/I_VIO/U_STATUS/U_STAT_CNT/CI [5]),
.DI(N1),
.S(\U0/I_VIO/U_STATUS/U_STAT_CNT/S [5]),
.LO(\U0/I_VIO/U_STATUS/U_STAT_CNT/CI [6])
);
XORCY \U0/I_VIO/U_STATUS/U_STAT_CNT/G[6].U_XORCY (
.CI(\U0/I_VIO/U_STATUS/U_STAT_CNT/CI [6]),
.LI(\U0/I_VIO/U_STATUS/U_STAT_CNT/S [6]),
.O(\U0/I_VIO/U_STATUS/U_STAT_CNT/D [6])
);
MUXCY_L \U0/I_VIO/U_STATUS/U_STAT_CNT/G[6].GnH.U_MUXCY (
.CI(\U0/I_VIO/U_STATUS/U_STAT_CNT/CI [6]),
.DI(N1),
.S(\U0/I_VIO/U_STATUS/U_STAT_CNT/S [6]),
.LO(\U0/I_VIO/U_STATUS/U_STAT_CNT/CI [7])
);
XORCY \U0/I_VIO/U_STATUS/U_STAT_CNT/G[7].U_XORCY (
.CI(\U0/I_VIO/U_STATUS/U_STAT_CNT/CI [7]),
.LI(\U0/I_VIO/U_STATUS/U_STAT_CNT/S [7]),
.O(\U0/I_VIO/U_STATUS/U_STAT_CNT/D [7])
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/I_VIO/U_STATUS/U_STAT_CNT/G[0].U_LUT (
.I0(\U0/I_VIO/U_STATUS/iSTAT_CNT [0]),
.O(\U0/I_VIO/U_STATUS/U_STAT_CNT/S [0])
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/I_VIO/U_STATUS/U_STAT_CNT/G[1].U_LUT (
.I0(\U0/I_VIO/U_STATUS/iSTAT_CNT [1]),
.O(\U0/I_VIO/U_STATUS/U_STAT_CNT/S [1])
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/I_VIO/U_STATUS/U_STAT_CNT/G[2].U_LUT (
.I0(\U0/I_VIO/U_STATUS/iSTAT_CNT [2]),
.O(\U0/I_VIO/U_STATUS/U_STAT_CNT/S [2])
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/I_VIO/U_STATUS/U_STAT_CNT/G[3].U_LUT (
.I0(\U0/I_VIO/U_STATUS/iSTAT_CNT [3]),
.O(\U0/I_VIO/U_STATUS/U_STAT_CNT/S [3])
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/I_VIO/U_STATUS/U_STAT_CNT/G[4].U_LUT (
.I0(\U0/I_VIO/U_STATUS/iSTAT_CNT [4]),
.O(\U0/I_VIO/U_STATUS/U_STAT_CNT/S [4])
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/I_VIO/U_STATUS/U_STAT_CNT/G[5].U_LUT (
.I0(\U0/I_VIO/U_STATUS/iSTAT_CNT [5]),
.O(\U0/I_VIO/U_STATUS/U_STAT_CNT/S [5])
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/I_VIO/U_STATUS/U_STAT_CNT/G[6].U_LUT (
.I0(\U0/I_VIO/U_STATUS/iSTAT_CNT [6]),
.O(\U0/I_VIO/U_STATUS/U_STAT_CNT/S [6])
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/I_VIO/U_STATUS/U_STAT_CNT/G[7].U_LUT (
.I0(\U0/I_VIO/U_STATUS/iSTAT_CNT [7]),
.O(\U0/I_VIO/U_STATUS/U_STAT_CNT/S [7])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/U_STATUS/U_STAT_CNT/G[0].U_FDRE (
.C(CONTROL[0]),
.CE(N0),
.D(\U0/I_VIO/U_STATUS/U_STAT_CNT/D [0]),
.R(\U0/I_VIO/U_STATUS/CFG_CE_n ),
.Q(\U0/I_VIO/U_STATUS/iSTAT_CNT [0])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/U_STATUS/U_STAT_CNT/G[1].U_FDRE (
.C(CONTROL[0]),
.CE(N0),
.D(\U0/I_VIO/U_STATUS/U_STAT_CNT/D [1]),
.R(\U0/I_VIO/U_STATUS/CFG_CE_n ),
.Q(\U0/I_VIO/U_STATUS/iSTAT_CNT [1])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/U_STATUS/U_STAT_CNT/G[2].U_FDRE (
.C(CONTROL[0]),
.CE(N0),
.D(\U0/I_VIO/U_STATUS/U_STAT_CNT/D [2]),
.R(\U0/I_VIO/U_STATUS/CFG_CE_n ),
.Q(\U0/I_VIO/U_STATUS/iSTAT_CNT [2])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/U_STATUS/U_STAT_CNT/G[3].U_FDRE (
.C(CONTROL[0]),
.CE(N0),
.D(\U0/I_VIO/U_STATUS/U_STAT_CNT/D [3]),
.R(\U0/I_VIO/U_STATUS/CFG_CE_n ),
.Q(\U0/I_VIO/U_STATUS/iSTAT_CNT [3])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/U_STATUS/U_STAT_CNT/G[4].U_FDRE (
.C(CONTROL[0]),
.CE(N0),
.D(\U0/I_VIO/U_STATUS/U_STAT_CNT/D [4]),
.R(\U0/I_VIO/U_STATUS/CFG_CE_n ),
.Q(\U0/I_VIO/U_STATUS/iSTAT_CNT [4])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/U_STATUS/U_STAT_CNT/G[5].U_FDRE (
.C(CONTROL[0]),
.CE(N0),
.D(\U0/I_VIO/U_STATUS/U_STAT_CNT/D [5]),
.R(\U0/I_VIO/U_STATUS/CFG_CE_n ),
.Q(\U0/I_VIO/U_STATUS/iSTAT_CNT [5])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/U_STATUS/U_STAT_CNT/G[6].U_FDRE (
.C(CONTROL[0]),
.CE(N0),
.D(\U0/I_VIO/U_STATUS/U_STAT_CNT/D [6]),
.R(\U0/I_VIO/U_STATUS/CFG_CE_n ),
.Q(\U0/I_VIO/U_STATUS/iSTAT_CNT [6])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/U_STATUS/U_STAT_CNT/G[7].U_FDRE (
.C(CONTROL[0]),
.CE(N0),
.D(\U0/I_VIO/U_STATUS/U_STAT_CNT/D [7]),
.R(\U0/I_VIO/U_STATUS/CFG_CE_n ),
.Q(\U0/I_VIO/U_STATUS/iSTAT_CNT [7])
);
XORCY \U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/COUNT/G[0].U_XORCY (
.CI(N0),
.LI(\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/COUNT/S [0]),
.O(\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/COUNT/D [0])
);
MUXCY_L \U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/COUNT/G[0].GnH.U_MUXCY (
.CI(N0),
.DI(N1),
.S(\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/COUNT/S [0]),
.LO(\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/COUNT/CI [1])
);
XORCY \U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/COUNT/G[1].U_XORCY (
.CI(\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/COUNT/CI [1]),
.LI(\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/COUNT/S [1]),
.O(\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/COUNT/D [1])
);
MUXCY_L \U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/COUNT/G[1].GnH.U_MUXCY (
.CI(\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/COUNT/CI [1]),
.DI(N1),
.S(\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/COUNT/S [1]),
.LO(\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/COUNT/CI [2])
);
XORCY \U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/COUNT/G[2].U_XORCY (
.CI(\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/COUNT/CI [2]),
.LI(\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/COUNT/S [2]),
.O(\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/COUNT/D [2])
);
MUXCY_L \U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/COUNT/G[2].GnH.U_MUXCY (
.CI(\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/COUNT/CI [2]),
.DI(N1),
.S(\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/COUNT/S [2]),
.LO(\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/COUNT/CI [3])
);
XORCY \U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/COUNT/G[3].U_XORCY (
.CI(\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/COUNT/CI [3]),
.LI(\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/COUNT/S [3]),
.O(\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/COUNT/D [3])
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/COUNT/G[0].U_LUT (
.I0(\U0/I_VIO/addr [0]),
.O(\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/COUNT/S [0])
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/COUNT/G[1].U_LUT (
.I0(\U0/I_VIO/addr [1]),
.O(\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/COUNT/S [1])
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/COUNT/G[2].U_LUT (
.I0(\U0/I_VIO/addr [2]),
.O(\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/COUNT/S [2])
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/COUNT/G[3].U_LUT (
.I0(\U0/I_VIO/addr [3]),
.O(\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/COUNT/S [3])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/COUNT/G[0].U_FDRE (
.C(CLK),
.CE(\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/cnt_ce ),
.D(\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/COUNT/D [0]),
.R(\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/cnt_reset ),
.Q(\U0/I_VIO/addr [0])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/COUNT/G[1].U_FDRE (
.C(CLK),
.CE(\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/cnt_ce ),
.D(\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/COUNT/D [1]),
.R(\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/cnt_reset ),
.Q(\U0/I_VIO/addr [1])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/COUNT/G[2].U_FDRE (
.C(CLK),
.CE(\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/cnt_ce ),
.D(\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/COUNT/D [2]),
.R(\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/cnt_reset ),
.Q(\U0/I_VIO/addr [2])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/COUNT/G[3].U_FDRE (
.C(CLK),
.CE(\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/cnt_ce ),
.D(\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/COUNT/D [3]),
.R(\U0/I_VIO/GEN_SYNC_OUT_ADDR.SYNC_OUT_ADDR/cnt_reset ),
.Q(\U0/I_VIO/addr [3])
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\U0/I_VIO/U_STATUS/U_SMUX/U_CS_MUX/I4.U_MUX16/Mmux_O21 (
.I0(\U0/I_VIO/U_STATUS/iSTAT_CNT [5]),
.I1(\U0/I_VIO/U_STATUS/iSTAT_CNT [6]),
.I2(\U0/I_VIO/U_STATUS/iSTAT [3]),
.I3(\U0/I_VIO/U_STATUS/iSTAT [7]),
.I4(\U0/I_VIO/U_STATUS/iSTAT [5]),
.I5(\U0/I_VIO/U_STATUS/iSTAT [1]),
.O(\U0/I_VIO/U_STATUS/U_SMUX/U_CS_MUX/I4.U_MUX16/Mmux_O2 )
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
\U0/I_VIO/U_STATUS/U_SMUX/U_CS_MUX/I4.U_MUX16/Mmux_O22 (
.I0(\U0/I_VIO/U_STATUS/iSTAT_CNT [5]),
.I1(\U0/I_VIO/U_STATUS/iSTAT_CNT [6]),
.I2(\U0/I_VIO/U_STATUS/iSTAT [2]),
.I3(\U0/I_VIO/U_STATUS/iSTAT [6]),
.I4(\U0/I_VIO/U_STATUS/iSTAT [4]),
.I5(\U0/I_VIO/U_STATUS/iSTAT [0]),
.O(\U0/I_VIO/U_STATUS/U_SMUX/U_CS_MUX/I4.U_MUX16/Mmux_O21_1647 )
);
LUT6 #(
.INIT ( 64'h7FFFFFFFFFFFFFFF ))
\U0/I_VIO/U_STATUS/U_SMUX/U_CS_MUX/I4.U_MUX16/Mmux_O23 (
.I0(CONTROL[15]),
.I1(CONTROL[14]),
.I2(CONTROL[16]),
.I3(CONTROL[17]),
.I4(CONTROL[18]),
.I5(CONTROL[19]),
.O(\U0/I_VIO/U_STATUS/U_SMUX/U_CS_MUX/I4.U_MUX16/Mmux_O22_1648 )
);
LUT6 #(
.INIT ( 64'h7FFFFFFFFFFFFFFF ))
\U0/I_VIO/U_STATUS/U_SMUX/U_CS_MUX/I4.U_MUX16/Mmux_O24 (
.I0(CONTROL[21]),
.I1(CONTROL[20]),
.I2(CONTROL[22]),
.I3(CONTROL[23]),
.I4(CONTROL[24]),
.I5(CONTROL[25]),
.O(\U0/I_VIO/U_STATUS/U_SMUX/U_CS_MUX/I4.U_MUX16/Mmux_O23_1649 )
);
LUT6 #(
.INIT ( 64'h7FFFFFFFFFFFFFFF ))
\U0/I_VIO/U_STATUS/U_SMUX/U_CS_MUX/I4.U_MUX16/Mmux_O25 (
.I0(CONTROL[2]),
.I1(CONTROL[1]),
.I2(CONTROL[4]),
.I3(CONTROL[5]),
.I4(CONTROL[6]),
.I5(CONTROL[7]),
.O(\U0/I_VIO/U_STATUS/U_SMUX/U_CS_MUX/I4.U_MUX16/Mmux_O24_1650 )
);
LUT6 #(
.INIT ( 64'h7FFFFFFFFFFFFFFF ))
\U0/I_VIO/U_STATUS/U_SMUX/U_CS_MUX/I4.U_MUX16/Mmux_O26 (
.I0(CONTROL[9]),
.I1(CONTROL[8]),
.I2(CONTROL[10]),
.I3(CONTROL[11]),
.I4(CONTROL[12]),
.I5(CONTROL[13]),
.O(\U0/I_VIO/U_STATUS/U_SMUX/U_CS_MUX/I4.U_MUX16/Mmux_O25_1651 )
);
LUT6 #(
.INIT ( 64'h7FFFFFFFFFFFFFFF ))
\U0/I_VIO/U_STATUS/U_SMUX/U_CS_MUX/I4.U_MUX16/Mmux_O27 (
.I0(CONTROL[27]),
.I1(CONTROL[26]),
.I2(CONTROL[28]),
.I3(CONTROL[29]),
.I4(CONTROL[30]),
.I5(CONTROL[31]),
.O(\U0/I_VIO/U_STATUS/U_SMUX/U_CS_MUX/I4.U_MUX16/Mmux_O26_1652 )
);
LUT4 #(
.INIT ( 16'h7FFF ))
\U0/I_VIO/U_STATUS/U_SMUX/U_CS_MUX/I4.U_MUX16/Mmux_O28 (
.I0(CONTROL[33]),
.I1(CONTROL[32]),
.I2(CONTROL[34]),
.I3(CONTROL[35]),
.O(\U0/I_VIO/U_STATUS/U_SMUX/U_CS_MUX/I4.U_MUX16/Mmux_O27_1653 )
);
LUT6 #(
.INIT ( 64'hFFFFFFFFFFFFFFFE ))
\U0/I_VIO/U_STATUS/U_SMUX/U_CS_MUX/I4.U_MUX16/Mmux_O29 (
.I0(\U0/I_VIO/U_STATUS/U_SMUX/U_CS_MUX/I4.U_MUX16/Mmux_O22_1648 ),
.I1(\U0/I_VIO/U_STATUS/U_SMUX/U_CS_MUX/I4.U_MUX16/Mmux_O23_1649 ),
.I2(\U0/I_VIO/U_STATUS/U_SMUX/U_CS_MUX/I4.U_MUX16/Mmux_O24_1650 ),
.I3(\U0/I_VIO/U_STATUS/U_SMUX/U_CS_MUX/I4.U_MUX16/Mmux_O25_1651 ),
.I4(\U0/I_VIO/U_STATUS/U_SMUX/U_CS_MUX/I4.U_MUX16/Mmux_O26_1652 ),
.I5(\U0/I_VIO/U_STATUS/U_SMUX/U_CS_MUX/I4.U_MUX16/Mmux_O27_1653 ),
.O(\U0/I_VIO/U_STATUS/U_SMUX/U_CS_MUX/I4.U_MUX16/Mmux_O28_1654 )
);
LUT5 #(
.INIT ( 32'hAFACA3A0 ))
\U0/I_VIO/U_STATUS/U_SMUX/U_CS_MUX/I4.U_MUX16/Mmux_O210 (
.I0(\U0/I_VIO/U_STATUS/U_SMUX/U_CS_MUX/I4.U_MUX16/Mmux_O28_1654 ),
.I1(\U0/I_VIO/U_STATUS/iSTAT_CNT [4]),
.I2(\U0/I_VIO/U_STATUS/iSTAT_CNT [7]),
.I3(\U0/I_VIO/U_STATUS/U_SMUX/U_CS_MUX/I4.U_MUX16/Mmux_O21_1647 ),
.I4(\U0/I_VIO/U_STATUS/U_SMUX/U_CS_MUX/I4.U_MUX16/Mmux_O2 ),
.O(\U0/I_VIO/U_STATUS/TDO_next )
);
FDC #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_TRANS.U_ARM/U_DOUT0 (
.C(CLK),
.CLR(\U0/I_VIO/GEN_TRANS.U_ARM/iCLR ),
.D(\U0/I_VIO/GEN_TRANS.U_ARM/din_latched ),
.Q(\U0/I_VIO/GEN_TRANS.U_ARM/iDIN [0])
);
FDC #(
.INIT ( 1'b0 ))
\U0/I_VIO/GEN_TRANS.U_ARM/U_DOUT1 (
.C(CLK),
.CLR(\U0/I_VIO/GEN_TRANS.U_ARM/iCLR ),
.D(\U0/I_VIO/GEN_TRANS.U_ARM/iDIN [0]),
.Q(\U0/I_VIO/GEN_TRANS.U_ARM/iDIN [1])
);
// synthesis translate_on
endmodule
// synthesis translate_off
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
// synthesis translate_on
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_jtag_uart_0_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 5: 0] wfifo_used;
input clk;
input [ 7: 0] fifo_wdata;
input fifo_wr;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
always @(posedge clk)
begin
if (fifo_wr)
$write("%c", fifo_wdata);
end
assign wfifo_used = {6{1'b0}};
assign r_dat = {8{1'b0}};
assign fifo_FF = 1'b0;
assign wfifo_empty = 1'b1;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_jtag_uart_0_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 5: 0] wfifo_used;
input clk;
input fifo_clear;
input [ 7: 0] fifo_wdata;
input fifo_wr;
input rd_wfifo;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
wasca_jtag_uart_0_sim_scfifo_w the_wasca_jtag_uart_0_sim_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo wfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (fifo_wdata),
// .empty (wfifo_empty),
// .full (fifo_FF),
// .q (r_dat),
// .rdreq (rd_wfifo),
// .usedw (wfifo_used),
// .wrreq (fifo_wr)
// );
//
// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// wfifo.lpm_numwords = 64,
// wfifo.lpm_showahead = "OFF",
// wfifo.lpm_type = "scfifo",
// wfifo.lpm_width = 8,
// wfifo.lpm_widthu = 6,
// wfifo.overflow_checking = "OFF",
// wfifo.underflow_checking = "OFF",
// wfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_jtag_uart_0_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [ 31: 0] bytes_left;
wire fifo_EF;
reg fifo_rd_d;
wire [ 7: 0] fifo_rdata;
wire new_rom;
wire [ 31: 0] num_bytes;
wire [ 6: 0] rfifo_entries;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Generate rfifo_entries for simulation
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
bytes_left <= 32'h0;
fifo_rd_d <= 1'b0;
end
else
begin
fifo_rd_d <= fifo_rd;
// decrement on read
if (fifo_rd_d)
bytes_left <= bytes_left - 1'b1;
// catch new contents
if (new_rom)
bytes_left <= num_bytes;
end
end
assign fifo_EF = bytes_left == 32'b0;
assign rfifo_full = bytes_left > 7'h40;
assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;
assign rfifo_used = rfifo_entries[5 : 0];
assign new_rom = 1'b0;
assign num_bytes = 32'b0;
assign fifo_rdata = 8'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_jtag_uart_0_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_clear;
input fifo_rd;
input rst_n;
input [ 7: 0] t_dat;
input wr_rfifo;
wire fifo_EF;
wire [ 7: 0] fifo_rdata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
wasca_jtag_uart_0_sim_scfifo_r the_wasca_jtag_uart_0_sim_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo rfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (t_dat),
// .empty (fifo_EF),
// .full (rfifo_full),
// .q (fifo_rdata),
// .rdreq (fifo_rd),
// .usedw (rfifo_used),
// .wrreq (wr_rfifo)
// );
//
// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// rfifo.lpm_numwords = 64,
// rfifo.lpm_showahead = "OFF",
// rfifo.lpm_type = "scfifo",
// rfifo.lpm_width = 8,
// rfifo.lpm_widthu = 6,
// rfifo.overflow_checking = "OFF",
// rfifo.underflow_checking = "OFF",
// rfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_jtag_uart_0 (
// inputs:
av_address,
av_chipselect,
av_read_n,
av_write_n,
av_writedata,
clk,
rst_n,
// outputs:
av_irq,
av_readdata,
av_waitrequest,
dataavailable,
readyfordata
)
/* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,C106,D101,D103\"" */ ;
output av_irq;
output [ 31: 0] av_readdata;
output av_waitrequest;
output dataavailable;
output readyfordata;
input av_address;
input av_chipselect;
input av_read_n;
input av_write_n;
input [ 31: 0] av_writedata;
input clk;
input rst_n;
reg ac;
wire activity;
wire av_irq;
wire [ 31: 0] av_readdata;
reg av_waitrequest;
reg dataavailable;
reg fifo_AE;
reg fifo_AF;
wire fifo_EF;
wire fifo_FF;
wire fifo_clear;
wire fifo_rd;
wire [ 7: 0] fifo_rdata;
wire [ 7: 0] fifo_wdata;
reg fifo_wr;
reg ien_AE;
reg ien_AF;
wire ipen_AE;
wire ipen_AF;
reg pause_irq;
wire [ 7: 0] r_dat;
wire r_ena;
reg r_val;
wire rd_wfifo;
reg read_0;
reg readyfordata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
reg rvalid;
reg sim_r_ena;
reg sim_t_dat;
reg sim_t_ena;
reg sim_t_pause;
wire [ 7: 0] t_dat;
reg t_dav;
wire t_ena;
wire t_pause;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
reg woverflow;
wire wr_rfifo;
//avalon_jtag_slave, which is an e_avalon_slave
assign rd_wfifo = r_ena & ~wfifo_empty;
assign wr_rfifo = t_ena & ~rfifo_full;
assign fifo_clear = ~rst_n;
wasca_jtag_uart_0_scfifo_w the_wasca_jtag_uart_0_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_clear (fifo_clear),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.rd_wfifo (rd_wfifo),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
wasca_jtag_uart_0_scfifo_r the_wasca_jtag_uart_0_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_clear (fifo_clear),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n),
.t_dat (t_dat),
.wr_rfifo (wr_rfifo)
);
assign ipen_AE = ien_AE & fifo_AE;
assign ipen_AF = ien_AF & (pause_irq | fifo_AF);
assign av_irq = ipen_AE | ipen_AF;
assign activity = t_pause | t_ena;
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
pause_irq <= 1'b0;
else // only if fifo is not empty...
if (t_pause & ~fifo_EF)
pause_irq <= 1'b1;
else if (read_0)
pause_irq <= 1'b0;
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
r_val <= 1'b0;
t_dav <= 1'b1;
end
else
begin
r_val <= r_ena & ~wfifo_empty;
t_dav <= ~rfifo_full;
end
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
fifo_AE <= 1'b0;
fifo_AF <= 1'b0;
fifo_wr <= 1'b0;
rvalid <= 1'b0;
read_0 <= 1'b0;
ien_AE <= 1'b0;
ien_AF <= 1'b0;
ac <= 1'b0;
woverflow <= 1'b0;
av_waitrequest <= 1'b1;
end
else
begin
fifo_AE <= {fifo_FF,wfifo_used} <= 8;
fifo_AF <= (7'h40 - {rfifo_full,rfifo_used}) <= 8;
fifo_wr <= 1'b0;
read_0 <= 1'b0;
av_waitrequest <= ~(av_chipselect & (~av_write_n | ~av_read_n) & av_waitrequest);
if (activity)
ac <= 1'b1;
// write
if (av_chipselect & ~av_write_n & av_waitrequest)
// addr 1 is control; addr 0 is data
if (av_address)
begin
ien_AF <= av_writedata[0];
ien_AE <= av_writedata[1];
if (av_writedata[10] & ~activity)
ac <= 1'b0;
end
else
begin
fifo_wr <= ~fifo_FF;
woverflow <= fifo_FF;
end
// read
if (av_chipselect & ~av_read_n & av_waitrequest)
begin
// addr 1 is interrupt; addr 0 is data
if (~av_address)
rvalid <= ~fifo_EF;
read_0 <= ~av_address;
end
end
end
assign fifo_wdata = av_writedata[7 : 0];
assign fifo_rd = (av_chipselect & ~av_read_n & av_waitrequest & ~av_address) ? ~fifo_EF : 1'b0;
assign av_readdata = read_0 ? { {9{1'b0}},rfifo_full,rfifo_used,rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,fifo_rdata } : { {9{1'b0}},(7'h40 - {fifo_FF,wfifo_used}),rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,{6{1'b0}},ien_AE,ien_AF };
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
readyfordata <= 0;
else
readyfordata <= ~fifo_FF;
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Tie off Atlantic Interface signals not used for simulation
always @(posedge clk)
begin
sim_t_pause <= 1'b0;
sim_t_ena <= 1'b0;
sim_t_dat <= t_dav ? r_dat : {8{r_val}};
sim_r_ena <= 1'b0;
end
assign r_ena = sim_r_ena;
assign t_ena = sim_t_ena;
assign t_dat = sim_t_dat;
assign t_pause = sim_t_pause;
always @(fifo_EF)
begin
dataavailable = ~fifo_EF;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// alt_jtag_atlantic wasca_jtag_uart_0_alt_jtag_atlantic
// (
// .clk (clk),
// .r_dat (r_dat),
// .r_ena (r_ena),
// .r_val (r_val),
// .rst_n (rst_n),
// .t_dat (t_dat),
// .t_dav (t_dav),
// .t_ena (t_ena),
// .t_pause (t_pause)
// );
//
// defparam wasca_jtag_uart_0_alt_jtag_atlantic.INSTANCE_ID = 0,
// wasca_jtag_uart_0_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 6,
// wasca_jtag_uart_0_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6,
// wasca_jtag_uart_0_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES";
//
// always @(posedge clk or negedge rst_n)
// begin
// if (rst_n == 0)
// dataavailable <= 0;
// else
// dataavailable <= ~fifo_EF;
// end
//
//
//synthesis read_comments_as_HDL off
endmodule
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:18:35 08/11/2009
// Design Name:
// Module Name: STATUS_IN
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////
/////
///// Decode four patterns for specific states
///// Idle 00000000
///// Reset 01010101
///// FIFO full 00001111
///// Training_done 00110011
/////
/////////////////////////////////////////////////////////////////////////////////
module RCB_FRL_STATUS_IN(
input CLK,
input MODULE_RST,
output reg RESET, //output indicating reset state
output reg FIFO_FULL, //output indicating full state
output reg TRAINING_DONE, //output indicating done state
input STATUS,
output reg status_error // indicates error if ambiguous status lasts longer than 8 cycles
// output reg IDLE_RESET // Jiansong: why we need IDLE_RESET?
);
/////////////////////////////////////////////////////////////////////////////////
// input CLK;
// input MODULE_RST;
// input STATUS;
// output RESET,
// FIFO_FULL,
// TRAINING_DONE,
// IDLE_RESET;
/////////////////////////////////////////////////////////////////////////////////
// reg RESET,
// FIFO_FULL,
// TRAINING_DONE,
reg IDLE_RESET;
reg IDLE_FLAG; // why we need this flag?
reg ambiguity; // indicates ambiguous status
reg [2:0] error_cnt;
reg [7:0] shift_reg;
parameter RST = 2'b00;
parameter FULL = 2'b01;
parameter DONE = 2'b10;
parameter IDLE = 2'b11;
reg [1:0] INT_SAT;
/////////////////////////////////////////////////////////////////////////////////
always @ ( negedge CLK ) begin
if ( MODULE_RST == 1'b1 ) begin
shift_reg <= 8'h00;
end
else begin
shift_reg <= {shift_reg[6:0], STATUS};
end
end
/////////////////////////////////////////////////////////////////////////////////
/// Pattern Recognition
// Modified by Jiansong, 2010-5-25, remove ambiguity
always @ ( negedge CLK ) begin
ambiguity <= 1'b0;
if ( shift_reg == 8'h55 | shift_reg == 8'hAA) begin
INT_SAT <= RST;
end
else if ( shift_reg == 8'hF0 | shift_reg == 8'h87 | shift_reg == 8'hC3 | shift_reg == 8'hE1 | shift_reg == 8'h78 | shift_reg == 8'h3C | shift_reg == 8'h1E | shift_reg == 8'h0F ) begin
INT_SAT <= FULL;
end
else if ( shift_reg == 8'h33 | shift_reg == 8'h66 | shift_reg == 8'hCC | shift_reg == 8'h99 ) begin
INT_SAT <= DONE;
end
else if ( shift_reg == 8'h00) begin
INT_SAT <= IDLE;
end
else begin// by default, the previous INT_SAT remains, this normally happen when the status is changing
INT_SAT <= INT_SAT;
ambiguity <= 1'b1;
end
end
always@ (negedge CLK) begin
if (MODULE_RST) begin
error_cnt <= 3'b000;
end else if(ambiguity) begin
if (error_cnt != 3'b111)
error_cnt <= error_cnt + 3'b001;
else
error_cnt <= error_cnt;
end else begin
error_cnt <= 3'b000;
end
end
always@ (negedge CLK) begin
status_error <= (error_cnt == 3'b111) ? 1'b1 : 1'b0;
end
/////////////////////////////////////////////////////////////////////////////////
/// States are exclusive of each other
always @ (posedge CLK) begin
if ( MODULE_RST == 1'b1 ) begin
RESET <= 1'b0;
TRAINING_DONE <= 1'b0;
FIFO_FULL <= 1'b0;
IDLE_RESET <= 0;
IDLE_FLAG <= 0;
end
else if ( INT_SAT == RST) begin
RESET <= 1'b1;
TRAINING_DONE <= 1'b0;
FIFO_FULL <= 1'b0;
IDLE_RESET <= 0;
IDLE_FLAG <= 0;
end
else if ( INT_SAT == DONE ) begin
TRAINING_DONE <= 1'b1;
FIFO_FULL <= 1'b0;
RESET <= 1'b0;
IDLE_RESET <= 0;
IDLE_FLAG <= 0;
end
else if ( INT_SAT == FULL ) begin
RESET <= 1'b0;
FIFO_FULL <= 1'b1;
TRAINING_DONE <= 1'b1;
IDLE_RESET <= 0;
IDLE_FLAG <= 0;
end
else if ( INT_SAT == IDLE ) begin
if(IDLE_FLAG == 0) // Jiansong: edge detection
begin
IDLE_FLAG <= 1;
IDLE_RESET <= 1;
end
else
begin
IDLE_RESET <= 0;
end
RESET <= 1'b0;
FIFO_FULL <= 1'b0;
TRAINING_DONE <= 1'b0;
end
end
endmodule
|
/*===========================================================================*/
/* Copyright (C) 2001 Authors */
/* */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer. */
/* */
/* This source file is free software; you can redistribute it and/or modify */
/* it under the terms of the GNU Lesser General Public License as published */
/* by the Free Software Foundation; either version 2.1 of the License, or */
/* (at your option) any later version. */
/* */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
/* License for more details. */
/* */
/* You should have received a copy of the GNU Lesser General Public License */
/* along with this source; if not, write to the Free Software Foundation, */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
/* */
/*===========================================================================*/
/* DEBUG INTERFACE */
/*---------------------------------------------------------------------------*/
/* Test the debug interface: */
/* - CPU Control features. */
/* */
/* Author(s): */
/* - Olivier Girard, [email protected] */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 95 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $ */
/*===========================================================================*/
integer test_nr;
integer test_var;
integer dco_clk_counter;
always @ (negedge dco_clk)
dco_clk_counter <= dco_clk_counter+1;
integer dbg_clk_counter;
always @ (negedge dbg_clk)
dbg_clk_counter <= dbg_clk_counter+1;
initial
begin
$display(" ===============================================");
$display("| START SIMULATION |");
$display(" ===============================================");
`ifdef DBG_EN
`ifdef DBG_I2C
`ifdef ASIC_CLOCKING
test_nr = 0;
#1 dbg_en = 0;
repeat(30) @(posedge dco_clk);
stimulus_done = 0;
// Make sure the CPU always starts executing when the
// debug interface is disabled during POR.
// Also make sure that the debug interface clock is stopped
// and that it is under reset
//--------------------------------------------------------
dbg_en = 0;
test_nr = 1;
@(negedge dco_clk) dbg_clk_counter = 0;
repeat(300) @(posedge dco_clk);
if (r14 === 16'h0000) tb_error("====== CPU is stopped event though the debug interface is disabled - test 1 =====");
if (dbg_clk_counter !== 0) tb_error("====== DBG_CLK is not stopped (test 1) =====");
if (dbg_rst == 1'b0) tb_error("====== DBG_RST signal is not active (test 3) =====");
test_var = r14;
// Make sure that enabling the debug interface after the POR
// don't stop the cpu
// Also make sure that the debug interface clock is running
// and that its reset is released
//--------------------------------------------------------
dbg_en = 1;
test_nr = 2;
@(negedge dco_clk) dbg_clk_counter = 0;
repeat(300) @(posedge dco_clk);
if (r14 === test_var[15:0]) tb_error("====== CPU is stopped when the debug interface is disabled after POR - test 4 =====");
if (dbg_clk_counter == 0) tb_error("====== DBG_CLK is not running (test 5) =====");
if (dbg_rst !== 1'b0) tb_error("====== DBG_RST signal is active (test 6) =====");
// Make sure that disabling the CPU with debug enabled
// will stop the CPU
// Also make sure that the debug interface clock is stopped
// and that it is NOT under reset
//--------------------------------------------------------
cpu_en = 0;
dbg_en = 1;
test_nr = 3;
#(6*50);
test_var = r14;
dbg_clk_counter = 0;
#(300*50);
if (r14 !== test_var[15:0]) tb_error("====== CPU is not stopped (test 7) =====");
if (dbg_clk_counter !== 0) tb_error("====== DBG_CLK is not running (test 8) =====");
if (dbg_rst !== 1'b0) tb_error("====== DBG_RST signal is active (test 9) =====");
cpu_en = 1;
repeat(6) @(negedge dco_clk);
// Create POR with debug enable and observe the
// behavior depending on the DBG_RST_BRK_EN define
//--------------------------------------------------------
dbg_en = 1;
test_nr = 4;
@(posedge dco_clk); // Generate POR
reset_n = 1'b0;
@(posedge dco_clk);
reset_n = 1'b1;
repeat(300) @(posedge dco_clk);
`ifdef DBG_RST_BRK_EN
if (r14 !== 16'h0000) tb_error("====== CPU is not stopped with the debug interface enabled and DBG_RST_BRK_EN=1 - test 3 =====");
`else
if (r14 === 16'h0000) tb_error("====== CPU is stopped with the debug interface enabled and DBG_RST_BRK_EN=0 - test 3 =====");
`endif
// Check CPU_CTL reset value
dbg_i2c_rd(CPU_CTL);
`ifdef DBG_RST_BRK_EN
if (dbg_i2c_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value - test 4 =====");
`else
if (dbg_i2c_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value - test 4 =====");
`endif
// Make sure that DBG_EN resets the debug interface
//--------------------------------------------------------
test_nr = 5;
// Let the CPU run
dbg_i2c_wr(CPU_CTL, 16'h0002);
repeat(300) @(posedge dco_clk);
dbg_i2c_wr(CPU_CTL, 16'h0000);
dbg_i2c_wr(MEM_DATA, 16'haa55);
dbg_i2c_rd(CPU_CTL);
if (dbg_i2c_buf !== 16'h0000) tb_error("====== CPU_CTL write access failed - test 5 =====");
dbg_i2c_rd(MEM_DATA);
if (dbg_i2c_buf !== 16'haa55) tb_error("====== MEM_DATA write access failed - test 6 =====");
test_var = r14; // Backup the current register value
@(posedge dco_clk); // Resets the debug interface
dbg_en = 1'b0;
repeat(2) @(posedge dco_clk);
dbg_en = 1'b1;
// Make sure that the register was not reseted
if (r14 < test_var) tb_error("====== CPU was reseted with DBG_EN - test 7 =====");
repeat(2) @(posedge dco_clk);
// Check CPU_CTL reset value
dbg_i2c_rd(CPU_CTL);
`ifdef DBG_RST_BRK_EN
if (dbg_i2c_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value - test 8 =====");
`else
if (dbg_i2c_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value - test 8 =====");
`endif
dbg_i2c_rd(MEM_DATA);
if (dbg_i2c_buf !== 16'h0000) tb_error("====== MEM_DATA read access failed - test 9 =====");
// Make sure that RESET_N resets the debug interface
//--------------------------------------------------------
test_nr = 6;
// Let the CPU run
dbg_i2c_wr(CPU_CTL, 16'h0002);
repeat(300) @(posedge dco_clk);
dbg_i2c_wr(CPU_CTL, 16'h0000);
dbg_i2c_wr(MEM_DATA, 16'haa55);
dbg_i2c_rd(CPU_CTL);
if (dbg_i2c_buf !== 16'h0000) tb_error("====== CPU_CTL write access failed - test 10 =====");
dbg_i2c_rd(MEM_DATA);
if (dbg_i2c_buf !== 16'haa55) tb_error("====== MEM_DATA write access failed - test 11 =====");
test_nr = 7;
@(posedge dco_clk); // Generates POR
reset_n = 1'b0;
repeat(2) @(posedge dco_clk);
reset_n = 1'b1;
// Make sure that the register was reseted
if (r14 !== 16'h0000) tb_error("====== CPU was not reseted with RESET_N - test 12 =====");
repeat(2) @(posedge dco_clk);
test_nr = 8;
// Check CPU_CTL reset value
dbg_i2c_rd(CPU_CTL);
`ifdef DBG_RST_BRK_EN
if (dbg_i2c_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value - test 8 =====");
`else
if (dbg_i2c_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value - test 8 =====");
`endif
dbg_i2c_rd(MEM_DATA);
if (dbg_i2c_buf !== 16'h0000) tb_error("====== MEM_DATA read access failed - test 9 =====");
// Let the CPU run
dbg_i2c_wr(CPU_CTL, 16'h0002);
test_nr = 9;
// Generate IRQ to terminate the test pattern
irq[`IRQ_NR-15] = 1'b1;
@(r13);
irq[`IRQ_NR-15] = 1'b0;
stimulus_done = 1;
`else
tb_skip_finish("| (this test is not supported in FPGA mode) |");
`endif
`else
tb_skip_finish("| (serial debug interface I2C not included) |");
`endif
`else
tb_skip_finish("| (serial debug interface not included) |");
`endif
end
|
/*
* MBus Copyright 2015 Regents of the University of Michigan
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* Last modified date: 03/16 '13
* Last modified by: Ye-sheng Kuo <[email protected]>
* Last modified content: Newly added
* --------------------------------------------------------------------------
* IMPORTANT: This module should be always on, do NOT connect this module
* to power gated domain. This module sits between Bus controller
* and layer controller
* --------------------------------------------------------------------------
* */
`include "include/mbus_def.v"
module mbus_regular_isolation(
input RELEASE_ISO_FROM_SLEEP_CTRL,
// LC stands for Layer Controller
// Interrconnect between this module and LC
input [`ADDR_WIDTH-1:0] TX_ADDR_FROM_LC,
input [`DATA_WIDTH-1:0] TX_DATA_FROM_LC,
input TX_PEND_FROM_LC,
input TX_REQ_FROM_LC,
input PRIORITY_FROM_LC,
output reg TX_ACK_TO_LC,
output reg [`ADDR_WIDTH-1:0] RX_ADDR_TO_LC,
output reg [`DATA_WIDTH-1:0] RX_DATA_TO_LC,
output reg RX_REQ_TO_LC,
input RX_ACK_FROM_LC,
output reg RX_FAIL_TO_LC,
output reg RX_PEND_TO_LC,
output reg TX_FAIL_TO_LC,
output reg TX_SUCC_TO_LC,
input TX_RESP_ACK_FROM_LC,
output reg RX_BROADCAST_TO_LC,
// BC stands for Bus Controller
// Interrconnect between this module and BC
output reg [`ADDR_WIDTH-1:0] TX_ADDR_TO_BC,
output reg [`DATA_WIDTH-1:0] TX_DATA_TO_BC,
output reg TX_PEND_TO_BC,
output reg TX_REQ_TO_BC,
output reg PRIORITY_TO_BC,
input TX_ACK_FROM_BC,
input [`ADDR_WIDTH-1:0] RX_ADDR_FROM_BC,
input [`DATA_WIDTH-1:0] RX_DATA_FROM_BC,
input RX_REQ_FROM_BC,
output reg RX_ACK_TO_BC,
input RX_FAIL_FROM_BC,
input RX_PEND_FROM_BC,
input TX_FAIL_FROM_BC,
input TX_SUCC_FROM_BC,
output reg TX_RESP_ACK_TO_BC,
input RX_BROADCAST_FROM_BC,
input POWER_ON_FROM_BC,
input RELEASE_CLK_FROM_BC,
input RELEASE_RST_FROM_BC,
input RELEASE_ISO_FROM_BC,
// use this to isolate signals between layer controller and CPU/MEM etc.
output reg RELEASE_ISO_FROM_BC_MASKED,
output reg POWER_ON_TO_LC,
output reg RELEASE_CLK_TO_LC,
output reg RELEASE_RST_TO_LC
);
parameter HOLD = `IO_HOLD; // During sleep
parameter RELEASE = `IO_RELEASE; // During wake-up
always @ *
begin
if (RELEASE_ISO_FROM_SLEEP_CTRL==HOLD)
begin
POWER_ON_TO_LC = HOLD;
RELEASE_CLK_TO_LC = HOLD;
RELEASE_RST_TO_LC = HOLD;
end
else
begin
POWER_ON_TO_LC = POWER_ON_FROM_BC;
RELEASE_CLK_TO_LC = RELEASE_CLK_FROM_BC;
RELEASE_RST_TO_LC = RELEASE_RST_FROM_BC;
end
end
always @ *
begin
if (RELEASE_ISO_FROM_SLEEP_CTRL==HOLD)
begin
TX_ACK_TO_LC = 0;
RX_ADDR_TO_LC = 0;
RX_DATA_TO_LC = 0;
RX_REQ_TO_LC = 0;
RX_FAIL_TO_LC = 0;
RX_PEND_TO_LC = 0;
TX_FAIL_TO_LC = 0;
TX_SUCC_TO_LC = 0;
RX_BROADCAST_TO_LC = 0;
RELEASE_ISO_FROM_BC_MASKED = HOLD;
end
else
begin
TX_ACK_TO_LC = TX_ACK_FROM_BC ;
RX_ADDR_TO_LC = RX_ADDR_FROM_BC;
RX_DATA_TO_LC = RX_DATA_FROM_BC;
RX_REQ_TO_LC = RX_REQ_FROM_BC;
RX_FAIL_TO_LC = RX_FAIL_FROM_BC;
RX_PEND_TO_LC = RX_PEND_FROM_BC;
TX_FAIL_TO_LC = TX_FAIL_FROM_BC;
TX_SUCC_TO_LC = TX_SUCC_FROM_BC;
RX_BROADCAST_TO_LC = RX_BROADCAST_FROM_BC;
RELEASE_ISO_FROM_BC_MASKED = RELEASE_ISO_FROM_BC;
end
end
always @ *
begin
if (RELEASE_ISO_FROM_BC_MASKED==HOLD)
begin
TX_ADDR_TO_BC = 0;
TX_DATA_TO_BC = 0;
TX_PEND_TO_BC = 0;
TX_REQ_TO_BC = 0;
PRIORITY_TO_BC = 0;
RX_ACK_TO_BC = 0;
TX_RESP_ACK_TO_BC=0;
end
else
begin
TX_ADDR_TO_BC = TX_ADDR_FROM_LC;
TX_DATA_TO_BC = TX_DATA_FROM_LC;
TX_PEND_TO_BC = TX_PEND_FROM_LC;
TX_REQ_TO_BC = TX_REQ_FROM_LC;
PRIORITY_TO_BC = PRIORITY_FROM_LC;
RX_ACK_TO_BC = RX_ACK_FROM_LC;
TX_RESP_ACK_TO_BC=TX_RESP_ACK_FROM_LC;
end
end
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlslice:1.0
// IP Revision: 0
(* X_CORE_INFO = "xlslice,Vivado 2016.2" *)
(* CHECK_LICENSE_TYPE = "design_1_xlslice_7_2,xlslice,{}" *)
(* CORE_GENERATION_INFO = "design_1_xlslice_7_2,xlslice,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlslice,x_ipVersion=1.0,x_ipCoreRevision=0,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,DIN_WIDTH=48,DIN_FROM=44,DIN_TO=29}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xlslice_7_2 (
Din,
Dout
);
input wire [47 : 0] Din;
output wire [15 : 0] Dout;
xlslice #(
.DIN_WIDTH(48),
.DIN_FROM(44),
.DIN_TO(29)
) inst (
.Din(Din),
.Dout(Dout)
);
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Generic single-channel AXI FIFO
// Synchronous FIFO is implemented using either LUTs (SRL) or BRAM.
// Transfers received on the AXI slave port are pushed onto the FIFO.
// FIFO output, when available, is presented on the AXI master port and
// popped when the master port responds (M_READY).
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
// Structure:
// axic_fifo
// fifo_gen
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_data_fifo_v2_1_axic_fifo #
(
parameter C_FAMILY = "virtex6",
parameter integer C_FIFO_DEPTH_LOG = 5, // FIFO depth = 2**C_FIFO_DEPTH_LOG
// Range = [5:9] when TYPE="lut",
// Range = [5:12] when TYPE="bram",
parameter integer C_FIFO_WIDTH = 64, // Width of payload [1:512]
parameter C_FIFO_TYPE = "lut" // "lut" = LUT (SRL) based,
// "bram" = BRAM based
)
(
// Global inputs
input wire ACLK, // Clock
input wire ARESET, // Reset
// Slave Port
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Payload (may be any set of channel signals)
input wire S_VALID, // FIFO push
output wire S_READY, // FIFO not full
// Master Port
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Payload
output wire M_VALID, // FIFO not empty
input wire M_READY // FIFO pop
);
axi_data_fifo_v2_1_fifo_gen #(
.C_FAMILY(C_FAMILY),
.C_COMMON_CLOCK(1),
.C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
.C_FIFO_WIDTH(C_FIFO_WIDTH),
.C_FIFO_TYPE(C_FIFO_TYPE))
inst (
.clk(ACLK),
.rst(ARESET),
.wr_clk(1'b0),
.wr_en(S_VALID),
.wr_ready(S_READY),
.wr_data(S_MESG),
.rd_clk(1'b0),
.rd_en(M_READY),
.rd_valid(M_VALID),
.rd_data(M_MESG));
endmodule
|
//Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module pll (
// inputs:
address,
chipselect,
clk,
read,
reset_n,
write,
writedata,
// outputs:
c0,
c1,
readdata,
resetrequest
)
;
output c0;
output c1;
output [ 15: 0] readdata;
output resetrequest;
input [ 2: 0] address;
input chipselect;
input clk;
input read;
input reset_n;
input write;
input [ 15: 0] writedata;
wire always_one;
wire areset_n;
wire c0;
wire c1;
wire control_reg_en;
wire [ 15: 0] control_reg_in;
reg [ 15: 0] control_reg_out;
reg count_done;
reg [ 5: 0] countup;
wire inclk0;
reg not_areset /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON" */;
wire [ 15: 0] readdata;
wire resetrequest;
wire [ 15: 0] status_reg_in;
reg [ 15: 0] status_reg_out;
initial
begin
countup = 1'b0;
count_done = 1'b0;
not_areset = 1'b0;
end
assign status_reg_in[15 : 1] = 15'b000000000000000;
assign resetrequest = ~count_done;
//Up counter that stops counting when it reaches max value
always @(posedge clk or negedge areset_n)
begin
if (areset_n == 0)
countup <= 0;
else if (count_done != 1'b1)
countup <= countup + 1;
end
//Count_done signal, which is also the resetrequest_n
always @(posedge clk or negedge areset_n)
begin
if (areset_n == 0)
count_done <= 0;
else if (countup == 6'b111111)
count_done <= 1'b1;
end
//Creates a reset generator that will reset internal counters that are independent of global system reset
always @(posedge clk or negedge 1'b1)
begin
if (1'b1 == 0)
not_areset <= 0;
else
not_areset <= always_one;
end
assign always_one = 1'b1;
assign status_reg_in[0] = 1'b0;
assign areset_n = not_areset;
assign inclk0 = clk;
//Mux status and control registers to the readdata output using address as select
assign readdata = (address[0] == 0)? status_reg_out :
({control_reg_out[15 : 2], ~control_reg_out[1], control_reg_out[0]} );
//Status register - Read-Only
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
status_reg_out <= 0;
else
status_reg_out <= status_reg_in;
end
//Control register - R/W
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
control_reg_out <= 0;
else if (control_reg_en)
control_reg_out <= {control_reg_in[15 : 2], ~control_reg_in[1], control_reg_in[0]};
end
assign control_reg_in = writedata;
assign control_reg_en = (address == 3'b001) && write && chipselect;
//s1, which is an e_avalon_slave
altpllpll the_pll
(
.c0 (c0),
.c1 (c1),
.inclk0 (inclk0)
);
endmodule
|
module convert_30to15_fifo(
input wire rst, // reset
input wire clk, // clock input
input wire clkx2, // 2x clock input
input wire [29:0] datain, // input data for 2:1 serialisation
output wire [14:0] dataout); // 5-bit data out
////////////////////////////////////////////////////
// Here we instantiate a 16x10 Dual Port RAM
// and fill first it with data aligned to
// clk domain
////////////////////////////////////////////////////
wire [3:0] wa; // RAM read address
reg [3:0] wa_d; // RAM read address
wire [3:0] ra; // RAM read address
reg [3:0] ra_d; // RAM read address
wire [29:0] dataint; // RAM output
parameter ADDR0 = 4'b0000;
parameter ADDR1 = 4'b0001;
parameter ADDR2 = 4'b0010;
parameter ADDR3 = 4'b0011;
parameter ADDR4 = 4'b0100;
parameter ADDR5 = 4'b0101;
parameter ADDR6 = 4'b0110;
parameter ADDR7 = 4'b0111;
parameter ADDR8 = 4'b1000;
parameter ADDR9 = 4'b1001;
parameter ADDR10 = 4'b1010;
parameter ADDR11 = 4'b1011;
parameter ADDR12 = 4'b1100;
parameter ADDR13 = 4'b1101;
parameter ADDR14 = 4'b1110;
parameter ADDR15 = 4'b1111;
always@(wa) begin
case (wa)
ADDR0 : wa_d = ADDR1 ;
ADDR1 : wa_d = ADDR2 ;
ADDR2 : wa_d = ADDR3 ;
ADDR3 : wa_d = ADDR4 ;
ADDR4 : wa_d = ADDR5 ;
ADDR5 : wa_d = ADDR6 ;
ADDR6 : wa_d = ADDR7 ;
ADDR7 : wa_d = ADDR8 ;
ADDR8 : wa_d = ADDR9 ;
ADDR9 : wa_d = ADDR10;
ADDR10 : wa_d = ADDR11;
ADDR11 : wa_d = ADDR12;
ADDR12 : wa_d = ADDR13;
ADDR13 : wa_d = ADDR14;
ADDR14 : wa_d = ADDR15;
default : wa_d = ADDR0;
endcase
end
FDC fdc_wa0 (.C(clk), .D(wa_d[0]), .CLR(rst), .Q(wa[0]));
FDC fdc_wa1 (.C(clk), .D(wa_d[1]), .CLR(rst), .Q(wa[1]));
FDC fdc_wa2 (.C(clk), .D(wa_d[2]), .CLR(rst), .Q(wa[2]));
FDC fdc_wa3 (.C(clk), .D(wa_d[3]), .CLR(rst), .Q(wa[3]));
//Dual Port fifo to bridge data from clk to clkx2
DRAM16XN #(.data_width(30))
fifo_u (
.DATA_IN(datain),
.ADDRESS(wa),
.ADDRESS_DP(ra),
.WRITE_EN(1'b1),
.CLK(clk),
.O_DATA_OUT(),
.O_DATA_OUT_DP(dataint));
/////////////////////////////////////////////////////////////////
// Here starts clk2x domain for fifo read out
// FIFO read is set to be once every 2 cycles of clk2x in order
// to keep up pace with the fifo write speed
// Also FIFO read reset is delayed a bit in order to avoid
// underflow.
/////////////////////////////////////////////////////////////////
always@(ra) begin
case (ra)
ADDR0 : ra_d = ADDR1 ;
ADDR1 : ra_d = ADDR2 ;
ADDR2 : ra_d = ADDR3 ;
ADDR3 : ra_d = ADDR4 ;
ADDR4 : ra_d = ADDR5 ;
ADDR5 : ra_d = ADDR6 ;
ADDR6 : ra_d = ADDR7 ;
ADDR7 : ra_d = ADDR8 ;
ADDR8 : ra_d = ADDR9 ;
ADDR9 : ra_d = ADDR10;
ADDR10 : ra_d = ADDR11;
ADDR11 : ra_d = ADDR12;
ADDR12 : ra_d = ADDR13;
ADDR13 : ra_d = ADDR14;
ADDR14 : ra_d = ADDR15;
default : ra_d = ADDR0;
endcase
end
wire rstsync, rstsync_q, rstp;
(* ASYNC_REG = "TRUE" *) FDP fdp_rst (.C(clkx2), .D(rst), .PRE(rst), .Q(rstsync));
FD fd_rstsync (.C(clkx2), .D(rstsync), .Q(rstsync_q));
FD fd_rstp (.C(clkx2), .D(rstsync_q), .Q(rstp));
wire sync;
FDR sync_gen (.Q (sync), .C (clkx2), .R(rstp), .D(~sync));
FDRE fdc_ra0 (.C(clkx2), .D(ra_d[0]), .R(rstp), .CE(sync), .Q(ra[0]));
FDRE fdc_ra1 (.C(clkx2), .D(ra_d[1]), .R(rstp), .CE(sync), .Q(ra[1]));
FDRE fdc_ra2 (.C(clkx2), .D(ra_d[2]), .R(rstp), .CE(sync), .Q(ra[2]));
FDRE fdc_ra3 (.C(clkx2), .D(ra_d[3]), .R(rstp), .CE(sync), .Q(ra[3]));
wire [29:0] db;
FDE fd_db0 (.C(clkx2), .D(dataint[0]), .CE(sync), .Q(db[0]));
FDE fd_db1 (.C(clkx2), .D(dataint[1]), .CE(sync), .Q(db[1]));
FDE fd_db2 (.C(clkx2), .D(dataint[2]), .CE(sync), .Q(db[2]));
FDE fd_db3 (.C(clkx2), .D(dataint[3]), .CE(sync), .Q(db[3]));
FDE fd_db4 (.C(clkx2), .D(dataint[4]), .CE(sync), .Q(db[4]));
FDE fd_db5 (.C(clkx2), .D(dataint[5]), .CE(sync), .Q(db[5]));
FDE fd_db6 (.C(clkx2), .D(dataint[6]), .CE(sync), .Q(db[6]));
FDE fd_db7 (.C(clkx2), .D(dataint[7]), .CE(sync), .Q(db[7]));
FDE fd_db8 (.C(clkx2), .D(dataint[8]), .CE(sync), .Q(db[8]));
FDE fd_db9 (.C(clkx2), .D(dataint[9]), .CE(sync), .Q(db[9]));
FDE fd_db10 (.C(clkx2), .D(dataint[10]), .CE(sync), .Q(db[10]));
FDE fd_db11 (.C(clkx2), .D(dataint[11]), .CE(sync), .Q(db[11]));
FDE fd_db12 (.C(clkx2), .D(dataint[12]), .CE(sync), .Q(db[12]));
FDE fd_db13 (.C(clkx2), .D(dataint[13]), .CE(sync), .Q(db[13]));
FDE fd_db14 (.C(clkx2), .D(dataint[14]), .CE(sync), .Q(db[14]));
FDE fd_db15 (.C(clkx2), .D(dataint[15]), .CE(sync), .Q(db[15]));
FDE fd_db16 (.C(clkx2), .D(dataint[16]), .CE(sync), .Q(db[16]));
FDE fd_db17 (.C(clkx2), .D(dataint[17]), .CE(sync), .Q(db[17]));
FDE fd_db18 (.C(clkx2), .D(dataint[18]), .CE(sync), .Q(db[18]));
FDE fd_db19 (.C(clkx2), .D(dataint[19]), .CE(sync), .Q(db[19]));
FDE fd_db20 (.C(clkx2), .D(dataint[20]), .CE(sync), .Q(db[20]));
FDE fd_db21 (.C(clkx2), .D(dataint[21]), .CE(sync), .Q(db[21]));
FDE fd_db22 (.C(clkx2), .D(dataint[22]), .CE(sync), .Q(db[22]));
FDE fd_db23 (.C(clkx2), .D(dataint[23]), .CE(sync), .Q(db[23]));
FDE fd_db24 (.C(clkx2), .D(dataint[24]), .CE(sync), .Q(db[24]));
FDE fd_db25 (.C(clkx2), .D(dataint[25]), .CE(sync), .Q(db[25]));
FDE fd_db26 (.C(clkx2), .D(dataint[26]), .CE(sync), .Q(db[26]));
FDE fd_db27 (.C(clkx2), .D(dataint[27]), .CE(sync), .Q(db[27]));
FDE fd_db28 (.C(clkx2), .D(dataint[28]), .CE(sync), .Q(db[28]));
FDE fd_db29 (.C(clkx2), .D(dataint[29]), .CE(sync), .Q(db[29]));
wire [14:0] mux;
assign mux = (~sync) ? db[14:0] : db[29:15];
FD fd_out0 (.C(clkx2), .D(mux[0]), .Q(dataout[0]));
FD fd_out1 (.C(clkx2), .D(mux[1]), .Q(dataout[1]));
FD fd_out2 (.C(clkx2), .D(mux[2]), .Q(dataout[2]));
FD fd_out3 (.C(clkx2), .D(mux[3]), .Q(dataout[3]));
FD fd_out4 (.C(clkx2), .D(mux[4]), .Q(dataout[4]));
FD fd_out5 (.C(clkx2), .D(mux[5]), .Q(dataout[5]));
FD fd_out6 (.C(clkx2), .D(mux[6]), .Q(dataout[6]));
FD fd_out7 (.C(clkx2), .D(mux[7]), .Q(dataout[7]));
FD fd_out8 (.C(clkx2), .D(mux[8]), .Q(dataout[8]));
FD fd_out9 (.C(clkx2), .D(mux[9]), .Q(dataout[9]));
FD fd_out10 (.C(clkx2), .D(mux[10]), .Q(dataout[10]));
FD fd_out11 (.C(clkx2), .D(mux[11]), .Q(dataout[11]));
FD fd_out12 (.C(clkx2), .D(mux[12]), .Q(dataout[12]));
FD fd_out13 (.C(clkx2), .D(mux[13]), .Q(dataout[13]));
FD fd_out14 (.C(clkx2), .D(mux[14]), .Q(dataout[14]));
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_phy_v2_3_phy_ocd_edge.v
// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose: Detects and stores edges as the test pattern is scanned via
// manipulating the phaser out stage 3 taps.
//
// Scanning always proceeds from the left to the right. For more
// on the scanning algorithm, see the _po_cntlr block.
//
// Four scan results are reported. The edges at fuzz2zero,
// zero2fuzz, fuzz2oneeighty, and oneeighty2fuzz. Each edge
// has a 6 bit stg3 tap value and a valid bit. The valid bits
// are reset before the scan starts.
//
// Once reset_scan is set low, this block waits for the first
// samp_done while scanning_right. This marks the left end
// of the scan, and initializes prev_samp_r with samp_result and
// sets the prev_samp_r valid bit to one.
//
// At each subesquent samp_done, the previous samp is compared
// to the current samp_result. The case statement details how
// edges are identified.
//
// Original design assumed fuzz between valid regions. Design
// has been updated to tolerate transitions from zero to oneeight
// and vice-versa without fuzz in between.
//
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_3_ddr_phy_ocd_edge #
(parameter TCQ = 100)
(/*AUTOARG*/
// Outputs
scan_right, z2f, f2z, o2f, f2o, zero2fuzz, fuzz2zero,
oneeighty2fuzz, fuzz2oneeighty,
// Inputs
clk, samp_done, phy_rddata_en_2, reset_scan, scanning_right,
samp_result, stg3
);
localparam [1:0] NULL = 2'b11,
FUZZ = 2'b00,
ONEEIGHTY = 2'b10,
ZERO = 2'b01;
input clk;
input samp_done;
input phy_rddata_en_2;
wire samp_valid = samp_done && phy_rddata_en_2;
input reset_scan;
input scanning_right;
reg prev_samp_valid_ns, prev_samp_valid_r;
always @(posedge clk) prev_samp_valid_r <= #TCQ prev_samp_valid_ns;
always @(*) begin
prev_samp_valid_ns = prev_samp_valid_r;
if (reset_scan) prev_samp_valid_ns = 1'b0;
else if (samp_valid) prev_samp_valid_ns = 1'b1;
end
input [1:0] samp_result;
reg [1:0] prev_samp_ns, prev_samp_r;
always @(posedge clk) prev_samp_r <= #TCQ prev_samp_ns;
always @(*)
if (samp_valid) prev_samp_ns = samp_result;
else prev_samp_ns = prev_samp_r;
reg scan_right_ns, scan_right_r;
always @(posedge clk) scan_right_r <= #TCQ scan_right_ns;
output scan_right;
assign scan_right = scan_right_r;
input [5:0] stg3;
reg z2f_ns, z2f_r, f2z_ns, f2z_r, o2f_ns, o2f_r, f2o_ns, f2o_r;
always @(posedge clk) z2f_r <= #TCQ z2f_ns;
always @(posedge clk) f2z_r <= #TCQ f2z_ns;
always @(posedge clk) o2f_r <= #TCQ o2f_ns;
always @(posedge clk) f2o_r <= #TCQ f2o_ns;
output z2f, f2z, o2f, f2o;
assign z2f = z2f_r;
assign f2z = f2z_r;
assign o2f = o2f_r;
assign f2o = f2o_r;
reg [5:0] zero2fuzz_ns, zero2fuzz_r, fuzz2zero_ns, fuzz2zero_r,
oneeighty2fuzz_ns, oneeighty2fuzz_r, fuzz2oneeighty_ns, fuzz2oneeighty_r;
always @(posedge clk) zero2fuzz_r <= #TCQ zero2fuzz_ns;
always @(posedge clk) fuzz2zero_r <= #TCQ fuzz2zero_ns;
always @(posedge clk) oneeighty2fuzz_r <= #TCQ oneeighty2fuzz_ns;
always @(posedge clk) fuzz2oneeighty_r <= #TCQ fuzz2oneeighty_ns;
output [5:0] zero2fuzz, fuzz2zero, oneeighty2fuzz, fuzz2oneeighty;
assign zero2fuzz = zero2fuzz_r;
assign fuzz2zero = fuzz2zero_r;
assign oneeighty2fuzz = oneeighty2fuzz_r;
assign fuzz2oneeighty = fuzz2oneeighty_r;
always @(*) begin
z2f_ns = z2f_r;
f2z_ns = f2z_r;
o2f_ns = o2f_r;
f2o_ns = f2o_r;
zero2fuzz_ns = zero2fuzz_r;
fuzz2zero_ns = fuzz2zero_r;
oneeighty2fuzz_ns = oneeighty2fuzz_r;
fuzz2oneeighty_ns = fuzz2oneeighty_r;
scan_right_ns = 1'b0;
if (reset_scan) begin
z2f_ns = 1'b0;
f2z_ns = 1'b0;
o2f_ns = 1'b0;
f2o_ns = 1'b0;
end
else if (samp_valid && prev_samp_valid_r)
case (prev_samp_r)
FUZZ :
if (scanning_right) begin
if (samp_result == ZERO) begin
fuzz2zero_ns = stg3;
f2z_ns = 1'b1;
end
if (samp_result == ONEEIGHTY) begin
fuzz2oneeighty_ns = stg3;
f2o_ns = 1'b1;
end
end
ZERO : begin
if (samp_result == FUZZ || samp_result == ONEEIGHTY) scan_right_ns = !scanning_right;
if (scanning_right) begin
if (samp_result == FUZZ) begin
zero2fuzz_ns = stg3 - 6'b1;
z2f_ns = 1'b1;
end
if (samp_result == ONEEIGHTY) begin
zero2fuzz_ns = stg3 - 6'b1;
z2f_ns = 1'b1;
fuzz2oneeighty_ns = stg3;
f2o_ns = 1'b1;
end
end
end
ONEEIGHTY :
if (scanning_right) begin
if (samp_result == FUZZ) begin
oneeighty2fuzz_ns = stg3 - 6'b1;
o2f_ns = 1'b1;
end
if (samp_result == ZERO)
if (f2o_r) begin
oneeighty2fuzz_ns = stg3 - 6'b1;
o2f_ns = 1'b1;
end else begin
fuzz2zero_ns = stg3;
f2z_ns = 1'b1;
end
end // if (scanning_right)
// NULL : // Should never happen
endcase
end
endmodule // mig_7series_v2_3_ddr_phy_ocd_edge
|
// file: mmcm_mkid_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge LOCKED)
module mmcm_mkid_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 7.812*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bits of the sampling counters
wire [4:1] COUNT;
// Status and control signals
wire LOCKED;
reg COUNTER_RESET = 0;
wire [4:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
real period1;
real ref_period1;
localparam ref_period1_clkin1 = (7.812*1*8.000*1000/8.000);
time prev_rise1;
real period2;
real ref_period2;
localparam ref_period2_clkin1 = (7.812*1*8*1000/8.000);
time prev_rise2;
real period3;
real ref_period3;
localparam ref_period3_clkin1 = (7.812*1*8*1000/8.000);
time prev_rise3;
real period4;
real ref_period4;
localparam ref_period4_clkin1 = (7.812*1*8*1000/8.000);
time prev_rise4;
reg [13:0] timeout_counter = 14'b00000000000000;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
$display ("Timing checks are not valid");
COUNTER_RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*19.5)
COUNTER_RESET = 0;
#(PER1*1)
$display ("Timing checks are valid");
test_phase = "counting";
#(PER1*COUNT_PHASE);
if ((period1 -ref_period1_clkin1) <= 100 && (period1 -ref_period1_clkin1) >= -100) begin
$display("Freq of CLK_OUT[1] ( in MHz ) : %0f\n", 1000000/period1);
end else
$display("ERROR: Freq of CLK_OUT[1] is not correct");
if ((period2 -ref_period2_clkin1) <= 100 && (period2 -ref_period2_clkin1) >= -100) begin
$display("Freq of CLK_OUT[2] ( in MHz ) : %0f\n", 1000000/period2);
end else
$display("ERROR: Freq of CLK_OUT[2] is not correct");
if ((period3 -ref_period3_clkin1) <= 100 && (period3 -ref_period3_clkin1) >= -100) begin
$display("Freq of CLK_OUT[3] ( in MHz ) : %0f\n", 1000000/period3);
end else
$display("ERROR: Freq of CLK_OUT[3] is not correct");
if ((period4 -ref_period4_clkin1) <= 100 && (period4 -ref_period4_clkin1) >= -100) begin
$display("Freq of CLK_OUT[4] ( in MHz ) : %0f\n", 1000000/period4);
end else
$display("ERROR: Freq of CLK_OUT[4] is not correct");
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
always@(posedge CLK_IN1) begin
timeout_counter <= timeout_counter + 1'b1;
if (timeout_counter == 14'b10000000000000) begin
if (LOCKED != 1'b1) begin
$display("ERROR : NO LOCK signal");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
end
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
mmcm_mkid_exdes
dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.LOCKED (LOCKED));
// Freq Check
initial
prev_rise1 = 0;
always @(posedge CLK_OUT[1])
begin
if (prev_rise1 != 0)
period1 = $time - prev_rise1;
prev_rise1 = $time;
end
initial
prev_rise2 = 0;
always @(posedge CLK_OUT[2])
begin
if (prev_rise2 != 0)
period2 = $time - prev_rise2;
prev_rise2 = $time;
end
initial
prev_rise3 = 0;
always @(posedge CLK_OUT[3])
begin
if (prev_rise3 != 0)
period3 = $time - prev_rise3;
prev_rise3 = $time;
end
initial
prev_rise4 = 0;
always @(posedge CLK_OUT[4])
begin
if (prev_rise4 != 0)
period4 = $time - prev_rise4;
prev_rise4 = $time;
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge ([email protected])
// div_pipelined.v
// Created: 4.3.2012
// Modified: 4.5.2012
//
// Testbench for div_pipelined.v
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module t_div_pipelined();
reg clk, start, reset_n;
reg [7:0] dividend, divisor;
wire data_valid, div_by_zero;
wire [7:0] quotient, quotient_correct;
parameter
BITS = 8;
div_pipelined
#(
.BITS(BITS)
)
div_pipelined
(
.clk(clk),
.reset_n(reset_n),
.dividend(dividend),
.divisor(divisor),
.quotient(quotient),
.div_by_zero(div_by_zero),
// .quotient_correct(quotient_correct),
.start(start),
.data_valid(data_valid)
);
initial begin
#10 reset_n = 0;
#50 reset_n = 1;
#1
clk = 0;
dividend = -1;
divisor = 127;
#1000 $finish;
end
// always
// #20 dividend = dividend + 1;
always begin
#10 divisor = divisor - 1; start = 1;
#10 start = 0;
end
always
#5 clk = ~clk;
endmodule
|
module SimpleMmuTest;
`include "Framework.v"
reg reset;
reg clk;
reg [31:0] addrA;
reg [31:0] addrB;
reg writeEnable = 0;
reg [7:0] dataIn;
reg requestA;
reg requestB;
wire [7:0] outA;
wire [7:0] outB;
wire busyA;
wire busyB;
wire [15:0] displayIn = 0;
wire [31:0] displayAddr;
wire displayWE;
Display dsp(clk, displayIn);
wire [31:0] mmioInB;
wire [31:0] mmioAddrB;
wire mmioWEB;
SimpleMmu mmu(clk, reset, addrA, addrB, writeEnable, dataIn, requestA, requestB, outA, outB, busyA, busyB,
displayIn,displayAddr,displayWE, mmioInB, mmioAddrB, mmioWEB);
always #10 clk = ~clk;
integer i;
integer j;
initial begin
$dumpfile("timing.vcd");
$dumpvars(0,mmu);
reset = 1;
clk = 0;
writeEnable = 0;
#20 reset = 0;
for(i = 0; i < 16; i = i + 1)
begin
addrA = i;
addrB = i;
requestA = 1;
requestB = 1;
@(negedge busyA) $display("Address: 0x%h = 0x%h, 0x%h", i, outA, outB);
requestA = 0;
requestB = 0;
end
j = 0;
for(i = 360; i < 375; i = i + 1)
begin
addrA = i;
dataIn = j;
writeEnable = 1;
requestA = 1;
#100 writeEnable = 0;
requestA = 0;
j = j + 1;
end
for(i = 360; i < 375; i = i + 1)
begin
addrA = i;
requestA = 1;
#100 $display("Address: 0x%h = 0x%h", i, outA);
requestA = 0;
end
$finish;
end
endmodule
|
/********************************************/
/* generic_output.v */
/* A generic implementation of outputs */
/* (LEDs, ...) */
/* */
/* 2012, [email protected] */
/********************************************/
module generic_output #(
parameter OW = 1, // output width
parameter DS = 1'b0, // default (off) state
parameter DBG = 0 // debug output
)(
output wire [ OW-1:0] i
);
////////////////////////////////////////
// logic //
////////////////////////////////////////
reg [ OW-1:0] state_old = {OW{DS}};
always @ (i) begin
if (i != state_old) begin
if (DBG) $display ("BENCH : %M : %t : changing state from [%b] to [%b].", $time, state_old, i);
state_old = #1 i;
end
end
////////////////////////////////////////
// tasks //
////////////////////////////////////////
//// read ////
task read;
output [ OW-1:0] data;
begin
data = state_old;
end
endtask
endmodule
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream rate limiter
*/
module axis_rate_limit #
(
parameter DATA_WIDTH = 8
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
input wire input_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
output wire output_axis_tuser,
/*
* Configuration
*/
input wire [7:0] rate_num,
input wire [7:0] rate_denom,
input wire rate_by_frame
);
// internal datapath
reg [DATA_WIDTH-1:0] output_axis_tdata_int;
reg output_axis_tvalid_int;
reg output_axis_tready_int = 0;
reg output_axis_tlast_int;
reg output_axis_tuser_int;
wire output_axis_tready_int_early;
reg [23:0] acc_reg = 0, acc_next;
reg pause;
reg frame_reg = 0, frame_next;
reg input_axis_tready_reg = 0, input_axis_tready_next;
assign input_axis_tready = input_axis_tready_reg;
always @* begin
acc_next = acc_reg;
pause = 0;
frame_next = frame_reg & ~input_axis_tlast;
if (acc_reg >= rate_num) begin
acc_next = acc_reg - rate_num;
end
if (input_axis_tready & input_axis_tvalid) begin
// read input
frame_next = ~input_axis_tlast;
acc_next = acc_reg + (rate_denom - rate_num);
end
if (acc_next >= rate_num) begin
if (rate_by_frame) begin
pause = ~frame_next;
end else begin
pause = 1;
end
end
input_axis_tready_next = output_axis_tready_int_early & ~pause;
output_axis_tdata_int = input_axis_tdata;
output_axis_tvalid_int = input_axis_tvalid & input_axis_tready;
output_axis_tlast_int = input_axis_tlast;
output_axis_tuser_int = input_axis_tuser;
end
always @(posedge clk or posedge rst) begin
if (rst) begin
acc_reg <= 0;
frame_reg <= 0;
input_axis_tready_reg <= 0;
end else begin
acc_reg <= acc_next;
frame_reg <= frame_next;
input_axis_tready_reg <= input_axis_tready_next;
end
end
// output datapath logic
reg [DATA_WIDTH-1:0] output_axis_tdata_reg = 0;
reg output_axis_tvalid_reg = 0;
reg output_axis_tlast_reg = 0;
reg output_axis_tuser_reg = 0;
reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = 0;
reg temp_axis_tvalid_reg = 0;
reg temp_axis_tlast_reg = 0;
reg temp_axis_tuser_reg = 0;
assign output_axis_tdata = output_axis_tdata_reg;
assign output_axis_tvalid = output_axis_tvalid_reg;
assign output_axis_tlast = output_axis_tlast_reg;
assign output_axis_tuser = output_axis_tuser_reg;
// enable ready input next cycle if output is ready or if there is space in both output registers or if there is space in the temp register that will not be filled next cycle
assign output_axis_tready_int_early = output_axis_tready | (~temp_axis_tvalid_reg & ~output_axis_tvalid_reg) | (~temp_axis_tvalid_reg & ~output_axis_tvalid_int);
always @(posedge clk or posedge rst) begin
if (rst) begin
output_axis_tdata_reg <= 0;
output_axis_tvalid_reg <= 0;
output_axis_tlast_reg <= 0;
output_axis_tuser_reg <= 0;
output_axis_tready_int <= 0;
temp_axis_tdata_reg <= 0;
temp_axis_tvalid_reg <= 0;
temp_axis_tlast_reg <= 0;
temp_axis_tuser_reg <= 0;
end else begin
// transfer sink ready state to source
output_axis_tready_int <= output_axis_tready_int_early;
if (output_axis_tready_int) begin
// input is ready
if (output_axis_tready | ~output_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
output_axis_tdata_reg <= output_axis_tdata_int;
output_axis_tvalid_reg <= output_axis_tvalid_int;
output_axis_tlast_reg <= output_axis_tlast_int;
output_axis_tuser_reg <= output_axis_tuser_int;
end else begin
// output is not ready, store input in temp
temp_axis_tdata_reg <= output_axis_tdata_int;
temp_axis_tvalid_reg <= output_axis_tvalid_int;
temp_axis_tlast_reg <= output_axis_tlast_int;
temp_axis_tuser_reg <= output_axis_tuser_int;
end
end else if (output_axis_tready) begin
// input is not ready, but output is ready
output_axis_tdata_reg <= temp_axis_tdata_reg;
output_axis_tvalid_reg <= temp_axis_tvalid_reg;
output_axis_tlast_reg <= temp_axis_tlast_reg;
output_axis_tuser_reg <= temp_axis_tuser_reg;
temp_axis_tdata_reg <= 0;
temp_axis_tvalid_reg <= 0;
temp_axis_tlast_reg <= 0;
temp_axis_tuser_reg <= 0;
end
end
end
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_240x128.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.1 Build 201 11/27/2006 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_240x128 (
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrempty,
wrfull,
wrusedw);
input [239:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [239:0] q;
output rdempty;
output wrempty;
output wrfull;
output [6:0] wrusedw;
wire sub_wire0;
wire [6:0] sub_wire1;
wire sub_wire2;
wire sub_wire3;
wire [239:0] sub_wire4;
wire rdempty = sub_wire0;
wire [6:0] wrusedw = sub_wire1[6:0];
wire wrfull = sub_wire2;
wire wrempty = sub_wire3;
wire [239:0] q = sub_wire4[239:0];
dcfifo dcfifo_component (
.wrclk (wrclk),
.rdreq (rdreq),
.rdclk (rdclk),
.wrreq (wrreq),
.data (data),
.rdempty (sub_wire0),
.wrusedw (sub_wire1),
.wrfull (sub_wire2),
.wrempty (sub_wire3),
.q (sub_wire4)
// synopsys translate_off
,
.aclr (),
.rdfull (),
.rdusedw ()
// synopsys translate_on
);
defparam
dcfifo_component.intended_device_family = "Cyclone II",
dcfifo_component.lpm_hint = "MAXIMIZE_SPEED=5,",
dcfifo_component.lpm_numwords = 128,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 240,
dcfifo_component.lpm_widthu = 7,
dcfifo_component.overflow_checking = "OFF",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "OFF",
dcfifo_component.use_eab = "ON",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "128"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "240"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "240"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=5,"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "240"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: data 0 0 240 0 INPUT NODEFVAL data[239..0]
// Retrieval info: USED_PORT: q 0 0 240 0 OUTPUT NODEFVAL q[239..0]
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL wrempty
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: wrusedw 0 0 7 0 OUTPUT NODEFVAL wrusedw[6..0]
// Retrieval info: CONNECT: @data 0 0 240 0 data 0 0 240 0
// Retrieval info: CONNECT: q 0 0 240 0 @q 0 0 240 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 7 0 @wrusedw 0 0 7 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_240x128.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_240x128.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_240x128.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_240x128.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_240x128_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_240x128_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_240x128_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_240x128_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O2BB2A_2_V
`define SKY130_FD_SC_HD__O2BB2A_2_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog wrapper for o2bb2a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o2bb2a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o2bb2a_2 (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o2bb2a base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o2bb2a_2 (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o2bb2a base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O2BB2A_2_V
|
// $Id: vcr_vc_alloc_mac.v 1534 2009-09-16 16:10:23Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
Neither the name of the Stanford University nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// VC allocator
module vcr_vc_alloc_mac
(clk, reset, route_port_ip_ivc, inc_rc_ip_ivc, elig_op_ovc, req_ip_ivc,
gnt_ip_ivc, gnt_ip_ivc_ovc, gnt_op_ovc, gnt_op_ovc_ip, gnt_op_ovc_ivc);
`include "c_functions.v"
`include "c_constants.v"
`include "vcr_constants.v"
// number of message classes (e.g. request, reply)
parameter num_message_classes = 2;
// number of resource classes (e.g. minimal, adaptive)
parameter num_resource_classes = 2;
// total number of packet classes
localparam num_packet_classes = num_message_classes * num_resource_classes;
// number of VCs per class
parameter num_vcs_per_class = 1;
// number of VCs
localparam num_vcs = num_packet_classes * num_vcs_per_class;
// number of input and output ports on switch
parameter num_ports = 5;
// width required to select an individual port
localparam port_idx_width = clogb(num_ports);
// select implementation variant for VC allocator
parameter allocator_type = `VC_ALLOC_TYPE_SEP_IF;
// select which arbiter type to use in allocator
parameter arbiter_type = `ARBITER_TYPE_ROUND_ROBIN;
parameter reset_type = `RESET_TYPE_ASYNC;
input clk;
input reset;
// destination port selects
input [0:num_ports*num_vcs*port_idx_width-1] route_port_ip_ivc;
// transition to next resource class
input [0:num_ports*num_vcs-1] inc_rc_ip_ivc;
// output VC is eligible for allocation (i.e., not currently allocated)
input [0:num_ports*num_vcs-1] elig_op_ovc;
// request VC allocation
input [0:num_ports*num_vcs-1] req_ip_ivc;
// VC allocation successful (to input controller)
output [0:num_ports*num_vcs-1] gnt_ip_ivc;
wire [0:num_ports*num_vcs-1] gnt_ip_ivc;
// granted output VC (to input controller)
output [0:num_ports*num_vcs*num_vcs-1] gnt_ip_ivc_ovc;
wire [0:num_ports*num_vcs*num_vcs-1] gnt_ip_ivc_ovc;
// output VC was granted (to output controller)
output [0:num_ports*num_vcs-1] gnt_op_ovc;
wire [0:num_ports*num_vcs-1] gnt_op_ovc;
// input port that each output VC was granted to (to output controller)
output [0:num_ports*num_vcs*num_ports-1] gnt_op_ovc_ip;
wire [0:num_ports*num_vcs*num_ports-1] gnt_op_ovc_ip;
// input VC that each output VC was granted to (to output controller)
output [0:num_ports*num_vcs*num_vcs-1] gnt_op_ovc_ivc;
wire [0:num_ports*num_vcs*num_vcs-1] gnt_op_ovc_ivc;
generate
if(allocator_type == `VC_ALLOC_TYPE_SEP_IF)
begin
vcr_vc_alloc_sep_if
#(.num_message_classes(num_message_classes),
.num_resource_classes(num_resource_classes),
.num_vcs_per_class(num_vcs_per_class),
.num_ports(num_ports),
.arbiter_type(arbiter_type),
.reset_type(reset_type))
core_sep_if
(.clk(clk),
.reset(reset),
.route_port_ip_ivc(route_port_ip_ivc),
.inc_rc_ip_ivc(inc_rc_ip_ivc),
.elig_op_ovc(elig_op_ovc),
.req_ip_ivc(req_ip_ivc),
.gnt_ip_ivc(gnt_ip_ivc),
.gnt_ip_ivc_ovc(gnt_ip_ivc_ovc),
.gnt_op_ovc(gnt_op_ovc),
.gnt_op_ovc_ip(gnt_op_ovc_ip),
.gnt_op_ovc_ivc(gnt_op_ovc_ivc));
end
else if(allocator_type == `VC_ALLOC_TYPE_SEP_OF)
begin
vcr_vc_alloc_sep_of
#(.num_message_classes(num_message_classes),
.num_resource_classes(num_resource_classes),
.num_vcs_per_class(num_vcs_per_class),
.num_ports(num_ports),
.arbiter_type(arbiter_type),
.reset_type(reset_type))
core_sep_of
(.clk(clk),
.reset(reset),
.route_port_ip_ivc(route_port_ip_ivc),
.inc_rc_ip_ivc(inc_rc_ip_ivc),
.elig_op_ovc(elig_op_ovc),
.req_ip_ivc(req_ip_ivc),
.gnt_ip_ivc(gnt_ip_ivc),
.gnt_ip_ivc_ovc(gnt_ip_ivc_ovc),
.gnt_op_ovc(gnt_op_ovc),
.gnt_op_ovc_ip(gnt_op_ovc_ip),
.gnt_op_ovc_ivc(gnt_op_ovc_ivc));
end
else if((allocator_type >= `VC_ALLOC_TYPE_WF_BASE) &&
(allocator_type <= `VC_ALLOC_TYPE_WF_LIMIT))
begin
vcr_vc_alloc_wf
#(.num_message_classes(num_message_classes),
.num_resource_classes(num_resource_classes),
.num_vcs_per_class(num_vcs_per_class),
.num_ports(num_ports),
.wf_alloc_type(allocator_type - `VC_ALLOC_TYPE_WF_BASE),
.reset_type(reset_type))
core_wf
(.clk(clk),
.reset(reset),
.route_port_ip_ivc(route_port_ip_ivc),
.inc_rc_ip_ivc(inc_rc_ip_ivc),
.elig_op_ovc(elig_op_ovc),
.req_ip_ivc(req_ip_ivc),
.gnt_ip_ivc(gnt_ip_ivc),
.gnt_ip_ivc_ovc(gnt_ip_ivc_ovc),
.gnt_op_ovc(gnt_op_ovc),
.gnt_op_ovc_ip(gnt_op_ovc_ip),
.gnt_op_ovc_ivc(gnt_op_ovc_ivc));
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FA_PP_SYMBOL_V
`define SKY130_FD_SC_HS__FA_PP_SYMBOL_V
/**
* fa: Full adder.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__fa (
//# {{data|Data Signals}}
input A ,
input B ,
input CIN ,
output COUT,
output SUM ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__FA_PP_SYMBOL_V
|
module subtractor_csel(a, b, diff_out, carry_out);
input [31:0] a, b;
output [31:0] diff_out;
output carry_out;
wire [31:0] not_b, diff_out;
wire carry_out;
bitwise_not negate_b(b, not_b);
adder_csel subtraction(a, not_b, 1, diff_out, carry_out);
endmodule //end 32-bit subtraction
module adder_csel(a, b, carry_in, sum_out, carry_out);
input [31:0] a, b;
input carry_in;
output [31:0] sum_out;
output carry_out;
wire [31:0] temp_out_0, temp_out_1, sum_out;
wire [21:0] carries;
wire carry_out;
ripple_carry_adder rca_0(a[3:0], b[3:0], carry_in, sum_out[3:0], carries[0]);
genvar i, j;
generate
for (i=1; i<8; i=i+1) begin: carry_select_block_loop
ripple_carry_adder rca_1(a[((4*i)+3):(4*i)], b[((4*i)+3):(4*i)], 0, temp_out_0[((4*i)+3):(4*i)], carries[(3*i)-2]);
ripple_carry_adder rca_2(a[((4*i)+3):(4*i)], b[((4*i)+3):(4*i)], 1, temp_out_1[((4*i)+3):(4*i)], carries[(3*i)-1]);
for (j=(4*i); j<((4*i)+4); j=j+1) begin: sum_mux_loop
mux2_1 sum_mux(temp_out_0[j], temp_out_1[j], carries[(3*i)-3], sum_out[j]);
end
mux2_1 carry_mux(carries[(3*i)-2], carries[(3*i)-1], carries[(3*i)-3], carries[(3*i)]);
end
endgenerate
assign carry_out = carries[21];
endmodule //end 32-bit carry select adder
module ripple_carry_adder(a, b, c_in, s, c_out);
input [3:0] a, b;
input c_in;
output [3:0] s;
output c_out;
wire [4:0] carries;
wire [3:0] s;
wire c_out;
assign carries[0] = c_in;
genvar i;
generate
for (i=0; i<4; i=i+1) begin: rca_loop_1
full_adder rcadder(a[i], b[i], carries[i], s[i], carries[i+1]);
end
endgenerate
assign c_out = carries[4];
endmodule //end 4-bit ripple carry adder
module full_adder(a, b, c_in, s, c_out);
input a, b, c_in;
output s, c_out;
wire [2:0] inter_out;
wire s, c_out;
xor(inter_out[0], a, b);
and(inter_out[1], a, b);
and(inter_out[2], inter_out[0], c_in);
xor(s, inter_out[0], c_in);
or(c_out, inter_out[1], inter_out[2]);
endmodule //end 1-bit full adder
module mux2_1(a, b, select, out);
input a, b, select;
output out;
wire not_select, out;
wire [1:0] inter_out;
not(not_select, select);
and(inter_out[0], not_select, a);
and(inter_out[1], select, b);
or(out, inter_out[0], inter_out[1]);
endmodule //end 2:1 mux
//end adder + supporting modules
module arithmetic_right_shift(a, shift, lsb, out);
input [31:0] a;
input [4:0] shift;
input lsb;
output [31:0] out;
wire [31:0] out, pre_shift, post_shift;
bit_reversal reverse_0(a, pre_shift);
logical_left_shift shifter(pre_shift, shift, lsb, post_shift);
bit_reversal reverse_1(post_shift, out);
endmodule //end 32-bit arithmetic right shift
module bit_reversal(a, out);
input [31:0] a;
output [31:0] out;
wire [31:0] out, temp;
assign temp = a;
genvar i;
generate
for(i=0; i<32; i=i+1) begin: reversal_loop
assign out[i] = temp[31-i];
end
endgenerate
endmodule //end 32-bit input bit reverser
module logical_left_shift(a, shift, lsb, out);
input [31:0] a;
input [4:0] shift;
input lsb;
output [31:0] out;
wire [31:0] out;
wire [31:0] mux_wire [4:0];
wire [31:0] shift_wire [4:0];
sll_16 s16(a, lsb, shift_wire[4]);
tsb_mux m16(a, shift_wire[4], shift[4], mux_wire[4]);
sll_8 s8(mux_wire[4], lsb, shift_wire[3]);
tsb_mux m8(mux_wire[4], shift_wire[3], shift[3], mux_wire[3]);
sll_4 s4(mux_wire[3], lsb, shift_wire[2]);
tsb_mux m4(mux_wire[3], shift_wire[2], shift[2], mux_wire[2]);
sll_2 s2(mux_wire[2], lsb, shift_wire[1]);
tsb_mux m2(mux_wire[2], shift_wire[1], shift[1], mux_wire[1]);
sll_1 s1(mux_wire[1], lsb, shift_wire[0]);
tsb_mux m1(mux_wire[1], shift_wire[0], shift[0], mux_wire[0]);
assign out = mux_wire[0];
endmodule //end 32-bit logical left barrel shifter
module sll_16(a, lsb, out);
input [31:0] a;
input lsb;
output[31:0] out;
wire [31:0] out;
genvar i;
generate
for(i=16; i<32; i=i+1) begin: shift_sixteen_loop
assign out[i] = a[i-16];
end
endgenerate
genvar j;
generate
for(j=0; j<16; j=j+1) begin: shift_sixteen_sub_loop
assign out[j] = lsb;
end
endgenerate
endmodule //end 16-bit logical left shift
module sll_8(a, lsb, out);
input [31:0] a;
input lsb;
output[31:0] out;
wire [31:0] out;
genvar i;
generate
for(i=8; i<32; i=i+1) begin: shift_eight_loop
assign out[i] = a[i-8];
end
endgenerate
genvar j;
generate
for(j=0; j<8; j=j+1) begin: shift_eight_sub_loop
assign out[j] = lsb;
end
endgenerate
endmodule //end 8-bit logical left shift
module sll_4(a, lsb, out);
input [31:0] a;
input lsb;
output[31:0] out;
wire [31:0] out;
genvar i;
generate
for(i=4; i<32; i=i+1) begin: shift_four_loop
assign out[i] = a[i-4];
end
endgenerate
assign out[0] = lsb;
assign out[1] = lsb;
assign out[2] = lsb;
assign out[3] = lsb;
endmodule //end 4-bit logical left shift
module sll_2(a, lsb, out);
input [31:0] a;
input lsb;
output[31:0] out;
wire [31:0] out;
genvar i;
generate
for(i=2; i<32; i=i+1) begin: shift_two_loop
assign out[i] = a[i-2];
end
endgenerate
assign out[0] = lsb;
assign out[1] = lsb;
endmodule //end 2-bit logical left shift
module sll_1(a, lsb, out);
input [31:0] a;
input lsb;
output [31:0] out;
wire [31:0] out;
genvar i;
generate
for(i=1; i<32; i=i+1) begin: shift_one_loop
assign out[i] = a[i-1];
end
endgenerate
assign out[0] = lsb;
endmodule //end 1-bit logical left shift
module tsb_mux(a, b, select, out);
input [31:0] a, b;
input select;
output [31:0] out;
wire not_select;
not(not_select, select);
tsb buffer_a(a, not_select, out);
tsb buffer_b(b, select, out);
endmodule //end mux based on tri-state buffers
module tsb(in, enable, out);
input [31:0] in;
input enable;
output [31:0] out;
wire [31:0] in, out;
wire enable;
assign out = (enable) ? in : 32'bz;
endmodule //end 32-bit tri-state buffer
//end barrel shifter + supporting modules
module bitwise_and(a, b, out);
input [31:0] a, b;
output [31:0] out;
wire [31:0] out;
genvar i;
generate
for(i=0; i<32; i=i+1) begin: and_loop
and(out[i], a[i], b[i]);
end
endgenerate
endmodule //end 32-bit bitwise AND
module bitwise_or(a, b, out);
input [31:0] a, b;
output [31:0] out;
wire [31:0] out;
genvar i;
generate
for(i=0; i<32; i=i+1) begin: or_loop
or(out[i], a[i], b[i]);
end
endgenerate
endmodule //end 32-bit bitwise OR
module bitwise_not(in, out);
input [31:0] in;
output [31:0] out;
wire [31:0] out;
genvar i;
generate
for(i=0; i<32; i=i+1) begin: not_loop
assign out[i] = ~in[i];
end
endgenerate
endmodule //end 32-bit bitwise NOT
//end bitwise operators
module equal_or_less(in, equal, less);
input [31:0] in;
output equal, less;
wire equal, less;
or(equal, in[31], in[30], in[29], in[28], in[27], in[26], in[25], in[24],
in[23], in[22], in[21], in[20], in[19], in[18], in[17], in[16],
in[15], in[14], in[13], in[12], in[11], in[10], in[9] , in[8] ,
in[7] , in[6] , in[5] , in[4] , in[3] , in[2] , in[1] , in[0]);
assign less = in[31];
endmodule //end shorthand comparator module
module tsb_1bit(in, enable, out);
input in, enable;
output out;
wire in, enable, out;
assign out = (enable) ? in : 1'bz;
endmodule //end 1-bit tri-state buffer
//end comparison modules
module opcode_decoder(code_in, code_out);
input [4:0] code_in;
output [5:0] code_out;
wire [5:0] code_out;
and(code_out[0], ~code_in[0], ~code_in[1], ~code_in[2], ~code_in[3], ~code_in[4]); //add
and(code_out[1], code_in[0], ~code_in[1], ~code_in[2], ~code_in[3], ~code_in[4]); //subtract
and(code_out[2], ~code_in[0], code_in[1], ~code_in[2], ~code_in[3], ~code_in[4]); //and
and(code_out[3], code_in[0], code_in[1], ~code_in[2], ~code_in[3], ~code_in[4]); //or
and(code_out[4], ~code_in[0], ~code_in[1], code_in[2], ~code_in[3], ~code_in[4]); //sll
and(code_out[5], code_in[0], ~code_in[1], code_in[2], ~code_in[3], ~code_in[4]); //sra
endmodule //end alu-opcode decoder
module alu(data_operandA, data_operandB, ctrl_ALUopcode, ctrl_shiftamt, data_result, isNotEqual, isLessThan);
input [31:0] data_operandA, data_operandB;
input [4:0] ctrl_ALUopcode, ctrl_shiftamt;
output [31:0] data_result;
output isNotEqual, isLessThan;
wire [5:0] decoded_op;
wire csum_out, cdif_out;
wire [31:0] results [5:0];
wire equal, less;
opcode_decoder alu_decoder(ctrl_ALUopcode, decoded_op);
adder_csel alu_adder(data_operandA, data_operandB, 0, results[0], csum_out);
subtractor_csel alu_subtract(data_operandA, data_operandB, results[1], cdif_out);
bitwise_and alu_and(data_operandA, data_operandB, results[2]);
bitwise_or alu_or(data_operandA, data_operandB, results[3]);
logical_left_shift left_shift_l(data_operandA, ctrl_shiftamt, 0, results[4]);
arithmetic_right_shift right_shift_a(data_operandA, ctrl_shiftamt, data_operandA[31], results[5]);
equal_or_less quick_compare(results[1], equal, less);
tsb buffer_add(results[0], decoded_op[0], data_result);
tsb buffer_sub(results[1], decoded_op[1], data_result);
tsb buffer_and(results[2], decoded_op[2], data_result);
tsb buffer_or (results[3], decoded_op[3], data_result);
tsb buffer_sll(results[4], decoded_op[4], data_result);
tsb buffer_sra(results[5], decoded_op[5], data_result);
tsb_1bit buffer_equal(equal, decoded_op[1], isNotEqual);
tsb_1bit buffer_less (less , decoded_op[1], isLessThan);
endmodule |
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_SRAM (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "soc_design_SRAM.hex";
output [ 31: 0] readdata;
input [ 14: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [ 31: 0] writedata;
wire clocken0;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 20480,
the_altsyncram.numwords_a = 20480,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 15;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
// Copyright (C) 2020-2021 The SymbiFlow Authors.
//
// Use of this source code is governed by a ISC-style
// license that can be found in the LICENSE file or at
// https://opensource.org/licenses/ISC
//
// SPDX-License-Identifier:ISC
module top (
input clk,
output [3:0] led,
inout out_a,
output [1:0] out_b
);
wire LD6, LD7, LD8, LD9;
wire inter_wire, inter_wire_2;
localparam BITS = 1;
localparam LOG2DELAY = 25;
reg [BITS+LOG2DELAY-1:0] counter = 0;
always @(posedge clk) begin
counter <= counter + 1;
end
assign led[1] = inter_wire;
assign inter_wire = inter_wire_2;
assign {LD9, LD8, LD7, LD6} = counter >> LOG2DELAY;
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_6 (
.I(LD6),
.O(led[0])
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_7 (
.I(LD7),
.O(inter_wire_2)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_OUT (
.I(LD7),
.O(out_a)
);
bottom bottom_inst (
.I (LD8),
.O (led[2]),
.OB(out_b)
);
bottom_intermediate bottom_intermediate_inst (
.I(LD9),
.O(led[3])
);
endmodule
module bottom_intermediate (
input I,
output O
);
wire bottom_intermediate_wire;
assign O = bottom_intermediate_wire;
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_8 (
.I(I),
.O(bottom_intermediate_wire)
);
endmodule
module bottom (
input I,
output [1:0] OB,
output O
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_9 (
.I(I),
.O(O)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_10 (
.I(I),
.O(OB[0])
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_11 (
.I(I),
.O(OB[1])
);
endmodule
|
/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for wb_async_reg
*/
module test_wb_async_reg;
// Parameters
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 32;
parameter SELECT_WIDTH = 4;
// Inputs
reg wbm_clk = 0;
reg wbm_rst = 0;
reg wbs_clk = 0;
reg wbs_rst = 0;
reg [7:0] current_test = 0;
reg [ADDR_WIDTH-1:0] wbm_adr_i = 0;
reg [DATA_WIDTH-1:0] wbm_dat_i = 0;
reg wbm_we_i = 0;
reg [SELECT_WIDTH-1:0] wbm_sel_i = 0;
reg wbm_stb_i = 0;
reg wbm_cyc_i = 0;
reg [DATA_WIDTH-1:0] wbs_dat_i = 0;
reg wbs_ack_i = 0;
reg wbs_err_i = 0;
reg wbs_rty_i = 0;
// Outputs
wire [DATA_WIDTH-1:0] wbm_dat_o;
wire wbm_ack_o;
wire wbm_err_o;
wire wbm_rty_o;
wire [ADDR_WIDTH-1:0] wbs_adr_o;
wire [DATA_WIDTH-1:0] wbs_dat_o;
wire wbs_we_o;
wire [SELECT_WIDTH-1:0] wbs_sel_o;
wire wbs_stb_o;
wire wbs_cyc_o;
initial begin
// myhdl integration
$from_myhdl(wbm_clk,
wbm_rst,
wbs_clk,
wbs_rst,
current_test,
wbm_adr_i,
wbm_dat_i,
wbm_we_i,
wbm_sel_i,
wbm_stb_i,
wbm_cyc_i,
wbs_dat_i,
wbs_ack_i,
wbs_err_i,
wbs_rty_i);
$to_myhdl(wbm_dat_o,
wbm_ack_o,
wbm_err_o,
wbm_rty_o,
wbs_adr_o,
wbs_dat_o,
wbs_we_o,
wbs_sel_o,
wbs_stb_o,
wbs_cyc_o);
// dump file
$dumpfile("test_wb_async_reg.lxt");
$dumpvars(0, test_wb_async_reg);
end
wb_async_reg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.SELECT_WIDTH(SELECT_WIDTH)
)
UUT (
.wbm_clk(wbm_clk),
.wbm_rst(wbm_rst),
.wbm_adr_i(wbm_adr_i),
.wbm_dat_i(wbm_dat_i),
.wbm_dat_o(wbm_dat_o),
.wbm_we_i(wbm_we_i),
.wbm_sel_i(wbm_sel_i),
.wbm_stb_i(wbm_stb_i),
.wbm_ack_o(wbm_ack_o),
.wbm_err_o(wbm_err_o),
.wbm_rty_o(wbm_rty_o),
.wbm_cyc_i(wbm_cyc_i),
.wbs_clk(wbs_clk),
.wbs_rst(wbs_rst),
.wbs_adr_o(wbs_adr_o),
.wbs_dat_i(wbs_dat_i),
.wbs_dat_o(wbs_dat_o),
.wbs_we_o(wbs_we_o),
.wbs_sel_o(wbs_sel_o),
.wbs_stb_o(wbs_stb_o),
.wbs_ack_i(wbs_ack_i),
.wbs_err_i(wbs_err_i),
.wbs_rty_i(wbs_rty_i),
.wbs_cyc_o(wbs_cyc_o)
);
endmodule
|
/*
* This source file contains a Verilog description of an IP core
* automatically generated by the SPIRAL HDL Generator.
*
* This product includes a hardware design developed by Carnegie Mellon University.
*
* Copyright (c) 2005-2011 by Peter A. Milder for the SPIRAL Project,
* Carnegie Mellon University
*
* For more information, see the SPIRAL project website at:
* http://www.spiral.net
*
* This design is provided for internal, non-commercial research use only
* and is not for redistribution, with or without modifications.
*
* You may not use the name "Carnegie Mellon University" or derivations
* thereof to endorse or promote products derived from this software.
*
* THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY
* THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY
* BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT,
* SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN
* ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY,
* CONTRACT, TORT OR OTHERWISE).
*
DFT Size = 64
direction = forward
data type = 16 bit fixed point, unscaled
architecture = fully streaming
radix = 2
streaming width = 2
data ordering = natural input / natural output
BRAM budget = 1000
*/
// Input/output stream: 2 complex words per cycle
// Throughput: one transform every 32 cycles
// Latency: 332 cycles
// Resources required:
// 20 multipliers (16 x 16 bit)
// 34 adders (16 x 16 bit)
// 4 RAMs (16 words, 32 bits per word)
// 4 RAMs (8 words, 32 bits per word)
// 12 RAMs (64 words, 32 bits per word)
// 4 RAMs (32 words, 32 bits per word)
// 2 ROMs (32 words, 16 bits per word)
// 2 ROMs (8 words, 16 bits per word)
// 12 ROMs (32 words, 5 bits per word)
// 2 ROMs (16 words, 16 bits per word)
// Generated on Fri Jul 25 15:42:10 EDT 2014
// Latency: 332 clock cycles
// Throughput: 1 transform every 32 cycles
// We use an interleaved complex data format. X0 represents the
// real portion of the first input, and X1 represents the imaginary
// portion. The X variables are system inputs and the Y variables
// are system outputs.
// The design uses a system of flag signals to indicate the
// beginning of the input and output data streams. The 'next'
// input (asserted high), is used to instruct the system that the
// input stream will begin on the following cycle.
// This system has a 'gap' of 32 cycles. This means that
// 32 cycles must elapse between the beginning of the input
// vectors.
// The output signal 'next_out' (also asserted high) indicates
// that the output vector will begin streaming out of the system
// on the following cycle.
// The system has a latency of 332 cycles. This means that
// the 'next_out' will be asserted 332 cycles after the user
// asserts 'next'.
// The simple testbench below will demonstrate the timing for loading
// and unloading data vectors.
// The system reset signal is asserted high.
// Please note: when simulating floating point code, you must include
// Xilinx's DSP slice simulation module.
// module dft_testbench();
// reg clk, reset, next;
// wire next_out;
// integer i, j, k, l, m;
// reg [15:0] counter;
// reg [15:0] in [3:0];
// wire [15:0] X0;
// wire [15:0] Y0;
// wire [15:0] X1;
// wire [15:0] Y1;
// wire [15:0] X2;
// wire [15:0] Y2;
// wire [15:0] X3;
// wire [15:0] Y3;
// reg clrCnt;
// assign X0 = in[0];
// assign X1 = in[1];
// assign X2 = in[2];
// assign X3 = in[3];
// initial clk = 0;
// always #10000 clk = ~clk;
// // Instantiate top-level module of core 'X' signals are system inputs
// // and 'Y' signals are system outputs
// dft_top dft_top_instance (.clk(clk), .reset(reset), .next(next), .next_out(next_out),
// .X0(X0), .Y0(Y0),
// .X1(X1), .Y1(Y1),
// .X2(X2), .Y2(Y2),
// .X3(X3), .Y3(Y3));
// // You can use this counter to verify that the gap and latency are as expected.
// always @(posedge clk) begin
// if (clrCnt) counter <= 0;
// else counter <= counter+1;
// end
// initial begin
// @(posedge clk);
// @(posedge clk);
// // On the next cycle, begin loading input vector.
// next <= 1;
// clrCnt <= 1;
// @(posedge clk);
// clrCnt <= 0;
// next <= 0;
// // The 64 complex data points enter the system over 32 cycles
// for (j=0; j < 31; j = j+1) begin
// // Input: 2 complex words per cycle
// for (k=0; k < 4; k = k+1) begin
// in[k] <= j*4 + k;
// end
// @(posedge clk);
// end
// j = 31;
// for (k=0; k < 4; k = k+1) begin
// in[k] <= j*4 + k;
// end
// @(posedge clk);
// // Wait until the next data vector can be entered
// while (counter < 30)
// @(posedge clk);
// // On the next cycle, we will start the next data vector
// next <= 1;
// clrCnt <= 1;
// @(posedge clk);
// clrCnt <= 0;
// next <= 0;
// // Start entering next input vector
// for (j=0; j < 31; j = j+1) begin
// // Input 4 words per cycle
// for (k=0; k < 4; k = k+1) begin
// in[k] <= 128 + j*4 + k;
// end
// @(posedge clk);
// end
// j = 31;
// for (k=0; k < 4; k = k+1) begin
// in[k] <= 128 + j*4 + k;
// end
// end
// initial begin
// // set initial values
// in[0] <= 0;
// in[1] <= 0;
// in[2] <= 0;
// in[3] <= 0;
// next <= 0;
// reset <= 0;
// @(posedge clk);
// reset <= 1;
// @(posedge clk);
// reset <= 0;
// @(posedge clk);
// @(posedge clk);
// // Wait until next_out goes high, then wait one clock cycle and begin receiving data
// @(posedge next_out);
// @(posedge clk); #1;
// $display("--- begin output 1---");
// for (m=0; m < 31; m=m+1) begin
// $display("%x", Y0);
// $display("%x", Y1);
// $display("%x", Y2);
// $display("%x", Y3);
// @(posedge clk); #1;
// end
// $display("%x", Y0);
// $display("%x", Y1);
// $display("%x", Y2);
// $display("%x", Y3);
// // Wait until next_out goes high, then wait one clock cycle and begin receiving data
// @(posedge next_out);
// @(posedge clk); #1;
// $display("--- begin output 2---");
// for (m=0; m < 31; m=m+1) begin
// $display("%x", Y0);
// $display("%x", Y1);
// $display("%x", Y2);
// $display("%x", Y3);
// @(posedge clk); #1;
// end
// $display("%x", Y0);
// $display("%x", Y1);
// $display("%x", Y2);
// $display("%x", Y3);
// $finish;
// end
// endmodule
// Latency: 332
// Gap: 32
// module_name_is:dft_top
module dft_top(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
wire [15:0] t0_0;
wire [15:0] t0_1;
wire [15:0] t0_2;
wire [15:0] t0_3;
wire next_0;
wire [15:0] t1_0;
wire [15:0] t1_1;
wire [15:0] t1_2;
wire [15:0] t1_3;
wire next_1;
wire [15:0] t2_0;
wire [15:0] t2_1;
wire [15:0] t2_2;
wire [15:0] t2_3;
wire next_2;
wire [15:0] t3_0;
wire [15:0] t3_1;
wire [15:0] t3_2;
wire [15:0] t3_3;
wire next_3;
wire [15:0] t4_0;
wire [15:0] t4_1;
wire [15:0] t4_2;
wire [15:0] t4_3;
wire next_4;
wire [15:0] t5_0;
wire [15:0] t5_1;
wire [15:0] t5_2;
wire [15:0] t5_3;
wire next_5;
wire [15:0] t6_0;
wire [15:0] t6_1;
wire [15:0] t6_2;
wire [15:0] t6_3;
wire next_6;
wire [15:0] t7_0;
wire [15:0] t7_1;
wire [15:0] t7_2;
wire [15:0] t7_3;
wire next_7;
wire [15:0] t8_0;
wire [15:0] t8_1;
wire [15:0] t8_2;
wire [15:0] t8_3;
wire next_8;
wire [15:0] t9_0;
wire [15:0] t9_1;
wire [15:0] t9_2;
wire [15:0] t9_3;
wire next_9;
wire [15:0] t10_0;
wire [15:0] t10_1;
wire [15:0] t10_2;
wire [15:0] t10_3;
wire next_10;
wire [15:0] t11_0;
wire [15:0] t11_1;
wire [15:0] t11_2;
wire [15:0] t11_3;
wire next_11;
wire [15:0] t12_0;
wire [15:0] t12_1;
wire [15:0] t12_2;
wire [15:0] t12_3;
wire next_12;
wire [15:0] t13_0;
wire [15:0] t13_1;
wire [15:0] t13_2;
wire [15:0] t13_3;
wire next_13;
wire [15:0] t14_0;
wire [15:0] t14_1;
wire [15:0] t14_2;
wire [15:0] t14_3;
wire next_14;
wire [15:0] t15_0;
wire [15:0] t15_1;
wire [15:0] t15_2;
wire [15:0] t15_3;
wire next_15;
wire [15:0] t16_0;
wire [15:0] t16_1;
wire [15:0] t16_2;
wire [15:0] t16_3;
wire next_16;
wire [15:0] t17_0;
wire [15:0] t17_1;
wire [15:0] t17_2;
wire [15:0] t17_3;
wire next_17;
wire [15:0] t18_0;
wire [15:0] t18_1;
wire [15:0] t18_2;
wire [15:0] t18_3;
wire next_18;
assign t0_0 = X0;
assign Y0 = t18_0;
assign t0_1 = X1;
assign Y1 = t18_1;
assign t0_2 = X2;
assign Y2 = t18_2;
assign t0_3 = X3;
assign Y3 = t18_3;
assign next_0 = next;
assign next_out = next_18;
// latency=68, gap=32
rc30655 stage0(.clk(clk), .reset(reset), .next(next_0), .next_out(next_1),
.X0(t0_0), .Y0(t1_0),
.X1(t0_1), .Y1(t1_1),
.X2(t0_2), .Y2(t1_2),
.X3(t0_3), .Y3(t1_3));
// latency=2, gap=32
codeBlock30657 stage1(.clk(clk), .reset(reset), .next_in(next_1), .next_out(next_2),
.X0_in(t1_0), .Y0(t2_0),
.X1_in(t1_1), .Y1(t2_1),
.X2_in(t1_2), .Y2(t2_2),
.X3_in(t1_3), .Y3(t2_3));
// latency=8, gap=32
rc30737 stage2(.clk(clk), .reset(reset), .next(next_2), .next_out(next_3),
.X0(t2_0), .Y0(t3_0),
.X1(t2_1), .Y1(t3_1),
.X2(t2_2), .Y2(t3_2),
.X3(t2_3), .Y3(t3_3));
// latency=8, gap=32
DirSum_30916 stage3(.next(next_3), .clk(clk), .reset(reset), .next_out(next_4),
.X0(t3_0), .Y0(t4_0),
.X1(t3_1), .Y1(t4_1),
.X2(t3_2), .Y2(t4_2),
.X3(t3_3), .Y3(t4_3));
// latency=2, gap=32
codeBlock30919 stage4(.clk(clk), .reset(reset), .next_in(next_4), .next_out(next_5),
.X0_in(t4_0), .Y0(t5_0),
.X1_in(t4_1), .Y1(t5_1),
.X2_in(t4_2), .Y2(t5_2),
.X3_in(t4_3), .Y3(t5_3));
// latency=12, gap=32
rc30999 stage5(.clk(clk), .reset(reset), .next(next_5), .next_out(next_6),
.X0(t5_0), .Y0(t6_0),
.X1(t5_1), .Y1(t6_1),
.X2(t5_2), .Y2(t6_2),
.X3(t5_3), .Y3(t6_3));
// latency=8, gap=32
DirSum_31186 stage6(.next(next_6), .clk(clk), .reset(reset), .next_out(next_7),
.X0(t6_0), .Y0(t7_0),
.X1(t6_1), .Y1(t7_1),
.X2(t6_2), .Y2(t7_2),
.X3(t6_3), .Y3(t7_3));
// latency=2, gap=32
codeBlock31189 stage7(.clk(clk), .reset(reset), .next_in(next_7), .next_out(next_8),
.X0_in(t7_0), .Y0(t8_0),
.X1_in(t7_1), .Y1(t8_1),
.X2_in(t7_2), .Y2(t8_2),
.X3_in(t7_3), .Y3(t8_3));
// latency=20, gap=32
rc31269 stage8(.clk(clk), .reset(reset), .next(next_8), .next_out(next_9),
.X0(t8_0), .Y0(t9_0),
.X1(t8_1), .Y1(t9_1),
.X2(t8_2), .Y2(t9_2),
.X3(t8_3), .Y3(t9_3));
// latency=8, gap=32
DirSum_31472 stage9(.next(next_9), .clk(clk), .reset(reset), .next_out(next_10),
.X0(t9_0), .Y0(t10_0),
.X1(t9_1), .Y1(t10_1),
.X2(t9_2), .Y2(t10_2),
.X3(t9_3), .Y3(t10_3));
// latency=2, gap=32
codeBlock31475 stage10(.clk(clk), .reset(reset), .next_in(next_10), .next_out(next_11),
.X0_in(t10_0), .Y0(t11_0),
.X1_in(t10_1), .Y1(t11_1),
.X2_in(t10_2), .Y2(t11_2),
.X3_in(t10_3), .Y3(t11_3));
// latency=36, gap=32
rc31555 stage11(.clk(clk), .reset(reset), .next(next_11), .next_out(next_12),
.X0(t11_0), .Y0(t12_0),
.X1(t11_1), .Y1(t12_1),
.X2(t11_2), .Y2(t12_2),
.X3(t11_3), .Y3(t12_3));
// latency=8, gap=32
DirSum_31790 stage12(.next(next_12), .clk(clk), .reset(reset), .next_out(next_13),
.X0(t12_0), .Y0(t13_0),
.X1(t12_1), .Y1(t13_1),
.X2(t12_2), .Y2(t13_2),
.X3(t12_3), .Y3(t13_3));
// latency=2, gap=32
codeBlock31793 stage13(.clk(clk), .reset(reset), .next_in(next_13), .next_out(next_14),
.X0_in(t13_0), .Y0(t14_0),
.X1_in(t13_1), .Y1(t14_1),
.X2_in(t13_2), .Y2(t14_2),
.X3_in(t13_3), .Y3(t14_3));
// latency=68, gap=32
rc31873 stage14(.clk(clk), .reset(reset), .next(next_14), .next_out(next_15),
.X0(t14_0), .Y0(t15_0),
.X1(t14_1), .Y1(t15_1),
.X2(t14_2), .Y2(t15_2),
.X3(t14_3), .Y3(t15_3));
// latency=8, gap=32
DirSum_32171 stage15(.next(next_15), .clk(clk), .reset(reset), .next_out(next_16),
.X0(t15_0), .Y0(t16_0),
.X1(t15_1), .Y1(t16_1),
.X2(t15_2), .Y2(t16_2),
.X3(t15_3), .Y3(t16_3));
// latency=2, gap=32
codeBlock32174 stage16(.clk(clk), .reset(reset), .next_in(next_16), .next_out(next_17),
.X0_in(t16_0), .Y0(t17_0),
.X1_in(t16_1), .Y1(t17_1),
.X2_in(t16_2), .Y2(t17_2),
.X3_in(t16_3), .Y3(t17_3));
// latency=68, gap=32
rc32254 stage17(.clk(clk), .reset(reset), .next(next_17), .next_out(next_18),
.X0(t17_0), .Y0(t18_0),
.X1(t17_1), .Y1(t18_1),
.X2(t17_2), .Y2(t18_2),
.X3(t17_3), .Y3(t18_3));
endmodule
// Latency: 68
// Gap: 32
module rc30655(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
wire [31:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[31:16];
assign Y1 = s0[15:0];
assign Y2 = s1[31:16];
assign Y3 = s1[15:0];
perm30653 instPerm33199(.x0(t0), .y0(s0),
.x1(t1), .y1(s1),
.clk(clk), .next(next), .next_out(next_out), .reset(reset)
);
endmodule
module swNet30653(itr, clk, ct
, x0, y0
, x1, y1
);
parameter width = 32;
input [4:0] ct;
input clk;
input [0:0] itr;
input [width-1:0] x0;
output [width-1:0] y0;
reg [width-1:0] y0;
input [width-1:0] x1;
output [width-1:0] y1;
reg [width-1:0] y1;
wire [width-1:0] t0_0, t0_1;
reg [width-1:0] t1_0, t1_1;
reg [0:0] control;
always @(posedge clk) begin
case(ct)
5'd0: control <= 1'b1;
5'd1: control <= 1'b1;
5'd2: control <= 1'b1;
5'd3: control <= 1'b1;
5'd4: control <= 1'b1;
5'd5: control <= 1'b1;
5'd6: control <= 1'b1;
5'd7: control <= 1'b1;
5'd8: control <= 1'b1;
5'd9: control <= 1'b1;
5'd10: control <= 1'b1;
5'd11: control <= 1'b1;
5'd12: control <= 1'b1;
5'd13: control <= 1'b1;
5'd14: control <= 1'b1;
5'd15: control <= 1'b1;
5'd16: control <= 1'b0;
5'd17: control <= 1'b0;
5'd18: control <= 1'b0;
5'd19: control <= 1'b0;
5'd20: control <= 1'b0;
5'd21: control <= 1'b0;
5'd22: control <= 1'b0;
5'd23: control <= 1'b0;
5'd24: control <= 1'b0;
5'd25: control <= 1'b0;
5'd26: control <= 1'b0;
5'd27: control <= 1'b0;
5'd28: control <= 1'b0;
5'd29: control <= 1'b0;
5'd30: control <= 1'b0;
5'd31: control <= 1'b0;
endcase
end
// synthesis attribute rom_style of control is "distributed"
reg [0:0] control0;
always @(posedge clk) begin
control0 <= control;
end
assign t0_0 = x0;
assign t0_1 = x1;
always @(posedge clk) begin
t1_0 <= (control0[0] == 0) ? t0_0 : t0_1;
t1_1 <= (control0[0] == 0) ? t0_1 : t0_0;
end
always @(posedge clk) begin
y0 <= t1_0;
y1 <= t1_1;
end
endmodule
// Latency: 68
// Gap: 32
module perm30653(clk, next, reset, next_out,
x0, y0,
x1, y1);
parameter width = 32;
parameter depth = 32;
parameter depthX2 = 64;
parameter addrbits = 5;
parameter addrbitsplusone = 6;
parameter muxbits = 1;
input [width-1:0] x0;
output [width-1:0] y0;
wire [width-1:0] t0;
wire [width-1:0] s0;
input [width-1:0] x1;
output [width-1:0] y1;
wire [width-1:0] t1;
wire [width-1:0] s1;
input next, reset, clk;
output next_out;
reg [addrbits-1:0] s1rdloc, s2rdloc;
reg [addrbits-1:0] s1wr0;
reg [addrbits-1:0] s1rd0, s2wr0, s2rd0;
reg [addrbits-1:0] s1rd1, s2wr1, s2rd1;
reg s1wr_en, state1, state2, state3;
wire next2, next3, next4;
reg inFlip0, outFlip0_z, outFlip1;
wire inFlip1, outFlip0;
wire [0:0] tm0;
assign tm0 = 0;
shiftRegFIFO shiftFIFO_33204(.X(outFlip0), .Y(inFlip1), .clk(clk));
defparam shiftFIFO_33204.depth = 3;
defparam shiftFIFO_33204.width = 1;
shiftRegFIFO shiftFIFO_33205(.X(outFlip0_z), .Y(outFlip0), .clk(clk));
defparam shiftFIFO_33205.depth = 1;
defparam shiftFIFO_33205.width = 1;
// shiftRegFIFO inFlip1Reg(outFlip0, inFlip1,
// defparam shiftRegFIFO.depth = 2;
// wi shiftRegFIFO.dth = 1;
// shiftRegFIFO outFlip0Reg(outFlip0_z, outFlip0,
// defparam shiftRegFIFO.depth = 1;
// wi shiftRegFIFO.dth = 1;
memMod_dist s1mem0(x0, t0, {inFlip0, s1wr0}, {outFlip0, s1rd0}, s1wr_en, clk);
defparam s1mem0.depth = 46;
defparam s1mem0.width = 32;
defparam s1mem0.logDepth = 6;
memMod_dist s1mem1(x1, t1, {inFlip0, s1wr0}, {outFlip0, s1rd1}, s1wr_en, clk);
defparam s1mem1.depth = 46;
defparam s1mem1.width = 32;
defparam s1mem1.logDepth = 6;
nextReg nextReg_33216(.X(next), .Y(next2), .reset(reset), .clk(clk));
defparam nextReg_33216.depth = 31;
defparam nextReg_33216.logDepth = 5;
shiftRegFIFO shiftFIFO_33217(.X(next2), .Y(next3), .clk(clk));
defparam shiftFIFO_33217.depth = 4;
defparam shiftFIFO_33217.width = 1;
nextReg nextReg_33220(.X(next3), .Y(next4), .reset(reset), .clk(clk));
defparam nextReg_33220.depth = 32;
defparam nextReg_33220.logDepth = 5;
shiftRegFIFO shiftFIFO_33221(.X(next4), .Y(next_out), .clk(clk));
defparam shiftFIFO_33221.depth = 1;
defparam shiftFIFO_33221.width = 1;
shiftRegFIFO shiftFIFO_33224(.X(tm0), .Y(tm0_d), .clk(clk));
defparam shiftFIFO_33224.depth = 31;
defparam shiftFIFO_33224.width = 1;
shiftRegFIFO shiftFIFO_33227(.X(tm0_d), .Y(tm0_dd), .clk(clk));
defparam shiftFIFO_33227.depth = 3;
defparam shiftFIFO_33227.width = 1;
// // shiftRegFIFO1) n1(next, next2,
// defparam shiftRegFIFO1.depth = dept;
// wi shiftRegFIFO1.dth = 1;,
// // shiftRegFIFO n2(next2, next3,
// defparam shiftRegFIFO.depth = 3;
// wi shiftRegFIFO.dth = 1;
// // shiftRegFIFO n3(next3, next4,
// defparam shiftRegFIFO.depth = depth;
// wi shiftRegFIFO.dth = 1;
// // shiftRegFIFO n4(next4, next_out,
// defparam shiftRegFIFO.depth = 1;
// wi shiftRegFIFO.dth = 1;
wire [addrbits-1:0] muxCycle, writeCycle;
assign muxCycle = s1rdloc;
shiftRegFIFO shiftFIFO_33232(.X(muxCycle), .Y(writeCycle), .clk(clk));
defparam shiftFIFO_33232.depth = 3;
defparam shiftFIFO_33232.width = 5;
wire readInt, s2wr_en;
assign readInt = (state2 == 1);
shiftRegFIFO writeIntReg(readInt, s2wr_en, clk);
defparam writeIntReg.depth = 4;
defparam writeIntReg.width = 1;
memMod_dist s2mem0(s0, y0, {inFlip1, s2wr0}, {outFlip1, s2rdloc}, s2wr_en, clk);
defparam s2mem0.depth = 46;
defparam s2mem0.width = 32;
defparam s2mem0.logDepth = 6;
memMod_dist s2mem1(s1, y1, {inFlip1, s2wr1}, {outFlip1, s2rdloc}, s2wr_en, clk);
defparam s2mem1.depth = 46;
defparam s2mem1.width = 32;
defparam s2mem1.logDepth = 6;
always @(posedge clk) begin
if (reset == 1) begin
state1 <= 0;
inFlip0 <= 0;
end
else if (next == 1) begin
s1wr0 <= 0;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
else begin
case(state1)
0: begin
s1wr0 <= 0;
state1 <= 0;
s1wr_en <= 0;
inFlip0 <= inFlip0;
end
1: begin
s1wr0 <= (s1wr0 == depth-1) ? 0 : s1wr0 + 1;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state2 <= 0;
outFlip0_z <= 0;
end
else if (next2 == 1) begin
s1rdloc <= 0;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
else begin
case(state2)
0: begin
s1rdloc <= 0;
state2 <= 0;
outFlip0_z <= outFlip0_z;
end
1: begin
s1rdloc <= (s1rdloc == depth-1) ? 0 : s1rdloc + 1;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state3 <= 0;
outFlip1 <= 0;
end
else if (next4 == 1) begin
s2rdloc <= 0;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
else begin
case(state3)
0: begin
s2rdloc <= 0;
state3 <= 0;
outFlip1 <= outFlip1;
end
1: begin
s2rdloc <= (s2rdloc == depth-1) ? 0 : s2rdloc + 1;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
endcase
end
end
always @(posedge clk) begin
case({tm0_d, s1rdloc})
{1'd0, 5'd0}: s1rd0 <= 16;
{1'd0, 5'd1}: s1rd0 <= 24;
{1'd0, 5'd2}: s1rd0 <= 20;
{1'd0, 5'd3}: s1rd0 <= 28;
{1'd0, 5'd4}: s1rd0 <= 18;
{1'd0, 5'd5}: s1rd0 <= 26;
{1'd0, 5'd6}: s1rd0 <= 22;
{1'd0, 5'd7}: s1rd0 <= 30;
{1'd0, 5'd8}: s1rd0 <= 17;
{1'd0, 5'd9}: s1rd0 <= 25;
{1'd0, 5'd10}: s1rd0 <= 21;
{1'd0, 5'd11}: s1rd0 <= 29;
{1'd0, 5'd12}: s1rd0 <= 19;
{1'd0, 5'd13}: s1rd0 <= 27;
{1'd0, 5'd14}: s1rd0 <= 23;
{1'd0, 5'd15}: s1rd0 <= 31;
{1'd0, 5'd16}: s1rd0 <= 0;
{1'd0, 5'd17}: s1rd0 <= 8;
{1'd0, 5'd18}: s1rd0 <= 4;
{1'd0, 5'd19}: s1rd0 <= 12;
{1'd0, 5'd20}: s1rd0 <= 2;
{1'd0, 5'd21}: s1rd0 <= 10;
{1'd0, 5'd22}: s1rd0 <= 6;
{1'd0, 5'd23}: s1rd0 <= 14;
{1'd0, 5'd24}: s1rd0 <= 1;
{1'd0, 5'd25}: s1rd0 <= 9;
{1'd0, 5'd26}: s1rd0 <= 5;
{1'd0, 5'd27}: s1rd0 <= 13;
{1'd0, 5'd28}: s1rd0 <= 3;
{1'd0, 5'd29}: s1rd0 <= 11;
{1'd0, 5'd30}: s1rd0 <= 7;
{1'd0, 5'd31}: s1rd0 <= 15;
endcase
end
// synthesis attribute rom_style of s1rd0 is "block"
always @(posedge clk) begin
case({tm0_d, s1rdloc})
{1'd0, 5'd0}: s1rd1 <= 0;
{1'd0, 5'd1}: s1rd1 <= 8;
{1'd0, 5'd2}: s1rd1 <= 4;
{1'd0, 5'd3}: s1rd1 <= 12;
{1'd0, 5'd4}: s1rd1 <= 2;
{1'd0, 5'd5}: s1rd1 <= 10;
{1'd0, 5'd6}: s1rd1 <= 6;
{1'd0, 5'd7}: s1rd1 <= 14;
{1'd0, 5'd8}: s1rd1 <= 1;
{1'd0, 5'd9}: s1rd1 <= 9;
{1'd0, 5'd10}: s1rd1 <= 5;
{1'd0, 5'd11}: s1rd1 <= 13;
{1'd0, 5'd12}: s1rd1 <= 3;
{1'd0, 5'd13}: s1rd1 <= 11;
{1'd0, 5'd14}: s1rd1 <= 7;
{1'd0, 5'd15}: s1rd1 <= 15;
{1'd0, 5'd16}: s1rd1 <= 16;
{1'd0, 5'd17}: s1rd1 <= 24;
{1'd0, 5'd18}: s1rd1 <= 20;
{1'd0, 5'd19}: s1rd1 <= 28;
{1'd0, 5'd20}: s1rd1 <= 18;
{1'd0, 5'd21}: s1rd1 <= 26;
{1'd0, 5'd22}: s1rd1 <= 22;
{1'd0, 5'd23}: s1rd1 <= 30;
{1'd0, 5'd24}: s1rd1 <= 17;
{1'd0, 5'd25}: s1rd1 <= 25;
{1'd0, 5'd26}: s1rd1 <= 21;
{1'd0, 5'd27}: s1rd1 <= 29;
{1'd0, 5'd28}: s1rd1 <= 19;
{1'd0, 5'd29}: s1rd1 <= 27;
{1'd0, 5'd30}: s1rd1 <= 23;
{1'd0, 5'd31}: s1rd1 <= 31;
endcase
end
// synthesis attribute rom_style of s1rd1 is "block"
swNet30653 sw(tm0_d, clk, muxCycle, t0, s0, t1, s1);
always @(posedge clk) begin
case({tm0_dd, writeCycle})
{1'd0, 5'd0}: s2wr0 <= 16;
{1'd0, 5'd1}: s2wr0 <= 17;
{1'd0, 5'd2}: s2wr0 <= 18;
{1'd0, 5'd3}: s2wr0 <= 19;
{1'd0, 5'd4}: s2wr0 <= 20;
{1'd0, 5'd5}: s2wr0 <= 21;
{1'd0, 5'd6}: s2wr0 <= 22;
{1'd0, 5'd7}: s2wr0 <= 23;
{1'd0, 5'd8}: s2wr0 <= 24;
{1'd0, 5'd9}: s2wr0 <= 25;
{1'd0, 5'd10}: s2wr0 <= 26;
{1'd0, 5'd11}: s2wr0 <= 27;
{1'd0, 5'd12}: s2wr0 <= 28;
{1'd0, 5'd13}: s2wr0 <= 29;
{1'd0, 5'd14}: s2wr0 <= 30;
{1'd0, 5'd15}: s2wr0 <= 31;
{1'd0, 5'd16}: s2wr0 <= 0;
{1'd0, 5'd17}: s2wr0 <= 1;
{1'd0, 5'd18}: s2wr0 <= 2;
{1'd0, 5'd19}: s2wr0 <= 3;
{1'd0, 5'd20}: s2wr0 <= 4;
{1'd0, 5'd21}: s2wr0 <= 5;
{1'd0, 5'd22}: s2wr0 <= 6;
{1'd0, 5'd23}: s2wr0 <= 7;
{1'd0, 5'd24}: s2wr0 <= 8;
{1'd0, 5'd25}: s2wr0 <= 9;
{1'd0, 5'd26}: s2wr0 <= 10;
{1'd0, 5'd27}: s2wr0 <= 11;
{1'd0, 5'd28}: s2wr0 <= 12;
{1'd0, 5'd29}: s2wr0 <= 13;
{1'd0, 5'd30}: s2wr0 <= 14;
{1'd0, 5'd31}: s2wr0 <= 15;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr0 is "block"
always @(posedge clk) begin
case({tm0_dd, writeCycle})
{1'd0, 5'd0}: s2wr1 <= 0;
{1'd0, 5'd1}: s2wr1 <= 1;
{1'd0, 5'd2}: s2wr1 <= 2;
{1'd0, 5'd3}: s2wr1 <= 3;
{1'd0, 5'd4}: s2wr1 <= 4;
{1'd0, 5'd5}: s2wr1 <= 5;
{1'd0, 5'd6}: s2wr1 <= 6;
{1'd0, 5'd7}: s2wr1 <= 7;
{1'd0, 5'd8}: s2wr1 <= 8;
{1'd0, 5'd9}: s2wr1 <= 9;
{1'd0, 5'd10}: s2wr1 <= 10;
{1'd0, 5'd11}: s2wr1 <= 11;
{1'd0, 5'd12}: s2wr1 <= 12;
{1'd0, 5'd13}: s2wr1 <= 13;
{1'd0, 5'd14}: s2wr1 <= 14;
{1'd0, 5'd15}: s2wr1 <= 15;
{1'd0, 5'd16}: s2wr1 <= 16;
{1'd0, 5'd17}: s2wr1 <= 17;
{1'd0, 5'd18}: s2wr1 <= 18;
{1'd0, 5'd19}: s2wr1 <= 19;
{1'd0, 5'd20}: s2wr1 <= 20;
{1'd0, 5'd21}: s2wr1 <= 21;
{1'd0, 5'd22}: s2wr1 <= 22;
{1'd0, 5'd23}: s2wr1 <= 23;
{1'd0, 5'd24}: s2wr1 <= 24;
{1'd0, 5'd25}: s2wr1 <= 25;
{1'd0, 5'd26}: s2wr1 <= 26;
{1'd0, 5'd27}: s2wr1 <= 27;
{1'd0, 5'd28}: s2wr1 <= 28;
{1'd0, 5'd29}: s2wr1 <= 29;
{1'd0, 5'd30}: s2wr1 <= 30;
{1'd0, 5'd31}: s2wr1 <= 31;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr1 is "block"
endmodule
module memMod(in, out, inAddr, outAddr, writeSel, clk);
parameter depth=1024, width=16, logDepth=10;
input [width-1:0] in;
input [logDepth-1:0] inAddr, outAddr;
input writeSel, clk;
output [width-1:0] out;
reg [width-1:0] out;
// synthesis attribute ram_style of mem is block
reg [width-1:0] mem[depth-1:0];
always @(posedge clk) begin
out <= mem[outAddr];
if (writeSel)
mem[inAddr] <= in;
end
endmodule
module memMod_dist(in, out, inAddr, outAddr, writeSel, clk);
parameter depth=1024;
parameter width=16;
parameter logDepth=10;
input [width-1:0] in;
input [logDepth-1:0] inAddr, outAddr;
input writeSel, clk;
output [width-1:0] out;
reg [width-1:0] out;
// synthesis attribute ram_style of mem is distributed
reg [width-1:0] mem[depth-1:0];
always @(posedge clk) begin
out <= mem[outAddr];
if (writeSel)
mem[inAddr] <= in;
end
endmodule
module shiftRegFIFO(X, Y, clk);
parameter depth=1;
parameter width=1;
output [width-1:0] Y;
input [width-1:0] X;
input clk;
reg [width-1:0] mem [depth-1:0];
integer index;
assign Y = mem[depth-1];
always @ (posedge clk) begin
for(index=1;index<depth;index=index+1) begin
mem[index] <= mem[index-1];
end
mem[0]<=X;
end
endmodule
module nextReg(X, Y, reset, clk);
parameter depth=2;
parameter logDepth=1;
output Y;
input X;
input clk, reset;
reg [logDepth:0] count;
reg active;
assign Y = (count == depth) ? 1 : 0;
always @ (posedge clk) begin
if (reset == 1) begin
count <= 0;
active <= 0;
end
else if (X == 1) begin
active <= 1;
count <= 1;
end
else if (count == depth) begin
count <= 0;
active <= 0;
end
else if (active)
count <= count+1;
end
endmodule
// Latency: 2
// Gap: 1
module codeBlock30657(clk, reset, next_in, next_out,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO shiftFIFO_33239(.X(next), .Y(next_out), .clk(clk));
defparam shiftFIFO_33239.depth = 1;
defparam shiftFIFO_33239.width = 1;
wire [15:0] a309; // signed
wire [15:0] a310; // signed
wire [15:0] a311; // signed
wire [15:0] a312; // signed
wire [15:0] t141; // signed
wire [15:0] t142; // signed
wire [15:0] t143; // signed
wire [15:0] t144; // signed
wire [15:0] Y0; // signed
wire [15:0] Y1; // signed
wire [15:0] Y2; // signed
wire [15:0] Y3; // signed
assign a309 = X0;
assign a310 = X2;
assign a311 = X1;
assign a312 = X3;
assign Y0 = t141;
assign Y1 = t142;
assign Y2 = t143;
assign Y3 = t144;
addfxp add30669(.a(a309), .b(a310), .clk(clk), .q(t141)); // 0
defparam add30669.width = 16;
addfxp add30684(.a(a311), .b(a312), .clk(clk), .q(t142)); // 0
defparam add30684.width = 16;
subfxp sub30698(.a(a309), .b(a310), .clk(clk), .q(t143)); // 0
defparam sub30698.width = 16;
subfxp sub30712(.a(a311), .b(a312), .clk(clk), .q(t144)); // 0
defparam sub30712.width = 16;
always @(posedge clk) begin
if (reset != 1) begin
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
end
end
endmodule
// Latency: 8
// Gap: 2
module rc30737(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
wire [31:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[31:16];
assign Y1 = s0[15:0];
assign Y2 = s1[31:16];
assign Y3 = s1[15:0];
perm30735 instPerm33240(.x0(t0), .y0(s0),
.x1(t1), .y1(s1),
.clk(clk), .next(next), .next_out(next_out), .reset(reset)
);
endmodule
module swNet30735(itr, clk, ct
, x0, y0
, x1, y1
);
parameter width = 32;
input [0:0] ct;
input clk;
input [0:0] itr;
input [width-1:0] x0;
output [width-1:0] y0;
reg [width-1:0] y0;
input [width-1:0] x1;
output [width-1:0] y1;
reg [width-1:0] y1;
wire [width-1:0] t0_0, t0_1;
reg [width-1:0] t1_0, t1_1;
reg [0:0] control;
always @(posedge clk) begin
case(ct)
1'd0: control <= 1'b1;
1'd1: control <= 1'b0;
endcase
end
// synthesis attribute rom_style of control is "distributed"
reg [0:0] control0;
always @(posedge clk) begin
control0 <= control;
end
assign t0_0 = x0;
assign t0_1 = x1;
always @(posedge clk) begin
t1_0 <= (control0[0] == 0) ? t0_0 : t0_1;
t1_1 <= (control0[0] == 0) ? t0_1 : t0_0;
end
always @(posedge clk) begin
y0 <= t1_0;
y1 <= t1_1;
end
endmodule
// Latency: 8
// Gap: 2
module perm30735(clk, next, reset, next_out,
x0, y0,
x1, y1);
parameter width = 32;
parameter depth = 2;
parameter depthX2 = 64;
parameter addrbits = 1;
parameter addrbitsplusone = 6;
parameter muxbits = 1;
input [width-1:0] x0;
output [width-1:0] y0;
wire [width-1:0] t0;
wire [width-1:0] s0;
input [width-1:0] x1;
output [width-1:0] y1;
wire [width-1:0] t1;
wire [width-1:0] s1;
input next, reset, clk;
output next_out;
reg [addrbits-1:0] s1rdloc, s2rdloc;
reg [addrbits-1:0] s1wr0;
reg [addrbits-1:0] s1rd0, s2wr0, s2rd0;
reg [addrbits-1:0] s1rd1, s2wr1, s2rd1;
reg s1wr_en, state1, state2, state3;
wire next2, next3, next4;
reg inFlip0, outFlip0_z, outFlip1;
wire inFlip1, outFlip0;
wire [0:0] tm1;
assign tm1 = 0;
shiftRegFIFO shiftFIFO_33245(.X(outFlip0), .Y(inFlip1), .clk(clk));
defparam shiftFIFO_33245.depth = 3;
defparam shiftFIFO_33245.width = 1;
shiftRegFIFO shiftFIFO_33246(.X(outFlip0_z), .Y(outFlip0), .clk(clk));
defparam shiftFIFO_33246.depth = 1;
defparam shiftFIFO_33246.width = 1;
// // shiftRegFIFO inFlip1Reg(outFlip0, inFlip1,
// defparam shiftRegFIFO.depth = 2;
// wi shiftRegFIFO.dth = 1;
// // shiftRegFIFO outFlip0Reg(outFlip0_z, outFlip0,
// defparam shiftRegFIFO.depth = 1;
// wi shiftRegFIFO.dth = 1;
memMod_dist s1mem0(x0, t0, {inFlip0, s1wr0}, {outFlip0, s1rd0}, s1wr_en, clk);
defparam s1mem0.depth = 8;
defparam s1mem0.width = 32;
defparam s1mem0.logDepth = 6;
memMod_dist s1mem1(x1, t1, {inFlip0, s1wr0}, {outFlip0, s1rd1}, s1wr_en, clk);
defparam s1mem1.depth = 8;
defparam s1mem1.width = 32;
defparam s1mem1.logDepth = 6;
shiftRegFIFO shiftFIFO_33255(.X(next), .Y(next2), .clk(clk));
defparam shiftFIFO_33255.depth = 1;
defparam shiftFIFO_33255.width = 1;
shiftRegFIFO shiftFIFO_33256(.X(next2), .Y(next3), .clk(clk));
defparam shiftFIFO_33256.depth = 4;
defparam shiftFIFO_33256.width = 1;
shiftRegFIFO shiftFIFO_33257(.X(next3), .Y(next4), .clk(clk));
defparam shiftFIFO_33257.depth = 2;
defparam shiftFIFO_33257.width = 1;
shiftRegFIFO shiftFIFO_33258(.X(next4), .Y(next_out), .clk(clk));
defparam shiftFIFO_33258.depth = 1;
defparam shiftFIFO_33258.width = 1;
shiftRegFIFO shiftFIFO_33261(.X(tm1), .Y(tm1_d), .clk(clk));
defparam shiftFIFO_33261.depth = 1;
defparam shiftFIFO_33261.width = 1;
shiftRegFIFO shiftFIFO_33264(.X(tm1_d), .Y(tm1_dd), .clk(clk));
defparam shiftFIFO_33264.depth = 3;
defparam shiftFIFO_33264.width = 1;
// // shiftRegFIFO1) n1(next, next2,
// defparam shiftRegFIFO1.depth = dept;
// wi shiftRegFIFO1.dth = 1;,
// // shiftRegFIFO n2(next2, next3,
// defparam shiftRegFIFO.depth = 3;
// wi shiftRegFIFO.dth = 1;
// // shiftRegFIFO n3(next3, next4,
// defparam shiftRegFIFO.depth = depth;
// wi shiftRegFIFO.dth = 1;
// // shiftRegFIFO n4(next4, next_out,
// defparam shiftRegFIFO.depth = 1;
// wi shiftRegFIFO.dth = 1;
wire [addrbits-1:0] muxCycle, writeCycle;
assign muxCycle = s1rdloc;
shiftRegFIFO shiftFIFO_33269(.X(muxCycle), .Y(writeCycle), .clk(clk));
defparam shiftFIFO_33269.depth = 3;
defparam shiftFIFO_33269.width = 1;
wire readInt, s2wr_en;
assign readInt = (state2 == 1);
shiftRegFIFO writeIntReg(readInt, s2wr_en, clk);
defparam writeIntReg.depth = 4;
defparam writeIntReg.width = 1;
memMod_dist s2mem0(s0, y0, {inFlip1, s2wr0}, {outFlip1, s2rdloc}, s2wr_en, clk);
defparam s2mem0.depth = 8;
defparam s2mem0.width = 32;
defparam s2mem0.logDepth = 6;
memMod_dist s2mem1(s1, y1, {inFlip1, s2wr1}, {outFlip1, s2rdloc}, s2wr_en, clk);
defparam s2mem1.depth = 8;
defparam s2mem1.width = 32;
defparam s2mem1.logDepth = 6;
always @(posedge clk) begin
if (reset == 1) begin
state1 <= 0;
inFlip0 <= 0;
end
else if (next == 1) begin
s1wr0 <= 0;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
else begin
case(state1)
0: begin
s1wr0 <= 0;
state1 <= 0;
s1wr_en <= 0;
inFlip0 <= inFlip0;
end
1: begin
s1wr0 <= (s1wr0 == depth-1) ? 0 : s1wr0 + 1;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state2 <= 0;
outFlip0_z <= 0;
end
else if (next2 == 1) begin
s1rdloc <= 0;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
else begin
case(state2)
0: begin
s1rdloc <= 0;
state2 <= 0;
outFlip0_z <= outFlip0_z;
end
1: begin
s1rdloc <= (s1rdloc == depth-1) ? 0 : s1rdloc + 1;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state3 <= 0;
outFlip1 <= 0;
end
else if (next4 == 1) begin
s2rdloc <= 0;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
else begin
case(state3)
0: begin
s2rdloc <= 0;
state3 <= 0;
outFlip1 <= outFlip1;
end
1: begin
s2rdloc <= (s2rdloc == depth-1) ? 0 : s2rdloc + 1;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
endcase
end
end
always @(posedge clk) begin
case({tm1_d, s1rdloc})
{1'd0, 1'd0}: s1rd0 <= 1;
{1'd0, 1'd1}: s1rd0 <= 0;
endcase
end
// synthesis attribute rom_style of s1rd0 is "block"
always @(posedge clk) begin
case({tm1_d, s1rdloc})
{1'd0, 1'd0}: s1rd1 <= 0;
{1'd0, 1'd1}: s1rd1 <= 1;
endcase
end
// synthesis attribute rom_style of s1rd1 is "block"
swNet30735 sw(tm1_d, clk, muxCycle, t0, s0, t1, s1);
always @(posedge clk) begin
case({tm1_dd, writeCycle})
{1'd0, 1'd0}: s2wr0 <= 1;
{1'd0, 1'd1}: s2wr0 <= 0;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr0 is "block"
always @(posedge clk) begin
case({tm1_dd, writeCycle})
{1'd0, 1'd0}: s2wr1 <= 0;
{1'd0, 1'd1}: s2wr1 <= 1;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr1 is "block"
endmodule
// Latency: 8
// Gap: 2
module DirSum_30916(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
reg [0:0] i5;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
always @(posedge clk) begin
if (reset == 1) begin
i5 <= 0;
end
else begin
if (next == 1)
i5 <= 0;
else if (i5 == 1)
i5 <= 0;
else
i5 <= i5 + 1;
end
end
codeBlock30740 codeBlockIsnt33270(.clk(clk), .reset(reset), .next_in(next), .next_out(next_out),
.i5_in(i5),
.X0_in(X0), .Y0(Y0),
.X1_in(X1), .Y1(Y1),
.X2_in(X2), .Y2(Y2),
.X3_in(X3), .Y3(Y3));
endmodule
module D18_30906(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [0:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h4000;
1: out3 <= 16'h0;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
module D20_30914(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [0:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h0;
1: out3 <= 16'hc000;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
// Latency: 8
// Gap: 1
module codeBlock30740(clk, reset, next_in, next_out,
i5_in,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [0:0] i5_in;
reg [0:0] i5;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO shiftFIFO_33273(.X(next), .Y(next_out), .clk(clk));
defparam shiftFIFO_33273.depth = 7;
defparam shiftFIFO_33273.width = 1;
wire [15:0] a293; // signed
wire [15:0] a282; // signed
wire [15:0] a296; // signed
wire [15:0] a286; // signed
wire [15:0] a297; // signed
wire [15:0] a298; // signed
reg [15:0] tm137; // signed
reg [15:0] tm141; // signed
reg [15:0] tm153; // signed
reg [15:0] tm160; // signed
reg [15:0] tm138; // signed
reg [15:0] tm142; // signed
reg [15:0] tm154; // signed
reg [15:0] tm161; // signed
wire [15:0] tm4; // signed
wire [15:0] a287; // signed
wire [15:0] tm5; // signed
wire [15:0] a289; // signed
reg [15:0] tm139; // signed
reg [15:0] tm143; // signed
reg [15:0] tm155; // signed
reg [15:0] tm162; // signed
reg [15:0] tm31; // signed
reg [15:0] tm32; // signed
reg [15:0] tm140; // signed
reg [15:0] tm144; // signed
reg [15:0] tm156; // signed
reg [15:0] tm163; // signed
reg [15:0] tm157; // signed
reg [15:0] tm164; // signed
wire [15:0] a288; // signed
wire [15:0] a290; // signed
wire [15:0] a291; // signed
wire [15:0] a292; // signed
reg [15:0] tm158; // signed
reg [15:0] tm165; // signed
wire [15:0] Y0; // signed
wire [15:0] Y1; // signed
wire [15:0] Y2; // signed
wire [15:0] Y3; // signed
reg [15:0] tm159; // signed
reg [15:0] tm166; // signed
assign a293 = X0;
assign a282 = a293;
assign a296 = X1;
assign a286 = a296;
assign a297 = X2;
assign a298 = X3;
assign a287 = tm4;
assign a289 = tm5;
assign Y0 = tm159;
assign Y1 = tm166;
D18_30906 instD18inst0_30906(.addr(i5[0:0]), .out(tm4), .clk(clk));
D20_30914 instD20inst0_30914(.addr(i5[0:0]), .out(tm5), .clk(clk));
multfix m30838(.a(tm31), .b(tm140), .clk(clk), .q_sc(a288), .rst(reset));
defparam m30838.WIDTH = 16;
multfix m30860(.a(tm32), .b(tm144), .clk(clk), .q_sc(a290), .rst(reset));
defparam m30860.WIDTH = 16;
multfix m30877(.a(tm32), .b(tm140), .clk(clk), .q_sc(a291), .rst(reset));
defparam m30877.WIDTH = 16;
multfix m30888(.a(tm31), .b(tm144), .clk(clk), .q_sc(a292), .rst(reset));
defparam m30888.WIDTH = 16;
subfxp sub30866(.a(a288), .b(a290), .clk(clk), .q(Y2)); // 6
defparam sub30866.width = 16;
addfxp add30895(.a(a291), .b(a292), .clk(clk), .q(Y3)); // 6
defparam add30895.width = 16;
always @(posedge clk) begin
if (reset == 1) begin
tm31 <= 0;
tm140 <= 0;
tm32 <= 0;
tm144 <= 0;
tm32 <= 0;
tm140 <= 0;
tm31 <= 0;
tm144 <= 0;
end
else begin
i5 <= i5_in;
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
tm137 <= a297;
tm141 <= a298;
tm153 <= a282;
tm160 <= a286;
tm138 <= tm137;
tm142 <= tm141;
tm154 <= tm153;
tm161 <= tm160;
tm139 <= tm138;
tm143 <= tm142;
tm155 <= tm154;
tm162 <= tm161;
tm31 <= a287;
tm32 <= a289;
tm140 <= tm139;
tm144 <= tm143;
tm156 <= tm155;
tm163 <= tm162;
tm157 <= tm156;
tm164 <= tm163;
tm158 <= tm157;
tm165 <= tm164;
tm159 <= tm158;
tm166 <= tm165;
end
end
endmodule
// Latency: 2
// Gap: 1
module codeBlock30919(clk, reset, next_in, next_out,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO shiftFIFO_33276(.X(next), .Y(next_out), .clk(clk));
defparam shiftFIFO_33276.depth = 1;
defparam shiftFIFO_33276.width = 1;
wire [15:0] a249; // signed
wire [15:0] a250; // signed
wire [15:0] a251; // signed
wire [15:0] a252; // signed
wire [15:0] t117; // signed
wire [15:0] t118; // signed
wire [15:0] t119; // signed
wire [15:0] t120; // signed
wire [15:0] Y0; // signed
wire [15:0] Y1; // signed
wire [15:0] Y2; // signed
wire [15:0] Y3; // signed
assign a249 = X0;
assign a250 = X2;
assign a251 = X1;
assign a252 = X3;
assign Y0 = t117;
assign Y1 = t118;
assign Y2 = t119;
assign Y3 = t120;
addfxp add30931(.a(a249), .b(a250), .clk(clk), .q(t117)); // 0
defparam add30931.width = 16;
addfxp add30946(.a(a251), .b(a252), .clk(clk), .q(t118)); // 0
defparam add30946.width = 16;
subfxp sub30960(.a(a249), .b(a250), .clk(clk), .q(t119)); // 0
defparam sub30960.width = 16;
subfxp sub30974(.a(a251), .b(a252), .clk(clk), .q(t120)); // 0
defparam sub30974.width = 16;
always @(posedge clk) begin
if (reset != 1) begin
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
end
end
endmodule
// Latency: 12
// Gap: 4
module rc30999(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
wire [31:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[31:16];
assign Y1 = s0[15:0];
assign Y2 = s1[31:16];
assign Y3 = s1[15:0];
perm30997 instPerm33277(.x0(t0), .y0(s0),
.x1(t1), .y1(s1),
.clk(clk), .next(next), .next_out(next_out), .reset(reset)
);
endmodule
module swNet30997(itr, clk, ct
, x0, y0
, x1, y1
);
parameter width = 32;
input [1:0] ct;
input clk;
input [0:0] itr;
input [width-1:0] x0;
output [width-1:0] y0;
reg [width-1:0] y0;
input [width-1:0] x1;
output [width-1:0] y1;
reg [width-1:0] y1;
wire [width-1:0] t0_0, t0_1;
reg [width-1:0] t1_0, t1_1;
reg [0:0] control;
always @(posedge clk) begin
case(ct)
2'd0: control <= 1'b1;
2'd1: control <= 1'b1;
2'd2: control <= 1'b0;
2'd3: control <= 1'b0;
endcase
end
// synthesis attribute rom_style of control is "distributed"
reg [0:0] control0;
always @(posedge clk) begin
control0 <= control;
end
assign t0_0 = x0;
assign t0_1 = x1;
always @(posedge clk) begin
t1_0 <= (control0[0] == 0) ? t0_0 : t0_1;
t1_1 <= (control0[0] == 0) ? t0_1 : t0_0;
end
always @(posedge clk) begin
y0 <= t1_0;
y1 <= t1_1;
end
endmodule
// Latency: 12
// Gap: 4
module perm30997(clk, next, reset, next_out,
x0, y0,
x1, y1);
parameter width = 32;
parameter depth = 4;
parameter depthX2 = 64;
parameter addrbits = 2;
parameter addrbitsplusone = 6;
parameter muxbits = 1;
input [width-1:0] x0;
output [width-1:0] y0;
wire [width-1:0] t0;
wire [width-1:0] s0;
input [width-1:0] x1;
output [width-1:0] y1;
wire [width-1:0] t1;
wire [width-1:0] s1;
input next, reset, clk;
output next_out;
reg [addrbits-1:0] s1rdloc, s2rdloc;
reg [addrbits-1:0] s1wr0;
reg [addrbits-1:0] s1rd0, s2wr0, s2rd0;
reg [addrbits-1:0] s1rd1, s2wr1, s2rd1;
reg s1wr_en, state1, state2, state3;
wire next2, next3, next4;
reg inFlip0, outFlip0_z, outFlip1;
wire inFlip1, outFlip0;
wire [0:0] tm6;
assign tm6 = 0;
shiftRegFIFO shiftFIFO_33282(.X(outFlip0), .Y(inFlip1), .clk(clk));
defparam shiftFIFO_33282.depth = 3;
defparam shiftFIFO_33282.width = 1;
shiftRegFIFO shiftFIFO_33283(.X(outFlip0_z), .Y(outFlip0), .clk(clk));
defparam shiftFIFO_33283.depth = 1;
defparam shiftFIFO_33283.width = 1;
// // shiftRegFIFO inFlip1Reg(outFlip0, inFlip1,
// defparam shiftRegFIFO.depth = 2;
// wi shiftRegFIFO.dth = 1;
// // shiftRegFIFO outFlip0Reg(outFlip0_z, outFlip0,
// defparam shiftRegFIFO.depth = 1;
// wi shiftRegFIFO.dth = 1;
memMod_dist s1mem0(x0, t0, {inFlip0, s1wr0}, {outFlip0, s1rd0}, s1wr_en, clk);
defparam s1mem0.depth = 8;
defparam s1mem0.width = 32;
defparam s1mem0.logDepth = 6;
memMod_dist s1mem1(x1, t1, {inFlip0, s1wr0}, {outFlip0, s1rd1}, s1wr_en, clk);
defparam s1mem1.depth = 8;
defparam s1mem1.width = 32;
defparam s1mem1.logDepth = 6;
shiftRegFIFO shiftFIFO_33292(.X(next), .Y(next2), .clk(clk));
defparam shiftFIFO_33292.depth = 3;
defparam shiftFIFO_33292.width = 1;
shiftRegFIFO shiftFIFO_33293(.X(next2), .Y(next3), .clk(clk));
defparam shiftFIFO_33293.depth = 4;
defparam shiftFIFO_33293.width = 1;
shiftRegFIFO shiftFIFO_33294(.X(next3), .Y(next4), .clk(clk));
defparam shiftFIFO_33294.depth = 4;
defparam shiftFIFO_33294.width = 1;
shiftRegFIFO shiftFIFO_33295(.X(next4), .Y(next_out), .clk(clk));
defparam shiftFIFO_33295.depth = 1;
defparam shiftFIFO_33295.width = 1;
shiftRegFIFO shiftFIFO_33298(.X(tm6), .Y(tm6_d), .clk(clk));
defparam shiftFIFO_33298.depth = 3;
defparam shiftFIFO_33298.width = 1;
shiftRegFIFO shiftFIFO_33301(.X(tm6_d), .Y(tm6_dd), .clk(clk));
defparam shiftFIFO_33301.depth = 3;
defparam shiftFIFO_33301.width = 1;
// // shiftRegFIFO1) n1(next, next2,
// defparam shiftRegFIFO1.depth = dept;
// wi shiftRegFIFO1.dth = 1;,
// // shiftRegFIFO n2(next2, next3,
// defparam shiftRegFIFO.depth = 3;
// wi shiftRegFIFO.dth = 1;
// // shiftRegFIFO n3(next3, next4,
// defparam shiftRegFIFO.depth = depth;
// wi shiftRegFIFO.dth = 1;
// // shiftRegFIFO n4(next4, next_out,
// defparam shiftRegFIFO.depth = 1;
// wi shiftRegFIFO.dth = 1;
wire [addrbits-1:0] muxCycle, writeCycle;
assign muxCycle = s1rdloc;
shiftRegFIFO shiftFIFO_33306(.X(muxCycle), .Y(writeCycle), .clk(clk));
defparam shiftFIFO_33306.depth = 3;
defparam shiftFIFO_33306.width = 2;
wire readInt, s2wr_en;
assign readInt = (state2 == 1);
shiftRegFIFO writeIntReg(readInt, s2wr_en, clk);
defparam writeIntReg.depth = 4;
defparam writeIntReg.width = 1;
memMod_dist s2mem0(s0, y0, {inFlip1, s2wr0}, {outFlip1, s2rdloc}, s2wr_en, clk);
defparam s2mem0.depth = 8;
defparam s2mem0.width = 32;
defparam s2mem0.logDepth = 6;
memMod_dist s2mem1(s1, y1, {inFlip1, s2wr1}, {outFlip1, s2rdloc}, s2wr_en, clk);
defparam s2mem1.depth = 8;
defparam s2mem1.width = 32;
defparam s2mem1.logDepth = 6;
always @(posedge clk) begin
if (reset == 1) begin
state1 <= 0;
inFlip0 <= 0;
end
else if (next == 1) begin
s1wr0 <= 0;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
else begin
case(state1)
0: begin
s1wr0 <= 0;
state1 <= 0;
s1wr_en <= 0;
inFlip0 <= inFlip0;
end
1: begin
s1wr0 <= (s1wr0 == depth-1) ? 0 : s1wr0 + 1;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state2 <= 0;
outFlip0_z <= 0;
end
else if (next2 == 1) begin
s1rdloc <= 0;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
else begin
case(state2)
0: begin
s1rdloc <= 0;
state2 <= 0;
outFlip0_z <= outFlip0_z;
end
1: begin
s1rdloc <= (s1rdloc == depth-1) ? 0 : s1rdloc + 1;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state3 <= 0;
outFlip1 <= 0;
end
else if (next4 == 1) begin
s2rdloc <= 0;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
else begin
case(state3)
0: begin
s2rdloc <= 0;
state3 <= 0;
outFlip1 <= outFlip1;
end
1: begin
s2rdloc <= (s2rdloc == depth-1) ? 0 : s2rdloc + 1;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
endcase
end
end
always @(posedge clk) begin
case({tm6_d, s1rdloc})
{1'd0, 2'd0}: s1rd0 <= 2;
{1'd0, 2'd1}: s1rd0 <= 3;
{1'd0, 2'd2}: s1rd0 <= 0;
{1'd0, 2'd3}: s1rd0 <= 1;
endcase
end
// synthesis attribute rom_style of s1rd0 is "block"
always @(posedge clk) begin
case({tm6_d, s1rdloc})
{1'd0, 2'd0}: s1rd1 <= 0;
{1'd0, 2'd1}: s1rd1 <= 1;
{1'd0, 2'd2}: s1rd1 <= 2;
{1'd0, 2'd3}: s1rd1 <= 3;
endcase
end
// synthesis attribute rom_style of s1rd1 is "block"
swNet30997 sw(tm6_d, clk, muxCycle, t0, s0, t1, s1);
always @(posedge clk) begin
case({tm6_dd, writeCycle})
{1'd0, 2'd0}: s2wr0 <= 2;
{1'd0, 2'd1}: s2wr0 <= 3;
{1'd0, 2'd2}: s2wr0 <= 0;
{1'd0, 2'd3}: s2wr0 <= 1;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr0 is "block"
always @(posedge clk) begin
case({tm6_dd, writeCycle})
{1'd0, 2'd0}: s2wr1 <= 0;
{1'd0, 2'd1}: s2wr1 <= 1;
{1'd0, 2'd2}: s2wr1 <= 2;
{1'd0, 2'd3}: s2wr1 <= 3;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr1 is "block"
endmodule
// Latency: 8
// Gap: 4
module DirSum_31186(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
reg [1:0] i4;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
always @(posedge clk) begin
if (reset == 1) begin
i4 <= 0;
end
else begin
if (next == 1)
i4 <= 0;
else if (i4 == 3)
i4 <= 0;
else
i4 <= i4 + 1;
end
end
codeBlock31002 codeBlockIsnt33307(.clk(clk), .reset(reset), .next_in(next), .next_out(next_out),
.i4_in(i4),
.X0_in(X0), .Y0(Y0),
.X1_in(X1), .Y1(Y1),
.X2_in(X2), .Y2(Y2),
.X3_in(X3), .Y3(Y3));
endmodule
module D14_31172(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [1:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h4000;
1: out3 <= 16'h2d41;
2: out3 <= 16'h0;
3: out3 <= 16'hd2bf;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
module D16_31184(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [1:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h0;
1: out3 <= 16'hd2bf;
2: out3 <= 16'hc000;
3: out3 <= 16'hd2bf;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
// Latency: 8
// Gap: 1
module codeBlock31002(clk, reset, next_in, next_out,
i4_in,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [1:0] i4_in;
reg [1:0] i4;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO shiftFIFO_33310(.X(next), .Y(next_out), .clk(clk));
defparam shiftFIFO_33310.depth = 7;
defparam shiftFIFO_33310.width = 1;
wire [15:0] a233; // signed
wire [15:0] a222; // signed
wire [15:0] a236; // signed
wire [15:0] a226; // signed
wire [15:0] a237; // signed
wire [15:0] a238; // signed
reg [15:0] tm167; // signed
reg [15:0] tm171; // signed
reg [15:0] tm183; // signed
reg [15:0] tm190; // signed
reg [15:0] tm168; // signed
reg [15:0] tm172; // signed
reg [15:0] tm184; // signed
reg [15:0] tm191; // signed
wire [15:0] tm9; // signed
wire [15:0] a227; // signed
wire [15:0] tm10; // signed
wire [15:0] a229; // signed
reg [15:0] tm169; // signed
reg [15:0] tm173; // signed
reg [15:0] tm185; // signed
reg [15:0] tm192; // signed
reg [15:0] tm39; // signed
reg [15:0] tm40; // signed
reg [15:0] tm170; // signed
reg [15:0] tm174; // signed
reg [15:0] tm186; // signed
reg [15:0] tm193; // signed
reg [15:0] tm187; // signed
reg [15:0] tm194; // signed
wire [15:0] a228; // signed
wire [15:0] a230; // signed
wire [15:0] a231; // signed
wire [15:0] a232; // signed
reg [15:0] tm188; // signed
reg [15:0] tm195; // signed
wire [15:0] Y0; // signed
wire [15:0] Y1; // signed
wire [15:0] Y2; // signed
wire [15:0] Y3; // signed
reg [15:0] tm189; // signed
reg [15:0] tm196; // signed
assign a233 = X0;
assign a222 = a233;
assign a236 = X1;
assign a226 = a236;
assign a237 = X2;
assign a238 = X3;
assign a227 = tm9;
assign a229 = tm10;
assign Y0 = tm189;
assign Y1 = tm196;
D14_31172 instD14inst0_31172(.addr(i4[1:0]), .out(tm9), .clk(clk));
D16_31184 instD16inst0_31184(.addr(i4[1:0]), .out(tm10), .clk(clk));
multfix m31100(.a(tm39), .b(tm170), .clk(clk), .q_sc(a228), .rst(reset));
defparam m31100.WIDTH = 16;
multfix m31122(.a(tm40), .b(tm174), .clk(clk), .q_sc(a230), .rst(reset));
defparam m31122.WIDTH = 16;
multfix m31139(.a(tm40), .b(tm170), .clk(clk), .q_sc(a231), .rst(reset));
defparam m31139.WIDTH = 16;
multfix m31150(.a(tm39), .b(tm174), .clk(clk), .q_sc(a232), .rst(reset));
defparam m31150.WIDTH = 16;
subfxp sub31128(.a(a228), .b(a230), .clk(clk), .q(Y2)); // 6
defparam sub31128.width = 16;
addfxp add31157(.a(a231), .b(a232), .clk(clk), .q(Y3)); // 6
defparam add31157.width = 16;
always @(posedge clk) begin
if (reset == 1) begin
tm39 <= 0;
tm170 <= 0;
tm40 <= 0;
tm174 <= 0;
tm40 <= 0;
tm170 <= 0;
tm39 <= 0;
tm174 <= 0;
end
else begin
i4 <= i4_in;
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
tm167 <= a237;
tm171 <= a238;
tm183 <= a222;
tm190 <= a226;
tm168 <= tm167;
tm172 <= tm171;
tm184 <= tm183;
tm191 <= tm190;
tm169 <= tm168;
tm173 <= tm172;
tm185 <= tm184;
tm192 <= tm191;
tm39 <= a227;
tm40 <= a229;
tm170 <= tm169;
tm174 <= tm173;
tm186 <= tm185;
tm193 <= tm192;
tm187 <= tm186;
tm194 <= tm193;
tm188 <= tm187;
tm195 <= tm194;
tm189 <= tm188;
tm196 <= tm195;
end
end
endmodule
// Latency: 2
// Gap: 1
module codeBlock31189(clk, reset, next_in, next_out,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO shiftFIFO_33313(.X(next), .Y(next_out), .clk(clk));
defparam shiftFIFO_33313.depth = 1;
defparam shiftFIFO_33313.width = 1;
wire [15:0] a189; // signed
wire [15:0] a190; // signed
wire [15:0] a191; // signed
wire [15:0] a192; // signed
wire [15:0] t93; // signed
wire [15:0] t94; // signed
wire [15:0] t95; // signed
wire [15:0] t96; // signed
wire [15:0] Y0; // signed
wire [15:0] Y1; // signed
wire [15:0] Y2; // signed
wire [15:0] Y3; // signed
assign a189 = X0;
assign a190 = X2;
assign a191 = X1;
assign a192 = X3;
assign Y0 = t93;
assign Y1 = t94;
assign Y2 = t95;
assign Y3 = t96;
addfxp add31201(.a(a189), .b(a190), .clk(clk), .q(t93)); // 0
defparam add31201.width = 16;
addfxp add31216(.a(a191), .b(a192), .clk(clk), .q(t94)); // 0
defparam add31216.width = 16;
subfxp sub31230(.a(a189), .b(a190), .clk(clk), .q(t95)); // 0
defparam sub31230.width = 16;
subfxp sub31244(.a(a191), .b(a192), .clk(clk), .q(t96)); // 0
defparam sub31244.width = 16;
always @(posedge clk) begin
if (reset != 1) begin
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
end
end
endmodule
// Latency: 20
// Gap: 8
module rc31269(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
wire [31:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[31:16];
assign Y1 = s0[15:0];
assign Y2 = s1[31:16];
assign Y3 = s1[15:0];
perm31267 instPerm33314(.x0(t0), .y0(s0),
.x1(t1), .y1(s1),
.clk(clk), .next(next), .next_out(next_out), .reset(reset)
);
endmodule
module swNet31267(itr, clk, ct
, x0, y0
, x1, y1
);
parameter width = 32;
input [2:0] ct;
input clk;
input [0:0] itr;
input [width-1:0] x0;
output [width-1:0] y0;
reg [width-1:0] y0;
input [width-1:0] x1;
output [width-1:0] y1;
reg [width-1:0] y1;
wire [width-1:0] t0_0, t0_1;
reg [width-1:0] t1_0, t1_1;
reg [0:0] control;
always @(posedge clk) begin
case(ct)
3'd0: control <= 1'b1;
3'd1: control <= 1'b1;
3'd2: control <= 1'b1;
3'd3: control <= 1'b1;
3'd4: control <= 1'b0;
3'd5: control <= 1'b0;
3'd6: control <= 1'b0;
3'd7: control <= 1'b0;
endcase
end
// synthesis attribute rom_style of control is "distributed"
reg [0:0] control0;
always @(posedge clk) begin
control0 <= control;
end
assign t0_0 = x0;
assign t0_1 = x1;
always @(posedge clk) begin
t1_0 <= (control0[0] == 0) ? t0_0 : t0_1;
t1_1 <= (control0[0] == 0) ? t0_1 : t0_0;
end
always @(posedge clk) begin
y0 <= t1_0;
y1 <= t1_1;
end
endmodule
// Latency: 20
// Gap: 8
module perm31267(clk, next, reset, next_out,
x0, y0,
x1, y1);
parameter width = 32;
parameter depth = 8;
parameter depthX2 = 64;
parameter addrbits = 3;
parameter addrbitsplusone = 6;
parameter muxbits = 1;
input [width-1:0] x0;
output [width-1:0] y0;
wire [width-1:0] t0;
wire [width-1:0] s0;
input [width-1:0] x1;
output [width-1:0] y1;
wire [width-1:0] t1;
wire [width-1:0] s1;
input next, reset, clk;
output next_out;
reg [addrbits-1:0] s1rdloc, s2rdloc;
reg [addrbits-1:0] s1wr0;
reg [addrbits-1:0] s1rd0, s2wr0, s2rd0;
reg [addrbits-1:0] s1rd1, s2wr1, s2rd1;
reg s1wr_en, state1, state2, state3;
wire next2, next3, next4;
reg inFlip0, outFlip0_z, outFlip1;
wire inFlip1, outFlip0;
wire [0:0] tm11;
assign tm11 = 0;
shiftRegFIFO shiftFIFO_33319(.X(outFlip0), .Y(inFlip1), .clk(clk));
defparam shiftFIFO_33319.depth = 3;
defparam shiftFIFO_33319.width = 1;
shiftRegFIFO shiftFIFO_33320(.X(outFlip0_z), .Y(outFlip0), .clk(clk));
defparam shiftFIFO_33320.depth = 1;
defparam shiftFIFO_33320.width = 1;
// // shiftRegFIFO inFlip1Reg(outFlip0, inFlip1,
// defparam shiftRegFIFO.depth = 2;
// wi shiftRegFIFO.dth = 1;
// // shiftRegFIFO outFlip0Reg(outFlip0_z, outFlip0,
// defparam shiftRegFIFO.depth = 1;
// wi shiftRegFIFO.dth = 1;
memMod_dist s1mem0(x0, t0, {inFlip0, s1wr0}, {outFlip0, s1rd0}, s1wr_en, clk);
defparam s1mem0.depth = 8;
defparam s1mem0.width = 32;
defparam s1mem0.logDepth = 6;
memMod_dist s1mem1(x1, t1, {inFlip0, s1wr0}, {outFlip0, s1rd1}, s1wr_en, clk);
defparam s1mem1.depth = 8;
defparam s1mem1.width = 32;
defparam s1mem1.logDepth = 6;
shiftRegFIFO shiftFIFO_33329(.X(next), .Y(next2), .clk(clk));
defparam shiftFIFO_33329.depth = 7;
defparam shiftFIFO_33329.width = 1;
shiftRegFIFO shiftFIFO_33330(.X(next2), .Y(next3), .clk(clk));
defparam shiftFIFO_33330.depth = 4;
defparam shiftFIFO_33330.width = 1;
shiftRegFIFO shiftFIFO_33331(.X(next3), .Y(next4), .clk(clk));
defparam shiftFIFO_33331.depth = 8;
defparam shiftFIFO_33331.width = 1;
shiftRegFIFO shiftFIFO_33332(.X(next4), .Y(next_out), .clk(clk));
defparam shiftFIFO_33332.depth = 1;
defparam shiftFIFO_33332.width = 1;
shiftRegFIFO shiftFIFO_33335(.X(tm11), .Y(tm11_d), .clk(clk));
defparam shiftFIFO_33335.depth = 7;
defparam shiftFIFO_33335.width = 1;
shiftRegFIFO shiftFIFO_33338(.X(tm11_d), .Y(tm11_dd), .clk(clk));
defparam shiftFIFO_33338.depth = 3;
defparam shiftFIFO_33338.width = 1;
// // shiftRegFIFO1) n1(next, next2,
// defparam shiftRegFIFO1.depth = dept;
// wi shiftRegFIFO1.dth = 1;,
// // shiftRegFIFO n2(next2, next3,
// defparam shiftRegFIFO.depth = 3;
// wi shiftRegFIFO.dth = 1;
// // shiftRegFIFO n3(next3, next4,
// defparam shiftRegFIFO.depth = depth;
// wi shiftRegFIFO.dth = 1;
// // shiftRegFIFO n4(next4, next_out,
// defparam shiftRegFIFO.depth = 1;
// wi shiftRegFIFO.dth = 1;
wire [addrbits-1:0] muxCycle, writeCycle;
assign muxCycle = s1rdloc;
shiftRegFIFO shiftFIFO_33343(.X(muxCycle), .Y(writeCycle), .clk(clk));
defparam shiftFIFO_33343.depth = 3;
defparam shiftFIFO_33343.width = 3;
wire readInt, s2wr_en;
assign readInt = (state2 == 1);
shiftRegFIFO writeIntReg(readInt, s2wr_en, clk);
defparam writeIntReg.depth = 4;
defparam writeIntReg.width = 1;
memMod_dist s2mem0(s0, y0, {inFlip1, s2wr0}, {outFlip1, s2rdloc}, s2wr_en, clk);
defparam s2mem0.depth = 8;
defparam s2mem0.width = 32;
defparam s2mem0.logDepth = 6;
memMod_dist s2mem1(s1, y1, {inFlip1, s2wr1}, {outFlip1, s2rdloc}, s2wr_en, clk);
defparam s2mem1.depth = 8;
defparam s2mem1.width = 32;
defparam s2mem1.logDepth = 6;
always @(posedge clk) begin
if (reset == 1) begin
state1 <= 0;
inFlip0 <= 0;
end
else if (next == 1) begin
s1wr0 <= 0;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
else begin
case(state1)
0: begin
s1wr0 <= 0;
state1 <= 0;
s1wr_en <= 0;
inFlip0 <= inFlip0;
end
1: begin
s1wr0 <= (s1wr0 == depth-1) ? 0 : s1wr0 + 1;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state2 <= 0;
outFlip0_z <= 0;
end
else if (next2 == 1) begin
s1rdloc <= 0;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
else begin
case(state2)
0: begin
s1rdloc <= 0;
state2 <= 0;
outFlip0_z <= outFlip0_z;
end
1: begin
s1rdloc <= (s1rdloc == depth-1) ? 0 : s1rdloc + 1;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state3 <= 0;
outFlip1 <= 0;
end
else if (next4 == 1) begin
s2rdloc <= 0;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
else begin
case(state3)
0: begin
s2rdloc <= 0;
state3 <= 0;
outFlip1 <= outFlip1;
end
1: begin
s2rdloc <= (s2rdloc == depth-1) ? 0 : s2rdloc + 1;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
endcase
end
end
always @(posedge clk) begin
case({tm11_d, s1rdloc})
{1'd0, 3'd0}: s1rd0 <= 4;
{1'd0, 3'd1}: s1rd0 <= 5;
{1'd0, 3'd2}: s1rd0 <= 6;
{1'd0, 3'd3}: s1rd0 <= 7;
{1'd0, 3'd4}: s1rd0 <= 0;
{1'd0, 3'd5}: s1rd0 <= 1;
{1'd0, 3'd6}: s1rd0 <= 2;
{1'd0, 3'd7}: s1rd0 <= 3;
endcase
end
// synthesis attribute rom_style of s1rd0 is "block"
always @(posedge clk) begin
case({tm11_d, s1rdloc})
{1'd0, 3'd0}: s1rd1 <= 0;
{1'd0, 3'd1}: s1rd1 <= 1;
{1'd0, 3'd2}: s1rd1 <= 2;
{1'd0, 3'd3}: s1rd1 <= 3;
{1'd0, 3'd4}: s1rd1 <= 4;
{1'd0, 3'd5}: s1rd1 <= 5;
{1'd0, 3'd6}: s1rd1 <= 6;
{1'd0, 3'd7}: s1rd1 <= 7;
endcase
end
// synthesis attribute rom_style of s1rd1 is "block"
swNet31267 sw(tm11_d, clk, muxCycle, t0, s0, t1, s1);
always @(posedge clk) begin
case({tm11_dd, writeCycle})
{1'd0, 3'd0}: s2wr0 <= 4;
{1'd0, 3'd1}: s2wr0 <= 5;
{1'd0, 3'd2}: s2wr0 <= 6;
{1'd0, 3'd3}: s2wr0 <= 7;
{1'd0, 3'd4}: s2wr0 <= 0;
{1'd0, 3'd5}: s2wr0 <= 1;
{1'd0, 3'd6}: s2wr0 <= 2;
{1'd0, 3'd7}: s2wr0 <= 3;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr0 is "block"
always @(posedge clk) begin
case({tm11_dd, writeCycle})
{1'd0, 3'd0}: s2wr1 <= 0;
{1'd0, 3'd1}: s2wr1 <= 1;
{1'd0, 3'd2}: s2wr1 <= 2;
{1'd0, 3'd3}: s2wr1 <= 3;
{1'd0, 3'd4}: s2wr1 <= 4;
{1'd0, 3'd5}: s2wr1 <= 5;
{1'd0, 3'd6}: s2wr1 <= 6;
{1'd0, 3'd7}: s2wr1 <= 7;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr1 is "block"
endmodule
// Latency: 8
// Gap: 8
module DirSum_31472(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
reg [2:0] i3;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
always @(posedge clk) begin
if (reset == 1) begin
i3 <= 0;
end
else begin
if (next == 1)
i3 <= 0;
else if (i3 == 7)
i3 <= 0;
else
i3 <= i3 + 1;
end
end
codeBlock31272 codeBlockIsnt33344(.clk(clk), .reset(reset), .next_in(next), .next_out(next_out),
.i3_in(i3),
.X0_in(X0), .Y0(Y0),
.X1_in(X1), .Y1(Y1),
.X2_in(X2), .Y2(Y2),
.X3_in(X3), .Y3(Y3));
endmodule
module D10_31450(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [2:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h4000;
1: out3 <= 16'h3b21;
2: out3 <= 16'h2d41;
3: out3 <= 16'h187e;
4: out3 <= 16'h0;
5: out3 <= 16'he782;
6: out3 <= 16'hd2bf;
7: out3 <= 16'hc4df;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
module D12_31470(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [2:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h0;
1: out3 <= 16'he782;
2: out3 <= 16'hd2bf;
3: out3 <= 16'hc4df;
4: out3 <= 16'hc000;
5: out3 <= 16'hc4df;
6: out3 <= 16'hd2bf;
7: out3 <= 16'he782;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
// Latency: 8
// Gap: 1
module codeBlock31272(clk, reset, next_in, next_out,
i3_in,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [2:0] i3_in;
reg [2:0] i3;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO shiftFIFO_33347(.X(next), .Y(next_out), .clk(clk));
defparam shiftFIFO_33347.depth = 7;
defparam shiftFIFO_33347.width = 1;
wire [15:0] a173; // signed
wire [15:0] a162; // signed
wire [15:0] a176; // signed
wire [15:0] a166; // signed
wire [15:0] a177; // signed
wire [15:0] a178; // signed
reg [15:0] tm197; // signed
reg [15:0] tm201; // signed
reg [15:0] tm213; // signed
reg [15:0] tm220; // signed
reg [15:0] tm198; // signed
reg [15:0] tm202; // signed
reg [15:0] tm214; // signed
reg [15:0] tm221; // signed
wire [15:0] tm14; // signed
wire [15:0] a167; // signed
wire [15:0] tm15; // signed
wire [15:0] a169; // signed
reg [15:0] tm199; // signed
reg [15:0] tm203; // signed
reg [15:0] tm215; // signed
reg [15:0] tm222; // signed
reg [15:0] tm47; // signed
reg [15:0] tm48; // signed
reg [15:0] tm200; // signed
reg [15:0] tm204; // signed
reg [15:0] tm216; // signed
reg [15:0] tm223; // signed
reg [15:0] tm217; // signed
reg [15:0] tm224; // signed
wire [15:0] a168; // signed
wire [15:0] a170; // signed
wire [15:0] a171; // signed
wire [15:0] a172; // signed
reg [15:0] tm218; // signed
reg [15:0] tm225; // signed
wire [15:0] Y0; // signed
wire [15:0] Y1; // signed
wire [15:0] Y2; // signed
wire [15:0] Y3; // signed
reg [15:0] tm219; // signed
reg [15:0] tm226; // signed
assign a173 = X0;
assign a162 = a173;
assign a176 = X1;
assign a166 = a176;
assign a177 = X2;
assign a178 = X3;
assign a167 = tm14;
assign a169 = tm15;
assign Y0 = tm219;
assign Y1 = tm226;
D10_31450 instD10inst0_31450(.addr(i3[2:0]), .out(tm14), .clk(clk));
D12_31470 instD12inst0_31470(.addr(i3[2:0]), .out(tm15), .clk(clk));
multfix m31370(.a(tm47), .b(tm200), .clk(clk), .q_sc(a168), .rst(reset));
defparam m31370.WIDTH = 16;
multfix m31392(.a(tm48), .b(tm204), .clk(clk), .q_sc(a170), .rst(reset));
defparam m31392.WIDTH = 16;
multfix m31409(.a(tm48), .b(tm200), .clk(clk), .q_sc(a171), .rst(reset));
defparam m31409.WIDTH = 16;
multfix m31420(.a(tm47), .b(tm204), .clk(clk), .q_sc(a172), .rst(reset));
defparam m31420.WIDTH = 16;
subfxp sub31398(.a(a168), .b(a170), .clk(clk), .q(Y2)); // 6
defparam sub31398.width = 16;
addfxp add31427(.a(a171), .b(a172), .clk(clk), .q(Y3)); // 6
defparam add31427.width = 16;
always @(posedge clk) begin
if (reset == 1) begin
tm47 <= 0;
tm200 <= 0;
tm48 <= 0;
tm204 <= 0;
tm48 <= 0;
tm200 <= 0;
tm47 <= 0;
tm204 <= 0;
end
else begin
i3 <= i3_in;
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
tm197 <= a177;
tm201 <= a178;
tm213 <= a162;
tm220 <= a166;
tm198 <= tm197;
tm202 <= tm201;
tm214 <= tm213;
tm221 <= tm220;
tm199 <= tm198;
tm203 <= tm202;
tm215 <= tm214;
tm222 <= tm221;
tm47 <= a167;
tm48 <= a169;
tm200 <= tm199;
tm204 <= tm203;
tm216 <= tm215;
tm223 <= tm222;
tm217 <= tm216;
tm224 <= tm223;
tm218 <= tm217;
tm225 <= tm224;
tm219 <= tm218;
tm226 <= tm225;
end
end
endmodule
// Latency: 2
// Gap: 1
module codeBlock31475(clk, reset, next_in, next_out,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO shiftFIFO_33350(.X(next), .Y(next_out), .clk(clk));
defparam shiftFIFO_33350.depth = 1;
defparam shiftFIFO_33350.width = 1;
wire [15:0] a129; // signed
wire [15:0] a130; // signed
wire [15:0] a131; // signed
wire [15:0] a132; // signed
wire [15:0] t69; // signed
wire [15:0] t70; // signed
wire [15:0] t71; // signed
wire [15:0] t72; // signed
wire [15:0] Y0; // signed
wire [15:0] Y1; // signed
wire [15:0] Y2; // signed
wire [15:0] Y3; // signed
assign a129 = X0;
assign a130 = X2;
assign a131 = X1;
assign a132 = X3;
assign Y0 = t69;
assign Y1 = t70;
assign Y2 = t71;
assign Y3 = t72;
addfxp add31487(.a(a129), .b(a130), .clk(clk), .q(t69)); // 0
defparam add31487.width = 16;
addfxp add31502(.a(a131), .b(a132), .clk(clk), .q(t70)); // 0
defparam add31502.width = 16;
subfxp sub31516(.a(a129), .b(a130), .clk(clk), .q(t71)); // 0
defparam sub31516.width = 16;
subfxp sub31530(.a(a131), .b(a132), .clk(clk), .q(t72)); // 0
defparam sub31530.width = 16;
always @(posedge clk) begin
if (reset != 1) begin
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
end
end
endmodule
// Latency: 36
// Gap: 16
module rc31555(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
wire [31:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[31:16];
assign Y1 = s0[15:0];
assign Y2 = s1[31:16];
assign Y3 = s1[15:0];
perm31553 instPerm33351(.x0(t0), .y0(s0),
.x1(t1), .y1(s1),
.clk(clk), .next(next), .next_out(next_out), .reset(reset)
);
endmodule
module swNet31553(itr, clk, ct
, x0, y0
, x1, y1
);
parameter width = 32;
input [3:0] ct;
input clk;
input [0:0] itr;
input [width-1:0] x0;
output [width-1:0] y0;
reg [width-1:0] y0;
input [width-1:0] x1;
output [width-1:0] y1;
reg [width-1:0] y1;
wire [width-1:0] t0_0, t0_1;
reg [width-1:0] t1_0, t1_1;
reg [0:0] control;
always @(posedge clk) begin
case(ct)
4'd0: control <= 1'b1;
4'd1: control <= 1'b1;
4'd2: control <= 1'b1;
4'd3: control <= 1'b1;
4'd4: control <= 1'b1;
4'd5: control <= 1'b1;
4'd6: control <= 1'b1;
4'd7: control <= 1'b1;
4'd8: control <= 1'b0;
4'd9: control <= 1'b0;
4'd10: control <= 1'b0;
4'd11: control <= 1'b0;
4'd12: control <= 1'b0;
4'd13: control <= 1'b0;
4'd14: control <= 1'b0;
4'd15: control <= 1'b0;
endcase
end
// synthesis attribute rom_style of control is "distributed"
reg [0:0] control0;
always @(posedge clk) begin
control0 <= control;
end
assign t0_0 = x0;
assign t0_1 = x1;
always @(posedge clk) begin
t1_0 <= (control0[0] == 0) ? t0_0 : t0_1;
t1_1 <= (control0[0] == 0) ? t0_1 : t0_0;
end
always @(posedge clk) begin
y0 <= t1_0;
y1 <= t1_1;
end
endmodule
// Latency: 36
// Gap: 16
module perm31553(clk, next, reset, next_out,
x0, y0,
x1, y1);
parameter width = 32;
parameter depth = 16;
parameter depthX2 = 64;
parameter addrbits = 4;
parameter addrbitsplusone = 6;
parameter muxbits = 1;
input [width-1:0] x0;
output [width-1:0] y0;
wire [width-1:0] t0;
wire [width-1:0] s0;
input [width-1:0] x1;
output [width-1:0] y1;
wire [width-1:0] t1;
wire [width-1:0] s1;
input next, reset, clk;
output next_out;
reg [addrbits-1:0] s1rdloc, s2rdloc;
reg [addrbits-1:0] s1wr0;
reg [addrbits-1:0] s1rd0, s2wr0, s2rd0;
reg [addrbits-1:0] s1rd1, s2wr1, s2rd1;
reg s1wr_en, state1, state2, state3;
wire next2, next3, next4;
reg inFlip0, outFlip0_z, outFlip1;
wire inFlip1, outFlip0;
wire [0:0] tm16;
assign tm16 = 0;
shiftRegFIFO shiftFIFO_33356(.X(outFlip0), .Y(inFlip1), .clk(clk));
defparam shiftFIFO_33356.depth = 3;
defparam shiftFIFO_33356.width = 1;
shiftRegFIFO shiftFIFO_33357(.X(outFlip0_z), .Y(outFlip0), .clk(clk));
defparam shiftFIFO_33357.depth = 1;
defparam shiftFIFO_33357.width = 1;
// // shiftRegFIFO inFlip1Reg(outFlip0, inFlip1,
// defparam shiftRegFIFO.depth = 2;
// wi shiftRegFIFO.dth = 1;
// // shiftRegFIFO outFlip0Reg(outFlip0_z, outFlip0,
// defparam shiftRegFIFO.depth = 1;
// wi shiftRegFIFO.dth = 1;
memMod_dist s1mem0(x0, t0, {inFlip0, s1wr0}, {outFlip0, s1rd0}, s1wr_en, clk);
defparam s1mem0.depth = 32;
defparam s1mem0.width = 32;
defparam s1mem0.logDepth = 6;
memMod_dist s1mem1(x1, t1, {inFlip0, s1wr0}, {outFlip0, s1rd1}, s1wr_en, clk);
defparam s1mem1.depth = 32;
defparam s1mem1.width = 32;
defparam s1mem1.logDepth = 6;
nextReg nextReg_33368(.X(next), .Y(next2), .reset(reset), .clk(clk));
defparam nextReg_33368.depth = 15;
defparam nextReg_33368.logDepth = 4;
shiftRegFIFO shiftFIFO_33369(.X(next2), .Y(next3), .clk(clk));
defparam shiftFIFO_33369.depth = 4;
defparam shiftFIFO_33369.width = 1;
nextReg nextReg_33372(.X(next3), .Y(next4), .reset(reset), .clk(clk));
defparam nextReg_33372.depth = 16;
defparam nextReg_33372.logDepth = 4;
shiftRegFIFO shiftFIFO_33373(.X(next4), .Y(next_out), .clk(clk));
defparam shiftFIFO_33373.depth = 1;
defparam shiftFIFO_33373.width = 1;
shiftRegFIFO shiftFIFO_33376(.X(tm16), .Y(tm16_d), .clk(clk));
defparam shiftFIFO_33376.depth = 15;
defparam shiftFIFO_33376.width = 1;
shiftRegFIFO shiftFIFO_33379(.X(tm16_d), .Y(tm16_dd), .clk(clk));
defparam shiftFIFO_33379.depth = 3;
defparam shiftFIFO_33379.width = 1;
// // shiftRegFIFO1) n1(next, next2,
// defparam shiftRegFIFO1.depth = dept;
// wi shiftRegFIFO1.dth = 1;,
// // shiftRegFIFO n2(next2, next3,
// defparam shiftRegFIFO.depth = 3;
// wi shiftRegFIFO.dth = 1;
// // shiftRegFIFO n3(next3, next4,
// defparam shiftRegFIFO.depth = depth;
// wi shiftRegFIFO.dth = 1;
// // shiftRegFIFO n4(next4, next_out,
// defparam shiftRegFIFO.depth = 1;
// wi shiftRegFIFO.dth = 1;
wire [addrbits-1:0] muxCycle, writeCycle;
assign muxCycle = s1rdloc;
shiftRegFIFO shiftFIFO_33384(.X(muxCycle), .Y(writeCycle), .clk(clk));
defparam shiftFIFO_33384.depth = 3;
defparam shiftFIFO_33384.width = 4;
wire readInt, s2wr_en;
assign readInt = (state2 == 1);
shiftRegFIFO writeIntReg(readInt, s2wr_en, clk);
defparam writeIntReg.depth = 4;
defparam writeIntReg.width = 1;
memMod_dist s2mem0(s0, y0, {inFlip1, s2wr0}, {outFlip1, s2rdloc}, s2wr_en, clk);
defparam s2mem0.depth = 32;
defparam s2mem0.width = 32;
defparam s2mem0.logDepth = 6;
memMod_dist s2mem1(s1, y1, {inFlip1, s2wr1}, {outFlip1, s2rdloc}, s2wr_en, clk);
defparam s2mem1.depth = 32;
defparam s2mem1.width = 32;
defparam s2mem1.logDepth = 6;
always @(posedge clk) begin
if (reset == 1) begin
state1 <= 0;
inFlip0 <= 0;
end
else if (next == 1) begin
s1wr0 <= 0;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
else begin
case(state1)
0: begin
s1wr0 <= 0;
state1 <= 0;
s1wr_en <= 0;
inFlip0 <= inFlip0;
end
1: begin
s1wr0 <= (s1wr0 == depth-1) ? 0 : s1wr0 + 1;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state2 <= 0;
outFlip0_z <= 0;
end
else if (next2 == 1) begin
s1rdloc <= 0;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
else begin
case(state2)
0: begin
s1rdloc <= 0;
state2 <= 0;
outFlip0_z <= outFlip0_z;
end
1: begin
s1rdloc <= (s1rdloc == depth-1) ? 0 : s1rdloc + 1;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state3 <= 0;
outFlip1 <= 0;
end
else if (next4 == 1) begin
s2rdloc <= 0;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
else begin
case(state3)
0: begin
s2rdloc <= 0;
state3 <= 0;
outFlip1 <= outFlip1;
end
1: begin
s2rdloc <= (s2rdloc == depth-1) ? 0 : s2rdloc + 1;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
endcase
end
end
always @(posedge clk) begin
case({tm16_d, s1rdloc})
{1'd0, 4'd0}: s1rd0 <= 8;
{1'd0, 4'd1}: s1rd0 <= 9;
{1'd0, 4'd2}: s1rd0 <= 10;
{1'd0, 4'd3}: s1rd0 <= 11;
{1'd0, 4'd4}: s1rd0 <= 12;
{1'd0, 4'd5}: s1rd0 <= 13;
{1'd0, 4'd6}: s1rd0 <= 14;
{1'd0, 4'd7}: s1rd0 <= 15;
{1'd0, 4'd8}: s1rd0 <= 0;
{1'd0, 4'd9}: s1rd0 <= 1;
{1'd0, 4'd10}: s1rd0 <= 2;
{1'd0, 4'd11}: s1rd0 <= 3;
{1'd0, 4'd12}: s1rd0 <= 4;
{1'd0, 4'd13}: s1rd0 <= 5;
{1'd0, 4'd14}: s1rd0 <= 6;
{1'd0, 4'd15}: s1rd0 <= 7;
endcase
end
// synthesis attribute rom_style of s1rd0 is "block"
always @(posedge clk) begin
case({tm16_d, s1rdloc})
{1'd0, 4'd0}: s1rd1 <= 0;
{1'd0, 4'd1}: s1rd1 <= 1;
{1'd0, 4'd2}: s1rd1 <= 2;
{1'd0, 4'd3}: s1rd1 <= 3;
{1'd0, 4'd4}: s1rd1 <= 4;
{1'd0, 4'd5}: s1rd1 <= 5;
{1'd0, 4'd6}: s1rd1 <= 6;
{1'd0, 4'd7}: s1rd1 <= 7;
{1'd0, 4'd8}: s1rd1 <= 8;
{1'd0, 4'd9}: s1rd1 <= 9;
{1'd0, 4'd10}: s1rd1 <= 10;
{1'd0, 4'd11}: s1rd1 <= 11;
{1'd0, 4'd12}: s1rd1 <= 12;
{1'd0, 4'd13}: s1rd1 <= 13;
{1'd0, 4'd14}: s1rd1 <= 14;
{1'd0, 4'd15}: s1rd1 <= 15;
endcase
end
// synthesis attribute rom_style of s1rd1 is "block"
swNet31553 sw(tm16_d, clk, muxCycle, t0, s0, t1, s1);
always @(posedge clk) begin
case({tm16_dd, writeCycle})
{1'd0, 4'd0}: s2wr0 <= 8;
{1'd0, 4'd1}: s2wr0 <= 9;
{1'd0, 4'd2}: s2wr0 <= 10;
{1'd0, 4'd3}: s2wr0 <= 11;
{1'd0, 4'd4}: s2wr0 <= 12;
{1'd0, 4'd5}: s2wr0 <= 13;
{1'd0, 4'd6}: s2wr0 <= 14;
{1'd0, 4'd7}: s2wr0 <= 15;
{1'd0, 4'd8}: s2wr0 <= 0;
{1'd0, 4'd9}: s2wr0 <= 1;
{1'd0, 4'd10}: s2wr0 <= 2;
{1'd0, 4'd11}: s2wr0 <= 3;
{1'd0, 4'd12}: s2wr0 <= 4;
{1'd0, 4'd13}: s2wr0 <= 5;
{1'd0, 4'd14}: s2wr0 <= 6;
{1'd0, 4'd15}: s2wr0 <= 7;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr0 is "block"
always @(posedge clk) begin
case({tm16_dd, writeCycle})
{1'd0, 4'd0}: s2wr1 <= 0;
{1'd0, 4'd1}: s2wr1 <= 1;
{1'd0, 4'd2}: s2wr1 <= 2;
{1'd0, 4'd3}: s2wr1 <= 3;
{1'd0, 4'd4}: s2wr1 <= 4;
{1'd0, 4'd5}: s2wr1 <= 5;
{1'd0, 4'd6}: s2wr1 <= 6;
{1'd0, 4'd7}: s2wr1 <= 7;
{1'd0, 4'd8}: s2wr1 <= 8;
{1'd0, 4'd9}: s2wr1 <= 9;
{1'd0, 4'd10}: s2wr1 <= 10;
{1'd0, 4'd11}: s2wr1 <= 11;
{1'd0, 4'd12}: s2wr1 <= 12;
{1'd0, 4'd13}: s2wr1 <= 13;
{1'd0, 4'd14}: s2wr1 <= 14;
{1'd0, 4'd15}: s2wr1 <= 15;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr1 is "block"
endmodule
// Latency: 8
// Gap: 16
module DirSum_31790(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
reg [3:0] i2;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
always @(posedge clk) begin
if (reset == 1) begin
i2 <= 0;
end
else begin
if (next == 1)
i2 <= 0;
else if (i2 == 15)
i2 <= 0;
else
i2 <= i2 + 1;
end
end
codeBlock31558 codeBlockIsnt33389(.clk(clk), .reset(reset), .next_in(next), .next_out(next_out),
.i2_in(i2),
.X0_in(X0), .Y0(Y0),
.X1_in(X1), .Y1(Y1),
.X2_in(X2), .Y2(Y2),
.X3_in(X3), .Y3(Y3));
endmodule
module D6_31752(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [3:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h4000;
1: out3 <= 16'h3ec5;
2: out3 <= 16'h3b21;
3: out3 <= 16'h3537;
4: out3 <= 16'h2d41;
5: out3 <= 16'h238e;
6: out3 <= 16'h187e;
7: out3 <= 16'hc7c;
8: out3 <= 16'h0;
9: out3 <= 16'hf384;
10: out3 <= 16'he782;
11: out3 <= 16'hdc72;
12: out3 <= 16'hd2bf;
13: out3 <= 16'hcac9;
14: out3 <= 16'hc4df;
15: out3 <= 16'hc13b;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
module D8_31788(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [3:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h0;
1: out3 <= 16'hf384;
2: out3 <= 16'he782;
3: out3 <= 16'hdc72;
4: out3 <= 16'hd2bf;
5: out3 <= 16'hcac9;
6: out3 <= 16'hc4df;
7: out3 <= 16'hc13b;
8: out3 <= 16'hc000;
9: out3 <= 16'hc13b;
10: out3 <= 16'hc4df;
11: out3 <= 16'hcac9;
12: out3 <= 16'hd2bf;
13: out3 <= 16'hdc72;
14: out3 <= 16'he782;
15: out3 <= 16'hf384;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
// Latency: 8
// Gap: 1
module codeBlock31558(clk, reset, next_in, next_out,
i2_in,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [3:0] i2_in;
reg [3:0] i2;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO shiftFIFO_33392(.X(next), .Y(next_out), .clk(clk));
defparam shiftFIFO_33392.depth = 7;
defparam shiftFIFO_33392.width = 1;
wire [15:0] a113; // signed
wire [15:0] a102; // signed
wire [15:0] a116; // signed
wire [15:0] a106; // signed
wire [15:0] a117; // signed
wire [15:0] a118; // signed
reg [15:0] tm227; // signed
reg [15:0] tm231; // signed
reg [15:0] tm243; // signed
reg [15:0] tm250; // signed
reg [15:0] tm228; // signed
reg [15:0] tm232; // signed
reg [15:0] tm244; // signed
reg [15:0] tm251; // signed
wire [15:0] tm19; // signed
wire [15:0] a107; // signed
wire [15:0] tm20; // signed
wire [15:0] a109; // signed
reg [15:0] tm229; // signed
reg [15:0] tm233; // signed
reg [15:0] tm245; // signed
reg [15:0] tm252; // signed
reg [15:0] tm55; // signed
reg [15:0] tm56; // signed
reg [15:0] tm230; // signed
reg [15:0] tm234; // signed
reg [15:0] tm246; // signed
reg [15:0] tm253; // signed
reg [15:0] tm247; // signed
reg [15:0] tm254; // signed
wire [15:0] a108; // signed
wire [15:0] a110; // signed
wire [15:0] a111; // signed
wire [15:0] a112; // signed
reg [15:0] tm248; // signed
reg [15:0] tm255; // signed
wire [15:0] Y0; // signed
wire [15:0] Y1; // signed
wire [15:0] Y2; // signed
wire [15:0] Y3; // signed
reg [15:0] tm249; // signed
reg [15:0] tm256; // signed
assign a113 = X0;
assign a102 = a113;
assign a116 = X1;
assign a106 = a116;
assign a117 = X2;
assign a118 = X3;
assign a107 = tm19;
assign a109 = tm20;
assign Y0 = tm249;
assign Y1 = tm256;
D6_31752 instD6inst0_31752(.addr(i2[3:0]), .out(tm19), .clk(clk));
D8_31788 instD8inst0_31788(.addr(i2[3:0]), .out(tm20), .clk(clk));
multfix m31656(.a(tm55), .b(tm230), .clk(clk), .q_sc(a108), .rst(reset));
defparam m31656.WIDTH = 16;
multfix m31678(.a(tm56), .b(tm234), .clk(clk), .q_sc(a110), .rst(reset));
defparam m31678.WIDTH = 16;
multfix m31695(.a(tm56), .b(tm230), .clk(clk), .q_sc(a111), .rst(reset));
defparam m31695.WIDTH = 16;
multfix m31706(.a(tm55), .b(tm234), .clk(clk), .q_sc(a112), .rst(reset));
defparam m31706.WIDTH = 16;
subfxp sub31684(.a(a108), .b(a110), .clk(clk), .q(Y2)); // 6
defparam sub31684.width = 16;
addfxp add31713(.a(a111), .b(a112), .clk(clk), .q(Y3)); // 6
defparam add31713.width = 16;
always @(posedge clk) begin
if (reset == 1) begin
tm55 <= 0;
tm230 <= 0;
tm56 <= 0;
tm234 <= 0;
tm56 <= 0;
tm230 <= 0;
tm55 <= 0;
tm234 <= 0;
end
else begin
i2 <= i2_in;
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
tm227 <= a117;
tm231 <= a118;
tm243 <= a102;
tm250 <= a106;
tm228 <= tm227;
tm232 <= tm231;
tm244 <= tm243;
tm251 <= tm250;
tm229 <= tm228;
tm233 <= tm232;
tm245 <= tm244;
tm252 <= tm251;
tm55 <= a107;
tm56 <= a109;
tm230 <= tm229;
tm234 <= tm233;
tm246 <= tm245;
tm253 <= tm252;
tm247 <= tm246;
tm254 <= tm253;
tm248 <= tm247;
tm255 <= tm254;
tm249 <= tm248;
tm256 <= tm255;
end
end
endmodule
// Latency: 2
// Gap: 1
module codeBlock31793(clk, reset, next_in, next_out,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO shiftFIFO_33395(.X(next), .Y(next_out), .clk(clk));
defparam shiftFIFO_33395.depth = 1;
defparam shiftFIFO_33395.width = 1;
wire [15:0] a69; // signed
wire [15:0] a70; // signed
wire [15:0] a71; // signed
wire [15:0] a72; // signed
wire [15:0] t45; // signed
wire [15:0] t46; // signed
wire [15:0] t47; // signed
wire [15:0] t48; // signed
wire [15:0] Y0; // signed
wire [15:0] Y1; // signed
wire [15:0] Y2; // signed
wire [15:0] Y3; // signed
assign a69 = X0;
assign a70 = X2;
assign a71 = X1;
assign a72 = X3;
assign Y0 = t45;
assign Y1 = t46;
assign Y2 = t47;
assign Y3 = t48;
addfxp add31805(.a(a69), .b(a70), .clk(clk), .q(t45)); // 0
defparam add31805.width = 16;
addfxp add31820(.a(a71), .b(a72), .clk(clk), .q(t46)); // 0
defparam add31820.width = 16;
subfxp sub31834(.a(a69), .b(a70), .clk(clk), .q(t47)); // 0
defparam sub31834.width = 16;
subfxp sub31848(.a(a71), .b(a72), .clk(clk), .q(t48)); // 0
defparam sub31848.width = 16;
always @(posedge clk) begin
if (reset != 1) begin
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
end
end
endmodule
// Latency: 68
// Gap: 32
module rc31873(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
wire [31:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[31:16];
assign Y1 = s0[15:0];
assign Y2 = s1[31:16];
assign Y3 = s1[15:0];
perm31871 instPerm33396(.x0(t0), .y0(s0),
.x1(t1), .y1(s1),
.clk(clk), .next(next), .next_out(next_out), .reset(reset)
);
endmodule
module swNet31871(itr, clk, ct
, x0, y0
, x1, y1
);
parameter width = 32;
input [4:0] ct;
input clk;
input [0:0] itr;
input [width-1:0] x0;
output [width-1:0] y0;
reg [width-1:0] y0;
input [width-1:0] x1;
output [width-1:0] y1;
reg [width-1:0] y1;
wire [width-1:0] t0_0, t0_1;
reg [width-1:0] t1_0, t1_1;
reg [0:0] control;
always @(posedge clk) begin
case(ct)
5'd0: control <= 1'b1;
5'd1: control <= 1'b1;
5'd2: control <= 1'b1;
5'd3: control <= 1'b1;
5'd4: control <= 1'b1;
5'd5: control <= 1'b1;
5'd6: control <= 1'b1;
5'd7: control <= 1'b1;
5'd8: control <= 1'b1;
5'd9: control <= 1'b1;
5'd10: control <= 1'b1;
5'd11: control <= 1'b1;
5'd12: control <= 1'b1;
5'd13: control <= 1'b1;
5'd14: control <= 1'b1;
5'd15: control <= 1'b1;
5'd16: control <= 1'b0;
5'd17: control <= 1'b0;
5'd18: control <= 1'b0;
5'd19: control <= 1'b0;
5'd20: control <= 1'b0;
5'd21: control <= 1'b0;
5'd22: control <= 1'b0;
5'd23: control <= 1'b0;
5'd24: control <= 1'b0;
5'd25: control <= 1'b0;
5'd26: control <= 1'b0;
5'd27: control <= 1'b0;
5'd28: control <= 1'b0;
5'd29: control <= 1'b0;
5'd30: control <= 1'b0;
5'd31: control <= 1'b0;
endcase
end
// synthesis attribute rom_style of control is "distributed"
reg [0:0] control0;
always @(posedge clk) begin
control0 <= control;
end
assign t0_0 = x0;
assign t0_1 = x1;
always @(posedge clk) begin
t1_0 <= (control0[0] == 0) ? t0_0 : t0_1;
t1_1 <= (control0[0] == 0) ? t0_1 : t0_0;
end
always @(posedge clk) begin
y0 <= t1_0;
y1 <= t1_1;
end
endmodule
// Latency: 68
// Gap: 32
module perm31871(clk, next, reset, next_out,
x0, y0,
x1, y1);
parameter width = 32;
parameter depth = 32;
parameter depthX2 = 64;
parameter addrbits = 5;
parameter addrbitsplusone = 6;
parameter muxbits = 1;
input [width-1:0] x0;
output [width-1:0] y0;
wire [width-1:0] t0;
wire [width-1:0] s0;
input [width-1:0] x1;
output [width-1:0] y1;
wire [width-1:0] t1;
wire [width-1:0] s1;
input next, reset, clk;
output next_out;
reg [addrbits-1:0] s1rdloc, s2rdloc;
reg [addrbits-1:0] s1wr0;
reg [addrbits-1:0] s1rd0, s2wr0, s2rd0;
reg [addrbits-1:0] s1rd1, s2wr1, s2rd1;
reg s1wr_en, state1, state2, state3;
wire next2, next3, next4;
reg inFlip0, outFlip0_z, outFlip1;
wire inFlip1, outFlip0;
wire [0:0] tm21;
assign tm21 = 0;
shiftRegFIFO shiftFIFO_33401(.X(outFlip0), .Y(inFlip1), .clk(clk));
defparam shiftFIFO_33401.depth = 3;
defparam shiftFIFO_33401.width = 1;
shiftRegFIFO shiftFIFO_33402(.X(outFlip0_z), .Y(outFlip0), .clk(clk));
defparam shiftFIFO_33402.depth = 1;
defparam shiftFIFO_33402.width = 1;
// // shiftRegFIFO inFlip1Reg(outFlip0, inFlip1,
// defparam shiftRegFIFO.depth = 2;
// wi shiftRegFIFO.dth = 1;
// // shiftRegFIFO outFlip0Reg(outFlip0_z, outFlip0,
// defparam shiftRegFIFO.depth = 1;
// wi shiftRegFIFO.dth = 1;
memMod_dist s1mem0(x0, t0, {inFlip0, s1wr0}, {outFlip0, s1rd0}, s1wr_en, clk);
defparam s1mem0.depth = 64;
defparam s1mem0.width = 32;
defparam s1mem0.logDepth = 6;
memMod_dist s1mem1(x1, t1, {inFlip0, s1wr0}, {outFlip0, s1rd1}, s1wr_en, clk);
defparam s1mem1.depth = 64;
defparam s1mem1.width = 32;
defparam s1mem1.logDepth = 6;
nextReg nextReg_33413(.X(next), .Y(next2), .reset(reset), .clk(clk));
defparam nextReg_33413.depth = 31;
defparam nextReg_33413.logDepth = 5;
shiftRegFIFO shiftFIFO_33414(.X(next2), .Y(next3), .clk(clk));
defparam shiftFIFO_33414.depth = 4;
defparam shiftFIFO_33414.width = 1;
nextReg nextReg_33417(.X(next3), .Y(next4), .reset(reset), .clk(clk));
defparam nextReg_33417.depth = 32;
defparam nextReg_33417.logDepth = 5;
shiftRegFIFO shiftFIFO_33418(.X(next4), .Y(next_out), .clk(clk));
defparam shiftFIFO_33418.depth = 1;
defparam shiftFIFO_33418.width = 1;
shiftRegFIFO shiftFIFO_33421(.X(tm21), .Y(tm21_d), .clk(clk));
defparam shiftFIFO_33421.depth = 31;
defparam shiftFIFO_33421.width = 1;
shiftRegFIFO shiftFIFO_33424(.X(tm21_d), .Y(tm21_dd), .clk(clk));
defparam shiftFIFO_33424.depth = 3;
defparam shiftFIFO_33424.width = 1;
// // shiftRegFIFO1) n1(next, next2,
// defparam shiftRegFIFO1.depth = dept;
// wi shiftRegFIFO1.dth = 1;,
// // shiftRegFIFO n2(next2, next3,
// defparam shiftRegFIFO.depth = 3;
// wi shiftRegFIFO.dth = 1;
// // shiftRegFIFO n3(next3, next4,
// defparam shiftRegFIFO.depth = depth;
// wi shiftRegFIFO.dth = 1;
// // shiftRegFIFO n4(next4, next_out,
// defparam shiftRegFIFO.depth = 1;
// wi shiftRegFIFO.dth = 1;
wire [addrbits-1:0] muxCycle, writeCycle;
assign muxCycle = s1rdloc;
shiftRegFIFO shiftFIFO_33429(.X(muxCycle), .Y(writeCycle), .clk(clk));
defparam shiftFIFO_33429.depth = 3;
defparam shiftFIFO_33429.width = 5;
wire readInt, s2wr_en;
assign readInt = (state2 == 1);
shiftRegFIFO writeIntReg(readInt, s2wr_en, clk);
defparam writeIntReg.depth = 4;
defparam writeIntReg.width = 1;
memMod_dist s2mem0(s0, y0, {inFlip1, s2wr0}, {outFlip1, s2rdloc}, s2wr_en, clk);
defparam s2mem0.depth = 64;
defparam s2mem0.width = 32;
defparam s2mem0.logDepth = 6;
memMod_dist s2mem1(s1, y1, {inFlip1, s2wr1}, {outFlip1, s2rdloc}, s2wr_en, clk);
defparam s2mem1.depth = 64;
defparam s2mem1.width = 32;
defparam s2mem1.logDepth = 6;
always @(posedge clk) begin
if (reset == 1) begin
state1 <= 0;
inFlip0 <= 0;
end
else if (next == 1) begin
s1wr0 <= 0;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
else begin
case(state1)
0: begin
s1wr0 <= 0;
state1 <= 0;
s1wr_en <= 0;
inFlip0 <= inFlip0;
end
1: begin
s1wr0 <= (s1wr0 == depth-1) ? 0 : s1wr0 + 1;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state2 <= 0;
outFlip0_z <= 0;
end
else if (next2 == 1) begin
s1rdloc <= 0;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
else begin
case(state2)
0: begin
s1rdloc <= 0;
state2 <= 0;
outFlip0_z <= outFlip0_z;
end
1: begin
s1rdloc <= (s1rdloc == depth-1) ? 0 : s1rdloc + 1;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state3 <= 0;
outFlip1 <= 0;
end
else if (next4 == 1) begin
s2rdloc <= 0;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
else begin
case(state3)
0: begin
s2rdloc <= 0;
state3 <= 0;
outFlip1 <= outFlip1;
end
1: begin
s2rdloc <= (s2rdloc == depth-1) ? 0 : s2rdloc + 1;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
endcase
end
end
always @(posedge clk) begin
case({tm21_d, s1rdloc})
{1'd0, 5'd0}: s1rd0 <= 16;
{1'd0, 5'd1}: s1rd0 <= 17;
{1'd0, 5'd2}: s1rd0 <= 18;
{1'd0, 5'd3}: s1rd0 <= 19;
{1'd0, 5'd4}: s1rd0 <= 20;
{1'd0, 5'd5}: s1rd0 <= 21;
{1'd0, 5'd6}: s1rd0 <= 22;
{1'd0, 5'd7}: s1rd0 <= 23;
{1'd0, 5'd8}: s1rd0 <= 24;
{1'd0, 5'd9}: s1rd0 <= 25;
{1'd0, 5'd10}: s1rd0 <= 26;
{1'd0, 5'd11}: s1rd0 <= 27;
{1'd0, 5'd12}: s1rd0 <= 28;
{1'd0, 5'd13}: s1rd0 <= 29;
{1'd0, 5'd14}: s1rd0 <= 30;
{1'd0, 5'd15}: s1rd0 <= 31;
{1'd0, 5'd16}: s1rd0 <= 0;
{1'd0, 5'd17}: s1rd0 <= 1;
{1'd0, 5'd18}: s1rd0 <= 2;
{1'd0, 5'd19}: s1rd0 <= 3;
{1'd0, 5'd20}: s1rd0 <= 4;
{1'd0, 5'd21}: s1rd0 <= 5;
{1'd0, 5'd22}: s1rd0 <= 6;
{1'd0, 5'd23}: s1rd0 <= 7;
{1'd0, 5'd24}: s1rd0 <= 8;
{1'd0, 5'd25}: s1rd0 <= 9;
{1'd0, 5'd26}: s1rd0 <= 10;
{1'd0, 5'd27}: s1rd0 <= 11;
{1'd0, 5'd28}: s1rd0 <= 12;
{1'd0, 5'd29}: s1rd0 <= 13;
{1'd0, 5'd30}: s1rd0 <= 14;
{1'd0, 5'd31}: s1rd0 <= 15;
endcase
end
// synthesis attribute rom_style of s1rd0 is "block"
always @(posedge clk) begin
case({tm21_d, s1rdloc})
{1'd0, 5'd0}: s1rd1 <= 0;
{1'd0, 5'd1}: s1rd1 <= 1;
{1'd0, 5'd2}: s1rd1 <= 2;
{1'd0, 5'd3}: s1rd1 <= 3;
{1'd0, 5'd4}: s1rd1 <= 4;
{1'd0, 5'd5}: s1rd1 <= 5;
{1'd0, 5'd6}: s1rd1 <= 6;
{1'd0, 5'd7}: s1rd1 <= 7;
{1'd0, 5'd8}: s1rd1 <= 8;
{1'd0, 5'd9}: s1rd1 <= 9;
{1'd0, 5'd10}: s1rd1 <= 10;
{1'd0, 5'd11}: s1rd1 <= 11;
{1'd0, 5'd12}: s1rd1 <= 12;
{1'd0, 5'd13}: s1rd1 <= 13;
{1'd0, 5'd14}: s1rd1 <= 14;
{1'd0, 5'd15}: s1rd1 <= 15;
{1'd0, 5'd16}: s1rd1 <= 16;
{1'd0, 5'd17}: s1rd1 <= 17;
{1'd0, 5'd18}: s1rd1 <= 18;
{1'd0, 5'd19}: s1rd1 <= 19;
{1'd0, 5'd20}: s1rd1 <= 20;
{1'd0, 5'd21}: s1rd1 <= 21;
{1'd0, 5'd22}: s1rd1 <= 22;
{1'd0, 5'd23}: s1rd1 <= 23;
{1'd0, 5'd24}: s1rd1 <= 24;
{1'd0, 5'd25}: s1rd1 <= 25;
{1'd0, 5'd26}: s1rd1 <= 26;
{1'd0, 5'd27}: s1rd1 <= 27;
{1'd0, 5'd28}: s1rd1 <= 28;
{1'd0, 5'd29}: s1rd1 <= 29;
{1'd0, 5'd30}: s1rd1 <= 30;
{1'd0, 5'd31}: s1rd1 <= 31;
endcase
end
// synthesis attribute rom_style of s1rd1 is "block"
swNet31871 sw(tm21_d, clk, muxCycle, t0, s0, t1, s1);
always @(posedge clk) begin
case({tm21_dd, writeCycle})
{1'd0, 5'd0}: s2wr0 <= 16;
{1'd0, 5'd1}: s2wr0 <= 17;
{1'd0, 5'd2}: s2wr0 <= 18;
{1'd0, 5'd3}: s2wr0 <= 19;
{1'd0, 5'd4}: s2wr0 <= 20;
{1'd0, 5'd5}: s2wr0 <= 21;
{1'd0, 5'd6}: s2wr0 <= 22;
{1'd0, 5'd7}: s2wr0 <= 23;
{1'd0, 5'd8}: s2wr0 <= 24;
{1'd0, 5'd9}: s2wr0 <= 25;
{1'd0, 5'd10}: s2wr0 <= 26;
{1'd0, 5'd11}: s2wr0 <= 27;
{1'd0, 5'd12}: s2wr0 <= 28;
{1'd0, 5'd13}: s2wr0 <= 29;
{1'd0, 5'd14}: s2wr0 <= 30;
{1'd0, 5'd15}: s2wr0 <= 31;
{1'd0, 5'd16}: s2wr0 <= 0;
{1'd0, 5'd17}: s2wr0 <= 1;
{1'd0, 5'd18}: s2wr0 <= 2;
{1'd0, 5'd19}: s2wr0 <= 3;
{1'd0, 5'd20}: s2wr0 <= 4;
{1'd0, 5'd21}: s2wr0 <= 5;
{1'd0, 5'd22}: s2wr0 <= 6;
{1'd0, 5'd23}: s2wr0 <= 7;
{1'd0, 5'd24}: s2wr0 <= 8;
{1'd0, 5'd25}: s2wr0 <= 9;
{1'd0, 5'd26}: s2wr0 <= 10;
{1'd0, 5'd27}: s2wr0 <= 11;
{1'd0, 5'd28}: s2wr0 <= 12;
{1'd0, 5'd29}: s2wr0 <= 13;
{1'd0, 5'd30}: s2wr0 <= 14;
{1'd0, 5'd31}: s2wr0 <= 15;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr0 is "block"
always @(posedge clk) begin
case({tm21_dd, writeCycle})
{1'd0, 5'd0}: s2wr1 <= 0;
{1'd0, 5'd1}: s2wr1 <= 1;
{1'd0, 5'd2}: s2wr1 <= 2;
{1'd0, 5'd3}: s2wr1 <= 3;
{1'd0, 5'd4}: s2wr1 <= 4;
{1'd0, 5'd5}: s2wr1 <= 5;
{1'd0, 5'd6}: s2wr1 <= 6;
{1'd0, 5'd7}: s2wr1 <= 7;
{1'd0, 5'd8}: s2wr1 <= 8;
{1'd0, 5'd9}: s2wr1 <= 9;
{1'd0, 5'd10}: s2wr1 <= 10;
{1'd0, 5'd11}: s2wr1 <= 11;
{1'd0, 5'd12}: s2wr1 <= 12;
{1'd0, 5'd13}: s2wr1 <= 13;
{1'd0, 5'd14}: s2wr1 <= 14;
{1'd0, 5'd15}: s2wr1 <= 15;
{1'd0, 5'd16}: s2wr1 <= 16;
{1'd0, 5'd17}: s2wr1 <= 17;
{1'd0, 5'd18}: s2wr1 <= 18;
{1'd0, 5'd19}: s2wr1 <= 19;
{1'd0, 5'd20}: s2wr1 <= 20;
{1'd0, 5'd21}: s2wr1 <= 21;
{1'd0, 5'd22}: s2wr1 <= 22;
{1'd0, 5'd23}: s2wr1 <= 23;
{1'd0, 5'd24}: s2wr1 <= 24;
{1'd0, 5'd25}: s2wr1 <= 25;
{1'd0, 5'd26}: s2wr1 <= 26;
{1'd0, 5'd27}: s2wr1 <= 27;
{1'd0, 5'd28}: s2wr1 <= 28;
{1'd0, 5'd29}: s2wr1 <= 29;
{1'd0, 5'd30}: s2wr1 <= 30;
{1'd0, 5'd31}: s2wr1 <= 31;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr1 is "block"
endmodule
// Latency: 8
// Gap: 32
module DirSum_32171(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
reg [4:0] i1;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
always @(posedge clk) begin
if (reset == 1) begin
i1 <= 0;
end
else begin
if (next == 1)
i1 <= 0;
else if (i1 == 31)
i1 <= 0;
else
i1 <= i1 + 1;
end
end
codeBlock31875 codeBlockIsnt33434(.clk(clk), .reset(reset), .next_in(next), .next_out(next_out),
.i1_in(i1),
.X0_in(X0), .Y0(Y0),
.X1_in(X1), .Y1(Y1),
.X2_in(X2), .Y2(Y2),
.X3_in(X3), .Y3(Y3));
endmodule
module D2_32101(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [4:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h4000;
1: out3 <= 16'h3fb1;
2: out3 <= 16'h3ec5;
3: out3 <= 16'h3d3f;
4: out3 <= 16'h3b21;
5: out3 <= 16'h3871;
6: out3 <= 16'h3537;
7: out3 <= 16'h3179;
8: out3 <= 16'h2d41;
9: out3 <= 16'h289a;
10: out3 <= 16'h238e;
11: out3 <= 16'h1e2b;
12: out3 <= 16'h187e;
13: out3 <= 16'h1294;
14: out3 <= 16'hc7c;
15: out3 <= 16'h646;
16: out3 <= 16'h0;
17: out3 <= 16'hf9ba;
18: out3 <= 16'hf384;
19: out3 <= 16'hed6c;
20: out3 <= 16'he782;
21: out3 <= 16'he1d5;
22: out3 <= 16'hdc72;
23: out3 <= 16'hd766;
24: out3 <= 16'hd2bf;
25: out3 <= 16'hce87;
26: out3 <= 16'hcac9;
27: out3 <= 16'hc78f;
28: out3 <= 16'hc4df;
29: out3 <= 16'hc2c1;
30: out3 <= 16'hc13b;
31: out3 <= 16'hc04f;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
module D4_32169(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [4:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h0;
1: out3 <= 16'hf9ba;
2: out3 <= 16'hf384;
3: out3 <= 16'hed6c;
4: out3 <= 16'he782;
5: out3 <= 16'he1d5;
6: out3 <= 16'hdc72;
7: out3 <= 16'hd766;
8: out3 <= 16'hd2bf;
9: out3 <= 16'hce87;
10: out3 <= 16'hcac9;
11: out3 <= 16'hc78f;
12: out3 <= 16'hc4df;
13: out3 <= 16'hc2c1;
14: out3 <= 16'hc13b;
15: out3 <= 16'hc04f;
16: out3 <= 16'hc000;
17: out3 <= 16'hc04f;
18: out3 <= 16'hc13b;
19: out3 <= 16'hc2c1;
20: out3 <= 16'hc4df;
21: out3 <= 16'hc78f;
22: out3 <= 16'hcac9;
23: out3 <= 16'hce87;
24: out3 <= 16'hd2bf;
25: out3 <= 16'hd766;
26: out3 <= 16'hdc72;
27: out3 <= 16'he1d5;
28: out3 <= 16'he782;
29: out3 <= 16'hed6c;
30: out3 <= 16'hf384;
31: out3 <= 16'hf9ba;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
// Latency: 8
// Gap: 1
module codeBlock31875(clk, reset, next_in, next_out,
i1_in,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [4:0] i1_in;
reg [4:0] i1;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO shiftFIFO_33437(.X(next), .Y(next_out), .clk(clk));
defparam shiftFIFO_33437.depth = 7;
defparam shiftFIFO_33437.width = 1;
wire [15:0] a53; // signed
wire [15:0] a42; // signed
wire [15:0] a56; // signed
wire [15:0] a46; // signed
wire [15:0] a57; // signed
wire [15:0] a58; // signed
reg [15:0] tm257; // signed
reg [15:0] tm261; // signed
reg [15:0] tm273; // signed
reg [15:0] tm280; // signed
reg [15:0] tm258; // signed
reg [15:0] tm262; // signed
reg [15:0] tm274; // signed
reg [15:0] tm281; // signed
wire [15:0] tm24; // signed
wire [15:0] a47; // signed
wire [15:0] tm25; // signed
wire [15:0] a49; // signed
reg [15:0] tm259; // signed
reg [15:0] tm263; // signed
reg [15:0] tm275; // signed
reg [15:0] tm282; // signed
reg [15:0] tm63; // signed
reg [15:0] tm64; // signed
reg [15:0] tm260; // signed
reg [15:0] tm264; // signed
reg [15:0] tm276; // signed
reg [15:0] tm283; // signed
reg [15:0] tm277; // signed
reg [15:0] tm284; // signed
wire [15:0] a48; // signed
wire [15:0] a50; // signed
wire [15:0] a51; // signed
wire [15:0] a52; // signed
reg [15:0] tm278; // signed
reg [15:0] tm285; // signed
wire [15:0] Y0; // signed
wire [15:0] Y1; // signed
wire [15:0] Y2; // signed
wire [15:0] Y3; // signed
reg [15:0] tm279; // signed
reg [15:0] tm286; // signed
assign a53 = X0;
assign a42 = a53;
assign a56 = X1;
assign a46 = a56;
assign a57 = X2;
assign a58 = X3;
assign a47 = tm24;
assign a49 = tm25;
assign Y0 = tm279;
assign Y1 = tm286;
D2_32101 instD2inst0_32101(.addr(i1[4:0]), .out(tm24), .clk(clk));
D4_32169 instD4inst0_32169(.addr(i1[4:0]), .out(tm25), .clk(clk));
multfix m31973(.a(tm63), .b(tm260), .clk(clk), .q_sc(a48), .rst(reset));
defparam m31973.WIDTH = 16;
multfix m31995(.a(tm64), .b(tm264), .clk(clk), .q_sc(a50), .rst(reset));
defparam m31995.WIDTH = 16;
multfix m32012(.a(tm64), .b(tm260), .clk(clk), .q_sc(a51), .rst(reset));
defparam m32012.WIDTH = 16;
multfix m32023(.a(tm63), .b(tm264), .clk(clk), .q_sc(a52), .rst(reset));
defparam m32023.WIDTH = 16;
subfxp sub32001(.a(a48), .b(a50), .clk(clk), .q(Y2)); // 6
defparam sub32001.width = 16;
addfxp add32030(.a(a51), .b(a52), .clk(clk), .q(Y3)); // 6
defparam add32030.width = 16;
always @(posedge clk) begin
if (reset == 1) begin
tm63 <= 0;
tm260 <= 0;
tm64 <= 0;
tm264 <= 0;
tm64 <= 0;
tm260 <= 0;
tm63 <= 0;
tm264 <= 0;
end
else begin
i1 <= i1_in;
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
tm257 <= a57;
tm261 <= a58;
tm273 <= a42;
tm280 <= a46;
tm258 <= tm257;
tm262 <= tm261;
tm274 <= tm273;
tm281 <= tm280;
tm259 <= tm258;
tm263 <= tm262;
tm275 <= tm274;
tm282 <= tm281;
tm63 <= a47;
tm64 <= a49;
tm260 <= tm259;
tm264 <= tm263;
tm276 <= tm275;
tm283 <= tm282;
tm277 <= tm276;
tm284 <= tm283;
tm278 <= tm277;
tm285 <= tm284;
tm279 <= tm278;
tm286 <= tm285;
end
end
endmodule
// Latency: 2
// Gap: 1
module codeBlock32174(clk, reset, next_in, next_out,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO shiftFIFO_33440(.X(next), .Y(next_out), .clk(clk));
defparam shiftFIFO_33440.depth = 1;
defparam shiftFIFO_33440.width = 1;
wire [15:0] a9; // signed
wire [15:0] a10; // signed
wire [15:0] a11; // signed
wire [15:0] a12; // signed
wire [15:0] t21; // signed
wire [15:0] t22; // signed
wire [15:0] t23; // signed
wire [15:0] t24; // signed
wire [15:0] Y0; // signed
wire [15:0] Y1; // signed
wire [15:0] Y2; // signed
wire [15:0] Y3; // signed
assign a9 = X0;
assign a10 = X2;
assign a11 = X1;
assign a12 = X3;
assign Y0 = t21;
assign Y1 = t22;
assign Y2 = t23;
assign Y3 = t24;
addfxp add32186(.a(a9), .b(a10), .clk(clk), .q(t21)); // 0
defparam add32186.width = 16;
addfxp add32201(.a(a11), .b(a12), .clk(clk), .q(t22)); // 0
defparam add32201.width = 16;
subfxp sub32215(.a(a9), .b(a10), .clk(clk), .q(t23)); // 0
defparam sub32215.width = 16;
subfxp sub32229(.a(a11), .b(a12), .clk(clk), .q(t24)); // 0
defparam sub32229.width = 16;
always @(posedge clk) begin
if (reset != 1) begin
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
end
end
endmodule
// Latency: 68
// Gap: 32
module rc32254(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
wire [31:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[31:16];
assign Y1 = s0[15:0];
assign Y2 = s1[31:16];
assign Y3 = s1[15:0];
perm32252 instPerm33441(.x0(t0), .y0(s0),
.x1(t1), .y1(s1),
.clk(clk), .next(next), .next_out(next_out), .reset(reset)
);
endmodule
module swNet32252(itr, clk, ct
, x0, y0
, x1, y1
);
parameter width = 32;
input [4:0] ct;
input clk;
input [0:0] itr;
input [width-1:0] x0;
output [width-1:0] y0;
reg [width-1:0] y0;
input [width-1:0] x1;
output [width-1:0] y1;
reg [width-1:0] y1;
wire [width-1:0] t0_0, t0_1;
reg [width-1:0] t1_0, t1_1;
reg [0:0] control;
always @(posedge clk) begin
case(ct)
5'd0: control <= 1'b1;
5'd1: control <= 1'b1;
5'd2: control <= 1'b1;
5'd3: control <= 1'b1;
5'd4: control <= 1'b1;
5'd5: control <= 1'b1;
5'd6: control <= 1'b1;
5'd7: control <= 1'b1;
5'd8: control <= 1'b1;
5'd9: control <= 1'b1;
5'd10: control <= 1'b1;
5'd11: control <= 1'b1;
5'd12: control <= 1'b1;
5'd13: control <= 1'b1;
5'd14: control <= 1'b1;
5'd15: control <= 1'b1;
5'd16: control <= 1'b0;
5'd17: control <= 1'b0;
5'd18: control <= 1'b0;
5'd19: control <= 1'b0;
5'd20: control <= 1'b0;
5'd21: control <= 1'b0;
5'd22: control <= 1'b0;
5'd23: control <= 1'b0;
5'd24: control <= 1'b0;
5'd25: control <= 1'b0;
5'd26: control <= 1'b0;
5'd27: control <= 1'b0;
5'd28: control <= 1'b0;
5'd29: control <= 1'b0;
5'd30: control <= 1'b0;
5'd31: control <= 1'b0;
endcase
end
// synthesis attribute rom_style of control is "distributed"
reg [0:0] control0;
always @(posedge clk) begin
control0 <= control;
end
assign t0_0 = x0;
assign t0_1 = x1;
always @(posedge clk) begin
t1_0 <= (control0[0] == 0) ? t0_0 : t0_1;
t1_1 <= (control0[0] == 0) ? t0_1 : t0_0;
end
always @(posedge clk) begin
y0 <= t1_0;
y1 <= t1_1;
end
endmodule
// Latency: 68
// Gap: 32
module perm32252(clk, next, reset, next_out,
x0, y0,
x1, y1);
parameter width = 32;
parameter depth = 32;
parameter depthX2 = 64;
parameter addrbits = 5;
parameter addrbitsplusone = 6;
parameter muxbits = 1;
input [width-1:0] x0;
output [width-1:0] y0;
wire [width-1:0] t0;
wire [width-1:0] s0;
input [width-1:0] x1;
output [width-1:0] y1;
wire [width-1:0] t1;
wire [width-1:0] s1;
input next, reset, clk;
output next_out;
reg [addrbits-1:0] s1rdloc, s2rdloc;
reg [addrbits-1:0] s1wr0;
reg [addrbits-1:0] s1rd0, s2wr0, s2rd0;
reg [addrbits-1:0] s1rd1, s2wr1, s2rd1;
reg s1wr_en, state1, state2, state3;
wire next2, next3, next4;
reg inFlip0, outFlip0_z, outFlip1;
wire inFlip1, outFlip0;
wire [0:0] tm26;
assign tm26 = 0;
shiftRegFIFO shiftFIFO_33446(.X(outFlip0), .Y(inFlip1), .clk(clk));
defparam shiftFIFO_33446.depth = 3;
defparam shiftFIFO_33446.width = 1;
shiftRegFIFO shiftFIFO_33447(.X(outFlip0_z), .Y(outFlip0), .clk(clk));
defparam shiftFIFO_33447.depth = 1;
defparam shiftFIFO_33447.width = 1;
// // shiftRegFIFO inFlip1Reg(outFlip0, inFlip1,
// defparam shiftRegFIFO.depth = 2;
// wi shiftRegFIFO.dth = 1;
// // shiftRegFIFO outFlip0Reg(outFlip0_z, outFlip0,
// defparam shiftRegFIFO.depth = 1;
// wi shiftRegFIFO.dth = 1;
memMod_dist s1mem0(x0, t0, {inFlip0, s1wr0}, {outFlip0, s1rd0}, s1wr_en, clk);
defparam s1mem0.depth = 64;
defparam s1mem0.width = 32;
defparam s1mem0.logDepth = 6;
memMod_dist s1mem1(x1, t1, {inFlip0, s1wr0}, {outFlip0, s1rd1}, s1wr_en, clk);
defparam s1mem1.depth = 64;
defparam s1mem1.width = 32;
defparam s1mem1.logDepth = 6;
nextReg nextReg_33458(.X(next), .Y(next2), .reset(reset), .clk(clk));
defparam nextReg_33458.depth = 31;
defparam nextReg_33458.logDepth = 5;
shiftRegFIFO shiftFIFO_33459(.X(next2), .Y(next3), .clk(clk));
defparam shiftFIFO_33459.depth = 4;
defparam shiftFIFO_33459.width = 1;
nextReg nextReg_33462(.X(next3), .Y(next4), .reset(reset), .clk(clk));
defparam nextReg_33462.depth = 32;
defparam nextReg_33462.logDepth = 5;
shiftRegFIFO shiftFIFO_33463(.X(next4), .Y(next_out), .clk(clk));
defparam shiftFIFO_33463.depth = 1;
defparam shiftFIFO_33463.width = 1;
shiftRegFIFO shiftFIFO_33466(.X(tm26), .Y(tm26_d), .clk(clk));
defparam shiftFIFO_33466.depth = 31;
defparam shiftFIFO_33466.width = 1;
shiftRegFIFO shiftFIFO_33469(.X(tm26_d), .Y(tm26_dd), .clk(clk));
defparam shiftFIFO_33469.depth = 3;
defparam shiftFIFO_33469.width = 1;
// // shiftRegFIFO1) n1(next, next2,
// defparam shiftRegFIFO1.depth = dept;
// wi shiftRegFIFO1.dth = 1;,
// // shiftRegFIFO n2(next2, next3,
// defparam shiftRegFIFO.depth = 3;
// wi shiftRegFIFO.dth = 1;
// // shiftRegFIFO n3(next3, next4,
// defparam shiftRegFIFO.depth = depth;
// wi shiftRegFIFO.dth = 1;
// // shiftRegFIFO n4(next4, next_out,
// defparam shiftRegFIFO.depth = 1;
// wi shiftRegFIFO.dth = 1;
wire [addrbits-1:0] muxCycle, writeCycle;
assign muxCycle = s1rdloc;
shiftRegFIFO shiftFIFO_33474(.X(muxCycle), .Y(writeCycle), .clk(clk));
defparam shiftFIFO_33474.depth = 3;
defparam shiftFIFO_33474.width = 5;
wire readInt, s2wr_en;
assign readInt = (state2 == 1);
shiftRegFIFO writeIntReg(readInt, s2wr_en, clk);
defparam writeIntReg.depth = 4;
defparam writeIntReg.width = 1;
memMod_dist s2mem0(s0, y0, {inFlip1, s2wr0}, {outFlip1, s2rdloc}, s2wr_en, clk);
defparam s2mem0.depth = 64;
defparam s2mem0.width = 32;
defparam s2mem0.logDepth = 6;
memMod_dist s2mem1(s1, y1, {inFlip1, s2wr1}, {outFlip1, s2rdloc}, s2wr_en, clk);
defparam s2mem1.depth = 64;
defparam s2mem1.width = 32;
defparam s2mem1.logDepth = 6;
always @(posedge clk) begin
if (reset == 1) begin
state1 <= 0;
inFlip0 <= 0;
end
else if (next == 1) begin
s1wr0 <= 0;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
else begin
case(state1)
0: begin
s1wr0 <= 0;
state1 <= 0;
s1wr_en <= 0;
inFlip0 <= inFlip0;
end
1: begin
s1wr0 <= (s1wr0 == depth-1) ? 0 : s1wr0 + 1;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state2 <= 0;
outFlip0_z <= 0;
end
else if (next2 == 1) begin
s1rdloc <= 0;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
else begin
case(state2)
0: begin
s1rdloc <= 0;
state2 <= 0;
outFlip0_z <= outFlip0_z;
end
1: begin
s1rdloc <= (s1rdloc == depth-1) ? 0 : s1rdloc + 1;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state3 <= 0;
outFlip1 <= 0;
end
else if (next4 == 1) begin
s2rdloc <= 0;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
else begin
case(state3)
0: begin
s2rdloc <= 0;
state3 <= 0;
outFlip1 <= outFlip1;
end
1: begin
s2rdloc <= (s2rdloc == depth-1) ? 0 : s2rdloc + 1;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
endcase
end
end
always @(posedge clk) begin
case({tm26_d, s1rdloc})
{1'd0, 5'd0}: s1rd0 <= 1;
{1'd0, 5'd1}: s1rd0 <= 3;
{1'd0, 5'd2}: s1rd0 <= 5;
{1'd0, 5'd3}: s1rd0 <= 7;
{1'd0, 5'd4}: s1rd0 <= 9;
{1'd0, 5'd5}: s1rd0 <= 11;
{1'd0, 5'd6}: s1rd0 <= 13;
{1'd0, 5'd7}: s1rd0 <= 15;
{1'd0, 5'd8}: s1rd0 <= 17;
{1'd0, 5'd9}: s1rd0 <= 19;
{1'd0, 5'd10}: s1rd0 <= 21;
{1'd0, 5'd11}: s1rd0 <= 23;
{1'd0, 5'd12}: s1rd0 <= 25;
{1'd0, 5'd13}: s1rd0 <= 27;
{1'd0, 5'd14}: s1rd0 <= 29;
{1'd0, 5'd15}: s1rd0 <= 31;
{1'd0, 5'd16}: s1rd0 <= 0;
{1'd0, 5'd17}: s1rd0 <= 2;
{1'd0, 5'd18}: s1rd0 <= 4;
{1'd0, 5'd19}: s1rd0 <= 6;
{1'd0, 5'd20}: s1rd0 <= 8;
{1'd0, 5'd21}: s1rd0 <= 10;
{1'd0, 5'd22}: s1rd0 <= 12;
{1'd0, 5'd23}: s1rd0 <= 14;
{1'd0, 5'd24}: s1rd0 <= 16;
{1'd0, 5'd25}: s1rd0 <= 18;
{1'd0, 5'd26}: s1rd0 <= 20;
{1'd0, 5'd27}: s1rd0 <= 22;
{1'd0, 5'd28}: s1rd0 <= 24;
{1'd0, 5'd29}: s1rd0 <= 26;
{1'd0, 5'd30}: s1rd0 <= 28;
{1'd0, 5'd31}: s1rd0 <= 30;
endcase
end
// synthesis attribute rom_style of s1rd0 is "block"
always @(posedge clk) begin
case({tm26_d, s1rdloc})
{1'd0, 5'd0}: s1rd1 <= 0;
{1'd0, 5'd1}: s1rd1 <= 2;
{1'd0, 5'd2}: s1rd1 <= 4;
{1'd0, 5'd3}: s1rd1 <= 6;
{1'd0, 5'd4}: s1rd1 <= 8;
{1'd0, 5'd5}: s1rd1 <= 10;
{1'd0, 5'd6}: s1rd1 <= 12;
{1'd0, 5'd7}: s1rd1 <= 14;
{1'd0, 5'd8}: s1rd1 <= 16;
{1'd0, 5'd9}: s1rd1 <= 18;
{1'd0, 5'd10}: s1rd1 <= 20;
{1'd0, 5'd11}: s1rd1 <= 22;
{1'd0, 5'd12}: s1rd1 <= 24;
{1'd0, 5'd13}: s1rd1 <= 26;
{1'd0, 5'd14}: s1rd1 <= 28;
{1'd0, 5'd15}: s1rd1 <= 30;
{1'd0, 5'd16}: s1rd1 <= 1;
{1'd0, 5'd17}: s1rd1 <= 3;
{1'd0, 5'd18}: s1rd1 <= 5;
{1'd0, 5'd19}: s1rd1 <= 7;
{1'd0, 5'd20}: s1rd1 <= 9;
{1'd0, 5'd21}: s1rd1 <= 11;
{1'd0, 5'd22}: s1rd1 <= 13;
{1'd0, 5'd23}: s1rd1 <= 15;
{1'd0, 5'd24}: s1rd1 <= 17;
{1'd0, 5'd25}: s1rd1 <= 19;
{1'd0, 5'd26}: s1rd1 <= 21;
{1'd0, 5'd27}: s1rd1 <= 23;
{1'd0, 5'd28}: s1rd1 <= 25;
{1'd0, 5'd29}: s1rd1 <= 27;
{1'd0, 5'd30}: s1rd1 <= 29;
{1'd0, 5'd31}: s1rd1 <= 31;
endcase
end
// synthesis attribute rom_style of s1rd1 is "block"
swNet32252 sw(tm26_d, clk, muxCycle, t0, s0, t1, s1);
always @(posedge clk) begin
case({tm26_dd, writeCycle})
{1'd0, 5'd0}: s2wr0 <= 16;
{1'd0, 5'd1}: s2wr0 <= 17;
{1'd0, 5'd2}: s2wr0 <= 18;
{1'd0, 5'd3}: s2wr0 <= 19;
{1'd0, 5'd4}: s2wr0 <= 20;
{1'd0, 5'd5}: s2wr0 <= 21;
{1'd0, 5'd6}: s2wr0 <= 22;
{1'd0, 5'd7}: s2wr0 <= 23;
{1'd0, 5'd8}: s2wr0 <= 24;
{1'd0, 5'd9}: s2wr0 <= 25;
{1'd0, 5'd10}: s2wr0 <= 26;
{1'd0, 5'd11}: s2wr0 <= 27;
{1'd0, 5'd12}: s2wr0 <= 28;
{1'd0, 5'd13}: s2wr0 <= 29;
{1'd0, 5'd14}: s2wr0 <= 30;
{1'd0, 5'd15}: s2wr0 <= 31;
{1'd0, 5'd16}: s2wr0 <= 0;
{1'd0, 5'd17}: s2wr0 <= 1;
{1'd0, 5'd18}: s2wr0 <= 2;
{1'd0, 5'd19}: s2wr0 <= 3;
{1'd0, 5'd20}: s2wr0 <= 4;
{1'd0, 5'd21}: s2wr0 <= 5;
{1'd0, 5'd22}: s2wr0 <= 6;
{1'd0, 5'd23}: s2wr0 <= 7;
{1'd0, 5'd24}: s2wr0 <= 8;
{1'd0, 5'd25}: s2wr0 <= 9;
{1'd0, 5'd26}: s2wr0 <= 10;
{1'd0, 5'd27}: s2wr0 <= 11;
{1'd0, 5'd28}: s2wr0 <= 12;
{1'd0, 5'd29}: s2wr0 <= 13;
{1'd0, 5'd30}: s2wr0 <= 14;
{1'd0, 5'd31}: s2wr0 <= 15;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr0 is "block"
always @(posedge clk) begin
case({tm26_dd, writeCycle})
{1'd0, 5'd0}: s2wr1 <= 0;
{1'd0, 5'd1}: s2wr1 <= 1;
{1'd0, 5'd2}: s2wr1 <= 2;
{1'd0, 5'd3}: s2wr1 <= 3;
{1'd0, 5'd4}: s2wr1 <= 4;
{1'd0, 5'd5}: s2wr1 <= 5;
{1'd0, 5'd6}: s2wr1 <= 6;
{1'd0, 5'd7}: s2wr1 <= 7;
{1'd0, 5'd8}: s2wr1 <= 8;
{1'd0, 5'd9}: s2wr1 <= 9;
{1'd0, 5'd10}: s2wr1 <= 10;
{1'd0, 5'd11}: s2wr1 <= 11;
{1'd0, 5'd12}: s2wr1 <= 12;
{1'd0, 5'd13}: s2wr1 <= 13;
{1'd0, 5'd14}: s2wr1 <= 14;
{1'd0, 5'd15}: s2wr1 <= 15;
{1'd0, 5'd16}: s2wr1 <= 16;
{1'd0, 5'd17}: s2wr1 <= 17;
{1'd0, 5'd18}: s2wr1 <= 18;
{1'd0, 5'd19}: s2wr1 <= 19;
{1'd0, 5'd20}: s2wr1 <= 20;
{1'd0, 5'd21}: s2wr1 <= 21;
{1'd0, 5'd22}: s2wr1 <= 22;
{1'd0, 5'd23}: s2wr1 <= 23;
{1'd0, 5'd24}: s2wr1 <= 24;
{1'd0, 5'd25}: s2wr1 <= 25;
{1'd0, 5'd26}: s2wr1 <= 26;
{1'd0, 5'd27}: s2wr1 <= 27;
{1'd0, 5'd28}: s2wr1 <= 28;
{1'd0, 5'd29}: s2wr1 <= 29;
{1'd0, 5'd30}: s2wr1 <= 30;
{1'd0, 5'd31}: s2wr1 <= 31;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr1 is "block"
endmodule
module multfix(clk, rst, a, b, q_sc, q_unsc);
parameter WIDTH=35;
input [WIDTH-1:0] a,b; // signed
output [WIDTH-1:0] q_sc;
output [WIDTH-1:0] q_unsc;
input clk, rst;
reg [2*WIDTH-1:0] q_0; // signed
reg [2*WIDTH-1:0] q_1; // signed
wire [2*WIDTH-1:0] res; // signed
assign res = q_1;
assign q_unsc = res[WIDTH-1:0];
assign q_sc = {res[2*WIDTH-1], res[2*WIDTH-4:WIDTH-2]};
always @(posedge clk) begin
q_0 <= a * b;
q_1 <= q_0;
end
endmodule
module addfxp(a, b, q, clk);
parameter width = 16;
input [width-1:0] a, b; // signed
input clk;
output [width-1:0] q; // signed
reg [width-1:0] res; // signed
assign q = res[0];
integer i;
always @(posedge clk) begin
res[0] <= a+b;
end
endmodule
module subfxp(a, b, q, clk);
parameter width = 16;
input [width-1:0] a, b; // signed
input clk;
output [width-1:0] q; // signed
reg [width-1:0] res; // signed
assign q = res;
always @(posedge clk) begin
res <= a-b;
end
endmodule
|
module parallella_base(/*AUTOARG*/
// Outputs
s_axi_wready, s_axi_rvalid, s_axi_rresp, s_axi_rlast, s_axi_rid,
s_axi_rdata, s_axi_bvalid, s_axi_bresp, s_axi_bid, s_axi_awready,
s_axi_arready, m_axi_wvalid, m_axi_wstrb, m_axi_wlast, m_axi_wid,
m_axi_wdata, m_axi_rready, m_axi_bready, m_axi_awvalid,
m_axi_awsize, m_axi_awqos, m_axi_awprot, m_axi_awlock, m_axi_awlen,
m_axi_awid, m_axi_awcache, m_axi_awburst, m_axi_awaddr,
m_axi_arvalid, m_axi_arsize, m_axi_arqos, m_axi_arprot,
m_axi_arlock, m_axi_arlen, m_axi_arid, m_axi_arcache,
m_axi_arburst, m_axi_araddr, cclk_n, cclk_p, chip_nreset, chipid,
elink_active, mailbox_irq, i2c_scl_i, i2c_sda_i, ps_gpio_i,
txo_data_n, txo_data_p, txo_frame_n, txo_frame_p, txo_lclk_n,
txo_lclk_p, rxo_rd_wait_n, rxo_rd_wait_p, rxo_wr_wait_n,
rxo_wr_wait_p, constant_zero, constant_one,
// Inouts
i2c_scl, i2c_sda, gpio_n, gpio_p,
// Inputs
s_axi_wvalid, s_axi_wstrb, s_axi_wlast, s_axi_wid, s_axi_wdata,
s_axi_rready, s_axi_bready, s_axi_awvalid, s_axi_awsize,
s_axi_awqos, s_axi_awprot, s_axi_awlock, s_axi_awlen, s_axi_awid,
s_axi_awcache, s_axi_awburst, s_axi_awaddr, s_axi_arvalid,
s_axi_arsize, s_axi_arqos, s_axi_arprot, s_axi_arlock, s_axi_arlen,
s_axi_arid, s_axi_aresetn, s_axi_arcache, s_axi_arburst,
s_axi_araddr, m_axi_wready, m_axi_rvalid, m_axi_rresp, m_axi_rlast,
m_axi_rid, m_axi_rdata, m_axi_bvalid, m_axi_bresp, m_axi_bid,
m_axi_awready, m_axi_arready, m_axi_aresetn, sys_clk, sys_nreset,
i2c_scl_o, i2c_scl_t, i2c_sda_o, i2c_sda_t, ps_gpio_o, ps_gpio_t,
txi_rd_wait_n, txi_rd_wait_p, txi_wr_wait_n, txi_wr_wait_p,
rxi_data_n, rxi_data_p, rxi_frame_n, rxi_frame_p, rxi_lclk_n,
rxi_lclk_p
);
parameter AW = 32;
parameter DW = 32;
parameter PW = 104; //packet width
parameter ID = 12'h810;
parameter S_IDW = 12; //ID width for S_AXI
parameter M_IDW = 6; //ID width for M_AXI
parameter IOSTD_ELINK = "LVDS_25";
parameter NGPIO = 24;
parameter NPS = 64; //Number of PS signals
//RESET+CLK
input sys_clk;
input sys_nreset;
//MISC
output cclk_n;
output cclk_p;
output chip_nreset;
output [11:0] chipid;
output elink_active;
output mailbox_irq;
//I2C
output i2c_scl_i;
output i2c_sda_i;
input i2c_scl_o;
input i2c_scl_t;
input i2c_sda_o;
input i2c_sda_t;
inout i2c_scl;
inout i2c_sda;
//GPIO
input [NPS-1:0] ps_gpio_o;
input [NPS-1:0] ps_gpio_t;
output [NPS-1:0] ps_gpio_i;
inout [NGPIO-1:0] gpio_n;
inout [NGPIO-1:0] gpio_p;
//TX
output [7:0] txo_data_n;
output [7:0] txo_data_p;
output txo_frame_n;
output txo_frame_p;
output txo_lclk_n;
output txo_lclk_p;
input txi_rd_wait_n;
input txi_rd_wait_p;
input txi_wr_wait_n;
input txi_wr_wait_p;
//RX
input [7:0] rxi_data_n;
input [7:0] rxi_data_p;
input rxi_frame_n;
input rxi_frame_p;
input rxi_lclk_n;
input rxi_lclk_p;
output rxo_rd_wait_n;
output rxo_rd_wait_p;
output rxo_wr_wait_n;
output rxo_wr_wait_p;
output constant_zero;
output constant_one;
/*AUTOINOUT*/
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [31:0] m_axi_araddr; // From axi_elink of axi_elink.v
output [1:0] m_axi_arburst; // From axi_elink of axi_elink.v
output [3:0] m_axi_arcache; // From axi_elink of axi_elink.v
output [M_IDW-1:0] m_axi_arid; // From axi_elink of axi_elink.v
output [7:0] m_axi_arlen; // From axi_elink of axi_elink.v
output m_axi_arlock; // From axi_elink of axi_elink.v
output [2:0] m_axi_arprot; // From axi_elink of axi_elink.v
output [3:0] m_axi_arqos; // From axi_elink of axi_elink.v
output [2:0] m_axi_arsize; // From axi_elink of axi_elink.v
output m_axi_arvalid; // From axi_elink of axi_elink.v
output [31:0] m_axi_awaddr; // From axi_elink of axi_elink.v
output [1:0] m_axi_awburst; // From axi_elink of axi_elink.v
output [3:0] m_axi_awcache; // From axi_elink of axi_elink.v
output [M_IDW-1:0] m_axi_awid; // From axi_elink of axi_elink.v
output [7:0] m_axi_awlen; // From axi_elink of axi_elink.v
output m_axi_awlock; // From axi_elink of axi_elink.v
output [2:0] m_axi_awprot; // From axi_elink of axi_elink.v
output [3:0] m_axi_awqos; // From axi_elink of axi_elink.v
output [2:0] m_axi_awsize; // From axi_elink of axi_elink.v
output m_axi_awvalid; // From axi_elink of axi_elink.v
output m_axi_bready; // From axi_elink of axi_elink.v
output m_axi_rready; // From axi_elink of axi_elink.v
output [63:0] m_axi_wdata; // From axi_elink of axi_elink.v
output [M_IDW-1:0] m_axi_wid; // From axi_elink of axi_elink.v
output m_axi_wlast; // From axi_elink of axi_elink.v
output [7:0] m_axi_wstrb; // From axi_elink of axi_elink.v
output m_axi_wvalid; // From axi_elink of axi_elink.v
output s_axi_arready; // From axi_elink of axi_elink.v
output s_axi_awready; // From axi_elink of axi_elink.v
output [S_IDW-1:0] s_axi_bid; // From axi_elink of axi_elink.v
output [1:0] s_axi_bresp; // From axi_elink of axi_elink.v
output s_axi_bvalid; // From axi_elink of axi_elink.v
output [31:0] s_axi_rdata; // From axi_elink of axi_elink.v
output [S_IDW-1:0] s_axi_rid; // From axi_elink of axi_elink.v
output s_axi_rlast; // From axi_elink of axi_elink.v
output [1:0] s_axi_rresp; // From axi_elink of axi_elink.v
output s_axi_rvalid; // From axi_elink of axi_elink.v
output s_axi_wready; // From axi_elink of axi_elink.v
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input m_axi_aresetn; // To axi_elink of axi_elink.v
input m_axi_arready; // To axi_elink of axi_elink.v
input m_axi_awready; // To axi_elink of axi_elink.v
input [M_IDW-1:0] m_axi_bid; // To axi_elink of axi_elink.v
input [1:0] m_axi_bresp; // To axi_elink of axi_elink.v
input m_axi_bvalid; // To axi_elink of axi_elink.v
input [63:0] m_axi_rdata; // To axi_elink of axi_elink.v
input [M_IDW-1:0] m_axi_rid; // To axi_elink of axi_elink.v
input m_axi_rlast; // To axi_elink of axi_elink.v
input [1:0] m_axi_rresp; // To axi_elink of axi_elink.v
input m_axi_rvalid; // To axi_elink of axi_elink.v
input m_axi_wready; // To axi_elink of axi_elink.v
input [31:0] s_axi_araddr; // To axi_elink of axi_elink.v
input [1:0] s_axi_arburst; // To axi_elink of axi_elink.v
input [3:0] s_axi_arcache; // To axi_elink of axi_elink.v
input s_axi_aresetn; // To axi_elink of axi_elink.v
input [S_IDW-1:0] s_axi_arid; // To axi_elink of axi_elink.v
input [7:0] s_axi_arlen; // To axi_elink of axi_elink.v
input s_axi_arlock; // To axi_elink of axi_elink.v
input [2:0] s_axi_arprot; // To axi_elink of axi_elink.v
input [3:0] s_axi_arqos; // To axi_elink of axi_elink.v
input [2:0] s_axi_arsize; // To axi_elink of axi_elink.v
input s_axi_arvalid; // To axi_elink of axi_elink.v
input [31:0] s_axi_awaddr; // To axi_elink of axi_elink.v
input [1:0] s_axi_awburst; // To axi_elink of axi_elink.v
input [3:0] s_axi_awcache; // To axi_elink of axi_elink.v
input [S_IDW-1:0] s_axi_awid; // To axi_elink of axi_elink.v
input [7:0] s_axi_awlen; // To axi_elink of axi_elink.v
input s_axi_awlock; // To axi_elink of axi_elink.v
input [2:0] s_axi_awprot; // To axi_elink of axi_elink.v
input [3:0] s_axi_awqos; // To axi_elink of axi_elink.v
input [2:0] s_axi_awsize; // To axi_elink of axi_elink.v
input s_axi_awvalid; // To axi_elink of axi_elink.v
input s_axi_bready; // To axi_elink of axi_elink.v
input s_axi_rready; // To axi_elink of axi_elink.v
input [31:0] s_axi_wdata; // To axi_elink of axi_elink.v
input [S_IDW-1:0] s_axi_wid; // To axi_elink of axi_elink.v
input s_axi_wlast; // To axi_elink of axi_elink.v
input [3:0] s_axi_wstrb; // To axi_elink of axi_elink.v
input s_axi_wvalid; // To axi_elink of axi_elink.v
// End of automatics
/*AUTOWIRE*/
assign constant_zero = 1'b0;
assign constant_one = 1'b1;
/*axi_elink AUTO_TEMPLATE (
.m_axi_\(.*\) (m_axi_\1[]),
.s_axi_\(.*\) (s_axi_\1[]),
);
*/
defparam axi_elink.ID=ID;
axi_elink axi_elink (
/*AUTOINST*/
// Outputs
.elink_active (elink_active),
.rxo_wr_wait_p (rxo_wr_wait_p),
.rxo_wr_wait_n (rxo_wr_wait_n),
.rxo_rd_wait_p (rxo_rd_wait_p),
.rxo_rd_wait_n (rxo_rd_wait_n),
.txo_lclk_p (txo_lclk_p),
.txo_lclk_n (txo_lclk_n),
.txo_frame_p (txo_frame_p),
.txo_frame_n (txo_frame_n),
.txo_data_p (txo_data_p[7:0]),
.txo_data_n (txo_data_n[7:0]),
.chipid (chipid[11:0]),
.chip_nreset (chip_nreset),
.cclk_p (cclk_p),
.cclk_n (cclk_n),
.mailbox_irq (mailbox_irq),
.m_axi_awid (m_axi_awid[M_IDW-1:0]), // Templated
.m_axi_awaddr (m_axi_awaddr[31:0]), // Templated
.m_axi_awlen (m_axi_awlen[7:0]), // Templated
.m_axi_awsize (m_axi_awsize[2:0]), // Templated
.m_axi_awburst (m_axi_awburst[1:0]), // Templated
.m_axi_awlock (m_axi_awlock), // Templated
.m_axi_awcache (m_axi_awcache[3:0]), // Templated
.m_axi_awprot (m_axi_awprot[2:0]), // Templated
.m_axi_awqos (m_axi_awqos[3:0]), // Templated
.m_axi_awvalid (m_axi_awvalid), // Templated
.m_axi_wid (m_axi_wid[M_IDW-1:0]), // Templated
.m_axi_wdata (m_axi_wdata[63:0]), // Templated
.m_axi_wstrb (m_axi_wstrb[7:0]), // Templated
.m_axi_wlast (m_axi_wlast), // Templated
.m_axi_wvalid (m_axi_wvalid), // Templated
.m_axi_bready (m_axi_bready), // Templated
.m_axi_arid (m_axi_arid[M_IDW-1:0]), // Templated
.m_axi_araddr (m_axi_araddr[31:0]), // Templated
.m_axi_arlen (m_axi_arlen[7:0]), // Templated
.m_axi_arsize (m_axi_arsize[2:0]), // Templated
.m_axi_arburst (m_axi_arburst[1:0]), // Templated
.m_axi_arlock (m_axi_arlock), // Templated
.m_axi_arcache (m_axi_arcache[3:0]), // Templated
.m_axi_arprot (m_axi_arprot[2:0]), // Templated
.m_axi_arqos (m_axi_arqos[3:0]), // Templated
.m_axi_arvalid (m_axi_arvalid), // Templated
.m_axi_rready (m_axi_rready), // Templated
.s_axi_arready (s_axi_arready), // Templated
.s_axi_awready (s_axi_awready), // Templated
.s_axi_bid (s_axi_bid[S_IDW-1:0]), // Templated
.s_axi_bresp (s_axi_bresp[1:0]), // Templated
.s_axi_bvalid (s_axi_bvalid), // Templated
.s_axi_rid (s_axi_rid[S_IDW-1:0]), // Templated
.s_axi_rdata (s_axi_rdata[31:0]), // Templated
.s_axi_rlast (s_axi_rlast), // Templated
.s_axi_rresp (s_axi_rresp[1:0]), // Templated
.s_axi_rvalid (s_axi_rvalid), // Templated
.s_axi_wready (s_axi_wready), // Templated
// Inputs
.sys_nreset (sys_nreset),
.sys_clk (sys_clk),
.rxi_lclk_p (rxi_lclk_p),
.rxi_lclk_n (rxi_lclk_n),
.rxi_frame_p (rxi_frame_p),
.rxi_frame_n (rxi_frame_n),
.rxi_data_p (rxi_data_p[7:0]),
.rxi_data_n (rxi_data_n[7:0]),
.txi_wr_wait_p (txi_wr_wait_p),
.txi_wr_wait_n (txi_wr_wait_n),
.txi_rd_wait_p (txi_rd_wait_p),
.txi_rd_wait_n (txi_rd_wait_n),
.m_axi_aresetn (m_axi_aresetn), // Templated
.m_axi_awready (m_axi_awready), // Templated
.m_axi_wready (m_axi_wready), // Templated
.m_axi_bid (m_axi_bid[M_IDW-1:0]), // Templated
.m_axi_bresp (m_axi_bresp[1:0]), // Templated
.m_axi_bvalid (m_axi_bvalid), // Templated
.m_axi_arready (m_axi_arready), // Templated
.m_axi_rid (m_axi_rid[M_IDW-1:0]), // Templated
.m_axi_rdata (m_axi_rdata[63:0]), // Templated
.m_axi_rresp (m_axi_rresp[1:0]), // Templated
.m_axi_rlast (m_axi_rlast), // Templated
.m_axi_rvalid (m_axi_rvalid), // Templated
.s_axi_aresetn (s_axi_aresetn), // Templated
.s_axi_arid (s_axi_arid[S_IDW-1:0]), // Templated
.s_axi_araddr (s_axi_araddr[31:0]), // Templated
.s_axi_arburst (s_axi_arburst[1:0]), // Templated
.s_axi_arcache (s_axi_arcache[3:0]), // Templated
.s_axi_arlock (s_axi_arlock), // Templated
.s_axi_arlen (s_axi_arlen[7:0]), // Templated
.s_axi_arprot (s_axi_arprot[2:0]), // Templated
.s_axi_arqos (s_axi_arqos[3:0]), // Templated
.s_axi_arsize (s_axi_arsize[2:0]), // Templated
.s_axi_arvalid (s_axi_arvalid), // Templated
.s_axi_awid (s_axi_awid[S_IDW-1:0]), // Templated
.s_axi_awaddr (s_axi_awaddr[31:0]), // Templated
.s_axi_awburst (s_axi_awburst[1:0]), // Templated
.s_axi_awcache (s_axi_awcache[3:0]), // Templated
.s_axi_awlock (s_axi_awlock), // Templated
.s_axi_awlen (s_axi_awlen[7:0]), // Templated
.s_axi_awprot (s_axi_awprot[2:0]), // Templated
.s_axi_awqos (s_axi_awqos[3:0]), // Templated
.s_axi_awsize (s_axi_awsize[2:0]), // Templated
.s_axi_awvalid (s_axi_awvalid), // Templated
.s_axi_bready (s_axi_bready), // Templated
.s_axi_rready (s_axi_rready), // Templated
.s_axi_wid (s_axi_wid[S_IDW-1:0]), // Templated
.s_axi_wdata (s_axi_wdata[31:0]), // Templated
.s_axi_wlast (s_axi_wlast), // Templated
.s_axi_wstrb (s_axi_wstrb[3:0]), // Templated
.s_axi_wvalid (s_axi_wvalid)); // Templated
pgpio #(.NGPIO(NGPIO)) pgpio (/*AUTOINST*/
// Outputs
.ps_gpio_i (ps_gpio_i[NPS-1:0]),
// Inouts
.gpio_p (gpio_p[NGPIO-1:0]),
.gpio_n (gpio_n[NGPIO-1:0]),
// Inputs
.ps_gpio_o (ps_gpio_o[NPS-1:0]),
.ps_gpio_t (ps_gpio_t[NPS-1:0]));
pi2c pi2c (/*AUTOINST*/
// Outputs
.i2c_sda_i (i2c_sda_i),
.i2c_scl_i (i2c_scl_i),
// Inouts
.i2c_sda (i2c_sda),
.i2c_scl (i2c_scl),
// Inputs
.i2c_sda_o (i2c_sda_o),
.i2c_sda_t (i2c_sda_t),
.i2c_scl_o (i2c_scl_o),
.i2c_scl_t (i2c_scl_t));
endmodule // parallella_generic
// Local Variables:
// verilog-library-directories:("." "../../elink/hdl")
// End:
|
module opt_rmdff_test (input C, input D, input E, output [29:0] Q);
\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove0 (.CLK(C), .D(D), .EN(1'b0), .Q(Q[0])); // EN is never active
(* init = 1'b1 *) wire Q1; assign Q[1] = Q1;
\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove1 (.CLK(C), .D(D), .EN(1'b0), .Q(Q1)); // EN is never active
\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove2 (.CLK(C), .D(D), .EN(1'bx), .Q(Q[2])); // EN is don't care
\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) keep3 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[3])); // EN is always active
(* init = 1'b0 *) wire Q4; assign Q[4] = Q4;
\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(1)) keep4 (.CLK(C), .D(D), .EN(1'b1), .Q(Q4)); // EN is always active
\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove5 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[5])); // EN is never active
\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove6 (.CLK(C), .D(D), .EN(1'bx), .Q(Q[6])); // EN is don't care
(* init = 1'b0 *) wire Q7; assign Q[7] = Q7;
\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(0)) keep7 (.CLK(C), .D(D), .EN(E), .Q(Q7)); // EN is non constant
\$_DFFE_PP_ remove8 (.C(C), .D(D), .E(1'b0), .Q(Q[8])); // EN is never active
(* init = 1'b1 *) wire Q9; assign Q[9] = Q9;
\$_DFFE_PP_ remove9 (.C(C), .D(D), .E(1'b0), .Q(Q9)); // EN is never active
\$_DFFE_PP_ remove10 (.C(C), .D(D), .E(1'bx), .Q(Q[10])); // EN is don't care
\$_DFFE_PP_ keep11 (.C(C), .D(D), .E(1'b1), .Q(Q[11])); // EN is always active
(* init = 1'b0 *) wire Q12; assign Q[12] = Q12;
\$_DFFE_PP_ keep12 (.C(C), .D(D), .E(1'b1), .Q(Q12)); // EN is always active
\$_DFFE_NN_ remove13 (.C(C), .D(D), .E(1'b1), .Q(Q[13])); // EN is never active
(* init = 1'b1 *) wire Q14; assign Q[14] = Q14;
\$_DFFE_NN_ remove14 (.C(C), .D(D), .E(1'b1), .Q(Q14)); // EN is never active
\$_DFFE_NN_ remove15 (.C(C), .D(D), .E(1'bx), .Q(Q[15])); // EN is don't care
\$_DFFE_NN_ keep16 (.C(C), .D(D), .E(1'b0), .Q(Q[16])); // EN is always active
(* init = 1'b0 *) wire Q17; assign Q[17] = Q17;
\$_DFFE_NN_ keep17 (.C(C), .D(D), .E(1'b0), .Q(Q17)); // EN is always active
\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove18 (.CLK(1'b0), .D(D), .EN(E), .Q(Q[18])); // CLK is constant
(* init = 1'b1 *) wire Q19; assign Q[19] = Q19;
\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove19 (.CLK(1'b1), .D(D), .EN(E), .Q(Q19)); // CLK is constant
\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove20 (.CLK(C), .D(1'bx), .EN(E), .Q(Q[20])); // D is undriven, Q has no initial value
(* init = 1'b0 *) wire Q21; assign Q[21] = Q21;
\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) keep21 (.CLK(C), .D(1'bx), .EN(E), .Q(Q21)); // D is undriven, Q has initial value
//\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(1)) remove22 (.CLK(C), .D(1'b0), .EN(1'b1), .Q(Q[22])); // D is constant, no initial Q value, EN is always active
// // (TODO, Q starts with 1'bx and becomes 1'b0)
(* init = 1'b0 *) wire Q23; assign Q[23] = Q23;
\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) noenable23 (.CLK(C), .D(1'b0), .EN(1'b1), .Q(Q23)); // D is constant, initial Q value same as D, EN is always active
(* init = 1'b1 *) wire Q24; assign Q[24] = Q24;
\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) keep24 (.CLK(C), .D(1'b0), .EN(1'b0), .Q(Q24)); // D is constant, initial Q value NOT same as D, EN is always active
(* init = 1'b1 *) wire Q25; assign Q[25] = Q25;
\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove25 (.CLK(C), .D(1'b0), .EN(1'b1), .Q(Q25)); // D is constant, EN is never active
\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove26 (.CLK(C), .D(Q[26]), .EN(1'b1), .Q(Q[26])); // D is Q, EN is always active
\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove27 (.CLK(C), .D(Q[27]), .EN(1'b1), .Q(Q[27])); // D is Q, EN is never active, but no initial value
\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove28 (.CLK(C), .D(Q[28]), .EN(E), .Q(Q[28])); // EN is nonconst, but no initial value
(* init = 1'b1 *) wire Q29; assign Q[29] = Q29;
\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) keep29 (.CLK(C), .D(Q[29]), .EN(1'b1), .Q(Q29)); // EN is always active, but with initial value
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_atomics_arb_stall
#(
// Configuration
parameter integer STALL_CYCLES = 6
)
(
input logic clock,
input logic resetn,
acl_arb_intf in_intf,
acl_arb_intf out_intf
);
/******************
* Local Variables *
******************/
reg shift_register [0:STALL_CYCLES-1];
wire atomic;
wire stall;
integer t;
/******************
* Local Variables *
******************/
assign out_intf.req.request = ( in_intf.req.request & ~stall ); // mask request
assign out_intf.req.read = ( in_intf.req.read & ~stall ); // mask read
assign out_intf.req.write = ( in_intf.req.write & ~stall ); // mask write
assign out_intf.req.writedata = in_intf.req.writedata;
assign out_intf.req.burstcount = in_intf.req.burstcount;
assign out_intf.req.address = in_intf.req.address;
assign out_intf.req.byteenable = in_intf.req.byteenable;
assign out_intf.req.id = in_intf.req.id;
assign in_intf.stall = ( out_intf.stall | stall );
/*****************
* Detect Atomic *
******************/
assign atomic = ( out_intf.req.request == 1'b1 &&
out_intf.req.read == 1'b1 &&
out_intf.req.writedata[0:0] == 1'b1 ) ? 1'b1 : 1'b0;
always@(posedge clock or negedge resetn)
begin
if ( !resetn ) begin
shift_register[0] <= 1'b0;
end
else begin
shift_register[0] <= atomic;
end
end
/*****************
* Shift Register *
******************/
always@(posedge clock or negedge resetn)
begin
for (t=1; t< STALL_CYCLES; t=t+1)
begin
if ( !resetn ) begin
shift_register[t] <= 1'b0;
end
else begin
shift_register[t] <= shift_register[t-1];
end
end
end
/***************
* Detect Stall *
***************/
assign stall = ( shift_register[STALL_CYCLES-1] == 1'b1 );
endmodule
|
module pwm_TB;
reg reset, clk;
reg micData, enable;
reg wr;
pwm uut(.reset(reset),.doutmic(micData),.clk(clk),.enable(enable),.wr(wr));
always
begin
wr=1'b0;
#100;
wr =1'b1;
#100;
end
always
begin
clk =1'b1;
#2;
clk=1'b0;
#2;
end
initial
begin
enable=1'b0;
#100000;
enable =1'b1;
end
initial
begin
reset =1'b1;
#10000;
reset =1'b0;
end
/*initial
begin
rd = 1'b0;
wr = 1'b0;
#10000 wr = 1'b1;
#150000 wr = 1'b0;
#15010 rd = 1'b1;
end
*/
initial begin
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
end
initial begin: TEST_CASE
$dumpfile("pwm_TB.vcd");
$dumpvars(-1, uut);
#(1000000) $finish;
end
endmodule //
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// NOTE: This is still WIP.
(* techmap_celltype = "$alu" *)
module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
//output [Y_WIDTH-1:0] CO;
output CO;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 4;
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
wire [Y_WIDTH-1:0] AA = A_buf;
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
//wire [Y_WIDTH:0] C = {CO, CI};
wire [Y_WIDTH+1:0] COx;
wire [Y_WIDTH+1:0] C = {COx, CI};
/* Start implementation */
(* keep *) cyclone10lp_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1));
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
if(i==Y_WIDTH-1) begin
(* keep *) cyclone10lp_lcell_comb #(.lut_mask(16'b1111_0000_1110_0000), .sum_lutc_input("cin")) carry_end (.combout(COx[Y_WIDTH]), .dataa(1'b1), .datab(1'b1), .datac(1'b1), .datad(1'b1), .cin(C[Y_WIDTH]));
assign CO = COx[Y_WIDTH];
end
else
cyclone10lp_lcell_comb #(.lut_mask(16'b1001_0110_1110_1000), .sum_lutc_input("cin")) arith_cell (.combout(Y[i]), .cout(COx[i+1]), .dataa(AA[i]), .datab(BB[i]), .datac(1'b1), .datad(1'b1), .cin(C[i+1]));
end: slice
endgenerate
/* End implementation */
assign X = AA ^ BB;
endmodule
|
// Copyright 2007 Altera Corporation. All rights reserved.
// Altera products are protected under numerous U.S. and foreign patents,
// maskwork rights, copyrights and other intellectual property laws.
//
// This reference design file, and your use thereof, is subject to and governed
// by the terms and conditions of the applicable Altera Reference Design
// License Agreement (either as signed by you or found at www.altera.com). By
// using this reference design file, you indicate your acceptance of such terms
// and conditions between you and Altera Corporation. In the event that you do
// not agree with such terms and conditions, you may not use the reference
// design file and please promptly destroy any copies you have made.
//
// This reference design file is being provided on an "as-is" basis and as an
// accommodation and therefore all warranties, representations or guarantees of
// any kind (whether express, implied or statutory) including, without
// limitation, warranties of merchantability, non-infringement, or fitness for
// a particular purpose, are specifically disclaimed. By making this reference
// design file available, Altera expressly does not recommend, suggest or
// require that this reference design file be used in combination with any
// other product not provided by Altera.
/////////////////////////////////////////////////////////////////////////////
// baeckler - 05-13-2005
//
// Six input three output compressor (non-carry adder)
//
// Maps to 3 Stratix II six luts. Use optimize = speed
//
module six_three_comp (data,sum);
input [5:0] data;
output [2:0] sum;
reg [2:0] sum /* synthesis keep */;
always @(data) begin
case (data)
0: sum=0;
1: sum=1;
2: sum=1;
3: sum=2;
4: sum=1;
5: sum=2;
6: sum=2;
7: sum=3;
8: sum=1;
9: sum=2;
10: sum=2;
11: sum=3;
12: sum=2;
13: sum=3;
14: sum=3;
15: sum=4;
16: sum=1;
17: sum=2;
18: sum=2;
19: sum=3;
20: sum=2;
21: sum=3;
22: sum=3;
23: sum=4;
24: sum=2;
25: sum=3;
26: sum=3;
27: sum=4;
28: sum=3;
29: sum=4;
30: sum=4;
31: sum=5;
32: sum=1;
33: sum=2;
34: sum=2;
35: sum=3;
36: sum=2;
37: sum=3;
38: sum=3;
39: sum=4;
40: sum=2;
41: sum=3;
42: sum=3;
43: sum=4;
44: sum=3;
45: sum=4;
46: sum=4;
47: sum=5;
48: sum=2;
49: sum=3;
50: sum=3;
51: sum=4;
52: sum=3;
53: sum=4;
54: sum=4;
55: sum=5;
56: sum=3;
57: sum=4;
58: sum=4;
59: sum=5;
60: sum=4;
61: sum=5;
62: sum=5;
63: sum=6;
default: sum=0;
endcase
end
endmodule
|
`default_nettype none
`timescale 1ns/1ns
module tb_mem();
wire clk, reset;
clock clock(clk, reset);
reg m0_write = 0;
reg m0_read = 0;
reg [35:0] m0_writedata = 0;
reg [17:0] m0_address = 0;
wire [35:0] m0_readdata;
wire m0_waitrequest;
reg m1_write = 0;
reg m1_read = 0;
reg [35:0] m1_writedata = 0;
reg [17:0] m1_address = 0;
wire [35:0] m1_readdata;
wire m1_waitrequest;
wire s_write, s_read, s_waitrequest;
wire [17:0] s_address;
wire [35:0] s_writedata, s_readdata;
arbiter arb0(.clk(clk), .reset(reset),
.s0_address(m0_address),
.s0_write(m0_write),
.s0_read(m0_read),
.s0_writedata(m0_writedata),
.s0_readdata(m0_readdata),
.s0_waitrequest(m0_waitrequest),
.s1_address(m1_address),
.s1_write(m1_write),
.s1_read(m1_read),
.s1_writedata(m1_writedata),
.s1_readdata(m1_readdata),
.s1_waitrequest(m1_waitrequest),
.m_address(s_address),
.m_write(s_write),
.m_read(s_read),
.m_writedata(s_writedata),
.m_readdata(s_readdata),
.m_waitrequest(s_waitrequest));
testmem16k memory(.i_clk(clk), .i_reset_n(reset),
.i_address(s_address), .i_write(s_write), .i_read(s_read),
.i_writedata(s_writedata),
.o_readdata(s_readdata),
.o_waitrequest(s_waitrequest));
initial begin
$dumpfile("dump.vcd");
$dumpvars();
// memory.mem[4] = 'o123;
// memory.mem[5] = 'o321;
// memory.mem[8] = 'o11111;
memory.ram.ram[4] = 'o123;
memory.ram.ram[5] = 'o321;
memory.ram.ram[6] = 'o444444;
memory.ram.ram[8] = 'o11111;
#5;
#200;
m0_address <= 'o4;
// m1_address <= 'o10;
m0_write <= 1;
// m1_write <= 1;
m0_writedata <= 'o1234;
// m1_writedata <= 'o4321;
@(negedge m0_write);
@(posedge clk);
m0_address <= 5;
m0_read <= 1;
@(negedge m0_read);
@(posedge clk);
m0_address <= 6;
m0_read <= 1;
@(negedge m0_read);
@(posedge clk);
m0_address <= 0;
m0_read <= 1;
@(negedge m0_read);
@(posedge clk);
m0_address <= 4;
m0_read <= 1;
end
initial begin
#40000;
$finish;
end
reg [35:0] data0;
reg [35:0] data1;
always @(posedge clk) begin
if(~m0_waitrequest & m0_write)
m0_write <= 0;
if(~m0_waitrequest & m0_read) begin
m0_read <= 0;
data0 <= m0_readdata;
end
if(~m1_waitrequest & m1_write)
m1_write <= 0;
if(~m1_waitrequest & m1_read) begin
m1_read <= 0;
data1 <= m1_readdata;
end
end
endmodule
|
module mem_window (
clk,
reset,
// Memory slave port
s1_address,
s1_read,
s1_readdata,
s1_readdatavalid,
s1_write,
s1_writedata,
s1_burstcount,
s1_byteenable,
s1_waitrequest,
// Configuration register slave port
cra_write,
cra_writedata,
cra_byteenable,
// Bridged master port to memory
m1_address,
m1_read,
m1_readdata,
m1_readdatavalid,
m1_write,
m1_writedata,
m1_burstcount,
m1_byteenable,
m1_waitrequest
);
parameter PAGE_ADDRESS_WIDTH = 20;
parameter MEM_ADDRESS_WIDTH = 32;
parameter NUM_BYTES = 32;
parameter BURSTCOUNT_WIDTH = 1;
parameter CRA_BITWIDTH = 32;
localparam ADDRESS_SHIFT = $clog2(NUM_BYTES);
localparam PAGE_ID_WIDTH = MEM_ADDRESS_WIDTH - PAGE_ADDRESS_WIDTH - ADDRESS_SHIFT;
localparam DATA_WIDTH = NUM_BYTES * 8;
input clk;
input reset;
// Memory slave port
input [PAGE_ADDRESS_WIDTH-1:0] s1_address;
input s1_read;
output [DATA_WIDTH-1:0] s1_readdata;
output s1_readdatavalid;
input s1_write;
input [DATA_WIDTH-1:0] s1_writedata;
input [BURSTCOUNT_WIDTH-1:0] s1_burstcount;
input [NUM_BYTES-1:0] s1_byteenable;
output s1_waitrequest;
// Bridged master port to memory
output [MEM_ADDRESS_WIDTH-1:0] m1_address;
output m1_read;
input [DATA_WIDTH-1:0] m1_readdata;
input m1_readdatavalid;
output m1_write;
output [DATA_WIDTH-1:0] m1_writedata;
output [BURSTCOUNT_WIDTH-1:0] m1_burstcount;
output [NUM_BYTES-1:0] m1_byteenable;
input m1_waitrequest;
// CRA slave
input cra_write;
input [CRA_BITWIDTH-1:0] cra_writedata;
input [CRA_BITWIDTH/8-1:0] cra_byteenable;
// Architecture
// CRA slave allows the master to change the active page
reg [PAGE_ID_WIDTH-1:0] page_id;
reg [CRA_BITWIDTH-1:0] cra_writemask;
integer i;
always@*
for (i=0; i<CRA_BITWIDTH; i=i+1)
cra_writemask[i] = cra_byteenable[i/8] & cra_write;
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
page_id <= {PAGE_ID_WIDTH{1'b0}};
else
page_id <= (cra_writedata & cra_writemask) | (page_id & ~cra_writemask);
end
// The s1 port bridges to the m1 port - with the page ID tacked on to the address
assign m1_address = {page_id, s1_address, {ADDRESS_SHIFT{1'b0}}};
assign m1_read = s1_read;
assign s1_readdata = m1_readdata;
assign s1_readdatavalid = m1_readdatavalid;
assign m1_write = s1_write;
assign m1_writedata = s1_writedata;
assign m1_burstcount = s1_burstcount;
assign m1_byteenable = s1_byteenable;
assign s1_waitrequest = m1_waitrequest;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLCLKP_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__DLCLKP_PP_BLACKBOX_V
/**
* dlclkp: Clock gate.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlclkp (
GCLK,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
output GCLK;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLCLKP_PP_BLACKBOX_V
|
// `define ASYNC_RESET
module fsm_test(clk, reset, button_a, button_b, red_a, green_a, red_b, green_b);
input clk, reset, button_a, button_b;
output reg red_a, green_a, red_b, green_b;
(* gentb_constant = 0 *)
wire reset;
(* fsm_obfuscate = "true" *)
(* fsm_obfuscate_states = "7" *)
integer state;
reg [3:0] cnt;
`ifdef ASYNC_RESET
always @(posedge clk, posedge reset)
`else
always @(posedge clk)
`endif
begin
cnt <= 0;
red_a <= 1;
red_b <= 1;
green_a <= 0;
green_b <= 0;
if (reset)
state <= 100;
else
case (state)
100: begin
if (button_a && !button_b)
state <= 200;
if (!button_a && button_b)
state <= 300;
end
200: begin
red_a <= 0;
green_a <= 1;
cnt <= cnt + 1;
if (cnt == 5)
state <= 210;
end
210: begin
red_a <= 0;
green_a <= cnt[0];
cnt <= cnt + 1;
if (cnt == 10)
state <= 100;
end
300: begin
red_b <= 0;
green_b <= 1;
cnt <= cnt + 1;
if (cnt == 5)
state <= 310;
end
310: begin
red_b <= 0;
green_b <= cnt[0];
cnt <= cnt + 1;
if (cnt == 10)
state <= 100;
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O2111A_PP_SYMBOL_V
`define SKY130_FD_SC_HD__O2111A_PP_SYMBOL_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o2111a (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input C1 ,
input D1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O2111A_PP_SYMBOL_V
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: one_hot_mux.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: A mux module, where the output select is a one-hot bus
// Author: Dustin Richmond
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "functions.vh"
module one_hot_mux
#(parameter C_DATA_WIDTH = 1,
parameter C_SELECT_WIDTH = 2,
parameter C_AGGREGATE_WIDTH = C_SELECT_WIDTH*C_DATA_WIDTH
)
(
input [C_SELECT_WIDTH-1:0] ONE_HOT_SELECT,
input [C_AGGREGATE_WIDTH-1:0] ONE_HOT_INPUTS,
output [C_DATA_WIDTH-1:0] ONE_HOT_OUTPUT);
genvar i;
wire [C_DATA_WIDTH-1:0] wOneHotInputs[(1<<C_SELECT_WIDTH):1];
reg [C_DATA_WIDTH-1:0] _rOneHotOutput;
assign ONE_HOT_OUTPUT = _rOneHotOutput;
generate
for( i = 0 ; i < C_SELECT_WIDTH; i = i + 1 ) begin : gen_input_array
assign wOneHotInputs[(1<<i)] = ONE_HOT_INPUTS[C_DATA_WIDTH*i +: C_DATA_WIDTH];
end
if(C_SELECT_WIDTH == 1) begin
always @(*) begin
_rOneHotOutput = wOneHotInputs[1];
end
end else if(C_SELECT_WIDTH == 2) begin
always @(*) begin
case(ONE_HOT_SELECT)
2'b01: _rOneHotOutput = wOneHotInputs[1];
2'b10: _rOneHotOutput = wOneHotInputs[2];
default:_rOneHotOutput = wOneHotInputs[1];
endcase // case (ONE_HOT_SELECT)
end
end else if( C_SELECT_WIDTH == 4) begin
always @(*) begin
case(ONE_HOT_SELECT)
4'b0001: _rOneHotOutput = wOneHotInputs[1];
4'b0010: _rOneHotOutput = wOneHotInputs[2];
4'b0100: _rOneHotOutput = wOneHotInputs[4];
4'b1000: _rOneHotOutput = wOneHotInputs[8];
default:_rOneHotOutput = wOneHotInputs[1];
endcase // case (ONE_HOT_SELECT)
end
end else if( C_SELECT_WIDTH == 8) begin
always @(*) begin
case(ONE_HOT_SELECT)
8'b00000001: _rOneHotOutput = wOneHotInputs[1];
8'b00000010: _rOneHotOutput = wOneHotInputs[2];
8'b00000100: _rOneHotOutput = wOneHotInputs[4];
8'b00001000: _rOneHotOutput = wOneHotInputs[8];
8'b00010000: _rOneHotOutput = wOneHotInputs[16];
8'b00100000: _rOneHotOutput = wOneHotInputs[32];
8'b01000000: _rOneHotOutput = wOneHotInputs[64];
8'b10000000: _rOneHotOutput = wOneHotInputs[128];
default:_rOneHotOutput = wOneHotInputs[1];
endcase // case (ONE_HOT_SELECT)
end
end
endgenerate
endmodule
|
// -- (c) Copyright 2012 -2013 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
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// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
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// -- Applications"). Customer assumes the sole risk and
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// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: axi_protocol_converter.v
//
// Description:
// This module is a bank of AXI4-Lite and AXI3 protocol converters for a vectored AXI interface.
// The interface of this module consists of a vectored slave and master interface
// which are each concatenations of upper-level AXI pathways,
// plus various vectored parameters.
// This module instantiates a set of individual protocol converter modules.
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_axi_protocol_converter #(
parameter C_FAMILY = "virtex6",
parameter integer C_M_AXI_PROTOCOL = 0,
parameter integer C_S_AXI_PROTOCOL = 0,
parameter integer C_IGNORE_ID = 0,
// 0 = RID/BID are stored by axilite_conv.
// 1 = RID/BID have already been stored in an upstream device, like SASD crossbar.
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_WRITE = 1,
parameter integer C_AXI_SUPPORTS_READ = 1,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
// 1 = Propagate all USER signals, 0 = Dont propagate.
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_TRANSLATION_MODE = 1
// 0 (Unprotected) = Disable all error checking; master is well-behaved.
// 1 (Protection) = Detect SI transaction violations, but perform no splitting.
// AXI4 -> AXI3 must be <= 16 beats; AXI4/3 -> AXI4LITE must be single.
// 2 (Conversion) = Include transaction splitting logic
) (
// Global Signals
input wire aclk,
input wire aresetn,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
input wire [3-1:0] s_axi_awsize,
input wire [2-1:0] s_axi_awburst,
input wire [((C_S_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
input wire [4-1:0] s_axi_awcache,
input wire [3-1:0] s_axi_awprot,
input wire [4-1:0] s_axi_awregion,
input wire [4-1:0] s_axi_awqos,
input wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
input wire s_axi_awvalid,
output wire s_axi_awready,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_wid,
input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input wire s_axi_wlast,
input wire [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
input wire s_axi_wvalid,
output wire s_axi_wready,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [2-1:0] s_axi_bresp,
output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
output wire s_axi_bvalid,
input wire s_axi_bready,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
input wire [3-1:0] s_axi_arsize,
input wire [2-1:0] s_axi_arburst,
input wire [((C_S_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
input wire [4-1:0] s_axi_arcache,
input wire [3-1:0] s_axi_arprot,
input wire [4-1:0] s_axi_arregion,
input wire [4-1:0] s_axi_arqos,
input wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
input wire s_axi_arvalid,
output wire s_axi_arready,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [2-1:0] s_axi_rresp,
output wire s_axi_rlast,
output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
output wire s_axi_rvalid,
input wire s_axi_rready,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_M_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_M_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
output wire m_axi_awvalid,
input wire m_axi_awready,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
output wire m_axi_wvalid,
input wire m_axi_wready,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
input wire m_axi_bvalid,
output wire m_axi_bready,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_M_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_M_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output wire m_axi_arvalid,
input wire m_axi_arready,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input wire m_axi_rvalid,
output wire m_axi_rready
);
localparam P_AXI4 = 32'h0;
localparam P_AXI3 = 32'h1;
localparam P_AXILITE = 32'h2;
localparam P_AXILITE_SIZE = (C_AXI_DATA_WIDTH == 32) ? 3'b010 : 3'b011;
localparam P_INCR = 2'b01;
localparam P_DECERR = 2'b11;
localparam P_SLVERR = 2'b10;
localparam integer P_PROTECTION = 1;
localparam integer P_CONVERSION = 2;
wire s_awvalid_i;
wire s_arvalid_i;
wire s_wvalid_i ;
wire s_bready_i ;
wire s_rready_i ;
wire s_awready_i;
wire s_wready_i;
wire s_bvalid_i;
wire [C_AXI_ID_WIDTH-1:0] s_bid_i;
wire [1:0] s_bresp_i;
wire [C_AXI_BUSER_WIDTH-1:0] s_buser_i;
wire s_arready_i;
wire s_rvalid_i;
wire [C_AXI_ID_WIDTH-1:0] s_rid_i;
wire [1:0] s_rresp_i;
wire [C_AXI_RUSER_WIDTH-1:0] s_ruser_i;
wire [C_AXI_DATA_WIDTH-1:0] s_rdata_i;
wire s_rlast_i;
generate
if ((C_M_AXI_PROTOCOL == P_AXILITE) || (C_S_AXI_PROTOCOL == P_AXILITE)) begin : gen_axilite
assign m_axi_awid = 0;
assign m_axi_awlen = 0;
assign m_axi_awsize = P_AXILITE_SIZE;
assign m_axi_awburst = P_INCR;
assign m_axi_awlock = 0;
assign m_axi_awcache = 0;
assign m_axi_awregion = 0;
assign m_axi_awqos = 0;
assign m_axi_awuser = 0;
assign m_axi_wid = 0;
assign m_axi_wlast = 1'b1;
assign m_axi_wuser = 0;
assign m_axi_arid = 0;
assign m_axi_arlen = 0;
assign m_axi_arsize = P_AXILITE_SIZE;
assign m_axi_arburst = P_INCR;
assign m_axi_arlock = 0;
assign m_axi_arcache = 0;
assign m_axi_arregion = 0;
assign m_axi_arqos = 0;
assign m_axi_aruser = 0;
if (((C_IGNORE_ID == 1) && (C_TRANSLATION_MODE != P_CONVERSION)) || (C_S_AXI_PROTOCOL == P_AXILITE)) begin : gen_axilite_passthru
assign m_axi_awaddr = s_axi_awaddr;
assign m_axi_awprot = s_axi_awprot;
assign m_axi_awvalid = s_awvalid_i;
assign s_awready_i = m_axi_awready;
assign m_axi_wdata = s_axi_wdata;
assign m_axi_wstrb = s_axi_wstrb;
assign m_axi_wvalid = s_wvalid_i;
assign s_wready_i = m_axi_wready;
assign s_bid_i = 0;
assign s_bresp_i = m_axi_bresp;
assign s_buser_i = 0;
assign s_bvalid_i = m_axi_bvalid;
assign m_axi_bready = s_bready_i;
assign m_axi_araddr = s_axi_araddr;
assign m_axi_arprot = s_axi_arprot;
assign m_axi_arvalid = s_arvalid_i;
assign s_arready_i = m_axi_arready;
assign s_rid_i = 0;
assign s_rdata_i = m_axi_rdata;
assign s_rresp_i = m_axi_rresp;
assign s_rlast_i = 1'b1;
assign s_ruser_i = 0;
assign s_rvalid_i = m_axi_rvalid;
assign m_axi_rready = s_rready_i;
end else if (C_TRANSLATION_MODE == P_CONVERSION) begin : gen_b2s_conv
assign s_buser_i = {C_AXI_BUSER_WIDTH{1'b0}};
assign s_ruser_i = {C_AXI_RUSER_WIDTH{1'b0}};
axi_protocol_converter_v2_1_b2s #(
.C_S_AXI_PROTOCOL (C_S_AXI_PROTOCOL),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_SUPPORTS_WRITE (C_AXI_SUPPORTS_WRITE),
.C_AXI_SUPPORTS_READ (C_AXI_SUPPORTS_READ)
) axilite_b2s (
.aresetn (aresetn),
.aclk (aclk),
.s_axi_awid (s_axi_awid),
.s_axi_awaddr (s_axi_awaddr),
.s_axi_awlen (s_axi_awlen),
.s_axi_awsize (s_axi_awsize),
.s_axi_awburst (s_axi_awburst),
.s_axi_awprot (s_axi_awprot),
.s_axi_awvalid (s_awvalid_i),
.s_axi_awready (s_awready_i),
.s_axi_wdata (s_axi_wdata),
.s_axi_wstrb (s_axi_wstrb),
.s_axi_wlast (s_axi_wlast),
.s_axi_wvalid (s_wvalid_i),
.s_axi_wready (s_wready_i),
.s_axi_bid (s_bid_i),
.s_axi_bresp (s_bresp_i),
.s_axi_bvalid (s_bvalid_i),
.s_axi_bready (s_bready_i),
.s_axi_arid (s_axi_arid),
.s_axi_araddr (s_axi_araddr),
.s_axi_arlen (s_axi_arlen),
.s_axi_arsize (s_axi_arsize),
.s_axi_arburst (s_axi_arburst),
.s_axi_arprot (s_axi_arprot),
.s_axi_arvalid (s_arvalid_i),
.s_axi_arready (s_arready_i),
.s_axi_rid (s_rid_i),
.s_axi_rdata (s_rdata_i),
.s_axi_rresp (s_rresp_i),
.s_axi_rlast (s_rlast_i),
.s_axi_rvalid (s_rvalid_i),
.s_axi_rready (s_rready_i),
.m_axi_awaddr (m_axi_awaddr),
.m_axi_awprot (m_axi_awprot),
.m_axi_awvalid (m_axi_awvalid),
.m_axi_awready (m_axi_awready),
.m_axi_wdata (m_axi_wdata),
.m_axi_wstrb (m_axi_wstrb),
.m_axi_wvalid (m_axi_wvalid),
.m_axi_wready (m_axi_wready),
.m_axi_bresp (m_axi_bresp),
.m_axi_bvalid (m_axi_bvalid),
.m_axi_bready (m_axi_bready),
.m_axi_araddr (m_axi_araddr),
.m_axi_arprot (m_axi_arprot),
.m_axi_arvalid (m_axi_arvalid),
.m_axi_arready (m_axi_arready),
.m_axi_rdata (m_axi_rdata),
.m_axi_rresp (m_axi_rresp),
.m_axi_rvalid (m_axi_rvalid),
.m_axi_rready (m_axi_rready)
);
end else begin : gen_axilite_conv
axi_protocol_converter_v2_1_axilite_conv #(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_SUPPORTS_WRITE (C_AXI_SUPPORTS_WRITE),
.C_AXI_SUPPORTS_READ (C_AXI_SUPPORTS_READ),
.C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH)
) axilite_conv_inst (
.ARESETN (aresetn),
.ACLK (aclk),
.S_AXI_AWID (s_axi_awid),
.S_AXI_AWADDR (s_axi_awaddr),
.S_AXI_AWPROT (s_axi_awprot),
.S_AXI_AWVALID (s_awvalid_i),
.S_AXI_AWREADY (s_awready_i),
.S_AXI_WDATA (s_axi_wdata),
.S_AXI_WSTRB (s_axi_wstrb),
.S_AXI_WVALID (s_wvalid_i),
.S_AXI_WREADY (s_wready_i),
.S_AXI_BID (s_bid_i),
.S_AXI_BRESP (s_bresp_i),
.S_AXI_BUSER (s_buser_i),
.S_AXI_BVALID (s_bvalid_i),
.S_AXI_BREADY (s_bready_i),
.S_AXI_ARID (s_axi_arid),
.S_AXI_ARADDR (s_axi_araddr),
.S_AXI_ARPROT (s_axi_arprot),
.S_AXI_ARVALID (s_arvalid_i),
.S_AXI_ARREADY (s_arready_i),
.S_AXI_RID (s_rid_i),
.S_AXI_RDATA (s_rdata_i),
.S_AXI_RRESP (s_rresp_i),
.S_AXI_RLAST (s_rlast_i),
.S_AXI_RUSER (s_ruser_i),
.S_AXI_RVALID (s_rvalid_i),
.S_AXI_RREADY (s_rready_i),
.M_AXI_AWADDR (m_axi_awaddr),
.M_AXI_AWPROT (m_axi_awprot),
.M_AXI_AWVALID (m_axi_awvalid),
.M_AXI_AWREADY (m_axi_awready),
.M_AXI_WDATA (m_axi_wdata),
.M_AXI_WSTRB (m_axi_wstrb),
.M_AXI_WVALID (m_axi_wvalid),
.M_AXI_WREADY (m_axi_wready),
.M_AXI_BRESP (m_axi_bresp),
.M_AXI_BVALID (m_axi_bvalid),
.M_AXI_BREADY (m_axi_bready),
.M_AXI_ARADDR (m_axi_araddr),
.M_AXI_ARPROT (m_axi_arprot),
.M_AXI_ARVALID (m_axi_arvalid),
.M_AXI_ARREADY (m_axi_arready),
.M_AXI_RDATA (m_axi_rdata),
.M_AXI_RRESP (m_axi_rresp),
.M_AXI_RVALID (m_axi_rvalid),
.M_AXI_RREADY (m_axi_rready)
);
end
end else if ((C_M_AXI_PROTOCOL == P_AXI3) && (C_S_AXI_PROTOCOL == P_AXI4)) begin : gen_axi4_axi3
axi_protocol_converter_v2_1_axi3_conv #(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_AXI_ARUSER_WIDTH (C_AXI_ARUSER_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH),
.C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_AXI_SUPPORTS_WRITE (C_AXI_SUPPORTS_WRITE),
.C_AXI_SUPPORTS_READ (C_AXI_SUPPORTS_READ),
.C_SUPPORT_SPLITTING ((C_TRANSLATION_MODE == P_CONVERSION) ? 1 : 0)
) axi3_conv_inst (
.ARESETN (aresetn),
.ACLK (aclk),
.S_AXI_AWID (s_axi_awid),
.S_AXI_AWADDR (s_axi_awaddr),
.S_AXI_AWLEN (s_axi_awlen),
.S_AXI_AWSIZE (s_axi_awsize),
.S_AXI_AWBURST (s_axi_awburst),
.S_AXI_AWLOCK (s_axi_awlock),
.S_AXI_AWCACHE (s_axi_awcache),
.S_AXI_AWPROT (s_axi_awprot),
.S_AXI_AWQOS (s_axi_awqos),
.S_AXI_AWUSER (s_axi_awuser),
.S_AXI_AWVALID (s_awvalid_i),
.S_AXI_AWREADY (s_awready_i),
.S_AXI_WDATA (s_axi_wdata),
.S_AXI_WSTRB (s_axi_wstrb),
.S_AXI_WLAST (s_axi_wlast),
.S_AXI_WUSER (s_axi_wuser),
.S_AXI_WVALID (s_wvalid_i),
.S_AXI_WREADY (s_wready_i),
.S_AXI_BID (s_bid_i),
.S_AXI_BRESP (s_bresp_i),
.S_AXI_BUSER (s_buser_i),
.S_AXI_BVALID (s_bvalid_i),
.S_AXI_BREADY (s_bready_i),
.S_AXI_ARID (s_axi_arid),
.S_AXI_ARADDR (s_axi_araddr),
.S_AXI_ARLEN (s_axi_arlen),
.S_AXI_ARSIZE (s_axi_arsize),
.S_AXI_ARBURST (s_axi_arburst),
.S_AXI_ARLOCK (s_axi_arlock),
.S_AXI_ARCACHE (s_axi_arcache),
.S_AXI_ARPROT (s_axi_arprot),
.S_AXI_ARQOS (s_axi_arqos),
.S_AXI_ARUSER (s_axi_aruser),
.S_AXI_ARVALID (s_arvalid_i),
.S_AXI_ARREADY (s_arready_i),
.S_AXI_RID (s_rid_i),
.S_AXI_RDATA (s_rdata_i),
.S_AXI_RRESP (s_rresp_i),
.S_AXI_RLAST (s_rlast_i),
.S_AXI_RUSER (s_ruser_i),
.S_AXI_RVALID (s_rvalid_i),
.S_AXI_RREADY (s_rready_i),
.M_AXI_AWID (m_axi_awid),
.M_AXI_AWADDR (m_axi_awaddr),
.M_AXI_AWLEN (m_axi_awlen),
.M_AXI_AWSIZE (m_axi_awsize),
.M_AXI_AWBURST (m_axi_awburst),
.M_AXI_AWLOCK (m_axi_awlock),
.M_AXI_AWCACHE (m_axi_awcache),
.M_AXI_AWPROT (m_axi_awprot),
.M_AXI_AWQOS (m_axi_awqos),
.M_AXI_AWUSER (m_axi_awuser),
.M_AXI_AWVALID (m_axi_awvalid),
.M_AXI_AWREADY (m_axi_awready),
.M_AXI_WID (m_axi_wid),
.M_AXI_WDATA (m_axi_wdata),
.M_AXI_WSTRB (m_axi_wstrb),
.M_AXI_WLAST (m_axi_wlast),
.M_AXI_WUSER (m_axi_wuser),
.M_AXI_WVALID (m_axi_wvalid),
.M_AXI_WREADY (m_axi_wready),
.M_AXI_BID (m_axi_bid),
.M_AXI_BRESP (m_axi_bresp),
.M_AXI_BUSER (m_axi_buser),
.M_AXI_BVALID (m_axi_bvalid),
.M_AXI_BREADY (m_axi_bready),
.M_AXI_ARID (m_axi_arid),
.M_AXI_ARADDR (m_axi_araddr),
.M_AXI_ARLEN (m_axi_arlen),
.M_AXI_ARSIZE (m_axi_arsize),
.M_AXI_ARBURST (m_axi_arburst),
.M_AXI_ARLOCK (m_axi_arlock),
.M_AXI_ARCACHE (m_axi_arcache),
.M_AXI_ARPROT (m_axi_arprot),
.M_AXI_ARQOS (m_axi_arqos),
.M_AXI_ARUSER (m_axi_aruser),
.M_AXI_ARVALID (m_axi_arvalid),
.M_AXI_ARREADY (m_axi_arready),
.M_AXI_RID (m_axi_rid),
.M_AXI_RDATA (m_axi_rdata),
.M_AXI_RRESP (m_axi_rresp),
.M_AXI_RLAST (m_axi_rlast),
.M_AXI_RUSER (m_axi_ruser),
.M_AXI_RVALID (m_axi_rvalid),
.M_AXI_RREADY (m_axi_rready)
);
assign m_axi_awregion = 0;
assign m_axi_arregion = 0;
end else if ((C_S_AXI_PROTOCOL == P_AXI3) && (C_M_AXI_PROTOCOL == P_AXI4)) begin : gen_axi3_axi4
assign m_axi_awid = s_axi_awid;
assign m_axi_awaddr = s_axi_awaddr;
assign m_axi_awlen = {4'h0, s_axi_awlen[3:0]};
assign m_axi_awsize = s_axi_awsize;
assign m_axi_awburst = s_axi_awburst;
assign m_axi_awlock = s_axi_awlock[0];
assign m_axi_awcache = s_axi_awcache;
assign m_axi_awprot = s_axi_awprot;
assign m_axi_awregion = 4'h0;
assign m_axi_awqos = s_axi_awqos;
assign m_axi_awuser = s_axi_awuser;
assign m_axi_awvalid = s_awvalid_i;
assign s_awready_i = m_axi_awready;
assign m_axi_wid = {C_AXI_ID_WIDTH{1'b0}} ;
assign m_axi_wdata = s_axi_wdata;
assign m_axi_wstrb = s_axi_wstrb;
assign m_axi_wlast = s_axi_wlast;
assign m_axi_wuser = s_axi_wuser;
assign m_axi_wvalid = s_wvalid_i;
assign s_wready_i = m_axi_wready;
assign s_bid_i = m_axi_bid;
assign s_bresp_i = m_axi_bresp;
assign s_buser_i = m_axi_buser;
assign s_bvalid_i = m_axi_bvalid;
assign m_axi_bready = s_bready_i;
assign m_axi_arid = s_axi_arid;
assign m_axi_araddr = s_axi_araddr;
assign m_axi_arlen = {4'h0, s_axi_arlen[3:0]};
assign m_axi_arsize = s_axi_arsize;
assign m_axi_arburst = s_axi_arburst;
assign m_axi_arlock = s_axi_arlock[0];
assign m_axi_arcache = s_axi_arcache;
assign m_axi_arprot = s_axi_arprot;
assign m_axi_arregion = 4'h0;
assign m_axi_arqos = s_axi_arqos;
assign m_axi_aruser = s_axi_aruser;
assign m_axi_arvalid = s_arvalid_i;
assign s_arready_i = m_axi_arready;
assign s_rid_i = m_axi_rid;
assign s_rdata_i = m_axi_rdata;
assign s_rresp_i = m_axi_rresp;
assign s_rlast_i = m_axi_rlast;
assign s_ruser_i = m_axi_ruser;
assign s_rvalid_i = m_axi_rvalid;
assign m_axi_rready = s_rready_i;
end else begin :gen_no_conv
assign m_axi_awid = s_axi_awid;
assign m_axi_awaddr = s_axi_awaddr;
assign m_axi_awlen = s_axi_awlen;
assign m_axi_awsize = s_axi_awsize;
assign m_axi_awburst = s_axi_awburst;
assign m_axi_awlock = s_axi_awlock;
assign m_axi_awcache = s_axi_awcache;
assign m_axi_awprot = s_axi_awprot;
assign m_axi_awregion = s_axi_awregion;
assign m_axi_awqos = s_axi_awqos;
assign m_axi_awuser = s_axi_awuser;
assign m_axi_awvalid = s_awvalid_i;
assign s_awready_i = m_axi_awready;
assign m_axi_wid = s_axi_wid;
assign m_axi_wdata = s_axi_wdata;
assign m_axi_wstrb = s_axi_wstrb;
assign m_axi_wlast = s_axi_wlast;
assign m_axi_wuser = s_axi_wuser;
assign m_axi_wvalid = s_wvalid_i;
assign s_wready_i = m_axi_wready;
assign s_bid_i = m_axi_bid;
assign s_bresp_i = m_axi_bresp;
assign s_buser_i = m_axi_buser;
assign s_bvalid_i = m_axi_bvalid;
assign m_axi_bready = s_bready_i;
assign m_axi_arid = s_axi_arid;
assign m_axi_araddr = s_axi_araddr;
assign m_axi_arlen = s_axi_arlen;
assign m_axi_arsize = s_axi_arsize;
assign m_axi_arburst = s_axi_arburst;
assign m_axi_arlock = s_axi_arlock;
assign m_axi_arcache = s_axi_arcache;
assign m_axi_arprot = s_axi_arprot;
assign m_axi_arregion = s_axi_arregion;
assign m_axi_arqos = s_axi_arqos;
assign m_axi_aruser = s_axi_aruser;
assign m_axi_arvalid = s_arvalid_i;
assign s_arready_i = m_axi_arready;
assign s_rid_i = m_axi_rid;
assign s_rdata_i = m_axi_rdata;
assign s_rresp_i = m_axi_rresp;
assign s_rlast_i = m_axi_rlast;
assign s_ruser_i = m_axi_ruser;
assign s_rvalid_i = m_axi_rvalid;
assign m_axi_rready = s_rready_i;
end
if ((C_TRANSLATION_MODE == P_PROTECTION) &&
(((C_S_AXI_PROTOCOL != P_AXILITE) && (C_M_AXI_PROTOCOL == P_AXILITE)) ||
((C_S_AXI_PROTOCOL == P_AXI4) && (C_M_AXI_PROTOCOL == P_AXI3)))) begin : gen_err_detect
wire e_awvalid;
reg e_awvalid_r;
wire e_arvalid;
reg e_arvalid_r;
wire e_wvalid;
wire e_bvalid;
wire e_rvalid;
reg e_awready;
reg e_arready;
wire e_wready;
reg [C_AXI_ID_WIDTH-1:0] e_awid;
reg [C_AXI_ID_WIDTH-1:0] e_arid;
reg [8-1:0] e_arlen;
wire [C_AXI_ID_WIDTH-1:0] e_bid;
wire [C_AXI_ID_WIDTH-1:0] e_rid;
wire e_rlast;
wire w_err;
wire r_err;
wire busy_aw;
wire busy_w;
wire busy_ar;
wire aw_push;
wire aw_pop;
wire w_pop;
wire ar_push;
wire ar_pop;
reg s_awvalid_pending;
reg s_awvalid_en;
reg s_arvalid_en;
reg s_awready_en;
reg s_arready_en;
reg [4:0] aw_cnt;
reg [4:0] ar_cnt;
reg [4:0] w_cnt;
reg w_borrow;
reg err_busy_w;
reg err_busy_r;
assign w_err = (C_M_AXI_PROTOCOL == P_AXILITE) ? (s_axi_awlen != 0) : ((s_axi_awlen>>4) != 0);
assign r_err = (C_M_AXI_PROTOCOL == P_AXILITE) ? (s_axi_arlen != 0) : ((s_axi_arlen>>4) != 0);
assign s_awvalid_i = s_axi_awvalid & s_awvalid_en & ~w_err;
assign e_awvalid = e_awvalid_r & ~busy_aw & ~busy_w;
assign s_arvalid_i = s_axi_arvalid & s_arvalid_en & ~r_err;
assign e_arvalid = e_arvalid_r & ~busy_ar ;
assign s_wvalid_i = s_axi_wvalid & (busy_w | (s_awvalid_pending & ~w_borrow));
assign e_wvalid = s_axi_wvalid & err_busy_w;
assign s_bready_i = s_axi_bready & busy_aw;
assign s_rready_i = s_axi_rready & busy_ar;
assign s_axi_awready = (s_awready_i & s_awready_en) | e_awready;
assign s_axi_wready = (s_wready_i & (busy_w | (s_awvalid_pending & ~w_borrow))) | e_wready;
assign s_axi_bvalid = (s_bvalid_i & busy_aw) | e_bvalid;
assign s_axi_bid = err_busy_w ? e_bid : s_bid_i;
assign s_axi_bresp = err_busy_w ? P_SLVERR : s_bresp_i;
assign s_axi_buser = err_busy_w ? {C_AXI_BUSER_WIDTH{1'b0}} : s_buser_i;
assign s_axi_arready = (s_arready_i & s_arready_en) | e_arready;
assign s_axi_rvalid = (s_rvalid_i & busy_ar) | e_rvalid;
assign s_axi_rid = err_busy_r ? e_rid : s_rid_i;
assign s_axi_rresp = err_busy_r ? P_SLVERR : s_rresp_i;
assign s_axi_ruser = err_busy_r ? {C_AXI_RUSER_WIDTH{1'b0}} : s_ruser_i;
assign s_axi_rdata = err_busy_r ? {C_AXI_DATA_WIDTH{1'b0}} : s_rdata_i;
assign s_axi_rlast = err_busy_r ? e_rlast : s_rlast_i;
assign busy_aw = (aw_cnt != 0);
assign busy_w = (w_cnt != 0);
assign busy_ar = (ar_cnt != 0);
assign aw_push = s_awvalid_i & s_awready_i & s_awready_en;
assign aw_pop = s_bvalid_i & s_bready_i;
assign w_pop = s_wvalid_i & s_wready_i & s_axi_wlast;
assign ar_push = s_arvalid_i & s_arready_i & s_arready_en;
assign ar_pop = s_rvalid_i & s_rready_i & s_rlast_i;
always @(posedge aclk) begin
if (~aresetn) begin
s_awvalid_en <= 1'b0;
s_arvalid_en <= 1'b0;
s_awready_en <= 1'b0;
s_arready_en <= 1'b0;
e_awvalid_r <= 1'b0;
e_arvalid_r <= 1'b0;
e_awready <= 1'b0;
e_arready <= 1'b0;
aw_cnt <= 0;
w_cnt <= 0;
ar_cnt <= 0;
err_busy_w <= 1'b0;
err_busy_r <= 1'b0;
w_borrow <= 1'b0;
s_awvalid_pending <= 1'b0;
end else begin
e_awready <= 1'b0; // One-cycle pulse
if (e_bvalid & s_axi_bready) begin
s_awvalid_en <= 1'b1;
s_awready_en <= 1'b1;
err_busy_w <= 1'b0;
end else if (e_awvalid) begin
e_awvalid_r <= 1'b0;
err_busy_w <= 1'b1;
end else if (s_axi_awvalid & w_err & ~e_awvalid_r & ~err_busy_w) begin
e_awvalid_r <= 1'b1;
e_awready <= ~(s_awready_i & s_awvalid_en); // 1-cycle pulse if awready not already asserted
s_awvalid_en <= 1'b0;
s_awready_en <= 1'b0;
end else if ((&aw_cnt) | (&w_cnt) | aw_push) begin
s_awvalid_en <= 1'b0;
s_awready_en <= 1'b0;
end else if (~err_busy_w & ~e_awvalid_r & ~(s_axi_awvalid & w_err)) begin
s_awvalid_en <= 1'b1;
s_awready_en <= 1'b1;
end
if (aw_push & ~aw_pop) begin
aw_cnt <= aw_cnt + 1;
end else if (~aw_push & aw_pop & (|aw_cnt)) begin
aw_cnt <= aw_cnt - 1;
end
if (aw_push) begin
if (~w_pop & ~w_borrow) begin
w_cnt <= w_cnt + 1;
end
w_borrow <= 1'b0;
end else if (~aw_push & w_pop) begin
if (|w_cnt) begin
w_cnt <= w_cnt - 1;
end else begin
w_borrow <= 1'b1;
end
end
s_awvalid_pending <= s_awvalid_i & ~s_awready_i;
e_arready <= 1'b0; // One-cycle pulse
if (e_rvalid & s_axi_rready & e_rlast) begin
s_arvalid_en <= 1'b1;
s_arready_en <= 1'b1;
err_busy_r <= 1'b0;
end else if (e_arvalid) begin
e_arvalid_r <= 1'b0;
err_busy_r <= 1'b1;
end else if (s_axi_arvalid & r_err & ~e_arvalid_r & ~err_busy_r) begin
e_arvalid_r <= 1'b1;
e_arready <= ~(s_arready_i & s_arvalid_en); // 1-cycle pulse if arready not already asserted
s_arvalid_en <= 1'b0;
s_arready_en <= 1'b0;
end else if ((&ar_cnt) | ar_push) begin
s_arvalid_en <= 1'b0;
s_arready_en <= 1'b0;
end else if (~err_busy_r & ~e_arvalid_r & ~(s_axi_arvalid & r_err)) begin
s_arvalid_en <= 1'b1;
s_arready_en <= 1'b1;
end
if (ar_push & ~ar_pop) begin
ar_cnt <= ar_cnt + 1;
end else if (~ar_push & ar_pop & (|ar_cnt)) begin
ar_cnt <= ar_cnt - 1;
end
end
end
always @(posedge aclk) begin
if (s_axi_awvalid & ~err_busy_w & ~e_awvalid_r ) begin
e_awid <= s_axi_awid;
end
if (s_axi_arvalid & ~err_busy_r & ~e_arvalid_r ) begin
e_arid <= s_axi_arid;
e_arlen <= s_axi_arlen;
end
end
axi_protocol_converter_v2_1_decerr_slave #
(
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_AXI_PROTOCOL (C_S_AXI_PROTOCOL),
.C_RESP (P_SLVERR),
.C_IGNORE_ID (C_IGNORE_ID)
)
decerr_slave_inst
(
.ACLK (aclk),
.ARESETN (aresetn),
.S_AXI_AWID (e_awid),
.S_AXI_AWVALID (e_awvalid),
.S_AXI_AWREADY (),
.S_AXI_WLAST (s_axi_wlast),
.S_AXI_WVALID (e_wvalid),
.S_AXI_WREADY (e_wready),
.S_AXI_BID (e_bid),
.S_AXI_BRESP (),
.S_AXI_BUSER (),
.S_AXI_BVALID (e_bvalid),
.S_AXI_BREADY (s_axi_bready),
.S_AXI_ARID (e_arid),
.S_AXI_ARLEN (e_arlen),
.S_AXI_ARVALID (e_arvalid),
.S_AXI_ARREADY (),
.S_AXI_RID (e_rid),
.S_AXI_RDATA (),
.S_AXI_RRESP (),
.S_AXI_RUSER (),
.S_AXI_RLAST (e_rlast),
.S_AXI_RVALID (e_rvalid),
.S_AXI_RREADY (s_axi_rready)
);
end else begin : gen_no_err_detect
assign s_awvalid_i = s_axi_awvalid;
assign s_arvalid_i = s_axi_arvalid;
assign s_wvalid_i = s_axi_wvalid;
assign s_bready_i = s_axi_bready;
assign s_rready_i = s_axi_rready;
assign s_axi_awready = s_awready_i;
assign s_axi_wready = s_wready_i;
assign s_axi_bvalid = s_bvalid_i;
assign s_axi_bid = s_bid_i;
assign s_axi_bresp = s_bresp_i;
assign s_axi_buser = s_buser_i;
assign s_axi_arready = s_arready_i;
assign s_axi_rvalid = s_rvalid_i;
assign s_axi_rid = s_rid_i;
assign s_axi_rresp = s_rresp_i;
assign s_axi_ruser = s_ruser_i;
assign s_axi_rdata = s_rdata_i;
assign s_axi_rlast = s_rlast_i;
end // gen_err_detect
endgenerate
endmodule
`default_nettype wire
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Embedded Memory ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Embedded Memory . ////
//// ////
//// To Do: ////
//// - QMEM and IC/DC muxes can be removed except for cycstb ////
//// (now are is there for easier debugging) ////
//// - currently arbitration is slow and stores take 2 clocks ////
//// (final debugged version will be faster) ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2003 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_qmem_top.v,v $
// Revision 1.1 2006-12-21 16:46:58 vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.3 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.2 2004/04/05 08:40:26 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.1.2.4 2004/01/11 22:45:46 andreje
// Separate instruction and data QMEM decoders, QMEM acknowledge and byte-select added
//
// Revision 1.1.2.3 2003/12/17 13:36:58 simons
// Qmem mbist signals fixed.
//
// Revision 1.1.2.2 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.1.2.1 2003/07/08 15:45:26 lampret
// Added embedded memory QMEM.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
`define OR1200_QMEMFSM_IDLE 3'd0
`define OR1200_QMEMFSM_STORE 3'd1
`define OR1200_QMEMFSM_LOAD 3'd2
`define OR1200_QMEMFSM_FETCH 3'd3
//
// Embedded memory
//
module or1200_qmem_top(
// Rst, clk and clock control
clk, rst,
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// QMEM and CPU/IMMU
qmemimmu_adr_i,
qmemimmu_cycstb_i,
qmemimmu_ci_i,
qmemicpu_sel_i,
qmemicpu_tag_i,
qmemicpu_dat_o,
qmemicpu_ack_o,
qmemimmu_rty_o,
qmemimmu_err_o,
qmemimmu_tag_o,
// QMEM and IC
icqmem_adr_o,
icqmem_cycstb_o,
icqmem_ci_o,
icqmem_sel_o,
icqmem_tag_o,
icqmem_dat_i,
icqmem_ack_i,
icqmem_rty_i,
icqmem_err_i,
icqmem_tag_i,
// QMEM and CPU/DMMU
qmemdmmu_adr_i,
qmemdmmu_cycstb_i,
qmemdmmu_ci_i,
qmemdcpu_we_i,
qmemdcpu_sel_i,
qmemdcpu_tag_i,
qmemdcpu_dat_i,
qmemdcpu_dat_o,
qmemdcpu_ack_o,
qmemdcpu_rty_o,
qmemdmmu_err_o,
qmemdmmu_tag_o,
// QMEM and DC
dcqmem_adr_o, dcqmem_cycstb_o, dcqmem_ci_o,
dcqmem_we_o, dcqmem_sel_o, dcqmem_tag_o, dcqmem_dat_o,
dcqmem_dat_i, dcqmem_ack_i, dcqmem_rty_i, dcqmem_err_i, dcqmem_tag_i
);
parameter dw = `OR1200_OPERAND_WIDTH;
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// QMEM and CPU/IMMU
//
input [31:0] qmemimmu_adr_i;
input qmemimmu_cycstb_i;
input qmemimmu_ci_i;
input [3:0] qmemicpu_sel_i;
input [3:0] qmemicpu_tag_i;
output [31:0] qmemicpu_dat_o;
output qmemicpu_ack_o;
output qmemimmu_rty_o;
output qmemimmu_err_o;
output [3:0] qmemimmu_tag_o;
//
// QMEM and IC
//
output [31:0] icqmem_adr_o;
output icqmem_cycstb_o;
output icqmem_ci_o;
output [3:0] icqmem_sel_o;
output [3:0] icqmem_tag_o;
input [31:0] icqmem_dat_i;
input icqmem_ack_i;
input icqmem_rty_i;
input icqmem_err_i;
input [3:0] icqmem_tag_i;
//
// QMEM and CPU/DMMU
//
input [31:0] qmemdmmu_adr_i;
input qmemdmmu_cycstb_i;
input qmemdmmu_ci_i;
input qmemdcpu_we_i;
input [3:0] qmemdcpu_sel_i;
input [3:0] qmemdcpu_tag_i;
input [31:0] qmemdcpu_dat_i;
output [31:0] qmemdcpu_dat_o;
output qmemdcpu_ack_o;
output qmemdcpu_rty_o;
output qmemdmmu_err_o;
output [3:0] qmemdmmu_tag_o;
//
// QMEM and DC
//
output [31:0] dcqmem_adr_o;
output dcqmem_cycstb_o;
output dcqmem_ci_o;
output dcqmem_we_o;
output [3:0] dcqmem_sel_o;
output [3:0] dcqmem_tag_o;
output [dw-1:0] dcqmem_dat_o;
input [dw-1:0] dcqmem_dat_i;
input dcqmem_ack_i;
input dcqmem_rty_i;
input dcqmem_err_i;
input [3:0] dcqmem_tag_i;
`ifdef OR1200_QMEM_IMPLEMENTED
//
// Internal regs and wires
//
wire iaddr_qmem_hit;
wire daddr_qmem_hit;
reg [2:0] state;
reg qmem_dack;
reg qmem_iack;
wire [31:0] qmem_di;
wire [31:0] qmem_do;
wire qmem_en;
wire qmem_we;
`ifdef OR1200_QMEM_BSEL
wire [3:0] qmem_sel;
`endif
wire [31:0] qmem_addr;
`ifdef OR1200_QMEM_ACK
wire qmem_ack;
`else
wire qmem_ack = 1'b1;
`endif
//
// QMEM and CPU/IMMU
//
assign qmemicpu_dat_o = qmem_iack ? qmem_do : icqmem_dat_i;
assign qmemicpu_ack_o = qmem_iack ? 1'b1 : icqmem_ack_i;
assign qmemimmu_rty_o = qmem_iack ? 1'b0 : icqmem_rty_i;
assign qmemimmu_err_o = qmem_iack ? 1'b0 : icqmem_err_i;
assign qmemimmu_tag_o = qmem_iack ? 4'h0 : icqmem_tag_i;
//
// QMEM and IC
//
assign icqmem_adr_o = iaddr_qmem_hit ? 32'h0000_0000 : qmemimmu_adr_i;
assign icqmem_cycstb_o = iaddr_qmem_hit ? 1'b0 : qmemimmu_cycstb_i;
assign icqmem_ci_o = iaddr_qmem_hit ? 1'b0 : qmemimmu_ci_i;
assign icqmem_sel_o = iaddr_qmem_hit ? 4'h0 : qmemicpu_sel_i;
assign icqmem_tag_o = iaddr_qmem_hit ? 4'h0 : qmemicpu_tag_i;
//
// QMEM and CPU/DMMU
//
assign qmemdcpu_dat_o = daddr_qmem_hit ? qmem_do : dcqmem_dat_i;
assign qmemdcpu_ack_o = daddr_qmem_hit ? qmem_dack : dcqmem_ack_i;
assign qmemdcpu_rty_o = daddr_qmem_hit ? ~qmem_dack : dcqmem_rty_i;
assign qmemdmmu_err_o = daddr_qmem_hit ? 1'b0 : dcqmem_err_i;
assign qmemdmmu_tag_o = daddr_qmem_hit ? 4'h0 : dcqmem_tag_i;
//
// QMEM and DC
//
assign dcqmem_adr_o = daddr_qmem_hit ? 32'h0000_0000 : qmemdmmu_adr_i;
assign dcqmem_cycstb_o = daddr_qmem_hit ? 1'b0 : qmemdmmu_cycstb_i;
assign dcqmem_ci_o = daddr_qmem_hit ? 1'b0 : qmemdmmu_ci_i;
assign dcqmem_we_o = daddr_qmem_hit ? 1'b0 : qmemdcpu_we_i;
assign dcqmem_sel_o = daddr_qmem_hit ? 4'h0 : qmemdcpu_sel_i;
assign dcqmem_tag_o = daddr_qmem_hit ? 4'h0 : qmemdcpu_tag_i;
assign dcqmem_dat_o = daddr_qmem_hit ? 32'h0000_0000 : qmemdcpu_dat_i;
//
// Address comparison whether QMEM was hit
//
`ifdef OR1200_QMEM_IADDR
assign iaddr_qmem_hit = (qmemimmu_adr_i & `OR1200_QMEM_IMASK) == `OR1200_QMEM_IADDR;
`else
assign iaddr_qmem_hit = 1'b0;
`endif
`ifdef OR1200_QMEM_DADDR
assign daddr_qmem_hit = (qmemdmmu_adr_i & `OR1200_QMEM_DMASK) == `OR1200_QMEM_DADDR;
`else
assign daddr_qmem_hit = 1'b0;
`endif
//
//
//
assign qmem_en = iaddr_qmem_hit & qmemimmu_cycstb_i | daddr_qmem_hit & qmemdmmu_cycstb_i;
assign qmem_we = qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i;
`ifdef OR1200_QMEM_BSEL
assign qmem_sel = (qmemdmmu_cycstb_i & daddr_qmem_hit) ? qmemdcpu_sel_i : qmemicpu_sel_i;
`endif
assign qmem_di = qmemdcpu_dat_i;
assign qmem_addr = (qmemdmmu_cycstb_i & daddr_qmem_hit) ? qmemdmmu_adr_i : qmemimmu_adr_i;
//
// QMEM control FSM
//
always @(posedge rst or posedge clk)
if (rst) begin
state <= #1 `OR1200_QMEMFSM_IDLE;
qmem_dack <= #1 1'b0;
qmem_iack <= #1 1'b0;
end
else case (state) // synopsys parallel_case
`OR1200_QMEMFSM_IDLE: begin
if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i & qmem_ack) begin
state <= #1 `OR1200_QMEMFSM_STORE;
qmem_dack <= #1 1'b1;
qmem_iack <= #1 1'b0;
end
else if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmem_ack) begin
state <= #1 `OR1200_QMEMFSM_LOAD;
qmem_dack <= #1 1'b1;
qmem_iack <= #1 1'b0;
end
else if (qmemimmu_cycstb_i & iaddr_qmem_hit & qmem_ack) begin
state <= #1 `OR1200_QMEMFSM_FETCH;
qmem_iack <= #1 1'b1;
qmem_dack <= #1 1'b0;
end
end
`OR1200_QMEMFSM_STORE: begin
if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i & qmem_ack) begin
state <= #1 `OR1200_QMEMFSM_STORE;
qmem_dack <= #1 1'b1;
qmem_iack <= #1 1'b0;
end
else if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmem_ack) begin
state <= #1 `OR1200_QMEMFSM_LOAD;
qmem_dack <= #1 1'b1;
qmem_iack <= #1 1'b0;
end
else if (qmemimmu_cycstb_i & iaddr_qmem_hit & qmem_ack) begin
state <= #1 `OR1200_QMEMFSM_FETCH;
qmem_iack <= #1 1'b1;
qmem_dack <= #1 1'b0;
end
else begin
state <= #1 `OR1200_QMEMFSM_IDLE;
qmem_dack <= #1 1'b0;
qmem_iack <= #1 1'b0;
end
end
`OR1200_QMEMFSM_LOAD: begin
if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i & qmem_ack) begin
state <= #1 `OR1200_QMEMFSM_STORE;
qmem_dack <= #1 1'b1;
qmem_iack <= #1 1'b0;
end
else if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmem_ack) begin
state <= #1 `OR1200_QMEMFSM_LOAD;
qmem_dack <= #1 1'b1;
qmem_iack <= #1 1'b0;
end
else if (qmemimmu_cycstb_i & iaddr_qmem_hit & qmem_ack) begin
state <= #1 `OR1200_QMEMFSM_FETCH;
qmem_iack <= #1 1'b1;
qmem_dack <= #1 1'b0;
end
else begin
state <= #1 `OR1200_QMEMFSM_IDLE;
qmem_dack <= #1 1'b0;
qmem_iack <= #1 1'b0;
end
end
`OR1200_QMEMFSM_FETCH: begin
if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmemdcpu_we_i & qmem_ack) begin
state <= #1 `OR1200_QMEMFSM_STORE;
qmem_dack <= #1 1'b1;
qmem_iack <= #1 1'b0;
end
else if (qmemdmmu_cycstb_i & daddr_qmem_hit & qmem_ack) begin
state <= #1 `OR1200_QMEMFSM_LOAD;
qmem_dack <= #1 1'b1;
qmem_iack <= #1 1'b0;
end
else if (qmemimmu_cycstb_i & iaddr_qmem_hit & qmem_ack) begin
state <= #1 `OR1200_QMEMFSM_FETCH;
qmem_iack <= #1 1'b1;
qmem_dack <= #1 1'b0;
end
else begin
state <= #1 `OR1200_QMEMFSM_IDLE;
qmem_dack <= #1 1'b0;
qmem_iack <= #1 1'b0;
end
end
default: begin
state <= #1 `OR1200_QMEMFSM_IDLE;
qmem_dack <= #1 1'b0;
qmem_iack <= #1 1'b0;
end
endcase
//
// Instantiation of embedded memory
//
or1200_spram_2048x32 or1200_qmem_ram(
.clk(clk),
.rst(rst),
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.addr(qmem_addr[12:2]),
`ifdef OR1200_QMEM_BSEL
.sel(qmem_sel),
`endif
`ifdef OR1200_QMEM_ACK
.ack(qmem_ack),
`endif
.ce(qmem_en),
.we(qmem_we),
.oe(1'b1),
.di(qmem_di),
.doq(qmem_do)
);
`else // OR1200_QMEM_IMPLEMENTED
//
// QMEM and CPU/IMMU
//
assign qmemicpu_dat_o = icqmem_dat_i;
assign qmemicpu_ack_o = icqmem_ack_i;
assign qmemimmu_rty_o = icqmem_rty_i;
assign qmemimmu_err_o = icqmem_err_i;
assign qmemimmu_tag_o = icqmem_tag_i;
//
// QMEM and IC
//
assign icqmem_adr_o = qmemimmu_adr_i;
assign icqmem_cycstb_o = qmemimmu_cycstb_i;
assign icqmem_ci_o = qmemimmu_ci_i;
assign icqmem_sel_o = qmemicpu_sel_i;
assign icqmem_tag_o = qmemicpu_tag_i;
//
// QMEM and CPU/DMMU
//
assign qmemdcpu_dat_o = dcqmem_dat_i;
assign qmemdcpu_ack_o = dcqmem_ack_i;
assign qmemdcpu_rty_o = dcqmem_rty_i;
assign qmemdmmu_err_o = dcqmem_err_i;
assign qmemdmmu_tag_o = dcqmem_tag_i;
//
// QMEM and DC
//
assign dcqmem_adr_o = qmemdmmu_adr_i;
assign dcqmem_cycstb_o = qmemdmmu_cycstb_i;
assign dcqmem_ci_o = qmemdmmu_ci_i;
assign dcqmem_we_o = qmemdcpu_we_i;
assign dcqmem_sel_o = qmemdcpu_sel_i;
assign dcqmem_tag_o = qmemdcpu_tag_i;
assign dcqmem_dat_o = qmemdcpu_dat_i;
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.91
// \ \ Application: MIG
// / / Filename: phy_top.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 07:18:04 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
//Purpose:
// Top-level for memory physical layer (PHY) interface
// NOTES:
// 1. Need to support multiple copies of CS outputs
// 2. DFI_DRAM_CKE_DISABLE not supported
//
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: phy_top.v,v 1.1 2011/06/02 07:18:04 mishra Exp $
**$Date: 2011/06/02 07:18:04 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_v3_9/data/dlib/virtex6/ddr3_sdram/verilog/rtl/phy/phy_top.v,v $
******************************************************************************/
`timescale 1ps/1ps
(* X_CORE_INFO = "mig_v3_91_ddr3_V6, Coregen 13.4" , CORE_GENERATION_INFO = "ddr3_V6_phy,mig_v3_91,{LANGUAGE=Verilog, SYNTHESIS_TOOL=ISE, LEVEL=PHY, AXI_ENABLE=0, NO_OF_CONTROLLERS=1, INTERFACE_TYPE=DDR3, CLK_PERIOD=2500, MEMORY_TYPE=SODIMM, MEMORY_PART=mt4jsf12864hz-1g4, DQ_WIDTH=64, ECC=OFF, DATA_MASK=1, BURST_MODE=8, BURST_TYPE=SEQ, OUTPUT_DRV=HIGH, RTT_NOM=60, REFCLK_FREQ=200, MMCM_ADV_BANDWIDTH=MMCM_ADV_BANDWIDTH, CLKFBOUT_MULT_F=6, CLKOUT_DIVIDE=3, DEBUG_PORT=ON, IODELAY_HP_MODE=ON, INTERNAL_VREF=0, DCI_INOUTS=1, CLASS_ADDR=II, INPUT_CLK_TYPE=DIFFERENTIAL}" *)
module phy_top #
(
parameter TCQ = 100,
parameter nCK_PER_CLK = 2, // # of memory clocks per CLK
parameter CLK_PERIOD = 3333, // Internal clock period (in ps)
parameter REFCLK_FREQ = 300.0, // IODELAY Reference Clock freq (MHz)
parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2"
// Slot Conifg parameters
parameter [7:0] SLOT_0_CONFIG = 8'b0000_0001,
parameter [7:0] SLOT_1_CONFIG = 8'b0000_0000,
// DRAM bus widths
parameter BANK_WIDTH = 2, // # of bank bits
parameter CK_WIDTH = 1, // # of CK/CK# outputs to memory
parameter COL_WIDTH = 10, // column address width
parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank
parameter DQ_CNT_WIDTH = 6, // = ceil(log2(DQ_WIDTH))
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DM_WIDTH = 8, // # of DM (data mask)
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter ROW_WIDTH = 14, // DRAM address bus width
parameter RANK_WIDTH = 1, // log2(CS_WIDTH)
parameter CS_WIDTH = 1, // # of DRAM ranks
parameter CKE_WIDTH = 1, // # of cke outputs
parameter CAL_WIDTH = "HALF", // # of DRAM ranks to be calibrated
// CAL_WIDTH = CS_WIDTH when "FULL"
// CAL_WIDTH = CS_WIDTH/2 when "HALF"
// calibration Address. The address given below will be used for calibration
// read and write operations.
parameter CALIB_ROW_ADD = 16'h0000,// Calibration row address
parameter CALIB_COL_ADD = 12'h000, // Calibration column address
parameter CALIB_BA_ADD = 3'h0, // Calibration bank address
// DRAM mode settings
parameter AL = "0", // Additive Latency option
parameter BURST_MODE = "8", // Burst length
parameter BURST_TYPE = "SEQ", // Burst type
parameter nAL = 0, // Additive latency (in clk cyc)
parameter nCL = 5, // Read CAS latency (in clk cyc)
parameter nCWL = 5, // Write CAS latency (in clk cyc)
parameter tRFC = 110000, // Refresh-to-command delay
parameter OUTPUT_DRV = "HIGH", // DRAM reduced output drive option
parameter REG_CTRL = "ON", // "ON" for registered DIMM
parameter RTT_NOM = "60", // ODT Nominal termination value
parameter RTT_WR = "60", // ODT Write termination value
parameter WRLVL = "OFF", // Enable write leveling
// Phase Detector/Read Leveling options
parameter PHASE_DETECT = "OFF", // Enable read phase detector
parameter PD_TAP_REQ = 0, // # of IODELAY taps reserved for PD
parameter PD_MSB_SEL = 8, // # of bits in PD response cntr
parameter PD_DQS0_ONLY = "ON", // Enable use of DQS[0] only for
// phase detector
parameter PD_LHC_WIDTH = 16, // sampling averaging cntr widths
parameter PD_CALIB_MODE = "PARALLEL", // parallel/seq PD calibration
// IODELAY/BUFFER options
parameter IBUF_LPWR_MODE = "OFF", // Input buffer low power mode
parameter IODELAY_HP_MODE = "ON", // IODELAY High Performance Mode
parameter IODELAY_GRP = "IODELAY_MIG", // May be assigned unique name
// when mult IP cores in design
// Pin-out related parameters
parameter nDQS_COL0 = DQS_WIDTH, // # DQS groups in I/O column #1
parameter nDQS_COL1 = 0, // # DQS groups in I/O column #2
parameter nDQS_COL2 = 0, // # DQS groups in I/O column #3
parameter nDQS_COL3 = 0, // # DQS groups in I/O column #4
parameter DQS_LOC_COL0 = 144'h11100F0E0D0C0B0A09080706050403020100,
// DQS grps in col #1
parameter DQS_LOC_COL1 = 0, // DQS grps in col #2
parameter DQS_LOC_COL2 = 0, // DQS grps in col #3
parameter DQS_LOC_COL3 = 0, // DQS grps in col #4
parameter USE_DM_PORT = 1, // DM instantation enable
// Simulation /debug options
parameter SIM_BYPASS_INIT_CAL = "OFF",
// Parameter used to force skipping
// or abbreviation of initialization
// and calibration. Overrides
// SIM_INIT_OPTION, SIM_CAL_OPTION,
// and disables various other blocks
parameter SIM_INIT_OPTION = "NONE", // Skip various initialization steps
parameter SIM_CAL_OPTION = "NONE", // Skip various calibration steps
parameter DEBUG_PORT = "OFF" // Enable debug port
)
(
input clk_mem, // Memory clock
input clk, // Internal (logic) clock
input clk_rd_base, // Base capture clock
input rst, // Reset sync'ed to CLK
// Slot present inputs
input [7:0] slot_0_present,
input [7:0] slot_1_present,
// DFI Control/Address
input [ROW_WIDTH-1:0] dfi_address0,
input [ROW_WIDTH-1:0] dfi_address1,
input [BANK_WIDTH-1:0] dfi_bank0,
input [BANK_WIDTH-1:0] dfi_bank1,
input dfi_cas_n0,
input dfi_cas_n1,
input [CKE_WIDTH-1:0] dfi_cke0,
input [CKE_WIDTH-1:0] dfi_cke1,
input [CS_WIDTH*nCS_PER_RANK-1:0] dfi_cs_n0,
input [CS_WIDTH*nCS_PER_RANK-1:0] dfi_cs_n1,
input [CS_WIDTH*nCS_PER_RANK-1:0] dfi_odt0,
input [CS_WIDTH*nCS_PER_RANK-1:0] dfi_odt1,
input dfi_ras_n0,
input dfi_ras_n1,
input dfi_reset_n,
input dfi_we_n0,
input dfi_we_n1,
// DFI Write
input dfi_wrdata_en,
input [4*DQ_WIDTH-1:0] dfi_wrdata,
input [4*(DQ_WIDTH/8)-1:0] dfi_wrdata_mask,
// DFI Read
input dfi_rddata_en,
output [4*DQ_WIDTH-1:0] dfi_rddata,
output dfi_rddata_valid,
// DFI Initialization Status / CLK Disable
input dfi_dram_clk_disable,
output dfi_init_complete,
// sideband signals
input io_config_strobe,
input [RANK_WIDTH:0] io_config,
// DDRx Output Interface
output [CK_WIDTH-1:0] ddr_ck_p,
output [CK_WIDTH-1:0] ddr_ck_n,
output [ROW_WIDTH-1:0] ddr_addr,
output [BANK_WIDTH-1:0] ddr_ba,
output ddr_ras_n,
output ddr_cas_n,
output ddr_we_n,
output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n,
output [CKE_WIDTH-1:0] ddr_cke,
output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_odt,
output ddr_reset_n,
output ddr_parity,
output [DM_WIDTH-1:0] ddr_dm,
inout [DQS_WIDTH-1:0] ddr_dqs_p,
inout [DQS_WIDTH-1:0] ddr_dqs_n,
inout [DQ_WIDTH-1:0] ddr_dq,
// Read Phase Detector Interface
input pd_PSDONE,
output pd_PSEN,
output pd_PSINCDEC,
// Debug Port
// Write leveling logic
input [5*DQS_WIDTH-1:0] dbg_wr_dqs_tap_set,
input [5*DQS_WIDTH-1:0] dbg_wr_dq_tap_set,
input dbg_wr_tap_set_en,
output dbg_wrlvl_start,
output dbg_wrlvl_done,
output dbg_wrlvl_err,
output [DQS_WIDTH-1:0] dbg_wl_dqs_inverted,
output [2*DQS_WIDTH-1:0] dbg_wr_calib_clk_delay,
output [5*DQS_WIDTH-1:0] dbg_wl_odelay_dqs_tap_cnt,
output [5*DQS_WIDTH-1:0] dbg_wl_odelay_dq_tap_cnt,
output [4:0] dbg_tap_cnt_during_wrlvl,
output dbg_wl_edge_detect_valid,
output [DQS_WIDTH-1:0] dbg_rd_data_edge_detect,
// Read leveling logic
output [1:0] dbg_rdlvl_start,
output [1:0] dbg_rdlvl_done,
output [1:0] dbg_rdlvl_err,
output [5*DQS_WIDTH-1:0] dbg_cpt_first_edge_cnt,
output [5*DQS_WIDTH-1:0] dbg_cpt_second_edge_cnt,
output [3*DQS_WIDTH-1:0] dbg_rd_bitslip_cnt,
output [2*DQS_WIDTH-1:0] dbg_rd_clkdly_cnt,
output [4:0] dbg_rd_active_dly,
output [4*DQ_WIDTH-1:0] dbg_rd_data,
// Delay control
input dbg_idel_up_all,
input dbg_idel_down_all,
input dbg_idel_up_cpt,
input dbg_idel_down_cpt,
input dbg_idel_up_rsync,
input dbg_idel_down_rsync,
input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt,
input dbg_sel_all_idel_cpt,
input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_rsync,
input dbg_sel_all_idel_rsync,
output [5*DQS_WIDTH-1:0] dbg_cpt_tap_cnt,
output [19:0] dbg_rsync_tap_cnt,
output [5*DQS_WIDTH-1:0] dbg_dqs_tap_cnt,
output [5*DQS_WIDTH-1:0] dbg_dq_tap_cnt,
// Phase detector
input dbg_pd_off,
input dbg_pd_maintain_off,
input dbg_pd_maintain_0_only,
input dbg_pd_inc_cpt,
input dbg_pd_dec_cpt,
input dbg_pd_inc_dqs,
input dbg_pd_dec_dqs,
input dbg_pd_disab_hyst,
input dbg_pd_disab_hyst_0,
input [3:0] dbg_pd_msb_sel,
input [DQS_CNT_WIDTH-1:0] dbg_pd_byte_sel,
input dbg_inc_rd_fps,
input dbg_dec_rd_fps,
// General debug ports - connect to internal nets as needed
output [255:0] dbg_phy_pd, // Phase Detector
output [255:0] dbg_phy_read, // Read datapath
output [255:0] dbg_phy_rdlvl, // Read leveling calibration
output [255:0] dbg_phy_top // General PHY debug
);
// Parameter used to force skipping or abbreviation of initialization
// and calibration. Overrides SIM_INIT_OPTION, SIM_CAL_OPTION, and
// disables various other blocks depending on the option selected
// This option should only be used during simulation. In the case of
// the "SKIP" option, the testbench used should also not be modeling
// propagation delays.
// Allowable options = {"NONE", "SKIP", "FAST"}
// "NONE" = options determined by the individual parameter settings
// "SKIP" = skip power-up delay, skip calibration for read leveling,
// write leveling, and phase detector. In the case of write
// leveling and the phase detector, this means not instantiating
// those blocks at all.
// "FAST" = skip power-up delay, and calibrate (read leveling, write
// leveling, and phase detector) only using one DQS group, and
// apply the results to all other DQS groups.
localparam SIM_INIT_OPTION_W
= ((SIM_BYPASS_INIT_CAL == "SKIP") ||
(SIM_BYPASS_INIT_CAL == "FAST")) ?
"SKIP_PU_DLY" : SIM_INIT_OPTION;
localparam SIM_CAL_OPTION_W
= (SIM_BYPASS_INIT_CAL == "SKIP") ? "SKIP_CAL" :
((SIM_BYPASS_INIT_CAL == "FAST") ? "FAST_CAL" : SIM_CAL_OPTION);
localparam WRLVL_W
= (SIM_BYPASS_INIT_CAL == "SKIP") ? "OFF" : WRLVL;
localparam PHASE_DETECT_W
= (SIM_BYPASS_INIT_CAL == "SKIP") ? "OFF" : PHASE_DETECT;
// Advance ODELAY of DQ by extra 0.25*tCK (quarter clock cycle) to center
// align DQ and DQS on writes. Round (up or down) value to nearest integer
localparam integer SHIFT_TBY4_TAP
= (CLK_PERIOD + (nCK_PER_CLK*(1000000/(REFCLK_FREQ*64))*2)-1) /
(nCK_PER_CLK*(1000000/(REFCLK_FREQ*64))*4);
// For reg dimm addign one extra cycle of latency for CWL. The new value
// will be passed to phy_write and phy_data_io
localparam CWL_M = (REG_CTRL == "ON") ? nCWL + 1 : nCWL;
// Calculate number of slots in the system
localparam nSLOTS = 1 + (|SLOT_1_CONFIG ? 1 : 0);
// Disable Phase Detector Below 250MHz
localparam USE_PHASE_DETECT = (CLK_PERIOD > 8000) ? "OFF" : PHASE_DETECT_W;
// Param to determine if the configuration is an UDIMM configuration for DDR2
// this parameter is used for advancing the chip select for frequencies above
// 200 MHz.
localparam DDR2_EARLY_CS = ((CLK_PERIOD < 10000) & ( DQ_WIDTH >= 64) &
(CK_WIDTH < 5) & (DRAM_TYPE == "DDR2") &
(REG_CTRL == "OFF"));
reg [2:0] calib_width;
wire [1:0] chip_cnt;
reg [1:0] chip_cnt_r;
reg [1:0] chip_cnt_r1;
wire [DQS_WIDTH-1:0] clk_cpt;
wire [3:0] clk_rsync;
wire [4*DQS_WIDTH-1:0] dfi_rd_dqs;
wire [DQS_WIDTH-1:0] dlyce_cpt;
wire [DQS_WIDTH-1:0] dlyce_pd_cpt;
wire [DQS_WIDTH-1:0] dlyce_rdlvl_cpt;
wire [3:0] dlyce_rdlvl_rsync;
wire [3:0] dlyce_rsync;
wire [DQS_WIDTH-1:0] dlyinc_cpt;
wire [DQS_WIDTH-1:0] dlyinc_pd_cpt;
wire dlyinc_pd_dqs;
wire dlyinc_rdlvl_cpt;
wire dlyinc_rdlvl_rsync;
wire [3:0] dlyinc_rsync;
wire dlyrst_cpt;
wire dlyrst_rsync;
wire [5*DQS_WIDTH-1:0] dlyval_dq;
wire [5*DQS_WIDTH-1:0] dlyval_dqs;
wire [5*DQS_WIDTH-1:0] dlyval_pd_dqs;
wire [5*DQS_WIDTH-1:0] dlyval_rdlvl_dq;
wire [5*DQS_WIDTH-1:0] dlyval_rdlvl_dqs;
wire [5*DQS_WIDTH-1:0] dlyval_wrlvl_dq;
wire [5*DQS_WIDTH-1:0] dlyval_wrlvl_dq_w;
wire [5*DQS_WIDTH-1:0] dlyval_wrlvl_dqs;
wire [5*DQS_WIDTH-1:0] dlyval_wrlvl_dqs_w;
wire [DQS_WIDTH-1:0] dm_ce;
wire [4*DQS_WIDTH-1:0] dq_oe_n;
wire [DQS_WIDTH-1:0] dqs_inv;
reg dqs_oe;
wire [4*DQS_WIDTH-1:0] dqs_oe_n;
wire [(DQS_WIDTH*4)-1:0] dqs_rst;
wire [DQS_WIDTH-1:0] inv_dqs;
wire [(DQ_WIDTH/8)-1:0] mask_data_fall0;
wire [(DQ_WIDTH/8)-1:0] mask_data_fall1;
wire [(DQ_WIDTH/8)-1:0] mask_data_rise0;
wire [(DQ_WIDTH/8)-1:0] mask_data_rise1;
wire pd_cal_done;
wire pd_cal_start;
wire pd_prech_req;
wire [ROW_WIDTH-1:0] phy_address0;
wire [ROW_WIDTH-1:0] phy_address1;
wire [BANK_WIDTH-1:0] phy_bank0;
wire [BANK_WIDTH-1:0] phy_bank1;
wire phy_cas_n0;
wire phy_cas_n1;
wire [CKE_WIDTH-1:0] phy_cke0;
wire [CKE_WIDTH-1:0] phy_cke1;
wire [CS_WIDTH*nCS_PER_RANK-1:0] phy_cs_n0;
wire [CS_WIDTH*nCS_PER_RANK-1:0] phy_cs_n1;
wire phy_init_data_sel;
wire [0:0] phy_io_config;
wire phy_io_config_strobe;
wire [CS_WIDTH*nCS_PER_RANK-1:0] phy_odt0;
wire [CS_WIDTH*nCS_PER_RANK-1:0] phy_odt1;
wire phy_ras_n0;
wire phy_ras_n1;
wire phy_rddata_en;
wire phy_reset_n;
wire phy_we_n0;
wire phy_we_n1;
wire [4*DQ_WIDTH-1:0] phy_wrdata;
wire phy_wrdata_en;
wire [4*(DQ_WIDTH/8)-1:0] phy_wrdata_mask;
wire prech_done;
wire [1:0] rank_cnt;
wire [4:0] rd_active_dly;
wire [2*DQS_WIDTH-1:0] rd_bitslip_cnt;
wire [DQS_WIDTH-1:0] rd_clkdiv_inv;
wire [2*DQS_WIDTH-1:0] rd_clkdly_cnt;
wire [DQ_WIDTH-1:0] rd_data_fall0;
wire [DQ_WIDTH-1:0] rd_data_fall1;
wire [DQ_WIDTH-1:0] rd_data_rise0;
wire [DQ_WIDTH-1:0] rd_data_rise1;
wire [DQS_WIDTH-1:0] rd_dqs_fall0;
wire [DQS_WIDTH-1:0] rd_dqs_fall1;
wire [DQS_WIDTH-1:0] rd_dqs_rise0;
wire [DQS_WIDTH-1:0] rd_dqs_rise1;
wire rdlvl_clkdiv_done;
wire rdlvl_clkdiv_start;
wire [1:0] rdlvl_done;
wire [1:0] rdlvl_err;
wire rdlvl_pat_resume;
wire rdlvl_pat_resume_w;
wire rdlvl_pat_err;
wire [DQS_CNT_WIDTH-1:0] rdlvl_pat_err_cnt;
wire rdlvl_prech_req;
wire [1:0] rdlvl_start;
wire [3:0] rst_rsync;
wire wl_sm_start;
wire [2*DQS_WIDTH-1:0] wr_calib_dly;
wire [DQ_WIDTH-1:0] wr_data_rise0;
wire [DQ_WIDTH-1:0] wr_data_fall0;
wire [DQ_WIDTH-1:0] wr_data_rise1;
wire [DQ_WIDTH-1:0] wr_data_fall1;
wire [2*DQS_WIDTH-1:0] wrcal_dly_w;
wire wrcal_err;
wire wrlvl_active;
wire wrlvl_done;
wire wrlvl_err;
wire wrlvl_start;
//***************************************************************************
// Debug
//***************************************************************************
// Captured data in clk domain
// NOTE: Prior to MIG 3.4, this data was synchronized to CLK_RSYNC domain
// But was never connected beyond PHY_TOP (at the MEM_INTFC level, this
// port is never used, and instead DFI_RDDATA was routed to DBG_RDDATA)
assign dbg_rd_data = dfi_rddata;
// Unused for now - use these as needed to bring up lower level signals
assign dbg_phy_top = 256'd0;
// Write Level and write calibration debug observation ports
assign dbg_wrlvl_start = wrlvl_start;
assign dbg_wrlvl_done = wrlvl_done;
assign dbg_wrlvl_err = wrlvl_err;
assign dbg_wl_dqs_inverted = dqs_inv;
assign dbg_wl_odelay_dqs_tap_cnt = dlyval_wrlvl_dqs;
assign dbg_wl_odelay_dq_tap_cnt = dlyval_wrlvl_dq;
assign dbg_wr_calib_clk_delay = wr_calib_dly;
// Read Level debug observation ports
assign dbg_rdlvl_start = rdlvl_start;
assign dbg_rdlvl_done = rdlvl_done;
assign dbg_rdlvl_err = rdlvl_err;
//***************************************************************************
// Write leveling dependent signals
//***************************************************************************
assign rdlvl_pat_resume_w = (WRLVL_W == "ON") ? rdlvl_pat_resume : 1'b0;
assign dqs_inv = (WRLVL_W == "ON") ? inv_dqs : {DQS_WIDTH{1'b0}};
assign wrcal_dly_w = (WRLVL_W == "ON") ? wr_calib_dly : {2*DQS_WIDTH{1'b0}};
// Rank count (chip_cnt) from phy_init for write bitslip during read leveling
// Rank count (io_config) from MC during normal operation
assign rank_cnt = (rst || (RANK_WIDTH == 0)) ? 2'b00 :
(~dfi_init_complete) ? chip_cnt_r1 :
// io_config[1:0] causes warning with VCS
// io_config[RANK_WIDTH-1:0] causes error with VCS
(RANK_WIDTH == 2) ? io_config[1:0] :
{1'b0, io_config[0]};
always @(posedge clk) begin
chip_cnt_r <= #TCQ chip_cnt;
chip_cnt_r1 <= #TCQ chip_cnt_r;
end
//*****************************************************************
// DETERMINE DQ/DQS output delay values
// 1. If WRLVL disabled: DQS = 0 delay, DQ = 90 degrees delay
// 2. If WRLVL enabled: DQS and DQ delays are determined during
// write leveling
// For multi-rank design the appropriate rank values will be sent to
// phy_write, phy_dly_ctrl, and phy_data_io
//*****************************************************************
generate
genvar offset_i;
for (offset_i = 0; offset_i < DQS_WIDTH;
offset_i = offset_i + 1) begin: gen_offset_tap
if (DEBUG_PORT == "ON") begin: gen_offset_tap_dbg
// Allow debug port to modify the post-write-leveling ODELAY
// values of DQ and DQS. This can be used to measure DQ-DQS
// (as well as tDQSS) timing margin on writes
assign dlyval_wrlvl_dq[5*offset_i+4:5*offset_i]
= (WRLVL_W == "ON") ?
((wrlvl_done && dbg_wr_tap_set_en) ?
dbg_wr_dq_tap_set[5*offset_i+4:5*offset_i] :
dlyval_wrlvl_dq_w[5*offset_i+4:5*offset_i]) :
((dbg_wr_tap_set_en) ?
dbg_wr_dq_tap_set[5*offset_i+4:5*offset_i] :
SHIFT_TBY4_TAP);
assign dlyval_wrlvl_dqs[5*offset_i+4:5*offset_i]
= (WRLVL_W == "ON") ?
((wrlvl_done && dbg_wr_tap_set_en) ?
dbg_wr_dqs_tap_set[5*offset_i+4:5*offset_i] :
dlyval_wrlvl_dqs_w[5*offset_i+4:5*offset_i]) :
((dbg_wr_tap_set_en) ?
dbg_wr_dqs_tap_set[5*offset_i+4:5*offset_i] :
5'b0);
end else begin: gen_offset_tap_nodbg
assign dlyval_wrlvl_dq[5*offset_i+4:5*offset_i]
= (WRLVL_W == "ON") ?
dlyval_wrlvl_dq_w[5*offset_i+4:5*offset_i] :
SHIFT_TBY4_TAP;
assign dlyval_wrlvl_dqs[5*offset_i+4:5*offset_i]
= (WRLVL_W == "ON") ?
dlyval_wrlvl_dqs_w[5*offset_i+4:5*offset_i] :
5'b0;
end
end
endgenerate
//***************************************************************************
// Used for multi-rank case to determine the number of ranks to be calibrated
// The number of ranks to be calibrated can be less than the CS_WIDTH (rank
// width)
// Assumes at least one rank per slot to be calibrated
// If nSLOTS equals 1 slot_1_present input will be ignored
// Assumes CS_WIDTH to be 1, 2, 3, or 4
//***************************************************************************
generate
if (nSLOTS == 1) begin: gen_single_slot
always @ (posedge clk) begin
case ({slot_0_present[0],slot_0_present[1],
slot_0_present[2],slot_0_present[3]})
// single slot quad rank calibration
4'b1111:
if (CAL_WIDTH == "FULL")
calib_width <= #TCQ 3'd4;
else
calib_width <= #TCQ 3'd2;
// single slot dual rank calibration
4'b1100:
if (CAL_WIDTH == "FULL")
calib_width <= #TCQ 3'd2;
else
calib_width <= #TCQ 3'd1;
default:
calib_width <= #TCQ 3'd1;
endcase
end
end else if (nSLOTS == 2) begin: gen_dual_slot
always @ (posedge clk) begin
case ({slot_0_present[0],slot_0_present[1],
slot_1_present[0],slot_1_present[1]})
// two slots single rank per slot CAL_WIDTH ignored since one rank
// per slot must be calibrated
4'b1010:
calib_width <= #TCQ 3'd2;
// two slots single rank in slot0
4'b1000:
calib_width <= #TCQ 3'd1;
// two slots single rank in slot1
4'b0010:
calib_width <= #TCQ 3'd1;
// two slots two ranks per slot calibration
4'b1111:
if (CAL_WIDTH == "FULL")
calib_width <= #TCQ 3'd4;
else
calib_width <= #TCQ 3'd2;
// two slots: 2 ranks in slot0, 1 rank in slot1
4'b1110:
if (CAL_WIDTH == "FULL")
calib_width <= #TCQ 3'd3;
else
calib_width <= #TCQ 3'd2;
// two slots: 2 ranks in slot0, none in slot1
4'b1100:
if (CAL_WIDTH == "FULL")
calib_width <= #TCQ 3'd2;
else
calib_width <= #TCQ 3'd1;
// two slots: 1 rank in slot0, 2 ranks in slot1
4'b1011:
if (CAL_WIDTH == "FULL")
calib_width <= #TCQ 3'd3;
else
calib_width <= #TCQ 3'd2;
// two slots: none in slot0, 2 ranks in slot1
4'b0011:
if (CAL_WIDTH == "FULL")
calib_width <= #TCQ 3'd2;
else
calib_width <= #TCQ 3'd1;
default:
calib_width <= #TCQ 3'd2;
endcase
end
end
endgenerate
//***************************************************************************
// Initialization / Master PHY state logic (overall control during memory
// init, timing leveling)
//***************************************************************************
phy_init #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.CLK_PERIOD (CLK_PERIOD),
.DRAM_TYPE (DRAM_TYPE),
.BANK_WIDTH (BANK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.nCS_PER_RANK (nCS_PER_RANK),
.DQ_WIDTH (DQ_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.CS_WIDTH (CS_WIDTH),
.CKE_WIDTH (CKE_WIDTH),
.CALIB_ROW_ADD (CALIB_ROW_ADD),
.CALIB_COL_ADD (CALIB_COL_ADD),
.CALIB_BA_ADD (CALIB_BA_ADD),
.AL (AL),
.BURST_MODE (BURST_MODE),
.BURST_TYPE (BURST_TYPE),
.nAL (nAL),
.nCL (nCL),
.nCWL (nCWL),
.tRFC (tRFC),
.OUTPUT_DRV (OUTPUT_DRV),
.REG_CTRL (REG_CTRL),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.WRLVL (WRLVL_W),
.PHASE_DETECT (USE_PHASE_DETECT),
.nSLOTS (nSLOTS),
.SIM_INIT_OPTION (SIM_INIT_OPTION_W),
.SIM_CAL_OPTION (SIM_CAL_OPTION_W)
)
u_phy_init
(
.clk (clk),
.rst (rst),
.calib_width (calib_width),
.rdpath_rdy (rdpath_rdy),
.wrlvl_done (wrlvl_done),
.wrlvl_rank_done (wrlvl_rank_done),
.wrlvl_active (wrlvl_active),
.slot_0_present (slot_0_present),
.slot_1_present (slot_1_present),
.rdlvl_done (rdlvl_done),
.rdlvl_start (rdlvl_start),
.rdlvl_clkdiv_done (rdlvl_clkdiv_done),
.rdlvl_clkdiv_start(rdlvl_clkdiv_start),
.rdlvl_prech_req (rdlvl_prech_req),
.rdlvl_resume (rdlvl_pat_resume_w),
.chip_cnt (chip_cnt),
.pd_cal_start (pd_cal_start),
.pd_cal_done (pd_cal_done),
.pd_prech_req (pd_prech_req),
.prech_done (prech_done),
.dfi_init_complete (dfi_init_complete),
.phy_address0 (phy_address0),
.phy_address1 (phy_address1),
.phy_bank0 (phy_bank0),
.phy_bank1 (phy_bank1),
.phy_cas_n0 (phy_cas_n0),
.phy_cas_n1 (phy_cas_n1),
.phy_cke0 (phy_cke0),
.phy_cke1 (phy_cke1),
.phy_cs_n0 (phy_cs_n0),
.phy_cs_n1 (phy_cs_n1),
.phy_init_data_sel (phy_init_data_sel),
.phy_odt0 (phy_odt0),
.phy_odt1 (phy_odt1),
.phy_ras_n0 (phy_ras_n0),
.phy_ras_n1 (phy_ras_n1),
.phy_reset_n (phy_reset_n),
.phy_we_n0 (phy_we_n0),
.phy_we_n1 (phy_we_n1),
.phy_wrdata_en (phy_wrdata_en),
.phy_wrdata (phy_wrdata),
.phy_rddata_en (phy_rddata_en),
.phy_ioconfig (phy_io_config),
.phy_ioconfig_en (phy_io_config_strobe)
);
//*****************************************************************
// Control/Address MUX and IOB logic
//*****************************************************************
phy_control_io #
(
.TCQ (TCQ),
.BANK_WIDTH (BANK_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.nCS_PER_RANK (nCS_PER_RANK),
.CS_WIDTH (CS_WIDTH),
.CKE_WIDTH (CKE_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.WRLVL (WRLVL_W),
.nCWL (CWL_M),
.DRAM_TYPE (DRAM_TYPE),
.REG_CTRL (REG_CTRL),
.REFCLK_FREQ (REFCLK_FREQ),
.IODELAY_HP_MODE (IODELAY_HP_MODE),
.IODELAY_GRP (IODELAY_GRP),
.DDR2_EARLY_CS (DDR2_EARLY_CS)
)
u_phy_control_io
(
.clk_mem (clk_mem),
.clk (clk),
.rst (rst),
.mc_data_sel (phy_init_data_sel),
.dfi_address0 (dfi_address0),
.dfi_address1 (dfi_address1),
.dfi_bank0 (dfi_bank0),
.dfi_bank1 (dfi_bank1),
.dfi_cas_n0 (dfi_cas_n0),
.dfi_cas_n1 (dfi_cas_n1),
.dfi_cke0 (dfi_cke0),
.dfi_cke1 (dfi_cke1),
.dfi_cs_n0 (dfi_cs_n0),
.dfi_cs_n1 (dfi_cs_n1),
.dfi_odt0 (dfi_odt0),
.dfi_odt1 (dfi_odt1),
.dfi_ras_n0 (dfi_ras_n0),
.dfi_ras_n1 (dfi_ras_n1),
.dfi_reset_n (dfi_reset_n),
.dfi_we_n0 (dfi_we_n0),
.dfi_we_n1 (dfi_we_n1),
.phy_address0 (phy_address0),
.phy_address1 (phy_address1),
.phy_bank0 (phy_bank0),
.phy_bank1 (phy_bank1),
.phy_cas_n0 (phy_cas_n0),
.phy_cas_n1 (phy_cas_n1),
.phy_cke0 (phy_cke0),
.phy_cke1 (phy_cke1),
.phy_cs_n0 (phy_cs_n0),
.phy_cs_n1 (phy_cs_n1),
.phy_odt0 (phy_odt0),
.phy_odt1 (phy_odt1),
.phy_ras_n0 (phy_ras_n0),
.phy_ras_n1 (phy_ras_n1),
.phy_reset_n (phy_reset_n),
.phy_we_n0 (phy_we_n0),
.phy_we_n1 (phy_we_n1),
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_ras_n (ddr_ras_n),
.ddr_cas_n (ddr_cas_n),
.ddr_we_n (ddr_we_n),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_odt (ddr_odt),
.ddr_parity (ddr_parity),
.ddr_reset_n (ddr_reset_n)
);
//*****************************************************************
// Memory clock forwarding and feedback
//*****************************************************************
phy_clock_io #
(
.TCQ (TCQ),
.CK_WIDTH (CK_WIDTH),
.WRLVL (WRLVL_W),
.DRAM_TYPE (DRAM_TYPE),
.REFCLK_FREQ (REFCLK_FREQ),
.IODELAY_GRP (IODELAY_GRP)
)
u_phy_clock_io
(
.clk_mem (clk_mem),
.clk (clk),
.rst (rst),
.ddr_ck_p (ddr_ck_p),
.ddr_ck_n (ddr_ck_n)
);
//*****************************************************************
// Data-related IOBs (data, strobe, mask), and regional clock buffers
// Also includes output clock IOBs, and external feedback clock
//*****************************************************************
phy_data_io #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.CLK_PERIOD (CLK_PERIOD),
.DRAM_TYPE (DRAM_TYPE),
.DRAM_WIDTH (DRAM_WIDTH),
.DM_WIDTH (DM_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.nCWL (CWL_M),
.WRLVL (WRLVL_W),
.REFCLK_FREQ (REFCLK_FREQ),
.IBUF_LPWR_MODE (IBUF_LPWR_MODE),
.IODELAY_HP_MODE (IODELAY_HP_MODE),
.IODELAY_GRP (IODELAY_GRP),
.nDQS_COL0 (nDQS_COL0),
.nDQS_COL1 (nDQS_COL1),
.nDQS_COL2 (nDQS_COL2),
.nDQS_COL3 (nDQS_COL3),
.DQS_LOC_COL0 (DQS_LOC_COL0),
.DQS_LOC_COL1 (DQS_LOC_COL1),
.DQS_LOC_COL2 (DQS_LOC_COL2),
.DQS_LOC_COL3 (DQS_LOC_COL3),
.USE_DM_PORT (USE_DM_PORT)
)
u_phy_data_io
(
.clk_mem (clk_mem),
.clk (clk),
.clk_cpt (clk_cpt),
.clk_rsync (clk_rsync),
.rst (rst),
.rst_rsync (rst_rsync),
//IODELAY I/F
.dlyval_dq (dlyval_dq),
.dlyval_dqs (dlyval_dqs),
//Write datapath I/F
.inv_dqs (dqs_inv),
.wr_calib_dly (wrcal_dly_w),
.dqs_oe_n (dqs_oe_n),
.dq_oe_n (dq_oe_n),
.dqs_rst (dqs_rst),
.dm_ce (dm_ce),
.mask_data_rise0 (mask_data_rise0),
.mask_data_fall0 (mask_data_fall0),
.mask_data_rise1 (mask_data_rise1),
.mask_data_fall1 (mask_data_fall1),
.wr_data_rise0 (wr_data_rise0),
.wr_data_fall0 (wr_data_fall0),
.wr_data_rise1 (wr_data_rise1),
.wr_data_fall1 (wr_data_fall1),
//Read datapath I/F
.rd_bitslip_cnt (rd_bitslip_cnt),
.rd_clkdly_cnt (rd_clkdly_cnt),
.rd_clkdiv_inv (rd_clkdiv_inv),
.rd_data_rise0 (rd_data_rise0),
.rd_data_fall0 (rd_data_fall0),
.rd_data_rise1 (rd_data_rise1),
.rd_data_fall1 (rd_data_fall1),
.rd_dqs_rise0 (rd_dqs_rise0),
.rd_dqs_fall0 (rd_dqs_fall0),
.rd_dqs_rise1 (rd_dqs_rise1),
.rd_dqs_fall1 (rd_dqs_fall1),
// DDR3 bus signals
.ddr_dm (ddr_dm),
.ddr_dqs_p (ddr_dqs_p),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dq (ddr_dq),
// Debug signals
.dbg_dqs_tap_cnt (dbg_dqs_tap_cnt),
.dbg_dq_tap_cnt (dbg_dq_tap_cnt)
);
//*****************************************************************
// IODELAY control logic
//*****************************************************************
phy_dly_ctrl #
(
.TCQ (TCQ),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.nCWL (CWL_M),
.REG_CTRL (REG_CTRL),
.WRLVL (WRLVL_W),
.PHASE_DETECT (USE_PHASE_DETECT),
.DRAM_TYPE (DRAM_TYPE),
.nDQS_COL0 (nDQS_COL0),
.nDQS_COL1 (nDQS_COL1),
.nDQS_COL2 (nDQS_COL2),
.nDQS_COL3 (nDQS_COL3),
.DQS_LOC_COL0 (DQS_LOC_COL0),
.DQS_LOC_COL1 (DQS_LOC_COL1),
.DQS_LOC_COL2 (DQS_LOC_COL2),
.DQS_LOC_COL3 (DQS_LOC_COL3),
.DEBUG_PORT (DEBUG_PORT)
)
u_phy_dly_ctrl
(
.clk (clk),
.rst (rst),
.clk_rsync (clk_rsync),
.rst_rsync (rst_rsync),
.wrlvl_done (wrlvl_done),
.rdlvl_done (rdlvl_done),
.pd_cal_done (pd_cal_done),
.mc_data_sel (phy_init_data_sel),
.mc_ioconfig (io_config),
.mc_ioconfig_en (io_config_strobe),
.phy_ioconfig (phy_io_config),
.phy_ioconfig_en (phy_io_config_strobe),
.dqs_oe (dqs_oe),
.dlyval_wrlvl_dqs (dlyval_wrlvl_dqs),
.dlyval_wrlvl_dq (dlyval_wrlvl_dq),
.dlyce_rdlvl_cpt (dlyce_rdlvl_cpt),
.dlyinc_rdlvl_cpt (dlyinc_rdlvl_cpt),
.dlyce_rdlvl_rsync (dlyce_rdlvl_rsync),
.dlyinc_rdlvl_rsync (dlyinc_rdlvl_rsync),
.dlyval_rdlvl_dq (dlyval_rdlvl_dq),
.dlyval_rdlvl_dqs (dlyval_rdlvl_dqs),
.dlyce_pd_cpt (dlyce_pd_cpt),
.dlyinc_pd_cpt (dlyinc_pd_cpt),
.dlyval_pd_dqs (dlyval_pd_dqs),
.dlyval_dqs (dlyval_dqs),
.dlyval_dq (dlyval_dq),
.dlyrst_cpt (dlyrst_cpt),
.dlyce_cpt (dlyce_cpt),
.dlyinc_cpt (dlyinc_cpt),
.dlyrst_rsync (dlyrst_rsync),
.dlyce_rsync (dlyce_rsync),
.dlyinc_rsync (dlyinc_rsync),
.dbg_pd_off (dbg_pd_off)
);
//*****************************************************************
// Write path logic (datapath, tri-state enable)
//*****************************************************************
phy_write #
(
.TCQ (TCQ),
.WRLVL (WRLVL_W),
.DQ_WIDTH (DQ_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.RANK_WIDTH (RANK_WIDTH),
.nCWL (CWL_M),
.REG_CTRL (REG_CTRL)
)
u_phy_write
(
.clk (clk),
.rst (rst),
.mc_data_sel (phy_init_data_sel),
.wrlvl_active (wrlvl_active),
.wrlvl_done (wrlvl_done),
.inv_dqs (dqs_inv),
.wr_calib_dly (wrcal_dly_w),
.dfi_wrdata (dfi_wrdata),
.dfi_wrdata_mask (dfi_wrdata_mask),
.dfi_wrdata_en (dfi_wrdata_en),
.mc_ioconfig_en (io_config_strobe),
.mc_ioconfig (io_config),
.phy_wrdata (phy_wrdata),
.phy_wrdata_en (phy_wrdata_en),
.phy_ioconfig_en (phy_io_config_strobe),
.phy_ioconfig (phy_io_config),
.dm_ce (dm_ce),
.dq_oe_n (dq_oe_n),
.dqs_oe_n (dqs_oe_n),
.dqs_rst (dqs_rst),
.out_oserdes_wc (out_oserdes_wc),
.dqs_wc (),
.dq_wc (),
.wl_sm_start (wl_sm_start),
.wr_lvl_start (wrlvl_start),
.wr_data_rise0 (wr_data_rise0),
.wr_data_fall0 (wr_data_fall0),
.wr_data_rise1 (wr_data_rise1),
.wr_data_fall1 (wr_data_fall1),
.mask_data_rise0 (mask_data_rise0),
.mask_data_fall0 (mask_data_fall0),
.mask_data_rise1 (mask_data_rise1),
.mask_data_fall1 (mask_data_fall1)
);
//***************************************************************************
// Registered version of DQS Output Enable to determine when to switch
// from ODELAY to IDELAY in phy_dly_ctrl module
//***************************************************************************
// SYNTHESIS_NOTE: might need another pipeline stage to meet timing
always @(posedge clk)
dqs_oe <= #TCQ ~(&dqs_oe_n);
//***************************************************************************
// Write-leveling calibration logic
//***************************************************************************
generate
if (WRLVL_W == "ON") begin: mb_wrlvl_inst
phy_wrlvl #
(
.TCQ (TCQ),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.CS_WIDTH (CS_WIDTH),
.CAL_WIDTH (CAL_WIDTH),
.DQS_TAP_CNT_INDEX (5*DQS_WIDTH-1),
.SHIFT_TBY4_TAP (SHIFT_TBY4_TAP),
.SIM_CAL_OPTION (SIM_CAL_OPTION_W)
)
u_phy_wrlvl
(
.clk (clk),
.rst (rst),
.calib_width (calib_width),
.rank_cnt (rank_cnt),
.wr_level_start (wrlvl_start),
.wl_sm_start (wl_sm_start),
.rd_data_rise0 (dfi_rddata[DQ_WIDTH-1:0]),
.rdlvl_done (rdlvl_done),
.wr_level_done (wrlvl_done),
.wrlvl_rank_done (wrlvl_rank_done),
.dlyval_wr_dqs (dlyval_wrlvl_dqs_w),
.dlyval_wr_dq (dlyval_wrlvl_dq_w),
.inv_dqs (inv_dqs),
.rdlvl_error (rdlvl_pat_err),
.rdlvl_err_byte (rdlvl_pat_err_cnt),
.rdlvl_resume (rdlvl_pat_resume),
.wr_calib_dly (wr_calib_dly),
.wrcal_err (wrcal_err),
.wrlvl_err (wrlvl_err),
.dbg_wl_tap_cnt (dbg_tap_cnt_during_wrlvl),
.dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid),
.dbg_rd_data_edge_detect (dbg_rd_data_edge_detect),
.dbg_rd_data_inv_edge_detect (),
.dbg_dqs_count (),
.dbg_wl_state ()
);
end
endgenerate
//*****************************************************************
// Read clock generation and data/control synchronization
//*****************************************************************
phy_read #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.CLK_PERIOD (CLK_PERIOD),
.REFCLK_FREQ (REFCLK_FREQ),
.DQS_WIDTH (DQS_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.IODELAY_GRP (IODELAY_GRP),
.nDQS_COL0 (nDQS_COL0),
.nDQS_COL1 (nDQS_COL1),
.nDQS_COL2 (nDQS_COL2),
.nDQS_COL3 (nDQS_COL3),
.DQS_LOC_COL0 (DQS_LOC_COL0),
.DQS_LOC_COL1 (DQS_LOC_COL1),
.DQS_LOC_COL2 (DQS_LOC_COL2),
.DQS_LOC_COL3 (DQS_LOC_COL3)
)
u_phy_read
(
.clk_mem (clk_mem),
.clk (clk),
.clk_rd_base (clk_rd_base),
.rst (rst),
.dlyrst_cpt (dlyrst_cpt),
.dlyce_cpt (dlyce_cpt),
.dlyinc_cpt (dlyinc_cpt),
.dlyrst_rsync (dlyrst_rsync),
.dlyce_rsync (dlyce_rsync),
.dlyinc_rsync (dlyinc_rsync),
.clk_cpt (clk_cpt),
.clk_rsync (clk_rsync),
.rst_rsync (rst_rsync),
.rdpath_rdy (rdpath_rdy),
.mc_data_sel (phy_init_data_sel),
.rd_active_dly (rd_active_dly),
.rd_data_rise0 (rd_data_rise0),
.rd_data_fall0 (rd_data_fall0),
.rd_data_rise1 (rd_data_rise1),
.rd_data_fall1 (rd_data_fall1),
.rd_dqs_rise0 (rd_dqs_rise0),
.rd_dqs_fall0 (rd_dqs_fall0),
.rd_dqs_rise1 (rd_dqs_rise1),
.rd_dqs_fall1 (rd_dqs_fall1),
.dfi_rddata_en (dfi_rddata_en),
.phy_rddata_en (phy_rddata_en),
.dfi_rddata_valid (dfi_rddata_valid),
.dfi_rddata_valid_phy (dfi_rddata_valid_phy),
.dfi_rddata (dfi_rddata),
.dfi_rd_dqs (dfi_rd_dqs),
.dbg_cpt_tap_cnt (dbg_cpt_tap_cnt),
.dbg_rsync_tap_cnt (dbg_rsync_tap_cnt),
.dbg_phy_read (dbg_phy_read)
);
//***************************************************************************
// Read-leveling calibration logic
//***************************************************************************
phy_rdlvl #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.CLK_PERIOD (CLK_PERIOD),
.REFCLK_FREQ (REFCLK_FREQ),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.nCL (nCL),
.PD_TAP_REQ (PD_TAP_REQ),
.SIM_CAL_OPTION (SIM_CAL_OPTION_W),
.DEBUG_PORT (DEBUG_PORT)
)
u_phy_rdlvl
(
.clk (clk),
.rst (rst),
.rdlvl_start (rdlvl_start),
.rdlvl_clkdiv_start (rdlvl_clkdiv_start),
.rdlvl_rd_active (dfi_rddata_valid_phy),
.rdlvl_done (rdlvl_done),
.rdlvl_clkdiv_done (rdlvl_clkdiv_done),
.rdlvl_err (rdlvl_err),
.rdlvl_prech_req (rdlvl_prech_req),
.prech_done (prech_done),
.rd_data_rise0 (dfi_rddata[DQ_WIDTH-1:0]),
.rd_data_fall0 (dfi_rddata[2*DQ_WIDTH-1:DQ_WIDTH]),
.rd_data_rise1 (dfi_rddata[3*DQ_WIDTH-1:2*DQ_WIDTH]),
.rd_data_fall1 (dfi_rddata[4*DQ_WIDTH-1:3*DQ_WIDTH]),
.dlyce_cpt (dlyce_rdlvl_cpt),
.dlyinc_cpt (dlyinc_rdlvl_cpt),
.dlyce_rsync (dlyce_rdlvl_rsync),
.dlyinc_rsync (dlyinc_rdlvl_rsync),
.dlyval_dq (dlyval_rdlvl_dq),
.dlyval_dqs (dlyval_rdlvl_dqs),
.rd_bitslip_cnt (rd_bitslip_cnt),
.rd_clkdly_cnt (rd_clkdly_cnt),
.rd_active_dly (rd_active_dly),
.rdlvl_pat_resume (rdlvl_pat_resume_w),
.rdlvl_pat_err (rdlvl_pat_err),
.rdlvl_pat_err_cnt (rdlvl_pat_err_cnt),
.rd_clkdiv_inv (rd_clkdiv_inv),
.dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt),
.dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt),
.dbg_rd_bitslip_cnt (dbg_rd_bitslip_cnt),
.dbg_rd_clkdiv_inv (), // connect in future release
.dbg_rd_clkdly_cnt (dbg_rd_clkdly_cnt),
.dbg_rd_active_dly (dbg_rd_active_dly),
.dbg_idel_up_all (dbg_idel_up_all),
.dbg_idel_down_all (dbg_idel_down_all),
.dbg_idel_up_cpt (dbg_idel_up_cpt),
.dbg_idel_down_cpt (dbg_idel_down_cpt),
.dbg_idel_up_rsync (dbg_idel_up_rsync),
.dbg_idel_down_rsync (dbg_idel_down_rsync),
.dbg_sel_idel_cpt (dbg_sel_idel_cpt),
.dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt),
.dbg_sel_idel_rsync (dbg_sel_idel_rsync),
.dbg_sel_all_idel_rsync (dbg_sel_all_idel_rsync),
.dbg_phy_rdlvl (dbg_phy_rdlvl)
);
//***************************************************************************
// Phase Detector: Periodic read-path delay compensation
//***************************************************************************
generate
if (USE_PHASE_DETECT == "ON") begin: gen_enable_pd
phy_pd_top #
(
.TCQ (TCQ),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.PD_LHC_WIDTH (PD_LHC_WIDTH),
.PD_CALIB_MODE (PD_CALIB_MODE),
.PD_MSB_SEL (PD_MSB_SEL),
.PD_DQS0_ONLY (PD_DQS0_ONLY),
.SIM_CAL_OPTION (SIM_CAL_OPTION_W),
.DEBUG_PORT (DEBUG_PORT)
)
u_phy_pd_top
(
.clk (clk),
.rst (rst),
.pd_cal_start (pd_cal_start),
.pd_cal_done (pd_cal_done),
.dfi_init_complete (phy_init_data_sel),
.read_valid (dfi_rddata_valid_phy),
.pd_PSEN (pd_PSEN),
.pd_PSINCDEC (pd_PSINCDEC),
.dlyval_rdlvl_dqs (dlyval_rdlvl_dqs),
.dlyce_pd_cpt (dlyce_pd_cpt),
.dlyinc_pd_cpt (dlyinc_pd_cpt),
.dlyval_pd_dqs (dlyval_pd_dqs),
.rd_dqs_rise0 (dfi_rd_dqs[DQS_WIDTH-1-:DQS_WIDTH]),
.rd_dqs_fall0 (dfi_rd_dqs[2*DQS_WIDTH-1-:DQS_WIDTH]),
.rd_dqs_rise1 (dfi_rd_dqs[3*DQS_WIDTH-1-:DQS_WIDTH]),
.rd_dqs_fall1 (dfi_rd_dqs[4*DQS_WIDTH-1-:DQS_WIDTH]),
.pd_prech_req (pd_prech_req),
.prech_done (prech_done),
.dbg_pd_off (dbg_pd_off),
.dbg_pd_maintain_off (dbg_pd_maintain_off),
.dbg_pd_maintain_0_only (dbg_pd_maintain_0_only),
.dbg_pd_inc_cpt (dbg_pd_inc_cpt),
.dbg_pd_dec_cpt (dbg_pd_dec_cpt),
.dbg_pd_inc_dqs (dbg_pd_inc_dqs),
.dbg_pd_dec_dqs (dbg_pd_dec_dqs),
.dbg_pd_disab_hyst (dbg_pd_disab_hyst),
.dbg_pd_disab_hyst_0 (dbg_pd_disab_hyst_0),
.dbg_pd_msb_sel (dbg_pd_msb_sel),
.dbg_pd_byte_sel (dbg_pd_byte_sel),
.dbg_inc_rd_fps (dbg_inc_rd_fps),
.dbg_dec_rd_fps (dbg_dec_rd_fps),
.dbg_phy_pd (dbg_phy_pd)
);
end else begin: gen_disable_pd_tie_off
// Otherwise if phase detector is not used, tie off all PD-related
// control signals
assign pd_cal_done = 1'b0;
assign pd_prech_req = 1'b0;
assign dlyce_pd_cpt = 'b0;
assign dlyinc_pd_cpt = 'b0;
assign dlyval_pd_dqs = 'b0;
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFSTP_BEHAVIORAL_V
`define SKY130_FD_SC_MS__DFSTP_BEHAVIORAL_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_ms__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dfstp (
Q ,
CLK ,
D ,
SET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire SET ;
reg notifier ;
wire D_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_ms__udp_dff$PS_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( SET_B_delayed === 1'b1 );
assign cond1 = ( SET_B === 1'b1 );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFSTP_BEHAVIORAL_V |
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: read_data_path.v
// /___/ /\ Date Last Modified:
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This is top level of read path and also consist of comparison logic
// for read data.
//Reference:
//Revision History: 11/18 /2011 Fixed a localparam ER_WIDTH bug for QDR2+ case.
// 03/15/2012 Registered error_byte, error_bit to avoid false
// comparison when data_valid_i is deasserted.
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_3_read_data_path #(
parameter TCQ = 100,
parameter START_ADDR = 32'h00000000,
parameter nCK_PER_CLK = 4, // DRAM clock : MC clock
parameter MEM_TYPE = "DDR3",
parameter FAMILY = "VIRTEX6",
parameter BL_WIDTH = 6,
parameter MEM_BURST_LEN = 8,
parameter ADDR_WIDTH = 32,
parameter CMP_DATA_PIPE_STAGES = 3,
parameter DATA_PATTERN = "DGEN_ALL", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
parameter NUM_DQ_PINS = 8,
parameter DWIDTH = nCK_PER_CLK * 2 * NUM_DQ_PINS,
parameter SEL_VICTIM_LINE = 3, // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
parameter MEM_COL_WIDTH = 10,
parameter SIMULATION = "FALSE"
)
(
input clk_i,
input [9:0] rst_i,
input manual_clear_error,
output cmd_rdy_o,
input cmd_valid_i,
input memc_cmd_full_i,
input [31:0] prbs_fseed_i,
input mode_load_i,
input [3:0] vio_instr_mode_value,
input [3:0] data_mode_i,
input [2:0] cmd_sent,
input [5:0] bl_sent ,
input cmd_en_i ,
// input [31:0] m_addr_i,
input [31:0] simple_data0 ,
input [31:0] simple_data1 ,
input [31:0] simple_data2 ,
input [31:0] simple_data3 ,
input [31:0] simple_data4 ,
input [31:0] simple_data5 ,
input [31:0] simple_data6 ,
input [31:0] simple_data7 ,
input [31:0] fixed_data_i,
input [31:0] addr_i,
input [BL_WIDTH-1:0] bl_i,
output data_rdy_o,
input data_valid_i,
input [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] data_i,
output data_error_o, //data_error on user data bus side
output [DWIDTH-1:0] cmp_data_o,
output [DWIDTH-1:0] rd_mdata_o ,
output cmp_data_valid,
output [31:0] cmp_addr_o,
output [5 :0] cmp_bl_o,
output [NUM_DQ_PINS/8 - 1:0] dq_error_bytelane_cmp, // V6: real time compare error byte lane
output [NUM_DQ_PINS/8 - 1:0] cumlative_dq_lane_error_r, // V6: latched error byte lane that occure on
// first error
output reg [NUM_DQ_PINS - 1:0] cumlative_dq_r0_bit_error_r ,
output reg [NUM_DQ_PINS - 1:0] cumlative_dq_f0_bit_error_r ,
output reg [NUM_DQ_PINS - 1:0] cumlative_dq_r1_bit_error_r ,
output reg [NUM_DQ_PINS - 1:0] cumlative_dq_f1_bit_error_r ,
output reg [NUM_DQ_PINS-1:0] dq_r0_bit_error_r,
output reg [NUM_DQ_PINS-1:0] dq_f0_bit_error_r,
output reg [NUM_DQ_PINS-1:0] dq_r1_bit_error_r,
output reg [NUM_DQ_PINS-1:0] dq_f1_bit_error_r,
output reg [NUM_DQ_PINS - 1:0] dq_r0_read_bit_r,
output reg [NUM_DQ_PINS - 1:0] dq_f0_read_bit_r,
output reg [NUM_DQ_PINS - 1:0] dq_r1_read_bit_r,
output reg [NUM_DQ_PINS - 1:0] dq_f1_read_bit_r,
output reg [NUM_DQ_PINS - 1:0] dq_r0_expect_bit_r,
output reg [NUM_DQ_PINS - 1:0] dq_f0_expect_bit_r,
output reg [NUM_DQ_PINS - 1:0] dq_r1_expect_bit_r,
output reg [NUM_DQ_PINS - 1:0] dq_f1_expect_bit_r,
output [31:0] error_addr_o
);
wire gen_rdy;
wire gen_valid;
wire [31:0] gen_addr;
wire [BL_WIDTH-1:0] gen_bl;
wire cmp_rdy;
wire cmp_valid;
wire [31:0] cmp_addr;
wire [5:0] cmp_bl;
reg data_error;
wire [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] cmp_data;
wire [31:0] tg_st_addr_o;
reg [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] cmp_data_r1,cmp_data_r2;
reg last_word_rd;
reg [5:0] bl_counter;
wire cmd_rdy;
wire user_bl_cnt_is_1;
wire data_rdy;
reg [DWIDTH:0] delayed_data;
wire rd_mdata_en;
reg [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] rd_data_r1;
reg [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] rd_data_r2;
reg force_wrcmd_gen;
reg wait_bl_end;
reg wait_bl_end_r1;
reg l_data_error ;
reg u_data_error;
reg v6_data_cmp_valid;
wire [DWIDTH -1 :0] rd_v6_mdata;
reg [DWIDTH -1 :0] cmpdata_r;
wire [DWIDTH -1 :0] rd_mdata;
reg cmp_data_en;
localparam ER_WIDTH = ( MEM_TYPE == "QDR2PLUS" && nCK_PER_CLK == 2) ? (NUM_DQ_PINS*MEM_BURST_LEN)/9 :
( MEM_TYPE != "QDR2PLUS" && nCK_PER_CLK == 2) ? NUM_DQ_PINS/2 : NUM_DQ_PINS;
reg [ER_WIDTH - 1:0] error_byte;
reg [ER_WIDTH - 1:0] error_byte_r1;
reg [NUM_DQ_PINS*nCK_PER_CLK*2 - 1:0] error_bit;
reg [NUM_DQ_PINS*nCK_PER_CLK*2 -1:0] error_bit_r1;
wire [NUM_DQ_PINS-1:0] dq_bit_error;
wire [NUM_DQ_PINS-1:0] cumlative_dq_bit_error_c;
wire [ NUM_DQ_PINS/8-1:0] dq_lane_error;
reg [ NUM_DQ_PINS/8-1:0] dq_lane_error_r1;
reg [ NUM_DQ_PINS/8-1:0] dq_lane_error_r2;
reg [NUM_DQ_PINS-1:0] dq_bit_error_r1;
wire [NUM_DQ_PINS-1:0] cumlative_dq_r0_bit_error_c;
wire [NUM_DQ_PINS-1:0] cumlative_dq_f0_bit_error_c;
wire [NUM_DQ_PINS-1:0] cumlative_dq_r1_bit_error_c;
wire [NUM_DQ_PINS-1:0] cumlative_dq_f1_bit_error_c;
wire [ NUM_DQ_PINS/8-1:0] cum_dq_lane_error_mask;
wire [ NUM_DQ_PINS/8-1:0] cumlative_dq_lane_error_c;
reg [ NUM_DQ_PINS/8-1:0] cumlative_dq_lane_error_reg;
reg [NUM_DQ_PINS - 1:0] dq_r0_read_bit_rdlay1;
reg [NUM_DQ_PINS - 1:0] dq_f0_read_bit_rdlay1;
reg [NUM_DQ_PINS - 1:0] dq_r1_read_bit_rdlay1;
reg [NUM_DQ_PINS - 1:0] dq_f1_read_bit_rdlay1;
reg [NUM_DQ_PINS - 1:0] dq_r0_expect_bit_rdlay1;
reg [NUM_DQ_PINS - 1:0] dq_f0_expect_bit_rdlay1;
reg [NUM_DQ_PINS - 1:0] dq_r1_expect_bit_rdlay1;
reg [NUM_DQ_PINS - 1:0] dq_f1_expect_bit_rdlay1;
wire [NUM_DQ_PINS-1:0] dq_r0_bit_error ;
wire [NUM_DQ_PINS-1:0] dq_f0_bit_error ;
wire [NUM_DQ_PINS-1:0] dq_r1_bit_error ;
wire [NUM_DQ_PINS-1:0] dq_f1_bit_error ;
reg [31:0] error_addr_r1;
reg [31:0] error_addr_r2;
reg [31:0] error_addr_r3;
reg data_valid_r1;
reg data_valid_r2;
wire cmd_start_i;
always @ (posedge clk_i) begin
wait_bl_end_r1 <= #TCQ wait_bl_end;
rd_data_r1 <= #TCQ data_i;
rd_data_r2 <= #TCQ rd_data_r1;
end
reg [7:0] force_wrcmd_timeout_cnts ;
always @ (posedge clk_i) begin
if (rst_i[0])
force_wrcmd_gen <= #TCQ 1'b0;
else if ((wait_bl_end == 1'b0 && wait_bl_end_r1 == 1'b1) || force_wrcmd_timeout_cnts == 8'b11111111)
force_wrcmd_gen <= #TCQ 1'b0;
else if ((cmd_valid_i && bl_i > 16) || wait_bl_end )
force_wrcmd_gen <= #TCQ 1'b1;
end
always @ (posedge clk_i) begin
if (rst_i[0])
force_wrcmd_timeout_cnts <= #TCQ 'b0;
else if (wait_bl_end == 1'b0 && wait_bl_end_r1 == 1'b1)
force_wrcmd_timeout_cnts <= #TCQ 'b0;
else if (force_wrcmd_gen)
force_wrcmd_timeout_cnts <= #TCQ force_wrcmd_timeout_cnts + 1'b1;
end
always @ (posedge clk_i)
if (rst_i[0])
wait_bl_end <= #TCQ 1'b0;
else if (force_wrcmd_timeout_cnts == 8'b11111111)
wait_bl_end <= #TCQ 1'b0;
else if (gen_rdy && gen_valid && gen_bl > 16)
wait_bl_end <= #TCQ 1'b1;
else if (wait_bl_end && user_bl_cnt_is_1)
wait_bl_end <= #TCQ 1'b0;
assign cmd_rdy_o = cmd_rdy;
mig_7series_v2_3_read_posted_fifo #
(
.TCQ (TCQ),
.FAMILY (FAMILY),
.nCK_PER_CLK (nCK_PER_CLK),
.MEM_BURST_LEN (MEM_BURST_LEN),
.ADDR_WIDTH (32),
.BL_WIDTH (BL_WIDTH)
)
read_postedfifo(
.clk_i (clk_i),
.rst_i (rst_i[0]),
.cmd_rdy_o (cmd_rdy ),
.cmd_valid_i (cmd_valid_i ),
.data_valid_i (data_rdy ), // input to
.addr_i (addr_i ),
.bl_i (bl_i ),
.cmd_start_i (cmd_start),
.cmd_sent (cmd_sent),
.bl_sent (bl_sent ),
.cmd_en_i (cmd_en_i),
.memc_cmd_full_i (memc_cmd_full_i),
.gen_valid_o (gen_valid ),
.gen_addr_o (gen_addr ),
.gen_bl_o (gen_bl ),
.rd_mdata_en (rd_mdata_en)
);
mig_7series_v2_3_rd_data_gen #
(
.TCQ (TCQ),
.FAMILY (FAMILY),
.MEM_TYPE (MEM_TYPE),
.BL_WIDTH (BL_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK),
.MEM_BURST_LEN (MEM_BURST_LEN),
.NUM_DQ_PINS (NUM_DQ_PINS),
.SEL_VICTIM_LINE (SEL_VICTIM_LINE),
.START_ADDR (START_ADDR),
.DATA_PATTERN (DATA_PATTERN),
.DWIDTH(DWIDTH),
.COLUMN_WIDTH (MEM_COL_WIDTH)
)
rd_datagen(
.clk_i (clk_i ),
.rst_i (rst_i[4:0]),
.prbs_fseed_i (prbs_fseed_i),
.data_mode_i (data_mode_i ),
.vio_instr_mode_value (vio_instr_mode_value),
.cmd_rdy_o (gen_rdy ),
.cmd_valid_i (gen_valid ),
.mode_load_i (mode_load_i),
.cmd_start_o (cmd_start),
// .m_addr_i (m_addr_i ),
.simple_data0 (simple_data0),
.simple_data1 (simple_data1),
.simple_data2 (simple_data2),
.simple_data3 (simple_data3),
.simple_data4 (simple_data4),
.simple_data5 (simple_data5),
.simple_data6 (simple_data6),
.simple_data7 (simple_data7),
.fixed_data_i (fixed_data_i),
.addr_i (gen_addr ),
.bl_i (gen_bl ),
.user_bl_cnt_is_1_o (user_bl_cnt_is_1),
.data_rdy_i (data_valid_i ), // input to
.data_valid_o (cmp_valid ),
.tg_st_addr_o (tg_st_addr_o),
.data_o (cmp_data )
);
mig_7series_v2_3_afifo #
(
.TCQ (TCQ),
.DSIZE (DWIDTH),
.FIFO_DEPTH (32),
.ASIZE (4),
.SYNC (1) // set the SYNC to 1 because rd_clk = wr_clk to reduce latency
)
rd_mdata_fifo
(
.wr_clk (clk_i),
.rst (rst_i[0]),
.wr_en (data_valid_i),
.wr_data (data_i),
.rd_en (rd_mdata_en),
.rd_clk (clk_i),
.rd_data (rd_v6_mdata),
.full (),
.empty (),
.almost_full ()
);
always @ (posedge clk_i)
begin
// delayed_data <= #TCQ {cmp_valid & data_valid_i,cmp_data};
cmp_data_r1 <= #TCQ cmp_data;
cmp_data_r2 <= #TCQ cmp_data_r1;
end
assign rd_mdata_o = rd_mdata;
assign rd_mdata = (FAMILY == "SPARTAN6") ? rd_data_r1:
(FAMILY == "VIRTEX6" && MEM_BURST_LEN == 4)? rd_v6_mdata:
rd_data_r2;
assign cmp_data_valid = (FAMILY == "SPARTAN6") ? cmp_data_en :
(FAMILY == "VIRTEX6" && MEM_BURST_LEN == 4)? v6_data_cmp_valid :data_valid_i;
assign cmp_data_o = cmp_data_r2;
assign cmp_addr_o = tg_st_addr_o;//gen_addr;
assign cmp_bl_o = gen_bl[5:0];
assign data_rdy_o = data_rdy;
assign data_rdy = cmp_valid & data_valid_i;
always @ (posedge clk_i)
v6_data_cmp_valid <= #TCQ rd_mdata_en;
always @ (posedge clk_i)
cmp_data_en <= #TCQ data_rdy;
genvar i;
generate
if (FAMILY == "SPARTAN6")
begin: gen_error_sp6
always @ (posedge clk_i)
begin
if (cmp_data_en)
l_data_error <= #TCQ (rd_data_r1[DWIDTH/2-1:0] != cmp_data_r1[DWIDTH/2-1:0]);
else
l_data_error <= #TCQ 1'b0;
if (cmp_data_en)
u_data_error <= #TCQ (rd_data_r1[DWIDTH-1:DWIDTH/2] != cmp_data_r1[DWIDTH-1:DWIDTH/2]);
else
u_data_error <= #TCQ 1'b0;
data_error <= #TCQ l_data_error | u_data_error;
//synthesis translate_off
if (data_error)
$display ("ERROR at time %t" , $time);
//synthesis translate_on
end
end
else
// if (FAMILY == "VIRTEX6" )
begin: gen_error_v7
if (nCK_PER_CLK == 2)
begin
if (MEM_TYPE == "QDR2PLUS")
begin: qdr_design
for (i = 0; i < (NUM_DQ_PINS*MEM_BURST_LEN)/9; i = i + 1)
begin: gen_cmp_2
always @ (posedge clk_i)
//synthesis translate_off
if (data_valid_i & (SIMULATION=="TRUE"))
error_byte[i] <= (data_i[9*(i+1)-1:9*i] !== cmp_data[9*(i+1)-1:9*i]) ;
else
//synthesis translate_on
if (data_valid_i)
error_byte[i] <= (data_i[9*(i+1)-1:9*i] != cmp_data[9*(i+1)-1:9*i]) ;
else
error_byte[i] <= 1'b0;
end
for (i = 0; i < NUM_DQ_PINS*MEM_BURST_LEN; i = i + 1)
begin: gen_cmp_bit_2
always @ (posedge clk_i)
//synthesis translate_off
if (data_valid_i & (SIMULATION=="TRUE"))
error_bit[i] <= (data_i[i] !== cmp_data[i]) ;
else
//synthesis translate_on
if (data_valid_i)
error_bit[i] <= (data_i[i] != cmp_data[i]) ;
else
error_bit[i] <= 1'b0;
end
end
else
begin: ddr_design
for (i = 0; i < NUM_DQ_PINS/2; i = i + 1)
begin: gen_cmp_2
always @ (posedge clk_i)
//synthesis translate_off
if (data_valid_i & (SIMULATION=="TRUE"))
error_byte[i] <= (data_i[8*(i+1)-1:8*i] !== cmp_data[8*(i+1)-1:8*i]) ;
else
//synthesis translate_on
if (data_valid_i)
error_byte[i] <= (data_i[8*(i+1)-1:8*i] != cmp_data[8*(i+1)-1:8*i]) ;
else
error_byte[i] <= 1'b0;
end
for (i = 0; i < NUM_DQ_PINS*4; i = i + 1)
begin: gen_cmp_bit_2
always @ (posedge clk_i)
//synthesis translate_off
if (data_valid_i & (SIMULATION=="TRUE"))
error_bit[i] <= ( (data_i[i] !== cmp_data[i]) ) ;
else
//synthesis translate_on
if (data_valid_i)
error_bit[i] <= ( (data_i[i] != cmp_data[i]) ) ;
else
error_bit[i] <= 1'b0;
end
end
end
else //nCK_PER_CLK == 4
begin
for (i = 0; i < NUM_DQ_PINS; i = i + 1)
begin: gen_cmp_4
always @ (posedge clk_i)
//synthesis translate_off
if (data_valid_i & (SIMULATION=="TRUE"))
error_byte[i] <= (data_i[8*(i+1)-1:8*i] !== cmp_data[8*(i+1)-1:8*i]) ;
else
//synthesis translate_on
if (data_valid_i)
error_byte[i] <= (data_i[8*(i+1)-1:8*i] != cmp_data[8*(i+1)-1:8*i]) ;
else
error_byte[i] <= 1'b0;
end
for (i = 0; i < NUM_DQ_PINS*8; i = i + 1)
begin: gen_cmp_bit_4
always @ (posedge clk_i)
//synthesis translate_off
if (data_valid_i & (SIMULATION=="TRUE"))
error_bit[i] <= (data_i[i] !== cmp_data[i]) ;
else
//synthesis translate_on
if (data_valid_i)
error_bit[i] <= (data_i[i] != cmp_data[i]) ;
else
error_bit[i] <= 1'b0;
end
end
always @ (posedge clk_i)
begin
dq_r0_read_bit_rdlay1 <= #TCQ data_i[NUM_DQ_PINS*1 - 1:0];
dq_f0_read_bit_rdlay1 <= #TCQ data_i[NUM_DQ_PINS*2 - 1:NUM_DQ_PINS*1];
dq_r1_read_bit_rdlay1 <= #TCQ data_i[NUM_DQ_PINS*3 - 1:NUM_DQ_PINS*2];
dq_f1_read_bit_rdlay1 <= #TCQ data_i[NUM_DQ_PINS*4 - 1:NUM_DQ_PINS*3];
dq_r0_expect_bit_rdlay1 <= #TCQ cmp_data[NUM_DQ_PINS*1 - 1:0];
dq_f0_expect_bit_rdlay1 <= #TCQ cmp_data[NUM_DQ_PINS*2 - 1:NUM_DQ_PINS*1];
dq_r1_expect_bit_rdlay1 <= #TCQ cmp_data[NUM_DQ_PINS*3 - 1:NUM_DQ_PINS*2];
dq_f1_expect_bit_rdlay1 <= #TCQ cmp_data[NUM_DQ_PINS*4 - 1:NUM_DQ_PINS*3];
dq_r0_read_bit_r <= #TCQ dq_r0_read_bit_rdlay1 ;
dq_f0_read_bit_r <= #TCQ dq_f0_read_bit_rdlay1 ;
dq_r1_read_bit_r <= #TCQ dq_r1_read_bit_rdlay1 ;
dq_f1_read_bit_r <= #TCQ dq_f1_read_bit_rdlay1 ;
dq_r0_expect_bit_r <= #TCQ dq_r0_expect_bit_rdlay1;
dq_f0_expect_bit_r <= #TCQ dq_f0_expect_bit_rdlay1;
dq_r1_expect_bit_r <= #TCQ dq_r1_expect_bit_rdlay1;
dq_f1_expect_bit_r <= #TCQ dq_f1_expect_bit_rdlay1;
end
always @ (posedge clk_i)
begin
if (rst_i[1] || manual_clear_error) begin
error_byte_r1 <= #TCQ 'b0;
error_bit_r1 <= #TCQ 'b0;
end
else if (data_valid_r1) begin
error_byte_r1 <= #TCQ error_byte;
error_bit_r1 <= #TCQ error_bit;
end
else
begin
error_byte_r1 <= #TCQ 'b0;
error_bit_r1 <= #TCQ 'b0;
end
end
always @ (posedge clk_i)
begin
if (rst_i[1] || manual_clear_error)
data_error <= #TCQ 1'b0;
else if (data_valid_r2)
data_error <= #TCQ | error_byte_r1;
else
data_error <= #TCQ 1'b0;
//synthesis translate_off
if (data_error)
$display ("ERROR: Expected data=%h, Received data=%h @ %t" ,cmp_data_r2, rd_data_r2, $time);
//synthesis translate_on
end
localparam NUM_OF_DQS = (MEM_TYPE == "QDR2PLUS") ? 9 : 8 ;
if (MEM_TYPE == "QDR2PLUS") begin: qdr_design_error_calc
if (MEM_BURST_LEN == 4) begin: bl4_design
for ( i = 0; i < NUM_DQ_PINS/NUM_OF_DQS; i = i+1) begin: gen_dq_error_map
assign dq_lane_error[i] = (error_byte_r1[i] |
error_byte_r1[i + (NUM_DQ_PINS/NUM_OF_DQS)] |
error_byte_r1[i + (NUM_DQ_PINS*2/NUM_OF_DQS)] |
error_byte_r1[i + (NUM_DQ_PINS*3/NUM_OF_DQS)] ) ? 1'b1 : 1'b0 ;
assign cumlative_dq_lane_error_c[i] = cumlative_dq_lane_error_r[i] | dq_lane_error_r1[i];
end
end else begin: bl2_design
for ( i = 0; i < NUM_DQ_PINS/NUM_OF_DQS; i = i+1) begin: gen_dq_error_map
assign dq_lane_error[i] = (error_byte_r1[i] |
error_byte_r1[i + (NUM_DQ_PINS/NUM_OF_DQS)] ) ? 1'b1 : 1'b0 ;
assign cumlative_dq_lane_error_c[i] = cumlative_dq_lane_error_r[i] | dq_lane_error_r1[i];
end
end
end else begin: ddr_design_error_calc
if (nCK_PER_CLK == 4) begin: ck_4to1_design
for ( i = 0; i < NUM_DQ_PINS/NUM_OF_DQS; i = i+1) begin: gen_dq_error_map
assign dq_lane_error[i] = (error_byte_r1[i] |
error_byte_r1[i + (NUM_DQ_PINS/NUM_OF_DQS)] |
error_byte_r1[i + (NUM_DQ_PINS*2/NUM_OF_DQS)] |
error_byte_r1[i + (NUM_DQ_PINS*3/NUM_OF_DQS)] |
error_byte_r1[i + (NUM_DQ_PINS*4/NUM_OF_DQS)] |
error_byte_r1[i + (NUM_DQ_PINS*5/NUM_OF_DQS)] |
error_byte_r1[i + (NUM_DQ_PINS*6/NUM_OF_DQS)] |
error_byte_r1[i + (NUM_DQ_PINS*7/NUM_OF_DQS)] ) ? 1'b1 : 1'b0 ;
assign cumlative_dq_lane_error_c[i] = cumlative_dq_lane_error_r[i] | dq_lane_error_r1[i];
end
end else if (nCK_PER_CLK == 2) begin: ck_2to1_design
for ( i = 0; i < NUM_DQ_PINS/NUM_OF_DQS; i = i+1) begin: gen_dq_error_map
assign dq_lane_error[i] = (error_byte_r1[i] |
error_byte_r1[i + (NUM_DQ_PINS/NUM_OF_DQS)] |
error_byte_r1[i + (NUM_DQ_PINS*2/NUM_OF_DQS)] |
error_byte_r1[i + (NUM_DQ_PINS*3/NUM_OF_DQS)] ) ? 1'b1 : 1'b0 ;
assign cumlative_dq_lane_error_c[i] = cumlative_dq_lane_error_r[i] | dq_lane_error_r1[i];
end
end
end
// mapped the user bits error to dq bits error
// mapper the error to rising 0
for ( i = 0; i < NUM_DQ_PINS; i = i+1)
begin: gen_dq_r0_error_mapbit
assign dq_r0_bit_error[i] = (error_bit_r1[i]);
assign cumlative_dq_r0_bit_error_c[i] = cumlative_dq_r0_bit_error_r[i] | dq_r0_bit_error[i];
end
// mapper the error to falling 0
for ( i = 0; i < NUM_DQ_PINS; i = i+1)
begin: gen_dq_f0_error_mapbit
assign dq_f0_bit_error[i] = (error_bit_r1[i+NUM_DQ_PINS*1] );
assign cumlative_dq_f0_bit_error_c[i] = cumlative_dq_f0_bit_error_r[i] | dq_f0_bit_error[i];
end
// mapper the error to rising 1
for ( i = 0; i < NUM_DQ_PINS; i = i+1)
begin: gen_dq_r1_error_mapbit
assign dq_r1_bit_error[i] = (error_bit_r1[i+ (NUM_DQ_PINS*2)]);
assign cumlative_dq_r1_bit_error_c[i] = cumlative_dq_r1_bit_error_r[i] | dq_r1_bit_error[i];
end
// mapper the error to falling 1
for ( i = 0; i < NUM_DQ_PINS; i = i+1)
begin: gen_dq_f1_error_mapbit
assign dq_f1_bit_error[i] = ( error_bit_r1[i+ (NUM_DQ_PINS*3)]);
assign cumlative_dq_f1_bit_error_c[i] = cumlative_dq_f1_bit_error_r[i] | dq_f1_bit_error[i];
end
reg COuta;
always @ (posedge clk_i)
begin
if (rst_i[1] || manual_clear_error) begin
dq_bit_error_r1 <= #TCQ 'b0;
dq_lane_error_r1 <= #TCQ 'b0;
dq_lane_error_r2 <= #TCQ 'b0;
data_valid_r1 <= #TCQ 1'b0;
data_valid_r2 <= #TCQ 1'b0;
dq_r0_bit_error_r <= #TCQ 'b0;
dq_f0_bit_error_r <= #TCQ 'b0;
dq_r1_bit_error_r <= #TCQ 'b0;
dq_f1_bit_error_r <= #TCQ 'b0;
cumlative_dq_lane_error_reg <= #TCQ 'b0;
cumlative_dq_r0_bit_error_r <= #TCQ 'b0;
cumlative_dq_f0_bit_error_r <= #TCQ 'b0;
cumlative_dq_r1_bit_error_r <= #TCQ 'b0;
cumlative_dq_f1_bit_error_r <= #TCQ 'b0;
error_addr_r1 <= #TCQ 'b0;
error_addr_r2 <= #TCQ 'b0;
error_addr_r3 <= #TCQ 'b0;
end
else begin
data_valid_r1 <= #TCQ data_valid_i;
data_valid_r2 <= #TCQ data_valid_r1;
dq_lane_error_r1 <= #TCQ dq_lane_error;
dq_bit_error_r1 <= #TCQ dq_bit_error;
cumlative_dq_lane_error_reg <= #TCQ cumlative_dq_lane_error_c;
cumlative_dq_r0_bit_error_r <= #TCQ cumlative_dq_r0_bit_error_c;
cumlative_dq_f0_bit_error_r <= #TCQ cumlative_dq_f0_bit_error_c;
cumlative_dq_r1_bit_error_r <= #TCQ cumlative_dq_r1_bit_error_c;
cumlative_dq_f1_bit_error_r <= #TCQ cumlative_dq_f1_bit_error_c;
dq_r0_bit_error_r <= #TCQ dq_r0_bit_error;
dq_f0_bit_error_r <= #TCQ dq_f0_bit_error;
dq_r1_bit_error_r <= #TCQ dq_r1_bit_error;
dq_f1_bit_error_r <= #TCQ dq_f1_bit_error;
error_addr_r2 <= #TCQ error_addr_r1;
error_addr_r3 <= #TCQ error_addr_r2;
if (rd_mdata_en)
error_addr_r1 <= #TCQ gen_addr;
else if (data_valid_i)
{COuta,error_addr_r1} <= #TCQ error_addr_r1 + 4;
end
end
end
endgenerate
assign cumlative_dq_lane_error_r = cumlative_dq_lane_error_reg;
assign dq_error_bytelane_cmp = dq_lane_error_r1;
assign data_error_o = data_error;
assign error_addr_o = error_addr_r3;
endmodule
|
/*
* HIFIFO: Harmon Instruments PCI Express to FIFO
* Copyright (C) 2014 Harmon Instruments, LLC
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/
*/
/*
* First word fall through FIFO
* Copyright 2014 Harmon Instruments
* Author: Darrell Harmon
*/
module fwft_fifo
(
input reset, // async
input i_clock,
input [NBITS-1:0] i_data,
input i_valid,
output i_ready,
input o_clock,
input o_read,
output [NBITS-1:0] o_data,
output o_valid,
output o_almost_empty
);
parameter NBITS = 64; // 1 to 72 valid
parameter FULL_OFFSET = 9'h080;
`ifdef SIM
// this is for simulation only!!!
reg [NBITS-1:0] fifo[0:511];
reg [NBITS-1:0] a_d, b_d;
reg a_v, b_v;
wire a_cken = (p_out != p_in) && (~a_v | ~b_v | c_cken);
wire b_cken = a_v && (~b_v | c_cken);
wire c_cken = o_read;
reg [8:0] p_in, p_out;
wire [8:0] count = p_in - p_out;
assign o_valid = b_v;
assign o_data = b_d;
assign i_ready = (count < 384);
assign o_almost_empty = ((count + a_v + b_v) < 16);
always @ (posedge i_clock)
begin
if(i_valid)
fifo[p_in] <= i_data;
p_in <= reset ? 1'b0 : p_in + i_valid;
end
always @ (posedge o_clock)
begin
p_out <= reset ? 1'b0 : p_out + a_cken;
a_v <= reset ? 1'b0 : a_cken | (a_v && ~b_cken);
if(a_cken)
a_d <= fifo[p_out];
b_v <= reset ? 1'b0 : b_cken | (b_v && ~c_cken);
if(b_cken)
b_d <= a_d;
end
`else
wire empty, almostfull;
assign i_ready = ~almostfull;
assign o_valid = ~empty;
generate
if(NBITS>36) begin : fifo_36
FIFO_DUALCLOCK_MACRO
#(
.ALMOST_EMPTY_OFFSET(9'h00F),
.ALMOST_FULL_OFFSET(FULL_OFFSET),
.DATA_WIDTH(NBITS),
.DEVICE("7SERIES"),
.FIFO_SIZE ("36Kb"),
.FIRST_WORD_FALL_THROUGH ("TRUE")
)
FIFO_DUALCLOCK_MACRO_inst
(
.ALMOSTEMPTY(o_almost_empty),
.ALMOSTFULL(almostfull),
.DO(o_data),
.EMPTY(empty),
.FULL(),
.RDCOUNT(),
.RDERR(),
.WRCOUNT(),
.WRERR(),
.DI(i_data),
.RDCLK(o_clock),
.RDEN(o_read),
.RST(reset),
.WRCLK(i_clock),
.WREN(i_valid)
);
end
else begin : fifo_18
FIFO_DUALCLOCK_MACRO
#(
.ALMOST_EMPTY_OFFSET(9'h00F),
.ALMOST_FULL_OFFSET(FULL_OFFSET),
.DATA_WIDTH(NBITS),
.DEVICE("7SERIES"),
.FIFO_SIZE ("18Kb"),
.FIRST_WORD_FALL_THROUGH ("TRUE")
)
FIFO_DUALCLOCK_MACRO_inst
(
.ALMOSTEMPTY(o_almost_empty),
.ALMOSTFULL(almostfull),
.DO(o_data),
.EMPTY(empty),
.FULL(),
.RDCOUNT(),
.RDERR(),
.WRCOUNT(),
.WRERR(),
.DI(i_data),
.RDCLK(o_clock),
.RDEN(o_read),
.RST(reset),
.WRCLK(i_clock),
.WREN(i_valid)
);
end
endgenerate
`endif
endmodule |
module test_bench(clk, rst);
input clk;
input rst;
wire [63:0] wire_39069600;
wire wire_39069600_stb;
wire wire_39069600_ack;
wire [63:0] wire_39795024;
wire wire_39795024_stb;
wire wire_39795024_ack;
wire [63:0] wire_39795168;
wire wire_39795168_stb;
wire wire_39795168_ack;
file_reader_a file_reader_a_39796104(
.clk(clk),
.rst(rst),
.output_z(wire_39069600),
.output_z_stb(wire_39069600_stb),
.output_z_ack(wire_39069600_ack));
file_reader_b file_reader_b_39759816(
.clk(clk),
.rst(rst),
.output_z(wire_39795024),
.output_z_stb(wire_39795024_stb),
.output_z_ack(wire_39795024_ack));
file_writer file_writer_39028208(
.clk(clk),
.rst(rst),
.input_a(wire_39795168),
.input_a_stb(wire_39795168_stb),
.input_a_ack(wire_39795168_ack));
double_divider divider_39759952(
.clk(clk),
.rst(rst),
.input_a(wire_39069600),
.input_a_stb(wire_39069600_stb),
.input_a_ack(wire_39069600_ack),
.input_b(wire_39795024),
.input_b_stb(wire_39795024_stb),
.input_b_ack(wire_39795024_ack),
.output_z(wire_39795168),
.output_z_stb(wire_39795168_stb),
.output_z_ack(wire_39795168_ack));
endmodule
|
// The shader asserts row lines for a length of time that is proportional
// to the intensity value stored in the values vector.
// Synchronous active low reset.
module shader(input clk,
input rst_n,
input [(32*5-1):0] values,
output reg [31:0] rows
);
reg [4:0] n;
always @(posedge clk) begin
if (!rst_n)
n = 0;
// icarus verilog doesn't implement the generate statement.
`define pulse(i) rows[i] = n < values[4+(5*i):(5*i)]
`pulse(0);
`pulse(1);
`pulse(2);
`pulse(3);
`pulse(4);
`pulse(5);
`pulse(6);
`pulse(7);
`pulse(8);
`pulse(9);
`pulse(10);
`pulse(11);
`pulse(12);
`pulse(13);
`pulse(14);
`pulse(15);
`pulse(16);
`pulse(17);
`pulse(18);
`pulse(19);
`pulse(20);
`pulse(21);
`pulse(22);
`pulse(23);
`pulse(24);
`pulse(25);
`pulse(26);
`pulse(27);
`pulse(28);
`pulse(29);
`pulse(30);
`pulse(31);
n = n+1;
end
endmodule // line
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O41AI_4_V
`define SKY130_FD_SC_HD__O41AI_4_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog wrapper for o41ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o41ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o41ai_4 (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o41ai_4 (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O41AI_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21BAI_SYMBOL_V
`define SKY130_FD_SC_HDLL__O21BAI_SYMBOL_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o21bai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1_N,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21BAI_SYMBOL_V
|
// limbus_mm_interconnect_0_avalon_st_adapter.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module limbus_mm_interconnect_0_avalon_st_adapter #(
parameter inBitsPerSymbol = 34,
parameter inUsePackets = 0,
parameter inDataWidth = 34,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 34,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [33:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [33:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
limbus_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
// // (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_custom_mul_ll_hc(
// this interface matches what hdlgen expects
input logic clock,
input logic resetn,
input logic valid_in,
input logic stall_in,
output logic valid_out,
output logic stall_out,
input logic [31:0] dataa,
input logic [31:0] datab,
output logic [31:0] result
);
acl_fp_custom_mul_ll_hc_core #(
.HIGH_CAPACITY(1)
)
core(
.clock(clock),
.resetn(resetn),
.valid_in(valid_in),
.stall_in(stall_in),
.valid_out(valid_out),
.stall_out(stall_out),
.dataa(dataa),
.datab(datab),
.result(result)
);
endmodule
|
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_acospi_s5 (
enable,
clock,
dataa,
result);
input enable;
input clock;
input [31:0] dataa;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
fp_arccospi_s5 inst (
.en (enable),
.areset(1'b0),
.clk(clock),
.a(dataa),
.q(sub_wire0));
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized OR with generic_baseblocks_v2_1_0_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_carry_latch_or #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire I,
output wire O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign O = CIN | I;
end else begin : USE_FPGA
OR2L or2l_inst1
(
.O(O),
.DI(CIN),
.SRI(I)
);
end
endgenerate
endmodule
|
module regfile_with_be #(
// Status register count
parameter STAT_CNT = 32,
// Control register count
parameter CTRL_CNT = 32,
// Address width
parameter ADDR_W = 7,
// Data width
parameter DATA_W = 8,
// If 1 -- selected status register using MSB,
// otherwise -- by registers count.
parameter SEL_SR_BY_MSB = 1
) (
input clk_i,
input rst_i,
input [DATA_W-1:0] data_i,
input wren_i,
//FIXME: add normal parametrization!
input [1:0] be_i,
input [ADDR_W-1:0] addr_i,
input [DATA_W-1:0] sreg_i [STAT_CNT-1:0],
output logic [DATA_W-1:0] data_o,
output logic [DATA_W-1:0] creg_o [CTRL_CNT-1:0]
);
localparam CR_CNT_WIDTH = ( CTRL_CNT == 1 ) ? ( 1 ) : $clog2( CTRL_CNT );
localparam SR_CNT_WIDTH = ( STAT_CNT == 1 ) ? ( 1 ) : $clog2( STAT_CNT );
// Inner address of status or conrrol register
logic [CR_CNT_WIDTH-1:0] cr_local_addr;
logic [SR_CNT_WIDTH-1:0] sr_local_addr;
// Array of control registers
logic [DATA_W-1:0] ctrl_regs [CTRL_CNT-1:0];
logic status_is_sel;
// Write to conotrl register operation
always_ff @( posedge clk_i, posedge rst_i )
if( rst_i )
begin
int i;
for( i = 0; i < CTRL_CNT; i++ )
ctrl_regs[i] <= '0;
end
else
if( wren_i & !status_is_sel )
//FIXME: add normal parametrization!
case( be_i )
3'b01:
ctrl_regs[cr_local_addr][7:0] <= data_i[7:0];
3'b10:
ctrl_regs[cr_local_addr][15:8] <= data_i[15:8];
3'b11:
ctrl_regs[cr_local_addr] <= data_i;
endcase
// SEL_SR_BY_MSB == 1:
// If MSB of address == 1, we access to status registers
// otherwise we access to control registers.
// SEL_SR_BY_MSB == 0:
// We used address for select registers type.
assign status_is_sel = ( SEL_SR_BY_MSB == 1 ) ? ( addr_i[ADDR_W-1] ) : ( addr_i >= CTRL_CNT );
assign cr_local_addr = ( SEL_SR_BY_MSB == 1 ) ? ( addr_i[ADDR_W-2:0] ) : ( addr_i[CR_CNT_WIDTH-1:0] );
assign sr_local_addr = ( SEL_SR_BY_MSB == 1 ) ? ( addr_i[ADDR_W-2:0] ) : ( addr_i - CTRL_CNT );
// Read operation.
always_comb
if( status_is_sel )
data_o = sreg_i[sr_local_addr];
else
data_o = ctrl_regs[cr_local_addr];
// Output assigning
always_comb
creg_o = ctrl_regs;
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : arb_mux.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_3_arb_mux #
(
parameter TCQ = 100,
parameter EVEN_CWL_2T_MODE = "OFF",
parameter ADDR_CMD_MODE = "1T",
parameter BANK_VECT_INDX = 11,
parameter BANK_WIDTH = 3,
parameter BURST_MODE = "8",
parameter CS_WIDTH = 4,
parameter CL = 5,
parameter CWL = 5,
parameter DATA_BUF_ADDR_VECT_INDX = 31,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DRAM_TYPE = "DDR3",
parameter CKE_ODT_AUX = "FALSE", //Parameter to turn on/off the aux_out signal
parameter EARLY_WR_DATA_ADDR = "OFF",
parameter ECC = "OFF",
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2, // # DRAM CKs per fabric CLKs
parameter nCS_PER_RANK = 1,
parameter nRAS = 37500, // ACT->PRE cmd period (CKs)
parameter nRCD = 12500, // ACT->R/W delay (CKs)
parameter nSLOTS = 2,
parameter nWR = 6, // Write recovery (CKs)
parameter RANKS = 1,
parameter RANK_VECT_INDX = 15,
parameter RANK_WIDTH = 2,
parameter ROW_VECT_INDX = 63,
parameter ROW_WIDTH = 16,
parameter RTT_NOM = "40",
parameter RTT_WR = "120",
parameter SLOT_0_CONFIG = 8'b0000_0101,
parameter SLOT_1_CONFIG = 8'b0000_1010
)
(/*AUTOARG*/
// Outputs
output [ROW_WIDTH-1:0] col_a, // From arb_select0 of arb_select.v
output [BANK_WIDTH-1:0] col_ba, // From arb_select0 of arb_select.v
output [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr,// From arb_select0 of arb_select.v
output col_periodic_rd, // From arb_select0 of arb_select.v
output [RANK_WIDTH-1:0] col_ra, // From arb_select0 of arb_select.v
output col_rmw, // From arb_select0 of arb_select.v
output col_rd_wr,
output [ROW_WIDTH-1:0] col_row, // From arb_select0 of arb_select.v
output col_size, // From arb_select0 of arb_select.v
output [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr,// From arb_select0 of arb_select.v
output wire [nCK_PER_CLK-1:0] mc_ras_n,
output wire [nCK_PER_CLK-1:0] mc_cas_n,
output wire [nCK_PER_CLK-1:0] mc_we_n,
output wire [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address,
output wire [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank,
output wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n,
output wire [1:0] mc_odt,
output wire [nCK_PER_CLK-1:0] mc_cke,
output wire [3:0] mc_aux_out0,
output wire [3:0] mc_aux_out1,
output [2:0] mc_cmd,
output [5:0] mc_data_offset,
output [5:0] mc_data_offset_1,
output [5:0] mc_data_offset_2,
output [1:0] mc_cas_slot,
output [RANK_WIDTH-1:0] rnk_config, // From arb_select0 of arb_select.v
output rnk_config_valid_r, // From arb_row_col0 of arb_row_col.v
output [nBANK_MACHS-1:0] sending_row, // From arb_row_col0 of arb_row_col.v
output [nBANK_MACHS-1:0] sending_pre,
output sent_col, // From arb_row_col0 of arb_row_col.v
output sent_col_r, // From arb_row_col0 of arb_row_col.v
output sent_row, // From arb_row_col0 of arb_row_col.v
output [nBANK_MACHS-1:0] sending_col,
output rnk_config_strobe,
output insert_maint_r1,
output rnk_config_kill_rts_col,
// Inputs
input clk,
input rst,
input init_calib_complete,
input [6*RANKS-1:0] calib_rddata_offset,
input [6*RANKS-1:0] calib_rddata_offset_1,
input [6*RANKS-1:0] calib_rddata_offset_2,
input [ROW_VECT_INDX:0] col_addr, // To arb_select0 of arb_select.v
input [nBANK_MACHS-1:0] col_rdy_wr, // To arb_row_col0 of arb_row_col.v
input insert_maint_r, // To arb_row_col0 of arb_row_col.v
input [RANK_WIDTH-1:0] maint_rank_r, // To arb_select0 of arb_select.v
input maint_zq_r, // To arb_select0 of arb_select.v
input maint_sre_r, // To arb_select0 of arb_select.v
input maint_srx_r, // To arb_select0 of arb_select.v
input [nBANK_MACHS-1:0] rd_wr_r, // To arb_select0 of arb_select.v
input [BANK_VECT_INDX:0] req_bank_r, // To arb_select0 of arb_select.v
input [nBANK_MACHS-1:0] req_cas, // To arb_select0 of arb_select.v
input [DATA_BUF_ADDR_VECT_INDX:0] req_data_buf_addr_r,// To arb_select0 of arb_select.v
input [nBANK_MACHS-1:0] req_periodic_rd_r, // To arb_select0 of arb_select.v
input [RANK_VECT_INDX:0] req_rank_r, // To arb_select0 of arb_select.v
input [nBANK_MACHS-1:0] req_ras, // To arb_select0 of arb_select.v
input [ROW_VECT_INDX:0] req_row_r, // To arb_select0 of arb_select.v
input [nBANK_MACHS-1:0] req_size_r, // To arb_select0 of arb_select.v
input [nBANK_MACHS-1:0] req_wr_r, // To arb_select0 of arb_select.v
input [ROW_VECT_INDX:0] row_addr, // To arb_select0 of arb_select.v
input [nBANK_MACHS-1:0] row_cmd_wr, // To arb_select0 of arb_select.v
input [nBANK_MACHS-1:0] rtc, // To arb_row_col0 of arb_row_col.v
input [nBANK_MACHS-1:0] rts_col, // To arb_row_col0 of arb_row_col.v
input [nBANK_MACHS-1:0] rts_row, // To arb_row_col0 of arb_row_col.v
input [nBANK_MACHS-1:0] rts_pre, // To arb_row_col0 of arb_row_col.v
input [7:0] slot_0_present, // To arb_select0 of arb_select.v
input [7:0] slot_1_present // To arb_select0 of arb_select.v
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire cs_en0; // From arb_row_col0 of arb_row_col.v
wire cs_en1; // From arb_row_col0 of arb_row_col.v
wire [nBANK_MACHS-1:0] grant_col_r; // From arb_row_col0 of arb_row_col.v
wire [nBANK_MACHS-1:0] grant_col_wr; // From arb_row_col0 of arb_row_col.v
wire [nBANK_MACHS-1:0] grant_config_r; // From arb_row_col0 of arb_row_col.v
wire [nBANK_MACHS-1:0] grant_row_r; // From arb_row_col0 of arb_row_col.v
wire [nBANK_MACHS-1:0] grant_pre_r; // From arb_row_col0 of arb_row_col.v
wire send_cmd0_row; // From arb_row_col0 of arb_row_col.v
wire send_cmd0_col; // From arb_row_col0 of arb_row_col.v
wire send_cmd1_row; // From arb_row_col0 of arb_row_col.v
wire send_cmd1_col;
wire send_cmd2_row;
wire send_cmd2_col;
wire send_cmd2_pre;
wire send_cmd3_col;
wire [5:0] col_channel_offset;
// End of automatics
wire sent_col_i;
wire cs_en2;
wire cs_en3;
assign sent_col = sent_col_i;
mig_7series_v2_3_arb_row_col #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.CWL (CWL),
.EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nRAS (nRAS),
.nRCD (nRCD),
.nWR (nWR))
arb_row_col0
(/*AUTOINST*/
// Outputs
.grant_row_r (grant_row_r[nBANK_MACHS-1:0]),
.grant_pre_r (grant_pre_r[nBANK_MACHS-1:0]),
.sent_row (sent_row),
.sending_row (sending_row[nBANK_MACHS-1:0]),
.sending_pre (sending_pre[nBANK_MACHS-1:0]),
.grant_config_r (grant_config_r[nBANK_MACHS-1:0]),
.rnk_config_strobe (rnk_config_strobe),
.rnk_config_kill_rts_col (rnk_config_kill_rts_col),
.rnk_config_valid_r (rnk_config_valid_r),
.grant_col_r (grant_col_r[nBANK_MACHS-1:0]),
.sending_col (sending_col[nBANK_MACHS-1:0]),
.sent_col (sent_col_i),
.sent_col_r (sent_col_r),
.grant_col_wr (grant_col_wr[nBANK_MACHS-1:0]),
.send_cmd0_row (send_cmd0_row),
.send_cmd0_col (send_cmd0_col),
.send_cmd1_row (send_cmd1_row),
.send_cmd1_col (send_cmd1_col),
.send_cmd2_row (send_cmd2_row),
.send_cmd2_col (send_cmd2_col),
.send_cmd2_pre (send_cmd2_pre),
.send_cmd3_col (send_cmd3_col),
.col_channel_offset (col_channel_offset),
.cs_en0 (cs_en0),
.cs_en1 (cs_en1),
.cs_en2 (cs_en2),
.cs_en3 (cs_en3),
.insert_maint_r1 (insert_maint_r1),
// Inputs
.clk (clk),
.rst (rst),
.rts_row (rts_row[nBANK_MACHS-1:0]),
.rts_pre (rts_pre[nBANK_MACHS-1:0]),
.insert_maint_r (insert_maint_r),
.rts_col (rts_col[nBANK_MACHS-1:0]),
.rtc (rtc[nBANK_MACHS-1:0]),
.col_rdy_wr (col_rdy_wr[nBANK_MACHS-1:0]));
mig_7series_v2_3_arb_select #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.EVEN_CWL_2T_MODE (EVEN_CWL_2T_MODE),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.BANK_VECT_INDX (BANK_VECT_INDX),
.BANK_WIDTH (BANK_WIDTH),
.BURST_MODE (BURST_MODE),
.CS_WIDTH (CS_WIDTH),
.CL (CL),
.CWL (CWL),
.DATA_BUF_ADDR_VECT_INDX (DATA_BUF_ADDR_VECT_INDX),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR),
.ECC (ECC),
.CKE_ODT_AUX (CKE_ODT_AUX),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nCS_PER_RANK (nCS_PER_RANK),
.nSLOTS (nSLOTS),
.RANKS (RANKS),
.RANK_VECT_INDX (RANK_VECT_INDX),
.RANK_WIDTH (RANK_WIDTH),
.ROW_VECT_INDX (ROW_VECT_INDX),
.ROW_WIDTH (ROW_WIDTH),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.SLOT_0_CONFIG (SLOT_0_CONFIG),
.SLOT_1_CONFIG (SLOT_1_CONFIG))
arb_select0
(/*AUTOINST*/
// Outputs
.col_periodic_rd (col_periodic_rd),
.col_ra (col_ra[RANK_WIDTH-1:0]),
.col_ba (col_ba[BANK_WIDTH-1:0]),
.col_a (col_a[ROW_WIDTH-1:0]),
.col_rmw (col_rmw),
.col_rd_wr (col_rd_wr),
.col_size (col_size),
.col_row (col_row[ROW_WIDTH-1:0]),
.col_data_buf_addr (col_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.col_wr_data_buf_addr (col_wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.mc_bank (mc_bank),
.mc_address (mc_address),
.mc_ras_n (mc_ras_n),
.mc_cas_n (mc_cas_n),
.mc_we_n (mc_we_n),
.mc_cs_n (mc_cs_n),
.mc_odt (mc_odt),
.mc_cke (mc_cke),
.mc_aux_out0 (mc_aux_out0),
.mc_aux_out1 (mc_aux_out1),
.mc_cmd (mc_cmd),
.mc_data_offset (mc_data_offset),
.mc_data_offset_1 (mc_data_offset_1),
.mc_data_offset_2 (mc_data_offset_2),
.mc_cas_slot (mc_cas_slot),
.col_channel_offset (col_channel_offset),
.rnk_config (rnk_config),
// Inputs
.clk (clk),
.rst (rst),
.init_calib_complete (init_calib_complete),
.calib_rddata_offset (calib_rddata_offset),
.calib_rddata_offset_1 (calib_rddata_offset_1),
.calib_rddata_offset_2 (calib_rddata_offset_2),
.req_rank_r (req_rank_r[RANK_VECT_INDX:0]),
.req_bank_r (req_bank_r[BANK_VECT_INDX:0]),
.req_ras (req_ras[nBANK_MACHS-1:0]),
.req_cas (req_cas[nBANK_MACHS-1:0]),
.req_wr_r (req_wr_r[nBANK_MACHS-1:0]),
.grant_row_r (grant_row_r[nBANK_MACHS-1:0]),
.grant_pre_r (grant_pre_r[nBANK_MACHS-1:0]),
.row_addr (row_addr[ROW_VECT_INDX:0]),
.row_cmd_wr (row_cmd_wr[nBANK_MACHS-1:0]),
.insert_maint_r1 (insert_maint_r1),
.maint_zq_r (maint_zq_r),
.maint_sre_r (maint_sre_r),
.maint_srx_r (maint_srx_r),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.req_periodic_rd_r (req_periodic_rd_r[nBANK_MACHS-1:0]),
.req_size_r (req_size_r[nBANK_MACHS-1:0]),
.rd_wr_r (rd_wr_r[nBANK_MACHS-1:0]),
.req_row_r (req_row_r[ROW_VECT_INDX:0]),
.col_addr (col_addr[ROW_VECT_INDX:0]),
.req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_VECT_INDX:0]),
.grant_col_r (grant_col_r[nBANK_MACHS-1:0]),
.grant_col_wr (grant_col_wr[nBANK_MACHS-1:0]),
.send_cmd0_row (send_cmd0_row),
.send_cmd0_col (send_cmd0_col),
.send_cmd1_row (send_cmd1_row),
.send_cmd1_col (send_cmd1_col),
.send_cmd2_row (send_cmd2_row),
.send_cmd2_col (send_cmd2_col),
.send_cmd2_pre (send_cmd2_pre),
.send_cmd3_col (send_cmd3_col),
.sent_col (EVEN_CWL_2T_MODE == "ON" ? sent_col_r : sent_col),
.cs_en0 (cs_en0),
.cs_en1 (cs_en1),
.cs_en2 (cs_en2),
.cs_en3 (cs_en3),
.grant_config_r (grant_config_r[nBANK_MACHS-1:0]),
.rnk_config_strobe (rnk_config_strobe),
.slot_0_present (slot_0_present[7:0]),
.slot_1_present (slot_1_present[7:0]));
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 13 23:24:41 2017
// Host : TheMosass-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_processing_system7_0_0_sim_netlist.v
// Design : design_1_processing_system7_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "design_1_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2016.4" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(GPIO_I,
GPIO_O,
GPIO_T,
SDIO0_WP,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
IRQ_F2P,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB);
(* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 GPIO_0 TRI_I" *) input [63:0]GPIO_I;
(* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 GPIO_0 TRI_O" *) output [63:0]GPIO_O;
(* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 GPIO_0 TRI_T" *) output [63:0]GPIO_T;
(* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 WP" *) input SDIO0_WP;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *) output [1:0]USB0_PORT_INDCTL;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *) output USB0_VBUS_PWRSELECT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *) input USB0_VBUS_PWRFAULT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *) output M_AXI_GP0_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *) output M_AXI_GP0_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *) output M_AXI_GP0_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *) output M_AXI_GP0_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *) output M_AXI_GP0_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *) output M_AXI_GP0_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *) output [11:0]M_AXI_GP0_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *) output [11:0]M_AXI_GP0_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *) output [11:0]M_AXI_GP0_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *) output [1:0]M_AXI_GP0_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *) output [1:0]M_AXI_GP0_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *) output [2:0]M_AXI_GP0_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *) output [1:0]M_AXI_GP0_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *) output [1:0]M_AXI_GP0_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *) output [2:0]M_AXI_GP0_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *) output [2:0]M_AXI_GP0_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *) output [2:0]M_AXI_GP0_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *) output [31:0]M_AXI_GP0_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *) output [31:0]M_AXI_GP0_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *) output [31:0]M_AXI_GP0_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *) output [3:0]M_AXI_GP0_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *) output [3:0]M_AXI_GP0_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *) output [3:0]M_AXI_GP0_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *) output [3:0]M_AXI_GP0_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *) output [3:0]M_AXI_GP0_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *) output [3:0]M_AXI_GP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *) output [3:0]M_AXI_GP0_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *) input M_AXI_GP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *) input M_AXI_GP0_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *) input M_AXI_GP0_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *) input M_AXI_GP0_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *) input M_AXI_GP0_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *) input M_AXI_GP0_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *) input M_AXI_GP0_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *) input [11:0]M_AXI_GP0_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *) input [11:0]M_AXI_GP0_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *) input [1:0]M_AXI_GP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *) input [1:0]M_AXI_GP0_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *) input [31:0]M_AXI_GP0_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT" *) input [0:0]IRQ_F2P;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *) output FCLK_CLK0;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *) output FCLK_RESET0_N;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_CAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_CKE;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_Clk_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_Clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_CS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_DRSTB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_ODT;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_RAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_WEB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout [2:0]DDR_BankAddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) inout [14:0]DDR_Addr;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) inout DDR_VRN;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout DDR_VRP;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout [3:0]DDR_DM;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout [31:0]DDR_DQ;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout [3:0]DDR_DQS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) inout [3:0]DDR_DQS;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout PS_SRSTB;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout PS_CLK;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) inout PS_PORB;
wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr;
wire DDR_CAS_n;
wire DDR_CKE;
wire DDR_CS_n;
wire DDR_Clk;
wire DDR_Clk_n;
wire [3:0]DDR_DM;
wire [31:0]DDR_DQ;
wire [3:0]DDR_DQS;
wire [3:0]DDR_DQS_n;
wire DDR_DRSTB;
wire DDR_ODT;
wire DDR_RAS_n;
wire DDR_VRN;
wire DDR_VRP;
wire DDR_WEB;
wire FCLK_CLK0;
wire FCLK_RESET0_N;
wire [63:0]GPIO_I;
wire [63:0]GPIO_O;
wire [63:0]GPIO_T;
wire [0:0]IRQ_F2P;
wire [53:0]MIO;
wire M_AXI_GP0_ACLK;
wire [31:0]M_AXI_GP0_ARADDR;
wire [1:0]M_AXI_GP0_ARBURST;
wire [3:0]M_AXI_GP0_ARCACHE;
wire [11:0]M_AXI_GP0_ARID;
wire [3:0]M_AXI_GP0_ARLEN;
wire [1:0]M_AXI_GP0_ARLOCK;
wire [2:0]M_AXI_GP0_ARPROT;
wire [3:0]M_AXI_GP0_ARQOS;
wire M_AXI_GP0_ARREADY;
wire [2:0]M_AXI_GP0_ARSIZE;
wire M_AXI_GP0_ARVALID;
wire [31:0]M_AXI_GP0_AWADDR;
wire [1:0]M_AXI_GP0_AWBURST;
wire [3:0]M_AXI_GP0_AWCACHE;
wire [11:0]M_AXI_GP0_AWID;
wire [3:0]M_AXI_GP0_AWLEN;
wire [1:0]M_AXI_GP0_AWLOCK;
wire [2:0]M_AXI_GP0_AWPROT;
wire [3:0]M_AXI_GP0_AWQOS;
wire M_AXI_GP0_AWREADY;
wire [2:0]M_AXI_GP0_AWSIZE;
wire M_AXI_GP0_AWVALID;
wire [11:0]M_AXI_GP0_BID;
wire M_AXI_GP0_BREADY;
wire [1:0]M_AXI_GP0_BRESP;
wire M_AXI_GP0_BVALID;
wire [31:0]M_AXI_GP0_RDATA;
wire [11:0]M_AXI_GP0_RID;
wire M_AXI_GP0_RLAST;
wire M_AXI_GP0_RREADY;
wire [1:0]M_AXI_GP0_RRESP;
wire M_AXI_GP0_RVALID;
wire [31:0]M_AXI_GP0_WDATA;
wire [11:0]M_AXI_GP0_WID;
wire M_AXI_GP0_WLAST;
wire M_AXI_GP0_WREADY;
wire [3:0]M_AXI_GP0_WSTRB;
wire M_AXI_GP0_WVALID;
wire PS_CLK;
wire PS_PORB;
wire PS_SRSTB;
wire SDIO0_WP;
wire TTC0_WAVE0_OUT;
wire TTC0_WAVE1_OUT;
wire TTC0_WAVE2_OUT;
wire [1:0]USB0_PORT_INDCTL;
wire USB0_VBUS_PWRFAULT;
wire USB0_VBUS_PWRSELECT;
wire NLW_inst_CAN0_PHY_TX_UNCONNECTED;
wire NLW_inst_CAN1_PHY_TX_UNCONNECTED;
wire NLW_inst_DMA0_DAVALID_UNCONNECTED;
wire NLW_inst_DMA0_DRREADY_UNCONNECTED;
wire NLW_inst_DMA0_RSTN_UNCONNECTED;
wire NLW_inst_DMA1_DAVALID_UNCONNECTED;
wire NLW_inst_DMA1_DRREADY_UNCONNECTED;
wire NLW_inst_DMA1_RSTN_UNCONNECTED;
wire NLW_inst_DMA2_DAVALID_UNCONNECTED;
wire NLW_inst_DMA2_DRREADY_UNCONNECTED;
wire NLW_inst_DMA2_RSTN_UNCONNECTED;
wire NLW_inst_DMA3_DAVALID_UNCONNECTED;
wire NLW_inst_DMA3_DRREADY_UNCONNECTED;
wire NLW_inst_DMA3_RSTN_UNCONNECTED;
wire NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED;
wire NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_MDC_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_O_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_T_UNCONNECTED;
wire NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED;
wire NLW_inst_ENET0_SOF_RX_UNCONNECTED;
wire NLW_inst_ENET0_SOF_TX_UNCONNECTED;
wire NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED;
wire NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_MDC_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_O_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_T_UNCONNECTED;
wire NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_RX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_TX_UNCONNECTED;
wire NLW_inst_EVENT_EVENTO_UNCONNECTED;
wire NLW_inst_FCLK_CLK1_UNCONNECTED;
wire NLW_inst_FCLK_CLK2_UNCONNECTED;
wire NLW_inst_FCLK_CLK3_UNCONNECTED;
wire NLW_inst_FCLK_RESET1_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET2_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET3_N_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED;
wire NLW_inst_I2C0_SCL_O_UNCONNECTED;
wire NLW_inst_I2C0_SCL_T_UNCONNECTED;
wire NLW_inst_I2C0_SDA_O_UNCONNECTED;
wire NLW_inst_I2C0_SDA_T_UNCONNECTED;
wire NLW_inst_I2C1_SCL_O_UNCONNECTED;
wire NLW_inst_I2C1_SCL_T_UNCONNECTED;
wire NLW_inst_I2C1_SDA_O_UNCONNECTED;
wire NLW_inst_I2C1_SDA_T_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CAN0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CAN1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CTI_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_GPIO_UNCONNECTED;
wire NLW_inst_IRQ_P2F_I2C0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_I2C1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_QSPI_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SMC_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SPI0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SPI1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_UART0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_UART1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_USB0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_USB1_UNCONNECTED;
wire NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED;
wire NLW_inst_PJTAG_TDO_UNCONNECTED;
wire NLW_inst_SDIO0_BUSPOW_UNCONNECTED;
wire NLW_inst_SDIO0_CLK_UNCONNECTED;
wire NLW_inst_SDIO0_CMD_O_UNCONNECTED;
wire NLW_inst_SDIO0_CMD_T_UNCONNECTED;
wire NLW_inst_SDIO0_LED_UNCONNECTED;
wire NLW_inst_SDIO1_BUSPOW_UNCONNECTED;
wire NLW_inst_SDIO1_CLK_UNCONNECTED;
wire NLW_inst_SDIO1_CMD_O_UNCONNECTED;
wire NLW_inst_SDIO1_CMD_T_UNCONNECTED;
wire NLW_inst_SDIO1_LED_UNCONNECTED;
wire NLW_inst_SPI0_MISO_O_UNCONNECTED;
wire NLW_inst_SPI0_MISO_T_UNCONNECTED;
wire NLW_inst_SPI0_MOSI_O_UNCONNECTED;
wire NLW_inst_SPI0_MOSI_T_UNCONNECTED;
wire NLW_inst_SPI0_SCLK_O_UNCONNECTED;
wire NLW_inst_SPI0_SCLK_T_UNCONNECTED;
wire NLW_inst_SPI0_SS1_O_UNCONNECTED;
wire NLW_inst_SPI0_SS2_O_UNCONNECTED;
wire NLW_inst_SPI0_SS_O_UNCONNECTED;
wire NLW_inst_SPI0_SS_T_UNCONNECTED;
wire NLW_inst_SPI1_MISO_O_UNCONNECTED;
wire NLW_inst_SPI1_MISO_T_UNCONNECTED;
wire NLW_inst_SPI1_MOSI_O_UNCONNECTED;
wire NLW_inst_SPI1_MOSI_T_UNCONNECTED;
wire NLW_inst_SPI1_SCLK_O_UNCONNECTED;
wire NLW_inst_SPI1_SCLK_T_UNCONNECTED;
wire NLW_inst_SPI1_SS1_O_UNCONNECTED;
wire NLW_inst_SPI1_SS2_O_UNCONNECTED;
wire NLW_inst_SPI1_SS_O_UNCONNECTED;
wire NLW_inst_SPI1_SS_T_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED;
wire NLW_inst_TRACE_CLK_OUT_UNCONNECTED;
wire NLW_inst_TRACE_CTL_UNCONNECTED;
wire NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED;
wire NLW_inst_UART0_DTRN_UNCONNECTED;
wire NLW_inst_UART0_RTSN_UNCONNECTED;
wire NLW_inst_UART0_TX_UNCONNECTED;
wire NLW_inst_UART1_DTRN_UNCONNECTED;
wire NLW_inst_UART1_RTSN_UNCONNECTED;
wire NLW_inst_UART1_TX_UNCONNECTED;
wire NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED;
wire NLW_inst_WDT_RST_OUT_UNCONNECTED;
wire [1:0]NLW_inst_DMA0_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA1_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA2_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA3_DATYPE_UNCONNECTED;
wire [7:0]NLW_inst_ENET0_GMII_TXD_UNCONNECTED;
wire [7:0]NLW_inst_ENET1_GMII_TXD_UNCONNECTED;
wire [1:0]NLW_inst_EVENT_STANDBYWFE_UNCONNECTED;
wire [1:0]NLW_inst_EVENT_STANDBYWFI_UNCONNECTED;
wire [31:0]NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_ARID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_AWID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_WID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED;
wire [2:0]NLW_inst_SDIO0_BUSVOLT_UNCONNECTED;
wire [3:0]NLW_inst_SDIO0_DATA_O_UNCONNECTED;
wire [3:0]NLW_inst_SDIO0_DATA_T_UNCONNECTED;
wire [2:0]NLW_inst_SDIO1_BUSVOLT_UNCONNECTED;
wire [3:0]NLW_inst_SDIO1_DATA_O_UNCONNECTED;
wire [3:0]NLW_inst_SDIO1_DATA_T_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_ACP_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_ACP_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP0_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP0_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP1_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP1_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED;
wire [1:0]NLW_inst_TRACE_DATA_UNCONNECTED;
wire [1:0]NLW_inst_USB1_PORT_INDCTL_UNCONNECTED;
PULLUP pullup_MIO_0
(.O(MIO[0]));
PULLUP pullup_MIO_9
(.O(MIO[9]));
PULLUP pullup_MIO_10
(.O(MIO[10]));
PULLUP pullup_MIO_11
(.O(MIO[11]));
PULLUP pullup_MIO_12
(.O(MIO[12]));
PULLUP pullup_MIO_13
(.O(MIO[13]));
PULLUP pullup_MIO_14
(.O(MIO[14]));
PULLUP pullup_MIO_15
(.O(MIO[15]));
PULLUP pullup_MIO_46
(.O(MIO[46]));
(* C_DM_WIDTH = "4" *)
(* C_DQS_WIDTH = "4" *)
(* C_DQ_WIDTH = "32" *)
(* C_EMIO_GPIO_WIDTH = "64" *)
(* C_EN_EMIO_ENET0 = "0" *)
(* C_EN_EMIO_ENET1 = "0" *)
(* C_EN_EMIO_PJTAG = "0" *)
(* C_EN_EMIO_TRACE = "0" *)
(* C_FCLK_CLK0_BUF = "TRUE" *)
(* C_FCLK_CLK1_BUF = "FALSE" *)
(* C_FCLK_CLK2_BUF = "FALSE" *)
(* C_FCLK_CLK3_BUF = "FALSE" *)
(* C_GP0_EN_MODIFIABLE_TXN = "0" *)
(* C_GP1_EN_MODIFIABLE_TXN = "0" *)
(* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
(* C_INCLUDE_TRACE_BUFFER = "0" *)
(* C_IRQ_F2P_MODE = "DIRECT" *)
(* C_MIO_PRIMITIVE = "54" *)
(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP0_ID_WIDTH = "12" *)
(* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP1_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
(* C_NUM_F2P_INTR_INPUTS = "1" *)
(* C_PACKAGE_NAME = "clg400" *)
(* C_PS7_SI_REV = "PRODUCTION" *)
(* C_S_AXI_ACP_ARUSER_VAL = "31" *)
(* C_S_AXI_ACP_AWUSER_VAL = "31" *)
(* C_S_AXI_ACP_ID_WIDTH = "3" *)
(* C_S_AXI_GP0_ID_WIDTH = "6" *)
(* C_S_AXI_GP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP0_DATA_WIDTH = "64" *)
(* C_S_AXI_HP0_ID_WIDTH = "6" *)
(* C_S_AXI_HP1_DATA_WIDTH = "64" *)
(* C_S_AXI_HP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP2_DATA_WIDTH = "64" *)
(* C_S_AXI_HP2_ID_WIDTH = "6" *)
(* C_S_AXI_HP3_DATA_WIDTH = "64" *)
(* C_S_AXI_HP3_ID_WIDTH = "6" *)
(* C_TRACE_BUFFER_CLOCK_DELAY = "12" *)
(* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
(* C_TRACE_INTERNAL_WIDTH = "2" *)
(* C_TRACE_PIPELINE_WIDTH = "8" *)
(* C_USE_AXI_NONSECURE = "0" *)
(* C_USE_DEFAULT_ACP_USER_VAL = "0" *)
(* C_USE_M_AXI_GP0 = "1" *)
(* C_USE_M_AXI_GP1 = "0" *)
(* C_USE_S_AXI_ACP = "0" *)
(* C_USE_S_AXI_GP0 = "0" *)
(* C_USE_S_AXI_GP1 = "0" *)
(* C_USE_S_AXI_HP0 = "0" *)
(* C_USE_S_AXI_HP1 = "0" *)
(* C_USE_S_AXI_HP2 = "0" *)
(* C_USE_S_AXI_HP3 = "0" *)
(* HW_HANDOFF = "design_1_processing_system7_0_0.hwdef" *)
(* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={650} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={3} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={5} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={I2C} ioStandard={LVCMOS33} bidis={3} ioBank={Vcco_p0} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
(* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 inst
(.CAN0_PHY_RX(1'b0),
.CAN0_PHY_TX(NLW_inst_CAN0_PHY_TX_UNCONNECTED),
.CAN1_PHY_RX(1'b0),
.CAN1_PHY_TX(NLW_inst_CAN1_PHY_TX_UNCONNECTED),
.Core0_nFIQ(1'b0),
.Core0_nIRQ(1'b0),
.Core1_nFIQ(1'b0),
.Core1_nIRQ(1'b0),
.DDR_ARB({1'b0,1'b0,1'b0,1'b0}),
.DDR_Addr(DDR_Addr),
.DDR_BankAddr(DDR_BankAddr),
.DDR_CAS_n(DDR_CAS_n),
.DDR_CKE(DDR_CKE),
.DDR_CS_n(DDR_CS_n),
.DDR_Clk(DDR_Clk),
.DDR_Clk_n(DDR_Clk_n),
.DDR_DM(DDR_DM),
.DDR_DQ(DDR_DQ),
.DDR_DQS(DDR_DQS),
.DDR_DQS_n(DDR_DQS_n),
.DDR_DRSTB(DDR_DRSTB),
.DDR_ODT(DDR_ODT),
.DDR_RAS_n(DDR_RAS_n),
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_WEB(DDR_WEB),
.DMA0_ACLK(1'b0),
.DMA0_DAREADY(1'b0),
.DMA0_DATYPE(NLW_inst_DMA0_DATYPE_UNCONNECTED[1:0]),
.DMA0_DAVALID(NLW_inst_DMA0_DAVALID_UNCONNECTED),
.DMA0_DRLAST(1'b0),
.DMA0_DRREADY(NLW_inst_DMA0_DRREADY_UNCONNECTED),
.DMA0_DRTYPE({1'b0,1'b0}),
.DMA0_DRVALID(1'b0),
.DMA0_RSTN(NLW_inst_DMA0_RSTN_UNCONNECTED),
.DMA1_ACLK(1'b0),
.DMA1_DAREADY(1'b0),
.DMA1_DATYPE(NLW_inst_DMA1_DATYPE_UNCONNECTED[1:0]),
.DMA1_DAVALID(NLW_inst_DMA1_DAVALID_UNCONNECTED),
.DMA1_DRLAST(1'b0),
.DMA1_DRREADY(NLW_inst_DMA1_DRREADY_UNCONNECTED),
.DMA1_DRTYPE({1'b0,1'b0}),
.DMA1_DRVALID(1'b0),
.DMA1_RSTN(NLW_inst_DMA1_RSTN_UNCONNECTED),
.DMA2_ACLK(1'b0),
.DMA2_DAREADY(1'b0),
.DMA2_DATYPE(NLW_inst_DMA2_DATYPE_UNCONNECTED[1:0]),
.DMA2_DAVALID(NLW_inst_DMA2_DAVALID_UNCONNECTED),
.DMA2_DRLAST(1'b0),
.DMA2_DRREADY(NLW_inst_DMA2_DRREADY_UNCONNECTED),
.DMA2_DRTYPE({1'b0,1'b0}),
.DMA2_DRVALID(1'b0),
.DMA2_RSTN(NLW_inst_DMA2_RSTN_UNCONNECTED),
.DMA3_ACLK(1'b0),
.DMA3_DAREADY(1'b0),
.DMA3_DATYPE(NLW_inst_DMA3_DATYPE_UNCONNECTED[1:0]),
.DMA3_DAVALID(NLW_inst_DMA3_DAVALID_UNCONNECTED),
.DMA3_DRLAST(1'b0),
.DMA3_DRREADY(NLW_inst_DMA3_DRREADY_UNCONNECTED),
.DMA3_DRTYPE({1'b0,1'b0}),
.DMA3_DRVALID(1'b0),
.DMA3_RSTN(NLW_inst_DMA3_RSTN_UNCONNECTED),
.ENET0_EXT_INTIN(1'b0),
.ENET0_GMII_COL(1'b0),
.ENET0_GMII_CRS(1'b0),
.ENET0_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ENET0_GMII_RX_CLK(1'b0),
.ENET0_GMII_RX_DV(1'b0),
.ENET0_GMII_RX_ER(1'b0),
.ENET0_GMII_TXD(NLW_inst_ENET0_GMII_TXD_UNCONNECTED[7:0]),
.ENET0_GMII_TX_CLK(1'b0),
.ENET0_GMII_TX_EN(NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED),
.ENET0_GMII_TX_ER(NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED),
.ENET0_MDIO_I(1'b0),
.ENET0_MDIO_MDC(NLW_inst_ENET0_MDIO_MDC_UNCONNECTED),
.ENET0_MDIO_O(NLW_inst_ENET0_MDIO_O_UNCONNECTED),
.ENET0_MDIO_T(NLW_inst_ENET0_MDIO_T_UNCONNECTED),
.ENET0_PTP_DELAY_REQ_RX(NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED),
.ENET0_PTP_DELAY_REQ_TX(NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED),
.ENET0_PTP_PDELAY_REQ_RX(NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED),
.ENET0_PTP_PDELAY_REQ_TX(NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED),
.ENET0_PTP_PDELAY_RESP_RX(NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED),
.ENET0_PTP_PDELAY_RESP_TX(NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED),
.ENET0_PTP_SYNC_FRAME_RX(NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED),
.ENET0_PTP_SYNC_FRAME_TX(NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED),
.ENET0_SOF_RX(NLW_inst_ENET0_SOF_RX_UNCONNECTED),
.ENET0_SOF_TX(NLW_inst_ENET0_SOF_TX_UNCONNECTED),
.ENET1_EXT_INTIN(1'b0),
.ENET1_GMII_COL(1'b0),
.ENET1_GMII_CRS(1'b0),
.ENET1_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ENET1_GMII_RX_CLK(1'b0),
.ENET1_GMII_RX_DV(1'b0),
.ENET1_GMII_RX_ER(1'b0),
.ENET1_GMII_TXD(NLW_inst_ENET1_GMII_TXD_UNCONNECTED[7:0]),
.ENET1_GMII_TX_CLK(1'b0),
.ENET1_GMII_TX_EN(NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED),
.ENET1_GMII_TX_ER(NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED),
.ENET1_MDIO_I(1'b0),
.ENET1_MDIO_MDC(NLW_inst_ENET1_MDIO_MDC_UNCONNECTED),
.ENET1_MDIO_O(NLW_inst_ENET1_MDIO_O_UNCONNECTED),
.ENET1_MDIO_T(NLW_inst_ENET1_MDIO_T_UNCONNECTED),
.ENET1_PTP_DELAY_REQ_RX(NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED),
.ENET1_PTP_DELAY_REQ_TX(NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED),
.ENET1_PTP_PDELAY_REQ_RX(NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED),
.ENET1_PTP_PDELAY_REQ_TX(NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED),
.ENET1_PTP_PDELAY_RESP_RX(NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED),
.ENET1_PTP_PDELAY_RESP_TX(NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED),
.ENET1_PTP_SYNC_FRAME_RX(NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED),
.ENET1_PTP_SYNC_FRAME_TX(NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED),
.ENET1_SOF_RX(NLW_inst_ENET1_SOF_RX_UNCONNECTED),
.ENET1_SOF_TX(NLW_inst_ENET1_SOF_TX_UNCONNECTED),
.EVENT_EVENTI(1'b0),
.EVENT_EVENTO(NLW_inst_EVENT_EVENTO_UNCONNECTED),
.EVENT_STANDBYWFE(NLW_inst_EVENT_STANDBYWFE_UNCONNECTED[1:0]),
.EVENT_STANDBYWFI(NLW_inst_EVENT_STANDBYWFI_UNCONNECTED[1:0]),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(NLW_inst_FCLK_CLK1_UNCONNECTED),
.FCLK_CLK2(NLW_inst_FCLK_CLK2_UNCONNECTED),
.FCLK_CLK3(NLW_inst_FCLK_CLK3_UNCONNECTED),
.FCLK_CLKTRIG0_N(1'b0),
.FCLK_CLKTRIG1_N(1'b0),
.FCLK_CLKTRIG2_N(1'b0),
.FCLK_CLKTRIG3_N(1'b0),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(NLW_inst_FCLK_RESET1_N_UNCONNECTED),
.FCLK_RESET2_N(NLW_inst_FCLK_RESET2_N_UNCONNECTED),
.FCLK_RESET3_N(NLW_inst_FCLK_RESET3_N_UNCONNECTED),
.FPGA_IDLE_N(1'b0),
.FTMD_TRACEIN_ATID({1'b0,1'b0,1'b0,1'b0}),
.FTMD_TRACEIN_CLK(1'b0),
.FTMD_TRACEIN_DATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMD_TRACEIN_VALID(1'b0),
.FTMT_F2P_DEBUG({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMT_F2P_TRIGACK_0(NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED),
.FTMT_F2P_TRIGACK_1(NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED),
.FTMT_F2P_TRIGACK_2(NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED),
.FTMT_F2P_TRIGACK_3(NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED),
.FTMT_F2P_TRIG_0(1'b0),
.FTMT_F2P_TRIG_1(1'b0),
.FTMT_F2P_TRIG_2(1'b0),
.FTMT_F2P_TRIG_3(1'b0),
.FTMT_P2F_DEBUG(NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED[31:0]),
.FTMT_P2F_TRIGACK_0(1'b0),
.FTMT_P2F_TRIGACK_1(1'b0),
.FTMT_P2F_TRIGACK_2(1'b0),
.FTMT_P2F_TRIGACK_3(1'b0),
.FTMT_P2F_TRIG_0(NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED),
.FTMT_P2F_TRIG_1(NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED),
.FTMT_P2F_TRIG_2(NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED),
.FTMT_P2F_TRIG_3(NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED),
.GPIO_I(GPIO_I),
.GPIO_O(GPIO_O),
.GPIO_T(GPIO_T),
.I2C0_SCL_I(1'b0),
.I2C0_SCL_O(NLW_inst_I2C0_SCL_O_UNCONNECTED),
.I2C0_SCL_T(NLW_inst_I2C0_SCL_T_UNCONNECTED),
.I2C0_SDA_I(1'b0),
.I2C0_SDA_O(NLW_inst_I2C0_SDA_O_UNCONNECTED),
.I2C0_SDA_T(NLW_inst_I2C0_SDA_T_UNCONNECTED),
.I2C1_SCL_I(1'b0),
.I2C1_SCL_O(NLW_inst_I2C1_SCL_O_UNCONNECTED),
.I2C1_SCL_T(NLW_inst_I2C1_SCL_T_UNCONNECTED),
.I2C1_SDA_I(1'b0),
.I2C1_SDA_O(NLW_inst_I2C1_SDA_O_UNCONNECTED),
.I2C1_SDA_T(NLW_inst_I2C1_SDA_T_UNCONNECTED),
.IRQ_F2P(IRQ_F2P),
.IRQ_P2F_CAN0(NLW_inst_IRQ_P2F_CAN0_UNCONNECTED),
.IRQ_P2F_CAN1(NLW_inst_IRQ_P2F_CAN1_UNCONNECTED),
.IRQ_P2F_CTI(NLW_inst_IRQ_P2F_CTI_UNCONNECTED),
.IRQ_P2F_DMAC0(NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED),
.IRQ_P2F_DMAC1(NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED),
.IRQ_P2F_DMAC2(NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED),
.IRQ_P2F_DMAC3(NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED),
.IRQ_P2F_DMAC4(NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED),
.IRQ_P2F_DMAC5(NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED),
.IRQ_P2F_DMAC6(NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED),
.IRQ_P2F_DMAC7(NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED),
.IRQ_P2F_DMAC_ABORT(NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED),
.IRQ_P2F_ENET0(NLW_inst_IRQ_P2F_ENET0_UNCONNECTED),
.IRQ_P2F_ENET1(NLW_inst_IRQ_P2F_ENET1_UNCONNECTED),
.IRQ_P2F_ENET_WAKE0(NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED),
.IRQ_P2F_ENET_WAKE1(NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED),
.IRQ_P2F_GPIO(NLW_inst_IRQ_P2F_GPIO_UNCONNECTED),
.IRQ_P2F_I2C0(NLW_inst_IRQ_P2F_I2C0_UNCONNECTED),
.IRQ_P2F_I2C1(NLW_inst_IRQ_P2F_I2C1_UNCONNECTED),
.IRQ_P2F_QSPI(NLW_inst_IRQ_P2F_QSPI_UNCONNECTED),
.IRQ_P2F_SDIO0(NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED),
.IRQ_P2F_SDIO1(NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED),
.IRQ_P2F_SMC(NLW_inst_IRQ_P2F_SMC_UNCONNECTED),
.IRQ_P2F_SPI0(NLW_inst_IRQ_P2F_SPI0_UNCONNECTED),
.IRQ_P2F_SPI1(NLW_inst_IRQ_P2F_SPI1_UNCONNECTED),
.IRQ_P2F_UART0(NLW_inst_IRQ_P2F_UART0_UNCONNECTED),
.IRQ_P2F_UART1(NLW_inst_IRQ_P2F_UART1_UNCONNECTED),
.IRQ_P2F_USB0(NLW_inst_IRQ_P2F_USB0_UNCONNECTED),
.IRQ_P2F_USB1(NLW_inst_IRQ_P2F_USB1_UNCONNECTED),
.MIO(MIO),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARESETN(NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP1_ACLK(1'b0),
.M_AXI_GP1_ARADDR(NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED[31:0]),
.M_AXI_GP1_ARBURST(NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED[1:0]),
.M_AXI_GP1_ARCACHE(NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED[3:0]),
.M_AXI_GP1_ARESETN(NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED),
.M_AXI_GP1_ARID(NLW_inst_M_AXI_GP1_ARID_UNCONNECTED[11:0]),
.M_AXI_GP1_ARLEN(NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED[3:0]),
.M_AXI_GP1_ARLOCK(NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED[1:0]),
.M_AXI_GP1_ARPROT(NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED[2:0]),
.M_AXI_GP1_ARQOS(NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED[3:0]),
.M_AXI_GP1_ARREADY(1'b0),
.M_AXI_GP1_ARSIZE(NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED[2:0]),
.M_AXI_GP1_ARVALID(NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED),
.M_AXI_GP1_AWADDR(NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED[31:0]),
.M_AXI_GP1_AWBURST(NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED[1:0]),
.M_AXI_GP1_AWCACHE(NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED[3:0]),
.M_AXI_GP1_AWID(NLW_inst_M_AXI_GP1_AWID_UNCONNECTED[11:0]),
.M_AXI_GP1_AWLEN(NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED[3:0]),
.M_AXI_GP1_AWLOCK(NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED[1:0]),
.M_AXI_GP1_AWPROT(NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED[2:0]),
.M_AXI_GP1_AWQOS(NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED[3:0]),
.M_AXI_GP1_AWREADY(1'b0),
.M_AXI_GP1_AWSIZE(NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED[2:0]),
.M_AXI_GP1_AWVALID(NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED),
.M_AXI_GP1_BID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_BREADY(NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED),
.M_AXI_GP1_BRESP({1'b0,1'b0}),
.M_AXI_GP1_BVALID(1'b0),
.M_AXI_GP1_RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_RID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_RLAST(1'b0),
.M_AXI_GP1_RREADY(NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED),
.M_AXI_GP1_RRESP({1'b0,1'b0}),
.M_AXI_GP1_RVALID(1'b0),
.M_AXI_GP1_WDATA(NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED[31:0]),
.M_AXI_GP1_WID(NLW_inst_M_AXI_GP1_WID_UNCONNECTED[11:0]),
.M_AXI_GP1_WLAST(NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED),
.M_AXI_GP1_WREADY(1'b0),
.M_AXI_GP1_WSTRB(NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED[3:0]),
.M_AXI_GP1_WVALID(NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED),
.PJTAG_TCK(1'b0),
.PJTAG_TDI(1'b0),
.PJTAG_TDO(NLW_inst_PJTAG_TDO_UNCONNECTED),
.PJTAG_TMS(1'b0),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB),
.PS_SRSTB(PS_SRSTB),
.SDIO0_BUSPOW(NLW_inst_SDIO0_BUSPOW_UNCONNECTED),
.SDIO0_BUSVOLT(NLW_inst_SDIO0_BUSVOLT_UNCONNECTED[2:0]),
.SDIO0_CDN(1'b0),
.SDIO0_CLK(NLW_inst_SDIO0_CLK_UNCONNECTED),
.SDIO0_CLK_FB(1'b0),
.SDIO0_CMD_I(1'b0),
.SDIO0_CMD_O(NLW_inst_SDIO0_CMD_O_UNCONNECTED),
.SDIO0_CMD_T(NLW_inst_SDIO0_CMD_T_UNCONNECTED),
.SDIO0_DATA_I({1'b0,1'b0,1'b0,1'b0}),
.SDIO0_DATA_O(NLW_inst_SDIO0_DATA_O_UNCONNECTED[3:0]),
.SDIO0_DATA_T(NLW_inst_SDIO0_DATA_T_UNCONNECTED[3:0]),
.SDIO0_LED(NLW_inst_SDIO0_LED_UNCONNECTED),
.SDIO0_WP(SDIO0_WP),
.SDIO1_BUSPOW(NLW_inst_SDIO1_BUSPOW_UNCONNECTED),
.SDIO1_BUSVOLT(NLW_inst_SDIO1_BUSVOLT_UNCONNECTED[2:0]),
.SDIO1_CDN(1'b0),
.SDIO1_CLK(NLW_inst_SDIO1_CLK_UNCONNECTED),
.SDIO1_CLK_FB(1'b0),
.SDIO1_CMD_I(1'b0),
.SDIO1_CMD_O(NLW_inst_SDIO1_CMD_O_UNCONNECTED),
.SDIO1_CMD_T(NLW_inst_SDIO1_CMD_T_UNCONNECTED),
.SDIO1_DATA_I({1'b0,1'b0,1'b0,1'b0}),
.SDIO1_DATA_O(NLW_inst_SDIO1_DATA_O_UNCONNECTED[3:0]),
.SDIO1_DATA_T(NLW_inst_SDIO1_DATA_T_UNCONNECTED[3:0]),
.SDIO1_LED(NLW_inst_SDIO1_LED_UNCONNECTED),
.SDIO1_WP(1'b0),
.SPI0_MISO_I(1'b0),
.SPI0_MISO_O(NLW_inst_SPI0_MISO_O_UNCONNECTED),
.SPI0_MISO_T(NLW_inst_SPI0_MISO_T_UNCONNECTED),
.SPI0_MOSI_I(1'b0),
.SPI0_MOSI_O(NLW_inst_SPI0_MOSI_O_UNCONNECTED),
.SPI0_MOSI_T(NLW_inst_SPI0_MOSI_T_UNCONNECTED),
.SPI0_SCLK_I(1'b0),
.SPI0_SCLK_O(NLW_inst_SPI0_SCLK_O_UNCONNECTED),
.SPI0_SCLK_T(NLW_inst_SPI0_SCLK_T_UNCONNECTED),
.SPI0_SS1_O(NLW_inst_SPI0_SS1_O_UNCONNECTED),
.SPI0_SS2_O(NLW_inst_SPI0_SS2_O_UNCONNECTED),
.SPI0_SS_I(1'b0),
.SPI0_SS_O(NLW_inst_SPI0_SS_O_UNCONNECTED),
.SPI0_SS_T(NLW_inst_SPI0_SS_T_UNCONNECTED),
.SPI1_MISO_I(1'b0),
.SPI1_MISO_O(NLW_inst_SPI1_MISO_O_UNCONNECTED),
.SPI1_MISO_T(NLW_inst_SPI1_MISO_T_UNCONNECTED),
.SPI1_MOSI_I(1'b0),
.SPI1_MOSI_O(NLW_inst_SPI1_MOSI_O_UNCONNECTED),
.SPI1_MOSI_T(NLW_inst_SPI1_MOSI_T_UNCONNECTED),
.SPI1_SCLK_I(1'b0),
.SPI1_SCLK_O(NLW_inst_SPI1_SCLK_O_UNCONNECTED),
.SPI1_SCLK_T(NLW_inst_SPI1_SCLK_T_UNCONNECTED),
.SPI1_SS1_O(NLW_inst_SPI1_SS1_O_UNCONNECTED),
.SPI1_SS2_O(NLW_inst_SPI1_SS2_O_UNCONNECTED),
.SPI1_SS_I(1'b0),
.SPI1_SS_O(NLW_inst_SPI1_SS_O_UNCONNECTED),
.SPI1_SS_T(NLW_inst_SPI1_SS_T_UNCONNECTED),
.SRAM_INTIN(1'b0),
.S_AXI_ACP_ACLK(1'b0),
.S_AXI_ACP_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARBURST({1'b0,1'b0}),
.S_AXI_ACP_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARESETN(NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED),
.S_AXI_ACP_ARID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARLOCK({1'b0,1'b0}),
.S_AXI_ACP_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARREADY(NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED),
.S_AXI_ACP_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARVALID(1'b0),
.S_AXI_ACP_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWBURST({1'b0,1'b0}),
.S_AXI_ACP_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWLOCK({1'b0,1'b0}),
.S_AXI_ACP_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWREADY(NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED),
.S_AXI_ACP_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWVALID(1'b0),
.S_AXI_ACP_BID(NLW_inst_S_AXI_ACP_BID_UNCONNECTED[2:0]),
.S_AXI_ACP_BREADY(1'b0),
.S_AXI_ACP_BRESP(NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED[1:0]),
.S_AXI_ACP_BVALID(NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED),
.S_AXI_ACP_RDATA(NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED[63:0]),
.S_AXI_ACP_RID(NLW_inst_S_AXI_ACP_RID_UNCONNECTED[2:0]),
.S_AXI_ACP_RLAST(NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED),
.S_AXI_ACP_RREADY(1'b0),
.S_AXI_ACP_RRESP(NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED[1:0]),
.S_AXI_ACP_RVALID(NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED),
.S_AXI_ACP_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_WID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_WLAST(1'b0),
.S_AXI_ACP_WREADY(NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED),
.S_AXI_ACP_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_WVALID(1'b0),
.S_AXI_GP0_ACLK(1'b0),
.S_AXI_GP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARBURST({1'b0,1'b0}),
.S_AXI_GP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARESETN(NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED),
.S_AXI_GP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARLOCK({1'b0,1'b0}),
.S_AXI_GP0_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARREADY(NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED),
.S_AXI_GP0_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARVALID(1'b0),
.S_AXI_GP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWBURST({1'b0,1'b0}),
.S_AXI_GP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWLOCK({1'b0,1'b0}),
.S_AXI_GP0_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWREADY(NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED),
.S_AXI_GP0_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWVALID(1'b0),
.S_AXI_GP0_BID(NLW_inst_S_AXI_GP0_BID_UNCONNECTED[5:0]),
.S_AXI_GP0_BREADY(1'b0),
.S_AXI_GP0_BRESP(NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED[1:0]),
.S_AXI_GP0_BVALID(NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED),
.S_AXI_GP0_RDATA(NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED[31:0]),
.S_AXI_GP0_RID(NLW_inst_S_AXI_GP0_RID_UNCONNECTED[5:0]),
.S_AXI_GP0_RLAST(NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED),
.S_AXI_GP0_RREADY(1'b0),
.S_AXI_GP0_RRESP(NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED[1:0]),
.S_AXI_GP0_RVALID(NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED),
.S_AXI_GP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WLAST(1'b0),
.S_AXI_GP0_WREADY(NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED),
.S_AXI_GP0_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WVALID(1'b0),
.S_AXI_GP1_ACLK(1'b0),
.S_AXI_GP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARBURST({1'b0,1'b0}),
.S_AXI_GP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARESETN(NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED),
.S_AXI_GP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARLOCK({1'b0,1'b0}),
.S_AXI_GP1_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARREADY(NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED),
.S_AXI_GP1_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARVALID(1'b0),
.S_AXI_GP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWBURST({1'b0,1'b0}),
.S_AXI_GP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWLOCK({1'b0,1'b0}),
.S_AXI_GP1_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWREADY(NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED),
.S_AXI_GP1_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWVALID(1'b0),
.S_AXI_GP1_BID(NLW_inst_S_AXI_GP1_BID_UNCONNECTED[5:0]),
.S_AXI_GP1_BREADY(1'b0),
.S_AXI_GP1_BRESP(NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED[1:0]),
.S_AXI_GP1_BVALID(NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED),
.S_AXI_GP1_RDATA(NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED[31:0]),
.S_AXI_GP1_RID(NLW_inst_S_AXI_GP1_RID_UNCONNECTED[5:0]),
.S_AXI_GP1_RLAST(NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED),
.S_AXI_GP1_RREADY(1'b0),
.S_AXI_GP1_RRESP(NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED[1:0]),
.S_AXI_GP1_RVALID(NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED),
.S_AXI_GP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WLAST(1'b0),
.S_AXI_GP1_WREADY(NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED),
.S_AXI_GP1_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WVALID(1'b0),
.S_AXI_HP0_ACLK(1'b0),
.S_AXI_HP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARBURST({1'b0,1'b0}),
.S_AXI_HP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARESETN(NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED),
.S_AXI_HP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLOCK({1'b0,1'b0}),
.S_AXI_HP0_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARREADY(NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED),
.S_AXI_HP0_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARVALID(1'b0),
.S_AXI_HP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWBURST({1'b0,1'b0}),
.S_AXI_HP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLOCK({1'b0,1'b0}),
.S_AXI_HP0_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWREADY(NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED),
.S_AXI_HP0_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWVALID(1'b0),
.S_AXI_HP0_BID(NLW_inst_S_AXI_HP0_BID_UNCONNECTED[5:0]),
.S_AXI_HP0_BREADY(1'b0),
.S_AXI_HP0_BRESP(NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP0_BVALID(NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED),
.S_AXI_HP0_RACOUNT(NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP0_RCOUNT(NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP0_RDATA(NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP0_RDISSUECAP1_EN(1'b0),
.S_AXI_HP0_RID(NLW_inst_S_AXI_HP0_RID_UNCONNECTED[5:0]),
.S_AXI_HP0_RLAST(NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED),
.S_AXI_HP0_RREADY(1'b0),
.S_AXI_HP0_RRESP(NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP0_RVALID(NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED),
.S_AXI_HP0_WACOUNT(NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP0_WCOUNT(NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WLAST(1'b0),
.S_AXI_HP0_WREADY(NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED),
.S_AXI_HP0_WRISSUECAP1_EN(1'b0),
.S_AXI_HP0_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WVALID(1'b0),
.S_AXI_HP1_ACLK(1'b0),
.S_AXI_HP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARBURST({1'b0,1'b0}),
.S_AXI_HP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARESETN(NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED),
.S_AXI_HP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARLOCK({1'b0,1'b0}),
.S_AXI_HP1_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARREADY(NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED),
.S_AXI_HP1_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARVALID(1'b0),
.S_AXI_HP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWBURST({1'b0,1'b0}),
.S_AXI_HP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWLOCK({1'b0,1'b0}),
.S_AXI_HP1_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWREADY(NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED),
.S_AXI_HP1_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWVALID(1'b0),
.S_AXI_HP1_BID(NLW_inst_S_AXI_HP1_BID_UNCONNECTED[5:0]),
.S_AXI_HP1_BREADY(1'b0),
.S_AXI_HP1_BRESP(NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP1_BVALID(NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED),
.S_AXI_HP1_RACOUNT(NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP1_RCOUNT(NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP1_RDATA(NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP1_RDISSUECAP1_EN(1'b0),
.S_AXI_HP1_RID(NLW_inst_S_AXI_HP1_RID_UNCONNECTED[5:0]),
.S_AXI_HP1_RLAST(NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED),
.S_AXI_HP1_RREADY(1'b0),
.S_AXI_HP1_RRESP(NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP1_RVALID(NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED),
.S_AXI_HP1_WACOUNT(NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP1_WCOUNT(NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WLAST(1'b0),
.S_AXI_HP1_WREADY(NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED),
.S_AXI_HP1_WRISSUECAP1_EN(1'b0),
.S_AXI_HP1_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WVALID(1'b0),
.S_AXI_HP2_ACLK(1'b0),
.S_AXI_HP2_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARBURST({1'b0,1'b0}),
.S_AXI_HP2_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARESETN(NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED),
.S_AXI_HP2_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLOCK({1'b0,1'b0}),
.S_AXI_HP2_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARREADY(NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED),
.S_AXI_HP2_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARVALID(1'b0),
.S_AXI_HP2_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWBURST({1'b0,1'b0}),
.S_AXI_HP2_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLOCK({1'b0,1'b0}),
.S_AXI_HP2_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWREADY(NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED),
.S_AXI_HP2_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWVALID(1'b0),
.S_AXI_HP2_BID(NLW_inst_S_AXI_HP2_BID_UNCONNECTED[5:0]),
.S_AXI_HP2_BREADY(1'b0),
.S_AXI_HP2_BRESP(NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP2_BVALID(NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED),
.S_AXI_HP2_RACOUNT(NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP2_RCOUNT(NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP2_RDATA(NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP2_RDISSUECAP1_EN(1'b0),
.S_AXI_HP2_RID(NLW_inst_S_AXI_HP2_RID_UNCONNECTED[5:0]),
.S_AXI_HP2_RLAST(NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED),
.S_AXI_HP2_RREADY(1'b0),
.S_AXI_HP2_RRESP(NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP2_RVALID(NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED),
.S_AXI_HP2_WACOUNT(NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP2_WCOUNT(NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP2_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WLAST(1'b0),
.S_AXI_HP2_WREADY(NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED),
.S_AXI_HP2_WRISSUECAP1_EN(1'b0),
.S_AXI_HP2_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WVALID(1'b0),
.S_AXI_HP3_ACLK(1'b0),
.S_AXI_HP3_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARBURST({1'b0,1'b0}),
.S_AXI_HP3_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARESETN(NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED),
.S_AXI_HP3_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARLOCK({1'b0,1'b0}),
.S_AXI_HP3_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARREADY(NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED),
.S_AXI_HP3_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARVALID(1'b0),
.S_AXI_HP3_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWBURST({1'b0,1'b0}),
.S_AXI_HP3_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWLOCK({1'b0,1'b0}),
.S_AXI_HP3_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWREADY(NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED),
.S_AXI_HP3_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWVALID(1'b0),
.S_AXI_HP3_BID(NLW_inst_S_AXI_HP3_BID_UNCONNECTED[5:0]),
.S_AXI_HP3_BREADY(1'b0),
.S_AXI_HP3_BRESP(NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP3_BVALID(NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED),
.S_AXI_HP3_RACOUNT(NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP3_RCOUNT(NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP3_RDATA(NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP3_RDISSUECAP1_EN(1'b0),
.S_AXI_HP3_RID(NLW_inst_S_AXI_HP3_RID_UNCONNECTED[5:0]),
.S_AXI_HP3_RLAST(NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED),
.S_AXI_HP3_RREADY(1'b0),
.S_AXI_HP3_RRESP(NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP3_RVALID(NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED),
.S_AXI_HP3_WACOUNT(NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP3_WCOUNT(NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP3_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WLAST(1'b0),
.S_AXI_HP3_WREADY(NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED),
.S_AXI_HP3_WRISSUECAP1_EN(1'b0),
.S_AXI_HP3_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WVALID(1'b0),
.TRACE_CLK(1'b0),
.TRACE_CLK_OUT(NLW_inst_TRACE_CLK_OUT_UNCONNECTED),
.TRACE_CTL(NLW_inst_TRACE_CTL_UNCONNECTED),
.TRACE_DATA(NLW_inst_TRACE_DATA_UNCONNECTED[1:0]),
.TTC0_CLK0_IN(1'b0),
.TTC0_CLK1_IN(1'b0),
.TTC0_CLK2_IN(1'b0),
.TTC0_WAVE0_OUT(TTC0_WAVE0_OUT),
.TTC0_WAVE1_OUT(TTC0_WAVE1_OUT),
.TTC0_WAVE2_OUT(TTC0_WAVE2_OUT),
.TTC1_CLK0_IN(1'b0),
.TTC1_CLK1_IN(1'b0),
.TTC1_CLK2_IN(1'b0),
.TTC1_WAVE0_OUT(NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED),
.TTC1_WAVE1_OUT(NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED),
.TTC1_WAVE2_OUT(NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED),
.UART0_CTSN(1'b0),
.UART0_DCDN(1'b0),
.UART0_DSRN(1'b0),
.UART0_DTRN(NLW_inst_UART0_DTRN_UNCONNECTED),
.UART0_RIN(1'b0),
.UART0_RTSN(NLW_inst_UART0_RTSN_UNCONNECTED),
.UART0_RX(1'b1),
.UART0_TX(NLW_inst_UART0_TX_UNCONNECTED),
.UART1_CTSN(1'b0),
.UART1_DCDN(1'b0),
.UART1_DSRN(1'b0),
.UART1_DTRN(NLW_inst_UART1_DTRN_UNCONNECTED),
.UART1_RIN(1'b0),
.UART1_RTSN(NLW_inst_UART1_RTSN_UNCONNECTED),
.UART1_RX(1'b1),
.UART1_TX(NLW_inst_UART1_TX_UNCONNECTED),
.USB0_PORT_INDCTL(USB0_PORT_INDCTL),
.USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
.USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
.USB1_PORT_INDCTL(NLW_inst_USB1_PORT_INDCTL_UNCONNECTED[1:0]),
.USB1_VBUS_PWRFAULT(1'b0),
.USB1_VBUS_PWRSELECT(NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED),
.WDT_CLK_IN(1'b0),
.WDT_RST_OUT(NLW_inst_WDT_RST_OUT_UNCONNECTED));
endmodule
(* C_DM_WIDTH = "4" *) (* C_DQS_WIDTH = "4" *) (* C_DQ_WIDTH = "32" *)
(* C_EMIO_GPIO_WIDTH = "64" *) (* C_EN_EMIO_ENET0 = "0" *) (* C_EN_EMIO_ENET1 = "0" *)
(* C_EN_EMIO_PJTAG = "0" *) (* C_EN_EMIO_TRACE = "0" *) (* C_FCLK_CLK0_BUF = "TRUE" *)
(* C_FCLK_CLK1_BUF = "FALSE" *) (* C_FCLK_CLK2_BUF = "FALSE" *) (* C_FCLK_CLK3_BUF = "FALSE" *)
(* C_GP0_EN_MODIFIABLE_TXN = "0" *) (* C_GP1_EN_MODIFIABLE_TXN = "0" *) (* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
(* C_INCLUDE_TRACE_BUFFER = "0" *) (* C_IRQ_F2P_MODE = "DIRECT" *) (* C_MIO_PRIMITIVE = "54" *)
(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP0_ID_WIDTH = "12" *) (* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP1_ID_WIDTH = "12" *) (* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
(* C_NUM_F2P_INTR_INPUTS = "1" *) (* C_PACKAGE_NAME = "clg400" *) (* C_PS7_SI_REV = "PRODUCTION" *)
(* C_S_AXI_ACP_ARUSER_VAL = "31" *) (* C_S_AXI_ACP_AWUSER_VAL = "31" *) (* C_S_AXI_ACP_ID_WIDTH = "3" *)
(* C_S_AXI_GP0_ID_WIDTH = "6" *) (* C_S_AXI_GP1_ID_WIDTH = "6" *) (* C_S_AXI_HP0_DATA_WIDTH = "64" *)
(* C_S_AXI_HP0_ID_WIDTH = "6" *) (* C_S_AXI_HP1_DATA_WIDTH = "64" *) (* C_S_AXI_HP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP2_DATA_WIDTH = "64" *) (* C_S_AXI_HP2_ID_WIDTH = "6" *) (* C_S_AXI_HP3_DATA_WIDTH = "64" *)
(* C_S_AXI_HP3_ID_WIDTH = "6" *) (* C_TRACE_BUFFER_CLOCK_DELAY = "12" *) (* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
(* C_TRACE_INTERNAL_WIDTH = "2" *) (* C_TRACE_PIPELINE_WIDTH = "8" *) (* C_USE_AXI_NONSECURE = "0" *)
(* C_USE_DEFAULT_ACP_USER_VAL = "0" *) (* C_USE_M_AXI_GP0 = "1" *) (* C_USE_M_AXI_GP1 = "0" *)
(* C_USE_S_AXI_ACP = "0" *) (* C_USE_S_AXI_GP0 = "0" *) (* C_USE_S_AXI_GP1 = "0" *)
(* C_USE_S_AXI_HP0 = "0" *) (* C_USE_S_AXI_HP1 = "0" *) (* C_USE_S_AXI_HP2 = "0" *)
(* C_USE_S_AXI_HP3 = "0" *) (* HW_HANDOFF = "design_1_processing_system7_0_0.hwdef" *) (* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={650} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={3} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={5} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={I2C} ioStandard={LVCMOS33} bidis={3} ioBank={Vcco_p0} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p0} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
(* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7
(CAN0_PHY_TX,
CAN0_PHY_RX,
CAN1_PHY_TX,
CAN1_PHY_RX,
ENET0_GMII_TX_EN,
ENET0_GMII_TX_ER,
ENET0_MDIO_MDC,
ENET0_MDIO_O,
ENET0_MDIO_T,
ENET0_PTP_DELAY_REQ_RX,
ENET0_PTP_DELAY_REQ_TX,
ENET0_PTP_PDELAY_REQ_RX,
ENET0_PTP_PDELAY_REQ_TX,
ENET0_PTP_PDELAY_RESP_RX,
ENET0_PTP_PDELAY_RESP_TX,
ENET0_PTP_SYNC_FRAME_RX,
ENET0_PTP_SYNC_FRAME_TX,
ENET0_SOF_RX,
ENET0_SOF_TX,
ENET0_GMII_TXD,
ENET0_GMII_COL,
ENET0_GMII_CRS,
ENET0_GMII_RX_CLK,
ENET0_GMII_RX_DV,
ENET0_GMII_RX_ER,
ENET0_GMII_TX_CLK,
ENET0_MDIO_I,
ENET0_EXT_INTIN,
ENET0_GMII_RXD,
ENET1_GMII_TX_EN,
ENET1_GMII_TX_ER,
ENET1_MDIO_MDC,
ENET1_MDIO_O,
ENET1_MDIO_T,
ENET1_PTP_DELAY_REQ_RX,
ENET1_PTP_DELAY_REQ_TX,
ENET1_PTP_PDELAY_REQ_RX,
ENET1_PTP_PDELAY_REQ_TX,
ENET1_PTP_PDELAY_RESP_RX,
ENET1_PTP_PDELAY_RESP_TX,
ENET1_PTP_SYNC_FRAME_RX,
ENET1_PTP_SYNC_FRAME_TX,
ENET1_SOF_RX,
ENET1_SOF_TX,
ENET1_GMII_TXD,
ENET1_GMII_COL,
ENET1_GMII_CRS,
ENET1_GMII_RX_CLK,
ENET1_GMII_RX_DV,
ENET1_GMII_RX_ER,
ENET1_GMII_TX_CLK,
ENET1_MDIO_I,
ENET1_EXT_INTIN,
ENET1_GMII_RXD,
GPIO_I,
GPIO_O,
GPIO_T,
I2C0_SDA_I,
I2C0_SDA_O,
I2C0_SDA_T,
I2C0_SCL_I,
I2C0_SCL_O,
I2C0_SCL_T,
I2C1_SDA_I,
I2C1_SDA_O,
I2C1_SDA_T,
I2C1_SCL_I,
I2C1_SCL_O,
I2C1_SCL_T,
PJTAG_TCK,
PJTAG_TMS,
PJTAG_TDI,
PJTAG_TDO,
SDIO0_CLK,
SDIO0_CLK_FB,
SDIO0_CMD_O,
SDIO0_CMD_I,
SDIO0_CMD_T,
SDIO0_DATA_I,
SDIO0_DATA_O,
SDIO0_DATA_T,
SDIO0_LED,
SDIO0_CDN,
SDIO0_WP,
SDIO0_BUSPOW,
SDIO0_BUSVOLT,
SDIO1_CLK,
SDIO1_CLK_FB,
SDIO1_CMD_O,
SDIO1_CMD_I,
SDIO1_CMD_T,
SDIO1_DATA_I,
SDIO1_DATA_O,
SDIO1_DATA_T,
SDIO1_LED,
SDIO1_CDN,
SDIO1_WP,
SDIO1_BUSPOW,
SDIO1_BUSVOLT,
SPI0_SCLK_I,
SPI0_SCLK_O,
SPI0_SCLK_T,
SPI0_MOSI_I,
SPI0_MOSI_O,
SPI0_MOSI_T,
SPI0_MISO_I,
SPI0_MISO_O,
SPI0_MISO_T,
SPI0_SS_I,
SPI0_SS_O,
SPI0_SS1_O,
SPI0_SS2_O,
SPI0_SS_T,
SPI1_SCLK_I,
SPI1_SCLK_O,
SPI1_SCLK_T,
SPI1_MOSI_I,
SPI1_MOSI_O,
SPI1_MOSI_T,
SPI1_MISO_I,
SPI1_MISO_O,
SPI1_MISO_T,
SPI1_SS_I,
SPI1_SS_O,
SPI1_SS1_O,
SPI1_SS2_O,
SPI1_SS_T,
UART0_DTRN,
UART0_RTSN,
UART0_TX,
UART0_CTSN,
UART0_DCDN,
UART0_DSRN,
UART0_RIN,
UART0_RX,
UART1_DTRN,
UART1_RTSN,
UART1_TX,
UART1_CTSN,
UART1_DCDN,
UART1_DSRN,
UART1_RIN,
UART1_RX,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
TTC0_CLK0_IN,
TTC0_CLK1_IN,
TTC0_CLK2_IN,
TTC1_WAVE0_OUT,
TTC1_WAVE1_OUT,
TTC1_WAVE2_OUT,
TTC1_CLK0_IN,
TTC1_CLK1_IN,
TTC1_CLK2_IN,
WDT_CLK_IN,
WDT_RST_OUT,
TRACE_CLK,
TRACE_CTL,
TRACE_DATA,
TRACE_CLK_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
USB1_PORT_INDCTL,
USB1_VBUS_PWRSELECT,
USB1_VBUS_PWRFAULT,
SRAM_INTIN,
M_AXI_GP0_ARESETN,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
M_AXI_GP1_ARESETN,
M_AXI_GP1_ARVALID,
M_AXI_GP1_AWVALID,
M_AXI_GP1_BREADY,
M_AXI_GP1_RREADY,
M_AXI_GP1_WLAST,
M_AXI_GP1_WVALID,
M_AXI_GP1_ARID,
M_AXI_GP1_AWID,
M_AXI_GP1_WID,
M_AXI_GP1_ARBURST,
M_AXI_GP1_ARLOCK,
M_AXI_GP1_ARSIZE,
M_AXI_GP1_AWBURST,
M_AXI_GP1_AWLOCK,
M_AXI_GP1_AWSIZE,
M_AXI_GP1_ARPROT,
M_AXI_GP1_AWPROT,
M_AXI_GP1_ARADDR,
M_AXI_GP1_AWADDR,
M_AXI_GP1_WDATA,
M_AXI_GP1_ARCACHE,
M_AXI_GP1_ARLEN,
M_AXI_GP1_ARQOS,
M_AXI_GP1_AWCACHE,
M_AXI_GP1_AWLEN,
M_AXI_GP1_AWQOS,
M_AXI_GP1_WSTRB,
M_AXI_GP1_ACLK,
M_AXI_GP1_ARREADY,
M_AXI_GP1_AWREADY,
M_AXI_GP1_BVALID,
M_AXI_GP1_RLAST,
M_AXI_GP1_RVALID,
M_AXI_GP1_WREADY,
M_AXI_GP1_BID,
M_AXI_GP1_RID,
M_AXI_GP1_BRESP,
M_AXI_GP1_RRESP,
M_AXI_GP1_RDATA,
S_AXI_GP0_ARESETN,
S_AXI_GP0_ARREADY,
S_AXI_GP0_AWREADY,
S_AXI_GP0_BVALID,
S_AXI_GP0_RLAST,
S_AXI_GP0_RVALID,
S_AXI_GP0_WREADY,
S_AXI_GP0_BRESP,
S_AXI_GP0_RRESP,
S_AXI_GP0_RDATA,
S_AXI_GP0_BID,
S_AXI_GP0_RID,
S_AXI_GP0_ACLK,
S_AXI_GP0_ARVALID,
S_AXI_GP0_AWVALID,
S_AXI_GP0_BREADY,
S_AXI_GP0_RREADY,
S_AXI_GP0_WLAST,
S_AXI_GP0_WVALID,
S_AXI_GP0_ARBURST,
S_AXI_GP0_ARLOCK,
S_AXI_GP0_ARSIZE,
S_AXI_GP0_AWBURST,
S_AXI_GP0_AWLOCK,
S_AXI_GP0_AWSIZE,
S_AXI_GP0_ARPROT,
S_AXI_GP0_AWPROT,
S_AXI_GP0_ARADDR,
S_AXI_GP0_AWADDR,
S_AXI_GP0_WDATA,
S_AXI_GP0_ARCACHE,
S_AXI_GP0_ARLEN,
S_AXI_GP0_ARQOS,
S_AXI_GP0_AWCACHE,
S_AXI_GP0_AWLEN,
S_AXI_GP0_AWQOS,
S_AXI_GP0_WSTRB,
S_AXI_GP0_ARID,
S_AXI_GP0_AWID,
S_AXI_GP0_WID,
S_AXI_GP1_ARESETN,
S_AXI_GP1_ARREADY,
S_AXI_GP1_AWREADY,
S_AXI_GP1_BVALID,
S_AXI_GP1_RLAST,
S_AXI_GP1_RVALID,
S_AXI_GP1_WREADY,
S_AXI_GP1_BRESP,
S_AXI_GP1_RRESP,
S_AXI_GP1_RDATA,
S_AXI_GP1_BID,
S_AXI_GP1_RID,
S_AXI_GP1_ACLK,
S_AXI_GP1_ARVALID,
S_AXI_GP1_AWVALID,
S_AXI_GP1_BREADY,
S_AXI_GP1_RREADY,
S_AXI_GP1_WLAST,
S_AXI_GP1_WVALID,
S_AXI_GP1_ARBURST,
S_AXI_GP1_ARLOCK,
S_AXI_GP1_ARSIZE,
S_AXI_GP1_AWBURST,
S_AXI_GP1_AWLOCK,
S_AXI_GP1_AWSIZE,
S_AXI_GP1_ARPROT,
S_AXI_GP1_AWPROT,
S_AXI_GP1_ARADDR,
S_AXI_GP1_AWADDR,
S_AXI_GP1_WDATA,
S_AXI_GP1_ARCACHE,
S_AXI_GP1_ARLEN,
S_AXI_GP1_ARQOS,
S_AXI_GP1_AWCACHE,
S_AXI_GP1_AWLEN,
S_AXI_GP1_AWQOS,
S_AXI_GP1_WSTRB,
S_AXI_GP1_ARID,
S_AXI_GP1_AWID,
S_AXI_GP1_WID,
S_AXI_ACP_ARESETN,
S_AXI_ACP_ARREADY,
S_AXI_ACP_AWREADY,
S_AXI_ACP_BVALID,
S_AXI_ACP_RLAST,
S_AXI_ACP_RVALID,
S_AXI_ACP_WREADY,
S_AXI_ACP_BRESP,
S_AXI_ACP_RRESP,
S_AXI_ACP_BID,
S_AXI_ACP_RID,
S_AXI_ACP_RDATA,
S_AXI_ACP_ACLK,
S_AXI_ACP_ARVALID,
S_AXI_ACP_AWVALID,
S_AXI_ACP_BREADY,
S_AXI_ACP_RREADY,
S_AXI_ACP_WLAST,
S_AXI_ACP_WVALID,
S_AXI_ACP_ARID,
S_AXI_ACP_ARPROT,
S_AXI_ACP_AWID,
S_AXI_ACP_AWPROT,
S_AXI_ACP_WID,
S_AXI_ACP_ARADDR,
S_AXI_ACP_AWADDR,
S_AXI_ACP_ARCACHE,
S_AXI_ACP_ARLEN,
S_AXI_ACP_ARQOS,
S_AXI_ACP_AWCACHE,
S_AXI_ACP_AWLEN,
S_AXI_ACP_AWQOS,
S_AXI_ACP_ARBURST,
S_AXI_ACP_ARLOCK,
S_AXI_ACP_ARSIZE,
S_AXI_ACP_AWBURST,
S_AXI_ACP_AWLOCK,
S_AXI_ACP_AWSIZE,
S_AXI_ACP_ARUSER,
S_AXI_ACP_AWUSER,
S_AXI_ACP_WDATA,
S_AXI_ACP_WSTRB,
S_AXI_HP0_ARESETN,
S_AXI_HP0_ARREADY,
S_AXI_HP0_AWREADY,
S_AXI_HP0_BVALID,
S_AXI_HP0_RLAST,
S_AXI_HP0_RVALID,
S_AXI_HP0_WREADY,
S_AXI_HP0_BRESP,
S_AXI_HP0_RRESP,
S_AXI_HP0_BID,
S_AXI_HP0_RID,
S_AXI_HP0_RDATA,
S_AXI_HP0_RCOUNT,
S_AXI_HP0_WCOUNT,
S_AXI_HP0_RACOUNT,
S_AXI_HP0_WACOUNT,
S_AXI_HP0_ACLK,
S_AXI_HP0_ARVALID,
S_AXI_HP0_AWVALID,
S_AXI_HP0_BREADY,
S_AXI_HP0_RDISSUECAP1_EN,
S_AXI_HP0_RREADY,
S_AXI_HP0_WLAST,
S_AXI_HP0_WRISSUECAP1_EN,
S_AXI_HP0_WVALID,
S_AXI_HP0_ARBURST,
S_AXI_HP0_ARLOCK,
S_AXI_HP0_ARSIZE,
S_AXI_HP0_AWBURST,
S_AXI_HP0_AWLOCK,
S_AXI_HP0_AWSIZE,
S_AXI_HP0_ARPROT,
S_AXI_HP0_AWPROT,
S_AXI_HP0_ARADDR,
S_AXI_HP0_AWADDR,
S_AXI_HP0_ARCACHE,
S_AXI_HP0_ARLEN,
S_AXI_HP0_ARQOS,
S_AXI_HP0_AWCACHE,
S_AXI_HP0_AWLEN,
S_AXI_HP0_AWQOS,
S_AXI_HP0_ARID,
S_AXI_HP0_AWID,
S_AXI_HP0_WID,
S_AXI_HP0_WDATA,
S_AXI_HP0_WSTRB,
S_AXI_HP1_ARESETN,
S_AXI_HP1_ARREADY,
S_AXI_HP1_AWREADY,
S_AXI_HP1_BVALID,
S_AXI_HP1_RLAST,
S_AXI_HP1_RVALID,
S_AXI_HP1_WREADY,
S_AXI_HP1_BRESP,
S_AXI_HP1_RRESP,
S_AXI_HP1_BID,
S_AXI_HP1_RID,
S_AXI_HP1_RDATA,
S_AXI_HP1_RCOUNT,
S_AXI_HP1_WCOUNT,
S_AXI_HP1_RACOUNT,
S_AXI_HP1_WACOUNT,
S_AXI_HP1_ACLK,
S_AXI_HP1_ARVALID,
S_AXI_HP1_AWVALID,
S_AXI_HP1_BREADY,
S_AXI_HP1_RDISSUECAP1_EN,
S_AXI_HP1_RREADY,
S_AXI_HP1_WLAST,
S_AXI_HP1_WRISSUECAP1_EN,
S_AXI_HP1_WVALID,
S_AXI_HP1_ARBURST,
S_AXI_HP1_ARLOCK,
S_AXI_HP1_ARSIZE,
S_AXI_HP1_AWBURST,
S_AXI_HP1_AWLOCK,
S_AXI_HP1_AWSIZE,
S_AXI_HP1_ARPROT,
S_AXI_HP1_AWPROT,
S_AXI_HP1_ARADDR,
S_AXI_HP1_AWADDR,
S_AXI_HP1_ARCACHE,
S_AXI_HP1_ARLEN,
S_AXI_HP1_ARQOS,
S_AXI_HP1_AWCACHE,
S_AXI_HP1_AWLEN,
S_AXI_HP1_AWQOS,
S_AXI_HP1_ARID,
S_AXI_HP1_AWID,
S_AXI_HP1_WID,
S_AXI_HP1_WDATA,
S_AXI_HP1_WSTRB,
S_AXI_HP2_ARESETN,
S_AXI_HP2_ARREADY,
S_AXI_HP2_AWREADY,
S_AXI_HP2_BVALID,
S_AXI_HP2_RLAST,
S_AXI_HP2_RVALID,
S_AXI_HP2_WREADY,
S_AXI_HP2_BRESP,
S_AXI_HP2_RRESP,
S_AXI_HP2_BID,
S_AXI_HP2_RID,
S_AXI_HP2_RDATA,
S_AXI_HP2_RCOUNT,
S_AXI_HP2_WCOUNT,
S_AXI_HP2_RACOUNT,
S_AXI_HP2_WACOUNT,
S_AXI_HP2_ACLK,
S_AXI_HP2_ARVALID,
S_AXI_HP2_AWVALID,
S_AXI_HP2_BREADY,
S_AXI_HP2_RDISSUECAP1_EN,
S_AXI_HP2_RREADY,
S_AXI_HP2_WLAST,
S_AXI_HP2_WRISSUECAP1_EN,
S_AXI_HP2_WVALID,
S_AXI_HP2_ARBURST,
S_AXI_HP2_ARLOCK,
S_AXI_HP2_ARSIZE,
S_AXI_HP2_AWBURST,
S_AXI_HP2_AWLOCK,
S_AXI_HP2_AWSIZE,
S_AXI_HP2_ARPROT,
S_AXI_HP2_AWPROT,
S_AXI_HP2_ARADDR,
S_AXI_HP2_AWADDR,
S_AXI_HP2_ARCACHE,
S_AXI_HP2_ARLEN,
S_AXI_HP2_ARQOS,
S_AXI_HP2_AWCACHE,
S_AXI_HP2_AWLEN,
S_AXI_HP2_AWQOS,
S_AXI_HP2_ARID,
S_AXI_HP2_AWID,
S_AXI_HP2_WID,
S_AXI_HP2_WDATA,
S_AXI_HP2_WSTRB,
S_AXI_HP3_ARESETN,
S_AXI_HP3_ARREADY,
S_AXI_HP3_AWREADY,
S_AXI_HP3_BVALID,
S_AXI_HP3_RLAST,
S_AXI_HP3_RVALID,
S_AXI_HP3_WREADY,
S_AXI_HP3_BRESP,
S_AXI_HP3_RRESP,
S_AXI_HP3_BID,
S_AXI_HP3_RID,
S_AXI_HP3_RDATA,
S_AXI_HP3_RCOUNT,
S_AXI_HP3_WCOUNT,
S_AXI_HP3_RACOUNT,
S_AXI_HP3_WACOUNT,
S_AXI_HP3_ACLK,
S_AXI_HP3_ARVALID,
S_AXI_HP3_AWVALID,
S_AXI_HP3_BREADY,
S_AXI_HP3_RDISSUECAP1_EN,
S_AXI_HP3_RREADY,
S_AXI_HP3_WLAST,
S_AXI_HP3_WRISSUECAP1_EN,
S_AXI_HP3_WVALID,
S_AXI_HP3_ARBURST,
S_AXI_HP3_ARLOCK,
S_AXI_HP3_ARSIZE,
S_AXI_HP3_AWBURST,
S_AXI_HP3_AWLOCK,
S_AXI_HP3_AWSIZE,
S_AXI_HP3_ARPROT,
S_AXI_HP3_AWPROT,
S_AXI_HP3_ARADDR,
S_AXI_HP3_AWADDR,
S_AXI_HP3_ARCACHE,
S_AXI_HP3_ARLEN,
S_AXI_HP3_ARQOS,
S_AXI_HP3_AWCACHE,
S_AXI_HP3_AWLEN,
S_AXI_HP3_AWQOS,
S_AXI_HP3_ARID,
S_AXI_HP3_AWID,
S_AXI_HP3_WID,
S_AXI_HP3_WDATA,
S_AXI_HP3_WSTRB,
IRQ_P2F_DMAC_ABORT,
IRQ_P2F_DMAC0,
IRQ_P2F_DMAC1,
IRQ_P2F_DMAC2,
IRQ_P2F_DMAC3,
IRQ_P2F_DMAC4,
IRQ_P2F_DMAC5,
IRQ_P2F_DMAC6,
IRQ_P2F_DMAC7,
IRQ_P2F_SMC,
IRQ_P2F_QSPI,
IRQ_P2F_CTI,
IRQ_P2F_GPIO,
IRQ_P2F_USB0,
IRQ_P2F_ENET0,
IRQ_P2F_ENET_WAKE0,
IRQ_P2F_SDIO0,
IRQ_P2F_I2C0,
IRQ_P2F_SPI0,
IRQ_P2F_UART0,
IRQ_P2F_CAN0,
IRQ_P2F_USB1,
IRQ_P2F_ENET1,
IRQ_P2F_ENET_WAKE1,
IRQ_P2F_SDIO1,
IRQ_P2F_I2C1,
IRQ_P2F_SPI1,
IRQ_P2F_UART1,
IRQ_P2F_CAN1,
IRQ_F2P,
Core0_nFIQ,
Core0_nIRQ,
Core1_nFIQ,
Core1_nIRQ,
DMA0_DATYPE,
DMA0_DAVALID,
DMA0_DRREADY,
DMA0_RSTN,
DMA1_DATYPE,
DMA1_DAVALID,
DMA1_DRREADY,
DMA1_RSTN,
DMA2_DATYPE,
DMA2_DAVALID,
DMA2_DRREADY,
DMA2_RSTN,
DMA3_DATYPE,
DMA3_DAVALID,
DMA3_DRREADY,
DMA3_RSTN,
DMA0_ACLK,
DMA0_DAREADY,
DMA0_DRLAST,
DMA0_DRVALID,
DMA1_ACLK,
DMA1_DAREADY,
DMA1_DRLAST,
DMA1_DRVALID,
DMA2_ACLK,
DMA2_DAREADY,
DMA2_DRLAST,
DMA2_DRVALID,
DMA3_ACLK,
DMA3_DAREADY,
DMA3_DRLAST,
DMA3_DRVALID,
DMA0_DRTYPE,
DMA1_DRTYPE,
DMA2_DRTYPE,
DMA3_DRTYPE,
FCLK_CLK3,
FCLK_CLK2,
FCLK_CLK1,
FCLK_CLK0,
FCLK_CLKTRIG3_N,
FCLK_CLKTRIG2_N,
FCLK_CLKTRIG1_N,
FCLK_CLKTRIG0_N,
FCLK_RESET3_N,
FCLK_RESET2_N,
FCLK_RESET1_N,
FCLK_RESET0_N,
FTMD_TRACEIN_DATA,
FTMD_TRACEIN_VALID,
FTMD_TRACEIN_CLK,
FTMD_TRACEIN_ATID,
FTMT_F2P_TRIG_0,
FTMT_F2P_TRIGACK_0,
FTMT_F2P_TRIG_1,
FTMT_F2P_TRIGACK_1,
FTMT_F2P_TRIG_2,
FTMT_F2P_TRIGACK_2,
FTMT_F2P_TRIG_3,
FTMT_F2P_TRIGACK_3,
FTMT_F2P_DEBUG,
FTMT_P2F_TRIGACK_0,
FTMT_P2F_TRIG_0,
FTMT_P2F_TRIGACK_1,
FTMT_P2F_TRIG_1,
FTMT_P2F_TRIGACK_2,
FTMT_P2F_TRIG_2,
FTMT_P2F_TRIGACK_3,
FTMT_P2F_TRIG_3,
FTMT_P2F_DEBUG,
FPGA_IDLE_N,
EVENT_EVENTO,
EVENT_STANDBYWFE,
EVENT_STANDBYWFI,
EVENT_EVENTI,
DDR_ARB,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB);
output CAN0_PHY_TX;
input CAN0_PHY_RX;
output CAN1_PHY_TX;
input CAN1_PHY_RX;
output ENET0_GMII_TX_EN;
output ENET0_GMII_TX_ER;
output ENET0_MDIO_MDC;
output ENET0_MDIO_O;
output ENET0_MDIO_T;
output ENET0_PTP_DELAY_REQ_RX;
output ENET0_PTP_DELAY_REQ_TX;
output ENET0_PTP_PDELAY_REQ_RX;
output ENET0_PTP_PDELAY_REQ_TX;
output ENET0_PTP_PDELAY_RESP_RX;
output ENET0_PTP_PDELAY_RESP_TX;
output ENET0_PTP_SYNC_FRAME_RX;
output ENET0_PTP_SYNC_FRAME_TX;
output ENET0_SOF_RX;
output ENET0_SOF_TX;
output [7:0]ENET0_GMII_TXD;
input ENET0_GMII_COL;
input ENET0_GMII_CRS;
input ENET0_GMII_RX_CLK;
input ENET0_GMII_RX_DV;
input ENET0_GMII_RX_ER;
input ENET0_GMII_TX_CLK;
input ENET0_MDIO_I;
input ENET0_EXT_INTIN;
input [7:0]ENET0_GMII_RXD;
output ENET1_GMII_TX_EN;
output ENET1_GMII_TX_ER;
output ENET1_MDIO_MDC;
output ENET1_MDIO_O;
output ENET1_MDIO_T;
output ENET1_PTP_DELAY_REQ_RX;
output ENET1_PTP_DELAY_REQ_TX;
output ENET1_PTP_PDELAY_REQ_RX;
output ENET1_PTP_PDELAY_REQ_TX;
output ENET1_PTP_PDELAY_RESP_RX;
output ENET1_PTP_PDELAY_RESP_TX;
output ENET1_PTP_SYNC_FRAME_RX;
output ENET1_PTP_SYNC_FRAME_TX;
output ENET1_SOF_RX;
output ENET1_SOF_TX;
output [7:0]ENET1_GMII_TXD;
input ENET1_GMII_COL;
input ENET1_GMII_CRS;
input ENET1_GMII_RX_CLK;
input ENET1_GMII_RX_DV;
input ENET1_GMII_RX_ER;
input ENET1_GMII_TX_CLK;
input ENET1_MDIO_I;
input ENET1_EXT_INTIN;
input [7:0]ENET1_GMII_RXD;
input [63:0]GPIO_I;
output [63:0]GPIO_O;
output [63:0]GPIO_T;
input I2C0_SDA_I;
output I2C0_SDA_O;
output I2C0_SDA_T;
input I2C0_SCL_I;
output I2C0_SCL_O;
output I2C0_SCL_T;
input I2C1_SDA_I;
output I2C1_SDA_O;
output I2C1_SDA_T;
input I2C1_SCL_I;
output I2C1_SCL_O;
output I2C1_SCL_T;
input PJTAG_TCK;
input PJTAG_TMS;
input PJTAG_TDI;
output PJTAG_TDO;
output SDIO0_CLK;
input SDIO0_CLK_FB;
output SDIO0_CMD_O;
input SDIO0_CMD_I;
output SDIO0_CMD_T;
input [3:0]SDIO0_DATA_I;
output [3:0]SDIO0_DATA_O;
output [3:0]SDIO0_DATA_T;
output SDIO0_LED;
input SDIO0_CDN;
input SDIO0_WP;
output SDIO0_BUSPOW;
output [2:0]SDIO0_BUSVOLT;
output SDIO1_CLK;
input SDIO1_CLK_FB;
output SDIO1_CMD_O;
input SDIO1_CMD_I;
output SDIO1_CMD_T;
input [3:0]SDIO1_DATA_I;
output [3:0]SDIO1_DATA_O;
output [3:0]SDIO1_DATA_T;
output SDIO1_LED;
input SDIO1_CDN;
input SDIO1_WP;
output SDIO1_BUSPOW;
output [2:0]SDIO1_BUSVOLT;
input SPI0_SCLK_I;
output SPI0_SCLK_O;
output SPI0_SCLK_T;
input SPI0_MOSI_I;
output SPI0_MOSI_O;
output SPI0_MOSI_T;
input SPI0_MISO_I;
output SPI0_MISO_O;
output SPI0_MISO_T;
input SPI0_SS_I;
output SPI0_SS_O;
output SPI0_SS1_O;
output SPI0_SS2_O;
output SPI0_SS_T;
input SPI1_SCLK_I;
output SPI1_SCLK_O;
output SPI1_SCLK_T;
input SPI1_MOSI_I;
output SPI1_MOSI_O;
output SPI1_MOSI_T;
input SPI1_MISO_I;
output SPI1_MISO_O;
output SPI1_MISO_T;
input SPI1_SS_I;
output SPI1_SS_O;
output SPI1_SS1_O;
output SPI1_SS2_O;
output SPI1_SS_T;
output UART0_DTRN;
output UART0_RTSN;
output UART0_TX;
input UART0_CTSN;
input UART0_DCDN;
input UART0_DSRN;
input UART0_RIN;
input UART0_RX;
output UART1_DTRN;
output UART1_RTSN;
output UART1_TX;
input UART1_CTSN;
input UART1_DCDN;
input UART1_DSRN;
input UART1_RIN;
input UART1_RX;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
input TTC0_CLK0_IN;
input TTC0_CLK1_IN;
input TTC0_CLK2_IN;
output TTC1_WAVE0_OUT;
output TTC1_WAVE1_OUT;
output TTC1_WAVE2_OUT;
input TTC1_CLK0_IN;
input TTC1_CLK1_IN;
input TTC1_CLK2_IN;
input WDT_CLK_IN;
output WDT_RST_OUT;
input TRACE_CLK;
output TRACE_CTL;
output [1:0]TRACE_DATA;
output TRACE_CLK_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output [1:0]USB1_PORT_INDCTL;
output USB1_VBUS_PWRSELECT;
input USB1_VBUS_PWRFAULT;
input SRAM_INTIN;
output M_AXI_GP0_ARESETN;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
output M_AXI_GP1_ARESETN;
output M_AXI_GP1_ARVALID;
output M_AXI_GP1_AWVALID;
output M_AXI_GP1_BREADY;
output M_AXI_GP1_RREADY;
output M_AXI_GP1_WLAST;
output M_AXI_GP1_WVALID;
output [11:0]M_AXI_GP1_ARID;
output [11:0]M_AXI_GP1_AWID;
output [11:0]M_AXI_GP1_WID;
output [1:0]M_AXI_GP1_ARBURST;
output [1:0]M_AXI_GP1_ARLOCK;
output [2:0]M_AXI_GP1_ARSIZE;
output [1:0]M_AXI_GP1_AWBURST;
output [1:0]M_AXI_GP1_AWLOCK;
output [2:0]M_AXI_GP1_AWSIZE;
output [2:0]M_AXI_GP1_ARPROT;
output [2:0]M_AXI_GP1_AWPROT;
output [31:0]M_AXI_GP1_ARADDR;
output [31:0]M_AXI_GP1_AWADDR;
output [31:0]M_AXI_GP1_WDATA;
output [3:0]M_AXI_GP1_ARCACHE;
output [3:0]M_AXI_GP1_ARLEN;
output [3:0]M_AXI_GP1_ARQOS;
output [3:0]M_AXI_GP1_AWCACHE;
output [3:0]M_AXI_GP1_AWLEN;
output [3:0]M_AXI_GP1_AWQOS;
output [3:0]M_AXI_GP1_WSTRB;
input M_AXI_GP1_ACLK;
input M_AXI_GP1_ARREADY;
input M_AXI_GP1_AWREADY;
input M_AXI_GP1_BVALID;
input M_AXI_GP1_RLAST;
input M_AXI_GP1_RVALID;
input M_AXI_GP1_WREADY;
input [11:0]M_AXI_GP1_BID;
input [11:0]M_AXI_GP1_RID;
input [1:0]M_AXI_GP1_BRESP;
input [1:0]M_AXI_GP1_RRESP;
input [31:0]M_AXI_GP1_RDATA;
output S_AXI_GP0_ARESETN;
output S_AXI_GP0_ARREADY;
output S_AXI_GP0_AWREADY;
output S_AXI_GP0_BVALID;
output S_AXI_GP0_RLAST;
output S_AXI_GP0_RVALID;
output S_AXI_GP0_WREADY;
output [1:0]S_AXI_GP0_BRESP;
output [1:0]S_AXI_GP0_RRESP;
output [31:0]S_AXI_GP0_RDATA;
output [5:0]S_AXI_GP0_BID;
output [5:0]S_AXI_GP0_RID;
input S_AXI_GP0_ACLK;
input S_AXI_GP0_ARVALID;
input S_AXI_GP0_AWVALID;
input S_AXI_GP0_BREADY;
input S_AXI_GP0_RREADY;
input S_AXI_GP0_WLAST;
input S_AXI_GP0_WVALID;
input [1:0]S_AXI_GP0_ARBURST;
input [1:0]S_AXI_GP0_ARLOCK;
input [2:0]S_AXI_GP0_ARSIZE;
input [1:0]S_AXI_GP0_AWBURST;
input [1:0]S_AXI_GP0_AWLOCK;
input [2:0]S_AXI_GP0_AWSIZE;
input [2:0]S_AXI_GP0_ARPROT;
input [2:0]S_AXI_GP0_AWPROT;
input [31:0]S_AXI_GP0_ARADDR;
input [31:0]S_AXI_GP0_AWADDR;
input [31:0]S_AXI_GP0_WDATA;
input [3:0]S_AXI_GP0_ARCACHE;
input [3:0]S_AXI_GP0_ARLEN;
input [3:0]S_AXI_GP0_ARQOS;
input [3:0]S_AXI_GP0_AWCACHE;
input [3:0]S_AXI_GP0_AWLEN;
input [3:0]S_AXI_GP0_AWQOS;
input [3:0]S_AXI_GP0_WSTRB;
input [5:0]S_AXI_GP0_ARID;
input [5:0]S_AXI_GP0_AWID;
input [5:0]S_AXI_GP0_WID;
output S_AXI_GP1_ARESETN;
output S_AXI_GP1_ARREADY;
output S_AXI_GP1_AWREADY;
output S_AXI_GP1_BVALID;
output S_AXI_GP1_RLAST;
output S_AXI_GP1_RVALID;
output S_AXI_GP1_WREADY;
output [1:0]S_AXI_GP1_BRESP;
output [1:0]S_AXI_GP1_RRESP;
output [31:0]S_AXI_GP1_RDATA;
output [5:0]S_AXI_GP1_BID;
output [5:0]S_AXI_GP1_RID;
input S_AXI_GP1_ACLK;
input S_AXI_GP1_ARVALID;
input S_AXI_GP1_AWVALID;
input S_AXI_GP1_BREADY;
input S_AXI_GP1_RREADY;
input S_AXI_GP1_WLAST;
input S_AXI_GP1_WVALID;
input [1:0]S_AXI_GP1_ARBURST;
input [1:0]S_AXI_GP1_ARLOCK;
input [2:0]S_AXI_GP1_ARSIZE;
input [1:0]S_AXI_GP1_AWBURST;
input [1:0]S_AXI_GP1_AWLOCK;
input [2:0]S_AXI_GP1_AWSIZE;
input [2:0]S_AXI_GP1_ARPROT;
input [2:0]S_AXI_GP1_AWPROT;
input [31:0]S_AXI_GP1_ARADDR;
input [31:0]S_AXI_GP1_AWADDR;
input [31:0]S_AXI_GP1_WDATA;
input [3:0]S_AXI_GP1_ARCACHE;
input [3:0]S_AXI_GP1_ARLEN;
input [3:0]S_AXI_GP1_ARQOS;
input [3:0]S_AXI_GP1_AWCACHE;
input [3:0]S_AXI_GP1_AWLEN;
input [3:0]S_AXI_GP1_AWQOS;
input [3:0]S_AXI_GP1_WSTRB;
input [5:0]S_AXI_GP1_ARID;
input [5:0]S_AXI_GP1_AWID;
input [5:0]S_AXI_GP1_WID;
output S_AXI_ACP_ARESETN;
output S_AXI_ACP_ARREADY;
output S_AXI_ACP_AWREADY;
output S_AXI_ACP_BVALID;
output S_AXI_ACP_RLAST;
output S_AXI_ACP_RVALID;
output S_AXI_ACP_WREADY;
output [1:0]S_AXI_ACP_BRESP;
output [1:0]S_AXI_ACP_RRESP;
output [2:0]S_AXI_ACP_BID;
output [2:0]S_AXI_ACP_RID;
output [63:0]S_AXI_ACP_RDATA;
input S_AXI_ACP_ACLK;
input S_AXI_ACP_ARVALID;
input S_AXI_ACP_AWVALID;
input S_AXI_ACP_BREADY;
input S_AXI_ACP_RREADY;
input S_AXI_ACP_WLAST;
input S_AXI_ACP_WVALID;
input [2:0]S_AXI_ACP_ARID;
input [2:0]S_AXI_ACP_ARPROT;
input [2:0]S_AXI_ACP_AWID;
input [2:0]S_AXI_ACP_AWPROT;
input [2:0]S_AXI_ACP_WID;
input [31:0]S_AXI_ACP_ARADDR;
input [31:0]S_AXI_ACP_AWADDR;
input [3:0]S_AXI_ACP_ARCACHE;
input [3:0]S_AXI_ACP_ARLEN;
input [3:0]S_AXI_ACP_ARQOS;
input [3:0]S_AXI_ACP_AWCACHE;
input [3:0]S_AXI_ACP_AWLEN;
input [3:0]S_AXI_ACP_AWQOS;
input [1:0]S_AXI_ACP_ARBURST;
input [1:0]S_AXI_ACP_ARLOCK;
input [2:0]S_AXI_ACP_ARSIZE;
input [1:0]S_AXI_ACP_AWBURST;
input [1:0]S_AXI_ACP_AWLOCK;
input [2:0]S_AXI_ACP_AWSIZE;
input [4:0]S_AXI_ACP_ARUSER;
input [4:0]S_AXI_ACP_AWUSER;
input [63:0]S_AXI_ACP_WDATA;
input [7:0]S_AXI_ACP_WSTRB;
output S_AXI_HP0_ARESETN;
output S_AXI_HP0_ARREADY;
output S_AXI_HP0_AWREADY;
output S_AXI_HP0_BVALID;
output S_AXI_HP0_RLAST;
output S_AXI_HP0_RVALID;
output S_AXI_HP0_WREADY;
output [1:0]S_AXI_HP0_BRESP;
output [1:0]S_AXI_HP0_RRESP;
output [5:0]S_AXI_HP0_BID;
output [5:0]S_AXI_HP0_RID;
output [63:0]S_AXI_HP0_RDATA;
output [7:0]S_AXI_HP0_RCOUNT;
output [7:0]S_AXI_HP0_WCOUNT;
output [2:0]S_AXI_HP0_RACOUNT;
output [5:0]S_AXI_HP0_WACOUNT;
input S_AXI_HP0_ACLK;
input S_AXI_HP0_ARVALID;
input S_AXI_HP0_AWVALID;
input S_AXI_HP0_BREADY;
input S_AXI_HP0_RDISSUECAP1_EN;
input S_AXI_HP0_RREADY;
input S_AXI_HP0_WLAST;
input S_AXI_HP0_WRISSUECAP1_EN;
input S_AXI_HP0_WVALID;
input [1:0]S_AXI_HP0_ARBURST;
input [1:0]S_AXI_HP0_ARLOCK;
input [2:0]S_AXI_HP0_ARSIZE;
input [1:0]S_AXI_HP0_AWBURST;
input [1:0]S_AXI_HP0_AWLOCK;
input [2:0]S_AXI_HP0_AWSIZE;
input [2:0]S_AXI_HP0_ARPROT;
input [2:0]S_AXI_HP0_AWPROT;
input [31:0]S_AXI_HP0_ARADDR;
input [31:0]S_AXI_HP0_AWADDR;
input [3:0]S_AXI_HP0_ARCACHE;
input [3:0]S_AXI_HP0_ARLEN;
input [3:0]S_AXI_HP0_ARQOS;
input [3:0]S_AXI_HP0_AWCACHE;
input [3:0]S_AXI_HP0_AWLEN;
input [3:0]S_AXI_HP0_AWQOS;
input [5:0]S_AXI_HP0_ARID;
input [5:0]S_AXI_HP0_AWID;
input [5:0]S_AXI_HP0_WID;
input [63:0]S_AXI_HP0_WDATA;
input [7:0]S_AXI_HP0_WSTRB;
output S_AXI_HP1_ARESETN;
output S_AXI_HP1_ARREADY;
output S_AXI_HP1_AWREADY;
output S_AXI_HP1_BVALID;
output S_AXI_HP1_RLAST;
output S_AXI_HP1_RVALID;
output S_AXI_HP1_WREADY;
output [1:0]S_AXI_HP1_BRESP;
output [1:0]S_AXI_HP1_RRESP;
output [5:0]S_AXI_HP1_BID;
output [5:0]S_AXI_HP1_RID;
output [63:0]S_AXI_HP1_RDATA;
output [7:0]S_AXI_HP1_RCOUNT;
output [7:0]S_AXI_HP1_WCOUNT;
output [2:0]S_AXI_HP1_RACOUNT;
output [5:0]S_AXI_HP1_WACOUNT;
input S_AXI_HP1_ACLK;
input S_AXI_HP1_ARVALID;
input S_AXI_HP1_AWVALID;
input S_AXI_HP1_BREADY;
input S_AXI_HP1_RDISSUECAP1_EN;
input S_AXI_HP1_RREADY;
input S_AXI_HP1_WLAST;
input S_AXI_HP1_WRISSUECAP1_EN;
input S_AXI_HP1_WVALID;
input [1:0]S_AXI_HP1_ARBURST;
input [1:0]S_AXI_HP1_ARLOCK;
input [2:0]S_AXI_HP1_ARSIZE;
input [1:0]S_AXI_HP1_AWBURST;
input [1:0]S_AXI_HP1_AWLOCK;
input [2:0]S_AXI_HP1_AWSIZE;
input [2:0]S_AXI_HP1_ARPROT;
input [2:0]S_AXI_HP1_AWPROT;
input [31:0]S_AXI_HP1_ARADDR;
input [31:0]S_AXI_HP1_AWADDR;
input [3:0]S_AXI_HP1_ARCACHE;
input [3:0]S_AXI_HP1_ARLEN;
input [3:0]S_AXI_HP1_ARQOS;
input [3:0]S_AXI_HP1_AWCACHE;
input [3:0]S_AXI_HP1_AWLEN;
input [3:0]S_AXI_HP1_AWQOS;
input [5:0]S_AXI_HP1_ARID;
input [5:0]S_AXI_HP1_AWID;
input [5:0]S_AXI_HP1_WID;
input [63:0]S_AXI_HP1_WDATA;
input [7:0]S_AXI_HP1_WSTRB;
output S_AXI_HP2_ARESETN;
output S_AXI_HP2_ARREADY;
output S_AXI_HP2_AWREADY;
output S_AXI_HP2_BVALID;
output S_AXI_HP2_RLAST;
output S_AXI_HP2_RVALID;
output S_AXI_HP2_WREADY;
output [1:0]S_AXI_HP2_BRESP;
output [1:0]S_AXI_HP2_RRESP;
output [5:0]S_AXI_HP2_BID;
output [5:0]S_AXI_HP2_RID;
output [63:0]S_AXI_HP2_RDATA;
output [7:0]S_AXI_HP2_RCOUNT;
output [7:0]S_AXI_HP2_WCOUNT;
output [2:0]S_AXI_HP2_RACOUNT;
output [5:0]S_AXI_HP2_WACOUNT;
input S_AXI_HP2_ACLK;
input S_AXI_HP2_ARVALID;
input S_AXI_HP2_AWVALID;
input S_AXI_HP2_BREADY;
input S_AXI_HP2_RDISSUECAP1_EN;
input S_AXI_HP2_RREADY;
input S_AXI_HP2_WLAST;
input S_AXI_HP2_WRISSUECAP1_EN;
input S_AXI_HP2_WVALID;
input [1:0]S_AXI_HP2_ARBURST;
input [1:0]S_AXI_HP2_ARLOCK;
input [2:0]S_AXI_HP2_ARSIZE;
input [1:0]S_AXI_HP2_AWBURST;
input [1:0]S_AXI_HP2_AWLOCK;
input [2:0]S_AXI_HP2_AWSIZE;
input [2:0]S_AXI_HP2_ARPROT;
input [2:0]S_AXI_HP2_AWPROT;
input [31:0]S_AXI_HP2_ARADDR;
input [31:0]S_AXI_HP2_AWADDR;
input [3:0]S_AXI_HP2_ARCACHE;
input [3:0]S_AXI_HP2_ARLEN;
input [3:0]S_AXI_HP2_ARQOS;
input [3:0]S_AXI_HP2_AWCACHE;
input [3:0]S_AXI_HP2_AWLEN;
input [3:0]S_AXI_HP2_AWQOS;
input [5:0]S_AXI_HP2_ARID;
input [5:0]S_AXI_HP2_AWID;
input [5:0]S_AXI_HP2_WID;
input [63:0]S_AXI_HP2_WDATA;
input [7:0]S_AXI_HP2_WSTRB;
output S_AXI_HP3_ARESETN;
output S_AXI_HP3_ARREADY;
output S_AXI_HP3_AWREADY;
output S_AXI_HP3_BVALID;
output S_AXI_HP3_RLAST;
output S_AXI_HP3_RVALID;
output S_AXI_HP3_WREADY;
output [1:0]S_AXI_HP3_BRESP;
output [1:0]S_AXI_HP3_RRESP;
output [5:0]S_AXI_HP3_BID;
output [5:0]S_AXI_HP3_RID;
output [63:0]S_AXI_HP3_RDATA;
output [7:0]S_AXI_HP3_RCOUNT;
output [7:0]S_AXI_HP3_WCOUNT;
output [2:0]S_AXI_HP3_RACOUNT;
output [5:0]S_AXI_HP3_WACOUNT;
input S_AXI_HP3_ACLK;
input S_AXI_HP3_ARVALID;
input S_AXI_HP3_AWVALID;
input S_AXI_HP3_BREADY;
input S_AXI_HP3_RDISSUECAP1_EN;
input S_AXI_HP3_RREADY;
input S_AXI_HP3_WLAST;
input S_AXI_HP3_WRISSUECAP1_EN;
input S_AXI_HP3_WVALID;
input [1:0]S_AXI_HP3_ARBURST;
input [1:0]S_AXI_HP3_ARLOCK;
input [2:0]S_AXI_HP3_ARSIZE;
input [1:0]S_AXI_HP3_AWBURST;
input [1:0]S_AXI_HP3_AWLOCK;
input [2:0]S_AXI_HP3_AWSIZE;
input [2:0]S_AXI_HP3_ARPROT;
input [2:0]S_AXI_HP3_AWPROT;
input [31:0]S_AXI_HP3_ARADDR;
input [31:0]S_AXI_HP3_AWADDR;
input [3:0]S_AXI_HP3_ARCACHE;
input [3:0]S_AXI_HP3_ARLEN;
input [3:0]S_AXI_HP3_ARQOS;
input [3:0]S_AXI_HP3_AWCACHE;
input [3:0]S_AXI_HP3_AWLEN;
input [3:0]S_AXI_HP3_AWQOS;
input [5:0]S_AXI_HP3_ARID;
input [5:0]S_AXI_HP3_AWID;
input [5:0]S_AXI_HP3_WID;
input [63:0]S_AXI_HP3_WDATA;
input [7:0]S_AXI_HP3_WSTRB;
output IRQ_P2F_DMAC_ABORT;
output IRQ_P2F_DMAC0;
output IRQ_P2F_DMAC1;
output IRQ_P2F_DMAC2;
output IRQ_P2F_DMAC3;
output IRQ_P2F_DMAC4;
output IRQ_P2F_DMAC5;
output IRQ_P2F_DMAC6;
output IRQ_P2F_DMAC7;
output IRQ_P2F_SMC;
output IRQ_P2F_QSPI;
output IRQ_P2F_CTI;
output IRQ_P2F_GPIO;
output IRQ_P2F_USB0;
output IRQ_P2F_ENET0;
output IRQ_P2F_ENET_WAKE0;
output IRQ_P2F_SDIO0;
output IRQ_P2F_I2C0;
output IRQ_P2F_SPI0;
output IRQ_P2F_UART0;
output IRQ_P2F_CAN0;
output IRQ_P2F_USB1;
output IRQ_P2F_ENET1;
output IRQ_P2F_ENET_WAKE1;
output IRQ_P2F_SDIO1;
output IRQ_P2F_I2C1;
output IRQ_P2F_SPI1;
output IRQ_P2F_UART1;
output IRQ_P2F_CAN1;
input [0:0]IRQ_F2P;
input Core0_nFIQ;
input Core0_nIRQ;
input Core1_nFIQ;
input Core1_nIRQ;
output [1:0]DMA0_DATYPE;
output DMA0_DAVALID;
output DMA0_DRREADY;
output DMA0_RSTN;
output [1:0]DMA1_DATYPE;
output DMA1_DAVALID;
output DMA1_DRREADY;
output DMA1_RSTN;
output [1:0]DMA2_DATYPE;
output DMA2_DAVALID;
output DMA2_DRREADY;
output DMA2_RSTN;
output [1:0]DMA3_DATYPE;
output DMA3_DAVALID;
output DMA3_DRREADY;
output DMA3_RSTN;
input DMA0_ACLK;
input DMA0_DAREADY;
input DMA0_DRLAST;
input DMA0_DRVALID;
input DMA1_ACLK;
input DMA1_DAREADY;
input DMA1_DRLAST;
input DMA1_DRVALID;
input DMA2_ACLK;
input DMA2_DAREADY;
input DMA2_DRLAST;
input DMA2_DRVALID;
input DMA3_ACLK;
input DMA3_DAREADY;
input DMA3_DRLAST;
input DMA3_DRVALID;
input [1:0]DMA0_DRTYPE;
input [1:0]DMA1_DRTYPE;
input [1:0]DMA2_DRTYPE;
input [1:0]DMA3_DRTYPE;
output FCLK_CLK3;
output FCLK_CLK2;
output FCLK_CLK1;
output FCLK_CLK0;
input FCLK_CLKTRIG3_N;
input FCLK_CLKTRIG2_N;
input FCLK_CLKTRIG1_N;
input FCLK_CLKTRIG0_N;
output FCLK_RESET3_N;
output FCLK_RESET2_N;
output FCLK_RESET1_N;
output FCLK_RESET0_N;
input [31:0]FTMD_TRACEIN_DATA;
input FTMD_TRACEIN_VALID;
input FTMD_TRACEIN_CLK;
input [3:0]FTMD_TRACEIN_ATID;
input FTMT_F2P_TRIG_0;
output FTMT_F2P_TRIGACK_0;
input FTMT_F2P_TRIG_1;
output FTMT_F2P_TRIGACK_1;
input FTMT_F2P_TRIG_2;
output FTMT_F2P_TRIGACK_2;
input FTMT_F2P_TRIG_3;
output FTMT_F2P_TRIGACK_3;
input [31:0]FTMT_F2P_DEBUG;
input FTMT_P2F_TRIGACK_0;
output FTMT_P2F_TRIG_0;
input FTMT_P2F_TRIGACK_1;
output FTMT_P2F_TRIG_1;
input FTMT_P2F_TRIGACK_2;
output FTMT_P2F_TRIG_2;
input FTMT_P2F_TRIGACK_3;
output FTMT_P2F_TRIG_3;
output [31:0]FTMT_P2F_DEBUG;
input FPGA_IDLE_N;
output EVENT_EVENTO;
output [1:0]EVENT_STANDBYWFE;
output [1:0]EVENT_STANDBYWFI;
input EVENT_EVENTI;
input [3:0]DDR_ARB;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
wire \<const0> ;
wire CAN0_PHY_RX;
wire CAN0_PHY_TX;
wire CAN1_PHY_RX;
wire CAN1_PHY_TX;
wire Core0_nFIQ;
wire Core0_nIRQ;
wire Core1_nFIQ;
wire Core1_nIRQ;
wire [3:0]DDR_ARB;
wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr;
wire DDR_CAS_n;
wire DDR_CKE;
wire DDR_CS_n;
wire DDR_Clk;
wire DDR_Clk_n;
wire [3:0]DDR_DM;
wire [31:0]DDR_DQ;
wire [3:0]DDR_DQS;
wire [3:0]DDR_DQS_n;
wire DDR_DRSTB;
wire DDR_ODT;
wire DDR_RAS_n;
wire DDR_VRN;
wire DDR_VRP;
wire DDR_WEB;
wire DMA0_ACLK;
wire DMA0_DAREADY;
wire [1:0]DMA0_DATYPE;
wire DMA0_DAVALID;
wire DMA0_DRLAST;
wire DMA0_DRREADY;
wire [1:0]DMA0_DRTYPE;
wire DMA0_DRVALID;
wire DMA0_RSTN;
wire DMA1_ACLK;
wire DMA1_DAREADY;
wire [1:0]DMA1_DATYPE;
wire DMA1_DAVALID;
wire DMA1_DRLAST;
wire DMA1_DRREADY;
wire [1:0]DMA1_DRTYPE;
wire DMA1_DRVALID;
wire DMA1_RSTN;
wire DMA2_ACLK;
wire DMA2_DAREADY;
wire [1:0]DMA2_DATYPE;
wire DMA2_DAVALID;
wire DMA2_DRLAST;
wire DMA2_DRREADY;
wire [1:0]DMA2_DRTYPE;
wire DMA2_DRVALID;
wire DMA2_RSTN;
wire DMA3_ACLK;
wire DMA3_DAREADY;
wire [1:0]DMA3_DATYPE;
wire DMA3_DAVALID;
wire DMA3_DRLAST;
wire DMA3_DRREADY;
wire [1:0]DMA3_DRTYPE;
wire DMA3_DRVALID;
wire DMA3_RSTN;
wire ENET0_EXT_INTIN;
wire ENET0_GMII_RX_CLK;
wire ENET0_GMII_TX_CLK;
wire ENET0_MDIO_I;
wire ENET0_MDIO_MDC;
wire ENET0_MDIO_O;
wire ENET0_MDIO_T;
wire ENET0_MDIO_T_n;
wire ENET0_PTP_DELAY_REQ_RX;
wire ENET0_PTP_DELAY_REQ_TX;
wire ENET0_PTP_PDELAY_REQ_RX;
wire ENET0_PTP_PDELAY_REQ_TX;
wire ENET0_PTP_PDELAY_RESP_RX;
wire ENET0_PTP_PDELAY_RESP_TX;
wire ENET0_PTP_SYNC_FRAME_RX;
wire ENET0_PTP_SYNC_FRAME_TX;
wire ENET0_SOF_RX;
wire ENET0_SOF_TX;
wire ENET1_EXT_INTIN;
wire ENET1_GMII_RX_CLK;
wire ENET1_GMII_TX_CLK;
wire ENET1_MDIO_I;
wire ENET1_MDIO_MDC;
wire ENET1_MDIO_O;
wire ENET1_MDIO_T;
wire ENET1_MDIO_T_n;
wire ENET1_PTP_DELAY_REQ_RX;
wire ENET1_PTP_DELAY_REQ_TX;
wire ENET1_PTP_PDELAY_REQ_RX;
wire ENET1_PTP_PDELAY_REQ_TX;
wire ENET1_PTP_PDELAY_RESP_RX;
wire ENET1_PTP_PDELAY_RESP_TX;
wire ENET1_PTP_SYNC_FRAME_RX;
wire ENET1_PTP_SYNC_FRAME_TX;
wire ENET1_SOF_RX;
wire ENET1_SOF_TX;
wire EVENT_EVENTI;
wire EVENT_EVENTO;
wire [1:0]EVENT_STANDBYWFE;
wire [1:0]EVENT_STANDBYWFI;
wire FCLK_CLK0;
wire FCLK_CLK1;
wire FCLK_CLK2;
wire FCLK_CLK3;
wire [0:0]FCLK_CLK_unbuffered;
wire FCLK_RESET0_N;
wire FCLK_RESET1_N;
wire FCLK_RESET2_N;
wire FCLK_RESET3_N;
wire FPGA_IDLE_N;
wire FTMD_TRACEIN_CLK;
wire [31:0]FTMT_F2P_DEBUG;
wire FTMT_F2P_TRIGACK_0;
wire FTMT_F2P_TRIGACK_1;
wire FTMT_F2P_TRIGACK_2;
wire FTMT_F2P_TRIGACK_3;
wire FTMT_F2P_TRIG_0;
wire FTMT_F2P_TRIG_1;
wire FTMT_F2P_TRIG_2;
wire FTMT_F2P_TRIG_3;
wire [31:0]FTMT_P2F_DEBUG;
wire FTMT_P2F_TRIGACK_0;
wire FTMT_P2F_TRIGACK_1;
wire FTMT_P2F_TRIGACK_2;
wire FTMT_P2F_TRIGACK_3;
wire FTMT_P2F_TRIG_0;
wire FTMT_P2F_TRIG_1;
wire FTMT_P2F_TRIG_2;
wire FTMT_P2F_TRIG_3;
wire [63:0]GPIO_I;
wire [63:0]GPIO_O;
wire [63:0]GPIO_T;
wire I2C0_SCL_I;
wire I2C0_SCL_O;
wire I2C0_SCL_T;
wire I2C0_SCL_T_n;
wire I2C0_SDA_I;
wire I2C0_SDA_O;
wire I2C0_SDA_T;
wire I2C0_SDA_T_n;
wire I2C1_SCL_I;
wire I2C1_SCL_O;
wire I2C1_SCL_T;
wire I2C1_SCL_T_n;
wire I2C1_SDA_I;
wire I2C1_SDA_O;
wire I2C1_SDA_T;
wire I2C1_SDA_T_n;
wire [0:0]IRQ_F2P;
wire IRQ_P2F_CAN0;
wire IRQ_P2F_CAN1;
wire IRQ_P2F_CTI;
wire IRQ_P2F_DMAC0;
wire IRQ_P2F_DMAC1;
wire IRQ_P2F_DMAC2;
wire IRQ_P2F_DMAC3;
wire IRQ_P2F_DMAC4;
wire IRQ_P2F_DMAC5;
wire IRQ_P2F_DMAC6;
wire IRQ_P2F_DMAC7;
wire IRQ_P2F_DMAC_ABORT;
wire IRQ_P2F_ENET0;
wire IRQ_P2F_ENET1;
wire IRQ_P2F_ENET_WAKE0;
wire IRQ_P2F_ENET_WAKE1;
wire IRQ_P2F_GPIO;
wire IRQ_P2F_I2C0;
wire IRQ_P2F_I2C1;
wire IRQ_P2F_QSPI;
wire IRQ_P2F_SDIO0;
wire IRQ_P2F_SDIO1;
wire IRQ_P2F_SMC;
wire IRQ_P2F_SPI0;
wire IRQ_P2F_SPI1;
wire IRQ_P2F_UART0;
wire IRQ_P2F_UART1;
wire IRQ_P2F_USB0;
wire IRQ_P2F_USB1;
wire [53:0]MIO;
wire M_AXI_GP0_ACLK;
wire [31:0]M_AXI_GP0_ARADDR;
wire [1:0]M_AXI_GP0_ARBURST;
wire [3:0]M_AXI_GP0_ARCACHE;
wire M_AXI_GP0_ARESETN;
wire [11:0]M_AXI_GP0_ARID;
wire [3:0]M_AXI_GP0_ARLEN;
wire [1:0]M_AXI_GP0_ARLOCK;
wire [2:0]M_AXI_GP0_ARPROT;
wire [3:0]M_AXI_GP0_ARQOS;
wire M_AXI_GP0_ARREADY;
wire [1:0]\^M_AXI_GP0_ARSIZE ;
wire M_AXI_GP0_ARVALID;
wire [31:0]M_AXI_GP0_AWADDR;
wire [1:0]M_AXI_GP0_AWBURST;
wire [3:0]M_AXI_GP0_AWCACHE;
wire [11:0]M_AXI_GP0_AWID;
wire [3:0]M_AXI_GP0_AWLEN;
wire [1:0]M_AXI_GP0_AWLOCK;
wire [2:0]M_AXI_GP0_AWPROT;
wire [3:0]M_AXI_GP0_AWQOS;
wire M_AXI_GP0_AWREADY;
wire [1:0]\^M_AXI_GP0_AWSIZE ;
wire M_AXI_GP0_AWVALID;
wire [11:0]M_AXI_GP0_BID;
wire M_AXI_GP0_BREADY;
wire [1:0]M_AXI_GP0_BRESP;
wire M_AXI_GP0_BVALID;
wire [31:0]M_AXI_GP0_RDATA;
wire [11:0]M_AXI_GP0_RID;
wire M_AXI_GP0_RLAST;
wire M_AXI_GP0_RREADY;
wire [1:0]M_AXI_GP0_RRESP;
wire M_AXI_GP0_RVALID;
wire [31:0]M_AXI_GP0_WDATA;
wire [11:0]M_AXI_GP0_WID;
wire M_AXI_GP0_WLAST;
wire M_AXI_GP0_WREADY;
wire [3:0]M_AXI_GP0_WSTRB;
wire M_AXI_GP0_WVALID;
wire M_AXI_GP1_ACLK;
wire [31:0]M_AXI_GP1_ARADDR;
wire [1:0]M_AXI_GP1_ARBURST;
wire [3:0]M_AXI_GP1_ARCACHE;
wire M_AXI_GP1_ARESETN;
wire [11:0]M_AXI_GP1_ARID;
wire [3:0]M_AXI_GP1_ARLEN;
wire [1:0]M_AXI_GP1_ARLOCK;
wire [2:0]M_AXI_GP1_ARPROT;
wire [3:0]M_AXI_GP1_ARQOS;
wire M_AXI_GP1_ARREADY;
wire [1:0]\^M_AXI_GP1_ARSIZE ;
wire M_AXI_GP1_ARVALID;
wire [31:0]M_AXI_GP1_AWADDR;
wire [1:0]M_AXI_GP1_AWBURST;
wire [3:0]M_AXI_GP1_AWCACHE;
wire [11:0]M_AXI_GP1_AWID;
wire [3:0]M_AXI_GP1_AWLEN;
wire [1:0]M_AXI_GP1_AWLOCK;
wire [2:0]M_AXI_GP1_AWPROT;
wire [3:0]M_AXI_GP1_AWQOS;
wire M_AXI_GP1_AWREADY;
wire [1:0]\^M_AXI_GP1_AWSIZE ;
wire M_AXI_GP1_AWVALID;
wire [11:0]M_AXI_GP1_BID;
wire M_AXI_GP1_BREADY;
wire [1:0]M_AXI_GP1_BRESP;
wire M_AXI_GP1_BVALID;
wire [31:0]M_AXI_GP1_RDATA;
wire [11:0]M_AXI_GP1_RID;
wire M_AXI_GP1_RLAST;
wire M_AXI_GP1_RREADY;
wire [1:0]M_AXI_GP1_RRESP;
wire M_AXI_GP1_RVALID;
wire [31:0]M_AXI_GP1_WDATA;
wire [11:0]M_AXI_GP1_WID;
wire M_AXI_GP1_WLAST;
wire M_AXI_GP1_WREADY;
wire [3:0]M_AXI_GP1_WSTRB;
wire M_AXI_GP1_WVALID;
wire PJTAG_TCK;
wire PJTAG_TDI;
wire PJTAG_TMS;
wire PS_CLK;
wire PS_PORB;
wire PS_SRSTB;
wire SDIO0_BUSPOW;
wire [2:0]SDIO0_BUSVOLT;
wire SDIO0_CDN;
wire SDIO0_CLK;
wire SDIO0_CLK_FB;
wire SDIO0_CMD_I;
wire SDIO0_CMD_O;
wire SDIO0_CMD_T;
wire SDIO0_CMD_T_n;
wire [3:0]SDIO0_DATA_I;
wire [3:0]SDIO0_DATA_O;
wire [3:0]SDIO0_DATA_T;
wire [3:0]SDIO0_DATA_T_n;
wire SDIO0_LED;
wire SDIO0_WP;
wire SDIO1_BUSPOW;
wire [2:0]SDIO1_BUSVOLT;
wire SDIO1_CDN;
wire SDIO1_CLK;
wire SDIO1_CLK_FB;
wire SDIO1_CMD_I;
wire SDIO1_CMD_O;
wire SDIO1_CMD_T;
wire SDIO1_CMD_T_n;
wire [3:0]SDIO1_DATA_I;
wire [3:0]SDIO1_DATA_O;
wire [3:0]SDIO1_DATA_T;
wire [3:0]SDIO1_DATA_T_n;
wire SDIO1_LED;
wire SDIO1_WP;
wire SPI0_MISO_I;
wire SPI0_MISO_O;
wire SPI0_MISO_T;
wire SPI0_MISO_T_n;
wire SPI0_MOSI_I;
wire SPI0_MOSI_O;
wire SPI0_MOSI_T;
wire SPI0_MOSI_T_n;
wire SPI0_SCLK_I;
wire SPI0_SCLK_O;
wire SPI0_SCLK_T;
wire SPI0_SCLK_T_n;
wire SPI0_SS1_O;
wire SPI0_SS2_O;
wire SPI0_SS_I;
wire SPI0_SS_O;
wire SPI0_SS_T;
wire SPI0_SS_T_n;
wire SPI1_MISO_I;
wire SPI1_MISO_O;
wire SPI1_MISO_T;
wire SPI1_MISO_T_n;
wire SPI1_MOSI_I;
wire SPI1_MOSI_O;
wire SPI1_MOSI_T;
wire SPI1_MOSI_T_n;
wire SPI1_SCLK_I;
wire SPI1_SCLK_O;
wire SPI1_SCLK_T;
wire SPI1_SCLK_T_n;
wire SPI1_SS1_O;
wire SPI1_SS2_O;
wire SPI1_SS_I;
wire SPI1_SS_O;
wire SPI1_SS_T;
wire SPI1_SS_T_n;
wire SRAM_INTIN;
wire S_AXI_ACP_ACLK;
wire [31:0]S_AXI_ACP_ARADDR;
wire [1:0]S_AXI_ACP_ARBURST;
wire [3:0]S_AXI_ACP_ARCACHE;
wire S_AXI_ACP_ARESETN;
wire [2:0]S_AXI_ACP_ARID;
wire [3:0]S_AXI_ACP_ARLEN;
wire [1:0]S_AXI_ACP_ARLOCK;
wire [2:0]S_AXI_ACP_ARPROT;
wire [3:0]S_AXI_ACP_ARQOS;
wire S_AXI_ACP_ARREADY;
wire [2:0]S_AXI_ACP_ARSIZE;
wire [4:0]S_AXI_ACP_ARUSER;
wire S_AXI_ACP_ARVALID;
wire [31:0]S_AXI_ACP_AWADDR;
wire [1:0]S_AXI_ACP_AWBURST;
wire [3:0]S_AXI_ACP_AWCACHE;
wire [2:0]S_AXI_ACP_AWID;
wire [3:0]S_AXI_ACP_AWLEN;
wire [1:0]S_AXI_ACP_AWLOCK;
wire [2:0]S_AXI_ACP_AWPROT;
wire [3:0]S_AXI_ACP_AWQOS;
wire S_AXI_ACP_AWREADY;
wire [2:0]S_AXI_ACP_AWSIZE;
wire [4:0]S_AXI_ACP_AWUSER;
wire S_AXI_ACP_AWVALID;
wire [2:0]S_AXI_ACP_BID;
wire S_AXI_ACP_BREADY;
wire [1:0]S_AXI_ACP_BRESP;
wire S_AXI_ACP_BVALID;
wire [63:0]S_AXI_ACP_RDATA;
wire [2:0]S_AXI_ACP_RID;
wire S_AXI_ACP_RLAST;
wire S_AXI_ACP_RREADY;
wire [1:0]S_AXI_ACP_RRESP;
wire S_AXI_ACP_RVALID;
wire [63:0]S_AXI_ACP_WDATA;
wire [2:0]S_AXI_ACP_WID;
wire S_AXI_ACP_WLAST;
wire S_AXI_ACP_WREADY;
wire [7:0]S_AXI_ACP_WSTRB;
wire S_AXI_ACP_WVALID;
wire S_AXI_GP0_ACLK;
wire [31:0]S_AXI_GP0_ARADDR;
wire [1:0]S_AXI_GP0_ARBURST;
wire [3:0]S_AXI_GP0_ARCACHE;
wire S_AXI_GP0_ARESETN;
wire [5:0]S_AXI_GP0_ARID;
wire [3:0]S_AXI_GP0_ARLEN;
wire [1:0]S_AXI_GP0_ARLOCK;
wire [2:0]S_AXI_GP0_ARPROT;
wire [3:0]S_AXI_GP0_ARQOS;
wire S_AXI_GP0_ARREADY;
wire [2:0]S_AXI_GP0_ARSIZE;
wire S_AXI_GP0_ARVALID;
wire [31:0]S_AXI_GP0_AWADDR;
wire [1:0]S_AXI_GP0_AWBURST;
wire [3:0]S_AXI_GP0_AWCACHE;
wire [5:0]S_AXI_GP0_AWID;
wire [3:0]S_AXI_GP0_AWLEN;
wire [1:0]S_AXI_GP0_AWLOCK;
wire [2:0]S_AXI_GP0_AWPROT;
wire [3:0]S_AXI_GP0_AWQOS;
wire S_AXI_GP0_AWREADY;
wire [2:0]S_AXI_GP0_AWSIZE;
wire S_AXI_GP0_AWVALID;
wire [5:0]S_AXI_GP0_BID;
wire S_AXI_GP0_BREADY;
wire [1:0]S_AXI_GP0_BRESP;
wire S_AXI_GP0_BVALID;
wire [31:0]S_AXI_GP0_RDATA;
wire [5:0]S_AXI_GP0_RID;
wire S_AXI_GP0_RLAST;
wire S_AXI_GP0_RREADY;
wire [1:0]S_AXI_GP0_RRESP;
wire S_AXI_GP0_RVALID;
wire [31:0]S_AXI_GP0_WDATA;
wire [5:0]S_AXI_GP0_WID;
wire S_AXI_GP0_WLAST;
wire S_AXI_GP0_WREADY;
wire [3:0]S_AXI_GP0_WSTRB;
wire S_AXI_GP0_WVALID;
wire S_AXI_GP1_ACLK;
wire [31:0]S_AXI_GP1_ARADDR;
wire [1:0]S_AXI_GP1_ARBURST;
wire [3:0]S_AXI_GP1_ARCACHE;
wire S_AXI_GP1_ARESETN;
wire [5:0]S_AXI_GP1_ARID;
wire [3:0]S_AXI_GP1_ARLEN;
wire [1:0]S_AXI_GP1_ARLOCK;
wire [2:0]S_AXI_GP1_ARPROT;
wire [3:0]S_AXI_GP1_ARQOS;
wire S_AXI_GP1_ARREADY;
wire [2:0]S_AXI_GP1_ARSIZE;
wire S_AXI_GP1_ARVALID;
wire [31:0]S_AXI_GP1_AWADDR;
wire [1:0]S_AXI_GP1_AWBURST;
wire [3:0]S_AXI_GP1_AWCACHE;
wire [5:0]S_AXI_GP1_AWID;
wire [3:0]S_AXI_GP1_AWLEN;
wire [1:0]S_AXI_GP1_AWLOCK;
wire [2:0]S_AXI_GP1_AWPROT;
wire [3:0]S_AXI_GP1_AWQOS;
wire S_AXI_GP1_AWREADY;
wire [2:0]S_AXI_GP1_AWSIZE;
wire S_AXI_GP1_AWVALID;
wire [5:0]S_AXI_GP1_BID;
wire S_AXI_GP1_BREADY;
wire [1:0]S_AXI_GP1_BRESP;
wire S_AXI_GP1_BVALID;
wire [31:0]S_AXI_GP1_RDATA;
wire [5:0]S_AXI_GP1_RID;
wire S_AXI_GP1_RLAST;
wire S_AXI_GP1_RREADY;
wire [1:0]S_AXI_GP1_RRESP;
wire S_AXI_GP1_RVALID;
wire [31:0]S_AXI_GP1_WDATA;
wire [5:0]S_AXI_GP1_WID;
wire S_AXI_GP1_WLAST;
wire S_AXI_GP1_WREADY;
wire [3:0]S_AXI_GP1_WSTRB;
wire S_AXI_GP1_WVALID;
wire S_AXI_HP0_ACLK;
wire [31:0]S_AXI_HP0_ARADDR;
wire [1:0]S_AXI_HP0_ARBURST;
wire [3:0]S_AXI_HP0_ARCACHE;
wire S_AXI_HP0_ARESETN;
wire [5:0]S_AXI_HP0_ARID;
wire [3:0]S_AXI_HP0_ARLEN;
wire [1:0]S_AXI_HP0_ARLOCK;
wire [2:0]S_AXI_HP0_ARPROT;
wire [3:0]S_AXI_HP0_ARQOS;
wire S_AXI_HP0_ARREADY;
wire [2:0]S_AXI_HP0_ARSIZE;
wire S_AXI_HP0_ARVALID;
wire [31:0]S_AXI_HP0_AWADDR;
wire [1:0]S_AXI_HP0_AWBURST;
wire [3:0]S_AXI_HP0_AWCACHE;
wire [5:0]S_AXI_HP0_AWID;
wire [3:0]S_AXI_HP0_AWLEN;
wire [1:0]S_AXI_HP0_AWLOCK;
wire [2:0]S_AXI_HP0_AWPROT;
wire [3:0]S_AXI_HP0_AWQOS;
wire S_AXI_HP0_AWREADY;
wire [2:0]S_AXI_HP0_AWSIZE;
wire S_AXI_HP0_AWVALID;
wire [5:0]S_AXI_HP0_BID;
wire S_AXI_HP0_BREADY;
wire [1:0]S_AXI_HP0_BRESP;
wire S_AXI_HP0_BVALID;
wire [2:0]S_AXI_HP0_RACOUNT;
wire [7:0]S_AXI_HP0_RCOUNT;
wire [63:0]S_AXI_HP0_RDATA;
wire S_AXI_HP0_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP0_RID;
wire S_AXI_HP0_RLAST;
wire S_AXI_HP0_RREADY;
wire [1:0]S_AXI_HP0_RRESP;
wire S_AXI_HP0_RVALID;
wire [5:0]S_AXI_HP0_WACOUNT;
wire [7:0]S_AXI_HP0_WCOUNT;
wire [63:0]S_AXI_HP0_WDATA;
wire [5:0]S_AXI_HP0_WID;
wire S_AXI_HP0_WLAST;
wire S_AXI_HP0_WREADY;
wire S_AXI_HP0_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP0_WSTRB;
wire S_AXI_HP0_WVALID;
wire S_AXI_HP1_ACLK;
wire [31:0]S_AXI_HP1_ARADDR;
wire [1:0]S_AXI_HP1_ARBURST;
wire [3:0]S_AXI_HP1_ARCACHE;
wire S_AXI_HP1_ARESETN;
wire [5:0]S_AXI_HP1_ARID;
wire [3:0]S_AXI_HP1_ARLEN;
wire [1:0]S_AXI_HP1_ARLOCK;
wire [2:0]S_AXI_HP1_ARPROT;
wire [3:0]S_AXI_HP1_ARQOS;
wire S_AXI_HP1_ARREADY;
wire [2:0]S_AXI_HP1_ARSIZE;
wire S_AXI_HP1_ARVALID;
wire [31:0]S_AXI_HP1_AWADDR;
wire [1:0]S_AXI_HP1_AWBURST;
wire [3:0]S_AXI_HP1_AWCACHE;
wire [5:0]S_AXI_HP1_AWID;
wire [3:0]S_AXI_HP1_AWLEN;
wire [1:0]S_AXI_HP1_AWLOCK;
wire [2:0]S_AXI_HP1_AWPROT;
wire [3:0]S_AXI_HP1_AWQOS;
wire S_AXI_HP1_AWREADY;
wire [2:0]S_AXI_HP1_AWSIZE;
wire S_AXI_HP1_AWVALID;
wire [5:0]S_AXI_HP1_BID;
wire S_AXI_HP1_BREADY;
wire [1:0]S_AXI_HP1_BRESP;
wire S_AXI_HP1_BVALID;
wire [2:0]S_AXI_HP1_RACOUNT;
wire [7:0]S_AXI_HP1_RCOUNT;
wire [63:0]S_AXI_HP1_RDATA;
wire S_AXI_HP1_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP1_RID;
wire S_AXI_HP1_RLAST;
wire S_AXI_HP1_RREADY;
wire [1:0]S_AXI_HP1_RRESP;
wire S_AXI_HP1_RVALID;
wire [5:0]S_AXI_HP1_WACOUNT;
wire [7:0]S_AXI_HP1_WCOUNT;
wire [63:0]S_AXI_HP1_WDATA;
wire [5:0]S_AXI_HP1_WID;
wire S_AXI_HP1_WLAST;
wire S_AXI_HP1_WREADY;
wire S_AXI_HP1_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP1_WSTRB;
wire S_AXI_HP1_WVALID;
wire S_AXI_HP2_ACLK;
wire [31:0]S_AXI_HP2_ARADDR;
wire [1:0]S_AXI_HP2_ARBURST;
wire [3:0]S_AXI_HP2_ARCACHE;
wire S_AXI_HP2_ARESETN;
wire [5:0]S_AXI_HP2_ARID;
wire [3:0]S_AXI_HP2_ARLEN;
wire [1:0]S_AXI_HP2_ARLOCK;
wire [2:0]S_AXI_HP2_ARPROT;
wire [3:0]S_AXI_HP2_ARQOS;
wire S_AXI_HP2_ARREADY;
wire [2:0]S_AXI_HP2_ARSIZE;
wire S_AXI_HP2_ARVALID;
wire [31:0]S_AXI_HP2_AWADDR;
wire [1:0]S_AXI_HP2_AWBURST;
wire [3:0]S_AXI_HP2_AWCACHE;
wire [5:0]S_AXI_HP2_AWID;
wire [3:0]S_AXI_HP2_AWLEN;
wire [1:0]S_AXI_HP2_AWLOCK;
wire [2:0]S_AXI_HP2_AWPROT;
wire [3:0]S_AXI_HP2_AWQOS;
wire S_AXI_HP2_AWREADY;
wire [2:0]S_AXI_HP2_AWSIZE;
wire S_AXI_HP2_AWVALID;
wire [5:0]S_AXI_HP2_BID;
wire S_AXI_HP2_BREADY;
wire [1:0]S_AXI_HP2_BRESP;
wire S_AXI_HP2_BVALID;
wire [2:0]S_AXI_HP2_RACOUNT;
wire [7:0]S_AXI_HP2_RCOUNT;
wire [63:0]S_AXI_HP2_RDATA;
wire S_AXI_HP2_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP2_RID;
wire S_AXI_HP2_RLAST;
wire S_AXI_HP2_RREADY;
wire [1:0]S_AXI_HP2_RRESP;
wire S_AXI_HP2_RVALID;
wire [5:0]S_AXI_HP2_WACOUNT;
wire [7:0]S_AXI_HP2_WCOUNT;
wire [63:0]S_AXI_HP2_WDATA;
wire [5:0]S_AXI_HP2_WID;
wire S_AXI_HP2_WLAST;
wire S_AXI_HP2_WREADY;
wire S_AXI_HP2_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP2_WSTRB;
wire S_AXI_HP2_WVALID;
wire S_AXI_HP3_ACLK;
wire [31:0]S_AXI_HP3_ARADDR;
wire [1:0]S_AXI_HP3_ARBURST;
wire [3:0]S_AXI_HP3_ARCACHE;
wire S_AXI_HP3_ARESETN;
wire [5:0]S_AXI_HP3_ARID;
wire [3:0]S_AXI_HP3_ARLEN;
wire [1:0]S_AXI_HP3_ARLOCK;
wire [2:0]S_AXI_HP3_ARPROT;
wire [3:0]S_AXI_HP3_ARQOS;
wire S_AXI_HP3_ARREADY;
wire [2:0]S_AXI_HP3_ARSIZE;
wire S_AXI_HP3_ARVALID;
wire [31:0]S_AXI_HP3_AWADDR;
wire [1:0]S_AXI_HP3_AWBURST;
wire [3:0]S_AXI_HP3_AWCACHE;
wire [5:0]S_AXI_HP3_AWID;
wire [3:0]S_AXI_HP3_AWLEN;
wire [1:0]S_AXI_HP3_AWLOCK;
wire [2:0]S_AXI_HP3_AWPROT;
wire [3:0]S_AXI_HP3_AWQOS;
wire S_AXI_HP3_AWREADY;
wire [2:0]S_AXI_HP3_AWSIZE;
wire S_AXI_HP3_AWVALID;
wire [5:0]S_AXI_HP3_BID;
wire S_AXI_HP3_BREADY;
wire [1:0]S_AXI_HP3_BRESP;
wire S_AXI_HP3_BVALID;
wire [2:0]S_AXI_HP3_RACOUNT;
wire [7:0]S_AXI_HP3_RCOUNT;
wire [63:0]S_AXI_HP3_RDATA;
wire S_AXI_HP3_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP3_RID;
wire S_AXI_HP3_RLAST;
wire S_AXI_HP3_RREADY;
wire [1:0]S_AXI_HP3_RRESP;
wire S_AXI_HP3_RVALID;
wire [5:0]S_AXI_HP3_WACOUNT;
wire [7:0]S_AXI_HP3_WCOUNT;
wire [63:0]S_AXI_HP3_WDATA;
wire [5:0]S_AXI_HP3_WID;
wire S_AXI_HP3_WLAST;
wire S_AXI_HP3_WREADY;
wire S_AXI_HP3_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP3_WSTRB;
wire S_AXI_HP3_WVALID;
wire TRACE_CLK;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[0] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[1] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[2] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[3] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[4] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[5] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[6] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[7] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[0] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[1] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[2] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[3] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[4] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[5] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[6] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[7] ;
wire TTC0_CLK0_IN;
wire TTC0_CLK1_IN;
wire TTC0_CLK2_IN;
wire TTC0_WAVE0_OUT;
wire TTC0_WAVE1_OUT;
wire TTC0_WAVE2_OUT;
wire TTC1_CLK0_IN;
wire TTC1_CLK1_IN;
wire TTC1_CLK2_IN;
wire TTC1_WAVE0_OUT;
wire TTC1_WAVE1_OUT;
wire TTC1_WAVE2_OUT;
wire UART0_CTSN;
wire UART0_DCDN;
wire UART0_DSRN;
wire UART0_DTRN;
wire UART0_RIN;
wire UART0_RTSN;
wire UART0_RX;
wire UART0_TX;
wire UART1_CTSN;
wire UART1_DCDN;
wire UART1_DSRN;
wire UART1_DTRN;
wire UART1_RIN;
wire UART1_RTSN;
wire UART1_RX;
wire UART1_TX;
wire [1:0]USB0_PORT_INDCTL;
wire USB0_VBUS_PWRFAULT;
wire USB0_VBUS_PWRSELECT;
wire [1:0]USB1_PORT_INDCTL;
wire USB1_VBUS_PWRFAULT;
wire USB1_VBUS_PWRSELECT;
wire WDT_CLK_IN;
wire WDT_RST_OUT;
wire [14:0]buffered_DDR_Addr;
wire [2:0]buffered_DDR_BankAddr;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_CS_n;
wire buffered_DDR_Clk;
wire buffered_DDR_Clk_n;
wire [3:0]buffered_DDR_DM;
wire [31:0]buffered_DDR_DQ;
wire [3:0]buffered_DDR_DQS;
wire [3:0]buffered_DDR_DQS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire buffered_DDR_WEB;
wire [53:0]buffered_MIO;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire buffered_PS_SRSTB;
wire [63:0]gpio_out_t_n;
wire NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED;
wire NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED;
wire NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED;
wire NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED;
wire NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED;
wire NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED;
wire NLW_PS7_i_EMIOTRACECTL_UNCONNECTED;
wire [7:0]NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED;
wire [7:0]NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED;
wire [31:0]NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED;
assign ENET0_GMII_TXD[7] = \<const0> ;
assign ENET0_GMII_TXD[6] = \<const0> ;
assign ENET0_GMII_TXD[5] = \<const0> ;
assign ENET0_GMII_TXD[4] = \<const0> ;
assign ENET0_GMII_TXD[3] = \<const0> ;
assign ENET0_GMII_TXD[2] = \<const0> ;
assign ENET0_GMII_TXD[1] = \<const0> ;
assign ENET0_GMII_TXD[0] = \<const0> ;
assign ENET0_GMII_TX_EN = \<const0> ;
assign ENET0_GMII_TX_ER = \<const0> ;
assign ENET1_GMII_TXD[7] = \<const0> ;
assign ENET1_GMII_TXD[6] = \<const0> ;
assign ENET1_GMII_TXD[5] = \<const0> ;
assign ENET1_GMII_TXD[4] = \<const0> ;
assign ENET1_GMII_TXD[3] = \<const0> ;
assign ENET1_GMII_TXD[2] = \<const0> ;
assign ENET1_GMII_TXD[1] = \<const0> ;
assign ENET1_GMII_TXD[0] = \<const0> ;
assign ENET1_GMII_TX_EN = \<const0> ;
assign ENET1_GMII_TX_ER = \<const0> ;
assign M_AXI_GP0_ARSIZE[2] = \<const0> ;
assign M_AXI_GP0_ARSIZE[1:0] = \^M_AXI_GP0_ARSIZE [1:0];
assign M_AXI_GP0_AWSIZE[2] = \<const0> ;
assign M_AXI_GP0_AWSIZE[1:0] = \^M_AXI_GP0_AWSIZE [1:0];
assign M_AXI_GP1_ARSIZE[2] = \<const0> ;
assign M_AXI_GP1_ARSIZE[1:0] = \^M_AXI_GP1_ARSIZE [1:0];
assign M_AXI_GP1_AWSIZE[2] = \<const0> ;
assign M_AXI_GP1_AWSIZE[1:0] = \^M_AXI_GP1_AWSIZE [1:0];
assign PJTAG_TDO = \<const0> ;
assign TRACE_CLK_OUT = \<const0> ;
assign TRACE_CTL = \TRACE_CTL_PIPE[0] ;
assign TRACE_DATA[1:0] = \TRACE_DATA_PIPE[0] ;
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CAS_n_BIBUF
(.IO(buffered_DDR_CAS_n),
.PAD(DDR_CAS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CKE_BIBUF
(.IO(buffered_DDR_CKE),
.PAD(DDR_CKE));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CS_n_BIBUF
(.IO(buffered_DDR_CS_n),
.PAD(DDR_CS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_BIBUF
(.IO(buffered_DDR_Clk),
.PAD(DDR_Clk));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_n_BIBUF
(.IO(buffered_DDR_Clk_n),
.PAD(DDR_Clk_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_DRSTB_BIBUF
(.IO(buffered_DDR_DRSTB),
.PAD(DDR_DRSTB));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_ODT_BIBUF
(.IO(buffered_DDR_ODT),
.PAD(DDR_ODT));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_RAS_n_BIBUF
(.IO(buffered_DDR_RAS_n),
.PAD(DDR_RAS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRN_BIBUF
(.IO(buffered_DDR_VRN),
.PAD(DDR_VRN));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRP_BIBUF
(.IO(buffered_DDR_VRP),
.PAD(DDR_VRP));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_WEB_BIBUF
(.IO(buffered_DDR_WEB),
.PAD(DDR_WEB));
LUT1 #(
.INIT(2'h1))
ENET0_MDIO_T_INST_0
(.I0(ENET0_MDIO_T_n),
.O(ENET0_MDIO_T));
LUT1 #(
.INIT(2'h1))
ENET1_MDIO_T_INST_0
(.I0(ENET1_MDIO_T_n),
.O(ENET1_MDIO_T));
GND GND
(.G(\<const0> ));
LUT1 #(
.INIT(2'h1))
\GPIO_T[0]_INST_0
(.I0(gpio_out_t_n[0]),
.O(GPIO_T[0]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[10]_INST_0
(.I0(gpio_out_t_n[10]),
.O(GPIO_T[10]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[11]_INST_0
(.I0(gpio_out_t_n[11]),
.O(GPIO_T[11]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[12]_INST_0
(.I0(gpio_out_t_n[12]),
.O(GPIO_T[12]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[13]_INST_0
(.I0(gpio_out_t_n[13]),
.O(GPIO_T[13]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[14]_INST_0
(.I0(gpio_out_t_n[14]),
.O(GPIO_T[14]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[15]_INST_0
(.I0(gpio_out_t_n[15]),
.O(GPIO_T[15]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[16]_INST_0
(.I0(gpio_out_t_n[16]),
.O(GPIO_T[16]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[17]_INST_0
(.I0(gpio_out_t_n[17]),
.O(GPIO_T[17]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[18]_INST_0
(.I0(gpio_out_t_n[18]),
.O(GPIO_T[18]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[19]_INST_0
(.I0(gpio_out_t_n[19]),
.O(GPIO_T[19]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[1]_INST_0
(.I0(gpio_out_t_n[1]),
.O(GPIO_T[1]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[20]_INST_0
(.I0(gpio_out_t_n[20]),
.O(GPIO_T[20]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[21]_INST_0
(.I0(gpio_out_t_n[21]),
.O(GPIO_T[21]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[22]_INST_0
(.I0(gpio_out_t_n[22]),
.O(GPIO_T[22]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[23]_INST_0
(.I0(gpio_out_t_n[23]),
.O(GPIO_T[23]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[24]_INST_0
(.I0(gpio_out_t_n[24]),
.O(GPIO_T[24]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[25]_INST_0
(.I0(gpio_out_t_n[25]),
.O(GPIO_T[25]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[26]_INST_0
(.I0(gpio_out_t_n[26]),
.O(GPIO_T[26]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[27]_INST_0
(.I0(gpio_out_t_n[27]),
.O(GPIO_T[27]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[28]_INST_0
(.I0(gpio_out_t_n[28]),
.O(GPIO_T[28]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[29]_INST_0
(.I0(gpio_out_t_n[29]),
.O(GPIO_T[29]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[2]_INST_0
(.I0(gpio_out_t_n[2]),
.O(GPIO_T[2]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[30]_INST_0
(.I0(gpio_out_t_n[30]),
.O(GPIO_T[30]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[31]_INST_0
(.I0(gpio_out_t_n[31]),
.O(GPIO_T[31]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[32]_INST_0
(.I0(gpio_out_t_n[32]),
.O(GPIO_T[32]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[33]_INST_0
(.I0(gpio_out_t_n[33]),
.O(GPIO_T[33]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[34]_INST_0
(.I0(gpio_out_t_n[34]),
.O(GPIO_T[34]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[35]_INST_0
(.I0(gpio_out_t_n[35]),
.O(GPIO_T[35]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[36]_INST_0
(.I0(gpio_out_t_n[36]),
.O(GPIO_T[36]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[37]_INST_0
(.I0(gpio_out_t_n[37]),
.O(GPIO_T[37]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[38]_INST_0
(.I0(gpio_out_t_n[38]),
.O(GPIO_T[38]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[39]_INST_0
(.I0(gpio_out_t_n[39]),
.O(GPIO_T[39]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[3]_INST_0
(.I0(gpio_out_t_n[3]),
.O(GPIO_T[3]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[40]_INST_0
(.I0(gpio_out_t_n[40]),
.O(GPIO_T[40]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[41]_INST_0
(.I0(gpio_out_t_n[41]),
.O(GPIO_T[41]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[42]_INST_0
(.I0(gpio_out_t_n[42]),
.O(GPIO_T[42]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[43]_INST_0
(.I0(gpio_out_t_n[43]),
.O(GPIO_T[43]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[44]_INST_0
(.I0(gpio_out_t_n[44]),
.O(GPIO_T[44]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[45]_INST_0
(.I0(gpio_out_t_n[45]),
.O(GPIO_T[45]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[46]_INST_0
(.I0(gpio_out_t_n[46]),
.O(GPIO_T[46]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[47]_INST_0
(.I0(gpio_out_t_n[47]),
.O(GPIO_T[47]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[48]_INST_0
(.I0(gpio_out_t_n[48]),
.O(GPIO_T[48]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[49]_INST_0
(.I0(gpio_out_t_n[49]),
.O(GPIO_T[49]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[4]_INST_0
(.I0(gpio_out_t_n[4]),
.O(GPIO_T[4]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[50]_INST_0
(.I0(gpio_out_t_n[50]),
.O(GPIO_T[50]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[51]_INST_0
(.I0(gpio_out_t_n[51]),
.O(GPIO_T[51]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[52]_INST_0
(.I0(gpio_out_t_n[52]),
.O(GPIO_T[52]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[53]_INST_0
(.I0(gpio_out_t_n[53]),
.O(GPIO_T[53]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[54]_INST_0
(.I0(gpio_out_t_n[54]),
.O(GPIO_T[54]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[55]_INST_0
(.I0(gpio_out_t_n[55]),
.O(GPIO_T[55]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[56]_INST_0
(.I0(gpio_out_t_n[56]),
.O(GPIO_T[56]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[57]_INST_0
(.I0(gpio_out_t_n[57]),
.O(GPIO_T[57]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[58]_INST_0
(.I0(gpio_out_t_n[58]),
.O(GPIO_T[58]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[59]_INST_0
(.I0(gpio_out_t_n[59]),
.O(GPIO_T[59]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[5]_INST_0
(.I0(gpio_out_t_n[5]),
.O(GPIO_T[5]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[60]_INST_0
(.I0(gpio_out_t_n[60]),
.O(GPIO_T[60]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[61]_INST_0
(.I0(gpio_out_t_n[61]),
.O(GPIO_T[61]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[62]_INST_0
(.I0(gpio_out_t_n[62]),
.O(GPIO_T[62]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[63]_INST_0
(.I0(gpio_out_t_n[63]),
.O(GPIO_T[63]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[6]_INST_0
(.I0(gpio_out_t_n[6]),
.O(GPIO_T[6]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[7]_INST_0
(.I0(gpio_out_t_n[7]),
.O(GPIO_T[7]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[8]_INST_0
(.I0(gpio_out_t_n[8]),
.O(GPIO_T[8]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[9]_INST_0
(.I0(gpio_out_t_n[9]),
.O(GPIO_T[9]));
LUT1 #(
.INIT(2'h1))
I2C0_SCL_T_INST_0
(.I0(I2C0_SCL_T_n),
.O(I2C0_SCL_T));
LUT1 #(
.INIT(2'h1))
I2C0_SDA_T_INST_0
(.I0(I2C0_SDA_T_n),
.O(I2C0_SDA_T));
LUT1 #(
.INIT(2'h1))
I2C1_SCL_T_INST_0
(.I0(I2C1_SCL_T_n),
.O(I2C1_SCL_T));
LUT1 #(
.INIT(2'h1))
I2C1_SDA_T_INST_0
(.I0(I2C1_SDA_T_n),
.O(I2C1_SDA_T));
(* BOX_TYPE = "PRIMITIVE" *)
PS7 PS7_i
(.DDRA(buffered_DDR_Addr),
.DDRARB(DDR_ARB),
.DDRBA(buffered_DDR_BankAddr),
.DDRCASB(buffered_DDR_CAS_n),
.DDRCKE(buffered_DDR_CKE),
.DDRCKN(buffered_DDR_Clk_n),
.DDRCKP(buffered_DDR_Clk),
.DDRCSB(buffered_DDR_CS_n),
.DDRDM(buffered_DDR_DM),
.DDRDQ(buffered_DDR_DQ),
.DDRDQSN(buffered_DDR_DQS_n),
.DDRDQSP(buffered_DDR_DQS),
.DDRDRSTB(buffered_DDR_DRSTB),
.DDRODT(buffered_DDR_ODT),
.DDRRASB(buffered_DDR_RAS_n),
.DDRVRN(buffered_DDR_VRN),
.DDRVRP(buffered_DDR_VRP),
.DDRWEB(buffered_DDR_WEB),
.DMA0ACLK(DMA0_ACLK),
.DMA0DAREADY(DMA0_DAREADY),
.DMA0DATYPE(DMA0_DATYPE),
.DMA0DAVALID(DMA0_DAVALID),
.DMA0DRLAST(DMA0_DRLAST),
.DMA0DRREADY(DMA0_DRREADY),
.DMA0DRTYPE(DMA0_DRTYPE),
.DMA0DRVALID(DMA0_DRVALID),
.DMA0RSTN(DMA0_RSTN),
.DMA1ACLK(DMA1_ACLK),
.DMA1DAREADY(DMA1_DAREADY),
.DMA1DATYPE(DMA1_DATYPE),
.DMA1DAVALID(DMA1_DAVALID),
.DMA1DRLAST(DMA1_DRLAST),
.DMA1DRREADY(DMA1_DRREADY),
.DMA1DRTYPE(DMA1_DRTYPE),
.DMA1DRVALID(DMA1_DRVALID),
.DMA1RSTN(DMA1_RSTN),
.DMA2ACLK(DMA2_ACLK),
.DMA2DAREADY(DMA2_DAREADY),
.DMA2DATYPE(DMA2_DATYPE),
.DMA2DAVALID(DMA2_DAVALID),
.DMA2DRLAST(DMA2_DRLAST),
.DMA2DRREADY(DMA2_DRREADY),
.DMA2DRTYPE(DMA2_DRTYPE),
.DMA2DRVALID(DMA2_DRVALID),
.DMA2RSTN(DMA2_RSTN),
.DMA3ACLK(DMA3_ACLK),
.DMA3DAREADY(DMA3_DAREADY),
.DMA3DATYPE(DMA3_DATYPE),
.DMA3DAVALID(DMA3_DAVALID),
.DMA3DRLAST(DMA3_DRLAST),
.DMA3DRREADY(DMA3_DRREADY),
.DMA3DRTYPE(DMA3_DRTYPE),
.DMA3DRVALID(DMA3_DRVALID),
.DMA3RSTN(DMA3_RSTN),
.EMIOCAN0PHYRX(CAN0_PHY_RX),
.EMIOCAN0PHYTX(CAN0_PHY_TX),
.EMIOCAN1PHYRX(CAN1_PHY_RX),
.EMIOCAN1PHYTX(CAN1_PHY_TX),
.EMIOENET0EXTINTIN(ENET0_EXT_INTIN),
.EMIOENET0GMIICOL(1'b0),
.EMIOENET0GMIICRS(1'b0),
.EMIOENET0GMIIRXCLK(ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.EMIOENET0GMIIRXDV(1'b0),
.EMIOENET0GMIIRXER(1'b0),
.EMIOENET0GMIITXCLK(ENET0_GMII_TX_CLK),
.EMIOENET0GMIITXD(NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED[7:0]),
.EMIOENET0GMIITXEN(NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED),
.EMIOENET0GMIITXER(NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED),
.EMIOENET0MDIOI(ENET0_MDIO_I),
.EMIOENET0MDIOMDC(ENET0_MDIO_MDC),
.EMIOENET0MDIOO(ENET0_MDIO_O),
.EMIOENET0MDIOTN(ENET0_MDIO_T_n),
.EMIOENET0PTPDELAYREQRX(ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX(ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX(ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX(ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX(ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX(ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX(ENET0_SOF_RX),
.EMIOENET0SOFTX(ENET0_SOF_TX),
.EMIOENET1EXTINTIN(ENET1_EXT_INTIN),
.EMIOENET1GMIICOL(1'b0),
.EMIOENET1GMIICRS(1'b0),
.EMIOENET1GMIIRXCLK(ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.EMIOENET1GMIIRXDV(1'b0),
.EMIOENET1GMIIRXER(1'b0),
.EMIOENET1GMIITXCLK(ENET1_GMII_TX_CLK),
.EMIOENET1GMIITXD(NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED[7:0]),
.EMIOENET1GMIITXEN(NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED),
.EMIOENET1GMIITXER(NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED),
.EMIOENET1MDIOI(ENET1_MDIO_I),
.EMIOENET1MDIOMDC(ENET1_MDIO_MDC),
.EMIOENET1MDIOO(ENET1_MDIO_O),
.EMIOENET1MDIOTN(ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX(ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX(ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX(ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX(ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX(ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX(ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX(ENET1_SOF_RX),
.EMIOENET1SOFTX(ENET1_SOF_TX),
.EMIOGPIOI(GPIO_I),
.EMIOGPIOO(GPIO_O),
.EMIOGPIOTN(gpio_out_t_n),
.EMIOI2C0SCLI(I2C0_SCL_I),
.EMIOI2C0SCLO(I2C0_SCL_O),
.EMIOI2C0SCLTN(I2C0_SCL_T_n),
.EMIOI2C0SDAI(I2C0_SDA_I),
.EMIOI2C0SDAO(I2C0_SDA_O),
.EMIOI2C0SDATN(I2C0_SDA_T_n),
.EMIOI2C1SCLI(I2C1_SCL_I),
.EMIOI2C1SCLO(I2C1_SCL_O),
.EMIOI2C1SCLTN(I2C1_SCL_T_n),
.EMIOI2C1SDAI(I2C1_SDA_I),
.EMIOI2C1SDAO(I2C1_SDA_O),
.EMIOI2C1SDATN(I2C1_SDA_T_n),
.EMIOPJTAGTCK(PJTAG_TCK),
.EMIOPJTAGTDI(PJTAG_TDI),
.EMIOPJTAGTDO(NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED),
.EMIOPJTAGTDTN(NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED),
.EMIOPJTAGTMS(PJTAG_TMS),
.EMIOSDIO0BUSPOW(SDIO0_BUSPOW),
.EMIOSDIO0BUSVOLT(SDIO0_BUSVOLT),
.EMIOSDIO0CDN(SDIO0_CDN),
.EMIOSDIO0CLK(SDIO0_CLK),
.EMIOSDIO0CLKFB(SDIO0_CLK_FB),
.EMIOSDIO0CMDI(SDIO0_CMD_I),
.EMIOSDIO0CMDO(SDIO0_CMD_O),
.EMIOSDIO0CMDTN(SDIO0_CMD_T_n),
.EMIOSDIO0DATAI(SDIO0_DATA_I),
.EMIOSDIO0DATAO(SDIO0_DATA_O),
.EMIOSDIO0DATATN(SDIO0_DATA_T_n),
.EMIOSDIO0LED(SDIO0_LED),
.EMIOSDIO0WP(SDIO0_WP),
.EMIOSDIO1BUSPOW(SDIO1_BUSPOW),
.EMIOSDIO1BUSVOLT(SDIO1_BUSVOLT),
.EMIOSDIO1CDN(SDIO1_CDN),
.EMIOSDIO1CLK(SDIO1_CLK),
.EMIOSDIO1CLKFB(SDIO1_CLK_FB),
.EMIOSDIO1CMDI(SDIO1_CMD_I),
.EMIOSDIO1CMDO(SDIO1_CMD_O),
.EMIOSDIO1CMDTN(SDIO1_CMD_T_n),
.EMIOSDIO1DATAI(SDIO1_DATA_I),
.EMIOSDIO1DATAO(SDIO1_DATA_O),
.EMIOSDIO1DATATN(SDIO1_DATA_T_n),
.EMIOSDIO1LED(SDIO1_LED),
.EMIOSDIO1WP(SDIO1_WP),
.EMIOSPI0MI(SPI0_MISO_I),
.EMIOSPI0MO(SPI0_MOSI_O),
.EMIOSPI0MOTN(SPI0_MOSI_T_n),
.EMIOSPI0SCLKI(SPI0_SCLK_I),
.EMIOSPI0SCLKO(SPI0_SCLK_O),
.EMIOSPI0SCLKTN(SPI0_SCLK_T_n),
.EMIOSPI0SI(SPI0_MOSI_I),
.EMIOSPI0SO(SPI0_MISO_O),
.EMIOSPI0SSIN(SPI0_SS_I),
.EMIOSPI0SSNTN(SPI0_SS_T_n),
.EMIOSPI0SSON({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0STN(SPI0_MISO_T_n),
.EMIOSPI1MI(SPI1_MISO_I),
.EMIOSPI1MO(SPI1_MOSI_O),
.EMIOSPI1MOTN(SPI1_MOSI_T_n),
.EMIOSPI1SCLKI(SPI1_SCLK_I),
.EMIOSPI1SCLKO(SPI1_SCLK_O),
.EMIOSPI1SCLKTN(SPI1_SCLK_T_n),
.EMIOSPI1SI(SPI1_MOSI_I),
.EMIOSPI1SO(SPI1_MISO_O),
.EMIOSPI1SSIN(SPI1_SS_I),
.EMIOSPI1SSNTN(SPI1_SS_T_n),
.EMIOSPI1SSON({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1STN(SPI1_MISO_T_n),
.EMIOSRAMINTIN(SRAM_INTIN),
.EMIOTRACECLK(TRACE_CLK),
.EMIOTRACECTL(NLW_PS7_i_EMIOTRACECTL_UNCONNECTED),
.EMIOTRACEDATA(NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED[31:0]),
.EMIOTTC0CLKI({TTC0_CLK2_IN,TTC0_CLK1_IN,TTC0_CLK0_IN}),
.EMIOTTC0WAVEO({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1CLKI({TTC1_CLK2_IN,TTC1_CLK1_IN,TTC1_CLK0_IN}),
.EMIOTTC1WAVEO({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0CTSN(UART0_CTSN),
.EMIOUART0DCDN(UART0_DCDN),
.EMIOUART0DSRN(UART0_DSRN),
.EMIOUART0DTRN(UART0_DTRN),
.EMIOUART0RIN(UART0_RIN),
.EMIOUART0RTSN(UART0_RTSN),
.EMIOUART0RX(UART0_RX),
.EMIOUART0TX(UART0_TX),
.EMIOUART1CTSN(UART1_CTSN),
.EMIOUART1DCDN(UART1_DCDN),
.EMIOUART1DSRN(UART1_DSRN),
.EMIOUART1DTRN(UART1_DTRN),
.EMIOUART1RIN(UART1_RIN),
.EMIOUART1RTSN(UART1_RTSN),
.EMIOUART1RX(UART1_RX),
.EMIOUART1TX(UART1_TX),
.EMIOUSB0PORTINDCTL(USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRFAULT(USB0_VBUS_PWRFAULT),
.EMIOUSB0VBUSPWRSELECT(USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL(USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRFAULT(USB1_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRSELECT(USB1_VBUS_PWRSELECT),
.EMIOWDTCLKI(WDT_CLK_IN),
.EMIOWDTRSTO(WDT_RST_OUT),
.EVENTEVENTI(EVENT_EVENTI),
.EVENTEVENTO(EVENT_EVENTO),
.EVENTSTANDBYWFE(EVENT_STANDBYWFE),
.EVENTSTANDBYWFI(EVENT_STANDBYWFI),
.FCLKCLK({FCLK_CLK3,FCLK_CLK2,FCLK_CLK1,FCLK_CLK_unbuffered}),
.FCLKCLKTRIGN({1'b0,1'b0,1'b0,1'b0}),
.FCLKRESETN({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.FPGAIDLEN(FPGA_IDLE_N),
.FTMDTRACEINATID({1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINCLOCK(FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINVALID(1'b0),
.FTMTF2PDEBUG(FTMT_F2P_DEBUG),
.FTMTF2PTRIG({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTF2PTRIGACK({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG(FTMT_P2F_DEBUG),
.FTMTP2FTRIG({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.FTMTP2FTRIGACK({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P({Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,IRQ_F2P}),
.IRQP2F({IRQ_P2F_DMAC_ABORT,IRQ_P2F_DMAC7,IRQ_P2F_DMAC6,IRQ_P2F_DMAC5,IRQ_P2F_DMAC4,IRQ_P2F_DMAC3,IRQ_P2F_DMAC2,IRQ_P2F_DMAC1,IRQ_P2F_DMAC0,IRQ_P2F_SMC,IRQ_P2F_QSPI,IRQ_P2F_CTI,IRQ_P2F_GPIO,IRQ_P2F_USB0,IRQ_P2F_ENET0,IRQ_P2F_ENET_WAKE0,IRQ_P2F_SDIO0,IRQ_P2F_I2C0,IRQ_P2F_SPI0,IRQ_P2F_UART0,IRQ_P2F_CAN0,IRQ_P2F_USB1,IRQ_P2F_ENET1,IRQ_P2F_ENET_WAKE1,IRQ_P2F_SDIO1,IRQ_P2F_I2C1,IRQ_P2F_SPI1,IRQ_P2F_UART1,IRQ_P2F_CAN1}),
.MAXIGP0ACLK(M_AXI_GP0_ACLK),
.MAXIGP0ARADDR(M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST(M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE(M_AXI_GP0_ARCACHE),
.MAXIGP0ARESETN(M_AXI_GP0_ARESETN),
.MAXIGP0ARID(M_AXI_GP0_ARID),
.MAXIGP0ARLEN(M_AXI_GP0_ARLEN),
.MAXIGP0ARLOCK(M_AXI_GP0_ARLOCK),
.MAXIGP0ARPROT(M_AXI_GP0_ARPROT),
.MAXIGP0ARQOS(M_AXI_GP0_ARQOS),
.MAXIGP0ARREADY(M_AXI_GP0_ARREADY),
.MAXIGP0ARSIZE(\^M_AXI_GP0_ARSIZE ),
.MAXIGP0ARVALID(M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR(M_AXI_GP0_AWADDR),
.MAXIGP0AWBURST(M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE(M_AXI_GP0_AWCACHE),
.MAXIGP0AWID(M_AXI_GP0_AWID),
.MAXIGP0AWLEN(M_AXI_GP0_AWLEN),
.MAXIGP0AWLOCK(M_AXI_GP0_AWLOCK),
.MAXIGP0AWPROT(M_AXI_GP0_AWPROT),
.MAXIGP0AWQOS(M_AXI_GP0_AWQOS),
.MAXIGP0AWREADY(M_AXI_GP0_AWREADY),
.MAXIGP0AWSIZE(\^M_AXI_GP0_AWSIZE ),
.MAXIGP0AWVALID(M_AXI_GP0_AWVALID),
.MAXIGP0BID(M_AXI_GP0_BID),
.MAXIGP0BREADY(M_AXI_GP0_BREADY),
.MAXIGP0BRESP(M_AXI_GP0_BRESP),
.MAXIGP0BVALID(M_AXI_GP0_BVALID),
.MAXIGP0RDATA(M_AXI_GP0_RDATA),
.MAXIGP0RID(M_AXI_GP0_RID),
.MAXIGP0RLAST(M_AXI_GP0_RLAST),
.MAXIGP0RREADY(M_AXI_GP0_RREADY),
.MAXIGP0RRESP(M_AXI_GP0_RRESP),
.MAXIGP0RVALID(M_AXI_GP0_RVALID),
.MAXIGP0WDATA(M_AXI_GP0_WDATA),
.MAXIGP0WID(M_AXI_GP0_WID),
.MAXIGP0WLAST(M_AXI_GP0_WLAST),
.MAXIGP0WREADY(M_AXI_GP0_WREADY),
.MAXIGP0WSTRB(M_AXI_GP0_WSTRB),
.MAXIGP0WVALID(M_AXI_GP0_WVALID),
.MAXIGP1ACLK(M_AXI_GP1_ACLK),
.MAXIGP1ARADDR(M_AXI_GP1_ARADDR),
.MAXIGP1ARBURST(M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE(M_AXI_GP1_ARCACHE),
.MAXIGP1ARESETN(M_AXI_GP1_ARESETN),
.MAXIGP1ARID(M_AXI_GP1_ARID),
.MAXIGP1ARLEN(M_AXI_GP1_ARLEN),
.MAXIGP1ARLOCK(M_AXI_GP1_ARLOCK),
.MAXIGP1ARPROT(M_AXI_GP1_ARPROT),
.MAXIGP1ARQOS(M_AXI_GP1_ARQOS),
.MAXIGP1ARREADY(M_AXI_GP1_ARREADY),
.MAXIGP1ARSIZE(\^M_AXI_GP1_ARSIZE ),
.MAXIGP1ARVALID(M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR(M_AXI_GP1_AWADDR),
.MAXIGP1AWBURST(M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE(M_AXI_GP1_AWCACHE),
.MAXIGP1AWID(M_AXI_GP1_AWID),
.MAXIGP1AWLEN(M_AXI_GP1_AWLEN),
.MAXIGP1AWLOCK(M_AXI_GP1_AWLOCK),
.MAXIGP1AWPROT(M_AXI_GP1_AWPROT),
.MAXIGP1AWQOS(M_AXI_GP1_AWQOS),
.MAXIGP1AWREADY(M_AXI_GP1_AWREADY),
.MAXIGP1AWSIZE(\^M_AXI_GP1_AWSIZE ),
.MAXIGP1AWVALID(M_AXI_GP1_AWVALID),
.MAXIGP1BID(M_AXI_GP1_BID),
.MAXIGP1BREADY(M_AXI_GP1_BREADY),
.MAXIGP1BRESP(M_AXI_GP1_BRESP),
.MAXIGP1BVALID(M_AXI_GP1_BVALID),
.MAXIGP1RDATA(M_AXI_GP1_RDATA),
.MAXIGP1RID(M_AXI_GP1_RID),
.MAXIGP1RLAST(M_AXI_GP1_RLAST),
.MAXIGP1RREADY(M_AXI_GP1_RREADY),
.MAXIGP1RRESP(M_AXI_GP1_RRESP),
.MAXIGP1RVALID(M_AXI_GP1_RVALID),
.MAXIGP1WDATA(M_AXI_GP1_WDATA),
.MAXIGP1WID(M_AXI_GP1_WID),
.MAXIGP1WLAST(M_AXI_GP1_WLAST),
.MAXIGP1WREADY(M_AXI_GP1_WREADY),
.MAXIGP1WSTRB(M_AXI_GP1_WSTRB),
.MAXIGP1WVALID(M_AXI_GP1_WVALID),
.MIO(buffered_MIO),
.PSCLK(buffered_PS_CLK),
.PSPORB(buffered_PS_PORB),
.PSSRSTB(buffered_PS_SRSTB),
.SAXIACPACLK(S_AXI_ACP_ACLK),
.SAXIACPARADDR(S_AXI_ACP_ARADDR),
.SAXIACPARBURST(S_AXI_ACP_ARBURST),
.SAXIACPARCACHE(S_AXI_ACP_ARCACHE),
.SAXIACPARESETN(S_AXI_ACP_ARESETN),
.SAXIACPARID(S_AXI_ACP_ARID),
.SAXIACPARLEN(S_AXI_ACP_ARLEN),
.SAXIACPARLOCK(S_AXI_ACP_ARLOCK),
.SAXIACPARPROT(S_AXI_ACP_ARPROT),
.SAXIACPARQOS(S_AXI_ACP_ARQOS),
.SAXIACPARREADY(S_AXI_ACP_ARREADY),
.SAXIACPARSIZE(S_AXI_ACP_ARSIZE[1:0]),
.SAXIACPARUSER(S_AXI_ACP_ARUSER),
.SAXIACPARVALID(S_AXI_ACP_ARVALID),
.SAXIACPAWADDR(S_AXI_ACP_AWADDR),
.SAXIACPAWBURST(S_AXI_ACP_AWBURST),
.SAXIACPAWCACHE(S_AXI_ACP_AWCACHE),
.SAXIACPAWID(S_AXI_ACP_AWID),
.SAXIACPAWLEN(S_AXI_ACP_AWLEN),
.SAXIACPAWLOCK(S_AXI_ACP_AWLOCK),
.SAXIACPAWPROT(S_AXI_ACP_AWPROT),
.SAXIACPAWQOS(S_AXI_ACP_AWQOS),
.SAXIACPAWREADY(S_AXI_ACP_AWREADY),
.SAXIACPAWSIZE(S_AXI_ACP_AWSIZE[1:0]),
.SAXIACPAWUSER(S_AXI_ACP_AWUSER),
.SAXIACPAWVALID(S_AXI_ACP_AWVALID),
.SAXIACPBID(S_AXI_ACP_BID),
.SAXIACPBREADY(S_AXI_ACP_BREADY),
.SAXIACPBRESP(S_AXI_ACP_BRESP),
.SAXIACPBVALID(S_AXI_ACP_BVALID),
.SAXIACPRDATA(S_AXI_ACP_RDATA),
.SAXIACPRID(S_AXI_ACP_RID),
.SAXIACPRLAST(S_AXI_ACP_RLAST),
.SAXIACPRREADY(S_AXI_ACP_RREADY),
.SAXIACPRRESP(S_AXI_ACP_RRESP),
.SAXIACPRVALID(S_AXI_ACP_RVALID),
.SAXIACPWDATA(S_AXI_ACP_WDATA),
.SAXIACPWID(S_AXI_ACP_WID),
.SAXIACPWLAST(S_AXI_ACP_WLAST),
.SAXIACPWREADY(S_AXI_ACP_WREADY),
.SAXIACPWSTRB(S_AXI_ACP_WSTRB),
.SAXIACPWVALID(S_AXI_ACP_WVALID),
.SAXIGP0ACLK(S_AXI_GP0_ACLK),
.SAXIGP0ARADDR(S_AXI_GP0_ARADDR),
.SAXIGP0ARBURST(S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE(S_AXI_GP0_ARCACHE),
.SAXIGP0ARESETN(S_AXI_GP0_ARESETN),
.SAXIGP0ARID(S_AXI_GP0_ARID),
.SAXIGP0ARLEN(S_AXI_GP0_ARLEN),
.SAXIGP0ARLOCK(S_AXI_GP0_ARLOCK),
.SAXIGP0ARPROT(S_AXI_GP0_ARPROT),
.SAXIGP0ARQOS(S_AXI_GP0_ARQOS),
.SAXIGP0ARREADY(S_AXI_GP0_ARREADY),
.SAXIGP0ARSIZE(S_AXI_GP0_ARSIZE[1:0]),
.SAXIGP0ARVALID(S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR(S_AXI_GP0_AWADDR),
.SAXIGP0AWBURST(S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE(S_AXI_GP0_AWCACHE),
.SAXIGP0AWID(S_AXI_GP0_AWID),
.SAXIGP0AWLEN(S_AXI_GP0_AWLEN),
.SAXIGP0AWLOCK(S_AXI_GP0_AWLOCK),
.SAXIGP0AWPROT(S_AXI_GP0_AWPROT),
.SAXIGP0AWQOS(S_AXI_GP0_AWQOS),
.SAXIGP0AWREADY(S_AXI_GP0_AWREADY),
.SAXIGP0AWSIZE(S_AXI_GP0_AWSIZE[1:0]),
.SAXIGP0AWVALID(S_AXI_GP0_AWVALID),
.SAXIGP0BID(S_AXI_GP0_BID),
.SAXIGP0BREADY(S_AXI_GP0_BREADY),
.SAXIGP0BRESP(S_AXI_GP0_BRESP),
.SAXIGP0BVALID(S_AXI_GP0_BVALID),
.SAXIGP0RDATA(S_AXI_GP0_RDATA),
.SAXIGP0RID(S_AXI_GP0_RID),
.SAXIGP0RLAST(S_AXI_GP0_RLAST),
.SAXIGP0RREADY(S_AXI_GP0_RREADY),
.SAXIGP0RRESP(S_AXI_GP0_RRESP),
.SAXIGP0RVALID(S_AXI_GP0_RVALID),
.SAXIGP0WDATA(S_AXI_GP0_WDATA),
.SAXIGP0WID(S_AXI_GP0_WID),
.SAXIGP0WLAST(S_AXI_GP0_WLAST),
.SAXIGP0WREADY(S_AXI_GP0_WREADY),
.SAXIGP0WSTRB(S_AXI_GP0_WSTRB),
.SAXIGP0WVALID(S_AXI_GP0_WVALID),
.SAXIGP1ACLK(S_AXI_GP1_ACLK),
.SAXIGP1ARADDR(S_AXI_GP1_ARADDR),
.SAXIGP1ARBURST(S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE(S_AXI_GP1_ARCACHE),
.SAXIGP1ARESETN(S_AXI_GP1_ARESETN),
.SAXIGP1ARID(S_AXI_GP1_ARID),
.SAXIGP1ARLEN(S_AXI_GP1_ARLEN),
.SAXIGP1ARLOCK(S_AXI_GP1_ARLOCK),
.SAXIGP1ARPROT(S_AXI_GP1_ARPROT),
.SAXIGP1ARQOS(S_AXI_GP1_ARQOS),
.SAXIGP1ARREADY(S_AXI_GP1_ARREADY),
.SAXIGP1ARSIZE(S_AXI_GP1_ARSIZE[1:0]),
.SAXIGP1ARVALID(S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR(S_AXI_GP1_AWADDR),
.SAXIGP1AWBURST(S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE(S_AXI_GP1_AWCACHE),
.SAXIGP1AWID(S_AXI_GP1_AWID),
.SAXIGP1AWLEN(S_AXI_GP1_AWLEN),
.SAXIGP1AWLOCK(S_AXI_GP1_AWLOCK),
.SAXIGP1AWPROT(S_AXI_GP1_AWPROT),
.SAXIGP1AWQOS(S_AXI_GP1_AWQOS),
.SAXIGP1AWREADY(S_AXI_GP1_AWREADY),
.SAXIGP1AWSIZE(S_AXI_GP1_AWSIZE[1:0]),
.SAXIGP1AWVALID(S_AXI_GP1_AWVALID),
.SAXIGP1BID(S_AXI_GP1_BID),
.SAXIGP1BREADY(S_AXI_GP1_BREADY),
.SAXIGP1BRESP(S_AXI_GP1_BRESP),
.SAXIGP1BVALID(S_AXI_GP1_BVALID),
.SAXIGP1RDATA(S_AXI_GP1_RDATA),
.SAXIGP1RID(S_AXI_GP1_RID),
.SAXIGP1RLAST(S_AXI_GP1_RLAST),
.SAXIGP1RREADY(S_AXI_GP1_RREADY),
.SAXIGP1RRESP(S_AXI_GP1_RRESP),
.SAXIGP1RVALID(S_AXI_GP1_RVALID),
.SAXIGP1WDATA(S_AXI_GP1_WDATA),
.SAXIGP1WID(S_AXI_GP1_WID),
.SAXIGP1WLAST(S_AXI_GP1_WLAST),
.SAXIGP1WREADY(S_AXI_GP1_WREADY),
.SAXIGP1WSTRB(S_AXI_GP1_WSTRB),
.SAXIGP1WVALID(S_AXI_GP1_WVALID),
.SAXIHP0ACLK(S_AXI_HP0_ACLK),
.SAXIHP0ARADDR(S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST(S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE(S_AXI_HP0_ARCACHE),
.SAXIHP0ARESETN(S_AXI_HP0_ARESETN),
.SAXIHP0ARID(S_AXI_HP0_ARID),
.SAXIHP0ARLEN(S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK(S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT(S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS(S_AXI_HP0_ARQOS),
.SAXIHP0ARREADY(S_AXI_HP0_ARREADY),
.SAXIHP0ARSIZE(S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID(S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR(S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST(S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE(S_AXI_HP0_AWCACHE),
.SAXIHP0AWID(S_AXI_HP0_AWID),
.SAXIHP0AWLEN(S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK(S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT(S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS(S_AXI_HP0_AWQOS),
.SAXIHP0AWREADY(S_AXI_HP0_AWREADY),
.SAXIHP0AWSIZE(S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID(S_AXI_HP0_AWVALID),
.SAXIHP0BID(S_AXI_HP0_BID),
.SAXIHP0BREADY(S_AXI_HP0_BREADY),
.SAXIHP0BRESP(S_AXI_HP0_BRESP),
.SAXIHP0BVALID(S_AXI_HP0_BVALID),
.SAXIHP0RACOUNT(S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT(S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA(S_AXI_HP0_RDATA),
.SAXIHP0RDISSUECAP1EN(S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RID(S_AXI_HP0_RID),
.SAXIHP0RLAST(S_AXI_HP0_RLAST),
.SAXIHP0RREADY(S_AXI_HP0_RREADY),
.SAXIHP0RRESP(S_AXI_HP0_RRESP),
.SAXIHP0RVALID(S_AXI_HP0_RVALID),
.SAXIHP0WACOUNT(S_AXI_HP0_WACOUNT),
.SAXIHP0WCOUNT(S_AXI_HP0_WCOUNT),
.SAXIHP0WDATA(S_AXI_HP0_WDATA),
.SAXIHP0WID(S_AXI_HP0_WID),
.SAXIHP0WLAST(S_AXI_HP0_WLAST),
.SAXIHP0WREADY(S_AXI_HP0_WREADY),
.SAXIHP0WRISSUECAP1EN(S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB(S_AXI_HP0_WSTRB),
.SAXIHP0WVALID(S_AXI_HP0_WVALID),
.SAXIHP1ACLK(S_AXI_HP1_ACLK),
.SAXIHP1ARADDR(S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST(S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE(S_AXI_HP1_ARCACHE),
.SAXIHP1ARESETN(S_AXI_HP1_ARESETN),
.SAXIHP1ARID(S_AXI_HP1_ARID),
.SAXIHP1ARLEN(S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK(S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT(S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS(S_AXI_HP1_ARQOS),
.SAXIHP1ARREADY(S_AXI_HP1_ARREADY),
.SAXIHP1ARSIZE(S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID(S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR(S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST(S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE(S_AXI_HP1_AWCACHE),
.SAXIHP1AWID(S_AXI_HP1_AWID),
.SAXIHP1AWLEN(S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK(S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT(S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS(S_AXI_HP1_AWQOS),
.SAXIHP1AWREADY(S_AXI_HP1_AWREADY),
.SAXIHP1AWSIZE(S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID(S_AXI_HP1_AWVALID),
.SAXIHP1BID(S_AXI_HP1_BID),
.SAXIHP1BREADY(S_AXI_HP1_BREADY),
.SAXIHP1BRESP(S_AXI_HP1_BRESP),
.SAXIHP1BVALID(S_AXI_HP1_BVALID),
.SAXIHP1RACOUNT(S_AXI_HP1_RACOUNT),
.SAXIHP1RCOUNT(S_AXI_HP1_RCOUNT),
.SAXIHP1RDATA(S_AXI_HP1_RDATA),
.SAXIHP1RDISSUECAP1EN(S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RID(S_AXI_HP1_RID),
.SAXIHP1RLAST(S_AXI_HP1_RLAST),
.SAXIHP1RREADY(S_AXI_HP1_RREADY),
.SAXIHP1RRESP(S_AXI_HP1_RRESP),
.SAXIHP1RVALID(S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT(S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT(S_AXI_HP1_WCOUNT),
.SAXIHP1WDATA(S_AXI_HP1_WDATA),
.SAXIHP1WID(S_AXI_HP1_WID),
.SAXIHP1WLAST(S_AXI_HP1_WLAST),
.SAXIHP1WREADY(S_AXI_HP1_WREADY),
.SAXIHP1WRISSUECAP1EN(S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB(S_AXI_HP1_WSTRB),
.SAXIHP1WVALID(S_AXI_HP1_WVALID),
.SAXIHP2ACLK(S_AXI_HP2_ACLK),
.SAXIHP2ARADDR(S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST(S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE(S_AXI_HP2_ARCACHE),
.SAXIHP2ARESETN(S_AXI_HP2_ARESETN),
.SAXIHP2ARID(S_AXI_HP2_ARID),
.SAXIHP2ARLEN(S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK(S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT(S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS(S_AXI_HP2_ARQOS),
.SAXIHP2ARREADY(S_AXI_HP2_ARREADY),
.SAXIHP2ARSIZE(S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID(S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR(S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST(S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE(S_AXI_HP2_AWCACHE),
.SAXIHP2AWID(S_AXI_HP2_AWID),
.SAXIHP2AWLEN(S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK(S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT(S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS(S_AXI_HP2_AWQOS),
.SAXIHP2AWREADY(S_AXI_HP2_AWREADY),
.SAXIHP2AWSIZE(S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID(S_AXI_HP2_AWVALID),
.SAXIHP2BID(S_AXI_HP2_BID),
.SAXIHP2BREADY(S_AXI_HP2_BREADY),
.SAXIHP2BRESP(S_AXI_HP2_BRESP),
.SAXIHP2BVALID(S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT(S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT(S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA(S_AXI_HP2_RDATA),
.SAXIHP2RDISSUECAP1EN(S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RID(S_AXI_HP2_RID),
.SAXIHP2RLAST(S_AXI_HP2_RLAST),
.SAXIHP2RREADY(S_AXI_HP2_RREADY),
.SAXIHP2RRESP(S_AXI_HP2_RRESP),
.SAXIHP2RVALID(S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT(S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT(S_AXI_HP2_WCOUNT),
.SAXIHP2WDATA(S_AXI_HP2_WDATA),
.SAXIHP2WID(S_AXI_HP2_WID),
.SAXIHP2WLAST(S_AXI_HP2_WLAST),
.SAXIHP2WREADY(S_AXI_HP2_WREADY),
.SAXIHP2WRISSUECAP1EN(S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB(S_AXI_HP2_WSTRB),
.SAXIHP2WVALID(S_AXI_HP2_WVALID),
.SAXIHP3ACLK(S_AXI_HP3_ACLK),
.SAXIHP3ARADDR(S_AXI_HP3_ARADDR),
.SAXIHP3ARBURST(S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE(S_AXI_HP3_ARCACHE),
.SAXIHP3ARESETN(S_AXI_HP3_ARESETN),
.SAXIHP3ARID(S_AXI_HP3_ARID),
.SAXIHP3ARLEN(S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK(S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT(S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS(S_AXI_HP3_ARQOS),
.SAXIHP3ARREADY(S_AXI_HP3_ARREADY),
.SAXIHP3ARSIZE(S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID(S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR(S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST(S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE(S_AXI_HP3_AWCACHE),
.SAXIHP3AWID(S_AXI_HP3_AWID),
.SAXIHP3AWLEN(S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK(S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT(S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS(S_AXI_HP3_AWQOS),
.SAXIHP3AWREADY(S_AXI_HP3_AWREADY),
.SAXIHP3AWSIZE(S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID(S_AXI_HP3_AWVALID),
.SAXIHP3BID(S_AXI_HP3_BID),
.SAXIHP3BREADY(S_AXI_HP3_BREADY),
.SAXIHP3BRESP(S_AXI_HP3_BRESP),
.SAXIHP3BVALID(S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT(S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT(S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA(S_AXI_HP3_RDATA),
.SAXIHP3RDISSUECAP1EN(S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RID(S_AXI_HP3_RID),
.SAXIHP3RLAST(S_AXI_HP3_RLAST),
.SAXIHP3RREADY(S_AXI_HP3_RREADY),
.SAXIHP3RRESP(S_AXI_HP3_RRESP),
.SAXIHP3RVALID(S_AXI_HP3_RVALID),
.SAXIHP3WACOUNT(S_AXI_HP3_WACOUNT),
.SAXIHP3WCOUNT(S_AXI_HP3_WCOUNT),
.SAXIHP3WDATA(S_AXI_HP3_WDATA),
.SAXIHP3WID(S_AXI_HP3_WID),
.SAXIHP3WLAST(S_AXI_HP3_WLAST),
.SAXIHP3WREADY(S_AXI_HP3_WREADY),
.SAXIHP3WRISSUECAP1EN(S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB(S_AXI_HP3_WSTRB),
.SAXIHP3WVALID(S_AXI_HP3_WVALID));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_CLK_BIBUF
(.IO(buffered_PS_CLK),
.PAD(PS_CLK));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_PORB_BIBUF
(.IO(buffered_PS_PORB),
.PAD(PS_PORB));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_SRSTB_BIBUF
(.IO(buffered_PS_SRSTB),
.PAD(PS_SRSTB));
LUT1 #(
.INIT(2'h1))
SDIO0_CMD_T_INST_0
(.I0(SDIO0_CMD_T_n),
.O(SDIO0_CMD_T));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[0]_INST_0
(.I0(SDIO0_DATA_T_n[0]),
.O(SDIO0_DATA_T[0]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[1]_INST_0
(.I0(SDIO0_DATA_T_n[1]),
.O(SDIO0_DATA_T[1]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[2]_INST_0
(.I0(SDIO0_DATA_T_n[2]),
.O(SDIO0_DATA_T[2]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[3]_INST_0
(.I0(SDIO0_DATA_T_n[3]),
.O(SDIO0_DATA_T[3]));
LUT1 #(
.INIT(2'h1))
SDIO1_CMD_T_INST_0
(.I0(SDIO1_CMD_T_n),
.O(SDIO1_CMD_T));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[0]_INST_0
(.I0(SDIO1_DATA_T_n[0]),
.O(SDIO1_DATA_T[0]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[1]_INST_0
(.I0(SDIO1_DATA_T_n[1]),
.O(SDIO1_DATA_T[1]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[2]_INST_0
(.I0(SDIO1_DATA_T_n[2]),
.O(SDIO1_DATA_T[2]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[3]_INST_0
(.I0(SDIO1_DATA_T_n[3]),
.O(SDIO1_DATA_T[3]));
LUT1 #(
.INIT(2'h1))
SPI0_MISO_T_INST_0
(.I0(SPI0_MISO_T_n),
.O(SPI0_MISO_T));
LUT1 #(
.INIT(2'h1))
SPI0_MOSI_T_INST_0
(.I0(SPI0_MOSI_T_n),
.O(SPI0_MOSI_T));
LUT1 #(
.INIT(2'h1))
SPI0_SCLK_T_INST_0
(.I0(SPI0_SCLK_T_n),
.O(SPI0_SCLK_T));
LUT1 #(
.INIT(2'h1))
SPI0_SS_T_INST_0
(.I0(SPI0_SS_T_n),
.O(SPI0_SS_T));
LUT1 #(
.INIT(2'h1))
SPI1_MISO_T_INST_0
(.I0(SPI1_MISO_T_n),
.O(SPI1_MISO_T));
LUT1 #(
.INIT(2'h1))
SPI1_MOSI_T_INST_0
(.I0(SPI1_MOSI_T_n),
.O(SPI1_MOSI_T));
LUT1 #(
.INIT(2'h1))
SPI1_SCLK_T_INST_0
(.I0(SPI1_SCLK_T_n),
.O(SPI1_SCLK_T));
LUT1 #(
.INIT(2'h1))
SPI1_SS_T_INST_0
(.I0(SPI1_SS_T_n),
.O(SPI1_SS_T));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG \buffer_fclk_clk_0.FCLK_CLK_0_BUFG
(.I(FCLK_CLK_unbuffered),
.O(FCLK_CLK0));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[0].MIO_BIBUF
(.IO(buffered_MIO[0]),
.PAD(MIO[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[10].MIO_BIBUF
(.IO(buffered_MIO[10]),
.PAD(MIO[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[11].MIO_BIBUF
(.IO(buffered_MIO[11]),
.PAD(MIO[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[12].MIO_BIBUF
(.IO(buffered_MIO[12]),
.PAD(MIO[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[13].MIO_BIBUF
(.IO(buffered_MIO[13]),
.PAD(MIO[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[14].MIO_BIBUF
(.IO(buffered_MIO[14]),
.PAD(MIO[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[15].MIO_BIBUF
(.IO(buffered_MIO[15]),
.PAD(MIO[15]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[16].MIO_BIBUF
(.IO(buffered_MIO[16]),
.PAD(MIO[16]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[17].MIO_BIBUF
(.IO(buffered_MIO[17]),
.PAD(MIO[17]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[18].MIO_BIBUF
(.IO(buffered_MIO[18]),
.PAD(MIO[18]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[19].MIO_BIBUF
(.IO(buffered_MIO[19]),
.PAD(MIO[19]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[1].MIO_BIBUF
(.IO(buffered_MIO[1]),
.PAD(MIO[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[20].MIO_BIBUF
(.IO(buffered_MIO[20]),
.PAD(MIO[20]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[21].MIO_BIBUF
(.IO(buffered_MIO[21]),
.PAD(MIO[21]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[22].MIO_BIBUF
(.IO(buffered_MIO[22]),
.PAD(MIO[22]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[23].MIO_BIBUF
(.IO(buffered_MIO[23]),
.PAD(MIO[23]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[24].MIO_BIBUF
(.IO(buffered_MIO[24]),
.PAD(MIO[24]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[25].MIO_BIBUF
(.IO(buffered_MIO[25]),
.PAD(MIO[25]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[26].MIO_BIBUF
(.IO(buffered_MIO[26]),
.PAD(MIO[26]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[27].MIO_BIBUF
(.IO(buffered_MIO[27]),
.PAD(MIO[27]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[28].MIO_BIBUF
(.IO(buffered_MIO[28]),
.PAD(MIO[28]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[29].MIO_BIBUF
(.IO(buffered_MIO[29]),
.PAD(MIO[29]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[2].MIO_BIBUF
(.IO(buffered_MIO[2]),
.PAD(MIO[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[30].MIO_BIBUF
(.IO(buffered_MIO[30]),
.PAD(MIO[30]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[31].MIO_BIBUF
(.IO(buffered_MIO[31]),
.PAD(MIO[31]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[32].MIO_BIBUF
(.IO(buffered_MIO[32]),
.PAD(MIO[32]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[33].MIO_BIBUF
(.IO(buffered_MIO[33]),
.PAD(MIO[33]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[34].MIO_BIBUF
(.IO(buffered_MIO[34]),
.PAD(MIO[34]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[35].MIO_BIBUF
(.IO(buffered_MIO[35]),
.PAD(MIO[35]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[36].MIO_BIBUF
(.IO(buffered_MIO[36]),
.PAD(MIO[36]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[37].MIO_BIBUF
(.IO(buffered_MIO[37]),
.PAD(MIO[37]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[38].MIO_BIBUF
(.IO(buffered_MIO[38]),
.PAD(MIO[38]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[39].MIO_BIBUF
(.IO(buffered_MIO[39]),
.PAD(MIO[39]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[3].MIO_BIBUF
(.IO(buffered_MIO[3]),
.PAD(MIO[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[40].MIO_BIBUF
(.IO(buffered_MIO[40]),
.PAD(MIO[40]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[41].MIO_BIBUF
(.IO(buffered_MIO[41]),
.PAD(MIO[41]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[42].MIO_BIBUF
(.IO(buffered_MIO[42]),
.PAD(MIO[42]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[43].MIO_BIBUF
(.IO(buffered_MIO[43]),
.PAD(MIO[43]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[44].MIO_BIBUF
(.IO(buffered_MIO[44]),
.PAD(MIO[44]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[45].MIO_BIBUF
(.IO(buffered_MIO[45]),
.PAD(MIO[45]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[46].MIO_BIBUF
(.IO(buffered_MIO[46]),
.PAD(MIO[46]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[47].MIO_BIBUF
(.IO(buffered_MIO[47]),
.PAD(MIO[47]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[48].MIO_BIBUF
(.IO(buffered_MIO[48]),
.PAD(MIO[48]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[49].MIO_BIBUF
(.IO(buffered_MIO[49]),
.PAD(MIO[49]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[4].MIO_BIBUF
(.IO(buffered_MIO[4]),
.PAD(MIO[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[50].MIO_BIBUF
(.IO(buffered_MIO[50]),
.PAD(MIO[50]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[51].MIO_BIBUF
(.IO(buffered_MIO[51]),
.PAD(MIO[51]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[52].MIO_BIBUF
(.IO(buffered_MIO[52]),
.PAD(MIO[52]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[53].MIO_BIBUF
(.IO(buffered_MIO[53]),
.PAD(MIO[53]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[5].MIO_BIBUF
(.IO(buffered_MIO[5]),
.PAD(MIO[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[6].MIO_BIBUF
(.IO(buffered_MIO[6]),
.PAD(MIO[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[7].MIO_BIBUF
(.IO(buffered_MIO[7]),
.PAD(MIO[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[8].MIO_BIBUF
(.IO(buffered_MIO[8]),
.PAD(MIO[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[9].MIO_BIBUF
(.IO(buffered_MIO[9]),
.PAD(MIO[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[0].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[0]),
.PAD(DDR_BankAddr[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[1].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[1]),
.PAD(DDR_BankAddr[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[2].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[2]),
.PAD(DDR_BankAddr[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[0].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[0]),
.PAD(DDR_Addr[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[10].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[10]),
.PAD(DDR_Addr[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[11].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[11]),
.PAD(DDR_Addr[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[12].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[12]),
.PAD(DDR_Addr[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[13].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[13]),
.PAD(DDR_Addr[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[14].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[14]),
.PAD(DDR_Addr[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[1].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[1]),
.PAD(DDR_Addr[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[2].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[2]),
.PAD(DDR_Addr[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[3].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[3]),
.PAD(DDR_Addr[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[4].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[4]),
.PAD(DDR_Addr[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[5].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[5]),
.PAD(DDR_Addr[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[6].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[6]),
.PAD(DDR_Addr[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[7].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[7]),
.PAD(DDR_Addr[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[8].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[8]),
.PAD(DDR_Addr[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[9].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[9]),
.PAD(DDR_Addr[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[0].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[0]),
.PAD(DDR_DM[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[1].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[1]),
.PAD(DDR_DM[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[2].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[2]),
.PAD(DDR_DM[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[3].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[3]),
.PAD(DDR_DM[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[0].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[0]),
.PAD(DDR_DQ[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[10].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[10]),
.PAD(DDR_DQ[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[11].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[11]),
.PAD(DDR_DQ[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[12].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[12]),
.PAD(DDR_DQ[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[13].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[13]),
.PAD(DDR_DQ[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[14].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[14]),
.PAD(DDR_DQ[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[15].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[15]),
.PAD(DDR_DQ[15]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[16].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[16]),
.PAD(DDR_DQ[16]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[17].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[17]),
.PAD(DDR_DQ[17]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[18].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[18]),
.PAD(DDR_DQ[18]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[19].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[19]),
.PAD(DDR_DQ[19]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[1].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[1]),
.PAD(DDR_DQ[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[20].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[20]),
.PAD(DDR_DQ[20]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[21].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[21]),
.PAD(DDR_DQ[21]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[22].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[22]),
.PAD(DDR_DQ[22]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[23].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[23]),
.PAD(DDR_DQ[23]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[24].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[24]),
.PAD(DDR_DQ[24]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[25].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[25]),
.PAD(DDR_DQ[25]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[26].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[26]),
.PAD(DDR_DQ[26]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[27].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[27]),
.PAD(DDR_DQ[27]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[28].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[28]),
.PAD(DDR_DQ[28]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[29].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[29]),
.PAD(DDR_DQ[29]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[2].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[2]),
.PAD(DDR_DQ[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[30].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[30]),
.PAD(DDR_DQ[30]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[31].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[31]),
.PAD(DDR_DQ[31]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[3].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[3]),
.PAD(DDR_DQ[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[4].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[4]),
.PAD(DDR_DQ[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[5].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[5]),
.PAD(DDR_DQ[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[6].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[6]),
.PAD(DDR_DQ[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[7].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[7]),
.PAD(DDR_DQ[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[8].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[8]),
.PAD(DDR_DQ[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[9].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[9]),
.PAD(DDR_DQ[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[0].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[0]),
.PAD(DDR_DQS_n[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[1].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[1]),
.PAD(DDR_DQS_n[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[2].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[2]),
.PAD(DDR_DQS_n[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[3].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[3]),
.PAD(DDR_DQS_n[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[0].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[0]),
.PAD(DDR_DQS[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[1].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[1]),
.PAD(DDR_DQS[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[2].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[2]),
.PAD(DDR_DQS[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[3].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[3]),
.PAD(DDR_DQS[3]));
LUT1 #(
.INIT(2'h2))
i_0
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[0] ));
LUT1 #(
.INIT(2'h2))
i_1
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[0] [1]));
LUT1 #(
.INIT(2'h2))
i_10
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[7] [1]));
LUT1 #(
.INIT(2'h2))
i_11
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[7] [0]));
LUT1 #(
.INIT(2'h2))
i_12
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[6] [1]));
LUT1 #(
.INIT(2'h2))
i_13
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[6] [0]));
LUT1 #(
.INIT(2'h2))
i_14
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[5] [1]));
LUT1 #(
.INIT(2'h2))
i_15
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[5] [0]));
LUT1 #(
.INIT(2'h2))
i_16
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[4] [1]));
LUT1 #(
.INIT(2'h2))
i_17
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[4] [0]));
LUT1 #(
.INIT(2'h2))
i_18
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[3] [1]));
LUT1 #(
.INIT(2'h2))
i_19
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[3] [0]));
LUT1 #(
.INIT(2'h2))
i_2
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[0] [0]));
LUT1 #(
.INIT(2'h2))
i_20
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[2] [1]));
LUT1 #(
.INIT(2'h2))
i_21
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[2] [0]));
LUT1 #(
.INIT(2'h2))
i_22
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[1] [1]));
LUT1 #(
.INIT(2'h2))
i_23
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[1] [0]));
LUT1 #(
.INIT(2'h2))
i_3
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[7] ));
LUT1 #(
.INIT(2'h2))
i_4
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[6] ));
LUT1 #(
.INIT(2'h2))
i_5
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[5] ));
LUT1 #(
.INIT(2'h2))
i_6
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[4] ));
LUT1 #(
.INIT(2'h2))
i_7
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[3] ));
LUT1 #(
.INIT(2'h2))
i_8
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[2] ));
LUT1 #(
.INIT(2'h2))
i_9
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[1] ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
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