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/*
# Ilkka Hautala
# [email protected]
# Center for Machine Vision and Signal Analysis (CMVS)
# University of Oulu, Finland
SystemC implementation of Memory arbiter
Based on VHDL implementation of avalon mem arbiter authored by AK (TCE project)
*/
#ifndef TTA_MEM_ARBITER_H_
#define TTA_MEM_ARBITER_H_
#include <systemc.h>
template<int ports_g, int addrw_g, int dataw_g, int memLen>
SC_MODULE(tta_mem_arbiter)
{
/*MODULE INPUT INTERFACE */
sc_in<bool> clk;
sc_in<bool> rst_n;
sc_in<sc_bv<dataw_g/8> > bit_wr_x[ports_g];
sc_in<bool> en_x[ports_g];
sc_in<bool> wr_x[ports_g];
sc_in<sc_bv<dataw_g> > d[ports_g];
sc_in<sc_bv<addrw_g> > addr[ports_g];
/*MODULE OUTPUT INTERFACE */
sc_out<sc_bv<dataw_g> > q[ports_g];
sc_out<bool> waitrequest[ports_g];
/*RAM MODULE INTERFACE SIGNALS*/
sc_out<bool> ram_en_x;
sc_out<bool> ram_wr_x;
sc_out<sc_bv<dataw_g> > ram_d;
sc_in<sc_bv<dataw_g> > ram_q;
sc_out<sc_bv<dataw_g/8> > ram_bit_wr_x;
sc_out<sc_bv<addrw_g> > ram_addr;
/*MODULE INTERNAL SIGNALS */
sc_signal<bool> input_latch_load;
sc_signal<bool> latch_en_x[ports_g], latch_en_x_r[ports_g];
sc_signal<bool> latch_wr_x[ports_g], latch_wr_x_r[ports_g];
sc_signal<sc_bv<dataw_g/8> > latch_bit_wr_x[ports_g];
sc_signal<sc_bv<dataw_g/8> > latch_bit_wr_x_r[ports_g];
sc_signal<sc_bv<dataw_g> > latch_d[ports_g];
sc_signal<sc_bv<dataw_g> > latch_d_r[ports_g];
sc_signal<sc_bv<addrw_g> > latch_addr[ports_g];
sc_signal<sc_bv<addrw_g> > latch_addr_r[ports_g];
sc_signal<bool> output_latch_load;
sc_signal<sc_bv<dataw_g> > q_v[ports_g];
sc_signal<sc_bv<dataw_g> > q_v_r[ports_g];
sc_signal<int> selected_port;
sc_signal<bool> selected_port_mask_x[ports_g];
sc_signal<bool> selected_port_mask_x_r[ports_g];
sc_signal<bool> wait_rq_r_in [ports_g];
sc_signal<bool> wait_rq_r [ports_g];
int pointer;
void priority_encoder(){
ram_en_x = true;
selected_port = 0;
int i;
for(i=0; i<ports_g; i++){
selected_port_mask_x[i] = true;
}
for(i=0; i<ports_g; i++){
if(latch_en_x[i] == false){
ram_en_x = false;
selected_port = i;
selected_port_mask_x[i] = false;
//cout << "selected_port " << pointer << "\n";
//pointer = (pointer + 1)%ports_g;
break;
}
//pointer = (pointer + 1)%ports_g;
}
}
void regs(){
int i;
if(rst_n == false){
for(i=0; i<ports_g; i++){
wait_rq_r[i] = false;
selected_port_mask_x_r[i] = true;
}
}
else if(clk.posedge()){
for(i=0; i<ports_g; i++){
wait_rq_r[i] = wait_rq_r_in[i];
selected_port_mask_x_r[i] = selected_port_mask_x[i];
}
}
}
void input_latch_seq(){
int i;
if(rst_n == false){
for(i=0; i<ports_g; i++){
latch_en_x_r[i] = true;
latch_wr_x_r[i] = true;
latch_d_r[i] = 0;
latch_bit_wr_x_r[i] = -1;
latch_addr_r[i] = 0;
}
}
else if(clk.posedge()){
for(i=0; i<ports_g; i++){
//cout << " wait_rq_r_in " << wait_rq_r_in[i] << " : wait_rq_r " << wait_rq_r[i] << "\n";
if(wait_rq_r_in[i] == true && wait_rq_r[i] == false){
//cout << "hello\n";
latch_en_x_r[i] = en_x[i].read();
latch_wr_x_r[i] = wr_x[i].read();
latch_d_r[i] = d[i].read();
latch_bit_wr_x_r[i] = bit_wr_x[i].read();
latch_addr_r[i] = addr[i].read();
}
}
}
}
void input_latch_comb(){
int i;
for(i=0; i<ports_g; i++){
if(wait_rq_r[i] == true){
latch_en_x[i] = latch_en_x_r[i];
latch_wr_x[i] = latch_wr_x_r[i];
latch_d[i] = latch_d_r[i];
latch_bit_wr_x[i] = latch_bit_wr_x_r[i];
latch_addr[i] = latch_addr_r[i];
}
else{
latch_en_x[i] = en_x[i];
latch_wr_x[i] = wr_x[i];
latch_d[i] = d[i].read();
latch_bit_wr_x[i] = bit_wr_x[i].read();
latch_addr[i] = addr[i].read();
}
}
}
void output_latch_seq(){
int i;
if(rst_n == false){
for(i=0; i<ports_g; i++){
q_v_r[i] = 0;
}
}
else if(clk.posedge()){
for(i=0; i<ports_g; i++){
if( selected_port_mask_x_r[i] == false){
q_v_r[i] = ram_q;
}
}
}
}
void output_latch_comb(){
int i;
for(i=0; i<ports_g; i++){
if( selected_port_mask_x_r[i] == false){
q_v[i] = ram_q;
}
else{
q_v[i] = q_v_r[i];
}
}
}
void pack(){
int i;
for(i=0; i<ports_g; i++){
q[i].write(q_v[i].read());
}
}
void wires(){
ram_wr_x = latch_wr_x[selected_port];
ram_d = latch_d[selected_port];
ram_bit_wr_x = latch_bit_wr_x[selected_port];
ram_addr = latch_addr[selected_port];
int i;
for(i=0; i<ports_g; i++){
//cout << "latch_en_x_ " <<i << " : " << latch_en_x[i].read()<< "\n" ;
//cout << " selected_port_mask_x_" << i << " : " << selected_port_mask_x[i]<< "\n";
wait_rq_r_in[i].write( (latch_en_x[i] + selected_port_mask_x[i])%2); //XOR
waitrequest[i] = wait_rq_r[i];
//cout << " wait_rq_r_in_" << i << " : " << (latch_en_x[i] + selected_port_mask_x[i])%2 << "\n";
}
}
SC_CTOR(tta_mem_arbiter)
{
int i;
cout << "Constructing Memory arbiter " << name() << endl;
SC_METHOD(wires);
for(i=0; i<ports_g;i++){
sensitive << wait_rq_r[i] << latch_en_x[i] << latch_d[i] << latch_bit_wr_x[i] << latch_addr[i] << latch_wr_x[i] << selected_port_mask_x[i] << selected_port;
}
SC_METHOD(priority_encoder);
for(i=0; i<ports_g;i++){
sensitive << latch_en_x[i] << clk.pos();
}
SC_METHOD(regs);
sensitive << clk.pos() << rst_n.neg();
SC_METHOD(input_latch_seq);
sensitive << clk.pos() << rst_n.neg();
SC_METHOD(input_latch_comb);
for(i=0; i<ports_g;i++){
sensitive << wait_rq_r[i] << latch_en_x_r[i] << latch_d_r[i] << latch_bit_wr_x_r[i] << latch_addr_r[i] << en_x[i] << bit_wr_x[i] << d[i] << addr[i] << wr_x[i] << latch_wr_x_r[i];
}
SC_METHOD(output_latch_seq);
sensitive << clk.pos() << rst_n.neg();
SC_METHOD(output_latch_comb);
sensitive << ram_q;
for(i=0; i<ports_g;i++){
sensitive << q_v_r[i] << selected_port_mask_x_r[i];
}
SC_METHOD(pack);
for(i=0; i<ports_g;i++){
sensitive << q_v[i];
}
pointer = 0;
//RESET
for(i=0; i<ports_g; i++){
wait_rq_r[i] = false;
selected_port_mask_x_r[i] = true;
latch_en_x_r[i] = true;
latch_wr_x_r[i] = true;
latch_d_r[i] = 0;
latch_bit_wr_x_r[i] = -1;
latch_addr_r[i] = 0;
q_v_r[i] = 0;
}
}
};
#endif
|
#include <iostream>
#include <systemc.h>
#define NORTH 0
#define EAST 1
#define SOUTH 2
#define WEST 3
#define LOCAL 4
class Arbitro
{
public:
sc_uint<32> portaDestino;
int buffercircular[5];
Arbitro();
~Arbitro();
void setPrioridade();
int checkPrioridade();
};
|
/*
HardwareSerial.h - Hardware serial library for Wiring
Copyright (c) 2006 Nicholas Zambetti. All right reserved.
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Modified 28 September 2010 by Mark Sproul
Modified 14 August 2012 by Alarus
Modified 3 December 2013 by Matthijs Kooijman
Modified 18 December 2014 by Ivan Grokhotkov (esp8266 platform support)
Modified 31 March 2015 by Markus Sattler (rewrite the code for UART0 + UART1 support in ESP8266)
Modified 25 April 2015 by Thomas Flayols (add configuration different from 8N1 in ESP8266)
Modified 13 October 2018 by Jeroen Döll (add baudrate detection)
Baudrate detection example usage (detection on Serial1):
void setup() {
Serial.begin(115200);
delay(100);
Serial.println();
Serial1.begin(0, SERIAL_8N1, -1, -1, true, 11000UL); // Passing 0 for baudrate to detect it, the last parameter is a timeout in ms
unsigned long detectedBaudRate = Serial1.baudRate();
if(detectedBaudRate) {
Serial.printf("Detected baudrate is %lu\n", detectedBaudRate);
} else {
Serial.println("No baudrate detected, Serial1 will not work!");
}
}
Pay attention: the baudrate returned by baudRate() may be rounded, eg 115200 returns 115201
*/
#ifndef HardwareSerial_h
#define HardwareSerial_h
#include <inttypes.h>
#include <systemc.h>
#include "Stream.h"
#include "esp32-hal.h"
#include <TestSerial.h>
class HardwareSerial: public Stream
{
public:
HardwareSerial(int uart_nr);
void begin(unsigned long baud, uint32_t config=SERIAL_8N1, int8_t rxPin=-1, int8_t txPin=-1, bool invert=false, unsigned long timeout_ms = 20000UL);
void end();
void updateBaudRate(unsigned long baud);
int available(void);
int availableForWrite(void);
int peek(void);
int read(void);
void flush(void);
void flush( bool txOnly);
size_t write(uint8_t);
size_t write(const uint8_t *buffer, size_t size);
inline size_t write(const char * s)
{
return write((uint8_t*) s, strlen(s));
}
inline size_t write(unsigned long n)
{
return write((uint8_t) n);
}
inline size_t write(long n)
{
return write((uint8_t) n);
}
inline size_t write(unsigned int n)
{
return write((uint8_t) n);
}
inline size_t write(int n)
{
return write((uint8_t) n);
}
uint32_t baudRate();
operator bool() const;
size_t setRxBufferSize(size_t);
void setDebugOutput(bool);
/* This function is needed to connect the HardwareSerial to the SystemC
* UART model.
*/
void setports(int modn, sc_fifo<unsigned char> *_to,
sc_fifo<unsigned char> *_from, void *_mod);
protected:
virtual int peek_timeout(unsigned long int tmout);
virtual int read_timeout(unsigned long int tmout);
protected:
int _uart_nr;
uart_t* _uart;
};
extern void serialEventRun(void) __attribute__((weak));
#if !defined(NO_GLOBAL_INSTANCES) && !defined(NO_GLOBAL_SERIAL)
extern HardwareSerial Serial;
extern HardwareSerial Serial1;
extern HardwareSerial Serial2;
#endif
#endif // HardwareSerial_h
|
//
// Copyright 2022 Sergey Khabarov, [email protected]
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
#pragma once
#include <systemc.h>
#include "../../techmap/mem/ram_cache_bwe_tech.h"
#include "../../techmap/mem/ram_tech.h"
#include "api_core.h"
namespace debugger {
template<int abus = 64, // system bus address width (64 or 32 bits)
int ibits = 6, // lines memory address width (usually 6..8)
int lnbits = 5, // One line bits: log2(bytes_per_line)
int flbits = 4, // total flags number saved with address tag
int snoop = 0> // 0 Snoop port disabled; 1 Enabled (L2 caching)
SC_MODULE(TagMem) {
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
sc_in<sc_uint<abus>> i_addr;
sc_in<sc_uint<(1 << lnbits)>> i_wstrb;
sc_in<sc_biguint<(8 * (1 << lnbits))>> i_wdata;
sc_in<sc_uint<flbits>> i_wflags;
sc_out<sc_uint<abus>> o_raddr;
sc_out<sc_biguint<(8 * (1 << lnbits))>> o_rdata;
sc_out<sc_uint<flbits>> o_rflags;
sc_out<bool> o_hit;
// L2 snoop port, active when snoop = 1
sc_in<sc_uint<abus>> i_snoop_addr;
sc_out<sc_uint<flbits>> o_snoop_flags;
void comb();
void registers();
SC_HAS_PROCESS(TagMem);
TagMem(sc_module_name name,
bool async_reset);
virtual ~TagMem();
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
bool async_reset_;
static const int TAG_BITS = ((abus - ibits) - lnbits);
static const int TAG_WITH_FLAGS = (TAG_BITS + flbits);
struct TagMem_registers {
sc_signal<sc_uint<TAG_BITS>> tagaddr;
sc_signal<sc_uint<ibits>> index;
sc_signal<sc_uint<TAG_BITS>> snoop_tagaddr;
} v, r;
void TagMem_r_reset(TagMem_registers &iv) {
iv.tagaddr = 0;
iv.index = 0;
iv.snoop_tagaddr = 0;
}
sc_signal<sc_uint<ibits>> wb_index;
sc_signal<sc_uint<TAG_WITH_FLAGS>> wb_tago_rdata;
sc_signal<sc_uint<TAG_WITH_FLAGS>> wb_tagi_wdata;
sc_signal<bool> w_tagi_we;
sc_signal<sc_uint<ibits>> wb_snoop_index;
sc_signal<sc_uint<TAG_BITS>> wb_snoop_tagaddr;
sc_signal<sc_uint<TAG_WITH_FLAGS>> wb_tago_snoop_rdata;
ram_cache_bwe_tech<ibits, (8 * (1 << lnbits))> *data0;
ram_tech<ibits, TAG_WITH_FLAGS> *tag0;
ram_tech<ibits, TAG_WITH_FLAGS> *tagsnoop0;
};
template<int abus, int ibits, int lnbits, int flbits, int snoop>
TagMem<abus, ibits, lnbits, flbits, snoop>::TagMem(sc_module_name name,
bool async_reset)
: sc_module(name),
i_clk("i_clk"),
i_nrst("i_nrst"),
i_addr("i_addr"),
i_wstrb("i_wstrb"),
i_wdata("i_wdata"),
i_wflags("i_wflags"),
o_raddr("o_raddr"),
o_rdata("o_rdata"),
o_rflags("o_rflags"),
o_hit("o_hit"),
i_snoop_addr("i_snoop_addr"),
o_snoop_flags("o_snoop_flags") {
async_reset_ = async_reset;
data0 = 0;
tag0 = 0;
tagsnoop0 = 0;
// bwe = byte write enable
data0 = new ram_cache_bwe_tech<ibits,
(8 * (1 << lnbits))>("data0");
data0->i_clk(i_clk);
data0->i_addr(wb_index);
data0->i_wena(i_wstrb);
data0->i_wdata(i_wdata);
data0->o_rdata(o_rdata);
tag0 = new ram_tech<ibits,
TAG_WITH_FLAGS>("tag0");
tag0->i_clk(i_clk);
tag0->i_addr(wb_index);
tag0->i_wena(w_tagi_we);
tag0->i_wdata(wb_tagi_wdata);
tag0->o_rdata(wb_tago_rdata);
// generate
if (snoop) {
tagsnoop0 = new ram_tech<ibits,
TAG_WITH_FLAGS>("tagsnoop0");
tagsnoop0->i_clk(i_clk);
tagsnoop0->i_addr(wb_snoop_index);
tagsnoop0->i_wena(w_tagi_we);
tagsnoop0->i_wdata(wb_tagi_wdata);
tagsnoop0->o_rdata(wb_tago_snoop_rdata);
} else {
wb_tago_snoop_rdata = 0;
}
// endgenerate
SC_METHOD(comb);
sensitive << i_nrst;
sensitive << i_addr;
sensitive << i_wstrb;
sensitive << i_wdata;
sensitive << i_wflags;
sensitive << i_snoop_addr;
sensitive << wb_index;
sensitive << wb_tago_rdata;
sensitive << wb_tagi_wdata;
sensitive << w_tagi_we;
sensitive << wb_snoop_index;
sensitive << wb_snoop_tagaddr;
sensitive << wb_tago_snoop_rdata;
sensitive << r.tagaddr;
sensitive << r.index;
sensitive << r.snoop_tagaddr;
SC_METHOD(registers);
sensitive << i_nrst;
sensitive << i_clk.pos();
}
template<int abus, int ibits, int lnbits, int flbits, int snoop>
TagMem<abus, ibits, lnbits, flbits, snoop>::~TagMem() {
if (data0) {
delete data0;
}
if (tag0) {
delete tag0;
}
if (tagsnoop0) {
delete tagsnoop0;
}
}
template<int abus, int ibits, int lnbits, int flbits, int snoop>
void TagMem<abus, ibits, lnbits, flbits, snoop>::generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd) {
std::string pn(name());
if (o_vcd) {
sc_trace(o_vcd, i_addr, i_addr.name());
sc_trace(o_vcd, i_wstrb, i_wstrb.name());
sc_trace(o_vcd, i_wdata, i_wdata.name());
sc_trace(o_vcd, i_wflags, i_wflags.name());
sc_trace(o_vcd, o_raddr, o_raddr.name());
sc_trace(o_vcd, o_rdata, o_rdata.name());
sc_trace(o_vcd, o_rflags, o_rflags.name());
sc_trace(o_vcd, o_hit, o_hit.name());
sc_trace(o_vcd, i_snoop_addr, i_snoop_addr.name());
sc_trace(o_vcd, o_snoop_flags, o_snoop_flags.name());
sc_trace(o_vcd, r.tagaddr, pn + ".r_tagaddr");
sc_trace(o_vcd, r.index, pn + ".r_index");
sc_trace(o_vcd, r.snoop_tagaddr, pn + ".r_snoop_tagaddr");
}
}
template<int abus, int ibits, int lnbits, int flbits, int snoop>
void TagMem<abus, ibits, lnbits, flbits, snoop>::comb() {
sc_uint<ibits> vb_index;
sc_uint<abus> vb_raddr;
sc_uint<TAG_WITH_FLAGS> vb_tagi_wdata;
bool v_hit;
sc_uint<ibits> vb_snoop_index;
sc_uint<TAG_BITS> vb_snoop_tagaddr;
sc_uint<flbits> vb_snoop_flags;
vb_index = 0;
vb_raddr = 0;
vb_tagi_wdata = 0;
v_hit = 0;
vb_snoop_index = 0;
vb_snoop_tagaddr = 0;
vb_snoop_flags = 0;
v = r;
if (r.tagaddr.read() == wb_tago_rdata.read()((TAG_BITS - 1), 0)) {
v_hit = wb_tago_rdata.read()[TAG_BITS]; // valid bit
}
vb_raddr((abus - 1), (ibits + lnbits)) = wb_tago_rdata.read()((TAG_BITS - 1), 0);
vb_raddr(((ibits + lnbits) - 1), lnbits) = r.index;
vb_index = i_addr.read()(((ibits + lnbits) - 1), lnbits);
vb_tagi_wdata((TAG_BITS - 1), 0) = i_addr.read()((abus - 1), (ibits + lnbits));
vb_tagi_wdata((TAG_WITH_FLAGS - 1), TAG_BITS) = i_wflags;
if (snoop == 1) {
vb_snoop_flags = wb_tago_snoop_rdata.read()((TAG_WITH_FLAGS - 1), TAG_BITS);
vb_snoop_index = i_snoop_addr.read()(((ibits + lnbits) - 1), lnbits);
vb_snoop_tagaddr = i_snoop_addr.read()((abus - 1), (ibits + lnbits));
if (i_wstrb.read().or_reduce() == 1) {
vb_snoop_index = vb_index;
}
if (r.snoop_tagaddr.read() != wb_tago_snoop_rdata.read()((TAG_BITS - 1), 0)) {
vb_snoop_flags = 0;
}
}
v.tagaddr = vb_tagi_wdata((TAG_BITS - 1), 0);
v.index = vb_index;
v.snoop_tagaddr = vb_snoop_tagaddr;
if (!async_reset_ && i_nrst.read() == 0) {
TagMem_r_reset(v);
}
wb_index = vb_index;
w_tagi_we = i_wstrb.read().or_reduce();
wb_tagi_wdata = vb_tagi_wdata;
o_raddr = vb_raddr;
o_rflags = wb_tago_rdata.read()((TAG_WITH_FLAGS - 1), TAG_BITS);
o_hit = v_hit;
wb_snoop_index = vb_snoop_index;
wb_snoop_tagaddr = vb_snoop_tagaddr;
o_snoop_flags = vb_snoop_flags;
}
template<int abus, int ibits, int lnbits, int flbits, int snoop>
void TagMem<abus, ibits, lnbits, flbits, snoop>::registers() {
if (async_reset_ && i_nrst.read() == 0) {
TagMem_r_reset(r);
} else {
r = v;
}
}
} // namespace debugger
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/************************************************/
// Copyright tlm_noc contributors.
// Author Mike
// SPDX-License-Identifier: Apache-2.0
/************************************************/
#ifndef _TLM_ROUTER_H__
#define _TLM_ROUTER_H__
#include <systemc.h>
#include <tlm.h>
#include <tlm_utils/peq_with_cb_and_phase.h>
#include <tlm_utils/simple_initiator_socket.h>
#include <tlm_utils/simple_target_socket.h>
#include "noc_payload.h"
#include "tlm_noc.h"
#include "dumpWave.h"
using namespace std;
using namespace tlm;
class Router: public sc_core::sc_module {
SC_HAS_PROCESS(Router);
public:
char signal[100];
char sbuff[10000];
int row_index;
int col_index;
// TLM interface
tlm_utils::simple_initiator_socket<Router> m_port[N_RTR_PORT];
tlm_utils::simple_target_socket<Router> s_port[N_RTR_PORT];
// Constructor
Router(sc_core::sc_module_name name, int row, int col);
private:
tlm_sync_enum slv_nb_transport_fw(gp& payload, tlm_phase& phase, sc_time& delay);
tlm_sync_enum mst_nb_transport_bw(gp& payload, tlm_phase& phase, sc_time& delay);
void route_fw_callback(gp& trans, const tlm_phase& phase);
void route_bw_callback(gp& trans, const tlm_phase& phase);
// Declare the peq with callback function
tlm_utils::peq_with_cb_and_phase<Router> peq_route_fw;
tlm_utils::peq_with_cb_and_phase<Router> peq_route_bw;
};
#endif
|
/**
* Author: Anubhav Tomar
*
* Library Definition
**/
#ifndef LIB_H
#define LIB_H
#include<systemc.h>
#include <map>
struct point {
double x;
double y;
};
std::map<int , point> leftPointMap ();
std::map<int , point> rightPointMap ();
std::map<int , int> northMap ();
std::map<int , int> southtMap ();
std::map<int , int> eastMap ();
std::map<int , int> westMap ();
std::map<int , std::vector<int> > robotPathMap ();
std::map<int , int> robotStatusMap ();
std::map<int , std::vector<int> > obstaclePathMap ();
std::map<int , int> robotDir ();
std::map<int , int> robotLocGrid ();
std::map<int , point> robotLocPoint ();
std::map<int , int> obstacleDir ();
std::map<int , int> obstacleLocGrid ();
std::map<int , point> obstacleLocPoint ();
std::vector<double> gridPointsLocRobot ();
std::vector<double> gridPointsLocObstacle ();
void _printValue (int grid);
void _logGridRobot ();
std::map<int , point> _leftPoint = leftPointMap();
std::map<int , point> _rightPoint = rightPointMap();
std::map<int , int> _north = northMap();
std::map<int , int> _south = southtMap();
std::map<int , int> _east = eastMap();
std::map<int , int> _west = westMap();
std::map<int , std::vector<int> > _robotPath = robotPathMap();
std::map<int , int> _robotStatus = robotStatusMap();
std::map<int , std::vector<int> > _obstaclePath = obstaclePathMap();
std::map<int , int> _robotDir = robotDir();
std::map<int , int> _robotLocGrid = robotLocGrid();
std::map<int , point> _robotLocPoint = robotLocPoint();
std::map<int , int> _obstacleDir = obstacleDir();
std::map<int , int> _obstacleLocGrid = obstacleLocGrid();
std::map<int , point> _obstacleLocPoint = obstacleLocPoint();
std::vector<double> _gridPointsLocRobot = gridPointsLocRobot();
std::vector<double> _gridPointsLocObstacle = gridPointsLocObstacle();
std::map<int , point> leftPointMap () {
std::map<int , point> _map;
int j=0;
for(int i = 1 ; i <= 10 ; i++) {
_map[i] = {j++*5 , 8*5};
}
_map[11] = {0*5 , 7*5};
_map[12] = {9*5 , 7*5};
j=0;
for(int i = 13 ; i <= 22 ; i++) {
_map[i] = {j++*5 , 6*5};
}
_map[23] = {0*5 , 5*5};
_map[24] = {5*5 , 5*5};
_map[25] = {9*5 , 5*5};
j=0;
for(int i = 26 ; i <= 35 ; i++) {
_map[i] = {j++*5 , 4*5};
}
_map[36] = {0*5 , 3*5};
_map[37] = {6*5 , 3*5};
_map[38] = {9*5 , 3*5};
j=0;
for(int i = 39 ; i <= 48 ; i++) {
_map[i] = {j++*5 , 2*5};
}
_map[49] = {0*5 , 1*5};
_map[50] = {9*5 , 1*5};
j=0;
for(int i = 51 ; i <= 60 ; i++) {
_map[i] = {j++*5 , 0*5};
}
return _map;
}
std::map<int , point> rightPointMap () {
std::map<int , point> _map;
int j=0;
for(int i = 1 ; i <= 10 ; i++) {
_map[i] = {++j*5 , 9*5};
}
_map[11] = {0*5 , 8*5};
_map[12] = {9*5 , 8*5};
j=0;
for(int i = 13 ; i <= 22 ; i++) {
_map[i] = {++j*5 , 7*5};
}
_map[23] = {1*5 , 6*5};
_map[24] = {6*5 , 6*5};
_map[25] = {10*5 , 6*5};
j=0;
for(int i = 26 ; i <= 35 ; i++) {
_map[i] = {++j*5 , 5*5};
}
_map[36] = {1*5 , 4*5};
_map[37] = {7*5 , 4*5};
_map[38] = {10*5 , 4*5};
j=0;
for(int i = 39 ; i <= 48 ; i++) {
_map[i] = {++j*5 , 3*5};
}
_map[49] = {1*5 , 2*5};
_map[50] = {10*5 , 2*5};
j=0;
for(int i = 51 ; i <= 60 ; i++) {
_map[i] = {++j*5 , 1*5};
}
return _map;
}
std::map<int , int> northMap () {
std::map<int , int> _map;
for(int i = 1 ; i <= 10 ; i++) {
_map[i] = -1;
}
_map[11] = 1;
_map[12] = 10;
_map[13] = 11;
for(int i = 14 ; i <= 21 ; i++) {
_map[i] = -1;
}
_map[22] = 12;
_map[23] = 13;
_map[24] = 18;
_map[25] = 22;
_map[26] = 23;
for(int i = 27 ; i <= 30 ; i++) {
_map[i] = -1;
}
_map[31] = 24;
for(int i = 32 ; i <= 34 ; i++) {
_map[i] = -1;
}
_map[35] = 25;
_map[36] = 26;
_map[37] = 32;
_map[38] = 35;
_map[39] = 36;
for(int i = 40 ; i <= 44 ; i++) {
_map[i] = -1;
}
_map[45] = 37;
for(int i = 46 ; i <= 47 ; i++) {
_map[i] = -1;
}
_map[48] = 38;
_map[49] = 39;
_map[50] = 48;
_map[51] = 49;
for(int i = 52 ; i <= 59 ; i++) {
_map[i] = -1;
}
_map[60] = 50;
return _map;
}
std::map<int , int> southtMap () {
std::map<int , int> _map;
_map[1] = 11;
for(int i = 2 ; i <= 9 ; i++) {
_map[i] = -1;
}
_map[10] = 12;
_map[11] = 1;
_map[12] = 10;
_map[13] = 11;
for(int i = 14 ; i <= 17 ; i++) {
_map[i] = -1;
}
_map[18] = 24;
for(int i = 19 ; i <= 21 ; i++) {
_map[i] = -1;
}
_map[22] = 25;
_map[23] = 26;
_map[24] = 31;
_map[25] = 35;
_map[26] = 36;
for(int i = 27 ; i <= 31 ; i++) {
_map[i] = -1;
}
_map[32] = 37;
for(int i = 33 ; i <= 34 ; i++) {
_map[i] = -1;
}
_map[35] = 38;
_map[36] = 39;
_map[37] = 45;
_map[38] = 48;
_map[39] = 49;
for(int i = 40 ; i <= 47 ; i++) {
_map[i] = -1;
}
_map[48] = 50;
_map[49] = 51;
_map[50] = 60;
for(int i = 51 ; i <= 60 ; i++) {
_map[i] = -1;
}
return _map;
}
std::map<int , int> eastMap () {
std::map<int , int> _map;
_map[1] = -1;
for(int i = 2 ; i <= 10 ; i++) {
_map[i] = i - 1;
}
_map[11] = -1;
_map[12] = -1;
_map[13] = -1;
for(int i = 14 ; i <= 22 ; i++) {
_map[i] = i - 1;
}
_map[23] = -1;
_map[24] = -1;
_map[25] = -1;
_map[26] = -1;
for(int i = 27 ; i <= 35 ; i++) {
_map[i] = i - 1;
}
_map[36] = -1;
_map[37] = -1;
_map[38] = -1;
_map[39] = -1;
for(int i = 40 ; i <= 48 ; i++) {
_map[i] = i - 1;
}
_map[49] = -1;
_map[50] = -1;
_map[51] = -1;
for(int i = 52 ; i <= 60 ; i++) {
_map[i] = i - 1;
}
return _map;
}
std::map<int , int> westMap () {
std::map<int , int> _map;
for(int i = 1 ; i <= 9 ; i++) {
_map[i] = i + 1;
}
_map[10] = -1;
_map[11] = -1;
_map[12] = -1;
for(int i = 13 ; i <= 21 ; i++) {
_map[i] = i + 1;
}
_map[22] = -1;
_map[23] = -1;
_map[24] = -1;
_map[25] = -1;
for(int i = 26 ; i <= 34 ; i++) {
_map[i] = i + 1;
}
_map[35] = -1;
_map[36] = -1;
_map[37] = -1;
_map[38] = -1;
for(int i = 39 ; i <= 47 ; i++) {
_map[i] = i + 1;
}
_map[48] = -1;
_map[49] = -1;
_map[50] = -1;
for(int i = 51 ; i <= 59 ; i++) {
_map[i] = i + 1;
}
_map[60] = -1;
return _map;
}
std::map<int , std::vector<int> > robotPathMap () {
std::map<int , std::vector<int> > _map;
// Robot 1
_map[1].push_back(0);
_map[1].push_back(1);
_map[1].push_back(11);
_map[1].push_back(13);
_map[1].push_back(14);
_map[1].push_back(15);
_map[1].push_back(16);
_map[1].push_back(17);
_map[1].push_back(18);
_map[1].push_back(24);
_map[1].push_back(31);
_map[1].push_back(30);
_map[1].push_back(29);
_map[1].push_back(28);
_map[1].push_back(27);
_map[1].push_back(26);
_map[1].push_back(36);
_map[1].push_back(39);
// Robot 2
_map[2].push_back(0);
_map[2].push_back(10);
_map[2].push_back(12);
_map[2].push_back(22);
_map[2].push_back(21);
_map[2].push_back(20);
_map[2].push_back(19);
_map[2].push_back(18);
_map[2].push_back(24);
_map[2].push_back(31);
_map[2].push_back(32);
_map[2].push_back(33);
_map[2].push_back(34);
_map[2].push_back(35);
_map[2].push_back(25);
// Robot 3
_map[3].push_back(0);
_map[3].push_back(49);
_map[3].push_back(39);
_map[3].push_back(36);
_map[3].push_back(26);
_map[3].push_back(27);
_map[3].push_back(28);
_map[3].push_back(29);
_map[3].push_back(30);
_map[3].push_back(31);
_map[3].push_back(32);
_map[3].push_back(37);
_map[3].push_back(45);
_map[3].push_back(46);
_map[3].push_back(47);
_map[3].push_back(48);
_map[3].push_back(38);
// Robot 4
_map[4].push_back(0);
_map[4].push_back(60);
_map[4].push_back(50);
_map[4].push_back(48);
_map[4].push_back(47);
_map[4].push_back(46);
_map[4].push_back(45);
_map[4].push_back(44);
_map[4].push_back(43);
_map[4].push_back(42);
_map[4].push_back(41);
_map[4].push_back(40);
_map[4].push_back(39);
_map[4].push_back(49);
_map[4].push_back(51);
_map[4].push_back(52);
_map[4].push_back(53);
_map[4].push_back(54);
_map[4].push_back(55);
return _map;
}
std::map<int , int> robotStatusMap () {
std::map<int , int> _map;
// Robot 1
_map[1] = 1;
// Robot 2
_map[2] = 1;
// Robot 3
_map[3] = 1;
// Robot 4
_map[4] = 1;
return _map;
}
std::map<int , std::vector<int> > obstaclePathMap () {
std::map<int , std::vector<int> > _map;
// Obstacle 1
for(int i = 1 ; i <= 10 ; i++) {
_map[1].push_back(i);
}
_map[1].push_back(12);
for(int i = 22 ; i >= 13 ; i--) {
_map[1].push_back(i);
}
_map[1].push_back(11);
// Obstacle 2
for(int i = 13 ; i <= 18 ; i++) {
_map[2].push_back(i);
}
_map[2].push_back(24);
for(int i = 31 ; i <= 35 ; i++) {
_map[2].push_back(i);
}
_map[2].push_back(25);
for(int i = 22 ; i >= 18 ; i--) {
_map[2].push_back(i);
}
_map[2].push_back(24);
for(int i = 31 ; i >= 26 ; i--) {
_map[2].push_back(i);
}
_map[2].push_back(23);
// Obstacle 3
for(int i = 26 ; i <= 32 ; i++) {
_map[3].push_back(i);
}
_map[3].push_back(37);
for(int i = 45 ; i <= 48 ; i++) {
_map[3].push_back(i);
}
_map[3].push_back(38);
for(int i = 35 ; i >= 32 ; i--) {
_map[3].push_back(i);
}
_map[3].push_back(37);
for(int i = 45 ; i >= 39 ; i--) {
_map[3].push_back(i);
}
_map[3].push_back(36);
// Obstacle 4
for(int i = 39 ; i <= 48 ; i++) {
_map[4].push_back(i);
}
_map[4].push_back(50);
for(int i = 60 ; i >= 51 ; i--) {
_map[4].push_back(i);
}
_map[4].push_back(49);
return _map;
}
std::map<int , int> robotDir () {
std::map<int , int> _map;
for(int i = 1 ; i <= 4 ; i++) {
_map[i] = 0;
}
return _map;
}
std::map<int , int> robotLocGrid () {
std::map<int , int> _map;
for(int i = 1 ; i <= 4 ; i++) {
_map[i] = 0;
}
return _map;
}
std::map<int , point> robotLocPoint () {
std::map<int , point> _map;
for(int i = 1 ; i <= 4 ; i++) {
_map[i] = {0 , 0};
}
return _map;
}
std::map<int , int> obstacleDir () {
std::map<int , int> _map;
for(int i = 1 ; i <= 4 ; i++) {
_map[i] = 0;
}
return _map;
}
std::map<int , int> obstacleLocGrid () {
std::map<int , int> _map;
for(int i = 1 ; i <= 4 ; i++) {
_map[i] = 0;
}
return _map;
}
std::map<int , point> obstacleLocPoint () {
std::map<int , point> _map;
for(int i = 1 ; i <= 4 ; i++) {
_map[i] = {0 , 0};
}
return _map;
}
std::vector<double> gridPointsLocRobot () {
std::vector<double> _v;
for(int i = 1 ; i <= 10 ; i++) {
_v.push_back(0.5*i);
}
return _v;
}
std::vector<double> gridPointsLocObstacle () {
std::vector<double> _v;
for(int i = 1 ; i <= 2 ; i++) {
_v.push_back(2.5*i);
}
return _v;
}
void _printValue (int grid) {
for(int j = 1 ; j <= 4 ; j++) {
if(_robotLocGrid[j] == grid) {
cout<<"R"<<j<<" ";
return;
} else if(_obstacleLocGrid[j] == grid) {
cout<<"O"<<j<<" ";
return;
}
}
cout<<" - ";
}
void _logGridRobot () {
for(int i = 1 ; i <= 10 ; i++) {
_printValue(i);
}
cout<<endl;
_printValue(11);
for(int i = 1 ; i <= 8 ; i++) {
cout<<" X ";
}
_printValue(12);
cout<<endl;
for(int i = 13 ; i <= 22 ; i++) {
_printValue(i);
}
cout<<endl;
_printValue(23);
for(int i = 1 ; i <= 4 ; i++) {
cout<<" X ";
}
_printValue(24);
for(int i = 1 ; i <= 3 ; i++) {
cout<<" X ";
}
_printValue(25);
cout<<endl;
for(int i = 26 ; i <= 35 ; i++) {
_printValue(i);
}
cout<<endl;
_printValue(36);
for(int i = 1 ; i <= 5 ; i++) {
cout<<" X ";
}
_printValue(37);
for(int i = 1 ; i <= 2 ; i++) {
cout<<"X ";
}
_printValue(38);
cout<<endl;
for(int i = 39 ; i <= 48 ; i++) {
_printValue(i);
}
cout<<endl;
_printValue(49);
for(int i = 1 ; i <= 8 ; i++) {
cout<<" X ";
}
_printValue(50);
cout<<endl;
for(int i = 51 ; i <= 60 ; i++) {
_printValue(i);
}
cout<<endl;
}
#endif
|
/*
* Created on: 21. jun. 2019
* Author: Jonathan Horsted Schougaard
*/
#pragma once
#include <systemc.h>
#include "hwcore/dsp/imfilter.h"
#include "hwcore/tb/scfileio.h"
#define TB_IMFILTER_W W_WIDTH
SC_MODULE(filter_load)
{
SC_MODULE_CLK_RESET_SIGNAL;
sc_out<sc_fixed<W_WIDTH,P_DATA> > Wout[3*3];
SC_CTOR_DEFAULT(filter_load)
{
SC_CTHREAD(thread_filter_load, clk.pos());
reset_signal_is(reset,true);
}
void thread_filter_load()
{
sc_fixed<W_WIDTH,P_DATA> coeffs[N_ROWS * N_ROWS] = {1.0f, 0.0f, -1.0f,
2.0f, 0.0f, -2.0f,
1.0f, 0.0f, -1.0f};
//sc_fixed<16,8> coeffs[N_ROWS * N_ROWS] = {0.1f, 0.2f, 0.3f,
// 0.4f, 0.5f, -0.4f,
// -0.3f, -0.2f, -0.1f};
for(int i=0;i<3*3;i++)
{
Wout[i].write(coeffs[i]);
}
while(1)
{
wait();
}
}
};
SC_MODULE(TB_imfilter_top)
{
sc_clock clk;
sc_signal<bool> reset;
template<int W>
using imread = hwcore::tb::imread_func_fx<W,W/2>;
template<int W>
using imwrite = hwcore::tb::imwrite_func_fx<W,W/2>;
template<int W=TB_IMFILTER_W, int depth=16>
using fifo=hwcore::hf::sc_fifo_template< hwcore::pipes::sc_data_stream_t<W>, depth >;
hwcore::tb::sc_fileread<TB_IMFILTER_W, imread> fr_u1;
fifo<> u1_2_u2;
filter_load filter_loader;
sc_signal<sc_fixed<W_WIDTH,P_DATA> > Wout[3*3];
imfilter filter_u2;
fifo<> u2_2_u3;
hwcore::tb::sc_filewrite<TB_IMFILTER_W, imwrite> fw_u3;
SC_CTOR_DEFAULT(TB_imfilter_top)
:clk("clk",sc_time(10,SC_NS)),fr_u1("in_im_512_x_512.txt"), fw_u3("out_im_512_x_512.txt")
{
SC_MODULE_LINK(filter_u2);
SC_MODULE_LINK(filter_loader);
fr_u1.dout(u1_2_u2);
for(int i = 0; i < 3*3; i++)
{
filter_loader.Wout[i](Wout[i]);
filter_u2.Win[i](Wout[i]);
}
filter_u2.din(u1_2_u2);
filter_u2.dout(u2_2_u3);
fw_u3.din(u2_2_u3);
}
};
|
/*
* Copyright (c) 2015, University of Kaiserslautern
* Copyright (c) 2016, Dresden University of Technology (TU Dresden)
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __SC_EXT_HH__
#define __SC_EXT_HH__
#include <systemc.h>
#include <tlm.h>
#include <iostream>
#include "mem/packet.hh"
namespace Gem5SystemC
{
class Gem5Extension: public tlm::tlm_extension<Gem5Extension>
{
public:
Gem5Extension(gem5::PacketPtr packet);
virtual tlm_extension_base* clone() const;
virtual void copy_from(const tlm_extension_base& ext);
static Gem5Extension&
getExtension(const tlm::tlm_generic_payload *payload);
static Gem5Extension&
getExtension(const tlm::tlm_generic_payload &payload);
gem5::PacketPtr getPacket();
private:
gem5::PacketPtr Packet;
};
}
#endif
|
/********************************************************************************
* University of L'Aquila - HEPSYCODE Source Code License *
* *
* *
* (c) 2018-2019 Centre of Excellence DEWS All rights reserved *
********************************************************************************
* <one line to give the program's name and a brief idea of what it does.> *
* Copyright (C) 2022 Vittoriano Muttillo, Luigi Pomante * *
* *
* This program is free software: you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation, either version 3 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
********************************************************************************
* *
* Created on: 09/May/2023 *
* Authors: Vittoriano Muttillo, Marco Santic, Luigi Pomante *
* *
* email: [email protected] *
* [email protected] *
* [email protected] *
* *
********************************************************************************
* This code has been developed from an HEPSYCODE model used as demonstrator by *
* University of L'Aquila. *
*******************************************************************************/
#include <systemc.h>
#include "../mainsystem.h"
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <math.h>
#include <unistd.h>
////////////////////////////// GENANN //////////////////
#ifdef __cplusplus
extern "C" {
#endif
#ifndef ann_01_GENANN_RANDOM
/* We use the following for uniform random numbers between 0 and 1.
* If you have a better function, redefine this macro. */
#define ann_01_GENANN_RANDOM() (((double)rand())/RAND_MAX)
#endif
struct ann_01_genann;
typedef double (*ann_01_genann_actfun)(const struct ann_01_genann *ann, double a);
typedef struct ann_01_genann {
/* How many inputs, outputs, and hidden neurons. */
int inputs, hidden_layers, hidden, outputs;
/* Which activation function to use for hidden neurons. Default: gennann_act_sigmoid_cached*/
ann_01_genann_actfun activation_hidden;
/* Which activation function to use for output. Default: gennann_act_sigmoid_cached*/
ann_01_genann_actfun activation_output;
/* Total number of weights, and size of weights buffer. */
int total_weights;
/* Total number of neurons + inputs and size of output buffer. */
int total_neurons;
/* All weights (total_weights long). */
double *weight;
/* Stores input array and output of each neuron (total_neurons long). */
double *output;
/* Stores delta of each hidden and output neuron (total_neurons - inputs long). */
double *delta;
} ann_01_genann;
#ifdef __cplusplus
}
#endif
///////////////////////////////////// GENANN ///////////////////////////
#ifndef ann_01_genann_act
#define ann_01_genann_act_hidden ann_01_genann_act_hidden_indirect
#define ann_01_genann_act_output ann_01_genann_act_output_indirect
#else
#define ann_01_genann_act_hidden ann_01_genann_act
#define ann_01_genann_act_output ann_01_genann_act
#endif
#define ann_01_LOOKUP_SIZE 4096
double ann_01_genann_act_hidden_indirect(const struct ann_01_genann *ann, double a) {
return ann->activation_hidden(ann, a);
}
double ann_01_genann_act_output_indirect(const struct ann_01_genann *ann, double a) {
return ann->activation_output(ann, a);
}
const double ann_01_sigmoid_dom_min = -15.0;
const double ann_01_sigmoid_dom_max = 15.0;
double ann_01_interval;
double ann_01_lookup[ann_01_LOOKUP_SIZE];
#ifdef __GNUC__
#define likely(x) __builtin_expect(!!(x), 1)
#define unlikely(x) __builtin_expect(!!(x), 0)
#define unused __attribute__((unused))
#else
#define likely(x) x
#define unlikely(x) x
#define unused
#pragma warning(disable : 4996) /* For fscanf */
#endif
double ann_01_genann_act_sigmoid(const ann_01_genann *ann unused, double a) {
if (a < -45.0) return 0;
if (a > 45.0) return 1;
return 1.0 / (1 + exp(-a));
}
void ann_01_genann_init_sigmoid_lookup(const ann_01_genann *ann) {
const double f = (ann_01_sigmoid_dom_max - ann_01_sigmoid_dom_min) / ann_01_LOOKUP_SIZE;
int i;
ann_01_interval = ann_01_LOOKUP_SIZE / (ann_01_sigmoid_dom_max - ann_01_sigmoid_dom_min);
for (i = 0; i < ann_01_LOOKUP_SIZE; ++i) {
ann_01_lookup[i] = ann_01_genann_act_sigmoid(ann, ann_01_sigmoid_dom_min + f * i);
}
}
double ann_01_genann_act_sigmoid_cached(const ann_01_genann *ann unused, double a) {
assert(!isnan(a));
if (a < ann_01_sigmoid_dom_min) return ann_01_lookup[0];
if (a >= ann_01_sigmoid_dom_max) return ann_01_lookup[ann_01_LOOKUP_SIZE - 1];
size_t j = (size_t)((a-ann_01_sigmoid_dom_min)*ann_01_interval+0.5);
/* Because floating point... */
if (unlikely(j >= ann_01_LOOKUP_SIZE)) return ann_01_lookup[ann_01_LOOKUP_SIZE - 1];
return ann_01_lookup[j];
}
double ann_01_genann_act_linear(const struct ann_01_genann *ann unused, double a) {
return a;
}
double ann_01_genann_act_threshold(const struct ann_01_genann *ann unused, double a) {
return a > 0;
}
void ann_01_genann_randomize(ann_01_genann *ann) {
int i;
for (i = 0; i < ann->total_weights; ++i) {
double r = ann_01_GENANN_RANDOM();
/* Sets weights from -0.5 to 0.5. */
ann->weight[i] = r - 0.5;
}
}
ann_01_genann *ann_01_genann_init(int inputs, int hidden_layers, int hidden, int outputs) {
if (hidden_layers < 0) return 0;
if (inputs < 1) return 0;
if (outputs < 1) return 0;
if (hidden_layers > 0 && hidden < 1) return 0;
const int hidden_weights = hidden_layers ? (inputs+1) * hidden + (hidden_layers-1) * (hidden+1) * hidden : 0;
const int output_weights = (hidden_layers ? (hidden+1) : (inputs+1)) * outputs;
const int total_weights = (hidden_weights + output_weights);
const int total_neurons = (inputs + hidden * hidden_layers + outputs);
/* Allocate extra size for weights, outputs, and deltas. */
const int size = sizeof(ann_01_genann) + sizeof(double) * (total_weights + total_neurons + (total_neurons - inputs));
ann_01_genann *ret = (ann_01_genann *)malloc(size);
if (!ret) return 0;
ret->inputs = inputs;
ret->hidden_layers = hidden_layers;
ret->hidden = hidden;
ret->outputs = outputs;
ret->total_weights = total_weights;
ret->total_neurons = total_neurons;
/* Set pointers. */
ret->weight = (double*)((char*)ret + sizeof(ann_01_genann));
ret->output = ret->weight + ret->total_weights;
ret->delta = ret->output + ret->total_neurons;
ann_01_genann_randomize(ret);
ret->activation_hidden = ann_01_genann_act_sigmoid_cached;
ret->activation_output = ann_01_genann_act_sigmoid_cached;
ann_01_genann_init_sigmoid_lookup(ret);
return ret;
}
void ann_01_genann_free(ann_01_genann *ann) {
/* The weight, output, and delta pointers go to the same buffer. */
free(ann);
}
//genann *genann_read(FILE *in)
//genann *genann_copy(genann const *ann)
double const *ann_01_genann_run(ann_01_genann const *ann, double const *inputs) {
double const *w = ann->weight;
double *o = ann->output + ann->inputs;
double const *i = ann->output;
/* Copy the inputs to the scratch area, where we also store each neuron's
* output, for consistency. This way the first layer isn't a special case. */
memcpy(ann->output, inputs, sizeof(double) * ann->inputs);
int h, j, k;
if (!ann->hidden_layers) {
double *ret = o;
for (j = 0; j < ann->outputs; ++j) {
double sum = *w++ * -1.0;
for (k = 0; k < ann->inputs; ++k) {
sum += *w++ * i[k];
}
*o++ = ann_01_genann_act_output(ann, sum);
}
return ret;
}
/* Figure input layer */
for (j = 0; j < ann->hidden; ++j) {
double sum = *w++ * -1.0;
for (k = 0; k < ann->inputs; ++k) {
sum += *w++ * i[k];
}
*o++ = ann_01_genann_act_hidden(ann, sum);
}
i += ann->inputs;
/* Figure hidden layers, if any. */
for (h = 1; h < ann->hidden_layers; ++h) {
for (j = 0; j < ann->hidden; ++j) {
double sum = *w++ * -1.0;
for (k = 0; k < ann->hidden; ++k) {
sum += *w++ * i[k];
}
*o++ = ann_01_genann_act_hidden(ann, sum);
}
i += ann->hidden;
}
double const *ret = o;
/* Figure output layer. */
for (j = 0; j < ann->outputs; ++j) {
double sum = *w++ * -1.0;
for (k = 0; k < ann->hidden; ++k) {
sum += *w++ * i[k];
}
*o++ = ann_01_genann_act_output(ann, sum);
}
/* Sanity check that we used all weights and wrote all outputs. */
assert(w - ann->weight == ann->total_weights);
assert(o - ann->output == ann->total_neurons);
return ret;
}
//void genann_train(genann const *ann, double const *inputs, double const *desired_outputs, double learning_rate)
//void genann_write(genann const *ann, FILE *out)
/////////////////////// ANN ////////////////////////
#define ann_01_NUM_DEV 1 // The equipment is composed of NUM_DEV devices ...
//-----------------------------------------------------------------------------
//
//-----------------------------------------------------------------------------
#define ann_01_MAX_ANN 100 // Maximum MAX_ANN ANN
#define ann_01_ANN_INPUTS 2 // Number of inputs
#define ann_01_ANN_HIDDEN_LAYERS 1 // Number of hidden layers
#define ann_01_ANN_HIDDEN_NEURONS 2 // Number of neurons of every hidden layer
#define ann_01_ANN_OUTPUTS 1 // Number of outputs
//-----------------------------------------------------------------------------
//
//-----------------------------------------------------------------------------
#define ann_01_ANN_EPOCHS 10000
#define ann_01_ANN_DATASET 6
#define ann_01_ANN_LEARNING_RATE 3 // ...
//-----------------------------------------------------------------------------
//
//-----------------------------------------------------------------------------
#define ann_01_MAX_ERROR 0.00756 // 0.009
//-----------------------------------------------------------------------------
//
//-----------------------------------------------------------------------------
static int ann_01_nANN = -1 ; // Number of ANN that have been created
static ann_01_genann * ann_01_ann[ann_01_MAX_ANN] ; // Now up to MAX_ANN ann
//static double ann_01_trainingInput[ann_01_ANN_DATASET][ann_01_ANN_INPUTS] = { {0, 0}, {0, 1}, {1, 0}, {1, 1}, {0, 1}, {0, 0} } ;
//static double ann_01_trainingExpected[ann_01_ANN_DATASET][ann_01_ANN_OUTPUTS] = { {0}, {1}, {1}, {0}, {1}, {0} } ;
static double ann_01_weights[] = {
-3.100438,
-7.155774,
-7.437955,
-8.132828,
-5.583678,
-5.327152,
5.564897,
-12.201226,
11.771879
} ;
// static double input[4][3] = {{0, 0, 1}, {0, 1, 1}, {1, 0, 1}, {1, 1, 1}};
// static double output[4] = {0, 1, 1, 0};
//-----------------------------------------------------------------------------
//
//-----------------------------------------------------------------------------
static int ann_01_annCheck(int index);
static int ann_01_annCreate(int n);
//-----------------------------------------------------------------------------
// Check the correctness of the index of the ANN
//-----------------------------------------------------------------------------
int ann_01_annCheck(int index)
{
if ( (index < 0) || (index >= ann_01_nANN) )
return( EXIT_FAILURE );
return( EXIT_SUCCESS );
}
//-----------------------------------------------------------------------------
// Create n ANN
//-----------------------------------------------------------------------------
int ann_01_annCreate(int n)
{
// If already created, or not legal number, or too many ANN, then error
if ( (ann_01_nANN != -1) || (n <= 0) || (n > ann_01_MAX_ANN) )
return( EXIT_FAILURE );
// Create the ANN's
for ( int i = 0; i < n; i++ )
{
// New ANN with ANN_INPUT inputs, ANN_HIDDEN_LAYER hidden layers all with ANN_HIDDEN_NEURON neurons, and ANN_OUTPUT outputs
ann_01_ann[i] = ann_01_genann_init(ann_01_ANN_INPUTS, ann_01_ANN_HIDDEN_LAYERS, ann_01_ANN_HIDDEN_NEURONS, ann_01_ANN_OUTPUTS);
if ( ann_01_ann[i] == 0 )
{
for (int j = 0; j < i; j++)
ann_01_genann_free(ann_01_ann[j]) ;
return( EXIT_FAILURE );
}
}
ann_01_nANN = n ;
return( EXIT_SUCCESS );
}
////-----------------------------------------------------------------------------
//// Create and train n identical ANN
////-----------------------------------------------------------------------------
//int annCreateAndTrain(int n)
//{
// if ( annCreate(n) != EXIT_SUCCESS )
// return( EXIT_FAILURE );
//
// // Train the ANN's
// for ( int index = 0; index < nANN; index++ )
// for ( int i = 0; i < ANN_EPOCHS; i++ )
// for ( int j = 0; j < ANN_DATASET; j++ )
// genann_train(ann[index], trainingInput[j], trainingExpected[j], ANN_LEARNING_RATE) ;
//
// return( EXIT_SUCCESS );
//}
//-----------------------------------------------------------------------------
// Create n identical ANN and set their weight
//-----------------------------------------------------------------------------
int ann_01_annCreateAndSetWeights(int n)
{
if ( ann_01_annCreate(n) != EXIT_SUCCESS )
return( EXIT_FAILURE );
// Set weights
for ( int index = 0; index < ann_01_nANN; index++ )
for ( int i = 0; i < ann_01_ann[index]->total_weights; ++i )
ann_01_ann[index]->weight[i] = ann_01_weights[i] ;
return( EXIT_SUCCESS );
}
//-----------------------------------------------------------------------------
// x[2] = x[0] XOR x[1]
//-----------------------------------------------------------------------------
int ann_01_annRun(int index, double x[ann_01_ANN_INPUTS + ann_01_ANN_OUTPUTS])
{
if ( ann_01_annCheck(index) != EXIT_SUCCESS )
return( EXIT_FAILURE ) ;
x[2] = * ann_01_genann_run(ann_01_ann[index], x) ;
return( EXIT_SUCCESS );
}
////-----------------------------------------------------------------------------
////
////-----------------------------------------------------------------------------
//int annPrintWeights(int index)
//{
// if ( annCheck(index) != EXIT_SUCCESS )
// return( EXIT_FAILURE ) ;
//
//
// printf("\n*** ANN index = %d\n", index) ;
// for ( int i = 0; i < ann[index]->total_weights; ++i )
// printf("*** w%d = %f\n", i, ann[index]->weight[i]) ;
//
// return( EXIT_SUCCESS );
//}
////-----------------------------------------------------------------------------
//// Run the index-th ANN k time on random input and return the number of error
////-----------------------------------------------------------------------------
//int annTest(int index, int k)
//{
// int x0; int x1; int y;
// double x[2];
// double xor_ex;
// int error = 0;
//
// if ( annCheck(index) != EXIT_SUCCESS )
// return( -1 ); // less than zero errors <==> the ANN isn't correctly created
//
// for (int i = 0; i < k; i++ )
// {
// x0 = rand() % 2; x[0] = (double)x0;
// x1 = rand() % 2; x[1] = (double)x1;
// y = x0 ^ x1 ;
//
// xor_ex = * genann_run(ann[index], x);
// if ( fabs(xor_ex - (double)y) > MAX_ERROR )
// {
// error++ ;
// printf("@@@ Error: ANN = %d, step = %d, x0 = %d, x1 = %d, y = %d, xor_ex = %f \n", index, i, x0, x1, y, xor_ex) ;
// }
// }
//
// if ( error )
// printf("@@@ ANN = %d: N� of errors = %d\n", index, error) ;
// else
// printf("*** ANN = %d: Test OK\n",index) ;
// return( error );
//}
//-----------------------------------------------------------------------------
//
//-----------------------------------------------------------------------------
void ann_01_annDestroy(void)
{
if ( ann_01_nANN == -1 )
return ;
for ( int index = 0; index < ann_01_nANN; index++ )
ann_01_genann_free(ann_01_ann[index]) ;
ann_01_nANN = -1 ;
}
void mainsystem::ann_01_main()
{
// datatype for channels
cleanData_xx_ann_xx_payload cleanData_xx_ann_xx_payload_var;
ann_xx_dataCollector_payload ann_xx_dataCollector_payload_var;
double x[ann_01_ANN_INPUTS + ann_01_ANN_OUTPUTS] ;
//int ann_01_index = 1;
if ( ann_01_annCreateAndSetWeights(ann_01_NUM_DEV) != EXIT_SUCCESS ){ // Create and init ANN
printf("Error Weights \n");
}
//implementation
HEPSY_S(ann_01_id) while(1)
{HEPSY_S(ann_01_id)
// content
cleanData_xx_ann_xx_payload_var = cleanData_01_ann_01_channel->read();
ann_xx_dataCollector_payload_var.dev = cleanData_xx_ann_xx_payload_var.dev;
ann_xx_dataCollector_payload_var.step = cleanData_xx_ann_xx_payload_var.step;
ann_xx_dataCollector_payload_var.ex_time = cleanData_xx_ann_xx_payload_var.ex_time;
ann_xx_dataCollector_payload_var.device_i = cleanData_xx_ann_xx_payload_var.device_i;
ann_xx_dataCollector_payload_var.device_v = cleanData_xx_ann_xx_payload_var.device_v;
ann_xx_dataCollector_payload_var.device_t = cleanData_xx_ann_xx_payload_var.device_t;
ann_xx_dataCollector_payload_var.device_r = cleanData_xx_ann_xx_payload_var.device_r;
x[0] = cleanData_xx_ann_xx_payload_var.x_0;
x[1] = cleanData_xx_ann_xx_payload_var.x_1;
x[2] = cleanData_xx_ann_xx_payload_var.x_2;
//u = cleanData_xx_ann_xx_payload_var.step;
ann_xx_dataCollector_payload_var.fault = cleanData_xx_ann_xx_payload_var.fault;
//RUN THE ANN...
// ### P R E D I C T (simple XOR)
// if ( annRun(index, x) != EXIT_SUCCESS ){
// printf("Step = %u Index = %d ANN error.\n", u, index) ;
// }else{
// device[index].fault = x[2] <= 0.5 ? 0 : 1 ;
// }
//u: cycle num
if ( ann_01_annRun(0, x) != EXIT_SUCCESS ){
printf("Step = %d Index = %d ANN error.\n", (int)ann_xx_dataCollector_payload_var.step, (int)ann_xx_dataCollector_payload_var.dev) ;
}else{
ann_xx_dataCollector_payload_var.fault = x[2] <= 0.5 ? 0 : 1 ;
}
ann_01_dataCollector_channel->write(ann_xx_dataCollector_payload_var);
HEPSY_P(ann_01_id)
}
}
// END
|
#ifndef __SC_VPI_MODULE_H__
#define __SC_VPI_MODULE_H__
#include <systemc.h>
#include <assert.h>
#include <vpi_user.h>
static int sc_vpi_module_value_change(p_cb_data cb_data);
#define sc_vpi_module_read_output_int(obj, name) \
{ \
s_vpi_value value_s; \
s_vpi_time vpi_time_s; \
\
value_s.format = vpiIntVal; \
\
vpi_time_s.type = vpiSimTime; \
vpi_time_s.high = 0; \
vpi_time_s.low = 0; \
\
std::string path = m_hdl_name; \
path = path + "." + name; \
vpiHandle handle = vpi_handle_by_name(path.c_str(), NULL); \
assert(handle != NULL); \
\
vpi_get_value(handle, &value_s); \
obj.write(value_s.value.integer); \
}
#define sc_vpi_module_write_input_int(obj, name) \
{ \
s_vpi_value value_s; \
s_vpi_time vpi_time_s; \
\
value_s.format = vpiIntVal; \
\
vpi_time_s.type = vpiSimTime; \
vpi_time_s.high = 0; \
vpi_time_s.low = 0; \
\
std::string path = m_hdl_name; \
path = path + "." + name; \
vpiHandle handle = vpi_handle_by_name(path.c_str(), NULL); \
assert(handle != NULL); \
\
value_s.value.integer = obj.read(); \
vpi_put_value(handle, &value_s, &vpi_time_s, vpiInertialDelay); \
}
class sc_vpi_module
{
public:
std::string m_hdl_name;
uint64_t m_last_time;
sc_signal<bool> m_stop;
sc_vpi_module(sc_module_name name) : m_hdl_name((std::string)name)
{
m_last_time = 0;
m_stop.write(false);
}
// Simulation control
void stopSimulation() { m_stop.write(true); }
bool isStopped() { return m_stop.read(); }
virtual void read_outputs(void) { }
virtual void write_inputs(void) { }
bool register_signal(const char *name)
{
static s_vpi_value value_s;
static s_vpi_time vpi_time;
s_cb_data cb_data_s;
vpi_time.high = 0;
vpi_time.low = 0;
vpi_time.type = vpiSimTime;
// For each I/O
std::string path = m_hdl_name;
path = path + "." + name;
vpiHandle handle = vpi_handle_by_name(path.c_str(), NULL);
if (!handle)
return false;
// Attach value change callbacks for outputs
cb_data_s.user_data = (PLI_BYTE8*)this;
cb_data_s.reason = cbValueChange;
cb_data_s.cb_rtn = sc_vpi_module_value_change;
cb_data_s.time = &vpi_time;
cb_data_s.value = &value_s;
value_s.format = vpiIntVal;
cb_data_s.obj = handle;
vpi_register_cb(&cb_data_s);
return true;
}
int value_change(void)
{
s_vpi_time vpi_time_s;
vpi_time_s.type = vpiSimTime;
vpi_time_s.high = 0;
vpi_time_s.low = 0;
// Outputs
read_outputs();
// Get current time
uint64_t time_value = 0;
s_vpi_time time_now;
time_now.type = vpiSimTime;
vpi_get_time (0, &time_now);
time_value = time_now.high;
time_value <<= 32;
time_value |= time_now.low;
// Update systemC TB
if(sc_pending_activity())
sc_start((int)(time_value-m_last_time),SC_NS);
m_last_time = time_value;
// Inputs
write_inputs();
if (isStopped())
vpi_sim_control(vpiFinish, 0);
return 0;
}
};
static int sc_vpi_module_value_change(p_cb_data cb_data)
{
sc_vpi_module *p = (sc_vpi_module*)cb_data->user_data;
return p->value_change();
}
#endif
|
// ================================================================
// NVDLA Open Source Project
//
// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
// NVDLA Open Hardware License; Check "LICENSE" which comes with
// this distribution for more information.
// ================================================================
// File Name: NV_NVDLA_glb_base.h
#ifndef _NV_NVDLA_GLB_BASE_H_
#define _NV_NVDLA_GLB_BASE_H_
#ifndef SC_INCLUDE_DYNAMIC_PROCESSES
#define SC_INCLUDE_DYNAMIC_PROCESSES
#endif
#include "NV_MSDEC_csb2xx_16m_secure_be_lvl_iface.h"
#include "nvdla_xx2csb_resp_iface.h"
#include "scsim_common.h"
#include <systemc.h>
#include <tlm.h>
#include <tlm_utils/multi_passthrough_initiator_socket.h>
#include <tlm_utils/multi_passthrough_target_socket.h>
SCSIM_NAMESPACE_START(cmod)
// Base SystemC class for module NV_NVDLA_glb
class NV_NVDLA_glb_base : public sc_module
{
public:
// Constructor
NV_NVDLA_glb_base(const sc_module_name name);
// Target Socket (unrecognized protocol: NV_MSDEC_csb2xx_16m_secure_be_lvl_t): csb2glb_req
tlm_utils::multi_passthrough_target_socket<NV_NVDLA_glb_base, 32, tlm::tlm_base_protocol_types> csb2glb_req;
virtual void csb2glb_req_b_transport(int ID, tlm::tlm_generic_payload& bp, sc_time& delay);
virtual void csb2glb_req_b_transport(int ID, NV_MSDEC_csb2xx_16m_secure_be_lvl_t* payload, sc_time& delay) = 0;
// Target Socket (unrecognized protocol: NV_MSDEC_csb2xx_16m_secure_be_lvl_t): csb2gec_req
tlm_utils::multi_passthrough_target_socket<NV_NVDLA_glb_base, 32, tlm::tlm_base_protocol_types> csb2gec_req;
virtual void csb2gec_req_b_transport(int ID, tlm::tlm_generic_payload& bp, sc_time& delay);
virtual void csb2gec_req_b_transport(int ID, NV_MSDEC_csb2xx_16m_secure_be_lvl_t* payload, sc_time& delay) = 0;
// Port has no flow: sdp2glb_done_intr
sc_vector< sc_in<bool> > sdp2glb_done_intr;
// Port has no flow: cdp2glb_done_intr
sc_vector< sc_in<bool> > cdp2glb_done_intr;
// Port has no flow: pdp2glb_done_intr
sc_vector< sc_in<bool> > pdp2glb_done_intr;
// Port has no flow: bdma2glb_done_intr
sc_vector< sc_in<bool> > bdma2glb_done_intr;
// Port has no flow: bdma2glb_done_intr
sc_vector< sc_in<bool> > rbk2glb_done_intr;
// Port has no flow: cdma_dat2glb_done_intr
sc_vector< sc_in<bool> > cdma_dat2glb_done_intr;
// Port has no flow: cdma_wt2glb_done_intr
sc_vector< sc_in<bool> > cdma_wt2glb_done_intr;
// Port has no flow: cacc2glb_done_intr
sc_vector< sc_in<bool> > cacc2glb_done_intr;
// Port has no flow: nvdla_fault_report_uncorrected
// sc_out<bool> nvdla_fault_report_uncorrected;
// Port has no flow: nvdla_fault_report_corrected
// sc_out<bool> nvdla_fault_report_corrected;
// Port has no flow: nvdla_intr
sc_out<bool> nvdla_intr;
// Initiator Socket (unrecognized protocol: nvdla_xx2csb_resp_t): glb2csb_resp
tlm::tlm_generic_payload glb2csb_resp_bp;
nvdla_xx2csb_resp_t glb2csb_resp_payload;
tlm_utils::multi_passthrough_initiator_socket<NV_NVDLA_glb_base, 32, tlm::tlm_base_protocol_types> glb2csb_resp;
virtual void glb2csb_resp_b_transport(nvdla_xx2csb_resp_t* payload, sc_time& delay);
// Initiator Socket (unrecognized protocol: nvdla_xx2csb_resp_t): gec2csb_resp
tlm::tlm_generic_payload gec2csb_resp_bp;
nvdla_xx2csb_resp_t gec2csb_resp_payload;
tlm_utils::multi_passthrough_initiator_socket<NV_NVDLA_glb_base, 32, tlm::tlm_base_protocol_types> gec2csb_resp;
virtual void gec2csb_resp_b_transport(nvdla_xx2csb_resp_t* payload, sc_time& delay);
// Destructor
virtual ~NV_NVDLA_glb_base() {}
};
// Constructor for base SystemC class for module NV_NVDLA_GLB
inline NV_NVDLA_glb_base::NV_NVDLA_glb_base(const sc_module_name name)
: sc_module(name),
csb2glb_req("csb2glb_req"),
csb2gec_req("csb2gec_req"),
sdp2glb_done_intr("sdp2glb_done_intr", 2),
cdp2glb_done_intr("cdp2glb_done_intr", 2),
pdp2glb_done_intr("pdp2glb_done_intr", 2),
bdma2glb_done_intr("bdma2glb_done_intr", 2),
rbk2glb_done_intr("rbk2glb_done_intr", 2),
cdma_dat2glb_done_intr("cdma_dat2glb_done_intr", 2),
cdma_wt2glb_done_intr("cdma_wt2glb_done_intr", 2),
cacc2glb_done_intr("cacc2glb_done_intr", 2),
// nvdla_fault_report_uncorrected("nvdla_fault_report_uncorrected"),
// nvdla_fault_report_corrected("nvdla_fault_report_corrected"),
nvdla_intr("nvdla_intr"),
glb2csb_resp_bp(),
glb2csb_resp("glb2csb_resp"),
gec2csb_resp_bp(),
gec2csb_resp("gec2csb_resp")
{
// Target Socket (unrecognized protocol: NV_MSDEC_csb2xx_16m_secure_be_lvl_t): csb2glb_req
this->csb2glb_req.register_b_transport(this, &NV_NVDLA_glb_base::csb2glb_req_b_transport);
// Target Socket (unrecognized protocol: NV_MSDEC_csb2xx_16m_secure_be_lvl_t): csb2gec_req
this->csb2gec_req.register_b_transport(this, &NV_NVDLA_glb_base::csb2gec_req_b_transport);
}
inline void
NV_NVDLA_glb_base::csb2glb_req_b_transport(int ID, tlm::tlm_generic_payload& bp, sc_time& delay)
{
NV_MSDEC_csb2xx_16m_secure_be_lvl_t* payload = (NV_MSDEC_csb2xx_16m_secure_be_lvl_t*) bp.get_data_ptr();
csb2glb_req_b_transport(ID, payload, delay);
}
inline void
NV_NVDLA_glb_base::csb2gec_req_b_transport(int ID, tlm::tlm_generic_payload& bp, sc_time& delay)
{
NV_MSDEC_csb2xx_16m_secure_be_lvl_t* payload = (NV_MSDEC_csb2xx_16m_secure_be_lvl_t*) bp.get_data_ptr();
csb2gec_req_b_transport(ID, payload, delay);
}
inline void
NV_NVDLA_glb_base::glb2csb_resp_b_transport(nvdla_xx2csb_resp_t* payload, sc_time& delay)
{
glb2csb_resp_bp.set_data_ptr((unsigned char*) payload);
glb2csb_resp->b_transport(glb2csb_resp_bp, delay);
}
inline void
NV_NVDLA_glb_base::gec2csb_resp_b_transport(nvdla_xx2csb_resp_t* payload, sc_time& delay)
{
gec2csb_resp_bp.set_data_ptr((unsigned char*) payload);
gec2csb_resp->b_transport(gec2csb_resp_bp, delay);
}
SCSIM_NAMESPACE_END()
#endif
|
// ================================================================
// NVDLA Open Source Project
//
// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
// NVDLA Open Hardware License; Check "LICENSE" which comes with
// this distribution for more information.
// ================================================================
// File Name: NV_NVDLA_glb_base.h
#ifndef _NV_NVDLA_GLB_BASE_H_
#define _NV_NVDLA_GLB_BASE_H_
#ifndef SC_INCLUDE_DYNAMIC_PROCESSES
#define SC_INCLUDE_DYNAMIC_PROCESSES
#endif
#include "NV_MSDEC_csb2xx_16m_secure_be_lvl_iface.h"
#include "nvdla_xx2csb_resp_iface.h"
#include "scsim_common.h"
#include <systemc.h>
#include <tlm.h>
#include <tlm_utils/multi_passthrough_initiator_socket.h>
#include <tlm_utils/multi_passthrough_target_socket.h>
SCSIM_NAMESPACE_START(cmod)
// Base SystemC class for module NV_NVDLA_glb
class NV_NVDLA_glb_base : public sc_module
{
public:
// Constructor
NV_NVDLA_glb_base(const sc_module_name name);
// Target Socket (unrecognized protocol: NV_MSDEC_csb2xx_16m_secure_be_lvl_t): csb2glb_req
tlm_utils::multi_passthrough_target_socket<NV_NVDLA_glb_base, 32, tlm::tlm_base_protocol_types> csb2glb_req;
virtual void csb2glb_req_b_transport(int ID, tlm::tlm_generic_payload& bp, sc_time& delay);
virtual void csb2glb_req_b_transport(int ID, NV_MSDEC_csb2xx_16m_secure_be_lvl_t* payload, sc_time& delay) = 0;
// Target Socket (unrecognized protocol: NV_MSDEC_csb2xx_16m_secure_be_lvl_t): csb2gec_req
tlm_utils::multi_passthrough_target_socket<NV_NVDLA_glb_base, 32, tlm::tlm_base_protocol_types> csb2gec_req;
virtual void csb2gec_req_b_transport(int ID, tlm::tlm_generic_payload& bp, sc_time& delay);
virtual void csb2gec_req_b_transport(int ID, NV_MSDEC_csb2xx_16m_secure_be_lvl_t* payload, sc_time& delay) = 0;
// Port has no flow: sdp2glb_done_intr
sc_vector< sc_in<bool> > sdp2glb_done_intr;
// Port has no flow: cdp2glb_done_intr
sc_vector< sc_in<bool> > cdp2glb_done_intr;
// Port has no flow: pdp2glb_done_intr
sc_vector< sc_in<bool> > pdp2glb_done_intr;
// Port has no flow: bdma2glb_done_intr
sc_vector< sc_in<bool> > bdma2glb_done_intr;
// Port has no flow: bdma2glb_done_intr
sc_vector< sc_in<bool> > rbk2glb_done_intr;
// Port has no flow: cdma_dat2glb_done_intr
sc_vector< sc_in<bool> > cdma_dat2glb_done_intr;
// Port has no flow: cdma_wt2glb_done_intr
sc_vector< sc_in<bool> > cdma_wt2glb_done_intr;
// Port has no flow: cacc2glb_done_intr
sc_vector< sc_in<bool> > cacc2glb_done_intr;
// Port has no flow: nvdla_fault_report_uncorrected
// sc_out<bool> nvdla_fault_report_uncorrected;
// Port has no flow: nvdla_fault_report_corrected
// sc_out<bool> nvdla_fault_report_corrected;
// Port has no flow: nvdla_intr
sc_out<bool> nvdla_intr;
// Initiator Socket (unrecognized protocol: nvdla_xx2csb_resp_t): glb2csb_resp
tlm::tlm_generic_payload glb2csb_resp_bp;
nvdla_xx2csb_resp_t glb2csb_resp_payload;
tlm_utils::multi_passthrough_initiator_socket<NV_NVDLA_glb_base, 32, tlm::tlm_base_protocol_types> glb2csb_resp;
virtual void glb2csb_resp_b_transport(nvdla_xx2csb_resp_t* payload, sc_time& delay);
// Initiator Socket (unrecognized protocol: nvdla_xx2csb_resp_t): gec2csb_resp
tlm::tlm_generic_payload gec2csb_resp_bp;
nvdla_xx2csb_resp_t gec2csb_resp_payload;
tlm_utils::multi_passthrough_initiator_socket<NV_NVDLA_glb_base, 32, tlm::tlm_base_protocol_types> gec2csb_resp;
virtual void gec2csb_resp_b_transport(nvdla_xx2csb_resp_t* payload, sc_time& delay);
// Destructor
virtual ~NV_NVDLA_glb_base() {}
};
// Constructor for base SystemC class for module NV_NVDLA_GLB
inline NV_NVDLA_glb_base::NV_NVDLA_glb_base(const sc_module_name name)
: sc_module(name),
csb2glb_req("csb2glb_req"),
csb2gec_req("csb2gec_req"),
sdp2glb_done_intr("sdp2glb_done_intr", 2),
cdp2glb_done_intr("cdp2glb_done_intr", 2),
pdp2glb_done_intr("pdp2glb_done_intr", 2),
bdma2glb_done_intr("bdma2glb_done_intr", 2),
rbk2glb_done_intr("rbk2glb_done_intr", 2),
cdma_dat2glb_done_intr("cdma_dat2glb_done_intr", 2),
cdma_wt2glb_done_intr("cdma_wt2glb_done_intr", 2),
cacc2glb_done_intr("cacc2glb_done_intr", 2),
// nvdla_fault_report_uncorrected("nvdla_fault_report_uncorrected"),
// nvdla_fault_report_corrected("nvdla_fault_report_corrected"),
nvdla_intr("nvdla_intr"),
glb2csb_resp_bp(),
glb2csb_resp("glb2csb_resp"),
gec2csb_resp_bp(),
gec2csb_resp("gec2csb_resp")
{
// Target Socket (unrecognized protocol: NV_MSDEC_csb2xx_16m_secure_be_lvl_t): csb2glb_req
this->csb2glb_req.register_b_transport(this, &NV_NVDLA_glb_base::csb2glb_req_b_transport);
// Target Socket (unrecognized protocol: NV_MSDEC_csb2xx_16m_secure_be_lvl_t): csb2gec_req
this->csb2gec_req.register_b_transport(this, &NV_NVDLA_glb_base::csb2gec_req_b_transport);
}
inline void
NV_NVDLA_glb_base::csb2glb_req_b_transport(int ID, tlm::tlm_generic_payload& bp, sc_time& delay)
{
NV_MSDEC_csb2xx_16m_secure_be_lvl_t* payload = (NV_MSDEC_csb2xx_16m_secure_be_lvl_t*) bp.get_data_ptr();
csb2glb_req_b_transport(ID, payload, delay);
}
inline void
NV_NVDLA_glb_base::csb2gec_req_b_transport(int ID, tlm::tlm_generic_payload& bp, sc_time& delay)
{
NV_MSDEC_csb2xx_16m_secure_be_lvl_t* payload = (NV_MSDEC_csb2xx_16m_secure_be_lvl_t*) bp.get_data_ptr();
csb2gec_req_b_transport(ID, payload, delay);
}
inline void
NV_NVDLA_glb_base::glb2csb_resp_b_transport(nvdla_xx2csb_resp_t* payload, sc_time& delay)
{
glb2csb_resp_bp.set_data_ptr((unsigned char*) payload);
glb2csb_resp->b_transport(glb2csb_resp_bp, delay);
}
inline void
NV_NVDLA_glb_base::gec2csb_resp_b_transport(nvdla_xx2csb_resp_t* payload, sc_time& delay)
{
gec2csb_resp_bp.set_data_ptr((unsigned char*) payload);
gec2csb_resp->b_transport(gec2csb_resp_bp, delay);
}
SCSIM_NAMESPACE_END()
#endif
|
/****************************************************************************
*
* Copyright (c) 2017, Cadence Design Systems. All Rights Reserved.
*
* This file contains confidential information that may not be
* distributed under any circumstances without the written permision
* of Cadence Design Systems.
*
****************************************************************************/
#ifndef _DUT_SC_FOREIGN_INCLUDED_
#define _DUT_SC_FOREIGN_INCLUDED_
#include <systemc.h>
// Declaration of wrapper with RTL level ports
struct dut : public ncsc_foreign_module
{
public:
sc_in< bool > clk;
sc_in< bool > rst;
sc_out< bool > din_busy;
sc_in< bool > din_vld;
sc_in< sc_uint< 8 > > din_data;
sc_in< bool > dout_busy;
sc_out< bool > dout_vld;
sc_out< sc_uint< 11 > > dout_data;
const char* hdl_name() const { return "dut"; }
dut( sc_module_name name )
: ncsc_foreign_module(name)
,clk("clk")
,rst("rst")
,din_busy("din_busy")
,din_vld("din_vld")
,din_data("din_data")
,dout_busy("dout_busy")
,dout_vld("dout_vld")
,dout_data("dout_data")
{
}
};
#endif /* _DUT_SC_FOREIGN_INCLUDED_ */
|
/****************************************************************************
*
* Copyright (c) 2017, Cadence Design Systems. All Rights Reserved.
*
* This file contains confidential information that may not be
* distributed under any circumstances without the written permision
* of Cadence Design Systems.
*
****************************************************************************/
#ifndef _DUT_SC_FOREIGN_INCLUDED_
#define _DUT_SC_FOREIGN_INCLUDED_
#include <systemc.h>
// Declaration of wrapper with RTL level ports
struct dut : public ncsc_foreign_module
{
public:
sc_in< bool > clk;
sc_in< bool > rst;
sc_out< bool > din_busy;
sc_in< bool > din_vld;
sc_in< sc_uint< 8 > > din_data;
sc_in< bool > dout_busy;
sc_out< bool > dout_vld;
sc_out< sc_uint< 11 > > dout_data;
const char* hdl_name() const { return "dut"; }
dut( sc_module_name name )
: ncsc_foreign_module(name)
,clk("clk")
,rst("rst")
,din_busy("din_busy")
,din_vld("din_vld")
,din_data("din_data")
,dout_busy("dout_busy")
,dout_vld("dout_vld")
,dout_data("dout_data")
{
}
};
#endif /* _DUT_SC_FOREIGN_INCLUDED_ */
|
// ================================================================
// NVDLA Open Source Project
//
// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
// NVDLA Open Hardware License; Check "LICENSE" which comes with
// this distribution for more information.
// ================================================================
// File Name: NvdlaCoreDummy.h
#ifndef _NVDLACOREDUMMY_H_
#define _NVDLACOREDUMMY_H_
#define SC_INCLUDE_DYNAMIC_PROCESSES
#include <systemc.h>
#include <tlm.h>
#include "tlm_utils/multi_passthrough_initiator_socket.h"
#include "tlm_utils/multi_passthrough_target_socket.h"
#include "scsim_common.h"
#define NVDLA_AXI_ADAPTOR_OUT_STANDING_REQUEST_NUM 1024
SCSIM_NAMESPACE_START(clib)
// clib class forward declaration
SCSIM_NAMESPACE_END()
SCSIM_NAMESPACE_START(cmod)
class NvdlaCoreDummy : public sc_module {
public:
SC_HAS_PROCESS(NvdlaCoreDummy);
NvdlaCoreDummy( sc_module_name module_name );
~NvdlaCoreDummy();
// Initiator sockets
// Initiator Socket (unrecognized protocol: nvdla_xx2csb_resp_t): cvif2csb_resp
tlm_utils::multi_passthrough_initiator_socket<NvdlaCoreDummy, 32, tlm::tlm_base_protocol_types> cvif2csb_resp;
// Initiator Socket (unrecognized protocol: nvdla_xx2csb_resp_t): mcif2csb_resp
tlm_utils::multi_passthrough_initiator_socket<NvdlaCoreDummy, 32, tlm::tlm_base_protocol_types> mcif2csb_resp;
// Target sockets
// Target Socket (unrecognized protocol: NV_MSDEC_csb2xx_16m_secure_be_lvl_t): csb2cvif_req
tlm_utils::multi_passthrough_target_socket<NvdlaCoreDummy, 32, tlm::tlm_base_protocol_types> csb2cvif_req;
virtual void csb2cvif_req_b_transport(int ID, tlm::tlm_generic_payload& bp, sc_time& delay);
// Target Socket (unrecognized protocol: NV_MSDEC_csb2xx_16m_secure_be_lvl_t): csb2mcif_req
tlm_utils::multi_passthrough_target_socket<NvdlaCoreDummy, 32, tlm::tlm_base_protocol_types> csb2mcif_req;
virtual void csb2mcif_req_b_transport(int ID, tlm::tlm_generic_payload& bp, sc_time& delay);
// sc_in, sc_out, sc_inout
};
SCSIM_NAMESPACE_END()
extern "C" scsim::cmod::NvdlaCoreDummy * NvdlaCoreDummyCon(sc_module_name module_name);
#endif
|
/*****************************************************************************
Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
more contributor license agreements. See the NOTICE file distributed
with this work for additional information regarding copyright ownership.
Accellera licenses this file to you under the Apache License, Version 2.0
(the "License"); you may not use this file except in compliance with the
License. You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
implied. See the License for the specific language governing
permissions and limitations under the License.
*****************************************************************************/
/*****************************************************************************
systemc.h - Top-level include file for the SystemC library with usings.
Original Author: Stan Y. Liao, Synopsys, Inc.
*****************************************************************************/
/*****************************************************************************
MODIFICATION LOG - modifiers, enter your name, affiliation, date and
changes you are making here.
Name, Affiliation, Date: Andy Goodrich, Forte Design Systems, 31 Mar 2005
Description of Modification: Changes for namespace support.
*****************************************************************************/
#ifndef SYSTEMC_H
#define SYSTEMC_H
// INCLUDE SYSTEM (std) DEFINITIONS:
#include <cassert>
#include <climits>
#include <cmath> // math.h?
#include <cstddef>
#include <cstdint>
#include <cstdio>
#include <cstdlib>
#include <cstring>
#include <exception>
#include <fstream>
#include <iostream>
#include <memory>
#include <string>
#include <typeinfo>
#include <utility>
#include <vector>
// USINGS FOR I/O STREAM SUPPORT:
using std::ios;
using std::streambuf;
using std::streampos;
using std::streamsize;
using std::iostream;
using std::istream;
using std::ostream;
using std::cin;
using std::cout;
using std::cerr;
using std::endl;
using std::flush;
using std::dec;
using std::hex;
using std::oct;
using std::noshowbase;
using std::showbase;
using std::fstream;
using std::ifstream;
using std::ofstream;
// from <cstdio>:
using std::size_t;
using std::FILE;
using std::fpos_t;
using std::fclose;
using std::clearerr;
using std::remove;
using std::rename;
using std::tmpfile;
using std::tmpnam;
using std::fflush;
using std::fopen;
using std::freopen;
using std::setbuf;
using std::setvbuf;
using std::fprintf;
using std::fscanf;
using std::printf;
using std::scanf;
using std::sprintf;
using std::sscanf;
using std::vfprintf;
using std::vprintf;
using std::vsprintf;
using std::fgetc;
using std::fgets;
using std::fputc;
using std::fputs;
using std::getc;
using std::getchar;
using std::putc;
using std::putchar;
using std::puts;
using std::ungetc;
using std::fread;
using std::fwrite;
using std::fgetpos;
using std::fseek;
using std::fsetpos;
using std::ftell;
using std::rewind;
using std::feof;
using std::ferror;
using std::perror;
// from <cstdlib>:
using std::div_t;
using std::ldiv_t;
using std::atof;
using std::atoi;
using std::atol;
using std::strtod;
using std::strtol;
using std::strtoul;
using std::rand;
using std::srand;
using std::calloc;
using std::free;
using std::malloc;
using std::realloc;
using std::abort;
using std::atexit;
using std::exit;
using std::getenv;
using std::system;
using std::bsearch;
using std::qsort;
using std::abs;
using std::div;
using std::labs;
using std::ldiv;
using std::mblen;
using std::mbtowc;
using std::mbstowcs;
#if !defined(__CYGWIN__) && !defined(__CYGWIN32)
using std::wctomb;
using std::wcstombs;
#endif
// from <cstring>:
using std::memcpy;
using std::memmove;
using std::strcpy;
using std::strncpy;
using std::strcat;
using std::strncat;
using std::memcmp;
using std::strcmp;
using std::strcoll;
using std::strncmp;
using std::strxfrm;
using std::memchr;
using std::strchr;
using std::strcspn;
using std::strpbrk;
using std::strrchr;
using std::strspn;
using std::strstr;
using std::strtok;
using std::memset;
using std::strerror;
using std::strlen;
// INCLUDE SYSTEMC DEFINITIONS for sc_dt AND sc_core NAMESPACES:
#include "systemc"
// USINGS FOR THE sc_dt NAMESPACE:
using sc_dt::SC_BIN;
using sc_dt::SC_BIN_SM;
using sc_dt::SC_BIN_US;
using sc_dt::SC_CSD;
using sc_dt::SC_DEC;
using sc_dt::SC_HEX;
using sc_dt::SC_HEX_SM;
using sc_dt::SC_HEX_US;
using sc_dt::SC_LOGIC_0;
using sc_dt::SC_LOGIC_1;
using sc_dt::SC_LOGIC_X;
using sc_dt::SC_LOGIC_Z;
using sc_dt::SC_NOBASE;
using sc_dt::SC_OCT;
using sc_dt::SC_OCT_SM;
using sc_dt::SC_OCT_US;
using sc_dt::int64;
using sc_dt::sc_abs;
using sc_dt::sc_bigint;
using sc_dt::sc_biguint;
using sc_dt::sc_bit;
using sc_dt::sc_bv;
using sc_dt::sc_bv_base;
using sc_dt::sc_digit;
using sc_dt::sc_int;
using sc_dt::sc_int_base;
using sc_dt::sc_io_show_base;
using sc_dt::sc_length_context;
using sc_dt::sc_length_param;
using sc_dt::sc_logic;
using sc_dt::sc_lv;
using sc_dt::sc_lv_base;
using sc_dt::sc_max;
using sc_dt::sc_min;
using sc_dt::sc_numrep;
using sc_dt::sc_signed;
using sc_dt::sc_uint;
using sc_dt::sc_uint_base;
using sc_dt::sc_unsigned;
using sc_dt::uint64;
// #ifdef SC_DT_DEPRECATED
using sc_dt::sc_logic_0;
using sc_dt::sc_logic_1;
using sc_dt::sc_logic_Z;
using sc_dt::sc_logic_X;
// #endif
#ifdef SC_INCLUDE_FX
using sc_dt::sc_fxnum;
using sc_dt::sc_fxnum_bitref;
using sc_dt::sc_fxnum_fast;
using sc_dt::sc_fix;
using sc_dt::sc_fix_fast;
using sc_dt::sc_ufix;
using sc_dt::sc_ufix_fast;
using sc_dt::sc_fixed;
using sc_dt::sc_fixed_fast;
using sc_dt::sc_ufixed;
using sc_dt::sc_ufixed_fast;
using sc_dt::sc_fxval;
using sc_dt::sc_fxval_fast;
using sc_dt::sc_fxcast_switch;
using sc_dt::sc_fxcast_context;
using sc_dt::sc_fxtype_params;
using sc_dt::sc_fxtype_context;
using sc_dt::sc_q_mode;
using sc_dt::SC_RND;
using sc_dt::SC_RND_ZERO;
using sc_dt::SC_RND_MIN_INF;
using sc_dt::SC_RND_INF;
using sc_dt::SC_RND_CONV;
using sc_dt::SC_TRN;
using sc_dt::SC_TRN_ZERO;
using sc_dt::sc_o_mode;
using sc_dt::SC_SAT;
using sc_dt::SC_SAT_ZERO;
using sc_dt::SC_SAT_SYM;
using sc_dt::SC_WRAP;
using sc_dt::SC_WRAP_SM;
using sc_dt::sc_switch;
using sc_dt::SC_OFF;
using sc_dt::SC_ON;
using sc_dt::sc_fmt;
using sc_dt::SC_F;
using sc_dt::SC_E;
using sc_dt::sc_context_begin;
using sc_dt::SC_NOW;
using sc_dt::SC_LATER;
#endif // SC_INCLUDE_FX
// USINGS FOR sc_core:
//
// The explicit using for ::sc_core::wait is to remove an ambiguity with
// the constructor for the system's union wait on Unix and Linux.
// It is generally advisable to explicitly select the SystemC wait
// functions using ::sc_core::wait(...).
using namespace sc_core;
using ::sc_core::wait;
typedef ::std::string sc_string;
#endif // SYSTEMC_H
|
#ifndef __COMMON_H__
#define __COMMON_H__
#include <list>
#include <sstream>
#include "Request.h"
#include "systemc.h"
std::ostream& operator<<(std::ostream &os, const ramulator::Request::Type &type);
// This macro is used to locate the code position.
#define HERE do {std::cout <<"File: " << __FILE__ << " Line: " << __LINE__ << std::endl;} while(0)
// ----------------------------------------------------------------------------
// The burst operation is decoded in the memory wrapper and
// it provides a simple and easy-to-use interface to the processing elements.
// Although the data between the memory wrapper and the pe is supposed to
// be transmitted word by word, now we will not send the burst data
// untill the whole burst transmission from the ramulator is
// detected while the real system may does the transmission gradually.
// Basically the difference is where we are going to
// buffer the partital data in the system. Since
// buffering in memory controller makes the
// whole system much more convenient and it is precise enough to simulate the
// data transmission, we adopt it in the simulator.
// ----------------------------------------------------------------------------
struct BurstOp{
public:
bool valid;
ramulator::Request::Type type;
int portIdx;
long burstIdx;
int peIdx;
long addr;
int length;
// Each burst operation consists of multiple basic memory requests/responses
// and the memory opid and address will be stored in the vector.
std::vector<long> reqVec;
std::vector<long> addrVec;
long departPeTime;
long arriveMemTime;
long departMemTime;
long arrivePeTime;
void convertToReq(std::list<ramulator::Request> &reqQueue);
template<typename T>
void burstReqToBuffer(std::list<T> &buffer){
char* p = (char*) malloc(sizeof(T));
if(length%sizeof(T) != 0){
HERE;
std::cout << "The burst request length is not aligned to the buffer type.";
std::cout << std::endl;
exit(EXIT_FAILURE);
}
for(int i = 0; i < length;){
for(size_t j = 0; j < sizeof(T); j++){
*(p+j) = data[i];
i++;
}
buffer.push_back(*((T*)p));
}
delete p;
}
// This fucntion copies the data from local buffer to the write burst request data section.
template<typename T>
void bufferToBurstReq(std::list<T> &buffer){
T *p = (T*)malloc(sizeof(T));
int size = length/sizeof(T);
for(int i = 0; i < size; i++){
*p = buffer.front();
buffer.pop_front();
for(int j = 0; j < (int)sizeof(T); j++){
data.push_back(*((char*)p+j));
}
}
}
template<typename T>
T removeFrontData(){
T t;
T* p = &t;
for(int i = 0; i < (int)sizeof(T); i++){
auto it = data.begin();
*((char*)p + i) = (*it);
data.erase(it);
}
return t;
}
bool isDataAvail(){
return !data.empty();
};
// Overloaded operators that are requred to support sc_in/out port
void operator=(const BurstOp &op);
bool operator==(const BurstOp &op) const;
friend void sc_trace(sc_trace_file *tf, const BurstOp &op, const std::string &name);
friend std::ostream& operator<<(std::ostream &os, const BurstOp &op);
int getReqNum() const;
void updateReqVec();
void updateAddrVec();
void ramToReq(const std::vector<char> &ramData);
void reqToRam(std::vector<char> &ramData);
// Constructors
BurstOp(ramulator::Request::Type _type,
int _peIdx,
int _portIdx,
long _burstIdx,
long _addr,
int _length);
BurstOp(bool _valid = false);
private:
// Attached data.
std::vector<char> data;
long getAlignedAddr() const;
int getOffset() const;
};
class GL{
public:
// Application parameters
static int vecLen;
static int bufferLen;
static long vecMemAddr0;
static long vecMemAddr1;
static long vecMemAddr2;
static long resultMemAddr;
static int baseLen;
static int burstLen;
static int burstAddrWidth;
static int portNum;
static int logon;
// Gloabl container that stores all the bursts created in the bfs.
// When the a burst is no longer used, the allocated memory will be
// released and the corresponding element in the vector will be set
// to be NULL.
static std::vector<BurstOp*> bursts;
// A long request will be split into base length of
// bursts such that the burst will not be overflow
// the buffer and block shorter bursts coming afterwards.
static long getReqIdx();
static long getBurstIdx();
static void cfgBfsParam(const std::string &cfgFileName);
private:
static long reqIdx;
static long burstIdx;
static int getBurstAddrWidth();
};
#endif
|
/* Copyright 2017 Columbia University, SLD Group */
//
// globals.h - Robert Margelli
// This file several defines and constants: number of registers, data width, opcodes etc.
//
#ifndef GLOBALS_H
#define GLOBALS_H
#include "systemc.h"
// Miscellanous sizes. Most of these can be changed to obtain new architectures.
#define XLEN 32 // Register width. 32 or 64. Currently only 32 is supported.
#define REG_NUM 32 // Number of registers in regfile (x0-x31) // CONST
#define REG_ADDR 5 // Number of reg file address lines // CONST
#define IMEM_SIZE 2048 // Size of instruction memory
#define DMEM_SIZE 2048 // Size of data memory
#define DATA_SIZE 32 // Size of data in DMEM // CONST
#define PC_LEN 32 // Width of PC register
#define ALUOP_SIZE 5 // Size of aluop signal.
#define ALUSRC_SIZE 2 // Size of alusrc signal.
#define BYTE 8 // 8-bits.
#define ZIMM_SIZE 5 // Bit-length of zimm field in CSRRWI, CSRRSI, CSRRCI
#define SHAMT 5 // Number of bits used for the shift value in shift operations.
// Values for CSR and traps
#define LOG2_NUM_CAUSES 3 // Log2 of number of trap causes
#define CSR_NUM 11 // Number of CSR registers (including Performance Counters).
#define CSR_IDX_LEN 4 // Log2 of CSR_NUM // TODO: this should be rewritten into something like log2(CSR_NUM)
#define PRF_CNT_NUM 1 // Number of Performance Counters.
#define CSR_ADDR 12 // CSRs are on a 12-bit addressing space.
#define LOG2_CSR_OP_NUM 2 // Log2 of number of operations on CSR.
#define CSR_OP_WR 1 // CSR write operation.
#define CSR_OP_SET 2 // CSR set operation.
#define CSR_OP_CLR 3 // CSR clear operation.
#define CSR_OP_NULL 0 // Not a CSR operation.
// Instruction fields sizes. All contant.
#define INSN_LEN 32
#define OPCODE_SIZE 5 // Note: in reality opcodes are on 7 bits but bits [1:0] are statically at '1'. This gives us a saving of approximately 300 in 'Total Area' of the fedec stage.
#define FUNCT7_SIZE 7
#define FUNCT3_SIZE 3
#define RS1_SIZE 5
#define RS2_SIZE 5
#define RD_SIZE 5
#define IMM_ITYPE 12 // imm[11:0]
#define IMM_STYPE1 7 // imm[11:5]
#define IMM_STYPE2 5 // imm[4:0]
#define IMM_SBTYPE1 7 // imm[12|10:5]
#define IMM_SBTYPE2 5 // imm[4:1|11]
#define IMM_UTYPE 20 // imm[31:12]
#define IMM_UJTYPE 20 // imm[20|10:1|11|19:12]
/* Supported instructions 45+8=53 :
* add, sll, slt, sltu, xor, srl, or, and, sub, sra,
* addi, slti, sltiu, xori, ori, andi, slli, srli, srai,
* sb, sh, sw, lb, lh, lw, lbu, lhu,
* beq, bne, blt, bge, bltu, bgeu,
* lui, auipc, jalr, jal,
* ebreak, ecall, csrrw, csrrs, csrrc, csrrwi, csrrsi, csrrci,
* mul, mulh, mulhsu, mulhu, div, divu, rem, remu
*
* i.e. all RV32I except {FENCE, FENCE.I} and all RV32M
* NB. ETH/Bologna's RI5CY does not support FENCE and FENCE.I
*/
/* Opcodes as integers. For control word generation switch case. */
#define OPC_ADD 12 // Original value is 51, but we trim the opcode's LSBs which are statically at 2'b11 for all instructions.
#define OPC_SLL OPC_ADD
#define OPC_SLT OPC_ADD
#define OPC_SLTU OPC_ADD
#define OPC_XOR OPC_ADD
#define OPC_SRL OPC_ADD
#define OPC_OR OPC_ADD
#define OPC_AND OPC_ADD
#define OPC_SUB OPC_ADD
#define OPC_SRA OPC_ADD
#define OPC_MUL OPC_ADD
#define OPC_MULH OPC_ADD
#define OPC_MULHSU OPC_ADD
#define OPC_MULHU OPC_ADD
#define OPC_DIV OPC_ADD
#define OPC_DIVU OPC_ADD
#define OPC_REM OPC_ADD
#define OPC_REMU OPC_ADD
#define OPC_ADDI 4 // Original value is 19, but we trim the opcode's LSBs which are statically at 2'b11 for all instructions.
#define OPC_SLTI OPC_ADDI
#define OPC_SLTIU OPC_ADDI
#define OPC_XORI OPC_ADDI
#define OPC_ORI OPC_ADDI
#define OPC_ANDI OPC_ADDI
#define OPC_SLLI OPC_ADDI
#define OPC_SRLI OPC_ADDI
#define OPC_SRAI OPC_ADDI
#define OPC_SB 8 // Original value is 35, but we trim the opcode's LSBs which are statically at 2'b11 for all instructions.
#define OPC_SH OPC_SB
#define OPC_SW OPC_SB
#define OPC_LB 0 // Original value is 3, but we trim the opcode's LSBs which are statically at 2'b11 for all instructions.
#define OPC_LH OPC_LB
#define OPC_LW OPC_LB
#define OPC_LBU OPC_LB
#define OPC_LHU OPC_LB
#define OPC_BEQ 24 // Original value is 99, but we trim the opcode's LSBs which are statically at 2'b11 for all instructions.
#define OPC_BNE OPC_BEQ
#define OPC_BLT OPC_BEQ
#define OPC_BGE OPC_BEQ
#define OPC_BLTU OPC_BEQ
#define OPC_BGEU OPC_BEQ
#define OPC_LUI 13 // Original value is 55, but we trim the opcode's LSBs which are statically at 2'b11 for all instructions.
#define OPC_AUIPC 5 // Original value is 23, but we trim the opcode's LSBs which are statically at 2'b11 for all instructions.
#define OPC_JAL 27 // Original value is 111, but we trim the opcode's LSBs which are statically at 2'b11 for all instructions.
#define OPC_JALR 25 // Original value is 103, but we trim the opcode's LSBs which are statically at 2'b11 for all instructions.
#define OPC_SYSTEM 28 // Original value is 115, but we trim the opcode's LSBs which are statically at 2'b11 for all instructions.
#define OPC_EBREAK OPC_SYSTEM
#define OPC_ECALL OPC_SYSTEM
#define OPC_CSRRW OPC_SYSTEM
#define OPC_CSRRS OPC_SYSTEM
#define OPC_CSRRC OPC_SYSTEM
#define OPC_CSRRWI OPC_SYSTEM
#define OPC_CSRRSI OPC_SYSTEM
#define OPC_CSRRCI OPC_SYSTEM
/* Funct3 as integers. For control word generation switch case. */
#define FUNCT3_ADD 0
#define FUNCT3_SLL 1
#define FUNCT3_SLT 2
#define FUNCT3_SLTU 3
#define FUNCT3_XOR 4
#define FUNCT3_SRL 5
#define FUNCT3_OR 6
#define FUNCT3_AND 7
#define FUNCT3_SUB 0
#define FUNCT3_SRA 5
#define FUNCT3_MUL 0
#define FUNCT3_MULH 1
#define FUNCT3_MULHSU 2
#define FUNCT3_MULHU 3
#define FUNCT3_DIV 4
#define FUNCT3_DIVU 5
#define FUNCT3_REM 6
#define FUNCT3_REMU 7
#define FUNCT3_ADDI 0
#define FUNCT3_SLTI 2
#define FUNCT3_SLTIU 3
#define FUNCT3_XORI 4
#define FUNCT3_ORI 6
#define FUNCT3_ANDI 7
#define FUNCT3_SLLI 1
#define FUNCT3_SRLI 5
#define FUNCT3_SRAI 5
#define FUNCT3_SB 0
#define FUNCT3_SH 1
#define FUNCT3_SW 2
#define FUNCT3_LB 0
#define FUNCT3_LH 1
#define FUNCT3_LW 2
#define FUNCT3_LBU 4
#define FUNCT3_LHU 5
#define FUNCT3_BEQ 0
#define FUNCT3_BNE 1
#define FUNCT3_BLT 4
#define FUNCT3_BGE 5
#define FUNCT3_BLTU 6
#define FUNCT3_BGEU 7
#define FUNCT3_JALR 0
#define FUNCT3_EBREAK 0
#define FUNCT3_ECALL 0
#define FUNCT3_CSRRW 1
#define FUNCT3_CSRRS 2
#define FUNCT3_CSRRC 3
#define FUNCT3_CSRRWI 5
#define FUNCT3_CSRRSI 6
#define FUNCT3_CSRRCI 7
/* Funct7 as integers. For control word generation switch case. */
#define FUNCT7_ADD 0
#define FUNCT7_SLL FUNCT7_ADD
#define FUNCT7_SLT FUNCT7_ADD
#define FUNCT7_SLTU FUNCT7_ADD
#define FUNCT7_XOR FUNCT7_ADD
#define FUNCT7_SRL FUNCT7_ADD
#define FUNCT7_OR FUNCT7_ADD
#define FUNCT7_AND FUNCT7_ADD
#define FUNCT7_SUB 32
#define FUNCT7_SRA FUNCT7_SUB
#define FUNCT7_MUL 1
#define FUNCT7_MULH FUNCT7_MUL
#define FUNCT7_MULHSU FUNCT7_MUL
#define FUNCT7_MULHU FUNCT7_MUL
#define FUNCT7_DIV FUNCT7_MUL
#define FUNCT7_DIVU FUNCT7_MUL
#define FUNCT7_REM FUNCT7_MUL
#define FUNCT7_REMU FUNCT7_MUL
#define FUNCT7_SLLI 0
#define FUNCT7_SRLI FUNCT7_SLLI
#define FUNCT7_SRAI 32
#define FUNCT7_EBREAK 0 // Note: strictly speaking ebreak and ecall don't have a funct7 field, but their [31-20] bits
#define FUNCT7_ECALL 1 // are used to distinguish between them. I call these FUNCT7 for the sake of modularity.
/* ALUOPS */
#define ALUOP_NULL 0
#define ALUOP_ADD 1
#define ALUOP_SLL 2
#define ALUOP_SLT 3
#define ALUOP_SLTU 4
#define ALUOP_XOR 5
#define ALUOP_SRL 6
#define ALUOP_OR 7
#define ALUOP_AND 8
#define ALUOP_SUB 9
#define ALUOP_SRA 10
#define ALUOP_MUL 11
#define ALUOP_MULH 12
#define ALUOP_MULHSU 13
#define ALUOP_MULHU 14
#define ALUOP_DIV 15
#define ALUOP_DIVU 16
#define ALUOP_REM 17
#define ALUOP_REMU 18
// Integer immediate operation's aluops coincide with their r-type counterparts
#define ALUOP_ADDI ALUOP_ADD
#define ALUOP_SLTI ALUOP_SLT
#define ALUOP_SLTIU ALUOP_SLTU
#define ALUOP_XORI ALUOP_XOR
#define ALUOP_ORI ALUOP_OR
#define ALUOP_ANDI ALUOP_AND
#define ALUOP_SLLI 19
#define ALUOP_SRLI 20
#define ALUOP_SRAI 21
#define ALUOP_LUI 22
#define ALUOP_AUIPC 23
#define ALUOP_JAL 24
#define ALUOP_JALR ALUOP_JAL // like JAL, the ALU operation is < rd = pc + 4 >
#define ALUOP_CSRRW 25
#define ALUOP_CSRRS 26
#define ALUOP_CSRRC 27
#define ALUOP_CSRRWI 28
#define ALUOP_CSRRSI 29
#define ALUOP_CSRRCI 30
/* ALU Source discrimination values */
#define ALUSRC_RS2 0
#define ALUSRC_IMM_I 1
#define ALUSRC_IMM_S 2
#define ALUSRC_IMM_U 3
/* Load and store discrimination values to be assigned to the ld or st signals */
#define NO_LOAD 5
#define LB_LOAD 0
#define LH_LOAD 1
#define LW_LOAD 2
#define LBU_LOAD 3
#define LHU_LOAD 4
#define NO_STORE 3
#define SB_STORE 0
#define SH_STORE 1
#define SW_STORE 2
/* Trap causes: see page 35 of RISC-V privileged ISA draft V1.10. */
#define NULL_CAUSE 10 // 10 is actually reserved in the specs but we use it to indicate no cause.
#define EBREAK_CAUSE 3
#define ECALL_CAUSE 11
#define ILL_INSN_CAUSE 2
/* Control Status Registers' addresses */
#define USTATUS_A 0x000
#define MSTATUS_A 0x300
#define MISA_A 0x301
#define MTVECT_A 0x305
#define MEPC_A 0x341
#define MCAUSE_A 0x342
#define MCYCLE_A 0xB00
#define MARCHID_A 0xF12
#define MIMPID_A 0xF13
#define MINSTRET_A 0xF02
#define MHARTID_A 0xF14
#define USTATUS_I 0
#define MSTATUS_I 1
#define MISA_I 2
#define MTVECT_I 3
#define MEPC_I 4
#define MCAUSE_I 5
#define MCYCLE_I 6
#define MARCHID_I 7
#define MIMPID_I 8
#define MINSTRET_I 9
#define MHARTID_I 10
#endif
|
#ifndef SDRAM_IO_H
#define SDRAM_IO_H
#include <systemc.h>
//----------------------------------------------------------------
// Interface (master)
//----------------------------------------------------------------
class sdram_io_master
{
public:
// Members
sc_uint <1> CLK;
sc_uint <1> CKE;
sc_uint <1> CS;
sc_uint <1> RAS;
sc_uint <1> CAS;
sc_uint <1> WE;
sc_uint <2> DQM;
sc_uint <13> ADDR;
sc_uint <2> BA;
sc_uint <16> DATA_OUTPUT;
sc_uint <1> DATA_OUT_EN;
// Construction
sdram_io_master() { init(); }
void init(void)
{
CLK = 0;
CKE = 0;
CS = 0;
RAS = 0;
CAS = 0;
WE = 0;
DQM = 0;
ADDR = 0;
BA = 0;
DATA_OUTPUT = 0;
DATA_OUT_EN = 0;
}
bool operator == (const sdram_io_master & v) const
{
bool eq = true;
eq &= (CLK == v.CLK);
eq &= (CKE == v.CKE);
eq &= (CS == v.CS);
eq &= (RAS == v.RAS);
eq &= (CAS == v.CAS);
eq &= (WE == v.WE);
eq &= (DQM == v.DQM);
eq &= (ADDR == v.ADDR);
eq &= (BA == v.BA);
eq &= (DATA_OUTPUT == v.DATA_OUTPUT);
eq &= (DATA_OUT_EN == v.DATA_OUT_EN);
return eq;
}
friend void sc_trace(sc_trace_file *tf, const sdram_io_master & v, const std::string & path)
{
sc_trace(tf,v.CLK, path + "/clk");
sc_trace(tf,v.CKE, path + "/cke");
sc_trace(tf,v.CS, path + "/cs");
sc_trace(tf,v.RAS, path + "/ras");
sc_trace(tf,v.CAS, path + "/cas");
sc_trace(tf,v.WE, path + "/we");
sc_trace(tf,v.DQM, path + "/dqm");
sc_trace(tf,v.ADDR, path + "/addr");
sc_trace(tf,v.BA, path + "/ba");
sc_trace(tf,v.DATA_OUTPUT, path + "/data_output");
sc_trace(tf,v.DATA_OUT_EN, path + "/data_out_en");
}
friend ostream& operator << (ostream& os, sdram_io_master const & v)
{
os << hex << "CLK: " << v.CLK << " ";
os << hex << "CKE: " << v.CKE << " ";
os << hex << "CS: " << v.CS << " ";
os << hex << "RAS: " << v.RAS << " ";
os << hex << "CAS: " << v.CAS << " ";
os << hex << "WE: " << v.WE << " ";
os << hex << "DQM: " << v.DQM << " ";
os << hex << "ADDR: " << v.ADDR << " ";
os << hex << "BA: " << v.BA << " ";
os << hex << "DATA_OUTPUT: " << v.DATA_OUTPUT << " ";
os << hex << "DATA_OUT_EN: " << v.DATA_OUT_EN << " ";
return os;
}
friend istream& operator >> ( istream& is, sdram_io_master & val)
{
// Not implemented
return is;
}
};
#define MEMBER_COPY_SDRAM_IO_MASTER(s,d) do { \
s.CLK = d.CLK; \
s.CKE = d.CKE; \
s.CS = d.CS; \
s.RAS = d.RAS; \
s.CAS = d.CAS; \
s.WE = d.WE; \
s.DQM = d.DQM; \
s.ADDR = d.ADDR; \
s.BA = d.BA; \
s.DATA_OUTPUT = d.DATA_OUTPUT; \
s.DATA_OUT_EN = d.DATA_OUT_EN; \
} while (0)
//----------------------------------------------------------------
// Interface (slave)
//----------------------------------------------------------------
class sdram_io_slave
{
public:
// Members
sc_uint <16> DATA_INPUT;
// Construction
sdram_io_slave() { init(); }
void init(void)
{
DATA_INPUT = 0;
}
bool operator == (const sdram_io_slave & v) const
{
bool eq = true;
eq &= (DATA_INPUT == v.DATA_INPUT);
return eq;
}
friend void sc_trace(sc_trace_file *tf, const sdram_io_slave & v, const std::string & path)
{
sc_trace(tf,v.DATA_INPUT, path + "/data_input");
}
friend ostream& operator << (ostream& os, sdram_io_slave const & v)
{
os << hex << "DATA_INPUT: " << v.DATA_INPUT << " ";
return os;
}
friend istream& operator >> ( istream& is, sdram_io_slave & val)
{
// Not implemented
return is;
}
};
#define MEMBER_COPY_SDRAM_IO_SLAVE(s,d) do { \
s.DATA_INPUT = d.DATA_INPUT; \
} while (0)
#endif
|
/********************************************************************************
* University of L'Aquila - HEPSYCODE Source Code License *
* *
* *
* (c) 2018-2019 Centre of Excellence DEWS All rights reserved *
********************************************************************************
* <one line to give the program's name and a brief idea of what it does.> *
* Copyright (C) 2022 Vittoriano Muttillo, Luigi Pomante * *
* *
* This program is free software: you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation, either version 3 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
********************************************************************************
* *
* Created on: 09/May/2023 *
* Authors: Vittoriano Muttillo, Marco Santic, Luigi Pomante *
* *
* email: [email protected] *
* [email protected] *
* [email protected] *
* *
********************************************************************************
* This code has been developed from an HEPSYCODE model used as demonstrator by *
* University of L'Aquila. *
*******************************************************************************/
#include <systemc.h>
#include "../mainsystem.h"
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <math.h>
#include <unistd.h>
////////////////////////////// GENANN //////////////////
#ifdef __cplusplus
extern "C" {
#endif
#ifndef ann_02_GENANN_RANDOM
/* We use the following for uniform random numbers between 0 and 1.
* If you have a better function, redefine this macro. */
#define ann_02_GENANN_RANDOM() (((double)rand())/RAND_MAX)
#endif
struct ann_02_genann;
typedef double (*ann_02_genann_actfun)(const struct ann_02_genann *ann, double a);
typedef struct ann_02_genann {
/* How many inputs, outputs, and hidden neurons. */
int inputs, hidden_layers, hidden, outputs;
/* Which activation function to use for hidden neurons. Default: gennann_act_sigmoid_cached*/
ann_02_genann_actfun activation_hidden;
/* Which activation function to use for output. Default: gennann_act_sigmoid_cached*/
ann_02_genann_actfun activation_output;
/* Total number of weights, and size of weights buffer. */
int total_weights;
/* Total number of neurons + inputs and size of output buffer. */
int total_neurons;
/* All weights (total_weights long). */
double *weight;
/* Stores input array and output of each neuron (total_neurons long). */
double *output;
/* Stores delta of each hidden and output neuron (total_neurons - inputs long). */
double *delta;
} ann_02_genann;
#ifdef __cplusplus
}
#endif
///////////////////////////////////// GENANN ///////////////////////////
#ifndef ann_02_genann_act
#define ann_02_genann_act_hidden ann_02_genann_act_hidden_indirect
#define ann_02_genann_act_output ann_02_genann_act_output_indirect
#else
#define ann_02_genann_act_hidden ann_02_genann_act
#define ann_02_genann_act_output ann_02_genann_act
#endif
#define ann_02_LOOKUP_SIZE 4096
double ann_02_genann_act_hidden_indirect(const struct ann_02_genann *ann, double a)
{HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) return ann->activation_hidden(ann, a);
}
double ann_02_genann_act_output_indirect(const struct ann_02_genann *ann, double a)
{HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) return ann->activation_output(ann, a);
}
const double ann_02_sigmoid_dom_min = -15.0;
const double ann_02_sigmoid_dom_max = 15.0;
double ann_02_interval;
double ann_02_lookup[ann_02_LOOKUP_SIZE];
#ifdef __GNUC__
#define likely(x) __builtin_expect(!!(x), 1)
#define unlikely(x) __builtin_expect(!!(x), 0)
#define unused __attribute__((unused))
#else
#define likely(x) x
#define unlikely(x) x
#define unused
#pragma warning(disable : 4996) /* For fscanf */
#endif
double ann_02_genann_act_sigmoid(const ann_02_genann *ann unused, double a)
{HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) if (a < -45.0)
{HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) return 0;
HEPSY_S(ann_02_id) }
HEPSY_S(ann_02_id) if (a > 45.0)
{HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) return 1;
HEPSY_S(ann_02_id) }
HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) return 1.0 / (1 + exp(-a));
}
void ann_02_genann_init_sigmoid_lookup(const ann_02_genann *ann)
{HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) const double f = (ann_02_sigmoid_dom_max - ann_02_sigmoid_dom_min) / ann_02_LOOKUP_SIZE;
HEPSY_S(ann_02_id) int i;
HEPSY_S(ann_02_id) ann_02_interval = ann_02_LOOKUP_SIZE / (ann_02_sigmoid_dom_max - ann_02_sigmoid_dom_min);
HEPSY_S(ann_02_id) for (i = 0; i < ann_02_LOOKUP_SIZE; ++i)
{HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) ann_02_lookup[i] = ann_02_genann_act_sigmoid(ann, ann_02_sigmoid_dom_min + f * i);
HEPSY_S(ann_02_id) }
}
double ann_02_genann_act_sigmoid_cached(const ann_02_genann *ann unused, double a)
{HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) assert(!isnan(a));
HEPSY_S(ann_02_id) if (a < ann_02_sigmoid_dom_min)
{HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) return ann_02_lookup[0];
HEPSY_S(ann_02_id) }
HEPSY_S(ann_02_id) if (a >= ann_02_sigmoid_dom_max)
{HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) return ann_02_lookup[ann_02_LOOKUP_SIZE - 1];
HEPSY_S(ann_02_id) }
HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) size_t j = (size_t)((a-ann_02_sigmoid_dom_min)*ann_02_interval+0.5);
/* Because floating point... */
HEPSY_S(ann_02_id) if (unlikely(j >= ann_02_LOOKUP_SIZE))
{HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) return ann_02_lookup[ann_02_LOOKUP_SIZE - 1];
HEPSY_S(ann_02_id) }
HEPSY_S(ann_02_id) return ann_02_lookup[j];
}
double ann_02_genann_act_linear(const struct ann_02_genann *ann unused, double a)
{HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) return a;
}
double ann_02_genann_act_threshold(const struct ann_02_genann *ann unused, double a)
{HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) return a > 0;
}
void ann_02_genann_randomize(ann_02_genann *ann)
{HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) int i;
HEPSY_S(ann_02_id) for (i = 0; i < ann->total_weights; ++i)
{HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) double r = ann_02_GENANN_RANDOM();
/* Sets weights from -0.5 to 0.5. */
HEPSY_S(ann_02_id) ann->weight[i] = r - 0.5;
HEPSY_S(ann_02_id) }
}
ann_02_genann *ann_02_genann_init(int inputs, int hidden_layers, int hidden, int outputs)
{HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) if (hidden_layers < 0)
{HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) return 0;
HEPSY_S(ann_02_id) }
HEPSY_S(ann_02_id) if (inputs < 1)
{HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) return 0;
HEPSY_S(ann_02_id) }
HEPSY_S(ann_02_id) if (outputs < 1)
{HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) return 0;
HEPSY_S(ann_02_id) }
HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) if (hidden_layers > 0 && hidden < 1)
{HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) return 0;
HEPSY_S(ann_02_id) }
HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) const int hidden_weights = hidden_layers ? (inputs+1) * hidden + (hidden_layers-1) * (hidden+1) * hidden : 0;
HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) const int output_weights = (hidden_layers ? (hidden+1) : (inputs+1)) * outputs;
HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) const int total_weights = (hidden_weights + output_weights);
HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) const int total_neurons = (inputs + hidden * hidden_layers + outputs);
/* Allocate extra size for weights, outputs, and deltas. */
HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) const int size = sizeof(ann_02_genann) + sizeof(double) * (total_weights + total_neurons + (total_neurons - inputs));
HEPSY_S(ann_02_id) ann_02_genann *ret = (ann_02_genann *)malloc(size);
HEPSY_S(ann_02_id) if (!ret)
{HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) return 0;
HEPSY_S(ann_02_id) }
HEPSY_S(ann_02_id) ret->inputs = inputs;
HEPSY_S(ann_02_id) ret->hidden_layers = hidden_layers;
HEPSY_S(ann_02_id) ret->hidden = hidden;
HEPSY_S(ann_02_id) ret->outputs = outputs;
HEPSY_S(ann_02_id) ret->total_weights = total_weights;
HEPSY_S(ann_02_id) ret->total_neurons = total_neurons;
/* Set pointers. */
HEPSY_S(ann_02_id) ret->weight = (double*)((char*)ret + sizeof(ann_02_genann));
HEPSY_S(ann_02_id) ret->output = ret->weight + ret->total_weights;
HEPSY_S(ann_02_id) ret->delta = ret->output + ret->total_neurons;
HEPSY_S(ann_02_id) ann_02_genann_randomize(ret);
HEPSY_S(ann_02_id) ret->activation_hidden = ann_02_genann_act_sigmoid_cached;
HEPSY_S(ann_02_id) ret->activation_output = ann_02_genann_act_sigmoid_cached;
HEPSY_S(ann_02_id) ann_02_genann_init_sigmoid_lookup(ret);
HEPSY_S(ann_02_id) return ret;
}
void ann_02_genann_free(ann_02_genann *ann)
{HEPSY_S(ann_02_id)
/* The weight, output, and delta pointers go to the same buffer. */
HEPSY_S(ann_02_id) free(ann);
}
//genann *genann_read(FILE *in)
//genann *genann_copy(genann const *ann)
double const *ann_02_genann_run(ann_02_genann const *ann, double const *inputs)
{HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) double const *w = ann->weight;
HEPSY_S(ann_02_id) double *o = ann->output + ann->inputs;
HEPSY_S(ann_02_id) double const *i = ann->output;
/* Copy the inputs to the scratch area, where we also store each neuron's
* output, for consistency. This way the first layer isn't a special case. */
HEPSY_S(ann_02_id) memcpy(ann->output, inputs, sizeof(double) * ann->inputs);
HEPSY_S(ann_02_id) int h, j, k;
HEPSY_S(ann_02_id) if (!ann->hidden_layers)
{HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) double *ret = o;
HEPSY_S(ann_02_id) for (j = 0; j < ann->outputs; ++j)
{HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) double sum = *w++ * -1.0;
HEPSY_S(ann_02_id) for (k = 0; k < ann->inputs; ++k)
{HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) sum += *w++ * i[k];
HEPSY_S(ann_02_id) }
HEPSY_S(ann_02_id) *o++ = ann_02_genann_act_output(ann, sum);
HEPSY_S(ann_02_id) }
HEPSY_S(ann_02_id) return ret;
HEPSY_S(ann_02_id) }
/* Figure input layer */
HEPSY_S(ann_02_id) for (j = 0; j < ann->hidden; ++j)
{HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) double sum = *w++ * -1.0;
HEPSY_S(ann_02_id) for (k = 0; k < ann->inputs; ++k) {
HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) sum += *w++ * i[k];
HEPSY_S(ann_02_id) }
HEPSY_S(ann_02_id) *o++ = ann_02_genann_act_hidden(ann, sum);
HEPSY_S(ann_02_id) }
HEPSY_S(ann_02_id) i += ann->inputs;
/* Figure hidden layers, if any. */
HEPSY_S(ann_02_id) for (h = 1; h < ann->hidden_layers; ++h)
{HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) for (j = 0; j < ann->hidden; ++j)
{HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) double sum = *w++ * -1.0;
HEPSY_S(ann_02_id) for (k = 0; k < ann->hidden; ++k)
{HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) sum += *w++ * i[k];
HEPSY_S(ann_02_id) }
HEPSY_S(ann_02_id) *o++ = ann_02_genann_act_hidden(ann, sum);
HEPSY_S(ann_02_id) }
HEPSY_S(ann_02_id) i += ann->hidden;
HEPSY_S(ann_02_id) }
HEPSY_S(ann_02_id) double const *ret = o;
/* Figure output layer. */
HEPSY_S(ann_02_id) for (j = 0; j < ann->outputs; ++j)
{HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) double sum = *w++ * -1.0;
HEPSY_S(ann_02_id) for (k = 0; k < ann->hidden; ++k)
{HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) sum += *w++ * i[k];
HEPSY_S(ann_02_id) }
HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) *o++ = ann_02_genann_act_output(ann, sum);
HEPSY_S(ann_02_id) }
/* Sanity check that we used all weights and wrote all outputs. */
HEPSY_S(ann_02_id) assert(w - ann->weight == ann->total_weights);
HEPSY_S(ann_02_id) assert(o - ann->output == ann->total_neurons);
HEPSY_S(ann_02_id) return ret;
}
//void genann_train(genann const *ann, double const *inputs, double const *desired_outputs, double learning_rate)
//void genann_write(genann const *ann, FILE *out)
/////////////////////// ANN ////////////////////////
#define ann_02_NUM_DEV 1 // The equipment is composed of NUM_DEV devices ...
//-----------------------------------------------------------------------------
//
//-----------------------------------------------------------------------------
#define ann_02_MAX_ANN 100 // Maximum MAX_ANN ANN
#define ann_02_ANN_INPUTS 2 // Number of inputs
#define ann_02_ANN_HIDDEN_LAYERS 1 // Number of hidden layers
#define ann_02_ANN_HIDDEN_NEURONS 2 // Number of neurons of every hidden layer
#define ann_02_ANN_OUTPUTS 1 // Number of outputs
//-----------------------------------------------------------------------------
//
//-----------------------------------------------------------------------------
#define ann_02_ANN_EPOCHS 10000
#define ann_02_ANN_DATASET 6
#define ann_02_ANN_LEARNING_RATE 3 // ...
//-----------------------------------------------------------------------------
//
//-----------------------------------------------------------------------------
#define ann_02_MAX_ERROR 0.00756 // 0.009
//-----------------------------------------------------------------------------
//
//-----------------------------------------------------------------------------
static int ann_02_nANN = -1 ; // Number of ANN that have been created
static ann_02_genann * ann_02_ann[ann_02_MAX_ANN] ; // Now up to MAX_ANN ann
//static double ann_02_trainingInput[ann_02_ANN_DATASET][ann_02_ANN_INPUTS] = { {0, 0}, {0, 1}, {1, 0}, {1, 1}, {0, 1}, {0, 0} } ;
//static double ann_02_trainingExpected[ann_02_ANN_DATASET][ann_02_ANN_OUTPUTS] = { {0}, {1}, {1}, {0}, {1}, {0} } ;
static double ann_02_weights[] = {
-3.100438,
-7.155774,
-7.437955,
-8.132828,
-5.583678,
-5.327152,
5.564897,
-12.201226,
11.771879
} ;
// static double input[4][3] = {{0, 0, 1}, {0, 1, 1}, {1, 0, 1}, {1, 1, 1}};
// static double output[4] = {0, 1, 1, 0};
//-----------------------------------------------------------------------------
//
//-----------------------------------------------------------------------------
static int ann_02_annCheck(int index);
static int ann_02_annCreate(int n);
//-----------------------------------------------------------------------------
// Check the correctness of the index of the ANN
//-----------------------------------------------------------------------------
int ann_02_annCheck(int index)
{HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) if( (index < 0) || (index >= ann_02_nANN) )
{HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) return( EXIT_FAILURE );
HEPSY_S(ann_02_id) }
HEPSY_S(ann_02_id) return( EXIT_SUCCESS );
}
//-----------------------------------------------------------------------------
// Create n ANN
//-----------------------------------------------------------------------------
int ann_02_annCreate(int n)
{HEPSY_S(ann_02_id)
// If already created, or not legal number, or too many ANN, then error
HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) if( (ann_02_nANN != -1) || (n <= 0) || (n > ann_02_MAX_ANN) )
{HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) return( EXIT_FAILURE );
}
// Create the ANN's
HEPSY_S(ann_02_id) for ( int i = 0; i < n; i++ )
{HEPSY_S(ann_02_id)
// New ANN with ANN_INPUT inputs, ANN_HIDDEN_LAYER hidden layers all with ANN_HIDDEN_NEURON neurons, and ANN_OUTPUT outputs
HEPSY_S(ann_02_id) ann_02_ann[i] = ann_02_genann_init(ann_02_ANN_INPUTS, ann_02_ANN_HIDDEN_LAYERS, ann_02_ANN_HIDDEN_NEURONS, ann_02_ANN_OUTPUTS);
HEPSY_S(ann_02_id) if ( ann_02_ann[i] == 0 )
{HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) for (int j = 0; j < i; j++)
{HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) ann_02_genann_free(ann_02_ann[j]) ;
HEPSY_S(ann_02_id) }
HEPSY_S(ann_02_id) return( EXIT_FAILURE );
HEPSY_S(ann_02_id) }
HEPSY_S(ann_02_id) }
HEPSY_S(ann_02_id) ann_02_nANN = n ;
HEPSY_S(ann_02_id) return( EXIT_SUCCESS );
}
////-----------------------------------------------------------------------------
//// Create and train n identical ANN
////-----------------------------------------------------------------------------
//int annCreateAndTrain(int n)
//{
// if ( annCreate(n) != EXIT_SUCCESS )
// return( EXIT_FAILURE );
//
// // Train the ANN's
// for ( int index = 0; index < nANN; index++ )
// for ( int i = 0; i < ANN_EPOCHS; i++ )
// for ( int j = 0; j < ANN_DATASET; j++ )
// genann_train(ann[index], trainingInput[j], trainingExpected[j], ANN_LEARNING_RATE) ;
//
// return( EXIT_SUCCESS );
//}
//-----------------------------------------------------------------------------
// Create n identical ANN and set their weight
//-----------------------------------------------------------------------------
int ann_02_annCreateAndSetWeights(int n)
{HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) if( ann_02_annCreate(n) != EXIT_SUCCESS )
{HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) return( EXIT_FAILURE );
HEPSY_S(ann_02_id) }
// Set weights
HEPSY_S(ann_02_id) for ( int index = 0; index < ann_02_nANN; index++ )
{HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) for( int i = 0; i < ann_02_ann[index]->total_weights; ++i )
{HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) ann_02_ann[index]->weight[i] = ann_02_weights[i] ;
HEPSY_S(ann_02_id) }
HEPSY_S(ann_02_id) }
HEPSY_S(ann_02_id) return( EXIT_SUCCESS );
}
//-----------------------------------------------------------------------------
// x[2] = x[0] XOR x[1]
//-----------------------------------------------------------------------------
int ann_02_annRun(int index, double x[ann_02_ANN_INPUTS + ann_02_ANN_OUTPUTS])
{HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) if( ann_02_annCheck(index) != EXIT_SUCCESS )
{HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) return( EXIT_FAILURE ) ;
HEPSY_S(ann_02_id) }
HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) x[2] = * ann_02_genann_run(ann_02_ann[index], x) ;
HEPSY_S(ann_02_id) return( EXIT_SUCCESS );
}
////-----------------------------------------------------------------------------
////
////-----------------------------------------------------------------------------
//int annPrintWeights(int index)
//{
// if ( annCheck(index) != EXIT_SUCCESS )
// return( EXIT_FAILURE ) ;
//
//
// printf("\n*** ANN index = %d\n", index) ;
// for ( int i = 0; i < ann[index]->total_weights; ++i )
// printf("*** w%d = %f\n", i, ann[index]->weight[i]) ;
//
// return( EXIT_SUCCESS );
//}
////-------------------------------------------------------
|
----------------------
//// Run the index-th ANN k time on random input and return the number of error
////-----------------------------------------------------------------------------
//int annTest(int index, int k)
//{
// int x0; int x1; int y;
// double x[2];
// double xor_ex;
// int error = 0;
//
// if ( annCheck(index) != EXIT_SUCCESS )
// return( -1 ); // less than zero errors <==> the ANN isn't correctly created
//
// for (int i = 0; i < k; i++ )
// {
// x0 = rand() % 2; x[0] = (double)x0;
// x1 = rand() % 2; x[1] = (double)x1;
// y = x0 ^ x1 ;
//
// xor_ex = * genann_run(ann[index], x);
// if ( fabs(xor_ex - (double)y) > MAX_ERROR )
// {
// error++ ;
// printf("@@@ Error: ANN = %d, step = %d, x0 = %d, x1 = %d, y = %d, xor_ex = %f \n", index, i, x0, x1, y, xor_ex) ;
// }
// }
//
// if ( error )
// printf("@@@ ANN = %d: N� of errors = %d\n", index, error) ;
// else
// printf("*** ANN = %d: Test OK\n",index) ;
// return( error );
//}
//-----------------------------------------------------------------------------
//
//-----------------------------------------------------------------------------
void ann_02_annDestroy(void)
{HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) if( ann_02_nANN == -1 )
{HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) return ;
}
HEPSY_S(ann_02_id) for ( int index = 0; index < ann_02_nANN; index++ )
{HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) ann_02_genann_free(ann_02_ann[index]) ;
HEPSY_S(ann_02_id) }
HEPSY_S(ann_02_id) ann_02_nANN = -1 ;
}
void mainsystem::ann_02_main()
{
// datatype for channels
cleanData_xx_ann_xx_payload cleanData_xx_ann_xx_payload_var;
ann_xx_dataCollector_payload ann_xx_dataCollector_payload_var;
double x[ann_02_ANN_INPUTS + ann_02_ANN_OUTPUTS] ;
//int ann_02_index = 1;
HEPSY_S(ann_02_id) if( ann_02_annCreateAndSetWeights(ann_02_NUM_DEV) != EXIT_SUCCESS )
{HEPSY_S(ann_02_id) // Create and init ANN
HEPSY_S(ann_02_id) printf("Error Weights \n");
HEPSY_S(ann_02_id) }
//implementation
HEPSY_S(ann_02_id) while(1)
{HEPSY_S(ann_02_id)
// content
HEPSY_S(ann_02_id)cleanData_xx_ann_xx_payload_var = cleanData_02_ann_02_channel->read();
HEPSY_S(ann_02_id) ann_xx_dataCollector_payload_var.dev = cleanData_xx_ann_xx_payload_var.dev;
HEPSY_S(ann_02_id) ann_xx_dataCollector_payload_var.step = cleanData_xx_ann_xx_payload_var.step;
HEPSY_S(ann_02_id) ann_xx_dataCollector_payload_var.ex_time = cleanData_xx_ann_xx_payload_var.ex_time;
HEPSY_S(ann_02_id) ann_xx_dataCollector_payload_var.device_i = cleanData_xx_ann_xx_payload_var.device_i;
HEPSY_S(ann_02_id) ann_xx_dataCollector_payload_var.device_v = cleanData_xx_ann_xx_payload_var.device_v;
HEPSY_S(ann_02_id) ann_xx_dataCollector_payload_var.device_t = cleanData_xx_ann_xx_payload_var.device_t;
HEPSY_S(ann_02_id) ann_xx_dataCollector_payload_var.device_r = cleanData_xx_ann_xx_payload_var.device_r;
HEPSY_S(ann_02_id) x[0] = cleanData_xx_ann_xx_payload_var.x_0;
HEPSY_S(ann_02_id) x[1] = cleanData_xx_ann_xx_payload_var.x_1;
HEPSY_S(ann_02_id) x[2] = cleanData_xx_ann_xx_payload_var.x_2;
//u = cleanData_xx_ann_xx_payload_var.step;
HEPSY_S(ann_02_id) ann_xx_dataCollector_payload_var.fault = cleanData_xx_ann_xx_payload_var.fault;
//RUN THE ANN...
// ### P R E D I C T (simple XOR)
// if ( annRun(index, x) != EXIT_SUCCESS ){
// printf("Step = %u Index = %d ANN error.\n", u, index) ;
// }else{
// device[index].fault = x[2] <= 0.5 ? 0 : 1 ;
// }
//u: cycle num
HEPSY_S(ann_02_id) if( ann_02_annRun(0, x) != EXIT_SUCCESS )
{HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) printf("Step = %d Index = %d ANN error.\n", (int)ann_xx_dataCollector_payload_var.step, (int)ann_xx_dataCollector_payload_var.dev) ;
HEPSY_S(ann_02_id) }
else
{HEPSY_S(ann_02_id)
HEPSY_S(ann_02_id) ann_xx_dataCollector_payload_var.fault = x[2] <= 0.5 ? 0 : 1 ;
HEPSY_S(ann_02_id) }
HEPSY_S(ann_02_id) ann_02_dataCollector_channel->write(ann_xx_dataCollector_payload_var);
HEPSY_P(ann_02_id)
}
}
// END
|
/*
* cache.h
*
* Created on: Sep 16, 2014
* Author: lloyd23
*/
#ifndef CACHE_H_
#define CACHE_H_
//------------------ Cache ------------------//
// cache management on host and accelerator
/* NOTE: if invalidate is used on non-cache aligned and sized allocations, */
/* it can corrupt the heap. */
#ifdef __cplusplus
#define ns(name) name::
#else
#define ns(name)
#endif
#if defined(CLIENT)
#define CACHE_BARRIER(a) {a.cache_flush(); a.cache_invalidate(); ns(host)cache_flush_invalidate();}
#define CACHE_DISPOSE(a,p,n) {a.cache_invalidate(p,n); ns(host)cache_invalidate(p,n);}
#define CACHE_BARRIER2(a,b) {a.cache_flush(); a.cache_invalidate(); b.cache_flush(); b.cache_invalidate(); ns(host)cache_flush_invalidate();}
#define CACHE_DISPOSE2(a,b,p,n) {a.cache_invalidate(p,n); b.cache_invalidate(p,n); ns(host)cache_invalidate(p,n);}
#else // not CLIENT
#define CACHE_BARRIER(a) {ns(host)cache_flush_invalidate();}
#define CACHE_DISPOSE(a,p,n) {ns(host)cache_invalidate(p,n);}
#define CACHE_BARRIER2(a,b) {ns(host)cache_flush_invalidate();}
#define CACHE_DISPOSE2(a,b,p,n) {ns(host)cache_invalidate(p,n);}
#endif // end CLIENT
#if defined(USE_STREAM)
/* Not enabled with defined(DIRECT) */
#define CACHE_SEND_ALL(a) {ns(host)cache_flush(); /*a.cache_flush(); a.cache_invalidate();*/}
#define CACHE_RECV_ALL(a) {/*a.cache_flush();*/ ns(host)cache_flush_invalidate();}
#define CACHE_SEND(a,p,n) {ns(host)cache_flush(p,n); /*a.cache_invalidate(p,n);*/}
#define CACHE_RECV(a,p,n) {/*a.cache_flush(p,n);*/ ns(host)cache_invalidate(p,n);}
#else // not USE_STREAM
#define CACHE_SEND_ALL(a)
#define CACHE_RECV_ALL(a)
#define CACHE_SEND(a,p,n)
#define CACHE_RECV(a,p,n)
#endif // end USE_STREAM
#if defined(XCACHE)
#include "xpseudo_asm.h" // mtcp*, dsb
#include "xil_cache.h" // Xil_D*
#if defined(__aarch64__)
#define Xil_L1DCacheFlush Xil_DCacheFlush
#define Xil_L1DCacheFlushRange Xil_DCacheFlushRange
#define Xil_L1DCacheInvalidate Xil_DCacheInvalidate
#define Xil_L1DCacheInvalidateRange Xil_DCacheInvalidateRange
#define dc_CVAC(va) mtcpdc(CVAC,(INTPTR)(va))
#define dc_CIVAC(va) mtcpdc(CIVAC,(INTPTR)(va))
#else // not __aarch64__
#include "xil_cache_l.h" // Xil_L1D*
#define dc_CVAC(va) mtcp(XREG_CP15_CLEAN_DC_LINE_MVA_POC,(INTPTR)(va))
#define dc_CIVAC(va) mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC,(INTPTR)(va))
#endif // end __aarch64__
#elif defined(__microblaze__)
#include "xil_cache.h" // Xil_L1D*, Xil_D*
#else // not XCACHE, __microblaze__
/* Data Synchronization Barrier */
#define dsb()
/* single cache line */
#define dc_CVAC(va)
#define dc_CIVAC(va)
/* L1 data cache */
#define Xil_L1DCacheEnable()
#define Xil_L1DCacheDisable()
#define Xil_L1DCacheInvalidate()
#define Xil_L1DCacheInvalidateRange(adr, len)
#define Xil_L1DCacheInvalidateLine(adr)
#define Xil_L1DCacheFlush()
#define Xil_L1DCacheFlushRange(adr, len)
#define Xil_L1DCacheFlushLine(adr)
#define Xil_L1DCacheStoreLine(adr)
#define Xil_DCacheEnable()
#define Xil_DCacheDisable()
#define Xil_DCacheInvalidate()
#define Xil_DCacheInvalidateRange(adr, len)
#define Xil_DCacheInvalidateLine(adr)
#define Xil_DCacheFlush()
#define Xil_DCacheFlushRange(adr, len)
#define Xil_DCacheFlushLine(adr)
#define Xil_ICacheEnable()
#define Xil_ICacheDisable()
#define Xil_ICacheInvalidate()
#define Xil_ICacheInvalidateRange(adr, len)
#define Xil_ICacheInvalidateLine(adr)
#define Xil_ConfigureL1Prefetch(num)
#endif // end XCACHE, __microblaze__
#ifdef __cplusplus
#if defined(SYSTEMC)
#include <systemc.h>
#endif
namespace host {
#if defined(ZYNQ)
#if defined(__aarch64__)
inline void cache_flush(void) {Xil_DCacheFlush();}
inline void cache_flush(const void *ptr, size_t size) {Xil_DCacheFlushRange((INTPTR)ptr, size);}
inline void cache_flush_invalidate(void) {Xil_DCacheFlush();}
inline void cache_flush_invalidate(const void *ptr, size_t size) {Xil_DCacheFlushRange((INTPTR)ptr, size);}
inline void cache_invalidate(void) {Xil_DCacheInvalidate();}
inline void cache_invalidate(const void *ptr, size_t size) {Xil_DCacheInvalidateRange((INTPTR)ptr, size);}
#else // not __aarch64__
// Differentiate between scratchpad (SP) with only L1 enabled (Xil_L1DCache*)
// and DRAM space with both L1 and L2 enabled (Xil_DCache*).
#define IS_SP(ptr) ((char*)(ptr) >= (char*)0x40000000 && (char*)(ptr) < (char*)0x40200000)
inline void cache_flush(void) {Xil_DCacheFlush();}
inline void cache_flush(const void *ptr, size_t size)
{
if (IS_SP(ptr)) Xil_L1DCacheFlushRange((INTPTR)ptr, size);
else Xil_DCacheFlushRange((INTPTR)ptr, size);
}
inline void cache_flush_invalidate(void) {Xil_DCacheFlush();}
inline void cache_flush_invalidate(const void *ptr, size_t size)
{
if (IS_SP(ptr)) Xil_L1DCacheFlushRange((INTPTR)ptr, size);
else Xil_DCacheFlushRange((INTPTR)ptr, size);
}
inline void cache_invalidate(void) {Xil_DCacheInvalidate();}
inline void cache_invalidate(const void *ptr, size_t size)
{
if (IS_SP(ptr)) Xil_L1DCacheInvalidateRange((INTPTR)ptr, size);
else Xil_DCacheInvalidateRange((INTPTR)ptr, size);
}
#endif // end __aarch64__
#elif defined(SYSTEMC)
// cache management overhead in ns per byte
#define _NSPB .230
inline void cache_flush(void) {}
inline void cache_flush(const void *ptr, size_t size) {wait(_NSPB*size,SC_NS);}
inline void cache_flush_invalidate(void) {}
inline void cache_flush_invalidate(const void *ptr, size_t size) {wait(_NSPB*size,SC_NS);}
inline void cache_invalidate(void) {}
inline void cache_invalidate(const void *ptr, size_t size) {wait(_NSPB*size,SC_NS);}
#undef _NSPB
#else // not ZYNQ, SYSTEMC
inline void cache_flush(void) {}
inline void cache_flush(const void *ptr, size_t size) {}
inline void cache_flush_invalidate(void) {}
inline void cache_flush_invalidate(const void *ptr, size_t size) {}
inline void cache_invalidate(void) {}
inline void cache_invalidate(const void *ptr, size_t size) {}
#endif // end ZYNQ, SYSTEMC
} // namespace host
#else // not __cplusplus
static inline void cache_flush(void) {Xil_DCacheFlush();}
static inline void cache_flush_invalidate(void) {Xil_DCacheFlush();}
#endif // end __cplusplus
#endif /* end CACHE_H_ */
|
#include <systemc.h>
#include "interfaces.cpp"
#include "fila.h"
#include "flit.h"
/* portas/sinais feitos de acordo com a imagem do roteador SoCIN.
* Dúvidas: como posso acionar os outros métodos via SC_METHOD? Pq a lista de sensibilidade está ok, mas não está acionando o método de leitura do buffer (apenas adição)
*
*/
class Buffer : public sc_module {
private:
sc_int<32> length;
fila posicoes(flit);
sc_in<sc_int<34>> din; // data + bop + eop
sc_in<sc_int<32>> wr;
sc_in<sc_int<32>> rd;
sc_out<sc_int<32>> wok;
sc_out<sc_int<32>> dout;
sc_out<sc_int<32>> rok;
int prioridade = 0; // Ver se realmente é necessário...
public:
sc_int<32> isFull();
sc_int<32> isEmpty();
void add();
void remove();
Buffer(sc_int<32>);
SC_CTOR(Buffer){
SC_METHOD(add);
sensitive << din;
sensitive << wr;
sensitive << rd;
}
};
|
// Copyright (c) 2011-2024 Columbia University, System Level Design Group
// SPDX-License-Identifier: MIT
#ifndef __ESP_UTILS_HPP__
#define __ESP_UTILS_HPP__
#include "esp_data.hpp"
#include "esp_systemc.hpp"
#define ESP_REPORT_INFO(...) \
fprintf(stderr, "Info: %s: ", sc_object::basename()); \
fprintf(stderr, __VA_ARGS__); \
fprintf(stderr, "\n\n");
#define ESP_REPORT_ERROR(...) \
fprintf(stderr, "Error: %s: ", sc_object::basename()); \
fprintf(stderr, __VA_ARGS__); \
fprintf(stderr, "\n\n");
#define ESP_REPORT_TIME(time, ...) \
{ std::stringstream _ss; _ss << time; \
std::string _s = _ss.str(); const char * _time = _s.c_str(); \
fprintf(stderr, "Info: %s: ", sc_object::basename()); \
fprintf(stderr, "@%s ", _time); \
fprintf(stderr, __VA_ARGS__); \
fprintf(stderr, "\n\n"); } \
template <unsigned int n>
struct slog_2 { enum { value = 1 + slog_2<n/2>::value }; };
template <> struct slog_2<1> { enum { value = 0 }; };
// Helper macros
#define __str(s) #s
#define __xstr(s) __str(s)
#define MYPPCAT_4(A,B,C,D) A ## _DMA ## B ## _CHK ## C ## _PP ## D
#define MYPPCAT_41(A,B,C,D) A ## _DMA ## B ## _CHK ## C ## _PP ## D ## _t
#define MYPPCAT_42(A,B,C,D) A ## _DMA ## B ## _CHK ## C ## _PP ## D.hpp
// Macros for users
#define GENERATE_PLM_TYPE(mem, dma, chk, pp) \
MYPPCAT_41(mem, dma, chk, pp)
#define GENERATE_PLM_NAME(mem, dma, chk, pp) \
__xstr(MYPPCAT_4(mem, dma, chk, pp))
#define GENERATE_PLM_HDR(mem, dma, chk, pp) \
__xstr(MYPPCAT_42(mem, dma, chk, pp))
#ifdef ESP_DEBUG
// Print info only if debug
#define ESP_REPORT_DEBUG(...) \
fprintf(stderr, "Debug: %s: ", sc_object::basename()); \
fprintf(stderr, __VA_ARGS__); \
fprintf(stderr, "\n\n");
#else
#define ESP_REPORT_DEBUG(...)
#endif
#endif /* __ESP_UTILS_HPP__ */
|
#ifndef __ROM_3840_32_H__
#define __ROM_3840_32_H__
#include <fstream>
#include <systemc.h>
class rom_3840x32_t : public sc_module
{
public:
sc_in<uint32_t> addr1;
sc_in<uint32_t> addr2;
sc_out<uint32_t> data1;
sc_out<uint32_t> data2;
uint32_t data[3840];
void port1() {
while(true) {
uint32_t addrw32 = addr1.read();
uint32_t addrw11 = addrw32 % 4096;
data1.write(data[addrw11]);
wait();
}
}
void port2() {
while(true) {
uint32_t addrw32 = addr2.read();
uint32_t addrw11 = addrw32 % 4096;
data2.write(data[addrw11]);
wait();
}
}
void clear_memory() {
for (int i=0; i<3840; ++i) data[i] = 0;
update.write(!update.read());
}
bool load_binary(const std::string& path)
{
clear_memory();
ifstream f(path, std::ios::binary);
if (f.is_open()) {
f.seekg(0, f.end);
int size = f.tellg();
f.seekg(0, f.beg);
auto buf = new char[size];
f.read(buf, size);
// std::vector<unsigned char> buf
// (std::istreambuf_iterator<char>(f), {});
if (size == 0) return false;
if (size % 4 != 0) return false;
auto words = (uint32_t*) buf;
for (int i=0; i<size/4; ++i) {
data[i] = words[i];
}
f.close();
delete[] buf;
update.write(!update.read());
return true;
}
else {
return false;
}
}
SC_CTOR(rom_3840x32_t)
: update("update")
{
update.write(false);
SC_THREAD(port1);
sensitive << addr1;
sensitive << update;
SC_THREAD(port2);
sensitive << addr2;
sensitive << update;
}
private:
sc_signal<bool> update;
};
#endif
|
#ifndef TOP_HPP
#define TOP_HPP
#include <systemc.h>
#include "scheduler.hpp"
#include "processing_engine.hpp"
#include "verbose.hpp"
#define CORE_BIND(NAME, INDEX) \
NAME.clk(clk); \
NAME.reset(reset); \
NAME.from_scheduler_instructions(npu_instructions[INDEX]); \
NAME.from_scheduler_weight(npu_weight[INDEX]); \
NAME.from_scheduler_input(npu_input[INDEX]); \
NAME.to_scheduler(npu_output[INDEX]);
class top_module : public sc_core::sc_module
{
public:
sc_in<bool> clk;
sc_in<bool> reset;
// IO
sc_fifo_in< sc_uint<64> > dma_config;
sc_fifo_in<float> dma_weight;
sc_fifo_in<float> dma_input;
sc_fifo_out<float> dma_output;
sc_fifo<sc_uint<34>> npu_instructions[CORE];
sc_fifo<float> npu_weight[CORE];
sc_fifo<float> npu_input[CORE];
sc_fifo<float> npu_output[CORE];
// Modules
scheduler_module mod_scheduler;
// Cores
#if CORE == 8
processing_engine_module mod_core_1;
processing_engine_module mod_core_2;
processing_engine_module mod_core_3;
processing_engine_module mod_core_4;
processing_engine_module mod_core_5;
processing_engine_module mod_core_6;
processing_engine_module mod_core_7;
processing_engine_module mod_core_8;
#elif CORE == 4
processing_engine_module mod_core_1;
processing_engine_module mod_core_2;
processing_engine_module mod_core_3;
processing_engine_module mod_core_4;
#elif CORE == 2
processing_engine_module mod_core_1;
processing_engine_module mod_core_2;
#elif CORE == 1
processing_engine_module mod_core_1;
#endif
top_module(sc_module_name name);
SC_HAS_PROCESS(top_module);
};
#endif
|
#define SC_INCLUDE_FX
#include <systemc.h>
#include "MAC.h"
#include <iostream>
#include <vector>
using namespace std;
SC_MODULE(ALEXNET)
{
CONV_RELU_1 m_CONV_RELU_1;
MAX_POOLING_1 m_MAX_POOLING_1;
CONV_RELU_2 m_CONV_RELU_2;
MAX_POOLING_2 m_MAX_POOLING_2;
CONV_RELU_3 m_CONV_RELU_3;
CONV_RELU_4 m_CONV_RELU_4;
CONV_RELU_5 m_CONV_RELU_5;
MAX_POOLING_3 m_MAX_POOLING_3;
LINEAR_RELU_1 m_LINEAR_RELU_1;
LINEAR_RELU_2 m_LINEAR_RELU_2;
LINEAR_3 m_LINEAR_3;
sc_in < bool > clk, rst;
sc_in < bool > in_valid;
sc_fifo < bool > conv1_valid;
sc_fifo < bool > mp1_valid;
sc_fifo < bool > conv2_valid;
sc_fifo < bool > mp2_valid;
sc_fifo < bool > conv3_valid;
sc_fifo < bool > conv4_valid;
sc_fifo < bool > conv5_valid;
sc_fifo < bool > mp3_valid;
sc_fifo < bool > linear1_valid;
sc_fifo < bool > linear2_valid;
sc_out < bool > linear3_valid;
sc_vector < sc_in < sc_fixed_fast<45,17> > > image{"image", 150528};
sc_vector < sc_fifo < sc_fixed_fast<45,17> > > conv1_result{"conv1_result", 193600};
sc_vector < sc_fifo < sc_fixed_fast<45,17> > > mp1_result{"mp1_result", 46656};
sc_vector < sc_fifo < sc_fixed_fast<45,17> > > conv2_result{"conv2_result", 139968};
sc_vector < sc_fifo < sc_fixed_fast<45,17> > > mp2_result{"mp2_result", 32448};
sc_vector < sc_fifo < sc_fixed_fast<45,17> > > conv3_result{"conv3_result", 64896};
sc_vector < sc_fifo < sc_fixed_fast<45,17> > > conv4_result{"conv4_result", 43264};
sc_vector < sc_fifo < sc_fixed_fast<45,17> > > conv5_result{"conv5_result", 43264};
sc_vector < sc_fifo < sc_fixed_fast<45,17> > > mp3_result{"mp3_result", 9216};
sc_vector < sc_fifo < sc_fixed_fast<45,17> > > linear1_result{"linear1_result", 4096};
sc_vector < sc_fifo < sc_fixed_fast<45,17> > > linear2_result{"linear2_result", 4096};
sc_vector < sc_out < sc_fixed_fast<45,17> > > linear3_result{"linear3_result", 1000};
SC_CTOR(ALEXNET): m_CONV_RELU_1( "m_CONV_RELU_1" ),
m_MAX_POOLING_1( "m_MAX_POOLING_1" ),
m_CONV_RELU_2( "m_CONV_RELU_2" ),
m_MAX_POOLING_2( "m_MAX_POOLING_2" ),
m_CONV_RELU_3( "m_CONV_RELU_3" ),
m_CONV_RELU_4( "m_CONV_RELU_4" ),
m_CONV_RELU_5( "m_CONV_RELU_5" ),
m_MAX_POOLING_3( "m_MAX_POOLING_3" ),
m_LINEAR_RELU_1( "m_LINEAR_RELU_1" ),
m_LINEAR_RELU_2( "m_LINEAR_RELU_2" ),
m_LINEAR_3( "m_LINEAR_3" )
{
m_CONV_RELU_1.clk(clk);
m_CONV_RELU_1.rst(rst);
m_CONV_RELU_1.in_feature_map(image);
m_CONV_RELU_1.out_feature_map(conv1_result);
m_CONV_RELU_1.in_valid(in_valid);
m_CONV_RELU_1.out_valid(conv1_valid);
// m_CONV_RELU_1.IN_VECTOR_SIZE = 150528;
// m_CONV_RELU_1.OUT_VECTOR_SIZE = 193600;
m_CONV_RELU_1.IN_CHANNELS = 3;
m_CONV_RELU_1.IN_HEIGHT = 224;
m_CONV_RELU_1.IN_WIDTH = 224;
m_CONV_RELU_1.KERNAL_SIZE = 11;
m_CONV_RELU_1.OUT_CHANNELS = 64;
m_CONV_RELU_1.OUT_HEIGHT = 55;
m_CONV_RELU_1.OUT_WIDTH = 55;
m_CONV_RELU_1.STRIDE = 4;
m_CONV_RELU_1.PADDING = 2;
m_CONV_RELU_1.weight_dir = "data/conv1_weight.txt";
m_CONV_RELU_1.bias_dir = "data/conv1_bias.txt";
m_MAX_POOLING_1.clk(clk);
m_MAX_POOLING_1.rst(rst);
m_MAX_POOLING_1.in_feature_map(conv1_result);
m_MAX_POOLING_1.out_feature_map(mp1_result);
m_MAX_POOLING_1.in_valid(conv1_valid);
m_MAX_POOLING_1.out_valid(mp1_valid);
m_CONV_RELU_2.clk(clk);
m_CONV_RELU_2.rst(rst);
m_CONV_RELU_2.in_feature_map(mp1_result);
m_CONV_RELU_2.out_feature_map(conv2_result);
m_CONV_RELU_2.in_valid(mp1_valid);
m_CONV_RELU_2.out_valid(conv2_valid);
m_MAX_POOLING_2.clk(clk);
m_MAX_POOLING_2.rst(rst);
m_MAX_POOLING_2.in_feature_map(conv2_result);
m_MAX_POOLING_2.out_feature_map(mp2_result);
m_MAX_POOLING_2.in_valid(conv2_valid);
m_MAX_POOLING_2.out_valid(mp2_valid);
m_CONV_RELU_3.clk(clk);
m_CONV_RELU_3.rst(rst);
m_CONV_RELU_3.in_feature_map(mp2_result);
m_CONV_RELU_3.out_feature_map(conv3_result);
m_CONV_RELU_3.in_valid(mp2_valid);
m_CONV_RELU_3.out_valid(conv3_valid);
m_CONV_RELU_4.clk(clk);
m_CONV_RELU_4.rst(rst);
m_CONV_RELU_4.in_feature_map(conv3_result);
m_CONV_RELU_4.out_feature_map(conv4_result);
m_CONV_RELU_4.in_valid(conv3_valid);
m_CONV_RELU_4.out_valid(conv4_valid);
m_CONV_RELU_5.clk(clk);
m_CONV_RELU_5.rst(rst);
m_CONV_RELU_5.in_feature_map(conv4_result);
m_CONV_RELU_5.out_feature_map(conv5_result);
m_CONV_RELU_5.in_valid(conv4_valid);
m_CONV_RELU_5.out_valid(conv5_valid);
m_MAX_POOLING_3.clk(clk);
m_MAX_POOLING_3.rst(rst);
m_MAX_POOLING_3.in_feature_map(conv5_result);
m_MAX_POOLING_3.out_feature_map(mp3_result);
m_MAX_POOLING_3.in_valid(conv5_valid);
m_MAX_POOLING_3.out_valid(mp3_valid);
m_LINEAR_RELU_1.clk(clk);
m_LINEAR_RELU_1.rst(rst);
m_LINEAR_RELU_1.in_feature_map(mp3_result);
m_LINEAR_RELU_1.out_feature_map(linear1_result);
m_LINEAR_RELU_1.in_valid(mp3_valid);
m_LINEAR_RELU_1.out_valid(linear1_valid);
m_LINEAR_RELU_2.clk(clk);
m_LINEAR_RELU_2.rst(rst);
m_LINEAR_RELU_2.in_feature_map(linear1_result);
m_LINEAR_RELU_2.out_feature_map(linear2_result);
m_LINEAR_RELU_2.in_valid(linear1_valid);
m_LINEAR_RELU_2.out_valid(linear2_valid);
m_LINEAR_3.clk(clk);
m_LINEAR_3.rst(rst);
m_LINEAR_3.in_feature_map(linear2_result);
m_LINEAR_3.out_feature_map(linear3_result);
m_LINEAR_3.in_valid(linear2_valid);
m_LINEAR_3.out_valid(linear3_valid);
}
};
|
/**
* Author: Anubhav Tomar
*
* Library Definition
**/
#ifndef LIB_H
#define LIB_H
#include<systemc.h>
#include <map>
#define TOTAL_TX_PACKETS 30
#define TUPLES_PER_PACKETS 20
struct roiTuple {
int roi;
int startTime;
int endTime;
roiTuple();
roiTuple(int _r , int _s , int _e) : roi(_r) , startTime(_s) , endTime(_e) {};
roiTuple(const roiTuple &_r) : roi(_r.roi) , startTime(_r.startTime) , endTime(_r.endTime) {};
};
struct point {
int x;
int y;
point(int _x , int _y) : x(_x) , y(_y) {};
};
std::map<int , std::vector<point> > roiMap ();
std::map<int , std::vector<point> > _roiMap = roiMap();
std::map<int , std::vector<point> > roiMap () {
std::map<int , std::vector<point> > _map;
// ROI 1
_map[1].push_back(point(50 , 20));
_map[1].push_back(point(400 , 320));
// ROI 2
_map[2].push_back(point(50 , 370));
_map[2].push_back(point(450 , 1000));
// ROI 3
_map[3].push_back(point(470 , 20));
_map[3].push_back(point(600 , 900));
// ROI 4
_map[4].push_back(point(670 , 40));
_map[4].push_back(point(950 , 550));
// ROI 5
_map[5].push_back(point(680 , 700));
_map[5].push_back(point(1000 , 1000));
return _map;
}
#endif
|
//-----Module definition for Quantize hardware block -------------
//-----You must modify this file as indicated by TODO comments----
#include "systemc.h"
#include "Block.h"
#define INT_PULSE_WIDTH sc_time(1, SC_US)
//module
SC_MODULE(HW_Quant)
{
public:
//constructor
SC_CTOR(HW_Quant) {
//instantiate the Quantize thread
SC_THREAD(Quant_thread);
}
//define the Quantize thread method
void Quant_thread();
//TODO: define the FIFO buffer interfaces
//TODO: name them InBuffer and OutBuffer
sc_fifo_in<Block> InBuffer;
sc_fifo_out<Block> OutBuffer;
//TODO: define the interrupt ports
//TODO: name them int_input_seek, int_output_avail
sc_out<bool> int_input_seek, int_output_avail;
};
|
#include "systemc.h"
#include "run_mode.h"
#include<iostream>
#include<fstream>
using namespace std;
SC_MODULE(lenet)
{
sc_in_clk clock;
sc_in<bool> reset;
sc_out<bool> rom_rd;
sc_out<bool> ram_wr;
sc_out<sc_uint<16> > rom_addr;
sc_out<sc_uint<16> > ram_addr;
sc_in<TYPE > rom_data_in; // TYPE
sc_in<TYPE > ram_data_in; // TYPE
sc_out<TYPE > ram_data_out; // TYPE
sc_out<TYPE > result; // TYPE
sc_out<bool> valid;
void le();
ifstream fin;
int steps, times, i_ker, i_rom ;
bool readKernel, getBias ;
TYPE pic[28*28] ;
TYPE kernel5x5[5*5] ;
TYPE bias ;
int dir[25][2] ;
TYPE temp ;
int cnt ;
int curPixel ;
int i, j ;
int ramCnt ;
TYPE tempMaxPool ;
int dir2x2[4] ;
TYPE kernel5x5x6[5*5*6] ;
int depth ;
TYPE neuralSum ;
SC_CTOR(lenet)
{
readKernel = true ;
int p = 0 ;
dir2x2[0] = 0 ;
dir2x2[1] = 1 ;
dir2x2[2] = 24 ;
dir2x2[3] = 25 ;
for( p = 0 ; p < 5 ; ++p ) {
dir[p][0] = -2 ;
dir[p][1] = p-2 ;
}
for( ; p < 10 ; ++p ) {
dir[p][0] = -1 ;
dir[p][1] = p-7 ;
}
for( ; p < 15 ; ++p ) {
dir[p][0] = 0 ;
dir[p][1] = p-12 ;
}
for( ; p < 20 ; ++p ) {
dir[p][0] = 1 ;
dir[p][1] = p-17 ;
}
for( ; p < 25 ; ++p ) {
dir[p][0] = 2 ;
dir[p][1] = p-22 ;
}
fin.open(INPUT_FILE);
float f ;
for( p = 0 ; fin >> f ; ++p )
pic[p] = f/255 ;
SC_METHOD(le);
sensitive << clock.neg();
}
};
|
/*
* Copyright (c) 2019 Sekhar Bhattacharya
*
* SPDX-License-Identifier: MIT
*/
#include <systemc.h>
#include "utils.h"
template <int sram_size>
SC_MODULE(Sram) {
sc_in<uint32_t> i_sram_addr;
sc_in<uint32_t> i_sram_dq;
sc_out<uint32_t> o_sram_dq;
sc_in<bool> i_sram_ce_n;
sc_in<bool> i_sram_we_n;
sc_in<bool> i_sram_oe_n;
sc_in<bool> i_sram_ub_n;
sc_in<bool> i_sram_lb_n;
SC_CTOR(Sram) {
SC_METHOD(process);
sensitive << i_sram_addr << i_sram_dq << i_sram_we_n << i_sram_ce_n << i_sram_oe_n << i_sram_ub_n << i_sram_lb_n;
m_sram = new uint16_t[sram_size >> 1];
dont_initialize();
}
void trace_all(sc_trace_file *tf, const std::string& parent_name);
void load_hex(const std::string& filename);
void load_bin(const std::string& filename);
void dump_mem(procyon::utils::dump_format_t group_fmt = procyon::utils::DUMP_FORMAT_4B, procyon::utils::dump_format_t line_fmt = procyon::utils::DUMP_FORMAT_16B);
~Sram();
private:
uint16_t* m_sram;
void process();
};
template <int sram_size>
Sram<sram_size>::~Sram() {
if (m_sram != NULL) delete m_sram;
}
template <int sram_size>
void Sram<sram_size>::trace_all(sc_trace_file *tf, const std::string& parent_name) {
const std::string module_name = parent_name+"."+name();
sc_trace(tf, i_sram_addr, module_name+".i_sram_addr");
sc_trace(tf, i_sram_dq, module_name+".i_sram_dq");
sc_trace(tf, o_sram_dq, module_name+".o_sram_dq");
sc_trace(tf, i_sram_ce_n, module_name+".i_sram_ce_n");
sc_trace(tf, i_sram_we_n, module_name+".i_sram_we_n");
sc_trace(tf, i_sram_oe_n, module_name+".i_sram_oe_n");
sc_trace(tf, i_sram_ub_n, module_name+".i_sram_ub_n");
sc_trace(tf, i_sram_lb_n, module_name+".i_sram_lb_n");
}
template <int sram_size>
void Sram<sram_size>::process() {
uint32_t addr = i_sram_addr.read();
bool we_n = i_sram_we_n.read();
uint8_t sram_lb = i_sram_lb_n.read() ? 0 : m_sram[addr] & 0xff;
uint8_t sram_ub = i_sram_ub_n.read() ? 0 : (m_sram[addr] >> 8) & 0xff;
o_sram_dq.write((sram_ub << 8) | sram_lb);
if (!we_n) {
uint16_t data_in = i_sram_dq.read();
sram_lb = i_sram_lb_n.read() ? m_sram[addr] & 0xff : data_in & 0xff;
sram_ub = i_sram_ub_n.read() ? (m_sram[addr] >> 8) & 0xff : (data_in >> 8) & 0xff;
m_sram[addr] = (sram_ub << 8) | sram_lb;
}
}
template <int sram_size>
void Sram<sram_size>::load_hex(const std::string& filename) {
procyon::utils::load_hex(filename, (uint8_t*)m_sram, sram_size);
}
template <int sram_size>
void Sram<sram_size>::load_bin(const std::string& filename) {
procyon::utils::load_bin(filename, (uint8_t*)m_sram, sram_size);
}
template <int sram_size>
void Sram<sram_size>::dump_mem(procyon::utils::dump_format_t group_fmt, procyon::utils::dump_format_t line_fmt) {
procyon::utils::dump_mem((uint8_t*)m_sram, sram_size, group_fmt, line_fmt);
}
|
//
//------------------------------------------------------------//
// Copyright 2009-2012 Mentor Graphics Corporation //
// All Rights Reserved Worldwid //
// //
// Licensed under the Apache License, Version 2.0 (the //
// "License"); you may not use this file except in //
// compliance with the License. You may obtain a copy of //
// the License at //
// //
// http://www.apache.org/licenses/LICENSE-2.0 //
// //
// Unless required by applicable law or agreed to in //
// writing, software distributed under the License is //
// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR //
// CONDITIONS OF ANY KIND, either express or implied. See //
// the License for the specific language governing //
// permissions and limitations under the License. //
//------------------------------------------------------------//
//-----------------------------------------------------------------------------
// Title- UVMC-based SC to SC Connections (not implemented yet)
//
// This example demonstrates connecting two SC components using UVMC.
//
// (see UVMC_Connections_SC2SC.png)
//
// In this example, we instantiate a <producer> and <consumer>
// sc_module. Then two ~uvmc_connect~ calls are made, one for each side of
// the connection. Because we use the same lookup string, "sc2sc", in each
// of these calls, UVMC will establish the connection during binding resolution
// at elaboration time.
//
// The connection must be valid, i.e. the port/export/interface types and
// transaction type must be compatible, else an elaboration-time error will
// result.
//
//-----------------------------------------------------------------------------
// (- inline source)
#include <systemc.h>
using namespace sc_core;
#include "consumer.h"
#include "producer.h"
#include "packet.h"
int sc_main(int argc, char* argv[])
{
producer prod("prod");
consumer cons("cons");
uvmc_connect(prod.out, "sc2sc");
uvmc_connect(cons.in, "sc2sc");
sc_start(-1);
return 0;
}
|
// ================================================================
// NVDLA Open Source Project
//
// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
// NVDLA Open Hardware License; Check "LICENSE" which comes with
// this distribution for more information.
// ================================================================
// File Name: log.h
#ifndef __LOG_H__
#define __LOG_H__
#include <string.h>
#include <systemc.h>
#if defined(__cplusplus)
// some c++ headers for csl
#include <iostream> // for ostream, cerr
#include <sstream>
#include <cstdlib> // for std::abort()
#endif
// FIXME: there're 2 strrchr, might not good for performance;
#define __FILENAME__ (strrchr(__FILE__, '/') ? (strrchr(__FILE__, '/') + 1):__FILE__)
#define MSG_BUF_SIZE 2048
#define cslDebugInternal(lvl, ...) do {\
char msg_buf[MSG_BUF_SIZE]; \
int pos = snprintf(msg_buf, MSG_BUF_SIZE, "%d:", __LINE__); \
snprintf(msg_buf + pos, MSG_BUF_SIZE - pos, __VA_ARGS__); \
SC_REPORT_INFO_VERB(__FILENAME__, msg_buf, SC_DEBUG ); \
} while(0)
#define cslDebug(args) cslDebugInternal args
#define cslInfoInternal(...) do {\
char msg_buf[MSG_BUF_SIZE]; \
int pos = snprintf(msg_buf, MSG_BUF_SIZE, "%d:", __LINE__); \
snprintf(msg_buf + pos, MSG_BUF_SIZE - pos, __VA_ARGS__); \
SC_REPORT_INFO_VERB(__FILENAME__, msg_buf, SC_FULL ); \
} while(0)
#define cslInfo(args) cslInfoInternal args
#define FAILInternal(...) do {\
char msg_buf[MSG_BUF_SIZE]; \
int pos = snprintf(msg_buf, MSG_BUF_SIZE, "%d:", __LINE__); \
snprintf(msg_buf + pos, MSG_BUF_SIZE - pos, __VA_ARGS__); \
SC_REPORT_INFO(__FILENAME__, msg_buf ); \
} while(0)
#define FAIL(args) FAILInternal args
#define Fail(...) FAILInternal(__VA_ARGS__)
#define cslAssert(expr) do {\
sc_assert(expr ); \
} while(0)
#endif
|
// ================================================================
// NVDLA Open Source Project
//
// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
// NVDLA Open Hardware License; Check "LICENSE" which comes with
// this distribution for more information.
// ================================================================
// File Name: log.h
#ifndef __LOG_H__
#define __LOG_H__
#include <string.h>
#include <systemc.h>
#if defined(__cplusplus)
// some c++ headers for csl
#include <iostream> // for ostream, cerr
#include <sstream>
#include <cstdlib> // for std::abort()
#endif
// FIXME: there're 2 strrchr, might not good for performance;
#define __FILENAME__ (strrchr(__FILE__, '/') ? (strrchr(__FILE__, '/') + 1):__FILE__)
#define MSG_BUF_SIZE 2048
#define cslDebugInternal(lvl, ...) do {\
char msg_buf[MSG_BUF_SIZE]; \
int pos = snprintf(msg_buf, MSG_BUF_SIZE, "%d:", __LINE__); \
snprintf(msg_buf + pos, MSG_BUF_SIZE - pos, __VA_ARGS__); \
SC_REPORT_INFO_VERB(__FILENAME__, msg_buf, SC_DEBUG ); \
} while(0)
#define cslDebug(args) cslDebugInternal args
#define cslInfoInternal(...) do {\
char msg_buf[MSG_BUF_SIZE]; \
int pos = snprintf(msg_buf, MSG_BUF_SIZE, "%d:", __LINE__); \
snprintf(msg_buf + pos, MSG_BUF_SIZE - pos, __VA_ARGS__); \
SC_REPORT_INFO_VERB(__FILENAME__, msg_buf, SC_FULL ); \
} while(0)
#define cslInfo(args) cslInfoInternal args
#define FAILInternal(...) do {\
char msg_buf[MSG_BUF_SIZE]; \
int pos = snprintf(msg_buf, MSG_BUF_SIZE, "%d:", __LINE__); \
snprintf(msg_buf + pos, MSG_BUF_SIZE - pos, __VA_ARGS__); \
SC_REPORT_INFO(__FILENAME__, msg_buf ); \
} while(0)
#define FAIL(args) FAILInternal args
#define Fail(...) FAILInternal(__VA_ARGS__)
#define cslAssert(expr) do {\
sc_assert(expr ); \
} while(0)
#endif
|
#ifndef IEEE_H
#define IEEE_H
#include "systemc.h"
//-----------------------------------------------------------------------------
// IEEE floating-point type
//-----------------------------------------------------------------------------
template<int E, int F>
struct fp_t {
static constexpr int ebits = E; // exponent bits
static constexpr int fbits = F; // fraction bits
static constexpr int bits = 1+E+F; // total bits
// exponent bias
// When E (bits) = 8, ebias = 127
// When E (bits) = 11, ebias = 1023
static constexpr int ebias = (1 << (E-1))-1;
typedef sc_int <bits> si_t;
typedef sc_uint<bits> ui_t;
typedef sc_uint<F> frac_t;
typedef sc_uint<E> expo_t;
typedef sc_uint<1> sign_t;
frac_t frac;
expo_t expo; // biased by ebias
sign_t sign;
fp_t(ui_t ui)
{
(sign,expo,frac) = ui;
}
fp_t(sc_dt::uint64 ui = 0)
{
(sign,expo,frac) = ui;
}
fp_t& operator=(ui_t ui)
{
(sign,expo,frac) = ui;
return *this;
}
operator ui_t() const
{
return (sign,expo,frac);
}
bool operator==(const fp_t& fp)
{
return
this->frac == fp.frac &&
this->expo == fp.expo &&
this->sign == fp.sign;
}
//---------- conditional int types ----------//
typedef typename std::conditional<bits==32, int, long long>::type sic_t;
typedef typename std::conditional<bits==32, unsigned int, unsigned long long>::type uic_t;
#if !defined(__SYNTHESIS__)
//---------- real_t ----------//
typedef typename std::conditional<bits==32, float, double>::type real_t;
explicit fp_t(real_t r)
{
sc_dt::uint64 ui = 0;
std::memcpy(&ui, &r, sizeof(r));
(sign,expo,frac) = ui;
}
fp_t& operator=(real_t r)
{
sc_dt::uint64 ui = 0;
std::memcpy(&ui, &r, sizeof(r));
(sign,expo,frac) = ui;
return *this;
}
real_t to_real() const
{
sc_dt::uint64 ui = (sign,expo,frac);
real_t r;
std::memcpy(&r, &ui, sizeof(r));
return r;
}
#endif // end !__SYNTHESIS__
};
template<int E, int F>
inline std::ostream& operator<<(std::ostream& os, const fp_t<E,F>& fp)
{
os << hex << fp.sign << ':' << fp.expo << ':' << fp.frac;
#if !defined(__SYNTHESIS__)
os << ", " << fp.to_real();
#endif // end !__SYNTHESIS__
return os;
}
template<int E, int F>
void sc_trace(sc_trace_file* tf, const fp_t<E,F>& ob, const std::string& nm)
{
sc_trace(tf, ob.frac, nm+".frac");
sc_trace(tf, ob.expo, nm+".expo");
sc_trace(tf, ob.sign, nm+".sign");
}
#endif // IEEE_H
|
#ifndef SDRAM_IO_H
#define SDRAM_IO_H
#include <systemc.h>
//----------------------------------------------------------------
// Interface (master)
//----------------------------------------------------------------
class sdram_io_master
{
public:
// Members
sc_uint <1> CLK;
sc_uint <1> CKE;
sc_uint <1> CS;
sc_uint <1> RAS;
sc_uint <1> CAS;
sc_uint <1> WE;
sc_uint <2> DQM;
sc_uint <13> ADDR;
sc_uint <2> BA;
sc_uint <16> DATA_OUTPUT;
sc_uint <1> DATA_OUT_EN;
// Construction
sdram_io_master() { init(); }
void init(void)
{
CLK = 0;
CKE = 0;
CS = 0;
RAS = 0;
CAS = 0;
WE = 0;
DQM = 0;
ADDR = 0;
BA = 0;
DATA_OUTPUT = 0;
DATA_OUT_EN = 0;
}
bool operator == (const sdram_io_master & v) const
{
bool eq = true;
eq &= (CLK == v.CLK);
eq &= (CKE == v.CKE);
eq &= (CS == v.CS);
eq &= (RAS == v.RAS);
eq &= (CAS == v.CAS);
eq &= (WE == v.WE);
eq &= (DQM == v.DQM);
eq &= (ADDR == v.ADDR);
eq &= (BA == v.BA);
eq &= (DATA_OUTPUT == v.DATA_OUTPUT);
eq &= (DATA_OUT_EN == v.DATA_OUT_EN);
return eq;
}
friend void sc_trace(sc_trace_file *tf, const sdram_io_master & v, const std::string & path)
{
sc_trace(tf,v.CLK, path + "/clk");
sc_trace(tf,v.CKE, path + "/cke");
sc_trace(tf,v.CS, path + "/cs");
sc_trace(tf,v.RAS, path + "/ras");
sc_trace(tf,v.CAS, path + "/cas");
sc_trace(tf,v.WE, path + "/we");
sc_trace(tf,v.DQM, path + "/dqm");
sc_trace(tf,v.ADDR, path + "/addr");
sc_trace(tf,v.BA, path + "/ba");
sc_trace(tf,v.DATA_OUTPUT, path + "/data_output");
sc_trace(tf,v.DATA_OUT_EN, path + "/data_out_en");
}
friend ostream& operator << (ostream& os, sdram_io_master const & v)
{
os << hex << "CLK: " << v.CLK << " ";
os << hex << "CKE: " << v.CKE << " ";
os << hex << "CS: " << v.CS << " ";
os << hex << "RAS: " << v.RAS << " ";
os << hex << "CAS: " << v.CAS << " ";
os << hex << "WE: " << v.WE << " ";
os << hex << "DQM: " << v.DQM << " ";
os << hex << "ADDR: " << v.ADDR << " ";
os << hex << "BA: " << v.BA << " ";
os << hex << "DATA_OUTPUT: " << v.DATA_OUTPUT << " ";
os << hex << "DATA_OUT_EN: " << v.DATA_OUT_EN << " ";
return os;
}
friend istream& operator >> ( istream& is, sdram_io_master & val)
{
// Not implemented
return is;
}
};
#define MEMBER_COPY_SDRAM_IO_MASTER(s,d) do { \
s.CLK = d.CLK; \
s.CKE = d.CKE; \
s.CS = d.CS; \
s.RAS = d.RAS; \
s.CAS = d.CAS; \
s.WE = d.WE; \
s.DQM = d.DQM; \
s.ADDR = d.ADDR; \
s.BA = d.BA; \
s.DATA_OUTPUT = d.DATA_OUTPUT; \
s.DATA_OUT_EN = d.DATA_OUT_EN; \
} while (0)
//----------------------------------------------------------------
// Interface (slave)
//----------------------------------------------------------------
class sdram_io_slave
{
public:
// Members
sc_uint <16> DATA_INPUT;
// Construction
sdram_io_slave() { init(); }
void init(void)
{
DATA_INPUT = 0;
}
bool operator == (const sdram_io_slave & v) const
{
bool eq = true;
eq &= (DATA_INPUT == v.DATA_INPUT);
return eq;
}
friend void sc_trace(sc_trace_file *tf, const sdram_io_slave & v, const std::string & path)
{
sc_trace(tf,v.DATA_INPUT, path + "/data_input");
}
friend ostream& operator << (ostream& os, sdram_io_slave const & v)
{
os << hex << "DATA_INPUT: " << v.DATA_INPUT << " ";
return os;
}
friend istream& operator >> ( istream& is, sdram_io_slave & val)
{
// Not implemented
return is;
}
};
#define MEMBER_COPY_SDRAM_IO_SLAVE(s,d) do { \
s.DATA_INPUT = d.DATA_INPUT; \
} while (0)
#endif
|
#include <systemc.h>
#include "interfaces.cpp"
#include "fila.h"
#include "flit.h"
/* portas/sinais feitos de acordo com a imagem do roteador SoCIN.
* Dúvidas: como posso acionar os outros métodos via SC_METHOD? Pq a lista de sensibilidade está ok, mas não está acionando o método de leitura do buffer (apenas adição)
*
*/
class Buffer : public sc_module {
private:
sc_int<32> length;
fila posicoes(flit);
sc_in<sc_int<34>> din; // data + bop + eop
sc_in<sc_int<32>> wr;
sc_in<sc_int<32>> rd;
sc_out<sc_int<32>> wok;
sc_out<sc_int<32>> dout;
sc_out<sc_int<32>> rok;
int prioridade = 0; // Ver se realmente é necessário...
public:
sc_int<32> isFull();
sc_int<32> isEmpty();
void add();
void remove();
Buffer(sc_int<32>);
SC_CTOR(Buffer){
SC_METHOD(add);
sensitive << din;
sensitive << wr;
sensitive << rd;
}
};
|
/******************************************************************************
* *
* Copyright (C) 2023 MachineWare GmbH *
* All Rights Reserved *
* *
* This is work is licensed under the terms described in the LICENSE file *
* found in the root directory of this source tree. *
* *
******************************************************************************/
#ifndef VCML_PROTOCOLS_TLM_BASE_H
#define VCML_PROTOCOLS_TLM_BASE_H
#include "vcml/core/types.h"
#include "vcml/core/systemc.h"
#include "vcml/core/range.h"
#include "vcml/core/thctl.h"
#include "vcml/core/module.h"
#include "vcml/protocols/base.h"
#include "vcml/protocols/tlm_sbi.h"
#include "vcml/protocols/tlm_exmon.h"
#include "vcml/protocols/tlm_stubs.h"
#include "vcml/protocols/tlm_adapters.h"
namespace vcml {
class tlm_base_initiator_socket : public tlm::tlm_initiator_socket<>,
public hierarchy_element
{
private:
tlm_target_stub* m_stub;
public:
tlm_base_initiator_socket(const char* nm,
address_space as = VCML_AS_DEFAULT):
tlm::tlm_initiator_socket<>(nm), hierarchy_element(), m_stub() {}
virtual ~tlm_base_initiator_socket() { delete m_stub; }
VCML_KIND(tlm_base_initiator_socket);
bool is_stubbed() const { return m_stub != nullptr; }
void stub(tlm_response_status r = TLM_ADDRESS_ERROR_RESPONSE) {
VCML_ERROR_ON(m_stub, "socket %s already stubbed", name());
auto guard = get_hierarchy_scope();
m_stub = new tlm_target_stub(strcat(basename(), "_stub").c_str(), r);
tlm::tlm_initiator_socket<>::bind(m_stub->in);
}
};
class tlm_base_target_socket : public tlm::tlm_target_socket<>,
public hierarchy_element
{
private:
tlm_initiator_stub* m_stub;
public:
tlm_base_target_socket(const char* nm, address_space as = VCML_AS_DEFAULT):
tlm::tlm_target_socket<>(nm), hierarchy_element(), m_stub() {}
virtual ~tlm_base_target_socket() { delete m_stub; }
VCML_KIND(tlm_base_target_socket);
bool is_stubbed() const { return m_stub != nullptr; }
void stub() {
VCML_ERROR_ON(m_stub, "socket %s already stubbed", name());
auto guard = get_hierarchy_scope();
m_stub = new tlm_initiator_stub(strcat(basename(), "_stub").c_str());
m_stub->out.bind(*this);
}
};
using tlm_base_initiator_array = socket_array<tlm_base_initiator_socket>;
using tlm_base_target_array = socket_array<tlm_base_target_socket>;
} // namespace vcml
#endif
|
#ifndef _TB_QVM_H_
#define _TB_QVM_H_
#include <systemc.h>
#include <iomanip>
#include <iostream>
#include "global_json.h"
#include "logger_wrapper.h"
#include "q_data_type.h"
#include "quma_tb_base.h"
#include "qvm.h"
using namespace sc_core;
using namespace sc_dt;
namespace cactus {
using sc_core::sc_in;
using sc_core::sc_out;
using sc_core::sc_signal;
using sc_core::sc_vector;
using sc_dt::sc_uint;
class QVM_TB : public Quma_tb_base {
protected: // modules
QVM qvm;
protected: // signals
// it seems that we need to add no signals.
protected:
// void do_test();
protected:
unsigned int m_num_sim_cycles;
int m_num_qubits;
void config();
public:
QVM_TB(const sc_core::sc_module_name& n, unsigned int num_sim_cycles_ = 3000);
SC_HAS_PROCESS(QVM_TB);
};
} // namespace cactus
#endif
|
#ifndef xtea_RTL_TESTBENCH_H
#define xtea_RTL_TESTBENCH_H
#include <systemc.h>
SC_MODULE(xtea_RTL_testbench) {
private:
void run();
public:
sc_in_clk clk;
sc_out< bool > rst;
sc_in<sc_uint<1> > dout_rdy; // output from xtea module
sc_in<sc_uint<32> > result0_in;
sc_in<sc_uint<32> > result1_in;
sc_out<sc_uint<1> > din_rdy; // input for xtea module
sc_out<sc_uint<32> > word0_out;
sc_out<sc_uint<32> > word1_out;
sc_out<sc_uint<32> > key0_out;
sc_out<sc_uint<32> > key1_out;
sc_out<sc_uint<32> > key2_out;
sc_out<sc_uint<32> > key3_out;
sc_out< bool > mode_out;
SC_CTOR(xtea_RTL_testbench) {
SC_THREAD(run);
sensitive << clk.pos();
}
};
#endif
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2019.1
// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _dct_HH_
#define _dct_HH_
#include "systemc.h"
#include "AESL_pkg.h"
#include "read_data.h"
#include "Loop_Row_DCT_Loop_pr.h"
#include "Loop_Xpose_Row_Outer.h"
#include "Loop_Col_DCT_Loop_pr.h"
#include "Loop_Xpose_Col_Outer.h"
#include "write_data.h"
#include "dct_row_outbuf_i.h"
#include "dct_col_inbuf_0.h"
namespace ap_rtl {
struct dct : public sc_module {
// Port declarations 26
sc_in_clk ap_clk;
sc_in< sc_logic > ap_rst;
sc_out< sc_lv<6> > input_r_address0;
sc_out< sc_logic > input_r_ce0;
sc_out< sc_lv<16> > input_r_d0;
sc_in< sc_lv<16> > input_r_q0;
sc_out< sc_logic > input_r_we0;
sc_out< sc_lv<6> > input_r_address1;
sc_out< sc_logic > input_r_ce1;
sc_out< sc_lv<16> > input_r_d1;
sc_in< sc_lv<16> > input_r_q1;
sc_out< sc_logic > input_r_we1;
sc_out< sc_lv<6> > output_r_address0;
sc_out< sc_logic > output_r_ce0;
sc_out< sc_lv<16> > output_r_d0;
sc_in< sc_lv<16> > output_r_q0;
sc_out< sc_logic > output_r_we0;
sc_out< sc_lv<6> > output_r_address1;
sc_out< sc_logic > output_r_ce1;
sc_out< sc_lv<16> > output_r_d1;
sc_in< sc_lv<16> > output_r_q1;
sc_out< sc_logic > output_r_we1;
sc_in< sc_logic > ap_start;
sc_out< sc_logic > ap_done;
sc_out< sc_logic > ap_ready;
sc_out< sc_logic > ap_idle;
sc_signal< sc_logic > ap_var_for_const2;
sc_signal< sc_logic > ap_var_for_const0;
sc_signal< sc_lv<16> > ap_var_for_const1;
// Module declarations
dct(sc_module_name name);
SC_HAS_PROCESS(dct);
~dct();
sc_trace_file* mVcdFile;
ofstream mHdltvinHandle;
ofstream mHdltvoutHandle;
dct_row_outbuf_i* row_outbuf_i_U;
dct_row_outbuf_i* col_outbuf_i_U;
dct_col_inbuf_0* col_inbuf_0_U;
dct_col_inbuf_0* col_inbuf_1_U;
dct_col_inbuf_0* col_inbuf_2_U;
dct_col_inbuf_0* col_inbuf_3_U;
dct_col_inbuf_0* col_inbuf_4_U;
dct_col_inbuf_0* col_inbuf_5_U;
dct_col_inbuf_0* col_inbuf_6_U;
dct_col_inbuf_0* col_inbuf_7_U;
dct_col_inbuf_0* buf_2d_in_0_U;
dct_col_inbuf_0* buf_2d_in_1_U;
dct_col_inbuf_0* buf_2d_in_2_U;
dct_col_inbuf_0* buf_2d_in_3_U;
dct_col_inbuf_0* buf_2d_in_4_U;
dct_col_inbuf_0* buf_2d_in_5_U;
dct_col_inbuf_0* buf_2d_in_6_U;
dct_col_inbuf_0* buf_2d_in_7_U;
dct_row_outbuf_i* buf_2d_out_U;
read_data* read_data_U0;
Loop_Row_DCT_Loop_pr* Loop_Row_DCT_Loop_pr_U0;
Loop_Xpose_Row_Outer* Loop_Xpose_Row_Outer_U0;
Loop_Col_DCT_Loop_pr* Loop_Col_DCT_Loop_pr_U0;
Loop_Xpose_Col_Outer* Loop_Xpose_Col_Outer_U0;
write_data* write_data_U0;
sc_signal< sc_lv<16> > row_outbuf_i_i_q0;
sc_signal< sc_lv<16> > row_outbuf_i_t_q0;
sc_signal< sc_lv<16> > col_outbuf_i_i_q0;
sc_signal< sc_lv<16> > col_outbuf_i_t_q0;
sc_signal< sc_lv<16> > col_inbuf_0_i_q0;
sc_signal< sc_lv<16> > col_inbuf_0_t_q0;
sc_signal< sc_lv<16> > col_inbuf_1_i_q0;
sc_signal< sc_lv<16> > col_inbuf_1_t_q0;
sc_signal< sc_lv<16> > col_inbuf_2_i_q0;
sc_signal< sc_lv<16> > col_inbuf_2_t_q0;
sc_signal< sc_lv<16> > col_inbuf_3_i_q0;
sc_signal< sc_lv<16> > col_inbuf_3_t_q0;
sc_signal< sc_lv<16> > col_inbuf_4_i_q0;
sc_signal< sc_lv<16> > col_inbuf_4_t_q0;
sc_signal< sc_lv<16> > col_inbuf_5_i_q0;
sc_signal< sc_lv<16> > col_inbuf_5_t_q0;
sc_signal< sc_lv<16> > col_inbuf_6_i_q0;
sc_signal< sc_lv<16> > col_inbuf_6_t_q0;
sc_signal< sc_lv<16> > col_inbuf_7_i_q0;
sc_signal< sc_lv<16> > col_inbuf_7_t_q0;
sc_signal< sc_lv<16> > buf_2d_in_0_i_q0;
sc_signal< sc_lv<16> > buf_2d_in_0_t_q0;
sc_signal< sc_lv<16> > buf_2d_in_1_i_q0;
sc_signal< sc_lv<16> > buf_2d_in_1_t_q0;
sc_signal< sc_lv<16> > buf_2d_in_2_i_q0;
sc_signal< sc_lv<16> > buf_2d_in_2_t_q0;
sc_signal< sc_lv<16> > buf_2d_in_3_i_q0;
sc_signal< sc_lv<16> > buf_2d_in_3_t_q0;
sc_signal< sc_lv<16> > buf_2d_in_4_i_q0;
sc_signal< sc_lv<16> > buf_2d_in_4_t_q0;
sc_signal< sc_lv<16> > buf_2d_in_5_i_q0;
sc_signal< sc_lv<16> > buf_2d_in_5_t_q0;
sc_signal< sc_lv<16> > buf_2d_in_6_i_q0;
sc_signal< sc_lv<16> > buf_2d_in_6_t_q0;
sc_signal< sc_lv<16> > buf_2d_in_7_i_q0;
sc_signal< sc_lv<16> > buf_2d_in_7_t_q0;
sc_signal< sc_lv<16> > buf_2d_out_i_q0;
sc_signal< sc_lv<16> > buf_2d_out_t_q0;
sc_signal< sc_logic > read_data_U0_ap_start;
sc_signal< sc_logic > read_data_U0_ap_done;
sc_signal< sc_logic > read_data_U0_ap_continue;
sc_signal< sc_logic > read_data_U0_ap_idle;
sc_signal< sc_logic > read_data_U0_ap_ready;
sc_signal< sc_lv<6> > read_data_U0_input_r_address0;
sc_signal< sc_logic > read_data_U0_input_r_ce0;
sc_signal< sc_lv<3> > read_data_U0_buf_0_address0;
sc_signal< sc_logic > read_data_U0_buf_0_ce0;
sc_signal< sc_logic > read_data_U0_buf_0_we0;
sc_signal< sc_lv<16> > read_data_U0_buf_0_d0;
sc_signal< sc_lv<3> > read_data_U0_buf_1_address0;
sc_signal< sc_logic > read_data_U0_buf_1_ce0;
sc_signal< sc_logic > read_data_U0_buf_1_we0;
sc_signal< sc_lv<16> > read_data_U0_buf_1_d0;
sc_signal< sc_lv<3> > read_data_U0_buf_2_address0;
sc_signal< sc_logic > read_data_U0_buf_2_ce0;
sc_signal< sc_logic > read_data_U0_buf_2_we0;
sc_signal< sc_lv<16> > read_data_U0_buf_2_d0;
sc_signal< sc_lv<3> > read_data_U0_buf_3_address0;
sc_signal< sc_logic > read_data_U0_buf_3_ce0;
sc_signal< sc_logic > read_data_U0_buf_3_we0;
sc_signal< sc_lv<16> > read_data_U0_buf_3_d0;
sc_signal< sc_lv<3> > read_data_U0_buf_4_address0;
sc_signal< sc_logic > read_data_U0_buf_4_ce0;
sc_signal< sc_logic > read_data_U0_buf_4_we0;
sc_signal< sc_lv<16> > read_data_U0_buf_4_d0;
sc_signal< sc_lv<3> > read_data_U0_buf_5_address0;
sc_signal< sc_logic > read_data_U0_buf_5_ce0;
sc_signal< sc_logic > read_data_U0_buf_5_we0;
sc_signal< sc_lv<16> > read_data_U0_buf_5_d0;
sc_signal< sc_lv<3> > read_data_U0_buf_6_address0;
sc_signal< sc_logic > read_data_U0_buf_6_ce0;
sc_signal< sc_logic > read_data_U0_buf_6_we0;
sc_signal< sc_lv<16> > read_data_U0_buf_6_d0;
sc_signal< sc_lv<3> > read_data_U0_buf_7_address0;
sc_signal< sc_logic > read_data_U0_buf_7_ce0;
sc_signal< sc_logic > read_data_U0_buf_7_we0;
sc_signal< sc_lv<16> > read_data_U0_buf_7_d0;
sc_signal< sc_logic > ap_channel_done_buf_2d_in_7;
sc_signal< sc_logic > read_data_U0_buf_7_full_n;
sc_signal< sc_logic > ap_sync_reg_channel_write_buf_2d_in_7;
sc_signal< sc_logic > ap_sync_channel_write_buf_2d_in_7;
sc_signal< sc_logic > ap_channel_done_buf_2d_in_6;
sc_signal< sc_logic > read_data_U0_buf_6_full_n;
sc_signal< sc_logic > ap_sync_reg_channel_write_buf_2d_in_6;
sc_signal< sc_logic > ap_sync_channel_write_buf_2d_in_6;
sc_signal< sc_logic > ap_channel_done_buf_2d_in_5;
sc_signal< sc_logic > read_data_U0_buf_5_full_n;
sc_signal< sc_logic > ap_sync_reg_channel_write_buf_2d_in_5;
sc_signal< sc_logic > ap_sync_channel_write_buf_2d_in_5;
sc_signal< sc_logic > ap_channel_done_buf_2d_in_4;
sc_signal< sc_logic > read_data_U0_buf_4_full_n;
sc_signal< sc_logic > ap_sync_reg_channel_write_buf_2d_in_4;
sc_signal< sc_logic > ap_sync_channel_write_buf_2d_in_4;
sc_signal< sc_logic > ap_channel_done_buf_2d_in_3;
sc_signal< sc_logic > read_data_U0_buf_3_full_n;
sc_signal< sc_logic > ap_sync_reg_channel_write_buf_2d_in_3;
sc_signal< sc_logic > ap_sync_channel_write_buf_2d_in_3;
sc_signal< sc_logic > ap_channel_done_buf_2d_in_2;
sc_signal< sc_logic > read_data_U0_buf_2_full_n;
sc_signal< sc_logic > ap_sync_reg_channel_write_buf_2d_in_2;
sc_signal< sc_logic > ap_sync_channel_write_buf_2d_in_2;
sc_signal< sc_logic > ap_channel_done_buf_2d_in_1;
sc_signal< sc_logic > read_data_U0_buf_1_full_n;
sc_signal< sc_logic > ap_sync_reg_channel_write_buf_2d_in_1;
sc_signal< sc_logic > ap_sync_channel_write_buf_2d_in_1;
sc_signal< sc_logic > ap_channel_done_buf_2d_in_0;
sc_signal< sc_logic > read_data_U0_buf_0_full_n;
sc_signal< sc_logic > ap_sync_reg_channel_write_buf_2d_in_0;
sc_signal< sc_logic > ap_sync_channel_write_buf_2d_in_0;
sc_signal< sc_logic > Loop_Row_DCT_Loop_pr_U0_ap_start;
sc_signal< sc_logic > Loop_Row_DCT_Loop_pr_U0_ap_done;
sc_signal< sc_logic > Loop_Row_DCT_Loop_pr_U0_ap_continue;
sc_signal< sc_logic > Loop_Row_DCT_Loop_pr_U0_ap_idle;
sc_signal< sc_logic > Loop_Row_DCT_Loop_pr_U0_ap_ready;
sc_signal< sc_lv<3> > Loop_Row_DCT_Loop_pr_U0_buf_2d_in_0_address0;
sc_signal< sc_logic > Loop_Row_DCT_Loop_pr_U0_buf_2d_in_0_ce0;
sc_signal< sc_lv<3> > Loop_Row_DCT_Loop_pr_U0_buf_2d_in_1_address0;
sc_signal< sc_logic > Loop_Row_DCT_Loop_pr_U0_buf_2d_in_1_ce0;
sc_signal< sc_lv<3> > Loop_Row_DCT_Loop_pr_U0_buf_2d_in_2_address0;
sc_signal< sc_logic > Loop_Row_DCT_Loop_pr_U0_buf_2d_in_2_ce0;
sc_signal< sc_lv<3> > Loop_Row_DCT_Loop_pr_U0_buf_2d_in_3_address0;
sc_signal< sc_logic > Loop_Row_DCT_Loop_pr_U0_buf_2d_in_3_ce0;
sc_signal< sc_lv<3> > Loop_Row_DCT_Loop_pr_U0_buf_2d_in_4_address0;
sc_signal< sc_logic > Loop_Row_DCT_Loop_pr_U0_buf_2d_in_4_ce0;
sc_signal< sc_lv<3> > Loop_Row_DCT_Loop_pr_U0_buf_2d_in_5_address0;
sc_signal< sc_logic > Loop_Row_DCT_Loop_pr_U0_buf_2d_in_5_ce0;
sc_signal< sc_lv<3> > Loop_Row_DCT_Loop_pr_U0_buf_2d_in_6_address0;
sc_signal< sc_logic > Loop_Row_DCT_Loop_pr_U0_buf_2d_in_6_ce0;
sc_signal< sc_lv<3> > Loop_Row_DCT_Loop_pr_U0_buf_2d_in_7_address0;
sc_signal< sc_logic > Loop_Row_DCT_Loop_pr_U0_buf_2d_in_7_ce0;
sc_signal< sc_lv<6> > Loop_Row_DCT_Loop_pr_U0_row_outbuf_i_address0;
sc_signal< sc_logic > Loop_Row_DCT_Loop_pr_U0_row_outbuf_i_ce0;
sc_signal< sc_logic > Loop_Row_DCT_Loop_pr_U0_row_outbuf_i_we0;
sc_signal< sc_lv<16> > Loop_Row_DCT_Loop_pr_U0_row_outbuf_i_d0;
sc_signal< sc_logic > ap_channel_done_row_outbuf_i;
sc_signal< sc_logic > Loop_Row_DCT_Loop_pr_U0_row_outbuf_i_full_n;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_ap_start;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_ap_done;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_ap_continue;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_ap_idle;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_ap_ready;
sc_signal< sc_lv<6> > Loop_Xpose_Row_Outer_U0_row_outbuf_i_address0;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_row_outbuf_i_ce0;
sc_signal< sc_lv<3> > Loop_Xpose_Row_Outer_U0_col_inbuf_0_address0;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_col_inbuf_0_ce0;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_col_inbuf_0_we0;
sc_signal< sc_lv<16> > Loop_Xpose_Row_Outer_U0_col_inbuf_0_d0;
sc_signal< sc_lv<3> > Loop_Xpose_Row_Outer_U0_col_inbuf_1_address0;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_col_inbuf_1_ce0;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_col_inbuf_1_we0;
sc_signal< sc_lv<16> > Loop_Xpose_Row_Outer_U0_col_inbuf_1_d0;
sc_signal< sc_lv<3> > Loop_Xpose_Row_Outer_U0_col_inbuf_2_address0;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_col_inbuf_2_ce0;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_col_inbuf_2_we0;
sc_signal< sc_lv<16> > Loop_Xpose_Row_Outer_U0_col_inbuf_2_d0;
sc_signal< sc_lv<3> > Loop_Xpose_Row_Outer_U0_col_inbuf_3_address0;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_col_inbuf_3_ce0;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_col_inbuf_3_we0;
sc_signal< sc_lv<16> > Loop_Xpose_Row_Outer_U0_col_inbuf_3_d0;
sc_signal< sc_lv<3> > Loop_Xpose_Row_Outer_U0_col_inbuf_4_address0;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_col_inbuf_4_ce0;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_col_inbuf_4_we0;
sc_signal< sc_lv<16> > Loop_Xpose_Row_Outer_U0_col_inbuf_4_d0;
sc_signal< sc_lv<3> > Loop_Xpose_Row_Outer_U0_col_inbuf_5_address0;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_col_inbuf_5_ce0;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_col_inbuf_5_we0;
sc_signal< sc_lv<16> > Loop_Xpose_Row_Outer_U0_col_inbuf_5_d0;
sc_signal< sc_lv<3> > Loop_Xpose_Row_Outer_U0_col_inbuf_6_address0;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_col_inbuf_6_ce0;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_col_inbuf_6_we0;
sc_signal< sc_lv<16> > Loop_Xpose_Row_Outer_U0_col_inbuf_6_d0;
sc_signal< sc_lv<3> > Loop_Xpose_Row_Outer_U0_col_inbuf_7_address0;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_col_inbuf_7_ce0;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_col_inbuf_7_we0;
sc_signal< sc_lv<16> > Loop_Xpose_Row_Outer_U0_col_inbuf_7_d0;
sc_signal< sc_logic > ap_channel_done_col_inbuf_7;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_col_inbuf_7_full_n;
sc_signal< sc_logic > ap_sync_reg_channel_write_col_inbuf_7;
sc_signal< sc_logic > ap_sync_channel_write_col_inbuf_7;
sc_signal< sc_logic > ap_channel_done_col_inbuf_6;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_col_inbuf_6_full_n;
sc_signal< sc_logic > ap_sync_reg_channel_write_col_inbuf_6;
sc_signal< sc_logic > ap_sync_channel_write_col_inbuf_6;
sc_signal< sc_logic > ap_channel_done_col_inbuf_5;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_col_inbuf_5_full_n;
sc_signal< sc_logic > ap_sync_reg_channel_write_col_inbuf_5;
sc_signal< sc_logic > ap_sync_channel_write_col_inbuf_5;
sc_signal< sc_logic > ap_channel_done_col_inbuf_4;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_col_inbuf_4_full_n;
sc_signal< sc_logic > ap_sync_reg_channel_write_col_inbuf_4;
sc_signal< sc_logic > ap_sync_channel_write_col_inbuf_4;
sc_signal< sc_logic > ap_channel_done_col_inbuf_3;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_col_inbuf_3_full_n;
sc_signal< sc_logic > ap_sync_reg_channel_write_col_inbuf_3;
sc_signal< sc_logic > ap_sync_channel_write_col_inbuf_3;
sc_signal< sc_logic > ap_channel_done_col_inbuf_2;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_col_inbuf_2_full_n;
sc_signal< sc_logic > ap_sync_reg_channel_write_col_inbuf_2;
sc_signal< sc_logic > ap_sync_channel_write_col_inbuf_2;
sc_signal< sc_logic > ap_channel_done_col_inbuf_1;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_col_inbuf_1_full_n;
sc_signal< sc_logic > ap_sync_reg_channel_write_col_inbuf_1;
sc_signal< sc_logic > ap_sync_channel_write_col_inbuf_1;
sc_signal< sc_logic > ap_channel_done_col_inbuf_0;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_col_inbuf_0_full_n;
sc_signal< sc_logic > ap_sync_reg_channel_write_col_inbuf_0;
sc_signal< sc_logic > ap_sync_channel_write_col_inbuf_0;
sc_signal< sc_logic > Loop_Col_DCT_Loop_pr_U0_ap_start;
sc_signal< sc_logic > Loop_Col_DCT_Loop_pr_U0_ap_done;
sc_signal< sc_logic > Loop_Col_DCT_Loop_pr_U0_ap_continue;
sc_signal< sc_logic > Loop_Col_DCT_Loop_pr_U0_ap_idle;
sc_signal< sc_logic > Loop_Col_DCT_Loop_pr_U0_ap_ready;
sc_signal< sc_lv<3> > Loop_Col_DCT_Loop_pr_U0_col_inbuf_0_address0;
sc_signal< sc_logic > Loop_Col_DCT_Loop_pr_U0_col_inbuf_0_ce0;
sc_signal< sc_lv<3> > Loop_Col_DCT_Loop_pr_U0_col_inbuf_1_address0;
sc_signal< sc_logic > Loop_Col_DCT_Loop_pr_U0_col_inbuf_1_ce0;
sc_signal< sc_lv<3> > Loop_Col_DCT_Loop_pr_U0_col_inbuf_2_address0;
sc_signal< sc_logic > Loop_Col_DCT_Loop_pr_U0_col_inbuf_2_ce0;
sc_signal< sc_lv<3> > Loop_Col_DCT_Loop_pr_U0_col_inbuf_3_address0;
sc_signal< sc_logic > Loop_Col_DCT_Loop_pr_U0_col_inbuf_3_ce0;
sc_signal< sc_lv<3> > Loop_Col_DCT_Loop_pr_U0_col_inbuf_4_address0;
sc_signal< sc_logic > Loop_Col_DCT_Loop_pr_U0_col_inbuf_4_ce0;
sc_signal< sc_lv<3> > Loop_Col_DCT_Loop_pr_U0_col_inbuf_5_address0;
sc_signal< sc_logic > Loop_Col_DCT_Loop_pr_U0_col_inbuf_5_ce0;
sc_signal< sc_lv<3> > Loop_Col_DCT_Loop_pr_U0_col_inbuf_6_address0;
sc_signal< sc_logic > Loop_Col_DCT_Loop_pr_U0_col_inbuf_6_ce0;
sc_signal< sc_lv<3> > Loop_Col_DCT_Loop_pr_U0_col_inbuf_7_address0;
sc_signal< sc_logic > Loop_Col_DCT_Loop_pr_U0_col_inbuf_7_ce0;
sc_signal< sc_lv<6> > Loop_Col_DCT_Loop_pr_U0_col_outbuf_i_address0;
sc_signal< sc_logic > Loop_Col_DCT_Loop_pr_U0_col_outbuf_i_ce0;
sc_signal< sc_logic > Loop_Col_DCT_Loop_pr_U0_col_outbuf_i_we0;
sc_signal< sc_lv<16> > Loop_Col_DCT_Loop_pr_U0_col_outbuf_i_d0;
sc_signal< sc_logic > ap_channel_done_col_outbuf_i;
sc_signal< sc_logic > Loop_Col_DCT_Loop_pr_U0_col_outbuf_i_full_n;
sc_signal< sc_logic > Loop_Xpose_Col_Outer_U0_ap_start;
sc_signal< sc_logic > Loop_Xpose_Col_Outer_U0_ap_done;
sc_signal< sc_logic > Loop_Xpose_Col_Outer_U0_ap_continue;
sc_signal< sc_logic > Loop_Xpose_Col_Outer_U0_ap_idle;
sc_signal< sc_logic > Loop_Xpose_Col_Outer_U0_ap_ready;
sc_signal< sc_lv<6> > Loop_Xpose_Col_Outer_U0_col_outbuf_i_address0;
sc_signal< sc_logic > Loop_Xpose_Col_Outer_U0_col_outbuf_i_ce0;
sc_signal< sc_lv<6> > Loop_Xpose_Col_Outer_U0_buf_2d_out_address0;
sc_signal< sc_logic > Loop_Xpose_Col_Outer_U0_buf_2d_out_ce0;
sc_signal< sc_logic > Loop_Xpose_Col_Outer_U0_buf_2d_out_we0;
sc_signal< sc_lv<16> > Loop_Xpose_Col_Outer_U0_buf_2d_out_d0;
sc_signal< sc_logic > ap_channel_done_buf_2d_out;
sc_signal< sc_logic > Loop_Xpose_Col_Outer_U0_buf_2d_out_full_n;
sc_signal< sc_logic > write_data_U0_ap_start;
sc_signal< sc_logic > write_data_U0_ap_done;
sc_signal< sc_logic > write_data_U0_ap_continue;
sc_signal< sc_logic > write_data_U0_ap_idle;
sc_signal< sc_logic > write_data_U0_ap_ready;
sc_signal< sc_lv<6> > write_data_U0_buf_r_address0;
sc_signal< sc_logic > write_data_U0_buf_r_ce0;
sc_signal< sc_lv<6> > write_data_U0_output_r_address0;
sc_signal< sc_logic > write_data_U0_output_r_ce0;
sc_signal< sc_logic > write_data_U0_output_r_we0;
sc_signal< sc_lv<16> > write_data_U0_output_r_d0;
sc_signal< sc_logic > ap_sync_continue;
sc_signal< sc_logic > buf_2d_in_0_i_full_n;
sc_signal< sc_logic > buf_2d_in_0_t_empty_n;
sc_signal< sc_logic > buf_2d_in_1_i_full_n;
sc_signal< sc_logic > buf_2d_in_1_t_empty_n;
sc_signal< sc_logic > buf_2d_in_2_i_full_n;
sc_signal< sc_logic > buf_2d_in_2_t_empty_n;
sc_signal< sc_logic > buf_2d_in_3_i_full_n;
sc_signal< sc_logic > buf_2d_in_3_t_empty_n;
sc_signal< sc_logic > buf_2d_in_4_i_full_n;
sc_signal< sc_logic > buf_2d_in_4_t_empty_n;
sc_signal< sc_logic > buf_2d_in_5_i_full_n;
sc_signal< sc_logic > buf_2d_in_5_t_empty_n;
sc_signal< sc_logic > buf_2d_in_6_i_full_n;
sc_signal< sc_logic > buf_2d_in_6_t_empty_n;
sc_signal< sc_logic > buf_2d_in_7_i_full_n;
sc_signal< sc_logic > buf_2d_in_7_t_empty_n;
sc_signal< sc_logic > row_outbuf_i_i_full_n;
sc_signal< sc_logic > row_outbuf_i_t_empty_n;
sc_signal< sc_logic > col_inbuf_0_i_full_n;
sc_signal< sc_logic > col_inbuf_0_t_empty_n;
sc_signal< sc_logic > col_inbuf_1_i_full_n;
sc_signal< sc_logic > col_inbuf_1_t_empty_n;
sc_signal< sc_logic > col_inbuf_2_i_full_n;
sc_signal< sc_logic > col_inbuf_2_t_empty_n;
sc_signal< sc_logic > col_inbuf_3_i_full_n;
sc_signal< sc_logic > col_inbuf_3_t_empty_n;
sc_signal< sc_logic > col_inbuf_4_i_full_n;
sc_signal< sc_logic > col_inbuf_4_t_empty_n;
sc_signal< sc_logic > col_inbuf_5_i_full_n;
sc_signal< sc_logic > col_inbuf_5_t_empty_n;
sc_signal< sc_logic > col_inbuf_6_i_full_n;
sc_signal< sc_logic > col_inbuf_6_t_empty_n;
sc_signal< sc_logic > col_inbuf_7_i_full_n;
sc_signal< sc_logic > col_inbuf_7_t_empty_n;
sc_signal< sc_logic > col_outbuf_i_i_full_n;
sc_signal< sc_logic > col_outbuf_i_t_empty_n;
sc_signal< sc_logic > buf_2d_out_i_full_n;
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sc_signal< sc_logic > buf_2d_out_t_empty_n;
sc_signal< sc_logic > ap_sync_done;
sc_signal< sc_logic > ap_sync_ready;
sc_signal< sc_logic > read_data_U0_start_full_n;
sc_signal< sc_logic > read_data_U0_start_write;
sc_signal< sc_logic > Loop_Row_DCT_Loop_pr_U0_start_full_n;
sc_signal< sc_logic > Loop_Row_DCT_Loop_pr_U0_start_write;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_start_full_n;
sc_signal< sc_logic > Loop_Xpose_Row_Outer_U0_start_write;
sc_signal< sc_logic > Loop_Col_DCT_Loop_pr_U0_start_full_n;
sc_signal< sc_logic > Loop_Col_DCT_Loop_pr_U0_start_write;
sc_signal< sc_logic > Loop_Xpose_Col_Outer_U0_start_full_n;
sc_signal< sc_logic > Loop_Xpose_Col_Outer_U0_start_write;
sc_signal< sc_logic > write_data_U0_start_full_n;
sc_signal< sc_logic > write_data_U0_start_write;
static const sc_logic ap_const_logic_1;
static const sc_lv<6> ap_const_lv6_0;
static const sc_logic ap_const_logic_0;
static const sc_lv<16> ap_const_lv16_0;
static const bool ap_const_boolean_1;
// Thread declarations
void thread_ap_var_for_const2();
void thread_ap_var_for_const0();
void thread_ap_var_for_const1();
void thread_ap_clk_no_reset_();
void thread_Loop_Col_DCT_Loop_pr_U0_ap_continue();
void thread_Loop_Col_DCT_Loop_pr_U0_ap_start();
void thread_Loop_Col_DCT_Loop_pr_U0_col_outbuf_i_full_n();
void thread_Loop_Col_DCT_Loop_pr_U0_start_full_n();
void thread_Loop_Col_DCT_Loop_pr_U0_start_write();
void thread_Loop_Row_DCT_Loop_pr_U0_ap_continue();
void thread_Loop_Row_DCT_Loop_pr_U0_ap_start();
void thread_Loop_Row_DCT_Loop_pr_U0_row_outbuf_i_full_n();
void thread_Loop_Row_DCT_Loop_pr_U0_start_full_n();
void thread_Loop_Row_DCT_Loop_pr_U0_start_write();
void thread_Loop_Xpose_Col_Outer_U0_ap_continue();
void thread_Loop_Xpose_Col_Outer_U0_ap_start();
void thread_Loop_Xpose_Col_Outer_U0_buf_2d_out_full_n();
void thread_Loop_Xpose_Col_Outer_U0_start_full_n();
void thread_Loop_Xpose_Col_Outer_U0_start_write();
void thread_Loop_Xpose_Row_Outer_U0_ap_continue();
void thread_Loop_Xpose_Row_Outer_U0_ap_start();
void thread_Loop_Xpose_Row_Outer_U0_col_inbuf_0_full_n();
void thread_Loop_Xpose_Row_Outer_U0_col_inbuf_1_full_n();
void thread_Loop_Xpose_Row_Outer_U0_col_inbuf_2_full_n();
void thread_Loop_Xpose_Row_Outer_U0_col_inbuf_3_full_n();
void thread_Loop_Xpose_Row_Outer_U0_col_inbuf_4_full_n();
void thread_Loop_Xpose_Row_Outer_U0_col_inbuf_5_full_n();
void thread_Loop_Xpose_Row_Outer_U0_col_inbuf_6_full_n();
void thread_Loop_Xpose_Row_Outer_U0_col_inbuf_7_full_n();
void thread_Loop_Xpose_Row_Outer_U0_start_full_n();
void thread_Loop_Xpose_Row_Outer_U0_start_write();
void thread_ap_channel_done_buf_2d_in_0();
void thread_ap_channel_done_buf_2d_in_1();
void thread_ap_channel_done_buf_2d_in_2();
void thread_ap_channel_done_buf_2d_in_3();
void thread_ap_channel_done_buf_2d_in_4();
void thread_ap_channel_done_buf_2d_in_5();
void thread_ap_channel_done_buf_2d_in_6();
void thread_ap_channel_done_buf_2d_in_7();
void thread_ap_channel_done_buf_2d_out();
void thread_ap_channel_done_col_inbuf_0();
void thread_ap_channel_done_col_inbuf_1();
void thread_ap_channel_done_col_inbuf_2();
void thread_ap_channel_done_col_inbuf_3();
void thread_ap_channel_done_col_inbuf_4();
void thread_ap_channel_done_col_inbuf_5();
void thread_ap_channel_done_col_inbuf_6();
void thread_ap_channel_done_col_inbuf_7();
void thread_ap_channel_done_col_outbuf_i();
void thread_ap_channel_done_row_outbuf_i();
void thread_ap_done();
void thread_ap_idle();
void thread_ap_ready();
void thread_ap_sync_channel_write_buf_2d_in_0();
void thread_ap_sync_channel_write_buf_2d_in_1();
void thread_ap_sync_channel_write_buf_2d_in_2();
void thread_ap_sync_channel_write_buf_2d_in_3();
void thread_ap_sync_channel_write_buf_2d_in_4();
void thread_ap_sync_channel_write_buf_2d_in_5();
void thread_ap_sync_channel_write_buf_2d_in_6();
void thread_ap_sync_channel_write_buf_2d_in_7();
void thread_ap_sync_channel_write_col_inbuf_0();
void thread_ap_sync_channel_write_col_inbuf_1();
void thread_ap_sync_channel_write_col_inbuf_2();
void thread_ap_sync_channel_write_col_inbuf_3();
void thread_ap_sync_channel_write_col_inbuf_4();
void thread_ap_sync_channel_write_col_inbuf_5();
void thread_ap_sync_channel_write_col_inbuf_6();
void thread_ap_sync_channel_write_col_inbuf_7();
void thread_ap_sync_continue();
void thread_ap_sync_done();
void thread_ap_sync_ready();
void thread_input_r_address0();
void thread_input_r_address1();
void thread_input_r_ce0();
void thread_input_r_ce1();
void thread_input_r_d0();
void thread_input_r_d1();
void thread_input_r_we0();
void thread_input_r_we1();
void thread_output_r_address0();
void thread_output_r_address1();
void thread_output_r_ce0();
void thread_output_r_ce1();
void thread_output_r_d0();
void thread_output_r_d1();
void thread_output_r_we0();
void thread_output_r_we1();
void thread_read_data_U0_ap_continue();
void thread_read_data_U0_ap_start();
void thread_read_data_U0_buf_0_full_n();
void thread_read_data_U0_buf_1_full_n();
void thread_read_data_U0_buf_2_full_n();
void thread_read_data_U0_buf_3_full_n();
void thread_read_data_U0_buf_4_full_n();
void thread_read_data_U0_buf_5_full_n();
void thread_read_data_U0_buf_6_full_n();
void thread_read_data_U0_buf_7_full_n();
void thread_read_data_U0_start_full_n();
void thread_read_data_U0_start_write();
void thread_write_data_U0_ap_continue();
void thread_write_data_U0_ap_start();
void thread_write_data_U0_start_full_n();
void thread_write_data_U0_start_write();
void thread_hdltv_gen();
};
}
using namespace ap_rtl;
#endif
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// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
#ifndef __ZYNQ_UTLRA_PS_E_TLM_H__
#define __ZYNQ_ULTRA_PS_E_TLM_H__
#include "systemc.h"
#include "xtlm.h"
#include "xtlm_adaptors/xaximm_xtlm2tlm.h"
#include "xtlm_adaptors/xaximm_tlm2xtlm.h"
#include "tlm_utils/simple_initiator_socket.h"
#include "tlm_utils/simple_target_socket.h"
#include <vector>
#include "genattr.h"
#include "xilinx_zynqmp_vitis.h"
#include "b_transport_converter.h"
#include "utils/xtlm_aximm_fifo.h"
/***************************************************************************************
*
* A Simple Converter which converts Remote-port's simplae_intiator_sockets<32>->b_transport()
* calls to xTLM sockets bn_transport_x() calls..
*
* This is Only specific to remote-port so not creating seperate header for it.
*
***************************************************************************************/
template <int IN_WIDTH, int OUT_WIDTH>
class rptlm2xtlm_converter : public sc_module{
public:
tlm::tlm_target_socket<IN_WIDTH> target_socket;
xtlm::xtlm_aximm_initiator_socket wr_socket;
xtlm::xtlm_aximm_initiator_socket rd_socket;
rptlm2xtlm_converter<IN_WIDTH, OUT_WIDTH>(sc_module_name name);//:sc_module(name)
void registerUserExtensionHandlerCallback(
void (*callback)(xtlm::aximm_payload*,
const tlm::tlm_generic_payload*));
private:
b_transport_converter<IN_WIDTH, OUT_WIDTH> m_btrans_conv;
xtlm::xaximm_tlm2xtlm_t<OUT_WIDTH> xtlm_bridge;
};
/***************************************************************************************
* Global method, get registered with tlm2xtlm bridge
* This function is called when tlm2xtlm bridge convert tlm payload to xtlm payload.
*
* caller: tlm2xtlm bridge
* purpose: To get master id and other parameters out of genattr_extension
* and use master id to AxUSER PIN of xtlm payload.
*
*
***************************************************************************************/
extern void get_extensions_from_tlm(xtlm::aximm_payload* xtlm_pay, const tlm::tlm_generic_payload* gp);
/***************************************************************************************
* Global method, get registered with xtlm2tlm bridge
* This function is called when xtlm2tlm bridge convert xtlm payload to tlm payload.
*
* caller: xtlm2tlm bridge
* purpose: To create and add master id and other parameters to genattr_extension.
* Master id red from AxID PIN of xtlm payload.
*
*
***************************************************************************************/
extern void add_extensions_to_tlm(const xtlm::aximm_payload* xtlm_pay, tlm::tlm_generic_payload* gp);
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// //
// File: zynq_ultra_ps_e_tlm.h //
// //
// Description: zynq_ultra_ps_e_tlm class is a sc_module, act as intermediate layer between //
// xilinx_zynqmp qemu wrapper and Vivado generated systemc simulation ip wrapper. //
// it's basically created for supporting tlm based xilinx_zynqmp from xtlm based vivado //
// generated systemc wrapper. this wrapper is live only when SELECTED_SIM_MODEL is set //
// to tlm. it's also act as bridge between vivado wrapper and xilinx_zynqmp wrapper. //
// it fill the the gap between input/output ports of vivado generated wrapper to //
// xilinx_zynqmp wrapper signals. This wrapper is auto generated by ttcl scripts //
// based on IP configuration in vivado. //
// //
// //
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
class zynq_ultra_ps_e_tlm : public sc_core::sc_module {
public:
// Non-AXI ports are declared here
sc_core::sc_in<bool> maxihpm0_lpd_aclk;
sc_core::sc_in<bool> saxihpc0_fpd_aclk;
sc_core::sc_out<sc_dt::sc_bv<94> > emio_enet0_enet_tsu_timer_cnt;
sc_core::sc_in<sc_dt::sc_bv<1> > emio_gpio_i;
sc_core::sc_out<sc_dt::sc_bv<1> > emio_gpio_o;
sc_core::sc_out<sc_dt::sc_bv<1> > emio_gpio_t;
sc_core::sc_in<bool> dp_aux_data_in;
sc_core::sc_out<bool> dp_aux_data_out;
sc_core::sc_out<bool> dp_aux_data_oe_n;
sc_core::sc_in<bool> dp_hot_plug_detect;
sc_core::sc_in<sc_dt::sc_bv<1> > pl_ps_irq0;
sc_core::sc_out<bool> pl_resetn0;
sc_core::sc_out<bool> pl_clk0;
// Xtlm aximm slave sockets are delcared here. these XTLM sockets will hierachically bound with
// slave sockets defined in vivado generated wrapper.
xtlm::xtlm_aximm_target_socket* S_AXI_HPC0_FPD_wr_socket;
xtlm::xtlm_aximm_target_socket* S_AXI_HPC0_FPD_rd_socket;
// Xtlm aximm master socket/s is/are delcared here. these XTLM sockets will hierachically bound with
// master sockets defined in vivado generated wrapper.
xtlm::xtlm_aximm_initiator_socket* M_AXI_HPM0_LPD_wr_socket;
xtlm::xtlm_aximm_initiator_socket* M_AXI_HPM0_LPD_rd_socket;
//constructor having three paramters
// 1. module name in sc_module_name objec,
// 2. reference to map object of name and integer value pairs
// 3. reference to map object of name and string value pairs
// All the model parameters (integer and string) which are configuration parameters
// of ZynqUltraScale+ IP propogated from Vivado
zynq_ultra_ps_e_tlm (sc_core::sc_module_name name,
xsc::common_cpp::properties&);
~zynq_ultra_ps_e_tlm ();
SC_HAS_PROCESS( zynq_ultra_ps_e_tlm );
private:
//zynqmp tlm wrapper provided by Edgar
//module with interfaces of standard tlm
//and input/output ports at signal level
zynqmp_tlm_vitis::xilinx_zynqmp* m_zynqmp_tlm_model;
// Xtlm2tlm_t Bridges
// Converts Xtlm transactions to tlm transactions
// Bridge's Xtlm wr/rd target sockets binds with
// xtlm initiator sockets of zynq_ultra_ps_e_tlm and tlm simple initiator
// socket with xilinx_zynqmp's target socket
xtlm::xaximm_xtlm2tlm_t<128,32> S_AXI_HPC0_FPD_xtlm_brdg;
xtlm::xtlm_aximm_fifo *S_AXI_HPC0_FPD_buff;
// This Bridges converts b_transport to nb_transports and also
// Converts tlm transactions to xtlm transactions.
// Bridge's tlm simple target socket binds with
// simple initiator socket of xilinx_zynqmp and xtlm
// socket with xilinx_zynqmp's simple target socket
rptlm2xtlm_converter<32, 32 > m_rp_bridge_M_AXI_HPM0_LPD;
// sc_clocks for generating pl clocks
// output pins pl_clk0..3 are drived by these clocks
sc_core::sc_clock pl_clk0_clk;
//Method which is sentive to pl_clk0_clk sc_clock object
//pl_clk0 pin written based on pl_clk0_clk clock value
void trigger_pl_clk0_pin();
void pl_ps_irq0_method();
//pl_resetn0 output reset pin get toggle when emio bank 2's 31th signal gets toggled
//EMIO[2] bank 31th(GPIO[95] signal)acts as reset signal to the PL(refer Zynq UltraScale+ TRM, page no:761)
void pl_resetn0_trigger();
sc_signal<bool> qemu_rst;
void start_of_simulation();
};
#endif
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// **************************************************************************************
// User-defined memory manager, which maintains a pool of transactions
// From TLM Duolos tutorials
// **************************************************************************************
#ifndef TRANSACTION_MEMORY_MANAGER_CPP
#define TRANSACTION_MEMORY_MANAGER_CPP
#include <systemc.h>
using namespace sc_core;
using namespace sc_dt;
using namespace std;
#include <tlm.h>
#include <tlm_utils/simple_initiator_socket.h>
#include <tlm_utils/simple_target_socket.h>
#include <tlm_utils/peq_with_cb_and_phase.h>
class mm: public tlm::tlm_mm_interface
{
typedef tlm::tlm_generic_payload gp_t;
public:
mm() : free_list(0), empties(0)
#ifdef DEBUG
, count(0)
#endif
{}
gp_t* allocate()
{
#ifdef DEBUG
cout << "----------------------------- Called allocate(), #trans = " << ++count << endl;
#endif
gp_t* ptr;
if (free_list)
{
ptr = free_list->trans;
empties = free_list;
free_list = free_list->next;
}
else
{
ptr = new gp_t(this);
}
return ptr;
}
void free(gp_t* trans)
{
#ifdef DEBUG
cout << "----------------------------- Called free(), #trans = " << --count << endl;
#endif
if (!empties)
{
empties = new access;
empties->next = free_list;
empties->prev = 0;
if (free_list)
free_list->prev = empties;
}
free_list = empties;
free_list->trans = trans;
empties = free_list->prev;
}
private:
struct access
{
gp_t* trans;
access* next;
access* prev;
};
access* free_list;
access* empties;
#ifdef DEBUG
int count;
#endif
};
#endif
|
/******************************************************************************
* *
* Copyright (C) 2022 MachineWare GmbH *
* All Rights Reserved *
* *
* This is work is licensed under the terms described in the LICENSE file *
* found in the root directory of this source tree. *
* *
******************************************************************************/
#ifndef VCML_VIRTIO_MMIO_H
#define VCML_VIRTIO_MMIO_H
#include "vcml/core/types.h"
#include "vcml/core/range.h"
#include "vcml/core/systemc.h"
#include "vcml/core/peripheral.h"
#include "vcml/core/model.h"
#include "vcml/protocols/tlm.h"
#include "vcml/protocols/gpio.h"
#include "vcml/protocols/virtio.h"
namespace vcml {
namespace virtio {
class mmio : public peripheral, public virtio_controller
{
private:
u64 m_drv_features;
u64 m_dev_features;
virtio_device_desc m_device;
std::unordered_map<u32, virtqueue*> m_queues;
void enable_virtqueue(u32 vqid);
void disable_virtqueue(u32 vqid);
void cleanup_virtqueues();
virtual void invalidate_dmi(u64 start, u64 end) override;
virtual bool get(u32 vqid, vq_message& msg) override;
virtual bool put(u32 vqid, vq_message& msg) override;
virtual bool notify() override;
virtual tlm_response_status read(const range& addr, void* data,
const tlm_sbi& info) override;
virtual tlm_response_status write(const range& addr, const void* data,
const tlm_sbi& info) override;
u8* lookup_dmi_ptr(u64 addr, vcml_access acs);
u32 read_device_id();
u32 read_vendor_id();
void write_device_features_sel(u32 val);
void write_driver_features(u32 val);
void write_queue_sel(u32 val);
void write_queue_ready(u32 val);
void write_queue_notify(u32 val);
void write_interrrupt_ack(u32 val);
void write_status(u32 val);
// disabled
mmio() = delete;
mmio(const mmio&) = delete;
public:
property<bool> use_packed_queues;
property<bool> use_strong_barriers;
reg<u32> magic;
reg<u32> version;
reg<u32> device_id;
reg<u32> vendor_id;
reg<u32> device_features;
reg<u32> device_features_sel;
reg<u32> driver_features;
reg<u32> driver_features_sel;
reg<u32> queue_sel;
reg<u32> queue_num_max;
reg<u32> queue_num;
reg<u32> queue_ready;
reg<u32> queue_notify;
reg<u32> interrupt_status;
reg<u32> interrupt_ack;
reg<u32> status;
reg<u32> queue_desc_lo;
reg<u32> queue_desc_hi;
reg<u32> queue_driver_lo;
reg<u32> queue_driver_hi;
reg<u32> queue_device_lo;
reg<u32> queue_device_hi;
reg<u32> config_gen;
tlm_target_socket in;
tlm_initiator_socket out;
gpio_initiator_socket irq;
virtio_initiator_socket virtio_out;
mmio(const sc_module_name& nm);
virtual ~mmio();
VCML_KIND(virtio::mmio);
virtual void reset() override;
bool has_feature(u64 feature) const;
bool device_ready() const;
};
inline bool mmio::has_feature(u64 feature) const {
return (m_drv_features & m_dev_features & feature) == feature;
}
inline bool mmio::device_ready() const {
return virtio_device_ready(status);
}
} // namespace virtio
} // namespace vcml
#endif
|
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION &
* AFFILIATES. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
// This is a stub needed for the generated interconnect, so that downstream flow
// and simulation knows where to look for it.
#ifndef GROUT_0_H
#define GROUT_0_H
#include <systemc.h>
#include <nvhls_connections.h>
#include <nvhls_packet.h>
#include <interconnect/Interconnect.hpp>
#include "interconnect_config.hpp"
#if defined(INTERCONNECT_GEN)
#include ic_header(INTERCONNECT_GEN)
#endif // if defined(INTERCONNECT_GEN)
#endif
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.1
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ===========================================================
#ifndef _memcachedPipeline_merger_HH_
#define _memcachedPipeline_merger_HH_
#include "systemc.h"
#include "AESL_pkg.h"
namespace ap_rtl {
struct memcachedPipeline_merger : public sc_module {
// Port declarations 16
sc_in_clk ap_clk;
sc_in< sc_logic > ap_rst;
sc_in< sc_logic > ap_start;
sc_out< sc_logic > ap_done;
sc_in< sc_logic > ap_continue;
sc_out< sc_logic > ap_idle;
sc_out< sc_logic > ap_ready;
sc_in< sc_lv<256> > valueStoreDram2merger_V_dout;
sc_in< sc_logic > valueStoreDram2merger_V_empty_n;
sc_out< sc_logic > valueStoreDram2merger_V_read;
sc_in< sc_lv<256> > valueStoreFlash2merger_V_dout;
sc_in< sc_logic > valueStoreFlash2merger_V_empty_n;
sc_out< sc_logic > valueStoreFlash2merger_V_read;
sc_out< sc_lv<256> > merger2responseFormatter_V_din;
sc_in< sc_logic > merger2responseFormatter_V_full_n;
sc_out< sc_logic > merger2responseFormatter_V_write;
// Module declarations
memcachedPipeline_merger(sc_module_name name);
SC_HAS_PROCESS(memcachedPipeline_merger);
~memcachedPipeline_merger();
sc_trace_file* mVcdFile;
sc_signal< sc_logic > ap_done_reg;
sc_signal< sc_lv<1> > ap_CS_fsm;
sc_signal< sc_logic > ap_sig_cseq_ST_pp0_stg0_fsm_0;
sc_signal< bool > ap_sig_bdd_20;
sc_signal< sc_logic > ap_reg_ppiten_pp0_it0;
sc_signal< sc_logic > ap_reg_ppiten_pp0_it1;
sc_signal< sc_lv<1> > grp_nbreadreq_fu_120_p3;
sc_signal< sc_lv<1> > grp_nbreadreq_fu_128_p3;
sc_signal< bool > ap_sig_bdd_76;
sc_signal< sc_lv<1> > mergerState_load_reg_214;
sc_signal< sc_lv<1> > tmp_reg_222;
sc_signal< sc_lv<1> > tmp_1_reg_226;
sc_signal< sc_lv<1> > dramOrFlash_V_1_load_reg_218;
sc_signal< sc_lv<1> > tmp_3_reg_230;
sc_signal< sc_lv<1> > tmp_2_reg_238;
sc_signal< bool > ap_sig_bdd_115;
sc_signal< sc_lv<1> > mergerState;
sc_signal< sc_lv<1> > dramOrFlash_V_1;
sc_signal< sc_lv<256> > reg_168;
sc_signal< sc_lv<256> > reg_173;
sc_signal< sc_lv<1> > tmp_EOP_V_1_fu_198_p3;
sc_signal< sc_lv<1> > tmp_EOP_V_fu_206_p3;
sc_signal< sc_lv<1> > ap_NS_fsm;
sc_signal< sc_logic > ap_sig_pprstidle_pp0;
sc_signal< bool > ap_sig_bdd_205;
sc_signal< bool > ap_sig_bdd_204;
static const sc_logic ap_const_logic_1;
static const sc_logic ap_const_logic_0;
static const sc_lv<1> ap_ST_pp0_stg0_fsm_0;
static const sc_lv<32> ap_const_lv32_0;
static const sc_lv<1> ap_const_lv1_1;
static const sc_lv<1> ap_const_lv1_0;
static const sc_lv<32> ap_const_lv32_7F;
static const sc_lv<256> ap_const_lv256_lc_1;
// Thread declarations
void thread_ap_clk_pos_reset_();
void thread_ap_done();
void thread_ap_idle();
void thread_ap_ready();
void thread_ap_reg_ppiten_pp0_it0();
void thread_ap_sig_bdd_115();
void thread_ap_sig_bdd_20();
void thread_ap_sig_bdd_204();
void thread_ap_sig_bdd_205();
void thread_ap_sig_bdd_76();
void thread_ap_sig_cseq_ST_pp0_stg0_fsm_0();
void thread_ap_sig_pprstidle_pp0();
void thread_grp_nbreadreq_fu_120_p3();
void thread_grp_nbreadreq_fu_128_p3();
void thread_merger2responseFormatter_V_din();
void thread_merger2responseFormatter_V_write();
void thread_tmp_EOP_V_1_fu_198_p3();
void thread_tmp_EOP_V_fu_206_p3();
void thread_valueStoreDram2merger_V_read();
void thread_valueStoreFlash2merger_V_read();
void thread_ap_NS_fsm();
};
}
using namespace ap_rtl;
#endif
|
/*
* fetch.h
*
* Created on: 4 de mai de 2017
* Author: drcfts
*/
#ifndef FETCH_H_
#define FETCH_H_
#include <systemc.h>
#include "shared.h"
#include "mem_if.h"
#include "breg_if.h"
#define RASTREIA_PC
//Criar uma classe memoria que implementa interface com metodos de leitura
//e escrita para ser acessado (por ponteiro) pelos metodos fetch
//e execute
SC_MODULE(fetch){
sc_port <mem_if> p_mem;
sc_port <breg_if> p_breg;
sc_fifo_in < contexto*> execute_fetch;
sc_fifo_out < contexto* > fetch_decode;
void fetch_method(){
while(true){
recebimento = execute_fetch.read();
escrita = recebimento;
PC = (p_breg->read(31));
#ifdef RASTREIA_PC
cout << "PC = " << PC << endl;
#endif
escrita->ri = p_mem->read(PC);
//Registrador 31 = PC
p_breg->write(31, PC +1);
//Instrucao que nao faz sentido lw $0, $0
//Interrompe execucao
if(escrita->ri == 0){
p_breg->dump_breg();
sc_stop();
exit(0);
} //if
fetch_decode.write(escrita);
} // while
}
SC_CTOR(fetch){
recebimento = new contexto();
escrita = new contexto();
SC_THREAD(fetch_method);
}
private:
contexto *escrita;
contexto *recebimento;
uint32_t PC;
};
#endif /* FETCH_H_ */
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
// Version: 2019.2
// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _pqcrystals_dilithium_1_1_HH_
#define _pqcrystals_dilithium_1_1_HH_
#include "systemc.h"
#include "AESL_pkg.h"
#include "pqcrystals_dilithium_9.h"
#include "pqcrystals_dilithium_13.h"
#include "pqcrystals_dilithium_12.h"
#include "pqcrystals_dilithium_15.h"
#include "shake256.h"
#include "KeccakF1600_StatePer_1.h"
#include "pqcrystals_dilithium_2.h"
#include "pqcrystals_dilithium_6.h"
#include "pqcrystals_dilithium_21.h"
#include "pqcrystals_dilithium_18.h"
#include "pqcrystals_dilithium_19.h"
#include "pqcrystals_dilithium_17.h"
#include "pqcrystals_dilithium_4.h"
#include "load64_3.h"
#include "pqcrystals_dilithium_5.h"
#include "pqcrystals_dilithium_3.h"
#include "pqcrystals_dilithium_7.h"
#include "pqcrystals_dilithium_8.h"
#include "pqcrystals_dilithDeQ.h"
#include "pqcrystals_dilithEe0.h"
#include "pqcrystals_dilithlbW.h"
#include "pqcrystals_dilithqcK.h"
#include "pqcrystals_dilithrcU.h"
#include "pqcrystals_dilithsc4.h"
#include "pqcrystals_dilithtde.h"
#include "pqcrystals_dilithudo.h"
#include "pqcrystals_dilithvdy.h"
#include "pqcrystals_dilithBew.h"
#include "shake256_state_0_s.h"
namespace ap_rtl {
struct pqcrystals_dilithium_1_1 : public sc_module {
// Port declarations 23
sc_in_clk ap_clk;
sc_in< sc_logic > ap_rst;
sc_in< sc_logic > ap_start;
sc_out< sc_logic > ap_done;
sc_out< sc_logic > ap_idle;
sc_out< sc_logic > ap_ready;
sc_out< sc_lv<13> > sig_address0;
sc_out< sc_logic > sig_ce0;
sc_out< sc_logic > sig_we0;
sc_out< sc_lv<8> > sig_d0;
sc_in< sc_lv<8> > sig_q0;
sc_out< sc_lv<13> > sig_address1;
sc_out< sc_logic > sig_ce1;
sc_out< sc_logic > sig_we1;
sc_out< sc_lv<8> > sig_d1;
sc_in< sc_lv<8> > sig_q1;
sc_in< sc_lv<64> > mlen;
sc_out< sc_lv<12> > sk_address0;
sc_out< sc_logic > sk_ce0;
sc_in< sc_lv<8> > sk_q0;
sc_out< sc_lv<12> > sk_address1;
sc_out< sc_logic > sk_ce1;
sc_in< sc_lv<8> > sk_q1;
sc_signal< sc_lv<8> > ap_var_for_const0;
// Module declarations
pqcrystals_dilithium_1_1(sc_module_name name);
SC_HAS_PROCESS(pqcrystals_dilithium_1_1);
~pqcrystals_dilithium_1_1();
sc_trace_file* mVcdFile;
pqcrystals_dilithqcK* t_6_U;
pqcrystals_dilithrcU* seedbuf_U;
pqcrystals_dilithsc4* mat_vec_coeffs_U;
pqcrystals_dilithtde* s1_vec_coeffs_U;
pqcrystals_dilithudo* y_vec_coeffs_U;
pqcrystals_dilithvdy* z_vec_coeffs_U;
pqcrystals_dilithtde* t0_vec_coeffs_U;
pqcrystals_dilithtde* s2_vec_coeffs_U;
pqcrystals_dilithvdy* w1_vec_coeffs_U;
pqcrystals_dilithvdy* w0_vec_coeffs_U;
pqcrystals_dilithvdy* h_vec_coeffs_U;
pqcrystals_dilithBew* cp_coeffs_U;
shake256_state_0_s* state_s_U;
pqcrystals_dilithium_9* grp_pqcrystals_dilithium_9_fu_1750;
pqcrystals_dilithium_13* grp_pqcrystals_dilithium_13_fu_1757;
pqcrystals_dilithium_12* grp_pqcrystals_dilithium_12_fu_1770;
pqcrystals_dilithium_15* grp_pqcrystals_dilithium_15_fu_1781;
shake256* grp_shake256_fu_1790;
KeccakF1600_StatePer_1* grp_KeccakF1600_StatePer_1_fu_1797;
pqcrystals_dilithium_2* grp_pqcrystals_dilithium_2_fu_1804;
pqcrystals_dilithium_6* grp_pqcrystals_dilithium_6_fu_1818;
pqcrystals_dilithium_21* grp_pqcrystals_dilithium_21_fu_1825;
pqcrystals_dilithium_18* grp_pqcrystals_dilithium_18_fu_1834;
pqcrystals_dilithium_19* grp_pqcrystals_dilithium_19_fu_1841;
pqcrystals_dilithium_17* grp_pqcrystals_dilithium_17_fu_1853;
pqcrystals_dilithium_4* grp_pqcrystals_dilithium_4_fu_1861;
load64_3* grp_load64_3_fu_1868;
pqcrystals_dilithium_5* grp_pqcrystals_dilithium_5_fu_1875;
pqcrystals_dilithium_3* grp_pqcrystals_dilithium_3_fu_1882;
pqcrystals_dilithium_7* grp_pqcrystals_dilithium_7_fu_1887;
pqcrystals_dilithium_8* grp_pqcrystals_dilithium_8_fu_1895;
pqcrystals_dilithDeQ<1,1,15,25,25,32>* pqcrystals_dilithDeQ_U89;
pqcrystals_dilithEe0<1,1,19,8,32,32>* pqcrystals_dilithEe0_U90;
pqcrystals_dilithlbW<1,1,9,24,32,32>* pqcrystals_dilithlbW_U91;
sc_signal< sc_lv<134> > ap_CS_fsm;
sc_signal< sc_logic > ap_CS_fsm_state1;
sc_signal< sc_lv<11> > indvar_flatten_reg_1516;
sc_signal< sc_lv<3> > i_0_i35_reg_1527;
sc_signal< sc_lv<9> > i_0_i_i36_reg_1538;
sc_signal< sc_lv<11> > indvar_flatten7_reg_1561;
sc_signal< sc_lv<3> > i_0_i43_reg_1572;
sc_signal< sc_lv<9> > i_0_i_i44_reg_1583;
sc_signal< sc_lv<11> > indvar_flatten15_reg_1594;
sc_signal< sc_lv<3> > i_0_i52_reg_1605;
sc_signal< sc_lv<9> > i_0_i_i54_reg_1616;
sc_signal< sc_lv<11> > indvar_flatten23_reg_1671;
sc_signal< sc_lv<3> > i_0_i67_reg_1682;
sc_signal< sc_lv<9> > i_0_i_i68_reg_1693;
sc_signal< sc_lv<8> > seedbuf_q0;
sc_signal< sc_lv<8> > reg_1912;
sc_signal< sc_logic > ap_CS_fsm_state5;
sc_signal< sc_logic > ap_CS_fsm_state78;
sc_signal< sc_lv<8> > seedbuf_q1;
sc_signal< sc_lv<8> > reg_1916;
sc_signal< sc_lv<8> > reg_1920;
sc_signal< sc_logic > ap_CS_fsm_state6;
sc_signal< sc_logic > ap_CS_fsm_state79;
sc_signal< sc_lv<8> > reg_1924;
sc_signal< sc_lv<8> > reg_1928;
sc_signal< sc_logic > ap_CS_fsm_state7;
sc_signal< sc_logic > ap_CS_fsm_state80;
sc_signal< sc_lv<8> > reg_1932;
sc_signal< sc_lv<64> > grp_fu_1907_p2;
sc_signal< sc_lv<64> > reg_1936;
sc_signal< sc_logic > ap_CS_fsm_state13;
sc_signal< sc_lv<1> > icmp_ln408_fu_2189_p2;
sc_signal< sc_logic > ap_CS_fsm_state2;
sc_signal< sc_logic > grp_pqcrystals_dilithium_2_fu_1804_ap_ready;
sc_signal< sc_logic > grp_pqcrystals_dilithium_2_fu_1804_ap_done;
sc_signal< sc_lv<5> > i_fu_1946_p2;
sc_signal< sc_logic > ap_CS_fsm_state3;
sc_signal< sc_lv<3> > add_ln416_fu_1968_p2;
sc_signal< sc_lv<3> > add_ln416_reg_4346;
sc_signal< sc_logic > ap_CS_fsm_state4;
sc_signal< sc_lv<7> > zext_ln417_fu_1982_p1;
sc_signal< sc_lv<7> > zext_ln417_reg_4351;
sc_signal< sc_lv<1> > icmp_ln416_fu_1962_p2;
sc_signal< sc_lv<5> > state_s_addr_14_reg_4371;
sc_signal< sc_lv<3> > add_ln387_fu_2095_p2;
sc_signal< sc_logic > ap_CS_fsm_state9;
sc_signal< sc_lv<1> > icmp_ln399_fu_2112_p2;
sc_signal< sc_lv<1> > icmp_ln399_reg_4414;
sc_signal< sc_lv<1> > icmp_ln387_fu_2106_p2;
sc_signal< sc_lv<4> > i_24_fu_2127_p2;
sc_signal< sc_lv<4> > i_24_reg_4421;
sc_signal< sc_logic > ap_CS_fsm_state10;
sc_signal< sc_lv<64> > zext_ln401_1_fu_2151_p1;
sc_signal< sc_lv<64> > zext_ln401_1_reg_4426;
sc_signal< sc_lv<1> > icmp_ln400_fu_2121_p2;
sc_signal< sc_lv<5> > state_s_addr_15_reg_4431;
sc_signal< sc_lv<14> > zext_ln408_fu_2177_p1;
sc_signal< sc_lv<14> > zext_ln408_reg_4436;
sc_signal< sc_logic > ap_CS_fsm_state12;
sc_signal< sc_logic > grp_KeccakF1600_StatePer_1_fu_1797_ap_ready;
sc_signal< sc_logic > grp_KeccakF1600_StatePer_1_fu_1797_ap_done;
sc_signal< bool > ap_block_state12_on_subcall_done;
sc_signal< sc_lv<64> > zext_ln408_1_fu_2181_p1;
sc_signal< sc_lv<64> > zext_ln408_1_reg_4441;
sc_signal< sc_lv<9> > zext_ln408_2_fu_2185_p1;
sc_signal< sc_lv<9> > zext_ln408_2_reg_4446;
sc_signal< sc_lv<14> > trunc_ln408_fu_2195_p1;
sc_signal< sc_lv<14> > trunc_ln408_reg_4454;
sc_signal< sc_lv<5> > zext_ln417_4_fu_2213_p1;
sc_signal< sc_lv<5> > zext_ln417_4_reg_4459;
sc_signal< sc_lv<5> > tmp_537_reg_4464;
sc_signal< sc_lv<5> > i_25_fu_2233_p2;
sc_signal< sc_lv<5> > i_25_reg_4473;
sc_signal< sc_logic > ap_CS_fsm_state14;
sc_signal< sc_lv<64> > add_ln410_2_fu_2261_p2;
sc_signal< sc_lv<64> > add_ln410_2_reg_4478;
sc_signal< sc_lv<1> > icmp_ln409_fu_2227_p2;
sc_signal< sc_lv<64> > add_ln411_fu_2267_p2;
sc_signal< sc_lv<64> > add_ln411_reg_4483;
sc_signal< sc_lv<64> > add_ln414_1_fu_2273_p2;
sc_signal< sc_lv<64> > add_ln414_1_reg_4488;
sc_signal< sc_lv<5> > state_s_addr_17_reg_4493;
sc_signal< sc_logic > ap_CS_fsm_state15;
sc_signal< sc_lv<5> > add_ln416_1_fu_2289_p2;
sc_signal< sc_lv<5> > add_ln416_1_reg_4501;
sc_signal< sc_logic > ap_CS_fsm_state18;
sc_signal< sc_lv<64> > add_ln417_3_fu_2321_p2;
sc_signal< sc_lv<64> > add_ln417_3_reg_4506;
sc_signal< sc_lv<1> > icmp_ln416_1_fu_2284_p2;
sc_signal< sc_lv<5> > add_ln417_4_fu_2327_p2;
sc_signal< sc_lv<5> > add_ln417_4_reg_4511;
sc_signal< sc_lv<14> > zext_ln419_fu_2347_p1;
sc_signal< sc_lv<14> > zext_ln419_reg_4516;
sc_signal< sc_lv<64> > sub_ln419_fu_2351_p2;
sc_signal< sc_lv<64> > sub_ln419_reg_4521;
sc_signal< sc_lv<33> > trunc_ln419_fu_2357_p1;
sc_signal< sc_lv<33> > trunc_ln419_reg_4526;
sc_signal< sc_lv<9> > add_ln420_fu_2361_p2;
sc_signal< sc_lv<9> > add_ln420_reg_4531;
sc_signal< sc_lv<10> > zext_ln420_fu_2366_p1;
sc_signal< sc_lv<10> > zext_ln420_reg_4536;
sc_signal< sc_lv<1> > icmp_ln422_fu_2370_p2;
sc_signal< sc_lv<1> > icmp_ln422_reg_4542;
sc_signal< sc_lv<5> > state_s_addr_16_reg_4546;
sc_signal< sc_logic > ap_CS_fsm_state19;
sc_signal< sc_lv<4> > i_26_fu_2386_p2;
sc_signal< sc_logic > ap_CS_fsm_state21;
sc_signal< sc_lv<14> > add_ln426_fu_2397_p2;
sc_signal< sc_lv<14> > add_ln426_reg_4559;
sc_signal< sc_lv<1> > icmp_ln423_fu_2380_p2;
sc_signal< sc_lv<64> > zext_ln425_fu_2401_p1;
sc_signal< sc_lv<64> > zext_ln425_reg_4564;
sc_signal< sc_logic > ap_CS_fsm_state22;
sc_signal< sc_lv<32> > i_27_fu_2418_p2;
sc_signal< sc_lv<32> > i_27_reg_4572;
sc_signal< sc_lv<1> > icmp_ln425_fu_2413_p2;
sc_signal< sc_lv<5> > state_s_addr_18_reg_4592;
sc_signal< sc_lv<10> > trunc_ln428_fu_2459_p1;
sc_signal< sc_lv<10> > trunc_ln428_reg_4597;
sc_signal< sc_lv<8> > t_6_q0;
sc_signal< sc_lv<8> > t_6_load_reg_4602;
sc_signal< sc_logic > ap_CS_fsm_state24;
sc_signal< sc_lv<8> > t_6_q1;
sc_signal< sc_lv<8> > t_6_load_1_reg_4607;
sc_signal< sc_lv<8> > t_6_load_2_reg_4622;
sc_signal< sc_logic > ap_CS_fsm_state25;
sc_signal< sc_lv<8> > t_6_load_3_reg_4627;
sc_signal< sc_lv<8> > t_6_load_4_reg_4642;
sc_signal< sc_logic > ap_CS_fsm_state26;
sc_signal< sc_lv<8> > t_6_load_5_reg_4647;
sc_signal< sc_lv<10> > add_ln428_fu_2483_p2;
sc_signal< sc_logic > ap_CS_fsm_state27;
sc_signal< sc_lv<5> > state_s_addr_19_reg_4667;
sc_signal< sc_logic > ap_CS_fsm_state28;
sc_signal< sc_lv<5> > state_s_addr_20_reg_4672;
sc_signal< sc_logic > ap_CS_fsm_state30;
sc_signal< sc_lv<3> > add_ln540_fu_2553_p2;
sc_signal< sc_lv<3> > add_ln540_reg_4681;
sc_signal< sc_logic > ap_CS_fsm_state34;
sc_signal< sc_lv<1> > icmp_ln540_fu_2547_p2;
sc_signal< sc_lv<6> > shl_ln17_fu_2564_p3;
sc_signal< sc_lv<6> > shl_ln17_reg_4691;
sc_signal< sc_logic > ap_CS_fsm_state35;
sc_signal< sc_lv<8> > trunc_ln12_reg_4701;
sc_signal< sc_lv<8> > trunc_ln13_reg_4706;
sc_signal< sc_lv<8> > trunc_ln14_reg_4711;
sc_signal< sc_lv<8> > trunc_ln15_reg_4716;
sc_signal< sc_lv<8> > trunc_ln16_reg_4721;
sc_signal< sc_lv<8> > trunc_ln17_reg_4726;
sc_signal< sc_lv<3> > i_28_fu_2805_p2;
sc_signal< sc_lv<3> > i_28_reg_4734;
sc_signal< sc_logic > ap_CS_fsm_state40;
sc_signal< sc_lv<3> > j_fu_2817_p2;
sc_signal< sc_lv<3> > j_reg_4742;
sc_signal< sc_logic > ap_CS_fsm_state41;
sc_signal< sc_lv<10> > add_ln_fu_2827_p4;
sc_signal< sc_lv<10> > add_ln_reg_4747;
sc_signal< sc_lv<1> > icmp_ln21_fu_2811_p2;
sc_signal< sc_lv<3> > i_29_fu_2844_p2;
sc_signal< sc_lv<3> > i_29_reg_4755;
sc_signal< sc_logic > ap_CS_fsm_state43;
sc_signal< sc_lv<3> > i_30_fu_2856_p2;
sc_signal< sc_lv<3> > i_30_reg_4763;
sc_signal< sc_logic > ap_CS_fsm_state45;
sc_signal< sc_lv<3> > i_31_fu_2868_p2;
sc_signal< sc_lv<3> > i_31_reg_4771;
sc_signal< sc_logic > ap_CS_fsm_state47;
sc_signal< sc_lv<1> > icmp_ln282_1_fu_2862_p2;
sc_signal< sc_lv<16> > nonce_fu_2874_p2;
sc_signal< sc_lv<16> > nonce_reg_4782;
sc_signal< sc_logic > ap_CS_fsm_state49;
sc_signal< sc_lv<16> > shl_ln47_fu_2880_p2;
sc_signal< sc_lv<16> > shl_ln47_reg_4787;
sc_signal< sc_lv<3> > i_32_fu_2892_p2;
sc_signal< sc_lv<3> > i_32_reg_4795;
sc_signal< sc_logic > ap_CS_fsm_state50;
sc_signal< sc_lv<16> > add_ln47_fu_2902_p2;
sc_signal< sc_lv<16> > add_ln47_reg_4800;
sc_signal< sc_lv<1> > icmp_ln46_fu_2886_p2;
sc_signal< sc_lv<8> > add_ln128_fu_2908_p2;
sc_signal< sc_lv<8> > add_ln128_reg_4805;
sc_signal< sc_logic > ap_CS_fsm_state52;
sc_signal< sc_lv<64> > zext_ln128_fu_2914_p1;
sc_signal< sc_lv<64> > zext_ln128_reg_4810;
sc_signal< sc_lv<1> > icmp_ln128_fu_2919_p2;
sc_signal< sc_lv<1> > icmp_ln128_reg_4820;
sc_signal< sc_lv<8> > add_ln128_1_fu_2930_p2;
sc_signal< sc_lv<8> > add_ln128_1_reg_4824;
sc_signal< sc_logic > ap_CS_fsm_state54;
sc_signal< sc_lv<64> > tmp_538_fu_2936_p3;
sc_signal< sc_lv<64> > tmp_538_reg_4829;
sc_signal< sc_lv<1> > icmp_ln128_1_fu_2945_p2;
sc_signal< sc_lv<1> > icmp_ln128_1_reg_4839;
sc_signal< sc_lv<8> > add_ln128_2_fu_2956_p2;
sc_signal< sc_lv<8> > add_ln128_2_reg_4843;
sc_signal< sc_logic > ap_CS_fsm_state56;
sc_signal< sc_lv<64> > tmp_539_fu_2962_p3;
sc_signal< sc_lv<64> > tmp_539_reg_4848;
sc_signal< sc_lv<1> > icmp_ln128_2_fu_2971_p2;
sc_signal< sc_lv<1> > icmp_ln128_2_reg_4858;
sc_signal< sc_lv<8> > add_ln128_3_fu_2982_p2;
sc_signal< sc_lv<8> > add_ln128_3_reg_4862;
sc_signal< sc_logic > ap_CS_fsm_state58;
sc_signal< sc_lv<64> > tmp_540_fu_2988_p3;
sc_signal< sc_lv<64> > tmp_540_reg_4867;
sc_signal< sc_lv<1> > icmp_ln128_3_fu_2997_p2;
sc_signal< sc_lv<1> > icmp_ln128_3_reg_4877;
sc_signal< sc_lv<3> > i_33_fu_3014_p2;
sc_signal< sc_lv<3> > i_33_reg_4884;
sc_signal< sc_logic > ap_CS_fsm_state60;
sc_signal< sc_lv<3> > i_34_fu_3026_p2;
sc_signal< sc_lv<3> > i_34_reg_4892;
sc_signal< sc_logic > ap_CS_fsm_state69;
sc_signal< sc_lv<12> > zext_ln221_fu_3040_p1;
sc_signal< sc_lv<12> > zext_ln221_reg_4897;
sc_signal< sc_lv<1> > icmp_ln371_fu_3020_p2;
sc_signal< sc_lv<9> > i_36_fu_3050_p2;
sc_signal< sc_lv<9> > i_36_reg_4905;
sc_signal< sc_logic > ap_CS_fsm_state70;
sc_signal< sc_lv<64> > zext_ln226_1_fu_3065_p1;
sc_signal< sc_lv<64> > zext_ln226_1_reg_4910;
sc_signal< sc_lv<1> > icmp_ln225_fu_3044_p2;
sc_signal< sc_lv<10> > w1_vec_coeffs_addr_reg_4915;
sc_signal< sc_lv<32> > w1_vec_coeffs_q0;
sc_signal< sc_lv<32> > w1_vec_coeffs_load_reg_4920;
sc_signal< sc_logic > ap_CS_fsm_state71;
sc_signal< sc_lv<25> > trunc_ln18_reg_4925;
sc_signal< sc_lv<8> > a1_1_fu_3130_p2;
sc_signal< sc_lv<8> > a1_1_reg_4930;
sc_signal< sc_logic > ap_CS_fsm_state72;
sc_signal< sc_lv<32> > grp_fu_4313_p3;
sc_signal< sc_lv<32> > add_ln51_reg_4936;
sc_signal< sc_logic > ap_CS_fsm_state73;
sc_signal< sc_lv<5> > i_35_fu_3176_p2;
sc_signal< sc_logic > ap_CS_fsm_state76;
sc_signal< sc_lv<3> > add_ln416_2_fu_3198_p2;
sc_signal< sc_lv<3> > add_ln416_2_reg_4953;
sc_signal< sc_logic > ap_CS_fsm_state77;
sc_signal< sc_lv<8> > zext_ln417_7_fu_3212_p1;
sc_signal< sc_lv<8> > zext_ln417_7_reg_4958;
sc_signal< sc_lv<1> > icmp_ln416_2_fu_3192_p2;
sc_signal< sc_lv<5> > state_s_addr_24_reg_4978;
sc_signal< sc_lv<4> > i_37_fu_3335_p2;
sc_signal< sc_lv<4> > i_37_reg_5016;
sc_signal< sc_logic > ap_CS_fsm_state82;
sc_signal< sc_lv<64> > zext_ln401_3_fu_3349_p1;
sc_signal< sc_lv<64> > zext_ln401_3_reg_5021;
sc_signal< sc_lv<1> > icmp_ln400_1_fu_3329_p2;
sc_signal< sc_lv<5> > state_s_addr_25_reg_5026;
sc_signal< sc_lv<5> > i_38_fu_3377_p2;
sc_signal< sc_lv<5> > i_38_reg_5037;
sc_signal< sc_logic > ap_CS_fsm_state86;
sc_signal< sc_lv<10> > add_ln410_4_fu_3401_p2;
sc_signal< sc_lv<10> > add_ln410_4_reg_5042;
sc_signal< sc_lv<1> > icmp_ln409_1_fu_3371_p2;
sc_signal< sc_lv<10> > add_ln411_1_fu_3407_p2;
sc_signal< sc_lv<10> > add_ln411_1_reg_5047;
sc_signal< sc_lv<10> > add_ln414_fu_3413_p2;
sc_signal< sc_lv<10> > add_ln414_reg_5052;
sc_signal< sc_lv<64> > zext_ln410_5_fu_3419_p1;
sc_signal< sc_lv<64> > zext_ln410_5_reg_5057;
sc_signal< sc_logic > ap_CS_fsm_state87;
sc_signal< sc_lv<5> > state_s_addr_27_reg_5062;
sc_signal< sc_lv<3> > add_ln540_1_fu_3460_p2;
sc_signal< sc_lv<3> > add_ln540_1_reg_5070;
sc_signal< sc_logic > ap_CS_fsm_state93;
sc_signal< sc_lv<1> > icmp_ln540_1_fu_3454_p2;
sc_signal< sc_lv<2> > trunc_ln541_2_fu_3466_p1;
sc_signal< sc_lv<2> > trunc_ln541_2_reg_5080;
sc_signal< sc_lv<5> > shl_ln541_1_fu_3475_p3;
sc_signal< sc_lv<5> > shl_ln541_1_reg_5085;
sc_signal< sc_logic > ap_CS_fsm_state94;
sc_signal< sc_lv<8> > trunc_ln543_1_reg_5095;
sc_signal< sc_lv<8> > trunc_ln544_1_reg_5100;
sc_signal< sc_lv<8> > trunc_ln545_1_reg_5105;
sc_signal< sc_lv<8> > trunc_ln546_1_reg_5110;
sc_signal< sc_lv<8> > trunc_ln547_1_reg_5115;
sc_signal< sc_lv<8> > trunc_ln548_1_reg_5120;
sc_signal< sc_lv<1> > icmp_ln114_fu_3629_p2;
sc_signal< sc_lv<1> > icmp_ln114_reg_5125;
sc_signal< sc_logic > ap_CS_fsm_pp0_stage0;
sc_signal< bool > ap_block_state101_pp0_stage0_iter0;
sc_signal< bool > ap_block_state102_pp0_stage0_iter1;
sc_signal< bool > ap_block_state103_pp0_stage0_iter2;
sc_signal< bool > ap_block_state104_pp0_stage0_iter3;
sc_signal< bool > ap_block_state105_pp0_stage0_iter4;
sc_signal< bool > ap_block_state106_pp0_stage0_iter5;
sc_signal< bool > ap_block_pp0_stage0_11001;
sc_signal< sc_lv<1> > icmp_ln114_reg_5125_pp0_iter1_reg;
sc_signal< sc_lv<1> > icmp_ln114_reg_5125_pp0_iter2_reg;
sc_signal< sc_lv<1> > icmp_ln114_reg_5125_pp0_iter3_reg;
sc_signal< sc_lv<1> > icmp_ln114_reg_5125_pp0_iter4_reg;
sc_signal< sc_lv<11> > add_ln114_fu_3635_p2;
sc_signal< sc_logic > ap_enable_reg_pp0_iter0;
sc_signal< sc_lv<3> > select_ln115_1_fu_3661_p3;
sc_signal< sc_lv<3> > select_ln115_1_reg_5134;
sc_signal< sc_lv<64> > zext_ln181_524_fu_3696_p1;
sc_signal< sc_lv<64> > zext_ln181_524_reg_5139;
sc_signal< sc_lv<64> > zext_ln181_524_reg_5139_pp0_iter1_reg;
sc_signal< sc_lv<64> > zext_ln181_524_reg_5139_pp0_iter2_reg;
sc_signal< sc_lv<64> > zext_ln181_524_reg_5139_pp0_iter3_reg;
sc_signal< sc_lv<64> > zext_ln181_524_reg_5139_pp0_iter4_reg;
sc_signal< sc_lv<9> > i_41_fu_3701_p2;
sc_signal< sc_lv<32> > cp_coeffs_q0;
sc_signal< sc_lv<32> > cp_coeffs_load_reg_5159;
sc_signal< sc_lv<32> > s1_vec_coeffs_q0;
sc_signal< sc_lv<32> > s1_vec_coeffs_load_reg_5164;
sc_signal< sc_lv<64> > mul_ln181_fu_3713_p2;
sc_signal< sc_lv<64> > mul_ln181_reg_5169;
sc_signal< sc_lv<64> > mul_ln181_reg_5169_pp0_iter3_reg;
sc_signal< sc_lv<64> > mul_ln181_reg_5169_pp0_iter4_reg;
sc_signal< sc_lv<32> > trunc_ln18_2_fu_3719_p1;
sc_signal< sc_lv<32> > trunc_ln18_2_reg_5174;
sc_signal< sc_lv<32> > t_fu_3723_p2;
sc_signal< sc_lv<32> > t_reg_5179;
sc_signal< sc_lv<55> > mul_ln19_fu_3731_p2;
sc_signal< sc_lv<55> > mul_ln19_reg_5184;
sc_signal< sc_lv<1> > icmp_ln107_fu_3756_p2;
sc_signal< sc_logic > ap_CS_fsm_state108;
sc_signal< sc_lv<3> > i_42_fu_3762_p2;
sc_signal< sc_lv<3> > i_42_reg_5193;
sc_signal< sc_lv<1> > icmp_ln85_fu_3768_p2;
sc_signal< sc_lv<1> > icmp_ln85_reg_5198;
sc_signal< sc_logic > ap_CS_fsm_pp1_stage0;
sc_signal< bool > ap_block_state110_pp1_stage0_iter0;
sc_signal< bool > ap_block_state111_pp1_stage0_iter1;
sc_signal< bool > ap_block_pp1_stage0_11001;
sc_signal< sc_lv<1
|
1> > add_ln85_fu_3774_p2;
sc_signal< sc_logic > ap_enable_reg_pp1_iter0;
sc_signal< sc_lv<3> > select_ln86_1_fu_3800_p3;
sc_signal< sc_lv<3> > select_ln86_1_reg_5207;
sc_signal< sc_lv<10> > z_vec_coeffs_addr_5_reg_5217;
sc_signal< sc_lv<9> > i_45_fu_3836_p2;
sc_signal< sc_lv<1> > icmp_ln53_fu_3853_p2;
sc_signal< sc_lv<1> > icmp_ln53_reg_5228;
sc_signal< sc_logic > ap_CS_fsm_pp2_stage0;
sc_signal< bool > ap_block_state113_pp2_stage0_iter0;
sc_signal< bool > ap_block_state114_pp2_stage0_iter1;
sc_signal< bool > ap_block_state115_pp2_stage0_iter2;
sc_signal< bool > ap_block_pp2_stage0_11001;
sc_signal< sc_lv<1> > icmp_ln53_reg_5228_pp2_iter1_reg;
sc_signal< sc_lv<11> > add_ln53_fu_3859_p2;
sc_signal< sc_logic > ap_enable_reg_pp2_iter0;
sc_signal< sc_lv<3> > select_ln54_1_fu_3885_p3;
sc_signal< sc_lv<3> > select_ln54_1_reg_5237;
sc_signal< sc_lv<10> > z_vec_coeffs_addr_6_reg_5242;
sc_signal< sc_lv<10> > z_vec_coeffs_addr_6_reg_5242_pp2_iter1_reg;
sc_signal< sc_lv<9> > i_48_fu_3920_p2;
sc_signal< sc_lv<32> > z_vec_coeffs_q1;
sc_signal< sc_lv<32> > z_vec_coeffs_load_1_reg_5253;
sc_signal< sc_logic > ap_enable_reg_pp2_iter1;
sc_signal< sc_lv<9> > trunc_ln20_reg_5258;
sc_signal< sc_lv<1> > icmp_ln158_fu_3945_p2;
sc_signal< sc_lv<1> > icmp_ln158_reg_5263;
sc_signal< sc_logic > ap_CS_fsm_state117;
sc_signal< sc_lv<3> > i_49_fu_3951_p2;
sc_signal< sc_lv<3> > i_49_reg_5267;
sc_signal< sc_lv<12> > zext_ln287_fu_3965_p1;
sc_signal< sc_lv<12> > zext_ln287_reg_5272;
sc_signal< sc_lv<9> > i_51_fu_3975_p2;
sc_signal< sc_lv<9> > i_51_reg_5280;
sc_signal< sc_logic > ap_CS_fsm_state118;
sc_signal< sc_lv<1> > icmp_ln298_fu_3969_p2;
sc_signal< sc_lv<3> > i_50_fu_4041_p2;
sc_signal< sc_lv<3> > i_50_reg_5296;
sc_signal< sc_logic > ap_CS_fsm_state123;
sc_signal< sc_lv<12> > zext_ln104_fu_4055_p1;
sc_signal< sc_lv<12> > zext_ln104_reg_5301;
sc_signal< sc_lv<1> > icmp_ln252_fu_4035_p2;
sc_signal< sc_lv<9> > i_52_fu_4065_p2;
sc_signal< sc_lv<9> > i_52_reg_5309;
sc_signal< sc_logic > ap_CS_fsm_state124;
sc_signal< sc_lv<10> > w0_vec_coeffs_addr_1_reg_5314;
sc_signal< sc_lv<1> > icmp_ln108_fu_4059_p2;
sc_signal< sc_lv<1> > grp_pqcrystals_dilithium_7_fu_1887_ap_return;
sc_signal< sc_lv<1> > tmp_127_reg_5324;
sc_signal< sc_logic > ap_CS_fsm_state128;
sc_signal< sc_logic > grp_pqcrystals_dilithium_7_fu_1887_ap_ready;
sc_signal< sc_logic > grp_pqcrystals_dilithium_7_fu_1887_ap_done;
sc_signal< sc_lv<1> > tmp_226_reg_5328;
sc_signal< sc_logic > ap_CS_fsm_state135;
sc_signal< sc_lv<1> > icmp_ln234_fu_4093_p2;
sc_signal< sc_lv<1> > icmp_ln234_reg_5332;
sc_signal< sc_logic > ap_CS_fsm_pp3_stage0;
sc_signal< bool > ap_block_state136_pp3_stage0_iter0;
sc_signal< bool > ap_block_state137_pp3_stage0_iter1;
sc_signal< bool > ap_block_pp3_stage0_11001;
sc_signal< sc_lv<11> > add_ln234_fu_4099_p2;
sc_signal< sc_logic > ap_enable_reg_pp3_iter0;
sc_signal< sc_lv<3> > select_ln235_1_fu_4125_p3;
sc_signal< sc_lv<3> > select_ln235_1_reg_5341;
sc_signal< sc_lv<10> > w0_vec_coeffs_addr_2_reg_5346;
sc_signal< sc_lv<9> > i_55_fu_4161_p2;
sc_signal< sc_lv<3> > i_56_fu_4180_p2;
sc_signal< sc_lv<3> > i_56_reg_5365;
sc_signal< sc_logic > ap_CS_fsm_state140;
sc_signal< sc_lv<12> > zext_ln244_fu_4194_p1;
sc_signal< sc_lv<12> > zext_ln244_reg_5370;
sc_signal< sc_lv<1> > icmp_ln392_fu_4174_p2;
sc_signal< sc_lv<9> > i_57_fu_4210_p2;
sc_signal< sc_lv<9> > i_57_reg_5381;
sc_signal< sc_logic > ap_CS_fsm_state141;
sc_signal< sc_lv<64> > zext_ln249_1_fu_4225_p1;
sc_signal< sc_lv<64> > zext_ln249_1_reg_5386;
sc_signal< sc_lv<1> > icmp_ln248_fu_4204_p2;
sc_signal< sc_lv<11> > s_fu_4235_p2;
sc_signal< sc_lv<9> > s_1_fu_4298_p2;
sc_signal< sc_logic > ap_CS_fsm_state142;
sc_signal< sc_logic > ap_CS_fsm_state100;
sc_signal< sc_logic > grp_pqcrystals_dilithium_18_fu_1834_ap_ready;
sc_signal< sc_logic > grp_pqcrystals_dilithium_18_fu_1834_ap_done;
sc_signal< bool > ap_block_pp0_stage0_subdone;
sc_signal< sc_logic > ap_condition_pp0_exit_iter0_state101;
sc_signal< sc_logic > ap_enable_reg_pp0_iter1;
sc_signal< sc_logic > ap_enable_reg_pp0_iter2;
sc_signal< sc_logic > ap_enable_reg_pp0_iter3;
sc_signal< sc_logic > ap_enable_reg_pp0_iter4;
sc_signal< sc_logic > ap_enable_reg_pp0_iter5;
sc_signal< bool > ap_block_pp1_stage0_subdone;
sc_signal< sc_logic > ap_condition_pp1_exit_iter0_state110;
sc_signal< sc_logic > ap_enable_reg_pp1_iter1;
sc_signal< sc_logic > ap_CS_fsm_state112;
sc_signal< bool > ap_block_pp2_stage0_subdone;
sc_signal< sc_logic > ap_condition_pp2_exit_iter0_state113;
sc_signal< sc_logic > ap_enable_reg_pp2_iter2;
sc_signal< bool > ap_block_pp3_stage0_subdone;
sc_signal< sc_logic > ap_condition_pp3_exit_iter0_state136;
sc_signal< sc_logic > ap_enable_reg_pp3_iter1;
sc_signal< sc_lv<3> > t_6_address0;
sc_signal< sc_logic > t_6_ce0;
sc_signal< sc_logic > t_6_we0;
sc_signal< sc_lv<3> > t_6_address1;
sc_signal< sc_logic > t_6_ce1;
sc_signal< sc_logic > t_6_we1;
sc_signal< sc_lv<8> > seedbuf_address0;
sc_signal< sc_logic > seedbuf_ce0;
sc_signal< sc_logic > seedbuf_we0;
sc_signal< sc_lv<8> > seedbuf_d0;
sc_signal< sc_lv<8> > seedbuf_address1;
sc_signal< sc_logic > seedbuf_ce1;
sc_signal< sc_logic > seedbuf_we1;
sc_signal< sc_lv<8> > seedbuf_d1;
sc_signal< sc_lv<12> > mat_vec_coeffs_address0;
sc_signal< sc_logic > mat_vec_coeffs_ce0;
sc_signal< sc_logic > mat_vec_coeffs_we0;
sc_signal< sc_lv<23> > mat_vec_coeffs_q0;
sc_signal< sc_logic > mat_vec_coeffs_ce1;
sc_signal< sc_lv<23> > mat_vec_coeffs_q1;
sc_signal< sc_lv<10> > s1_vec_coeffs_address0;
sc_signal< sc_logic > s1_vec_coeffs_ce0;
sc_signal< sc_logic > s1_vec_coeffs_we0;
sc_signal< sc_lv<32> > s1_vec_coeffs_d0;
sc_signal< sc_logic > s1_vec_coeffs_ce1;
sc_signal< sc_logic > s1_vec_coeffs_we1;
sc_signal< sc_lv<10> > y_vec_coeffs_address0;
sc_signal< sc_logic > y_vec_coeffs_ce0;
sc_signal< sc_logic > y_vec_coeffs_we0;
sc_signal< sc_lv<19> > y_vec_coeffs_q0;
sc_signal< sc_lv<10> > z_vec_coeffs_address0;
sc_signal< sc_logic > z_vec_coeffs_ce0;
sc_signal< sc_logic > z_vec_coeffs_we0;
sc_signal< sc_lv<32> > z_vec_coeffs_d0;
sc_signal< sc_lv<32> > z_vec_coeffs_q0;
sc_signal< sc_lv<10> > z_vec_coeffs_address1;
sc_signal< sc_logic > z_vec_coeffs_ce1;
sc_signal< sc_logic > z_vec_coeffs_we1;
sc_signal< sc_lv<32> > z_vec_coeffs_d1;
sc_signal< sc_lv<10> > t0_vec_coeffs_address0;
sc_signal< sc_logic > t0_vec_coeffs_ce0;
sc_signal< sc_logic > t0_vec_coeffs_we0;
sc_signal< sc_lv<32> > t0_vec_coeffs_d0;
sc_signal< sc_lv<32> > t0_vec_coeffs_q0;
sc_signal< sc_logic > t0_vec_coeffs_ce1;
sc_signal< sc_logic > t0_vec_coeffs_we1;
sc_signal< sc_lv<10> > s2_vec_coeffs_address0;
sc_signal< sc_logic > s2_vec_coeffs_ce0;
sc_signal< sc_logic > s2_vec_coeffs_we0;
sc_signal< sc_lv<32> > s2_vec_coeffs_d0;
sc_signal< sc_lv<32> > s2_vec_coeffs_q0;
sc_signal< sc_logic > s2_vec_coeffs_ce1;
sc_signal< sc_logic > s2_vec_coeffs_we1;
sc_signal< sc_lv<10> > w1_vec_coeffs_address0;
sc_signal< sc_logic > w1_vec_coeffs_ce0;
sc_signal< sc_logic > w1_vec_coeffs_we0;
sc_signal< sc_lv<32> > w1_vec_coeffs_d0;
sc_signal< sc_lv<10> > w1_vec_coeffs_address1;
sc_signal< sc_logic > w1_vec_coeffs_ce1;
sc_signal< sc_logic > w1_vec_coeffs_we1;
sc_signal< sc_lv<32> > w1_vec_coeffs_d1;
sc_signal< sc_lv<32> > w1_vec_coeffs_q1;
sc_signal< sc_lv<10> > w0_vec_coeffs_address0;
sc_signal< sc_logic > w0_vec_coeffs_ce0;
sc_signal< sc_logic > w0_vec_coeffs_we0;
sc_signal< sc_lv<32> > w0_vec_coeffs_d0;
sc_signal< sc_lv<32> > w0_vec_coeffs_q0;
sc_signal< sc_lv<10> > w0_vec_coeffs_address1;
sc_signal< sc_logic > w0_vec_coeffs_ce1;
sc_signal< sc_logic > w0_vec_coeffs_we1;
sc_signal< sc_lv<32> > w0_vec_coeffs_d1;
sc_signal< sc_lv<32> > w0_vec_coeffs_q1;
sc_signal< sc_lv<10> > h_vec_coeffs_address0;
sc_signal< sc_logic > h_vec_coeffs_ce0;
sc_signal< sc_logic > h_vec_coeffs_we0;
sc_signal< sc_lv<32> > h_vec_coeffs_d0;
sc_signal< sc_lv<32> > h_vec_coeffs_q0;
sc_signal< sc_lv<10> > h_vec_coeffs_address1;
sc_signal< sc_logic > h_vec_coeffs_ce1;
sc_signal< sc_logic > h_vec_coeffs_we1;
sc_signal< sc_lv<32> > h_vec_coeffs_q1;
sc_signal< sc_lv<8> > cp_coeffs_address0;
sc_signal< sc_logic > cp_coeffs_ce0;
sc_signal< sc_logic > cp_coeffs_we0;
sc_signal< sc_lv<32> > cp_coeffs_d0;
sc_signal< sc_lv<5> > state_s_address0;
sc_signal< sc_logic > state_s_ce0;
sc_signal< sc_logic > state_s_we0;
sc_signal< sc_lv<64> > state_s_d0;
sc_signal< sc_lv<64> > state_s_q0;
sc_signal< sc_lv<5> > state_s_address1;
sc_signal< sc_logic > state_s_ce1;
sc_signal< sc_logic > state_s_we1;
sc_signal< sc_lv<64> > state_s_d1;
sc_signal< sc_lv<64> > state_s_q1;
sc_signal< sc_logic > grp_pqcrystals_dilithium_9_fu_1750_ap_start;
sc_signal< sc_logic > grp_pqcrystals_dilithium_9_fu_1750_ap_done;
sc_signal< sc_logic > grp_pqcrystals_dilithium_9_fu_1750_ap_idle;
sc_signal< sc_logic > grp_pqcrystals_dilithium_9_fu_1750_ap_ready;
sc_signal< sc_lv<10> > grp_pqcrystals_dilithium_9_fu_1750_t_vec_coeffs_address0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_9_fu_1750_t_vec_coeffs_ce0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_9_fu_1750_t_vec_coeffs_we0;
sc_signal< sc_lv<32> > grp_pqcrystals_dilithium_9_fu_1750_t_vec_coeffs_d0;
sc_signal< sc_lv<10> > grp_pqcrystals_dilithium_9_fu_1750_t_vec_coeffs_address1;
sc_signal< sc_logic > grp_pqcrystals_dilithium_9_fu_1750_t_vec_coeffs_ce1;
sc_signal< sc_logic > grp_pqcrystals_dilithium_9_fu_1750_t_vec_coeffs_we1;
sc_signal< sc_lv<32> > grp_pqcrystals_dilithium_9_fu_1750_t_vec_coeffs_d1;
sc_signal< sc_lv<12> > grp_pqcrystals_dilithium_9_fu_1750_mat_vec_coeffs_address0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_9_fu_1750_mat_vec_coeffs_ce0;
sc_signal< sc_lv<12> > grp_pqcrystals_dilithium_9_fu_1750_mat_vec_coeffs_address1;
sc_signal< sc_logic > grp_pqcrystals_dilithium_9_fu_1750_mat_vec_coeffs_ce1;
sc_signal< sc_lv<10> > grp_pqcrystals_dilithium_9_fu_1750_v_vec_coeffs_address0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_9_fu_1750_v_vec_coeffs_ce0;
sc_signal< sc_lv<10> > grp_pqcrystals_dilithium_9_fu_1750_v_vec_coeffs_address1;
sc_signal< sc_logic > grp_pqcrystals_dilithium_9_fu_1750_v_vec_coeffs_ce1;
sc_signal< sc_logic > grp_pqcrystals_dilithium_13_fu_1757_ap_start;
sc_signal< sc_logic > grp_pqcrystals_dilithium_13_fu_1757_ap_done;
sc_signal< sc_logic > grp_pqcrystals_dilithium_13_fu_1757_ap_idle;
sc_signal< sc_logic > grp_pqcrystals_dilithium_13_fu_1757_ap_ready;
sc_signal< sc_lv<12> > grp_pqcrystals_dilithium_13_fu_1757_a_coeffs_address0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_13_fu_1757_a_coeffs_ce0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_13_fu_1757_a_coeffs_we0;
sc_signal< sc_lv<23> > grp_pqcrystals_dilithium_13_fu_1757_a_coeffs_d0;
sc_signal< sc_lv<8> > grp_pqcrystals_dilithium_13_fu_1757_seed_address0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_13_fu_1757_seed_ce0;
sc_signal< sc_lv<8> > grp_pqcrystals_dilithium_13_fu_1757_seed_address1;
sc_signal< sc_logic > grp_pqcrystals_dilithium_13_fu_1757_seed_ce1;
sc_signal< sc_logic > grp_pqcrystals_dilithium_12_fu_1770_ap_start;
sc_signal< sc_logic > grp_pqcrystals_dilithium_12_fu_1770_ap_done;
sc_signal< sc_logic > grp_pqcrystals_dilithium_12_fu_1770_ap_idle;
sc_signal< sc_logic > grp_pqcrystals_dilithium_12_fu_1770_ap_ready;
sc_signal< sc_lv<10> > grp_pqcrystals_dilithium_12_fu_1770_a_coeffs_address0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_12_fu_1770_a_coeffs_ce0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_12_fu_1770_a_coeffs_we0;
sc_signal< sc_lv<19> > grp_pqcrystals_dilithium_12_fu_1770_a_coeffs_d0;
sc_signal< sc_lv<8> > grp_pqcrystals_dilithium_12_fu_1770_seed_address0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_12_fu_1770_seed_ce0;
sc_signal< sc_lv<8> > grp_pqcrystals_dilithium_12_fu_1770_seed_address1;
sc_signal< sc_logic > grp_pqcrystals_dilithium_12_fu_1770_seed_ce1;
sc_signal< sc_logic > grp_pqcrystals_dilithium_15_fu_1781_ap_start;
sc_signal< sc_logic > grp_pqcrystals_dilithium_15_fu_1781_ap_done;
sc_signal< sc_logic > grp_pqcrystals_dilithium_15_fu_1781_ap_idle;
sc_signal< sc_logic > grp_pqcrystals_dilithium_15_fu_1781_ap_ready;
sc_signal< sc_lv<8> > grp_pqcrystals_dilithium_15_fu_1781_c_coeffs_address0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_15_fu_1781_c_coeffs_ce0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_15_fu_1781_c_coeffs_we0;
sc_signal< sc_lv<32> > grp_pqcrystals_dilithium_15_fu_1781_c_coeffs_d0;
sc_signal< sc_lv<13> > grp_pqcrystals_dilithium_15_fu_1781_seed_address0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_15_fu_1781_seed_ce0;
sc_signal< sc_lv<13> > grp_pqcrystals_dilithium_15_fu_1781_seed_address1;
sc_signal< sc_logic > grp_pqcrystals_dilithium_15_fu_1781_seed_ce1;
sc_signal< sc_logic > grp_shake256_fu_1790_ap_start;
sc_signal< sc_logic > grp_shake256_fu_1790_ap_done;
sc_signal< sc_logic > grp_shake256_fu_1790_ap_idle;
sc_signal< sc_logic > grp_shake256_fu_1790_ap_ready;
sc_signal< sc_lv<8> > grp_shake256_fu_1790_out_r_address0;
sc_signal< sc_logic > grp_shake256_fu_1790_out_r_ce0;
sc_signal< sc_logic > grp_shake256_fu_1790_out_r_we0;
sc_signal< sc_lv<8> > grp_shake256_fu_1790_out_r_d0;
sc_signal< sc_lv<8> > grp_shake256_fu_1790_out_r_address1;
sc_signal< sc_logic > grp_shake256_fu_1790_out_r_ce1;
sc_signal< sc_logic > grp_shake256_fu_1790_out_r_we1;
sc_signal< sc_lv<8> > grp_shake256_fu_1790_out_r_d1;
sc_signal< sc_logic > grp_KeccakF1600_StatePer_1_fu_1797_ap_start;
sc_signal< sc_logic > grp_KeccakF1600_StatePer_1_fu_1797_ap_idle;
sc_signal< sc_lv<5> > grp_KeccakF1600_StatePer_1_fu_1797_state_address0;
sc_signal< sc_logic > grp_KeccakF1600_StatePer_1_fu_1797_state_ce0;
sc_signal< sc_logic > grp_KeccakF1600_StatePer_1_fu_1797_state_we0;
sc_signal< sc_lv<64> > grp_KeccakF1600_StatePer_1_fu_1797_state_d0;
sc_signal< sc_lv<5> > grp_KeccakF1600_StatePer_1_fu_1797_state_address1;
sc_signal< sc_logic > grp_KeccakF1600_StatePer_1_fu_1797_state_ce1;
sc_signal< sc_logic > grp_KeccakF1600_StatePer_1_fu_1797_state_we1;
sc_signal< sc_lv<64> > grp_KeccakF1600_StatePer_1_fu_1797_state_d1;
sc_signal< sc_logic > grp_pqcrystals_dilithium_2_fu_1804_ap_start;
sc_signal< sc_logic > grp_pqcrystals_dilithium_2_fu_1804_ap_idle;
sc_signal< sc_lv<8> > grp_pqcrystals_dilithium_2_fu_1804_rho_address0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_2_fu_1804_rho_ce0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_2_fu_1804_rho_we0;
sc_signal< sc_lv<8> > grp_pqcrystals_dilithium_2_fu_1804_rho_d0;
sc_signal< sc_lv<10> > grp_pqcrystals_dilithium_2_fu_1804_t0_vec_coeffs_address0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_2_fu_1804_t0_vec_coeffs_ce0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_2_fu_1804_t0_vec_coeffs_we0;
sc_signal< sc_lv<32> > grp_pqcrystals_dilithium_2_fu_1804_t0_vec_coeffs_d0;
sc_signal< sc_lv<10> > grp_pqcrystals_dilithium_2_fu_1804_t0_vec_coeffs_address1;
sc_signal< sc_logic > grp_pqcrystals_dilithium_2_fu_1804_t0_vec_coeffs_ce1;
sc_signal< sc_logic > grp_pqcrystals_dilithium_2_fu_1804_t0_vec_coeffs_we1;
sc_signal< sc_lv<32> > grp_pqcrystals_dilithium_2_fu_1804_t0_vec_coeffs_d1;
sc_signal< sc_lv<10> > grp_pqcrystals_dilithium_2_fu_1804_s1_vec_coeffs_address0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_2_fu_1804_s1_vec_coeffs_ce0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_2_fu_1804_s1_vec_coeffs_we0;
sc_signal< sc_lv<32> > grp_pqcrystals_dilithium_2_fu_1804_s1_vec_coeffs_d0;
sc_signal< sc_lv<10> > grp_pqcrystals_dilithium_2_fu_1804_s1_vec_coeffs_address1;
sc_signal< sc_logic > grp_pqcrystals_dilithium_2_fu_1804_s1_vec_coeffs_ce1;
sc_signal< sc_logic > grp_pqcrystals_dilithium_2_fu_1804_s1_vec_coeffs_we1;
sc_signal< sc_lv<32> > grp_pqcrystals_dilithium_2_fu_1804_s1_vec_coeffs_d1;
sc_signal< sc_lv<10> > grp_pqcrystals_dilithium_2_fu_1804_s2_vec_coeffs_address0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_2_fu_1804_s2_vec_coeffs_ce0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_2_fu_1804_s2_vec_coeffs_we0;
sc_signal< sc_lv<32> > grp_pqcrystals_dilithium_2_fu_1804_s2_vec_coeffs_d0;
sc_signal< sc_lv<10> > grp_pqcrystals_dilithium_2_fu_1804_s2_vec_coeffs_address1;
sc_signal< sc_logic > grp_pqcrystals_dilithium_2_fu_1804_s2_vec_coeffs_ce1;
sc_signal< sc_logic > grp_pqcrystals_dilithium_2_fu_1804_s2_vec_coeffs_we1;
sc_signal< sc_lv<32> > grp_pqcrystals_dilithium_2_fu_1804_s2_vec_coeffs_d1;
sc_signal< sc_lv<12> > grp_pqcrystals_dilithium_2_fu_1804_sk_address0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_2_fu_1804_sk_ce0;
sc_signal< sc_lv<12> > grp_pqcrystals_dilithium_2_fu_1804_sk_address1;
sc_signal< sc_logic > grp_pqcrystals_dilithium_2_fu_1804_sk_ce1;
sc_signal< sc_logic > grp_pqcrystals_dilithium_6_fu_1818_ap_start;
sc_signal< sc_logic > grp_pqcrystals_dilithium_6_fu_1818_ap_done;
sc_signal< sc_logic > grp_pqcrystals_dilithium_6_fu_1818_ap_idle;
sc_signal< sc_logic > grp_pqcrystals_dilithium_6_fu_1818_ap_ready;
sc_signal< sc_lv<10> > grp_pqcrystals_dilithium_6_fu_1818_v_vec_coeffs_address0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_6_fu_1818_v_vec_coeffs_ce0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_6_fu_1818_v_vec_coeffs_we0;
sc_signal< sc_lv<32> > grp_pqcrystals_dilithium_6_fu_1818_v_vec_coeffs_d0;
sc_signal< sc_lv<32> > grp_pqcrystals_dilithium_6_fu_1818_v_vec_coeffs_q0;
sc_signal< sc_lv<10> > grp_pqcrystals_dilithium_6_fu_1818_v_vec_coeffs_address1;
sc_signal< sc_logic > grp_pqcrystals_dilithium_6_fu_1818_v_vec_coeffs_ce1;
sc_signal< sc_lv<32> > grp_pqcrystals_dilithium_6_fu_1818_v_vec_coeffs_q1;
sc_signal< sc_logic > grp_pqcrystals_dilithium_21_fu_1825_ap_start;
sc_signal< sc_logic > grp_pqcrystals_dilithium_21_fu_1825_ap_done;
sc_signal< sc_logic > grp_pqcrystals_dilithium_21_fu_1825_ap_idle;
sc_signal< sc_logic > grp_pqcrystals_dilithium_21_fu_1825_ap_ready;
sc_signal< sc_lv<10> > grp_pqcrystals_dilithium_21_fu_1825_a_address0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_21_fu_1825_a_ce0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_21_fu_1825_a_we0;
sc_signal< sc_lv<32> > grp_pqcrystals_dilithium_21_fu_1825_a_d0;
sc_signal< sc_lv<10> > grp_pqcrystals_dilithium_21_fu_1825_a_address1;
sc_signal< sc_logic > grp_pqcrystals_dilithium_21_fu_1825_a_ce1;
sc_signal< sc_logic > grp_pqcrystals_dilithium_18_fu_1834_ap_start;
sc_signal< sc_logic > grp_pqcrystals_dilithium_18_fu_1834_ap_idle;
sc_signal< sc_lv<8> > grp_pqcrystals_dilithium_18_fu_1834_a_address0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_18_fu_1834_a_ce0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_18_fu_1834_a_we0;
sc_signal< sc_lv<32> > grp_pqcrystals_dilithium_18_fu_1834_a_d0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_19_fu_1841_ap_start;
sc_signal< sc_logic > grp_pqcrystals_dilithium_19_fu_1841_ap_done;
sc_signal< sc_logic > grp_pqcrystals_dilithium_19_fu_1841_ap_idle;
sc_signal< sc_logic > grp_pqcrystals_dilithium_19_fu_1841_ap_ready;
sc_sig
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nal< sc_lv<10> > grp_pqcrystals_dilithium_19_fu_1841_a_address0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_19_fu_1841_a_ce0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_19_fu_1841_a_we0;
sc_signal< sc_lv<32> > grp_pqcrystals_dilithium_19_fu_1841_a_d0;
sc_signal< sc_lv<32> > grp_pqcrystals_dilithium_19_fu_1841_a_q0;
sc_signal< sc_lv<3> > grp_pqcrystals_dilithium_19_fu_1841_a_offset;
sc_signal< sc_logic > grp_pqcrystals_dilithium_17_fu_1853_ap_start;
sc_signal< sc_logic > grp_pqcrystals_dilithium_17_fu_1853_ap_done;
sc_signal< sc_logic > grp_pqcrystals_dilithium_17_fu_1853_ap_idle;
sc_signal< sc_logic > grp_pqcrystals_dilithium_17_fu_1853_ap_ready;
sc_signal< sc_lv<13> > grp_pqcrystals_dilithium_17_fu_1853_sig_address0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_17_fu_1853_sig_ce0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_17_fu_1853_sig_we0;
sc_signal< sc_lv<8> > grp_pqcrystals_dilithium_17_fu_1853_sig_d0;
sc_signal< sc_lv<10> > grp_pqcrystals_dilithium_17_fu_1853_z_vec_coeffs_address0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_17_fu_1853_z_vec_coeffs_ce0;
sc_signal< sc_lv<10> > grp_pqcrystals_dilithium_17_fu_1853_h_vec_coeffs_address0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_17_fu_1853_h_vec_coeffs_ce0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_4_fu_1861_ap_start;
sc_signal< sc_logic > grp_pqcrystals_dilithium_4_fu_1861_ap_done;
sc_signal< sc_logic > grp_pqcrystals_dilithium_4_fu_1861_ap_idle;
sc_signal< sc_logic > grp_pqcrystals_dilithium_4_fu_1861_ap_ready;
sc_signal< sc_lv<10> > grp_pqcrystals_dilithium_4_fu_1861_r_vec_coeffs_address0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_4_fu_1861_r_vec_coeffs_ce0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_4_fu_1861_r_vec_coeffs_we0;
sc_signal< sc_lv<32> > grp_pqcrystals_dilithium_4_fu_1861_r_vec_coeffs_d0;
sc_signal< sc_lv<8> > grp_pqcrystals_dilithium_4_fu_1861_a_coeffs_address0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_4_fu_1861_a_coeffs_ce0;
sc_signal< sc_lv<10> > grp_pqcrystals_dilithium_4_fu_1861_v_vec_coeffs_address0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_4_fu_1861_v_vec_coeffs_ce0;
sc_signal< sc_lv<32> > grp_pqcrystals_dilithium_4_fu_1861_v_vec_coeffs_q0;
sc_signal< sc_logic > grp_load64_3_fu_1868_ap_start;
sc_signal< sc_logic > grp_load64_3_fu_1868_ap_done;
sc_signal< sc_logic > grp_load64_3_fu_1868_ap_idle;
sc_signal< sc_logic > grp_load64_3_fu_1868_ap_ready;
sc_signal< sc_lv<13> > grp_load64_3_fu_1868_x_address0;
sc_signal< sc_logic > grp_load64_3_fu_1868_x_ce0;
sc_signal< sc_lv<13> > grp_load64_3_fu_1868_x_address1;
sc_signal< sc_logic > grp_load64_3_fu_1868_x_ce1;
sc_signal< sc_lv<64> > grp_load64_3_fu_1868_x_offset;
sc_signal< sc_lv<64> > grp_load64_3_fu_1868_ap_return;
sc_signal< sc_logic > grp_pqcrystals_dilithium_5_fu_1875_ap_start;
sc_signal< sc_logic > grp_pqcrystals_dilithium_5_fu_1875_ap_done;
sc_signal< sc_logic > grp_pqcrystals_dilithium_5_fu_1875_ap_idle;
sc_signal< sc_logic > grp_pqcrystals_dilithium_5_fu_1875_ap_ready;
sc_signal< sc_lv<13> > grp_pqcrystals_dilithium_5_fu_1875_r_address0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_5_fu_1875_r_ce0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_5_fu_1875_r_we0;
sc_signal< sc_lv<8> > grp_pqcrystals_dilithium_5_fu_1875_r_d0;
sc_signal< sc_lv<13> > grp_pqcrystals_dilithium_5_fu_1875_r_address1;
sc_signal< sc_logic > grp_pqcrystals_dilithium_5_fu_1875_r_ce1;
sc_signal< sc_logic > grp_pqcrystals_dilithium_5_fu_1875_r_we1;
sc_signal< sc_lv<8> > grp_pqcrystals_dilithium_5_fu_1875_r_d1;
sc_signal< sc_lv<10> > grp_pqcrystals_dilithium_5_fu_1875_w1_vec_coeffs_address0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_5_fu_1875_w1_vec_coeffs_ce0;
sc_signal< sc_lv<10> > grp_pqcrystals_dilithium_5_fu_1875_w1_vec_coeffs_address1;
sc_signal< sc_logic > grp_pqcrystals_dilithium_5_fu_1875_w1_vec_coeffs_ce1;
sc_signal< sc_logic > grp_pqcrystals_dilithium_3_fu_1882_ap_start;
sc_signal< sc_logic > grp_pqcrystals_dilithium_3_fu_1882_ap_done;
sc_signal< sc_logic > grp_pqcrystals_dilithium_3_fu_1882_ap_idle;
sc_signal< sc_logic > grp_pqcrystals_dilithium_3_fu_1882_ap_ready;
sc_signal< sc_lv<10> > grp_pqcrystals_dilithium_3_fu_1882_v_vec_coeffs_address0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_3_fu_1882_v_vec_coeffs_ce0;
sc_signal< sc_lv<32> > grp_pqcrystals_dilithium_3_fu_1882_v_vec_coeffs_q0;
sc_signal< sc_lv<10> > grp_pqcrystals_dilithium_3_fu_1882_v_vec_coeffs_address1;
sc_signal< sc_logic > grp_pqcrystals_dilithium_3_fu_1882_v_vec_coeffs_ce1;
sc_signal< sc_logic > grp_pqcrystals_dilithium_3_fu_1882_v_vec_coeffs_we1;
sc_signal< sc_lv<32> > grp_pqcrystals_dilithium_3_fu_1882_v_vec_coeffs_d1;
sc_signal< sc_logic > grp_pqcrystals_dilithium_7_fu_1887_ap_start;
sc_signal< sc_logic > grp_pqcrystals_dilithium_7_fu_1887_ap_idle;
sc_signal< sc_lv<10> > grp_pqcrystals_dilithium_7_fu_1887_v_vec_coeffs_address0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_7_fu_1887_v_vec_coeffs_ce0;
sc_signal< sc_lv<32> > grp_pqcrystals_dilithium_7_fu_1887_v_vec_coeffs_q0;
sc_signal< sc_lv<18> > grp_pqcrystals_dilithium_7_fu_1887_bound;
sc_signal< sc_logic > grp_pqcrystals_dilithium_8_fu_1895_ap_start;
sc_signal< sc_logic > grp_pqcrystals_dilithium_8_fu_1895_ap_done;
sc_signal< sc_logic > grp_pqcrystals_dilithium_8_fu_1895_ap_idle;
sc_signal< sc_logic > grp_pqcrystals_dilithium_8_fu_1895_ap_ready;
sc_signal< sc_lv<10> > grp_pqcrystals_dilithium_8_fu_1895_v_vec_coeffs_address0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_8_fu_1895_v_vec_coeffs_ce0;
sc_signal< sc_lv<32> > grp_pqcrystals_dilithium_8_fu_1895_v_vec_coeffs_q0;
sc_signal< sc_lv<10> > grp_pqcrystals_dilithium_8_fu_1895_v_vec_coeffs_address1;
sc_signal< sc_logic > grp_pqcrystals_dilithium_8_fu_1895_v_vec_coeffs_ce1;
sc_signal< sc_logic > grp_pqcrystals_dilithium_8_fu_1895_v_vec_coeffs_we1;
sc_signal< sc_lv<32> > grp_pqcrystals_dilithium_8_fu_1895_v_vec_coeffs_d1;
sc_signal< sc_lv<5> > i_0_i_i1_reg_1106;
sc_signal< sc_lv<1> > icmp_ln362_fu_1940_p2;
sc_signal< sc_lv<3> > i_3_i_i116_reg_1117;
sc_signal< sc_logic > ap_CS_fsm_state8;
sc_signal< sc_lv<3> > phi_ln387_reg_1128;
sc_signal< sc_lv<4> > i_1_i_i62_reg_1139;
sc_signal< sc_logic > ap_CS_fsm_state11;
sc_signal< sc_lv<7> > ap_phi_mux_p_27_i_i64142_phi_fu_1154_p4;
sc_signal< sc_lv<7> > p_27_i_i64142_reg_1150;
sc_signal< sc_lv<5> > ap_phi_mux_p_23_i_i65_phi_fu_1166_p4;
sc_signal< sc_lv<5> > p_23_i_i65_reg_1162;
sc_signal< sc_lv<64> > add_ln403_fu_2167_p2;
sc_signal< sc_lv<64> > ap_phi_mux_p_2_i_i66_phi_fu_1178_p4;
sc_signal< sc_lv<64> > p_2_i_i66_reg_1175;
sc_signal< sc_lv<64> > indvars_iv_i_i68_reg_1185;
sc_signal< sc_logic > ap_CS_fsm_state17;
sc_signal< sc_lv<64> > p_38_rec_i_i69_reg_1196;
sc_signal< sc_lv<5> > i_2_i_i70_reg_1208;
sc_signal< sc_logic > ap_CS_fsm_state16;
sc_signal< sc_lv<5> > i_3_i_i75_reg_1220;
sc_signal< sc_logic > ap_CS_fsm_state20;
sc_signal< sc_lv<4> > i_4_i_i77_reg_1231;
sc_signal< sc_lv<32> > i_5_i_i81_reg_1242;
sc_signal< sc_logic > ap_CS_fsm_state23;
sc_signal< sc_lv<10> > state_pos_reg_1253;
sc_signal< sc_lv<3> > i_3_i_reg_1263;
sc_signal< sc_logic > ap_CS_fsm_state33;
sc_signal< sc_logic > ap_CS_fsm_state38;
sc_signal< sc_lv<3> > i_0_i3_reg_1275;
sc_signal< sc_logic > ap_CS_fsm_state39;
sc_signal< sc_lv<3> > j_0_i_reg_1287;
sc_signal< sc_logic > ap_CS_fsm_state42;
sc_signal< sc_lv<1> > icmp_ln20_fu_2799_p2;
sc_signal< sc_lv<3> > i_0_i127_reg_1299;
sc_signal< sc_logic > ap_CS_fsm_state44;
sc_signal< sc_lv<3> > i_0_i4_reg_1311;
sc_signal< sc_logic > ap_CS_fsm_state46;
sc_signal< sc_lv<1> > icmp_ln100_fu_2838_p2;
sc_signal< sc_lv<3> > i_0_i6_reg_1323;
sc_signal< sc_logic > ap_CS_fsm_state48;
sc_signal< sc_lv<1> > icmp_ln282_fu_2850_p2;
sc_signal< sc_lv<16> > nonce_assign_reg_1335;
sc_signal< sc_lv<1> > icmp_ln179_fu_4198_p2;
sc_signal< sc_lv<3> > i_0_i11_reg_1346;
sc_signal< sc_logic > ap_CS_fsm_state51;
sc_signal< sc_lv<8> > phi_ln128_reg_1358;
sc_signal< sc_logic > ap_CS_fsm_state53;
sc_signal< sc_lv<8> > phi_ln128_1_reg_1369;
sc_signal< sc_logic > ap_CS_fsm_state55;
sc_signal< sc_lv<8> > phi_ln128_2_reg_1380;
sc_signal< sc_logic > ap_CS_fsm_state57;
sc_signal< sc_lv<8> > phi_ln128_3_reg_1391;
sc_signal< sc_logic > ap_CS_fsm_state59;
sc_signal< sc_lv<3> > i_0_i_reg_1402;
sc_signal< sc_logic > ap_CS_fsm_state61;
sc_signal< sc_lv<3> > i_0_i13_reg_1414;
sc_signal< sc_logic > ap_CS_fsm_state68;
sc_signal< sc_lv<9> > i_0_i_i14_reg_1425;
sc_signal< sc_logic > ap_CS_fsm_state74;
sc_signal< sc_lv<5> > i_0_i_i17_reg_1436;
sc_signal< sc_logic > ap_CS_fsm_state75;
sc_signal< sc_lv<1> > icmp_ln362_1_fu_3170_p2;
sc_signal< sc_lv<3> > i_3_i_i34_reg_1447;
sc_signal< sc_logic > ap_CS_fsm_state81;
sc_signal< sc_lv<4> > i_1_i_i_reg_1458;
sc_signal< sc_logic > ap_CS_fsm_state83;
sc_signal< sc_lv<10> > indvars_iv_i_i_reg_1469;
sc_signal< sc_logic > ap_CS_fsm_state89;
sc_signal< sc_logic > ap_CS_fsm_state84;
sc_signal< sc_lv<10> > p_38_rec_i_i_reg_1481;
sc_signal< sc_lv<5> > i_2_i_i_reg_1493;
sc_signal< sc_logic > ap_CS_fsm_state88;
sc_signal< sc_logic > ap_CS_fsm_state85;
sc_signal< sc_lv<1> > icmp_ln408_1_fu_3365_p2;
sc_signal< sc_lv<3> > i_3_i35_reg_1505;
sc_signal< sc_logic > ap_CS_fsm_state92;
sc_signal< sc_logic > ap_CS_fsm_state97;
sc_signal< sc_lv<3> > ap_phi_mux_i_0_i35_phi_fu_1531_p4;
sc_signal< bool > ap_block_pp0_stage0;
sc_signal< sc_lv<3> > i_0_i41_reg_1549;
sc_signal< sc_logic > ap_CS_fsm_state109;
sc_signal< sc_logic > ap_CS_fsm_state107;
sc_signal< sc_lv<3> > ap_phi_mux_i_0_i43_phi_fu_1576_p4;
sc_signal< bool > ap_block_pp1_stage0;
sc_signal< sc_lv<3> > ap_phi_mux_i_0_i52_phi_fu_1609_p4;
sc_signal< bool > ap_block_pp2_stage0;
sc_signal< sc_lv<3> > i_0_i73_reg_1627;
sc_signal< sc_logic > ap_CS_fsm_state116;
sc_signal< sc_lv<9> > i_0_i_i_reg_1638;
sc_signal< sc_logic > ap_CS_fsm_state119;
sc_signal< sc_lv<1> > icmp_ln303_fu_4029_p2;
sc_signal< sc_lv<3> > i_0_i59_reg_1649;
sc_signal< sc_logic > ap_CS_fsm_state122;
sc_signal< sc_lv<9> > i_0_i_i60_reg_1660;
sc_signal< sc_logic > ap_CS_fsm_state125;
sc_signal< sc_lv<3> > ap_phi_mux_i_0_i67_phi_fu_1686_p4;
sc_signal< bool > ap_block_pp3_stage0;
sc_signal< sc_lv<3> > i_0_i74_reg_1704;
sc_signal< sc_logic > ap_CS_fsm_state139;
sc_signal< sc_lv<11> > n_reg_1715;
sc_signal< sc_lv<9> > i_0_i_i75_reg_1727;
sc_signal< sc_lv<9> > s_0_i_i_reg_1738;
sc_signal< sc_logic > grp_pqcrystals_dilithium_9_fu_1750_ap_start_reg;
sc_signal< sc_lv<1> > icmp_ln100_1_fu_3008_p2;
sc_signal< sc_logic > ap_CS_fsm_state62;
sc_signal< sc_logic > grp_pqcrystals_dilithium_13_fu_1757_ap_start_reg;
sc_signal< sc_logic > grp_pqcrystals_dilithium_12_fu_1770_ap_start_reg;
sc_signal< sc_logic > grp_pqcrystals_dilithium_15_fu_1781_ap_start_reg;
sc_signal< sc_logic > ap_CS_fsm_state98;
sc_signal< sc_logic > grp_shake256_fu_1790_ap_start_reg;
sc_signal< sc_logic > grp_KeccakF1600_StatePer_1_fu_1797_ap_start_reg;
sc_signal< sc_logic > ap_CS_fsm_state32;
sc_signal< sc_logic > ap_CS_fsm_state91;
sc_signal< sc_logic > grp_pqcrystals_dilithium_2_fu_1804_ap_start_reg;
sc_signal< sc_logic > grp_pqcrystals_dilithium_6_fu_1818_ap_start_reg;
sc_signal< sc_logic > ap_CS_fsm_state65;
sc_signal< sc_logic > ap_CS_fsm_state121;
sc_signal< sc_logic > ap_CS_fsm_state130;
sc_signal< sc_logic > ap_CS_fsm_state66;
sc_signal< sc_logic > ap_CS_fsm_state131;
sc_signal< sc_logic > grp_pqcrystals_dilithium_21_fu_1825_ap_start_reg;
sc_signal< sc_logic > grp_pqcrystals_dilithium_18_fu_1834_ap_start_reg;
sc_signal< sc_logic > ap_CS_fsm_state99;
sc_signal< sc_logic > grp_pqcrystals_dilithium_19_fu_1841_ap_start_reg;
sc_signal< sc_logic > grp_pqcrystals_dilithium_17_fu_1853_ap_start_reg;
sc_signal< sc_logic > ap_CS_fsm_state143;
sc_signal< sc_logic > grp_pqcrystals_dilithium_4_fu_1861_ap_start_reg;
sc_signal< sc_logic > ap_CS_fsm_state120;
sc_signal< sc_logic > ap_CS_fsm_state129;
sc_signal< sc_logic > grp_load64_3_fu_1868_ap_start_reg;
sc_signal< sc_logic > grp_pqcrystals_dilithium_5_fu_1875_ap_start_reg;
sc_signal< sc_logic > grp_pqcrystals_dilithium_3_fu_1882_ap_start_reg;
sc_signal< sc_logic > ap_CS_fsm_state63;
sc_signal< sc_logic > ap_CS_fsm_state132;
sc_signal< sc_logic > ap_CS_fsm_state64;
sc_signal< sc_logic > ap_CS_fsm_state126;
sc_signal< sc_logic > ap_CS_fsm_state133;
sc_signal< sc_logic > grp_pqcrystals_dilithium_7_fu_1887_ap_start_reg;
sc_signal< sc_logic > ap_CS_fsm_state127;
sc_signal< sc_logic > ap_CS_fsm_state134;
sc_signal< sc_logic > grp_pqcrystals_dilithium_8_fu_1895_ap_start_reg;
sc_signal< sc_logic > ap_CS_fsm_state67;
sc_signal< sc_logic > ap_CS_fsm_state138;
sc_signal< sc_lv<64> > zext_ln363_fu_1952_p1;
sc_signal< sc_lv<64> > zext_ln417_2_fu_1992_p1;
sc_signal< sc_lv<64> > zext_ln31_fu_2003_p1;
sc_signal< sc_lv<64> > zext_ln416_fu_1957_p1;
sc_signal< sc_lv<64> > zext_ln31_7_fu_2013_p1;
sc_signal< sc_lv<64> > zext_ln31_8_fu_2023_p1;
sc_signal< sc_lv<64> > zext_ln31_9_fu_2033_p1;
sc_signal< sc_lv<64> > zext_ln31_10_fu_2043_p1;
sc_signal< sc_lv<64> > zext_ln31_11_fu_2053_p1;
sc_signal< sc_lv<64> > zext_ln31_12_fu_2063_p1;
sc_signal< sc_lv<64> > zext_ln387_fu_2101_p1;
sc_signal< sc_lv<64> > zext_ln401_2_fu_2162_p1;
sc_signal< sc_lv<64> > zext_ln410_2_fu_2279_p1;
sc_signal< sc_lv<64> > zext_ln417_3_fu_2376_p1;
sc_signal< sc_lv<64> > zext_ln424_fu_2392_p1;
sc_signal< sc_lv<64> > zext_ln426_fu_2440_p1;
sc_signal< sc_lv<64> > zext_ln427_fu_2454_p1;
sc_signal< sc_lv<64> > zext_ln450_1_fu_2501_p1;
sc_signal< sc_lv<64> > zext_ln540_fu_2542_p1;
sc_signal< sc_lv<64> > zext_ln541_2_fu_2582_p1;
sc_signal< sc_lv<64> > zext_ln542_2_fu_2614_p1;
sc_signal< sc_lv<64> > zext_ln543_2_fu_2694_p1;
sc_signal< sc_logic > ap_CS_fsm_state36;
sc_signal< sc_lv<64> > zext_ln544_2_fu_2714_p1;
sc_signal< sc_lv<64> > zext_ln545_2_fu_2734_p1;
sc_signal< sc_logic > ap_CS_fsm_state37;
sc_signal< sc_lv<64> > zext_ln546_2_fu_2754_p1;
sc_signal< sc_lv<64> > zext_ln547_2_fu_2774_p1;
sc_signal< sc_lv<64> > zext_ln548_2_fu_2794_p1;
sc_signal< sc_lv<64> > zext_ln363_1_fu_3182_p1;
sc_signal< sc_lv<64> > zext_ln417_8_fu_3222_p1;
sc_signal< sc_lv<64> > zext_ln31_13_fu_3233_p1;
sc_signal< sc_lv<64> > zext_ln416_1_fu_3187_p1;
sc_signal< sc_lv<64> > zext_ln31_14_fu_3243_p1;
sc_signal< sc_lv<64> > zext_ln31_15_fu_3253_p1;
sc_signal< sc_lv<64> > zext_ln31_16_fu_3263_p1;
sc_signal< sc_lv<64> > zext_ln31_17_fu_3273_p1;
sc_signal< sc_lv<64> > zext_ln31_18_fu_3283_p1;
sc_signal< sc_lv<64> > zext_ln31_19_fu_3293_p1;
sc_signal< sc_lv<64> > zext_ln401_4_fu_3360_p1;
sc_signal< sc_lv<64> > zext_ln410_4_fu_3423_p1;
sc_signal< sc_lv<64> > zext_ln540_1_fu_3449_p1;
sc_signal< sc_lv<64> > zext_ln541_3_fu_3482_p1;
sc_signal< sc_lv<64> > zext_ln542_3_fu_3504_p1;
sc_signal< sc_lv<64> > zext_ln543_3_fu_3574_p1;
sc_signal< sc_logic > ap_CS_fsm_state95;
sc_signal< sc_lv<64> > zext_ln544_3_fu_3584_p1;
sc_signal< sc_lv<64> > zext_ln545_3_fu_3594_p1;
sc_signal< sc_logic > ap_CS_fsm_state96;
sc_signal< sc_lv<64> > zext_ln546_3_fu_3604_p1;
sc_signal< sc_lv<64> > zext_ln547_3_fu_3614_p1;
sc_signal< sc_lv<64> > zext_ln548_3_fu_3624_p1;
sc_signal< sc_lv<64> > zext_ln181_fu_3681_p1;
sc_signal< sc_lv<64> > zext_ln88_3_fu_3830_p1;
sc_signal< sc_lv<64> > zext_ln33_4_fu_3915_p1;
sc_signal< sc_lv<64> > zext_ln300_2_fu_3990_p1;
sc_signal< sc_lv<64> > zext_ln109_1_fu_4080_p1;
sc_signal< sc_lv<64> > zext_ln88_6_fu_4155_p1;
sc_signal< sc_lv<64> > xor_ln417_fu_2088_p2;
sc_signal< sc_lv<64> > grp_fu_1900_p2;
sc_signal< sc_lv<64> > xor_ln427_fu_2476_p2;
sc_signal< sc_logic > ap_CS_fsm_state29;
sc_signal< sc_lv<64> > xor_ln450_fu_2528_p2;
sc_signal< sc_logic > ap_CS_fsm_state31;
sc_signal< sc_lv<64> > xor_ln451_fu_2535_p2;
sc_signal< sc_lv<64> > xor_ln417_2_fu_3318_p2;
sc_signal< sc_lv<64> > xor_ln410_1_fu_3428_p2;
sc_signal< sc_logic > ap_CS_fsm_state90;
sc_signal< sc_lv<64> > xor_ln450_1_fu_3435_p2;
sc_signal< sc_lv<64> > xor_ln451_1_fu_3442_p2;
sc_signal< sc_lv<8> > trunc_ln541_fu_2559_p1;
sc_signal< sc_lv<8> > trunc_ln541_1_fu_3470_p1;
sc_signal< sc_lv<32> > sext_ln128_fu_2925_p1;
sc_signal< sc_lv<32> > sext_ln128_1_fu_2951_p1;
sc_signal< sc_lv<32> > sext_ln128_2_fu_2977_p1;
sc_signal< sc_lv<32> > sext_ln128_3_fu_3003_p1;
sc_signal< sc_lv<32> > grp_fu_4320_p3;
sc_signal< sc_lv<32> > sext_ln48_1_fu_3139_p1;
sc_signal< sc_lv<32> > sub_ln52_1_fu_3164_p2;
sc_signal< sc_lv<32> > sub_ln109_fu_4086_p2;
sc_signal< sc_lv<32> > add_ln88_1_fu_4167_p2;
sc_signal< sc_lv<32> > zext_ln69_1_fu_4293_p1;
sc_signal< sc_lv<6> > shl_ln_fu_1974_p3;
sc_signal< sc_lv<7> > add_ln417_fu_1986_p2;
sc_signal< sc_lv<7> > add_ln31_fu_1997_p2;
sc_signal< sc_lv<7> > add_ln31_7_fu_2008_p2;
sc_signal< sc_lv<7> > add_ln31_8_fu_2018_p2;
sc_signal< sc_lv<7> > add_ln31_9_fu_2028_p2;
sc_signal< sc_lv<7> > add_ln31_10_fu_2038_p2;
sc_signal< sc_lv<7> > add_ln31_11_fu_2048_p2;
sc_signal< sc_lv<7> > add_ln31_12_fu_2058_p2;
sc_signal< sc_lv<64> > r_7_i_fu_2068_p9;
sc_signal< sc_lv<7> > shl_ln14_fu_2133_p3;
sc_signal< sc_lv<12> > zext_ln401_fu_2141_p1;
sc_signal< sc_lv<12> > add_ln401_fu_2145_p2;
sc_signal< sc_lv<5> > i_1_i_i62_cast106_fu_2117_p1;
sc_signal< sc_lv<5> > add_ln401_1_fu_2156_p2;
sc_signal< sc_lv<6> > sext_ln408_fu_2173_p1;
sc_signal< sc_lv<2> > trunc_ln417_1_fu_2199_p4;
sc_signal< sc_lv<3> > sext_ln417_fu_2209_p1;
sc_signal< sc_lv<8> > shl_ln15_fu_2239_p3;
sc_signal< sc_lv<12> > zext_ln410_fu_2247_p1;
sc_signal< sc_lv<12> > add_ln410_1_fu_2251_p2;
sc_signal< sc_lv<64> > zext_ln410_1_fu_2257_p1;
sc_signal< sc_lv<4> > trunc_ln417_fu_2295_p1;
sc_signal< sc_lv<7> > shl_ln417_1_fu_2299_p3;
sc_signal< sc_lv<12> > zext_ln417_5_fu_2307_p1;
sc_signal< sc_lv<12> > add_ln417_2_fu_2311_p2;
sc_signal< sc_lv<64> > zext_ln417_6_fu_2317_p1;
sc_signal< sc_lv<8> > and_ln_fu_2332_p3;
sc_signal< sc_lv<64> > zext_ln418_fu_2343_p1;
sc_signal< sc_lv<9> > zext_ln418_1_fu_2339_p1;
sc_signal< sc_lv<33> > zext_ln425_1_fu_2409_p1;
sc_signal< sc_lv<14> > trunc_ln425_fu_2405_p1;
sc_signal< sc_lv<14> > add_ln426_1_fu_2424_p2;
sc_signal< sc_lv<14> > add_ln426_2_fu_2430_p2;
sc_signal< sc_lv<14> > add_ln426_3_fu_2435_p2;
sc_signal< sc_lv<6> > lshr_ln_fu_2445_p4;
sc_signal< sc_lv<64> > r_7_i1_fu_2462_p9;
sc_signal< sc_lv<7> > trunc_ln_fu_2487_p4;
sc_signal< sc_lv<29> > sext_ln448_fu_2497_p1;
sc_signal< sc_lv<3> > trunc_ln450_fu_2506_p1;
sc_signal< sc_lv<6> > shl_ln16_fu_2510_p3;
sc_signal< sc_lv<64> > zext_ln450_fu_2518_p1;
sc_signal< sc_lv<64> > shl_ln450_fu_2522_p2;
sc_signal< sc_lv<8> > zext_ln541_fu_2572_p1;
sc_signal< sc_lv<8> > add_ln541_fu_2576_p2;
sc_signal< sc_lv<6> > or_ln542_fu_2598_p2;
sc_signal< sc_lv<8> > zext_ln542_fu_2604_p1;
sc_signal< sc_lv<8> > add_ln542_fu_2608_p2;
sc_signal< sc_lv<6> > or_ln543_fu_2679_p2;
sc_signal< sc_lv<8> > zext_ln543_fu_2684_p1;
sc_signal< sc
|
_lv<8> > add_ln543_fu_2688_p2;
sc_signal< sc_lv<6> > or_ln544_fu_2699_p2;
sc_signal< sc_lv<8> > zext_ln544_fu_2704_p1;
sc_signal< sc_lv<8> > add_ln544_fu_2708_p2;
sc_signal< sc_lv<6> > or_ln545_fu_2719_p2;
sc_signal< sc_lv<8> > zext_ln545_fu_2724_p1;
sc_signal< sc_lv<8> > add_ln545_fu_2728_p2;
sc_signal< sc_lv<6> > or_ln546_fu_2739_p2;
sc_signal< sc_lv<8> > zext_ln546_fu_2744_p1;
sc_signal< sc_lv<8> > add_ln546_fu_2748_p2;
sc_signal< sc_lv<6> > or_ln547_fu_2759_p2;
sc_signal< sc_lv<8> > zext_ln547_fu_2764_p1;
sc_signal< sc_lv<8> > add_ln547_fu_2768_p2;
sc_signal< sc_lv<6> > or_ln548_fu_2779_p2;
sc_signal< sc_lv<8> > zext_ln548_fu_2784_p1;
sc_signal< sc_lv<8> > add_ln548_fu_2788_p2;
sc_signal< sc_lv<2> > trunc_ln22_fu_2823_p1;
sc_signal< sc_lv<16> > zext_ln47_fu_2898_p1;
sc_signal< sc_lv<11> > tmp_541_fu_3032_p3;
sc_signal< sc_lv<12> > zext_ln226_fu_3056_p1;
sc_signal< sc_lv<12> > add_ln226_fu_3060_p2;
sc_signal< sc_lv<32> > add_ln42_fu_3070_p2;
sc_signal< sc_lv<32> > grp_fu_4304_p3;
sc_signal< sc_lv<8> > trunc_ln19_fu_3089_p4;
sc_signal< sc_lv<9> > sext_ln47_fu_3098_p1;
sc_signal< sc_lv<9> > sub_ln48_fu_3102_p2;
sc_signal< sc_lv<1> > tmp_fu_3108_p3;
sc_signal< sc_lv<1> > xor_ln48_fu_3116_p2;
sc_signal< sc_lv<8> > select_ln48_fu_3122_p3;
sc_signal< sc_lv<32> > sub_ln52_fu_3143_p2;
sc_signal< sc_lv<1> > tmp_257_fu_3148_p3;
sc_signal< sc_lv<32> > select_ln52_fu_3156_p3;
sc_signal< sc_lv<6> > shl_ln417_2_fu_3204_p3;
sc_signal< sc_lv<8> > add_ln417_5_fu_3216_p2;
sc_signal< sc_lv<8> > add_ln31_13_fu_3227_p2;
sc_signal< sc_lv<8> > add_ln31_14_fu_3238_p2;
sc_signal< sc_lv<8> > add_ln31_15_fu_3248_p2;
sc_signal< sc_lv<8> > add_ln31_16_fu_3258_p2;
sc_signal< sc_lv<8> > add_ln31_17_fu_3268_p2;
sc_signal< sc_lv<8> > add_ln31_18_fu_3278_p2;
sc_signal< sc_lv<8> > add_ln31_19_fu_3288_p2;
sc_signal< sc_lv<64> > r_7_i2_fu_3298_p9;
sc_signal< sc_lv<7> > shl_ln401_1_fu_3341_p3;
sc_signal< sc_lv<5> > i_1_i_i_cast93_fu_3325_p1;
sc_signal< sc_lv<5> > add_ln401_2_fu_3354_p2;
sc_signal< sc_lv<8> > shl_ln410_1_fu_3383_p3;
sc_signal< sc_lv<8> > add_ln410_3_fu_3391_p2;
sc_signal< sc_lv<10> > zext_ln410_3_fu_3397_p1;
sc_signal< sc_lv<5> > or_ln542_1_fu_3498_p2;
sc_signal< sc_lv<5> > or_ln543_1_fu_3569_p2;
sc_signal< sc_lv<5> > or_ln544_1_fu_3579_p2;
sc_signal< sc_lv<5> > or_ln545_1_fu_3589_p2;
sc_signal< sc_lv<5> > or_ln546_1_fu_3599_p2;
sc_signal< sc_lv<5> > or_ln547_1_fu_3609_p2;
sc_signal< sc_lv<5> > or_ln548_1_fu_3619_p2;
sc_signal< sc_lv<1> > icmp_ln180_fu_3647_p2;
sc_signal< sc_lv<3> > i_40_fu_3641_p2;
sc_signal< sc_lv<11> > tmp_542_fu_3669_p3;
sc_signal< sc_lv<9> > select_ln115_fu_3653_p3;
sc_signal< sc_lv<12> > zext_ln181_522_fu_3677_p1;
sc_signal< sc_lv<12> > zext_ln181_523_fu_3686_p1;
sc_signal< sc_lv<12> > add_ln181_fu_3690_p2;
sc_signal< sc_lv<32> > mul_ln181_fu_3713_p0;
sc_signal< sc_lv<32> > mul_ln181_fu_3713_p1;
sc_signal< sc_lv<32> > mul_ln19_fu_3731_p1;
sc_signal< sc_lv<64> > sext_ln19_1_fu_3737_p1;
sc_signal< sc_lv<64> > add_ln19_fu_3740_p2;
sc_signal< sc_lv<1> > icmp_ln87_fu_3786_p2;
sc_signal< sc_lv<3> > i_44_fu_3780_p2;
sc_signal< sc_lv<11> > tmp_543_fu_3808_p3;
sc_signal< sc_lv<9> > select_ln86_fu_3792_p3;
sc_signal< sc_lv<12> > zext_ln88_2_fu_3820_p1;
sc_signal< sc_lv<12> > zext_ln88_fu_3816_p1;
sc_signal< sc_lv<12> > add_ln88_256_fu_3824_p2;
sc_signal< sc_lv<32> > sext_ln88_fu_3842_p1;
sc_signal< sc_lv<1> > icmp_ln32_fu_3871_p2;
sc_signal< sc_lv<3> > i_47_fu_3865_p2;
sc_signal< sc_lv<11> > tmp_544_fu_3893_p3;
sc_signal< sc_lv<9> > select_ln54_fu_3877_p3;
sc_signal< sc_lv<12> > zext_ln33_3_fu_3905_p1;
sc_signal< sc_lv<12> > zext_ln33_fu_3901_p1;
sc_signal< sc_lv<12> > add_ln33_fu_3909_p2;
sc_signal< sc_lv<32> > add_ln36_fu_3926_p2;
sc_signal< sc_lv<11> > tmp_545_fu_3957_p3;
sc_signal< sc_lv<12> > zext_ln300_fu_3981_p1;
sc_signal< sc_lv<12> > add_ln300_fu_3985_p2;
sc_signal< sc_lv<1> > tmp_258_fu_3995_p3;
sc_signal< sc_lv<32> > shl_ln301_fu_4011_p2;
sc_signal< sc_lv<32> > t_14_fu_4003_p3;
sc_signal< sc_lv<32> > and_ln301_fu_4017_p2;
sc_signal< sc_lv<32> > t_15_fu_4023_p2;
sc_signal< sc_lv<11> > tmp_546_fu_4047_p3;
sc_signal< sc_lv<12> > zext_ln109_fu_4071_p1;
sc_signal< sc_lv<12> > add_ln109_fu_4075_p2;
sc_signal< sc_lv<1> > icmp_ln87_1_fu_4111_p2;
sc_signal< sc_lv<3> > i_54_fu_4105_p2;
sc_signal< sc_lv<11> > tmp_547_fu_4133_p3;
sc_signal< sc_lv<9> > select_ln235_fu_4117_p3;
sc_signal< sc_lv<12> > zext_ln88_5_fu_4145_p1;
sc_signal< sc_lv<12> > zext_ln88_4_fu_4141_p1;
sc_signal< sc_lv<12> > add_ln88_257_fu_4149_p2;
sc_signal< sc_lv<11> > tmp_548_fu_4186_p3;
sc_signal< sc_lv<12> > zext_ln249_fu_4216_p1;
sc_signal< sc_lv<12> > add_ln249_fu_4220_p2;
sc_signal< sc_lv<11> > zext_ln248_fu_4231_p1;
sc_signal< sc_lv<1> > icmp_ln69_2_fu_4253_p2;
sc_signal< sc_lv<1> > icmp_ln69_3_fu_4259_p2;
sc_signal< sc_lv<1> > icmp_ln69_1_fu_4247_p2;
sc_signal< sc_lv<1> > and_ln69_fu_4265_p2;
sc_signal< sc_lv<1> > or_ln69_fu_4271_p2;
sc_signal< sc_lv<1> > icmp_ln69_fu_4241_p2;
sc_signal< sc_lv<1> > or_ln69_1_fu_4277_p2;
sc_signal< sc_lv<1> > xor_ln69_fu_4283_p2;
sc_signal< sc_lv<9> > zext_ln69_fu_4289_p1;
sc_signal< sc_lv<15> > grp_fu_4304_p0;
sc_signal< sc_lv<25> > grp_fu_4304_p2;
sc_signal< sc_lv<19> > grp_fu_4313_p0;
sc_signal< sc_lv<24> > grp_fu_4320_p1;
sc_signal< sc_lv<134> > ap_NS_fsm;
sc_signal< sc_logic > ap_idle_pp0;
sc_signal< sc_logic > ap_enable_pp0;
sc_signal< sc_logic > ap_idle_pp1;
sc_signal< sc_logic > ap_enable_pp1;
sc_signal< sc_logic > ap_idle_pp2;
sc_signal< sc_logic > ap_enable_pp2;
sc_signal< sc_logic > ap_idle_pp3;
sc_signal< sc_logic > ap_enable_pp3;
static const sc_logic ap_const_logic_1;
static const sc_logic ap_const_logic_0;
static const sc_lv<134> ap_ST_fsm_state1;
static const sc_lv<134> ap_ST_fsm_state2;
static const sc_lv<134> ap_ST_fsm_state3;
static const sc_lv<134> ap_ST_fsm_state4;
static const sc_lv<134> ap_ST_fsm_state5;
static const sc_lv<134> ap_ST_fsm_state6;
static const sc_lv<134> ap_ST_fsm_state7;
static const sc_lv<134> ap_ST_fsm_state8;
static const sc_lv<134> ap_ST_fsm_state9;
static const sc_lv<134> ap_ST_fsm_state10;
static const sc_lv<134> ap_ST_fsm_state11;
static const sc_lv<134> ap_ST_fsm_state12;
static const sc_lv<134> ap_ST_fsm_state13;
static const sc_lv<134> ap_ST_fsm_state14;
static const sc_lv<134> ap_ST_fsm_state15;
static const sc_lv<134> ap_ST_fsm_state16;
static const sc_lv<134> ap_ST_fsm_state17;
static const sc_lv<134> ap_ST_fsm_state18;
static const sc_lv<134> ap_ST_fsm_state19;
static const sc_lv<134> ap_ST_fsm_state20;
static const sc_lv<134> ap_ST_fsm_state21;
static const sc_lv<134> ap_ST_fsm_state22;
static const sc_lv<134> ap_ST_fsm_state23;
static const sc_lv<134> ap_ST_fsm_state24;
static const sc_lv<134> ap_ST_fsm_state25;
static const sc_lv<134> ap_ST_fsm_state26;
static const sc_lv<134> ap_ST_fsm_state27;
static const sc_lv<134> ap_ST_fsm_state28;
static const sc_lv<134> ap_ST_fsm_state29;
static const sc_lv<134> ap_ST_fsm_state30;
static const sc_lv<134> ap_ST_fsm_state31;
static const sc_lv<134> ap_ST_fsm_state32;
static const sc_lv<134> ap_ST_fsm_state33;
static const sc_lv<134> ap_ST_fsm_state34;
static const sc_lv<134> ap_ST_fsm_state35;
static const sc_lv<134> ap_ST_fsm_state36;
static const sc_lv<134> ap_ST_fsm_state37;
static const sc_lv<134> ap_ST_fsm_state38;
static const sc_lv<134> ap_ST_fsm_state39;
static const sc_lv<134> ap_ST_fsm_state40;
static const sc_lv<134> ap_ST_fsm_state41;
static const sc_lv<134> ap_ST_fsm_state42;
static const sc_lv<134> ap_ST_fsm_state43;
static const sc_lv<134> ap_ST_fsm_state44;
static const sc_lv<134> ap_ST_fsm_state45;
static const sc_lv<134> ap_ST_fsm_state46;
static const sc_lv<134> ap_ST_fsm_state47;
static const sc_lv<134> ap_ST_fsm_state48;
static const sc_lv<134> ap_ST_fsm_state49;
static const sc_lv<134> ap_ST_fsm_state50;
static const sc_lv<134> ap_ST_fsm_state51;
static const sc_lv<134> ap_ST_fsm_state52;
static const sc_lv<134> ap_ST_fsm_state53;
static const sc_lv<134> ap_ST_fsm_state54;
static const sc_lv<134> ap_ST_fsm_state55;
static const sc_lv<134> ap_ST_fsm_state56;
static const sc_lv<134> ap_ST_fsm_state57;
static const sc_lv<134> ap_ST_fsm_state58;
static const sc_lv<134> ap_ST_fsm_state59;
static const sc_lv<134> ap_ST_fsm_state60;
static const sc_lv<134> ap_ST_fsm_state61;
static const sc_lv<134> ap_ST_fsm_state62;
static const sc_lv<134> ap_ST_fsm_state63;
static const sc_lv<134> ap_ST_fsm_state64;
static const sc_lv<134> ap_ST_fsm_state65;
static const sc_lv<134> ap_ST_fsm_state66;
static const sc_lv<134> ap_ST_fsm_state67;
static const sc_lv<134> ap_ST_fsm_state68;
static const sc_lv<134> ap_ST_fsm_state69;
static const sc_lv<134> ap_ST_fsm_state70;
static const sc_lv<134> ap_ST_fsm_state71;
static const sc_lv<134> ap_ST_fsm_state72;
static const sc_lv<134> ap_ST_fsm_state73;
static const sc_lv<134> ap_ST_fsm_state74;
static const sc_lv<134> ap_ST_fsm_state75;
static const sc_lv<134> ap_ST_fsm_state76;
static const sc_lv<134> ap_ST_fsm_state77;
static const sc_lv<134> ap_ST_fsm_state78;
static const sc_lv<134> ap_ST_fsm_state79;
static const sc_lv<134> ap_ST_fsm_state80;
static const sc_lv<134> ap_ST_fsm_state81;
static const sc_lv<134> ap_ST_fsm_state82;
static const sc_lv<134> ap_ST_fsm_state83;
static const sc_lv<134> ap_ST_fsm_state84;
static const sc_lv<134> ap_ST_fsm_state85;
static const sc_lv<134> ap_ST_fsm_state86;
static const sc_lv<134> ap_ST_fsm_state87;
static const sc_lv<134> ap_ST_fsm_state88;
static const sc_lv<134> ap_ST_fsm_state89;
static const sc_lv<134> ap_ST_fsm_state90;
static const sc_lv<134> ap_ST_fsm_state91;
static const sc_lv<134> ap_ST_fsm_state92;
static const sc_lv<134> ap_ST_fsm_state93;
static const sc_lv<134> ap_ST_fsm_state94;
static const sc_lv<134> ap_ST_fsm_state95;
static const sc_lv<134> ap_ST_fsm_state96;
static const sc_lv<134> ap_ST_fsm_state97;
static const sc_lv<134> ap_ST_fsm_state98;
static const sc_lv<134> ap_ST_fsm_state99;
static const sc_lv<134> ap_ST_fsm_state100;
static const sc_lv<134> ap_ST_fsm_pp0_stage0;
static const sc_lv<134> ap_ST_fsm_state107;
static const sc_lv<134> ap_ST_fsm_state108;
static const sc_lv<134> ap_ST_fsm_state109;
static const sc_lv<134> ap_ST_fsm_pp1_stage0;
static const sc_lv<134> ap_ST_fsm_state112;
static const sc_lv<134> ap_ST_fsm_pp2_stage0;
static const sc_lv<134> ap_ST_fsm_state116;
static const sc_lv<134> ap_ST_fsm_state117;
static const sc_lv<134> ap_ST_fsm_state118;
static const sc_lv<134> ap_ST_fsm_state119;
static const sc_lv<134> ap_ST_fsm_state120;
static const sc_lv<134> ap_ST_fsm_state121;
static const sc_lv<134> ap_ST_fsm_state122;
static const sc_lv<134> ap_ST_fsm_state123;
static const sc_lv<134> ap_ST_fsm_state124;
static const sc_lv<134> ap_ST_fsm_state125;
static const sc_lv<134> ap_ST_fsm_state126;
static const sc_lv<134> ap_ST_fsm_state127;
static const sc_lv<134> ap_ST_fsm_state128;
static const sc_lv<134> ap_ST_fsm_state129;
static const sc_lv<134> ap_ST_fsm_state130;
static const sc_lv<134> ap_ST_fsm_state131;
static const sc_lv<134> ap_ST_fsm_state132;
static const sc_lv<134> ap_ST_fsm_state133;
static const sc_lv<134> ap_ST_fsm_state134;
static const sc_lv<134> ap_ST_fsm_state135;
static const sc_lv<134> ap_ST_fsm_pp3_stage0;
static const sc_lv<134> ap_ST_fsm_state138;
static const sc_lv<134> ap_ST_fsm_state139;
static const sc_lv<134> ap_ST_fsm_state140;
static const sc_lv<134> ap_ST_fsm_state141;
static const sc_lv<134> ap_ST_fsm_state142;
static const sc_lv<134> ap_ST_fsm_state143;
static const bool ap_const_boolean_1;
static const sc_lv<32> ap_const_lv32_0;
static const sc_lv<32> ap_const_lv32_4;
static const sc_lv<32> ap_const_lv32_4D;
static const sc_lv<32> ap_const_lv32_5;
static const sc_lv<32> ap_const_lv32_4E;
static const sc_lv<32> ap_const_lv32_6;
static const sc_lv<32> ap_const_lv32_4F;
static const sc_lv<32> ap_const_lv32_C;
static const sc_lv<1> ap_const_lv1_0;
static const sc_lv<1> ap_const_lv1_1;
static const sc_lv<32> ap_const_lv32_1;
static const sc_lv<32> ap_const_lv32_2;
static const sc_lv<32> ap_const_lv32_3;
static const sc_lv<32> ap_const_lv32_8;
static const sc_lv<32> ap_const_lv32_9;
static const sc_lv<32> ap_const_lv32_B;
static const bool ap_const_boolean_0;
static const sc_lv<32> ap_const_lv32_D;
static const sc_lv<32> ap_const_lv32_E;
static const sc_lv<32> ap_const_lv32_11;
static const sc_lv<32> ap_const_lv32_12;
static const sc_lv<32> ap_const_lv32_14;
static const sc_lv<32> ap_const_lv32_15;
static const sc_lv<32> ap_const_lv32_17;
static const sc_lv<32> ap_const_lv32_18;
static const sc_lv<32> ap_const_lv32_19;
static const sc_lv<32> ap_const_lv32_1A;
static const sc_lv<32> ap_const_lv32_1B;
static const sc_lv<32> ap_const_lv32_1D;
static const sc_lv<32> ap_const_lv32_21;
static const sc_lv<32> ap_const_lv32_22;
static const sc_lv<32> ap_const_lv32_27;
static const sc_lv<32> ap_const_lv32_28;
static const sc_lv<32> ap_const_lv32_2A;
static const sc_lv<32> ap_const_lv32_2C;
static const sc_lv<32> ap_const_lv32_2E;
static const sc_lv<32> ap_const_lv32_30;
static const sc_lv<32> ap_const_lv32_31;
static const sc_lv<32> ap_const_lv32_33;
static const sc_lv<32> ap_const_lv32_35;
static const sc_lv<32> ap_const_lv32_37;
static const sc_lv<32> ap_const_lv32_39;
static const sc_lv<32> ap_const_lv32_3B;
static const sc_lv<32> ap_const_lv32_44;
static const sc_lv<32> ap_const_lv32_45;
static const sc_lv<32> ap_const_lv32_46;
static const sc_lv<32> ap_const_lv32_47;
static const sc_lv<32> ap_const_lv32_48;
static const sc_lv<32> ap_const_lv32_4B;
static const sc_lv<32> ap_const_lv32_4C;
static const sc_lv<32> ap_const_lv32_51;
static const sc_lv<32> ap_const_lv32_55;
static const sc_lv<32> ap_const_lv32_56;
static const sc_lv<32> ap_const_lv32_5C;
static const sc_lv<32> ap_const_lv32_5D;
static const sc_lv<32> ap_const_lv32_64;
static const sc_lv<32> ap_const_lv32_66;
static const sc_lv<32> ap_const_lv32_68;
static const sc_lv<32> ap_const_lv32_6A;
static const sc_lv<32> ap_const_lv32_6C;
static const sc_lv<32> ap_const_lv32_6D;
static const sc_lv<32> ap_const_lv32_72;
static const sc_lv<32> ap_const_lv32_73;
static const sc_lv<32> ap_const_lv32_77;
static const sc_lv<32> ap_const_lv32_7E;
static const sc_lv<32> ap_const_lv32_7F;
static const sc_lv<32> ap_const_lv32_82;
static const sc_lv<32> ap_const_lv32_83;
static const sc_lv<32> ap_const_lv32_84;
static const sc_lv<32> ap_const_lv32_63;
static const sc_lv<32> ap_const_lv32_69;
static const sc_lv<5> ap_const_lv5_0;
static const sc_lv<32> ap_const_lv32_7;
static const sc_lv<3> ap_const_lv3_0;
static const sc_lv<32> ap_const_lv32_A;
static const sc_lv<4> ap_const_lv4_0;
static const sc_lv<7> ap_const_lv7_58;
static const sc_lv<7> ap_const_lv7_0;
static const sc_lv<5> ap_const_lv5_10;
static const sc_lv<32> ap_const_lv32_10;
static const sc_lv<64> ap_const_lv64_0;
static const sc_lv<32> ap_const_lv32_F;
static const sc_lv<32> ap_const_lv32_13;
static const sc_lv<32> ap_const_lv32_16;
static const sc_lv<32> ap_const_lv32_20;
static const sc_lv<32> ap_const_lv32_25;
static const sc_lv<32> ap_const_lv32_26;
static const sc_lv<32> ap_const_lv32_29;
static const sc_lv<32> ap_const_lv32_2B;
static const sc_lv<32> ap_const_lv32_2D;
static const sc_lv<32> ap_const_lv32_2F;
static const sc_lv<16> ap_const_lv16_0;
static const sc_lv<32> ap_const_lv32_32;
static const sc_lv<32> ap_const_lv32_34;
static const sc_lv<8> ap_const_lv8_0;
static const sc_lv<32> ap_const_lv32_36;
static const sc_lv<32> ap_const_lv32_38;
static const sc_lv<32> ap_const_lv32_3A;
static const sc_lv<32> ap_const_lv32_3C;
static const sc_lv<32> ap_const_lv32_43;
static const sc_lv<9> ap_const_lv9_0;
static const sc_lv<32> ap_const_lv32_49;
static const sc_lv<32> ap_const_lv32_4A;
static const sc_lv<32> ap_const_lv32_50;
static const sc_lv<32> ap_const_lv32_52;
static const sc_lv<32> ap_const_lv32_58;
static const sc_lv<10> ap_const_lv10_2A8;
static const sc_lv<32> ap_const_lv32_53;
static const sc_lv<10> ap_const_lv10_0;
static const sc_lv<32> ap_const_lv32_57;
static const sc_lv<32> ap_const_lv32_54;
static const sc_lv<32> ap_const_lv32_5B;
static const sc_lv<32> ap_const_lv32_60;
static const sc_lv<11> ap_const_lv11_0;
static const sc_lv<32> ap_const_lv32_67;
static const sc_lv<32> ap_const_lv32_65;
static const sc_lv<32> ap_const_lv32_6B;
static const sc_lv<32> ap_const_lv32_6E;
static const sc_lv<32> ap_const_lv32_71;
static const sc_lv<32> ap_const_lv32_74;
static const sc_lv<32> ap_const_lv32_81;
static const sc_lv<32> ap_const_lv32_3D;
static const sc_lv<32> ap_const_lv32_61;
static const sc_lv<32> ap_const_lv32_1F;
static const sc_lv<32> ap_const_lv32_5A;
static const sc_lv<32> ap_const_lv32_40;
static const sc_lv<32> ap_const_lv32_70;
static const sc_lv<32> ap_const_lv32_79;
static const sc_lv<32> ap_const_lv32_41;
static const sc_lv<32> ap_const_lv32_7A;
static const sc_lv<32> ap_const_lv32_62;
static const sc_lv<32> ap_const_lv32_85;
static const sc_lv<32> ap_const_lv32_6F;
static const sc_lv<32> ap_const_lv32_78;
static const sc_lv<32> ap_const_lv32_3E;
static const sc_lv<32> ap_const_lv32_7B;
static const sc_lv<32> ap_const_lv32_3F;
static const sc_lv<32> ap_const_lv32_75;
static const sc_lv<32> ap_const_lv32_7C;
static const sc_lv<32> ap_const_lv32_76;
static const sc_lv<32> ap_const_lv32_7D;
static const sc_lv<18> ap_const_lv18_173B2;
static const sc_lv<18> ap_const_lv18_17400;
static const sc_lv<32> ap_const_lv32_42;
static const sc_lv<32> ap_const_lv32_80;
static const sc_lv<64> ap_const_lv64_1;
static const sc_lv<64> ap_const_lv64_2;
static const sc_lv<64> ap_const_lv64_3;
static const sc_lv<64> ap_const_lv64_4;
static const sc_lv<64> ap_const_lv64_5;
static const sc_lv<64> ap_const_lv64_6;
static const sc_lv<64> ap_const_lv64_7;
static const sc_lv<64> ap_const_lv64_10;
static const sc_lv<32> ap_const_lv32_23;
static const sc_lv<32> ap_const_lv32_24;
static const sc_lv<32> ap_const_lv32_5E;
static const sc_lv<32> ap_const_lv32_5F;
static const sc_lv<32> ap_const_lv32_1C;
static const sc_lv<32> ap_const_lv32_1E;
static const sc_lv<32> ap_const_lv32_59;
static const sc_lv<5> ap_const_lv5_19;
static const sc_lv<5> ap_const_lv5_1;
static const sc_lv<3> ap_const_lv3_6;
static const sc_lv<3> ap_const_lv3_1;
static const sc_lv<7> ap_const_lv7_20;
static const sc_lv<7> ap_const_lv7_21;
static const sc_lv<7> ap_const_lv7_22;
static const sc_lv<7> ap_const_lv7
|
_23;
static const sc_lv<7> ap_const_lv7_24;
static const sc_lv<7> ap_const_lv7_25;
static const sc_lv<7> ap_const_lv7_26;
static const sc_lv<7> ap_const_lv7_27;
static const sc_lv<3> ap_const_lv3_7;
static const sc_lv<64> ap_const_lv64_58;
static const sc_lv<4> ap_const_lv4_B;
static const sc_lv<4> ap_const_lv4_1;
static const sc_lv<12> ap_const_lv12_974;
static const sc_lv<5> ap_const_lv5_6;
static const sc_lv<64> ap_const_lv64_FFFFFFFFFFFFFFA8;
static const sc_lv<64> ap_const_lv64_88;
static const sc_lv<5> ap_const_lv5_11;
static const sc_lv<64> ap_const_lv64_FFFFFFFFFFFFFF78;
static const sc_lv<4> ap_const_lv4_8;
static const sc_lv<14> ap_const_lv14_974;
static const sc_lv<64> ap_const_lv64_1F;
static const sc_lv<64> ap_const_lv64_8000000000000000;
static const sc_lv<8> ap_const_lv8_70;
static const sc_lv<6> ap_const_lv6_1;
static const sc_lv<6> ap_const_lv6_2;
static const sc_lv<6> ap_const_lv6_3;
static const sc_lv<6> ap_const_lv6_4;
static const sc_lv<6> ap_const_lv6_5;
static const sc_lv<6> ap_const_lv6_6;
static const sc_lv<6> ap_const_lv6_7;
static const sc_lv<3> ap_const_lv3_4;
static const sc_lv<16> ap_const_lv16_1;
static const sc_lv<16> ap_const_lv16_2;
static const sc_lv<8> ap_const_lv8_1;
static const sc_lv<8> ap_const_lv8_FF;
static const sc_lv<56> ap_const_lv56_1;
static const sc_lv<56> ap_const_lv56_2;
static const sc_lv<56> ap_const_lv56_3;
static const sc_lv<9> ap_const_lv9_100;
static const sc_lv<9> ap_const_lv9_1;
static const sc_lv<9> ap_const_lv9_2B;
static const sc_lv<32> ap_const_lv32_3FF000;
static const sc_lv<32> ap_const_lv32_7FE001;
static const sc_lv<8> ap_const_lv8_71;
static const sc_lv<8> ap_const_lv8_72;
static const sc_lv<8> ap_const_lv8_73;
static const sc_lv<8> ap_const_lv8_74;
static const sc_lv<8> ap_const_lv8_75;
static const sc_lv<8> ap_const_lv8_76;
static const sc_lv<8> ap_const_lv8_77;
static const sc_lv<10> ap_const_lv10_88;
static const sc_lv<8> ap_const_lv8_58;
static const sc_lv<10> ap_const_lv10_378;
static const sc_lv<5> ap_const_lv5_2;
static const sc_lv<5> ap_const_lv5_3;
static const sc_lv<5> ap_const_lv5_4;
static const sc_lv<5> ap_const_lv5_5;
static const sc_lv<5> ap_const_lv5_7;
static const sc_lv<11> ap_const_lv11_400;
static const sc_lv<11> ap_const_lv11_1;
static const sc_lv<32> ap_const_lv32_3802001;
static const sc_lv<55> ap_const_lv55_7FFFFFFF801FFF;
static const sc_lv<32> ap_const_lv32_400000;
static const sc_lv<32> ap_const_lv32_FFFFFFFF;
static const sc_lv<32> ap_const_lv32_1FFB2;
static const sc_lv<11> ap_const_lv11_50;
static const sc_lv<32> ap_const_lv32_17401;
static const sc_lv<32> ap_const_lv32_7E6C01;
static const sc_lv<32> ap_const_lv32_2C0B;
static const sc_lv<32> ap_const_lv32_800000;
static const sc_lv<27> ap_const_lv27_7FD1800;
static const sc_lv<32> ap_const_lv32_FF801FFF;
// Thread declarations
void thread_ap_var_for_const0();
void thread_ap_clk_no_reset_();
void thread_a1_1_fu_3130_p2();
void thread_add_ln109_fu_4075_p2();
void thread_add_ln114_fu_3635_p2();
void thread_add_ln128_1_fu_2930_p2();
void thread_add_ln128_2_fu_2956_p2();
void thread_add_ln128_3_fu_2982_p2();
void thread_add_ln128_fu_2908_p2();
void thread_add_ln181_fu_3690_p2();
void thread_add_ln19_fu_3740_p2();
void thread_add_ln226_fu_3060_p2();
void thread_add_ln234_fu_4099_p2();
void thread_add_ln249_fu_4220_p2();
void thread_add_ln300_fu_3985_p2();
void thread_add_ln31_10_fu_2038_p2();
void thread_add_ln31_11_fu_2048_p2();
void thread_add_ln31_12_fu_2058_p2();
void thread_add_ln31_13_fu_3227_p2();
void thread_add_ln31_14_fu_3238_p2();
void thread_add_ln31_15_fu_3248_p2();
void thread_add_ln31_16_fu_3258_p2();
void thread_add_ln31_17_fu_3268_p2();
void thread_add_ln31_18_fu_3278_p2();
void thread_add_ln31_19_fu_3288_p2();
void thread_add_ln31_7_fu_2008_p2();
void thread_add_ln31_8_fu_2018_p2();
void thread_add_ln31_9_fu_2028_p2();
void thread_add_ln31_fu_1997_p2();
void thread_add_ln33_fu_3909_p2();
void thread_add_ln36_fu_3926_p2();
void thread_add_ln387_fu_2095_p2();
void thread_add_ln401_1_fu_2156_p2();
void thread_add_ln401_2_fu_3354_p2();
void thread_add_ln401_fu_2145_p2();
void thread_add_ln403_fu_2167_p2();
void thread_add_ln410_1_fu_2251_p2();
void thread_add_ln410_2_fu_2261_p2();
void thread_add_ln410_3_fu_3391_p2();
void thread_add_ln410_4_fu_3401_p2();
void thread_add_ln411_1_fu_3407_p2();
void thread_add_ln411_fu_2267_p2();
void thread_add_ln414_1_fu_2273_p2();
void thread_add_ln414_fu_3413_p2();
void thread_add_ln416_1_fu_2289_p2();
void thread_add_ln416_2_fu_3198_p2();
void thread_add_ln416_fu_1968_p2();
void thread_add_ln417_2_fu_2311_p2();
void thread_add_ln417_3_fu_2321_p2();
void thread_add_ln417_4_fu_2327_p2();
void thread_add_ln417_5_fu_3216_p2();
void thread_add_ln417_fu_1986_p2();
void thread_add_ln420_fu_2361_p2();
void thread_add_ln426_1_fu_2424_p2();
void thread_add_ln426_2_fu_2430_p2();
void thread_add_ln426_3_fu_2435_p2();
void thread_add_ln426_fu_2397_p2();
void thread_add_ln428_fu_2483_p2();
void thread_add_ln42_fu_3070_p2();
void thread_add_ln47_fu_2902_p2();
void thread_add_ln53_fu_3859_p2();
void thread_add_ln540_1_fu_3460_p2();
void thread_add_ln540_fu_2553_p2();
void thread_add_ln541_fu_2576_p2();
void thread_add_ln542_fu_2608_p2();
void thread_add_ln543_fu_2688_p2();
void thread_add_ln544_fu_2708_p2();
void thread_add_ln545_fu_2728_p2();
void thread_add_ln546_fu_2748_p2();
void thread_add_ln547_fu_2768_p2();
void thread_add_ln548_fu_2788_p2();
void thread_add_ln85_fu_3774_p2();
void thread_add_ln88_1_fu_4167_p2();
void thread_add_ln88_256_fu_3824_p2();
void thread_add_ln88_257_fu_4149_p2();
void thread_add_ln_fu_2827_p4();
void thread_and_ln301_fu_4017_p2();
void thread_and_ln69_fu_4265_p2();
void thread_and_ln_fu_2332_p3();
void thread_ap_CS_fsm_pp0_stage0();
void thread_ap_CS_fsm_pp1_stage0();
void thread_ap_CS_fsm_pp2_stage0();
void thread_ap_CS_fsm_pp3_stage0();
void thread_ap_CS_fsm_state1();
void thread_ap_CS_fsm_state10();
void thread_ap_CS_fsm_state100();
void thread_ap_CS_fsm_state107();
void thread_ap_CS_fsm_state108();
void thread_ap_CS_fsm_state109();
void thread_ap_CS_fsm_state11();
void thread_ap_CS_fsm_state112();
void thread_ap_CS_fsm_state116();
void thread_ap_CS_fsm_state117();
void thread_ap_CS_fsm_state118();
void thread_ap_CS_fsm_state119();
void thread_ap_CS_fsm_state12();
void thread_ap_CS_fsm_state120();
void thread_ap_CS_fsm_state121();
void thread_ap_CS_fsm_state122();
void thread_ap_CS_fsm_state123();
void thread_ap_CS_fsm_state124();
void thread_ap_CS_fsm_state125();
void thread_ap_CS_fsm_state126();
void thread_ap_CS_fsm_state127();
void thread_ap_CS_fsm_state128();
void thread_ap_CS_fsm_state129();
void thread_ap_CS_fsm_state13();
void thread_ap_CS_fsm_state130();
void thread_ap_CS_fsm_state131();
void thread_ap_CS_fsm_state132();
void thread_ap_CS_fsm_state133();
void thread_ap_CS_fsm_state134();
void thread_ap_CS_fsm_state135();
void thread_ap_CS_fsm_state138();
void thread_ap_CS_fsm_state139();
void thread_ap_CS_fsm_state14();
void thread_ap_CS_fsm_state140();
void thread_ap_CS_fsm_state141();
void thread_ap_CS_fsm_state142();
void thread_ap_CS_fsm_state143();
void thread_ap_CS_fsm_state15();
void thread_ap_CS_fsm_state16();
void thread_ap_CS_fsm_state17();
void thread_ap_CS_fsm_state18();
void thread_ap_CS_fsm_state19();
void thread_ap_CS_fsm_state2();
void thread_ap_CS_fsm_state20();
void thread_ap_CS_fsm_state21();
void thread_ap_CS_fsm_state22();
void thread_ap_CS_fsm_state23();
void thread_ap_CS_fsm_state24();
void thread_ap_CS_fsm_state25();
void thread_ap_CS_fsm_state26();
void thread_ap_CS_fsm_state27();
void thread_ap_CS_fsm_state28();
void thread_ap_CS_fsm_state29();
void thread_ap_CS_fsm_state3();
void thread_ap_CS_fsm_state30();
void thread_ap_CS_fsm_state31();
void thread_ap_CS_fsm_state32();
void thread_ap_CS_fsm_state33();
void thread_ap_CS_fsm_state34();
void thread_ap_CS_fsm_state35();
void thread_ap_CS_fsm_state36();
void thread_ap_CS_fsm_state37();
void thread_ap_CS_fsm_state38();
void thread_ap_CS_fsm_state39();
void thread_ap_CS_fsm_state4();
void thread_ap_CS_fsm_state40();
void thread_ap_CS_fsm_state41();
void thread_ap_CS_fsm_state42();
void thread_ap_CS_fsm_state43();
void thread_ap_CS_fsm_state44();
void thread_ap_CS_fsm_state45();
void thread_ap_CS_fsm_state46();
void thread_ap_CS_fsm_state47();
void thread_ap_CS_fsm_state48();
void thread_ap_CS_fsm_state49();
void thread_ap_CS_fsm_state5();
void thread_ap_CS_fsm_state50();
void thread_ap_CS_fsm_state51();
void thread_ap_CS_fsm_state52();
void thread_ap_CS_fsm_state53();
void thread_ap_CS_fsm_state54();
void thread_ap_CS_fsm_state55();
void thread_ap_CS_fsm_state56();
void thread_ap_CS_fsm_state57();
void thread_ap_CS_fsm_state58();
void thread_ap_CS_fsm_state59();
void thread_ap_CS_fsm_state6();
void thread_ap_CS_fsm_state60();
void thread_ap_CS_fsm_state61();
void thread_ap_CS_fsm_state62();
void thread_ap_CS_fsm_state63();
void thread_ap_CS_fsm_state64();
void thread_ap_CS_fsm_state65();
void thread_ap_CS_fsm_state66();
void thread_ap_CS_fsm_state67();
void thread_ap_CS_fsm_state68();
void thread_ap_CS_fsm_state69();
void thread_ap_CS_fsm_state7();
void thread_ap_CS_fsm_state70();
void thread_ap_CS_fsm_state71();
void thread_ap_CS_fsm_state72();
void thread_ap_CS_fsm_state73();
void thread_ap_CS_fsm_state74();
void thread_ap_CS_fsm_state75();
void thread_ap_CS_fsm_state76();
void thread_ap_CS_fsm_state77();
void thread_ap_CS_fsm_state78();
void thread_ap_CS_fsm_state79();
void thread_ap_CS_fsm_state8();
void thread_ap_CS_fsm_state80();
void thread_ap_CS_fsm_state81();
void thread_ap_CS_fsm_state82();
void thread_ap_CS_fsm_state83();
void thread_ap_CS_fsm_state84();
void thread_ap_CS_fsm_state85();
void thread_ap_CS_fsm_state86();
void thread_ap_CS_fsm_state87();
void thread_ap_CS_fsm_state88();
void thread_ap_CS_fsm_state89();
void thread_ap_CS_fsm_state9();
void thread_ap_CS_fsm_state90();
void thread_ap_CS_fsm_state91();
void thread_ap_CS_fsm_state92();
void thread_ap_CS_fsm_state93();
void thread_ap_CS_fsm_state94();
void thread_ap_CS_fsm_state95();
void thread_ap_CS_fsm_state96();
void thread_ap_CS_fsm_state97();
void thread_ap_CS_fsm_state98();
void thread_ap_CS_fsm_state99();
void thread_ap_block_pp0_stage0();
void thread_ap_block_pp0_stage0_11001();
void thread_ap_block_pp0_stage0_subdone();
void thread_ap_block_pp1_stage0();
void thread_ap_block_pp1_stage0_11001();
void thread_ap_block_pp1_stage0_subdone();
void thread_ap_block_pp2_stage0();
void thread_ap_block_pp2_stage0_11001();
void thread_ap_block_pp2_stage0_subdone();
void thread_ap_block_pp3_stage0();
void thread_ap_block_pp3_stage0_11001();
void thread_ap_block_pp3_stage0_subdone();
void thread_ap_block_state101_pp0_stage0_iter0();
void thread_ap_block_state102_pp0_stage0_iter1();
void thread_ap_block_state103_pp0_stage0_iter2();
void thread_ap_block_state104_pp0_stage0_iter3();
void thread_ap_block_state105_pp0_stage0_iter4();
void thread_ap_block_state106_pp0_stage0_iter5();
void thread_ap_block_state110_pp1_stage0_iter0();
void thread_ap_block_state111_pp1_stage0_iter1();
void thread_ap_block_state113_pp2_stage0_iter0();
void thread_ap_block_state114_pp2_stage0_iter1();
void thread_ap_block_state115_pp2_stage0_iter2();
void thread_ap_block_state12_on_subcall_done();
void thread_ap_block_state136_pp3_stage0_iter0();
void thread_ap_block_state137_pp3_stage0_iter1();
void thread_ap_condition_pp0_exit_iter0_state101();
void thread_ap_condition_pp1_exit_iter0_state110();
void thread_ap_condition_pp2_exit_iter0_state113();
void thread_ap_condition_pp3_exit_iter0_state136();
void thread_ap_done();
void thread_ap_enable_pp0();
void thread_ap_enable_pp1();
void thread_ap_enable_pp2();
void thread_ap_enable_pp3();
void thread_ap_idle();
void thread_ap_idle_pp0();
void thread_ap_idle_pp1();
void thread_ap_idle_pp2();
void thread_ap_idle_pp3();
void thread_ap_phi_mux_i_0_i35_phi_fu_1531_p4();
void thread_ap_phi_mux_i_0_i43_phi_fu_1576_p4();
void thread_ap_phi_mux_i_0_i52_phi_fu_1609_p4();
void thread_ap_phi_mux_i_0_i67_phi_fu_1686_p4();
void thread_ap_phi_mux_p_23_i_i65_phi_fu_1166_p4();
void thread_ap_phi_mux_p_27_i_i64142_phi_fu_1154_p4();
void thread_ap_phi_mux_p_2_i_i66_phi_fu_1178_p4();
void thread_ap_ready();
void thread_cp_coeffs_address0();
void thread_cp_coeffs_ce0();
void thread_cp_coeffs_d0();
void thread_cp_coeffs_we0();
void thread_grp_KeccakF1600_StatePer_1_fu_1797_ap_start();
void thread_grp_fu_1900_p2();
void thread_grp_fu_1907_p2();
void thread_grp_fu_4304_p0();
void thread_grp_fu_4304_p2();
void thread_grp_fu_4313_p0();
void thread_grp_fu_4320_p1();
void thread_grp_load64_3_fu_1868_ap_start();
void thread_grp_load64_3_fu_1868_x_offset();
void thread_grp_pqcrystals_dilithium_12_fu_1770_ap_start();
void thread_grp_pqcrystals_dilithium_13_fu_1757_ap_start();
void thread_grp_pqcrystals_dilithium_15_fu_1781_ap_start();
void thread_grp_pqcrystals_dilithium_17_fu_1853_ap_start();
void thread_grp_pqcrystals_dilithium_18_fu_1834_ap_start();
void thread_grp_pqcrystals_dilithium_19_fu_1841_a_offset();
void thread_grp_pqcrystals_dilithium_19_fu_1841_a_q0();
void thread_grp_pqcrystals_dilithium_19_fu_1841_ap_start();
void thread_grp_pqcrystals_dilithium_21_fu_1825_ap_start();
void thread_grp_pqcrystals_dilithium_2_fu_1804_ap_start();
void thread_grp_pqcrystals_dilithium_3_fu_1882_ap_start();
void thread_grp_pqcrystals_dilithium_3_fu_1882_v_vec_coeffs_q0();
void thread_grp_pqcrystals_dilithium_4_fu_1861_ap_start();
void thread_grp_pqcrystals_dilithium_4_fu_1861_v_vec_coeffs_q0();
void thread_grp_pqcrystals_dilithium_5_fu_1875_ap_start();
void thread_grp_pqcrystals_dilithium_6_fu_1818_ap_start();
void thread_grp_pqcrystals_dilithium_6_fu_1818_v_vec_coeffs_q0();
void thread_grp_pqcrystals_dilithium_6_fu_1818_v_vec_coeffs_q1();
void thread_grp_pqcrystals_dilithium_7_fu_1887_ap_start();
void thread_grp_pqcrystals_dilithium_7_fu_1887_bound();
void thread_grp_pqcrystals_dilithium_7_fu_1887_v_vec_coeffs_q0();
void thread_grp_pqcrystals_dilithium_8_fu_1895_ap_start();
void thread_grp_pqcrystals_dilithium_8_fu_1895_v_vec_coeffs_q0();
void thread_grp_pqcrystals_dilithium_9_fu_1750_ap_start();
void thread_grp_shake256_fu_1790_ap_start();
void thread_h_vec_coeffs_address0();
void thread_h_vec_coeffs_address1();
void thread_h_vec_coeffs_ce0();
void thread_h_vec_coeffs_ce1();
void thread_h_vec_coeffs_d0();
void thread_h_vec_coeffs_we0();
void thread_h_vec_coeffs_we1();
void thread_i_1_i_i62_cast106_fu_2117_p1();
void thread_i_1_i_i_cast93_fu_3325_p1();
void thread_i_24_fu_2127_p2();
void thread_i_25_fu_2233_p2();
void thread_i_26_fu_2386_p2();
void thread_i_27_fu_2418_p2();
void thread_i_28_fu_2805_p2();
void thread_i_29_fu_2844_p2();
void thread_i_30_fu_2856_p2();
void thread_i_31_fu_2868_p2();
void thread_i_32_fu_2892_p2();
void thread_i_33_fu_3014_p2();
void thread_i_34_fu_3026_p2();
void thread_i_35_fu_3176_p2();
void thread_i_36_fu_3050_p2();
void thread_i_37_fu_3335_p2();
void thread_i_38_fu_3377_p2();
void thread_i_40_fu_3641_p2();
void thread_i_41_fu_3701_p2();
void thread_i_42_fu_3762_p2();
void thread_i_44_fu_3780_p2();
void thread_i_45_fu_3836_p2();
void thread_i_47_fu_3865_p2();
void thread_i_48_fu_3920_p2();
void thread_i_49_fu_3951_p2();
void thread_i_50_fu_4041_p2();
void thread_i_51_fu_3975_p2();
void thread_i_52_fu_4065_p2();
void thread_i_54_fu_4105_p2();
void thread_i_55_fu_4161_p2();
void thread_i_56_fu_4180_p2();
void thread_i_57_fu_4210_p2();
void thread_i_fu_1946_p2();
void thread_icmp_ln100_1_fu_3008_p2();
void thread_icmp_ln100_fu_2838_p2();
void thread_icmp_ln107_fu_3756_p2();
void thread_icmp_ln108_fu_4059_p2();
void thread_icmp_ln114_fu_3629_p2();
void thread_icmp_ln128_1_fu_2945_p2();
void thread_icmp_ln128_2_fu_2971_p2();
void thread_icmp_ln128_3_fu_2997_p2();
void thread_icmp_ln128_fu_2919_p2();
void thread_icmp_ln158_fu_3945_p2();
void thread_icmp_ln179_fu_4198_p2();
void thread_icmp_ln180_fu_3647_p2();
void thread_icmp_ln20_fu_2799_p2();
void thread_icmp_ln21_fu_2811_p2();
void thread_icmp_ln225_fu_3044_p2();
void thread_icmp_ln234_fu_4093_p2();
void thread_icmp_ln248_fu_4204_p2();
void thread_icmp_ln252_fu_4035_p2();
void thread_icmp_ln282_1_fu_2862_p2();
void thread_icmp_ln282_fu_2850_p2();
void thread_icmp_ln298_fu_3969_p2();
void thread_icmp_ln303_fu_4029_p2();
void thread_icmp_ln32_fu_3871_p2();
void thread_icmp_ln362_1_fu_3170_p2();
void thread_icmp_ln362_fu_1940_p2();
void thread_icmp_ln371_fu_3020_p2();
void thread_icmp_ln387_fu_2106_p2();
void thread_icmp_ln392_fu_4174_p2();
void thread_icmp_ln399_fu_2112_p2();
void thread_icmp_ln400_1_fu_3329_p2();
void thread_icmp_ln400_fu_2121_p2();
void thread_icmp_ln408_1_fu_3365_p2();
void thread_icmp_ln408_fu_2189_p2();
void thread_icmp_ln409_1_fu_3371_p2();
void thread_icmp_ln409_fu_2227_p2();
void thread_icmp_ln416_1_fu_2284_p2();
void thread_icmp_ln416_2_fu_3192_p2();
void thread_icmp_ln416_fu_1962_p2();
void thread_icmp_ln422_fu_2370_p2();
void thread_icmp_ln423_fu_2380_p2();
void thread_icmp_ln425_fu_2413_p2();
void thread_icmp_ln46_fu_2886_p2();
void thread_icmp_ln53_fu_3853_p2();
void thread_icmp_ln540_1_fu_3454_p2();
void thread_icmp_ln540_fu_2547_p2();
void thread_icmp_ln69_1_fu_4247_p2();
void thread_icmp_ln69_2_fu_4253_p2();
void thread_icmp_ln69_3_fu_4259_p2();
void thread_icmp_ln69_fu_4241_p2();
void thread_icmp_ln85_fu_3768_p2();
void thread_icmp_ln87_1_fu_4111_p2();
void thread_icmp_ln87_fu_3786_p2();
void thread_j_fu_2817_p2();
void thread_lshr_ln_fu_2445_p4();
void thread_mat_vec_coeffs_address0();
void thread_mat_vec_coeffs_ce0();
void thread_mat_vec_coeffs_ce1();
void thread_mat_vec_coeffs_we0();
void thread_mul_ln181_fu_3713_p0();
void thread_mul_ln181_fu_3713_p1();
void thread_mul_ln181_fu_3713_p2();
void thread_mul_ln19_fu_3731_p1();
void thread_mul_ln19_fu_3731_p2();
void thread_nonce_fu_2874_p2();
void thread_or_ln542_1_fu_3498_p2();
void thread_or_ln542_fu_2598_p2();
void thread_or_ln543_1_fu_3569_p2();
void thread_or_ln543_fu_2679_p2();
void thread_or_ln544_1_fu_3579_p2();
void thread_or_ln544_fu_2699_p2();
void thread_or_ln545_1_fu_3589_p2();
void thread_or_ln545_fu_2719_p2();
v
|
oid thread_or_ln546_1_fu_3599_p2();
void thread_or_ln546_fu_2739_p2();
void thread_or_ln547_1_fu_3609_p2();
void thread_or_ln547_fu_2759_p2();
void thread_or_ln548_1_fu_3619_p2();
void thread_or_ln548_fu_2779_p2();
void thread_or_ln69_1_fu_4277_p2();
void thread_or_ln69_fu_4271_p2();
void thread_r_7_i1_fu_2462_p9();
void thread_r_7_i2_fu_3298_p9();
void thread_r_7_i_fu_2068_p9();
void thread_s1_vec_coeffs_address0();
void thread_s1_vec_coeffs_ce0();
void thread_s1_vec_coeffs_ce1();
void thread_s1_vec_coeffs_d0();
void thread_s1_vec_coeffs_we0();
void thread_s1_vec_coeffs_we1();
void thread_s2_vec_coeffs_address0();
void thread_s2_vec_coeffs_ce0();
void thread_s2_vec_coeffs_ce1();
void thread_s2_vec_coeffs_d0();
void thread_s2_vec_coeffs_we0();
void thread_s2_vec_coeffs_we1();
void thread_s_1_fu_4298_p2();
void thread_s_fu_4235_p2();
void thread_seedbuf_address0();
void thread_seedbuf_address1();
void thread_seedbuf_ce0();
void thread_seedbuf_ce1();
void thread_seedbuf_d0();
void thread_seedbuf_d1();
void thread_seedbuf_we0();
void thread_seedbuf_we1();
void thread_select_ln115_1_fu_3661_p3();
void thread_select_ln115_fu_3653_p3();
void thread_select_ln235_1_fu_4125_p3();
void thread_select_ln235_fu_4117_p3();
void thread_select_ln48_fu_3122_p3();
void thread_select_ln52_fu_3156_p3();
void thread_select_ln54_1_fu_3885_p3();
void thread_select_ln54_fu_3877_p3();
void thread_select_ln86_1_fu_3800_p3();
void thread_select_ln86_fu_3792_p3();
void thread_sext_ln128_1_fu_2951_p1();
void thread_sext_ln128_2_fu_2977_p1();
void thread_sext_ln128_3_fu_3003_p1();
void thread_sext_ln128_fu_2925_p1();
void thread_sext_ln19_1_fu_3737_p1();
void thread_sext_ln408_fu_2173_p1();
void thread_sext_ln417_fu_2209_p1();
void thread_sext_ln448_fu_2497_p1();
void thread_sext_ln47_fu_3098_p1();
void thread_sext_ln48_1_fu_3139_p1();
void thread_sext_ln88_fu_3842_p1();
void thread_shl_ln14_fu_2133_p3();
void thread_shl_ln15_fu_2239_p3();
void thread_shl_ln16_fu_2510_p3();
void thread_shl_ln17_fu_2564_p3();
void thread_shl_ln301_fu_4011_p2();
void thread_shl_ln401_1_fu_3341_p3();
void thread_shl_ln410_1_fu_3383_p3();
void thread_shl_ln417_1_fu_2299_p3();
void thread_shl_ln417_2_fu_3204_p3();
void thread_shl_ln450_fu_2522_p2();
void thread_shl_ln47_fu_2880_p2();
void thread_shl_ln541_1_fu_3475_p3();
void thread_shl_ln_fu_1974_p3();
void thread_sig_address0();
void thread_sig_address1();
void thread_sig_ce0();
void thread_sig_ce1();
void thread_sig_d0();
void thread_sig_d1();
void thread_sig_we0();
void thread_sig_we1();
void thread_sk_address0();
void thread_sk_address1();
void thread_sk_ce0();
void thread_sk_ce1();
void thread_state_s_addr_20_reg_4672();
void thread_state_s_address0();
void thread_state_s_address1();
void thread_state_s_ce0();
void thread_state_s_ce1();
void thread_state_s_d0();
void thread_state_s_d1();
void thread_state_s_we0();
void thread_state_s_we1();
void thread_sub_ln109_fu_4086_p2();
void thread_sub_ln419_fu_2351_p2();
void thread_sub_ln48_fu_3102_p2();
void thread_sub_ln52_1_fu_3164_p2();
void thread_sub_ln52_fu_3143_p2();
void thread_t0_vec_coeffs_address0();
void thread_t0_vec_coeffs_ce0();
void thread_t0_vec_coeffs_ce1();
void thread_t0_vec_coeffs_d0();
void thread_t0_vec_coeffs_we0();
void thread_t0_vec_coeffs_we1();
void thread_t_14_fu_4003_p3();
void thread_t_15_fu_4023_p2();
void thread_t_6_address0();
void thread_t_6_address1();
void thread_t_6_ce0();
void thread_t_6_ce1();
void thread_t_6_we0();
void thread_t_6_we1();
void thread_t_fu_3723_p2();
void thread_tmp_257_fu_3148_p3();
void thread_tmp_258_fu_3995_p3();
void thread_tmp_538_fu_2936_p3();
void thread_tmp_539_fu_2962_p3();
void thread_tmp_540_fu_2988_p3();
void thread_tmp_541_fu_3032_p3();
void thread_tmp_542_fu_3669_p3();
void thread_tmp_543_fu_3808_p3();
void thread_tmp_544_fu_3893_p3();
void thread_tmp_545_fu_3957_p3();
void thread_tmp_546_fu_4047_p3();
void thread_tmp_547_fu_4133_p3();
void thread_tmp_548_fu_4186_p3();
void thread_tmp_fu_3108_p3();
void thread_trunc_ln18_2_fu_3719_p1();
void thread_trunc_ln19_fu_3089_p4();
void thread_trunc_ln22_fu_2823_p1();
void thread_trunc_ln408_fu_2195_p1();
void thread_trunc_ln417_1_fu_2199_p4();
void thread_trunc_ln417_fu_2295_p1();
void thread_trunc_ln419_fu_2357_p1();
void thread_trunc_ln425_fu_2405_p1();
void thread_trunc_ln428_fu_2459_p1();
void thread_trunc_ln450_fu_2506_p1();
void thread_trunc_ln541_1_fu_3470_p1();
void thread_trunc_ln541_2_fu_3466_p1();
void thread_trunc_ln541_fu_2559_p1();
void thread_trunc_ln_fu_2487_p4();
void thread_w0_vec_coeffs_address0();
void thread_w0_vec_coeffs_address1();
void thread_w0_vec_coeffs_ce0();
void thread_w0_vec_coeffs_ce1();
void thread_w0_vec_coeffs_d0();
void thread_w0_vec_coeffs_d1();
void thread_w0_vec_coeffs_we0();
void thread_w0_vec_coeffs_we1();
void thread_w1_vec_coeffs_address0();
void thread_w1_vec_coeffs_address1();
void thread_w1_vec_coeffs_ce0();
void thread_w1_vec_coeffs_ce1();
void thread_w1_vec_coeffs_d0();
void thread_w1_vec_coeffs_d1();
void thread_w1_vec_coeffs_we0();
void thread_w1_vec_coeffs_we1();
void thread_xor_ln410_1_fu_3428_p2();
void thread_xor_ln417_2_fu_3318_p2();
void thread_xor_ln417_fu_2088_p2();
void thread_xor_ln427_fu_2476_p2();
void thread_xor_ln450_1_fu_3435_p2();
void thread_xor_ln450_fu_2528_p2();
void thread_xor_ln451_1_fu_3442_p2();
void thread_xor_ln451_fu_2535_p2();
void thread_xor_ln48_fu_3116_p2();
void thread_xor_ln69_fu_4283_p2();
void thread_y_vec_coeffs_address0();
void thread_y_vec_coeffs_ce0();
void thread_y_vec_coeffs_we0();
void thread_z_vec_coeffs_address0();
void thread_z_vec_coeffs_address1();
void thread_z_vec_coeffs_ce0();
void thread_z_vec_coeffs_ce1();
void thread_z_vec_coeffs_d0();
void thread_z_vec_coeffs_d1();
void thread_z_vec_coeffs_we0();
void thread_z_vec_coeffs_we1();
void thread_zext_ln104_fu_4055_p1();
void thread_zext_ln109_1_fu_4080_p1();
void thread_zext_ln109_fu_4071_p1();
void thread_zext_ln128_fu_2914_p1();
void thread_zext_ln181_522_fu_3677_p1();
void thread_zext_ln181_523_fu_3686_p1();
void thread_zext_ln181_524_fu_3696_p1();
void thread_zext_ln181_fu_3681_p1();
void thread_zext_ln221_fu_3040_p1();
void thread_zext_ln226_1_fu_3065_p1();
void thread_zext_ln226_fu_3056_p1();
void thread_zext_ln244_fu_4194_p1();
void thread_zext_ln248_fu_4231_p1();
void thread_zext_ln249_1_fu_4225_p1();
void thread_zext_ln249_fu_4216_p1();
void thread_zext_ln287_fu_3965_p1();
void thread_zext_ln300_2_fu_3990_p1();
void thread_zext_ln300_fu_3981_p1();
void thread_zext_ln31_10_fu_2043_p1();
void thread_zext_ln31_11_fu_2053_p1();
void thread_zext_ln31_12_fu_2063_p1();
void thread_zext_ln31_13_fu_3233_p1();
void thread_zext_ln31_14_fu_3243_p1();
void thread_zext_ln31_15_fu_3253_p1();
void thread_zext_ln31_16_fu_3263_p1();
void thread_zext_ln31_17_fu_3273_p1();
void thread_zext_ln31_18_fu_3283_p1();
void thread_zext_ln31_19_fu_3293_p1();
void thread_zext_ln31_7_fu_2013_p1();
void thread_zext_ln31_8_fu_2023_p1();
void thread_zext_ln31_9_fu_2033_p1();
void thread_zext_ln31_fu_2003_p1();
void thread_zext_ln33_3_fu_3905_p1();
void thread_zext_ln33_4_fu_3915_p1();
void thread_zext_ln33_fu_3901_p1();
void thread_zext_ln363_1_fu_3182_p1();
void thread_zext_ln363_fu_1952_p1();
void thread_zext_ln387_fu_2101_p1();
void thread_zext_ln401_1_fu_2151_p1();
void thread_zext_ln401_2_fu_2162_p1();
void thread_zext_ln401_3_fu_3349_p1();
void thread_zext_ln401_4_fu_3360_p1();
void thread_zext_ln401_fu_2141_p1();
void thread_zext_ln408_1_fu_2181_p1();
void thread_zext_ln408_2_fu_2185_p1();
void thread_zext_ln408_fu_2177_p1();
void thread_zext_ln410_1_fu_2257_p1();
void thread_zext_ln410_2_fu_2279_p1();
void thread_zext_ln410_3_fu_3397_p1();
void thread_zext_ln410_4_fu_3423_p1();
void thread_zext_ln410_5_fu_3419_p1();
void thread_zext_ln410_fu_2247_p1();
void thread_zext_ln416_1_fu_3187_p1();
void thread_zext_ln416_fu_1957_p1();
void thread_zext_ln417_2_fu_1992_p1();
void thread_zext_ln417_3_fu_2376_p1();
void thread_zext_ln417_4_fu_2213_p1();
void thread_zext_ln417_5_fu_2307_p1();
void thread_zext_ln417_6_fu_2317_p1();
void thread_zext_ln417_7_fu_3212_p1();
void thread_zext_ln417_8_fu_3222_p1();
void thread_zext_ln417_fu_1982_p1();
void thread_zext_ln418_1_fu_2339_p1();
void thread_zext_ln418_fu_2343_p1();
void thread_zext_ln419_fu_2347_p1();
void thread_zext_ln420_fu_2366_p1();
void thread_zext_ln424_fu_2392_p1();
void thread_zext_ln425_1_fu_2409_p1();
void thread_zext_ln425_fu_2401_p1();
void thread_zext_ln426_fu_2440_p1();
void thread_zext_ln427_fu_2454_p1();
void thread_zext_ln450_1_fu_2501_p1();
void thread_zext_ln450_fu_2518_p1();
void thread_zext_ln47_fu_2898_p1();
void thread_zext_ln540_1_fu_3449_p1();
void thread_zext_ln540_fu_2542_p1();
void thread_zext_ln541_2_fu_2582_p1();
void thread_zext_ln541_3_fu_3482_p1();
void thread_zext_ln541_fu_2572_p1();
void thread_zext_ln542_2_fu_2614_p1();
void thread_zext_ln542_3_fu_3504_p1();
void thread_zext_ln542_fu_2604_p1();
void thread_zext_ln543_2_fu_2694_p1();
void thread_zext_ln543_3_fu_3574_p1();
void thread_zext_ln543_fu_2684_p1();
void thread_zext_ln544_2_fu_2714_p1();
void thread_zext_ln544_3_fu_3584_p1();
void thread_zext_ln544_fu_2704_p1();
void thread_zext_ln545_2_fu_2734_p1();
void thread_zext_ln545_3_fu_3594_p1();
void thread_zext_ln545_fu_2724_p1();
void thread_zext_ln546_2_fu_2754_p1();
void thread_zext_ln546_3_fu_3604_p1();
void thread_zext_ln546_fu_2744_p1();
void thread_zext_ln547_2_fu_2774_p1();
void thread_zext_ln547_3_fu_3614_p1();
void thread_zext_ln547_fu_2764_p1();
void thread_zext_ln548_2_fu_2794_p1();
void thread_zext_ln548_3_fu_3624_p1();
void thread_zext_ln548_fu_2784_p1();
void thread_zext_ln69_1_fu_4293_p1();
void thread_zext_ln69_fu_4289_p1();
void thread_zext_ln88_2_fu_3820_p1();
void thread_zext_ln88_3_fu_3830_p1();
void thread_zext_ln88_4_fu_4141_p1();
void thread_zext_ln88_5_fu_4145_p1();
void thread_zext_ln88_6_fu_4155_p1();
void thread_zext_ln88_fu_3816_p1();
void thread_ap_NS_fsm();
};
}
using namespace ap_rtl;
#endif
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.1
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _contact_discovery_HH_
#define _contact_discovery_HH_
#include "systemc.h"
#include "AESL_pkg.h"
#include "compare.h"
#include "contact_discoverybkb.h"
#include "contact_discoverycud.h"
#include "contact_discoverydEe.h"
#include "contact_discovery_AXILiteS_s_axi.h"
namespace ap_rtl {
template<unsigned int C_S_AXI_AXILITES_ADDR_WIDTH = 11,
unsigned int C_S_AXI_AXILITES_DATA_WIDTH = 32>
struct contact_discovery : public sc_module {
// Port declarations 20
sc_in_clk ap_clk;
sc_in< sc_logic > ap_rst_n;
sc_in< sc_logic > s_axi_AXILiteS_AWVALID;
sc_out< sc_logic > s_axi_AXILiteS_AWREADY;
sc_in< sc_uint<C_S_AXI_AXILITES_ADDR_WIDTH> > s_axi_AXILiteS_AWADDR;
sc_in< sc_logic > s_axi_AXILiteS_WVALID;
sc_out< sc_logic > s_axi_AXILiteS_WREADY;
sc_in< sc_uint<C_S_AXI_AXILITES_DATA_WIDTH> > s_axi_AXILiteS_WDATA;
sc_in< sc_uint<C_S_AXI_AXILITES_DATA_WIDTH/8> > s_axi_AXILiteS_WSTRB;
sc_in< sc_logic > s_axi_AXILiteS_ARVALID;
sc_out< sc_logic > s_axi_AXILiteS_ARREADY;
sc_in< sc_uint<C_S_AXI_AXILITES_ADDR_WIDTH> > s_axi_AXILiteS_ARADDR;
sc_out< sc_logic > s_axi_AXILiteS_RVALID;
sc_in< sc_logic > s_axi_AXILiteS_RREADY;
sc_out< sc_uint<C_S_AXI_AXILITES_DATA_WIDTH> > s_axi_AXILiteS_RDATA;
sc_out< sc_lv<2> > s_axi_AXILiteS_RRESP;
sc_out< sc_logic > s_axi_AXILiteS_BVALID;
sc_in< sc_logic > s_axi_AXILiteS_BREADY;
sc_out< sc_lv<2> > s_axi_AXILiteS_BRESP;
sc_out< sc_logic > interrupt;
sc_signal< sc_logic > ap_var_for_const0;
// Module declarations
contact_discovery(sc_module_name name);
SC_HAS_PROCESS(contact_discovery);
~contact_discovery();
sc_trace_file* mVcdFile;
ofstream mHdltvinHandle;
ofstream mHdltvoutHandle;
contact_discoverybkb* contacts_U;
contact_discoverycud* database_U;
contact_discovery_AXILiteS_s_axi<C_S_AXI_AXILITES_ADDR_WIDTH,C_S_AXI_AXILITES_DATA_WIDTH>* contact_discovery_AXILiteS_s_axi_U;
contact_discoverydEe* results_U;
compare* grp_compare_fu_6234;
sc_signal< sc_logic > ap_rst_n_inv;
sc_signal< sc_logic > ap_start;
sc_signal< sc_logic > ap_done;
sc_signal< sc_logic > ap_idle;
sc_signal< sc_lv<568> > ap_CS_fsm;
sc_signal< sc_logic > ap_CS_fsm_state1;
sc_signal< sc_logic > ap_ready;
sc_signal< sc_lv<32> > operation;
sc_signal< sc_lv<32> > operation_preg;
sc_signal< sc_logic > operation_ap_vld;
sc_signal< sc_lv<32> > operation_in_sig;
sc_signal< sc_logic > operation_ap_vld_preg;
sc_signal< sc_logic > operation_ap_vld_in_sig;
sc_signal< sc_lv<6> > contact_in_address0;
sc_signal< sc_logic > contact_in_ce0;
sc_signal< sc_lv<8> > contact_in_q0;
sc_signal< sc_lv<6> > database_in_address0;
sc_signal< sc_logic > database_in_ce0;
sc_signal< sc_lv<8> > database_in_q0;
sc_signal< sc_lv<9> > matched_out_address0;
sc_signal< sc_logic > matched_out_ce0;
sc_signal< sc_logic > matched_out_we0;
sc_signal< sc_lv<32> > matched_finished_1_data_reg;
sc_signal< sc_lv<32> > matched_finished_1_data_in;
sc_signal< sc_logic > matched_finished_1_vld_reg;
sc_signal< sc_logic > matched_finished_1_vld_in;
sc_signal< sc_logic > matched_finished_1_ack_in;
sc_signal< sc_lv<32> > error_out_1_data_reg;
sc_signal< sc_lv<32> > error_out_1_data_in;
sc_signal< sc_logic > error_out_1_vld_reg;
sc_signal< sc_logic > error_out_1_vld_in;
sc_signal< sc_logic > error_out_1_ack_in;
sc_signal< sc_lv<32> > database_size_out_1_data_reg;
sc_signal< sc_lv<32> > database_size_out_1_data_in;
sc_signal< sc_logic > database_size_out_1_vld_reg;
sc_signal< sc_logic > database_size_out_1_vld_in;
sc_signal< sc_logic > database_size_out_1_ack_in;
sc_signal< sc_lv<32> > contacts_size_out_1_data_reg;
sc_signal< sc_lv<32> > contacts_size_out_1_data_in;
sc_signal< sc_logic > contacts_size_out_1_vld_reg;
sc_signal< sc_logic > contacts_size_out_1_vld_in;
sc_signal< sc_logic > contacts_size_out_1_ack_in;
sc_signal< sc_lv<32> > contacts_size;
sc_signal< sc_lv<32> > database_size;
sc_signal< sc_lv<13> > contacts_address0;
sc_signal< sc_logic > contacts_ce0;
sc_signal< sc_logic > contacts_we0;
sc_signal< sc_lv<8> > contacts_q0;
sc_signal< sc_logic > contacts_ce1;
sc_signal< sc_lv<8> > contacts_q1;
sc_signal< sc_lv<15> > database_address0;
sc_signal< sc_logic > database_ce0;
sc_signal< sc_logic > database_we0;
sc_signal< sc_lv<8> > database_q0;
sc_signal< sc_logic > database_ce1;
sc_signal< sc_lv<8> > database_q1;
sc_signal< sc_logic > operation_blk_n;
sc_signal< sc_lv<32> > operation_read_read_fu_968_p2;
sc_signal< bool > ap_block_state1;
sc_signal< sc_lv<32> > contacts_size_load_reg_7180;
sc_signal< sc_lv<32> > database_size_load_reg_7189;
sc_signal< sc_lv<16> > tmp_6_cast_fu_6404_p3;
sc_signal< sc_lv<16> > tmp_6_cast_reg_7202;
sc_signal< sc_logic > ap_CS_fsm_state2;
sc_signal< sc_lv<1> > tmp_1_fu_6396_p2;
sc_signal< sc_lv<15> > tmp_3_cast_fu_6430_p3;
sc_signal< sc_lv<15> > tmp_3_cast_reg_7210;
sc_signal< sc_lv<1> > icmp_fu_6421_p2;
sc_signal< sc_lv<31> > database_index_1_fu_6447_p2;
sc_signal< sc_lv<31> > database_index_1_reg_7218;
sc_signal< sc_logic > ap_CS_fsm_state3;
sc_signal< sc_lv<1> > tmp_8_fu_6442_p2;
sc_signal< sc_lv<1> > grp_compare_fu_6234_ap_return;
sc_signal< sc_lv<1> > tmp_s_reg_7228;
sc_signal< sc_logic > ap_CS_fsm_state4;
sc_signal< sc_logic > grp_compare_fu_6234_ap_done;
sc_signal< sc_lv<1> > tmp_1_11_reg_7233;
sc_signal< sc_logic > ap_CS_fsm_state6;
sc_signal< sc_lv<1> > tmp_2_13_reg_7238;
sc_signal< sc_logic > ap_CS_fsm_state8;
sc_signal< sc_lv<1> > tmp5_fu_6462_p2;
sc_signal< sc_lv<1> > tmp5_reg_7243;
sc_signal< sc_logic > ap_CS_fsm_state10;
sc_signal< sc_lv<1> > tmp_4_17_reg_7248;
sc_signal< sc_logic > ap_CS_fsm_state12;
sc_signal< sc_lv<1> > tmp_5_19_reg_7253;
sc_signal< sc_logic > ap_CS_fsm_state14;
sc_signal< sc_lv<1> > tmp_6_21_reg_7258;
sc_signal< sc_logic > ap_CS_fsm_state16;
sc_signal< sc_lv<1> > tmp4_fu_6483_p2;
sc_signal< sc_lv<1> > tmp4_reg_7263;
sc_signal< sc_logic > ap_CS_fsm_state18;
sc_signal< sc_lv<1> > tmp_8_25_reg_7268;
sc_signal< sc_logic > ap_CS_fsm_state20;
sc_signal< sc_lv<1> > tmp_9_reg_7273;
sc_signal< sc_logic > ap_CS_fsm_state22;
sc_signal< sc_lv<1> > tmp_s_28_reg_7278;
sc_signal< sc_logic > ap_CS_fsm_state24;
sc_signal< sc_lv<1> > tmp12_fu_6497_p2;
sc_signal< sc_lv<1> > tmp12_reg_7283;
sc_signal< sc_logic > ap_CS_fsm_state26;
sc_signal< sc_lv<1> > tmp_11_32_reg_7288;
sc_signal< sc_logic > ap_CS_fsm_state28;
sc_signal< sc_lv<1> > tmp_12_34_reg_7293;
sc_signal< sc_logic > ap_CS_fsm_state30;
sc_signal< sc_lv<1> > tmp_13_36_reg_7298;
sc_signal< sc_logic > ap_CS_fsm_state32;
sc_signal< sc_lv<1> > tmp3_fu_6523_p2;
sc_signal< sc_lv<1> > tmp3_reg_7303;
sc_signal< sc_logic > ap_CS_fsm_state34;
sc_signal< sc_lv<1> > tmp_15_40_reg_7308;
sc_signal< sc_logic > ap_CS_fsm_state36;
sc_signal< sc_lv<1> > tmp_16_42_reg_7313;
sc_signal< sc_logic > ap_CS_fsm_state38;
sc_signal< sc_lv<1> > tmp_17_44_reg_7318;
sc_signal< sc_logic > ap_CS_fsm_state40;
sc_signal< sc_lv<1> > tmp20_fu_6537_p2;
sc_signal< sc_lv<1> > tmp20_reg_7323;
sc_signal< sc_logic > ap_CS_fsm_state42;
sc_signal< sc_lv<1> > tmp_19_48_reg_7328;
sc_signal< sc_logic > ap_CS_fsm_state44;
sc_signal< sc_lv<1> > tmp_20_50_reg_7333;
sc_signal< sc_logic > ap_CS_fsm_state46;
sc_signal< sc_lv<1> > tmp_21_52_reg_7338;
sc_signal< sc_logic > ap_CS_fsm_state48;
sc_signal< sc_lv<1> > tmp19_fu_6558_p2;
sc_signal< sc_lv<1> > tmp19_reg_7343;
sc_signal< sc_logic > ap_CS_fsm_state50;
sc_signal< sc_lv<1> > tmp_23_56_reg_7348;
sc_signal< sc_logic > ap_CS_fsm_state52;
sc_signal< sc_lv<1> > tmp_24_58_reg_7353;
sc_signal< sc_logic > ap_CS_fsm_state54;
sc_signal< sc_lv<1> > tmp_25_60_reg_7358;
sc_signal< sc_logic > ap_CS_fsm_state56;
sc_signal< sc_lv<1> > tmp27_fu_6572_p2;
sc_signal< sc_lv<1> > tmp27_reg_7363;
sc_signal< sc_logic > ap_CS_fsm_state58;
sc_signal< sc_lv<1> > tmp_27_64_reg_7368;
sc_signal< sc_logic > ap_CS_fsm_state60;
sc_signal< sc_lv<1> > tmp_28_66_reg_7373;
sc_signal< sc_logic > ap_CS_fsm_state62;
sc_signal< sc_lv<1> > tmp_29_68_reg_7378;
sc_signal< sc_logic > ap_CS_fsm_state64;
sc_signal< sc_lv<1> > tmp18_fu_6598_p2;
sc_signal< sc_lv<1> > tmp18_reg_7383;
sc_signal< sc_logic > ap_CS_fsm_state66;
sc_signal< sc_lv<1> > tmp_31_72_reg_7388;
sc_signal< sc_logic > ap_CS_fsm_state68;
sc_signal< sc_lv<1> > tmp_32_74_reg_7393;
sc_signal< sc_logic > ap_CS_fsm_state70;
sc_signal< sc_lv<1> > tmp_33_76_reg_7398;
sc_signal< sc_logic > ap_CS_fsm_state72;
sc_signal< sc_lv<1> > tmp36_fu_6612_p2;
sc_signal< sc_lv<1> > tmp36_reg_7403;
sc_signal< sc_logic > ap_CS_fsm_state74;
sc_signal< sc_lv<1> > tmp_35_80_reg_7408;
sc_signal< sc_logic > ap_CS_fsm_state76;
sc_signal< sc_lv<1> > tmp_36_82_reg_7413;
sc_signal< sc_logic > ap_CS_fsm_state78;
sc_signal< sc_lv<1> > tmp_37_84_reg_7418;
sc_signal< sc_logic > ap_CS_fsm_state80;
sc_signal< sc_lv<1> > tmp35_fu_6633_p2;
sc_signal< sc_lv<1> > tmp35_reg_7423;
sc_signal< sc_logic > ap_CS_fsm_state82;
sc_signal< sc_lv<1> > tmp_39_88_reg_7428;
sc_signal< sc_logic > ap_CS_fsm_state84;
sc_signal< sc_lv<1> > tmp_40_90_reg_7433;
sc_signal< sc_logic > ap_CS_fsm_state86;
sc_signal< sc_lv<1> > tmp_41_92_reg_7438;
sc_signal< sc_logic > ap_CS_fsm_state88;
sc_signal< sc_lv<1> > tmp43_fu_6647_p2;
sc_signal< sc_lv<1> > tmp43_reg_7443;
sc_signal< sc_logic > ap_CS_fsm_state90;
sc_signal< sc_lv<1> > tmp_43_96_reg_7448;
sc_signal< sc_logic > ap_CS_fsm_state92;
sc_signal< sc_lv<1> > tmp_44_98_reg_7453;
sc_signal< sc_logic > ap_CS_fsm_state94;
sc_signal< sc_lv<1> > tmp_45_100_reg_7458;
sc_signal< sc_logic > ap_CS_fsm_state96;
sc_signal< sc_lv<1> > tmp34_fu_6673_p2;
sc_signal< sc_lv<1> > tmp34_reg_7463;
sc_signal< sc_logic > ap_CS_fsm_state98;
sc_signal< sc_lv<1> > tmp_47_104_reg_7468;
sc_signal< sc_logic > ap_CS_fsm_state100;
sc_signal< sc_lv<1> > tmp_48_106_reg_7473;
sc_signal< sc_logic > ap_CS_fsm_state102;
sc_signal< sc_lv<1> > tmp_49_108_reg_7478;
sc_signal< sc_logic > ap_CS_fsm_state104;
sc_signal< sc_lv<1> > tmp51_fu_6687_p2;
sc_signal< sc_lv<1> > tmp51_reg_7483;
sc_signal< sc_logic > ap_CS_fsm_state106;
sc_signal< sc_lv<1> > tmp_51_112_reg_7488;
sc_signal< sc_logic > ap_CS_fsm_state108;
sc_signal< sc_lv<1> > tmp_52_114_reg_7493;
sc_signal< sc_logic > ap_CS_fsm_state110;
sc_signal< sc_lv<1> > tmp_53_116_reg_7498;
sc_signal< sc_logic > ap_CS_fsm_state112;
sc_signal< sc_lv<1> > tmp50_fu_6708_p2;
sc_signal< sc_lv<1> > tmp50_reg_7503;
sc_signal< sc_logic > ap_CS_fsm_state114;
sc_signal< sc_lv<1> > tmp_55_120_reg_7508;
sc_signal< sc_logic > ap_CS_fsm_state116;
sc_signal< sc_lv<1> > tmp_56_122_reg_7513;
sc_signal< sc_logic > ap_CS_fsm_state118;
sc_signal< sc_lv<1> > tmp_57_124_reg_7518;
sc_signal< sc_logic > ap_CS_fsm_state120;
sc_signal< sc_lv<1> > tmp58_fu_6722_p2;
sc_signal< sc_lv<1> > tmp58_reg_7523;
sc_signal< sc_logic > ap_CS_fsm_state122;
sc_signal< sc_lv<1> > tmp_59_128_reg_7528;
sc_signal< sc_logic > ap_CS_fsm_state124;
sc_signal< sc_lv<1> > tmp_60_130_reg_7533;
sc_signal< sc_logic > ap_CS_fsm_state126;
sc_signal< sc_lv<1> > tmp_61_132_reg_7538;
sc_signal< sc_logic > ap_CS_fsm_state128;
sc_signal< sc_lv<1> > tmp1_fu_6762_p2;
sc_signal< sc_lv<1> > tmp1_reg_7543;
sc_signal< sc_logic > ap_CS_fsm_state130;
sc_signal< sc_lv<1> > tmp_63_136_reg_7548;
sc_signal< sc_logic > ap_CS_fsm_state132;
sc_signal< sc_lv<1> > tmp_64_138_reg_7553;
sc_signal< sc_logic > ap_CS_fsm_state134;
sc_signal< sc_lv<1> > tmp_65_140_reg_7558;
sc_signal< sc_logic > ap_CS_fsm_state136;
sc_signal< sc_lv<1> > tmp68_fu_6777_p2;
sc_signal< sc_lv<1> > tmp68_reg_7563;
sc_signal< sc_logic > ap_CS_fsm_state138;
sc_signal< sc_lv<1> > tmp_67_144_reg_7568;
sc_signal< sc_logic > ap_CS_fsm_state140;
sc_signal< sc_lv<1> > tmp_68_146_reg_7573;
sc_signal< sc_logic > ap_CS_fsm_state142;
sc_signal< sc_lv<1> > tmp_69_148_reg_7578;
sc_signal< sc_logic > ap_CS_fsm_state144;
sc_signal< sc_lv<1> > tmp67_fu_6798_p2;
sc_signal< sc_lv<1> > tmp67_reg_7583;
sc_signal< sc_logic > ap_CS_fsm_state146;
sc_signal< sc_lv<1> > tmp_71_152_reg_7588;
sc_signal< sc_logic > ap_CS_fsm_state148;
sc_signal< sc_lv<1> > tmp_72_154_reg_7593;
sc_signal< sc_logic > ap_CS_fsm_state150;
sc_signal< sc_lv<1> > tmp_73_156_reg_7598;
sc_signal< sc_logic > ap_CS_fsm_state152;
sc_signal< sc_lv<1> > tmp75_fu_6812_p2;
sc_signal< sc_lv<1> > tmp75_reg_7603;
sc_signal< sc_logic > ap_CS_fsm_state154;
sc_signal< sc_lv<1> > tmp_75_160_reg_7608;
sc_signal< sc_logic > ap_CS_fsm_state156;
sc_signal< sc_lv<1> > tmp_76_162_reg_7613;
sc_signal< sc_logic > ap_CS_fsm_state158;
sc_signal< sc_lv<1> > tmp_77_164_reg_7618;
sc_signal< sc_logic > ap_CS_fsm_state160;
sc_signal< sc_lv<1> > tmp66_fu_6838_p2;
sc_signal< sc_lv<1> > tmp66_reg_7623;
sc_signal< sc_logic > ap_CS_fsm_state162;
sc_signal< sc_lv<1> > tmp_79_168_reg_7628;
sc_signal< sc_logic > ap_CS_fsm_state164;
sc_signal< sc_lv<1> > tmp_80_170_reg_7633;
sc_signal< sc_logic > ap_CS_fsm_state166;
sc_signal< sc_lv<1> > tmp_81_172_reg_7638;
sc_signal< sc_logic > ap_CS_fsm_state168;
sc_signal< sc_lv<1> > tmp83_fu_6852_p2;
sc_signal< sc_lv<1> > tmp83_reg_7643;
sc_signal< sc_logic > ap_CS_fsm_state170;
sc_signal< sc_lv<1> > tmp_83_176_reg_7648;
sc_signal< sc_logic > ap_CS_fsm_state172;
sc_signal< sc_lv<1> > tmp_84_178_reg_7653;
sc_signal< sc_logic > ap_CS_fsm_state174;
sc_signal< sc_lv<1> > tmp_85_180_reg_7658;
sc_signal< sc_logic > ap_CS_fsm_state176;
sc_signal< sc_lv<1> > tmp82_fu_6873_p2;
sc_signal< sc_lv<1> > tmp82_reg_7663;
sc_signal< sc_logic > ap_CS_fsm_state178;
sc_signal< sc_lv<1> > tmp_87_184_reg_7668;
sc_signal< sc_logic > ap_CS_fsm_state180;
sc_signal< sc_lv<1> > tmp_88_186_reg_7673;
sc_signal< sc_logic > ap_CS_fsm_state182;
sc_signal< sc_lv<1> > tmp_89_188_reg_7678;
sc_signal< sc_logic > ap_CS_fsm_state184;
sc_signal< sc_lv<1> > tmp90_fu_6887_p2;
sc_signal< sc_lv<1> > tmp90_reg_7683;
sc_signal< sc_logic > ap_CS_fsm_state186;
sc_signal< sc_lv<1> > tmp_91_192_reg_7688;
sc_signal< sc_logic > ap_CS_fsm_state188;
sc_signal< sc_lv<1> > tmp_92_194_reg_7693;
sc_signal< sc_logic > ap_CS_fsm_state190;
sc_signal< sc_lv<1> > tmp_93_196_reg_7698;
sc_signal< sc_logic > ap_CS_fsm_state192;
sc_signal< sc_lv<1> > tmp81_fu_6913_p2;
sc_signal< sc_lv<1> > tmp81_reg_7703;
sc_signal< sc_logic > ap_CS_fsm_state194;
sc_signal< sc_lv<1> > tmp_95_200_reg_7708;
sc_signal< sc_logic > ap_CS_fsm_state196;
sc_signal< sc_lv<1> > tmp_96_202_reg_7713;
sc_signal< sc_logic > ap_CS_fsm_state198;
sc_signal< sc_lv<1> > tmp_97_204_reg_7718;
sc_signal< sc_logic > ap_CS_fsm_state200;
sc_signal< sc_lv<1> > tmp99_fu_6927_p2;
sc_signal< sc_lv<1> > tmp99_reg_7723;
sc_signal< sc_logic > ap_CS_fsm_state202;
sc_signal< sc_lv<1> > tmp_99_208_reg_7728;
sc_signal< sc_logic > ap_CS_fsm_state204;
sc_signal< sc_lv<1> > tmp_100_210_reg_7733;
sc_signal< sc_logic > ap_CS_fsm_state206;
sc_signal< sc_lv<1> > tmp_101_212_reg_7738;
sc_signal< sc_logic > ap_CS_fsm_state208;
sc_signal< sc_lv<1> > tmp98_fu_6948_p2;
sc_signal< sc_lv<1> > tmp98_reg_7743;
sc_signal< sc_logic > ap_CS_fsm_state210;
sc_signal< sc_lv<1> > tmp_103_216_reg_7748;
sc_signal< sc_logic > ap_CS_fsm_state212;
sc_signal< sc_lv<1> > tmp_104_218_reg_7753;
sc_signal< sc_logic > ap_CS_fsm_state214;
sc_signal< sc_lv<1> > tmp_105_220_reg_7758;
sc_signal< sc_logic > ap_CS_fsm_state216;
sc_signal< sc_lv<1> > tmp106_fu_6962_p2;
sc_signal< sc_lv<1> > tmp106_reg_7763;
sc_signal< sc_logic > ap_CS_fsm_state218;
sc_signal< sc_lv<1> > tmp_107_224_reg_7768;
sc_signal< sc_logic > ap_CS_fsm_state220;
sc_signal< sc_lv<1> > tmp_108_226_reg_7773;
sc_signal< sc_logic > ap_CS_fsm_state222;
sc_signal< sc_lv<1> > tmp_109_228_reg_7778;
sc_signal< sc_logic > ap_CS_fsm_state224;
sc_signal< sc_lv<1> > tmp97_fu_6988_p2;
sc_signal< sc_lv<1> > tmp97_reg_7783;
sc_signal< sc_logic > ap_CS_fsm_state226;
sc_signal< sc_lv<1> > tmp_111_232_reg_7788;
sc_signal< sc_logic > ap_CS_fsm_state228;
sc_signal< sc_lv<1> > tmp_112_234_reg_7793;
sc_signal< sc_logic > ap_CS_fsm_state230;
sc_signal< sc_lv<1> > tmp_113_236_reg_7798;
sc_signal< sc_logic > ap_CS_fsm_state232;
sc_signal< sc_lv<1> > tmp114_fu_7002_p2;
sc_signal< sc_lv<1> > tmp114_reg_7803;
sc_signal< sc_logic > ap_CS_fsm_state234;
sc_signal< sc_lv<1> > tmp_115_240_reg_7808;
sc_signal< sc_logic > ap_CS_fsm_state236;
sc_signal< sc_lv<1> > tmp_116_242_reg_7813;
sc_signal< sc_logic > ap_CS_fsm_state238;
sc_signal< sc_lv<1> > tmp_117_244_reg_7818;
sc_signal< sc_logic > ap_CS_fsm_state240;
sc_signal< sc_lv<1> > tmp113_fu_7023_p2;
sc_signal< sc_lv<1> > tmp113_reg_7823;
sc_signal< sc_logic > ap_CS_fsm_state242;
sc_signal< sc_lv<1> > tmp_119_248_reg_7828;
sc_signal< sc_logic > ap_CS_fsm_state244;
sc_signal< sc_lv<1> > tmp_120_250_reg_7833;
sc_signal< sc_logic > ap_CS_fsm_state246;
sc_signal< sc_lv<1> > tmp_121_252_reg_7838;
sc_signal< sc_logic > ap_CS_fsm_state248;
sc_signal< sc_lv<1> > tmp121_fu_7037_p2;
sc_signal< sc_lv<1> > tmp121_reg_7843;
sc_signal< sc_logic > ap_CS_fsm_state250;
sc_signal< sc_lv<1> > tmp_123_256_reg_7848;
sc_signal< sc_logic > ap_CS_fsm_state252;
sc_signal< sc_lv<1> > tmp_124_258_reg_7853;
sc_signal< sc_logic > ap_CS_fsm_state254;
sc_signal< sc_lv<1> > tmp_125_260_reg_7858;
sc_signal< sc_logic > ap_CS_fsm_state256;
sc_signal< sc_logic > ap_CS_fsm_state259;
sc_signal< sc_logic > ap_CS_fsm_state260;
sc_signal< sc_logic > ap_CS_fsm_state261;
sc_signal< sc_logic > ap_CS_fsm_state262;
sc_signal< sc_logic > ap_CS_fsm_state263;
sc_signal< sc_logic > ap_CS_fsm_state264;
sc_signal< sc_logic > ap_CS_fsm_state265;
sc_signal< sc_logic > ap_CS_fsm_state266;
sc_signal< sc_logic > ap_CS_fsm_state267;
sc_signal< sc_logic > ap_CS_fsm_state268;
sc_signal< sc_logic > ap_CS_fsm_state269;
sc_signal< sc_logic > ap_CS_fsm_state270;
sc_signal< sc_logic > ap_CS_fsm_state271;
sc_signal< sc_logic > ap_CS_fsm_state272;
sc_signal< sc_logic > ap_CS_fsm_state273;
sc_signal< sc_logic > ap_CS_fsm_state274;
sc_signal< sc_logic > ap_CS_fsm_state275;
sc_signal< sc_logic > ap_CS_fsm_state276;
sc_signal< sc_logic > ap_CS_fsm_state277;
sc_signal< sc_logic > ap_CS_fsm_state278;
sc_signal< sc_logic > ap_CS_fsm_state279;
sc_signal< sc_logic > ap_CS_fsm_state280;
sc_signal< sc_logic > ap_CS_fsm_state281;
sc_signal< sc_logic > ap_CS_fsm_state282;
sc_signal< sc_logic > ap_CS_fsm_state283;
sc_signal< sc_logic > ap_CS_fsm_state284;
sc_signal< sc_logic > ap_CS_fsm_state285;
sc_signal< sc_logic > ap_CS_fs
|
m_state286;
sc_signal< sc_logic > ap_CS_fsm_state287;
sc_signal< sc_logic > ap_CS_fsm_state288;
sc_signal< sc_logic > ap_CS_fsm_state289;
sc_signal< sc_logic > ap_CS_fsm_state290;
sc_signal< sc_logic > ap_CS_fsm_state291;
sc_signal< sc_logic > ap_CS_fsm_state292;
sc_signal< sc_logic > ap_CS_fsm_state293;
sc_signal< sc_logic > ap_CS_fsm_state294;
sc_signal< sc_logic > ap_CS_fsm_state295;
sc_signal< sc_logic > ap_CS_fsm_state296;
sc_signal< sc_logic > ap_CS_fsm_state297;
sc_signal< sc_logic > ap_CS_fsm_state298;
sc_signal< sc_logic > ap_CS_fsm_state299;
sc_signal< sc_logic > ap_CS_fsm_state300;
sc_signal< sc_logic > ap_CS_fsm_state301;
sc_signal< sc_logic > ap_CS_fsm_state302;
sc_signal< sc_logic > ap_CS_fsm_state303;
sc_signal< sc_logic > ap_CS_fsm_state304;
sc_signal< sc_logic > ap_CS_fsm_state305;
sc_signal< sc_logic > ap_CS_fsm_state306;
sc_signal< sc_logic > ap_CS_fsm_state307;
sc_signal< sc_logic > ap_CS_fsm_state308;
sc_signal< sc_logic > ap_CS_fsm_state309;
sc_signal< sc_logic > ap_CS_fsm_state310;
sc_signal< sc_logic > ap_CS_fsm_state311;
sc_signal< sc_logic > ap_CS_fsm_state312;
sc_signal< sc_logic > ap_CS_fsm_state313;
sc_signal< sc_logic > ap_CS_fsm_state314;
sc_signal< sc_logic > ap_CS_fsm_state315;
sc_signal< sc_logic > ap_CS_fsm_state316;
sc_signal< sc_logic > ap_CS_fsm_state317;
sc_signal< sc_logic > ap_CS_fsm_state318;
sc_signal< sc_logic > ap_CS_fsm_state319;
sc_signal< sc_logic > ap_CS_fsm_state320;
sc_signal< sc_logic > ap_CS_fsm_state321;
sc_signal< sc_logic > ap_CS_fsm_state322;
sc_signal< sc_logic > ap_CS_fsm_state323;
sc_signal< sc_logic > ap_CS_fsm_state324;
sc_signal< sc_logic > ap_CS_fsm_state325;
sc_signal< sc_logic > ap_CS_fsm_state326;
sc_signal< sc_logic > ap_CS_fsm_state327;
sc_signal< sc_logic > ap_CS_fsm_state328;
sc_signal< sc_logic > ap_CS_fsm_state329;
sc_signal< sc_logic > ap_CS_fsm_state330;
sc_signal< sc_logic > ap_CS_fsm_state331;
sc_signal< sc_logic > ap_CS_fsm_state332;
sc_signal< sc_logic > ap_CS_fsm_state333;
sc_signal< sc_logic > ap_CS_fsm_state334;
sc_signal< sc_logic > ap_CS_fsm_state335;
sc_signal< sc_logic > ap_CS_fsm_state336;
sc_signal< sc_logic > ap_CS_fsm_state337;
sc_signal< sc_logic > ap_CS_fsm_state338;
sc_signal< sc_logic > ap_CS_fsm_state339;
sc_signal< sc_logic > ap_CS_fsm_state340;
sc_signal< sc_logic > ap_CS_fsm_state341;
sc_signal< sc_logic > ap_CS_fsm_state342;
sc_signal< sc_logic > ap_CS_fsm_state343;
sc_signal< sc_logic > ap_CS_fsm_state344;
sc_signal< sc_logic > ap_CS_fsm_state345;
sc_signal< sc_logic > ap_CS_fsm_state346;
sc_signal< sc_logic > ap_CS_fsm_state347;
sc_signal< sc_logic > ap_CS_fsm_state348;
sc_signal< sc_logic > ap_CS_fsm_state349;
sc_signal< sc_logic > ap_CS_fsm_state350;
sc_signal< sc_logic > ap_CS_fsm_state351;
sc_signal< sc_logic > ap_CS_fsm_state352;
sc_signal< sc_logic > ap_CS_fsm_state353;
sc_signal< sc_logic > ap_CS_fsm_state354;
sc_signal< sc_logic > ap_CS_fsm_state355;
sc_signal< sc_logic > ap_CS_fsm_state356;
sc_signal< sc_logic > ap_CS_fsm_state357;
sc_signal< sc_logic > ap_CS_fsm_state358;
sc_signal< sc_logic > ap_CS_fsm_state359;
sc_signal< sc_logic > ap_CS_fsm_state360;
sc_signal< sc_logic > ap_CS_fsm_state361;
sc_signal< sc_logic > ap_CS_fsm_state362;
sc_signal< sc_logic > ap_CS_fsm_state363;
sc_signal< sc_logic > ap_CS_fsm_state364;
sc_signal< sc_logic > ap_CS_fsm_state365;
sc_signal< sc_logic > ap_CS_fsm_state366;
sc_signal< sc_logic > ap_CS_fsm_state367;
sc_signal< sc_logic > ap_CS_fsm_state368;
sc_signal< sc_logic > ap_CS_fsm_state369;
sc_signal< sc_logic > ap_CS_fsm_state370;
sc_signal< sc_logic > ap_CS_fsm_state371;
sc_signal< sc_logic > ap_CS_fsm_state372;
sc_signal< sc_logic > ap_CS_fsm_state373;
sc_signal< sc_logic > ap_CS_fsm_state374;
sc_signal< sc_logic > ap_CS_fsm_state375;
sc_signal< sc_logic > ap_CS_fsm_state376;
sc_signal< sc_logic > ap_CS_fsm_state377;
sc_signal< sc_logic > ap_CS_fsm_state378;
sc_signal< sc_logic > ap_CS_fsm_state379;
sc_signal< sc_logic > ap_CS_fsm_state380;
sc_signal< sc_logic > ap_CS_fsm_state381;
sc_signal< sc_logic > ap_CS_fsm_state382;
sc_signal< sc_logic > ap_CS_fsm_state383;
sc_signal< sc_logic > ap_CS_fsm_state384;
sc_signal< sc_logic > ap_CS_fsm_state385;
sc_signal< sc_logic > ap_CS_fsm_state386;
sc_signal< sc_logic > ap_CS_fsm_state387;
sc_signal< sc_logic > ap_CS_fsm_state388;
sc_signal< sc_logic > ap_CS_fsm_state389;
sc_signal< sc_logic > ap_CS_fsm_state390;
sc_signal< sc_logic > ap_CS_fsm_state391;
sc_signal< sc_logic > ap_CS_fsm_state392;
sc_signal< sc_logic > ap_CS_fsm_state393;
sc_signal< sc_logic > ap_CS_fsm_state394;
sc_signal< sc_logic > ap_CS_fsm_state395;
sc_signal< sc_logic > ap_CS_fsm_state396;
sc_signal< sc_logic > ap_CS_fsm_state397;
sc_signal< sc_logic > ap_CS_fsm_state398;
sc_signal< sc_logic > ap_CS_fsm_state399;
sc_signal< sc_logic > ap_CS_fsm_state400;
sc_signal< sc_logic > ap_CS_fsm_state401;
sc_signal< sc_logic > ap_CS_fsm_state402;
sc_signal< sc_logic > ap_CS_fsm_state403;
sc_signal< sc_logic > ap_CS_fsm_state404;
sc_signal< sc_logic > ap_CS_fsm_state405;
sc_signal< sc_logic > ap_CS_fsm_state406;
sc_signal< sc_logic > ap_CS_fsm_state407;
sc_signal< sc_logic > ap_CS_fsm_state408;
sc_signal< sc_logic > ap_CS_fsm_state409;
sc_signal< sc_logic > ap_CS_fsm_state410;
sc_signal< sc_logic > ap_CS_fsm_state411;
sc_signal< sc_logic > ap_CS_fsm_state412;
sc_signal< sc_logic > ap_CS_fsm_state413;
sc_signal< sc_logic > ap_CS_fsm_state414;
sc_signal< sc_logic > ap_CS_fsm_state415;
sc_signal< sc_logic > ap_CS_fsm_state416;
sc_signal< sc_logic > ap_CS_fsm_state417;
sc_signal< sc_logic > ap_CS_fsm_state418;
sc_signal< sc_logic > ap_CS_fsm_state419;
sc_signal< sc_logic > ap_CS_fsm_state420;
sc_signal< sc_logic > ap_CS_fsm_state421;
sc_signal< sc_logic > ap_CS_fsm_state422;
sc_signal< sc_logic > ap_CS_fsm_state423;
sc_signal< sc_logic > ap_CS_fsm_state424;
sc_signal< sc_logic > ap_CS_fsm_state425;
sc_signal< sc_logic > ap_CS_fsm_state426;
sc_signal< sc_logic > ap_CS_fsm_state427;
sc_signal< sc_logic > ap_CS_fsm_state428;
sc_signal< sc_logic > ap_CS_fsm_state429;
sc_signal< sc_logic > ap_CS_fsm_state430;
sc_signal< sc_logic > ap_CS_fsm_state431;
sc_signal< sc_logic > ap_CS_fsm_state432;
sc_signal< sc_logic > ap_CS_fsm_state433;
sc_signal< sc_logic > ap_CS_fsm_state434;
sc_signal< sc_logic > ap_CS_fsm_state435;
sc_signal< sc_logic > ap_CS_fsm_state436;
sc_signal< sc_logic > ap_CS_fsm_state437;
sc_signal< sc_logic > ap_CS_fsm_state438;
sc_signal< sc_logic > ap_CS_fsm_state439;
sc_signal< sc_logic > ap_CS_fsm_state440;
sc_signal< sc_logic > ap_CS_fsm_state441;
sc_signal< sc_logic > ap_CS_fsm_state442;
sc_signal< sc_logic > ap_CS_fsm_state443;
sc_signal< sc_logic > ap_CS_fsm_state444;
sc_signal< sc_logic > ap_CS_fsm_state445;
sc_signal< sc_logic > ap_CS_fsm_state446;
sc_signal< sc_logic > ap_CS_fsm_state447;
sc_signal< sc_logic > ap_CS_fsm_state448;
sc_signal< sc_logic > ap_CS_fsm_state449;
sc_signal< sc_logic > ap_CS_fsm_state450;
sc_signal< sc_logic > ap_CS_fsm_state451;
sc_signal< sc_logic > ap_CS_fsm_state452;
sc_signal< sc_logic > ap_CS_fsm_state453;
sc_signal< sc_logic > ap_CS_fsm_state454;
sc_signal< sc_logic > ap_CS_fsm_state455;
sc_signal< sc_logic > ap_CS_fsm_state456;
sc_signal< sc_logic > ap_CS_fsm_state457;
sc_signal< sc_logic > ap_CS_fsm_state458;
sc_signal< sc_logic > ap_CS_fsm_state459;
sc_signal< sc_logic > ap_CS_fsm_state460;
sc_signal< sc_logic > ap_CS_fsm_state461;
sc_signal< sc_logic > ap_CS_fsm_state462;
sc_signal< sc_logic > ap_CS_fsm_state463;
sc_signal< sc_logic > ap_CS_fsm_state464;
sc_signal< sc_logic > ap_CS_fsm_state465;
sc_signal< sc_logic > ap_CS_fsm_state466;
sc_signal< sc_logic > ap_CS_fsm_state467;
sc_signal< sc_logic > ap_CS_fsm_state468;
sc_signal< sc_logic > ap_CS_fsm_state469;
sc_signal< sc_logic > ap_CS_fsm_state470;
sc_signal< sc_logic > ap_CS_fsm_state471;
sc_signal< sc_logic > ap_CS_fsm_state472;
sc_signal< sc_logic > ap_CS_fsm_state473;
sc_signal< sc_logic > ap_CS_fsm_state474;
sc_signal< sc_logic > ap_CS_fsm_state475;
sc_signal< sc_logic > ap_CS_fsm_state476;
sc_signal< sc_logic > ap_CS_fsm_state477;
sc_signal< sc_logic > ap_CS_fsm_state478;
sc_signal< sc_logic > ap_CS_fsm_state479;
sc_signal< sc_logic > ap_CS_fsm_state480;
sc_signal< sc_logic > ap_CS_fsm_state481;
sc_signal< sc_logic > ap_CS_fsm_state482;
sc_signal< sc_logic > ap_CS_fsm_state483;
sc_signal< sc_logic > ap_CS_fsm_state484;
sc_signal< sc_logic > ap_CS_fsm_state485;
sc_signal< sc_logic > ap_CS_fsm_state486;
sc_signal< sc_logic > ap_CS_fsm_state487;
sc_signal< sc_logic > ap_CS_fsm_state488;
sc_signal< sc_logic > ap_CS_fsm_state489;
sc_signal< sc_logic > ap_CS_fsm_state490;
sc_signal< sc_logic > ap_CS_fsm_state491;
sc_signal< sc_logic > ap_CS_fsm_state492;
sc_signal< sc_logic > ap_CS_fsm_state493;
sc_signal< sc_logic > ap_CS_fsm_state494;
sc_signal< sc_logic > ap_CS_fsm_state495;
sc_signal< sc_logic > ap_CS_fsm_state496;
sc_signal< sc_logic > ap_CS_fsm_state497;
sc_signal< sc_logic > ap_CS_fsm_state498;
sc_signal< sc_logic > ap_CS_fsm_state499;
sc_signal< sc_logic > ap_CS_fsm_state500;
sc_signal< sc_logic > ap_CS_fsm_state501;
sc_signal< sc_logic > ap_CS_fsm_state502;
sc_signal< sc_logic > ap_CS_fsm_state503;
sc_signal< sc_logic > ap_CS_fsm_state504;
sc_signal< sc_logic > ap_CS_fsm_state505;
sc_signal< sc_logic > ap_CS_fsm_state506;
sc_signal< sc_logic > ap_CS_fsm_state507;
sc_signal< sc_logic > ap_CS_fsm_state508;
sc_signal< sc_logic > ap_CS_fsm_state509;
sc_signal< sc_logic > ap_CS_fsm_state510;
sc_signal< sc_logic > ap_CS_fsm_state511;
sc_signal< sc_logic > ap_CS_fsm_state512;
sc_signal< sc_logic > ap_CS_fsm_state513;
sc_signal< sc_logic > ap_CS_fsm_state514;
sc_signal< sc_logic > ap_CS_fsm_state515;
sc_signal< sc_logic > ap_CS_fsm_state516;
sc_signal< sc_logic > ap_CS_fsm_state517;
sc_signal< sc_logic > ap_CS_fsm_state518;
sc_signal< sc_logic > ap_CS_fsm_state519;
sc_signal< sc_logic > ap_CS_fsm_state520;
sc_signal< sc_logic > ap_CS_fsm_state521;
sc_signal< sc_logic > ap_CS_fsm_state522;
sc_signal< sc_logic > ap_CS_fsm_state523;
sc_signal< sc_logic > ap_CS_fsm_state524;
sc_signal< sc_logic > ap_CS_fsm_state525;
sc_signal< sc_logic > ap_CS_fsm_state526;
sc_signal< sc_logic > ap_CS_fsm_state527;
sc_signal< sc_logic > ap_CS_fsm_state528;
sc_signal< sc_logic > ap_CS_fsm_state529;
sc_signal< sc_logic > ap_CS_fsm_state530;
sc_signal< sc_logic > ap_CS_fsm_state531;
sc_signal< sc_logic > ap_CS_fsm_state532;
sc_signal< sc_logic > ap_CS_fsm_state533;
sc_signal< sc_logic > ap_CS_fsm_state534;
sc_signal< sc_logic > ap_CS_fsm_state535;
sc_signal< sc_logic > ap_CS_fsm_state536;
sc_signal< sc_logic > ap_CS_fsm_state537;
sc_signal< sc_logic > ap_CS_fsm_state538;
sc_signal< sc_logic > ap_CS_fsm_state539;
sc_signal< sc_logic > ap_CS_fsm_state540;
sc_signal< sc_logic > ap_CS_fsm_state541;
sc_signal< sc_logic > ap_CS_fsm_state542;
sc_signal< sc_logic > ap_CS_fsm_state543;
sc_signal< sc_logic > ap_CS_fsm_state544;
sc_signal< sc_logic > ap_CS_fsm_state545;
sc_signal< sc_logic > ap_CS_fsm_state546;
sc_signal< sc_logic > ap_CS_fsm_state547;
sc_signal< sc_logic > ap_CS_fsm_state548;
sc_signal< sc_logic > ap_CS_fsm_state549;
sc_signal< sc_logic > ap_CS_fsm_state550;
sc_signal< sc_logic > ap_CS_fsm_state551;
sc_signal< sc_logic > ap_CS_fsm_state552;
sc_signal< sc_logic > ap_CS_fsm_state553;
sc_signal< sc_logic > ap_CS_fsm_state554;
sc_signal< sc_logic > ap_CS_fsm_state555;
sc_signal< sc_logic > ap_CS_fsm_state556;
sc_signal< sc_logic > ap_CS_fsm_state557;
sc_signal< sc_lv<7> > i_1_fu_7100_p2;
sc_signal< sc_lv<7> > i_1_reg_9361;
sc_signal< sc_logic > ap_CS_fsm_state559;
sc_signal< sc_lv<1> > exitcond_i1_fu_7094_p2;
sc_signal< sc_lv<16> > sum_i1_fu_7115_p2;
sc_signal< sc_lv<16> > sum_i1_reg_9371;
sc_signal< sc_lv<32> > tmp_7_fu_7120_p2;
sc_signal< sc_lv<7> > i_fu_7141_p2;
sc_signal< sc_lv<7> > i_reg_9384;
sc_signal< sc_logic > ap_CS_fsm_state564;
sc_signal< sc_lv<1> > exitcond_i_fu_7135_p2;
sc_signal< sc_lv<15> > sum_i_fu_7156_p2;
sc_signal< sc_lv<15> > sum_i_reg_9394;
sc_signal< sc_lv<32> > tmp_4_fu_7161_p2;
sc_signal< sc_lv<9> > results_address0;
sc_signal< sc_logic > results_ce0;
sc_signal< sc_logic > results_we0;
sc_signal< sc_lv<1> > results_d0;
sc_signal< sc_lv<1> > results_q0;
sc_signal< sc_logic > grp_compare_fu_6234_ap_start;
sc_signal< sc_logic > grp_compare_fu_6234_ap_idle;
sc_signal< sc_logic > grp_compare_fu_6234_ap_ready;
sc_signal< sc_lv<8> > grp_compare_fu_6234_contacts_index;
sc_signal< sc_lv<13> > grp_compare_fu_6234_contacts_address0;
sc_signal< sc_logic > grp_compare_fu_6234_contacts_ce0;
sc_signal< sc_lv<13> > grp_compare_fu_6234_contacts_address1;
sc_signal< sc_logic > grp_compare_fu_6234_contacts_ce1;
sc_signal< sc_lv<15> > grp_compare_fu_6234_database_address0;
sc_signal< sc_logic > grp_compare_fu_6234_database_ce0;
sc_signal< sc_lv<15> > grp_compare_fu_6234_database_address1;
sc_signal< sc_logic > grp_compare_fu_6234_database_ce1;
sc_signal< sc_lv<31> > database_index_reg_6176;
sc_signal< sc_logic > ap_CS_fsm_state258;
sc_signal< sc_lv<7> > i_i1_reg_6188;
sc_signal< sc_logic > ap_CS_fsm_state560;
sc_signal< sc_lv<32> > storemerge_reg_6199;
sc_signal< sc_logic > ap_CS_fsm_state561;
sc_signal< sc_lv<7> > i_i_reg_6211;
sc_signal< sc_logic > ap_CS_fsm_state565;
sc_signal< sc_lv<32> > storemerge1_reg_6222;
sc_signal< sc_logic > ap_CS_fsm_state566;
sc_signal< sc_logic > ap_reg_grp_compare_fu_6234_ap_start;
sc_signal< sc_logic > ap_CS_fsm_state5;
sc_signal< sc_logic > ap_CS_fsm_state7;
sc_signal< sc_logic > ap_CS_fsm_state9;
sc_signal< sc_logic > ap_CS_fsm_state11;
sc_signal< sc_logic > ap_CS_fsm_state13;
sc_signal< sc_logic > ap_CS_fsm_state15;
sc_signal< sc_logic > ap_CS_fsm_state17;
sc_signal< sc_logic > ap_CS_fsm_state19;
sc_signal< sc_logic > ap_CS_fsm_state21;
sc_signal< sc_logic > ap_CS_fsm_state23;
sc_signal< sc_logic > ap_CS_fsm_state25;
sc_signal< sc_logic > ap_CS_fsm_state27;
sc_signal< sc_logic > ap_CS_fsm_state29;
sc_signal< sc_logic > ap_CS_fsm_state31;
sc_signal< sc_logic > ap_CS_fsm_state33;
sc_signal< sc_logic > ap_CS_fsm_state35;
sc_signal< sc_logic > ap_CS_fsm_state37;
sc_signal< sc_logic > ap_CS_fsm_state39;
sc_signal< sc_logic > ap_CS_fsm_state41;
sc_signal< sc_logic > ap_CS_fsm_state43;
sc_signal< sc_logic > ap_CS_fsm_state45;
sc_signal< sc_logic > ap_CS_fsm_state47;
sc_signal< sc_logic > ap_CS_fsm_state49;
sc_signal< sc_logic > ap_CS_fsm_state51;
sc_signal< sc_logic > ap_CS_fsm_state53;
sc_signal< sc_logic > ap_CS_fsm_state55;
sc_signal< sc_logic > ap_CS_fsm_state57;
sc_signal< sc_logic > ap_CS_fsm_state59;
sc_signal< sc_logic > ap_CS_fsm_state61;
sc_signal< sc_logic > ap_CS_fsm_state63;
sc_signal< sc_logic > ap_CS_fsm_state65;
sc_signal< sc_logic > ap_CS_fsm_state67;
sc_signal< sc_logic > ap_CS_fsm_state69;
sc_signal< sc_logic > ap_CS_fsm_state71;
sc_signal< sc_logic > ap_CS_fsm_state73;
sc_signal< sc_logic > ap_CS_fsm_state75;
sc_signal< sc_logic > ap_CS_fsm_state77;
sc_signal< sc_logic > ap_CS_fsm_state79;
sc_signal< sc_logic > ap_CS_fsm_state81;
sc_signal< sc_logic > ap_CS_fsm_state83;
sc_signal< sc_logic > ap_CS_fsm_state85;
sc_signal< sc_logic > ap_CS_fsm_state87;
sc_signal< sc_logic > ap_CS_fsm_state89;
sc_signal< sc_logic > ap_CS_fsm_state91;
sc_signal< sc_logic > ap_CS_fsm_state93;
sc_signal< sc_logic > ap_CS_fsm_state95;
sc_signal< sc_logic > ap_CS_fsm_state97;
sc_signal< sc_logic > ap_CS_fsm_state99;
sc_signal< sc_logic > ap_CS_fsm_state101;
sc_signal< sc_logic > ap_CS_fsm_state103;
sc_signal< sc_logic > ap_CS_fsm_state105;
sc_signal< sc_logic > ap_CS_fsm_state107;
sc_signal< sc_logic > ap_CS_fsm_state109;
sc_signal< sc_logic > ap_CS_fsm_state111;
sc_signal< sc_logic > ap_CS_fsm_state113;
sc_signal< sc_logic > ap_CS_fsm_state115;
sc_signal< sc_logic > ap_CS_fsm_state117;
sc_signal< sc_logic > ap_CS_fsm_state119;
sc_signal< sc_logic > ap_CS_fsm_state121;
sc_signal< sc_logic > ap_CS_fsm_state123;
sc_signal< sc_logic > ap_CS_fsm_state125;
sc_signal< sc_logic > ap_CS_fsm_state127;
sc_signal< sc_logic > ap_CS_fsm_state129;
sc_signal< sc_logic > ap_CS_fsm_state131;
sc_signal< sc_logic > ap_CS_fsm_state133;
sc_signal< sc_logic > ap_CS_fsm_state135;
sc_signal< sc_logic > ap_CS_fsm_state137;
sc_signal< sc_logic > ap_CS_fsm_state139;
sc_signal< sc_logic > ap_CS_fsm_state141;
sc_signal< sc_logic > ap_CS_fsm_state143;
sc_signal< sc_logic > ap_CS_fsm_state145;
sc_signal< sc_logic > ap_CS_fsm_state147;
sc_signal< sc_logic > ap_CS_fsm_state149;
sc_signal< sc_logic > ap_CS_fsm_state151;
sc_signal< sc_logic > ap_CS_fsm_state153;
sc_signal< sc_logic > ap_CS_fsm_state155;
sc_signal< sc_logic > ap_CS_fsm_state157;
sc_signal< sc_logic > ap_CS_fsm_state159;
sc_signal< sc_logic > ap_CS_fsm_state161;
sc_signal< sc_logic > ap_CS_fsm_state163;
sc_signal< sc_logic > ap_CS_fsm_state165;
sc_signal< sc_logic > ap_CS_fsm_state167;
sc_signal< sc_logic > ap_CS_fsm_state169;
sc_signal< sc_logic > ap_CS_fsm_state171;
sc_signal< sc_logic > ap_CS_fsm_state173;
sc_signal< sc_logic > ap_CS_fsm_state175;
sc_signal< sc_logic > ap_CS_fsm_state177;
sc_signal< sc_logic > ap_CS_fsm_state179;
sc_signal< sc_logic > ap_CS_fsm_state181;
sc_signal< sc_logic > ap_CS_fsm_state183;
sc_signal< sc_logic > ap_CS_fsm_state185;
sc_signal< sc_logic > ap_CS_fsm_state187;
sc_signal< sc_logic > ap_CS_fsm_state189;
sc_signal< sc_logic > ap_CS_fsm_state191;
sc_signal< sc_logic > ap_CS_fsm_state193;
sc_signal< sc_logic > ap_CS_fsm_state195;
sc_signal< sc_logic > ap_CS_fsm_state197;
sc_signal< sc_logic > ap_CS_fsm_state199;
sc_signal< sc_logic > ap_CS_fsm_state201;
sc_signal< sc_logic > ap_CS_fsm_state203;
sc_signal< sc_logic > ap_CS_fsm_state205;
sc_signal< sc_logic > ap_CS_fsm_state207;
sc_signal< sc_logic > ap_CS_fsm_state209;
sc_signal< sc_logic > ap_CS_fsm_state211;
sc_signal< sc_logic > ap_CS_fsm_state213;
sc_signal< sc_logic > ap_CS_fsm_state215;
sc_signal< sc_logic > ap_CS_fsm_state217;
sc_signal< sc_logic > ap_CS_fsm_state219;
sc_signal< sc_logic > ap_CS_fsm_state221;
sc_signal< sc_logic > ap_CS_fsm_state223;
sc_signal< sc_logic > ap_CS_fsm_state225;
sc_signal< sc_logic > ap_CS_fsm_state227;
sc_signal< sc_logic > ap_CS_fsm_state229;
sc_signal< sc_logic > ap_CS_fsm_state231;
sc_signal< sc_logic > ap_CS_fsm_state233;
sc_signal< sc_logic > ap_CS_fsm_state235;
sc_signal< sc_logic > ap_CS_fsm_state237;
sc_signal< sc_logic > ap_CS_fsm_state239;
sc_signal< sc_logic > ap_CS_fsm_state241;
sc_signal< sc_logic >
|
ap_CS_fsm_state243;
sc_signal< sc_logic > ap_CS_fsm_state245;
sc_signal< sc_logic > ap_CS_fsm_state247;
sc_signal< sc_logic > ap_CS_fsm_state249;
sc_signal< sc_logic > ap_CS_fsm_state251;
sc_signal< sc_logic > ap_CS_fsm_state253;
sc_signal< sc_logic > ap_CS_fsm_state255;
sc_signal< sc_logic > ap_CS_fsm_state257;
sc_signal< sc_lv<64> > tmp_9_264_fu_7089_p1;
sc_signal< sc_logic > ap_CS_fsm_state558;
sc_signal< sc_lv<64> > tmp_i1_fu_7106_p1;
sc_signal< sc_lv<64> > sum_i1_cast_fu_7131_p1;
sc_signal< sc_lv<64> > tmp_i_fu_7147_p1;
sc_signal< sc_lv<64> > sum_i_cast_fu_7172_p1;
sc_signal< sc_logic > ap_CS_fsm_state567;
sc_signal< sc_logic > ap_CS_fsm_state562;
sc_signal< bool > ap_block_state558;
sc_signal< sc_lv<10> > tmp_3_fu_6401_p1;
sc_signal< sc_lv<25> > tmp_fu_6412_p4;
sc_signal< sc_lv<9> > tmp_2_fu_6427_p1;
sc_signal< sc_lv<32> > database_index_cast_fu_6438_p1;
sc_signal< sc_lv<1> > tmp7_fu_6457_p2;
sc_signal< sc_lv<1> > tmp6_fu_6453_p2;
sc_signal< sc_lv<1> > tmp10_fu_6472_p2;
sc_signal< sc_lv<1> > tmp9_fu_6468_p2;
sc_signal< sc_lv<1> > tmp8_fu_6477_p2;
sc_signal< sc_lv<1> > tmp14_fu_6492_p2;
sc_signal< sc_lv<1> > tmp13_fu_6488_p2;
sc_signal< sc_lv<1> > tmp17_fu_6507_p2;
sc_signal< sc_lv<1> > tmp16_fu_6503_p2;
sc_signal< sc_lv<1> > tmp15_fu_6512_p2;
sc_signal< sc_lv<1> > tmp11_fu_6518_p2;
sc_signal< sc_lv<1> > tmp22_fu_6532_p2;
sc_signal< sc_lv<1> > tmp21_fu_6528_p2;
sc_signal< sc_lv<1> > tmp25_fu_6547_p2;
sc_signal< sc_lv<1> > tmp24_fu_6543_p2;
sc_signal< sc_lv<1> > tmp23_fu_6552_p2;
sc_signal< sc_lv<1> > tmp29_fu_6567_p2;
sc_signal< sc_lv<1> > tmp28_fu_6563_p2;
sc_signal< sc_lv<1> > tmp32_fu_6582_p2;
sc_signal< sc_lv<1> > tmp31_fu_6578_p2;
sc_signal< sc_lv<1> > tmp30_fu_6587_p2;
sc_signal< sc_lv<1> > tmp26_fu_6593_p2;
sc_signal< sc_lv<1> > tmp38_fu_6607_p2;
sc_signal< sc_lv<1> > tmp37_fu_6603_p2;
sc_signal< sc_lv<1> > tmp41_fu_6622_p2;
sc_signal< sc_lv<1> > tmp40_fu_6618_p2;
sc_signal< sc_lv<1> > tmp39_fu_6627_p2;
sc_signal< sc_lv<1> > tmp45_fu_6642_p2;
sc_signal< sc_lv<1> > tmp44_fu_6638_p2;
sc_signal< sc_lv<1> > tmp48_fu_6657_p2;
sc_signal< sc_lv<1> > tmp47_fu_6653_p2;
sc_signal< sc_lv<1> > tmp46_fu_6662_p2;
sc_signal< sc_lv<1> > tmp42_fu_6668_p2;
sc_signal< sc_lv<1> > tmp53_fu_6682_p2;
sc_signal< sc_lv<1> > tmp52_fu_6678_p2;
sc_signal< sc_lv<1> > tmp56_fu_6697_p2;
sc_signal< sc_lv<1> > tmp55_fu_6693_p2;
sc_signal< sc_lv<1> > tmp54_fu_6702_p2;
sc_signal< sc_lv<1> > tmp60_fu_6717_p2;
sc_signal< sc_lv<1> > tmp59_fu_6713_p2;
sc_signal< sc_lv<1> > tmp63_fu_6736_p2;
sc_signal< sc_lv<1> > tmp62_fu_6732_p2;
sc_signal< sc_lv<1> > tmp61_fu_6741_p2;
sc_signal< sc_lv<1> > tmp57_fu_6747_p2;
sc_signal< sc_lv<1> > tmp49_fu_6752_p2;
sc_signal< sc_lv<1> > tmp33_fu_6757_p2;
sc_signal< sc_lv<1> > tmp2_fu_6728_p2;
sc_signal< sc_lv<1> > tmp70_fu_6772_p2;
sc_signal< sc_lv<1> > tmp69_fu_6768_p2;
sc_signal< sc_lv<1> > tmp73_fu_6787_p2;
sc_signal< sc_lv<1> > tmp72_fu_6783_p2;
sc_signal< sc_lv<1> > tmp71_fu_6792_p2;
sc_signal< sc_lv<1> > tmp77_fu_6807_p2;
sc_signal< sc_lv<1> > tmp76_fu_6803_p2;
sc_signal< sc_lv<1> > tmp80_fu_6822_p2;
sc_signal< sc_lv<1> > tmp79_fu_6818_p2;
sc_signal< sc_lv<1> > tmp78_fu_6827_p2;
sc_signal< sc_lv<1> > tmp74_fu_6833_p2;
sc_signal< sc_lv<1> > tmp85_fu_6847_p2;
sc_signal< sc_lv<1> > tmp84_fu_6843_p2;
sc_signal< sc_lv<1> > tmp88_fu_6862_p2;
sc_signal< sc_lv<1> > tmp87_fu_6858_p2;
sc_signal< sc_lv<1> > tmp86_fu_6867_p2;
sc_signal< sc_lv<1> > tmp92_fu_6882_p2;
sc_signal< sc_lv<1> > tmp91_fu_6878_p2;
sc_signal< sc_lv<1> > tmp95_fu_6897_p2;
sc_signal< sc_lv<1> > tmp94_fu_6893_p2;
sc_signal< sc_lv<1> > tmp93_fu_6902_p2;
sc_signal< sc_lv<1> > tmp89_fu_6908_p2;
sc_signal< sc_lv<1> > tmp101_fu_6922_p2;
sc_signal< sc_lv<1> > tmp100_fu_6918_p2;
sc_signal< sc_lv<1> > tmp104_fu_6937_p2;
sc_signal< sc_lv<1> > tmp103_fu_6933_p2;
sc_signal< sc_lv<1> > tmp102_fu_6942_p2;
sc_signal< sc_lv<1> > tmp108_fu_6957_p2;
sc_signal< sc_lv<1> > tmp107_fu_6953_p2;
sc_signal< sc_lv<1> > tmp111_fu_6972_p2;
sc_signal< sc_lv<1> > tmp110_fu_6968_p2;
sc_signal< sc_lv<1> > tmp109_fu_6977_p2;
sc_signal< sc_lv<1> > tmp105_fu_6983_p2;
sc_signal< sc_lv<1> > tmp116_fu_6997_p2;
sc_signal< sc_lv<1> > tmp115_fu_6993_p2;
sc_signal< sc_lv<1> > tmp119_fu_7012_p2;
sc_signal< sc_lv<1> > tmp118_fu_7008_p2;
sc_signal< sc_lv<1> > tmp117_fu_7017_p2;
sc_signal< sc_lv<1> > tmp123_fu_7032_p2;
sc_signal< sc_lv<1> > tmp122_fu_7028_p2;
sc_signal< sc_lv<1> > tmp126_fu_7051_p2;
sc_signal< sc_lv<1> > tmp125_fu_7047_p2;
sc_signal< sc_lv<1> > tmp124_fu_7056_p2;
sc_signal< sc_lv<1> > tmp120_fu_7062_p2;
sc_signal< sc_lv<1> > tmp112_fu_7067_p2;
sc_signal< sc_lv<1> > tmp96_fu_7072_p2;
sc_signal< sc_lv<1> > tmp65_fu_7043_p2;
sc_signal< sc_lv<1> > tmp64_fu_7077_p2;
sc_signal< sc_lv<16> > tmp_i1_cast_fu_7111_p1;
sc_signal< sc_lv<15> > tmp_i_cast_fu_7152_p1;
sc_signal< sc_lv<568> > ap_NS_fsm;
static const sc_logic ap_const_logic_1;
static const sc_logic ap_const_logic_0;
static const sc_lv<568> ap_ST_fsm_state1;
static const sc_lv<568> ap_ST_fsm_state2;
static const sc_lv<568> ap_ST_fsm_state3;
static const sc_lv<568> ap_ST_fsm_state4;
static const sc_lv<568> ap_ST_fsm_state5;
static const sc_lv<568> ap_ST_fsm_state6;
static const sc_lv<568> ap_ST_fsm_state7;
static const sc_lv<568> ap_ST_fsm_state8;
static const sc_lv<568> ap_ST_fsm_state9;
static const sc_lv<568> ap_ST_fsm_state10;
static const sc_lv<568> ap_ST_fsm_state11;
static const sc_lv<568> ap_ST_fsm_state12;
static const sc_lv<568> ap_ST_fsm_state13;
static const sc_lv<568> ap_ST_fsm_state14;
static const sc_lv<568> ap_ST_fsm_state15;
static const sc_lv<568> ap_ST_fsm_state16;
static const sc_lv<568> ap_ST_fsm_state17;
static const sc_lv<568> ap_ST_fsm_state18;
static const sc_lv<568> ap_ST_fsm_state19;
static const sc_lv<568> ap_ST_fsm_state20;
static const sc_lv<568> ap_ST_fsm_state21;
static const sc_lv<568> ap_ST_fsm_state22;
static const sc_lv<568> ap_ST_fsm_state23;
static const sc_lv<568> ap_ST_fsm_state24;
static const sc_lv<568> ap_ST_fsm_state25;
static const sc_lv<568> ap_ST_fsm_state26;
static const sc_lv<568> ap_ST_fsm_state27;
static const sc_lv<568> ap_ST_fsm_state28;
static const sc_lv<568> ap_ST_fsm_state29;
static const sc_lv<568> ap_ST_fsm_state30;
static const sc_lv<568> ap_ST_fsm_state31;
static const sc_lv<568> ap_ST_fsm_state32;
static const sc_lv<568> ap_ST_fsm_state33;
static const sc_lv<568> ap_ST_fsm_state34;
static const sc_lv<568> ap_ST_fsm_state35;
static const sc_lv<568> ap_ST_fsm_state36;
static const sc_lv<568> ap_ST_fsm_state37;
static const sc_lv<568> ap_ST_fsm_state38;
static const sc_lv<568> ap_ST_fsm_state39;
static const sc_lv<568> ap_ST_fsm_state40;
static const sc_lv<568> ap_ST_fsm_state41;
static const sc_lv<568> ap_ST_fsm_state42;
static const sc_lv<568> ap_ST_fsm_state43;
static const sc_lv<568> ap_ST_fsm_state44;
static const sc_lv<568> ap_ST_fsm_state45;
static const sc_lv<568> ap_ST_fsm_state46;
static const sc_lv<568> ap_ST_fsm_state47;
static const sc_lv<568> ap_ST_fsm_state48;
static const sc_lv<568> ap_ST_fsm_state49;
static const sc_lv<568> ap_ST_fsm_state50;
static const sc_lv<568> ap_ST_fsm_state51;
static const sc_lv<568> ap_ST_fsm_state52;
static const sc_lv<568> ap_ST_fsm_state53;
static const sc_lv<568> ap_ST_fsm_state54;
static const sc_lv<568> ap_ST_fsm_state55;
static const sc_lv<568> ap_ST_fsm_state56;
static const sc_lv<568> ap_ST_fsm_state57;
static const sc_lv<568> ap_ST_fsm_state58;
static const sc_lv<568> ap_ST_fsm_state59;
static const sc_lv<568> ap_ST_fsm_state60;
static const sc_lv<568> ap_ST_fsm_state61;
static const sc_lv<568> ap_ST_fsm_state62;
static const sc_lv<568> ap_ST_fsm_state63;
static const sc_lv<568> ap_ST_fsm_state64;
static const sc_lv<568> ap_ST_fsm_state65;
static const sc_lv<568> ap_ST_fsm_state66;
static const sc_lv<568> ap_ST_fsm_state67;
static const sc_lv<568> ap_ST_fsm_state68;
static const sc_lv<568> ap_ST_fsm_state69;
static const sc_lv<568> ap_ST_fsm_state70;
static const sc_lv<568> ap_ST_fsm_state71;
static const sc_lv<568> ap_ST_fsm_state72;
static const sc_lv<568> ap_ST_fsm_state73;
static const sc_lv<568> ap_ST_fsm_state74;
static const sc_lv<568> ap_ST_fsm_state75;
static const sc_lv<568> ap_ST_fsm_state76;
static const sc_lv<568> ap_ST_fsm_state77;
static const sc_lv<568> ap_ST_fsm_state78;
static const sc_lv<568> ap_ST_fsm_state79;
static const sc_lv<568> ap_ST_fsm_state80;
static const sc_lv<568> ap_ST_fsm_state81;
static const sc_lv<568> ap_ST_fsm_state82;
static const sc_lv<568> ap_ST_fsm_state83;
static const sc_lv<568> ap_ST_fsm_state84;
static const sc_lv<568> ap_ST_fsm_state85;
static const sc_lv<568> ap_ST_fsm_state86;
static const sc_lv<568> ap_ST_fsm_state87;
static const sc_lv<568> ap_ST_fsm_state88;
static const sc_lv<568> ap_ST_fsm_state89;
static const sc_lv<568> ap_ST_fsm_state90;
static const sc_lv<568> ap_ST_fsm_state91;
static const sc_lv<568> ap_ST_fsm_state92;
static const sc_lv<568> ap_ST_fsm_state93;
static const sc_lv<568> ap_ST_fsm_state94;
static const sc_lv<568> ap_ST_fsm_state95;
static const sc_lv<568> ap_ST_fsm_state96;
static const sc_lv<568> ap_ST_fsm_state97;
static const sc_lv<568> ap_ST_fsm_state98;
static const sc_lv<568> ap_ST_fsm_state99;
static const sc_lv<568> ap_ST_fsm_state100;
static const sc_lv<568> ap_ST_fsm_state101;
static const sc_lv<568> ap_ST_fsm_state102;
static const sc_lv<568> ap_ST_fsm_state103;
static const sc_lv<568> ap_ST_fsm_state104;
static const sc_lv<568> ap_ST_fsm_state105;
static const sc_lv<568> ap_ST_fsm_state106;
static const sc_lv<568> ap_ST_fsm_state107;
static const sc_lv<568> ap_ST_fsm_state108;
static const sc_lv<568> ap_ST_fsm_state109;
static const sc_lv<568> ap_ST_fsm_state110;
static const sc_lv<568> ap_ST_fsm_state111;
static const sc_lv<568> ap_ST_fsm_state112;
static const sc_lv<568> ap_ST_fsm_state113;
static const sc_lv<568> ap_ST_fsm_state114;
static const sc_lv<568> ap_ST_fsm_state115;
static const sc_lv<568> ap_ST_fsm_state116;
static const sc_lv<568> ap_ST_fsm_state117;
static const sc_lv<568> ap_ST_fsm_state118;
static const sc_lv<568> ap_ST_fsm_state119;
static const sc_lv<568> ap_ST_fsm_state120;
static const sc_lv<568> ap_ST_fsm_state121;
static const sc_lv<568> ap_ST_fsm_state122;
static const sc_lv<568> ap_ST_fsm_state123;
static const sc_lv<568> ap_ST_fsm_state124;
static const sc_lv<568> ap_ST_fsm_state125;
static const sc_lv<568> ap_ST_fsm_state126;
static const sc_lv<568> ap_ST_fsm_state127;
static const sc_lv<568> ap_ST_fsm_state128;
static const sc_lv<568> ap_ST_fsm_state129;
static const sc_lv<568> ap_ST_fsm_state130;
static const sc_lv<568> ap_ST_fsm_state131;
static const sc_lv<568> ap_ST_fsm_state132;
static const sc_lv<568> ap_ST_fsm_state133;
static const sc_lv<568> ap_ST_fsm_state134;
static const sc_lv<568> ap_ST_fsm_state135;
static const sc_lv<568> ap_ST_fsm_state136;
static const sc_lv<568> ap_ST_fsm_state137;
static const sc_lv<568> ap_ST_fsm_state138;
static const sc_lv<568> ap_ST_fsm_state139;
static const sc_lv<568> ap_ST_fsm_state140;
static const sc_lv<568> ap_ST_fsm_state141;
static const sc_lv<568> ap_ST_fsm_state142;
static const sc_lv<568> ap_ST_fsm_state143;
static const sc_lv<568> ap_ST_fsm_state144;
static const sc_lv<568> ap_ST_fsm_state145;
static const sc_lv<568> ap_ST_fsm_state146;
static const sc_lv<568> ap_ST_fsm_state147;
static const sc_lv<568> ap_ST_fsm_state148;
static const sc_lv<568> ap_ST_fsm_state149;
static const sc_lv<568> ap_ST_fsm_state150;
static const sc_lv<568> ap_ST_fsm_state151;
static const sc_lv<568> ap_ST_fsm_state152;
static const sc_lv<568> ap_ST_fsm_state153;
static const sc_lv<568> ap_ST_fsm_state154;
static const sc_lv<568> ap_ST_fsm_state155;
static const sc_lv<568> ap_ST_fsm_state156;
static const sc_lv<568> ap_ST_fsm_state157;
static const sc_lv<568> ap_ST_fsm_state158;
static const sc_lv<568> ap_ST_fsm_state159;
static const sc_lv<568> ap_ST_fsm_state160;
static const sc_lv<568> ap_ST_fsm_state161;
static const sc_lv<568> ap_ST_fsm_state162;
static const sc_lv<568> ap_ST_fsm_state163;
static const sc_lv<568> ap_ST_fsm_state164;
static const sc_lv<568> ap_ST_fsm_state165;
static const sc_lv<568> ap_ST_fsm_state166;
static const sc_lv<568> ap_ST_fsm_state167;
static const sc_lv<568> ap_ST_fsm_state168;
static const sc_lv<568> ap_ST_fsm_state169;
static const sc_lv<568> ap_ST_fsm_state170;
static const sc_lv<568> ap_ST_fsm_state171;
static const sc_lv<568> ap_ST_fsm_state172;
static const sc_lv<568> ap_ST_fsm_state173;
static const sc_lv<568> ap_ST_fsm_state174;
static const sc_lv<568> ap_ST_fsm_state175;
static const sc_lv<568> ap_ST_fsm_state176;
static const sc_lv<568> ap_ST_fsm_state177;
static const sc_lv<568> ap_ST_fsm_state178;
static const sc_lv<568> ap_ST_fsm_state179;
static const sc_lv<568> ap_ST_fsm_state180;
static const sc_lv<568> ap_ST_fsm_state181;
static const sc_lv<568> ap_ST_fsm_state182;
static const sc_lv<568> ap_ST_fsm_state183;
static const sc_lv<568> ap_ST_fsm_state184;
static const sc_lv<568> ap_ST_fsm_state185;
static const sc_lv<568> ap_ST_fsm_state186;
static const sc_lv<568> ap_ST_fsm_state187;
static const sc_lv<568> ap_ST_fsm_state188;
static const sc_lv<568> ap_ST_fsm_state189;
static const sc_lv<568> ap_ST_fsm_state190;
static const sc_lv<568> ap_ST_fsm_state191;
static const sc_lv<568> ap_ST_fsm_state192;
static const sc_lv<568> ap_ST_fsm_state193;
static const sc_lv<568> ap_ST_fsm_state194;
static const sc_lv<568> ap_ST_fsm_state195;
static const sc_lv<568> ap_ST_fsm_state196;
static const sc_lv<568> ap_ST_fsm_state197;
static const sc_lv<568> ap_ST_fsm_state198;
static const sc_lv<568> ap_ST_fsm_state199;
static const sc_lv<568> ap_ST_fsm_state200;
static const sc_lv<568> ap_ST_fsm_state201;
static const sc_lv<568> ap_ST_fsm_state202;
static const sc_lv<568> ap_ST_fsm_state203;
static const sc_lv<568> ap_ST_fsm_state204;
static const sc_lv<568> ap_ST_fsm_state205;
static const sc_lv<568> ap_ST_fsm_state206;
static const sc_lv<568> ap_ST_fsm_state207;
static const sc_lv<568> ap_ST_fsm_state208;
static const sc_lv<568> ap_ST_fsm_state209;
static const sc_lv<568> ap_ST_fsm_state210;
static const sc_lv<568> ap_ST_fsm_state211;
static const sc_lv<568> ap_ST_fsm_state212;
static const sc_lv<568> ap_ST_fsm_state213;
static const sc_lv<568> ap_ST_fsm_state214;
static const sc_lv<568> ap_ST_fsm_state215;
static const sc_lv<568> ap_ST_fsm_state216;
static const sc_lv<568> ap_ST_fsm_state217;
static const sc_lv<568> ap_ST_fsm_state218;
static const sc_lv<568> ap_ST_fsm_state219;
static const sc_lv<568> ap_ST_fsm_state220;
static const sc_lv<568> ap_ST_fsm_state221;
static const sc_lv<568> ap_ST_fsm_state222;
static const sc_lv<568> ap_ST_fsm_state223;
static const sc_lv<568> ap_ST_fsm_state224;
static const sc_lv<568> ap_ST_fsm_state225;
static const sc_lv<568> ap_ST_fsm_state226;
static const sc_lv<568> ap_ST_fsm_state227;
static const sc_lv<568> ap_ST_fsm_state228;
static const sc_lv<568> ap_ST_fsm_state229;
static const sc_lv<568> ap_ST_fsm_state230;
static const sc_lv<568> ap_ST_fsm_state231;
static const sc_lv<568> ap_ST_fsm_state232;
static const sc_lv<568> ap_ST_fsm_state233;
static const sc_lv<568> ap_ST_fsm_state234;
static const sc_lv<568> ap_ST_fsm_state235;
static const sc_lv<568> ap_ST_fsm_state236;
static const sc_lv<568> ap_ST_fsm_state237;
static const sc_lv<568> ap_ST_fsm_state238;
static const sc_lv<568> ap_ST_fsm_state239;
static const sc_lv<568> ap_ST_fsm_state240;
static const sc_lv<568> ap_ST_fsm_state241;
static const sc_lv<568> ap_ST_fsm_state242;
static const sc_lv<568> ap_ST_fsm_state243;
static const sc_lv<568> ap_ST_fsm_state244;
static const sc_lv<568> ap_ST_fsm_state245;
static const sc_lv<568> ap_ST_fsm_state246;
static const sc_lv<568> ap_ST_fsm_state247;
static const sc_lv<568> ap_ST_fsm_state248;
static const sc_lv<568> ap_ST_fsm_state249;
static const sc_lv<568> ap_ST_fsm_state250;
static const sc_lv<568> ap_ST_fsm_state251;
static const sc_lv<568> ap_ST_fsm_state252;
static const sc_lv<568> ap_ST_fsm_state253;
static const sc_lv<568> ap_ST_fsm_state254;
static const sc_lv<568> ap_ST_fsm_state255;
static const sc_lv<568> ap_ST_fsm_state256;
static const sc_lv<568> ap_ST_fsm_state257;
static const sc_lv<568> ap_ST_fsm_state258;
static const sc_lv<568> ap_ST_fsm_state259;
static const sc_lv<568> ap_ST_fsm_state260;
static const sc_lv<568> ap_ST_fsm_state261;
static const sc_lv<568> ap_ST_fsm_state262;
static const sc_lv<568> ap_ST_fsm_state263;
static const sc_lv<568> ap_ST_fsm_state264;
static const sc_lv<568> ap_ST_fsm_state265;
static const sc_lv<568> ap_ST_fsm_state266;
static const sc_lv<568> ap_ST_fsm_state267;
static const sc_lv<568> ap_ST_fsm_state268;
static const sc_lv<568> ap_ST_fsm_state269;
static const sc_lv<568> ap_ST_fsm_state270;
static const sc_lv<568> ap_ST_fsm_state271;
static const sc_lv<568> ap_ST_fsm_state272;
static const sc_lv<568> ap_ST_fsm_state273;
static const sc_lv<568> ap_ST_fsm_state274;
static const sc_lv<568> ap_ST_fsm_state275;
static const sc_lv<568> ap_ST_fsm_state276;
static const sc_lv<568> ap_ST_fsm_state277;
static const sc_lv<568> ap_ST_fsm_state278;
static const sc_lv<568> ap_ST_fsm_state279;
static const sc_lv<568> ap_ST_fsm_state280;
static const sc_lv<568> ap_ST_fsm_state281;
static const sc_lv<568> ap_ST_fsm_state282;
static const sc_lv<568> ap_ST_fsm_state283;
static const sc_lv<568> ap_ST_fsm_state284;
static const sc_lv<568> ap_ST_fsm_state285;
static const sc_lv<568> ap_ST_fsm_state286;
static const sc_lv<568> ap_ST_fsm_state287;
static const sc_lv<568> ap_ST_fsm_state288;
static const sc_lv<568> ap_ST_fsm_state289;
static const sc_lv<568> ap_ST_fsm_state290;
static const sc_lv<568> ap_ST_fsm_state291;
static const sc_lv<568> ap_ST_fsm_state292;
static const sc_lv<568> ap_ST_fsm_state293;
static const sc_lv<568> ap_ST_fsm_state294;
static const sc_lv<568> ap_ST_fsm_state295;
static const sc_lv<568> ap_ST_fsm_state296;
static const sc_lv<568> ap_ST_fsm_state297;
static const sc_lv<568> ap_ST_fsm_state298;
static const sc_lv<568> ap_ST_fsm_state299;
static const sc_lv<568> ap_ST_fsm_state300;
static const sc_lv<568> ap_ST_fsm_state301;
static const sc_lv<568> ap_ST_fsm_state302;
static const sc_lv<568> ap_ST_fsm_state303;
static const sc_lv<568> ap_ST_fsm_state304;
static const sc_lv<568> ap_ST_fsm_state305;
static const sc_lv<568> ap_ST_fsm_state306;
static const sc_lv<568> ap_ST_fsm_sta
|
te307;
static const sc_lv<568> ap_ST_fsm_state308;
static const sc_lv<568> ap_ST_fsm_state309;
static const sc_lv<568> ap_ST_fsm_state310;
static const sc_lv<568> ap_ST_fsm_state311;
static const sc_lv<568> ap_ST_fsm_state312;
static const sc_lv<568> ap_ST_fsm_state313;
static const sc_lv<568> ap_ST_fsm_state314;
static const sc_lv<568> ap_ST_fsm_state315;
static const sc_lv<568> ap_ST_fsm_state316;
static const sc_lv<568> ap_ST_fsm_state317;
static const sc_lv<568> ap_ST_fsm_state318;
static const sc_lv<568> ap_ST_fsm_state319;
static const sc_lv<568> ap_ST_fsm_state320;
static const sc_lv<568> ap_ST_fsm_state321;
static const sc_lv<568> ap_ST_fsm_state322;
static const sc_lv<568> ap_ST_fsm_state323;
static const sc_lv<568> ap_ST_fsm_state324;
static const sc_lv<568> ap_ST_fsm_state325;
static const sc_lv<568> ap_ST_fsm_state326;
static const sc_lv<568> ap_ST_fsm_state327;
static const sc_lv<568> ap_ST_fsm_state328;
static const sc_lv<568> ap_ST_fsm_state329;
static const sc_lv<568> ap_ST_fsm_state330;
static const sc_lv<568> ap_ST_fsm_state331;
static const sc_lv<568> ap_ST_fsm_state332;
static const sc_lv<568> ap_ST_fsm_state333;
static const sc_lv<568> ap_ST_fsm_state334;
static const sc_lv<568> ap_ST_fsm_state335;
static const sc_lv<568> ap_ST_fsm_state336;
static const sc_lv<568> ap_ST_fsm_state337;
static const sc_lv<568> ap_ST_fsm_state338;
static const sc_lv<568> ap_ST_fsm_state339;
static const sc_lv<568> ap_ST_fsm_state340;
static const sc_lv<568> ap_ST_fsm_state341;
static const sc_lv<568> ap_ST_fsm_state342;
static const sc_lv<568> ap_ST_fsm_state343;
static const sc_lv<568> ap_ST_fsm_state344;
static const sc_lv<568> ap_ST_fsm_state345;
static const sc_lv<568> ap_ST_fsm_state346;
static const sc_lv<568> ap_ST_fsm_state347;
static const sc_lv<568> ap_ST_fsm_state348;
static const sc_lv<568> ap_ST_fsm_state349;
static const sc_lv<568> ap_ST_fsm_state350;
static const sc_lv<568> ap_ST_fsm_state351;
static const sc_lv<568> ap_ST_fsm_state352;
static const sc_lv<568> ap_ST_fsm_state353;
static const sc_lv<568> ap_ST_fsm_state354;
static const sc_lv<568> ap_ST_fsm_state355;
static const sc_lv<568> ap_ST_fsm_state356;
static const sc_lv<568> ap_ST_fsm_state357;
static const sc_lv<568> ap_ST_fsm_state358;
static const sc_lv<568> ap_ST_fsm_state359;
static const sc_lv<568> ap_ST_fsm_state360;
static const sc_lv<568> ap_ST_fsm_state361;
static const sc_lv<568> ap_ST_fsm_state362;
static const sc_lv<568> ap_ST_fsm_state363;
static const sc_lv<568> ap_ST_fsm_state364;
static const sc_lv<568> ap_ST_fsm_state365;
static const sc_lv<568> ap_ST_fsm_state366;
static const sc_lv<568> ap_ST_fsm_state367;
static const sc_lv<568> ap_ST_fsm_state368;
static const sc_lv<568> ap_ST_fsm_state369;
static const sc_lv<568> ap_ST_fsm_state370;
static const sc_lv<568> ap_ST_fsm_state371;
static const sc_lv<568> ap_ST_fsm_state372;
static const sc_lv<568> ap_ST_fsm_state373;
static const sc_lv<568> ap_ST_fsm_state374;
static const sc_lv<568> ap_ST_fsm_state375;
static const sc_lv<568> ap_ST_fsm_state376;
static const sc_lv<568> ap_ST_fsm_state377;
static const sc_lv<568> ap_ST_fsm_state378;
static const sc_lv<568> ap_ST_fsm_state379;
static const sc_lv<568> ap_ST_fsm_state380;
static const sc_lv<568> ap_ST_fsm_state381;
static const sc_lv<568> ap_ST_fsm_state382;
static const sc_lv<568> ap_ST_fsm_state383;
static const sc_lv<568> ap_ST_fsm_state384;
static const sc_lv<568> ap_ST_fsm_state385;
static const sc_lv<568> ap_ST_fsm_state386;
static const sc_lv<568> ap_ST_fsm_state387;
static const sc_lv<568> ap_ST_fsm_state388;
static const sc_lv<568> ap_ST_fsm_state389;
static const sc_lv<568> ap_ST_fsm_state390;
static const sc_lv<568> ap_ST_fsm_state391;
static const sc_lv<568> ap_ST_fsm_state392;
static const sc_lv<568> ap_ST_fsm_state393;
static const sc_lv<568> ap_ST_fsm_state394;
static const sc_lv<568> ap_ST_fsm_state395;
static const sc_lv<568> ap_ST_fsm_state396;
static const sc_lv<568> ap_ST_fsm_state397;
static const sc_lv<568> ap_ST_fsm_state398;
static const sc_lv<568> ap_ST_fsm_state399;
static const sc_lv<568> ap_ST_fsm_state400;
static const sc_lv<568> ap_ST_fsm_state401;
static const sc_lv<568> ap_ST_fsm_state402;
static const sc_lv<568> ap_ST_fsm_state403;
static const sc_lv<568> ap_ST_fsm_state404;
static const sc_lv<568> ap_ST_fsm_state405;
static const sc_lv<568> ap_ST_fsm_state406;
static const sc_lv<568> ap_ST_fsm_state407;
static const sc_lv<568> ap_ST_fsm_state408;
static const sc_lv<568> ap_ST_fsm_state409;
static const sc_lv<568> ap_ST_fsm_state410;
static const sc_lv<568> ap_ST_fsm_state411;
static const sc_lv<568> ap_ST_fsm_state412;
static const sc_lv<568> ap_ST_fsm_state413;
static const sc_lv<568> ap_ST_fsm_state414;
static const sc_lv<568> ap_ST_fsm_state415;
static const sc_lv<568> ap_ST_fsm_state416;
static const sc_lv<568> ap_ST_fsm_state417;
static const sc_lv<568> ap_ST_fsm_state418;
static const sc_lv<568> ap_ST_fsm_state419;
static const sc_lv<568> ap_ST_fsm_state420;
static const sc_lv<568> ap_ST_fsm_state421;
static const sc_lv<568> ap_ST_fsm_state422;
static const sc_lv<568> ap_ST_fsm_state423;
static const sc_lv<568> ap_ST_fsm_state424;
static const sc_lv<568> ap_ST_fsm_state425;
static const sc_lv<568> ap_ST_fsm_state426;
static const sc_lv<568> ap_ST_fsm_state427;
static const sc_lv<568> ap_ST_fsm_state428;
static const sc_lv<568> ap_ST_fsm_state429;
static const sc_lv<568> ap_ST_fsm_state430;
static const sc_lv<568> ap_ST_fsm_state431;
static const sc_lv<568> ap_ST_fsm_state432;
static const sc_lv<568> ap_ST_fsm_state433;
static const sc_lv<568> ap_ST_fsm_state434;
static const sc_lv<568> ap_ST_fsm_state435;
static const sc_lv<568> ap_ST_fsm_state436;
static const sc_lv<568> ap_ST_fsm_state437;
static const sc_lv<568> ap_ST_fsm_state438;
static const sc_lv<568> ap_ST_fsm_state439;
static const sc_lv<568> ap_ST_fsm_state440;
static const sc_lv<568> ap_ST_fsm_state441;
static const sc_lv<568> ap_ST_fsm_state442;
static const sc_lv<568> ap_ST_fsm_state443;
static const sc_lv<568> ap_ST_fsm_state444;
static const sc_lv<568> ap_ST_fsm_state445;
static const sc_lv<568> ap_ST_fsm_state446;
static const sc_lv<568> ap_ST_fsm_state447;
static const sc_lv<568> ap_ST_fsm_state448;
static const sc_lv<568> ap_ST_fsm_state449;
static const sc_lv<568> ap_ST_fsm_state450;
static const sc_lv<568> ap_ST_fsm_state451;
static const sc_lv<568> ap_ST_fsm_state452;
static const sc_lv<568> ap_ST_fsm_state453;
static const sc_lv<568> ap_ST_fsm_state454;
static const sc_lv<568> ap_ST_fsm_state455;
static const sc_lv<568> ap_ST_fsm_state456;
static const sc_lv<568> ap_ST_fsm_state457;
static const sc_lv<568> ap_ST_fsm_state458;
static const sc_lv<568> ap_ST_fsm_state459;
static const sc_lv<568> ap_ST_fsm_state460;
static const sc_lv<568> ap_ST_fsm_state461;
static const sc_lv<568> ap_ST_fsm_state462;
static const sc_lv<568> ap_ST_fsm_state463;
static const sc_lv<568> ap_ST_fsm_state464;
static const sc_lv<568> ap_ST_fsm_state465;
static const sc_lv<568> ap_ST_fsm_state466;
static const sc_lv<568> ap_ST_fsm_state467;
static const sc_lv<568> ap_ST_fsm_state468;
static const sc_lv<568> ap_ST_fsm_state469;
static const sc_lv<568> ap_ST_fsm_state470;
static const sc_lv<568> ap_ST_fsm_state471;
static const sc_lv<568> ap_ST_fsm_state472;
static const sc_lv<568> ap_ST_fsm_state473;
static const sc_lv<568> ap_ST_fsm_state474;
static const sc_lv<568> ap_ST_fsm_state475;
static const sc_lv<568> ap_ST_fsm_state476;
static const sc_lv<568> ap_ST_fsm_state477;
static const sc_lv<568> ap_ST_fsm_state478;
static const sc_lv<568> ap_ST_fsm_state479;
static const sc_lv<568> ap_ST_fsm_state480;
static const sc_lv<568> ap_ST_fsm_state481;
static const sc_lv<568> ap_ST_fsm_state482;
static const sc_lv<568> ap_ST_fsm_state483;
static const sc_lv<568> ap_ST_fsm_state484;
static const sc_lv<568> ap_ST_fsm_state485;
static const sc_lv<568> ap_ST_fsm_state486;
static const sc_lv<568> ap_ST_fsm_state487;
static const sc_lv<568> ap_ST_fsm_state488;
static const sc_lv<568> ap_ST_fsm_state489;
static const sc_lv<568> ap_ST_fsm_state490;
static const sc_lv<568> ap_ST_fsm_state491;
static const sc_lv<568> ap_ST_fsm_state492;
static const sc_lv<568> ap_ST_fsm_state493;
static const sc_lv<568> ap_ST_fsm_state494;
static const sc_lv<568> ap_ST_fsm_state495;
static const sc_lv<568> ap_ST_fsm_state496;
static const sc_lv<568> ap_ST_fsm_state497;
static const sc_lv<568> ap_ST_fsm_state498;
static const sc_lv<568> ap_ST_fsm_state499;
static const sc_lv<568> ap_ST_fsm_state500;
static const sc_lv<568> ap_ST_fsm_state501;
static const sc_lv<568> ap_ST_fsm_state502;
static const sc_lv<568> ap_ST_fsm_state503;
static const sc_lv<568> ap_ST_fsm_state504;
static const sc_lv<568> ap_ST_fsm_state505;
static const sc_lv<568> ap_ST_fsm_state506;
static const sc_lv<568> ap_ST_fsm_state507;
static const sc_lv<568> ap_ST_fsm_state508;
static const sc_lv<568> ap_ST_fsm_state509;
static const sc_lv<568> ap_ST_fsm_state510;
static const sc_lv<568> ap_ST_fsm_state511;
static const sc_lv<568> ap_ST_fsm_state512;
static const sc_lv<568> ap_ST_fsm_state513;
static const sc_lv<568> ap_ST_fsm_state514;
static const sc_lv<568> ap_ST_fsm_state515;
static const sc_lv<568> ap_ST_fsm_state516;
static const sc_lv<568> ap_ST_fsm_state517;
static const sc_lv<568> ap_ST_fsm_state518;
static const sc_lv<568> ap_ST_fsm_state519;
static const sc_lv<568> ap_ST_fsm_state520;
static const sc_lv<568> ap_ST_fsm_state521;
static const sc_lv<568> ap_ST_fsm_state522;
static const sc_lv<568> ap_ST_fsm_state523;
static const sc_lv<568> ap_ST_fsm_state524;
static const sc_lv<568> ap_ST_fsm_state525;
static const sc_lv<568> ap_ST_fsm_state526;
static const sc_lv<568> ap_ST_fsm_state527;
static const sc_lv<568> ap_ST_fsm_state528;
static const sc_lv<568> ap_ST_fsm_state529;
static const sc_lv<568> ap_ST_fsm_state530;
static const sc_lv<568> ap_ST_fsm_state531;
static const sc_lv<568> ap_ST_fsm_state532;
static const sc_lv<568> ap_ST_fsm_state533;
static const sc_lv<568> ap_ST_fsm_state534;
static const sc_lv<568> ap_ST_fsm_state535;
static const sc_lv<568> ap_ST_fsm_state536;
static const sc_lv<568> ap_ST_fsm_state537;
static const sc_lv<568> ap_ST_fsm_state538;
static const sc_lv<568> ap_ST_fsm_state539;
static const sc_lv<568> ap_ST_fsm_state540;
static const sc_lv<568> ap_ST_fsm_state541;
static const sc_lv<568> ap_ST_fsm_state542;
static const sc_lv<568> ap_ST_fsm_state543;
static const sc_lv<568> ap_ST_fsm_state544;
static const sc_lv<568> ap_ST_fsm_state545;
static const sc_lv<568> ap_ST_fsm_state546;
static const sc_lv<568> ap_ST_fsm_state547;
static const sc_lv<568> ap_ST_fsm_state548;
static const sc_lv<568> ap_ST_fsm_state549;
static const sc_lv<568> ap_ST_fsm_state550;
static const sc_lv<568> ap_ST_fsm_state551;
static const sc_lv<568> ap_ST_fsm_state552;
static const sc_lv<568> ap_ST_fsm_state553;
static const sc_lv<568> ap_ST_fsm_state554;
static const sc_lv<568> ap_ST_fsm_state555;
static const sc_lv<568> ap_ST_fsm_state556;
static const sc_lv<568> ap_ST_fsm_state557;
static const sc_lv<568> ap_ST_fsm_state558;
static const sc_lv<568> ap_ST_fsm_state559;
static const sc_lv<568> ap_ST_fsm_state560;
static const sc_lv<568> ap_ST_fsm_state561;
static const sc_lv<568> ap_ST_fsm_state562;
static const sc_lv<568> ap_ST_fsm_state563;
static const sc_lv<568> ap_ST_fsm_state564;
static const sc_lv<568> ap_ST_fsm_state565;
static const sc_lv<568> ap_ST_fsm_state566;
static const sc_lv<568> ap_ST_fsm_state567;
static const sc_lv<568> ap_ST_fsm_state568;
static const sc_lv<32> ap_const_lv32_0;
static const int C_S_AXI_DATA_WIDTH;
static const sc_lv<32> ap_const_lv32_1;
static const sc_lv<1> ap_const_lv1_0;
static const sc_lv<32> ap_const_lv32_2;
static const sc_lv<32> ap_const_lv32_3;
static const sc_lv<32> ap_const_lv32_5;
static const sc_lv<32> ap_const_lv32_7;
static const sc_lv<32> ap_const_lv32_9;
static const sc_lv<32> ap_const_lv32_B;
static const sc_lv<32> ap_const_lv32_D;
static const sc_lv<32> ap_const_lv32_F;
static const sc_lv<32> ap_const_lv32_11;
static const sc_lv<32> ap_const_lv32_13;
static const sc_lv<32> ap_const_lv32_15;
static const sc_lv<32> ap_const_lv32_17;
static const sc_lv<32> ap_const_lv32_19;
static const sc_lv<32> ap_const_lv32_1B;
static const sc_lv<32> ap_const_lv32_1D;
static const sc_lv<32> ap_const_lv32_1F;
static const sc_lv<32> ap_const_lv32_21;
static const sc_lv<32> ap_const_lv32_23;
static const sc_lv<32> ap_const_lv32_25;
static const sc_lv<32> ap_const_lv32_27;
static const sc_lv<32> ap_const_lv32_29;
static const sc_lv<32> ap_const_lv32_2B;
static const sc_lv<32> ap_const_lv32_2D;
static const sc_lv<32> ap_const_lv32_2F;
static const sc_lv<32> ap_const_lv32_31;
static const sc_lv<32> ap_const_lv32_33;
static const sc_lv<32> ap_const_lv32_35;
static const sc_lv<32> ap_const_lv32_37;
static const sc_lv<32> ap_const_lv32_39;
static const sc_lv<32> ap_const_lv32_3B;
static const sc_lv<32> ap_const_lv32_3D;
static const sc_lv<32> ap_const_lv32_3F;
static const sc_lv<32> ap_const_lv32_41;
static const sc_lv<32> ap_const_lv32_43;
static const sc_lv<32> ap_const_lv32_45;
static const sc_lv<32> ap_const_lv32_47;
static const sc_lv<32> ap_const_lv32_49;
static const sc_lv<32> ap_const_lv32_4B;
static const sc_lv<32> ap_const_lv32_4D;
static const sc_lv<32> ap_const_lv32_4F;
static const sc_lv<32> ap_const_lv32_51;
static const sc_lv<32> ap_const_lv32_53;
static const sc_lv<32> ap_const_lv32_55;
static const sc_lv<32> ap_const_lv32_57;
static const sc_lv<32> ap_const_lv32_59;
static const sc_lv<32> ap_const_lv32_5B;
static const sc_lv<32> ap_const_lv32_5D;
static const sc_lv<32> ap_const_lv32_5F;
static const sc_lv<32> ap_const_lv32_61;
static const sc_lv<32> ap_const_lv32_63;
static const sc_lv<32> ap_const_lv32_65;
static const sc_lv<32> ap_const_lv32_67;
static const sc_lv<32> ap_const_lv32_69;
static const sc_lv<32> ap_const_lv32_6B;
static const sc_lv<32> ap_const_lv32_6D;
static const sc_lv<32> ap_const_lv32_6F;
static const sc_lv<32> ap_const_lv32_71;
static const sc_lv<32> ap_const_lv32_73;
static const sc_lv<32> ap_const_lv32_75;
static const sc_lv<32> ap_const_lv32_77;
static const sc_lv<32> ap_const_lv32_79;
static const sc_lv<32> ap_const_lv32_7B;
static const sc_lv<32> ap_const_lv32_7D;
static const sc_lv<32> ap_const_lv32_7F;
static const sc_lv<32> ap_const_lv32_81;
static const sc_lv<32> ap_const_lv32_83;
static const sc_lv<32> ap_const_lv32_85;
static const sc_lv<32> ap_const_lv32_87;
static const sc_lv<32> ap_const_lv32_89;
static const sc_lv<32> ap_const_lv32_8B;
static const sc_lv<32> ap_const_lv32_8D;
static const sc_lv<32> ap_const_lv32_8F;
static const sc_lv<32> ap_const_lv32_91;
static const sc_lv<32> ap_const_lv32_93;
static const sc_lv<32> ap_const_lv32_95;
static const sc_lv<32> ap_const_lv32_97;
static const sc_lv<32> ap_const_lv32_99;
static const sc_lv<32> ap_const_lv32_9B;
static const sc_lv<32> ap_const_lv32_9D;
static const sc_lv<32> ap_const_lv32_9F;
static const sc_lv<32> ap_const_lv32_A1;
static const sc_lv<32> ap_const_lv32_A3;
static const sc_lv<32> ap_const_lv32_A5;
static const sc_lv<32> ap_const_lv32_A7;
static const sc_lv<32> ap_const_lv32_A9;
static const sc_lv<32> ap_const_lv32_AB;
static const sc_lv<32> ap_const_lv32_AD;
static const sc_lv<32> ap_const_lv32_AF;
static const sc_lv<32> ap_const_lv32_B1;
static const sc_lv<32> ap_const_lv32_B3;
static const sc_lv<32> ap_const_lv32_B5;
static const sc_lv<32> ap_const_lv32_B7;
static const sc_lv<32> ap_const_lv32_B9;
static const sc_lv<32> ap_const_lv32_BB;
static const sc_lv<32> ap_const_lv32_BD;
static const sc_lv<32> ap_const_lv32_BF;
static const sc_lv<32> ap_const_lv32_C1;
static const sc_lv<32> ap_const_lv32_C3;
static const sc_lv<32> ap_const_lv32_C5;
static const sc_lv<32> ap_const_lv32_C7;
static const sc_lv<32> ap_const_lv32_C9;
static const sc_lv<32> ap_const_lv32_CB;
static const sc_lv<32> ap_const_lv32_CD;
static const sc_lv<32> ap_const_lv32_CF;
static const sc_lv<32> ap_const_lv32_D1;
static const sc_lv<32> ap_const_lv32_D3;
static const sc_lv<32> ap_const_lv32_D5;
static const sc_lv<32> ap_const_lv32_D7;
static const sc_lv<32> ap_const_lv32_D9;
static const sc_lv<32> ap_const_lv32_DB;
static const sc_lv<32> ap_const_lv32_DD;
static const sc_lv<32> ap_const_lv32_DF;
static const sc_lv<32> ap_const_lv32_E1;
static const sc_lv<32> ap_const_lv32_E3;
static const sc_lv<32> ap_const_lv32_E5;
static const sc_lv<32> ap_const_lv32_E7;
static const sc_lv<32> ap_const_lv32_E9;
static const sc_lv<32> ap_const_lv32_EB;
static const sc_lv<32> ap_const_lv32_ED;
static const sc_lv<32> ap_const_lv32_EF;
static const sc_lv<32> ap_const_lv32_F1;
static const sc_lv<32> ap_const_lv32_F3;
static const sc_lv<32> ap_const_lv32_F5;
static const sc_lv<32> ap_const_lv32_F7;
static const sc_lv<32> ap_const_lv32_F9;
static const sc_lv<32> ap_const_lv32_FB;
static const sc_lv<32> ap_const_lv32_FD;
static const sc_lv<32> ap_const_lv32_FF;
static const sc_lv<32> ap_const_lv32_102;
static const sc_lv<32> ap_const_lv32_103;
static const sc_lv<32> ap_const_lv32_104;
static const sc_lv<32> ap_const_lv32_105;
static const sc_lv<32> ap_const_lv32_106;
static const sc_lv<32> ap_const_lv32_107;
static const sc_lv<32> ap_const_lv32_108;
static const sc_lv<32> ap_const_lv32_109;
static const sc_lv<32> ap_const_lv32_10A;
static const sc_lv<32> ap_const_lv32_10B;
static const sc_lv<32> ap_const_lv32_10C;
static const sc_lv<32> ap_const_lv32_10D;
static const sc_lv<32> ap_const_lv32_10E;
static const sc_lv<32> ap_const_lv32_10F;
static const sc_lv<32> ap_const_lv32_110;
static const sc_lv<32> ap_const_lv32_111;
static const sc_lv<32> ap_const_lv32_112;
static const sc_lv<32> ap_const_lv32_113;
static const sc_lv<32> ap_const_lv32_114;
static const sc_lv<32> ap_const_lv32_115;
static const sc_lv<32> ap_const_lv32_116;
static const sc_lv<32> ap_const_lv32_117;
static const sc_lv<32> ap_const_lv32_118;
static const sc_lv<32> ap_const_lv32_119;
static const sc_lv<32> ap_const_lv32_11A;
static const sc_lv<32> ap_const_lv32_11B;
static const sc_lv<32> ap_const_lv32_11C;
static const sc_lv<32> ap_const_lv32_11D;
static const sc_lv<32> ap_const_lv32_11E;
static const sc_lv<32> ap_const_lv32_11F;
static const sc_lv<32> ap_const_lv32_120;
static const sc_lv<32> ap_const_lv32_121;
static const sc_lv<32> ap_const_lv32_122;
static const sc_lv<3
|
2> ap_const_lv32_123;
static const sc_lv<32> ap_const_lv32_124;
static const sc_lv<32> ap_const_lv32_125;
static const sc_lv<32> ap_const_lv32_126;
static const sc_lv<32> ap_const_lv32_127;
static const sc_lv<32> ap_const_lv32_128;
static const sc_lv<32> ap_const_lv32_129;
static const sc_lv<32> ap_const_lv32_12A;
static const sc_lv<32> ap_const_lv32_12B;
static const sc_lv<32> ap_const_lv32_12C;
static const sc_lv<32> ap_const_lv32_12D;
static const sc_lv<32> ap_const_lv32_12E;
static const sc_lv<32> ap_const_lv32_12F;
static const sc_lv<32> ap_const_lv32_130;
static const sc_lv<32> ap_const_lv32_131;
static const sc_lv<32> ap_const_lv32_132;
static const sc_lv<32> ap_const_lv32_133;
static const sc_lv<32> ap_const_lv32_134;
static const sc_lv<32> ap_const_lv32_135;
static const sc_lv<32> ap_const_lv32_136;
static const sc_lv<32> ap_const_lv32_137;
static const sc_lv<32> ap_const_lv32_138;
static const sc_lv<32> ap_const_lv32_139;
static const sc_lv<32> ap_const_lv32_13A;
static const sc_lv<32> ap_const_lv32_13B;
static const sc_lv<32> ap_const_lv32_13C;
static const sc_lv<32> ap_const_lv32_13D;
static const sc_lv<32> ap_const_lv32_13E;
static const sc_lv<32> ap_const_lv32_13F;
static const sc_lv<32> ap_const_lv32_140;
static const sc_lv<32> ap_const_lv32_141;
static const sc_lv<32> ap_const_lv32_142;
static const sc_lv<32> ap_const_lv32_143;
static const sc_lv<32> ap_const_lv32_144;
static const sc_lv<32> ap_const_lv32_145;
static const sc_lv<32> ap_const_lv32_146;
static const sc_lv<32> ap_const_lv32_147;
static const sc_lv<32> ap_const_lv32_148;
static const sc_lv<32> ap_const_lv32_149;
static const sc_lv<32> ap_const_lv32_14A;
static const sc_lv<32> ap_const_lv32_14B;
static const sc_lv<32> ap_const_lv32_14C;
static const sc_lv<32> ap_const_lv32_14D;
static const sc_lv<32> ap_const_lv32_14E;
static const sc_lv<32> ap_const_lv32_14F;
static const sc_lv<32> ap_const_lv32_150;
static const sc_lv<32> ap_const_lv32_151;
static const sc_lv<32> ap_const_lv32_152;
static const sc_lv<32> ap_const_lv32_153;
static const sc_lv<32> ap_const_lv32_154;
static const sc_lv<32> ap_const_lv32_155;
static const sc_lv<32> ap_const_lv32_156;
static const sc_lv<32> ap_const_lv32_157;
static const sc_lv<32> ap_const_lv32_158;
static const sc_lv<32> ap_const_lv32_159;
static const sc_lv<32> ap_const_lv32_15A;
static const sc_lv<32> ap_const_lv32_15B;
static const sc_lv<32> ap_const_lv32_15C;
static const sc_lv<32> ap_const_lv32_15D;
static const sc_lv<32> ap_const_lv32_15E;
static const sc_lv<32> ap_const_lv32_15F;
static const sc_lv<32> ap_const_lv32_160;
static const sc_lv<32> ap_const_lv32_161;
static const sc_lv<32> ap_const_lv32_162;
static const sc_lv<32> ap_const_lv32_163;
static const sc_lv<32> ap_const_lv32_164;
static const sc_lv<32> ap_const_lv32_165;
static const sc_lv<32> ap_const_lv32_166;
static const sc_lv<32> ap_const_lv32_167;
static const sc_lv<32> ap_const_lv32_168;
static const sc_lv<32> ap_const_lv32_169;
static const sc_lv<32> ap_const_lv32_16A;
static const sc_lv<32> ap_const_lv32_16B;
static const sc_lv<32> ap_const_lv32_16C;
static const sc_lv<32> ap_const_lv32_16D;
static const sc_lv<32> ap_const_lv32_16E;
static const sc_lv<32> ap_const_lv32_16F;
static const sc_lv<32> ap_const_lv32_170;
static const sc_lv<32> ap_const_lv32_171;
static const sc_lv<32> ap_const_lv32_172;
static const sc_lv<32> ap_const_lv32_173;
static const sc_lv<32> ap_const_lv32_174;
static const sc_lv<32> ap_const_lv32_175;
static const sc_lv<32> ap_const_lv32_176;
static const sc_lv<32> ap_const_lv32_177;
static const sc_lv<32> ap_const_lv32_178;
static const sc_lv<32> ap_const_lv32_179;
static const sc_lv<32> ap_const_lv32_17A;
static const sc_lv<32> ap_const_lv32_17B;
static const sc_lv<32> ap_const_lv32_17C;
static const sc_lv<32> ap_const_lv32_17D;
static const sc_lv<32> ap_const_lv32_17E;
static const sc_lv<32> ap_const_lv32_17F;
static const sc_lv<32> ap_const_lv32_180;
static const sc_lv<32> ap_const_lv32_181;
static const sc_lv<32> ap_const_lv32_182;
static const sc_lv<32> ap_const_lv32_183;
static const sc_lv<32> ap_const_lv32_184;
static const sc_lv<32> ap_const_lv32_185;
static const sc_lv<32> ap_const_lv32_186;
static const sc_lv<32> ap_const_lv32_187;
static const sc_lv<32> ap_const_lv32_188;
static const sc_lv<32> ap_const_lv32_189;
static const sc_lv<32> ap_const_lv32_18A;
static const sc_lv<32> ap_const_lv32_18B;
static const sc_lv<32> ap_const_lv32_18C;
static const sc_lv<32> ap_const_lv32_18D;
static const sc_lv<32> ap_const_lv32_18E;
static const sc_lv<32> ap_const_lv32_18F;
static const sc_lv<32> ap_const_lv32_190;
static const sc_lv<32> ap_const_lv32_191;
static const sc_lv<32> ap_const_lv32_192;
static const sc_lv<32> ap_const_lv32_193;
static const sc_lv<32> ap_const_lv32_194;
static const sc_lv<32> ap_const_lv32_195;
static const sc_lv<32> ap_const_lv32_196;
static const sc_lv<32> ap_const_lv32_197;
static const sc_lv<32> ap_const_lv32_198;
static const sc_lv<32> ap_const_lv32_199;
static const sc_lv<32> ap_const_lv32_19A;
static const sc_lv<32> ap_const_lv32_19B;
static const sc_lv<32> ap_const_lv32_19C;
static const sc_lv<32> ap_const_lv32_19D;
static const sc_lv<32> ap_const_lv32_19E;
static const sc_lv<32> ap_const_lv32_19F;
static const sc_lv<32> ap_const_lv32_1A0;
static const sc_lv<32> ap_const_lv32_1A1;
static const sc_lv<32> ap_const_lv32_1A2;
static const sc_lv<32> ap_const_lv32_1A3;
static const sc_lv<32> ap_const_lv32_1A4;
static const sc_lv<32> ap_const_lv32_1A5;
static const sc_lv<32> ap_const_lv32_1A6;
static const sc_lv<32> ap_const_lv32_1A7;
static const sc_lv<32> ap_const_lv32_1A8;
static const sc_lv<32> ap_const_lv32_1A9;
static const sc_lv<32> ap_const_lv32_1AA;
static const sc_lv<32> ap_const_lv32_1AB;
static const sc_lv<32> ap_const_lv32_1AC;
static const sc_lv<32> ap_const_lv32_1AD;
static const sc_lv<32> ap_const_lv32_1AE;
static const sc_lv<32> ap_const_lv32_1AF;
static const sc_lv<32> ap_const_lv32_1B0;
static const sc_lv<32> ap_const_lv32_1B1;
static const sc_lv<32> ap_const_lv32_1B2;
static const sc_lv<32> ap_const_lv32_1B3;
static const sc_lv<32> ap_const_lv32_1B4;
static const sc_lv<32> ap_const_lv32_1B5;
static const sc_lv<32> ap_const_lv32_1B6;
static const sc_lv<32> ap_const_lv32_1B7;
static const sc_lv<32> ap_const_lv32_1B8;
static const sc_lv<32> ap_const_lv32_1B9;
static const sc_lv<32> ap_const_lv32_1BA;
static const sc_lv<32> ap_const_lv32_1BB;
static const sc_lv<32> ap_const_lv32_1BC;
static const sc_lv<32> ap_const_lv32_1BD;
static const sc_lv<32> ap_const_lv32_1BE;
static const sc_lv<32> ap_const_lv32_1BF;
static const sc_lv<32> ap_const_lv32_1C0;
static const sc_lv<32> ap_const_lv32_1C1;
static const sc_lv<32> ap_const_lv32_1C2;
static const sc_lv<32> ap_const_lv32_1C3;
static const sc_lv<32> ap_const_lv32_1C4;
static const sc_lv<32> ap_const_lv32_1C5;
static const sc_lv<32> ap_const_lv32_1C6;
static const sc_lv<32> ap_const_lv32_1C7;
static const sc_lv<32> ap_const_lv32_1C8;
static const sc_lv<32> ap_const_lv32_1C9;
static const sc_lv<32> ap_const_lv32_1CA;
static const sc_lv<32> ap_const_lv32_1CB;
static const sc_lv<32> ap_const_lv32_1CC;
static const sc_lv<32> ap_const_lv32_1CD;
static const sc_lv<32> ap_const_lv32_1CE;
static const sc_lv<32> ap_const_lv32_1CF;
static const sc_lv<32> ap_const_lv32_1D0;
static const sc_lv<32> ap_const_lv32_1D1;
static const sc_lv<32> ap_const_lv32_1D2;
static const sc_lv<32> ap_const_lv32_1D3;
static const sc_lv<32> ap_const_lv32_1D4;
static const sc_lv<32> ap_const_lv32_1D5;
static const sc_lv<32> ap_const_lv32_1D6;
static const sc_lv<32> ap_const_lv32_1D7;
static const sc_lv<32> ap_const_lv32_1D8;
static const sc_lv<32> ap_const_lv32_1D9;
static const sc_lv<32> ap_const_lv32_1DA;
static const sc_lv<32> ap_const_lv32_1DB;
static const sc_lv<32> ap_const_lv32_1DC;
static const sc_lv<32> ap_const_lv32_1DD;
static const sc_lv<32> ap_const_lv32_1DE;
static const sc_lv<32> ap_const_lv32_1DF;
static const sc_lv<32> ap_const_lv32_1E0;
static const sc_lv<32> ap_const_lv32_1E1;
static const sc_lv<32> ap_const_lv32_1E2;
static const sc_lv<32> ap_const_lv32_1E3;
static const sc_lv<32> ap_const_lv32_1E4;
static const sc_lv<32> ap_const_lv32_1E5;
static const sc_lv<32> ap_const_lv32_1E6;
static const sc_lv<32> ap_const_lv32_1E7;
static const sc_lv<32> ap_const_lv32_1E8;
static const sc_lv<32> ap_const_lv32_1E9;
static const sc_lv<32> ap_const_lv32_1EA;
static const sc_lv<32> ap_const_lv32_1EB;
static const sc_lv<32> ap_const_lv32_1EC;
static const sc_lv<32> ap_const_lv32_1ED;
static const sc_lv<32> ap_const_lv32_1EE;
static const sc_lv<32> ap_const_lv32_1EF;
static const sc_lv<32> ap_const_lv32_1F0;
static const sc_lv<32> ap_const_lv32_1F1;
static const sc_lv<32> ap_const_lv32_1F2;
static const sc_lv<32> ap_const_lv32_1F3;
static const sc_lv<32> ap_const_lv32_1F4;
static const sc_lv<32> ap_const_lv32_1F5;
static const sc_lv<32> ap_const_lv32_1F6;
static const sc_lv<32> ap_const_lv32_1F7;
static const sc_lv<32> ap_const_lv32_1F8;
static const sc_lv<32> ap_const_lv32_1F9;
static const sc_lv<32> ap_const_lv32_1FA;
static const sc_lv<32> ap_const_lv32_1FB;
static const sc_lv<32> ap_const_lv32_1FC;
static const sc_lv<32> ap_const_lv32_1FD;
static const sc_lv<32> ap_const_lv32_1FE;
static const sc_lv<32> ap_const_lv32_1FF;
static const sc_lv<32> ap_const_lv32_200;
static const sc_lv<32> ap_const_lv32_201;
static const sc_lv<32> ap_const_lv32_202;
static const sc_lv<32> ap_const_lv32_203;
static const sc_lv<32> ap_const_lv32_204;
static const sc_lv<32> ap_const_lv32_205;
static const sc_lv<32> ap_const_lv32_206;
static const sc_lv<32> ap_const_lv32_207;
static const sc_lv<32> ap_const_lv32_208;
static const sc_lv<32> ap_const_lv32_209;
static const sc_lv<32> ap_const_lv32_20A;
static const sc_lv<32> ap_const_lv32_20B;
static const sc_lv<32> ap_const_lv32_20C;
static const sc_lv<32> ap_const_lv32_20D;
static const sc_lv<32> ap_const_lv32_20E;
static const sc_lv<32> ap_const_lv32_20F;
static const sc_lv<32> ap_const_lv32_210;
static const sc_lv<32> ap_const_lv32_211;
static const sc_lv<32> ap_const_lv32_212;
static const sc_lv<32> ap_const_lv32_213;
static const sc_lv<32> ap_const_lv32_214;
static const sc_lv<32> ap_const_lv32_215;
static const sc_lv<32> ap_const_lv32_216;
static const sc_lv<32> ap_const_lv32_217;
static const sc_lv<32> ap_const_lv32_218;
static const sc_lv<32> ap_const_lv32_219;
static const sc_lv<32> ap_const_lv32_21A;
static const sc_lv<32> ap_const_lv32_21B;
static const sc_lv<32> ap_const_lv32_21C;
static const sc_lv<32> ap_const_lv32_21D;
static const sc_lv<32> ap_const_lv32_21E;
static const sc_lv<32> ap_const_lv32_21F;
static const sc_lv<32> ap_const_lv32_220;
static const sc_lv<32> ap_const_lv32_221;
static const sc_lv<32> ap_const_lv32_222;
static const sc_lv<32> ap_const_lv32_223;
static const sc_lv<32> ap_const_lv32_224;
static const sc_lv<32> ap_const_lv32_225;
static const sc_lv<32> ap_const_lv32_226;
static const sc_lv<32> ap_const_lv32_227;
static const sc_lv<32> ap_const_lv32_228;
static const sc_lv<32> ap_const_lv32_229;
static const sc_lv<32> ap_const_lv32_22A;
static const sc_lv<32> ap_const_lv32_22B;
static const sc_lv<32> ap_const_lv32_22C;
static const sc_lv<32> ap_const_lv32_22E;
static const sc_lv<1> ap_const_lv1_1;
static const sc_lv<32> ap_const_lv32_233;
static const sc_lv<31> ap_const_lv31_0;
static const sc_lv<32> ap_const_lv32_101;
static const sc_lv<7> ap_const_lv7_0;
static const sc_lv<32> ap_const_lv32_22F;
static const sc_lv<32> ap_const_lv32_230;
static const sc_lv<32> ap_const_lv32_234;
static const sc_lv<32> ap_const_lv32_235;
static const sc_lv<32> ap_const_lv32_4;
static const sc_lv<32> ap_const_lv32_6;
static const sc_lv<32> ap_const_lv32_8;
static const sc_lv<32> ap_const_lv32_A;
static const sc_lv<32> ap_const_lv32_C;
static const sc_lv<32> ap_const_lv32_E;
static const sc_lv<32> ap_const_lv32_10;
static const sc_lv<32> ap_const_lv32_12;
static const sc_lv<32> ap_const_lv32_14;
static const sc_lv<32> ap_const_lv32_16;
static const sc_lv<32> ap_const_lv32_18;
static const sc_lv<32> ap_const_lv32_1A;
static const sc_lv<32> ap_const_lv32_1C;
static const sc_lv<32> ap_const_lv32_1E;
static const sc_lv<32> ap_const_lv32_20;
static const sc_lv<32> ap_const_lv32_22;
static const sc_lv<32> ap_const_lv32_24;
static const sc_lv<32> ap_const_lv32_26;
static const sc_lv<32> ap_const_lv32_28;
static const sc_lv<32> ap_const_lv32_2A;
static const sc_lv<32> ap_const_lv32_2C;
static const sc_lv<32> ap_const_lv32_2E;
static const sc_lv<32> ap_const_lv32_30;
static const sc_lv<32> ap_const_lv32_32;
static const sc_lv<32> ap_const_lv32_34;
static const sc_lv<32> ap_const_lv32_36;
static const sc_lv<32> ap_const_lv32_38;
static const sc_lv<32> ap_const_lv32_3A;
static const sc_lv<32> ap_const_lv32_3C;
static const sc_lv<32> ap_const_lv32_3E;
static const sc_lv<32> ap_const_lv32_40;
static const sc_lv<32> ap_const_lv32_42;
static const sc_lv<32> ap_const_lv32_44;
static const sc_lv<32> ap_const_lv32_46;
static const sc_lv<32> ap_const_lv32_48;
static const sc_lv<32> ap_const_lv32_4A;
static const sc_lv<32> ap_const_lv32_4C;
static const sc_lv<32> ap_const_lv32_4E;
static const sc_lv<32> ap_const_lv32_50;
static const sc_lv<32> ap_const_lv32_52;
static const sc_lv<32> ap_const_lv32_54;
static const sc_lv<32> ap_const_lv32_56;
static const sc_lv<32> ap_const_lv32_58;
static const sc_lv<32> ap_const_lv32_5A;
static const sc_lv<32> ap_const_lv32_5C;
static const sc_lv<32> ap_const_lv32_5E;
static const sc_lv<32> ap_const_lv32_60;
static const sc_lv<32> ap_const_lv32_62;
static const sc_lv<32> ap_const_lv32_64;
static const sc_lv<32> ap_const_lv32_66;
static const sc_lv<32> ap_const_lv32_68;
static const sc_lv<32> ap_const_lv32_6A;
static const sc_lv<32> ap_const_lv32_6C;
static const sc_lv<32> ap_const_lv32_6E;
static const sc_lv<32> ap_const_lv32_70;
static const sc_lv<32> ap_const_lv32_72;
static const sc_lv<32> ap_const_lv32_74;
static const sc_lv<32> ap_const_lv32_76;
static const sc_lv<32> ap_const_lv32_78;
static const sc_lv<32> ap_const_lv32_7A;
static const sc_lv<32> ap_const_lv32_7C;
static const sc_lv<32> ap_const_lv32_7E;
static const sc_lv<32> ap_const_lv32_80;
static const sc_lv<32> ap_const_lv32_82;
static const sc_lv<32> ap_const_lv32_84;
static const sc_lv<32> ap_const_lv32_86;
static const sc_lv<32> ap_const_lv32_88;
static const sc_lv<32> ap_const_lv32_8A;
static const sc_lv<32> ap_const_lv32_8C;
static const sc_lv<32> ap_const_lv32_8E;
static const sc_lv<32> ap_const_lv32_90;
static const sc_lv<32> ap_const_lv32_92;
static const sc_lv<32> ap_const_lv32_94;
static const sc_lv<32> ap_const_lv32_96;
static const sc_lv<32> ap_const_lv32_98;
static const sc_lv<32> ap_const_lv32_9A;
static const sc_lv<32> ap_const_lv32_9C;
static const sc_lv<32> ap_const_lv32_9E;
static const sc_lv<32> ap_const_lv32_A0;
static const sc_lv<32> ap_const_lv32_A2;
static const sc_lv<32> ap_const_lv32_A4;
static const sc_lv<32> ap_const_lv32_A6;
static const sc_lv<32> ap_const_lv32_A8;
static const sc_lv<32> ap_const_lv32_AA;
static const sc_lv<32> ap_const_lv32_AC;
static const sc_lv<32> ap_const_lv32_AE;
static const sc_lv<32> ap_const_lv32_B0;
static const sc_lv<32> ap_const_lv32_B2;
static const sc_lv<32> ap_const_lv32_B4;
static const sc_lv<32> ap_const_lv32_B6;
static const sc_lv<32> ap_const_lv32_B8;
static const sc_lv<32> ap_const_lv32_BA;
static const sc_lv<32> ap_const_lv32_BC;
static const sc_lv<32> ap_const_lv32_BE;
static const sc_lv<32> ap_const_lv32_C0;
static const sc_lv<32> ap_const_lv32_C2;
static const sc_lv<32> ap_const_lv32_C4;
static const sc_lv<32> ap_const_lv32_C6;
static const sc_lv<32> ap_const_lv32_C8;
static const sc_lv<32> ap_const_lv32_CA;
static const sc_lv<32> ap_const_lv32_CC;
static const sc_lv<32> ap_const_lv32_CE;
static const sc_lv<32> ap_const_lv32_D0;
static const sc_lv<32> ap_const_lv32_D2;
static const sc_lv<32> ap_const_lv32_D4;
static const sc_lv<32> ap_const_lv32_D6;
static const sc_lv<32> ap_const_lv32_D8;
static const sc_lv<32> ap_const_lv32_DA;
static const sc_lv<32> ap_const_lv32_DC;
static const sc_lv<32> ap_const_lv32_DE;
static const sc_lv<32> ap_const_lv32_E0;
static const sc_lv<32> ap_const_lv32_E2;
static const sc_lv<32> ap_const_lv32_E4;
static const sc_lv<32> ap_const_lv32_E6;
static const sc_lv<32> ap_const_lv32_E8;
static const sc_lv<32> ap_const_lv32_EA;
static const sc_lv<32> ap_const_lv32_EC;
static const sc_lv<32> ap_const_lv32_EE;
static const sc_lv<32> ap_const_lv32_F0;
static const sc_lv<32> ap_const_lv32_F2;
static const sc_lv<32> ap_const_lv32_F4;
static const sc_lv<32> ap_const_lv32_F6;
static const sc_lv<32> ap_const_lv32_F8;
static const sc_lv<32> ap_const_lv32_FA;
static const sc_lv<32> ap_const_lv32_FC;
static const sc_lv<32> ap_const_lv32_FE;
static const sc_lv<32> ap_const_lv32_100;
static const sc_lv<8> ap_const_lv8_0;
static const sc_lv<8> ap_const_lv8_1;
static const sc_lv<8> ap_const_lv8_2;
static const sc_lv<8> ap_const_lv8_3;
static const sc_lv<8> ap_const_lv8_4;
static const sc_lv<8> ap_const_lv8_5;
static const sc_lv<8> ap_const_lv8_6;
static const sc_lv<8> ap_const_lv8_7;
static const sc_lv<8> ap_const_lv8_8;
static const sc_lv<8> ap_const_lv8_9;
static const sc_lv<8> ap_const_lv8_A;
static const sc_lv<8> ap_const_lv8_B;
static const sc_lv<8> ap_const_lv8_C;
static const sc_lv<8> ap_const_lv8_D;
static const sc_lv<8> ap_const_lv8_E;
static const sc_lv<8> ap_const_lv8_F;
static const sc_lv<8> ap_const_lv8_10;
static const sc_lv<8> ap_const_lv8_11;
static const sc_lv<8> ap_const_lv8_12;
static const sc_lv<8> ap_const_lv8_13;
static const sc_lv<8> ap_const_lv8_14;
static const sc_lv<8> ap_const_lv8_15;
static const sc_lv<8> ap_const_lv8_16;
static const sc_lv<8> ap_const_lv8_17;
static const sc_lv<8> ap_const_lv8_18;
static const sc_lv<8> ap_const_lv8_19;
static const sc_lv<8> ap_const_lv8_1A;
static const sc_lv<8> ap_const_lv8_1B;
static const sc_lv<8> ap_const_lv8_1C;
static const sc_lv<8> ap_const_lv8_1D;
static const sc_lv<8> ap_const_lv8_1E;
static const sc_lv<8> ap_const_lv8_1F;
static const sc_lv<8> ap_const_lv8_20;
static const sc_lv<8> ap_const_lv8_21;
static const sc_lv<8> ap_const_lv8_22;
static const sc_lv<8> ap_const_lv8_23;
static const sc_lv<8> ap_const_lv8_24;
static const sc_lv<8> ap_const_lv8_25;
static
|
const sc_lv<8> ap_const_lv8_26;
static const sc_lv<8> ap_const_lv8_27;
static const sc_lv<8> ap_const_lv8_28;
static const sc_lv<8> ap_const_lv8_29;
static const sc_lv<8> ap_const_lv8_2A;
static const sc_lv<8> ap_const_lv8_2B;
static const sc_lv<8> ap_const_lv8_2C;
static const sc_lv<8> ap_const_lv8_2D;
static const sc_lv<8> ap_const_lv8_2E;
static const sc_lv<8> ap_const_lv8_2F;
static const sc_lv<8> ap_const_lv8_30;
static const sc_lv<8> ap_const_lv8_31;
static const sc_lv<8> ap_const_lv8_32;
static const sc_lv<8> ap_const_lv8_33;
static const sc_lv<8> ap_const_lv8_34;
static const sc_lv<8> ap_const_lv8_35;
static const sc_lv<8> ap_const_lv8_36;
static const sc_lv<8> ap_const_lv8_37;
static const sc_lv<8> ap_const_lv8_38;
static const sc_lv<8> ap_const_lv8_39;
static const sc_lv<8> ap_const_lv8_3A;
static const sc_lv<8> ap_const_lv8_3B;
static const sc_lv<8> ap_const_lv8_3C;
static const sc_lv<8> ap_const_lv8_3D;
static const sc_lv<8> ap_const_lv8_3E;
static const sc_lv<8> ap_const_lv8_3F;
static const sc_lv<8> ap_const_lv8_40;
static const sc_lv<8> ap_const_lv8_41;
static const sc_lv<8> ap_const_lv8_42;
static const sc_lv<8> ap_const_lv8_43;
static const sc_lv<8> ap_const_lv8_44;
static const sc_lv<8> ap_const_lv8_45;
static const sc_lv<8> ap_const_lv8_46;
static const sc_lv<8> ap_const_lv8_47;
static const sc_lv<8> ap_const_lv8_48;
static const sc_lv<8> ap_const_lv8_49;
static const sc_lv<8> ap_const_lv8_4A;
static const sc_lv<8> ap_const_lv8_4B;
static const sc_lv<8> ap_const_lv8_4C;
static const sc_lv<8> ap_const_lv8_4D;
static const sc_lv<8> ap_const_lv8_4E;
static const sc_lv<8> ap_const_lv8_4F;
static const sc_lv<8> ap_const_lv8_50;
static const sc_lv<8> ap_const_lv8_51;
static const sc_lv<8> ap_const_lv8_52;
static const sc_lv<8> ap_const_lv8_53;
static const sc_lv<8> ap_const_lv8_54;
static const sc_lv<8> ap_const_lv8_55;
static const sc_lv<8> ap_const_lv8_56;
static const sc_lv<8> ap_const_lv8_57;
static const sc_lv<8> ap_const_lv8_58;
static const sc_lv<8> ap_const_lv8_59;
static const sc_lv<8> ap_const_lv8_5A;
static const sc_lv<8> ap_const_lv8_5B;
static const sc_lv<8> ap_const_lv8_5C;
static const sc_lv<8> ap_const_lv8_5D;
static const sc_lv<8> ap_const_lv8_5E;
static const sc_lv<8> ap_const_lv8_5F;
static const sc_lv<8> ap_const_lv8_60;
static const sc_lv<8> ap_const_lv8_61;
static const sc_lv<8> ap_const_lv8_62;
static const sc_lv<8> ap_const_lv8_63;
static const sc_lv<8> ap_const_lv8_64;
static const sc_lv<8> ap_const_lv8_65;
static const sc_lv<8> ap_const_lv8_66;
static const sc_lv<8> ap_const_lv8_67;
static const sc_lv<8> ap_const_lv8_68;
static const sc_lv<8> ap_const_lv8_69;
static const sc_lv<8> ap_const_lv8_6A;
static const sc_lv<8> ap_const_lv8_6B;
static const sc_lv<8> ap_const_lv8_6C;
static const sc_lv<8> ap_const_lv8_6D;
static const sc_lv<8> ap_const_lv8_6E;
static const sc_lv<8> ap_const_lv8_6F;
static const sc_lv<8> ap_const_lv8_70;
static const sc_lv<8> ap_const_lv8_71;
static const sc_lv<8> ap_const_lv8_72;
static const sc_lv<8> ap_const_lv8_73;
static const sc_lv<8> ap_const_lv8_74;
static const sc_lv<8> ap_const_lv8_75;
static const sc_lv<8> ap_const_lv8_76;
static const sc_lv<8> ap_const_lv8_77;
static const sc_lv<8> ap_const_lv8_78;
static const sc_lv<8> ap_const_lv8_79;
static const sc_lv<8> ap_const_lv8_7A;
static const sc_lv<8> ap_const_lv8_7B;
static const sc_lv<8> ap_const_lv8_7C;
static const sc_lv<8> ap_const_lv8_7D;
static const sc_lv<8> ap_const_lv8_7E;
static const sc_lv<8> ap_const_lv8_7F;
static const sc_lv<64> ap_const_lv64_0;
static const sc_lv<64> ap_const_lv64_1;
static const sc_lv<64> ap_const_lv64_2;
static const sc_lv<64> ap_const_lv64_3;
static const sc_lv<64> ap_const_lv64_4;
static const sc_lv<64> ap_const_lv64_5;
static const sc_lv<64> ap_const_lv64_6;
static const sc_lv<64> ap_const_lv64_7;
static const sc_lv<64> ap_const_lv64_8;
static const sc_lv<64> ap_const_lv64_9;
static const sc_lv<64> ap_const_lv64_A;
static const sc_lv<64> ap_const_lv64_B;
static const sc_lv<64> ap_const_lv64_C;
static const sc_lv<64> ap_const_lv64_D;
static const sc_lv<64> ap_const_lv64_E;
static const sc_lv<64> ap_const_lv64_F;
static const sc_lv<64> ap_const_lv64_10;
static const sc_lv<64> ap_const_lv64_11;
static const sc_lv<64> ap_const_lv64_12;
static const sc_lv<64> ap_const_lv64_13;
static const sc_lv<64> ap_const_lv64_14;
static const sc_lv<64> ap_const_lv64_15;
static const sc_lv<64> ap_const_lv64_16;
static const sc_lv<64> ap_const_lv64_17;
static const sc_lv<64> ap_const_lv64_18;
static const sc_lv<64> ap_const_lv64_19;
static const sc_lv<64> ap_const_lv64_1A;
static const sc_lv<64> ap_const_lv64_1B;
static const sc_lv<64> ap_const_lv64_1C;
static const sc_lv<64> ap_const_lv64_1D;
static const sc_lv<64> ap_const_lv64_1E;
static const sc_lv<64> ap_const_lv64_1F;
static const sc_lv<64> ap_const_lv64_20;
static const sc_lv<64> ap_const_lv64_21;
static const sc_lv<64> ap_const_lv64_22;
static const sc_lv<64> ap_const_lv64_23;
static const sc_lv<64> ap_const_lv64_24;
static const sc_lv<64> ap_const_lv64_25;
static const sc_lv<64> ap_const_lv64_26;
static const sc_lv<64> ap_const_lv64_27;
static const sc_lv<64> ap_const_lv64_28;
static const sc_lv<64> ap_const_lv64_29;
static const sc_lv<64> ap_const_lv64_2A;
static const sc_lv<64> ap_const_lv64_2B;
static const sc_lv<64> ap_const_lv64_2C;
static const sc_lv<64> ap_const_lv64_2D;
static const sc_lv<64> ap_const_lv64_2E;
static const sc_lv<64> ap_const_lv64_2F;
static const sc_lv<64> ap_const_lv64_30;
static const sc_lv<64> ap_const_lv64_31;
static const sc_lv<64> ap_const_lv64_32;
static const sc_lv<64> ap_const_lv64_33;
static const sc_lv<64> ap_const_lv64_34;
static const sc_lv<64> ap_const_lv64_35;
static const sc_lv<64> ap_const_lv64_36;
static const sc_lv<64> ap_const_lv64_37;
static const sc_lv<64> ap_const_lv64_38;
static const sc_lv<64> ap_const_lv64_39;
static const sc_lv<64> ap_const_lv64_3A;
static const sc_lv<64> ap_const_lv64_3B;
static const sc_lv<64> ap_const_lv64_3C;
static const sc_lv<64> ap_const_lv64_3D;
static const sc_lv<64> ap_const_lv64_3E;
static const sc_lv<64> ap_const_lv64_3F;
static const sc_lv<64> ap_const_lv64_40;
static const sc_lv<64> ap_const_lv64_41;
static const sc_lv<64> ap_const_lv64_42;
static const sc_lv<64> ap_const_lv64_43;
static const sc_lv<64> ap_const_lv64_44;
static const sc_lv<64> ap_const_lv64_45;
static const sc_lv<64> ap_const_lv64_46;
static const sc_lv<64> ap_const_lv64_47;
static const sc_lv<64> ap_const_lv64_48;
static const sc_lv<64> ap_const_lv64_49;
static const sc_lv<64> ap_const_lv64_4A;
static const sc_lv<64> ap_const_lv64_4B;
static const sc_lv<64> ap_const_lv64_4C;
static const sc_lv<64> ap_const_lv64_4D;
static const sc_lv<64> ap_const_lv64_4E;
static const sc_lv<64> ap_const_lv64_4F;
static const sc_lv<64> ap_const_lv64_50;
static const sc_lv<64> ap_const_lv64_51;
static const sc_lv<64> ap_const_lv64_52;
static const sc_lv<64> ap_const_lv64_53;
static const sc_lv<64> ap_const_lv64_54;
static const sc_lv<64> ap_const_lv64_55;
static const sc_lv<64> ap_const_lv64_56;
static const sc_lv<64> ap_const_lv64_57;
static const sc_lv<64> ap_const_lv64_58;
static const sc_lv<64> ap_const_lv64_59;
static const sc_lv<64> ap_const_lv64_5A;
static const sc_lv<64> ap_const_lv64_5B;
static const sc_lv<64> ap_const_lv64_5C;
static const sc_lv<64> ap_const_lv64_5D;
static const sc_lv<64> ap_const_lv64_5E;
static const sc_lv<64> ap_const_lv64_5F;
static const sc_lv<64> ap_const_lv64_60;
static const sc_lv<64> ap_const_lv64_61;
static const sc_lv<64> ap_const_lv64_62;
static const sc_lv<64> ap_const_lv64_63;
static const sc_lv<64> ap_const_lv64_64;
static const sc_lv<64> ap_const_lv64_65;
static const sc_lv<64> ap_const_lv64_66;
static const sc_lv<64> ap_const_lv64_67;
static const sc_lv<64> ap_const_lv64_68;
static const sc_lv<64> ap_const_lv64_69;
static const sc_lv<64> ap_const_lv64_6A;
static const sc_lv<64> ap_const_lv64_6B;
static const sc_lv<64> ap_const_lv64_6C;
static const sc_lv<64> ap_const_lv64_6D;
static const sc_lv<64> ap_const_lv64_6E;
static const sc_lv<64> ap_const_lv64_6F;
static const sc_lv<64> ap_const_lv64_70;
static const sc_lv<64> ap_const_lv64_71;
static const sc_lv<64> ap_const_lv64_72;
static const sc_lv<64> ap_const_lv64_73;
static const sc_lv<64> ap_const_lv64_74;
static const sc_lv<64> ap_const_lv64_75;
static const sc_lv<64> ap_const_lv64_76;
static const sc_lv<64> ap_const_lv64_77;
static const sc_lv<64> ap_const_lv64_78;
static const sc_lv<64> ap_const_lv64_79;
static const sc_lv<64> ap_const_lv64_7A;
static const sc_lv<64> ap_const_lv64_7B;
static const sc_lv<64> ap_const_lv64_7C;
static const sc_lv<64> ap_const_lv64_7D;
static const sc_lv<64> ap_const_lv64_7E;
static const sc_lv<64> ap_const_lv64_7F;
static const sc_lv<64> ap_const_lv64_80;
static const sc_lv<64> ap_const_lv64_81;
static const sc_lv<64> ap_const_lv64_82;
static const sc_lv<64> ap_const_lv64_83;
static const sc_lv<64> ap_const_lv64_84;
static const sc_lv<64> ap_const_lv64_85;
static const sc_lv<64> ap_const_lv64_86;
static const sc_lv<64> ap_const_lv64_87;
static const sc_lv<64> ap_const_lv64_88;
static const sc_lv<64> ap_const_lv64_89;
static const sc_lv<64> ap_const_lv64_8A;
static const sc_lv<64> ap_const_lv64_8B;
static const sc_lv<64> ap_const_lv64_8C;
static const sc_lv<64> ap_const_lv64_8D;
static const sc_lv<64> ap_const_lv64_8E;
static const sc_lv<64> ap_const_lv64_8F;
static const sc_lv<64> ap_const_lv64_90;
static const sc_lv<64> ap_const_lv64_91;
static const sc_lv<64> ap_const_lv64_92;
static const sc_lv<64> ap_const_lv64_93;
static const sc_lv<64> ap_const_lv64_94;
static const sc_lv<64> ap_const_lv64_95;
static const sc_lv<64> ap_const_lv64_96;
static const sc_lv<64> ap_const_lv64_97;
static const sc_lv<64> ap_const_lv64_98;
static const sc_lv<64> ap_const_lv64_99;
static const sc_lv<64> ap_const_lv64_9A;
static const sc_lv<64> ap_const_lv64_9B;
static const sc_lv<64> ap_const_lv64_9C;
static const sc_lv<64> ap_const_lv64_9D;
static const sc_lv<64> ap_const_lv64_9E;
static const sc_lv<64> ap_const_lv64_9F;
static const sc_lv<64> ap_const_lv64_A0;
static const sc_lv<64> ap_const_lv64_A1;
static const sc_lv<64> ap_const_lv64_A2;
static const sc_lv<64> ap_const_lv64_A3;
static const sc_lv<64> ap_const_lv64_A4;
static const sc_lv<64> ap_const_lv64_A5;
static const sc_lv<64> ap_const_lv64_A6;
static const sc_lv<64> ap_const_lv64_A7;
static const sc_lv<64> ap_const_lv64_A8;
static const sc_lv<64> ap_const_lv64_A9;
static const sc_lv<64> ap_const_lv64_AA;
static const sc_lv<64> ap_const_lv64_AB;
static const sc_lv<64> ap_const_lv64_AC;
static const sc_lv<64> ap_const_lv64_AD;
static const sc_lv<64> ap_const_lv64_AE;
static const sc_lv<64> ap_const_lv64_AF;
static const sc_lv<64> ap_const_lv64_B0;
static const sc_lv<64> ap_const_lv64_B1;
static const sc_lv<64> ap_const_lv64_B2;
static const sc_lv<64> ap_const_lv64_B3;
static const sc_lv<64> ap_const_lv64_B4;
static const sc_lv<64> ap_const_lv64_B5;
static const sc_lv<64> ap_const_lv64_B6;
static const sc_lv<64> ap_const_lv64_B7;
static const sc_lv<64> ap_const_lv64_B8;
static const sc_lv<64> ap_const_lv64_B9;
static const sc_lv<64> ap_const_lv64_BA;
static const sc_lv<64> ap_const_lv64_BB;
static const sc_lv<64> ap_const_lv64_BC;
static const sc_lv<64> ap_const_lv64_BD;
static const sc_lv<64> ap_const_lv64_BE;
static const sc_lv<64> ap_const_lv64_BF;
static const sc_lv<64> ap_const_lv64_C0;
static const sc_lv<64> ap_const_lv64_C1;
static const sc_lv<64> ap_const_lv64_C2;
static const sc_lv<64> ap_const_lv64_C3;
static const sc_lv<64> ap_const_lv64_C4;
static const sc_lv<64> ap_const_lv64_C5;
static const sc_lv<64> ap_const_lv64_C6;
static const sc_lv<64> ap_const_lv64_C7;
static const sc_lv<64> ap_const_lv64_C8;
static const sc_lv<64> ap_const_lv64_C9;
static const sc_lv<64> ap_const_lv64_CA;
static const sc_lv<64> ap_const_lv64_CB;
static const sc_lv<64> ap_const_lv64_CC;
static const sc_lv<64> ap_const_lv64_CD;
static const sc_lv<64> ap_const_lv64_CE;
static const sc_lv<64> ap_const_lv64_CF;
static const sc_lv<64> ap_const_lv64_D0;
static const sc_lv<64> ap_const_lv64_D1;
static const sc_lv<64> ap_const_lv64_D2;
static const sc_lv<64> ap_const_lv64_D3;
static const sc_lv<64> ap_const_lv64_D4;
static const sc_lv<64> ap_const_lv64_D5;
static const sc_lv<64> ap_const_lv64_D6;
static const sc_lv<64> ap_const_lv64_D7;
static const sc_lv<64> ap_const_lv64_D8;
static const sc_lv<64> ap_const_lv64_D9;
static const sc_lv<64> ap_const_lv64_DA;
static const sc_lv<64> ap_const_lv64_DB;
static const sc_lv<64> ap_const_lv64_DC;
static const sc_lv<64> ap_const_lv64_DD;
static const sc_lv<64> ap_const_lv64_DE;
static const sc_lv<64> ap_const_lv64_DF;
static const sc_lv<64> ap_const_lv64_E0;
static const sc_lv<64> ap_const_lv64_E1;
static const sc_lv<64> ap_const_lv64_E2;
static const sc_lv<64> ap_const_lv64_E3;
static const sc_lv<64> ap_const_lv64_E4;
static const sc_lv<64> ap_const_lv64_E5;
static const sc_lv<64> ap_const_lv64_E6;
static const sc_lv<64> ap_const_lv64_E7;
static const sc_lv<64> ap_const_lv64_E8;
static const sc_lv<64> ap_const_lv64_E9;
static const sc_lv<64> ap_const_lv64_EA;
static const sc_lv<64> ap_const_lv64_EB;
static const sc_lv<64> ap_const_lv64_EC;
static const sc_lv<64> ap_const_lv64_ED;
static const sc_lv<64> ap_const_lv64_EE;
static const sc_lv<64> ap_const_lv64_EF;
static const sc_lv<64> ap_const_lv64_F0;
static const sc_lv<64> ap_const_lv64_F1;
static const sc_lv<64> ap_const_lv64_F2;
static const sc_lv<64> ap_const_lv64_F3;
static const sc_lv<64> ap_const_lv64_F4;
static const sc_lv<64> ap_const_lv64_F5;
static const sc_lv<64> ap_const_lv64_F6;
static const sc_lv<64> ap_const_lv64_F7;
static const sc_lv<64> ap_const_lv64_F8;
static const sc_lv<64> ap_const_lv64_F9;
static const sc_lv<64> ap_const_lv64_FA;
static const sc_lv<64> ap_const_lv64_FB;
static const sc_lv<64> ap_const_lv64_FC;
static const sc_lv<64> ap_const_lv64_FD;
static const sc_lv<64> ap_const_lv64_FE;
static const sc_lv<64> ap_const_lv64_FF;
static const sc_lv<64> ap_const_lv64_100;
static const sc_lv<64> ap_const_lv64_101;
static const sc_lv<64> ap_const_lv64_102;
static const sc_lv<64> ap_const_lv64_103;
static const sc_lv<64> ap_const_lv64_104;
static const sc_lv<64> ap_const_lv64_105;
static const sc_lv<64> ap_const_lv64_106;
static const sc_lv<64> ap_const_lv64_107;
static const sc_lv<64> ap_const_lv64_108;
static const sc_lv<64> ap_const_lv64_109;
static const sc_lv<64> ap_const_lv64_10A;
static const sc_lv<64> ap_const_lv64_10B;
static const sc_lv<64> ap_const_lv64_10C;
static const sc_lv<64> ap_const_lv64_10D;
static const sc_lv<64> ap_const_lv64_10E;
static const sc_lv<64> ap_const_lv64_10F;
static const sc_lv<64> ap_const_lv64_110;
static const sc_lv<64> ap_const_lv64_111;
static const sc_lv<64> ap_const_lv64_112;
static const sc_lv<64> ap_const_lv64_113;
static const sc_lv<64> ap_const_lv64_114;
static const sc_lv<64> ap_const_lv64_115;
static const sc_lv<64> ap_const_lv64_116;
static const sc_lv<64> ap_const_lv64_117;
static const sc_lv<64> ap_const_lv64_118;
static const sc_lv<64> ap_const_lv64_119;
static const sc_lv<64> ap_const_lv64_11A;
static const sc_lv<64> ap_const_lv64_11B;
static const sc_lv<64> ap_const_lv64_11C;
static const sc_lv<64> ap_const_lv64_11D;
static const sc_lv<64> ap_const_lv64_11E;
static const sc_lv<64> ap_const_lv64_11F;
static const sc_lv<64> ap_const_lv64_120;
static const sc_lv<64> ap_const_lv64_121;
static const sc_lv<64> ap_const_lv64_122;
static const sc_lv<64> ap_const_lv64_123;
static const sc_lv<64> ap_const_lv64_124;
static const sc_lv<64> ap_const_lv64_125;
static const sc_lv<64> ap_const_lv64_126;
static const sc_lv<64> ap_const_lv64_127;
static const sc_lv<64> ap_const_lv64_128;
static const sc_lv<64> ap_const_lv64_129;
static const sc_lv<64> ap_const_lv64_12A;
static const sc_lv<64> ap_const_lv64_12B;
static const sc_lv<32> ap_const_lv32_22D;
static const sc_lv<32> ap_const_lv32_236;
static const sc_lv<32> ap_const_lv32_231;
static const sc_lv<6> ap_const_lv6_0;
static const sc_lv<25> ap_const_lv25_0;
static const sc_lv<31> ap_const_lv31_1;
static const sc_lv<7> ap_const_lv7_40;
static const sc_lv<7> ap_const_lv7_1;
static const bool ap_const_boolean_1;
// Thread declarations
void thread_ap_var_for_const0();
void thread_ap_clk_no_reset_();
void thread_ap_CS_fsm_state1();
void thread_ap_CS_fsm_state10();
void thread_ap_CS_fsm_state100();
void thread_ap_CS_fsm_state101();
void thread_ap_CS_fsm_state102();
void thread_ap_CS_fsm_state103();
void thread_ap_CS_fsm_state104();
void thread_ap_CS_fsm_state105();
void thread_ap_CS_fsm_state106();
void thread_ap_CS_fsm_state107();
void thread_ap_CS_fsm_state108();
void thread_ap_CS_fsm_state109();
void thread_ap_CS_fsm_state11();
void thread_ap_CS_fsm_state110();
void thread_ap_CS_fsm_state111();
void thread_ap_CS_fsm_state112();
void thread_ap_CS_fsm_state113();
void thread_ap_CS_fsm_state114();
void thread_ap_CS_fsm_state115();
void thread_ap_CS_fsm_state116();
void thread_ap_CS_fsm_state117();
void thread_ap_CS_fsm_state118();
void thread_ap_CS_fsm_state119();
void thread_ap_CS_fsm_state12();
void thread_ap_CS_fsm_state120();
void thread_ap_CS_fsm_state121();
void thread_ap_CS_fsm_state122();
void thread_ap_CS_fsm_state123();
void thread_ap_CS_fsm_state124();
void thread_ap_CS_fsm_state125();
void thread_ap_CS_fsm_state126();
void thread_ap_CS_fsm_state127();
void thread_ap_CS_fsm_state128();
void thread_ap_CS_fsm_state129();
void thread_ap_CS_fsm_state13();
void thread_ap_CS_fsm_state130();
void thread_ap_CS_fsm_state131();
void thread_ap_CS_fsm_state132();
void thread_ap_CS_fsm_state133();
void thread_ap_CS_fsm_state134();
void thread_ap_CS_fsm_state135();
void thread_ap_CS_fsm_state136();
void thread_ap_CS_fsm_state137();
void thread_ap_CS_fsm_state138();
void thread_ap_CS_fsm_state139();
void thread_ap_CS_fsm_state14();
void thread_ap_CS_fsm_state140();
void thread_ap_CS_fsm_state141();
void thread_ap_CS_fsm_state142();
void thread_ap_CS_fsm_state143();
void thread_ap_CS_fsm_state144();
void thread_ap_CS_fsm_state145();
void thread_ap_CS_fsm_state146();
void thread_ap_CS_fsm_state147();
void thread_ap_CS_fsm_state148();
void thread_ap_CS_fsm_state149
|
();
void thread_ap_CS_fsm_state15();
void thread_ap_CS_fsm_state150();
void thread_ap_CS_fsm_state151();
void thread_ap_CS_fsm_state152();
void thread_ap_CS_fsm_state153();
void thread_ap_CS_fsm_state154();
void thread_ap_CS_fsm_state155();
void thread_ap_CS_fsm_state156();
void thread_ap_CS_fsm_state157();
void thread_ap_CS_fsm_state158();
void thread_ap_CS_fsm_state159();
void thread_ap_CS_fsm_state16();
void thread_ap_CS_fsm_state160();
void thread_ap_CS_fsm_state161();
void thread_ap_CS_fsm_state162();
void thread_ap_CS_fsm_state163();
void thread_ap_CS_fsm_state164();
void thread_ap_CS_fsm_state165();
void thread_ap_CS_fsm_state166();
void thread_ap_CS_fsm_state167();
void thread_ap_CS_fsm_state168();
void thread_ap_CS_fsm_state169();
void thread_ap_CS_fsm_state17();
void thread_ap_CS_fsm_state170();
void thread_ap_CS_fsm_state171();
void thread_ap_CS_fsm_state172();
void thread_ap_CS_fsm_state173();
void thread_ap_CS_fsm_state174();
void thread_ap_CS_fsm_state175();
void thread_ap_CS_fsm_state176();
void thread_ap_CS_fsm_state177();
void thread_ap_CS_fsm_state178();
void thread_ap_CS_fsm_state179();
void thread_ap_CS_fsm_state18();
void thread_ap_CS_fsm_state180();
void thread_ap_CS_fsm_state181();
void thread_ap_CS_fsm_state182();
void thread_ap_CS_fsm_state183();
void thread_ap_CS_fsm_state184();
void thread_ap_CS_fsm_state185();
void thread_ap_CS_fsm_state186();
void thread_ap_CS_fsm_state187();
void thread_ap_CS_fsm_state188();
void thread_ap_CS_fsm_state189();
void thread_ap_CS_fsm_state19();
void thread_ap_CS_fsm_state190();
void thread_ap_CS_fsm_state191();
void thread_ap_CS_fsm_state192();
void thread_ap_CS_fsm_state193();
void thread_ap_CS_fsm_state194();
void thread_ap_CS_fsm_state195();
void thread_ap_CS_fsm_state196();
void thread_ap_CS_fsm_state197();
void thread_ap_CS_fsm_state198();
void thread_ap_CS_fsm_state199();
void thread_ap_CS_fsm_state2();
void thread_ap_CS_fsm_state20();
void thread_ap_CS_fsm_state200();
void thread_ap_CS_fsm_state201();
void thread_ap_CS_fsm_state202();
void thread_ap_CS_fsm_state203();
void thread_ap_CS_fsm_state204();
void thread_ap_CS_fsm_state205();
void thread_ap_CS_fsm_state206();
void thread_ap_CS_fsm_state207();
void thread_ap_CS_fsm_state208();
void thread_ap_CS_fsm_state209();
void thread_ap_CS_fsm_state21();
void thread_ap_CS_fsm_state210();
void thread_ap_CS_fsm_state211();
void thread_ap_CS_fsm_state212();
void thread_ap_CS_fsm_state213();
void thread_ap_CS_fsm_state214();
void thread_ap_CS_fsm_state215();
void thread_ap_CS_fsm_state216();
void thread_ap_CS_fsm_state217();
void thread_ap_CS_fsm_state218();
void thread_ap_CS_fsm_state219();
void thread_ap_CS_fsm_state22();
void thread_ap_CS_fsm_state220();
void thread_ap_CS_fsm_state221();
void thread_ap_CS_fsm_state222();
void thread_ap_CS_fsm_state223();
void thread_ap_CS_fsm_state224();
void thread_ap_CS_fsm_state225();
void thread_ap_CS_fsm_state226();
void thread_ap_CS_fsm_state227();
void thread_ap_CS_fsm_state228();
void thread_ap_CS_fsm_state229();
void thread_ap_CS_fsm_state23();
void thread_ap_CS_fsm_state230();
void thread_ap_CS_fsm_state231();
void thread_ap_CS_fsm_state232();
void thread_ap_CS_fsm_state233();
void thread_ap_CS_fsm_state234();
void thread_ap_CS_fsm_state235();
void thread_ap_CS_fsm_state236();
void thread_ap_CS_fsm_state237();
void thread_ap_CS_fsm_state238();
void thread_ap_CS_fsm_state239();
void thread_ap_CS_fsm_state24();
void thread_ap_CS_fsm_state240();
void thread_ap_CS_fsm_state241();
void thread_ap_CS_fsm_state242();
void thread_ap_CS_fsm_state243();
void thread_ap_CS_fsm_state244();
void thread_ap_CS_fsm_state245();
void thread_ap_CS_fsm_state246();
void thread_ap_CS_fsm_state247();
void thread_ap_CS_fsm_state248();
void thread_ap_CS_fsm_state249();
void thread_ap_CS_fsm_state25();
void thread_ap_CS_fsm_state250();
void thread_ap_CS_fsm_state251();
void thread_ap_CS_fsm_state252();
void thread_ap_CS_fsm_state253();
void thread_ap_CS_fsm_state254();
void thread_ap_CS_fsm_state255();
void thread_ap_CS_fsm_state256();
void thread_ap_CS_fsm_state257();
void thread_ap_CS_fsm_state258();
void thread_ap_CS_fsm_state259();
void thread_ap_CS_fsm_state26();
void thread_ap_CS_fsm_state260();
void thread_ap_CS_fsm_state261();
void thread_ap_CS_fsm_state262();
void thread_ap_CS_fsm_state263();
void thread_ap_CS_fsm_state264();
void thread_ap_CS_fsm_state265();
void thread_ap_CS_fsm_state266();
void thread_ap_CS_fsm_state267();
void thread_ap_CS_fsm_state268();
void thread_ap_CS_fsm_state269();
void thread_ap_CS_fsm_state27();
void thread_ap_CS_fsm_state270();
void thread_ap_CS_fsm_state271();
void thread_ap_CS_fsm_state272();
void thread_ap_CS_fsm_state273();
void thread_ap_CS_fsm_state274();
void thread_ap_CS_fsm_state275();
void thread_ap_CS_fsm_state276();
void thread_ap_CS_fsm_state277();
void thread_ap_CS_fsm_state278();
void thread_ap_CS_fsm_state279();
void thread_ap_CS_fsm_state28();
void thread_ap_CS_fsm_state280();
void thread_ap_CS_fsm_state281();
void thread_ap_CS_fsm_state282();
void thread_ap_CS_fsm_state283();
void thread_ap_CS_fsm_state284();
void thread_ap_CS_fsm_state285();
void thread_ap_CS_fsm_state286();
void thread_ap_CS_fsm_state287();
void thread_ap_CS_fsm_state288();
void thread_ap_CS_fsm_state289();
void thread_ap_CS_fsm_state29();
void thread_ap_CS_fsm_state290();
void thread_ap_CS_fsm_state291();
void thread_ap_CS_fsm_state292();
void thread_ap_CS_fsm_state293();
void thread_ap_CS_fsm_state294();
void thread_ap_CS_fsm_state295();
void thread_ap_CS_fsm_state296();
void thread_ap_CS_fsm_state297();
void thread_ap_CS_fsm_state298();
void thread_ap_CS_fsm_state299();
void thread_ap_CS_fsm_state3();
void thread_ap_CS_fsm_state30();
void thread_ap_CS_fsm_state300();
void thread_ap_CS_fsm_state301();
void thread_ap_CS_fsm_state302();
void thread_ap_CS_fsm_state303();
void thread_ap_CS_fsm_state304();
void thread_ap_CS_fsm_state305();
void thread_ap_CS_fsm_state306();
void thread_ap_CS_fsm_state307();
void thread_ap_CS_fsm_state308();
void thread_ap_CS_fsm_state309();
void thread_ap_CS_fsm_state31();
void thread_ap_CS_fsm_state310();
void thread_ap_CS_fsm_state311();
void thread_ap_CS_fsm_state312();
void thread_ap_CS_fsm_state313();
void thread_ap_CS_fsm_state314();
void thread_ap_CS_fsm_state315();
void thread_ap_CS_fsm_state316();
void thread_ap_CS_fsm_state317();
void thread_ap_CS_fsm_state318();
void thread_ap_CS_fsm_state319();
void thread_ap_CS_fsm_state32();
void thread_ap_CS_fsm_state320();
void thread_ap_CS_fsm_state321();
void thread_ap_CS_fsm_state322();
void thread_ap_CS_fsm_state323();
void thread_ap_CS_fsm_state324();
void thread_ap_CS_fsm_state325();
void thread_ap_CS_fsm_state326();
void thread_ap_CS_fsm_state327();
void thread_ap_CS_fsm_state328();
void thread_ap_CS_fsm_state329();
void thread_ap_CS_fsm_state33();
void thread_ap_CS_fsm_state330();
void thread_ap_CS_fsm_state331();
void thread_ap_CS_fsm_state332();
void thread_ap_CS_fsm_state333();
void thread_ap_CS_fsm_state334();
void thread_ap_CS_fsm_state335();
void thread_ap_CS_fsm_state336();
void thread_ap_CS_fsm_state337();
void thread_ap_CS_fsm_state338();
void thread_ap_CS_fsm_state339();
void thread_ap_CS_fsm_state34();
void thread_ap_CS_fsm_state340();
void thread_ap_CS_fsm_state341();
void thread_ap_CS_fsm_state342();
void thread_ap_CS_fsm_state343();
void thread_ap_CS_fsm_state344();
void thread_ap_CS_fsm_state345();
void thread_ap_CS_fsm_state346();
void thread_ap_CS_fsm_state347();
void thread_ap_CS_fsm_state348();
void thread_ap_CS_fsm_state349();
void thread_ap_CS_fsm_state35();
void thread_ap_CS_fsm_state350();
void thread_ap_CS_fsm_state351();
void thread_ap_CS_fsm_state352();
void thread_ap_CS_fsm_state353();
void thread_ap_CS_fsm_state354();
void thread_ap_CS_fsm_state355();
void thread_ap_CS_fsm_state356();
void thread_ap_CS_fsm_state357();
void thread_ap_CS_fsm_state358();
void thread_ap_CS_fsm_state359();
void thread_ap_CS_fsm_state36();
void thread_ap_CS_fsm_state360();
void thread_ap_CS_fsm_state361();
void thread_ap_CS_fsm_state362();
void thread_ap_CS_fsm_state363();
void thread_ap_CS_fsm_state364();
void thread_ap_CS_fsm_state365();
void thread_ap_CS_fsm_state366();
void thread_ap_CS_fsm_state367();
void thread_ap_CS_fsm_state368();
void thread_ap_CS_fsm_state369();
void thread_ap_CS_fsm_state37();
void thread_ap_CS_fsm_state370();
void thread_ap_CS_fsm_state371();
void thread_ap_CS_fsm_state372();
void thread_ap_CS_fsm_state373();
void thread_ap_CS_fsm_state374();
void thread_ap_CS_fsm_state375();
void thread_ap_CS_fsm_state376();
void thread_ap_CS_fsm_state377();
void thread_ap_CS_fsm_state378();
void thread_ap_CS_fsm_state379();
void thread_ap_CS_fsm_state38();
void thread_ap_CS_fsm_state380();
void thread_ap_CS_fsm_state381();
void thread_ap_CS_fsm_state382();
void thread_ap_CS_fsm_state383();
void thread_ap_CS_fsm_state384();
void thread_ap_CS_fsm_state385();
void thread_ap_CS_fsm_state386();
void thread_ap_CS_fsm_state387();
void thread_ap_CS_fsm_state388();
void thread_ap_CS_fsm_state389();
void thread_ap_CS_fsm_state39();
void thread_ap_CS_fsm_state390();
void thread_ap_CS_fsm_state391();
void thread_ap_CS_fsm_state392();
void thread_ap_CS_fsm_state393();
void thread_ap_CS_fsm_state394();
void thread_ap_CS_fsm_state395();
void thread_ap_CS_fsm_state396();
void thread_ap_CS_fsm_state397();
void thread_ap_CS_fsm_state398();
void thread_ap_CS_fsm_state399();
void thread_ap_CS_fsm_state4();
void thread_ap_CS_fsm_state40();
void thread_ap_CS_fsm_state400();
void thread_ap_CS_fsm_state401();
void thread_ap_CS_fsm_state402();
void thread_ap_CS_fsm_state403();
void thread_ap_CS_fsm_state404();
void thread_ap_CS_fsm_state405();
void thread_ap_CS_fsm_state406();
void thread_ap_CS_fsm_state407();
void thread_ap_CS_fsm_state408();
void thread_ap_CS_fsm_state409();
void thread_ap_CS_fsm_state41();
void thread_ap_CS_fsm_state410();
void thread_ap_CS_fsm_state411();
void thread_ap_CS_fsm_state412();
void thread_ap_CS_fsm_state413();
void thread_ap_CS_fsm_state414();
void thread_ap_CS_fsm_state415();
void thread_ap_CS_fsm_state416();
void thread_ap_CS_fsm_state417();
void thread_ap_CS_fsm_state418();
void thread_ap_CS_fsm_state419();
void thread_ap_CS_fsm_state42();
void thread_ap_CS_fsm_state420();
void thread_ap_CS_fsm_state421();
void thread_ap_CS_fsm_state422();
void thread_ap_CS_fsm_state423();
void thread_ap_CS_fsm_state424();
void thread_ap_CS_fsm_state425();
void thread_ap_CS_fsm_state426();
void thread_ap_CS_fsm_state427();
void thread_ap_CS_fsm_state428();
void thread_ap_CS_fsm_state429();
void thread_ap_CS_fsm_state43();
void thread_ap_CS_fsm_state430();
void thread_ap_CS_fsm_state431();
void thread_ap_CS_fsm_state432();
void thread_ap_CS_fsm_state433();
void thread_ap_CS_fsm_state434();
void thread_ap_CS_fsm_state435();
void thread_ap_CS_fsm_state436();
void thread_ap_CS_fsm_state437();
void thread_ap_CS_fsm_state438();
void thread_ap_CS_fsm_state439();
void thread_ap_CS_fsm_state44();
void thread_ap_CS_fsm_state440();
void thread_ap_CS_fsm_state441();
void thread_ap_CS_fsm_state442();
void thread_ap_CS_fsm_state443();
void thread_ap_CS_fsm_state444();
void thread_ap_CS_fsm_state445();
void thread_ap_CS_fsm_state446();
void thread_ap_CS_fsm_state447();
void thread_ap_CS_fsm_state448();
void thread_ap_CS_fsm_state449();
void thread_ap_CS_fsm_state45();
void thread_ap_CS_fsm_state450();
void thread_ap_CS_fsm_state451();
void thread_ap_CS_fsm_state452();
void thread_ap_CS_fsm_state453();
void thread_ap_CS_fsm_state454();
void thread_ap_CS_fsm_state455();
void thread_ap_CS_fsm_state456();
void thread_ap_CS_fsm_state457();
void thread_ap_CS_fsm_state458();
void thread_ap_CS_fsm_state459();
void thread_ap_CS_fsm_state46();
void thread_ap_CS_fsm_state460();
void thread_ap_CS_fsm_state461();
void thread_ap_CS_fsm_state462();
void thread_ap_CS_fsm_state463();
void thread_ap_CS_fsm_state464();
void thread_ap_CS_fsm_state465();
void thread_ap_CS_fsm_state466();
void thread_ap_CS_fsm_state467();
void thread_ap_CS_fsm_state468();
void thread_ap_CS_fsm_state469();
void thread_ap_CS_fsm_state47();
void thread_ap_CS_fsm_state470();
void thread_ap_CS_fsm_state471();
void thread_ap_CS_fsm_state472();
void thread_ap_CS_fsm_state473();
void thread_ap_CS_fsm_state474();
void thread_ap_CS_fsm_state475();
void thread_ap_CS_fsm_state476();
void thread_ap_CS_fsm_state477();
void thread_ap_CS_fsm_state478();
void thread_ap_CS_fsm_state479();
void thread_ap_CS_fsm_state48();
void thread_ap_CS_fsm_state480();
void thread_ap_CS_fsm_state481();
void thread_ap_CS_fsm_state482();
void thread_ap_CS_fsm_state483();
void thread_ap_CS_fsm_state484();
void thread_ap_CS_fsm_state485();
void thread_ap_CS_fsm_state486();
void thread_ap_CS_fsm_state487();
void thread_ap_CS_fsm_state488();
void thread_ap_CS_fsm_state489();
void thread_ap_CS_fsm_state49();
void thread_ap_CS_fsm_state490();
void thread_ap_CS_fsm_state491();
void thread_ap_CS_fsm_state492();
void thread_ap_CS_fsm_state493();
void thread_ap_CS_fsm_state494();
void thread_ap_CS_fsm_state495();
void thread_ap_CS_fsm_state496();
void thread_ap_CS_fsm_state497();
void thread_ap_CS_fsm_state498();
void thread_ap_CS_fsm_state499();
void thread_ap_CS_fsm_state5();
void thread_ap_CS_fsm_state50();
void thread_ap_CS_fsm_state500();
void thread_ap_CS_fsm_state501();
void thread_ap_CS_fsm_state502();
void thread_ap_CS_fsm_state503();
void thread_ap_CS_fsm_state504();
void thread_ap_CS_fsm_state505();
void thread_ap_CS_fsm_state506();
void thread_ap_CS_fsm_state507();
void thread_ap_CS_fsm_state508();
void thread_ap_CS_fsm_state509();
void thread_ap_CS_fsm_state51();
void thread_ap_CS_fsm_state510();
void thread_ap_CS_fsm_state511();
void thread_ap_CS_fsm_state512();
void thread_ap_CS_fsm_state513();
void thread_ap_CS_fsm_state514();
void thread_ap_CS_fsm_state515();
void thread_ap_CS_fsm_state516();
void thread_ap_CS_fsm_state517();
void thread_ap_CS_fsm_state518();
void thread_ap_CS_fsm_state519();
void thread_ap_CS_fsm_state52();
void thread_ap_CS_fsm_state520();
void thread_ap_CS_fsm_state521();
void thread_ap_CS_fsm_state522();
void thread_ap_CS_fsm_state523();
void thread_ap_CS_fsm_state524();
void thread_ap_CS_fsm_state525();
void thread_ap_CS_fsm_state526();
void thread_ap_CS_fsm_state527();
void thread_ap_CS_fsm_state528();
void thread_ap_CS_fsm_state529();
void thread_ap_CS_fsm_state53();
void thread_ap_CS_fsm_state530();
void thread_ap_CS_fsm_state531();
void thread_ap_CS_fsm_state532();
void thread_ap_CS_fsm_state533();
void thread_ap_CS_fsm_state534();
void thread_ap_CS_fsm_state535();
void thread_ap_CS_fsm_state536();
void thread_ap_CS_fsm_state537();
void thread_ap_CS_fsm_state538();
void thread_ap_CS_fsm_state539();
void thread_ap_CS_fsm_state54();
void thread_ap_CS_fsm_state540();
void thread_ap_CS_fsm_state541();
void thread_ap_CS_fsm_state542();
void thread_ap_CS_fsm_state543();
void thread_ap_CS_fsm_state544();
void thread_ap_CS_fsm_state545();
void thread_ap_CS_fsm_state546();
void thread_ap_CS_fsm_state547();
void thread_ap_CS_fsm_state548();
void thread_ap_CS_fsm_state549();
void thread_ap_CS_fsm_state55();
void thread_ap_CS_fsm_state550();
void thread_ap_CS_fsm_state551();
void thread_ap_CS_fsm_state552();
void thread_ap_CS_fsm_state553();
void thread_ap_CS_fsm_state554();
void thread_ap_CS_fsm_state555();
void thread_ap_CS_fsm_state556();
void thread_ap_CS_fsm_state557();
void thread_ap_CS_fsm_state558();
void thread_ap_CS_fsm_state559();
void thread_ap_CS_fsm_state56();
void thread_ap_CS_fsm_state560();
void thread_ap_CS_fsm_state561();
void thread_ap_CS_fsm_state562();
void thread_ap_CS_fsm_state564();
void thread_ap_CS_fsm_state565();
void thread_ap_CS_fsm_state566();
void thread_ap_CS_fsm_state567();
void thread_ap_CS_fsm_state57();
void thread_ap_CS_fsm_state58();
void thread_ap_CS_fsm_state59();
void thread_ap_CS_fsm_state6();
void thread_ap_CS_fsm_state60();
void thread_ap_CS_fsm_state61();
void thread_ap_CS_fsm_state62();
void thread_ap_CS_fsm_state63();
void thread_ap_CS_fsm_state64();
void thread_ap_CS_fsm_state65();
void thread_ap_CS_fsm_state66();
void thread_ap_CS_fsm_state67();
void thread_ap_CS_fsm_state68();
void thread_ap_CS_fsm_state69();
void thread_ap_CS_fsm_state7();
void thread_ap_CS_fsm_state70();
void thread_ap_CS_fsm_state71();
void thread_ap_CS_fsm_state72();
void thread_ap_CS_fsm_state73();
void thread_ap_CS_fsm_state74();
void thread_ap_CS_fsm_state75();
void thread_ap_CS_fsm_state76();
void thread_ap_CS_fsm_state77();
void thread_ap_CS_fsm_state78();
void thread_ap_CS_fsm_state79();
void thread_ap_CS_fsm_state8();
void thread_ap_CS_fsm_state80();
void thread_ap_CS_fsm_state81();
void thread_ap_CS_fsm_state82();
void thread_ap_CS_fsm_state83();
void thread_ap_CS_fsm_state84();
void thread_ap_CS_fsm_state85();
void thread_ap_CS_fsm_state86();
void thread_ap_CS_fsm_state87();
void thread_ap_CS_fsm_state88();
void thread_ap_CS_fsm_state89();
void thread_ap_CS_fsm_state9();
void thread_ap_CS_fsm_state90();
void thread_ap_CS_fsm_state91();
void thread_ap_CS_fsm_state92();
void thread_ap_CS_fsm_state93();
void thread_ap_CS_fsm_state94();
void thread_ap_CS_fsm_state95();
void thread_ap_CS_fsm_state96();
void thread_ap_CS_fsm_state97();
void thread_ap_CS_fsm_state98();
void thread_ap_CS_fsm_state99();
void thread_ap_block_state1();
void thread_ap_block_state558();
void thread_ap_done();
void thread_ap_idle();
void thread_ap_ready();
void thread_ap_rst_n_inv();
void thread_contact_in_address0();
void thread_contact_in_ce0();
void thread_contacts_address0();
void thread_contacts_ce0();
void thread_contacts_ce1();
void thread_contacts_size_out_1_ack_in();
void thread_contacts_size_out_1_data_in();
void thread_contacts_size_out_1_vld_in();
void thread_contacts_we0();
void thread_database_address0();
void thread_database_ce0();
void thread_database_ce1();
void thread_database_in_address0();
void thread_database_in_ce0();
void t
|
hread_database_index_1_fu_6447_p2();
void thread_database_index_cast_fu_6438_p1();
void thread_database_size_out_1_ack_in();
void thread_database_size_out_1_data_in();
void thread_database_size_out_1_vld_in();
void thread_database_we0();
void thread_error_out_1_ack_in();
void thread_error_out_1_data_in();
void thread_error_out_1_vld_in();
void thread_exitcond_i1_fu_7094_p2();
void thread_exitcond_i_fu_7135_p2();
void thread_grp_compare_fu_6234_ap_start();
void thread_grp_compare_fu_6234_contacts_index();
void thread_i_1_fu_7100_p2();
void thread_i_fu_7141_p2();
void thread_icmp_fu_6421_p2();
void thread_matched_finished_1_ack_in();
void thread_matched_finished_1_data_in();
void thread_matched_finished_1_vld_in();
void thread_matched_out_address0();
void thread_matched_out_ce0();
void thread_matched_out_we0();
void thread_operation_ap_vld_in_sig();
void thread_operation_blk_n();
void thread_operation_in_sig();
void thread_operation_read_read_fu_968_p2();
void thread_results_address0();
void thread_results_ce0();
void thread_results_d0();
void thread_results_we0();
void thread_sum_i1_cast_fu_7131_p1();
void thread_sum_i1_fu_7115_p2();
void thread_sum_i_cast_fu_7172_p1();
void thread_sum_i_fu_7156_p2();
void thread_tmp100_fu_6918_p2();
void thread_tmp101_fu_6922_p2();
void thread_tmp102_fu_6942_p2();
void thread_tmp103_fu_6933_p2();
void thread_tmp104_fu_6937_p2();
void thread_tmp105_fu_6983_p2();
void thread_tmp106_fu_6962_p2();
void thread_tmp107_fu_6953_p2();
void thread_tmp108_fu_6957_p2();
void thread_tmp109_fu_6977_p2();
void thread_tmp10_fu_6472_p2();
void thread_tmp110_fu_6968_p2();
void thread_tmp111_fu_6972_p2();
void thread_tmp112_fu_7067_p2();
void thread_tmp113_fu_7023_p2();
void thread_tmp114_fu_7002_p2();
void thread_tmp115_fu_6993_p2();
void thread_tmp116_fu_6997_p2();
void thread_tmp117_fu_7017_p2();
void thread_tmp118_fu_7008_p2();
void thread_tmp119_fu_7012_p2();
void thread_tmp11_fu_6518_p2();
void thread_tmp120_fu_7062_p2();
void thread_tmp121_fu_7037_p2();
void thread_tmp122_fu_7028_p2();
void thread_tmp123_fu_7032_p2();
void thread_tmp124_fu_7056_p2();
void thread_tmp125_fu_7047_p2();
void thread_tmp126_fu_7051_p2();
void thread_tmp12_fu_6497_p2();
void thread_tmp13_fu_6488_p2();
void thread_tmp14_fu_6492_p2();
void thread_tmp15_fu_6512_p2();
void thread_tmp16_fu_6503_p2();
void thread_tmp17_fu_6507_p2();
void thread_tmp18_fu_6598_p2();
void thread_tmp19_fu_6558_p2();
void thread_tmp1_fu_6762_p2();
void thread_tmp20_fu_6537_p2();
void thread_tmp21_fu_6528_p2();
void thread_tmp22_fu_6532_p2();
void thread_tmp23_fu_6552_p2();
void thread_tmp24_fu_6543_p2();
void thread_tmp25_fu_6547_p2();
void thread_tmp26_fu_6593_p2();
void thread_tmp27_fu_6572_p2();
void thread_tmp28_fu_6563_p2();
void thread_tmp29_fu_6567_p2();
void thread_tmp2_fu_6728_p2();
void thread_tmp30_fu_6587_p2();
void thread_tmp31_fu_6578_p2();
void thread_tmp32_fu_6582_p2();
void thread_tmp33_fu_6757_p2();
void thread_tmp34_fu_6673_p2();
void thread_tmp35_fu_6633_p2();
void thread_tmp36_fu_6612_p2();
void thread_tmp37_fu_6603_p2();
void thread_tmp38_fu_6607_p2();
void thread_tmp39_fu_6627_p2();
void thread_tmp3_fu_6523_p2();
void thread_tmp40_fu_6618_p2();
void thread_tmp41_fu_6622_p2();
void thread_tmp42_fu_6668_p2();
void thread_tmp43_fu_6647_p2();
void thread_tmp44_fu_6638_p2();
void thread_tmp45_fu_6642_p2();
void thread_tmp46_fu_6662_p2();
void thread_tmp47_fu_6653_p2();
void thread_tmp48_fu_6657_p2();
void thread_tmp49_fu_6752_p2();
void thread_tmp4_fu_6483_p2();
void thread_tmp50_fu_6708_p2();
void thread_tmp51_fu_6687_p2();
void thread_tmp52_fu_6678_p2();
void thread_tmp53_fu_6682_p2();
void thread_tmp54_fu_6702_p2();
void thread_tmp55_fu_6693_p2();
void thread_tmp56_fu_6697_p2();
void thread_tmp57_fu_6747_p2();
void thread_tmp58_fu_6722_p2();
void thread_tmp59_fu_6713_p2();
void thread_tmp5_fu_6462_p2();
void thread_tmp60_fu_6717_p2();
void thread_tmp61_fu_6741_p2();
void thread_tmp62_fu_6732_p2();
void thread_tmp63_fu_6736_p2();
void thread_tmp64_fu_7077_p2();
void thread_tmp65_fu_7043_p2();
void thread_tmp66_fu_6838_p2();
void thread_tmp67_fu_6798_p2();
void thread_tmp68_fu_6777_p2();
void thread_tmp69_fu_6768_p2();
void thread_tmp6_fu_6453_p2();
void thread_tmp70_fu_6772_p2();
void thread_tmp71_fu_6792_p2();
void thread_tmp72_fu_6783_p2();
void thread_tmp73_fu_6787_p2();
void thread_tmp74_fu_6833_p2();
void thread_tmp75_fu_6812_p2();
void thread_tmp76_fu_6803_p2();
void thread_tmp77_fu_6807_p2();
void thread_tmp78_fu_6827_p2();
void thread_tmp79_fu_6818_p2();
void thread_tmp7_fu_6457_p2();
void thread_tmp80_fu_6822_p2();
void thread_tmp81_fu_6913_p2();
void thread_tmp82_fu_6873_p2();
void thread_tmp83_fu_6852_p2();
void thread_tmp84_fu_6843_p2();
void thread_tmp85_fu_6847_p2();
void thread_tmp86_fu_6867_p2();
void thread_tmp87_fu_6858_p2();
void thread_tmp88_fu_6862_p2();
void thread_tmp89_fu_6908_p2();
void thread_tmp8_fu_6477_p2();
void thread_tmp90_fu_6887_p2();
void thread_tmp91_fu_6878_p2();
void thread_tmp92_fu_6882_p2();
void thread_tmp93_fu_6902_p2();
void thread_tmp94_fu_6893_p2();
void thread_tmp95_fu_6897_p2();
void thread_tmp96_fu_7072_p2();
void thread_tmp97_fu_6988_p2();
void thread_tmp98_fu_6948_p2();
void thread_tmp99_fu_6927_p2();
void thread_tmp9_fu_6468_p2();
void thread_tmp_1_fu_6396_p2();
void thread_tmp_2_fu_6427_p1();
void thread_tmp_3_cast_fu_6430_p3();
void thread_tmp_3_fu_6401_p1();
void thread_tmp_4_fu_7161_p2();
void thread_tmp_6_cast_fu_6404_p3();
void thread_tmp_7_fu_7120_p2();
void thread_tmp_8_fu_6442_p2();
void thread_tmp_9_264_fu_7089_p1();
void thread_tmp_fu_6412_p4();
void thread_tmp_i1_cast_fu_7111_p1();
void thread_tmp_i1_fu_7106_p1();
void thread_tmp_i_cast_fu_7152_p1();
void thread_tmp_i_fu_7147_p1();
void thread_ap_NS_fsm();
void thread_hdltv_gen();
};
}
using namespace ap_rtl;
#endif
|
/*
* Copyright 2021 Chair of EDA, Technical University of Munich
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
////////////////////////////////////////////////////////////////////////////////////////////////////
/// @file reset_gen.h
/// @date 2019-03-10
////////////////////////////////////////////////////////////////////////////////////////////////////
#ifndef __ETISS_SC_TLM_GENERIC_RESET_GEN_H__
#define __ETISS_SC_TLM_GENERIC_RESET_GEN_H__
#include "systemc.h"
namespace etiss_sc
{
class ResetGenerator final : public sc_core::sc_module
{
SC_HAS_PROCESS(ResetGenerator);
bool active_high_;
public:
sc_core::sc_out<bool> rst_o_{ "reset_out" };
ResetGenerator(sc_core::sc_module_name name, uint64_t clk_period, bool active_high = true);
private:
uint64_t clk_period_{ 0 };
void genRst();
};
} // namespace etiss_sc
#endif // __ETISS_SC_TLM_GENERIC_RESET_GEN_H__
|
/*******************************************************************************
* gndemux.h -- Copyright 2019 (c) Glenn Ramalho - RFIDo Design
*******************************************************************************
* Description:
* This is a simple gnmuxin for GN logic use in testbenches.
*******************************************************************************
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
#ifndef _GNDEMUX_H
#define _GNDEMUX_H
#include <systemc.h>
#include "gn_mixed.h"
SC_MODULE(gndemux) {
sc_port< sc_signal_out_if<gn_mixed>,0 > pin {"pin"};
sc_in<int> pinS {"pinS"};
sc_in<gn_mixed> pinY {"pinY"};
void drivepin_th();
gndemux (sc_module_name name, gn_mixed _def = GN_LOGIC_Z) {
def = _def;
SC_THREAD(drivepin_th);
}
SC_HAS_PROCESS(gndemux);
protected:
gn_mixed def;
};
#endif
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
// Version: 2019.2
// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _Mat2AXIvideo_HH_
#define _Mat2AXIvideo_HH_
#include "systemc.h"
#include "AESL_pkg.h"
namespace ap_rtl {
struct Mat2AXIvideo : public sc_module {
// Port declarations 25
sc_in_clk ap_clk;
sc_in< sc_logic > ap_rst;
sc_in< sc_logic > ap_start;
sc_out< sc_logic > ap_done;
sc_in< sc_logic > ap_continue;
sc_out< sc_logic > ap_idle;
sc_out< sc_logic > ap_ready;
sc_in< sc_lv<10> > img_rows_V_dout;
sc_in< sc_logic > img_rows_V_empty_n;
sc_out< sc_logic > img_rows_V_read;
sc_in< sc_lv<11> > img_cols_V_dout;
sc_in< sc_logic > img_cols_V_empty_n;
sc_out< sc_logic > img_cols_V_read;
sc_in< sc_lv<8> > img_data_stream_V_dout;
sc_in< sc_logic > img_data_stream_V_empty_n;
sc_out< sc_logic > img_data_stream_V_read;
sc_out< sc_lv<8> > video_out_TDATA;
sc_out< sc_logic > video_out_TVALID;
sc_in< sc_logic > video_out_TREADY;
sc_out< sc_lv<1> > video_out_TKEEP;
sc_out< sc_lv<1> > video_out_TSTRB;
sc_out< sc_lv<1> > video_out_TUSER;
sc_out< sc_lv<1> > video_out_TLAST;
sc_out< sc_lv<1> > video_out_TID;
sc_out< sc_lv<1> > video_out_TDEST;
sc_signal< sc_lv<1> > ap_var_for_const1;
sc_signal< sc_lv<1> > ap_var_for_const0;
// Module declarations
Mat2AXIvideo(sc_module_name name);
SC_HAS_PROCESS(Mat2AXIvideo);
~Mat2AXIvideo();
sc_trace_file* mVcdFile;
regslice_both<8>* regslice_both_AXI_video_strm_V_data_V_U;
regslice_both<1>* regslice_both_AXI_video_strm_V_keep_V_U;
regslice_both<1>* regslice_both_AXI_video_strm_V_strb_V_U;
regslice_both<1>* regslice_both_AXI_video_strm_V_user_V_U;
regslice_both<1>* regslice_both_AXI_video_strm_V_last_V_U;
regslice_both<1>* regslice_both_AXI_video_strm_V_id_V_U;
regslice_both<1>* regslice_both_AXI_video_strm_V_dest_V_U;
sc_signal< sc_logic > ap_done_reg;
sc_signal< sc_lv<4> > ap_CS_fsm;
sc_signal< sc_logic > ap_CS_fsm_state1;
sc_signal< sc_logic > img_rows_V_blk_n;
sc_signal< sc_logic > img_cols_V_blk_n;
sc_signal< sc_logic > img_data_stream_V_blk_n;
sc_signal< sc_logic > ap_CS_fsm_pp0_stage0;
sc_signal< sc_logic > ap_enable_reg_pp0_iter1;
sc_signal< bool > ap_block_pp0_stage0;
sc_signal< sc_lv<1> > icmp_ln126_reg_282;
sc_signal< sc_logic > video_out_TDATA_blk_n;
sc_signal< sc_logic > ap_enable_reg_pp0_iter2;
sc_signal< sc_lv<1> > icmp_ln126_reg_282_pp0_iter1_reg;
sc_signal< sc_lv<32> > t_V_2_reg_177;
sc_signal< sc_lv<32> > rows_V_fu_188_p1;
sc_signal< sc_lv<32> > rows_V_reg_258;
sc_signal< bool > ap_block_state1;
sc_signal< sc_lv<32> > cols_V_fu_192_p1;
sc_signal< sc_lv<32> > cols_V_reg_263;
sc_signal< sc_lv<33> > ret_V_fu_200_p2;
sc_signal< sc_lv<33> > ret_V_reg_268;
sc_signal< sc_lv<1> > icmp_ln125_fu_211_p2;
sc_signal< sc_logic > ap_CS_fsm_state2;
sc_signal< sc_logic > regslice_both_AXI_video_strm_V_data_V_U_apdone_blk;
sc_signal< sc_lv<32> > i_V_fu_216_p2;
sc_signal< sc_lv<32> > i_V_reg_277;
sc_signal< sc_lv<1> > icmp_ln126_fu_222_p2;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1;
sc_signal< bool > ap_block_state4_io;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2;
sc_signal< bool > ap_block_state5_io;
sc_signal< bool > ap_block_pp0_stage0_11001;
sc_signal< sc_lv<32> > j_V_fu_227_p2;
sc_signal< sc_logic > ap_enable_reg_pp0_iter0;
sc_signal< sc_lv<1> > axi_last_V_fu_237_p2;
sc_signal< sc_lv<1> > axi_last_V_reg_291;
sc_signal< bool > ap_block_pp0_stage0_subdone;
sc_signal< sc_logic > ap_condition_pp0_exit_iter0_state3;
sc_signal< sc_lv<32> > t_V_reg_166;
sc_signal< sc_logic > ap_CS_fsm_state6;
sc_signal< sc_lv<1> > tmp_user_V_fu_114;
sc_signal< bool > ap_block_pp0_stage0_01001;
sc_signal< sc_lv<33> > zext_ln1354_fu_196_p1;
sc_signal< sc_lv<33> > zext_ln879_fu_233_p1;
sc_signal< sc_lv<4> > ap_NS_fsm;
sc_signal< sc_logic > ap_idle_pp0;
sc_signal< sc_logic > ap_enable_pp0;
sc_signal< sc_logic > video_out_TVALID_int;
sc_signal< sc_logic > video_out_TREADY_int;
sc_signal< sc_logic > regslice_both_AXI_video_strm_V_data_V_U_vld_out;
sc_signal< sc_logic > regslice_both_AXI_video_strm_V_keep_V_U_apdone_blk;
sc_signal< sc_logic > regslice_both_AXI_video_strm_V_keep_V_U_ack_in_dummy;
sc_signal< sc_logic > regslice_both_AXI_video_strm_V_keep_V_U_vld_out;
sc_signal< sc_logic > regslice_both_AXI_video_strm_V_strb_V_U_apdone_blk;
sc_signal< sc_logic > regslice_both_AXI_video_strm_V_strb_V_U_ack_in_dummy;
sc_signal< sc_logic > regslice_both_AXI_video_strm_V_strb_V_U_vld_out;
sc_signal< sc_logic > regslice_both_AXI_video_strm_V_user_V_U_apdone_blk;
sc_signal< sc_logic > regslice_both_AXI_video_strm_V_user_V_U_ack_in_dummy;
sc_signal< sc_logic > regslice_both_AXI_video_strm_V_user_V_U_vld_out;
sc_signal< sc_logic > regslice_both_AXI_video_strm_V_last_V_U_apdone_blk;
sc_signal< sc_logic > regslice_both_AXI_video_strm_V_last_V_U_ack_in_dummy;
sc_signal< sc_logic > regslice_both_AXI_video_strm_V_last_V_U_vld_out;
sc_signal< sc_logic > regslice_both_AXI_video_strm_V_id_V_U_apdone_blk;
sc_signal< sc_logic > regslice_both_AXI_video_strm_V_id_V_U_ack_in_dummy;
sc_signal< sc_logic > regslice_both_AXI_video_strm_V_id_V_U_vld_out;
sc_signal< sc_logic > regslice_both_AXI_video_strm_V_dest_V_U_apdone_blk;
sc_signal< sc_logic > regslice_both_AXI_video_strm_V_dest_V_U_ack_in_dummy;
sc_signal< sc_logic > regslice_both_AXI_video_strm_V_dest_V_U_vld_out;
static const sc_logic ap_const_logic_1;
static const sc_logic ap_const_logic_0;
static const sc_lv<4> ap_ST_fsm_state1;
static const sc_lv<4> ap_ST_fsm_state2;
static const sc_lv<4> ap_ST_fsm_pp0_stage0;
static const sc_lv<4> ap_ST_fsm_state6;
static const sc_lv<32> ap_const_lv32_0;
static const bool ap_const_boolean_1;
static const sc_lv<32> ap_const_lv32_2;
static const bool ap_const_boolean_0;
static const sc_lv<1> ap_const_lv1_0;
static const sc_lv<32> ap_const_lv32_1;
static const sc_lv<1> ap_const_lv1_1;
static const sc_lv<32> ap_const_lv32_3;
static const sc_lv<33> ap_const_lv33_1FFFFFFFF;
// Thread declarations
void thread_ap_var_for_const1();
void thread_ap_var_for_const0();
void thread_ap_clk_no_reset_();
void thread_ap_CS_fsm_pp0_stage0();
void thread_ap_CS_fsm_state1();
void thread_ap_CS_fsm_state2();
void thread_ap_CS_fsm_state6();
void thread_ap_block_pp0_stage0();
void thread_ap_block_pp0_stage0_01001();
void thread_ap_block_pp0_stage0_11001();
void thread_ap_block_pp0_stage0_subdone();
void thread_ap_block_state1();
void thread_ap_block_state3_pp0_stage0_iter0();
void thread_ap_block_state4_io();
void thread_ap_block_state4_pp0_stage0_iter1();
void thread_ap_block_state5_io();
void thread_ap_block_state5_pp0_stage0_iter2();
void thread_ap_condition_pp0_exit_iter0_state3();
void thread_ap_done();
void thread_ap_enable_pp0();
void thread_ap_idle();
void thread_ap_idle_pp0();
void thread_ap_ready();
void thread_axi_last_V_fu_237_p2();
void thread_cols_V_fu_192_p1();
void thread_i_V_fu_216_p2();
void thread_icmp_ln125_fu_211_p2();
void thread_icmp_ln126_fu_222_p2();
void thread_img_cols_V_blk_n();
void thread_img_cols_V_read();
void thread_img_data_stream_V_blk_n();
void thread_img_data_stream_V_read();
void thread_img_rows_V_blk_n();
void thread_img_rows_V_read();
void thread_j_V_fu_227_p2();
void thread_ret_V_fu_200_p2();
void thread_rows_V_fu_188_p1();
void thread_video_out_TDATA_blk_n();
void thread_video_out_TVALID();
void thread_video_out_TVALID_int();
void thread_zext_ln1354_fu_196_p1();
void thread_zext_ln879_fu_233_p1();
void thread_ap_NS_fsm();
};
}
using namespace ap_rtl;
#endif
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ===========================================================
#ifndef _acorn128_dec_onebyte_Decrypt_StateUpdate128_1bit_HH_
#define _acorn128_dec_onebyte_Decrypt_StateUpdate128_1bit_HH_
#include "systemc.h"
#include "AESL_pkg.h"
namespace ap_rtl {
struct acorn128_dec_onebyte_Decrypt_StateUpdate128_1bit : public sc_module {
// Port declarations 14
sc_in_clk ap_clk;
sc_in< sc_logic > ap_rst;
sc_in< sc_logic > ap_start;
sc_out< sc_logic > ap_done;
sc_out< sc_logic > ap_idle;
sc_out< sc_logic > ap_ready;
sc_out< sc_lv<9> > state_address0;
sc_out< sc_logic > state_ce0;
sc_out< sc_logic > state_we0;
sc_out< sc_lv<8> > state_d0;
sc_in< sc_lv<8> > state_q0;
sc_in< sc_lv<1> > ciphertextbit;
sc_in< sc_lv<1> > ca;
sc_in< sc_lv<1> > cb;
// Module declarations
acorn128_dec_onebyte_Decrypt_StateUpdate128_1bit(sc_module_name name);
SC_HAS_PROCESS(acorn128_dec_onebyte_Decrypt_StateUpdate128_1bit);
~acorn128_dec_onebyte_Decrypt_StateUpdate128_1bit();
sc_trace_file* mVcdFile;
sc_signal< sc_lv<23> > ap_CS_fsm;
sc_signal< sc_logic > ap_sig_cseq_ST_st1_fsm_0;
sc_signal< bool > ap_sig_bdd_41;
sc_signal< sc_lv<8> > reg_256;
sc_signal< sc_logic > ap_sig_cseq_ST_st3_fsm_2;
sc_signal< bool > ap_sig_bdd_62;
sc_signal< sc_logic > ap_sig_cseq_ST_st6_fsm_5;
sc_signal< bool > ap_sig_bdd_69;
sc_signal< sc_logic > ap_sig_cseq_ST_st12_fsm_11;
sc_signal< bool > ap_sig_bdd_77;
sc_signal< sc_logic > ap_sig_cseq_ST_st14_fsm_13;
sc_signal< bool > ap_sig_bdd_85;
sc_signal< sc_lv<8> > reg_260;
sc_signal< sc_logic > ap_sig_cseq_ST_st4_fsm_3;
sc_signal< bool > ap_sig_bdd_94;
sc_signal< sc_logic > ap_sig_cseq_ST_st7_fsm_6;
sc_signal< bool > ap_sig_bdd_101;
sc_signal< sc_lv<8> > reg_264;
sc_signal< sc_logic > ap_sig_cseq_ST_st5_fsm_4;
sc_signal< bool > ap_sig_bdd_110;
sc_signal< sc_logic > ap_sig_cseq_ST_st8_fsm_7;
sc_signal< bool > ap_sig_bdd_117;
sc_signal< sc_logic > ap_sig_cseq_ST_st13_fsm_12;
sc_signal< bool > ap_sig_bdd_125;
sc_signal< sc_lv<8> > state_load_reg_499;
sc_signal< sc_logic > ap_sig_cseq_ST_st2_fsm_1;
sc_signal< bool > ap_sig_bdd_139;
sc_signal< sc_lv<9> > state_addr_2_gep_fu_91_p3;
sc_signal< sc_lv<9> > state_addr_2_reg_505;
sc_signal< sc_lv<9> > state_addr_3_gep_fu_100_p3;
sc_signal< sc_lv<9> > state_addr_3_reg_510;
sc_signal< sc_lv<1> > tmp_24_fu_274_p1;
sc_signal< sc_lv<1> > tmp_24_reg_520;
sc_signal< sc_lv<9> > state_addr_5_gep_fu_118_p3;
sc_signal< sc_lv<9> > state_addr_5_reg_525;
sc_signal< sc_lv<8> > tmp_s_fu_283_p2;
sc_signal< sc_lv<8> > tmp_s_reg_530;
sc_signal< sc_lv<8> > x_assign_1_fu_289_p2;
sc_signal< sc_lv<8> > x_assign_1_reg_535;
sc_signal< sc_lv<9> > state_addr_7_gep_fu_136_p3;
sc_signal< sc_lv<9> > state_addr_7_reg_547;
sc_signal< sc_lv<8> > state_load_7_reg_557;
sc_signal< sc_logic > ap_sig_cseq_ST_st9_fsm_8;
sc_signal< bool > ap_sig_bdd_167;
sc_signal< sc_lv<9> > state_addr_9_gep_fu_154_p3;
sc_signal< sc_lv<9> > state_addr_9_reg_563;
sc_signal< sc_lv<8> > state_load_8_reg_568;
sc_signal< sc_logic > ap_sig_cseq_ST_st10_fsm_9;
sc_signal< bool > ap_sig_bdd_177;
sc_signal< sc_lv<8> > state_load_9_reg_579;
sc_signal< sc_logic > ap_sig_cseq_ST_st11_fsm_10;
sc_signal< bool > ap_sig_bdd_187;
sc_signal< sc_lv<9> > state_addr_11_gep_fu_172_p3;
sc_signal< sc_lv<9> > state_addr_11_reg_585;
sc_signal< sc_lv<8> > tmp3_fu_295_p2;
sc_signal< sc_lv<8> > tmp3_reg_590;
sc_signal< sc_lv<8> > tmp_3_fu_306_p2;
sc_signal< sc_lv<8> > tmp_3_reg_595;
sc_signal< sc_lv<8> > tmp_5_fu_316_p2;
sc_signal< sc_lv<8> > tmp_5_reg_601;
sc_signal< sc_lv<8> > tmp7_fu_335_p2;
sc_signal< sc_lv<8> > tmp7_reg_612;
sc_signal< sc_lv<8> > grp_fu_268_p2;
sc_signal< sc_lv<8> > tmp6_reg_622;
sc_signal< sc_lv<8> > z_assign_fu_341_p2;
sc_signal< sc_lv<8> > z_assign_reg_632;
sc_signal< sc_logic > ap_sig_cseq_ST_st15_fsm_14;
sc_signal< bool > ap_sig_bdd_214;
sc_signal< sc_lv<8> > y_assign_fu_346_p2;
sc_signal< sc_lv<8> > y_assign_reg_637;
sc_signal< sc_lv<8> > tmp_i_i_fu_384_p2;
sc_signal< sc_lv<8> > tmp_i_i_reg_642;
sc_signal< sc_lv<1> > tmp_25_fu_390_p1;
sc_signal< sc_lv<1> > tmp_25_reg_647;
sc_signal< sc_lv<8> > tmp_1_i_i_fu_400_p2;
sc_signal< sc_lv<8> > tmp_1_i_i_reg_657;
sc_signal< sc_logic > ap_sig_cseq_ST_st16_fsm_15;
sc_signal< bool > ap_sig_bdd_231;
sc_signal< sc_lv<8> > tmp_2_i_i_fu_406_p2;
sc_signal< sc_lv<8> > tmp_2_i_i_reg_662;
sc_signal< sc_lv<8> > ciphertextbit_cast_fu_412_p1;
sc_signal< sc_lv<8> > ciphertextbit_cast_reg_667;
sc_signal< sc_logic > ap_sig_cseq_ST_st21_fsm_20;
sc_signal< bool > ap_sig_bdd_242;
sc_signal< sc_lv<1> > tmp_1_i_fu_416_p2;
sc_signal< sc_lv<1> > tmp_1_i_reg_672;
sc_signal< sc_lv<1> > tmp_2_i_fu_421_p2;
sc_signal< sc_lv<1> > tmp_2_i_reg_677;
sc_signal< sc_lv<9> > j_1_fu_432_p2;
sc_signal< sc_lv<9> > j_1_reg_685;
sc_signal< sc_logic > ap_sig_cseq_ST_st22_fsm_21;
sc_signal< bool > ap_sig_bdd_255;
sc_signal< sc_lv<1> > exitcond_fu_426_p2;
sc_signal< sc_lv<9> > j_reg_243;
sc_signal< sc_logic > ap_sig_cseq_ST_st23_fsm_22;
sc_signal< bool > ap_sig_bdd_271;
sc_signal< sc_lv<64> > tmp_6_fu_438_p1;
sc_signal< sc_lv<64> > tmp_7_fu_489_p1;
sc_signal< sc_logic > ap_sig_cseq_ST_st17_fsm_16;
sc_signal< bool > ap_sig_bdd_317;
sc_signal< sc_logic > ap_sig_cseq_ST_st18_fsm_17;
sc_signal< bool > ap_sig_bdd_325;
sc_signal< sc_logic > ap_sig_cseq_ST_st19_fsm_18;
sc_signal< bool > ap_sig_bdd_333;
sc_signal< sc_logic > ap_sig_cseq_ST_st20_fsm_19;
sc_signal< bool > ap_sig_bdd_341;
sc_signal< sc_lv<8> > tmp_4_fu_482_p2;
sc_signal< sc_lv<8> > tmp1_fu_278_p2;
sc_signal< sc_lv<8> > tmp4_fu_301_p2;
sc_signal< sc_lv<8> > tmp5_fu_311_p2;
sc_signal< sc_lv<8> > tmp_4_i_i_i_fu_325_p2;
sc_signal< sc_lv<8> > tmp_i9_i_i_fu_321_p2;
sc_signal< sc_lv<8> > tmp_5_i_i_i_fu_330_p2;
sc_signal< sc_lv<8> > tmp_i_i_i_fu_351_p2;
sc_signal< sc_lv<8> > tmp_1_i_i_i_fu_357_p2;
sc_signal< sc_lv<8> > tmp_fu_368_p2;
sc_signal< sc_lv<8> > tmp_2_i_i_i_fu_362_p2;
sc_signal< sc_lv<8> > tmp8_fu_380_p2;
sc_signal< sc_lv<8> > tmp9_fu_374_p2;
sc_signal< sc_lv<8> > tmp_i_i_2_fu_394_p2;
sc_signal< sc_lv<1> > tmp11_fu_447_p2;
sc_signal< sc_lv<8> > tmp15_cast_fu_451_p1;
sc_signal< sc_lv<8> > tmp10_fu_443_p2;
sc_signal< sc_lv<8> > tmp14_fu_465_p2;
sc_signal< sc_lv<8> > tmp15_fu_471_p2;
sc_signal< sc_lv<8> > tmp13_fu_461_p2;
sc_signal< sc_lv<8> > tmp16_fu_476_p2;
sc_signal< sc_lv<8> > tmp12_fu_455_p2;
sc_signal< sc_lv<23> > ap_NS_fsm;
static const sc_logic ap_const_logic_1;
static const sc_logic ap_const_logic_0;
static const sc_lv<23> ap_ST_st1_fsm_0;
static const sc_lv<23> ap_ST_st2_fsm_1;
static const sc_lv<23> ap_ST_st3_fsm_2;
static const sc_lv<23> ap_ST_st4_fsm_3;
static const sc_lv<23> ap_ST_st5_fsm_4;
static const sc_lv<23> ap_ST_st6_fsm_5;
static const sc_lv<23> ap_ST_st7_fsm_6;
static const sc_lv<23> ap_ST_st8_fsm_7;
static const sc_lv<23> ap_ST_st9_fsm_8;
static const sc_lv<23> ap_ST_st10_fsm_9;
static const sc_lv<23> ap_ST_st11_fsm_10;
static const sc_lv<23> ap_ST_st12_fsm_11;
static const sc_lv<23> ap_ST_st13_fsm_12;
static const sc_lv<23> ap_ST_st14_fsm_13;
static const sc_lv<23> ap_ST_st15_fsm_14;
static const sc_lv<23> ap_ST_st16_fsm_15;
static const sc_lv<23> ap_ST_st17_fsm_16;
static const sc_lv<23> ap_ST_st18_fsm_17;
static const sc_lv<23> ap_ST_st19_fsm_18;
static const sc_lv<23> ap_ST_st20_fsm_19;
static const sc_lv<23> ap_ST_st21_fsm_20;
static const sc_lv<23> ap_ST_st22_fsm_21;
static const sc_lv<23> ap_ST_st23_fsm_22;
static const sc_lv<32> ap_const_lv32_0;
static const sc_lv<1> ap_const_lv1_1;
static const sc_lv<32> ap_const_lv32_2;
static const sc_lv<32> ap_const_lv32_5;
static const sc_lv<32> ap_const_lv32_B;
static const sc_lv<32> ap_const_lv32_D;
static const sc_lv<32> ap_const_lv32_3;
static const sc_lv<32> ap_const_lv32_6;
static const sc_lv<32> ap_const_lv32_4;
static const sc_lv<32> ap_const_lv32_7;
static const sc_lv<32> ap_const_lv32_C;
static const sc_lv<32> ap_const_lv32_1;
static const sc_lv<32> ap_const_lv32_8;
static const sc_lv<32> ap_const_lv32_9;
static const sc_lv<32> ap_const_lv32_A;
static const sc_lv<32> ap_const_lv32_E;
static const sc_lv<32> ap_const_lv32_F;
static const sc_lv<32> ap_const_lv32_14;
static const sc_lv<32> ap_const_lv32_15;
static const sc_lv<1> ap_const_lv1_0;
static const sc_lv<9> ap_const_lv9_0;
static const sc_lv<32> ap_const_lv32_16;
static const sc_lv<64> ap_const_lv64_EB;
static const sc_lv<64> ap_const_lv64_E6;
static const sc_lv<64> ap_const_lv64_121;
static const sc_lv<64> ap_const_lv64_C4;
static const sc_lv<64> ap_const_lv64_C1;
static const sc_lv<64> ap_const_lv64_A0;
static const sc_lv<64> ap_const_lv64_9A;
static const sc_lv<64> ap_const_lv64_6F;
static const sc_lv<64> ap_const_lv64_6B;
static const sc_lv<64> ap_const_lv64_42;
static const sc_lv<64> ap_const_lv64_3D;
static const sc_lv<64> ap_const_lv64_17;
static const sc_lv<64> ap_const_lv64_0;
static const sc_lv<64> ap_const_lv64_C;
static const sc_lv<64> ap_const_lv64_F4;
static const sc_lv<64> ap_const_lv64_124;
static const sc_lv<32> ap_const_lv32_10;
static const sc_lv<32> ap_const_lv32_11;
static const sc_lv<32> ap_const_lv32_12;
static const sc_lv<32> ap_const_lv32_13;
static const sc_lv<8> ap_const_lv8_1;
static const sc_lv<9> ap_const_lv9_124;
static const sc_lv<9> ap_const_lv9_1;
// Thread declarations
void thread_ap_clk_no_reset_();
void thread_ap_done();
void thread_ap_idle();
void thread_ap_ready();
void thread_ap_sig_bdd_101();
void thread_ap_sig_bdd_110();
void thread_ap_sig_bdd_117();
void thread_ap_sig_bdd_125();
void thread_ap_sig_bdd_139();
void thread_ap_sig_bdd_167();
void thread_ap_sig_bdd_177();
void thread_ap_sig_bdd_187();
void thread_ap_sig_bdd_214();
void thread_ap_sig_bdd_231();
void thread_ap_sig_bdd_242();
void thread_ap_sig_bdd_255();
void thread_ap_sig_bdd_271();
void thread_ap_sig_bdd_317();
void thread_ap_sig_bdd_325();
void thread_ap_sig_bdd_333();
void thread_ap_sig_bdd_341();
void thread_ap_sig_bdd_41();
void thread_ap_sig_bdd_62();
void thread_ap_sig_bdd_69();
void thread_ap_sig_bdd_77();
void thread_ap_sig_bdd_85();
void thread_ap_sig_bdd_94();
void thread_ap_sig_cseq_ST_st10_fsm_9();
void thread_ap_sig_cseq_ST_st11_fsm_10();
void thread_ap_sig_cseq_ST_st12_fsm_11();
void thread_ap_sig_cseq_ST_st13_fsm_12();
void thread_ap_sig_cseq_ST_st14_fsm_13();
void thread_ap_sig_cseq_ST_st15_fsm_14();
void thread_ap_sig_cseq_ST_st16_fsm_15();
void thread_ap_sig_cseq_ST_st17_fsm_16();
void thread_ap_sig_cseq_ST_st18_fsm_17();
void thread_ap_sig_cseq_ST_st19_fsm_18();
void thread_ap_sig_cseq_ST_st1_fsm_0();
void thread_ap_sig_cseq_ST_st20_fsm_19();
void thread_ap_sig_cseq_ST_st21_fsm_20();
void thread_ap_sig_cseq_ST_st22_fsm_21();
void thread_ap_sig_cseq_ST_st23_fsm_22();
void thread_ap_sig_cseq_ST_st2_fsm_1();
void thread_ap_sig_cseq_ST_st3_fsm_2();
void thread_ap_sig_cseq_ST_st4_fsm_3();
void thread_ap_sig_cseq_ST_st5_fsm_4();
void thread_ap_sig_cseq_ST_st6_fsm_5();
void thread_ap_sig_cseq_ST_st7_fsm_6();
void thread_ap_sig_cseq_ST_st8_fsm_7();
void thread_ap_sig_cseq_ST_st9_fsm_8();
void thread_ciphertextbit_cast_fu_412_p1();
void thread_exitcond_fu_426_p2();
void thread_grp_fu_268_p2();
void thread_j_1_fu_432_p2();
void thread_state_addr_11_gep_fu_172_p3();
void thread_state_addr_2_gep_fu_91_p3();
void thread_state_addr_3_gep_fu_100_p3();
void thread_state_addr_5_gep_fu_118_p3();
void thread_state_addr_7_gep_fu_136_p3();
void thread_state_addr_9_gep_fu_154_p3();
void thread_state_address0();
void thread_state_ce0();
void thread_state_d0();
void thread_state_we0();
void thread_tmp10_fu_443_p2();
void thread_tmp11_fu_447_p2();
void thread_tmp12_fu_455_p2();
void thread_tmp13_fu_461_p2();
void thread_tmp14_fu_465_p2();
void thread_tmp15_cast_fu_451_p1();
void thread_tmp15_fu_471_p2();
void thread_tmp16_fu_476_p2();
void thread_tmp1_fu_278_p2();
void thread_tmp3_fu_295_p2();
void thread_tmp4_fu_301_p2();
void thread_tmp5_fu_311_p2();
void thread_tmp7_fu_335_p2();
void thread_tmp8_fu_380_p2();
void thread_tmp9_fu_374_p2();
void thread_tmp_1_i_fu_416_p2();
void thread_tmp_1_i_i_fu_400_p2();
void thread_tmp_1_i_i_i_fu_357_p2();
void thread_tmp_24_fu_274_p1();
void thread_tmp_25_fu_390_p1();
void thread_tmp_2_i_fu_421_p2();
void thread_tmp_2_i_i_fu_406_p2();
void thread_tmp_2_i_i_i_fu_362_p2();
void thread_tmp_3_fu_306_p2();
void thread_tmp_4_fu_482_p2();
void thread_tmp_4_i_i_i_fu_325_p2();
void thread_tmp_5_fu_316_p2();
void thread_tmp_5_i_i_i_fu_330_p2();
void thread_tmp_6_fu_438_p1();
void thread_tmp_7_fu_489_p1();
void thread_tmp_fu_368_p2();
void thread_tmp_i9_i_i_fu_321_p2();
void thread_tmp_i_i_2_fu_394_p2();
void thread_tmp_i_i_fu_384_p2();
void thread_tmp_i_i_i_fu_351_p2();
void thread_tmp_s_fu_283_p2();
void thread_x_assign_1_fu_289_p2();
void thread_y_assign_fu_346_p2();
void thread_z_assign_fu_341_p2();
void thread_ap_NS_fsm();
};
}
using namespace ap_rtl;
#endif
|
/*
* Copyright (C) 2020 GreenWaves Technologies, SAS, ETH Zurich and
* University of Bologna
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* Authors: Germain Haugou, GreenWaves Technologies ([email protected])
*/
#include <vp/vp.hpp>
#include <vp/itf/io.hpp>
#include <stdio.h>
#include <string.h>
#include <systemc.h>
#include <vector>
#include <list>
#include <queue>
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <cstdint>
#include <dlfcn.h> // Linux specific header for dynamic loading
typedef void* CallbackInstance_t;
typedef void (AsynCallbackResp_Meth)(CallbackInstance_t instance, int is_write);
typedef void (AsynCallbackUpdateReq_Meth)(CallbackInstance_t instance);
#define GRANULARITY 64
#define GRAN_CLOG 6
class ddr : public vp::Component
{
public:
ddr(vp::ComponentConf &conf);
~ddr();
void paraSendRequest(vp::IoReq *req);
static vp::IoReqStatus req(vp::Block *__this, vp::IoReq *req);
static void rspCallback(void *__this, int is_write);
static void reqCallback(void *__this);
private:
vp::Trace trace;
vp::IoSlave in;
void* libraryHandle;
int dram_id;
int (*add_dram)(char * resources_path, char * config_path);
void (*cloes_dram)(int dram_id);
int (*dram_can_accept_req)(int dram_id);
int (*dram_has_read_rsp)(int dram_id);
int (*dram_has_write_rsp)(int dram_id);
int (*dram_get_write_rsp)(int dram_id);
void (*dram_write_buffer)(int dram_id, int byte_int, int idx);
void (*dram_write_strobe)(int dram_id, int strob_int, int idx);
void (*dram_send_req)(int dram_id, uint64_t addr, uint64_t length , uint64_t is_write, uint64_t strob_enable);
void (*dram_get_read_rsp)(int dram_id, uint64_t length, const void* buf);
int (*dram_get_read_rsp_byte)(int dram_id);
int (*dram_get_inflight_read)(int dram_id);
void (*dram_preload_byte)(int dram_id, uint64_t dram_addr_ofst, int byte_int);
int (*dram_check_byte)(int dram_id, uint64_t dram_addr_ofst);
void (*dram_load_elf)(int dram_id, uint64_t dram_base_addr, char * elf_path);
void (*dram_load_memfile)(int dram_id, uint64_t addr_ofst, char * mem_path);
void (*dram_register_async_callback)(int dram_id, CallbackInstance_t instance, AsynCallbackResp_Meth* resp_meth, AsynCallbackUpdateReq_Meth* req_meth);
std::queue<vp::IoReq *> denied_req_queue;
std::list<std::pair<vp::IoReq *, std::queue<int>>> pending_read_req_queue;
};
ddr::ddr(vp::ComponentConf &config)
: vp::Component(config)
{
traces.new_trace("trace", &trace, vp::DEBUG);
in.set_req_meth(&ddr::req);
new_slave_port("input", &in);
libraryHandle = dlopen("libDRAMSys_Simulator.so", RTLD_LAZY);
add_dram = (int (*)(char*, char*))dlsym(libraryHandle, "add_dram");
cloes_dram = (void (*)(int))dlsym(libraryHandle, "cloes_dram");
dram_can_accept_req = (int (*)(int))dlsym(libraryHandle, "dram_can_accept_req");
dram_has_read_rsp = (int (*)(int))dlsym(libraryHandle, "dram_has_read_rsp");
dram_has_write_rsp = (int (*)(int))dlsym(libraryHandle, "dram_has_write_rsp");
dram_get_write_rsp = (int (*)(int))dlsym(libraryHandle, "dram_get_write_rsp");
dram_write_buffer = (void (*)(int, int, int))dlsym(libraryHandle, "dram_write_buffer");
dram_write_strobe = (void (*)(int, int, int))dlsym(libraryHandle, "dram_write_strobe");
dram_send_req = (void (*)(int, uint64_t, uint64_t, uint64_t, uint64_t))dlsym(libraryHandle, "dram_send_req");
dram_get_read_rsp = (void (*)(int, uint64_t, const void*))dlsym(libraryHandle, "dram_get_read_rsp");
dram_get_read_rsp_byte = (int (*)(int))dlsym(libraryHandle, "dram_get_read_rsp_byte");
dram_get_inflight_read = (int (*)(int))dlsym(libraryHandle, "dram_get_inflight_read");
dram_preload_byte = (void (*)(int, uint64_t, int))dlsym(libraryHandle, "dram_preload_byte");
dram_check_byte = (int (*)(int, uint64_t))dlsym(libraryHandle, "dram_check_byte");
dram_load_elf = (void (*)(int, uint64_t, char*))dlsym(libraryHandle, "dram_load_elf");
dram_load_memfile = (void (*)(int, uint64_t, char*))dlsym(libraryHandle, "dram_load_memfile");
dram_register_async_callback = (void (*)(int, CallbackInstance_t, AsynCallbackResp_Meth*, AsynCallbackUpdateReq_Meth*))dlsym(libraryHandle, "dram_register_async_callback");
#ifdef DRAMSYS_PATH
std::cout << "DRAMSYS_PATH is defined!: " << DRAMSYS_PATH << std::endl;
#else
std::cout << "DRAMSYS_PATH is not defined." << std::endl;
#endif
std::string current_path = DRAMSYS_PATH;
std::string resources_path = current_path + "/dramsys_configs";
std::string dram_type = get_js_config()->get("dram-type")->get_str();
std::string simulationJson_path;
if (dram_type == "ddr3") simulationJson_path = resources_path + "/ddr3-example.json";
else if (dram_type == "ddr4") simulationJson_path = resources_path + "/ddr4-example.json";
else if (dram_type == "lpddr4") simulationJson_path = resources_path + "/lpddr4-example.json";
else if (dram_type == "hbm2") simulationJson_path = resources_path + "/hbm2-example.json";
else simulationJson_path = resources_path + "/hbm2-example.json";
dram_id = add_dram((char*)resources_path.c_str(), (char*)simulationJson_path.c_str());
dram_register_async_callback(dram_id, (CallbackInstance_t)this, (AsynCallbackResp_Meth *)&ddr::rspCallback, (AsynCallbackUpdateReq_Meth*)&ddr::reqCallback);
}
void ddr::paraSendRequest(vp::IoReq *req){
uint64_t offset = req->get_addr();
uint8_t *data = req->get_data();
uint64_t size = req->get_size();
//Basic information
uint64_t req_start_addr = (offset >> GRAN_CLOG) << GRAN_CLOG;
uint64_t num_req = 1 + (((offset + size - 1) - req_start_addr) >> GRAN_CLOG);
trace.msg("---- Req Info: aligned addr->0x%x, #DRAM requests->%d \n",req_start_addr, num_req);
//Generate masks and data queue
std::queue<int> mask_q, mask_d;
std::queue<uint8_t> data_q;
for (int i = 0; i < GRANULARITY * num_req; ++i)
{
if (i >= (offset - req_start_addr) && i< (offset + size - req_start_addr))
{
mask_q.push(1);
mask_d.push(1);
data_q.push(data[ i - (offset - req_start_addr)]);
} else {
mask_q.push(0);
mask_d.push(0);
data_q.push(0);
}
}
//splite up for each request
for (int iter = 0; iter < num_req; ++iter)
{
if (req->get_is_write()) trace.msg("---- Write Data List of DRAM REQ #%d \n", iter);
//Write mask and data to buffer
for (int i = 0; i < GRANULARITY; ++i)
{
if (req->get_is_write()) trace.msg("-------- iter %d Put byte %d valid %d \n", i, (int)data_q.front(), mask_q.front());
dram_write_buffer(dram_id, data_q.front(), i);
dram_write_strobe(dram_id, mask_q.front(), i);
data_q.pop();
mask_q.pop();
}
//Send req to dram
dram_send_req(dram_id, req_start_addr + iter*GRANULARITY, GRANULARITY, req->get_is_write(), req->get_is_write());
}
//queue read request
std::pair<vp::IoReq *, std::queue<int>> pair;
pair.first = req;
pair.second = mask_d;
if (!req->get_is_write())
{
pending_read_req_queue.push_back(pair);
trace.msg("---- Add in Pending list: mask length->%d \n",pair.second.size());
}
}
vp::IoReqStatus ddr::req(vp::Block *__this, vp::IoReq *req)
{
ddr *_this = (ddr *)__this;
uint64_t offset = req->get_addr();
uint8_t *data = req->get_data();
uint64_t size = req->get_size();
_this->trace.msg("IO access (offset: 0x%x, size: 0x%x, is_write: %d)\n", offset, size, req->get_is_write());
if (_this->dram_can_accept_req(_this->dram_id))
{
_this->paraSendRequest(req);
if (req->get_is_write()) return vp::IO_REQ_OK;
return vp::IO_REQ_PENDING;
}else{
_this->denied_req_queue.push(req);
_this->trace.msg("---- Add in denied request list \n");
return vp::IO_REQ_DENIED;
}
}
void ddr::rspCallback(void *__this, int is_write){
ddr *_this = (ddr *)__this;
int rep_byte_int, mask;
_this->trace.msg("---- Response Callback Triggered \n");
if (is_write)
{
while(_this->dram_has_write_rsp(_this->dram_id)) rep_byte_int = _this->dram_get_write_rsp(_this->dram_id);
} else {
while(_this->dram_has_read_rsp(_this->dram_id) && _this->pending_read_req_queue.size() != 0){
vp::IoReq *req = _this->pending_read_req_queue.front().first;
uint64_t offset = req->get_addr();
uint8_t *data = req->get_data();
uint64_t size = req->get_size();
//Basic information
uint64_t req_start_addr = (offset >> GRAN_CLOG) << GRAN_CLOG;
uint64_t num_req = 1 + (((offset + size - 1) - req_start_addr) >> GRAN_CLOG);
uint64_t read_ptr = num_req*GRANULARITY - _this->pending_read_req_queue.front().second.size();
uint64_t start_ptr = offset - req_start_addr;
uint64_t end_ptr = offset - req_start_addr + size;
//Get byte and pop mask list
rep_byte_int = _this->dram_get_read_rsp_byte(_this->dram_id);
mask = _this->pending_read_req_queue.front().second.front();
_this->pending_read_req_queue.front().second.pop();
_this->trace.msg("-------- iter %d Get byte %d valid %d \n", read_ptr, rep_byte_int, (read_ptr >= start_ptr && read_ptr < end_ptr));
//Fill read data
if (read_ptr >= start_ptr && read_ptr < end_ptr)
{
data[read_ptr - start_ptr] = mask? (uint8_t)rep_byte_int: 0;
}
//Check mask list size, response request, pop pending req in list
if (_this->pending_read_req_queue.front().second.size() == 0)
{
_this->trace.msg("---- Response read \n");
req->get_resp_port()->resp(req);
_this->pending_read_req_queue.pop_front();
}
}
}
}
void ddr::reqCallback(void *__this){
ddr *_this = (ddr *)__this;
while(_this->dram_can_accept_req(_this->dram_id) && _this->denied_req_queue.size() != 0)
{
vp::IoReq *req = _this->denied_req_queue.front();
_this->paraSendRequest(req);
req->get_resp_port()->grant(req);
if (req->get_is_write()) req->get_resp_port()->resp(req);
_this->denied_req_queue.pop();
}
}
ddr::~ddr(){
cloes_dram(dram_id);
}
extern "C" vp::Component *gv_new(vp::ComponentConf &config)
{
return new ddr(config);
}
|
/*****************************************************************************
Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
more contributor license agreements. See the NOTICE file distributed
with this work for additional information regarding copyright ownership.
Accellera licenses this file to you under the Apache License, Version 2.0
(the "License"); you may not use this file except in compliance with the
License. You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
implied. See the License for the specific language governing
permissions and limitations under the License.
*****************************************************************************/
/*****************************************************************************
stimulus.cpp --
Original Author: Rocco Jonack, Synopsys, Inc.
*****************************************************************************/
/*****************************************************************************
MODIFICATION LOG - modifiers, enter your name, affiliation, date and
changes you are making here.
Name, Affiliation, Date:
Description of Modification:
*****************************************************************************/
#include <systemc.h>
#include "stimulus.h"
void stimulus::entry() {
cycle++;
// sending some reset values
if (cycle<4) {
reset.write(true);
input_valid.write(false);
} else {
reset.write(false);
input_valid.write( false );
// sending normal mode values
if (cycle%10==0) {
input_valid.write(true);
sample.write( (int)send_value1 );
cout << "Stimuli : " << (int)send_value1 << " at time "
/* << sc_time_stamp() << endl; */
<< sc_time_stamp().to_double() << endl;
send_value1++;
};
}
}
|
#ifndef RGB2GRAY_TLM_HPP
#define RGB2GRAY_TLM_HPP
#include <systemc.h>
using namespace sc_core;
using namespace sc_dt;
using namespace std;
#include <tlm.h>
#include <tlm_utils/simple_initiator_socket.h>
#include <tlm_utils/simple_target_socket.h>
#include <tlm_utils/peq_with_cb_and_phase.h>
#include "rgb2gray_pv_model.hpp"
#include "../src/img_target.cpp"
//Extended Unification TLM
struct rgb2gray_tlm : public Rgb2Gray, public img_target
{
rgb2gray_tlm(sc_module_name name) : Rgb2Gray((std::string(name) + "_HW_block").c_str()), img_target((std::string(name) + "_target").c_str()) {
#ifdef DISABLE_RGB_DEBUG
this->use_prints = false;
#endif //DISABLE_RGB_DEBUG
checkprintenableimgtar(use_prints);
}
//Override do_when_transaction functions
virtual void do_when_read_transaction(unsigned char*& data, unsigned int data_length, sc_dt::uint64 address);
virtual void do_when_write_transaction(unsigned char*& data, unsigned int data_length, sc_dt::uint64 address);
};
#endif // RGB2GRAY_TLM_HPP
|
/******************************************************************************
* *
* Copyright (C) 2022 MachineWare GmbH *
* All Rights Reserved *
* *
* This is work is licensed under the terms described in the LICENSE file *
* found in the root directory of this source tree. *
* *
******************************************************************************/
#ifndef VCML_GENERIC_GATE_H
#define VCML_GENERIC_GATE_H
#include "vcml/core/types.h"
#include "vcml/core/systemc.h"
#include "vcml/core/module.h"
#include "vcml/core/model.h"
#include "vcml/protocols/gpio.h"
namespace vcml {
namespace gpio {
class gate : public module, public gpio_host
{
public:
enum logic_type {
LOGIC_NOT,
LOGIC_AND,
LOGIC_OR,
LOGIC_NAND,
LOGIC_NOR,
LOGIC_XOR,
};
gpio_target_array in;
gpio_initiator_socket out;
gate(const sc_module_name& name, logic_type type);
virtual ~gate() = default;
virtual const char* kind() const override;
protected:
logic_type m_type;
virtual void gpio_transport(const gpio_target_socket& socket,
gpio_payload& tx) override;
};
} // namespace gpio
} // namespace vcml
#endif
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
// Version: 2019.2
// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _Add_Rectangle_HH_
#define _Add_Rectangle_HH_
#include "systemc.h"
#include "AESL_pkg.h"
namespace ap_rtl {
struct Add_Rectangle : public sc_module {
// Port declarations 67
sc_in_clk ap_clk;
sc_in< sc_logic > ap_rst;
sc_in< sc_logic > ap_start;
sc_out< sc_logic > ap_done;
sc_in< sc_logic > ap_continue;
sc_out< sc_logic > ap_idle;
sc_out< sc_logic > ap_ready;
sc_in< sc_lv<8> > src_data_stream_0_V_dout;
sc_in< sc_logic > src_data_stream_0_V_empty_n;
sc_out< sc_logic > src_data_stream_0_V_read;
sc_in< sc_lv<8> > src_data_stream_1_V_dout;
sc_in< sc_logic > src_data_stream_1_V_empty_n;
sc_out< sc_logic > src_data_stream_1_V_read;
sc_in< sc_lv<8> > src_data_stream_2_V_dout;
sc_in< sc_logic > src_data_stream_2_V_empty_n;
sc_out< sc_logic > src_data_stream_2_V_read;
sc_in< sc_lv<8> > src_data_stream_3_V_dout;
sc_in< sc_logic > src_data_stream_3_V_empty_n;
sc_out< sc_logic > src_data_stream_3_V_read;
sc_out< sc_lv<8> > dst_data_stream_0_V_din;
sc_in< sc_logic > dst_data_stream_0_V_full_n;
sc_out< sc_logic > dst_data_stream_0_V_write;
sc_out< sc_lv<8> > dst_data_stream_1_V_din;
sc_in< sc_logic > dst_data_stream_1_V_full_n;
sc_out< sc_logic > dst_data_stream_1_V_write;
sc_out< sc_lv<8> > dst_data_stream_2_V_din;
sc_in< sc_logic > dst_data_stream_2_V_full_n;
sc_out< sc_logic > dst_data_stream_2_V_write;
sc_out< sc_lv<8> > dst_data_stream_3_V_din;
sc_in< sc_logic > dst_data_stream_3_V_full_n;
sc_out< sc_logic > dst_data_stream_3_V_write;
sc_in< sc_lv<16> > xleft_dout;
sc_in< sc_logic > xleft_empty_n;
sc_out< sc_logic > xleft_read;
sc_in< sc_lv<16> > xright_dout;
sc_in< sc_logic > xright_empty_n;
sc_out< sc_logic > xright_read;
sc_in< sc_lv<16> > ytop_dout;
sc_in< sc_logic > ytop_empty_n;
sc_out< sc_logic > ytop_read;
sc_in< sc_lv<16> > ydown_dout;
sc_in< sc_logic > ydown_empty_n;
sc_out< sc_logic > ydown_read;
sc_in< sc_lv<8> > color1_dout;
sc_in< sc_logic > color1_empty_n;
sc_out< sc_logic > color1_read;
sc_in< sc_lv<8> > color2_dout;
sc_in< sc_logic > color2_empty_n;
sc_out< sc_logic > color2_read;
sc_in< sc_lv<8> > color3_dout;
sc_in< sc_logic > color3_empty_n;
sc_out< sc_logic > color3_read;
sc_out< sc_lv<16> > xleft_out_din;
sc_in< sc_logic > xleft_out_full_n;
sc_out< sc_logic > xleft_out_write;
sc_out< sc_lv<16> > ytop_out_din;
sc_in< sc_logic > ytop_out_full_n;
sc_out< sc_logic > ytop_out_write;
sc_out< sc_lv<8> > color1_out_din;
sc_in< sc_logic > color1_out_full_n;
sc_out< sc_logic > color1_out_write;
sc_out< sc_lv<8> > color2_out_din;
sc_in< sc_logic > color2_out_full_n;
sc_out< sc_logic > color2_out_write;
sc_out< sc_lv<8> > color3_out_din;
sc_in< sc_logic > color3_out_full_n;
sc_out< sc_logic > color3_out_write;
// Module declarations
Add_Rectangle(sc_module_name name);
SC_HAS_PROCESS(Add_Rectangle);
~Add_Rectangle();
sc_trace_file* mVcdFile;
sc_signal< sc_logic > ap_done_reg;
sc_signal< sc_lv<4> > ap_CS_fsm;
sc_signal< sc_logic > ap_CS_fsm_state1;
sc_signal< sc_logic > src_data_stream_0_V_blk_n;
sc_signal< sc_logic > ap_CS_fsm_pp0_stage0;
sc_signal< sc_logic > ap_enable_reg_pp0_iter1;
sc_signal< bool > ap_block_pp0_stage0;
sc_signal< sc_lv<1> > icmp_ln70_reg_799;
sc_signal< sc_logic > src_data_stream_1_V_blk_n;
sc_signal< sc_logic > src_data_stream_2_V_blk_n;
sc_signal< sc_logic > src_data_stream_3_V_blk_n;
sc_signal< sc_logic > dst_data_stream_0_V_blk_n;
sc_signal< sc_logic > ap_enable_reg_pp0_iter2;
sc_signal< sc_lv<1> > icmp_ln70_reg_799_pp0_iter1_reg;
sc_signal< sc_logic > dst_data_stream_1_V_blk_n;
sc_signal< sc_logic > dst_data_stream_2_V_blk_n;
sc_signal< sc_logic > dst_data_stream_3_V_blk_n;
sc_signal< sc_logic > xleft_blk_n;
sc_signal< sc_logic > xright_blk_n;
sc_signal< sc_logic > ytop_blk_n;
sc_signal< sc_logic > ydown_blk_n;
sc_signal< sc_logic > color1_blk_n;
sc_signal< sc_logic > color2_blk_n;
sc_signal< sc_logic > color3_blk_n;
sc_signal< sc_logic > xleft_out_blk_n;
sc_signal< sc_logic > ytop_out_blk_n;
sc_signal< sc_logic > color1_out_blk_n;
sc_signal< sc_logic > color2_out_blk_n;
sc_signal< sc_logic > color3_out_blk_n;
sc_signal< sc_lv<11> > j_0_i_reg_469;
sc_signal< sc_lv<16> > xleft_read_reg_719;
sc_signal< bool > ap_block_state1;
sc_signal< sc_lv<16> > xright_read_reg_724;
sc_signal< sc_lv<16> > ytop_read_reg_730;
sc_signal< sc_lv<16> > ydown_read_reg_735;
sc_signal< sc_lv<8> > pix1_val_0_2_reg_740;
sc_signal< sc_lv<8> > pix1_val_1_2_reg_745;
sc_signal< sc_lv<8> > pix1_val_2_2_reg_750;
sc_signal< sc_lv<17> > add_ln74_fu_484_p2;
sc_signal< sc_lv<17> > add_ln74_reg_755;
sc_signal< sc_lv<17> > add_ln74_1_fu_494_p2;
sc_signal< sc_lv<17> > add_ln74_1_reg_760;
sc_signal< sc_lv<17> > add_ln74_2_fu_504_p2;
sc_signal< sc_lv<17> > add_ln74_2_reg_765;
sc_signal< sc_lv<17> > add_ln74_3_fu_514_p2;
sc_signal< sc_lv<17> > add_ln74_3_reg_770;
sc_signal< sc_lv<1> > icmp_ln68_fu_524_p2;
sc_signal< sc_logic > ap_CS_fsm_state2;
sc_signal< sc_lv<10> > i_fu_530_p2;
sc_signal< sc_lv<10> > i_reg_779;
sc_signal< sc_lv<1> > or_ln74_fu_560_p2;
sc_signal< sc_lv<1> > or_ln74_reg_784;
sc_signal< sc_lv<1> > and_ln74_fu_578_p2;
sc_signal< sc_lv<1> > and_ln74_reg_789;
sc_signal< sc_lv<1> > xor_ln74_fu_584_p2;
sc_signal< sc_lv<1> > xor_ln74_reg_794;
sc_signal< sc_lv<1> > icmp_ln70_fu_594_p2;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2;
sc_signal< bool > ap_block_pp0_stage0_11001;
sc_signal< sc_lv<11> > j_fu_600_p2;
sc_signal< sc_logic > ap_enable_reg_pp0_iter0;
sc_signal< sc_lv<1> > and_ln74_1_fu_658_p2;
sc_signal< sc_lv<1> > and_ln74_1_reg_808;
sc_signal< sc_lv<1> > and_ln74_4_fu_674_p2;
sc_signal< sc_lv<1> > and_ln74_4_reg_815;
sc_signal< sc_lv<8> > tmp_9_reg_822;
sc_signal< sc_lv<8> > pix1_val_0_fu_686_p3;
sc_signal< sc_lv<8> > pix1_val_0_reg_827;
sc_signal< sc_lv<8> > pix1_val_1_fu_699_p3;
sc_signal< sc_lv<8> > pix1_val_1_reg_832;
sc_signal< sc_lv<8> > pix1_val_2_fu_712_p3;
sc_signal< sc_lv<8> > pix1_val_2_reg_837;
sc_signal< bool > ap_block_pp0_stage0_subdone;
sc_signal< sc_logic > ap_condition_pp0_exit_iter0_state3;
sc_signal< sc_lv<10> > i_0_i_reg_458;
sc_signal< sc_logic > ap_CS_fsm_state6;
sc_signal< bool > ap_block_pp0_stage0_01001;
sc_signal< sc_lv<17> > zext_ln74_fu_480_p1;
sc_signal< sc_lv<17> > zext_ln74_1_fu_490_p1;
sc_signal< sc_lv<17> > zext_ln74_2_fu_500_p1;
sc_signal< sc_lv<17> > zext_ln74_3_fu_510_p1;
sc_signal< sc_lv<16> > zext_ln68_fu_520_p1;
sc_signal< sc_lv<17> > zext_ln74_4_fu_541_p1;
sc_signal< sc_lv<1> > icmp_ln74_fu_536_p2;
sc_signal< sc_lv<1> > icmp_ln74_1_fu_545_p2;
sc_signal< sc_lv<1> > icmp_ln74_3_fu_555_p2;
sc_signal< sc_lv<1> > icmp_ln74_2_fu_550_p2;
sc_signal< sc_lv<1> > or_ln74_1_fu_566_p2;
sc_signal< sc_lv<1> > or_ln74_2_fu_572_p2;
sc_signal< sc_lv<16> > zext_ln70_fu_590_p1;
sc_signal< sc_lv<1> > icmp_ln74_5_fu_611_p2;
sc_signal< sc_lv<1> > or_ln74_3_fu_616_p2;
sc_signal< sc_lv<1> > icmp_ln74_4_fu_606_p2;
sc_signal< sc_lv<17> > zext_ln74_5_fu_627_p1;
sc_signal< sc_lv<1> > icmp_ln74_6_fu_631_p2;
sc_signal< sc_lv<1> > icmp_ln74_7_fu_642_p2;
sc_signal< sc_lv<1> > icmp_ln74_8_fu_647_p2;
sc_signal< sc_lv<1> > or_ln74_4_fu_621_p2;
sc_signal< sc_lv<1> > or_ln74_5_fu_636_p2;
sc_signal< sc_lv<1> > or_ln74_6_fu_652_p2;
sc_signal< sc_lv<1> > and_ln74_3_fu_668_p2;
sc_signal< sc_lv<1> > and_ln74_2_fu_663_p2;
sc_signal< sc_lv<8> > pix1_val_0_3_fu_680_p3;
sc_signal< sc_lv<8> > pix1_val_1_3_fu_693_p3;
sc_signal< sc_lv<8> > pix1_val_2_3_fu_706_p3;
sc_signal< sc_lv<4> > ap_NS_fsm;
sc_signal< sc_logic > ap_idle_pp0;
sc_signal< sc_logic > ap_enable_pp0;
static const sc_logic ap_const_logic_1;
static const sc_logic ap_const_logic_0;
static const sc_lv<4> ap_ST_fsm_state1;
static const sc_lv<4> ap_ST_fsm_state2;
static const sc_lv<4> ap_ST_fsm_pp0_stage0;
static const sc_lv<4> ap_ST_fsm_state6;
static const sc_lv<32> ap_const_lv32_0;
static const bool ap_const_boolean_1;
static const sc_lv<32> ap_const_lv32_2;
static const bool ap_const_boolean_0;
static const sc_lv<1> ap_const_lv1_0;
static const sc_lv<32> ap_const_lv32_1;
static const sc_lv<1> ap_const_lv1_1;
static const sc_lv<10> ap_const_lv10_0;
static const sc_lv<32> ap_const_lv32_3;
static const sc_lv<11> ap_const_lv11_0;
static const sc_lv<17> ap_const_lv17_4;
static const sc_lv<10> ap_const_lv10_2D0;
static const sc_lv<10> ap_const_lv10_1;
static const sc_lv<11> ap_const_lv11_500;
static const sc_lv<11> ap_const_lv11_1;
// Thread declarations
void thread_ap_clk_no_reset_();
void thread_add_ln74_1_fu_494_p2();
void thread_add_ln74_2_fu_504_p2();
void thread_add_ln74_3_fu_514_p2();
void thread_add_ln74_fu_484_p2();
void thread_and_ln74_1_fu_658_p2();
void thread_and_ln74_2_fu_663_p2();
void thread_and_ln74_3_fu_668_p2();
void thread_and_ln74_4_fu_674_p2();
void thread_and_ln74_fu_578_p2();
void thread_ap_CS_fsm_pp0_stage0();
void thread_ap_CS_fsm_state1();
void thread_ap_CS_fsm_state2();
void thread_ap_CS_fsm_state6();
void thread_ap_block_pp0_stage0();
void thread_ap_block_pp0_stage0_01001();
void thread_ap_block_pp0_stage0_11001();
void thread_ap_block_pp0_stage0_subdone();
void thread_ap_block_state1();
void thread_ap_block_state3_pp0_stage0_iter0();
void thread_ap_block_state4_pp0_stage0_iter1();
void thread_ap_block_state5_pp0_stage0_iter2();
void thread_ap_condition_pp0_exit_iter0_state3();
void thread_ap_done();
void thread_ap_enable_pp0();
void thread_ap_idle();
void thread_ap_idle_pp0();
void thread_ap_ready();
void thread_color1_blk_n();
void thread_color1_out_blk_n();
void thread_color1_out_din();
void thread_color1_out_write();
void thread_color1_read();
void thread_color2_blk_n();
void thread_color2_out_blk_n();
void thread_color2_out_din();
void thread_color2_out_write();
void thread_color2_read();
void thread_color3_blk_n();
void thread_color3_out_blk_n();
void thread_color3_out_din();
void thread_color3_out_write();
void thread_color3_read();
void thread_dst_data_stream_0_V_blk_n();
void thread_dst_data_stream_0_V_din();
void thread_dst_data_stream_0_V_write();
void thread_dst_data_stream_1_V_blk_n();
void thread_dst_data_stream_1_V_din();
void thread_dst_data_stream_1_V_write();
void thread_dst_data_stream_2_V_blk_n();
void thread_dst_data_stream_2_V_din();
void thread_dst_data_stream_2_V_write();
void thread_dst_data_stream_3_V_blk_n();
void thread_dst_data_stream_3_V_din();
void thread_dst_data_stream_3_V_write();
void thread_i_fu_530_p2();
void thread_icmp_ln68_fu_524_p2();
void thread_icmp_ln70_fu_594_p2();
void thread_icmp_ln74_1_fu_545_p2();
void thread_icmp_ln74_2_fu_550_p2();
void thread_icmp_ln74_3_fu_555_p2();
void thread_icmp_ln74_4_fu_606_p2();
void thread_icmp_ln74_5_fu_611_p2();
void thread_icmp_ln74_6_fu_631_p2();
void thread_icmp_ln74_7_fu_642_p2();
void thread_icmp_ln74_8_fu_647_p2();
void thread_icmp_ln74_fu_536_p2();
void thread_j_fu_600_p2();
void thread_or_ln74_1_fu_566_p2();
void thread_or_ln74_2_fu_572_p2();
void thread_or_ln74_3_fu_616_p2();
void thread_or_ln74_4_fu_621_p2();
void thread_or_ln74_5_fu_636_p2();
void thread_or_ln74_6_fu_652_p2();
void thread_or_ln74_fu_560_p2();
void thread_pix1_val_0_3_fu_680_p3();
void thread_pix1_val_0_fu_686_p3();
void thread_pix1_val_1_3_fu_693_p3();
void thread_pix1_val_1_fu_699_p3();
void thread_pix1_val_2_3_fu_706_p3();
void thread_pix1_val_2_fu_712_p3();
void thread_src_data_stream_0_V_blk_n();
void thread_src_data_stream_0_V_read();
void thread_src_data_stream_1_V_blk_n();
void thread_src_data_stream_1_V_read();
void thread_src_data_stream_2_V_blk_n();
void thread_src_data_stream_2_V_read();
void thread_src_data_stream_3_V_blk_n();
void thread_src_data_stream_3_V_read();
void thread_xleft_blk_n();
void thread_xleft_out_blk_n();
void thread_xleft_out_din();
void thread_xleft_out_write();
void thread_xleft_read();
void thread_xor_ln74_fu_584_p2();
void thread_xright_blk_n();
void thread_xright_read();
void thread_ydown_blk_n();
void thread_ydown_read();
void thread_ytop_blk_n();
void thread_ytop_out_blk_n();
void thread_ytop_out_din();
void thread_ytop_out_write();
void thread_ytop_read();
void thread_zext_ln68_fu_520_p1();
void thread_zext_ln70_fu_590_p1();
void thread_zext_ln74_1_fu_490_p1();
void thread_zext_ln74_2_fu_500_p1();
void thread_zext_ln74_3_fu_510_p1();
void thread_zext_ln74_4_fu_541_p1();
void thread_zext_ln74_5_fu_627_p1();
void thread_zext_ln74_fu_480_p1();
void thread_ap_NS_fsm();
};
}
using namespace ap_rtl;
#endif
|
/**
* @file lzss_enc_dut.h
* @brief
*
* @par Copyright
* (C) 2012 Taichi Ishitani All Rights Reserved.
*
* @author Taichi Ishitani
*
* @date 0.0.00 2012/07/07 T. Ishitani coding start
*/
#ifndef LZSS_ENC_DUT_H_
#define LZSS_ENC_DUT_H_
#include <string>
#include <stdint.h>
#include "systemc.h"
#include "lzss_type.h"
#include "Vdut_enc.h"
#include "verilated_vcd_sc.h"
using namespace std;
using namespace sc_core;
using namespace sc_dt;
template <int reference_size = 32, int coding_size = 9>
class LzssEncDut :
public sc_module
{
LzssTypeDefine(reference_size, coding_size)
public:
sc_in_clk clk;
sc_in<bool> rst_x;
sc_port<data_in_if_t> data_in_if;
sc_port<code_out_if_t> code_out_if;
typedef LzssEncDut<reference_size, coding_size> SC_CURRENT_USER_MODULE;
LzssEncDut(const sc_module_name& name);
virtual void trace(sc_trace_file* tr) const;
virtual void trace(VerilatedVcdSc* tr);
protected:
data_packet_t data;
code_packet_t code;
// DUT
Vdut_enc dut;
// 入出力信号
sc_signal<bool> i_valid;
sc_signal<bool> ow_ready;
sc_signal<uint32_t> i_data;
sc_signal<bool> i_last;
sc_signal<bool> o_valid;
sc_signal<bool> i_ready;
sc_signal<uint32_t> o_code;
sc_signal<bool> o_last;
void input_thread();
void output_thread();
};
template <int reference_size, int coding_size>
LzssEncDut<reference_size, coding_size>::LzssEncDut(const sc_module_name& name) :
sc_module (name),
dut ("dut")
{
SC_CTHREAD(input_thread, clk.pos());
reset_signal_is(rst_x, false);
SC_CTHREAD(output_thread, clk.pos());
reset_signal_is(rst_x, false);
dut.clk(clk);
dut.rst_x(rst_x);
dut.i_valid(i_valid);
dut.ow_ready(ow_ready);
dut.i_data(i_data);
dut.i_last(i_last);
dut.o_valid(o_valid);
dut.i_ready(i_ready);
dut.o_code(o_code);
dut.o_last(o_last);
}
template <int reference_size, int coding_size>
void LzssEncDut<reference_size, coding_size>::trace(sc_trace_file* tr) const {
sc_trace(tr, data, string(name()) + ".data");
sc_trace(tr, code, string(name()) + ".code");
}
template <int reference_size, int coding_size>
void LzssEncDut<reference_size, coding_size>::trace(VerilatedVcdSc* tr) {
dut.trace(tr, 1);
}
template <int reference_size, int coding_size>
void LzssEncDut<reference_size, coding_size>::input_thread() {
// リセット
i_valid.write(0);
i_data.write(0);
i_last.write(0);
wait();
while (true) {
// 入力待ち
while (data_in_if->num_available() == 0) {
wait();
}
data_in_if->nb_read(data);
// 入力セット
i_valid.write(1);
i_data.write((uint32_t)data.value);
i_last.write(data.last);
// レディ待ち
do {
wait();
} while (ow_ready.read() == 0);
// 入力クリア
i_valid.write(0);
i_data.write(0);
i_last.write(0);
}
}
template <int reference_size, int coding_size>
void LzssEncDut<reference_size, coding_size>::output_thread() {
// リセット
i_ready.write(0);
wait();
while (true) {
// 出力待ち
i_ready.write(1);
do {
wait();
} while (o_valid.read() == 0);
i_ready.write(0);
// 出力取りだし
code.value = o_code.read();
code.last = o_last.read();
while (code_out_if->num_free() == 0) {
wait();
}
code_out_if->nb_write(code);
}
}
#endif /* LZSS_ENC_DUT_H_ */
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.3
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _CvtColor_1_HH_
#define _CvtColor_1_HH_
#include "systemc.h"
#include "AESL_pkg.h"
#include "sobel_hls_mul_mulbkb.h"
#include "sobel_hls_mac_mulcud.h"
#include "sobel_hls_mac_muldEe.h"
namespace ap_rtl {
struct CvtColor_1 : public sc_module {
// Port declarations 28
sc_in_clk ap_clk;
sc_in< sc_logic > ap_rst;
sc_in< sc_logic > ap_start;
sc_in< sc_logic > start_full_n;
sc_out< sc_logic > ap_done;
sc_in< sc_logic > ap_continue;
sc_out< sc_logic > ap_idle;
sc_out< sc_logic > ap_ready;
sc_out< sc_logic > start_out;
sc_out< sc_logic > start_write;
sc_in< sc_lv<11> > p_src_rows_V_dout;
sc_in< sc_logic > p_src_rows_V_empty_n;
sc_out< sc_logic > p_src_rows_V_read;
sc_in< sc_lv<12> > p_src_cols_V_dout;
sc_in< sc_logic > p_src_cols_V_empty_n;
sc_out< sc_logic > p_src_cols_V_read;
sc_in< sc_lv<8> > p_src_data_stream_0_V_dout;
sc_in< sc_logic > p_src_data_stream_0_V_empty_n;
sc_out< sc_logic > p_src_data_stream_0_V_read;
sc_in< sc_lv<8> > p_src_data_stream_1_V_dout;
sc_in< sc_logic > p_src_data_stream_1_V_empty_n;
sc_out< sc_logic > p_src_data_stream_1_V_read;
sc_in< sc_lv<8> > p_src_data_stream_2_V_dout;
sc_in< sc_logic > p_src_data_stream_2_V_empty_n;
sc_out< sc_logic > p_src_data_stream_2_V_read;
sc_out< sc_lv<8> > p_dst_data_stream_V_din;
sc_in< sc_logic > p_dst_data_stream_V_full_n;
sc_out< sc_logic > p_dst_data_stream_V_write;
// Module declarations
CvtColor_1(sc_module_name name);
SC_HAS_PROCESS(CvtColor_1);
~CvtColor_1();
sc_trace_file* mVcdFile;
sobel_hls_mul_mulbkb<1,1,22,8,29>* sobel_hls_mul_mulbkb_U19;
sobel_hls_mac_mulcud<1,1,20,8,29,29>* sobel_hls_mac_mulcud_U20;
sobel_hls_mac_muldEe<1,1,23,8,29,30>* sobel_hls_mac_muldEe_U21;
sc_signal< sc_logic > real_start;
sc_signal< sc_logic > start_once_reg;
sc_signal< sc_logic > ap_done_reg;
sc_signal< sc_lv<4> > ap_CS_fsm;
sc_signal< sc_logic > ap_CS_fsm_state1;
sc_signal< sc_logic > internal_ap_ready;
sc_signal< sc_logic > p_src_rows_V_blk_n;
sc_signal< sc_logic > p_src_cols_V_blk_n;
sc_signal< sc_logic > p_src_data_stream_0_V_blk_n;
sc_signal< sc_logic > ap_CS_fsm_pp0_stage0;
sc_signal< sc_logic > ap_enable_reg_pp0_iter1;
sc_signal< bool > ap_block_pp0_stage0;
sc_signal< sc_lv<1> > tmp_70_i_reg_368;
sc_signal< sc_logic > p_src_data_stream_1_V_blk_n;
sc_signal< sc_logic > p_src_data_stream_2_V_blk_n;
sc_signal< sc_logic > p_dst_data_stream_V_blk_n;
sc_signal< sc_logic > ap_enable_reg_pp0_iter4;
sc_signal< sc_lv<1> > tmp_70_i_reg_368_pp0_iter3_reg;
sc_signal< sc_lv<11> > j_i_reg_212;
sc_signal< sc_lv<12> > p_src_cols_V_read_reg_349;
sc_signal< bool > ap_block_state1;
sc_signal< sc_lv<11> > p_src_rows_V_read_reg_354;
sc_signal< sc_lv<1> > tmp_i_fu_227_p2;
sc_signal< sc_logic > ap_CS_fsm_state2;
sc_signal< sc_lv<10> > i_fu_232_p2;
sc_signal< sc_lv<10> > i_reg_363;
sc_signal< sc_lv<1> > tmp_70_i_fu_242_p2;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4;
sc_signal< bool > ap_block_pp0_stage0_11001;
sc_signal< sc_lv<1> > tmp_70_i_reg_368_pp0_iter1_reg;
sc_signal< sc_lv<1> > tmp_70_i_reg_368_pp0_iter2_reg;
sc_signal< sc_lv<11> > j_fu_247_p2;
sc_signal< sc_logic > ap_enable_reg_pp0_iter0;
sc_signal< sc_lv<8> > tmp_84_reg_377;
sc_signal< sc_lv<8> > tmp_84_reg_377_pp0_iter2_reg;
sc_signal< sc_lv<8> > tmp_85_reg_382;
sc_signal< sc_lv<8> > tmp_85_reg_382_pp0_iter2_reg;
sc_signal< sc_lv<8> > tmp_86_reg_387;
sc_signal< sc_lv<29> > r_V_4_i_i_fu_325_p2;
sc_signal< sc_lv<29> > r_V_4_i_i_reg_392;
sc_signal< sc_lv<30> > grp_fu_339_p3;
sc_signal< sc_lv<30> > ret_V_1_reg_397;
sc_signal< sc_logic > ap_enable_reg_pp0_iter3;
sc_signal< sc_lv<8> > p_Val2_9_reg_402;
sc_signal< sc_lv<1> > tmp_reg_407;
sc_signal< bool > ap_block_pp0_stage0_subdone;
sc_signal< sc_logic > ap_condition_pp0_exit_iter0_state3;
sc_signal< sc_logic > ap_enable_reg_pp0_iter2;
sc_signal< sc_lv<10> > i_i_reg_201;
sc_signal< sc_logic > ap_CS_fsm_state8;
sc_signal< bool > ap_block_pp0_stage0_01001;
sc_signal< sc_lv<11> > i_cast_cast_i_fu_223_p1;
sc_signal< sc_lv<12> > j_cast_cast_i_fu_238_p1;
sc_signal< sc_lv<29> > grp_fu_331_p3;
sc_signal< sc_lv<8> > tmp_3_i_i_i_cast_i_fu_281_p1;
sc_signal< sc_lv<1> > tmp_81_fu_289_p3;
sc_signal< sc_lv<8> > p_Val2_10_fu_284_p2;
sc_signal< sc_lv<1> > tmp_82_fu_302_p3;
sc_signal< sc_lv<1> > rev_fu_296_p2;
sc_signal< sc_lv<1> > deleted_zeros_fu_310_p2;
sc_signal< sc_lv<22> > r_V_4_i_i_fu_325_p0;
sc_signal< sc_lv<8> > r_V_4_i_i_fu_325_p1;
sc_signal< sc_lv<20> > grp_fu_331_p0;
sc_signal< sc_lv<8> > grp_fu_331_p1;
sc_signal< sc_lv<23> > grp_fu_339_p0;
sc_signal< sc_lv<8> > grp_fu_339_p1;
sc_signal< sc_lv<29> > grp_fu_339_p2;
sc_signal< sc_lv<4> > ap_NS_fsm;
sc_signal< sc_logic > ap_idle_pp0;
sc_signal< sc_logic > ap_enable_pp0;
sc_signal< sc_lv<28> > grp_fu_331_p10;
sc_signal< sc_lv<30> > grp_fu_339_p10;
sc_signal< sc_lv<30> > grp_fu_339_p20;
sc_signal< sc_lv<29> > r_V_4_i_i_fu_325_p10;
static const sc_logic ap_const_logic_1;
static const sc_logic ap_const_logic_0;
static const sc_lv<4> ap_ST_fsm_state1;
static const sc_lv<4> ap_ST_fsm_state2;
static const sc_lv<4> ap_ST_fsm_pp0_stage0;
static const sc_lv<4> ap_ST_fsm_state8;
static const bool ap_const_boolean_1;
static const sc_lv<32> ap_const_lv32_0;
static const sc_lv<32> ap_const_lv32_2;
static const bool ap_const_boolean_0;
static const sc_lv<1> ap_const_lv1_1;
static const sc_lv<32> ap_const_lv32_1;
static const sc_lv<1> ap_const_lv1_0;
static const sc_lv<10> ap_const_lv10_0;
static const sc_lv<32> ap_const_lv32_3;
static const sc_lv<11> ap_const_lv11_0;
static const sc_lv<10> ap_const_lv10_1;
static const sc_lv<11> ap_const_lv11_1;
static const sc_lv<32> ap_const_lv32_16;
static const sc_lv<32> ap_const_lv32_1D;
static const sc_lv<32> ap_const_lv32_15;
static const sc_lv<32> ap_const_lv32_7;
static const sc_lv<8> ap_const_lv8_FF;
static const sc_lv<29> ap_const_lv29_1322D0;
static const sc_lv<28> ap_const_lv28_74BC6;
static const sc_lv<30> ap_const_lv30_259168;
// Thread declarations
void thread_ap_clk_no_reset_();
void thread_ap_CS_fsm_pp0_stage0();
void thread_ap_CS_fsm_state1();
void thread_ap_CS_fsm_state2();
void thread_ap_CS_fsm_state8();
void thread_ap_block_pp0_stage0();
void thread_ap_block_pp0_stage0_01001();
void thread_ap_block_pp0_stage0_11001();
void thread_ap_block_pp0_stage0_subdone();
void thread_ap_block_state1();
void thread_ap_block_state3_pp0_stage0_iter0();
void thread_ap_block_state4_pp0_stage0_iter1();
void thread_ap_block_state5_pp0_stage0_iter2();
void thread_ap_block_state6_pp0_stage0_iter3();
void thread_ap_block_state7_pp0_stage0_iter4();
void thread_ap_condition_pp0_exit_iter0_state3();
void thread_ap_done();
void thread_ap_enable_pp0();
void thread_ap_idle();
void thread_ap_idle_pp0();
void thread_ap_ready();
void thread_deleted_zeros_fu_310_p2();
void thread_grp_fu_331_p0();
void thread_grp_fu_331_p1();
void thread_grp_fu_331_p10();
void thread_grp_fu_339_p0();
void thread_grp_fu_339_p1();
void thread_grp_fu_339_p10();
void thread_grp_fu_339_p2();
void thread_grp_fu_339_p20();
void thread_i_cast_cast_i_fu_223_p1();
void thread_i_fu_232_p2();
void thread_internal_ap_ready();
void thread_j_cast_cast_i_fu_238_p1();
void thread_j_fu_247_p2();
void thread_p_Val2_10_fu_284_p2();
void thread_p_dst_data_stream_V_blk_n();
void thread_p_dst_data_stream_V_din();
void thread_p_dst_data_stream_V_write();
void thread_p_src_cols_V_blk_n();
void thread_p_src_cols_V_read();
void thread_p_src_data_stream_0_V_blk_n();
void thread_p_src_data_stream_0_V_read();
void thread_p_src_data_stream_1_V_blk_n();
void thread_p_src_data_stream_1_V_read();
void thread_p_src_data_stream_2_V_blk_n();
void thread_p_src_data_stream_2_V_read();
void thread_p_src_rows_V_blk_n();
void thread_p_src_rows_V_read();
void thread_r_V_4_i_i_fu_325_p0();
void thread_r_V_4_i_i_fu_325_p1();
void thread_r_V_4_i_i_fu_325_p10();
void thread_real_start();
void thread_rev_fu_296_p2();
void thread_start_out();
void thread_start_write();
void thread_tmp_3_i_i_i_cast_i_fu_281_p1();
void thread_tmp_70_i_fu_242_p2();
void thread_tmp_81_fu_289_p3();
void thread_tmp_82_fu_302_p3();
void thread_tmp_i_fu_227_p2();
void thread_ap_NS_fsm();
};
}
using namespace ap_rtl;
#endif
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.3
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _blobsCount_HH_
#define _blobsCount_HH_
#include "systemc.h"
#include "AESL_pkg.h"
namespace ap_rtl {
struct blobsCount : public sc_module {
// Port declarations 13
sc_in_clk ap_clk;
sc_in< sc_logic > ap_rst;
sc_in< sc_logic > ap_start;
sc_out< sc_logic > ap_done;
sc_out< sc_logic > ap_idle;
sc_out< sc_logic > ap_ready;
sc_out< sc_lv<15> > foreground_clean_address0;
sc_out< sc_logic > foreground_clean_ce0;
sc_in< sc_lv<8> > foreground_clean_q0;
sc_out< sc_lv<15> > foreground_clean_address1;
sc_out< sc_logic > foreground_clean_ce1;
sc_in< sc_lv<8> > foreground_clean_q1;
sc_out< sc_lv<31> > ap_return;
// Module declarations
blobsCount(sc_module_name name);
SC_HAS_PROCESS(blobsCount);
~blobsCount();
sc_trace_file* mVcdFile;
sc_signal< sc_lv<6> > ap_CS_fsm;
sc_signal< sc_logic > ap_CS_fsm_state1;
sc_signal< sc_lv<15> > indvar_flatten_reg_99;
sc_signal< sc_lv<8> > i_reg_110;
sc_signal< sc_lv<32> > external_1_reg_122;
sc_signal< sc_lv<8> > j_reg_134;
sc_signal< sc_lv<32> > internal_1_reg_145;
sc_signal< sc_lv<8> > reg_157;
sc_signal< sc_logic > ap_CS_fsm_pp0_stage0;
sc_signal< sc_logic > ap_enable_reg_pp0_iter2;
sc_signal< bool > ap_block_state2_pp0_stage0_iter0;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1;
sc_signal< bool > ap_block_state6_pp0_stage0_iter2;
sc_signal< bool > ap_block_state8_pp0_stage0_iter3;
sc_signal< bool > ap_block_pp0_stage0_11001;
sc_signal< sc_lv<1> > exitcond_flatten_reg_454;
sc_signal< sc_lv<1> > exitcond_flatten_reg_454_pp0_iter1_reg;
sc_signal< sc_logic > ap_CS_fsm_pp0_stage1;
sc_signal< bool > ap_block_state3_pp0_stage1_iter0;
sc_signal< bool > ap_block_state5_pp0_stage1_iter1;
sc_signal< bool > ap_block_state7_pp0_stage1_iter2;
sc_signal< bool > ap_block_state9_pp0_stage1_iter3;
sc_signal< bool > ap_block_pp0_stage1_11001;
sc_signal< sc_lv<1> > exitcond_flatten_reg_454_pp0_iter2_reg;
sc_signal< sc_lv<8> > reg_161;
sc_signal< sc_lv<8> > i_17_fu_177_p2;
sc_signal< sc_lv<8> > i_17_reg_448;
sc_signal< sc_lv<1> > exitcond_flatten_fu_183_p2;
sc_signal< sc_lv<1> > exitcond_flatten_reg_454_pp0_iter3_reg;
sc_signal< sc_lv<15> > indvar_flatten_next_fu_189_p2;
sc_signal< sc_lv<15> > indvar_flatten_next_reg_458;
sc_signal< sc_logic > ap_enable_reg_pp0_iter0;
sc_signal< sc_lv<1> > exitcond5_fu_195_p2;
sc_signal< sc_lv<1> > exitcond5_reg_463;
sc_signal< sc_lv<8> > j_mid2_fu_201_p3;
sc_signal< sc_lv<8> > j_mid2_reg_469;
sc_signal< sc_lv<8> > i_cast5_mid2_fu_209_p3;
sc_signal< sc_lv<8> > i_cast5_mid2_reg_475;
sc_signal< sc_lv<8> > i_17_mid1_fu_215_p2;
sc_signal< sc_lv<8> > i_17_mid1_reg_481;
sc_signal< sc_lv<15> > tmp_28_fu_224_p2;
sc_signal< sc_lv<15> > tmp_28_reg_486;
sc_signal< sc_lv<8> > j_4_fu_230_p2;
sc_signal< sc_lv<8> > j_4_reg_494;
sc_signal< sc_lv<15> > i_cast5_mid2_cast_fu_235_p1;
sc_signal< sc_lv<15> > i_cast5_mid2_cast_reg_499;
sc_signal< sc_lv<15> > tmp_29_fu_247_p2;
sc_signal< sc_lv<15> > tmp_29_reg_505;
sc_signal< sc_lv<15> > tmp_32_fu_252_p2;
sc_signal< sc_lv<15> > tmp_32_reg_510;
sc_signal< sc_lv<15> > tmp_35_fu_270_p2;
sc_signal< sc_lv<15> > tmp_35_reg_525;
sc_signal< sc_lv<15> > tmp_38_fu_280_p2;
sc_signal< sc_lv<15> > tmp_38_reg_530;
sc_signal< sc_lv<1> > tmp_39_fu_289_p2;
sc_signal< sc_lv<1> > tmp_39_reg_541;
sc_signal< sc_lv<1> > tmp_39_reg_541_pp0_iter3_reg;
sc_signal< sc_lv<1> > grp_fu_165_p2;
sc_signal< sc_lv<1> > tmp_31_reg_551;
sc_signal< sc_lv<1> > grp_fu_171_p2;
sc_signal< sc_lv<1> > tmp_34_reg_557;
sc_signal< sc_lv<2> > p_px_1_fu_321_p3;
sc_signal< sc_lv<2> > p_px_1_reg_562;
sc_signal< sc_lv<1> > tmp_41_reg_567;
sc_signal< sc_logic > ap_enable_reg_pp0_iter3;
sc_signal< sc_lv<32> > external_fu_329_p2;
sc_signal< sc_lv<32> > external_reg_572;
sc_signal< sc_lv<32> > internal_fu_335_p2;
sc_signal< sc_lv<32> > internal_reg_577;
sc_signal< sc_lv<32> > p_external_1_fu_370_p3;
sc_signal< sc_lv<32> > internal_2_fu_383_p3;
sc_signal< sc_lv<32> > tmp_fu_390_p2;
sc_signal< sc_lv<32> > tmp_reg_592;
sc_signal< sc_logic > ap_CS_fsm_state10;
sc_signal< sc_lv<1> > tmp_26_reg_597;
sc_signal< sc_lv<30> > tmp_25_reg_602;
sc_signal< sc_lv<30> > tmp_24_reg_607;
sc_signal< sc_logic > ap_CS_fsm_state11;
sc_signal< bool > ap_block_pp0_stage0_subdone;
sc_signal< sc_logic > ap_condition_pp0_exit_iter0_state2;
sc_signal< sc_logic > ap_enable_reg_pp0_iter1;
sc_signal< bool > ap_block_pp0_stage1_subdone;
sc_signal< sc_lv<15> > ap_phi_mux_indvar_flatten_phi_fu_103_p4;
sc_signal< bool > ap_block_pp0_stage0;
sc_signal< sc_lv<8> > ap_phi_mux_i_phi_fu_114_p4;
sc_signal< sc_lv<8> > ap_phi_mux_j_phi_fu_138_p4;
sc_signal< sc_lv<64> > tmp_30_fu_257_p1;
sc_signal< bool > ap_block_pp0_stage1;
sc_signal< sc_lv<64> > tmp_33_fu_261_p1;
sc_signal< sc_lv<64> > tmp_36_fu_285_p1;
sc_signal< sc_lv<64> > tmp_40_fu_294_p1;
sc_signal< sc_lv<8> > tmp_28_fu_224_p0;
sc_signal< sc_lv<8> > i_17_cast_mid2_fu_238_p3;
sc_signal< sc_lv<15> > i_17_cast_mid2_cast_fu_243_p1;
sc_signal< sc_lv<15> > tmp1_fu_265_p2;
sc_signal< sc_lv<15> > tmp2_fu_275_p2;
sc_signal< sc_lv<2> > px_fu_301_p3;
sc_signal< sc_lv<2> > p_cast_fu_298_p1;
sc_signal< sc_lv<2> > px_1_fu_308_p3;
sc_signal< sc_lv<2> > px_2_fu_315_p2;
sc_signal< sc_lv<3> > p_px_1_cast_fu_341_p1;
sc_signal< sc_lv<3> > px_4_fu_344_p2;
sc_signal< sc_lv<3> > p_px_1_30_fu_350_p3;
sc_signal< sc_lv<3> > px_3_fu_357_p3;
sc_signal< sc_lv<1> > tmp_42_fu_364_p2;
sc_signal< sc_lv<1> > tmp_43_fu_377_p2;
sc_signal< sc_lv<32> > p_neg_fu_414_p2;
sc_signal< sc_logic > ap_CS_fsm_state12;
sc_signal< sc_lv<31> > p_lshr_cast_fu_429_p1;
sc_signal< sc_lv<31> > p_neg_t_fu_432_p2;
sc_signal< sc_lv<31> > p_lshr_f_cast_fu_438_p1;
sc_signal< sc_lv<6> > ap_NS_fsm;
sc_signal< sc_logic > ap_idle_pp0;
sc_signal< sc_logic > ap_enable_pp0;
sc_signal< sc_lv<15> > tmp_28_fu_224_p00;
static const sc_logic ap_const_logic_1;
static const sc_logic ap_const_logic_0;
static const sc_lv<6> ap_ST_fsm_state1;
static const sc_lv<6> ap_ST_fsm_pp0_stage0;
static const sc_lv<6> ap_ST_fsm_pp0_stage1;
static const sc_lv<6> ap_ST_fsm_state10;
static const sc_lv<6> ap_ST_fsm_state11;
static const sc_lv<6> ap_ST_fsm_state12;
static const bool ap_const_boolean_1;
static const sc_lv<32> ap_const_lv32_0;
static const sc_lv<32> ap_const_lv32_1;
static const bool ap_const_boolean_0;
static const sc_lv<1> ap_const_lv1_0;
static const sc_lv<32> ap_const_lv32_2;
static const sc_lv<1> ap_const_lv1_1;
static const sc_lv<32> ap_const_lv32_3;
static const sc_lv<32> ap_const_lv32_4;
static const sc_lv<15> ap_const_lv15_0;
static const sc_lv<8> ap_const_lv8_0;
static const sc_lv<8> ap_const_lv8_FF;
static const sc_lv<8> ap_const_lv8_1;
static const sc_lv<15> ap_const_lv15_7DDC;
static const sc_lv<15> ap_const_lv15_1;
static const sc_lv<8> ap_const_lv8_B3;
static const sc_lv<8> ap_const_lv8_2;
static const sc_lv<15> ap_const_lv15_B4;
static const sc_lv<15> ap_const_lv15_B5;
static const sc_lv<15> ap_const_lv15_7E90;
static const sc_lv<2> ap_const_lv2_2;
static const sc_lv<2> ap_const_lv2_1;
static const sc_lv<3> ap_const_lv3_1;
static const sc_lv<3> ap_const_lv3_3;
static const sc_lv<32> ap_const_lv32_1F;
static const sc_lv<32> ap_const_lv32_5;
static const sc_lv<31> ap_const_lv31_0;
// Thread declarations
void thread_ap_clk_no_reset_();
void thread_ap_CS_fsm_pp0_stage0();
void thread_ap_CS_fsm_pp0_stage1();
void thread_ap_CS_fsm_state1();
void thread_ap_CS_fsm_state10();
void thread_ap_CS_fsm_state11();
void thread_ap_CS_fsm_state12();
void thread_ap_block_pp0_stage0();
void thread_ap_block_pp0_stage0_11001();
void thread_ap_block_pp0_stage0_subdone();
void thread_ap_block_pp0_stage1();
void thread_ap_block_pp0_stage1_11001();
void thread_ap_block_pp0_stage1_subdone();
void thread_ap_block_state2_pp0_stage0_iter0();
void thread_ap_block_state3_pp0_stage1_iter0();
void thread_ap_block_state4_pp0_stage0_iter1();
void thread_ap_block_state5_pp0_stage1_iter1();
void thread_ap_block_state6_pp0_stage0_iter2();
void thread_ap_block_state7_pp0_stage1_iter2();
void thread_ap_block_state8_pp0_stage0_iter3();
void thread_ap_block_state9_pp0_stage1_iter3();
void thread_ap_condition_pp0_exit_iter0_state2();
void thread_ap_done();
void thread_ap_enable_pp0();
void thread_ap_idle();
void thread_ap_idle_pp0();
void thread_ap_phi_mux_i_phi_fu_114_p4();
void thread_ap_phi_mux_indvar_flatten_phi_fu_103_p4();
void thread_ap_phi_mux_j_phi_fu_138_p4();
void thread_ap_ready();
void thread_ap_return();
void thread_exitcond5_fu_195_p2();
void thread_exitcond_flatten_fu_183_p2();
void thread_external_fu_329_p2();
void thread_foreground_clean_address0();
void thread_foreground_clean_address1();
void thread_foreground_clean_ce0();
void thread_foreground_clean_ce1();
void thread_grp_fu_165_p2();
void thread_grp_fu_171_p2();
void thread_i_17_cast_mid2_cast_fu_243_p1();
void thread_i_17_cast_mid2_fu_238_p3();
void thread_i_17_fu_177_p2();
void thread_i_17_mid1_fu_215_p2();
void thread_i_cast5_mid2_cast_fu_235_p1();
void thread_i_cast5_mid2_fu_209_p3();
void thread_indvar_flatten_next_fu_189_p2();
void thread_internal_2_fu_383_p3();
void thread_internal_fu_335_p2();
void thread_j_4_fu_230_p2();
void thread_j_mid2_fu_201_p3();
void thread_p_cast_fu_298_p1();
void thread_p_external_1_fu_370_p3();
void thread_p_lshr_cast_fu_429_p1();
void thread_p_lshr_f_cast_fu_438_p1();
void thread_p_neg_fu_414_p2();
void thread_p_neg_t_fu_432_p2();
void thread_p_px_1_30_fu_350_p3();
void thread_p_px_1_cast_fu_341_p1();
void thread_p_px_1_fu_321_p3();
void thread_px_1_fu_308_p3();
void thread_px_2_fu_315_p2();
void thread_px_3_fu_357_p3();
void thread_px_4_fu_344_p2();
void thread_px_fu_301_p3();
void thread_tmp1_fu_265_p2();
void thread_tmp2_fu_275_p2();
void thread_tmp_28_fu_224_p0();
void thread_tmp_28_fu_224_p00();
void thread_tmp_28_fu_224_p2();
void thread_tmp_29_fu_247_p2();
void thread_tmp_30_fu_257_p1();
void thread_tmp_32_fu_252_p2();
void thread_tmp_33_fu_261_p1();
void thread_tmp_35_fu_270_p2();
void thread_tmp_36_fu_285_p1();
void thread_tmp_38_fu_280_p2();
void thread_tmp_39_fu_289_p2();
void thread_tmp_40_fu_294_p1();
void thread_tmp_42_fu_364_p2();
void thread_tmp_43_fu_377_p2();
void thread_tmp_fu_390_p2();
void thread_ap_NS_fsm();
};
}
using namespace ap_rtl;
#endif
|
//
// Copyright 2022 Sergey Khabarov, [email protected]
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
#pragma once
#include <systemc.h>
namespace debugger {
SC_MODULE(sdctrl_crc16) {
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
sc_in<bool> i_clear; // Clear CRC register;
sc_in<bool> i_next; // Shift enable strob
sc_in<bool> i_dat; // Input bit
sc_out<sc_uint<16>> o_crc15; // Computed value
void comb();
void registers();
SC_HAS_PROCESS(sdctrl_crc16);
sdctrl_crc16(sc_module_name name,
bool async_reset);
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
bool async_reset_;
struct sdctrl_crc16_registers {
sc_signal<sc_uint<16>> crc16;
} v, r;
void sdctrl_crc16_r_reset(sdctrl_crc16_registers &iv) {
iv.crc16 = 0;
}
};
} // namespace debugger
|
#include "systemc.h"
#include "system.h"
#include "checksum.h"
#include "application.h"
#include "noc_adapter_if.h"
#ifndef NOC_TILE_H
#define NOC_TILE_H
// =================================
// ===== TILE TYPES AND STATES =====
// =================================
/** Command structure. */
struct noc_cmd_t {
uint32_t skey; // Header start key, must match `NOC_CMD_SKEY`.
uint32_t cmd; // Command to execute.
uint32_t size; // Size of the payload.
uint32_t tx_addr; // Location to write acknowledge packet.
uint32_t trans_id; // ID of the transaction.
uint32_t status; // Response status, only used in acknowledge.
uint32_t ekey; // Header end key, must match `NOC_CMD_EKEY`.
uint32_t chksum; // Header checksum.
};
#define NOC_CMD_SKEY 0xBEEFCAFE
#define NOC_CMD_EKEY 0x01234567
// calculate the checksum of a command packet
#define CALC_CMD_CHKSUM(_cmd) \
_cmd.skey ^ _cmd.cmd ^ _cmd.size ^ _cmd.tx_addr ^ _cmd.trans_id ^ _cmd.status ^ _cmd.ekey
// statuses
#define NOC_STAT_OKAY 0x00000000
#define NOC_STAT_ERR_KEY 0x00000001
#define NOC_STAT_ERR_CHKSM 0x00000002
/** State of the commander. */
enum noc_commander_state_e {
NOC_COMMANDER_IDLE,
NOC_COMMANDER_WRITE_DATA
};
/** State of the responder. */
enum noc_responder_state_e {
NOC_RESPONDER_IDLE,
NOC_RESPONDER_WAIT_SIZE,
NOC_RESPONDER_WAIT_TRANS_ID,
NOC_RESPONDER_WAIT_EKEY,
NOC_RESPONDER_WAIT_DATA
};
// determine number of checkpoints to store
#define CHECKPOINT_SIZE (2*sizeof(noc_data_t))
#define N_CHECKPOINTS (MAX_OUT_SIZE / CHECKPOINT_SIZE)
// ========================
// ===== TILE MODULES =====
// ========================
class noc_tile_if : virtual public sc_interface {
public:
virtual void signal(uint32_t signal) = 0;
};
/** NoC tile module. */
class noc_tile : public sc_module, public noc_tile_if {
public:
/** Corresponding adapter. */
sc_port<noc_adapter_if> adapter_if;
/** Constructor. */
noc_tile(sc_module_name name);
/** noc_tile_if functions. */
virtual void signal(uint32_t signal) = 0;
};
/** Command issuer. */
class noc_commander : public noc_tile {
public:
/** Constructor. */
SC_HAS_PROCESS(noc_commander);
noc_commander(sc_module_name name);
/** noc_tile functions. */
void signal(uint32_t signal);
private:
/** Current state. */
noc_cmd_t _cur_cmd;
noc_cmd_t _cur_ack;
noc_commander_state_e _state;
/** Buffers. */
uint8_t _write_buf[AES_256_KEY_LEN + AES_BLOCK_LEN + MAX_DATA_SIZE];
uint8_t _exp_buf[MAX_OUT_SIZE];
uint8_t _rsp_buf[MAX_OUT_SIZE];
uint32_t _write_buf_size;
uint32_t _exp_buf_size;
/** Input FIFO from the adapter. */
uint32_t _in_fifo_src_addr[RESPONSE_FIFO_BUF_SIZE];
uint32_t _in_fifo_rel_addr[RESPONSE_FIFO_BUF_SIZE];
noc_data_t _in_fifo_data[RESPONSE_FIFO_BUF_SIZE];
uint32_t _in_fifo_head;
uint32_t _in_fifo_tail;
/** Transmit a packet to the redundant copies. */
void transmit_to_responders(noc_data_t *packets, uint32_t n_bytes);
/** Main thread functions. */
void main();
void recv_listener();
void recv_processor();
};
/** Command responder. */
class noc_responder : public noc_tile {
public:
sc_port<application> proc_if;
/** Constructor. */
SC_HAS_PROCESS(noc_responder);
noc_responder(sc_module_name name, uint32_t base_addr);
/** noc_tile functions. */
void signal(uint32_t signal);
private:
uint32_t _base_addr;
/** Current state. */
noc_cmd_t _cur_cmd;
noc_cmd_t _cur_ack;
noc_responder_state_e _state;
bool _last_packet_loaded;
uint32_t _cur_loaded_size;
/** Main thread functions. */
void main();
void recv_listener();
};
#endif // NOC_TILE_H
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
#ifndef _Mayo_keygen_Ground32_0_H_
#define _Mayo_keygen_Ground32_0_H_
#include "xlconstant_v1_1_7.h"
#include "systemc.h"
class Mayo_keygen_Ground32_0 : public sc_module {
public:
xlconstant_v1_1_7<32,0x00000000> mod;
sc_out< sc_bv<32> > dout;
Mayo_keygen_Ground32_0 (sc_core::sc_module_name name);
};
#endif
|
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD and is protected under U.S. and international copyright
// and other intellectual property laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// AMD, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) AMD shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or AMD had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// AMD products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of AMD products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
#ifndef _icyradio_GND_18_0_H_
#define _icyradio_GND_18_0_H_
#include "xlconstant_v1_1_8.h"
#include "systemc.h"
class icyradio_GND_18_0 : public sc_module {
public:
xlconstant_v1_1_8<1,0> mod;
sc_out< sc_bv<1> > dout;
icyradio_GND_18_0 (sc_core::sc_module_name name);
};
#endif
|
/*****************************************************************************
Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
more contributor license agreements. See the NOTICE file distributed
with this work for additional information regarding copyright ownership.
Accellera licenses this file to you under the Apache License, Version 2.0
(the "License"); you may not use this file except in compliance with the
License. You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
implied. See the License for the specific language governing
permissions and limitations under the License.
*****************************************************************************/
/*****************************************************************************
stimulus.cpp --
Original Author: Rocco Jonack, Synopsys, Inc.
*****************************************************************************/
/*****************************************************************************
MODIFICATION LOG - modifiers, enter your name, affiliation, date and
changes you are making here.
Name, Affiliation, Date:
Description of Modification:
*****************************************************************************/
#include <systemc.h>
#include "stimulus.h"
void stimulus::entry() {
cycle++;
// sending some reset values
if (cycle<4) {
reset.write(true);
input_valid.write(false);
} else {
reset.write(false);
input_valid.write( false );
// sending normal mode values
if (cycle%10==0) {
input_valid.write(true);
sample.write( (int)send_value1 );
cout << "Stimuli : " << (int)send_value1 << " at time "
/* << sc_time_stamp() << endl; */
<< sc_time_stamp().to_double() << endl;
send_value1++;
};
}
}
|
//
// Copyright 2022 Sergey Khabarov, [email protected]
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
#pragma once
#include <systemc.h>
#include "../river_cfg.h"
namespace debugger {
SC_MODULE(RegIntBank) {
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
sc_in<sc_uint<6>> i_radr1; // Port 1 read address
sc_out<sc_uint<RISCV_ARCH>> o_rdata1; // Port 1 read value
sc_out<sc_uint<CFG_REG_TAG_WIDTH>> o_rtag1; // Port 1 read tag value
sc_in<sc_uint<6>> i_radr2; // Port 2 read address
sc_out<sc_uint<RISCV_ARCH>> o_rdata2; // Port 2 read value
sc_out<sc_uint<CFG_REG_TAG_WIDTH>> o_rtag2; // Port 2 read tag value
sc_in<sc_uint<6>> i_waddr; // Writing value
sc_in<bool> i_wena; // Writing is enabled
sc_in<sc_uint<CFG_REG_TAG_WIDTH>> i_wtag; // Writing register tag
sc_in<sc_uint<RISCV_ARCH>> i_wdata; // Writing value
sc_in<bool> i_inorder; // Writing only if tag sequenced
sc_out<bool> o_ignored; // Sequenced writing is ignored because it was overwritten by executor (need for tracer)
sc_in<sc_uint<6>> i_dport_addr; // Debug port address
sc_in<bool> i_dport_ena; // Debug port is enabled
sc_in<bool> i_dport_write; // Debug port write is enabled
sc_in<sc_uint<RISCV_ARCH>> i_dport_wdata; // Debug port write value
sc_out<sc_uint<RISCV_ARCH>> o_dport_rdata; // Debug port read value
sc_out<sc_uint<RISCV_ARCH>> o_ra; // Return address for branch predictor
sc_out<sc_uint<RISCV_ARCH>> o_sp; // Stack Pointer for border control
sc_out<sc_uint<RISCV_ARCH>> o_gp;
sc_out<sc_uint<RISCV_ARCH>> o_tp;
sc_out<sc_uint<RISCV_ARCH>> o_t0;
sc_out<sc_uint<RISCV_ARCH>> o_t1;
sc_out<sc_uint<RISCV_ARCH>> o_t2;
sc_out<sc_uint<RISCV_ARCH>> o_fp;
sc_out<sc_uint<RISCV_ARCH>> o_s1;
sc_out<sc_uint<RISCV_ARCH>> o_a0;
sc_out<sc_uint<RISCV_ARCH>> o_a1;
sc_out<sc_uint<RISCV_ARCH>> o_a2;
sc_out<sc_uint<RISCV_ARCH>> o_a3;
sc_out<sc_uint<RISCV_ARCH>> o_a4;
sc_out<sc_uint<RISCV_ARCH>> o_a5;
sc_out<sc_uint<RISCV_ARCH>> o_a6;
sc_out<sc_uint<RISCV_ARCH>> o_a7;
sc_out<sc_uint<RISCV_ARCH>> o_s2;
sc_out<sc_uint<RISCV_ARCH>> o_s3;
sc_out<sc_uint<RISCV_ARCH>> o_s4;
sc_out<sc_uint<RISCV_ARCH>> o_s5;
sc_out<sc_uint<RISCV_ARCH>> o_s6;
sc_out<sc_uint<RISCV_ARCH>> o_s7;
sc_out<sc_uint<RISCV_ARCH>> o_s8;
sc_out<sc_uint<RISCV_ARCH>> o_s9;
sc_out<sc_uint<RISCV_ARCH>> o_s10;
sc_out<sc_uint<RISCV_ARCH>> o_s11;
sc_out<sc_uint<RISCV_ARCH>> o_t3;
sc_out<sc_uint<RISCV_ARCH>> o_t4;
sc_out<sc_uint<RISCV_ARCH>> o_t5;
sc_out<sc_uint<RISCV_ARCH>> o_t6;
void comb();
void registers();
SC_HAS_PROCESS(RegIntBank);
RegIntBank(sc_module_name name,
bool async_reset);
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
bool async_reset_;
struct RegValueType {
sc_signal<sc_uint<RISCV_ARCH>> val;
sc_signal<sc_uint<CFG_REG_TAG_WIDTH>> tag;
};
struct RegIntBank_registers {
RegValueType arr[REGS_TOTAL];
} v, r;
};
} // namespace debugger
|
/**
#define meta ...
prInt32f("%s\n", meta);
**/
/*
All rights reserved to Alireza Poshtkohi (c) 1999-2023.
Email: [email protected]
Website: http://www.poshtkohi.info
*/
#ifndef __pe_work_stealing_scheduler_sc__h__
#define __pe_work_stealing_scheduler_sc__h__
#include <systemc.h>
#include "globals.h"
//----------------------------------------------------
class pe_work_stealing_scheduler : public sc_module
{
/*---------------------fields-----------------*/
public: sc_in<bool> clock;
public: sc_in<bool> re_cores[NumOfCores]; // Read Enable
public: sc_in<bool> cs_cores[NumOfCores]; // Chip Select
public: sc_out<sc_int<32> > work_cores[NumOfCores];
private: const int numOfWorks;
/*---------------------methods----------------*/
SC_HAS_PROCESS(pe_work_stealing_scheduler);
public: pe_work_stealing_scheduler(sc_module_name name_, int numOfWorks_);
public: ~pe_work_stealing_scheduler();
private: void pe_work_stealing_scheduler_proc();
private: void print_ports(int i);
/*--------------------------------------------*/
};
//----------------------------------------------------
#endif
|
/*
* Created on: 21. jun. 2019
* Author: Jonathan Horsted Schougaard
*/
#pragma once
#define SC_INCLUDE_FX
#include "hwcore/hf/helperlib.h"
#include "hwcore/hw/singleportram.h"
#include "hwcore/pipes/data_types.h"
#include <systemc.h>
template <int W = 16, bool stream_while_write = false, int L = (((18 * 1024) / W) * 4)> SC_MODULE(_sc_stream_buffer) {
typedef typename hwcore::pipes::SC_DATA_STREAM_T_trait<1 * W>::interface_T interface_T;
enum ctrls { newset = 0, reapeat = 1 };
SC_MODULE_CLK_RESET_SIGNAL;
sc_fifo_in<interface_T> din;
sc_fifo_in<sc_uint<16> > ctrls_in;
sc_fifo_in<sc_uint<16> > ctrls_replay;
sc_fifo_out<interface_T> dout;
inline void trace(sc_trace_file * trace) {
SC_TRACE_ADD(clk);
SC_TRACE_ADD(reset);
// SC_TRACE_ADD(din);
// SC_TRACE_ADD(ctrls_in);
// SC_TRACE_ADD(dout);
}
SC_CTOR_TEMPLATE(_sc_stream_buffer) {
//#//pragma HLS function_instantiate variable=pW,pstream_while_write,pL
// dummy_rtl_generator(W+stream_while_write+L);
//#//pragma HLS function_instantiate variable=W_value,stream_while_write_value,L_value
SC_CTHREAD(thread_sc_stream_buffer, clk.pos());
reset_signal_is(reset, true);
}
void thread_sc_stream_buffer() {
/// pragma HLS function_instantiate variable=SC_CURRENT_USER_MODULE
// dummy_rtl_generator(W+stream_while_write+L);
//#pragma HLS function_instantiate variable=W_value,stream_while_write_value,L_value
//#//pragma HLS function_instantiate variable=W,stream_while_write,L
//#/pragma HLS function_instantiate variable=W_value,stream_while_write_value,L_value
HLS_DEBUG(1, 1, 0, "init thread");
hwcore::hw::singleport_ram<L, (W) + ((W) / 8) + 1> buf;
unsigned high_addr = 0;
while (true) {
interface_T tmp_in;
interface_T tmp_out;
int ctrls_tmp = ctrls_in.read();
if (ctrls_tmp == 0) {
HLS_DEBUG(1, 1, 0, "reading -- start");
high_addr = 0;
do {
#pragma HLS pipeline II = 1
tmp_in = din.read();
HLS_DEBUG(1, 1, 5, "reading -- got data: %s @ address: %d tlast? %s",
tmp_in.data.to_string().c_str(), high_addr, (tmp_in.tlast ? "true" : "false"));
if (stream_while_write)
dout.write(tmp_in); // if(stream_while_write)
if (!tmp_in.EOP()) {
buf.exec(hwcore::hf::bv_merge<1, (W / 8) + W>(
tmp_in.tlast, hwcore::hf::bv_merge<W / 8, W>(tmp_in.tkeep, tmp_in.data)),
high_addr, true);
high_addr++;
}
} while (!tmp_in.EOP());
/*if (stream_while_write)
{
HLS_DEBUG(1, 1, 0, "sending EOP");
tmp_in.setEOP();
dout.write(tmp_in);
}*/
buf.flush(high_addr - 1);
HLS_DEBUG(1, 1, 0, "reading -- done");
} else {
int ctrls_replay_tmp = ctrls_replay.read();
for (int re = 0; re < ctrls_tmp; re++) {
HLS_DEBUG(1, 1, 0, "writing -- start");
int i = 0;
int re_w = ctrls_replay_tmp;
int start = 0;
while (i < high_addr) {
#pragma HLS pipeline II = 1
sc_bv<W + (W / 8) + 1> tmp = buf.exec_read(0, i);
tmp_out.data = tmp(W - 1, 0);
tmp_out.tkeep = tmp((W + (W / 8)) - 1, W);
tmp_out.tlast = tmp.get_bit(W + (W / 8));
HLS_DEBUG(1, 1, 5, "writing -- sending data: %s @ address: %d / %d tlast? %s",
tmp_out.data.to_string().c_str(), i, high_addr - 1,
(tmp_out.tlast ? "true" : "false"));
// tmp_out.tfinal = (i == high_addr-1 ? 1 : 0);
dout.write(tmp_out);
if (tmp_out.tlast == 1) {
if (re_w != 0) {
i = start;
re_w--;
} else {
i++;
start = i;
re_w = ctrls_replay_tmp;
}
} else {
i++;
}
}
#if 0
for (int re = 0; re < ctrls_tmp; re++) {
HLS_DEBUG(1, 1, 0, "writing -- start");
for (int i = 0; i < high_addr; i++) {
#pragma HLS pipeline II = 1
sc_bv<W + (W / 8) + 1> tmp = buf.exec(0, i, false);
tmp_out.data = tmp(W - 1, 0);
tmp_out.tkeep = tmp((W + (W / 8)) - 1, W);
tmp_out.tlast = tmp.get_bit(W + (W / 8));
HLS_DEBUG(1, 1, 5, "writing -- sending data: %s @ address: %d / %d tlast? %s",
tmp_out.data.to_string().c_str(), i, high_addr - 1,
(tmp_out.tlast ? "true" : "false"));
// tmp_out.tfinal = (i == high_addr-1 ? 1 : 0);
dout.write(tmp_out);
}
/*HLS_DEBUG(1, 1, 0, "sending EOP");
tmp_out.setEOP();
dout.write(tmp_out);*/
HLS_DEBUG(1, 1, 0, "writing -- done");
#endif
}
}
}
}
};
template <int W = 16, int L = (((18 * 1024) / W) * 4)> //, bool stream_while_write = false>
SC_MODULE(_sc_stream_buffer_not_stream_while_write) {
typedef typename hwcore::pipes::SC_DATA_STREAM_T_trait<1 * W>::interface_T interface_T;
enum ctrls { newset = 0, reapeat = 1 };
SC_MODULE_CLK_RESET_SIGNAL;
sc_fifo_in<interface_T> din;
sc_fifo_in<sc_uint<31> > ctrls_in;
sc_fifo_out<interface_T> dout;
sc_out_opt<int> count_in;
sc_out_opt<int> count_out;
sc_out_opt<int> state;
inline void trace(sc_trace_file * trace) {
SC_TRACE_ADD(clk);
SC_TRACE_ADD(reset);
// SC_TRACE_ADD(din);
// SC_TRACE_ADD(ctrls_in);
// SC_TRACE_ADD(dout);
}
SC_CTOR_TEMPLATE(_sc_stream_buffer_not_stream_while_write) {
SC_CTHREAD(thread_sc_stream_buffer_not_stream_while_write, clk.pos());
HLS_DEBUG_EXEC(set_stack_size(100 * 1024 * 1024));
reset_signal_is(reset, true);
}
void thread_sc_stream_buffer_not_stream_while_write() {
HLS_DEBUG(1, 1, 0, "init thread");
// hwcore::hw::singleport_ram<L, (W) + ((W) / 8) + 1> buf;
sc_bv<W + (W / 8) + 1> buf[L];
hls_array_partition(buf, block factor = 1);
sc_uint<hwcore::hf::log2_ceil<L>::val> high_addr = 0;
sc_uint<hwcore::hf::log2_ceil<L>::val> cur_addr = 0;
while (true) {
hls_loop();
interface_T tmp_in, tmp_in_pre;
interface_T tmp_out;
sc_uint<31> ctrls_in_raw = ctrls_in.read();
sc_uint<20> ctrls_tmp = ctrls_in_raw(19, 0);
sc_uint<10> last_interval = ctrls_in_raw(29, 20);
// bool stream_while_write = ctrls_in_raw[29] == 1;
bool overwrite_last = (last_interval != 0);
bool forward = ctrls_in_raw[30] == 1;
if (forward) {
tmp_in_pre = din.read();
if (!tmp_in_pre.EOP()) {
do {
hls_pipeline(1);
tmp_in = din.read();
if (tmp_in.EOP()) {
tmp_in_pre.tlast = 1;
} else {
tmp_in_pre.tlast = 0;
}
dout.write(tmp_in_pre);
tmp_in_pre = tmp_in;
} while (!tmp_in.EOP());
}
tmp_out.setEOP();
dout.write(tmp_out);
} else if (ctrls_tmp == 0) {
HLS_DEBUG(1, 1, 0, "reading -- start");
high_addr = 0;
cur_addr = 0;
sc_uint<14> last_counter = 0;
bool new_data = false;
do {
hls_pipeline_raw(2);
wait();
if (cur_addr < high_addr) { // stream_while_write &&
sc_bv<W + (W / 8) + 1> tmp = buf[cur_addr];
tmp_out.data = tmp(W - 1, 0);
tmp_out.tkeep = tmp((W + (W / 8)) - 1, W);
tmp_out.tlast = tmp.get_bit(W + (W / 8));
if (dout.nb_write(tmp_out))
cur_addr++;
}
new_data = din.nb_read(tmp_in);
if (new_data) {
HLS_DEBUG(5, 1, 5, "reading -- got data: %s @ address: %d tlast? %s",
tmp_in.data.to_string().c_str(), high_addr.to_int(),
(tmp_in.tlast ? "true" : "false"));
if (!tmp_in.EOP()) {
sc_bv<1> tlast;
if (overwrite_last) {
tlast = (last_counter == last_interval - 1);
} else {
tlast = tmp_in.tlast;
}
buf[high_addr] = hwcore::hf::bv_merge<1, (W / 8) + W>(
tlast, hwcore::hf::bv_merge<W / 8, W>(tmp_in.tkeep, tmp_in.data));
high_addr++;
if (last_counter == last_interval - 1) {
last_counter = 0;
} else {
last_counter++;
}
}
}
} while (!(new_data && tmp_in.EOP()));
HLS_DEBUG(1, 1, 0, "reading -- done");
} else {
// int ctrls_replay_tmp = ctrls_replay.read();
sc_uint<28> replay = ctrls_tmp;
for (sc_uint<28> re = 0; re < replay; re++) {
hls_loop();
HLS_DEBUG(1, 1, 0, "writing -- start");
for (sc_uint<hwcore::hf::log2_ceil<L + 1>::val> i = cur_addr; i < high_addr; i++) {
hls_pipeline(1);
sc_bv<W + (W / 8) + 1> tmp = buf[i];
tmp_out.data = tmp(W - 1, 0);
tmp_out.tkeep = tmp((W + (W / 8)) - 1, W);
tmp_out.tlast = tmp.get_bit(W + (W / 8));
HLS_DEBUG(5, 1, 5, "writing -- sending data: %s @ address: %d / %d tlast? %s",
tmp_out.data.to_string().c_str(), i.to_int(), high_addr.to_int() - 1,
(tmp_out.tlast ? "true" : "false"));
// tmp_out.tfinal = (i == high_addr-1 ? 1 : 0);
dout.write(tmp_out);
}
cur_addr = 0;
}
tmp_out.setEOP();
dout.write(tmp_out);
HLS_DEBUG(1, 1, 0, "writing -- done and sending EOP");
}
}
}
};
namespace hwcore {
namespace pipes {
template <int W = 16, bool stream_while_write = false, int L = (((18 * 1024) / W) * 4)>
using sc_stream_buffer = ::_sc_stream_buffer<W, stream_while_write, L>;
#warning "replace with: not stream while write version"
template <int W = 16, int L = (((18 * 1024) / W) * 4)> //, bool stream_while_write = false>
using sc_stream_buffer_not_stream_while_write =
::_sc_stream_buffer_not_stream_while_write<W, L>; //, stream_while_write>;
} // namespace pipes
} // namespace hwcore
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2019.1
// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _dct_2d_HH_
#define _dct_2d_HH_
#include "systemc.h"
#include "AESL_pkg.h"
#include "dct_1d.h"
#include "dct_2d_row_outbuf.h"
#include "dct_2d_col_inbuf_0.h"
namespace ap_rtl {
struct dct_2d : public sc_module {
// Port declarations 34
sc_in_clk ap_clk;
sc_in< sc_logic > ap_rst;
sc_in< sc_logic > ap_start;
sc_out< sc_logic > ap_done;
sc_out< sc_logic > ap_idle;
sc_out< sc_logic > ap_ready;
sc_out< sc_lv<3> > in_block_0_address0;
sc_out< sc_logic > in_block_0_ce0;
sc_in< sc_lv<16> > in_block_0_q0;
sc_out< sc_lv<3> > in_block_1_address0;
sc_out< sc_logic > in_block_1_ce0;
sc_in< sc_lv<16> > in_block_1_q0;
sc_out< sc_lv<3> > in_block_2_address0;
sc_out< sc_logic > in_block_2_ce0;
sc_in< sc_lv<16> > in_block_2_q0;
sc_out< sc_lv<3> > in_block_3_address0;
sc_out< sc_logic > in_block_3_ce0;
sc_in< sc_lv<16> > in_block_3_q0;
sc_out< sc_lv<3> > in_block_4_address0;
sc_out< sc_logic > in_block_4_ce0;
sc_in< sc_lv<16> > in_block_4_q0;
sc_out< sc_lv<3> > in_block_5_address0;
sc_out< sc_logic > in_block_5_ce0;
sc_in< sc_lv<16> > in_block_5_q0;
sc_out< sc_lv<3> > in_block_6_address0;
sc_out< sc_logic > in_block_6_ce0;
sc_in< sc_lv<16> > in_block_6_q0;
sc_out< sc_lv<3> > in_block_7_address0;
sc_out< sc_logic > in_block_7_ce0;
sc_in< sc_lv<16> > in_block_7_q0;
sc_out< sc_lv<6> > out_block_address0;
sc_out< sc_logic > out_block_ce0;
sc_out< sc_logic > out_block_we0;
sc_out< sc_lv<16> > out_block_d0;
// Module declarations
dct_2d(sc_module_name name);
SC_HAS_PROCESS(dct_2d);
~dct_2d();
sc_trace_file* mVcdFile;
dct_2d_row_outbuf* row_outbuf_U;
dct_2d_row_outbuf* col_outbuf_U;
dct_2d_col_inbuf_0* col_inbuf_0_U;
dct_2d_col_inbuf_0* col_inbuf_1_U;
dct_2d_col_inbuf_0* col_inbuf_2_U;
dct_2d_col_inbuf_0* col_inbuf_3_U;
dct_2d_col_inbuf_0* col_inbuf_4_U;
dct_2d_col_inbuf_0* col_inbuf_5_U;
dct_2d_col_inbuf_0* col_inbuf_6_U;
dct_2d_col_inbuf_0* col_inbuf_7_U;
dct_1d* grp_dct_1d_fu_373;
sc_signal< sc_lv<9> > ap_CS_fsm;
sc_signal< sc_logic > ap_CS_fsm_state1;
sc_signal< sc_lv<7> > indvar_flatten_reg_295;
sc_signal< sc_lv<4> > j_0_reg_306;
sc_signal< sc_lv<4> > i_1_reg_317;
sc_signal< sc_lv<7> > indvar_flatten19_reg_340;
sc_signal< sc_lv<4> > j_1_reg_351;
sc_signal< sc_lv<4> > i_3_reg_362;
sc_signal< sc_lv<1> > icmp_ln32_fu_416_p2;
sc_signal< sc_logic > ap_CS_fsm_state2;
sc_signal< sc_lv<4> > i_fu_422_p2;
sc_signal< sc_lv<4> > i_reg_626;
sc_signal< sc_lv<1> > icmp_ln37_fu_428_p2;
sc_signal< sc_lv<1> > icmp_ln37_reg_631;
sc_signal< sc_logic > ap_CS_fsm_pp0_stage0;
sc_signal< bool > ap_block_state4_pp0_stage0_iter0;
sc_signal< bool > ap_block_state5_pp0_stage0_iter1;
sc_signal< bool > ap_block_state6_pp0_stage0_iter2;
sc_signal< bool > ap_block_pp0_stage0_11001;
sc_signal< sc_lv<7> > add_ln37_fu_434_p2;
sc_signal< sc_logic > ap_enable_reg_pp0_iter0;
sc_signal< sc_lv<4> > select_ln40_fu_452_p3;
sc_signal< sc_lv<4> > select_ln40_reg_640;
sc_signal< sc_lv<4> > select_ln40_1_fu_460_p3;
sc_signal< sc_lv<4> > select_ln40_1_reg_645;
sc_signal< sc_lv<4> > select_ln40_1_reg_645_pp0_iter1_reg;
sc_signal< sc_lv<3> > trunc_ln40_fu_468_p1;
sc_signal< sc_lv<3> > trunc_ln40_reg_652;
sc_signal< sc_lv<3> > trunc_ln40_reg_652_pp0_iter1_reg;
sc_signal< sc_lv<4> > i_5_fu_472_p2;
sc_signal< sc_lv<1> > icmp_ln43_fu_514_p2;
sc_signal< sc_logic > ap_CS_fsm_state8;
sc_signal< sc_lv<4> > i_4_fu_520_p2;
sc_signal< sc_lv<4> > i_4_reg_670;
sc_signal< sc_lv<1> > icmp_ln48_fu_526_p2;
sc_signal< sc_lv<1> > icmp_ln48_reg_675;
sc_signal< sc_logic > ap_CS_fsm_pp1_stage0;
sc_signal< bool > ap_block_state10_pp1_stage0_iter0;
sc_signal< bool > ap_block_state11_pp1_stage0_iter1;
sc_signal< bool > ap_block_state12_pp1_stage0_iter2;
sc_signal< bool > ap_block_state13_pp1_stage0_iter3;
sc_signal< bool > ap_block_pp1_stage0_11001;
sc_signal< sc_lv<1> > icmp_ln48_reg_675_pp1_iter1_reg;
sc_signal< sc_lv<1> > icmp_ln48_reg_675_pp1_iter2_reg;
sc_signal< sc_lv<7> > add_ln48_fu_532_p2;
sc_signal< sc_logic > ap_enable_reg_pp1_iter0;
sc_signal< sc_lv<4> > select_ln51_fu_550_p3;
sc_signal< sc_lv<4> > select_ln51_reg_684;
sc_signal< sc_lv<4> > select_ln51_reg_684_pp1_iter1_reg;
sc_signal< sc_lv<4> > select_ln51_reg_684_pp1_iter2_reg;
sc_signal< sc_lv<4> > select_ln51_1_fu_558_p3;
sc_signal< sc_lv<4> > select_ln51_1_reg_690;
sc_signal< sc_lv<4> > select_ln51_1_reg_690_pp1_iter1_reg;
sc_signal< sc_lv<4> > select_ln51_1_reg_690_pp1_iter2_reg;
sc_signal< sc_lv<4> > i_6_fu_566_p2;
sc_signal< sc_lv<16> > col_outbuf_q0;
sc_signal< sc_lv<16> > col_outbuf_load_reg_707;
sc_signal< bool > ap_block_pp0_stage0_subdone;
sc_signal< sc_logic > ap_condition_pp0_exit_iter0_state4;
sc_signal< sc_logic > ap_enable_reg_pp0_iter1;
sc_signal< sc_logic > ap_enable_reg_pp0_iter2;
sc_signal< bool > ap_block_pp1_stage0_subdone;
sc_signal< sc_logic > ap_condition_pp1_exit_iter0_state10;
sc_signal< sc_logic > ap_enable_reg_pp1_iter1;
sc_signal< sc_logic > ap_enable_reg_pp1_iter2;
sc_signal< sc_logic > ap_enable_reg_pp1_iter3;
sc_signal< sc_lv<6> > row_outbuf_address0;
sc_signal< sc_logic > row_outbuf_ce0;
sc_signal< sc_logic > row_outbuf_we0;
sc_signal< sc_lv<16> > row_outbuf_q0;
sc_signal< sc_lv<6> > col_outbuf_address0;
sc_signal< sc_logic > col_outbuf_ce0;
sc_signal< sc_logic > col_outbuf_we0;
sc_signal< sc_lv<3> > col_inbuf_0_address0;
sc_signal< sc_logic > col_inbuf_0_ce0;
sc_signal< sc_logic > col_inbuf_0_we0;
sc_signal< sc_lv<16> > col_inbuf_0_q0;
sc_signal< sc_lv<3> > col_inbuf_1_address0;
sc_signal< sc_logic > col_inbuf_1_ce0;
sc_signal< sc_logic > col_inbuf_1_we0;
sc_signal< sc_lv<16> > col_inbuf_1_q0;
sc_signal< sc_lv<3> > col_inbuf_2_address0;
sc_signal< sc_logic > col_inbuf_2_ce0;
sc_signal< sc_logic > col_inbuf_2_we0;
sc_signal< sc_lv<16> > col_inbuf_2_q0;
sc_signal< sc_lv<3> > col_inbuf_3_address0;
sc_signal< sc_logic > col_inbuf_3_ce0;
sc_signal< sc_logic > col_inbuf_3_we0;
sc_signal< sc_lv<16> > col_inbuf_3_q0;
sc_signal< sc_lv<3> > col_inbuf_4_address0;
sc_signal< sc_logic > col_inbuf_4_ce0;
sc_signal< sc_logic > col_inbuf_4_we0;
sc_signal< sc_lv<16> > col_inbuf_4_q0;
sc_signal< sc_lv<3> > col_inbuf_5_address0;
sc_signal< sc_logic > col_inbuf_5_ce0;
sc_signal< sc_logic > col_inbuf_5_we0;
sc_signal< sc_lv<16> > col_inbuf_5_q0;
sc_signal< sc_lv<3> > col_inbuf_6_address0;
sc_signal< sc_logic > col_inbuf_6_ce0;
sc_signal< sc_logic > col_inbuf_6_we0;
sc_signal< sc_lv<16> > col_inbuf_6_q0;
sc_signal< sc_lv<3> > col_inbuf_7_address0;
sc_signal< sc_logic > col_inbuf_7_ce0;
sc_signal< sc_logic > col_inbuf_7_we0;
sc_signal< sc_lv<16> > col_inbuf_7_q0;
sc_signal< sc_logic > grp_dct_1d_fu_373_ap_start;
sc_signal< sc_logic > grp_dct_1d_fu_373_ap_done;
sc_signal< sc_logic > grp_dct_1d_fu_373_ap_idle;
sc_signal< sc_logic > grp_dct_1d_fu_373_ap_ready;
sc_signal< sc_lv<3> > grp_dct_1d_fu_373_src_address0;
sc_signal< sc_logic > grp_dct_1d_fu_373_src_ce0;
sc_signal< sc_lv<16> > grp_dct_1d_fu_373_src_q0;
sc_signal< sc_lv<3> > grp_dct_1d_fu_373_src1_address0;
sc_signal< sc_logic > grp_dct_1d_fu_373_src1_ce0;
sc_signal< sc_lv<16> > grp_dct_1d_fu_373_src1_q0;
sc_signal< sc_lv<3> > grp_dct_1d_fu_373_src2_address0;
sc_signal< sc_logic > grp_dct_1d_fu_373_src2_ce0;
sc_signal< sc_lv<16> > grp_dct_1d_fu_373_src2_q0;
sc_signal< sc_lv<3> > grp_dct_1d_fu_373_src3_address0;
sc_signal< sc_logic > grp_dct_1d_fu_373_src3_ce0;
sc_signal< sc_lv<16> > grp_dct_1d_fu_373_src3_q0;
sc_signal< sc_lv<3> > grp_dct_1d_fu_373_src4_address0;
sc_signal< sc_logic > grp_dct_1d_fu_373_src4_ce0;
sc_signal< sc_lv<16> > grp_dct_1d_fu_373_src4_q0;
sc_signal< sc_lv<3> > grp_dct_1d_fu_373_src5_address0;
sc_signal< sc_logic > grp_dct_1d_fu_373_src5_ce0;
sc_signal< sc_lv<16> > grp_dct_1d_fu_373_src5_q0;
sc_signal< sc_lv<3> > grp_dct_1d_fu_373_src6_address0;
sc_signal< sc_logic > grp_dct_1d_fu_373_src6_ce0;
sc_signal< sc_lv<16> > grp_dct_1d_fu_373_src6_q0;
sc_signal< sc_lv<3> > grp_dct_1d_fu_373_src7_address0;
sc_signal< sc_logic > grp_dct_1d_fu_373_src7_ce0;
sc_signal< sc_lv<16> > grp_dct_1d_fu_373_src7_q0;
sc_signal< sc_lv<4> > grp_dct_1d_fu_373_src_offset;
sc_signal< sc_lv<6> > grp_dct_1d_fu_373_dst_address0;
sc_signal< sc_logic > grp_dct_1d_fu_373_dst_ce0;
sc_signal< sc_logic > grp_dct_1d_fu_373_dst_we0;
sc_signal< sc_lv<16> > grp_dct_1d_fu_373_dst_d0;
sc_signal< sc_lv<4> > grp_dct_1d_fu_373_dst_offset;
sc_signal< sc_lv<4> > i_0_reg_283;
sc_signal< sc_logic > ap_CS_fsm_state3;
sc_signal< sc_lv<4> > ap_phi_mux_j_0_phi_fu_310_p4;
sc_signal< bool > ap_block_pp0_stage0;
sc_signal< sc_lv<4> > i_2_reg_328;
sc_signal< sc_logic > ap_CS_fsm_state9;
sc_signal< sc_logic > ap_CS_fsm_state7;
sc_signal< sc_lv<4> > ap_phi_mux_j_1_phi_fu_355_p4;
sc_signal< bool > ap_block_pp1_stage0;
sc_signal< sc_logic > grp_dct_1d_fu_373_ap_start_reg;
sc_signal< sc_lv<64> > zext_ln40_3_fu_498_p1;
sc_signal< sc_lv<64> > zext_ln40_fu_503_p1;
sc_signal< sc_lv<64> > zext_ln51_5_fu_592_p1;
sc_signal< sc_lv<64> > zext_ln51_3_fu_617_p1;
sc_signal< sc_lv<1> > icmp_ln39_fu_446_p2;
sc_signal< sc_lv<4> > j_fu_440_p2;
sc_signal< sc_lv<7> > tmp_fu_481_p3;
sc_signal< sc_lv<8> > zext_ln40_2_fu_488_p1;
sc_signal< sc_lv<8> > zext_ln40_1_fu_478_p1;
sc_signal< sc_lv<8> > add_ln40_fu_492_p2;
sc_signal< sc_lv<1> > icmp_ln50_fu_544_p2;
sc_signal< sc_lv<4> > j_2_fu_538_p2;
sc_signal< sc_lv<7> > tmp_2_fu_575_p3;
sc_signal< sc_lv<8> > zext_ln51_fu_572_p1;
sc_signal< sc_lv<8> > zext_ln51_4_fu_582_p1;
sc_signal< sc_lv<8> > add_ln51_1_fu_586_p2;
sc_signal< sc_lv<7> > tmp_1_fu_597_p3;
sc_signal< sc_lv<8> > zext_ln51_2_fu_608_p1;
sc_signal< sc_lv<8> > zext_ln51_1_fu_604_p1;
sc_signal< sc_lv<8> > add_ln51_fu_611_p2;
sc_signal< sc_logic > ap_CS_fsm_state14;
sc_signal< sc_lv<9> > ap_NS_fsm;
sc_signal< sc_logic > ap_idle_pp0;
sc_signal< sc_logic > ap_enable_pp0;
sc_signal< sc_logic > ap_idle_pp1;
sc_signal< sc_logic > ap_enable_pp1;
static const sc_logic ap_const_logic_1;
static const sc_logic ap_const_logic_0;
static const sc_lv<9> ap_ST_fsm_state1;
static const sc_lv<9> ap_ST_fsm_state2;
static const sc_lv<9> ap_ST_fsm_state3;
static const sc_lv<9> ap_ST_fsm_pp0_stage0;
static const sc_lv<9> ap_ST_fsm_state7;
static const sc_lv<9> ap_ST_fsm_state8;
static const sc_lv<9> ap_ST_fsm_state9;
static const sc_lv<9> ap_ST_fsm_pp1_stage0;
static const sc_lv<9> ap_ST_fsm_state14;
static const bool ap_const_boolean_1;
static const sc_lv<32> ap_const_lv32_0;
static const sc_lv<32> ap_const_lv32_1;
static const sc_lv<32> ap_const_lv32_3;
static const bool ap_const_boolean_0;
static const sc_lv<1> ap_const_lv1_0;
static const sc_lv<32> ap_const_lv32_5;
static const sc_lv<32> ap_const_lv32_7;
static const sc_lv<1> ap_const_lv1_1;
static const sc_lv<4> ap_const_lv4_0;
static const sc_lv<32> ap_const_lv32_2;
static const sc_lv<7> ap_const_lv7_0;
static const sc_lv<32> ap_const_lv32_6;
static const sc_lv<32> ap_const_lv32_4;
static const sc_lv<3> ap_const_lv3_6;
static const sc_lv<3> ap_const_lv3_5;
static const sc_lv<3> ap_const_lv3_4;
static const sc_lv<3> ap_const_lv3_3;
static const sc_lv<3> ap_const_lv3_2;
static const sc_lv<3> ap_const_lv3_1;
static const sc_lv<3> ap_const_lv3_0;
static const sc_lv<3> ap_const_lv3_7;
static const sc_lv<4> ap_const_lv4_8;
static const sc_lv<4> ap_const_lv4_1;
static const sc_lv<7> ap_const_lv7_40;
static const sc_lv<7> ap_const_lv7_1;
static const sc_lv<32> ap_const_lv32_8;
// Thread declarations
void thread_ap_clk_no_reset_();
void thread_add_ln37_fu_434_p2();
void thread_add_ln40_fu_492_p2();
void thread_add_ln48_fu_532_p2();
void thread_add_ln51_1_fu_586_p2();
void thread_add_ln51_fu_611_p2();
void thread_ap_CS_fsm_pp0_stage0();
void thread_ap_CS_fsm_pp1_stage0();
void thread_ap_CS_fsm_state1();
void thread_ap_CS_fsm_state14();
void thread_ap_CS_fsm_state2();
void thread_ap_CS_fsm_state3();
void thread_ap_CS_fsm_state7();
void thread_ap_CS_fsm_state8();
void thread_ap_CS_fsm_state9();
void thread_ap_block_pp0_stage0();
void thread_ap_block_pp0_stage0_11001();
void thread_ap_block_pp0_stage0_subdone();
void thread_ap_block_pp1_stage0();
void thread_ap_block_pp1_stage0_11001();
void thread_ap_block_pp1_stage0_subdone();
void thread_ap_block_state10_pp1_stage0_iter0();
void thread_ap_block_state11_pp1_stage0_iter1();
void thread_ap_block_state12_pp1_stage0_iter2();
void thread_ap_block_state13_pp1_stage0_iter3();
void thread_ap_block_state4_pp0_stage0_iter0();
void thread_ap_block_state5_pp0_stage0_iter1();
void thread_ap_block_state6_pp0_stage0_iter2();
void thread_ap_condition_pp0_exit_iter0_state4();
void thread_ap_condition_pp1_exit_iter0_state10();
void thread_ap_done();
void thread_ap_enable_pp0();
void thread_ap_enable_pp1();
void thread_ap_idle();
void thread_ap_idle_pp0();
void thread_ap_idle_pp1();
void thread_ap_phi_mux_j_0_phi_fu_310_p4();
void thread_ap_phi_mux_j_1_phi_fu_355_p4();
void thread_ap_ready();
void thread_col_inbuf_0_address0();
void thread_col_inbuf_0_ce0();
void thread_col_inbuf_0_we0();
void thread_col_inbuf_1_address0();
void thread_col_inbuf_1_ce0();
void thread_col_inbuf_1_we0();
void thread_col_inbuf_2_address0();
void thread_col_inbuf_2_ce0();
void thread_col_inbuf_2_we0();
void thread_col_inbuf_3_address0();
void thread_col_inbuf_3_ce0();
void thread_col_inbuf_3_we0();
void thread_col_inbuf_4_address0();
void thread_col_inbuf_4_ce0();
void thread_col_inbuf_4_we0();
void thread_col_inbuf_5_address0();
void thread_col_inbuf_5_ce0();
void thread_col_inbuf_5_we0();
void thread_col_inbuf_6_address0();
void thread_col_inbuf_6_ce0();
void thread_col_inbuf_6_we0();
void thread_col_inbuf_7_address0();
void thread_col_inbuf_7_ce0();
void thread_col_inbuf_7_we0();
void thread_col_outbuf_address0();
void thread_col_outbuf_ce0();
void thread_col_outbuf_we0();
void thread_grp_dct_1d_fu_373_ap_start();
void thread_grp_dct_1d_fu_373_dst_offset();
void thread_grp_dct_1d_fu_373_src1_q0();
void thread_grp_dct_1d_fu_373_src2_q0();
void thread_grp_dct_1d_fu_373_src3_q0();
void thread_grp_dct_1d_fu_373_src4_q0();
void thread_grp_dct_1d_fu_373_src5_q0();
void thread_grp_dct_1d_fu_373_src6_q0();
void thread_grp_dct_1d_fu_373_src7_q0();
void thread_grp_dct_1d_fu_373_src_offset();
void thread_grp_dct_1d_fu_373_src_q0();
void thread_i_4_fu_520_p2();
void thread_i_5_fu_472_p2();
void thread_i_6_fu_566_p2();
void thread_i_fu_422_p2();
void thread_icmp_ln32_fu_416_p2();
void thread_icmp_ln37_fu_428_p2();
void thread_icmp_ln39_fu_446_p2();
void thread_icmp_ln43_fu_514_p2();
void thread_icmp_ln48_fu_526_p2();
void thread_icmp_ln50_fu_544_p2();
void thread_in_block_0_address0();
void thread_in_block_0_ce0();
void thread_in_block_1_address0();
void thread_in_block_1_ce0();
void thread_in_block_2_address0();
void thread_in_block_2_ce0();
void thread_in_block_3_address0();
void thread_in_block_3_ce0();
void thread_in_block_4_address0();
void thread_in_block_4_ce0();
void thread_in_block_5_address0();
void thread_in_block_5_ce0();
void thread_in_block_6_address0();
void thread_in_block_6_ce0();
void thread_in_block_7_address0();
void thread_in_block_7_ce0();
void thread_j_2_fu_538_p2();
void thread_j_fu_440_p2();
void thread_out_block_address0();
void thread_out_block_ce0();
void thread_out_block_d0();
void thread_out_block_we0();
void thread_row_outbuf_address0();
void thread_row_outbuf_ce0();
void thread_row_outbuf_we0();
void thread_select_ln40_1_fu_460_p3();
void thread_select_ln40_fu_452_p3();
void thread_select_ln51_1_fu_558_p3();
void thread_select_ln51_fu_550_p3();
void thread_tmp_1_fu_597_p3();
void thread_tmp_2_fu_575_p3();
void thread_tmp_fu_481_p3();
void thread_trunc_ln40_fu_468_p1();
void thread_zext_ln40_1_fu_478_p1();
void thread_zext_ln40_2_fu_488_p1();
void thread_zext_ln40_3_fu_498_p1();
void thread_zext_ln40_fu_503_p1();
void thread_zext_ln51_1_fu_604_p1();
void thread_zext_ln51_2_fu_608_p1();
void thread_zext_ln51_3_fu_617_p1();
void thread_zext_ln51_4_fu_582_p1();
void thread_zext_ln51_5_fu_592_p1();
void thread_zext_ln51_fu_572_p1();
void thread_ap_NS_fsm();
};
}
using namespace ap_rtl;
#endif
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
// Version: 2019.2
// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _pqcrystals_dilithium_9_HH_
#define _pqcrystals_dilithium_9_HH_
#include "systemc.h"
#include "AESL_pkg.h"
namespace ap_rtl {
struct pqcrystals_dilithium_9 : public sc_module {
// Port declarations 11
sc_in_clk ap_clk;
sc_in< sc_logic > ap_rst;
sc_in< sc_logic > ap_start;
sc_out< sc_logic > ap_done;
sc_out< sc_logic > ap_idle;
sc_out< sc_logic > ap_ready;
sc_out< sc_lv<10> > v_vec_coeffs_address0;
sc_out< sc_logic > v_vec_coeffs_ce0;
sc_out< sc_logic > v_vec_coeffs_we0;
sc_out< sc_lv<32> > v_vec_coeffs_d0;
sc_in< sc_lv<32> > v_vec_coeffs_q0;
// Module declarations
pqcrystals_dilithium_9(sc_module_name name);
SC_HAS_PROCESS(pqcrystals_dilithium_9);
~pqcrystals_dilithium_9();
sc_trace_file* mVcdFile;
sc_signal< sc_lv<4> > ap_CS_fsm;
sc_signal< sc_logic > ap_CS_fsm_state1;
sc_signal< sc_lv<3> > i_fu_75_p2;
sc_signal< sc_lv<3> > i_reg_145;
sc_signal< sc_logic > ap_CS_fsm_state2;
sc_signal< sc_lv<12> > zext_ln46_fu_89_p1;
sc_signal< sc_lv<12> > zext_ln46_reg_150;
sc_signal< sc_lv<1> > icmp_ln202_fu_69_p2;
sc_signal< sc_lv<9> > i_2_fu_99_p2;
sc_signal< sc_lv<9> > i_2_reg_158;
sc_signal< sc_logic > ap_CS_fsm_state3;
sc_signal< sc_lv<10> > v_vec_coeffs_addr_reg_163;
sc_signal< sc_lv<1> > icmp_ln50_fu_93_p2;
sc_signal< sc_lv<3> > i_0_reg_47;
sc_signal< sc_lv<9> > i_0_i_reg_58;
sc_signal< sc_logic > ap_CS_fsm_state4;
sc_signal< sc_lv<64> > zext_ln51_1_fu_114_p1;
sc_signal< sc_lv<11> > tmp_fu_81_p3;
sc_signal< sc_lv<12> > zext_ln51_fu_105_p1;
sc_signal< sc_lv<12> > add_ln51_fu_109_p2;
sc_signal< sc_lv<1> > tmp_1_fu_119_p3;
sc_signal< sc_lv<32> > select_ln51_fu_127_p3;
sc_signal< sc_lv<4> > ap_NS_fsm;
static const sc_logic ap_const_logic_1;
static const sc_logic ap_const_logic_0;
static const sc_lv<4> ap_ST_fsm_state1;
static const sc_lv<4> ap_ST_fsm_state2;
static const sc_lv<4> ap_ST_fsm_state3;
static const sc_lv<4> ap_ST_fsm_state4;
static const sc_lv<32> ap_const_lv32_0;
static const sc_lv<32> ap_const_lv32_1;
static const sc_lv<1> ap_const_lv1_0;
static const sc_lv<32> ap_const_lv32_2;
static const sc_lv<3> ap_const_lv3_0;
static const sc_lv<1> ap_const_lv1_1;
static const sc_lv<9> ap_const_lv9_0;
static const sc_lv<32> ap_const_lv32_3;
static const sc_lv<3> ap_const_lv3_4;
static const sc_lv<3> ap_const_lv3_1;
static const sc_lv<8> ap_const_lv8_0;
static const sc_lv<9> ap_const_lv9_100;
static const sc_lv<9> ap_const_lv9_1;
static const sc_lv<32> ap_const_lv32_1F;
static const sc_lv<32> ap_const_lv32_7FE001;
static const bool ap_const_boolean_1;
// Thread declarations
void thread_ap_clk_no_reset_();
void thread_add_ln51_fu_109_p2();
void thread_ap_CS_fsm_state1();
void thread_ap_CS_fsm_state2();
void thread_ap_CS_fsm_state3();
void thread_ap_CS_fsm_state4();
void thread_ap_done();
void thread_ap_idle();
void thread_ap_ready();
void thread_i_2_fu_99_p2();
void thread_i_fu_75_p2();
void thread_icmp_ln202_fu_69_p2();
void thread_icmp_ln50_fu_93_p2();
void thread_select_ln51_fu_127_p3();
void thread_tmp_1_fu_119_p3();
void thread_tmp_fu_81_p3();
void thread_v_vec_coeffs_address0();
void thread_v_vec_coeffs_ce0();
void thread_v_vec_coeffs_d0();
void thread_v_vec_coeffs_we0();
void thread_zext_ln46_fu_89_p1();
void thread_zext_ln51_1_fu_114_p1();
void thread_zext_ln51_fu_105_p1();
void thread_ap_NS_fsm();
};
}
using namespace ap_rtl;
#endif
|
#ifndef blocking_IFS
#define blocking_IFS
#include "systemc.h"
template<typename T>
class blocking_in_if : virtual public sc_interface
{
public:
virtual void read(T & out) = 0;
virtual bool nb_read(T & out) = 0;
};
template<typename T>
class blocking_out_if : virtual public sc_interface
{
public:
virtual void write(const T & val) = 0;
virtual bool nb_write(const T & val) = 0;
};
#endif
|
/****************************************************************************
*
* Copyright (c) 2015, Cadence Design Systems. All Rights Reserved.
*
* This file contains confidential information that may not be
* distributed under any circumstances without the written permision
* of Cadence Design Systems.
*
****************************************************************************/
#ifndef _DUT_WRAP_INCLUDED_
#define _DUT_WRAP_INCLUDED_
/* Save ioConfig define values for parent module and define those for this module's ioConfigs. */
#if defined(CYNTHVLG)
#include <systemc.h>
#define dut_wrapper dut
/* This is the section that is seen during processing by cynthVLG of a module
* that instantiates the module defined by this wrapper.
*/
SC_MODULE(dut)
{
public:
sc_in< bool > clk;
sc_in< bool > rst;
sc_out< bool > din_busy;
sc_in< bool > din_vld;
sc_in< sc_uint< 8 > > din_data;
sc_in< bool > dout_busy;
sc_out< bool > dout_vld;
sc_out< sc_uint< 11 > > dout_data;
sc_out< bool > mem_WE0;
sc_out< sc_uint< 8 > > mem_DIN0;
sc_in< sc_uint< 8 > > mem_DOUT0;
sc_out< sc_uint< 6 > > mem_A0;
sc_out< bool > mem_REQ0;
SC_CTOR(dut);
};
#elif defined(CYNTHHL) || defined(BDW_EXTRACT)
/* This is the section seen during processing by cynthHL or bdw_extract of a module
* that instantiates the module defined by this wrapper.
*/
#include <systemc.h>
#include "cynw_p2p.h"
#include "cyn_enums.h"
#include "RAM_64x8.h"
#define dut_wrapper dut
/* Only port declarations are required for nested modules.
*/
SC_MODULE(dut)
{
public:
sc_in< bool > clk;
sc_in< bool > rst;
cynw::cynw_p2p_base_in <sc_dt::sc_uint <(int)8 >, CYN::cyn_enum <(int)1 > > din;
cynw::cynw_p2p_base_out <sc_dt::sc_uint <(int)11 >, CYN::cyn_enum <(int)1 > > dout;
RAM_64x8::port <CYN::cyn_enum <(int)1 >, sc_dt::sc_uint <(int)8 >, (HLS::HLS_INDEX_MAPPING_OPTIONS)256 > mem;
SC_HAS_PROCESS(dut);
dut_wrapper( sc_module_name name = sc_module_name( sc_gen_unique_name("dut")) );
};
#else
#include <esc.h>
/* This is the section seen during processing by gcc either when the module
* itself is compiled, or when a module that instantiates it is compiled.
*/
struct dut;
struct dut_cosim;
struct dut_cycsim;
struct dut_rtl;
#ifdef BDW_COWARE
#include "dut_coware.h"
#endif
#include "cynw_p2p.h"
#include "cyn_enums.h"
#include "RAM_64x8.h"
// Declaration of wrapper with BEH level ports
SC_MODULE(dut_wrapper)
{
public:
sc_in< bool > clk;
sc_in< bool > rst;
cynw::cynw_p2p_base_in <sc_dt::sc_uint <(int)8 >, CYN::cyn_enum <(int)1 > > din;
cynw::cynw_p2p_base_out <sc_dt::sc_uint <(int)11 >, CYN::cyn_enum <(int)1 > > dout;
RAM_64x8::port <CYN::cyn_enum <(int)1 >, sc_dt::sc_uint <(int)8 >, (HLS::HLS_INDEX_MAPPING_OPTIONS)256 > mem;
// These signals are used to connect structured ports or ports that need
// type conversion to the RTL ports.
enum Representation { BDWRep_None, BDWRep_Behavioral, BDWRep_RTL_C, BDWRep_RTL_HDL, BDWRep_Gates, BDWRep_CYC_HDL };
static const char * simConfigName();
static Representation lookupRepresentation( const char* instName );
// create the netlist
void InitInstances( );
void InitThreads();
// delete the netlist
void DeleteInstances();
void CloseTrace();
void start_of_simulation();
void end_of_simulation();
// The following threads are used to connect structured ports to the actual
// RTL ports.
SC_HAS_PROCESS(dut_wrapper);
dut_wrapper( sc_module_name name = sc_module_name( sc_gen_unique_name("dut")) )
: sc_module(name)
,clk("clk")
,rst("rst")
,din("din")
,dout("dout")
,mem("mem")
,dut0(0), dut_cosim0(0), dut_rtl0(0), dut_cycsim0(0)
{
InitInstances( );
InitThreads();
}
// destructor
~dut_wrapper()
{
DeleteInstances();
CloseTrace();
}
bool isBEH() { return ( dut_wrapper::lookupRepresentation( name() ) == BDWRep_Behavioral ); }
bool isRTL_C() { return ( dut_wrapper::lookupRepresentation( name() ) == BDWRep_RTL_C ); }
bool isRTL_V() { return ( dut_wrapper::lookupRepresentation( name() ) == BDWRep_RTL_HDL ); }
bool isGATES_V() { return ( dut_wrapper::lookupRepresentation( name() ) == BDWRep_Gates ); }
bool isCosim() { return ( isRTL_V() || isGATES_V() ); }
bool isCycsim() { return ( dut_wrapper::lookupRepresentation( name() ) == BDWRep_CYC_HDL ); }
dut* behModule() { return dut0; }
dut_cosim* cosimModule() { return dut_cosim0; }
dut_cycsim* cycsimModule() { return dut_cycsim0; }
dut_rtl* rtlModule() { return dut_rtl0; }
dut* dut0;
dut_cosim* dut_cosim0;
dut_rtl* dut_rtl0;
dut_cycsim* dut_cycsim0;
};
// Declaration of wrapper with RTL level ports
SC_MODULE(dut_wrapper_r)
{
public:
sc_in< bool > clk;
sc_in< bool > rst;
sc_out< bool > din_busy;
sc_in< bool > din_vld;
sc_in< sc_uint< 8 > > din_data;
sc_in< bool > dout_busy;
sc_out< bool > dout_vld;
sc_out< sc_uint< 11 > > dout_data;
sc_out< bool > mem_WE0;
sc_out< sc_uint< 8 > > mem_DIN0;
sc_in< sc_uint< 8 > > mem_DOUT0;
sc_out< sc_uint< 6 > > mem_A0;
sc_out< bool > mem_REQ0;
// These signals are used to connect structured ports or ports that need
// type conversion to the RTL ports.
enum Representation { BDWRep_None, BDWRep_Behavioral, BDWRep_RTL_C, BDWRep_RTL_HDL, BDWRep_Gates, BDWRep_CYC_HDL };
static const char * simConfigName();
static Representation lookupRepresentation( const char* instName );
// create the netlist
void InitInstances();
void InitThreads();
// delete the netlist
void DeleteInstances();
void CloseTrace();
void start_of_simulation();
void end_of_simulation();
// The following threads are used to connect structured ports to the actual
// RTL ports.
SC_HAS_PROCESS(dut_wrapper_r);
dut_wrapper_r( sc_module_name name = sc_module_name( sc_gen_unique_name("dut")) )
: sc_module(name)
,clk("clk")
,rst("rst")
,din_busy("din_busy")
,din_vld("din_vld")
,din_data("din_data")
,dout_busy("dout_busy")
,dout_vld("dout_vld")
,dout_data("dout_data")
,mem_WE0("mem_WE0")
,mem_DIN0("mem_DIN0")
,mem_DOUT0("mem_DOUT0")
,mem_A0("mem_A0")
,mem_REQ0("mem_REQ0")
,dut0(0), dut_cosim0(0), dut_rtl0(0), dut_cycsim0(0)
{
InitInstances();
InitThreads();
end_module();
}
// destructor
~dut_wrapper_r()
{
DeleteInstances();
CloseTrace();
}
bool isBEH() { return ( dut_wrapper_r::lookupRepresentation( name() ) == BDWRep_Behavioral ); }
bool isRTL_C() { return ( dut_wrapper_r::lookupRepresentation( name() ) == BDWRep_RTL_C ); }
bool isRTL_V() { return ( dut_wrapper_r::lookupRepresentation( name() ) == BDWRep_RTL_HDL ); }
bool isGATES_V() { return ( dut_wrapper_r::lookupRepresentation( name() ) == BDWRep_Gates ); }
bool isCosim() { return ( isRTL_V() || isGATES_V() ); }
bool isCycsim() { return ( dut_wrapper_r::lookupRepresentation( name() ) == BDWRep_CYC_HDL ); }
dut* behModule() { return dut0; }
dut_cosim* cosimModule() { return dut_cosim0; }
dut_cycsim* cycsimModule() { return dut_cycsim0; }
dut_rtl* rtlModule() { return dut_rtl0; }
protected:
dut* dut0;
dut_cosim* dut_cosim0;
dut_rtl* dut_rtl0;
dut_cycsim* dut_cycsim0;
};
#endif
/* Restore ioConfig define values for parent module. */
#endif /* */
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
#ifndef _Mayo_keygen_no_zynq_Ground0_0_H_
#define _Mayo_keygen_no_zynq_Ground0_0_H_
#include "xlconstant_v1_1_7.h"
#include "systemc.h"
class Mayo_keygen_no_zynq_Ground0_0 : public sc_module {
public:
xlconstant_v1_1_7<1,0> mod;
sc_out< sc_bv<1> > dout;
Mayo_keygen_no_zynq_Ground0_0 (sc_core::sc_module_name name);
};
#endif
|
//
//------------------------------------------------------------//
// Copyright 2009-2012 Mentor Graphics Corporation //
// All Rights Reserved Worldwid //
// //
// Licensed under the Apache License, Version 2.0 (the //
// "License"); you may not use this file except in //
// compliance with the License. You may obtain a copy of //
// the License at //
// //
// http://www.apache.org/licenses/LICENSE-2.0 //
// //
// Unless required by applicable law or agreed to in //
// writing, software distributed under the License is //
// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR //
// CONDITIONS OF ANY KIND, either express or implied. See //
// the License for the specific language governing //
// permissions and limitations under the License. //
//------------------------------------------------------------//
//-----------------------------------------------------------------------------
// Title: UVMC Command API
//
// This section describes the API for accessing and controlling UVM simulation
// in SystemVerilog from SystemC (or C or C++). To use, the SV side must have
// called the ~uvmc_init~, which starts a background process that receives and
// processes incoming commands.
//
// The UVM Connect library provides an SystemC API for accessing SystemVeilog
// UVM during simulation. With this API users can:
//
// - Wait for a UVM to reach a given simulation phase
// - Raise and drop objections
// - Set and get UVM configuration
// - Send UVM report messages
// - Set type and instance overrides in the UVM factory
// - Print UVM component topology
//
// While most commands are compatible with C, a few functions take object
// arguments or block on sc_events. Therefore, SystemC is currently the only
// practical source language for using the UVM Command API. Future releases may
// separate the subset of C-compatible functions into a separate shared library
// that would not require linking in SystemC.
//
// The following may appear in a future release, based on demand
//
// - Callbacks on phase and objection activity
// - Receive UVM report messages, i.e. SC-side acts as report catcher or server
// - Integration with SystemCs sc_report_handler facility
// - Print factory contents, config db contents, and other UVM information
// - Separate command layer into SC, C++, and C-accessible components; i.e.
// not require SystemC for non-SystemC-dependent functions
//
// The following sections provide details and examples for each command in the
// UVM Command API. To enable access to the UVM command layer, you must call
// the uvmc_cmd_init function from an initial block in a top-level module as in
// the following example:
//
// SystemVerilog:
//
//| module sv_main;
//|
//| import uvm_pkg::*;
//| import uvmc_pkg::*;
//|
//| initial begin
//| uvmc_cmd_init();
//| run_test();
//| end
//|
//| endmodule
//
// SystemC-side calls to the UVM Command API will block until SystemVerilog has
// finished elaboration and the uvmc_cmd_init function has been called. Because
// any call to the UVM Command layer may block, calls must be made from within
// thread processes.
//
// All code provided in the UVM Command descriptions that follow are SystemC
// unless stated otherwise.
#ifndef UVMC_COMMANDS_H
#define UVMC_COMMANDS_H
#include "svdpi.h"
#include <string>
#include <map>
#include <vector>
#include <iomanip>
#include <systemc.h>
#include <tlm.h>
using namespace sc_core;
using namespace sc_dt;
using namespace tlm;
using std::string;
using std::map;
using std::vector;
using sc_core::sc_semaphore;
#include "uvmc_common.h"
#include "uvmc_convert.h"
extern "C" {
//------------------------------------------------------------------------------
// Group: Enumeration Constants
//
// The following enumeration constants are used in various UVM Commands:
//------------------------------------------------------------------------------
// Enum: uvmc_phase_state
//
// The state of a UVM phase
//
// UVM_PHASE_DORMANT - Phase has not started yet
// UVM_PHASE_STARTED - Phase has started
// UVM_PHASE_EXECUTING - Phase is executing
// UVM_PHASE_READY_TO_END - Phase is ready to end
// UVM_PHASE_ENDED - Phase has ended
// UVM_PHASE_DONE - Phase has completed
//
enum uvmc_phase_state {
UVM_PHASE_DORMANT = 1,
UVM_PHASE_SCHEDULED = 2,
UVM_PHASE_SYNCING = 4,
UVM_PHASE_STARTED = 8,
UVM_PHASE_EXECUTING = 16,
UVM_PHASE_READY_TO_END = 32,
UVM_PHASE_ENDED = 64,
UVM_PHASE_CLEANUP = 128,
UVM_PHASE_DONE = 256,
UVM_PHASE_JUMPING = 512
};
// Enum: uvmc_report_severity
//
// The severity of a report
//
// UVM_INFO - Informative message. Verbosity settings affect whether
// they are printed.
// UVM_WARNING - Warning. Not affected by verbosity settings.
// UVM_ERROR - Error. Error counter incremented by default. Not affected
// by verbosity settings.
// UVM_FATAL - Unrecoverable error. SV simulation will end immediately.
//
enum uvmc_report_severity {
UVM_INFO,
UVM_WARNING,
UVM_ERROR,
UVM_FATAL
};
// Enum: uvmc_report_verbosity
//
// The verbosity level assigned to UVM_INFO reports
//
// UVM_NONE - report will always be issued (unaffected by
// verbosity level)
// UVM_LOW - report is issued at low verbosity setting and higher
// UVM_MEDIUM - report is issued at medium verbosity and higher
// UVM_HIGH - report is issued at high verbosity and higher
// UVM_FULL - report is issued only when verbosity is set to full
//
enum uvmc_report_verbosity {
UVM_NONE = 0,
UVM_LOW = 100,
UVM_MEDIUM = 200,
UVM_HIGH = 300,
UVM_FULL = 400
};
// Enum: uvmc_wait_op
//
// The relational operator to apply in <uvmc_wait_for_phase> calls
//
// UVM_LT - Wait until UVM is before the given phase
// UVM_LTE - Wait until UVM is before or at the given phase
// UVM_NE - Wait until UVM is not at the given phase
// UVM_EQ - Wait until UVM is at the given phase
// UVM_GT - Wait until UVM is after the given phase
// UVM_GTE - Wait until UVM is at or after the given phase
//
enum uvmc_wait_op {
UVM_LT,
UVM_LTE,
UVM_NE,
UVM_EQ,
UVM_GT,
UVM_GTE
};
void wait_sv_ready();
} // extern "C"
//------------------------------------------------------------------------------
// UVM COMMANDS
extern "C" {
// Internal API (SV DPI Export Functions)
void UVMC_print_topology(const char* context="", int depth=-1);
bool UVMC_report_enabled (const char* context,
int verbosity,
int severity,
const char* id);
void UVMC_set_report_verbosity(int level,
const char* context,
bool recurse=0);
void UVMC_report (int severity,
const char* id,
const char* message,
int verbosity,
const char* context,
const char* filename,
int line);
// up to 64 bits
void UVMC_set_config_int (const char* context, const char* inst_name,
const char* field_name, uint64 value);
void UVMC_set_config_object (const char* type_name,
const char* context, const char* inst_name,
const char* field_name, const bits_t *value);
void UVMC_set_config_string (const char* context, const char* inst_name,
const char* field_name, const char* value);
bool UVMC_get_config_int (const char* context, const char* inst_name,
const char* field_name, uint64 *value);
bool UVMC_get_config_object (const char* type_name,
const char* context, const char* inst_name,
const char* field_name, bits_t* bits);
bool UVMC_get_config_string (const char* context, const char* inst_name,
const char* field_name, const char** value);
void UVMC_raise_objection (const char* name, const char* context="",
const char* description="", unsigned int count=1);
void UVMC_drop_objection (const char* name, const char* context="",
const char* description="", unsigned int count=1);
void UVMC_print_factory (int all_types=1);
void UVMC_set_factory_inst_override
(const char* original_type_name,
const char* override_type_name,
const char* full_inst_path);
void UVMC_set_factory_type_override (const char* original_type_name,
const char* override_type_name,
bool replace=1);
void UVMC_debug_factory_create (const char* requested_type,
const char* context="");
void UVMC_find_factory_override (const char* requested_type,
const char* context,
const char** override_type_name);
int UVMC_wait_for_phase_request(const char *phase, int state, int op);
void UVMC_get_uvm_version(unsigned int *major, unsigned int *minor, char **fix);
bool SV2C_phase_notification(int id);
bool SV2C_sv_ready();
void uvmc_set_scope(); // internal
} // extern "C"
extern "C" {
//------------------------------------------------------------------------------
// Group: Topology
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Function: uvmc_print_topology
//
// Prints the current UVM testbench topology.
//
// If called prior to UVM completing the build phase,
// the topology will be incomplete.
//
// Arguments:
//
// context - The hierarchical path of the component from which to start printing
// topology. If unspecified, topology printing will begin at
// uvm_top. Multiple components can be specified by using glob
// wildcards (* and ?), e.g. "top.env.*.driver". You can also specify
// a POSIX extended regular expression by enclosing the contxt in
// forward slashes, e.g. "/a[hp]b/". Default: "" (uvm_top)
//
// depth - The number of levels of hierarchy to print. If not specified,
// all levels of hierarchy starting from the given context are printed.
// Default: -1 (recurse all children)
//------------------------------------------------------------------------------
//
void uvmc_print_topology (const char *context="", int depth=-1);
//------------------------------------------------------------------------------
// Group: Reporting
//
// The reporting API provides the ability to issue UVM reports, set verbosity,
// and other reporting features.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Function: uvmc_report_enabled
//
// Returns true if a report at the specified verbosity, severity, and id would
// be emitted if made within the specified component contxt.
//
// The primary purpose of this command is to determine whether a report has a
// chance of being emitted before incurring the high run-time overhead of
// formatting the string message.
//
// A report at severity UVM_INFO is ignored if its verbosity is greater than
// the verbosity configured for the component in which it is issued. Reports at
// other severities are not affected by verbosity settings.
//
// If the action of a report with the specified severity and id is configured
// as UVM_NO_ACTION within the specified component contxt.
//
// Filtration by any registered report_catchers is not considered.
//
// Arguments:
//
// verbosity - The uvmc_report_verbosity of the hypothetical report.
//
// severity - The <uvmc_report_severity> of the hypothetical report.
// Default: UVM_INFO.
//
// id - The identifier string of the hypothetical report. Must be an
// exact match. If not specified, then uvmc_report_enabled checks
// only if UVM_NO_ACTION is the configured action for the given
// severity at the specified context. Default: "" (unspecified)
//
// context - The hierarchical path of the component that would issue the
// hypothetical report. If not specified, the context is global,
// i.e. uvm_top. Reports not issued by components come from uvm_top.
// Default: "" (unspecified)
//
// Example:
//
//| if (uvmc_report_enabled(UVM_HIGH, UVM_INFO, "PRINT_TRANS") {
//| string detailed_msg;
//| ...prepare message string here...
//| uvmc_report(UVM_INFO, "PRINT_TRANS", detailed_msg, UVM_HIGH);
//| }
//------------------------------------------------------------------------------
//
bool uvmc_report_enabled (int verbosity,
int severity=UVM_INFO,
const char* id="",
const char* context="");
//------------------------------------------------------------------------------
// Function: uvmc_set_report_verbosity
//
// Sets the run-time verbosity level for all UVM_INFO-severity reports issued
// by the component(s) at the specified context. Any report from the component
// context whose verbosity exceeds this maximum will be ignored.
//
// Reports issued by SC via uvmc_report are affected only by the verbosity level
// setting for the global context, i.e. context="". To have finer-grained
// control over SC-issued reports, register a uvm_report_catcher with uvm_top.
//
// Arguments:
//
// level - The verbosity level. Specify UVM_NONE, UVM_LOW, UVM_MEDIUM,
// UVM_HIGH, or UVM_FULL. Required.
//
// context - The hierarchical path of the component. Multiple components can be
// specified by using glob wildcards * and ?, e.g. "top.env.*.driver".
// You can also specify a POSIX extended regular expression by
// enclosing the contxt in forward slashes, e.g. "/a[hp]b/".
// Default: "" (uvm_top)
//
// recurse - If true, sets the verbosity of all descendents of the component(s)
// matching context. Default:false
//
// Examples:
//
// Set global UVM report verbosity to maximum (FULL) output:
//
// | uvmc_set_report_verbosity(UVM_FULL);
//
// Disable all filterable INFO reports for the top.env.agent1.driver,
// but none of its children:
//
// | uvmc_set_report_verbosity(UVM_NONE, "top.env.agent1.driver");
//
// Set report verbosity for all components to UVM_LOW, except for the
// troublemaker component, which gets UVM_HIGH verbosity:
//
// | uvmc_set_report_verbosity(UVM_LOW, true);
// | uvmc_set_report_verbosity(UVM_HIGH, "top.env.troublemaker");
//
// In the last example, the recursion flag is set to false, so all of
// troublemaker's children, if any, will remain at UVM_LOW verbosity.
//------------------------------------------------------------------------------
void uvmc_set_report_verbosity (int level,
const char* context="",
bool recurse=0);
//------------------------------------------------------------------------------
// Function: uvmc_report
//
// Send a report to UVM for processing, subject to possible filtering by
// verbosity, action, and active report catchers.
//
// See uvmc_report_enabled to learn how a report may be filtered.
//
// The UVM report mechanism is used instead of $display and other ad hoc
// approaches to ensure consistent output and to control whether a report is
// issued and what if any actions are taken when it is issued. All reporting
// methods have the same arguments, except a verbosity level is applied to
// UVM_INFO-severity reports.
//
// Arguments:
//
// severity - The report severity: specify either UVM_INFO, UVM_WARNING,
// UVM_ERROR, or UVM_FATAL. Required argument.
//
// id - The report id string, used for identification and targeted
// filtering. See context description for details on how the
// report's id affects filtering. Required argument.
//
// message - The message body, pre-formatted if necessary to a single string.
// Required.
//
// verbosity - The verbosity level indicating an INFO report's relative detail.
// Ignored for warning, error, and fatal reports. Specify UVM_NONE,
// UVM_LOW, UVM_MEDIUM, UVM_HIGH, or UVM_FULL. Default: UVM_MEDIUM.
//
// context - The hierarchical path of the SC-side component issuing the
// report. The context string appears as the hierarchical name in
// the report on the SV side, but it does not play a role in report
// filtering in all cases. All SC-side reports are issued from the
// global context in UVM, i.e. uvm_top. To apply filter settings,
// make them from that context, e.g. uvm_top.set_report_id_action().
// With the context fixed, only the report's id can be used to
// uniquely identify the SC report to filter. Report catchers,
// however, are passed the report's context and so can filter based
// on both SC context and id. Default: "" (unspecified)
//
// filename - The optional filename from which the report was issued. Use
// __FILE__. If specified, the filename will be displayed as part
// of the report. Default: "" (unspecified)
//
// line - The optional line number within filename from which the report
// was issued. Use __LINE__. If specified, the line number will be
// displayed as part of the report. Default: 0 (unspecified)
//
// Examples:
//
// Send a global (uvm_top-sourced) info report of medium verbosity to UVM:
//
// | uvmc_report(UVM_INFO, "SC_READY", "SystemC side is ready");
//
// Issue the same report, this time with low verbosity a filename and line number.
//
// | uvmc_report(UVM_INFO, "SC_READY", "SystemC side is ready",
// | UVM_LOW, "", __FILE__, __LINE__);
//
// UVM_LOW verbosity does not mean lower output. On the contrary, reports with
// UVM_LOW verbosity are printed if the run-time verbosity setting is anything
// but UVM_NONE. Reports issued with UVM_NONE verbosity cannot be filtered by
// the run-time verbosity setting.
//
// The next example sends a WARNING and INFO report from an SC-side producer
// component. In SV, we disable the warning by setting the action for its
// effective ID to UVM_NO_ACTION. We also set the verbosity threshold for INFO
// messages with the effective ID to UVM_NONE. This causes the INFO report to
// be filtered, as the run-time verbosity for reports of that particular ID are
// now much lower than the reports stated verbosity level (UVM_HIGH).
//
//| class producer : public sc_module {
//| ...
//| void run_thread() {
//| ...
//| uvmc_report(UVM_WARNING, "TransEvent",
//| "Generated error transaction.",, this.name());
//| ...
//| uvmc_report(UVM_INFO, "TransEvent",
//| "Transaction complete.", UVM_HIGH, this.name());
//| ...
//| }
//| };
//
// To filter SC-sourced reports on the SV side:
//
//| uvm_top.set_report_id_action("TransEvent@top/prod",UVM_NO_ACTION);
//| uvm_top.set_report_id_verbosity("TransEvent@top/prod",UVM_NONE);
//| uvm_top.set_report_id_verbosity("TransDump",UVM_NONE);
//
|
// The last statement disables all reports to the global context (uvm_top)
// having the ID "TransDump". Note that it is currently not possible to
// set filters for reports for several contexts at once using wildcards. Also,
// the hierarchical separator for SC may be configurable in your simulator, and
// thus could affect the context provided to these commands.
//------------------------------------------------------------------------------
void uvmc_report (int severity,
const char* id,
const char* message,
int verbosity=UVM_MEDIUM,
const char* context="",
const char* filename="",
int line=0);
// Function: uvmc_report_info
//
// Equivalent to <uvmc_report> (UVM_INFO, ...)
void uvmc_report_info (const char* id,
const char* message,
int verbosity=UVM_MEDIUM,
const char* context="",
const char* filename="",
int line=0);
// Function: uvmc_report_warning
//
// Equivalent to <uvmc_report> (UVM_WARNING, ...)
void uvmc_report_warning (const char* id,
const char* message,
const char* context="",
const char* filename="",
int line=0);
// Function: uvmc_report_error
//
// Equivalent to <uvmc_report> (UVM_ERROR, ...)
void uvmc_report_error (const char* id,
const char* message,
const char* context="",
const char* filename="",
int line=0);
// Function: uvmc_report_fatal
//
// Equivalent to <uvmc_report> (UVM_FATAL, ...)
void uvmc_report_fatal (const char* id,
const char* message,
const char* context="",
const char* filename="",
int line=0);
//------------------------------------------------------------------------------
// Topic: Report Macros
//
// Convenience macros to <uvmc_report>.
// See <uvmc_report> for details on macro arguments.
//
// | UVMC_INFO (ID, message, verbosity, context)
// | UVMC_WARNING (ID, message, context)
// | UVMC_ERROR (ID, message, context)
// | UVMC_FATAL (ID, message, context)
//
//
// Before sending the report, the macros first call <uvmc_report_enabled> to
// avoid sending the report at all if its verbosity or action would prevent
// it from reaching the report server. If the report is enabled, then
// <uvmc_report> is called with the filename and line number arguments
// provided for you.
//
// Invocations of these macros must be terminated with semicolons, which is
// in keeping with the SystemC convention established for the ~SC_REPORT~
// macros. Future releases may provide a UVMC sc_report_handler that you
// can use to redirect all SC_REPORTs to UVM.
//
// Example:
//
//| UVMC_ERROR("SC_TOP/NO_CFG","Missing required config object", name());
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Group: Phasing
//
// An API that provides access UVM's phase state and the objection objects used
// to control phase progression.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Function: uvmc_wait_for_phase
//
// Wait for a UVM phase to reach a certain state.
//
// The call must be made from a SystemC process thread that is either statically
// declared via SC_THREAD or dynamically started via sc_spawn. If the latter,
// you must include the following define on the sccom command
// line: -DSC_INCLUDE_DYNAMIC_PROCESSES.
//
// Arguments:
//
// phase - The name of the phase to wait on. The built-in phase names are, in
// order of execution: build, connect, end_of_elaboration,
// start_of_simulation, run, extract, check, report. The fine-grained
// run-time phases, which run in parallel with the run phase, are, in
// order: pre_reset, reset, post_reset, pre_configure, configure,
// post_configure, pre_main, main, post_main, pre_shutdown, shutdown,
// and post_shutdown.
//
// state - The state to wait on. A phase may transition through
// ~UVM_PHASE_JUMPING~ instead of UVM_PHASE_READY_TO_END if its
// execution had been preempted by a phase jump operation. Phases
// execute in the following state order:
//
// | UVM_PHASE_STARTED
// | UVM_PHASE_EXECUTING
// | UVM_PHASE_READY_TO_END | UVM_PHASE_JUMPING
// | UVM_PHASE_ENDED
// | UVM_PHASE_DONE
//
// condition - The state condition to wait for. When state is
// ~UVM_PHASE_JUMPING~, ~condition~ must be UVM_EQ. Default is
// ~UVM_EQ~. Valid values are:
//
// | UVM_LT - Phase is before the given state.
// | UVM_LTE - Phase is before or at the given state.
// | UVM_EQ - Phase is at the given state.
// | UVM_GTE - Phase is at or after the given state.
// | UVM_GT - Phase is after the given state.
// | UVM_NE - Phase is not at the given state.
//
//
// Examples:
//
// The following example shows how to spawn threads that correspond to UVM's
// phases. Here, the ~run_phase~ method executes during the UVM's run phase.
// As any UVM component executing the run phase would do, the SC component's
// ~run_phase~ process prevents the UVM (SV-side) run phase from ending until
// it is finished by calling <uvmc_drop_objection>.
//
//| SC_MODULE(top)
//| {
//| sc_process_handle run_proc;
//|
//| SC_CTOR(top) {
//| run_proc = sc_spawn(sc_bind(&run_phase,this),"run_phase");
//| };
//|
//| void async_reset() {
//| if (run_proc != null && run_proc.valid())
//| run_proc.reset(SC_INCLUDE_DESCENDANTS);
//| }
//|
//| void run_phase() {
//| uvmc_wait_for_phase("run",UVM_PHASE_STARTED,UVM_EQ);
//| uvmc_raise_objection("run","","SC run_phase executing");
//| ...
//| uvmc_drop_objection("run","","SC run_phase finished");
//| }
//| };
//
// If ~async_reset~ is called, the run_proc process and all descendants are
// killed, then run_proc is restarted. The run_proc calls run_phase again,
// which first waits for the UVM to reach the run_phase before resuming
// its work.
//------------------------------------------------------------------------------
void uvmc_wait_for_phase(const char *phase,
uvmc_phase_state state,
uvmc_wait_op op=UVM_EQ);
//------------------------------------------------------------------------------
// Function: uvmc_raise_objection
void uvmc_raise_objection (const char* name,
const char* context="",
const char* description="",
unsigned int count=1);
// Function: uvmc_drop_objection
//
// Raise or drop an objection to ending the specified phase on behalf of the
// component at a given context. Raises can be made before the actual phase is
// executing. However, drops that move the objection count to zero must be
// avoided until the phase is actually executing, else the all-dropped
// condition will occur prematurely. Typical usage includes calling
// <uvmc_wait_for_phase>.
// Arguments:
//
// name - The verbosity level. Specify UVM_NONE, UVM_LOW, UVM_MEDIUM,
// UVM_HIGH, or UVM_FULL. Required.
//
// context - The hierarchical path of the component on whose behalf the
// specified objection is raised or dropped. Wildcards or regular
// expressions are not allowed. The context must exactly match an
// existing component's hierarchical name. Default: "" (uvm_top)
//
// description - The reason for raising or dropping the objection. This string
// is passed in all callbacks and printed when objection tracing is
// turned on. Default: ""
//
// count - The number of objections to raise or drop. Default: 1
//
// Examples:
//
// The following routine will force the specified UVM task phase to last at
// minimum number of nanoseconds, assuming SystemC and SystemVerilog are
// operating on the same timescale.
//
//| void set_min_phase_duration(const char* ph_name, sc_time min_time) {
//| uvmc_wait_for_phase(ph_name, UVM_PHASE_STARTED);
//| uvmc_raise_objection(ph_name,"","Forcing minimum run time");
//| wait(min_time);
//| uvmc_drop_objection(ph_name,"","Phase met minimum run time");
//| }
//
// Use directly as a blocking call, or use in non-blocking fashion with
// sc_spawn/sc_bind:
//
//| sc_spawn(sc_bind(&top:set_min_phase_duration, // <--func pointer
//| this,"run",sc_time(100,SC_NS)),"min_run_time");
//------------------------------------------------------------------------------
void uvmc_drop_objection (const char* name,
const char* context="",
const char* description="",
unsigned int count=1);
//------------------------------------------------------------------------------
// Group: Factory
//
// This API provides access to UVM's object and component factory.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Function: uvmc_print_factory
//
// Prints the state of the UVM factory, including registered types, instance
// overrides, and type overrides.
//
// Arguments:
//
// all_types - When all_types is 0, only type and instance overrides are
// displayed. When all_types is 1 (default), all registered
// user-defined types are printed as well, provided they have type
// names associated with them. (Parameterized types usually do not.)
// When all_types is 2, all UVM types (prefixed with uvm_) are
// included in the list of registered types.
//
// Examples:
//
// Print all type and instance overrides in the factory.
//
//| uvmc_print_factory(0);
//
// Print all type and instance overrides, plus all registered user-defined
// types.
//
//| uvmc_print_factory(1);
//
// Print all type and instance overrides, plus all registered types, including
// UVM types.
//
//| uvmc_print_factory(2);
//------------------------------------------------------------------------------
void uvmc_print_factory (int all_types=1);
//------------------------------------------------------------------------------
// Function: uvmc_set_factory_type_override
void uvmc_set_factory_type_override (const char* original_type,
const char* override_type,
bool replace=1);
// Function: uvmc_set_factory_inst_override
//
// Set a type or instance override. Instance overrides take precedence over
// type overrides. All specified types must have been registered with the
// factory.
//
// Arguments:
//
// requested_type - The name of the requested type.
//
// override_type - The name of the override type. Must be an extension of the
// requested_type.
//
// context - The hierarchical path of the component. Multiple components
// can be specified by using glob wildcards (* and ?), e.g.
// "top.env.*.driver". You can also specify a POSIX extended
// regular expression by enclosing the context string in
// forward slashes, e.g. "/a[hp]b/".
//
// replace - If true, replace any existing type override. Default: true
//
// Examples:
//
// The following sets an instance override in the UVM factory. Any component
// whose inst path matches the glob expression "e.*" that requests an object
// of type scoreboard_base (i.e. scoreboard_base:type_id::create) will instead
// get an object of type scoreboard.
//
//| uvmc_set_factory_inst_override("scoreboard_base","scoreboard","e.*");
//
// The following sets a type override in the UVM factory. Any component whose
// hierarchical path matches the glob expression "e.*" that requests an
// object of type producer_base (i.e. producer_base:type_id::create) will
// instead get an object of type producer.
//
//| uvmc_set_factory_type_override("producer_base","producer");
//
// The following sets an override chain. Given any request for an atype, a
// ctype object is returned, except for the component with hierarchical name
// "e.prod", which will get a dtype.
//
//| uvmc_set_factory_type_override("atype","btype");
//| uvmc_set_factory_type_override("btype","ctype");
//| uvmc_set_factory_inst_override("ctype","dtype","e.prod");
//------------------------------------------------------------------------------
void uvmc_set_factory_inst_override (const char* original_type,
const char* override_type,
const char* context);
//------------------------------------------------------------------------------
// Function: uvmc_debug_factory_create
//
// Display detailed information about the object type the UVM factory would
// create given a requested type and context, listing each override that was
// applied to arrive at the result.
//
// Arguments:
//
// requested - The requested type name for a hypothetical call to create.
//
// context - The hierarchical path of the object to be created, which is a
// concatenation of the parent's hierarchical name with the
// name of the object being created. Wildcards or regular
// expressions are not allowed. The context must exactly match
// an existing component's hierarchical name, or can be the
// empty string to specify global context.
//
// Example:
//
// The following example answers the question: If the component at
// hierarchical path ~env.agent1.scoreboard~ requested an object of type
// scoreboard_base, what are all the applicable overrides, and which of
// those were applied to arrive at the result?
//
//| uvmc_debug_factory_create("scoreboard_base","env.agent1.scoreboard");
//------------------------------------------------------------------------------
void uvmc_debug_factory_create (const char* requested_type,
const char* context="");
//------------------------------------------------------------------------------
// Function: uvmc_find_factory_override
//
// Returns the type name of the type that would be created by the factory given
// the requested type and context.
//
// Arguments:
//
// requested - The requested type name for a hypothetical call to create.
//
// context - The hierarchical path of the component that would make the
// request. Wildcards or regular expressions are not allowed.
// The context must exactly match an existing component's
// hierarchical name, or can be the empty string to specify
// global context.
//
// Examples:
//
// The following examples assume all types, A through D, have been registered
// with the UVM factory. Given the following overrides:
//
//| uvmc_set_type_override("B","C");
//| uvmc_set_type_override("A","B");
//| uvmc_set_inst_override("D", "C", "top.env.agent1.*");
//
// The following will display "C":
//
//| $display(uvmc_find_factory_override("A"));
//
// The following will display "D":
//
//| $display(uvmc_find_factory_override("A", "top.env.agent1.driver"));
//
// The returned string can be used in subsequent calls to
// <uvmc_set_factory_type_override> and <uvmc_set_factory_inst_override>.
//------------------------------------------------------------------------------
string uvmc_find_factory_override (const char* requested_type,
const char* context="");
//------------------------------------------------------------------------------
// Group: set_config
//------------------------------------------------------------------------------
//
// Creates or updates a configuration setting for a field at a specified
// hierarchical context.
//
// These functions establish configuration settings, storing them as resource
// entries in the resource database for later lookup by get_config calls. They
// do not directly affect the field values being targeted. As the component
// hierarchy is being constructed during UVM's build phase, components
// spring into existence and establish their context. Once its context is
// known, each component can call get_config to retrieve any configuration
// settings that apply to it.
//
// The context is specified as the concatenation of two arguments, context and
// inst_name, which are separated by a "." if both context and inst_name are
// not empty. Both context and inst_name may be glob style or regular
// expression style expressions.
//
// The name of the configuration parameter is specified by the ~field_name~
// argument.
//
// The semantic of the set methods is different when UVM is in the build phase
// versus any other phase. If a set call is made during the build phase, the
// context determines precedence in the database. A set call from a higher
// level in the hierarchy (e.g. mytop.test1) has precedence over a set call to
// the same field from a lower level (e.g. mytop.test1.env.agent). Set calls
// made at the same level of hierarchy have equal precedence, so each set call
// overwrites the field value from a previous set call.
//
// After the build phase, all set calls have the same precedence regardless of
// their hierarchical context. Each set call overwrites the value of the
// previous call.
//
// Arguments:
//
// type_name - For uvmc_set_config_object only. Specifies the type name of the
// equivalent object to set in SV. UVM Connect will utilize the
// factory to allocate an object of this type and unpack the
// serialized value into it. Parameterized classes are not
// supported.
//
// context - The hierarchical path of the component, or the empty string,
// which specifies uvm_top. Multiple components can be specified
// by using glob wildcards (* and ?), e.g. "top.env.*.driver".
// You can also specify a POSIX extended regular expression by
// enclosing the contxt in forward slashes, e.g. "/a[hp]b/".
// Default: "" (uvm_top)
//
// inst_name - The instance path of the object being configured, relative to
// the specified context(s). Can contain wildcards or be a
// regular expression.
//
// field_name - The name of the configuration parameter. Typically this name
// is the same as or similar to the variable used to hold the
// configured value in the target context(s).
//
// value - The value of the configuration parameter. Integral values
// currently cannot exceed 64 bits. Object values must have a
// uvmc_convert<object_type> specialization defined for it.
// Use of the converter convenience macros is acceptable for
// meeting this requirement.
//
// Examples:
//
// The following example sets the configuration object field at path
// "e.prod.trans" to the tr instance, which is type uvm_tlm_generic_payload.
//
//| uvmc_set_config_object("uvm_tlm_generic_payload","e.prod","","trans", tr);
//
// The next example sets the string property at hierarchical path
// "e.prod.message" to "Hello from SystemC!".
//
//| uvmc_set_config_string ("e.prod", "", "message", "Hello from SystemC!");
//
// The next example sets the integral property at hierarchical path
// "e.prod.start_addr" to hex 0x1234.
//
//| uvmc_set_config_int ("e.prod", "", "start_addr", 0x1234);
//--------------------------
|
----------------------------------------------------
// Function: uvmc_set_config_int
//
// Set an integral configuration value
//
void uvmc_set_config_int (const char* context, const char* inst_name,
const char* field_name, uint64 value);
// Function: uvmc_set_config_string
//
// Set a string configuration value
//
void uvmc_set_config_string (const char* context, const char* inst_name,
const char* field_name, const string& value);
} // extern "C"
namespace uvmc {
// Function: uvmc_set_config_object
//
// Set an object configuration value using a custom converter
//
template <class T, class CVRT>
void uvmc_set_config_object (const char* type_name,
const char* context,
const char* inst_name,
const char* field_name,
T &value,
uvmc_packer *packer=NULL) {
static bits_t bits;
static uvmc_packer def_packer;
if (packer == NULL) {
packer = &def_packer;
//packer->big_endian = 0;
}
wait_sv_ready();
packer->init_pack(bits);
CVRT::do_pack(value,packer);
svSetScope(uvmc_pkg_scope);
UVMC_set_config_object(type_name,context,inst_name,field_name,bits);
}
// Function: uvmc_set_config_object
//
// Set an object configuration value using the default converter
//
template <class T>
void uvmc_set_config_object (const char* type_name,
const char* context,
const char* inst_name,
const char* field_name,
T &value,
uvmc_packer *packer=NULL) {
static bits_t bits[UVMC_MAX_WORDS];
static uvmc_packer def_packer;
if (packer == NULL) {
packer = &def_packer;
//packer->big_endian = 0;
}
wait_sv_ready();
packer->init_pack(bits);
uvmc_converter<T>::do_pack(value,*packer);
svSetScope(uvmc_pkg_scope);
UVMC_set_config_object(type_name,context,inst_name,field_name,bits);
}
} // namespace uvmc
extern "C" {
//------------------------------------------------------------------------------
// Group: get_config
//------------------------------------------------------------------------------
//
// Gets a configuration field ~value~ at a specified hierarchical ~context~.
// Returns true if successful, false if a configuration setting could not be
// found at the given ~context~. If false, the ~value~ reference is unmodified.
//
// The ~context~ specifies the starting point for a search for a configuration
// setting for the field made at that level of hierarchy or higher. The
// ~inst_name~ is an explicit instance name relative to context and may be an
// empty string if ~context~ is the full context that the configuration
// setting applies to.
//
// The ~context~ and ~inst_name~ strings must be simple strings--no wildcards
// or regular expressions.
//
// See the section on <set_config> for the semantics
// that apply when setting configuration.
//
// Arguments:
//
// type_name - For <uvmc_get_config_object> only. Specifies the type name
// of the equivalent object to retrieve in SV. UVM Connect
// will check that the object retrieved from the configuration
// database matches this type name. If a match, the object is
// serialized (packed) and returned across the language
// boundary. Once on this side, the object data is unpacked
// into the object passed by reference via the value argument.
// Parameterized classes are not supported.
//
// context - The hierarchical path of the component on whose behalf the
// specified configuration is being retrieved. Wildcards or
// regular expressions are not allowed. The context must
// exactly match an existing component's hierarchical name,
// or be the empty string, which specifies uvm_top.
//
// inst_name - The instance path of the object being configured, relative
// to the specified context(s).
//
// field_name - The name of the configuration parameter. Typically this name
// is the same as or similar to the variable used to hold the
// configured value in the target context(s).
//
// value - The value of the configuration parameter. Integral values
// currently cannot exceed 64 bits. Object values must have a
// uvmc_convert<object_type> specialization defined for it. Use
// of the converter convenience macros is acceptable for meeting
// this requirement. The equivalent class in SV must be based
// on uvm_object and registered with the UVM factory, i.e.
// contain a `uvm_object_utils macro invocation.
//
// Examples:
//
// The following example retrieves the uvm_tlm_generic_payload configuration
// property at hierarchical path "e.prod.trans" into tr2.
//
//| uvmc_get_config_object("uvm_tlm_generic_payload","e","prod","trans", tr2);
//
// The context specification is split between the context and inst_name
// arguments. Unlike setting configuration, there is no semantic difference
// between the context and inst_name properties. When getting configuration,
// the full context is always the concatenation of the context, ".", and
// inst_name. The transaction tr2 will effectively become a copy of the
// object used to set the configuration property.
//
// The next example retrieves the string property at hierarchical path
// "e.prod.message" into local variable str.
//
//| uvmc_get_config_string ("e", "prod", "message", str);
//
// The following example retrieves the integral property at hierarchical path
// "e.prod.start_addr" into the local variable, saddr.
//
//| uvmc_get_config_int ("e.prod", "", "start_addr", saddr);
//------------------------------------------------------------------------------
// Function: uvmc_get_config_int
//
// Set an integral configuration value.
//
bool uvmc_get_config_int (const char* context, const char* inst_name,
const char* field_name, uint64 &value);
// Function: uvmc_get_config_string
//
// Set a string configuration value.
//
bool uvmc_get_config_string (const char* context, const char* inst_name,
const char* field_name, string &value);
} // extern "C"
namespace uvmc {
// Function: uvmc_get_config_object
//
// Set an object configuration value using a custom converter
//
template <class T, class CVRT>
bool uvmc_get_config_object (const char* type_name,
const char* context,
const char* inst_name,
const char* field_name,
T &value,
uvmc_packer *packer=NULL) {
static bits_t bits;
static uvmc_packer def_packer;
if (packer == NULL) {
packer = &def_packer;
//packer->big_endian = 0;
}
wait_sv_ready();
svSetScope(uvmc_pkg_scope);
if (UVMC_get_config_object(type_name,context,inst_name,field_name,bits)) {
packer->init_unpack(bits);
CVRT::do_unpack(value,packer);
return 1;
}
return 0;
}
// Function: uvmc_get_config_object
//
// Set an object configuration value using the default converter
//
template <class T>
bool uvmc_get_config_object (const char* type_name,
const char* context,
const char* inst_name,
const char* field_name,
T &value,
uvmc_packer *packer=NULL) {
static bits_t bits[UVMC_MAX_WORDS];
static uvmc_packer def_packer;
if (packer == NULL) {
packer = &def_packer;
//packer->big_endian = 0;
}
wait_sv_ready();
svSetScope(uvmc_pkg_scope);
if (UVMC_get_config_object(type_name,context,inst_name,field_name,bits)) {
packer->init_unpack(bits);
uvmc_converter<T>::do_unpack(value,*packer);
return 1;
}
return 0;
}
} // namespace uvmc
#endif // UVMC_COMMANDS_H
|
//****************************************************************************************
// MIT License
//****************************************************************************************
// Copyright (c) 2012-2020 University of Bremen, Germany.
// Copyright (c) 2015-2020 DFKI GmbH Bremen, Germany.
// Copyright (c) 2020 Johannes Kepler University Linz, Austria.
// Copyright (c) 2022 - 2023 Coseda Technologies GmbH.
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all
// copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
//****************************************************************************************
#pragma once
#include "VariableBase.hpp"
#include "../frontend/Operators.hpp"
#include "../frontend/WeightedRange.hpp"
#include "../frontend/Distribution.hpp"
#include "../ir/UserExpression.hpp"
#include "Constraint.hpp"
namespace crave {
/**
* \ingroup newAPI
* \brief Creates a distribution_tag to be used directly in constraints from a single weighted range.
* Convenient function, which calls distribution::create.
*
* \param range a weighted range.
* \return A distribution_tag of a distribution to be used in constraints.
*/
template <typename T>
distribution_tag<T> make_distribution(weighted_range<T> const& range) {
return distribution<T>::create(range);
}
/**
* \ingroup newAPI
* \brief Creates a distribution_tag to be used directly in constraints from the given ranges.
*
* Convenient function, which should be preferred to chaining calls of distribution::create and distribution::operator().
*
* \param range the first range.
* \param args the following ranges.
* \return A distribution_tag of a distribution to be used in constraints.
*/
template <typename T, typename... Args>
distribution_tag<T> make_distribution(weighted_range<T> const& range, Args... args) {
return make_distribution(args...)(range);
}
/**
* constructor
* @param name name of the variable
*/
#define CRV_VARIABLE_COMMON_CONSTRUCTORS(Typename) \
public: \
crv_variable(crv_object_name name = "var") {create_default_cstr ();} \
crv_variable(const crv_variable& other) : crv_variable_base<Typename>(other) {}
/**
* assignment operator
* @param i value for the assignment
*/
#define CRV_VARIABLE_ASSIGNMENT_INTERFACE(Typename) \
public: \
crv_variable<Typename>& operator=(const crv_variable<Typename>& i) { \
this->value = i.value; \
return *this; \
} \
crv_variable<Typename>& operator=(Typename i) { \
this->value = i; \
return *this; \
}
/**
* arithmetic operations
* @param i value for arithmetic operation
*/
#define CRV_VARIABLE_ARITHMETIC_INTERFACE(Typename) \
public: \
crv_variable<Typename>& operator++() { \
++(this->value); \
return *this; \
} \
Typename operator++(int) { \
Typename tmp = this->value; \
++(this->value); \
return tmp; \
} \
crv_variable<Typename>& operator--() { \
--(this->value); \
return *this; \
} \
Typename operator--(int) { \
Typename tmp = this->value; \
--(this->value); \
return tmp; \
} \
crv_variable<Typename>& operator+=(Typename i) { \
this->value += i; \
return *this; \
} \
crv_variable<Typename>& operator-=(Typename i) { \
this->value -= i; \
return *this; \
} \
crv_variable<Typename>& operator*=(Typename i) { \
this->value *= i; \
return *this; \
} \
crv_variable<Typename>& operator/=(Typename i) { \
this->value /= i; \
return *this; \
} \
crv_variable<Typename>& operator%=(Typename i) { \
this->value %= i; \
return *this; \
}
/**
* bitwise operators
* @param i value for bitwise operation
*/
#define CRV_VARIABLE_BITWISE_INTERFACE(Typename) \
public: \
crv_variable<Typename>& operator&=(Typename i) { \
this->value &= i; \
return *this; \
} \
crv_variable<Typename>& operator|=(Typename i) { \
this->value |= i; \
return *this; \
} \
crv_variable<Typename>& operator^=(Typename i) { \
this->value ^= i; \
return *this; \
} \
crv_variable<Typename>& operator<<=(Typename i) { \
this->value <<= i; \
return *this; \
} \
crv_variable<Typename>& operator>>=(Typename i) { \
this->value >>= i; \
return *this; \
}
/**
* boolean operators
* @param i value for bitwise operation
*/
#define CRV_VARIABLE_BOOLEAN_INTERFACE(Typename) \
public: \
crv_variable<Typename>& operator&=(Typename i) { \
this->value &= i; \
return *this; \
} \
crv_variable<Typename>& operator|=(Typename i) { \
this->value |= i; \
return *this; \
} \
crv_variable<Typename>& operator^=(Typename i) { \
this->value ^= i; \
return *this; \
} \
/*!
*\ingroup newAPI
*\brief A randomizable variable of type T in new API.
*
* <p>This class is the type for all randomizable variables of type T.
* Default the following types of C++ are supported:
* <ul>
* <li>bool</li>
* <li>(unsigned) int</li>
* <li>(signed|unsigned) char</li>
* <li>(unsigned) short</li>
* <li>(unsigned) long</li>
* <li>(unsigned) long long</li>
* </ul>
* You can add support for SystemC Datatypes by including experimental/SystemC.hpp.
* This adds support for
* <ul>
* <li>sc_bv<n></li>
* <li>sc_(u)int<n></li>
* </ul>
* It is also possible to randomize enumerations.
* To randomize an enumeration, you must previously declare it with the macro \ref CRAVE_BETTER_ENUM </p><p>
* A crv_variable<T> also supports basic binary and arithmetic operations +=,-=,*=,/=,=,|=,&=,%=,<<=,>>=,^=.
* A very important operator is the operator ().
* This operator can be used to get a WriteReference which is to be used in the definition of constraints.
* For details see crave::crv_constraint</p><p>
* For coverage aspects there is a method named bind() for a crv_variable.
* Bind takes another crv_variable as a parameter.
* If two variables are bound together, they share the same value.
* </p>
*/
class crv_var {
public:
virtual ~crv_var() {}
virtual unsigned getVarID() = 0;
};
template <typename T, typename Enable = void>
class crv_variable {};
/**
* class for randomisation of a variable
*/
template <typename T >
class crv_variable<T, typename std::enable_if<std::is_integral<T>::value>::type> : public crv_var, public crv_variable_base<T> {
CRV_VARIABLE_COMMON_CONSTRUCTORS(T);
CRV_VARIABLE_ASSIGNMENT_INTERFACE(T);
CRV_VARIABLE_ARITHMETIC_INTERFACE(T);
CRV_VARIABLE_BITWISE_INTERFACE(T);
crv_constraint c_var_uniform;
public:
/**
* generate random value
*/
bool randomize() override {
static distribution<T> dist;
this->value = dist.nextValue();
return true;
}
void create_default_cstr () {
c_var_uniform = { dist(this->var, make_distribution(range<T>(std::numeric_limits<T>::min(), std::numeric_limits<T>::max())))};
}
unsigned getVarID() override {
return crv_variable_base<T>::id();
}
};
/**
* class for randomisation of a variable
*/
template <>
class crv_variable<bool> : public crv_var, public crv_variable_base<bool> {
CRV_VARIABLE_COMMON_CONSTRUCTORS(bool);
CRV_VARIABLE_ASSIGNMENT_INTERFACE(bool);
//CRV_VARIABLE_ARITHMETIC_INTERFACE(bool);
CRV_VARIABLE_BOOLEAN_INTERFACE(bool);
crv_constraint c_var_uniform;
public:
/**
* generate random value
*/
bool randomize() override {
static distribution<bool> dist;
this->value = dist.nextValue();
return true;
}
void create_default_cstr () {
c_var_uniform = { dist(this->var, distribution<bool>::create(0.5))};
}
unsigned getVarID() override {
return crv_variable_base<bool>::id();
}
};
template <typename T>
struct bitsize_traits<crv_variable<T>> : public bitsize_traits<T> {};
} // namespace crave
|
#include <systemc.h>
SC_MODULE( or_gate )
{
sc_inout<bool> a;
sc_inout<bool> b;
sc_out<bool> c;
void or_process( void )
{
c = a.read() || b.read();
}
void test_process( void )
{
assert( (a.read() || b.read() ) == c.read() );
}
SC_CTOR( or_gate )
{
}
};
int sc_main( int argc, char * argv[] )
{
sc_signal<bool> s1;
sc_signal<bool> s2;
sc_signal<bool> s3;
s1.write(true);
s2.write(false);
s3.write(true);
or_gate gate("or_gate");
gate.a(s1);
gate.b(s2);
gate.c(s3);
// gate.or_process();
gate.test_process();
return 0;
}
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
#ifndef _bd_9cfa_one_0_H_
#define _bd_9cfa_one_0_H_
#include "xlconstant_v1_1_7.h"
#include "systemc.h"
class bd_9cfa_one_0 : public sc_module {
public:
xlconstant_v1_1_7<1,1> mod;
sc_out< sc_bv<1> > dout;
bd_9cfa_one_0 (sc_core::sc_module_name name);
};
#endif
|
/*
* Copyright (c) 2010 TIMA Laboratory
*
* This file is part of Rabbits.
*
* Rabbits is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* Rabbits is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Rabbits. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef _QEMU_WRAPPER_ACCESS_INTERFACE_
#define _QEMU_WRAPPER_ACCESS_INTERFACE_
#include <systemc.h>
class qemu_wrapper_access_interface : public sc_interface
{
public:
virtual unsigned long get_no_cpus () = 0;
virtual unsigned long get_cpu_fv_level (unsigned long cpu) = 0;
virtual void set_cpu_fv_level (unsigned long cpu, unsigned long val) = 0;
virtual void generate_swi (unsigned long cpu_mask, unsigned long swi) = 0;
virtual void swi_ack (int cpu, unsigned long swi_mask) = 0;
virtual unsigned long get_cpu_ncycles (unsigned long cpu) = 0;
virtual uint64 get_no_cycles_cpu (int cpu) = 0;
virtual unsigned long get_int_status () = 0;
virtual unsigned long get_int_enable () = 0;
virtual void set_int_enable (unsigned long val) = 0;
};
#endif
/*
* Vim standard variables
* vim:set ts=4 expandtab tw=80 cindent syntax=c:
*
* Emacs standard variables
* Local Variables:
* mode: c
* tab-width: 4
* c-basic-offset: 4
* indent-tabs-mode: nil
* End:
*/
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.2
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _FBTA64_theta_HH_
#define _FBTA64_theta_HH_
#include "systemc.h"
#include "AESL_pkg.h"
#include "log_2_64bit.h"
#include "FBTA64_theta_mux_eOg.h"
#include "FBTA64_theta_buddbkb.h"
#include "FBTA64_theta_buddcud.h"
#include "FBTA64_theta_addrdEe.h"
namespace ap_rtl {
struct FBTA64_theta : public sc_module {
// Port declarations 18
sc_in_clk ap_clk;
sc_in< sc_logic > ap_rst;
sc_in< sc_logic > ap_start;
sc_out< sc_logic > ap_done;
sc_out< sc_logic > ap_idle;
sc_out< sc_logic > ap_ready;
sc_in< sc_lv<32> > alloc_size;
sc_in< sc_logic > alloc_size_ap_vld;
sc_out< sc_logic > alloc_size_ap_ack;
sc_in< sc_lv<32> > alloc_free_target;
sc_in< sc_logic > alloc_free_target_ap_vld;
sc_out< sc_logic > alloc_free_target_ap_ack;
sc_out< sc_lv<32> > alloc_addr;
sc_out< sc_logic > alloc_addr_ap_vld;
sc_in< sc_logic > alloc_addr_ap_ack;
sc_in< sc_lv<8> > alloc_cmd;
sc_in< sc_logic > alloc_cmd_ap_vld;
sc_out< sc_logic > alloc_cmd_ap_ack;
sc_signal< sc_lv<64> > ap_var_for_const0;
sc_signal< sc_lv<64> > ap_var_for_const1;
sc_signal< sc_lv<64> > ap_var_for_const2;
sc_signal< sc_lv<64> > ap_var_for_const3;
sc_signal< sc_lv<64> > ap_var_for_const4;
sc_signal< sc_lv<64> > ap_var_for_const5;
sc_signal< sc_lv<64> > ap_var_for_const6;
// Module declarations
FBTA64_theta(sc_module_name name);
SC_HAS_PROCESS(FBTA64_theta);
~FBTA64_theta();
sc_trace_file* mVcdFile;
ofstream mHdltvinHandle;
ofstream mHdltvoutHandle;
FBTA64_theta_buddbkb* buddy_tree_V_1_U;
FBTA64_theta_buddcud* buddy_tree_V_0_U;
FBTA64_theta_addrdEe* addr_layer_map_V_U;
log_2_64bit* loc1_V_11_log_2_64bit_fu_522;
FBTA64_theta_mux_eOg<1,1,64,64,64,64,2,64>* FBTA64_theta_mux_eOg_U2;
FBTA64_theta_mux_eOg<1,1,64,64,64,64,2,64>* FBTA64_theta_mux_eOg_U3;
FBTA64_theta_mux_eOg<1,1,64,64,64,64,2,64>* FBTA64_theta_mux_eOg_U4;
FBTA64_theta_mux_eOg<1,1,64,64,64,64,2,64>* FBTA64_theta_mux_eOg_U5;
sc_signal< sc_lv<19> > ap_CS_fsm;
sc_signal< sc_logic > ap_CS_fsm_state1;
sc_signal< sc_lv<2> > buddy_tree_V_1_address0;
sc_signal< sc_logic > buddy_tree_V_1_ce0;
sc_signal< sc_logic > buddy_tree_V_1_we0;
sc_signal< sc_lv<64> > buddy_tree_V_1_d0;
sc_signal< sc_lv<64> > buddy_tree_V_1_q0;
sc_signal< sc_lv<2> > buddy_tree_V_1_address1;
sc_signal< sc_logic > buddy_tree_V_1_ce1;
sc_signal< sc_logic > buddy_tree_V_1_we1;
sc_signal< sc_lv<64> > buddy_tree_V_1_d1;
sc_signal< sc_lv<64> > buddy_tree_V_1_q1;
sc_signal< sc_lv<2> > buddy_tree_V_0_address0;
sc_signal< sc_logic > buddy_tree_V_0_ce0;
sc_signal< sc_logic > buddy_tree_V_0_we0;
sc_signal< sc_lv<64> > buddy_tree_V_0_d0;
sc_signal< sc_lv<64> > buddy_tree_V_0_q0;
sc_signal< sc_lv<2> > buddy_tree_V_0_address1;
sc_signal< sc_logic > buddy_tree_V_0_ce1;
sc_signal< sc_logic > buddy_tree_V_0_we1;
sc_signal< sc_lv<64> > buddy_tree_V_0_d1;
sc_signal< sc_lv<64> > buddy_tree_V_0_q1;
sc_signal< sc_lv<7> > addr_layer_map_V_address0;
sc_signal< sc_logic > addr_layer_map_V_ce0;
sc_signal< sc_logic > addr_layer_map_V_we0;
sc_signal< sc_lv<4> > addr_layer_map_V_q0;
sc_signal< sc_logic > alloc_size_blk_n;
sc_signal< sc_logic > ap_CS_fsm_state2;
sc_signal< sc_logic > alloc_free_target_blk_n;
sc_signal< sc_logic > alloc_addr_blk_n;
sc_signal< sc_logic > ap_CS_fsm_state19;
sc_signal< sc_logic > alloc_cmd_blk_n;
sc_signal< sc_lv<64> > p_01606_0_in_reg_444;
sc_signal< sc_lv<8> > p_01598_1_in_reg_454;
sc_signal< sc_lv<8> > p_01590_5_in_reg_463;
sc_signal< sc_lv<8> > p_01594_1_in_reg_473;
sc_signal< sc_lv<8> > p_01586_3_in_reg_482;
sc_signal< sc_lv<9> > op2_assign_5_reg_491;
sc_signal< sc_lv<8> > size_V_fu_546_p1;
sc_signal< sc_lv<8> > size_V_reg_1531;
sc_signal< bool > ap_block_state2;
sc_signal< sc_lv<8> > free_target_V_fu_550_p1;
sc_signal< sc_lv<8> > free_target_V_reg_1536;
sc_signal< sc_lv<8> > p_Result_1_fu_560_p4;
sc_signal< sc_lv<8> > p_Result_1_reg_1543;
sc_signal< sc_lv<1> > tmp_fu_570_p2;
sc_signal< sc_logic > ap_CS_fsm_state3;
sc_signal< sc_lv<1> > tmp_s_fu_576_p2;
sc_signal< sc_lv<1> > tmp_s_reg_1553;
sc_signal< sc_lv<4> > ans_V_fu_717_p2;
sc_signal< sc_lv<4> > ans_V_reg_1558;
sc_signal< sc_lv<1> > tmp_6_fu_723_p2;
sc_signal< sc_logic > ap_CS_fsm_state4;
sc_signal< sc_lv<4> > addr_layer_map_V_loa_reg_1572;
sc_signal< sc_logic > ap_CS_fsm_state5;
sc_signal< sc_lv<1> > tmp_27_fu_733_p1;
sc_signal< sc_lv<1> > tmp_27_reg_1578;
sc_signal< sc_lv<64> > newIndex2_fu_747_p1;
sc_signal< sc_lv<64> > newIndex2_reg_1583;
sc_signal< sc_lv<8> > ans_V_2_fu_753_p1;
sc_signal< sc_lv<8> > ans_V_2_reg_1599;
sc_signal< sc_logic > ap_CS_fsm_state6;
sc_signal< sc_lv<8> > r_V_12_fu_805_p3;
sc_signal< sc_lv<8> > r_V_12_reg_1605;
sc_signal< sc_lv<64> > tmp_17_fu_834_p2;
sc_signal< sc_lv<64> > tmp_17_reg_1611;
sc_signal< sc_lv<8> > p_Result_2_fu_840_p4;
sc_signal< sc_logic > ap_CS_fsm_state7;
sc_signal< sc_lv<64> > r_V_fu_853_p2;
sc_signal< sc_lv<8> > now1_V_4_fu_858_p2;
sc_signal< sc_lv<8> > now1_V_4_reg_1628;
sc_signal< sc_logic > ap_CS_fsm_pp0_stage0;
sc_signal< sc_logic > ap_enable_reg_pp0_iter0;
sc_signal< bool > ap_block_state8_pp0_stage0_iter0;
sc_signal< bool > ap_block_state9_pp0_stage0_iter1;
sc_signal< bool > ap_block_state10_pp0_stage0_iter2;
sc_signal< bool > ap_block_pp0_stage0_11001;
sc_signal< sc_lv<1> > icmp1_fu_874_p2;
sc_signal< sc_lv<1> > icmp1_reg_1633;
sc_signal< sc_lv<1> > icmp1_reg_1633_pp0_iter1_reg;
sc_signal< sc_lv<1> > tmp_58_fu_880_p1;
sc_signal< sc_lv<1> > tmp_58_reg_1637;
sc_signal< sc_lv<1> > tmp_58_reg_1637_pp0_iter1_reg;
sc_signal< sc_lv<64> > newIndex6_fu_894_p1;
sc_signal< sc_lv<64> > newIndex6_reg_1642;
sc_signal< sc_lv<64> > newIndex6_reg_1642_pp0_iter1_reg;
sc_signal< sc_lv<7> > loc1_V_fu_900_p4;
sc_signal< sc_lv<7> > loc1_V_reg_1658;
sc_signal< sc_lv<64> > buddy_tree_V_0_load_2_reg_1663;
sc_signal< sc_logic > ap_enable_reg_pp0_iter1;
sc_signal< sc_lv<64> > buddy_tree_V_1_load_2_reg_1668;
sc_signal< sc_lv<8> > p_Result_3_fu_914_p4;
sc_signal< sc_lv<8> > p_Result_3_reg_1673;
sc_signal< sc_lv<64> > r_V_3_fu_975_p2;
sc_signal< sc_logic > ap_enable_reg_pp0_iter2;
sc_signal< sc_lv<8> > p_Repl2_2_fu_981_p2;
sc_signal< sc_lv<8> > p_Repl2_2_reg_1684;
sc_signal< sc_logic > ap_CS_fsm_pp1_stage0;
sc_signal< sc_logic > ap_enable_reg_pp1_iter0;
sc_signal< bool > ap_block_state12_pp1_stage0_iter0;
sc_signal< bool > ap_block_state13_pp1_stage0_iter1;
sc_signal< bool > ap_block_pp1_stage0_11001;
sc_signal< sc_lv<1> > tmp_29_fu_987_p2;
sc_signal< sc_lv<1> > tmp_29_reg_1689;
sc_signal< sc_lv<8> > p_Repl2_s_fu_993_p2;
sc_signal< sc_lv<8> > p_Repl2_s_reg_1693;
sc_signal< sc_lv<1> > tmp_63_fu_999_p1;
sc_signal< sc_lv<1> > tmp_63_reg_1698;
sc_signal< sc_lv<64> > r_V_13_fu_1057_p2;
sc_signal< sc_lv<64> > r_V_13_reg_1703;
sc_signal< sc_lv<64> > newIndex9_fu_1073_p1;
sc_signal< sc_lv<64> > newIndex9_reg_1708;
sc_signal< sc_lv<9> > cnt_fu_1079_p2;
sc_signal< sc_lv<4> > p_s_fu_1099_p3;
sc_signal< sc_lv<4> > p_s_reg_1729;
sc_signal< sc_logic > ap_CS_fsm_state15;
sc_signal< sc_lv<1> > tmp_20_fu_1105_p1;
sc_signal< sc_lv<1> > tmp_20_reg_1736;
sc_signal< sc_lv<64> > newIndex4_fu_1119_p1;
sc_signal< sc_lv<64> > newIndex4_reg_1741;
sc_signal< sc_lv<64> > buddy_tree_V_load_1_s_fu_1125_p3;
sc_signal< sc_lv<64> > buddy_tree_V_load_1_s_reg_1757;
sc_signal< sc_logic > ap_CS_fsm_state16;
sc_signal< sc_lv<64> > tmp_5_fu_1132_p2;
sc_signal< sc_lv<64> > tmp_5_reg_1765;
sc_signal< sc_lv<64> > tmp_12_fu_1138_p2;
sc_signal< sc_lv<64> > tmp_12_reg_1770;
sc_signal< sc_logic > ap_CS_fsm_state17;
sc_signal< sc_lv<64> > tmp_V_fu_1142_p2;
sc_signal< sc_lv<64> > tmp_V_reg_1775;
sc_signal< sc_lv<8> > now1_V_cast_fu_1152_p1;
sc_signal< sc_lv<8> > now1_V_cast_reg_1780;
sc_signal< sc_lv<4> > now2_V_fu_1156_p2;
sc_signal< sc_lv<4> > now2_V_reg_1785;
sc_signal< sc_lv<8> > now2_V_1_cast_fu_1161_p1;
sc_signal< sc_lv<8> > now2_V_1_cast_reg_1790;
sc_signal< sc_lv<64> > tmp_13_fu_1171_p2;
sc_signal< sc_lv<64> > tmp_13_reg_1795;
sc_signal< sc_lv<8> > loc1_V_11_log_2_64bit_fu_522_ap_return;
sc_signal< sc_lv<8> > loc1_V_11_reg_1801;
sc_signal< sc_logic > ap_CS_fsm_state18;
sc_signal< sc_lv<1> > tmp_18_fu_1176_p2;
sc_signal< sc_lv<1> > tmp_18_reg_1807;
sc_signal< sc_lv<7> > loc1_V_2_reg_1812;
sc_signal< sc_lv<1> > tmp_46_fu_1235_p3;
sc_signal< sc_logic > ap_sig_ioackin_alloc_addr_ap_ack;
sc_signal< sc_lv<1> > op2_assign_2_fu_1274_p2;
sc_signal< sc_lv<1> > op2_assign_2_reg_1843;
sc_signal< sc_logic > ap_CS_fsm_state20;
sc_signal< sc_lv<1> > tmp_25_fu_1280_p2;
sc_signal< sc_lv<1> > tmp_25_reg_1848;
sc_signal< sc_lv<1> > icmp2_fu_1296_p2;
sc_signal< sc_lv<1> > icmp2_reg_1852;
sc_signal< sc_lv<64> > rhs_V_fu_1362_p2;
sc_signal< sc_lv<64> > rhs_V_reg_1856;
sc_signal< sc_lv<1> > tmp_60_fu_1368_p1;
sc_signal< sc_lv<1> > tmp_60_reg_1861;
sc_signal< sc_lv<64> > newIndex_fu_1382_p1;
sc_signal< sc_lv<64> > newIndex_reg_1866;
sc_signal< sc_lv<1> > tmp_44_fu_1388_p2;
sc_signal< sc_lv<1> > tmp_44_reg_1882;
sc_signal< sc_lv<64> > newIndex10_fu_1404_p1;
sc_signal< sc_lv<64> > newIndex10_reg_1886;
sc_signal< sc_lv<8> > now1_V_2_fu_1509_p2;
sc_signal< sc_logic > ap_CS_fsm_state21;
sc_signal< sc_lv<8> > now2_V_2_fu_1518_p2;
sc_signal< bool > ap_block_pp0_stage0_subdone;
sc_signal< sc_logic > ap_condition_pp0_exit_iter0_state8;
sc_signal< sc_logic > ap_CS_fsm_state11;
sc_signal< bool > ap_block_pp1_stage0_subdone;
sc_signal< sc_logic > ap_condition_pp1_exit_iter0_state12;
sc_signal< sc_logic > ap_enable_reg_pp1_iter1;
sc_signal< sc_logic > loc1_V_11_log_2_64bit_fu_522_ap_ready;
sc_signal< sc_lv<8> > ap_phi_mux_p_01598_1_in_phi_fu_457_p4;
sc_signal< bool > ap_block_pp0_stage0;
sc_signal< sc_lv<8> > ap_phi_mux_p_01590_5_in_phi_fu_466_p4;
sc_signal< sc_lv<8> > ap_phi_mux_p_01594_1_in_phi_fu_476_p4;
sc_signal< bool > ap_block_pp1_stage0;
sc_signal< sc_lv<8> > ap_phi_mux_p_01586_3_in_phi_fu_485_p4;
sc_signal< sc_lv<8> > p_4_reg_502;
sc_signal< sc_lv<8> > p_5_reg_512;
sc_signal< sc_lv<64> > tmp_8_fu_729_p1;
sc_signal< sc_lv<64> > tmp_21_fu_1222_p1;
sc_signal< sc_lv<1> > tmp_66_fu_1453_p1;
sc_signal< sc_lv<8> > cmd_fu_172;
sc_signal< sc_lv<32> > cnt_1_fu_176;
sc_signal< sc_lv<32> > cnt_2_fu_1430_p2;
sc_signal< sc_lv<8> > loc2_V_2_fu_180;
sc_signal< sc_lv<8> > r_V_10_fu_1230_p2;
sc_signal< sc_lv<8> > loc2_V_3_fu_1424_p2;
sc_signal< sc_lv<8> > loc1_V_6_fu_184;
sc_signal< sc_lv<8> > loc1_V_4_fu_1227_p1;
sc_signal< sc_lv<8> > loc1_V_9_fu_1490_p1;
sc_signal< sc_lv<32> > p_Val2_4_cast_fu_1217_p1;
sc_signal< sc_logic > ap_reg_ioackin_alloc_addr_ap_ack;
sc_signal< sc_lv<64> > tmp_35_fu_964_p2;
sc_signal< sc_lv<64> > r_V_5_fu_1092_p2;
sc_signal< sc_lv<64> > r_V_8_fu_1417_p2;
sc_signal< sc_lv<64> > p_Result_s_fu_1465_p4;
sc_signal< sc_lv<8> > tmp_size_V_fu_554_p2;
sc_signal< sc_lv<8> > p_not_fu_581_p2;
sc_signal< sc_lv<8> > tmp_7_fu_586_p2;
sc_signal< sc_lv<1> > sel_tmp_fu_591_p2;
sc_signal< sc_lv<1> > sel_tmp4_fu_635_p2;
sc_signal< sc_lv<1> > sel_tmp1_fu_629_p2;
sc_signal< sc_lv<1> > sel_tmp9_fu_623_p2;
sc_signal< sc_lv<1> > sel_tmp7_fu_617_p2;
sc_signal< sc_lv<1> > sel_tmp5_fu_611_p2;
sc_signal< sc_lv<1> > sel_tmp3_fu_605_p2;
sc_signal< sc_lv<1> > or_cond_fu_649_p2;
sc_signal< sc_lv<3> > newSel_cast_cast_fu_641_p3;
sc_signal< sc_lv<3> > newSel_fu_655_p3;
sc_signal< sc_lv<1> > or_cond1_fu_663_p2;
sc_signal< sc_lv<1> > or_cond2_fu_677_p2;
sc_signal< sc_lv<3> > newSel1_fu_669_p3;
sc_signal< sc_lv<3> > sel_tmp2_fu_597_p3;
sc_signal< sc_lv<1> > or_cond3_fu_691_p2;
sc_signal< sc_lv<3> > newSel2_fu_683_p3;
sc_signal< sc_lv<3> > newSel3_fu_697_p3;
sc_signal< sc_lv<3> > newSel4_fu_705_p3;
sc_signal< sc_lv<4> > tmp_15_cast_fu_713_p1;
sc_signal< sc_lv<3> > tmp_30_fu_737_p4;
sc_signal< sc_lv<5> > lhs_V_cast_cast_fu_756_p1;
sc_signal< sc_lv<5> > r_V_11_fu_759_p2;
sc_signal< sc_lv<5> > tmp_10_fu_780_p2;
sc_signal< sc_lv<32> > tmp_9_fu_777_p1;
sc_signal< sc_lv<32> > tmp_10_cast_fu_786_p1;
sc_signal< sc_lv<8> > r_V_11_cast5_fu_765_p1;
sc_signal< sc_lv<32> > tmp_11_fu_790_p2;
sc_signal< sc_lv<1> > tmp_23_fu_769_p3;
sc_signal< sc_lv<8> > tmp_24_fu_801_p1;
sc_signal< sc_lv<8> > tmp_14_fu_796_p2;
sc_signal< sc_lv<32> > tmp_15_fu_813_p1;
sc_signal< sc_lv<32> > op2_assign_3_fu_817_p2;
sc_signal< sc_lv<64> > buddy_tree_V_load_ph_fu_827_p3;
sc_signal< sc_lv<64> > tmp_16_fu_823_p1;
sc_signal< sc_lv<64> > tmp_22_fu_849_p1;
sc_signal< sc_lv<5> > tmp_54_fu_864_p4;
sc_signal< sc_lv<7> > newIndex5_fu_884_p4;
sc_signal< sc_lv<8> > loc1_V_12_fu_910_p1;
sc_signal< sc_lv<1> > tmp_56_fu_924_p3;
sc_signal< sc_lv<1> > tmp_57_fu_932_p1;
sc_signal< sc_lv<1> > tmp_31_fu_936_p2;
sc_signal< sc_lv<32> > tmp_32_fu_942_p1;
sc_signal< sc_lv<32> > tmp_33_fu_946_p1;
sc_signal< sc_lv<32> > op2_assign_4_fu_949_p2;
sc_signal< sc_lv<64> > buddy_tree_V_load_2_s_fu_959_p3;
sc_signal< sc_lv<64> > tmp_34_fu_955_p1;
sc_signal< sc_lv<64> > tmp_40_fu_972_p1;
sc_signal< sc_lv<2> > tmp_41_fu_1017_p5;
sc_signal< sc_lv<2> > tmp_42_fu_1031_p5;
sc_signal< sc_lv<1> > tmp_64_fu_1003_p1;
sc_signal< sc_lv<64> > tmp_41_fu_1017_p6;
sc_signal< sc_lv<64> > tmp_42_fu_1031_p6;
sc_signal< sc_lv<64> > mask_V_load_phi_fu_1045_p3;
sc_signal< sc_lv<64> > tmp_43_fu_1053_p1;
sc_signal< sc_lv<7> > newIndex8_fu_1063_p4;
sc_signal< sc_lv<64> > lhs_V_1_fu_1085_p3;
sc_signal< sc_lv<3> > newIndex3_fu_1109_p4;
sc_signal< sc_lv<4> > now1_V_fu_1147_p2;
sc_signal< sc_lv<64> > op2_assign_fu_1165_p2;
sc_signal< sc_lv<16> > tmp_28_cast_fu_1190_p1;
sc_signal< sc_lv<16> > tmp_33_cast_fu_1193_p1;
sc_signal< sc_lv<16> > tmp_19_fu_1196_p2;
sc_signal< sc_lv<8> > r_V_4_fu_1202_p1;
sc_signal< sc_lv<9> > output_addr_V_cast_fu_1206_p1;
sc_signal< sc_lv<9> > p_Val2_2_fu_1210_p3;
sc_signal< sc_lv<5> > tmp_53_fu_1258_p4;
sc_signal< sc_lv<1> > icmp_fu_1268_p2;
sc_signal< sc_lv<5> > tmp_55_fu_1286_p4;
sc_signal< sc_lv<2> > tmp_36_fu_1316_p5;
sc_signal< sc_lv<2> > tmp_37_fu_1330_p5;
sc_signal< sc_lv<1> > tmp_59_fu_1302_p1;
sc_signal< sc_lv<64> > tmp_36_fu_1316_p6;
sc_signal< sc_lv<64> > tmp_37_fu_1330_p6;
sc_signal< sc_lv<64> > mask_V_load_1_phi_fu_1344_p3;
sc_signal< sc_lv<64> > tmp_38_fu_1352_p1;
sc_signal< sc_lv<64> > r_V_7_fu_1356_p2;
sc_signal< sc_lv<7> > newIndex1_fu_1372_p4;
sc_signal< sc_lv<7> > newIndex7_fu_1394_p4;
sc_signal< sc_lv<64> > lhs_V_fu_1410_p3;
sc_signal< sc_lv<64> > p_Val2_5_fu_1457_p3;
sc_signal< sc_lv<32> > i_assign_fu_1449_p1;
sc_signal< sc_lv<7> > loc1_V_5_fu_1480_p4;
sc_signal< sc_lv<1> > op2_assign_1_fu_1499_p2;
sc_signal< sc_lv<8> > tmp_45_fu_1505_p1;
sc_signal< sc_lv<8> > tmp_47_fu_1515_p1;
sc_signal< sc_logic > ap_CS_fsm_state14;
sc_signal< sc_lv<19> > ap_NS_fsm;
sc_signal< sc_logic > ap_idle_pp0;
sc_signal< sc_logic > ap_enable_pp0;
sc_signal< sc_logic > ap_idle_pp1;
sc_signal< sc_logic > ap_enable_pp1;
static const sc_logic ap_const_logic_1;
static const sc_logic ap_const_logic_0;
static const sc_lv<19> ap_ST_fsm_state1;
static const sc_lv<19> ap_ST_fsm_state2;
static const sc_lv<19> ap_ST_fsm_state3;
static const sc_lv<19> ap_ST_fsm_state4;
static const sc_lv<19> ap_ST_fsm_state5;
static const sc_lv<19> ap_ST_fsm_state6;
static const sc_lv<19> ap_ST_fsm_state7;
static const sc_lv<19> ap_ST_fsm_pp0_stage0;
static const sc_lv<19> ap_ST_fsm_state11;
static const sc_lv<19> ap_ST_fsm_pp1_stage0;
static const sc_lv<19> ap_ST_fsm_state14;
static const sc_lv<19> ap_ST_fsm_state15;
static const sc_lv<19> ap_ST_fsm_state16;
static const sc_lv<19> ap_ST_fsm_state17;
static const sc_lv<19> ap_ST_fsm_state18;
static const sc_lv<19> ap_ST_fsm_state19;
static const sc_lv<19> ap_ST_fsm_state20;
static const sc_lv<19> ap_ST_fsm_state21;
static const sc_lv<19> ap_ST_fsm_state22;
static const sc_lv<32> ap_const_lv32_0;
static const bool ap_const_boolean_1;
static const sc_lv<32> ap_const_lv32_1;
static const sc_lv<32> ap_const_lv32_F;
static const sc_lv<32> ap_const_lv32_2;
static const sc_lv<1> ap_const_lv1_1;
static const sc_lv<32> ap_const_lv32_3;
static const sc_lv<32> ap_const_lv32_4;
static const sc_lv<32> ap_const_lv32_5;
static const sc_lv<32> ap_const_lv32_6;
static const sc_lv<32> ap_const_lv32_7;
static const bool ap_const_boolean_0;
static const sc_lv<32> ap_const_lv32_9;
static const sc_lv<1> ap_const_lv1_0;
static const sc_lv<32> ap_const_lv32_B;
static const sc_lv<32> ap_const_lv32_C;
static const sc_lv<32> ap_const_lv32_D;
static const sc_lv<32> ap_const_lv32_E;
static const sc_lv<32> ap_const_lv32_10;
static const sc_lv<32> ap_const_lv32_11;
static const sc_lv<32> ap_const_lv32_8;
static const sc_lv<9> ap_const_lv9_1;
static const sc_lv<8> ap_const_lv8_0;
static const sc_lv<8> ap_const_lv8_FF;
static const sc_lv<8> ap_const_lv8_2;
static const sc_lv<8> ap_const_lv8_1;
static const sc_lv<8> ap_const_lv8_80;
static const sc_lv<3> ap_const_lv3_7;
static const sc_lv<3> ap_const_lv3_0;
static const sc_lv<8> ap_const_lv8_40;
static const sc_lv<8> ap_const_lv8_20;
static const sc_lv<8> ap_const_lv8_10;
static const sc_lv<8> ap_const_lv8_8;
static const sc_lv<8> ap_const_lv8_4;
static const sc_lv<3> ap_const_lv3_1;
static const sc_lv<3> ap_const_lv3_2;
static const sc_lv<3> ap_const_lv3_3;
static const sc_lv<3> ap_const_lv3_4;
static const sc_lv<3> ap_const_lv3_5;
static const sc_lv<3> ap_const_lv3_6;
static const sc_lv<4> ap_const_lv4_9;
static const sc_lv<8> ap_const_lv8_3;
static const sc_lv<5> ap_const_lv5_1F;
static const sc_lv<5> ap_const_lv5_1;
static const sc_lv<5> ap_const_lv5_0;
static const sc_lv<64> ap_const_lv64_3;
static const sc_lv<64> ap_const_lv64_FF;
static const sc_lv<64> ap_const_lv64_FFFFFFFF;
static const sc_lv<64> ap_const_lv64_FFFFFFFFFFFFFFFF;
static const sc_lv<64> ap_const_lv64_0;
static const sc_lv<64> ap_const_lv64_F;
static const sc_lv<64> ap_const_lv64_FFFF;
static const sc_lv<4> ap_const_lv4_1;
static const sc_lv<4> ap_const_lv4_F;
static const sc_lv<9> ap_const_lv9_1FF;
static const sc_lv<32> ap_const_lv32_A;
// Thread declarations
void thread_ap_var_for_const0();
void thread_ap_var_for_const1();
void thread_ap_var_for_const2();
void thread_ap_var_for_const3();
void thread_ap_var_for_const4();
void thread_ap_var_for_const5();
void thread_ap_var_for_const6();
void thread_ap_clk_no_reset_();
void thread_addr_layer_map_V_address0();
void thread_addr_layer_map_V_ce0();
void thread_addr_layer_map_V_we0();
void thread_alloc_addr();
void th
|
read_alloc_addr_ap_vld();
void thread_alloc_addr_blk_n();
void thread_alloc_cmd_ap_ack();
void thread_alloc_cmd_blk_n();
void thread_alloc_free_target_ap_ack();
void thread_alloc_free_target_blk_n();
void thread_alloc_size_ap_ack();
void thread_alloc_size_blk_n();
void thread_ans_V_2_fu_753_p1();
void thread_ans_V_fu_717_p2();
void thread_ap_CS_fsm_pp0_stage0();
void thread_ap_CS_fsm_pp1_stage0();
void thread_ap_CS_fsm_state1();
void thread_ap_CS_fsm_state11();
void thread_ap_CS_fsm_state14();
void thread_ap_CS_fsm_state15();
void thread_ap_CS_fsm_state16();
void thread_ap_CS_fsm_state17();
void thread_ap_CS_fsm_state18();
void thread_ap_CS_fsm_state19();
void thread_ap_CS_fsm_state2();
void thread_ap_CS_fsm_state20();
void thread_ap_CS_fsm_state21();
void thread_ap_CS_fsm_state3();
void thread_ap_CS_fsm_state4();
void thread_ap_CS_fsm_state5();
void thread_ap_CS_fsm_state6();
void thread_ap_CS_fsm_state7();
void thread_ap_block_pp0_stage0();
void thread_ap_block_pp0_stage0_11001();
void thread_ap_block_pp0_stage0_subdone();
void thread_ap_block_pp1_stage0();
void thread_ap_block_pp1_stage0_11001();
void thread_ap_block_pp1_stage0_subdone();
void thread_ap_block_state10_pp0_stage0_iter2();
void thread_ap_block_state12_pp1_stage0_iter0();
void thread_ap_block_state13_pp1_stage0_iter1();
void thread_ap_block_state2();
void thread_ap_block_state8_pp0_stage0_iter0();
void thread_ap_block_state9_pp0_stage0_iter1();
void thread_ap_condition_pp0_exit_iter0_state8();
void thread_ap_condition_pp1_exit_iter0_state12();
void thread_ap_done();
void thread_ap_enable_pp0();
void thread_ap_enable_pp1();
void thread_ap_idle();
void thread_ap_idle_pp0();
void thread_ap_idle_pp1();
void thread_ap_phi_mux_p_01586_3_in_phi_fu_485_p4();
void thread_ap_phi_mux_p_01590_5_in_phi_fu_466_p4();
void thread_ap_phi_mux_p_01594_1_in_phi_fu_476_p4();
void thread_ap_phi_mux_p_01598_1_in_phi_fu_457_p4();
void thread_ap_ready();
void thread_ap_sig_ioackin_alloc_addr_ap_ack();
void thread_buddy_tree_V_0_address0();
void thread_buddy_tree_V_0_address1();
void thread_buddy_tree_V_0_ce0();
void thread_buddy_tree_V_0_ce1();
void thread_buddy_tree_V_0_d0();
void thread_buddy_tree_V_0_d1();
void thread_buddy_tree_V_0_we0();
void thread_buddy_tree_V_0_we1();
void thread_buddy_tree_V_1_address0();
void thread_buddy_tree_V_1_address1();
void thread_buddy_tree_V_1_ce0();
void thread_buddy_tree_V_1_ce1();
void thread_buddy_tree_V_1_d0();
void thread_buddy_tree_V_1_d1();
void thread_buddy_tree_V_1_we0();
void thread_buddy_tree_V_1_we1();
void thread_buddy_tree_V_load_1_s_fu_1125_p3();
void thread_buddy_tree_V_load_2_s_fu_959_p3();
void thread_buddy_tree_V_load_ph_fu_827_p3();
void thread_cnt_2_fu_1430_p2();
void thread_cnt_fu_1079_p2();
void thread_free_target_V_fu_550_p1();
void thread_i_assign_fu_1449_p1();
void thread_icmp1_fu_874_p2();
void thread_icmp2_fu_1296_p2();
void thread_icmp_fu_1268_p2();
void thread_lhs_V_1_fu_1085_p3();
void thread_lhs_V_cast_cast_fu_756_p1();
void thread_lhs_V_fu_1410_p3();
void thread_loc1_V_12_fu_910_p1();
void thread_loc1_V_4_fu_1227_p1();
void thread_loc1_V_5_fu_1480_p4();
void thread_loc1_V_9_fu_1490_p1();
void thread_loc1_V_fu_900_p4();
void thread_loc2_V_3_fu_1424_p2();
void thread_mask_V_load_1_phi_fu_1344_p3();
void thread_mask_V_load_phi_fu_1045_p3();
void thread_newIndex10_fu_1404_p1();
void thread_newIndex1_fu_1372_p4();
void thread_newIndex2_fu_747_p1();
void thread_newIndex3_fu_1109_p4();
void thread_newIndex4_fu_1119_p1();
void thread_newIndex5_fu_884_p4();
void thread_newIndex6_fu_894_p1();
void thread_newIndex7_fu_1394_p4();
void thread_newIndex8_fu_1063_p4();
void thread_newIndex9_fu_1073_p1();
void thread_newIndex_fu_1382_p1();
void thread_newSel1_fu_669_p3();
void thread_newSel2_fu_683_p3();
void thread_newSel3_fu_697_p3();
void thread_newSel4_fu_705_p3();
void thread_newSel_cast_cast_fu_641_p3();
void thread_newSel_fu_655_p3();
void thread_now1_V_2_fu_1509_p2();
void thread_now1_V_4_fu_858_p2();
void thread_now1_V_cast_fu_1152_p1();
void thread_now1_V_fu_1147_p2();
void thread_now2_V_1_cast_fu_1161_p1();
void thread_now2_V_2_fu_1518_p2();
void thread_now2_V_fu_1156_p2();
void thread_op2_assign_1_fu_1499_p2();
void thread_op2_assign_2_fu_1274_p2();
void thread_op2_assign_3_fu_817_p2();
void thread_op2_assign_4_fu_949_p2();
void thread_op2_assign_fu_1165_p2();
void thread_or_cond1_fu_663_p2();
void thread_or_cond2_fu_677_p2();
void thread_or_cond3_fu_691_p2();
void thread_or_cond_fu_649_p2();
void thread_output_addr_V_cast_fu_1206_p1();
void thread_p_Repl2_2_fu_981_p2();
void thread_p_Repl2_s_fu_993_p2();
void thread_p_Result_1_fu_560_p4();
void thread_p_Result_2_fu_840_p4();
void thread_p_Result_3_fu_914_p4();
void thread_p_Result_s_fu_1465_p4();
void thread_p_Val2_2_fu_1210_p3();
void thread_p_Val2_4_cast_fu_1217_p1();
void thread_p_Val2_5_fu_1457_p3();
void thread_p_not_fu_581_p2();
void thread_p_s_fu_1099_p3();
void thread_r_V_10_fu_1230_p2();
void thread_r_V_11_cast5_fu_765_p1();
void thread_r_V_11_fu_759_p2();
void thread_r_V_12_fu_805_p3();
void thread_r_V_13_fu_1057_p2();
void thread_r_V_3_fu_975_p2();
void thread_r_V_4_fu_1202_p1();
void thread_r_V_5_fu_1092_p2();
void thread_r_V_7_fu_1356_p2();
void thread_r_V_8_fu_1417_p2();
void thread_r_V_fu_853_p2();
void thread_rhs_V_fu_1362_p2();
void thread_sel_tmp1_fu_629_p2();
void thread_sel_tmp2_fu_597_p3();
void thread_sel_tmp3_fu_605_p2();
void thread_sel_tmp4_fu_635_p2();
void thread_sel_tmp5_fu_611_p2();
void thread_sel_tmp7_fu_617_p2();
void thread_sel_tmp9_fu_623_p2();
void thread_sel_tmp_fu_591_p2();
void thread_size_V_fu_546_p1();
void thread_tmp_10_cast_fu_786_p1();
void thread_tmp_10_fu_780_p2();
void thread_tmp_11_fu_790_p2();
void thread_tmp_12_fu_1138_p2();
void thread_tmp_13_fu_1171_p2();
void thread_tmp_14_fu_796_p2();
void thread_tmp_15_cast_fu_713_p1();
void thread_tmp_15_fu_813_p1();
void thread_tmp_16_fu_823_p1();
void thread_tmp_17_fu_834_p2();
void thread_tmp_18_fu_1176_p2();
void thread_tmp_19_fu_1196_p2();
void thread_tmp_20_fu_1105_p1();
void thread_tmp_21_fu_1222_p1();
void thread_tmp_22_fu_849_p1();
void thread_tmp_23_fu_769_p3();
void thread_tmp_24_fu_801_p1();
void thread_tmp_25_fu_1280_p2();
void thread_tmp_27_fu_733_p1();
void thread_tmp_28_cast_fu_1190_p1();
void thread_tmp_29_fu_987_p2();
void thread_tmp_30_fu_737_p4();
void thread_tmp_31_fu_936_p2();
void thread_tmp_32_fu_942_p1();
void thread_tmp_33_cast_fu_1193_p1();
void thread_tmp_33_fu_946_p1();
void thread_tmp_34_fu_955_p1();
void thread_tmp_35_fu_964_p2();
void thread_tmp_36_fu_1316_p5();
void thread_tmp_37_fu_1330_p5();
void thread_tmp_38_fu_1352_p1();
void thread_tmp_40_fu_972_p1();
void thread_tmp_41_fu_1017_p5();
void thread_tmp_42_fu_1031_p5();
void thread_tmp_43_fu_1053_p1();
void thread_tmp_44_fu_1388_p2();
void thread_tmp_45_fu_1505_p1();
void thread_tmp_46_fu_1235_p3();
void thread_tmp_47_fu_1515_p1();
void thread_tmp_53_fu_1258_p4();
void thread_tmp_54_fu_864_p4();
void thread_tmp_55_fu_1286_p4();
void thread_tmp_56_fu_924_p3();
void thread_tmp_57_fu_932_p1();
void thread_tmp_58_fu_880_p1();
void thread_tmp_59_fu_1302_p1();
void thread_tmp_5_fu_1132_p2();
void thread_tmp_60_fu_1368_p1();
void thread_tmp_63_fu_999_p1();
void thread_tmp_64_fu_1003_p1();
void thread_tmp_66_fu_1453_p1();
void thread_tmp_6_fu_723_p2();
void thread_tmp_7_fu_586_p2();
void thread_tmp_8_fu_729_p1();
void thread_tmp_9_fu_777_p1();
void thread_tmp_V_fu_1142_p2();
void thread_tmp_fu_570_p2();
void thread_tmp_s_fu_576_p2();
void thread_tmp_size_V_fu_554_p2();
void thread_ap_NS_fsm();
void thread_hdltv_gen();
};
}
using namespace ap_rtl;
#endif
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
// Version: 2020.1
// Copyright (C) 1986-2020 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _Detecteur_HH_
#define _Detecteur_HH_
#include "systemc.h"
#include "AESL_pkg.h"
#include "Seuil_calc.h"
#include "trames_separ.h"
#include "DOUBLEUR_U.h"
#include "fifo_w8_d1024_A.h"
#include "fifo_w1_d1024_A.h"
namespace ap_rtl {
struct Detecteur : public sc_module {
// Port declarations 8
sc_in_clk clock;
sc_in< sc_logic > reset;
sc_in< sc_lv<8> > e_dout;
sc_in< sc_logic > e_empty_n;
sc_out< sc_logic > e_read;
sc_out< sc_lv<8> > s_din;
sc_in< sc_logic > s_full_n;
sc_out< sc_logic > s_write;
sc_signal< sc_logic > ap_var_for_const0;
// Module declarations
Detecteur(sc_module_name name);
SC_HAS_PROCESS(Detecteur);
~Detecteur();
sc_trace_file* mVcdFile;
Seuil_calc* grp_Seuil_calc_fu_100;
trames_separ* grp_trames_separ_fu_114;
DOUBLEUR_U* grp_DOUBLEUR_U_fu_130;
fifo_w8_d1024_A* dbl2scalc_1_fifo_U;
fifo_w8_d1024_A* dbl2tsep_1_fifo_U;
fifo_w1_d1024_A* detect_1_fifo_U;
sc_signal< sc_logic > grp_Seuil_calc_fu_100_e_read;
sc_signal< sc_logic > grp_Seuil_calc_fu_100_detect_din;
sc_signal< sc_logic > grp_Seuil_calc_fu_100_detect_write;
sc_signal< sc_logic > grp_trames_separ_fu_114_e_read;
sc_signal< sc_logic > grp_trames_separ_fu_114_detect_dout;
sc_signal< sc_logic > grp_trames_separ_fu_114_detect_read;
sc_signal< sc_lv<8> > grp_trames_separ_fu_114_s_din;
sc_signal< sc_logic > grp_trames_separ_fu_114_s_write;
sc_signal< sc_logic > grp_DOUBLEUR_U_fu_130_e_read;
sc_signal< sc_lv<8> > grp_DOUBLEUR_U_fu_130_s1_din;
sc_signal< sc_logic > grp_DOUBLEUR_U_fu_130_s1_write;
sc_signal< sc_lv<8> > grp_DOUBLEUR_U_fu_130_s2_din;
sc_signal< sc_logic > grp_DOUBLEUR_U_fu_130_s2_write;
sc_signal< sc_logic > dbl2scalc_1_full_n;
sc_signal< sc_logic > dbl2tsep_1_full_n;
sc_signal< sc_lv<8> > dbl2scalc_1_dout;
sc_signal< sc_logic > dbl2scalc_1_empty_n;
sc_signal< sc_lv<1> > detect_1_din;
sc_signal< sc_logic > detect_1_full_n;
sc_signal< sc_lv<8> > dbl2tsep_1_dout;
sc_signal< sc_logic > dbl2tsep_1_empty_n;
sc_signal< sc_lv<1> > detect_1_dout;
sc_signal< sc_logic > detect_1_empty_n;
static const sc_logic ap_const_logic_1;
static const sc_logic ap_const_logic_0;
// Thread declarations
void thread_ap_var_for_const0();
void thread_detect_1_din();
void thread_e_read();
void thread_grp_trames_separ_fu_114_detect_dout();
void thread_s_din();
void thread_s_write();
};
}
using namespace ap_rtl;
#endif
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2019.1
// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _foo_HH_
#define _foo_HH_
#include "systemc.h"
#include "AESL_pkg.h"
namespace ap_rtl {
struct foo : public sc_module {
// Port declarations 10
sc_in_clk ap_clk;
sc_in< sc_logic > ap_rst;
sc_in< sc_logic > ap_start;
sc_out< sc_logic > ap_done;
sc_out< sc_logic > ap_idle;
sc_out< sc_logic > ap_ready;
sc_in< sc_lv<32> > in1;
sc_in< sc_lv<32> > in2;
sc_out< sc_lv<32> > out_data;
sc_out< sc_logic > out_data_ap_vld;
// Module declarations
foo(sc_module_name name);
SC_HAS_PROCESS(foo);
~foo();
sc_trace_file* mVcdFile;
ofstream mHdltvinHandle;
ofstream mHdltvoutHandle;
sc_signal< sc_lv<2> > ap_CS_fsm;
sc_signal< sc_logic > ap_CS_fsm_state1;
sc_signal< sc_lv<32> > accum;
sc_signal< sc_lv<4> > i_fu_177_p2;
sc_signal< sc_logic > ap_CS_fsm_state2;
sc_signal< sc_lv<1> > ap_phi_mux_do_init_phi_fu_75_p6;
sc_signal< sc_lv<1> > do_init_reg_71;
sc_signal< sc_lv<1> > icmp_ln4_fu_183_p2;
sc_signal< sc_lv<32> > ap_phi_mux_in12_phi_phi_fu_132_p4;
sc_signal< sc_lv<32> > in12_rewind_reg_86;
sc_signal< sc_lv<32> > ap_phi_mux_in23_phi_phi_fu_145_p4;
sc_signal< sc_lv<32> > in23_rewind_reg_100;
sc_signal< sc_lv<4> > i_01_reg_114;
sc_signal< sc_lv<32> > add_ln5_1_fu_164_p2;
sc_signal< sc_lv<32> > add_ln5_fu_158_p2;
sc_signal< sc_lv<2> > ap_NS_fsm;
static const sc_logic ap_const_logic_1;
static const sc_logic ap_const_logic_0;
static const sc_lv<2> ap_ST_fsm_state1;
static const sc_lv<2> ap_ST_fsm_state2;
static const sc_lv<32> ap_const_lv32_0;
static const sc_lv<32> ap_const_lv32_1;
static const sc_lv<1> ap_const_lv1_1;
static const sc_lv<1> ap_const_lv1_0;
static const sc_lv<4> ap_const_lv4_0;
static const sc_lv<4> ap_const_lv4_1;
static const sc_lv<4> ap_const_lv4_9;
static const bool ap_const_boolean_1;
// Thread declarations
void thread_ap_clk_no_reset_();
void thread_add_ln5_1_fu_164_p2();
void thread_add_ln5_fu_158_p2();
void thread_ap_CS_fsm_state1();
void thread_ap_CS_fsm_state2();
void thread_ap_done();
void thread_ap_idle();
void thread_ap_phi_mux_do_init_phi_fu_75_p6();
void thread_ap_phi_mux_in12_phi_phi_fu_132_p4();
void thread_ap_phi_mux_in23_phi_phi_fu_145_p4();
void thread_ap_ready();
void thread_i_fu_177_p2();
void thread_icmp_ln4_fu_183_p2();
void thread_out_data();
void thread_out_data_ap_vld();
void thread_ap_NS_fsm();
void thread_hdltv_gen();
};
}
using namespace ap_rtl;
#endif
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
// Version: 2019.2
// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _pqcrystals_dilithium2_ref_HH_
#define _pqcrystals_dilithium2_ref_HH_
#include "systemc.h"
#include "AESL_pkg.h"
#include "pqcrystals_dilithium_1_1.h"
namespace ap_rtl {
struct pqcrystals_dilithium2_ref : public sc_module {
// Port declarations 29
sc_in_clk ap_clk;
sc_in< sc_logic > ap_rst;
sc_in< sc_logic > ap_start;
sc_out< sc_logic > ap_done;
sc_out< sc_logic > ap_idle;
sc_out< sc_logic > ap_ready;
sc_out< sc_lv<13> > sm_address0;
sc_out< sc_logic > sm_ce0;
sc_out< sc_logic > sm_we0;
sc_out< sc_lv<8> > sm_d0;
sc_in< sc_lv<8> > sm_q0;
sc_out< sc_lv<13> > sm_address1;
sc_out< sc_logic > sm_ce1;
sc_out< sc_logic > sm_we1;
sc_out< sc_lv<8> > sm_d1;
sc_in< sc_lv<8> > sm_q1;
sc_out< sc_lv<64> > smlen;
sc_out< sc_logic > smlen_ap_vld;
sc_out< sc_lv<12> > m_address0;
sc_out< sc_logic > m_ce0;
sc_in< sc_lv<8> > m_q0;
sc_in< sc_lv<64> > mlen;
sc_out< sc_lv<12> > sk_address0;
sc_out< sc_logic > sk_ce0;
sc_in< sc_lv<8> > sk_q0;
sc_out< sc_lv<12> > sk_address1;
sc_out< sc_logic > sk_ce1;
sc_in< sc_lv<8> > sk_q1;
sc_out< sc_lv<32> > ap_return;
// Module declarations
pqcrystals_dilithium2_ref(sc_module_name name);
SC_HAS_PROCESS(pqcrystals_dilithium2_ref);
~pqcrystals_dilithium2_ref();
sc_trace_file* mVcdFile;
ofstream mHdltvinHandle;
ofstream mHdltvoutHandle;
pqcrystals_dilithium_1_1* grp_pqcrystals_dilithium_1_1_fu_107;
sc_signal< sc_lv<4> > ap_CS_fsm;
sc_signal< sc_logic > ap_CS_fsm_state1;
sc_signal< sc_lv<13> > add_ln213_fu_124_p2;
sc_signal< sc_lv<13> > add_ln213_reg_191;
sc_signal< sc_lv<14> > add_ln213_1_fu_134_p2;
sc_signal< sc_lv<14> > add_ln213_1_reg_196;
sc_signal< sc_lv<64> > i_fu_153_p2;
sc_signal< sc_lv<64> > i_reg_204;
sc_signal< sc_logic > ap_CS_fsm_state2;
sc_signal< sc_lv<1> > icmp_ln212_fu_148_p2;
sc_signal< sc_lv<14> > sub_ln213_1_fu_169_p2;
sc_signal< sc_lv<14> > sub_ln213_1_reg_214;
sc_signal< sc_logic > grp_pqcrystals_dilithium_1_1_fu_107_ap_start;
sc_signal< sc_logic > grp_pqcrystals_dilithium_1_1_fu_107_ap_done;
sc_signal< sc_logic > grp_pqcrystals_dilithium_1_1_fu_107_ap_idle;
sc_signal< sc_logic > grp_pqcrystals_dilithium_1_1_fu_107_ap_ready;
sc_signal< sc_lv<13> > grp_pqcrystals_dilithium_1_1_fu_107_sig_address0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_1_1_fu_107_sig_ce0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_1_1_fu_107_sig_we0;
sc_signal< sc_lv<8> > grp_pqcrystals_dilithium_1_1_fu_107_sig_d0;
sc_signal< sc_lv<13> > grp_pqcrystals_dilithium_1_1_fu_107_sig_address1;
sc_signal< sc_logic > grp_pqcrystals_dilithium_1_1_fu_107_sig_ce1;
sc_signal< sc_logic > grp_pqcrystals_dilithium_1_1_fu_107_sig_we1;
sc_signal< sc_lv<8> > grp_pqcrystals_dilithium_1_1_fu_107_sig_d1;
sc_signal< sc_lv<12> > grp_pqcrystals_dilithium_1_1_fu_107_sk_address0;
sc_signal< sc_logic > grp_pqcrystals_dilithium_1_1_fu_107_sk_ce0;
sc_signal< sc_lv<12> > grp_pqcrystals_dilithium_1_1_fu_107_sk_address1;
sc_signal< sc_logic > grp_pqcrystals_dilithium_1_1_fu_107_sk_ce1;
sc_signal< sc_lv<64> > i_0_reg_96;
sc_signal< sc_logic > ap_CS_fsm_state3;
sc_signal< sc_logic > grp_pqcrystals_dilithium_1_1_fu_107_ap_start_reg;
sc_signal< sc_logic > ap_CS_fsm_state4;
sc_signal< sc_lv<64> > zext_ln213_fu_164_p1;
sc_signal< sc_lv<64> > zext_ln213_1_fu_180_p1;
sc_signal< sc_lv<13> > trunc_ln213_fu_120_p1;
sc_signal< sc_lv<14> > trunc_ln213_1_fu_130_p1;
sc_signal< sc_lv<13> > trunc_ln212_1_fu_144_p1;
sc_signal< sc_lv<13> > sub_ln213_fu_159_p2;
sc_signal< sc_lv<14> > trunc_ln212_fu_140_p1;
sc_signal< sc_lv<4> > ap_NS_fsm;
static const sc_logic ap_const_logic_1;
static const sc_logic ap_const_logic_0;
static const sc_lv<4> ap_ST_fsm_state1;
static const sc_lv<4> ap_ST_fsm_state2;
static const sc_lv<4> ap_ST_fsm_state3;
static const sc_lv<4> ap_ST_fsm_state4;
static const sc_lv<32> ap_const_lv32_0;
static const sc_lv<32> ap_const_lv32_1;
static const sc_lv<1> ap_const_lv1_0;
static const sc_lv<64> ap_const_lv64_0;
static const sc_lv<32> ap_const_lv32_2;
static const sc_lv<1> ap_const_lv1_1;
static const sc_lv<32> ap_const_lv32_3;
static const sc_lv<13> ap_const_lv13_1FFF;
static const sc_lv<14> ap_const_lv14_973;
static const sc_lv<64> ap_const_lv64_1;
static const sc_lv<64> ap_const_lv64_974;
static const bool ap_const_boolean_1;
// Thread declarations
void thread_ap_clk_no_reset_();
void thread_add_ln213_1_fu_134_p2();
void thread_add_ln213_fu_124_p2();
void thread_ap_CS_fsm_state1();
void thread_ap_CS_fsm_state2();
void thread_ap_CS_fsm_state3();
void thread_ap_CS_fsm_state4();
void thread_ap_done();
void thread_ap_idle();
void thread_ap_ready();
void thread_ap_return();
void thread_grp_pqcrystals_dilithium_1_1_fu_107_ap_start();
void thread_i_fu_153_p2();
void thread_icmp_ln212_fu_148_p2();
void thread_m_address0();
void thread_m_ce0();
void thread_sk_address0();
void thread_sk_address1();
void thread_sk_ce0();
void thread_sk_ce1();
void thread_sm_address0();
void thread_sm_address1();
void thread_sm_ce0();
void thread_sm_ce1();
void thread_sm_d0();
void thread_sm_d1();
void thread_sm_we0();
void thread_sm_we1();
void thread_smlen();
void thread_smlen_ap_vld();
void thread_sub_ln213_1_fu_169_p2();
void thread_sub_ln213_fu_159_p2();
void thread_trunc_ln212_1_fu_144_p1();
void thread_trunc_ln212_fu_140_p1();
void thread_trunc_ln213_1_fu_130_p1();
void thread_trunc_ln213_fu_120_p1();
void thread_zext_ln213_1_fu_180_p1();
void thread_zext_ln213_fu_164_p1();
void thread_ap_NS_fsm();
void thread_hdltv_gen();
};
}
using namespace ap_rtl;
#endif
|
/* Copyright (c) 2015 Convey Computer Corporation
*
* This file is part of the OpenHT toolset located at:
*
* https://github.com/TonyBrewer/OpenHT
*
* Use and distribution licensed under the BSD 3-clause license.
* See the LICENSE file for the complete license text.
*/
#pragma once
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <string.h>
#include <assert.h>
#include <pthread.h>
#include <string>
#include <queue>
#include <list>
#include <map>
#include <errno.h>
#ifdef WIN32
#include <crtdbg.h>
#endif
#if defined(HT_SYSC) || defined(_HTV) || defined(HT_LIB_SYSC)
#include <systemc.h>
# if !defined(_HTV)
#include "sysc/HtStrFmt.h"
# endif
#endif
#if !defined(HT_LIB_HIF) && !defined(HT_LIB_SYSC)
#include "HostIntf.h"
#endif
#include "host/HtDefines.h"
#include "host/HtPlatform.h"
#if defined(HT_SYSC) || defined(_HTV)
#include "sysc/Params.h"
#endif
#if !defined(_HTV)
using namespace std;
#include "host/HtCtrlMsg.h"
#include "host/HtHif.h"
#include "host/HtModel.h"
#include "sysc/mtrand.h"
#endif
#if defined(HT_SYSC) || defined(_HTV) || defined(HT_LIB_SYSC)
#include "sysc/HtInt.h"
# if !defined(_HTV)
#include "sysc/MemMon.h"
# endif
#include "sysc/HtMemTypes.h"
#include "sysc/MemRdWrIntf.h"
#include "sysc/PersXbarStub.h"
#include "sysc/PersMiStub.h"
#include "sysc/PersMoStub.h"
#include "sysc/PersUnitCnt.h"
#include "sysc/SyscClock.h"
#include "sysc/SyscDisp.h"
#include "sysc/SyscMem.h"
#endif
#if !defined(HT_LIB_HIF) && !defined(HT_LIB_SYSC)
#include "UnitIntf.h"
#endif
|
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