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#define SC_INCLUDE_FX
#include <systemc.h>
#include "MAC.h"
#include <iostream>
#include <vector>
using namespace std;
SC_MODULE(ALEXNET)
{
CONV_RELU_1 m_CONV_RELU_1;
MAX_POOLING_1 m_MAX_POOLING_1;
CONV_RELU_2 m_CONV_RELU_2;
MAX_POOLING_2 m_MAX_POOLING_2;
CONV_RELU_3 m_CONV_RELU_3;
CONV_RELU_4 m_CONV_RELU_4;
CONV_RELU_5 m_CONV_RELU_5;
MAX_POOLING_3 m_MAX_POOLING_3;
LINEAR_RELU_1 m_LINEAR_RELU_1;
LINEAR_RELU_2 m_LINEAR_RELU_2;
LINEAR_3 m_LINEAR_3;
sc_in < bool > clk, rst;
sc_in < bool > in_valid;
sc_fifo < bool > conv1_valid;
sc_fifo < bool > mp1_valid;
sc_fifo < bool > conv2_valid;
sc_fifo < bool > mp2_valid;
sc_fifo < bool > conv3_valid;
sc_fifo < bool > conv4_valid;
sc_fifo < bool > conv5_valid;
sc_fifo < bool > mp3_valid;
sc_fifo < bool > linear1_valid;
sc_fifo < bool > linear2_valid;
sc_out < bool > linear3_valid;
sc_vector < sc_in < sc_fixed_fast<45,17> > > image{"image", 150528};
sc_vector < sc_fifo < sc_fixed_fast<45,17> > > conv1_result{"conv1_result", 193600};
sc_vector < sc_fifo < sc_fixed_fast<45,17> > > mp1_result{"mp1_result", 46656};
sc_vector < sc_fifo < sc_fixed_fast<45,17> > > conv2_result{"conv2_result", 139968};
sc_vector < sc_fifo < sc_fixed_fast<45,17> > > mp2_result{"mp2_result", 32448};
sc_vector < sc_fifo < sc_fixed_fast<45,17> > > conv3_result{"conv3_result", 64896};
sc_vector < sc_fifo < sc_fixed_fast<45,17> > > conv4_result{"conv4_result", 43264};
sc_vector < sc_fifo < sc_fixed_fast<45,17> > > conv5_result{"conv5_result", 43264};
sc_vector < sc_fifo < sc_fixed_fast<45,17> > > mp3_result{"mp3_result", 9216};
sc_vector < sc_fifo < sc_fixed_fast<45,17> > > linear1_result{"linear1_result", 4096};
sc_vector < sc_fifo < sc_fixed_fast<45,17> > > linear2_result{"linear2_result", 4096};
sc_vector < sc_out < sc_fixed_fast<45,17> > > linear3_result{"linear3_result", 1000};
SC_CTOR(ALEXNET): m_CONV_RELU_1( "m_CONV_RELU_1" ),
m_MAX_POOLING_1( "m_MAX_POOLING_1" ),
m_CONV_RELU_2( "m_CONV_RELU_2" ),
m_MAX_POOLING_2( "m_MAX_POOLING_2" ),
m_CONV_RELU_3( "m_CONV_RELU_3" ),
m_CONV_RELU_4( "m_CONV_RELU_4" ),
m_CONV_RELU_5( "m_CONV_RELU_5" ),
m_MAX_POOLING_3( "m_MAX_POOLING_3" ),
m_LINEAR_RELU_1( "m_LINEAR_RELU_1" ),
m_LINEAR_RELU_2( "m_LINEAR_RELU_2" ),
m_LINEAR_3( "m_LINEAR_3" )
{
m_CONV_RELU_1.clk(clk);
m_CONV_RELU_1.rst(rst);
m_CONV_RELU_1.in_feature_map(image);
m_CONV_RELU_1.out_feature_map(conv1_result);
m_CONV_RELU_1.in_valid(in_valid);
m_CONV_RELU_1.out_valid(conv1_valid);
// m_CONV_RELU_1.IN_VECTOR_SIZE = 150528;
// m_CONV_RELU_1.OUT_VECTOR_SIZE = 193600;
m_CONV_RELU_1.IN_CHANNELS = 3;
m_CONV_RELU_1.IN_HEIGHT = 224;
m_CONV_RELU_1.IN_WIDTH = 224;
m_CONV_RELU_1.KERNAL_SIZE = 11;
m_CONV_RELU_1.OUT_CHANNELS = 64;
m_CONV_RELU_1.OUT_HEIGHT = 55;
m_CONV_RELU_1.OUT_WIDTH = 55;
m_CONV_RELU_1.STRIDE = 4;
m_CONV_RELU_1.PADDING = 2;
m_CONV_RELU_1.weight_dir = "data/conv1_weight.txt";
m_CONV_RELU_1.bias_dir = "data/conv1_bias.txt";
m_MAX_POOLING_1.clk(clk);
m_MAX_POOLING_1.rst(rst);
m_MAX_POOLING_1.in_feature_map(conv1_result);
m_MAX_POOLING_1.out_feature_map(mp1_result);
m_MAX_POOLING_1.in_valid(conv1_valid);
m_MAX_POOLING_1.out_valid(mp1_valid);
m_CONV_RELU_2.clk(clk);
m_CONV_RELU_2.rst(rst);
m_CONV_RELU_2.in_feature_map(mp1_result);
m_CONV_RELU_2.out_feature_map(conv2_result);
m_CONV_RELU_2.in_valid(mp1_valid);
m_CONV_RELU_2.out_valid(conv2_valid);
m_MAX_POOLING_2.clk(clk);
m_MAX_POOLING_2.rst(rst);
m_MAX_POOLING_2.in_feature_map(conv2_result);
m_MAX_POOLING_2.out_feature_map(mp2_result);
m_MAX_POOLING_2.in_valid(conv2_valid);
m_MAX_POOLING_2.out_valid(mp2_valid);
m_CONV_RELU_3.clk(clk);
m_CONV_RELU_3.rst(rst);
m_CONV_RELU_3.in_feature_map(mp2_result);
m_CONV_RELU_3.out_feature_map(conv3_result);
m_CONV_RELU_3.in_valid(mp2_valid);
m_CONV_RELU_3.out_valid(conv3_valid);
m_CONV_RELU_4.clk(clk);
m_CONV_RELU_4.rst(rst);
m_CONV_RELU_4.in_feature_map(conv3_result);
m_CONV_RELU_4.out_feature_map(conv4_result);
m_CONV_RELU_4.in_valid(conv3_valid);
m_CONV_RELU_4.out_valid(conv4_valid);
m_CONV_RELU_5.clk(clk);
m_CONV_RELU_5.rst(rst);
m_CONV_RELU_5.in_feature_map(conv4_result);
m_CONV_RELU_5.out_feature_map(conv5_result);
m_CONV_RELU_5.in_valid(conv4_valid);
m_CONV_RELU_5.out_valid(conv5_valid);
m_MAX_POOLING_3.clk(clk);
m_MAX_POOLING_3.rst(rst);
m_MAX_POOLING_3.in_feature_map(conv5_result);
m_MAX_POOLING_3.out_feature_map(mp3_result);
m_MAX_POOLING_3.in_valid(conv5_valid);
m_MAX_POOLING_3.out_valid(mp3_valid);
m_LINEAR_RELU_1.clk(clk);
m_LINEAR_RELU_1.rst(rst);
m_LINEAR_RELU_1.in_feature_map(mp3_result);
m_LINEAR_RELU_1.out_feature_map(linear1_result);
m_LINEAR_RELU_1.in_valid(mp3_valid);
m_LINEAR_RELU_1.out_valid(linear1_valid);
m_LINEAR_RELU_2.clk(clk);
m_LINEAR_RELU_2.rst(rst);
m_LINEAR_RELU_2.in_feature_map(linear1_result);
m_LINEAR_RELU_2.out_feature_map(linear2_result);
m_LINEAR_RELU_2.in_valid(linear1_valid);
m_LINEAR_RELU_2.out_valid(linear2_valid);
m_LINEAR_3.clk(clk);
m_LINEAR_3.rst(rst);
m_LINEAR_3.in_feature_map(linear2_result);
m_LINEAR_3.out_feature_map(linear3_result);
m_LINEAR_3.in_valid(linear2_valid);
m_LINEAR_3.out_valid(linear3_valid);
}
}; |
/**
#define meta ...
prInt32f("%s\n", meta);
**/
/*
All rights reserved to Alireza Poshtkohi (c) 1999-2023.
Email: [email protected]
Website: http://www.poshtkohi.info
*/
#ifndef __tb_h__
#define __tb_h__
#include <systemc.h>
#include <vector>
using namespace std;
SC_MODULE(tb)
{
// inputs
sc_in<bool> clk;
sc_in<sc_uint<64> > rt_des_data_i;
sc_in<bool> rt_des_ready_i;
// outputs
sc_out<bool> rt_load_o;
sc_out<sc_uint<64> >rt_des_data_o;
sc_out<sc_uint<64> >rt_des_key_o;
sc_out<bool> rt_decrypt_o;
sc_out<bool> rt_reset;
void send();
void recv();
SC_CTOR(tb)
{
SC_THREAD(send);
sensitive << clk.pos();
SC_THREAD(recv);
sensitive << rt_des_ready_i.pos();
}
~tb()
{
}
};
#endif
|
#ifndef _param_in_h
#define _param_in_h
#include <systemc.h>
#include "hocl.h"
template<class T>
SC_MODULE(param_in) {
sc_in<bool> clk;
sc_fifo_out<T> o;
void main(void) {
while ( 1 ) {
o.write(val);
if ( trace ) cout << modname << " put " << val << " at " << sc_time_stamp() << endl;
wait(clk.posedge_event());
}
}
SC_HAS_PROCESS(param_in);
param_in(sc_module_name name_, T val_, bool trace_=false) :
modname(name_), sc_module(name_), val(val_), trace(trace_)
{
SC_THREAD(main);
}
~param_in() { }
private:
// Local variables
T val;
// Service
bool trace;
sc_module_name modname;
};
#endif
|
/**************************************************************************
* *
* Algorithmic C (tm) Simulation Utilities *
* *
* Software Version: 1.6 *
* *
* Release Date : Wed Feb 21 17:43:38 PST 2024 *
* Release Type : Production Release *
* Release Build : 1.6.0 *
* *
* Copyright 2020 Siemens *
* *
**************************************************************************
* Licensed under the Apache License, Version 2.0 (the "License"); *
* you may not use this file except in compliance with the License. *
* You may obtain a copy of the License at *
* *
* http://www.apache.org/licenses/LICENSE-2.0 *
* *
* Unless required by applicable law or agreed to in writing, software *
* distributed under the License is distributed on an "AS IS" BASIS, *
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or *
* implied. *
* See the License for the specific language governing permissions and *
* limitations under the License. *
**************************************************************************
* *
* The most recent version of this package is available at github. *
* *
*************************************************************************/
#ifndef _INCLUDE_AC_SYSC_TRACE_H_
#define _INCLUDE_AC_SYSC_TRACE_H_
//
// ac_sysc_trace.h
//
// Helpful macros and functionality for simulation trace SystemC designs.
//
#include <systemc.h>
//
// The SC_SIG, SC_VAR, and SC_VAR_NM macros assume a mechanism to get an open sc_trace_file
// This is the mechanism pto provide that
// See: https://stackoverflow.com/questions/18860895/how-to-initialize-static-members-in-the-header
//
// In sc_main, do this:
// sc_trace_file *trace_file = sc_trace_static::setup_trace_file("trace");
//
class sc_trace_static
{
public:
sc_trace_static() {}
~sc_trace_static() {(void) static_accessor(0,true);}
static sc_trace_file *static_accessor(sc_trace_file *newPtr = 0, bool done=false) {
static sc_trace_file *staticPtr = 0;
if (newPtr) {
staticPtr = newPtr;
}
if (done && staticPtr) {
sc_close_vcd_trace_file(staticPtr);
}
return (staticPtr);
}
static sc_trace_file *setup_trace_file(const char *fname) {
sc_trace_file *retPtr = static_accessor();
if (retPtr) {
std::cout << "Error: Can only call CCS_TraceFileStatics::setup_trace_file once. Original file used!" << std::endl;
} else {
if (fname) {
retPtr = sc_create_vcd_trace_file(fname);
} else {
retPtr = sc_create_vcd_trace_file("trace");
}
(void) static_accessor(retPtr);
}
return (retPtr);
}
};
#ifndef _CCS_OLD_CONNECTIONS_
//
// sc_trace helpers used when the below macros are used to declared variables
// and signals which are to be traced.
template <class T>
struct sc_object_tracer {
sc_object_tracer(T &obj) {
sc_trace(sc_trace_static::static_accessor(), obj, obj.name());
}
~sc_object_tracer() {}
};
template <class T>
struct sc_var_tracer {
sc_var_tracer(T &obj, const std::string &nm) {
sc_trace(sc_trace_static::static_accessor(), obj, nm);
}
~sc_var_tracer() {}
};
#else
// Hardwired for this global fileptr
extern sc_trace_file *trace_file_ptr;
template <class T>
struct sc_object_tracer {
sc_object_tracer(T &obj) {
sc_trace(trace_file_ptr, obj, obj.name());
}
~sc_object_tracer() {}
};
template <class T>
struct sc_var_tracer {
sc_var_tracer(T &obj, const std::string &nm) {
sc_trace(trace_file_ptr, obj, nm);
}
~sc_var_tracer() {}
};
#endif
// Macro: SC_SIG(T,N)
// Useful for declaring an sc_signal of type T with name N and cause it to be traced.
//
// Macro: SC_VAR(T,N)
// Useful for declaring avariable of type T with name N and cause it to be traced.
//
// Macro: SC_VARNM(T,N,NM)
// Useful for declaring a variable of type T with name N and cause it to be traced.
// The name used for tracing will use scope NM for its name.
#if (defined(SC_SIG) || defined(SC_VAR) || defined(SC_VAR_NM))
#warning One or more of the following is defined: SC_SIG.SC_VAR,SC_VAR_NM. Definition conflicts with their usage as Systemc helpers.
#warning Unpredictable systemc simulation may result.
#else
#ifndef __SYNTHESIS__
#define SC_SIG(T,N) sc_signal<T> N{#N} ; sc_object_tracer<sc_signal<T>> N ## _tracer { N }
#define SC_VAR(T,N) T N ; sc_var_tracer<T> N ## _tracer { N, std::string(name()) + std::string(".") + #N }
#define SC_VAR_NM(T,N, NM) T N ; sc_var_tracer<T> N ## _tracer { N, std::string(NM) + std::string(".") + #N }
#else
#define SC_SIG(T,N) sc_signal<T> N{#N}
#define SC_VAR(T,N) T N
#define SC_VAR_NM(T,N, NM) T N
#endif
#endif
/**
* Example of how to enable tracing for user defined structs:
* The inline function is of interest.
*
struct MyType
{
int info {0};
bool flag {false};
inline friend void sc_trace(sc_trace_file *tf, const MyType & v, const std::string& NAME ) {
sc_trace(tf,v.info, NAME + ".info");
sc_trace(tf,v.flag, NAME + ".flag");
}
};
**/
#endif // _INCLUDE_AC_SYSC_TRACE_H_
|
/**************************************************************************
* *
* Algorithmic C (tm) Simulation Utilities *
* *
* Software Version: 1.6 *
* *
* Release Date : Wed Feb 21 17:43:38 PST 2024 *
* Release Type : Production Release *
* Release Build : 1.6.0 *
* *
* Copyright 2020 Siemens *
* *
**************************************************************************
* Licensed under the Apache License, Version 2.0 (the "License"); *
* you may not use this file except in compliance with the License. *
* You may obtain a copy of the License at *
* *
* http://www.apache.org/licenses/LICENSE-2.0 *
* *
* Unless required by applicable law or agreed to in writing, software *
* distributed under the License is distributed on an "AS IS" BASIS, *
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or *
* implied. *
* See the License for the specific language governing permissions and *
* limitations under the License. *
**************************************************************************
* *
* The most recent version of this package is available at github. *
* *
*************************************************************************/
//*****************************************************************************************
// File: ccs_types.h
//
// Description: Provides helper functions to convert between datatypes.
//
// Revision History:
// 1.5.0 - Add mc_typedef_T_traits<sc_logic>
// 1.2.1 - Initial version on github
//*****************************************************************************************
//------------------------------------------------------------------------------
// Catapult Synthesis - Sample I/O Port Library
//
// This document may be used and distributed without restriction provided that
// this copyright statement is not removed from the file and that any derivative
// work contains this copyright notice.
//
// The design information contained in this file is intended to be an example
// of the functionality which the end user may study in preparation for creating
// their own custom interfaces. This design does not necessarily present a
// complete implementation of the named protocol or standard.
//
//------------------------------------------------------------------------------
#ifndef __CCS_TYPES_H
#define __CCS_TYPES_H
#include <systemc.h>
#include <tlm.h>
#undef for
#include <sstream>
// Includes all AC types
#include <ac_sc.h>
#include <ac_complex.h>
#include <mc_typeconv.h>
#ifndef CALYPTO_SYSC
#define ccs_concat(n1,n2) (n1 ? ((std::string(n1)+"_"+n2).c_str()) : 0)
#else
#define ccs_concat(n1,n2) (n2)
#endif
#ifndef P2P_DEFAULT_VIEW
#define P2P_DEFAULT_VIEW TLM
#endif
// This enumeration defines the abstraction of channels and ports
// TLM - Uses an abstract, transaction based interconnect object, usually an array or TLM FIFO.
// SYN - Uses signal based interconnect objects. This view is always used by synthesis.
// AUTO - Default setting. Channel is TLM in source simulation and SYN for synthesis and SCVerify.
enum abstraction_t {TLM = 0, SYN = 1, AUTO = 2};
namespace mc_typedef_T_traits_private
{
// helper structs for statically computing log2 like functions (nbits, log2_floor, log2_ceil)
// using recursive templates
template<unsigned char N>
struct s_N {
template<unsigned X>
struct s_X {
enum {
X2 = X >> N,
N_div_2 = N >> 1,
nbits = X ? (X2 ? N + s_N<N_div_2>::template s_X<X2>::nbits : s_N<N_div_2>::template s_X<X>::nbits) : 0
};
};
};
template<> struct s_N<0> {
template<unsigned X>
struct s_X {
enum {nbits = !!X };
};
};
};
// compiler time constant for log2 like functions
template<unsigned X>
struct nbits {
enum { val = mc_typedef_T_traits_private::s_N<16>::s_X<X>::nbits };
};
// Helper struct for determining bitwidth of types
template <class T> struct mc_typedef_T_traits;
// INT <-> SC_LV
template <>
struct mc_typedef_T_traits< int > {
enum { bitwidth = 32,
issigned = 1
};
};
// UINT <-> SC_LV
template <>
struct mc_typedef_T_traits< unsigned int > {
enum { bitwidth = 32,
issigned = 0
};
};
// SHORT <-> SC_LV
template <>
struct mc_typedef_T_traits< short > {
enum { bitwidth = 16,
issigned = 1
};
};
// USHORT <-> SC_LV
template <>
struct mc_typedef_T_traits< unsigned short > {
enum { bitwidth = 16,
issigned = 0
};
};
// CHAR <-> SC_LV
template <>
struct mc_typedef_T_traits< char > {
enum { bitwidth = 8,
issigned = 1
};
};
// UCHAR <-> SC_LV
template <>
struct mc_typedef_T_traits< unsigned char > {
enum { bitwidth = 8,
issigned = 0
};
};
// LONG LONG <-> SC_LV
template <>
struct mc_typedef_T_traits< long long > {
enum { bitwidth = 64,
issigned = 1
};
};
// ULONG LONG <-> SC_LV
template <>
struct mc_typedef_T_traits< unsigned long long > {
enum { bitwidth = 64,
issigned = 0
};
};
// LONG <-> SC_LV
template <>
struct mc_typedef_T_traits< long > {
enum { bitwidth = 32,
issigned = 1
};
};
// ULONG <-> SC_LV
template <>
struct mc_typedef_T_traits< unsigned long > {
enum { bitwidth = 32,
issigned = 0
};
};
// BOOL <-> SC_LV
template <>
struct mc_typedef_T_traits< bool > {
enum { bitwidth = 1,
issigned = 0
};
};
// SC_LV <-> SC_LV
template <int Twidth>
struct mc_typedef_T_traits< sc_lv<Twidth> > {
enum { bitwidth = Twidth,
issigned = 0
};
};
// SC_UINT <-> SC_LV
template <int Twidth>
struct mc_typedef_T_traits< sc_uint<Twidth> > {
enum { bitwidth = Twidth,
issigned = 0
};
};
// SC_BV <-> SC_LV
template <int Twidth>
struct mc_typedef_T_traits< sc_bv<Twidth> > {
enum { bitwidth = Twidth,
issigned = 0
};
};
// SC_BIT <-> SC_LV
template<>
struct mc_typedef_T_traits< sc_bit > {
enum { bitwidth = 1,
issigned = 0
};
};
// SC_LOGIC <-> SC_LV
template<>
struct mc_typedef_T_traits< sc_logic > {
enum { bitwidth = 1,
issigned = 0
};
};
// SC_INT <-> SC_LV
template <int Twidth>
struct mc_typedef_T_traits< sc_int<Twidth> > {
enum { bitwidth = Twidth,
issigned = 1
};
};
// SC_BIGUINT <-> SC_LV
template <int Twidth>
struct mc_typedef_T_traits< sc_biguint<Twidth> > {
enum { bitwidth = Twidth,
issigned = 0
};
};
// SC_BIGINT <-> SC_LV
template <int Twidth>
struct mc_typedef_T_traits< sc_bigint<Twidth> > {
enum { bitwidth = Twidth,
issigned = 1
};
};
#if defined(SC_INCLUDE_FX)
// SC_FIXED <-> SC_LV
template<int Twidth, int Ibits, sc_q_mode Qmode, sc_o_mode Omode, int Nbits>
struct mc_typedef_T_traits< sc_fixed<Twidth,Ibits,Qmode,Omode,Nbits> > {
enum { bitwidth = Twidth,
issigned = 1
};
};
// SC_UFIXED <-> SC_LV
template<int Twidth, int Ibits, sc_q_mode Qmode, sc_o_mode Omode, int Nbits>
struct mc_typedef_T_traits< sc_ufixed<Twidth,Ibits,Qmode,Omode,Nbits> > {
enum { bitwidth = Twidth,
issigned = 0
};
};
#endif
// AC_INT (signed) <-> SC_LV
template <int Twidth>
struct mc_typedef_T_traits< ac_int<Twidth,true> > {
enum { bitwidth = Twidth,
issigned = 1
};
};
// AC_INT (unsigned) <-> SC_LV
template <int Twidth>
struct mc_typedef_T_traits< ac_int<Twidth,false> > {
enum { bitwidth = Twidth,
issigned = 0
};
};
// AC_FIXED (signed) <-> SC_LV
template<int Twidth, int Ibits, bool Signed, ac_q_mode Qmode, ac_o_mode Omode>
struct mc_typedef_T_traits< ac_fixed<Twidth,Ibits,Signed,Qmode,Omode> > {
enum { bitwidth = Twidth,
issigned = Signed?1:0
};
};
#ifdef __AC_FLOAT_H
// Guard added because SLEC doesn't have ac_float support yet
// AC_FLOAT (unsigned only) <-> SC_LV
template<int MTbits, int MIbits, int Ebits, ac_q_mode Qmode>
struct mc_typedef_T_traits<ac_float<MTbits,MIbits,Ebits,Qmode> > {
enum { bitwidth = MTbits+Ebits,
issigned = 0
};
};
#endif
template<class T> // Template arguments may be added as needed
struct mc_typedef_T_traits< ac_complex<T> > {
enum { bitwidth = mc_typedef_T_traits<T>::bitwidth * 2, // Requires bitwidth trait for based type
issigned = false
};
};
template<class T>
inline void type_to_vector(const ac_complex<T> &in, int length, sc_lv<mc_typedef_T_traits< ac_complex<T> >::bitwidth> &rvec)
{
sc_lv<mc_typedef_T_traits<T>::bitwidth> vec_r, vec_i;
type_to_vector(in.r(),mc_typedef_T_traits<T>::issigned,vec_r);
type_to_vector(in.i(),mc_typedef_T_traits<T>::issigned,vec_i);
rvec = (vec_r << mc_typedef_T_traits<T>::bitwidth) | vec_i;
}
template<class T>
inline void vector_to_type(const sc_lv<mc_typedef_T_traits< ac_complex<T> >::bitwidth> &in, bool issigned, ac_complex<T> *result)
{
sc_lv<mc_typedef_T_traits<T>::bitwidth> vec_r, vec_i;
vec_r = in >> mc_typedef_T_traits<T>::bitwidth;
vec_i = in;
T r, i;
vector_to_type(vec_r,mc_typedef_T_traits<T>::issigned,&r);
vector_to_type(vec_i,mc_typedef_T_traits<T>::issigned,&i);
result->set_r(r);
result->set_i(i);
}
// Helper Classes for checking that reset was called and all ports are bound
class p2p_checker
{
mutable bool is_ok;
#ifndef __SYNTHESIS__
const char *objname;
std::stringstream error_string;
#endif
public:
p2p_checker (const char *name, const char *func_name, const char *operation) :
is_ok(false) {
#ifndef __SYNTHESIS__
objname = name;
error_string << "You must " << func_name << " before you can " << operation << ".";
#endif
}
inline void ok () {
is_ok = true;
}
inline void test () const {
#ifndef __SYNTHESIS__
if ( !is_ok ) {
SC_REPORT_ERROR(objname, error_string.str().c_str());
is_ok = true; // Only report error message one time
}
#endif
}
};
#endif
|
#include <systemc.h>
//
// Every HW component class has to be derived from :class:`hwt.hwModule.HwModule` class
//
// .. hwt-autodoc::
//
SC_MODULE(Showcase0) {
// ports
sc_in<sc_uint<32>> a;
sc_in<sc_int<32>> b;
sc_out<sc_uint<32>> c;
sc_in_clk clk;
sc_out<sc_uint<1>> cmp_0;
sc_out<sc_uint<1>> cmp_1;
sc_out<sc_uint<1>> cmp_2;
sc_out<sc_uint<1>> cmp_3;
sc_out<sc_uint<1>> cmp_4;
sc_out<sc_uint<1>> cmp_5;
sc_out<sc_uint<32>> contOut;
sc_in<sc_uint<32>> d;
sc_in<sc_uint<1>> e;
sc_out<sc_uint<1>> f;
sc_out<sc_uint<16>> fitted;
sc_out<sc_uint<8>> g;
sc_out<sc_uint<8>> h;
sc_in<sc_uint<2>> i;
sc_out<sc_uint<8>> j;
sc_out<sc_uint<32>> k;
sc_out<sc_uint<1>> out;
sc_out<sc_uint<1>> output;
sc_in<sc_uint<1>> rst_n;
sc_out<sc_uint<8>> sc_signal_0;
// component instances
// internal signals
sc_uint<32> const_private_signal = sc_uint<32>("0x0000007B");
sc_int<8> fallingEdgeRam[4];
sc_uint<1> r = sc_uint<1>("0b0");
sc_uint<2> r_0 = sc_uint<2>("0b00");
sc_uint<2> r_1 = sc_uint<2>("0b00");
sc_signal<sc_uint<1>> r_next;
sc_signal<sc_uint<2>> r_next_0;
sc_signal<sc_uint<2>> r_next_1;
sc_uint<8> rom[4] = {sc_uint<8>("0x00"),
sc_uint<8>("0x01"),
sc_uint<8>("0x02"),
sc_uint<8>("0x03"),
};
void assig_process_c() {
c.write(static_cast<sc_uint<32>>(a.read() + static_cast<sc_uint<32>>(b.read())));
}
void assig_process_cmp_0() {
cmp_0.write(a.read() < sc_uint<32>("0x00000004"));
}
void assig_process_cmp_1() {
cmp_1.write(a.read() > sc_uint<32>("0x00000004"));
}
void assig_process_cmp_2() {
cmp_2.write(b.read() <= sc_int<32>("0x00000004"));
}
void assig_process_cmp_3() {
cmp_3.write(b.read() >= sc_int<32>("0x00000004"));
}
void assig_process_cmp_4() {
cmp_4.write(b.read() != sc_int<32>("0x00000004"));
}
void assig_process_cmp_5() {
cmp_5.write(b.read() == sc_int<32>("0x00000004"));
}
void assig_process_contOut() {
contOut.write(static_cast<sc_uint<32>>(const_private_signal));
}
void assig_process_f() {
f.write(r);
}
void assig_process_fallingEdgeRam() {
sc_signal<sc_uint<32>> tmpConcat_0;
tmpConcat_0.write((sc_uint<24>("0x000000"), static_cast<sc_uint<8>>(static_cast<sc_uint<8>>(fallingEdgeRam[r_1])), ));
{
(fallingEdgeRam[r_1]).write(static_cast<sc_int<8>>(a.read().range(sc_int<32>("0x00000008"), sc_int<32>("0x00000000"))));
k = tmpConcat_0.read();
}
}
void assig_process_fitted() {
fitted.write(static_cast<sc_uint<16>>(a.read().range(sc_int<32>("0x00000010"), sc_int<32>("0x00000000"))));
}
void assig_process_g() {
sc_signal<sc_uint<2>> tmpConcat_1;
sc_signal<sc_uint<8>> tmpConcat_0;
tmpConcat_1.write((a.read()[sc_int<32>("0x00000001")] & b.read()[sc_int<32>("0x00000001")], a.read()[sc_int<32>("0x00000000")] ^ b.read()[sc_int<32>("0x00000000")] | a.read()[sc_int<32>("0x00000001")], ));
tmpConcat_0.write((tmpConcat_1.read(), static_cast<sc_uint<6>>(a.read().range(sc_int<32>("0x00000006"), sc_int<32>("0x00000000"))), ));
g.write(tmpConcat_0.read());
}
void assig_process_h() {
if (a.read()[sc_int<32>("0x00000002")] == sc_uint<1>("0b1"))
if (r == sc_uint<1>("0b1"))
h.write(sc_uint<8>("0x00"));
else if (a.read()[sc_int<32>("0x00000001")] == sc_uint<1>("0b1"))
h.write(sc_uint<8>("0x01"));
else
h.write(sc_uint<8>("0x02"));
}
void assig_process_j() {
j = static_cast<sc_uint<8>>(rom[r_1]);
}
void assig_process_out() {
out.write(sc_uint<1>("0b0"));
}
void assig_process_output() {
output.write(sc_uint<1>("0bX"));
}
void assig_process_r() {
if (rst_n.read() == sc_uint<1>("0b0")) {
r_1 = sc_uint<2>("0b00");
r_0 = sc_uint<2>("0b00");
r = sc_uint<1>("0b0");
} else {
r_1 = r_next_1.read();
r_0 = r_next_0.read();
r = r_next.read();
}
}
void assig_process_r_next() {
r_next_0.write(i.read());
}
void assig_process_r_next_0() {
r_next_1.write(r_0);
}
void assig_process_r_next_1() {
if (r == sc_uint<1>("0b0"))
r_next.write(e.read());
else
r_next.write(r);
}
void assig_process_sc_signal_0() {
switch(a.read()) {
case sc_uint<32>("0x00000001"): {
sc_signal_0.write(sc_uint<8>("0x00"));
break;
}
case sc_uint<32>("0x00000002"): {
sc_signal_0.write(sc_uint<8>("0x01"));
break;
}
case sc_uint<32>("0x00000003"): {
sc_signal_0.write(sc_uint<8>("0x03"));
break;
}
default:
sc_signal_0.write(sc_uint<8>("0x04"));
}
}
SC_CTOR(Showcase0) {
SC_METHOD(assig_process_c);
sensitive << a << b;
SC_METHOD(assig_process_cmp_0);
sensitive << a;
SC_METHOD(assig_process_cmp_1);
sensitive << a;
SC_METHOD(assig_process_cmp_2);
sensitive << b;
SC_METHOD(assig_process_cmp_3);
sensitive << b;
SC_METHOD(assig_process_cmp_4);
sensitive << b;
SC_METHOD(assig_process_cmp_5);
sensitive << b;
assig_process_contOut();
SC_METHOD(assig_process_f);
sensitive << r;
SC_METHOD(assig_process_fallingEdgeRam);
sensitive << clk.neg();
SC_METHOD(assig_process_fitted);
sensitive << a;
SC_METHOD(assig_process_g);
sensitive << a << b;
SC_METHOD(assig_process_h);
sensitive << a << r;
SC_METHOD(assig_process_j);
sensitive << clk.pos();
assig_process_out();
assig_process_output();
SC_METHOD(assig_process_r);
sensitive << clk.pos();
SC_METHOD(assig_process_r_next);
sensitive << i;
SC_METHOD(assig_process_r_next_0);
sensitive << r_0;
SC_METHOD(assig_process_r_next_1);
sensitive << e << r;
SC_METHOD(assig_process_sc_signal_0);
sensitive << a;
// connect ports
}
};
|
/*******************************************************************************
* tb_gpio.h -- Copyright 2019 (c) Glenn Ramalho - RFIDo Design
*******************************************************************************
* Description:
* Testbench for the GPIO models.
*******************************************************************************
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
#ifndef _TB_GPIO_H
#define _TB_GPIO_H
#include <systemc.h>
#include "gpio_simple.h"
#include "gpio_mix.h"
#include "gpio_mf.h"
#include "gpio_mfmix.h"
#include "gn_mixed.h"
SC_MODULE(tb_gpio) {
public:
sc_signal_resolved pin1 {"pin1"};
gn_signal_mix pin_a1 {"pin_a1"};
gn_signal_mix pin_a2 {"pin_a2"};
sc_signal_resolved pin3 {"pin3"};
sc_signal<bool> f1in {"f1in"}, f1out {"f1out"}, f1en {"f1en"};
sc_signal<bool> f2in {"f2in"}, f2out {"f2out"}, f2en {"f2en"};
sc_signal<bool> f3in {"f3in"}, f3out {"f3out"}, f3en {"f3en"};
gpio i_gpio{"i_gpio",
GPIOMODE_NONE | GPIOMODE_INPUT | GPIOMODE_OUTPUT | GPIOMODE_INOUT |
GPIOMODE_WPU | GPIOMODE_WPD | GPIOMODE_OD,
GPIOMODE_NONE};
gpio_mix i_gpio_mix{"i_gpio_mix",
GPIOMODE_NONE | GPIOMODE_INPUT | GPIOMODE_OUTPUT | GPIOMODE_INOUT |
GPIOMODE_WPU | GPIOMODE_WPD | GPIOMODE_OD,
GPIOMODE_NONE, true, GPIOMF_GPIO};
gpio_mfmix i_gpio_mfmix{"i_gpio_mfmix",
GPIOMODE_NONE | GPIOMODE_INPUT | GPIOMODE_OUTPUT | GPIOMODE_INOUT |
GPIOMODE_WPU | GPIOMODE_WPD | GPIOMODE_OD,
GPIOMODE_NONE, true, GPIOMF_GPIO};
gpio_mf i_gpio_mf{"i_gpio_mf",
GPIOMODE_NONE | GPIOMODE_INPUT | GPIOMODE_OUTPUT | GPIOMODE_INOUT |
GPIOMODE_WPU | GPIOMODE_WPD | GPIOMODE_OD,
GPIOMODE_NONE, GPIOMF_GPIO};
/* Testenches */
int tn;
void testbench();
void t0();
void expect(const char *name, bool a, sc_logic v);
void expect(const char *name, sc_logic a, sc_logic v);
void expect(const char *name, gn_mixed a, sc_logic v);
void expectfunc(const char *name, int a, int v);
SC_CTOR(tb_gpio) {
i_gpio.pin(pin1);
i_gpio_mix.pin(pin_a1);
i_gpio_mfmix.pin(pin_a2);
/* Function 1 */
i_gpio_mfmix.fin(f1in);
i_gpio_mfmix.fen(f1en);
i_gpio_mfmix.fout(f1out);
/* Function 2 */
i_gpio_mfmix.fin(f2in);
i_gpio_mfmix.fen(f2en);
i_gpio_mfmix.fout(f2out);
i_gpio_mf.pin(pin3);
/* Function 1 */
i_gpio_mf.fin(f3in);
i_gpio_mf.fen(f3en);
i_gpio_mf.fout(f3out);
SC_THREAD(testbench);
}
void trace(sc_trace_file *tf);
};
#endif
|
#ifndef TOP_HPP
#define TOP_HPP
#include <systemc.h>
#include "scheduler.hpp"
#include "processing_engine.hpp"
#include "verbose.hpp"
#define CORE_BIND(NAME, INDEX) \
NAME.clk(clk); \
NAME.reset(reset); \
NAME.from_scheduler_instructions(npu_instructions[INDEX]); \
NAME.from_scheduler_weight(npu_weight[INDEX]); \
NAME.from_scheduler_input(npu_input[INDEX]); \
NAME.to_scheduler(npu_output[INDEX]);
class top_module : public sc_core::sc_module
{
public:
sc_in<bool> clk;
sc_in<bool> reset;
// IO
sc_fifo_in< sc_uint<64> > dma_config;
sc_fifo_in<float> dma_weight;
sc_fifo_in<float> dma_input;
sc_fifo_out<float> dma_output;
sc_fifo<sc_uint<34>> npu_instructions[CORE];
sc_fifo<float> npu_weight[CORE];
sc_fifo<float> npu_input[CORE];
sc_fifo<float> npu_output[CORE];
// Modules
scheduler_module mod_scheduler;
// Cores
#if CORE == 8
processing_engine_module mod_core_1;
processing_engine_module mod_core_2;
processing_engine_module mod_core_3;
processing_engine_module mod_core_4;
processing_engine_module mod_core_5;
processing_engine_module mod_core_6;
processing_engine_module mod_core_7;
processing_engine_module mod_core_8;
#elif CORE == 4
processing_engine_module mod_core_1;
processing_engine_module mod_core_2;
processing_engine_module mod_core_3;
processing_engine_module mod_core_4;
#elif CORE == 2
processing_engine_module mod_core_1;
processing_engine_module mod_core_2;
#elif CORE == 1
processing_engine_module mod_core_1;
#endif
top_module(sc_module_name name);
SC_HAS_PROCESS(top_module);
};
#endif |
/**
* Author: Anubhav Tomar
*
* Program Memory Definition
**/
#ifndef PM_H
#define PM_H
#include<systemc.h>
template <class _addrSize>
class _programMemory : public sc_module {
public:
// Inputs
sc_in<_addrSize> _addrPC;
sc_in<bool> _pmRead;
// Outputs
sc_out<sc_uint<16> > _instructionOut;
SC_HAS_PROCESS(_programMemory);
_programMemory(sc_module_name name) : sc_module(name) {
SC_METHOD(_read);
sensitive<<_pmRead.pos();
};
void write(std::vector<sc_uint<16> > _program) {
cout<<"@ "<<sc_time_stamp()<<"------Start _programLoad--------"<<endl<<endl<<endl;
sc_uint<5> _len = _program.size();
for(sc_uint<5> i ; i < _len ; i++) {
_programStore.push_back(_program[i]);
cout<<"/**===================================PROGRAM MEMORY LOG===================================**/"<<endl;
cout<<" Address Input : "<<i<<endl;
cout<<" Instruction Output : "<<_program[i]<<endl;
cout<<"/**===================================PROGRAM MEMORY LOG===================================**/"<<endl<<endl<<endl;
}
cout<<"@ "<<sc_time_stamp()<<"------End _programLoad--------"<<endl<<endl<<endl;
}
private:
std::vector<_addrSize> _programStore;
void _read () {
cout<<"@ "<<sc_time_stamp()<<"------Start _read--------"<<endl<<endl<<endl;
_addrSize _addr = _addrPC.read();
if(_addr < _programStore.size()) {
_instructionOut.write(_programStore[_addr]);
cout<<"/**===================================PROGRAM MEMORY LOG===================================**/"<<endl;
cout<<" Address Input : "<<_addr<<endl;
cout<<" Instruction Output : "<<_programStore[_addr]<<endl;
cout<<"/**===================================PROGRAM MEMORY LOG===================================**/"<<endl<<endl<<endl;
} else {
cout<<"/**===================================PROGRAM MEMORY LOG===================================**/"<<endl;
cout<<" Address Input : "<<_addr<<endl;
cout<<" Instruction Output : NOP Found"<<endl;
cout<<"/**===================================PROGRAM MEMORY LOG===================================**/"<<endl<<endl<<endl;
}
cout<<"@ "<<sc_time_stamp()<<"------End _read--------"<<endl<<endl<<endl;
};
};
#endif |
#include <systemc.h>
#include "testbench_vbase.h"
#include "tb_memory.h"
#include "tb_axi4_driver.h"
#include "tb_sdram_mem.h"
#include "tb_mem_test.h"
#include "sdram_axi.h"
#define MEM_BASE 0x00000000
#define MEM_SIZE (512 * 1024)
//-----------------------------------------------------------------
// Module
//-----------------------------------------------------------------
class testbench: public testbench_vbase
{
public:
tb_axi4_driver *m_driver;
tb_mem_test *m_sequencer;
sdram_axi *m_dut;
tb_sdram_mem *m_mem;
sc_signal <axi4_master> axi_m;
sc_signal <axi4_slave> axi_s;
sc_signal <sdram_io_master> sdram_io_m;
sc_signal <sdram_io_slave> sdram_io_s;
//-----------------------------------------------------------------
// process: Drive input sequence
//-----------------------------------------------------------------
void process(void)
{
wait();
m_driver->enable_delays(true);
// Allocate some memory
m_mem->add_region(MEM_BASE, MEM_SIZE);
// Allocate some memory
m_sequencer->add_region(MEM_BASE, MEM_SIZE);
m_sequencer->trace_access(true);
// Initialise to memory known value
for (int i=0;i<MEM_SIZE;i++)
{
m_sequencer->write(MEM_BASE + i, i);
m_mem->write(MEM_BASE + i, i);
}
m_sequencer->start(50000);
m_sequencer->wait_complete();
sc_stop();
}
SC_HAS_PROCESS(testbench);
testbench(sc_module_name name): testbench_vbase(name)
{
m_driver = new tb_axi4_driver("DRIVER");
m_driver->axi_out(axi_m);
m_driver->axi_in(axi_s);
m_sequencer = new tb_mem_test("SEQ", m_driver, 32);
m_sequencer->clk_in(clk);
m_sequencer->rst_in(rst);
m_dut = new sdram_axi("MEM");
m_dut->clk_in(clk);
m_dut->rst_in(rst);
m_dut->inport_in(axi_m);
m_dut->inport_out(axi_s);
m_dut->sdram_out(sdram_io_m);
m_dut->sdram_in(sdram_io_s);
m_mem = new tb_sdram_mem("TB_MEM");
m_mem->clk_in(clk);
m_mem->rst_in(rst);
m_mem->sdram_in(sdram_io_m);
m_mem->sdram_out(sdram_io_s);
verilator_trace_enable("verilator.vcd", m_dut);
}
};
|
#ifndef SDRAM_IO_H
#define SDRAM_IO_H
#include <systemc.h>
//----------------------------------------------------------------
// Interface (master)
//----------------------------------------------------------------
class sdram_io_master
{
public:
// Members
sc_uint <1> CLK;
sc_uint <1> CKE;
sc_uint <1> CS;
sc_uint <1> RAS;
sc_uint <1> CAS;
sc_uint <1> WE;
sc_uint <2> DQM;
sc_uint <13> ADDR;
sc_uint <2> BA;
sc_uint <16> DATA_OUTPUT;
sc_uint <1> DATA_OUT_EN;
// Construction
sdram_io_master() { init(); }
void init(void)
{
CLK = 0;
CKE = 0;
CS = 0;
RAS = 0;
CAS = 0;
WE = 0;
DQM = 0;
ADDR = 0;
BA = 0;
DATA_OUTPUT = 0;
DATA_OUT_EN = 0;
}
bool operator == (const sdram_io_master & v) const
{
bool eq = true;
eq &= (CLK == v.CLK);
eq &= (CKE == v.CKE);
eq &= (CS == v.CS);
eq &= (RAS == v.RAS);
eq &= (CAS == v.CAS);
eq &= (WE == v.WE);
eq &= (DQM == v.DQM);
eq &= (ADDR == v.ADDR);
eq &= (BA == v.BA);
eq &= (DATA_OUTPUT == v.DATA_OUTPUT);
eq &= (DATA_OUT_EN == v.DATA_OUT_EN);
return eq;
}
friend void sc_trace(sc_trace_file *tf, const sdram_io_master & v, const std::string & path)
{
sc_trace(tf,v.CLK, path + "/clk");
sc_trace(tf,v.CKE, path + "/cke");
sc_trace(tf,v.CS, path + "/cs");
sc_trace(tf,v.RAS, path + "/ras");
sc_trace(tf,v.CAS, path + "/cas");
sc_trace(tf,v.WE, path + "/we");
sc_trace(tf,v.DQM, path + "/dqm");
sc_trace(tf,v.ADDR, path + "/addr");
sc_trace(tf,v.BA, path + "/ba");
sc_trace(tf,v.DATA_OUTPUT, path + "/data_output");
sc_trace(tf,v.DATA_OUT_EN, path + "/data_out_en");
}
friend ostream& operator << (ostream& os, sdram_io_master const & v)
{
os << hex << "CLK: " << v.CLK << " ";
os << hex << "CKE: " << v.CKE << " ";
os << hex << "CS: " << v.CS << " ";
os << hex << "RAS: " << v.RAS << " ";
os << hex << "CAS: " << v.CAS << " ";
os << hex << "WE: " << v.WE << " ";
os << hex << "DQM: " << v.DQM << " ";
os << hex << "ADDR: " << v.ADDR << " ";
os << hex << "BA: " << v.BA << " ";
os << hex << "DATA_OUTPUT: " << v.DATA_OUTPUT << " ";
os << hex << "DATA_OUT_EN: " << v.DATA_OUT_EN << " ";
return os;
}
friend istream& operator >> ( istream& is, sdram_io_master & val)
{
// Not implemented
return is;
}
};
#define MEMBER_COPY_SDRAM_IO_MASTER(s,d) do { \
s.CLK = d.CLK; \
s.CKE = d.CKE; \
s.CS = d.CS; \
s.RAS = d.RAS; \
s.CAS = d.CAS; \
s.WE = d.WE; \
s.DQM = d.DQM; \
s.ADDR = d.ADDR; \
s.BA = d.BA; \
s.DATA_OUTPUT = d.DATA_OUTPUT; \
s.DATA_OUT_EN = d.DATA_OUT_EN; \
} while (0)
//----------------------------------------------------------------
// Interface (slave)
//----------------------------------------------------------------
class sdram_io_slave
{
public:
// Members
sc_uint <16> DATA_INPUT;
// Construction
sdram_io_slave() { init(); }
void init(void)
{
DATA_INPUT = 0;
}
bool operator == (const sdram_io_slave & v) const
{
bool eq = true;
eq &= (DATA_INPUT == v.DATA_INPUT);
return eq;
}
friend void sc_trace(sc_trace_file *tf, const sdram_io_slave & v, const std::string & path)
{
sc_trace(tf,v.DATA_INPUT, path + "/data_input");
}
friend ostream& operator << (ostream& os, sdram_io_slave const & v)
{
os << hex << "DATA_INPUT: " << v.DATA_INPUT << " ";
return os;
}
friend istream& operator >> ( istream& is, sdram_io_slave & val)
{
// Not implemented
return is;
}
};
#define MEMBER_COPY_SDRAM_IO_SLAVE(s,d) do { \
s.DATA_INPUT = d.DATA_INPUT; \
} while (0)
#endif
|
/* Copyright 2017 Columbia University, SLD Group */
//
// tb.h - Robert Margelli
// Testbench header file.
//
#ifndef __TB__H
#define __TB__H
#include <time.h>
#include <systemc.h>
#include "cynw_flex_channels.h"
#include <esc.h>
#include "hl5_datatypes.hpp"
#include "globals.hpp"
#include "defines.hpp"
SC_MODULE(tb)
{
public:
// Declaration of clock and reset parameters
sc_in < bool > clk;
sc_in < bool > rst;
// End of simulation signal.
sc_in < bool > program_end;
// Fetch enable signal.
sc_out < bool > fetch_en;
// CPU Reset
sc_out < bool > cpu_rst;
// Entry point
sc_out < unsigned > entry_point;
// TODO: removeme
// sc_in < bool > main_start;
// sc_in < bool > main_end;
// Instruction counters
sc_in < long int > icount;
sc_in < long int > j_icount;
sc_in < long int > b_icount;
sc_in < long int > m_icount;
sc_in < long int > o_icount;
sc_uint<XLEN> *imem;
sc_uint<XLEN> *dmem;
SC_HAS_PROCESS(tb);
tb(sc_module_name name, sc_uint<XLEN> imem[ICACHE_SIZE], sc_uint<XLEN> dmem[DCACHE_SIZE])
: clk("clk")
, rst("rst")
, program_end("program_end")
, fetch_en("fetch_en")
, cpu_rst("cpu_rst")
, entry_point("entry_point")
// , main_start("main_start")
// , main_end("main_end")
, icount("icount")
, j_icount("j_icount")
, b_icount("b_icount")
, m_icount("m_icount")
, o_icount("o_icount")
, imem(imem)
, dmem(dmem)
{
SC_CTHREAD(source, clk.pos());
reset_signal_is(rst, 0);
SC_CTHREAD(sink, clk.pos());
reset_signal_is(rst, 0);
}
void source();
void sink();
double exec_start;
// double exec_main_start;
};
#endif
|
//
// Copyright 2022 Sergey Khabarov, [email protected]
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
#pragma once
#include <systemc.h>
#include "../ambalib/types_amba.h"
#include "../ambalib/types_pnp.h"
#include "../ambalib/axi_slv.h"
#include "api_core.h"
namespace debugger {
template<int ctxmax = 8,
int irqmax = 128>
SC_MODULE(plic) {
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
sc_in<mapinfo_type> i_mapinfo; // interconnect slot information
sc_out<dev_config_type> o_cfg; // Device descriptor
sc_in<axi4_slave_in_type> i_xslvi; // AXI Slave to Bridge interface
sc_out<axi4_slave_out_type> o_xslvo; // AXI Bridge to Slave interface
sc_in<sc_biguint<irqmax>> i_irq_request; // [0] must be tight to GND
sc_out<sc_uint<ctxmax>> o_ip;
void comb();
void registers();
SC_HAS_PROCESS(plic);
plic(sc_module_name name,
bool async_reset);
virtual ~plic();
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
bool async_reset_;
struct plic_context_type {
sc_uint<4> priority_th;
sc_bv<1024> ie; // interrupt enable per context
sc_bv<(4 * 1024)> ip_prio; // interrupt pending priority per context
sc_uint<16> prio_mask; // pending interrupts priorites
sc_uint<4> sel_prio; // the most available priority
sc_uint<10> irq_idx; // currently selected most prio irq
sc_uint<10> irq_prio; // currently selected prio level
};
struct plic_registers {
sc_signal<sc_bv<(4 * 1024)>> src_priority;
sc_signal<sc_bv<1024>> pending;
sc_signal<sc_uint<ctxmax>> ip;
plic_context_type ctx[ctxmax];
sc_signal<sc_uint<64>> rdata;
} v, r;
sc_signal<bool> w_req_valid;
sc_signal<sc_uint<CFG_SYSBUS_ADDR_BITS>> wb_req_addr;
sc_signal<sc_uint<8>> wb_req_size;
sc_signal<bool> w_req_write;
sc_signal<sc_uint<CFG_SYSBUS_DATA_BITS>> wb_req_wdata;
sc_signal<sc_uint<CFG_SYSBUS_DATA_BYTES>> wb_req_wstrb;
sc_signal<bool> w_req_last;
sc_signal<bool> w_req_ready;
sc_signal<bool> w_resp_valid;
sc_signal<sc_uint<CFG_SYSBUS_DATA_BITS>> wb_resp_rdata;
sc_signal<bool> wb_resp_err;
axi_slv *xslv0;
};
template<int ctxmax, int irqmax>
plic<ctxmax, irqmax>::plic(sc_module_name name,
bool async_reset)
: sc_module(name),
i_clk("i_clk"),
i_nrst("i_nrst"),
i_mapinfo("i_mapinfo"),
o_cfg("o_cfg"),
i_xslvi("i_xslvi"),
o_xslvo("o_xslvo"),
i_irq_request("i_irq_request"),
o_ip("o_ip") {
async_reset_ = async_reset;
xslv0 = 0;
xslv0 = new axi_slv("xslv0", async_reset,
VENDOR_OPTIMITECH,
OPTIMITECH_PLIC);
xslv0->i_clk(i_clk);
xslv0->i_nrst(i_nrst);
xslv0->i_mapinfo(i_mapinfo);
xslv0->o_cfg(o_cfg);
xslv0->i_xslvi(i_xslvi);
xslv0->o_xslvo(o_xslvo);
xslv0->o_req_valid(w_req_valid);
xslv0->o_req_addr(wb_req_addr);
xslv0->o_req_size(wb_req_size);
xslv0->o_req_write(w_req_write);
xslv0->o_req_wdata(wb_req_wdata);
xslv0->o_req_wstrb(wb_req_wstrb);
xslv0->o_req_last(w_req_last);
xslv0->i_req_ready(w_req_ready);
xslv0->i_resp_valid(w_resp_valid);
xslv0->i_resp_rdata(wb_resp_rdata);
xslv0->i_resp_err(wb_resp_err);
SC_METHOD(comb);
sensitive << i_nrst;
sensitive << i_mapinfo;
sensitive << i_xslvi;
sensitive << i_irq_request;
sensitive << w_req_valid;
sensitive << wb_req_addr;
sensitive << wb_req_size;
sensitive << w_req_write;
sensitive << wb_req_wdata;
sensitive << wb_req_wstrb;
sensitive << w_req_last;
sensitive << w_req_ready;
sensitive << w_resp_valid;
sensitive << wb_resp_rdata;
sensitive << wb_resp_err;
sensitive << r.src_priority;
sensitive << r.pending;
sensitive << r.ip;
sensitive << r.rdata;
SC_METHOD(registers);
sensitive << i_nrst;
sensitive << i_clk.pos();
}
template<int ctxmax, int irqmax>
plic<ctxmax, irqmax>::~plic() {
if (xslv0) {
delete xslv0;
}
}
template<int ctxmax, int irqmax>
void plic<ctxmax, irqmax>::generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd) {
std::string pn(name());
if (o_vcd) {
sc_trace(o_vcd, i_xslvi, i_xslvi.name());
sc_trace(o_vcd, o_xslvo, o_xslvo.name());
sc_trace(o_vcd, i_irq_request, i_irq_request.name());
sc_trace(o_vcd, o_ip, o_ip.name());
sc_trace(o_vcd, r.src_priority, pn + ".r_src_priority");
sc_trace(o_vcd, r.pending, pn + ".r_pending");
sc_trace(o_vcd, r.ip, pn + ".r_ip");
for (int i = 0; i < ctxmax; i++) {
char tstr[1024];
RISCV_sprintf(tstr, sizeof(tstr), "%s.r_ctx%d_priority_th", pn.c_str(), i);
sc_trace(o_vcd, r.ctx[i].priority_th, tstr);
RISCV_sprintf(tstr, sizeof(tstr), "%s.r_ctx%d_ie", pn.c_str(), i);
sc_trace(o_vcd, r.ctx[i].ie, tstr);
RISCV_sprintf(tstr, sizeof(tstr), "%s.r_ctx%d_ip_prio", pn.c_str(), i);
sc_trace(o_vcd, r.ctx[i].ip_prio, tstr);
RISCV_sprintf(tstr, sizeof(tstr), "%s.r_ctx%d_prio_mask", pn.c_str(), i);
sc_trace(o_vcd, r.ctx[i].prio_mask, tstr);
RISCV_sprintf(tstr, sizeof(tstr), "%s.r_ctx%d_sel_prio", pn.c_str(), i);
sc_trace(o_vcd, r.ctx[i].sel_prio, tstr);
RISCV_sprintf(tstr, sizeof(tstr), "%s.r_ctx%d_irq_idx", pn.c_str(), i);
sc_trace(o_vcd, r.ctx[i].irq_idx, tstr);
RISCV_sprintf(tstr, sizeof(tstr), "%s.r_ctx%d_irq_prio", pn.c_str(), i);
sc_trace(o_vcd, r.ctx[i].irq_prio, tstr);
}
sc_trace(o_vcd, r.rdata, pn + ".r_rdata");
}
if (xslv0) {
xslv0->generateVCD(i_vcd, o_vcd);
}
}
template<int ctxmax, int irqmax>
void plic<ctxmax, irqmax>::comb() {
sc_uint<CFG_SYSBUS_DATA_BITS> vrdata;
sc_uint<10> vb_irq_idx[ctxmax]; // Currently selected most prio irq
sc_uint<10> vb_irq_prio[ctxmax]; // Currently selected prio level
plic_context_type vb_ctx[ctxmax];
sc_bv<(4 * 1024)> vb_src_priority;
sc_bv<1024> vb_pending;
sc_uint<ctxmax> vb_ip;
int rctx_idx;
vrdata = 0;
for (int i = 0; i < ctxmax; i++) {
vb_irq_idx[i] = 0;
}
for (int i = 0; i < ctxmax; i++) {
vb_irq_prio[i] = 0;
}
for (int i = 0; i < ctxmax; i++) {
vb_ctx[i].priority_th = 0;
vb_ctx[i].ie = 0;
vb_ctx[i].ip_prio = 0;
vb_ctx[i].prio_mask = 0;
vb_ctx[i].sel_prio = 0;
vb_ctx[i].irq_idx = 0;
vb_ctx[i].irq_prio = 0;
}
vb_src_priority = 0;
vb_pending = 0;
vb_ip = 0;
rctx_idx = 0;
v.src_priority = r.src_priority;
v.pending = r.pending;
v.ip = r.ip;
for (int i = 0; i < ctxmax; i++) {
v.ctx[i].priority_th = r.ctx[i].priority_th;
v.ctx[i].ie = r.ctx[i].ie;
v.ctx[i].ip_prio = r.ctx[i].ip_prio;
v.ctx[i].prio_mask = r.ctx[i].prio_mask;
v.ctx[i].sel_prio = r.ctx[i].sel_prio;
v.ctx[i].irq_idx = r.ctx[i].irq_idx;
v.ctx[i].irq_prio = r.ctx[i].irq_prio;
}
v.rdata = r.rdata;
// Warning SystemC limitation workaround:
// Cannot directly write into bitfields of the signals v.* registers
// So, use the following vb_* logic variables for that and then copy them.
vb_src_priority = r.src_priority;
vb_pending = r.pending;
for (int i = 0; i < ctxmax; i++) {
vb_ctx[i].priority_th = r.ctx[i].priority_th;
vb_ctx[i].ie = r.ctx[i].ie;
vb_ctx[i].irq_idx = r.ctx[i].irq_idx;
vb_ctx[i].irq_prio = r.ctx[i].irq_prio;
}
for (int i = 1; i < irqmax; i++) {
if ((i_irq_request.read()[i] == 1) && (r.src_priority.read()((4 * i) + 4 - 1, (4 * i)).to_int() > 0)) {
vb_pending[i] = 1;
}
}
for (int n = 0; n < ctxmax; n++) {
for (int i = 0; i < irqmax; i++) {
if ((r.pending.read()[i] == 1)
&& (r.ctx[n].ie[i] == 1)
&& (r.src_priority.read()((4 * i) + 4 - 1, (4 * i)).to_int() > r.ctx[n].priority_th)) {
vb_ctx[n].ip_prio((4 * i) + 4 - 1, (4 * i)) = r.src_priority.read()((4 * i) + 4 - 1, (4 * i));
vb_ctx[n].prio_mask[r.src_priority.read()((4 * i) + 4 - 1, (4 * i)).to_int()] = 1;
}
}
}
// Select max priority in each context
for (int n = 0; n < ctxmax; n++) {
for (int i = 0; i < 16; i++) {
if (r.ctx[n].prio_mask[i] == 1) {
vb_ctx[n].sel_prio = i;
}
}
}
// Select max priority in each context
for (int n = 0; n < ctxmax; n++) {
for (int i = 0; i < irqmax; i++) {
if (r.ctx[n].sel_prio.or_reduce()
&& (r.ctx[n].ip_prio((4 * i) + 4 - 1, (4 * i)) == r.ctx[n].sel_prio)) {
// Most prio irq and prio level
vb_irq_idx[n] = i;
vb_irq_prio[n] = r.ctx[n].sel_prio;
}
}
}
for (int n = 0; n < ctxmax; n++) {
vb_ctx[n].irq_idx = vb_irq_idx[n];
vb_ctx[n].irq_prio = vb_irq_prio[n];
vb_ip[n] = vb_irq_idx[n].or_reduce();
}
// R/W registers access:
rctx_idx = wb_req_addr.read()(20, 12).to_int();
if (wb_req_addr.read()(21, 12) == 0) { // src_prioirty
// 0x000000..0x001000: Irq 0 unused
if (wb_req_addr.read()(11, 3).or_reduce() == 1) {
vrdata(3, 0) = r.src_priority.read()((8 * wb_req_addr.read()(11, 3)) + 4 - 1, (8 * wb_req_addr.read()(11, 3))).to_uint64();
if ((w_req_valid.read() == 1) && (w_req_write.read() == 1)) {
if (wb_req_wstrb.read()(3, 0).or_reduce() == 1) {
vb_src_priority((8 * wb_req_addr.read()(11, 3)) + 4 - 1, (8 * wb_req_addr.read()(11, 3))) = wb_req_wdata.read()(3, 0);
}
}
}
vrdata(35, 32) = r.src_priority.read()(((8 * wb_req_addr.read()(11, 3)) + 32) + 4 - 1, ((8 * wb_req_addr.read()(11, 3)) + 32)).to_uint64();
if ((w_req_valid.read() == 1) && (w_req_write.read() == 1)) {
if (wb_req_wstrb.read()(7, 4).or_reduce() == 1) {
vb_src_priority(((8 * wb_req_addr.read()(11, 3)) + 32) + 4 - 1, ((8 * wb_req_addr.read()(11, 3)) + 32)) = wb_req_wdata.read()(35, 32);
}
}
} else if (wb_req_addr.read()(21, 12) == 1) {
// 0x001000..0x001080
vrdata = r.pending.read()((64 * wb_req_addr.read()(6, 3)) + 64 - 1, (64 * wb_req_addr.read()(6, 3))).to_uint64();
if ((w_req_valid.read() == 1) && (w_req_write.read() == 1)) {
if (wb_req_wstrb.read()(3, 0).or_reduce() == 1) {
vb_pending((64 * wb_req_addr.read()(6, 3)) + 32 - 1, (64 * wb_req_addr.read()(6, 3))) = wb_req_wdata.read()(31, 0);
}
if (wb_req_wstrb.read()(7, 4).or_reduce() == 1) {
vb_pending(((64 * wb_req_addr.read()(6, 3)) + 32) + 32 - 1, ((64 * wb_req_addr.read()(6, 3)) + 32)) = wb_req_wdata.read()(63, 32);
}
}
} else if ((wb_req_addr.read()(21, 12) == 2)
&& (wb_req_addr.read()(11, 7) < ctxmax)) {
// First 32 context of 15867 support only
// 0x002000,0x002080,...,0x200000
vrdata = r.ctx[wb_req_addr.read()(11, 7)].ie((64 * wb_req_addr.read()(6, 3)) + 64 - 1, (64 * wb_req_addr.read()(6, 3))).to_uint64();
if ((w_req_valid.read() == 1) && (w_req_write.read() == 1)) {
if (wb_req_wstrb.read()(3, 0).or_reduce() == 1) {
vb_ctx[wb_req_addr.read()(11, 7)].ie((64 * wb_req_addr.read()(6, 3)) + 32 - 1, (64 * wb_req_addr.read()(6, 3))) = wb_req_wdata.read()(31, 0);
}
if (wb_req_wstrb.read()(7, 4).or_reduce() == 1) {
vb_ctx[wb_req_addr.read()(11, 7)].ie(((64 * wb_req_addr.read()(6, 3)) + 32) + 32 - 1, ((64 * wb_req_addr.read()(6, 3)) + 32)) = wb_req_wdata.read()(63, 32);
}
}
} else if ((wb_req_addr.read()(21, 12) >= 0x200) && (wb_req_addr.read()(20, 12) < ctxmax)) {
// 0x200000,0x201000,...,0x4000000
if (wb_req_addr.read()(11, 3) == 0) {
// masking (disabling) all interrupt with <= priority
vrdata(3, 0) = r.ctx[rctx_idx].priority_th;
vrdata(41, 32) = r.ctx[rctx_idx].irq_idx;
// claim/ complete. Reading clears pending bit
if (r.ip.read()[rctx_idx] == 1) {
vb_pending[r.ctx[rctx_idx].irq_idx] = 0;
}
if ((w_req_valid.read() == 1) && (w_req_write.read() == 1)) {
if (wb_req_wstrb.read()(3, 0).or_reduce() == 1) {
vb_ctx[rctx_idx].priority_th = wb_req_wdata.read()(3, 0);
}
if (wb_req_wstrb.read()(7, 4).or_reduce() == 1) {
// claim/ complete. Reading clears pedning bit
vb_ctx[rctx_idx].irq_idx = 0;
}
}
} else {
// reserved
}
}
v.rdata = vrdata;
v.src_priority = vb_src_priority;
v.pending = vb_pending;
v.ip = vb_ip;
for (int n = 0; n < ctxmax; n++) {
v.ctx[n].priority_th = vb_ctx[n].priority_th;
v.ctx[n].ie = vb_ctx[n].ie;
v.ctx[n].ip_prio = vb_ctx[n].ip_prio;
v.ctx[n].prio_mask = vb_ctx[n].prio_mask;
v.ctx[n].sel_prio = vb_ctx[n].sel_prio;
v.ctx[n].irq_idx = vb_ctx[n].irq_idx;
v.ctx[n].irq_prio = vb_ctx[n].irq_prio;
}
if (!async_reset_ && i_nrst.read() == 0) {
v.src_priority = 0;
v.pending = 0;
v.ip = 0;
for (int i = 0; i < ctxmax; i++) {
v.ctx[i].priority_th = 0;
v.ctx[i].ie = 0;
v.ctx[i].ip_prio = 0;
v.ctx[i].prio_mask = 0;
v.ctx[i].sel_prio = 0;
v.ctx[i].irq_idx = 0;
v.ctx[i].irq_prio = 0;
}
v.rdata = 0;
}
w_req_ready = 1;
w_resp_valid = 1;
wb_resp_rdata = r.rdata;
wb_resp_err = 0;
o_ip = r.ip;
}
template<int ctxmax, int irqmax>
void plic<ctxmax, irqmax>::registers() {
if (async_reset_ && i_nrst.read() == 0) {
r.src_priority = 0;
r.pending = 0;
r.ip = 0;
for (int i = 0; i < ctxmax; i++) {
r.ctx[i].priority_th = 0;
r.ctx[i].ie = 0;
r.ctx[i].ip_prio = 0;
r.ctx[i].prio_mask = 0;
r.ctx[i].sel_prio = 0;
r.ctx[i].irq_idx = 0;
r.ctx[i].irq_prio = 0;
}
r.rdata = 0;
} else {
r.src_priority = v.src_priority;
r.pending = v.pending;
r.ip = v.ip;
for (int i = 0; i < ctxmax; i++) {
r.ctx[i].priority_th = v.ctx[i].priority_th;
r.ctx[i].ie = v.ctx[i].ie;
r.ctx[i].ip_prio = v.ctx[i].ip_prio;
r.ctx[i].prio_mask = v.ctx[i].prio_mask;
r.ctx[i].sel_prio = v.ctx[i].sel_prio;
r.ctx[i].irq_idx = v.ctx[i].irq_idx;
r.ctx[i].irq_prio = v.ctx[i].irq_prio;
}
r.rdata = v.rdata;
}
}
} // namespace debugger
|
/**
* Author: Anubhav Tomar
*
* Robot Definition
**/
#ifndef ROBOT_H
#define ROBOT_H
#include<systemc.h>
#include<LIB.h>
// template < >
class _robotBlock : public sc_module {
public:
// Inputs
sc_in<bool> _enableFromServer , _enableFromEnv;
sc_fifo_in<int> _serverToRobot , _envToRobot;
// Outputs
sc_fifo_out<int> _robotToServer , _robotToEnv;
SC_HAS_PROCESS(_robotBlock);
_robotBlock(sc_module_name name , int _robotId) : sc_module(name) {
SC_THREAD(_robotProcess);
sensitive<<_enableFromServer.pos();
sensitive<<_enableFromEnv.pos();
_id = _robotId;
};
private:
int _id;
void _relayToServer (int type , int data) {
cout<<"/**===================================ROBOT LOG===================================**/"<<endl;
cout<<"@ "<<sc_time_stamp()<<"------Start _relayToServer--------"<<endl;
cout<<"/**===================================ROBOT LOG===================================**/"<<endl<<endl<<endl;
// wait(10 , SC_NS);
_robotToServer.write(type);
_robotToServer.write(data);
// wait(10 , SC_NS);
}
void _relayToEnv (int type , int data) {
cout<<"/**===================================ROBOT LOG===================================**/"<<endl;
cout<<"@ "<<sc_time_stamp()<<"------Start _relayToEnv--------"<<endl;
cout<<"/**===================================ROBOT LOG===================================**/"<<endl<<endl<<endl;
// wait(10 , SC_NS);
_robotToEnv.write(type);
_robotToEnv.write(data);
// wait(10 , SC_NS);
}
void _robotProcess () {
while(true) {
wait();
cout<<"/**===================================ROBOT LOG===================================**/"<<endl;
cout<<"@ "<<sc_time_stamp()<<"------Start _robotProcess--------"<<endl;
cout<<"/**===================================ROBOT LOG===================================**/"<<endl<<endl<<endl;
int _robotId;
if(_serverToRobot.nb_read(_robotId)) {
cout<<"ID "<<_robotId<<endl;
if(_robotId != _id) {
// not this robot
continue;
}
int _count;
_serverToRobot.read(_count);
_robotToEnv.write(_id);
_robotToEnv.write(_count);
while(_count--) {
int _type , _data;
_serverToRobot.read(_type);
_serverToRobot.read(_data);
_relayToEnv(_type , _data);
}
}
if(_envToRobot.nb_read(_robotId)) {
cout<<"ID "<<_robotId<<endl;
if(_robotId != _id) {
// not this robot
continue;
}
int _count;
_envToRobot.read(_count);
_robotToServer.write(_id);
_robotToServer.write(_count);
while(_count--) {
int _type , _data;
_envToRobot.read(_type);
_envToRobot.read(_data);
_relayToServer(_type , _data);
}
}
}
}
};
#endif |
#include <systemc.h>
#include "/Users/ebinouri/Documents/UNi/Master_Thesis/Enhancement/AES_systemc/utility_functions.h"
#ifndef __KEYEXPANSION_H__
#define __KEYEXPANSION_H__
using namespace sc_core;
// #ifndef SENSITIVITY(X, Y)
#define SENSITIVITY(X, Y) sensitive << X[Y]
// #endif
SC_MODULE( keyExpansion ) {
sc_in<sc_logic> key[128];
sc_out<sc_logic> w[1408];
sc_signal<sc_lv<1408>> w_lv;
sc_signal<sc_lv<128>> key_lv;
sc_lv<32> temp;
sc_lv<32> r;
sc_lv<32> rot;
sc_lv<32> x;
sc_lv<32> rconv;
sc_lv<32> new_k;
sc_lv<1408> w_temp;
SC_CTOR( keyExpansion ) {
SC_METHOD(eval);
dont_initialize();
sensitive << key_lv;
// convert w port (array of logic) to w_lv (logic_vector)
SC_THREAD(w_assignment);
sensitive << w_lv;
// convert key port (array of logic) to key_lv (logic_vector)
SC_THREAD(key_assignment);
// dont_initialize();
for(int i = 0; i < 128; i++){
SENSITIVITY(key, i);
}
}
void w_assignment(void){
while(true) {
for (int i = 0; i < 1408; i++){
w[1407 - i].write(w_lv.read()[i]);
}
wait(SC_ZERO_TIME);
wait();
}
}
void key_assignment(void){
while(true) {
sc_lv<128> key_lv_temp;
for (int i = 0; i < 128; i++){
key_lv_temp[i] = key[i].read();
}
key_lv.write(key_lv_temp.range(0, 127));
wait(SC_ZERO_TIME);
wait();
}
}
void eval(void){
const char* zeros = zero_fill(1408 - 128).c_str();
w_temp = (zeros, key_lv.read());
// std::cout << "key(): " << key_lv.read() << std::endl;
for (int i = 4; i < 4*(10 + 1); i = i + 1) {
temp = w_temp.range(1407 - (1407- (32 - 1)), 1407 - (1407));
// temp = w_temp.range((128 * (10 + 1) - 32), (128 * (10 + 1) - 32) + (32 - 1));
// std::cout << "R [" << i << "]" << std::endl;
// std::cout << "Initial temp: " << temp << std::endl;
// std::cout << "R [" << i << "]- w_temp.range(1407-32, 1407): " << w_temp.range(1407 - (1407- (32 - 1)), 1407 - (1407)) << std::endl;
if ((i % 4) == 0){
rot = rotword(temp); // A call to the function rotword() is done and the returned value is stored in rot.
x = subwordx(rot); //A call to the function subwordx() is done and the returned value is stored in x.
rconv = rconx(i/4); //A call to the function rconx() is done and the returned value is stored in rconv.
temp = x ^ rconv;
} else if (i % 4 == 4){
temp = subwordx(temp);
}
new_k = w_temp.range((1407 - (128*(10+1)-(4*32))), (1407 - ((128*(10+1)-(4*32))+(32-1)))) ^ temp;
w_temp = w_temp << 32;
// w_temp = (w_temp.range(1407 - 0, 1407 - ((128 * (10 + 1) - 32) - 1)), new_k);
w_temp = (w_temp.range(1407 - 0, 1407 - ((128 * (10 + 1) - 32) - 1)), new_k);
// std::cout << "!!!! "<< std::endl;
// std::cout << "rot: " << rot << std::endl;
// std::cout << "x: " << x << std::endl;
// std::cout << "rconv: " << rconv << std::endl;
// std::cout << "temp: " << temp << std::endl;
// std::cout << "new_k: " << new_k << std::endl;
// std::cout << "W-temp: " << w_temp << std::endl;
// std::cout << "------------------- "<< std::endl;
}
w_lv.write(w_temp);
// std::cout << "W : " << w_temp << std::endl;
}
};
#endif /* __KEYEXPANSION_H__ */
|
#ifndef __ROM_3840_32_H__
#define __ROM_3840_32_H__
#include <fstream>
#include <systemc.h>
class rom_3840x32_t : public sc_module
{
public:
sc_in<uint32_t> addr1;
sc_in<uint32_t> addr2;
sc_out<uint32_t> data1;
sc_out<uint32_t> data2;
uint32_t data[3840];
void port1() {
while(true) {
uint32_t addrw32 = addr1.read();
uint32_t addrw11 = addrw32 % 4096;
data1.write(data[addrw11]);
wait();
}
}
void port2() {
while(true) {
uint32_t addrw32 = addr2.read();
uint32_t addrw11 = addrw32 % 4096;
data2.write(data[addrw11]);
wait();
}
}
void clear_memory() {
for (int i=0; i<3840; ++i) data[i] = 0;
update.write(!update.read());
}
bool load_binary(const std::string& path)
{
clear_memory();
ifstream f(path, std::ios::binary);
if (f.is_open()) {
f.seekg(0, f.end);
int size = f.tellg();
f.seekg(0, f.beg);
auto buf = new char[size];
f.read(buf, size);
// std::vector<unsigned char> buf
// (std::istreambuf_iterator<char>(f), {});
if (size == 0) return false;
if (size % 4 != 0) return false;
auto words = (uint32_t*) buf;
for (int i=0; i<size/4; ++i) {
data[i] = words[i];
}
f.close();
delete[] buf;
update.write(!update.read());
return true;
}
else {
return false;
}
}
SC_CTOR(rom_3840x32_t)
: update("update")
{
update.write(false);
SC_THREAD(port1);
sensitive << addr1;
sensitive << update;
SC_THREAD(port2);
sensitive << addr2;
sensitive << update;
}
private:
sc_signal<bool> update;
};
#endif
|
/*****************************************************************************
Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
more contributor license agreements. See the NOTICE file distributed
with this work for additional information regarding copyright ownership.
Accellera licenses this file to you under the Apache License, Version 2.0
(the "License"); you may not use this file except in compliance with the
License. You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
implied. See the License for the specific language governing
permissions and limitations under the License.
*****************************************************************************/
/*****************************************************************************
fir.cpp --
Original Author: Rocco Jonack, Synopsys, Inc.
*****************************************************************************/
/*****************************************************************************
MODIFICATION LOG - modifiers, enter your name, affiliation, date and
changes you are making here.
Name, Affiliation: Teodor Vasilache and Dragos Dospinescu,
AMIQ Consulting s.r.l. ([email protected])
Date: 2018-Feb-20
Description of Modification: Added sampling of the covergroup created in the
"fir.h" file.
*****************************************************************************/
/*****************************************************************************
MODIFICATION LOG - modifiers, enter your name, affiliation, date and
changes you are making here.
Name, Affiliation, Date:
Description of Modification:
*****************************************************************************/
#include <systemc.h>
#include "fir.h"
void fir::entry() {
sc_int<8> sample_tmp;
sc_int<17> pro;
sc_int<19> acc;
sc_int<8> shift[16];
// reset watching
/* this would be an unrolled loop */
for (int i=0; i<=15; i++)
shift[i] = 0;
result.write(0);
output_data_ready.write(false);
wait();
// main functionality
while(1) {
output_data_ready.write(false);
do { wait(); } while ( !(input_valid == true) );
sample_tmp = sample.read();
acc = sample_tmp*coefs[0];
for(int i=14; i>=0; i--) {
/* this would be an unrolled loop */
pro = shift[i]*coefs[i+1];
acc += pro;
};
for(int i=14; i>=0; i--) {
/* this would be an unrolled loop */
shift[i+1] = shift[i];
};
shift[0] = sample_tmp;
// sample the shift value
shift_cg.sample(shift[0]);
// write output values
result.write((int)acc);
output_data_ready.write(true);
wait();
};
}
|
/********************************************************************************
* University of L'Aquila - HEPSYCODE Source Code License *
* *
* *
* (c) 2018-2019 Centre of Excellence DEWS All rights reserved *
********************************************************************************
* <one line to give the program's name and a brief idea of what it does.> *
* Copyright (C) 2022 Vittoriano Muttillo, Luigi Pomante * *
* *
* This program is free software: you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation, either version 3 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
********************************************************************************
* *
* Created on: 09/May/2023 *
* Authors: Vittoriano Muttillo, Marco Santic, Luigi Pomante *
* *
* email: [email protected] *
* [email protected] *
* [email protected] *
* *
********************************************************************************
* This code has been developed from an HEPSYCODE model used as demonstrator by *
* University of L'Aquila. *
*******************************************************************************/
#include <systemc.h>
#include "../mainsystem.h"
#include <math.h>
#define cD_02_ANN_INPUTS 2 // Number of inputs
#define cD_02_ANN_OUTPUTS 1 // Number of outputs
//-----------------------------------------------------------------------------
// Physical constants
//-----------------------------------------------------------------------------
static double cD_02_I_0 = 77.3 ; // [A] Nominal current
static double cD_02_T_0 = 298.15 ; // [K] Ambient temperature
static double cD_02_R_0 = 0.01 ; // [Ω] Data-sheet R_DS_On (Drain-Source resistance in the On State)
static double cD_02_V_0 = 47.2 ; // [V] Nominal voltage
static double cD_02_Alpha = 0.002 ; // [Ω/K] Temperature coefficient of Drain-Source resistance in the On State
static double cD_02_ThermalConstant = 0.75 ;
static double cD_02_Tau = 0.02 ; // [s] Sampling period
//-----------------------------------------------------------------------------
// Status descriptors
//-----------------------------------------------------------------------------
typedef struct cD_02_DEVICE // Descriptor of the state of the device
{
double t ; // Operating temperature
double r ; // Operating Drain-Source resistance in the On State
double i ; // Operating current
double v ; // Operating voltage
double time_Ex ;
int fault ;
} cD_02_DEVICE ;
static cD_02_DEVICE cD_02_device;
//-----------------------------------------------------------------------------
// Mnemonics to access the array that contains the sampled data
//-----------------------------------------------------------------------------
#define cD_02_SAMPLE_LEN 3 // Array of SAMPLE_LEN elements
#define cD_02_I_INDEX 0 // Current
#define cD_02_V_INDEX 1 // Voltage
#define cD_02_TIME_INDEX 2 // Time
///-----------------------------------------------------------------------------
// Forward references
//-----------------------------------------------------------------------------
static int cD_02_initDescriptors(cD_02_DEVICE device) ;
//static void getSample(int index, double sample[SAMPLE_LEN]) ;
static void cD_02_cleanData(int index, double sample[cD_02_SAMPLE_LEN]) ;
static double cD_02_extractFeatures(double tPrev, double iPrev, double iNow, double rPrev) ;
static void cD_02_normalize(int index, double x[cD_02_ANN_INPUTS]) ;
static double cD_02_degradationModel(double tNow) ;
//-----------------------------------------------------------------------------
//
//-----------------------------------------------------------------------------
int cD_02_initDescriptors(cD_02_DEVICE device)
{
// for (int i = 0; i < NUM_DEV; i++)
// {
device.t = cD_02_T_0 ; // Operating temperature = Ambient temperature
device.r = cD_02_R_0 ; // Operating R_DS_On = Data-sheet R_DS_On
// printf("Init %d \n",i);
// }
return( EXIT_SUCCESS );
}
//-----------------------------------------------------------------------------
//
//-----------------------------------------------------------------------------
void cD_02_cleanData(int index, double sample[cD_02_SAMPLE_LEN])
{
// the parameter "index" could be useful to retrieve the characteristics of the device
if ( sample[cD_02_I_INDEX] < 0 )
sample[cD_02_I_INDEX] = 0 ;
else if ( sample[cD_02_I_INDEX] > (2.0 * cD_02_I_0) )
sample[cD_02_I_INDEX] = (2.0 * cD_02_I_0) ;
// Postcondition: (0 <= sample[I_INDEX] <= 2.0*I_0)
if ( sample[cD_02_V_INDEX] < 0 )
sample[cD_02_V_INDEX] = 0 ;
else if ( sample[cD_02_V_INDEX] > (2.0 * cD_02_V_0 ) )
sample[cD_02_V_INDEX] = (2.0 * cD_02_V_0) ;
// Postcondition: (0 <= sample[V_INDEX] <= 2.0*V_0)
}
//-----------------------------------------------------------------------------
// Input:
// - tPrev = temperature at previous step
// - iPrev = current at previous step
// - iNow = current at this step
// - rPrev = resistance at the previous step
// Return:
// - The new temperature
// Very simple model:
// - one constant for dissipation and heat capacity
// - temperature considered constant during the step
//-----------------------------------------------------------------------------
double cD_02_extractFeatures(double tPrev, double iPrev, double iNow, double rPrev)
{
double t ; // Temperature
double i = 0.5*(iPrev + iNow); // Average current
//printf("cD_02_extractFeatures tPrev=%f\n",tPrev);
t = tPrev + // Previous temperature
rPrev * (i * i) * cD_02_Tau - // Heat generated: P = I·R^2
cD_02_ThermalConstant * (tPrev - cD_02_T_0) * cD_02_Tau ; // Dissipation and heat capacity
return( t );
}
//-----------------------------------------------------------------------------
// Input:
// - tNow: temperature at this step
// Return:
// - the resistance
// The model isn't realistic because the even the simpler law is exponential
//-----------------------------------------------------------------------------
double cD_02_degradationModel(double tNow)
{
double r ;
//r = R_0 + Alpha * tNow ;
r = cD_02_R_0 * ( 2 - exp(-cD_02_Alpha*tNow) );
return( r );
}
//-----------------------------------------------------------------------------
//
//-----------------------------------------------------------------------------
void cD_02_normalize(int index, double sample[cD_02_ANN_INPUTS])
{
double i ; double v ;
// Precondition: (0 <= sample[I_INDEX] <= 2*I_0) && (0 <= sample[V_INDEX] <= 2*V_0)
i = sample[cD_02_I_INDEX] <= cD_02_I_0 ? 0.0 : 1.0;
v = sample[cD_02_V_INDEX] <= cD_02_V_0 ? 0.0 : 1.0;
// Postcondition: (i in {0.0, 1.0}) and (v in {0.0, 1.0})
sample[cD_02_I_INDEX] = i ;
sample[cD_02_V_INDEX] = v ;
}
void mainsystem::cleanData_02_main()
{
// datatype for channels
sampleTimCord_cleanData_xx_payload sampleTimCord_cleanData_xx_payload_var;
cleanData_xx_ann_xx_payload cleanData_xx_ann_xx_payload_var;
//device var
uint8_t dev;
//step var
uint16_t step;
// ex_time (for extractFeatures...)
double ex_time;
//samples i and v
double sample_i;
double sample_v;
//var for samples, to re-use cleanData()
double cD_02_sample[cD_02_SAMPLE_LEN] ;
double x[cD_02_ANN_INPUTS + cD_02_ANN_OUTPUTS] ;
// NOTE: commented, should be changed param by ref...
//cD_02_initDescriptors(cD_02_device);
cD_02_device.t = cD_02_T_0 ; // Operating temperature = Ambient temperature
cD_02_device.r = cD_02_R_0 ; // Operating R_DS_On = Data-sheet R_DS_On
// ### added for time related dynamics
//static double cD_02_Tau = 0.02 ; // [s] Sampling period
double cD_02_last_sample_time = 0;
//implementation
HEPSY_S(cleanData_02_id) while(1)
{HEPSY_S(cleanData_02_id)
// content
sampleTimCord_cleanData_xx_payload_var = sampleTimCord_cleanData_02_channel->read();
dev = sampleTimCord_cleanData_xx_payload_var.dev;
step = sampleTimCord_cleanData_xx_payload_var.step;
ex_time = sampleTimCord_cleanData_xx_payload_var.ex_time;
sample_i = sampleTimCord_cleanData_xx_payload_var.sample_i;
sample_v = sampleTimCord_cleanData_xx_payload_var.sample_v;
// cout << "cleanData_02 rcv \t dev: " << dev
// <<"\t step: " << step
// <<"\t time_ex:" << ex_time
// <<"\t i:" << sample_i
// <<"\t v:" << sample_v
// << endl;
// reconstruct sample
cD_02_sample[cD_02_I_INDEX] = sample_i;
cD_02_sample[cD_02_V_INDEX] = sample_v;
cD_02_sample[cD_02_TIME_INDEX] = ex_time;
// ### C L E A N D A T A (0 <= I <= 2.0*I_0) and (0 <= V <= 2.0*V_0)
cD_02_cleanData(dev, cD_02_sample) ;
cD_02_device.time_Ex = cD_02_sample[cD_02_TIME_INDEX] ;
cD_02_device.i = cD_02_sample[cD_02_I_INDEX] ;
cD_02_device.v = cD_02_sample[cD_02_V_INDEX] ;
// ### added for time related dynamics
//static double cD_02_Tau = 0.02 ; // [s] Sampling period
cD_02_Tau = ex_time - cD_02_last_sample_time;
cD_02_last_sample_time = ex_time;
// ### F E A T U R E S E X T R A C T I O N (compute the temperature)
cD_02_device.t = cD_02_extractFeatures( cD_02_device.t, // Previous temperature
cD_02_device.i, // Previous current
cD_02_sample[cD_02_I_INDEX], // Current at this step
cD_02_device.r) ; // Previous resistance
// ### D E G R A D A T I O N M O D E L (compute R_DS_On)
cD_02_device.r = cD_02_degradationModel(cD_02_device.t) ;
// ### N O R M A L I Z E: (x[0] in {0.0, 1.0}) and (x[1] in {0.0, 1.0})
x[0] = cD_02_device.i ;
x[1] = cD_02_device.v ;
cD_02_normalize(dev, x) ;
// // ### P R E D I C T (simple XOR)
// if ( annRun(index, x) != EXIT_SUCCESS ){
//prepare out data payload
cleanData_xx_ann_xx_payload_var.dev = dev;
cleanData_xx_ann_xx_payload_var.step = step;
cleanData_xx_ann_xx_payload_var.ex_time = ex_time;
cleanData_xx_ann_xx_payload_var.device_i = cD_02_device.i;
cleanData_xx_ann_xx_payload_var.device_v = cD_02_device.v;
cleanData_xx_ann_xx_payload_var.device_t = cD_02_device.t;
cleanData_xx_ann_xx_payload_var.device_r = cD_02_device.r;
cleanData_xx_ann_xx_payload_var.x_0 = x[0];
cleanData_xx_ann_xx_payload_var.x_1 = x[1];
cleanData_xx_ann_xx_payload_var.x_2 = x[2];
cleanData_02_ann_02_channel->write(cleanData_xx_ann_xx_payload_var);
HEPSY_P(cleanData_02_id)
}
}
//END
|
/*******************************************************************************
* st7735.h -- Copyright 2019 (c) Glenn Ramalho - RFIDo Design
*******************************************************************************
* Description:
* This is a simple model for the ST7735 display controller model.
*******************************************************************************
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
#ifndef _ST7735_H
#define _ST7735_H
#include <systemc.h>
#include "gn_mixed.h"
SC_MODULE(st7735) {
sc_inout<gn_mixed> sda {"sda"};
sc_inout<gn_mixed> d0 {"d0"};
sc_inout<gn_mixed> d1 {"d1"};
sc_inout<gn_mixed> d2 {"d2"};
sc_inout<gn_mixed> d3 {"d3"};
sc_inout<gn_mixed> d4 {"d4"};
sc_inout<gn_mixed> d5 {"d5"};
sc_inout<gn_mixed> d6 {"d6"};
sc_inout<gn_mixed> d7 {"d7"};
sc_inout<gn_mixed> d8 {"d8"};
sc_inout<gn_mixed> d9 {"d9"};
sc_inout<gn_mixed> d10 {"d10"};
sc_inout<gn_mixed> d11 {"d11"};
sc_inout<gn_mixed> d12 {"d12"};
sc_inout<gn_mixed> d13 {"d13"};
sc_inout<gn_mixed> d14 {"d14"};
sc_inout<gn_mixed> d15 {"d15"};
sc_inout<gn_mixed> d16 {"d16"};
sc_inout<gn_mixed> d17 {"d17"};
sc_in<gn_mixed> wrx {"wrx"};
sc_in<gn_mixed> rdx {"rdx"};
sc_in<gn_mixed> resx {"resx"};
sc_in<gn_mixed> csx {"csx"};
sc_in<gn_mixed> scl_dcx {"scl_dcx"};
sc_out<gn_mixed> te {"te"};
sc_out<gn_mixed> osc {"osc"};
sc_in<gn_mixed> spi4w {"spi4w"};
sc_in<sc_bv<3> > im {"im"};
private:
bool readmode;
bool initialized;
int collected;
int pos;
public:
void collect();
SC_CTOR(st7735) {
initialized = false;
readmode = false;
SC_THREAD(collect);
sensitive << csx << scl_dcx << resx << wrx;
}
void start_of_simulation();
void trace(sc_trace_file *tf);
};
#endif
|
/*******************************************************************************
* btmod.h -- Copyright 2019 (c) Glenn Ramalho - RFIDo Design
*******************************************************************************
* Description:
* Implements a SystemC module for the ESP32 BT module.
*******************************************************************************
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
#ifndef _BTMOD_H
#define _BTMOD_H
#include <systemc.h>
#include "cchan.h"
#include "TestSerial.h"
#include "esp_bt.h"
class btmod : public cchan {
public:
sc_event connected_ev;
sc_event disconnected_ev;
sc_event running_ev;
protected:
esp_power_level_t power_level[ESP_BLE_PWR_TYPE_NUM];
esp_power_level_t minpower, maxpower;
public:
btmod(sc_module_name name, int tx_buffer_size, int rx_buffer_size):
cchan(name, tx_buffer_size, rx_buffer_size) {
};
void set_power(esp_ble_power_type_t _pt, esp_power_level_t _pl) {
if (_pt < ESP_BLE_PWR_TYPE_NUM) power_level[_pt] = _pl;
}
esp_power_level_t get_power(esp_ble_power_type_t _pt) {
/* As long as the PT is valid, we return the level. If the pt is
* illegal, we return anything just because we have to return something.
*/
if (_pt < ESP_BLE_PWR_TYPE_NUM) return power_level[_pt];
else return power_level[ESP_BLE_PWR_TYPE_NUM-1];
}
bool bredr_tx_pwr_set(esp_power_level_t _min, esp_power_level_t _max) {
if (_min < ESP_PWR_LVL_N12 || _min > ESP_PWR_LVL_P7) return false;
if (_max < ESP_PWR_LVL_N12 || _max > ESP_PWR_LVL_P7) return false;
if (_min > _max) return false;
minpower = _min;
maxpower = _max;
return true;
}
int bredr_tx_pwr_get(int *_min, int *_max) {
if (_min != NULL) *_min = (int)minpower;
if (_max != NULL) *_max = (int)maxpower;
return 0;
}
};
extern btmod *btptr;
extern TestSerial BTserial;
#endif
|
/*******************************************************************************
* cd4067.h -- Copyright 2019 (c) Glenn Ramalho - RFIDo Design
*******************************************************************************
* Description:
* This is a simple model for the CD4067 Analog Mux.
*******************************************************************************
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
#ifndef _CD4067_H
#define _CD4067_H
#include <systemc.h>
#include "gn_mixed.h"
SC_MODULE(cd4067) {
sc_in<bool> inh {"inh"};
sc_in<bool> a {"a"};
sc_in<bool> b {"b"};
sc_in<bool> c {"c"};
sc_in<bool> d {"d"};
sc_port<sc_signal_inout_if<gn_mixed>,16> channel;
sc_inout<gn_mixed> x {"x"};
private:
int sel;
bool debug;
public:
/* Tasks */
void process_th();
/* Functions */
void set_debug(bool _d) { debug = _d; }
bool get_debug() { return debug; }
int get_selector();
SC_CTOR(cd4067) {
sel = 0;
debug = false;
SC_THREAD(process_th);
}
void trace(sc_trace_file *tf);
};
#endif
|
// Copyright 1991-2014 Mentor Graphics Corporation
// All Rights Reserved.
// THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
// WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
// OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
#ifndef INCLUDED_STORE
#define INCLUDED_STORE
#include <systemc.h>
class store : public sc_module
{
public:
sc_in<bool> clock;
sc_in<bool> reset;
sc_in<bool> oeenable;
sc_in<bool> txda;
sc_in<sc_uint<9> > ramadrs;
sc_out<sc_uint<16> > buffer;
void storer();
SC_CTOR(store)
: clock("clock"),
reset("reset"),
oeenable("oeenable"),
txda("txda"),
ramadrs("ramadrs"),
buffer("buffer")
{
SC_METHOD(storer);
sensitive << clock.pos();
dont_initialize();
}
// Destructor does nothing
~store()
{
}
};
//
// This process initializes the buffer.
// In operation, it uses the ramadrs input to
// select the appropriate bit and set it to
// the value of txda.
//
inline void store::storer()
{
if (reset.read() == 0)
buffer.write(0);
else if (oeenable.read() == 0)
{
// Calculate address of bit in buffer that we should write.
int i = ramadrs.read().range(8, 5);
// RMW operation - merge in the txda bit.
sc_uint<16> var_buffer = buffer.read();
var_buffer[i] = txda;
buffer.write(var_buffer);
}
}
#endif
|
// ================================================================
// NVDLA Open Source Project
//
// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
// NVDLA Open Hardware License; Check "LICENSE" which comes with
// this distribution for more information.
// ================================================================
// File Name: log.h
#ifndef __LOG_H__
#define __LOG_H__
#include <string.h>
#include <systemc.h>
#if defined(__cplusplus)
// some c++ headers for csl
#include <iostream> // for ostream, cerr
#include <sstream>
#include <cstdlib> // for std::abort()
#endif
// FIXME: there're 2 strrchr, might not good for performance;
#define __FILENAME__ (strrchr(__FILE__, '/') ? (strrchr(__FILE__, '/') + 1):__FILE__)
#define MSG_BUF_SIZE 2048
#define cslDebugInternal(lvl, ...) do {\
char msg_buf[MSG_BUF_SIZE]; \
int pos = snprintf(msg_buf, MSG_BUF_SIZE, "%d:", __LINE__); \
snprintf(msg_buf + pos, MSG_BUF_SIZE - pos, __VA_ARGS__); \
SC_REPORT_INFO_VERB(__FILENAME__, msg_buf, SC_DEBUG ); \
} while(0)
#define cslDebug(args) cslDebugInternal args
#define cslInfoInternal(...) do {\
char msg_buf[MSG_BUF_SIZE]; \
int pos = snprintf(msg_buf, MSG_BUF_SIZE, "%d:", __LINE__); \
snprintf(msg_buf + pos, MSG_BUF_SIZE - pos, __VA_ARGS__); \
SC_REPORT_INFO_VERB(__FILENAME__, msg_buf, SC_FULL ); \
} while(0)
#define cslInfo(args) cslInfoInternal args
#define FAILInternal(...) do {\
char msg_buf[MSG_BUF_SIZE]; \
int pos = snprintf(msg_buf, MSG_BUF_SIZE, "%d:", __LINE__); \
snprintf(msg_buf + pos, MSG_BUF_SIZE - pos, __VA_ARGS__); \
SC_REPORT_INFO(__FILENAME__, msg_buf ); \
} while(0)
#define FAIL(args) FAILInternal args
#define Fail(...) FAILInternal(__VA_ARGS__)
#define cslAssert(expr) do {\
sc_assert(expr ); \
} while(0)
#endif
|
// ================================================================
// NVDLA Open Source Project
//
// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
// NVDLA Open Hardware License; Check "LICENSE" which comes with
// this distribution for more information.
// ================================================================
// File Name: log.h
#ifndef __LOG_H__
#define __LOG_H__
#include <string.h>
#include <systemc.h>
#if defined(__cplusplus)
// some c++ headers for csl
#include <iostream> // for ostream, cerr
#include <sstream>
#include <cstdlib> // for std::abort()
#endif
// FIXME: there're 2 strrchr, might not good for performance;
#define __FILENAME__ (strrchr(__FILE__, '/') ? (strrchr(__FILE__, '/') + 1):__FILE__)
#define MSG_BUF_SIZE 2048
#define cslDebugInternal(lvl, ...) do {\
char msg_buf[MSG_BUF_SIZE]; \
int pos = snprintf(msg_buf, MSG_BUF_SIZE, "%d:", __LINE__); \
snprintf(msg_buf + pos, MSG_BUF_SIZE - pos, __VA_ARGS__); \
SC_REPORT_INFO_VERB(__FILENAME__, msg_buf, SC_DEBUG ); \
} while(0)
#define cslDebug(args) cslDebugInternal args
#define cslInfoInternal(...) do {\
char msg_buf[MSG_BUF_SIZE]; \
int pos = snprintf(msg_buf, MSG_BUF_SIZE, "%d:", __LINE__); \
snprintf(msg_buf + pos, MSG_BUF_SIZE - pos, __VA_ARGS__); \
SC_REPORT_INFO_VERB(__FILENAME__, msg_buf, SC_FULL ); \
} while(0)
#define cslInfo(args) cslInfoInternal args
#define FAILInternal(...) do {\
char msg_buf[MSG_BUF_SIZE]; \
int pos = snprintf(msg_buf, MSG_BUF_SIZE, "%d:", __LINE__); \
snprintf(msg_buf + pos, MSG_BUF_SIZE - pos, __VA_ARGS__); \
SC_REPORT_INFO(__FILENAME__, msg_buf ); \
} while(0)
#define FAIL(args) FAILInternal args
#define Fail(...) FAILInternal(__VA_ARGS__)
#define cslAssert(expr) do {\
sc_assert(expr ); \
} while(0)
#endif
|
#include <systemc.h>
#include "testbench_vbase.h"
#include "tb_memory.h"
#include "tb_axi4_driver.h"
#include "tb_sdram_mem.h"
#include "tb_mem_test.h"
#include "sdram_axi.h"
#define MEM_BASE 0x00000000
#define MEM_SIZE (512 * 1024)
//-----------------------------------------------------------------
// Module
//-----------------------------------------------------------------
class testbench: public testbench_vbase
{
public:
tb_axi4_driver *m_driver;
tb_mem_test *m_sequencer;
sdram_axi *m_dut;
tb_sdram_mem *m_mem;
sc_signal <axi4_master> axi_m;
sc_signal <axi4_slave> axi_s;
sc_signal <sdram_io_master> sdram_io_m;
sc_signal <sdram_io_slave> sdram_io_s;
//-----------------------------------------------------------------
// process: Drive input sequence
//-----------------------------------------------------------------
void process(void)
{
wait();
m_driver->enable_delays(true);
// Allocate some memory
m_mem->add_region(MEM_BASE, MEM_SIZE);
// Allocate some memory
m_sequencer->add_region(MEM_BASE, MEM_SIZE);
m_sequencer->trace_access(true);
// Initialise to memory known value
for (int i=0;i<MEM_SIZE;i++)
{
m_sequencer->write(MEM_BASE + i, i);
m_mem->write(MEM_BASE + i, i);
}
m_sequencer->start(50000);
m_sequencer->wait_complete();
sc_stop();
}
SC_HAS_PROCESS(testbench);
testbench(sc_module_name name): testbench_vbase(name)
{
m_driver = new tb_axi4_driver("DRIVER");
m_driver->axi_out(axi_m);
m_driver->axi_in(axi_s);
m_sequencer = new tb_mem_test("SEQ", m_driver, 32);
m_sequencer->clk_in(clk);
m_sequencer->rst_in(rst);
m_dut = new sdram_axi("MEM");
m_dut->clk_in(clk);
m_dut->rst_in(rst);
m_dut->inport_in(axi_m);
m_dut->inport_out(axi_s);
m_dut->sdram_out(sdram_io_m);
m_dut->sdram_in(sdram_io_s);
m_mem = new tb_sdram_mem("TB_MEM");
m_mem->clk_in(clk);
m_mem->rst_in(rst);
m_mem->sdram_in(sdram_io_m);
m_mem->sdram_out(sdram_io_s);
verilator_trace_enable("verilator.vcd", m_dut);
}
};
|
#ifndef SDRAM_IO_H
#define SDRAM_IO_H
#include <systemc.h>
//----------------------------------------------------------------
// Interface (master)
//----------------------------------------------------------------
class sdram_io_master
{
public:
// Members
sc_uint <1> CLK;
sc_uint <1> CKE;
sc_uint <1> CS;
sc_uint <1> RAS;
sc_uint <1> CAS;
sc_uint <1> WE;
sc_uint <2> DQM;
sc_uint <13> ADDR;
sc_uint <2> BA;
sc_uint <16> DATA_OUTPUT;
sc_uint <1> DATA_OUT_EN;
// Construction
sdram_io_master() { init(); }
void init(void)
{
CLK = 0;
CKE = 0;
CS = 0;
RAS = 0;
CAS = 0;
WE = 0;
DQM = 0;
ADDR = 0;
BA = 0;
DATA_OUTPUT = 0;
DATA_OUT_EN = 0;
}
bool operator == (const sdram_io_master & v) const
{
bool eq = true;
eq &= (CLK == v.CLK);
eq &= (CKE == v.CKE);
eq &= (CS == v.CS);
eq &= (RAS == v.RAS);
eq &= (CAS == v.CAS);
eq &= (WE == v.WE);
eq &= (DQM == v.DQM);
eq &= (ADDR == v.ADDR);
eq &= (BA == v.BA);
eq &= (DATA_OUTPUT == v.DATA_OUTPUT);
eq &= (DATA_OUT_EN == v.DATA_OUT_EN);
return eq;
}
friend void sc_trace(sc_trace_file *tf, const sdram_io_master & v, const std::string & path)
{
sc_trace(tf,v.CLK, path + "/clk");
sc_trace(tf,v.CKE, path + "/cke");
sc_trace(tf,v.CS, path + "/cs");
sc_trace(tf,v.RAS, path + "/ras");
sc_trace(tf,v.CAS, path + "/cas");
sc_trace(tf,v.WE, path + "/we");
sc_trace(tf,v.DQM, path + "/dqm");
sc_trace(tf,v.ADDR, path + "/addr");
sc_trace(tf,v.BA, path + "/ba");
sc_trace(tf,v.DATA_OUTPUT, path + "/data_output");
sc_trace(tf,v.DATA_OUT_EN, path + "/data_out_en");
}
friend ostream& operator << (ostream& os, sdram_io_master const & v)
{
os << hex << "CLK: " << v.CLK << " ";
os << hex << "CKE: " << v.CKE << " ";
os << hex << "CS: " << v.CS << " ";
os << hex << "RAS: " << v.RAS << " ";
os << hex << "CAS: " << v.CAS << " ";
os << hex << "WE: " << v.WE << " ";
os << hex << "DQM: " << v.DQM << " ";
os << hex << "ADDR: " << v.ADDR << " ";
os << hex << "BA: " << v.BA << " ";
os << hex << "DATA_OUTPUT: " << v.DATA_OUTPUT << " ";
os << hex << "DATA_OUT_EN: " << v.DATA_OUT_EN << " ";
return os;
}
friend istream& operator >> ( istream& is, sdram_io_master & val)
{
// Not implemented
return is;
}
};
#define MEMBER_COPY_SDRAM_IO_MASTER(s,d) do { \
s.CLK = d.CLK; \
s.CKE = d.CKE; \
s.CS = d.CS; \
s.RAS = d.RAS; \
s.CAS = d.CAS; \
s.WE = d.WE; \
s.DQM = d.DQM; \
s.ADDR = d.ADDR; \
s.BA = d.BA; \
s.DATA_OUTPUT = d.DATA_OUTPUT; \
s.DATA_OUT_EN = d.DATA_OUT_EN; \
} while (0)
//----------------------------------------------------------------
// Interface (slave)
//----------------------------------------------------------------
class sdram_io_slave
{
public:
// Members
sc_uint <16> DATA_INPUT;
// Construction
sdram_io_slave() { init(); }
void init(void)
{
DATA_INPUT = 0;
}
bool operator == (const sdram_io_slave & v) const
{
bool eq = true;
eq &= (DATA_INPUT == v.DATA_INPUT);
return eq;
}
friend void sc_trace(sc_trace_file *tf, const sdram_io_slave & v, const std::string & path)
{
sc_trace(tf,v.DATA_INPUT, path + "/data_input");
}
friend ostream& operator << (ostream& os, sdram_io_slave const & v)
{
os << hex << "DATA_INPUT: " << v.DATA_INPUT << " ";
return os;
}
friend istream& operator >> ( istream& is, sdram_io_slave & val)
{
// Not implemented
return is;
}
};
#define MEMBER_COPY_SDRAM_IO_SLAVE(s,d) do { \
s.DATA_INPUT = d.DATA_INPUT; \
} while (0)
#endif
|
// ================================================================
// NVDLA Open Source Project
//
// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
// NVDLA Open Hardware License; Check "LICENSE" which comes with
// this distribution for more information.
// ================================================================
// File Name: NV_NVDLA_sdp.h
#ifndef _NV_NVDLA_SDP_H_
#define _NV_NVDLA_SDP_H_
#define SC_INCLUDE_DYNAMIC_PROCESSES
#include <systemc.h>
#include <tlm.h>
#include "tlm_utils/multi_passthrough_initiator_socket.h"
#include "tlm_utils/multi_passthrough_target_socket.h"
#include "scsim_common.h"
#include "nvdla_accu2pp_if_iface.h"
#include "nvdla_dma_wr_req_iface.h"
#include "nvdla_xx2csb_resp_iface.h"
#include "NV_NVDLA_sdp_base.h"
#include "sdp_reg_model.h"
#include "sdp_rdma_reg_model.h"
#include "sdp_hls_wrapper.h"
#define MEM_BUSWIDTH_IN_BIT 64
#define ATOM_CUBE_SIZE 32
#define SDP_RDMA_BUFFER_SIZE 9*256
#define SDP_CC2PP_BUFFER_SIZE 9*256
#define SDP_WDMA_BUFFER_SIZE 2*256
#define MAX_MEM_TRANSACTION_SIZE 256
#define MAX_DMA_TRANSACTION_SIZE 32*8192
#define DMA_TRANSACTION_SIZE 64
#define DATA_FORMAT_IS_INT8 0
#define DATA_FORMAT_IS_INT16 1
#define DATA_FORMAT_IS_FP16 2
#define ELEMENT_PER_GROUP_INT8 32
#define ELEMENT_PER_GROUP_INT16 16
#define ELEMENT_PER_GROUP_FP16 16
#define ELEMENT_PER_ATOM_INT8 32
#define ELEMENT_PER_ATOM_INT16 16
#define ELEMENT_PER_ATOM_FP16 16
#define WINOGRAD_HORI_ATOM_NUM 2
#define WINOGRAD_VERT_ATOM_NUM 4
#define SDP_PARALLEL_PROC_NUM 16
SCSIM_NAMESPACE_START(clib)
// clib class forward declaration
SCSIM_NAMESPACE_END()
SCSIM_NAMESPACE_START(cmod)
// Register class forward declaration
#define CC2PP_PAYLOAD_SIZE 16
typedef enum {
SDP_RDMA_INPUT,
SDP_RDMA_X1_INPUT,
SDP_RDMA_X2_INPUT,
SDP_RDMA_Y_INPUT,
SDP_RDMA_NUM,
} te_rdma_type;
class SdpConfig {
public:
uint8_t sdp_rdma_brdma_data_mode_;
uint8_t sdp_rdma_nrdma_data_mode_;
uint8_t sdp_rdma_erdma_data_mode_;
};
class ack_info {
public:
int8_t is_mc;
uint8_t group_id;
};
class NV_NVDLA_sdp:
public NV_NVDLA_sdp_base, // ports
private sdp_reg_model, // sdp data path and write dma register accessing
private sdp_rdma_reg_model // sdp rdma register accessing
{
public:
SC_HAS_PROCESS(NV_NVDLA_sdp);
NV_NVDLA_sdp( sc_module_name module_name );
~NV_NVDLA_sdp();
// Overload for pure virtual TLM target functions
// # CSB request transport implementation shall in generated code
void csb2sdp_req_b_transport (int ID, NV_MSDEC_csb2xx_16m_secure_be_lvl_t* payload, sc_time& delay);
void csb2sdp_rdma_req_b_transport (int ID, NV_MSDEC_csb2xx_16m_secure_be_lvl_t* payload, sc_time& delay);
// # CACC -> SDP
void cacc2sdp_b_transport(int ID, nvdla_accu2pp_if_t* payload, sc_time& delay);
// # MC/CV_SRAM read response
void mcif2sdp_rd_rsp_b_transport(int ID, nvdla_dma_rd_rsp_t*, sc_core::sc_time&);
void mcif2sdp_b_rd_rsp_b_transport(int ID, nvdla_dma_rd_rsp_t*, sc_core::sc_time&);
void mcif2sdp_n_rd_rsp_b_transport(int ID, nvdla_dma_rd_rsp_t*, sc_core::sc_time&);
void mcif2sdp_e_rd_rsp_b_transport(int ID, nvdla_dma_rd_rsp_t*, sc_core::sc_time&);
void cvif2sdp_rd_rsp_b_transport(int ID, nvdla_dma_rd_rsp_t*, sc_core::sc_time&);
void cvif2sdp_b_rd_rsp_b_transport(int ID, nvdla_dma_rd_rsp_t*, sc_core::sc_time&);
void cvif2sdp_n_rd_rsp_b_transport(int ID, nvdla_dma_rd_rsp_t*, sc_core::sc_time&);
void cvif2sdp_e_rd_rsp_b_transport(int ID, nvdla_dma_rd_rsp_t*, sc_core::sc_time&);
// Port has no flow: bdma2glb_done_intr
sc_vector< sc_out<bool> > sdp2glb_done_intr;
private:
sc_core::sc_fifo <SdpConfig *> *sdp_config_fifo_;
SdpConfig sdp_cfg_;
// HLS module
sdp_hls_wrapper sdp_hls_wrapper_;
// Payloads
nvdla_dma_wr_req_t *dma_wr_req_cmd_payload_;
nvdla_dma_wr_req_t *dma_wr_req_data_payload_;
nvdla_dma_rd_req_t *dma_rd_req_payload_;
nvdla_dma_rd_req_t *dma_b_rd_req_payload_;
nvdla_dma_rd_req_t *dma_n_rd_req_payload_;
nvdla_dma_rd_req_t *dma_e_rd_req_payload_;
// Variables
bool is_there_ongoing_csb2sdp_response_;
bool is_there_ongoing_csb2sdp_rdma_response_;
// Delay
sc_core::sc_time dma_delay_;
sc_core::sc_time csb_delay_;
sc_core::sc_time b_transport_delay_;
// buffers
int32_t hls_data_in_[16];
// round, proc, element
int16_t hls_x1_alu_op_[2][2][16];
int16_t hls_x1_mul_op_[2][2][16];
int16_t hls_x2_alu_op_[2][2][16];
int16_t hls_x2_mul_op_[2][2][16];
int16_t hls_y_alu_op_[2][2][16];
int16_t hls_y_mul_op_[2][2][16];
// Events
sc_event sdp_rdma_kickoff_;
sc_event sdp_kickoff_;
sc_event sdp_rdma_done_;
sc_event sdp_b_rdma_done_;
sc_event sdp_n_rdma_done_;
sc_event sdp_e_rdma_done_;
sc_event sdp_done_;
sc_event sdp_mc_ack_;
sc_event sdp_cv_ack_;
bool is_mc_ack_done_;
bool is_cv_ack_done_;
int16_t *payload_alu_;
int16_t *payload_mul_;
int payload_index_;
sc_core::sc_fifo <int16_t *> *rdma_fifo_;
sc_core::sc_fifo <int16_t *> *rdma_b_alu_fifo_;
sc_core::sc_fifo <int16_t *> *rdma_b_mul_fifo_;
sc_core::sc_fifo <int16_t *> *rdma_n_alu_fifo_;
sc_core::sc_fifo <int16_t *> *rdma_n_mul_fifo_;
sc_core::sc_fifo <int16_t *> *rdma_e_alu_fifo_;
sc_core::sc_fifo <int16_t *> *rdma_e_mul_fifo_;
sc_core::sc_fifo <int16_t *> *wdma_fifo_;
sc_core::sc_fifo <int32_t *> *cc2pp_fifo_;
sc_core::sc_fifo <ack_info *> *sdp_ack_fifo_;
uint8_t *sdp_internal_buf_[SDP_RDMA_NUM];
uint32_t sdp_buf_wr_ptr_[SDP_RDMA_NUM];
uint32_t sdp_buf_rd_ptr_[SDP_RDMA_NUM];
uint32_t sdp_buf_width_iter_[SDP_RDMA_NUM];
uint32_t rdma_atom_total_[SDP_RDMA_NUM];
uint32_t rdma_atom_recieved_[SDP_RDMA_NUM];
// Function declaration
// # Threads
void SdpRdmaConsumerThread();
void SdpConsumerThread();
// ## RDMA thread
void SdpRdmaCore( te_rdma_type eRdma );
void SdpRdmaThread();
void SdpBRdmaThread();
void SdpNRdmaThread();
void SdpERdmaThread();
void SdpIntrThread();
// ## Data path operation thread
void SdpDataOperationWG();
void SdpDataOperationBatch();
void SdpDataOperationDC();
void SdpDataOperationThread();
// ## WDMA thread
void WdmaSequenceDC();
void WdmaSequenceWG();
void WdmaSequenceBatch();
void SdpWdmaThread();
void WriteResponseThreadMc();
void WriteResponseThreadCv();
// # Functional functions
void WdmaSequenceCommon();
// ## Reset
void Reset();
// ## Hardware layer trigger function
void SdpRdmaHardwareLayerExecutionTrigger();
void SdpHardwareLayerExecutionTrigger();
// ## Operation
void SdpLoadPerChannelData(uint32_t proc_num);
void SdpLoadPerElementData(uint32_t round, uint32_t proc);
void ExtractRdmaResponsePayloadCore(te_rdma_type eRdDma, nvdla_dma_rd_rsp_t* payload);
void SdpConfigHls();
// # TLM sockets
// ## CSB target socket
// void WaitUntilRdmaFifoFreeSizeGreaterThan(uint32_t num);
void SdpSendCsbResponse(uint8_t type, uint32_t data, uint8_t error_id);
void SdpRdmaSendCsbResponse(uint8_t type, uint32_t data, uint8_t error_id);
void SendDmaReadRequest(te_rdma_type eRdDma, nvdla_dma_rd_req_t* payload, sc_time& delay);
void SendDmaWriteRequest(nvdla_dma_wr_req_t* payload, sc_time& delay, bool ack_required = false);
void SendDmaWriteRequest(uint64_t payload_addr, uint32_t payload_size, uint32_t payload_atom_num, bool ack_required = false);
// LUT functions
uint16_t read_lut();
void write_lut();
};
SCSIM_NAMESPACE_END()
extern "C" scsim::cmod::NV_NVDLA_sdp * NV_NVDLA_sdpCon(sc_module_name module_name);
#endif
|
// ================================================================
// NVDLA Open Source Project
//
// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
// NVDLA Open Hardware License; Check "LICENSE" which comes with
// this distribution for more information.
// ================================================================
// File Name: NV_NVDLA_sdp.h
#ifndef _NV_NVDLA_SDP_H_
#define _NV_NVDLA_SDP_H_
#define SC_INCLUDE_DYNAMIC_PROCESSES
#include <systemc.h>
#include <tlm.h>
#include "tlm_utils/multi_passthrough_initiator_socket.h"
#include "tlm_utils/multi_passthrough_target_socket.h"
#include "scsim_common.h"
#include "nvdla_accu2pp_if_iface.h"
#include "nvdla_dma_wr_req_iface.h"
#include "nvdla_xx2csb_resp_iface.h"
#include "NV_NVDLA_sdp_base.h"
#include "sdp_reg_model.h"
#include "sdp_rdma_reg_model.h"
#include "sdp_hls_wrapper.h"
#define MEM_BUSWIDTH_IN_BIT 64
#define ATOM_CUBE_SIZE 32
#define SDP_RDMA_BUFFER_SIZE 9*256
#define SDP_CC2PP_BUFFER_SIZE 9*256
#define SDP_WDMA_BUFFER_SIZE 2*256
#define MAX_MEM_TRANSACTION_SIZE 256
#define MAX_DMA_TRANSACTION_SIZE 32*8192
#define DMA_TRANSACTION_SIZE 64
#define DATA_FORMAT_IS_INT8 0
#define DATA_FORMAT_IS_INT16 1
#define DATA_FORMAT_IS_FP16 2
#define ELEMENT_PER_GROUP_INT8 32
#define ELEMENT_PER_GROUP_INT16 16
#define ELEMENT_PER_GROUP_FP16 16
#define ELEMENT_PER_ATOM_INT8 32
#define ELEMENT_PER_ATOM_INT16 16
#define ELEMENT_PER_ATOM_FP16 16
#define WINOGRAD_HORI_ATOM_NUM 2
#define WINOGRAD_VERT_ATOM_NUM 4
#define SDP_PARALLEL_PROC_NUM 16
SCSIM_NAMESPACE_START(clib)
// clib class forward declaration
SCSIM_NAMESPACE_END()
SCSIM_NAMESPACE_START(cmod)
// Register class forward declaration
#define CC2PP_PAYLOAD_SIZE 16
typedef enum {
SDP_RDMA_INPUT,
SDP_RDMA_X1_INPUT,
SDP_RDMA_X2_INPUT,
SDP_RDMA_Y_INPUT,
SDP_RDMA_NUM,
} te_rdma_type;
class SdpConfig {
public:
uint8_t sdp_rdma_brdma_data_mode_;
uint8_t sdp_rdma_nrdma_data_mode_;
uint8_t sdp_rdma_erdma_data_mode_;
};
class ack_info {
public:
int8_t is_mc;
uint8_t group_id;
};
class NV_NVDLA_sdp:
public NV_NVDLA_sdp_base, // ports
private sdp_reg_model, // sdp data path and write dma register accessing
private sdp_rdma_reg_model // sdp rdma register accessing
{
public:
SC_HAS_PROCESS(NV_NVDLA_sdp);
NV_NVDLA_sdp( sc_module_name module_name );
~NV_NVDLA_sdp();
// Overload for pure virtual TLM target functions
// # CSB request transport implementation shall in generated code
void csb2sdp_req_b_transport (int ID, NV_MSDEC_csb2xx_16m_secure_be_lvl_t* payload, sc_time& delay);
void csb2sdp_rdma_req_b_transport (int ID, NV_MSDEC_csb2xx_16m_secure_be_lvl_t* payload, sc_time& delay);
// # CACC -> SDP
void cacc2sdp_b_transport(int ID, nvdla_accu2pp_if_t* payload, sc_time& delay);
// # MC/CV_SRAM read response
void mcif2sdp_rd_rsp_b_transport(int ID, nvdla_dma_rd_rsp_t*, sc_core::sc_time&);
void mcif2sdp_b_rd_rsp_b_transport(int ID, nvdla_dma_rd_rsp_t*, sc_core::sc_time&);
void mcif2sdp_n_rd_rsp_b_transport(int ID, nvdla_dma_rd_rsp_t*, sc_core::sc_time&);
void mcif2sdp_e_rd_rsp_b_transport(int ID, nvdla_dma_rd_rsp_t*, sc_core::sc_time&);
void cvif2sdp_rd_rsp_b_transport(int ID, nvdla_dma_rd_rsp_t*, sc_core::sc_time&);
void cvif2sdp_b_rd_rsp_b_transport(int ID, nvdla_dma_rd_rsp_t*, sc_core::sc_time&);
void cvif2sdp_n_rd_rsp_b_transport(int ID, nvdla_dma_rd_rsp_t*, sc_core::sc_time&);
void cvif2sdp_e_rd_rsp_b_transport(int ID, nvdla_dma_rd_rsp_t*, sc_core::sc_time&);
// Port has no flow: bdma2glb_done_intr
sc_vector< sc_out<bool> > sdp2glb_done_intr;
private:
sc_core::sc_fifo <SdpConfig *> *sdp_config_fifo_;
SdpConfig sdp_cfg_;
// HLS module
sdp_hls_wrapper sdp_hls_wrapper_;
// Payloads
nvdla_dma_wr_req_t *dma_wr_req_cmd_payload_;
nvdla_dma_wr_req_t *dma_wr_req_data_payload_;
nvdla_dma_rd_req_t *dma_rd_req_payload_;
nvdla_dma_rd_req_t *dma_b_rd_req_payload_;
nvdla_dma_rd_req_t *dma_n_rd_req_payload_;
nvdla_dma_rd_req_t *dma_e_rd_req_payload_;
// Variables
bool is_there_ongoing_csb2sdp_response_;
bool is_there_ongoing_csb2sdp_rdma_response_;
// Delay
sc_core::sc_time dma_delay_;
sc_core::sc_time csb_delay_;
sc_core::sc_time b_transport_delay_;
// buffers
int32_t hls_data_in_[16];
// round, proc, element
int16_t hls_x1_alu_op_[2][2][16];
int16_t hls_x1_mul_op_[2][2][16];
int16_t hls_x2_alu_op_[2][2][16];
int16_t hls_x2_mul_op_[2][2][16];
int16_t hls_y_alu_op_[2][2][16];
int16_t hls_y_mul_op_[2][2][16];
// Events
sc_event sdp_rdma_kickoff_;
sc_event sdp_kickoff_;
sc_event sdp_rdma_done_;
sc_event sdp_b_rdma_done_;
sc_event sdp_n_rdma_done_;
sc_event sdp_e_rdma_done_;
sc_event sdp_done_;
sc_event sdp_mc_ack_;
sc_event sdp_cv_ack_;
bool is_mc_ack_done_;
bool is_cv_ack_done_;
int16_t *payload_alu_;
int16_t *payload_mul_;
int payload_index_;
sc_core::sc_fifo <int16_t *> *rdma_fifo_;
sc_core::sc_fifo <int16_t *> *rdma_b_alu_fifo_;
sc_core::sc_fifo <int16_t *> *rdma_b_mul_fifo_;
sc_core::sc_fifo <int16_t *> *rdma_n_alu_fifo_;
sc_core::sc_fifo <int16_t *> *rdma_n_mul_fifo_;
sc_core::sc_fifo <int16_t *> *rdma_e_alu_fifo_;
sc_core::sc_fifo <int16_t *> *rdma_e_mul_fifo_;
sc_core::sc_fifo <int16_t *> *wdma_fifo_;
sc_core::sc_fifo <int32_t *> *cc2pp_fifo_;
sc_core::sc_fifo <ack_info *> *sdp_ack_fifo_;
uint8_t *sdp_internal_buf_[SDP_RDMA_NUM];
uint32_t sdp_buf_wr_ptr_[SDP_RDMA_NUM];
uint32_t sdp_buf_rd_ptr_[SDP_RDMA_NUM];
uint32_t sdp_buf_width_iter_[SDP_RDMA_NUM];
uint32_t rdma_atom_total_[SDP_RDMA_NUM];
uint32_t rdma_atom_recieved_[SDP_RDMA_NUM];
// Function declaration
// # Threads
void SdpRdmaConsumerThread();
void SdpConsumerThread();
// ## RDMA thread
void SdpRdmaCore( te_rdma_type eRdma );
void SdpRdmaThread();
void SdpBRdmaThread();
void SdpNRdmaThread();
void SdpERdmaThread();
void SdpIntrThread();
// ## Data path operation thread
void SdpDataOperationWG();
void SdpDataOperationBatch();
void SdpDataOperationDC();
void SdpDataOperationThread();
// ## WDMA thread
void WdmaSequenceDC();
void WdmaSequenceWG();
void WdmaSequenceBatch();
void SdpWdmaThread();
void WriteResponseThreadMc();
void WriteResponseThreadCv();
// # Functional functions
void WdmaSequenceCommon();
// ## Reset
void Reset();
// ## Hardware layer trigger function
void SdpRdmaHardwareLayerExecutionTrigger();
void SdpHardwareLayerExecutionTrigger();
// ## Operation
void SdpLoadPerChannelData(uint32_t proc_num);
void SdpLoadPerElementData(uint32_t round, uint32_t proc);
void ExtractRdmaResponsePayloadCore(te_rdma_type eRdDma, nvdla_dma_rd_rsp_t* payload);
void SdpConfigHls();
// # TLM sockets
// ## CSB target socket
// void WaitUntilRdmaFifoFreeSizeGreaterThan(uint32_t num);
void SdpSendCsbResponse(uint8_t type, uint32_t data, uint8_t error_id);
void SdpRdmaSendCsbResponse(uint8_t type, uint32_t data, uint8_t error_id);
void SendDmaReadRequest(te_rdma_type eRdDma, nvdla_dma_rd_req_t* payload, sc_time& delay);
void SendDmaWriteRequest(nvdla_dma_wr_req_t* payload, sc_time& delay, bool ack_required = false);
void SendDmaWriteRequest(uint64_t payload_addr, uint32_t payload_size, uint32_t payload_atom_num, bool ack_required = false);
// LUT functions
uint16_t read_lut();
void write_lut();
};
SCSIM_NAMESPACE_END()
extern "C" scsim::cmod::NV_NVDLA_sdp * NV_NVDLA_sdpCon(sc_module_name module_name);
#endif
|
/*
* Created on: 21. jun. 2019
* Author: Jonathan Horsted Schougaard
*/
#ifdef HW_COSIM
//#define __GMP_WITHIN_CONFIGURE
#endif
#define DEBUG_SYSTEMC
#define SC_INCLUDE_FX
#include "hwcore/tb/pipes/tb_streamcircularlinebuffer.h"
#include <cstdlib>
#include <iostream>
#include <systemc.h>
unsigned errors = 0;
const char simulation_name[] = "streamcircularlinebuffer_tb";
void flush_io() { std::cout << "flush_io()" << std::flush; }
void flush_quick_io() { std::cout << "flush_quick_io()" << std::flush; }
int sc_main(int argc, char *argv[]) {
if (std::atexit(flush_io) != 0 || std::at_quick_exit(flush_quick_io) != 0) {
std::cout << "error setup flush at exit" << std::endl;
std::exit(1);
}
return errors ? 1 : 0;
cout << "INFO: Elaborating " << simulation_name << endl;
sc_core::sc_report_handler::set_actions("/IEEE_Std_1666/deprecated", sc_core::SC_DO_NOTHING);
sc_report_handler::set_actions(SC_ID_LOGIC_X_TO_BOOL_, SC_LOG);
sc_report_handler::set_actions(SC_ID_VECTOR_CONTAINS_LOGIC_VALUE_, SC_LOG);
// sc_report_handler::set_actions( SC_ID_OBJECT_EXISTS_, SC_LOG);
// sc_set_time_resolution(1,SC_PS);
// sc_set_default_time_unit(1,SC_NS);
// ModuleSingle modulesingle("modulesingle_i");
tb_top_streamcircularlinebuffer<sizeof(int) * 8, 3> top("tb_top_streamcircularlinebuffer");
cout << "INFO: Simulating " << simulation_name << endl;
sc_time time_out(1000, SC_US);
sc_start(time_out);
cout << "INFO: end time is: " << sc_time_stamp().to_string() << ", and max time is: " << time_out.to_string()
<< std::endl
<< std::flush;
sc_assert(sc_time_stamp() != time_out);
// assert(sc_time_stamp()!=sc_max_time());
cout << "INFO: Post-processing " << simulation_name << endl;
cout << "INFO: Simulation " << simulation_name << " " << (errors ? "FAILED" : "PASSED") << " with " << errors
<< " errors" << std::endl
<< std::flush;
#ifdef __RTL_SIMULATION__
cout << "HW cosim done" << endl;
#endif
return errors ? 1 : 0;
}
// test2 |
//
// Copyright 2022 Sergey Khabarov, [email protected]
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
#pragma once
#include <systemc.h>
#include "../ambalib/types_amba.h"
#include "../ambalib/types_pnp.h"
#include "../ambalib/apb_slv.h"
#include "api_core.h"
namespace debugger {
template<int cfg_slots = 1>
SC_MODULE(apb_pnp) {
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
sc_in<mapinfo_type> i_mapinfo; // interconnect slot information
sc_vector<sc_in<dev_config_type>> i_cfg; // Device descriptors vector
sc_out<dev_config_type> o_cfg; // PNP Device descriptor
sc_in<apb_in_type> i_apbi; // APB Slave to Bridge interface
sc_out<apb_out_type> o_apbo; // APB Bridge to Slave interface
sc_out<bool> o_irq;
void comb();
void registers();
SC_HAS_PROCESS(apb_pnp);
apb_pnp(sc_module_name name,
bool async_reset,
sc_uint<32> hwid,
int cpu_max,
int l2cache_ena,
int plic_irq_max);
virtual ~apb_pnp();
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
bool async_reset_;
sc_uint<32> hwid_;
int cpu_max_;
int l2cache_ena_;
int plic_irq_max_;
struct apb_pnp_registers {
sc_signal<sc_uint<32>> fw_id;
sc_signal<sc_uint<32>> idt_l;
sc_signal<sc_uint<32>> idt_m;
sc_signal<sc_uint<32>> malloc_addr_l;
sc_signal<sc_uint<32>> malloc_addr_m;
sc_signal<sc_uint<32>> malloc_size_l;
sc_signal<sc_uint<32>> malloc_size_m;
sc_signal<sc_uint<32>> fwdbg1;
sc_signal<sc_uint<32>> fwdbg2;
sc_signal<sc_uint<32>> fwdbg3;
sc_signal<sc_uint<32>> fwdbg4;
sc_signal<sc_uint<32>> fwdbg5;
sc_signal<sc_uint<32>> fwdbg6;
sc_signal<bool> irq;
sc_signal<bool> resp_valid;
sc_signal<sc_uint<32>> resp_rdata;
sc_signal<bool> resp_err;
} v, r;
void apb_pnp_r_reset(apb_pnp_registers &iv) {
iv.fw_id = 0;
iv.idt_l = 0;
iv.idt_m = 0;
iv.malloc_addr_l = 0;
iv.malloc_addr_m = 0;
iv.malloc_size_l = 0;
iv.malloc_size_m = 0;
iv.fwdbg1 = 0;
iv.fwdbg2 = 0;
iv.fwdbg3 = 0;
iv.fwdbg4 = 0;
iv.fwdbg5 = 0;
iv.fwdbg6 = 0;
iv.irq = 0;
iv.resp_valid = 0;
iv.resp_rdata = 0;
iv.resp_err = 0;
}
sc_signal<bool> w_req_valid;
sc_signal<sc_uint<32>> wb_req_addr;
sc_signal<bool> w_req_write;
sc_signal<sc_uint<32>> wb_req_wdata;
apb_slv *pslv0;
};
template<int cfg_slots>
apb_pnp<cfg_slots>::apb_pnp(sc_module_name name,
bool async_reset,
sc_uint<32> hwid,
int cpu_max,
int l2cache_ena,
int plic_irq_max)
: sc_module(name),
i_clk("i_clk"),
i_nrst("i_nrst"),
i_mapinfo("i_mapinfo"),
i_cfg("i_cfg", SOC_PNP_TOTAL),
o_cfg("o_cfg"),
i_apbi("i_apbi"),
o_apbo("o_apbo"),
o_irq("o_irq") {
async_reset_ = async_reset;
hwid_ = hwid;
cpu_max_ = cpu_max;
l2cache_ena_ = l2cache_ena;
plic_irq_max_ = plic_irq_max;
pslv0 = 0;
pslv0 = new apb_slv("pslv0", async_reset,
VENDOR_OPTIMITECH,
OPTIMITECH_PNP);
pslv0->i_clk(i_clk);
pslv0->i_nrst(i_nrst);
pslv0->i_mapinfo(i_mapinfo);
pslv0->o_cfg(o_cfg);
pslv0->i_apbi(i_apbi);
pslv0->o_apbo(o_apbo);
pslv0->o_req_valid(w_req_valid);
pslv0->o_req_addr(wb_req_addr);
pslv0->o_req_write(w_req_write);
pslv0->o_req_wdata(wb_req_wdata);
pslv0->i_resp_valid(r.resp_valid);
pslv0->i_resp_rdata(r.resp_rdata);
pslv0->i_resp_err(r.resp_err);
SC_METHOD(comb);
sensitive << i_nrst;
sensitive << i_mapinfo;
for (int i = 0; i < SOC_PNP_TOTAL; i++) {
sensitive << i_cfg[i];
}
sensitive << i_apbi;
sensitive << w_req_valid;
sensitive << wb_req_addr;
sensitive << w_req_write;
sensitive << wb_req_wdata;
sensitive << r.fw_id;
sensitive << r.idt_l;
sensitive << r.idt_m;
sensitive << r.malloc_addr_l;
sensitive << r.malloc_addr_m;
sensitive << r.malloc_size_l;
sensitive << r.malloc_size_m;
sensitive << r.fwdbg1;
sensitive << r.fwdbg2;
sensitive << r.fwdbg3;
sensitive << r.fwdbg4;
sensitive << r.fwdbg5;
sensitive << r.fwdbg6;
sensitive << r.irq;
sensitive << r.resp_valid;
sensitive << r.resp_rdata;
sensitive << r.resp_err;
SC_METHOD(registers);
sensitive << i_nrst;
sensitive << i_clk.pos();
}
template<int cfg_slots>
apb_pnp<cfg_slots>::~apb_pnp() {
if (pslv0) {
delete pslv0;
}
}
template<int cfg_slots>
void apb_pnp<cfg_slots>::generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd) {
std::string pn(name());
if (o_vcd) {
sc_trace(o_vcd, i_apbi, i_apbi.name());
sc_trace(o_vcd, o_apbo, o_apbo.name());
sc_trace(o_vcd, o_irq, o_irq.name());
sc_trace(o_vcd, r.fw_id, pn + ".r_fw_id");
sc_trace(o_vcd, r.idt_l, pn + ".r_idt_l");
sc_trace(o_vcd, r.idt_m, pn + ".r_idt_m");
sc_trace(o_vcd, r.malloc_addr_l, pn + ".r_malloc_addr_l");
sc_trace(o_vcd, r.malloc_addr_m, pn + ".r_malloc_addr_m");
sc_trace(o_vcd, r.malloc_size_l, pn + ".r_malloc_size_l");
sc_trace(o_vcd, r.malloc_size_m, pn + ".r_malloc_size_m");
sc_trace(o_vcd, r.fwdbg1, pn + ".r_fwdbg1");
sc_trace(o_vcd, r.fwdbg2, pn + ".r_fwdbg2");
sc_trace(o_vcd, r.fwdbg3, pn + ".r_fwdbg3");
sc_trace(o_vcd, r.fwdbg4, pn + ".r_fwdbg4");
sc_trace(o_vcd, r.fwdbg5, pn + ".r_fwdbg5");
sc_trace(o_vcd, r.fwdbg6, pn + ".r_fwdbg6");
sc_trace(o_vcd, r.irq, pn + ".r_irq");
sc_trace(o_vcd, r.resp_valid, pn + ".r_resp_valid");
sc_trace(o_vcd, r.resp_rdata, pn + ".r_resp_rdata");
sc_trace(o_vcd, r.resp_err, pn + ".r_resp_err");
}
if (pslv0) {
pslv0->generateVCD(i_vcd, o_vcd);
}
}
template<int cfg_slots>
void apb_pnp<cfg_slots>::comb() {
sc_uint<32> cfgmap[(8 * cfg_slots)];
sc_uint<32> vrdata;
for (int i = 0; i < (8 * cfg_slots); i++) {
cfgmap[i] = 0;
}
vrdata = 0;
v = r;
v.irq = 0;
for (int i = 0; i < cfg_slots; i++) {
cfgmap[(8 * i)] = (0, i_cfg[i].read().descrtype, i_cfg[i].read().descrsize);
cfgmap[((8 * i) + 1)] = (i_cfg[i].read().vid, i_cfg[i].read().did);
cfgmap[((8 * i) + 4)] = i_cfg[i].read().addr_start(31, 0);
cfgmap[((8 * i) + 5)] = i_cfg[i].read().addr_start(63, 32);
cfgmap[((8 * i) + 6)] = i_cfg[i].read().addr_end(31, 0);
cfgmap[((8 * i) + 7)] = i_cfg[i].read().addr_end(63, 32);
}
if (wb_req_addr.read()(11, 2) == 0) {
vrdata = hwid_;
if ((w_req_valid.read() & w_req_write.read()) == 1) {
v.irq = 1;
}
} else if (wb_req_addr.read()(11, 2) == 1) {
vrdata = r.fw_id;
if ((w_req_valid.read() & w_req_write.read()) == 1) {
v.fw_id = wb_req_wdata;
}
} else if (wb_req_addr.read()(11, 2) == 2) {
vrdata(31, 28) = (cpu_max_ >> 0);
vrdata[24] = l2cache_ena_;
vrdata(15, 8) = (cfg_slots >> 0);
vrdata(7, 0) = (plic_irq_max_ >> 0);
} else if (wb_req_addr.read()(11, 2) == 3) {
vrdata = 0;
} else if (wb_req_addr.read()(11, 2) == 4) {
vrdata = r.idt_l;
if ((w_req_valid.read() & w_req_write.read()) == 1) {
v.idt_l = wb_req_wdata;
}
} else if (wb_req_addr.read()(11, 2) == 5) {
vrdata = r.idt_m;
if ((w_req_valid.read() & w_req_write.read()) == 1) {
v.idt_m = wb_req_wdata;
}
} else if (wb_req_addr.read()(11, 2) == 6) {
vrdata = r.malloc_addr_l;
if ((w_req_valid.read() & w_req_write.read()) == 1) {
v.malloc_addr_l = wb_req_wdata;
}
} else if (wb_req_addr.read()(11, 2) == 7) {
vrdata = r.malloc_addr_m;
if ((w_req_valid.read() & w_req_write.read()) == 1) {
v.malloc_addr_m = wb_req_wdata;
}
} else if (wb_req_addr.read()(11, 2) == 8) {
vrdata = r.malloc_size_l;
if ((w_req_valid.read() & w_req_write.read()) == 1) {
v.malloc_size_l = wb_req_wdata;
}
} else if (wb_req_addr.read()(11, 2) == 9) {
vrdata = r.malloc_size_m;
if ((w_req_valid.read() & w_req_write.read()) == 1) {
v.malloc_size_m = wb_req_wdata;
}
} else if (wb_req_addr.read()(11, 2) == 10) {
vrdata = r.fwdbg1;
if ((w_req_valid.read() & w_req_write.read()) == 1) {
v.fwdbg1 = wb_req_wdata;
}
} else if (wb_req_addr.read()(11, 2) == 11) {
vrdata = r.fwdbg2;
if ((w_req_valid.read() & w_req_write.read()) == 1) {
v.fwdbg2 = wb_req_wdata;
}
} else if (wb_req_addr.read()(11, 2) == 12) {
vrdata = r.fwdbg3;
if ((w_req_valid.read() & w_req_write.read()) == 1) {
v.fwdbg3 = wb_req_wdata;
}
} else if (wb_req_addr.read()(11, 2) == 13) {
vrdata = r.fwdbg4;
if ((w_req_valid.read() & w_req_write.read()) == 1) {
v.fwdbg4 = wb_req_wdata;
}
} else if (wb_req_addr.read()(11, 2) == 14) {
vrdata = r.fwdbg5;
if ((w_req_valid.read() & w_req_write.read()) == 1) {
v.fwdbg5 = wb_req_wdata;
}
} else if (wb_req_addr.read()(11, 2) == 15) {
vrdata = r.fwdbg6;
if ((w_req_valid.read() & w_req_write.read()) == 1) {
v.fwdbg6 = wb_req_wdata;
}
} else if ((wb_req_addr.read()(11, 2) >= 16)
&& (wb_req_addr.read()(11, 2) < (16 + (8 * cfg_slots)))) {
vrdata = cfgmap[(wb_req_addr.read()(11, 2).to_int() - 16)];
}
if (!async_reset_ && i_nrst.read() == 0) {
apb_pnp_r_reset(v);
}
v.resp_valid = w_req_valid;
v.resp_rdata = vrdata;
v.resp_err = 0;
o_irq = r.irq;
}
template<int cfg_slots>
void apb_pnp<cfg_slots>::registers() {
if (async_reset_ && i_nrst.read() == 0) {
apb_pnp_r_reset(r);
} else {
r = v;
}
}
} // namespace debugger
|
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION &
* AFFILIATES. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
// This is a stub needed for the generated interconnect, so that downstream flow
// and simulation knows where to look for it.
#ifndef GROUT_0_H
#define GROUT_0_H
#include <systemc.h>
#include <nvhls_connections.h>
#include <nvhls_packet.h>
#include <interconnect/Interconnect.hpp>
#include "interconnect_config.hpp"
#if defined(INTERCONNECT_GEN)
#include ic_header(INTERCONNECT_GEN)
#endif // if defined(INTERCONNECT_GEN)
#endif
|
//
// Copyright 2022 Sergey Khabarov, [email protected]
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
#pragma once
#include <systemc.h>
#include "../river_cfg.h"
namespace debugger {
SC_MODULE(RegIntBank) {
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
sc_in<sc_uint<6>> i_radr1; // Port 1 read address
sc_out<sc_uint<RISCV_ARCH>> o_rdata1; // Port 1 read value
sc_out<sc_uint<CFG_REG_TAG_WIDTH>> o_rtag1; // Port 1 read tag value
sc_in<sc_uint<6>> i_radr2; // Port 2 read address
sc_out<sc_uint<RISCV_ARCH>> o_rdata2; // Port 2 read value
sc_out<sc_uint<CFG_REG_TAG_WIDTH>> o_rtag2; // Port 2 read tag value
sc_in<sc_uint<6>> i_waddr; // Writing value
sc_in<bool> i_wena; // Writing is enabled
sc_in<sc_uint<CFG_REG_TAG_WIDTH>> i_wtag; // Writing register tag
sc_in<sc_uint<RISCV_ARCH>> i_wdata; // Writing value
sc_in<bool> i_inorder; // Writing only if tag sequenced
sc_out<bool> o_ignored; // Sequenced writing is ignored because it was overwritten by executor (need for tracer)
sc_in<sc_uint<6>> i_dport_addr; // Debug port address
sc_in<bool> i_dport_ena; // Debug port is enabled
sc_in<bool> i_dport_write; // Debug port write is enabled
sc_in<sc_uint<RISCV_ARCH>> i_dport_wdata; // Debug port write value
sc_out<sc_uint<RISCV_ARCH>> o_dport_rdata; // Debug port read value
sc_out<sc_uint<RISCV_ARCH>> o_ra; // Return address for branch predictor
sc_out<sc_uint<RISCV_ARCH>> o_sp; // Stack Pointer for border control
sc_out<sc_uint<RISCV_ARCH>> o_gp;
sc_out<sc_uint<RISCV_ARCH>> o_tp;
sc_out<sc_uint<RISCV_ARCH>> o_t0;
sc_out<sc_uint<RISCV_ARCH>> o_t1;
sc_out<sc_uint<RISCV_ARCH>> o_t2;
sc_out<sc_uint<RISCV_ARCH>> o_fp;
sc_out<sc_uint<RISCV_ARCH>> o_s1;
sc_out<sc_uint<RISCV_ARCH>> o_a0;
sc_out<sc_uint<RISCV_ARCH>> o_a1;
sc_out<sc_uint<RISCV_ARCH>> o_a2;
sc_out<sc_uint<RISCV_ARCH>> o_a3;
sc_out<sc_uint<RISCV_ARCH>> o_a4;
sc_out<sc_uint<RISCV_ARCH>> o_a5;
sc_out<sc_uint<RISCV_ARCH>> o_a6;
sc_out<sc_uint<RISCV_ARCH>> o_a7;
sc_out<sc_uint<RISCV_ARCH>> o_s2;
sc_out<sc_uint<RISCV_ARCH>> o_s3;
sc_out<sc_uint<RISCV_ARCH>> o_s4;
sc_out<sc_uint<RISCV_ARCH>> o_s5;
sc_out<sc_uint<RISCV_ARCH>> o_s6;
sc_out<sc_uint<RISCV_ARCH>> o_s7;
sc_out<sc_uint<RISCV_ARCH>> o_s8;
sc_out<sc_uint<RISCV_ARCH>> o_s9;
sc_out<sc_uint<RISCV_ARCH>> o_s10;
sc_out<sc_uint<RISCV_ARCH>> o_s11;
sc_out<sc_uint<RISCV_ARCH>> o_t3;
sc_out<sc_uint<RISCV_ARCH>> o_t4;
sc_out<sc_uint<RISCV_ARCH>> o_t5;
sc_out<sc_uint<RISCV_ARCH>> o_t6;
void comb();
void registers();
SC_HAS_PROCESS(RegIntBank);
RegIntBank(sc_module_name name,
bool async_reset);
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
bool async_reset_;
struct RegValueType {
sc_signal<sc_uint<RISCV_ARCH>> val;
sc_signal<sc_uint<CFG_REG_TAG_WIDTH>> tag;
};
struct RegIntBank_registers {
RegValueType arr[REGS_TOTAL];
} v, r;
};
} // namespace debugger
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//
//------------------------------------------------------------//
// Copyright 2009-2012 Mentor Graphics Corporation //
// All Rights Reserved Worldwid //
// //
// Licensed under the Apache License, Version 2.0 (the //
// "License"); you may not use this file except in //
// compliance with the License. You may obtain a copy of //
// the License at //
// //
// http://www.apache.org/licenses/LICENSE-2.0 //
// //
// Unless required by applicable law or agreed to in //
// writing, software distributed under the License is //
// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR //
// CONDITIONS OF ANY KIND, either express or implied. See //
// the License for the specific language governing //
// permissions and limitations under the License. //
//------------------------------------------------------------//
#ifndef PACKET_H
#define PACKET_H
#include <vector>
using std::vector;
#include <systemc.h>
#include <tlm.h>
using namespace sc_core;
class packet {
public:
short cmd;
int addr;
vector<char> data;
};
//------------------------------------------------------------------------------
// Begin UVMC-specific code
#include "uvmc.h"
using namespace uvmc;
UVMC_UTILS_3 (packet,cmd,addr,data)
#endif // PACKET_H
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/*
* Created on: 21. jun. 2019
* Author: Jonathan Horsted Schougaard
*/
#pragma once
#define SC_INCLUDE_FX
#include "hwcore/hf/helperlib.h"
#include "hwcore/hw/singleportram.h"
#include "hwcore/pipes/data_types.h"
#include <systemc.h>
template <int W = 16, bool stream_while_write = false, int L = (((18 * 1024) / W) * 4)> SC_MODULE(_sc_stream_buffer) {
typedef typename hwcore::pipes::SC_DATA_STREAM_T_trait<1 * W>::interface_T interface_T;
enum ctrls { newset = 0, reapeat = 1 };
SC_MODULE_CLK_RESET_SIGNAL;
sc_fifo_in<interface_T> din;
sc_fifo_in<sc_uint<16> > ctrls_in;
sc_fifo_in<sc_uint<16> > ctrls_replay;
sc_fifo_out<interface_T> dout;
inline void trace(sc_trace_file * trace) {
SC_TRACE_ADD(clk);
SC_TRACE_ADD(reset);
// SC_TRACE_ADD(din);
// SC_TRACE_ADD(ctrls_in);
// SC_TRACE_ADD(dout);
}
SC_CTOR_TEMPLATE(_sc_stream_buffer) {
//#//pragma HLS function_instantiate variable=pW,pstream_while_write,pL
// dummy_rtl_generator(W+stream_while_write+L);
//#//pragma HLS function_instantiate variable=W_value,stream_while_write_value,L_value
SC_CTHREAD(thread_sc_stream_buffer, clk.pos());
reset_signal_is(reset, true);
}
void thread_sc_stream_buffer() {
/// pragma HLS function_instantiate variable=SC_CURRENT_USER_MODULE
// dummy_rtl_generator(W+stream_while_write+L);
//#pragma HLS function_instantiate variable=W_value,stream_while_write_value,L_value
//#//pragma HLS function_instantiate variable=W,stream_while_write,L
//#/pragma HLS function_instantiate variable=W_value,stream_while_write_value,L_value
HLS_DEBUG(1, 1, 0, "init thread");
hwcore::hw::singleport_ram<L, (W) + ((W) / 8) + 1> buf;
unsigned high_addr = 0;
while (true) {
interface_T tmp_in;
interface_T tmp_out;
int ctrls_tmp = ctrls_in.read();
if (ctrls_tmp == 0) {
HLS_DEBUG(1, 1, 0, "reading -- start");
high_addr = 0;
do {
#pragma HLS pipeline II = 1
tmp_in = din.read();
HLS_DEBUG(1, 1, 5, "reading -- got data: %s @ address: %d tlast? %s",
tmp_in.data.to_string().c_str(), high_addr, (tmp_in.tlast ? "true" : "false"));
if (stream_while_write)
dout.write(tmp_in); // if(stream_while_write)
if (!tmp_in.EOP()) {
buf.exec(hwcore::hf::bv_merge<1, (W / 8) + W>(
tmp_in.tlast, hwcore::hf::bv_merge<W / 8, W>(tmp_in.tkeep, tmp_in.data)),
high_addr, true);
high_addr++;
}
} while (!tmp_in.EOP());
/*if (stream_while_write)
{
HLS_DEBUG(1, 1, 0, "sending EOP");
tmp_in.setEOP();
dout.write(tmp_in);
}*/
buf.flush(high_addr - 1);
HLS_DEBUG(1, 1, 0, "reading -- done");
} else {
int ctrls_replay_tmp = ctrls_replay.read();
for (int re = 0; re < ctrls_tmp; re++) {
HLS_DEBUG(1, 1, 0, "writing -- start");
int i = 0;
int re_w = ctrls_replay_tmp;
int start = 0;
while (i < high_addr) {
#pragma HLS pipeline II = 1
sc_bv<W + (W / 8) + 1> tmp = buf.exec_read(0, i);
tmp_out.data = tmp(W - 1, 0);
tmp_out.tkeep = tmp((W + (W / 8)) - 1, W);
tmp_out.tlast = tmp.get_bit(W + (W / 8));
HLS_DEBUG(1, 1, 5, "writing -- sending data: %s @ address: %d / %d tlast? %s",
tmp_out.data.to_string().c_str(), i, high_addr - 1,
(tmp_out.tlast ? "true" : "false"));
// tmp_out.tfinal = (i == high_addr-1 ? 1 : 0);
dout.write(tmp_out);
if (tmp_out.tlast == 1) {
if (re_w != 0) {
i = start;
re_w--;
} else {
i++;
start = i;
re_w = ctrls_replay_tmp;
}
} else {
i++;
}
}
#if 0
for (int re = 0; re < ctrls_tmp; re++) {
HLS_DEBUG(1, 1, 0, "writing -- start");
for (int i = 0; i < high_addr; i++) {
#pragma HLS pipeline II = 1
sc_bv<W + (W / 8) + 1> tmp = buf.exec(0, i, false);
tmp_out.data = tmp(W - 1, 0);
tmp_out.tkeep = tmp((W + (W / 8)) - 1, W);
tmp_out.tlast = tmp.get_bit(W + (W / 8));
HLS_DEBUG(1, 1, 5, "writing -- sending data: %s @ address: %d / %d tlast? %s",
tmp_out.data.to_string().c_str(), i, high_addr - 1,
(tmp_out.tlast ? "true" : "false"));
// tmp_out.tfinal = (i == high_addr-1 ? 1 : 0);
dout.write(tmp_out);
}
/*HLS_DEBUG(1, 1, 0, "sending EOP");
tmp_out.setEOP();
dout.write(tmp_out);*/
HLS_DEBUG(1, 1, 0, "writing -- done");
#endif
}
}
}
}
};
template <int W = 16, int L = (((18 * 1024) / W) * 4)> //, bool stream_while_write = false>
SC_MODULE(_sc_stream_buffer_not_stream_while_write) {
typedef typename hwcore::pipes::SC_DATA_STREAM_T_trait<1 * W>::interface_T interface_T;
enum ctrls { newset = 0, reapeat = 1 };
SC_MODULE_CLK_RESET_SIGNAL;
sc_fifo_in<interface_T> din;
sc_fifo_in<sc_uint<31> > ctrls_in;
sc_fifo_out<interface_T> dout;
sc_out_opt<int> count_in;
sc_out_opt<int> count_out;
sc_out_opt<int> state;
inline void trace(sc_trace_file * trace) {
SC_TRACE_ADD(clk);
SC_TRACE_ADD(reset);
// SC_TRACE_ADD(din);
// SC_TRACE_ADD(ctrls_in);
// SC_TRACE_ADD(dout);
}
SC_CTOR_TEMPLATE(_sc_stream_buffer_not_stream_while_write) {
SC_CTHREAD(thread_sc_stream_buffer_not_stream_while_write, clk.pos());
HLS_DEBUG_EXEC(set_stack_size(100 * 1024 * 1024));
reset_signal_is(reset, true);
}
void thread_sc_stream_buffer_not_stream_while_write() {
HLS_DEBUG(1, 1, 0, "init thread");
// hwcore::hw::singleport_ram<L, (W) + ((W) / 8) + 1> buf;
sc_bv<W + (W / 8) + 1> buf[L];
hls_array_partition(buf, block factor = 1);
sc_uint<hwcore::hf::log2_ceil<L>::val> high_addr = 0;
sc_uint<hwcore::hf::log2_ceil<L>::val> cur_addr = 0;
while (true) {
hls_loop();
interface_T tmp_in, tmp_in_pre;
interface_T tmp_out;
sc_uint<31> ctrls_in_raw = ctrls_in.read();
sc_uint<20> ctrls_tmp = ctrls_in_raw(19, 0);
sc_uint<10> last_interval = ctrls_in_raw(29, 20);
// bool stream_while_write = ctrls_in_raw[29] == 1;
bool overwrite_last = (last_interval != 0);
bool forward = ctrls_in_raw[30] == 1;
if (forward) {
tmp_in_pre = din.read();
if (!tmp_in_pre.EOP()) {
do {
hls_pipeline(1);
tmp_in = din.read();
if (tmp_in.EOP()) {
tmp_in_pre.tlast = 1;
} else {
tmp_in_pre.tlast = 0;
}
dout.write(tmp_in_pre);
tmp_in_pre = tmp_in;
} while (!tmp_in.EOP());
}
tmp_out.setEOP();
dout.write(tmp_out);
} else if (ctrls_tmp == 0) {
HLS_DEBUG(1, 1, 0, "reading -- start");
high_addr = 0;
cur_addr = 0;
sc_uint<14> last_counter = 0;
bool new_data = false;
do {
hls_pipeline_raw(2);
wait();
if (cur_addr < high_addr) { // stream_while_write &&
sc_bv<W + (W / 8) + 1> tmp = buf[cur_addr];
tmp_out.data = tmp(W - 1, 0);
tmp_out.tkeep = tmp((W + (W / 8)) - 1, W);
tmp_out.tlast = tmp.get_bit(W + (W / 8));
if (dout.nb_write(tmp_out))
cur_addr++;
}
new_data = din.nb_read(tmp_in);
if (new_data) {
HLS_DEBUG(5, 1, 5, "reading -- got data: %s @ address: %d tlast? %s",
tmp_in.data.to_string().c_str(), high_addr.to_int(),
(tmp_in.tlast ? "true" : "false"));
if (!tmp_in.EOP()) {
sc_bv<1> tlast;
if (overwrite_last) {
tlast = (last_counter == last_interval - 1);
} else {
tlast = tmp_in.tlast;
}
buf[high_addr] = hwcore::hf::bv_merge<1, (W / 8) + W>(
tlast, hwcore::hf::bv_merge<W / 8, W>(tmp_in.tkeep, tmp_in.data));
high_addr++;
if (last_counter == last_interval - 1) {
last_counter = 0;
} else {
last_counter++;
}
}
}
} while (!(new_data && tmp_in.EOP()));
HLS_DEBUG(1, 1, 0, "reading -- done");
} else {
// int ctrls_replay_tmp = ctrls_replay.read();
sc_uint<28> replay = ctrls_tmp;
for (sc_uint<28> re = 0; re < replay; re++) {
hls_loop();
HLS_DEBUG(1, 1, 0, "writing -- start");
for (sc_uint<hwcore::hf::log2_ceil<L + 1>::val> i = cur_addr; i < high_addr; i++) {
hls_pipeline(1);
sc_bv<W + (W / 8) + 1> tmp = buf[i];
tmp_out.data = tmp(W - 1, 0);
tmp_out.tkeep = tmp((W + (W / 8)) - 1, W);
tmp_out.tlast = tmp.get_bit(W + (W / 8));
HLS_DEBUG(5, 1, 5, "writing -- sending data: %s @ address: %d / %d tlast? %s",
tmp_out.data.to_string().c_str(), i.to_int(), high_addr.to_int() - 1,
(tmp_out.tlast ? "true" : "false"));
// tmp_out.tfinal = (i == high_addr-1 ? 1 : 0);
dout.write(tmp_out);
}
cur_addr = 0;
}
tmp_out.setEOP();
dout.write(tmp_out);
HLS_DEBUG(1, 1, 0, "writing -- done and sending EOP");
}
}
}
};
namespace hwcore {
namespace pipes {
template <int W = 16, bool stream_while_write = false, int L = (((18 * 1024) / W) * 4)>
using sc_stream_buffer = ::_sc_stream_buffer<W, stream_while_write, L>;
#warning "replace with: not stream while write version"
template <int W = 16, int L = (((18 * 1024) / W) * 4)> //, bool stream_while_write = false>
using sc_stream_buffer_not_stream_while_write =
::_sc_stream_buffer_not_stream_while_write<W, L>; //, stream_while_write>;
} // namespace pipes
} // namespace hwcore
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#ifndef RGB2GRAY_TLM_HPP
#define RGB2GRAY_TLM_HPP
#include <systemc.h>
using namespace sc_core;
using namespace sc_dt;
using namespace std;
#include <tlm.h>
#include <tlm_utils/simple_initiator_socket.h>
#include <tlm_utils/simple_target_socket.h>
#include <tlm_utils/peq_with_cb_and_phase.h>
#include "rgb2gray_pv_model.hpp"
#include "../src/img_target.cpp"
//Extended Unification TLM
struct rgb2gray_tlm : public Rgb2Gray, public img_target
{
rgb2gray_tlm(sc_module_name name) : Rgb2Gray((std::string(name) + "_HW_block").c_str()), img_target((std::string(name) + "_target").c_str()) {
#ifdef DISABLE_RGB_DEBUG
this->use_prints = false;
#endif //DISABLE_RGB_DEBUG
checkprintenableimgtar(use_prints);
}
//Override do_when_transaction functions
virtual void do_when_read_transaction(unsigned char*& data, unsigned int data_length, sc_dt::uint64 address);
virtual void do_when_write_transaction(unsigned char*& data, unsigned int data_length, sc_dt::uint64 address);
};
#endif // RGB2GRAY_TLM_HPP
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#ifndef ETHERNET_DECODER_H
#define ETHERNET_DECODER_H
#include <systemc-ams.h>
#include <map>
#include <systemc.h>
#include <deque>
SCA_TDF_MODULE(ethernetDecoder)
{
public:
sca_tdf::sca_in<double> mlt3_in; // MLT-3 input signal
sca_tdf::sca_out<sc_dt::sc_bv<4>> data_out; // 4-bit output
std::map<std::string, std::string> decoding_map;
void set_attributes();
void initialize();
virtual void processing();
ethernetDecoder(sc_core::sc_module_name name, sca_core::sca_time sample_time) : sca_tdf::sca_module(name),
mlt3_in("mlt3_in"), data_out("data_out"), previous_level(0), bit_count(0), sample_count(0), found_sequence(false),
received_first_eight_decodes(false), data_length(0), decode_count(0)
{
this->sample_time = sample_time;
}
#ifndef USING_TLM_TB_EN
private:
#endif // USING_TLM_TB_EN
int previous_level;
int current_level;
int bit_count;
int sample_count;
std::deque<char> bit_sequence;
bool found_sequence;
const std::string target_sequence = "10110";
const std::string end_sequence = "10111";
bool check_sequence(const std::deque<char>& sequence);
// New members
bool received_first_eight_decodes;
int data_length;
sc_dt::sc_bv<4> first_eight_decodes[8];
int decode_count;
sca_core::sca_time sample_time;
};
#endif // ETHERNET_DECODER_H
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/****************************************************************************
*
* Copyright (c) 2017, Cadence Design Systems. All Rights Reserved.
*
* This file contains confidential information that may not be
* distributed under any circumstances without the written permision
* of Cadence Design Systems.
*
****************************************************************************/
#ifndef _ADD_ONE_SC_WRAP_INCLUDED_
#define _ADD_ONE_SC_WRAP_INCLUDED_
#include <systemc.h>
struct add_one;
#include "cynw_p2p.h"
#include "hls_enums.h"
// Declaration of wrapper with BEH level ports
SC_MODULE(add_one_wrapper)
{
public:
sc_in< bool > clk;
sc_in< bool > rst;
cynw::cynw_p2p_base_in <sc_dt::sc_int <(int)32 >, HLS::hls_enum <(int)1 > > add_one_x;
cynw::cynw_p2p_base_out <sc_dt::sc_int <(int)32 >, HLS::hls_enum <(int)1 > > add_one_return;
// These signals are used to connect structured ports or ports that need
// type conversion to the RTL ports.
// create the netlist
void InitInstances( sc_int< 32 > _A[10]);
void InitThreads();
// delete the netlist
void DeleteInstances();
// The following threads are used to connect structured ports to the actual
// RTL ports.
SC_HAS_PROCESS(add_one_wrapper);
add_one_wrapper( sc_core::sc_module_name name, sc_int< 32 > _A[10] )
: sc_module(name)
,clk("clk")
,rst("rst")
,add_one_x("add_one_x")
,add_one_return("add_one_return")
,add_one0(0)
{
InitInstances( _A);
InitThreads();
}
// destructor
~add_one_wrapper()
{
DeleteInstances();
}
add_one* add_one0;
};
#endif /* _ADD_ONE_SC_WRAP_INCLUDED_ */
|
/* -*- sysc -*-*/
/*
#- (c) Copyright 2011-2017 Xilinx, Inc. All rights reserved.
#-
#- This file contains confidential and proprietary information
#- of Xilinx, Inc. and is protected under U.S. and
#- international copyright and other intellectual property
#- laws.
#-
#- DISCLAIMER
#- This disclaimer is not a license and does not grant any
#- rights to the materials distributed herewith. Except as
#- otherwise provided in a valid license issued to you by
#- Xilinx, and to the maximum extent permitted by applicable
#- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
#- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
#- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
#- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
#- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
#- (2) Xilinx shall not be liable (whether in contract or tort,
#- including negligence, or under any other theory of
#- liability) for any loss or damage of any kind or nature
#- related to, arising under or in connection with these
#- materials, including for any direct, or any indirect,
#- special, incidental, or consequential loss or damage
#- (including loss of data, profits, goodwill, or any type of
#- loss or damage suffered as a result of any action brought
#- by a third party) even if such damage or loss was
#- reasonably foreseeable or Xilinx had been advised of the
#- possibility of the same.
#-
#- CRITICAL APPLICATIONS
#- Xilinx products are not designed or intended to be fail-
#- safe, or for use in any application requiring fail-safe
#- performance, such as life-support or safety devices or
#- systems, Class III medical devices, nuclear facilities,
#- applications related to the deployment of airbags, or any
#- other applications that could lead to death, personal
#- injury, or severe property or environmental damage
#- (individually and collectively, "Critical
#- Applications"). Customer assumes the sole risk and
#- liability of any use of Xilinx products in Critical
#- Applications, subject only to applicable laws and
#- regulations governing limitations on product liability.
#-
#- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
#- PART OF THIS FILE AT ALL TIMES.
#- ************************************************************************
*
*
*/
#ifndef _AP_MEM_IF_H
#define _AP_MEM_IF_H
#include <systemc.h>
//#define USER_DEBUG_MEMORY
/* ap_mem_port Types */
enum ap_mem_port_type {
RAM_1P = 0,
RAM1P = RAM_1P,
RAM_2P = 1,
RAM2P = RAM_2P,
RAM_T2P = 2,
RAMT2P = RAM_T2P,
ROM_1P = 3,
ROM1P = ROM_1P,
ROM_2P = 4,
ROM2P = ROM_2P,
};
//=================================================================
//======================== ap_mem ports =========================
//=================================================================
//----------------------------------------------------------
// ap_mem_if
//----------------------------------------------------------
template <typename _hls_mem_dt, typename _hls_mem_addrt, int t_size,
ap_mem_port_type portType = RAM1P>
class ap_mem_if : public sc_interface {
public:
// read the current value
virtual _hls_mem_dt &read(const _hls_mem_addrt addr) = 0;
virtual void write(const _hls_mem_addrt addr, const _hls_mem_dt data) = 0;
protected:
// constructor
ap_mem_if() {}
private:
// disabled
ap_mem_if(const ap_mem_if<_hls_mem_dt, _hls_mem_addrt, t_size, portType> &);
ap_mem_if<_hls_mem_dt, _hls_mem_addrt, t_size, portType> &
operator=(const ap_mem_if<_hls_mem_dt, _hls_mem_addrt, t_size, portType> &);
};
//----------------------------------------------------------
// ap_mem_port
//----------------------------------------------------------
template <typename _hls_mem_dt, typename _hls_mem_addrt, int t_size,
ap_mem_port_type portType = RAM1P>
class ap_mem_port
: public sc_port<ap_mem_if<_hls_mem_dt, _hls_mem_addrt, t_size, portType>> {
// typedefs
// typedef T _hls_mem_dt;
typedef ap_mem_if<_hls_mem_dt, _hls_mem_addrt, t_size, portType> if_type;
typedef sc_port<if_type, 1, SC_ONE_OR_MORE_BOUND> base_type;
typedef ap_mem_port<_hls_mem_dt, _hls_mem_addrt, t_size, portType> this_type;
typedef if_type in_if_type;
typedef base_type in_port_type;
_hls_mem_addrt ADDR_tmp;
public:
ap_mem_port() {
#ifndef __RTL_SIMULATION__
cout << "@W [SIM] Please add name for your ap_mem_port, or RTL simulation "
"will fail."
<< endl;
#endif
}
explicit ap_mem_port(const char *name_) {}
void reset() {}
_hls_mem_dt &read(const _hls_mem_addrt addr) { return (*this)->read(addr); }
void write(const _hls_mem_addrt addr, const _hls_mem_dt data) {
(*this)->write(addr, data);
}
ap_mem_port &operator[](const _hls_mem_addrt addr) {
// return (*this)->read(addr);
ADDR_tmp = addr;
return *this;
}
void operator=(_hls_mem_dt data) { (*this)->write(ADDR_tmp, data); }
operator _hls_mem_dt() { return (*this)->read(ADDR_tmp); }
};
//----------------------------------------------------------
// ap_mem_chn
//----------------------------------------------------------
template <typename _hls_mem_dt, typename _hls_mem_addrt, int t_size,
ap_mem_port_type portType = RAM1P>
class ap_mem_chn
: public ap_mem_if<_hls_mem_dt, _hls_mem_addrt, t_size, portType>,
public sc_prim_channel {
private:
_hls_mem_dt mArray[2][t_size];
int mInitiatorBank;
int mTargetCurBank;
int mCurBank;
std::string mem_name;
public:
explicit ap_mem_chn(const char *name = "ap_mem_chn")
: mCurBank(0), mem_name(name) {}
virtual ~ap_mem_chn(){};
_hls_mem_dt &read(const _hls_mem_addrt addr) {
#ifdef USER_DEBUG_MEMORY
cout << "mem read : " << mem_name << "[" << addr
<< "] = " << mArray[mCurBank][addr] << endl;
#endif
return mArray[mCurBank][addr];
}
void write(const _hls_mem_addrt addr, const _hls_mem_dt data) {
mArray[mCurBank][addr] = data;
#ifdef USER_DEBUG_MEMORY
cout << "mem write: " << mem_name << "[" << addr
<< "] = " << mArray[mCurBank][addr] << endl;
#endif
}
_hls_mem_dt &operator[](const _hls_mem_addrt &addr) {
return mArray[mCurBank][addr];
}
// int put() { mCurBank++; mCurBank %= 2; }
// int get() { }
};
//=================================================================
//======================== ap_pingpong_if =========================
//=================================================================
//--------------------------------------------
// ap_pingpong_if
//--------------------------------------------
template <typename _hls_mem_dt, typename _hls_mem_addrt, int t_size,
ap_mem_port_type portType = RAM1P>
class ap_pingpong_if : public sc_interface {
public:
virtual bool put_is_ready() = 0;
virtual void put_request() = 0;
virtual void put_release() = 0;
virtual _hls_mem_dt put_read(const _hls_mem_addrt addr) = 0;
virtual void put_write(const _hls_mem_addrt addr, const _hls_mem_dt data) = 0;
virtual bool get_is_ready() = 0;
virtual void get_request() = 0;
virtual void get_release() = 0;
virtual _hls_mem_dt get_read(const _hls_mem_addrt addr) = 0;
virtual void get_write(const _hls_mem_addrt addr, const _hls_mem_dt data) = 0;
protected:
// constructor
ap_pingpong_if() {}
private:
// disabled
ap_pingpong_if(
const ap_pingpong_if<_hls_mem_dt, _hls_mem_addrt, t_size, portType> &);
ap_pingpong_if<_hls_mem_dt, _hls_mem_addrt, t_size, portType> &operator=(
const ap_pingpong_if<_hls_mem_dt, _hls_mem_addrt, t_size, portType> &);
};
//--------------------------------------------
// ap_pingpong_get
//--------------------------------------------
template <typename _hls_mem_dt, typename _hls_mem_addrt, int t_size,
ap_mem_port_type portType = RAM1P>
class ap_pingpong_get
: public sc_port<
ap_pingpong_if<_hls_mem_dt, _hls_mem_addrt, t_size, portType>> {
// typedef sc_port_b<ap_pingpong_if<_hls_mem_dt, _hls_mem_addrt, t_size,
// portType> > Get_Base;
public:
explicit ap_pingpong_get(const char *name_) {}
/// functions
void reset() {}
bool is_ready() { return (*this)->get_is_ready(); }
void request() { (*this)->get_request(); }
void release() { (*this)->get_release(); }
_hls_mem_dt read(_hls_mem_addrt addr) { return (*this)->get_read(addr); }
void write(_hls_mem_addrt addr, _hls_mem_dt data) {
(*this)->get_write(addr, data);
}
};
//--------------------------------------------
// ap_pingpong_put
//--------------------------------------------
template <typename _hls_mem_dt, typename _hls_mem_addrt, int t_size,
ap_mem_port_type portType = RAM1P>
class ap_pingpong_put
: public sc_port<
ap_pingpong_if<_hls_mem_dt, _hls_mem_addrt, t_size, portType>> {
public:
explicit ap_pingpong_put(const char *name_) {}
/// functions
void reset() {}
bool is_ready() { return (*this)->put_is_ready(); }
void request() { (*this)->put_request(); }
void release() { (*this)->put_release(); }
_hls_mem_dt read(_hls_mem_addrt addr) { return (*this)->put_read(addr); }
void write(_hls_mem_addrt addr, _hls_mem_dt data) {
(*this)->put_write(addr, data);
}
};
//--------------------------------------------
// ap_pingpong_chn
//--------------------------------------------
template <typename _hls_mem_dt, typename _hls_mem_addrt, int t_size,
ap_mem_port_type portType = RAM1P>
class ap_pingpong_chn
: public ap_pingpong_if<_hls_mem_dt, _hls_mem_addrt, t_size, portType>,
public sc_prim_channel {
private:
_hls_mem_dt mArray[2][t_size];
int mInitiatorBank;
int mTargetBank;
std::string mem_name;
bool cur_bankflag[2];
bool new_bankflag[2];
protected:
virtual void update() {
cur_bankflag[0] = new_bankflag[0];
cur_bankflag[1] = new_bankflag[1];
}
public:
explicit ap_pingpong_chn(const char *name = "ap_pingpong_chn")
: mem_name(name), mInitiatorBank(0), mTargetBank(0) {
cur_bankflag[0] = 0;
cur_bankflag[1] = 0;
new_bankflag[0] = 0;
new_bankflag[1] = 0;
}
virtual ~ap_pingpong_chn(){};
/// Initiator/put APIs
bool put_is_ready() { return (!cur_bankflag[mInitiatorBank]); }
void put_request() {
do {
wait();
} while (!put_is_ready());
}
void put_release() {
new_bankflag[mInitiatorBank] = 1;
mInitiatorBank++;
mInitiatorBank %= 2;
request_update();
}
_hls_mem_dt put_read(const _hls_mem_addrt addr) {
#ifdef USER_DEBUG_MEMORY
cout << "Initor read : " << mem_name << "[" << addr
<< "] = " << mArray[mInitiatorBank][addr] << endl;
#endif
return mArray[mInitiatorBank][addr];
}
void put_write(const _hls_mem_addrt addr, const _hls_mem_dt data) {
mArray[mInitiatorBank][addr] = data;
#ifdef USER_DEBUG_MEMORY
cout << "Initor write: " << mem_name << "[" << addr
<< "] = " << mArray[mInitiatorBank][addr] << endl;
#endif
}
/// Target/get APIs
bool get_is_ready() { return (cur_bankflag[mTargetBank]); }
void get_request() {
do {
wait();
} while (!get_is_ready());
}
void get_release() {
new_bankflag[mTargetBank] = 0;
mTargetBank++;
mTargetBank %= 2;
request_update();
}
_hls_mem_dt get_read(const _hls_mem_addrt addr) {
if (!get_is_ready()) {
return 0;
}
#ifdef USER_DEBUG_MEMORY
cout << "Target read : " << mem_name << "[" << addr
<< "] = " << mArray[mTargetBank][addr] << endl;
#endif
return mArray[mTargetBank][addr];
}
void get_write(const _hls_mem_addrt addr, const _hls_mem_dt data) {
if (!get_is_ready()) {
return;
}
mArray[mTargetBank][addr] = data;
#ifdef USER_DEBUG_MEMORY
cout << "Target write: " << mem_name << "[" << addr
<< "] = " << mArray[mTargetBank][addr] << endl;
#endif
}
};
template <typename _hls_mem_dt, typename _hls_mem_addrt, int t_size,
ap_mem_port_type portType = RAM1P>
class ap_pingpong {
public:
typedef ap_pingpong_put<_hls_mem_dt, _hls_mem_addrt, t_size, portType> put;
typedef ap_pingpong_get<_hls_mem_dt, _hls_mem_addrt, t_size, portType> get;
typedef ap_pingpong_chn<_hls_mem_dt, _hls_mem_addrt, t_size, portType> chn;
};
#endif /* Header Guard */
// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
|
#ifndef IPS_FILTER_LT_MODEL_HPP
#define IPS_FILTER_LT_MODEL_HPP
#ifdef IPS_DEBUG_EN
#include <iostream>
#endif // IPS_DEBUG_ENi
#ifdef IPS_DUMP_EN
#include <sstream>
#endif // IPS_DUMP_EN
#include <systemc.h>
#ifdef USING_TLM_TB_EN
#include "ips_filter_defines.hpp"
#endif // USING_TLM_TB_EN
/**
* @brief Filter module.
* It takes care of filtering a image/kernel using a median filter or an
* equivalent convolution like:
* | 1/N^2 ... 1/N^2 | | img(row - N/2, col - N/2) ... img(row + N/2, col + N/2) |
* img(row, col) = | ... ... .... | * | ... ... ... |
* | 1/N^2 ... 1/N^2 | | img(row + N/2, col - N/2) ... img(row + N/2, col + N/2) |
*
* @tparam IN - data type of the inputs
* @tparam OUT - data type of the outputs
* @tparam N - size of the kernel
*/
template <typename IN = sc_uint<8>, typename OUT = sc_uint<8>, uint8_t N = 3>
SC_MODULE(Filter)
{
protected:
//----------------------------Internal Variables----------------------------
#ifdef IPS_DUMP_EN
sc_trace_file* wf;
#endif // IPS_DUMP_EN
OUT* img_window_tmp;
OUT* kernel;
OUT* result_ptr;
// Event to trigger the filter execution
sc_event event;
//-----------------------------Internal Methods-----------------------------
void exec_filter();
void init();
public:
/**
* @brief Default constructor for Filter
*/
SC_HAS_PROCESS(Filter);
#ifdef IPS_DUMP_EN
/**
* @brief Construct a new Filter object
*
* @param name - name of the module
* @param wf - waveform file pointer
*/
Filter(sc_core::sc_module_name name, sc_core::sc_trace_file* wf)
: sc_core::sc_module(name), wf(wf)
#else
/**
* @brief Construct a new Filter object
*
* @param name - name of the module
*/
Filter(sc_core::sc_module_name name) : sc_core::sc_module(name)
#endif // IPS_DUMP_EN
{
// Calling this method by default since it is no time consumer
// It is assumed that this kernel is already loaded in the model
// Kernel does not change after synthesis
SC_METHOD(init);
// Thread waiting for the request
SC_THREAD(exec_filter);
}
//---------------------------------Methods---------------------------------
void filter(IN* img_window, OUT* result);
};
/**
* @brief Execute the image filtering
*
*/
template <typename IN, typename OUT, uint8_t N>
void Filter<IN, OUT, N>::exec_filter()
{
size_t i;
size_t j;
while (true)
{
// Wait to peform the convolution
wait(this->event);
// Default value for the result depending on the output datatype
*(this->result_ptr) = static_cast<OUT >(0);
// Perform the convolution
for (i = 0; i < N; ++i)
for (j = 0; j < N; ++j)
*(this->result_ptr) += this->kernel[i * N + j] * this->img_window_tmp[i * N + j];
}
}
/**
* @brief Filtering image
*
* @param img_window - image window to filter
* @param result - resultant pixel
*/
template <typename IN, typename OUT, uint8_t N>
void Filter<IN, OUT, N>::filter(IN* img_window, OUT* result)
{
size_t i;
size_t j;
// Default value for the result depending on the output datatype
this->result_ptr = result;
// Perform the convolution
for (i = 0; i < N; ++i)
for (j = 0; j < N; ++j)
this->img_window_tmp[i * N + j] = static_cast<OUT >(img_window[i * N + j]);
this->event.notify(DELAY_TIME, SC_NS);
}
/**
* @brief Initializes a kernel of N x N with default value of 1 / (N^2)
*
*/
template <typename IN, typename OUT, uint8_t N>
void Filter<IN, OUT, N>::init()
{
// Init a kernel of N x N with default value of 1 / (N * N)
this->kernel = new OUT[N * N];
std::fill_n(this->kernel, N * N, static_cast<OUT >(1) / static_cast<OUT > (N * N));
// Init image window of N x N with default value of 1 / (N * N)
this->img_window_tmp = new OUT[N * N];
#ifdef IPS_DEBUG_EN
// Print the initialized kernel
SC_REPORT_INFO(this->name(), "init result");
size_t i, j;
for (i = 0; i < N; ++i)
{
for (j = 0; j < N; ++j)
{
std::cout << "[" << this->kernel[i * N + j] << "]";
#ifdef IPS_DUMP_EN
// Adding the signals to the waveform
std::ostringstream var_name;
var_name << "kernel_" << i << "_" << j;
sc_trace(this->wf, this->kernel[i * N + j], var_name.str());
#endif // IPS_DUMP_EN
}
std::cout << std::endl;
}
#else
#ifdef IPS_DUMP_EN
size_t i, j;
for (i = 0; i < N; ++i)
{
for (j = 0; j < N; ++j)
{
// Adding the signals to the waveform
std::ostringstream var_name;
var_name << "kernel_" << i << "_" << j;
sc_trace(this->wf, this->kernel[i * N + j], var_name.str());
}
}
#endif // IPS_DUMP_EN
#endif // IPS_DEBUG_EN
}
#endif // IPS_FILTER_LT_MODEL_HPP
|
/*******************************************************************************
* i2c.cpp -- Copyright 2019 (c) Glenn Ramalho - RFIDo Design
*******************************************************************************
* Description:
* Model for a I2C.
*******************************************************************************
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
#include <systemc.h>
#include "i2c.h"
#include "info.h"
void i2c::transfer_th() {
unsigned char p;
bool rwbit;
sda_en_o.write(false);
scl_en_o.write(false);
state = IDLE;
while(true) {
p = to.read();
snd.write(p);
/* For the start and stop bit, we could be in the middle of a command,
* therefore we cannot assume the bits are correct.
*/
if (p == 'S') {
sda_en_o.write(false);
scl_en_o.write(false);
wait(625, SC_NS); sda_en_o.write(true);
wait(625, SC_NS); scl_en_o.write(true);
wait(1250, SC_NS);
state = DEVID;
}
else if (p == 'P') {
/* If the SDA is high, we need to take it low first. If not, we cam
* go straight into the stop bit.
*/
wait(625, SC_NS); sda_en_o.write(true);
wait(625, SC_NS); scl_en_o.write(false);
wait(625, SC_NS); sda_en_o.write(false);
wait(1250, SC_NS);
state = IDLE;
}
else if (state == DEVID || state == WRITING) {
if (p == '1') {
wait(625, SC_NS); sda_en_o.write(false);
wait(625, SC_NS); scl_en_o.write(false);
wait(1250, SC_NS); scl_en_o.write(true);
rwbit = true;
}
else if (p == '0') {
wait(625, SC_NS); sda_en_o.write(true);
wait(625, SC_NS); scl_en_o.write(false);
wait(1250, SC_NS); scl_en_o.write(true);
rwbit = false;
}
else if (p == 'Z') {
sda_en_o.write(false);
/* Then we tick the clock. */
wait(1250, SC_NS); scl_en_o.write(false);
/* After the clock, we sample it. */
if (sda_i.read()) {
snd.write('N');
from.write('N');
state = IDLE;
}
else {
snd.write('A');
from.write('A');
/* If the readwrite bit is low and we are in the DEVID state
* we go to the WRITING state. If we are already in the WRITING
* state we remain in it.
*/
if (state == DEVID && !rwbit || state == WRITING) state= WRITING;
else state = READING;
}
wait(1250, SC_NS); scl_en_o.write(true);
}
else wait(2500, SC_NS);
}
else if (state == READING) {
if (p == 'N') {
wait(625, SC_NS); sda_en_o.write(false);
wait(625, SC_NS); scl_en_o.write(false);
wait(1250, SC_NS); scl_en_o.write(true);
state = IDLE;
}
else if (p == 'A') {
wait(625, SC_NS); sda_en_o.write(true);
wait(625, SC_NS); scl_en_o.write(false);
wait(1250, SC_NS); scl_en_o.write(true);
}
else if (p == 'Z') {
sda_en_o.write(false);
wait(1250, SC_NS); scl_en_o.write(false);
if (sda_i.read()) {
from.write('1');
snd.write('1');
}
else {
from.write('0');
snd.write('0');
}
wait(1250, SC_NS); scl_en_o.write(true);
}
else wait(2500, SC_NS);
}
}
}
void i2c::trace(sc_trace_file *tf) {
sc_trace(tf, snd, snd.name());
}
|
//**********************************************************************
// Copyright (c) 2016-2018 Xilinx Inc. All Rights Reserved
//**********************************************************************
//
// TLM wrapper for CanCat IP. It
// This is a Dummy IP and doesn't perform any real functionality. This IP will come into picture when the design is M*N Stream
//**********************************************************************
#ifndef _design_1_xlconcat_0_0_core_h_
#define _design_1_xlconcat_0_0_core_h_
#include <systemc.h>
#include "properties.h"
#define IN0_WIDTH 1
#define IN0_WIDTH 1
#define IN1_WIDTH 1
#define IN2_WIDTH 1
#define IN3_WIDTH 1
#define IN4_WIDTH 1
#define IN5_WIDTH 1
#define IN6_WIDTH 1
#define IN7_WIDTH 1
#define IN8_WIDTH 1
#define IN9_WIDTH 1
#define IN10_WIDTH 1
#define IN11_WIDTH 1
#define IN12_WIDTH 1
#define IN13_WIDTH 1
#define IN14_WIDTH 1
#define IN15_WIDTH 1
#define IN16_WIDTH 1
#define IN17_WIDTH 1
#define IN18_WIDTH 1
#define IN19_WIDTH 1
#define IN20_WIDTH 1
#define IN21_WIDTH 1
#define IN22_WIDTH 1
#define IN23_WIDTH 1
#define IN24_WIDTH 1
#define IN25_WIDTH 1
#define IN26_WIDTH 1
#define IN27_WIDTH 1
#define IN28_WIDTH 1
#define IN29_WIDTH 1
#define IN30_WIDTH 1
#define IN31_WIDTH 1
#define IN32_WIDTH 1
#define IN33_WIDTH 1
#define IN34_WIDTH 1
#define IN35_WIDTH 1
#define IN36_WIDTH 1
#define IN37_WIDTH 1
#define IN38_WIDTH 1
#define IN39_WIDTH 1
#define IN40_WIDTH 1
#define IN41_WIDTH 1
#define IN42_WIDTH 1
#define IN43_WIDTH 1
#define IN44_WIDTH 1
#define IN45_WIDTH 1
#define IN46_WIDTH 1
#define IN47_WIDTH 1
#define IN48_WIDTH 1
#define IN49_WIDTH 1
#define IN50_WIDTH 1
#define IN51_WIDTH 1
#define IN52_WIDTH 1
#define IN53_WIDTH 1
#define IN54_WIDTH 1
#define IN55_WIDTH 1
#define IN56_WIDTH 1
#define IN57_WIDTH 1
#define IN58_WIDTH 1
#define IN59_WIDTH 1
#define IN60_WIDTH 1
#define IN61_WIDTH 1
#define IN62_WIDTH 1
#define IN63_WIDTH 1
#define IN64_WIDTH 1
#define IN65_WIDTH 1
#define IN66_WIDTH 1
#define IN67_WIDTH 1
#define IN68_WIDTH 1
#define IN69_WIDTH 1
#define IN70_WIDTH 1
#define IN71_WIDTH 1
#define IN72_WIDTH 1
#define IN73_WIDTH 1
#define IN74_WIDTH 1
#define IN75_WIDTH 1
#define IN76_WIDTH 1
#define IN77_WIDTH 1
#define IN78_WIDTH 1
#define IN79_WIDTH 1
#define IN80_WIDTH 1
#define IN81_WIDTH 1
#define IN82_WIDTH 1
#define IN83_WIDTH 1
#define IN84_WIDTH 1
#define IN85_WIDTH 1
#define IN86_WIDTH 1
#define IN87_WIDTH 1
#define IN88_WIDTH 1
#define IN89_WIDTH 1
#define IN90_WIDTH 1
#define IN91_WIDTH 1
#define IN92_WIDTH 1
#define IN93_WIDTH 1
#define IN94_WIDTH 1
#define IN95_WIDTH 1
#define IN96_WIDTH 1
#define IN97_WIDTH 1
#define IN98_WIDTH 1
#define IN99_WIDTH 1
#define IN100_WIDTH 1
#define IN101_WIDTH 1
#define IN102_WIDTH 1
#define IN103_WIDTH 1
#define IN104_WIDTH 1
#define IN105_WIDTH 1
#define IN106_WIDTH 1
#define IN107_WIDTH 1
#define IN108_WIDTH 1
#define IN109_WIDTH 1
#define IN110_WIDTH 1
#define IN111_WIDTH 1
#define IN112_WIDTH 1
#define IN113_WIDTH 1
#define IN114_WIDTH 1
#define IN115_WIDTH 1
#define IN116_WIDTH 1
#define IN117_WIDTH 1
#define IN118_WIDTH 1
#define IN119_WIDTH 1
#define IN120_WIDTH 1
#define IN121_WIDTH 1
#define IN122_WIDTH 1
#define IN123_WIDTH 1
#define IN124_WIDTH 1
#define IN125_WIDTH 1
#define IN126_WIDTH 1
#define IN127_WIDTH 1
class design_1_xlconcat_0_0_core : public sc_module
{
public:
design_1_xlconcat_0_0_core (sc_core::sc_module_name nm, const xsc::common_cpp::properties& props)
: sc_module(nm)
, In0 ( "In0" )
, In1 ( "In1" )
, dout ( "dout" )
{
SC_HAS_PROCESS(design_1_xlconcat_0_0_core);
SC_METHOD(concate_input_port_values);
sensitive << In0
<< In1 ;
dont_initialize();
}
virtual ~design_1_xlconcat_0_0_core() = default;
void concate_input_port_values()
{
sc_bv <2> portConcateVal;
portConcateVal.range(0,0) = In0.read();
portConcateVal.range(1,1) = In1.read();
dout.write(portConcateVal);
}
public:
sc_in< sc_bv<IN0_WIDTH> > In0;
sc_in< sc_bv<IN1_WIDTH> > In1;
sc_out< sc_bv <2> > dout;
};
#endif
|
/*******************************************************************************
* gndemux.h -- Copyright 2019 (c) Glenn Ramalho - RFIDo Design
*******************************************************************************
* Description:
* This is a simple gnmuxin for GN logic use in testbenches.
*******************************************************************************
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
#ifndef _GNDEMUX_H
#define _GNDEMUX_H
#include <systemc.h>
#include "gn_mixed.h"
SC_MODULE(gndemux) {
sc_port< sc_signal_out_if<gn_mixed>,0 > pin {"pin"};
sc_in<int> pinS {"pinS"};
sc_in<gn_mixed> pinY {"pinY"};
void drivepin_th();
gndemux (sc_module_name name, gn_mixed _def = GN_LOGIC_Z) {
def = _def;
SC_THREAD(drivepin_th);
}
SC_HAS_PROCESS(gndemux);
protected:
gn_mixed def;
};
#endif
|
#include <systemc.h>
#include "Complex_NAgate_45.h"
#include "inverseSbox.h"
#include "inverseSbox.h"
#include "inverseSbox.h"
#include "inverseSbox.h"
#include "inverseSbox.h"
#include "inverseSbox.h"
#include "inverseSbox.h"
#include "inverseSbox.h"
#include "inverseSbox.h"
#include "inverseSbox.h"
#include "inverseSbox.h"
#include "inverseSbox.h"
#include "inverseSbox.h"
#include "inverseSbox.h"
#include "inverseSbox.h"
#include "inverseSbox.h"
#ifndef __INVERSESUBBYTES_H__
#define __INVERSESUBBYTES_H__
using namespace sc_core;
SC_MODULE( inverseSubBytes ) {
sc_in<sc_logic> in[128];
sc_out<sc_logic> out[128];
sc_signal<sc_logic> sc_logic_1_signal;
sc_signal<sc_logic> sc_logic_0_signal;
sc_signal<sc_logic, sc_core::SC_MANY_WRITERS> S0[128];
sc_signal<sc_logic, sc_core::SC_MANY_WRITERS> S1[128];
BUF_X1* BUF_X1_1;
BUF_X1* BUF_X1_2;
BUF_X1* BUF_X1_3;
BUF_X1* BUF_X1_4;
BUF_X1* BUF_X1_5;
BUF_X1* BUF_X1_6;
BUF_X1* BUF_X1_7;
BUF_X1* BUF_X1_8;
BUF_X1* BUF_X1_9;
BUF_X1* BUF_X1_10;
BUF_X1* BUF_X1_11;
BUF_X1* BUF_X1_12;
BUF_X1* BUF_X1_13;
BUF_X1* BUF_X1_14;
BUF_X1* BUF_X1_15;
BUF_X1* BUF_X1_16;
BUF_X1* BUF_X1_17;
BUF_X1* BUF_X1_18;
BUF_X1* BUF_X1_19;
BUF_X1* BUF_X1_20;
BUF_X1* BUF_X1_21;
BUF_X1* BUF_X1_22;
BUF_X1* BUF_X1_23;
BUF_X1* BUF_X1_24;
BUF_X1* BUF_X1_25;
BUF_X1* BUF_X1_26;
BUF_X1* BUF_X1_27;
BUF_X1* BUF_X1_28;
BUF_X1* BUF_X1_29;
BUF_X1* BUF_X1_30;
BUF_X1* BUF_X1_31;
BUF_X1* BUF_X1_32;
BUF_X1* BUF_X1_33;
BUF_X1* BUF_X1_34;
BUF_X1* BUF_X1_35;
BUF_X1* BUF_X1_36;
BUF_X1* BUF_X1_37;
BUF_X1* BUF_X1_38;
BUF_X1* BUF_X1_39;
BUF_X1* BUF_X1_40;
BUF_X1* BUF_X1_41;
BUF_X1* BUF_X1_42;
BUF_X1* BUF_X1_43;
BUF_X1* BUF_X1_44;
BUF_X1* BUF_X1_45;
BUF_X1* BUF_X1_46;
BUF_X1* BUF_X1_47;
BUF_X1* BUF_X1_48;
BUF_X1* BUF_X1_49;
BUF_X1* BUF_X1_50;
BUF_X1* BUF_X1_51;
BUF_X1* BUF_X1_52;
BUF_X1* BUF_X1_53;
BUF_X1* BUF_X1_54;
BUF_X1* BUF_X1_55;
BUF_X1* BUF_X1_56;
BUF_X1* BUF_X1_57;
BUF_X1* BUF_X1_58;
BUF_X1* BUF_X1_59;
BUF_X1* BUF_X1_60;
BUF_X1* BUF_X1_61;
BUF_X1* BUF_X1_62;
BUF_X1* BUF_X1_63;
BUF_X1* BUF_X1_64;
BUF_X1* BUF_X1_65;
BUF_X1* BUF_X1_66;
BUF_X1* BUF_X1_67;
BUF_X1* BUF_X1_68;
BUF_X1* BUF_X1_69;
BUF_X1* BUF_X1_70;
BUF_X1* BUF_X1_71;
BUF_X1* BUF_X1_72;
BUF_X1* BUF_X1_73;
BUF_X1* BUF_X1_74;
BUF_X1* BUF_X1_75;
BUF_X1* BUF_X1_76;
BUF_X1* BUF_X1_77;
BUF_X1* BUF_X1_78;
BUF_X1* BUF_X1_79;
BUF_X1* BUF_X1_80;
BUF_X1* BUF_X1_81;
BUF_X1* BUF_X1_82;
BUF_X1* BUF_X1_83;
BUF_X1* BUF_X1_84;
BUF_X1* BUF_X1_85;
BUF_X1* BUF_X1_86;
BUF_X1* BUF_X1_87;
BUF_X1* BUF_X1_88;
BUF_X1* BUF_X1_89;
BUF_X1* BUF_X1_90;
BUF_X1* BUF_X1_91;
BUF_X1* BUF_X1_92;
BUF_X1* BUF_X1_93;
BUF_X1* BUF_X1_94;
BUF_X1* BUF_X1_95;
BUF_X1* BUF_X1_96;
BUF_X1* BUF_X1_97;
BUF_X1* BUF_X1_98;
BUF_X1* BUF_X1_99;
BUF_X1* BUF_X1_100;
BUF_X1* BUF_X1_101;
BUF_X1* BUF_X1_102;
BUF_X1* BUF_X1_103;
BUF_X1* BUF_X1_104;
BUF_X1* BUF_X1_105;
BUF_X1* BUF_X1_106;
BUF_X1* BUF_X1_107;
BUF_X1* BUF_X1_108;
BUF_X1* BUF_X1_109;
BUF_X1* BUF_X1_110;
BUF_X1* BUF_X1_111;
BUF_X1* BUF_X1_112;
BUF_X1* BUF_X1_113;
BUF_X1* BUF_X1_114;
BUF_X1* BUF_X1_115;
BUF_X1* BUF_X1_116;
BUF_X1* BUF_X1_117;
BUF_X1* BUF_X1_118;
BUF_X1* BUF_X1_119;
BUF_X1* BUF_X1_120;
BUF_X1* BUF_X1_121;
BUF_X1* BUF_X1_122;
BUF_X1* BUF_X1_123;
BUF_X1* BUF_X1_124;
BUF_X1* BUF_X1_125;
BUF_X1* BUF_X1_126;
BUF_X1* BUF_X1_127;
BUF_X1* BUF_X1_128;
BUF_X1* BUF_X1_129;
BUF_X1* BUF_X1_130;
BUF_X1* BUF_X1_131;
BUF_X1* BUF_X1_132;
BUF_X1* BUF_X1_133;
BUF_X1* BUF_X1_134;
BUF_X1* BUF_X1_135;
BUF_X1* BUF_X1_136;
BUF_X1* BUF_X1_137;
BUF_X1* BUF_X1_138;
BUF_X1* BUF_X1_139;
BUF_X1* BUF_X1_140;
BUF_X1* BUF_X1_141;
BUF_X1* BUF_X1_142;
BUF_X1* BUF_X1_143;
BUF_X1* BUF_X1_144;
BUF_X1* BUF_X1_145;
BUF_X1* BUF_X1_146;
BUF_X1* BUF_X1_147;
BUF_X1* BUF_X1_148;
BUF_X1* BUF_X1_149;
BUF_X1* BUF_X1_150;
BUF_X1* BUF_X1_151;
BUF_X1* BUF_X1_152;
BUF_X1* BUF_X1_153;
BUF_X1* BUF_X1_154;
BUF_X1* BUF_X1_155;
BUF_X1* BUF_X1_156;
BUF_X1* BUF_X1_157;
BUF_X1* BUF_X1_158;
BUF_X1* BUF_X1_159;
BUF_X1* BUF_X1_160;
BUF_X1* BUF_X1_161;
BUF_X1* BUF_X1_162;
BUF_X1* BUF_X1_163;
BUF_X1* BUF_X1_164;
BUF_X1* BUF_X1_165;
BUF_X1* BUF_X1_166;
BUF_X1* BUF_X1_167;
BUF_X1* BUF_X1_168;
BUF_X1* BUF_X1_169;
BUF_X1* BUF_X1_170;
BUF_X1* BUF_X1_171;
BUF_X1* BUF_X1_172;
BUF_X1* BUF_X1_173;
BUF_X1* BUF_X1_174;
BUF_X1* BUF_X1_175;
BUF_X1* BUF_X1_176;
BUF_X1* BUF_X1_177;
BUF_X1* BUF_X1_178;
BUF_X1* BUF_X1_179;
BUF_X1* BUF_X1_180;
BUF_X1* BUF_X1_181;
BUF_X1* BUF_X1_182;
BUF_X1* BUF_X1_183;
BUF_X1* BUF_X1_184;
BUF_X1* BUF_X1_185;
BUF_X1* BUF_X1_186;
BUF_X1* BUF_X1_187;
BUF_X1* BUF_X1_188;
BUF_X1* BUF_X1_189;
BUF_X1* BUF_X1_190;
BUF_X1* BUF_X1_191;
BUF_X1* BUF_X1_192;
BUF_X1* BUF_X1_193;
BUF_X1* BUF_X1_194;
BUF_X1* BUF_X1_195;
BUF_X1* BUF_X1_196;
BUF_X1* BUF_X1_197;
BUF_X1* BUF_X1_198;
BUF_X1* BUF_X1_199;
BUF_X1* BUF_X1_200;
BUF_X1* BUF_X1_201;
BUF_X1* BUF_X1_202;
BUF_X1* BUF_X1_203;
BUF_X1* BUF_X1_204;
BUF_X1* BUF_X1_205;
BUF_X1* BUF_X1_206;
BUF_X1* BUF_X1_207;
BUF_X1* BUF_X1_208;
BUF_X1* BUF_X1_209;
BUF_X1* BUF_X1_210;
BUF_X1* BUF_X1_211;
BUF_X1* BUF_X1_212;
BUF_X1* BUF_X1_213;
BUF_X1* BUF_X1_214;
BUF_X1* BUF_X1_215;
BUF_X1* BUF_X1_216;
BUF_X1* BUF_X1_217;
BUF_X1* BUF_X1_218;
BUF_X1* BUF_X1_219;
BUF_X1* BUF_X1_220;
BUF_X1* BUF_X1_221;
BUF_X1* BUF_X1_222;
BUF_X1* BUF_X1_223;
BUF_X1* BUF_X1_224;
BUF_X1* BUF_X1_225;
BUF_X1* BUF_X1_226;
BUF_X1* BUF_X1_227;
BUF_X1* BUF_X1_228;
BUF_X1* BUF_X1_229;
BUF_X1* BUF_X1_230;
BUF_X1* BUF_X1_231;
BUF_X1* BUF_X1_232;
BUF_X1* BUF_X1_233;
BUF_X1* BUF_X1_234;
BUF_X1* BUF_X1_235;
BUF_X1* BUF_X1_236;
BUF_X1* BUF_X1_237;
BUF_X1* BUF_X1_238;
BUF_X1* BUF_X1_239;
BUF_X1* BUF_X1_240;
BUF_X1* BUF_X1_241;
BUF_X1* BUF_X1_242;
BUF_X1* BUF_X1_243;
BUF_X1* BUF_X1_244;
BUF_X1* BUF_X1_245;
BUF_X1* BUF_X1_246;
BUF_X1* BUF_X1_247;
BUF_X1* BUF_X1_248;
BUF_X1* BUF_X1_249;
BUF_X1* BUF_X1_250;
BUF_X1* BUF_X1_251;
BUF_X1* BUF_X1_252;
BUF_X1* BUF_X1_253;
BUF_X1* BUF_X1_254;
BUF_X1* BUF_X1_255;
BUF_X1* BUF_X1_256;
inverseSbox* sub_Bytes_0__s;
inverseSbox* sub_Bytes_104__s;
inverseSbox* sub_Bytes_112__s;
inverseSbox* sub_Bytes_120__s;
inverseSbox* sub_Bytes_16__s;
inverseSbox* sub_Bytes_24__s;
inverseSbox* sub_Bytes_32__s;
inverseSbox* sub_Bytes_40__s;
inverseSbox* sub_Bytes_48__s;
inverseSbox* sub_Bytes_56__s;
inverseSbox* sub_Bytes_64__s;
inverseSbox* sub_Bytes_72__s;
inverseSbox* sub_Bytes_80__s;
inverseSbox* sub_Bytes_88__s;
inverseSbox* sub_Bytes_8__s;
inverseSbox* sub_Bytes_96__s;
SC_CTOR( inverseSubBytes ) {
BUF_X1_1 = new BUF_X1("BUF_X1_1");
BUF_X1_1->A(in[0]);
BUF_X1_1->Z(S0[0]);
BUF_X1_2 = new BUF_X1("BUF_X1_2");
BUF_X1_2->A(in[1]);
BUF_X1_2->Z(S0[1]);
BUF_X1_3 = new BUF_X1("BUF_X1_3");
BUF_X1_3->A(in[10]);
BUF_X1_3->Z(S0[10]);
BUF_X1_4 = new BUF_X1("BUF_X1_4");
BUF_X1_4->A(in[100]);
BUF_X1_4->Z(S0[100]);
BUF_X1_5 = new BUF_X1("BUF_X1_5");
BUF_X1_5->A(in[101]);
BUF_X1_5->Z(S0[101]);
BUF_X1_6 = new BUF_X1("BUF_X1_6");
BUF_X1_6->A(in[102]);
BUF_X1_6->Z(S0[102]);
BUF_X1_7 = new BUF_X1("BUF_X1_7");
BUF_X1_7->A(in[103]);
BUF_X1_7->Z(S0[103]);
BUF_X1_8 = new BUF_X1("BUF_X1_8");
BUF_X1_8->A(in[104]);
BUF_X1_8->Z(S0[104]);
BUF_X1_9 = new BUF_X1("BUF_X1_9");
BUF_X1_9->A(in[105]);
BUF_X1_9->Z(S0[105]);
BUF_X1_10 = new BUF_X1("BUF_X1_10");
BUF_X1_10->A(in[106]);
BUF_X1_10->Z(S0[106]);
BUF_X1_11 = new BUF_X1("BUF_X1_11");
BUF_X1_11->A(in[107]);
BUF_X1_11->Z(S0[107]);
BUF_X1_12 = new BUF_X1("BUF_X1_12");
BUF_X1_12->A(in[108]);
BUF_X1_12->Z(S0[108]);
BUF_X1_13 = new BUF_X1("BUF_X1_13");
BUF_X1_13->A(in[109]);
BUF_X1_13->Z(S0[109]);
BUF_X1_14 = new BUF_X1("BUF_X1_14");
BUF_X1_14->A(in[11]);
BUF_X1_14->Z(S0[11]);
BUF_X1_15 = new BUF_X1("BUF_X1_15");
BUF_X1_15->A(in[110]);
BUF_X1_15->Z(S0[110]);
BUF_X1_16 = new BUF_X1("BUF_X1_16");
BUF_X1_16->A(in[111]);
BUF_X1_16->Z(S0[111]);
BUF_X1_17 = new BUF_X1("BUF_X1_17");
BUF_X1_17->A(in[112]);
BUF_X1_17->Z(S0[112]);
BUF_X1_18 = new BUF_X1("BUF_X1_18");
BUF_X1_18->A(in[113]);
BUF_X1_18->Z(S0[113]);
BUF_X1_19 = new BUF_X1("BUF_X1_19");
BUF_X1_19->A(in[114]);
BUF_X1_19->Z(S0[114]);
BUF_X1_20 = new BUF_X1("BUF_X1_20");
BUF_X1_20->A(in[115]);
BUF_X1_20->Z(S0[115]);
BUF_X1_21 = new BUF_X1("BUF_X1_21");
BUF_X1_21->A(in[116]);
BUF_X1_21->Z(S0[116]);
BUF_X1_22 = new BUF_X1("BUF_X1_22");
BUF_X1_22->A(in[117]);
BUF_X1_22->Z(S0[117]);
BUF_X1_23 = new BUF_X1("BUF_X1_23");
BUF_X1_23->A(in[118]);
BUF_X1_23->Z(S0[118]);
BUF_X1_24 = new BUF_X1("BUF_X1_24");
BUF_X1_24->A(in[119]);
BUF_X1_24->Z(S0[119]);
BUF_X1_25 = new BUF_X1("BUF_X1_25");
BUF_X1_25->A(in[12]);
BUF_X1_25->Z(S0[12]);
BUF_X1_26 = new BUF_X1("BUF_X1_26");
BUF_X1_26->A(in[120]);
BUF_X1_26->Z(S0[120]);
BUF_X1_27 = new BUF_X1("BUF_X1_27");
BUF_X1_27->A(in[121]);
BUF_X1_27->Z(S0[121]);
BUF_X1_28 = new BUF_X1("BUF_X1_28");
BUF_X1_28->A(in[122]);
BUF_X1_28->Z(S0[122]);
BUF_X1_29 = new BUF_X1("BUF_X1_29");
BUF_X1_29->A(in[123]);
BUF_X1_29->Z(S0[123]);
BUF_X1_30 = new BUF_X1("BUF_X1_30");
BUF_X1_30->A(in[124]);
BUF_X1_30->Z(S0[124]);
BUF_X1_31 = new BUF_X1("BUF_X1_31");
BUF_X1_31->A(in[125]);
BUF_X1_31->Z(S0[125]);
BUF_X1_32 = new BUF_X1("BUF_X1_32");
BUF_X1_32->A(in[126]);
BUF_X1_32->Z(S0[126]);
BUF_X1_33 = new BUF_X1("BUF_X1_33");
BUF_X1_33->A(in[127]);
BUF_X1_33->Z(S0[127]);
BUF_X1_34 = new BUF_X1("BUF_X1_34");
BUF_X1_34->A(in[13]);
BUF_X1_34->Z(S0[13]);
BUF_X1_35 = new BUF_X1("BUF_X1_35");
BUF_X1_35->A(in[14]);
BUF_X1_35->Z(S0[14]);
BUF_X1_36 = new BUF_X1("BUF_X1_36");
BUF_X1_36->A(in[15]);
BUF_X1_36->Z(S0[15]);
BUF_X1_37 = new BUF_X1("BUF_X1_37");
BUF_X1_37->A(in[16]);
BUF_X1_37->Z(S0[16]);
BUF_X1_38 = new BUF_X1("BUF_X1_38");
BUF_X1_38->A(in[17]);
BUF_X1_38->Z(S0[17]);
BUF_X1_39 = new BUF_X1("BUF_X1_39");
BUF_X1_39->A(in[18]);
BUF_X1_39->Z(S0[18]);
BUF_X1_40 = new BUF_X1("BUF_X1_40");
BUF_X1_40->A(in[19]);
BUF_X1_40->Z(S0[19]);
BUF_X1_41 = new BUF_X1("BUF_X1_41");
BUF_X1_41->A(in[2]);
BUF_X1_41->Z(S0[2]);
BUF_X1_42 = new BUF_X1("BUF_X1_42");
BUF_X1_42->A(in[20]);
BUF_X1_42->Z(S0[20]);
BUF_X1_43 = new BUF_X1("BUF_X1_43");
BUF_X1_43->A(in[21]);
BUF_X1_43->Z(S0[21]);
BUF_X1_44 = new BUF_X1("BUF_X1_44");
BUF_X1_44->A(in[22]);
BUF_X1_44->Z(S0[22]);
BUF_X1_45 = new BUF_X1("BUF_X1_45");
BUF_X1_45->A(in[23]);
BUF_X1_45->Z(S0[23]);
BUF_X1_46 = new BUF_X1("BUF_X1_46");
BUF_X1_46->A(in[24]);
BUF_X1_46->Z(S0[24]);
BUF_X1_47 = new BUF_X1("BUF_X1_47");
BUF_X1_47->A(in[25]);
BUF_X1_47->Z(S0[25]);
BUF_X1_48 = new BUF_X1("BUF_X1_48");
BUF_X1_48->A(in[26]);
BUF_X1_48->Z(S0[26]);
BUF_X1_49 = new BUF_X1("BUF_X1_49");
BUF_X1_49->A(in[27]);
BUF_X1_49->Z(S0[27]);
BUF_X1_50 = new BUF_X1("BUF_X1_50");
BUF_X1_50->A(in[28]);
BUF_X1_50->Z(S0[28]);
BUF_X1_51 = new BUF_X1("BUF_X1_51");
BUF_X1_51->A(in[29]);
BUF_X1_51->Z(S0[29]);
BUF_X1_52 = new BUF_X1("BUF_X1_52");
BUF_X1_52->A(in[3]);
BUF_X1_52->Z(S0[3]);
BUF_X1_53 = new BUF_X1("BUF_X1_53");
BUF_X1_53->A(in[30]);
BUF_X1_53->Z(S0[30]);
BUF_X1_54 = new BUF_X1("BUF_X1_54");
BUF_X1_54->A(in[31]);
BUF_X1_54->Z(S0[31]);
BUF_X1_55 = new BUF_X1("BUF_X1_55");
BUF_X1_55->A(in[32]);
BUF_X1_55->Z(S0[32]);
BUF_X1_56 = new BUF_X1("BUF_X1_56");
BUF_X1_56->A(in[33]);
BUF_X1_56->Z(S0[33]);
BUF_X1_57 = new BUF_X1("BUF_X1_57");
BUF_X1_57->A(in[34]);
BUF_X1_57->Z(S0[34]);
BUF_X1_58 = new BUF_X1("BUF_X1_58");
BUF_X1_58->A(in[35]);
BUF_X1_58->Z(S0[35]);
BUF_X1_59 = new BUF_X1("BUF_X1_59");
BUF_X1_59->A(in[36]);
BUF_X1_59->Z(S0[36]);
BUF_X1_60 = new BUF_X1("BUF_X1_60");
BUF_X1_60->A(in[37]);
BUF_X1_60->Z(S0[37]);
BUF_X1_61 = new BUF_X1("BUF_X1_61");
BUF_X1_61->A(in[38]);
BUF_X1_61->Z(S0[38]);
BUF_X1_62 = new BUF_X1("BUF_X1_62");
BUF_X1_62->A(in[39]);
BUF_X1_62->Z(S0[39]);
BUF_X1_63 = new BUF_X1("BUF_X1_63");
BUF_X1_63->A(in[4]);
BUF_X1_63->Z(S0[4]);
BUF_X1_64 = new BUF_X1("BUF_X1_64");
BUF_X1_64->A(in[40]);
BUF_X1_64->Z(S0[40]);
BUF_X1_65 = new BUF_X1("BUF_X1_65");
BUF_X1_65->A(in[41]);
BUF_X1_65->Z(S0[41]);
BUF_X1_66 = new BUF_X1("BUF_X1_66");
BUF_X1_66->A(in[42]);
BUF_X1_66->Z(S0[42]);
BUF_X1_67 = new BUF_X1("BUF_X1_67");
BUF_X1_67->A(in[43]);
BUF_X1_67->Z(S0[43]);
BUF_X1_68 = new BUF_X1("BUF_X1_68");
BUF_X1_68->A(in[44]);
BUF_X1_68->Z(S0[44]);
BUF_X1_69 = new BUF_X1("BUF_X1_69");
BUF_X1_69->A(in[45]);
BUF_X1_69->Z(S0[45]);
BUF_X1_70 = new BUF_X1("BUF_X1_70");
BUF_X1_70->A(in[46]);
BUF_X1_70->Z(S0[46]);
BUF_X1_71 = new BUF_X1("BUF_X1_71");
BUF_X1_71->A(in[47]);
BUF_X1_71->Z(S0[47]);
BUF_X1_72 = new BUF_X1("BUF_X1_72");
BUF_X1_72->A(in[48]);
BUF_X1_72->Z(S0[48]);
BUF_X1_73 = new BUF_X1("BUF_X1_73");
BUF_X1_73->A(in[49]);
BUF_X1_73->Z(S0[49]);
BUF_X1_74 = new BUF_X1("BUF_X1_74");
BUF_X1_74->A(in[5]);
BUF_X1_74->Z(S0[5]);
BUF_X1_75 = new BUF_X1("BUF_X1_75");
BUF_X1_75->A(in[50]);
BUF_X1_75->Z(S0[50]);
BUF_X1_76 = new BUF_X1("BUF_X1_76");
BUF_X1_76->A(in[51]);
BUF_X1_76->Z(S0[51]);
BUF_X1_77 = new BUF_X1("BUF_X1_77");
BUF_X1_77->A(in[52]);
BUF_X1_77->Z(S0[52]);
BUF_X1_78 = new BUF_X1("BUF_X1_78");
BUF_X1_78->A(in[53]);
BUF_X1_78->Z(S0[53]);
BUF_X1_79 = new BUF_X1("BUF_X1_79");
BUF_X1_79->A(in[54]);
BUF_X1_79->Z(S0[54]);
BUF_X1_80 = new BUF_X1("BUF_X1_80");
BUF_X1_80->A(in[55]);
BUF_X1_80->Z(S0[55]);
BUF_X1_81 = new BUF_X1("BUF_X1_81");
BUF_X1_81->A(in[56]);
BUF_X1_81->Z(S0[56]);
BUF_X1_82 = new BUF_X1("BUF_X1_82");
BUF_X1_82->A(in[57]);
BUF_X1_82->Z(S0[57]);
BUF_X1_83 = new BUF_X1("BUF_X1_83");
BUF_X1_83->A(in[58]);
BUF_X1_83->Z(S0[58]);
BUF_X1_84 = new BUF_X1("BUF_X1_84");
BUF_X1_84->A(in[59]);
BUF_X1_84->Z(S0[59]);
BUF_X1_85 = new BUF_X1("BUF_X1_85");
BUF_X1_85->A(in[6]);
BUF_X1_85->Z(S0[6]);
BUF_X1_86 = new BUF_X1("BUF_X1_86");
BUF_X1_86->A(in[60]);
BUF_X1_86->Z(S0[60]);
BUF_X1_87 = new BUF_X1("BUF_X1_87");
BUF_X1_87->A(in[61]);
BUF_X1_87->Z(S0[61]);
BUF_X1_88 = new BUF_X1("BUF_X1_88");
BUF_X1_88->A(in[62]);
BUF_X1_88->Z(S0[62]);
BUF_X1_89 = new BUF_X1("BUF_X1_89");
BUF_X1_89->A(in[63]);
BUF_X1_89->Z(S0[63]);
BUF_X1_90 = new BUF_X1("BUF_X1_90");
BUF_X1_90->A(in[64]);
BUF_X1_90->Z(S0[64]);
BUF_X1_91 = new BUF_X1("BUF_X1_91");
BUF_X1_91->A(in[65]);
BUF_X1_91->Z(S0[65]);
BUF_X1_92 = new BUF_X1("BUF_X1_92");
BUF_X1_92->A(in[66]);
BUF_X1_92->Z(S0[66]);
BUF_X1_93 = new BUF_X1("BUF_X1_93");
BUF_X1_93->A(in[67]);
BUF_X1_93->Z(S0[67]);
BUF_X1_94 = new BUF_X1("BUF_X1_94");
BUF_X1_94->A(in[68]);
BUF_X1_94->Z(S0[68]);
BUF_X1_95 = new BUF_X1("BUF_X1_95");
BUF_X1_95->A(in[69]);
BUF_X1_95->Z(S0[69]);
BUF_X1_96 = new BUF_X1("BUF_X1_96");
BUF_X1_96->A(in[7]);
BUF_X1_96->Z(S0[7]);
BUF_X1_97 = new BUF_X1("BUF_X1_97");
BUF_X1_97->A(in[70]);
BUF_X1_97->Z(S0[70]);
BUF_X1_98 = new BUF_X1("BUF_X1_98");
BUF_X1_98->A(in[71]);
BUF_X1_98->Z(S0[71]);
BUF_X1_99 = new BUF_X1("BUF_X1_99");
BUF_X1_99->A(in[72]);
BUF_X1_99->Z(S0[72]);
BUF_X1_100 = new BUF_X1("BUF_X1_100");
BUF_X1_100->A(in[73]);
BUF_X1_100->Z(S0[73]);
BUF_X1_101 = new BUF_X1("BUF_X1_101");
BUF_X1_101->A(in[74]);
BUF_X1_101->Z(S0[74]);
BUF_X1_102 = new BUF_X1("BUF_X1_102");
BUF_X1_102->A(in[75]);
BUF_X1_102->Z(S0[75]);
BUF_X1_103 = new BUF_X1("BUF_X1_103");
BUF_X1_103->A(in[76]);
BUF_X1_103->Z(S0[76]);
BUF_X1_104 = new BUF_X1("BUF_X1_104");
BUF_X1_104->A(in[77]);
BUF_X1_104->Z(S0[77]);
BUF_X1_105 = new BUF_X1("BUF_X1_105");
BUF_X1_105->A(in[78]);
BUF_X1_105->Z(S0[78]);
BUF_X1_106 = new BUF_X1("BUF_X1_106");
BUF_X1_106->A(in[79]);
BUF_X1_106->Z(S0[79]);
BUF_X1_107 = new BUF_X1("BUF_X1_107");
BUF_X1_107->A(in[8]);
BUF_X1_107->Z(S0[8]);
BUF_X1_108 = new BUF_X1("BUF_X1_108");
BUF_X1_108->A(in[80]);
BUF_X1_108->Z(S0[80]);
BUF_X1_109 = new BUF_X1("BUF_X1_109");
BUF_X1_109->A(in[81]);
BUF_X1_109->Z(S0[81]);
BUF_X1_110 = new BUF_X1("BUF_X1_110");
BUF_X1_110->A(in[82]);
BUF_X1_110->Z(S0[82]);
BUF_X1_111 = new BUF_X1("BUF_X1_111");
BUF_X1_111->A(in[83]);
BUF_X1_111->Z(S0[83]);
BUF_X1_112 = new BUF_X1("BUF_X1_112");
BUF_X1_112->A(in[84]);
BUF_X1_112->Z(S0[84]);
BUF_X1_113 = new BUF_X1("BUF_X1_113");
BUF_X1_113->A(in[85]);
BUF_X1_113->Z(S0[85]);
BUF_X1_114 = new BUF_X1("BUF_X1_114");
BUF_X1_114->A(in[86]);
BUF_X1_114->Z(S0[86]);
BUF_X1_115 = new BUF_X1("BUF_X1_115");
BUF_X1_115->A(in[87]);
BUF_X1_115->Z(S0[87]);
BUF_X1_116 = new BUF_X1("BUF_X1_116");
BUF_X1_116->A(in[88]);
BUF_X1_116->Z(S0[88]);
BUF_X1_117 = new BUF_X1("BUF_X1_117");
BUF_X1_117->A(in[89]);
BUF_X1_117->Z(S0[89]);
BUF_X1_118 = new BUF_X1("BUF_X1_118");
BUF_X1_118->A(in[9]);
BUF_X1_118->Z(S0[9]);
BUF_X1_119 = new BUF_X1("BUF_X1_119");
BUF_X1_119->A(in[90]);
BUF_X1_119->Z(S0[90]);
BUF_X1_120 = new BUF_X1("BUF_X1_120");
BUF_X1_120->A(in[91]);
BUF_X1_120->Z(S0[91]);
BUF_X1_121 = new BUF_X1("BUF_X1_121");
BUF_X1_121->A(in[92]);
BUF_X1_121->Z(S0[92]);
BUF_X1_122 = new BUF_X1("BUF_X1_122");
BUF_X1_122->A(in[93]);
BUF_X1_122->Z(S0[93]);
BUF_X1_12 |
3 = new BUF_X1("BUF_X1_123");
BUF_X1_123->A(in[94]);
BUF_X1_123->Z(S0[94]);
BUF_X1_124 = new BUF_X1("BUF_X1_124");
BUF_X1_124->A(in[95]);
BUF_X1_124->Z(S0[95]);
BUF_X1_125 = new BUF_X1("BUF_X1_125");
BUF_X1_125->A(in[96]);
BUF_X1_125->Z(S0[96]);
BUF_X1_126 = new BUF_X1("BUF_X1_126");
BUF_X1_126->A(in[97]);
BUF_X1_126->Z(S0[97]);
BUF_X1_127 = new BUF_X1("BUF_X1_127");
BUF_X1_127->A(in[98]);
BUF_X1_127->Z(S0[98]);
BUF_X1_128 = new BUF_X1("BUF_X1_128");
BUF_X1_128->A(in[99]);
BUF_X1_128->Z(S0[99]);
BUF_X1_129 = new BUF_X1("BUF_X1_129");
BUF_X1_129->A(S1[0]);
BUF_X1_129->Z(out[0]);
BUF_X1_130 = new BUF_X1("BUF_X1_130");
BUF_X1_130->A(S1[1]);
BUF_X1_130->Z(out[1]);
BUF_X1_131 = new BUF_X1("BUF_X1_131");
BUF_X1_131->A(S1[10]);
BUF_X1_131->Z(out[10]);
BUF_X1_132 = new BUF_X1("BUF_X1_132");
BUF_X1_132->A(S1[100]);
BUF_X1_132->Z(out[100]);
BUF_X1_133 = new BUF_X1("BUF_X1_133");
BUF_X1_133->A(S1[101]);
BUF_X1_133->Z(out[101]);
BUF_X1_134 = new BUF_X1("BUF_X1_134");
BUF_X1_134->A(S1[102]);
BUF_X1_134->Z(out[102]);
BUF_X1_135 = new BUF_X1("BUF_X1_135");
BUF_X1_135->A(S1[103]);
BUF_X1_135->Z(out[103]);
BUF_X1_136 = new BUF_X1("BUF_X1_136");
BUF_X1_136->A(S1[104]);
BUF_X1_136->Z(out[104]);
BUF_X1_137 = new BUF_X1("BUF_X1_137");
BUF_X1_137->A(S1[105]);
BUF_X1_137->Z(out[105]);
BUF_X1_138 = new BUF_X1("BUF_X1_138");
BUF_X1_138->A(S1[106]);
BUF_X1_138->Z(out[106]);
BUF_X1_139 = new BUF_X1("BUF_X1_139");
BUF_X1_139->A(S1[107]);
BUF_X1_139->Z(out[107]);
BUF_X1_140 = new BUF_X1("BUF_X1_140");
BUF_X1_140->A(S1[108]);
BUF_X1_140->Z(out[108]);
BUF_X1_141 = new BUF_X1("BUF_X1_141");
BUF_X1_141->A(S1[109]);
BUF_X1_141->Z(out[109]);
BUF_X1_142 = new BUF_X1("BUF_X1_142");
BUF_X1_142->A(S1[11]);
BUF_X1_142->Z(out[11]);
BUF_X1_143 = new BUF_X1("BUF_X1_143");
BUF_X1_143->A(S1[110]);
BUF_X1_143->Z(out[110]);
BUF_X1_144 = new BUF_X1("BUF_X1_144");
BUF_X1_144->A(S1[111]);
BUF_X1_144->Z(out[111]);
BUF_X1_145 = new BUF_X1("BUF_X1_145");
BUF_X1_145->A(S1[112]);
BUF_X1_145->Z(out[112]);
BUF_X1_146 = new BUF_X1("BUF_X1_146");
BUF_X1_146->A(S1[113]);
BUF_X1_146->Z(out[113]);
BUF_X1_147 = new BUF_X1("BUF_X1_147");
BUF_X1_147->A(S1[114]);
BUF_X1_147->Z(out[114]);
BUF_X1_148 = new BUF_X1("BUF_X1_148");
BUF_X1_148->A(S1[115]);
BUF_X1_148->Z(out[115]);
BUF_X1_149 = new BUF_X1("BUF_X1_149");
BUF_X1_149->A(S1[116]);
BUF_X1_149->Z(out[116]);
BUF_X1_150 = new BUF_X1("BUF_X1_150");
BUF_X1_150->A(S1[117]);
BUF_X1_150->Z(out[117]);
BUF_X1_151 = new BUF_X1("BUF_X1_151");
BUF_X1_151->A(S1[118]);
BUF_X1_151->Z(out[118]);
BUF_X1_152 = new BUF_X1("BUF_X1_152");
BUF_X1_152->A(S1[119]);
BUF_X1_152->Z(out[119]);
BUF_X1_153 = new BUF_X1("BUF_X1_153");
BUF_X1_153->A(S1[12]);
BUF_X1_153->Z(out[12]);
BUF_X1_154 = new BUF_X1("BUF_X1_154");
BUF_X1_154->A(S1[120]);
BUF_X1_154->Z(out[120]);
BUF_X1_155 = new BUF_X1("BUF_X1_155");
BUF_X1_155->A(S1[121]);
BUF_X1_155->Z(out[121]);
BUF_X1_156 = new BUF_X1("BUF_X1_156");
BUF_X1_156->A(S1[122]);
BUF_X1_156->Z(out[122]);
BUF_X1_157 = new BUF_X1("BUF_X1_157");
BUF_X1_157->A(S1[123]);
BUF_X1_157->Z(out[123]);
BUF_X1_158 = new BUF_X1("BUF_X1_158");
BUF_X1_158->A(S1[124]);
BUF_X1_158->Z(out[124]);
BUF_X1_159 = new BUF_X1("BUF_X1_159");
BUF_X1_159->A(S1[125]);
BUF_X1_159->Z(out[125]);
BUF_X1_160 = new BUF_X1("BUF_X1_160");
BUF_X1_160->A(S1[126]);
BUF_X1_160->Z(out[126]);
BUF_X1_161 = new BUF_X1("BUF_X1_161");
BUF_X1_161->A(S1[127]);
BUF_X1_161->Z(out[127]);
BUF_X1_162 = new BUF_X1("BUF_X1_162");
BUF_X1_162->A(S1[13]);
BUF_X1_162->Z(out[13]);
BUF_X1_163 = new BUF_X1("BUF_X1_163");
BUF_X1_163->A(S1[14]);
BUF_X1_163->Z(out[14]);
BUF_X1_164 = new BUF_X1("BUF_X1_164");
BUF_X1_164->A(S1[15]);
BUF_X1_164->Z(out[15]);
BUF_X1_165 = new BUF_X1("BUF_X1_165");
BUF_X1_165->A(S1[16]);
BUF_X1_165->Z(out[16]);
BUF_X1_166 = new BUF_X1("BUF_X1_166");
BUF_X1_166->A(S1[17]);
BUF_X1_166->Z(out[17]);
BUF_X1_167 = new BUF_X1("BUF_X1_167");
BUF_X1_167->A(S1[18]);
BUF_X1_167->Z(out[18]);
BUF_X1_168 = new BUF_X1("BUF_X1_168");
BUF_X1_168->A(S1[19]);
BUF_X1_168->Z(out[19]);
BUF_X1_169 = new BUF_X1("BUF_X1_169");
BUF_X1_169->A(S1[2]);
BUF_X1_169->Z(out[2]);
BUF_X1_170 = new BUF_X1("BUF_X1_170");
BUF_X1_170->A(S1[20]);
BUF_X1_170->Z(out[20]);
BUF_X1_171 = new BUF_X1("BUF_X1_171");
BUF_X1_171->A(S1[21]);
BUF_X1_171->Z(out[21]);
BUF_X1_172 = new BUF_X1("BUF_X1_172");
BUF_X1_172->A(S1[22]);
BUF_X1_172->Z(out[22]);
BUF_X1_173 = new BUF_X1("BUF_X1_173");
BUF_X1_173->A(S1[23]);
BUF_X1_173->Z(out[23]);
BUF_X1_174 = new BUF_X1("BUF_X1_174");
BUF_X1_174->A(S1[24]);
BUF_X1_174->Z(out[24]);
BUF_X1_175 = new BUF_X1("BUF_X1_175");
BUF_X1_175->A(S1[25]);
BUF_X1_175->Z(out[25]);
BUF_X1_176 = new BUF_X1("BUF_X1_176");
BUF_X1_176->A(S1[26]);
BUF_X1_176->Z(out[26]);
BUF_X1_177 = new BUF_X1("BUF_X1_177");
BUF_X1_177->A(S1[27]);
BUF_X1_177->Z(out[27]);
BUF_X1_178 = new BUF_X1("BUF_X1_178");
BUF_X1_178->A(S1[28]);
BUF_X1_178->Z(out[28]);
BUF_X1_179 = new BUF_X1("BUF_X1_179");
BUF_X1_179->A(S1[29]);
BUF_X1_179->Z(out[29]);
BUF_X1_180 = new BUF_X1("BUF_X1_180");
BUF_X1_180->A(S1[3]);
BUF_X1_180->Z(out[3]);
BUF_X1_181 = new BUF_X1("BUF_X1_181");
BUF_X1_181->A(S1[30]);
BUF_X1_181->Z(out[30]);
BUF_X1_182 = new BUF_X1("BUF_X1_182");
BUF_X1_182->A(S1[31]);
BUF_X1_182->Z(out[31]);
BUF_X1_183 = new BUF_X1("BUF_X1_183");
BUF_X1_183->A(S1[32]);
BUF_X1_183->Z(out[32]);
BUF_X1_184 = new BUF_X1("BUF_X1_184");
BUF_X1_184->A(S1[33]);
BUF_X1_184->Z(out[33]);
BUF_X1_185 = new BUF_X1("BUF_X1_185");
BUF_X1_185->A(S1[34]);
BUF_X1_185->Z(out[34]);
BUF_X1_186 = new BUF_X1("BUF_X1_186");
BUF_X1_186->A(S1[35]);
BUF_X1_186->Z(out[35]);
BUF_X1_187 = new BUF_X1("BUF_X1_187");
BUF_X1_187->A(S1[36]);
BUF_X1_187->Z(out[36]);
BUF_X1_188 = new BUF_X1("BUF_X1_188");
BUF_X1_188->A(S1[37]);
BUF_X1_188->Z(out[37]);
BUF_X1_189 = new BUF_X1("BUF_X1_189");
BUF_X1_189->A(S1[38]);
BUF_X1_189->Z(out[38]);
BUF_X1_190 = new BUF_X1("BUF_X1_190");
BUF_X1_190->A(S1[39]);
BUF_X1_190->Z(out[39]);
BUF_X1_191 = new BUF_X1("BUF_X1_191");
BUF_X1_191->A(S1[4]);
BUF_X1_191->Z(out[4]);
BUF_X1_192 = new BUF_X1("BUF_X1_192");
BUF_X1_192->A(S1[40]);
BUF_X1_192->Z(out[40]);
BUF_X1_193 = new BUF_X1("BUF_X1_193");
BUF_X1_193->A(S1[41]);
BUF_X1_193->Z(out[41]);
BUF_X1_194 = new BUF_X1("BUF_X1_194");
BUF_X1_194->A(S1[42]);
BUF_X1_194->Z(out[42]);
BUF_X1_195 = new BUF_X1("BUF_X1_195");
BUF_X1_195->A(S1[43]);
BUF_X1_195->Z(out[43]);
BUF_X1_196 = new BUF_X1("BUF_X1_196");
BUF_X1_196->A(S1[44]);
BUF_X1_196->Z(out[44]);
BUF_X1_197 = new BUF_X1("BUF_X1_197");
BUF_X1_197->A(S1[45]);
BUF_X1_197->Z(out[45]);
BUF_X1_198 = new BUF_X1("BUF_X1_198");
BUF_X1_198->A(S1[46]);
BUF_X1_198->Z(out[46]);
BUF_X1_199 = new BUF_X1("BUF_X1_199");
BUF_X1_199->A(S1[47]);
BUF_X1_199->Z(out[47]);
BUF_X1_200 = new BUF_X1("BUF_X1_200");
BUF_X1_200->A(S1[48]);
BUF_X1_200->Z(out[48]);
BUF_X1_201 = new BUF_X1("BUF_X1_201");
BUF_X1_201->A(S1[49]);
BUF_X1_201->Z(out[49]);
BUF_X1_202 = new BUF_X1("BUF_X1_202");
BUF_X1_202->A(S1[5]);
BUF_X1_202->Z(out[5]);
BUF_X1_203 = new BUF_X1("BUF_X1_203");
BUF_X1_203->A(S1[50]);
BUF_X1_203->Z(out[50]);
BUF_X1_204 = new BUF_X1("BUF_X1_204");
BUF_X1_204->A(S1[51]);
BUF_X1_204->Z(out[51]);
BUF_X1_205 = new BUF_X1("BUF_X1_205");
BUF_X1_205->A(S1[52]);
BUF_X1_205->Z(out[52]);
BUF_X1_206 = new BUF_X1("BUF_X1_206");
BUF_X1_206->A(S1[53]);
BUF_X1_206->Z(out[53]);
BUF_X1_207 = new BUF_X1("BUF_X1_207");
BUF_X1_207->A(S1[54]);
BUF_X1_207->Z(out[54]);
BUF_X1_208 = new BUF_X1("BUF_X1_208");
BUF_X1_208->A(S1[55]);
BUF_X1_208->Z(out[55]);
BUF_X1_209 = new BUF_X1("BUF_X1_209");
BUF_X1_209->A(S1[56]);
BUF_X1_209->Z(out[56]);
BUF_X1_210 = new BUF_X1("BUF_X1_210");
BUF_X1_210->A(S1[57]);
BUF_X1_210->Z(out[57]);
BUF_X1_211 = new BUF_X1("BUF_X1_211");
BUF_X1_211->A(S1[58]);
BUF_X1_211->Z(out[58]);
BUF_X1_212 = new BUF_X1("BUF_X1_212");
BUF_X1_212->A(S1[59]);
BUF_X1_212->Z(out[59]);
BUF_X1_213 = new BUF_X1("BUF_X1_213");
BUF_X1_213->A(S1[6]);
BUF_X1_213->Z(out[6]);
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BUF_X1_224->Z(out[7]);
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BUF_X1_225->Z(out[70]);
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BUF_X1_226->Z(out[71]);
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BUF_X1_231->Z(out[76]);
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BUF_X1_232->Z(out[77]);
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BUF_X1_233->Z(out[78]);
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BUF_X1_234->Z(out[79]);
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BUF_X1_235->Z(out[8]);
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BUF_X1_236->Z(out[80]);
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BUF_X1_237->Z(out[81]);
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BUF_X1_238->Z(out[82]);
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BUF_X1_239->Z(out[83]);
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BUF_X1_240->Z(out[84]);
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BUF_X1_241->Z(out[85]);
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BUF_X1_242->Z(out[86]);
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BUF_X1_243->Z(out[87]);
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BUF_X1_244->Z(out[88]);
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BUF_X1_245->Z(out[89]);
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BUF_X1_246->Z(out[9]);
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BUF_X1_247->Z(out[90]);
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BUF_X1_248->Z(out[91]);
BUF_X1_249 = new BUF_X1("BUF_X1_249");
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BUF_X1_249->Z(out[92]);
BUF_X1_250 = new BUF_X1("BUF_X1_250");
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BUF_X1_250->Z(out[93]);
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BUF_X1_251->Z(out[94]);
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BUF_X1_252->Z(out[95]);
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BUF_X1_253->Z(out[96]);
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BUF_X1_254->Z(out[97]);
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BUF_X1_255->Z(out[98]);
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BUF_X1_256->Z(out[99]);
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sub_Bytes_0__s->sbout[1](S1[1]);
sub_Bytes_0__s->sbout[2](S1[2]);
sub_Bytes_0__s->sbout[3](S1[3]);
sub_Bytes_0__s->sbout[4](S1[4]);
sub_Bytes_0__s->sbout[5](S1[5]);
sub_Bytes_0__s->sbout[6](S1[6]);
sub_Bytes_0__s->sbout[7](S1[7]);
sub_Bytes_0__s->selector[0](S0[0]);
sub_Bytes_0__s->selector[1](S0[1]);
sub_Bytes_0__s->selector[2](S0[2]);
sub_Bytes_0__s->selector[3](S0[3]);
sub_Bytes_0__s->selector[4](S0[4]);
sub_Bytes_0__s->selector[5](S0[5]);
sub_Bytes_0__s->selector[6](S0[6]);
sub_Bytes_0__s->selector[7](S0[7]);
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sub_Bytes_104__s->sbout[0](S1[104]);
sub_Bytes_104__s->sbout[1](S1[105]);
sub_Bytes_104__s->sbout[2](S1[106]);
sub_Bytes_104__s->sbout[3](S1[107]);
sub_Bytes_104__s->sbout[4](S1[108]);
sub_Bytes_104__s->sbout[5](S1[109]);
sub_Bytes_104__s->sbout[6](S1[110]);
sub_Bytes_104__s->sbout[7](S1[111]);
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sub_Bytes_104__s->selector[1](S0[105]);
sub_Bytes_104__s->selector[2](S0[106]);
sub_Bytes_104__s->selector[3](S0[107]);
sub_Bytes_104__s->selector[4](S0[108]);
sub_Bytes_104__s->selector[5](S0[109]);
sub_Bytes_104__s->selector[6](S0[110]);
sub_Bytes_104__s->selector[7](S0[111]);
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sub_Bytes_112__s->sbout[0](S1[112]);
sub_Bytes_112__s->sbout[1](S1[113]);
sub_Bytes_112__s->sbout[2](S1[114]);
sub_Bytes_112__s->sbout[3](S1[115]);
sub_Bytes_112__s->sbout[4](S1[116]);
sub_Bytes_112__s->sbout[5](S1[117]);
sub_Bytes_112__s->sbout[6](S1[118]);
sub_Bytes_112__s->sbout[7](S1[119]);
sub_Bytes_112__s->selector[0](S0[112]);
sub_Bytes_112__s->selector[1](S0[113]);
sub_Bytes_112__s->selector[2](S0[114]);
sub_Bytes_112__s->selector[3](S0[115]);
sub_Bytes_112__s->selector[4](S0[116]);
sub_Bytes_112__s->selector[5](S0[117]);
sub_Bytes_112__s->selector[6](S0[118]);
sub_Bytes_112__s->selector[7](S0[119]);
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sub_Bytes_120__s->sbout[0](S1[120]);
sub_Bytes_120__s->sbout[1](S1[121]);
sub_Bytes_120__s->sbout[2](S1[122]);
sub_Bytes_120__s->sbout[3](S1[123]);
sub_Bytes_120__s->sbout[4](S1[124]);
sub_Bytes_120__s->sbout[5](S1[125]);
sub_Bytes_120__s->sbout[6](S1[126]);
sub_Bytes_120__s->sbout[7](S1[127]);
sub_Bytes_120__s->selector[0](S0[120]);
sub_Bytes_120__s->selector[1](S0[121]);
sub_Bytes_120__s->selector[2](S0[122]);
sub_Bytes_120__s->selector[3](S0[123]);
sub_Bytes_120__s->selector[4](S0[124]);
sub_Bytes_120__s->selector[5](S0[125]);
sub_Bytes_120__s->selector[6](S0[126]);
sub_Bytes_120__s->selector[7](S0[127]);
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sub_Bytes_16__s->sbout[0](S1[16]);
sub_Bytes_16__s->sbout[1](S1[17]);
sub_Bytes_16__s->sbout[2](S1[18]);
sub_Bytes_16__s->sbout[3](S1[19]);
sub_Bytes_16__s->sbout[4](S1[20]);
sub_Bytes_16__s->sbout[5](S1[21]);
sub_Bytes_16__s->sbout[6](S1[22]);
sub_Bytes_16__s->sbout[7](S1[23]);
sub_Bytes_16__s->selector[0](S0[16]);
sub_Bytes_16__s->selector[1](S0[17]);
sub_Bytes_16__s->selector[2](S0[18]);
sub_Bytes_16__s->selector[3](S0[19]);
sub_Bytes_16__s->selector[4](S0[20]);
sub_Bytes_16__s->selector[5](S0[21]);
sub_Bytes_16__s->selector[6](S0[22]);
sub_Bytes_16__s->selector[7](S0[23]);
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sub_Bytes_24__s->sbout[0](S1[24]);
sub_Bytes_24__s->sbout[1](S1[25]);
sub_Bytes_24__s->sbout[2](S1[26]);
sub_Bytes_24__s->sbout[3](S1[27]);
sub_Bytes_24__s->sbout[4](S1[28]);
sub_Bytes_24__s->sbout[5](S1[29]);
sub_Bytes_24__s->sbout[6](S1[30]);
sub_Bytes_24__s->sbout[7](S1[31]);
sub_Bytes_24__s->selector[0](S0[24]);
sub_Bytes_24__s->selector[1](S0[25]);
sub_Bytes_24__s->selector[2](S0[26]);
sub_Bytes_24__s->selector[3](S0[27]);
sub_Bytes_24__s->selector[4](S0[28]);
sub_Bytes_24__s->selector[5](S0[29]);
sub_Bytes_24__s->selector[6](S0[30]);
sub_Bytes_24__s->selector[7](S0[31]);
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sub_Bytes_32__s->sbout[0](S1[32]);
sub_Bytes_32__s->sbout[1](S1[33]);
sub_Bytes_32__s->sbout[2](S1[34]);
sub_Bytes_32__s->sbout[3](S1[35]);
sub_Bytes_32__s->sbout[4](S1[36]);
sub_Bytes_32__s->sbout[5](S1[37]);
sub_Bytes_32__s->sbout[6](S1[38]);
sub_Bytes_32__s->sbout[7](S1[39]);
sub_Bytes_32__s->selector[0](S0[32]);
sub_Bytes_32__s->selector[1](S0[33]);
sub_Bytes_32__s->selector[2](S0[34]);
sub_Bytes_32__s->selector[3](S0[35]);
sub_Bytes_32__s->selector[4](S0[36]);
sub_Bytes_32__s->selector[5](S0[37]);
sub_Bytes_32__s->selector[6](S0[38]);
sub_Bytes_32__s->selector[7](S0[39]);
sub_Bytes_40__s = new inverseSbox("sub_Bytes_40__s");
sub_Bytes_40__s->sbout[0](S1[40]);
sub_Bytes_40__s->sbout[1](S1[41]);
sub_Bytes_40__s->sbout[2](S1 |
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sub_Bytes_40__s->sbout[3](S1[43]);
sub_Bytes_40__s->sbout[4](S1[44]);
sub_Bytes_40__s->sbout[5](S1[45]);
sub_Bytes_40__s->sbout[6](S1[46]);
sub_Bytes_40__s->sbout[7](S1[47]);
sub_Bytes_40__s->selector[0](S0[40]);
sub_Bytes_40__s->selector[1](S0[41]);
sub_Bytes_40__s->selector[2](S0[42]);
sub_Bytes_40__s->selector[3](S0[43]);
sub_Bytes_40__s->selector[4](S0[44]);
sub_Bytes_40__s->selector[5](S0[45]);
sub_Bytes_40__s->selector[6](S0[46]);
sub_Bytes_40__s->selector[7](S0[47]);
sub_Bytes_48__s = new inverseSbox("sub_Bytes_48__s");
sub_Bytes_48__s->sbout[0](S1[48]);
sub_Bytes_48__s->sbout[1](S1[49]);
sub_Bytes_48__s->sbout[2](S1[50]);
sub_Bytes_48__s->sbout[3](S1[51]);
sub_Bytes_48__s->sbout[4](S1[52]);
sub_Bytes_48__s->sbout[5](S1[53]);
sub_Bytes_48__s->sbout[6](S1[54]);
sub_Bytes_48__s->sbout[7](S1[55]);
sub_Bytes_48__s->selector[0](S0[48]);
sub_Bytes_48__s->selector[1](S0[49]);
sub_Bytes_48__s->selector[2](S0[50]);
sub_Bytes_48__s->selector[3](S0[51]);
sub_Bytes_48__s->selector[4](S0[52]);
sub_Bytes_48__s->selector[5](S0[53]);
sub_Bytes_48__s->selector[6](S0[54]);
sub_Bytes_48__s->selector[7](S0[55]);
sub_Bytes_56__s = new inverseSbox("sub_Bytes_56__s");
sub_Bytes_56__s->sbout[0](S1[56]);
sub_Bytes_56__s->sbout[1](S1[57]);
sub_Bytes_56__s->sbout[2](S1[58]);
sub_Bytes_56__s->sbout[3](S1[59]);
sub_Bytes_56__s->sbout[4](S1[60]);
sub_Bytes_56__s->sbout[5](S1[61]);
sub_Bytes_56__s->sbout[6](S1[62]);
sub_Bytes_56__s->sbout[7](S1[63]);
sub_Bytes_56__s->selector[0](S0[56]);
sub_Bytes_56__s->selector[1](S0[57]);
sub_Bytes_56__s->selector[2](S0[58]);
sub_Bytes_56__s->selector[3](S0[59]);
sub_Bytes_56__s->selector[4](S0[60]);
sub_Bytes_56__s->selector[5](S0[61]);
sub_Bytes_56__s->selector[6](S0[62]);
sub_Bytes_56__s->selector[7](S0[63]);
sub_Bytes_64__s = new inverseSbox("sub_Bytes_64__s");
sub_Bytes_64__s->sbout[0](S1[64]);
sub_Bytes_64__s->sbout[1](S1[65]);
sub_Bytes_64__s->sbout[2](S1[66]);
sub_Bytes_64__s->sbout[3](S1[67]);
sub_Bytes_64__s->sbout[4](S1[68]);
sub_Bytes_64__s->sbout[5](S1[69]);
sub_Bytes_64__s->sbout[6](S1[70]);
sub_Bytes_64__s->sbout[7](S1[71]);
sub_Bytes_64__s->selector[0](S0[64]);
sub_Bytes_64__s->selector[1](S0[65]);
sub_Bytes_64__s->selector[2](S0[66]);
sub_Bytes_64__s->selector[3](S0[67]);
sub_Bytes_64__s->selector[4](S0[68]);
sub_Bytes_64__s->selector[5](S0[69]);
sub_Bytes_64__s->selector[6](S0[70]);
sub_Bytes_64__s->selector[7](S0[71]);
sub_Bytes_72__s = new inverseSbox("sub_Bytes_72__s");
sub_Bytes_72__s->sbout[0](S1[72]);
sub_Bytes_72__s->sbout[1](S1[73]);
sub_Bytes_72__s->sbout[2](S1[74]);
sub_Bytes_72__s->sbout[3](S1[75]);
sub_Bytes_72__s->sbout[4](S1[76]);
sub_Bytes_72__s->sbout[5](S1[77]);
sub_Bytes_72__s->sbout[6](S1[78]);
sub_Bytes_72__s->sbout[7](S1[79]);
sub_Bytes_72__s->selector[0](S0[72]);
sub_Bytes_72__s->selector[1](S0[73]);
sub_Bytes_72__s->selector[2](S0[74]);
sub_Bytes_72__s->selector[3](S0[75]);
sub_Bytes_72__s->selector[4](S0[76]);
sub_Bytes_72__s->selector[5](S0[77]);
sub_Bytes_72__s->selector[6](S0[78]);
sub_Bytes_72__s->selector[7](S0[79]);
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sub_Bytes_80__s->sbout[0](S1[80]);
sub_Bytes_80__s->sbout[1](S1[81]);
sub_Bytes_80__s->sbout[2](S1[82]);
sub_Bytes_80__s->sbout[3](S1[83]);
sub_Bytes_80__s->sbout[4](S1[84]);
sub_Bytes_80__s->sbout[5](S1[85]);
sub_Bytes_80__s->sbout[6](S1[86]);
sub_Bytes_80__s->sbout[7](S1[87]);
sub_Bytes_80__s->selector[0](S0[80]);
sub_Bytes_80__s->selector[1](S0[81]);
sub_Bytes_80__s->selector[2](S0[82]);
sub_Bytes_80__s->selector[3](S0[83]);
sub_Bytes_80__s->selector[4](S0[84]);
sub_Bytes_80__s->selector[5](S0[85]);
sub_Bytes_80__s->selector[6](S0[86]);
sub_Bytes_80__s->selector[7](S0[87]);
sub_Bytes_88__s = new inverseSbox("sub_Bytes_88__s");
sub_Bytes_88__s->sbout[0](S1[88]);
sub_Bytes_88__s->sbout[1](S1[89]);
sub_Bytes_88__s->sbout[2](S1[90]);
sub_Bytes_88__s->sbout[3](S1[91]);
sub_Bytes_88__s->sbout[4](S1[92]);
sub_Bytes_88__s->sbout[5](S1[93]);
sub_Bytes_88__s->sbout[6](S1[94]);
sub_Bytes_88__s->sbout[7](S1[95]);
sub_Bytes_88__s->selector[0](S0[88]);
sub_Bytes_88__s->selector[1](S0[89]);
sub_Bytes_88__s->selector[2](S0[90]);
sub_Bytes_88__s->selector[3](S0[91]);
sub_Bytes_88__s->selector[4](S0[92]);
sub_Bytes_88__s->selector[5](S0[93]);
sub_Bytes_88__s->selector[6](S0[94]);
sub_Bytes_88__s->selector[7](S0[95]);
sub_Bytes_8__s = new inverseSbox("sub_Bytes_8__s");
sub_Bytes_8__s->sbout[0](S1[8]);
sub_Bytes_8__s->sbout[1](S1[9]);
sub_Bytes_8__s->sbout[2](S1[10]);
sub_Bytes_8__s->sbout[3](S1[11]);
sub_Bytes_8__s->sbout[4](S1[12]);
sub_Bytes_8__s->sbout[5](S1[13]);
sub_Bytes_8__s->sbout[6](S1[14]);
sub_Bytes_8__s->sbout[7](S1[15]);
sub_Bytes_8__s->selector[0](S0[8]);
sub_Bytes_8__s->selector[1](S0[9]);
sub_Bytes_8__s->selector[2](S0[10]);
sub_Bytes_8__s->selector[3](S0[11]);
sub_Bytes_8__s->selector[4](S0[12]);
sub_Bytes_8__s->selector[5](S0[13]);
sub_Bytes_8__s->selector[6](S0[14]);
sub_Bytes_8__s->selector[7](S0[15]);
sub_Bytes_96__s = new inverseSbox("sub_Bytes_96__s");
sub_Bytes_96__s->sbout[0](S1[96]);
sub_Bytes_96__s->sbout[1](S1[97]);
sub_Bytes_96__s->sbout[2](S1[98]);
sub_Bytes_96__s->sbout[3](S1[99]);
sub_Bytes_96__s->sbout[4](S1[100]);
sub_Bytes_96__s->sbout[5](S1[101]);
sub_Bytes_96__s->sbout[6](S1[102]);
sub_Bytes_96__s->sbout[7](S1[103]);
sub_Bytes_96__s->selector[0](S0[96]);
sub_Bytes_96__s->selector[1](S0[97]);
sub_Bytes_96__s->selector[2](S0[98]);
sub_Bytes_96__s->selector[3](S0[99]);
sub_Bytes_96__s->selector[4](S0[100]);
sub_Bytes_96__s->selector[5](S0[101]);
sub_Bytes_96__s->selector[6](S0[102]);
sub_Bytes_96__s->selector[7](S0[103]);
SC_METHOD(sc_logic_signal_assignment);
}
void sc_logic_signal_assignment(void){
sc_logic_1_signal.write(SC_LOGIC_1);
sc_logic_0_signal.write(SC_LOGIC_0);
}
};
#endif /* __INVERSESUBBYTES_H__ */
|
// Stop fonts etc being loaded multiple times
#ifndef _TFTDEBUGWRAP_H
#define _TFTDEBUGWRAP_H
#include <TFT_eSPI.h>
#include <systemc.h>
#include <stdint.h>
// Class functions and variables
class tftdebugwrap : public TFT_eSPI {
public:
tftdebugwrap(int16_t _W = TFT_WIDTH, int16_t _H = TFT_HEIGHT);
sc_event start;
sc_event end;
String msg;
int _x1, _y1, _x2, _y2;
unsigned int fg, bg;
int sz;
bool skip;
void drawChar(int32_t x, int32_t y, uint16_t c, uint32_t color, uint32_t bg,
uint8_t size);
void drawLine(int32_t x0, int32_t y0, int32_t x1, int32_t y1,
uint32_t color);
void drawFastVLine(int32_t x, int32_t y, int32_t h, uint32_t color);
void drawFastHLine(int32_t x, int32_t y, int32_t w, uint32_t color);
void fillRect(int32_t x, int32_t y, int32_t w, int32_t h,
uint32_t color);
int16_t drawChar(uint16_t uniCode, int32_t x, int32_t y,
uint8_t font);
virtual int16_t drawChar(uint16_t uniCode, int32_t x, int32_t y);
void setWindow(int32_t xs, int32_t ys, int32_t xe, int32_t ye);
void drawRect(int32_t x, int32_t y, int32_t w, int32_t h, uint32_t color);
void drawRoundRect(int32_t x0, int32_t y0, int32_t w, int32_t h,
int32_t radius, uint32_t color);
void fillRoundRect(int32_t x0, int32_t y0, int32_t w, int32_t h,
int32_t radius, uint32_t color);
void setRotation(uint8_t r);
void invertDisplay(boolean i);
void drawCircle(int32_t x0, int32_t y0, int32_t r, uint32_t color);
void fillCircle(int32_t x0, int32_t y0, int32_t r, uint32_t color);
void drawEllipse(int16_t x0, int16_t y0, int32_t rx, int32_t ry,
uint16_t color);
void fillEllipse(int16_t x0, int16_t y0, int32_t rx, int32_t ry,
uint16_t color);
void drawBitmap(int16_t x, int16_t y, const uint8_t *bitmap, int16_t w,
int16_t h, uint16_t color);
void pushImage(int32_t x0, int32_t y0, int32_t w, int32_t h, uint16_t *data);
void pushImage(int32_t x0, int32_t y0, int32_t w, int32_t h, uint16_t *data,
uint16_t transparent);
void pushImage(int32_t x0, int32_t y0, int32_t w, int32_t h,
const uint16_t *data, uint16_t transparent);
void pushImage(int32_t x0, int32_t y0, int32_t w, int32_t h,
const uint16_t *data);
void pushImage(int32_t x0, int32_t y0, int32_t w, int32_t h,
uint8_t *data, bool bpp8 = true);
void pushImage(int32_t x0, int32_t y0, int32_t w, int32_t h,
uint8_t *data, uint8_t transparent, bool bpp8 = true);
int16_t drawNumber(long long_num, int32_t poX, int32_t poY, uint8_t font);
int16_t drawNumber(long long_num, int32_t poX, int32_t poY);
int16_t drawFloat(float floatNumber, uint8_t decimal, int32_t poX,
int32_t poY, uint8_t font);
int16_t drawFloat(float floatNumber, uint8_t decimal, int32_t poX,
int32_t poY);
int16_t drawString(const char *string, int32_t poX, int32_t poY,
uint8_t font);
int16_t drawString(const char *string, int32_t poX, int32_t poY);
int16_t drawString(const String& string, int32_t poX, int32_t poY,
uint8_t font);
int16_t drawString(const String& string, int32_t poX, int32_t poY);
void startcmd(const char *nm, int nx1, int ny1, int nx2, int ny2, int nfg,
int nbg, int nsz);
void endcmd();
void set_debug(bool on) { debug = on; }
protected:
bool debug;
bool pushskip(int nx1, int ny1, int nx2, int ny2, int nfg,
int nbg, int nsz, String nm);
void popskip(bool wasskip);
};
#endif
|
#ifndef IPS_FILTER_AT_MODEL_HPP
#define IPS_FILTER_AT_MODEL_HPP
#ifdef IPS_DEBUG_EN
#include <iostream>
#endif // IPS_DEBUG_ENi
#ifdef IPS_DUMP_EN
#include <sstream>
#endif // IPS_DUMP_EN
#include <systemc.h>
/**
* @brief Filter module.
* It takes care of filtering a image/kernel using a median filter or an
* equivalent convolution like:
* | 1/N^2 ... 1/N^2 | | img(row - N/2, col - N/2) ... img(row + N/2, col + N/2) |
* img(row, col) = | ... ... .... | * | ... ... ... |
* | 1/N^2 ... 1/N^2 | | img(row + N/2, col - N/2) ... img(row + N/2, col + N/2) |
*
* @tparam IN - data type of the inputs
* @tparam OUT - data type of the outputs
* @tparam N - size of the kernel
*/
template <typename IN = sc_uint<8>, typename OUT = sc_uint<8>, uint8_t N = 3>
SC_MODULE(Filter)
{
protected:
//----------------------------Internal Variables----------------------------
#ifdef IPS_DUMP_EN
sc_trace_file* wf;
#endif // IPS_DUMP_EN
OUT* kernel;
// Event to trigger the filter execution
sc_event event;
//-----------------------------Internal Methods-----------------------------
void exec_filter();
void init();
public:
sc_in<IN* > img_window;
sc_out<OUT > result;
/**
* @brief Default constructor for Filter
*/
SC_HAS_PROCESS(Filter);
#ifdef IPS_DUMP_EN
/**
* @brief Construct a new Filter object
*
* @param name - name of the module
* @param wf - waveform file pointer
*/
Filter(sc_core::sc_module_name name, sc_core::sc_trace_file* wf)
: sc_core::sc_module(name), wf(wf)
#else
/**
* @brief Construct a new Filter object
*
* @param name - name of the module
*/
Filter(sc_core::sc_module_name name) : sc_core::sc_module(name)
#endif // IPS_DUMP_EN
{
// Calling this method by default since it is no time consumer
// It is assumed that this kernel is already loaded in the model
// Kernel does not change after synthesis
SC_METHOD(init);
// Thread waiting for the request
SC_THREAD(exec_filter);
}
//---------------------------------Methods---------------------------------
void filter();
};
/**
* @brief Execute the image filtering
*
*/
template <typename IN, typename OUT, uint8_t N>
void Filter<IN, OUT, N>::exec_filter()
{
size_t i;
size_t j;
OUT result_tmp;
while (true)
{
// Wait to peform the convolution
wait(this->event);
// Default value for the result depending on the output datatype
result_tmp = static_cast<OUT >(0);
// Getting the image window to filter
IN* img_window_tmp = this->img_window.read();
// Perform the convolution
for (i = 0; i < N; ++i)
for (j = 0; j < N; ++j)
result_tmp += this->kernel[i * N + j] * static_cast<OUT >(img_window_tmp[i * N + j]);
this->result.write(result_tmp);
}
}
/**
* @brief Filtering image
*
* @param img_window - image window to filter
* @param result - resultant pixel
*/
template <typename IN, typename OUT, uint8_t N>
void Filter<IN, OUT, N>::filter()
{
this->event.notify(DELAY_TIME, SC_NS);
}
/**
* @brief Initializes a kernel of N x N with default value of 1 / (N^2)
*
*/
template <typename IN, typename OUT, uint8_t N>
void Filter<IN, OUT, N>::init()
{
// Init a kernel of N x N with default value of 1 / (N * N)
this->kernel = new OUT[N * N];
std::fill_n(this->kernel, N * N, static_cast<OUT >(1) / static_cast<OUT >(N * N));
#ifdef IPS_DEBUG_EN
// Print the initialized kernel
SC_REPORT_INFO(this->name(), "init result");
size_t i, j;
for (i = 0; i < N; ++i)
{
for (j = 0; j < N; ++j)
{
std::cout << "[" << this->kernel[i * N + j] << "]";
#ifdef IPS_DUMP_EN
// Adding the signals to the waveform
std::ostringstream var_name;
var_name << "kernel_" << i << "_" << j;
sc_trace(this->wf, this->kernel[i * N + j], var_name.str());
#endif // IPS_DUMP_EN
}
std::cout << std::endl;
}
#else
#ifdef IPS_DUMP_EN
size_t i, j;
for (i = 0; i < N; ++i)
{
for (j = 0; j < N; ++j)
{
// Adding the signals to the waveform
std::ostringstream var_name;
var_name << "kernel_" << i << "_" << j;
sc_trace(this->wf, this->kernel[i * N + j], var_name.str());
}
}
#endif // IPS_DUMP_EN
#endif // IPS_DEBUG_EN
}
#endif // IPS_FILTER_AT_MODEL_HPP
|
/*****************************************************************************
Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
more contributor license agreements. See the NOTICE file distributed
with this work for additional information regarding copyright ownership.
Accellera licenses this file to you under the Apache License, Version 2.0
(the "License"); you may not use this file except in compliance with the
License. You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
implied. See the License for the specific language governing
permissions and limitations under the License.
*****************************************************************************/
/*****************************************************************************
simple_bus_master_blocking.h : The master using the blocking BUS interface.
Original Author: Ric Hilderink, Synopsys, Inc., 2001-10-11
*****************************************************************************/
/*****************************************************************************
MODIFICATION LOG - modifiers, enter your name, affiliation, date and
changes you are making here.
Name, Affiliation, Date:
Description of Modification:
*****************************************************************************/
#ifndef __simple_bus_master_blocking_h
#define __simple_bus_master_blocking_h
#include <systemc.h>
#include "simple_bus_types.h"
#include "simple_bus_blocking_if.h"
SC_MODULE(simple_bus_master_blocking)
{
// ports
sc_in_clk clock;
sc_port<simple_bus_blocking_if> bus_port;
// constructor
simple_bus_master_blocking(sc_module_name name_
, unsigned int unique_priority
, unsigned int address
, bool lock
, int timeout)
: sc_module(name_)
, m_unique_priority(unique_priority)
, m_address(address)
, m_lock(lock)
, m_timeout(timeout)
{
// process declaration
SC_THREAD(main_action);
sensitive << clock.pos();
}
// process
void main_action();
private:
unsigned int m_unique_priority;
unsigned int m_address;
bool m_lock;
int m_timeout;
}; // end class simple_bus_master_blocking
#endif
|
/**
* @license MIT
* @brief Private type definitions for Huffman coding.
*/
#ifndef HUFFMAN_CODING_PRIV_TYPES_H
#define HUFFMAN_CODING_PRIV_TYPES_H
///////////////////////////////////////////////////////////////////////////////
#include <stdint.h>
#include <systemc.h>
#include "huffman_coding_public_types.h"
#include "huffman_coding_priv_config.h"
///////////////////////////////////////////////////////////////////////////////
namespace huffman_coding {
typedef sc_uint<freq_width> freq_t;
typedef sc_uint<freq_width> node_t;
typedef sc_uint<dep_width> dep_t;
typedef sc_uint<len_width> len_t;
typedef sc_uint<len_freq_width> len_freq_t;
typedef sc_uint<code_width> code_t;
}
///////////////////////////////////////////////////////////////////////////////
#endif // HUFFMAN_CODING_PRIV_TYPES_H
|
/**
#define meta ...
prInt32f("%s\n", meta);
**/
/*
All rights reserved to Alireza Poshtkohi (c) 1999-2023.
Email: [email protected]
Website: http://www.poshtkohi.info
*/
#ifndef __bus_controller_sc__h__
#define __bus_controller_sc__h__
#include <systemc.h>
#include "globals.h"
//----------------------------------------------------
class bus_controller : public sc_module
{
/*---------------------fields-----------------*/
public: sc_in<bool> clock;
public: sc_in<bool> re_cores[NumOfCores]; // Cores Read Enable
public: sc_in<bool> we_cores[NumOfCores]; // Cores Write Enable
public: sc_in<bool> cs_cores[NumOfCores]; // Cores Chip Eelect
public: sc_in<sc_int<64> > data_in_mem;
public: sc_in<sc_uint<64> > address_cores[NumOfCores];
public: sc_in<sc_int<64> > data_in_cores[NumOfCores];
public: sc_out<sc_int<64> > data_out_cores[NumOfCores];
public: sc_out<bool> re_mem; // Memory Read Enable
public: sc_out<bool> we_mem; // Memory Write Enable
public: sc_out<bool> cs_mem; // Memory Chip Select
public: sc_out<sc_uint<64> > address_mem;
public: sc_out<sc_int<64> > data_out_mem;
//private: const int remote_access_latency = MemoryAccessLatency;
/*---------------------methods----------------*/
SC_HAS_PROCESS(bus_controller);
public: bus_controller(sc_module_name name_);
public: ~bus_controller();
private: void bus_controller_proc();
private: void print_ports(int i);
/*--------------------------------------------*/
};
//----------------------------------------------------
#endif
|
#include <systemc.h>
#include <ahb_master_if.h>
using namespace std;
class fake_master: public sc_module, public ahb_master_if
{
public:
sc_in_clk clk;
SC_HAS_PROCESS(fake_master);
fake_master(sc_module_name name);
~fake_master();
protected:
void run();
bool bus_read(uint32_t* data, uint32_t addr, uint32_t length);
bool bus_write(uint32_t data, uint32_t addr, uint32_t length);
};
|
/*
* fetch.h
*
* Created on: 4 de mai de 2017
* Author: drcfts
*/
#ifndef FETCH_H_
#define FETCH_H_
#include <systemc.h>
#include "shared.h"
#include "mem_if.h"
#include "breg_if.h"
#define RASTREIA_PC
//Criar uma classe memoria que implementa interface com metodos de leitura
//e escrita para ser acessado (por ponteiro) pelos metodos fetch
//e execute
SC_MODULE(fetch){
sc_port <mem_if> p_mem;
sc_port <breg_if> p_breg;
sc_fifo_in < contexto*> execute_fetch;
sc_fifo_out < contexto* > fetch_decode;
void fetch_method(){
while(true){
recebimento = execute_fetch.read();
escrita = recebimento;
PC = (p_breg->read(31));
#ifdef RASTREIA_PC
cout << "PC = " << PC << endl;
#endif
escrita->ri = p_mem->read(PC);
//Registrador 31 = PC
p_breg->write(31, PC +1);
//Instrucao que nao faz sentido lw $0, $0
//Interrompe execucao
if(escrita->ri == 0){
p_breg->dump_breg();
sc_stop();
exit(0);
} //if
fetch_decode.write(escrita);
} // while
}
SC_CTOR(fetch){
recebimento = new contexto();
escrita = new contexto();
SC_THREAD(fetch_method);
}
private:
contexto *escrita;
contexto *recebimento;
uint32_t PC;
};
#endif /* FETCH_H_ */
|
#ifndef IMG_ROUTER_CPP
#define IMG_ROUTER_CPP
// #include "tlm_transaction.cpp"
#include "transaction_memory_manager.cpp"
#include <systemc.h>
using namespace sc_core;
using namespace sc_dt;
using namespace std;
#include <tlm.h>
#include <tlm_utils/simple_initiator_socket.h>
#include <tlm_utils/simple_target_socket.h>
#include <tlm_utils/peq_with_cb_and_phase.h>
#include <ostream>
#include "common_func.hpp"
#include "img_generic_extension.hpp"
//#include "tlm_queue.cpp"
#include "important_defines.hpp"
//const char* tlm_enum_names[] = {"TLM_ACCEPTED", "TLM_UPDATED", "TLM_COMPLETED"};
struct tlm_item{
tlm::tlm_generic_payload *transaction;
tlm::tlm_phase phase;
sc_time delay;
tlm_item(tlm::tlm_generic_payload *transaction = 0, tlm::tlm_phase phase = tlm::BEGIN_REQ, sc_time delay = sc_time(0, SC_NS)){}
tlm_item& operator=(const tlm_item& rhs){
transaction = rhs.transaction;
phase = rhs.phase;
delay = rhs.delay;
return *this;
}
bool operator==(const tlm_item& rhs){
return transaction == rhs.transaction && phase == rhs.phase && delay == rhs.delay;
}
friend std::ostream& operator<<(std::ostream& os, const tlm_item& val) {
os << "Transaction Pointer = " << val.transaction << "; phase = " << val.phase << "; delay = " << val.delay << std::endl;
return os;
}
};
// inline void sc_trace(sc_trace_file*& f, const tlm_item& val, std::string name) {
// sc_trace(f, val.transaction, name + ".transaction");
// sc_trace(f, val.phase, name + ".phase");
// sc_trace(f, val.delay, name + ".delay");
// }
// Initiator module generating generic payload transactions
template<unsigned int N_TARGETS>
struct img_router: sc_module
{
// TLM2.0 Socket
tlm_utils::simple_target_socket<img_router> target_socket;
tlm_utils::simple_initiator_socket<img_router>* initiator_socket[N_TARGETS];
//Memory Manager for transaction memory allocation
mm memory_manager;
//Payload event queue with callback and phase
tlm_utils::peq_with_cb_and_phase<img_router> bw_m_peq; //For initiator access
tlm_utils::peq_with_cb_and_phase<img_router> fw_m_peq; //For target access
//Delay
sc_time bw_delay;
sc_time fw_delay;
//TLM Items queue
sc_fifo<tlm_item> fw_fifo;
sc_fifo<tlm_item> bw_fifo;
//DEBUG
unsigned int transaction_in_fw_path_id = 0;
unsigned int transaction_in_bw_path_id = 0;
bool use_prints;
//Constructor
SC_CTOR(img_router)
: target_socket("socket"), bw_m_peq(this, &img_router::bw_peq_cb), fw_m_peq(this, &img_router::fw_peq_cb), fw_fifo(10), bw_fifo(2), use_prints(true) // Construct and name socket
{
// Register callbacks for incoming interface method calls
target_socket.register_nb_transport_fw(this, &img_router::nb_transport_fw);
for (unsigned int i = 0; i < N_TARGETS; i++) {
char txt[20];
sprintf(txt, "socket_%d", i);
initiator_socket[i] = new tlm_utils::simple_initiator_socket<img_router>(txt);
(*initiator_socket[i]).register_nb_transport_bw(this, &img_router::nb_transport_bw);
}
SC_THREAD(fw_thread);
SC_THREAD(bw_thread);
#ifdef DISABLE_ROUTER_DEBUG
this->use_prints = false;
#endif //DISABLE_ROUTER_DEBUG
checkprintenable(use_prints);
}
//Address Decoding
#define IMG_FILTER_INITIATOR_ID 0
#define IMG_SOBEL_INITIATOR_ID 1
#define IMG_MEMORY_INITIATOR_ID 2
#define IMG_ETHERNET_INITIATOR_ID 3
#define IMG_VGA_INITIATOR_ID 4
#define INVALID_INITIATOR_ID 5
unsigned int decode_address (sc_dt::uint64 address)
{
switch(address) {
// To Filter
case IMG_FILTER_KERNEL_ADDRESS_LO: {
dbgmodprint(use_prints, "Decoded address %016llX corresponds to Filter module.", address);
return IMG_FILTER_INITIATOR_ID;
}
// To/from Sobel
case SOBEL_INPUT_0_ADDRESS_LO:
case SOBEL_INPUT_1_ADDRESS_LO:
case SOBEL_OUTPUT_ADDRESS_LO: {
dbgmodprint(use_prints, "Decoded address %016llX corresponds to Sobel module.", address);
return IMG_SOBEL_INITIATOR_ID;
}
case IMG_OUTPUT_ADDRESS_LO ... (IMG_OUTPUT_ADDRESS_HI - 1):
case IMG_OUTPUT_SIZE_ADDRESS_LO:
case IMG_OUTPUT_DONE_ADDRESS_LO:
case IMG_OUTPUT_STATUS_ADDRESS_LO:
{
dbgmodprint(use_prints, "Decoded address %016llX corresponds to Ethernet module.", address);
return IMG_ETHERNET_INITIATOR_ID;
}
// To/from Input Image
case IMG_INPUT_ADDRESS_LO ... (IMG_INPUT_ADDRESS_HI - 1):
case IMG_INPUT_START_ADDRESS_LO:
case IMG_INPUT_DONE_ADDRESS_LO:
{
dbgmodprint(use_prints, "Decoded address %016llX corresponds to VGA module.", address);
return IMG_VGA_INITIATOR_ID;
}
// To/From Memory Valid addresses
case MEMORY_ADDRESS_LO ... (MEMORY_ADDRESS_HI - 1) : {
dbgmodprint(use_prints, "Decoded address %016llX corresponds to Memory.", address);
return IMG_MEMORY_INITIATOR_ID;
}
default: {
dbgmodprint(true, "[ERROR] Decoding invalid address %016llX.", address);
SC_REPORT_FATAL("[IMG ROUTER]", "Received address is invalid, does not match any hardware block");
return INVALID_INITIATOR_ID;
}
}
}
// TLM2 backward path non-blocking transport method
virtual tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload& trans,
tlm::tlm_phase& phase, sc_time& delay )
{
img_generic_extension* img_ext;
//Call event queue
tlm_item item;
item.transaction = &trans;
item.phase = phase;
item.delay = delay;
trans.get_extension(img_ext);
if (bw_fifo.num_free() == 0) {
dbgmodprint(use_prints, "[BW_FIFO] FIFO is FULL. Waiting...");
wait(bw_fifo.data_read_event());
}
bw_fifo.nb_write(item);
wait(bw_fifo.data_written_event());
dbgmodprint(use_prints, "[BW_FIFO] Pushed transaction #%0d", img_ext->transaction_number);
return tlm::TLM_ACCEPTED;
}
// TLM2 forward path non-blocking transport method
virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& trans,
tlm::tlm_phase& phase, sc_time& delay )
{
img_generic_extension* img_ext;
//Call event queue
tlm_item item;
item.transaction = &trans;
item.phase = phase;
item.delay = delay;
trans.get_extension(img_ext);
if (fw_fifo.num_free() == 0) {
dbgmodprint(use_prints, "[FW_FIFO] FIFO is FULL. Waiting...");
wait(fw_fifo.data_read_event());
}
fw_fifo.nb_write(item);
wait(fw_fifo.data_written_event());
dbgmodprint(use_prints, "[FW_FIFO] Pushed transaction #%0d", img_ext->transaction_number);
return tlm::TLM_ACCEPTED;
}
void fw_thread() {
while(true) {
img_generic_extension* img_ext;
tlm::tlm_generic_payload* trans_ptr = new tlm::tlm_generic_payload;
tlm::tlm_phase phase;
sc_time delay;
tlm_item item;
if (fw_fifo.num_available() == 0) {
wait(fw_fifo.data_written_event());
}
fw_fifo.nb_read(item);
wait(fw_fifo.data_read_event());
trans_ptr = item.transaction;
phase = item.phase;
delay = item.delay;
(*trans_ptr).get_extension(img_ext);
dbgmodprint(use_prints, "[FW_FIFO] Popped transaction #%0d", img_ext->transaction_number);
fw_m_peq.notify(*trans_ptr, phase, delay);
wait(fw_delay);
}
}
void bw_thread() {
while(true) {
img_generic_extension* img_ext;
tlm::tlm_generic_payload* trans_ptr = new tlm::tlm_generic_payload;
tlm::tlm_phase phase;
sc_time delay;
tlm_item item;
if (bw_fifo.num_available() == 0) {
wait(bw_fifo.data_written_event());
}
bw_fifo.nb_read(item);
wait(bw_fifo.data_read_event());
trans_ptr = item.transaction;
phase = item.phase;
delay = item.delay;
(*trans_ptr).get_extension(img_ext);
dbgmodprint(use_prints, "[BW_FIFO] Popped transaction #%0d", img_ext->transaction_number);
bw_m_peq.notify(*trans_ptr, phase, delay);
wait(bw_delay);
}
}
//Payload event and queue callback to handle transactions received from target
void bw_peq_cb(tlm::tlm_generic_payload& trans, const tlm::tlm_phase& phase)
{
img_generic_extension* img_ext;
trans.get_extension(img_ext);
tlm::tlm_phase local_phase = phase;
sc_dt::uint64 address = trans.get_address();
this->transaction_in_bw_path_id = img_ext->transaction_number;
dbgmodprint(use_prints, "Received transaction #%0d with address %016llX in backward path. Redirecting transaction to CPU", img_ext->transaction_number, address);
target_socket->nb_transport_bw(trans, local_phase, this->bw_delay);
}
void fw_peq_cb(tlm::tlm_generic_payload& trans, const tlm::tlm_phase& phase)
{
img_generic_extension* img_ext;
trans.get_extension(img_ext);
tlm::tlm_phase local_phase = phase;
sc_dt::uint64 address = trans.get_address();
this->transaction_in_fw_path_id = img_ext->transaction_number;
unsigned int initiator_id = decode_address(address);
dbgmodprint(use_prints, "Received transaction #%0d with address %016llX in forward path. Redirecting transaction through initiator %d", img_ext->transaction_number, address, initiator_id);
(*initiator_socket[initiator_id])->nb_transport_fw(trans, local_phase, this->fw_delay);
}
void set_delays(sc_time fw_delay, sc_time bw_delay)
{
this->bw_delay = bw_delay;
this->fw_delay = fw_delay;
}
} ;
#endif
|
%(
## icglue - systemC module template
array set mod_data [module_to_arraylist $obj_id]
proc sc_type {} {
upvar port(size) size port(direction) dir
set type "< sc_logic > "
if {$size > 1} {
set type "< sc_lv<[format "%3d" ${size}]> >"
}
switch $dir {
input {return "sc_in $type"}
output {return "sc_out $type"}
inout {return "sc_inout $type"}
}
log -warn "Can't translate type $type to systemC."
}
%)
/* ICGLUE GENERATED FILE - manual changes out of prepared *icglue keep begin/end* blocks will be overwritten */
#ifndef __[string toupper ${mod_data(name)}]_H__
#define __[string toupper ${mod_data(name)}]_H__
[pop_keep_block_content keep_block_data "keep" "include" {} "
#include <systemc.h>
"]
%(
set sc_module {}
lappend sc_module "class $mod_data(name) : public sc_module {"
lappend sc_module " public:"
lappend sc_module " SC_HAS_PROCESS (${mod_data(name)});"
lappend sc_module " ${mod_data(name)} (::sc_core::sc_module_name name);"
set sc_module [join $sc_module "\n"]
%)
[pop_keep_block_content keep_block_data "keep" "sc_module(${mod_data(name)})" {} "
$sc_module
"]
// interface declaration
% foreach_array port $mod_data(ports) {
[sc_type] ${port(name)};
% }
// additional declaration
[pop_keep_block_content keep_block_data "keep" "class-decl" {} "
private:
//TODO: add your custom declarations here
//e.g.
//void testcase_control ();
//void testcase ();
//void onEvent ();
//sc_event_queue eq;
//void onClock();
"]
};
[pop_keep_block_content keep_block_data "keep" "header-decl"]
%(
## orphaned keep-blocks
set rem_keeps [remaining_keep_block_contents $keep_block_data]
if {[llength $rem_keeps] > 0} {
log -warn "There are orphaned keep blocks in the verilog source - they will be appended to the code."
%)
#if 0
/* orphaned icglue keep blocks ...
* TODO: remove if unnecessary or reintegrate
*/
% foreach b $rem_keeps {
$b
%}
#endif
%}
#endif
|
#ifndef IMG_RECEIVER_TLM_HPP
#define IMG_RECEIVER_TLM_HPP
#include <systemc.h>
#include "img_receiver.hpp"
#include "../src/img_target.cpp"
#include "address_map.hpp"
struct img_receiver_tlm: public img_receiver, public img_target
{
SC_CTOR(img_receiver_tlm): img_receiver(img_receiver::name()), img_target(img_target::name()) {
set_mem_attributes(IMG_INPUT_ADDRESS_LO, IMG_INPUT_SIZE);
}
//Override do_when_transaction functions
virtual void do_when_read_transaction(unsigned char*& data, unsigned int data_length, sc_dt::uint64 address);
virtual void do_when_write_transaction(unsigned char*& data, unsigned int data_length, sc_dt::uint64 address);
};
#endif // IMG_RECEIVER_TLM_HPP
|
#ifndef GEMMDRIVER_H
#define GEMMDRIVER_H
#define FULLSIM
#include <sys/time.h>
#include <fstream>
#include <iostream>
#include <iomanip>
#include <cstdlib>
#include <systemc.h>
#ifdef FULLSIM
#include "../acc_comps/acc.h"
#else
#include "acc.h"
#endif
SC_MODULE(GemmDriver) {
sc_in<bool> clock;
sc_in <bool> reset;
sc_fifo_in<DATA> dout1;
sc_fifo_in<DATA> dout2;
sc_fifo_in<DATA> dout3;
sc_fifo_in<DATA> dout4;
sc_fifo_out<DATA> din1;
sc_fifo_out<DATA> din2;
sc_fifo_out<DATA> din3;
sc_fifo_out<DATA> din4;
bool sent;
bool retval;
//States
int states[9];
sc_signal<int> sourceS;
sc_signal<int> sinkS;
sc_in<int> inS;
sc_in<int> outS;
sc_in<int> w1S;
sc_in<int> w2S;
sc_in<int> w3S;
sc_in<int> w4S;
sc_in<int> schS;
sc_in<int> p1S;
sc_in<int> read_cycle_count;
sc_in<int> process_cycle_count;
sc_in<int> gemm_1_idle;
sc_in<int> gemm_2_idle;
sc_in<int> gemm_3_idle;
sc_in<int> gemm_4_idle;
sc_in<int> gemm_1_write;
sc_in<int> gemm_2_write;
sc_in<int> gemm_3_write;
sc_in<int> gemm_4_write;
sc_in<int> gemm_1;
sc_in<int> gemm_2;
sc_in<int> gemm_3;
sc_in<int> gemm_4;
sc_in<int> wstall_1;
sc_in<int> wstall_2;
sc_in<int> wstall_3;
sc_in<int> wstall_4;
sc_in<int> rmax;
sc_in<int> lmax;
int p_cycles= 0;
int waiting= 0;
int loading= 0;
int g1_idle= 0;
int g2_idle= 0;
int g3_idle= 0;
int g4_idle= 0;
int g1_write= 0;
int g2_write= 0;
int g3_write= 0;
int g4_write= 0;
int g1_gemm= 0;
int g2_gemm= 0;
int g3_gemm= 0;
int g4_gemm= 0;
int wstall1=0;
int wstall2=0;
int wstall3=0;
int wstall4=0;
int r_max=0;
int l_max=0;
void Source();
void Sink();
void Status();
void read_in();
void read_out();
SC_HAS_PROCESS(GemmDriver);
// Parameters for the DUT
GemmDriver(sc_module_name name_) :sc_module(name_) { // @suppress("Class members should be properly initialized")
SC_CTHREAD(Source, clock.pos());
reset_signal_is(reset,true);
SC_CTHREAD(Sink, clock.pos());
reset_signal_is(reset,true);
SC_CTHREAD(Status, clock.neg());
reset_signal_is(reset,true);
}
int inl0;
int inl1;
int inl2;
int inl3;
int in0[563840];
int in1[563840];
int in2[563840];
int in3[563840];
int out0[554800];
int out1[554800];
int out2[554800];
int out3[554800];
};
#endif /* GEMMDRIVER_H */
|
#ifndef VTA_H
#define VTA_H
#include <systemc.h>
#include "AXI4_if.h"
#include <iostream>
using namespace std;
#ifndef __SYNTHESIS__
// #define DWAIT(x) wait(x)
#define DWAIT() wait(1)
#define DWAIT(x) wait(1)
#define DPROF(x) x
#else
#define DWAIT(x)
#define DPROF(x)
#endif
#ifndef __SYNTHESIS__
//#define VLOG(X) cout X
#define VLOG(X)
#else
#define VLOG(X)
#endif
// typedef sc_int<64> inp_bt;
// typedef sc_int<64> wgt_bt;
// typedef sc_int<64> acc_bt;
typedef unsigned long long inp_bt;
typedef unsigned long long wgt_bt;
//typedef sc_int<32> out_bt;
typedef int out_bt;
typedef unsigned long long acc_bt;
//typedef sc_int<64> acc_bt;
typedef sc_int<8> dat_t;
typedef sc_int<32> acc_t;
#define INP_ACCESS 8
#define WGT_ACCESS 8
#define ACC_ACCESS 2
#define INP_DEPTH 4096
#define WGT_DEPTH 8192
#define ACC_DEPTH 8192
//#define INP_DEPTH 8192
//#define WGT_DEPTH 8192
//#define ACC_DEPTH 2048
#define INP_SIZE (INP_DEPTH * INP_ACCESS * INP_MEMS)
#define WGT_SIZE (WGT_DEPTH * WGT_ACCESS * WGT_MEMS)
#define ACC_SIZE (ACC_DEPTH * ACC_ACCESS * ACC_MEMS)
#define SC_INP_ELEM_BYTES_RATIO 4
#define MAX8 127
#define MIN8 -128
#define MAX32 2147483647
#define MIN32 -2147483648
#define DIVMAX 2147483648
#define POS 1073741824
#define NEG -1073741823
struct opcode {
unsigned long long p1;
unsigned long long p2;
int dstride;
int x_size;
int y_size;
int doffset;
int op;
opcode(sc_uint<64> _p1, sc_uint<64> _p2) {
p1 = _p1;
p2 = _p2;
dstride = _p1.range(63, 32);
x_size = _p1.range(31, 16);
y_size = _p1.range(15, 0);
doffset = _p2.range(63, 32);
op = _p2.range(31, 0);
}
};
#define ACCNAME FC_ACC
SC_MODULE(ACCNAME) {
sc_in<bool> clock;
sc_in<bool> reset;
sc_in<unsigned int> start_acc;
sc_out<unsigned int> done_acc;
sc_in<bool> reset_acc;
sc_in<unsigned int> insn_count;
sc_in<unsigned int> insn_addr;
sc_in<unsigned int> input_addr;
sc_in<unsigned int> weight_addr;
sc_in<unsigned int> bias_addr;
sc_in<unsigned int> output_addr;
sc_in<int> crf;
sc_in<int> crx;
sc_in<int> ra;
sc_in<int> depth;
AXI4M_bus_port<unsigned long long> insn_port;
AXI4M_bus_port<unsigned long long> input_port;
AXI4M_bus_port<unsigned long long> weight_port;
AXI4M_bus_port<unsigned long long> bias_port;
AXI4M_bus_port<unsigned int> out_port;
// Instantiate memories
#ifndef __SYNTHESIS__
wgt_bt* wgt_mem1 = new wgt_bt[WGT_DEPTH];
wgt_bt* wgt_mem2 = new wgt_bt[WGT_DEPTH];
wgt_bt* wgt_mem3 = new wgt_bt[WGT_DEPTH];
wgt_bt* wgt_mem4 = new wgt_bt[WGT_DEPTH];
inp_bt* inp_mem1 = new inp_bt[INP_DEPTH];
inp_bt* inp_mem2 = new inp_bt[INP_DEPTH];
inp_bt* inp_mem3 = new inp_bt[INP_DEPTH];
inp_bt* inp_mem4 = new inp_bt[INP_DEPTH];
acc_bt* acc_mem = new acc_bt[ACC_DEPTH];
#else
wgt_bt wgt_mem1[WGT_DEPTH];
wgt_bt wgt_mem2[WGT_DEPTH];
wgt_bt wgt_mem3[WGT_DEPTH];
wgt_bt wgt_mem4[WGT_DEPTH];
inp_bt inp_mem1[INP_DEPTH];
inp_bt inp_mem2[INP_DEPTH];
inp_bt inp_mem3[INP_DEPTH];
inp_bt inp_mem4[INP_DEPTH];
acc_bt acc_mem[ACC_DEPTH];
#endif
out_bt out_mem[4][4];
#ifndef __SYNTHESIS__
sc_signal<bool, SC_MANY_WRITERS> wgt_load;
sc_signal<bool, SC_MANY_WRITERS> inp_load;
sc_signal<bool, SC_MANY_WRITERS> bias_load;
sc_signal<bool, SC_MANY_WRITERS> gemm_wait;
sc_signal<bool, SC_MANY_WRITERS> schedule;
sc_signal<bool, SC_MANY_WRITERS> storing;
#else
sc_signal<bool> wgt_load;
sc_signal<bool> inp_load;
sc_signal<bool> bias_load;
sc_signal<bool> gemm_wait;
sc_signal<bool> schedule;
sc_signal<bool> storing;
#endif
sc_signal<bool> loading;
sc_uint<64> wgt_insn1;
sc_uint<64> wgt_insn2;
sc_uint<64> inp_insn1;
sc_uint<64> inp_insn2;
sc_uint<64> bias_insn1;
sc_uint<64> bias_insn2;
// sc_signal<unsigned int> bias_load_doffset;
// sc_signal<unsigned int> bias_load_dstride;
// sc_signal<unsigned int> bias_minc;
// sc_signal<unsigned int> bias_load_length;
// Scheduler
sc_signal<unsigned int> wgt_block;
sc_signal<unsigned int> inp_block;
sc_signal<unsigned int> depth_val;
// GEMM Unit signals
sc_signal<unsigned int> wp_val;
sc_signal<unsigned int> ip_val;
// Store Unit signals
sc_signal<unsigned int> store_doffset;
sc_signal<unsigned int> store_dstride;
sc_signal<unsigned int> m_off;
sc_signal<unsigned int> n_off;
sc_signal<bool> fetch_resetted;
int start_count;
int done_count;
int ra_val;
int crf_val;
int crx_val;
bool resetted;
sc_int<64> pl;
sc_int<32> pr;
sc_int<32> msk;
sc_int<32> sm;
// // Profiling variable
// ClockCycles* per_batch_cycles = new ClockCycles("per_batch_cycles", true);
// std::vector<Metric*> profiling_vars = {per_batch_cycles};
// int layer = 0;
// int pc = 0;
sc_int<32> mul_s8(sc_int<8>,sc_int<8>);
int Quantised_Multiplier(int, int, int);
void fetch();
void load_weights();
void load_inputs();
void load_bias();
void scheduler();
void compute();
void store();
void tracker();
SC_HAS_PROCESS(ACCNAME);
ACCNAME(sc_module_name name_) : sc_module(name_), // @suppress("Class members should be properly initialized")
insn_port("insn_port"),
input_port("input_port"),
weight_port("weight_port"),
bias_port("bias_port"),
out_port("out_port")
{
SC_CTHREAD(fetch, clock.pos());
reset_signal_is(reset, true);
SC_CTHREAD(load_weights, clock.pos());
reset_signal_is(reset, true);
SC_CTHREAD(load_inputs, clock.pos());
reset_signal_is(reset, true);
SC_CTHREAD(load_bias, clock.pos());
reset_signal_is(reset, true);
SC_CTHREAD(compute, clock.pos());
reset_signal_is(reset, true);
SC_CTHREAD(store, clock.pos());
reset_signal_is(reset, true);
SC_CTHREAD(scheduler, clock.pos());
reset_signal_is(reset, true);
// SC_CTHREAD(tracker, clock.pos());
// reset_signal_is(reset, true);
#pragma HLS RESET variable = reset
}
};
#endif // VTA_H
|
/*
* Created on: 21. jun. 2019
* Author: Jonathan Horsted Schougaard
*/
#pragma once
#define SC_INCLUDE_FX
#include <cmath>
#include <systemc.h>
#ifndef __SYNTHESIS__
#include <algorithm>
#include <functional>
#include <memory>
#include <vector>
#endif
//#include <type_traits>
// https://gcc.gnu.org/onlinedocs/cpp/Pragmas.html
#define DO_PRAGMA(x) _Pragma(#x)
// https://stackoverflow.com/questions/19666142/why-is-a-level-of-indirection-needed-for-this-concatenation-macro
// @DaoWen
#define JOIN(symbol1, symbol2) _DO_JOIN(symbol1, symbol2)
#define _DO_JOIN(symbol1, symbol2) symbol1##symbol2
#define str(s) #s
#define xstr(s) str(s)
#define EXPAND(x) x
#define FIRST(first, ...) first
#define REMOVE_FIRST(first, ...) __VA_ARGS__
#define dummy_end() \
do { \
} while (false)
#ifdef HLS_APPROX_TIME
#define wait_approx() wait()
#define wait_approx_for(n) \
for (int __wafi = 0; __wafi < n; __wafi++) { \
wait_approx(); \
} \
dummy_end()
#else
#define wait_approx()
#define wait_approx_for(n)
#endif
#define hls_pipeline(_II) \
DO_PRAGMA(HLS pipeline II = _II); \
wait_approx_for(_II)
#define hls_pipeline_raw(_II) DO_PRAGMA(HLS pipeline II = _II)
#define hls_unroll() DO_PRAGMA(HLS unroll)
#define hls_unroll_factor(_factor) DO_PRAGMA(HLS unroll factor = _factor)
// wait_approx_for(_factor / N)
#define hls_loop() wait_approx()
#define hls_array_partition(_variable, param) DO_PRAGMA(HLS array_partition variable = _variable param)
#define hls_array_partition_complete(_variable) hls_array_partition(_variable, complete)
#define SC_MODULE_CLK_RESET_SIGNAL \
sc_in<bool> clk; \
sc_in<bool> reset
#define SC_MODULE_LINK(module) \
module.reset(reset); \
module.clk(clk)
#define SC_CTOR_DEFAULT(user_module_name) \
typedef user_module_name SC_CURRENT_USER_MODULE; \
inline explicit user_module_name( \
::sc_core::sc_module_name) //=sc_gen_unique_name(#user_module_name "_u" xstr(__COUNTER__) ))
#define SC_CTOR_DEFAULT_PARAM(user_module_name, ...) \
typedef user_module_name SC_CURRENT_USER_MODULE; \
inline explicit user_module_name( \
__VA_ARGS__, ::sc_core::sc_module_name) //=sc_gen_unique_name(#user_module_name "_u" xstr(__COUNTER__) ) )
#define SC_CTOR_TEMPLATE(user_module_name) \
typedef user_module_name SC_CURRENT_USER_MODULE; \
inline explicit user_module_name( \
::sc_core::sc_module_name) //=sc_gen_unique_name(#user_module_name "_u" xstr(__COUNTER__) ))
#define SC_CTOR_TEMPLATE_PARAM(user_module_name, ...) \
typedef user_module_name SC_CURRENT_USER_MODULE; \
inline explicit user_module_name( \
__VA_ARGS__, ::sc_core::sc_module_name) //=sc_gen_unique_name(#user_module_name "_u" xstr(__COUNTER__) ) )
#define IF_SC_FIFO_NB_READ_FLUSH(fifo_in_port, data) \
if (!fifo_in_port.nb_read(data)) { \
wait(); \
} else
#define IF_SC_FIFO_NB_READ_FLUSH_SKIP(fifo_in_port, data, skip_read) \
bool blob = false; \
if (!(skip_read)) { \
blob = !fifo_in_port.nb_read(data); \
} \
if (blob) { \
wait(); \
} else
#define SC_INST(module_name) module_name(#module_name)
#ifdef __SYNTHESIS__TEST
#define SC_TRACE_ADD(port) sc_trace(trace, port, std::string("(" #port ").") + port.name())
#define SC_TRACE_ADD_MODULE(module) module.trace(trace);
#define SC_TRACE_ADD_MODULE_FIFO(module) \
module.trace(trace); \
sc_trace_fifo::add(trace);
#else
#define SC_TRACE_ADD(port)
#define SC_TRACE_ADD_MODULE(module)
#define SC_TRACE_ADD_MODULE_FIFO(module)
#endif
#ifndef HLS_DEBUG_LEVEL
#define HLS_DEBUG_LEVEL 999
#endif
#ifndef __SYNTHESIS__
#define HLS_DEBUG(LEVEL, interval, max_N_times, ...) \
if (LEVEL <= HLS_DEBUG_LEVEL) { \
static int __value__HLS_DEBUG_INTERVAL__ = 0; \
__value__HLS_DEBUG_INTERVAL__ = 0; \
if (__value__HLS_DEBUG_INTERVAL__ % interval == 0 && \
(max_N_times == 0 || __value__HLS_DEBUG_INTERVAL__ < max_N_times)) { \
printf("[ "); \
sc_time_stamp().print(); \
printf(" ] - "); \
printf("(func: %s) %s:%d: (%s)", __func__, __FILE__, __LINE__, this->name()); \
printf(__VA_ARGS__); \
printf("\r\n"); \
fflush(stdout); \
} \
__value__HLS_DEBUG_INTERVAL__++; \
}
#define HLS_DEBUG_EXEC(func) func
#define HLS_DEBUG_SWITCH_EXEC(func_debug, func_synth) func_debug
#else
#define HLS_DEBUG(...)
#define HLS_DEBUG_EXEC(func)
#define HLS_DEBUG_SWITCH_EXEC(func_debug, func_synth) func_synth
#endif
#define debug_cout \
std::cout << "[ " << sc_time_stamp().to_string() << " ] - (func: " << __func__ << ") " << __FILE__ << ":" \
<< __LINE__ << ": (" << this->name() << ")"
//#define HLS_DEBUG(...)
namespace hwcore {
namespace hf {
template <class T> void create_dummy_signal(sc_out<T> &port) {
sc_signal<T> *ptr = new sc_signal<T>();
port(*ptr);
}
#define sc_set_port_optional(port) HLS_DEBUG_EXEC(hwcore::hf::create_dummy_signal(port))
#ifndef __SYNTHESIS__
/*
class sc_port_optional {
static std::vector<std::function<void()> > &getVec() {
static std::vector<std::function<void()> > exec;
return exec;
}
public:
template <class T> void set_port(sc_out<T> &port) {
getVec.push_back([&]() { port });
}
void doWork() {
auto vec = getVec();
for (auto itr : vec) {
itr();
}
}
};*/
class sc_trace_fifo {
public:
class sc_fifo_wrap_base {
public:
virtual ~sc_fifo_wrap_base() {}
virtual int num_available() const = 0;
virtual int num_free() const = 0;
virtual void print(::std::ostream & = ::std::cout) const = 0;
virtual void dump(::std::ostream & = ::std::cout) const = 0;
virtual const char *name() const = 0;
virtual sc_port_base *getReader() = 0;
virtual sc_port_base *getWriter() = 0;
};
template <class fifo> class sc_fifo_wrap : public virtual sc_fifo_wrap_base {
fifo *mRef;
public:
sc_fifo_wrap(fifo &ref) : mRef(&ref) {}
virtual ~sc_fifo_wrap() {}
virtual int num_available() const { return mRef->num_available(); };
virtual int num_free() const { return mRef->num_free(); };
virtual void print(::std::ostream &os = ::std::cout) const { mRef->print(os); };
virtual void dump(::std::ostream &os = ::std::cout) const { mRef->dump(os); };
virtual const char *name() const { return mRef->name(); }
virtual sc_port_base *getReader() { return mRef->getReader(); };
virtual sc_port_base *getWriter() { return mRef->getWriter(); };
};
static std::vector<std::shared_ptr<sc_fifo_wrap_base> > &getList() {
static std::vector<std::shared_ptr<sc_fifo_wrap_base> > list;
return list;
}
template <class fifo> static void add(fifo &f) { getList().push_back(std::make_shared<sc_fifo_wrap<fifo> >(f)); }
};
template <class T> class sc_fifo_with_trace : public sc_fifo<T> {
public:
explicit sc_fifo_with_trace(int size_ = 16) : sc_fifo<T>(size_) { sc_trace_fifo::add(*this); }
explicit sc_fifo_with_trace(const char *name_, int size_ = 16) : sc_fifo<T>(name_, size_) {
sc_trace_fifo::add(*this);
}
sc_port_base *getReader() { return sc_fifo<T>::m_reader; }
sc_port_base *getWriter() { return sc_fifo<T>::m_writer; }
virtual ~sc_fifo_with_trace() {}
};
#endif
template <unsigned N, class Linker> //, template<unsigned,typename,typename> class helper>
struct unroll {
template <typename F> inline static void link(F &f) {
// helper<N-1,F,T>::link(f,t);
Linker::link(f, N - 1);
unroll<N - 1, Linker>::link(f);
}
};
template <class Linker> // template<unsigned,typename,typename> class helper>
struct unroll<0, Linker> {
template <typename F> inline static void link(F &f) {}
};
/*template <unsigned N>//, template<unsigned,typename,typename> class helper>
struct linkArray {
template <typename T1, typename T2> inline static void link(F & f) {
//helper<N-1,F,T>::link(f,t);
Linker::link(f,N-1);
unroll<N-1,Linker>::link(f);
}
};
template <class Linker>//template<unsigned,typename,typename> class helper>
struct unroll<0,Linker> {
template <typename F> inline static void link(F & f) {
}
};*/
template <class T> struct sc_wrap {
T _module;
inline explicit sc_wrap(const char *name) : _module(sc_gen_unique_name(name)) {}
inline explicit sc_wrap() : _module(sc_gen_unique_name("sc_wrap")) {}
inline T *operator->() { return &_module; }
inline T &get() { return _module; }
};
template <class T, int N, int _cur_indx = 0> class sc_static_data_list {
T elem;
sc_static_data_list<T, N - 1, _cur_indx + 1> next;
public:
inline explicit sc_static_data_list() {}
inline T &get(int indx) {
if (indx == _cur_indx) {
return elem;
} else {
return next.get(indx);
}
}
inline T *operator[](int indx) {
if (indx == _cur_indx) {
return &elem;
} else {
return next[indx];
}
}
};
template <class T, int _cur_indx> class sc_static_data_list<T, 1, _cur_indx> {
T elem;
public:
inline explicit sc_static_data_list() {}
inline T &get(int indx) { return elem; }
inline T *operator[](int indx) { return &elem; }
};
struct none_param {};
template <class T, int N, int _cur_indx = 0> class sc_static_list {
T elem;
sc_static_list<T, N - 1, _cur_indx + 1> next;
public:
inline explicit sc_static_list(const char *name = "list") : elem(sc_gen_unique_name(name)), next(name) {}
inline explicit sc_static_list(const char *name, int size)
: elem(sc_gen_unique_name(name), size), next(name, size) {}
inline explicit sc_static_list(int size) : elem(size), next(size) {}
inline explicit sc_static_list(none_param none) : next(none) {}
inline T &get(int indx) {
if (indx == _cur_indx) {
return elem;
} else {
return next.get(indx);
}
}
inline T *operator[](int indx) {
if (indx == _cur_indx) {
return &elem;
} else {
return next[indx];
}
}
};
template <class T, int _cur_indx> class sc_static_list<T, 1, _cur_indx> {
T elem;
public:
inline explicit sc_static_list(const char *name = "list") : elem(sc_gen_unique_name(name)) {}
inline explicit sc_static_list(const char *name, int size) : elem(sc_gen_unique_name(name), size) {}
inline explicit sc_static_list(int size) : elem(size) {}
inline explicit sc_static_list(none_param none) {}
inline T &get(int indx) { return elem; }
inline T *operator[](int indx) { return &elem; }
};
template <class T, int N, int _cur_indx = 0> class sc_static_list2 {
T elem;
sc_static_list2<T, N - 1, _cur_indx + 1> next;
public:
inline explicit sc_static_list2(const char *name = "list2") : elem(sc_gen_unique_name(name)), next(name) {}
inline explicit sc_static_list2(const char *name, int size)
: elem(sc_gen_unique_name(name), size), next(name, size) {}
inline explicit sc_static_list2(int size) : elem(size), next(size) {}
inline T &get(int indx) {
if (indx == _cur_indx) {
return elem;
} else {
return next.get(indx);
}
}
inline T *operator[](int indx) {
if (indx == _cur_indx) {
return &elem;
} else {
return next[indx];
}
}
};
template <class T, int _cur_indx> class sc_static_list2<T, 1, _cur_indx> {
T elem;
public:
inline explicit sc_static_list2(const char *name = "list2") : elem(sc_gen_unique_name(name)) {}
inline explicit sc_static_list2(const char *name, int size) : elem(sc_gen_unique_name(name), size) {}
inline explicit sc_static_list2(int size) : elem(size) {}
inline T &get(int indx) { return elem; }
inline T *operator[](int indx) { return &elem; }
};
template <class T, int N> class sc_vector {
private:
const int _N;
T mVec[N];
// sc_core::sc_vector<T> mVec;
public:
inline explicit sc_vector() : _N(N) {
#pragma HLS ARRAY_PARTITION variable = mVec complete dim = 1
}
inline T &operator[](int idx) { return mVec[idx]; }
inline T &get(int idx) { return mVec[idx]; }
};
/*template<int W, int I>
using sc_fixed_sat = sc_fixed<W,I,sc_dt::sc_q_mode::SC_TRN,sc_dt::sc_o_mode::SC_SAT>;*/
/*template <class T, int size = 16>
class sc_fifo_template : public sc_fifo<T>
{
public:
explicit sc_fifo_template()
: sc_fifo<T>(size)
{
}
explicit sc_fifo_template(const char *name_)
: sc_fifo<T>(name_, size)
{
}
private:
// disabled
sc_fifo_template(const sc_fifo_template<T> &);
sc_fifo_template &operator=(const sc_fifo_template<T> &);
};*/
template <int W1, int W2> inline sc_bv<W1 + W2> bv_merge(sc_bv<W1> bv1, sc_bv<W2> bv2) {
#pragma HLS loop_merge
sc_bv<W1 + W2> tmp;
for (int i = 0; i < W2; i++) {
#pragma HLS unroll
tmp[i] = bv2[i];
}
for (int i = 0; i < W1; i++) {
#pragma HLS unroll
tmp[i + W2] = bv1[i];
}
return tmp;
}
template <int W, int p> inline sc_fixed<W, p> bv2fixed(const sc_bv<W> bitvec) {
sc_fixed<W, p> tmp;
for (int i = 0; i < W; i++) {
#pragma HLS unroll
tmp[i] = bitvec.get_bit(i);
}
return tmp;
}
template <int W, int p> inline sc_ufixed<W, p> bv2ufixed(const sc_bv<W> bitvec) {
sc_ufixed<W, p> tmp;
for (int i = 0; i < W; i++) {
#pragma HLS unroll
tmp[i] = bitvec.get_bit(i);
}
return tmp;
}
template <int W, int p> inline sc_bv<W> fixed2bv(const sc_fixed<W, p> fixval) {
sc_bv<W> tmp;
for (int i = 0; i < W; i++) {
#pragma HLS unroll
tmp[i] = fixval[i];
}
return tmp;
}
template <int W, int p> inline sc_bv<W> ufixed2bv(const sc_ufixed<W, p> fixval) {
sc_bv<W> tmp;
for (int i = 0; i < W; i++) {
#pragma HLS unroll
tmp[i] = fixval[i];
}
return tmp;
}
// https://stackoverflow.com/questions/2183087/why-cant-i-use-float-value-as-a-template-parameter @ Ashley Smart
template <int NUM, int DEN = 1, int FACTOR_1000 = 1000> struct const_float {
enum {
FLOOR = (int)(((float)NUM / (float)DEN) * ((float)FACTOR_1000 / 1000.0f)),
CEIL = (int)FLOOR + ((float)FLOOR == (((float)NUM / (float)DEN) * ((float)FACTOR_1000 / 1000.0f)) ? 0 : 1)
};
};
template <bool switch_P, class T1_true = void, class T2_false = void> struct switch_if_t {};
template <class T1_true, class T2_false> struct switch_if_t<true, T1_true, T2_false> { typedef T1_true type; };
template <class T1_true, class T2_false> struct switch_if_t<false, T1_true, T2_false> { typedef T2_false type; };
template <int N_VAL> struct log2_floor {
enum { val = 1 + log2_floor<(N_VAL / 2 <= 1 ? 1 : N_VAL / 2)>::val };
};
template <> struct log2_floor<-1> {
enum { val = 0 };
};
template <> struct log2_floor<0> {
enum { val = 1 };
};
template <> struct log2_floor<1> {
enum { val = 1 };
};
template <int N_VAL> struct log2_ceil {
enum { val = log2_floor<N_VAL - 1>::val };
};
template <template <int> class data_T, int W> inline data_T<W> HIGH() {
data_T<W> tmp;
for (int i = 0; i < W; i++) {
tmp[i] = 1;
}
return tmp;
}
template <int N> struct max_s {
template <typename T> inline T max(T *a) {
T m0 = max_s<N / 2>::max(*a[0]);
T m1 = max_s<N - N / 2>::max(*a[N / 2]);
return (m0 > m1 ? m0 : m1);
}
};
template <> struct max_s<1> {
template <typename T> inline T max(T *a) { return a[0]; }
};
template <int N, typename T> inline T max(T *a) { return max_s<N>::max(a); }
} // namespace hf
} // namespace hwcore
#ifndef __SYNTHESIS__
// template <class T> using sc_out_opt = sc_port<sc_signal_out_if<T>, 1, SC_ZERO_OR_MORE_BOUND>;
template <class T> struct sc_out_opt : public sc_port<sc_signal_out_if<T>, 2, SC_ONE_OR_MORE_BOUND> {
private:
sc_signal<T> mSignal;
public:
sc_out_opt() : sc_port<sc_signal_out_if<T>, 2, SC_ONE_OR_MORE_BOUND>() { (*this)(mSignal); }
virtual ~sc_out_opt() {}
void write(T data) { (*this)->write(data); }
};
#else
#define sc_out_opt sc_out
// template <class T> using sc_out_opt = sc_out<T>;
#endif
/*
#ifdef __SYNTHESIS__
#include <ap_fixed.h>
template <int W, int I> using sc_fixed_sat = ap_fixed<W, I, AP_RND, AP_SAT>;
#else
#endif*/
// template <int W, int I> using sc_fixed_sat = sc_fixed<W, I, SC_TRN, SC_SAT>;
|
/**
* @file
* @copyright Copyright 2016 GNSS Sensor Ltd. All right reserved.
* @author Sergey Khabarov - [email protected]
* @brief CPU Fetch Instruction stage.
*/
#ifndef __DEBUGGER_RIVERLIB_FETCH_H__
#define __DEBUGGER_RIVERLIB_FETCH_H__
#include <systemc.h>
#include "../river_cfg.h"
namespace debugger {
SC_MODULE(InstrFetch) {
sc_in<bool> i_clk;
sc_in<bool> i_nrst;
sc_in<bool> i_pipeline_hold;
sc_in<bool> i_mem_req_ready;
sc_out<bool> o_mem_addr_valid;
sc_out<sc_uint<BUS_ADDR_WIDTH>> o_mem_addr;
sc_in<bool> i_mem_data_valid;
sc_in<sc_uint<BUS_ADDR_WIDTH>> i_mem_data_addr;
sc_in<sc_uint<32>> i_mem_data;
sc_in<bool> i_mem_load_fault;
sc_out<bool> o_mem_resp_ready;
sc_in<sc_uint<BUS_ADDR_WIDTH>> i_e_npc;
sc_in<sc_uint<BUS_ADDR_WIDTH>> i_predict_npc;
sc_in<bool> i_predict;
sc_out<bool> o_predict_miss;
sc_out<bool> o_mem_req_fire; // used by branch predictor to form new npc value
sc_out<bool> o_ex_load_fault;
sc_out<bool> o_valid;
sc_out<sc_uint<BUS_ADDR_WIDTH>> o_pc;
sc_out<sc_uint<32>> o_instr;
sc_out<bool> o_hold; // Hold due no response from icache yet
sc_in<bool> i_br_fetch_valid; // Fetch injection address/instr are valid
sc_in<sc_uint<BUS_ADDR_WIDTH>> i_br_address_fetch; // Fetch injection address to skip ebreak instruciton only once
sc_in<sc_uint<32>> i_br_instr_fetch; // Real instruction value that was replaced by ebreak
sc_out<sc_biguint<DBG_FETCH_TRACE_SIZE*64>> o_instr_buf; // todo: remove it
void comb();
void registers();
SC_HAS_PROCESS(InstrFetch);
InstrFetch(sc_module_name name_);
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
struct RegistersType {
sc_signal<bool> wait_resp;
sc_signal<sc_uint<5>> pipeline_init;
sc_signal<sc_uint<BUS_ADDR_WIDTH>> pc_z1;
sc_signal<sc_uint<BUS_ADDR_WIDTH>> raddr_not_resp_yet;
sc_signal<sc_uint<BUS_ADDR_WIDTH>> br_address;
sc_signal<sc_uint<32>> br_instr;
sc_signal<sc_biguint<DBG_FETCH_TRACE_SIZE*64>> instr_buf;
} v, r;
};
} // namespace debugger
#endif // __DEBUGGER_RIVERLIB_FETCH_H__
|
/* Copyright (c) 2015 Convey Computer Corporation
*
* This file is part of the OpenHT toolset located at:
*
* https://github.com/TonyBrewer/OpenHT
*
* Use and distribution licensed under the BSD 3-clause license.
* See the LICENSE file for the complete license text.
*/
#pragma once
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <string.h>
#include <assert.h>
#include <pthread.h>
#include <string>
#include <queue>
#include <list>
#include <map>
#include <errno.h>
#ifdef WIN32
#include <crtdbg.h>
#endif
#if defined(HT_SYSC) || defined(_HTV) || defined(HT_LIB_SYSC)
#include <systemc.h>
# if !defined(_HTV)
#include "sysc/HtStrFmt.h"
# endif
#endif
#if !defined(HT_LIB_HIF) && !defined(HT_LIB_SYSC)
#include "HostIntf.h"
#endif
#include "host/HtDefines.h"
#include "host/HtPlatform.h"
#if defined(HT_SYSC) || defined(_HTV)
#include "sysc/Params.h"
#endif
#if !defined(_HTV)
using namespace std;
#include "host/HtCtrlMsg.h"
#include "host/HtHif.h"
#include "host/HtModel.h"
#include "sysc/mtrand.h"
#endif
#if defined(HT_SYSC) || defined(_HTV) || defined(HT_LIB_SYSC)
#include "sysc/HtInt.h"
# if !defined(_HTV)
#include "sysc/MemMon.h"
# endif
#include "sysc/HtMemTypes.h"
#include "sysc/MemRdWrIntf.h"
#include "sysc/PersXbarStub.h"
#include "sysc/PersMiStub.h"
#include "sysc/PersMoStub.h"
#include "sysc/PersUnitCnt.h"
#include "sysc/SyscClock.h"
#include "sysc/SyscDisp.h"
#include "sysc/SyscMem.h"
#endif
#if !defined(HT_LIB_HIF) && !defined(HT_LIB_SYSC)
#include "UnitIntf.h"
#endif
|
#include <systemc.h>
SC_MODULE( tb ) {
public:
sc_vector<sc_out<bool>> inp_a, inp_b;
sc_out<bool> inp_cin;
sc_vector<sc_in<bool>> sum;
sc_in<bool> co;
SC_HAS_PROCESS( tb );
bool a[6][4];
bool b[6][4];
tb( sc_module_name nm );
private:
void source();
void sink();
};
|
#pragma once
#include <systemc.h>
#include "hwcore/hf/helperlib.h"
#include "hwcore/pipes/data_types.h"
#include "hwcore/pipes/streamimagedatafix.h"
#include <algorithm>
#include <list>
#define W 16
#define I 2
#define BW 8
SC_MODULE(tb_top_imagedata_fix) {
sc_clock clk;
sc_in<bool> iclk;
sc_signal<bool> reset;
typedef hwcore::pipes::sc_stream_imagedatafix<W, I, BW> stream_image_t;
typedef typename stream_image_t::din_T fifo_t;
stream_image_t imagefix_u0;
sc_fifo<fifo_t> din;
sc_fifo<fifo_t> dout;
sc_fifo<sc_uint<1> > enable;
SC_CTOR(tb_top_imagedata_fix) : clk("clk", sc_time(10, SC_NS)), SC_INST(imagefix_u0) {
iclk(clk);
SC_MODULE_LINK(imagefix_u0);
imagefix_u0.din(din);
imagefix_u0.dout(dout);
imagefix_u0.enable(enable);
SC_CTHREAD(wave_thread, iclk.pos());
HLS_DEBUG_EXEC(set_stack_size(128 * 10 * 1024 * 1024));
SC_CTHREAD(mon_thread, iclk.pos());
HLS_DEBUG_EXEC(set_stack_size(128 * 10 * 1024 * 1024));
}
sc_ufixed<8, 0> func(int a, int b, int c) {
sc_ufixed<8, 0> tmp = 0;
tmp(7, 5) = a;
tmp(4, 2) = b;
tmp(1, 0) = c;
return tmp;
}
void func_inv(sc_ufixed<8, 0> in, int &a, int &b, int &c) {
a = in(7, 5).to_int();
b = in(4, 2).to_int();
c = in(1, 0).to_int();
}
void wave_thread() {
reset.write(1);
wait();
reset.write(0);
wait();
sc_assert(BW >= 3);
const int image_size = 32;
sc_fixed<W, I> *realign_data = new sc_fixed<W, I>[image_size * image_size * BW];
for (int x = 0; x < image_size; x++) {
for (int y = 0; y < image_size; y++) {
for (int z = 0; z < BW; z++) {
int ptr_to = (x * image_size * BW) + (y * BW) + z;
if (z < 3) {
realign_data[ptr_to] = func(x, y, z);
std::cout << realign_data[ptr_to].to_float() << std::endl;
} else {
realign_data[ptr_to] = 0;
}
}
}
}
enable.write(0);
for (int i = 0; i < image_size * image_size; i++) {
fifo_t tmp_out;
tmp_out.setKeep();
tmp_out.setDataFixed<W, I, BW>(&realign_data[i * BW]);
tmp_out.tlast = (i == (image_size * image_size) - 1 ? 1 : 0);
din.write(tmp_out);
}
sc_ufixed<8, 0> *raw_data = new sc_ufixed<8, 0>[image_size * image_size * 3];
for (int x = 0; x < image_size; x++) {
for (int y = 0; y < image_size; y++) {
for (int z = 0; z < 3; z++) {
int ptr_to = (x * image_size * 3) + (y * 3) + z;
raw_data[ptr_to] = func(x, y, z);
std::cout << raw_data[ptr_to].to_float() << std::endl;
}
}
}
enable.write(1);
const int N = (image_size * image_size * 3 * 8) / (BW * W);
const int N_pr_pkg = (BW * W) / 8;
for (int i = 0; i < N; i++) {
fifo_t tmp_out;
tmp_out.setKeep();
tmp_out.setDataUfixed<8, 0, (BW * W) / 8>(&raw_data[i * N_pr_pkg]);
tmp_out.tlast = (i == N - 1 ? 1 : 0);
din.write(tmp_out);
}
while (true) {
wait();
}
}
void mon_thread() {
std::list<fifo_t> realign_data;
std::list<fifo_t> raw_data;
fifo_t tmp;
do {
tmp = dout.read();
realign_data.push_back(tmp);
} while (tmp.tlast == 0);
std::cout << "mon got N samples " << realign_data.size() << std::endl;
do {
tmp = dout.read();
raw_data.push_back(tmp);
} while (tmp.tlast == 0);
std::cout << "mon got N samples " << raw_data.size() << std::endl;
sc_assert(raw_data.size() == realign_data.size());
auto itr_realign_data = realign_data.begin();
auto itr_raw_data = raw_data.begin();
for (int i = 0; i < realign_data.size(); i++) {
sc_assert(*itr_realign_data == *itr_raw_data);
itr_realign_data++;
itr_raw_data++;
}
wait();
sc_stop();
}
};
|
/* Copyright 2017 Pedro Cuadra <[email protected]> & Meghadoot Gardi
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License. */
#ifndef VITERBI_PATH_H_
#define VITERBI_PATH_H_
#include <systemc.h>
#include <sysc/utils/sc_string.h>
#include <common/util.h>
#include <sstream>
#include <bitset>
#define CURR_STAGE 0
#define NEXT_STAGE 1
#define MAX_STAGES 2
#define MAX_PATH_WIDTH 32
#define MAX_METRIC_WIDTH 32
template<int output_buffer_bit_size>
struct viterbi_path_s {
/** Metric Value */
sc_uint<MAX_METRIC_WIDTH> metric_value;
/** Size of the path */
sc_uint<MAX_PATH_WIDTH> path_size;
/** Path */
sc_uint<output_buffer_bit_size> path_output;
/** Valid flag */
bool is_alive;
/**
* Overload the = operation
*/
inline viterbi_path_s<output_buffer_bit_size>& operator= (const viterbi_path_s<output_buffer_bit_size>& obj) {
metric_value = obj.metric_value;
path_size = obj.path_size;
path_output = obj.path_output;
is_alive = obj.is_alive;
}
/**
* Overload the == operation
*/
inline bool operator== (const viterbi_path_s<output_buffer_bit_size>& obj) const {
bool ret_val = true;
ret_val &= (metric_value == obj.metric_value);
ret_val &= (path_size == obj.path_size);
ret_val &= (is_alive == obj.is_alive);
ret_val &= (path_output == obj.path_output);
return ret_val;
}
inline friend void sc_trace(sc_trace_file * tf, const viterbi_path_s<output_buffer_bit_size>& obj, const std::string& name) {
std::stringstream ss;
sc_trace(tf, obj.metric_value, name + ".metric");
sc_trace(tf, obj.is_alive, name + ".is_alive");
sc_trace(tf, obj.path_size, name + ".path_size");
sc_trace(tf, obj.path_output, name + ".output");
}
};
#endif
|
/*******************************************************************************
* gn_mixed.cpp -- Copyright 2019 (c) Glenn Ramalho - RFIDo Design
*******************************************************************************
* Description:
* This is a derivative of the sc_signal_resolved class from SystemC
* which was extended to support a third, analog level, data state. It should
* be noted that this is not a real AMS style signal, for that we need
* SystemC-AMS. This is just a shortcut to make it possible to express
* a signal which can be either analog or 4-state without having to
* use a AMS style simulator.
*******************************************************************************
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* This was based off the work licensed as:
*
* Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
* more contributor license agreements. See the NOTICE file distributed
* with this work for additional information regarding copyright ownership.
* Accellera licenses this file to you under the Apache License, Version 2.0
* (the "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
* implied. See the License for the specific language governing
* permissions and limitations under the License.
*
* Original Author: Martin Janssen, Synopsys, Inc., 2001-05-21
*******************************************************************************
*/
#include <systemc.h>
#include "gn_mixed.h"
/* The table for resolving GN_LOGIC.
* Some notes:
* -weak always looses from strong,
* -there is no weak undefined as we do not know if a weak undefined would
* loose.
* -Analog only wins from Z as a short between analog requires us to know
* the currents.
* -Conflicts with Undefined always produce an Undefined.
*/
gn_mixed::gn_logic_t
gn_logic_resolution_tbl[7][7] =
/* 0 */ /* 1 */ /* W0 */ /* W1 */ /* Z */ /* A */ /* X */
/* 0 */{{GN_LOGIC_0,GN_LOGIC_X,GN_LOGIC_0 ,GN_LOGIC_0 ,GN_LOGIC_0 ,GN_LOGIC_X,GN_LOGIC_X},
/* 1 */ {GN_LOGIC_X,GN_LOGIC_1,GN_LOGIC_1 ,GN_LOGIC_1 ,GN_LOGIC_1 ,GN_LOGIC_X,GN_LOGIC_X},
/*W0 */ {GN_LOGIC_0,GN_LOGIC_1,GN_LOGIC_W0,GN_LOGIC_X ,GN_LOGIC_W0,GN_LOGIC_X,GN_LOGIC_X},
/*W1 */ {GN_LOGIC_0,GN_LOGIC_1,GN_LOGIC_X ,GN_LOGIC_W1,GN_LOGIC_W1,GN_LOGIC_X,GN_LOGIC_X},
/* Z */ {GN_LOGIC_0,GN_LOGIC_1,GN_LOGIC_W0,GN_LOGIC_W1,GN_LOGIC_Z ,GN_LOGIC_A,GN_LOGIC_X},
/* A */ {GN_LOGIC_X,GN_LOGIC_X,GN_LOGIC_X ,GN_LOGIC_X ,GN_LOGIC_A ,GN_LOGIC_X,GN_LOGIC_X},
/* X */ {GN_LOGIC_X,GN_LOGIC_X,GN_LOGIC_X ,GN_LOGIC_X ,GN_LOGIC_X ,GN_LOGIC_X,GN_LOGIC_X}};
/* These are globals that set the analog levels to be used for the different
* digital levels. There is no resolution or feedback calculated in them.
* It is just a convention to make it more easily vieable in a digital
* waveform viewer. vdd_lvl is the level for logic 1, vss_lvl is for logic 0
* and undef_lvl is for Z or X.
*/
float gn_mixed::vdd_lvl = 3.3f;
float gn_mixed::vss_lvl = 0.0f;
float gn_mixed::undef_lvl = 1.5f;
sc_logic gn_to_sc_logic(gn_mixed::gn_logic_t g) {
switch(g) {
case GN_LOGIC_0:
case GN_LOGIC_W0: return SC_LOGIC_0;
case GN_LOGIC_1:
case GN_LOGIC_W1: return SC_LOGIC_1;
case GN_LOGIC_Z: return SC_LOGIC_Z;
default: return SC_LOGIC_X;
}
}
float gn_mixed::guess_lvl(sc_logic &l) {
if (l == SC_LOGIC_0) return vss_lvl;
else if (l == SC_LOGIC_1) return vdd_lvl;
else return undef_lvl;
}
gn_mixed::gn_param_t gn_mixed::guess_param(gn_logic_t g) {
switch(g) {
case GN_LOGIC_W0: return GN_TYPE_WEAK;
case GN_LOGIC_W1: return GN_TYPE_WEAK;
case GN_LOGIC_A: return GN_TYPE_ANALOG;
case GN_LOGIC_Z: return GN_TYPE_Z;
default: return GN_TYPE_STRONG;
}
}
gn_mixed::gn_logic_t char_to_gn(const char c_) {
switch(c_) {
case '0': return GN_LOGIC_0;
case '1': return GN_LOGIC_1;
case 'l': return GN_LOGIC_W0;
case 'h': return GN_LOGIC_W1;
case 'Z': return GN_LOGIC_Z;
case 'A': return GN_LOGIC_A;
default: return GN_LOGIC_X;
}
}
gn_mixed::gn_mixed() {
logic = SC_LOGIC_X;
lvl = undef_lvl;
param = GN_TYPE_STRONG;
}
gn_mixed::gn_mixed(const gn_mixed &n) {
logic = n.logic;
lvl = n.lvl;
param = n.param;
}
gn_mixed::gn_mixed(const gn_logic_t n_) {
logic = gn_to_sc_logic(n_);
lvl = guess_lvl(logic);
param = guess_param(n_);
}
gn_mixed::gn_mixed(const sc_logic &n) {
logic = n;
lvl = guess_lvl(logic);
param = (n == SC_LOGIC_Z)?GN_TYPE_Z:GN_TYPE_STRONG;
}
gn_mixed::gn_mixed(const float &n) {
logic = SC_LOGIC_X;
lvl = n;
param = GN_TYPE_ANALOG;
}
gn_mixed::gn_mixed(const char c_) {
gn_logic_t g = char_to_gn(c_);
logic = gn_to_sc_logic(g);
lvl = guess_lvl(logic);
param = guess_param(g);
}
gn_mixed::gn_mixed(const bool b_) {
logic = sc_logic(b_);
lvl = guess_lvl(logic);
param = GN_TYPE_STRONG;
}
gn_mixed &gn_mixed::operator=(const gn_mixed &n) {
logic = n.logic;
lvl = n.lvl;
param = n.param;
return *this;
}
gn_mixed &gn_mixed::operator=(const gn_logic_t n_) {
logic = gn_to_sc_logic(n_);
lvl = guess_lvl(logic);
param = guess_param(n_);
return *this;
}
gn_mixed &gn_mixed::operator=(const sc_logic &n) {
logic = n;
lvl = guess_lvl(logic);
param = (n == SC_LOGIC_Z)?GN_TYPE_Z:GN_TYPE_STRONG;
return *this;
}
gn_mixed &gn_mixed::operator=(const float &n) {
logic = LOGIC_A;
lvl = n;
param = GN_TYPE_ANALOG;
return *this;
}
gn_mixed &gn_mixed::operator=(const char c_) {
gn_logic_t g = char_to_gn(c_);
logic = gn_to_sc_logic(g);
lvl = guess_lvl(logic);
param = guess_param(g);
return *this;
}
gn_mixed &gn_mixed::operator=(const bool b_) {
logic = sc_logic(b_);
lvl = guess_lvl(logic);
param = GN_TYPE_STRONG;
return *this;
}
/* When comparing GN_MIXED, we compare all fields. When comparing GN_MIXED to
* SC_LOGIC we have to treat the weak and strong signals as the same. We also
* have to treat analog signals as simply undefined.
*/
bool operator==(const gn_mixed &a, const gn_mixed &b) {
if (a.logic != b.logic) return false;
if (a.param != b.param) return false;
if (a.param != gn_mixed::GN_TYPE_ANALOG) return true;
return (a.lvl > b.lvl - 0.01 && a.lvl < b.lvl + 0.01);
}
bool operator==(const gn_mixed &a, const sc_logic &b) {
return a.logic == b;
}
char gn_mixed::to_char() const {
if (param == GN_TYPE_ANALOG) return 'A';
else if (logic == SC_LOGIC_X) return 'X';
else if (logic == SC_LOGIC_Z) return 'Z';
else if (logic == SC_LOGIC_0) return (param == GN_TYPE_WEAK)?'l':'0';
else if (logic == SC_LOGIC_1) return (param == GN_TYPE_WEAK)?'h':'1';
else return GN_LOGIC_X;
}
gn_mixed::gn_logic_t gn_mixed::value() {
if (param == GN_TYPE_ANALOG) return GN_LOGIC_A;
else if (logic == SC_LOGIC_X) return GN_LOGIC_X;
else if (logic == SC_LOGIC_Z) return GN_LOGIC_Z;
else if (logic == SC_LOGIC_0)
return (param == GN_TYPE_WEAK)?GN_LOGIC_W0:GN_LOGIC_0;
else if (logic == SC_LOGIC_1)
return (param == GN_TYPE_WEAK)?GN_LOGIC_W1:GN_LOGIC_1;
else return GN_LOGIC_X;
}
static void gn_mixed_resolve(gn_mixed& result_,
const std::vector<gn_mixed>& values_ )
{
int sz = values_.size();
sc_assert( sz != 0 );
if( sz == 1 ) {
result_ = values_[0];
return;
}
gn_mixed current;
gn_mixed res = values_[0];
int i;
/* We now scan the list of driven values so we can resolve it. If we find
* a X it all goes X, so we can stop looking.
*/
for(i = sz - 1; i>0 && res.logic != SC_LOGIC_X; --i) {
/* If the resolved is high-Z, we resolve to the next one. */
if (res.value() == GN_LOGIC_Z) {
res = values_[i];
continue;
}
/* In other cases we use the resolution table. */
current = values_[i];
/* This case is simple. */
if (current.value() == GN_LOGIC_Z) continue;
/* We let the resolution table handle the rest. */
res = gn_logic_resolution_tbl[res.value()][current.value()];
}
result_ = res;
}
void gn_signal_mix::write(const value_type& value_) {
sc_process_b* cur_proc = sc_get_current_process_b();
bool value_changed = false;
bool found = false;
for( int i = m_proc_vec.size() - 1; i >= 0; -- i ) {
if( cur_proc == m_proc_vec[i] ) {
if( value_ != m_val_vec[i] ) {
m_val_vec[i] = value_;
value_changed = true;
}
found = true;
break;
}
}
if( ! found ) {
m_proc_vec.push_back( cur_proc );
m_val_vec.push_back( value_ );
value_changed = true;
}
if( value_changed ) {
request_update();
}
}
void gn_signal_mix::write( const gn_mixed::gn_logic_t value_ )
{ write(gn_mixed(value_));}
void gn_signal_mix::write( const sc_logic& value_ ) { write(gn_mixed(value_)); }
void gn_signal_mix::write( const float& value_ ) { write(gn_mixed(value_)); }
void gn_signal_mix::write( const char value_ ) { write(gn_mixed(value_)); }
void gn_signal_mix::write( const bool value_ ) { write(gn_mixed(value_)); }
sc_logic gn_signal_mix::read_logic( ) {
return read().logic;
}
float gn_signal_mix::read_lvl( ) {
return read().lvl;
}
void gn_signal_mix::update()
{
gn_mixed_resolve( m_new_val, m_val_vec );
base_type::update();
}
void gn_tie_mix::update()
{
base_type::update();
}
|
/**
#define meta ...
prInt32f("%s\n", meta);
**/
/*
All rights reserved to Alireza Poshtkohi (c) 1999-2023.
Email: [email protected]
Website: http://www.poshtkohi.info
*/
#ifndef __pe_work_stealing_scheduler_sc__h__
#define __pe_work_stealing_scheduler_sc__h__
#include <systemc.h>
#include "globals.h"
//----------------------------------------------------
class pe_work_stealing_scheduler : public sc_module
{
/*---------------------fields-----------------*/
public: sc_in<bool> clock;
public: sc_in<bool> re_cores[NumOfCores]; // Read Enable
public: sc_in<bool> cs_cores[NumOfCores]; // Chip Select
public: sc_out<sc_int<32> > work_cores[NumOfCores];
private: const int numOfWorks;
/*---------------------methods----------------*/
SC_HAS_PROCESS(pe_work_stealing_scheduler);
public: pe_work_stealing_scheduler(sc_module_name name_, int numOfWorks_);
public: ~pe_work_stealing_scheduler();
private: void pe_work_stealing_scheduler_proc();
private: void print_ports(int i);
/*--------------------------------------------*/
};
//----------------------------------------------------
#endif
|
#include <config.hpp>
#include <core.hpp>
#include <systemc.h>
SC_MODULE(Sensor_${sensor_name}_functional)
{
Core* core;
//Input Port
sc_core::sc_in <bool> enable;
sc_core::sc_in <unsigned int> address;
sc_core::sc_in <uint8_t*> data_in;
sc_core::sc_in <unsigned int> req_size;
sc_core::sc_in <bool> flag_wr;
sc_core::sc_in <bool> ready;
//Output Port
sc_core::sc_out <uint8_t*> data_out;
sc_core::sc_out <bool> go;
//Power Port
sc_core::sc_out <int> power_signal;
//Thermal Port
//sc_core::sc_out <int> thermal_signal;
SC_CTOR(Sensor_${sensor_name}_functional):
enable("Enable_signal"),
address("Address"),
data_in("Data_in"),
flag_wr("Flag"),
ready("Ready"),
data_out("Data_out"),
go("Go"),
power_signal("Func_to_Power_signal")
{
//printf("SENSOR :: systemc constructor");
register_memory = new uint8_t[${register_memory}];
SC_THREAD(sensor_logic);
sensitive << ready;
}
void sensor_logic();
Sensor_${sensor_name}_functional(){
//printf("SENSOR :: constructor");
}
~Sensor_${sensor_name}_functional(){
delete[]register_memory;
}
//Register Map
private:
uint8_t* register_memory;
int register_memory_size=${register_memory};
}; |
//
//------------------------------------------------------------//
// Copyright 2009-2012 Mentor Graphics Corporation //
// All Rights Reserved Worldwid //
// //
// Licensed under the Apache License, Version 2.0 (the //
// "License"); you may not use this file except in //
// compliance with the License. You may obtain a copy of //
// the License at //
// //
// http://www.apache.org/licenses/LICENSE-2.0 //
// //
// Unless required by applicable law or agreed to in //
// writing, software distributed under the License is //
// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR //
// CONDITIONS OF ANY KIND, either express or implied. See //
// the License for the specific language governing //
// permissions and limitations under the License. //
//------------------------------------------------------------//
//-----------------------------------------------------------------------------
// Title: UVMC Command API
//
// This section describes the API for accessing and controlling UVM simulation
// in SystemVerilog from SystemC (or C or C++). To use, the SV side must have
// called the ~uvmc_init~, which starts a background process that receives and
// processes incoming commands.
//
// The UVM Connect library provides an SystemC API for accessing SystemVeilog
// UVM during simulation. With this API users can:
//
// - Wait for a UVM to reach a given simulation phase
// - Raise and drop objections
// - Set and get UVM configuration
// - Send UVM report messages
// - Set type and instance overrides in the UVM factory
// - Print UVM component topology
//
// While most commands are compatible with C, a few functions take object
// arguments or block on sc_events. Therefore, SystemC is currently the only
// practical source language for using the UVM Command API. Future releases may
// separate the subset of C-compatible functions into a separate shared library
// that would not require linking in SystemC.
//
// The following may appear in a future release, based on demand
//
// - Callbacks on phase and objection activity
// - Receive UVM report messages, i.e. SC-side acts as report catcher or server
// - Integration with SystemCs sc_report_handler facility
// - Print factory contents, config db contents, and other UVM information
// - Separate command layer into SC, C++, and C-accessible components; i.e.
// not require SystemC for non-SystemC-dependent functions
//
// The following sections provide details and examples for each command in the
// UVM Command API. To enable access to the UVM command layer, you must call
// the uvmc_cmd_init function from an initial block in a top-level module as in
// the following example:
//
// SystemVerilog:
//
//| module sv_main;
//|
//| import uvm_pkg::*;
//| import uvmc_pkg::*;
//|
//| initial begin
//| uvmc_cmd_init();
//| run_test();
//| end
//|
//| endmodule
//
// SystemC-side calls to the UVM Command API will block until SystemVerilog has
// finished elaboration and the uvmc_cmd_init function has been called. Because
// any call to the UVM Command layer may block, calls must be made from within
// thread processes.
//
// All code provided in the UVM Command descriptions that follow are SystemC
// unless stated otherwise.
#ifndef UVMC_COMMANDS_H
#define UVMC_COMMANDS_H
#include "svdpi.h"
#include <string>
#include <map>
#include <vector>
#include <iomanip>
#include <systemc.h>
#include <tlm.h>
using namespace sc_core;
using namespace sc_dt;
using namespace tlm;
using std::string;
using std::map;
using std::vector;
using sc_core::sc_semaphore;
#include "uvmc_common.h"
#include "uvmc_convert.h"
extern "C" {
//------------------------------------------------------------------------------
// Group: Enumeration Constants
//
// The following enumeration constants are used in various UVM Commands:
//------------------------------------------------------------------------------
// Enum: uvmc_phase_state
//
// The state of a UVM phase
//
// UVM_PHASE_DORMANT - Phase has not started yet
// UVM_PHASE_STARTED - Phase has started
// UVM_PHASE_EXECUTING - Phase is executing
// UVM_PHASE_READY_TO_END - Phase is ready to end
// UVM_PHASE_ENDED - Phase has ended
// UVM_PHASE_DONE - Phase has completed
//
enum uvmc_phase_state {
UVM_PHASE_DORMANT = 1,
UVM_PHASE_SCHEDULED = 2,
UVM_PHASE_SYNCING = 4,
UVM_PHASE_STARTED = 8,
UVM_PHASE_EXECUTING = 16,
UVM_PHASE_READY_TO_END = 32,
UVM_PHASE_ENDED = 64,
UVM_PHASE_CLEANUP = 128,
UVM_PHASE_DONE = 256,
UVM_PHASE_JUMPING = 512
};
// Enum: uvmc_report_severity
//
// The severity of a report
//
// UVM_INFO - Informative message. Verbosity settings affect whether
// they are printed.
// UVM_WARNING - Warning. Not affected by verbosity settings.
// UVM_ERROR - Error. Error counter incremented by default. Not affected
// by verbosity settings.
// UVM_FATAL - Unrecoverable error. SV simulation will end immediately.
//
enum uvmc_report_severity {
UVM_INFO,
UVM_WARNING,
UVM_ERROR,
UVM_FATAL
};
// Enum: uvmc_report_verbosity
//
// The verbosity level assigned to UVM_INFO reports
//
// UVM_NONE - report will always be issued (unaffected by
// verbosity level)
// UVM_LOW - report is issued at low verbosity setting and higher
// UVM_MEDIUM - report is issued at medium verbosity and higher
// UVM_HIGH - report is issued at high verbosity and higher
// UVM_FULL - report is issued only when verbosity is set to full
//
enum uvmc_report_verbosity {
UVM_NONE = 0,
UVM_LOW = 100,
UVM_MEDIUM = 200,
UVM_HIGH = 300,
UVM_FULL = 400
};
// Enum: uvmc_wait_op
//
// The relational operator to apply in <uvmc_wait_for_phase> calls
//
// UVM_LT - Wait until UVM is before the given phase
// UVM_LTE - Wait until UVM is before or at the given phase
// UVM_NE - Wait until UVM is not at the given phase
// UVM_EQ - Wait until UVM is at the given phase
// UVM_GT - Wait until UVM is after the given phase
// UVM_GTE - Wait until UVM is at or after the given phase
//
enum uvmc_wait_op {
UVM_LT,
UVM_LTE,
UVM_NE,
UVM_EQ,
UVM_GT,
UVM_GTE
};
void wait_sv_ready();
} // extern "C"
//------------------------------------------------------------------------------
// UVM COMMANDS
extern "C" {
// Internal API (SV DPI Export Functions)
void UVMC_print_topology(const char* context="", int depth=-1);
bool UVMC_report_enabled (const char* context,
int verbosity,
int severity,
const char* id);
void UVMC_set_report_verbosity(int level,
const char* context,
bool recurse=0);
void UVMC_report (int severity,
const char* id,
const char* message,
int verbosity,
const char* context,
const char* filename,
int line);
// up to 64 bits
void UVMC_set_config_int (const char* context, const char* inst_name,
const char* field_name, uint64 value);
void UVMC_set_config_object (const char* type_name,
const char* context, const char* inst_name,
const char* field_name, const bits_t *value);
void UVMC_set_config_string (const char* context, const char* inst_name,
const char* field_name, const char* value);
bool UVMC_get_config_int (const char* context, const char* inst_name,
const char* field_name, uint64 *value);
bool UVMC_get_config_object (const char* type_name,
const char* context, const char* inst_name,
const char* field_name, bits_t* bits);
bool UVMC_get_config_string (const char* context, const char* inst_name,
const char* field_name, const char** value);
void UVMC_raise_objection (const char* name, const char* context="",
const char* description="", unsigned int count=1);
void UVMC_drop_objection (const char* name, const char* context="",
const char* description="", unsigned int count=1);
void UVMC_print_factory (int all_types=1);
void UVMC_set_factory_inst_override
(const char* original_type_name,
const char* override_type_name,
const char* full_inst_path);
void UVMC_set_factory_type_override (const char* original_type_name,
const char* override_type_name,
bool replace=1);
void UVMC_debug_factory_create (const char* requested_type,
const char* context="");
void UVMC_find_factory_override (const char* requested_type,
const char* context,
const char** override_type_name);
int UVMC_wait_for_phase_request(const char *phase, int state, int op);
void UVMC_get_uvm_version(unsigned int *major, unsigned int *minor, char **fix);
bool SV2C_phase_notification(int id);
bool SV2C_sv_ready();
void uvmc_set_scope(); // internal
} // extern "C"
extern "C" {
//------------------------------------------------------------------------------
// Group: Topology
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Function: uvmc_print_topology
//
// Prints the current UVM testbench topology.
//
// If called prior to UVM completing the build phase,
// the topology will be incomplete.
//
// Arguments:
//
// context - The hierarchical path of the component from which to start printing
// topology. If unspecified, topology printing will begin at
// uvm_top. Multiple components can be specified by using glob
// wildcards (* and ?), e.g. "top.env.*.driver". You can also specify
// a POSIX extended regular expression by enclosing the contxt in
// forward slashes, e.g. "/a[hp]b/". Default: "" (uvm_top)
//
// depth - The number of levels of hierarchy to print. If not specified,
// all levels of hierarchy starting from the given context are printed.
// Default: -1 (recurse all children)
//------------------------------------------------------------------------------
//
void uvmc_print_topology (const char *context="", int depth=-1);
//------------------------------------------------------------------------------
// Group: Reporting
//
// The reporting API provides the ability to issue UVM reports, set verbosity,
// and other reporting features.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Function: uvmc_report_enabled
//
// Returns true if a report at the specified verbosity, severity, and id would
// be emitted if made within the specified component contxt.
//
// The primary purpose of this command is to determine whether a report has a
// chance of being emitted before incurring the high run-time overhead of
// formatting the string message.
//
// A report at severity UVM_INFO is ignored if its verbosity is greater than
// the verbosity configured for the component in which it is issued. Reports at
// other severities are not affected by verbosity settings.
//
// If the action of a report with the specified severity and id is configured
// as UVM_NO_ACTION within the specified component contxt.
//
// Filtration by any registered report_catchers is not considered.
//
// Arguments:
//
// verbosity - The uvmc_report_verbosity of the hypothetical report.
//
// severity - The <uvmc_report_severity> of the hypothetical report.
// Default: UVM_INFO.
//
// id - The identifier string of the hypothetical report. Must be an
// exact match. If not specified, then uvmc_report_enabled checks
// only if UVM_NO_ACTION is the configured action for the given
// severity at the specified context. Default: "" (unspecified)
//
// context - The hierarchical path of the component that would issue the
// hypothetical report. If not specified, the context is global,
// i.e. uvm_top. Reports not issued by components come from uvm_top.
// Default: "" (unspecified)
//
// Example:
//
//| if (uvmc_report_enabled(UVM_HIGH, UVM_INFO, "PRINT_TRANS") {
//| string detailed_msg;
//| ...prepare message string here...
//| uvmc_report(UVM_INFO, "PRINT_TRANS", detailed_msg, UVM_HIGH);
//| }
//------------------------------------------------------------------------------
//
bool uvmc_report_enabled (int verbosity,
int severity=UVM_INFO,
const char* id="",
const char* context="");
//------------------------------------------------------------------------------
// Function: uvmc_set_report_verbosity
//
// Sets the run-time verbosity level for all UVM_INFO-severity reports issued
// by the component(s) at the specified context. Any report from the component
// context whose verbosity exceeds this maximum will be ignored.
//
// Reports issued by SC via uvmc_report are affected only by the verbosity level
// setting for the global context, i.e. context="". To have finer-grained
// control over SC-issued reports, register a uvm_report_catcher with uvm_top.
//
// Arguments:
//
// level - The verbosity level. Specify UVM_NONE, UVM_LOW, UVM_MEDIUM,
// UVM_HIGH, or UVM_FULL. Required.
//
// context - The hierarchical path of the component. Multiple components can be
// specified by using glob wildcards * and ?, e.g. "top.env.*.driver".
// You can also specify a POSIX extended regular expression by
// enclosing the contxt in forward slashes, e.g. "/a[hp]b/".
// Default: "" (uvm_top)
//
// recurse - If true, sets the verbosity of all descendents of the component(s)
// matching context. Default:false
//
// Examples:
//
// Set global UVM report verbosity to maximum (FULL) output:
//
// | uvmc_set_report_verbosity(UVM_FULL);
//
// Disable all filterable INFO reports for the top.env.agent1.driver,
// but none of its children:
//
// | uvmc_set_report_verbosity(UVM_NONE, "top.env.agent1.driver");
//
// Set report verbosity for all components to UVM_LOW, except for the
// troublemaker component, which gets UVM_HIGH verbosity:
//
// | uvmc_set_report_verbosity(UVM_LOW, true);
// | uvmc_set_report_verbosity(UVM_HIGH, "top.env.troublemaker");
//
// In the last example, the recursion flag is set to false, so all of
// troublemaker's children, if any, will remain at UVM_LOW verbosity.
//------------------------------------------------------------------------------
void uvmc_set_report_verbosity (int level,
const char* context="",
bool recurse=0);
//------------------------------------------------------------------------------
// Function: uvmc_report
//
// Send a report to UVM for processing, subject to possible filtering by
// verbosity, action, and active report catchers.
//
// See uvmc_report_enabled to learn how a report may be filtered.
//
// The UVM report mechanism is used instead of $display and other ad hoc
// approaches to ensure consistent output and to control whether a report is
// issued and what if any actions are taken when it is issued. All reporting
// methods have the same arguments, except a verbosity level is applied to
// UVM_INFO-severity reports.
//
// Arguments:
//
// severity - The report severity: specify either UVM_INFO, UVM_WARNING,
// UVM_ERROR, or UVM_FATAL. Required argument.
//
// id - The report id string, used for identification and targeted
// filtering. See context description for details on how the
// report's id affects filtering. Required argument.
//
// message - The message body, pre-formatted if necessary to a single string.
// Required.
//
// verbosity - The verbosity level indicating an INFO report's relative detail.
// Ignored for warning, error, and fatal reports. Specify UVM_NONE,
// UVM_LOW, UVM_MEDIUM, UVM_HIGH, or UVM_FULL. Default: UVM_MEDIUM.
//
// context - The hierarchical path of the SC-side component issuing the
// report. The context string appears as the hierarchical name in
// the report on the SV side, but it does not play a role in report
// filtering in all cases. All SC-side reports are issued from the
// global context in UVM, i.e. uvm_top. To apply filter settings,
// make them from that context, e.g. uvm_top.set_report_id_action().
// With the context fixed, only the report's id can be used to
// uniquely identify the SC report to filter. Report catchers,
// however, are passed the report's context and so can filter based
// on both SC context and id. Default: "" (unspecified)
//
// filename - The optional filename from which the report was issued. Use
// __FILE__. If specified, the filename will be displayed as part
// of the report. Default: "" (unspecified)
//
// line - The optional line number within filename from which the report
// was issued. Use __LINE__. If specified, the line number will be
// displayed as part of the report. Default: 0 (unspecified)
//
// Examples:
//
// Send a global (uvm_top-sourced) info report of medium verbosity to UVM:
//
// | uvmc_report(UVM_INFO, "SC_READY", "SystemC side is ready");
//
// Issue the same report, this time with low verbosity a filename and line number.
//
// | uvmc_report(UVM_INFO, "SC_READY", "SystemC side is ready",
// | UVM_LOW, "", __FILE__, __LINE__);
//
// UVM_LOW verbosity does not mean lower output. On the contrary, reports with
// UVM_LOW verbosity are printed if the run-time verbosity setting is anything
// but UVM_NONE. Reports issued with UVM_NONE verbosity cannot be filtered by
// the run-time verbosity setting.
//
// The next example sends a WARNING and INFO report from an SC-side producer
// component. In SV, we disable the warning by setting the action for its
// effective ID to UVM_NO_ACTION. We also set the verbosity threshold for INFO
// messages with the effective ID to UVM_NONE. This causes the INFO report to
// be filtered, as the run-time verbosity for reports of that particular ID are
// now much lower than the reports stated verbosity level (UVM_HIGH).
//
//| class producer : public sc_module {
//| ...
//| void run_thread() {
//| ...
//| uvmc_report(UVM_WARNING, "TransEvent",
//| "Generated error transaction.",, this.name());
//| ...
//| uvmc_report(UVM_INFO, "TransEvent",
//| "Transaction complete.", UVM_HIGH, this.name());
//| ...
//| }
//| };
//
// To filter SC-sourced reports on the SV side:
//
//| uvm_top.set_report_id_action("TransEvent@top/prod",UVM_NO_ACTION);
//| uvm_top.set_report_id_verbosity("TransEvent@top/prod",UVM_NONE);
//| uvm_top.set_report_id_verbosity("TransDump",UVM_NONE);
// |
// The last statement disables all reports to the global context (uvm_top)
// having the ID "TransDump". Note that it is currently not possible to
// set filters for reports for several contexts at once using wildcards. Also,
// the hierarchical separator for SC may be configurable in your simulator, and
// thus could affect the context provided to these commands.
//------------------------------------------------------------------------------
void uvmc_report (int severity,
const char* id,
const char* message,
int verbosity=UVM_MEDIUM,
const char* context="",
const char* filename="",
int line=0);
// Function: uvmc_report_info
//
// Equivalent to <uvmc_report> (UVM_INFO, ...)
void uvmc_report_info (const char* id,
const char* message,
int verbosity=UVM_MEDIUM,
const char* context="",
const char* filename="",
int line=0);
// Function: uvmc_report_warning
//
// Equivalent to <uvmc_report> (UVM_WARNING, ...)
void uvmc_report_warning (const char* id,
const char* message,
const char* context="",
const char* filename="",
int line=0);
// Function: uvmc_report_error
//
// Equivalent to <uvmc_report> (UVM_ERROR, ...)
void uvmc_report_error (const char* id,
const char* message,
const char* context="",
const char* filename="",
int line=0);
// Function: uvmc_report_fatal
//
// Equivalent to <uvmc_report> (UVM_FATAL, ...)
void uvmc_report_fatal (const char* id,
const char* message,
const char* context="",
const char* filename="",
int line=0);
//------------------------------------------------------------------------------
// Topic: Report Macros
//
// Convenience macros to <uvmc_report>.
// See <uvmc_report> for details on macro arguments.
//
// | UVMC_INFO (ID, message, verbosity, context)
// | UVMC_WARNING (ID, message, context)
// | UVMC_ERROR (ID, message, context)
// | UVMC_FATAL (ID, message, context)
//
//
// Before sending the report, the macros first call <uvmc_report_enabled> to
// avoid sending the report at all if its verbosity or action would prevent
// it from reaching the report server. If the report is enabled, then
// <uvmc_report> is called with the filename and line number arguments
// provided for you.
//
// Invocations of these macros must be terminated with semicolons, which is
// in keeping with the SystemC convention established for the ~SC_REPORT~
// macros. Future releases may provide a UVMC sc_report_handler that you
// can use to redirect all SC_REPORTs to UVM.
//
// Example:
//
//| UVMC_ERROR("SC_TOP/NO_CFG","Missing required config object", name());
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Group: Phasing
//
// An API that provides access UVM's phase state and the objection objects used
// to control phase progression.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Function: uvmc_wait_for_phase
//
// Wait for a UVM phase to reach a certain state.
//
// The call must be made from a SystemC process thread that is either statically
// declared via SC_THREAD or dynamically started via sc_spawn. If the latter,
// you must include the following define on the sccom command
// line: -DSC_INCLUDE_DYNAMIC_PROCESSES.
//
// Arguments:
//
// phase - The name of the phase to wait on. The built-in phase names are, in
// order of execution: build, connect, end_of_elaboration,
// start_of_simulation, run, extract, check, report. The fine-grained
// run-time phases, which run in parallel with the run phase, are, in
// order: pre_reset, reset, post_reset, pre_configure, configure,
// post_configure, pre_main, main, post_main, pre_shutdown, shutdown,
// and post_shutdown.
//
// state - The state to wait on. A phase may transition through
// ~UVM_PHASE_JUMPING~ instead of UVM_PHASE_READY_TO_END if its
// execution had been preempted by a phase jump operation. Phases
// execute in the following state order:
//
// | UVM_PHASE_STARTED
// | UVM_PHASE_EXECUTING
// | UVM_PHASE_READY_TO_END | UVM_PHASE_JUMPING
// | UVM_PHASE_ENDED
// | UVM_PHASE_DONE
//
// condition - The state condition to wait for. When state is
// ~UVM_PHASE_JUMPING~, ~condition~ must be UVM_EQ. Default is
// ~UVM_EQ~. Valid values are:
//
// | UVM_LT - Phase is before the given state.
// | UVM_LTE - Phase is before or at the given state.
// | UVM_EQ - Phase is at the given state.
// | UVM_GTE - Phase is at or after the given state.
// | UVM_GT - Phase is after the given state.
// | UVM_NE - Phase is not at the given state.
//
//
// Examples:
//
// The following example shows how to spawn threads that correspond to UVM's
// phases. Here, the ~run_phase~ method executes during the UVM's run phase.
// As any UVM component executing the run phase would do, the SC component's
// ~run_phase~ process prevents the UVM (SV-side) run phase from ending until
// it is finished by calling <uvmc_drop_objection>.
//
//| SC_MODULE(top)
//| {
//| sc_process_handle run_proc;
//|
//| SC_CTOR(top) {
//| run_proc = sc_spawn(sc_bind(&run_phase,this),"run_phase");
//| };
//|
//| void async_reset() {
//| if (run_proc != null && run_proc.valid())
//| run_proc.reset(SC_INCLUDE_DESCENDANTS);
//| }
//|
//| void run_phase() {
//| uvmc_wait_for_phase("run",UVM_PHASE_STARTED,UVM_EQ);
//| uvmc_raise_objection("run","","SC run_phase executing");
//| ...
//| uvmc_drop_objection("run","","SC run_phase finished");
//| }
//| };
//
// If ~async_reset~ is called, the run_proc process and all descendants are
// killed, then run_proc is restarted. The run_proc calls run_phase again,
// which first waits for the UVM to reach the run_phase before resuming
// its work.
//------------------------------------------------------------------------------
void uvmc_wait_for_phase(const char *phase,
uvmc_phase_state state,
uvmc_wait_op op=UVM_EQ);
//------------------------------------------------------------------------------
// Function: uvmc_raise_objection
void uvmc_raise_objection (const char* name,
const char* context="",
const char* description="",
unsigned int count=1);
// Function: uvmc_drop_objection
//
// Raise or drop an objection to ending the specified phase on behalf of the
// component at a given context. Raises can be made before the actual phase is
// executing. However, drops that move the objection count to zero must be
// avoided until the phase is actually executing, else the all-dropped
// condition will occur prematurely. Typical usage includes calling
// <uvmc_wait_for_phase>.
// Arguments:
//
// name - The verbosity level. Specify UVM_NONE, UVM_LOW, UVM_MEDIUM,
// UVM_HIGH, or UVM_FULL. Required.
//
// context - The hierarchical path of the component on whose behalf the
// specified objection is raised or dropped. Wildcards or regular
// expressions are not allowed. The context must exactly match an
// existing component's hierarchical name. Default: "" (uvm_top)
//
// description - The reason for raising or dropping the objection. This string
// is passed in all callbacks and printed when objection tracing is
// turned on. Default: ""
//
// count - The number of objections to raise or drop. Default: 1
//
// Examples:
//
// The following routine will force the specified UVM task phase to last at
// minimum number of nanoseconds, assuming SystemC and SystemVerilog are
// operating on the same timescale.
//
//| void set_min_phase_duration(const char* ph_name, sc_time min_time) {
//| uvmc_wait_for_phase(ph_name, UVM_PHASE_STARTED);
//| uvmc_raise_objection(ph_name,"","Forcing minimum run time");
//| wait(min_time);
//| uvmc_drop_objection(ph_name,"","Phase met minimum run time");
//| }
//
// Use directly as a blocking call, or use in non-blocking fashion with
// sc_spawn/sc_bind:
//
//| sc_spawn(sc_bind(&top:set_min_phase_duration, // <--func pointer
//| this,"run",sc_time(100,SC_NS)),"min_run_time");
//------------------------------------------------------------------------------
void uvmc_drop_objection (const char* name,
const char* context="",
const char* description="",
unsigned int count=1);
//------------------------------------------------------------------------------
// Group: Factory
//
// This API provides access to UVM's object and component factory.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Function: uvmc_print_factory
//
// Prints the state of the UVM factory, including registered types, instance
// overrides, and type overrides.
//
// Arguments:
//
// all_types - When all_types is 0, only type and instance overrides are
// displayed. When all_types is 1 (default), all registered
// user-defined types are printed as well, provided they have type
// names associated with them. (Parameterized types usually do not.)
// When all_types is 2, all UVM types (prefixed with uvm_) are
// included in the list of registered types.
//
// Examples:
//
// Print all type and instance overrides in the factory.
//
//| uvmc_print_factory(0);
//
// Print all type and instance overrides, plus all registered user-defined
// types.
//
//| uvmc_print_factory(1);
//
// Print all type and instance overrides, plus all registered types, including
// UVM types.
//
//| uvmc_print_factory(2);
//------------------------------------------------------------------------------
void uvmc_print_factory (int all_types=1);
//------------------------------------------------------------------------------
// Function: uvmc_set_factory_type_override
void uvmc_set_factory_type_override (const char* original_type,
const char* override_type,
bool replace=1);
// Function: uvmc_set_factory_inst_override
//
// Set a type or instance override. Instance overrides take precedence over
// type overrides. All specified types must have been registered with the
// factory.
//
// Arguments:
//
// requested_type - The name of the requested type.
//
// override_type - The name of the override type. Must be an extension of the
// requested_type.
//
// context - The hierarchical path of the component. Multiple components
// can be specified by using glob wildcards (* and ?), e.g.
// "top.env.*.driver". You can also specify a POSIX extended
// regular expression by enclosing the context string in
// forward slashes, e.g. "/a[hp]b/".
//
// replace - If true, replace any existing type override. Default: true
//
// Examples:
//
// The following sets an instance override in the UVM factory. Any component
// whose inst path matches the glob expression "e.*" that requests an object
// of type scoreboard_base (i.e. scoreboard_base:type_id::create) will instead
// get an object of type scoreboard.
//
//| uvmc_set_factory_inst_override("scoreboard_base","scoreboard","e.*");
//
// The following sets a type override in the UVM factory. Any component whose
// hierarchical path matches the glob expression "e.*" that requests an
// object of type producer_base (i.e. producer_base:type_id::create) will
// instead get an object of type producer.
//
//| uvmc_set_factory_type_override("producer_base","producer");
//
// The following sets an override chain. Given any request for an atype, a
// ctype object is returned, except for the component with hierarchical name
// "e.prod", which will get a dtype.
//
//| uvmc_set_factory_type_override("atype","btype");
//| uvmc_set_factory_type_override("btype","ctype");
//| uvmc_set_factory_inst_override("ctype","dtype","e.prod");
//------------------------------------------------------------------------------
void uvmc_set_factory_inst_override (const char* original_type,
const char* override_type,
const char* context);
//------------------------------------------------------------------------------
// Function: uvmc_debug_factory_create
//
// Display detailed information about the object type the UVM factory would
// create given a requested type and context, listing each override that was
// applied to arrive at the result.
//
// Arguments:
//
// requested - The requested type name for a hypothetical call to create.
//
// context - The hierarchical path of the object to be created, which is a
// concatenation of the parent's hierarchical name with the
// name of the object being created. Wildcards or regular
// expressions are not allowed. The context must exactly match
// an existing component's hierarchical name, or can be the
// empty string to specify global context.
//
// Example:
//
// The following example answers the question: If the component at
// hierarchical path ~env.agent1.scoreboard~ requested an object of type
// scoreboard_base, what are all the applicable overrides, and which of
// those were applied to arrive at the result?
//
//| uvmc_debug_factory_create("scoreboard_base","env.agent1.scoreboard");
//------------------------------------------------------------------------------
void uvmc_debug_factory_create (const char* requested_type,
const char* context="");
//------------------------------------------------------------------------------
// Function: uvmc_find_factory_override
//
// Returns the type name of the type that would be created by the factory given
// the requested type and context.
//
// Arguments:
//
// requested - The requested type name for a hypothetical call to create.
//
// context - The hierarchical path of the component that would make the
// request. Wildcards or regular expressions are not allowed.
// The context must exactly match an existing component's
// hierarchical name, or can be the empty string to specify
// global context.
//
// Examples:
//
// The following examples assume all types, A through D, have been registered
// with the UVM factory. Given the following overrides:
//
//| uvmc_set_type_override("B","C");
//| uvmc_set_type_override("A","B");
//| uvmc_set_inst_override("D", "C", "top.env.agent1.*");
//
// The following will display "C":
//
//| $display(uvmc_find_factory_override("A"));
//
// The following will display "D":
//
//| $display(uvmc_find_factory_override("A", "top.env.agent1.driver"));
//
// The returned string can be used in subsequent calls to
// <uvmc_set_factory_type_override> and <uvmc_set_factory_inst_override>.
//------------------------------------------------------------------------------
string uvmc_find_factory_override (const char* requested_type,
const char* context="");
//------------------------------------------------------------------------------
// Group: set_config
//------------------------------------------------------------------------------
//
// Creates or updates a configuration setting for a field at a specified
// hierarchical context.
//
// These functions establish configuration settings, storing them as resource
// entries in the resource database for later lookup by get_config calls. They
// do not directly affect the field values being targeted. As the component
// hierarchy is being constructed during UVM's build phase, components
// spring into existence and establish their context. Once its context is
// known, each component can call get_config to retrieve any configuration
// settings that apply to it.
//
// The context is specified as the concatenation of two arguments, context and
// inst_name, which are separated by a "." if both context and inst_name are
// not empty. Both context and inst_name may be glob style or regular
// expression style expressions.
//
// The name of the configuration parameter is specified by the ~field_name~
// argument.
//
// The semantic of the set methods is different when UVM is in the build phase
// versus any other phase. If a set call is made during the build phase, the
// context determines precedence in the database. A set call from a higher
// level in the hierarchy (e.g. mytop.test1) has precedence over a set call to
// the same field from a lower level (e.g. mytop.test1.env.agent). Set calls
// made at the same level of hierarchy have equal precedence, so each set call
// overwrites the field value from a previous set call.
//
// After the build phase, all set calls have the same precedence regardless of
// their hierarchical context. Each set call overwrites the value of the
// previous call.
//
// Arguments:
//
// type_name - For uvmc_set_config_object only. Specifies the type name of the
// equivalent object to set in SV. UVM Connect will utilize the
// factory to allocate an object of this type and unpack the
// serialized value into it. Parameterized classes are not
// supported.
//
// context - The hierarchical path of the component, or the empty string,
// which specifies uvm_top. Multiple components can be specified
// by using glob wildcards (* and ?), e.g. "top.env.*.driver".
// You can also specify a POSIX extended regular expression by
// enclosing the contxt in forward slashes, e.g. "/a[hp]b/".
// Default: "" (uvm_top)
//
// inst_name - The instance path of the object being configured, relative to
// the specified context(s). Can contain wildcards or be a
// regular expression.
//
// field_name - The name of the configuration parameter. Typically this name
// is the same as or similar to the variable used to hold the
// configured value in the target context(s).
//
// value - The value of the configuration parameter. Integral values
// currently cannot exceed 64 bits. Object values must have a
// uvmc_convert<object_type> specialization defined for it.
// Use of the converter convenience macros is acceptable for
// meeting this requirement.
//
// Examples:
//
// The following example sets the configuration object field at path
// "e.prod.trans" to the tr instance, which is type uvm_tlm_generic_payload.
//
//| uvmc_set_config_object("uvm_tlm_generic_payload","e.prod","","trans", tr);
//
// The next example sets the string property at hierarchical path
// "e.prod.message" to "Hello from SystemC!".
//
//| uvmc_set_config_string ("e.prod", "", "message", "Hello from SystemC!");
//
// The next example sets the integral property at hierarchical path
// "e.prod.start_addr" to hex 0x1234.
//
//| uvmc_set_config_int ("e.prod", "", "start_addr", 0x1234);
//-------------------------- |
----------------------------------------------------
// Function: uvmc_set_config_int
//
// Set an integral configuration value
//
void uvmc_set_config_int (const char* context, const char* inst_name,
const char* field_name, uint64 value);
// Function: uvmc_set_config_string
//
// Set a string configuration value
//
void uvmc_set_config_string (const char* context, const char* inst_name,
const char* field_name, const string& value);
} // extern "C"
namespace uvmc {
// Function: uvmc_set_config_object
//
// Set an object configuration value using a custom converter
//
template <class T, class CVRT>
void uvmc_set_config_object (const char* type_name,
const char* context,
const char* inst_name,
const char* field_name,
T &value,
uvmc_packer *packer=NULL) {
static bits_t bits;
static uvmc_packer def_packer;
if (packer == NULL) {
packer = &def_packer;
//packer->big_endian = 0;
}
wait_sv_ready();
packer->init_pack(bits);
CVRT::do_pack(value,packer);
svSetScope(uvmc_pkg_scope);
UVMC_set_config_object(type_name,context,inst_name,field_name,bits);
}
// Function: uvmc_set_config_object
//
// Set an object configuration value using the default converter
//
template <class T>
void uvmc_set_config_object (const char* type_name,
const char* context,
const char* inst_name,
const char* field_name,
T &value,
uvmc_packer *packer=NULL) {
static bits_t bits[UVMC_MAX_WORDS];
static uvmc_packer def_packer;
if (packer == NULL) {
packer = &def_packer;
//packer->big_endian = 0;
}
wait_sv_ready();
packer->init_pack(bits);
uvmc_converter<T>::do_pack(value,*packer);
svSetScope(uvmc_pkg_scope);
UVMC_set_config_object(type_name,context,inst_name,field_name,bits);
}
} // namespace uvmc
extern "C" {
//------------------------------------------------------------------------------
// Group: get_config
//------------------------------------------------------------------------------
//
// Gets a configuration field ~value~ at a specified hierarchical ~context~.
// Returns true if successful, false if a configuration setting could not be
// found at the given ~context~. If false, the ~value~ reference is unmodified.
//
// The ~context~ specifies the starting point for a search for a configuration
// setting for the field made at that level of hierarchy or higher. The
// ~inst_name~ is an explicit instance name relative to context and may be an
// empty string if ~context~ is the full context that the configuration
// setting applies to.
//
// The ~context~ and ~inst_name~ strings must be simple strings--no wildcards
// or regular expressions.
//
// See the section on <set_config> for the semantics
// that apply when setting configuration.
//
// Arguments:
//
// type_name - For <uvmc_get_config_object> only. Specifies the type name
// of the equivalent object to retrieve in SV. UVM Connect
// will check that the object retrieved from the configuration
// database matches this type name. If a match, the object is
// serialized (packed) and returned across the language
// boundary. Once on this side, the object data is unpacked
// into the object passed by reference via the value argument.
// Parameterized classes are not supported.
//
// context - The hierarchical path of the component on whose behalf the
// specified configuration is being retrieved. Wildcards or
// regular expressions are not allowed. The context must
// exactly match an existing component's hierarchical name,
// or be the empty string, which specifies uvm_top.
//
// inst_name - The instance path of the object being configured, relative
// to the specified context(s).
//
// field_name - The name of the configuration parameter. Typically this name
// is the same as or similar to the variable used to hold the
// configured value in the target context(s).
//
// value - The value of the configuration parameter. Integral values
// currently cannot exceed 64 bits. Object values must have a
// uvmc_convert<object_type> specialization defined for it. Use
// of the converter convenience macros is acceptable for meeting
// this requirement. The equivalent class in SV must be based
// on uvm_object and registered with the UVM factory, i.e.
// contain a `uvm_object_utils macro invocation.
//
// Examples:
//
// The following example retrieves the uvm_tlm_generic_payload configuration
// property at hierarchical path "e.prod.trans" into tr2.
//
//| uvmc_get_config_object("uvm_tlm_generic_payload","e","prod","trans", tr2);
//
// The context specification is split between the context and inst_name
// arguments. Unlike setting configuration, there is no semantic difference
// between the context and inst_name properties. When getting configuration,
// the full context is always the concatenation of the context, ".", and
// inst_name. The transaction tr2 will effectively become a copy of the
// object used to set the configuration property.
//
// The next example retrieves the string property at hierarchical path
// "e.prod.message" into local variable str.
//
//| uvmc_get_config_string ("e", "prod", "message", str);
//
// The following example retrieves the integral property at hierarchical path
// "e.prod.start_addr" into the local variable, saddr.
//
//| uvmc_get_config_int ("e.prod", "", "start_addr", saddr);
//------------------------------------------------------------------------------
// Function: uvmc_get_config_int
//
// Set an integral configuration value.
//
bool uvmc_get_config_int (const char* context, const char* inst_name,
const char* field_name, uint64 &value);
// Function: uvmc_get_config_string
//
// Set a string configuration value.
//
bool uvmc_get_config_string (const char* context, const char* inst_name,
const char* field_name, string &value);
} // extern "C"
namespace uvmc {
// Function: uvmc_get_config_object
//
// Set an object configuration value using a custom converter
//
template <class T, class CVRT>
bool uvmc_get_config_object (const char* type_name,
const char* context,
const char* inst_name,
const char* field_name,
T &value,
uvmc_packer *packer=NULL) {
static bits_t bits;
static uvmc_packer def_packer;
if (packer == NULL) {
packer = &def_packer;
//packer->big_endian = 0;
}
wait_sv_ready();
svSetScope(uvmc_pkg_scope);
if (UVMC_get_config_object(type_name,context,inst_name,field_name,bits)) {
packer->init_unpack(bits);
CVRT::do_unpack(value,packer);
return 1;
}
return 0;
}
// Function: uvmc_get_config_object
//
// Set an object configuration value using the default converter
//
template <class T>
bool uvmc_get_config_object (const char* type_name,
const char* context,
const char* inst_name,
const char* field_name,
T &value,
uvmc_packer *packer=NULL) {
static bits_t bits[UVMC_MAX_WORDS];
static uvmc_packer def_packer;
if (packer == NULL) {
packer = &def_packer;
//packer->big_endian = 0;
}
wait_sv_ready();
svSetScope(uvmc_pkg_scope);
if (UVMC_get_config_object(type_name,context,inst_name,field_name,bits)) {
packer->init_unpack(bits);
uvmc_converter<T>::do_unpack(value,*packer);
return 1;
}
return 0;
}
} // namespace uvmc
#endif // UVMC_COMMANDS_H
|
#ifndef _TB_QVM_H_
#define _TB_QVM_H_
#include <systemc.h>
#include <iomanip>
#include <iostream>
#include "global_json.h"
#include "logger_wrapper.h"
#include "q_data_type.h"
#include "quma_tb_base.h"
#include "qvm.h"
using namespace sc_core;
using namespace sc_dt;
namespace cactus {
using sc_core::sc_in;
using sc_core::sc_out;
using sc_core::sc_signal;
using sc_core::sc_vector;
using sc_dt::sc_uint;
class QVM_TB : public Quma_tb_base {
protected: // modules
QVM qvm;
protected: // signals
// it seems that we need to add no signals.
protected:
// void do_test();
protected:
unsigned int m_num_sim_cycles;
int m_num_qubits;
void config();
public:
QVM_TB(const sc_core::sc_module_name& n, unsigned int num_sim_cycles_ = 3000);
SC_HAS_PROCESS(QVM_TB);
};
} // namespace cactus
#endif
|
/***************************************************************************\
*
*
* ___ ___ ___ ___
* / /\ / /\ / /\ / /\
* / /:/ / /::\ / /::\ / /::\
* / /:/ / /:/\:\ / /:/\:\ / /:/\:\
* / /:/ / /:/~/:/ / /:/~/::\ / /:/~/:/
* / /::\ /__/:/ /:/___ /__/:/ /:/\:\ /__/:/ /:/
* /__/:/\:\ \ \:\/:::::/ \ \:\/:/__\/ \ \:\/:/
* \__\/ \:\ \ \::/~~~~ \ \::/ \ \::/
* \ \:\ \ \:\ \ \:\ \ \:\
* \ \ \ \ \:\ \ \:\ \ \:\
* \__\/ \__\/ \__\/ \__\/
*
*
*
*
* This file is part of TRAP.
*
* TRAP is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this program; if not, write to the
* Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
* or see <http://www.gnu.org/licenses/>.
*
*
*
* (c) Luca Fossati, [email protected], [email protected]
*
\***************************************************************************/
/**
* This file contains the methods necessary to communicate with GDB in
* order to debug software running on simulators. Source code takes inspiration
* from the linux kernel (sparc-stub.c) and from ac_gdb.H in the ArchC sources
* In order to debug the remote protocol (as a help in the development of this
* stub, issue the "set debug remote 1" command in GDB)
* "set remotelogfile file" logs all the remote communication on the specified file
*/
//// **** TODO: it seeems that watchpoints are completely ignored ... :-(
//// **** TODO: sometimes segmentation fault when GDB is closed while the program is
//still running; it seems there is a race condition with the GDB thread...
#ifndef GDBSTUB_HPP
#define GDBSTUB_HPP
#include <csignal>
#ifndef SIGTRAP
#define SIGTRAP 5
#endif
#ifndef SIGQUIT
#define SIGQUIT 3
#endif
#include <systemc.h>
#include <vector>
#include "trap_utils.hpp"
#include "ABIIf.hpp"
#include "ToolsIf.hpp"
#include "instructionBase.hpp"
#include "BreakpointManager.hpp"
#include "WatchpointManager.hpp"
#include "GDBConnectionManager.hpp"
#include <boost/thread/thread.hpp>
#include <boost/thread/xtime.hpp>
#include <boost/thread/condition.hpp>
#include <boost/thread/mutex.hpp>
#include <boost/lexical_cast.hpp>
#include <boost/algorithm/string.hpp>
#include <boost/circular_buffer.hpp>
namespace trap{
template<class issueWidth> class GDBStub : public ToolsIf<issueWidth>, public MemoryToolsIf<issueWidth>, public sc_module{
public:
bool simulationPaused;
private:
enum stopType {BREAK_stop=0, WATCH_stop, STEP_stop, SEG_stop, TIMEOUT_stop, PAUSED_stop, UNK_stop};
///Thread used to send and receive responses with the GDB debugger
struct GDBThread{
GDBStub<issueWidth> &gdbStub;
GDBThread(GDBStub<issueWidth> &gdbStub) : gdbStub(gdbStub){}
void operator()(){
while(!gdbStub.isKilled){
if(gdbStub.connManager.checkInterrupt()){
gdbStub.step = 2;
}
else{
//An Error happened: First of all I have to perform some cleanup
if(!gdbStub.isKilled){
boost::mutex::scoped_lock lk(gdbStub.cleanupMutex);
gdbStub.breakManager.clearAllBreaks();
gdbStub.watchManager.clearAllWatchs();
gdbStub.step = 0;
gdbStub.isConnected = false;
}
break;
}
}
}
};
///Manages connection among the GDB target stub (this class) and
///the GDB debugger
GDBConnectionManager connManager;
///Interface for communication with the internal processor's structure
ABIIf<issueWidth> &processorInstance;
///Handles the breakpoints which have been set in the system
BreakpointManager<issueWidth> breakManager;
///Handles the watchpoints which have been set in the system
WatchpointManager<issueWidth> watchManager;
///Determines whether the processor has to halt as a consequence of a
///step command
unsigned int step;
///Keeps track of the last breakpoint encountered by this processor
Breakpoint<issueWidth> * breakReached;
///Keeps track of the last watchpoint encountered by this processor
Watchpoint<issueWidth> * watchReached;
///Specifies whether the breakpoints are enabled or not
bool breakEnabled;
///Specifies whether the watchpoints are enabled or not
bool watchEnabled;
///Specifies whether GDB server side killed the simulation
bool isKilled;
///In case we decided to run the simulation only for a limited ammount of time
///this variable contains that time
double timeToGo;
///In case we decided to jump onwards or backwards for a specified ammount of time,
///this variable contains that time
double timeToJump;
///In case the simulation is run only for a specified ammount of time, this variable
///contains the simulation time at that start time
double simStartTime;
///Specifies that we have to stop because a timeout was encountered
bool timeout;
///Event used to manage execution for a specified ammount of time
sc_event pauseEvent;
///Condition used to stop processor execution until simulation is restarted
boost::condition gdbPausedEvent;
///Mutex used to access the condition
boost::mutex global_mutex;
///Sepecifies if GDB is connected to this stub or not
bool isConnected;
///Specifies that the first run is being made
bool firstRun;
///Mutex controlling the cleanup of GDB status
boost::mutex cleanupMutex;
/********************************************************************/
///Checks if a breakpoint is present at the current address and
///in case it halts execution
#ifndef NDEBUG
inline void checkBreakpoint(const issueWidth &address){
#else
inline void checkBreakpoint(const issueWidth &address) throw(){
#endif
if(this->breakEnabled && this->breakManager.hasBreakpoint(address)){
this->breakReached = this->breakManager.getBreakPoint(address);
#ifndef NDEBUG
if(this->breakReached == NULL){
THROW_EXCEPTION("I stopped because of a breakpoint, but no breakpoint was found");
}
#endif
this->setStopped(BREAK_stop);
}
}
///If true, the system is in the step mode and, as such, execution
///needs to be stopped
inline bool goingToBreak(const issueWidth &address) const throw(){
return this->breakEnabled && this->breakManager.hasBreakpoint(address);
}
///Checks if execution must be stopped because of a step command
inline void checkStep() throw(){
if(this->step == 1){
this->step++;
}
else if(this->step == 2){
this->step = 0;
if(this->timeout){
this->timeout = false;
this->setStopped(TIMEOUT_stop);
}
else{
this->setStopped(STEP_stop);
}
}
}
///If true, the system is in the step mode and, as such, execution
///needs to be stopped
inline bool goingToStep() const throw(){
return this->step == 2;
}
///Starts the thread which will manage the connection with the
///GDB debugger
void startThread(){
GDBThread thread(*this);
boost::thread th(thread);
}
///This method is called when we need asynchronously halt the
///execution of the processor this instance of the stub is
///connected to; it is usually used when a processor is halted
///and it has to communicated to the other processor that they have
///to halt too; note that this method halts SystemC execution and
///it also starts new threads (one for each processor) which will
///deal with communication with the stub; when a continue or
///step signal is met, then the receving thread is killed. When
///all the threads are killed execution can be resumed (this means
///that all GDBs pressed the resume button)
///This method is also called at the beginning of the simulation by
///the first processor which starts execution
void setStopped(stopType stopReason = UNK_stop){
//saving current simulation time
double curSimTime = sc_time_stamp().to_double();
//Now I have to behave differently depending on whether database support is enabled or not
//if it is enabled I do not stop simulation, while if it is not enabled I have to stop simulation in
//order to be able to inspect the content of the processor - memory - etc...
//Computing the next simulation time instant
if(this->timeToGo > 0){
this->timeToGo -= (curSimTime - this->simStartTime);
if(this->timeToGo < 0)
this->timeToGo = 0;
this->simStartTime = curSimTime;
}
//Disabling break and watch points
this->breakEnabled = false;
this->watchEnabled = false;
this->awakeGDB(stopReason);
//pausing simulation
while(this->waitForRequest())
;
}
///Sends a TRAP message to GDB so that it is awaken
void awakeGDB(stopType stopReason = UNK_stop){
switch(stopReason){
case STEP_stop:{
GDBResponse response;
response.type = GDBResponse::S_rsp;
response.payload = SIGTRAP;
this->connManager.sendResponse(response);
break;}
case BREAK_stop:{
#ifndef NDEBUG
if(this->breakReached == NULL){
THROW_EXCEPTION("I stopped because of a breakpoint, but it is NULL");
}
#endif
GDBResponse response;
response.type = GDBResponse::S_rsp;
response.payload = SIGTRAP;
this->connManager.sendResponse(response);
break;}
case WATCH_stop:{
#ifndef NDEBUG
if(this->watchReached == NULL){
THROW_EXCEPTION("I stopped because of a breakpoint, but it is NULL");
}
#endif
GDBResponse response;
response.type = GDBResponse::T_rsp;
response.payload = SIGTRAP;
std::pair<std::string, unsigned int> info;
info.second = this->watchReached->address;
switch(this->watchReached->type){
case Watchpoint<issueWidth>::WRITE_watch:
info.first = "watch";
break;
case Watchpoint<issueWidth>::READ_watch:
info.first = "rwatch";
break;
case Watchpoint<issueWidth>::ACCESS_watch:
info.first = "awatch";
break;
default:
info.first = "none";
break;
}
response.size = sizeof(issueWidth);
response.info.push_back(info);
this->connManager.sendResponse(response);
break;}
case SEG_stop:{
//An error has occurred during processor execution (illelgal instruction, reading out of memory, ...);
GDBResponse response;
response.type = GDBResponse::S_rsp;
response.payload = SIGILL;
this->connManager.sendResponse(response);
break;}
case TIMEOUT_stop:{
//the simulation time specified has elapsed, so simulation halted
GDBResponse resp;
resp.type = GDBResponse::OUTPUT_rsp;
resp.message = "Specified Simulation time completed - Current simulation time: " + sc_time_stamp().to_string() + " (ps)\n";
this->connManager.sendResponse(resp);
this->connManager.sendInterrupt();
break;}
case PAUSED_stop:{
//the simulation time specified has elapsed, so simulation halted
GDBResponse resp;
resp.type = GDBResponse::OUTPUT_rsp;
resp.message = "Simulation Paused - Current simulation time: " + sc_time_stamp().to_string() + " (ps)\n";
this->connManager.sendResponse(resp);
this->connManager.sendInterrupt();
break;}
default:
this->connManager.sendInterrupt();
break;
}
}
///Signals to the GDB debugger that simulation ended; the error variable specifies
///if the program ended with an error
void signalProgramEnd(bool error = false){
if(!this->isKilled || error){
GDBResponse response;
//Now I just print a message to the GDB console signaling the user that the program is ending
if(error){
//I start anyway by signaling an error
GDBResponse rsp;
rsp.type = GDBResponse::ERROR_rsp;
this->connManager.sendResponse(rsp);
}
response.type = GDBResponse::OUTPUT_rsp;
if(error){
response.message = "\nProgram Ended With an Error\n";
}
else
response.message = "\nProgram Correctly Ended\n";
this->connManager.sendResponse(response);
//Now I really communicate to GDB that the program ended
response.type = GDBResponse::W_rsp;
if(error)
response.payload = SIGABRT;
else{
extern int exitValue;
response.payload = exitValue;
}
this->connManager.sendResponse(response);
}
}
///Waits for an incoming request by the GDB debugger and, once it
///has been received, it routes it to the appropriate handler
///Returns whether we must be listening for other incoming data or not
bool waitForRequest(){
this->simulationPaused = true;
GDBRequest req = connManager.processRequest();
this->simulationPaused = false;
switch(req.type){
case GDBRequest::QUEST_req:
//? request: it asks the target the reason why it halted
return this->reqStopReason();
break;
case GDBRequest::EXCL_req:
// ! request: it asks if extended mode is supported
return this->emptyAction(req);
break;
case GDBRequest::c_req:
//c request: Continue command
return this->cont(req.address);
break;
case GDBRequest::C_req:
//C request: Continue with signal command, currently not supported
return this->emptyAction(req);
break;
case GDBRequest::D_req:
//D request: disconnection from the remote target
return this->detach(req);
break;
case GDBRequest::g_req:
//g request: read general register
return this->readRegisters();
break;
case GDBRequest::G_req:
//G request: write general register
return this->writeRegisters(req);
break;
case GDBRequest::H_req:
//H request: multithreading stuff, not currently supported
return this->emptyAction(req);
break;
case GDBRequest::i_req:
//i request: single clock cycle step; currently it is not supported
//since it requires advancing systemc by a specified ammont of
//time equal to the clock cycle (or one of its multiple) and I still
//have to think how to know the clock cycle of the processor and
//how to awake again all the processors after simulation stopped again
return this->emptyAction(req);
break;
case GDBRequest::I_req:
//i request: signal and single clock cycle step
return this->emptyAction(req);
break;
case GDBRequest::k_req:
//i request: kill application: I simply call the sc_stop method
return this->killApp();
break;
case GDBRequest::m_req:
//m request: read memory
return this->readMemory(req);
break;
case GDBRequest::M_req:
// case GDBRequest::X_req:
//M request: write memory
return this->writeMemory(req);
break;
case GDBRequest::p_req:
//p request: register read
return this->readRegister(req);
break;
case GDBRequest::P_req:
//P request: register write
return this->writeRegister(req);
break;
case GDBRequest::q_req:
//q request: generic query
return this->genericQuery(req);
break;
case GDBRequest::s_req:
//s request: single step
return this->doStep(req.address);
break;
case GDBRequest::S_req:
//S request: single step with signal
return this->emptyAction(req);
break;
case GDBRequest::t_req:
//t request: backward search: currently not supported
return this->emptyAction(req);
break;
case GDBRequest::T_req:
//T request: thread stuff: currently not supported
return this->emptyAction(req);
break;
case GDBRequest::v_req:{
//Note that I support only the vCont packets; in particular, the only
//supported actions are continue and stop
std::size_t foundCont = req.command.find("Cont");
if(foundCont == std::string::npos){
return this->emptyAction(req);
}
if(req.command.find_last_of('?') == (req.command.size() - 1)){
// Query of the supported commands: I support only the
// c, and s commands
return this->vContQuery(req);
}
else{
req.command = req.command.substr(foundCont + 5);
std::vector<std::string> lineElements;
boost::split( lineElements, req.command, boost::is_any_of(";"));
// Actual continue/step command; note that I should have only
// one element in the vCont command (since only one thread is supported)
if(lineElements.size() != 1){
GDBResponse resp;
resp.type = GDBResponse::ERROR_rsp;
this->connManager.sendResponse(resp);
return t |
rue;
}
// Here I check whether I have to issue a continue or a step command
if(lineElements[0][0] == 'c'){
return this->cont();
}
else if(lineElements[0][0] == 's'){
return this->doStep();
}
else{
GDBResponse resp;
resp.type = GDBResponse::ERROR_rsp;
this->connManager.sendResponse(resp);
return true;
}
}
break;}
case GDBRequest::z_req:
//z request: breakpoint/watch removal
return this->removeBreakWatch(req);
break;
case GDBRequest::Z_req:
//z request: breakpoint/watch addition
return this->addBreakWatch(req);
break;
case GDBRequest::INTR_req:
//received an iterrupt from GDB: I pause simulation and signal GDB that I stopped
return this->recvIntr();
break;
case GDBRequest::ERROR_req:
this->isConnected = false;
this->resumeExecution();
this->breakEnabled = false;
this->watchEnabled = false;
return false;
break;
default:
return this->emptyAction(req);
break;
}
}
///Method used to resume execution after GDB has issued
///the continue or step signal
void resumeExecution(){
//I'm going to restart execution, so I can again re-enable watch and break points
this->breakEnabled = true;
this->watchEnabled = true;
this->simStartTime = sc_time_stamp().to_double();
if(this->timeToGo > 0){
this->pauseEvent.notify(sc_time(this->timeToGo, SC_PS));
}
}
/** Here start all the methods to handle the different GDB requests **/
///It does nothing, it simply sends an empty string back to the
///GDB debugger
bool emptyAction(GDBRequest &req){
GDBResponse resp;
resp.type = GDBResponse::NOT_SUPPORTED_rsp;
this->connManager.sendResponse(resp);
return true;
}
/// Queries the supported vCont commands; only the c and s commands
/// are supported
bool vContQuery(GDBRequest &req){
GDBResponse resp;
resp.type = GDBResponse::CONT_rsp;
resp.data.push_back('c');
resp.data.push_back('s');
this->connManager.sendResponse(resp);
return true;
}
///Asks for the reason why the processor is stopped
bool reqStopReason(){
this->awakeGDB();
return true;
}
///Reads the value of a register;
bool readRegister(GDBRequest &req){
GDBResponse rsp;
rsp.type = GDBResponse::REG_READ_rsp;
try{
if(req.reg < this->processorInstance.nGDBRegs()){
issueWidth regContent = this->processorInstance.readGDBReg(req.reg);
this->valueToBytes(rsp.data, regContent);
}
else{
this->valueToBytes(rsp.data, 0);
}
}
catch(...){
this->valueToBytes(rsp.data, 0);
}
this->connManager.sendResponse(rsp);
return true;
}
///Reads the value of a memory location
bool readMemory(GDBRequest &req){
GDBResponse rsp;
rsp.type = GDBResponse::MEM_READ_rsp;
for(unsigned int i = 0; i < req.length; i++){
try{
unsigned char memContent = this->processorInstance.readCharMem(req.address + i);
this->valueToBytes(rsp.data, memContent);
}
catch(...){
std::cerr << "GDB Stub: error in reading memory at address " << std::hex << std::showbase << req.address + i << std::endl;
this->valueToBytes(rsp.data, 0);
}
}
this->connManager.sendResponse(rsp);
return true;
}
bool cont(unsigned int address = 0){
if(address != 0){
this->processorInstance.setPC(address);
}
//Now, I have to restart SystemC, since the processor
//has to go on; note that actually SystemC restarts only
//after all the gdbs has issued some kind of start command
//(either a continue, a step ...)
this->resumeExecution();
return false;
}
bool detach(GDBRequest &req){
boost::mutex::scoped_lock lk(this->cleanupMutex);
//First of all I have to perform some cleanup
this->breakManager.clearAllBreaks();
this->watchManager.clearAllWatchs();
this->step = 0;
this->isConnected = false;
//Finally I can send a positive response
GDBResponse resp;
resp.type = GDBResponse::OK_rsp;
this->connManager.sendResponse(resp);
this->resumeExecution();
this->breakEnabled = false;
this->watchEnabled = false;
return false;
}
bool readRegisters(){
//I have to read all the general purpose registers and
//send their content back to GDB
GDBResponse resp;
resp.type = GDBResponse::REG_READ_rsp;
for(unsigned int i = 0; i < this->processorInstance.nGDBRegs(); i++){
try{
issueWidth regContent = this->processorInstance.readGDBReg(i);
this->valueToBytes(resp.data, regContent);
}
catch(...){
this->valueToBytes(resp.data, 0);
}
}
this->connManager.sendResponse(resp);
return true;
}
bool writeRegisters(GDBRequest &req){
std::vector<issueWidth> regContent;
this->bytesToValue(req.data, regContent);
typename std::vector<issueWidth>::iterator dataIter, dataEnd;
bool error = false;
unsigned int i = 0;
for(dataIter = regContent.begin(), dataEnd = regContent.end();
dataIter != dataEnd; dataIter++){
try{
this->processorInstance.setGDBReg(*dataIter, i);
}
catch(...){
error = true;
}
i++;
}
GDBResponse resp;
if(i != (unsigned int)this->processorInstance.nGDBRegs() || error)
resp.type = GDBResponse::ERROR_rsp;
else
resp.type = GDBResponse::OK_rsp;
this->connManager.sendResponse(resp);
return true;
}
bool writeMemory(GDBRequest &req){
bool error = false;
unsigned int bytes = 0;
std::vector<unsigned char>::iterator dataIter, dataEnd;
for(dataIter = req.data.begin(), dataEnd = req.data.end(); dataIter != dataEnd; dataIter++){
try{
this->processorInstance.writeCharMem(req.address + bytes, *dataIter);
bytes++;
}
catch(...){
std::cerr << "Error in writing in memory " << std::hex << std::showbase << (unsigned int)*dataIter << " at address " << std::hex << std::showbase << req.address + bytes << std::endl;
error = true;
break;
}
}
GDBResponse resp;
resp.type = GDBResponse::OK_rsp;
if(bytes != (unsigned int)req.length || error){
resp.type = GDBResponse::ERROR_rsp;
}
this->connManager.sendResponse(resp);
return true;
}
bool writeRegister(GDBRequest &req){
GDBResponse rsp;
if(req.reg <= this->processorInstance.nGDBRegs()){
try{
this->processorInstance.setGDBReg(req.value, req.reg);
rsp.type = GDBResponse::OK_rsp;
}
catch(...){
rsp.type = GDBResponse::ERROR_rsp;
}
}
else{
rsp.type = GDBResponse::ERROR_rsp;
}
this->connManager.sendResponse(rsp);
return true;
}
bool killApp(){
std::cerr << std::endl << "Killing the program according to GDB request" << std::endl << std::endl;
this->isKilled = true;
sc_stop();
wait();
return true;
}
bool doStep(unsigned int address = 0){
if(address != 0){
this->processorInstance.setPC(address);
}
this->step = 1;
this->resumeExecution();
return false;
}
bool recvIntr(){
boost::mutex::scoped_lock lk(this->cleanupMutex);
this->breakManager.clearAllBreaks();
this->watchManager.clearAllWatchs();
this->step = 0;
this->isConnected = false;
return true;
}
bool addBreakWatch(GDBRequest &req){
GDBResponse resp;
switch(req.value){
case 0:
case 1:
if(this->breakManager.addBreakpoint(Breakpoint<issueWidth>::HW_break, req.address, req.length))
resp.type = GDBResponse::OK_rsp;
else
resp.type = GDBResponse::ERROR_rsp;
break;
case 2:
if(this->watchManager.addWatchpoint(Watchpoint<issueWidth>::WRITE_watch, req.address, req.length))
resp.type = GDBResponse::OK_rsp;
else
resp.type = GDBResponse::ERROR_rsp;
break;
case 3:
if(this->watchManager.addWatchpoint(Watchpoint<issueWidth>::READ_watch, req.address, req.length))
resp.type = GDBResponse::OK_rsp;
else
resp.type = GDBResponse::ERROR_rsp;
break;
case 4:
if(this->watchManager.addWatchpoint(Watchpoint<issueWidth>::ACCESS_watch, req.address, req.length))
resp.type = GDBResponse::OK_rsp;
else
resp.type = GDBResponse::ERROR_rsp;
break;
default:
resp.type = GDBResponse::NOT_SUPPORTED_rsp;
break;
}
this->connManager.sendResponse(resp);
return true;
}
bool removeBreakWatch(GDBRequest &req){
GDBResponse resp;
if(this->breakManager.removeBreakpoint(req.address) or this->watchManager.removeWatchpoint(req.address, req.length))
resp.type = GDBResponse::OK_rsp;
else
resp.type = GDBResponse::ERROR_rsp;
this->connManager.sendResponse(resp);
return true;
}
//Note that to add additional custom commands you simply have to extend the following chain of
//if clauses
bool genericQuery(GDBRequest &req){
//I have to determine the query packet; in case it is Rcmd I deal with it
GDBResponse resp;
if(req.command != "Rcmd"){
resp.type = GDBResponse::NOT_SUPPORTED_rsp;
}
else{
//lets see which is the custom command being sent
std::string::size_type spacePos = req.extension.find(' ');
std::string custComm;
if(spacePos == std::string::npos)
custComm = req.extension;
else
custComm = req.extension.substr(0, spacePos);
if(custComm == "go"){
//Ok, finally I got the right command: lets see for
//how many nanoseconds I have to execute the continue
this->timeToGo = boost::lexical_cast<double>(req.extension.substr(spacePos + 1))*1e3;
if(this->timeToGo < 0){
resp.type = GDBResponse::OUTPUT_rsp;
resp.message = "Please specify a positive offset";
this->connManager.sendResponse(resp);
resp.type = GDBResponse::NOT_SUPPORTED_rsp;
this->timeToGo = 0;
}
else
resp.type = GDBResponse::OK_rsp;
}
else if(custComm == "go_abs"){
//This command specify to go up to a specified simulation time; the time is specified in nanoseconds
this->timeToGo = boost::lexical_cast<double>(req.extension.substr(spacePos + 1))*1e3 - sc_time_stamp().to_double();
if(this->timeToGo < 0){
resp.type = GDBResponse::OUTPUT_rsp;
resp.message = "Please specify a positive offset";
this->connManager.sendResponse(resp);
resp.type = GDBResponse::NOT_SUPPORTED_rsp;
this->timeToGo = 0;
}
else{
resp.type = GDBResponse::OK_rsp;
}
}
else if(custComm == "status"){
//Returns the current status of the STUB
resp.type = GDBResponse::OUTPUT_rsp;
resp.message = "Current simulation time: " + boost::lexical_cast<std::string>((sc_time_stamp().to_default_time_units())/(sc_time(1, \
SC_US).to_default_time_units())) + " (us)\n";
if(this->timeToGo != 0)
resp.message += "Simulating for : " + boost::lexical_cast<std::string>(this->timeToGo) + " Nanoseconds\n";
this->connManager.sendResponse(resp);
resp.type = GDBResponse::OK_rsp;
}
else if(custComm == "time"){
//This command is simply a query to know the current simulation time
resp.type = GDBResponse::OUTPUT_rsp;
resp.message = "Current simulation time: " + boost::lexical_cast<std::string>((sc_time_stamp().to_default_time_units())/(sc_time(1, \
SC_US).to_default_time_units())) + " (us)\n";
this->connManager.sendResponse(resp);
resp.type = GDBResponse::OK_rsp;
}
else if(custComm == "hist"){
//Now I have to print the last n executed instructions; lets first get such number n
resp.type = GDBResponse::OUTPUT_rsp;
#ifndef ENABLE_HISTORY
resp.message = "\nInstruction History not enabled at compile time: please reconfigure the project with the --enable-history option\n\n";
#else
unsigned int histLen = 0;
try{
histLen = boost::lexical_cast<unsigned int>(req.extension.substr(spacePos + 1));
}
catch(...){
resp.message = "\nPlease specify a correct history length\n\n";
}
if(histLen > 1000){
resp.message = "\nAt maximum 1000 instructions are kept in the history\n\n";
}
// Lets now print the history
boost::circular_buffer<HistoryInstrType> & historyQueue = processorInstance.getInstructionHistory();
std::vector<std::string> histVec;
boost::circular_buffer<HistoryInstrType>::const_reverse_iterator beg, end;
unsigned int histRead = 0;
for(histRead = 0, beg = historyQueue.rbegin(), end = historyQueue.rend(); beg != end && histRead < histLen; beg++, histRead++){
histVec.push_back(beg->toStr());
}
resp.message += "\nAddress\t\tname\t\t\tmnemonic\t\tcycle\n\n";
std::vector<std::string>::const_reverse_iterator histVecBeg, histVecEnd;
unsigned int sentLines = 0;
for(histVecBeg = histVec.rbegin(), histVecEnd = histVec.rend(); histVecBeg != histVecEnd; histVecBeg++){
resp.message += *histVecBeg + "\n";
sentLines++;
if(sentLines == 5){
sentLines = 0;
this->connManager.sendResponse(resp);
resp.message = "";
}
}
#endif
this->connManager.sendResponse(resp);
resp.type = GDBResponse::OK_rsp;
}
else if(custComm == "help"){
//This command is simply a query to know the current simulation time
resp.type = GDBResponse::OUTPUT_rsp;
resp.message = "Help about the custom GDB commands available for TRAP generated simulators:\n";
resp.message += " monitor help: prints the current message\n";
resp.message += " monitor time: returns the current simulation time\n";
resp.message += " monitor status: returns the status of the simulation\n";
this->connManager.sendResponse(resp);
resp.message = " monitor hist n: prints the last n (up to a maximum of 1000) instructions\n";
resp.message += " monitor go n: after the \'continue\' command is given, it simulates for n (ns) starting from the current time\n";
resp.message += " monitor go_abs n: after the \'continue\' command is given, it simulates up to instant n (ns)\n";
this->connManager.sendResponse(resp);
resp.type = GDBResponse::OK_rsp;
}
else{
resp.type = GDBResponse::NOT_SUPPORTED_rsp;
}
}
this->connManager.sendResponse(resp);
return true;
}
///Separates the bytes which form an integer value and puts them
///into an array of bytes
template <class ValueType> void valueToBytes(std::vector<char> &byteHolder, ValueType value, bool ConvertEndian = true){
if(this->processorInstance.matchEndian() || !ConvertEndian){
for(unsigned int i = 0; i < sizeof(ValueType); i++){
byteHolder.push_back((char)((value & (0x0FF << 8*i)) >> 8*i));
}
}
else{
for(int i = sizeof(ValueType) - 1; i >= 0; i--){
byteHolder.push_back((char)((value & (0x0FF << 8*i)) >> 8*i));
}
}
}
///Converts a vector of bytes into a vector of integer values
void bytesToValue(std::vector<unsigned char> &byteHolder, std::vector<issueWidth> &values){
for(unsigned int i = 0; i < byteHolder.size(); i += sizeof(issueWidth)){
issueWidth buf = 0;
for(unsigned int k = 0; k < sizeof(issueWidth); k++){
buf |= (byteHolder[i + k] << 8*k);
}
values.push_back(buf);
}
}
public:
SC_HAS_PROCESS(GDBStub);
GDBStub(ABIIf<issueWidth> &processorInstance) :
sc_module(sc_module_name("debugger")), connManager(processorInstance.matchEndian()), processorInstance(processorInstance),
step(0), breakReached(NULL), breakEnabled(true), watchEnabled(true), isKilled(false), timeout(false), isConnected(false),
timeToGo(0), timeToJump(0), simStartTime(0), firstRun(true), simulationPaused(false){
SC_METHOD(pauseMethod);
sensitive << this->pauseEvent;
dont_initialize();
end_module();
}
///Method used to pause simulation
void pauseMethod(){
this->step = 2;
this->timeout = true;
}
///Overloading of the end_of_simulation method; it can be used to execute methods
///at the end of the simulation
void end_of_simulation(){
if(this->isConnected){
this->isKilled = false;
this->signalProgramEnd();
this->isKilled = true;
}
}
///Starts the connection with the GDB client
void initialize(unsigned int port = 1500){
this->connManager.initialize(port);
this->isConnected = true;
//Now I have to listen for incoming GDB messages; this will
//be done in a new thread.
this->startThread();
}
///Method called at eve |
ry cycle from the processor's main loop
bool newIssue(const issueWidth &curPC, const InstructionBase *curInstr) throw(){
if(!this->firstRun){
this->checkStep();
this->checkBreakpoint(curPC);
}
else{
this->firstRun = false;
this->breakEnabled = false;
this->watchEnabled = false;
while(this->waitForRequest())
;
}
return false;
}
///The debugger needs the pipeline to be empty only in case it is going to be stopped
///because, for exmple, we hitted a breakpoint or we are in step mode
bool emptyPipeline(const issueWidth &curPC) const throw(){
return !this->firstRun && (this->goingToStep() || this->goingToBreak(curPC));
}
///Method called whenever a particular address is written into memory
#ifndef NDEBUG
inline void notifyAddress(issueWidth address, unsigned int size) throw(){
#else
inline void notifyAddress(issueWidth address, unsigned int size){
#endif
if(this->watchEnabled && this->watchManager.hasWatchpoint(address, size)){
this->watchReached = this->watchManager.getWatchPoint(address, size);
#ifndef NDEBUG
if(this->watchReached == NULL){
THROW_EXCEPTION("I stopped because of a watchpoint, but no watchpoint was found");
}
#endif
this->setStopped(WATCH_stop);
}
}
};
};
#endif
|
/*
* VLSI InputSetup module to include input SRAM and Data Setup
* Step 3: implement ReadReqRun to generate a sequence of address/valids
*/
#ifndef __INPUTSETUP_H__
#define __INPUTSETUP_H__
#include <systemc.h>
#include <nvhls_int.h>
#include <nvhls_connections.h>
#include <nvhls_vector.h>
#include <ArbitratedScratchpad.h>
#include <ArbitratedScratchpad/ArbitratedScratchpadTypes.h>
#include "../SysPE/SysPE.h"
#include "../SysArray/SysArray.h"
#include "string"
SC_MODULE(InputSetup)
{
public:
sc_in_clk clk;
sc_in<bool> rst;
typedef SysPE::InputType InputType;
static const int N = SysArray::N; // # banks = N
static const int Entries = N*4; // # of entries per bank
static const int Capacity = N*Entries;
typedef ArbitratedScratchpad<InputType, Capacity, N, N, 0> MemType;
static const int IndexBits = nvhls::nbits<Entries-1>::val;
typedef NVUINTW(IndexBits) IndexType;
typedef NVUINTW(IndexBits+1) StartType;
typedef typename nvhls::nv_scvector <InputType, N> VectorType;
// Customized data type for Input Write Request
class WriteReq: public nvhls_message{
public:
VectorType data;
IndexType index;
static const unsigned int width = IndexType::width + VectorType::width;
template <unsigned int Size>
void Marshall(Marshaller<Size>& m) {
m& data;
m& index;
}
};
MemType mem_inst;
// I/O
Connections::In<WriteReq> write_req;
Connections::In<StartType> start; // Push input #col M as start signal
Connections::Out<InputType> act_in_vec[N];
// Interconnect
// We use Request/Respons datatypes req_t, rsp_t defined in ArbitratedScratchpad
// req_t:
// * type (0: LOAD, 1: STORE),
// * vailds[N],
// * addr[N],
// * data[N]
// rsp_t:
// * valids[N],
// * data[N]
// See cli_req_t, cli_rsp_t in following for details
// ~/cs148/matchlib/cmod/include/ArbitratedScratchpad/ArbitratedScratchpadTypes.h
Connections::Combinational<MemType::req_t> req_inter;
Connections::Combinational<MemType::rsp_t> rsp_inter;
SC_HAS_PROCESS(InputSetup);
InputSetup(sc_module_name name_) : sc_module(name_) {
SC_THREAD (MemoryRun);
sensitive << clk.pos();
NVHLS_NEG_RESET_SIGNAL_IS(rst);
SC_THREAD (ReadReqRun);
sensitive << clk.pos();
NVHLS_NEG_RESET_SIGNAL_IS(rst);
SC_THREAD (ReadRspRun);
sensitive << clk.pos();
NVHLS_NEG_RESET_SIGNAL_IS(rst);
}
// Handels memory R/W
void MemoryRun() {
write_req.Reset();
req_inter.ResetRead();
rsp_inter.ResetWrite();
#pragma hls_pipeline_init_interval 1
while(1) {
WriteReq write_req_reg;
MemType::req_t req_reg;
MemType::rsp_t rsp_reg;
bool input_ready[N]; // we neglect this features
bool is_read = 0, is_write = 0;
if (req_inter.PopNB(req_reg)) {
is_read = 1;
}
else if (write_req.PopNB(write_req_reg)) {
is_write = 1;
req_reg.type.val = CLITYPE_T::STORE;
#pragma hls_unroll yes
for (int i = 0; i < N; i++) {
req_reg.valids[i] = true;
req_reg.addr[i] = write_req_reg.index*N + i;
req_reg.data[i] = write_req_reg.data[i];
}
}
if (is_read || is_write) {
mem_inst.load_store(req_reg, rsp_reg, input_ready);
}
if (is_read) {
rsp_inter.Push(rsp_reg);
}
wait();
}
}
// The main process that generate read req that matches
// systolic array data setup
void ReadReqRun() {
start.Reset();
req_inter.ResetWrite();
while(1) {
StartType M;
M = start.Pop();
MemType::req_t req_reg; // Request Message
req_reg.type.val = CLITYPE_T::LOAD; // Set to load mode for read request
// With given N, M, we want to generate and push a sequence of read requests
// i.e. addr/valids that matches Systolic array data pattern
//
// For example (N=4), first read request should be reading only the
// entry 0 of first bank. Thus,
// First Read Req:
// req_reg.valids = [1, 0, 0, 0]
// req_reg.addr = [0, 0, 0, 0]
//
// Second Read Req:
// req_reg.valids = [1, 1, 0, 0]
// req_reg.addr = [4, 1, 0, 0] = [1*4, 0*4+1, 0, 0]
//
// Note that addr = N*bank_addr + bank_index
// Implement your code here!!!
#pragma hls_pipeline_init_interval 1
if(M) { // wait for start signal
int T = M + N - 1;
// for each time step
for(int t = 0; t< T; t++){
if(t<N){ // first case : entering cascade
#pragma hls_unroll yes
// for each bank id
for(int i = 0; i < N; i++){
// cascade pattern, not that i<t in the diagram
if(i<=t){
//addr = N * bank_addr + bank_id
req_reg.addr[i] = N*(t-i) + i;
//flip valid bit
req_reg.valids[i] = 1;
}else{
//should be empty and not valid
req_reg.addr[i] = 0;
req_reg.valids[i] = 0;
}
}
}
else if (t>=M){ // second case: leaving cascade
#pragma hls_unroll yes
// for each bank id
for(int i = 0; i < N; i++){
// cascade pattern, note that bank_id > t-M
if(i>t-M){
//addr = N * bank_addr + bank_id
req_reg.addr[i] = N*(t-i) + i;
//flip valid bit
req_reg.valids[i] = 1;
}else{
//should be empty and not valid
req_reg.addr[i] = 0;
req_reg.valids[i] = 0;
}
}
}
else{ // last case: middle part
#pragma hls_unroll yes
// for each bank id
for(int i = 0; i < N; i++){
//addr = N * bank_addr + bank_id
req_reg.addr[i] = N*(t-i) + i;
//flip valid bit
req_reg.valids[i] = 1;
}
}
req_inter.PushNB(req_reg);
wait();
}
}
wait();
}
}
// Push data read from SRAM to SysArray
// only push banks with valid rsp
void ReadRspRun() {
#pragma hls_unroll yes
for (int i = 0; i < N; i++) {
act_in_vec[i].Reset();
}
rsp_inter.ResetRead();
#pragma hls_pipeline_init_interval 1
while(1) {
MemType::rsp_t rsp_reg;
if (rsp_inter.PopNB(rsp_reg)) {
#pragma hls_unroll yes
for (int i = 0; i < N; i++) {
if (rsp_reg.valids[i] == true)
act_in_vec[i].Push(rsp_reg.data[i]);
}
}
wait();
}
}
};
#endif
|
/* Copyright 2017 Pedro Cuadra <[email protected]> & Meghadoot Gardi
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License. */
#ifndef SHIFT_REGISTER_H_
#define SHIFT_REGISTER_H_
#include<systemc.h>
/**
* Shift register Template
* @param width size of the shift register
*/
template<int width>
SC_MODULE (shift_register) {
/** Input CLK */
sc_in_clk clk;
/** Data in */
sc_in<sc_logic> data_in;
/** Stored value output */
sc_out<sc_lv<width> > q;
/** Stored value state */
sc_lv<width> q_state;
/**
* Shift register Process
*/
void prc_shift_register () {
// Shift value
q_state.range(0, width - 2) = q_state.range(1, width - 1);
// Take data into the register's state
q_state[width - 1] = data_in;
// Link state to the output
q = q_state;
}
/**
* Constructor
*/
SC_CTOR (shift_register) {
q_state = sc_lv<width> (sc_logic_0);
SC_METHOD (prc_shift_register);
sensitive_pos << clk;
}
};
#endif
|
#ifndef xtea_RTL_TESTBENCH_H
#define xtea_RTL_TESTBENCH_H
#include <systemc.h>
SC_MODULE(xtea_RTL_testbench) {
private:
void run();
public:
sc_in_clk clk;
sc_out< bool > rst;
sc_in<sc_uint<1> > dout_rdy; // output from xtea module
sc_in<sc_uint<32> > result0_in;
sc_in<sc_uint<32> > result1_in;
sc_out<sc_uint<1> > din_rdy; // input for xtea module
sc_out<sc_uint<32> > word0_out;
sc_out<sc_uint<32> > word1_out;
sc_out<sc_uint<32> > key0_out;
sc_out<sc_uint<32> > key1_out;
sc_out<sc_uint<32> > key2_out;
sc_out<sc_uint<32> > key3_out;
sc_out< bool > mode_out;
SC_CTOR(xtea_RTL_testbench) {
SC_THREAD(run);
sensitive << clk.pos();
}
};
#endif
|
/*
* Copyright (c) 2010 TIMA Laboratory
*
* This file is part of Rabbits.
*
* Rabbits is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* Rabbits is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Rabbits. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef _QEMU_WRAPPER_REQUEST_
#define _QEMU_WRAPPER_REQUEST_
#include <systemc.h>
class qemu_wrapper_request
{
public:
qemu_wrapper_request (unsigned id);
public:
unsigned char tid;
unsigned char ropcode;
unsigned char bDone;
unsigned char bWrite;
sc_event evDone;
unsigned long rcv_data;
qemu_wrapper_request *m_next;
};
class qemu_wrapper_requests
{
public:
qemu_wrapper_requests (int count);
~qemu_wrapper_requests ();
qemu_wrapper_request* GetNewRequest (int bWaitEmpty);
qemu_wrapper_request* GetRequestByTid (unsigned char tid);
void FreeRequest (qemu_wrapper_request *rq);
void WaitWBEmpty ();
private:
qemu_wrapper_request *m_headFree;
qemu_wrapper_request *m_headBusy;
sc_event m_evEmpty;
};
#endif
/*
* Vim standard variables
* vim:set ts=4 expandtab tw=80 cindent syntax=c:
*
* Emacs standard variables
* Local Variables:
* mode: c
* tab-width: 4
* c-basic-offset: 4
* indent-tabs-mode: nil
* End:
*/
|
/*
* Copyright (c) 2010 TIMA Laboratory
*
* This file is part of Rabbits.
*
* Rabbits is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* Rabbits is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Rabbits. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef _QEMU_WRAPPER_ACCESS_INTERFACE_
#define _QEMU_WRAPPER_ACCESS_INTERFACE_
#include <systemc.h>
class qemu_wrapper_access_interface : public sc_interface
{
public:
virtual unsigned long get_no_cpus () = 0;
virtual unsigned long get_cpu_fv_level (unsigned long cpu) = 0;
virtual void set_cpu_fv_level (unsigned long cpu, unsigned long val) = 0;
virtual void generate_swi (unsigned long cpu_mask, unsigned long swi) = 0;
virtual void swi_ack (int cpu, unsigned long swi_mask) = 0;
virtual unsigned long get_cpu_ncycles (unsigned long cpu) = 0;
virtual uint64 get_no_cycles_cpu (int cpu) = 0;
virtual unsigned long get_int_status () = 0;
virtual unsigned long get_int_enable () = 0;
virtual void set_int_enable (unsigned long val) = 0;
};
#endif
/*
* Vim standard variables
* vim:set ts=4 expandtab tw=80 cindent syntax=c:
*
* Emacs standard variables
* Local Variables:
* mode: c
* tab-width: 4
* c-basic-offset: 4
* indent-tabs-mode: nil
* End:
*/
|
// Copyright 2018 Evandro Luis Copercini
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "sdkconfig.h"
#include <cstdint>
#include <cstdio>
#include <cstdlib>
#include <cstring>
#include "esp_gap_bt_api.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include <systemc.h>
#include "info.h"
#include "btmod.h"
#if defined(CONFIG_BT_ENABLED) && defined(CONFIG_BLUEDROID_ENABLED)
#ifdef ARDUINO_ARCH_ESP32
#include "esp32-hal-log.h"
#endif
#include "BluetoothSerial.h"
#include "esp_bt.h"
#include "esp_bt_main.h"
#include "esp_gap_bt_api.h"
#include "esp_bt_device.h"
#include "esp_spp_api.h"
#include <esp_log.h>
#include "esp32-hal-log.h"
const char * _spp_server_name = "ESP32SPP";
#define RX_QUEUE_SIZE 512
#define TX_QUEUE_SIZE 32
static uint32_t _spp_client = 0;
static boolean secondConnectionAttempt;
static esp_spp_cb_t * custom_spp_callback = NULL;
static BluetoothSerialDataCb custom_data_callback = NULL;
#define INQ_LEN 0x10
#define INQ_NUM_RSPS 20
#define READY_TIMEOUT (10 * 1000)
#define SCAN_TIMEOUT (INQ_LEN * 2 * 1000)
static esp_bd_addr_t _peer_bd_addr;
static char _remote_name[ESP_BT_GAP_MAX_BDNAME_LEN + 1];
static bool _isRemoteAddressSet;
static bool _isMaster;
static esp_bt_pin_code_t _pin_code;
static int _pin_len;
static bool _isPinSet;
static bool _enableSSP;
#define SPP_RUNNING 0x01
#define SPP_CONNECTED 0x02
#define SPP_CONGESTED 0x04
#define SPP_DISCONNECTED 0x08
typedef struct {
size_t len;
uint8_t data[];
} spp_packet_t;
#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO)
static char *bda2str(esp_bd_addr_t bda, char *str, size_t size)
{
if (bda == NULL || str == NULL || size < 18) {
return NULL;
}
uint8_t *p = bda;
sprintf(str, "%02x:%02x:%02x:%02x:%02x:%02x",
p[0], p[1], p[2], p[3], p[4], p[5]);
return str;
}
#endif
static bool get_name_from_eir(uint8_t *eir, char *bdname, uint8_t *bdname_len)
{
if (!eir || !bdname || !bdname_len) {
return false;
}
uint8_t *rmt_bdname, rmt_bdname_len;
*bdname = *bdname_len = rmt_bdname_len = 0;
rmt_bdname = esp_bt_gap_resolve_eir_data(eir, ESP_BT_EIR_TYPE_CMPL_LOCAL_NAME, &rmt_bdname_len);
if (!rmt_bdname) {
rmt_bdname = esp_bt_gap_resolve_eir_data(eir, ESP_BT_EIR_TYPE_SHORT_LOCAL_NAME, &rmt_bdname_len);
}
if (rmt_bdname) {
rmt_bdname_len = rmt_bdname_len > ESP_BT_GAP_MAX_BDNAME_LEN ? ESP_BT_GAP_MAX_BDNAME_LEN : rmt_bdname_len;
memcpy(bdname, rmt_bdname, rmt_bdname_len);
bdname[rmt_bdname_len] = 0;
*bdname_len = rmt_bdname_len;
return true;
}
return false;
}
static bool btSetPin() {
esp_bt_pin_type_t pin_type;
if (_isPinSet) {
if (_pin_len) {
log_i("pin set");
pin_type = ESP_BT_PIN_TYPE_FIXED;
} else {
_isPinSet = false;
log_i("pin reset");
pin_type = ESP_BT_PIN_TYPE_VARIABLE; // pin_code would be ignored (default)
}
return (esp_bt_gap_set_pin(pin_type, _pin_len, _pin_code) == ESP_OK);
}
return false;
}
static void esp_spp_cb(esp_spp_cb_event_t event, esp_spp_cb_param_t *param)
{
/*
switch (event)
{
case ESP_SPP_INIT_EVT:
log_i("ESP_SPP_INIT_EVT");
esp_bt_gap_set_scan_mode(ESP_BT_SCAN_MODE_CONNECTABLE_DISCOVERABLE);
if (!_isMaster) {
log_i("ESP_SPP_INIT_EVT: slave: start");
esp_spp_start_srv(ESP_SPP_SEC_NONE, ESP_SPP_ROLE_SLAVE, 0, _spp_server_name);
}
break;
case ESP_SPP_SRV_OPEN_EVT://Server connection open
log_i("ESP_SPP_SRV_OPEN_EVT");
if (!_spp_client){
_spp_client = param->open.handle;
} else {
secondConnectionAttempt = true;
esp_spp_disconnect(param->open.handle);
}
break;
case ESP_SPP_CLOSE_EVT://Client connection closed
log_i("ESP_SPP_CLOSE_EVT");
if(secondConnectionAttempt) {
secondConnectionAttempt = false;
} else {
_spp_client = 0;
}
break;
case ESP_SPP_CONG_EVT://connection congestion status changed
log_v("ESP_SPP_CONG_EVT: %s", param->cong.cong?"CONGESTED":"FREE");
break;
case ESP_SPP_WRITE_EVT://write operation completed
log_v("ESP_SPP_WRITE_EVT: %u %s", param->write.len, param->write.cong?"CONGESTED":"FREE");
break;
case ESP_SPP_DATA_IND_EVT://connection received data
log_v("ESP_SPP_DATA_IND_EVT len=%d handle=%d", param->data_ind.len, param->data_ind.handle);
//esp_log_buffer_hex("",param->data_ind.data,param->data_ind.len); //for low level debug
//ets_printf("r:%u\n", param->data_ind.len);
if(custom_data_callback){
custom_data_callback(param->data_ind.data, param->data_ind.len);
}
break;
case ESP_SPP_DISCOVERY_COMP_EVT://discovery complete
log_i("ESP_SPP_DISCOVERY_COMP_EVT");
if (param->disc_comp.status == ESP_SPP_SUCCESS) {
log_i("ESP_SPP_DISCOVERY_COMP_EVT: spp connect to remote");
esp_spp_connect(ESP_SPP_SEC_AUTHENTICATE, ESP_SPP_ROLE_MASTER, param->disc_comp.scn[0], _peer_bd_addr);
}
break;
case ESP_SPP_OPEN_EVT://Client connection open
log_i("ESP_SPP_OPEN_EVT");
if (!_spp_client){
_spp_client = param->open.handle;
} else {
secondConnectionAttempt = true;
esp_spp_disconnect(param->open.handle);
}
break;
case ESP_SPP_START_EVT://server started
log_i("ESP_SPP_START_EVT");
break;
case ESP_SPP_CL_INIT_EVT://client initiated a connection
log_i("ESP_SPP_CL_INIT_EVT");
break;
default:
break;
}
if(custom_spp_callback)(*custom_spp_callback)(event, param);
*/
}
void BluetoothSerial::onData(BluetoothSerialDataCb cb){
custom_data_callback = cb;
}
static void esp_bt_gap_cb(esp_bt_gap_cb_event_t event, esp_bt_gap_cb_param_t *param)
{
/*
switch(event){
case ESP_BT_GAP_DISC_RES_EVT:
log_i("ESP_BT_GAP_DISC_RES_EVT");
#if (ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO)
char bda_str[18];
log_i("Scanned device: %s", bda2str(param->disc_res.bda, bda_str, 18));
#endif
for (int i = 0; i < param->disc_res.num_prop; i++) {
uint8_t peer_bdname_len;
char peer_bdname[ESP_BT_GAP_MAX_BDNAME_LEN + 1];
switch(param->disc_res.prop[i].type) {
case ESP_BT_GAP_DEV_PROP_EIR:
if (get_name_from_eir((uint8_t*)param->disc_res.prop[i].val, peer_bdname, &peer_bdname_len)) {
log_i("ESP_BT_GAP_DISC_RES_EVT : EIR : %s : %d", peer_bdname, peer_bdname_len);
if (strlen(_remote_name) == peer_bdname_len
&& strncmp(peer_bdname, _remote_name, peer_bdname_len) == 0) {
log_v("ESP_BT_GAP_DISC_RES_EVT : SPP_START_DISCOVERY_EIR : %s", peer_bdname, peer_bdname_len);
_isRemoteAddressSet = true;
memcpy(_peer_bd_addr, param->disc_res.bda, ESP_BD_ADDR_LEN);
esp_bt_gap_cancel_discovery();
esp_spp_start_discovery(_peer_bd_addr);
}
}
break;
case ESP_BT_GAP_DEV_PROP_BDNAME:
peer_bdname_len = param->disc_res.prop[i].len;
memcpy(peer_bdname, param->disc_res.prop[i].val, peer_bdname_len);
peer_bdname_len--; // len includes 0 terminator
log_v("ESP_BT_GAP_DISC_RES_EVT : BDNAME : %s : %d", peer_bdname, peer_bdname_len);
if (strlen(_remote_name) == peer_bdname_len
&& strncmp(peer_bdname, _remote_name, peer_bdname_len) == 0) {
log_i("ESP_BT_GAP_DISC_RES_EVT : SPP_START_DISCOVERY_BDNAME : %s", peer_bdname);
_isRemoteAddressSet = true;
memcpy(_peer_bd_addr, param->disc_res.bda, ESP_BD_ADDR_LEN);
esp_bt_gap_cancel_discovery();
esp_spp_start_discovery(_peer_bd_addr);
}
break;
case ESP_BT_GAP_DEV_PROP_COD:
log_d("ESP_BT_GAP_DEV_PROP_COD");
break;
case ESP_BT_GAP_DEV_PROP_RSSI:
log_d("ESP_BT_GAP_DEV_PROP_RSSI");
break;
default:
break;
}
if (_isRemoteAddressSet)
break;
}
break;
case ESP_BT_GAP_DISC_STATE_CHANGED_EVT:
log_i("ESP_BT_GAP_DISC_STATE_CHANGED_EVT");
break;
case ESP_BT_GAP_RMT_SRVCS_EVT:
log_i( "ESP_BT_GAP_RMT_SRVCS_EVT");
break;
case ESP_BT_GAP_RMT_SRVC_REC_EVT:
log_i("ESP_BT_GAP_RMT_SRVC_REC_EVT");
break;
case ESP_BT_GAP_AUTH_CMPL_EVT:
if (param->auth_cmpl.stat == ESP_BT_STATUS_SUCCESS) {
log_v("authentication success: %s", param->auth_cmpl.device_name);
} else {
log_e("authentication failed, status:%d", param->auth_cmpl.stat);
}
break;
case ESP_BT_GAP_PIN_REQ_EVT:
// default pairing pins
log_i("ESP_BT_GAP_PIN_REQ_EVT min_16_digit:%d", param->pin_req.min_16_digit);
if (param->pin_req.min_16_digit) {
log_i("Input pin code: 0000 0000 0000 0000");
esp_bt_pin_code_t pin_code;
memset(pin_code, '0', ESP_BT_PIN_CODE_LEN);
esp_bt_gap_pin_reply(param->pin_req.bda, true, 16, pin_code);
} else {
log_i("Input pin code: 1234");
esp_bt_pin_code_t pin_code;
memcpy(pin_code, "1234", 4);
esp_bt_gap_pin_reply(param->pin_req.bda, true, 4, pin_code);
}
break;
case ESP_BT_GAP_CFM_REQ_EVT:
log_i("ESP_BT_GAP_CFM_REQ_EVT Please compare the numeric value: %d", param->cfm_req.num_val);
esp_bt_gap_ssp_confirm_reply(param->cfm_req.bda, true);
break;
case ESP_BT_GAP_KEY_NOTIF_EVT:
log_i("ESP_BT_GAP_KEY_NOTIF_EVT passkey:%d", param->key_notif.passkey);
break;
case ESP_BT_GAP_KEY_REQ_EVT:
log_i("ESP_BT_GAP_KEY_REQ_EVT Please enter passkey!");
break;
default:
break;
}
*/
}
static bool _init_bt(const char *deviceName)
{
if (!btStarted() && !btStart()){
log_e("initialize controller failed");
return false;
}
esp_bluedroid_status_t bt_state = esp_bluedroid_get_status();
if (bt_state == ESP_BLUEDROID_STATUS_UNINITIALIZED){
if (esp_bluedroid_init()) {
log_e("initialize bluedroid failed");
return false;
}
}
if (bt_state != ESP_BLUEDROID_STATUS_ENABLED){
if (esp_bluedroid_enable()) {
log_e("enable bluedroid failed");
return false;
}
}
if (_isMaster && esp_bt_gap_register_callback(esp_bt_gap_cb) != ESP_OK) {
log_e("gap register failed");
return false;
}
/*
if (esp_spp_register_callback(esp_spp_cb) != ESP_OK){
log_e("spp register failed");
return false;
}
*/
/*
if (esp_spp_init(ESP_SPP_MODE_CB) != ESP_OK){
log_e("spp init failed");
return false;
}
*/
if (esp_bt_sleep_disable() != ESP_OK){
log_e("esp_bt_sleep_disable failed");
}
log_i("device name set");
//esp_bt_dev_set_device_name(deviceName);
if (_isPinSet) {
btSetPin();
}
if (_enableSSP) {
log_i("Simple Secure Pairing");
//esp_bt_sp_param_t param_type = ESP_BT_SP_IOCAP_MODE;
//esp_bt_io_cap_t iocap = ESP_BT_IO_CAP_IO;
//esp_bt_gap_set_security_param(param_type, &iocap, sizeof(uint8_t));
}
// the default BTA_DM_COD_LOUDSPEAKER does not work with the macOS BT stack
esp_bt_cod_t cod;
cod.major = 0b00001;
cod.minor = 0b000100;
cod.service = 0b00000010110;
if (esp_bt_gap_set_cod(cod, ESP_BT_INIT_COD) != ESP_OK) {
log_e("set cod failed");
return false;
}
return true;
}
static bool _stop_bt()
{
if (btStarted()){
/*
if(_spp_client)
esp_spp_disconnect(_spp_client);
esp_spp_deinit();
*/
esp_bluedroid_disable();
esp_bluedroid_deinit();
btStop();
}
_spp_client = 0;
return true;
}
static bool waitForConnect(int timeout) {
if(btptr == NULL) {
PRINTF_ERROR("BSER", "BTPTR not setup");
return false;
}
wait(sc_time(timeout, SC_MS), btptr->connected_ev);
if (btptr->connected_ev.triggered()) return true;
else return false;
}
/*
* Serial Bluetooth Arduino
*
* */
BluetoothSerial::BluetoothSerial()
{
local_name = "ESP32"; //default bluetooth name
}
BluetoothSerial::~BluetoothSerial(void)
{
_stop_bt();
}
bool BluetoothSerial::begin(String localName, bool isMaster)
{
_isMaster = isMaster;
if (localName.length()){
local_name = localName;
}
return _init_bt(local_name.c_str());
}
int BluetoothSerial::available(void)
{
if(btptr == NULL) {
PRINTF_ERROR("BSER", "BTPTR not setup");
return -1;
}
return BTserial.available();
}
int BluetoothSerial::peek(void)
{
if(btptr == NULL) {
PRINTF_ERROR("BSER", "BTPTR not setup");
return -1;
}
return BTserial.peek();
}
bool BluetoothSerial::hasClient(void)
{
return _spp_client > 0;
}
int BluetoothSerial::read(void)
{
if(btptr == NULL) {
PRINTF_ERROR("BSER", "BTPTR not setup");
return 0;
}
return BTserial.read();
}
size_t BluetoothSerial::write(uint8_t c)
{
if(btptr == NULL) {
PRINTF_ERROR("BSER", "BTPTR not setup");
return 0;
}
return BTserial.write(c);
}
size_t BluetoothSerial::write(const uint8_t *buffer, size_t size)
{
if (!_spp_client){
return 0;
}
if(btptr == NULL) {
PRINTF_ERROR("BSER", "BTPTR not setup");
return 0;
}
return BTserial.write((char *)buffer, size);
}
void BluetoothSerial::flush()
{
if(btptr == NULL) {
PRINTF_ERROR("BSER", "BTPTR not setup");
}
else BTserial.flush();
}
void BluetoothSerial::end()
{
_stop_bt();
}
esp_err_t BluetoothSerial::register_callback(esp_spp_cb_t * callback)
{
custom_spp_callback = callback;
return ESP_OK;
}
//Simple Secure Pairing
void BluetoothSerial::enableSSP() {
_enableSSP = true;
}
/*
* Set default parameters for Legacy Pairing
* Use fixed pin code
*/
bool BluetoothSerial::setPin(const char *pin) {
bool isEmpty = !(pin && *pin);
if (isEmpty && !_isPinSet) {
return true; // nothing to do
} else if (!isEmpty){
_pin_len = strlen(pin);
memcpy(_pin_code, pin, _pin_len);
} else {
_pin_len = 0; // resetting pin to none (default)
}
_pin_code[_pin_len] = 0;
_isPinSet = true;
if (isReady(false, READY_TIMEOUT)) {
btSetPin();
}
return true;
}
bool BluetoothSerial::connect(String remoteName)
{
if (!isReady(true, READY_TIMEOUT)) return false;
if (remoteName && remoteName.length() < 1) {
log_e("No remote name is provided");
return false;
}
disconnect();
_isRemoteAddressSet = false;
strncpy(_remote_name, remoteName.c_str(), ESP_BT_GAP_MAX_BDNAME_LEN);
_remote_name[ESP_BT_GAP_MAX_BDNAME_LEN] = 0;
log_i("master : remoteName");
// will first resolve name to address
//esp_bt_gap_set_scan_mode(ESP_BT_SCAN_MODE_CONNECTABLE_DISCOVERABLE);
//if (esp_bt_gap_start_discovery(ESP_BT_INQ_MODE_GENERAL_INQUIRY, INQ_LEN, INQ_NUM_RSPS) == ESP_OK) {
// return waitForConnect(SCAN_TIMEOUT);
//}
//return false;
return true;
}
bool BluetoothSerial::connect(uint8_t remoteAddress[])
{
if (!isReady(true, READY_TIMEOUT)) return false;
if (!remoteAddress) {
log_e("No remote address is provided");
return false;
}
disconnect();
_remote_name[0] = 0;
_isRemoteAddressSet = true;
memcpy(_peer_bd_addr, remoteAddress, ESP_BD_ADDR_LEN);
log_i("master : remoteAddress");
/*
if (esp_spp_start_discovery(_peer_bd_addr) == ESP_OK) {
return waitForConnect(READY_TIMEOUT);
}
return false;
*/
return true;
}
bool BluetoothSerial::connect()
{
if (!isReady(true, READY_TIMEOUT)) return false;
if (_isRemoteAddressSet){
disconnect();
// use resolved or set address first
log_i("master : remoteAddress");
//if (esp_spp_start_discovery(_peer_bd_addr) == ESP_OK) {
// return waitForConnect(READY_TIMEOUT);
//}
//return false;
return true;
} else if (_remote_name[0]) {
disconnect();
log_i("master : remoteName");
// will resolve name to address first - it may take a while
//esp_bt_gap_set_scan_mode(ESP_BT_SCAN_MODE_CONNECTABLE_DISCOVERABLE);
//if (esp_bt_gap_start_discovery(ESP_BT_INQ_MODE_GENERAL_INQUIRY, INQ_LEN, INQ_NUM_RSPS) == ESP_OK) {
// return waitForConnect(SCAN_TIMEOUT);
//}
//return false;
return true;
}
log_e("Neither Remote name nor address was provided");
return false;
}
bool BluetoothSerial::disconnect() {
/*
if (_spp_client) {
flush();
log_i("disconnecting");
if (esp_spp_disconnect(_spp_client) == ESP_OK) {
wait(sc_time(READY_TIMEOUT, SC_MS), btptr->disconnected_ev);
if (btptr->disconnected_ev.triggered()) return true;
else return false;
}
}
return false;
*/
return true;
}
bool BluetoothSerial::unpairDevice(uint8_t remoteAddress[]) {
if (isReady(false, READY_TIMEOUT)) {
log_i("removing bonded device");
return (esp_bt_gap_remove_bond_device(remoteAddress) == ESP_OK);
}
return false;
}
bool BluetoothSerial::connected(int timeout) {
return waitForConnect(timeout);
}
bool BluetoothSerial::isReady(bool checkMaster, int timeout) {
if (checkMaster && !_isMaster) {
log_e("Master mode is not active. Call begin(localName, true) to enable Master mode");
return false;
}
if (!btStarted()) {
log_e("BT is not initialized. Call begin() first");
return false;
}
wait(sc_time(timeout, SC_MS), btptr->running_ev);
if (btptr->running_ev.triggered()) return true;
else return false;
}
#endif
|
//**********************************************************************
// Copyright (c) 2016-2018 Xilinx Inc. All Rights Reserved
//**********************************************************************
//
// TLM wrapper for CanCat IP. It
// This is a Dummy IP and doesn't perform any real functionality. This IP will come into picture when the design is M*N Stream
//**********************************************************************
#ifndef _kr260_xlconcat_0_0_core_h_
#define _kr260_xlconcat_0_0_core_h_
#include <systemc.h>
#include "properties.h"
#define IN0_WIDTH 1
#define IN0_WIDTH 1
#define IN1_WIDTH 1
#define IN2_WIDTH 1
#define IN3_WIDTH 1
#define IN4_WIDTH 1
#define IN5_WIDTH 1
#define IN6_WIDTH 1
#define IN7_WIDTH 1
#define IN8_WIDTH 1
#define IN9_WIDTH 1
#define IN10_WIDTH 1
#define IN11_WIDTH 1
#define IN12_WIDTH 1
#define IN13_WIDTH 1
#define IN14_WIDTH 1
#define IN15_WIDTH 1
#define IN16_WIDTH 1
#define IN17_WIDTH 1
#define IN18_WIDTH 1
#define IN19_WIDTH 1
#define IN20_WIDTH 1
#define IN21_WIDTH 1
#define IN22_WIDTH 1
#define IN23_WIDTH 1
#define IN24_WIDTH 1
#define IN25_WIDTH 1
#define IN26_WIDTH 1
#define IN27_WIDTH 1
#define IN28_WIDTH 1
#define IN29_WIDTH 1
#define IN30_WIDTH 1
#define IN31_WIDTH 1
#define IN32_WIDTH 1
#define IN33_WIDTH 1
#define IN34_WIDTH 1
#define IN35_WIDTH 1
#define IN36_WIDTH 1
#define IN37_WIDTH 1
#define IN38_WIDTH 1
#define IN39_WIDTH 1
#define IN40_WIDTH 1
#define IN41_WIDTH 1
#define IN42_WIDTH 1
#define IN43_WIDTH 1
#define IN44_WIDTH 1
#define IN45_WIDTH 1
#define IN46_WIDTH 1
#define IN47_WIDTH 1
#define IN48_WIDTH 1
#define IN49_WIDTH 1
#define IN50_WIDTH 1
#define IN51_WIDTH 1
#define IN52_WIDTH 1
#define IN53_WIDTH 1
#define IN54_WIDTH 1
#define IN55_WIDTH 1
#define IN56_WIDTH 1
#define IN57_WIDTH 1
#define IN58_WIDTH 1
#define IN59_WIDTH 1
#define IN60_WIDTH 1
#define IN61_WIDTH 1
#define IN62_WIDTH 1
#define IN63_WIDTH 1
#define IN64_WIDTH 1
#define IN65_WIDTH 1
#define IN66_WIDTH 1
#define IN67_WIDTH 1
#define IN68_WIDTH 1
#define IN69_WIDTH 1
#define IN70_WIDTH 1
#define IN71_WIDTH 1
#define IN72_WIDTH 1
#define IN73_WIDTH 1
#define IN74_WIDTH 1
#define IN75_WIDTH 1
#define IN76_WIDTH 1
#define IN77_WIDTH 1
#define IN78_WIDTH 1
#define IN79_WIDTH 1
#define IN80_WIDTH 1
#define IN81_WIDTH 1
#define IN82_WIDTH 1
#define IN83_WIDTH 1
#define IN84_WIDTH 1
#define IN85_WIDTH 1
#define IN86_WIDTH 1
#define IN87_WIDTH 1
#define IN88_WIDTH 1
#define IN89_WIDTH 1
#define IN90_WIDTH 1
#define IN91_WIDTH 1
#define IN92_WIDTH 1
#define IN93_WIDTH 1
#define IN94_WIDTH 1
#define IN95_WIDTH 1
#define IN96_WIDTH 1
#define IN97_WIDTH 1
#define IN98_WIDTH 1
#define IN99_WIDTH 1
#define IN100_WIDTH 1
#define IN101_WIDTH 1
#define IN102_WIDTH 1
#define IN103_WIDTH 1
#define IN104_WIDTH 1
#define IN105_WIDTH 1
#define IN106_WIDTH 1
#define IN107_WIDTH 1
#define IN108_WIDTH 1
#define IN109_WIDTH 1
#define IN110_WIDTH 1
#define IN111_WIDTH 1
#define IN112_WIDTH 1
#define IN113_WIDTH 1
#define IN114_WIDTH 1
#define IN115_WIDTH 1
#define IN116_WIDTH 1
#define IN117_WIDTH 1
#define IN118_WIDTH 1
#define IN119_WIDTH 1
#define IN120_WIDTH 1
#define IN121_WIDTH 1
#define IN122_WIDTH 1
#define IN123_WIDTH 1
#define IN124_WIDTH 1
#define IN125_WIDTH 1
#define IN126_WIDTH 1
#define IN127_WIDTH 1
class kr260_xlconcat_0_0_core : public sc_module
{
public:
kr260_xlconcat_0_0_core (sc_core::sc_module_name nm, const xsc::common_cpp::properties& props)
: sc_module(nm)
, In0 ( "In0" )
, In1 ( "In1" )
, In2 ( "In2" )
, In3 ( "In3" )
, In4 ( "In4" )
, In5 ( "In5" )
, In6 ( "In6" )
, In7 ( "In7" )
, In8 ( "In8" )
, In9 ( "In9" )
, In10 ( "In10" )
, In11 ( "In11" )
, In12 ( "In12" )
, In13 ( "In13" )
, In14 ( "In14" )
, dout ( "dout" )
{
SC_HAS_PROCESS(kr260_xlconcat_0_0_core);
SC_METHOD(concate_input_port_values);
sensitive << In0
<< In1
<< In2
<< In3
<< In4
<< In5
<< In6
<< In7
<< In8
<< In9
<< In10
<< In11
<< In12
<< In13
<< In14 ;
dont_initialize();
}
virtual ~kr260_xlconcat_0_0_core() = default;
void concate_input_port_values()
{
sc_bv <15> portConcateVal;
portConcateVal.range(0,0) = In0.read();
portConcateVal.range(1,1) = In1.read();
portConcateVal.range(2,2) = In2.read();
portConcateVal.range(3,3) = In3.read();
portConcateVal.range(4,4) = In4.read();
portConcateVal.range(5,5) = In5.read();
portConcateVal.range(6,6) = In6.read();
portConcateVal.range(7,7) = In7.read();
portConcateVal.range(8,8) = In8.read();
portConcateVal.range(9,9) = In9.read();
portConcateVal.range(10,10) = In10.read();
portConcateVal.range(11,11) = In11.read();
portConcateVal.range(12,12) = In12.read();
portConcateVal.range(13,13) = In13.read();
portConcateVal.range(14,14) = In14.read();
dout.write(portConcateVal);
}
public:
sc_in< sc_bv<IN0_WIDTH> > In0;
sc_in< sc_bv<IN1_WIDTH> > In1;
sc_in< sc_bv<IN2_WIDTH> > In2;
sc_in< sc_bv<IN3_WIDTH> > In3;
sc_in< sc_bv<IN4_WIDTH> > In4;
sc_in< sc_bv<IN5_WIDTH> > In5;
sc_in< sc_bv<IN6_WIDTH> > In6;
sc_in< sc_bv<IN7_WIDTH> > In7;
sc_in< sc_bv<IN8_WIDTH> > In8;
sc_in< sc_bv<IN9_WIDTH> > In9;
sc_in< sc_bv<IN10_WIDTH> > In10;
sc_in< sc_bv<IN11_WIDTH> > In11;
sc_in< sc_bv<IN12_WIDTH> > In12;
sc_in< sc_bv<IN13_WIDTH> > In13;
sc_in< sc_bv<IN14_WIDTH> > In14;
sc_out< sc_bv <15> > dout;
};
#endif
|
/*******************************************************************************
* spimod.h -- Copyright 2020 (c) Glenn Ramalho - RFIDo Design
*******************************************************************************
* Description:
* Models a single ESP32 SPI
*******************************************************************************
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
#ifndef _SPIMOD_H
#define _SPIMOD_H
#include <systemc.h>
#include "soc/spi_struct.h"
SC_MODULE(spimod) {
public:
sc_out<bool> d_oen_o {"d_oen_o"};
sc_out<bool> d_o {"d_o"};
sc_in<bool> d_i {"d_i"};
sc_out<bool> q_oen_o {"q_oen_o"};
sc_out<bool> q_o {"q_o"};
sc_in<bool> q_i {"q_i"};
sc_out<bool> cs0_oen_o {"cs0_oen_o"};
sc_out<bool> cs0_o {"cs0_o"};
sc_in<bool> cs0_i {"cs0_i"};
sc_out<bool> cs1_oen_o {"cs1_oen_o"};
sc_out<bool> cs1_o {"cs1_o"};
sc_in<bool> cs1_i {"cs1_i"};
sc_out<bool> cs2_oen_o {"cs2_oen_o"};
sc_out<bool> cs2_o {"cs2_o"};
sc_in<bool> cs2_i {"cs2_i"};
sc_out<bool> clk_oen_o {"clk_oen_o"};
sc_out<bool> clk_o {"clk_o"};
sc_in<bool> clk_i {"clk_i"};
sc_out<bool> wp_oen_o {"wp_oen_o"};
sc_out<bool> wp_o {"wp_o"};
sc_in<bool> wp_i {"wp_i"};
sc_out<bool> hd_oen_o {"hd_oen_o"};
sc_out<bool> hd_o {"hd_o"};
sc_in<bool> hd_i {"hd_i"};
/* Registers */
sc_signal<uint32_t> ctrl {"ctrl"};
sc_signal<uint32_t> ctrl2 {"ctrl2"};
sc_signal<uint32_t> clock {"clock"};
sc_signal<uint32_t> pin {"pin"};
sc_signal<uint32_t> slave {"slave"};
sc_signal<uint32_t> slave1 {"slave1"};
sc_signal<uint32_t> slave2 {"slave2"};
sc_signal<uint32_t> slv_wr_status {"slv_wr_status"};
sc_signal<uint32_t> slv_wrbuf_dlen {"slv_wrbuf_dlen"};
sc_signal<uint32_t> slv_rdbuf_dlen {"slv_rdbuf_dlen"};
sc_signal<uint32_t> slv_rd_bit {"slv_rd_bit"};
sc_signal<uint32_t> cmd {"cmd"};
sc_signal<uint32_t> addr {"addr"};
sc_signal<uint32_t> user {"user"};
sc_signal<uint32_t> user1 {"user1"};
sc_signal<uint32_t> user2 {"user2"};
sc_signal<uint32_t> mosi_dlen {"mosi_dlen"};
sc_signal<uint32_t> miso_dlen {"miso_dlen"};
/* Signals */
sc_signal<bool> master {"master"};
/* Variables */
spi_dev_t *spistruct;
bool actclk;
int dlywr, dlyrd;
int precycwr, precycrd;
int startbit, startbitrd;
int lastbit, lastbitrd;
bool wrlittleendian, rdlittleendian;
bool wrmsbfirst, rdmsbfirst;
sc_event update_ev, start_ev, reset_ev, lowerusrbit_ev;
sc_time period, hightime, lowtime;
/* Simulation Interface Functions */
void update();
void waitdone();
void configure(spi_dev_t *_spistruct);
void trace(sc_trace_file *tf);
/* Internal Functions */
private:
void start_of_simulation();
int calcnextbit(int bitpos, bool littleendian, bool msbfirst);
int converttoendian(bool littleendian, bool msbfirst, int pos);
int getdly(int mode);
void activatecs(bool withdelay);
void deactivatecs(bool withdelay);
void setupmasterslave();
void setupmaster();
void setupslave();
/* Threads */
public:
void update_th();
void return_th();
void transfer_th();
void configure_meth();
// Constructor
SC_CTOR(spimod) {
spistruct = NULL;
actclk = false;
SC_THREAD(update_th);
sensitive << update_ev << lowerusrbit_ev;
SC_THREAD(return_th);
sensitive << slv_wr_status;
SC_THREAD(transfer_th);
SC_METHOD(configure_meth);
sensitive << reset_ev << slave;
}
};
extern spimod *hspiptr;
extern spimod *vspiptr;
#endif
|
#pragma once
#include <systemc.h>
SC_MODULE(EdgeDetector) {
enum ed_icm_mode {
Any,
Pos,
Neg
};
sc_in<bool> clk_i;
sc_in<sc_uint<3>> icm_i;
sc_in<bool> ins_i;
sc_out<bool> ins_o;
SC_HAS_PROCESS(EdgeDetector);
EdgeDetector(sc_module_name nm);
~EdgeDetector() = default;
private:
bool reg_prev_ins;
void on_clk();
ed_icm_mode get_mode();
};
|
#ifdef EDGE_DETECTOR_AT_EN
#ifndef SOBEL_EDGE_DETECTOR_HPP
#define SOBEL_EDGE_DETECTOR_HPP
#include <systemc.h>
#include "address_map.hpp"
SC_MODULE(Edge_Detector)
{
#ifndef USING_TLM_TB_EN
sc_inout<sc_uint<64>> data;
sc_in<sc_uint<24>> address;
#else
sc_uint<64> data;
sc_uint<64> address;
#endif // USING_TLM_TB_EN
const double delay_full_adder_1_bit = 0.361;
const double delay_full_adder = delay_full_adder_1_bit * 16;
const double delay_multiplier = 9.82;
const sc_int<16> sobelGradientX[3][3] = {{-1, 0, 1},
{-2, 0, 2},
{-1, 0, 1}};
const sc_int<16> sobelGradientY[3][3] = {{-1, -2, -1},
{ 0, 0, 0},
{ 1, 2, 1}};
sc_int<16> localWindow[3][3];
sc_int<16> resultSobelGradientX;
sc_int<16> resultSobelGradientY;
sc_int<16> localMultX[3][3];
sc_int<16> localMultY[3][3];
sc_event gotLocalWindow;
sc_event rd_t, wr_t;
sc_event mult_x, mult_y, sum_x, sum_y;
SC_CTOR(Edge_Detector)
{
SC_THREAD(wr);
SC_THREAD(rd);
SC_THREAD(compute_sobel_gradient_x);
SC_THREAD(compute_sobel_gradient_y);
SC_THREAD(perform_mult_gradient_x);
SC_THREAD(perform_mult_gradient_y);
SC_THREAD(perform_sum_gradient_x);
SC_THREAD(perform_sum_gradient_y);
}
virtual void write();
virtual void read();
virtual void wr();
void rd();
void compute_sobel_gradient_x();
void compute_sobel_gradient_y();
void perform_mult_gradient_x();
void perform_mult_gradient_y();
void perform_sum_gradient_x();
void perform_sum_gradient_y();
};
#endif // SOBEL_EDGE_DETECTOR_HPP
#endif // EDGE_DETECTOR_AT_EN
|
// ================================================================
// NVDLA Open Source Project
//
// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
// NVDLA Open Hardware License; Check "LICENSE" which comes with
// this distribution for more information.
// ================================================================
// File Name: NV_NVDLA_pdp.h
#ifndef _NV_NVDLA_PDP_H_
#define _NV_NVDLA_PDP_H_
#define SC_INCLUDE_DYNAMIC_PROCESSES
#include <systemc.h>
#include <tlm.h>
#include "tlm_utils/multi_passthrough_initiator_socket.h"
#include "tlm_utils/multi_passthrough_target_socket.h"
#include "scsim_common.h"
#include "nvdla_dma_wr_req_iface.h"
#include "systemc.h"
#include "nvdla_xx2csb_resp_iface.h"
#include "NV_NVDLA_pdp_base.h"
#include "pdp_reg_model.h"
#include "pdp_rdma_reg_model.h"
#include "NvdlaDataFormatConvertor.h"
#define PDP_RDMA_TRANSACTION_SIZE_GRANULARITY 32
#define PDP_RDMA_BUFFER_CMOD_ENTRY_GRANULARITY 4
#define PDP_WDMA_BUFFER_SIZE 256
#define PDP_CVT_OUT_BIT_WIDTH 16
#define PDP_CVT_OUT_NUMBER 8
#define PDP_GROUP_SIZE_IN_BYTE 32
#define MAX_MEM_TRANSACTION_SIZE 256
#define KERNEL_PER_GROUP_INT8 32
#define KERNEL_PER_GROUP_INT16 16
#define KERNEL_PER_GROUP_FP16 16
#define KERNEL_PER_GROUP_SIZE 32
#define SDP2PDP_ELEMENT_NUM 8
#define SDP2PDP_ELEMENT_BIT_WIDTH 16
#define PDP_WRITE_DMA_SUB_TRANSACTION_SIZE 64
#define DATA_FORMAT_IS_INT8 0
#define DATA_FORMAT_IS_INT16 1
#define DATA_FORMAT_IS_FP16 2
#define ELEMENT_SIZE_INT8 1
#define ELEMENT_SIZE_INT16 2
#define ELEMENT_SIZE_FP16 2
#define ELEMENT_PER_ATOM_INT8 32
#define ELEMENT_PER_ATOM_INT16 16
#define ELEMENT_PER_ATOM_FP16 16
#define TAG_CMD 0
#define TAG_DATA 1
#define ATOM_CUBE_SIZE 32
#define PDP_RDMA_BUFFER_TOTAL_SIZE 32*8192
#define PDP_RDMA_BUFFER_ENTRY_SIZE ATOM_CUBE_SIZE
#define PDP_RDMA_BUFFER_ENTRY_NUM PDP_RDMA_BUFFER_TOTAL_SIZE/PDP_RDMA_BUFFER_ENTRY_SIZE
#define SDP2PDP_PAYLOAD_SIZE 32
#define SDP2PDP_PAYLOAD_ELEMENT_NUM 16
#define SDP2PDP_FIFO_ENTRY_NUM 16 // ATOM_CUBE_SIZE/SDP2PDP_PAYLOAD_SIZE
#define PDP_LINE_BUFFER_INT8_ELEMENT_NUM 8*1024
#define PDP_LINE_BUFFER_INT16_ELEMENT_NUM 4*1024
#define PDP_LINE_BUFFER_FP16_ELEMENT_NUM 4*1024
#define PDP_LINE_BUFFER_PHYSICAL_BUFFER_NUM 8
#define PDP_LINE_BUFFER_SIZE (PDP_LINE_BUFFER_INT8_ELEMENT_NUM*2)
#define PDP_LINE_BUFFER_ENTRY_NUM (PDP_LINE_BUFFER_SIZE)/(ATOM_CUBE_SIZE*2) //Each atom consumes 64Bytes
#define POOLING_FLYING_MODE_ON_FLYING NVDLA_PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_ON_FLYING
#define POOLING_FLYING_MODE_OFF_FLYING NVDLA_PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_OFF_FLYING
#define POOLING_METHOD_AVE NVDLA_PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_POOLING_METHOD_AVERAGE
#define POOLING_METHOD_MAX NVDLA_PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_POOLING_METHOD_MAX
#define POOLING_METHOD_MIN NVDLA_PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_POOLING_METHOD_MIN
#define DATA_TYPE_IS_INT 0
#define DATA_TYPE_IS_FLOAT 1
#define PDP_MAX_PADDING_SIZE 7
// class NvdlaDataFormatConvertor;
SCSIM_NAMESPACE_START(clib)
// clib class forward declaration
SCSIM_NAMESPACE_END()
SCSIM_NAMESPACE_START(cmod)
// class container_payload_wrapper {
// public:
// uint8_t *data;
// uint8_t data_num;
// };
//
// std::ostream& operator<<(std::ostream& out, const container_payload_wrapper& obj) {
// return out << "Just to fool compiler" << endl;
// }
//
// std::ostream& operator<<(std::ostream& out, const nvdla_container_number_8_bit_width_16_t& obj) {
// return out << "Just to fool compiler" << endl;
// }
class pdp_ack_info {
public:
bool is_mc;
uint8_t group_id;
};
class NV_NVDLA_pdp:
public NV_NVDLA_pdp_base, // ports
private pdp_reg_model, // pdp register accessing
private pdp_rdma_reg_model // pdp_rdma
{
public:
SC_HAS_PROCESS(NV_NVDLA_pdp);
NV_NVDLA_pdp( sc_module_name module_name );
~NV_NVDLA_pdp();
// CSB request transport implementation shall in generated code
void csb2pdp_req_b_transport (int ID, NV_MSDEC_csb2xx_16m_secure_be_lvl_t* payload, sc_time& delay);
void csb2pdp_rdma_req_b_transport (int ID, NV_MSDEC_csb2xx_16m_secure_be_lvl_t* payload, sc_time& delay);
void sdp2pdp_b_transport(int ID, nvdla_sdp2pdp_t* payload, sc_core::sc_time& delay);
void mcif2pdp_rd_rsp_b_transport(int ID, nvdla_dma_rd_rsp_t*, sc_core::sc_time&);
void cvif2pdp_rd_rsp_b_transport(int ID, nvdla_dma_rd_rsp_t*, sc_core::sc_time&);
// void pdp2csb_resp_b_transport(nvdla_xx2csb_resp_t* payload, sc_time& delay) {NV_NVDLA_pdp_base::pdp2csb_resp_b_transport(payload, delay);}
// void pdp_rdma2csb_resp_b_transport(nvdla_xx2csb_resp_t* payload, sc_time& delay) {NV_NVDLA_pdp_base::pdp2csb_resp_b_transport(payload, delay);}
private:
// Payloads
nvdla_dma_wr_req_t *dma_wr_req_cmd_payload_;
nvdla_dma_wr_req_t *dma_wr_req_data_payload_;
nvdla_dma_rd_req_t *dma_rd_req_payload_;
// Delay
sc_core::sc_time dma_delay_;
sc_core::sc_time csb_delay_;
sc_core::sc_time b_transport_delay_;
// Events
// PDP config evaluation is done
sc_event event_pdp_config_evaluation_done;
// Receiving data from sdp
sc_event event_got_conv_data;
// Functional logic have fetched data from RDMA buffer
sc_event event_functional_logic_got_data;
sc_event rdma_read_event;
sc_event rdma_write_event;
// For PDP hardware layer kickoff and end
sc_event pdp_rdma_kickoff_;
sc_event pdp_rdma_done_;
sc_event pdp_kickoff_;
sc_event pdp_done_;
sc_core::sc_fifo<uint8_t> *line_buffer_usage_free_[PDP_LINE_BUFFER_ENTRY_NUM];
sc_core::sc_fifo<uint8_t> *line_buffer_usage_available_;
// sc_event *line_buffer_usage_free_read_event;
// sc_event *line_buffer_usage_free_write_event;
// sc_mutex line_buffer_data_ready_;
// uint32_t line_buffer_data_num_;
sc_core::sc_fifo<uint8_t> *line_buffer_ready_[PDP_LINE_BUFFER_ENTRY_NUM];
// Evaluated configs based on register config
uint32_t pdp_rdma_operation_mode_;
uint32_t pdp_operation_mode_;
bool pdp_ready_to_receive_data_;
// Temperal and intermedia signals
bool is_there_ongoing_csb2pdp_response_;
bool is_there_ongoing_csb2pdp_rdma_response_;
// Variables needs to be added to register
// uint8_t pdp_rdma_kernel_stride_width_;
// uint8_t pdp_rdma_kernel_width_;
// uint8_t pdp_rdma_pad_width_;
uint32_t pdp_cvt_offset_input_;
uint16_t pdp_cvt_scale_input_;
uint8_t pdp_cvt_truncate_lsb_input_;
uint8_t pdp_cvt_truncate_msb_input_;
sc_core::sc_fifo <uint8_t *> *spd2pdp_fifo_;
sc_core::sc_fifo <uint8_t *> *rdma_buffer_;
sc_core::sc_fifo <uint8_t *> *wdma_buffer_;
sc_core::sc_fifo <pdp_ack_info *> *pdp_ack_fifo_;
sc_event pdp_mc_ack_;
sc_event pdp_cv_ack_;
bool is_mc_ack_done_;
bool is_cv_ack_done_;
// RDMA buffer index
uint32_t rdma_buffer_write_idx_;
uint32_t rdma_buffer_read_idx_;
// WDMA buffer index
uint32_t wdma_buffer_write_idx_;
uint32_t wdma_buffer_read_idx_;
// Data buffers
// # Shared line buffer, each entry stores one int8 element
// In HW, its size is 8KB. In CMOD, it's 16KB. The num of entries are same as HW, however each entry size is 16B, not 8B for precision in arithmetic.
uint16_t line_buffer_[PDP_LINE_BUFFER_INT8_ELEMENT_NUM];
uint16_t line_operation_buffer_[8*ELEMENT_PER_ATOM_INT8];
// Function declaration
// # Threads
void PdpRdmaConsumerThread();
void PdpConsumerThread();
void PoolingStage0SequenceThread ();
void PoolingStage1SequenceThread ();
void PdpRdmaSequenceThread ();
void PdpWdmaSequenceThread ();
void PdpIntrThread();
void WriteResponseThreadMc();
void WriteResponseThreadCv();
// # Config evaluation
void PdpRdmaConfigEvaluation(CNVDLA_PDP_RDMA_REGSET *register_group_ptr);
void PdpConfigEvaluation(CNVDLA_PDP_REGSET *register_group_ptr);
// # Hardware layer execution trigger
void PdpRdmaHardwareLayerExecutionTrigger();
void PdpHardwareLayerExecutionTrigger();
// # Operation
void OperationModePdpRdmaCommon();
void OperationModePdpCommon();
void RdmaSequenceCommon(uint64_t src_base_addr, uint32_t cube_in_width);
// void RdmaSequence8Bto8B();
// void RdmaSequence16Bto16B();
// void RdmaSequence8Bto16B();
void RdmaSequence16Bto8B();
// Pooling function
void PoolingStage0SequenceCommon(uint32_t cube_in_width, uint32_t pad_left, uint32_t pad_right, uint32_t acc_subcube_out_width, uint32_t cube_out_width);
void PoolingStage0Sequence8Bto8B();
void PoolingStage0Sequence16Bto16B();
void PoolingStage1SequenceCommon(uint32_t cube_out_width, uint32_t acc_subcube_out_width, uint32_t pad_left, uint32_t pad_right, uint32_t cube_in_width);
void PoolingStage1Sequence8Bto8B();
void PoolingStage1Sequence16Bto16B();
// void WdmaSequenceCommon();
void WdmaSequenceCommon(uint64_t dst_base_addr, uint32_t cube_out_width, bool split_last);
// # Functional functions
// Send DMA read request
void SendDmaReadRequest(nvdla_dma_rd_req_t* payload, sc_time& delay);
// void SendDmaReadRequest(nvdla_dma_rd_req_t* payload, sc_time& delay, uint8_t src_ram_type);
// Extract DMA read response payload
void ExtractDmaPayload(nvdla_dma_rd_rsp_t* payload);
// Send DMA write request
void SendDmaWriteRequest(nvdla_dma_wr_req_t* payload, sc_time& delay, bool ack_required = false);
void SendDmaWriteRequest(uint64_t payload_addr, uint32_t payload_size, uint32_t payload_atom_num, bool ack_required = false);
// template <typename T>
// void FetchInputData (uint8_t * atomic_cube);
uint8_t * FetchInputData ();
template <typename T_IN, typename T_OUT, typename T_PAD>
void PoolingStage0Calc (T_IN * atomic_data_in, T_OUT * line_buffer_ptr, uint32_t cube_out_width_idx, uint32_t cube_out_height_idx, uint32_t surface, uint32_t cube_in_height, uint32_t kernel_height_iter, uint32_t kernel_height, uint32_t cube_in_height_iter, T_PAD * padding_value_ptr, uint8_t element_num, uint32_t surface_num, uint32_t acc_subcube_out_width, uint32_t cube_out_width);
template <typename T_OUT, typename T_IN>
void PoolingStage1Calc (T_OUT * atomic_data_out, T_IN * line_buffer_ptr, uint32_t width, uint32_t height, uint32_t surface, uint8_t element_num, uint32_t surface_num, uint32_t acc_subcube_out_width, uint32_t cube_out_width, uint32_t pad_left, uint32_t pad_right, uint32_t cube_in_width);
template <typename T_IN, typename T_OUT, typename T_PAD>
void LineOperation (T_IN * atomic_data_in, T_OUT * line_buffer_ptr, uint32_t kernel_width_iter, uint32_t kernel_width, uint32_t cube_in_width_iter, uint32_t cube_in_width, T_PAD * padding_value_ptr, uint8_t element_num, uint32_t pad_left);
// ## Reset
void Reset();
void WaitUntilRdmaBufferFreeSizeGreaterThan(uint32_t num);
void WaitUntilRdmaBufferAvailableSizeGreaterThan(uint32_t num);
void WaitUntilWdmaBufferFreeSizeGreaterThan(uint32_t num);
void WaitUntilWdmaBufferAvailableSizeGreaterThan(uint32_t num);
void PdpSendCsbResponse(uint8_t type, uint32_t data, uint8_t error_id);
void PdpRdmaSendCsbResponse(uint8_t type, uint32_t data, uint8_t error_id);
bool IsFirstElement(uint32_t pad_left, uint32_t width_iter, uint32_t height_iter, uint32_t kernel_width_iter, uint32_t kernel_height_iter);
bool IsLastElement(uint32_t cube_in_width, uint32_t pad_left, uint32_t width_iter, uint32_t height_iter, uint32_t kernel_width_iter, uint32_t kernel_height_iter);
bool IsContributeToANewLine(uint32_t cube_in_height_iter, uint32_t kernel_height_iter);
template <typename T_IN, typename T_OUT>
void int_sign_extend(T_IN original_value, uint8_t sign_bit_idx, uint8_t extended_bit_num, T_OUT *return_value);
void reset_stats_regs();
void update_stats_regs();
uint32_t nan_input_num;
uint32_t inf_input_num;
uint32_t nan_output_num;
};
SCSIM_NAMESPACE_END()
extern "C" scsim::cmod::NV_NVDLA_pdp * NV_NVDLA_pdpCon(sc_module_name module_name);
#endif
|
// ================================================================
// NVDLA Open Source Project
//
// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
// NVDLA Open Hardware License; Check "LICENSE" which comes with
// this distribution for more information.
// ================================================================
// File Name: NV_NVDLA_pdp.h
#ifndef _NV_NVDLA_PDP_H_
#define _NV_NVDLA_PDP_H_
#define SC_INCLUDE_DYNAMIC_PROCESSES
#include <systemc.h>
#include <tlm.h>
#include "tlm_utils/multi_passthrough_initiator_socket.h"
#include "tlm_utils/multi_passthrough_target_socket.h"
#include "scsim_common.h"
#include "nvdla_dma_wr_req_iface.h"
#include "systemc.h"
#include "nvdla_xx2csb_resp_iface.h"
#include "NV_NVDLA_pdp_base.h"
#include "pdp_reg_model.h"
#include "pdp_rdma_reg_model.h"
#include "NvdlaDataFormatConvertor.h"
#define PDP_RDMA_TRANSACTION_SIZE_GRANULARITY 32
#define PDP_RDMA_BUFFER_CMOD_ENTRY_GRANULARITY 4
#define PDP_WDMA_BUFFER_SIZE 256
#define PDP_CVT_OUT_BIT_WIDTH 16
#define PDP_CVT_OUT_NUMBER 8
#define PDP_GROUP_SIZE_IN_BYTE 32
#define MAX_MEM_TRANSACTION_SIZE 256
#define KERNEL_PER_GROUP_INT8 32
#define KERNEL_PER_GROUP_INT16 16
#define KERNEL_PER_GROUP_FP16 16
#define KERNEL_PER_GROUP_SIZE 32
#define SDP2PDP_ELEMENT_NUM 8
#define SDP2PDP_ELEMENT_BIT_WIDTH 16
#define PDP_WRITE_DMA_SUB_TRANSACTION_SIZE 64
#define DATA_FORMAT_IS_INT8 0
#define DATA_FORMAT_IS_INT16 1
#define DATA_FORMAT_IS_FP16 2
#define ELEMENT_SIZE_INT8 1
#define ELEMENT_SIZE_INT16 2
#define ELEMENT_SIZE_FP16 2
#define ELEMENT_PER_ATOM_INT8 32
#define ELEMENT_PER_ATOM_INT16 16
#define ELEMENT_PER_ATOM_FP16 16
#define TAG_CMD 0
#define TAG_DATA 1
#define ATOM_CUBE_SIZE 32
#define PDP_RDMA_BUFFER_TOTAL_SIZE 32*8192
#define PDP_RDMA_BUFFER_ENTRY_SIZE ATOM_CUBE_SIZE
#define PDP_RDMA_BUFFER_ENTRY_NUM PDP_RDMA_BUFFER_TOTAL_SIZE/PDP_RDMA_BUFFER_ENTRY_SIZE
#define SDP2PDP_PAYLOAD_SIZE 32
#define SDP2PDP_PAYLOAD_ELEMENT_NUM 16
#define SDP2PDP_FIFO_ENTRY_NUM 16 // ATOM_CUBE_SIZE/SDP2PDP_PAYLOAD_SIZE
#define PDP_LINE_BUFFER_INT8_ELEMENT_NUM 8*1024
#define PDP_LINE_BUFFER_INT16_ELEMENT_NUM 4*1024
#define PDP_LINE_BUFFER_FP16_ELEMENT_NUM 4*1024
#define PDP_LINE_BUFFER_PHYSICAL_BUFFER_NUM 8
#define PDP_LINE_BUFFER_SIZE (PDP_LINE_BUFFER_INT8_ELEMENT_NUM*2)
#define PDP_LINE_BUFFER_ENTRY_NUM (PDP_LINE_BUFFER_SIZE)/(ATOM_CUBE_SIZE*2) //Each atom consumes 64Bytes
#define POOLING_FLYING_MODE_ON_FLYING NVDLA_PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_ON_FLYING
#define POOLING_FLYING_MODE_OFF_FLYING NVDLA_PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_OFF_FLYING
#define POOLING_METHOD_AVE NVDLA_PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_POOLING_METHOD_AVERAGE
#define POOLING_METHOD_MAX NVDLA_PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_POOLING_METHOD_MAX
#define POOLING_METHOD_MIN NVDLA_PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_POOLING_METHOD_MIN
#define DATA_TYPE_IS_INT 0
#define DATA_TYPE_IS_FLOAT 1
#define PDP_MAX_PADDING_SIZE 7
// class NvdlaDataFormatConvertor;
SCSIM_NAMESPACE_START(clib)
// clib class forward declaration
SCSIM_NAMESPACE_END()
SCSIM_NAMESPACE_START(cmod)
// class container_payload_wrapper {
// public:
// uint8_t *data;
// uint8_t data_num;
// };
//
// std::ostream& operator<<(std::ostream& out, const container_payload_wrapper& obj) {
// return out << "Just to fool compiler" << endl;
// }
//
// std::ostream& operator<<(std::ostream& out, const nvdla_container_number_8_bit_width_16_t& obj) {
// return out << "Just to fool compiler" << endl;
// }
class pdp_ack_info {
public:
bool is_mc;
uint8_t group_id;
};
class NV_NVDLA_pdp:
public NV_NVDLA_pdp_base, // ports
private pdp_reg_model, // pdp register accessing
private pdp_rdma_reg_model // pdp_rdma
{
public:
SC_HAS_PROCESS(NV_NVDLA_pdp);
NV_NVDLA_pdp( sc_module_name module_name );
~NV_NVDLA_pdp();
// CSB request transport implementation shall in generated code
void csb2pdp_req_b_transport (int ID, NV_MSDEC_csb2xx_16m_secure_be_lvl_t* payload, sc_time& delay);
void csb2pdp_rdma_req_b_transport (int ID, NV_MSDEC_csb2xx_16m_secure_be_lvl_t* payload, sc_time& delay);
void sdp2pdp_b_transport(int ID, nvdla_sdp2pdp_t* payload, sc_core::sc_time& delay);
void mcif2pdp_rd_rsp_b_transport(int ID, nvdla_dma_rd_rsp_t*, sc_core::sc_time&);
void cvif2pdp_rd_rsp_b_transport(int ID, nvdla_dma_rd_rsp_t*, sc_core::sc_time&);
// void pdp2csb_resp_b_transport(nvdla_xx2csb_resp_t* payload, sc_time& delay) {NV_NVDLA_pdp_base::pdp2csb_resp_b_transport(payload, delay);}
// void pdp_rdma2csb_resp_b_transport(nvdla_xx2csb_resp_t* payload, sc_time& delay) {NV_NVDLA_pdp_base::pdp2csb_resp_b_transport(payload, delay);}
private:
// Payloads
nvdla_dma_wr_req_t *dma_wr_req_cmd_payload_;
nvdla_dma_wr_req_t *dma_wr_req_data_payload_;
nvdla_dma_rd_req_t *dma_rd_req_payload_;
// Delay
sc_core::sc_time dma_delay_;
sc_core::sc_time csb_delay_;
sc_core::sc_time b_transport_delay_;
// Events
// PDP config evaluation is done
sc_event event_pdp_config_evaluation_done;
// Receiving data from sdp
sc_event event_got_conv_data;
// Functional logic have fetched data from RDMA buffer
sc_event event_functional_logic_got_data;
sc_event rdma_read_event;
sc_event rdma_write_event;
// For PDP hardware layer kickoff and end
sc_event pdp_rdma_kickoff_;
sc_event pdp_rdma_done_;
sc_event pdp_kickoff_;
sc_event pdp_done_;
sc_core::sc_fifo<uint8_t> *line_buffer_usage_free_[PDP_LINE_BUFFER_ENTRY_NUM];
sc_core::sc_fifo<uint8_t> *line_buffer_usage_available_;
// sc_event *line_buffer_usage_free_read_event;
// sc_event *line_buffer_usage_free_write_event;
// sc_mutex line_buffer_data_ready_;
// uint32_t line_buffer_data_num_;
sc_core::sc_fifo<uint8_t> *line_buffer_ready_[PDP_LINE_BUFFER_ENTRY_NUM];
// Evaluated configs based on register config
uint32_t pdp_rdma_operation_mode_;
uint32_t pdp_operation_mode_;
bool pdp_ready_to_receive_data_;
// Temperal and intermedia signals
bool is_there_ongoing_csb2pdp_response_;
bool is_there_ongoing_csb2pdp_rdma_response_;
// Variables needs to be added to register
// uint8_t pdp_rdma_kernel_stride_width_;
// uint8_t pdp_rdma_kernel_width_;
// uint8_t pdp_rdma_pad_width_;
uint32_t pdp_cvt_offset_input_;
uint16_t pdp_cvt_scale_input_;
uint8_t pdp_cvt_truncate_lsb_input_;
uint8_t pdp_cvt_truncate_msb_input_;
sc_core::sc_fifo <uint8_t *> *spd2pdp_fifo_;
sc_core::sc_fifo <uint8_t *> *rdma_buffer_;
sc_core::sc_fifo <uint8_t *> *wdma_buffer_;
sc_core::sc_fifo <pdp_ack_info *> *pdp_ack_fifo_;
sc_event pdp_mc_ack_;
sc_event pdp_cv_ack_;
bool is_mc_ack_done_;
bool is_cv_ack_done_;
// RDMA buffer index
uint32_t rdma_buffer_write_idx_;
uint32_t rdma_buffer_read_idx_;
// WDMA buffer index
uint32_t wdma_buffer_write_idx_;
uint32_t wdma_buffer_read_idx_;
// Data buffers
// # Shared line buffer, each entry stores one int8 element
// In HW, its size is 8KB. In CMOD, it's 16KB. The num of entries are same as HW, however each entry size is 16B, not 8B for precision in arithmetic.
uint16_t line_buffer_[PDP_LINE_BUFFER_INT8_ELEMENT_NUM];
uint16_t line_operation_buffer_[8*ELEMENT_PER_ATOM_INT8];
// Function declaration
// # Threads
void PdpRdmaConsumerThread();
void PdpConsumerThread();
void PoolingStage0SequenceThread ();
void PoolingStage1SequenceThread ();
void PdpRdmaSequenceThread ();
void PdpWdmaSequenceThread ();
void PdpIntrThread();
void WriteResponseThreadMc();
void WriteResponseThreadCv();
// # Config evaluation
void PdpRdmaConfigEvaluation(CNVDLA_PDP_RDMA_REGSET *register_group_ptr);
void PdpConfigEvaluation(CNVDLA_PDP_REGSET *register_group_ptr);
// # Hardware layer execution trigger
void PdpRdmaHardwareLayerExecutionTrigger();
void PdpHardwareLayerExecutionTrigger();
// # Operation
void OperationModePdpRdmaCommon();
void OperationModePdpCommon();
void RdmaSequenceCommon(uint64_t src_base_addr, uint32_t cube_in_width);
// void RdmaSequence8Bto8B();
// void RdmaSequence16Bto16B();
// void RdmaSequence8Bto16B();
void RdmaSequence16Bto8B();
// Pooling function
void PoolingStage0SequenceCommon(uint32_t cube_in_width, uint32_t pad_left, uint32_t pad_right, uint32_t acc_subcube_out_width, uint32_t cube_out_width);
void PoolingStage0Sequence8Bto8B();
void PoolingStage0Sequence16Bto16B();
void PoolingStage1SequenceCommon(uint32_t cube_out_width, uint32_t acc_subcube_out_width, uint32_t pad_left, uint32_t pad_right, uint32_t cube_in_width);
void PoolingStage1Sequence8Bto8B();
void PoolingStage1Sequence16Bto16B();
// void WdmaSequenceCommon();
void WdmaSequenceCommon(uint64_t dst_base_addr, uint32_t cube_out_width, bool split_last);
// # Functional functions
// Send DMA read request
void SendDmaReadRequest(nvdla_dma_rd_req_t* payload, sc_time& delay);
// void SendDmaReadRequest(nvdla_dma_rd_req_t* payload, sc_time& delay, uint8_t src_ram_type);
// Extract DMA read response payload
void ExtractDmaPayload(nvdla_dma_rd_rsp_t* payload);
// Send DMA write request
void SendDmaWriteRequest(nvdla_dma_wr_req_t* payload, sc_time& delay, bool ack_required = false);
void SendDmaWriteRequest(uint64_t payload_addr, uint32_t payload_size, uint32_t payload_atom_num, bool ack_required = false);
// template <typename T>
// void FetchInputData (uint8_t * atomic_cube);
uint8_t * FetchInputData ();
template <typename T_IN, typename T_OUT, typename T_PAD>
void PoolingStage0Calc (T_IN * atomic_data_in, T_OUT * line_buffer_ptr, uint32_t cube_out_width_idx, uint32_t cube_out_height_idx, uint32_t surface, uint32_t cube_in_height, uint32_t kernel_height_iter, uint32_t kernel_height, uint32_t cube_in_height_iter, T_PAD * padding_value_ptr, uint8_t element_num, uint32_t surface_num, uint32_t acc_subcube_out_width, uint32_t cube_out_width);
template <typename T_OUT, typename T_IN>
void PoolingStage1Calc (T_OUT * atomic_data_out, T_IN * line_buffer_ptr, uint32_t width, uint32_t height, uint32_t surface, uint8_t element_num, uint32_t surface_num, uint32_t acc_subcube_out_width, uint32_t cube_out_width, uint32_t pad_left, uint32_t pad_right, uint32_t cube_in_width);
template <typename T_IN, typename T_OUT, typename T_PAD>
void LineOperation (T_IN * atomic_data_in, T_OUT * line_buffer_ptr, uint32_t kernel_width_iter, uint32_t kernel_width, uint32_t cube_in_width_iter, uint32_t cube_in_width, T_PAD * padding_value_ptr, uint8_t element_num, uint32_t pad_left);
// ## Reset
void Reset();
void WaitUntilRdmaBufferFreeSizeGreaterThan(uint32_t num);
void WaitUntilRdmaBufferAvailableSizeGreaterThan(uint32_t num);
void WaitUntilWdmaBufferFreeSizeGreaterThan(uint32_t num);
void WaitUntilWdmaBufferAvailableSizeGreaterThan(uint32_t num);
void PdpSendCsbResponse(uint8_t type, uint32_t data, uint8_t error_id);
void PdpRdmaSendCsbResponse(uint8_t type, uint32_t data, uint8_t error_id);
bool IsFirstElement(uint32_t pad_left, uint32_t width_iter, uint32_t height_iter, uint32_t kernel_width_iter, uint32_t kernel_height_iter);
bool IsLastElement(uint32_t cube_in_width, uint32_t pad_left, uint32_t width_iter, uint32_t height_iter, uint32_t kernel_width_iter, uint32_t kernel_height_iter);
bool IsContributeToANewLine(uint32_t cube_in_height_iter, uint32_t kernel_height_iter);
template <typename T_IN, typename T_OUT>
void int_sign_extend(T_IN original_value, uint8_t sign_bit_idx, uint8_t extended_bit_num, T_OUT *return_value);
void reset_stats_regs();
void update_stats_regs();
uint32_t nan_input_num;
uint32_t inf_input_num;
uint32_t nan_output_num;
};
SCSIM_NAMESPACE_END()
extern "C" scsim::cmod::NV_NVDLA_pdp * NV_NVDLA_pdpCon(sc_module_name module_name);
#endif
|
/* -*- sysc -*-*/
/*
#- (c) Copyright 2011-2017 Xilinx, Inc. All rights reserved.
#-
#- This file contains confidential and proprietary information
#- of Xilinx, Inc. and is protected under U.S. and
#- international copyright and other intellectual property
#- laws.
#-
#- DISCLAIMER
#- This disclaimer is not a license and does not grant any
#- rights to the materials distributed herewith. Except as
#- otherwise provided in a valid license issued to you by
#- Xilinx, and to the maximum extent permitted by applicable
#- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
#- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
#- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
#- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
#- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
#- (2) Xilinx shall not be liable (whether in contract or tort,
#- including negligence, or under any other theory of
#- liability) for any loss or damage of any kind or nature
#- related to, arising under or in connection with these
#- materials, including for any direct, or any indirect,
#- special, incidental, or consequential loss or damage
#- (including loss of data, profits, goodwill, or any type of
#- loss or damage suffered as a result of any action brought
#- by a third party) even if such damage or loss was
#- reasonably foreseeable or Xilinx had been advised of the
#- possibility of the same.
#-
#- CRITICAL APPLICATIONS
#- Xilinx products are not designed or intended to be fail-
#- safe, or for use in any application requiring fail-safe
#- performance, such as life-support or safety devices or
#- systems, Class III medical devices, nuclear facilities,
#- applications related to the deployment of airbags, or any
#- other applications that could lead to death, personal
#- injury, or severe property or environmental damage
#- (individually and collectively, "Critical
#- Applications"). Customer assumes the sole risk and
#- liability of any use of Xilinx products in Critical
#- Applications, subject only to applicable laws and
#- regulations governing limitations on product liability.
#-
#- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
#- PART OF THIS FILE AT ALL TIMES.
#- ************************************************************************
*
*
*/
#ifndef _AP_MEM_IF_H
#define _AP_MEM_IF_H
#include <systemc.h>
//#define USER_DEBUG_MEMORY
/* ap_mem_port Types */
enum ap_mem_port_type {
RAM_1P = 0,
RAM1P = RAM_1P,
RAM_2P = 1,
RAM2P = RAM_2P,
RAM_T2P = 2,
RAMT2P = RAM_T2P,
ROM_1P = 3,
ROM1P = ROM_1P,
ROM_2P = 4,
ROM2P = ROM_2P,
};
//=================================================================
//======================== ap_mem ports =========================
//=================================================================
//----------------------------------------------------------
// ap_mem_if
//----------------------------------------------------------
template <typename _hls_mem_dt, typename _hls_mem_addrt, int t_size,
ap_mem_port_type portType = RAM1P>
class ap_mem_if : public sc_interface {
public:
// read the current value
virtual _hls_mem_dt &read(const _hls_mem_addrt addr) = 0;
virtual void write(const _hls_mem_addrt addr, const _hls_mem_dt data) = 0;
protected:
// constructor
ap_mem_if() {}
private:
// disabled
ap_mem_if(const ap_mem_if<_hls_mem_dt, _hls_mem_addrt, t_size, portType> &);
ap_mem_if<_hls_mem_dt, _hls_mem_addrt, t_size, portType> &
operator=(const ap_mem_if<_hls_mem_dt, _hls_mem_addrt, t_size, portType> &);
};
//----------------------------------------------------------
// ap_mem_port
//----------------------------------------------------------
template <typename _hls_mem_dt, typename _hls_mem_addrt, int t_size,
ap_mem_port_type portType = RAM1P>
class ap_mem_port
: public sc_port<ap_mem_if<_hls_mem_dt, _hls_mem_addrt, t_size, portType>> {
// typedefs
// typedef T _hls_mem_dt;
typedef ap_mem_if<_hls_mem_dt, _hls_mem_addrt, t_size, portType> if_type;
typedef sc_port<if_type, 1, SC_ONE_OR_MORE_BOUND> base_type;
typedef ap_mem_port<_hls_mem_dt, _hls_mem_addrt, t_size, portType> this_type;
typedef if_type in_if_type;
typedef base_type in_port_type;
_hls_mem_addrt ADDR_tmp;
public:
ap_mem_port() {
#ifndef __RTL_SIMULATION__
cout << "@W [SIM] Please add name for your ap_mem_port, or RTL simulation "
"will fail."
<< endl;
#endif
}
explicit ap_mem_port(const char *name_) {}
void reset() {}
_hls_mem_dt &read(const _hls_mem_addrt addr) { return (*this)->read(addr); }
void write(const _hls_mem_addrt addr, const _hls_mem_dt data) {
(*this)->write(addr, data);
}
ap_mem_port &operator[](const _hls_mem_addrt addr) {
// return (*this)->read(addr);
ADDR_tmp = addr;
return *this;
}
void operator=(_hls_mem_dt data) { (*this)->write(ADDR_tmp, data); }
operator _hls_mem_dt() { return (*this)->read(ADDR_tmp); }
};
//----------------------------------------------------------
// ap_mem_chn
//----------------------------------------------------------
template <typename _hls_mem_dt, typename _hls_mem_addrt, int t_size,
ap_mem_port_type portType = RAM1P>
class ap_mem_chn
: public ap_mem_if<_hls_mem_dt, _hls_mem_addrt, t_size, portType>,
public sc_prim_channel {
private:
_hls_mem_dt mArray[2][t_size];
int mInitiatorBank;
int mTargetCurBank;
int mCurBank;
std::string mem_name;
public:
explicit ap_mem_chn(const char *name = "ap_mem_chn")
: mCurBank(0), mem_name(name) {}
virtual ~ap_mem_chn(){};
_hls_mem_dt &read(const _hls_mem_addrt addr) {
#ifdef USER_DEBUG_MEMORY
cout << "mem read : " << mem_name << "[" << addr
<< "] = " << mArray[mCurBank][addr] << endl;
#endif
return mArray[mCurBank][addr];
}
void write(const _hls_mem_addrt addr, const _hls_mem_dt data) {
mArray[mCurBank][addr] = data;
#ifdef USER_DEBUG_MEMORY
cout << "mem write: " << mem_name << "[" << addr
<< "] = " << mArray[mCurBank][addr] << endl;
#endif
}
_hls_mem_dt &operator[](const _hls_mem_addrt &addr) {
return mArray[mCurBank][addr];
}
// int put() { mCurBank++; mCurBank %= 2; }
// int get() { }
};
//=================================================================
//======================== ap_pingpong_if =========================
//=================================================================
//--------------------------------------------
// ap_pingpong_if
//--------------------------------------------
template <typename _hls_mem_dt, typename _hls_mem_addrt, int t_size,
ap_mem_port_type portType = RAM1P>
class ap_pingpong_if : public sc_interface {
public:
virtual bool put_is_ready() = 0;
virtual void put_request() = 0;
virtual void put_release() = 0;
virtual _hls_mem_dt put_read(const _hls_mem_addrt addr) = 0;
virtual void put_write(const _hls_mem_addrt addr, const _hls_mem_dt data) = 0;
virtual bool get_is_ready() = 0;
virtual void get_request() = 0;
virtual void get_release() = 0;
virtual _hls_mem_dt get_read(const _hls_mem_addrt addr) = 0;
virtual void get_write(const _hls_mem_addrt addr, const _hls_mem_dt data) = 0;
protected:
// constructor
ap_pingpong_if() {}
private:
// disabled
ap_pingpong_if(
const ap_pingpong_if<_hls_mem_dt, _hls_mem_addrt, t_size, portType> &);
ap_pingpong_if<_hls_mem_dt, _hls_mem_addrt, t_size, portType> &operator=(
const ap_pingpong_if<_hls_mem_dt, _hls_mem_addrt, t_size, portType> &);
};
//--------------------------------------------
// ap_pingpong_get
//--------------------------------------------
template <typename _hls_mem_dt, typename _hls_mem_addrt, int t_size,
ap_mem_port_type portType = RAM1P>
class ap_pingpong_get
: public sc_port<
ap_pingpong_if<_hls_mem_dt, _hls_mem_addrt, t_size, portType>> {
// typedef sc_port_b<ap_pingpong_if<_hls_mem_dt, _hls_mem_addrt, t_size,
// portType> > Get_Base;
public:
explicit ap_pingpong_get(const char *name_) {}
/// functions
void reset() {}
bool is_ready() { return (*this)->get_is_ready(); }
void request() { (*this)->get_request(); }
void release() { (*this)->get_release(); }
_hls_mem_dt read(_hls_mem_addrt addr) { return (*this)->get_read(addr); }
void write(_hls_mem_addrt addr, _hls_mem_dt data) {
(*this)->get_write(addr, data);
}
};
//--------------------------------------------
// ap_pingpong_put
//--------------------------------------------
template <typename _hls_mem_dt, typename _hls_mem_addrt, int t_size,
ap_mem_port_type portType = RAM1P>
class ap_pingpong_put
: public sc_port<
ap_pingpong_if<_hls_mem_dt, _hls_mem_addrt, t_size, portType>> {
public:
explicit ap_pingpong_put(const char *name_) {}
/// functions
void reset() {}
bool is_ready() { return (*this)->put_is_ready(); }
void request() { (*this)->put_request(); }
void release() { (*this)->put_release(); }
_hls_mem_dt read(_hls_mem_addrt addr) { return (*this)->put_read(addr); }
void write(_hls_mem_addrt addr, _hls_mem_dt data) {
(*this)->put_write(addr, data);
}
};
//--------------------------------------------
// ap_pingpong_chn
//--------------------------------------------
template <typename _hls_mem_dt, typename _hls_mem_addrt, int t_size,
ap_mem_port_type portType = RAM1P>
class ap_pingpong_chn
: public ap_pingpong_if<_hls_mem_dt, _hls_mem_addrt, t_size, portType>,
public sc_prim_channel {
private:
_hls_mem_dt mArray[2][t_size];
int mInitiatorBank;
int mTargetBank;
std::string mem_name;
bool cur_bankflag[2];
bool new_bankflag[2];
protected:
virtual void update() {
cur_bankflag[0] = new_bankflag[0];
cur_bankflag[1] = new_bankflag[1];
}
public:
explicit ap_pingpong_chn(const char *name = "ap_pingpong_chn")
: mem_name(name), mInitiatorBank(0), mTargetBank(0) {
cur_bankflag[0] = 0;
cur_bankflag[1] = 0;
new_bankflag[0] = 0;
new_bankflag[1] = 0;
}
virtual ~ap_pingpong_chn(){};
/// Initiator/put APIs
bool put_is_ready() { return (!cur_bankflag[mInitiatorBank]); }
void put_request() {
do {
wait();
} while (!put_is_ready());
}
void put_release() {
new_bankflag[mInitiatorBank] = 1;
mInitiatorBank++;
mInitiatorBank %= 2;
request_update();
}
_hls_mem_dt put_read(const _hls_mem_addrt addr) {
#ifdef USER_DEBUG_MEMORY
cout << "Initor read : " << mem_name << "[" << addr
<< "] = " << mArray[mInitiatorBank][addr] << endl;
#endif
return mArray[mInitiatorBank][addr];
}
void put_write(const _hls_mem_addrt addr, const _hls_mem_dt data) {
mArray[mInitiatorBank][addr] = data;
#ifdef USER_DEBUG_MEMORY
cout << "Initor write: " << mem_name << "[" << addr
<< "] = " << mArray[mInitiatorBank][addr] << endl;
#endif
}
/// Target/get APIs
bool get_is_ready() { return (cur_bankflag[mTargetBank]); }
void get_request() {
do {
wait();
} while (!get_is_ready());
}
void get_release() {
new_bankflag[mTargetBank] = 0;
mTargetBank++;
mTargetBank %= 2;
request_update();
}
_hls_mem_dt get_read(const _hls_mem_addrt addr) {
if (!get_is_ready()) {
return 0;
}
#ifdef USER_DEBUG_MEMORY
cout << "Target read : " << mem_name << "[" << addr
<< "] = " << mArray[mTargetBank][addr] << endl;
#endif
return mArray[mTargetBank][addr];
}
void get_write(const _hls_mem_addrt addr, const _hls_mem_dt data) {
if (!get_is_ready()) {
return;
}
mArray[mTargetBank][addr] = data;
#ifdef USER_DEBUG_MEMORY
cout << "Target write: " << mem_name << "[" << addr
<< "] = " << mArray[mTargetBank][addr] << endl;
#endif
}
};
template <typename _hls_mem_dt, typename _hls_mem_addrt, int t_size,
ap_mem_port_type portType = RAM1P>
class ap_pingpong {
public:
typedef ap_pingpong_put<_hls_mem_dt, _hls_mem_addrt, t_size, portType> put;
typedef ap_pingpong_get<_hls_mem_dt, _hls_mem_addrt, t_size, portType> get;
typedef ap_pingpong_chn<_hls_mem_dt, _hls_mem_addrt, t_size, portType> chn;
};
#endif /* Header Guard */
// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
|
/* -*- sysc -*-*/
/*
#- (c) Copyright 2011-2017 Xilinx, Inc. All rights reserved.
#-
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#- of Xilinx, Inc. and is protected under U.S. and
#- international copyright and other intellectual property
#- laws.
#-
#- DISCLAIMER
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#- otherwise provided in a valid license issued to you by
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#- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
#- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
#- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
#- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
#- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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#- including negligence, or under any other theory of
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#- related to, arising under or in connection with these
#- materials, including for any direct, or any indirect,
#- special, incidental, or consequential loss or damage
#- (including loss of data, profits, goodwill, or any type of
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#- reasonably foreseeable or Xilinx had been advised of the
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#- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
#- PART OF THIS FILE AT ALL TIMES.
#- ************************************************************************
*
*
*/
#ifndef _AP_MEM_IF_H
#define _AP_MEM_IF_H
#include <systemc.h>
//#define USER_DEBUG_MEMORY
/* ap_mem_port Types */
enum ap_mem_port_type {
RAM_1P = 0,
RAM1P = RAM_1P,
RAM_2P = 1,
RAM2P = RAM_2P,
RAM_T2P = 2,
RAMT2P = RAM_T2P,
ROM_1P = 3,
ROM1P = ROM_1P,
ROM_2P = 4,
ROM2P = ROM_2P,
};
//=================================================================
//======================== ap_mem ports =========================
//=================================================================
//----------------------------------------------------------
// ap_mem_if
//----------------------------------------------------------
template <typename _hls_mem_dt, typename _hls_mem_addrt, int t_size,
ap_mem_port_type portType = RAM1P>
class ap_mem_if : public sc_interface {
public:
// read the current value
virtual _hls_mem_dt &read(const _hls_mem_addrt addr) = 0;
virtual void write(const _hls_mem_addrt addr, const _hls_mem_dt data) = 0;
protected:
// constructor
ap_mem_if() {}
private:
// disabled
ap_mem_if(const ap_mem_if<_hls_mem_dt, _hls_mem_addrt, t_size, portType> &);
ap_mem_if<_hls_mem_dt, _hls_mem_addrt, t_size, portType> &
operator=(const ap_mem_if<_hls_mem_dt, _hls_mem_addrt, t_size, portType> &);
};
//----------------------------------------------------------
// ap_mem_port
//----------------------------------------------------------
template <typename _hls_mem_dt, typename _hls_mem_addrt, int t_size,
ap_mem_port_type portType = RAM1P>
class ap_mem_port
: public sc_port<ap_mem_if<_hls_mem_dt, _hls_mem_addrt, t_size, portType>> {
// typedefs
// typedef T _hls_mem_dt;
typedef ap_mem_if<_hls_mem_dt, _hls_mem_addrt, t_size, portType> if_type;
typedef sc_port<if_type, 1, SC_ONE_OR_MORE_BOUND> base_type;
typedef ap_mem_port<_hls_mem_dt, _hls_mem_addrt, t_size, portType> this_type;
typedef if_type in_if_type;
typedef base_type in_port_type;
_hls_mem_addrt ADDR_tmp;
public:
ap_mem_port() {
#ifndef __RTL_SIMULATION__
cout << "@W [SIM] Please add name for your ap_mem_port, or RTL simulation "
"will fail."
<< endl;
#endif
}
explicit ap_mem_port(const char *name_) {}
void reset() {}
_hls_mem_dt &read(const _hls_mem_addrt addr) { return (*this)->read(addr); }
void write(const _hls_mem_addrt addr, const _hls_mem_dt data) {
(*this)->write(addr, data);
}
ap_mem_port &operator[](const _hls_mem_addrt addr) {
// return (*this)->read(addr);
ADDR_tmp = addr;
return *this;
}
void operator=(_hls_mem_dt data) { (*this)->write(ADDR_tmp, data); }
operator _hls_mem_dt() { return (*this)->read(ADDR_tmp); }
};
//----------------------------------------------------------
// ap_mem_chn
//----------------------------------------------------------
template <typename _hls_mem_dt, typename _hls_mem_addrt, int t_size,
ap_mem_port_type portType = RAM1P>
class ap_mem_chn
: public ap_mem_if<_hls_mem_dt, _hls_mem_addrt, t_size, portType>,
public sc_prim_channel {
private:
_hls_mem_dt mArray[2][t_size];
int mInitiatorBank;
int mTargetCurBank;
int mCurBank;
std::string mem_name;
public:
explicit ap_mem_chn(const char *name = "ap_mem_chn")
: mCurBank(0), mem_name(name) {}
virtual ~ap_mem_chn(){};
_hls_mem_dt &read(const _hls_mem_addrt addr) {
#ifdef USER_DEBUG_MEMORY
cout << "mem read : " << mem_name << "[" << addr
<< "] = " << mArray[mCurBank][addr] << endl;
#endif
return mArray[mCurBank][addr];
}
void write(const _hls_mem_addrt addr, const _hls_mem_dt data) {
mArray[mCurBank][addr] = data;
#ifdef USER_DEBUG_MEMORY
cout << "mem write: " << mem_name << "[" << addr
<< "] = " << mArray[mCurBank][addr] << endl;
#endif
}
_hls_mem_dt &operator[](const _hls_mem_addrt &addr) {
return mArray[mCurBank][addr];
}
// int put() { mCurBank++; mCurBank %= 2; }
// int get() { }
};
//=================================================================
//======================== ap_pingpong_if =========================
//=================================================================
//--------------------------------------------
// ap_pingpong_if
//--------------------------------------------
template <typename _hls_mem_dt, typename _hls_mem_addrt, int t_size,
ap_mem_port_type portType = RAM1P>
class ap_pingpong_if : public sc_interface {
public:
virtual bool put_is_ready() = 0;
virtual void put_request() = 0;
virtual void put_release() = 0;
virtual _hls_mem_dt put_read(const _hls_mem_addrt addr) = 0;
virtual void put_write(const _hls_mem_addrt addr, const _hls_mem_dt data) = 0;
virtual bool get_is_ready() = 0;
virtual void get_request() = 0;
virtual void get_release() = 0;
virtual _hls_mem_dt get_read(const _hls_mem_addrt addr) = 0;
virtual void get_write(const _hls_mem_addrt addr, const _hls_mem_dt data) = 0;
protected:
// constructor
ap_pingpong_if() {}
private:
// disabled
ap_pingpong_if(
const ap_pingpong_if<_hls_mem_dt, _hls_mem_addrt, t_size, portType> &);
ap_pingpong_if<_hls_mem_dt, _hls_mem_addrt, t_size, portType> &operator=(
const ap_pingpong_if<_hls_mem_dt, _hls_mem_addrt, t_size, portType> &);
};
//--------------------------------------------
// ap_pingpong_get
//--------------------------------------------
template <typename _hls_mem_dt, typename _hls_mem_addrt, int t_size,
ap_mem_port_type portType = RAM1P>
class ap_pingpong_get
: public sc_port<
ap_pingpong_if<_hls_mem_dt, _hls_mem_addrt, t_size, portType>> {
// typedef sc_port_b<ap_pingpong_if<_hls_mem_dt, _hls_mem_addrt, t_size,
// portType> > Get_Base;
public:
explicit ap_pingpong_get(const char *name_) {}
/// functions
void reset() {}
bool is_ready() { return (*this)->get_is_ready(); }
void request() { (*this)->get_request(); }
void release() { (*this)->get_release(); }
_hls_mem_dt read(_hls_mem_addrt addr) { return (*this)->get_read(addr); }
void write(_hls_mem_addrt addr, _hls_mem_dt data) {
(*this)->get_write(addr, data);
}
};
//--------------------------------------------
// ap_pingpong_put
//--------------------------------------------
template <typename _hls_mem_dt, typename _hls_mem_addrt, int t_size,
ap_mem_port_type portType = RAM1P>
class ap_pingpong_put
: public sc_port<
ap_pingpong_if<_hls_mem_dt, _hls_mem_addrt, t_size, portType>> {
public:
explicit ap_pingpong_put(const char *name_) {}
/// functions
void reset() {}
bool is_ready() { return (*this)->put_is_ready(); }
void request() { (*this)->put_request(); }
void release() { (*this)->put_release(); }
_hls_mem_dt read(_hls_mem_addrt addr) { return (*this)->put_read(addr); }
void write(_hls_mem_addrt addr, _hls_mem_dt data) {
(*this)->put_write(addr, data);
}
};
//--------------------------------------------
// ap_pingpong_chn
//--------------------------------------------
template <typename _hls_mem_dt, typename _hls_mem_addrt, int t_size,
ap_mem_port_type portType = RAM1P>
class ap_pingpong_chn
: public ap_pingpong_if<_hls_mem_dt, _hls_mem_addrt, t_size, portType>,
public sc_prim_channel {
private:
_hls_mem_dt mArray[2][t_size];
int mInitiatorBank;
int mTargetBank;
std::string mem_name;
bool cur_bankflag[2];
bool new_bankflag[2];
protected:
virtual void update() {
cur_bankflag[0] = new_bankflag[0];
cur_bankflag[1] = new_bankflag[1];
}
public:
explicit ap_pingpong_chn(const char *name = "ap_pingpong_chn")
: mem_name(name), mInitiatorBank(0), mTargetBank(0) {
cur_bankflag[0] = 0;
cur_bankflag[1] = 0;
new_bankflag[0] = 0;
new_bankflag[1] = 0;
}
virtual ~ap_pingpong_chn(){};
/// Initiator/put APIs
bool put_is_ready() { return (!cur_bankflag[mInitiatorBank]); }
void put_request() {
do {
wait();
} while (!put_is_ready());
}
void put_release() {
new_bankflag[mInitiatorBank] = 1;
mInitiatorBank++;
mInitiatorBank %= 2;
request_update();
}
_hls_mem_dt put_read(const _hls_mem_addrt addr) {
#ifdef USER_DEBUG_MEMORY
cout << "Initor read : " << mem_name << "[" << addr
<< "] = " << mArray[mInitiatorBank][addr] << endl;
#endif
return mArray[mInitiatorBank][addr];
}
void put_write(const _hls_mem_addrt addr, const _hls_mem_dt data) {
mArray[mInitiatorBank][addr] = data;
#ifdef USER_DEBUG_MEMORY
cout << "Initor write: " << mem_name << "[" << addr
<< "] = " << mArray[mInitiatorBank][addr] << endl;
#endif
}
/// Target/get APIs
bool get_is_ready() { return (cur_bankflag[mTargetBank]); }
void get_request() {
do {
wait();
} while (!get_is_ready());
}
void get_release() {
new_bankflag[mTargetBank] = 0;
mTargetBank++;
mTargetBank %= 2;
request_update();
}
_hls_mem_dt get_read(const _hls_mem_addrt addr) {
if (!get_is_ready()) {
return 0;
}
#ifdef USER_DEBUG_MEMORY
cout << "Target read : " << mem_name << "[" << addr
<< "] = " << mArray[mTargetBank][addr] << endl;
#endif
return mArray[mTargetBank][addr];
}
void get_write(const _hls_mem_addrt addr, const _hls_mem_dt data) {
if (!get_is_ready()) {
return;
}
mArray[mTargetBank][addr] = data;
#ifdef USER_DEBUG_MEMORY
cout << "Target write: " << mem_name << "[" << addr
<< "] = " << mArray[mTargetBank][addr] << endl;
#endif
}
};
template <typename _hls_mem_dt, typename _hls_mem_addrt, int t_size,
ap_mem_port_type portType = RAM1P>
class ap_pingpong {
public:
typedef ap_pingpong_put<_hls_mem_dt, _hls_mem_addrt, t_size, portType> put;
typedef ap_pingpong_get<_hls_mem_dt, _hls_mem_addrt, t_size, portType> get;
typedef ap_pingpong_chn<_hls_mem_dt, _hls_mem_addrt, t_size, portType> chn;
};
#endif /* Header Guard */
// 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
|
// ================================================================
// NVDLA Open Source Project
//
// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
// NVDLA Open Hardware License; Check "LICENSE" which comes with
// this distribution for more information.
// ================================================================
// File Name: cdma_reg_model.h
#ifndef _CDMA_REG_MODEL_H_
#define _CDMA_REG_MODEL_H_
#include <systemc.h>
#include <tlm.h>
#include "scsim_common.h"
//LUT_COMMENT #include "NvdlaLut.h"
// //LUT_COMMENT class NvdlaLut;
SCSIM_NAMESPACE_START(clib)
SCSIM_NAMESPACE_END()
SCSIM_NAMESPACE_START(cmod)
// Forward declarating cmacro parsed register model class
class CNVDLA_CDMA_REGSET;
//
class cdma_reg_model {
public:
cdma_reg_model();
~cdma_reg_model();
protected:
//bool is_there_ongoing_cdma_csb_response_;
CNVDLA_CDMA_REGSET *cdma_register_group_0;
CNVDLA_CDMA_REGSET *cdma_register_group_1;
sc_event event_cdma_reg_group_0_operation_enable;
sc_event event_cdma_reg_group_1_operation_enable;
//LUT_COMMENT NvdlaLut *cdma_lut;
uint32_t cdma_lut_table_idx; // 0: RAW, 1: DENSITY
uint32_t cdma_lut_entry_idx;
uint32_t cdma_lut_data;
uint32_t cdma_lut_access;
// Register field variables
uint8_t cdma_status_0_;
uint8_t cdma_status_1_;
uint8_t cdma_producer_;
uint8_t cdma_consumer_;
uint8_t cdma_arb_weight_;
uint8_t cdma_arb_wmb_;
uint8_t cdma_flush_done_;
uint8_t cdma_op_en_;
uint8_t cdma_conv_mode_;
uint8_t cdma_in_precision_;
uint8_t cdma_proc_precision_;
uint8_t cdma_data_reuse_;
uint8_t cdma_weight_reuse_;
uint8_t cdma_skip_data_rls_;
uint8_t cdma_skip_weight_rls_;
uint8_t cdma_datain_format_;
uint8_t cdma_pixel_format_;
uint8_t cdma_pixel_mapping_;
uint8_t cdma_pixel_sign_override_;
uint16_t cdma_datain_width_;
uint16_t cdma_datain_height_;
uint16_t cdma_datain_channel_;
uint16_t cdma_datain_width_ext_;
uint16_t cdma_datain_height_ext_;
uint8_t cdma_pixel_x_offset_;
uint8_t cdma_pixel_y_offset_;
uint8_t cdma_datain_ram_type_;
uint32_t cdma_datain_addr_high_0_;
uint32_t cdma_datain_addr_low_0_;
uint32_t cdma_datain_addr_high_1_;
uint32_t cdma_datain_addr_low_1_;
uint32_t cdma_line_stride_;
uint32_t cdma_uv_line_stride_;
uint32_t cdma_surf_stride_;
uint8_t cdma_line_packed_;
uint8_t cdma_surf_packed_;
uint16_t cdma_rsv_per_line_;
uint16_t cdma_rsv_per_uv_line_;
uint8_t cdma_rsv_height_;
uint8_t cdma_rsv_y_index_;
uint8_t cdma_batches_;
uint32_t cdma_batch_stride_;
uint16_t cdma_entries_;
uint16_t cdma_grains_;
uint8_t cdma_weight_format_;
uint32_t cdma_byte_per_kernel_;
uint16_t cdma_weight_kernel_;
uint8_t cdma_weight_ram_type_;
uint32_t cdma_weight_addr_high_;
uint32_t cdma_weight_addr_low_;
uint32_t cdma_weight_bytes_;
uint32_t cdma_wgs_addr_high_;
uint32_t cdma_wgs_addr_low_;
uint32_t cdma_wmb_addr_high_;
uint32_t cdma_wmb_addr_low_;
uint32_t cdma_wmb_bytes_;
uint8_t cdma_mean_format_;
uint16_t cdma_mean_ry_;
uint16_t cdma_mean_gu_;
uint16_t cdma_mean_bv_;
uint16_t cdma_mean_ax_;
uint8_t cdma_cvt_en_;
uint8_t cdma_cvt_truncate_;
uint16_t cdma_cvt_offset_;
uint16_t cdma_cvt_scale_;
uint8_t cdma_conv_x_stride_;
uint8_t cdma_conv_y_stride_;
uint8_t cdma_pad_left_;
uint8_t cdma_pad_right_;
uint8_t cdma_pad_top_;
uint8_t cdma_pad_bottom_;
uint16_t cdma_pad_value_;
uint8_t cdma_data_bank_;
uint8_t cdma_weight_bank_;
uint8_t cdma_nan_to_zero_;
uint32_t cdma_nan_data_num_;
uint32_t cdma_nan_weight_num_;
uint32_t cdma_inf_data_num_;
uint32_t cdma_inf_weight_num_;
uint8_t cdma_dma_en_;
uint32_t cdma_dat_rd_stall_;
uint32_t cdma_wt_rd_stall_;
uint32_t cdma_dat_rd_latency_;
uint32_t cdma_wt_rd_latency_;
uint32_t cdma_cya_;
// CSB request target socket
// void csb2cdma_b_transport (int ID, NV_MSDEC_csb2xx_16m_secure_be_lvl_t* payload, sc_time& delay);
// CSB response send function
// void CdmaSendCsbResponse(uint32_t date, uint8_t error_id);
// Register accessing
bool CdmaAccessRegister(uint32_t reg_addr, uint32_t & data, bool is_write);
// Reset
void CdmaRegReset();
// Update configuration from register to variable
void CdmaUpdateVariables(CNVDLA_CDMA_REGSET *reg_group_ptr);
bool CdmaUpdateStatusRegister(uint32_t addr, uint8_t group, uint32_t reg);
void CdmaClearOpeartionEnable(CNVDLA_CDMA_REGSET *reg_group_ptr);
uint32_t CdmaGetOpeartionEnable(CNVDLA_CDMA_REGSET *reg_group_ptr);
void CdmaIncreaseConsumerPointer();
void CdmaUpdateWorkingStatus(uint32_t group_id, uint32_t status);
void CdmaUpdateStatRegisters(uint32_t group_id);
void CdmaUpdateStatRegisters(uint32_t group_id, uint32_t data_nan_num, uint32_t weight_nan_num, uint32_t data_inf_num, uint32_t weight_inf_num);
void CdmaUpdateStatRegisters(uint32_t group_id, uint32_t saturation_num);
//LUT read/write functions
//LUT_COMMENT virtual uint16_t read_lut() = 0;
//LUT_COMMENT virtual void write_lut() = 0;
};
SCSIM_NAMESPACE_END()
#endif
|
/**
* @license MIT
* @brief Private type definitions for Huffman coding.
*/
#ifndef HUFFMAN_CODING_PRIV_TYPES_H
#define HUFFMAN_CODING_PRIV_TYPES_H
///////////////////////////////////////////////////////////////////////////////
#include <stdint.h>
#include <systemc.h>
#include "huffman_coding_public_types.h"
#include "huffman_coding_priv_config.h"
///////////////////////////////////////////////////////////////////////////////
namespace huffman_coding {
typedef sc_uint<freq_width> freq_t;
typedef sc_uint<freq_width> node_t;
typedef sc_uint<dep_width> dep_t;
typedef sc_uint<len_width> len_t;
typedef sc_uint<len_freq_width> len_freq_t;
typedef sc_uint<code_width> code_t;
}
///////////////////////////////////////////////////////////////////////////////
#endif // HUFFMAN_CODING_PRIV_TYPES_H
|
#ifndef IPS_FILTER_TLM_CPP
#define IPS_FILTER_TLM_CPP
#include <systemc.h>
using namespace sc_core;
using namespace sc_dt;
using namespace std;
#include <tlm.h>
#include <tlm_utils/simple_initiator_socket.h>
#include <tlm_utils/simple_target_socket.h>
#include <tlm_utils/peq_with_cb_and_phase.h>
#include "ips_filter_tlm.hpp"
#include "common_func.hpp"
#include "important_defines.hpp"
void ips_filter_tlm::do_when_read_transaction(unsigned char*& data, unsigned int data_length, sc_dt::uint64 address)
{
dbgimgtarmodprint(use_prints, "Called do_when_read_transaction with an address %016llX and length %d", address, data_length);
this->img_result = *(Filter<IPS_IN_TYPE_TB, IPS_OUT_TYPE_TB, IPS_FILTER_KERNEL_SIZE>::result_ptr);
*data = (unsigned char) this->img_result;
dbgimgtarmodprint(true, "Returning filter result %f", this->img_result);
//memcpy(data, Filter<IPS_IN_TYPE_TB, IPS_OUT_TYPE_TB, IPS_FILTER_KERNEL_SIZE>::result_ptr, sizeof(IPS_OUT_TYPE_TB));
}
void ips_filter_tlm::do_when_write_transaction(unsigned char*& data, unsigned int data_length, sc_dt::uint64 address)
{
IPS_OUT_TYPE_TB* result = new IPS_OUT_TYPE_TB;
dbgimgtarmodprint(use_prints, "Called do_when_write_transaction with an address %016llX and length %d", address, data_length);
//dbgimgtarmodprint(use_prints, "[DEBUG]: data: %0d, address %0d, data_length %0d, size of char %0d", *data, address, data_length, sizeof(char));
for (int i = 0; i < data_length; i++) {
this->img_window[address + i] = (IPS_IN_TYPE_TB) *(data + i);
}
//dbgimgtarmodprint(use_prints, "[DEBUG]: img_window data: %0f", this->img_window[address]);
if (address == 8) {
dbgimgtarmodprint(true, "Got full window, starting filtering now");
filter(this->img_window, result);
}
}
#endif // IPS_FILTER_TLM_CPP
|
////////////////////////////////////////////////////////////
// tb.h
// Testbench
#ifndef __TB_H__
#define __TB_H__
#include <cstdlib>
#include <systemc.h>
enum stim_select_t {
STIM_UNIT_STEP,
STIM_RANDOM
};
SC_MODULE (tb) {
sc_in < bool > clk;
sc_out < bool > rstn;
sc_out < sc_int<32> > in;
sc_out < bool > in_vld;
sc_in < bool > in_rdy;
sc_in < sc_int<32> > out;
sc_in < bool > out_vld;
sc_out < bool > out_rdy;
void driver();
void monitor();
sc_int<32> stim_unit_step(int);
sc_int<32> stim_random(int);
stim_select_t stim_select;
SC_CTOR(tb) {
std::srand(0);
// argument
std::string arg;
for (int i=1; i != sc_argc(); ++i) {
arg = sc_argv()[i];
// stimulus
stim_select = STIM_UNIT_STEP;
if (arg.compare("-stim_unit_step")) {
stim_select = STIM_UNIT_STEP;
}
if (arg.compare("-stim_random")) {
stim_select = STIM_RANDOM;
}
switch (stim_select) {
case STIM_UNIT_STEP:
std::cout << "Select stimulus: unit step" << std::endl;
break;
case STIM_RANDOM:
std::cout << "Select stimulus: random" << std::endl;
break;
}
}
// driver
SC_CTHREAD(driver, clk.pos());
// monitor
SC_CTHREAD(monitor, clk.pos());
}
};
#endif
|
/**
* @file
* @copyright Copyright 2016 GNSS Sensor Ltd. All right reserved.
* @author Sergey Khabarov - [email protected]
* @brief CPU Memory Access stage.
*/
#ifndef __DEBUGGER_RIVERLIB_MEMSTAGE_H__
#define __DEBUGGER_RIVERLIB_MEMSTAGE_H__
#include <systemc.h>
#include "../river_cfg.h"
namespace debugger {
SC_MODULE(MemAccess) {
sc_in<bool> i_clk;
sc_in<bool> i_nrst;
sc_in<bool> i_e_valid; // Execution stage outputs are valid
sc_in<sc_uint<BUS_ADDR_WIDTH>> i_e_pc; // Execution stage instruction pointer
sc_in<sc_uint<32>> i_e_instr; // Execution stage instruction value
sc_in<sc_uint<5>> i_res_addr; // Register address to be written (0=no writing)
sc_in<sc_uint<RISCV_ARCH>> i_res_data; // Register value to be written
sc_in<bool> i_memop_sign_ext; // Load data with sign extending (if less than 8 Bytes)
sc_in<bool> i_memop_load; // Load data from memory and write to i_res_addr
sc_in<bool> i_memop_store; // Store i_res_data value into memory
sc_in<sc_uint<2>> i_memop_size; // Encoded memory transaction size in bytes: 0=1B; 1=2B; 2=4B; 3=8B
sc_in<sc_uint<BUS_ADDR_WIDTH>> i_memop_addr; // Memory access address
sc_out<bool> o_wena; // Write enable signal
sc_out<sc_uint<5>> o_waddr; // Output register address (0 = x0 = no write)
sc_out<sc_uint<RISCV_ARCH>> o_wdata; // Register value
// Memory interface:
sc_in<bool> i_mem_req_ready; // Data cache is ready to accept request
sc_out<bool> o_mem_valid; // Memory request is valid
sc_out<bool> o_mem_write; // Memory write request
sc_out<sc_uint<2>> o_mem_sz; // Encoded data size in bytes: 0=1B; 1=2B; 2=4B; 3=8B
sc_out<sc_uint<BUS_ADDR_WIDTH>> o_mem_addr; // Data path requested address
sc_out<sc_uint<BUS_DATA_WIDTH>> o_mem_data; // Data path requested data (write transaction)
sc_in<bool> i_mem_data_valid; // Data path memory response is valid
sc_in<sc_uint<BUS_ADDR_WIDTH>> i_mem_data_addr; // Data path memory response address
sc_in<sc_uint<BUS_DATA_WIDTH>> i_mem_data; // Data path memory response value
sc_out<bool> o_mem_resp_ready; // Pipeline is ready to accept memory operation response
sc_out<bool> o_hold; // Hold pipeline by data cache wait state reason
sc_out<bool> o_valid; // Output is valid
sc_out<sc_uint<BUS_ADDR_WIDTH>> o_pc; // Valid instruction pointer
sc_out<sc_uint<32>> o_instr; // Valid instruction value
void comb();
void registers();
SC_HAS_PROCESS(MemAccess);
MemAccess(sc_module_name name_);
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
struct RegistersType {
sc_signal<bool> valid;
sc_signal<sc_uint<BUS_ADDR_WIDTH>> pc;
sc_signal<sc_uint<32>> instr;
sc_signal<bool> wena;
sc_signal<sc_uint<5>> waddr;
sc_signal<bool> sign_ext;
sc_signal<sc_uint<2>> size;
sc_signal<sc_uint<RISCV_ARCH>> wdata;
sc_signal<bool> wait_req;
sc_signal<bool> wait_req_write;
sc_signal<sc_uint<2>> wait_req_sz;
sc_signal<sc_uint<BUS_ADDR_WIDTH>> wait_req_addr;
sc_signal<sc_uint<RISCV_ARCH>> wait_req_wdata;
sc_signal<bool> wait_resp;
} v, r;
};
} // namespace debugger
#endif // __DEBUGGER_RIVERLIB_EXECUTE_H__
|
#ifndef GEMMDRIVER_H
#define GEMMDRIVER_H
#define FULLSIM
#include <sys/time.h>
#include <fstream>
#include <iostream>
#include <iomanip>
#include <cstdlib>
#include <systemc.h>
#ifdef FULLSIM
#include "../acc_comps/acc.h"
#else
#include "acc.h"
#endif
SC_MODULE(GemmDriver) {
sc_in<bool> clock;
sc_in <bool> reset;
sc_fifo_in<DATA> dout1;
sc_fifo_in<DATA> dout2;
sc_fifo_in<DATA> dout3;
sc_fifo_in<DATA> dout4;
sc_fifo_out<DATA> din1;
sc_fifo_out<DATA> din2;
sc_fifo_out<DATA> din3;
sc_fifo_out<DATA> din4;
bool sent;
bool retval;
//States
int states[9];
sc_signal<int> sourceS;
sc_signal<int> sinkS;
sc_in<int> inS;
sc_in<int> outS;
sc_in<int> w1S;
sc_in<int> w2S;
sc_in<int> w3S;
sc_in<int> w4S;
sc_in<int> schS;
sc_in<int> p1S;
sc_in<int> read_cycle_count;
sc_in<int> process_cycle_count;
sc_in<int> gemm_1_idle;
sc_in<int> gemm_2_idle;
sc_in<int> gemm_3_idle;
sc_in<int> gemm_4_idle;
sc_in<int> gemm_1_write;
sc_in<int> gemm_2_write;
sc_in<int> gemm_3_write;
sc_in<int> gemm_4_write;
sc_in<int> gemm_1;
sc_in<int> gemm_2;
sc_in<int> gemm_3;
sc_in<int> gemm_4;
sc_in<int> wstall_1;
sc_in<int> wstall_2;
sc_in<int> wstall_3;
sc_in<int> wstall_4;
sc_in<int> rmax;
sc_in<int> lmax;
int p_cycles= 0;
int waiting= 0;
int loading= 0;
int g1_idle= 0;
int g2_idle= 0;
int g3_idle= 0;
int g4_idle= 0;
int g1_write= 0;
int g2_write= 0;
int g3_write= 0;
int g4_write= 0;
int g1_gemm= 0;
int g2_gemm= 0;
int g3_gemm= 0;
int g4_gemm= 0;
int wstall1=0;
int wstall2=0;
int wstall3=0;
int wstall4=0;
int r_max=0;
int l_max=0;
void Source();
void Sink();
void Status();
void read_in();
void read_out();
SC_HAS_PROCESS(GemmDriver);
// Parameters for the DUT
GemmDriver(sc_module_name name_) :sc_module(name_) { // @suppress("Class members should be properly initialized")
SC_CTHREAD(Source, clock.pos());
reset_signal_is(reset,true);
SC_CTHREAD(Sink, clock.pos());
reset_signal_is(reset,true);
SC_CTHREAD(Status, clock.neg());
reset_signal_is(reset,true);
}
int inl0;
int inl1;
int inl2;
int inl3;
int in0[563840];
int in1[563840];
int in2[563840];
int in3[563840];
int out0[554800];
int out1[554800];
int out2[554800];
int out3[554800];
};
#endif /* GEMMDRIVER_H */
|
//
//------------------------------------------------------------//
// Copyright 2009-2012 Mentor Graphics Corporation //
// All Rights Reserved Worldwid //
// //
// Licensed under the Apache License, Version 2.0 (the //
// "License"); you may not use this file except in //
// compliance with the License. You may obtain a copy of //
// the License at //
// //
// http://www.apache.org/licenses/LICENSE-2.0 //
// //
// Unless required by applicable law or agreed to in //
// writing, software distributed under the License is //
// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR //
// CONDITIONS OF ANY KIND, either express or implied. See //
// the License for the specific language governing //
// permissions and limitations under the License. //
//------------------------------------------------------------//
//-----------------------------------------------------------------------------
// Title: UVMC Command API
//
// This section describes the API for accessing and controlling UVM simulation
// in SystemVerilog from SystemC (or C or C++). To use, the SV side must have
// called the ~uvmc_init~, which starts a background process that receives and
// processes incoming commands.
//
// The UVM Connect library provides an SystemC API for accessing SystemVeilog
// UVM during simulation. With this API users can:
//
// - Wait for a UVM to reach a given simulation phase
// - Raise and drop objections
// - Set and get UVM configuration
// - Send UVM report messages
// - Set type and instance overrides in the UVM factory
// - Print UVM component topology
//
// While most commands are compatible with C, a few functions take object
// arguments or block on sc_events. Therefore, SystemC is currently the only
// practical source language for using the UVM Command API. Future releases may
// separate the subset of C-compatible functions into a separate shared library
// that would not require linking in SystemC.
//
// The following may appear in a future release, based on demand
//
// - Callbacks on phase and objection activity
// - Receive UVM report messages, i.e. SC-side acts as report catcher or server
// - Integration with SystemCs sc_report_handler facility
// - Print factory contents, config db contents, and other UVM information
// - Separate command layer into SC, C++, and C-accessible components; i.e.
// not require SystemC for non-SystemC-dependent functions
//
// The following sections provide details and examples for each command in the
// UVM Command API. To enable access to the UVM command layer, you must call
// the uvmc_cmd_init function from an initial block in a top-level module as in
// the following example:
//
// SystemVerilog:
//
//| module sv_main;
//|
//| import uvm_pkg::*;
//| import uvmc_pkg::*;
//|
//| initial begin
//| uvmc_cmd_init();
//| run_test();
//| end
//|
//| endmodule
//
// SystemC-side calls to the UVM Command API will block until SystemVerilog has
// finished elaboration and the uvmc_cmd_init function has been called. Because
// any call to the UVM Command layer may block, calls must be made from within
// thread processes.
//
// All code provided in the UVM Command descriptions that follow are SystemC
// unless stated otherwise.
#ifndef UVMC_COMMANDS_H
#define UVMC_COMMANDS_H
#include "svdpi.h"
#include <string>
#include <map>
#include <vector>
#include <iomanip>
#include <systemc.h>
#include <tlm.h>
using namespace sc_core;
using namespace sc_dt;
using namespace tlm;
using std::string;
using std::map;
using std::vector;
using sc_core::sc_semaphore;
#include "uvmc_common.h"
#include "uvmc_convert.h"
extern "C" {
//------------------------------------------------------------------------------
// Group: Enumeration Constants
//
// The following enumeration constants are used in various UVM Commands:
//------------------------------------------------------------------------------
// Enum: uvmc_phase_state
//
// The state of a UVM phase
//
// UVM_PHASE_DORMANT - Phase has not started yet
// UVM_PHASE_STARTED - Phase has started
// UVM_PHASE_EXECUTING - Phase is executing
// UVM_PHASE_READY_TO_END - Phase is ready to end
// UVM_PHASE_ENDED - Phase has ended
// UVM_PHASE_DONE - Phase has completed
//
enum uvmc_phase_state {
UVM_PHASE_DORMANT = 1,
UVM_PHASE_SCHEDULED = 2,
UVM_PHASE_SYNCING = 4,
UVM_PHASE_STARTED = 8,
UVM_PHASE_EXECUTING = 16,
UVM_PHASE_READY_TO_END = 32,
UVM_PHASE_ENDED = 64,
UVM_PHASE_CLEANUP = 128,
UVM_PHASE_DONE = 256,
UVM_PHASE_JUMPING = 512
};
// Enum: uvmc_report_severity
//
// The severity of a report
//
// UVM_INFO - Informative message. Verbosity settings affect whether
// they are printed.
// UVM_WARNING - Warning. Not affected by verbosity settings.
// UVM_ERROR - Error. Error counter incremented by default. Not affected
// by verbosity settings.
// UVM_FATAL - Unrecoverable error. SV simulation will end immediately.
//
enum uvmc_report_severity {
UVM_INFO,
UVM_WARNING,
UVM_ERROR,
UVM_FATAL
};
// Enum: uvmc_report_verbosity
//
// The verbosity level assigned to UVM_INFO reports
//
// UVM_NONE - report will always be issued (unaffected by
// verbosity level)
// UVM_LOW - report is issued at low verbosity setting and higher
// UVM_MEDIUM - report is issued at medium verbosity and higher
// UVM_HIGH - report is issued at high verbosity and higher
// UVM_FULL - report is issued only when verbosity is set to full
//
enum uvmc_report_verbosity {
UVM_NONE = 0,
UVM_LOW = 100,
UVM_MEDIUM = 200,
UVM_HIGH = 300,
UVM_FULL = 400
};
// Enum: uvmc_wait_op
//
// The relational operator to apply in <uvmc_wait_for_phase> calls
//
// UVM_LT - Wait until UVM is before the given phase
// UVM_LTE - Wait until UVM is before or at the given phase
// UVM_NE - Wait until UVM is not at the given phase
// UVM_EQ - Wait until UVM is at the given phase
// UVM_GT - Wait until UVM is after the given phase
// UVM_GTE - Wait until UVM is at or after the given phase
//
enum uvmc_wait_op {
UVM_LT,
UVM_LTE,
UVM_NE,
UVM_EQ,
UVM_GT,
UVM_GTE
};
void wait_sv_ready();
} // extern "C"
//------------------------------------------------------------------------------
// UVM COMMANDS
extern "C" {
// Internal API (SV DPI Export Functions)
void UVMC_print_topology(const char* context="", int depth=-1);
bool UVMC_report_enabled (const char* context,
int verbosity,
int severity,
const char* id);
void UVMC_set_report_verbosity(int level,
const char* context,
bool recurse=0);
void UVMC_report (int severity,
const char* id,
const char* message,
int verbosity,
const char* context,
const char* filename,
int line);
// up to 64 bits
void UVMC_set_config_int (const char* context, const char* inst_name,
const char* field_name, uint64 value);
void UVMC_set_config_object (const char* type_name,
const char* context, const char* inst_name,
const char* field_name, const bits_t *value);
void UVMC_set_config_string (const char* context, const char* inst_name,
const char* field_name, const char* value);
bool UVMC_get_config_int (const char* context, const char* inst_name,
const char* field_name, uint64 *value);
bool UVMC_get_config_object (const char* type_name,
const char* context, const char* inst_name,
const char* field_name, bits_t* bits);
bool UVMC_get_config_string (const char* context, const char* inst_name,
const char* field_name, const char** value);
void UVMC_raise_objection (const char* name, const char* context="",
const char* description="", unsigned int count=1);
void UVMC_drop_objection (const char* name, const char* context="",
const char* description="", unsigned int count=1);
void UVMC_print_factory (int all_types=1);
void UVMC_set_factory_inst_override
(const char* original_type_name,
const char* override_type_name,
const char* full_inst_path);
void UVMC_set_factory_type_override (const char* original_type_name,
const char* override_type_name,
bool replace=1);
void UVMC_debug_factory_create (const char* requested_type,
const char* context="");
void UVMC_find_factory_override (const char* requested_type,
const char* context,
const char** override_type_name);
int UVMC_wait_for_phase_request(const char *phase, int state, int op);
void UVMC_get_uvm_version(unsigned int *major, unsigned int *minor, char **fix);
bool SV2C_phase_notification(int id);
bool SV2C_sv_ready();
void uvmc_set_scope(); // internal
} // extern "C"
extern "C" {
//------------------------------------------------------------------------------
// Group: Topology
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Function: uvmc_print_topology
//
// Prints the current UVM testbench topology.
//
// If called prior to UVM completing the build phase,
// the topology will be incomplete.
//
// Arguments:
//
// context - The hierarchical path of the component from which to start printing
// topology. If unspecified, topology printing will begin at
// uvm_top. Multiple components can be specified by using glob
// wildcards (* and ?), e.g. "top.env.*.driver". You can also specify
// a POSIX extended regular expression by enclosing the contxt in
// forward slashes, e.g. "/a[hp]b/". Default: "" (uvm_top)
//
// depth - The number of levels of hierarchy to print. If not specified,
// all levels of hierarchy starting from the given context are printed.
// Default: -1 (recurse all children)
//------------------------------------------------------------------------------
//
void uvmc_print_topology (const char *context="", int depth=-1);
//------------------------------------------------------------------------------
// Group: Reporting
//
// The reporting API provides the ability to issue UVM reports, set verbosity,
// and other reporting features.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Function: uvmc_report_enabled
//
// Returns true if a report at the specified verbosity, severity, and id would
// be emitted if made within the specified component contxt.
//
// The primary purpose of this command is to determine whether a report has a
// chance of being emitted before incurring the high run-time overhead of
// formatting the string message.
//
// A report at severity UVM_INFO is ignored if its verbosity is greater than
// the verbosity configured for the component in which it is issued. Reports at
// other severities are not affected by verbosity settings.
//
// If the action of a report with the specified severity and id is configured
// as UVM_NO_ACTION within the specified component contxt.
//
// Filtration by any registered report_catchers is not considered.
//
// Arguments:
//
// verbosity - The uvmc_report_verbosity of the hypothetical report.
//
// severity - The <uvmc_report_severity> of the hypothetical report.
// Default: UVM_INFO.
//
// id - The identifier string of the hypothetical report. Must be an
// exact match. If not specified, then uvmc_report_enabled checks
// only if UVM_NO_ACTION is the configured action for the given
// severity at the specified context. Default: "" (unspecified)
//
// context - The hierarchical path of the component that would issue the
// hypothetical report. If not specified, the context is global,
// i.e. uvm_top. Reports not issued by components come from uvm_top.
// Default: "" (unspecified)
//
// Example:
//
//| if (uvmc_report_enabled(UVM_HIGH, UVM_INFO, "PRINT_TRANS") {
//| string detailed_msg;
//| ...prepare message string here...
//| uvmc_report(UVM_INFO, "PRINT_TRANS", detailed_msg, UVM_HIGH);
//| }
//------------------------------------------------------------------------------
//
bool uvmc_report_enabled (int verbosity,
int severity=UVM_INFO,
const char* id="",
const char* context="");
//------------------------------------------------------------------------------
// Function: uvmc_set_report_verbosity
//
// Sets the run-time verbosity level for all UVM_INFO-severity reports issued
// by the component(s) at the specified context. Any report from the component
// context whose verbosity exceeds this maximum will be ignored.
//
// Reports issued by SC via uvmc_report are affected only by the verbosity level
// setting for the global context, i.e. context="". To have finer-grained
// control over SC-issued reports, register a uvm_report_catcher with uvm_top.
//
// Arguments:
//
// level - The verbosity level. Specify UVM_NONE, UVM_LOW, UVM_MEDIUM,
// UVM_HIGH, or UVM_FULL. Required.
//
// context - The hierarchical path of the component. Multiple components can be
// specified by using glob wildcards * and ?, e.g. "top.env.*.driver".
// You can also specify a POSIX extended regular expression by
// enclosing the contxt in forward slashes, e.g. "/a[hp]b/".
// Default: "" (uvm_top)
//
// recurse - If true, sets the verbosity of all descendents of the component(s)
// matching context. Default:false
//
// Examples:
//
// Set global UVM report verbosity to maximum (FULL) output:
//
// | uvmc_set_report_verbosity(UVM_FULL);
//
// Disable all filterable INFO reports for the top.env.agent1.driver,
// but none of its children:
//
// | uvmc_set_report_verbosity(UVM_NONE, "top.env.agent1.driver");
//
// Set report verbosity for all components to UVM_LOW, except for the
// troublemaker component, which gets UVM_HIGH verbosity:
//
// | uvmc_set_report_verbosity(UVM_LOW, true);
// | uvmc_set_report_verbosity(UVM_HIGH, "top.env.troublemaker");
//
// In the last example, the recursion flag is set to false, so all of
// troublemaker's children, if any, will remain at UVM_LOW verbosity.
//------------------------------------------------------------------------------
void uvmc_set_report_verbosity (int level,
const char* context="",
bool recurse=0);
//------------------------------------------------------------------------------
// Function: uvmc_report
//
// Send a report to UVM for processing, subject to possible filtering by
// verbosity, action, and active report catchers.
//
// See uvmc_report_enabled to learn how a report may be filtered.
//
// The UVM report mechanism is used instead of $display and other ad hoc
// approaches to ensure consistent output and to control whether a report is
// issued and what if any actions are taken when it is issued. All reporting
// methods have the same arguments, except a verbosity level is applied to
// UVM_INFO-severity reports.
//
// Arguments:
//
// severity - The report severity: specify either UVM_INFO, UVM_WARNING,
// UVM_ERROR, or UVM_FATAL. Required argument.
//
// id - The report id string, used for identification and targeted
// filtering. See context description for details on how the
// report's id affects filtering. Required argument.
//
// message - The message body, pre-formatted if necessary to a single string.
// Required.
//
// verbosity - The verbosity level indicating an INFO report's relative detail.
// Ignored for warning, error, and fatal reports. Specify UVM_NONE,
// UVM_LOW, UVM_MEDIUM, UVM_HIGH, or UVM_FULL. Default: UVM_MEDIUM.
//
// context - The hierarchical path of the SC-side component issuing the
// report. The context string appears as the hierarchical name in
// the report on the SV side, but it does not play a role in report
// filtering in all cases. All SC-side reports are issued from the
// global context in UVM, i.e. uvm_top. To apply filter settings,
// make them from that context, e.g. uvm_top.set_report_id_action().
// With the context fixed, only the report's id can be used to
// uniquely identify the SC report to filter. Report catchers,
// however, are passed the report's context and so can filter based
// on both SC context and id. Default: "" (unspecified)
//
// filename - The optional filename from which the report was issued. Use
// __FILE__. If specified, the filename will be displayed as part
// of the report. Default: "" (unspecified)
//
// line - The optional line number within filename from which the report
// was issued. Use __LINE__. If specified, the line number will be
// displayed as part of the report. Default: 0 (unspecified)
//
// Examples:
//
// Send a global (uvm_top-sourced) info report of medium verbosity to UVM:
//
// | uvmc_report(UVM_INFO, "SC_READY", "SystemC side is ready");
//
// Issue the same report, this time with low verbosity a filename and line number.
//
// | uvmc_report(UVM_INFO, "SC_READY", "SystemC side is ready",
// | UVM_LOW, "", __FILE__, __LINE__);
//
// UVM_LOW verbosity does not mean lower output. On the contrary, reports with
// UVM_LOW verbosity are printed if the run-time verbosity setting is anything
// but UVM_NONE. Reports issued with UVM_NONE verbosity cannot be filtered by
// the run-time verbosity setting.
//
// The next example sends a WARNING and INFO report from an SC-side producer
// component. In SV, we disable the warning by setting the action for its
// effective ID to UVM_NO_ACTION. We also set the verbosity threshold for INFO
// messages with the effective ID to UVM_NONE. This causes the INFO report to
// be filtered, as the run-time verbosity for reports of that particular ID are
// now much lower than the reports stated verbosity level (UVM_HIGH).
//
//| class producer : public sc_module {
//| ...
//| void run_thread() {
//| ...
//| uvmc_report(UVM_WARNING, "TransEvent",
//| "Generated error transaction.",, this.name());
//| ...
//| uvmc_report(UVM_INFO, "TransEvent",
//| "Transaction complete.", UVM_HIGH, this.name());
//| ...
//| }
//| };
//
// To filter SC-sourced reports on the SV side:
//
//| uvm_top.set_report_id_action("TransEvent@top/prod",UVM_NO_ACTION);
//| uvm_top.set_report_id_verbosity("TransEvent@top/prod",UVM_NONE);
//| uvm_top.set_report_id_verbosity("TransDump",UVM_NONE);
// |
// The last statement disables all reports to the global context (uvm_top)
// having the ID "TransDump". Note that it is currently not possible to
// set filters for reports for several contexts at once using wildcards. Also,
// the hierarchical separator for SC may be configurable in your simulator, and
// thus could affect the context provided to these commands.
//------------------------------------------------------------------------------
void uvmc_report (int severity,
const char* id,
const char* message,
int verbosity=UVM_MEDIUM,
const char* context="",
const char* filename="",
int line=0);
// Function: uvmc_report_info
//
// Equivalent to <uvmc_report> (UVM_INFO, ...)
void uvmc_report_info (const char* id,
const char* message,
int verbosity=UVM_MEDIUM,
const char* context="",
const char* filename="",
int line=0);
// Function: uvmc_report_warning
//
// Equivalent to <uvmc_report> (UVM_WARNING, ...)
void uvmc_report_warning (const char* id,
const char* message,
const char* context="",
const char* filename="",
int line=0);
// Function: uvmc_report_error
//
// Equivalent to <uvmc_report> (UVM_ERROR, ...)
void uvmc_report_error (const char* id,
const char* message,
const char* context="",
const char* filename="",
int line=0);
// Function: uvmc_report_fatal
//
// Equivalent to <uvmc_report> (UVM_FATAL, ...)
void uvmc_report_fatal (const char* id,
const char* message,
const char* context="",
const char* filename="",
int line=0);
//------------------------------------------------------------------------------
// Topic: Report Macros
//
// Convenience macros to <uvmc_report>.
// See <uvmc_report> for details on macro arguments.
//
// | UVMC_INFO (ID, message, verbosity, context)
// | UVMC_WARNING (ID, message, context)
// | UVMC_ERROR (ID, message, context)
// | UVMC_FATAL (ID, message, context)
//
//
// Before sending the report, the macros first call <uvmc_report_enabled> to
// avoid sending the report at all if its verbosity or action would prevent
// it from reaching the report server. If the report is enabled, then
// <uvmc_report> is called with the filename and line number arguments
// provided for you.
//
// Invocations of these macros must be terminated with semicolons, which is
// in keeping with the SystemC convention established for the ~SC_REPORT~
// macros. Future releases may provide a UVMC sc_report_handler that you
// can use to redirect all SC_REPORTs to UVM.
//
// Example:
//
//| UVMC_ERROR("SC_TOP/NO_CFG","Missing required config object", name());
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Group: Phasing
//
// An API that provides access UVM's phase state and the objection objects used
// to control phase progression.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Function: uvmc_wait_for_phase
//
// Wait for a UVM phase to reach a certain state.
//
// The call must be made from a SystemC process thread that is either statically
// declared via SC_THREAD or dynamically started via sc_spawn. If the latter,
// you must include the following define on the sccom command
// line: -DSC_INCLUDE_DYNAMIC_PROCESSES.
//
// Arguments:
//
// phase - The name of the phase to wait on. The built-in phase names are, in
// order of execution: build, connect, end_of_elaboration,
// start_of_simulation, run, extract, check, report. The fine-grained
// run-time phases, which run in parallel with the run phase, are, in
// order: pre_reset, reset, post_reset, pre_configure, configure,
// post_configure, pre_main, main, post_main, pre_shutdown, shutdown,
// and post_shutdown.
//
// state - The state to wait on. A phase may transition through
// ~UVM_PHASE_JUMPING~ instead of UVM_PHASE_READY_TO_END if its
// execution had been preempted by a phase jump operation. Phases
// execute in the following state order:
//
// | UVM_PHASE_STARTED
// | UVM_PHASE_EXECUTING
// | UVM_PHASE_READY_TO_END | UVM_PHASE_JUMPING
// | UVM_PHASE_ENDED
// | UVM_PHASE_DONE
//
// condition - The state condition to wait for. When state is
// ~UVM_PHASE_JUMPING~, ~condition~ must be UVM_EQ. Default is
// ~UVM_EQ~. Valid values are:
//
// | UVM_LT - Phase is before the given state.
// | UVM_LTE - Phase is before or at the given state.
// | UVM_EQ - Phase is at the given state.
// | UVM_GTE - Phase is at or after the given state.
// | UVM_GT - Phase is after the given state.
// | UVM_NE - Phase is not at the given state.
//
//
// Examples:
//
// The following example shows how to spawn threads that correspond to UVM's
// phases. Here, the ~run_phase~ method executes during the UVM's run phase.
// As any UVM component executing the run phase would do, the SC component's
// ~run_phase~ process prevents the UVM (SV-side) run phase from ending until
// it is finished by calling <uvmc_drop_objection>.
//
//| SC_MODULE(top)
//| {
//| sc_process_handle run_proc;
//|
//| SC_CTOR(top) {
//| run_proc = sc_spawn(sc_bind(&run_phase,this),"run_phase");
//| };
//|
//| void async_reset() {
//| if (run_proc != null && run_proc.valid())
//| run_proc.reset(SC_INCLUDE_DESCENDANTS);
//| }
//|
//| void run_phase() {
//| uvmc_wait_for_phase("run",UVM_PHASE_STARTED,UVM_EQ);
//| uvmc_raise_objection("run","","SC run_phase executing");
//| ...
//| uvmc_drop_objection("run","","SC run_phase finished");
//| }
//| };
//
// If ~async_reset~ is called, the run_proc process and all descendants are
// killed, then run_proc is restarted. The run_proc calls run_phase again,
// which first waits for the UVM to reach the run_phase before resuming
// its work.
//------------------------------------------------------------------------------
void uvmc_wait_for_phase(const char *phase,
uvmc_phase_state state,
uvmc_wait_op op=UVM_EQ);
//------------------------------------------------------------------------------
// Function: uvmc_raise_objection
void uvmc_raise_objection (const char* name,
const char* context="",
const char* description="",
unsigned int count=1);
// Function: uvmc_drop_objection
//
// Raise or drop an objection to ending the specified phase on behalf of the
// component at a given context. Raises can be made before the actual phase is
// executing. However, drops that move the objection count to zero must be
// avoided until the phase is actually executing, else the all-dropped
// condition will occur prematurely. Typical usage includes calling
// <uvmc_wait_for_phase>.
// Arguments:
//
// name - The verbosity level. Specify UVM_NONE, UVM_LOW, UVM_MEDIUM,
// UVM_HIGH, or UVM_FULL. Required.
//
// context - The hierarchical path of the component on whose behalf the
// specified objection is raised or dropped. Wildcards or regular
// expressions are not allowed. The context must exactly match an
// existing component's hierarchical name. Default: "" (uvm_top)
//
// description - The reason for raising or dropping the objection. This string
// is passed in all callbacks and printed when objection tracing is
// turned on. Default: ""
//
// count - The number of objections to raise or drop. Default: 1
//
// Examples:
//
// The following routine will force the specified UVM task phase to last at
// minimum number of nanoseconds, assuming SystemC and SystemVerilog are
// operating on the same timescale.
//
//| void set_min_phase_duration(const char* ph_name, sc_time min_time) {
//| uvmc_wait_for_phase(ph_name, UVM_PHASE_STARTED);
//| uvmc_raise_objection(ph_name,"","Forcing minimum run time");
//| wait(min_time);
//| uvmc_drop_objection(ph_name,"","Phase met minimum run time");
//| }
//
// Use directly as a blocking call, or use in non-blocking fashion with
// sc_spawn/sc_bind:
//
//| sc_spawn(sc_bind(&top:set_min_phase_duration, // <--func pointer
//| this,"run",sc_time(100,SC_NS)),"min_run_time");
//------------------------------------------------------------------------------
void uvmc_drop_objection (const char* name,
const char* context="",
const char* description="",
unsigned int count=1);
//------------------------------------------------------------------------------
// Group: Factory
//
// This API provides access to UVM's object and component factory.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Function: uvmc_print_factory
//
// Prints the state of the UVM factory, including registered types, instance
// overrides, and type overrides.
//
// Arguments:
//
// all_types - When all_types is 0, only type and instance overrides are
// displayed. When all_types is 1 (default), all registered
// user-defined types are printed as well, provided they have type
// names associated with them. (Parameterized types usually do not.)
// When all_types is 2, all UVM types (prefixed with uvm_) are
// included in the list of registered types.
//
// Examples:
//
// Print all type and instance overrides in the factory.
//
//| uvmc_print_factory(0);
//
// Print all type and instance overrides, plus all registered user-defined
// types.
//
//| uvmc_print_factory(1);
//
// Print all type and instance overrides, plus all registered types, including
// UVM types.
//
//| uvmc_print_factory(2);
//------------------------------------------------------------------------------
void uvmc_print_factory (int all_types=1);
//------------------------------------------------------------------------------
// Function: uvmc_set_factory_type_override
void uvmc_set_factory_type_override (const char* original_type,
const char* override_type,
bool replace=1);
// Function: uvmc_set_factory_inst_override
//
// Set a type or instance override. Instance overrides take precedence over
// type overrides. All specified types must have been registered with the
// factory.
//
// Arguments:
//
// requested_type - The name of the requested type.
//
// override_type - The name of the override type. Must be an extension of the
// requested_type.
//
// context - The hierarchical path of the component. Multiple components
// can be specified by using glob wildcards (* and ?), e.g.
// "top.env.*.driver". You can also specify a POSIX extended
// regular expression by enclosing the context string in
// forward slashes, e.g. "/a[hp]b/".
//
// replace - If true, replace any existing type override. Default: true
//
// Examples:
//
// The following sets an instance override in the UVM factory. Any component
// whose inst path matches the glob expression "e.*" that requests an object
// of type scoreboard_base (i.e. scoreboard_base:type_id::create) will instead
// get an object of type scoreboard.
//
//| uvmc_set_factory_inst_override("scoreboard_base","scoreboard","e.*");
//
// The following sets a type override in the UVM factory. Any component whose
// hierarchical path matches the glob expression "e.*" that requests an
// object of type producer_base (i.e. producer_base:type_id::create) will
// instead get an object of type producer.
//
//| uvmc_set_factory_type_override("producer_base","producer");
//
// The following sets an override chain. Given any request for an atype, a
// ctype object is returned, except for the component with hierarchical name
// "e.prod", which will get a dtype.
//
//| uvmc_set_factory_type_override("atype","btype");
//| uvmc_set_factory_type_override("btype","ctype");
//| uvmc_set_factory_inst_override("ctype","dtype","e.prod");
//------------------------------------------------------------------------------
void uvmc_set_factory_inst_override (const char* original_type,
const char* override_type,
const char* context);
//------------------------------------------------------------------------------
// Function: uvmc_debug_factory_create
//
// Display detailed information about the object type the UVM factory would
// create given a requested type and context, listing each override that was
// applied to arrive at the result.
//
// Arguments:
//
// requested - The requested type name for a hypothetical call to create.
//
// context - The hierarchical path of the object to be created, which is a
// concatenation of the parent's hierarchical name with the
// name of the object being created. Wildcards or regular
// expressions are not allowed. The context must exactly match
// an existing component's hierarchical name, or can be the
// empty string to specify global context.
//
// Example:
//
// The following example answers the question: If the component at
// hierarchical path ~env.agent1.scoreboard~ requested an object of type
// scoreboard_base, what are all the applicable overrides, and which of
// those were applied to arrive at the result?
//
//| uvmc_debug_factory_create("scoreboard_base","env.agent1.scoreboard");
//------------------------------------------------------------------------------
void uvmc_debug_factory_create (const char* requested_type,
const char* context="");
//------------------------------------------------------------------------------
// Function: uvmc_find_factory_override
//
// Returns the type name of the type that would be created by the factory given
// the requested type and context.
//
// Arguments:
//
// requested - The requested type name for a hypothetical call to create.
//
// context - The hierarchical path of the component that would make the
// request. Wildcards or regular expressions are not allowed.
// The context must exactly match an existing component's
// hierarchical name, or can be the empty string to specify
// global context.
//
// Examples:
//
// The following examples assume all types, A through D, have been registered
// with the UVM factory. Given the following overrides:
//
//| uvmc_set_type_override("B","C");
//| uvmc_set_type_override("A","B");
//| uvmc_set_inst_override("D", "C", "top.env.agent1.*");
//
// The following will display "C":
//
//| $display(uvmc_find_factory_override("A"));
//
// The following will display "D":
//
//| $display(uvmc_find_factory_override("A", "top.env.agent1.driver"));
//
// The returned string can be used in subsequent calls to
// <uvmc_set_factory_type_override> and <uvmc_set_factory_inst_override>.
//------------------------------------------------------------------------------
string uvmc_find_factory_override (const char* requested_type,
const char* context="");
//------------------------------------------------------------------------------
// Group: set_config
//------------------------------------------------------------------------------
//
// Creates or updates a configuration setting for a field at a specified
// hierarchical context.
//
// These functions establish configuration settings, storing them as resource
// entries in the resource database for later lookup by get_config calls. They
// do not directly affect the field values being targeted. As the component
// hierarchy is being constructed during UVM's build phase, components
// spring into existence and establish their context. Once its context is
// known, each component can call get_config to retrieve any configuration
// settings that apply to it.
//
// The context is specified as the concatenation of two arguments, context and
// inst_name, which are separated by a "." if both context and inst_name are
// not empty. Both context and inst_name may be glob style or regular
// expression style expressions.
//
// The name of the configuration parameter is specified by the ~field_name~
// argument.
//
// The semantic of the set methods is different when UVM is in the build phase
// versus any other phase. If a set call is made during the build phase, the
// context determines precedence in the database. A set call from a higher
// level in the hierarchy (e.g. mytop.test1) has precedence over a set call to
// the same field from a lower level (e.g. mytop.test1.env.agent). Set calls
// made at the same level of hierarchy have equal precedence, so each set call
// overwrites the field value from a previous set call.
//
// After the build phase, all set calls have the same precedence regardless of
// their hierarchical context. Each set call overwrites the value of the
// previous call.
//
// Arguments:
//
// type_name - For uvmc_set_config_object only. Specifies the type name of the
// equivalent object to set in SV. UVM Connect will utilize the
// factory to allocate an object of this type and unpack the
// serialized value into it. Parameterized classes are not
// supported.
//
// context - The hierarchical path of the component, or the empty string,
// which specifies uvm_top. Multiple components can be specified
// by using glob wildcards (* and ?), e.g. "top.env.*.driver".
// You can also specify a POSIX extended regular expression by
// enclosing the contxt in forward slashes, e.g. "/a[hp]b/".
// Default: "" (uvm_top)
//
// inst_name - The instance path of the object being configured, relative to
// the specified context(s). Can contain wildcards or be a
// regular expression.
//
// field_name - The name of the configuration parameter. Typically this name
// is the same as or similar to the variable used to hold the
// configured value in the target context(s).
//
// value - The value of the configuration parameter. Integral values
// currently cannot exceed 64 bits. Object values must have a
// uvmc_convert<object_type> specialization defined for it.
// Use of the converter convenience macros is acceptable for
// meeting this requirement.
//
// Examples:
//
// The following example sets the configuration object field at path
// "e.prod.trans" to the tr instance, which is type uvm_tlm_generic_payload.
//
//| uvmc_set_config_object("uvm_tlm_generic_payload","e.prod","","trans", tr);
//
// The next example sets the string property at hierarchical path
// "e.prod.message" to "Hello from SystemC!".
//
//| uvmc_set_config_string ("e.prod", "", "message", "Hello from SystemC!");
//
// The next example sets the integral property at hierarchical path
// "e.prod.start_addr" to hex 0x1234.
//
//| uvmc_set_config_int ("e.prod", "", "start_addr", 0x1234);
//-------------------------- |
----------------------------------------------------
// Function: uvmc_set_config_int
//
// Set an integral configuration value
//
void uvmc_set_config_int (const char* context, const char* inst_name,
const char* field_name, uint64 value);
// Function: uvmc_set_config_string
//
// Set a string configuration value
//
void uvmc_set_config_string (const char* context, const char* inst_name,
const char* field_name, const string& value);
} // extern "C"
namespace uvmc {
// Function: uvmc_set_config_object
//
// Set an object configuration value using a custom converter
//
template <class T, class CVRT>
void uvmc_set_config_object (const char* type_name,
const char* context,
const char* inst_name,
const char* field_name,
T &value,
uvmc_packer *packer=NULL) {
static bits_t bits;
static uvmc_packer def_packer;
if (packer == NULL) {
packer = &def_packer;
//packer->big_endian = 0;
}
wait_sv_ready();
packer->init_pack(bits);
CVRT::do_pack(value,packer);
svSetScope(uvmc_pkg_scope);
UVMC_set_config_object(type_name,context,inst_name,field_name,bits);
}
// Function: uvmc_set_config_object
//
// Set an object configuration value using the default converter
//
template <class T>
void uvmc_set_config_object (const char* type_name,
const char* context,
const char* inst_name,
const char* field_name,
T &value,
uvmc_packer *packer=NULL) {
static bits_t bits[UVMC_MAX_WORDS];
static uvmc_packer def_packer;
if (packer == NULL) {
packer = &def_packer;
//packer->big_endian = 0;
}
wait_sv_ready();
packer->init_pack(bits);
uvmc_converter<T>::do_pack(value,*packer);
svSetScope(uvmc_pkg_scope);
UVMC_set_config_object(type_name,context,inst_name,field_name,bits);
}
} // namespace uvmc
extern "C" {
//------------------------------------------------------------------------------
// Group: get_config
//------------------------------------------------------------------------------
//
// Gets a configuration field ~value~ at a specified hierarchical ~context~.
// Returns true if successful, false if a configuration setting could not be
// found at the given ~context~. If false, the ~value~ reference is unmodified.
//
// The ~context~ specifies the starting point for a search for a configuration
// setting for the field made at that level of hierarchy or higher. The
// ~inst_name~ is an explicit instance name relative to context and may be an
// empty string if ~context~ is the full context that the configuration
// setting applies to.
//
// The ~context~ and ~inst_name~ strings must be simple strings--no wildcards
// or regular expressions.
//
// See the section on <set_config> for the semantics
// that apply when setting configuration.
//
// Arguments:
//
// type_name - For <uvmc_get_config_object> only. Specifies the type name
// of the equivalent object to retrieve in SV. UVM Connect
// will check that the object retrieved from the configuration
// database matches this type name. If a match, the object is
// serialized (packed) and returned across the language
// boundary. Once on this side, the object data is unpacked
// into the object passed by reference via the value argument.
// Parameterized classes are not supported.
//
// context - The hierarchical path of the component on whose behalf the
// specified configuration is being retrieved. Wildcards or
// regular expressions are not allowed. The context must
// exactly match an existing component's hierarchical name,
// or be the empty string, which specifies uvm_top.
//
// inst_name - The instance path of the object being configured, relative
// to the specified context(s).
//
// field_name - The name of the configuration parameter. Typically this name
// is the same as or similar to the variable used to hold the
// configured value in the target context(s).
//
// value - The value of the configuration parameter. Integral values
// currently cannot exceed 64 bits. Object values must have a
// uvmc_convert<object_type> specialization defined for it. Use
// of the converter convenience macros is acceptable for meeting
// this requirement. The equivalent class in SV must be based
// on uvm_object and registered with the UVM factory, i.e.
// contain a `uvm_object_utils macro invocation.
//
// Examples:
//
// The following example retrieves the uvm_tlm_generic_payload configuration
// property at hierarchical path "e.prod.trans" into tr2.
//
//| uvmc_get_config_object("uvm_tlm_generic_payload","e","prod","trans", tr2);
//
// The context specification is split between the context and inst_name
// arguments. Unlike setting configuration, there is no semantic difference
// between the context and inst_name properties. When getting configuration,
// the full context is always the concatenation of the context, ".", and
// inst_name. The transaction tr2 will effectively become a copy of the
// object used to set the configuration property.
//
// The next example retrieves the string property at hierarchical path
// "e.prod.message" into local variable str.
//
//| uvmc_get_config_string ("e", "prod", "message", str);
//
// The following example retrieves the integral property at hierarchical path
// "e.prod.start_addr" into the local variable, saddr.
//
//| uvmc_get_config_int ("e.prod", "", "start_addr", saddr);
//------------------------------------------------------------------------------
// Function: uvmc_get_config_int
//
// Set an integral configuration value.
//
bool uvmc_get_config_int (const char* context, const char* inst_name,
const char* field_name, uint64 &value);
// Function: uvmc_get_config_string
//
// Set a string configuration value.
//
bool uvmc_get_config_string (const char* context, const char* inst_name,
const char* field_name, string &value);
} // extern "C"
namespace uvmc {
// Function: uvmc_get_config_object
//
// Set an object configuration value using a custom converter
//
template <class T, class CVRT>
bool uvmc_get_config_object (const char* type_name,
const char* context,
const char* inst_name,
const char* field_name,
T &value,
uvmc_packer *packer=NULL) {
static bits_t bits;
static uvmc_packer def_packer;
if (packer == NULL) {
packer = &def_packer;
//packer->big_endian = 0;
}
wait_sv_ready();
svSetScope(uvmc_pkg_scope);
if (UVMC_get_config_object(type_name,context,inst_name,field_name,bits)) {
packer->init_unpack(bits);
CVRT::do_unpack(value,packer);
return 1;
}
return 0;
}
// Function: uvmc_get_config_object
//
// Set an object configuration value using the default converter
//
template <class T>
bool uvmc_get_config_object (const char* type_name,
const char* context,
const char* inst_name,
const char* field_name,
T &value,
uvmc_packer *packer=NULL) {
static bits_t bits[UVMC_MAX_WORDS];
static uvmc_packer def_packer;
if (packer == NULL) {
packer = &def_packer;
//packer->big_endian = 0;
}
wait_sv_ready();
svSetScope(uvmc_pkg_scope);
if (UVMC_get_config_object(type_name,context,inst_name,field_name,bits)) {
packer->init_unpack(bits);
uvmc_converter<T>::do_unpack(value,*packer);
return 1;
}
return 0;
}
} // namespace uvmc
#endif // UVMC_COMMANDS_H
|
#ifndef TESTBENCH_VBASE_H
#define TESTBENCH_VBASE_H
#include <systemc.h>
#include "verilated.h"
#include "verilated_vcd_sc.h"
#define verilator_trace_enable(vcd_filename, dut) \
if (waves_enabled()) \
{ \
Verilated::traceEverOn(true); \
VerilatedVcdC *v_vcd = new VerilatedVcdC; \
sc_core::sc_time delay_us; \
if (waves_delayed(delay_us)) \
dut->trace_enable (v_vcd, delay_us); \
else \
dut->trace_enable (v_vcd); \
v_vcd->open (vcd_filename); \
this->m_verilate_vcd = v_vcd; \
}
//-----------------------------------------------------------------
// Module
//-----------------------------------------------------------------
class testbench_vbase: public sc_module
{
public:
sc_in <bool> clk;
sc_in <bool> rst;
virtual void set_testcase(int tc) { }
virtual void set_delays(bool en) { }
virtual void set_iterations(int iterations) { }
virtual void set_argcv(int argc, char* argv[]) { }
virtual void process(void) { while (1) wait(); }
virtual void monitor(void) { while (1) wait(); }
SC_HAS_PROCESS(testbench_vbase);
testbench_vbase(sc_module_name name): sc_module(name)
{
SC_CTHREAD(process, clk);
SC_CTHREAD(monitor, clk);
}
virtual void add_trace(sc_trace_file * fp, std::string prefix) { }
virtual void abort(void)
{
cout << "TB: Aborted at " << sc_time_stamp() << endl;
if (m_verilate_vcd)
{
m_verilate_vcd->flush();
m_verilate_vcd->close();
m_verilate_vcd = NULL;
}
}
bool waves_enabled(void)
{
char *s = getenv("ENABLE_WAVES");
if (s && !strcmp(s, "no"))
return false;
else
return true;
}
bool waves_delayed(sc_core::sc_time &delay)
{
char *s = getenv("WAVES_DELAY_US");
if (s != NULL)
{
uint32_t us = strtoul(s, NULL, 0);
printf("WAVES: Delay start until %duS\n", us);
delay = sc_core::sc_time(us, SC_US);
return true;
}
else
return false;
}
std::string getenv_str(std::string name, std::string defval)
{
char *s = getenv(name.c_str());
if (!s || (s && !strcmp(s, "")))
return defval;
else
return std::string(s);
}
protected:
VerilatedVcdC *m_verilate_vcd;
};
#endif |
//
// Copyright 2022 Sergey Khabarov, [email protected]
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
#pragma once
#include <systemc.h>
#include "../river_cfg.h"
#include "icache_lru.h"
#include "dcache_lru.h"
#include "pma.h"
#include "pmp.h"
#include "../core/queue.h"
namespace debugger {
SC_MODULE(CacheTop) {
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
// Control path:
sc_in<bool> i_req_ctrl_valid; // Control request from CPU Core is valid
sc_in<sc_uint<RISCV_ARCH>> i_req_ctrl_addr; // Control request address
sc_out<bool> o_req_ctrl_ready; // Control request from CPU Core is accepted
sc_out<bool> o_resp_ctrl_valid; // ICache response is valid and can be accepted
sc_out<sc_uint<RISCV_ARCH>> o_resp_ctrl_addr; // ICache response address
sc_out<sc_uint<64>> o_resp_ctrl_data; // ICache read data
sc_out<bool> o_resp_ctrl_load_fault; // Bus response ERRSLV or ERRDEC on read
sc_in<bool> i_resp_ctrl_ready; // CPU Core is ready to accept ICache response
// Data path:
sc_in<bool> i_req_data_valid; // Data path request from CPU Core is valid
sc_in<sc_uint<MemopType_Total>> i_req_data_type; // Data write memopy operation flag
sc_in<sc_uint<RISCV_ARCH>> i_req_data_addr; // Memory operation address
sc_in<sc_uint<64>> i_req_data_wdata; // Memory operation write value
sc_in<sc_uint<8>> i_req_data_wstrb; // 8-bytes aligned strob
sc_in<sc_uint<2>> i_req_data_size;
sc_out<bool> o_req_data_ready; // Memory operation request accepted by DCache
sc_out<bool> o_resp_data_valid; // DCache response is ready
sc_out<sc_uint<RISCV_ARCH>> o_resp_data_addr; // DCache response address
sc_out<sc_uint<64>> o_resp_data_data; // DCache response read data
sc_out<bool> o_resp_data_load_fault; // Bus response ERRSLV or ERRDEC on read
sc_out<bool> o_resp_data_store_fault; // Bus response ERRSLV or ERRDEC on write
sc_in<bool> i_resp_data_ready; // CPU Core is ready to accept DCache repsonse
// Memory interface:
sc_in<bool> i_req_mem_ready; // System Bus is ready to accept memory operation request
sc_out<bool> o_req_mem_path; // 1=ctrl; 0=data path
sc_out<bool> o_req_mem_valid; // AXI memory request is valid
sc_out<sc_uint<REQ_MEM_TYPE_BITS>> o_req_mem_type; // AXI memory request type
sc_out<sc_uint<3>> o_req_mem_size; // request size: 0=1 B;...; 7=128 B
sc_out<sc_uint<CFG_CPU_ADDR_BITS>> o_req_mem_addr; // AXI memory request address
sc_out<sc_uint<L1CACHE_BYTES_PER_LINE>> o_req_mem_strob;// Writing strob. 1 bit per Byte (uncached only)
sc_out<sc_biguint<L1CACHE_LINE_BITS>> o_req_mem_data; // Writing data
sc_in<bool> i_resp_mem_valid; // AXI response is valid
sc_in<bool> i_resp_mem_path; // 0=ctrl; 1=data path
sc_in<sc_biguint<L1CACHE_LINE_BITS>> i_resp_mem_data; // Read data
sc_in<bool> i_resp_mem_load_fault; // data load error
sc_in<bool> i_resp_mem_store_fault; // data store error
// PMP interface:
sc_in<bool> i_pmp_ena; // PMP is active in S or U modes or if L/MPRV bit is set in M-mode
sc_in<bool> i_pmp_we; // write enable into PMP
sc_in<sc_uint<CFG_PMP_TBL_WIDTH>> i_pmp_region; // selected PMP region
sc_in<sc_uint<RISCV_ARCH>> i_pmp_start_addr; // PMP region start address
sc_in<sc_uint<RISCV_ARCH>> i_pmp_end_addr; // PMP region end address (inclusive)
sc_in<sc_uint<CFG_PMP_FL_TOTAL>> i_pmp_flags; // {ena, lock, r, w, x}
// $D Snoop interface:
sc_in<bool> i_req_snoop_valid;
sc_in<sc_uint<SNOOP_REQ_TYPE_BITS>> i_req_snoop_type;
sc_out<bool> o_req_snoop_ready;
sc_in<sc_uint<CFG_CPU_ADDR_BITS>> i_req_snoop_addr;
sc_in<bool> i_resp_snoop_ready;
sc_out<bool> o_resp_snoop_valid;
sc_out<sc_biguint<L1CACHE_LINE_BITS>> o_resp_snoop_data;
sc_out<sc_uint<DTAG_FL_TOTAL>> o_resp_snoop_flags;
// Debug signals:
sc_in<bool> i_flushi_valid; // address to clear icache is valid
sc_in<sc_uint<RISCV_ARCH>> i_flushi_addr; // clear ICache address from debug interface
sc_in<bool> i_flushd_valid;
sc_in<sc_uint<RISCV_ARCH>> i_flushd_addr;
sc_out<bool> o_flushd_end;
void comb();
SC_HAS_PROCESS(CacheTop);
CacheTop(sc_module_name name,
bool async_reset,
bool coherence_ena);
virtual ~CacheTop();
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
bool async_reset_;
bool coherence_ena_;
static const int DATA_PATH = 0;
static const int CTRL_PATH = 1;
static const int QUEUE_WIDTH = (CFG_CPU_ADDR_BITS // o_req_mem_addr
+ REQ_MEM_TYPE_BITS // o_req_mem_type
+ 3 // o_req_mem_size
+ 1 // i_resp_mem_path
);
struct CacheOutputType {
sc_signal<bool> req_mem_valid;
sc_signal<sc_uint<REQ_MEM_TYPE_BITS>> req_mem_type;
sc_signal<sc_uint<3>> req_mem_size;
sc_signal<sc_uint<CFG_CPU_ADDR_BITS>> req_mem_addr;
sc_signal<sc_uint<L1CACHE_BYTES_PER_LINE>> req_mem_strob;
sc_signal<sc_biguint<L1CACHE_LINE_BITS>> req_mem_wdata;
sc_signal<sc_uint<CFG_CPU_ADDR_BITS>> mpu_addr;
sc_signal<sc_uint<CFG_CPU_ADDR_BITS>> resp_addr;
};
sc_signal<sc_uint<CFG_CPU_ADDR_BITS>> wb_i_req_ctrl_addr;
sc_signal<sc_uint<CFG_CPU_ADDR_BITS>> wb_i_req_data_addr;
sc_signal<sc_uint<CFG_CPU_ADDR_BITS>> wb_i_flushi_addr;
sc_signal<sc_uint<CFG_CPU_ADDR_BITS>> wb_i_flushd_addr;
CacheOutputType i;
CacheOutputType d;
// Memory Control interface:
sc_signal<bool> w_ctrl_resp_mem_data_valid;
sc_signal<sc_biguint<L1CACHE_LINE_BITS>> wb_ctrl_resp_mem_data;
sc_signal<bool> w_ctrl_resp_mem_load_fault;
sc_signal<bool> w_ctrl_req_ready;
// Memory Data interface:
sc_signal<bool> w_data_resp_mem_data_valid;
sc_signal<sc_biguint<L1CACHE_LINE_BITS>> wb_data_resp_mem_data;
sc_signal<bool> w_data_resp_mem_load_fault;
sc_signal<bool> w_data_req_ready;
sc_signal<bool> w_pma_icached;
sc_signal<bool> w_pma_dcached;
sc_signal<bool> w_pmp_r;
sc_signal<bool> w_pmp_w;
sc_signal<bool> w_pmp_x;
// Queue interface
sc_signal<bool> queue_re_i;
sc_signal<bool> queue_we_i;
sc_signal<sc_biguint<QUEUE_WIDTH>> queue_wdata_i;
sc_signal<sc_biguint<QUEUE_WIDTH>> queue_rdata_o;
sc_signal<bool> queue_full_o;
sc_signal<bool> queue_nempty_o;
ICacheLru *i1;
DCacheLru *d0;
PMA *pma0;
PMP *pmp0;
Queue<2, QUEUE_WIDTH> *queue0;
};
} // namespace debugger
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#pragma once
#include <systemc.h>
#include <unordered_map>
#include "../../UTIL/debug_util.h"
#define RAM_SIZE 6000 //0xFFFF FFFF -> max size
SC_MODULE(RAM)
{
sc_in_clk CLK;
sc_in<bool> RESET_N;
sc_in<sc_uint<32>> ADR_I;
sc_in<sc_uint<32>> DAT_I;
sc_in<bool> VALID_I;
sc_in<bool> WE_I;
sc_in<sc_uint<2>> MEM_SIZE;
sc_out<sc_uint<32>> DAT_O;
//signals
sc_signal<sc_uint<4>> current_state;
sc_signal<sc_uint<4>> future_state;
std::unordered_map<int,int>* RAM_REGISTERS;
void init_mem(std::unordered_map<int,int>*);
void reponse();
void trace(sc_trace_file*);
SC_CTOR(RAM)
{
SC_METHOD(reponse);
sensitive << CLK.neg();
}
};
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//
// Copyright 2022 Sergey Khabarov, [email protected]
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
#pragma once
#include <systemc.h>
namespace debugger {
SC_MODULE(vip_spi_transmitter) {
public:
sc_in<bool> i_nrst;
sc_in<bool> i_clk;
sc_in<bool> i_csn;
sc_in<bool> i_sclk;
sc_in<bool> i_mosi;
sc_out<bool> o_miso;
sc_out<bool> o_req_valid;
sc_out<bool> o_req_write;
sc_out<sc_uint<32>> o_req_addr;
sc_out<sc_uint<32>> o_req_wdata;
sc_in<bool> i_req_ready;
sc_in<bool> i_resp_valid;
sc_in<sc_uint<32>> i_resp_rdata;
sc_out<bool> o_resp_ready;
void comb();
void registers();
SC_HAS_PROCESS(vip_spi_transmitter);
vip_spi_transmitter(sc_module_name name,
bool async_reset,
int scaler);
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
bool async_reset_;
int scaler_;
int scaler_max;
int scaler_mid;
static const uint8_t state_cmd = 0;
static const uint8_t state_addr = 1;
static const uint8_t state_data = 2;
struct vip_spi_transmitter_registers {
sc_signal<sc_uint<2>> state;
sc_signal<bool> sclk;
sc_signal<sc_uint<32>> rxshift;
sc_signal<sc_uint<32>> txshift;
sc_signal<sc_uint<4>> bitcnt;
sc_signal<sc_uint<3>> bytecnt;
sc_signal<bool> byterdy;
sc_signal<bool> req_valid;
sc_signal<bool> req_write;
sc_signal<sc_uint<32>> req_addr;
sc_signal<sc_uint<32>> req_wdata;
} v, r;
void vip_spi_transmitter_r_reset(vip_spi_transmitter_registers &iv) {
iv.state = state_cmd;
iv.sclk = 0;
iv.rxshift = ~0ull;
iv.txshift = ~0ull;
iv.bitcnt = 0;
iv.bytecnt = 0;
iv.byterdy = 0;
iv.req_valid = 0;
iv.req_write = 0;
iv.req_addr = 0;
iv.req_wdata = 0;
}
};
} // namespace debugger
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