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/***************************************************************************\
*
*
* ___ ___ ___ ___
* / /\ / /\ / /\ / /\
* / /:/ / /::\ / /::\ / /::\
* / /:/ / /:/\:\ / /:/\:\ / /:/\:\
* / /:/ / /:/~/:/ / /:/~/::\ / /:/~/:/
* / /::\ /__/:/ /:/___ /__/:/ /:/\:\ /__/:/ /:/
* /__/:/\:\ \ \:\/:::::/ \ \:\/:/__\/ \ \:\/:/
* \__\/ \:\ \ \::/~~~~ \ \::/ \ \::/
* \ \:\ \ \:\ \ \:\ \ \:\
* \ \ \ \ \:\ \ \:\ \ \:\
* \__\/ \__\/ \__\/ \__\/
*
*
*
*
* This file is part of TRAP.
*
* TRAP is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this program; if not, write to the
* Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
* or see <http://www.gnu.org/licenses/>.
*
*
*
* (c) Luca Fossati, [email protected], [email protected]
*
\***************************************************************************/
#ifndef PROFINFO_HPP
#define PROFINFO_HPP
#include <string>
#include <systemc.h>
namespace trap{
///Represents all the profiling data which can be
///associated with a single assembly instruction
struct ProfInstruction{
///Name of the assembly instruction (MOV, ADD ...)
std::string name;
///Number of times this instruction is called
unsigned long long numCalls;
///Total number of instructions executed
static unsigned long long numTotalCalls;
///Total time spent in executing the instruction
sc_time time;
///dump these information to a string, in the command separated values (CVS) format
std::string printCsv();
///Prints the description of the informations which describe an instruction, in the command separated values (CVS) format
static std::string printCsvHeader();
///Prints the summary of all the executed instructions, in the command separated values (CVS) format
static std::string printCsvSummary();
///Empty constructor, performs the initialization of the statistics
ProfInstruction();
};
///Represents all the profiling data which can be
///associated with a single function
struct ProfFunction{
///Address of the function
unsigned int address;
///Name of the function
std::string name;
///Number of times this function is called
unsigned long long numCalls;
///Total number of function calls
static unsigned long long numTotalCalls;
///The number of assembly instructions executed in total inside the function
unsigned long long totalNumInstr;
///The number of assembly instructions executed exclusively inside the function
unsigned long long exclNumInstr;
///Total time spent in the function
sc_time totalTime;
///Time spent exclusively in the function
sc_time exclTime;
///Used to coorectly keep track of the increment of the time, instruction count, etc.
///in recursive functions
bool alreadyExamined;
///dump these information to a string, in the command separated values (CVS) format
std::string printCsv();
///Prints the description of the informations which describe a function, in the command separated values (CVS) format
static std::string printCsvHeader();
///Empty constructor, performs the initialization of the statistics
ProfFunction();
};
}
#endif
|
#ifndef RISCV_TOP_H
#define RISCV_TOP_H
#include <systemc.h>
#include "axi4.h"
#include "axi4.h"
class Vriscv_top;
class VerilatedVcdC;
//-------------------------------------------------------------
// riscv_top: RTL wrapper class
//-------------------------------------------------------------
class riscv_top: public sc_module
{
public:
sc_in <bool> clk_in;
sc_in <bool> rst_in;
sc_in <bool> intr_in;
sc_in <uint32_t> reset_vector_in;
sc_in <axi4_slave> axi_i_in;
sc_out <axi4_master> axi_i_out;
sc_in <axi4_slave> axi_d_in;
sc_out <axi4_master> axi_d_out;
//-------------------------------------------------------------
// Constructor
//-------------------------------------------------------------
SC_HAS_PROCESS(riscv_top);
riscv_top(sc_module_name name);
//-------------------------------------------------------------
// Trace
//-------------------------------------------------------------
virtual void add_trace(sc_trace_file *vcd, std::string prefix)
{
#undef TRACE_SIGNAL
#define TRACE_SIGNAL(s) sc_trace(vcd,s,prefix + #s)
TRACE_SIGNAL(clk_in);
TRACE_SIGNAL(rst_in);
TRACE_SIGNAL(intr_in);
TRACE_SIGNAL(reset_vector_in);
TRACE_SIGNAL(axi_i_in);
TRACE_SIGNAL(axi_i_out);
TRACE_SIGNAL(axi_d_in);
TRACE_SIGNAL(axi_d_out);
#undef TRACE_SIGNAL
}
void async_outputs(void);
void trace_rtl(void);
void trace_enable(VerilatedVcdC *p);
void trace_enable(VerilatedVcdC *p, sc_core::sc_time start_time);
//-------------------------------------------------------------
// Signals
//-------------------------------------------------------------
private:
sc_signal <bool> m_clk_in;
sc_signal <bool> m_rst_in;
sc_signal <bool> m_axi_i_awready_in;
sc_signal <bool> m_axi_i_wready_in;
sc_signal <bool> m_axi_i_bvalid_in;
sc_signal <uint32_t> m_axi_i_bresp_in;
sc_signal <uint32_t> m_axi_i_bid_in;
sc_signal <bool> m_axi_i_arready_in;
sc_signal <bool> m_axi_i_rvalid_in;
sc_signal <uint32_t> m_axi_i_rdata_in;
sc_signal <uint32_t> m_axi_i_rresp_in;
sc_signal <uint32_t> m_axi_i_rid_in;
sc_signal <bool> m_axi_i_rlast_in;
sc_signal <bool> m_axi_d_awready_in;
sc_signal <bool> m_axi_d_wready_in;
sc_signal <bool> m_axi_d_bvalid_in;
sc_signal <uint32_t> m_axi_d_bresp_in;
sc_signal <uint32_t> m_axi_d_bid_in;
sc_signal <bool> m_axi_d_arready_in;
sc_signal <bool> m_axi_d_rvalid_in;
sc_signal <uint32_t> m_axi_d_rdata_in;
sc_signal <uint32_t> m_axi_d_rresp_in;
sc_signal <uint32_t> m_axi_d_rid_in;
sc_signal <bool> m_axi_d_rlast_in;
sc_signal <bool> m_intr_in;
sc_signal <uint32_t> m_reset_vector_in;
sc_signal <bool> m_axi_i_awvalid_out;
sc_signal <uint32_t> m_axi_i_awaddr_out;
sc_signal <uint32_t> m_axi_i_awid_out;
sc_signal <uint32_t> m_axi_i_awlen_out;
sc_signal <uint32_t> m_axi_i_awburst_out;
sc_signal <bool> m_axi_i_wvalid_out;
sc_signal <uint32_t> m_axi_i_wdata_out;
sc_signal <uint32_t> m_axi_i_wstrb_out;
sc_signal <bool> m_axi_i_wlast_out;
sc_signal <bool> m_axi_i_bready_out;
sc_signal <bool> m_axi_i_arvalid_out;
sc_signal <uint32_t> m_axi_i_araddr_out;
sc_signal <uint32_t> m_axi_i_arid_out;
sc_signal <uint32_t> m_axi_i_arlen_out;
sc_signal <uint32_t> m_axi_i_arburst_out;
sc_signal <bool> m_axi_i_rready_out;
sc_signal <bool> m_axi_d_awvalid_out;
sc_signal <uint32_t> m_axi_d_awaddr_out;
sc_signal <uint32_t> m_axi_d_awid_out;
sc_signal <uint32_t> m_axi_d_awlen_out;
sc_signal <uint32_t> m_axi_d_awburst_out;
sc_signal <bool> m_axi_d_wvalid_out;
sc_signal <uint32_t> m_axi_d_wdata_out;
sc_signal <uint32_t> m_axi_d_wstrb_out;
sc_signal <bool> m_axi_d_wlast_out;
sc_signal <bool> m_axi_d_bready_out;
sc_signal <bool> m_axi_d_arvalid_out;
sc_signal <uint32_t> m_axi_d_araddr_out;
sc_signal <uint32_t> m_axi_d_arid_out;
sc_signal <uint32_t> m_axi_d_arlen_out;
sc_signal <uint32_t> m_axi_d_arburst_out;
sc_signal <bool> m_axi_d_rready_out;
sc_signal<bool> m_tck;
sc_signal<bool> m_tms;
sc_signal<bool> m_tdi;
sc_signal<bool> m_tdo;
public:
Vriscv_top *m_rtl;
#if VM_TRACE
VerilatedVcdC * m_vcd;
bool m_delay_waves;
sc_core::sc_time m_waves_start;
#endif
};
#endif
|
#include <memory>
#include <systemc.h>
#include "Vtop.h"
#include "bfm.h"
int sc_main(int argc, char* argv[]) {
if (false && argc && argv) {}
Verilated::debug(0);
Verilated::randReset(2);
Verilated::commandArgs(argc, argv);
ios::sync_with_stdio();
sc_clock clk{"clk", 10, SC_NS, 0.5, 5, SC_NS, true};
sc_signal<bool> reset;
sc_signal<bool> cs;
sc_signal<bool> rw;
sc_signal<uint32_t> addr;
sc_signal<uint32_t> data_in;
sc_signal<bool> ready;
sc_signal<uint32_t> data_out;
const std::unique_ptr<Vtop> top{new Vtop{"top"}};
top->clk(clk);
top->reset(reset);
top->cs(cs);
top->rw(rw);
top->addr(addr);
top->data_in(data_in);
top->ready(ready);
top->data_out(data_out);
const std::unique_ptr<bfm> u_bfm{new bfm("bfm")};
u_bfm->clk(clk);
u_bfm->reset(reset);
u_bfm->cs(cs);
u_bfm->rw(rw);
u_bfm->addr(addr);
u_bfm->data_in(data_out);
u_bfm->ready(ready);
u_bfm->data_out(data_in);
sc_start();
top->final();
cout << "done, time = " << sc_time_stamp() << endl;
return 0;
}
#ifdef VL_USER_STOP
void vl_stop(const char *filename, int linenum, const char *hier) VL_MT_UNSAFE
{
sc_stop();
cout << "call vl_stop" << endl;
}
#endif
|
/*
* Created on: 24. OCT. 2019
* Author: Jonathan Horsted Schougaard
*/
#define SC_INCLUDE_FX
#include "hwcore/hf/helperlib.h"
#include "hwcore/pipes/data_types.h"
#include <systemc.h>
#ifndef __tag
#warning __tag not defined!!!
#undef _sc_stream_stitching
#else
#define _sc_stream_stitching JOIN(_sc_stream_stitching, __tag)
#endif
template <int W> SC_MODULE(_sc_stream_stitching) {
typedef typename hwcore::pipes::SC_DATA_STREAM_T_trait<1 * W>::interface_T din_T;
typedef typename hwcore::pipes::SC_DATA_STREAM_T_trait<1 * W>::interface_T dout_T;
sc_in<bool> clk, reset;
sc_fifo_in<din_T> din_buf;
sc_fifo_in<din_T> din;
sc_fifo_out<dout_T> dout;
sc_fifo_in<sc_uint<16> > ctrl_depth;
sc_fifo_in<sc_uint<16> > ctrl_buf_depth;
SC_CTOR(_sc_stream_stitching) {
SC_CTHREAD(thread, clk.pos());
reset_signal_is(reset, true);
}
void thread() {
din_T tmp_in;
while (true) {
sc_uint<16> depth = ctrl_depth.read();
sc_uint<16> buf_depth = ctrl_buf_depth.read();
sc_uint<16> ptr = 0;
bool last = false;
do {
hls_pipeline(1);
if (ptr < buf_depth) {
tmp_in = din_buf.read();
tmp_in.tlast = 0;
} else {
tmp_in = din.read();
last = (tmp_in.tlast == 1);
}
dout.write(tmp_in);
ptr = (ptr + 1 >= depth ? sc_uint<16>(0) : sc_uint<16>(ptr + 1));
} while (!last);
}
}
};
namespace hwcore {
namespace pipes {
#ifndef __tag
template <int W> using sc_stream_stitching = _sc_stream_stitching<W>;
#else
namespace __tag {
template <int W> using sc_stream_stitching = _sc_stream_stitching<W>;
} // namespace __tag
#endif
} // namespace pipes
} // namespace hwcore
|
#ifndef IPS_FILTER_TLM_HPP
#define IPS_FILTER_TLM_HPP
#include <systemc.h>
using namespace sc_core;
using namespace sc_dt;
using namespace std;
#include "ips_filter_lt_model.hpp"
#include "../src/img_target.cpp"
#include "important_defines.hpp"
//Extended Unification TLM
struct ips_filter_tlm : public Filter<IPS_IN_TYPE_TB, IPS_OUT_TYPE_TB, IPS_FILTER_KERNEL_SIZE>, public img_target
{
SC_CTOR(ips_filter_tlm): Filter<IPS_IN_TYPE_TB, IPS_OUT_TYPE_TB, IPS_FILTER_KERNEL_SIZE>(Filter<IPS_IN_TYPE_TB, IPS_OUT_TYPE_TB, IPS_FILTER_KERNEL_SIZE>::name()), img_target(img_target::name()) {
set_mem_attributes(IMG_FILTER_KERNEL_ADDRESS_LO, IMG_FILTER_KERNEL_SIZE+IMG_FILTER_OUTPUT_SIZE);
}
//Override do_when_transaction functions
virtual void do_when_read_transaction(unsigned char*& data, unsigned int data_length, sc_dt::uint64 address);
virtual void do_when_write_transaction(unsigned char*& data, unsigned int data_length, sc_dt::uint64 address);
IPS_IN_TYPE_TB img_window[IPS_FILTER_KERNEL_SIZE * IPS_FILTER_KERNEL_SIZE];
IPS_OUT_TYPE_TB img_result;
};
#endif // IPS_FILTER_TLM_HPP
|
/*******************************************************************************
* i2c.h -- Copyright 2020 (c) Glenn Ramalho - RFIDo Design
*******************************************************************************
* Description:
* Models a single ESP32 I2C
*******************************************************************************
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
#ifndef _I2C_H
#define _I2C_H
#include <systemc.h>
SC_MODULE(i2c) {
public:
sc_out<bool> scl_en_o {"scl_en_o"};
sc_out<bool> sda_en_o {"sda_en_o"};
sc_in<bool> scl_i {"scl_i"};
sc_in<bool> sda_i {"sda_i"};
sc_fifo<unsigned char> to {"to", 32*8};
sc_fifo<unsigned char> from {"from", 32*8};
sc_signal<unsigned char> snd {"snd"};
enum {IDLE, DEVID, READING, WRITING} state;
void transfer_th();
void trace(sc_trace_file *tf);
// Constructor
SC_CTOR(i2c) {
SC_THREAD(transfer_th);
}
};
extern i2c *i2c0ptr;
extern i2c *i2c1ptr;
#endif
|
/*******************************************************************************
* gpio_mf.h -- Copyright 2019 (c) Glenn Ramalho - RFIDo Design
*******************************************************************************
* Description:
* Implements a SystemC model of a generic multi-function GPIO.
*******************************************************************************
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
#ifndef _GPIO_MF_H
#define _GPIO_MF_H
#include <systemc.h>
#include "gpio_simple.h"
class gpio_mf : public gpio {
public:
/* We inherit the main i/o pin and add the function pins. */
sc_port< sc_signal_in_if<bool>,0 > fin {"fin"};
sc_port< sc_signal_in_if<bool>,0 > fen {"fen"};
sc_port< sc_signal_out_if<bool>,0 > fout {"fout"};
/* Multifunction specific tasks */
virtual void set_function(gpio_function_t newfunction);
virtual gpio_function_t get_function();
virtual void set_val(bool newval);
/* Threads */
sc_event updatefunc; /* Triggers a function change. */
sc_event updatereturn; /* Triggers a feedback drive event. */
void drive_func(); /* Updates the function drive. */
void drive_return(); /* Updates feedback pins to functions */
/* Sets initial drive condition. */
gpio_mf(sc_module_name name, int optargs, int initial,
gpio_function_t initialfunc = GPIOMF_GPIO):
gpio(name, optargs, initial) {
function = initialfunc;
SC_THREAD(drive_return);
sensitive << pin << updatereturn;
/* This one has no sensitivity list as it varies according to the
* selected function.
*/
SC_THREAD(drive_func);
}
SC_HAS_PROCESS(gpio_mf);
virtual gpio_type_t get_type() const {return GPIO_TYPE_MF; }
protected:
gpio_function_t function; /* Indicates internal selected function */
bool pinval; /* Indicates intended drive value for pin */
};
#endif
|
//
// Copyright 2022 Sergey Khabarov, [email protected]
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
#pragma once
#include <systemc.h>
#include "../ambalib/types_amba.h"
#include "../ambalib/types_pnp.h"
#include "river_cfg.h"
#include "types_river.h"
#include "dmi/dmidebug.h"
#include "dmi/ic_dport.h"
#include "ic_axi4_to_l1.h"
#include "river_amba.h"
#include "dummycpu.h"
#include "l2cache/l2_top.h"
#include "l2cache/l2dummy.h"
#include "l2cache/l2serdes.h"
namespace debugger {
SC_MODULE(Workgroup) {
public:
sc_in<bool> i_cores_nrst; // System reset without DMI inteface
sc_in<bool> i_dmi_nrst; // Debug interface reset
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_trst;
sc_in<bool> i_tck;
sc_in<bool> i_tms;
sc_in<bool> i_tdi;
sc_out<bool> o_tdo;
sc_in<sc_uint<CFG_CPU_MAX>> i_msip;
sc_in<sc_uint<CFG_CPU_MAX>> i_mtip;
sc_in<sc_uint<CFG_CPU_MAX>> i_meip;
sc_in<sc_uint<CFG_CPU_MAX>> i_seip;
sc_in<sc_uint<64>> i_mtimer; // Read-only shadow value of memory-mapped mtimer register (see CLINT).
// coherent port:
sc_in<axi4_master_out_type> i_acpo;
sc_out<axi4_master_in_type> o_acpi;
// System bus port
sc_out<dev_config_type> o_xmst_cfg; // Workgroup master interface descriptor
sc_in<axi4_master_in_type> i_msti;
sc_out<axi4_master_out_type> o_msto;
// APB debug access:
sc_in<mapinfo_type> i_dmi_mapinfo; // DMI APB itnerface mapping information
sc_out<dev_config_type> o_dmi_cfg; // DMI device descriptor
sc_in<apb_in_type> i_dmi_apbi;
sc_out<apb_out_type> o_dmi_apbo;
sc_out<bool> o_dmreset; // reset everything except DMI debug interface
void comb();
SC_HAS_PROCESS(Workgroup);
Workgroup(sc_module_name name,
bool async_reset,
uint32_t cpu_num,
uint32_t l2cache_ena);
virtual ~Workgroup();
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
bool async_reset_;
uint32_t cpu_num_;
uint32_t l2cache_ena_;
bool coherence_ena;
static const uint32_t ACP_SLOT_IDX = CFG_CPU_MAX;
axi4_l1_out_vector coreo;
axi4_l1_in_vector corei;
sc_signal<axi4_l2_in_type> l2i;
sc_signal<axi4_l2_out_type> l2o;
dport_in_vector wb_dport_i;
dport_out_vector wb_dport_o;
hart_irq_vector vec_irq;
hart_signal_vector vec_halted;
hart_signal_vector vec_available;
hart_signal_vector vec_flush_l2;
sc_signal<sc_uint<CFG_CPU_MAX>> wb_halted;
sc_signal<sc_uint<CFG_CPU_MAX>> wb_available;
sc_signal<sc_uint<CFG_LOG2_CPU_MAX>> wb_dmi_hartsel;
sc_signal<bool> w_dmi_haltreq;
sc_signal<bool> w_dmi_resumereq;
sc_signal<bool> w_dmi_resethaltreq;
sc_signal<bool> w_dmi_hartreset;
sc_signal<bool> w_dmi_dport_req_valid;
sc_signal<sc_uint<DPortReq_Total>> wb_dmi_dport_req_type;
sc_signal<sc_uint<RISCV_ARCH>> wb_dmi_dport_addr;
sc_signal<sc_uint<RISCV_ARCH>> wb_dmi_dport_wdata;
sc_signal<sc_uint<3>> wb_dmi_dport_size;
sc_signal<bool> w_ic_dport_req_ready;
sc_signal<bool> w_dmi_dport_resp_ready;
sc_signal<bool> w_ic_dport_resp_valid;
sc_signal<bool> w_ic_dport_resp_error;
sc_signal<sc_uint<RISCV_ARCH>> wb_ic_dport_rdata;
sc_signal<sc_biguint<(32 * CFG_PROGBUF_REG_TOTAL)>> wb_progbuf;
sc_signal<bool> w_flush_l2;
dmidebug *dmi0;
ic_dport *dport_ic0;
ic_axi4_to_l1 *acp_bridge;
RiverAmba *cpux[CFG_CPU_MAX];
DummyCpu *dumx[CFG_CPU_MAX];
L2Top *l2cache;
L2Dummy *l2dummy;
L2SerDes *l2serdes0;
};
} // namespace debugger
|
//
// Copyright 2022 Sergey Khabarov, [email protected]
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
#pragma once
#include <systemc.h>
#include "api_core.h"
namespace debugger {
template<int iwidth = 105, // Input bus width
int shiftwidth = 7> // Encoded value width
SC_MODULE(zeroenc) {
public:
sc_in<sc_biguint<iwidth>> i_value; // Input value to encode
sc_out<sc_uint<shiftwidth>> o_shift; // First non-zero bit
void gen0();
SC_HAS_PROCESS(zeroenc);
zeroenc(sc_module_name name);
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
sc_signal<sc_uint<shiftwidth>> wb_muxind[(iwidth + 1)];
};
template<int iwidth, int shiftwidth>
zeroenc<iwidth, shiftwidth>::zeroenc(sc_module_name name)
: sc_module(name),
i_value("i_value"),
o_shift("o_shift") {
SC_METHOD(gen0);
sensitive << i_value;
for (int i = 0; i < (iwidth + 1); i++) {
sensitive << wb_muxind[i];
}
}
template<int iwidth, int shiftwidth>
void zeroenc<iwidth, shiftwidth>::generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd) {
if (o_vcd) {
sc_trace(o_vcd, i_value, i_value.name());
sc_trace(o_vcd, o_shift, o_shift.name());
}
}
template<int iwidth, int shiftwidth>
void zeroenc<iwidth, shiftwidth>::gen0() {
wb_muxind[iwidth] = 0;
for (int i = (iwidth - 1); i >= 0; i--) {
wb_muxind[i] = (i_value.read()[i] == 1) ? i : wb_muxind[(i + 1)].read().to_int();
}
o_shift = wb_muxind[0];
}
} // namespace debugger
|
#include <systemc.h>
SC_MODULE(nand_gate) {
public:
sc_in<bool> inp_a, inp_b;
sc_out<bool> out;
SC_HAS_PROCESS(nand_gate);
nand_gate(sc_module_name nm);
private:
void nand_main(void);
};
|
/* Copyright (c) 2015 Convey Computer Corporation
*
* This file is part of the OpenHT toolset located at:
*
* https://github.com/TonyBrewer/OpenHT
*
* Use and distribution licensed under the BSD 3-clause license.
* See the LICENSE file for the complete license text.
*/
#pragma once
#include <stdint.h>
#include <assert.h>
#include <systemc.h>
#ifdef _HTV
#define HT_CYCLE() 0
#define assert(a)
#define ht_assert(a)
#define printf(...)
#define fprintf(...)
#else
#define SC_X 0
#define ht_topology_top
#define ht_prim
#define ht_noload
#define ht_state
#define ht_local
#define ht_clk(...)
#define ht_attrib(name,inst,value)
#endif
ht_prim ht_clk("clk") inline void HtResetFlop (bool &r_reset, const bool &i_reset) { r_reset = i_reset; }
ht_prim ht_clk("clkhx", "clk1x") inline void HtResetFlop1x (bool &r_reset, const bool &i_reset) { r_reset = i_reset; }
ht_prim ht_clk("clkhx", "clk2x") inline void HtResetFlop2x (bool &r_reset, const bool &i_reset) { r_reset = i_reset; }
ht_prim ht_clk("clkhx", "clk1x", "clk2x") inline void HtResetFlop1x2x (bool &r_reset1x, bool&r_reset2x, const bool &i_reset) { r_reset1x = i_reset; r_reset2x = i_reset; }
#ifndef _HTV
namespace Ht {
extern sc_core::sc_trace_file * g_vcdp;
}
inline void ht_assert(bool bCond)
{
if (bCond) return;
if (Ht::g_vcdp) sc_close_vcd_trace_file(Ht::g_vcdp);
assert(0);
}
template<typename T>
inline T ht_bad_data(T const &)
{
return (T)0xDBADBADBADBADBADLL;
}
template <typename T, int addrBits> class ht_dist_que {
public:
ht_dist_que() {
ht_assert(addrBits < 10);
m_maxEntriesUsed = 0;
m_bPop = false;
m_bPush = false;
m_bPushWasReset = false;
m_bPopWasReset = false;
}
~ht_dist_que() {
#ifdef QUE_DEBUG
if (m_pName)
fprintf(stderr, "%s - maxEntries = %d of %d\n", m_pName, m_maxEntriesUsed, (1 << addrBits));
#endif
}
void SetName(char *pName) { m_pName = pName; }
uint32_t size() {
return (uint32_t)((m_cmpWrIdx.read() >= m_cmpRdIdx.read())
? m_cmpWrIdx.read() - m_cmpRdIdx.read()
: (m_cmpWrIdx.read() + (1 << (addrBits+1)) - m_cmpRdIdx.read())); }
bool empty() { return m_cmpWrIdx.read() == m_cmpRdIdx.read(); }
bool full(uint32_t num=0) { return size() >= (1 << addrBits) - num; }
const T &front() { return m_que[m_rdIdx & ((1 << addrBits)-1)]; }
T &read_entry_debug(int idx) { return m_que[(m_rdIdx + idx) & ((1 << addrBits)-1)]; }
void pop() {
if (m_bPopWasReset && m_bPushWasReset) {
ht_assert(!empty());
ht_assert(!m_bPop);
m_bPop = true;
}
}
void push(T data) {
if (m_bPopWasReset && m_bPushWasReset) {
ht_assert(!full());
ht_assert(!m_bPush);
m_bPush = true;
m_pushData = data;
}
}
bool push_in_use() { return m_bPush; }
void clock(bool bReset) {
push_clock(bReset);
pop_clock(bReset);
}
void push_clock(bool bReset) {
uint32_t wrIdx = (uint32_t)m_cmpWrIdx.read();
if (bReset) {
wrIdx = 0;
m_bPushWasReset = true;
} else if (m_bPush) {
m_que[m_wrIdx & ((1 << addrBits)-1)] = m_pushData;
wrIdx += 1;
if (m_maxEntriesUsed < size()) m_maxEntriesUsed = size();
}
m_wrIdx = wrIdx;
m_cmpWrIdx = wrIdx;
m_bPush = false;
}
void pop_clock(bool bReset) {
uint32_t rdIdx = (uint32_t)m_cmpRdIdx.read();
if (bReset) {
rdIdx = 0;
m_bPopWasReset = true;
} else if (m_bPop) {
ht_assert(!empty());
rdIdx += 1;
}
m_rdIdx = rdIdx;
m_cmpRdIdx = rdIdx;
m_bPop = false;
}
uint32_t read_addr() { return m_rdIdx & ((1 << addrBits)-1); }
uint32_t write_addr() { return m_wrIdx & ((1 << addrBits)-1); }
uint32_t capacity() { return (1 << addrBits); }
friend void sc_trace(sc_trace_file *tf, const ht_dist_que & v, const std::string & NAME ) {
}
private:
char * m_pName;
uint32_t m_maxEntriesUsed;
T m_que[1 << addrBits];
T m_pushData;
T m_postClockFrontData;
uint32_t m_rdIdx;
uint32_t m_wrIdx;
sc_signal<sc_uint<addrBits+1> > m_cmpWrIdx; // compares use an sc_signal to allow different rd/wr clocks
sc_signal<sc_uint<addrBits+1> > m_cmpRdIdx;
bool m_bPop;
bool m_bPush;
bool m_bPopWasReset;
bool m_bPushWasReset;
};
template <typename T, int addrBits> class ht_block_que {
public:
ht_block_que() {
ht_assert(addrBits < 18);
m_maxEntriesUsed = 0;
m_bPop = false;
m_bPush = false;
m_bPushWasReset = false;
m_bPopWasReset = false;
}
~ht_block_que() {
#ifdef QUE_DEBUG
if (m_pName)
fprintf(stderr, "%s - maxEntries = %d of %d\n", m_pName, m_maxEntriesUsed, (1 << addrBits));
#endif
}
void SetName(char *pName) { m_pName = pName; }
uint32_t size() {
return (uint32_t)((m_cmpWrIdx.read() >= m_cmpRdIdx.read())
? m_cmpWrIdx.read() - m_cmpRdIdx.read()
: (m_cmpWrIdx.read() + (1 << (addrBits+1)) - m_cmpRdIdx.read()));
}
bool empty() { return m_cmpWrIdx2.read() == m_cmpRdIdx.read(); }
bool full(uint32_t num=0) { return size() >= (1 << addrBits) - num; }
const T &front() { return m_que[m_rdIdx & ((1 << addrBits)-1)]; }
T &EntryIgnore(int idx) { return m_que[idx]; }
void pop() {
if (m_bPopWasReset && m_bPushWasReset) {
ht_assert(!empty());
ht_assert(!m_bPop);
m_bPop = true;
}
}
void push(T data) {
if (m_bPopWasReset && m_bPushWasReset) {
ht_assert(!full());
ht_assert(!m_bPush);
m_bPush = true;
m_pushData = data;
}
}
bool push_in_use() { return m_bPush; }
void clock(bool bReset) {
push_clock(bReset);
pop_clock(bReset);
}
void push_clock(bool bReset) {
uint32_t wrIdx = (uint32_t)m_cmpWrIdx.read();
if (bReset) {
wrIdx = 0;
m_cmpWrIdx2 = 0;
m_bPushWasReset = true;
} else if (m_bPush) {
m_que[m_wrIdx & ((1 << addrBits)-1)] = m_pushData;
wrIdx += 1;
if (m_maxEntriesUsed < size()) m_maxEntriesUsed = size();
}
m_cmpWrIdx2 = m_cmpWrIdx;
m_wrIdx = wrIdx;
m_cmpWrIdx = wrIdx;
m_bPush = false;
}
void pop_clock(bool bReset) {
uint32_t rdIdx = (uint32_t)m_cmpRdIdx.read();
if (bReset) {
rdIdx = 0;
m_bPopWasReset = true;
} else if (m_bPop) {
ht_assert(!empty());
rdIdx += 1;
}
m_rdIdx = rdIdx;
m_cmpRdIdx = rdIdx;
m_bPop = false;
}
uint32_t read_addr() { return m_rdIdx & ((1 << addrBits)-1); }
uint32_t write_addr() { return m_wrIdx & ((1 << addrBits)-1); }
uint32_t capacity() { return (1 << addrBits); }
friend void sc_trace(sc_trace_file *tf, const ht_block_que & v, const std::string & NAME ) {
}
private:
char * m_pName;
uint32_t m_maxEntriesUsed;
T m_que[1 << addrBits];
T m_pushData;
T m_postClockFrontData;
uint32_t m_rdIdx;
uint32_t m_wrIdx;
sc_signal<sc_uint<addrBits+1> > m_cmpWrIdx; // compares use an sc_signal to allow different rd/wr clocks
sc_signal<sc_uint<addrBits+1> > m_cmpWrIdx2;
sc_signal<sc_uint<addrBits+1> > m_cmpRdIdx;
bool m_bPop;
bool m_bPush;
bool m_bPopWasReset;
bool m_bPushWasReset;
};
template <typename T, int AW1, int AW2=0>
class ht_dist_ram {
public:
ht_dist_ram() {
m_bReset = true;
m_bWrAddr = false;
m_bRdAddr = false;
m_bWrData = false;
}
const T & read_mem_debug(uint64_t rdIdx1, uint64_t rdIdx2=0) {
return m_mem[(rdIdx1 + (rdIdx2 << AW1)) & ((1<<AW1) * (1<<AW2) - 1)];
}
void read_addr_ignore(uint64_t rdIdx1, uint64_t rdIdx2=0) {
m_rdAddr = (rdIdx1 + (rdIdx2 << AW1)) & ((1<<AW1) * (1<<AW2) - 1);
}
const T & read_mem_ignore() { return m_mem[m_rdAddr]; }
void read_addr(uint64_t rdIdx1, uint64_t rdIdx2 = 0) {
uint64_t rdAddr = (rdIdx1 + (rdIdx2 << AW1)) & ((1 << AW1) * (1 << AW2) - 1);
ht_assert(m_bReset || !m_bRdAddr || m_rdAddr == rdAddr);
m_bRdAddr = true;
m_rdAddr = rdAddr;
}
void read_addr(uint64_t rdIdx1, uint64_t rdIdx2 = 0) const {
uint64_t rdAddr = (rdIdx1 + (rdIdx2 << AW1)) & ((1 << AW1) * (1 << AW2) - 1);
ht_assert(m_bReset || !m_bRdAddr || m_rdAddr == rdAddr);
const_cast<ht_dist_ram*>(this)->m_bRdAddr = true;
const_cast<ht_dist_ram*>(this)->m_rdAddr = rdAddr;
}
bool read_in_use() { return m_bRdAddr; }
void write_addr(uint64_t wrIdx1, uint64_t wrIdx2=0) {
uint64_t wrAddr = (wrIdx1 + (wrIdx2 << AW1)) & ((1 << AW1) * (1 << AW2) - 1);
ht_assert(m_bReset || !m_bWrAddr || m_wrAddr == wrAddr);
m_wrAddr = wrAddr;
if (!m_bWrAddr)
m_wrData = m_mem[m_bReset ? 0 : m_wrAddr];
m_bWrAddr = true;
}
uint64_t write_addr_debug() { return m_wrAddr; }
bool write_in_use() { return m_bWrAddr; }
T & write_mem_debug(uint64_t wrIdx1, uint64_t wrIdx2=0) {
uint64_t wrAddr = (wrIdx1 + (wrIdx2 << AW1)) & ((1<<AW1) * (1<<AW2) - 1);
return m_mem[wrAddr];
}
const T & read_mem() const {
if (m_bReset) return m_mem[0];
ht_assert(m_bRdAddr);
return m_mem[m_rdAddr];
}
T & write_mem() {
m_bWrData = true;
return m_wrData;
}
void write_mem(const T &wrData) {
m_bWrData = true;
m_wrData = wrData;
}
void read_clock(bool bReset = false) {
m_bReset = bReset;
m_bRdAddr = false;
}
void write_clock(bool bReset = false) {
m_bReset = bReset;
if (!m_bReset && m_bWrData) {
ht_assert(m_bWrAddr);
m_mem[m_wrAddr] = m_wrData;
}
m_bWrData = false;
m_bWrAddr = false;
}
void clock(bool bReset=false) {
read_clock(bReset);
write_clock(bReset);
}
friend void sc_trace(sc_trace_file *tf, const ht_dist_ram & v, const std::string & NAME ) {
}
private:
bool m_bReset;
T m_mem[(1<<AW1)*(1<<AW2)];
bool m_bRdAddr;
uint64_t m_rdAddr;
bool m_bWrAddr;
bool m_bWrData;
T m_wrData;
uint64_t m_wrAddr;
};
template <typename T, int AW1, int AW2=0, bool bDoReg=false>
class ht_block_ram {
public:
ht_block_ram() {
m_bReset = true;
m_bWrAddr = false;
m_bWrData = false;
r_bWrData = false;
r_wrAddr = 0;
m_bRdAddr = false;
r_bRdAddr = true;
r_rdAddr = 0;
}
void RdAddrIgnore(uint64_t rdIdx1, uint64_t rdIdx2) {
m_bRdAddr = true;
m_rdAddr = (rdIdx1 + (rdIdx2 << AW1)) & ((1<<AW1) * (1<<AW2) - 1);
}
void read_addr(uint64_t rdIdx1, uint64_t rdIdx2 = 0) {
ht_assert(m_bReset || !m_bRdAddr);
m_bRdAddr = true;
m_rdAddr = (rdIdx1 + (rdIdx2 << AW1)) & ((1 << AW1) * (1 << AW2) - 1);
}
void read_addr(uint64_t rdIdx1, uint64_t rdIdx2 = 0) const {
ht_assert(m_bReset || !m_bRdAddr);
const_cast<ht_block_ram*>(this)->m_bRdAddr = true;
const_cast<ht_block_ram*>(this)->m_rdAddr = (rdIdx1 + (rdIdx2 << AW1)) & ((1 << AW1) * (1 << AW2) - 1);
}
uint64_t read_addr() { return m_rdAddr; }
bool read_in_use() { return m_bRdAddr; }
void write_addr(uint64_t wrIdx1, uint64_t wrIdx2=0) {
uint64_t wrAddr = (wrIdx1 + (wrIdx2 << AW1)) & ((1 << AW1) * (1 << AW2) - 1);
ht_assert(m_bReset || !m_bWrAddr || m_wrAddr == wrAddr);
m_wrAddr = wrAddr;
if (!m_bWrAddr)
m_wrData = m_mem[m_bReset ? 0 : m_wrAddr];
m_bWrAddr = true;
}
bool write_in_use() { return m_bWrAddr; }
const T & read_mem_debug(uint64_t rdIdx1, uint64_t rdIdx2=0) {
return m_mem[(rdIdx1 + (rdIdx2 << AW1)) & ((1<<AW1) * (1<<AW2) - 1)];
}
T read_mem() const {
if (m_bReset) return m_mem[0];
ht_assert(bDoReg ? r_bRdAddr2 : r_bRdAddr);
return bDoReg ? r_doReg : ((r_bRdAddr && r_bWrData && r_rdAddr == r_wrAddr) ? ht_bad_data(r_doReg) : m_mem[r_rdAddr]);
}
T & write_mem() { ht_assert(m_bWrAddr); return m_wrData; }
void write_mem(const T &wrData) {
ht_assert(m_bReset || m_bWrAddr);
m_bWrData = true;
m_wrData = wrData;
}
T & write_mem_debug(uint64_t wrIdx1, uint64_t wrIdx2=0) {
uint64_t wrAddr = (wrIdx1 + (wrIdx2 << AW1)) & ((1<<AW1) * (1<<AW2) - 1);
return m_mem[wrAddr];
}
void read_clock(bool bReset = false) {
m_bReset = bReset;
if (!m_bReset && r_bRdAddr)
r_doReg = (r_bRdAddr && r_bWrData && r_rdAddr == r_wrAddr) ? ht_bad_data(r_doReg) : m_mem[r_rdAddr];
r_bRdAddr2 = r_bRdAddr;
r_bRdAddr = m_bRdAddr;
m_bRdAddr = false;
r_rdAddr = m_rdAddr;
}
void write_clock(bool bReset = false) {
m_bReset = bReset;
if (!m_bReset && m_bWrData)
m_mem[m_wrAddr] = m_wrData;
r_bWrData = m_bWrData;
r_wrAddr = m_wrAddr;
m_bWrAddr = false;
m_bWrData = false;
}
void clock(bool bReset = false) {
read_clock(bReset);
write_clock(bReset);
}
friend void sc_trace(sc_trace_file *tf, const ht_block_ram & v, const std::string & NAME ) {
}
private:
bool m_bReset;
T m_mem[(1<<AW1)*(1<<AW2)];
T r_doReg;
bool m_bRdAddr;
uint64_t m_rdAddr;
sc_signal<bool> r_bRdAddr;
bool r_bRdAddr2;
sc_signal<uint64_t> r_rdAddr;
bool m_bWrData;
sc_signal<bool> r_bWrData;
bool m_bWrAddr;
T m_wrData;
uint64_t m_wrAddr;
sc_signal<uint64_t> r_wrAddr;
};
////////////////////////////////
// T - type
// SW - select width
// AW1 - address 1 width
// AW2 - address 2 width
// bDoReg - data out register enable
// specialization for WC=1
template <typename T, int SW, int AW1, int AW2=0, bool bDoReg=false>
class ht_mrd_block_ram {
public:
ht_mrd_block_ram() {
m_bReset = true;
m_bWrAddr = false;
m_bWrData = false;
r_bWrData = false;
r_wrAddr = 0;
m_bRdAddr = false;
r_bRdAddr = true;
r_rdAddr = 0;
}
void RdAddrIgnore(uint64_t rdIdx1, uint64_t rdIdx2) {
m_bRdAddr = true;
m_rdAddr = (rdIdx1 + (rdIdx2 << AW1)) & ((1<<AW1) * (1<<AW2) - 1);
}
void read_addr(uint64_t rdIdx1, uint64_t rdIdx2=0) {
ht_assert(m_bReset || !m_bRdAddr);
m_bRdAddr = true;
m_rdAddr = (rdIdx1 + (rdIdx2 << AW1)) & ((1<<AW1) * (1<<AW2) - 1);
}
uint64_t read_addr() { return m_rdAddr; }
void write_addr(uint64_t wrSel, uint64_t wrIdx1, uint64_t wrIdx2=0) {
uint64_t wrAddr = (wrIdx1 + (wrIdx2 << AW1)) & ((1 << AW1) * (1 << AW2) - 1);
ht_assert(wrSel < (1 << SW));
ht_assert(m_bReset || !m_bWrAddr || m_wrAddr == wrAddr);
m_wrAddr = wrAddr;
m_wrSel = wrSel;
if (!m_bWrAddr)
m_wrData = m_bReset ? m_mem[0][0] : m_mem[m_wrAddr][m_wrSel];
m_bWrAddr = true;
}
const T & read_mem_debug(uint64_t rdSel, uint64_t rdIdx1, uint64_t rdIdx2=0) {
ht_assert(rdSel < (1<<SW));
return m_mem[(rdIdx1 + (rdIdx2 << AW1)) & ((1<<AW1) * (1<<AW2) - 1)][rdSel];
}
T read_mem(uint64_t rdSel) {
if (m_bReset) return m_mem[0][0];
ht_assert(rdSel < (1 << SW));
ht_assert(bDoReg ? r_bRdAddr2 : r_bRdAddr);
return bDoReg ? r_doReg[rdSel] : ((r_bRdAddr && r_bWrData && r_rdAddr == r_wrAddr) ? ht_bad_data(r_doReg[0]) : m_mem[r_rdAddr][rdSel]);
}
T & write_mem() { ht_assert(m_bWrAddr); return m_wrData; }
void write_mem(const T &wrData) {
ht_assert(m_bReset || m_bWrAddr);
m_bWrData = true;
m_wrData = wrData;
}
T & write_mem_debug(uint64_t wrSel, uint64_t wrIdx1, uint64_t wrIdx2=0) {
ht_assert(wrSel < (1<<SW));
uint64_t wrAddr = (wrIdx1 + (wrIdx2 << AW1)) & ((1<<AW1) * (1<<AW2) - 1);
return m_mem[wrAddr][wrSel];
}
void read_clock(bool bReset = false) {
m_bReset = bReset;
if (!m_bReset && r_bRdAddr) {
for (uint64_t rdSel = 0; rdSel < (1<<SW); rdSel += 1)
r_doReg[rdSel] = (r_bRdAddr && r_bWrData && r_rdAddr == r_wrAddr) ? ht_bad_data(r_doReg[0]) : m_mem[r_rdAddr][rdSel];
}
r_bRdAddr2 = r_bRdAddr;
r_bRdAddr = m_bRdAddr;
m_bRdAddr = false;
r_rdAddr = m_rdAddr;
}
void write_clock(bool bReset = false) {
m_bReset = bReset;
if (!m_bReset && m_bWrData)
m_mem[m_wrAddr][m_wrSel] = m_wrData;
r_bWrData = m_bWrData;
r_wrAddr = m_wrAddr;
m_bWrAddr = false;
m_bWrData = false;
}
void clock(bool bReset = false) {
read_clock(bReset);
write_clock(bReset);
}
friend void sc_trace(sc_trace_file *tf, const ht_mrd_block_ram & v, const std::string & NAME ) {
}
private:
bool m_bReset;
T m_mem[(1 << AW1)*(1 << AW2)][1 << SW];
T r_doReg[1<<SW];
bool m_bRdAddr;
uint64_t m_rdAddr;
bool r_bRdAddr;
bool r_bRdAddr2;
uint64_t r_rdAddr;
bool m_bWrData;
bool r_bWrData;
bool m_bWrAddr;
T m_wrData;
uint64_t m_wrAddr;
uint64_t m_wrSel;
uint64_t r_wrAddr;
};
template <typename T, int SW, int AW1, int AW2=0, bool bDoReg=false>
class ht_mwr_block_ram {
public:
ht_mwr_block_ram() {
m_bReset = true;
m_bWrAddr = false;
m_bWrData = false;
r_bWrData = false;
r_wrAddr = 0;
m_bRdAddr = false;
r_bRdAddr = true;
r_rdSel = 0;
r_rdAddr = 0;
}
void RdAddrIgnore(uint64_t rdSel, uint64_t rdIdx1, uint64_t rdIdx2=0) {
ht_assert(rdSel < (1<<SW));
m_bRdAddr = true;
m_rdSel = rdSel;
m_rdAddr = (rdIdx1 + (rdIdx2 << AW1)) & ((1<<AW1) * (1<<AW2) - 1);
}
void read_addr(uint64_t rdSel, uint64_t rdIdx1, uint64_t rdIdx2=0) {
ht_assert(m_bReset || rdSel < (1 << SW));
ht_assert(m_bReset || !m_bRdAddr);
m_bRdAddr = true;
m_rdSel = rdSel;
m_rdAddr = (rdIdx1 + (rdIdx2 << AW1)) & ((1<<AW1) * (1<<AW2) - 1);
}
uint64_t read_addr() { return m_rdAddr; }
void write_addr(uint64_t wrIdx1, uint64_t wrIdx2=0) {
uint64_t wrAddr = (wrIdx1 + (wrIdx2 << AW1)) & ((1 << AW1) * (1 << AW2) - 1);
ht_assert(m_bReset || !m_bWrAddr || m_wrAddr == wrAddr);
m_wrAddr = wrAddr;
for (uint64_t wrSel = 0; wrSel < (1<<SW); wrSel += 1)
m_wrData[wrSel] = 0;
m_bWrAddr = true;
}
const T & read_mem_debug(uint64_t rdSel, uint64_t rdIdx1, uint64_t rdIdx2=0) {
ht_assert(rdSel < (1<<SW));
return m_mem[(rdIdx1 + (rdIdx2 << AW1)) & ((1<<AW1) * (1<<AW2) - 1)][rdSel];
}
T read_mem() {
if (m_bReset) return m_mem[0][0];
ht_assert(bDoReg ? r_bRdAddr2 : r_bRdAddr);
return bDoReg ? r_doReg : ((r_bRdAddr && r_bWrData && r_rdAddr == r_wrAddr) ? ht_bad_data(r_doReg) : m_mem[r_rdAddr][r_rdSel]);
}
T & write_mem() { ht_assert(m_bWrAddr); return m_wrData; }
void write_mem(uint64_t wrSel, const T &wrData) {
ht_assert(m_bReset || wrSel < (1 << SW));
ht_assert(m_bReset || m_bWrAddr);
m_bWrData = true;
m_wrData[m_bReset ? 0 : wrSel] = wrData;
}
T & write_mem_debug(uint64_t wrSel, uint64_t wrIdx1, uint64_t wrIdx2=0) {
ht_assert(wrSel < (1<<SW));
uint64_t wrAddr = (wrIdx1 + (wrIdx2 << AW1)) & ((1<<AW1) * (1<<AW2) - 1);
return m_mem[wrAddr][wrSel];
}
void read_clock(bool bReset = false) {
m_bReset = bReset;
if (!m_bReset && r_bRdAddr)
r_doReg = (r_bRdAddr && r_bWrData && r_rdAddr == r_wrAddr) ? ht_bad_data(r_doReg) : m_mem[r_rdAddr][r_rdSel];
r_bRdAddr2 = r_bRdAddr;
r_bRdAddr = m_bRdAddr;
m_bRdAddr = false;
r_rdSel = m_rdSel;
r_rdAddr = m_rdAddr;
}
void write_clock(bool bReset = false) {
m_bReset = bReset;
if (!m_bReset && m_bWrData) {
for (int wrSel = 0; wrSel < (1<<SW); wrSel += 1)
m_mem[m_wrAddr][wrSel] = m_wrData[wrSel];
}
r_bWrData = m_bWrData;
r_wrAddr = m_wrAddr;
m_bWrAddr = false;
m_bWrData = false;
}
void clock(bool bReset = false) {
read_clock(bReset);
write_clock(bReset);
}
friend void sc_trace(sc_trace_file *tf, const ht_mwr_block_ram & v, const std::string & NAME ) {
}
private:
bool m_bReset;
T m_mem[(1 << AW1)*(1 << AW2)][1 << SW];
T r_doReg;
bool m_bRdAddr;
uint64_t m_rdSel;
uint64_t m_rdAddr;
bool r_bRdAddr;
bool r_bRdAddr2;
uint64_t r_rdSel;
uint64_t r_rdAddr;
bool m_bWrData;
bool r_bWrData;
bool m_bWrAddr;
T m_wrData[1<<SW];
uint64_t m_wrSel;
uint64_t m_wrAddr;
uint64_t r_wrAddr;
};
template <typename T, int addrBits> class ht_ultra_que {
public:
ht_ultra_que() {
ht_assert(addrBits < 18);
m_maxEntriesUsed = 0;
m_bPop = false;
m_bPush = false;
m_bPushWasReset = false;
m_bPopWasReset = false;
}
~ht_ultra_que() {
#ifdef QUE_DEBUG
if (m_pName)
fprintf(stderr, "%s - maxEntries = %d of %d\n", m_pName, m_maxEntriesUsed, (1 << addrBits));
#endif
}
void SetName(char *pName) { m_pName = pName; }
uint32_t size() {
return (uint32_t)((m_cmpWrIdx.read() >= m_cmpRdIdx.read())
? m_cmpWrIdx.read() - m_cmpRdIdx.read()
: (m_cmpWrIdx.read() + (1 << (addrBits+1)) - m_cmpRdIdx.read()));
}
bool empty() { return m_cmpWrIdx2.read() == m_cmpRdIdx.read(); }
bool full(uint32_t num=0) { return size() >= (1 << addrBits) - num; }
const T &front() { return m_que[m_rdIdx & ((1 << addrBits)-1)]; }
T &EntryIgnore(int idx) { return m_que[idx]; }
void pop() {
if (m_bPopWasReset && m_bPushWasReset) {
ht_assert(!empty());
ht_assert(!m_bPop);
m_bPop = true;
}
}
void push(T data) {
if (m_bPopWasReset && m_bPushWasReset) {
ht_assert(!full());
ht_assert(!m_bPush);
m_bPush = true;
m_pushData = data;
}
}
bool push_in_use() { return m_bPush; }
void clock(bool bReset) {
push_clock(bReset);
pop_clock(bReset);
}
void push_clock(bool bReset) {
uint32_t wrIdx = (uint32_t)m_cmpWrIdx.read();
if (bReset) {
wrIdx = 0;
m |
_cmpWrIdx2 = 0;
m_bPushWasReset = true;
} else if (m_bPush) {
m_que[m_wrIdx & ((1 << addrBits)-1)] = m_pushData;
wrIdx += 1;
if (m_maxEntriesUsed < size()) m_maxEntriesUsed = size();
}
m_cmpWrIdx2 = m_cmpWrIdx;
m_wrIdx = wrIdx;
m_cmpWrIdx = wrIdx;
m_bPush = false;
}
void pop_clock(bool bReset) {
uint32_t rdIdx = (uint32_t)m_cmpRdIdx.read();
if (bReset) {
rdIdx = 0;
m_bPopWasReset = true;
} else if (m_bPop) {
ht_assert(!empty());
rdIdx += 1;
}
m_rdIdx = rdIdx;
m_cmpRdIdx = rdIdx;
m_bPop = false;
}
uint32_t read_addr() { return m_rdIdx & ((1 << addrBits)-1); }
uint32_t write_addr() { return m_wrIdx & ((1 << addrBits)-1); }
uint32_t capacity() { return (1 << addrBits); }
friend void sc_trace(sc_trace_file *tf, const ht_ultra_que & v, const std::string & NAME ) {
}
private:
char * m_pName;
uint32_t m_maxEntriesUsed;
T m_que[1 << addrBits];
T m_pushData;
T m_postClockFrontData;
uint32_t m_rdIdx;
uint32_t m_wrIdx;
sc_signal<sc_uint<addrBits+1> > m_cmpWrIdx; // compares use an sc_signal to allow different rd/wr clocks
sc_signal<sc_uint<addrBits+1> > m_cmpWrIdx2;
sc_signal<sc_uint<addrBits+1> > m_cmpRdIdx;
bool m_bPop;
bool m_bPush;
bool m_bPopWasReset;
bool m_bPushWasReset;
};
template <typename T, int AW1, int AW2=0, bool bDoReg=false>
class ht_ultra_ram {
public:
ht_ultra_ram() {
m_bReset = true;
m_bWrAddr = false;
m_bWrData = false;
r_bWrData = false;
r_wrAddr = 0;
m_bRdAddr = false;
r_bRdAddr = true;
r_rdAddr = 0;
}
void RdAddrIgnore(uint64_t rdIdx1, uint64_t rdIdx2) {
m_bRdAddr = true;
m_rdAddr = (rdIdx1 + (rdIdx2 << AW1)) & ((1<<AW1) * (1<<AW2) - 1);
}
void read_addr(uint64_t rdIdx1, uint64_t rdIdx2 = 0) {
ht_assert(m_bReset || !m_bRdAddr);
m_bRdAddr = true;
m_rdAddr = (rdIdx1 + (rdIdx2 << AW1)) & ((1 << AW1) * (1 << AW2) - 1);
}
void read_addr(uint64_t rdIdx1, uint64_t rdIdx2 = 0) const {
ht_assert(m_bReset || !m_bRdAddr);
const_cast<ht_ultra_ram*>(this)->m_bRdAddr = true;
const_cast<ht_ultra_ram*>(this)->m_rdAddr = (rdIdx1 + (rdIdx2 << AW1)) & ((1 << AW1) * (1 << AW2) - 1);
}
uint64_t read_addr() { return m_rdAddr; }
bool read_in_use() { return m_bRdAddr; }
void write_addr(uint64_t wrIdx1, uint64_t wrIdx2=0) {
uint64_t wrAddr = (wrIdx1 + (wrIdx2 << AW1)) & ((1 << AW1) * (1 << AW2) - 1);
ht_assert(m_bReset || !m_bWrAddr || m_wrAddr == wrAddr);
m_wrAddr = wrAddr;
if (!m_bWrAddr)
m_wrData = m_mem[m_bReset ? 0 : m_wrAddr];
m_bWrAddr = true;
}
bool write_in_use() { return m_bWrAddr; }
const T & read_mem_debug(uint64_t rdIdx1, uint64_t rdIdx2=0) {
return m_mem[(rdIdx1 + (rdIdx2 << AW1)) & ((1<<AW1) * (1<<AW2) - 1)];
}
T read_mem() const {
if (m_bReset) return m_mem[0];
ht_assert(bDoReg ? r_bRdAddr2 : r_bRdAddr);
return bDoReg ? r_doReg : ((r_bRdAddr && r_bWrData && r_rdAddr == r_wrAddr) ? ht_bad_data(r_doReg) : m_mem[r_rdAddr]);
}
T & write_mem() { ht_assert(m_bWrAddr); return m_wrData; }
void write_mem(const T &wrData) {
ht_assert(m_bReset || m_bWrAddr);
m_bWrData = true;
m_wrData = wrData;
}
T & write_mem_debug(uint64_t wrIdx1, uint64_t wrIdx2=0) {
uint64_t wrAddr = (wrIdx1 + (wrIdx2 << AW1)) & ((1<<AW1) * (1<<AW2) - 1);
return m_mem[wrAddr];
}
void read_clock(bool bReset = false) {
m_bReset = bReset;
if (!m_bReset && r_bRdAddr)
r_doReg = (r_bRdAddr && r_bWrData && r_rdAddr == r_wrAddr) ? ht_bad_data(r_doReg) : m_mem[r_rdAddr];
r_bRdAddr2 = r_bRdAddr;
r_bRdAddr = m_bRdAddr;
m_bRdAddr = false;
r_rdAddr = m_rdAddr;
}
void write_clock(bool bReset = false) {
m_bReset = bReset;
if (!m_bReset && m_bWrData)
m_mem[m_wrAddr] = m_wrData;
r_bWrData = m_bWrData;
r_wrAddr = m_wrAddr;
m_bWrAddr = false;
m_bWrData = false;
}
void clock(bool bReset = false) {
read_clock(bReset);
write_clock(bReset);
}
friend void sc_trace(sc_trace_file *tf, const ht_ultra_ram & v, const std::string & NAME ) {
}
private:
bool m_bReset;
T m_mem[(1<<AW1)*(1<<AW2)];
T r_doReg;
bool m_bRdAddr;
uint64_t m_rdAddr;
sc_signal<bool> r_bRdAddr;
bool r_bRdAddr2;
sc_signal<uint64_t> r_rdAddr;
bool m_bWrData;
sc_signal<bool> r_bWrData;
bool m_bWrAddr;
T m_wrData;
uint64_t m_wrAddr;
sc_signal<uint64_t> r_wrAddr;
};
////////////////////////////////
// T - type
// SW - select width
// AW1 - address 1 width
// AW2 - address 2 width
// bDoReg - data out register enable
// specialization for WC=1
template <typename T, int SW, int AW1, int AW2=0, bool bDoReg=false>
class ht_mrd_ultra_ram {
public:
ht_mrd_ultra_ram() {
m_bReset = true;
m_bWrAddr = false;
m_bWrData = false;
r_bWrData = false;
r_wrAddr = 0;
m_bRdAddr = false;
r_bRdAddr = true;
r_rdAddr = 0;
}
void RdAddrIgnore(uint64_t rdIdx1, uint64_t rdIdx2) {
m_bRdAddr = true;
m_rdAddr = (rdIdx1 + (rdIdx2 << AW1)) & ((1<<AW1) * (1<<AW2) - 1);
}
void read_addr(uint64_t rdIdx1, uint64_t rdIdx2=0) {
ht_assert(m_bReset || !m_bRdAddr);
m_bRdAddr = true;
m_rdAddr = (rdIdx1 + (rdIdx2 << AW1)) & ((1<<AW1) * (1<<AW2) - 1);
}
uint64_t read_addr() { return m_rdAddr; }
void write_addr(uint64_t wrSel, uint64_t wrIdx1, uint64_t wrIdx2=0) {
uint64_t wrAddr = (wrIdx1 + (wrIdx2 << AW1)) & ((1 << AW1) * (1 << AW2) - 1);
ht_assert(wrSel < (1 << SW));
ht_assert(m_bReset || !m_bWrAddr || m_wrAddr == wrAddr);
m_wrAddr = wrAddr;
m_wrSel = wrSel;
if (!m_bWrAddr)
m_wrData = m_bReset ? m_mem[0][0] : m_mem[m_wrAddr][m_wrSel];
m_bWrAddr = true;
}
const T & read_mem_debug(uint64_t rdSel, uint64_t rdIdx1, uint64_t rdIdx2=0) {
ht_assert(rdSel < (1<<SW));
return m_mem[(rdIdx1 + (rdIdx2 << AW1)) & ((1<<AW1) * (1<<AW2) - 1)][rdSel];
}
T read_mem(uint64_t rdSel) {
if (m_bReset) return m_mem[0][0];
ht_assert(rdSel < (1 << SW));
ht_assert(bDoReg ? r_bRdAddr2 : r_bRdAddr);
return bDoReg ? r_doReg[rdSel] : ((r_bRdAddr && r_bWrData && r_rdAddr == r_wrAddr) ? ht_bad_data(r_doReg[0]) : m_mem[r_rdAddr][rdSel]);
}
T & write_mem() { ht_assert(m_bWrAddr); return m_wrData; }
void write_mem(const T &wrData) {
ht_assert(m_bReset || m_bWrAddr);
m_bWrData = true;
m_wrData = wrData;
}
T & write_mem_debug(uint64_t wrSel, uint64_t wrIdx1, uint64_t wrIdx2=0) {
ht_assert(wrSel < (1<<SW));
uint64_t wrAddr = (wrIdx1 + (wrIdx2 << AW1)) & ((1<<AW1) * (1<<AW2) - 1);
return m_mem[wrAddr][wrSel];
}
void read_clock(bool bReset = false) {
m_bReset = bReset;
if (!m_bReset && r_bRdAddr) {
for (uint64_t rdSel = 0; rdSel < (1<<SW); rdSel += 1)
r_doReg[rdSel] = (r_bRdAddr && r_bWrData && r_rdAddr == r_wrAddr) ? ht_bad_data(r_doReg[0]) : m_mem[r_rdAddr][rdSel];
}
r_bRdAddr2 = r_bRdAddr;
r_bRdAddr = m_bRdAddr;
m_bRdAddr = false;
r_rdAddr = m_rdAddr;
}
void write_clock(bool bReset = false) {
m_bReset = bReset;
if (!m_bReset && m_bWrData)
m_mem[m_wrAddr][m_wrSel] = m_wrData;
r_bWrData = m_bWrData;
r_wrAddr = m_wrAddr;
m_bWrAddr = false;
m_bWrData = false;
}
void clock(bool bReset = false) {
read_clock(bReset);
write_clock(bReset);
}
friend void sc_trace(sc_trace_file *tf, const ht_mrd_ultra_ram & v, const std::string & NAME ) {
}
private:
bool m_bReset;
T m_mem[(1 << AW1)*(1 << AW2)][1 << SW];
T r_doReg[1<<SW];
bool m_bRdAddr;
uint64_t m_rdAddr;
bool r_bRdAddr;
bool r_bRdAddr2;
uint64_t r_rdAddr;
bool m_bWrData;
bool r_bWrData;
bool m_bWrAddr;
T m_wrData;
uint64_t m_wrAddr;
uint64_t m_wrSel;
uint64_t r_wrAddr;
};
template <typename T, int SW, int AW1, int AW2=0, bool bDoReg=false>
class ht_mwr_ultra_ram {
public:
ht_mwr_ultra_ram() {
m_bReset = true;
m_bWrAddr = false;
m_bWrData = false;
r_bWrData = false;
r_wrAddr = 0;
m_bRdAddr = false;
r_bRdAddr = true;
r_rdSel = 0;
r_rdAddr = 0;
}
void RdAddrIgnore(uint64_t rdSel, uint64_t rdIdx1, uint64_t rdIdx2=0) {
ht_assert(rdSel < (1<<SW));
m_bRdAddr = true;
m_rdSel = rdSel;
m_rdAddr = (rdIdx1 + (rdIdx2 << AW1)) & ((1<<AW1) * (1<<AW2) - 1);
}
void read_addr(uint64_t rdSel, uint64_t rdIdx1, uint64_t rdIdx2=0) {
ht_assert(m_bReset || rdSel < (1 << SW));
ht_assert(m_bReset || !m_bRdAddr);
m_bRdAddr = true;
m_rdSel = rdSel;
m_rdAddr = (rdIdx1 + (rdIdx2 << AW1)) & ((1<<AW1) * (1<<AW2) - 1);
}
uint64_t read_addr() { return m_rdAddr; }
void write_addr(uint64_t wrIdx1, uint64_t wrIdx2=0) {
uint64_t wrAddr = (wrIdx1 + (wrIdx2 << AW1)) & ((1 << AW1) * (1 << AW2) - 1);
ht_assert(m_bReset || !m_bWrAddr || m_wrAddr == wrAddr);
m_wrAddr = wrAddr;
for (uint64_t wrSel = 0; wrSel < (1<<SW); wrSel += 1)
m_wrData[wrSel] = 0;
m_bWrAddr = true;
}
const T & read_mem_debug(uint64_t rdSel, uint64_t rdIdx1, uint64_t rdIdx2=0) {
ht_assert(rdSel < (1<<SW));
return m_mem[(rdIdx1 + (rdIdx2 << AW1)) & ((1<<AW1) * (1<<AW2) - 1)][rdSel];
}
T read_mem() {
if (m_bReset) return m_mem[0][0];
ht_assert(bDoReg ? r_bRdAddr2 : r_bRdAddr);
return bDoReg ? r_doReg : ((r_bRdAddr && r_bWrData && r_rdAddr == r_wrAddr) ? ht_bad_data(r_doReg) : m_mem[r_rdAddr][r_rdSel]);
}
T & write_mem() { ht_assert(m_bWrAddr); return m_wrData; }
void write_mem(uint64_t wrSel, const T &wrData) {
ht_assert(m_bReset || wrSel < (1 << SW));
ht_assert(m_bReset || m_bWrAddr);
m_bWrData = true;
m_wrData[m_bReset ? 0 : wrSel] = wrData;
}
T & write_mem_debug(uint64_t wrSel, uint64_t wrIdx1, uint64_t wrIdx2=0) {
ht_assert(wrSel < (1<<SW));
uint64_t wrAddr = (wrIdx1 + (wrIdx2 << AW1)) & ((1<<AW1) * (1<<AW2) - 1);
return m_mem[wrAddr][wrSel];
}
void read_clock(bool bReset = false) {
m_bReset = bReset;
if (!m_bReset && r_bRdAddr)
r_doReg = (r_bRdAddr && r_bWrData && r_rdAddr == r_wrAddr) ? ht_bad_data(r_doReg) : m_mem[r_rdAddr][r_rdSel];
r_bRdAddr2 = r_bRdAddr;
r_bRdAddr = m_bRdAddr;
m_bRdAddr = false;
r_rdSel = m_rdSel;
r_rdAddr = m_rdAddr;
}
void write_clock(bool bReset = false) {
m_bReset = bReset;
if (!m_bReset && m_bWrData) {
for (int wrSel = 0; wrSel < (1<<SW); wrSel += 1)
m_mem[m_wrAddr][wrSel] = m_wrData[wrSel];
}
r_bWrData = m_bWrData;
r_wrAddr = m_wrAddr;
m_bWrAddr = false;
m_bWrData = false;
}
void clock(bool bReset = false) {
read_clock(bReset);
write_clock(bReset);
}
friend void sc_trace(sc_trace_file *tf, const ht_mwr_ultra_ram & v, const std::string & NAME ) {
}
private:
bool m_bReset;
T m_mem[(1 << AW1)*(1 << AW2)][1 << SW];
T r_doReg;
bool m_bRdAddr;
uint64_t m_rdSel;
uint64_t m_rdAddr;
bool r_bRdAddr;
bool r_bRdAddr2;
uint64_t r_rdSel;
uint64_t r_rdAddr;
bool m_bWrData;
bool r_bWrData;
bool m_bWrAddr;
T m_wrData[1<<SW];
uint64_t m_wrSel;
uint64_t m_wrAddr;
uint64_t r_wrAddr;
};
#endif
|
#ifndef PROCESSING_ENGINE_HPP
#define PROCESSING_ENGINE_HPP
#include <systemc.h>
#include "verbose.hpp"
SC_MODULE(processing_engine_module)
{
// PORTS
sc_in<bool> clk;
sc_in<bool> reset;
sc_fifo_in<float> from_scheduler_weight;
sc_fifo_in<float> from_scheduler_input;
sc_fifo_in< sc_uint<34> > from_scheduler_instructions;
sc_fifo_out<float> to_scheduler;
// STATES
sc_uint<30> state_length;
sc_uint<4> state_activation_function;
// PROCESS
void process(void);
// UTIL
float sigmoid(float input);
float relu(float input);
float softmax(float input);
SC_CTOR(processing_engine_module)
{
state_length = 0;
state_activation_function = 0;
SC_CTHREAD(process, clk.pos());
reset_signal_is(reset,true);
}
};
#endif |
#pragma once
#include <systemc.h>
#include "RAM.h"
#include "wb_ram_sc.h"
SC_MODULE(IP_RAM)
{
sc_in_clk CLK;
sc_in<bool> RESET_N;
sc_in<sc_uint<32>> DAT_I;
sc_in<sc_uint<32>> ADR_I;
sc_in<bool> CYC_I; // when asserted indicates that a valid bus cycle in progress
sc_in<sc_uint<2>> SEL_I; // select which words on DAT_O are valid
sc_in<bool> STB_I;
sc_in<bool> WE_I;
sc_out<sc_uint<32>> DAT_O;
sc_out<bool> ACK_O; // when asserted indicates the termination of a bus cycle
sc_in<bool> ARBITER_SEL_I;
//signals
sc_signal<sc_uint<32>> ADR;
sc_signal<sc_uint<32>> RAM_I;
sc_signal<sc_uint<32>> RAM_O;
sc_signal<sc_uint<2>> MEM_SIZE;
sc_signal<bool> WE;
sc_signal<bool> RAM2WRAPPER_VALID;
sc_signal<bool> WRAPPER2RAM_VALID;
void init_mem(std::unordered_map<int,int>*);
void trace(sc_trace_file*);
RAM ram_inst;
wb_ram_sc wrapper_inst;
SC_CTOR(IP_RAM):
ram_inst("RAM"),
wrapper_inst("wb_ram_sc")
{
wrapper_inst.CLK(CLK);
wrapper_inst.RESET_N(RESET_N);
wrapper_inst.DAT_I(DAT_I);
wrapper_inst.ADR_I(ADR_I);
wrapper_inst.CYC_I(CYC_I);
wrapper_inst.SEL_I(SEL_I);
wrapper_inst.STB_I(STB_I);
wrapper_inst.WE_I(WE_I);
wrapper_inst.DAT_O(DAT_O);
wrapper_inst.ACK_O(ACK_O);
wrapper_inst.RAM_DTA_RDY_O(RAM2WRAPPER_VALID);
wrapper_inst.RAM_DT_I(RAM_O);
wrapper_inst.RAM_DT_O(RAM_I);
wrapper_inst.RAM_ADR_O(ADR);
wrapper_inst.RAM_WE_O(WE);
wrapper_inst.RAM_SEL_O(MEM_SIZE);
wrapper_inst.ARBITER_SEL_I(ARBITER_SEL_I);
ram_inst.CLK(CLK);
ram_inst.RESET_N(RESET_N);
ram_inst.ADR_I(ADR);
ram_inst.DAT_I(RAM_I);
ram_inst.VALID_I(RAM2WRAPPER_VALID);
ram_inst.WE_I(WE);
ram_inst.MEM_SIZE(MEM_SIZE);
ram_inst.DAT_O(RAM_O);
}
}; |
/*******************************************************************************
* TestSerial.cpp -- Copyright 2019 Glenn Ramalho - RFIDo Design
*******************************************************************************
* Description:
* Generic Serial Class for communicating with a set of SystemC ports.
* This class tries to mimic the behaviour used by the Hardware Serial
* and SoftwareSerial classes used by the Arduino IDE.
*******************************************************************************
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
#include <systemc.h>
#include "info.h"
#include "TestSerial.h"
#include "clockpacer.h"
#include "Arduino.h"
TestSerial::TestSerial() {
taken = false;
waiting = '\0';
uartno = -1;
pinmodeset = false;
}
TestSerial::TestSerial(int _u) {
if(_u < 0 || _u > 2) {
printf("Invalid UART %d", _u);
uartno = 0;
}
uartno = _u;
taken = false;
waiting = '\0';
pinmodeset = false;
}
TestSerial::TestSerial(int _rxpin, int _rxmode, int _txpin, int _txmode) {
taken = false; waiting = '\0'; pinmodeset = true;
rxpin = _rxpin;
rxmode = _rxmode;
txpin = _txpin;
txmode = _txmode;
}
TestSerial::~TestSerial() {}
void TestSerial::begin(int baudrate, int mode, int pinrx, int pintx) {
if (baudrate <= 0) baudrate = 9600;
PRINTF_INFO("TSER", "Setting UART %d Baud rate to %0d", uartno, baudrate);
/* We set the pin modes. If a value was given in the arguments, we take it.
* If not, we check the pinmodeset list. If it was set, we leave it as is.
* If not, we go with the UART number.
*/
if (pinrx >= 0) rxpin = pinrx;
else if (!pinmodeset) switch(uartno) {
case 0: rxpin = RX; break;
case 1: rxpin = 9; break;
case 2: rxpin = 16; break;
}
if (pintx >= 0) txpin = pintx;
else if (!pinmodeset) switch(uartno) {
case 0: txpin = TX; break;
case 1: txpin = 10; break;
case 2: txpin = 17; break;
}
/* For the modes, we do the same. */
if (mode < 0 || !pinmodeset) {
rxmode = INPUT;
txmode = OUTPUT;
}
/* We first drive the TX level high. It is now an input, but when we change
* the pin to be an output, it will not drive a zero.
*/
pinMode(rxpin, rxmode);
pinMatrixInAttach(rxpin,
(uartno == 0)?U0RXD_IN_IDX:
(uartno == 1)?U1RXD_IN_IDX:
(uartno == 2)?U2RXD_IN_IDX:0, false);
pinMode(txpin, txmode);
pinMatrixOutAttach(txpin,
(uartno == 0)?U0TXD_OUT_IDX:
(uartno == 1)?U1TXD_OUT_IDX:
(uartno == 2)?U2TXD_OUT_IDX:0, false, false);
}
void TestSerial::setports(sc_fifo<unsigned char> *_to,
sc_fifo<unsigned char> *_from) {
to = _to;
from = _from;
}
bool TestSerial::isinit() {
if (from == NULL || to == NULL) return false;
else return true;
}
void TestSerial::end() { PRINTF_INFO("TSER", "Ending Serial");}
int TestSerial::printf(const char *fmt, ...) {
char buff[128], *ptr;
int resp;
va_list argptr;
va_start(argptr, fmt);
resp = vsnprintf(buff, 127, fmt, argptr);
va_end(argptr);
ptr = buff;
if (to == NULL) return 0;
while(*ptr != '\0') {
clockpacer.wait_next_apb_clk();
to->write(*ptr++);
}
return resp;
}
size_t TestSerial::write(uint8_t ch) {
clockpacer.wait_next_apb_clk();
if (to == NULL) return 0;
to->write(ch);
return 1;
}
size_t TestSerial::write(const char* buf) {
size_t sent = 0;
clockpacer.wait_next_apb_clk();
while(*buf != '\0') {
write(*buf);
sent = sent + 1;
buf = buf + 1;
}
return sent;
}
size_t TestSerial::write(const char* buf, size_t len) {
size_t sent = 0;
clockpacer.wait_next_apb_clk();
while(sent < len) {
write(*buf);
sent = sent + 1;
buf = buf + 1;
}
return sent;
}
int TestSerial::availableForWrite() {
/* We return if there is space in the buffer. */
if (to == NULL) return 0;
return to->num_free();
}
int TestSerial::available() {
/* If we have something taken due to a peek, we need to inform the
* requester that we still have something to return. So we have at
* least one. If taken is false, then it depends on the number
* available.
*/
clockpacer.wait_next_apb_clk();
if (from == NULL) return 0;
if (taken) return 1 + from->num_available();
else return from->num_available();
}
void TestSerial::flush() {
/* For flush we get rid of the taken character and then we use the FIFO's
* read to dump the rest.
*/
taken = false;
while(from != NULL && from->num_available()>0) from->read();
}
int TestSerial::read() {
/* Anytime we leave the CPU we need to do a dummy delay. This makes sure
* time advances, in case we happen to be in a timeout loop.
*/
clockpacer.wait_next_apb_clk();
if (from == NULL) return -1;
if (taken) {
taken = false;
return waiting;
}
else if (!from->num_available()) return -1;
return (int)from->read();
}
int TestSerial::bl_read() {
/* Just like the one above but it does a blocking read. Useful to cut
* on polled reads.
*/
clockpacer.wait_next_apb_clk();
if (from == NULL) return -1;
if (taken) {
taken = false;
return waiting;
}
return from->read();
}
int TestSerial::bl_read(sc_time tmout) {
/* And this is a blocking read with a timeout. */
clockpacer.wait_next_apb_clk();
if (from == NULL) return -1;
if (taken) {
taken = false;
return waiting;
}
/* If there is nothing available, we wait for it to arrive or a timeout. */
if (available() == 0) {
wait(tmout, from->data_written_event());
clockpacer.wait_next_apb_clk();
if (available() == 0) return -1;
}
/* If it was all good, we return it. */
return from->read();
}
int TestSerial::peek() {
clockpacer.wait_next_apb_clk();
if (from == NULL) return -1;
if (taken) return waiting;
else if (!from->num_available()) return -1;
else {
taken = true;
waiting = from->read();
return waiting;
}
}
int TestSerial::bl_peek() {
clockpacer.wait_next_apb_clk();
if (from == NULL) return -1;
if (taken) return waiting;
else {
taken = true;
waiting = from->read();
return waiting;
}
}
int TestSerial::bl_peek(sc_time tmout) {
clockpacer.wait_next_apb_clk();
if (from == NULL) return -1;
if (taken) return waiting;
else {
/* If there is nothing available,we wait for it to arrive or a timeout. */
if (available() == 0) {
wait(tmout, from->data_written_event());
clockpacer.wait_next_apb_clk();
if (available() == 0) return -1;
}
taken = true;
waiting = from->read();
return waiting;
}
}
|
//
// Copyright 2022 Sergey Khabarov, [email protected]
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
#pragma once
#include <systemc.h>
#include "../ambalib/types_amba.h"
#include "river_cfg.h"
namespace debugger {
// Debug interface
class dport_in_type {
public:
dport_in_type() {
haltreq = 0;
resumereq = 0;
resethaltreq = 0;
hartreset = 0;
req_valid = 0;
dtype = 0;
addr = 0;
wdata = 0;
size = 0;
resp_ready = 0;
}
dport_in_type(bool haltreq_,
bool resumereq_,
bool resethaltreq_,
bool hartreset_,
bool req_valid_,
sc_uint<DPortReq_Total> dtype_,
sc_uint<RISCV_ARCH> addr_,
sc_uint<RISCV_ARCH> wdata_,
sc_uint<3> size_,
bool resp_ready_) {
haltreq = haltreq_;
resumereq = resumereq_;
resethaltreq = resethaltreq_;
hartreset = hartreset_;
req_valid = req_valid_;
dtype = dtype_;
addr = addr_;
wdata = wdata_;
size = size_;
resp_ready = resp_ready_;
}
inline bool operator == (const dport_in_type &rhs) const {
bool ret = true;
ret = ret
&& rhs.haltreq == haltreq
&& rhs.resumereq == resumereq
&& rhs.resethaltreq == resethaltreq
&& rhs.hartreset == hartreset
&& rhs.req_valid == req_valid
&& rhs.dtype == dtype
&& rhs.addr == addr
&& rhs.wdata == wdata
&& rhs.size == size
&& rhs.resp_ready == resp_ready;
return ret;
}
inline dport_in_type& operator = (const dport_in_type &rhs) {
haltreq = rhs.haltreq;
resumereq = rhs.resumereq;
resethaltreq = rhs.resethaltreq;
hartreset = rhs.hartreset;
req_valid = rhs.req_valid;
dtype = rhs.dtype;
addr = rhs.addr;
wdata = rhs.wdata;
size = rhs.size;
resp_ready = rhs.resp_ready;
return *this;
}
inline friend void sc_trace(sc_trace_file *tf,
const dport_in_type&v,
const std::string &NAME) {
sc_trace(tf, v.haltreq, NAME + "_haltreq");
sc_trace(tf, v.resumereq, NAME + "_resumereq");
sc_trace(tf, v.resethaltreq, NAME + "_resethaltreq");
sc_trace(tf, v.hartreset, NAME + "_hartreset");
sc_trace(tf, v.req_valid, NAME + "_req_valid");
sc_trace(tf, v.dtype, NAME + "_dtype");
sc_trace(tf, v.addr, NAME + "_addr");
sc_trace(tf, v.wdata, NAME + "_wdata");
sc_trace(tf, v.size, NAME + "_size");
sc_trace(tf, v.resp_ready, NAME + "_resp_ready");
}
inline friend ostream &operator << (ostream &os,
dport_in_type const &v) {
os << "("
<< v.haltreq << ","
<< v.resumereq << ","
<< v.resethaltreq << ","
<< v.hartreset << ","
<< v.req_valid << ","
<< v.dtype << ","
<< v.addr << ","
<< v.wdata << ","
<< v.size << ","
<< v.resp_ready << ")";
return os;
}
public:
bool haltreq;
bool resumereq;
bool resethaltreq;
bool hartreset;
bool req_valid;
sc_uint<DPortReq_Total> dtype;
sc_uint<RISCV_ARCH> addr;
sc_uint<RISCV_ARCH> wdata;
sc_uint<3> size;
bool resp_ready;
};
static const dport_in_type dport_in_none;
class dport_out_type {
public:
dport_out_type() {
req_ready = 1;
resp_valid = 1;
resp_error = 0;
rdata = 0;
}
dport_out_type(bool req_ready_,
bool resp_valid_,
bool resp_error_,
sc_uint<RISCV_ARCH> rdata_) {
req_ready = req_ready_;
resp_valid = resp_valid_;
resp_error = resp_error_;
rdata = rdata_;
}
inline bool operator == (const dport_out_type &rhs) const {
bool ret = true;
ret = ret
&& rhs.req_ready == req_ready
&& rhs.resp_valid == resp_valid
&& rhs.resp_error == resp_error
&& rhs.rdata == rdata;
return ret;
}
inline dport_out_type& operator = (const dport_out_type &rhs) {
req_ready = rhs.req_ready;
resp_valid = rhs.resp_valid;
resp_error = rhs.resp_error;
rdata = rhs.rdata;
return *this;
}
inline friend void sc_trace(sc_trace_file *tf,
const dport_out_type&v,
const std::string &NAME) {
sc_trace(tf, v.req_ready, NAME + "_req_ready");
sc_trace(tf, v.resp_valid, NAME + "_resp_valid");
sc_trace(tf, v.resp_error, NAME + "_resp_error");
sc_trace(tf, v.rdata, NAME + "_rdata");
}
inline friend ostream &operator << (ostream &os,
dport_out_type const &v) {
os << "("
<< v.req_ready << ","
<< v.resp_valid << ","
<< v.resp_error << ","
<< v.rdata << ")";
return os;
}
public:
bool req_ready; // ready to accept request
bool resp_valid; // rdata is valid
bool resp_error; // response error
sc_uint<RISCV_ARCH> rdata;
};
static const dport_out_type dport_out_none;
typedef sc_vector<sc_signal<dport_in_type>> dport_in_vector;
typedef sc_vector<sc_signal<dport_out_type>> dport_out_vector;
typedef sc_vector<sc_signal<bool>> hart_signal_vector;
typedef sc_vector<sc_signal<sc_uint<IRQ_TOTAL>>> hart_irq_vector;
// L1 AXI interface
class axi4_l1_out_type {
public:
axi4_l1_out_type() {
aw_valid = 0;
aw_bits.addr = 0;
aw_bits.len = 0;
aw_bits.size = 0;
aw_bits.burst = AXI_BURST_INCR;
aw_bits.lock = 0;
aw_bits.cache = 0;
aw_bits.prot = 0;
aw_bits.qos = 0;
aw_bits.region = 0;
aw_id = 0;
aw_user = 0;
w_valid = 0;
w_data = 0;
w_last = 0;
w_strb = 0;
w_user = 0;
b_ready = 0;
ar_valid = 0;
ar_bits.addr = 0;
ar_bits.len = 0;
ar_bits.size = 0;
ar_bits.burst = AXI_BURST_INCR;
ar_bits.lock = 0;
ar_bits.cache = 0;
ar_bits.prot = 0;
ar_bits.qos = 0;
ar_bits.region = 0;
ar_id = 0;
ar_user = 0;
r_ready = 0;
// ACE signals
ar_domain = 0;
ar_snoop = 0;
ar_bar = 0;
aw_domain = 0;
aw_snoop = 0;
aw_bar = 0;
ac_ready = 1;
cr_valid = 1;
cr_resp = 0;
cd_valid = 0;
cd_data = 0;
cd_last = 0;
rack = 0;
wack = 0;
}
axi4_l1_out_type(bool aw_valid_,
axi4_metadata_type aw_bits_,
sc_uint<CFG_CPU_ID_BITS> aw_id_,
sc_uint<CFG_SYSBUS_USER_BITS> aw_user_,
bool w_valid_,
sc_biguint<L1CACHE_LINE_BITS> w_data_,
bool w_last_,
sc_uint<L1CACHE_BYTES_PER_LINE> w_strb_,
sc_uint<CFG_CPU_USER_BITS> w_user_,
bool b_ready_,
bool ar_valid_,
axi4_metadata_type ar_bits_,
sc_uint<CFG_CPU_ID_BITS> ar_id_,
sc_uint<CFG_SYSBUS_USER_BITS> ar_user_,
bool r_ready_,
sc_uint<2> ar_domain_,
sc_uint<4> ar_snoop_,
sc_uint<2> ar_bar_,
sc_uint<2> aw_domain_,
sc_uint<3> aw_snoop_,
sc_uint<2> aw_bar_,
bool ac_ready_,
bool cr_valid_,
sc_uint<5> cr_resp_,
bool cd_valid_,
sc_biguint<L1CACHE_LINE_BITS> cd_data_,
bool cd_last_,
bool rack_,
bool wack_) {
aw_valid = aw_valid_;
aw_bits = aw_bits_;
aw_id = aw_id_;
aw_user = aw_user_;
w_valid = w_valid_;
w_data = w_data_;
w_last = w_last_;
w_strb = w_strb_;
w_user = w_user_;
b_ready = b_ready_;
ar_valid = ar_valid_;
ar_bits = ar_bits_;
ar_id = ar_id_;
ar_user = ar_user_;
r_ready = r_ready_;
ar_domain = ar_domain_;
ar_snoop = ar_snoop_;
ar_bar = ar_bar_;
aw_domain = aw_domain_;
aw_snoop = aw_snoop_;
aw_bar = aw_bar_;
ac_ready = ac_ready_;
cr_valid = cr_valid_;
cr_resp = cr_resp_;
cd_valid = cd_valid_;
cd_data = cd_data_;
cd_last = cd_last_;
rack = rack_;
wack = wack_;
}
inline bool operator == (const axi4_l1_out_type &rhs) const {
bool ret = true;
ret = ret
&& rhs.aw_valid == aw_valid
&& rhs.aw_bits.addr == aw_bits.addr
&& rhs.aw_bits.len == aw_bits.len
&& rhs.aw_bits.size == aw_bits.size
&& rhs.aw_bits.burst == aw_bits.burst
&& rhs.aw_bits.lock == aw_bits.lock
&& rhs.aw_bits.cache == aw_bits.cache
&& rhs.aw_bits.prot == aw_bits.prot
&& rhs.aw_bits.qos == aw_bits.qos
&& rhs.aw_bits.region == aw_bits.region
&& rhs.aw_id == aw_id
&& rhs.aw_user == aw_user
&& rhs.w_valid == w_valid
&& rhs.w_data == w_data
&& rhs.w_last == w_last
&& rhs.w_strb == w_strb
&& rhs.w_user == w_user
&& rhs.b_ready == b_ready
&& rhs.ar_valid == ar_valid
&& rhs.ar_bits.addr == ar_bits.addr
&& rhs.ar_bits.len == ar_bits.len
&& rhs.ar_bits.size == ar_bits.size
&& rhs.ar_bits.burst == ar_bits.burst
&& rhs.ar_bits.lock == ar_bits.lock
&& rhs.ar_bits.cache == ar_bits.cache
&& rhs.ar_bits.prot == ar_bits.prot
&& rhs.ar_bits.qos == ar_bits.qos
&& rhs.ar_bits.region == ar_bits.region
&& rhs.ar_id == ar_id
&& rhs.ar_user == ar_user
&& rhs.r_ready == r_ready
&& rhs.ar_domain == ar_domain
&& rhs.ar_snoop == ar_snoop
&& rhs.ar_bar == ar_bar
&& rhs.aw_domain == aw_domain
&& rhs.aw_snoop == aw_snoop
&& rhs.aw_bar == aw_bar
&& rhs.ac_ready == ac_ready
&& rhs.cr_valid == cr_valid
&& rhs.cr_resp == cr_resp
&& rhs.cd_valid == cd_valid
&& rhs.cd_data == cd_data
&& rhs.cd_last == cd_last
&& rhs.rack == rack
&& rhs.wack == wack;
return ret;
}
inline axi4_l1_out_type& operator = (const axi4_l1_out_type &rhs) {
aw_valid = rhs.aw_valid;
aw_bits.addr = rhs.aw_bits.addr;
aw_bits.len = rhs.aw_bits.len;
aw_bits.size = rhs.aw_bits.size;
aw_bits.burst = rhs.aw_bits.burst;
aw_bits.lock = rhs.aw_bits.lock;
aw_bits.cache = rhs.aw_bits.cache;
aw_bits.prot = rhs.aw_bits.prot;
aw_bits.qos = rhs.aw_bits.qos;
aw_bits.region = rhs.aw_bits.region;
aw_id = rhs.aw_id;
aw_user = rhs.aw_user;
w_valid = rhs.w_valid;
w_data = rhs.w_data;
w_last = rhs.w_last;
w_strb = rhs.w_strb;
w_user = rhs.w_user;
b_ready = rhs.b_ready;
ar_valid = rhs.ar_valid;
ar_bits.addr = rhs.ar_bits.addr;
ar_bits.len = rhs.ar_bits.len;
ar_bits.size = rhs.ar_bits.size;
ar_bits.burst = rhs.ar_bits.burst;
ar_bits.lock = rhs.ar_bits.lock;
ar_bits.cache = rhs.ar_bits.cache;
ar_bits.prot = rhs.ar_bits.prot;
ar_bits.qos = rhs.ar_bits.qos;
ar_bits.region = rhs.ar_bits.region;
ar_id = rhs.ar_id;
ar_user = rhs.ar_user;
r_ready = rhs.r_ready;
ar_domain = rhs.ar_domain;
ar_snoop = rhs.ar_snoop;
ar_bar = rhs.ar_bar;
aw_domain = rhs.aw_domain;
aw_snoop = rhs.aw_snoop;
aw_bar = rhs.aw_bar;
ac_ready = rhs.ac_ready;
cr_valid = rhs.cr_valid;
cr_resp = rhs.cr_resp;
cd_valid = rhs.cd_valid;
cd_data = rhs.cd_data;
cd_last = rhs.cd_last;
rack = rhs.rack;
wack = rhs.wack;
return *this;
}
inline friend void sc_trace(sc_trace_file *tf,
const axi4_l1_out_type&v,
const std::string &NAME) {
sc_trace(tf, v.aw_valid, NAME + "_aw_valid");
sc_trace(tf, v.aw_bits.addr, NAME + "_aw_bits_addr");
sc_trace(tf, v.aw_bits.len, NAME + "_aw_bits_len");
sc_trace(tf, v.aw_bits.size, NAME + "_aw_bits_size");
sc_trace(tf, v.aw_bits.burst, NAME + "_aw_bits_burst");
sc_trace(tf, v.aw_bits.lock, NAME + "_aw_bits_lock");
sc_trace(tf, v.aw_bits.cache, NAME + "_aw_bits_cache");
sc_trace(tf, v.aw_bits.prot, NAME + "_aw_bits_prot");
sc_trace(tf, v.aw_bits.qos, NAME + "_aw_bits_qos");
sc_trace(tf, v.aw_bits.region, NAME + "_aw_bits_region");
sc_trace(tf, v.aw_id, NAME + "_aw_id");
sc_trace(tf, v.aw_user, NAME + "_aw_user");
sc_trace(tf, v.w_valid, NAME + "_w_valid");
sc_trace(tf, v.w_data, NAME + "_w_data");
sc_trace(tf, v.w_last, NAME + "_w_last");
sc_trace(tf, v.w_strb, NAME + "_w_strb");
sc_trace(tf, v.w_user, NAME + "_w_user");
sc_trace(tf, v.b_ready, NAME + "_b_ready");
sc_trace(tf, v.ar_valid, NAME + "_ar_valid");
sc_trace(tf, v.ar_bits.addr, NAME + "_ar_bits_addr");
sc_trace(tf, v.ar_bits.len, NAME + "_ar_bits_len");
sc_trace(tf, v.ar_bits.size, NAME + "_ar_bits_size");
sc_trace(tf, v.ar_bits.burst, NAME + "_ar_bits_burst");
sc_trace(tf, v.ar_bits.lock, NAME + "_ar_bits_lock");
sc_trace(tf, v.ar_bits.cache, NAME + "_ar_bits_cache");
sc_trace(tf, v.ar_bits.prot, NAME + "_ar_bits_prot");
sc_trace(tf, v.ar_bits.qos, NAME + "_ar_bits_qos");
sc_trace(tf, v.ar_bits.region, NAME + "_ar_bits_region");
sc_trace(tf, v.ar_id, NAME + "_ar_id");
sc_trace(tf, v.ar_user, NAME + "_ar_user");
sc_trace(tf, v.r_ready, NAME + "_r_ready");
sc_trace(tf, v.ar_domain, NAME + "_ar_domain");
sc_trace(tf, v.ar_snoop, NAME + "_ar_snoop");
sc_trace(tf, v.ar_bar, NAME + "_ar_bar");
sc_trace(tf, v.aw_domain, NAME + "_aw_domain");
sc_trace(tf, v.aw_snoop, NAME + "_aw_snoop");
sc_trace(tf, v.aw_bar, NAME + "_aw_bar");
sc_trace(tf, v.ac_ready, NAME + "_ac_ready");
sc_trace(tf, v.cr_valid, NAME + "_cr_valid");
sc_trace(tf, v.cr_resp, NAME + "_cr_resp");
sc_trace(tf, v.cd_valid, NAME + "_cd_valid");
sc_trace(tf, v.cd_data, NAME + "_cd_data");
sc_trace(tf, v.cd_last, NAME + "_cd_last");
sc_trace(tf, v.rack, NAME + "_rack");
sc_trace(tf, v.wack, NAME + "_wack");
}
inline friend ostream &operator << (ostream &os,
axi4_l1_out_type const &v) {
os << "("
<< v.aw_valid << ","
<< v.aw_bits.addr << ","
<< v.aw_bits.len << ","
<< v.aw_bits.size << ","
<< v.aw_bits.burst << ","
<< v.aw_bits.lock << ","
<< v.aw_bits.cache << ","
<< v.aw_bits.prot << ","
<< v.aw_bits.qos << ","
<< v.aw_bits.region << ","
<< v.aw_id << ","
<< v.aw_user << ","
<< v.w_valid << ","
<< v.w_data << ","
<< v.w_last << ","
<< v.w_strb << ","
<< v.w_user << ","
<< v.b_ready << ","
<< v.ar_valid << ","
<< v.ar_bits.addr << ","
<< v.ar_bits.len << ","
<< v.ar_bits.size << ","
<< v.ar_bits.burst << ","
<< v.ar_bits.lock << ","
<< v.ar_bits.cache << ","
<< v.ar_bits.prot << ","
<< v.ar_bits.qos << ","
<< v.ar_bits.region << ","
<< v.ar_id << ","
<< v.ar_user << ","
<< v.r_ready << ","
<< v.ar_domain << ","
<< v.ar_snoop << ","
<< v.ar_bar << ","
<< v.aw_domain << ","
<< v.aw_snoop << ","
<< v.aw_bar << ","
<< v.ac_ready << ","
<< v.cr_valid << ","
<< v.cr_resp << ","
<< v.cd_valid << ","
<< v.cd_data << ","
<< v.cd_last << ","
<< v.rack << ","
<< v.wack << ")";
return os;
}
public:
bool aw_valid;
axi4_metadata_type aw_bits;
sc_uint<CFG_CPU_ID_BITS> aw_id;
sc_uint<CFG_SYSBUS_USER_BITS> aw_user;
bool w_valid;
sc_biguint<L1CACHE_LINE_BITS> w_data;
bool w_last;
sc_uint<L1CACHE_BYTES_PER_LINE> w_strb;
sc_uint<CFG_CPU_USER_BITS> w_user;
bool b_ready;
bool ar_valid;
axi4_metadata_type ar_bits;
sc_uint<CFG_CPU_ID_BITS> ar_id;
sc_uint<CFG_SYSBUS_USER_BITS> ar_user;
bool r_ready;
// ACE signals
sc_uint<2> ar_domain; // 00=Non-shareable (single master in domain)
sc_uint<4> ar_snoop; // Table C3-7:
sc_uint<2> ar_bar; // read barrier transaction
sc_uint<2> aw_domain;
sc_uint<3> aw_snoop; // Table C3-8
sc_uint<2> aw_bar; // write barrier transaction
bool ac_ready;
bool cr_valid;
sc_uint<5> cr_resp;
bool cd_valid;
sc_biguint<L1CACHE_LINE_BITS> cd_data;
bool cd_last;
bool rack;
bool wack;
};
static const axi4_l1_out_type axi4_l1_out_none;
class axi4_l1_in_type {
public:
axi4_l1_in_type() {
aw_ready = 0;
w_ready = 0;
b_valid = 0;
b_resp = 0;
b_id = 0;
b_user = 0;
ar_ready = 0;
r_valid = 0;
r_resp = 0;
r_data = 0;
r_last = 0;
r_id = 0;
r_user = 0;
ac_valid = 0;
ac_addr = 0;
ac_snoop = 0;
ac_prot = 0;
cr_ready = 1;
cd_ready = 1;
}
axi4_l1_in_type(bool aw_ready_,
bool w_ready_,
bool b_valid_,
sc_uint<2> b_resp_,
sc_uint<CFG_CPU_ID_BITS> b_id_,
sc_uint<CFG_SYSBUS_USER_BITS> b_user_,
bool ar_ready_,
bool r_valid_,
sc_uint<4> r_resp_,
sc_biguint<L1CACHE_LINE_BITS> r_data_,
bool r_last_,
sc_uint<CFG_CPU_ID_BITS> r_id_,
sc_uint<CFG_SYSBUS_USER_BITS> r_user_,
bool ac_valid_,
sc_uint<CFG_CPU_ADDR_BITS> ac_addr_,
sc_uint<4> ac_snoop_,
sc_uint<3> ac_prot_,
bool cr_ready_,
bool cd_ready_) {
aw_ready = aw_ready_; |
w_ready = w_ready_;
b_valid = b_valid_;
b_resp = b_resp_;
b_id = b_id_;
b_user = b_user_;
ar_ready = ar_ready_;
r_valid = r_valid_;
r_resp = r_resp_;
r_data = r_data_;
r_last = r_last_;
r_id = r_id_;
r_user = r_user_;
ac_valid = ac_valid_;
ac_addr = ac_addr_;
ac_snoop = ac_snoop_;
ac_prot = ac_prot_;
cr_ready = cr_ready_;
cd_ready = cd_ready_;
}
inline bool operator == (const axi4_l1_in_type &rhs) const {
bool ret = true;
ret = ret
&& rhs.aw_ready == aw_ready
&& rhs.w_ready == w_ready
&& rhs.b_valid == b_valid
&& rhs.b_resp == b_resp
&& rhs.b_id == b_id
&& rhs.b_user == b_user
&& rhs.ar_ready == ar_ready
&& rhs.r_valid == r_valid
&& rhs.r_resp == r_resp
&& rhs.r_data == r_data
&& rhs.r_last == r_last
&& rhs.r_id == r_id
&& rhs.r_user == r_user
&& rhs.ac_valid == ac_valid
&& rhs.ac_addr == ac_addr
&& rhs.ac_snoop == ac_snoop
&& rhs.ac_prot == ac_prot
&& rhs.cr_ready == cr_ready
&& rhs.cd_ready == cd_ready;
return ret;
}
inline axi4_l1_in_type& operator = (const axi4_l1_in_type &rhs) {
aw_ready = rhs.aw_ready;
w_ready = rhs.w_ready;
b_valid = rhs.b_valid;
b_resp = rhs.b_resp;
b_id = rhs.b_id;
b_user = rhs.b_user;
ar_ready = rhs.ar_ready;
r_valid = rhs.r_valid;
r_resp = rhs.r_resp;
r_data = rhs.r_data;
r_last = rhs.r_last;
r_id = rhs.r_id;
r_user = rhs.r_user;
ac_valid = rhs.ac_valid;
ac_addr = rhs.ac_addr;
ac_snoop = rhs.ac_snoop;
ac_prot = rhs.ac_prot;
cr_ready = rhs.cr_ready;
cd_ready = rhs.cd_ready;
return *this;
}
inline friend void sc_trace(sc_trace_file *tf,
const axi4_l1_in_type&v,
const std::string &NAME) {
sc_trace(tf, v.aw_ready, NAME + "_aw_ready");
sc_trace(tf, v.w_ready, NAME + "_w_ready");
sc_trace(tf, v.b_valid, NAME + "_b_valid");
sc_trace(tf, v.b_resp, NAME + "_b_resp");
sc_trace(tf, v.b_id, NAME + "_b_id");
sc_trace(tf, v.b_user, NAME + "_b_user");
sc_trace(tf, v.ar_ready, NAME + "_ar_ready");
sc_trace(tf, v.r_valid, NAME + "_r_valid");
sc_trace(tf, v.r_resp, NAME + "_r_resp");
sc_trace(tf, v.r_data, NAME + "_r_data");
sc_trace(tf, v.r_last, NAME + "_r_last");
sc_trace(tf, v.r_id, NAME + "_r_id");
sc_trace(tf, v.r_user, NAME + "_r_user");
sc_trace(tf, v.ac_valid, NAME + "_ac_valid");
sc_trace(tf, v.ac_addr, NAME + "_ac_addr");
sc_trace(tf, v.ac_snoop, NAME + "_ac_snoop");
sc_trace(tf, v.ac_prot, NAME + "_ac_prot");
sc_trace(tf, v.cr_ready, NAME + "_cr_ready");
sc_trace(tf, v.cd_ready, NAME + "_cd_ready");
}
inline friend ostream &operator << (ostream &os,
axi4_l1_in_type const &v) {
os << "("
<< v.aw_ready << ","
<< v.w_ready << ","
<< v.b_valid << ","
<< v.b_resp << ","
<< v.b_id << ","
<< v.b_user << ","
<< v.ar_ready << ","
<< v.r_valid << ","
<< v.r_resp << ","
<< v.r_data << ","
<< v.r_last << ","
<< v.r_id << ","
<< v.r_user << ","
<< v.ac_valid << ","
<< v.ac_addr << ","
<< v.ac_snoop << ","
<< v.ac_prot << ","
<< v.cr_ready << ","
<< v.cd_ready << ")";
return os;
}
public:
bool aw_ready;
bool w_ready;
bool b_valid;
sc_uint<2> b_resp;
sc_uint<CFG_CPU_ID_BITS> b_id;
sc_uint<CFG_SYSBUS_USER_BITS> b_user;
bool ar_ready;
bool r_valid;
sc_uint<4> r_resp;
sc_biguint<L1CACHE_LINE_BITS> r_data;
bool r_last;
sc_uint<CFG_CPU_ID_BITS> r_id;
sc_uint<CFG_SYSBUS_USER_BITS> r_user;
bool ac_valid;
sc_uint<CFG_CPU_ADDR_BITS> ac_addr;
sc_uint<4> ac_snoop; // Table C3-19
sc_uint<3> ac_prot;
bool cr_ready;
bool cd_ready;
};
static const axi4_l1_in_type axi4_l1_in_none;
typedef sc_vector<sc_signal<axi4_l1_in_type>> axi4_l1_in_vector;
typedef sc_vector<sc_signal<axi4_l1_out_type>> axi4_l1_out_vector;
class axi4_l2_out_type {
public:
axi4_l2_out_type() {
aw_valid = 0;
aw_bits.addr = 0;
aw_bits.len = 0;
aw_bits.size = 0;
aw_bits.burst = AXI_BURST_INCR;
aw_bits.lock = 0;
aw_bits.cache = 0;
aw_bits.prot = 0;
aw_bits.qos = 0;
aw_bits.region = 0;
aw_id = 0;
aw_user = 0;
w_valid = 0;
w_data = 0;
w_last = 0;
w_strb = 0;
w_user = 0;
b_ready = 0;
ar_valid = 0;
ar_bits.addr = 0;
ar_bits.len = 0;
ar_bits.size = 0;
ar_bits.burst = AXI_BURST_INCR;
ar_bits.lock = 0;
ar_bits.cache = 0;
ar_bits.prot = 0;
ar_bits.qos = 0;
ar_bits.region = 0;
ar_id = 0;
ar_user = 0;
r_ready = 0;
}
axi4_l2_out_type(bool aw_valid_,
axi4_metadata_type aw_bits_,
sc_uint<CFG_CPU_ID_BITS> aw_id_,
sc_uint<CFG_SYSBUS_USER_BITS> aw_user_,
bool w_valid_,
sc_biguint<L2CACHE_LINE_BITS> w_data_,
bool w_last_,
sc_uint<L2CACHE_BYTES_PER_LINE> w_strb_,
sc_uint<CFG_CPU_USER_BITS> w_user_,
bool b_ready_,
bool ar_valid_,
axi4_metadata_type ar_bits_,
sc_uint<CFG_CPU_ID_BITS> ar_id_,
sc_uint<CFG_SYSBUS_USER_BITS> ar_user_,
bool r_ready_) {
aw_valid = aw_valid_;
aw_bits = aw_bits_;
aw_id = aw_id_;
aw_user = aw_user_;
w_valid = w_valid_;
w_data = w_data_;
w_last = w_last_;
w_strb = w_strb_;
w_user = w_user_;
b_ready = b_ready_;
ar_valid = ar_valid_;
ar_bits = ar_bits_;
ar_id = ar_id_;
ar_user = ar_user_;
r_ready = r_ready_;
}
inline bool operator == (const axi4_l2_out_type &rhs) const {
bool ret = true;
ret = ret
&& rhs.aw_valid == aw_valid
&& rhs.aw_bits.addr == aw_bits.addr
&& rhs.aw_bits.len == aw_bits.len
&& rhs.aw_bits.size == aw_bits.size
&& rhs.aw_bits.burst == aw_bits.burst
&& rhs.aw_bits.lock == aw_bits.lock
&& rhs.aw_bits.cache == aw_bits.cache
&& rhs.aw_bits.prot == aw_bits.prot
&& rhs.aw_bits.qos == aw_bits.qos
&& rhs.aw_bits.region == aw_bits.region
&& rhs.aw_id == aw_id
&& rhs.aw_user == aw_user
&& rhs.w_valid == w_valid
&& rhs.w_data == w_data
&& rhs.w_last == w_last
&& rhs.w_strb == w_strb
&& rhs.w_user == w_user
&& rhs.b_ready == b_ready
&& rhs.ar_valid == ar_valid
&& rhs.ar_bits.addr == ar_bits.addr
&& rhs.ar_bits.len == ar_bits.len
&& rhs.ar_bits.size == ar_bits.size
&& rhs.ar_bits.burst == ar_bits.burst
&& rhs.ar_bits.lock == ar_bits.lock
&& rhs.ar_bits.cache == ar_bits.cache
&& rhs.ar_bits.prot == ar_bits.prot
&& rhs.ar_bits.qos == ar_bits.qos
&& rhs.ar_bits.region == ar_bits.region
&& rhs.ar_id == ar_id
&& rhs.ar_user == ar_user
&& rhs.r_ready == r_ready;
return ret;
}
inline axi4_l2_out_type& operator = (const axi4_l2_out_type &rhs) {
aw_valid = rhs.aw_valid;
aw_bits.addr = rhs.aw_bits.addr;
aw_bits.len = rhs.aw_bits.len;
aw_bits.size = rhs.aw_bits.size;
aw_bits.burst = rhs.aw_bits.burst;
aw_bits.lock = rhs.aw_bits.lock;
aw_bits.cache = rhs.aw_bits.cache;
aw_bits.prot = rhs.aw_bits.prot;
aw_bits.qos = rhs.aw_bits.qos;
aw_bits.region = rhs.aw_bits.region;
aw_id = rhs.aw_id;
aw_user = rhs.aw_user;
w_valid = rhs.w_valid;
w_data = rhs.w_data;
w_last = rhs.w_last;
w_strb = rhs.w_strb;
w_user = rhs.w_user;
b_ready = rhs.b_ready;
ar_valid = rhs.ar_valid;
ar_bits.addr = rhs.ar_bits.addr;
ar_bits.len = rhs.ar_bits.len;
ar_bits.size = rhs.ar_bits.size;
ar_bits.burst = rhs.ar_bits.burst;
ar_bits.lock = rhs.ar_bits.lock;
ar_bits.cache = rhs.ar_bits.cache;
ar_bits.prot = rhs.ar_bits.prot;
ar_bits.qos = rhs.ar_bits.qos;
ar_bits.region = rhs.ar_bits.region;
ar_id = rhs.ar_id;
ar_user = rhs.ar_user;
r_ready = rhs.r_ready;
return *this;
}
inline friend void sc_trace(sc_trace_file *tf,
const axi4_l2_out_type&v,
const std::string &NAME) {
sc_trace(tf, v.aw_valid, NAME + "_aw_valid");
sc_trace(tf, v.aw_bits.addr, NAME + "_aw_bits_addr");
sc_trace(tf, v.aw_bits.len, NAME + "_aw_bits_len");
sc_trace(tf, v.aw_bits.size, NAME + "_aw_bits_size");
sc_trace(tf, v.aw_bits.burst, NAME + "_aw_bits_burst");
sc_trace(tf, v.aw_bits.lock, NAME + "_aw_bits_lock");
sc_trace(tf, v.aw_bits.cache, NAME + "_aw_bits_cache");
sc_trace(tf, v.aw_bits.prot, NAME + "_aw_bits_prot");
sc_trace(tf, v.aw_bits.qos, NAME + "_aw_bits_qos");
sc_trace(tf, v.aw_bits.region, NAME + "_aw_bits_region");
sc_trace(tf, v.aw_id, NAME + "_aw_id");
sc_trace(tf, v.aw_user, NAME + "_aw_user");
sc_trace(tf, v.w_valid, NAME + "_w_valid");
sc_trace(tf, v.w_data, NAME + "_w_data");
sc_trace(tf, v.w_last, NAME + "_w_last");
sc_trace(tf, v.w_strb, NAME + "_w_strb");
sc_trace(tf, v.w_user, NAME + "_w_user");
sc_trace(tf, v.b_ready, NAME + "_b_ready");
sc_trace(tf, v.ar_valid, NAME + "_ar_valid");
sc_trace(tf, v.ar_bits.addr, NAME + "_ar_bits_addr");
sc_trace(tf, v.ar_bits.len, NAME + "_ar_bits_len");
sc_trace(tf, v.ar_bits.size, NAME + "_ar_bits_size");
sc_trace(tf, v.ar_bits.burst, NAME + "_ar_bits_burst");
sc_trace(tf, v.ar_bits.lock, NAME + "_ar_bits_lock");
sc_trace(tf, v.ar_bits.cache, NAME + "_ar_bits_cache");
sc_trace(tf, v.ar_bits.prot, NAME + "_ar_bits_prot");
sc_trace(tf, v.ar_bits.qos, NAME + "_ar_bits_qos");
sc_trace(tf, v.ar_bits.region, NAME + "_ar_bits_region");
sc_trace(tf, v.ar_id, NAME + "_ar_id");
sc_trace(tf, v.ar_user, NAME + "_ar_user");
sc_trace(tf, v.r_ready, NAME + "_r_ready");
}
inline friend ostream &operator << (ostream &os,
axi4_l2_out_type const &v) {
os << "("
<< v.aw_valid << ","
<< v.aw_bits.addr << ","
<< v.aw_bits.len << ","
<< v.aw_bits.size << ","
<< v.aw_bits.burst << ","
<< v.aw_bits.lock << ","
<< v.aw_bits.cache << ","
<< v.aw_bits.prot << ","
<< v.aw_bits.qos << ","
<< v.aw_bits.region << ","
<< v.aw_id << ","
<< v.aw_user << ","
<< v.w_valid << ","
<< v.w_data << ","
<< v.w_last << ","
<< v.w_strb << ","
<< v.w_user << ","
<< v.b_ready << ","
<< v.ar_valid << ","
<< v.ar_bits.addr << ","
<< v.ar_bits.len << ","
<< v.ar_bits.size << ","
<< v.ar_bits.burst << ","
<< v.ar_bits.lock << ","
<< v.ar_bits.cache << ","
<< v.ar_bits.prot << ","
<< v.ar_bits.qos << ","
<< v.ar_bits.region << ","
<< v.ar_id << ","
<< v.ar_user << ","
<< v.r_ready << ")";
return os;
}
public:
bool aw_valid;
axi4_metadata_type aw_bits;
sc_uint<CFG_CPU_ID_BITS> aw_id;
sc_uint<CFG_SYSBUS_USER_BITS> aw_user;
bool w_valid;
sc_biguint<L2CACHE_LINE_BITS> w_data;
bool w_last;
sc_uint<L2CACHE_BYTES_PER_LINE> w_strb;
sc_uint<CFG_CPU_USER_BITS> w_user;
bool b_ready;
bool ar_valid;
axi4_metadata_type ar_bits;
sc_uint<CFG_CPU_ID_BITS> ar_id;
sc_uint<CFG_SYSBUS_USER_BITS> ar_user;
bool r_ready;
};
static const axi4_l2_out_type axi4_l2_out_none;
class axi4_l2_in_type {
public:
axi4_l2_in_type() {
aw_ready = 0;
w_ready = 0;
b_valid = 0;
b_resp = 0;
b_id = 0;
b_user = 0;
ar_ready = 0;
r_valid = 0;
r_resp = 0;
r_data = 0;
r_last = 0;
r_id = 0;
r_user = 0;
}
axi4_l2_in_type(bool aw_ready_,
bool w_ready_,
bool b_valid_,
sc_uint<2> b_resp_,
sc_uint<CFG_CPU_ID_BITS> b_id_,
sc_uint<CFG_SYSBUS_USER_BITS> b_user_,
bool ar_ready_,
bool r_valid_,
sc_uint<2> r_resp_,
sc_biguint<L2CACHE_LINE_BITS> r_data_,
bool r_last_,
sc_uint<CFG_CPU_ID_BITS> r_id_,
sc_uint<CFG_SYSBUS_USER_BITS> r_user_) {
aw_ready = aw_ready_;
w_ready = w_ready_;
b_valid = b_valid_;
b_resp = b_resp_;
b_id = b_id_;
b_user = b_user_;
ar_ready = ar_ready_;
r_valid = r_valid_;
r_resp = r_resp_;
r_data = r_data_;
r_last = r_last_;
r_id = r_id_;
r_user = r_user_;
}
inline bool operator == (const axi4_l2_in_type &rhs) const {
bool ret = true;
ret = ret
&& rhs.aw_ready == aw_ready
&& rhs.w_ready == w_ready
&& rhs.b_valid == b_valid
&& rhs.b_resp == b_resp
&& rhs.b_id == b_id
&& rhs.b_user == b_user
&& rhs.ar_ready == ar_ready
&& rhs.r_valid == r_valid
&& rhs.r_resp == r_resp
&& rhs.r_data == r_data
&& rhs.r_last == r_last
&& rhs.r_id == r_id
&& rhs.r_user == r_user;
return ret;
}
inline axi4_l2_in_type& operator = (const axi4_l2_in_type &rhs) {
aw_ready = rhs.aw_ready;
w_ready = rhs.w_ready;
b_valid = rhs.b_valid;
b_resp = rhs.b_resp;
b_id = rhs.b_id;
b_user = rhs.b_user;
ar_ready = rhs.ar_ready;
r_valid = rhs.r_valid;
r_resp = rhs.r_resp;
r_data = rhs.r_data;
r_last = rhs.r_last;
r_id = rhs.r_id;
r_user = rhs.r_user;
return *this;
}
inline friend void sc_trace(sc_trace_file *tf,
const axi4_l2_in_type&v,
const std::string &NAME) {
sc_trace(tf, v.aw_ready, NAME + "_aw_ready");
sc_trace(tf, v.w_ready, NAME + "_w_ready");
sc_trace(tf, v.b_valid, NAME + "_b_valid");
sc_trace(tf, v.b_resp, NAME + "_b_resp");
sc_trace(tf, v.b_id, NAME + "_b_id");
sc_trace(tf, v.b_user, NAME + "_b_user");
sc_trace(tf, v.ar_ready, NAME + "_ar_ready");
sc_trace(tf, v.r_valid, NAME + "_r_valid");
sc_trace(tf, v.r_resp, NAME + "_r_resp");
sc_trace(tf, v.r_data, NAME + "_r_data");
sc_trace(tf, v.r_last, NAME + "_r_last");
sc_trace(tf, v.r_id, NAME + "_r_id");
sc_trace(tf, v.r_user, NAME + "_r_user");
}
inline friend ostream &operator << (ostream &os,
axi4_l2_in_type const &v) {
os << "("
<< v.aw_ready << ","
<< v.w_ready << ","
<< v.b_valid << ","
<< v.b_resp << ","
<< v.b_id << ","
<< v.b_user << ","
<< v.ar_ready << ","
<< v.r_valid << ","
<< v.r_resp << ","
<< v.r_data << ","
<< v.r_last << ","
<< v.r_id << ","
<< v.r_user << ")";
return os;
}
public:
bool aw_ready;
bool w_ready;
bool b_valid;
sc_uint<2> b_resp;
sc_uint<CFG_CPU_ID_BITS> b_id; // create ID for L2?
sc_uint<CFG_SYSBUS_USER_BITS> b_user;
bool ar_ready;
bool r_valid;
sc_uint<2> r_resp;
sc_biguint<L2CACHE_LINE_BITS> r_data;
bool r_last;
sc_uint<CFG_CPU_ID_BITS> r_id;
sc_uint<CFG_SYSBUS_USER_BITS> r_user;
};
static const axi4_l2_in_type axi4_l2_in_none;
} // namespace debugger
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2017 Cadence Design Systems, Inc. All rights reserved worldwide.
//
// The code contained herein is the proprietary and confidential information
// of Cadence or its licensors, and is supplied subject to a previously
// executed license and maintenance agreement between Cadence and customer.
// This code is intended for use with Cadence high-level synthesis tools and
// may not be used with other high-level synthesis tools. Permission is only
// granted to distribute the code as indicated. Cadence grants permission for
// customer to distribute a copy of this code to any partner to aid in designing
// or verifying the customer's intellectual property, as long as such
// distribution includes a restriction of no additional distributions from the
// partner, unless the partner receives permission directly from Cadence.
//
// ALL CODE FURNISHED BY CADENCE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY
// KIND, AND CADENCE SPECIFICALLY DISCLAIMS ANY WARRANTY OF NONINFRINGEMENT,
// FITNESS FOR A PARTICULAR PURPOSE OR MERCHANTABILITY. CADENCE SHALL NOT BE
// LIABLE FOR ANY COSTS OF PROCUREMENT OF SUBSTITUTES, LOSS OF PROFITS,
// INTERRUPTION OF BUSINESS, OR FOR ANY OTHER SPECIAL, CONSEQUENTIAL OR
// INCIDENTAL DAMAGES, HOWEVER CAUSED, WHETHER FOR BREACH OF WARRANTY,
// CONTRACT, TORT, NEGLIGENCE, STRICT LIABILITY OR OTHERWISE.
//
////////////////////////////////////////////////////////////////////////////////
#ifndef SYSTEM_H
#define SYSTEM_H
/* This file defines the module "System", which is the top-level
module in the simulation. See the file main.cc, which shows how a
SystemC simulation is created and run. */
/* Include some required files. */
#include <systemc.h> /* SystemC definitions. */
#include <esc.h> /* Cadence ESC functions and utilities. */
#include <stratus_hls.h> /* Cadence Stratus definitions. */
#include <cynw_p2p.h> /* The cynw_p2p communication channel. */
/* Include the local header files that define the modules to be instantiated. */
#include "tb.h" /* The testbench module. */
#include "dut_wrap.h" /* The DUT module. Need dut_wrap.h, not dut.h. */
SC_MODULE( System )
{
public:
/* Instantiated sub-modules. We instantiate the dut_wrapper module,
rather than the dut module directly. This is because the dut
module can exist in multiple versions (such as behavioral and
synthesized RTL), and the wrapper module automatically selects
between the versions based on the simulation configuration. */
dut_wrapper DUT;
tb TB;
sc_clock clk_sig;
sc_signal< bool > rst_sig;
cynw_p2p< input_t > chan1; /* TB to DUT, using struct input_t. */
cynw_p2p< output_t > chan2; /* DUT to TB, using type output_t. */
SC_CTOR( System )
: clk_sig( "clk_sig", CLOCK_PERIOD, SC_NS )
, rst_sig( "rst_sig" )
, TB( "TB" )
, chan1( "chan1" )
, DUT( "DUT" )
, chan2( "chan2" )
{
TB.clk( clk_sig );
TB.rst_out( rst_sig );
DUT.clk( clk_sig );
DUT.rst( rst_sig );
TB.dout( chan1 );
DUT.din( chan1 );
DUT.dout( chan2 );
TB.din( chan2 );
}
};
#endif /* SYSTEM_H */
|
/*
* Copyright (c) 2019 Sekhar Bhattacharya
*
* SPDX-License-Identifier: MIT
*/
#include <systemc.h>
#include "utils.h"
template <int sram_size>
SC_MODULE(Sram) {
sc_in<uint32_t> i_sram_addr;
sc_in<uint32_t> i_sram_dq;
sc_out<uint32_t> o_sram_dq;
sc_in<bool> i_sram_ce_n;
sc_in<bool> i_sram_we_n;
sc_in<bool> i_sram_oe_n;
sc_in<bool> i_sram_ub_n;
sc_in<bool> i_sram_lb_n;
SC_CTOR(Sram) {
SC_METHOD(process);
sensitive << i_sram_addr << i_sram_dq << i_sram_we_n << i_sram_ce_n << i_sram_oe_n << i_sram_ub_n << i_sram_lb_n;
m_sram = new uint16_t[sram_size >> 1];
dont_initialize();
}
void trace_all(sc_trace_file *tf, const std::string& parent_name);
void load_hex(const std::string& filename);
void load_bin(const std::string& filename);
void dump_mem(procyon::utils::dump_format_t group_fmt = procyon::utils::DUMP_FORMAT_4B, procyon::utils::dump_format_t line_fmt = procyon::utils::DUMP_FORMAT_16B);
~Sram();
private:
uint16_t* m_sram;
void process();
};
template <int sram_size>
Sram<sram_size>::~Sram() {
if (m_sram != NULL) delete m_sram;
}
template <int sram_size>
void Sram<sram_size>::trace_all(sc_trace_file *tf, const std::string& parent_name) {
const std::string module_name = parent_name+"."+name();
sc_trace(tf, i_sram_addr, module_name+".i_sram_addr");
sc_trace(tf, i_sram_dq, module_name+".i_sram_dq");
sc_trace(tf, o_sram_dq, module_name+".o_sram_dq");
sc_trace(tf, i_sram_ce_n, module_name+".i_sram_ce_n");
sc_trace(tf, i_sram_we_n, module_name+".i_sram_we_n");
sc_trace(tf, i_sram_oe_n, module_name+".i_sram_oe_n");
sc_trace(tf, i_sram_ub_n, module_name+".i_sram_ub_n");
sc_trace(tf, i_sram_lb_n, module_name+".i_sram_lb_n");
}
template <int sram_size>
void Sram<sram_size>::process() {
uint32_t addr = i_sram_addr.read();
bool we_n = i_sram_we_n.read();
uint8_t sram_lb = i_sram_lb_n.read() ? 0 : m_sram[addr] & 0xff;
uint8_t sram_ub = i_sram_ub_n.read() ? 0 : (m_sram[addr] >> 8) & 0xff;
o_sram_dq.write((sram_ub << 8) | sram_lb);
if (!we_n) {
uint16_t data_in = i_sram_dq.read();
sram_lb = i_sram_lb_n.read() ? m_sram[addr] & 0xff : data_in & 0xff;
sram_ub = i_sram_ub_n.read() ? (m_sram[addr] >> 8) & 0xff : (data_in >> 8) & 0xff;
m_sram[addr] = (sram_ub << 8) | sram_lb;
}
}
template <int sram_size>
void Sram<sram_size>::load_hex(const std::string& filename) {
procyon::utils::load_hex(filename, (uint8_t*)m_sram, sram_size);
}
template <int sram_size>
void Sram<sram_size>::load_bin(const std::string& filename) {
procyon::utils::load_bin(filename, (uint8_t*)m_sram, sram_size);
}
template <int sram_size>
void Sram<sram_size>::dump_mem(procyon::utils::dump_format_t group_fmt, procyon::utils::dump_format_t line_fmt) {
procyon::utils::dump_mem((uint8_t*)m_sram, sram_size, group_fmt, line_fmt);
}
|
/****************************************************************************
*
* Copyright (c) 2015, Cadence Design Systems. All Rights Reserved.
*
* This file contains confidential information that may not be
* distributed under any circumstances without the written permision
* of Cadence Design Systems.
*
****************************************************************************/
/****************************************************************************
*
* This file contains the dut_type_wrapper module
* for use in the verilog verification wrapper dut_vlwrapper.v
* It creats an instance of the dut module and has threads
* for converting the BEH ports to RTL level ports on the wrapper.
*
****************************************************************************/
#ifndef _DUT_TYPE_WRAP_INCLUDED_
#define _DUT_TYPE_WRAP_INCLUDED_
#if !defined(ioConfig_TLM) && !defined(ioConfig_PIN)
#if defined(_p_ioConfig_TLM)
#define ioConfig_TLM 1
#endif
#if defined(_p_ioConfig_PIN)
#define ioConfig_PIN 1
#endif
#endif
#include <systemc.h>
#include "dut.h"
// Declaration of wrapper with RTL level ports
SC_MODULE(dut_type_wrapper)
{
public:
#if defined ( ioConfig_TLM )
sc_in< bool > clk;
sc_in< bool > rst;
#else
sc_in< bool > clk;
sc_in< bool > rst;
#endif
// These signals are used to connect structured ports or ports that need
// type conversion to the RTL ports.
#if defined ( ioConfig_TLM )
#else
#endif
// create the netlist
void InitInstances();
void InitThreads();
// delete the netlist
void DeleteInstances();
// The following threads are used to connect structured ports to the actual
// RTL ports.
#if defined ( ioConfig_TLM )
#else
#endif
SC_HAS_PROCESS(dut_type_wrapper);
dut_type_wrapper( sc_module_name name = sc_module_name( sc_gen_unique_name("dut")) )
: sc_module(name)
#if defined ( ioConfig_TLM )
,clk("clk")
,rst("rst")
#else
,clk("clk")
,rst("rst")
#endif
,dut0(0)
{
InitInstances();
InitThreads();
end_module();
}
// destructor
~dut_type_wrapper()
{
DeleteInstances();
}
protected:
dut* dut0;
};
#endif /* */
|
#ifndef IPS_VGA_TLM_HPP
#define IPS_VGA_TLM_HPP
#include <systemc.h>
using namespace sc_core;
using namespace sc_dt;
using namespace std;
#include <tlm.h>
#include <tlm_utils/simple_initiator_socket.h>
#include <tlm_utils/simple_target_socket.h>
#include <tlm_utils/peq_with_cb_and_phase.h>
#include "common_func.hpp"
#include "important_defines.hpp"
#include "vga.hpp"
#include "../src/img_target.cpp"
// Extended Unification TLM
struct vga_tlm
: public vga<
IPS_BITS,
IPS_H_ACTIVE, IPS_H_FP, IPS_H_SYNC_PULSE, IPS_H_BP,
IPS_V_ACTIVE, IPS_V_FP, IPS_V_SYNC_PULSE, IPS_V_BP
>, public img_target
{
protected:
unsigned char* tmp_img;
public:
vga_tlm(sc_module_name name, bool use_prints_)
: vga<
IPS_BITS,
IPS_H_ACTIVE, IPS_H_FP, IPS_H_SYNC_PULSE, IPS_H_BP,
IPS_V_ACTIVE, IPS_V_FP, IPS_V_SYNC_PULSE, IPS_V_BP>((std::string(name) + "_HW_block").c_str()),
img_target((std::string(name) + "_target").c_str())
{
this->use_prints = use_prints_;
checkprintenableimgtar(use_prints);
set_mem_attributes(IMG_INPUT_ADDRESS_LO, IMG_INPUT_SIZE+IMG_INPUT_START_SIZE+IMG_INPUT_DONE_SIZE);
}
// Override do_when_transaction functions
virtual void do_when_read_transaction(unsigned char *&data, unsigned int data_length, sc_dt::uint64 address);
virtual void do_when_write_transaction(unsigned char *&data, unsigned int data_length, sc_dt::uint64 address);
//Backdoor access to memory
void backdoor_write(unsigned char*&data, unsigned int data_length, sc_dt::uint64 address);
void backdoor_read(unsigned char*&data, unsigned int data_length, sc_dt::uint64 address);
unsigned char *return_mem_ptr();
};
#endif // IPS_VGA_TLM_HPP
|
/*
* memoria.h
*
* Created on: 14 de mai de 2017
* Author: drcfts
*/
#ifndef MEMORIA_H_
#define MEMORIA_H_
#include <systemc.h>
#include "mem_if.h"
#include "shared.h"
using namespace std;
//Implementacao da interface de memoria, para se conectar
//com os modulos do RISC-V
struct mem : public sc_module, public mem_if {
int32_t read(const unsigned adress);
int32_t lw(const unsigned address, int32_t constante);
int32_t lh(const unsigned address, int32_t constante);
int32_t lhu(const unsigned address, int32_t constante);
int32_t lb(const unsigned address, int32_t constante);
int32_t lbu(const unsigned address, int32_t constante);
void sw(const unsigned address, int32_t constante, int32_t dado);
void sh(const unsigned address, int32_t constante, int32_t dado);
void sb(const unsigned address, int32_t constante, int32_t dado);
void write_mem(const unsigned address, int32_t data);
void dump_mem(int inicio, int fim, char formato);
SC_CTOR(mem){
mem_ptr = new int32_t[MAX_MEM];
}
private:
int32_t *mem_ptr;
};
/****************************
* ENDEREÇO VAI TER 32 BITS *
****************************
* 32 bits -------------------
* 2 bits-- de dados(coluna) -
* 20 bits-- tag -
* 10 bits indica a linha -
* ---------------------------
* O TAMANHO DA CACHE VAI SER 1024 = 2¹⁰
* -------------------------
* Matriz da memória de cache
* bit de validade - 0 ou 1 -> indicando se foi preenchida ou nao
* Tag -> uma parte do endereço para verificar se é aquele endereço mesmo
* Dados -> é onde vai conter os dados como a memória é de 4K, vai ter um vetor
* 4dados
* **************************************************************
*
* typedef struct{
bool validade;
uint32_t tag_cache;
int dados[4];
uint32_t palavra_coluna;
uint32_t linha_endereco_cache;
}mem_cache;
*
*
*decode_mem(endereco){
palavra_coluna = (endereco) & 0x3;
tag_cache = (endereco >> 12) & 0xFFFFF;
linha_endereco_cache = (endereco >> 2) & 0x3FF;
}
*/
#endif /* MEMORIA_H_ */
|
//
// Copyright 2022 Sergey Khabarov, [email protected]
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
#pragma once
#include <systemc.h>
namespace debugger {
SC_MODULE(vip_uart_receiver) {
public:
sc_in<bool> i_nrst;
sc_in<bool> i_clk;
sc_in<bool> i_rx;
sc_out<bool> o_rdy;
sc_in<bool> i_rdy_clr;
sc_out<sc_uint<8>> o_data;
void comb();
void registers();
SC_HAS_PROCESS(vip_uart_receiver);
vip_uart_receiver(sc_module_name name,
bool async_reset,
int scaler);
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
bool async_reset_;
int scaler_;
int scaler_max;
int scaler_mid;
static const uint8_t startbit = 0;
static const uint8_t data = 1;
static const uint8_t stopbit = 2;
static const uint8_t dummy = 3;
struct vip_uart_receiver_registers {
sc_signal<bool> rx;
sc_signal<sc_uint<2>> state;
sc_signal<bool> rdy;
sc_signal<sc_uint<8>> rdata;
sc_signal<sc_uint<32>> sample;
sc_signal<sc_uint<4>> bitpos;
sc_signal<sc_uint<8>> scratch;
sc_signal<bool> rx_err;
} v, r;
void vip_uart_receiver_r_reset(vip_uart_receiver_registers &iv) {
iv.rx = 0;
iv.state = startbit;
iv.rdy = 0;
iv.rdata = 0;
iv.sample = 0;
iv.bitpos = 0;
iv.scratch = 0;
iv.rx_err = 0;
}
};
} // namespace debugger
|
/* Copyright 2017 Columbia University, SLD Group */
//
// system.h - Robert Margelli
// Top-level model header file.
// Instantiates the CPU, TB, IMEM, DMEM.
//
#ifndef SYSTEM_H_INCLUDED
#define SYSTEM_H_INCLUDED
#include <systemc.h>
#include "cynw_flex_channels.h"
#include "hl5_datatypes.hpp"
#include "defines.hpp"
#include "globals.hpp"
#include "hl5_wrap.h"
#include "tb.hpp"
SC_MODULE(TOP)
{
public:
// Clock and reset
sc_in<bool> clk;
sc_in<bool> rst;
// End of simulation signal.
sc_signal < bool > program_end;
// Fetch enable signal.
sc_signal < bool > fetch_en;
// CPU Reset
sc_signal < bool > cpu_rst;
// Entry point
sc_signal < unsigned > entry_point;
// TODO: removeme
// sc_signal < bool > main_start;
// sc_signal < bool > main_end;
// Instruction counters
sc_signal < long int > icount;
sc_signal < long int > j_icount;
sc_signal < long int > b_icount;
sc_signal < long int > m_icount;
sc_signal < long int > o_icount;
// Cache modeled as arryas
sc_uint<XLEN> imem[ICACHE_SIZE];
sc_uint<XLEN> dmem[DCACHE_SIZE];
/* The testbench, DUT, IMEM and DMEM modules. */
tb *m_tb;
hl5_wrapper *m_dut;
SC_CTOR(TOP)
: clk("clk")
, rst("rst")
, program_end("program_end")
, fetch_en("fetch_en")
, cpu_rst("cpu_rst")
, entry_point("entry_point")
{
m_tb = new tb("tb", imem, dmem);
m_dut = new hl5_wrapper("dut", imem, dmem);
// Connect the design module
m_dut->clk(clk);
m_dut->rst(cpu_rst);
m_dut->entry_point(entry_point);
m_dut->program_end(program_end);
m_dut->fetch_en(fetch_en);
// m_dut->main_start(main_start);
// m_dut->main_end(main_end);
m_dut->icount(icount);
m_dut->j_icount(j_icount);
m_dut->b_icount(b_icount);
m_dut->m_icount(m_icount);
m_dut->o_icount(o_icount);
// Connect the testbench
m_tb->clk(clk);
m_tb->rst(rst);
m_tb->cpu_rst(cpu_rst);
m_tb->entry_point(entry_point);
m_tb->program_end(program_end);
m_tb->fetch_en(fetch_en);
// m_tb->main_start(main_start);
// m_tb->main_end(main_end);
m_tb->icount(icount);
m_tb->j_icount(j_icount);
m_tb->b_icount(b_icount);
m_tb->m_icount(m_icount);
m_tb->o_icount(o_icount);
}
~TOP()
{
delete m_tb;
delete m_dut;
delete imem;
delete dmem;
}
};
#endif // SYSTEM_H_INCLUDED
|
//
// Copyright 2022 Sergey Khabarov, [email protected]
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
#pragma once
#include <systemc.h>
#include "../../ambalib/types_amba.h"
namespace debugger {
SC_MODULE(cdc_axi_sync_tech) {
public:
sc_in<bool> i_xslv_clk; // system clock
sc_in<bool> i_xslv_nrst; // system reset
sc_in<axi4_slave_in_type> i_xslvi; // system clock
sc_out<axi4_slave_out_type> o_xslvo; // system clock
sc_in<bool> i_xmst_clk; // ddr clock
sc_in<bool> i_xmst_nrst; // ddr reset
sc_out<axi4_slave_in_type> o_xmsto; // ddr clock
sc_in<axi4_slave_out_type> i_xmsti; // ddr clock
void comb();
SC_HAS_PROCESS(cdc_axi_sync_tech);
cdc_axi_sync_tech(sc_module_name name);
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
};
} // namespace debugger
|
//
// Copyright 2022 Sergey Khabarov, [email protected]
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
#pragma once
#include <systemc.h>
#include "sdctrl_cfg.h"
#include "../riverlib/cache/tagmem.h"
namespace debugger {
SC_MODULE(sdctrl_cache) {
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
// Data path:
sc_in<bool> i_req_valid;
sc_in<bool> i_req_write;
sc_in<sc_uint<CFG_SDCACHE_ADDR_BITS>> i_req_addr;
sc_in<sc_uint<64>> i_req_wdata;
sc_in<sc_uint<8>> i_req_wstrb;
sc_out<bool> o_req_ready;
sc_out<bool> o_resp_valid;
sc_out<sc_uint<64>> o_resp_data;
sc_out<bool> o_resp_err;
sc_in<bool> i_resp_ready;
// Memory interface:
sc_in<bool> i_req_mem_ready;
sc_out<bool> o_req_mem_valid;
sc_out<bool> o_req_mem_write;
sc_out<sc_uint<CFG_SDCACHE_ADDR_BITS>> o_req_mem_addr;
sc_out<sc_biguint<SDCACHE_LINE_BITS>> o_req_mem_data;
sc_in<bool> i_mem_data_valid;
sc_in<sc_biguint<SDCACHE_LINE_BITS>> i_mem_data;
sc_in<bool> i_mem_fault;
// Debug interface
sc_in<bool> i_flush_valid;
sc_out<bool> o_flush_end;
void comb();
void registers();
SC_HAS_PROCESS(sdctrl_cache);
sdctrl_cache(sc_module_name name,
bool async_reset);
virtual ~sdctrl_cache();
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
bool async_reset_;
static const int abus = CFG_SDCACHE_ADDR_BITS;
static const int ibits = CFG_LOG2_SDCACHE_LINEBITS;
static const int lnbits = CFG_LOG2_SDCACHE_BYTES_PER_LINE;
static const int flbits = SDCACHE_FL_TOTAL;
// State machine states:
static const uint8_t State_Idle = 0;
static const uint8_t State_CheckHit = 2;
static const uint8_t State_TranslateAddress = 3;
static const uint8_t State_WaitGrant = 4;
static const uint8_t State_WaitResp = 5;
static const uint8_t State_CheckResp = 6;
static const uint8_t State_SetupReadAdr = 1;
static const uint8_t State_WriteBus = 7;
static const uint8_t State_FlushAddr = 8;
static const uint8_t State_FlushCheck = 9;
static const uint8_t State_Reset = 10;
static const uint8_t State_ResetWrite = 11;
static const uint64_t LINE_BYTES_MASK = ((1 << CFG_LOG2_SDCACHE_BYTES_PER_LINE) - 1);
static const uint32_t FLUSH_ALL_VALUE = ((1 << ibits) - 1);
struct sdctrl_cache_registers {
sc_signal<bool> req_write;
sc_signal<sc_uint<CFG_SDCACHE_ADDR_BITS>> req_addr;
sc_signal<sc_uint<64>> req_wdata;
sc_signal<sc_uint<8>> req_wstrb;
sc_signal<sc_uint<4>> state;
sc_signal<bool> req_mem_valid;
sc_signal<bool> req_mem_write;
sc_signal<sc_uint<CFG_SDCACHE_ADDR_BITS>> mem_addr;
sc_signal<bool> mem_fault;
sc_signal<bool> write_first;
sc_signal<bool> write_flush;
sc_signal<bool> req_flush;
sc_signal<sc_uint<32>> flush_cnt;
sc_signal<sc_uint<CFG_SDCACHE_ADDR_BITS>> line_addr_i;
sc_signal<sc_biguint<SDCACHE_LINE_BITS>> cache_line_i;
sc_signal<sc_biguint<SDCACHE_LINE_BITS>> cache_line_o;
} v, r;
void sdctrl_cache_r_reset(sdctrl_cache_registers &iv) {
iv.req_write = 0;
iv.req_addr = 0;
iv.req_wdata = 0;
iv.req_wstrb = 0;
iv.state = State_Reset;
iv.req_mem_valid = 0;
iv.req_mem_write = 0;
iv.mem_addr = 0;
iv.mem_fault = 0;
iv.write_first = 0;
iv.write_flush = 0;
iv.req_flush = 0;
iv.flush_cnt = 0;
iv.line_addr_i = 0;
iv.cache_line_i = 0;
iv.cache_line_o = 0;
}
sc_signal<sc_biguint<SDCACHE_LINE_BITS>> line_wdata_i;
sc_signal<sc_uint<SDCACHE_BYTES_PER_LINE>> line_wstrb_i;
sc_signal<sc_uint<SDCACHE_FL_TOTAL>> line_wflags_i;
sc_signal<sc_uint<CFG_SDCACHE_ADDR_BITS>> line_raddr_o;
sc_signal<sc_biguint<SDCACHE_LINE_BITS>> line_rdata_o;
sc_signal<sc_uint<SDCACHE_FL_TOTAL>> line_rflags_o;
sc_signal<bool> line_hit_o;
// Snoop signals:
sc_signal<sc_uint<CFG_SDCACHE_ADDR_BITS>> line_snoop_addr_i;
sc_signal<sc_uint<SDCACHE_FL_TOTAL>> line_snoop_flags_o;
TagMem<abus, ibits, lnbits, flbits, 0> *mem0;
};
} // namespace debugger
|
/*******************************************************************************
* <DIRNAME>test.cpp -- Copyright 2019 (c) Glenn Ramalho - RFIDo Design
*******************************************************************************
* Description:
* This is the main testbench for the <DIRNAME>.ino test.
*******************************************************************************
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
#include <systemc.h>
#include "<DIRNAME>test.h"
#include <string>
#include <vector>
#include "info.h"
<IFESPIDF>#include "main.h"
/**********************
* Function: trace()
* inputs: trace file
* outputs: none
* return: none
* globals: none
*
* Traces all signals in the design. For a signal to be traced it must be listed
* here. This function should also call tracing in any subblocks, if desired.
*/
void <DIRNAME>test::trace(sc_trace_file *tf) {
sc_trace(tf, led, led.name());
sc_trace(tf, rx, rx.name());
sc_trace(tf, tx, tx.name());
i_esp.trace(tf);
}
/**********************
* Task: start_of_simulation():
* inputs: none
* outputs: none
* return: none
* globals: none
*
* Runs commands at the beginning of the simulation.
*/
void <DIRNAME>test::start_of_simulation() {
/* We add a deadtime to the uart client as the ESP sends a glitch down the
* UART0 at power-up.
*/
i_uartclient.i_uart.set_deadtime(sc_time(5, SC_US));
}
/**********************
* Task: serflush():
* inputs: none
* outputs: none
* return: none
* globals: none
*
* Dumps everything comming from the serial interface.
*/
void <DIRNAME>test::serflush() {
//i_uartclient.i_uart.set_debug(true);
i_uartclient.dump();
}
/*******************************************************************************
** Testbenches *****************************************************************
*******************************************************************************/
void <DIRNAME>test::t0(void) {
SC_REPORT_INFO("TEST", "Running Test T0.");
wait(1, SC_MS); sc_stop();
PRINTF_INFO("TEST", "Waiting for power-up");
wait(500, SC_MS);
}
void <DIRNAME>test::testbench(void) {
/* Now we check the test case and run the correct TB. */
printf("Starting Testbench Test%d @%s\n", tn,
sc_time_stamp().to_string().c_str());
if (tn == 0) t0();
else SC_REPORT_ERROR("TEST", "Test number too large.");
sc_stop();
}
|
/*
* Copyright 2018 Sergey Khabarov, [email protected]
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* @details Use the following targets attributes to generate trace files:
* GenerateRef - Generate memory and registers write accesses
* trace files to compare them with functional model
* InVcdFile - Stimulus VCD file
* OutVcdFile - Reference VCD file with any number of signals
*
* @note When GenerateRef is true Core uses step counter instead
* of clock counter to generate callbacks.
*/
#ifndef __DEBUGGER_CPU_RISCV_RTL_H__
#define __DEBUGGER_CPU_RISCV_RTL_H__
#include "iclass.h"
#include "iservice.h"
#include "ihap.h"
#include "async_tqueue.h"
#include "coreservices/ithread.h"
#include "coreservices/icpuriscv.h"
#include "coreservices/imemop.h"
#include "coreservices/iclock.h"
#include "coreservices/icmdexec.h"
#include "coreservices/itap.h"
#include "cmds/cmd_br_riscv.h"
#include "cmds/cmd_reg_riscv.h"
#include "cmds/cmd_regs_riscv.h"
#include "cmds/cmd_csr.h"
#include "rtl_wrapper.h"
#include "riverlib/river_top.h"
#include <systemc.h>
namespace debugger {
class CpuRiscV_RTL : public IService,
public IThread,
public IClock,
public IHap {
public:
CpuRiscV_RTL(const char *name);
virtual ~CpuRiscV_RTL();
/** IService interface */
virtual void postinitService();
virtual void predeleteService();
/** IClock */
virtual uint64_t getStepCounter() {
return wb_time.read() + 2;
}
virtual void registerStepCallback(IClockListener *cb, uint64_t t) {
wrapper_->registerStepCallback(cb, t);
}
bool moveStepCallback(IClockListener *cb, uint64_t t) {
//if (queue_.move(cb, t)) {
// return true;
//}
registerStepCallback(cb, t);
return false;
}
virtual double getFreqHz() { return 1.0; }
/** IHap */
virtual void hapTriggered(IFace *isrc, EHapType type, const char *descr);
virtual void stop();
protected:
/** IThread interface */
virtual void busyLoop();
private:
void createSystemC();
void deleteSystemC();
private:
AttributeType hartid_;
AttributeType bus_;
AttributeType cmdexec_;
AttributeType tap_;
AttributeType freqHz_;
AttributeType InVcdFile_;
AttributeType OutVcdFile_;
AttributeType GenerateRef_;
event_def config_done_;
ICmdExecutor *icmdexec_;
ITap *itap_;
IMemoryOperation *ibus_;
sc_signal<bool> w_clk;
sc_signal<bool> w_nrst;
// Timer:
sc_signal<sc_uint<64>> wb_time;
// Memory interface:
sc_signal<bool> w_req_mem_ready;
sc_signal<bool> w_req_mem_valid;
sc_signal<bool> w_req_mem_write;
sc_signal<sc_uint<BUS_ADDR_WIDTH>> wb_req_mem_addr;
sc_signal<sc_uint<BUS_DATA_BYTES>> wb_req_mem_strob;
sc_signal<sc_uint<BUS_DATA_WIDTH>> wb_req_mem_data;
sc_signal<bool> w_resp_mem_data_valid;
sc_signal<sc_uint<BUS_DATA_WIDTH>> wb_resp_mem_data;
sc_signal<bool> w_resp_mem_load_fault;
sc_signal<bool> w_resp_mem_store_fault;
/** Interrupt line from external interrupts controller. */
sc_signal<bool> w_interrupt;
// Debug interface
sc_signal<bool> w_dport_valid;
sc_signal<bool> w_dport_write;
sc_signal<sc_uint<2>> wb_dport_region;
sc_signal<sc_uint<12>> wb_dport_addr;
sc_signal<sc_uint<RISCV_ARCH>> wb_dport_wdata;
sc_signal<bool> w_dport_ready;
sc_signal<sc_uint<RISCV_ARCH>> wb_dport_rdata;
sc_trace_file *i_vcd_; // stimulus pattern
sc_trace_file *o_vcd_; // reference pattern for comparision
RiverTop *top_;
RtlWrapper *wrapper_;
CmdBrRiscv *pcmd_br_;
CmdRegRiscv *pcmd_reg_;
CmdRegsRiscv *pcmd_regs_;
CmdCsr *pcmd_csr_;
};
DECLARE_CLASS(CpuRiscV_RTL)
} // namespace debugger
#endif // __DEBUGGER_CPU_RISCV_RTL_H__
|
#include <config.hpp>
#include <core.hpp>
#include <systemc.h>
SC_MODULE(Sensor_${sensor_name}_functional)
{
Core* core;
//Input Port
sc_core::sc_in <bool> enable;
sc_core::sc_in <int> address;
sc_core::sc_in <int> data_in;
sc_core::sc_in <bool> flag_wr;
sc_core::sc_in <bool> ready;
//Output Port
sc_core::sc_out <int> data_out;
sc_core::sc_out <bool> go;
//Power Port
sc_core::sc_out <int> power_signal;
//Thermal Port
//sc_core::sc_out <int> thermal_signal;
SC_CTOR(Sensor_${sensor_name}_functional):
enable("Enable_signal"),
address("Address"),
data_in("Data_in"),
flag_wr("Flag"),
ready("Ready"),
data_out("Data_out"),
go("Go"),
power_signal("Func_to_Power_signal")
{
//printf("SENSOR :: systemc constructor");
register_memory = new uint8_t[${register_memory}];
SC_THREAD(sensor_logic);
sensitive << ready;
}
void sensor_logic();
Sensor_${sensor_name}_functional(){
//printf("SENSOR :: constructor");
}
~Sensor_${sensor_name}_functional(){
delete[]register_memory;
}
//Register Map
private:
uint8_t* register_memory;
int register_memory_size=${register_memory};
}; |
/*******************************************************************************
* pcntbus.h -- Copyright 2019 (c) Glenn Ramalho - RFIDo Design
*******************************************************************************
* Description:
* Defines the format of the PCNT bus. This is a simple encapsulation bus to
* gather all signals related to one channel and make the top look a bit
* simpler.
*******************************************************************************
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
#ifndef _PCNTBUS_H
#define _PCNTBUS_H
#include <systemc.h>
struct pcntbus_t {
bool sig_ch0;
bool sig_ch1;
bool ctrl_ch0;
bool ctrl_ch1;
};
inline bool operator==(const pcntbus_t &a, const pcntbus_t &b) {
if (a.sig_ch0 != b.sig_ch0) return false;
if (a.sig_ch1 != b.sig_ch1) return false;
if (a.ctrl_ch0 != b.ctrl_ch0) return false;
if (a.ctrl_ch1 != b.ctrl_ch1) return false;
return true;
}
inline std::ostream &operator<<(std::ostream &os, const pcntbus_t &a) {
os << "ch0(" << a.sig_ch0 << "/" << a.ctrl_ch0 << ") ch1(" << a.sig_ch1
<< "/" << a.ctrl_ch1 << ")";
return os;
}
inline bool operator!=(const pcntbus_t &a, const pcntbus_t &b) {
return !operator==(a,b);
}
inline void sc_trace(sc_trace_file *tf, const pcntbus_t &object,
const std::string &name) {
sc_trace(tf, object.sig_ch0, name + "_sigch0");
sc_trace(tf, object.sig_ch1, name + "_sigch1");
sc_trace(tf, object.ctrl_ch0, name + "_ctrlch0");
sc_trace(tf, object.ctrl_ch1, name + "_ctrlch1");
}
#endif
|
#ifndef _DRAM_H_
#define _DRAM_H_
#include <stdint.h>
#include <systemc.h>
#include <ahb_slave_if.h>
#include <math.h>
#define READ_PIPELINE
#define REF_TIME 6400000 //#cycle @ 100MHz (10ns)
#define REF_CYCLE 8192
#define CL 10 //ns
#define CWL 10 //ns
#define tRAS 12000 // Active to Precharge
#define tRP 10 // Precharge to Active ns
#define DRAM_CLK 6 // NS
enum ST_SDRAM {IDLE, // 0
RowActive, // 1
READ, // 2
WRITE, // 3
PRECHARGE // 4
};
enum BURST_STATE{
FIRST_BURST,
BURST,
NO_BURST
};
/* module of RAM */
class DRAM: public ahb_slave_if, public sc_module
{
public:
SC_HAS_PROCESS(DRAM);
DRAM(sc_module_name name, uint32_t mapping_size, const char* slave_num);
~DRAM();
bool read(uint32_t*, uint32_t, int);
bool write(uint32_t, uint32_t, int);
virtual bool local_access(bool write, uint32_t addr, uint32_t& data, unsigned int length,uint32_t burst_length);
//DRAM Model
void InitDramController();
bool NeedActive(unsigned int addr);
bool NeedPrecharge(unsigned int addr, unsigned int tRAS_count);
private:
uint8_t* bank;
uint32_t bank_bit;
uint32_t row_bit;
uint32_t col_bit;
uint32_t dw_bit;
inline uint32_t* ptr_word(uint32_t addr)
{
return (uint32_t*)(bank + addr);
}
inline uint16_t* ptr_hword(uint32_t addr)
{
return (uint16_t*)(bank + addr);
}
inline uint8_t* ptr_byte(uint32_t addr)
{
return (uint8_t*)(bank + addr);
}
//DRAM Model
ST_SDRAM state;
unsigned int AddrOffset_Bank;
unsigned int AddrOffset_Row;
unsigned int AddrOffset_Col;
unsigned int AddrMask_Bank;
unsigned int AddrMask_Row;
unsigned int AddrMask_Col;
unsigned int Index_Bank;
unsigned int Index_Row;
unsigned int Index_Col;
unsigned int prev_Bank;
unsigned int prev_Row;
void InitAddressDecode();
void AddrDecode(unsigned int addr);
unsigned int GetMask(unsigned int bit);
char dram_name[16];
uint32_t precharge_counter;
int b_length;
BURST_STATE burst_state;
int pre_burst;
bool pre_w_burst;
bool pre_r_burst;
};
#endif
|
/*
* Copyright (c) 2009 Thales Communication - AAL
*
* This file is part of Rabbits.
*
* Rabbits is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* Rabbits is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Rabbits. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef _ETRACE_IF_H_
#define _ETRACE_IF_H_
#include <cfg.h>
#ifdef ENERGY_TRACE_ENABLED
#include <systemc.h>
#include <stdint.h>
#define ETRACE_MODE(mode, fvset) (((fvset) << 5) | (mode))
#define ETRACE_CPU_IDLE 0
#define ETRACE_CPU_RUNNING 1
#define MAX_PERIPHERALS 20
#define MAX_HISTORY 10
#define WRITE_COMMAND 0x0
#define READ_COMMAND 0x1
typedef struct sample sample_t;
typedef struct per_en per_en_t;
typedef struct scope_state scope_state_t;
typedef struct periph periph_t;
typedef struct
{
const char *class_name;
int max_energy_ms;
int nmodes;
int nfvsets;
uint64_t *mode_cost;
} periph_class_t;
struct periph
{
char *name;
const periph_class_t *pclass;
int group_id;
char *group_name;
periph_t *next;
int idx;
uint64_t last_change_stamp;
int curr_mode;
int curr_fvset;
};
struct scope_state
{
uint64_t sample_period;
sample_t *samples_head;
uint64_t last_measure_stamp;
periph_t *head_periphs;
int nb_periphs;
int nb_groups;
int max_energy_ms;
};
struct per_en
{
int processed;
uint64_t energy;
};
struct sample
{
sample_t *next;
uint64_t time_stamp;
per_en_t per_costs[MAX_PERIPHERALS];
};
class etrace_if : public sc_module
{
public:
SC_HAS_PROCESS (etrace_if);
etrace_if (sc_module_name name);
~etrace_if ();
public:
unsigned long add_periph (const char *name, const periph_class_t *pclass, int &group_id,
const char * group_name);
void change_energy_mode (unsigned long periph_id, unsigned long mode);
void energy_event (unsigned long periph_id, unsigned long event_id, unsigned long value);
void start_measure (void);
unsigned long stop_measure (void);
private:
void display_init (void);
void scope_trigger (void);
uint64_t roll_average (uint64_t new_samp);
private:
scope_state_t *m_scope;
int m_disp_pipe;
int m_full_average;
int m_curr_idx;
uint64_t m_history[MAX_HISTORY];
int m_measure_started;
uint64_t m_measure_accum;
uint32_t m_measure_nbsamp;
};
extern etrace_if etrace;
#endif /* ENERGY_TRACE_ENABLED */
#endif /* _ETRACE_IF_H_ */
/*
* Vim standard variables
* vim:set ts=4 expandtab tw=80 cindent syntax=c:
*
* Emacs standard variables
* Local Variables:
* mode: c
* tab-width: 4
* c-basic-offset: 4
* indent-tabs-mode: nil
* End:
*/
|
#ifndef MEMORY_TLM_HPP
#define MEMORY_TLM_HPP
#include <systemc.h>
using namespace sc_core;
using namespace sc_dt;
using namespace std;
#include <tlm.h>
#include <tlm_utils/simple_initiator_socket.h>
#include <tlm_utils/simple_target_socket.h>
#include <tlm_utils/peq_with_cb_and_phase.h>
#include "../src/img_target.cpp"
#include "address_map.hpp"
//Extended Unification TLM
struct memory_tlm : public img_target
{
memory_tlm(sc_module_name name) : img_target((std::string(name) + "_target").c_str()) {
mem_array = new unsigned char[MEMORY_SIZE];
#ifdef DISABLE_MEM_DEBUG
this->use_prints = false;
#endif //DISABLE_MEM_DEBUG
checkprintenableimgtar(use_prints);
}
//Override do_when_transaction functions
virtual void do_when_read_transaction(unsigned char*& data, unsigned int data_length, sc_dt::uint64 address);
virtual void do_when_write_transaction(unsigned char*& data, unsigned int data_length, sc_dt::uint64 address);
void backdoor_write(unsigned char*& data, unsigned int data_length, sc_dt::uint64 address);
void backdoor_read(unsigned char*& data, unsigned int data_length, sc_dt::uint64 address);
unsigned char* mem_array;
sc_uint<64> mem_data;
sc_uint<24> mem_address;
sc_uint<1> mem_we;
};
#endif // MEMORY_TLM_HPP
|
#ifndef MC_SCVERIFY_H_INC
#define MC_SCVERIFY_H_INC
//
// mc_scverify.h
//
// This header file provides macros useful for creating testbenches
// for standard C++ designs as well as SystemC testbenches.
// Support for either standard C++ or SystemC is controlled by
// the compiler directive '#ifdef CCS_SYSC'.
//
#if defined(CCS_SYSC) && !defined(CCS_SCVERIFY)
//---------------------------------------------------------
// SystemC testbench mode
//
// Verification with SystemC testbenches requires that the
// testbench be self-checking and that it return a non-zero
// exit code to signal failure.
//
// A sample SystemC testbench (and sc_main) look like this:
//
// TBD
//
// SC_MODULE(testbench)
// {
// public:
// // Clock
// sc_clock clk;
//
// // Interconnect
// sc_in_clk clk;
// sc_signal<bool> rst;
// sc_signal<int> datain;
// sc_signal<int> dataout;
//
// // Design Under Test (DUT)
// CCS_DESIGN(adder) adder_INST;
//
// SC_CTOR(testbench)
// : CCS_CLK_CTOR(clk, "clk", 10, SC_NS, 0.5, 0, SC_NS, false) // effectively clk("clk", 10, SC_NS, 0.5, 0, SC_NS, false)
// , adder_INST("adder_INST")
// , rst("rst"), datain("datain"), dataout("dataout") {
// SC_THREAD(reset_driver);
// }
//
// // Active-high Asynchronous reset driver
// void reset_driver() {
// rst.write(1);
// wait(clk.period() * 1.5); // wait 1.5 clock cycles
// std::ostringstream msg;
// msg << "De-asserting reset signal '" << rst.name() << "' @ " << sc_time_stamp();
// SC_REPORT_INFO(this->name(),msg.str().c_str());
// rst.write(0);
// }
//
// // ... BODY OF TESTBENCH GOES HERE. Create methods
// // to drive inputs and check outputs. Mismatches
// // should report the error using:
// // SC_REPORT_ERROR("testbench", "ERROR: some error message\n");
//
// };
//
// int sc_main(int argc, char *argv[])
// {
// sc_report_handler::set_actions("/IEEE_Std_1666/deprecated", SC_DO_NOTHING);
// testbench testbench_INST("testbench_INST");
// sc_report_handler::set_actions(SC_ERROR, SC_DISPLAY);
// sc_start();
// if (sc_report_handler::get_count(SC_ERROR) > 0) {
// cout << "Simulation FAILED\n"
// return -1;
// } else {
// cout << "Simulation PASSED\n"
// }
// return 0;
// }
#undef CCS_DESIGN
#undef CCS_CLK_CTOR
// Macro expands out to sc_module created in sysc_sim.cpp that
// encapsulates the RTL instance and corresponding transactors
#define CCS_DESIGN(a) CCS_RTL::sysc_sim_wrapper
#define CCS_CLK_CTOR(clkobj,name_,period_v_,period_tu_,duty_cycle_,start_time_v_,start_time_tu_,posedge_first_) clkobj(name_,scverify_lookup_clk(name_,period_v_,period_tu_),duty_cycle_,sc_time(start_time_v_,start_time_tu_),posedge_first_)
#ifndef SC_USE_STD_STRING
#define SC_USE_STD_STRING
#endif
#ifndef SC_INCLUDE_DYNAMIC_PROCESSES
#define SC_INCLUDE_DYNAMIC_PROCESSES
#endif
#define CCS_PRIVATE public
#define CCS_PROTECTED public
// Include transactor models
#include <mc_scv_trans.h>
#else
#if !defined(CCS_SYSC) && defined(CCS_SCVERIFY)
//---------------------------------------------------------
// Standard C++ testbench mode
//
// For standard C++ design testbenches, this file provides macros to
// simplify the creation of C++ testbench files that are SCVerify-ready.
//
// A sample testbench file looks like this:
//
// #include <mc_scverify.h>
// // Include C++ design function
// #include "my_func.h"
//
// CCS_MAIN(int argc, char *argv[])
// {
// for (int iteration=0; iteration<5; iteration++) {
// int arg1 = iteration; // 1st arg to my_func
// int arg2 = iteration+1; // 2nd arg to my_func
// int arg3; // result
// CCS_DESIGN(my_func)(arg1,arg2,&arg3);
// cout << arg3 << endl;
// }
// return 0; // return success
// }
#undef CCS_RETURN
#undef CCS_DESIGN
#undef CCS_MAIN
#undef CCS_CLK_CTOR
#define CCS_PRIVATE public
#define CCS_PROTECTED public
#define CCS_RETURN(a) return(a)
#define CCS_DESIGN(a) testbench::exec_##a
#define CCS_MAIN(a,b) int testbench::main()
#define CCS_CLK_CTOR(clkobj,name_,period_v_,period_tu_,duty_cycle_,start_time_v_,start_time_tu_,posedge_first_) clkobj(name_,scverify_lookup_clk(name_,period_v_,period_tu_),duty_cycle_,sc_time(start_time_v_,start_time_tu_),posedge_first_)
#include <mc_testbench.h>
#else
//---------------------------------------------------------
// No special verification mode
#define CCS_PRIVATE private
#define CCS_PROTECTED private
#define CCS_DESIGN(a) a
#define CCS_MAIN(a,b) int main(a,b)
#define CCS_RETURN(a) return(a)
#define CCS_CLK_CTOR(clkobj,name_,period_v_,period_tu_,duty_cycle_,start_time_v_,start_time_tu_,posedge_first_) clkobj(name_,sc_time(period_v_,period_tu_),duty_cycle_,sc_time(start_time_v_,start_time_tu_),posedge_first_)
#endif
#endif
#if (defined(CCS_SCVERIFY) && !defined(AC_REPLAY_STAND_ALONE)) || defined(CCS_SYSC)
#include <sstream>
#include <systemc.h>
inline sc_time scverify_lookup_clk(const char *clkname, double default_period, sc_time_unit default_unit) {
std::ostringstream warnmsg;
sc_time default_clkp(default_period,default_unit);
std::string env_var_name;
env_var_name = "CCS_SCVERIFY_CLK_";
env_var_name += clkname;
char *val_str = getenv(env_var_name.c_str());
if (val_str != NULL) {
std::string str(val_str);
size_t pos = str.find(" ");
double period = atof(str.substr(0,pos).c_str());
if ( period != 0) {
std::string unitstr(str.substr(++pos));
sc_time_unit units = SC_NS;
if (unitstr == "SC_NS") units = SC_NS;
if (unitstr == "SC_FS") units = SC_FS;
if (unitstr == "SC_PS") units = SC_PS;
if (unitstr == "SC_US") units = SC_US;
if (unitstr == "SC_MS") units = SC_MS;
if (unitstr == "SC_SEC") units = SC_SEC;
sc_time clkp(period,units);
warnmsg << "Clock '" << clkname << "' - Overriding default clock period '" << default_clkp << "' with value '" << clkp << "'";
SC_REPORT_WARNING("CCS_CLK_CTOR", warnmsg.str().c_str());
return clkp;
} else {
warnmsg << "Clock '" << clkname << "' - Could not parse clock period override value '" << val_str << "'";
SC_REPORT_ERROR("CCS_CLK_CTOR", warnmsg.str().c_str());
warnmsg.clear();
}
}
warnmsg << "Clock '" << clkname << "' - Using default clock period '" << default_clkp << "'";
SC_REPORT_INFO("CCS_CLK_CTOR", warnmsg.str().c_str());
return default_clkp;
}
#endif
//---------------------------------------------------------
// Experimental block-based capture mode
#ifdef __SYNTHESIS__
#define CCS_BLOCK(fn) fn
#else
#if !defined(CCS_SCVERIFY) || !defined(CCS_SCVERIFY_USE_CCS_BLOCK)
#define CCS_BLOCK(fn) fn
#else
#undef CCS_DESIGN
#define CCS_DESIGN(fn) fn
#include "ccs_block_macros.h"
// Define macro such that
// #pragma design
// template <int INST>
// int CCS_BLOCK(my_func) (int arg1, int arg2)
// { // begining of function to synthesize
// return arg1+arg2;
// }
// expands at first to:
// #pragma design
// template <int INST>
// int
// ccs_intercept_my_func
// (int arg1, int arg2)
// { // begining of function to synthesize
// return arg1+arg2;
// }
// which (via ccs_block_macros.h) finally becomes:
// #pragma design
// template <int INST>
// int
// ccs_real_my_func(int,int);
// template <int INST>
// int my_func(int &arg1, int &arg2) {
// testbench::my_func_capture_IN(arg1,arg2);
// int _ret = ccs_real_my_func<INST>(arg1,arg2);
// testbench::my_func_capture_OUT(_ret,arg1,arg2);
// return _ret;
// }
// template <int INST>
// int ccs_real_my_func
// (int arg1, int arg2)
// { // begining of function to synthesize
// return arg1+arg2;
// }
#define CCS_BLOCK_TOKENPASTE(x,y) ccs_intercept_ ## x ##_## y
#define CCS_BLOCK_TOKENPASTE2(x,y) CCS_BLOCK_TOKENPASTE(x,y)
#define CCS_BLOCK(a) CCS_BLOCK_TOKENPASTE2(a,__LINE__)
#endif
#endif
//---------------------------------------------------------
#endif
|
#ifndef IMG_TRANSMITER_HPP
#define IMG_TRANSMITER_HPP
#include <systemc.h>
#include "address_map.hpp"
SC_MODULE(img_transmiter)
{
//Array for input image
unsigned char* output_image;
sc_dt::uint64 address_offset;
SC_CTOR(img_transmiter)
{
output_image = new unsigned char[IMG_INPUT_SIZE];
address_offset = IMG_OUTPUT_ADDRESS_LO;
}
//Backdoor access to memory
void backdoor_write(unsigned char*&data, unsigned int data_length, sc_dt::uint64 address);
void backdoor_read(unsigned char*&data, unsigned int data_length, sc_dt::uint64 address);
};
#endif // IMG_TRANSMITER_HPP
|
/*
* Copyright 2018 Sergey Khabarov, [email protected]
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __DEBUGGER_RIVERLIB_EXECUTE_H__
#define __DEBUGGER_RIVERLIB_EXECUTE_H__
#include <systemc.h>
#include "../river_cfg.h"
#include "arith/int_div.h"
#include "arith/int_mul.h"
#include "arith/shift.h"
namespace debugger {
SC_MODULE(InstrExecute) {
sc_in<bool> i_clk;
sc_in<bool> i_nrst; // Reset active LOW
sc_in<bool> i_pipeline_hold; // Hold execution by any reason
sc_in<bool> i_d_valid; // Decoded instruction is valid
sc_in<sc_uint<BUS_ADDR_WIDTH>> i_d_pc; // Instruction pointer on decoded instruction
sc_in<sc_uint<32>> i_d_instr; // Decoded instruction value
sc_in<bool> i_wb_done; // write back done (Used to clear hazardness)
sc_in<bool> i_memop_store; // Store to memory operation
sc_in<bool> i_memop_load; // Load from memoru operation
sc_in<bool> i_memop_sign_ext; // Load memory value with sign extending
sc_in<sc_uint<2>> i_memop_size; // Memory transaction size
sc_in<bool> i_unsigned_op; // Unsigned operands
sc_in<bool> i_rv32; // 32-bits instruction
sc_in<bool> i_compressed; // C-extension (2-bytes length)
sc_in<sc_bv<ISA_Total>> i_isa_type; // Type of the instruction's structure (ISA spec.)
sc_in<sc_bv<Instr_Total>> i_ivec; // One pulse per supported instruction.
sc_in<bool> i_unsup_exception; // Unsupported instruction exception
sc_in<bool> i_dport_npc_write; // Write npc value from debug port
sc_in<sc_uint<BUS_ADDR_WIDTH>> i_dport_npc; // Debug port npc value to write
sc_out<sc_uint<5>> o_radr1; // Integer register index 1
sc_in<sc_uint<RISCV_ARCH>> i_rdata1; // Integer register value 1
sc_out<sc_uint<5>> o_radr2; // Integer register index 2
sc_in<sc_uint<RISCV_ARCH>> i_rdata2; // Integer register value 2
sc_out<sc_uint<5>> o_res_addr; // Address to store result of the instruction (0=do not store)
sc_out<sc_uint<RISCV_ARCH>> o_res_data; // Value to store
sc_out<bool> o_pipeline_hold; // Hold pipeline while 'writeback' not done or multi-clock instruction.
sc_out<sc_uint<12>> o_csr_addr; // CSR address. 0 if not a CSR instruction with xret signals mode switching
sc_out<bool> o_csr_wena; // Write new CSR value
sc_in<sc_uint<RISCV_ARCH>> i_csr_rdata; // CSR current value
sc_out<sc_uint<RISCV_ARCH>> o_csr_wdata; // CSR new value
sc_in<bool> i_trap_valid; // async trap event
sc_in<sc_uint<BUS_ADDR_WIDTH>> i_trap_pc; // jump to address
// exceptions:
sc_out<sc_uint<BUS_ADDR_WIDTH>> o_ex_npc; // npc on before trap
sc_out<bool> o_ex_illegal_instr;
sc_out<bool> o_ex_unalign_store;
sc_out<bool> o_ex_unalign_load;
sc_out<bool> o_ex_breakpoint;
sc_out<bool> o_ex_ecall;
sc_out<bool> o_memop_sign_ext; // Load data with sign extending
sc_out<bool> o_memop_load; // Load data instruction
sc_out<bool> o_memop_store; // Store data instruction
sc_out<sc_uint<2>> o_memop_size; // 0=1bytes; 1=2bytes; 2=4bytes; 3=8bytes
sc_out<sc_uint<BUS_ADDR_WIDTH>> o_memop_addr;// Memory access address
sc_out<bool> o_pre_valid; // pre-latch of valid
sc_out<bool> o_valid; // Output is valid
sc_out<sc_uint<BUS_ADDR_WIDTH>> o_pc; // Valid instruction pointer
sc_out<sc_uint<BUS_ADDR_WIDTH>> o_npc; // Next instruction pointer. Next decoded pc must match to this value or will be ignored.
sc_out<sc_uint<32>> o_instr; // Valid instruction value
sc_out<bool> o_call; // CALL pseudo instruction detected
sc_out<bool> o_ret; // RET pseudoinstruction detected
sc_out<bool> o_mret; // MRET.
sc_out<bool> o_uret; // MRET.
void comb();
void registers();
SC_HAS_PROCESS(InstrExecute);
InstrExecute(sc_module_name name_);
virtual ~InstrExecute();
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
enum EMultiCycleInstruction {
Multi_MUL,
Multi_DIV,
Multi_Total
};
struct multi_arith_type {
sc_signal<sc_uint<RISCV_ARCH>> arr[Multi_Total];
};
struct RegistersType {
sc_signal<bool> d_valid; // Valid decoded instruction latch
sc_signal<sc_uint<BUS_ADDR_WIDTH>> pc;
sc_signal<sc_uint<BUS_ADDR_WIDTH>> npc;
sc_signal<sc_uint<32>> instr;
sc_uint<5> res_addr;
sc_signal<sc_uint<RISCV_ARCH>> res_val;
sc_signal<bool> memop_load;
sc_signal<bool> memop_store;
bool memop_sign_ext;
sc_uint<2> memop_size;
sc_signal<sc_uint<BUS_ADDR_WIDTH>> memop_addr;
sc_signal<sc_uint<5>> multi_res_addr; // latched output reg. address while multi-cycle instruction
sc_signal<sc_uint<BUS_ADDR_WIDTH>> multi_pc; // latched pc-value while multi-cycle instruction
sc_signal<sc_uint<BUS_ADDR_WIDTH>> multi_npc; // latched npc-value while multi-cycle instruction
sc_signal<sc_uint<32>> multi_instr; // Multi-cycle instruction is under processing
sc_signal<bool> multi_ena[Multi_Total]; // Enable pulse for Operation that takes more than 1 clock
sc_signal<bool> multi_rv32; // Long operation with 32-bits operands
sc_signal<bool> multi_unsigned; // Long operation with unsiged operands
sc_signal<bool> multi_residual_high; // Flag for Divider module: 0=divsion output; 1=residual output
// Flag for multiplier: 0=usual; 1=get high bits
sc_signal<bool> multiclock_ena;
sc_signal<sc_uint<RISCV_ARCH>> multi_a1; // Multi-cycle operand 1
sc_signal<sc_uint<RISCV_ARCH>> multi_a2; // Multi-cycle operand 2
sc_signal<sc_uint<5>> hazard_addr0; // Updated register address on previous step
sc_signal<sc_uint<5>> hazard_addr1; // Updated register address on pre-previous step
sc_signal<sc_uint<2>> hazard_depth; // Number of modificated registers that wasn't done yet
sc_signal<bool> call;
sc_signal<bool> ret;
} v, r;
sc_signal<bool> w_hazard_detected;
multi_arith_type wb_arith_res;
sc_signal<bool> w_arith_valid[Multi_Total];
sc_signal<bool> w_arith_busy[Multi_Total];
bool w_exception_store;
bool w_exception_load;
sc_signal<sc_uint<RISCV_ARCH>> wb_shifter_a1; // Shifters operand 1
sc_signal<sc_uint<6>> wb_shifter_a2; // Shifters operand 2
sc_signal<sc_uint<RISCV_ARCH>> wb_sll;
sc_signal<sc_uint<RISCV_ARCH>> wb_sllw;
sc_signal<sc_uint<RISCV_ARCH>> wb_srl;
sc_signal<sc_uint<RISCV_ARCH>> wb_srlw;
sc_signal<sc_uint<RISCV_ARCH>> wb_sra;
sc_signal<sc_uint<RISCV_ARCH>> wb_sraw;
IntMul *mul0;
IntDiv *div0;
Shifter *sh0;
};
} // namespace debugger
#endif // __DEBUGGER_RIVERLIB_EXECUTE_H__
|
/*******************************************************************************
* pn532_base.h -- Copyright 2020 (c) Glenn Ramalho - RFIDo Design
*******************************************************************************
* Description:
* This is a crude model for the PN532 with firmware v1.6. It will work for
* basic work with a PN532 system. This is the base class, without I/Os.
* Usually one of the derived classes should be used.
*******************************************************************************
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
#ifndef _PN532_BASE_H
#define _PN532_BASE_H
#include <systemc.h>
#include "gn_mixed.h"
#include <map>
struct data_block_t {
char data[16];
bool authenticated;
data_block_t() {
int i;
for (i = 0; i < 16; i = i + 1) data[i] = 0;
authenticated = false;
}
};
SC_MODULE(pn532_base) {
/* Signals */
sc_out<gn_mixed> irq {"irq"};
sc_signal<int> opstate {"opstate"};
sc_signal<int> pnstate {"pnstate"};
sc_signal<unsigned char> intoken {"intoken"};
sc_signal<unsigned char> outtoken {"outtoken"};
sc_fifo<unsigned char> to {"to"};
sc_fifo<unsigned char> from {"from"};
sc_event ack_ev {"ack_ev"};
sc_event newcommand_ev {"newcommand_ev"};
/* Functions */
void trace(sc_trace_file *tf);
void setcardnotpresent();
void setcardpresent(uint32_t uid);
void start_of_simulation();
/* Processes */
void process_th(void);
void resp_th(void);
void irqmanage_th(void);
/* I2C */
struct {
unsigned char tags;
unsigned int sens_res;
unsigned char sel_res;
unsigned char uidLength;
uint32_t uidValue;
unsigned char cmd;
unsigned char mode;
bool cmdbad;
unsigned short int lastincmd;
unsigned short int bn;
unsigned short int maxtg;
unsigned short int brty;
std::map<int, data_block_t> mem;
int len;
int timeout;
bool useirq;
unsigned int delay;
unsigned int predelay;
unsigned int retries;
unsigned int mxrtypassiveactivation;
} mif;
// Constructor
SC_CTOR(pn532_base) {
SC_THREAD(process_th);
SC_THREAD(resp_th);
SC_THREAD(irqmanage_th);
}
void mifset(int pos, const char *value);
void mifsetn(int pos, const uint8_t *value, int len);
/* Private routines. */
protected:
typedef enum {OPOFF, OPIDLE, OPACK, OPACKRDOUT, OPPREDELAY, OPBUSY,
OPREADOUT} op_t;
typedef enum {RESP_OK, RESP_RETRY} resp_t;
void pushack();
void pushsyntaxerr();
void pushpreamble(int len, bool hosttopn, int cmd, unsigned char *c);
resp_t pushresp();
void flush_to() { while(to.num_available() != 0) (void)to.read(); }
unsigned char grab(unsigned char *c) {
unsigned char m = from.read();
intoken.write(m);
if (c != NULL) *c = 0xff & (*c + m);
return m;
}
void pushandcalc(const unsigned char m, unsigned char *cksum) {
*cksum = 0xff & (*cksum + m);
to.write(m);
}
};
#endif
|
#include <systemc.h>
#include <systemc-ams.h>
// #ifndef IPS_AMS
// #define IPS_AMS
// #endif // IPS_AMS
#include "adc.hpp"
#include "dac.hpp"
#include "memory.hpp"
#include "seq_item_ams.hpp"
#include "vga.hpp"
// Main clock frequency in Hz - 25.175 MHz
#define CLK_FREQ 25175000
// VGA settings
#define H_ACTIVE 640
#define H_FP 16
#define H_SYNC_PULSE 96
#define H_BP 48
#define V_ACTIVE 480
#define V_FP 10
#define V_SYNC_PULSE 2
#define V_BP 33
// Compute the total number of pixels
#define TOTAL_VERTICAL (H_ACTIVE + H_FP + H_SYNC_PULSE + H_BP)
#define TOTAL_HORIZONTAL (V_ACTIVE + V_FP + V_SYNC_PULSE + V_BP)
#define TOTAL_PIXELES (TOTAL_VERTICAL * TOTAL_HORIZONTAL)
// Number of bits for ADC, DAC and VGA
#define BITS 8
#define VOLTAGE_MIN 0
#define VOLTAGE_MAX 3300
// Memory parameters
#define IMG_INPUT_ADDR 0x00000034u
#define MEM_SIZE 0x002A3034u
int sc_main(int, char *[])
{
// Compute the clock time in seconds
const double CLK_TIME = 1.0 / static_cast<double>(CLK_FREQ);
// Compute the total simulation based on the total amount of pixels in the
// screen
const double SIM_TIME = CLK_TIME * static_cast<double>(TOTAL_PIXELES);
// Signals to use
// -- Inputs of VGA
sc_core::sc_clock clk("clk", CLK_TIME, sc_core::SC_SEC);
sc_core::sc_signal<sc_uint<BITS>> s_tx_red;
sc_core::sc_signal<sc_uint<BITS>> s_tx_green;
sc_core::sc_signal<sc_uint<BITS>> s_tx_blue;
// -- Outputs of VGA
sc_core::sc_signal<bool> s_hsync;
sc_core::sc_signal<bool> s_vsync;
sc_core::sc_signal<unsigned int> s_h_count;
sc_core::sc_signal<unsigned int> s_v_count;
sc_core::sc_signal<sc_uint<BITS>> s_rx_red;
sc_core::sc_signal<sc_uint<BITS>> s_rx_green;
sc_core::sc_signal<sc_uint<BITS>> s_rx_blue;
// -- Outputs of DAC
sca_tdf::sca_signal<double> s_ana_red;
sca_tdf::sca_signal<double> s_ana_green;
sca_tdf::sca_signal<double> s_ana_blue;
// -- Outputs of ADC
sc_core::sc_signal<sc_uint<BITS>> s_dig_out_red;
sc_core::sc_signal<sc_uint<BITS>> s_dig_out_green;
sc_core::sc_signal<sc_uint<BITS>> s_dig_out_blue;
// -- Memory
sc_core::sc_signal<bool> s_we;
sc_core::sc_signal<unsigned long long int> s_address;
sc_core::sc_signal<sc_uint<24>> s_wdata;
sc_core::sc_signal<sc_uint<24>> s_rdata;
// Data generation for the VGA pixels
seq_item_ams<
BITS,
H_ACTIVE, H_FP, H_SYNC_PULSE, H_BP,
V_ACTIVE, V_FP, V_SYNC_PULSE, V_BP>
ips_seq_item_ams("ips_seq_item_ams");
ips_seq_item_ams.clk(clk);
ips_seq_item_ams.hcount(s_h_count);
ips_seq_item_ams.vcount(s_v_count);
ips_seq_item_ams.o_red(s_tx_red);
ips_seq_item_ams.o_green(s_tx_green);
ips_seq_item_ams.o_blue(s_tx_blue);
// VGA module instanciation and connections
vga<
BITS,
H_ACTIVE, H_FP, H_SYNC_PULSE, H_BP,
V_ACTIVE, V_FP, V_SYNC_PULSE, V_BP>
ips_vga("ips_vga");
ips_vga.clk(clk);
ips_vga.red(s_tx_red);
ips_vga.green(s_tx_green);
ips_vga.blue(s_tx_blue);
ips_vga.o_hsync(s_hsync);
ips_vga.o_vsync(s_vsync);
ips_vga.o_h_count(s_h_count);
ips_vga.o_v_count(s_v_count);
ips_vga.o_red(s_rx_red);
ips_vga.o_green(s_rx_green);
ips_vga.o_blue(s_rx_blue);
// DAC module instanciations and connections
dac<BITS, VOLTAGE_MIN, VOLTAGE_MAX, VUnit::mv> ips_dac_red("ips_dac_red");
ips_dac_red.in(s_rx_red);
ips_dac_red.out(s_ana_red);
dac<BITS, VOLTAGE_MIN, VOLTAGE_MAX, VUnit::mv> ips_dac_green("ips_dac_green");
ips_dac_green.in(s_rx_green);
ips_dac_green.out(s_ana_green);
dac<BITS, VOLTAGE_MIN, VOLTAGE_MAX, VUnit::mv> ips_dac_blue("ips_dac_blue");
ips_dac_blue.in(s_rx_blue);
ips_dac_blue.out(s_ana_blue);
// ADC module instanciations and connections
adc<BITS, VOLTAGE_MIN, VOLTAGE_MAX, VUnit::mv> ips_adc_red("ips_adc_red");
ips_adc_red.in(s_ana_red);
ips_adc_red.out(s_dig_out_red);
adc<BITS, VOLTAGE_MIN, VOLTAGE_MAX, VUnit::mv> ips_adc_green("ips_adc_green");
ips_adc_green.in(s_ana_green);
ips_adc_green.out(s_dig_out_green);
adc<BITS, VOLTAGE_MIN, VOLTAGE_MAX, VUnit::mv> ips_adc_blue("ips_adc_blue");
ips_adc_blue.in(s_ana_blue);
ips_adc_blue.out(s_dig_out_blue);
memory<MEM_SIZE> ips_memory("ips_memory");
ips_memory.clk(clk);
ips_memory.address(s_address);
ips_memory.we(s_we);
ips_memory.wdata(s_wdata);
ips_memory.rdata(s_rdata);
// Signals to dump
#ifdef IPS_DUMP_EN
sca_util::sca_trace_file *wf = sca_util::sca_create_vcd_trace_file("ips_ams");
sca_trace(wf, clk, "clk");
sca_trace(wf, s_hsync, "hsync");
sca_trace(wf, s_vsync, "vsync");
sca_trace(wf, s_h_count, "h_count");
sca_trace(wf, s_v_count, "v_count");
sca_trace(wf, s_tx_red, "tx_red");
sca_trace(wf, s_tx_green, "tx_green");
sca_trace(wf, s_tx_blue, "tx_blue");
sca_trace(wf, s_rx_red, "rx_red");
sca_trace(wf, s_rx_green, "rx_green");
sca_trace(wf, s_rx_blue, "rx_blue");
sca_trace(wf, s_ana_red, "ana_red");
sca_trace(wf, s_ana_green, "ana_green");
sca_trace(wf, s_ana_blue, "ana_blue");
sca_trace(wf, s_dig_out_red, "to_mem_red");
sca_trace(wf, s_dig_out_green, "to_mem_green");
sca_trace(wf, s_dig_out_blue, "to_mem_blue");
sca_trace(wf, s_we, "we");
sca_trace(wf, s_address, "address");
sca_trace(wf, s_rdata, "rdata");
#endif // IPS_DUMP_EN
// Start time
std::cout << "@" << sc_time_stamp() << std::endl;
double total_sim_time = 0.0;
while (SIM_TIME > total_sim_time)
{
const int IMG_ROW = s_v_count.read() - (V_SYNC_PULSE + V_BP);
const int IMG_COL = s_h_count.read() - (H_SYNC_PULSE + H_BP);
if ((IMG_ROW < 0) || (IMG_COL < 0) || (IMG_ROW >= V_ACTIVE) || (IMG_COL >= H_ACTIVE))
{
s_we.write(false);
}
else
{
const unsigned long long ADDR = static_cast<unsigned long long>(IMG_INPUT_ADDR + IMG_ROW * V_ACTIVE + IMG_COL);
s_address.write(ADDR);
s_wdata.write((s_dig_out_red.read() << 16) + (s_dig_out_green.read() << 8) + s_dig_out_blue.read());
s_we.write(true);
#ifdef IPS_DEBUG_EN
std::cout << " MEM[" << ADDR << "] = " << s_dig_out_blue.read() << std::endl
<< " MEM[" << (ADDR + 1) << "] = " << s_dig_out_green.read() << std::endl
<< " MEM[" << (ADDR + 2) << "] = " << s_dig_out_red.read() << std::endl;
#endif // IPS_DEBUG_EN
}
total_sim_time += CLK_TIME;
sc_start(CLK_TIME, sc_core::SC_SEC);
}
// End time
std::cout << "@" << sc_time_stamp() << std::endl;
#ifdef IPS_DUMP_EN
sca_util::sca_close_vcd_trace_file(wf);
#endif // IPS_DUMP_EN
return 0;
}
|
/*******************************************************************************
* st7735.cpp -- Copyright 2019 (c) Glenn Ramalho - RFIDo Design
*******************************************************************************
* Description:
* This is a testbench module to emulate the ST7735 display controller.
*******************************************************************************
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
#include <systemc.h>
#include "info.h"
#include "st7735.h"
void st7735::collect() {
pos = 0;
collected = 0;
while(1) {
wait();
/* We check the reset. */
if (!resx.read().islogic()) {
PRINTF_WARN("ST7735", "RESX is non-logic value %c", resx.read().to_char());
continue;
}
else if (resx.read().islow()) {
pos = 0;
collected = 0;
initialized = true;
continue;
}
// If the CSX is not low, we ignore what came in.
if (!csx.read().islogic()) {
PRINTF_WARN("ST7735", "CSX is non-logic value %c", csx.read().to_char());
continue;
}
else if (csx.read().ishigh()) continue;
// To use the controller, it needs to have been reset.
if (!initialized) {
PRINTF_WARN("ST7735", "Module has not been reset");
continue;
}
// Now we check the mode to see what came in. This depends on the mode
// selection.
switch(im.read().to_uint()) {
// SPI mode -- we only react to a chane in the SCL pin.
default:
/* We first discard the illegal values. */
if (!scl_dcx.read().islogic()) {
PRINTF_WARN("ST7735", "SCL is non-logic value %c",
scl_dcx.read().to_char());
continue;
}
/* If we are in readmode, we return the value. */
if (readmode) {
if (scl_dcx.read().ishigh()) sda.write(GN_LOGIC_Z);
else if (pos > 0)
sda.write(((collected & (1 << (pos-1)))>0)?GN_LOGIC_1:GN_LOGIC_0);
continue;
}
/* If it is not a read it is a write. We sample on the rising edge. */
if (scl_dcx.read() != SC_LOGIC_1) continue;
/* We increment the counter. If we are using the 3wire interface, we
* need to get the DCX first
*/
if (!spi4w.read().islogic()) {
PRINTF_WARN("ST7735",
"Tried to latch while spi4w is non-logic value %c",
spi4w.read().to_char());
continue;
}
else if (wrx.read().ishigh()) collected = collected | 0x100;
if (pos <= 0 && spi4w.read().islow()) {
collected = 0;
pos = 9;
}
else if (pos <= 0) {
collected = 0;
pos = 8;
}
else pos = pos - 1;
if (spi4w.read().ishigh()) {
if (!wrx.read().islogic()) {
PRINTF_WARN("ST7735", "Tried to latch non-logic WRX value %c",
wrx.read().to_char());
}
else if (wrx.read().ishigh()) collected = collected | 0x100;
else collected = collected & 0x0ff;
}
/* If the pin is non-logic we complain and skip it. */
if(!sda.read().islogic()) {
PRINTF_WARN("ST7735", "Tried to latch non-logic SDA value %c",
sda.read().to_char());
}
/* If the logic is valid, we take in the ones. */
else if (sda.read().ishigh()) collected = collected | (1 << (pos-1));
if (pos == 1) {
printf("%s: received %03x\n", sc_time_stamp().to_string().c_str(),
collected);
}
break;
}
}
}
void st7735::start_of_simulation() {
sda.write(GN_LOGIC_Z);
osc.write(GN_LOGIC_0);
te.write(GN_LOGIC_0);
d0.write(GN_LOGIC_Z);
d1.write(GN_LOGIC_Z);
d2.write(GN_LOGIC_Z);
d3.write(GN_LOGIC_Z);
d4.write(GN_LOGIC_Z);
d5.write(GN_LOGIC_Z);
d6.write(GN_LOGIC_Z);
d7.write(GN_LOGIC_Z);
d8.write(GN_LOGIC_Z);
d9.write(GN_LOGIC_Z);
d10.write(GN_LOGIC_Z);
d11.write(GN_LOGIC_Z);
d12.write(GN_LOGIC_Z);
d13.write(GN_LOGIC_Z);
d14.write(GN_LOGIC_Z);
d15.write(GN_LOGIC_Z);
d16.write(GN_LOGIC_Z);
d17.write(GN_LOGIC_Z);
}
void st7735::trace(sc_trace_file *tf) {
sc_trace(tf, sda, sda.name());
sc_trace(tf, d0, d0.name());
sc_trace(tf, d1, d1.name());
sc_trace(tf, d2, d2.name());
sc_trace(tf, d3, d3.name());
sc_trace(tf, d4, d4.name());
sc_trace(tf, d5, d5.name());
sc_trace(tf, d6, d6.name());
sc_trace(tf, d7, d7.name());
sc_trace(tf, d8, d8.name());
sc_trace(tf, d9, d9.name());
sc_trace(tf, d10, d10.name());
sc_trace(tf, d11, d11.name());
sc_trace(tf, d12, d12.name());
sc_trace(tf, d13, d13.name());
sc_trace(tf, d14, d14.name());
sc_trace(tf, d15, d15.name());
sc_trace(tf, d16, d16.name());
sc_trace(tf, d17, d17.name());
sc_trace(tf, wrx, wrx.name());
sc_trace(tf, rdx, rdx.name());
sc_trace(tf, csx, csx.name());
sc_trace(tf, scl_dcx, scl_dcx.name());
sc_trace(tf, spi4w, spi4w.name());
sc_trace(tf, im, im.name());
}
|
//
//------------------------------------------------------------//
// Copyright 2009-2012 Mentor Graphics Corporation //
// All Rights Reserved Worldwid //
// //
// Licensed under the Apache License, Version 2.0 (the //
// "License"); you may not use this file except in //
// compliance with the License. You may obtain a copy of //
// the License at //
// //
// http://www.apache.org/licenses/LICENSE-2.0 //
// //
// Unless required by applicable law or agreed to in //
// writing, software distributed under the License is //
// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR //
// CONDITIONS OF ANY KIND, either express or implied. See //
// the License for the specific language governing //
// permissions and limitations under the License. //
//------------------------------------------------------------//
//-----------------------------------------------------------------------------
// Title: SC Consumer
//
// Topic: Description
//
// A simple SC consumer TLM model that prints received transactions (of type
// ~tlm_generic_payload~ and sends them out its ~ap~ analysis port.
//
// This example uses the ~simple_target_socket~, a derivative of the TLM
// core class, ~tlm_target_socket~. Unlike the ~tlm_target_socket~, the simple
// socket does not require the module to inherit and implement all four
// target socket interface methods. Instead, you only need to register the
// interfaces you actually implement, ~b_transport~ in this case. This is what
// makes these sockets simple, flexible, and convenient.
//
// While trivial in functionality, the model demonstrates use of TLM ports
// to facilitate external communication.
//
// - Users of the model are not coupled to its internal implementation, using
// only the provided TLM port and socket to communicate.
//
// - The model itself does not refer to anything outside its encapsulated
// implementation. It does not know nor care about what might
// be driving its ~in~ socket or who might be listening on its ~ap~
// analysis port.
//-----------------------------------------------------------------------------
// (inline source)
#include <string>
#include <iomanip>
using std::string;
#include <systemc.h>
#include <tlm.h>
using namespace sc_core;
using namespace tlm;
#include "simple_target_socket.h"
using tlm_utils::simple_target_socket;
class consumer : public sc_module
{
public:
simple_target_socket<consumer> in; // defaults to tlm_gp
tlm_analysis_port<tlm_generic_payload> ap;
consumer(sc_module_name nm) : in("in"), ap("ap")
{
in.register_b_transport(this, &consumer::b_transport);
}
virtual void b_transport(tlm_generic_payload &gp, sc_time &t) {
char unsigned *data;
int len;
len = gp.get_data_length();
data = gp.get_data_ptr();
cout << sc_time_stamp() << " [CONSUMER/GP/RECV] ";
cout << "cmd:" << gp.get_command()
<< " addr:" << hex << gp.get_address() << " data:{ ";
for (int i=0; i<len; i++)
cout << hex << (int)*(data+i) << " ";
cout << "}" << endl;
wait(t);
t = SC_ZERO_TIME;
ap.write(gp);
}
};
|
//
// Copyright 2022 Sergey Khabarov, [email protected]
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
#pragma once
#include <systemc.h>
#include "types_amba.h"
namespace debugger {
// @defgroup slave_id_group AMBA APB slaves generic IDs.
// @details Each module in a SoC has to be indexed by unique identificator.
// In current implementation it is used sequential indexing for it.
// Indexes are used to specify a device bus item in a vectors.
// @brief UART0 APB device.
static const int CFG_BUS1_PSLV_UART1 = 0;
// @brief System status and control registers device.
static const int CFG_BUS1_PSLV_PRCI = 1;
// @brief Worjgroup DMI interface.
static const int CFG_BUS1_PSLV_DMI = 2;
// Configuration index of the SD-card control registers.
static const int CFG_BUS1_PSLV_SDCTRL_REG = 3;
// Configuration index of the GPIO (General Purpose In/Out) module.
static const int CFG_BUS1_PSLV_GPIO = 4;
// @brief DDR control register.
static const int CFG_BUS1_PSLV_DDR = 5;
// Configuration index of the Plug-n-Play module.
static const int CFG_BUS1_PSLV_PNP = 6;
// Total number of the APB slaves devices on Bus[1].
static const int CFG_BUS1_PSLV_TOTAL = 7;
// Necessary bus width to store index + 1.
static const int CFG_BUS1_PSLV_LOG2_TOTAL = 3; // $clog2(CFG_BUS1_PSLV_TOTAL + 1)
typedef sc_vector<sc_signal<apb_in_type>> bus1_apb_in_vector;
typedef sc_vector<sc_signal<apb_out_type>> bus1_apb_out_vector;
typedef sc_vector<sc_signal<mapinfo_type>> bus1_mapinfo_vector;
// Bus 1 device tree
static const mapinfo_type CFG_BUS1_MAP[CFG_BUS1_PSLV_TOTAL] = {
{0x0000000000010000, 0x0000000000011000}, // 0, uart1 4KB
{0x0000000000012000, 0x0000000000013000}, // 1, PRCI 4KB
{0x000000000001E000, 0x000000000001F000}, // 2, dmi 4KB. TODO: change base address
{0x0000000000050000, 0x0000000000051000}, // 4, SPI SD-card 4KB
{0x0000000000060000, 0x0000000000061000}, // 3, GPIO 4KB
{0x00000000000C0000, 0x00000000000C1000}, // 5, DDR MGMT 4KB
{0x00000000000FF000, 0x0000000000100000} // 6, Plug'n'Play 4KB
};
} // namespace debugger
|
//
// Copyright 2022 Sergey Khabarov, [email protected]
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
#pragma once
#include <systemc.h>
namespace debugger {
static const int CFG_SYSBUS_ADDR_BITS = 48;
static const int CFG_LOG2_SYSBUS_DATA_BYTES = 3;
static const int CFG_SYSBUS_ID_BITS = 5;
static const int CFG_SYSBUS_USER_BITS = 1;
static const int CFG_SYSBUS_DATA_BYTES = (1 << CFG_LOG2_SYSBUS_DATA_BYTES);
static const int CFG_SYSBUS_DATA_BITS = (8 * CFG_SYSBUS_DATA_BYTES);
// @brief Map information for the memory mapped device.
class mapinfo_type {
public:
mapinfo_type() {
// Base Address.
addr_start = 0;
// Maskable bits of the base address.
addr_end = 0;
}
mapinfo_type(uint64_t addr_start_,
uint64_t addr_end_) {
addr_start = addr_start_;
addr_end = addr_end_;
}
inline bool operator == (const mapinfo_type &rhs) const {
bool ret = true;
ret = ret
&& rhs.addr_start == addr_start
&& rhs.addr_end == addr_end;
return ret;
}
inline mapinfo_type& operator = (const mapinfo_type &rhs) {
addr_start = rhs.addr_start;
addr_end = rhs.addr_end;
return *this;
}
inline friend void sc_trace(sc_trace_file *tf,
const mapinfo_type&v,
const std::string &NAME) {
sc_trace(tf, v.addr_start, NAME + "_addr_start");
sc_trace(tf, v.addr_end, NAME + "_addr_end");
}
inline friend ostream &operator << (ostream &os,
mapinfo_type const &v) {
os << "("
<< v.addr_start << ","
<< v.addr_end << ")";
return os;
}
public:
// Base Address.
uint64_t addr_start;
// Maskable bits of the base address.
uint64_t addr_end;
};
// @brief Empty entry value for the map info table
static const mapinfo_type mapinfo_none = {0, 0};
// Burst length size decoder
static const int XSIZE_TOTAL = 8;
// Decoder of the transaction bytes from AXI format to Bytes.
static sc_uint<XSIZE_TOTAL> XSizeToBytes(sc_uint<3> xsize) {
sc_uint<XSIZE_TOTAL> ret;
ret = (1 << xsize.to_int());
return ret;
}
// @brief Normal access success.
// @details Indicates that a normal access has been
// successful. Can also indicate an exclusive access has failed.
static const uint8_t AXI_RESP_OKAY = 0;
// @brief Exclusive access okay.
// @details Indicates that either the read or write
// portion of an exclusive access has been successful.
static const uint8_t AXI_RESP_EXOKAY = 1;
// @brief Slave error.
// @details Used the access has reached the slave successfully,
// but the slave wishes to return an error condition to the originating
// master.
static const uint8_t AXI_RESP_SLVERR = 2;
// @brief Decode error.
// @details Generated, typically by an interconnect component,
// to indicate that there is no slave at the transaction address.
static const uint8_t AXI_RESP_DECERR = 3;
// @brief Fixed address burst operation.
// @details The address is the same for every transfer in the burst
// (FIFO type)
static const uint8_t AXI_BURST_FIXED = 0;
// @brief Burst operation with address increment.
// @details The address for each transfer in the burst is an increment of
// the address for the previous transfer. The increment value depends
// on the size of the transfer.
static const uint8_t AXI_BURST_INCR = 1;
// @brief Burst operation with address increment and wrapping.
// @details A wrapping burst is similar to an incrementing burst, except that
// the address wraps around to a lower address if an upper address
// limit is reached
static const uint8_t AXI_BURST_WRAP = 2;
// @}
static const uint8_t ARCACHE_DEVICE_NON_BUFFERABLE = 0x0;
static const uint8_t ARCACHE_WRBACK_READ_ALLOCATE = 0xF;
static const uint8_t AWCACHE_DEVICE_NON_BUFFERABLE = 0x0;
static const uint8_t AWCACHE_WRBACK_WRITE_ALLOCATE = 0xF;
// see table C3-7 Permitted read address control signal combinations
//
// read | cached | unique |
// 0 | 0 | * | ReadNoSnoop
// 0 | 1 | 0 | ReadShared
// 0 | 1 | 1 | ReadMakeUnique
static const uint8_t ARSNOOP_READ_NO_SNOOP = 0x0;
static const uint8_t ARSNOOP_READ_SHARED = 0x1;
static const uint8_t ARSNOOP_READ_MAKE_UNIQUE = 0xC;
// see table C3-8 Permitted read address control signal combinations
//
// write | cached | unique |
// 1 | 0 | * | WriteNoSnoop
// 1 | 1 | 1 | WriteLineUnique
// 1 | 1 | 0 | WriteBack
static const uint8_t AWSNOOP_WRITE_NO_SNOOP = 0x0;
static const uint8_t AWSNOOP_WRITE_LINE_UNIQUE = 0x1;
static const uint8_t AWSNOOP_WRITE_BACK = 0x3;
// see table C3-19
static const uint8_t AC_SNOOP_READ_UNIQUE = 0x7;
static const uint8_t AC_SNOOP_MAKE_INVALID = 0xD;
class axi4_metadata_type {
public:
axi4_metadata_type() {
addr = 0;
// @brief Burst length.
// @details This signal indicates the exact number of transfers in
// a burst. This changes between AXI3 and AXI4. nastiXLenBits=8 so
// this is an AXI4 implementation.
// Burst_Length = len[7:0] + 1
len = 0;
// @brief Burst size.
// @details This signal indicates the size of each transfer
// in the burst: 0=1 byte; ..., 6=64 bytes; 7=128 bytes;
size = 0;
// @brief Read response.
// @details This signal indicates the status of the read transfer.
// The responses are:
// 0b00 FIXED - In a fixed burst, the address is the same for every transfer
// in the burst. Typically is used for FIFO.
// 0b01 INCR - Incrementing. In an incrementing burst, the address for each
// transfer in the burst is an increment of the address for the
// previous transfer. The increment value depends on the size of
// the transfer.
// 0b10 WRAP - A wrapping burst is similar to an incrementing burst, except
// that the address wraps around to a lower address if an upper address
// limit is reached.
// 0b11 resrved.
burst = AXI_BURST_INCR;
lock = 0;
cache = 0;
// @brief Protection type.
// @details This signal indicates the privilege and security level
// of the transaction, and whether the transaction is a data access
// or an instruction access:
// [0] : 0 = Unpriviledge access
// 1 = Priviledge access
// [1] : 0 = Secure access
// 1 = Non-secure access
// [2] : 0 = Data access
// 1 = Instruction access
prot = 0;
// @brief Quality of Service, QoS.
// @details QoS identifier sent for each read transaction.
// Implemented only in AXI4:
// 0b0000 - default value. Indicates that the interface is
// not participating in any QoS scheme.
qos = 0;
// @brief Region identifier.
// @details Permits a single physical interface on a slave to be used for
// multiple logical interfaces. Implemented only in AXI4. This is
// similar to the banks implementation in Leon3 without address
// decoding.
region = 0;
}
axi4_metadata_type(sc_uint<CFG_SYSBUS_ADDR_BITS> addr_,
sc_uint<8> len_,
sc_uint<3> size_,
sc_uint<2> burst_,
bool lock_,
sc_uint<4> cache_,
sc_uint<3> prot_,
sc_uint<4> qos_,
sc_uint<4> region_) {
addr = addr_;
len = len_;
size = size_;
burst = burst_;
lock = lock_;
cache = cache_;
prot = prot_;
qos = qos_;
region = region_;
}
inline bool operator == (const axi4_metadata_type &rhs) const {
bool ret = true;
ret = ret
&& rhs.addr == addr
&& rhs.len == len
&& rhs.size == size
&& rhs.burst == burst
&& rhs.lock == lock
&& rhs.cache == cache
&& rhs.prot == prot
&& rhs.qos == qos
&& rhs.region == region;
return ret;
}
inline axi4_metadata_type& operator = (const axi4_metadata_type &rhs) {
addr = rhs.addr;
len = rhs.len;
size = rhs.size;
burst = rhs.burst;
lock = rhs.lock;
cache = rhs.cache;
prot = rhs.prot;
qos = rhs.qos;
region = rhs.region;
return *this;
}
inline friend void sc_trace(sc_trace_file *tf,
const axi4_metadata_type&v,
const std::string &NAME) {
sc_trace(tf, v.addr, NAME + "_addr");
sc_trace(tf, v.len, NAME + "_len");
sc_trace(tf, v.size, NAME + "_size");
sc_trace(tf, v.burst, NAME + "_burst");
sc_trace(tf, v.lock, NAME + "_lock");
sc_trace(tf, v.cache, NAME + "_cache");
sc_trace(tf, v.prot, NAME + "_prot");
sc_trace(tf, v.qos, NAME + "_qos");
sc_trace(tf, v.region, NAME + "_region");
}
inline friend ostream &operator << (ostream &os,
axi4_metadata_type const &v) {
os << "("
<< v.addr << ","
<< v.len << ","
<< v.size << ","
<< v.burst << ","
<< v.lock << ","
<< v.cache << ","
<< v.prot << ","
<< v.qos << ","
<< v.region << ")";
return os;
}
public:
sc_uint<CFG_SYSBUS_ADDR_BITS> addr;
// @brief Burst length.
// @details This signal indicates the exact number of transfers in
// a burst. This changes between AXI3 and AXI4. nastiXLenBits=8 so
// this is an AXI4 implementation.
// Burst_Length = len[7:0] + 1
sc_uint<8> len;
// @brief Burst size.
// @details This signal indicates the size of each transfer
// in the burst: 0=1 byte; ..., 6=64 bytes; 7=128 bytes;
sc_uint<3> size;
// @brief Read response.
// @details This signal indicates the status of the read transfer.
// The responses are:
// 0b00 FIXED - In a fixed burst, the address is the same for every transfer
// in the burst. Typically is used for FIFO.
// 0b01 INCR - Incrementing. In an incrementing burst, the address for each
// transfer in the burst is an increment of the address for the
// previous transfer. The increment value depends on the size of
// the transfer.
// 0b10 WRAP - A wrapping burst is similar to an incrementing burst, except
// that the address wraps around to a lower address if an upper address
// limit is reached.
// 0b11 resrved.
sc_uint<2> burst;
bool lock;
sc_uint<4> cache;
// @brief Protection type.
// @details This signal indicates the privilege and security level
// of the transaction, and whether the transaction is a data access
// or an instruction access:
// [0] : 0 = Unpriviledge access
// 1 = Priviledge access
// [1] : 0 = Secure access
// 1 = Non-secure access
// [2] : 0 = Data access
// 1 = Instruction access
sc_uint<3> prot;
// @brief Quality of Service, QoS.
// @details QoS identifier sent for each read transaction.
// Implemented only in AXI4:
// 0b0000 - default value. Indicates that the interface is
// not participating in any QoS scheme.
sc_uint<4> qos;
// @brief Region identifier.
// @details Permits a single physical interface on a slave to be used for
// multiple logical interfaces. Implemented only in AXI4. This is
// similar to the banks implementation in Leon3 without address
// decoding.
sc_uint<4> region;
};
static const axi4_metadata_type META_NONE;
class axi4_master_out_type {
public:
axi4_master_out_type() {
aw_valid = 0;
aw_bits.addr = 0;
aw_bits.len = 0;
aw_bits.size = 0;
aw_bits.burst = AXI_BURST_INCR;
aw_bits.lock = 0;
aw_bits.cache = 0;
aw_bits.prot = 0;
aw_bits.qos = 0;
aw_bits.region = 0;
aw_id = 0;
aw_user = 0;
w_valid = 0;
w_data = 0;
w_last = 0;
w_strb = 0;
w_user = 0;
b_ready = 0;
ar_valid = 0;
ar_bits.addr = 0;
ar_bits.len = 0;
ar_bits.size = 0;
ar_bits.burst = AXI_BURST_INCR;
ar_bits.lock = 0;
ar_bits.cache = 0;
ar_bits.prot = 0;
ar_bits.qos = 0;
ar_bits.region = 0;
ar_id = 0;
ar_user = 0;
r_ready = 0;
}
axi4_master_out_type(bool aw_valid_,
axi4_metadata_type aw_bits_,
sc_uint<CFG_SYSBUS_ID_BITS> aw_id_,
sc_uint<CFG_SYSBUS_USER_BITS> aw_user_,
bool w_valid_,
sc_uint<CFG_SYSBUS_DATA_BITS> w_data_,
bool w_last_,
sc_uint<CFG_SYSBUS_DATA_BYTES> w_strb_,
sc_uint<CFG_SYSBUS_USER_BITS> w_user_,
bool b_ready_,
bool ar_valid_,
axi4_metadata_type ar_bits_,
sc_uint<CFG_SYSBUS_ID_BITS> ar_id_,
sc_uint<CFG_SYSBUS_USER_BITS> ar_user_,
bool r_ready_) {
aw_valid = aw_valid_;
aw_bits = aw_bits_;
aw_id = aw_id_;
aw_user = aw_user_;
w_valid = w_valid_;
w_data = w_data_;
w_last = w_last_;
w_strb = w_strb_;
w_user = w_user_;
b_ready = b_ready_;
ar_valid = ar_valid_;
ar_bits = ar_bits_;
ar_id = ar_id_;
ar_user = ar_user_;
r_ready = r_ready_;
}
inline bool operator == (const axi4_master_out_type &rhs) const {
bool ret = true;
ret = ret
&& rhs.aw_valid == aw_valid
&& rhs.aw_bits.addr == aw_bits.addr
&& rhs.aw_bits.len == aw_bits.len
&& rhs.aw_bits.size == aw_bits.size
&& rhs.aw_bits.burst == aw_bits.burst
&& rhs.aw_bits.lock == aw_bits.lock
&& rhs.aw_bits.cache == aw_bits.cache
&& rhs.aw_bits.prot == aw_bits.prot
&& rhs.aw_bits.qos == aw_bits.qos
&& rhs.aw_bits.region == aw_bits.region
&& rhs.aw_id == aw_id
&& rhs.aw_user == aw_user
&& rhs.w_valid == w_valid
&& rhs.w_data == w_data
&& rhs.w_last == w_last
&& rhs.w_strb == w_strb
&& rhs.w_user == w_user
&& rhs.b_ready == b_ready
&& rhs.ar_valid == ar_valid
&& rhs.ar_bits.addr == ar_bits.addr
&& rhs.ar_bits.len == ar_bits.len
&& rhs.ar_bits.size == ar_bits.size
&& rhs.ar_bits.burst == ar_bits.burst
&& rhs.ar_bits.lock == ar_bits.lock
&& rhs.ar_bits.cache == ar_bits.cache
&& rhs.ar_bits.prot == ar_bits.prot
&& rhs.ar_bits.qos == ar_bits.qos
&& rhs.ar_bits.region == ar_bits.region
&& rhs.ar_id == ar_id
&& rhs.ar_user == ar_user
&& rhs.r_ready == r_ready;
return ret;
}
inline axi4_master_out_type& operator = (const axi4_master_out_type &rhs) {
aw_valid = rhs.aw_valid;
aw_bits.addr = rhs.aw_bits.addr;
aw_bits.len = rhs.aw_bits.len;
aw_bits.size = rhs.aw_bits.size;
aw_bits.burst = rhs.aw_bits.burst;
aw_bits.lock = rhs.aw_bits.lock;
aw_bits.cache = rhs.aw_bits.cache;
aw_bits.prot = rhs.aw_bits.prot;
aw_bits.qos = rhs.aw_bits.qos;
aw_bits.region = rhs.aw_bits.region;
aw_id = rhs.aw_id;
aw_user = rhs.aw_user;
w_valid = rhs.w_valid;
w_data = rhs.w_data;
w_last = rhs.w_last;
w_strb = rhs.w_strb;
w_user = rhs.w_user;
b_ready = rhs.b_ready;
ar_valid = rhs.ar_valid;
ar_bits.addr = rhs.ar_bits.addr;
ar_bits.len = rhs.ar_bits.len;
ar_bits.size = rhs.ar_bits.size;
ar_bits.burst = rhs.ar_bits.burst;
ar_bits.lock = rhs.ar_bits.lock;
ar_bits.cache = rhs.ar_bits.cache;
ar_bits.prot = rhs.ar_bits.prot;
ar_bits.qos = rhs.ar_bits.qos;
ar_bits.region = rhs.ar_bits.region;
ar_id = rhs.ar_id;
ar_user = rhs.ar_user;
r_ready = rhs.r_ready;
return *this;
}
inline friend void sc_trace(sc_trace_file *tf,
const axi4_master_out_type&v,
const std::string &NAME) {
sc_trace(tf, v.aw_valid, NAME + "_aw_valid");
sc_trace(tf, v.aw_bits.addr, NAME + "_aw_bits_addr");
sc_trace(tf, v.aw_bits.len, NAME + "_aw_bits_len");
sc_trace(tf, v.aw_bits.size, NAME + "_aw_bits_size");
sc_trace(tf, v.aw_bits.burst, NAME + "_aw_bits_burst");
sc_trace(tf, v.aw_bits.lock, NAME + "_aw_bits_lock");
sc_trace(tf, v.aw_bits.cache, NAME + "_aw_bits_cache");
sc_trace(tf, v.aw_bits.prot, NAME + "_aw_bits_prot");
sc_trace(tf, v.aw_bits.qos, NAME + "_aw_bits_qos");
sc_trace(tf, v.aw_bits.region, NAME + "_aw_bits_region");
sc_trace(tf, v.aw_id, NAME + "_aw_id");
sc_trace(tf, v.aw_user, NAME + "_aw_user");
sc_trace(tf, v.w_valid, NAME + "_w_valid");
sc_trace(tf, v.w_data, NAME + "_w_data");
sc_trace(tf, v.w_last, NAME + "_w_last");
sc_trace(tf, v.w_strb, NAME + "_w_strb");
sc_trace(tf, v.w_user, NAME + "_w_user");
sc_trace(tf, v.b_ready, NAME + "_b_ready");
sc_trace(tf, v.ar_valid, NAME + "_ar_valid");
sc_trace(tf, v.ar_bits.addr, NAME + "_ar_bits_addr");
sc_trace(tf, v.ar_bits.len, NAME + "_ar_bits_len");
sc_trace(tf, v.ar_bits.size, NAME + "_ar_bits_size");
sc_trace(tf, v.ar_bits.burst, NAME + "_ar_bits_burst");
sc_trace(tf, v.ar_bits.lock, NAME + "_ar_bits_lock");
sc_trace(tf, v.ar_bits.cache, NAME + "_ar_bits_cache");
sc_trace(tf, v.ar_bits.prot, NAME + "_ar_bits_prot");
sc_trace(tf, v.ar_bits.qos, NAME + "_ar_bits_qos");
sc_trace(tf, v.ar_bits.region, NAME + "_ar_bits_region");
sc_trace(tf, v.ar_id, NAME + "_ar_id");
sc_trace(tf, v.ar_user, NAME + "_ar_user");
sc_trace(tf, v.r_ready, NAME + "_r_ready");
}
inline friend ostream &operator << (ostream &os,
axi4_master_out_type const &v) {
os << "("
|
<< v.aw_valid << ","
<< v.aw_bits.addr << ","
<< v.aw_bits.len << ","
<< v.aw_bits.size << ","
<< v.aw_bits.burst << ","
<< v.aw_bits.lock << ","
<< v.aw_bits.cache << ","
<< v.aw_bits.prot << ","
<< v.aw_bits.qos << ","
<< v.aw_bits.region << ","
<< v.aw_id << ","
<< v.aw_user << ","
<< v.w_valid << ","
<< v.w_data << ","
<< v.w_last << ","
<< v.w_strb << ","
<< v.w_user << ","
<< v.b_ready << ","
<< v.ar_valid << ","
<< v.ar_bits.addr << ","
<< v.ar_bits.len << ","
<< v.ar_bits.size << ","
<< v.ar_bits.burst << ","
<< v.ar_bits.lock << ","
<< v.ar_bits.cache << ","
<< v.ar_bits.prot << ","
<< v.ar_bits.qos << ","
<< v.ar_bits.region << ","
<< v.ar_id << ","
<< v.ar_user << ","
<< v.r_ready << ")";
return os;
}
public:
bool aw_valid;
axi4_metadata_type aw_bits;
sc_uint<CFG_SYSBUS_ID_BITS> aw_id;
sc_uint<CFG_SYSBUS_USER_BITS> aw_user;
bool w_valid;
sc_uint<CFG_SYSBUS_DATA_BITS> w_data;
bool w_last;
sc_uint<CFG_SYSBUS_DATA_BYTES> w_strb;
sc_uint<CFG_SYSBUS_USER_BITS> w_user;
bool b_ready;
bool ar_valid;
axi4_metadata_type ar_bits;
sc_uint<CFG_SYSBUS_ID_BITS> ar_id;
sc_uint<CFG_SYSBUS_USER_BITS> ar_user;
bool r_ready;
};
// @brief Master device empty value.
// @warning If the master is not connected to the vector begin vector value
// MUST BE initialized by this value.
static const axi4_master_out_type axi4_master_out_none;
// @brief Master device input signals.
class axi4_master_in_type {
public:
axi4_master_in_type() {
aw_ready = 0;
w_ready = 0;
b_valid = 0;
b_resp = 0;
b_id = 0;
b_user = 0;
ar_ready = 0;
r_valid = 0;
r_resp = 0;
r_data = 0;
r_last = 0;
r_id = 0;
r_user = 0;
}
axi4_master_in_type(bool aw_ready_,
bool w_ready_,
bool b_valid_,
sc_uint<2> b_resp_,
sc_uint<CFG_SYSBUS_ID_BITS> b_id_,
sc_uint<CFG_SYSBUS_USER_BITS> b_user_,
bool ar_ready_,
bool r_valid_,
sc_uint<2> r_resp_,
sc_uint<CFG_SYSBUS_DATA_BITS> r_data_,
bool r_last_,
sc_uint<CFG_SYSBUS_ID_BITS> r_id_,
sc_uint<CFG_SYSBUS_USER_BITS> r_user_) {
aw_ready = aw_ready_;
w_ready = w_ready_;
b_valid = b_valid_;
b_resp = b_resp_;
b_id = b_id_;
b_user = b_user_;
ar_ready = ar_ready_;
r_valid = r_valid_;
r_resp = r_resp_;
r_data = r_data_;
r_last = r_last_;
r_id = r_id_;
r_user = r_user_;
}
inline bool operator == (const axi4_master_in_type &rhs) const {
bool ret = true;
ret = ret
&& rhs.aw_ready == aw_ready
&& rhs.w_ready == w_ready
&& rhs.b_valid == b_valid
&& rhs.b_resp == b_resp
&& rhs.b_id == b_id
&& rhs.b_user == b_user
&& rhs.ar_ready == ar_ready
&& rhs.r_valid == r_valid
&& rhs.r_resp == r_resp
&& rhs.r_data == r_data
&& rhs.r_last == r_last
&& rhs.r_id == r_id
&& rhs.r_user == r_user;
return ret;
}
inline axi4_master_in_type& operator = (const axi4_master_in_type &rhs) {
aw_ready = rhs.aw_ready;
w_ready = rhs.w_ready;
b_valid = rhs.b_valid;
b_resp = rhs.b_resp;
b_id = rhs.b_id;
b_user = rhs.b_user;
ar_ready = rhs.ar_ready;
r_valid = rhs.r_valid;
r_resp = rhs.r_resp;
r_data = rhs.r_data;
r_last = rhs.r_last;
r_id = rhs.r_id;
r_user = rhs.r_user;
return *this;
}
inline friend void sc_trace(sc_trace_file *tf,
const axi4_master_in_type&v,
const std::string &NAME) {
sc_trace(tf, v.aw_ready, NAME + "_aw_ready");
sc_trace(tf, v.w_ready, NAME + "_w_ready");
sc_trace(tf, v.b_valid, NAME + "_b_valid");
sc_trace(tf, v.b_resp, NAME + "_b_resp");
sc_trace(tf, v.b_id, NAME + "_b_id");
sc_trace(tf, v.b_user, NAME + "_b_user");
sc_trace(tf, v.ar_ready, NAME + "_ar_ready");
sc_trace(tf, v.r_valid, NAME + "_r_valid");
sc_trace(tf, v.r_resp, NAME + "_r_resp");
sc_trace(tf, v.r_data, NAME + "_r_data");
sc_trace(tf, v.r_last, NAME + "_r_last");
sc_trace(tf, v.r_id, NAME + "_r_id");
sc_trace(tf, v.r_user, NAME + "_r_user");
}
inline friend ostream &operator << (ostream &os,
axi4_master_in_type const &v) {
os << "("
<< v.aw_ready << ","
<< v.w_ready << ","
<< v.b_valid << ","
<< v.b_resp << ","
<< v.b_id << ","
<< v.b_user << ","
<< v.ar_ready << ","
<< v.r_valid << ","
<< v.r_resp << ","
<< v.r_data << ","
<< v.r_last << ","
<< v.r_id << ","
<< v.r_user << ")";
return os;
}
public:
bool aw_ready;
bool w_ready;
bool b_valid;
sc_uint<2> b_resp;
sc_uint<CFG_SYSBUS_ID_BITS> b_id;
sc_uint<CFG_SYSBUS_USER_BITS> b_user;
bool ar_ready;
bool r_valid;
sc_uint<2> r_resp;
sc_uint<CFG_SYSBUS_DATA_BITS> r_data;
bool r_last;
sc_uint<CFG_SYSBUS_ID_BITS> r_id;
sc_uint<CFG_SYSBUS_USER_BITS> r_user;
};
static const axi4_master_in_type axi4_master_in_none;
class axi4_slave_in_type {
public:
axi4_slave_in_type() {
aw_valid = 0;
aw_bits.addr = 0;
aw_bits.len = 0;
aw_bits.size = 0;
aw_bits.burst = AXI_BURST_INCR;
aw_bits.lock = 0;
aw_bits.cache = 0;
aw_bits.prot = 0;
aw_bits.qos = 0;
aw_bits.region = 0;
aw_id = 0;
aw_user = 0;
w_valid = 0;
w_data = 0;
w_last = 0;
w_strb = 0;
w_user = 0;
b_ready = 0;
ar_valid = 0;
ar_bits.addr = 0;
ar_bits.len = 0;
ar_bits.size = 0;
ar_bits.burst = AXI_BURST_INCR;
ar_bits.lock = 0;
ar_bits.cache = 0;
ar_bits.prot = 0;
ar_bits.qos = 0;
ar_bits.region = 0;
ar_id = 0;
ar_user = 0;
r_ready = 0;
}
axi4_slave_in_type(bool aw_valid_,
axi4_metadata_type aw_bits_,
sc_uint<CFG_SYSBUS_ID_BITS> aw_id_,
sc_uint<CFG_SYSBUS_USER_BITS> aw_user_,
bool w_valid_,
sc_uint<CFG_SYSBUS_DATA_BITS> w_data_,
bool w_last_,
sc_uint<CFG_SYSBUS_DATA_BYTES> w_strb_,
sc_uint<CFG_SYSBUS_USER_BITS> w_user_,
bool b_ready_,
bool ar_valid_,
axi4_metadata_type ar_bits_,
sc_uint<CFG_SYSBUS_ID_BITS> ar_id_,
sc_uint<CFG_SYSBUS_USER_BITS> ar_user_,
bool r_ready_) {
aw_valid = aw_valid_;
aw_bits = aw_bits_;
aw_id = aw_id_;
aw_user = aw_user_;
w_valid = w_valid_;
w_data = w_data_;
w_last = w_last_;
w_strb = w_strb_;
w_user = w_user_;
b_ready = b_ready_;
ar_valid = ar_valid_;
ar_bits = ar_bits_;
ar_id = ar_id_;
ar_user = ar_user_;
r_ready = r_ready_;
}
inline bool operator == (const axi4_slave_in_type &rhs) const {
bool ret = true;
ret = ret
&& rhs.aw_valid == aw_valid
&& rhs.aw_bits.addr == aw_bits.addr
&& rhs.aw_bits.len == aw_bits.len
&& rhs.aw_bits.size == aw_bits.size
&& rhs.aw_bits.burst == aw_bits.burst
&& rhs.aw_bits.lock == aw_bits.lock
&& rhs.aw_bits.cache == aw_bits.cache
&& rhs.aw_bits.prot == aw_bits.prot
&& rhs.aw_bits.qos == aw_bits.qos
&& rhs.aw_bits.region == aw_bits.region
&& rhs.aw_id == aw_id
&& rhs.aw_user == aw_user
&& rhs.w_valid == w_valid
&& rhs.w_data == w_data
&& rhs.w_last == w_last
&& rhs.w_strb == w_strb
&& rhs.w_user == w_user
&& rhs.b_ready == b_ready
&& rhs.ar_valid == ar_valid
&& rhs.ar_bits.addr == ar_bits.addr
&& rhs.ar_bits.len == ar_bits.len
&& rhs.ar_bits.size == ar_bits.size
&& rhs.ar_bits.burst == ar_bits.burst
&& rhs.ar_bits.lock == ar_bits.lock
&& rhs.ar_bits.cache == ar_bits.cache
&& rhs.ar_bits.prot == ar_bits.prot
&& rhs.ar_bits.qos == ar_bits.qos
&& rhs.ar_bits.region == ar_bits.region
&& rhs.ar_id == ar_id
&& rhs.ar_user == ar_user
&& rhs.r_ready == r_ready;
return ret;
}
inline axi4_slave_in_type& operator = (const axi4_slave_in_type &rhs) {
aw_valid = rhs.aw_valid;
aw_bits.addr = rhs.aw_bits.addr;
aw_bits.len = rhs.aw_bits.len;
aw_bits.size = rhs.aw_bits.size;
aw_bits.burst = rhs.aw_bits.burst;
aw_bits.lock = rhs.aw_bits.lock;
aw_bits.cache = rhs.aw_bits.cache;
aw_bits.prot = rhs.aw_bits.prot;
aw_bits.qos = rhs.aw_bits.qos;
aw_bits.region = rhs.aw_bits.region;
aw_id = rhs.aw_id;
aw_user = rhs.aw_user;
w_valid = rhs.w_valid;
w_data = rhs.w_data;
w_last = rhs.w_last;
w_strb = rhs.w_strb;
w_user = rhs.w_user;
b_ready = rhs.b_ready;
ar_valid = rhs.ar_valid;
ar_bits.addr = rhs.ar_bits.addr;
ar_bits.len = rhs.ar_bits.len;
ar_bits.size = rhs.ar_bits.size;
ar_bits.burst = rhs.ar_bits.burst;
ar_bits.lock = rhs.ar_bits.lock;
ar_bits.cache = rhs.ar_bits.cache;
ar_bits.prot = rhs.ar_bits.prot;
ar_bits.qos = rhs.ar_bits.qos;
ar_bits.region = rhs.ar_bits.region;
ar_id = rhs.ar_id;
ar_user = rhs.ar_user;
r_ready = rhs.r_ready;
return *this;
}
inline friend void sc_trace(sc_trace_file *tf,
const axi4_slave_in_type&v,
const std::string &NAME) {
sc_trace(tf, v.aw_valid, NAME + "_aw_valid");
sc_trace(tf, v.aw_bits.addr, NAME + "_aw_bits_addr");
sc_trace(tf, v.aw_bits.len, NAME + "_aw_bits_len");
sc_trace(tf, v.aw_bits.size, NAME + "_aw_bits_size");
sc_trace(tf, v.aw_bits.burst, NAME + "_aw_bits_burst");
sc_trace(tf, v.aw_bits.lock, NAME + "_aw_bits_lock");
sc_trace(tf, v.aw_bits.cache, NAME + "_aw_bits_cache");
sc_trace(tf, v.aw_bits.prot, NAME + "_aw_bits_prot");
sc_trace(tf, v.aw_bits.qos, NAME + "_aw_bits_qos");
sc_trace(tf, v.aw_bits.region, NAME + "_aw_bits_region");
sc_trace(tf, v.aw_id, NAME + "_aw_id");
sc_trace(tf, v.aw_user, NAME + "_aw_user");
sc_trace(tf, v.w_valid, NAME + "_w_valid");
sc_trace(tf, v.w_data, NAME + "_w_data");
sc_trace(tf, v.w_last, NAME + "_w_last");
sc_trace(tf, v.w_strb, NAME + "_w_strb");
sc_trace(tf, v.w_user, NAME + "_w_user");
sc_trace(tf, v.b_ready, NAME + "_b_ready");
sc_trace(tf, v.ar_valid, NAME + "_ar_valid");
sc_trace(tf, v.ar_bits.addr, NAME + "_ar_bits_addr");
sc_trace(tf, v.ar_bits.len, NAME + "_ar_bits_len");
sc_trace(tf, v.ar_bits.size, NAME + "_ar_bits_size");
sc_trace(tf, v.ar_bits.burst, NAME + "_ar_bits_burst");
sc_trace(tf, v.ar_bits.lock, NAME + "_ar_bits_lock");
sc_trace(tf, v.ar_bits.cache, NAME + "_ar_bits_cache");
sc_trace(tf, v.ar_bits.prot, NAME + "_ar_bits_prot");
sc_trace(tf, v.ar_bits.qos, NAME + "_ar_bits_qos");
sc_trace(tf, v.ar_bits.region, NAME + "_ar_bits_region");
sc_trace(tf, v.ar_id, NAME + "_ar_id");
sc_trace(tf, v.ar_user, NAME + "_ar_user");
sc_trace(tf, v.r_ready, NAME + "_r_ready");
}
inline friend ostream &operator << (ostream &os,
axi4_slave_in_type const &v) {
os << "("
<< v.aw_valid << ","
<< v.aw_bits.addr << ","
<< v.aw_bits.len << ","
<< v.aw_bits.size << ","
<< v.aw_bits.burst << ","
<< v.aw_bits.lock << ","
<< v.aw_bits.cache << ","
<< v.aw_bits.prot << ","
<< v.aw_bits.qos << ","
<< v.aw_bits.region << ","
<< v.aw_id << ","
<< v.aw_user << ","
<< v.w_valid << ","
<< v.w_data << ","
<< v.w_last << ","
<< v.w_strb << ","
<< v.w_user << ","
<< v.b_ready << ","
<< v.ar_valid << ","
<< v.ar_bits.addr << ","
<< v.ar_bits.len << ","
<< v.ar_bits.size << ","
<< v.ar_bits.burst << ","
<< v.ar_bits.lock << ","
<< v.ar_bits.cache << ","
<< v.ar_bits.prot << ","
<< v.ar_bits.qos << ","
<< v.ar_bits.region << ","
<< v.ar_id << ","
<< v.ar_user << ","
<< v.r_ready << ")";
return os;
}
public:
bool aw_valid;
axi4_metadata_type aw_bits;
sc_uint<CFG_SYSBUS_ID_BITS> aw_id;
sc_uint<CFG_SYSBUS_USER_BITS> aw_user;
bool w_valid;
sc_uint<CFG_SYSBUS_DATA_BITS> w_data;
bool w_last;
sc_uint<CFG_SYSBUS_DATA_BYTES> w_strb;
sc_uint<CFG_SYSBUS_USER_BITS> w_user;
bool b_ready;
bool ar_valid;
axi4_metadata_type ar_bits;
sc_uint<CFG_SYSBUS_ID_BITS> ar_id;
sc_uint<CFG_SYSBUS_USER_BITS> ar_user;
bool r_ready;
};
static const axi4_slave_in_type axi4_slave_in_none;
class axi4_slave_out_type {
public:
axi4_slave_out_type() {
aw_ready = 0;
w_ready = 0;
b_valid = 0;
b_resp = 0;
b_id = 0;
b_user = 0;
ar_ready = 0;
r_valid = 0;
r_resp = 0;
r_data = 0;
r_last = 0;
r_id = 0;
r_user = 0;
}
axi4_slave_out_type(bool aw_ready_,
bool w_ready_,
bool b_valid_,
sc_uint<2> b_resp_,
sc_uint<CFG_SYSBUS_ID_BITS> b_id_,
sc_uint<CFG_SYSBUS_USER_BITS> b_user_,
bool ar_ready_,
bool r_valid_,
sc_uint<2> r_resp_,
sc_uint<CFG_SYSBUS_DATA_BITS> r_data_,
bool r_last_,
sc_uint<CFG_SYSBUS_ID_BITS> r_id_,
sc_uint<CFG_SYSBUS_USER_BITS> r_user_) {
aw_ready = aw_ready_;
w_ready = w_ready_;
b_valid = b_valid_;
b_resp = b_resp_;
b_id = b_id_;
b_user = b_user_;
ar_ready = ar_ready_;
r_valid = r_valid_;
r_resp = r_resp_;
r_data = r_data_;
r_last = r_last_;
r_id = r_id_;
r_user = r_user_;
}
inline bool operator == (const axi4_slave_out_type &rhs) const {
bool ret = true;
ret = ret
&& rhs.aw_ready == aw_ready
&& rhs.w_ready == w_ready
&& rhs.b_valid == b_valid
&& rhs.b_resp == b_resp
&& rhs.b_id == b_id
&& rhs.b_user == b_user
&& rhs.ar_ready == ar_ready
&& rhs.r_valid == r_valid
&& rhs.r_resp == r_resp
&& rhs.r_data == r_data
&& rhs.r_last == r_last
&& rhs.r_id == r_id
&& rhs.r_user == r_user;
return ret;
}
inline axi4_slave_out_type& operator = (const axi4_slave_out_type &rhs) {
aw_ready = rhs.aw_ready;
w_ready = rhs.w_ready;
b_valid = rhs.b_valid;
b_resp = rhs.b_resp;
b_id = rhs.b_id;
b_user = rhs.b_user;
ar_ready = rhs.ar_ready;
r_valid = rhs.r_valid;
r_resp = rhs.r_resp;
r_data = rhs.r_data;
r_last = rhs.r_last;
r_id = rhs.r_id;
r_user = rhs.r_user;
return *this;
}
inline friend void sc_trace(sc_trace_file *tf,
const axi4_slave_out_type&v,
const std::string &NAME) {
sc_trace(tf, v.aw_ready, NAME + "_aw_ready");
sc_trace(tf, v.w_ready, NAME + "_w_ready");
sc_trace(tf, v.b_valid, NAME + "_b_valid");
sc_trace(tf, v.b_resp, NAME + "_b_resp");
sc_trace(tf, v.b_id, NAME + "_b_id");
sc_trace(tf, v.b_user, NAME + "_b_user");
sc_trace(tf, v.ar_ready, NAME + "_ar_ready");
sc_trace(tf, v.r_valid, NAME + "_r_valid");
sc_trace(tf, v.r_resp, NAME + "_r_resp");
sc_trace(tf, v.r_data, NAME + "_r_data");
sc_trace(tf, v.r_last, NAME + "_r_last");
sc_trace(tf, v.r_id, NAME + "_r_id");
sc_trace(tf, v.r_user, NAME + "_r_user");
}
inline friend ostream &operator << (ostream &os,
axi4_slave_out_type const &v) {
os << "("
<< v.aw_ready << ","
<< v.w_ready << ","
<< v.b_valid << ","
<< v.b_resp << ","
<< v.b_id << ","
<< v.b_user << ","
<< v.ar_ready << ","
<< v.r_valid << ","
<< v.r_resp << ","
<< v.r_data << ","
<< v.r_last << ","
<< v.r_id << ","
<< v.r_user << ")";
return os;
}
public:
bool aw_ready;
bool w_ready;
bool b_valid;
sc_uint<2> b_resp;
sc_uint<CFG_SYSBUS_ID_BITS> b_id;
sc_uint<CFG_SYSBUS_USER_BITS> b_user;
bool ar_ready;
bool r_valid;
sc_uint<2> r_resp;
sc_uint<CFG_SYSBUS_DATA_BITS> r_data;
bool r_last;
sc_uint<CFG_SYSBUS_ID_BITS> r_id;
sc_uint<CFG_SYSBUS_USER_BITS> r_user;
};
static const axi4_slave_out_type axi4_slave_out_none;
class apb_in_type {
public:
apb_in_type() {
paddr = 0;
pprot = 0;
pselx = 0;
penable = 0;
pwrite = 0;
pwdata = 0;
pstrb = 0;
}
apb_in_type(sc_uint<32> paddr_,
sc_uint<3> pprot_,
bool pselx_,
bool penable_,
bool pwrite_,
sc_uint<32> pwdata_,
sc_uint<4> pstrb_) {
paddr = paddr_;
pprot = pprot_;
pselx = pselx_;
penable = penable_;
pwrite = pwrite_;
pwdata = pwdata_;
pstrb = pstrb_;
}
inline bool operator == (const apb_in_type &rhs) const {
bool ret = true;
ret = ret
&& rhs.paddr == paddr
&& rhs.pprot == pprot
&& rhs.pselx == pselx
&& rhs.penable == penable
&& rhs.pwrite == pwrite
&& rhs.pwdata == pwdata
&& rhs.pstrb == pstrb;
return ret;
}
inline apb_in_type& operator = (const apb_in_type &rhs) {
paddr = rhs.paddr;
pprot = rhs.pprot;
pselx = rhs.pselx;
penable = rhs.penable;
pwrite = rhs.pwrite;
pwdata = rhs.pwdata;
pstrb = rhs.pstrb;
return *this;
}
inline friend void sc_trace(sc_trace_file *tf,
const apb_in_type&v,
const std::string &NAME) {
sc_trace(tf, v.paddr, NAME + "_paddr");
sc_tr |
ace(tf, v.pprot, NAME + "_pprot");
sc_trace(tf, v.pselx, NAME + "_pselx");
sc_trace(tf, v.penable, NAME + "_penable");
sc_trace(tf, v.pwrite, NAME + "_pwrite");
sc_trace(tf, v.pwdata, NAME + "_pwdata");
sc_trace(tf, v.pstrb, NAME + "_pstrb");
}
inline friend ostream &operator << (ostream &os,
apb_in_type const &v) {
os << "("
<< v.paddr << ","
<< v.pprot << ","
<< v.pselx << ","
<< v.penable << ","
<< v.pwrite << ","
<< v.pwdata << ","
<< v.pstrb << ")";
return os;
}
public:
sc_uint<32> paddr;
sc_uint<3> pprot;
bool pselx;
bool penable;
bool pwrite;
sc_uint<32> pwdata;
sc_uint<4> pstrb;
};
static const apb_in_type apb_in_none;
class apb_out_type {
public:
apb_out_type() {
pready = 0;
prdata = 0;
pslverr = 0;
}
apb_out_type(bool pready_,
sc_uint<32> prdata_,
bool pslverr_) {
pready = pready_;
prdata = prdata_;
pslverr = pslverr_;
}
inline bool operator == (const apb_out_type &rhs) const {
bool ret = true;
ret = ret
&& rhs.pready == pready
&& rhs.prdata == prdata
&& rhs.pslverr == pslverr;
return ret;
}
inline apb_out_type& operator = (const apb_out_type &rhs) {
pready = rhs.pready;
prdata = rhs.prdata;
pslverr = rhs.pslverr;
return *this;
}
inline friend void sc_trace(sc_trace_file *tf,
const apb_out_type&v,
const std::string &NAME) {
sc_trace(tf, v.pready, NAME + "_pready");
sc_trace(tf, v.prdata, NAME + "_prdata");
sc_trace(tf, v.pslverr, NAME + "_pslverr");
}
inline friend ostream &operator << (ostream &os,
apb_out_type const &v) {
os << "("
<< v.pready << ","
<< v.prdata << ","
<< v.pslverr << ")";
return os;
}
public:
bool pready; // when 1 it breaks callback to functional model
sc_uint<32> prdata;
bool pslverr;
};
static const apb_out_type apb_out_none;
} // namespace debugger
|
#include <systemc.h>
#include <iostream>
#include "constants.h"
#include "fifo.h"
SC_MODULE(decod) {
/*****************************************************
Interface with REG
******************************************************/
// adresses of Rs and Rd
sc_out<sc_uint<6>> RADR1_SD;
sc_out<sc_uint<6>> RADR2_SD;
// Data read in registers
sc_in<sc_uint<32>> RDATA1_SR;
sc_in<sc_uint<32>> RDATA2_SR;
// Current value of PC
sc_in<sc_uint<32>> READ_PC_SR;
// Port to write into PC
sc_out<sc_uint<32>> WRITE_PC_SD;
sc_out<bool> WRITE_PC_ENABLE_SD;
/*****************************************************
Interface with EXE
******************************************************/
sc_out<sc_uint<32>> OP1_RD;
sc_out<sc_uint<32>> OP2_RD;
/* Command sent to EXE.
In case of a shift :
- 0 : Shift Left Logical (sll)
- 1 : Shift Right Logical (srl)
- 2 : Shift Right Arithmetic (sra)
In case of an ALU operation :
- 0 : add
- 1 : and
- 2 : or
- 3 : xor
In case of an SLT operation
- 0 : slt
- 1 : sltu
*/
sc_out<sc_uint<2>> EXE_CMD_RD;
sc_out<bool> NEG_OP2_RD; // negates the second operator, to do substractions
sc_out<bool> WB_RD; // write back the result in reg
sc_out<sc_uint<6>> EXE_DEST_SD; // the destination register
/* operation types :
- 0 : alu
- 1 : shifter
- 2 : slt
*/
sc_out<sc_uint<3>> OPTYPE_RD;
sc_out<sc_uint<32>> MEM_DATA_RD; // data sent to mem for storage
sc_out<bool> MEM_LOAD_RD; // a memory load
sc_out<bool> MEM_STORE_RD; // a memory store
sc_out<bool> MEM_SIGN_EXTEND_RD; // loads and stores can be signed or unsigned
sc_out<sc_uint<2>> MEM_SIZE_RD; // mem accesses can be words, half words or bytes
/*****************************************************
Interface with DEC2IF
******************************************************/
sc_in<bool> DEC2IF_POP_SI; // The POP signal coming from Ifetch
sc_out<bool> DEC2IF_EMPTY_SD;
sc_out<sc_bv<32>> PC_RD; // the output of the fifo, containing the PC of the next instruction
/*****************************************************
Interface with IF2DEC
******************************************************/
sc_in<sc_bv<32>> INSTR_RI; // The instruction coming from Ifetch
sc_in<sc_uint<32>> PC_RI; // The pc of the instruction being executed
sc_in<bool> IF2DEC_EMPTY_SI;
sc_out<bool> IF2DEC_POP_SD; // the POP signal sent to Ifetch
sc_out<bool> IF2DEC_FLUSH_SD; // Signal sent to IFETCH to flush all instructions
/*****************************************************
Interface with DEC2EXE
******************************************************/
sc_in<bool> DEC2EXE_POP_SE; // The POP signal coming from EXE
sc_out<bool> DEC2EXE_EMPTY_SD;
sc_signal<sc_bv<DEC2EXE_SIZE>> dec2exe_out_sd;
/*****************************************************
BYPASSES
******************************************************/
// see the bypasses process in dec.cpp, or the documentation, for an explanation
// pipeline data coming from the end of EXE
sc_in<sc_uint<6>> DEST_RE; // the destination register of the data
sc_in<sc_uint<32>> EXE_RES_RE; // the data
sc_in<bool> MEM_LOAD_RE; // whether it is a memory load
sc_in<bool> EXE2MEM_EMPTY_SE; // whether the data is valid
// pipeline data coming from the end of MEM
sc_in<sc_uint<6>> DEST_RM; // the destination register of the data
sc_in<sc_uint<32>> MEM_RES_RM; // the data
sc_in<bool> MEM2WBK_EMPTY_SM; // Whether the data is valid
// Bypass outputs for EXE
sc_out<sc_uint<6>> BP_RADR1_RD; // the register of the data in OP1
sc_out<sc_uint<6>> BP_RADR2_RD; // the register of the data in OP2
sc_out<bool> BLOCK_BP_RD; // prevent any further bypasses
// General Interface :
sc_in_clk CLK;
sc_in<bool> RESET;
// Signals :
sc_signal<sc_uint<32>> rdata1_sd;
sc_signal<sc_uint<32>> rdata2_sd;
sc_signal<bool> invalid_operand_sd;
// fifo dec2if :
sc_signal<sc_bv<32>> dec2if_in_sd; // pc sent to fifo
sc_signal<bool> dec2if_push_sd;
sc_signal<bool> dec2if_full_sd;
sc_signal<sc_bv<32>> dec2if_out_sd;
// fifo dec2exe :
sc_signal<sc_bv<DEC2EXE_SIZE>> dec2exe_in_sd;
sc_signal<bool> dec2exe_push_sd;
sc_signal<bool> dec2exe_full_sd;
// Instruction format type :
sc_signal<bool> r_type_inst_sd; // R type format
sc_signal<bool> i_type_inst_sd; // I type format
sc_signal<bool> s_type_inst_sd; // S type format
sc_signal<bool> b_type_inst_sd; // B type format
sc_signal<bool> u_type_inst_sd; // U type format
sc_signal<bool> j_type_inst_sd; // J type format
sc_signal<bool> jalr_type_inst_sd; // JALR has a specific opcode
// R-type Instructions :
sc_signal<bool> add_i_sd;
sc_signal<bool> slt_i_sd;
sc_signal<bool> sltu_i_sd;
sc_signal<bool> and_i_sd;
sc_signal<bool> or_i_sd;
sc_signal<bool> xor_i_sd;
sc_signal<bool> sll_i_sd;
sc_signal<bool> srl_i_sd;
sc_signal<bool> sub_i_sd;
sc_signal<bool> sra_i_sd;
// I-type Instructions :
sc_signal<bool> addi_i_sd;
sc_signal<bool> slti_i_sd;
sc_signal<bool> sltiu_i_sd;
sc_signal<bool> andi_i_sd;
sc_signal<bool> ori_i_sd;
sc_signal<bool> xori_i_sd;
sc_signal<bool> jalr_i_sd;
sc_signal<bool> fence_i_sd;
// I-type shift instructions :
sc_signal<bool> slli_i_sd;
sc_signal<bool> srli_i_sd;
sc_signal<bool> srai_i_sd;
// I-type load instructions :
sc_signal<bool> lw_i_sd;
sc_signal<bool> lh_i_sd;
sc_signal<bool> lhu_i_sd;
sc_signal<bool> lb_i_sd;
sc_signal<bool> lbu_i_sd;
// B-type Instruction :
sc_signal<bool> beq_i_sd;
sc_signal<bool> bne_i_sd;
sc_signal<bool> blt_i_sd;
sc_signal<bool> bge_i_sd;
sc_signal<bool> bltu_i_sd;
sc_signal<bool> bgeu_i_sd;
// U-type Instruction :
sc_signal<bool> lui_i_sd;
sc_signal<bool> auipc_i_sd;
// J-type Instruction :
sc_signal<bool> jal_i_sd;
// S-type Instructions :
sc_signal<bool> sw_i_sd;
sc_signal<bool> sh_i_sd;
sc_signal<bool> sb_i_sd;
// Offset for branch :
sc_signal<sc_uint<32>> offset_branch_sd;
// PC gestion :
sc_signal<bool> inc_pc_sd;
sc_signal<bool> jump_sd;
// Pipeline Gestion
sc_signal<bool> stall_sd;
sc_signal<bool> normal_sd;
sc_signal<bool> block_in_dec_sd;
// Internal signals :
sc_signal<sc_uint<6>> adr_dest_sd;
sc_signal<sc_uint<32>> exe_op1_sd;
sc_signal<sc_uint<32>> exe_op2_sd;
sc_signal<sc_uint<32>> mem_data_sd;
sc_signal<sc_uint<2>> mem_size_sd;
sc_signal<bool> mem_load_sd;
sc_signal<bool> mem_store_sd;
sc_signal<sc_uint<2>> exe_cmd_sd;
sc_signal<sc_uint<2>> optype_sd;
sc_signal<bool> exe_neg_op2_sd;
sc_signal<bool> exe_wb_sd;
sc_signal<bool> mem_sign_extend_sd;
sc_signal<bool> block_bp_sd;
// Instance used :
fifo<32> dec2if;
fifo<DEC2EXE_SIZE> dec2exe;
void concat_dec2exe();
void unconcat_dec2exe();
void decoding_instruction_type();
void decoding_instruction();
void pre_reg_read_decoding();
void post_reg_read_decoding();
void pc_inc();
void bypasses();
void stall_method();
void trace(sc_trace_file * tf);
SC_CTOR(decod) : dec2if("dec2if"), dec2exe("dec2exe") {
dec2if.DATAIN_S(dec2if_in_sd);
dec2if.DATAOUT_R(PC_RD);
dec2if.EMPTY_S(DEC2IF_EMPTY_SD);
dec2if.FULL_S(dec2if_full_sd);
dec2if.PUSH_S(dec2if_push_sd);
dec2if.POP_S(DEC2IF_POP_SI);
dec2if.CLK(CLK);
dec2if.RESET(RESET);
dec2exe.DATAIN_S(dec2exe_in_sd);
dec2exe.DATAOUT_R(dec2exe_out_sd);
dec2exe.EMPTY_S(DEC2EXE_EMPTY_SD);
dec2exe.FULL_S(dec2exe_full_sd);
dec2exe.PUSH_S(dec2exe_push_sd);
dec2exe.POP_S(DEC2EXE_POP_SE);
dec2exe.CLK(CLK);
dec2exe.RESET(RESET);
SC_METHOD(concat_dec2exe)
sensitive << dec2exe_in_sd << exe_op1_sd << exe_op2_sd << exe_cmd_sd << exe_neg_op2_sd
<< exe_wb_sd << mem_data_sd << mem_load_sd << mem_store_sd << mem_sign_extend_sd
<< mem_size_sd << optype_sd << adr_dest_sd << slti_i_sd << slt_i_sd << sltiu_i_sd
<< sltu_i_sd << RADR1_SD << RADR2_SD << block_bp_sd;
SC_METHOD(unconcat_dec2exe)
sensitive << dec2exe_out_sd;
SC_METHOD(stall_method)
sensitive << b_type_inst_sd << jalr_type_inst_sd << j_type_inst_sd << invalid_operand_sd
<< DEC2EXE_EMPTY_SD << EXE2MEM_EMPTY_SE << IF2DEC_EMPTY_SI << dec2exe_full_sd
<< block_in_dec_sd;
SC_METHOD(decoding_instruction_type)
sensitive << INSTR_RI << READ_PC_SR;
SC_METHOD(decoding_instruction)
sensitive << INSTR_RI;
SC_METHOD(pre_reg_read_decoding)
sensitive << INSTR_RI << r_type_inst_sd << i_type_inst_sd << i_type_inst_sd
<< s_type_inst_sd << b_type_inst_sd << u_type_inst_sd << j_type_inst_sd
<< jalr_type_inst_sd << beq_i_sd << bne_i_sd << blt_i_sd << bge_i_sd << bltu_i_sd
<< bgeu_i_sd << fence_i_sd << RESET;
SC_METHOD(post_reg_read_decoding)
sensitive << i_type_inst_sd << s_type_inst_sd << b_type_inst_sd << u_type_inst_sd
<< j_type_inst_sd << jalr_type_inst_sd << beq_i_sd << bne_i_sd << blt_i_sd
<< bge_i_sd << bltu_i_sd << bgeu_i_sd << IF2DEC_EMPTY_SI << dec2if_push_sd
<< READ_PC_SR << stall_sd << dec2if_push_sd << add_i_sd << slt_i_sd << sltu_i_sd
<< and_i_sd << or_i_sd << xor_i_sd << sll_i_sd << srl_i_sd << sub_i_sd << sra_i_sd
<< addi_i_sd << slti_i_sd << sltiu_i_sd << andi_i_sd << ori_i_sd << xori_i_sd
<< jalr_i_sd << slli_i_sd << srli_i_sd << srai_i_sd << lw_i_sd << lh_i_sd
<< lhu_i_sd << lb_i_sd << lbu_i_sd << beq_i_sd << bne_i_sd << blt_i_sd << bge_i_sd
<< bltu_i_sd << bgeu_i_sd << lui_i_sd << auipc_i_sd << jal_i_sd << sw_i_sd
<< sh_i_sd << sb_i_sd << j_type_inst_sd << jalr_type_inst_sd << dec2exe_push_sd
<< rdata1_sd << rdata2_sd << fence_i_sd << PC_RI;
SC_METHOD(pc_inc)
sensitive << CLK.pos() << READ_PC_SR << offset_branch_sd << inc_pc_sd << jump_sd << PC_RI
<< dec2if_full_sd << IF2DEC_EMPTY_SI << stall_sd;
SC_METHOD(bypasses);
sensitive << RDATA1_SR << RDATA2_SR << DEST_RE << EXE_RES_RE << DEST_RM
<< MEM_RES_RM << RADR1_SD << EXE_DEST_SD << RADR2_SD << EXE2MEM_EMPTY_SE
<< DEC2EXE_EMPTY_SD << MEM_LOAD_RE << MEM2WBK_EMPTY_SM;
reset_signal_is(RESET, false);
}
}; |
#ifndef CONTROLLER_TRANSACTOR_HH
#define CONTROLLER_TRANSACTOR_HH
#include <systemc.h>
#include <tlm.h>
#include <tlm_utils/tlm_quantumkeeper.h>
#include "global.hh"
class ControllerTransactor
: public sc_module
, public virtual tlm::tlm_fw_transport_if<>
{
public:
//TLM side
tlm::tlm_target_socket<> target_socket;
iostruct ioDataStruct;
type_splitter splitterDataStruct;
tlm::tlm_generic_payload* pending_transaction;
sc_time timing_annotation;
sc_event begin_write, end_write;
//TLM interfaces
virtual void b_transport(tlm::tlm_generic_payload& trans, sc_time& t);
virtual bool get_direct_mem_ptr(tlm::tlm_generic_payload& trans, tlm::tlm_dmi& dmi_data);
virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_time& t);
virtual unsigned int transport_dbg(tlm::tlm_generic_payload& trans);
//RTL side
//RTL ports
sc_in< sc_dt::sc_logic > clk;
sc_in<sc_uint<1> > dout_rdy; // xtea notify that the result is ready for valve
sc_out<sc_uint<1> > din_rdy;
sc_out<uint32_t> word00_in;
sc_out<uint32_t> word01_in;
sc_out<int > word1_in;
sc_out<sc_uint<32> > key0_in, key1_in, key2_in, key3_in;
sc_out<bool> mode_in;
sc_out<bool> rst;
//sc_signal<bool > rst;
//processes
void WRITEPROCESS();
//mandatory for TLM
//void sync();
void end_of_elaboration();
void reset();
SC_HAS_PROCESS(ControllerTransactor);
ControllerTransactor(sc_module_name name_);
};
#endif //CONTROLLER_TRANSACTOR_HH
|
#ifndef SC_GATES_PV_H
#define SC_GATES_PV_H
#include <QtXml>
//#include <QDomNodeList>
#include <systemc.h>
/**
* @brief The SyscLogicGate_pv::sc_core::sc_module class
* @details A generic SystemC module that implements a logic gate with N inputs and 1 output.
* The gate is combinational, i.e., the output is updated whenever any of the inputs changes.
* pv
*/
template <unsigned int N = 2, unsigned int W = 1>
class SyscLogicGate_pv : public ::sc_core::sc_module
{
public:
static_assert(N >= 2, "SyscLogicGate_pv DESIGN ERROR: N must be >= 2");
static_assert(W >= 1, "SyscLogicGate_pv DESIGN ERROR: W must be >= 1");
typedef sc_lv<W> data_t;
/**
* Data input(s)
* Array of pointers so each port name can be initialized in the constructor to 'd0', 'd1', and so on (instead of 'port_0', 'port_1', etc.)
* mapping is done as (*mux_object.d[index])(signal_to_bind_the_port) instead of mux_object.d[index](signal_to_bind_the_port)
* see https://stackoverflow.com/questions/35425052/how-to-initialize-a-systemc-port-name-which-is-an-array/35535730#35535730
*/
sc_vector<sc_in<data_t>> d;
// Data output
sc_out<data_t> y{"y"};
typedef SyscLogicGate_pv<N,W> SC_CURRENT_USER_MODULE;
SyscLogicGate_pv<N,W>(::sc_core::sc_module_name name) : ::sc_core::sc_module(name), d("d", N) {
SC_METHOD(combinational);
for (unsigned int i=0; i < N; i++)
{
sensitive << d[i];
}
}
virtual void combinational () {
data_t result(SC_LOGIC_X);
y.write(result);
}
static bool find(QString id, QDomNodeList children) {
for (int i = 0; i < children.size(); i++) {
QDomElement child = children.at(i).toElement();
if (child.attribute("id").toUpper() == id) {
return true;
}
}
}
static int getNInputs(QString gate, bool &ok) {
int res = -1;
ok = false;
(void)gate;
// Some code here to extract n from gate:
// Gates with single-bit ports -> and (= and2), and2, andn, nand, ... both lowercase and uppercase
// number of inputs (N) -> 2 2 n 2
// bits per input (W) -> 1 1 1 1
// Gates with w-bit ports -> and_w (= and2_w), and2_w, andn_w, nand_w, ... both lowercase and uppercase
// number of inputs (N) -> 2 2 n 2
// bits per input (W) -> w w w w
// ...
// In the end:
// a) any non-numerical string ended by a number: XXXXXXXnnnn
// b) any non-numerical string ended by a two numbers separated by _: XXXXXXXnnnn_wwww
// Resort to Qt Regular Expression x for help about extracting this
return res;
}
static int getWInputs(QString gate, bool &ok) {
int res = -1;
ok = false;
(void)gate;
// Some code here to extract w from gate:
// Gates with single-bit ports -> and (= and2), and2, andn, nand, ... both lowercase and uppercase
// number of inputs (N) -> 2 2 n 2
// bits per input (W) -> 1 1 1 1
// Gates with w-bit ports -> and_w (= and2_w), and2_w, andn_w, nand_w, ... both lowercase and uppercase
// number of inputs (N) -> 2 2 n 2
// bits per input (W) -> w w w w
// ...
// In the end:
// a) any non-numerical string ended by a number: XXXXXXXnnnn
// b) any non-numerical string ended by a two numbers separated by _: XXXXXXXnnnn_wwww
// Resort to Qt Regular Expression x for help about extracting this
return res;
}
static bool validate(QString gate, QString id, QDomElement gElement) {
QDomNodeList children = gElement.elementsByTagName("id");
bool ninputs_ok;
// To validate the logic gate is in the catalog, only the number of inputs is required
// (the bits/input is irrelevant at this moment)
int ninputs = getNInputs(id, ninputs_ok);
// vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
// Rework this part to accept: and, and_wide, and2, and2_wide, ...,
// AND2, ANDn, AND2_WIDE, ANDn_WIDE, (lowercase, uppercase, camelcase)
// Being n the number of inputs (D_0, D_1, ..., D_n-1)
// Y is the output
// @remark: Be very "picky" here, reject *anything that doesn't match perfectly
if (!id.toUpper().startsWith(gate)) {
return false;
}
if (!ninputs_ok) {
return false;
}
// ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
if (!find("y", children)) {
return false;
}
for (auto i = 0; i < ninputs; i++) {
// For the SyscLogicGate class and its derivatives,
// it should be "d" below (not "d_")
if (!find("d_" + QString::number(i), children)) {
return false;
}
}
return true;
}
};
template <unsigned int N = 2,
unsigned int W = 1>
class SyscAnd_pv : public SyscLogicGate_pv<N,W> {
public:
static_assert(N >= 2, "SyscAnd_pv DESIGN ERROR: N must be >= 2");
static_assert(W >= 1, "SyscAnd_pv DESIGN ERROR: W must be >= 1");
typedef SyscLogicGate_pv<N,W> BASE_MODULE;
typedef SyscAnd_pv<N,W> SC_CURRENT_USER_MODULE;
SyscAnd_pv<N,W>(::sc_core::sc_module_name name) : SyscLogicGate_pv<N,W>(name) {
}
virtual void combinational () {
auto i = N-1;
auto result = BASE_MODULE::d[0].read();
for (; i > 0; i--) {
auto operand = BASE_MODULE::d[i].read();
result &= operand;
}
BASE_MODULE::y.write(result);
}
static bool validate(QString id, QDomElement gElement) {
return SyscLogicGate_pv<>::validate("AND", id, gElement);
}
};
template <unsigned int N = 2,
unsigned int W = 1>
class SyscNand_pv : public SyscLogicGate_pv<N,W> {
public:
static_assert(N >= 2, "SyscNand_pv DESIGN ERROR: N must be >= 2");
static_assert(W >= 1, "SyscNand_pv DESIGN ERROR: W must be >= 1");
typedef SyscLogicGate_pv<N,W> BASE_MODULE;
typedef SyscNand_pv<N,W> SC_CURRENT_USER_MODULE;
SyscNand_pv<N,W>(::sc_core::sc_module_name name) : SyscLogicGate_pv<N,W>(name) {
}
virtual void combinational () {
auto i = N-1;
auto result = BASE_MODULE::d[0].read();
for (; i > 0; i--) {
auto operand = BASE_MODULE::d[i].read();
result &= operand;
}
BASE_MODULE::y.write(~result);
}
static bool validate(QString id, QDomElement gElement) {
return SyscLogicGate_pv<>::validate("NAND", id, gElement);
}
};
template <unsigned int N = 2,
unsigned int W = 1>
class SyscOr_pv : public SyscLogicGate_pv<N,W> {
public:
static_assert(N >= 2, "SyscOr_pv DESIGN ERROR: N must be >= 2");
static_assert(W >= 1, "SyscOr_pv DESIGN ERROR: W must be >= 1");
typedef SyscLogicGate_pv<N,W> BASE_MODULE;
typedef SyscOr_pv<N,W> SC_CURRENT_USER_MODULE;
SyscOr_pv<N,W>(::sc_core::sc_module_name name) : SyscLogicGate_pv<N,W>(name) {
}
virtual void combinational () {
auto i = N-1;
auto result = BASE_MODULE::d[0].read();
for (; i > 0; i--) {
auto operand = BASE_MODULE::d[i].read();
result |= operand;
}
BASE_MODULE::y.write(result);
}
static bool validate(QString id, QDomElement gElement) {
return SyscLogicGate_pv<>::validate("OR", id, gElement);
}
};
template <unsigned int N = 2,
unsigned int W = 1>
class SyscNor_pv : public SyscLogicGate_pv<N,W> {
public:
static_assert(N >= 2, "SyscNor_pv DESIGN ERROR: N must be >= 2");
static_assert(W >= 1, "SyscNor_pv DESIGN ERROR: W must be >= 1");
typedef SyscLogicGate_pv<N,W> BASE_MODULE;
typedef SyscNor_pv<N,W> SC_CURRENT_USER_MODULE;
SyscNor_pv<N,W>(::sc_core::sc_module_name name) : SyscLogicGate_pv<N,W>(name) {
}
virtual void combinational () {
auto i = N-1;
auto result = BASE_MODULE::d[0].read();
for (; i > 0; i--) {
auto operand = BASE_MODULE::d[i].read();
result |= operand;
}
BASE_MODULE::y.write(~result);
}
static bool validate(QString id, QDomElement gElement) {
return SyscLogicGate_pv<>::validate("NOR", id, gElement);
}
};
template <unsigned int N = 2,
unsigned int W = 1>
class SyscXor_pv : public SyscLogicGate_pv<N,W> {
public:
static_assert(N >= 2, "SyscXor_pv DESIGN ERROR: N must be >= 2");
static_assert(W >= 1, "SyscXor_pv DESIGN ERROR: W must be >= 1");
typedef SyscLogicGate_pv<N,W> BASE_MODULE;
typedef SyscXor_pv<N,W> SC_CURRENT_USER_MODULE;
SyscXor_pv<N,W>(::sc_core::sc_module_name name) : SyscLogicGate_pv<N,W>(name) {
}
virtual void combinational () {
auto i = N-1;
auto result = BASE_MODULE::d[0].read();
for (; i > 0; i--) {
auto operand = BASE_MODULE::d[i].read();
result ^= operand;
}
BASE_MODULE::y.write(result);
}
static bool validate(QString id, QDomElement gElement) {
return SyscLogicGate_pv<>::validate("XOR", id, gElement);
}
};
template <unsigned int N = 2,
unsigned int W = 1>
class SyscXnor_pv : public SyscLogicGate_pv<N,W> {
public:
static_assert(N >= 2, "SyscXnor_pv DESIGN ERROR: N must be >= 2");
static_assert(W >= 1, "SyscXnor_pv DESIGN ERROR: W must be >= 1");
typedef SyscLogicGate_pv<N,W> BASE_MODULE;
typedef SyscXnor_pv<N,W> SC_CURRENT_USER_MODULE;
SyscXnor_pv<N,W>(::sc_core::sc_module_name name) : SyscLogicGate_pv<N,W>(name) {
}
virtual void combinational () {
auto i = N-1;
auto result = BASE_MODULE::d[0].read();
for (; i > 0; i--) {
auto operand = BASE_MODULE::d[i].read();
result ^= operand;
}
BASE_MODULE::y.write(~result);
}
static bool validate(QString id, QDomElement gElement) {
return SyscLogicGate_pv<>::validate("XNOR", id, gElement);
}
};
#endif // SC_GATES_PV_H
|
#include <systemc.h>
/**
* @brief jpg_output module. Federico Cruz
* It takes the image and compresses it into jpeg format
* It is done in 4 parts:
* 1. Divides the image in 8x8 pixel blocks; for 8-bit grayscale images the a level shift is done by substracting 128 from each pixel.
* 2. Discrete Cosine Transform (DCT) of the 8x8 image.
* 3. Each transformed 8x8 block is divided by a quantization value for each block entry.
* 4. Each quantized 8x8 block is reordered by a Zig-Zag sequence into a array of size 64.
* *5. Entropy compression by variable length encoding (huffman). Used to maximize compression. Not implemented here.
*/
#define PI 3.1415926535897932384626433832795
#define BLOCK_ROWS 8
#define BLOCK_COLS 8
SC_MODULE(jpg_output)
{
//-----------Internal variables-------------------
// const int Block_rows = 8;
// const int Block_cols = 8;
double *image;
int image_rows = 480;
int image_cols = 640;
signed char eob = 127; // end of block
int quantificator[8][8] = {// quantization table
{16, 11, 10, 16, 24, 40, 51, 61},
{12, 12, 14, 19, 26, 58, 60, 55},
{14, 13, 16, 24, 40, 57, 69, 56},
{14, 17, 22, 29, 51, 87, 80, 62},
{18, 22, 37, 56, 68, 109, 103, 77},
{24, 35, 55, 64, 81, 104, 113, 92},
{49, 64, 78, 87, 103, 121, 120, 101},
{72, 92, 95, 98, 112, 100, 103, 99}};
int zigzag_index[64] = {// zigzag table
0, 1, 5, 6, 14, 15, 27, 28,
2, 4, 7, 13, 16, 26, 29, 42,
3, 8, 12, 17, 25, 30, 41, 43,
9, 11, 18, 24, 31, 40, 44, 53,
10, 19, 23, 32, 39, 45, 52, 54,
20, 22, 33, 38, 46, 51, 55, 60,
21, 34, 37, 47, 50, 56, 59, 61,
35, 36, 48, 49, 57, 58, 62, 63};
// Constructor for compressor
SC_HAS_PROCESS(jpg_output);
jpg_output(sc_module_name jpg_compressor, int im_rows = 480, int im_cols = 640) : sc_module(jpg_compressor)
{
if (im_rows % BLOCK_ROWS == 0)
{
image_rows = im_rows;
}
else
{
image_rows = (im_rows / BLOCK_ROWS + 1) * BLOCK_ROWS;
}
if (im_cols % BLOCK_COLS == 0)
{
image_cols = im_cols;
}
else
{
image_cols = (im_cols / BLOCK_COLS + 1) * BLOCK_COLS;
}
image = new double[image_rows * image_cols];
// initialize the image matrix to avoid nan
for (int i = 0; i < (image_rows * image_cols); i++)
{
image[i] = 0;
}
} // End of Constructor
//------------Code Starts Here-------------------------
void input_pixel(int pixel_value, int row, int col)
{
double *i_row = &image[row * image_cols];
i_row[col] = double(pixel_value);
}
void output_pixel(int *Pixel, int row, int col)
{
double *i_row = &image[row * image_cols];
*Pixel = int(i_row[col]);
}
void output_byte(signed char *element, int index)
{
element[index] = image[index];
}
void jpeg_compression(int *output_size)
{
// Level shift
for (int i = 0; i < (image_rows * image_cols); i++)
{
image[i] = image[i] - 128;
}
int number_of_blocks = image_rows * image_cols / (BLOCK_ROWS * BLOCK_COLS);
#ifndef USING_TLM_TB_EN
int block_output[number_of_blocks][BLOCK_ROWS * BLOCK_COLS] = {0};
int block_output_size[number_of_blocks] = {0};
#else
int **block_output = new int *[number_of_blocks];
int *block_output_size = new int[number_of_blocks];
for (int i = 0; i < number_of_blocks; i++)
{
block_output[i] = new int[BLOCK_ROWS * BLOCK_COLS];
}
for (int i = 0; i < number_of_blocks; i++)
{
block_output_size[i] = 0;
for (int j = 0; j < BLOCK_ROWS * BLOCK_COLS; j++)
{
block_output[i][j] = 0;
}
}
#endif // USING_TLM_TB_EN
int block_counter = 0;
*output_size = 0;
for (int row = 0; row < image_rows; row += BLOCK_ROWS)
{
for (int col = 0; col < image_cols; col += BLOCK_COLS)
{
// Divided the image in 8×8 blocks
dct(row, col);
quantization(row, col);
zigzag(row, col, &block_output_size[block_counter], block_output[block_counter]);
*output_size += block_output_size[block_counter] + 1;
block_counter++;
}
}
int output_counter = 0;
for (int block_index = 0; block_index < number_of_blocks; block_index++)
{
for (int out_index = 0; out_index < block_output_size[block_index]; out_index++)
{
image[output_counter] = block_output[block_index][out_index];
output_counter++;
}
image[output_counter] = eob;
output_counter++;
}
#ifdef USING_TLM_TB_EN
for (int i = 0; i < number_of_blocks; i++)
{
delete[] block_output[i];
}
delete[] block_output;
delete[] block_output_size;
#endif // USING_TLM_TB_EN
}
void dct(int row_offset, int col_offset)
{
double cos_table[BLOCK_ROWS][BLOCK_COLS];
// make the cosine table
for (int row = 0; row < BLOCK_ROWS; row++)
{
for (int col = 0; col < BLOCK_COLS; col++)
{
cos_table[row][col] = cos((((2 * row) + 1) * col * PI) / 16);
}
}
double temp = 0.0;
for (int row = row_offset; row < row_offset + BLOCK_ROWS; row++)
{
double *i_row = &image[row * image_cols];
for (int col = col_offset; col < col_offset + BLOCK_COLS; col++)
{
// i_row[col] = cos_table[row-row_offset][col-col_offset];
temp = 0.0;
for (int x = 0; x < 8; x++)
{
double *x_row = &image[(x + row_offset) * image_cols];
for (int y = 0; y < 8; y++)
{
temp += x_row[y + col_offset] * cos_table[x][row - row_offset] * cos_table[y][col - col_offset];
}
}
if ((row - row_offset == 0) && (col - col_offset == 0))
{
temp /= 8.0;
}
else if (((row - row_offset == 0) && (col - col_offset != 0)) || ((row - row_offset != 0) && (col - col_offset == 0)))
{
temp /= (4.0 * sqrt(2.0));
}
else
{
temp /= 4.0;
}
i_row[col] = temp;
}
}
}
void quantization(int row_offset, int col_offset)
{
for (int row = row_offset; row < row_offset + BLOCK_ROWS; row++)
{
double *i_row = &image[row * image_cols];
for (int col = col_offset; col < col_offset + BLOCK_COLS; col++)
{
i_row[col] = round(i_row[col] / quantificator[row - row_offset][col - col_offset]);
}
}
}
void zigzag(int row_offset, int col_offset, int *block_output_size, int *block_output)
{
int index_last_non_zero_value = 0;
// index to last non-zero in a block zigzag array
for (int row = row_offset; row < row_offset + BLOCK_ROWS; row++)
{
double *i_row = &image[row * image_cols];
for (int col = col_offset; col < col_offset + BLOCK_COLS; col++)
{
int temp_index = zigzag_index[(row - row_offset) * 8 + (col - col_offset)];
block_output[temp_index] = i_row[col];
if (i_row[col] != 0 && temp_index > index_last_non_zero_value)
{
index_last_non_zero_value = temp_index + 1;
}
}
}
*block_output_size = index_last_non_zero_value;
}
};
|
#ifndef TESTBENCH_H
#define TESTBENCH_H
#include <systemc.h>
#include <iostream>
using namespace std;
template <class DataType>
class Testbench : public sc_module
{
private:
void test()
{
print();
en_out = 1;
data_out = 1234;
wait();
print();
data_out.write(data_in.read());
wait();
print();
data_out.write(data_in.read());
wait();
print();
data_out.write(data_in.read());
wait();
print();
data_out.write(data_in.read());
wait();
print();
data_out.write(data_in.read());
wait();
print();
data_out.write(data_in.read());
wait();
print();
data_out.write(data_in.read());
wait();
print();
data_out.write(data_in.read());
wait();
print();
data_out.write(data_in.read());
sc_stop();
}
void print()
{
cout << clk_in.read() << " | "
<< en_out.read() << " |\n";
}
public:
sc_in<bool> clk_in;
sc_out<bool> en_out;
sc_out<DataType> data_out;
sc_in<DataType> data_in;
SC_CTOR(Testbench)
{
cout << "Pipe_1 | Pipe_2 | Pipe_3 | Tiempo | Enable |\n";
cout << "------------------------------------------------------------|\n";
SC_THREAD(test);
sensitive << clk_in;
}
};
#endif//TESTBENCH_H |
// ================================================================
// NVDLA Open Source Project
//
// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
// NVDLA Open Hardware License; Check "LICENSE" which comes with
// this distribution for more information.
// ================================================================
// File Name: NvdlaTopDummy.h
#ifndef _NVDLATOPDUMMY_H_
#define _NVDLATOPDUMMY_H_
#define SC_INCLUDE_DYNAMIC_PROCESSES
#include <systemc.h>
#include <tlm.h>
#include "tlm_utils/multi_passthrough_initiator_socket.h"
#include "tlm_utils/multi_passthrough_target_socket.h"
#include "scsim_common.h"
SCSIM_NAMESPACE_START(cmod)
class NvdlaTopDummy : public sc_module {
public:
SC_HAS_PROCESS(NvdlaTopDummy);
NvdlaTopDummy( sc_module_name module_name );
// Target sockets
tlm_utils::multi_passthrough_target_socket<NvdlaTopDummy> m_target;
private:
void dummy_b_transport(int ID, tlm::tlm_generic_payload& bp, sc_time& delay);
};
SCSIM_NAMESPACE_END()
#endif
|
// ================================================================
// NVDLA Open Source Project
//
// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
// NVDLA Open Hardware License; Check "LICENSE" which comes with
// this distribution for more information.
// ================================================================
// File Name: NvdlaTopDummy.h
#ifndef _NVDLATOPDUMMY_H_
#define _NVDLATOPDUMMY_H_
#define SC_INCLUDE_DYNAMIC_PROCESSES
#include <systemc.h>
#include <tlm.h>
#include "tlm_utils/multi_passthrough_initiator_socket.h"
#include "tlm_utils/multi_passthrough_target_socket.h"
#include "scsim_common.h"
SCSIM_NAMESPACE_START(cmod)
class NvdlaTopDummy : public sc_module {
public:
SC_HAS_PROCESS(NvdlaTopDummy);
NvdlaTopDummy( sc_module_name module_name );
// Target sockets
tlm_utils::multi_passthrough_target_socket<NvdlaTopDummy> m_target;
private:
void dummy_b_transport(int ID, tlm::tlm_generic_payload& bp, sc_time& delay);
};
SCSIM_NAMESPACE_END()
#endif
|
/************************************************/
// Copyright tlm_noc contributors.
// Author Mike
// SPDX-License-Identifier: Apache-2.0
/************************************************/
#include <systemc.h>
#include <tlm.h>
#include <tlm_utils/peq_with_cb_and_phase.h>
#include <tlm_utils/simple_initiator_socket.h>
#include <tlm_utils/simple_target_socket.h>
#include "pe_base.h"
#include "host_base.h"
#include "host.h"
#include "router.h"
#include "l2cache.h"
#include "dumpWave.h"
using namespace std;
using namespace tlm;
#include <systemc.h>
#include <tlm.h>
int sc_main (int, char **)
{
ofstream outfile("./build/wavedump.txt");
if (!outfile.is_open()) {
std::cerr << "Error opening file!" << std::endl;
return 1;
}
char blkName[100];
sc_set_time_resolution(1, SC_NS);
int i = 0;
int j = 0;
int m = 0;
int h = 0;
// ----------------------------------- //
// create object
// ----------------------------------- //
pe_base* pe[N_PE];
for (int i = 0; i < N_PE; i++) {
sprintf(blkName, "PE%d", i);
pe[i] = new pe_base(blkName);
}
i = 0;
Router* R[N_PE];
for (int r = 0; r < N_PE_ROW; r++) {
for (int c = 0; c < N_PE_COL; c++) {
sprintf(blkName, "router(%d,%d)", r, c);
R[i] = new Router(blkName, r, c);
i++;
}
}
host_base* HP[N_HOST_BASE +1];
for (int i = 0; i < N_HOST_BASE +1; i++) {
if (i < 1) {
sprintf(blkName, "Host_%d", i);
HP[i] = new host(blkName, i);
} else {
sprintf(blkName, "HostDummy_%d", i);
HP[i] = new host_base(blkName);
}
}
l2cache* mem[N_SM];
for (int i = 0; i < N_SM; i++) {
sprintf(blkName, "MEM%d", i);
mem[i] = new l2cache(blkName);
}
// ----------------------------------- //
// bind PEs
// ----------------------------------- //
for (int i = 0; i < N_PE; i++) {
pe[i]->m_port.bind(R[i]->s_port[Local]);
R[i]->m_port[Local].bind(pe[i]->s_port);
}
// ----------------------------------- //
// East2West
// ----------------------------------- //
cout << "Route: Eest2West" << endl;
for (int r = 0; r < N_PE_ROW; r++) {
for (int c = 0; c < N_PE_COL-1; c++) {
i = r*N_PE_ROW+c;
j = i + 1;
R[i]->m_port[West].bind(R[j]->s_port[West]);
cout << "R" << i << "<---->" << "R" << j << " ";
}
cout << endl;
}
cout << "bind Host:" << endl;
for (int r = 0; r < N_PE_ROW; r++) {
i = r*N_PE_COL;
HP[h++]->m_port.bind(R[i]->s_port[West]);
cout << "Host" << h-1 << "<---->" << "R" << i << " ";
cout << endl;
}
cout << "bind Mem" << endl;
for (int r = 0; r < N_PE_ROW; r++) {
i = (r+1)*N_PE_COL -1;
R[i]->m_port[West].bind(mem[m++]->s_port);
cout << "MEM" << m-1 << "<---->" << "R" << i << " ";
cout << endl;
}
// ----------------------------------- //
// West2East
// ----------------------------------- //
cout << "Route: West2East" << endl;
for (int r = 0; r < N_PE_ROW; r++) {
for (int c = N_PE_COL-1; c > 0; c--) {
i = r*N_PE_ROW+c;
j = i - 1;
R[i]->m_port[East].bind(R[j]->s_port[East]);
cout << "R" << i << "<---->" << "R" << j << " ";
}
cout << endl;
}
cout << "bind Host:" << endl;
for (int r = 0; r < N_PE_ROW; r++) {
i = (r+1)*N_PE_COL-1;
HP[h++]->m_port.bind(R[i]->s_port[East]);
cout << "Host" << h-1 << "<---->" << "R" << i << " ";
cout << endl;
}
cout << "bind Mem" << endl;
for (int r = 0; r < N_PE_ROW; r++) {
i = r*N_PE_COL;
R[i]->m_port[East].bind(mem[m++]->s_port);
cout << "MEM" << m-1 << "<---->" << "R" << i << " ";
cout << endl;
}
// ----------------------------------- //
// South2North
// ----------------------------------- //
cout << "Route: South2North" << endl;
for (int c = 0; c < N_PE_COL; c++) {
for (int r = 0; r < N_PE_ROW-1; r++) {
i = r*N_PE_COL+c;
j = i + N_PE_COL;
R[i]->m_port[North].bind(R[j]->s_port[North]);
cout << "R" << i << "<---->" << "R" << j << " ";
}
cout << endl;
}
cout << "bind Host:" << endl;
for (int c = 0; c < N_PE_COL; c++) {
i = c;
HP[h++]->m_port.bind(R[i]->s_port[North]);
cout << "Host" << h-1 << "<---->" << "R" << i << " ";
cout << endl;
}
cout << "bind Mem" << endl;
for (int c = 0; c < N_PE_COL; c++) {
i = (N_PE_ROW -1) * N_PE_COL + c;
R[i]->m_port[North].bind(mem[m++]->s_port);
cout << "MEM" << m-1 << "<---->" << "R" << i << " ";
cout << endl;
}
// ----------------------------------- //
// North2South
// ----------------------------------- //
cout << "Route: North2South" << endl;
for (int c = 0; c < N_PE_COL; c++) {
for (int r = N_PE_ROW-1; r > 0; r--) {
i = r*N_PE_COL+c;
j = i - N_PE_COL;
R[i]->m_port[South].bind(R[j]->s_port[South]);
cout << "R" << i << "<---->" << "R" << j << " ";
}
cout << endl;
}
cout << "bind Host:" << endl;
for (int c = 0; c < N_PE_COL; c++) {
i = (N_PE_ROW-1) * N_PE_COL+ c;
HP[h++]->m_port.bind(R[i]->s_port[South]);
cout << "Host" << h-1 << "<---->" << "R" << i << " ";
cout << endl;
}
cout << "bind Mem" << endl;
for (int c = 0; c < N_PE_COL; c++) {
i = c;
R[i]->m_port[South].bind(mem[m++]->s_port);
cout << "MEM" << m-1 << "<---->" << "R" << i << " ";
cout << endl;
}
sc_start(100, SC_MS);
cout << "----dump Wavefrom file----" << endl;
for (int i=0; i<9; i++)
outfile << R[i]->sbuff << endl;
return 0;
}
|
#ifndef TESTBENCH_VBASE_H
#define TESTBENCH_VBASE_H
#include <systemc.h>
#include "verilated.h"
#include "verilated_vcd_sc.h"
#define verilator_trace_enable(vcd_filename, dut) \
if (waves_enabled()) \
{ \
Verilated::traceEverOn(true); \
VerilatedVcdC *v_vcd = new VerilatedVcdC; \
sc_core::sc_time delay_us; \
if (waves_delayed(delay_us)) \
dut->trace_enable (v_vcd, delay_us); \
else \
dut->trace_enable (v_vcd); \
v_vcd->open (vcd_filename); \
this->m_verilate_vcd = v_vcd; \
}
//-----------------------------------------------------------------
// Module
//-----------------------------------------------------------------
class testbench_vbase: public sc_module
{
public:
sc_in <bool> clk;
sc_in <bool> rst;
virtual void set_testcase(int tc) { }
virtual void set_delays(bool en) { }
virtual void set_iterations(int iterations) { }
virtual void set_argcv(int argc, char* argv[]) { }
virtual void process(void) { while (1) wait(); }
virtual void monitor(void) { while (1) wait(); }
SC_HAS_PROCESS(testbench_vbase);
testbench_vbase(sc_module_name name): sc_module(name)
{
SC_CTHREAD(process, clk);
SC_CTHREAD(monitor, clk);
}
virtual void add_trace(sc_trace_file * fp, std::string prefix) { }
virtual void abort(void)
{
cout << "TB: Aborted at " << sc_time_stamp() << endl;
if (m_verilate_vcd)
{
m_verilate_vcd->flush();
m_verilate_vcd->close();
m_verilate_vcd = NULL;
}
}
bool waves_enabled(void)
{
char *s = getenv("ENABLE_WAVES");
if (s && !strcmp(s, "no"))
return false;
else
return true;
}
bool waves_delayed(sc_core::sc_time &delay)
{
char *s = getenv("WAVES_DELAY_US");
if (s != NULL)
{
uint32_t us = strtoul(s, NULL, 0);
printf("WAVES: Delay start until %duS\n", us);
delay = sc_core::sc_time(us, SC_US);
return true;
}
else
return false;
}
std::string getenv_str(std::string name, std::string defval)
{
char *s = getenv(name.c_str());
if (!s || (s && !strcmp(s, "")))
return defval;
else
return std::string(s);
}
protected:
VerilatedVcdC *m_verilate_vcd;
};
#endif |
// ================================================================
// NVDLA Open Source Project
//
// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
// NVDLA Open Hardware License; Check "LICENSE" which comes with
// this distribution for more information.
// ================================================================
// File Name: NV_NVDLA_csc_base.h
#ifndef _NV_NVDLA_CSC_BASE_H_
#define _NV_NVDLA_CSC_BASE_H_
#define SC_INCLUDE_DYNAMIC_PROCESSES
#include "NV_MSDEC_csb2xx_16m_secure_be_lvl_iface.h"
#include "nvdla_xx2csb_resp_iface.h"
#include "nvdla_cc_credit_iface.h"
#include "nvdla_dat_info_update_iface.h"
#include "nvdla_ram_rd_valid_port_RADDR_8_RDATA_1024_iface.h"
#include "nvdla_ram_rd_valid_port_RADDR_12_RDATA_1024_iface.h"
#include "nvdla_sc2mac_data_if_iface.h"
#include "nvdla_sc2mac_weight_if_iface.h"
#include "nvdla_wt_info_update_iface.h"
#include "scsim_common.h"
#include <systemc.h>
#include <tlm.h>
#include <tlm_utils/multi_passthrough_initiator_socket.h>
#include <tlm_utils/multi_passthrough_target_socket.h>
SCSIM_NAMESPACE_START(cmod)
// Base SystemC class for module NV_NVDLA_csc
class NV_NVDLA_csc_base : public sc_module
{
public:
// Constructor
NV_NVDLA_csc_base(const sc_module_name name);
// Target Socket (unrecognized protocol: NV_MSDEC_csb2xx_16m_secure_be_lvl_t): csb2csc_req
tlm_utils::multi_passthrough_target_socket<NV_NVDLA_csc_base, 32, tlm::tlm_base_protocol_types> csb2csc_req;
virtual void csb2csc_req_b_transport(int ID, tlm::tlm_generic_payload& bp, sc_time& delay);
virtual void csb2csc_req_b_transport(int ID, NV_MSDEC_csb2xx_16m_secure_be_lvl_t* payload, sc_time& delay) = 0;
// Target Socket (unrecognized protocol: nvdla_cc_credit_t): accu2sc_credit
tlm_utils::multi_passthrough_target_socket<NV_NVDLA_csc_base, 32, tlm::tlm_base_protocol_types> accu2sc_credit;
virtual void accu2sc_credit_b_transport(int ID, tlm::tlm_generic_payload& bp, sc_time& delay);
virtual void accu2sc_credit_b_transport(int ID, nvdla_cc_credit_t* payload, sc_time& delay) = 0;
// Target Socket (unrecognized protocol: nvdla_dat_info_update_t): dat_up_cdma2sc
tlm_utils::multi_passthrough_target_socket<NV_NVDLA_csc_base, 32, tlm::tlm_base_protocol_types> dat_up_cdma2sc;
virtual void dat_up_cdma2sc_b_transport(int ID, tlm::tlm_generic_payload& bp, sc_time& delay);
virtual void dat_up_cdma2sc_b_transport(int ID, nvdla_dat_info_update_t* payload, sc_time& delay) = 0;
// Target Socket (unrecognized protocol: nvdla_wt_info_update_t): wt_up_cdma2sc
tlm_utils::multi_passthrough_target_socket<NV_NVDLA_csc_base, 32, tlm::tlm_base_protocol_types> wt_up_cdma2sc;
virtual void wt_up_cdma2sc_b_transport(int ID, tlm::tlm_generic_payload& bp, sc_time& delay);
virtual void wt_up_cdma2sc_b_transport(int ID, nvdla_wt_info_update_t* payload, sc_time& delay) = 0;
// Initiator Socket (unrecognized protocol: nvdla_xx2csb_resp_t): csc2csb_resp
tlm::tlm_generic_payload csc2csb_resp_bp;
nvdla_xx2csb_resp_t csc2csb_resp_payload;
tlm_utils::multi_passthrough_initiator_socket<NV_NVDLA_csc_base, 32, tlm::tlm_base_protocol_types> csc2csb_resp;
virtual void csc2csb_resp_b_transport(nvdla_xx2csb_resp_t* payload, sc_time& delay);
// Initiator Socket (unrecognized protocol: nvdla_dat_info_update_t): dat_up_sc2cdma
tlm::tlm_generic_payload dat_up_sc2cdma_bp;
nvdla_dat_info_update_t dat_up_sc2cdma_payload;
tlm_utils::multi_passthrough_initiator_socket<NV_NVDLA_csc_base, 32, tlm::tlm_base_protocol_types> dat_up_sc2cdma;
virtual void dat_up_sc2cdma_b_transport(nvdla_dat_info_update_t* payload, sc_time& delay);
// Initiator Socket (unrecognized protocol: nvdla_ram_rd_valid_port_RADDR_12_RDATA_1024_t): sc2buf_dat_rd
tlm::tlm_generic_payload sc2buf_dat_rd_bp;
nvdla_ram_rd_valid_port_RADDR_12_RDATA_1024_t sc2buf_dat_rd_payload;
tlm_utils::multi_passthrough_initiator_socket<NV_NVDLA_csc_base, 32, tlm::tlm_base_protocol_types> sc2buf_dat_rd;
virtual void sc2buf_dat_rd_b_transport(nvdla_ram_rd_valid_port_RADDR_12_RDATA_1024_t* payload, sc_time& delay);
// Initiator Socket (unrecognized protocol: nvdla_ram_rd_valid_port_RADDR_12_RDATA_1024_t): sc2buf_wt_rd
tlm::tlm_generic_payload sc2buf_wt_rd_bp;
nvdla_ram_rd_valid_port_RADDR_12_RDATA_1024_t sc2buf_wt_rd_payload;
tlm_utils::multi_passthrough_initiator_socket<NV_NVDLA_csc_base, 32, tlm::tlm_base_protocol_types> sc2buf_wt_rd;
virtual void sc2buf_wt_rd_b_transport(nvdla_ram_rd_valid_port_RADDR_12_RDATA_1024_t* payload, sc_time& delay);
// Initiator Socket (unrecognized protocol: nvdla_ram_rd_valid_port_RADDR_8_RDATA_1024_t): sc2buf_wmb_rd
tlm::tlm_generic_payload sc2buf_wmb_rd_bp;
nvdla_ram_rd_valid_port_RADDR_12_RDATA_1024_t sc2buf_wmb_rd_payload;
tlm_utils::multi_passthrough_initiator_socket<NV_NVDLA_csc_base, 32, tlm::tlm_base_protocol_types> sc2buf_wmb_rd;
virtual void sc2buf_wmb_rd_b_transport(nvdla_ram_rd_valid_port_RADDR_8_RDATA_1024_t* payload, sc_time& delay);
// Initiator Socket (unrecognized protocol: nvdla_sc2mac_data_if_t): sc2mac_dat
tlm::tlm_generic_payload sc2mac_a_dat_bp;
nvdla_sc2mac_data_if_t sc2mac_a_dat_payload;
tlm_utils::multi_passthrough_initiator_socket<NV_NVDLA_csc_base, 32, tlm::tlm_base_protocol_types> sc2mac_dat_a;
virtual void sc2mac_a_dat_b_transport(nvdla_sc2mac_data_if_t* payload, sc_time& delay);
tlm::tlm_generic_payload sc2mac_b_dat_bp;
nvdla_sc2mac_data_if_t sc2mac_b_dat_payload;
tlm_utils::multi_passthrough_initiator_socket<NV_NVDLA_csc_base, 32, tlm::tlm_base_protocol_types> sc2mac_dat_b;
virtual void sc2mac_b_dat_b_transport(nvdla_sc2mac_data_if_t* payload, sc_time& delay);
// Initiator Socket (unrecognized protocol: nvdla_sc2mac_weight_if_t): sc2mac_wt
tlm::tlm_generic_payload sc2mac_a_wt_bp;
nvdla_sc2mac_weight_if_t sc2mac_a_wt_payload;
tlm_utils::multi_passthrough_initiator_socket<NV_NVDLA_csc_base, 32, tlm::tlm_base_protocol_types> sc2mac_wt_a;
virtual void sc2mac_a_wt_b_transport(nvdla_sc2mac_weight_if_t* payload, sc_time& delay);
tlm::tlm_generic_payload sc2mac_b_wt_bp;
nvdla_sc2mac_weight_if_t sc2mac_b_wt_payload;
tlm_utils::multi_passthrough_initiator_socket<NV_NVDLA_csc_base, 32, tlm::tlm_base_protocol_types> sc2mac_wt_b;
virtual void sc2mac_b_wt_b_transport(nvdla_sc2mac_weight_if_t* payload, sc_time& delay);
// Initiator Socket (unrecognized protocol: nvdla_wt_info_update_t): wt_up_sc2cdma
tlm::tlm_generic_payload wt_up_sc2cdma_bp;
nvdla_wt_info_update_t wt_up_sc2cdma_payload;
tlm_utils::multi_passthrough_initiator_socket<NV_NVDLA_csc_base, 32, tlm::tlm_base_protocol_types> wt_up_sc2cdma;
virtual void wt_up_sc2cdma_b_transport(nvdla_wt_info_update_t* payload, sc_time& delay);
// Destructor
virtual ~NV_NVDLA_csc_base() {}
};
// Constructor for base SystemC class for module NV_NVDLA_csc
inline NV_NVDLA_csc_base::NV_NVDLA_csc_base(const sc_module_name name)
: sc_module(name),
csb2csc_req("csb2csc_req"),
accu2sc_credit("accu2sc_credit"),
dat_up_cdma2sc("dat_up_cdma2sc"),
wt_up_cdma2sc("wt_up_cdma2sc"),
csc2csb_resp_bp(),
csc2csb_resp("csc2csb_resp"),
dat_up_sc2cdma_bp(),
dat_up_sc2cdma("dat_up_sc2cdma"),
sc2buf_dat_rd_bp(),
sc2buf_dat_rd("sc2buf_dat_rd"),
sc2buf_wt_rd_bp(),
sc2buf_wt_rd("sc2buf_wt_rd"),
sc2buf_wmb_rd_bp(),
sc2buf_wmb_rd("sc2buf_wmb_rd"),
sc2mac_a_dat_bp(),
sc2mac_dat_a("sc2mac_dat_a"),
sc2mac_b_dat_bp(),
sc2mac_dat_b("sc2mac_dat_b"),
sc2mac_a_wt_bp(),
sc2mac_wt_a("sc2mac_wt_a"),
sc2mac_b_wt_bp(),
sc2mac_wt_b("sc2mac_wt_b"),
wt_up_sc2cdma_bp(),
wt_up_sc2cdma("wt_up_sc2cdma")
{
// Target Socket (unrecognized protocol: NV_MSDEC_csb2xx_16m_secure_be_lvl_t): csb2csc_req
this->csb2csc_req.register_b_transport(this, &NV_NVDLA_csc_base::csb2csc_req_b_transport);
// Target Socket (unrecognized protocol: nvdla_cc_credit_t): accu2sc_credit
this->accu2sc_credit.register_b_transport(this, &NV_NVDLA_csc_base::accu2sc_credit_b_transport);
// Target Socket (unrecognized protocol: nvdla_dat_info_update_t): dat_up_cdma2sc
this->dat_up_cdma2sc.register_b_transport(this, &NV_NVDLA_csc_base::dat_up_cdma2sc_b_transport);
// Target Socket (unrecognized protocol: nvdla_wt_info_update_t): wt_up_cdma2sc
this->wt_up_cdma2sc.register_b_transport(this, &NV_NVDLA_csc_base::wt_up_cdma2sc_b_transport);
}
inline void
NV_NVDLA_csc_base::csb2csc_req_b_transport(int ID, tlm::tlm_generic_payload& bp, sc_time& delay)
{
NV_MSDEC_csb2xx_16m_secure_be_lvl_t* payload = (NV_MSDEC_csb2xx_16m_secure_be_lvl_t*) bp.get_data_ptr();
csb2csc_req_b_transport(ID, payload, delay);
}
inline void
NV_NVDLA_csc_base::accu2sc_credit_b_transport(int ID, tlm::tlm_generic_payload& bp, sc_time& delay)
{
nvdla_cc_credit_t* payload = (nvdla_cc_credit_t*) bp.get_data_ptr();
accu2sc_credit_b_transport(ID, payload, delay);
}
inline void
NV_NVDLA_csc_base::dat_up_cdma2sc_b_transport(int ID, tlm::tlm_generic_payload& bp, sc_time& delay)
{
nvdla_dat_info_update_t* payload = (nvdla_dat_info_update_t*) bp.get_data_ptr();
dat_up_cdma2sc_b_transport(ID, payload, delay);
}
inline void
NV_NVDLA_csc_base::wt_up_cdma2sc_b_transport(int ID, tlm::tlm_generic_payload& bp, sc_time& delay)
{
nvdla_wt_info_update_t* payload = (nvdla_wt_info_update_t*) bp.get_data_ptr();
wt_up_cdma2sc_b_transport(ID, payload, delay);
}
inline void
NV_NVDLA_csc_base::csc2csb_resp_b_transport(nvdla_xx2csb_resp_t* payload, sc_time& delay)
{
csc2csb_resp_bp.set_data_ptr((unsigned char*) payload);
for (uint8_t socket_id=0; socket_id < csc2csb_resp.size(); socket_id++) {
csc2csb_resp[socket_id]->b_transport(csc2csb_resp_bp, delay);
}
}
inline void
NV_NVDLA_csc_base::dat_up_sc2cdma_b_transport(nvdla_dat_info_update_t* payload, sc_time& delay)
{
dat_up_sc2cdma_bp.set_data_ptr((unsigned char*) payload);
for (uint8_t socket_id=0; socket_id < dat_up_sc2cdma.size(); socket_id++) {
dat_up_sc2cdma[socket_id]->b_transport(dat_up_sc2cdma_bp, delay);
}
}
inline void
NV_NVDLA_csc_base::sc2buf_dat_rd_b_transport(nvdla_ram_rd_valid_port_RADDR_12_RDATA_1024_t* payload, sc_time& delay)
{
sc2buf_dat_rd_bp.set_data_ptr((unsigned char*) payload);
for (uint8_t socket_id=0; socket_id < sc2buf_dat_rd.size(); socket_id++) {
sc2buf_dat_rd[socket_id]->b_transport(sc2buf_dat_rd_bp, delay);
}
}
inline void
NV_NVDLA_csc_base::sc2buf_wt_rd_b_transport(nvdla_ram_rd_valid_port_RADDR_12_RDATA_1024_t* payload, sc_time& delay)
{
sc2buf_wt_rd_bp.set_data_ptr((unsigned char*) payload);
for (uint8_t socket_id=0; socket_id < sc2buf_wt_rd.size(); socket_id++) {
sc2buf_wt_rd[socket_id]->b_transport(sc2buf_wt_rd_bp, delay);
}
}
inline void
NV_NVDLA_csc_base::sc2buf_wmb_rd_b_transport(nvdla_ram_rd_valid_port_RADDR_8_RDATA_1024_t* payload, sc_time& delay)
{
sc2buf_wmb_rd_bp.set_data_ptr((unsigned char*) payload);
for (uint8_t socket_id=0; socket_id < sc2buf_wmb_rd.size(); socket_id++) {
sc2buf_wmb_rd[socket_id]->b_transport(sc2buf_wmb_rd_bp, delay);
}
}
inline void
NV_NVDLA_csc_base::sc2mac_a_dat_b_transport(nvdla_sc2mac_data_if_t* payload, sc_time& delay)
{
sc2mac_a_dat_bp.set_data_ptr((unsigned char*) payload);
for (uint8_t socket_id=0; socket_id < sc2mac_dat_a.size(); socket_id++) {
sc2mac_dat_a[socket_id]->b_transport(sc2mac_a_dat_bp, delay);
}
}
inline void
NV_NVDLA_csc_base::sc2mac_b_dat_b_transport(nvdla_sc2mac_data_if_t* payload, sc_time& delay)
{
sc2mac_b_dat_bp.set_data_ptr((unsigned char*) payload);
for (uint8_t socket_id=0; socket_id < sc2mac_dat_b.size(); socket_id++) {
sc2mac_dat_b[socket_id]->b_transport(sc2mac_b_dat_bp, delay);
}
}
inline void
NV_NVDLA_csc_base::sc2mac_a_wt_b_transport(nvdla_sc2mac_weight_if_t* payload, sc_time& delay)
{
sc2mac_a_wt_bp.set_data_ptr((unsigned char*) payload);
for (uint8_t socket_id=0; socket_id < sc2mac_dat_a.size(); socket_id++) {
sc2mac_wt_a[socket_id]->b_transport(sc2mac_a_wt_bp, delay);
}
}
inline void
NV_NVDLA_csc_base::sc2mac_b_wt_b_transport(nvdla_sc2mac_weight_if_t* payload, sc_time& delay)
{
sc2mac_b_wt_bp.set_data_ptr((unsigned char*) payload);
for (uint8_t socket_id=0; socket_id < sc2mac_dat_b.size(); socket_id++) {
sc2mac_wt_b[socket_id]->b_transport(sc2mac_b_wt_bp, delay);
}
}
inline void
NV_NVDLA_csc_base::wt_up_sc2cdma_b_transport(nvdla_wt_info_update_t* payload, sc_time& delay)
{
wt_up_sc2cdma_bp.set_data_ptr((unsigned char*) payload);
for (uint8_t socket_id=0; socket_id < wt_up_sc2cdma.size(); socket_id++) {
wt_up_sc2cdma[socket_id]->b_transport(wt_up_sc2cdma_bp, delay);
}
}
SCSIM_NAMESPACE_END()
#endif
|
// ================================================================
// NVDLA Open Source Project
//
// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
// NVDLA Open Hardware License; Check "LICENSE" which comes with
// this distribution for more information.
// ================================================================
// File Name: NV_NVDLA_csc_base.h
#ifndef _NV_NVDLA_CSC_BASE_H_
#define _NV_NVDLA_CSC_BASE_H_
#define SC_INCLUDE_DYNAMIC_PROCESSES
#include "NV_MSDEC_csb2xx_16m_secure_be_lvl_iface.h"
#include "nvdla_xx2csb_resp_iface.h"
#include "nvdla_cc_credit_iface.h"
#include "nvdla_dat_info_update_iface.h"
#include "nvdla_ram_rd_valid_port_RADDR_8_RDATA_1024_iface.h"
#include "nvdla_ram_rd_valid_port_RADDR_12_RDATA_1024_iface.h"
#include "nvdla_sc2mac_data_if_iface.h"
#include "nvdla_sc2mac_weight_if_iface.h"
#include "nvdla_wt_info_update_iface.h"
#include "scsim_common.h"
#include <systemc.h>
#include <tlm.h>
#include <tlm_utils/multi_passthrough_initiator_socket.h>
#include <tlm_utils/multi_passthrough_target_socket.h>
SCSIM_NAMESPACE_START(cmod)
// Base SystemC class for module NV_NVDLA_csc
class NV_NVDLA_csc_base : public sc_module
{
public:
// Constructor
NV_NVDLA_csc_base(const sc_module_name name);
// Target Socket (unrecognized protocol: NV_MSDEC_csb2xx_16m_secure_be_lvl_t): csb2csc_req
tlm_utils::multi_passthrough_target_socket<NV_NVDLA_csc_base, 32, tlm::tlm_base_protocol_types> csb2csc_req;
virtual void csb2csc_req_b_transport(int ID, tlm::tlm_generic_payload& bp, sc_time& delay);
virtual void csb2csc_req_b_transport(int ID, NV_MSDEC_csb2xx_16m_secure_be_lvl_t* payload, sc_time& delay) = 0;
// Target Socket (unrecognized protocol: nvdla_cc_credit_t): accu2sc_credit
tlm_utils::multi_passthrough_target_socket<NV_NVDLA_csc_base, 32, tlm::tlm_base_protocol_types> accu2sc_credit;
virtual void accu2sc_credit_b_transport(int ID, tlm::tlm_generic_payload& bp, sc_time& delay);
virtual void accu2sc_credit_b_transport(int ID, nvdla_cc_credit_t* payload, sc_time& delay) = 0;
// Target Socket (unrecognized protocol: nvdla_dat_info_update_t): dat_up_cdma2sc
tlm_utils::multi_passthrough_target_socket<NV_NVDLA_csc_base, 32, tlm::tlm_base_protocol_types> dat_up_cdma2sc;
virtual void dat_up_cdma2sc_b_transport(int ID, tlm::tlm_generic_payload& bp, sc_time& delay);
virtual void dat_up_cdma2sc_b_transport(int ID, nvdla_dat_info_update_t* payload, sc_time& delay) = 0;
// Target Socket (unrecognized protocol: nvdla_wt_info_update_t): wt_up_cdma2sc
tlm_utils::multi_passthrough_target_socket<NV_NVDLA_csc_base, 32, tlm::tlm_base_protocol_types> wt_up_cdma2sc;
virtual void wt_up_cdma2sc_b_transport(int ID, tlm::tlm_generic_payload& bp, sc_time& delay);
virtual void wt_up_cdma2sc_b_transport(int ID, nvdla_wt_info_update_t* payload, sc_time& delay) = 0;
// Initiator Socket (unrecognized protocol: nvdla_xx2csb_resp_t): csc2csb_resp
tlm::tlm_generic_payload csc2csb_resp_bp;
nvdla_xx2csb_resp_t csc2csb_resp_payload;
tlm_utils::multi_passthrough_initiator_socket<NV_NVDLA_csc_base, 32, tlm::tlm_base_protocol_types> csc2csb_resp;
virtual void csc2csb_resp_b_transport(nvdla_xx2csb_resp_t* payload, sc_time& delay);
// Initiator Socket (unrecognized protocol: nvdla_dat_info_update_t): dat_up_sc2cdma
tlm::tlm_generic_payload dat_up_sc2cdma_bp;
nvdla_dat_info_update_t dat_up_sc2cdma_payload;
tlm_utils::multi_passthrough_initiator_socket<NV_NVDLA_csc_base, 32, tlm::tlm_base_protocol_types> dat_up_sc2cdma;
virtual void dat_up_sc2cdma_b_transport(nvdla_dat_info_update_t* payload, sc_time& delay);
// Initiator Socket (unrecognized protocol: nvdla_ram_rd_valid_port_RADDR_12_RDATA_1024_t): sc2buf_dat_rd
tlm::tlm_generic_payload sc2buf_dat_rd_bp;
nvdla_ram_rd_valid_port_RADDR_12_RDATA_1024_t sc2buf_dat_rd_payload;
tlm_utils::multi_passthrough_initiator_socket<NV_NVDLA_csc_base, 32, tlm::tlm_base_protocol_types> sc2buf_dat_rd;
virtual void sc2buf_dat_rd_b_transport(nvdla_ram_rd_valid_port_RADDR_12_RDATA_1024_t* payload, sc_time& delay);
// Initiator Socket (unrecognized protocol: nvdla_ram_rd_valid_port_RADDR_12_RDATA_1024_t): sc2buf_wt_rd
tlm::tlm_generic_payload sc2buf_wt_rd_bp;
nvdla_ram_rd_valid_port_RADDR_12_RDATA_1024_t sc2buf_wt_rd_payload;
tlm_utils::multi_passthrough_initiator_socket<NV_NVDLA_csc_base, 32, tlm::tlm_base_protocol_types> sc2buf_wt_rd;
virtual void sc2buf_wt_rd_b_transport(nvdla_ram_rd_valid_port_RADDR_12_RDATA_1024_t* payload, sc_time& delay);
// Initiator Socket (unrecognized protocol: nvdla_ram_rd_valid_port_RADDR_8_RDATA_1024_t): sc2buf_wmb_rd
tlm::tlm_generic_payload sc2buf_wmb_rd_bp;
nvdla_ram_rd_valid_port_RADDR_12_RDATA_1024_t sc2buf_wmb_rd_payload;
tlm_utils::multi_passthrough_initiator_socket<NV_NVDLA_csc_base, 32, tlm::tlm_base_protocol_types> sc2buf_wmb_rd;
virtual void sc2buf_wmb_rd_b_transport(nvdla_ram_rd_valid_port_RADDR_8_RDATA_1024_t* payload, sc_time& delay);
// Initiator Socket (unrecognized protocol: nvdla_sc2mac_data_if_t): sc2mac_dat
tlm::tlm_generic_payload sc2mac_a_dat_bp;
nvdla_sc2mac_data_if_t sc2mac_a_dat_payload;
tlm_utils::multi_passthrough_initiator_socket<NV_NVDLA_csc_base, 32, tlm::tlm_base_protocol_types> sc2mac_dat_a;
virtual void sc2mac_a_dat_b_transport(nvdla_sc2mac_data_if_t* payload, sc_time& delay);
tlm::tlm_generic_payload sc2mac_b_dat_bp;
nvdla_sc2mac_data_if_t sc2mac_b_dat_payload;
tlm_utils::multi_passthrough_initiator_socket<NV_NVDLA_csc_base, 32, tlm::tlm_base_protocol_types> sc2mac_dat_b;
virtual void sc2mac_b_dat_b_transport(nvdla_sc2mac_data_if_t* payload, sc_time& delay);
// Initiator Socket (unrecognized protocol: nvdla_sc2mac_weight_if_t): sc2mac_wt
tlm::tlm_generic_payload sc2mac_a_wt_bp;
nvdla_sc2mac_weight_if_t sc2mac_a_wt_payload;
tlm_utils::multi_passthrough_initiator_socket<NV_NVDLA_csc_base, 32, tlm::tlm_base_protocol_types> sc2mac_wt_a;
virtual void sc2mac_a_wt_b_transport(nvdla_sc2mac_weight_if_t* payload, sc_time& delay);
tlm::tlm_generic_payload sc2mac_b_wt_bp;
nvdla_sc2mac_weight_if_t sc2mac_b_wt_payload;
tlm_utils::multi_passthrough_initiator_socket<NV_NVDLA_csc_base, 32, tlm::tlm_base_protocol_types> sc2mac_wt_b;
virtual void sc2mac_b_wt_b_transport(nvdla_sc2mac_weight_if_t* payload, sc_time& delay);
// Initiator Socket (unrecognized protocol: nvdla_wt_info_update_t): wt_up_sc2cdma
tlm::tlm_generic_payload wt_up_sc2cdma_bp;
nvdla_wt_info_update_t wt_up_sc2cdma_payload;
tlm_utils::multi_passthrough_initiator_socket<NV_NVDLA_csc_base, 32, tlm::tlm_base_protocol_types> wt_up_sc2cdma;
virtual void wt_up_sc2cdma_b_transport(nvdla_wt_info_update_t* payload, sc_time& delay);
// Destructor
virtual ~NV_NVDLA_csc_base() {}
};
// Constructor for base SystemC class for module NV_NVDLA_csc
inline NV_NVDLA_csc_base::NV_NVDLA_csc_base(const sc_module_name name)
: sc_module(name),
csb2csc_req("csb2csc_req"),
accu2sc_credit("accu2sc_credit"),
dat_up_cdma2sc("dat_up_cdma2sc"),
wt_up_cdma2sc("wt_up_cdma2sc"),
csc2csb_resp_bp(),
csc2csb_resp("csc2csb_resp"),
dat_up_sc2cdma_bp(),
dat_up_sc2cdma("dat_up_sc2cdma"),
sc2buf_dat_rd_bp(),
sc2buf_dat_rd("sc2buf_dat_rd"),
sc2buf_wt_rd_bp(),
sc2buf_wt_rd("sc2buf_wt_rd"),
sc2buf_wmb_rd_bp(),
sc2buf_wmb_rd("sc2buf_wmb_rd"),
sc2mac_a_dat_bp(),
sc2mac_dat_a("sc2mac_dat_a"),
sc2mac_b_dat_bp(),
sc2mac_dat_b("sc2mac_dat_b"),
sc2mac_a_wt_bp(),
sc2mac_wt_a("sc2mac_wt_a"),
sc2mac_b_wt_bp(),
sc2mac_wt_b("sc2mac_wt_b"),
wt_up_sc2cdma_bp(),
wt_up_sc2cdma("wt_up_sc2cdma")
{
// Target Socket (unrecognized protocol: NV_MSDEC_csb2xx_16m_secure_be_lvl_t): csb2csc_req
this->csb2csc_req.register_b_transport(this, &NV_NVDLA_csc_base::csb2csc_req_b_transport);
// Target Socket (unrecognized protocol: nvdla_cc_credit_t): accu2sc_credit
this->accu2sc_credit.register_b_transport(this, &NV_NVDLA_csc_base::accu2sc_credit_b_transport);
// Target Socket (unrecognized protocol: nvdla_dat_info_update_t): dat_up_cdma2sc
this->dat_up_cdma2sc.register_b_transport(this, &NV_NVDLA_csc_base::dat_up_cdma2sc_b_transport);
// Target Socket (unrecognized protocol: nvdla_wt_info_update_t): wt_up_cdma2sc
this->wt_up_cdma2sc.register_b_transport(this, &NV_NVDLA_csc_base::wt_up_cdma2sc_b_transport);
}
inline void
NV_NVDLA_csc_base::csb2csc_req_b_transport(int ID, tlm::tlm_generic_payload& bp, sc_time& delay)
{
NV_MSDEC_csb2xx_16m_secure_be_lvl_t* payload = (NV_MSDEC_csb2xx_16m_secure_be_lvl_t*) bp.get_data_ptr();
csb2csc_req_b_transport(ID, payload, delay);
}
inline void
NV_NVDLA_csc_base::accu2sc_credit_b_transport(int ID, tlm::tlm_generic_payload& bp, sc_time& delay)
{
nvdla_cc_credit_t* payload = (nvdla_cc_credit_t*) bp.get_data_ptr();
accu2sc_credit_b_transport(ID, payload, delay);
}
inline void
NV_NVDLA_csc_base::dat_up_cdma2sc_b_transport(int ID, tlm::tlm_generic_payload& bp, sc_time& delay)
{
nvdla_dat_info_update_t* payload = (nvdla_dat_info_update_t*) bp.get_data_ptr();
dat_up_cdma2sc_b_transport(ID, payload, delay);
}
inline void
NV_NVDLA_csc_base::wt_up_cdma2sc_b_transport(int ID, tlm::tlm_generic_payload& bp, sc_time& delay)
{
nvdla_wt_info_update_t* payload = (nvdla_wt_info_update_t*) bp.get_data_ptr();
wt_up_cdma2sc_b_transport(ID, payload, delay);
}
inline void
NV_NVDLA_csc_base::csc2csb_resp_b_transport(nvdla_xx2csb_resp_t* payload, sc_time& delay)
{
csc2csb_resp_bp.set_data_ptr((unsigned char*) payload);
for (uint8_t socket_id=0; socket_id < csc2csb_resp.size(); socket_id++) {
csc2csb_resp[socket_id]->b_transport(csc2csb_resp_bp, delay);
}
}
inline void
NV_NVDLA_csc_base::dat_up_sc2cdma_b_transport(nvdla_dat_info_update_t* payload, sc_time& delay)
{
dat_up_sc2cdma_bp.set_data_ptr((unsigned char*) payload);
for (uint8_t socket_id=0; socket_id < dat_up_sc2cdma.size(); socket_id++) {
dat_up_sc2cdma[socket_id]->b_transport(dat_up_sc2cdma_bp, delay);
}
}
inline void
NV_NVDLA_csc_base::sc2buf_dat_rd_b_transport(nvdla_ram_rd_valid_port_RADDR_12_RDATA_1024_t* payload, sc_time& delay)
{
sc2buf_dat_rd_bp.set_data_ptr((unsigned char*) payload);
for (uint8_t socket_id=0; socket_id < sc2buf_dat_rd.size(); socket_id++) {
sc2buf_dat_rd[socket_id]->b_transport(sc2buf_dat_rd_bp, delay);
}
}
inline void
NV_NVDLA_csc_base::sc2buf_wt_rd_b_transport(nvdla_ram_rd_valid_port_RADDR_12_RDATA_1024_t* payload, sc_time& delay)
{
sc2buf_wt_rd_bp.set_data_ptr((unsigned char*) payload);
for (uint8_t socket_id=0; socket_id < sc2buf_wt_rd.size(); socket_id++) {
sc2buf_wt_rd[socket_id]->b_transport(sc2buf_wt_rd_bp, delay);
}
}
inline void
NV_NVDLA_csc_base::sc2buf_wmb_rd_b_transport(nvdla_ram_rd_valid_port_RADDR_8_RDATA_1024_t* payload, sc_time& delay)
{
sc2buf_wmb_rd_bp.set_data_ptr((unsigned char*) payload);
for (uint8_t socket_id=0; socket_id < sc2buf_wmb_rd.size(); socket_id++) {
sc2buf_wmb_rd[socket_id]->b_transport(sc2buf_wmb_rd_bp, delay);
}
}
inline void
NV_NVDLA_csc_base::sc2mac_a_dat_b_transport(nvdla_sc2mac_data_if_t* payload, sc_time& delay)
{
sc2mac_a_dat_bp.set_data_ptr((unsigned char*) payload);
for (uint8_t socket_id=0; socket_id < sc2mac_dat_a.size(); socket_id++) {
sc2mac_dat_a[socket_id]->b_transport(sc2mac_a_dat_bp, delay);
}
}
inline void
NV_NVDLA_csc_base::sc2mac_b_dat_b_transport(nvdla_sc2mac_data_if_t* payload, sc_time& delay)
{
sc2mac_b_dat_bp.set_data_ptr((unsigned char*) payload);
for (uint8_t socket_id=0; socket_id < sc2mac_dat_b.size(); socket_id++) {
sc2mac_dat_b[socket_id]->b_transport(sc2mac_b_dat_bp, delay);
}
}
inline void
NV_NVDLA_csc_base::sc2mac_a_wt_b_transport(nvdla_sc2mac_weight_if_t* payload, sc_time& delay)
{
sc2mac_a_wt_bp.set_data_ptr((unsigned char*) payload);
for (uint8_t socket_id=0; socket_id < sc2mac_dat_a.size(); socket_id++) {
sc2mac_wt_a[socket_id]->b_transport(sc2mac_a_wt_bp, delay);
}
}
inline void
NV_NVDLA_csc_base::sc2mac_b_wt_b_transport(nvdla_sc2mac_weight_if_t* payload, sc_time& delay)
{
sc2mac_b_wt_bp.set_data_ptr((unsigned char*) payload);
for (uint8_t socket_id=0; socket_id < sc2mac_dat_b.size(); socket_id++) {
sc2mac_wt_b[socket_id]->b_transport(sc2mac_b_wt_bp, delay);
}
}
inline void
NV_NVDLA_csc_base::wt_up_sc2cdma_b_transport(nvdla_wt_info_update_t* payload, sc_time& delay)
{
wt_up_sc2cdma_bp.set_data_ptr((unsigned char*) payload);
for (uint8_t socket_id=0; socket_id < wt_up_sc2cdma.size(); socket_id++) {
wt_up_sc2cdma[socket_id]->b_transport(wt_up_sc2cdma_bp, delay);
}
}
SCSIM_NAMESPACE_END()
#endif
|
#include <systemc.h>
SC_MODULE(nand_gate) {
public:
sc_in<bool> inp_a, inp_b;
sc_out<bool> out;
SC_HAS_PROCESS(nand_gate);
nand_gate(sc_module_name nm);
private:
void nand_main(void);
};
|
#include <systemc.h>
SC_MODULE(nand_gate) {
public:
sc_in<bool> inp_a, inp_b;
sc_out<bool> out;
SC_HAS_PROCESS(nand_gate);
nand_gate(sc_module_name nm);
private:
void nand_main(void);
};
|
#include <systemc.h>
SC_MODULE(nand_gate) {
public:
sc_in<bool> inp_a, inp_b;
sc_out<bool> out;
SC_HAS_PROCESS(nand_gate);
nand_gate(sc_module_name nm);
private:
void nand_main(void);
};
|
/*****************************************************************************
Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
more contributor license agreements. See the NOTICE file distributed
with this work for additional information regarding copyright ownership.
Accellera licenses this file to you under the Apache License, Version 2.0
(the "License"); you may not use this file except in compliance with the
License. You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
implied. See the License for the specific language governing
permissions and limitations under the License.
*****************************************************************************/
/*****************************************************************************
simple_bus_master_direct.h : The monitor (master) using the direct BUS
interface.
Original Author: Ric Hilderink, Synopsys, Inc., 2001-10-11
*****************************************************************************/
/*****************************************************************************
MODIFICATION LOG - modifiers, enter your name, affiliation, date and
changes you are making here.
Name, Affiliation, Date:
Description of Modification:
*****************************************************************************/
#ifndef __simple_bus_master_direct_h
#define __simple_bus_master_direct_h
#include <systemc.h>
#include "simple_bus_direct_if.h"
SC_MODULE(simple_bus_master_direct)
{
// ports
sc_in_clk clock;
sc_port<simple_bus_direct_if> bus_port;
SC_HAS_PROCESS(simple_bus_master_direct);
// constructor
simple_bus_master_direct(sc_module_name name_
, unsigned int address
, int timeout
, bool verbose = true)
: sc_module(name_)
, m_address(address)
, m_timeout(timeout)
, m_verbose(verbose)
{
// process declaration
SC_THREAD(main_action);
}
// process
void main_action();
private:
unsigned int m_address;
int m_timeout;
bool m_verbose;
}; // end class simple_bus_master_direct
#endif
|
#ifndef _DRAM_H_
#define _DRAM_H_
#include <stdint.h>
#include <systemc.h>
#include <ahb_slave_if.h>
#include <math.h>
#define READ_PIPELINE
#define REF_TIME 6400000 //#cycle @ 100MHz (10ns)
#define REF_CYCLE 8192
#define CL 10 //ns
#define CWL 10 //ns
#define tRAS 12000 // Active to Precharge
#define tRP 10 // Precharge to Active ns
#define DRAM_CLK 6 // NS
enum ST_SDRAM {IDLE, // 0
RowActive, // 1
READ, // 2
WRITE, // 3
PRECHARGE // 4
};
enum BURST_STATE{
FIRST_BURST,
BURST,
NO_BURST
};
/* module of RAM */
class DRAM: public ahb_slave_if, public sc_module
{
public:
SC_HAS_PROCESS(DRAM);
DRAM(sc_module_name name, uint32_t mapping_size, const char* slave_num);
~DRAM();
bool read(uint32_t*, uint32_t, int);
bool write(uint32_t, uint32_t, int);
virtual bool local_access(bool write, uint32_t addr, uint32_t& data, unsigned int length,uint32_t burst_length);
//DRAM Model
void InitDramController();
bool NeedActive(unsigned int addr);
bool NeedPrecharge(unsigned int addr, unsigned int tRAS_count);
private:
uint8_t* bank;
uint32_t bank_bit;
uint32_t row_bit;
uint32_t col_bit;
uint32_t dw_bit;
inline uint32_t* ptr_word(uint32_t addr)
{
return (uint32_t*)(bank + addr);
}
inline uint16_t* ptr_hword(uint32_t addr)
{
return (uint16_t*)(bank + addr);
}
inline uint8_t* ptr_byte(uint32_t addr)
{
return (uint8_t*)(bank + addr);
}
//DRAM Model
ST_SDRAM state;
unsigned int AddrOffset_Bank;
unsigned int AddrOffset_Row;
unsigned int AddrOffset_Col;
unsigned int AddrMask_Bank;
unsigned int AddrMask_Row;
unsigned int AddrMask_Col;
unsigned int Index_Bank;
unsigned int Index_Row;
unsigned int Index_Col;
unsigned int prev_Bank;
unsigned int prev_Row;
void InitAddressDecode();
void AddrDecode(unsigned int addr);
unsigned int GetMask(unsigned int bit);
char dram_name[16];
uint32_t precharge_counter;
int b_length;
BURST_STATE burst_state;
int pre_burst;
bool pre_w_burst;
bool pre_r_burst;
};
#endif
|
//
//------------------------------------------------------------//
// Copyright 2009-2012 Mentor Graphics Corporation //
// All Rights Reserved Worldwid //
// //
// Licensed under the Apache License, Version 2.0 (the //
// "License"); you may not use this file except in //
// compliance with the License. You may obtain a copy of //
// the License at //
// //
// http://www.apache.org/licenses/LICENSE-2.0 //
// //
// Unless required by applicable law or agreed to in //
// writing, software distributed under the License is //
// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR //
// CONDITIONS OF ANY KIND, either express or implied. See //
// the License for the specific language governing //
// permissions and limitations under the License. //
//------------------------------------------------------------//
//-----------------------------------------------------------------------------
// Title: SC Consumer
//
// Topic: Description
//
// A simple SC consumer TLM model that prints received transactions (of type
// ~tlm_generic_payload~ and sends them out its ~ap~ analysis port.
//
// This example uses the ~simple_target_socket~, a derivative of the TLM
// core class, ~tlm_target_socket~. Unlike the ~tlm_target_socket~, the simple
// socket does not require the module to inherit and implement all four
// target socket interface methods. Instead, you only need to register the
// interfaces you actually implement, ~b_transport~ in this case. This is what
// makes these sockets simple, flexible, and convenient.
//
// While trivial in functionality, the model demonstrates use of TLM ports
// to facilitate external communication.
//
// - Users of the model are not coupled to its internal implementation, using
// only the provided TLM port and socket to communicate.
//
// - The model itself does not refer to anything outside its encapsulated
// implementation. It does not know nor care about what might
// be driving its ~in~ socket or who might be listening on its ~ap~
// analysis port.
//-----------------------------------------------------------------------------
// (inline source)
#include <string>
#include <iomanip>
using std::string;
#include <systemc.h>
#include <tlm.h>
using namespace sc_core;
using namespace tlm;
#include "simple_target_socket.h"
using tlm_utils::simple_target_socket;
class consumer : public sc_module
{
public:
simple_target_socket<consumer> in; // defaults to tlm_gp
tlm_analysis_port<tlm_generic_payload> ap;
consumer(sc_module_name nm) : in("in"), ap("ap")
{
in.register_b_transport(this, &consumer::b_transport);
}
virtual void b_transport(tlm_generic_payload &gp, sc_time &t) {
char unsigned *data;
int len;
len = gp.get_data_length();
data = gp.get_data_ptr();
cout << sc_time_stamp() << " [CONSUMER/GP/RECV] ";
cout << "cmd:" << gp.get_command()
<< " addr:" << hex << gp.get_address() << " data:{ ";
for (int i=0; i<len; i++)
cout << hex << (int)*(data+i) << " ";
cout << "}" << endl;
wait(t);
t = SC_ZERO_TIME;
ap.write(gp);
}
};
|
#include <systemc.h>
#include <iostream>
#include "constants.h"
#include "fifo.h"
SC_MODULE(decod) {
/*****************************************************
Interface with REG
******************************************************/
// adresses of Rs and Rd
sc_out<sc_uint<6>> RADR1_SD;
sc_out<sc_uint<6>> RADR2_SD;
// Data read in registers
sc_in<sc_uint<32>> RDATA1_SR;
sc_in<sc_uint<32>> RDATA2_SR;
// Current value of PC
sc_in<sc_uint<32>> READ_PC_SR;
// Port to write into PC
sc_out<sc_uint<32>> WRITE_PC_SD;
sc_out<bool> WRITE_PC_ENABLE_SD;
/*****************************************************
Interface with EXE
******************************************************/
sc_out<sc_uint<32>> OP1_RD;
sc_out<sc_uint<32>> OP2_RD;
/* Command sent to EXE.
In case of a shift :
- 0 : Shift Left Logical (sll)
- 1 : Shift Right Logical (srl)
- 2 : Shift Right Arithmetic (sra)
In case of an ALU operation :
- 0 : add
- 1 : and
- 2 : or
- 3 : xor
In case of an SLT operation
- 0 : slt
- 1 : sltu
*/
sc_out<sc_uint<2>> EXE_CMD_RD;
sc_out<bool> NEG_OP2_RD; // negates the second operator, to do substractions
sc_out<bool> WB_RD; // write back the result in reg
sc_out<sc_uint<6>> EXE_DEST_SD; // the destination register
/* operation types :
- 0 : alu
- 1 : shifter
- 2 : slt
*/
sc_out<sc_uint<3>> OPTYPE_RD;
sc_out<sc_uint<32>> MEM_DATA_RD; // data sent to mem for storage
sc_out<bool> MEM_LOAD_RD; // a memory load
sc_out<bool> MEM_STORE_RD; // a memory store
sc_out<bool> MEM_SIGN_EXTEND_RD; // loads and stores can be signed or unsigned
sc_out<sc_uint<2>> MEM_SIZE_RD; // mem accesses can be words, half words or bytes
/*****************************************************
Interface with DEC2IF
******************************************************/
sc_in<bool> DEC2IF_POP_SI; // The POP signal coming from Ifetch
sc_out<bool> DEC2IF_EMPTY_SD;
sc_out<sc_bv<32>> PC_RD; // the output of the fifo, containing the PC of the next instruction
/*****************************************************
Interface with IF2DEC
******************************************************/
sc_in<sc_bv<32>> INSTR_RI; // The instruction coming from Ifetch
sc_in<sc_uint<32>> PC_RI; // The pc of the instruction being executed
sc_in<bool> IF2DEC_EMPTY_SI;
sc_out<bool> IF2DEC_POP_SD; // the POP signal sent to Ifetch
sc_out<bool> IF2DEC_FLUSH_SD; // Signal sent to IFETCH to flush all instructions
/*****************************************************
Interface with DEC2EXE
******************************************************/
sc_in<bool> DEC2EXE_POP_SE; // The POP signal coming from EXE
sc_out<bool> DEC2EXE_EMPTY_SD;
sc_signal<sc_bv<DEC2EXE_SIZE>> dec2exe_out_sd;
/*****************************************************
BYPASSES
******************************************************/
// see the bypasses process in dec.cpp, or the documentation, for an explanation
// pipeline data coming from the end of EXE
sc_in<sc_uint<6>> DEST_RE; // the destination register of the data
sc_in<sc_uint<32>> EXE_RES_RE; // the data
sc_in<bool> MEM_LOAD_RE; // whether it is a memory load
sc_in<bool> EXE2MEM_EMPTY_SE; // whether the data is valid
// pipeline data coming from the end of MEM
sc_in<sc_uint<6>> DEST_RM; // the destination register of the data
sc_in<sc_uint<32>> MEM_RES_RM; // the data
sc_in<bool> MEM2WBK_EMPTY_SM; // Whether the data is valid
// Bypass outputs for EXE
sc_out<sc_uint<6>> BP_RADR1_RD; // the register of the data in OP1
sc_out<sc_uint<6>> BP_RADR2_RD; // the register of the data in OP2
sc_out<bool> BLOCK_BP_RD; // prevent any further bypasses
// General Interface :
sc_in_clk CLK;
sc_in<bool> RESET;
// Signals :
sc_signal<sc_uint<32>> rdata1_sd;
sc_signal<sc_uint<32>> rdata2_sd;
sc_signal<bool> invalid_operand_sd;
// fifo dec2if :
sc_signal<sc_bv<32>> dec2if_in_sd; // pc sent to fifo
sc_signal<bool> dec2if_push_sd;
sc_signal<bool> dec2if_full_sd;
sc_signal<sc_bv<32>> dec2if_out_sd;
// fifo dec2exe :
sc_signal<sc_bv<DEC2EXE_SIZE>> dec2exe_in_sd;
sc_signal<bool> dec2exe_push_sd;
sc_signal<bool> dec2exe_full_sd;
// Instruction format type :
sc_signal<bool> r_type_inst_sd; // R type format
sc_signal<bool> i_type_inst_sd; // I type format
sc_signal<bool> s_type_inst_sd; // S type format
sc_signal<bool> b_type_inst_sd; // B type format
sc_signal<bool> u_type_inst_sd; // U type format
sc_signal<bool> j_type_inst_sd; // J type format
sc_signal<bool> jalr_type_inst_sd; // JALR has a specific opcode
// R-type Instructions :
sc_signal<bool> add_i_sd;
sc_signal<bool> slt_i_sd;
sc_signal<bool> sltu_i_sd;
sc_signal<bool> and_i_sd;
sc_signal<bool> or_i_sd;
sc_signal<bool> xor_i_sd;
sc_signal<bool> sll_i_sd;
sc_signal<bool> srl_i_sd;
sc_signal<bool> sub_i_sd;
sc_signal<bool> sra_i_sd;
// I-type Instructions :
sc_signal<bool> addi_i_sd;
sc_signal<bool> slti_i_sd;
sc_signal<bool> sltiu_i_sd;
sc_signal<bool> andi_i_sd;
sc_signal<bool> ori_i_sd;
sc_signal<bool> xori_i_sd;
sc_signal<bool> jalr_i_sd;
sc_signal<bool> fence_i_sd;
// I-type shift instructions :
sc_signal<bool> slli_i_sd;
sc_signal<bool> srli_i_sd;
sc_signal<bool> srai_i_sd;
// I-type load instructions :
sc_signal<bool> lw_i_sd;
sc_signal<bool> lh_i_sd;
sc_signal<bool> lhu_i_sd;
sc_signal<bool> lb_i_sd;
sc_signal<bool> lbu_i_sd;
// B-type Instruction :
sc_signal<bool> beq_i_sd;
sc_signal<bool> bne_i_sd;
sc_signal<bool> blt_i_sd;
sc_signal<bool> bge_i_sd;
sc_signal<bool> bltu_i_sd;
sc_signal<bool> bgeu_i_sd;
// U-type Instruction :
sc_signal<bool> lui_i_sd;
sc_signal<bool> auipc_i_sd;
// J-type Instruction :
sc_signal<bool> jal_i_sd;
// S-type Instructions :
sc_signal<bool> sw_i_sd;
sc_signal<bool> sh_i_sd;
sc_signal<bool> sb_i_sd;
// Offset for branch :
sc_signal<sc_uint<32>> offset_branch_sd;
// PC gestion :
sc_signal<bool> inc_pc_sd;
sc_signal<bool> jump_sd;
// Pipeline Gestion
sc_signal<bool> stall_sd;
sc_signal<bool> normal_sd;
sc_signal<bool> block_in_dec_sd;
// Internal signals :
sc_signal<sc_uint<6>> adr_dest_sd;
sc_signal<sc_uint<32>> exe_op1_sd;
sc_signal<sc_uint<32>> exe_op2_sd;
sc_signal<sc_uint<32>> mem_data_sd;
sc_signal<sc_uint<2>> mem_size_sd;
sc_signal<bool> mem_load_sd;
sc_signal<bool> mem_store_sd;
sc_signal<sc_uint<2>> exe_cmd_sd;
sc_signal<sc_uint<2>> optype_sd;
sc_signal<bool> exe_neg_op2_sd;
sc_signal<bool> exe_wb_sd;
sc_signal<bool> mem_sign_extend_sd;
sc_signal<bool> block_bp_sd;
// Instance used :
fifo<32> dec2if;
fifo<DEC2EXE_SIZE> dec2exe;
void concat_dec2exe();
void unconcat_dec2exe();
void decoding_instruction_type();
void decoding_instruction();
void pre_reg_read_decoding();
void post_reg_read_decoding();
void pc_inc();
void bypasses();
void stall_method();
void trace(sc_trace_file * tf);
SC_CTOR(decod) : dec2if("dec2if"), dec2exe("dec2exe") {
dec2if.DATAIN_S(dec2if_in_sd);
dec2if.DATAOUT_R(PC_RD);
dec2if.EMPTY_S(DEC2IF_EMPTY_SD);
dec2if.FULL_S(dec2if_full_sd);
dec2if.PUSH_S(dec2if_push_sd);
dec2if.POP_S(DEC2IF_POP_SI);
dec2if.CLK(CLK);
dec2if.RESET(RESET);
dec2exe.DATAIN_S(dec2exe_in_sd);
dec2exe.DATAOUT_R(dec2exe_out_sd);
dec2exe.EMPTY_S(DEC2EXE_EMPTY_SD);
dec2exe.FULL_S(dec2exe_full_sd);
dec2exe.PUSH_S(dec2exe_push_sd);
dec2exe.POP_S(DEC2EXE_POP_SE);
dec2exe.CLK(CLK);
dec2exe.RESET(RESET);
SC_METHOD(concat_dec2exe)
sensitive << dec2exe_in_sd << exe_op1_sd << exe_op2_sd << exe_cmd_sd << exe_neg_op2_sd
<< exe_wb_sd << mem_data_sd << mem_load_sd << mem_store_sd << mem_sign_extend_sd
<< mem_size_sd << optype_sd << adr_dest_sd << slti_i_sd << slt_i_sd << sltiu_i_sd
<< sltu_i_sd << RADR1_SD << RADR2_SD << block_bp_sd;
SC_METHOD(unconcat_dec2exe)
sensitive << dec2exe_out_sd;
SC_METHOD(stall_method)
sensitive << b_type_inst_sd << jalr_type_inst_sd << j_type_inst_sd << invalid_operand_sd
<< DEC2EXE_EMPTY_SD << EXE2MEM_EMPTY_SE << IF2DEC_EMPTY_SI << dec2exe_full_sd
<< block_in_dec_sd;
SC_METHOD(decoding_instruction_type)
sensitive << INSTR_RI << READ_PC_SR;
SC_METHOD(decoding_instruction)
sensitive << INSTR_RI;
SC_METHOD(pre_reg_read_decoding)
sensitive << INSTR_RI << r_type_inst_sd << i_type_inst_sd << i_type_inst_sd
<< s_type_inst_sd << b_type_inst_sd << u_type_inst_sd << j_type_inst_sd
<< jalr_type_inst_sd << beq_i_sd << bne_i_sd << blt_i_sd << bge_i_sd << bltu_i_sd
<< bgeu_i_sd << fence_i_sd << RESET;
SC_METHOD(post_reg_read_decoding)
sensitive << i_type_inst_sd << s_type_inst_sd << b_type_inst_sd << u_type_inst_sd
<< j_type_inst_sd << jalr_type_inst_sd << beq_i_sd << bne_i_sd << blt_i_sd
<< bge_i_sd << bltu_i_sd << bgeu_i_sd << IF2DEC_EMPTY_SI << dec2if_push_sd
<< READ_PC_SR << stall_sd << dec2if_push_sd << add_i_sd << slt_i_sd << sltu_i_sd
<< and_i_sd << or_i_sd << xor_i_sd << sll_i_sd << srl_i_sd << sub_i_sd << sra_i_sd
<< addi_i_sd << slti_i_sd << sltiu_i_sd << andi_i_sd << ori_i_sd << xori_i_sd
<< jalr_i_sd << slli_i_sd << srli_i_sd << srai_i_sd << lw_i_sd << lh_i_sd
<< lhu_i_sd << lb_i_sd << lbu_i_sd << beq_i_sd << bne_i_sd << blt_i_sd << bge_i_sd
<< bltu_i_sd << bgeu_i_sd << lui_i_sd << auipc_i_sd << jal_i_sd << sw_i_sd
<< sh_i_sd << sb_i_sd << j_type_inst_sd << jalr_type_inst_sd << dec2exe_push_sd
<< rdata1_sd << rdata2_sd << fence_i_sd << PC_RI;
SC_METHOD(pc_inc)
sensitive << CLK.pos() << READ_PC_SR << offset_branch_sd << inc_pc_sd << jump_sd << PC_RI
<< dec2if_full_sd << IF2DEC_EMPTY_SI << stall_sd;
SC_METHOD(bypasses);
sensitive << RDATA1_SR << RDATA2_SR << DEST_RE << EXE_RES_RE << DEST_RM
<< MEM_RES_RM << RADR1_SD << EXE_DEST_SD << RADR2_SD << EXE2MEM_EMPTY_SE
<< DEC2EXE_EMPTY_SD << MEM_LOAD_RE << MEM2WBK_EMPTY_SM;
reset_signal_is(RESET, false);
}
}; |
#include <systemc.h>
#include "memory.cpp"
int sc_main (int argc, char* argv[]) {
int data;
ram mem("MEM", 1024);
// Open VCD file
sc_trace_file *wf = sc_create_vcd_trace_file("memory");
wf->set_time_unit(1, SC_NS);
// Dump the desired signals
sc_trace(wf, data, "data");
sc_start();
cout << "@" << sc_time_stamp()<< endl;
printf("Writing in zero time\n");
printf("WR: addr = 0x10, data = 0xaced\n");
printf("WR: addr = 0x12, data = 0xbeef\n");
printf("WR: addr = 0x13, data = 0xdead\n");
printf("WR: addr = 0x14, data = 0x1234\n");
mem.wr(0x10, 0xaced);
mem.wr(0x11, 0xbeef);
mem.wr(0x12, 0xdead);
mem.wr(0x13, 0x1234);
cout << "@" << sc_time_stamp()<< endl;
cout << "Reading in zero time" <<endl;
data = mem.rd(0x10);
printf("Rd: addr = 0x10, data = %x\n",data);
data = mem.rd(0x11);
printf("Rd: addr = 0x11, data = %x\n",data);
data = mem.rd(0x12);
printf("Rd: addr = 0x12, data = %x\n",data);
data = mem.rd(0x13);
printf("Rd: addr = 0x13, data = %x\n",data);
cout << "@" << sc_time_stamp()<< endl;
cout << "@" << sc_time_stamp() <<" Terminating simulation\n" << endl;
sc_close_vcd_trace_file(wf);
return 0;// Terminate simulation
} |
// ================================================================
// NVDLA Open Source Project
//
// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
// NVDLA Open Hardware License; Check "LICENSE" which comes with
// this distribution for more information.
// ================================================================
// File Name: NV_NVDLA_rbk_base.h
#ifndef _NV_NVDLA_RBK_BASE_H_
#define _NV_NVDLA_RBK_BASE_H_
#define SC_INCLUDE_DYNAMIC_PROCESSES
#include "NV_MSDEC_csb2xx_16m_secure_be_lvl_iface.h"
#include "nvdla_xx2csb_resp_iface.h"
#include "nvdla_dma_rd_req_iface.h"
#include "nvdla_dma_rd_rsp_iface.h"
#include "nvdla_dma_wr_req_iface.h"
#include "scsim_common.h"
#include <systemc.h>
#include <tlm.h>
#include <tlm_utils/multi_passthrough_initiator_socket.h>
#include <tlm_utils/multi_passthrough_target_socket.h>
SCSIM_NAMESPACE_START(cmod)
// Base SystemC class for module NV_NVDLA_rbk
class NV_NVDLA_rbk_base : public sc_module
{
public:
// Constructor
NV_NVDLA_rbk_base(const sc_module_name name);
// Target Socket (unrecognized protocol: NV_MSDEC_csb2xx_16m_secure_be_lvl_t): csb2rbk_req
tlm_utils::multi_passthrough_target_socket<NV_NVDLA_rbk_base, 32, tlm::tlm_base_protocol_types> csb2rbk_req;
virtual void csb2rbk_req_b_transport(int ID, tlm::tlm_generic_payload& bp, sc_time& delay);
virtual void csb2rbk_req_b_transport(int ID, NV_MSDEC_csb2xx_16m_secure_be_lvl_t* payload, sc_time& delay) = 0;
// Target Socket (unrecognized protocol: nvdla_dma_rd_rsp_t): cvif2rbk_rd_rsp
tlm_utils::multi_passthrough_target_socket<NV_NVDLA_rbk_base, 32, tlm::tlm_base_protocol_types> cvif2rbk_rd_rsp;
virtual void cvif2rbk_rd_rsp_b_transport(int ID, tlm::tlm_generic_payload& bp, sc_time& delay);
virtual void cvif2rbk_rd_rsp_b_transport(int ID, nvdla_dma_rd_rsp_t* payload, sc_time& delay) = 0;
// Target Socket (unrecognized protocol: nvdla_dma_rd_rsp_t): mcif2rbk_rd_rsp
tlm_utils::multi_passthrough_target_socket<NV_NVDLA_rbk_base, 32, tlm::tlm_base_protocol_types> mcif2rbk_rd_rsp;
virtual void mcif2rbk_rd_rsp_b_transport(int ID, tlm::tlm_generic_payload& bp, sc_time& delay);
virtual void mcif2rbk_rd_rsp_b_transport(int ID, nvdla_dma_rd_rsp_t* payload, sc_time& delay) = 0;
// Port has no flow: cvif2rbk_wr_rsp
sc_in<bool> cvif2rbk_wr_rsp;
// Port has no flow: mcif2rbk_wr_rsp
sc_in<bool> mcif2rbk_wr_rsp;
// Initiator Socket (unrecognized protocol: nvdla_xx2csb_resp_t): rbk2csb_resp
tlm::tlm_generic_payload rbk2csb_resp_bp;
nvdla_xx2csb_resp_t rbk2csb_resp_payload;
tlm_utils::multi_passthrough_initiator_socket<NV_NVDLA_rbk_base, 32, tlm::tlm_base_protocol_types> rbk2csb_resp;
virtual void rbk2csb_resp_b_transport(nvdla_xx2csb_resp_t* payload, sc_time& delay);
// Initiator Socket (unrecognized protocol: nvdla_dma_rd_req_t): rbk2cvif_rd_req
tlm::tlm_generic_payload rbk2cvif_rd_req_bp;
nvdla_dma_rd_req_t rbk2cvif_rd_req_payload;
tlm_utils::multi_passthrough_initiator_socket<NV_NVDLA_rbk_base, 32, tlm::tlm_base_protocol_types> rbk2cvif_rd_req;
virtual void rbk2cvif_rd_req_b_transport(nvdla_dma_rd_req_t* payload, sc_time& delay);
// Initiator Socket (unrecognized protocol: nvdla_dma_rd_req_t): rbk2mcif_rd_req
tlm::tlm_generic_payload rbk2mcif_rd_req_bp;
nvdla_dma_rd_req_t rbk2mcif_rd_req_payload;
tlm_utils::multi_passthrough_initiator_socket<NV_NVDLA_rbk_base, 32, tlm::tlm_base_protocol_types> rbk2mcif_rd_req;
virtual void rbk2mcif_rd_req_b_transport(nvdla_dma_rd_req_t* payload, sc_time& delay);
// Initiator Socket (unrecognized protocol: nvdla_dma_wr_req_t): rbk2cvif_wr_req
tlm::tlm_generic_payload rbk2cvif_wr_req_bp;
nvdla_dma_wr_req_t rbk2cvif_wr_req_payload;
tlm_utils::multi_passthrough_initiator_socket<NV_NVDLA_rbk_base, 32, tlm::tlm_base_protocol_types> rbk2cvif_wr_req;
virtual void rbk2cvif_wr_req_b_transport(nvdla_dma_wr_req_t* payload, sc_time& delay);
// Initiator Socket (unrecognized protocol: nvdla_dma_wr_req_t): rbk2mcif_wr_req
tlm::tlm_generic_payload rbk2mcif_wr_req_bp;
nvdla_dma_wr_req_t rbk2mcif_wr_req_payload;
tlm_utils::multi_passthrough_initiator_socket<NV_NVDLA_rbk_base, 32, tlm::tlm_base_protocol_types> rbk2mcif_wr_req;
virtual void rbk2mcif_wr_req_b_transport(nvdla_dma_wr_req_t* payload, sc_time& delay);
// Port has no flow: rbk2glb_done_intr
sc_vector< sc_out<bool> > rbk2glb_done_intr;
// Destructor
virtual ~NV_NVDLA_rbk_base() {}
};
// Constructor for base SystemC class for module NV_NVDLA_rbk
inline NV_NVDLA_rbk_base::NV_NVDLA_rbk_base(const sc_module_name name)
: sc_module(name),
csb2rbk_req("csb2rbk_req"),
cvif2rbk_rd_rsp("cvif2rbk_rd_rsp"),
mcif2rbk_rd_rsp("mcif2rbk_rd_rsp"),
rbk2csb_resp_bp(),
rbk2csb_resp("rbk2csb_resp"),
rbk2cvif_rd_req_bp(),
rbk2cvif_rd_req("rbk2cvif_rd_req"),
rbk2mcif_rd_req_bp(),
rbk2mcif_rd_req("rbk2mcif_rd_req"),
rbk2cvif_wr_req_bp(),
rbk2cvif_wr_req("rbk2cvif_wr_req"),
rbk2mcif_wr_req_bp(),
rbk2mcif_wr_req("rbk2mcif_wr_req"),
rbk2glb_done_intr("rbk2glb_done_intr", 2)
{
// Target Socket (unrecognized protocol: NV_MSDEC_csb2xx_16m_secure_be_lvl_t): csb2rbk_req
this->csb2rbk_req.register_b_transport(this, &NV_NVDLA_rbk_base::csb2rbk_req_b_transport);
// Target Socket (unrecognized protocol: nvdla_dma_rd_rsp_t): cvif2rbk_rd_rsp
this->cvif2rbk_rd_rsp.register_b_transport(this, &NV_NVDLA_rbk_base::cvif2rbk_rd_rsp_b_transport);
// Target Socket (unrecognized protocol: nvdla_dma_rd_rsp_t): mcif2rbk_rd_rsp
this->mcif2rbk_rd_rsp.register_b_transport(this, &NV_NVDLA_rbk_base::mcif2rbk_rd_rsp_b_transport);
}
inline void
NV_NVDLA_rbk_base::csb2rbk_req_b_transport(int ID, tlm::tlm_generic_payload& bp, sc_time& delay)
{
NV_MSDEC_csb2xx_16m_secure_be_lvl_t* payload = (NV_MSDEC_csb2xx_16m_secure_be_lvl_t*) bp.get_data_ptr();
csb2rbk_req_b_transport(ID, payload, delay);
}
inline void
NV_NVDLA_rbk_base::cvif2rbk_rd_rsp_b_transport(int ID, tlm::tlm_generic_payload& bp, sc_time& delay)
{
nvdla_dma_rd_rsp_t* payload = (nvdla_dma_rd_rsp_t*) bp.get_data_ptr();
cvif2rbk_rd_rsp_b_transport(ID, payload, delay);
}
inline void
NV_NVDLA_rbk_base::mcif2rbk_rd_rsp_b_transport(int ID, tlm::tlm_generic_payload& bp, sc_time& delay)
{
nvdla_dma_rd_rsp_t* payload = (nvdla_dma_rd_rsp_t*) bp.get_data_ptr();
mcif2rbk_rd_rsp_b_transport(ID, payload, delay);
}
inline void
NV_NVDLA_rbk_base::rbk2csb_resp_b_transport(nvdla_xx2csb_resp_t* payload, sc_time& delay)
{
rbk2csb_resp_bp.set_data_ptr((unsigned char*) payload);
for (uint8_t socket_id=0; socket_id < rbk2csb_resp.size(); socket_id++) {
rbk2csb_resp[socket_id]->b_transport(rbk2csb_resp_bp, delay);
}
}
inline void
NV_NVDLA_rbk_base::rbk2cvif_rd_req_b_transport(nvdla_dma_rd_req_t* payload, sc_time& delay)
{
rbk2cvif_rd_req_bp.set_data_ptr((unsigned char*) payload);
for (uint8_t socket_id=0; socket_id < rbk2cvif_rd_req.size(); socket_id++) {
rbk2cvif_rd_req[socket_id]->b_transport(rbk2cvif_rd_req_bp, delay);
}
}
inline void
NV_NVDLA_rbk_base::rbk2mcif_rd_req_b_transport(nvdla_dma_rd_req_t* payload, sc_time& delay)
{
rbk2mcif_rd_req_bp.set_data_ptr((unsigned char*) payload);
for (uint8_t socket_id=0; socket_id < rbk2mcif_rd_req.size(); socket_id++) {
rbk2mcif_rd_req[socket_id]->b_transport(rbk2mcif_rd_req_bp, delay);
}
}
inline void
NV_NVDLA_rbk_base::rbk2cvif_wr_req_b_transport(nvdla_dma_wr_req_t* payload, sc_time& delay)
{
rbk2cvif_wr_req_bp.set_data_ptr((unsigned char*) payload);
for (uint8_t socket_id=0; socket_id < rbk2cvif_wr_req.size(); socket_id++) {
rbk2cvif_wr_req[socket_id]->b_transport(rbk2cvif_wr_req_bp, delay);
}
}
inline void
NV_NVDLA_rbk_base::rbk2mcif_wr_req_b_transport(nvdla_dma_wr_req_t* payload, sc_time& delay)
{
rbk2mcif_wr_req_bp.set_data_ptr((unsigned char*) payload);
for (uint8_t socket_id=0; socket_id < rbk2mcif_wr_req.size(); socket_id++) {
rbk2mcif_wr_req[socket_id]->b_transport(rbk2mcif_wr_req_bp, delay);
}
}
SCSIM_NAMESPACE_END()
#endif
|
// ================================================================
// NVDLA Open Source Project
//
// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
// NVDLA Open Hardware License; Check "LICENSE" which comes with
// this distribution for more information.
// ================================================================
// File Name: NV_NVDLA_rbk_base.h
#ifndef _NV_NVDLA_RBK_BASE_H_
#define _NV_NVDLA_RBK_BASE_H_
#define SC_INCLUDE_DYNAMIC_PROCESSES
#include "NV_MSDEC_csb2xx_16m_secure_be_lvl_iface.h"
#include "nvdla_xx2csb_resp_iface.h"
#include "nvdla_dma_rd_req_iface.h"
#include "nvdla_dma_rd_rsp_iface.h"
#include "nvdla_dma_wr_req_iface.h"
#include "scsim_common.h"
#include <systemc.h>
#include <tlm.h>
#include <tlm_utils/multi_passthrough_initiator_socket.h>
#include <tlm_utils/multi_passthrough_target_socket.h>
SCSIM_NAMESPACE_START(cmod)
// Base SystemC class for module NV_NVDLA_rbk
class NV_NVDLA_rbk_base : public sc_module
{
public:
// Constructor
NV_NVDLA_rbk_base(const sc_module_name name);
// Target Socket (unrecognized protocol: NV_MSDEC_csb2xx_16m_secure_be_lvl_t): csb2rbk_req
tlm_utils::multi_passthrough_target_socket<NV_NVDLA_rbk_base, 32, tlm::tlm_base_protocol_types> csb2rbk_req;
virtual void csb2rbk_req_b_transport(int ID, tlm::tlm_generic_payload& bp, sc_time& delay);
virtual void csb2rbk_req_b_transport(int ID, NV_MSDEC_csb2xx_16m_secure_be_lvl_t* payload, sc_time& delay) = 0;
// Target Socket (unrecognized protocol: nvdla_dma_rd_rsp_t): cvif2rbk_rd_rsp
tlm_utils::multi_passthrough_target_socket<NV_NVDLA_rbk_base, 32, tlm::tlm_base_protocol_types> cvif2rbk_rd_rsp;
virtual void cvif2rbk_rd_rsp_b_transport(int ID, tlm::tlm_generic_payload& bp, sc_time& delay);
virtual void cvif2rbk_rd_rsp_b_transport(int ID, nvdla_dma_rd_rsp_t* payload, sc_time& delay) = 0;
// Target Socket (unrecognized protocol: nvdla_dma_rd_rsp_t): mcif2rbk_rd_rsp
tlm_utils::multi_passthrough_target_socket<NV_NVDLA_rbk_base, 32, tlm::tlm_base_protocol_types> mcif2rbk_rd_rsp;
virtual void mcif2rbk_rd_rsp_b_transport(int ID, tlm::tlm_generic_payload& bp, sc_time& delay);
virtual void mcif2rbk_rd_rsp_b_transport(int ID, nvdla_dma_rd_rsp_t* payload, sc_time& delay) = 0;
// Port has no flow: cvif2rbk_wr_rsp
sc_in<bool> cvif2rbk_wr_rsp;
// Port has no flow: mcif2rbk_wr_rsp
sc_in<bool> mcif2rbk_wr_rsp;
// Initiator Socket (unrecognized protocol: nvdla_xx2csb_resp_t): rbk2csb_resp
tlm::tlm_generic_payload rbk2csb_resp_bp;
nvdla_xx2csb_resp_t rbk2csb_resp_payload;
tlm_utils::multi_passthrough_initiator_socket<NV_NVDLA_rbk_base, 32, tlm::tlm_base_protocol_types> rbk2csb_resp;
virtual void rbk2csb_resp_b_transport(nvdla_xx2csb_resp_t* payload, sc_time& delay);
// Initiator Socket (unrecognized protocol: nvdla_dma_rd_req_t): rbk2cvif_rd_req
tlm::tlm_generic_payload rbk2cvif_rd_req_bp;
nvdla_dma_rd_req_t rbk2cvif_rd_req_payload;
tlm_utils::multi_passthrough_initiator_socket<NV_NVDLA_rbk_base, 32, tlm::tlm_base_protocol_types> rbk2cvif_rd_req;
virtual void rbk2cvif_rd_req_b_transport(nvdla_dma_rd_req_t* payload, sc_time& delay);
// Initiator Socket (unrecognized protocol: nvdla_dma_rd_req_t): rbk2mcif_rd_req
tlm::tlm_generic_payload rbk2mcif_rd_req_bp;
nvdla_dma_rd_req_t rbk2mcif_rd_req_payload;
tlm_utils::multi_passthrough_initiator_socket<NV_NVDLA_rbk_base, 32, tlm::tlm_base_protocol_types> rbk2mcif_rd_req;
virtual void rbk2mcif_rd_req_b_transport(nvdla_dma_rd_req_t* payload, sc_time& delay);
// Initiator Socket (unrecognized protocol: nvdla_dma_wr_req_t): rbk2cvif_wr_req
tlm::tlm_generic_payload rbk2cvif_wr_req_bp;
nvdla_dma_wr_req_t rbk2cvif_wr_req_payload;
tlm_utils::multi_passthrough_initiator_socket<NV_NVDLA_rbk_base, 32, tlm::tlm_base_protocol_types> rbk2cvif_wr_req;
virtual void rbk2cvif_wr_req_b_transport(nvdla_dma_wr_req_t* payload, sc_time& delay);
// Initiator Socket (unrecognized protocol: nvdla_dma_wr_req_t): rbk2mcif_wr_req
tlm::tlm_generic_payload rbk2mcif_wr_req_bp;
nvdla_dma_wr_req_t rbk2mcif_wr_req_payload;
tlm_utils::multi_passthrough_initiator_socket<NV_NVDLA_rbk_base, 32, tlm::tlm_base_protocol_types> rbk2mcif_wr_req;
virtual void rbk2mcif_wr_req_b_transport(nvdla_dma_wr_req_t* payload, sc_time& delay);
// Port has no flow: rbk2glb_done_intr
sc_vector< sc_out<bool> > rbk2glb_done_intr;
// Destructor
virtual ~NV_NVDLA_rbk_base() {}
};
// Constructor for base SystemC class for module NV_NVDLA_rbk
inline NV_NVDLA_rbk_base::NV_NVDLA_rbk_base(const sc_module_name name)
: sc_module(name),
csb2rbk_req("csb2rbk_req"),
cvif2rbk_rd_rsp("cvif2rbk_rd_rsp"),
mcif2rbk_rd_rsp("mcif2rbk_rd_rsp"),
rbk2csb_resp_bp(),
rbk2csb_resp("rbk2csb_resp"),
rbk2cvif_rd_req_bp(),
rbk2cvif_rd_req("rbk2cvif_rd_req"),
rbk2mcif_rd_req_bp(),
rbk2mcif_rd_req("rbk2mcif_rd_req"),
rbk2cvif_wr_req_bp(),
rbk2cvif_wr_req("rbk2cvif_wr_req"),
rbk2mcif_wr_req_bp(),
rbk2mcif_wr_req("rbk2mcif_wr_req"),
rbk2glb_done_intr("rbk2glb_done_intr", 2)
{
// Target Socket (unrecognized protocol: NV_MSDEC_csb2xx_16m_secure_be_lvl_t): csb2rbk_req
this->csb2rbk_req.register_b_transport(this, &NV_NVDLA_rbk_base::csb2rbk_req_b_transport);
// Target Socket (unrecognized protocol: nvdla_dma_rd_rsp_t): cvif2rbk_rd_rsp
this->cvif2rbk_rd_rsp.register_b_transport(this, &NV_NVDLA_rbk_base::cvif2rbk_rd_rsp_b_transport);
// Target Socket (unrecognized protocol: nvdla_dma_rd_rsp_t): mcif2rbk_rd_rsp
this->mcif2rbk_rd_rsp.register_b_transport(this, &NV_NVDLA_rbk_base::mcif2rbk_rd_rsp_b_transport);
}
inline void
NV_NVDLA_rbk_base::csb2rbk_req_b_transport(int ID, tlm::tlm_generic_payload& bp, sc_time& delay)
{
NV_MSDEC_csb2xx_16m_secure_be_lvl_t* payload = (NV_MSDEC_csb2xx_16m_secure_be_lvl_t*) bp.get_data_ptr();
csb2rbk_req_b_transport(ID, payload, delay);
}
inline void
NV_NVDLA_rbk_base::cvif2rbk_rd_rsp_b_transport(int ID, tlm::tlm_generic_payload& bp, sc_time& delay)
{
nvdla_dma_rd_rsp_t* payload = (nvdla_dma_rd_rsp_t*) bp.get_data_ptr();
cvif2rbk_rd_rsp_b_transport(ID, payload, delay);
}
inline void
NV_NVDLA_rbk_base::mcif2rbk_rd_rsp_b_transport(int ID, tlm::tlm_generic_payload& bp, sc_time& delay)
{
nvdla_dma_rd_rsp_t* payload = (nvdla_dma_rd_rsp_t*) bp.get_data_ptr();
mcif2rbk_rd_rsp_b_transport(ID, payload, delay);
}
inline void
NV_NVDLA_rbk_base::rbk2csb_resp_b_transport(nvdla_xx2csb_resp_t* payload, sc_time& delay)
{
rbk2csb_resp_bp.set_data_ptr((unsigned char*) payload);
for (uint8_t socket_id=0; socket_id < rbk2csb_resp.size(); socket_id++) {
rbk2csb_resp[socket_id]->b_transport(rbk2csb_resp_bp, delay);
}
}
inline void
NV_NVDLA_rbk_base::rbk2cvif_rd_req_b_transport(nvdla_dma_rd_req_t* payload, sc_time& delay)
{
rbk2cvif_rd_req_bp.set_data_ptr((unsigned char*) payload);
for (uint8_t socket_id=0; socket_id < rbk2cvif_rd_req.size(); socket_id++) {
rbk2cvif_rd_req[socket_id]->b_transport(rbk2cvif_rd_req_bp, delay);
}
}
inline void
NV_NVDLA_rbk_base::rbk2mcif_rd_req_b_transport(nvdla_dma_rd_req_t* payload, sc_time& delay)
{
rbk2mcif_rd_req_bp.set_data_ptr((unsigned char*) payload);
for (uint8_t socket_id=0; socket_id < rbk2mcif_rd_req.size(); socket_id++) {
rbk2mcif_rd_req[socket_id]->b_transport(rbk2mcif_rd_req_bp, delay);
}
}
inline void
NV_NVDLA_rbk_base::rbk2cvif_wr_req_b_transport(nvdla_dma_wr_req_t* payload, sc_time& delay)
{
rbk2cvif_wr_req_bp.set_data_ptr((unsigned char*) payload);
for (uint8_t socket_id=0; socket_id < rbk2cvif_wr_req.size(); socket_id++) {
rbk2cvif_wr_req[socket_id]->b_transport(rbk2cvif_wr_req_bp, delay);
}
}
inline void
NV_NVDLA_rbk_base::rbk2mcif_wr_req_b_transport(nvdla_dma_wr_req_t* payload, sc_time& delay)
{
rbk2mcif_wr_req_bp.set_data_ptr((unsigned char*) payload);
for (uint8_t socket_id=0; socket_id < rbk2mcif_wr_req.size(); socket_id++) {
rbk2mcif_wr_req[socket_id]->b_transport(rbk2mcif_wr_req_bp, delay);
}
}
SCSIM_NAMESPACE_END()
#endif
|
//
// Copyright 2022 Sergey Khabarov, [email protected]
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
#pragma once
#include <systemc.h>
#include "../ambalib/types_amba.h"
#include "../ambalib/types_pnp.h"
#include "../ambalib/axi_slv.h"
#include "../techmap/mem/ram_bytes_tech.h"
#include "api_core.h"
namespace debugger {
template<int abits = 17>
SC_MODULE(axi_sram) {
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
sc_in<mapinfo_type> i_mapinfo; // interconnect slot information
sc_out<dev_config_type> o_cfg; // Device descriptor
sc_in<axi4_slave_in_type> i_xslvi; // AXI Slave to Bridge interface
sc_out<axi4_slave_out_type> o_xslvo; // AXI Bridge to Slave interface
void comb();
SC_HAS_PROCESS(axi_sram);
axi_sram(sc_module_name name,
bool async_reset);
virtual ~axi_sram();
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
bool async_reset_;
sc_signal<bool> w_req_valid;
sc_signal<sc_uint<CFG_SYSBUS_ADDR_BITS>> wb_req_addr;
sc_signal<sc_uint<8>> wb_req_size;
sc_signal<bool> w_req_write;
sc_signal<sc_uint<CFG_SYSBUS_DATA_BITS>> wb_req_wdata;
sc_signal<sc_uint<CFG_SYSBUS_DATA_BYTES>> wb_req_wstrb;
sc_signal<bool> w_req_last;
sc_signal<bool> w_req_ready;
sc_signal<bool> w_resp_valid;
sc_signal<sc_uint<CFG_SYSBUS_DATA_BITS>> wb_resp_rdata;
sc_signal<bool> wb_resp_err;
sc_signal<sc_uint<abits>> wb_req_addr_abits;
axi_slv *xslv0;
ram_bytes_tech<abits, CFG_LOG2_SYSBUS_DATA_BYTES> *tech0;
};
template<int abits>
axi_sram<abits>::axi_sram(sc_module_name name,
bool async_reset)
: sc_module(name),
i_clk("i_clk"),
i_nrst("i_nrst"),
i_mapinfo("i_mapinfo"),
o_cfg("o_cfg"),
i_xslvi("i_xslvi"),
o_xslvo("o_xslvo") {
async_reset_ = async_reset;
xslv0 = 0;
tech0 = 0;
xslv0 = new axi_slv("xslv0", async_reset,
VENDOR_OPTIMITECH,
OPTIMITECH_SRAM);
xslv0->i_clk(i_clk);
xslv0->i_nrst(i_nrst);
xslv0->i_mapinfo(i_mapinfo);
xslv0->o_cfg(o_cfg);
xslv0->i_xslvi(i_xslvi);
xslv0->o_xslvo(o_xslvo);
xslv0->o_req_valid(w_req_valid);
xslv0->o_req_addr(wb_req_addr);
xslv0->o_req_size(wb_req_size);
xslv0->o_req_write(w_req_write);
xslv0->o_req_wdata(wb_req_wdata);
xslv0->o_req_wstrb(wb_req_wstrb);
xslv0->o_req_last(w_req_last);
xslv0->i_req_ready(w_req_ready);
xslv0->i_resp_valid(w_resp_valid);
xslv0->i_resp_rdata(wb_resp_rdata);
xslv0->i_resp_err(wb_resp_err);
tech0 = new ram_bytes_tech<abits,
CFG_LOG2_SYSBUS_DATA_BYTES>("tech0");
tech0->i_clk(i_clk);
tech0->i_addr(wb_req_addr_abits);
tech0->i_wena(w_req_write);
tech0->i_wstrb(wb_req_wstrb);
tech0->i_wdata(wb_req_wdata);
tech0->o_rdata(wb_resp_rdata);
SC_METHOD(comb);
sensitive << i_nrst;
sensitive << i_mapinfo;
sensitive << i_xslvi;
sensitive << w_req_valid;
sensitive << wb_req_addr;
sensitive << wb_req_size;
sensitive << w_req_write;
sensitive << wb_req_wdata;
sensitive << wb_req_wstrb;
sensitive << w_req_last;
sensitive << w_req_ready;
sensitive << w_resp_valid;
sensitive << wb_resp_rdata;
sensitive << wb_resp_err;
sensitive << wb_req_addr_abits;
}
template<int abits>
axi_sram<abits>::~axi_sram() {
if (xslv0) {
delete xslv0;
}
if (tech0) {
delete tech0;
}
}
template<int abits>
void axi_sram<abits>::generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd) {
if (o_vcd) {
sc_trace(o_vcd, i_xslvi, i_xslvi.name());
sc_trace(o_vcd, o_xslvo, o_xslvo.name());
}
if (xslv0) {
xslv0->generateVCD(i_vcd, o_vcd);
}
}
template<int abits>
void axi_sram<abits>::comb() {
wb_req_addr_abits = wb_req_addr.read()((abits - 1), 0);
w_req_ready = 1;
w_resp_valid = 1;
wb_resp_err = 0;
}
} // namespace debugger
|
/*****************************************************************************
Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
more contributor license agreements. See the NOTICE file distributed
with this work for additional information regarding copyright ownership.
Accellera licenses this file to you under the Apache License, Version 2.0
(the "License"); you may not use this file except in compliance with the
License. You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
implied. See the License for the specific language governing
permissions and limitations under the License.
*****************************************************************************/
/*****************************************************************************
adder.h : N-port adder. Header-only SystemC module, for PImpl idiom
demonstration
Original Author: Roman I. Popov, Intel
*****************************************************************************/
#ifndef ADDER_H_
#define ADDER_H_
#include <systemc.h>
template <typename T, int N_INPUTS>
struct adder : sc_module {
// SC_NAMED - convenient macro to initialize sc_object name with variable name
sc_out<T> SC_NAMED(res);
// SC_NAMED supports passing arbitrary number of parameters
sc_vector<sc_in<T>> SC_NAMED(din, N_INPUTS);
SC_CTOR(adder){}
private:
// In-class initialization of SC_METHOD
// As a second parameter SC_METHOD_IMP takes arbitrary code that can be used to initialize process
// curly braces are optional
SC_METHOD_IMP(add_method, { for(auto &d : din) sensitive << d; } ); // Body can be in or outside of class
};
template <typename T, int N_INPUTS>
void adder<T,N_INPUTS>::add_method()
{
T result = 0;
for(auto &d : din)
result += d.read();
res = result;
}
#endif // ADDER_H_ |
/*
* timer.h
*
* Created on: 18 de abr de 2017
* Author: vieira
*/
#ifndef INCLUDE_TIMER_H_
#define INCLUDE_TIMER_H_
#include <systemc.h>
SC_MODULE(Timer){
sc_in<bool> at, reset;
sc_in<bool> clk;
sc_out<bool> IL, IC;
SC_CTOR(Timer){
counter = 0;
SC_METHOD(proc);
sensitive << reset << at << clk.pos();
SC_METHOD(printcounter);
sensitive << clk.pos();
}
private:
void proc();
void printcounter();
int counter;
};
#endif /* INCLUDE_TIMER_H_ */
|
#include <systemc.h>
#include "sbox.h"
#ifndef __SUBBYTES_H__
#define __SUBBYTES_H__
using namespace sc_core;
SC_MODULE( subBytes ) {
sc_in<sc_logic> in[128];
sc_out<sc_logic> out[128];
sbox* sub_Bytes_0;
sbox* sub_Bytes_1;
sbox* sub_Bytes_2;
sbox* sub_Bytes_3;
sbox* sub_Bytes_4;
sbox* sub_Bytes_5;
sbox* sub_Bytes_6;
sbox* sub_Bytes_7;
sbox* sub_Bytes_8;
sbox* sub_Bytes_9;
sbox* sub_Bytes_10;
sbox* sub_Bytes_11;
sbox* sub_Bytes_12;
sbox* sub_Bytes_13;
sbox* sub_Bytes_14;
sbox* sub_Bytes_15;
SC_CTOR( subBytes ) {
sub_Bytes_0 = new sbox("sub_Bytes_0");
sub_Bytes_0->a[0](in[0]);
sub_Bytes_0->a[1](in[1]);
sub_Bytes_0->a[2](in[2]);
sub_Bytes_0->a[3](in[3]);
sub_Bytes_0->a[4](in[4]);
sub_Bytes_0->a[5](in[5]);
sub_Bytes_0->a[6](in[6]);
sub_Bytes_0->a[7](in[7]);
sub_Bytes_0->c[0](out[0]);
sub_Bytes_0->c[1](out[1]);
sub_Bytes_0->c[2](out[2]);
sub_Bytes_0->c[3](out[3]);
sub_Bytes_0->c[4](out[4]);
sub_Bytes_0->c[5](out[5]);
sub_Bytes_0->c[6](out[6]);
sub_Bytes_0->c[7](out[7]);
sub_Bytes_14 = new sbox("sub_Bytes_14");
sub_Bytes_14->a[0](in[8]);
sub_Bytes_14->a[1](in[9]);
sub_Bytes_14->a[2](in[10]);
sub_Bytes_14->a[3](in[11]);
sub_Bytes_14->a[4](in[12]);
sub_Bytes_14->a[5](in[13]);
sub_Bytes_14->a[6](in[14]);
sub_Bytes_14->a[7](in[15]);
sub_Bytes_14->c[0](out[8]);
sub_Bytes_14->c[1](out[9]);
sub_Bytes_14->c[2](out[10]);
sub_Bytes_14->c[3](out[11]);
sub_Bytes_14->c[4](out[12]);
sub_Bytes_14->c[5](out[13]);
sub_Bytes_14->c[6](out[14]);
sub_Bytes_14->c[7](out[15]);
sub_Bytes_4 = new sbox("sub_Bytes_4");
sub_Bytes_4->a[0](in[16]);
sub_Bytes_4->a[1](in[17]);
sub_Bytes_4->a[2](in[18]);
sub_Bytes_4->a[3](in[19]);
sub_Bytes_4->a[4](in[20]);
sub_Bytes_4->a[5](in[21]);
sub_Bytes_4->a[6](in[22]);
sub_Bytes_4->a[7](in[23]);
sub_Bytes_4->c[0](out[16]);
sub_Bytes_4->c[1](out[17]);
sub_Bytes_4->c[2](out[18]);
sub_Bytes_4->c[3](out[19]);
sub_Bytes_4->c[4](out[20]);
sub_Bytes_4->c[5](out[21]);
sub_Bytes_4->c[6](out[22]);
sub_Bytes_4->c[7](out[23]);
sub_Bytes_5 = new sbox("sub_Bytes_5");
sub_Bytes_5->a[0](in[24]);
sub_Bytes_5->a[1](in[25]);
sub_Bytes_5->a[2](in[26]);
sub_Bytes_5->a[3](in[27]);
sub_Bytes_5->a[4](in[28]);
sub_Bytes_5->a[5](in[29]);
sub_Bytes_5->a[6](in[30]);
sub_Bytes_5->a[7](in[31]);
sub_Bytes_5->c[0](out[24]);
sub_Bytes_5->c[1](out[25]);
sub_Bytes_5->c[2](out[26]);
sub_Bytes_5->c[3](out[27]);
sub_Bytes_5->c[4](out[28]);
sub_Bytes_5->c[5](out[29]);
sub_Bytes_5->c[6](out[30]);
sub_Bytes_5->c[7](out[31]);
sub_Bytes_6 = new sbox("sub_Bytes_6");
sub_Bytes_6->a[0](in[32]);
sub_Bytes_6->a[1](in[33]);
sub_Bytes_6->a[2](in[34]);
sub_Bytes_6->a[3](in[35]);
sub_Bytes_6->a[4](in[36]);
sub_Bytes_6->a[5](in[37]);
sub_Bytes_6->a[6](in[38]);
sub_Bytes_6->a[7](in[39]);
sub_Bytes_6->c[0](out[32]);
sub_Bytes_6->c[1](out[33]);
sub_Bytes_6->c[2](out[34]);
sub_Bytes_6->c[3](out[35]);
sub_Bytes_6->c[4](out[36]);
sub_Bytes_6->c[5](out[37]);
sub_Bytes_6->c[6](out[38]);
sub_Bytes_6->c[7](out[39]);
sub_Bytes_7 = new sbox("sub_Bytes_7");
sub_Bytes_7->a[0](in[40]);
sub_Bytes_7->a[1](in[41]);
sub_Bytes_7->a[2](in[42]);
sub_Bytes_7->a[3](in[43]);
sub_Bytes_7->a[4](in[44]);
sub_Bytes_7->a[5](in[45]);
sub_Bytes_7->a[6](in[46]);
sub_Bytes_7->a[7](in[47]);
sub_Bytes_7->c[0](out[40]);
sub_Bytes_7->c[1](out[41]);
sub_Bytes_7->c[2](out[42]);
sub_Bytes_7->c[3](out[43]);
sub_Bytes_7->c[4](out[44]);
sub_Bytes_7->c[5](out[45]);
sub_Bytes_7->c[6](out[46]);
sub_Bytes_7->c[7](out[47]);
sub_Bytes_8 = new sbox("sub_Bytes_8");
sub_Bytes_8->a[0](in[48]);
sub_Bytes_8->a[1](in[49]);
sub_Bytes_8->a[2](in[50]);
sub_Bytes_8->a[3](in[51]);
sub_Bytes_8->a[4](in[52]);
sub_Bytes_8->a[5](in[53]);
sub_Bytes_8->a[6](in[54]);
sub_Bytes_8->a[7](in[55]);
sub_Bytes_8->c[0](out[48]);
sub_Bytes_8->c[1](out[49]);
sub_Bytes_8->c[2](out[50]);
sub_Bytes_8->c[3](out[51]);
sub_Bytes_8->c[4](out[52]);
sub_Bytes_8->c[5](out[53]);
sub_Bytes_8->c[6](out[54]);
sub_Bytes_8->c[7](out[55]);
sub_Bytes_9 = new sbox("sub_Bytes_9");
sub_Bytes_9->a[0](in[56]);
sub_Bytes_9->a[1](in[57]);
sub_Bytes_9->a[2](in[58]);
sub_Bytes_9->a[3](in[59]);
sub_Bytes_9->a[4](in[60]);
sub_Bytes_9->a[5](in[61]);
sub_Bytes_9->a[6](in[62]);
sub_Bytes_9->a[7](in[63]);
sub_Bytes_9->c[0](out[56]);
sub_Bytes_9->c[1](out[57]);
sub_Bytes_9->c[2](out[58]);
sub_Bytes_9->c[3](out[59]);
sub_Bytes_9->c[4](out[60]);
sub_Bytes_9->c[5](out[61]);
sub_Bytes_9->c[6](out[62]);
sub_Bytes_9->c[7](out[63]);
sub_Bytes_10 = new sbox("sub_Bytes_10");
sub_Bytes_10->a[0](in[64]);
sub_Bytes_10->a[1](in[65]);
sub_Bytes_10->a[2](in[66]);
sub_Bytes_10->a[3](in[67]);
sub_Bytes_10->a[4](in[68]);
sub_Bytes_10->a[5](in[69]);
sub_Bytes_10->a[6](in[70]);
sub_Bytes_10->a[7](in[71]);
sub_Bytes_10->c[0](out[64]);
sub_Bytes_10->c[1](out[65]);
sub_Bytes_10->c[2](out[66]);
sub_Bytes_10->c[3](out[67]);
sub_Bytes_10->c[4](out[68]);
sub_Bytes_10->c[5](out[69]);
sub_Bytes_10->c[6](out[70]);
sub_Bytes_10->c[7](out[71]);
sub_Bytes_11 = new sbox("sub_Bytes_11");
sub_Bytes_11->a[0](in[72]);
sub_Bytes_11->a[1](in[73]);
sub_Bytes_11->a[2](in[74]);
sub_Bytes_11->a[3](in[75]);
sub_Bytes_11->a[4](in[76]);
sub_Bytes_11->a[5](in[77]);
sub_Bytes_11->a[6](in[78]);
sub_Bytes_11->a[7](in[79]);
sub_Bytes_11->c[0](out[72]);
sub_Bytes_11->c[1](out[73]);
sub_Bytes_11->c[2](out[74]);
sub_Bytes_11->c[3](out[75]);
sub_Bytes_11->c[4](out[76]);
sub_Bytes_11->c[5](out[77]);
sub_Bytes_11->c[6](out[78]);
sub_Bytes_11->c[7](out[79]);
sub_Bytes_12 = new sbox("sub_Bytes_12");
sub_Bytes_12->a[0](in[80]);
sub_Bytes_12->a[1](in[81]);
sub_Bytes_12->a[2](in[82]);
sub_Bytes_12->a[3](in[83]);
sub_Bytes_12->a[4](in[84]);
sub_Bytes_12->a[5](in[85]);
sub_Bytes_12->a[6](in[86]);
sub_Bytes_12->a[7](in[87]);
sub_Bytes_12->c[0](out[80]);
sub_Bytes_12->c[1](out[81]);
sub_Bytes_12->c[2](out[82]);
sub_Bytes_12->c[3](out[83]);
sub_Bytes_12->c[4](out[84]);
sub_Bytes_12->c[5](out[85]);
sub_Bytes_12->c[6](out[86]);
sub_Bytes_12->c[7](out[87]);
sub_Bytes_13 = new sbox("sub_Bytes_13");
sub_Bytes_13->a[0](in[88]);
sub_Bytes_13->a[1](in[89]);
sub_Bytes_13->a[2](in[90]);
sub_Bytes_13->a[3](in[91]);
sub_Bytes_13->a[4](in[92]);
sub_Bytes_13->a[5](in[93]);
sub_Bytes_13->a[6](in[94]);
sub_Bytes_13->a[7](in[95]);
sub_Bytes_13->c[0](out[88]);
sub_Bytes_13->c[1](out[89]);
sub_Bytes_13->c[2](out[90]);
sub_Bytes_13->c[3](out[91]);
sub_Bytes_13->c[4](out[92]);
sub_Bytes_13->c[5](out[93]);
sub_Bytes_13->c[6](out[94]);
sub_Bytes_13->c[7](out[95]);
sub_Bytes_15 = new sbox("sub_Bytes_15");
sub_Bytes_15->a[0](in[96]);
sub_Bytes_15->a[1](in[97]);
sub_Bytes_15->a[2](in[98]);
sub_Bytes_15->a[3](in[99]);
sub_Bytes_15->a[4](in[100]);
sub_Bytes_15->a[5](in[101]);
sub_Bytes_15->a[6](in[102]);
sub_Bytes_15->a[7](in[103]);
sub_Bytes_15->c[0](out[96]);
sub_Bytes_15->c[1](out[97]);
sub_Bytes_15->c[2](out[98]);
sub_Bytes_15->c[3](out[99]);
sub_Bytes_15->c[4](out[100]);
sub_Bytes_15->c[5](out[101]);
sub_Bytes_15->c[6](out[102]);
sub_Bytes_15->c[7](out[103]);
sub_Bytes_1 = new sbox("sub_Bytes_1");
sub_Bytes_1->a[0](in[104]);
sub_Bytes_1->a[1](in[105]);
sub_Bytes_1->a[2](in[106]);
sub_Bytes_1->a[3](in[107]);
sub_Bytes_1->a[4](in[108]);
sub_Bytes_1->a[5](in[109]);
sub_Bytes_1->a[6](in[110]);
sub_Bytes_1->a[7](in[111]);
sub_Bytes_1->c[0](out[104]);
sub_Bytes_1->c[1](out[105]);
sub_Bytes_1->c[2](out[106]);
sub_Bytes_1->c[3](out[107]);
sub_Bytes_1->c[4](out[108]);
sub_Bytes_1->c[5](out[109]);
sub_Bytes_1->c[6](out[110]);
sub_Bytes_1->c[7](out[111]);
sub_Bytes_2 = new sbox("sub_Bytes_2");
sub_Bytes_2->a[0](in[112]);
sub_Bytes_2->a[1](in[113]);
sub_Bytes_2->a[2](in[114]);
sub_Bytes_2->a[3](in[115]);
sub_Bytes_2->a[4](in[116]);
sub_Bytes_2->a[5](in[117]);
sub_Bytes_2->a[6](in[118]);
sub_Bytes_2->a[7](in[119]);
sub_Bytes_2->c[0](out[112]);
sub_Bytes_2->c[1](out[113]);
sub_Bytes_2->c[2](out[114]);
sub_Bytes_2->c[3](out[115]);
sub_Bytes_2->c[4](out[116]);
sub_Bytes_2->c[5](out[117]);
sub_Bytes_2->c[6](out[118]);
sub_Bytes_2->c[7](out[119]);
sub_Bytes_3 = new sbox("sub_Bytes_3");
sub_Bytes_3->a[0](in[120]);
sub_Bytes_3->a[1](in[121]);
sub_Bytes_3->a[2](in[122]);
sub_Bytes_3->a[3](in[123]);
sub_Bytes_3->a[4](in[124]);
sub_Bytes_3->a[5](in[125]);
sub_Bytes_3->a[6](in[126]);
sub_Bytes_3->a[7](in[127]);
sub_Bytes_3->c[0](out[120]);
sub_Bytes_3->c[1](out[121]);
sub_Bytes_3->c[2](out[122]);
sub_Bytes_3->c[3](out[123]);
sub_Bytes_3->c[4](out[124]);
sub_Bytes_3->c[5](out[125]);
sub_Bytes_3->c[6](out[126]);
sub_Bytes_3->c[7](out[127]);
}
};
#endif /* __SUBBYTES_H__ */
|
#pragma once
#include <systemc.h>
#include <iostream>
#include <string>
#include "debug_util.h"
SC_MODULE(shifter) {
sc_in<sc_uint<32>> DIN_SE; // input
sc_in<sc_uint<5>> SHIFT_VAL_SE; // shift value
sc_in<sc_uint<2>> CMD_SE; // command
/*
Command value :
- 0 : Shift Left Logical (sll)
- 1 : Shift Right Logical (srl)
- 2 : Shift Right Arithmetic (sra)
*/
sc_out<sc_uint<32>> DOUT_SE; // output
/*
Vous pouvez ajouter des signaux internes ici.
Si vous les faites, n'oubliez pas de les ajouter à la fonction trace
dans shifter.cpp, pour qu'ils apparaissent dans GTKWAVE
*/
void trace(sc_trace_file * tf);
SC_CTOR(shifter) {}
};
|
#ifdef RGB2GRAY_PV_EN
#ifndef RGB2GRAY_HPP
#define RGB2GRAY_HPP
#include <systemc.h>
SC_MODULE(Rgb2Gray)
{
unsigned char r;
unsigned char g;
unsigned char b;
unsigned char gray_value;
SC_CTOR(Rgb2Gray)
{
}
void set_rgb_pixel(unsigned char r_val, unsigned char g_val, unsigned char b_val);
void compute_gray_value();
unsigned char obtain_gray_value();
};
#endif // RGB2GRAY_HPP
#endif // RGB2GRAY_PV_EN
|
// Copyright (c) 2011-2021 Columbia University, System Level Design Group
// SPDX-License-Identifier: Apache-2.0
#ifndef __GEMM_ACCELERATOR_CONF_INFO_HPP__
#define __GEMM_ACCELERATOR_CONF_INFO_HPP__
#include <systemc.h>
//
// Configuration parameters for the accelerator.
//
class conf_info_t
{
public:
//
// constructors
//
conf_info_t()
{
/* <<--ctor-->> */
this->gemm_m = 64;
this->gemm_n = 64;
this->gemm_k = 64;
}
conf_info_t(
/* <<--ctor-args-->> */
int32_t gemm_m,
int32_t gemm_n,
int32_t gemm_k
)
{
/* <<--ctor-custom-->> */
this->gemm_m = gemm_m;
this->gemm_n = gemm_n;
this->gemm_k = gemm_k;
}
// equals operator
inline bool operator==(const conf_info_t &rhs) const
{
/* <<--eq-->> */
if (gemm_m != rhs.gemm_m) return false;
if (gemm_n != rhs.gemm_n) return false;
if (gemm_k != rhs.gemm_k) return false;
return true;
}
// assignment operator
inline conf_info_t& operator=(const conf_info_t& other)
{
/* <<--assign-->> */
gemm_m = other.gemm_m;
gemm_n = other.gemm_n;
gemm_k = other.gemm_k;
return *this;
}
// VCD dumping function
friend void sc_trace(sc_trace_file *tf, const conf_info_t &v, const std::string &NAME)
{}
// redirection operator
friend ostream& operator << (ostream& os, conf_info_t const &conf_info)
{
os << "{";
/* <<--print-->> */
os << "gemm_m = " << conf_info.gemm_m << ", ";
os << "gemm_n = " << conf_info.gemm_n << ", ";
os << "gemm_k = " << conf_info.gemm_k << "";
os << "}";
return os;
}
/* <<--params-->> */
int32_t gemm_m;
int32_t gemm_n;
int32_t gemm_k;
};
#endif // __GEMM_ACCELERATOR_CONF_INFO_HPP__
|
#ifndef __DW_IntrGen_h
#define __DW_IntrGen_h
#include <systemc.h>
#include <ccss_systemc.h>
#include "ahb_slave_if.h"
#ifdef CCSS_USE_SC_CTOR
#define CCSS_INIT_MEMBERS_PREFIX :
#undef CCSS_USE_SC_CTOR
#else
#define CCSS_INIT_MEMBERS_PREFIX ,
#endif
#ifndef SYNTHESIS
#define CCSS_INIT_MEMBERS CCSS_INIT_MEMBERS_PREFIX \
nFIQ("nFIQ") \
, nIRQ("nIRQ") \
, nRESET("nRESET") \
, VINITHI("VINITHI") \
, clk("clk") \
, INITRAM("INITRAM")
#else
#define CCSS_INIT_MEMBERS
#endif
// The memory is a slave module that stores data values. This
// model can be used as RAM or ROM. An arbitrary number of wait states
// can be specified for read and write data transactions by the parameters
// ReadWaitStates, and WriteWaitStates, with a default value of zero.
// This module implements the slave interface and the debug interface.
// The memory module can be accessed by bus modules with a data bus
// bus width higher than 32.
//
// The memory module has two constructors. The first constructor specifies
// one memory region that is the same for the boot and the normal address modes.
// The first constructor has the following arguments:
//
// - sc_module_name, instance name of the module
//
// - ahb_addr_t, start address of the memory
//
// - ahb_addr_t, end address of the memory
//
// - const sc_string& = "", file name to read initial values
//
// - bool = true, memory encoding (little-endian default)
//
// A second constructor can be used to specify multiple memory regions
// for boot and normal mode. The address ranges are given by the start
// and end addresses for the normal mode followed by the start and end
// addresses for the boot mode. A memory region is disabled by specifying
// zero values for the start and end addresses. The second constructor has
// the following arguments:
//
// - sc_module_name, instance name of the module
//
// - const sc_string& = "", file name to read initial values
//
// - bool = false, memory encoding (little-endian default)
//
// - ahb_addr_t = 0, start address of the memory in normal mode, first region
//
// - ahb_addr_t = 0x3FF, end address of the memory in normal mode, first region
//
// - ahb_addr_t = 0, start address of the memory in boot mode, first region
//
// - ahb_addr_t = 0x3FF, end address of the memory in boot mode, first region
//
// - ahb_addr_t = 0, remapped start address of the memory in normal mode, second region
//
// - ahb_addr_t = 0, remapped end address of the memory in normal mode, second region
//
// - ahb_addr_t = 0, start address of the memory in boot mode, second region
//
// - ahb_addr_t = 0, end address of the memory in boot mode, second region
//
// etc.
//
// The start and end addresses define a memory segment. The start_address,
// the end_address+1, and the memory size, have to be alligned to the
// 1k address boundary. The start_address must also be less than the
// end_address.
//
// The memory is initialized with zero values at reset time. Optionally,
// initialization values can be read from a file. If the constructor argument
// file_name is not empty, values are read from this file until all the memory
// space is written to, or the end of the file is reached.
//
// The values given by the initialization file must be given in hexadecimal
// byte format. The values must be sepatated by blank, tab, or newline characters.
// For example, the following file data:
//
// a1 1f d8
// c7 27 3a
//
// will initialize the memory with the byte values 0xa1, 0x1f, 0xd8, 0xc7,
// 0x27, 0x3a starting at the base address of the memory.
//
// The contents of the memory can be monitored. If monitor update is enabled
// by the DoTrace parameter, the simulation performance decreases.
//
template<class SIF = ahb_slave_if >
class DW_IntrGen// An External Memory Slave Module
: public sc_module, public SIF
{
public:
// parameters
// This identifier for the slave is used by the Inter
// Connection Matrix (ICM) to identify the slave.
CCSS_PARAMETER(int, SlaveID);
// This parameter specifies the number of data cycle wait
// states to complete a data transfer.
CCSS_PARAMETER(int, ReadWaitStates);
// This parameter specifies the number of data cycle wait
// states to complete a data transfer.
CCSS_PARAMETER(int, WriteWaitStates);
// Parameter to enable the read only mode (Read Only Memory)
CCSS_PARAMETER(bool, ReadOnly);
// This flag allows the user to disable the creation of the memory
// table monitor object.
CCSS_PARAMETER(bool, DisableMonitor);
// This flag enables monitoring features if the simulation was
// started with the DisableMonitor flag set to false.
CCSS_PARAMETER(bool, DoTrace);
// ports
// Active low output pin for fast interrupt signal to processor
sc_out<bool> nFIQ;
// Active low output pin for interrupt request signal to processor
sc_out<bool> nIRQ;
// Active low output pin for reset signal to processor
sc_out<bool> nRESET;
// Active high output pin for initializing processor to high vectors.
sc_out<bool> VINITHI;
// Clock input
sc_in_clk clk;
// Active high output for turning TCM functionality on in processor.
sc_out<bool> INITRAM;
// initialize parameters
virtual void InitParameters() {
int _tmp_SlaveID = 1 ;
SlaveID.conditional_init(_tmp_SlaveID);
int _tmp_ReadWaitStates = 0 ;
ReadWaitStates.conditional_init(_tmp_ReadWaitStates);
int _tmp_WriteWaitStates = 0 ;
WriteWaitStates.conditional_init(_tmp_WriteWaitStates);
bool _tmp_ReadOnly = false;
ReadOnly.conditional_init(_tmp_ReadOnly);
bool _tmp_DisableMonitor = false;
DisableMonitor.conditional_init(_tmp_DisableMonitor);
bool _tmp_DoTrace = false;
DoTrace.conditional_init(_tmp_DoTrace);
}
SC_HAS_PROCESS(DW_IntrGen);
// constructor 1
DW_IntrGen(sc_module_name name_, // name of the module
ahb_addr_t start_address, // start address of the memory in normal mode
ahb_addr_t end_address, // end address of the memory in normal mode
const sc_string& file_name = "", // file name to read initial values
bool big_endian = false); // memory encoding (little endian default)
// constructor 2
DW_IntrGen(sc_module_name name_, // name of the module
const sc_string& file_name = "", // file name to read initial values
bool big_endian = false, // memory encoding (little endian default)
ahb_addr_t normal_start_addr1 = 0, // start address of the memory in normal mode, first region
ahb_addr_t normal_end_addr1 = 0x3FF, // end address of the memory in normal mode, first region
ahb_addr_t boot_start_addr1 = 0, // start address of the memory in boot mode, first region
ahb_addr_t boot_end_addr1 = 0, // end address of the memory in boot mode, first region
ahb_addr_t normal_start_addr2 = 0, // remapped start address of the memory in normal mode, second region
ahb_addr_t normal_end_addr2 = 0, // remapped end address of the memory in normal mode, second region
ahb_addr_t boot_start_addr2 = 0, // start address of the memory in boot mode, second region
ahb_addr_t boot_end_addr2 = 0, // end address of the memory in boot mode, second region
ahb_addr_t normal_start_addr3 = 0, // ...
ahb_addr_t normal_end_addr3 = 0,
ahb_addr_t boot_start_addr3 = 0,
ahb_addr_t boot_end_addr3 = 0,
ahb_addr_t normal_start_addr4 = 0,
ahb_addr_t normal_end_addr4 = 0,
ahb_addr_t boot_start_addr4 = 0,
ahb_addr_t boot_end_addr4 = 0,
ahb_addr_t normal_start_addr5 = 0,
ahb_addr_t normal_end_addr5 = 0,
ahb_addr_t boot_start_addr5 = 0,
ahb_addr_t boot_end_addr5 = 0,
ahb_addr_t normal_start_addr6 = 0,
ahb_addr_t normal_end_addr6 = 0,
ahb_addr_t boot_start_addr6 = 0,
ahb_addr_t boot_end_addr6 = 0,
ahb_addr_t normal_start_addr7 = 0,
ahb_addr_t normal_end_addr7 = 0,
ahb_addr_t boot_start_addr7 = 0,
ahb_addr_t boot_end_addr7 = 0,
ahb_addr_t normal_start_addr8 = 0,
ahb_addr_t normal_end_addr8 = 0,
ahb_addr_t boot_start_addr8 = 0,
ahb_addr_t boot_end_addr8 = 0);
~DW_IntrGen();
// interface methods
// Register a port, make sure that only one port
// is connected to the interface.
virtual void
register_port(sc_port_base&,
const char*);
// Register the bus connected to this slave interface.
virtual int
register_bus(int, // bus handle
int, // priority
int, // address bus width in bits
int); // data bus width in bits
// Query the status response of the transaction.
virtual bool
response(int, ahb_hresp&);
// Initiate a read transaction from the slave.
virtual void
read(int, // bus handle, unused here
ahb_addr_t, // address
ahb_hsize); // transfer size
// Write data to the slave.
virtual void
write(int, // bus handle, unused here
ahb_addr_t, // address
ahb_hsize); // transfer size
// This method provides additional control information, e.g.
// the burst mode and the transfer type.
virtual void
control_info(int, // id of the bus
ahb_hburst, // mode of the active burst
ahb_htrans, // the transfer type
ahb_hprot, // access protection information
int, // master id
bool); // master locks the bus
// This method provides control information base on the ARM11 extensions
virtual void
set_ahb11ext_control(int, // bus id
const unsigned int*, // byte strobe line information
bool, // unaligned access indication
int){} // protection domain
// Set the data pointer where the data shoud be
// - written to for a read transaction
// - read from for a write transaction
virtual void
set_data(int, // bus handle, unused here
ahb_data_t); // pointer to the data
// Direct read from the memory for debugging purposes
virtual bool
direct_read(int, // bus handle, unused here
ahb_addr_t, // address
ahb_data_t, // data
int = 4); // number of bytes
// Direct write to the memory for debugging purposes
virtual bool
direct_write(int, // bus handle, unused here
ahb_addr_t, // address
ahb_data_t, // data
int = 4); // number of bytes
// Return the memory map of the slave
virtual const ahb_address_map&
get_address_map(int) {
return _address_map;
}
// Query the name of the slave
virtual const char*
name() const
{return sc_module::name();}
protected:
// main process for interrupt sampling.
void
main_action();
// Read the memory from a file
void
read_from_file(const sc_string&);
// Write the memory contents to a file
void
write_to_file(const sc_string&);
// parameter change handler
void
do_trace_action();
void
create_memory();
// Clear the memory contrents to zero
void
clear_mem();
bool
get_physical_address(unsigned int &);
bool
get_mem(unsigned int,
ahb_data_t,
const unsigned int*,
int);
bool
put_mem(unsigned int,
ahb_data_t,
const unsigned int*,
int);
// Update the table monitor for the memory contents
// complete:
void
set_monitor();
// one word with relative address:
void
set_monitor(int);
// address information
unsigned int _address;
int _address_width_word;
// control information
ahb_hwrite _rwflag;
int _num_bytes;
unsigned int _strobe_width_word;
const unsigned int* _byte_strobe;
bool _unaligned;
int _prot_domain;
ahb_hprot _protection;
int _masterid;
// data location
ahb_data_t _data;
int _data_width_word;
// internal states, storage, and configuration
ahb_address_map _address_map; // vector of up to 8 memory regions
unsigned int _region_offset[8]; // start addresses of each memory region in
// the real linear memory _mem
unsigned int* _mem;
unsigned int _mem_length;
sc_string _file_name;
bool _big_endian;
int _waitstates;
bool _idlebusy;
bool _ready;
bool _okay;
unsigned int _tmp_byte_strobe[4];
ahb_addr_t _xfer_addr[NUM_MASTERS];
bool _xfer_state[NUM_MASTERS];
int _xfer_domain[NUM_MASTERS];
ccss_monitor_table* _mem_monitor_table;
sc_port_base* _slave_port;
int reset_cnt;
int irq_pulse;
int fiq_pulse;
}; // end module DW_IntrGen
#undef CCSS_INIT_MEMBERS_PREFIX
#undef CCSS_INIT_MEMBERS
#endif
|
/*******************************************************************************
* pcf8574.cpp -- Copyright 2020 (c) Glenn Ramalho - RFIDo Design
*******************************************************************************
* Description:
* This is a crude model for the PN532 with firmware v1.6. It will work for
* basic work with a PN532 system.
*******************************************************************************
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
#include <systemc.h>
#include "pcf8574.h"
#include "info.h"
unsigned char pcf8574::sampleport() {
unsigned char samp = 0;
int cnt;
for(cnt = 0; cnt < sig.size(); cnt = cnt + 1) {
if (!sig[cnt]->read().islogic()) {
PRINTF_WARN("PCF8574", "Sampled a signal at level %c",
sig[cnt]->read().to_char());
}
else if (sig[cnt]->read().ishigh()) samp = samp | (1 << cnt);
}
return samp;
}
void pcf8574::intr_th() {
intr.write(GN_LOGIC_Z);
while(1) {
switch (sig.size()) {
case 0: wait(clearintr_ev); break;
case 1:
wait(clearintr_ev | sig[0]->default_event());
break;
case 2:
wait(clearintr_ev |
sig[0]->default_event() | sig[1]->default_event());
break;
case 3:
wait(clearintr_ev |
sig[0]->default_event() | sig[1]->default_event() |
sig[2]->default_event());
break;
case 4:
wait(clearintr_ev |
sig[0]->default_event() | sig[1]->default_event() |
sig[2]->default_event() | sig[3]->default_event());
break;
case 5:
wait(clearintr_ev |
sig[0]->default_event() | sig[1]->default_event() |
sig[2]->default_event() | sig[3]->default_event() |
sig[4]->default_event());
break;
case 6:
wait(clearintr_ev |
sig[0]->default_event() | sig[1]->default_event() |
sig[2]->default_event() | sig[3]->default_event() |
sig[4]->default_event() | sig[5]->default_event());
break;
case 7:
wait(clearintr_ev |
sig[0]->default_event() | sig[1]->default_event() |
sig[2]->default_event() | sig[3]->default_event() |
sig[4]->default_event() | sig[5]->default_event() |
sig[6]->default_event());
break;
default:
wait(clearintr_ev |
sig[0]->default_event() | sig[1]->default_event() |
sig[2]->default_event() | sig[3]->default_event() |
sig[4]->default_event() | sig[5]->default_event() |
sig[6]->default_event() | sig[7]->default_event());
break;
}
/* If we got a lowerintr we lower the line. Anything else raises it.
* Note that we do not raise the interrupt while we were writing.
*/
if (clearintr_ev.triggered()) intr.write(GN_LOGIC_Z);
else if (i2cstate != WRDATA && i2cstate != ACKWRD && i2cstate != ACKWR)
intr.write(GN_LOGIC_0);
}
}
void pcf8574::i2c_th(void) {
int i;
unsigned int devid, data;
/* We begin initializing all ports to weak 1. */
for(i = 0; i < sig.size(); i = i + 1) {
sig[i]->write(GN_LOGIC_W1);
}
/* The interrupt begins as Z. */
intr.write(GN_LOGIC_Z);
/* Then we begin waiting for the I2C commands. */
while(1) {
/* We wait for a change on either the SDA or the SCL. */
wait();
state.write((int)i2cstate);
/* If we get Z or X, we ignore it. */
if (!scl.read().islogic()) {
PRINTF_WARN("PN532", "SCL is not defined");
}
else if (!sda.read().islogic()) {
PRINTF_WARN("PN532", "SDA is not defined");
}
/* At any time a start or stop bit can come in. */
else if (scl.read().ishigh() && sda.value_changed_event().triggered()) {
if (sda.read().islow()) {
/* START BIT */
i2cstate = DEVID;
i = 7;
devid = 0;
}
/* STOP BIT */
else i2cstate = IDLE;
}
/* The rest has to be data changes. For simplicity all data in and flow
* control is here. The data returned is done on another branch.
*/
else if (scl.value_changed_event().triggered() && scl.read().ishigh())
switch(i2cstate) {
case IDLE: break;
case DEVID:
/* We collect all bits of the device ID. The last bit is the R/W
* bit.
*/
if (i > 0) devid = (devid << 1) + ((sda.read().ishigh())?1:0);
/* If the ID matches, we can process it. */
else if (devid == device_id && sda.read().ishigh()) i2cstate=ACKRD;
else if (devid == device_id && sda.read().islow()) i2cstate=ACKWR;
/* If the devid does not match, we return Z. */
else i2cstate = RETZ;
i = i - 1;
break;
/* If the address does not match, we return Z. */
case RETZ:
i2cstate = IDLE;
break;
/* When we recognize the ACKRD, we sample the pins. This will be
* returned via the I2C.
*/
case ACKRD:
i = 7;
i2cstate = READ;
data = sampleport();
/* We also clear the interrupt. */
clearintr_ev.notify();
break;
/* When we hit the ACKWR, all we do is clear the shiftregister to
* begin to receive data.
*/
case ACKWR:
i = 7;
data = 0;
i2cstate = WRDATA;
/* We also clear the interrupt. */
clearintr_ev.notify();
break;
/* Each bit is taken. */
case WRDATA:
/* Just when we enter the WRDATA phase we need to release the SDA */
if (i == 7) sda.write(GN_LOGIC_Z);
/* And the data we collect to drive in the WRD phase. */
data = (data << 1) + ((sda.read().ishigh())?1:0);
if (i == 0) i2cstate = ACKWRD;
else i = i - 1;
break;
/* When we have finished a write, we send back an ACK to the master.
* We also will drive all pins strong.
*/
case ACKWRD: {
/* We first take in the new drive value received. */
drive = data;
/* In the ACKWRD state, we drive all pins strong, once we exit, we
* lower the logic 1s to weak so that they can be read.
*/
if (i2cstate == ACKWRD) {
int cnt;
for (cnt = 0; cnt < sig.size(); cnt = cnt + 1) {
sig[cnt]->write(((drive & (1<<cnt))>0)?GN_LOGIC_1:GN_LOGIC_0);
}
}
/* Then we clear the shiftregister to begin to collect data from
* the master.
*/
data = 0;
i = 7;
i2cstate = WRDATA;
/* We also clear the interrupt. */
clearintr_ev.notify();
break;
}
/* Depending on the acknack we either return more data or not. */
case ACKNACK:
if (sda.read().ishigh()) i2cstate = IDLE;
else {
/* If we got the ACK, we then clear the registers, sample the
* I/Os and return to the read state.
*/
i2cstate = READ;
i = 7;
data = sampleport();
}
break;
/* On reads, we send the data after each bit change. Note: the driving
* is done on the other edge.
*/
case READ:
if (i == 0) i2cstate = ACKNACK;
else i = i - 1;
break;
}
/* Anytime the clock drops, we return data. We only do the data return
* to keep the FSM simpler.
*/
else if (scl.value_changed_event().triggered() && scl.read().islow())
switch (i2cstate) {
/* If we get an illegal code, we return Z. We remain here until
* we get.
*/
case RETZ: sda.write(GN_LOGIC_Z); break;
/* ACKWRD, ACKWR and ACKRD we return a 0. */
case ACKRD:
case ACKWR:
case ACKWRD:
sda.write(GN_LOGIC_0);
break;
/* For the WRITE state, all we do is release the SDA so that the
* master can write. */
case WRDATA:
/* When we enter the WRDATA, we need to weaken the driving logic 1s.
* We then scan through them and redrive any of them from 1 to W1.
* We only need to do this if it is not all 0s.
*/
if (i == 7 && drive != 0x0) {
int cnt;
for (cnt = 0; cnt < sig.size(); cnt = cnt + 1) {
if ((drive & (1<<cnt))>0) sig[cnt]->write(GN_LOGIC_W1);
}
}
break;
case ACKNACK:
/* The SDA we float. */
sda.write(GN_LOGIC_Z);
break;
/* Each bit is returned. */
case READ:
if ((data & (1 << i))>0) sda.write(GN_LOGIC_Z);
else sda.write(GN_LOGIC_0);
break;
default: ; /* For the others we do nothing. */
}
}
}
void pcf8574::trace(sc_trace_file *tf) {
sc_trace(tf, state, state.name());
}
|
//
// Copyright 2022 Sergey Khabarov, [email protected]
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
#pragma once
#include <systemc.h>
#include "../ambalib/types_amba.h"
#include "types_river.h"
#include "river_cfg.h"
namespace debugger {
SC_MODULE(ic_axi4_to_l1) {
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
// AXI4 port
sc_in<axi4_master_out_type> i_xmsto;
sc_out<axi4_master_in_type> o_xmsti;
// L1 port
sc_in<axi4_l1_in_type> i_l1i;
sc_out<axi4_l1_out_type> o_l1o;
void comb();
void registers();
SC_HAS_PROCESS(ic_axi4_to_l1);
ic_axi4_to_l1(sc_module_name name,
bool async_reset);
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
bool async_reset_;
static const uint8_t Idle = 0;
static const uint8_t ReadLineRequest = 1;
static const uint8_t WaitReadLineResponse = 2;
static const uint8_t WriteDataAccept = 3;
static const uint8_t WriteLineRequest = 4;
static const uint8_t WaitWriteConfirmResponse = 5;
static const uint8_t WaitWriteAccept = 6;
static const uint8_t WaitReadAccept = 7;
static const uint8_t CheckBurst = 8;
struct ic_axi4_to_l1_registers {
sc_signal<sc_uint<4>> state;
sc_signal<sc_uint<CFG_SYSBUS_ADDR_BITS>> req_addr;
sc_signal<sc_uint<CFG_SYSBUS_ID_BITS>> req_id;
sc_signal<sc_uint<CFG_SYSBUS_USER_BITS>> req_user;
sc_signal<sc_uint<8>> req_wstrb;
sc_signal<sc_uint<64>> req_wdata;
sc_signal<sc_uint<8>> req_len;
sc_signal<sc_uint<3>> req_size;
sc_signal<sc_uint<3>> req_prot;
sc_signal<bool> writing;
sc_signal<bool> read_modify_write;
sc_signal<sc_biguint<L1CACHE_LINE_BITS>> line_data;
sc_signal<sc_uint<L1CACHE_BYTES_PER_LINE>> line_wstrb;
sc_signal<sc_uint<64>> resp_data;
} v, r;
void ic_axi4_to_l1_r_reset(ic_axi4_to_l1_registers &iv) {
iv.state = Idle;
iv.req_addr = 0;
iv.req_id = 0;
iv.req_user = 0;
iv.req_wstrb = 0;
iv.req_wdata = 0;
iv.req_len = 0;
iv.req_size = 0;
iv.req_prot = 0;
iv.writing = 0;
iv.read_modify_write = 0;
iv.line_data = 0;
iv.line_wstrb = 0;
iv.resp_data = 0;
}
};
} // namespace debugger
|
//
// Copyright 2022 Sergey Khabarov, [email protected]
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
#pragma once
#include <systemc.h>
#include "../ambalib/types_amba.h"
#include "../ambalib/types_pnp.h"
#include "../ambalib/apb_slv.h"
#include "api_core.h"
namespace debugger {
template<int log2_fifosz = 4>
SC_MODULE(apb_uart) {
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
sc_in<mapinfo_type> i_mapinfo; // interconnect slot information
sc_out<dev_config_type> o_cfg; // Device descriptor
sc_in<apb_in_type> i_apbi; // APB Slave to Bridge interface
sc_out<apb_out_type> o_apbo; // APB Bridge to Slave interface
sc_in<bool> i_rd;
sc_out<bool> o_td;
sc_out<bool> o_irq;
void comb();
void registers();
SC_HAS_PROCESS(apb_uart);
apb_uart(sc_module_name name,
bool async_reset,
int sim_speedup_rate);
virtual ~apb_uart();
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
bool async_reset_;
int sim_speedup_rate_;
static const int fifosz = (1 << log2_fifosz);
// Rx/Tx states
static const uint8_t idle = 0;
static const uint8_t startbit = 1;
static const uint8_t data = 2;
static const uint8_t parity = 3;
static const uint8_t stopbit = 4;
struct apb_uart_registers {
sc_signal<sc_uint<32>> scaler;
sc_signal<sc_uint<32>> scaler_cnt;
sc_signal<bool> level;
sc_signal<bool> err_parity;
sc_signal<bool> err_stopbit;
sc_signal<sc_uint<32>> fwcpuid;
sc_signal<sc_uint<8>> rx_fifo[fifosz];
sc_signal<sc_uint<3>> rx_state;
sc_signal<bool> rx_ena;
sc_signal<bool> rx_ie;
sc_signal<bool> rx_ip;
sc_signal<bool> rx_nstop;
sc_signal<bool> rx_par;
sc_signal<sc_uint<log2_fifosz>> rx_wr_cnt;
sc_signal<sc_uint<log2_fifosz>> rx_rd_cnt;
sc_signal<sc_uint<log2_fifosz>> rx_byte_cnt;
sc_signal<sc_uint<log2_fifosz>> rx_irq_thresh;
sc_signal<sc_uint<4>> rx_frame_cnt;
sc_signal<bool> rx_stop_cnt;
sc_signal<sc_uint<11>> rx_shift;
sc_signal<sc_uint<8>> tx_fifo[fifosz];
sc_signal<sc_uint<3>> tx_state;
sc_signal<bool> tx_ena;
sc_signal<bool> tx_ie;
sc_signal<bool> tx_ip;
sc_signal<bool> tx_nstop;
sc_signal<bool> tx_par;
sc_signal<sc_uint<log2_fifosz>> tx_wr_cnt;
sc_signal<sc_uint<log2_fifosz>> tx_rd_cnt;
sc_signal<sc_uint<log2_fifosz>> tx_byte_cnt;
sc_signal<sc_uint<log2_fifosz>> tx_irq_thresh;
sc_signal<sc_uint<4>> tx_frame_cnt;
sc_signal<bool> tx_stop_cnt;
sc_signal<sc_uint<11>> tx_shift;
sc_signal<bool> tx_amo_guard; // AMO operation read-modify-write often hit on full flag border
sc_signal<bool> resp_valid;
sc_signal<sc_uint<32>> resp_rdata;
sc_signal<bool> resp_err;
} v, r;
sc_signal<bool> w_req_valid;
sc_signal<sc_uint<32>> wb_req_addr;
sc_signal<bool> w_req_write;
sc_signal<sc_uint<32>> wb_req_wdata;
apb_slv *pslv0;
};
template<int log2_fifosz>
apb_uart<log2_fifosz>::apb_uart(sc_module_name name,
bool async_reset,
int sim_speedup_rate)
: sc_module(name),
i_clk("i_clk"),
i_nrst("i_nrst"),
i_mapinfo("i_mapinfo"),
o_cfg("o_cfg"),
i_apbi("i_apbi"),
o_apbo("o_apbo"),
i_rd("i_rd"),
o_td("o_td"),
o_irq("o_irq") {
async_reset_ = async_reset;
sim_speedup_rate_ = sim_speedup_rate;
pslv0 = 0;
pslv0 = new apb_slv("pslv0", async_reset,
VENDOR_OPTIMITECH,
OPTIMITECH_UART);
pslv0->i_clk(i_clk);
pslv0->i_nrst(i_nrst);
pslv0->i_mapinfo(i_mapinfo);
pslv0->o_cfg(o_cfg);
pslv0->i_apbi(i_apbi);
pslv0->o_apbo(o_apbo);
pslv0->o_req_valid(w_req_valid);
pslv0->o_req_addr(wb_req_addr);
pslv0->o_req_write(w_req_write);
pslv0->o_req_wdata(wb_req_wdata);
pslv0->i_resp_valid(r.resp_valid);
pslv0->i_resp_rdata(r.resp_rdata);
pslv0->i_resp_err(r.resp_err);
SC_METHOD(comb);
sensitive << i_nrst;
sensitive << i_mapinfo;
sensitive << i_apbi;
sensitive << i_rd;
sensitive << w_req_valid;
sensitive << wb_req_addr;
sensitive << w_req_write;
sensitive << wb_req_wdata;
sensitive << r.scaler;
sensitive << r.scaler_cnt;
sensitive << r.level;
sensitive << r.err_parity;
sensitive << r.err_stopbit;
sensitive << r.fwcpuid;
for (int i = 0; i < fifosz; i++) {
sensitive << r.rx_fifo[i];
}
sensitive << r.rx_state;
sensitive << r.rx_ena;
sensitive << r.rx_ie;
sensitive << r.rx_ip;
sensitive << r.rx_nstop;
sensitive << r.rx_par;
sensitive << r.rx_wr_cnt;
sensitive << r.rx_rd_cnt;
sensitive << r.rx_byte_cnt;
sensitive << r.rx_irq_thresh;
sensitive << r.rx_frame_cnt;
sensitive << r.rx_stop_cnt;
sensitive << r.rx_shift;
for (int i = 0; i < fifosz; i++) {
sensitive << r.tx_fifo[i];
}
sensitive << r.tx_state;
sensitive << r.tx_ena;
sensitive << r.tx_ie;
sensitive << r.tx_ip;
sensitive << r.tx_nstop;
sensitive << r.tx_par;
sensitive << r.tx_wr_cnt;
sensitive << r.tx_rd_cnt;
sensitive << r.tx_byte_cnt;
sensitive << r.tx_irq_thresh;
sensitive << r.tx_frame_cnt;
sensitive << r.tx_stop_cnt;
sensitive << r.tx_shift;
sensitive << r.tx_amo_guard;
sensitive << r.resp_valid;
sensitive << r.resp_rdata;
sensitive << r.resp_err;
SC_METHOD(registers);
sensitive << i_nrst;
sensitive << i_clk.pos();
}
template<int log2_fifosz>
apb_uart<log2_fifosz>::~apb_uart() {
if (pslv0) {
delete pslv0;
}
}
template<int log2_fifosz>
void apb_uart<log2_fifosz>::generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd) {
std::string pn(name());
if (o_vcd) {
sc_trace(o_vcd, i_apbi, i_apbi.name());
sc_trace(o_vcd, o_apbo, o_apbo.name());
sc_trace(o_vcd, i_rd, i_rd.name());
sc_trace(o_vcd, o_td, o_td.name());
sc_trace(o_vcd, o_irq, o_irq.name());
sc_trace(o_vcd, r.scaler, pn + ".r_scaler");
sc_trace(o_vcd, r.scaler_cnt, pn + ".r_scaler_cnt");
sc_trace(o_vcd, r.level, pn + ".r_level");
sc_trace(o_vcd, r.err_parity, pn + ".r_err_parity");
sc_trace(o_vcd, r.err_stopbit, pn + ".r_err_stopbit");
sc_trace(o_vcd, r.fwcpuid, pn + ".r_fwcpuid");
for (int i = 0; i < fifosz; i++) {
char tstr[1024];
RISCV_sprintf(tstr, sizeof(tstr), "%s.r_rx_fifo%d", pn.c_str(), i);
sc_trace(o_vcd, r.rx_fifo[i], tstr);
}
sc_trace(o_vcd, r.rx_state, pn + ".r_rx_state");
sc_trace(o_vcd, r.rx_ena, pn + ".r_rx_ena");
sc_trace(o_vcd, r.rx_ie, pn + ".r_rx_ie");
sc_trace(o_vcd, r.rx_ip, pn + ".r_rx_ip");
sc_trace(o_vcd, r.rx_nstop, pn + ".r_rx_nstop");
sc_trace(o_vcd, r.rx_par, pn + ".r_rx_par");
sc_trace(o_vcd, r.rx_wr_cnt, pn + ".r_rx_wr_cnt");
sc_trace(o_vcd, r.rx_rd_cnt, pn + ".r_rx_rd_cnt");
sc_trace(o_vcd, r.rx_byte_cnt, pn + ".r_rx_byte_cnt");
sc_trace(o_vcd, r.rx_irq_thresh, pn + ".r_rx_irq_thresh");
sc_trace(o_vcd, r.rx_frame_cnt, pn + ".r_rx_frame_cnt");
sc_trace(o_vcd, r.rx_stop_cnt, pn + ".r_rx_stop_cnt");
sc_trace(o_vcd, r.rx_shift, pn + ".r_rx_shift");
for (int i = 0; i < fifosz; i++) {
char tstr[1024];
RISCV_sprintf(tstr, sizeof(tstr), "%s.r_tx_fifo%d", pn.c_str(), i);
sc_trace(o_vcd, r.tx_fifo[i], tstr);
}
sc_trace(o_vcd, r.tx_state, pn + ".r_tx_state");
sc_trace(o_vcd, r.tx_ena, pn + ".r_tx_ena");
sc_trace(o_vcd, r.tx_ie, pn + ".r_tx_ie");
sc_trace(o_vcd, r.tx_ip, pn + ".r_tx_ip");
sc_trace(o_vcd, r.tx_nstop, pn + ".r_tx_nstop");
sc_trace(o_vcd, r.tx_par, pn + ".r_tx_par");
sc_trace(o_vcd, r.tx_wr_cnt, pn + ".r_tx_wr_cnt");
sc_trace(o_vcd, r.tx_rd_cnt, pn + ".r_tx_rd_cnt");
sc_trace(o_vcd, r.tx_byte_cnt, pn + ".r_tx_byte_cnt");
sc_trace(o_vcd, r.tx_irq_thresh, pn + ".r_tx_irq_thresh");
sc_trace(o_vcd, r.tx_frame_cnt, pn + ".r_tx_frame_cnt");
sc_trace(o_vcd, r.tx_stop_cnt, pn + ".r_tx_stop_cnt");
sc_trace(o_vcd, r.tx_shift, pn + ".r_tx_shift");
sc_trace(o_vcd, r.tx_amo_guard, pn + ".r_tx_amo_guard");
sc_trace(o_vcd, r.resp_valid, pn + ".r_resp_valid");
sc_trace(o_vcd, r.resp_rdata, pn + ".r_resp_rdata");
sc_trace(o_vcd, r.resp_err, pn + ".r_resp_err");
}
if (pslv0) {
pslv0->generateVCD(i_vcd, o_vcd);
}
}
template<int log2_fifosz>
void apb_uart<log2_fifosz>::comb() {
sc_uint<32> vb_rdata;
sc_uint<log2_fifosz> vb_tx_wr_cnt_next;
bool v_tx_fifo_full;
bool v_tx_fifo_empty;
sc_uint<8> vb_tx_fifo_rdata;
bool v_tx_fifo_we;
sc_uint<log2_fifosz> vb_rx_wr_cnt_next;
bool v_rx_fifo_full;
bool v_rx_fifo_empty;
sc_uint<8> vb_rx_fifo_rdata;
bool v_rx_fifo_we;
bool v_rx_fifo_re;
bool v_negedge_flag;
bool v_posedge_flag;
bool par;
vb_rdata = 0;
vb_tx_wr_cnt_next = 0;
v_tx_fifo_full = 0;
v_tx_fifo_empty = 0;
vb_tx_fifo_rdata = 0;
v_tx_fifo_we = 0;
vb_rx_wr_cnt_next = 0;
v_rx_fifo_full = 0;
v_rx_fifo_empty = 0;
vb_rx_fifo_rdata = 0;
v_rx_fifo_we = 0;
v_rx_fifo_re = 0;
v_negedge_flag = 0;
v_posedge_flag = 0;
par = 0;
v.scaler = r.scaler;
v.scaler_cnt = r.scaler_cnt;
v.level = r.level;
v.err_parity = r.err_parity;
v.err_stopbit = r.err_stopbit;
v.fwcpuid = r.fwcpuid;
for (int i = 0; i < fifosz; i++) {
v.rx_fifo[i] = r.rx_fifo[i];
}
v.rx_state = r.rx_state;
v.rx_ena = r.rx_ena;
v.rx_ie = r.rx_ie;
v.rx_ip = r.rx_ip;
v.rx_nstop = r.rx_nstop;
v.rx_par = r.rx_par;
v.rx_wr_cnt = r.rx_wr_cnt;
v.rx_rd_cnt = r.rx_rd_cnt;
v.rx_byte_cnt = r.rx_byte_cnt;
v.rx_irq_thresh = r.rx_irq_thresh;
v.rx_frame_cnt = r.rx_frame_cnt;
v.rx_stop_cnt = r.rx_stop_cnt;
v.rx_shift = r.rx_shift;
for (int i = 0; i < fifosz; i++) {
v.tx_fifo[i] = r.tx_fifo[i];
}
v.tx_state = r.tx_state;
v.tx_ena = r.tx_ena;
v.tx_ie = r.tx_ie;
v.tx_ip = r.tx_ip;
v.tx_nstop = r.tx_nstop;
v.tx_par = r.tx_par;
v.tx_wr_cnt = r.tx_wr_cnt;
v.tx_rd_cnt = r.tx_rd_cnt;
v.tx_byte_cnt = r.tx_byte_cnt;
v.tx_irq_thresh = r.tx_irq_thresh;
v.tx_frame_cnt = r.tx_frame_cnt;
v.tx_stop_cnt = r.tx_stop_cnt;
v.tx_shift = r.tx_shift;
v.tx_amo_guard = r.tx_amo_guard;
v.resp_valid = r.resp_valid;
v.resp_rdata = r.resp_rdata;
v.resp_err = r.resp_err;
vb_rx_fifo_rdata = r.rx_fifo[r.rx_rd_cnt.read().to_int()];
vb_tx_fifo_rdata = r.tx_fifo[r.tx_rd_cnt.read().to_int()];
// Check FIFOs counters with thresholds:
if (r.tx_byte_cnt.read() < r.tx_irq_thresh.read()) {
v.tx_ip = r.tx_ie;
}
if (r.rx_byte_cnt.read() > r.rx_irq_thresh.read()) {
v.rx_ip = r.rx_ie;
}
// Transmitter's FIFO:
vb_tx_wr_cnt_next = (r.tx_wr_cnt.read() + 1);
if (vb_tx_wr_cnt_next == r.tx_rd_cnt.read()) {
v_tx_fifo_full = 1;
}
if (r.tx_rd_cnt.read() == r.tx_wr_cnt.read()) {
v_tx_fifo_empty = 1;
v.tx_byte_cnt = 0;
}
// Receiver's FIFO:
vb_rx_wr_cnt_next = (r.rx_wr_cnt.read() + 1);
if (vb_rx_wr_cnt_next == r.rx_rd_cnt.read()) {
v_rx_fifo_full = 1;
}
if (r.rx_rd_cnt.read() == r.rx_wr_cnt.read()) {
v_rx_fifo_empty = 1;
v.rx_byte_cnt = 0;
}
// system bus clock scaler to baudrate:
if (r.scaler.read().or_reduce() == 1) {
if (r.scaler_cnt.read() == (r.scaler.read() - 1)) {
v.scaler_cnt = 0;
v.level = (!r.level.read());
v_posedge_flag = (!r.level.read());
v_negedge_flag = r.level;
} else {
v.scaler_cnt = (r.scaler_cnt.read() + 1);
}
if (((r.rx_state.read() == idle) && (i_rd.read() == 1))
&& ((r.tx_state.read() == idle) && (v_tx_fifo_empty == 1))) {
v.scaler_cnt = 0;
v.level = 1;
}
}
// Transmitter's state machine:
if (v_posedge_flag == 1) {
switch (r.tx_state.read()) {
case idle:
if ((v_tx_fifo_empty == 0) && (r.tx_ena.read() == 1)) {
// stopbit=1,parity=xor,data[7:0],startbit=0
if (r.tx_par.read() == 1) {
par = (vb_tx_fifo_rdata[7]
^ vb_tx_fifo_rdata[6]
^ vb_tx_fifo_rdata[5]
^ vb_tx_fifo_rdata[4]
^ vb_tx_fifo_rdata[3]
^ vb_tx_fifo_rdata[2]
^ vb_tx_fifo_rdata[1]
^ vb_tx_fifo_rdata[0]);
v.tx_shift = (1, par, vb_tx_fifo_rdata, 0);
} else {
v.tx_shift = (3, vb_tx_fifo_rdata, 0);
}
v.tx_state = startbit;
v.tx_rd_cnt = (r.tx_rd_cnt.read() + 1);
v.tx_byte_cnt = (r.tx_byte_cnt.read() - 1);
v.tx_frame_cnt = 0;
} else {
v.tx_shift = ~0ull;
}
break;
case startbit:
v.tx_state = data;
break;
case data:
if (r.tx_frame_cnt.read() == 8) {
if (r.tx_par.read() == 1) {
v.tx_state = parity;
} else {
v.tx_state = stopbit;
v.tx_stop_cnt = r.tx_nstop;
}
}
break;
case parity:
v.tx_state = stopbit;
break;
case stopbit:
if (r.tx_stop_cnt.read() == 0) {
v.tx_state = idle;
v.tx_shift = ~0ull;
} else {
v.tx_stop_cnt = 0;
}
break;
default:
break;
}
if ((r.tx_state.read() != idle) && (r.tx_state.read() != stopbit)) {
v.tx_frame_cnt = (r.tx_frame_cnt.read() + 1);
v.tx_shift = (1, r.tx_shift.read()(10, 1));
}
}
// Receiver's state machine:
if (v_negedge_flag == 1) {
switch (r.rx_state.read()) {
case idle:
if ((i_rd.read() == 0) && (r.rx_ena.read() == 1)) {
v.rx_state = data;
v.rx_shift = 0;
v.rx_frame_cnt = 0;
}
break;
case data:
v.rx_shift = (i_rd.read(), r.rx_shift.read()(7, 1));
if (r.rx_frame_cnt.read() == 7) {
if (r.rx_par.read() == 1) {
v.rx_state = parity;
} else {
v.rx_state = stopbit;
v.rx_stop_cnt = r.rx_nstop;
}
} else {
v.rx_frame_cnt = (r.rx_frame_cnt.read() + 1);
}
break;
case parity:
par = (r.rx_shift.read()[7]
^ r.rx_shift.read()[6]
^ r.rx_shift.read()[5]
^ r.rx_shift.read()[4]
^ r.rx_shift.read()[3]
^ r.rx_shift.read()[2]
^ r.rx_shift.read()[1]
^ r.rx_shift.read()[0]);
if (par == i_rd.read()) {
v.err_parity = 0;
} else {
v.err_parity = 1;
}
v.rx_state = stopbit;
break;
case stopbit:
if (i_rd.read() == 0) {
v.err_stopbit = 1;
} else {
v.err_stopbit = 0;
}
if (r.rx_stop_cnt.read() == 0) {
if (v_rx_fifo_full == 0) {
v_rx_fifo_we = 1;
}
v.rx_state = idle;
} else {
v.rx_stop_cnt = 0;
}
break;
default:
break;
}
}
// Registers access:
switch (wb_req_addr.read()(11, 2)) {
case 0: // 0x00: txdata
vb_rdata[31] = v_tx_fifo_full;
if (w_req_valid.read() == 1) {
if (w_req_write.read() == 1) {
v_tx_fifo_we = ((~v_tx_fifo_full) & (~r.tx_amo_guard.read()));
} else {
v.tx_amo_guard = v_tx_fifo_full; // skip next write
}
}
break;
case 1: // 0x04: rxdata
vb_rdata[31] = v_rx_fifo_empty;
vb_rdata(7, 0) = vb_rx_fifo_rdata;
if (w_req_valid.read() == 1) {
if (w_req_write.read() == 1) {
// do nothing:
} else {
v_rx_fifo_re = (!v_rx_fifo_empty);
}
}
break;
case 2: // 0x08: txctrl
vb_rdata[0] = r.tx_ena; // [0] tx ena
vb_rdata[1] = r.tx_nstop; // [1] Number of stop bits
vb_rdata[2] = r.tx_par; // [2] parity bit enable
vb_rdata(18, 16) = r.tx_irq_thresh.read()(2, 0); // [18:16] FIFO threshold to raise irq
if ((w_req_valid.read() == 1) && (w_req_write.read() == 1)) {
v.tx_ena = wb_req_wdata.read()[0];
v.tx_nstop = wb_req_wdata.read()[1];
v.tx_par = wb_req_wdata.read()[2];
v.tx_irq_thresh = wb_req_wdata.read()(18, 16);
}
break;
case 3: // 0x0C: rxctrl
vb_rdata[0] = r.rx_ena; // [0] txena
vb_rdata[1] = r.rx_nstop; // [1] Number of stop bits
vb_rdata[2] = r.rx_par;
vb_rdata(18, 16) = r.rx_irq_thresh.read()(2, 0);
if ((w_req_valid.read() == 1) && (w_req_write.read() == 1)) {
v.rx_ena = wb_req_wdata.read()[0];
v.rx_nstop = wb_req_wdata.read()[1];
v.rx_par = wb_req_wdata.read()[2];
v.rx_irq_thresh = wb_req_wdata.read()(18, 16);
}
break;
case 4: // 0x10: ie
vb_rdata[0] = r.tx_ie;
vb_rdata[1] = r.rx_ie;
if ((w_req_valid.read() == 1) && (w_req_write.read() == 1)) {
v.tx_ie = wb_req_wdata.read()[0];
v.rx_ie = wb_req_wdata.read()[1];
}
break;
case 5: // 0x14: ip
vb_rdata[0] = r.tx_ip;
vb_rdata[1] = r.rx_ip;
if ((w_req_valid.read() == 1) && (w_req_write.read() == 1)) {
v.tx_ip = wb_req_wdata.read()[0];
v.rx_ip = wb_req_wdata.read()[1];
}
break;
case 6: // 0x18: |
scaler
vb_rdata = r.scaler;
if ((w_req_valid.read() == 1) && (w_req_write.read() == 1)) {
v.scaler = wb_req_wdata.read()(30, sim_speedup_rate_);
v.scaler_cnt = 0;
}
break;
case 7: // 0x1C: fwcpuid
vb_rdata = r.fwcpuid;
if ((w_req_valid.read() == 1) && (w_req_write.read() == 1)) {
if ((r.fwcpuid.read().or_reduce() == 0) || (wb_req_wdata.read().or_reduce() == 0)) {
v.fwcpuid = wb_req_wdata;
}
}
break;
default:
break;
}
if (v_rx_fifo_we == 1) {
v.rx_wr_cnt = (r.rx_wr_cnt.read() + 1);
v.rx_byte_cnt = (r.rx_byte_cnt.read() + 1);
v.rx_fifo[r.rx_wr_cnt.read().to_int()] = r.rx_shift.read()(7, 0);
} else if (v_rx_fifo_re == 1) {
v.rx_rd_cnt = (r.rx_rd_cnt.read() + 1);
v.rx_byte_cnt = (r.rx_byte_cnt.read() - 1);
}
if (v_tx_fifo_we == 1) {
v.tx_wr_cnt = (r.tx_wr_cnt.read() + 1);
v.tx_byte_cnt = (r.tx_byte_cnt.read() + 1);
v.tx_fifo[r.tx_wr_cnt.read().to_int()] = wb_req_wdata.read()(7, 0);
}
v.resp_valid = w_req_valid;
v.resp_rdata = vb_rdata;
v.resp_err = 0;
if (!async_reset_ && i_nrst.read() == 0) {
v.scaler = 0;
v.scaler_cnt = 0;
v.level = 1;
v.err_parity = 0;
v.err_stopbit = 0;
v.fwcpuid = 0;
for (int i = 0; i < fifosz; i++) {
v.rx_fifo[i] = 0;
}
v.rx_state = idle;
v.rx_ena = 0;
v.rx_ie = 0;
v.rx_ip = 0;
v.rx_nstop = 0;
v.rx_par = 0;
v.rx_wr_cnt = 0;
v.rx_rd_cnt = 0;
v.rx_byte_cnt = 0;
v.rx_irq_thresh = 0;
v.rx_frame_cnt = 0;
v.rx_stop_cnt = 0;
v.rx_shift = 0;
for (int i = 0; i < fifosz; i++) {
v.tx_fifo[i] = 0;
}
v.tx_state = idle;
v.tx_ena = 0;
v.tx_ie = 0;
v.tx_ip = 0;
v.tx_nstop = 0;
v.tx_par = 0;
v.tx_wr_cnt = 0;
v.tx_rd_cnt = 0;
v.tx_byte_cnt = 0;
v.tx_irq_thresh = 0;
v.tx_frame_cnt = 0;
v.tx_stop_cnt = 0;
v.tx_shift = ~0ull;
v.tx_amo_guard = 0;
v.resp_valid = 0;
v.resp_rdata = 0;
v.resp_err = 0;
}
o_td = r.tx_shift.read()[0];
o_irq = (r.tx_ip.read() | r.rx_ip.read());
}
template<int log2_fifosz>
void apb_uart<log2_fifosz>::registers() {
if (async_reset_ && i_nrst.read() == 0) {
r.scaler = 0;
r.scaler_cnt = 0;
r.level = 1;
r.err_parity = 0;
r.err_stopbit = 0;
r.fwcpuid = 0;
for (int i = 0; i < fifosz; i++) {
r.rx_fifo[i] = 0;
}
r.rx_state = idle;
r.rx_ena = 0;
r.rx_ie = 0;
r.rx_ip = 0;
r.rx_nstop = 0;
r.rx_par = 0;
r.rx_wr_cnt = 0;
r.rx_rd_cnt = 0;
r.rx_byte_cnt = 0;
r.rx_irq_thresh = 0;
r.rx_frame_cnt = 0;
r.rx_stop_cnt = 0;
r.rx_shift = 0;
for (int i = 0; i < fifosz; i++) {
r.tx_fifo[i] = 0;
}
r.tx_state = idle;
r.tx_ena = 0;
r.tx_ie = 0;
r.tx_ip = 0;
r.tx_nstop = 0;
r.tx_par = 0;
r.tx_wr_cnt = 0;
r.tx_rd_cnt = 0;
r.tx_byte_cnt = 0;
r.tx_irq_thresh = 0;
r.tx_frame_cnt = 0;
r.tx_stop_cnt = 0;
r.tx_shift = ~0ull;
r.tx_amo_guard = 0;
r.resp_valid = 0;
r.resp_rdata = 0;
r.resp_err = 0;
} else {
r.scaler = v.scaler;
r.scaler_cnt = v.scaler_cnt;
r.level = v.level;
r.err_parity = v.err_parity;
r.err_stopbit = v.err_stopbit;
r.fwcpuid = v.fwcpuid;
for (int i = 0; i < fifosz; i++) {
r.rx_fifo[i] = v.rx_fifo[i];
}
r.rx_state = v.rx_state;
r.rx_ena = v.rx_ena;
r.rx_ie = v.rx_ie;
r.rx_ip = v.rx_ip;
r.rx_nstop = v.rx_nstop;
r.rx_par = v.rx_par;
r.rx_wr_cnt = v.rx_wr_cnt;
r.rx_rd_cnt = v.rx_rd_cnt;
r.rx_byte_cnt = v.rx_byte_cnt;
r.rx_irq_thresh = v.rx_irq_thresh;
r.rx_frame_cnt = v.rx_frame_cnt;
r.rx_stop_cnt = v.rx_stop_cnt;
r.rx_shift = v.rx_shift;
for (int i = 0; i < fifosz; i++) {
r.tx_fifo[i] = v.tx_fifo[i];
}
r.tx_state = v.tx_state;
r.tx_ena = v.tx_ena;
r.tx_ie = v.tx_ie;
r.tx_ip = v.tx_ip;
r.tx_nstop = v.tx_nstop;
r.tx_par = v.tx_par;
r.tx_wr_cnt = v.tx_wr_cnt;
r.tx_rd_cnt = v.tx_rd_cnt;
r.tx_byte_cnt = v.tx_byte_cnt;
r.tx_irq_thresh = v.tx_irq_thresh;
r.tx_frame_cnt = v.tx_frame_cnt;
r.tx_stop_cnt = v.tx_stop_cnt;
r.tx_shift = v.tx_shift;
r.tx_amo_guard = v.tx_amo_guard;
r.resp_valid = v.resp_valid;
r.resp_rdata = v.resp_rdata;
r.resp_err = v.resp_err;
}
}
} // namespace debugger
|
/* Copyright 2017 Columbia University, SLD Group */
//
// execute.h - Robert Margelli
// execute stage header file.
//
// Division algorithm for DIV, DIVU, REM, REMU instructions. Division by zero
// and overflow semantics are compliant with the RISC-V specs (page 32).
//
#include <systemc.h>
#include "cynw_flex_channels.h"
#include "defines.hpp"
#include "globals.hpp"
#include "hl5_datatypes.hpp"
#include "syn_directives.hpp"
#ifndef __EXECUTE__H
#define __EXECUTE__H
#define BIT(_N) (1 << _N)
// Signed division quotient and remainder struct.
struct div_res_t{
sc_int<XLEN> quotient;
sc_int<XLEN> remainder;
};
// Unsigned division quotient and remainder struct.
struct u_div_res_t{
sc_uint<XLEN> quotient;
sc_uint<XLEN> remainder;
};
SC_MODULE(execute)
{
// FlexChannel initiators
get_initiator< de_out_t > din;
put_initiator< exe_out_t > dout;
// Forward
sc_out< reg_forward_t > fwd_exe;
// Clock and reset signals
sc_in_clk clk;
sc_in<bool> rst;
// Thread prototype
void execute_th(void);
void perf_th(void);
// Support functions
sc_bv<XLEN> sign_extend_imm_s(sc_bv<12> imm); // Sign extend the S-type immediate field.
sc_bv<XLEN> zero_ext_zimm(sc_bv<ZIMM_SIZE> zimm); // Zero extend the zimm field for CSRRxI instructions.
sc_uint<CSR_IDX_LEN> get_csr_index(sc_bv<CSR_ADDR> csr_addr); // Get csr index given the 12-bit CSR address.
void set_csr_value(sc_uint<CSR_IDX_LEN> csr_index, sc_bv<XLEN> rs1, sc_uint<LOG2_CSR_OP_NUM> operation, sc_bv<2> rw_permission); // Perform requested CSR operation (write/set/clear).
// Divider functions
u_div_res_t udiv_func(sc_uint<XLEN> num, sc_uint<XLEN> den);
div_res_t div_func(sc_int<XLEN> num, sc_int<XLEN> den);
// Constructor
SC_CTOR(execute)
: din("din")
, dout("dout")
, fwd_exe("fwd_exe")
, clk("clk")
, rst("rst")
{
SC_CTHREAD(execute_th, clk.pos());
reset_signal_is(rst, false);
SC_CTHREAD(perf_th, clk.pos());
reset_signal_is(rst, false);
din.clk_rst(clk, rst);
dout.clk_rst(clk, rst);
HLS_FLATTEN_ARRAY(csr);
}
// Member variables
de_out_t input;
exe_out_t output;
sc_uint<XLEN> csr[CSR_NUM]; // Control and status registers.
};
#endif
|
/*
' * execute.h
*
* Created on: 4 de mai de 2017
* Author: drcfts
*/
#include <systemc.h>
#include "breg_if.h"
#include "mem_if.h"
#include "shared.h"
SC_MODULE(execute){
sc_port <mem_if> p_mem;
sc_port <breg_if> p_breg;
sc_fifo_in < contexto* > decode_execute;
sc_fifo_out < contexto*> execute_fetch;
void execute_method(){
while(true){
recebimento = decode_execute.read();
escrita = recebimento;
e_rs2 = recebimento->rs2;
e_rs1 = recebimento-> rs1;
e_rd = recebimento->rd;
e_op = recebimento-> opcode;
e_funct7 = recebimento->funct7;
e_funct3 = recebimento->funct3;
e_imm_I = recebimento->Imm_I;
e_imm_U = recebimento->Imm_U;
e_imm_J = recebimento->Imm_J;
e_imm_B = recebimento->Imm_B;
e_shamt = recebimento->shamt;
// switch
//Caso R:
// Caso Funct 3:
// Caso Funct 7:
//Caso I:
// Caso Funct 3:
// Caso Func 7:
//Caso B:
// Caso Funct 3:
//Caso S/ADDI...:
// Caso Funct 3:
switch(e_op){
case TIPO_LUI:
// operacao lui
//20 MSB pro reg, 12 LSB = 0
p_breg->write(e_rd, (e_imm_U<<20) & 0xFFFFF000);
break;
case TIPO_AUIPC:
// operacao AUIPC
//PC = reg(31)
_t1 = ((e_imm_U<<20) & 0xFFFFF000) +
p_breg->read(31);
//Adiciona offset e escreve no PC e no Rd
p_breg->write(31, _t1);
p_breg->write(e_rd, _t1);
break;
case TIPO_JAL:
// operacao JAL
p_breg->write(e_rd, p_breg->read(31));
p_breg->write(31, e_imm_J);
break;
case TIPO_JALR:
// operacao JALR
if(e_funct3 == 0x0){
// operacao JALR
_t1 = e_imm_I + p_breg->read(e_rs1);
//Seta BIT0 como 0
_t1 = _t1 & 0xFFFFFFFE;
p_breg->write(e_rd, p_breg->read(31));
p_breg->write(31, _t1);
}
break;
case TIPO_B:
// branches -> tipo B
switch(e_funct3){
case f3_BEQ:
// funcao beq
if (p_breg->read(e_rs1) == p_breg->read(e_rs2)) {
_t1 = e_imm_B << 1;
_t1 += p_breg->read(31);
p_breg->write(31, _t1);
}
break;
case f3_BNE:
// funcao bne
if (p_breg->read(e_rs1) != p_breg->read(e_rs2)) {
_t1 = e_imm_B << 1;
_t1 += p_breg->read(31);
p_breg->write(31, _t1);
}
break;
case f3_BLT:
// funcao bLT
if (p_breg->read(e_rs1) < p_breg->read(e_rs2)) {
_t1 = e_imm_B << 1;
_t1 += p_breg->read(31);
p_breg->write(31, _t1);
}
break;
case f3_BGE:
// funcao bGe
if (p_breg->read(e_rs1) >= p_breg->read(e_rs2)) {
_t1 = e_imm_B << 1;
_t1 += p_breg->read(31);
p_breg->write(31, _t1);
}
break;
case f3_BLTU:
// funcao bLTU
if ((unsigned)p_breg->read(e_rs1) < (unsigned)p_breg->read(e_rs2)) {
_t1 = e_imm_B << 1;
_t1 += p_breg->read(31);
p_breg->write(31, _t1);
}
break;
case f3_BGEU:
// funcao bGeU
if ((unsigned)p_breg->read(e_rs1) >= (unsigned)p_breg->read(e_rs2)) {
_t1 = e_imm_B << 1;
_t1 += p_breg->read(31);
p_breg->write(31, _t1);
}
break;
default:
break;
}// fim SWITCHh funct3 - Branch
break;
case TIPO_I_REST0 :
// operacoes loads
switch(e_funct3){
case f3_LB:
// load byte
p_breg->write(e_rd, p_mem->lb(p_breg->read(e_rs1), e_imm_S));
break;
case f3_LH:
// load half
p_breg->write(e_rd, p_mem->lh(p_breg->read(e_rs1), e_imm_S));
break;
case f3_LW:
// load word
p_breg->write(e_rd, p_mem->lw(p_breg->read(e_rs1), e_imm_S));
break;
case f3_LBU:
// load byte unsigned
p_breg->write(e_rd, p_mem->lbu(p_breg->read(e_rs1), e_imm_S));
break;
case f3_LHU:
// load half unsigned
p_breg->write(e_rd, p_mem->lhu(p_breg->read(e_rs1), e_imm_S));
break;
// default?
} // fim switch funct3 - loads
break;
case TIPO_S:
// funcoes do tipo store
switch(e_funct3){
case f3_SB:
// store byte
p_mem->sb((p_breg->read(e_rs1)), e_imm_S, p_breg->read(e_rs2));
break;
case f3_SH:
// store half
p_mem->sh((p_breg->read(e_rs1)), e_imm_S, p_breg->read(e_rs2));
break;
case f3_SW:
// store word
p_mem->sw((p_breg->read(e_rs1)), e_imm_S, p_breg->read(e_rs2));
break;
// default?
} // fim switch funct3 - STORE
break;
case TIPO_I2_SHAMT:
// tipos i e shifts
switch(e_funct3){
case f3_ADDI:
//Se for NOP
if(!e_rs1 && !e_rd && !e_imm_I){
break;
}
// addi
_t1 = e_imm_I + p_breg->read(e_rs1);
p_breg->write(e_rd, _t1);
break;
case f3_SLTI:
// slti
if(p_breg->read(e_rs1) < e_imm_I){
p_breg->write(e_rd, 1);
}
else{
p_breg->write(e_rd, 0);
}
break;
case f3_SLTIU:
// sltiu
//Primeiro faz extensao de sinal p/ 32 bits,
//dps trata os dois como sem sinal
_t1 = e_imm_I;
if((unsigned)p_breg->read(e_rs1) < (unsigned)_t1){
p_breg->write(e_rd, 1);
}
else{
p_breg->write(e_rd, 0);
}
break;
case f3_XORI:
// XORI
_t1 = e_imm_I ^ p_breg->read(e_rs1);
p_breg->write(e_rd, _t1);
break;
case f3_ORI:
// ORI
_t1 = e_imm_I | p_breg->read(e_rs1);
p_breg->write(e_rd, _t1);
break;
case f3_ANDI:
// ANDI
_t1 = e_imm_I & p_breg->read(e_rs1);
p_breg->write(e_rd, _t1);
break;
case f3_SRLI_SRAI:
// srli ou srai
if(e_funct7 == f7_SRAI){
// srai
p_breg->write(e_rd, (p_breg->read(e_rs1)) >> e_shamt);
}
if(e_funct7 == f7_RESTO_I){
// SRLI
_t1 = (unsigned)(p_breg->read(e_rs1)) >> e_shamt;
p_breg->write(e_rd, _t1);
}
break;
case f3_SLLI:
// SLLI
if(e_funct7 == f7_RESTO_I ){
// SLLI
p_breg->write(e_rd, (p_breg->read(e_rs1))<< e_shamt);
}
break;
case TIPO_R:
switch(e_funct7){
case f7_RESTO:
switch(e_funct3){
case f3_ADD_SUB:
// add
p_breg->write(e_rd, (p_breg->read(e_rs1)+ p_breg->read(e_rs2)));
break;
case f3_SLL:
// Sll
//Shamt = 5 LSB do registrador RS2
p_breg->write(e_rd, (p_breg->read(e_rs1))<< (p_breg->read(e_rs2) & 0x1F));
break;
case f3_SLT:
// SlT
p_breg->write(e_rd, (p_breg->read(e_rs1)< p_breg->read(e_rs2)));
break;
case f3_SLTU:
// SLT unsigned
p_breg->write(e_rd, ((unsigned)p_breg->read(e_rs1)<(unsigned)p_breg->read(e_rs2)));
break;
case f3_XOR:
// xor
p_breg->write(e_rd, (p_breg->read(e_rs1) ^ p_breg->read(e_rs2)));
break;
case f3_SRL_SRA:
// SRL
_t1 = (unsigned)(p_breg->read(e_rs1)) >> (p_breg->read(e_rs2) & 0x1F);
p_breg->write(e_rd, _t1);
break;
case f3_OR:
// or
p_breg->write(e_rd, (p_breg->read(e_rs1) | p_breg->read(e_rs2)));
break;
case f3_AND:
// and
p_breg->write(e_rd, (p_breg->read(e_rs1) & p_breg->read(e_rs2)));
break;
} // fim funct 3 -> f7 resto
break;
case f7_SRA_SUB:
switch(e_funct3){
case f3_ADD_SUB:
// sub
p_breg->write(e_rd, (p_breg->read(e_rs1) - p_breg->read(e_rs2)));
break;
case f3_SRL_SRA:
// SRA
p_breg->write(e_rd, (p_breg->read(e_rs1)) >> (p_breg->read(e_rs2) & 0x1F));
break;
}// fim funct 3 -> f7 SRA_SUB
break;
}// fim switch funct 7
break;
}// fim switch funct3 - imediato
}// FIM SWITCH
//p_breg->write(0, 0);
execute_fetch.write(escrita);
} //while
} // execute_method()
SC_CTOR(execute){
recebimento = new contexto();
escrita = new contexto();
SC_THREAD(execute_method);
}
private:
contexto *recebimento, *escrita;
unsigned short e_rs1, e_rs2, e_rd, e_op,e_funct3,e_funct7,e_shamt;
int32_t e_imm_I,e_imm_U,e_imm_S,e_imm_B,e_imm_J;
int32_t _t1;
};
/*
switch (e_op) {
case i_ADD: p_breg->write(e_rd, (p_breg->read(e_rs)+ p_breg->read(e_rt)));
break;
case i_SUB: p_breg->write(e_rd, (p_breg->read(e_rs)- p_breg->read(e_rt)));
break;
case i_AND: p_breg->write(e_rd, (p_breg->read(e_rs)& p_breg->read(e_rt)));
break;
case i_OR : p_breg->write(e_rd, (p_breg->read(e_rs)| p_breg->read(e_rt)));
break;
case i_XOR: p_breg->write(e_rd, (p_breg->read(e_rs)^ p_breg->read(e_rt)));
break;
case i_NOT: p_breg->write(e_rs, ~(p_breg->read(e_rs)));
break;
//case i_NOT: breg[rd] = ~breg[rs]; break;
case i_ADDi: p_breg->write(e_rs, (p_breg->read(e_rs)+ e_k8));
break;
case i_SHIFT:
if (e_k8 < 0) p_breg->write(e_rs, (p_breg->read(e_rs))<< (-e_k8));
else p_breg->write(e_rs, (p_breg->read(e_rs)) >> (e_k8));
break;
case i_SLT: p_breg->write(e_rd, (p_breg->read(e_rs)<p_breg->read(e_rt)));
break;
case i_LW: p_breg->write(e_rd, p_mem->lw(p_breg->read(e_rs) + p_breg->read(e_rt), 0));
break;
case i_SW: p_mem->sw((p_breg->read(e_rs)+p_breg->read(e_rt)), 0, p_breg->read(e_rd));
break;
case i_LUI: p_breg->write(e_rs, e_k8<<8);
break;
case i_BEQ: if (p_breg->read(e_rs) == p_breg->read(e_rt)) recebimento->pc = recebimento->pc + e_k4;
break;
case i_BNE: if (p_breg->read(e_rs) != p_breg->read(e_rt)) recebimento->pc = recebimento->pc + e_k4;
break;
case i_J: recebimento->pc = p_breg->read(e_rs) + e_k8;
break;
case i_JAL: p_breg->write(15, recebimento->pc);
recebimento->pc = p_breg->read(e_rs) + e_k8;
break;
} // switch
*/
|
/*****************************************************************************
Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
more contributor license agreements. See the NOTICE file distributed
with this work for additional information regarding copyright ownership.
Accellera licenses this file to you under the Apache License, Version 2.0
(the "License"); you may not use this file except in compliance with the
License. You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
implied. See the License for the specific language governing
permissions and limitations under the License.
*****************************************************************************/
/*****************************************************************************
simple_bus_master_direct.h : The monitor (master) using the direct BUS
interface.
Original Author: Ric Hilderink, Synopsys, Inc., 2001-10-11
*****************************************************************************/
/*****************************************************************************
MODIFICATION LOG - modifiers, enter your name, affiliation, date and
changes you are making here.
Name, Affiliation, Date:
Description of Modification:
*****************************************************************************/
#ifndef __simple_bus_master_direct_h
#define __simple_bus_master_direct_h
#include <systemc.h>
#include "simple_bus_direct_if.h"
SC_MODULE(simple_bus_master_direct)
{
// ports
sc_in_clk clock;
sc_port<simple_bus_direct_if> bus_port;
// constructor
simple_bus_master_direct(sc_module_name name_
, unsigned int address
, int timeout
, bool verbose = true)
: sc_module(name_)
, m_address(address)
, m_timeout(timeout)
, m_verbose(verbose)
{
// process declaration
SC_THREAD(main_action);
}
// process
void main_action();
private:
unsigned int m_address;
int m_timeout;
bool m_verbose;
}; // end class simple_bus_master_direct
#endif
|
/**
* @license MIT
* @brief Print stuff for types and structs.
*/
#ifndef HUFFMAN_CODING_PRINT_H
#define HUFFMAN_CODING_PRINT_H
///////////////////////////////////////////////////////////////////////////////
#include <ostream>
#include <vector>
#include <deque>
#include <systemc.h>
///////////////////////////////////////////////////////////////////////////////
namespace huffman_coding {
class binary_ostream {
public:
explicit binary_ostream(std::ostream& os)
: _os(os) {}
template<typename T>
binary_ostream& operator<<(const T& x) {
_os << x;
return *this;
}
binary_ostream& operator<<(std::ostream& (*pf)(std::ostream&)) {
pf(_os);
return *this;
}
template<int W>
binary_ostream& operator<<(const sc_uint<W>& x) {
this->print(x);
return *this;
}
private:
std::ostream& _os;
void print(const sc_uint_base&);
};
template<typename T>
binary_ostream& operator<<(binary_ostream& bos, std::vector<T> v) {
auto iter = v.begin();
auto last = v.end() - 1;
for(; iter != last; iter++){
bos << *iter << std::endl;
}
bos << *last;
return bos;
}
template<typename T>
binary_ostream& operator<<(binary_ostream& bos, std::deque<T> v) {
auto iter = v.begin();
auto last = v.end() - 1;
for(; iter != last; iter++){
bos << *iter << std::endl;
}
bos << *last;
return bos;
}
}
///////////////////////////////////////////////////////////////////////////////
#endif // HUFFMAN_CODING_STRUCTS_H
|
// Copyright 1991-2014 Mentor Graphics Corporation
// All Rights Reserved.
// THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
// WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION
// OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
#ifndef INCLUDED_CONTROL
#define INCLUDED_CONTROL
#include <systemc.h>
class control : public sc_module
{
public:
sc_in<bool> clock;
sc_in<bool> reset;
sc_out<sc_uint<9> > ramadrs;
sc_out<bool> oeenable;
sc_out<bool> txc;
sc_out<bool> outstrobe;
// Class methods
void incrementer();
void enable_gen();
void outstrobe_gen();
// Constructor
SC_CTOR(control)
: clock("clock"),
reset("reset"),
ramadrs("ramadrs"),
oeenable("oeenable"),
txc("txc"),
outstrobe("outstrobe")
{
SC_METHOD(incrementer);
sensitive << clock.pos();
dont_initialize();
SC_METHOD(enable_gen);
sensitive << clock.pos();
dont_initialize();
SC_METHOD(outstrobe_gen);
sensitive << ramadrs;
dont_initialize();
}
// Empty Destructor
~control()
{
}
};
//
// This process increments the ram address.
//
inline void control::incrementer()
{
if (reset.read() == 0)
ramadrs.write(0);
else
ramadrs.write(ramadrs.read() + 1);
}
//
// This process generates the output enable signal.
//
inline void control::enable_gen()
{
if (reset.read() == 0)
oeenable.write(0);
else
{
if (ramadrs.read().range(4, 0) == 0)
oeenable.write(1);
else
oeenable.write(0);
}
}
//
// This process generates the outstrobe and the txc data line.
//
inline void control::outstrobe_gen()
{
bool x = 1;
for (int i = 4; i < 9; i++)
x &= (bool)ramadrs.read()[i];
outstrobe.write(x);
txc.write((bool)ramadrs.read()[4]);
}
#endif
|
//
// Copyright 2022 Sergey Khabarov, [email protected]
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
#pragma once
#include <systemc.h>
#include "../river_cfg.h"
namespace debugger {
SC_MODULE(ic_csr_m2_s1) {
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
// master[0]:
sc_in<bool> i_m0_req_valid;
sc_out<bool> o_m0_req_ready;
sc_in<sc_uint<CsrReq_TotalBits>> i_m0_req_type;
sc_in<sc_uint<12>> i_m0_req_addr;
sc_in<sc_uint<RISCV_ARCH>> i_m0_req_data;
sc_out<bool> o_m0_resp_valid;
sc_in<bool> i_m0_resp_ready;
sc_out<sc_uint<RISCV_ARCH>> o_m0_resp_data;
sc_out<bool> o_m0_resp_exception;
// master[1]
sc_in<bool> i_m1_req_valid;
sc_out<bool> o_m1_req_ready;
sc_in<sc_uint<CsrReq_TotalBits>> i_m1_req_type;
sc_in<sc_uint<12>> i_m1_req_addr;
sc_in<sc_uint<RISCV_ARCH>> i_m1_req_data;
sc_out<bool> o_m1_resp_valid;
sc_in<bool> i_m1_resp_ready;
sc_out<sc_uint<RISCV_ARCH>> o_m1_resp_data;
sc_out<bool> o_m1_resp_exception;
// slave[0]
sc_out<bool> o_s0_req_valid;
sc_in<bool> i_s0_req_ready;
sc_out<sc_uint<CsrReq_TotalBits>> o_s0_req_type;
sc_out<sc_uint<12>> o_s0_req_addr;
sc_out<sc_uint<RISCV_ARCH>> o_s0_req_data;
sc_in<bool> i_s0_resp_valid;
sc_out<bool> o_s0_resp_ready;
sc_in<sc_uint<RISCV_ARCH>> i_s0_resp_data;
sc_in<bool> i_s0_resp_exception;
void comb();
void registers();
SC_HAS_PROCESS(ic_csr_m2_s1);
ic_csr_m2_s1(sc_module_name name,
bool async_reset);
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
bool async_reset_;
struct ic_csr_m2_s1_registers {
sc_signal<bool> midx;
sc_signal<bool> acquired;
} v, r;
void ic_csr_m2_s1_r_reset(ic_csr_m2_s1_registers &iv) {
iv.midx = 0;
iv.acquired = 0;
}
};
} // namespace debugger
|
// Copyright (c) 2011-2024 Columbia University, System Level Design Group
// SPDX-License-Identifier: MIT
#ifndef __ESP_SYSTEMC_HPP__
#define __ESP_SYSTEMC_HPP__
// Fixed point
#if defined(SC_FIXED_POINT) || defined(SC_FIXED_POINT_FAST)
// Using SystemC fixed point
#define SC_INCLUDE_FX
#include <systemc.h>
#else
// Using cynw fixed point (default)
#include <systemc.h>
#include <cynw_fixed.h>
#endif
// Channels
#ifdef __CARGO__
// Using CARGO flex channels
#include <flex_channels.hpp>
#else
// Using cynw flex channels (default)
#include <cynw_flex_channels.h>
#endif
#endif // __ESP_SYSTEMC_HPP__
|
/****************************************************************************
*
* Copyright (c) 2017, Cadence Design Systems. All Rights Reserved.
*
* This file contains confidential information that may not be
* distributed under any circumstances without the written permision
* of Cadence Design Systems.
*
****************************************************************************/
#ifndef _DUT_SC_FOREIGN_INCLUDED_
#define _DUT_SC_FOREIGN_INCLUDED_
#include <systemc.h>
// Declaration of wrapper with RTL level ports
struct dut : public ncsc_foreign_module
{
public:
sc_in< bool > clk;
sc_in< bool > rst;
sc_out< bool > din_busy;
sc_in< bool > din_vld;
sc_in< sc_uint< 8 > > din_data;
sc_in< bool > dout_busy;
sc_out< bool > dout_vld;
sc_out< sc_uint< 11 > > dout_data;
const char* hdl_name() const { return "dut"; }
dut( sc_module_name name )
: ncsc_foreign_module(name)
,clk("clk")
,rst("rst")
,din_busy("din_busy")
,din_vld("din_vld")
,din_data("din_data")
,dout_busy("dout_busy")
,dout_vld("dout_vld")
,dout_data("dout_data")
{
}
};
#endif /* _DUT_SC_FOREIGN_INCLUDED_ */
|
#include<systemc.h>
#include<string>
#include<vector>
#include<map>
#include<fstream>
#include<nana/gui.hpp>
#include<nana/gui/widgets/button.hpp>
#include<nana/gui/widgets/menubar.hpp>
#include<nana/gui/widgets/group.hpp>
#include<nana/gui/widgets/textbox.hpp>
#include<nana/gui/filebox.hpp>
#include "top.hpp"
#include "gui.hpp"
using std::string;
using std::vector;
using std::map;
using std::fstream;
int sc_main(int argc, char *argv[])
{
using namespace nana;
vector<string> instruction_queue;
string bench_name = "";
int nadd,nmul,nls, n_bits, bpb_size, cpu_freq;
nadd = 3;
nmul = nls = 2;
n_bits = 2;
bpb_size = 4;
cpu_freq = 500; // definido em Mhz - 500Mhz default
std::vector<int> sizes;
bool spec = false;
int mode = 0;
bool fila = false;
ifstream inFile;
form fm(API::make_center(1024,700));
place plc(fm);
place upper(fm);
place lower(fm);
listbox table(fm);
listbox reg(fm);
listbox instruct(fm);
listbox rob(fm);
menubar mnbar(fm);
button start(fm);
button run_all(fm);
button clock_control(fm);
button exit(fm);
group clock_group(fm);
label clock_count(clock_group);
fm.caption("TFSim");
clock_group.caption("Ciclo");
clock_group.div("count");
grid memory(fm,rectangle(),10,50);
// Tempo de latencia de uma instrucao
// Novas instrucoes devem ser inseridas manualmente aqui
map<string,int> instruct_time{{"DADD",4},{"DADDI",4},{"DSUB",6},
{"DSUBI",6},{"DMUL",10},{"DDIV",16},{"MEM",2},
{"SLT",1},{"SGT", 1}};
// Responsavel pelos modos de execução
top top1("top");
start.caption("Start");
clock_control.caption("Next cycle");
run_all.caption("Run all");
exit.caption("Exit");
plc["rst"] << table;
plc["btns"] << start << clock_control << run_all << exit;
plc["memor"] << memory;
plc["regs"] << reg;
plc["rob"] << rob;
plc["instr"] << instruct;
plc["clk_c"] << clock_group;
clock_group["count"] << clock_count;
clock_group.collocate();
spec = false;
//set_spec eh so visual
set_spec(plc,spec);
plc.collocate();
mnbar.push_back("Opções");
menu &op = mnbar.at(0);
//menu::item_proxy spec_ip =
op.append("Especulação");
auto spec_sub = op.create_sub_menu(0);
// Modo com 1 preditor para todos os branchs
spec_sub->append("1 Preditor", [&](menu::item_proxy &ip)
{
if(ip.checked()){
spec = true;
mode = 1;
spec_sub->checked(1, false);
}
else{
spec = false;
mode = 0;
}
set_spec(plc,spec);
});
// Modo com o bpb
spec_sub->append("Branch Prediction Buffer", [&](menu::item_proxy &ip)
{
if(ip.checked()){
spec = true;
mode = 2;
spec_sub->checked(0, false);
}
else{
spec = false;
mode = 0;
}
set_spec(plc, spec);
});
spec_sub->check_style(0,menu::checks::highlight);
spec_sub->check_style(1,menu::checks::highlight);
op.append("Modificar valores...");
// novo submenu para escolha do tamanho do bpb e do preditor
auto sub = op.create_sub_menu(1);
sub->append("Tamanho do BPB e Preditor", [&](menu::item_proxy &ip)
{
inputbox ibox(fm, "", "Definir tamanhos");
inputbox::integer size("BPB", bpb_size, 2, 10, 2);
inputbox::integer bits("N_BITS", n_bits, 1, 3, 1);
if(ibox.show_modal(size, bits)){
bpb_size = size.value();
n_bits = bits.value();
}
});
sub->append("Número de Estações de Reserva",[&](menu::item_proxy ip)
{
inputbox ibox(fm,"","Quantidade de Estações de Reserva");
inputbox::integer add("ADD/SUB",nadd,1,10,1);
inputbox::integer mul("MUL/DIV",nmul,1,10,1);
inputbox::integer sl("LOAD/STORE",nls,1,10,1);
if(ibox.show_modal(add,mul,sl))
{
nadd = add.value();
nmul = mul.value();
nls = sl.value();
}
});
// Menu de ajuste dos tempos de latencia na interface
// Novas instrucoes devem ser adcionadas manualmente aqui
sub->append("Tempos de latência", [&](menu::item_proxy &ip)
{
inputbox ibox(fm,"","Tempos de latência para instruções");
inputbox::text dadd_t("DADD",std::to_string(instruct_time["DADD"]));
inputbox::text daddi_t("DADDI",std::to_string(instruct_time["DADDI"]));
inputbox::text dsub_t("DSUB",std::to_string(instruct_time["DSUB"]));
inputbox::text dsubi_t("DSUBI",std::to_string(instruct_time["DSUBI"]));
inputbox::text dmul_t("DMUL",std::to_string(instruct_time["DMUL"]));
inputbox::text ddiv_t("DDIV",std::to_string(instruct_time["DDIV"]));
inputbox::text mem_t("Load/Store",std::to_string(instruct_time["MEM"]));
if(ibox.show_modal(dadd_t,daddi_t,dsub_t,dsubi_t,dmul_t,ddiv_t,mem_t))
{
instruct_time["DADD"] = std::stoi(dadd_t.value());
instruct_time["DADDI"] = std::stoi(daddi_t.value());
instruct_time["DSUB"] = std::stoi(dsub_t.value());
instruct_time["DSUBI"] = std::stoi(dsubi_t.value());
instruct_time["DMUL"] = std::stoi(dmul_t.value());
instruct_time["DDIV"] = std::stoi(ddiv_t.value());
instruct_time["MEM"] = std::stoi(mem_t.value());
}
});
sub->append("Frequência CPU", [&](menu::item_proxy &ip)
{
inputbox ibox(fm,"Em Mhz","Definir frequência da CPU");
inputbox::text freq("Frequência", std::to_string(cpu_freq));
if(ibox.show_modal(freq)){
cpu_freq = std::stoi(freq.value());
}
});
sub->append("Fila de instruções", [&](menu::item_proxy &ip)
{
filebox fb(0,true);
inputbox ibox(fm,"Localização do arquivo com a lista de instruções:");
inputbox::path caminho("",fb);
if(ibox.show_modal(caminho))
{
auto path = caminho.value();
inFile.open(path);
if(!add_instructions(inFile,instruction_queue,instruct))
show_message("Arquivo inválido","Não foi possível abrir o arquivo!");
else
fila = true;
}
});
sub->append("Valores de registradores inteiros",[&](menu::item_proxy &ip)
{
filebox fb(0,true);
inputbox ibox(fm,"Localização do arquivo de valores de registradores inteiros:");
inputbox::path caminho("",fb);
if(ibox.show_modal(caminho))
{
auto path = caminho.value();
inFile.open(path);
if(!inFile.is_open())
show_message("Arquivo inválido","Não foi possível abrir o arquivo!");
else
{
auto reg_gui = reg.at(0);
int value,i = 0;
while(inFile >> value && i < 32)
{
reg_gui.at(i).text(1,std::to_string(value));
i++;
}
for(; i < 32 ; i++)
reg_gui.at(i).text(1,"0");
inFile.close();
}
}
});
sub->append("Valores de registradores PF",[&](menu::item_proxy &ip)
{
filebox fb(0,true);
inputbox ibox(fm,"Localização do arquivo de valores de registradores PF:");
inputbox::path caminho("",fb);
if(ibox.show_modal(caminho))
{
auto path = caminho.value();
inFile.open(path);
if(!inFile.is_open())
show_message("Arquivo inválido","Não foi possível abrir o arquivo!");
else
{
auto reg_gui = reg.at(0);
int i = 0;
float value;
while(inFile >> value && i < 32)
{
reg_gui.at(i).text(4,std::to_string(value));
i++;
}
for(; i < 32 ; i++)
reg_gui.at(i).text(4,"0");
inFile.close();
}
}
});
sub->append("Valores de memória",[&](menu::item_proxy &ip)
{
filebox fb(0,true);
inputbox ibox(fm,"Localização do arquivo de valores de memória:");
inputbox::path caminho("",fb);
if(ibox.show_modal(caminho))
{
auto path = caminho.value();
inFile.open(path);
if(!inFile.is_open())
show_message("Arquivo inválido","Não foi possível abrir o arquivo!");
else
{
int i = 0;
int value;
while(inFile >> value && i < 500)
{
memory.Set(i,std::to_string(value));
i++;
}
for(; i < 500 ; i++)
{
memory.Set(i,"0");
}
inFile.close();
}
}
});
op.append("Verificar conteúdo...");
auto new_sub = op.create_sub_menu(2);
new_sub->append("Valores de registradores",[&](menu::item_proxy &ip) {
filebox fb(0,true);
inputbox ibox(fm,"Localização do arquivo de valores de registradores:");
inputbox::path caminho("",fb);
if(ibox.show_modal(caminho))
{
auto path = caminho.value();
inFile.open(path);
if(!inFile.is_open())
show_message("Arquivo inválido","Não foi possível abrir o arquivo!");
else
{
string str;
int reg_pos,i;
bool is_float, ok;
ok = true;
while(inFile >> str)
{
if(str[0] == '$')
{
if(str[1] == 'f')
{
i = 2;
is_float = true;
}
else
{
i = 1;
is_float = false;
}
reg_pos = std::stoi(str.substr(i,str.size()-i));
auto reg_gui = reg.at(0);
string value;
inFile >> value;
if(!is_float)
{
if(reg_gui.at(reg_pos).text(1) != value)
{
ok = false;
break;
}
}
else
{
if(std::stof(reg_gui.at(reg_pos).text(4)) != std::stof(value))
{
ok = false;
break;
}
}
}
}
inFile.close();
msgbox msg("Verificação de registradores");
if(ok)
{
msg << "Registradores especificados apresentam valores idênticos!";
msg.icon(msgbox::icon_information);
}
else
{
msg << "Registradores especificados apresentam valores distintos!";
msg.icon(msgbox::icon_error);
}
msg.show();
}
}
});
new_sub->append("Valores de memória",[&](menu::item_proxy &ip) {
filebox fb(0,true);
inputbox ibox(fm,"Localização do arquivo de valores de memória:");
inputbox::path caminho("",fb);
if(ibox.show_modal(caminho))
{
auto path = caminho.value();
inFile.open(path);
if(!inFile.is_open())
show_message("Arquivo inválido","Não foi possível abrir o arquivo!");
else
{
string value;
bool ok;
ok = true;
for(int i = 0 ; i < 500 ; i++)
{
inFile >> value;
if(std::stoi(memory.Get(i)) != (int)std::stol(value,nullptr,16))
{
ok = false;
break;
}
}
inFile.close();
msgbox msg("Verificação de memória");
if(ok)
{
msg << "Endereços de memória especificados apresentam valores idênticos!";
msg.icon(msgbox::icon_information);
}
else
{
msg << "Endereços de memória especificados apresentam valores distintos!";
msg.icon(msgbox::icon_error);
}
msg.show();
}
}
});
op.append("Benchmarks");
auto bench_sub = op.create_sub_menu(3);
bench_sub->append("Fibonacci",[&](menu::item_proxy &ip){
string path = "in/benchmarks/fibonacci/fibonacci.txt";
bench_name = "fibonacci";
inFile.open(path);
if(!add_instructions(inFile,instruction_queue,instruct))
show_message("Arquivo inválido","Não foi possível abrir o arquivo!");
else
fila = true;
});
bench_sub->append("Stall por Divisão",[&](menu::item_proxy &ip){
string path = "in/benchmarks/division_stall.txt";
inFile.open(path);
if(!add_instructions(inFile,instruction_queue,instruct))
show_message("Arquivo inválido","Não foi possível abrir o arquivo!");
else
fila = true;
});
bench_sub->append("Stress de Memória (Stores)",[&](menu::item_proxy &ip){
string path = "in/benchmarks/store_stress/store_stress.txt";
bench_name = "store_stress";
inFile.open(path);
if(!add_instructions(inFile,instruction_queue,instruct))
show_message("Arquivo inválido","Não foi possível abrir o arquivo!");
else
fila = true;
});
bench_sub->append("Stall por hazard estrutural (Adds)",[&](menu::item_proxy &ip){
string path = "in/benchmarks/res_stations_stall.txt";
inFile.open(path);
if(!add_instructions(inFile,instruction_queue,instruct))
show_message("Arquivo inválido","Não foi possível abrir o arquivo!");
else
fila = true;
});
bench_sub->append("Busca Linear",[&](menu::item_proxy &ip){
string path = "in/benchmarks/linear_search/linear_search.txt";
bench_name = "linear_search";
inFile.open(path);
if(!add_instructions(inFile,instruction_queue,instruct))
show_message("Arquivo inválido","Não foi possível abrir o arquivo");
else
fila = true;
path = "in/benchmarks/linear_search/memory.txt";
inFile.open(path);
if(!inFile.is_open())
show_message("Arquivo inválido","Não foi possível abrir o arquivo!");
else
{
int i = 0;
int value;
while(inFile >> value && i < 500)
{
memory.Set(i,std::to_string(value));
i++;
}
for(; i < 500 ; i++)
{
memory.Set(i,"0");
}
inFile.close();
}
path = "in/benchmarks/linear_search/regi_i.txt";
inFile.open(path);
if(!inFile.is_open())
show_message("Arquivo inválido","Não foi possível abrir o arquivo!");
else
{
auto reg_gui = reg.at(0);
int value,i = 0;
while(inFile >> value && i < 32)
{
reg_gui.at(i).text(1,std::to_string(value));
i++;
}
for(; i < 32 ; i++)
reg_gui.at(i).text(1,"0");
inFile.close();
}
});
bench_sub->append("Busca Binária",[&](menu::item_proxy &ip){
string path = "in/benchmarks/binary_search/binary_search.txt";
bench_name = "binary_search";
inFile.open(path);
if(!add_instructions(inFile,instruction_queue,instruct))
show_message("Arquivo inválido","Não foi possível abrir o arquivo");
else
fila = true;
path = "in/benchmarks/binary_search/memory.txt";
inFile.open(path);
if(!inFile.is_open())
show_message("Arquivo inválido","Não foi possível abrir o arquivo!");
else
{
int i = 0;
int value;
while(inFile >> value && i < 500)
{
memory.Set(i,std::to_string(value));
i++;
}
for(; i < 500 ; i++)
{
memory.Set(i,"0");
}
inFile.close();
}
path = "in/benchmarks/binary_search/regs.txt";
inFile.open(path);
if(!inFile.is_open())
show_message("Arquivo inválido","Não foi possível abrir o arquivo!");
else
{
auto reg_gui = reg.at(0);
int value,i = 0;
while(inFile >> value && i < 32)
{
reg_gui.at(i).text(1,std::to_string(value));
i++;
}
for(; i < 32 ; i++)
reg_gui.at(i).text(1,"0");
inFile.close();
}
});
bench_sub->append("Matriz Search",[&](menu::item_proxy &ip){
string path = "in/benchmarks/matriz_search/matriz_search.txt";
bench_name = "matriz_search";
inFile.open(path);
if(!add_instructions(inFile,instruction_queue,instruct))
show_message("Arquivo inválido","Não foi possível abrir o arquivo");
else
fila = true;
path = "in/benchmarks/matriz_search/memory.txt";
inFile.open(path);
if(!inFile.is_open())
show_message("Arquivo inválido","Não foi possível abrir o arquivo!");
else
{
int i = 0;
int value;
while(inFile >> value && i < 500)
{
memory.Set(i,std::to_string(value));
i++;
}
for(; i < 500 ; i++)
{
memory.Set(i,"0");
}
inFile.close();
}
path = "in/benchmarks/matriz_search/regs.txt";
inFile.open(path);
if(!inFile.is_open())
show_message("Arquivo inválido","Não foi possível abrir o arquivo!");
else
{
auto reg_gui = reg.at(0);
int value,i = 0;
while(inFile >> value && i < 32)
{
reg_gui.at(i).text(1,std::to_string(value));
i++;
}
for(; i < 32 ; i++)
reg_gui.at(i).text(1,"0");
inFile.close();
}
});
bench_sub->append("Bubble Sort",[&](menu::item_proxy &ip){
string path = "in/benchmarks/bubble_sort/bubble_sort.txt";
bench_name = "bubble_sort";
inFile.open(path);
if(!add_instructions(inFile,instruction_queue,instruct))
show_message("Arquivo inválido","Não foi possível abrir o arquivo");
else
fila = true;
path = "in/benchmarks/bubble_sort/memory.txt";
|
inFile.open(path);
if(!inFile.is_open())
show_message("Arquivo inválido","Não foi possível abrir o arquivo!");
else
{
int i = 0;
int value;
while(inFile >> value && i < 500)
{
memory.Set(i,std::to_string(value));
i++;
}
for(; i < 500 ; i++)
{
memory.Set(i,"0");
}
inFile.close();
}
path = "in/benchmarks/bubble_sort/regs.txt";
inFile.open(path);
if(!inFile.is_open())
show_message("Arquivo inválido","Não foi possível abrir o arquivo!");
else
{
auto reg_gui = reg.at(0);
int value,i = 0;
while(inFile >> value && i < 32)
{
reg_gui.at(i).text(1,std::to_string(value));
i++;
}
for(; i < 32 ; i++)
reg_gui.at(i).text(1,"0");
inFile.close();
}
});
bench_sub->append("Insertion Sort",[&](menu::item_proxy &ip){
string path = "in/benchmarks/insertion_sort/insertion_sort.txt";
bench_name = "insertion_sort";
inFile.open(path);
if(!add_instructions(inFile,instruction_queue,instruct))
show_message("Arquivo inválido","Não foi possível abrir o arquivo");
else
fila = true;
path = "in/benchmarks/insertion_sort/memory.txt";
inFile.open(path);
if(!inFile.is_open())
show_message("Arquivo inválido","Não foi possível abrir o arquivo!");
else
{
int i = 0;
int value;
while(inFile >> value && i < 500)
{
memory.Set(i,std::to_string(value));
i++;
}
for(; i < 500 ; i++)
{
memory.Set(i,"0");
}
inFile.close();
}
path = "in/benchmarks/insertion_sort/regs.txt";
inFile.open(path);
if(!inFile.is_open())
show_message("Arquivo inválido","Não foi possível abrir o arquivo!");
else
{
auto reg_gui = reg.at(0);
int value,i = 0;
while(inFile >> value && i < 32)
{
reg_gui.at(i).text(1,std::to_string(value));
i++;
}
for(; i < 32 ; i++)
reg_gui.at(i).text(1,"0");
inFile.close();
}
});
bench_sub->append("Tick Tack",[&](menu::item_proxy &ip){
string path = "in/benchmarks/tick_tack/tick_tack.txt";
bench_name = "tick_tack";
inFile.open(path);
if(!add_instructions(inFile,instruction_queue,instruct))
show_message("Arquivo inválido","Não foi possível abrir o arquivo");
else
fila = true;
path = "in/benchmarks/tick_tack/regs.txt";
inFile.open(path);
if(!inFile.is_open())
show_message("Arquivo inválido","Não foi possível abrir o arquivo!");
else
{
auto reg_gui = reg.at(0);
int value,i = 0;
while(inFile >> value && i < 32)
{
reg_gui.at(i).text(1,std::to_string(value));
i++;
}
for(; i < 32 ; i++)
reg_gui.at(i).text(1,"0");
inFile.close();
}
});
vector<string> columns = {"#","Name","Busy","Op","Vj","Vk","Qj","Qk","A"};
for(unsigned int i = 0 ; i < columns.size() ; i++)
{
table.append_header(columns[i].c_str());
if(i && i != 3)
table.column_at(i).width(45);
else if (i == 3)
table.column_at(i).width(60);
else
table.column_at(i).width(30);
}
columns = {"","Value","Qi"};
sizes = {30,75,40};
for(unsigned int k = 0 ; k < 2 ; k++)
for(unsigned int i = 0 ; i < columns.size() ; i++)
{
reg.append_header(columns[i]);
reg.column_at(k*columns.size() + i).width(sizes[i]);
}
auto reg_gui = reg.at(0);
for(int i = 0 ; i < 32 ;i++)
{
string index = std::to_string(i);
reg_gui.append("R" + index);
reg_gui.at(i).text(3,"F" + index);
}
columns = {"Instruction","Issue","Execute","Write Result"};
sizes = {140,60,70,95};
for(unsigned int i = 0 ; i < columns.size() ; i++)
{
instruct.append_header(columns[i]);
instruct.column_at(i).width(sizes[i]);
}
columns = {"Entry","Busy","Instruction","State","Destination","Value"};
sizes = {45,45,120,120,90,60};
for(unsigned int i = 0 ; i < columns.size() ; i++)
{
rob.append_header(columns[i]);
rob.column_at(i).width(sizes[i]);
}
srand(static_cast <unsigned> (time(0)));
for(int i = 0 ; i < 32 ; i++)
{
if(i)
reg_gui.at(i).text(1,std::to_string(rand()%100));
else
reg_gui.at(i).text(1,std::to_string(0));
reg_gui.at(i).text(2,"0");
reg_gui.at(i).text(4,std::to_string(static_cast <float> (rand()) / static_cast <float> (RAND_MAX/100.0)));
reg_gui.at(i).text(5,"0");
}
for(int i = 0 ; i < 500 ; i++)
memory.Push(std::to_string(rand()%100));
for(int k = 1; k < argc; k+=2)
{
int i;
if (strlen(argv[k]) > 2)
show_message("Opção inválida",string("Opção \"") + string(argv[k]) + string("\" inválida"));
else
{
char c = argv[k][1];
switch(c)
{
case 'q':
inFile.open(argv[k+1]);
if(!add_instructions(inFile,instruction_queue,instruct))
show_message("Arquivo inválido","Não foi possível abrir o arquivo!");
else
fila = true;
break;
case 'i':
inFile.open(argv[k+1]);
int value;
i = 0;
if(!inFile.is_open())
show_message("Arquivo inválido","Não foi possível abrir o arquivo!");
else
{
while(inFile >> value && i < 32)
{
reg_gui.at(i).text(1,std::to_string(value));
i++;
}
for(; i < 32 ; i++)
reg_gui.at(i).text(1,"0");
inFile.close();
}
break;
case 'f':
float value_fp;
i = 0;
inFile.open(argv[k+1]);
if(!inFile.is_open())
show_message("Arquivo inválido","Não foi possível abrir o arquivo!");
else
{
while(inFile >> value_fp && i < 32)
{
reg_gui.at(i).text(4,std::to_string(value_fp));
i++;
}
for(; i < 32 ; i++)
reg_gui.at(i).text(4,"0");
inFile.close();
}
break;
case 'm':
inFile.open(argv[k+1]);
if(!inFile.is_open())
show_message("Arquivo inválido","Não foi possível abrir o arquivo!");
else
{
int value;
i = 0;
while(inFile >> value && i < 500)
{
memory.Set(i,std::to_string(value));
i++;
}
for(; i < 500 ; i++)
{
memory.Set(i,"0");
}
inFile.close();
}
break;
case 'r':
inFile.open(argv[k+1]);
if(!inFile.is_open())
show_message("Arquivo inválido","Não foi possível abrir o arquivo!");
else
{
int value;
if(inFile >> value && value <= 10 && value > 0)
nadd = value;
if(inFile >> value && value <= 10 && value > 0)
nmul = value;
if(inFile >> value && value <= 10 && value > 0)
nls = value;
inFile.close();
}
break;
case 's':
spec = true;
set_spec(plc,spec);
//spec_ip.checked(true);
k--;
break;
case 'l':
inFile.open(argv[k+1]);
if(!inFile.is_open())
show_message("Arquivo inválido","Não foi possível abrir o arquivo!");
else
{
string inst;
int value;
while(inFile >> inst)
{
if(inFile >> value && instruct_time.count(inst))
instruct_time[inst] = value;
}
}
inFile.close();
break;
default:
show_message("Opção inválida",string("Opção \"") + string(argv[k]) + string("\" inválida"));
break;
}
}
}
clock_control.enabled(false);
run_all.enabled(false);
start.events().click([&]
{
if(fila)
{
start.enabled(false);
clock_control.enabled(true);
run_all.enabled(true);
//Desativa os menus apos inicio da execucao
op.enabled(0,false);
op.enabled(1,false);
op.enabled(3,false);
for(int i = 0; i < 2; i++)
spec_sub->enabled(i, false);
for(int i = 0 ; i < 8 ; i++)
sub->enabled(i,false);
for(int i = 0 ; i < 10 ; i++)
bench_sub->enabled(i,false);
if(spec){
// Flag mode setada pela escolha no menu
if(mode == 1)
top1.rob_mode(n_bits,nadd,nmul,nls,instruct_time,instruction_queue,table,memory,reg,instruct,clock_count,rob);
else if(mode == 2)
top1.rob_mode_bpb(n_bits, bpb_size, nadd,nmul,nls,instruct_time,instruction_queue,table,memory,reg,instruct,clock_count,rob);
}
else
top1.simple_mode(nadd,nmul,nls,instruct_time,instruction_queue,table,memory,reg,instruct,clock_count);
sc_start();
}
else
show_message("Fila de instruções vazia","A fila de instruções está vazia. Insira um conjunto de instruções para iniciar.");
});
clock_control.events().click([&]
{
if(top1.get_queue().queue_is_empty() && top1.get_rob().rob_is_empty())
return;
if(sc_is_running())
sc_start();
});
run_all.events().click([&]{
// enquanto queue e rob nao estao vazios, roda ate o fim
while(!(top1.get_queue().queue_is_empty() && top1.get_rob().rob_is_empty())){
if(sc_is_running())
sc_start();
}
top1.metrics(cpu_freq, mode, bench_name, n_bits);
});
exit.events().click([]
{
sc_stop();
API::exit();
});
fm.show();
exec();
return 0;
}
|
// ================================================================
// NVDLA Open Source Project
//
// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
// NVDLA Open Hardware License; Check "LICENSE" which comes with
// this distribution for more information.
// ================================================================
// File Name: NvdlaCoreDummy.h
#ifndef _NVDLACOREDUMMY_H_
#define _NVDLACOREDUMMY_H_
#define SC_INCLUDE_DYNAMIC_PROCESSES
#include <systemc.h>
#include <tlm.h>
#include "tlm_utils/multi_passthrough_initiator_socket.h"
#include "tlm_utils/multi_passthrough_target_socket.h"
#include "scsim_common.h"
#define NVDLA_AXI_ADAPTOR_OUT_STANDING_REQUEST_NUM 1024
SCSIM_NAMESPACE_START(clib)
// clib class forward declaration
SCSIM_NAMESPACE_END()
SCSIM_NAMESPACE_START(cmod)
class NvdlaCoreDummy : public sc_module {
public:
SC_HAS_PROCESS(NvdlaCoreDummy);
NvdlaCoreDummy( sc_module_name module_name );
~NvdlaCoreDummy();
// Initiator sockets
// Initiator Socket (unrecognized protocol: nvdla_xx2csb_resp_t): cvif2csb_resp
tlm_utils::multi_passthrough_initiator_socket<NvdlaCoreDummy, 32, tlm::tlm_base_protocol_types> cvif2csb_resp;
// Initiator Socket (unrecognized protocol: nvdla_xx2csb_resp_t): mcif2csb_resp
tlm_utils::multi_passthrough_initiator_socket<NvdlaCoreDummy, 32, tlm::tlm_base_protocol_types> mcif2csb_resp;
// Target sockets
// Target Socket (unrecognized protocol: NV_MSDEC_csb2xx_16m_secure_be_lvl_t): csb2cvif_req
tlm_utils::multi_passthrough_target_socket<NvdlaCoreDummy, 32, tlm::tlm_base_protocol_types> csb2cvif_req;
virtual void csb2cvif_req_b_transport(int ID, tlm::tlm_generic_payload& bp, sc_time& delay);
// Target Socket (unrecognized protocol: NV_MSDEC_csb2xx_16m_secure_be_lvl_t): csb2mcif_req
tlm_utils::multi_passthrough_target_socket<NvdlaCoreDummy, 32, tlm::tlm_base_protocol_types> csb2mcif_req;
virtual void csb2mcif_req_b_transport(int ID, tlm::tlm_generic_payload& bp, sc_time& delay);
// sc_in, sc_out, sc_inout
};
SCSIM_NAMESPACE_END()
extern "C" scsim::cmod::NvdlaCoreDummy * NvdlaCoreDummyCon(sc_module_name module_name);
#endif
|
#ifndef SYSC_TYPES_H
#define SYSC_TYPES_H
#include <iomanip>
#include <iostream>
#include <systemc.h>
#include "secda_hw_utils.sc.h"
#ifndef DWAIT
#ifndef __SYNTHESIS__
#define DWAIT(x) wait(x)
#else
#define DWAIT(x)
#endif
#endif
#define INITSIGPORT(X, SID) X((std::string(#X) + std::to_string(SID)).c_str())
// Hardware struct to contain output signal and port
struct sc_out_sig {
sc_out<int> oS;
sc_signal<int> iS;
void write(int x) {
oS.write(x);
iS.write(x);
}
int read() { return iS.read(); }
void operator=(int x) { write(x); }
void bind(sc_signal<int> &sig) { oS.bind(sig); }
void operator()(sc_signal<int> &sig) { bind(sig); }
void bind(sc_out<int> &sig) { oS.bind(sig); }
void operator()(sc_out<int> &sig) { bind(sig); }
};
typedef struct _DATA {
sc_uint<32> data;
bool tlast;
void operator=(_DATA _data) {
data = _data.data;
tlast = _data.tlast;
}
inline friend ostream &operator<<(ostream &os, const _DATA &v) {
cout << "data: " << v.data << " tlast: " << v.tlast;
return os;
}
void pack(sc_int<8> a1, sc_int<8> a2, sc_int<8> a3, sc_int<8> a4) {
data.range(7, 0) = a1;
data.range(15, 8) = a2;
data.range(23, 16) = a3;
data.range(31, 24) = a4;
}
} DATA;
typedef struct _SDATA {
sc_int<32> data;
bool tlast;
inline friend ostream &operator<<(ostream &os, const _SDATA &v) {
cout << "data: " << v.data << " tlast: " << v.tlast;
return os;
}
} SDATA;
template <int W>
struct _FDATA {
sc_uint<W> data;
bool tlast;
inline friend ostream &operator<<(ostream &os, const _FDATA &v) {
cout << "data: " << v.data << " tlast: " << v.tlast;
return os;
}
};
struct rm_data2 {
sc_fifo_in<DATA> dout1;
sc_fifo_out<DATA> din1;
// int base_r_addr = 0;
// int mem_r_addr = 0;
// sc_out<bool> mem_start_read;
// sc_in<bool> mem_read_done;
// sc_out<unsigned int> mem_r_addr_p;
// sc_out<unsigned int> mem_r_length_p;
// int base_w_addr = 0;
// int mem_w_addr = 0;
// sc_out<bool> mem_start_write;
// sc_in<bool> mem_write_done;
// sc_out<unsigned int> mem_w_addr_p;
// sc_out<unsigned int> mem_w_length_p;
bool use_sim = false;
int layer = 0;
// this writes to acc and reads from main memory
void generate_reads(int addr, int length) {
// generate trace for ramulator
ofstream file;
std::string filename =
".data/secda_pim/traces/" + std::to_string(layer) + ".trace";
file.open(filename, std::ios_base::app);
int index = 0;
for (int i = 0; i < length; i += 4) {
file << "0x" << std::setfill('0') << std::setw(8) << std::hex
<< (addr + i + 0) << " R" << endl;
// file << "0x" << std::setfill('0') << std::setw(8) << std::hex
// << (addr + i + 1) << " R" << endl;
// file << "0x" << std::setfill('0') << std::setw(8) << std::hex
// << (addr + i + 2) << " R" << endl;
// file << "0x" << std::setfill('0') << std::setw(8) << std::hex
// << (addr + i + 3) << " R" << endl;
}
file.close();
}
void generate_writes(int addr, int length) {
// generate trace for ramulator
ofstream file;
std::string filename =
".data/secda_pim/traces/" + std::to_string(layer) + ".trace";
file.open(filename, std::ios_base::app);
int index = 0;
for (int i = 0; i < length; i += 4) {
file << "0x" << std::setfill('0') << std::setw(8) << std::hex
<< (addr + i + 0) << " W" << endl;
// file << "0x" << std::setfill('0') << std::setw(8) << std::hex
// << (addr + i + 1) << " W" << endl;
// file << "0x" << std::setfill('0') << std::setw(8) << std::hex
// << (addr + i + 2) << " W" << endl;
// file << "0x" << std::setfill('0') << std::setw(8) << std::hex
// << (addr + i + 3) << " W" << endl;
}
file.close();
}
void write(DATA d, int r_addr) {
if (!use_sim) {
// generate_reads(r_addr, 4);
// mem_start_read.write(true);
// mem_r_addr_p.write(r_addr);
// mem_r_length_p.write(4);
// DWAIT(1);
// while (!mem_read_done.read()) DWAIT(1);
// mem_start_read.write(false);
// DWAIT(1);
}
din1.write(d);
}
// this reads from acc and writes to the main memory
DATA read(int w_addr) {
if (!use_sim) {
// generate_writes(w_addr, 4);
// mem_start_write.write(true);
// mem_w_addr_p.write(w_addr);
// mem_w_length_p.write(4);
// DWAIT(1);
// while (!mem_write_done.read()) DWAIT(1);
// mem_start_write.write(false);
// DWAIT(1);
}
return dout1.read();
}
};
template <int W>
using FDATA = _FDATA<W>;
#endif |
//
// Copyright 2022 Sergey Khabarov, [email protected]
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
#pragma once
#include <systemc.h>
#include "sdctrl_cfg.h"
#include "sdctrl_crc7.h"
namespace debugger {
SC_MODULE(sdctrl_cmd_transmitter) {
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
sc_in<bool> i_sclk_posedge;
sc_in<bool> i_sclk_negedge;
sc_in<bool> i_cmd;
sc_out<bool> o_cmd;
sc_out<bool> o_cmd_dir;
sc_out<bool> o_cmd_cs;
sc_in<bool> i_spi_mode; // SPI mode was selected by FW
sc_in<sc_uint<4>> i_err_code;
sc_in<bool> i_wdog_trigger; // Event from wdog timer
sc_in<bool> i_cmd_set_low; // Set forcibly o_cmd output to LOW
sc_in<bool> i_req_valid;
sc_in<sc_uint<6>> i_req_cmd;
sc_in<sc_uint<32>> i_req_arg;
sc_in<sc_uint<3>> i_req_rn; // R1, R3,R6 or R2
sc_out<bool> o_req_ready;
sc_out<bool> o_resp_valid;
sc_out<sc_uint<6>> o_resp_cmd; // Mirrored command
sc_out<sc_uint<32>> o_resp_reg; // Card Status, OCR register (R3) or RCA register (R6)
sc_out<sc_uint<7>> o_resp_crc7_rx; // Received CRC7
sc_out<sc_uint<7>> o_resp_crc7_calc; // Calculated CRC7
sc_out<sc_uint<15>> o_resp_spistatus; // {R1,R2} response valid only in SPI mode
sc_in<bool> i_resp_ready;
sc_out<bool> o_wdog_ena;
sc_out<bool> o_err_valid;
sc_out<sc_uint<4>> o_err_setcode;
void comb();
void registers();
SC_HAS_PROCESS(sdctrl_cmd_transmitter);
sdctrl_cmd_transmitter(sc_module_name name,
bool async_reset);
virtual ~sdctrl_cmd_transmitter();
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
bool async_reset_;
// Command request states:
static const uint8_t CMDSTATE_IDLE = 0;
static const uint8_t CMDSTATE_REQ_CONTENT = 1;
static const uint8_t CMDSTATE_REQ_CRC7 = 2;
static const uint8_t CMDSTATE_REQ_STOPBIT = 3;
static const uint8_t CMDSTATE_RESP_WAIT = 4;
static const uint8_t CMDSTATE_RESP_TRANSBIT = 5;
static const uint8_t CMDSTATE_RESP_CMD_MIRROR = 6;
static const uint8_t CMDSTATE_RESP_REG = 7;
static const uint8_t CMDSTATE_RESP_CID_CSD = 8;
static const uint8_t CMDSTATE_RESP_CRC7 = 9;
static const uint8_t CMDSTATE_RESP_STOPBIT = 10;
static const uint8_t CMDSTATE_RESP_SPI_R1 = 11;
static const uint8_t CMDSTATE_RESP_SPI_R2 = 12;
static const uint8_t CMDSTATE_RESP_SPI_DATA = 13;
static const uint8_t CMDSTATE_PAUSE = 15;
struct sdctrl_cmd_transmitter_registers {
sc_signal<sc_uint<6>> req_cmd;
sc_signal<sc_uint<3>> req_rn;
sc_signal<bool> resp_valid;
sc_signal<sc_uint<6>> resp_cmd;
sc_signal<sc_uint<32>> resp_arg;
sc_signal<sc_uint<15>> resp_spistatus;
sc_signal<sc_uint<40>> cmdshift;
sc_signal<sc_uint<6>> cmdmirror;
sc_signal<sc_uint<32>> regshift;
sc_signal<sc_biguint<120>> cidshift;
sc_signal<sc_uint<7>> crc_calc;
sc_signal<sc_uint<7>> crc_rx;
sc_signal<sc_uint<7>> cmdbitcnt;
sc_signal<bool> crc7_clear;
sc_signal<sc_uint<4>> cmdstate;
sc_signal<bool> err_valid;
sc_signal<sc_uint<4>> err_setcode;
sc_signal<bool> cmd_cs;
sc_signal<bool> cmd_dir;
sc_signal<bool> wdog_ena;
} v, r;
void sdctrl_cmd_transmitter_r_reset(sdctrl_cmd_transmitter_registers &iv) {
iv.req_cmd = 0;
iv.req_rn = 0;
iv.resp_valid = 0;
iv.resp_cmd = 0;
iv.resp_arg = 0;
iv.resp_spistatus = 0;
iv.cmdshift = ~0ull;
iv.cmdmirror = 0;
iv.regshift = 0;
iv.cidshift = 0;
iv.crc_calc = 0;
iv.crc_rx = 0;
iv.cmdbitcnt = 0;
iv.crc7_clear = 1;
iv.cmdstate = CMDSTATE_IDLE;
iv.err_valid = 0;
iv.err_setcode = CMDERR_NONE;
iv.cmd_cs = 1;
iv.cmd_dir = 1;
iv.wdog_ena = 0;
}
sc_signal<sc_uint<7>> wb_crc7;
sc_signal<bool> w_crc7_next;
sc_signal<bool> w_crc7_dat;
sdctrl_crc7 *crc0;
};
} // namespace debugger
|
//
// Copyright 2022 Sergey Khabarov, [email protected]
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
#pragma once
#include <systemc.h>
#include "../../river_cfg.h"
namespace debugger {
SC_MODULE(Shifter) {
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
sc_in<sc_uint<4>> i_mode; // operation type: [0]0=rv64;1=rv32;[1]=sll;[2]=srl;[3]=sra
sc_in<sc_uint<RISCV_ARCH>> i_a1; // Operand 1
sc_in<sc_uint<6>> i_a2; // Operand 2
sc_out<sc_uint<RISCV_ARCH>> o_res; // Result
void comb();
void registers();
SC_HAS_PROCESS(Shifter);
Shifter(sc_module_name name,
bool async_reset);
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
bool async_reset_;
struct Shifter_registers {
sc_signal<sc_uint<RISCV_ARCH>> res;
} v, r;
void Shifter_r_reset(Shifter_registers &iv) {
iv.res = 0;
}
};
} // namespace debugger
|
#include <systemc.h>
SC_MODULE( tb ) {
public:
sc_out<bool> inp_a[4], inp_b[4], inp_cin;
sc_in<bool> sum[4], co;
SC_HAS_PROCESS( tb );
bool a[6][4];
bool b[6][4];
tb( sc_module_name nm );
private:
void source();
void sink();
};
|
//-----------------------------------------------------
//Module: Image Unification (PV) Header
//By: Roger Morales Monge
//Description: Programmer's View Model of unification
//process for two images (magnitude)
//-----------------------------------------------------
#ifdef IMG_UNIFICATE_PV_EN
#ifndef IMG_UNIFICATE_HPP
#define IMG_UNIFICATE_HPP
#include <systemc.h>
#include <math.h>
SC_MODULE (img_unification_module) {
//-----------Internal Variables-----------
unsigned char x_pixel, y_pixel;
unsigned char *unificated_pixel;
//-----------Constructor-----------
SC_CTOR(img_unification_module) {
} // End of Constructor
//------------Methods------------
void unificate_pixel(int x_pixel, int y_pixel, unsigned char * unificated_pixel);
void unificate_img(unsigned char *x_img, unsigned char *y_img, unsigned char *unificated_img, int img_size, int channels);
int norm(int a, int b);
};
#endif //IMG_UNIFICATE_HPP
#endif //IMG_UNIFICATE_PV_EN
|
/************************************************/
// Copyright tlm_noc contributors.
// Author Mike
// SPDX-License-Identifier: Apache-2.0
/************************************************/
#ifndef __HOST_H__
#define __HOST_H__
#include <sstream>
#include <systemc.h>
#include <tlm.h>
#include <tlm_utils/simple_initiator_socket.h>
#include <tlm_utils/simple_target_socket.h>
#include "host_base.h"
using namespace std;
using namespace sc_core;
using namespace tlm_utils;
using namespace tlm;
class host: public host_base {
SC_HAS_PROCESS(host);
public:
int32_t host_id;
host(sc_core::sc_module_name name, int32_t hid);
private:
void thread(void);
void read(uint64_t* src, uint64_t* dst, uint64 id, uint64_t addr);
void write(uint64_t* src, uint64_t* dst, uint64 id, uint64_t addr);
};
#endif
|
/****************************************************************************
*
* Copyright (c) 2017, Cadence Design Systems. All Rights Reserved.
*
* This file contains confidential information that may not be
* distributed under any circumstances without the written permision
* of Cadence Design Systems.
*
****************************************************************************/
#ifndef _DUT_SC_WRAP_INCLUDED_
#define _DUT_SC_WRAP_INCLUDED_
#include <systemc.h>
struct dut;
#include "cynw_p2p.h"
#include "hls_enums.h"
// Declaration of wrapper with BEH level ports
SC_MODULE(dut_wrapper)
{
public:
sc_in< bool > clk;
sc_in< bool > rst;
sc_out< bool > finish;
cynw::cynw_p2p_base_out <sc_dt::sc_int <(int)32 >, HLS::hls_enum <(int)1 > > find_max_x_out;
cynw::cynw_p2p_base_in <sc_dt::sc_int <(int)32 >, HLS::hls_enum <(int)1 > > find_max_return_in;
// These signals are used to connect structured ports or ports that need
// type conversion to the RTL ports.
// create the netlist
void InitInstances( sc_int< 32 > _A[10], sc_int< 32 > _B[10], sc_int< 32 > _D[10]);
void InitThreads();
// delete the netlist
void DeleteInstances();
// The following threads are used to connect structured ports to the actual
// RTL ports.
SC_HAS_PROCESS(dut_wrapper);
dut_wrapper( sc_core::sc_module_name name, sc_int< 32 > _A[10], sc_int< 32 > _B[10], sc_int< 32 > _D[10] )
: sc_module(name)
,clk("clk")
,rst("rst")
,finish("finish")
,find_max_x_out("find_max_x_out")
,find_max_return_in("find_max_return_in")
,dut0(0)
{
InitInstances( _A, _B, _D);
InitThreads();
}
// destructor
~dut_wrapper()
{
DeleteInstances();
}
dut* dut0;
};
#endif /* _DUT_SC_WRAP_INCLUDED_ */
|
/*+
* Copyright (c) 2022-2023 Zhengde
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1 Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2 Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3 Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
/*+
* special LT target to illustrate bus access to memory mapped peripheral
* adapted from SystemC TLM example
-*/
#ifndef __MYTARGET_H__
#define __MYTARGET_H__
#include <systemc.h>
#include "tlm.h" // TLM headers
#include "memory.h"
#include "tlm_utils/simple_target_socket.h"
class MyTarget
: public sc_core::sc_module // inherit from SC module base clase
, virtual public tlm::tlm_fw_transport_if<> /// inherit from TLM "forward interface"
{
public:
// PORTS
// The target writes and reads these signals to
// access registers of peripheral
sc_in<bool> bus2ip_clk;
sc_in<bool> bus2ip_rst_n;
sc_out<bool> bus2ip_rd_ce_o;
sc_out<bool> bus2ip_wr_ce_o;
sc_out<uint32_t> bus2ip_addr_o;
sc_out<uint32_t> bus2ip_data_o;
sc_in<uint32_t> ip2bus_data_i;
public:
// Constructor for LT target
MyTarget
( sc_core::sc_module_name module_name ///< SC module name
, const unsigned int ID ///< target ID
, const unsigned int clock_id ///< corresponding to clockIdentity
, const sc_core::sc_time accept_delay ///< accept delay (SC_TIME, SC_NS)
);
private:
// thread to initialize and reset peripheral bus
void reset_pbus(void);
// task to write register
void write_reg(const uint32_t addr, const uint32_t data);
// task to read register
void read_reg(const uint32_t addr, uint32_t &data);
// b_transport() - Blocking Transport
void // returns nothing
b_transport
( tlm::tlm_generic_payload &payload // ref to payload
, sc_core::sc_time &delay_time // delay time
);
/// Not implemented for this example but required by interface
tlm::tlm_sync_enum // sync status
nb_transport_fw
( tlm::tlm_generic_payload &gp ///< generic payoad pointer
, tlm::tlm_phase &phase ///< transaction phase
, sc_core::sc_time &delay_time ///< time taken for transport
)
{
return tlm::TLM_COMPLETED;
}
/// Not implemented for this example but required by interface
bool // success / failure
get_direct_mem_ptr
( tlm::tlm_generic_payload &payload, // address + extensions
tlm::tlm_dmi &dmi_data // DMI data
)
{
return false;
}
/// Not implemented for this example but required by interface
unsigned int // result
transport_dbg
( tlm::tlm_generic_payload &payload // debug payload
)
{
return 0;
}
// Member Variables ===================================================
public:
typedef tlm::tlm_generic_payload *gp_ptr; ///< generic payload pointer
//for hierarchical parent-to-child binding, simple_target_socket is not allowed
tlm::tlm_target_socket<> m_target_socket; ///< target socket
private:
const unsigned int m_ID; ///< target ID, corresponding to port id in fact
const unsigned int m_clock_id; ///< corresponding to clockIdentity
const sc_core::sc_time m_accept_delay; ///< accept delay
};
#endif /* __MYTARGET_H__ */
|
/*****************************************************************************
Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
more contributor license agreements. See the NOTICE file distributed
with this work for additional information regarding copyright ownership.
Accellera licenses this file to you under the Apache License, Version 2.0
(the "License"); you may not use this file except in compliance with the
License. You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
implied. See the License for the specific language governing
permissions and limitations under the License.
*****************************************************************************/
/*****************************************************************************
simple_bus_slow_mem.h : Slave : The memory (slave) with wait states.
Original Author: Ric Hilderink, Synopsys, Inc., 2001-10-11
*****************************************************************************/
/*****************************************************************************
MODIFICATION LOG - modifiers, enter your name, affiliation, date and
changes you are making here.
Name, Affiliation, Date:
Description of Modification:
*****************************************************************************/
#ifndef __simple_bus_slow_mem_h
#define __simple_bus_slow_mem_h
#include <systemc.h>
#include "simple_bus_types.h"
#include "simple_bus_slave_if.h"
class simple_bus_slow_mem
: public simple_bus_slave_if
, public sc_module
{
public:
// ports
sc_in_clk clock;
// constructor
simple_bus_slow_mem(sc_module_name name_
, unsigned int start_address
, unsigned int end_address
, unsigned int nr_wait_states)
: sc_module(name_)
, m_start_address(start_address)
, m_end_address(end_address)
, m_nr_wait_states(nr_wait_states)
, m_wait_count(-1)
{
// process declaration
SC_METHOD(wait_loop);
dont_initialize();
sensitive << clock.pos();
sc_assert(m_start_address <= m_end_address);
sc_assert((m_end_address-m_start_address+1)%4 == 0);
unsigned int size = (m_end_address-m_start_address+1)/4;
MEM = new int [size];
for (unsigned int i = 0; i < size; ++i)
MEM[i] = 0;
}
// destructor
~simple_bus_slow_mem();
// process
void wait_loop();
// direct Slave Interface
bool direct_read(int *data, unsigned int address);
bool direct_write(int *data, unsigned int address);
// Slave Interface
simple_bus_status read(int *data, unsigned int address);
simple_bus_status write(int *data, unsigned int address);
unsigned int start_address() const;
unsigned int end_address() const;
private:
int *MEM;
unsigned int m_start_address;
unsigned int m_end_address;
unsigned int m_nr_wait_states;
int m_wait_count;
}; // end class simple_bus_slow_mem
inline simple_bus_slow_mem::~simple_bus_slow_mem()
{
if (MEM) delete [] MEM;
MEM = (int *)0;
}
inline void simple_bus_slow_mem::wait_loop()
{
if (m_wait_count >= 0) m_wait_count--;
}
inline bool simple_bus_slow_mem::direct_read(int *data, unsigned int address)
{
*data = MEM[(address - m_start_address)/4];
return true;
}
inline bool simple_bus_slow_mem::direct_write(int *data, unsigned int address)
{
MEM[(address - m_start_address)/4] = *data;
return true;
}
inline simple_bus_status simple_bus_slow_mem::read(int *data
, unsigned int address)
{
// accept a new call if m_wait_count < 0)
if (m_wait_count < 0)
{
m_wait_count = m_nr_wait_states;
return SIMPLE_BUS_WAIT;
}
if (m_wait_count == 0)
{
*data = MEM[(address - m_start_address)/4];
return SIMPLE_BUS_OK;
}
return SIMPLE_BUS_WAIT;
}
inline simple_bus_status simple_bus_slow_mem::write(int *data
, unsigned int address)
{
// accept a new call if m_wait_count < 0)
if (m_wait_count < 0)
{
m_wait_count = m_nr_wait_states;
return SIMPLE_BUS_WAIT;
}
if (m_wait_count == 0)
{
MEM[(address - m_start_address)/4] = *data;
return SIMPLE_BUS_OK;
}
return SIMPLE_BUS_WAIT;
}
inline unsigned int simple_bus_slow_mem::start_address() const
{
return m_start_address;
}
inline unsigned int simple_bus_slow_mem::end_address() const
{
return m_end_address;
}
#endif
|
#ifndef IPS_FILTER_TLM_CPP
#define IPS_FILTER_TLM_CPP
#include <systemc.h>
using namespace sc_core;
using namespace sc_dt;
using namespace std;
#include <tlm.h>
#include <tlm_utils/simple_initiator_socket.h>
#include <tlm_utils/simple_target_socket.h>
#include <tlm_utils/peq_with_cb_and_phase.h>
#include "ips_filter_tlm.hpp"
#include "common_func.hpp"
#include "important_defines.hpp"
void ips_filter_tlm::do_when_read_transaction(unsigned char*& data, unsigned int data_length, sc_dt::uint64 address)
{
this->img_result = *(Filter<IPS_IN_TYPE_TB, IPS_OUT_TYPE_TB, IPS_FILTER_KERNEL_SIZE>::result_ptr);
memcpy(data, Filter<IPS_IN_TYPE_TB, IPS_OUT_TYPE_TB, IPS_FILTER_KERNEL_SIZE>::result_ptr, sizeof(IPS_OUT_TYPE_TB));
}
void ips_filter_tlm::do_when_write_transaction(unsigned char*&data, unsigned int data_length, sc_dt::uint64 address)
{
IPS_OUT_TYPE_TB* result = new IPS_OUT_TYPE_TB;
IPS_IN_TYPE_TB* img_window = new IPS_IN_TYPE_TB[3 * 3];
if ((IPS_FILTER_KERNEL_SIZE * IPS_FILTER_KERNEL_SIZE * sizeof(char)) != data_length)
{
SC_REPORT_FATAL("IPS_FILTER", "Illegal transaction size");
}
for (int i = 0; i < IPS_FILTER_KERNEL_SIZE; i++)
{
for (int j = 0; j < IPS_FILTER_KERNEL_SIZE; j++)
{
*(img_window + ((i * IPS_FILTER_KERNEL_SIZE) + j)) = (IPS_IN_TYPE_TB)*(data + ((i * IPS_FILTER_KERNEL_SIZE) + j));
this->img_window[(i * IPS_FILTER_KERNEL_SIZE) + j] = (IPS_IN_TYPE_TB)*(data + ((i * IPS_FILTER_KERNEL_SIZE) + j));
}
}
filter(img_window, result);
}
#endif // IPS_FILTER_TLM_CPP
|
//
// Copyright 2022 Sergey Khabarov, [email protected]
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
#pragma once
#include <systemc.h>
#include "types_pnp.h"
#include "types_amba.h"
#include "types_bus0.h"
#include "axi_slv.h"
namespace debugger {
SC_MODULE(axictrl_bus0) {
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
sc_out<dev_config_type> o_cfg; // Slave config descriptor
sc_vector<sc_in<axi4_master_out_type>> i_xmsto; // AXI4 masters output vector
sc_vector<sc_out<axi4_master_in_type>> o_xmsti; // AXI4 masters input vector
sc_vector<sc_in<axi4_slave_out_type>> i_xslvo; // AXI4 slaves output vectors
sc_vector<sc_out<axi4_slave_in_type>> o_xslvi; // AXI4 slaves input vectors
sc_vector<sc_out<mapinfo_type>> o_mapinfo; // AXI devices memory mapping information
void comb();
void registers();
SC_HAS_PROCESS(axictrl_bus0);
axictrl_bus0(sc_module_name name,
bool async_reset);
virtual ~axictrl_bus0();
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
bool async_reset_;
struct axictrl_bus0_registers {
sc_signal<sc_uint<CFG_BUS0_XMST_LOG2_TOTAL>> r_midx;
sc_signal<sc_uint<CFG_BUS0_XSLV_LOG2_TOTAL>> r_sidx;
sc_signal<sc_uint<CFG_BUS0_XMST_LOG2_TOTAL>> w_midx;
sc_signal<sc_uint<CFG_BUS0_XSLV_LOG2_TOTAL>> w_sidx;
sc_signal<sc_uint<CFG_BUS0_XMST_LOG2_TOTAL>> b_midx;
sc_signal<sc_uint<CFG_BUS0_XSLV_LOG2_TOTAL>> b_sidx;
} v, r;
void axictrl_bus0_r_reset(axictrl_bus0_registers &iv) {
iv.r_midx = CFG_BUS0_XMST_TOTAL;
iv.r_sidx = CFG_BUS0_XSLV_TOTAL;
iv.w_midx = CFG_BUS0_XMST_TOTAL;
iv.w_sidx = CFG_BUS0_XSLV_TOTAL;
iv.b_midx = CFG_BUS0_XMST_TOTAL;
iv.b_sidx = CFG_BUS0_XSLV_TOTAL;
}
sc_signal<mapinfo_type> wb_def_mapinfo;
sc_signal<axi4_slave_in_type> wb_def_xslvi;
sc_signal<axi4_slave_out_type> wb_def_xslvo;
sc_signal<bool> w_def_req_valid;
sc_signal<sc_uint<CFG_SYSBUS_ADDR_BITS>> wb_def_req_addr;
sc_signal<sc_uint<8>> wb_def_req_size;
sc_signal<bool> w_def_req_write;
sc_signal<sc_uint<CFG_SYSBUS_DATA_BITS>> wb_def_req_wdata;
sc_signal<sc_uint<CFG_SYSBUS_DATA_BYTES>> wb_def_req_wstrb;
sc_signal<bool> w_def_req_last;
sc_signal<bool> w_def_req_ready;
sc_signal<bool> w_def_resp_valid;
sc_signal<sc_uint<CFG_SYSBUS_DATA_BITS>> wb_def_resp_rdata;
sc_signal<bool> w_def_resp_err;
axi_slv *xdef0;
};
} // namespace debugger
|
#ifndef _AHB_SLAVE_IF_H_
#define _AHB_SLAVE_IF_H_
#include <stdint.h>
using namespace std;
#include <systemc.h>
#include <tlm.h>
#include <tlm_utils/simple_target_socket.h>
using namespace tlm;
using namespace tlm_utils;
//#include <debug_utils.h>
class ahb_slave_if
{
public:
simple_target_socket<ahb_slave_if> ahb_slave_socket;
ahb_slave_if(uint32_t mapping_size,const char* ahb_slave_name);
~ahb_slave_if()
{
}
virtual void b_transport(tlm_generic_payload& trans, sc_time& delay);
virtual bool local_access(bool write, uint32_t addr, uint32_t& data, unsigned int length, uint32_t burst_length) = 0;
uint32_t get_address_mask();
protected:
private:
uint32_t address_mask;
inline bool is_power_of_two(uint32_t addr);
};
#endif
|
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