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#pragma once
#include <systemc.h>
#include "../../UTIL/debug_util.h"
SC_MODULE(Diviseur)
{
// input :
sc_in<sc_uint<32>> OP1_SE;
sc_in<sc_uint<32>> OP2_SE;
sc_in<sc_uint<2>> CMD_RD;
sc_in<bool> START_SE;
// output :
sc_out<sc_uint<32>> DIVIDER_RES_OUTPUT;
sc_out<bool> BUSY_SE;
sc_out<bool> DONE_SE;
// General interface:
sc_in_clk CLK;
// signals :
sc_signal<sc_biguint<64>> divisor_re;
sc_signal<sc_uint<32>> quotient_re;
sc_signal<sc_biguint<64>> reminder_re;
sc_signal<sc_biguint<64>> divisor_se;
sc_signal<sc_uint<32>> quotient_se;
sc_signal<sc_biguint<64>> reminder_se;
sc_signal<sc_uint<3>> current_state;
sc_signal<sc_uint<3>> next_state;
sc_signal<sc_uint<6>> shift_cpt_se;
sc_signal<sc_uint<6>> shift_cpt_re;
sc_signal<bool> quotient_sign_se;
sc_signal<bool> reminder_sign_se;
//mae
void new_state();
void state_transition();
void mae_output();
void RET();
void trace(sc_trace_file * tf);
SC_CTOR(Diviseur)
{
SC_METHOD(new_state);
sensitive << CLK.pos();
SC_METHOD(state_transition);
sensitive << current_state << START_SE << shift_cpt_re << OP2_SE;
SC_METHOD(mae_output);
sensitive << current_state << START_SE << divisor_re
<< quotient_re << reminder_re
<< OP1_SE << OP2_SE << shift_cpt_re;
SC_METHOD(RET);
sensitive << reminder_re << quotient_re << CMD_RD;
}
}; |
/********************************************************************************
* University of L'Aquila - HEPSYCODE Source Code License *
* *
* *
* (c) 2018-2019 Centre of Excellence DEWS All rights reserved *
********************************************************************************
* <one line to give the program's name and a brief idea of what it does.> *
* Copyright (C) 2022 Vittoriano Muttillo, Luigi Pomante * *
* *
* This program is free software: you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation, either version 3 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
********************************************************************************
* *
* Created on: 09/May/2023 *
* Authors: Vittoriano Muttillo, Marco Santic, Luigi Pomante *
* *
* email: [email protected] *
* [email protected] *
* [email protected] *
* *
********************************************************************************
* This code has been developed from an HEPSYCODE model used as demonstrator by *
* University of L'Aquila. *
*******************************************************************************/
#ifndef __DISPLAY__
#define __DISPLAY__
#include <systemc.h>
#include "datatype.h"
#include "sc_csp_channel.h"
#include "sc_csp_channel_ifs.h"
SC_MODULE(display)
{
sc_port < sc_csp_channel_in_if < system_display_payload > > system_display_port_in;
SC_CTOR(display)
{
SC_THREAD(main);
}
void main();
};
#endif
|
#ifndef COUNTER_TB_H
#define COUNTER_TB_H
#include <systemc.h>
#include "constants.h"
SC_MODULE(CounterTestbench){
// Inputs
sc_in<bool> clk;
sc_in<sc_uint<N> > count_out;
sc_in<bool> overflow_intr;
sc_in<bool> underflow_intr;
//Outputs
sc_out<bool> reset;
sc_out<bool> up_down_ctrl;
sc_out<bool> count_enable;
// Main function of the module
void do_testbench();
SC_CTOR(CounterTestbench){
SC_THREAD(do_testbench);
sensitive << clk.pos();
}
};
#endif
|
#pragma once
#include <systemc.h>
#include "../../UTIL/debug_util.h"
typedef enum // MAE STATES
{
SLAVE_IDLE = 0,
SLAVE_BUS_REQUEST = 1,
SLAVE_MODULE_WAIT_D0 = 2,
SLAVE_MODULE_WAIT_D1 = 3,
SLAVE_MODULE_WAIT_D2 = 4,
SLAVE_MODULE_WAIT_D3 = 5
} ram_states_fsm;
SC_MODULE(wb_ram_sc)
{
sc_in_clk CLK;
sc_in<bool> RESET_N;
//interface with BUS
sc_in<sc_uint<32>> DAT_I;
sc_in<sc_uint<32>> ADR_I;
sc_in<bool> CYC_I; // when asserted indicates that a valid bus cycle in progress
sc_in<sc_uint<2>> SEL_I; // select which words on DAT_O are valid
sc_in<bool> STB_I;
sc_in<bool> WE_I;
sc_out<sc_uint<32>> DAT_O;
sc_out<bool> ACK_O; // when asserted indicates the termination of a bus cycle
//interface with module
sc_in<sc_uint<32>> RAM_DT_I;
sc_out<sc_uint<32>> RAM_DT_O;
sc_out<sc_uint<32>> RAM_ADR_O;
sc_out<bool> RAM_WE_O;
sc_out<sc_uint<2>> RAM_SEL_O;
sc_out<bool> RAM_DTA_RDY_O;
//interface with BCU
sc_in<bool> ARBITER_SEL_I;
//signals
sc_signal<sc_uint<4>> current_state;
sc_signal<sc_uint<4>> future_state;
sc_signal<sc_uint<32>> ADR_REG;
sc_signal<bool> strobe;
void strobe_signal();
void new_state();
void state_transition();
void mae_output();
void trace(sc_trace_file*);
SC_CTOR(wb_ram_sc)
{
SC_METHOD(new_state);
sensitive << CLK.pos() << RESET_N;
SC_METHOD(state_transition);
sensitive << current_state << STB_I << CYC_I << ARBITER_SEL_I << WE_I;
SC_METHOD(mae_output);
sensitive << current_state << WE_I;
}
}; |
/*******************************************************************************
* e4067test.h -- Copyright 2019 (c) Glenn Ramalho - RFIDo Design
*******************************************************************************
* Description:
* This is the main testbench header for the test. It describes how
* the model should be wired up and connected to any monitors.
*******************************************************************************
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
#include <systemc.h>
#include <Arduino.h>
#include "doitesp32devkitv1.h"
#include "uartclient.h"
#include "cd4067.h"
SC_MODULE(e4067test) {
/* Signals */
sc_signal<bool> led {"led"};
gn_signal_mix d2_a12 {"d2_a12"};
gn_signal_mix rx {"rx"};
gn_signal_mix tx {"tx"};
sc_signal<unsigned int> fromwifi {"fromwifi"};
sc_signal<unsigned int> towifi {"towifi"};
gn_signal_mix a0 {"a0"};
gn_signal_mix a1 {"a1"};
gn_signal_mix a2 {"a2"};
gn_signal_mix adc {"adc"};
/* Note: these will soon be replaced with better interfaces. */
sc_signal<unsigned int> fromflash {"fromflash"};
sc_signal<unsigned int> toflash {"toflash"};
sc_signal<bool> fromi2c {"fromi2c"};
sc_signal<bool> toi2c {"toi2c"};
/* Unconnected signals */
gn_signal_mix logic_0 {"logic_0", GN_LOGIC_0};
gn_signal_mix d0 {"d0"}; gn_signal_mix d1 {"d1"};
gn_signal_mix d2 {"d2"}; gn_signal_mix d3 {"d3"};
sc_signal<bool> d0_bool {"d0_bool"}; sc_signal<bool> d1_bool {"d1_bool"};
sc_signal<bool> d2_bool {"d2_bool"}; sc_signal<bool> d3_bool {"d3_bool"};
sc_signal<bool> inh {"inh", false};
/* blocks */
doitesp32devkitv1 i_esp{"i_esp"};
uartclient i_uartclient{"i_uartclient"};
netcon_mixtobool i_netcon{"i_netcon"};
netcon_mixtobool i_netcon_s0{"i_netcon_s0"};
netcon_mixtobool i_netcon_s1{"i_netcon_s1"};
netcon_mixtobool i_netcon_s2{"i_netcon_s2"};
netcon_mixtobool i_netcon_s3{"i_netcon_s3"};
cd4067 i_cd4067{"i_cd4067"};
/* Processes */
void testbench(void);
void serflush(void);
/* Tests */
unsigned int tn; /* Testcase number */
void t0();
// Constructor
SC_CTOR(e4067test) {
/* UART 0 - we connect the wires to the corresponding tasks. Yes, the
* RX and TX need to be switched.
*/
i_esp.d3(rx); i_uartclient.tx(rx);
i_esp.d1(tx); i_uartclient.rx(tx);
/* LED */
i_esp.d2_a12(d2_a12);
i_netcon.a(d2_a12);
i_netcon.b(led);
/* We connect the waveform to these. */
/* Other interfaces, none are used so they are just left floating. */
i_esp.wrx(fromwifi); i_esp.wtx(towifi);
/* Note: these two will soon be replaced with the real flash and I2C
* interfaces, as soon as someone takes the time to implement them. */
i_esp.frx(fromflash); i_esp.ftx(toflash);
i_esp.irx(fromi2c); i_esp.itx(toi2c);
i_esp.d36_a0(adc);
i_esp.d4_a10(d0); i_esp.d5(d1); i_esp.d14_a16(d2); i_esp.d13_a14(d3);
/* CD4067 */
i_netcon_s0.a(d0); i_netcon_s0.b(d0_bool);
i_netcon_s1.a(d1); i_netcon_s1.b(d1_bool);
i_netcon_s2.a(d2); i_netcon_s2.b(d2_bool);
i_netcon_s3.a(d3); i_netcon_s3.b(d3_bool);
i_cd4067.inh(inh);
i_cd4067.channel(a0);
i_cd4067.channel(a1);
i_cd4067.channel(a2);
i_cd4067.a(d0_bool);
i_cd4067.b(d1_bool);
i_cd4067.c(d2_bool);
i_cd4067.d(d3_bool);
i_cd4067.x(adc);
/* Pins not used in this simulation */
i_esp.d0_a11(logic_0); /* BOOT pin */
i_esp.d12_a15(logic_0); i_esp.d21(logic_0);
i_esp.d26_a19(logic_0); i_esp.d27_a17(logic_0);
i_esp.d15_a13(logic_0); i_esp.d16(logic_0);
i_esp.d17(logic_0); i_esp.d18(logic_0); i_esp.d19(logic_0);
i_esp.d23(logic_0);
i_esp.d25_a18(logic_0);
i_esp.d33_a5(logic_0); i_esp.d34_a6(logic_0);
i_esp.d35_a7(logic_0); i_esp.d37_a1(logic_0);
i_esp.d38_a2(logic_0); i_esp.d39_a3(logic_0);
i_esp.d22(logic_0); i_esp.d32_a4(logic_0);
SC_THREAD(testbench);
SC_THREAD(serflush);
}
void trace(sc_trace_file *tf);
void start_of_simulation();
};
|
/// \file receiver.h
/// \brief File containing the entity of the receiver component.
///
/// See also receiver.cpp
#ifndef RECEIVER_H
#define RECEIVER_H
#include <systemc.h>
#include "NOC_package.h"
#include "RX_package.h"
/*! \class receiver
\brief SystemC description of the receiver module.
It is the receiver block of the GRLS wrapper.
*/
SC_MODULE(receiver)
//class receiver : public sc_module
{
/// Input port for datac from the transmitter
sc_in<Packet> datac;
/// Input port for the strobe from the transmitter
sc_in<sc_bit> strobe;
/// reset port
sc_in<bool> rst_n;
/// clock port
sc_in<bool> clk;
/// output port for the data to the receiver switch
sc_out<Packet> dataout;
/// analysis of the strobe and decision if to sample or not the next PC
void strobe_analysis();
/// manage the output, deciding from which FF to take the results (pos edge triggered, neg edge triggered, or synch reg)
void receiver_register();
/// evaluate when the strobe has changed the last time
void time_strobe();
/// manage the positive edge sensitive input FF
void update_P();
/// manage the negative edge sensitive input FF
void update_N();
/// manage the synchronisation register
void synch_reg_module();
/// matrix of 2 lines. In the first line i put the samples sampled on clkR edge, on the second one the ones from clkR2
bool** sample_container;
/// used to manage the output
Packet datac_container[2];
/// counter to decide which column of sample_container i'm analyzing
int actual_sample;
/// general counter
int i; //general counter
/// vector used to decide when to sample on clkR1 edge
bool* must_i_sample;
/// when strobe has changed the last time
sc_time strobelastchange;
/// manage particular case in which strobe and clkR change simultaneously
sc_time synchro_delta_cycle; //in case strobe and clkR change simultaneously, strobechange is evaluated BEFORE strobeget function
/// manage kernel
sc_event update_event_P;
/// manage kernel
sc_event update_event_N;
/// manage kernel
sc_event output_update;
/// info in reg_N
Packet save_register_N;
/// info in reg_P
Packet save_register_P;
/// info to output
Packet saved_packet;
/// info from synchreg
Packet synch_reg_out;
/// vs flag
bool vs_flag;
/// flag set in case of error
bool error_flag;
//SC_CTOR(receiver)
SC_HAS_PROCESS(receiver);
/// constructor of the transmitter
receiver(sc_module_name name_ , int N_R , int N_T, int Tsw, int Tsu) : sc_module(name_), m_N_R(N_R), m_N_T(N_T),m_Tsw(Tsw),m_Tsu(Tsu)
{
sample_container = new bool*[2];
sample_container[0] = new bool[(m_N_T*2)+1];
sample_container[1] = new bool[(m_N_T*2)+1];
must_i_sample = new bool[(m_N_T*2)+1];
SC_METHOD(receiver_register);
//sensitive<<clk.pos()<<rst_n.neg();
sensitive<<output_update<<rst_n.neg();
SC_THREAD(strobe_analysis);
sensitive<<clk<<rst_n.neg();
SC_METHOD(update_P);
sensitive<<update_event_P<<rst_n.neg(); //sensitive on clkr1
SC_METHOD(update_N);
sensitive<<update_event_N<<rst_n.neg();
SC_METHOD(synch_reg_module);
//sensitive<<clk.pos()<<rst_n.neg();
sensitive<<update_event_P<<rst_n.neg(); //sensitive on clkr1
SC_METHOD(time_strobe);
sensitive<<strobe;
dont_initialize();
}
private:
int m_N_R,m_N_T,m_Tsw,m_Tsu;
};
#endif
|
//This file is to demonstrate the use of sc_cthread
//In SC_METHOD, one iteration of a thread takes exactly one cycle of the clock if
// there is a clock in its sensitivity list
// So SC_METHODS are fine for simple sequential designs like counters (but simple RTL
// is recommended for this)
//SC_CTHREADS are not limited to 1 cycle and can contain continuous loops and complex
// control and algorithms
#ifndef FIR_H
#define FIR_H
#include <systemc.h>
SC_MODULE( fir )
{
sc_in<bool> clk;
sc_in<bool> rst;
sc_in< sc_int<16> > inp;
sc_out< sc_int<16> > outp;
sc_in<bool> inp_sig_vld;
sc_in<bool> outp_sig_rdy;
sc_out<bool> inp_sig_rdy;
sc_out<bool> outp_sig_vld;
//Just prototype this here as you have a lot to type and we don't want to
//inline the whole behavioral in this file
//this should just be ports, threads, and constructors
void fir_main(void);
SC_CTOR( fir )
{
//Takes 2 arguments
//name of the clock thread function
//edge of the clock the thread is sensitive to
SC_CTHREAD( fir_main, clk.pos() );
//Takes 2 arguments
//name of the reset input port
//polarity of the reset (true = reset is asserted high, false = reset is asserted low)
reset_signal_is( rst, true );
}
};
#endif
|
#include <string>
#include <algorithm>
#include <sstream>
#include <vector>
#include <systemc.h>
#include "sc_qt_adaptor.h"
#include "sc_config.h"
#include "sc_run.h"
#include "sc_debug_object.h"
void scQtAdaptor::trace_module (sc_module *module) {
auto children = module->get_child_objects();
sc_object * o;
for (size_t nchildren=0; nchildren < children.size(); nchildren++) {
o = children.at(nchildren);
debug_object debobj(o);
register_object(debobj);
if (debobj.isModule()) {
trace_module(dynamic_cast<sc_module *>(o));
}
}
}
void scQtAdaptor::AdaptorThread () {
sc_time ustep = sc_getMicrostep();
sc_time now;
while (sc_waitStateChange() == SC_ST_COMMAND_EXIT) {
wait();
}
hierarchy();
report(now);
sc_NotifyUIFromSC();
wait(1, SC_PS);
while (1) {
while (sc_waitStateChange() == SC_ST_COMMAND_EXIT) {
wait();
}
wait(ustep-sc_time(1, SC_PS));
now = sc_time_stamp();
wait(1, SC_PS);
report(now);
sc_NotifyUIFromSC();
}
}
void scQtAdaptor::end_of_elaboration() {
sc_simcontext* simc = simcontext();
std::vector<sc_object *> objects = sc_get_top_level_objects(simc);
sc_object * o;
if (simc != nullptr) {
for (size_t i=0; i < objects.size(); i++){
o = objects.at(i);
debug_object debobj(o);
register_object(debobj);
if (debobj.isModule()) {
trace_module(dynamic_cast<sc_module *>(o));
}
}
}
}
void scQtAdaptor::register_object(debug_object &object)
{
if (object.isHierarchy()) {
m_hierarchy_objects.push_back(object);
}
if (object.isTraceable()) {
m_traceable_objects.push_back(object);
}
}
void scQtAdaptor::report(sc_time &now)
{
std::vector<std::string> rep;
//rep.push_back(sc_time_stamp().to_string());
rep.push_back(now.to_string());
//cout << "TRACE :: @" << sc_time_stamp() << endl;
for (size_t i = 0; i < m_traceable_objects.size(); i++) {
std::string value(m_traceable_objects.at(i).report_value());
rep.push_back(value);
//cout << " " << value << endl;
}
sc_setReportFromSC(rep);
}
void scQtAdaptor::hierarchy()
{
std::vector<std::string> hier;
//cout << "HIERARCHY :: " << endl;
for (size_t i = 0; i < m_hierarchy_objects.size(); i++) {
std::string prefix;
std::string node;
std::string name(m_hierarchy_objects.at(i).name());
std::string::difference_type n = std::count(name.begin(), name.end(), '.');
prefix.append(3*n, '-');
if (m_hierarchy_objects.at(i).isModule()) {
node = " (node)";
}
hier.push_back(m_hierarchy_objects.at(i).name());
//cout << " " << prefix << name << node << endl;
}
sc_setHierarchyFromSC(hier);
}
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2019 Cadence Design Systems, Inc. All rights reserved worldwide.
//
// The code contained herein is the proprietary and confidential information
// of Cadence or its licensors, and is supplied subject to a previously
// executed license and maintenance agreement between Cadence and customer.
// This code is intended for use with Cadence high-level synthesis tools and
// may not be used with other high-level synthesis tools. Permission is only
// granted to distribute the code as indicated. Cadence grants permission for
// customer to distribute a copy of this code to any partner to aid in designing
// or verifying the customer's intellectual property, as long as such
// distribution includes a restriction of no additional distributions from the
// partner, unless the partner receives permission directly from Cadence.
//
// ALL CODE FURNISHED BY CADENCE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY
// KIND, AND CADENCE SPECIFICALLY DISCLAIMS ANY WARRANTY OF NONINFRINGEMENT,
// FITNESS FOR A PARTICULAR PURPOSE OR MERCHANTABILITY. CADENCE SHALL NOT BE
// LIABLE FOR ANY COSTS OF PROCUREMENT OF SUBSTITUTES, LOSS OF PROFITS,
// INTERRUPTION OF BUSINESS, OR FOR ANY OTHER SPECIAL, CONSEQUENTIAL OR
// INCIDENTAL DAMAGES, HOWEVER CAUSED, WHETHER FOR BREACH OF WARRANTY,
// CONTRACT, TORT, NEGLIGENCE, STRICT LIABILITY OR OTHERWISE.
//
////////////////////////////////////////////////////////////////////////////////
#ifndef SYSTEM_H
#define SYSTEM_H
// Include some required files.
#include <systemc.h> // SystemC definitions.
#include <esc.h> // Cadence ESC functions and utilities.
#include <stratus_hls.h> // Cadence Stratus definitions.
#include <cynw_p2p.h> // the cynw_p2p communication channel.
#include "defines.h"
#include "tb.h"
#include "dut_wrap.h" // use the generated wrapper for all hls_modules
SC_MODULE( System )
{
// testbench and DUT modules
dut_wrapper *m_dut; // use the generated wrapper for all hls_modules
tb *m_tb;
// clock and reset signals
sc_clock clk_sig;
sc_signal< bool > rst_sig;
// cynw_p2p channels
cynw_p2p< input_t > in_chan1; // For data going into the design
cynw_p2p< input_t > in_chan2; // For data going into the design
cynw_p2p< output_t > out_chan; // For data coming out of the design
SC_CTOR( System )
: clk_sig( "clk_sig", CLOCK_PERIOD, SC_NS )
, rst_sig( "rst_sig" )
, in_chan1( "in_chan1" )
, in_chan2( "in_chan2" )
, out_chan( "out_chan" )
{
// Connect the design module
m_dut = new dut_wrapper( "dut_wrapper" );
m_dut->clk( clk_sig );
m_dut->rst( rst_sig );
m_dut->din_1( in_chan1 );
m_dut->din_2( in_chan2 );
m_dut->dout( out_chan );
// Connect the testbench
m_tb = new tb( "tb" );
m_tb->clk( clk_sig );
m_tb->rst( rst_sig );
m_tb->dout_1( in_chan1 );
m_tb->dout_2( in_chan2 );
m_tb->din( out_chan );
}
~System()
{
delete m_tb;
delete m_dut;
}
};
#endif // SYSTEM_H
|
#ifndef SC_RST_H
#define SC_RST_H
#include <systemc.h>
#include "sc_config.h"
SC_MODULE (scRst)
{
sc_out<bool> rst_o{"rst_o"};
SC_CTOR(scRst)
{
SC_THREAD(resetThread);
}
void resetThread ()
{
sc_time ustep = sc_getMicrostep();
bool act_level = sc_getRstActLevel();
int act_usteps = sc_getRstActMicrosteps();
while(1)
{
rst_o.write(act_level);
for (int i = 0; i < act_usteps; i++)
{
wait(ustep);
}
rst_o.write(!act_level);
for (;;)
{
wait(ustep);
}
}
}
};
#endif // SC_RST_H
|
/********************************************************************************
* University of L'Aquila - HEPSYCODE Source Code License *
* *
* *
* (c) 2018-2019 Centre of Excellence DEWS All rights reserved *
********************************************************************************
* <one line to give the program's name and a brief idea of what it does.> *
* Copyright (C) 2022 Vittoriano Muttillo, Luigi Pomante * *
* *
* This program is free software: you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation, either version 3 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
********************************************************************************
* *
* Created on: 09/May/2023 *
* Authors: Vittoriano Muttillo, Marco Santic, Luigi Pomante *
* *
* email: [email protected] *
* [email protected] *
* [email protected] *
* *
********************************************************************************
* This code has been developed from an HEPSYCODE model used as demonstrator by *
* University of L'Aquila. *
*******************************************************************************/
#ifndef __STIMGEN__
#define __STIMGEN__
#include <systemc.h>
#include "datatype.h"
#include "sc_csp_channel.h"
#include "sc_csp_channel_ifs.h"
SC_MODULE(stim_gen)
{
sc_port < sc_csp_channel_out_if < stimulus_system_payload > > stimulus_system_port_out;
SC_CTOR(stim_gen)
{
SC_THREAD(main);
}
void main();
};
#endif
|
/*******************************************************************************
* ledctest.h -- Copyright 2019 (c) Glenn Ramalho - RFIDo Design
*******************************************************************************
* Description:
* This is the main testbench header for the ledc.ino test. It describes how
* the model should be wired up and connected to any monitors.
*******************************************************************************
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
#include <systemc.h>
#include <Arduino.h>
#include "doitesp32devkitv1.h"
#include "uartclient.h"
SC_MODULE(ledctest) {
/* Signals */
sc_signal<bool> led {"led"};
gn_signal_mix d2_a12 {"d2_a12"};
gn_signal_mix rx {"rx"};
gn_signal_mix tx {"tx"};
sc_signal<unsigned int> fromwifi {"fromwifi"};
sc_signal<unsigned int> towifi {"towifi"};
gn_signal_mix ledc0 {"ledc0"};
gn_signal_mix ledc1 {"ledc1"};
gn_signal_mix ledc2 {"ledc2"};
gn_signal_mix ledc3 {"ledc3"};
/* Note: these will soon be replaced with better interfaces. */
sc_signal<unsigned int> fromflash {"fromflash"};
sc_signal<unsigned int> toflash {"toflash"};
sc_signal<bool> fromi2c {"fromi2c"};
sc_signal<bool> toi2c {"toi2c"};
/* Unconnected signals */
gn_signal_mix logic_0 {"logic_0", GN_LOGIC_0};
/* blocks */
doitesp32devkitv1 i_esp{"i_esp"};
uartclient i_uartclient{"i_uartclient"};
netcon_mixtobool i_netcon{"i_netcon"};
/* Processes */
void testbench(void);
void serflush(void);
/* Tests */
unsigned int tn; /* Testcase number */
void t0();
// Constructor
SC_CTOR(ledctest) {
/* UART 0 - we connect the wires to the corresponding tasks. Yes, the
* RX and TX need to be switched.
*/
i_esp.d3(rx); i_uartclient.tx(rx);
i_esp.d1(tx); i_uartclient.rx(tx);
/* LED */
i_esp.d2_a12(d2_a12);
i_netcon.a(d2_a12);
i_netcon.b(led);
/* We connect the waveform to these. */
i_esp.d12_a15(ledc0);
i_esp.d21(ledc1);
i_esp.d26_a19(ledc2);
i_esp.d27_a17(ledc3);
/* Other interfaces, none are used so they are just left floating. */
i_esp.wrx(fromwifi); i_esp.wtx(towifi);
/* Note: these two will soon be replaced with the real flash and I2C
* interfaces, as soon as someone takes the time to implement them. */
i_esp.frx(fromflash); i_esp.ftx(toflash);
i_esp.irx(fromi2c); i_esp.itx(toi2c);
/* Pins not used in this simulation */
i_esp.d0_a11(logic_0); /* BOOT pin */
i_esp.d4_a10(logic_0); i_esp.d5(logic_0);
i_esp.d14_a16(logic_0);
i_esp.d15_a13(logic_0); i_esp.d16(logic_0);
i_esp.d17(logic_0); i_esp.d18(logic_0); i_esp.d19(logic_0);
i_esp.d23(logic_0);
i_esp.d25_a18(logic_0);
i_esp.d33_a5(logic_0); i_esp.d34_a6(logic_0);
i_esp.d35_a7(logic_0); i_esp.d36_a0(logic_0); i_esp.d37_a1(logic_0);
i_esp.d38_a2(logic_0); i_esp.d39_a3(logic_0);
i_esp.d13_a14(logic_0); i_esp.d22(logic_0); i_esp.d32_a4(logic_0);
SC_THREAD(testbench);
SC_THREAD(serflush);
}
void trace(sc_trace_file *tf);
};
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/********************************************************************************
* University of L'Aquila - HEPSYCODE Source Code License *
* *
* *
* (c) 2018-2019 Centre of Excellence DEWS All rights reserved *
********************************************************************************
* <one line to give the program's name and a brief idea of what it does.> *
* Copyright (C) 2022 Vittoriano Muttillo, Luigi Pomante * *
* *
* This program is free software: you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation, either version 3 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
********************************************************************************
* *
* Created on: 09/May/2023 *
* Authors: Vittoriano Muttillo, Marco Santic, Luigi Pomante *
* *
* email: [email protected] *
* [email protected] *
* [email protected] *
* *
********************************************************************************
* This code has been developed from an HEPSYCODE model used as demonstrator by *
* University of L'Aquila. *
*******************************************************************************/
#ifndef __DATATYPE__
#define __DATATYPE__
#include <systemc.h>
enum idEnum{EVENT_0,EVENT_A,EVENT_B};
struct stimulus_system_payload
{
idEnum Id;
sc_int<16> example;
};
struct system_display_payload
{
sc_int<8> example;
};
struct sampleTimCord_cleanData_xx_payload
{
sc_int<8> dev;
sc_int<16> step;
double ex_time;
double sample_i;
double sample_v;
};
//struct sampleTimCord_cleanData_01_payload
//{
// sc_int<8> example;
//};
//
//struct sampleTimCord_cleanData_02_payload
//{
// sc_int<8> example;
//};
//
//struct sampleTimCord_cleanData_03_payload
//{
// sc_int<8> example;
//};
//
//struct sampleTimCord_cleanData_04_payload
//{
// sc_int<8> example;
//};
struct cleanData_xx_ann_xx_payload
{
sc_int<8> dev;
sc_int<16> step;
double ex_time;
double device_i;
double device_v;
double device_t;
double device_r;
double x_0;
double x_1;
double x_2;
double fault;
};
//struct cleanData_01_ann_01_payload
//{
// sc_int<8> example;
//};
//
//struct cleanData_02_ann_02_payload
//{
// sc_int<8> example;
//};
//
//struct cleanData_03_ann_03_payload
//{
// sc_int<8> example;
//};
//
//struct cleanData_04_ann_04_payload
//{
//
//sc_int<8> example;
//
//};
struct ann_xx_dataCollector_payload
{
sc_int<8> dev;
sc_int<16> step;
double ex_time;
double device_i;
double device_v;
double device_t;
double device_r;
double x_0;
double x_1;
double x_2;
double fault;
};
//struct ann_01_dataCollector_payload
//{
// sc_int<8> example;
//};
//
//struct ann_02_dataCollector_payload
//{
// sc_int<8> example;
//};
//
//struct ann_03_dataCollector_payload
//{
// sc_int<8> example;
//};
//
//struct ann_04_dataCollector_payload
//{
// sc_int<8> example;
//};
#endif
/*
struct stim_system_payload
{
idEnum Id;
sc_uint<8> type;
void * p;
};
struct system_display_payload
{
sc_uint<8> feedback;
};
#endif
*/
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2017 Cadence Design Systems, Inc. All rights reserved worldwide.
//
// The code contained herein is the proprietary and confidential information
// of Cadence or its licensors, and is supplied subject to a previously
// executed license and maintenance agreement between Cadence and customer.
// This code is intended for use with Cadence high-level synthesis tools and
// may not be used with other high-level synthesis tools. Permission is only
// granted to distribute the code as indicated. Cadence grants permission for
// customer to distribute a copy of this code to any partner to aid in designing
// or verifying the customer's intellectual property, as long as such
// distribution includes a restriction of no additional distributions from the
// partner, unless the partner receives permission directly from Cadence.
//
// ALL CODE FURNISHED BY CADENCE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY
// KIND, AND CADENCE SPECIFICALLY DISCLAIMS ANY WARRANTY OF NONINFRINGEMENT,
// FITNESS FOR A PARTICULAR PURPOSE OR MERCHANTABILITY. CADENCE SHALL NOT BE
// LIABLE FOR ANY COSTS OF PROCUREMENT OF SUBSTITUTES, LOSS OF PROFITS,
// INTERRUPTION OF BUSINESS, OR FOR ANY OTHER SPECIAL, CONSEQUENTIAL OR
// INCIDENTAL DAMAGES, HOWEVER CAUSED, WHETHER FOR BREACH OF WARRANTY,
// CONTRACT, TORT, NEGLIGENCE, STRICT LIABILITY OR OTHERWISE.
//
////////////////////////////////////////////////////////////////////////////////
#ifndef _SYSTEM_H_
#define _SYSTEM_H_
// Include some required files.
#include <systemc.h> // SystemC definitions.
#include <esc.h> // Cadence ESC functions and utilities.
#include <stratus_hls.h> // Cadence Stratus definitions.
#include <cynw_p2p.h> // The cynw_p2p communication channel.
#include "defines.h"
#include "tb.h"
#include "dut_wrap.h" // use the generated wrapper for all hls_modules
SC_MODULE( System )
{
// clock and reset signals
sc_clock clk_sig;
sc_signal< bool > rst_sig;
// cynw_p2p channels
cynw_p2p< input_t > in_chan_1; // For data going into the design
cynw_p2p< input_t > in_chan_2; // For data going into the design
cynw_p2p< output_t > out_chan; // For data coming out of the design
// The testbench and DUT modules.
dut_wrapper *m_dut; // use the generated wrapper for the DUT hls module
tb *m_tb;
SC_CTOR( System )
: clk_sig( "clk_sig", CLOCK_PERIOD, SC_NS )
, rst_sig( "rst_sig" )
, in_chan_1( "in_chan_1" )
, in_chan_2( "in_chan_2" )
, out_chan( "out_chan" )
{
// Connect the design module
m_dut = new dut_wrapper( "dut_wrapper" );
m_dut->clk( clk_sig );
m_dut->rst( rst_sig );
m_dut->din_1( in_chan_1 );
m_dut->din_2( in_chan_2 );
m_dut->dout( out_chan );
// Connect the testbench
m_tb = new tb( "tb" );
m_tb->clk( clk_sig );
m_tb->rst( rst_sig );
m_tb->dout_1( in_chan_1 );
m_tb->dout_2( in_chan_2 );
m_tb->din( out_chan );
}
~System()
{
delete m_tb;
delete m_dut;
}
};
#endif // _SYSTEM_H_
|
/**********************************************************************
Co-Simulation of Verilated+SystemC VPI+iVerilog'
Filename: sc_fir8.h
Purpose : Core of 8-Tab Systolic FIR filter
Author : GoodKook, [email protected]
History : Mar. 2024, First release
***********************************************************************/
#ifndef _SC_FIR8_H_
#define _SC_FIR8_H_
#include <systemc.h>
#include "V_fir_pe.h" // Verilated PE
#include "fir8.h" // Filter Tab. Coeff
#define N_PE_ARRAY 7 // 7-PEs in the Array & Last PE is Verilog
SC_MODULE(sc_fir8)
{
sc_in<bool> clk;
sc_in<bool> Rdy;
sc_out<bool> Vld;
sc_in<sc_uint<4> > Xin;
sc_out<sc_uint<4> > Xout;
sc_in<sc_uint<4> > Yin;
sc_out<sc_uint<4> > Yout;
V_fir_pe* u_fir_pe[N_PE_ARRAY];
sc_signal<sc_uint<4> > X[N_PE_ARRAY-1]; // X-input
sc_signal<sc_uint<4> > Y[N_PE_ARRAY-1]; // Accumulated
sc_signal<sc_uint<6> > C[N_PE_ARRAY]; // Filter-Tabs Coeff
sc_signal<bool> Valid[N_PE_ARRAY];
sc_trace_file* fp; // VCD file
SC_CTOR(sc_fir8):
clk("clk"),
Xin("Xin"),
Xout("Xout"),
Yin("Yin"),
Yout("Yout")
{
// Instaltiate PE array
char szPeName[16];
for (int i=0; i<N_PE_ARRAY; i++)
{
sprintf(szPeName, "u_PE_%d", i);
u_fir_pe[i] = new V_fir_pe(szPeName);
C[i].write(sc_uint<8>(filter_taps[i])); // Filter Coeff.
u_fir_pe[i]->Cin(C[i]);
u_fir_pe[i]->clk(clk);
}
// 0-th PE
u_fir_pe[0]->Xin(Xin);
u_fir_pe[0]->Xout(X[0]);
u_fir_pe[0]->Yin(Yin);
u_fir_pe[0]->Yout(Y[0]);
u_fir_pe[0]->Rdy(Rdy);
u_fir_pe[0]->Vld(Valid[0]);
// Systolic Array
for (int i=1; i<N_PE_ARRAY-1; i++)
{
u_fir_pe[i]->Xin(X[i-1]);
u_fir_pe[i]->Xout(X[i]);
u_fir_pe[i]->Yin(Y[i-1]);
u_fir_pe[i]->Yout(Y[i]);
u_fir_pe[i]->Rdy(Valid[i-1]);
u_fir_pe[i]->Vld(Valid[i]);
}
// Last PE
u_fir_pe[N_PE_ARRAY-1]->Xin(X[N_PE_ARRAY-2]);
u_fir_pe[N_PE_ARRAY-1]->Xout(Xout);
u_fir_pe[N_PE_ARRAY-1]->Yin(Y[N_PE_ARRAY-2]);
u_fir_pe[N_PE_ARRAY-1]->Yout(Yout);
u_fir_pe[N_PE_ARRAY-1]->Rdy(Valid[N_PE_ARRAY-2]);
u_fir_pe[N_PE_ARRAY-1]->Vld(Vld);
// VCD Trace
fp = sc_create_vcd_trace_file("sc_fir8");
fp->set_time_unit(100, SC_PS); // resolution (trace) ps
sc_trace(fp, clk, "clk");
sc_trace(fp, Xin, "Xin");
sc_trace(fp, Xout, "Xout");
sc_trace(fp, Yin, "Yin");
sc_trace(fp, Yout, "Yout");
sc_trace(fp, Rdy, "Rdy");
sc_trace(fp, Vld, "Vld");
char szTrace[16];
for (int i=0; i<N_PE_ARRAY-1; i++)
{
sprintf(szTrace, "X_%d", i);
sc_trace(fp, X[i], szTrace);
sprintf(szTrace, "Y_%d", i);
sc_trace(fp, Y[i], szTrace);
sprintf(szTrace, "Valid_%d", i);
sc_trace(fp, Valid[i], szTrace);
}
}
~sc_fir8(void)
{
}
};
#endif
|
/******************************************************************************
* *
* Copyright (C) 2022 MachineWare GmbH *
* All Rights Reserved *
* *
* This is work is licensed under the terms described in the LICENSE file *
* found in the root directory of this source tree. *
* *
******************************************************************************/
#ifndef VCML_H
#define VCML_H
#include "vcml/core/types.h"
#include "vcml/core/version.h"
#include "vcml/core/thctl.h"
#include "vcml/core/systemc.h"
#include "vcml/core/range.h"
#include "vcml/core/fifo.h"
#include "vcml/core/peq.h"
#include "vcml/core/command.h"
#include "vcml/core/module.h"
#include "vcml/core/component.h"
#include "vcml/core/register.h"
#include "vcml/core/peripheral.h"
#include "vcml/core/processor.h"
#include "vcml/core/system.h"
#include "vcml/core/setup.h"
#include "vcml/core/model.h"
#include "vcml/logging/logger.h"
#include "vcml/logging/inscight.h"
#include "vcml/tracing/tracer.h"
#include "vcml/tracing/tracer_file.h"
#include "vcml/tracing/tracer_term.h"
#include "vcml/tracing/tracer_inscight.h"
#include "vcml/properties/property_base.h"
#include "vcml/properties/property.h"
#include "vcml/properties/broker.h"
#include "vcml/properties/broker_arg.h"
#include "vcml/properties/broker_env.h"
#include "vcml/properties/broker_file.h"
#include "vcml/properties/broker_lua.h"
#include "vcml/debugging/symtab.h"
#include "vcml/debugging/target.h"
#include "vcml/debugging/loader.h"
#include "vcml/debugging/subscriber.h"
#include "vcml/debugging/suspender.h"
#include "vcml/debugging/rspserver.h"
#include "vcml/debugging/gdbarch.h"
#include "vcml/debugging/gdbserver.h"
#include "vcml/debugging/vspserver.h"
#include "vcml/ui/keymap.h"
#include "vcml/ui/video.h"
#include "vcml/ui/display.h"
#include "vcml/ui/console.h"
#include "vcml/protocols/tlm.h"
#include "vcml/protocols/gpio.h"
#include "vcml/protocols/clk.h"
#include "vcml/protocols/spi.h"
#include "vcml/protocols/sd.h"
#include "vcml/protocols/i2c.h"
#include "vcml/protocols/pci.h"
#include "vcml/protocols/pci_ids.h"
#include "vcml/protocols/eth.h"
#include "vcml/protocols/can.h"
#include "vcml/protocols/usb.h"
#include "vcml/protocols/serial.h"
#include "vcml/protocols/virtio.h"
#include "vcml/models/generic/clock.h"
#include "vcml/models/generic/reset.h"
#include "vcml/models/generic/bus.h"
#include "vcml/models/generic/memory.h"
#include "vcml/models/generic/hwrng.h"
#include "vcml/models/generic/fbdev.h"
#include "vcml/models/gpio/gate.h"
#include "vcml/models/gpio/mmgpio.h"
#include "vcml/models/gpio/sifive.h"
#include "vcml/models/serial/backend.h"
#include "vcml/models/serial/terminal.h"
#include "vcml/models/serial/uart.h"
#include "vcml/models/serial/pl011.h"
#include "vcml/models/serial/nrf51.h"
#include "vcml/models/serial/cdns.h"
#include "vcml/models/serial/sifive.h"
#include "vcml/models/timers/rtc1742.h"
#include "vcml/models/timers/sp804.h"
#include "vcml/models/timers/nrf51.h"
#include "vcml/models/timers/pl031.h"
#include "vcml/models/block/backend.h"
#include "vcml/models/block/disk.h"
#include "vcml/models/ethernet/backend.h"
#include "vcml/models/ethernet/bridge.h"
#include "vcml/models/ethernet/network.h"
#include "vcml/models/ethernet/lan9118.h"
#include "vcml/models/ethernet/ethoc.h"
#include "vcml/models/can/backend.h"
#include "vcml/models/can/bridge.h"
#include "vcml/models/can/bus.h"
#include "vcml/models/can/m_can.h"
#include "vcml/models/i2c/lm75.h"
#include "vcml/models/i2c/oci2c.h"
#include "vcml/models/i2c/sifive.h"
#include "vcml/models/spi/bus.h"
#include "vcml/models/spi/spi2sd.h"
#include "vcml/models/spi/max31855.h"
#include "vcml/models/spi/flash.h"
#include "vcml/models/spi/ocspi.h"
#include "vcml/models/spi/sifive.h"
#include "vcml/models/sd/card.h"
#include "vcml/models/sd/sdhci.h"
#include "vcml/models/usb/xhci.h"
#include "vcml/models/usb/xhcipci.h"
#include "vcml/models/usb/device.h"
#include "vcml/models/usb/keyboard.h"
#include "vcml/models/usb/drive.h"
#include "vcml/models/usb/hostdev.h"
#include "vcml/models/pci/device.h"
#include "vcml/models/pci/host.h"
#include "vcml/models/pci/endpoint.h"
#include "vcml/models/virtio/mmio.h"
#include "vcml/models/virtio/pci.h"
#include "vcml/models/virtio/rng.h"
#include "vcml/models/virtio/blk.h"
#include "vcml/models/virtio/net.h"
#include "vcml/models/virtio/console.h"
#include "vcml/models/virtio/input.h"
#include "vcml/models/meta/loader.h"
#include "vcml/models/meta/simdev.h"
#include "vcml/models/meta/throttle.h"
#include "vcml/models/opencores/ompic.h"
#include "vcml/models/opencores/ockbd.h"
#include "vcml/models/opencores/ocfbc.h"
#include "vcml/models/dma/pl330.h"
#include "vcml/models/arm/pl190vic.h"
#include "vcml/models/arm/syscon.h"
#include "vcml/models/arm/gic400.h"
#include "vcml/models/arm/gicv2m.h"
#include "vcml/models/riscv/clint.h"
#include "vcml/models/riscv/plic.h"
#include "vcml/models/riscv/aclint.h"
#include "vcml/models/riscv/aplic.h"
#include "vcml/models/riscv/simdev.h"
#include "vcml/models/deprecated.h"
#endif
|
/// \file fifo.h
/// \brief File containing the entity of the fifo component.
///
/// See also fifo.cpp
#ifndef FIFO_H
#define FIFO_H
#include "systemc.h"
#include "NOC_package.h"
/*! \class fifo
\brief SystemC description of the fifo module.
Classical clocked fifo with asynchronous reset. The fifo takes inputs every clock period (in the inputs to the fifo have the empty bit = true).
The fifo fournishes a value to the NoC switch (output) every clock period only if the signal Resource_ready equals zero.
*/
SC_MODULE(fifo)
//class fifo : public sc_module
{
/// It is used to get input values from a file which represents the resource.
sc_in<Packet> FIFO_in;
/// reset signal
sc_in<sc_bit> rst_n;
/// Input of the resource ready signal. If the resource is ready (true) i can output values from the fifo every clock period.
sc_in<sc_bit> Resource_ready;
/// It gives packets to the switch only when the switch is ready to take a new packet (see resourceready signal).
sc_out<Packet> FIFO_out;
/// Row and column of the switch in the Network.
public:
/// Row of the switch in the Network.
int row_fifo;
/// Col of the switch in the Network.
int col_fifo;
/*! Main clocked process of the fifo module.
*/
void prc_fifo();
/// Useful to see how many elements are memorized in the fifo.
int FIFO_LastPosition;
/// Useful to see how many elements are memorized in the fifo.
struct Packet FIFO_vector[10];
/// Variable used to memorize the next output value of the fifo.
struct Packet FIFO_reg;
/// Counter for loops.
int i;
/// Clock of the fifo
sc_clock clkfifo;
/// Open a file in order to write on it.
ofstream fifofile;
/// Signal which samples the input.
struct Packet FIFO_in_s,FIFO_reg_appoggio;
/// Constructor: Initializes the fifo (all zeros) and open the fifofile to write on it.
SC_CTOR(fifo):clkfifo("clkfifo",1,SC_NS)
{
SC_METHOD(prc_fifo);
sensitive<<rst_n<<clkfifo; //is the same of having sensitive<<d<<empty
//dont_initialize();
FIFO_LastPosition=0;
for (i=0;i<10;i++)
FIFO_vector[i]=empty_NL_PDU;
FIFO_reg=empty_NL_PDU;
fifofile.open ("fifo.txt",ios::trunc);
fifofile << "SIMULATION STARTS NOW: "<<endl<<endl;
fifofile.close();
}
};
#endif
|
///////////////////////////////////////////////////////////////////////////////
///\\file RSCommon.h
///\\brief
///
/// INF8500 - Laboratoire 2
/// Automne 2009
/// par Laurent Moss (moss_AT_grm.polymtl.ca)
///
/// Modification Automne 2013
/// par Etienne Gauthier ([email protected])
///
/// (c) All Rights Reserved. Ecole Polytechnique Montreal 2008,2013
///
///
///////////////////////////////////////////////////////////////////////////////
#ifndef RSCOMMON_H_
#define RSCOMMON_H_
#include "systemc.h"
// Device configuration
const unsigned int NB_BYTE_INPUT = 16;
const unsigned int RANDOM_SEED = 123456;
// Reed-Solomon Algorythm configuration
#define mm 8 /* RS code over GF(2**mm) - change to suit */
#define n1 256 /* n = size of the field */
#define nn 255 /* nn=2**mm -1 length of codeword */
#define tt 8 /* number of errors that can be corrected */
#define kk 239 /* kk = nn-2*tt */ /* Degree of g(x) = 2*tt */
#define b0 0 /* g(x) has roots @**b0, @**(b0+1), ... ,@^(b0+2*tt-1) */
const unsigned int NB_SYMBOL_BITS = 8; // m /* RS code over GF(2**mm) - change to suit */ // GF(q) q = 2**m = 2**8 , n = q ou n = q-1
const unsigned int BLOCK_LENGTH = nn; // n = 2**m - 1 = 2**8 - 1 = 255
const unsigned int CORRECTION_CAPACITY = tt; // tt mm 8 symbole can be corrected
const unsigned int MESSAGE_LENGTH = BLOCK_LENGTH - 2 * CORRECTION_CAPACITY; // (k) message length < block length (n)
/**** Primitive polynomial ****/
// Polynome premier (ireductible) servant de base pour generer les corps de galoies GF(p^m) de degre m;
static sc_uint<1> pp[NB_SYMBOL_BITS + 1] = { 1, 0, 1, 1, 1, 0, 0, 0, 1 }; /* 1+x^2+x^3+x^4+x^8 */
#endif // RSCOMMON_H_
|
/*
* @ASCK
*/
#include <systemc.h>
SC_MODULE (ALU) {
sc_in <sc_int<8>> in1; // A
sc_in <sc_int<8>> in2; // B
sc_in <bool> c; // Carry Out // in this project, this signal is always 1
// ALUOP // has 5 bits by merging: opselect (4bits) and first LSB bit of opcode (1bit)
sc_in <sc_uint<5>> aluop;
sc_in <sc_uint<3>> sa; // Shift Amount
sc_out <sc_int<8>> out; // Output
/*
** module global variables
*/
//
SC_CTOR (ALU){
SC_METHOD (process);
sensitive << in1 << in2 << aluop;
}
void process () {
sc_int<8> a = in1.read();
sc_int<8> b = in2.read();
bool cin = c.read();
sc_uint<5> op = aluop.read();
sc_uint<3> sh = sa.read();
switch (op){
case 0b00000 :
out.write(a);
break;
case 0b00001 :
out.write(++a);
break;
case 0b00010 :
out.write(a+b);
break;
case 0b00011 :
out.write(a+b+cin);
break;
case 0b00100 :
out.write(a-b);
break;
case 0b00101 :
out.write(a-b-cin);
break;
case 0b00110 :
out.write(--a);
break;
case 0b00111 :
out.write(b);
break;
case 0b01000 :
case 0b01001 :
out.write(a&b);
break;
case 0b01010 :
case 0b01011 :
out.write(a|b);
break;
case 0b01100 :
case 0b01101 :
out.write(a^b);
break;
case 0b01110 :
case 0b01111 :
out.write(~a);
break;
case 0b10000 :
case 0b10001 :
case 0b10010 :
case 0b10011 :
case 0b10100 :
case 0b10101 :
case 0b10110 :
case 0b10111 :
out.write(a>>sh);
break;
default:
out.write(a<<sh);
break;
}
}
}; |
/**
#define meta ...
prInt32f("%s\n", meta);
**/
/*
All rights reserved to Alireza Poshtkohi (c) 1999-2023.
Email: [email protected]
Website: http://www.poshtkohi.info
*/
#ifndef __s5_h__
#define __s5_h__
#include <systemc.h>
SC_MODULE(s5)
{
sc_in<sc_uint<6> > stage1_input;
sc_out<sc_uint<4> > stage1_output;
void s5_box();
SC_CTOR(s5)
{
SC_METHOD(s5_box);
sensitive << stage1_input;
}
};
#endif
|
#ifndef _CPUIF_H
#define _CPUIF_H
#include "systemc.h"
#include "port_axis.h" // axi_tc_in, axi_tc_out
#define MAX_PORTS 2
extern axi_tc_in *s_gctl[MAX_PORTS];
extern axi_tc_out *m_gctl[MAX_PORTS];
#endif // _CPUIF_H
|
#ifndef DFT_MODULE_H_
#define DFT_MODULE_H_
#include "systemc.h"
SC_MODULE(DFTModule)
{
sc_in_clk clock;
sc_in<bool> f_Enable;
sc_in<bool> f_RxSamples;
sc_in<bool> f_Calculate;
sc_in<bool> Reset;
sc_in<int> N;
sc_in<double> Sample;
sc_out<double> OutReal;
sc_out<double> OutImg;
double* _Samples;
int _N;
int _Counter;
void DFT(void);
SC_CTOR(DFTModule)
{
SC_METHOD(DFT);
sensitive << clock.pos();
sensitive << Reset;
}
~DFTModule()
{
if(_Samples)
delete[] _Samples;
}
};
#endif
|
#ifndef SC_RST_H
#define SC_RST_H
#include <systemc.h>
#include "sc_config.h"
SC_MODULE (scRst) {
sc_out<bool> rst_o{"rst_o"};
SC_CTOR(scRst) {
SC_THREAD(resetThread);
}
void resetThread () {
sc_time ustep = sc_getMicrostep();
bool act_level = sc_getRstActLevel();
int act_usteps =sc_getRstActMicrosteps();
while (1) {
rst_o.write(act_level);
for (int i = 0; i < act_usteps; i++) {
wait(ustep);
}
rst_o.write(!act_level);
for (;;) {
wait(ustep);
}
}
}
};
#endif // SC_RST_H
|
#include "systemc.h"
#include "../cnm_base.h"
#include "../half.hpp"
using half_float::half;
SC_MODULE(fpu_monitor) {
#if MIXED_SIM
sc_in<sc_logic> clk;
sc_in<sc_logic> rst;
sc_in<sc_logic> mult_en; // Signals that a multiply computation step should be performed
sc_in<sc_logic> add_en; // Signals that an add computation step should be performed
sc_in<sc_lv<16> > srf_in; // Scalar operand from SRF
sc_in<sc_lv<16> > grfa_in1[SIMD_WIDTH]; // Input 1 from GRF_A
sc_in<sc_lv<16> > grfa_in2[SIMD_WIDTH]; // Input 2 from GRF_A
sc_in<sc_lv<16> > grfb_in1[SIMD_WIDTH]; // Input 1 from GRF_B
sc_in<sc_lv<16> > grfb_in2[SIMD_WIDTH]; // Input 2 from GRF_B
// sc_in<sc_lv<16> > even_in[SIMD_WIDTH]; // Input from EVEN_BANK
// sc_in<sc_lv<16> > odd_in[SIMD_WIDTH]; // Input from ODD_BANK
sc_in<sc_lv<8> > mult_in1_sel; // Selects input 1 for addition
sc_in<sc_lv<8> > mult_in2_sel; // Selects input 2 for multiplication
sc_in<sc_lv<8> > add_in1_sel; // Selects input 1 for addition
sc_in<sc_lv<8> > add_in2_sel; // Selects input 2 for multiplication
sc_in<sc_logic> out_sel; // Selects the output: 0 for adder output, 1 for multiplier output
sc_in<sc_lv<16> > output[SIMD_WIDTH]; // Output of the Floating Point Unit
#else
sc_in_clk clk;
sc_in<bool> rst;
sc_in<bool> mult_en; // Signals that a multiply computation step should be performed
sc_in<bool> add_en; // Signals that an add computation step should be performed
sc_in<half> srf_in; // Scalar operand from SRF
sc_in<half> grfa_in1[SIMD_WIDTH]; // Input 1 from GRF_A
sc_in<half> grfa_in2[SIMD_WIDTH]; // Input 2 from GRF_A
sc_in<half> grfb_in1[SIMD_WIDTH]; // Input 1 from GRF_B
sc_in<half> grfb_in2[SIMD_WIDTH]; // Input 2 from GRF_B
// sc_in<half> even_in[SIMD_WIDTH]; // Input from EVEN_BANK
// sc_in<half> odd_in[SIMD_WIDTH]; // Input from ODD_BANK
sc_in<uint8_t> mult_in1_sel; // Selects input 1 for addition
sc_in<uint8_t> mult_in2_sel; // Selects input 2 for multiplication
sc_in<uint8_t> add_in1_sel; // Selects input 1 for addition
sc_in<uint8_t> add_in2_sel; // Selects input 2 for multiplication
sc_in<bool> out_sel; // Selects the output: 0 for adder output, 1 for multiplier output
sc_in<half> output[SIMD_WIDTH]; // Output of the Floating Point Unit
#endif
// Internal events
sc_event_or_list output_change_evnt; // Event signaling that any of the outputs has changed
// Internal variables and signals for checking
half **mpipe;
half **apipe;
half *m1_in;
half *m2_in;
half *a1_in;
half *a2_in;
half *pred_out;
bool error;
SC_CTOR(fpu_monitor) {
SC_THREAD(monitor_thread);
sensitive << clk.pos();
SC_THREAD(mirror_thread);
sensitive << rst.neg() << clk.pos();
SC_METHOD(out_mirror_thread);
int i, j;
mpipe = new half*[MULT_STAGES];
for (i = 0; i < MULT_STAGES; i++) {
mpipe[i] = new half[SIMD_WIDTH];
for (j = 0; j < SIMD_WIDTH; j++)
mpipe[i][j] = half_float::half_cast<half>(0.0);
}
apipe = new half*[ADD_STAGES];
for (i = 0; i < ADD_STAGES; i++) {
apipe[i] = new half[SIMD_WIDTH];
for (j = 0; j < SIMD_WIDTH; j++)
apipe[i][j] = half_float::half_cast<half>(0.0);
}
m1_in = new half[SIMD_WIDTH];
m2_in = new half[SIMD_WIDTH];
a1_in = new half[SIMD_WIDTH];
a2_in = new half[SIMD_WIDTH];
pred_out = new half[SIMD_WIDTH];
for (i = 0; i < SIMD_WIDTH; i++) {
m1_in[i] = half_float::half_cast<half>(0.0);
m2_in[i] = half_float::half_cast<half>(0.0);
a1_in[i] = half_float::half_cast<half>(0.0);
a2_in[i] = half_float::half_cast<half>(0.0);
pred_out[i] = half_float::half_cast<half>(0.0);
}
error = false;
}
void end_of_elaboration() {
// creates output_change_evnt once all ports are bounded
for (int i = 0; i < SIMD_WIDTH; i++) {
output_change_evnt |= output[i]->value_changed_event();
}
}
void monitor_thread(); // Outputs the behavior for the first SIMD rail, and automatically checks the functionality
void mirror_thread(); // Mirror FPU behavior for checking its functionality
void out_mirror_thread(); // Mirror FPU output for checking functionality
};
|
#include <systemc.h>
#ifndef PRODUCER_H_
#define PRODUCER_H_
SC_MODULE(Producer){
sc_out<int> data;
int generatedNumber;
int i;
SC_CTOR(Producer){
data.initialize(42); //initialisiert den Ausgangsport mit dem angegebenen Wert (ansonsten 0)
SC_THREAD(produce);
}
void produce()
{
i = 0;
while(i < 10) {
generatedNumber = rand();
cout << "[" << sc_time_stamp() << "](" << name() << "): generated " << generatedNumber << endl;
data.write(generatedNumber);
//data = generatedNumber; //geht bei SC_SIGNAL auch
wait(SC_ZERO_TIME); //sonst kommt der Consumer nie dran
i++;
}
}
};
#endif
|
/***************************************************************
* systemc.h
*
* Includes the libraries to handle with SystemC
* codes. Also defines the sc_main function
*
* @author Luciano Sobral <[email protected]>
*
***************************************************************/
#ifndef SYSTEMC_H
#define SYSTEMC_H
/***************************************************************/
/*********************** CPP INCLUDES **************************/
/***************************************************************/
//#include <iostream>
//#include <string>
/***************************************************************/
/*********************** SYSTEMC INCLUDES **********************/
/***************************************************************/
#include "systemc/kernel/sc_module.h"
#include "systemc/kernel/sc_wait.h"
//#include "systemc/kernel/sc_sensitive.h"
#include "systemc/communication/sc_signal.h"
#include "systemc/communication/sc_signal_ports.h"
#include "systemc/communication/sc_clock.h"
#define sc_main main
#endif
|
/***************************************************************
* systemc.h
*
* Includes the libraries to handle with SystemC
* codes. Also defines the sc_main function
*
* @author Luciano Sobral <[email protected]>
*
***************************************************************/
#ifndef SYSTEMC_H
#define SYSTEMC_H
/***************************************************************/
/*********************** CPP INCLUDES **************************/
/***************************************************************/
//#include <iostream>
//#include <string>
/***************************************************************/
/*********************** SYSTEMC INCLUDES **********************/
/***************************************************************/
#include "systemc/kernel/sc_module.h"
#include "systemc/kernel/sc_wait.h"
//#include "systemc/kernel/sc_sensitive.h"
#include "systemc/communication/sc_signal.h"
#include "systemc/communication/sc_signal_ports.h"
#include "systemc/communication/sc_clock.h"
#define sc_main main
#endif
|
/***************************************************************
* systemc.h
*
* Includes the libraries to handle with SystemC
* codes. Also defines the sc_main function
*
* @author Luciano Sobral <[email protected]>
*
***************************************************************/
#ifndef SYSTEMC_H
#define SYSTEMC_H
/***************************************************************/
/*********************** CPP INCLUDES **************************/
/***************************************************************/
//#include <iostream>
//#include <string>
/***************************************************************/
/*********************** SYSTEMC INCLUDES **********************/
/***************************************************************/
#include "systemc/kernel/sc_module.h"
#include "systemc/kernel/sc_wait.h"
//#include "systemc/kernel/sc_sensitive.h"
#include "systemc/communication/sc_signal.h"
#include "systemc/communication/sc_signal_ports.h"
#include "systemc/communication/sc_clock.h"
#define sc_main main
#endif
|
/*****************************************************************************
Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
more contributor license agreements. See the NOTICE file distributed
with this work for additional information regarding copyright ownership.
Accellera licenses this file to you under the Apache License, Version 2.0
(the "License"); you may not use this file except in compliance with the
License. You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
implied. See the License for the specific language governing
permissions and limitations under the License.
*****************************************************************************/
/*****************************************************************************
sender.h - This is the interface file for the synchronous process "sender".
Original Author: Rashmi Goswami, Synopsys, Inc.
*****************************************************************************/
/*****************************************************************************
MODIFICATION LOG - modifiers, enter your name, affiliation, date and
changes you are making here.
Name, Affiliation, Date:
Description of Modification:
*****************************************************************************/
#ifndef SENDER_H_INCLUDED
#define SENDER_H_INCLUDED
#include "systemc.h"
#include "pkt.h"
struct sender: sc_module {
sc_out<pkt> pkt_out;
sc_in<sc_int<4> > source_id;
sc_in_clk CLK;
SC_CTOR(sender)
{
SC_CTHREAD(entry, CLK.pos());
}
void entry();
};
#endif // SENDER_H_INCLUDED
|
/*******************************************************************************
* encoder.cpp -- Copyright 2019 (c) Glenn Ramalho - RFIDo Design
*******************************************************************************
* Description:
* This is a testbench module to emulate a rotary quad encoder with a button.
* Two pins are provided for the encoder function and a third one handles
* the button.
*******************************************************************************
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
#include <systemc.h>
#include "encoder.h"
void encoder::press(bool pb) {
if (pb) pinC.write(GN_LOGIC_1);
else pinC.write(GN_LOGIC_Z);
}
void encoder::turnleft(int pulses, bool pressbutton) {
/* We start by raising the button, if requested. */
if (pressbutton) press(true);
/* If the last was a left turn, we need to do the direction change glitch.
* Note that if the button is pressed, we only toggle pin B. */
if (!lastwasright) {
wait(speed, SC_MS);
pinB.write(GN_LOGIC_1);
wait(speed, SC_MS);
pinB.write(GN_LOGIC_Z);
}
/* And we apply the pulses, again, watching for the button. */
wait(phase, SC_MS);
while(pulses > 0) {
wait(speed-phase, SC_MS);
pinA.write(GN_LOGIC_1);
wait(phase, SC_MS);
pinB.write(GN_LOGIC_1);
wait(speed-phase, SC_MS);
pinA.write(GN_LOGIC_Z);
if (edges == 2) wait(phase, SC_MS);
pinB.write(GN_LOGIC_Z);
if (edges != 2) wait(phase, SC_MS);
pulses = pulses - 1;
}
/* If the customer requested us to press the button with a turn, we release
* it now.
*/
if (pressbutton) {
wait(speed, SC_MS);
press(false);
}
/* And we tag that the last was a right turn as when we shift to the left
* we can have some odd behaviour.
*/
lastwasright = true;
}
void encoder::turnright(int pulses, bool pressbutton) {
/* We start by raising the button, if requested. */
if (pressbutton) press(true);
/* If the last was a right turn, we need to do the direction change glitch.
* Note that if the button is pressed, we only toggle pin A. */
if (lastwasright) {
wait(speed, SC_MS);
pinA.write(GN_LOGIC_1);
wait(speed, SC_MS);
pinB.write(GN_LOGIC_1);
wait(speed, SC_MS);
pinB.write(GN_LOGIC_Z);
wait(speed, SC_MS);
pinA.write(GN_LOGIC_Z);
}
/* And we apply the pulses, again, watching for the button. */
wait(phase, SC_MS);
while(pulses > 0) {
wait(speed-phase, SC_MS);
pinB.write(GN_LOGIC_1);
wait(phase, SC_MS);
pinA.write(GN_LOGIC_1);
wait(speed-phase, SC_MS);
pinB.write(GN_LOGIC_Z);
if (edges == 2) wait(phase, SC_MS);
pinA.write(GN_LOGIC_Z);
if (edges != 2) wait(phase, SC_MS);
pulses = pulses - 1;
}
/* If the customer requested us to press the button with a turn, we release
* it now.
*/
if (pressbutton) {
wait(speed, SC_MS);
press(false);
}
/* And we tag that the last was a left turn, so we can do the left turn to
* right turn glitch.
*/
lastwasright = false;
}
void encoder::start_of_simulation() {
pinA.write(GN_LOGIC_Z);
pinB.write(GN_LOGIC_Z);
pinC.write(GN_LOGIC_Z);
}
void encoder::trace(sc_trace_file *tf) {
sc_trace(tf, pinA, pinA.name());
sc_trace(tf, pinB, pinB.name());
sc_trace(tf, pinC, pinC.name());
}
|
#ifndef _CPU_H
#define _CPU_H
#include <malloc.h> // memalign
#include "systemc.h"
#include "port_axis.h" // axi_tc_in, axi_tc_out
#include "cpuif.h" // s_gctl, m_gctl
SC_MODULE(cpu)
{
sc_in<bool> clk;
sc_in<bool> reset;
axi_tc_in s_ctl;
axi_tc_out m_ctl;
int exitval;
void th_main()
{
if (reset.read() == RLEVEL) for (int i = 0; i < 2; i++) wait();
#if 0
printf("&s_ctl: %p\n", &s_ctl);
printf("s_gctl: %p\n", s_gctl);
// printf("sbrk(0): %p\n", sbrk(0));
{int var; printf("var: %p\n", &var);}
{void *heap = memalign(64,1024); printf("aheap: %p\n", heap);}
{void *heap = malloc(1UL<<30); printf("heap: %p\n", heap); if (heap!=NULL) free(heap);}
#endif
// &s_ctl: 0x7ffc632447e0
// s_gctl: 0x8da410
// sbrk(0): 0xb58000
// var: 0x7f5c66946d6c
// aheap: 0x7fe0dc0008c0
// heap: 0x7f5c1ffff010
int _sub_main(int argc, char *argv[]);
exitval = _sub_main(sc_argc(), (char**)sc_argv());
// cout << "Info: Application exit value: " << exitval << endl;
sc_stop();
}
SC_CTOR(cpu) :
exitval(-1)
{
// initialize global references to ports
s_gctl[0] = &s_ctl;
m_gctl[0] = &m_ctl;
#if 0
printf("&s_ctl: %p\n", &s_ctl);
printf("s_gctl: %p\n", s_gctl);
// printf("sbrk(0): %p\n", sbrk(0));
{int var; printf("var: %p\n", &var);}
{void *heap = memalign(64,1024); printf("aheap: %p\n", heap);}
{void *heap = malloc(1UL<<30); printf("heap: %p\n", heap); /*if (heap!=NULL) free(heap);*/}
#endif
// &s_ctl: 0x7ffc632447e0
// s_gctl: 0x8da410
// sbrk(0): 0xaf5000
// var: 0x7ffc63242790
// aheap: 0x10e9180
// heap: 0x7f5c672ee010
SC_THREAD(th_main);
sensitive << clk.pos();
// sensitive << s_ctl.data_chg() << s_ctl.valid_chg() << m_ctl.ready_chg();
reset_signal_is(reset, RLEVEL);
}
};
#endif // _CPU_H
|
#ifndef D_CACHE
#define D_CACHE
#include <systemc.h>
#include "buffercache.h"
#include "../../UTIL/debug_util.h"
//cache N-way associatif, write through et buffet
// taille du cache 1024
// buffer de taille 2
// 2-way => 1024/2 => 512 / 4mots => 128 lignes
// index => 7 bits
// offset => 4 mots => 2 bits
// tag => 23 bits
//communication direct avec la MP (pas de bus ni BCU)
// C: cache M: memory P: MP
//acronym_X
#define WAY_SIZE 128
typedef enum // MAE STATES
{
IDLE = 0,
WAIT_MEM = 2,
UPDT = 3
} states_fsm;
SC_MODULE(dcache)
{
sc_in_clk CLK;
sc_in<bool> RESET_N;
// interface processeur
sc_in<sc_uint<32>> DATA_ADR_SM;
sc_in<sc_uint<32>> DATA_SM;
sc_in<bool> LOAD_SM;
sc_in<bool> STORE_SM;
sc_in<bool> VALID_ADR_SM;
sc_in<sc_uint<2>> MEM_SIZE_SM;
sc_out<sc_uint<32>> DATA_SC;
sc_out<bool> STALL_SC; // if stall donc miss else hit
// interface MP
sc_out<bool> DTA_VALID_SC;
sc_out<bool> READ_SC, WRITE_SC;
sc_out<sc_uint<2>> SIZE_SC;
sc_out<sc_uint<32>> DT_SC;
sc_out<sc_uint<32>> A_SC;
sc_in<sc_uint<32>> DT_SP;
sc_in<sc_uint<32>> A_SP;
sc_in<bool> SLAVE_ACK_SP; // slave answer (slave dt valid)
//signals
//parse address from CPU
sc_signal<sc_uint<21>> address_tag;
sc_signal<sc_uint<7>> address_index;
sc_signal<sc_uint<4>> address_offset;
//parse address from MP
sc_signal<sc_uint<21>> mp_address_tag;
sc_signal<sc_uint<7>> mp_address_index;
sc_signal<sc_uint<4>> mp_address_offset;
sc_signal<sc_uint<4>> mp_last_addr_offset;
sc_signal<bool> way0_hit;
sc_signal<bool> way1_hit;
sc_signal<bool> miss;
sc_signal<sc_uint<32>> selected_data;
sc_signal<bool> current_LRU; // false: 0, true: 1
// WAYS 128 lines
sc_signal<bool> LRU_bit_check[128]; // bit to compare least recently used
// WAY 0
sc_signal<sc_uint<32>> w0_word[128][4];
sc_signal<sc_uint<21>> w0_TAG[128];
sc_signal<bool> w0_LINE_VALIDATE[128];
//WAY 1
sc_signal<sc_uint<32>> w1_word[128][4];
sc_signal<sc_uint<21>> w1_TAG[128];
sc_signal<bool> w1_LINE_VALIDATE[128];
//buffer
sc_signal<bool> write_buff, read_buff;
sc_signal<bool> full, empty;
sc_signal<sc_uint<32>> adr_sc;
sc_signal<sc_uint<32>> dt_sc;
int burst_cpt;
sc_signal<sc_uint<32>> data_mask_sc;
//FMS signal debug
sc_signal<sc_uint<3>> current_state;
sc_signal<sc_uint<3>> future_state;
void adresse_parcer();
void miss_detection();
void new_state();
void state_transition();
void mae_output();
void buffer_manager();
void trace(sc_trace_file*);
buffercache buffcache_inst;
SC_CTOR(dcache) :
buffcache_inst("buffercache")
{
SC_METHOD(adresse_parcer);
sensitive << DATA_ADR_SM << A_SP;
SC_METHOD(miss_detection);
sensitive << address_tag
<< address_index
<< address_offset
<< LOAD_SM
<< STORE_SM
<< way0_hit
<< way1_hit
<< CLK.neg();
SC_METHOD(new_state);
sensitive << CLK.neg() << RESET_N;
SC_METHOD(state_transition);
sensitive << CLK.neg() << RESET_N;
SC_METHOD(mae_output);
sensitive << CLK.neg() << RESET_N << mp_address_tag
<< mp_address_index << mp_address_offset;
reset_signal_is(RESET_N, false);
buffcache_inst.RESET_N(RESET_N);
buffcache_inst.CLK(CLK);
buffcache_inst.WRITE_OBUFF(write_buff);
buffcache_inst.READ_OBUFF(read_buff);
buffcache_inst.DATA_C(DATA_SM);
buffcache_inst.ADR_C(DATA_ADR_SM);
buffcache_inst.STORE_C(STORE_SM);
buffcache_inst.LOAD_C(LOAD_SM);
buffcache_inst.SIZE_C(MEM_SIZE_SM);
buffcache_inst.FULL(full);
buffcache_inst.EMPTY(empty);
buffcache_inst.DATA_MP(DT_SC);
buffcache_inst.ADR_MP(A_SC);
buffcache_inst.STORE_MP(WRITE_SC);
buffcache_inst.LOAD_MP(READ_SC);
buffcache_inst.SIZE_MP(SIZE_SC);
}
};
#endif |
/**
#define meta ...
prInt32f("%s\n", meta);
**/
/*
All rights reserved to Alireza Poshtkohi (c) 1999-2023.
Email: [email protected]
Website: http://www.poshtkohi.info
*/
#ifndef __des_h__
#define __des_h__
#include <systemc.h>
#include "round.h"
//S boxes
#include "s1.h"
#include "s2.h"
#include "s3.h"
#include "s4.h"
#include "s5.h"
#include "s6.h"
#include "s7.h"
#include "s8.h"
SC_MODULE(des)
{
sc_in<bool > clk;
sc_in<bool > reset;
sc_in<bool > load_i;
sc_in<bool > decrypt_i;
sc_in<sc_uint<64> > data_i;
sc_in<sc_uint<64> > key_i;
sc_out<sc_uint<64> > data_o;
sc_out<bool > ready_o;
//Registers for iteration counters
sc_signal<sc_uint<4> > stage1_iter, next_stage1_iter;
sc_signal<bool > next_ready_o;
sc_signal<sc_uint<64> > next_data_o;
sc_signal<bool > data_ready, next_data_ready;
//Conections to desround stage1
sc_signal<sc_uint<32> > stage1_L_i;
sc_signal<sc_uint<32> > stage1_R_i;
sc_signal<sc_uint<56> > stage1_round_key_i;
sc_signal<sc_uint<4> > stage1_iteration_i;
sc_signal<sc_uint<32> > stage1_R_o;
sc_signal<sc_uint<32> > stage1_L_o;
sc_signal<sc_uint<56> > stage1_round_key_o;
sc_signal<sc_uint<6> > s1_stag1_i, s2_stag1_i, s3_stag1_i, s4_stag1_i, s5_stag1_i, s6_stag1_i, s7_stag1_i, s8_stag1_i;
sc_signal<sc_uint<4> > s1_stag1_o, s2_stag1_o, s3_stag1_o, s4_stag1_o, s5_stag1_o, s6_stag1_o, s7_stag1_o, s8_stag1_o;
void des_proc();
void reg_signal();
desround *rd1;
s1 *sbox1;
s2 *sbox2;
s3 *sbox3;
s4 *sbox4;
s5 *sbox5;
s6 *sbox6;
s7 *sbox7;
s8 *sbox8;
SC_CTOR(des)
{
SC_METHOD(reg_signal);
sensitive << clk.pos();
sensitive << reset.neg();
SC_METHOD(des_proc);
sensitive << data_i << key_i << load_i << stage1_iter << data_ready;
sensitive << stage1_L_o << stage1_R_o << stage1_round_key_o;
rd1 = new desround("round1");
sbox1 = new s1("s1");
sbox2 = new s2("s2");
sbox3 = new s3("s3");
sbox4 = new s4("s4");
sbox5 = new s5("s5");
sbox6 = new s6("s6");
sbox7 = new s7("s7");
sbox8 = new s8("s8");
//For each stage in the pipe one instance
//First stage always present
rd1->clk(clk);
rd1->reset(reset);
rd1->iteration_i(stage1_iteration_i);
rd1->decrypt_i(decrypt_i);
rd1->R_i(stage1_R_i);
rd1->L_i(stage1_L_i);
rd1->Key_i(stage1_round_key_i);
rd1->R_o(stage1_R_o);
rd1->L_o(stage1_L_o);
rd1->Key_o(stage1_round_key_o);
rd1->s1_o(s1_stag1_i);
rd1->s2_o(s2_stag1_i);
rd1->s3_o(s3_stag1_i);
rd1->s4_o(s4_stag1_i);
rd1->s5_o(s5_stag1_i);
rd1->s6_o(s6_stag1_i);
rd1->s7_o(s7_stag1_i);
rd1->s8_o(s8_stag1_i);
rd1->s1_i(s1_stag1_o);
rd1->s2_i(s2_stag1_o);
rd1->s3_i(s3_stag1_o);
rd1->s4_i(s4_stag1_o);
rd1->s5_i(s5_stag1_o);
rd1->s6_i(s6_stag1_o);
rd1->s7_i(s7_stag1_o);
rd1->s8_i(s8_stag1_o);
sbox1->stage1_input(s1_stag1_i);
sbox1->stage1_output(s1_stag1_o);
sbox2->stage1_input(s2_stag1_i);
sbox2->stage1_output(s2_stag1_o);
sbox3->stage1_input(s3_stag1_i);
sbox3->stage1_output(s3_stag1_o);
sbox4->stage1_input(s4_stag1_i);
sbox4->stage1_output(s4_stag1_o);
sbox5->stage1_input(s5_stag1_i);
sbox5->stage1_output(s5_stag1_o);
sbox6->stage1_input(s6_stag1_i);
sbox6->stage1_output(s6_stag1_o);
sbox7->stage1_input(s7_stag1_i);
sbox7->stage1_output(s7_stag1_o);
sbox8->stage1_input(s8_stag1_i);
sbox8->stage1_output(s8_stag1_o);
}
};
#endif
|
/// \file wrapper_mod.h
/// \brief File containing the entity of the wrapper. It put togheter transmitter and receiver blocks;
///
/// See also wrapper_mod.cpp
#ifndef WRAPPER_H
#define WRAPPER_H
#include "systemc.h"
#include "transmitter.h"
#include "receiver.h"
#include "NOC_package.h"
/*! \class wrapper_mod
\brief SystemC description of the wrapper module (structural description).
Structural description of the wrapper. Instantiation and connection of the sub-blocks transmitter and receiver. Everything is modular.
*/
SC_MODULE(wrapper_mod)
//class wrapper_mod : public sc_module
{
private:
int m_N_left,m_N_right;
public:
///data input port of the left side of the wrapper
sc_in<Packet> L_datain;
///data output port of the left side of the wrapper
sc_out<Packet> L_dataout;
///data input port of the right side of the wrapper
sc_in<Packet> R_datain;
///data output port of the right side of the wrapper
sc_out<Packet> R_dataout;
///clock input form the switch on the left side of the wrapper
sc_in<bool> clkL;
///clock input form the switch on the right side of the wrapper
sc_in<bool> clkR;
///reset input
sc_in<bool> rst_n;
///instantiation of the transmitters sub-blocks
transmitter tx_LtoR;
///instantiation of the transmitters sub-blocks
transmitter tx_RtoL;
///instantiation of the receivers sub-blocks
receiver rx_LtoR;
///instantiation of the receivers sub-blocks
receiver rx_RtoL;
///stobe signal for the left to right couple of tx and rx
sc_signal<sc_bit> L_strobe_s;
///full signal for the left to right couple of tx and rx
sc_signal<sc_bit> L_full_s;
///stobe signal for the right to left couple of tx and rx
sc_signal<sc_bit> R_strobe_s;
///full signal for the right to left couple of tx and rx
sc_signal<sc_bit> R_full_s;
///data signal for the left to right couple of tx and rx
sc_signal<Packet> L_datac_s;
///data signal for the right to left couple of tx and rx
sc_signal<Packet> R_datac_s;
//SC_CTOR(wrapper_mod):tx_LtoR("tx_LtoR",5,3,7),tx_RtoL("tx_RtoL",3,5,7),rx_LtoR("rx_LtoR",5,3,100,25),rx_RtoL("rx_RtoL",3,5,100,25)
/// indication that we want to explicit the constructor
SC_HAS_PROCESS(wrapper_mod);
/// constructor of the wrapper
wrapper_mod(sc_module_name name_ , int N_left , int N_right) : sc_module(name_), m_N_left(N_left), m_N_right(N_right) ,tx_LtoR("tx_LtoR",m_N_left,m_N_right,7),tx_RtoL("tx_RtoL",m_N_right,m_N_left,7),rx_LtoR("rx_LtoR",m_N_left,m_N_right,100,25),rx_RtoL("rx_RtoL",m_N_right,m_N_left,100,25)
{
tx_LtoR.datain(L_datain);
tx_LtoR.rst_n(rst_n);
tx_LtoR.clk(clkL);
tx_LtoR.full(L_full_s);
tx_LtoR.datac(L_datac_s);
tx_LtoR.strobe(L_strobe_s);
rx_LtoR.datac(L_datac_s);
rx_LtoR.strobe(L_strobe_s);
rx_LtoR.clk(clkR);
rx_LtoR.rst_n(rst_n);
rx_LtoR.dataout(R_dataout);
tx_RtoL.datain(R_datain);
tx_RtoL.rst_n(rst_n);
tx_RtoL.clk(clkR);
tx_RtoL.full(R_full_s);
tx_RtoL.datac(R_datac_s);
tx_RtoL.strobe(R_strobe_s);
rx_RtoL.datac(R_datac_s);
rx_RtoL.strobe(R_strobe_s);
rx_RtoL.clk(clkL);
rx_RtoL.rst_n(rst_n);
rx_RtoL.dataout(L_dataout);
}
};
#endif
|
/*******************************************************************************
* Blinktest.h -- Copyright 2019 (c) Glenn Ramalho - RFIDo Design
*******************************************************************************
* Description:
* This is the main testbench header for the Blink.ino test. It describes how
* the model should be wired up and connected to any monitors.
*******************************************************************************
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
#include <systemc.h>
#include <Arduino.h>
#include "doitesp32devkitv1.h"
#include "uartclient.h"
SC_MODULE(Blinktest) {
/* Signals */
sc_signal<bool> led {"led"};
gn_signal_mix d2_a12 {"d2_a12"};
gn_signal_mix rx {"rx"};
gn_signal_mix tx {"tx"};
sc_signal<unsigned int> fromwifi {"fromwifi"};
sc_signal<unsigned int> towifi {"towifi"};
/* Note: these will soon be replaced with better interfaces. */
sc_signal<unsigned int> fromflash {"fromflash"};
sc_signal<unsigned int> toflash {"toflash"};
sc_signal<bool> fromi2c {"fromi2c"};
sc_signal<bool> toi2c {"toi2c"};
/* Unconnected signals */
gn_signal_mix logic_0 {"logic_0", GN_LOGIC_0};
/* blocks */
doitesp32devkitv1 i_esp{"i_esp"};
uartclient i_uartclient{"i_uartclient"};
netcon_mixtobool i_netcon{"i_netcon"};
/* Processes */
void testbench(void);
void serflush(void);
/* Tests */
unsigned int tn; /* Testcase number */
void t0();
// Constructor
SC_CTOR(Blinktest) {
/* UART 0 - we connect the wires to the corresponding tasks. Yes, the
* RX and TX need to be switched.
*/
i_esp.d3(rx); i_uartclient.tx(rx);
i_esp.d1(tx); i_uartclient.rx(tx);
/* LED */
i_esp.d2_a12(d2_a12);
i_netcon.a(d2_a12);
i_netcon.b(led);
/* Other interfaces, none are used so they are just left floating. */
i_esp.wrx(fromwifi); i_esp.wtx(towifi);
/* Note: these two will soon be replaced with the real flash and I2C
* interfaces, as soon as someone takes the time to implement them. */
i_esp.frx(fromflash); i_esp.ftx(toflash);
i_esp.irx(fromi2c); i_esp.itx(toi2c);
/* Pins not used in this simulation */
i_esp.d0_a11(logic_0); /* BOOT pin */
i_esp.d4_a10(logic_0); i_esp.d5(logic_0);
i_esp.d12_a15(logic_0); i_esp.d13_a14(logic_0); i_esp.d14_a16(logic_0);
i_esp.d15_a13(logic_0); i_esp.d16(logic_0);
i_esp.d17(logic_0); i_esp.d18(logic_0); i_esp.d19(logic_0);
i_esp.d21(logic_0); i_esp.d22(logic_0); i_esp.d23(logic_0);
i_esp.d25_a18(logic_0); i_esp.d26_a19(logic_0); i_esp.d27_a17(logic_0);
i_esp.d32_a4(logic_0); i_esp.d33_a5(logic_0); i_esp.d34_a6(logic_0);
i_esp.d35_a7(logic_0); i_esp.d36_a0(logic_0); i_esp.d37_a1(logic_0);
i_esp.d38_a2(logic_0); i_esp.d39_a3(logic_0);
SC_THREAD(testbench);
SC_THREAD(serflush);
}
void trace(sc_trace_file *tf);
};
|
#ifndef SYSC_TYPES_H
#define SYSC_TYPES_H
#include <systemc.h>
typedef struct _DATA {
sc_uint<32> data;
bool tlast;
inline friend ostream &operator<<(ostream &os, const _DATA &v) {
cout << "data: " << v.data << " tlast: " << v.tlast;
return os;
}
} DATA;
typedef struct _SDATA {
sc_int<32> data;
bool tlast;
inline friend ostream &operator<<(ostream &os, const _SDATA &v) {
cout << "data: " << v.data << " tlast: " << v.tlast;
return os;
}
} SDATA;
#endif |
/*
* ******************************************************************************
* This file includes the SystemC models of the Nangate 45 nm library cells *
* Copyright (C) 2021 University of Teheran *
* This source file may be used and distributed without restriction provided *
* that this copyright statement is not removed from the file and that any *
* derivative work contains the original copyright notice and the associated *
* disclaimer. *
* Project: QFLOW *
* Last Author : Katayoon *
* ******************************************************************************
*/
#include "systemc.h"
#ifndef __TBUF_H__
#define __TBUF_H__
/*******************************------------------TRI_BUF-----------------*******************************/
/////////////////////////////////////////////////////////////////////////////////////
// __TBUF_
/*
__________
|A EN Z|
|L L L|
|H L H|
|- H Z|
|________|
*/
SC_MODULE(__TBUF_){
sc_in< sc_logic> A;
sc_in< sc_logic> E;
sc_out< sc_logic> Y;
SC_CTOR(__TBUF_){
SC_METHOD(eval);
sensitive << A << E;
}
void eval(void){
if (E->read() == SC_LOGIC_1){
Y->write(A->read());
} else {
Y->write(SC_LOGIC_Z);
}
};
};
#endif /* __TBUF_H__ */ |
#pragma once
#include <systemc.h>
#include "../../UTIL/debug_util.h"
typedef enum // MAE STATES
{
R_IDLE = 0,
R_REQ = 1,
R_DC_READ = 2,
R_DC_END_BURST = 3,
R_DC_WRITE = 4,
R_IC = 5,
R_IC_END_BURST = 6
} river_states_fsm;
SC_MODULE(wb_river_mc)
{
sc_in_clk CLK;
sc_in<bool> RESET_N;
//interface with BUS
sc_in<sc_uint<32>> DAT_I;
sc_in<bool> ACK_I; // when asserted indicates the normal termination of a bus cycle
sc_out<sc_uint<32>> DAT_O;
sc_out<sc_uint<32>> ADR_O;
sc_out<sc_uint<2>> SEL_O; // select which words on DAT_O are valid
sc_out<bool> WE_O;
sc_out<bool> STB_O; // Master is talking on the bus
//interface with ICACHE
sc_in<sc_uint<32>> A_IC;
sc_in<bool> DTA_VALID_IC;
sc_out<sc_uint<32>> DT_IC;
sc_out<bool> ACK_IC;
//interface with DCACHE
sc_in<bool> DTA_VALID_DC;
sc_in<bool> READ_DC;
sc_in<bool> WRITE_DC;
sc_in<sc_uint<2>> SIZE_SEL_DC;
sc_in<sc_uint<32>> DT_DC;
sc_in<sc_uint<32>> A_DC;
sc_out<sc_uint<32>> DT_RM;
sc_out<bool> ACK_DC;
sc_out<bool> STALL_SW;
//interface with BCU
sc_in<bool> GRANT_I;
sc_out<bool> CYC_O;
//signals
sc_signal<sc_uint<3>> current_state;
sc_signal<sc_uint<3>> future_state;
void new_state();
void state_transition();
void mae_output();
void trace(sc_trace_file*);
SC_CTOR(wb_river_mc)
{
SC_METHOD(new_state);
sensitive << CLK.pos() << RESET_N;
SC_METHOD(state_transition);
sensitive << CLK.pos() << DTA_VALID_DC << DTA_VALID_IC
<< GRANT_I << WRITE_DC << READ_DC << ACK_I;
SC_METHOD(mae_output);
sensitive << current_state << DAT_I << ACK_I;
}
}; |
#include "systemc.h"
#include "../cnm_base.h"
SC_MODULE(id_driver) {
sc_out<bool> rst;
sc_out<bool> rf_access; // Enables rd/wr to the RFs while not in PIM mode
// sc_out<bool> rf_wr_nrd; // Signals if reading (low) or writing (high)
sc_out<bool> decode_en; // Enables decoding of the next CRF instruction
sc_out<uint8_t> pc_in; // Program Counter
sc_out<uint32_t> instr; // Instruction input from CRF
sc_out<sc_uint<ROW_BITS> > row_addr; // Address of the bank row
sc_out<sc_uint<COL_BITS> > col_addr; // Address of the bank column
SC_CTOR(id_driver) {
SC_THREAD(driver_thread);
}
void driver_thread();
};
|
// Generated by stratus_hls 17.20-p100 (88533.190925)
// Tue Nov 17 22:54:34 2020
// from dut.cc
#ifndef CYNTH_PART_dut_dut_rtl_h
#define CYNTH_PART_dut_dut_rtl_h
#include "systemc.h"
/* Include declarations of instantiated parts. */
/* Declaration of the synthesized module. */
struct dut : public sc_module {
sc_in<bool > clk;
sc_in<bool > rst;
sc_out<bool > din_busy;
sc_in<bool > din_vld;
sc_in<sc_uint<8> > din_data;
sc_in<bool > dout_busy;
sc_out<bool > dout_vld;
sc_out<sc_uint<11> > dout_data;
dut( sc_module_name name );
SC_HAS_PROCESS(dut);
sc_signal<bool > dout_m_req_m_prev_trig_req;
sc_signal<sc_uint<1> > dut_Xor_1Ux1U_1U_4_9_out1;
sc_signal<bool > dout_m_unacked_req;
sc_signal<sc_uint<1> > dut_Or_1Ux1U_1U_4_10_out1;
sc_signal<sc_uint<1> > dut_N_Muxb_1_2_0_4_1_out1;
sc_signal<sc_uint<1> > dut_And_1Ux1U_1U_4_5_out1;
sc_signal<sc_uint<1> > dut_Not_1U_1U_4_4_out1;
sc_signal<sc_uint<1> > dut_Or_1Ux1U_1U_4_2_out1;
sc_signal<bool > din_m_unvalidated_req;
sc_signal<sc_uint<1> > dut_And_1Ux1U_1U_4_3_out1;
sc_signal<sc_uint<4> > global_state_next;
sc_signal<sc_uint<8> > dut_Add_11Ux8U_11U_4_15_in1;
sc_signal<sc_uint<3> > gs_ctrl1;
sc_signal<sc_uint<11> > dut_Add_11Ux8U_11U_4_15_in2;
sc_signal<sc_uint<1> > gs_ctrl0;
sc_signal<sc_uint<8> > s_reg_25;
sc_signal<sc_uint<8> > s_reg_24;
sc_signal<sc_uint<8> > s_reg_23;
sc_signal<sc_uint<8> > s_reg_22;
sc_signal<sc_uint<8> > s_reg_21;
sc_signal<sc_uint<8> > s_reg_20;
sc_signal<sc_uint<8> > s_reg_19;
sc_signal<sc_uint<1> > dut_Not_1U_1U_4_6_out1;
sc_signal<sc_uint<1> > dut_And_1Ux1U_1U_4_11_out1;
sc_signal<sc_uint<1> > dut_Not_1U_1U_4_12_out1;
sc_signal<bool > dout_m_req_m_trig_req;
sc_signal<bool > din_m_busy_req_0;
sc_signal<sc_uint<11> > dut_Add_11Ux8U_11U_4_15_out1;
sc_signal<sc_uint<10> > dut_Add_9Ux8U_10U_4_14_out1;
sc_signal<sc_uint<9> > dut_Add_8Ux8U_9U_4_13_out1;
sc_signal<sc_uint<4> > global_state;
sc_signal<sc_uint<1> > stall0;
void drive_dout_data();
void drive_din_m_busy_req_0();
void drive_dout_m_req_m_trig_req();
void drive_stall0();
void drive_s_reg_19();
void drive_s_reg_20();
void drive_s_reg_21();
void drive_s_reg_22();
void drive_s_reg_23();
void drive_s_reg_24();
void drive_s_reg_25();
void dut_Add_8Ux8U_9U_4_13();
void dut_Add_9Ux8U_10U_4_14();
void drive_dut_Add_11Ux8U_11U_4_15_in2();
void drive_dut_Add_11Ux8U_11U_4_15_in1();
void dut_Add_11Ux8U_11U_4_15();
void drive_global_state();
void drive_global_state_next();
void drive_gs_ctrl0();
void drive_gs_ctrl1();
void drive_din_busy();
void dut_Or_1Ux1U_1U_4_2();
void dut_And_1Ux1U_1U_4_3();
void dut_Not_1U_1U_4_4();
void dut_And_1Ux1U_1U_4_5();
void dut_Not_1U_1U_4_6();
void drive_din_m_unvalidated_req();
void dut_N_Muxb_1_2_0_4_1();
void drive_dout_vld();
void dut_Or_1Ux1U_1U_4_10();
void drive_dout_m_unacked_req();
void dut_And_1Ux1U_1U_4_11();
void dut_Xor_1Ux1U_1U_4_9();
void drive_dout_m_req_m_prev_trig_req();
void dut_Not_1U_1U_4_12();
};
#endif
|
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