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#pragma once
#include <systemc.h>
#include "constants.h"
#include "debug_util.h"
SC_MODULE(reg) {
// Reading Port :
sc_in<sc_uint<6>> RADR1_SD;
sc_in<sc_uint<6>> RADR2_SD;
sc_out<sc_uint<32>> RDATA1_SR;
sc_out<sc_uint<32>> RDATA2_SR;
// Writing Port :
sc_in<sc_uint<6>> WADR_SW;
sc_in<bool> WENABLE_SW;
sc_in<sc_uint<32>> WDATA_SW;
sc_in<sc_uint<32>> WRITE_PC_SD;
sc_in<bool> WRITE_PC_ENABLE_SD;
// PC Gestion :
sc_out<sc_uint<32>> READ_PC_SR;
// Global Interface :
sc_in_clk CLK;
sc_in<bool> RESET;
// Registres :
sc_signal<sc_uint<32>> REG_RR[32];
sc_signal<sc_uint<32>> PC_RR;
void read();
void write();
void trace(sc_trace_file * tf);
SC_CTOR(reg) {
SC_METHOD(read);
sensitive << RADR1_SD << RADR2_SD << RESET << PC_RR;
for (int i = 0; i < 32; i++)
sensitive << REG_RR[i];
SC_CTHREAD(write, reg::CLK.pos());
reset_signal_is(RESET, false);
}
}; |
// ================================================================
// NVDLA Open Source Project
//
// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
// NVDLA Open Hardware License; Check "LICENSE" which comes with
// this distribution for more information.
// ================================================================
// File Name: nvdla_container_number_8_bit_width_32_iface.h
#if !defined(_nvdla_container_number_8_bit_width_32_iface_H_)
#define _nvdla_container_number_8_bit_width_32_iface_H_
#include <systemc.h>
#include <stdint.h>
typedef struct nvdla_container_number_8_bit_width_32_s {
uint8_t mask ;
sc_uint<32> data [8];
uint8_t last ;
} nvdla_container_number_8_bit_width_32_t;
#endif // !defined(_nvdla_container_number_8_bit_width_32_iface_H_)
|
/*****************************************************************************
Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
more contributor license agreements. See the NOTICE file distributed
with this work for additional information regarding copyright ownership.
Accellera licenses this file to you under the Apache License, Version 2.0
(the "License"); you may not use this file except in compliance with the
License. You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
implied. See the License for the specific language governing
permissions and limitations under the License.
*****************************************************************************/
/*****************************************************************************
fir_top.h --
Original Author: Rocco Jonack, Synopsys, Inc.
*****************************************************************************/
/*****************************************************************************
MODIFICATION LOG - modifiers, enter your name, affiliation, date and
changes you are making here.
Name, Affiliation, Date:
Description of Modification:
*****************************************************************************/
#include <systemc.h>
#include "fir_fsm.h"
#include "fir_data.h"
SC_MODULE(fir_top) {
sc_in<bool> CLK;
sc_in<bool> RESET;
sc_in<bool> IN_VALID;
sc_in<int> SAMPLE;
sc_out<bool> OUTPUT_DATA_READY;
sc_out<int> RESULT;
sc_signal<unsigned> state_out;
fir_fsm *fir_fsm1;
fir_data *fir_data1;
SC_CTOR(fir_top) {
fir_fsm1 = new fir_fsm("FirFSM");
fir_fsm1->clock(CLK);
fir_fsm1->reset(RESET);
fir_fsm1->in_valid(IN_VALID);
fir_fsm1->state_out(state_out);
fir_data1 = new fir_data("FirData");
fir_data1 -> reset(RESET);
fir_data1 -> state_out(state_out);
fir_data1 -> sample(SAMPLE);
fir_data1 -> result(RESULT);
fir_data1 -> output_data_ready(OUTPUT_DATA_READY);
}
};
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2017 Cadence Design Systems, Inc. All rights reserved worldwide.
//
// The code contained herein is the proprietary and confidential information
// of Cadence or its licensors, and is supplied subject to a previously
// executed license and maintenance agreement between Cadence and customer.
// This code is intended for use with Cadence high-level synthesis tools and
// may not be used with other high-level synthesis tools. Permission is only
// granted to distribute the code as indicated. Cadence grants permission for
// customer to distribute a copy of this code to any partner to aid in designing
// or verifying the customer's intellectual property, as long as such
// distribution includes a restriction of no additional distributions from the
// partner, unless the partner receives permission directly from Cadence.
//
// ALL CODE FURNISHED BY CADENCE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY
// KIND, AND CADENCE SPECIFICALLY DISCLAIMS ANY WARRANTY OF NONINFRINGEMENT,
// FITNESS FOR A PARTICULAR PURPOSE OR MERCHANTABILITY. CADENCE SHALL NOT BE
// LIABLE FOR ANY COSTS OF PROCUREMENT OF SUBSTITUTES, LOSS OF PROFITS,
// INTERRUPTION OF BUSINESS, OR FOR ANY OTHER SPECIAL, CONSEQUENTIAL OR
// INCIDENTAL DAMAGES, HOWEVER CAUSED, WHETHER FOR BREACH OF WARRANTY,
// CONTRACT, TORT, NEGLIGENCE, STRICT LIABILITY OR OTHERWISE.
//
////////////////////////////////////////////////////////////////////////////////
#ifndef DUT_H
#define DUT_H
/* This file defines the module "dut", which is synthesizable. It is
instantiated in the top-level module System (see system.h). */
#include <systemc.h> /* SystemC definitions. */
#include <esc.h> /* Cadence ESC functions and utilities. */
#include <stratus_hls.h> /* Cadence Stratus definitions. */
#include <cynw_p2p.h> /* The cynw_p2p communication channel. */
#include "stream_16X8.h" /* Generated stream interface classes */
#include "defines.h" /* definitions common to the TB and DUT. */
#include "directives.h" /* Synthesis directives. */
SC_MODULE( dut )
{
sc_in_clk clk;
sc_in< bool > rst;
cynw_p2p< input_data, ioConfig >::in in;
cynw_p2p< output_data, ioConfig >::out out;
stream_16X8::in<ioConfig> streamin;
stream_16X8::out<ioConfig> streamout;
SC_CTOR( dut )
: clk( "clk" )
, rst( "rst" )
, in( "in" )
, out( "out" )
, streamin( "streamin" )
, streamout( "streamout" )
{
SC_CTHREAD( thread1, clk.pos() );
reset_signal_is( rst, false );
in.clk_rst( clk, rst );
out.clk_rst( clk, rst );
streamin.clk_rst( clk, rst );
streamout.clk_rst( clk, rst );
}
sc_uint<8> x[8];
sc_uint<8> y[4];
sc_uint<8> data[16];
void thread1();
};
#endif /* DUT_H */
|
/**********************************************************************
Filename: sc_fir_pe.h
Purpose : Verilated PE of Systolic FIR filter
Author : [email protected]
History : Mar. 2024, First release
***********************************************************************/
#ifndef _V_FIR_PE_H_
#define _V_FIR_PE_H_
#include <systemc.h>
#include "./obj_dir/Vfir_pe.h"
SC_MODULE(V_fir_pe)
{
sc_in<bool> clk;
sc_in<bool> Rdy;
sc_out<bool> Vld;
sc_in<sc_uint<6> > Cin;
sc_in<sc_uint<4> > Xin;
sc_out<sc_uint<4> > Xout;
sc_in<sc_uint<4> > Yin;
sc_out<sc_uint<4> > Yout;
Vfir_pe* u_Vfir_pe;
sc_signal<uint32_t> _Cin;
sc_signal<uint32_t> _Xin;
sc_signal<uint32_t> _Xout;
sc_signal<uint32_t> _Yin;
sc_signal<uint32_t> _Yout;
sc_signal<bool> _Rdy;
sc_signal<bool> _Vld;
void pe_method(void)
{
_Cin = (uint32_t)Cin.read();
_Xin = (uint32_t)Xin.read();
_Yin = (uint32_t)Yin.read();
_Rdy = Rdy.read();
Xout.write(sc_uint<4>(_Xout));
Yout.write(sc_uint<4>(_Yout));
Vld.write(_Vld);
}
SC_CTOR(V_fir_pe):
clk("clk"),
Rdy("Rdy"), _Rdy("_Rdy"),
Vld("Vld"), _Vld("_Vld"),
Cin("Cin"), _Cin("_Cin"),
Xin("Xin"), _Xin("_Xin"),
Xout("Xout"), _Xout("_Xout"),
Yin("Yin"), _Yin("_Yin"),
Yout("Yout"), _Yout("_Yout")
{
SC_METHOD(pe_method);
sensitive << clk << Cin << Xin << Yin << Rdy;
// Instantiate Verilated PE
u_Vfir_pe = new Vfir_pe("u_Vfir_pe");
u_Vfir_pe->clk(clk);
u_Vfir_pe->Cin(_Cin);
u_Vfir_pe->Xin(_Xin);
u_Vfir_pe->Xout(_Xout);
u_Vfir_pe->Yin(_Yin);
u_Vfir_pe->Yout(_Yout);
u_Vfir_pe->Rdy(_Rdy);
u_Vfir_pe->Vld(_Vld);
}
~V_fir_pe(void)
{
}
};
#endif
|
#include <systemc.h>
#ifndef ACC_H
#define ACC_H
//#define __SYNTHESIS__
//#define SYSC_ACC_DEBUG
//#define SYSC_ACC_DEBUG2
#ifndef __SYNTHESIS__
#define DWAIT(x) wait(x)
#else
#define DWAIT(x)
#endif
#define ACCNAME SA_INT8_V1_0
#define ACC_DTYPE sc_int
#define ACC_C_DTYPE int
#define MAX 2147483647
#define MIN -2147483648
#define POS 1073741824
#define NEG -1073741823
#define DIVMAX 2147483648
#define MAX8 127
#define MIN8 -128
typedef struct _DATA{
ACC_DTYPE<32> data;
bool tlast;
inline friend ostream& operator << (ostream& os, const _DATA &v){
cout << "data: " << v.data << " tlast: " << v.tlast;
return os;
}
} DATA;
typedef struct _HDATA{
bool rhs_take;
bool lhs_take;
sc_uint<8> rhs_count;
sc_uint<8> lhs_count;
sc_uint<16> dst_addr;
} HDATA;
typedef struct _ADATA{
ACC_DTYPE<32> d2;
ACC_DTYPE<32> d3;
ACC_DTYPE<32> d4;
ACC_DTYPE<32> d5;
ACC_DTYPE<32> d6;
ACC_DTYPE<32> d7;
ACC_DTYPE<32> d8;
ACC_DTYPE<32> d9;
ACC_DTYPE<32> d10;
ACC_DTYPE<32> d11;
ACC_DTYPE<32> d12;
ACC_DTYPE<32> d13;
ACC_DTYPE<32> d14;
ACC_DTYPE<32> d15;
ACC_DTYPE<32> d16;
ACC_DTYPE<32> d17;
inline friend ostream& operator << (ostream& os, const _ADATA &v){
return os;
}
} ADATA;
SC_MODULE(ACCNAME) {
//debug vars
bool print_po = false;
bool print_wo = false;
int simplecounter=0;
ACC_DTYPE<14> depth;
sc_in<bool> clock;
sc_in <bool> reset;
sc_fifo_in<DATA> din1;
sc_fifo_in<DATA> din2;
sc_fifo_in<DATA> din3;
sc_fifo_in<DATA> din4;
sc_fifo_out<DATA> dout1;
sc_fifo_out<DATA> dout2;
sc_fifo_out<DATA> dout3;
sc_fifo_out<DATA> dout4;
sc_signal<bool> read_inputs;
sc_signal<bool> rtake;
sc_signal<bool> ltake;
sc_signal<int> llen;
sc_signal<int> rlen;
sc_signal<int> lhs_block_max;
sc_signal<int> rhs_block_max;
#ifndef __SYNTHESIS__
sc_signal<bool,SC_MANY_WRITERS> d_in1;
sc_signal<bool,SC_MANY_WRITERS> d_in2;
sc_signal<bool,SC_MANY_WRITERS> d_in3;
sc_signal<bool,SC_MANY_WRITERS> d_in4;
sc_signal<bool,SC_MANY_WRITERS> schedule;
sc_signal<bool,SC_MANY_WRITERS> out_check;
sc_signal<bool,SC_MANY_WRITERS> gemm_unit_1_ready;
sc_signal<bool,SC_MANY_WRITERS> write1;
sc_signal<bool,SC_MANY_WRITERS> arrange1;
#else
sc_signal<bool> d_in1;
sc_signal<bool> d_in2;
sc_signal<bool> d_in3;
sc_signal<bool> d_in4;
sc_signal<bool> schedule;
sc_signal<bool> out_check;
sc_signal<bool> gemm_unit_1_ready;
sc_signal<bool> write1;
sc_signal<bool> arrange1;
#endif
sc_signal<int> gemm_unit_1_l_pointer;
sc_signal<bool> gemm_unit_1_iwuse;
ACC_DTYPE<32> g1 [256];
ACC_DTYPE<8> r1 [256];
//GEMM 1 Inputs
ACC_DTYPE<32> lhsdata1a[4096];
ACC_DTYPE<32> lhsdata2a[4096];
ACC_DTYPE<32> lhsdata3a[4096];
ACC_DTYPE<32> lhsdata4a[4096];
//Global Weights
ACC_DTYPE<32> rhsdata1[8192];
ACC_DTYPE<32> rhsdata2[8192];
ACC_DTYPE<32> rhsdata3[8192];
ACC_DTYPE<32> rhsdata4[8192];
// //new sums bram
// ACC_DTYPE<32> lhs_sum1[512];
// ACC_DTYPE<32> lhs_sum2[512];
// ACC_DTYPE<32> lhs_sum3[512];
// ACC_DTYPE<32> lhs_sum4[512];
//
// ACC_DTYPE<32> rhs_sum1[512];
// ACC_DTYPE<32> rhs_sum2[512];
// ACC_DTYPE<32> rhs_sum3[512];
// ACC_DTYPE<32> rhs_sum4[512];
//
// //crf & crx
// ACC_DTYPE<32> crf1[512];
// ACC_DTYPE<32> crf2[512];
// ACC_DTYPE<32> crf3[512];
// ACC_DTYPE<32> crf4[512];
// ACC_DTYPE<32> crx[512];
//new sums bram
ACC_DTYPE<32> lhs_sum1[1024];
ACC_DTYPE<32> lhs_sum2[1024];
ACC_DTYPE<32> lhs_sum3[1024];
ACC_DTYPE<32> lhs_sum4[1024];
ACC_DTYPE<32> rhs_sum1[1024];
ACC_DTYPE<32> rhs_sum2[1024];
ACC_DTYPE<32> rhs_sum3[1024];
ACC_DTYPE<32> rhs_sum4[1024];
//crf & crx
ACC_DTYPE<32> crf1[1024];
ACC_DTYPE<32> crf2[1024];
ACC_DTYPE<32> crf3[1024];
ACC_DTYPE<32> crf4[1024];
ACC_DTYPE<32> crx[1024];
int ra=0;
sc_fifo<int> WRQ1;
sc_fifo<int> WRQ2;
sc_fifo<int> WRQ3;
sc_fifo<char> sIs1;
sc_fifo<char> sIs2;
sc_fifo<char> sIs3;
sc_fifo<char> sIs4;
sc_fifo<char> sIs5;
sc_fifo<char> sIs6;
sc_fifo<char> sIs7;
sc_fifo<char> sIs8;
sc_fifo<char> sIs9;
sc_fifo<char> sIs10;
sc_fifo<char> sIs11;
sc_fifo<char> sIs12;
sc_fifo<char> sIs13;
sc_fifo<char> sIs14;
sc_fifo<char> sIs15;
sc_fifo<char> sIs16;
sc_fifo<char> sWs1;
sc_fifo<char> sWs2;
sc_fifo<char> sWs3;
sc_fifo<char> sWs4;
sc_fifo<char> sWs5;
sc_fifo<char> sWs6;
sc_fifo<char> sWs7;
sc_fifo<char> sWs8;
sc_fifo<char> sWs9;
sc_fifo<char> sWs10;
sc_fifo<char> sWs11;
sc_fifo<char> sWs12;
sc_fifo<char> sWs13;
sc_fifo<char> sWs14;
sc_fifo<char> sWs15;
sc_fifo<char> sWs16;
sc_signal<int> w1S;
sc_signal<int> w2S;
sc_signal<int> w3S;
sc_signal<int> w4S;
#ifndef __SYNTHESIS__
int weight_max_index=0;
int input_max_index=0;
int local_weight_max_index=0;
int g1_macs=0;
int g2_macs=0;
int g3_macs=0;
int g4_macs=0;
int g1_out_count=0;
int g2_out_count=0;
int g3_out_count=0;
int g4_out_count=0;
#endif
sc_out<int> inS;
sc_out<int> read_cycle_count;
sc_out<int> process_cycle_count;
sc_out<int> gemm_1_idle;
sc_out<int> gemm_2_idle;
sc_out<int> gemm_3_idle;
sc_out<int> gemm_4_idle;
sc_out<int> gemm_1_write;
sc_out<int> gemm_2_write;
sc_out<int> gemm_3_write;
sc_out<int> gemm_4_write;
sc_out<int> gemm_1;
sc_out<int> gemm_2;
sc_out<int> gemm_3;
sc_out<int> gemm_4;
sc_out<int> wstall_1;
sc_out<int> wstall_2;
sc_out<int> wstall_3;
sc_out<int> wstall_4;
sc_out<int> rmax;
sc_out<int> lmax;
sc_out<int> outS;
sc_out<int> w1SS;
sc_out<int> w2SS;
sc_out<int> w3SS;
sc_out<int> w4SS;
sc_out<int> schS;
sc_out<int> p1S;
void Input_Handler();
void Output_Handler();
void Worker1();
void Data_In1();
void Data_In2();
void Data_In3();
void Data_In4();
void Tracker();
void Scheduler();
void Post1();
void schedule_gemm_unit(int, int, int, int, int,int,int);
int SHR(int,int);
void Read_Cycle_Counter();
void Process_Cycle_Counter();
void Writer_Cycle_Counter();
SC_HAS_PROCESS(ACCNAME);
// Parameters for the DUT
ACCNAME(sc_module_name name_) :sc_module(name_),WRQ1(512),sIs1(2048),sIs2(2048),sIs3(2048),sIs4(2048),sIs5(2048),sIs6(2048),sIs7(2048),sIs8(2048),
sIs9(2048),sIs10(2048),sIs11(2048),sIs12(2048),sIs13(2048),sIs14(2048),sIs15(2048),sIs16(2048),
WRQ2(512),sWs1(2048),sWs2(2048),sWs3(2048),sWs4(2048),sWs5(2048),sWs6(2048),sWs7(2048),sWs8(2048),
sWs9(2048),sWs10(2048),sWs11(2048),sWs12(2048),sWs13(2048),sWs14(2048),sWs15(2048),sWs16(2048),WRQ3(512){
SC_CTHREAD(Input_Handler,clock.pos());
reset_signal_is(reset,true);
SC_CTHREAD(Worker1,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Output_Handler,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Data_In1,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Data_In2,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Data_In3,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Data_In4,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Scheduler,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Post1,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Read_Cycle_Counter,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Process_Cycle_Counter,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Writer_Cycle_Counter,clock);
reset_signal_is(reset,true);
#pragma HLS RESOURCE variable=din1 core=AXI4Stream metadata="-bus_bundle S_AXIS_DATA1" port_map={{din1_0 TDATA} {din1_1 TLAST}}
#pragma HLS RESOURCE variable=din2 core=AXI4Stream metadata="-bus_bundle S_AXIS_DATA2" port_map={{din2_0 TDATA} {din2_1 TLAST}}
#pragma HLS RESOURCE variable=din3 core=AXI4Stream metadata="-bus_bundle S_AXIS_DATA3" port_map={{din3_0 TDATA} {din3_1 TLAST}}
#pragma HLS RESOURCE variable=din4 core=AXI4Stream metadata="-bus_bundle S_AXIS_DATA4" port_map={{din4_0 TDATA} {din4_1 TLAST}}
#pragma HLS RESOURCE variable=dout1 core=AXI4Stream metadata="-bus_bundle M_AXIS_DATA1" port_map={{dout1_0 TDATA} {dout1_1 TLAST}}
#pragma HLS RESOURCE variable=dout2 core=AXI4Stream metadata="-bus_bundle M_AXIS_DATA2" port_map={{dout2_0 TDATA} {dout2_1 TLAST}}
#pragma HLS RESOURCE variable=dout3 core=AXI4Stream metadata="-bus_bundle M_AXIS_DATA3" port_map={{dout3_0 TDATA} {dout3_1 TLAST}}
#pragma HLS RESOURCE variable=dout4 core=AXI4Stream metadata="-bus_bundle M_AXIS_DATA4" port_map={{dout4_0 TDATA} {dout4_1 TLAST}}
#pragma HLS array_partition variable=g1 complete dim=0
#pragma HLS RESET variable=reset
}
};
#endif /* ACC_H */
|
// Shows the non-blocking transport interface with the generic payload and sockets
// Shows nb_transport being called on the forward and backward paths
// No support for temporal decoupling
// No support for DMI or debug transport interfaces
#include <systemc.h>
using namespace sc_core;
using namespace sc_dt;
using namespace std;
#include "tlm.h"
#include "tlm_utils/simple_initiator_socket.h"
#include "tlm_utils/simple_target_socket.h"
#include "tlm_utils/peq_with_cb_and_phase.h"
// User-defined extension class
struct ID_extension: tlm::tlm_extension<ID_extension> {
ID_extension() : transaction_id(0) {}
virtual tlm_extension_base* clone() const { // Must override pure virtual clone method
ID_extension* t = new ID_extension;
t->transaction_id = this->transaction_id;
return t;
}
// Must override pure virtual copy_from method
virtual void copy_from(tlm_extension_base const &ext) {
transaction_id = static_cast<ID_extension const &>(ext).transaction_id;
}
unsigned int transaction_id;
};
// Initiator module generating generic payload transactions
struct Initiator: sc_module
{
// TLM2 socket, defaults to 32-bits wide, generic payload, generic DMI mode
sc_core::sc_in<bool> IO_request;
tlm_utils::simple_initiator_socket<Initiator> socket;
SC_HAS_PROCESS(Initiator);
Initiator(sc_module_name initiator) // Construct and name socket
{
// Register callbacks for incoming interface method calls
socket.register_nb_transport_bw(this, &Initiator::nb_transport_bw);
SC_THREAD(thread_process);
}
void thread_process()
{
while (true) {
// TLM2 generic payload transaction
tlm::tlm_generic_payload trans;
ID_extension* id_extension = new ID_extension;
//trans.set_extension( id_extension ); // Add the extension to the transaction
trans.set_extension( id_extension ); // Add the extension to the transaction
// Generate a random sequence of reads and writes
//for (int i = 0; i < 100; i++)
//printf("%i",IO_request->read());
cout << "TLM Z value:" <<IO_request->read() << endl;
if(IO_request->read() == 1)
{
int i = rand()%100;
tlm::tlm_phase phase = tlm::BEGIN_REQ;
sc_time delay = sc_time(10, SC_NS);
tlm::tlm_command cmd = static_cast<tlm::tlm_command>(rand() % 2);
trans.set_command( cmd );
trans.set_address( rand() % 0xFF );
if (cmd == tlm::TLM_WRITE_COMMAND) data = 0xFF000000 | i;
trans.set_data_ptr( reinterpret_cast<unsigned char*>(&data) );
trans.set_data_length( 4 );
// Other fields default: byte enable = 0, streaming width = 0, DMI_hint = false, no extensions
//Delay for BEGIN_REQ
wait(10, SC_NS);
tlm::tlm_sync_enum status;
cout << name() << " BEGIN_REQ SENT" << " TRANS ID " << id_extension->transaction_id << " at time " << sc_time_stamp() << endl;
status = socket->nb_transport_fw( trans, phase, delay ); // Non-blocking transport call
// Check value returned from nb_transport
switch (status)
{
case tlm::TLM_ACCEPTED:
//Delay for END_REQ
wait(10, SC_NS);
cout << name() << " END_REQ SENT" << " TRANS ID " << id_extension->transaction_id << " at time " << sc_time_stamp() << endl;
// Expect response on the backward path
phase = tlm::END_REQ;
status = socket->nb_transport_fw( trans, phase, delay ); // Non-blocking transport call
break;
case tlm::TLM_UPDATED:
case tlm::TLM_COMPLETED:
// Initiator obliged to check response status
if (trans.is_response_error() )
SC_REPORT_ERROR("TLM2", "Response error from nb_transport_fw");
cout << "trans/fw = { " << (cmd ? 'W' : 'R') << ", " << hex << i << " } , data = "
<< hex << data << " at time " << sc_time_stamp() << ", delay = " << delay << endl;
break;
}
while(IO_request==1){
wait(10,SC_NS);
}
id_extension->transaction_id++;
}
wait(10,SC_NS);
}
}
// *********************************************
// TLM2 backward path non-blocking transport method
// *********************************************
virtual tlm::tlm_sync_enum nb_transport_bw( tlm::tlm_generic_payload& trans,
tlm::tlm_phase& phase, sc_time& delay )
{
tlm::tlm_command cmd = trans.get_command();
sc_dt::uint64 adr = trans.get_address();
ID_extension* id_extension = new ID_extension;
trans.get_extension( id_extension );
if (phase == tlm::END_RESP) {
//Delay for TLM_COMPLETE
wait(delay);
cout << name() << " END_RESP RECEIVED" << " TRANS ID " << id_extension->transaction_id << " at time " << sc_time_stamp() << endl;
return tlm::TLM_COMPLETED;
}
if (phase == tlm::BEGIN_RESP) {
// Initiator obliged to check response status
if (trans.is_response_error() )
SC_REPORT_ERROR("TLM2", "Response error from nb_transport");
cout << "trans/bw = { " << (cmd ? 'W' : 'R') << ", " << hex << adr
<< " } , data = " << hex << data << " at time " << sc_time_stamp()
<< ", delay = " << delay << endl;
//Delay
wait(delay);
cout << name () << " BEGIN_RESP RECEIVED" << " TRANS ID " << id_extension->transaction_id << " at time " << sc_time_stamp() << endl;
return tlm::TLM_ACCEPTED;
}
}
// Internal data buffer used by initiator with generic payload
int data;
};
// Target module representing a simple memory
struct Memory: sc_module
{
// TLM-2 socket, defaults to 32-bits wide, base protocol
tlm_utils::simple_target_socket<Memory> socket;
enum { SIZE = 256 };
const sc_time LATENCY;
SC_CTOR(Memory)
: socket("socket"), LATENCY(10, SC_NS)
{
// Register callbacks for incoming interface method calls
socket.register_nb_transport_fw(this, &Memory::nb_transport_fw);
//socket.register_nb_transport_bw(this, &Memory::nb_transport_bw);
// Initialize memory with random data
for (int i = 0; i < SIZE; i++)
mem[i] = 0xAA000000 | (rand() % 256);
SC_THREAD(thread_process);
}
// TLM2 non-blocking transport method
virtual tlm::tlm_sync_enum nb_transport_fw( tlm::tlm_generic_payload& trans,
tlm::tlm_phase& phase, sc_time& delay )
{
sc_dt::uint64 adr = trans.get_address();
unsigned int len = trans.get_data_length();
unsigned char* byt = trans.get_byte_enable_ptr();
unsigned int wid = trans.get_streaming_width();
ID_extension* id_extension = new ID_extension;
trans.get_extension( id_extension );
if(phase == tlm::END_REQ){
wait(delay);
cout << name() << " END_REQ RECEIVED" << " TRANS ID " << id_extension->transaction_id << " at time " << sc_time_stamp() << endl;
return tlm::TLM_COMPLETED;
}
if(phase == tlm::BEGIN_REQ){
// Obliged to check the transaction attributes for unsupported features
// and to generate the appropriate error response
if (byt != 0) {
trans.set_response_status( tlm::TLM_BYTE_ENABLE_ERROR_RESPONSE );
return tlm::TLM_COMPLETED;
}
//if (len > 4 || wid < len) {
// trans.set_response_status( tlm::TLM_BURST_ERROR_RESPONSE );
// return tlm::TLM_COMPLETED;
//}
// Now queue the transaction until the annotated time has elapsed
trans_pending=&trans;
phase_pending=phase;
delay_pending=delay;
e1.notify();
//Delay
wait(delay);
cout << name() << " BEGIN_REQ RECEIVED" << " TRANS ID " << id_extension->transaction_id << " at time " << sc_time_stamp() << endl;
return tlm::TLM_ACCEPTED;
}
}
// *********************************************
// Thread to call nb_transport on backward path
// *********************************************
void thread_process()
{
while (true) {
// Wait for an event to pop out of the back end of the queue
wait(e1);
//printf("ACCESING MEMORY\n");
//tlm::tlm_generic_payload* trans_ptr;
tlm::tlm_phase phase;
ID_extension* id_extension = new ID_extension;
trans_pending->get_extension( id_extension );
tlm::tlm_command cmd = trans_pending->get_command();
sc_dt::uint64 adr = trans_pending->get_address() / 4;
unsigned char* ptr = trans_pending->get_data_ptr();
unsigned int len = trans_pending->get_data_length();
unsigned char* byt = trans_pending->get_byte_enable_ptr();
unsigned int wid = trans_pending->get_streaming_width();
// Obliged to check address range and check for unsupported features,
// i.e. byte enables, streaming, and bursts
// Can ignore DMI hint and extensions
// Using the SystemC report handler is an acceptable way of signalling an error
if (adr >= sc_dt::uint64(SIZE) || byt != 0 || wid != 0 || len > 4)
SC_REPORT_ERROR("TLM2", "Target does not support given generic payload transaction");
// Obliged to implement read and write commands
if ( cmd == tlm::TLM_READ_COMMAND )
memcpy(ptr, &mem[adr], len);
else if ( cmd == tlm::TLM_WRITE_COMMAND )
memcpy(&mem[adr], ptr, len);
// Obliged to set response status to indicate successful completion
trans_pending->set_response_status( tlm::TLM_OK_RESPONSE );
wait(20, SC_NS);
delay_pending= (rand() % 4) * sc_time(10, SC_NS);
cout << name() << " BEGIN_RESP SENT" << " TRANS ID " << id_extension->transaction_id << " at time " << sc_time_stamp() << endl;
// Call on backward path to complete the transaction
tlm::tlm_sync_enum status;
phase = tlm::BEGIN_RESP;
status = socket->nb_transport_bw( *trans_pending, phase, delay_pending );
// The target gets a final chance to read or update the transaction object at this point.
// Once this process yields, the target must assume that the transaction object
// will be deleted by the initiator
// Check value returned from nb_transport
switch (status)
//case tlm::TLM_REJECTED:
case tlm::TLM_ACCEPTED:
wait(10, SC_NS);
cout << name() << " END_RESP SENT" << " TRANS ID " << id_extension->transaction_id << " at time " << sc_time_stamp() << endl;
// Expect response on the backward path
phase = tlm::END_RESP;
socket->nb_transport_bw( *trans_pending, phase, delay_pending ); // Non-blocking transport call
//break;
}
}
int mem[SIZE];
sc_event e1;
tlm::tlm_generic_payload* trans_pending;
tlm::tlm_phase phase_pending;
sc_time delay_pending;
};
SC_MODULE(TLM)
{
Initiator *initiator;
Memory *memory;
sc_core::sc_in<bool> IO_request;
SC_HAS_PROCESS(TLM);
TLM(sc_module_name tlm) // Construct and name socket
{
// Instantiate components
initiator = new Initiator("initiator");
initiator->IO_request(IO_request);
memory = new Memory ("memory");
// One initiator is bound directly to one target with no intervening bus
// Bind initiator socket to target socket
initiator->socket.bind(memory->socket);
}
};
|
#include <systemc.h>
SC_MODULE( tb )
{
sc_in<bool> clk;
sc_out<bool> rst;
sc_out< sc_int<16> > inp;
sc_out<bool> inp_vld;
sc_in<bool> inp_rdy;
sc_in< sc_int<16> > outp;
sc_in<bool> outp_vld;
sc_out<bool> outp_rdy;
void source();
void sink();
FILE *outfp;
sc_time start_time[64], end_time[64], clock_period;
SC_CTOR( tb ){
SC_CTHREAD( source, clk.pos() );
SC_CTHREAD( sink, clk.pos() );
}
};
|
/**
#define meta ...
prInt32f("%s\n", meta);
**/
/*
All rights reserved to Alireza Poshtkohi (c) 1999-2023.
Email: [email protected]
Website: http://www.poshtkohi.info
*/
#ifndef __s6_h__
#define __s6_h__
#include <systemc.h>
SC_MODULE(s6)
{
sc_in<sc_uint<6> > stage1_input;
sc_out<sc_uint<4> > stage1_output;
void s6_box();
SC_CTOR(s6)
{
SC_METHOD(s6_box);
sensitive << stage1_input;
}
};
#endif
|
/********************************************************************************
* University of L'Aquila - HEPSYCODE Source Code License *
* *
* *
* (c) 2018-2019 Centre of Excellence DEWS All rights reserved *
********************************************************************************
* <one line to give the program's name and a brief idea of what it does.> *
* Copyright (C) 2022 Vittoriano Muttillo, Luigi Pomante * *
* *
* This program is free software: you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation, either version 3 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
********************************************************************************
* *
* Created on: 09/May/2022 *
* Authors: Vittoriano Muttillo, Luigi Pomante *
* *
* email: [email protected] *
* [email protected] *
* *
********************************************************************************
* This code has been developed from an HEPSYCODE model used as demonstrator by *
* University of L'Aquila. *
* *
* The code is used as a working example in the 'Embedded Systems' course of *
* the Master in Conputer Science Engineering offered by the *
* University of L'Aquila *
*******************************************************************************/
/********************************************************************************
* display : FirFirGCD Display.
*
* Display: Display (feedback) file
*
********************************************************************************/
/*! \file display.h
\brief Display Documented file.
Display: Display (feedback) file
*/
/** @defgroup firfirgcd_display_group FirFirGCD Display.
*
* Display Implementation
*
* @author V. Muttillo, L. Pomante
* @date Apr. 2022
* @{
*/ // start firfirgcd_display_group
#ifndef __DISPLAY_H__
#define __DISPLAY_H__
/********************************************************************************
*** Includes ***
*******************************************************************************/
#include <systemc.h>
#include "sc_csp_channel_ifs.h"
/********************************************************************************
*** Functions ***
*******************************************************************************/
////////////////////////////
// SBM DEPENDENT
////////////////////////////
////////////////////////////
// DISPLAY: PRINTS TO THE SCREEN DATA FROM THE SYSTEM
////////////////////////////
SC_MODULE(display)
{
// Port for input by channel
sc_port< sc_csp_channel_in_if< sc_uint<8> > > result_channel_port;
SC_CTOR(display)
{
SC_THREAD(output);
}
// Main method
void output();
};
/** @} */ // end of firfirgcd_display_group
#endif
/********************************************************************************
*** EOF ***
********************************************************************************/
|
#ifndef SC_CONFIG_H
#define SC_CONFIG_H
#include <systemc.h>
typedef struct sc_thread_config_s {
bool rst_act_level;
int rst_act_microsteps;
bool ena_act_level;
bool clk_act_edge;
sc_time clk_period;
sc_time microstep;
int clk_semiperiod_microsteps;
} sc_thread_config_t;
void sc_setConfig(sc_thread_config_t *theConfig);
bool sc_getRstActLevel(void);
int sc_getRstActMicrosteps(void);
bool sc_getEnaActLevel(void);
bool sc_getClkActEdge(void);
sc_time sc_getClkPeriod(void);
sc_time sc_getMicrostep(void);
int sc_getClkSemiperiodMicrosteps(void);
#endif // SC_CONFIG_H
|
#include <systemc.h>
SC_MODULE(tb)
{
sc_in<bool> clk;
sc_out<bool> reset;
sc_out< sc_int<16> > input;
sc_out<bool> input_valid;
sc_in<bool> input_ready;
sc_in< sc_int<16> > output;
sc_in<bool> output_valid;
sc_out<bool> output_ready;
void source();
void sink();
SC_CTOR(tb){
SC_CTHREAD(source, clk.pos());
SC_CTHREAD(sink, clk.pos());
} |
#include <memory>
#include <systemc.h>
#include "Vtop.h"
#include "bfm.h"
SC_MODULE(sc_top) {
sc_clock clk;
sc_signal<bool> reset;
sc_signal<bool> cs;
sc_signal<bool> rw;
sc_signal<bool> ready;
#ifdef VERILATOR
sc_signal<uint32_t> addr;
sc_signal<uint32_t> data_in;
sc_signal<uint32_t> data_out;
#else
sc_signal<sc_uint<16>> addr;
sc_signal<sc_uint<32>> data_in;
sc_signal<sc_uint<32>> data_out;
#endif
Vtop *u_top;
bfm *u_bfm;
SC_CTOR(sc_top) :
clk("clk", 10, SC_NS, 0.5, 5, SC_NS, true),
reset("reset"), cs("cs"), rw("rw"), addr("addr"), ready("ready"), data_in("data_in"), data_out("data_out") {
#ifdef VERILATOR
u_top = new Vtop{"top"};
#else
u_top = new Vtop{"top", "Vtop", 0, NULL};
#endif
u_top->clk(clk);
u_top->reset(reset);
u_top->cs(cs);
u_top->rw(rw);
u_top->addr(addr);
u_top->data_in(data_in);
u_top->ready(ready);
u_top->data_out(data_out);
u_bfm = new bfm("bfm");
u_bfm->clk(clk);
u_bfm->reset(reset);
u_bfm->cs(cs);
u_bfm->rw(rw);
u_bfm->addr(addr);
u_bfm->data_in(data_out);
u_bfm->ready(ready);
u_bfm->data_out(data_in);
}
~sc_top() {
#ifdef VERILATOR
u_top->final();
#endif
delete u_top;
delete u_bfm;
}
};
|
#ifndef __I2C_CONTROLLER_TB_H
#define __I2C_CONTROLLER_TB_H
#include <systemc.h>
#include <i2c_controller.h>
#include <i2c_slave_controller.h>
SC_MODULE(i2c_controller_tb)
{
sc_clock *clk;
sc_signal<bool> rst;
sc_signal<sc_uint<7>> addr;
sc_signal<sc_uint<8>> data_in;
sc_signal<bool> enable;
sc_signal<bool> rw;
sc_signal<sc_lv<8>> data_out;
sc_signal<bool> ready;
sc_signal<sc_logic, SC_MANY_WRITERS> i2c_sda;
sc_signal<sc_logic> i2c_scl;
i2c_controller *master;
i2c_slave_controller *slave;
SC_CTOR(i2c_controller_tb)
{
clk = new sc_clock("clk",2,SC_NS);
master = new i2c_controller("i2c_controller");
master->clk(*clk);
master->rst(rst);
master->addr(addr);
master->data_in(data_in);
master->enable(enable);
master->rw(rw);
master->data_out(data_out);
master->ready(ready);
master->i2c_sda(i2c_sda);
master->i2c_scl(i2c_scl);
slave = new i2c_slave_controller("i2c_slave_controller");
slave->sda(i2c_sda);
slave->scl(i2c_scl);
SC_THREAD(stimuli);
sensitive << *clk << rst;
}
~i2c_controller_tb()
{
delete master;
delete slave;
}
void stimuli();
};
#endif
|
#include <systemc.h>
SC_MODULE( fir ) {
sc_in<bool> clk;
sc_in<bool> rst;
sc_in<sc_int<16>> inp;
sc_out<sc_int<16>> out;
// Handshake signals
sc_in<bool> inp_vld;
sc_out<bool> inp_rdy;
sc_out<bool> out_vld;
sc_in<bool> out_rdy;
void fir_main();
SC_CTOR( fir ) {
SC_CTHREAD(fir_main, clk.pos());
reset_signal_is(rst, true);
}
}; |
#ifndef COUNTER_H
#define COUNTER_H
#include <systemc.h>
#include "constants.h"
SC_MODULE(CounterModule){
// Inputs
sc_in<bool> clk;
sc_in<bool> reset;
sc_in<bool> up_down_ctrl;
sc_in<bool> count_enable;
//Outputs
sc_out<sc_uint<N> > count_out;
sc_out<bool> overflow_intr;
sc_out<bool> underflow_intr;
// Variables
sc_uint<N> count;
// Main function of the module
void do_count();
SC_CTOR(CounterModule){
SC_METHOD(do_count);
sensitive << clk.pos();
}
};
#endif
|
/**********************************************************************
Filename: sc_fir8_tb.h
Purpose : Testbench of 8-Tab Systolic FIR filter
Author : [email protected]
History : Mar. 2024, First release
***********************************************************************/
#ifndef _SC_FIR8_TB_H_
#define _SC_FIR8_TB_H_
#include <systemc.h>
#include "sc_fir8.h"
SC_MODULE(sc_fir8_tb)
{
sc_clock clk;
sc_signal<sc_uint<8> > Xin;
sc_signal<sc_uint<8> > Xout;
sc_signal<sc_uint<16> > Yin;
sc_signal<sc_uint<16> > Yout;
#ifdef EMULATED
sc_signal<sc_uint<8> > E_Xout;
sc_signal<sc_uint<16> > E_Yout;
#endif
sc_fir8* u_sc_fir8;
// Test utilities
void Test_Gen();
void Test_Mon();
sc_uint<8> x[F_SAMPLE]; // Time seq. input
sc_uint<16> y[F_SAMPLE]; // Filter output
#ifdef VCD_TRACE_FIR8_TB
sc_trace_file* fp; // VCD file
#endif
SC_CTOR(sc_fir8_tb):
clk("clk", 100, SC_NS, 0.5, 0.0, SC_NS, false),
Xin("Xin"),
Xout("Xout"),
Yin("Yin"),
Yout("Yout")
{
SC_THREAD(Test_Gen);
sensitive << clk;
SC_THREAD(Test_Mon);
sensitive << clk;
// Instaltiate FIR8
u_sc_fir8 = new sc_fir8("u_sc_fir8");
u_sc_fir8->clk(clk);
u_sc_fir8->Xin(Xin);
u_sc_fir8->Xout(Xout);
u_sc_fir8->Yin(Yin);
u_sc_fir8->Yout(Yout);
#ifdef EMULATED
u_sc_fir8->E_Xout(E_Xout);
u_sc_fir8->E_Yout(E_Yout);
#endif
#ifdef VCD_TRACE_FIR8_TB
// WAVE
fp = sc_create_vcd_trace_file("sc_fir8_tb");
fp->set_time_unit(100, SC_PS); // resolution (trace) ps
sc_trace(fp, clk, "clk");
sc_trace(fp, Xin, "Xin");
sc_trace(fp, Xout, "Xout");
sc_trace(fp, Yin, "Yin");
sc_trace(fp, Yout, "Yout");
#endif
}
~sc_fir8_tb(void)
{
}
};
#endif |
//
//------------------------------------------------------------//
// Copyright 2009-2012 Mentor Graphics Corporation //
// All Rights Reserved Worldwid //
// //
// Licensed under the Apache License, Version 2.0 (the //
// "License"); you may not use this file except in //
// compliance with the License. You may obtain a copy of //
// the License at //
// //
// http://www.apache.org/licenses/LICENSE-2.0 //
// //
// Unless required by applicable law or agreed to in //
// writing, software distributed under the License is //
// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR //
// CONDITIONS OF ANY KIND, either express or implied. See //
// the License for the specific language governing //
// permissions and limitations under the License. //
//------------------------------------------------------------//
//-----------------------------------------------------------------------------
// Title: UVMC Connection Example - Native SC to SC
//
// This example serves as a review for how to make 'native' TLM connections
// between two SystemC components (does not use UVMC).
//
// (see UVMC_Connections_SC2SC-native.png)
//
// In SystemC, a ~port~ is connected to an ~export~ or an ~interface~ using
// the port's ~bind~ function. An sc_module's port can also be connected to
// a port in a parent module, which effectively promotes the port up one
// level of hierarchy.
//
// In this particular example, ~sc_main~ does the following
//
// - Instantiates ~producer~ and ~consumer~ sc_modules
//
// - Binds the producer's ~out~ port to the consumer's ~in~ export
//
// - Calls ~sc_start~ to start the SystemC portion of our testbench.
//
// The ~bind~ call looks the same for all port-to-export/interface connections,
// regardless of the port types and transaction types. The C++ compiler
// will let you know if you've attempted an incompatible connection.
//-----------------------------------------------------------------------------
// (inline source)
#include <systemc.h>
using namespace sc_core;
#include "consumer.h"
#include "producer.h"
int sc_main(int argc, char* argv[])
{
producer prod("prod");
consumer cons("cons");
prod.out.bind(cons.in);
sc_start(-1);
return 0;
}
|
/**********************************************************************
Filename: sc_fir8.h
Purpose : Core of 8-Tab Systolic FIR filter
Author : [email protected]
History : Mar. 2024, First release
***********************************************************************/
#ifndef _SC_FIR8_H_
#define _SC_FIR8_H_
#include <systemc.h>
// Includes for accessing Arduino via serial port
#include <stdio.h>
#include <string.h>
#include <unistd.h>
#include <fcntl.h>
#include <termios.h>
#include "../c_untimed/fir8.h"
SC_MODULE(sc_fir8)
{
sc_in<bool> clk;
sc_in<sc_uint<8> > Xin;
sc_out<sc_uint<8> > Xout;
sc_in<sc_uint<16> > Yin;
sc_out<sc_uint<16> > Yout;
sc_signal<sc_uint<8> > X[FILTER_TAP_NUM]; // Shift Register X
void fir8_thread(void)
{
uint8_t x;
uint8_t yL, yH;
uint16_t y;
while(true)
{
wait(clk.posedge_event());
x = (uint8_t)Xin.read();
while(write(fd, &x, 1)<=0) // Send Byte
usleep(100);
for (int i=0; i<FILTER_TAP_NUM; i++)
{
while(read(fd, &x, 1)<=0) // Receive Byte: Shift Register of X
usleep(100);
X[i].write(sc_uint<8>(x));
}
while(read(fd, &yL, 1)<=0) // Receive Byte:LSB of y
usleep(100);
while(read(fd, &yH, 1)<=0) // Receive Byte:MSB of y
usleep(100);
y = (uint16_t)(yH<<8) | (uint16_t)(yL);
Yout.write(y);
}
}
// Arduino Serial IF
int fd; // Serial port file descriptor
struct termios options; // Serial port setting
#ifdef VCD_TRACE_FIR8
sc_trace_file* fp; // VCD file
#endif
SC_CTOR(sc_fir8):
clk("clk"),
Xin("Xin"),
Xout("Xout"),
Yin("Yin"),
Yout("Yout")
{
SC_THREAD(fir8_thread);
sensitive << clk;
// Arduino DUT
//fd = open("/dev/ttyACM0", O_RDWR | O_NDELAY | O_NOCTTY);
fd = open("/dev/ttyACM0", O_RDWR | O_NOCTTY);
if (fd < 0)
{
perror("Error opening serial port");
//return -1;
}
// Set up serial port
options.c_cflag = B9600 | CS8 | CLOCAL | CREAD;
options.c_iflag = IGNPAR;
options.c_oflag = 0;
options.c_lflag = 0;
// Apply the settings
tcflush(fd, TCIFLUSH);
tcsetattr(fd, TCSANOW, &options);
// Establish Contact
int len = 0;
char rx;
while(!len)
len = read(fd, &rx, 1);
if (rx=='A')
write(fd, &rx, 1);
printf("Connection established...\n");
#ifdef VCD_TRACE_FIR8
// WAVE
fp = sc_create_vcd_trace_file("sc_fir8");
fp->set_time_unit(100, SC_PS); // resolution (trace) ps
sc_trace(fp, clk, "clk");
sc_trace(fp, Xin, "Xin");
sc_trace(fp, Xout, "Xout");
sc_trace(fp, Yin, "Yin");
sc_trace(fp, Yout, "Yout");
char szTrace[8];
for (int i=0; i<FILTER_TAP_NUM; i++)
{
sprintf(szTrace, "X_%d", i);
sc_trace(fp, X[i], szTrace);
}
#endif
}
~sc_fir8(void)
{
close(fd);
}
};
#endif
|
/**********************************************************************
Filename: sc_fir8.h
Purpose : Core of 8-Tab Systolic FIR filter
Author : [email protected]
History : Mar. 2024, First release
***********************************************************************/
#ifndef _SC_FIR8_H_
#define _SC_FIR8_H_
#include <systemc.h>
#include "../c_untimed/fir8.h"
#include "sc_fir_pe.h"
#define N_PE_ARRAY 8
SC_MODULE(sc_fir8)
{
sc_in<bool> clk;
sc_in<sc_uint<8> > Xin;
sc_out<sc_uint<8> > Xout;
sc_in<sc_uint<16> > Yin;
sc_out<sc_uint<16> > Yout;
sc_fir_pe* u_fir_pe[N_PE_ARRAY];
sc_signal<sc_uint<8> > X[N_PE_ARRAY-1]; // X-input
sc_signal<sc_uint<16> > Y[N_PE_ARRAY-1]; // Accumulated
sc_signal<sc_uint<8> > C[N_PE_ARRAY]; // Filter-Tabs Coeff
#ifdef VCD_TRACE_FIR8
sc_trace_file* fp; // VCD file
#endif
SC_CTOR(sc_fir8):
clk("clk"),
Xin("Xin"),
Xout("Xout"),
Yin("Yin"),
Yout("Yout")
{
// Instaltiate PE array -----------------------------
char szPeName[16];
for (int i=0; i<N_PE_ARRAY; i++)
{
sprintf(szPeName, "u_PE_%d", i);
u_fir_pe[i] = new sc_fir_pe(szPeName);
C[i].write(sc_uint<8>(filter_taps[i]));
u_fir_pe[i]->Cin(C[i]);
u_fir_pe[i]->clk(clk);
}
// Configure Array -----------------------------------
// 0-th PE
u_fir_pe[0]->Xin(Xin);
u_fir_pe[0]->Xout(X[0]);
u_fir_pe[0]->Yin(Yin);
u_fir_pe[0]->Yout(Y[0]);
// Systolic Array
for (int i=1; i<N_PE_ARRAY-1; i++)
{
u_fir_pe[i]->Xin(X[i-1]);
u_fir_pe[i]->Xout(X[i]);
u_fir_pe[i]->Yin(Y[i-1]);
u_fir_pe[i]->Yout(Y[i]);
}
// Last PE
u_fir_pe[N_PE_ARRAY-1]->Xin(X[N_PE_ARRAY-2]);
u_fir_pe[N_PE_ARRAY-1]->Xout(Xout);
u_fir_pe[N_PE_ARRAY-1]->Yin(Y[N_PE_ARRAY-2]);
u_fir_pe[N_PE_ARRAY-1]->Yout(Yout);
#ifdef VCD_TRACE_FIR8
// WAVE
fp = sc_create_vcd_trace_file("sc_fir8");
fp->set_time_unit(100, SC_PS); // resolution (trace) ps
sc_trace(fp, clk, "clk");
sc_trace(fp, Xin, "Xin");
sc_trace(fp, Xout, "Xout");
sc_trace(fp, Yin, "Yin");
sc_trace(fp, Yout, "Yout");
char szTrace[8];
for (int i=0; i<N_PE_ARRAY-1; i++)
{
sprintf(szTrace, "X_%d", i);
sc_trace(fp, X[i], szTrace);
sprintf(szTrace, "Y_%d", i);
sc_trace(fp, Y[i], szTrace);
}
#endif
}
~sc_fir8(void)
{
}
};
#endif
|
/*******************************************************************************
Poorman's Standard-Emulator
---------------------------
Vendor: GoodKook, [email protected]
Associated Filename: sc_DUT_TB.h
Purpose: Testbench for DUT
Revision History: Jun. 1, 2024
*******************************************************************************/
#ifndef _SC_DUT_TB_H_
#define _SC_DUT_TB_H_
#include <systemc.h>
#include "VDUT.h"
#ifdef CO_EMULATION
#include "DUT.h"
#endif
SC_MODULE(sc_DUT_TB)
{
sc_clock CLK;
sc_signal<bool> nCLR;
sc_signal<bool> nLOAD;
sc_signal<bool> ENP;
sc_signal<bool> ENT;
sc_signal<bool> RCO;
// Verilator treats all Verilog's vector as <uint32_t>
sc_signal<uint32_t> Digit;
sc_signal<uint32_t> Din;
sc_signal<uint32_t> Dout;
// Exact DUT ports' vector width
sc_signal<sc_uint<2> > Digit_n2;
sc_signal<sc_uint<4> > Din_n4;
sc_signal<sc_uint<16> > Dout_n16;
// Verilated DUT or Foreign Verilog
VDUT* u_VDUT;
#ifdef CO_EMULATION
// Emulator DUT
DUT* u_DUT;
sc_signal<sc_uint<16> > Dout_emu;
sc_signal<bool> RCO_emu;
#endif
// Convert Verilator's ports to DUT's ports
void conv_method()
{
Digit_n2.write((sc_uint<2>)Digit);
Din_n4.write((sc_uint<4>)Din);
Dout_n16.write((sc_uint<16>)Dout);
}
void test_generator();
void monitor();
sc_trace_file* fp; // VCD file
SC_CTOR(sc_DUT_TB) : // Constructor
CLK("CLK", 100, SC_NS, 0.5, 0.0, SC_NS, false)
{
SC_THREAD(test_generator);
sensitive << CLK;
SC_THREAD(monitor);
sensitive << CLK;
SC_METHOD(conv_method);
sensitive << Din << Dout << Digit;
// DUT Instantiation
u_VDUT = new VDUT("u_VDUT");
// Binding
u_VDUT->CLK(CLK);
u_VDUT->nCLR(nCLR);
u_VDUT->nLOAD(nLOAD);
u_VDUT->Digit(Digit);
u_VDUT->ENP(ENP);
u_VDUT->ENT(ENT);
u_VDUT->Din(Din);
u_VDUT->Dout(Dout);
u_VDUT->RCO(RCO);
#ifdef CO_EMULATION
u_DUT = new DUT("u_DUT");
// Binding
u_DUT->CLK(CLK);
u_DUT->nCLR(nCLR);
u_DUT->nLOAD(nLOAD);
u_DUT->Digit(Digit_n2);
u_DUT->Din(Din_n4);
u_DUT->Dout(Dout_emu);
u_DUT->RCO(RCO_emu);
#endif
// VCD Trace
fp = sc_create_vcd_trace_file("sc_DUT_TB");
fp->set_time_unit(100, SC_PS);
sc_trace(fp, CLK, "CLK");
sc_trace(fp, nCLR, "nCLR");
sc_trace(fp, nLOAD, "nLOAD");
sc_trace(fp, Digit_n2, "Digit");
sc_trace(fp, ENP, "ENP");
sc_trace(fp, ENT, "ENT");
sc_trace(fp, Din_n4, "Din");
sc_trace(fp, Dout_n16, "Dout");
sc_trace(fp, RCO, "RCO");
#ifdef CO_EMULATION
sc_trace(fp, Dout_emu, "Dout_emu");
sc_trace(fp, RCO_emu, "RCO_emu");
#endif
}
// Destructor
~sc_DUT_TB()
{}
};
#endif // _SC_DUT_H_
|
#include <systemc.h>
SC_MODULE ( half_adder ) {
sc_in< sc_logic > augend;
sc_in< sc_logic > addend;
sc_out< sc_logic > sum;
sc_out< sc_logic > carry_out;
void func();
SC_CTOR ( half_adder ) {
SC_METHOD ( func );
sensitive << augend << addend;
};
};
|
/*******************************************************************************
* adc_types.h -- Copyright 2019 (c) Glenn Ramalho - RFIDo Design
*******************************************************************************
* Description:
* Defines types of ESP32 ADC being used.
*******************************************************************************
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
#ifndef _ADC_TYPES_H
#define _ADC_TYPES_H
#include <systemc.h>
#include "esp32adc1.h"
#include "esp32adc2.h"
typedef esp32adc1 adc1;
typedef esp32adc2 adc2;
extern adc1 *adc1ptr;
extern adc2 *adc2ptr;
#endif
|
/**********************************************************************
Filename: sc_fir8_tb.h
Purpose : Testbench of 8-Tab Systolic FIR filter
Author : [email protected]
History : Mar. 2024, First release
***********************************************************************/
#ifndef _SC_FIR8_TB_H_
#define _SC_FIR8_TB_H_
#include <systemc.h>
#include "sc_fir8.h"
#include <verilated_vcd_sc.h>
SC_MODULE(sc_fir8_tb)
{
sc_clock clk;
sc_signal<sc_uint<4> > Xin;
sc_signal<sc_uint<4> > Xout;
sc_signal<sc_uint<4> > Yin;
sc_signal<sc_uint<4> > Yout;
sc_signal<bool> Vld;
sc_signal<bool> Rdy;
#ifdef EMULATED
sc_signal<sc_uint<4> > E_Xout;
sc_signal<sc_uint<4> > E_Yout;
sc_signal<bool> E_Vld;
#endif
sc_fir8* u_sc_fir8;
VerilatedVcdSc* tfp; // Verilator VCD
// Test utilities
void Test_Gen();
void Test_Mon();
sc_uint<8> x[F_SAMPLE]; // Time seq. input
sc_uint<16> y[F_SAMPLE]; // Filter output
#ifdef VCD_TRACE_FIR8_TB
sc_trace_file* fp; // VCD file
#endif
SC_CTOR(sc_fir8_tb):
clk("clk", 100, SC_NS, 0.5, 0.0, SC_NS, false),
Vld("Vld"),
Rdy("Rdy"),
Xin("Xin"),
Xout("Xout"),
Yin("Yin"),
Yout("Yout")
{
SC_THREAD(Test_Gen);
sensitive << clk;
SC_THREAD(Test_Mon);
sensitive << clk;
// Instaltiate FIR8
u_sc_fir8 = new sc_fir8("u_sc_fir8");
u_sc_fir8->clk(clk);
u_sc_fir8->Xin(Xin);
u_sc_fir8->Xout(Xout);
u_sc_fir8->Yin(Yin);
u_sc_fir8->Yout(Yout);
u_sc_fir8->Rdy(Rdy);
u_sc_fir8->Vld(Vld);
#ifdef EMULATED
u_sc_fir8->E_Xout(E_Xout);
u_sc_fir8->E_Yout(E_Yout);
u_sc_fir8->E_Vld(E_Vld);
#endif
#ifdef VCD_TRACE_FIR8_TB
// WAVE
fp = sc_create_vcd_trace_file("sc_fir8_tb");
fp->set_time_unit(100, SC_PS); // resolution (trace) ps
sc_trace(fp, clk, "clk");
sc_trace(fp, Xin, "Xin");
sc_trace(fp, Xout, "Xout");
sc_trace(fp, Yin, "Yin");
sc_trace(fp, Yout, "Yout");
sc_trace(fp, Rdy, "Rdy");
sc_trace(fp, Vld, "Vld");
#endif
// Trace Verilated Verilog internals
Verilated::traceEverOn(true);
tfp = new VerilatedVcdSc;
sc_start(SC_ZERO_TIME);
u_sc_fir8->
u_fir_pe[N_PE_ARRAY-1]->
u_Vfir_pe->trace(tfp, 99); // Trace levels of hierarchy
tfp->open("Vfir_pe.vcd");
}
~sc_fir8_tb(void)
{
}
};
#endif |
/*****************************************************************************
Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
more contributor license agreements. See the NOTICE file distributed
with this work for additional information regarding copyright ownership.
Accellera licenses this file to you under the Apache License, Version 2.0
(the "License"); you may not use this file except in compliance with the
License. You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
implied. See the License for the specific language governing
permissions and limitations under the License.
*****************************************************************************/
/*****************************************************************************
simple_bus_test.h : The test bench.
Original Author: Ric Hilderink, Synopsys, Inc., 2001-10-11
*****************************************************************************/
/*****************************************************************************
MODIFICATION LOG - modifiers, enter your name, affiliation, date and
changes you are making here.
Name, Affiliation, Date:
Description of Modification:
*****************************************************************************/
#ifndef __simple_bus_test_h
#define __simple_bus_test_h
#include <systemc.h>
#include "simple_bus_master_blocking.h"
#include "simple_bus_master_non_blocking.h"
#include "simple_bus_master_direct.h"
#include "simple_bus_slow_mem.h"
#include "simple_bus.h"
#include "simple_bus_fast_mem.h"
#include "simple_bus_arbiter.h"
SC_MODULE(simple_bus_test)
{
// channels
sc_clock C1;
// module instances
simple_bus_master_blocking *master_b;
simple_bus_master_non_blocking *master_nb;
simple_bus_master_direct *master_d;
simple_bus_slow_mem *mem_slow;
simple_bus *bus;
simple_bus_fast_mem *mem_fast;
simple_bus_arbiter *arbiter;
// constructor
SC_CTOR(simple_bus_test)
: C1("C1")
{
// create instances
master_b = new simple_bus_master_blocking("master_b", 4, 0x4c, false, 300);
master_nb = new simple_bus_master_non_blocking("master_nb", 3, 0x38, false, 20);
master_d = new simple_bus_master_direct("master_d", 0x78, 100);
mem_fast = new simple_bus_fast_mem("mem_fast", 0x00, 0x7f);
mem_slow = new simple_bus_slow_mem("mem_slow", 0x80, 0xff, 1);
// bus = new simple_bus("bus",true); // verbose output
bus = new simple_bus("bus");
// arbiter = new simple_bus_arbiter("arbiter",true); // verbose output
arbiter = new simple_bus_arbiter("arbiter");
// connect instances
master_d->clock(C1);
bus->clock(C1);
master_b->clock(C1);
master_nb->clock(C1);
mem_slow->clock(C1);
master_d->bus_port(*bus);
master_b->bus_port(*bus);
master_nb->bus_port(*bus);
bus->arbiter_port(*arbiter);
bus->slave_port(*mem_slow);
bus->slave_port(*mem_fast);
}
// destructor
~simple_bus_test()
{
if (master_b) {delete master_b; master_b = 0;}
if (master_nb) {delete master_nb; master_nb = 0;}
if (master_d) {delete master_d; master_d = 0;}
if (mem_slow) {delete mem_slow; mem_slow = 0;}
if (bus) {delete bus; bus = 0;}
if (mem_fast) {delete mem_fast; mem_fast = 0;}
if (arbiter) {delete arbiter; arbiter = 0;}
}
}; // end class simple_bus_test
#endif
|
/**********************************************************************
Filename: sc_fir_pe.h
Purpose : Verilated PE of Systolic FIR filter
Author : [email protected]
History : Mar. 2024, First release
***********************************************************************/
#ifndef _V_FIR_PE_H_
#define _V_FIR_PE_H_
#include <systemc.h>
#include "./obj_dir/Vfir_pe.h"
SC_MODULE(V_fir_pe)
{
sc_in<bool> clk;
sc_in<bool> Rdy;
sc_out<bool> Vld;
sc_in<sc_uint<6> > Cin;
sc_in<sc_uint<4> > Xin;
sc_out<sc_uint<4> > Xout;
sc_in<sc_uint<4> > Yin;
sc_out<sc_uint<4> > Yout;
Vfir_pe* u_Vfir_pe;
sc_signal<uint32_t> _Cin;
sc_signal<uint32_t> _Xin;
sc_signal<uint32_t> _Xout;
sc_signal<uint32_t> _Yin;
sc_signal<uint32_t> _Yout;
sc_signal<bool> _Rdy;
sc_signal<bool> _Vld;
void pe_method(void)
{
_Cin = (uint32_t)Cin.read();
_Xin = (uint32_t)Xin.read();
_Yin = (uint32_t)Yin.read();
_Rdy = Rdy.read();
Xout.write(sc_uint<4>(_Xout));
Yout.write(sc_uint<4>(_Yout));
Vld.write(_Vld);
}
SC_CTOR(V_fir_pe):
clk("clk"),
Rdy("Rdy"), _Rdy("_Rdy"),
Vld("Vld"), _Vld("_Vld"),
Cin("Cin"), _Cin("_Cin"),
Xin("Xin"), _Xin("_Xin"),
Xout("Xout"), _Xout("_Xout"),
Yin("Yin"), _Yin("_Yin"),
Yout("Yout"), _Yout("_Yout")
{
SC_METHOD(pe_method);
sensitive << clk << Cin << Xin << Yin << Rdy;
// Instantiate Verilated PE
u_Vfir_pe = new Vfir_pe("u_Vfir_pe");
u_Vfir_pe->clk(clk);
u_Vfir_pe->Cin(_Cin);
u_Vfir_pe->Xin(_Xin);
u_Vfir_pe->Xout(_Xout);
u_Vfir_pe->Yin(_Yin);
u_Vfir_pe->Yout(_Yout);
u_Vfir_pe->Rdy(_Rdy);
u_Vfir_pe->Vld(_Vld);
}
~V_fir_pe(void)
{
}
};
#endif
|
#include <memory>
#include <systemc.h>
#include "Vtop.h"
#include "bfm.h"
SC_MODULE(sc_top) {
sc_clock clk;
sc_signal<bool> reset;
sc_signal<bool> cs;
sc_signal<bool> rw;
sc_signal<bool> ready;
#ifdef VERILATOR
sc_signal<uint32_t> addr;
sc_signal<uint32_t> data_in;
sc_signal<uint32_t> data_out;
#else
sc_signal<sc_uint<16>> addr;
sc_signal<sc_uint<32>> data_in;
sc_signal<sc_uint<32>> data_out;
#endif
Vtop *u_top;
bfm *u_bfm;
SC_CTOR(sc_top) :
clk("clk", 10, SC_NS, 0.5, 5, SC_NS, true),
reset("reset"), cs("cs"), rw("rw"), addr("addr"), ready("ready"), data_in("data_in"), data_out("data_out") {
#ifdef VERILATOR
u_top = new Vtop{"top"};
#else
u_top = new Vtop{"top", "Vtop", 0, NULL};
#endif
u_top->clk(clk);
u_top->reset(reset);
u_top->cs(cs);
u_top->rw(rw);
u_top->addr(addr);
u_top->data_in(data_in);
u_top->ready(ready);
u_top->data_out(data_out);
u_bfm = new bfm("bfm");
u_bfm->clk(clk);
u_bfm->reset(reset);
u_bfm->cs(cs);
u_bfm->rw(rw);
u_bfm->addr(addr);
u_bfm->data_in(data_out);
u_bfm->ready(ready);
u_bfm->data_out(data_in);
}
~sc_top() {
#ifdef VERILATOR
u_top->final();
#endif
delete u_top;
delete u_bfm;
}
};
|
/*****************************************************************************
Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
more contributor license agreements. See the NOTICE file distributed
with this work for additional information regarding copyright ownership.
Accellera licenses this file to you under the Apache License, Version 2.0
(the "License"); you may not use this file except in compliance with the
License. You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
implied. See the License for the specific language governing
permissions and limitations under the License.
*****************************************************************************/
/*****************************************************************************
quant.h --
Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
*****************************************************************************/
/*****************************************************************************
MODIFICATION LOG - modifiers, enter your name, affiliation, date and
changes you are making here.
Name, Affiliation, Date:
Description of Modification:
*****************************************************************************/
#ifndef QUANTH
#define QUANTH
#include <systemc.h>
#include "global.h"
SC_MODULE(quant) {
sc_in_clk clk;
sc_in<Coeff8x8> data_in;
sc_in<bool> start;
sc_in<bool> data_ok;
sc_out<Coeff8x8> data_out;
sc_out<bool> ready;
sc_out<bool> data_out_ready;
void do_quant();
SC_CTOR(quant) {
SC_CTHREAD(do_quant,clk.pos());
};
};
#endif
|
/*
* @ASCK
*/
#include <systemc.h>
SC_MODULE (IR) {
sc_in <sc_uint<14>> addr;
sc_out <sc_uint<20>> inst;
/*
** module global variables
*/
sc_uint<20> mem[819]; // 819 rows and 819*20=16380 bits = (16KB - 4bits) ~= 16KB
int instNum = 50;
sc_uint<20> instruction[50] = {
// 0b01234567890123456789
0b00000000000000000000,
0b00100000000000000111, // transfer (r0 <- 7): 7
0b00010010010000000000, // inc (r1++): 1
//stall for achieving the correct register data - sub
0b11110000000000000000, //stall
0b11110000000000000000, //stall
0b11110000000000000000, //stall
0b00000110000010000010, // sub (r3 <-r0 - r1): 6
0b11110000000000000000, //stall
0b11110000000000000000, //stall
0b11110000000000000000, //stall
0b00011000110010000001, // addc (r4 <- r3 + r1 + 1): 8
0b11110000000000000000, //stall
0b11110000000000000000, //stall
0b11110000000000000000, //stall
0b00001001000000101001, // shiftR (r4 >> 2): 2
0b01010000000000000101, // stroe (mem[5] <= r0) : 7
0b01001010000000000101, // load (r5 <= mem[5]) : 7
0b01100000000000000000, // do accelerator
0b01000100000000010100, // load (r2 <= mem[20]) : 17 => 0x11
0b11110000000000000000, //nop
0b11110000000000000000, //nop
0b11110000000000000000, //nop
0b11110000000000000000, //nop
0b11110000000000000000, //nop
0b11110000000000000000 //nop
};
SC_CTOR (IR){
SC_METHOD (process);
sensitive << addr;
for(int i=0; i<instNum; i++){
mem[i] = instruction[i];
}
// filling out other rows with a nop opcode
for(int i=instNum; i<819; i++){
mem[i] = 0b11110000000000000000;
}
}
void process () {
if(addr.read() < 819){
inst.write(mem[addr.read()]);
}
else{
inst.write(0);
}
}
}; |
/********************************************************************************
* University of L'Aquila - HEPSYCODE Source Code License *
* *
* *
* (c) 2018-2019 Centre of Excellence DEWS All rights reserved *
********************************************************************************
* <one line to give the program's name and a brief idea of what it does.> *
* Copyright (C) 2022 Vittoriano Muttillo, Luigi Pomante * *
* *
* This program is free software: you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation, either version 3 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
********************************************************************************
* *
* Created on: 09/May/2023 *
* Authors: Vittoriano Muttillo, Marco Santic, Luigi Pomante *
* *
* email: [email protected] *
* [email protected] *
* [email protected] *
* *
********************************************************************************
* This code has been developed from an HEPSYCODE model used as demonstrator by *
* University of L'Aquila. *
*******************************************************************************/
#include <systemc.h>
#include "../mainsystem.h"
#include <math.h>
//-----------------------------------------------------------------------------
// Physical constants
//-----------------------------------------------------------------------------
static double sTC_I_0 = 77.3 ; // [A] Nominal current
//static double sTC_T_0 = 298.15 ; // [K] Ambient temperature
//static double sTC_R_0 = 0.01 ; // [Ω] Data-sheet R_DS_On (Drain-Source resistance in the On State)
static double sTC_V_0 = 47.2 ; // [V] Nominal voltage
//static double sTC_Alpha = 0.002 ; // [Ω/K] Temperature coefficient of Drain-Source resistance in the On State
//static double sTC_ThermalConstant = 0.75 ;
//static double sTC_Tau = 0.02 ; // [s] Sampling period
//-----------------------------------------------------------------------------
// Simulation related data
//-----------------------------------------------------------------------------
//#define N_CYCLES 1000 // Change by command line option -n<number>
#define sTC_NOISE 0.2 // Measurement noise = 10%
static double sTC_time_Ex = 0 ; // Simple time simulation
//-----------------------------------------------------------------------------
// Mnemonics to access the array that contains the sampled data
//-----------------------------------------------------------------------------
#define sTC_SAMPLE_LEN 3 // Array of SAMPLE_LEN elements
#define sTC_I_INDEX 0 // Current
#define sTC_V_INDEX 1 // Voltage
#define sTC_TIME_INDEX 2 // Time
///-----------------------------------------------------------------------------
// Forward references
//-----------------------------------------------------------------------------
//static int sTC_initDescriptors(void) ;
static void sTC_getSample(int index, double sample[sTC_SAMPLE_LEN]) ;
//-----------------------------------------------------------------------------
//
//-----------------------------------------------------------------------------
void sTC_getSample(int index, double sample[sTC_SAMPLE_LEN])
{HEPSY_S(sampleTimCord_id)
// the parameter "index" is needed as device identifier
HEPSY_S(sampleTimCord_id) sample[sTC_TIME_INDEX] = sTC_time_Ex ;
// Random generation of i (current)
HEPSY_S(sampleTimCord_id) double i; double v ; double noise ;
// Random i
HEPSY_S(sampleTimCord_id) i = (double)rand() / (double)RAND_MAX ; // 0.0 <= i <= 1.0
HEPSY_S(sampleTimCord_id) i *= 2.0 ; // 0.0 <= i <= 2.0
HEPSY_S(sampleTimCord_id) i *= sTC_I_0 ; // 0.0 <= i <= 2.0*I_0
// Postcondition: (0 <= i <= 2.0*I_0)
// Add some noise every 3 samples
HEPSY_S(sampleTimCord_id)
HEPSY_S(sampleTimCord_id) noise = rand() % 3 == 0 ? 1.0 : 0.0 ;
HEPSY_S(sampleTimCord_id)
HEPSY_S(sampleTimCord_id)
HEPSY_S(sampleTimCord_id) noise *= (double)rand() / (double)RAND_MAX ;
HEPSY_S(sampleTimCord_id) noise *= 2.0 ;
HEPSY_S(sampleTimCord_id) noise -= 1.0 ;
HEPSY_S(sampleTimCord_id)
HEPSY_S(sampleTimCord_id) noise *= (sTC_NOISE * sTC_I_0 ) ; // NOISE as % of I_0
HEPSY_S(sampleTimCord_id) i += noise ;
// Postcondition: (-NOISE*I_0 <= i <= (2.0+NOISE)*I_0 )
// Random v
HEPSY_S(sampleTimCord_id) v = (double)rand() / (double)RAND_MAX ; // 0.0 <= i <= 1.0
HEPSY_S(sampleTimCord_id) v *= 2.0 ; // 0.0 <= i <= 2.0
HEPSY_S(sampleTimCord_id) v *= sTC_V_0 ; // 0.0 <= i <= 2.0*I_0
// Postcondition: (0 <= i <= 2.0*I_0)
// Add some noise every 3 samples
HEPSY_S(sampleTimCord_id)
HEPSY_S(sampleTimCord_id) noise = rand() % 3 == 0 ? 1.0 : 0.0 ;
HEPSY_S(sampleTimCord_id)
HEPSY_S(sampleTimCord_id)
HEPSY_S(sampleTimCord_id) noise *= (double)rand() / (double)RAND_MAX ;
HEPSY_S(sampleTimCord_id) noise *= 2.0 ;
HEPSY_S(sampleTimCord_id) noise -= 1.0 ;
HEPSY_S(sampleTimCord_id)
HEPSY_S(sampleTimCord_id) noise *= (sTC_NOISE * sTC_V_0 ) ; // NOISE as % of I_0
HEPSY_S(sampleTimCord_id) v += noise ;
// Postcondition: (-NOISE*V_0 <= v <= (2.0+NOISE)*V_0 )
HEPSY_S(sampleTimCord_id) sample[sTC_I_INDEX] = i ;
HEPSY_S(sampleTimCord_id) sample[sTC_V_INDEX] = v ;
}
void mainsystem::sampleTimCord_main()
{
// datatype for channels
stimulus_system_payload stimulus_system_payload_var;
sampleTimCord_cleanData_xx_payload sampleTimCord_cleanData_xx_payload_var;
//step var
uint16_t step;
//device var
int dev;
// ex_time (for extractFeatures...)
double ex_time;
//var for samples, to re-use getSample()
double sample[sTC_SAMPLE_LEN] ;
srand(1);
//implementation
HEPSY_S(sampleTimCord_id) while(1)
{HEPSY_S(sampleTimCord_id)
// content
HEPSY_S(sampleTimCord_id) stimulus_system_payload_var = stimulus_system_port_out->read();
HEPSY_S(sampleTimCord_id) dev = 0;
HEPSY_S(sampleTimCord_id) step = stimulus_system_payload_var.example; //step
HEPSY_S(sampleTimCord_id) ex_time = sc_time_stamp().to_seconds();
//providing sample to ward device 0 (cleanData_01)
HEPSY_S(sampleTimCord_id) sTC_getSample(dev, sample);
// cout << "sampleTimCord \t dev: " << dev
// <<"\t s0:" << sample[0]
// <<"\t s1:" << sample[1]
// <<"\t s3:" << sample[2]
// << endl;
HEPSY_S(sampleTimCord_id) sampleTimCord_cleanData_xx_payload_var.dev = dev++;
HEPSY_S(sampleTimCord_id) sampleTimCord_cleanData_xx_payload_var.step = step;
HEPSY_S(sampleTimCord_id) sampleTimCord_cleanData_xx_payload_var.ex_time = ex_time;
HEPSY_S(sampleTimCord_id) sampleTimCord_cleanData_xx_payload_var.sample_i = sample[sTC_I_INDEX];
HEPSY_S(sampleTimCord_id) sampleTimCord_cleanData_xx_payload_var.sample_v = sample[sTC_V_INDEX];
HEPSY_S(sampleTimCord_id) sampleTimCord_cleanData_01_channel->write(sampleTimCord_cleanData_xx_payload_var);
//providing sample to ward device 1 (cleanData_02)
HEPSY_S(sampleTimCord_id) sTC_getSample(dev, sample);
// cout << "sampleTimCord \t dev: " << dev
// <<"\t s0:" << sample[0]
// <<"\t s1:" << sample[1]
// <<"\t s3:" << sample[2]
// << endl;
HEPSY_S(sampleTimCord_id) sampleTimCord_cleanData_xx_payload_var.dev = dev++;
HEPSY_S(sampleTimCord_id) sampleTimCord_cleanData_xx_payload_var.step = step;
HEPSY_S(sampleTimCord_id) sampleTimCord_cleanData_xx_payload_var.ex_time = ex_time;
HEPSY_S(sampleTimCord_id) sampleTimCord_cleanData_xx_payload_var.sample_i = sample[sTC_I_INDEX];
HEPSY_S(sampleTimCord_id) sampleTimCord_cleanData_xx_payload_var.sample_v = sample[sTC_V_INDEX];
HEPSY_S(sampleTimCord_id) sampleTimCord_cleanData_02_channel->write(sampleTimCord_cleanData_xx_payload_var);
//providing sample to ward device 2 (cleanData_03)
HEPSY_S(sampleTimCord_id) sTC_getSample(dev, sample);
// cout << "sampleTimCord \t dev: " << dev
// <<"\t s0:" << sample[0]
// <<"\t s1:" << sample[1]
// <<"\t s3:" << sample[2]
// << endl;
HEPSY_S(sampleTimCord_id) sampleTimCord_cleanData_xx_payload_var.dev = dev++;
HEPSY_S(sampleTimCord_id) sampleTimCord_cleanData_xx_payload_var.step = step;
HEPSY_S(sampleTimCord_id) sampleTimCord_cleanData_xx_payload_var.ex_time = ex_time;
HEPSY_S(sampleTimCord_id) sampleTimCord_cleanData_xx_payload_var.sample_i = sample[sTC_I_INDEX];
HEPSY_S(sampleTimCord_id) sampleTimCord_cleanData_xx_payload_var.sample_v = sample[sTC_V_INDEX];
HEPSY_S(sampleTimCord_id) sampleTimCord_cleanData_03_channel->write(sampleTimCord_cleanData_xx_payload_var);
//providing sample to ward device 3 (cleanData_04)
HEPSY_S(sampleTimCord_id) sTC_getSample(dev, sample);
// cout << "sampleTimCord \t dev: " << dev
// <<"\t s0:" << sample[0]
// <<"\t s1:" << sample[1]
// <<"\t s3:" << sample[2]
// << endl;
HEPSY_S(sampleTimCord_id) sampleTimCord_cleanData_xx_payload_var.dev = dev++;
HEPSY_S(sampleTimCord_id) sampleTimCord_cleanData_xx_payload_var.step = step;
HEPSY_S(sampleTimCord_id) sampleTimCord_cleanData_xx_payload_var.ex_time = ex_time;
HEPSY_S(sampleTimCord_id) sampleTimCord_cleanData_xx_payload_var.sample_i = sample[sTC_I_INDEX];
HEPSY_S(sampleTimCord_id) sampleTimCord_cleanData_xx_payload_var.sample_v = sample[sTC_V_INDEX];
HEPSY_S(sampleTimCord_id) sampleTimCord_cleanData_04_channel->write(sampleTimCord_cleanData_xx_payload_var);
HEPSY_P(sampleTimCord_id)
}
}
//END
|
/*****************************************************************************
Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
more contributor license agreements. See the NOTICE file distributed
with this work for additional information regarding copyright ownership.
Accellera licenses this file to you under the Apache License, Version 2.0
(the "License"); you may not use this file except in compliance with the
License. You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
implied. See the License for the specific language governing
permissions and limitations under the License.
*****************************************************************************/
/*****************************************************************************
quant.h --
Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
*****************************************************************************/
/*****************************************************************************
MODIFICATION LOG - modifiers, enter your name, affiliation, date and
changes you are making here.
Name, Affiliation, Date:
Description of Modification:
*****************************************************************************/
#ifndef QUANTH
#define QUANTH
#include <systemc.h>
#include "global.h"
SC_MODULE(quant) {
sc_in_clk clk;
sc_in<Coeff8x8> data_in;
sc_in<bool> start;
sc_in<bool> data_ok;
sc_out<Coeff8x8> data_out;
sc_out<bool> ready;
sc_out<bool> data_out_ready;
void do_quant();
SC_CTOR(quant) {
SC_CTHREAD(do_quant,clk.pos());
};
};
#endif
|
/*****************************************************************************
Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
more contributor license agreements. See the NOTICE file distributed
with this work for additional information regarding copyright ownership.
Accellera licenses this file to you under the Apache License, Version 2.0
(the "License"); you may not use this file except in compliance with the
License. You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
implied. See the License for the specific language governing
permissions and limitations under the License.
*****************************************************************************/
/*****************************************************************************
quant.h --
Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
*****************************************************************************/
/*****************************************************************************
MODIFICATION LOG - modifiers, enter your name, affiliation, date and
changes you are making here.
Name, Affiliation, Date:
Description of Modification:
*****************************************************************************/
#ifndef QUANTH
#define QUANTH
#include <systemc.h>
#include "global.h"
SC_MODULE(quant) {
sc_in_clk clk;
sc_in<Coeff8x8> data_in;
sc_in<bool> start;
sc_in<bool> data_ok;
sc_out<Coeff8x8> data_out;
sc_out<bool> ready;
sc_out<bool> data_out_ready;
void do_quant();
SC_CTOR(quant) {
SC_CTHREAD(do_quant,clk.pos());
};
};
#endif
|
/// \file transmitter.h
/// \brief File containing the entity of the transmitter component.
///
/// See also transmitter.cpp
#ifndef TRANSMITTER_H
#define TRANSMITTER_H
#include <systemc.h>
#include "NOC_package.h"
/*! \class transmitter
\brief SystemC description of the transmitter module.
It is the transmitter bolck of the GRLS wrapper.
*/
SC_MODULE(transmitter)
//class transmitter : public sc_module
{
/// Input port for datas from the switch
sc_in<Packet> datain;
/// reset port
sc_in<bool> rst_n;
/// clk port
sc_in<bool> clk;
/// full port. If it's set it indicates that the fifo of the transmitter is to small to contain all datas
sc_out<sc_bit> full;
/// strobe output port.It changes with datac
sc_out<sc_bit> strobe;
/// data to the receiver sub-block of the wrapper
sc_out<Packet> datac;
/// main process of the transmitter module
void evaluate();
//Packet FIFO[FIFO_TX_DIM];
/// fifo used to manage case of fast transmitter
Packet* FIFO;
int i,last_pos,c;
ofstream tx_file;
//SC_CTOR(transmitter)
/// constructor of the transmitter
SC_HAS_PROCESS(transmitter);
transmitter(sc_module_name name_ , int N_R , int N_T, int fifo_tx_dim) : sc_module(name_), m_N_R(N_R), m_N_T(N_T),m_fifo_tx_dim(fifo_tx_dim)
{
SC_METHOD(evaluate);
sensitive<<clk.pos()<<rst_n.neg();
FIFO= new Packet[m_fifo_tx_dim];
for (i=0;i<m_fifo_tx_dim;i++)
FIFO[i]=empty_NL_PDU;
last_pos=0;
if(m_N_R > m_N_T)
c=m_N_R;
tx_file.open ("tx_file.txt",ios::trunc);
tx_file << "SIMULATION STARTS NOW: "<<endl<<endl;
tx_file.close();
}
private:
int m_N_R,m_N_T,m_fifo_tx_dim;
};
#endif
|
//---------------------------------------------------------------------------------------
//
// DISTRIBUTED HEMPS - version 5.0
//
// Research group: GAPH-PUCRS - contact [email protected]
//
// Distribution: September 2013
//
// Source name: queue.h
//
// Brief description: Methods of process control queue occupancy
//
//---------------------------------------------------------------------------------------
#ifndef _fila_h
#define _fila_h
#include <systemc.h>
#include "packet.h"
SC_MODULE(fila){
sc_in<bool > clock;
sc_in<bool > reset_n;
sc_in<regflit > data_in;
sc_in<bool > rx;
sc_out<bool > credit_o;
//sc_out<bool > ack_rx;
sc_out<bool > h;
sc_in<bool > ack_h;
sc_out<bool > data_av;
sc_out<regflit > data;
sc_in<bool > data_ack;
sc_out<bool > sender;
enum fila_out{S_INIT, S_PAYLOAD, S_SENDHEADER, S_HEADER, S_END, S_END2};
sc_signal<fila_out > EA, PE;
regflit buffer_in[BUFFER_TAM];
sc_signal<sc_uint<4> > first,last;
sc_signal<bool > tem_espaco_na_fila, auxack_rx;
sc_signal<regflit > counter_flit;
void in_proc_FSM();
void in_proc_updPtr();
void out_proc_data();
void out_proc_FSM();
void change_state_sequ();
void change_state_comb();
SC_CTOR(fila){
SC_METHOD(in_proc_FSM);
sensitive << reset_n.neg();
sensitive << clock.pos();
SC_METHOD(out_proc_data);
sensitive << first;
sensitive << last;
SC_METHOD(out_proc_FSM);
sensitive << reset_n.neg();
sensitive << clock.pos();
SC_METHOD(in_proc_updPtr);
sensitive << reset_n.neg();
sensitive << clock.neg();
}
};
#endif
|
/******************************************************************************
* (C) Copyright 2014 AMIQ Consulting
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* NAME: amiq_eth.h
* PROJECT: amiq_eth
* Description: This file includes all the C++ files which are part of
* amiq_eth package.
*******************************************************************************/
#ifndef __AMIQ_ETH
//protection against multiple includes
#define __AMIQ_ETH
#include <systemc.h>
#include "sysc/utils/sc_report.h"
#include "amiq_eth_defines.cpp"
#include "amiq_eth_ethernet_protocols.cpp"
#include "amiq_eth_packer.cpp"
#include "amiq_eth_types.cpp"
#include "amiq_eth_packet.cpp"
#include "amiq_eth_packet_ether_type.cpp"
#include "amiq_eth_packet_length.cpp"
#include "amiq_eth_packet_pause.cpp"
#include "amiq_eth_packet_pfc_pause.cpp"
#include "amiq_eth_packet_snap.cpp"
#include "amiq_eth_packet_jumbo.cpp"
#include "amiq_eth_packet_magic.cpp"
#include "amiq_eth_packet_ethernet_configuration_testing.cpp"
#include "amiq_eth_packet_ipv4.cpp"
#include "amiq_eth_packet_hsr_base.cpp"
#include "amiq_eth_packet_hsr_standard.cpp"
#include "amiq_eth_packet_fcoe.cpp"
#include "amiq_eth_packet_arp.cpp"
#include "amiq_eth_packet_ptp.cpp"
#endif
|
#ifndef ACC_H
#define ACC_H
#include <systemc.h>
// #define __SYNTHESIS__
#define SYSC_ACC_DEBUG
//#define SYSC_ACC_DEBUG2
#ifndef __SYNTHESIS__
#define DWAIT(x) wait(x)
#else
#define DWAIT(x)
#endif
#define ACCNAME VM_INT8_V1_0
#define ACC_DTYPE sc_int
#define ACC_C_DTYPE int
#define MAX 2147483647
#define MIN -2147483648
#define POS 1073741824
#define NEG -1073741823
#define DIVMAX 2147483648
#define MAX8 127
#define MIN8 -128
typedef struct _DATA{
ACC_DTYPE<32> data;
bool tlast;
inline friend ostream& operator << (ostream& os, const _DATA &v){
cout << "data: " << v.data << " tlast: " << v.tlast;
return os;
}
} DATA;
typedef struct _HDATA{
bool rhs_take;
bool lhs_take;
sc_uint<8> rhs_count;
sc_uint<8> lhs_count;
sc_uint<16> dst_addr;
} HDATA;
typedef struct _ADATA{
ACC_DTYPE<32> d2;
ACC_DTYPE<32> d3;
ACC_DTYPE<32> d4;
ACC_DTYPE<32> d5;
ACC_DTYPE<32> d6;
ACC_DTYPE<32> d7;
ACC_DTYPE<32> d8;
ACC_DTYPE<32> d9;
ACC_DTYPE<32> d10;
ACC_DTYPE<32> d11;
ACC_DTYPE<32> d12;
ACC_DTYPE<32> d13;
ACC_DTYPE<32> d14;
ACC_DTYPE<32> d15;
ACC_DTYPE<32> d16;
ACC_DTYPE<32> d17;
inline friend ostream& operator << (ostream& os, const _ADATA &v){
return os;
}
} ADATA;
SC_MODULE(ACCNAME) {
//debug vars
bool print_po = false;
bool print_wo = false;
int simplecounter=0;
// int rows=0;
ACC_DTYPE<14> depth;
sc_in<bool> clock;
sc_in <bool> reset;
sc_fifo_in<DATA> din1;
sc_fifo_in<DATA> din2;
sc_fifo_in<DATA> din3;
sc_fifo_in<DATA> din4;
sc_fifo_out<DATA> dout1;
sc_fifo_out<DATA> dout2;
sc_fifo_out<DATA> dout3;
sc_fifo_out<DATA> dout4;
sc_signal<bool> read_inputs;
sc_signal<bool> rtake;
sc_signal<bool> ltake;
sc_signal<int> llen;
sc_signal<int> rlen;
sc_signal<int> lhs_block_max;
sc_signal<int> rhs_block_max;
#ifndef __SYNTHESIS__
sc_signal<bool,SC_MANY_WRITERS> d_in1;
sc_signal<bool,SC_MANY_WRITERS> d_in2;
sc_signal<bool,SC_MANY_WRITERS> d_in3;
sc_signal<bool,SC_MANY_WRITERS> d_in4;
sc_signal<bool,SC_MANY_WRITERS> schedule;
sc_signal<bool,SC_MANY_WRITERS> out_check;
sc_signal<bool,SC_MANY_WRITERS> gemm_unit_1_ready;
sc_signal<bool,SC_MANY_WRITERS> gemm_unit_2_ready;
sc_signal<bool,SC_MANY_WRITERS> gemm_unit_3_ready;
sc_signal<bool,SC_MANY_WRITERS> gemm_unit_4_ready;
sc_signal<bool,SC_MANY_WRITERS> write1;
sc_signal<bool,SC_MANY_WRITERS> write2;
sc_signal<bool,SC_MANY_WRITERS> write3;
sc_signal<bool,SC_MANY_WRITERS> write4;
sc_signal<bool,SC_MANY_WRITERS> arrange1;
sc_signal<bool,SC_MANY_WRITERS> arrange2;
sc_signal<bool,SC_MANY_WRITERS> arrange3;
sc_signal<bool,SC_MANY_WRITERS> arrange4;
sc_signal<bool,SC_MANY_WRITERS> write1_1;
sc_signal<bool,SC_MANY_WRITERS> write1_2;
sc_signal<bool,SC_MANY_WRITERS> write1_3;
sc_signal<bool,SC_MANY_WRITERS> write1_4;
sc_signal<bool,SC_MANY_WRITERS> write2_1;
sc_signal<bool,SC_MANY_WRITERS> write2_2;
sc_signal<bool,SC_MANY_WRITERS> write2_3;
sc_signal<bool,SC_MANY_WRITERS> write2_4;
sc_signal<bool,SC_MANY_WRITERS> write3_1;
sc_signal<bool,SC_MANY_WRITERS> write3_2;
sc_signal<bool,SC_MANY_WRITERS> write3_3;
sc_signal<bool,SC_MANY_WRITERS> write3_4;
sc_signal<bool,SC_MANY_WRITERS> write4_1;
sc_signal<bool,SC_MANY_WRITERS> write4_2;
sc_signal<bool,SC_MANY_WRITERS> write4_3;
sc_signal<bool,SC_MANY_WRITERS> write4_4;
#else
sc_signal<bool> d_in1;
sc_signal<bool> d_in2;
sc_signal<bool> d_in3;
sc_signal<bool> d_in4;
sc_signal<bool> schedule;
sc_signal<bool> out_check;
sc_signal<bool> gemm_unit_1_ready;
sc_signal<bool> gemm_unit_2_ready;
sc_signal<bool> gemm_unit_3_ready;
sc_signal<bool> gemm_unit_4_ready;
sc_signal<bool> write1;
sc_signal<bool> write2;
sc_signal<bool> write3;
sc_signal<bool> write4;
sc_signal<bool> arrange1;
sc_signal<bool> arrange2;
sc_signal<bool> arrange3;
sc_signal<bool> arrange4;
sc_signal<bool> write1_1;
sc_signal<bool> write1_2;
sc_signal<bool> write1_3;
sc_signal<bool> write1_4;
sc_signal<bool> write2_1;
sc_signal<bool> write2_2;
sc_signal<bool> write2_3;
sc_signal<bool> write2_4;
sc_signal<bool> write3_1;
sc_signal<bool> write3_2;
sc_signal<bool> write3_3;
sc_signal<bool> write3_4;
sc_signal<bool> write4_1;
sc_signal<bool> write4_2;
sc_signal<bool> write4_3;
sc_signal<bool> write4_4;
#endif
sc_signal<int> gemm_unit_1_l_pointer;
sc_signal<int> gemm_unit_2_l_pointer;
sc_signal<int> gemm_unit_3_l_pointer;
sc_signal<int> gemm_unit_4_l_pointer;
sc_signal<bool> gemm_unit_1_iwuse;
sc_signal<bool> gemm_unit_2_iwuse;
sc_signal<bool> gemm_unit_3_iwuse;
sc_signal<bool> gemm_unit_4_iwuse;
ADATA g1;
ADATA g2;
ADATA g3;
ADATA g4;
ADATA r1;
ADATA r2;
ADATA r3;
ADATA r4;
//GEMM 1 Inputs
ACC_DTYPE<32> lhsdata1a[2048];
ACC_DTYPE<32> lhsdata2a[2048];
ACC_DTYPE<32> lhsdata3a[2048];
ACC_DTYPE<32> lhsdata4a[2048];
//GEMM 2 Inputs
ACC_DTYPE<32> lhsdata1b[2048];
ACC_DTYPE<32> lhsdata2b[2048];
ACC_DTYPE<32> lhsdata3b[2048];
ACC_DTYPE<32> lhsdata4b[2048];
//GEMM 3 Inputs
ACC_DTYPE<32> lhsdata1c[2048];
ACC_DTYPE<32> lhsdata2c[2048];
ACC_DTYPE<32> lhsdata3c[2048];
ACC_DTYPE<32> lhsdata4c[2048];
//GEMM 4 Inputs
ACC_DTYPE<32> lhsdata1d[2048];
ACC_DTYPE<32> lhsdata2d[2048];
ACC_DTYPE<32> lhsdata3d[2048];
ACC_DTYPE<32> lhsdata4d[2048];
// //GEMM 1 Inputs
// ACC_DTYPE<32> lhsdata1a[4096];
// ACC_DTYPE<32> lhsdata2a[4096];
// ACC_DTYPE<32> lhsdata3a[4096];
// ACC_DTYPE<32> lhsdata4a[4096];
//
// //GEMM 2 Inputs
// ACC_DTYPE<32> lhsdata1b[4096];
// ACC_DTYPE<32> lhsdata2b[4096];
// ACC_DTYPE<32> lhsdata3b[4096];
// ACC_DTYPE<32> lhsdata4b[4096];
//
// //GEMM 3 Inputs
// ACC_DTYPE<32> lhsdata1c[4096];
// ACC_DTYPE<32> lhsdata2c[4096];
// ACC_DTYPE<32> lhsdata3c[4096];
// ACC_DTYPE<32> lhsdata4c[4096];
//
// //GEMM 4 Inputs
// ACC_DTYPE<32> lhsdata1d[4096];
// ACC_DTYPE<32> lhsdata2d[4096];
// ACC_DTYPE<32> lhsdata3d[4096];
// ACC_DTYPE<32> lhsdata4d[4096];
//Global Weights
ACC_DTYPE<32> rhsdata1[8192];
ACC_DTYPE<32> rhsdata2[8192];
ACC_DTYPE<32> rhsdata3[8192];
ACC_DTYPE<32> rhsdata4[8192];
//First Set (A)
ACC_DTYPE<32> rhs1a_1[2048];
ACC_DTYPE<32> rhs1b_1[2048];
ACC_DTYPE<32> rhs1c_1[2048];
ACC_DTYPE<32> rhs1d_1[2048];
ACC_DTYPE<32> rhs2a_1[2048];
ACC_DTYPE<32> rhs2b_1[2048];
ACC_DTYPE<32> rhs2c_1[2048];
ACC_DTYPE<32> rhs2d_1[2048];
ACC_DTYPE<32> rhs3a_1[2048];
ACC_DTYPE<32> rhs3b_1[2048];
ACC_DTYPE<32> rhs3c_1[2048];
ACC_DTYPE<32> rhs3d_1[2048];
ACC_DTYPE<32> rhs4a_1[2048];
ACC_DTYPE<32> rhs4b_1[2048];
ACC_DTYPE<32> rhs4c_1[2048];
ACC_DTYPE<32> rhs4d_1[2048];
// //First Set (A)
// ACC_DTYPE<32> rhs1a_1[1024];
// ACC_DTYPE<32> rhs1b_1[1024];
// ACC_DTYPE<32> rhs1c_1[1024];
// ACC_DTYPE<32> rhs1d_1[1024];
//
// ACC_DTYPE<32> rhs2a_1[1024];
// ACC_DTYPE<32> rhs2b_1[1024];
// ACC_DTYPE<32> rhs2c_1[1024];
// ACC_DTYPE<32> rhs2d_1[1024];
//
// ACC_DTYPE<32> rhs3a_1[1024];
// ACC_DTYPE<32> rhs3b_1[1024];
// ACC_DTYPE<32> rhs3c_1[1024];
// ACC_DTYPE<32> rhs3d_1[1024];
//
// ACC_DTYPE<32> rhs4a_1[1024];
// ACC_DTYPE<32> rhs4b_1[1024];
// ACC_DTYPE<32> rhs4c_1[1024];
// ACC_DTYPE<32> rhs4d_1[1024];
//new sums bram
ACC_DTYPE<32> lhs_sum1[512];
ACC_DTYPE<32> lhs_sum2[512];
ACC_DTYPE<32> lhs_sum3[512];
ACC_DTYPE<32> lhs_sum4[512];
ACC_DTYPE<32> rhs_sum1[512];
ACC_DTYPE<32> rhs_sum2[512];
ACC_DTYPE<32> rhs_sum3[512];
ACC_DTYPE<32> rhs_sum4[512];
//crf & crx
ACC_DTYPE<32> crf1[512];
ACC_DTYPE<32> crf2[512];
ACC_DTYPE<32> crf3[512];
ACC_DTYPE<32> crf4[512];
ACC_DTYPE<32> crx[512];
int ra=0;
sc_fifo<int> WRQ1;
sc_fifo<int> WRQ2;
sc_fifo<int> WRQ3;
sc_fifo<int> WRQ4;
sc_signal<int> w1S;
sc_signal<int> w2S;
sc_signal<int> w3S;
sc_signal<int> w4S;
#ifndef __SYNTHESIS__
int weight_max_index=0;
int input_max_index=0;
int local_weight_max_index=0;
int g1_macs=0;
int g2_macs=0;
int g3_macs=0;
int g4_macs=0;
int g1_out_count=0;
int g2_out_count=0;
int g3_out_count=0;
int g4_out_count=0;
#endif
sc_out<int> inS;
sc_out<int> read_cycle_count;
sc_out<int> process_cycle_count;
sc_out<int> gemm_1_idle;
sc_out<int> gemm_2_idle;
sc_out<int> gemm_3_idle;
sc_out<int> gemm_4_idle;
sc_out<int> gemm_1_write;
sc_out<int> gemm_2_write;
sc_out<int> gemm_3_write;
sc_out<int> gemm_4_write;
sc_out<int> gemm_1;
sc_out<int> gemm_2;
sc_out<int> gemm_3;
sc_out<int> gemm_4;
sc_out<int> wstall_1;
sc_out<int> wstall_2;
sc_out<int> wstall_3;
sc_out<int> wstall_4;
sc_out<int> rmax;
sc_out<int> lmax;
sc_out<int> outS;
sc_out<int> w1SS;
sc_out<int> w2SS;
sc_out<int> w3SS;
sc_out<int> w4SS;
sc_out<int> schS;
sc_out<int> p1S;
void Input_Handler();
void Output_Handler();
void Worker1();
void Worker2();
void Worker3();
void Worker4();
void Data_In1();
void Data_In2();
void Data_In3();
void Data_In4();
void Tracker();
void Scheduler();
void Post1();
void Post2();
void Post3();
void Post4();
void Arranger1();
void Arranger2();
void Arranger3();
void Arranger4();
void WSync1();
void WSync2();
void WSync3();
void WSync4();
void load_weights(int,int);
void schedule_gemm_unit(int, int, int, int);
int SHR(int,int);
void overwrite_weights_check();
void Read_Cycle_Counter();
void Process_Cycle_Counter();
void Writer_Cycle_Counter();
SC_HAS_PROCESS(ACCNAME);
// Parameters for the DUT
ACCNAME(sc_module_name name_) :sc_module(name_),WRQ1(512), WRQ2(512), WRQ3(512), WRQ4(512){
SC_CTHREAD(Input_Handler,clock.pos());
reset_signal_is(reset,true);
SC_CTHREAD(Worker1,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Worker2,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Worker3,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Worker4,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Output_Handler,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Data_In1,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Data_In2,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Data_In3,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Data_In4,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Scheduler,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Post1,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Post2,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Post3,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Post4,clock);
reset_signal_is(reset,true);
SC_CTHREAD(WSync1,clock);
reset_signal_is(reset,true);
SC_CTHREAD(WSync2,clock);
reset_signal_is(reset,true);
SC_CTHREAD(WSync3,clock);
reset_signal_is(reset,true);
SC_CTHREAD(WSync4,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Arranger1,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Arranger2,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Arranger3,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Arranger4,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Read_Cycle_Counter,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Process_Cycle_Counter,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Writer_Cycle_Counter,clock);
reset_signal_is(reset,true);
#pragma HLS RESOURCE variable=din1 core=AXI4Stream metadata="-bus_bundle S_AXIS_DATA1" port_map={{din1_0 TDATA} {din1_1 TLAST}}
#pragma HLS RESOURCE variable=din2 core=AXI4Stream metadata="-bus_bundle S_AXIS_DATA2" port_map={{din2_0 TDATA} {din2_1 TLAST}}
#pragma HLS RESOURCE variable=din3 core=AXI4Stream metadata="-bus_bundle S_AXIS_DATA3" port_map={{din3_0 TDATA} {din3_1 TLAST}}
#pragma HLS RESOURCE variable=din4 core=AXI4Stream metadata="-bus_bundle S_AXIS_DATA4" port_map={{din4_0 TDATA} {din4_1 TLAST}}
#pragma HLS RESOURCE variable=dout1 core=AXI4Stream metadata="-bus_bundle M_AXIS_DATA1" port_map={{dout1_0 TDATA} {dout1_1 TLAST}}
#pragma HLS RESOURCE variable=dout2 core=AXI4Stream metadata="-bus_bundle M_AXIS_DATA2" port_map={{dout2_0 TDATA} {dout2_1 TLAST}}
#pragma HLS RESOURCE variable=dout3 core=AXI4Stream metadata="-bus_bundle M_AXIS_DATA3" port_map={{dout3_0 TDATA} {dout3_1 TLAST}}
#pragma HLS RESOURCE variable=dout4 core=AXI4Stream metadata="-bus_bundle M_AXIS_DATA4" port_map={{dout4_0 TDATA} {dout4_1 TLAST}}
#pragma HLS RESET variable=reset
}
};
#endif /* ACC_H */
|
#include <systemc.h>
SC_MODULE( tb )
{
sc_in<bool> clk;
sc_out<bool> rst;
sc_out< sc_int<16> > inp;
sc_out<bool> inp_vld;
sc_in<bool> inp_rdy;
sc_in< sc_int<16> > outp;
sc_in<bool> outp_vld;
sc_out<bool> outp_rdy;
void source();
void sink();
FILE *outfp;
sc_time start_time[64], end_time[64], clock_period;
SC_HAS_PROCESS( tb );
tb( sc_module_name nm );
};
|
#pragma once
#include <systemc.h>
#include "../../UTIL/debug_util.h"
#include "../../UTIL/fifo.h"
#define x12x2_size 130
SC_MODULE(x1_multiplier)
{
// input :
sc_in<sc_bv<320>> IN_RX0;
sc_in<bool> SELECT_HIGHER_BITS_RX0;
sc_in<bool> SIGNED_RES_RX0;
sc_in<bool> X02X1_EMPTY_SX0;
sc_in<bool> X12X2_POP_SX2;
// output :
sc_out<sc_bv<128>> RES_RX1;
sc_out<bool> SELECT_HIGHER_BITS_RX1;
sc_out<bool> SIGNED_RES_RX1;
sc_out<bool> X12X2_EMPTY_SX1;
sc_out<bool> X02X1_POP_SX1;
// General interace :
sc_in_clk CLK;
sc_in<bool> RESET;
//data from input
sc_signal<sc_bv<64>> M[5];
//Res from stage 6
sc_signal<sc_bv<64>> product_s6[4];
//Res from stage 7
sc_signal<sc_bv<64>> product_s7[2];
//Res from stage 8
sc_signal<sc_bv<64>> product_s8[2];
// fifo x12x2
sc_signal<sc_bv<x12x2_size>> x12x2_din_sx1;
sc_signal<sc_bv<x12x2_size>> x12x2_dout_sx1;
sc_signal<bool> x12x2_full_sx1;
sc_signal<bool> x12x2_push_sx1;
fifo<x12x2_size> fifo_inst;
void parse_data();
//stage 6 (2 CSA)
void CSA1();
void CSA2();
//stage 7 (1 CSA remind product_s6 M3)
void CSA3();
//stage 8 (1 CSA)
void CSA4();
void manage_fifo();
void fifo_concat();
void fifo_unconcat();
void trace(sc_trace_file* tf);
SC_CTOR(x1_multiplier) :
fifo_inst("x12x2")
{
fifo_inst.DIN_S(x12x2_din_sx1);
fifo_inst.DOUT_R(x12x2_dout_sx1);
fifo_inst.EMPTY_S(X12X2_EMPTY_SX1);
fifo_inst.FULL_S(x12x2_full_sx1);
fifo_inst.PUSH_S(x12x2_push_sx1);
fifo_inst.POP_S(X12X2_POP_SX2);
fifo_inst.CLK(CLK);
fifo_inst.RESET_N(RESET);
SC_METHOD(parse_data);
sensitive << IN_RX0;
SC_METHOD(CSA1);
sensitive << M[0] << M[1] << M[2];
SC_METHOD(CSA3);
sensitive << product_s6[0] << product_s6[1] << M[3];
SC_METHOD(CSA4);
sensitive << product_s7[0] << product_s7[1] << M[4];
SC_METHOD(manage_fifo);
sensitive << x12x2_full_sx1 << X02X1_EMPTY_SX0;
SC_METHOD(fifo_concat);
sensitive << SELECT_HIGHER_BITS_RX0 << product_s8[0] << product_s8[1] << SIGNED_RES_RX0;
SC_METHOD(fifo_unconcat);
sensitive << x12x2_dout_sx1;
}
}; |
#pragma once
#include <systemc.h>
//#include "../CORE/core.h"
#include "../../CORE/core.h"
#include "CACHES/icache.h"
#include "CACHES/dcache.h"
#include "wb_river_mc.h"
SC_MODULE(IP_RIVER)
{
sc_in_clk CLK;
sc_in<bool> RESET_N;
//interface bus
sc_in<bool> ACK;
sc_in<sc_uint<32>> DAT_I;
sc_in<bool> GRANT;
sc_in<sc_uint<32>> ADR_I;
sc_out<sc_uint<32>> ADR;
sc_out<sc_uint<32>> DAT_O;
sc_out<sc_uint<2>> SEL;
sc_out<bool> STB;
sc_out<bool> WE;
sc_out<bool> CYC;
// DCache-Core
sc_signal<sc_uint<32>> DATA_ADR_SM;
sc_signal<sc_uint<32>> DATA_SM;
sc_signal<bool> VALID_ADR_SM;
sc_signal<bool> STORE_SM;
sc_signal<bool> LOAD_SM;
sc_signal<sc_uint<2>> MEM_SIZE_SM;
sc_signal<sc_uint<32>> DATA_SDC;
sc_signal<bool> STALL_SDC;
// ICache-Core
sc_signal<sc_uint<32>> ADR_SI;
sc_signal<bool> ADR_VALID_SI;
sc_signal<sc_bv<32>> INST_SIC;
sc_signal<bool> STALL_SIC;
//DCache-Wrapper
sc_signal<bool> READ_SDC;
sc_signal<bool> WRITE_SDC;
sc_signal<bool> DTA_VALID_SDC;
sc_signal<sc_uint<32>> DCACHE_DT;
sc_signal<sc_uint<32>> A_SDC;
sc_signal<sc_uint<2>> SIZE_SDC;
sc_signal<sc_uint<32>> WRAPPER_DT;
sc_signal<bool> DCACHE_ACK;
sc_signal<bool> STALL_SW;
//ICache-Wrapper
sc_signal<bool> ICACHE_ACK;
sc_signal<sc_uint<32>> ICACHE_DT;
sc_signal<sc_uint<32>> A_SIC;
sc_signal<bool> DTA_VALID_SIC;
//Debug CORE
sc_in<sc_uint<32>> PC_RESET;
sc_out<sc_uint<32>> PC_VALUE;
sc_in<sc_uint<32>> PROC_ID;
void trace(sc_trace_file*);
core core_inst;
icache icache_inst;
dcache dcache_inst;
wb_river_mc wrapper_inst;
SC_CTOR(IP_RIVER):
core_inst("core"),
icache_inst("icache"),
dcache_inst("dcache"),
wrapper_inst("wb_river_mc")
{
//CORE map
core_inst.CLK(CLK);
core_inst.RESET(RESET_N);
core_inst.DEBUG_PC_READ(PC_VALUE);
core_inst.PC_INIT(PC_RESET);
core_inst.PROC_ID(PROC_ID);
core_inst.MCACHE_ADR_SM(DATA_ADR_SM);
core_inst.MCACHE_DATA_SM(DATA_SM);
core_inst.MCACHE_ADR_VALID_SM(VALID_ADR_SM);
core_inst.MCACHE_STORE_SM(STORE_SM);
core_inst.MCACHE_LOAD_SM(LOAD_SM);
core_inst.MCACHE_RESULT_SM(DATA_SDC);
core_inst.MCACHE_STALL_SM(STALL_SDC);
core_inst.MEM_SIZE_SM(MEM_SIZE_SM);
core_inst.ADR_SI(ADR_SI);
core_inst.ADR_VALID_SI(ADR_VALID_SI);
core_inst.INST_SIC(INST_SIC);
core_inst.STALL_SIC(STALL_SIC);
//DCache map
dcache_inst.CLK(CLK);
dcache_inst.RESET_N(RESET_N);
dcache_inst.DATA_ADR_SM(DATA_ADR_SM);
dcache_inst.DATA_SM(DATA_SM);
dcache_inst.LOAD_SM(LOAD_SM);
dcache_inst.STORE_SM(STORE_SM);
dcache_inst.VALID_ADR_SM(VALID_ADR_SM);
dcache_inst.MEM_SIZE_SM(MEM_SIZE_SM);
dcache_inst.DATA_SDC(DATA_SDC);
dcache_inst.STALL_SDC(STALL_SDC);
dcache_inst.DTA_VALID_SDC(DTA_VALID_SDC);
dcache_inst.READ_SDC(READ_SDC);
dcache_inst.WRITE_SDC(WRITE_SDC);
dcache_inst.SIZE_SDC(SIZE_SDC);
dcache_inst.DT_SDC(DCACHE_DT);
dcache_inst.A_SDC(A_SDC);
dcache_inst.DT_SW(WRAPPER_DT);
dcache_inst.ACK_SW(DCACHE_ACK);
dcache_inst.ADR_SW(ADR_I);
dcache_inst.GRANT(GRANT); // signal for snoopy control
dcache_inst.STALL_SW(STALL_SW);
//ICache map
icache_inst.CLK(CLK);
icache_inst.RESET_N(RESET_N);
icache_inst.ADR_SI(ADR_SI);
icache_inst.ADR_VALID_SI(ADR_VALID_SI);
icache_inst.INST_SIC(INST_SIC);
icache_inst.STALL_SIC(STALL_SIC);
icache_inst.DT_SW(ICACHE_DT);
icache_inst.A_SIC(A_SIC);
icache_inst.DTA_VALID_SIC(DTA_VALID_SIC);
icache_inst.ACK_SW(ICACHE_ACK);
icache_inst.STALL_SW(STALL_SW);
//Wrapper map
wrapper_inst.CLK(CLK);
wrapper_inst.RESET_N(RESET_N);
wrapper_inst.DAT_I(DAT_I);
wrapper_inst.ACK_I(ACK);
wrapper_inst.DAT_O(DAT_O);
wrapper_inst.ADR_O(ADR);
wrapper_inst.SEL_O(SEL);
wrapper_inst.WE_O(WE);
wrapper_inst.STB_O(STB);
wrapper_inst.A_IC(A_SIC);
wrapper_inst.DTA_VALID_IC(DTA_VALID_SIC);
wrapper_inst.DT_IC(ICACHE_DT);
wrapper_inst.ACK_IC(ICACHE_ACK);
wrapper_inst.DTA_VALID_DC(DTA_VALID_SDC);
wrapper_inst.READ_DC(READ_SDC);
wrapper_inst.WRITE_DC(WRITE_SDC);
wrapper_inst.SIZE_SEL_DC(SIZE_SDC);
wrapper_inst.DT_DC(DCACHE_DT);
wrapper_inst.A_DC(A_SDC);
wrapper_inst.DT_RM(WRAPPER_DT);
wrapper_inst.ACK_DC(DCACHE_ACK);
wrapper_inst.GRANT_I(GRANT);
wrapper_inst.CYC_O(CYC);
wrapper_inst.STALL_SW(STALL_SW);
}
}; |
/* Copyright 2017 Pedro Cuadra <[email protected]> & Meghadoot Gardi
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License. */
#ifndef DECODER_H_
#define DECODER_H_
#include<systemc.h>
SC_MODULE (decoder) {
sc_in<bool> a, b, carry_in;
sc_out<bool> sum, carry_out;
void prc_decoder();
SC_CTOR (decoder) {
SC_METHOD (prc_decoder);
sensitive << a << b << carry_in;
}
};
#endif
|
/*******************************************************************************
* cd4067.cpp -- Copyright 2019 (c) Glenn Ramalho - RFIDo Design
*******************************************************************************
* Description:
* This is a simple model for the CD4067 Analog Mux.
*******************************************************************************
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
#include <systemc.h>
#include "info.h"
#include "cd4067.h"
int cd4067::get_selector() {
return
(((d.read())?1:0) << 3) |
(((c.read())?1:0) << 2) |
(((b.read())?1:0) << 1) |
((a.read())?1:0);
}
void cd4067::process_th() {
int line;
bool channel_is_driver = false;
x.write(GN_LOGIC_Z);
for(line = 0; line < channel.size(); line = line + 1)
channel[line]->write(GN_LOGIC_Z);
sel = get_selector();
bool recheck = false;
while(true) {
/* If the recheck is high, this means the selector changed and we need
* to refigure out who is driving.
*/
if (recheck) {
/* We wait a time stamp and redo the driving. */
wait(1, SC_NS);
recheck = false;
/* In these cases, we just keep everyone at Z. */
if (inh.read() || sel >= channel.size()) continue;
/* We check who is the driver and drive the other. If they are both
* being driven, we drive X everywhere.
*/
if (x.read() == GN_LOGIC_Z) {
channel_is_driver = true;
x.write(channel[sel]->read());
}
else if (channel[sel]->read()==GN_LOGIC_Z) {
channel_is_driver = false;
channel[sel]->write(x.read());
}
else {
PRINTF_WARN("TEST", "Two drivers on MUX");
channel[sel]->write(GN_LOGIC_X);
x.write(GN_LOGIC_X);
}
continue;
}
/* We wait for one either a change in the selector or a change in
* either side of the mux. If the selector is pointing to an illegal
* value, we then just wait for a change in the selector.
*/
if (sel >= channel.size())
wait(a->default_event() | b->default_event() | c->default_event()
| d->default_event() | inh->default_event());
else wait(channel[sel]->default_event()
| a->default_event() | b->default_event() | c->default_event()
| d->default_event() | inh->default_event() | x->default_event());
bool sel_triggered =
a->value_changed_event().triggered() ||
b->value_changed_event().triggered() ||
c->value_changed_event().triggered() ||
d->value_changed_event().triggered();
if (debug) {
/* If the sel is illegal, we only can process the selector. */
if (sel >= channel.size())
printf("%s: sel = %d, triggers: sel %c, inh %c, x %c\n",
name(), sel, (sel_triggered)?'t':'f',
(inh->value_changed_event().triggered())?'t':'f',
(x->value_changed_event().triggered())?'t':'f');
else printf(
"%s: sel = %d, triggers: channel %c, sel %c, inh %c, x %c\n",
name(), sel,
(channel[sel]->value_changed_event().triggered())?'t':'f',
(sel_triggered)?'t':'f',
(inh->value_changed_event().triggered())?'t':'f',
(x->value_changed_event().triggered())?'t':'f');
}
/* If inh went high we shut it all off, it does not matter who triggered
* what.
*/
if (inh.read() == GN_LOGIC_1) {
x.write(GN_LOGIC_Z);
if (sel < channel.size()) channel[sel]->write(GN_LOGIC_Z);
channel_is_driver = false;
}
/* If inh came back, we then need to resolve. */
else if (inh.value_changed_event().triggered()) {
/* No need to drive Z if it is already. */
recheck = true;
channel_is_driver = false;
}
/* Now we check the selector. If it changed, we need to drive Z and
* recheck. This is because it is difficult to check every single
* driver in a signal to find out what is going on.
*/
else if (sel_triggered) {
int newsel = get_selector();
/* We now drive Z everywhere. */
if (sel < channel.size()) channel[sel]->write(GN_LOGIC_Z);
x.write(GN_LOGIC_Z);
channel_is_driver = false;
/* And we update the selector variable. */
sel = newsel;
/* And if the new selector is valid, we do a recheck. */
if (sel < channel.size()) recheck = true;
}
/* If the selector is not valid, we just ignore any activity on either
* side as there can't be any change. We simply drive Z everywhere.
* Note: this path is a safety one, it is probably never called.
*/
else if (sel >= channel.size()) {
channel_is_driver = false;
x.write(GN_LOGIC_Z);
}
/* When we update a output pin, there is always a reflection. If both
* sides have the same value, this probably was a reflection, so we
* can dump it.
*/
else if (x.read() == channel[sel]->read()) continue;
/* We have an analog mux. In a real mux system, we would do a fight
* between the sides and eventually settle to something. This is a
* digital simulator though, so we need a simplification. If I get a
* driver on one side, we drive that value on the other.
*/
else if (channel[sel]->value_changed_event().triggered()
&& (channel_is_driver || x.read() == GN_LOGIC_Z)) {
channel_is_driver = true;
x.write(channel[sel]->read());
}
else if (x.default_event().triggered()
&& (!channel_is_driver || channel[sel]->read() == GN_LOGIC_Z)) {
channel_is_driver = false;
channel[sel]->write(x.read());
}
/* If there are drivers on both sides, we need to put X on both sides.
* Note: the current model will not leave this state unless there is
* an inh or sel change.
*/
else {
PRINTF_WARN("TEST", "Two drivers on MUX");
channel[sel]->write(GN_LOGIC_X);
x.write(GN_LOGIC_X);
}
}
}
void cd4067::trace(sc_trace_file *tf) {
sc_trace(tf, x, x.name());
sc_trace(tf, a, a.name());
sc_trace(tf, b, b.name());
sc_trace(tf, c, c.name());
sc_trace(tf, d, d.name());
sc_trace(tf, inh, inh.name());
}
|
/**
#define meta ...
prInt32f("%s\n", meta);
**/
/*
All rights reserved to Alireza Poshtkohi (c) 1999-2023.
Email: [email protected]
Website: http://www.poshtkohi.info
*/
#ifndef __s8_h__
#define __s8_h__
#include <systemc.h>
SC_MODULE(s8)
{
sc_in<sc_uint<6> > stage1_input;
sc_out<sc_uint<4> > stage1_output;
void s8_box();
SC_CTOR(s8)
{
SC_METHOD(s8_box);
sensitive << stage1_input;
}
};
#endif
|
#ifndef LOCAL_TEST_UTILS_H
#define LOCAL_TEST_UTILS_H
// Needed for all tests
#include <Gemmini.h>
static Gemmini g("g");
static sc_signal<sc_biguint<7>> funct_write;
static sc_signal<sc_biguint<64>> rs1;
static sc_signal<sc_biguint<64>> rs2;
static sc_signal<sc_biguint<7>> opcode;
#define FUNCT_CONFIG 0
#define FUNCT_LOAD1 2
#define CONFIG_TYPE_MVIN 0b01
#define ACC_MVIN_ACCTYPE 0
#define ACC_MVIN_INPUTTYPE 1
#define CONFIG_MVIN1 0
#define CONFIG_MVIN2 1
#define CONFIG_MVIN3 2
#define OPCODE_CUSTOM3 0b1111011
#define ARRAY_DIM 16
enum test_status {SUCCESS, FAIL, UNFINISHED};
#include <systemc.h>
#include <include/gemmini_testutils.h>
#include <endian.h>
#endif |
#ifndef I_CACHE
#define I_CACHE
#include <systemc.h>
#include "../../../UTIL/debug_util.h"
SC_MODULE(icache)
{
// interface global
sc_in_clk CLK;
sc_in<bool> RESET_N;
// interface RiVer
sc_in<sc_uint<32> > ADR_SI;
sc_in<bool> ADR_VALID_SI;
sc_out<sc_bv<32> > INST_SIC;
sc_out<bool> STALL_SIC;
//interface wrapper
sc_in<sc_uint<32>> DT_SW;
sc_out<sc_uint<32>> A_SIC;
sc_out<bool> DTA_VALID_SIC;
sc_in<bool> ACK_SW;
sc_in<bool> STALL_SW;
//signals
sc_signal<sc_bv<32>> data[256][4];
sc_signal<sc_uint<20>> tag[256];
sc_signal<bool> data_validate[256];
sc_signal<sc_uint<20>> address_tag;
sc_signal<sc_uint<8>> address_index;
sc_signal<sc_uint<4>> address_offset;
sc_signal<sc_uint<20>> current_address_tag;
sc_signal<sc_uint<8>> current_address_index;
sc_signal<bool> hit;
sc_signal<sc_uint<3>> fsm_state;
void trace(sc_trace_file*);
void parse_adr();
void miss_detection();
void transition();
SC_CTOR(icache)
{
SC_METHOD(parse_adr);
sensitive << ADR_SI;
SC_METHOD(miss_detection);
sensitive << address_tag
<< address_index
<< address_offset
<< STALL_SIC;
for(int i=0; i < 256 ;i++){
sensitive << data[i][0]
<< data[i][1]
<< data[i][2]
<< data[i][3]
<< data_validate[i];
}
SC_THREAD(transition);
sensitive << CLK.neg();
reset_signal_is(RESET_N, false);
}
};
#endif |
/*******************************************************************************
Vendor: GoodKook, [email protected]
Associated Filename: sc_dffrs_TB.cpp
Purpose: Testbench
Revision History: Aug. 1, 2024
*******************************************************************************/
#ifndef _SC_DFFRS_TB_H_
#define _SC_DFFRS_TB_H_
#include <systemc.h>
#include "Vdffrs.h" // Verilated DUT
SC_MODULE(sc_dffrs_TB)
{
sc_clock clk;
sc_signal<bool> r, s, d, q;
Vdffrs* u_Vdffrs;
sc_trace_file* fp; // VCD file
SC_CTOR(sc_dffrs_TB): // constructor
clk("clk", 100, SC_NS, 0.5, 0.0, SC_NS, false)
{
// instantiate DUT
u_Vdffrs = new Vdffrs("u_Vdffrs");
// Binding
u_Vdffrs->clk(clk);
u_Vdffrs->r(r);
u_Vdffrs->s(s);
u_Vdffrs->d(d);
u_Vdffrs->q(q);
SC_THREAD(test_generator);
sensitive << clk;
// VCD Trace
fp = sc_create_vcd_trace_file("sc_dffrs_TB");
sc_trace(fp, clk, "clk");
sc_trace(fp, r, "r");
sc_trace(fp, s, "s");
sc_trace(fp, d, "d");
sc_trace(fp, q, "q");
}
void test_generator()
{
int test_count =0;
r.write(1);
s.write(1);
d.write(0);
while(true)
{
wait(clk.posedge_event());
wait(clk.negedge_event());
s.write(0);
wait(clk.posedge_event());
s.write(1);
wait(clk.negedge_event());
r.write(0);
wait(clk.posedge_event());
r.write(1);
wait(clk.posedge_event());
d = 1;
wait(clk.posedge_event());
d = false;
wait(clk.negedge_event());
d = 1;
wait(clk.posedge_event());
d = 0;
wait(clk.posedge_event());
d = 1;
wait(clk.posedge_event());
wait(clk.posedge_event());
r.write(1);
s.write(1);
d.write(1);
wait(clk.posedge_event());
r.write(0);
s.write(0);
//d.write(0);
wait(clk.posedge_event());
r.write(1);
s.write(1);
d.write(0);
wait(clk.posedge_event());
s.write(0);
wait(clk.posedge_event());
s.write(1);
wait(clk.posedge_event());
// Ending stimulus
wait(clk.posedge_event());
wait(clk.posedge_event());
sc_close_vcd_trace_file(fp);
sc_stop();
}
}
};
#endif
|
/**
* @file sc_clk.h
* @brief This file contains the SystemC module for the clock
* @ingroup systemc_modules
*/
#ifndef SC_CLK_H
#define SC_CLK_H
#include <systemc.h>
#include "sc_config.h"
//#include "sc_run.h"
SC_MODULE(scClk)
{
sc_out<bool> clk{"clk_o"};
SC_CTOR(scClk)
{
SC_THREAD(clockThread);
}
void clockThread ()
{
sc_time ustep = sc_getMicrostep();
int semiperiod_usteps = sc_getClkSemiperiodMicrosteps();
bool act_edge = sc_getClkActEdge();
while(1)
{
clk.write(act_edge);
for (int i = 0; i < semiperiod_usteps; i++)
{
wait(ustep);
}
clk.write(!act_edge);
for (int i = 0; i < semiperiod_usteps; i++)
{
wait(ustep);
}
}
}
};
#endif // SC_CLK_H
|
/*******************************************************************************
Vendor: GoodKook, [email protected]
Associated Filename: sc_beh_shifter_TB.cpp
Purpose: Testbench
Revision History: Aug. 1, 2024
*******************************************************************************/
#ifndef _SC_BEH_SHIFTER_TB_H_
#define _SC_BEH_SHIFTER_TB_H_
#include <systemc.h>
#include "Vbeh_shifter.h" // Verilated DUT
SC_MODULE(sc_beh_shifter_TB)
{
sc_clock clk;
sc_signal<bool> rst;
sc_signal<uint32_t> din, qout;
Vbeh_shifter* u_Vbeh_shifter;
sc_trace_file* fp; // SystemC VCD file
SC_CTOR(sc_beh_shifter_TB): // constructor
clk("clk", 100, SC_NS, 0.5, 0.0, SC_NS, false)
{
// instantiate DUT
u_Vbeh_shifter = new Vbeh_shifter("u_Vbeh_shifter");
// Binding
u_Vbeh_shifter->clk(clk);
u_Vbeh_shifter->rst(rst);
u_Vbeh_shifter->din(din);
u_Vbeh_shifter->qout(qout);
SC_THREAD(test_generator);
sensitive << clk;
// VCD Trace
fp = sc_create_vcd_trace_file("sc_shifter_TB");
sc_trace(fp, clk, "clk");
sc_trace(fp, rst, "rst");
sc_trace(fp, din, "din");
sc_trace(fp, qout, "qout");
}
void test_generator()
{
int test_count =0;
din.write(0);
rst.write(0);
wait(clk.posedge_event());
wait(clk.posedge_event());
rst.write(1);
wait(clk.posedge_event());
while(true)
{
din.write(1);
wait(clk.posedge_event());
if (test_count>6)
{
sc_close_vcd_trace_file(fp);
sc_stop();
}
else
test_count++;
}
}
};
#endif
|
/*
* Created on: 21. jun. 2019
* Author: Jonathan Horsted Schougaard
*/
#pragma once
#define SC_INCLUDE_FX
#include "hwcore/cnn/data_buffer.h"
#include "hwcore/cnn/pe.h"
#include "hwcore/cnn/top_cnn.h"
#include "hwcore/cnn/weight_buffer.h"
#include "hwcore/hw/statusreg.h"
#include "hwcore/pipes/pipes.h"
#include <systemc.h>
#ifdef __RTL_SIMULATION__
#include "syn/systemc/cnn.h"
#endif
#ifndef P_data_P
#define P_data_P 2
#warning Using defualt parameter!
#endif
#ifndef P_data_W
#define P_data_W 16
#warning Using defualt parameter!
#endif
#ifndef P_input_width
#define P_input_width 128
#warning Using defualt parameter!
#endif
#ifndef P_output_width
#define P_output_width 128
#warning Using defualt parameter!
#endif
// calculatd parameter
#define P_input_BW_N (P_input_width / P_data_W)
#define P_output_BW_N (P_output_width / P_data_W)
// end
#ifndef P_pe_n
#define P_pe_n 8
#warning Using defualt parameter!
#endif
#ifndef P_pe_bw_n
#define P_pe_bw_n P_input_BW_N
#warning Using defualt parameter!
#endif
#ifndef P_wbuf_size
#define P_wbuf_size 3072
#warning Using defualt parameter!
#endif
#ifndef P_data_buf_clb_size
#define P_data_buf_clb_size 8192
#warning Using defualt parameter!
#endif
#ifndef P_data_buf_clb_n
#define P_data_buf_clb_n 3
#warning Using defualt parameter!
#endif
#ifndef P_data_buf_shift_size
#define P_data_buf_shift_size 384
#warning Using defualt parameter!
#endif
#ifndef P_data_out_n
#define P_data_out_n 1
#warning Using defualt parameter!
#endif
#ifndef P_pool_size
#define P_pool_size 1024
#warning Using defualt parameter!
#endif
#if P_pool_size < 512
#error bad pool size!!!
#endif
#ifndef P_PE_pipeline_II
#define P_PE_pipeline_II 1
#warning Using defualt parameter!
#endif
#ifndef P_pe_pre_fifo_deep
#define P_pe_pre_fifo_deep 1
#warning Using defualt parameter!
#endif
#ifndef P_X_fifo_deep
#define P_X_fifo_deep 1
#warning Using defualt parameter!
#endif
#ifndef P_W_fifo_deep
#define P_W_fifo_deep 1
#warning Using defualt parameter!
#endif
#ifndef P_Y_fifo_deep
#define P_Y_fifo_deep 1
#warning Using defualt parameter!
#endif
#ifndef P_BUF_fifo_deep
#define P_BUF_fifo_deep 1
#warning Using defualt parameter!
#endif
SC_MODULE(cnn) {
// typedef
typedef hwcore::cnn::top_cnn<P_data_W, P_data_P, P_input_BW_N, P_output_BW_N, P_pe_n, P_pe_bw_n, P_wbuf_size,
P_data_buf_clb_size, P_data_buf_clb_n, P_data_buf_shift_size, P_data_out_n,
P_pool_size, P_PE_pipeline_II, P_pe_pre_fifo_deep>
top_cnn_t;
// interface
SC_MODULE_CLK_RESET_SIGNAL;
sc_fifo_in<hwcore::pipes::SC_DATA_T(P_input_width)> data_sink;
sc_fifo_in<hwcore::pipes::SC_DATA_T(P_input_width)> data_buf_sink;
sc_fifo_in<hwcore::pipes::SC_DATA_T(P_input_width)> w_sink;
sc_fifo_in<hwcore::pipes::SC_DATA_T(64)> ctrl_sink;
sc_fifo_out<hwcore::pipes::SC_DATA_T(P_output_width)> data_source;
#if __RTL_SIMULATION__
sc_status_module_create_interface_only(reg1);
ap_rtl::cnn rtl_wrapper_cnn;
SC_FIFO_IN_TRANS<P_input_width> data_sink_trans;
SC_FIFO_IN_TRANS<P_input_width> data_buf_sink_trans;
SC_FIFO_IN_TRANS<P_input_width> w_sink_trans;
SC_FIFO_IN_TRANS<64> ctrl_sink_trans;
SC_FIFO_OUT_TRANS<P_output_width> data_source_trans;
sc_signal<sc_logic> reset_s;
sc_signal<sc_lv<32> > status_add_s;
sc_signal<sc_lv<32> > status_val_s;
void signal_connection() {
sc_dt::sc_logic reset_tmp = (sc_dt::sc_logic)reset.read();
reset_s.write(reset_tmp);
status_add_s.write(status_add.read());
status_val.write(status_val_s.read().to_int());
}
SC_CTOR(cnn)
: rtl_wrapper_cnn("rtl_wrapper_cnn"), data_sink_trans("data_sink_trans"),
data_buf_sink_trans("data_buf_sink_trans"), data_source_trans("data_source_trans"),
w_sink_trans("w_sink_trans"), ctrl_sink_trans("ctrl_sink_trans") {
// SC_MODULE_LINK(rtl_wrapper_cnn);
SC_FIFO_IN_TRANS_CONNECT(rtl_wrapper_cnn, data_sink_trans, data_sink);
SC_FIFO_IN_TRANS_CONNECT(rtl_wrapper_cnn, data_buf_sink_trans, data_buf_sink);
SC_FIFO_IN_TRANS_CONNECT(rtl_wrapper_cnn, w_sink_trans, w_sink);
SC_FIFO_IN_TRANS_CONNECT(rtl_wrapper_cnn, ctrl_sink_trans, ctrl_sink);
SC_FIFO_OUT_TRANS_CONNECT(rtl_wrapper_cnn, data_source_trans, data_source);
rtl_wrapper_cnn.clk(clk);
rtl_wrapper_cnn.reset(reset_s);
rtl_wrapper_cnn.status_add(status_add_s);
rtl_wrapper_cnn.status_val(status_val_s);
SC_METHOD(signal_connection);
sensitive << status_add << status_val_s << reset;
}
#else
sc_status_module_create(reg1);
sc_status_reg_create(r0_dma_ingress);
sc_status_reg_create(r1_dma_egress);
sc_status_reg_create(r2_data_W);
sc_status_reg_create(r3_data_P);
sc_status_reg_create(r4_input_BW_N);
sc_status_reg_create(r5_output_BW_N);
sc_status_reg_create(r6_pe_n);
sc_status_reg_create(r7_pe_bw_n);
sc_status_reg_create(r8_wbuf_size);
sc_status_reg_create(r9_data_buf_clb_size);
sc_status_reg_create(r10_data_buf_clb_n);
sc_status_reg_create(r11_data_buf_shift_size);
sc_status_reg_create(r12_data_out_n);
sc_status_end_create(regend);
void status_reg_param_link() {
r2_data_W_status.write(P_data_W);
r3_data_P_status.write(P_data_P);
r4_input_BW_N_status.write(P_input_BW_N);
r5_output_BW_N_status.write(P_pool_size);
r6_pe_n_status.write(P_pe_n);
r7_pe_bw_n_status.write(P_pe_bw_n);
r8_wbuf_size_status.write(P_wbuf_size);
r9_data_buf_clb_size_status.write(P_data_buf_clb_size);
r10_data_buf_clb_n_status.write(P_data_buf_clb_n);
r11_data_buf_shift_size_status.write(P_data_buf_shift_size);
r12_data_out_n_status.write(P_data_out_n);
}
sc_fifo<hwcore::pipes::SC_DATA_T(P_input_width)> data_sink_forward;
sc_fifo<hwcore::pipes::SC_DATA_T(P_input_width)> data_buf_sink_forward;
sc_fifo<hwcore::pipes::SC_DATA_T(P_input_width)> w_sink_forward;
sc_fifo<hwcore::pipes::SC_DATA_T(P_output_width)> data_source_forward;
sc_fifo<sc_uint<31> > weight_ctrls_fifo;
sc_fifo<sc_uint<32> > ctrl_image_size_fifo;
sc_fifo<sc_uint<16> > ctrl_row_size_pkg_fifo;
sc_fifo<sc_uint<16> > ctrl_window_size_fifo;
sc_fifo<sc_uint<16> > ctrl_depth_fifo;
sc_fifo<sc_uint<16> > ctrl_stride_fifo;
sc_fifo<sc_uint<16> > ctrl_replay_fifo;
sc_fifo<sc_uint<16> > ctrl_zeropad_fifo;
sc_fifo<sc_uint<1> > ctrl_output_channel_fifo;
sc_fifo<sc_uint<16> > ctrl_stitch_depth_fifo;
sc_fifo<sc_uint<16> > ctrl_stitch_buf_depth_fifo;
sc_fifo<sc_uint<1> > ctrl_db_output_fifo;
sc_fifo<sc_uint<1> > ctrl_image_data_fifo;
sc_fifo<sc_uint<16> > ctrl_pool_depth_fifo;
sc_fifo<sc_uint<16> > ctrl_pool_type_fifo;
sc_fifo<sc_uint<16> > ctrl_pool_N_fifo;
sc_fifo<sc_uint<16> > ctrl_pool_size_fifo;
sc_fifo<sc_uint<16> > ctrl_row_N_fifo;
sc_fifo<sc_uint<16> > ctrl_acf_fifo;
// modules
hwcore::cnn::top_cnn<P_data_W, P_data_P, P_input_BW_N, P_output_BW_N, P_pe_n, P_pe_bw_n, P_wbuf_size,
P_data_buf_clb_size, P_data_buf_clb_n, P_data_buf_shift_size, P_data_out_n>
top_cnn;
sc_status_reg_create_dummy(top_cnn_reg);
SC_CTOR(cnn)
: data_sink_forward(P_X_fifo_deep), data_buf_sink_forward(P_BUF_fifo_deep), w_sink_forward(P_W_fifo_deep),
data_source_forward(P_Y_fifo_deep), weight_ctrls_fifo(16), ctrl_row_size_pkg_fifo(16),
ctrl_window_size_fifo(16), ctrl_depth_fifo(16), ctrl_stride_fifo(16), ctrl_replay_fifo(16),
ctrl_row_N_fifo(16), ctrl_acf_fifo(16), ctrl_zeropad_fifo(16), SC_INST(top_cnn), SC_INST(reg1),
SC_INST(regend), SC_INST(r0_dma_ingress), SC_INST(r1_dma_egress), SC_INST(r2_data_W), SC_INST(r3_data_P),
SC_INST(r4_input_BW_N), SC_INST(r5_output_BW_N), SC_INST(r6_pe_n), SC_INST(r7_pe_bw_n), SC_INST(r8_wbuf_size),
SC_INST(r9_data_buf_clb_size), SC_INST(r10_data_buf_clb_n), SC_INST(r11_data_buf_shift_size),
SC_INST(r12_data_out_n), ctrl_output_channel_fifo(16), ctrl_db_output_fifo(16), ctrl_pool_depth_fifo(16),
ctrl_pool_type_fifo(16), ctrl_pool_N_fifo(16), ctrl_pool_size_fifo(16), ctrl_stitch_depth_fifo(16),
ctrl_stitch_buf_depth_fifo(1), ctrl_image_data_fifo(16)
{
top_cnn.clk(clk);
top_cnn.reset(reset);
/*SC_METHOD(reset_logic);
sensitive << reset << iclear;
SC_CTHREAD(clear_reg, clk.pos());*/
top_cnn.data_sink(data_sink_forward);
top_cnn.data_buf_sink(data_buf_sink_forward);
top_cnn.w_sink(w_sink_forward);
top_cnn.data_source(data_source_forward);
top_cnn.weight_ctrls_in(weight_ctrls_fifo);
// top_cnn.data_ctrls_in(data_ctrls_fifo);
top_cnn.ctrl_row_N(ctrl_row_N_fifo);
top_cnn.ctrl_row_size_pkg(ctrl_row_size_pkg_fifo);
top_cnn.ctrl_window_size(ctrl_window_size_fifo);
top_cnn.ctrl_depth(ctrl_depth_fifo);
top_cnn.ctrl_stride(ctrl_stride_fifo);
top_cnn.ctrl_replay(ctrl_replay_fifo);
top_cnn.ctrl_image_size(ctrl_image_size_fifo);
top_cnn.ctrl_acf(ctrl_acf_fifo);
top_cnn.ctrl_zeropad(ctrl_zeropad_fifo);
top_cnn.ctrl_output_channel(ctrl_output_channel_fifo);
top_cnn.ctrl_stitch_depth(ctrl_stitch_depth_fifo);
top_cnn.ctrl_stitch_buf_depth(ctrl_stitch_buf_depth_fifo);
top_cnn.ctrl_db_output(ctrl_db_output_fifo);
top_cnn.ctrl_image_data(ctrl_image_data_fifo);
top_cnn.ctrl_pool_depth(ctrl_pool_depth_fifo);
top_cnn.ctrl_pool_type(ctrl_pool_type_fifo);
top_cnn.ctrl_pool_N(ctrl_pool_N_fifo);
top_cnn.ctrl_pool_size(ctrl_pool_size_fifo);
// status reg
sc_status_module_connect(reg1);
sc_status_reg_connect(r0_dma_ingress, reg1);
sc_status_reg_connect(r1_dma_egress, r0_dma_ingress);
sc_status_reg_connect(r2_data_W, r1_dma_egress);
sc_status_reg_connect(r3_data_P, r2_data_W);
sc_status_reg_connect(r4_input_BW_N, r3_data_P);
sc_status_reg_connect(r5_output_BW_N, r4_input_BW_N);
sc_status_reg_connect(r6_pe_n, r5_output_BW_N);
sc_status_reg_connect(r7_pe_bw_n, r6_pe_n);
sc_status_reg_connect(r8_wbuf_size, r7_pe_bw_n);
sc_status_reg_connect(r9_data_buf_clb_size, r8_wbuf_size);
sc_status_reg_connect(r10_data_buf_clb_n, r9_data_buf_clb_size);
sc_status_reg_connect(r11_data_buf_shift_size, r10_data_buf_clb_n);
sc_status_reg_connect(r12_data_out_n, r11_data_buf_shift_size);
sc_status_end_connect(regend, r12_data_out_n);
SC_CTHREAD(thread_cnn_stream_source, clk.pos());
reset_signal_is(reset, true);
SC_CTHREAD(thread_cnn_stream_sink, clk.pos());
reset_signal_is(reset, true);
SC_CTHREAD(thread_cnn_stream_buf_sink, clk.pos());
reset_signal_is(reset, true);
SC_CTHREAD(thread_cnn_stream_w_sink, clk.pos());
reset_signal_is(reset, true);
SC_CTHREAD(thread_cnn_ctrl, clk.pos());
reset_signal_is(reset, true);
}
void thread_cnn_stream_source() {
SC_STREAM_INTERFACE_CREATE_SOURCE(data_source, "-bus_bundle M_AXIS_Y")
int count = 0;
while (true) {
hls_pipeline(1);
hwcore::pipes::SC_DATA_T(P_output_width) tmp_out = data_source_forward.read();
data_source.write(tmp_out);
count++;
r0_dma_ingress_status.write(count);
}
}
void thread_cnn_stream_sink() {
SC_STREAM_INTERFACE_CREATE_SINK(data_sink, "-bus_bundle S_AXIS_X")
int count = 0;
while (true) {
hls_pipeline(1);
hwcore::pipes::SC_DATA_T(P_input_width) tmp_in = data_sink.read();
data_sink_forward.write(tmp_in);
count++;
r1_dma_egress_status.write(count);
}
}
void thread_cnn_stream_buf_sink() {
SC_STREAM_INTERFACE_CREATE_SINK(data_buf_sink, "-bus_bundle S_AXIS_BUF")
while (true) {
hls_pipeline(1);
hwcore::pipes::SC_DATA_T(P_input_width) tmp_in = data_buf_sink.read();
data_buf_sink_forward.write(tmp_in);
}
}
void thread_cnn_stream_w_sink() {
SC_STREAM_INTERFACE_CREATE_SINK(w_sink, "-bus_bundle S_AXIS_W")
while (true) {
hls_pipeline(1);
hwcore::pipes::SC_DATA_T(P_input_width) tmp_in = w_sink.read();
w_sink_forward.write(tmp_in);
}
}
void thread_cnn_ctrl() {
SC_STREAM_INTERFACE_CREATE_SINK(ctrl_sink, "-bus_bundle S_AXIS_CTRL")
hwcore::pipes::SC_DATA_T(64) tmp_in;
status_reg_param_link();
while (true) {
do {
hls_pipeline(1);
tmp_in = ctrl_sink.read();
sc_uint<64> raw = tmp_in.data;
sc_uint<56> value = raw(56 - 1, 0);
sc_uint<8> address;
if (tmp_in.tkeep == 0) {
address = -1;
} else {
address = raw(64 - 1, 56);
}
#define add_new_reg_interface(name_, nr_) \
case nr_: \
name_##_fifo.write(value); \
break;
switch (address) {
add_new_reg_interface(weight_ctrls, 0);
add_new_reg_interface(ctrl_row_N, 1);
add_new_reg_interface(ctrl_row_size_pkg, 2);
add_new_reg_interface(ctrl_window_size, 3);
add_new_reg_interface(ctrl_depth, 4);
add_new_reg_interface(ctrl_stride, 5);
add_new_reg_interface(ctrl_replay, 6);
add_new_reg_interface(ctrl_image_size, 7);
add_new_reg_interface(ctrl_acf, 8);
add_new_reg_interface(ctrl_zeropad, 9);
add_new_reg_interface(ctrl_output_channel, 10);
add_new_reg_interface(ctrl_stitch_depth, 11);
add_new_reg_interface(ctrl_stitch_buf_depth, 12);
add_new_reg_interface(ctrl_db_output, 13);
add_new_reg_interface(ctrl_image_data, 14);
add_new_reg_interface(ctrl_pool_depth, 15);
add_new_reg_interface(ctrl_pool_type, 16);
add_new_reg_interface(ctrl_pool_N, 17);
add_new_reg_interface(ctrl_pool_size, 18);
default:
break;
};
} while (tmp_in.tlast == 0);
}
}
#endif
};
|
/**********************************************************************
Filename: sc_fir8_tb.h
Purpose : Testbench of 8-Tab Systolic FIR filter
Author : [email protected]
History : Mar. 2024, First release
***********************************************************************/
#ifndef _SC_FIR8_TB_H_
#define _SC_FIR8_TB_H_
#include <systemc.h>
#include "sc_fir8.h"
SC_MODULE(sc_fir8_tb)
{
sc_clock clk;
sc_signal<sc_uint<4> > Xin;
sc_signal<sc_uint<4> > Xout;
sc_signal<sc_uint<4> > Yin;
sc_signal<sc_uint<4> > Yout;
sc_signal<bool> Vld;
sc_signal<bool> Rdy;
#ifdef EMULATED
sc_signal<sc_uint<4> > E_Xout;
sc_signal<sc_uint<4> > E_Yout;
sc_signal<bool> E_Vld;
#endif
sc_fir8* u_sc_fir8;
// Test utilities
void Test_Gen();
void Test_Mon();
sc_uint<8> x[F_SAMPLE]; // Time seq. input
sc_uint<16> y[F_SAMPLE]; // Filter output
#ifdef VCD_TRACE_FIR8_TB
sc_trace_file* fp; // VCD file
#endif
SC_CTOR(sc_fir8_tb):
clk("clk", 100, SC_NS, 0.5, 0.0, SC_NS, false),
Vld("Vld"),
Rdy("Rdy"),
Xin("Xin"),
Xout("Xout"),
Yin("Yin"),
Yout("Yout")
{
SC_THREAD(Test_Gen);
sensitive << clk;
SC_THREAD(Test_Mon);
sensitive << clk;
// Instaltiate FIR8
u_sc_fir8 = new sc_fir8("u_sc_fir8");
u_sc_fir8->clk(clk);
u_sc_fir8->Xin(Xin);
u_sc_fir8->Xout(Xout);
u_sc_fir8->Yin(Yin);
u_sc_fir8->Yout(Yout);
u_sc_fir8->Rdy(Rdy);
u_sc_fir8->Vld(Vld);
#ifdef EMULATED
u_sc_fir8->E_Xout(E_Xout);
u_sc_fir8->E_Yout(E_Yout);
u_sc_fir8->E_Vld(E_Vld);
#endif
#ifdef VCD_TRACE_FIR8_TB
// WAVE
fp = sc_create_vcd_trace_file("sc_fir8_tb");
fp->set_time_unit(100, SC_PS); // resolution (trace) ps
sc_trace(fp, clk, "clk");
sc_trace(fp, Xin, "Xin");
sc_trace(fp, Xout, "Xout");
sc_trace(fp, Yin, "Yin");
sc_trace(fp, Yout, "Yout");
sc_trace(fp, Rdy, "Rdy");
sc_trace(fp, Vld, "Vld");
#endif
}
~sc_fir8_tb(void)
{
}
};
#endif |
#ifndef SC_CLK_H
#define SC_CLK_H
#include <systemc.h>
#include "sc_config.h"
#include "sc_run.h"
SC_MODULE (scClk) {
// --------------------- Ports ---------------------
sc_out<bool> clk{"clk_o"};
SC_CTOR(scClk) {
SC_THREAD(clockThread);
}
void clockThread () {
sc_time ustep = sc_getMicrostep();
int semiperiod_usteps = sc_getClkSemiperiodMicrosteps();
bool act_edge = sc_getClkActEdge();
while (1) {
clk.write(act_edge);
for (int i = 0; i < semiperiod_usteps; i++) {
wait(ustep);
}
clk.write(!act_edge);
for (int i = 0; i < semiperiod_usteps; i++) {
wait(ustep);
}
}
}
};
#endif // SC_CLK_H
|
/*******************************************************************************
* mux_pcnt.h -- Copyright 2019 (c) Glenn Ramalho - RFIDo Design
*******************************************************************************
* Description:
* Model for the PCNT mux in the GPIO matrix.
*******************************************************************************
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
#ifndef _MUX_PCNT_H
#define _MUX_PCNT_H
#include <systemc.h>
#include "pcntbus.h"
SC_MODULE(mux_pcnt) {
sc_port<sc_signal_in_if<bool>,0> mout_i {"mout_i"};
sc_port<sc_signal_out_if<pcntbus_t>,8> pcntbus_o {"pcntbus_o"};
int function[8][4];
sc_event fchange_ev;
/* Functions */
void mux(int bit, int gpiosel);
void initialize();
/* Threads */
void transfer(int function);
SC_CTOR(mux_pcnt) { initialize(); }
};
#endif
|
#ifndef RGB2GRAY_TLM_CPP
#define RGB2GRAY_TLM_CPP
#include <systemc.h>
using namespace sc_core;
using namespace sc_dt;
using namespace std;
#include <tlm.h>
#include <tlm_utils/simple_initiator_socket.h>
#include <tlm_utils/simple_target_socket.h>
#include <tlm_utils/peq_with_cb_and_phase.h>
#include "rgb2gray_tlm.hpp"
#include "common_func.hpp"
void rgb2gray_tlm::do_when_read_transaction(unsigned char*& data, unsigned int data_length, sc_dt::uint64 address){
unsigned char pixel_value;
pixel_value = this->obtain_gray_value();
dbgimgtarmodprint(use_prints, "%0u", pixel_value);
memcpy(data, &pixel_value, sizeof(char));
}
void rgb2gray_tlm::do_when_write_transaction(unsigned char*&data, unsigned int data_length, sc_dt::uint64 address){
unsigned char rgb_values[3];
int j = 0;
for (unsigned char *i = data; (i - data) < 3; i++)
{
rgb_values[j] = *i;
dbgimgtarmodprint(use_prints, "VAL: %0ld -> %0u", i - data, *i);
j++;
}
this->set_rgb_pixel(rgb_values[0], rgb_values[1], rgb_values[2]);
}
#endif // RGB2GRAY_TLM_CPP
|
#ifndef SC_RST_H
#define SC_RST_H
#include <systemc.h>
#include "sc_config.h"
SC_MODULE (scRst) {
sc_out<bool> rst_o{"rst_o"};
SC_CTOR(scRst) {
SC_THREAD(resetThread);
}
void resetThread () {
sc_time ustep = sc_getMicrostep();
bool act_level = sc_getRstActLevel();
int act_usteps =sc_getRstActMicrosteps();
while (1) {
rst_o.write(act_level);
for (int i = 0; i < act_usteps; i++) {
wait(ustep);
}
rst_o.write(!act_level);
for (;;) {
wait(ustep);
}
}
}
};
#endif // SC_RST_H
|
#ifndef TESTBENCH_
#define TESTBENCH_
#include <systemc.h>
SC_MODULE (tbreg){
//l'horloge
sc_in <bool> clk;
sc_out < sc_uint<11> > din;
sc_in < sc_uint<15> > coded_dout;
sc_out < sc_uint<15> > coded_din;
sc_in < sc_uint<11> > dout;
//hand shake signals
sc_out < bool > din_vld;
sc_in < bool > din_rdy;
sc_in < bool > codedout_vld;
sc_out < bool > codedout_rdy;
sc_out < bool > codedin_vld;
sc_in < bool > codedin_rdy;
sc_in < bool > dout_vld;
sc_out < bool > dout_rdy;
void send();
void receive();
SC_CTOR(tbreg){
SC_CTHREAD(send,clk);
SC_CTHREAD(receive,clk);
sensitive << clk.pos();
}
};
#endif
|
/**********************************************************************
Filename: E_fir_pe.h
Purpose : Emulated PE of Systolic FIR filter
Author : [email protected]
History : Mar. 2024, First release
***********************************************************************/
#ifndef _E_FIR_PE_H_
#define _E_FIR_PE_H_
#include <systemc.h>
// Includes for accessing Arduino via serial port
#include <stdio.h>
#include <string.h>
#include <unistd.h>
#include <fcntl.h>
#include <termios.h>
SC_MODULE(E_fir_pe)
{
sc_in<bool> clk;
sc_in<sc_uint<8> > Cin;
sc_in<sc_uint<8> > Xin;
sc_out<sc_uint<8> > Xout;
sc_in<sc_uint<16> > Yin;
sc_out<sc_uint<16> > Yout;
#define N_TX 4
#define N_RX 3
void pe_thread(void)
{
uint8_t x, y, txPacket[N_TX], rxPacket[N_RX];
while(true)
{
wait(clk.posedge_event());
txPacket[3] = (uint8_t)(Yin.read()); // LSB of Yin
txPacket[2] = (uint8_t)(Yin.read()>>8); // MSB of Yin
txPacket[1] = (uint8_t)Xin.read(); // Xin
txPacket[0] = (uint8_t)Cin.read(); // Cin
// Send to Emulator
for (int i=0; i<N_TX; i++)
{
x = txPacket[i];
while(write(fd, &x, 1)<=0) usleep(1);
}
// Receive from Emulator
for (int i=0; i<N_RX; i++)
{
while(read(fd, &y, 1)<=0) usleep(1);
rxPacket[i] = y;
}
Xout.write( (uint8_t)rxPacket[0]);
Yout.write((uint16_t)rxPacket[1]<<8 | (uint16_t)rxPacket[2]);
}
}
// Arduino Serial IF
int fd; // Serial port file descriptor
struct termios options; // Serial port setting
SC_CTOR(E_fir_pe):
clk("clk"),
Cin("Cin"), Xin("Xin"), Xout("Xout"),
Yin("Yin"), Yout("Yout")
{
SC_THREAD(pe_thread);
sensitive << clk;
// Arduino DUT
//fd = open("/dev/ttyACM0", O_RDWR | O_NDELAY | O_NOCTTY);
fd = open("/dev/ttyACM0", O_RDWR | O_NOCTTY);
if (fd < 0)
{
perror("Error opening serial port");
return;
}
// Set up serial port
options.c_cflag = B115200 | CS8 | CLOCAL | CREAD;
options.c_iflag = IGNPAR;
options.c_oflag = 0;
options.c_lflag = 0;
// Apply the settings
tcflush(fd, TCIFLUSH);
tcsetattr(fd, TCSANOW, &options);
// Establish Contact
int len = 0;
char rx;
while(!len)
len = read(fd, &rx, 1);
if (rx=='A')
write(fd, &rx, 1);
printf("Connection established...\n");
}
~E_fir_pe(void)
{
}
};
#endif
|
/*******************************************************************************
* <DIRNAME>test.h -- Copyright 2019 (c) Glenn Ramalho - RFIDo Design
*******************************************************************************
* Description:
* This is the main testbench header for the test. It describes how
* the model should be wired up and connected to any monitors.
*******************************************************************************
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
#include <systemc.h>
#include <Arduino.h>
#include "doitesp32devkitv1.h"
#include "uartclient.h"
SC_MODULE(<DIRNAME>test) {
/* Signals */
sc_signal<bool> led {"led"};
gn_signal_mix d2_a12 {"d2_a12"};
gn_signal_mix rx {"rx"};
gn_signal_mix tx {"tx"};
sc_signal<unsigned int> fromwifi {"fromwifi"};
sc_signal<unsigned int> towifi {"towifi"};
/* Note: these will soon be replaced with better interfaces. */
sc_signal<unsigned int> fromflash {"fromflash"};
sc_signal<unsigned int> toflash {"toflash"};
sc_signal<bool> fromi2c {"fromi2c"};
sc_signal<bool> toi2c {"toi2c"};
/* Unconnected signals */
gn_signal_mix logic_0 {"logic_0", GN_LOGIC_0};
/* blocks */
doitesp32devkitv1 i_esp{"i_esp"};
uartclient i_uartclient{"i_uartclient"};
netcon_mixtobool i_netcon{"i_netcon"};
/* Processes */
void testbench(void);
void serflush(void);
/* Tests */
unsigned int tn; /* Testcase number */
void t0();
// Constructor
SC_CTOR(<DIRNAME>test) {
/* UART 0 - we connect the wires to the corresponding tasks. Yes, the
* RX and TX need to be switched.
*/
i_esp.d3(rx); i_uartclient.tx(rx);
i_esp.d1(tx); i_uartclient.rx(tx);
/* LED */
i_esp.d2_a12(d2_a12);
i_netcon.a(d2_a12);
i_netcon.b(led);
/* We connect the waveform to these. */
/* Other interfaces, none are used so they are just left floating. */
i_esp.wrx(fromwifi); i_esp.wtx(towifi);
/* Note: these two will soon be replaced with the real flash and I2C
* interfaces, as soon as someone takes the time to implement them. */
i_esp.frx(fromflash); i_esp.ftx(toflash);
i_esp.irx(fromi2c); i_esp.itx(toi2c);
/* Pins not used in this simulation */
i_esp.d0_a11(logic_0); /* BOOT pin */
i_esp.d12_a15(logic_0); i_esp.d21(logic_0);
i_esp.d26_a19(logic_0); i_esp.d27_a17(logic_0);
i_esp.d4_a10(logic_0); i_esp.d5(logic_0);
i_esp.d14_a16(logic_0);
i_esp.d15_a13(logic_0); i_esp.d16(logic_0);
i_esp.d17(logic_0); i_esp.d18(logic_0); i_esp.d19(logic_0);
i_esp.d23(logic_0);
i_esp.d25_a18(logic_0);
i_esp.d33_a5(logic_0); i_esp.d34_a6(logic_0);
i_esp.d35_a7(logic_0); i_esp.d36_a0(logic_0); i_esp.d37_a1(logic_0);
i_esp.d38_a2(logic_0); i_esp.d39_a3(logic_0);
i_esp.d13_a14(logic_0); i_esp.d22(logic_0); i_esp.d32_a4(logic_0);
SC_THREAD(testbench);
SC_THREAD(serflush);
}
void trace(sc_trace_file *tf);
void start_of_simulation();
};
|
#ifndef __full_adder_h__
#define __full_adder_h__
#include <systemc.h>
//---------------------------------------
SC_MODULE(full_adder)
{
public: sc_in<bool> a, b, cin;
public: sc_out<bool> sum, cout;
//---------------------------------------
public: SC_CTOR(full_adder)
{
SC_METHOD(process);
sensitive << a << b << cin;
}
//---------------------------------------
private: void process()
{
bool aANDb, aXORb, cinANDaXORb;
aANDb = a.read() & b.read();
aXORb = a.read() ^ b.read();
cinANDaXORb = cin.read() & aXORb;
//Calculate sum and carry out of the 1-BIT adder
sum = aXORb ^ cin.read();
cout = aANDb | cinANDaXORb;
//next_trigger(1, SC_NS);
}
//---------------------------------------
};
//---------------------------------------
#endif
|
#ifndef AXIS_ENGINE_H
#define AXIS_ENGINE_H
#include <systemc.h>
#include "sysc_types.h"
SC_MODULE(AXIS_ENGINE) {
sc_in<bool> clock;
sc_in<bool> reset;
sc_fifo_in<DATA> dout1;
sc_fifo_out<DATA> din1;
bool send;
bool recv;
int id;
void DMA_MMS2() {
while (1) {
while (!send) wait();
for (int i = 0; i < input_len; i++) {
int d = DMA_input_buffer[i + input_offset];
din1.write({d, 1});
wait();
}
send = false;
wait();
sc_pause();
wait();
}
};
void DMA_S2MM() {
while (1) {
while (!recv) wait();
bool last = false;
int i = 0;
do {
DATA d = dout1.read();
while (i >= output_len) wait();
last = d.tlast;
int k = d.data;
DMA_output_buffer[output_offset + i++] = d.data;
wait();
} while (!last);
output_len = i;
recv = false;
// // To ensure wait_send() does not evoke the sc_pause
// while (send)
// wait(2);
wait();
sc_pause();
wait();
}
};
SC_HAS_PROCESS(AXIS_ENGINE);
AXIS_ENGINE(sc_module_name name_) : sc_module(name_) {
SC_CTHREAD(DMA_MMS2, clock.pos());
reset_signal_is(reset, true);
SC_CTHREAD(DMA_S2MM, clock.pos());
reset_signal_is(reset, true);
}
int* DMA_input_buffer;
int* DMA_output_buffer;
int input_len;
int input_offset;
int output_len;
int output_offset;
};
#endif |
#ifndef ACCNAME_H
#define ACCNAME_H
#include <systemc.h>
#include "tensorflow/lite/delegates/utils/secda_tflite/sysc_integrator/sysc_types.h"
#ifndef __SYNTHESIS__
#define DWAIT(x) wait(x)
#else
#define DWAIT(x)
#endif
#define ACCNAME TOY_ADD
#define ACC_DTYPE sc_uint
#define ACC_C_DTYPE unsigned int
#define STOPPER -1
#define IN_BUF_LEN 4096
#define WE_BUF_LEN 8192
#define SUMS_BUF_LEN 1024
#define MAX 2147483647
#define MIN -2147483648
#define POS 1073741824
#define NEG -1073741823
#define DIVMAX 2147483648
#define MAX8 127
#define MIN8 -128
SC_MODULE(ACCNAME) {
sc_in<bool> clock;
sc_in<bool> reset;
sc_fifo_in<DATA> din1;
sc_fifo_out<DATA> dout1;
// GEMM 1 Inputs
ACC_DTYPE<32> A1[IN_BUF_LEN];
ACC_DTYPE<32> A2[IN_BUF_LEN];
ACC_DTYPE<32> B1[IN_BUF_LEN];
ACC_DTYPE<32> B2[IN_BUF_LEN];
ACC_DTYPE<32> C1[IN_BUF_LEN * 4];
ACC_DTYPE<32> C2[IN_BUF_LEN * 4];
int qm;
sc_int<8> shift;
#ifndef __SYNTHESIS__
sc_signal<int, SC_MANY_WRITERS> lenX;
sc_signal<int, SC_MANY_WRITERS> lenY;
sc_signal<bool, SC_MANY_WRITERS> computeX;
sc_signal<bool, SC_MANY_WRITERS> computeY;
sc_signal<bool, SC_MANY_WRITERS> readX;
sc_signal<bool, SC_MANY_WRITERS> readY;
sc_signal<bool, SC_MANY_WRITERS> writeX;
sc_signal<bool, SC_MANY_WRITERS> writeY;
#else
sc_signal<int> lenX;
sc_signal<int> lenY;
sc_signal<bool> computeX;
sc_signal<bool> computeY;
sc_signal<bool> readX;
sc_signal<bool> readY;
sc_signal<bool> writeX;
sc_signal<bool> writeY;
#endif
void Control();
void Data_Read();
void PE_Add();
void Data_Write();
int Quantised_Multiplier(int, int, sc_int<8>);
SC_HAS_PROCESS(ACCNAME);
ACCNAME(sc_module_name name_) : sc_module(name_) {
SC_CTHREAD(Control, clock);
reset_signal_is(reset, true);
SC_CTHREAD(Data_Read, clock);
reset_signal_is(reset, true);
SC_CTHREAD(PE_Add, clock);
reset_signal_is(reset, true);
SC_CTHREAD(Data_Write, clock);
reset_signal_is(reset, true);
#pragma HLS RESOURCE variable = din1 core = AXI4Stream metadata = \
"-bus_bundle S_AXIS_DATA1" port_map = { \
{din1_0 TDATA } { \
din1_1 TLAST } }
#pragma HLS RESOURCE variable = dout1 core = AXI4Stream metadata = \
"-bus_bundle M_AXIS_DATA1" port_map = { \
{dout1_0 TDATA } { \
dout1_1 TLAST } }
}
};
#endif |
// TODO Generalise this code so it is easy for all new accelerators
#ifndef SYSTEMC_INTEGRATE
#define SYSTEMC_INTEGRATE
#include <systemc.h>
#include "../ap_sysc/hls_bus_if.h"
// #include "tb_driver.h"
int sc_main(int argc, char* argv[]) { return 0; }
void sysC_init() {
sc_report_handler::set_actions("/IEEE_Std_1666/deprecated", SC_DO_NOTHING);
sc_report_handler::set_actions(SC_ID_LOGIC_X_TO_BOOL_, SC_LOG);
sc_report_handler::set_actions(SC_ID_VECTOR_CONTAINS_LOGIC_VALUE_, SC_LOG);
}
// struct systemC_sigs {
// sc_clock clk_fast;
// sc_signal<bool> sig_reset;
// hls_bus_chn<unsigned long long> insn_mem;
// hls_bus_chn<unsigned long long> inp_mem;
// hls_bus_chn<unsigned long long> wgt_mem;
// hls_bus_chn<unsigned int> out_mem;
// hls_bus_chn<unsigned long long> bias_mem;
// sc_signal<unsigned int> sig_start_acc;
// sc_signal<unsigned int> sig_done_acc;
// sc_signal<unsigned int> sig_reset_acc;
// sc_signal<unsigned int> sig_insn_count;
// sc_signal<unsigned int> sig_insn_addr;
// sc_signal<unsigned int> sig_input_addr;
// sc_signal<unsigned int> sig_weight_addr;
// sc_signal<unsigned int> sig_bias_addr;
// sc_signal<unsigned int> sig_output_addr;
// sc_signal<int> sig_depth;
// sc_signal<int> sig_crf;
// sc_signal<int> sig_crx;
// sc_signal<int> sig_ra;
// int id;
// systemC_sigs(int _id)
// : insn_mem("insn_port", 0, 81920),
// inp_mem("input_port", 0, 409600),
// wgt_mem("weight_port", 0, 409600),
// bias_mem("bias_port", 0, 409600),
// out_mem("out_port", 0, 409600) {
// sc_clock clk_fast("ClkFast", 1, SC_NS);
// id = _id;
// }
// };
// void systemC_binder(ACCNAME* acc, TB_Driver* tb_driver, int _insns_mem_size,
// int _uops_mem_size, int _data_mem_size, systemC_sigs* scs) {
// acc->clock(scs->clk_fast);
// acc->reset(scs->sig_reset);
// acc->start_acc(scs->sig_start_acc);
// acc->done_acc(scs->sig_done_acc);
// acc->reset_acc(scs->sig_reset_acc);
// acc->insn_count(scs->sig_insn_count);
// acc->insn_addr(scs->sig_insn_addr);
// acc->input_addr(scs->sig_input_addr);
// acc->weight_addr(scs->sig_weight_addr);
// acc->bias_addr(scs->sig_bias_addr);
// acc->output_addr(scs->sig_output_addr);
// acc->depth(scs->sig_depth);
// acc->crf(scs->sig_crf);
// acc->crx(scs->sig_crx);
// acc->ra(scs->sig_ra);
// acc->insn_port(scs->insn_mem);
// acc->input_port(scs->inp_mem);
// acc->weight_port(scs->wgt_mem);
// acc->bias_port(scs->bias_mem);
// acc->out_port(scs->out_mem);
// tb_driver->clock(scs->clk_fast);
// tb_driver->reset(scs->sig_reset);
// }
#endif // SYSTEMC_INTEGRATE
|
/*******************************************************************************
* readMifaretest.h -- Copyright 2019 (c) Glenn Ramalho - RFIDo Design
*******************************************************************************
* File: readMifaretest.h
* Project: IWM testbench
*******************************************************************************
* Description:
* This is the main testbench header for the test. It describes how
* the model should be wired up and connected to any monitors.
*******************************************************************************
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
#include <systemc.h>
#include <Arduino.h>
#include "uartclient.h"
#include "doitesp32devkitv1_i2c.h"
#include "pn532.h"
SC_MODULE(readMifaretest) {
/* Signals */
gn_signal_mix i2c_sda {"i2c_sda"};
gn_signal_mix i2c_scl {"i2c_scl"};
gn_signal_mix pn532_reset {"pn532_reset"};
gn_signal_mix pn532_irq {"pn532_irq"};
gn_signal_mix led {"led"};
gn_signal_mix rx {"rx"};
gn_signal_mix tx {"tx"};
sc_signal<unsigned int> fromwifi {"fromwifi"};
sc_signal<unsigned int> towifi {"towifi"};
/* Note: these will soon be replaced with better interfaces. */
sc_signal<unsigned int> fromflash {"fromflash"};
sc_signal<unsigned int> toflash {"toflash"};
/* Unconnected signals */
gn_signal_mix logic_0 {"logic_0", GN_LOGIC_0};
/* blocks */
doitesp32devkitv1_i2c i_esp{"i_esp"};
pn532 i_pn532 {"i_pn532"};
uartclient i_uartclient{"i_uartclient"};
/* Processes */
void testbench(void);
void serflush(void);
/* Tests */
unsigned int tn; /* Testcase number */
void t0();
// Constructor
SC_CTOR(readMifaretest) {
/* UART 0 - we connect the wires to the corresponding tasks. Yes, the
* RX and TX need to be switched.
*/
i_esp.d3(rx); i_uartclient.tx(rx);
i_esp.d1(tx); i_uartclient.rx(tx);
/* LED */
i_esp.d2_a12(led);
/* Other interfaces, none are used so they are just left floating. */
i_esp.wrx(fromwifi); i_esp.wtx(towifi);
/* Note: these two will soon be replaced with the real flash and I2C
* interfaces, as soon as someone takes the time to implement them. */
i_esp.frx(fromflash); i_esp.ftx(toflash);
i_esp.d13_a14(pn532_reset);
i_esp.d12_a15(pn532_irq);
/* I2C BUS */
i_esp.d21(i2c_sda); i_esp.d22(i2c_scl);
i_pn532.sda(i2c_sda); i_pn532.scl(i2c_scl);
i_pn532.irq(pn532_irq); i_pn532.reset(pn532_reset);
/* Pins not used in this simulation */
i_esp.d0_a11(logic_0); /* BOOT pin */
i_esp.d26_a19(logic_0); i_esp.d27_a17(logic_0);
i_esp.d4_a10(logic_0); i_esp.d5(logic_0);
i_esp.d14_a16(logic_0);
i_esp.d15_a13(logic_0); i_esp.d16(logic_0);
i_esp.d17(logic_0); i_esp.d18(logic_0); i_esp.d19(logic_0);
i_esp.d23(logic_0);
i_esp.d25_a18(logic_0);
i_esp.d33_a5(logic_0); i_esp.d34_a6(logic_0);
i_esp.d35_a7(logic_0); i_esp.d36_a0(logic_0); i_esp.d37_a1(logic_0);
i_esp.d38_a2(logic_0); i_esp.d39_a3(logic_0);
i_esp.d32_a4(logic_0);
SC_THREAD(testbench);
SC_THREAD(serflush);
}
void start_of_simulation();
void trace(sc_trace_file *tf);
};
|
/*******************************************************************************
* SerialToSerialBTtest.h -- Copyright 2019 (c) Glenn Ramalho - RFIDo Design
*******************************************************************************
* Description:
* This is the main testbench header for the test. It describes how
* the model should be wired up and connected to any monitors.
*******************************************************************************
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
#include <systemc.h>
#include <Arduino.h>
#include "doitesp32devkitv1_bt.h"
#include "btclient.h"
#include "uartclient.h"
SC_MODULE(SerialToSerialBTtest) {
/* Signals */
sc_signal<bool> led {"led"};
gn_signal_mix d2_a12 {"d2_a12"};
gn_signal_mix rx {"rx"};
gn_signal_mix tx {"tx"};
sc_signal<unsigned int> fromwifi {"fromwifi"};
sc_signal<unsigned int> towifi {"towifi"};
sc_signal<unsigned int> frombt {"frombt"};
sc_signal<unsigned int> tobt {"tobt"};
/* Note: these will soon be replaced with better interfaces. */
sc_signal<unsigned int> fromflash {"fromflash"};
sc_signal<unsigned int> toflash {"toflash"};
sc_signal<bool> fromi2c {"fromi2c"};
sc_signal<bool> toi2c {"toi2c"};
/* Unconnected signals */
gn_signal_mix logic_0 {"logic_0", GN_LOGIC_0};
/* blocks */
doitesp32devkitv1_bt i_esp{"i_esp"};
uartclient i_uartclient{"i_uartclient"};
netcon_mixtobool i_netcon{"i_netcon"};
btclient i_btclient{"i_btclient"};
/* Processes */
void testbench(void);
void serflush(void);
/* Tests */
unsigned int tn; /* Testcase number */
void t0();
// Constructor
SC_CTOR(SerialToSerialBTtest) {
/* UART 0 - we connect the wires to the corresponding tasks. Yes, the
* RX and TX need to be switched.
*/
i_esp.d3(rx); i_uartclient.tx(rx);
i_esp.d1(tx); i_uartclient.rx(tx);
/* LED */
i_esp.d2_a12(d2_a12);
i_netcon.a(d2_a12);
i_netcon.b(led);
/* The bluetooth is wireless, but we need to connect it to something
* in the model, so we use this cchan interface.
*/
i_esp.brx(frombt); i_btclient.tx(frombt);
i_esp.btx(tobt); i_btclient.rx(tobt);
/* We connect the waveform to these. */
/* Other interfaces, none are used so they are just left floating. */
i_esp.wrx(fromwifi); i_esp.wtx(towifi);
/* Note: these two will soon be replaced with the real flash and I2C
* interfaces, as soon as someone takes the time to implement them. */
i_esp.frx(fromflash); i_esp.ftx(toflash);
/* Pins not used in this simulation */
i_esp.d0_a11(logic_0); /* BOOT pin */
i_esp.d12_a15(logic_0); i_esp.d21(logic_0);
i_esp.d26_a19(logic_0); i_esp.d27_a17(logic_0);
i_esp.d4_a10(logic_0); i_esp.d5(logic_0);
i_esp.d14_a16(logic_0);
i_esp.d15_a13(logic_0); i_esp.d16(logic_0);
i_esp.d17(logic_0); i_esp.d18(logic_0); i_esp.d19(logic_0);
i_esp.d23(logic_0);
i_esp.d25_a18(logic_0);
i_esp.d33_a5(logic_0); i_esp.d34_a6(logic_0);
i_esp.d35_a7(logic_0); i_esp.d36_a0(logic_0); i_esp.d37_a1(logic_0);
i_esp.d38_a2(logic_0); i_esp.d39_a3(logic_0);
i_esp.d13_a14(logic_0); i_esp.d22(logic_0); i_esp.d32_a4(logic_0);
SC_THREAD(testbench);
SC_THREAD(serflush);
}
void trace(sc_trace_file *tf);
void start_of_simulation();
};
|
//****************************************************************************************
// MIT License
//****************************************************************************************
// Copyright (c) 2012-2020 University of Bremen, Germany.
// Copyright (c) 2015-2020 DFKI GmbH Bremen, Germany.
// Copyright (c) 2020 Johannes Kepler University Linz, Austria.
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all
// copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
//****************************************************************************************
#include <crave/experimental/SystemC.hpp>
#include <crave/ConstrainedRandom.hpp>
#include <systemc.h>
#include <boost/timer.hpp>
#include <crave/experimental/Experimental.hpp>
using crave::crv_sequence_item;
using crave::crv_constraint;
using crave::crv_variable;
using crave::crv_object_name;
using sc_dt::sc_bv;
using sc_dt::sc_uint;
using crave::dist;
using crave::distribution;
using crave::reference;
struct ALU12 : public crv_sequence_item {
crv_variable<sc_bv<2> > op;
crv_variable<sc_uint<12> > a, b;
crv_constraint c_dist{ "dist" };
crv_constraint c_add{ "add" };
crv_constraint c_sub{ "sub" };
crv_constraint c_mul{ "mul" };
crv_constraint c_div{ "div" };
ALU12(crv_object_name) {
c_dist = { dist(op(), distribution<short>::simple_range(0, 3)) };
c_add = {(op() != 0x0) || (4095 >= a() + b()) };
c_sub = {(op() != 0x1) || ((4095 >= a() - b()) && (b() <= a())) };
c_mul = {(op() != 0x2) || (4095 >= a() * b()) };
c_div = {(op() != 0x3) || (b() != 0) };
}
friend std::ostream& operator<<(std::ostream& o, ALU12 const& alu) {
o << alu.op << ' ' << alu.a << ' ' << alu.b;
return o;
}
};
int sc_main(int argc, char** argv) {
crave::init("crave.cfg");
boost::timer timer;
ALU12 c("ALU");
CHECK(c.randomize());
std::cout << "first: " << timer.elapsed() << "\n";
for (int i = 0; i < 1000; ++i) {
CHECK(c.randomize());
std::cout << c << std::endl;
}
std::cout << "complete: " << timer.elapsed() << "\n";
return 0;
}
|
#ifndef ACCNAME_H
#define ACCNAME_H
#include <systemc.h>
#include "tensorflow/lite/delegates/utils/secda_tflite/sysc_integrator/sysc_types.h"
#ifndef __SYNTHESIS__
#define DWAIT(x) wait(x)
#else
#define DWAIT(x)
#endif
#define ACCNAME TOY_ADD
#define ACC_DTYPE sc_uint
#define ACC_C_DTYPE unsigned int
#define STOPPER -1
#define IN_BUF_LEN 4096
#define WE_BUF_LEN 8192
#define SUMS_BUF_LEN 1024
#define MAX 2147483647
#define MIN -2147483648
#define POS 1073741824
#define NEG -1073741823
#define DIVMAX 2147483648
#define MAX8 127
#define MIN8 -128
SC_MODULE(ACCNAME) {
sc_in<bool> clock;
sc_in<bool> reset;
sc_fifo_in<DATA> din1;
sc_fifo_out<DATA> dout1;
// GEMM 1 Inputs
ACC_DTYPE<32> A1[IN_BUF_LEN];
ACC_DTYPE<32> A2[IN_BUF_LEN];
ACC_DTYPE<32> B1[IN_BUF_LEN];
ACC_DTYPE<32> B2[IN_BUF_LEN];
ACC_DTYPE<32> C1[IN_BUF_LEN * 4];
ACC_DTYPE<32> C2[IN_BUF_LEN * 4];
int qm;
sc_int<8> shift;
#ifndef __SYNTHESIS__
sc_signal<int, SC_MANY_WRITERS> lenX;
sc_signal<int, SC_MANY_WRITERS> lenY;
sc_signal<bool, SC_MANY_WRITERS> computeX;
sc_signal<bool, SC_MANY_WRITERS> computeY;
sc_signal<bool, SC_MANY_WRITERS> readX;
sc_signal<bool, SC_MANY_WRITERS> readY;
sc_signal<bool, SC_MANY_WRITERS> writeX;
sc_signal<bool, SC_MANY_WRITERS> writeY;
#else
sc_signal<int> lenX;
sc_signal<int> lenY;
sc_signal<bool> computeX;
sc_signal<bool> computeY;
sc_signal<bool> readX;
sc_signal<bool> readY;
sc_signal<bool> writeX;
sc_signal<bool> writeY;
#endif
void Control();
void Data_Read();
void PE_Add();
void Data_Write();
int Quantised_Multiplier(int, int, sc_int<8>);
SC_HAS_PROCESS(ACCNAME);
ACCNAME(sc_module_name name_) : sc_module(name_) {
SC_CTHREAD(Control, clock);
reset_signal_is(reset, true);
SC_CTHREAD(Data_Read, clock);
reset_signal_is(reset, true);
SC_CTHREAD(PE_Add, clock);
reset_signal_is(reset, true);
SC_CTHREAD(Data_Write, clock);
reset_signal_is(reset, true);
#pragma HLS RESOURCE variable = din1 core = AXI4Stream metadata = \
"-bus_bundle S_AXIS_DATA1" port_map = { \
{din1_0 TDATA } { \
din1_1 TLAST } }
#pragma HLS RESOURCE variable = dout1 core = AXI4Stream metadata = \
"-bus_bundle M_AXIS_DATA1" port_map = { \
{dout1_0 TDATA } { \
dout1_1 TLAST } }
}
};
#endif |
#ifndef D_CACHE
#define D_CACHE
#include <systemc.h>
#include "buffercache.h"
#include "../../../UTIL/debug_util.h"
//cache N-way associatif, write through et buffet
// taille du cache 1024
// buffer de taille 2
// 2-way => 1024/2 => 512 / 4mots => 128 lignes
// index => 7 bits
// offset => 4 mots => 2 bits
// tag => 23 bits
//communication direct avec la MP (pas de bus ni BCU)
// C: cache M: memory P: MP
//acronym_X
#define WAY_SIZE 128
typedef enum // MAE STATES
{
DC_IDLE = 0,
DC_WAIT_MEM = 1,
DC_UPDT = 2
} dcache_states_fsm;
SC_MODULE(dcache)
{
sc_in_clk CLK;
sc_in<bool> RESET_N;
// interface processeur
sc_in<sc_uint<32>> DATA_ADR_SM;
sc_in<sc_uint<32>> DATA_SM;
sc_in<bool> LOAD_SM;
sc_in<bool> STORE_SM;
sc_in<bool> VALID_ADR_SM;
sc_in<sc_uint<2>> MEM_SIZE_SM;
sc_out<sc_uint<32>> DATA_SDC;
sc_out<bool> STALL_SDC; // if stall donc miss else hit
// interface wrapper
sc_out<bool> DTA_VALID_SDC;
sc_out<bool> READ_SDC;
sc_out<bool> WRITE_SDC;
sc_out<sc_uint<2>> SIZE_SDC;
sc_out<sc_uint<32>> DT_SDC;
sc_out<sc_uint<32>> A_SDC;
sc_in<sc_uint<32>> DT_SW;
sc_in<bool> ACK_SW; // slave answer (slave dt valid)
sc_in<sc_uint<32>> ADR_SW;
sc_in<bool> GRANT;
sc_in<bool> STALL_SW;
//signals
//parse address from CPU
sc_signal<sc_uint<21>> address_tag;
sc_signal<sc_uint<7>> address_index;
sc_signal<sc_uint<4>> address_offset;
//parse address from MP
sc_signal<sc_uint<21>> mp_address_tag;
sc_signal<sc_uint<7>> mp_address_index;
sc_signal<sc_uint<4>> mp_address_offset;
//parse address from BUS
sc_signal<sc_uint<21>> bus_tag;
sc_signal<sc_uint<7>> bus_index;
sc_signal<sc_uint<4>> bus_offset;
sc_signal<sc_uint<4>> mp_last_addr_offset;
sc_signal<bool> way0_hit;
sc_signal<bool> way1_hit;
sc_signal<bool> miss;
sc_signal<sc_uint<32>> selected_data;
sc_signal<bool> current_LRU; // false: 0, true: 1
// WAYS 128 lines
sc_signal<bool> LRU_bit_check[128]; // bit to compare least recently used
// WAY 0
sc_signal<sc_uint<32>> w0_word[128][4];
sc_signal<sc_uint<21>> w0_TAG[128];
sc_signal<bool> w0_LINE_VALIDATE[128];
//WAY 1
sc_signal<sc_uint<32>> w1_word[128][4];
sc_signal<sc_uint<21>> w1_TAG[128];
sc_signal<bool> w1_LINE_VALIDATE[128];
//buffer
sc_signal<bool> write_buff;
sc_signal<bool> full, empty;
sc_signal<sc_uint<32>> adr_sc;
int burst_cpt;
sc_signal<sc_uint<32>> data_mask_sc;
//FMS signal debug
sc_signal<sc_uint<2>> current_state;
sc_signal<sc_uint<2>> future_state;
void adresse_parcer();
void miss_detection();
void new_state();
void state_transition();
void mae_output();
void buffer_manager();
void trace(sc_trace_file*);
buffercache buffcache_inst;
SC_CTOR(dcache) :
buffcache_inst("buffercache")
{
SC_METHOD(adresse_parcer);
sensitive << DATA_ADR_SM << ADR_SW;
SC_METHOD(miss_detection);
sensitive << address_tag
<< address_index
<< address_offset
<< LOAD_SM
<< STORE_SM
<< way0_hit
<< way1_hit
<< CLK.neg();
SC_METHOD(new_state);
sensitive << CLK.neg() << RESET_N;
SC_METHOD(state_transition);
sensitive << CLK.neg() << RESET_N;
SC_METHOD(mae_output);
sensitive << CLK.neg() << RESET_N;
reset_signal_is(RESET_N, false);
buffcache_inst.RESET_N(RESET_N);
buffcache_inst.CLK(CLK);
buffcache_inst.WRITE_OBUFF(write_buff);
buffcache_inst.ACK(ACK_SW);
buffcache_inst.DATA_C(DATA_SM);
buffcache_inst.ADR_C(DATA_ADR_SM);
buffcache_inst.STORE_C(STORE_SM);
buffcache_inst.LOAD_C(LOAD_SM);
buffcache_inst.SIZE_C(MEM_SIZE_SM);
buffcache_inst.ADR_I(ADR_SW);
buffcache_inst.FULL(full);
buffcache_inst.EMPTY(empty);
buffcache_inst.DATA_MP(DT_SDC);
buffcache_inst.ADR_MP(A_SDC);
buffcache_inst.STORE_MP(WRITE_SDC);
buffcache_inst.LOAD_MP(READ_SDC);
buffcache_inst.SIZE_MP(SIZE_SDC);
}
};
#endif |
/*******************************************************************************
* pcnttest.h -- Copyright 2019 (c) Glenn Ramalho - RFIDo Design
*******************************************************************************
* Description:
* This is the main testbench header for the pcnt.ino test. It describes how
* the model should be wired up and connected to any monitors.
*******************************************************************************
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
#include <systemc.h>
#include <Arduino.h>
#include "doitesp32devkitv1.h"
#include "uartclient.h"
SC_MODULE(pcnttest) {
/* Signals */
sc_signal<bool> led {"led"};
gn_signal_mix d2_a12 {"d2_a12"};
gn_signal_mix rx {"rx"};
gn_signal_mix tx {"tx"};
sc_signal<unsigned int> fromwifi {"fromwifi"};
sc_signal<unsigned int> towifi {"towifi"};
gn_signal_mix pwm0 {"pwm0"};
gn_signal_mix pwm1 {"pwm1"};
gn_signal_mix pwm2 {"pwm2"};
gn_signal_mix pwm3 {"pwm3"};
gn_signal_mix ctrl0 {"ctrl0"};
gn_signal_mix ctrl1 {"ctrl1"};
gn_signal_mix ctrl2 {"ctrl2"};
/* Note: these will soon be replaced with better interfaces. */
sc_signal<unsigned int> fromflash {"fromflash"};
sc_signal<unsigned int> toflash {"toflash"};
sc_signal<bool> fromi2c {"fromi2c"};
sc_signal<bool> toi2c {"toi2c"};
/* Unconnected signals */
gn_signal_mix logic_0 {"logic_0", GN_LOGIC_0};
/* blocks */
doitesp32devkitv1 i_esp{"i_esp"};
uartclient i_uartclient{"i_uartclient"};
netcon_mixtobool i_netcon{"i_netcon"};
/* Processes */
void testbench(void);
void serflush(void);
void drivewave(void);
/* Tests */
unsigned int tn; /* Testcase number */
void t0();
// Constructor
SC_CTOR(pcnttest) {
/* UART 0 - we connect the wires to the corresponding tasks. Yes, the
* RX and TX need to be switched.
*/
i_esp.d3(rx); i_uartclient.tx(rx);
i_esp.d1(tx); i_uartclient.rx(tx);
/* LED */
i_esp.d2_a12(d2_a12);
i_netcon.a(d2_a12);
i_netcon.b(led);
/* We connect the waveform to these. */
i_esp.d12_a15(pwm0);
i_esp.d13_a14(ctrl0);
i_esp.d21(pwm1);
i_esp.d22(ctrl1);
i_esp.d26_a19(pwm2);
i_esp.d27_a17(pwm3);
i_esp.d32_a4(ctrl2);
/* Other interfaces, none are used so they are just left floating. */
i_esp.wrx(fromwifi); i_esp.wtx(towifi);
/* Note: these two will soon be replaced with the real flash and I2C
* interfaces, as soon as someone takes the time to implement them. */
i_esp.frx(fromflash); i_esp.ftx(toflash);
i_esp.irx(fromi2c); i_esp.itx(toi2c);
/* Pins not used in this simulation */
i_esp.d0_a11(logic_0); /* BOOT pin */
i_esp.d4_a10(logic_0); i_esp.d5(logic_0);
i_esp.d14_a16(logic_0);
i_esp.d15_a13(logic_0); i_esp.d16(logic_0);
i_esp.d17(logic_0); i_esp.d18(logic_0); i_esp.d19(logic_0);
i_esp.d23(logic_0);
i_esp.d25_a18(logic_0);
i_esp.d33_a5(logic_0); i_esp.d34_a6(logic_0);
i_esp.d35_a7(logic_0); i_esp.d36_a0(logic_0); i_esp.d37_a1(logic_0);
i_esp.d38_a2(logic_0); i_esp.d39_a3(logic_0);
SC_THREAD(testbench);
SC_THREAD(serflush);
SC_THREAD(drivewave);
}
void trace(sc_trace_file *tf);
};
|
#ifndef ACCNAME_H
#define ACCNAME_H
#include <systemc.h>
#ifndef __SYNTHESIS__
#define DWAIT(x) wait(x)
#else
#define DWAIT(x)
#endif
#define ACCNAME SA_UINT8_V2_0
#define ACC_DTYPE sc_uint
#define ACC_C_DTYPE unsigned int
#define STOPPER 4294967295
#define IN_BUF_LEN 4096
#define WE_BUF_LEN 8192
#define SUMS_BUF_LEN 1024
#define MAX 2147483647
#define MIN -2147483648
#define POS 1073741824
#define NEG -1073741823
#define DIVMAX 2147483648
#define MAX8 255
typedef struct _DATA{
sc_uint<32> data;
bool tlast;
inline friend ostream& operator << (ostream& os, const _DATA &v){
cout << "data: " << v.data << " tlast: " << v.tlast;
return os;
}
} DATA;
SC_MODULE(ACCNAME) {
sc_uint<14> depth;
sc_in<bool> clock;
sc_in <bool> reset;
sc_fifo_in<DATA> din1;
sc_fifo_in<DATA> din2;
sc_fifo_in<DATA> din3;
sc_fifo_in<DATA> din4;
sc_fifo_out<DATA> dout1;
sc_fifo_out<DATA> dout2;
sc_fifo_out<DATA> dout3;
sc_fifo_out<DATA> dout4;
sc_signal<bool> read_inputs;
sc_signal<bool> rtake;
sc_signal<bool> ltake;
sc_signal<int> llen;
sc_signal<int> rlen;
sc_signal<int> lhs_block_max;
sc_signal<int> rhs_block_max;
#ifndef __SYNTHESIS__
sc_signal<bool,SC_MANY_WRITERS> d_in1;
sc_signal<bool,SC_MANY_WRITERS> schedule;
sc_signal<bool,SC_MANY_WRITERS> out_check;
sc_signal<bool,SC_MANY_WRITERS> gemm_unit_1_ready;
sc_signal<bool,SC_MANY_WRITERS> write1;
sc_signal<bool,SC_MANY_WRITERS> arrange1;
#else
sc_signal<bool> d_in1;
sc_signal<bool> schedule;
sc_signal<bool> out_check;
sc_signal<bool> gemm_unit_1_ready;
sc_signal<bool> write1;
sc_signal<bool> arrange1;
#endif
sc_signal<int> gemm_unit_1_l_pointer;
sc_signal<bool> gemm_unit_1_iwuse;
sc_uint<32> g1 [256];
sc_uint<8> r1 [256];
//GEMM 1 Inputs
sc_uint<32> lhsdata1a[IN_BUF_LEN];
sc_uint<32> lhsdata2a[IN_BUF_LEN];
sc_uint<32> lhsdata3a[IN_BUF_LEN];
sc_uint<32> lhsdata4a[IN_BUF_LEN];
//Global Weights
sc_uint<32> rhsdata1[WE_BUF_LEN];
sc_uint<32> rhsdata2[WE_BUF_LEN];
sc_uint<32> rhsdata3[WE_BUF_LEN];
sc_uint<32> rhsdata4[WE_BUF_LEN];
//new sums bram
sc_int<32> lhs_sum1[SUMS_BUF_LEN];
sc_int<32> lhs_sum2[SUMS_BUF_LEN];
sc_int<32> lhs_sum3[SUMS_BUF_LEN];
sc_int<32> lhs_sum4[SUMS_BUF_LEN];
sc_int<32> rhs_sum1[SUMS_BUF_LEN];
sc_int<32> rhs_sum2[SUMS_BUF_LEN];
sc_int<32> rhs_sum3[SUMS_BUF_LEN];
sc_int<32> rhs_sum4[SUMS_BUF_LEN];
sc_fifo<int> WRQ1;
sc_fifo<int> WRQ2;
sc_fifo<char> sIs1;
sc_fifo<char> sIs2;
sc_fifo<char> sIs3;
sc_fifo<char> sIs4;
sc_fifo<char> sIs5;
sc_fifo<char> sIs6;
sc_fifo<char> sIs7;
sc_fifo<char> sIs8;
sc_fifo<char> sIs9;
sc_fifo<char> sIs10;
sc_fifo<char> sIs11;
sc_fifo<char> sIs12;
sc_fifo<char> sIs13;
sc_fifo<char> sIs14;
sc_fifo<char> sIs15;
sc_fifo<char> sIs16;
sc_fifo<char> sWs1;
sc_fifo<char> sWs2;
sc_fifo<char> sWs3;
sc_fifo<char> sWs4;
sc_fifo<char> sWs5;
sc_fifo<char> sWs6;
sc_fifo<char> sWs7;
sc_fifo<char> sWs8;
sc_fifo<char> sWs9;
sc_fifo<char> sWs10;
sc_fifo<char> sWs11;
sc_fifo<char> sWs12;
sc_fifo<char> sWs13;
sc_fifo<char> sWs14;
sc_fifo<char> sWs15;
sc_fifo<char> sWs16;
sc_int<64> rf;
int ra=0;
sc_int<32> l_offset = 0;
int mask = 0;
int r = 0;
int sm = 0;
sc_signal<int> w1S;
sc_signal<int> w2S;
sc_signal<int> w3S;
sc_signal<int> w4S;
#ifndef __SYNTHESIS__
int weight_max_index=0;
int input_max_index=0;
int g1_macs=0;
int g1_out_count=0;
#endif
sc_out<int> inS;
sc_out<int> read_cycle_count;
sc_out<int> process_cycle_count;
sc_out<int> gemm_1_idle;
sc_out<int> gemm_1_write;
sc_out<int> gemm_1;
sc_out<int> wstall_1;
sc_out<int> rmax;
sc_out<int> lmax;
sc_out<int> outS;
sc_out<int> w1SS;
sc_out<int> w2SS;
sc_out<int> w3SS;
sc_out<int> w4SS;
sc_out<int> schS;
sc_out<int> p1S;
void Input_Handler();
void Output_Handler();
void Worker1();
void Data_In();
void Tracker();
void Scheduler();
void Post1();
void schedule_gemm_unit(int, int, int, int, int,int,int);
int SHR(int,int);
void Read_Cycle_Counter();
void Process_Cycle_Counter();
void Writer_Cycle_Counter();
sc_uint<32> mul_u8(sc_uint<8>,sc_uint<8>);
SC_HAS_PROCESS(ACCNAME);
ACCNAME(sc_module_name name_) :sc_module(name_),WRQ1(512),sIs1(2048),sIs2(2048),sIs3(2048),sIs4(2048),sIs5(2048),sIs6(2048),sIs7(2048),sIs8(2048),
sIs9(2048),sIs10(2048),sIs11(2048),sIs12(2048),sIs13(2048),sIs14(2048),sIs15(2048),sIs16(2048),
WRQ2(512),sWs1(2048),sWs2(2048),sWs3(2048),sWs4(2048),sWs5(2048),sWs6(2048),sWs7(2048),sWs8(2048),
sWs9(2048),sWs10(2048),sWs11(2048),sWs12(2048),sWs13(2048),sWs14(2048),sWs15(2048),sWs16(2048){
SC_CTHREAD(Input_Handler,clock.pos());
reset_signal_is(reset,true);
SC_CTHREAD(Output_Handler,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Worker1,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Data_In,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Scheduler,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Post1,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Read_Cycle_Counter,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Process_Cycle_Counter,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Writer_Cycle_Counter,clock);
reset_signal_is(reset,true);
#pragma HLS RESOURCE variable=din1 core=AXI4Stream metadata="-bus_bundle S_AXIS_DATA1" port_map={{din1_0 TDATA} {din1_1 TLAST}}
#pragma HLS RESOURCE variable=din2 core=AXI4Stream metadata="-bus_bundle S_AXIS_DATA2" port_map={{din2_0 TDATA} {din2_1 TLAST}}
#pragma HLS RESOURCE variable=din3 core=AXI4Stream metadata="-bus_bundle S_AXIS_DATA3" port_map={{din3_0 TDATA} {din3_1 TLAST}}
#pragma HLS RESOURCE variable=din4 core=AXI4Stream metadata="-bus_bundle S_AXIS_DATA4" port_map={{din4_0 TDATA} {din4_1 TLAST}}
#pragma HLS RESOURCE variable=dout1 core=AXI4Stream metadata="-bus_bundle M_AXIS_DATA1" port_map={{dout1_0 TDATA} {dout1_1 TLAST}}
#pragma HLS RESOURCE variable=dout2 core=AXI4Stream metadata="-bus_bundle M_AXIS_DATA2" port_map={{dout2_0 TDATA} {dout2_1 TLAST}}
#pragma HLS RESOURCE variable=dout3 core=AXI4Stream metadata="-bus_bundle M_AXIS_DATA3" port_map={{dout3_0 TDATA} {dout3_1 TLAST}}
#pragma HLS RESOURCE variable=dout4 core=AXI4Stream metadata="-bus_bundle M_AXIS_DATA4" port_map={{dout4_0 TDATA} {dout4_1 TLAST}}
#pragma HLS array_partition variable=g1 complete dim=0
#pragma HLS RESET variable=reset
#pragma HLS resource core=AXI4LiteS metadata="-bus_bundle slv0" variable=inS
#pragma HLS resource core=AXI4LiteS metadata="-bus_bundle slv0" variable=rmax
#pragma HLS resource core=AXI4LiteS metadata="-bus_bundle slv0" variable=lmax
#pragma HLS resource core=AXI4LiteS metadata="-bus_bundle slv0" variable=outS
#pragma HLS resource core=AXI4LiteS metadata="-bus_bundle slv0" variable=schS
#pragma HLS resource core=AXI4LiteS metadata="-bus_bundle slv0" variable=inS
#pragma HLS resource core=AXI4LiteS metadata="-bus_bundle slv0" variable=p1S
}
};
#endif /* ACCNAME_H */
|
#ifndef HAMMINGREG_
#define HAMMINGREG_
#include <systemc.h>
#include "HCGenerator.h"
#include "SynGenerator.h"
#include "Corrector.h"
//code and decode words using hamming code
SC_MODULE(HamReg)
{
HCGen *hgen; //this circuit generate a code word
SynGen *sgen; //this circuit calculate the syndrome
Corrector *corr; //this circuit correct and decode a word
//Ports
sc_in < bool > clk;
sc_in < sc_uint<15> > coded_din;
sc_out < sc_uint<15> > coded_dout;
sc_in < sc_uint<11> > din;
sc_out < sc_uint<11> > dout;
//signals to connect between the modules
sc_signal < sc_uint <4> > syndSig;
sc_signal< sc_uint <11> > din_sig;
sc_signal< sc_uint <15> > codeddout_sig;
// handshake signals
sc_in < bool > din_vld;
sc_out < bool > din_rdy;
sc_out < bool > codedout_vld;
sc_in < bool > codedout_rdy;
sc_in < bool > codedin_vld;
sc_out < bool > codedin_rdy;
sc_out < bool > dout_vld;
sc_in < bool > dout_rdy;
void ham_main_din(); //coding process
void ham_main_codedin(); //decoding process
SC_CTOR(HamReg){
hgen=new HCGen("hgen");
hgen->din( din );
hgen->dout( coded_dout );
hgen->clk(clk);
hgen->din_rdy(din_rdy);
hgen->din_vld(din_vld);
hgen->codedout_rdy(codedout_rdy);
hgen->codedout_vld(codedout_vld);
sgen=new SynGen("sgen");
sgen->din( coded_din );
sgen->dout( syndSig );
sgen->clk(clk);
corr=new Corrector("corr");
corr->datain( coded_din );
corr->syndin( syndSig );
corr->dout( dout );
corr->clk(clk);
corr->codedin_rdy(codedin_rdy);
corr->codedin_vld(codedin_vld);
corr->dout_rdy(dout_rdy);
corr->dout_vld(dout_vld);
SC_CTHREAD(ham_main_din,clk.pos());
SC_CTHREAD(ham_main_codedin,clk.pos());
sensitive << din;
sensitive << din_vld;
sensitive << clk.pos();
}
~HamReg(){
delete hgen;
delete sgen;
delete corr;
}
};
#endif
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2017 Cadence Design Systems, Inc. All rights reserved worldwide.
//
// The code contained herein is the proprietary and confidential information
// of Cadence or its licensors, and is supplied subject to a previously
// executed license and maintenance agreement between Cadence and customer.
// This code is intended for use with Cadence high-level synthesis tools and
// may not be used with other high-level synthesis tools. Permission is only
// granted to distribute the code as indicated. Cadence grants permission for
// customer to distribute a copy of this code to any partner to aid in designing
// or verifying the customer's intellectual property, as long as such
// distribution includes a restriction of no additional distributions from the
// partner, unless the partner receives permission directly from Cadence.
//
// ALL CODE FURNISHED BY CADENCE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY
// KIND, AND CADENCE SPECIFICALLY DISCLAIMS ANY WARRANTY OF NONINFRINGEMENT,
// FITNESS FOR A PARTICULAR PURPOSE OR MERCHANTABILITY. CADENCE SHALL NOT BE
// LIABLE FOR ANY COSTS OF PROCUREMENT OF SUBSTITUTES, LOSS OF PROFITS,
// INTERRUPTION OF BUSINESS, OR FOR ANY OTHER SPECIAL, CONSEQUENTIAL OR
// INCIDENTAL DAMAGES, HOWEVER CAUSED, WHETHER FOR BREACH OF WARRANTY,
// CONTRACT, TORT, NEGLIGENCE, STRICT LIABILITY OR OTHERWISE.
//
////////////////////////////////////////////////////////////////////////////////
#ifndef TB_H
#define TB_H
/* This file defines the module "tb", which is a testbench used to
exercise the DUT. The same testbench module is used with both
behavioral (user-defined) and RTL (Stratus-generated) versions
of the DUT. It is instantiated in the top-level module System (see
system.h). */
#include <systemc.h> /* SystemC definitions. */
#include <esc.h> /* Cadence ESC functions and utilities. */
#include <stratus_hls.h> /* Cadence Stratus definitions. */
#include <cynw_p2p.h> /* The cynw_p2p communication channel. */
#include "stream_16X8.h" /* Generated stream interface classes */
#include "defines.h" /* definitions common to the TB and DUT. */
SC_MODULE( tb )
{
sc_in_clk clk;
sc_out< bool > rst;
cynw_p2p< input_data, ioConfig >::base_out out; /* from tb to dut. */
cynw_p2p< output_data, ioConfig >::base_in in; /* from dut to tb. */
stream_16X8::in <ioConfig> streamin;
stream_16X8::out <ioConfig> streamout;
FILE * ofile;
SC_CTOR( tb )
: clk( "clk" )
, rst( "rst" )
, in( "in" )
, out( "out" )
, streamin( "streamin" )
, streamout( "streamout" )
{
SC_CTHREAD( source, clk.pos() );
SC_CTHREAD( sink, clk.pos() );
streamout.clk_rst( clk, rst );
streamin.clk_rst( clk, rst );
/* Open a file to save DUT output. The environment variable
"BDW_SIM_CONFIG_DIR" is set by Stratus to a unique
directory for each simulation configuration. */
char filename[PATH_MAX];
char * dir = getenv( "BDW_SIM_CONFIG_DIR" );
if( !dir )
{
dir = ".";
}
sprintf( filename, "%s/response.dat", dir );
ofile = fopen( filename, "w" );
if( !ofile )
{
fprintf( stderr, "Could not open file '%s' for writing.\n", filename );
}
}
/* The module destructor closes the output file. */
~tb()
{
fclose( ofile );
}
sc_uint<8> x[8];
sc_uint<8> y[4];
sc_uint<8> data[16];
/* Declaration of source and sink thread functions. */
void source();
void sink();
/* Local data members of type sc_time, used to keep track of
simulation timings (e.g. latency of the DUT). */
sc_time start_time, end_time, clock_period;
};
#endif /* TB_H */
|
/**********************************************************************
Filename: sc_fir_pe.h
Purpose : PE of Systolic FIR filter
Author : [email protected]
History : Mar. 2024, First release
***********************************************************************/
#ifndef _SC_FIR_PE_H_
#define _SC_FIR_PE_H_
#include <systemc.h>
SC_MODULE(sc_fir_pe)
{
sc_in<bool> clk;
sc_in<sc_uint<8> > Cin;
sc_in<sc_uint<8> > Xin;
sc_out<sc_uint<8> > Xout;
sc_in<sc_uint<16> > Yin;
sc_out<sc_uint<16> > Yout;
sc_signal<sc_uint<16> > mul;
sc_signal<sc_uint<16> > rYin;
void pe_thread(void)
{
while (true)
{
wait(clk.posedge_event());
Xout.write(Xin.read());
mul.write(Xin.read() * Cin.read()); // Multiplication
rYin.write(Yin.read()); // Delay 1-clock
Yout.write(rYin.read() + mul.read()); // Accumulation
}
}
SC_CTOR(sc_fir_pe):
clk("clk"),
Cin("Cin"),
Xin("Xin"),
Xout("Xout"),
Yin("Yin"),
Yout("Yout")
{
SC_THREAD(pe_thread);
sensitive << clk;
}
~sc_fir_pe(void)
{
}
};
#endif
|
#pragma once
#include <systemc.h>
#include "../../UTIL/debug_util.h"
#include "../../UTIL/fifo.h"
#define x02x1_size 322
SC_MODULE(x0_multiplier)
{
// input :
sc_in<sc_uint<32>> OP1_SE, OP2_SE;
sc_in<sc_uint<2>> EXE_CMD_RD;
sc_in<bool> X02X1_POP_SX1;
sc_in<bool> DEC2X0_EMPTY_SD;
// output :
sc_out<sc_bv<320>> RES_RX0;
sc_out<bool> SELECT_HIGHER_BITS_RX0;
sc_out<bool> SIGNED_RES_RX0;
sc_out<bool> X02X1_EMPTY_SX0;
// General interace :
sc_in_clk CLK;
sc_in<bool> RESET;
sc_signal<sc_bv<64>> product[32];
sc_signal<sc_bv<64>> product_s1[20]; // product of stage 1
sc_signal<sc_bv<64>> product_s2[14]; // product of stage 2
sc_signal<sc_bv<64>> product_s3[10]; // product of stage 3
sc_signal<sc_bv<64>> product_s4[6]; // product of stage 4
sc_signal<sc_bv<64>> product_s5[4]; // product of stage 5
sc_signal<bool> signed_op;
sc_signal<bool> select_higher_bits_sx0;
sc_signal<bool> signed_res_sx0;
// fifo x02x1
sc_signal<sc_bv<x02x1_size>> x02x1_din_sx0;
sc_signal<sc_bv<x02x1_size>> x02x1_dout_sx0;
sc_signal<bool> x02x1_push_sx0, x02x1_full_sx0;
fifo<x02x1_size> fifo_inst;
void operation();
// stage 1 (11 CSA remind product 33)
void CSA_1();
void CSA_2();
void CSA_3();
void CSA_4();
void CSA_5();
void CSA_6();
void CSA_7();
void CSA_8();
void CSA_9();
void CSA_10();
void CSA_11();
// stage 2 (7 CSA remind product 33 and product_s1 21)
void CSA_12();
void CSA_13();
void CSA_14();
void CSA_15();
void CSA_16();
void CSA_17();
void CSA_18();
//stage 3 (5 CSA remind product 33)
void CSA_19();
void CSA_20();
void CSA_21();
void CSA_22();
void CSA_23();
//stage 4 (3 CSA remind product_s3 9 product 33)
void CSA_24();
void CSA_25();
void CSA_26();
//stage 5 (2 CSA remind product_s3 9)
void CSA_27();
void CSA_28();
//res => 320bits => 5x64 => M4 M3 M2 M1 M0
void manage_fifo();
void fifo_concat();
void fifo_unconcat();
void trace(sc_trace_file* tf);
SC_CTOR(x0_multiplier) :
fifo_inst("x02x1")
{
fifo_inst.DIN_S(x02x1_din_sx0);
fifo_inst.DOUT_R(x02x1_dout_sx0);
fifo_inst.EMPTY_S(X02X1_EMPTY_SX0);
fifo_inst.FULL_S(x02x1_full_sx0);
fifo_inst.PUSH_S(x02x1_push_sx0);
fifo_inst.POP_S(X02X1_POP_SX1);
fifo_inst.CLK(CLK);
fifo_inst.RESET_N(RESET);
SC_METHOD(operation);
sensitive << OP1_SE << OP2_SE << EXE_CMD_RD;
//stage 1
SC_METHOD(CSA_1);
sensitive << product[0] << product[1] << product[2];
SC_METHOD(CSA_2);
sensitive << product[3] << product[4] << product[5];
SC_METHOD(CSA_3);
sensitive << product[6] << product[7] << product[8];
SC_METHOD(CSA_4);
sensitive << product[9] << product[10] << product[11];
SC_METHOD(CSA_5);
sensitive << product[12] << product[13] << product[14];
SC_METHOD(CSA_6);
sensitive << product[15] << product[16] << product[17];
SC_METHOD(CSA_7);
sensitive << product[18] << product[19] << product[20];
SC_METHOD(CSA_8);
sensitive << product[21] << product[22] << product[23];
SC_METHOD(CSA_9);
sensitive << product[24] << product[25] << product[26];
SC_METHOD(CSA_10);
sensitive << product[27] << product[28] << product[29];
// stage 2
SC_METHOD(CSA_11);
sensitive << product_s1[0] << product_s1[1] << product_s1[2];
SC_METHOD(CSA_12);
sensitive << product_s1[3] << product_s1[4] << product_s1[5];
SC_METHOD(CSA_13);
sensitive << product_s1[6] << product_s1[7] << product_s1[8];
SC_METHOD(CSA_14);
sensitive << product_s1[9] << product_s1[10] << product_s1[11];
SC_METHOD(CSA_15);
sensitive << product_s1[12] << product_s1[13] << product_s1[14];
SC_METHOD(CSA_16);
sensitive << product_s1[15] << product_s1[16] << product_s1[17];
SC_METHOD(CSA_17);
sensitive << product_s1[18] << product_s1[19] << product[30];
// stage 3
SC_METHOD(CSA_18);
sensitive << product_s2[0] << product_s2[1] << product_s2[2];
SC_METHOD(CSA_19);
sensitive << product_s2[3] << product_s2[4] << product_s2[5];
SC_METHOD(CSA_20);
sensitive << product_s2[6] << product_s2[7] << product_s2[8];
SC_METHOD(CSA_21);
sensitive << product_s2[9] << product_s2[10] << product_s2[11];
SC_METHOD(CSA_22);
sensitive << product_s2[12] << product_s2[13] << product[31];
//stage 4
SC_METHOD(CSA_23);
sensitive << product_s3[0] << product_s3[1] << product_s3[2];
SC_METHOD(CSA_24);
sensitive << product_s3[3] << product_s3[4] << product_s3[5];
SC_METHOD(CSA_25);
sensitive << product_s3[6] << product_s3[7] << product_s3[8];
//stage 5
SC_METHOD(CSA_26);
sensitive << product_s4[0] << product_s4[1] << product_s4[2];
SC_METHOD(CSA_27);
sensitive << product_s4[3] << product_s4[4] << product_s4[5];
//fifo
SC_METHOD(fifo_concat);
sensitive << product_s5[0] << product_s5[1] << product_s5[2]
<< product_s5[3] << select_higher_bits_sx0 << signed_res_sx0;
SC_METHOD(fifo_unconcat);
sensitive << x02x1_dout_sx0;
SC_METHOD(manage_fifo);
sensitive << x02x1_full_sx0 << DEC2X0_EMPTY_SD;
}
}; |
// TODO Generalise this code so it is easy for all new accelerators
#ifndef SYSTEMC_INTEGRATION
#define SYSTEMC_INTEGRATION
#include <systemc.h>
#include "../acc.sc.h"
// #include "tensorflow/lite/delegates/utils/secda_tflite/sysc_integrator/axi4s_engine.sc.h"
#include "tensorflow/lite/delegates/utils/secda_tflite/axi_support/axi_api_v2.h"
int sc_main(int argc, char* argv[]) { return 0; }
void sysC_init() {
sc_report_handler::set_actions("/IEEE_Std_1666/deprecated", SC_DO_NOTHING);
sc_report_handler::set_actions(SC_ID_LOGIC_X_TO_BOOL_, SC_LOG);
sc_report_handler::set_actions(SC_ID_VECTOR_CONTAINS_LOGIC_VALUE_, SC_LOG);
}
struct systemC_sigs {
sc_clock clk_fast;
sc_signal<bool> sig_reset;
sc_fifo<DATA> dout1;
sc_fifo<DATA> din1;
int id;
systemC_sigs(int _id)
: dout1("dout1_fifo", 563840), din1("din1_fifo", 554800) {
sc_clock clk_fast("ClkFast", 1, SC_NS);
id = _id;
}
};
void systemC_binder(ACCNAME* acc, stream_dma* sdma, systemC_sigs* scs) {
acc->clock(scs->clk_fast);
acc->reset(scs->sig_reset);
acc->dout1(scs->dout1);
acc->din1(scs->din1);
sdma->dmad->clock(scs->clk_fast);
sdma->dmad->reset(scs->sig_reset);
sdma->dmad->dout1(scs->dout1);
sdma->dmad->din1(scs->din1);
// static int* dma_input_address =
// (int*)malloc(65536 * sizeof(int));
// static int* dma_output_address =
// (int*)malloc(65536 * sizeof(int));
// // Initialize with zeros
// for (int64_t i = 0; i < 65536; i++) {
// *(dma_input_address + i) = 0;
// }
// for (int64_t i = 0; i < 65536; i++) {
// *(dma_output_address + i) = 0;
// }
// dmad->DMA_input_buffer = (int*)dma_input_address;
// dmad->DMA_output_buffer = (int*)dma_output_address;
}
#endif // SYSTEMC_INTEGRATION
|
/**
#define meta ...
prInt32f("%s\n", meta);
**/
/*
All rights reserved to Alireza Poshtkohi (c) 1999-2023.
Email: [email protected]
Website: http://www.poshtkohi.info
*/
#ifndef __s7_h__
#define __s7_h__
#include <systemc.h>
SC_MODULE(s7)
{
sc_in<sc_uint<6> > stage1_input;
sc_out<sc_uint<4> > stage1_output;
void s7_box();
SC_CTOR(s7)
{
SC_METHOD(s7_box);
sensitive << stage1_input;
}
};
#endif
|
#include <systemc.h>
#include <i2c_controller.h>
void i2c_controller::clk_divider()
{
if(rst)
{
i2c_clk.write(1);
}
else
{
if(counter2 == 1)
{
bool t = i2c_clk.read();
i2c_clk.write(!t);
counter2 = 0;
}
else {
counter2 = counter2 + 1;
}
}
}
void i2c_controller::scl_controller()
{
if(rst)
{
i2c_scl_enable = 0;
}
else
{
if((state == IDLE) | (state == START) | (state == STOP))
{
i2c_scl_enable = 0;
}
else
{
i2c_scl_enable = 1;
}
}
}
void i2c_controller::logic_fsm()
{
if(rst)
{
state = IDLE;
}
else
{
switch(state)
{
case IDLE:
if(enable == 1)
{
state = START;
saved_addr = (addr,rw);
saved_data = data_in;
}
else
{
state = IDLE;
}
break;
case START:
counter = 7;
state = ADDRESS;
break;
case ADDRESS:
if(counter == 0)
{
state = READ_ACK;
}
else
{
counter = counter - 1;
}
break;
case READ_ACK:
if(i2c_sda ==(sc_logic) 0)
{
counter = 7;
if(saved_addr[0] == 0)
{
state = WRITE_DATA;
}
else
{
state = READ_DATA;
}
}
else
{
state = STOP;
}
break;
case WRITE_DATA:
if(counter == 0)
{
state = READ_ACK2;
}
else
{
counter = counter - 1;
}
break;
case READ_ACK2:
if((i2c_sda == 0) & (enable == 1))
{
state = IDLE;
}
else
{
state = STOP;
}
break;
case READ_DATA:
data_from_slave[counter] = i2c_sda;
if(counter == 0)
{
state = WRITE_ACK;
}
else
{
counter = counter - 1;
}
break;
case WRITE_ACK:
state = STOP;
break;
case STOP:
state = IDLE;
break;
}
}
}
void i2c_controller::data_fsm()
{
if(rst)
{
write_enable.write(1);
i2c_sda.write((sc_logic)1);
}
else
{
switch(state)
{
case IDLE:
break;
case READ_ACK2:
break;
case START:
write_enable.write(1);
i2c_sda.write((sc_logic)0);
break;
case ADDRESS:
{
int t = saved_addr[counter];
i2c_sda.write((sc_logic) t);
}
break;
case READ_ACK:
i2c_sda.write(sc_logic('Z'));
write_enable.write(0);
break;
case WRITE_DATA:
{
write_enable.write(1);
sc_logic t = saved_data[counter];
i2c_sda.write((sc_logic) t);
}
break;
case WRITE_ACK:
i2c_sda.write((sc_logic) 0);
write_enable.write(1);
break;
case READ_DATA:
write_enable.write(0);
break;
case STOP:
write_enable.write(1);
i2c_sda.write((sc_logic)1);
break;
}
}
}
void i2c_controller::ready_assign()
{
if((rst == 0) && (state == IDLE))
{
ready.write(1);
}
else
{
ready.write(0);
}
}
void i2c_controller::i2c_scl_assign()
{
if(i2c_scl_enable == 0)
{
i2c_scl.write((sc_logic)1);
}
else
{
i2c_scl.write((sc_logic)i2c_clk);
}
}
|
#ifndef BUFFER_CACHE
#define BUFFER_CACHE
#include <systemc.h>
#include "../../../UTIL/debug_util.h"
SC_MODULE(buffercache)
{
sc_in<bool> RESET_N;
sc_in_clk CLK;
//INPUT from DCACHE
sc_in<bool> WRITE_OBUFF;
sc_in<bool> ACK;
sc_in<sc_uint<32>> DATA_C;
sc_in<sc_uint<32>> ADR_C;
sc_in<bool> STORE_C;
sc_in<bool> LOAD_C;
sc_in<sc_uint<2>> SIZE_C;
//Snoopy
sc_in<sc_uint<32>> ADR_I;
//OUTPUT
//TO DCACHE
sc_out<bool> FULL;
sc_out<bool> EMPTY;
//TO RAM
sc_out<sc_uint<32>> DATA_MP; // MP mem primaire
sc_out<sc_uint<32>> ADR_MP;
sc_out<bool> STORE_MP;
sc_out<bool> LOAD_MP;
sc_out<sc_uint<2>> SIZE_MP;
//signals
// buffers
sc_signal<bool> buffer_choice;
//buff0
sc_signal<sc_uint<32>> buff0_DATA;
sc_signal<sc_uint<32>> buff0_DATA_ADR;
sc_signal<bool> buff0_STORE;
sc_signal<bool> buff0_LOAD;
sc_signal<sc_uint<2>> buff0_SIZE;
sc_signal<bool> buff0_VALIDATE; // data valid on buffer
//buff1
sc_signal<sc_uint<32>> buff1_DATA;
sc_signal<sc_uint<32>> buff1_DATA_ADR;
sc_signal<bool> buff1_STORE;
sc_signal<bool> buff1_LOAD;
sc_signal<sc_uint<2>> buff1_SIZE;
sc_signal<bool> buff1_VALIDATE; // data valid on buffer
sc_signal<bool> busreq_we;
sc_signal<bool> wait_for_ack_falling_edge;
void fifo();
void write_output();
void bufferfull();
void read_buffer_choice();
void choice_buff();
void trace(sc_trace_file*);
SC_CTOR(buffercache)
{
SC_METHOD(fifo);
sensitive << CLK.neg() << ACK;
SC_METHOD(write_output);
sensitive << buffer_choice << buff0_VALIDATE << buff1_VALIDATE
<< buff0_LOAD << buff0_STORE << buff1_LOAD << buff1_STORE
<< ADR_I;
SC_METHOD(bufferfull);
sensitive << buff0_VALIDATE << buff1_VALIDATE;
SC_METHOD(choice_buff);
sensitive << RESET_N << ACK;
reset_signal_is(RESET_N, false);
}
};
#endif |
/**
* @file sc_config.h
* @brief This file contains the SystemC configuration
* @ingroup systemc_modules
*/
#ifndef SC_CONFIG_H
#define SC_CONFIG_H
#include <systemc.h>
typedef struct sc_thread_config_s
{
bool rst_act_level;
int rst_act_microsteps;
bool ena_act_level;
bool clk_act_edge;
sc_time clk_period;
sc_time microstep;
int clk_semiperiod_microsteps;
}sc_thread_config_t;
void sc_setConfig(sc_thread_config_t *theConfig);
bool sc_getRstActLevel(void);
int sc_getRstActMicrosteps(void);
bool sc_getEnaActLevel(void);
bool sc_getClkActEdge(void);
sc_time sc_getClkPeriod(void);
sc_time sc_getMicrostep(void);
int sc_getClkSemiperiodMicrosteps(void);
#endif // SC_CONFIG_H
|
/**
#define meta ...
prInt32f("%s\n", meta);
**/
/*
All rights reserved to Alireza Poshtkohi (c) 1999-2023.
Email: [email protected]
Website: http://www.poshtkohi.info
*/
#ifndef __desround_h__
#define __desround_h__
#include <systemc.h>
#include "key_gen.h"
SC_MODULE(desround)
{
sc_in<bool > clk;
sc_in<bool > reset;
sc_in<sc_uint<4> > iteration_i;
sc_in<bool > decrypt_i;
sc_in<sc_uint<32> > R_i;
sc_in<sc_uint<32> > L_i;
sc_in<sc_uint<56> > Key_i;
sc_out<sc_uint<32> > R_o;
sc_out<sc_uint<32> > L_o;
sc_out<sc_uint<56> > Key_o;
sc_out<sc_uint<6> > s1_o, s2_o, s3_o, s4_o, s5_o, s6_o, s7_o, s8_o;
sc_in<sc_uint<4> > s1_i, s2_i, s3_i, s4_i, s5_i, s6_i, s7_i, s8_i;
void registers();
void round_proc();
sc_signal<sc_uint<56> > previous_key;
sc_signal<sc_uint<4> > iteration;
sc_signal<bool > decrypt; //When decrypting we rotate rigth instead of left
sc_signal<sc_uint<56> > non_perm_key;
sc_signal<sc_uint<48> > new_key;
sc_signal<sc_uint<32> > next_R;
///sc_signal<sc_uint<32> > expanRSig;
//Round key generator
key_gen *kg1;
SC_CTOR(desround)
{
kg1 = new key_gen("key_gen");
kg1->previous_key(previous_key);
kg1->iteration(iteration);
kg1->decrypt(decrypt);
kg1->new_key(new_key);
kg1->non_perm_key(non_perm_key);
SC_METHOD(registers);
sensitive << clk.pos();
sensitive << reset.neg();
SC_METHOD(round_proc);
sensitive << R_i << L_i << Key_i << iteration_i << decrypt_i;
sensitive << new_key << s1_i << s2_i << s3_i << s4_i << s5_i;
sensitive << s6_i << s7_i << s8_i;
}
};
#endif
|
#ifndef __CONTADOR_ARGS_H__
#define __CONTADOR_ARGS_H__
#include <systemc.h>
#endif // __CONTADOR_ARGS_H__
|
#ifndef SC_ENV_H
#define SC_ENV_H
#include <stdint.h>
#include <systemc.h>
#endif
|
/*******************************************************************************
* cchan.h -- Copyright 2019 Glenn Ramalho - RFIDo Design
*******************************************************************************
* Description:
* Implements a SystemC module for a character wide UART like protocol.
* This is intended mainly as a way to simplify more complex communication
* protocols and does not represent any existing protocol.
*******************************************************************************
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
#ifndef _CCHAN_H
#define _CCHAN_H
#include <systemc.h>
SC_MODULE(cchan) {
sc_in<unsigned int> rx;
sc_out<unsigned int> tx;
sc_fifo<unsigned char> from;
sc_fifo<unsigned char> to;
void intake();
void outtake();
sc_time baudperiod;
void set_baud(unsigned int baudrate);
cchan(sc_module_name name, int tx_buffer_size, int rx_buffer_size):
rx("rx"), tx("tx"),
from("fromfifo", rx_buffer_size), to("tofifo", tx_buffer_size) {
SC_THREAD(intake);
sensitive << rx;
SC_THREAD(outtake); /* Active when something is in the fifo. */
set_baud(2000000); /* The default is 2MHz. */
}
SC_HAS_PROCESS(cchan);
};
#endif
|
// ================================================================
// NVDLA Open Source Project
//
// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
// NVDLA Open Hardware License; Check "LICENSE" which comes with
// this distribution for more information.
// ================================================================
// File Name: nvdla_mac2accu_data_monitor.h
#if !defined(_nvdla_mac2accu_data_monitor_H_)
#define _nvdla_mac2accu_data_monitor_H_
#include <systemc.h>
#include <stdint.h>
#ifndef _nvdla_stripe_info_struct_H_
#include "nvdla_stripe_info_struct.h"
#endif
// union nvdla_mac2accu_data_if_u {
// nvdla_stripe_info_t nvdla_stripe_info;
// };
typedef struct nvdla_mac2accu_data_monitor_s {
uint8_t mask ;
uint8_t mode;
int32_t data [8*8];
// union nvdla_mac2accu_data_if_u pd ;
nvdla_stripe_info_t nvdla_stripe_info;
} nvdla_mac2accu_data_monitor_t;
#endif // !defined(_nvdla_mac2accu_data_monitor_H_)
|
// ================================================================
// NVDLA Open Source Project
//
// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
// NVDLA Open Hardware License; Check "LICENSE" which comes with
// this distribution for more information.
// ================================================================
// File Name: nvdla_mac2accu_data_monitor.h
#if !defined(_nvdla_mac2accu_data_monitor_H_)
#define _nvdla_mac2accu_data_monitor_H_
#include <systemc.h>
#include <stdint.h>
#ifndef _nvdla_stripe_info_struct_H_
#include "nvdla_stripe_info_struct.h"
#endif
// union nvdla_mac2accu_data_if_u {
// nvdla_stripe_info_t nvdla_stripe_info;
// };
typedef struct nvdla_mac2accu_data_monitor_s {
uint8_t mask ;
uint8_t mode;
int32_t data [8*8];
// union nvdla_mac2accu_data_if_u pd ;
nvdla_stripe_info_t nvdla_stripe_info;
} nvdla_mac2accu_data_monitor_t;
#endif // !defined(_nvdla_mac2accu_data_monitor_H_)
|
/*****************************************************************************
NoximNoC.h -- Network-on-Chip (NoC) definition
*****************************************************************************/
#ifndef __NoximNoC_H__
#define __NoximNoC_H__
//---------------------------------------------------------------------------
#include <systemc.h>
#include "NoximTile.h"
#include "NoximGlobalTrafficTable.h"
#include "NoximGlobalRoutingTable.h"
SC_MODULE(NoximNoC)
{
// I/O Ports
sc_in_clk clock; // The input clock for the NoC
sc_in<bool> reset; // The reset signal for the NoC
// Signals
sc_signal <bool> req_to_east [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][DEFAULT_NUMBER_VIRTUAL_CHANNEL];
sc_signal <bool> req_to_west [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][DEFAULT_NUMBER_VIRTUAL_CHANNEL];
sc_signal <bool> req_to_south [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][DEFAULT_NUMBER_VIRTUAL_CHANNEL];
sc_signal <bool> req_to_north [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][DEFAULT_NUMBER_VIRTUAL_CHANNEL];
sc_signal <bool> req_to_up [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][DEFAULT_NUMBER_VIRTUAL_CHANNEL];
sc_signal <bool> req_to_down [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][DEFAULT_NUMBER_VIRTUAL_CHANNEL];
sc_signal <bool> ack_to_east [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][DEFAULT_NUMBER_VIRTUAL_CHANNEL];
sc_signal <bool> ack_to_west [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][DEFAULT_NUMBER_VIRTUAL_CHANNEL];
sc_signal <bool> ack_to_south [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][DEFAULT_NUMBER_VIRTUAL_CHANNEL];
sc_signal <bool> ack_to_north [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][DEFAULT_NUMBER_VIRTUAL_CHANNEL];
sc_signal <bool> ack_to_up [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][DEFAULT_NUMBER_VIRTUAL_CHANNEL];
sc_signal <bool> ack_to_down [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][DEFAULT_NUMBER_VIRTUAL_CHANNEL];
sc_signal <NoximFlit> flit_to_east [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1];
sc_signal <NoximFlit> flit_to_west [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1];
sc_signal <NoximFlit> flit_to_south [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1];
sc_signal <NoximFlit> flit_to_north [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1];
sc_signal <NoximFlit> flit_to_up [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1];
sc_signal <NoximFlit> flit_to_down [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1];
sc_signal <int> free_slots_to_east [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][DEFAULT_NUMBER_VIRTUAL_CHANNEL];
sc_signal <int> free_slots_to_west [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][DEFAULT_NUMBER_VIRTUAL_CHANNEL];
sc_signal <int> free_slots_to_south [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][DEFAULT_NUMBER_VIRTUAL_CHANNEL];
sc_signal <int> free_slots_to_north [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][DEFAULT_NUMBER_VIRTUAL_CHANNEL];
sc_signal <int> free_slots_to_up [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][DEFAULT_NUMBER_VIRTUAL_CHANNEL];
sc_signal <int> free_slots_to_down [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][DEFAULT_NUMBER_VIRTUAL_CHANNEL];
// NoP
sc_signal <NoximNoP_data> NoP_data_to_east [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1];
sc_signal <NoximNoP_data> NoP_data_to_west [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1];
sc_signal <NoximNoP_data> NoP_data_to_south [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1];
sc_signal <NoximNoP_data> NoP_data_to_north [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1];
sc_signal <NoximNoP_data> NoP_data_to_up [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1];
sc_signal <NoximNoP_data> NoP_data_to_down [MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1][MAX_STATIC_DIM + 1];
// Matrix of tiles
NoximTile *t[MAX_STATIC_DIM][MAX_STATIC_DIM][MAX_STATIC_DIM];
// Global tables
NoximGlobalRoutingTable grtable;
NoximGlobalTrafficTable gttable;
void flitsMonitor()
{
if (!reset.read())
{
unsigned int count = 0;
for(int i=0; i<NoximGlobalParams::mesh_dim_x; i++)
for(int j=0; j<NoximGlobalParams::mesh_dim_y; j++)
for(int k=0; k<NoximGlobalParams::mesh_dim_z; k++)
count += t[i][j][k]->r->getFlitsCount();
cout << count << endl;
}
}
// Constructor
SC_CTOR(NoximNoC)
{
// Build the Mesh
buildMesh();
}
// Support methods
NoximTile* searchNode(const int id) const;
private:
void buildMesh();
};
//---------------------------------------------------------------------------
#endif |
// TODO Generalise this code so it is easy for all new accelerators
#ifndef SYSTEMC_INTEGRATION
#define SYSTEMC_INTEGRATION
#include <systemc.h>
#include "../acc.sc.h"
// #include "tensorflow/lite/delegates/utils/secda_tflite/sysc_integrator/axi4s_engine.sc.h"
#include "tensorflow/lite/delegates/utils/secda_tflite/axi_support/axi_api_v2.h"
int sc_main(int argc, char* argv[]) { return 0; }
void sysC_init() {
sc_report_handler::set_actions("/IEEE_Std_1666/deprecated", SC_DO_NOTHING);
sc_report_handler::set_actions(SC_ID_LOGIC_X_TO_BOOL_, SC_LOG);
sc_report_handler::set_actions(SC_ID_VECTOR_CONTAINS_LOGIC_VALUE_, SC_LOG);
}
struct systemC_sigs {
sc_clock clk_fast;
sc_signal<bool> sig_reset;
sc_fifo<DATA> dout1;
sc_fifo<DATA> din1;
int id;
systemC_sigs(int _id)
: dout1("dout1_fifo", 563840), din1("din1_fifo", 554800) {
sc_clock clk_fast("ClkFast", 1, SC_NS);
id = _id;
}
};
void systemC_binder(ACCNAME* acc, stream_dma* sdma, systemC_sigs* scs) {
acc->clock(scs->clk_fast);
acc->reset(scs->sig_reset);
acc->dout1(scs->dout1);
acc->din1(scs->din1);
sdma->dmad->clock(scs->clk_fast);
sdma->dmad->reset(scs->sig_reset);
sdma->dmad->dout1(scs->dout1);
sdma->dmad->din1(scs->din1);
// static int* dma_input_address =
// (int*)malloc(65536 * sizeof(int));
// static int* dma_output_address =
// (int*)malloc(65536 * sizeof(int));
// // Initialize with zeros
// for (int64_t i = 0; i < 65536; i++) {
// *(dma_input_address + i) = 0;
// }
// for (int64_t i = 0; i < 65536; i++) {
// *(dma_output_address + i) = 0;
// }
// dmad->DMA_input_buffer = (int*)dma_input_address;
// dmad->DMA_output_buffer = (int*)dma_output_address;
}
#endif // SYSTEMC_INTEGRATION
|
/*
Problem 2 Design
*/
#include<systemc.h>
SC_MODULE(counters) {
sc_in<sc_uint<8> > in1 , in2 , in3;
sc_in<bool> dec1 , dec2 , clock , load1 , load2;
sc_out<sc_uint<8> > count1 , count2;
sc_out<bool> ended;
sc_signal<bool> isOverflow1 , isOverflow2;
void handleCount1();
void handleCount2();
void updateEnded();
SC_CTOR(counters) {
isOverflow1.write(false);
isOverflow2.write(false);
SC_METHOD(handleCount1);
sensitive<<clock.pos();
SC_METHOD(handleCount2);
sensitive<<clock.pos();
SC_METHOD(updateEnded);
sensitive<<clock.pos();
}
};
void counters::handleCount1() {
if(load1.read() == true) {
cout<<"@ "<<sc_time_stamp()<<"----------Start registerCount1---------"<<endl;
count1.write(in1.read());
cout<<"@ "<<sc_time_stamp()<<"----------End registerCount1---------"<<endl;
} else if(dec1.read() == true) {
cout<<"@ "<<sc_time_stamp()<<"----------Start decCount1---------"<<endl;
if(count1.read() == 0) {
isOverflow1.write(true);
return;
}
isOverflow1.write(false);
count1.write(count1.read() - 1);
cout<<"@ "<<sc_time_stamp()<<"----------End decCount1---------"<<endl;
}
}
void counters::handleCount2() {
if(load2.read() == true) {
cout<<"@ "<<sc_time_stamp()<<"----------Start registerCount2---------"<<endl;
count2.write(in2.read());
cout<<"@ "<<sc_time_stamp()<<"----------End registerCount2---------"<<endl;
} else if(dec2.read() == true) {
cout<<"@ "<<sc_time_stamp()<<"----------Start decCount2---------"<<endl;
if(count2.read() <= in3.read()) {
isOverflow2.write(true);
return;
}
isOverflow2.write(false);
count2.write(count2.read() - in3.read());
cout<<"@ "<<sc_time_stamp()<<"----------End decCount2---------"<<endl;
}
}
void counters::updateEnded() {
cout<<"@ "<<sc_time_stamp()<<"----------Start updateEnded---------"<<endl;
if(count1.read() == count2.read() || isOverflow1.read() || isOverflow2.read()) {
ended.write(true);
} else {
ended.write(false);
}
cout<<"@ "<<sc_time_stamp()<<"----------End updateEnded---------"<<endl;
} |
// TODO Generalise this code so it is easy for all new accelerators
#ifndef SYSTEMC_INTEGRATION
#define SYSTEMC_INTEGRATION
#include <systemc.h>
#include "../acc.sc.h"
// #include "tensorflow/lite/delegates/utils/secda_tflite/sysc_integrator/axi4s_engine.sc.h"
#include "tensorflow/lite/delegates/utils/secda_tflite/axi_support/axi_api_v2.h"
int sc_main(int argc, char* argv[]) { return 0; }
void sysC_init() {
sc_report_handler::set_actions("/IEEE_Std_1666/deprecated", SC_DO_NOTHING);
sc_report_handler::set_actions(SC_ID_LOGIC_X_TO_BOOL_, SC_LOG);
sc_report_handler::set_actions(SC_ID_VECTOR_CONTAINS_LOGIC_VALUE_, SC_LOG);
}
struct systemC_sigs {
sc_clock clk_fast;
sc_signal<bool> sig_reset;
sc_fifo<DATA> dout1;
sc_fifo<DATA> din1;
int id;
systemC_sigs(int _id)
: dout1("dout1_fifo", 563840), din1("din1_fifo", 554800) {
sc_clock clk_fast("ClkFast", 1, SC_NS);
id = _id;
}
};
void systemC_binder(ACCNAME* acc, stream_dma* sdma, systemC_sigs* scs) {
acc->clock(scs->clk_fast);
acc->reset(scs->sig_reset);
acc->dout1(scs->dout1);
acc->din1(scs->din1);
sdma->dmad->clock(scs->clk_fast);
sdma->dmad->reset(scs->sig_reset);
sdma->dmad->dout1(scs->dout1);
sdma->dmad->din1(scs->din1);
// static int* dma_input_address =
// (int*)malloc(65536 * sizeof(int));
// static int* dma_output_address =
// (int*)malloc(65536 * sizeof(int));
// // Initialize with zeros
// for (int64_t i = 0; i < 65536; i++) {
// *(dma_input_address + i) = 0;
// }
// for (int64_t i = 0; i < 65536; i++) {
// *(dma_output_address + i) = 0;
// }
// dmad->DMA_input_buffer = (int*)dma_input_address;
// dmad->DMA_output_buffer = (int*)dma_output_address;
}
#endif // SYSTEMC_INTEGRATION
|
#pragma once
#include <systemc.h>
#include "../../UTIL/debug_util.h"
SC_MODULE(alu) {
sc_in<sc_uint<32>> OP1_SE, OP2_SE;
sc_in<bool> CIN_SE;
sc_in<sc_uint<2>> CMD_SE;
sc_out<sc_uint<32>> RES_SE;
void operation();
void trace(sc_trace_file * tf);
SC_CTOR(alu) {
SC_METHOD(operation);
sensitive << OP1_SE << OP2_SE << CIN_SE << CMD_SE;
}
};
|
#ifndef __I2C_SLAVE_CONTROLLER_H
#define __I2C_SLAVE_CONTROLLER_H
#include <systemc.h>
SC_MODULE(i2c_slave_controller)
{
sc_inout<sc_logic> sda;
sc_inout<sc_logic> scl;
enum states {READ_ADDR, SEND_ACK, READ_DATA, WRITE_DATA, SEND_ACK2};
sc_signal<states> state;
const sc_lv<7> ADDRESS = "0101010";
sc_signal<sc_logic> sda_out;
sc_signal<bool> start;
sc_signal<bool> write_enable;
sc_lv<8> addr;
sc_uint<8> counter;
sc_lv<8> data_in;
sc_uint<8> data_out = 170;
SC_CTOR(i2c_slave_controller)
{
SC_METHOD(start_condition);
sensitive << sda.neg();
SC_METHOD(stop_condition);
sensitive << sda;
SC_METHOD(logic_fsm);
sensitive << scl.pos();
SC_METHOD(data_fsm);
sensitive << scl.neg();
}
void start_condition();
void stop_condition();
void logic_fsm();
void data_fsm();
};
#endif
|
/* Copyright 2017 Pedro Cuadra <[email protected]> & Meghadoot Gardi
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License. */
#ifndef FULL_ADDER_H_
#define FULL_ADDER_H_
#include<systemc.h>
SC_MODULE (full_adder) {
sc_in<bool> a, b, carry_in;
sc_out<bool> sum, carry_out;
void prc_full_adder();
SC_CTOR (full_adder) {
SC_METHOD (prc_full_adder);
sensitive << a << b << carry_in;
}
};
#endif
|
#include <systemc.h>
SC_MODULE(dual_memory)
{
}; |
/**********************************************************************
Filename: sc_fir8.h
Purpose : Core of 8-Tab Systolic FIR filter
Author : [email protected]
History : Mar. 2024, First release
***********************************************************************/
#ifndef _SC_FIR8_H_
#define _SC_FIR8_H_
#include <systemc.h>
#ifdef VERILATED
#include "V_fir_pe.h"
#endif
#ifdef EMULATED
#include "E_fir_pe.h"
#endif
#ifdef MTI_SIM
#include "fir_pe.h"
#endif
#if !defined(VERILATED) && !defined(MTI_SIM)
#include "sc_fir_pe.h"
#endif
#include "../c_untimed/fir8.h"
#define N_PE_ARRAY 8
SC_MODULE(sc_fir8)
{
sc_in<bool> clk;
sc_in<sc_uint<8> > Xin;
sc_out<sc_uint<8> > Xout;
sc_in<sc_uint<16> > Yin;
sc_out<sc_uint<16> > Yout;
#ifdef EMULATED
sc_out<sc_uint<8> > E_Xout;
sc_out<sc_uint<16> > E_Yout;
#endif
// void fir8_thread(void)
// {
// }
#ifdef VERILATED
V_fir_pe* u_fir_pe[N_PE_ARRAY];
#endif
#ifdef EMULATED
E_fir_pe* u_E_fir_pe;
// sc_signal<sc_uint<8> > E_Xout;
// sc_signal<sc_uint<16> > E_Yout;
#endif
#ifdef MTI_SIM
fir_pe* u_fir_pe[N_PE_ARRAY];
#endif
#if !defined(VERILATED) && !defined(MTI_SIM)
sc_fir_pe* u_fir_pe[N_PE_ARRAY];
#endif
sc_signal<sc_uint<8> > X[N_PE_ARRAY-1]; // X-input
sc_signal<sc_uint<16> > Y[N_PE_ARRAY-1]; // Accumulated
sc_signal<sc_uint<8> > C[N_PE_ARRAY]; // Filter-Tabs Coeff
#ifdef VCD_TRACE_FIR8
sc_trace_file* fp; // VCD file
#endif
SC_CTOR(sc_fir8):
clk("clk"),
Xin("Xin"),
Xout("Xout"),
Yin("Yin"),
Yout("Yout")
{
// SC_THREAD(fir8_thread);
// sensitive << clk;
// Instaltiate PE array -----------------------------
char szPeName[16];
for (int i=0; i<N_PE_ARRAY; i++)
{
sprintf(szPeName, "u_PE_%d", i);
#ifdef VERILATED
u_fir_pe[i] = new V_fir_pe(szPeName);
#endif
#ifdef MTI_SIM
u_fir_pe[i] = new fir_pe(szPeName);
#endif
#if !defined(VERILATED) && !defined(MTI_SIM)
u_fir_pe[i] = new sc_fir_pe(szPeName);
#endif
C[i].write(sc_uint<8>(filter_taps[i]));
u_fir_pe[i]->Cin(C[i]);
u_fir_pe[i]->clk(clk);
}
#ifdef EMULATED
u_E_fir_pe = new E_fir_pe("u_PE_Emulated");
u_E_fir_pe->Cin(C[N_PE_ARRAY-1]);
u_E_fir_pe->clk(clk);
#endif
// Configure Array -----------------------------------
// 0-th PE
u_fir_pe[0]->Xin(Xin);
u_fir_pe[0]->Xout(X[0]);
u_fir_pe[0]->Yin(Yin);
u_fir_pe[0]->Yout(Y[0]);
// Systolic Array
for (int i=1; i<N_PE_ARRAY-1; i++)
{
u_fir_pe[i]->Xin(X[i-1]);
u_fir_pe[i]->Xout(X[i]);
u_fir_pe[i]->Yin(Y[i-1]);
u_fir_pe[i]->Yout(Y[i]);
}
// Last PE
#ifdef EMULATED
u_E_fir_pe->Xin(X[N_PE_ARRAY-2]);
u_E_fir_pe->Xout(E_Xout);
u_E_fir_pe->Yin(Y[N_PE_ARRAY-2]);
u_E_fir_pe->Yout(E_Yout);
#endif
u_fir_pe[N_PE_ARRAY-1]->Xin(X[N_PE_ARRAY-2]);
u_fir_pe[N_PE_ARRAY-1]->Xout(Xout);
u_fir_pe[N_PE_ARRAY-1]->Yin(Y[N_PE_ARRAY-2]);
u_fir_pe[N_PE_ARRAY-1]->Yout(Yout);
#ifdef VCD_TRACE_FIR8
// WAVE
fp = sc_create_vcd_trace_file("sc_fir8");
fp->set_time_unit(100, SC_PS); // resolution (trace) ps
sc_trace(fp, clk, "clk");
sc_trace(fp, Xin, "Xin");
sc_trace(fp, Xout, "Xout");
sc_trace(fp, Yin, "Yin");
sc_trace(fp, Yout, "Yout");
#ifdef EMULATED
sc_trace(fp, E_Xout, "E_Xout");
sc_trace(fp, E_Yout, "E_Yout");
#endif
char szTrace[8];
for (int i=0; i<N_PE_ARRAY-1; i++)
{
sprintf(szTrace, "X_%d", i);
sc_trace(fp, X[i], szTrace);
sprintf(szTrace, "Y_%d", i);
sc_trace(fp, Y[i], szTrace);
}
#endif
}
~sc_fir8(void)
{
}
};
#endif
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2017 Cadence Design Systems, Inc. All rights reserved worldwide.
//
// The code contained herein is the proprietary and confidential information
// of Cadence or its licensors, and is supplied subject to a previously
// executed license and maintenance agreement between Cadence and customer.
// This code is intended for use with Cadence high-level synthesis tools and
// may not be used with other high-level synthesis tools. Permission is only
// granted to distribute the code as indicated. Cadence grants permission for
// customer to distribute a copy of this code to any partner to aid in designing
// or verifying the customer's intellectual property, as long as such
// distribution includes a restriction of no additional distributions from the
// partner, unless the partner receives permission directly from Cadence.
//
// ALL CODE FURNISHED BY CADENCE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY
// KIND, AND CADENCE SPECIFICALLY DISCLAIMS ANY WARRANTY OF NONINFRINGEMENT,
// FITNESS FOR A PARTICULAR PURPOSE OR MERCHANTABILITY. CADENCE SHALL NOT BE
// LIABLE FOR ANY COSTS OF PROCUREMENT OF SUBSTITUTES, LOSS OF PROFITS,
// INTERRUPTION OF BUSINESS, OR FOR ANY OTHER SPECIAL, CONSEQUENTIAL OR
// INCIDENTAL DAMAGES, HOWEVER CAUSED, WHETHER FOR BREACH OF WARRANTY,
// CONTRACT, TORT, NEGLIGENCE, STRICT LIABILITY OR OTHERWISE.
//
////////////////////////////////////////////////////////////////////////////////
#ifndef _DUT_H_
#define _DUT_H_
#include <systemc.h>
#include <stratus_hls.h>
#include <cynw_p2p.h>
#include "defines.h"
SC_MODULE( dut )
{
// Declare the clock and reset ports
sc_in< bool > clk;
sc_in< bool > rst;
// Declare the input port and the output port.
// The template specializations <DT_*> configure the
// modular interfaces to carry the desired datatypes.
// LAB EXERCISE: Add a second parameter to select TLM I/O
// OLD
cynw_p2p< input_t, CYN::TLM >::in din; // The input port
cynw_p2p< output_t, CYN::TLM >::out dout; // The output port
// NEW
//cynw_p2p< input_t, ioConfig >::in din; // The input port
//cynw_p2p< output_t, ioConfig >::out dout; // The output port
SC_CTOR( dut )
: clk( "clk" )
, rst( "rst" )
, din( "din" )
, dout( "dout" )
{
SC_CTHREAD( thread1, clk.pos() );
reset_signal_is( rst, 0 );
// Connect the clk and rst signals to the modular interface ports
din.clk_rst( clk, rst );
dout.clk_rst( clk, rst );
}
void thread1(); // the thread function
};
#endif // _DUT_H_
|
/**********************************************************************
Filename: sc_fir_pe.h
Purpose : PE of Systolic FIR filter
Author : [email protected]
History : Mar. 2024, First release
***********************************************************************/
#ifndef _SC_FIR_PE_H_
#define _SC_FIR_PE_H_
#include <systemc.h>
SC_MODULE(sc_fir_pe)
{
sc_in<bool> clk;
sc_in<sc_uint<8> > Cin;
sc_in<sc_uint<8> > Xin;
sc_out<sc_uint<8> > Xout;
sc_in<sc_uint<16> > Yin;
sc_out<sc_uint<16> > Yout;
sc_signal<sc_uint<16> > y;
void pe_thread(void)
{
//sc_uint<16> y=0; // Beware! Do NOT use variable for F/F model
while (true)
{
wait(clk.posedge_event());
Xout.write(Xin.read());
//y = Xin.read() * Cin.read() + Yin.read();
Yout.write(y);
y = Xin.read() * Cin.read() + Yin.read();
}
}
SC_CTOR(sc_fir_pe):
clk("clk"),
Cin("Cin"),
Xin("Xin"),
Xout("Xout"),
Yin("Yin"),
Yout("Yout")
{
SC_THREAD(pe_thread);
sensitive << clk;
}
~sc_fir_pe(void)
{
}
};
#endif
|
/**
#define meta ...
prInt32f("%s\n", meta);
**/
/*
All rights reserved to Alireza Poshtkohi (c) 1999-2023.
Email: [email protected]
Website: http://www.poshtkohi.info
*/
#ifndef __s2_h__
#define __s2_h__
#include <systemc.h>
SC_MODULE(s2)
{
sc_in<sc_uint<6> > stage1_input;
sc_out<sc_uint<4> > stage1_output;
void s2_box();
SC_CTOR(s2)
{
SC_METHOD(s2_box);
sensitive << stage1_input;
}
};
#endif
|
/**
#define meta ...
prInt32f("%s\n", meta);
**/
/*
All rights reserved to Alireza Poshtkohi (c) 1999-2023.
Email: [email protected]
Website: http://www.poshtkohi.info
*/
#ifndef __s1_h__
#define __s1_h__
#include <systemc.h>
SC_MODULE(s1)
{
sc_in<sc_uint<6> > stage1_input;
sc_out<sc_uint<4> > stage1_output;
void s1_box();
SC_CTOR(s1)
{
SC_METHOD(s1_box);
sensitive << stage1_input;
}
};
#endif
|
#include <systemc.h>
#include <string>
#include <vector>
#include <map>
#include <fstream>
#include <nana/gui.hpp>
#include <nana/gui/widgets/button.hpp>
#include <nana/gui/widgets/menubar.hpp>
#include <nana/gui/widgets/group.hpp>
#include <nana/gui/widgets/textbox.hpp>
#include <nana/gui/filebox.hpp>
#include "top.hpp"
#include "gui.hpp"
using std::fstream;
using std::map;
using std::string;
using std::vector;
int sc_main(int argc, char *argv[])
{
using namespace nana;
vector<string> instruction_queue;
string bench_name = "";
int nadd, nmul, nls, n_bits, bpb_size, cpu_freq, m_size;
m_size = 2;
nadd = 3;
nmul = nls = 2;
n_bits = 2;
bpb_size = 4;
cpu_freq = 500; // definido em Mhz - 500Mhz default
std::vector<int> sizes;
bool spec = false;
int mode = 0;
bool fila = false;
ifstream inFile;
form fm(API::make_center(1024, 700));
place plc(fm);
place upper(fm);
place lower(fm);
listbox table(fm);
listbox reg(fm);
listbox instruct(fm);
listbox rob(fm);
menubar mnbar(fm);
button start(fm);
button run_all(fm);
button clock_control(fm);
button exit(fm);
group clock_group(fm);
label clock_count(clock_group);
fm.caption("TFSim");
clock_group.caption("Ciclo");
clock_group.div("count");
grid memory(fm, rectangle(), 10, 50);
// Tempo de latencia de uma instrucao
// Novas instrucoes devem ser inseridas manualmente aqui
map<string, int> instruct_time{{"DADD", 4}, {"DADDI", 4}, {"DSUB", 6}, {"DSUBI", 6}, {"DMUL", 10}, {"DDIV", 16}, {"MEM", 2}, {"SLT", 1}, {"SGT", 1}};
// Responsavel pelos modos de execução
top top1("top");
start.caption("Start");
clock_control.caption("Next cycle");
run_all.caption("Run all");
exit.caption("Exit");
plc["rst"] << table;
plc["btns"] << start << clock_control << run_all << exit;
plc["memor"] << memory;
plc["regs"] << reg;
plc["rob"] << rob;
plc["instr"] << instruct;
plc["clk_c"] << clock_group;
clock_group["count"] << clock_count;
clock_group.collocate();
spec = false;
// set_spec eh so visual
set_spec(plc, spec);
plc.collocate();
mnbar.push_back("Opções");
menu &op = mnbar.at(0);
// menu::item_proxy spec_ip =
op.append("Especulação");
auto spec_sub = op.create_sub_menu(0);
// Modo com 1 preditor para todos os branchs
spec_sub->append("1 Preditor", [&](menu::item_proxy &ip)
{
if(ip.checked()){
spec = true;
mode = 1;
spec_sub->checked(1, false);
spec_sub->checked(2, false);
}
else{
spec = false;
mode = 0;
}
set_spec(plc,spec); });
spec_sub->append("2 Preditor M,N", [&](menu::item_proxy &ip)
{
if (ip.checked())
{
spec = true;
mode = 3;
spec_sub->checked(0, false);
spec_sub->checked(2, false);
}
else
{
spec = false;
mode = 0;
}
set_spec(plc,spec); });
// Modo com o bpb
spec_sub->append("Branch Prediction Buffer", [&](menu::item_proxy &ip)
{
if (ip.checked())
{
spec = true;
mode = 2;
spec_sub->checked(0, false);
spec_sub->checked(1, false);
}
else
{
spec = false;
mode = 0;
}
set_spec(plc, spec); });
spec_sub->check_style(0, menu::checks::highlight);
spec_sub->check_style(1, menu::checks::highlight);
spec_sub->check_style(2, menu::checks::highlight);
op.append("Modificar valores...");
// novo submenu para escolha do tamanho do bpb e do preditor
auto sub = op.create_sub_menu(1);
sub->append("Tamanho do BPB e Preditor", [&](menu::item_proxy &ip)
{
inputbox ibox(fm, "", "Definir tamanhos");
inputbox::integer size("BPB", bpb_size, 2, 10, 2);
inputbox::integer bits("N_BITS", n_bits, 1, 3, 1);
inputbox::integer m_size_input("M_SIZE", m_size, 1, 8, 1);
if (ibox.show_modal(size, bits, m_size_input))
{
bpb_size = size.value();
n_bits = bits.value();
m_size = m_size_input.value();
} });
sub->append("Número de Estações de Reserva", [&](menu::item_proxy ip)
{
inputbox ibox(fm, "", "Quantidade de Estações de Reserva");
inputbox::integer add("ADD/SUB", nadd, 1, 10, 1);
inputbox::integer mul("MUL/DIV", nmul, 1, 10, 1);
inputbox::integer sl("LOAD/STORE", nls, 1, 10, 1);
if (ibox.show_modal(add, mul, sl))
{
nadd = add.value();
nmul = mul.value();
nls = sl.value();
} });
// Menu de ajuste dos tempos de latencia na interface
// Novas instrucoes devem ser adcionadas manualmente aqui
sub->append("Tempos de latência", [&](menu::item_proxy &ip)
{
inputbox ibox(fm, "", "Tempos de latência para instruções");
inputbox::text dadd_t("DADD", std::to_string(instruct_time["DADD"]));
inputbox::text daddi_t("DADDI", std::to_string(instruct_time["DADDI"]));
inputbox::text dsub_t("DSUB", std::to_string(instruct_time["DSUB"]));
inputbox::text dsubi_t("DSUBI", std::to_string(instruct_time["DSUBI"]));
inputbox::text dmul_t("DMUL", std::to_string(instruct_time["DMUL"]));
inputbox::text ddiv_t("DDIV", std::to_string(instruct_time["DDIV"]));
inputbox::text mem_t("Load/Store", std::to_string(instruct_time["MEM"]));
if (ibox.show_modal(dadd_t, daddi_t, dsub_t, dsubi_t, dmul_t, ddiv_t, mem_t))
{
instruct_time["DADD"] = std::stoi(dadd_t.value());
instruct_time["DADDI"] = std::stoi(daddi_t.value());
instruct_time["DSUB"] = std::stoi(dsub_t.value());
instruct_time["DSUBI"] = std::stoi(dsubi_t.value());
instruct_time["DMUL"] = std::stoi(dmul_t.value());
instruct_time["DDIV"] = std::stoi(ddiv_t.value());
instruct_time["MEM"] = std::stoi(mem_t.value());
} });
sub->append("Frequência CPU", [&](menu::item_proxy &ip)
{
inputbox ibox(fm, "Em Mhz", "Definir frequência da CPU");
inputbox::text freq("Frequência", std::to_string(cpu_freq));
if (ibox.show_modal(freq))
{
cpu_freq = std::stoi(freq.value());
} });
sub->append("Fila de instruções", [&](menu::item_proxy &ip)
{
filebox fb(0, true);
inputbox ibox(fm, "Localização do arquivo com a lista de instruções:");
inputbox::path caminho("", fb);
if (ibox.show_modal(caminho))
{
auto path = caminho.value();
inFile.open(path);
if (!add_instructions(inFile, instruction_queue, instruct))
show_message("Arquivo inválido", "Não foi possível abrir o arquivo!");
else
fila = true;
} });
sub->append("Valores de registradores inteiros", [&](menu::item_proxy &ip)
{
filebox fb(0, true);
inputbox ibox(fm, "Localização do arquivo de valores de registradores inteiros:");
inputbox::path caminho("", fb);
if (ibox.show_modal(caminho))
{
auto path = caminho.value();
inFile.open(path);
if (!inFile.is_open())
show_message("Arquivo inválido", "Não foi possível abrir o arquivo!");
else
{
auto reg_gui = reg.at(0);
int value, i = 0;
while (inFile >> value && i < 32)
{
reg_gui.at(i).text(1, std::to_string(value));
i++;
}
for (; i < 32; i++)
reg_gui.at(i).text(1, "0");
inFile.close();
}
} });
sub->append("Valores de registradores PF", [&](menu::item_proxy &ip)
{
filebox fb(0, true);
inputbox ibox(fm, "Localização do arquivo de valores de registradores PF:");
inputbox::path caminho("", fb);
if (ibox.show_modal(caminho))
{
auto path = caminho.value();
inFile.open(path);
if (!inFile.is_open())
show_message("Arquivo inválido", "Não foi possível abrir o arquivo!");
else
{
auto reg_gui = reg.at(0);
int i = 0;
float value;
while (inFile >> value && i < 32)
{
reg_gui.at(i).text(4, std::to_string(value));
i++;
}
for (; i < 32; i++)
reg_gui.at(i).text(4, "0");
inFile.close();
}
} });
sub->append("Valores de memória", [&](menu::item_proxy &ip)
{
filebox fb(0, true);
inputbox ibox(fm, "Localização do arquivo de valores de memória:");
inputbox::path caminho("", fb);
if (ibox.show_modal(caminho))
{
auto path = caminho.value();
inFile.open(path);
if (!inFile.is_open())
show_message("Arquivo inválido", "Não foi possível abrir o arquivo!");
else
{
int i = 0;
int value;
while (inFile >> value && i < 500)
{
memory.Set(i, std::to_string(value));
i++;
}
for (; i < 500; i++)
{
memory.Set(i, "0");
}
inFile.close();
}
} });
op.append("Verificar conteúdo...");
auto new_sub = op.create_sub_menu(2);
new_sub->append("Valores de registradores", [&](menu::item_proxy &ip)
{
filebox fb(0, true);
inputbox ibox(fm, "Localização do arquivo de valores de registradores:");
inputbox::path caminho("", fb);
if (ibox.show_modal(caminho))
{
auto path = caminho.value();
inFile.open(path);
if (!inFile.is_open())
show_message("Arquivo inválido", "Não foi possível abrir o arquivo!");
else
{
string str;
int reg_pos, i;
bool is_float, ok;
ok = true;
while (inFile >> str)
{
if (str[0] == '$')
{
if (str[1] == 'f')
{
i = 2;
is_float = true;
}
else
{
i = 1;
is_float = false;
}
reg_pos = std::stoi(str.substr(i, str.size() - i));
auto reg_gui = reg.at(0);
string value;
inFile >> value;
if (!is_float)
{
if (reg_gui.at(reg_pos).text(1) != value)
{
ok = false;
break;
}
}
else
{
if (std::stof(reg_gui.at(reg_pos).text(4)) != std::stof(value))
{
ok = false;
break;
}
}
}
}
inFile.close();
msgbox msg("Verificação de registradores");
if (ok)
{
msg << "Registradores especificados apresentam valores idênticos!";
msg.icon(msgbox::icon_information);
}
else
{
msg << "Registradores especificados apresentam valores distintos!";
msg.icon(msgbox::icon_error);
}
msg.show();
}
} });
new_sub->append("Valores de memória", [&](menu::item_proxy &ip)
{
filebox fb(0, true);
inputbox ibox(fm, "Localização do arquivo de valores de memória:");
inputbox::path caminho("", fb);
if (ibox.show_modal(caminho))
{
auto path = caminho.value();
inFile.open(path);
if (!inFile.is_open())
show_message("Arquivo inválido", "Não foi possível abrir o arquivo!");
else
{
string value;
bool ok;
ok = true;
for (int i = 0; i < 500; i++)
{
inFile >> value;
if (std::stoi(memory.Get(i)) != (int)std::stol(value, nullptr, 16))
{
ok = false;
break;
}
}
inFile.close();
msgbox msg("Verificação de memória");
if (ok)
{
msg << "Endereços de memória especificados apresentam valores idênticos!";
msg.icon(msgbox::icon_information);
}
else
{
msg << "Endereços de memória especificados apresentam valores distintos!";
msg.icon(msgbox::icon_error);
}
msg.show();
}
} });
op.append("Benchmarks");
auto bench_sub = op.create_sub_menu(3);
bench_sub->append("Fibonacci", [&](menu::item_proxy &ip)
{
string path = "in/benchmarks/fibonacci/fibonacci.txt";
bench_name = "fibonacci";
inFile.open(path);
if (!add_instructions(inFile, instruction_queue, instruct))
show_message("Arquivo inválido", "Não foi possível abrir o arquivo!");
else
fila = true; });
bench_sub->append("Stall por Divisão", [&](menu::item_proxy &ip)
{
string path = "in/benchmarks/division_stall.txt";
inFile.open(path);
if (!add_instructions(inFile, instruction_queue, instruct))
show_message("Arquivo inválido", "Não foi possível abrir o arquivo!");
else
fila = true; });
bench_sub->append("Stress de Memória (Stores)", [&](menu::item_proxy &ip)
{
string path = "in/benchmarks/store_stress/store_stress.txt";
bench_name = "store_stress";
inFile.open(path);
if (!add_instructions(inFile, instruction_queue, instruct))
show_message("Arquivo inválido", "Não foi possível abrir o arquivo!");
else
fila = true; });
bench_sub->append("Stall por hazard estrutural (Adds)", [&](menu::item_proxy &ip)
{
string path = "in/benchmarks/res_stations_stall.txt";
inFile.open(path);
if (!add_instructions(inFile, instruction_queue, instruct))
show_message("Arquivo inválido", "Não foi possível abrir o arquivo!");
else
fila = true; });
bench_sub->append("Busca Linear", [&](menu::item_proxy &ip)
{
string path = "in/benchmarks/linear_search/linear_search.txt";
bench_name = "linear_search";
inFile.open(path);
if (!add_instructions(inFile, instruction_queue, instruct))
show_message("Arquivo inválido", "Não foi possível abrir o arquivo");
else
fila = true;
path = "in/benchmarks/linear_search/memory.txt";
inFile.open(path);
if (!inFile.is_open())
show_message("Arquivo inválido", "Não foi possível abrir o arquivo!");
else
{
int i = 0;
int value;
while (inFile >> value && i < 500)
{
memory.Set(i, std::to_string(value));
i++;
}
for (; i < 500; i++)
{
memory.Set(i, "0");
}
inFile.close();
}
path = "in/benchmarks/linear_search/regi_i.txt";
inFile.open(path);
if (!inFile.is_open())
show_message("Arquivo inválido", "Não foi possível abrir o arquivo!");
else
{
auto reg_gui = reg.at(0);
int value, i = 0;
while (inFile >> value && i < 32)
{
reg_gui.at(i).text(1, std::to_string(value));
i++;
}
for (; i < 32; i++)
reg_gui.at(i).text(1, "0");
inFile.close();
} });
bench_sub->append("Busca Binária", [&](menu::item_proxy &ip)
{
string path = "in/benchmarks/binary_search/binary_search.txt";
bench_name = "binary_search";
inFile.open(path);
if (!add_instructions(inFile, instruction_queue, instruct))
show_message("Arquivo inválido", "Não foi possível abrir o arquivo");
else
fila = true;
path = "in/benchmarks/binary_search/memory.txt";
inFile.open(path);
if (!inFile.is_open())
show_message("Arquivo inválido", "Não foi possível abrir o arquivo!");
else
{
int i = 0;
int value;
while (inFile >> value && i < 500)
{
memory.Set(i, std::to_string(value));
i++;
}
for (; i < 500; i++)
{
memory.Set(i, "0");
}
inFile.close();
}
path = "in/benchmarks/binary_search/regs.txt";
inFile.open(path);
if (!inFile.is_open())
show_message("Arquivo inválido", "Não foi possível abrir o arquivo!");
else
{
auto reg_gui = reg.at(0);
int value, i = 0;
while (inFile >> value && i < 32)
{
reg_gui.at(i).text(1, std::to_string(value));
i++;
}
for (; i < 32; i++)
reg_gui.at(i).text(1, "0");
inFile.close();
} });
bench_sub->append("Matriz Search", [&](menu::item_proxy &ip)
{
string path = "in/benchmarks/matriz_search/matriz_search.txt";
bench_name = "matriz_search";
inFile.open(path);
if (!add_instructions(inFile, instruction_queue, instruct))
show_message("Arquivo inválido", "Não foi possível abrir o arquivo");
else
fila = true;
path = "in/benchmarks/matriz_search/memory.txt";
inFile.open(path);
if (!inFile.is_open())
show_message("Arquivo inválido", "Não foi possível abrir o arquivo!");
else
{
int i = 0;
int value;
while (inFile >> value && i < 500)
{
memory.Set(i, std::to_string(value));
i++;
}
for (; i < 500; i++)
{
memory.Set(i, "0");
}
inFile.close();
}
path = "in/benchmarks/matriz_search/regs.txt";
inFile.open(path);
if (!inFile.is_open())
show_message("Arquivo inválido", "Não foi possível abrir o arquivo!");
else
{
auto reg_gui = reg.at(0);
int value, i = 0;
while (inFile >> value |
&& i < 32)
{
reg_gui.at(i).text(1, std::to_string(value));
i++;
}
for (; i < 32; i++)
reg_gui.at(i).text(1, "0");
inFile.close();
} });
bench_sub->append("Bubble Sort", [&](menu::item_proxy &ip)
{
string path = "in/benchmarks/bubble_sort/bubble_sort.txt";
bench_name = "bubble_sort";
inFile.open(path);
if (!add_instructions(inFile, instruction_queue, instruct))
show_message("Arquivo inválido", "Não foi possível abrir o arquivo");
else
fila = true;
path = "in/benchmarks/bubble_sort/memory.txt";
inFile.open(path);
if (!inFile.is_open())
show_message("Arquivo inválido", "Não foi possível abrir o arquivo!");
else
{
int i = 0;
int value;
while (inFile >> value && i < 500)
{
memory.Set(i, std::to_string(value));
i++;
}
for (; i < 500; i++)
{
memory.Set(i, "0");
}
inFile.close();
}
path = "in/benchmarks/bubble_sort/regs.txt";
inFile.open(path);
if (!inFile.is_open())
show_message("Arquivo inválido", "Não foi possível abrir o arquivo!");
else
{
auto reg_gui = reg.at(0);
int value, i = 0;
while (inFile >> value && i < 32)
{
reg_gui.at(i).text(1, std::to_string(value));
i++;
}
for (; i < 32; i++)
reg_gui.at(i).text(1, "0");
inFile.close();
} });
bench_sub->append("Insertion Sort", [&](menu::item_proxy &ip)
{
string path = "in/benchmarks/insertion_sort/insertion_sort.txt";
bench_name = "insertion_sort";
inFile.open(path);
if (!add_instructions(inFile, instruction_queue, instruct))
show_message("Arquivo inválido", "Não foi possível abrir o arquivo");
else
fila = true;
path = "in/benchmarks/insertion_sort/memory.txt";
inFile.open(path);
if (!inFile.is_open())
show_message("Arquivo inválido", "Não foi possível abrir o arquivo!");
else
{
int i = 0;
int value;
while (inFile >> value && i < 500)
{
memory.Set(i, std::to_string(value));
i++;
}
for (; i < 500; i++)
{
memory.Set(i, "0");
}
inFile.close();
}
path = "in/benchmarks/insertion_sort/regs.txt";
inFile.open(path);
if (!inFile.is_open())
show_message("Arquivo inválido", "Não foi possível abrir o arquivo!");
else
{
auto reg_gui = reg.at(0);
int value, i = 0;
while (inFile >> value && i < 32)
{
reg_gui.at(i).text(1, std::to_string(value));
i++;
}
for (; i < 32; i++)
reg_gui.at(i).text(1, "0");
inFile.close();
} });
bench_sub->append("Tick Tack", [&](menu::item_proxy &ip)
{
string path = "in/benchmarks/tick_tack/tick_tack.txt";
bench_name = "tick_tack";
inFile.open(path);
if (!add_instructions(inFile, instruction_queue, instruct))
show_message("Arquivo inválido", "Não foi possível abrir o arquivo");
else
fila = true;
path = "in/benchmarks/tick_tack/regs.txt";
inFile.open(path);
if (!inFile.is_open())
show_message("Arquivo inválido", "Não foi possível abrir o arquivo!");
else
{
auto reg_gui = reg.at(0);
int value, i = 0;
while (inFile >> value && i < 32)
{
reg_gui.at(i).text(1, std::to_string(value));
i++;
}
for (; i < 32; i++)
reg_gui.at(i).text(1, "0");
inFile.close();
} });
bench_sub->append("Double Interaction", [&](menu::item_proxy &ip)
{
string path = "in/benchmarks/double_interaction/double_interaction.txt";
bench_name = "double_interaction";
inFile.open(path);
if (!add_instructions(inFile, instruction_queue, instruct))
show_message("Arquivo inválido", "Não foi possível abrir o arquivo");
else
fila = true; });
bench_sub->append("Linear Search Extended", [&](menu::item_proxy &ip)
{
string path = "in/benchmarks/linear_search_extended/linear_search_extended.txt";
bench_name = "linear_search_extended";
inFile.open(path);
if (!add_instructions(inFile, instruction_queue, instruct))
show_message("Arquivo inválido", "Não foi possível abrir o arquivo");
else
fila = true; });
bench_sub->append("Log Calc", [&](menu::item_proxy &ip)
{
string path = "in/benchmarks/log_calc/log_calc.txt";
bench_name = "log_calc";
inFile.open(path);
if (!add_instructions(inFile, instruction_queue, instruct))
show_message("Arquivo inválido", "Não foi possível abrir o arquivo");
else
fila = true; });
bench_sub->append("Simple Loop", [&](menu::item_proxy &ip)
{
string path = "in/benchmarks/simple_loop/simple_loop.txt";
bench_name = "simple_loop";
inFile.open(path);
if (!add_instructions(inFile, instruction_queue, instruct))
show_message("Arquivo inválido", "Não foi possível abrir o arquivo");
else
fila = true; });
vector<string> columns = {"#", "Name", "Busy", "Op", "Vj", "Vk", "Qj", "Qk", "A"};
for (unsigned int i = 0; i < columns.size(); i++)
{
table.append_header(columns[i].c_str());
if (i && i != 3)
table.column_at(i).width(45);
else if (i == 3)
table.column_at(i).width(60);
else
table.column_at(i).width(30);
}
columns = {"", "Value", "Qi"};
sizes = {30, 75, 40};
for (unsigned int k = 0; k < 2; k++)
for (unsigned int i = 0; i < columns.size(); i++)
{
reg.append_header(columns[i]);
reg.column_at(k * columns.size() + i).width(sizes[i]);
}
auto reg_gui = reg.at(0);
for (int i = 0; i < 32; i++)
{
string index = std::to_string(i);
reg_gui.append("R" + index);
reg_gui.at(i).text(3, "F" + index);
}
columns = {"Instruction", "Issue", "Execute", "Write Result"};
sizes = {140, 60, 70, 95};
for (unsigned int i = 0; i < columns.size(); i++)
{
instruct.append_header(columns[i]);
instruct.column_at(i).width(sizes[i]);
}
columns = {"Entry", "Busy", "Instruction", "State", "Destination", "Value"};
sizes = {45, 45, 120, 120, 90, 60};
for (unsigned int i = 0; i < columns.size(); i++)
{
rob.append_header(columns[i]);
rob.column_at(i).width(sizes[i]);
}
srand(static_cast<unsigned>(time(0)));
for (int i = 0; i < 32; i++)
{
if (i)
reg_gui.at(i).text(1, std::to_string(rand() % 100));
else
reg_gui.at(i).text(1, std::to_string(0));
reg_gui.at(i).text(2, "0");
reg_gui.at(i).text(4, std::to_string(static_cast<float>(rand()) / static_cast<float>(RAND_MAX / 100.0)));
reg_gui.at(i).text(5, "0");
}
for (int i = 0; i < 500; i++)
memory.Push(std::to_string(rand() % 100));
for (int k = 1; k < argc; k += 2)
{
int i;
if (strlen(argv[k]) > 2)
show_message("Opção inválida", string("Opção \"") + string(argv[k]) + string("\" inválida"));
else
{
char c = argv[k][1];
switch (c)
{
case 'q':
inFile.open(argv[k + 1]);
if (!add_instructions(inFile, instruction_queue, instruct))
show_message("Arquivo inválido", "Não foi possível abrir o arquivo!");
else
fila = true;
break;
case 'i':
inFile.open(argv[k + 1]);
int value;
i = 0;
if (!inFile.is_open())
show_message("Arquivo inválido", "Não foi possível abrir o arquivo!");
else
{
while (inFile >> value && i < 32)
{
reg_gui.at(i).text(1, std::to_string(value));
i++;
}
for (; i < 32; i++)
reg_gui.at(i).text(1, "0");
inFile.close();
}
break;
case 'f':
float value_fp;
i = 0;
inFile.open(argv[k + 1]);
if (!inFile.is_open())
show_message("Arquivo inválido", "Não foi possível abrir o arquivo!");
else
{
while (inFile >> value_fp && i < 32)
{
reg_gui.at(i).text(4, std::to_string(value_fp));
i++;
}
for (; i < 32; i++)
reg_gui.at(i).text(4, "0");
inFile.close();
}
break;
case 'm':
inFile.open(argv[k + 1]);
if (!inFile.is_open())
show_message("Arquivo inválido", "Não foi possível abrir o arquivo!");
else
{
int value;
i = 0;
while (inFile >> value && i < 500)
{
memory.Set(i, std::to_string(value));
i++;
}
for (; i < 500; i++)
{
memory.Set(i, "0");
}
inFile.close();
}
break;
case 'r':
inFile.open(argv[k + 1]);
if (!inFile.is_open())
show_message("Arquivo inválido", "Não foi possível abrir o arquivo!");
else
{
int value;
if (inFile >> value && value <= 10 && value > 0)
nadd = value;
if (inFile >> value && value <= 10 && value > 0)
nmul = value;
if (inFile >> value && value <= 10 && value > 0)
nls = value;
inFile.close();
}
break;
case 's':
spec = true;
set_spec(plc, spec);
// spec_ip.checked(true);
k--;
break;
case 'l':
inFile.open(argv[k + 1]);
if (!inFile.is_open())
show_message("Arquivo inválido", "Não foi possível abrir o arquivo!");
else
{
string inst;
int value;
while (inFile >> inst)
{
if (inFile >> value && instruct_time.count(inst))
instruct_time[inst] = value;
}
}
inFile.close();
break;
default:
show_message("Opção inválida", string("Opção \"") + string(argv[k]) + string("\" inválida"));
break;
}
}
}
clock_control.enabled(false);
run_all.enabled(false);
start.events().click([&]
{
if (fila)
{
start.enabled(false);
clock_control.enabled(true);
run_all.enabled(true);
// Desativa os menus apos inicio da execucao
op.enabled(0, false);
op.enabled(1, false);
op.enabled(3, false);
for (int i = 0; i < 2; i++)
spec_sub->enabled(i, false);
for (int i = 0; i < 8; i++)
sub->enabled(i, false);
for (int i = 0; i < 10; i++)
bench_sub->enabled(i, false);
if (spec)
{
// Flag mode setada pela escolha no menu
if (mode == 1)
top1.rob_mode(n_bits, nadd, nmul, nls, instruct_time, instruction_queue, table, memory, reg, instruct, clock_count, rob);
else if(mode == 3)
top1.rob_mode_mn(n_bits,nadd,nmul,nls,instruct_time,instruction_queue,table,memory,reg,instruct,clock_count,rob, m_size);
else if (mode == 2)
top1.rob_mode_bpb(n_bits, bpb_size, nadd, nmul, nls, instruct_time, instruction_queue, table, memory, reg, instruct, clock_count, rob);
}
else
top1.simple_mode(nadd, nmul, nls, instruct_time, instruction_queue, table, memory, reg, instruct, clock_count);
sc_start();
}
else
show_message("Fila de instruções vazia", "A fila de instruções está vazia. Insira um conjunto de instruções para iniciar."); });
clock_control.events().click([&]
{
if (top1.get_queue().queue_is_empty() && top1.get_rob().rob_is_empty())
return;
if (sc_is_running())
sc_start(); });
run_all.events().click([&]
{
// enquanto queue e rob nao estao vazios, roda ate o fim
while (!(top1.get_queue().queue_is_empty() && top1.get_rob().rob_is_empty()))
{
if (sc_is_running())
sc_start();
}
top1.metrics(cpu_freq, mode, bench_name, n_bits); });
exit.events().click([]
{
sc_stop();
API::exit(); });
fm.show();
exec();
return 0;
}
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2017 Cadence Design Systems, Inc. All rights reserved worldwide.
//
// The code contained herein is the proprietary and confidential information
// of Cadence or its licensors, and is supplied subject to a previously
// executed license and maintenance agreement between Cadence and customer.
// This code is intended for use with Cadence high-level synthesis tools and
// may not be used with other high-level synthesis tools. Permission is only
// granted to distribute the code as indicated. Cadence grants permission for
// customer to distribute a copy of this code to any partner to aid in designing
// or verifying the customer's intellectual property, as long as such
// distribution includes a restriction of no additional distributions from the
// partner, unless the partner receives permission directly from Cadence.
//
// ALL CODE FURNISHED BY CADENCE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY
// KIND, AND CADENCE SPECIFICALLY DISCLAIMS ANY WARRANTY OF NONINFRINGEMENT,
// FITNESS FOR A PARTICULAR PURPOSE OR MERCHANTABILITY. CADENCE SHALL NOT BE
// LIABLE FOR ANY COSTS OF PROCUREMENT OF SUBSTITUTES, LOSS OF PROFITS,
// INTERRUPTION OF BUSINESS, OR FOR ANY OTHER SPECIAL, CONSEQUENTIAL OR
// INCIDENTAL DAMAGES, HOWEVER CAUSED, WHETHER FOR BREACH OF WARRANTY,
// CONTRACT, TORT, NEGLIGENCE, STRICT LIABILITY OR OTHERWISE.
//
////////////////////////////////////////////////////////////////////////////////
#ifndef SYSTEM_H
#define SYSTEM_H
#include <systemc.h>
#include <cynw_p2p.h>
#include "defines.h"
#include "tb.h"
// LAB EXERCISE: Include memory header file
// NEW
#include "memlib.h"
#include "dut_wrap.h" // use the generated wrapper for all HLS modules
SC_MODULE( System )
{
// clock and reset signals
sc_clock clk_sig;
sc_signal< bool > rst_sig;
// cynw_p2p channels
cynw_p2p< input_t > chan1;
cynw_p2p< output_t > chan2;
// Declare pointers for the testbench and dut modules
dut_wrapper *m_dut; // use the generated wrapper for all HLS modules
tb *m_tb;
// LAB EXERCISE: Declare a pointer for the memory
// NEW
RAM_64x8::wrapper<> *m_mem;
SC_CTOR( System )
: clk_sig( "clk_sig", CLOCK_PERIOD, SC_NS )
, rst_sig( "rst_sig" )
, chan1( "chan1" )
, chan2( "chan2" )
{
// Connect the design module
m_dut = new dut_wrapper( "dut_wrapper" );
m_dut->clk( clk_sig );
m_dut->rst( rst_sig );
m_dut->din( chan1 );
m_dut->dout( chan2 );
// Connect the testbench
m_tb = new tb( "tb" );
m_tb->clk( clk_sig );
m_tb->rst( rst_sig );
m_tb->dout( chan1 );
m_tb->din( chan2 );
// LAB EXERCISE: Instantiate and connect the memory
// NEW
m_mem = new RAM_64x8::wrapper<>("mem");
m_dut->mem( *m_mem );
m_mem->clk_rst( clk_sig, rst_sig );
}
~System()
{
delete m_tb;
delete m_dut;
}
};
#endif // SYSTEM_H
|
/*******************************************************************************
* serial_tft.h -- Copyright 2019 (c) Glenn Ramalho - RFIDo Design
*******************************************************************************
* Description:
* This is a simple model for a ST7735 based screen module.
*******************************************************************************
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
#ifndef _SERIAL_TFT
#define _SERIAL_TFT
#include <systemc.h>
#include "gn_mixed.h"
#include "st7735.h"
SC_MODULE(serial_tft) {
sc_in<gn_mixed> sck {"sck"};
sc_inout<gn_mixed> sda {"sda"};
sc_in<gn_mixed> res {"res"};
sc_in<gn_mixed> rs {"rs"};
sc_in<gn_mixed> cs {"cs"};
st7735 i_controller{"i_controller"};
gn_tie logic_0 {"logic_0", GN_LOGIC_0};
gn_tie logic_1 {"logic_0", GN_LOGIC_1};
sc_signal<gn_mixed> osc {"osc"};
sc_signal<gn_mixed> te {"te"};
sc_signal<sc_bv<3> > im {"im", 7};
SC_CTOR(serial_tft) {
i_controller.scl_dcx(sck);
i_controller.sda(sda);
i_controller.csx(cs);
i_controller.resx(res);
i_controller.wrx(rs);
i_controller.im(im);
i_controller.spi4w(logic_1);
i_controller.rdx(logic_0);
i_controller.d0(logic_0);
i_controller.d1(logic_0);
i_controller.d2(logic_0);
i_controller.d3(logic_0);
i_controller.d4(logic_0);
i_controller.d5(logic_0);
i_controller.d6(logic_0);
i_controller.d7(logic_0);
i_controller.d8(logic_0);
i_controller.d9(logic_0);
i_controller.d10(logic_0);
i_controller.d11(logic_0);
i_controller.d12(logic_0);
i_controller.d13(logic_0);
i_controller.d14(logic_0);
i_controller.d15(logic_0);
i_controller.d16(logic_0);
i_controller.d17(logic_0);
i_controller.te(te);
i_controller.osc(osc);
}
void trace(sc_trace_file *tf) {
trace(tf, sck, sck.name());
trace(tf, sda, sda.name());
trace(tf, res, res.name());
trace(tf, rs, rs.name());
trace(tf, cs, cs.name());
i_controller.trace(tf);
}
};
#endif
|
/*******************************************************************************
* clkgen.h -- Copyright 2019 (c) Glenn Ramalho - RFIDo Design
*******************************************************************************
* Description:
* Emulates the clocks on the ESP32.
*******************************************************************************
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
#ifndef _CLKGEN_H
#define _CLKGEN_H
#include <systemc.h>
SC_MODULE(clkgen) {
sc_out<bool> apb_clk {"apb_clk"};
/* Threads */
void gen(void);
/* Sets initial drive condition. */
SC_CTOR(clkgen) {
SC_THREAD(gen);
}
};
#endif
|
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