text
stringlengths 41
20k
|
|---|
#include "systemc.h"
#include <bitset>
#include "../cnm_base.h"
SC_MODULE(pch_monitor) {
#if MIXED_SIM
sc_in<sc_logic> clk;
sc_in<sc_logic> rst;
sc_in<sc_logic> RD; // DRAM read command
sc_in<sc_logic> WR; // DRAM write command
sc_in<sc_logic> ACT; // DRAM activate command
// sc_in<sc_logic> RSTB; //
sc_in<sc_logic> AB_mode; // Signals if the All-Banks mode is enabled
sc_in<sc_logic> pim_mode; // Signals if the PIM mode is enabled
sc_in<sc_lv<BANK_BITS> > bank_addr; // Address of the bank
sc_in<sc_lv<ROW_BITS> > row_addr; // Address of the bank row
sc_in<sc_lv<COL_BITS> > col_addr; // Address of the bank column
sc_in<sc_lv<DQ_BITS> > DQ; // Data input from DRAM controller (output makes no sense)
sc_in<sc_lv<GRF_WIDTH> > even_in[CORES_PER_PCH]; // Direct data in/out to the even banks
sc_in<sc_lv<GRF_WIDTH> > odd_in[CORES_PER_PCH]; // Direct data in/out to the odd banks
sc_in<sc_lv<GRF_WIDTH> > even_out[CORES_PER_PCH];// Direct data in/out to the even banks
sc_in<sc_lv<GRF_WIDTH> > odd_out[CORES_PER_PCH]; // Direct data in/out to the odd banks
#else
sc_in_clk clk;
sc_in<bool> rst;
sc_in<bool> RD; // DRAM read command
sc_in<bool> WR; // DRAM write command
sc_in<bool> ACT; // DRAM activate command
// sc_in<bool> RSTB; //
sc_in<bool> AB_mode; // Signals if the All-Banks mode is enabled
sc_in<bool> pim_mode; // Signals if the PIM mode is enabled
sc_in<sc_uint<BANK_BITS> > bank_addr; // Address of the bank
sc_in<sc_uint<ROW_BITS> > row_addr; // Address of the bank row
sc_in<sc_uint<COL_BITS> > col_addr; // Address of the bank column
sc_in<sc_uint<DQ_BITS> > DQ; // Data input from DRAM controller (output makes no sense)
sc_inout_rv<GRF_WIDTH> even_buses[CORES_PER_PCH]; // Direct data in/out to the even banks
sc_inout_rv<GRF_WIDTH> odd_buses[CORES_PER_PCH]; // Direct data in/out to the odd banks
#endif
// Internal events
// Internal variables and signals for checking
SC_CTOR(pch_monitor) {
SC_THREAD(monitor_thread);
sensitive << clk.pos() << rst.neg();
}
void monitor_thread(); // Outputs the behavior and automatically checks the functionality
// void mirror_thread(); // Mirror IMC core behavior for checking its functionality
// void out_mirror_thread(); // Mirror IMC core output for checking functionality
};
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
#ifndef _blockdesign_1_xlconstant_3_0_H_
#define _blockdesign_1_xlconstant_3_0_H_
#include "xlconstant_v1_1_7.h"
#include "systemc.h"
class blockdesign_1_xlconstant_3_0 : public sc_module {
public:
xlconstant_v1_1_7<1,0> mod;
sc_out< sc_bv<1> > dout;
blockdesign_1_xlconstant_3_0 (sc_core::sc_module_name name);
};
#endif
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.1
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ===========================================================
#ifndef _memcachedPipeline_bp_r_HH_
#define _memcachedPipeline_bp_r_HH_
#include "systemc.h"
#include "AESL_pkg.h"
namespace ap_rtl {
struct memcachedPipeline_bp_r : public sc_module {
// Port declarations 19
sc_in_clk ap_clk;
sc_in< sc_logic > ap_rst;
sc_in< sc_logic > ap_start;
sc_out< sc_logic > ap_done;
sc_in< sc_logic > ap_continue;
sc_out< sc_logic > ap_idle;
sc_out< sc_logic > ap_ready;
sc_in< sc_lv<64> > keyBuffer_rp_V_V_dout;
sc_in< sc_logic > keyBuffer_rp_V_V_empty_n;
sc_out< sc_logic > keyBuffer_rp_V_V_read;
sc_in< sc_lv<64> > valueBuffer_rp_V_V_dout;
sc_in< sc_logic > valueBuffer_rp_V_V_empty_n;
sc_out< sc_logic > valueBuffer_rp_V_V_read;
sc_in< sc_lv<248> > metadataBuffer_rp_V_V_dout;
sc_in< sc_logic > metadataBuffer_rp_V_V_empty_n;
sc_out< sc_logic > metadataBuffer_rp_V_V_read;
sc_out< sc_lv<256> > requestParser2hashTable_V_din;
sc_in< sc_logic > requestParser2hashTable_V_full_n;
sc_out< sc_logic > requestParser2hashTable_V_write;
// Module declarations
memcachedPipeline_bp_r(sc_module_name name);
SC_HAS_PROCESS(memcachedPipeline_bp_r);
~memcachedPipeline_bp_r();
sc_trace_file* mVcdFile;
sc_signal< sc_logic > ap_done_reg;
sc_signal< sc_lv<1> > ap_CS_fsm0;
sc_signal< sc_logic > ap_sig_cseq_ST_st1_fsm0_0;
sc_signal< bool > ap_sig_bdd_23;
sc_signal< sc_lv<2> > ap_CS_fsm1;
sc_signal< sc_logic > ap_sig_cseq_ST_st0_fsm1_0;
sc_signal< bool > ap_sig_bdd_34;
sc_signal< sc_lv<1> > tmp_147_fu_439_p2;
sc_signal< sc_lv<1> > grp_nbreadreq_fu_138_p3;
sc_signal< sc_lv<1> > tmp_149_fu_445_p2;
sc_signal< sc_lv<1> > grp_nbreadreq_fu_146_p3;
sc_signal< sc_lv<1> > tmp_s_fu_523_p2;
sc_signal< sc_lv<1> > tmp_150_fu_539_p2;
sc_signal< sc_lv<1> > tmp_148_fu_529_p2;
sc_signal< sc_lv<1> > tmp_153_fu_582_p2;
sc_signal< sc_lv<1> > tmp_nbreadreq_fu_166_p3;
sc_signal< bool > ap_sig_bdd_126;
sc_signal< sc_lv<2> > binaryParserRearState_load_reg_722;
sc_signal< sc_lv<1> > tmp_147_reg_732;
sc_signal< sc_lv<1> > tmp_149_reg_740;
sc_signal< sc_lv<1> > tmp_46_reg_736;
sc_signal< sc_lv<1> > tmp_48_reg_744;
sc_signal< sc_lv<1> > tmp_s_reg_752;
sc_signal< sc_lv<1> > tmp_45_reg_756;
sc_signal< sc_lv<1> > tmp_148_reg_760;
sc_signal< sc_lv<1> > tmp_47_reg_764;
sc_signal< bool > ap_sig_bdd_185;
sc_signal< sc_logic > ap_sig_cseq_ST_st2_fsm1_1;
sc_signal< bool > ap_sig_bdd_191;
sc_signal< sc_lv<2> > binaryParserRearState;
sc_signal< sc_lv<248> > outMetadataBuffer_V;
sc_signal< sc_lv<8> > bpr_opCode;
sc_signal< sc_lv<16> > bpr_valueLength;
sc_signal< sc_lv<8> > bpr_keyLength;
sc_signal< sc_lv<1> > bpr_wordCounter_V;
sc_signal< sc_lv<1> > tmp_valueValid_V_5_reg_196;
sc_signal< sc_lv<248> > p_Val2_23_reg_726;
sc_signal< sc_lv<1> > or_cond_fu_511_p2;
sc_signal< sc_lv<1> > or_cond_reg_748;
sc_signal< sc_lv<1> > ap_reg_ppstg_or_cond_reg_748_pp0_it0;
sc_signal< sc_lv<8> > storemerge3_fu_463_p3;
sc_signal< sc_lv<8> > ap_reg_phiprechg_bpr_keyLength_load_4_reg_187pp0_it0;
sc_signal< sc_lv<8> > bpr_keyLength_load_4_phi_fu_190_p4;
sc_signal< sc_lv<1> > ap_reg_phiprechg_tmp_valueValid_V_5_reg_196pp0_it0;
sc_signal< sc_lv<1> > tmp_valueValid_V_5_phi_fu_199_p4;
sc_signal< sc_lv<16> > ap_reg_phiprechg_tmp_160_reg_208pp0_it0;
sc_signal< sc_lv<16> > tmp_160_phi_fu_211_p4;
sc_signal< sc_lv<16> > storemerge_fu_490_p3;
sc_signal< sc_lv<8> > ap_reg_phiprechg_bpr_opCode_load_3_reg_217pp0_it0;
sc_signal< sc_lv<8> > bpr_opCode_load_3_phi_fu_220_p6;
sc_signal< sc_lv<16> > storemerge4_fu_600_p3;
sc_signal< sc_lv<16> > ap_reg_phiprechg_bpr_valueLength_new_reg_229pp0_it0;
sc_signal< sc_lv<16> > bpr_valueLength_new_phi_fu_232_p4;
sc_signal< sc_lv<16> > p_Result_s_93_fu_545_p4;
sc_signal< sc_lv<1> > ap_reg_phiprechg_bpr_valueLength_flag_4_reg_238pp0_it0;
sc_signal< sc_lv<1> > bpr_valueLength_flag_4_phi_fu_241_p16;
sc_signal< sc_lv<16> > ap_reg_phiprechg_bpr_valueLength_new_4_reg_268pp0_it0;
sc_signal< sc_lv<16> > bpr_valueLength_new_4_phi_fu_271_p16;
sc_signal< sc_lv<1> > ap_reg_phiprechg_tmp_keyValid_V_reg_297pp0_it0;
sc_signal< sc_lv<1> > ap_reg_phiprechg_tmp_keyValid_V_reg_297pp0_it1;
sc_signal< sc_lv<64> > ap_reg_phiprechg_tmp_key_V_11_reg_310pp0_it0;
sc_signal< sc_lv<64> > ap_reg_phiprechg_tmp_key_V_11_reg_310pp0_it1;
sc_signal< sc_lv<64> > ap_reg_phiprechg_tmp_value_V_7_reg_321pp0_it0;
sc_signal< sc_lv<64> > ap_reg_phiprechg_tmp_value_V_7_reg_321pp0_it1;
sc_signal< sc_lv<1> > not_bpr_wordCounter_V_load_fu_662_p2;
sc_signal< sc_lv<1> > ap_reg_phiprechg_bpr_wordCounter_V_flag_1_reg_332pp0_it1;
sc_signal< sc_lv<1> > bpr_wordCounter_V_flag_1_phi_fu_336_p4;
sc_signal< sc_lv<1> > ap_reg_phiprechg_bpr_wordCounter_V_flag_1_reg_332pp0_it0;
sc_signal< sc_lv<1> > ap_reg_phiprechg_bpr_wordCounter_V_new_1_reg_343pp0_it1;
sc_signal< sc_lv<1> > bpr_wordCounter_V_new_1_phi_fu_347_p4;
sc_signal< sc_lv<1> > ap_reg_phiprechg_bpr_wordCounter_V_new_1_reg_343pp0_it0;
sc_signal< sc_lv<1> > ap_reg_phiprechg_tmp_EOP_V_reg_355pp0_it1;
sc_signal< sc_lv<1> > tmp_EOP_V_phi_fu_359_p4;
sc_signal< sc_lv<1> > ap_reg_phiprechg_tmp_EOP_V_reg_355pp0_it0;
sc_signal< sc_lv<64> > ap_reg_phiprechg_tempOutput_key_V_reg_367pp0_it0;
sc_signal< sc_lv<64> > ap_reg_phiprechg_tempOutput_key_V_reg_367pp0_it1;
sc_signal< sc_lv<1> > ap_reg_phiprechg_tmp_valueValid_V_reg_378pp0_it0;
sc_signal< sc_lv<1> > ap_reg_phiprechg_tmp_valueValid_V_reg_378pp0_it1;
sc_signal< sc_lv<64> > ap_reg_phiprechg_tmp_value_V_reg_391pp0_it0;
sc_signal< sc_lv<64> > ap_reg_phiprechg_tmp_value_V_reg_391pp0_it1;
sc_signal< sc_lv<256> > tmp_1_fu_677_p8;
sc_signal< sc_lv<256> > tmp78_fu_705_p7;
sc_signal< sc_lv<8> > storemerge2_fu_568_p3;
sc_signal< sc_lv<1> > tmp_154_fu_451_p2;
sc_signal< sc_lv<8> > tmp_155_fu_457_p2;
sc_signal< sc_lv<1> > tmp_158_fu_478_p2;
sc_signal< sc_lv<16> > tmp_159_fu_484_p2;
sc_signal< sc_lv<1> > notrhs_fu_505_p2;
sc_signal< sc_lv<1> > notlhs_fu_499_p2;
sc_signal< sc_lv<8> > tmp_291_fu_535_p1;
sc_signal< sc_lv<1> > tmp_151_fu_556_p2;
sc_signal< sc_lv<8> > tmp_152_fu_562_p2;
sc_signal< sc_lv<1> > tmp_156_fu_588_p2;
sc_signal< sc_lv<16> > tmp_157_fu_594_p2;
sc_signal< sc_lv<124> > tempOutput_metadata_V_fu_653_p4;
sc_signal< sc_lv<124> > tmp_metadata_V_11_fu_669_p3;
sc_signal< sc_lv<124> > tempOutput_metadata_V_2_fu_702_p1;
sc_signal< sc_lv<1> > ap_NS_fsm0;
sc_signal< sc_lv<2> > ap_NS_fsm1;
sc_signal< bool > ap_sig_bdd_443;
sc_signal< bool > ap_sig_bdd_198;
sc_signal< bool > ap_sig_bdd_96;
sc_signal< bool > ap_sig_bdd_461;
sc_signal< bool > ap_sig_bdd_63;
sc_signal< bool > ap_sig_bdd_306;
sc_signal< bool > ap_sig_bdd_105;
sc_signal< bool > ap_sig_bdd_353;
sc_signal< bool > ap_sig_bdd_314;
sc_signal< bool > ap_sig_bdd_77;
sc_signal< bool > ap_sig_bdd_389;
sc_signal< bool > ap_sig_bdd_117;
sc_signal< bool > ap_sig_bdd_298;
sc_signal< bool > ap_sig_bdd_275;
sc_signal< bool > ap_sig_bdd_160;
sc_signal< bool > ap_sig_bdd_183;
sc_signal< bool > ap_sig_bdd_409;
static const sc_logic ap_const_logic_1;
static const sc_logic ap_const_logic_0;
static const sc_lv<1> ap_ST_st1_fsm0_0;
static const sc_lv<2> ap_ST_st2_fsm1_1;
static const sc_lv<2> ap_ST_st0_fsm1_0;
static const sc_lv<32> ap_const_lv32_0;
static const sc_lv<1> ap_const_lv1_1;
static const sc_lv<2> ap_const_lv2_2;
static const sc_lv<1> ap_const_lv1_0;
static const sc_lv<2> ap_const_lv2_1;
static const sc_lv<2> ap_const_lv2_0;
static const sc_lv<32> ap_const_lv32_1;
static const sc_lv<248> ap_const_lv248_lc_1;
static const sc_lv<8> ap_const_lv8_0;
static const sc_lv<16> ap_const_lv16_0;
static const sc_lv<8> ap_const_lv8_1;
static const sc_lv<64> ap_const_lv64_0;
static const sc_lv<8> ap_const_lv8_8;
static const sc_lv<8> ap_const_lv8_F8;
static const sc_lv<16> ap_const_lv16_8;
static const sc_lv<16> ap_const_lv16_FFF8;
static const sc_lv<32> ap_const_lv32_8;
static const sc_lv<32> ap_const_lv32_17;
static const sc_lv<8> ap_const_lv8_9;
static const sc_lv<32> ap_const_lv32_68;
static const sc_lv<32> ap_const_lv32_6F;
static const sc_lv<32> ap_const_lv32_7C;
static const sc_lv<32> ap_const_lv32_F7;
static const sc_lv<124> ap_const_lv124_0;
static const sc_lv<2> ap_const_lv2_3;
static const bool ap_true;
// Thread declarations
void thread_ap_clk_pos_reset_();
void thread_ap_done();
void thread_ap_idle();
void thread_ap_ready();
void thread_ap_reg_phiprechg_bpr_keyLength_load_4_reg_187pp0_it0();
void thread_ap_reg_phiprechg_bpr_opCode_load_3_reg_217pp0_it0();
void thread_ap_reg_phiprechg_bpr_valueLength_flag_4_reg_238pp0_it0();
void thread_ap_reg_phiprechg_bpr_valueLength_new_4_reg_268pp0_it0();
void thread_ap_reg_phiprechg_bpr_valueLength_new_reg_229pp0_it0();
void thread_ap_reg_phiprechg_bpr_wordCounter_V_flag_1_reg_332pp0_it0();
void thread_ap_reg_phiprechg_bpr_wordCounter_V_new_1_reg_343pp0_it0();
void thread_ap_reg_phiprechg_tempOutput_key_V_reg_367pp0_it0();
void thread_ap_reg_phiprechg_tmp_160_reg_208pp0_it0();
void thread_ap_reg_phiprechg_tmp_EOP_V_reg_355pp0_it0();
void thread_ap_reg_phiprechg_tmp_keyValid_V_reg_297pp0_it0();
void thread_ap_reg_phiprechg_tmp_key_V_11_reg_310pp0_it0();
void thread_ap_reg_phiprechg_tmp_valueValid_V_5_reg_196pp0_it0();
void thread_ap_reg_phiprechg_tmp_valueValid_V_reg_378pp0_it0();
void thread_ap_reg_phiprechg_tmp_value_V_7_reg_321pp0_it0();
void thread_ap_reg_phiprechg_tmp_value_V_reg_391pp0_it0();
void thread_ap_reg_ppstg_or_cond_reg_748_pp0_it0();
void thread_ap_sig_bdd_105();
void thread_ap_sig_bdd_117();
void thread_ap_sig_bdd_126();
void thread_ap_sig_bdd_160();
void thread_ap_sig_bdd_183();
void thread_ap_sig_bdd_185();
void thread_ap_sig_bdd_191();
void thread_ap_sig_bdd_198();
void thread_ap_sig_bdd_23();
void thread_ap_sig_bdd_275();
void thread_ap_sig_bdd_298();
void thread_ap_sig_bdd_306();
void thread_ap_sig_bdd_314();
void thread_ap_sig_bdd_34();
void thread_ap_sig_bdd_353();
void thread_ap_sig_bdd_389();
void thread_ap_sig_bdd_409();
void thread_ap_sig_bdd_443();
void thread_ap_sig_bdd_461();
void thread_ap_sig_bdd_63();
void thread_ap_sig_bdd_77();
void thread_ap_sig_bdd_96();
void thread_ap_sig_cseq_ST_st0_fsm1_0();
void thread_ap_sig_cseq_ST_st1_fsm0_0();
void thread_ap_sig_cseq_ST_st2_fsm1_1();
void thread_bpr_keyLength_load_4_phi_fu_190_p4();
void thread_bpr_opCode_load_3_phi_fu_220_p6();
void thread_bpr_valueLength_flag_4_phi_fu_241_p16();
void thread_bpr_valueLength_new_4_phi_fu_271_p16();
void thread_bpr_valueLength_new_phi_fu_232_p4();
void thread_bpr_wordCounter_V_flag_1_phi_fu_336_p4();
void thread_bpr_wordCounter_V_new_1_phi_fu_347_p4();
void thread_grp_nbreadreq_fu_138_p3();
void thread_grp_nbreadreq_fu_146_p3();
void thread_keyBuffer_rp_V_V_read();
void thread_metadataBuffer_rp_V_V_read();
void thread_not_bpr_wordCounter_V_load_fu_662_p2();
void thread_notlhs_fu_499_p2();
void thread_notrhs_fu_505_p2();
void thread_or_cond_fu_511_p2();
void thread_p_Result_s_93_fu_545_p4();
void thread_requestParser2hashTable_V_din();
void thread_requestParser2hashTable_V_write();
void thread_storemerge2_fu_568_p3();
void thread_storemerge3_fu_463_p3();
void thread_storemerge4_fu_600_p3();
void thread_storemerge_fu_490_p3();
void thread_tempOutput_metadata_V_2_fu_702_p1();
void thread_tempOutput_metadata_V_fu_653_p4();
void thread_tmp78_fu_705_p7();
void thread_tmp_147_fu_439_p2();
void thread_tmp_148_fu_529_p2();
void thread_tmp_149_fu_445_p2();
void thread_tmp_150_fu_539_p2();
void thread_tmp_151_fu_556_p2();
void thread_tmp_152_fu_562_p2();
void thread_tmp_153_fu_582_p2();
void thread_tmp_154_fu_451_p2();
void thread_tmp_155_fu_457_p2();
void thread_tmp_156_fu_588_p2();
void thread_tmp_157_fu_594_p2();
void thread_tmp_158_fu_478_p2();
void thread_tmp_159_fu_484_p2();
void thread_tmp_160_phi_fu_211_p4();
void thread_tmp_1_fu_677_p8();
void thread_tmp_291_fu_535_p1();
void thread_tmp_EOP_V_phi_fu_359_p4();
void thread_tmp_metadata_V_11_fu_669_p3();
void thread_tmp_nbreadreq_fu_166_p3();
void thread_tmp_s_fu_523_p2();
void thread_tmp_valueValid_V_5_phi_fu_199_p4();
void thread_valueBuffer_rp_V_V_read();
void thread_ap_NS_fsm1();
void thread_ap_NS_fsm0();
};
}
using namespace ap_rtl;
#endif
|
/*
* Created on: 24. OCT. 2019
* Author: Jonathan Horsted Schougaard
*/
#define SC_INCLUDE_FX
#include "hwcore/hf/helperlib.h"
#include "hwcore/pipes/data_types.h"
#include <systemc.h>
#ifndef __tag
#warning __tag not defined!!!
#undef _sc_stream_stitching
#else
#define _sc_stream_stitching JOIN(_sc_stream_stitching, __tag)
#endif
template <int W> SC_MODULE(_sc_stream_stitching) {
typedef typename hwcore::pipes::SC_DATA_STREAM_T_trait<1 * W>::interface_T din_T;
typedef typename hwcore::pipes::SC_DATA_STREAM_T_trait<1 * W>::interface_T dout_T;
sc_in<bool> clk, reset;
sc_fifo_in<din_T> din_buf;
sc_fifo_in<din_T> din;
sc_fifo_out<dout_T> dout;
sc_fifo_in<sc_uint<16> > ctrl_depth;
sc_fifo_in<sc_uint<16> > ctrl_buf_depth;
SC_CTOR(_sc_stream_stitching) {
SC_CTHREAD(thread, clk.pos());
reset_signal_is(reset, true);
}
void thread() {
din_T tmp_in;
while (true) {
sc_uint<16> depth = ctrl_depth.read();
sc_uint<16> buf_depth = ctrl_buf_depth.read();
sc_uint<16> ptr = 0;
bool last = false;
do {
hls_pipeline(1);
if (ptr < buf_depth) {
tmp_in = din_buf.read();
tmp_in.tlast = 0;
} else {
tmp_in = din.read();
last = (tmp_in.tlast == 1);
}
dout.write(tmp_in);
ptr = (ptr + 1 >= depth ? sc_uint<16>(0) : sc_uint<16>(ptr + 1));
} while (!last);
}
}
};
namespace hwcore {
namespace pipes {
#ifndef __tag
template <int W> using sc_stream_stitching = _sc_stream_stitching<W>;
#else
namespace __tag {
template <int W> using sc_stream_stitching = _sc_stream_stitching<W>;
} // namespace __tag
#endif
} // namespace pipes
} // namespace hwcore
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.1
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _contact_discovery_HH_
#define _contact_discovery_HH_
#include "systemc.h"
#include "AESL_pkg.h"
#include "contact_discoverybkb.h"
#include "contact_discoverycud.h"
#include "contact_discovery_AXILiteS_s_axi.h"
namespace ap_rtl {
template<unsigned int C_S_AXI_AXILITES_ADDR_WIDTH = 6,
unsigned int C_S_AXI_AXILITES_DATA_WIDTH = 32>
struct contact_discovery : public sc_module {
// Port declarations 29
sc_in_clk ap_clk;
sc_in< sc_logic > ap_rst_n;
sc_in< sc_lv<8> > contacts_in_V_TDATA;
sc_in< sc_logic > contacts_in_V_TVALID;
sc_out< sc_logic > contacts_in_V_TREADY;
sc_in< sc_lv<8> > database_in_V_TDATA;
sc_in< sc_logic > database_in_V_TVALID;
sc_out< sc_logic > database_in_V_TREADY;
sc_out< sc_lv<8> > matched_out_V_TDATA;
sc_out< sc_logic > matched_out_V_TVALID;
sc_in< sc_logic > matched_out_V_TREADY;
sc_in< sc_logic > s_axi_AXILiteS_AWVALID;
sc_out< sc_logic > s_axi_AXILiteS_AWREADY;
sc_in< sc_uint<C_S_AXI_AXILITES_ADDR_WIDTH> > s_axi_AXILiteS_AWADDR;
sc_in< sc_logic > s_axi_AXILiteS_WVALID;
sc_out< sc_logic > s_axi_AXILiteS_WREADY;
sc_in< sc_uint<C_S_AXI_AXILITES_DATA_WIDTH> > s_axi_AXILiteS_WDATA;
sc_in< sc_uint<C_S_AXI_AXILITES_DATA_WIDTH/8> > s_axi_AXILiteS_WSTRB;
sc_in< sc_logic > s_axi_AXILiteS_ARVALID;
sc_out< sc_logic > s_axi_AXILiteS_ARREADY;
sc_in< sc_uint<C_S_AXI_AXILITES_ADDR_WIDTH> > s_axi_AXILiteS_ARADDR;
sc_out< sc_logic > s_axi_AXILiteS_RVALID;
sc_in< sc_logic > s_axi_AXILiteS_RREADY;
sc_out< sc_uint<C_S_AXI_AXILITES_DATA_WIDTH> > s_axi_AXILiteS_RDATA;
sc_out< sc_lv<2> > s_axi_AXILiteS_RRESP;
sc_out< sc_logic > s_axi_AXILiteS_BVALID;
sc_in< sc_logic > s_axi_AXILiteS_BREADY;
sc_out< sc_lv<2> > s_axi_AXILiteS_BRESP;
sc_out< sc_logic > interrupt;
sc_signal< sc_logic > ap_var_for_const0;
// Module declarations
contact_discovery(sc_module_name name);
SC_HAS_PROCESS(contact_discovery);
~contact_discovery();
sc_trace_file* mVcdFile;
ofstream mHdltvinHandle;
ofstream mHdltvoutHandle;
contact_discoverybkb* contacts_U;
contact_discoverycud* current_database_ite_U;
contact_discovery_AXILiteS_s_axi<C_S_AXI_AXILITES_ADDR_WIDTH,C_S_AXI_AXILITES_DATA_WIDTH>* contact_discovery_AXILiteS_s_axi_U;
sc_signal< sc_logic > ap_rst_n_inv;
sc_signal< sc_logic > ap_start;
sc_signal< sc_logic > ap_done;
sc_signal< sc_logic > ap_idle;
sc_signal< sc_lv<15> > ap_CS_fsm;
sc_signal< sc_logic > ap_CS_fsm_state1;
sc_signal< sc_logic > ap_ready;
sc_signal< sc_lv<32> > operation;
sc_signal< sc_lv<32> > operation_preg;
sc_signal< sc_logic > operation_ap_vld;
sc_signal< sc_logic > operation_ap_vld_preg;
sc_signal< sc_logic > operation_ap_vld_in_sig;
sc_signal< sc_lv<8> > matched_out_V_1_data_out;
sc_signal< sc_logic > matched_out_V_1_vld_in;
sc_signal< sc_logic > matched_out_V_1_vld_out;
sc_signal< sc_logic > matched_out_V_1_ack_in;
sc_signal< sc_logic > matched_out_V_1_ack_out;
sc_signal< sc_lv<8> > matched_out_V_1_payload_A;
sc_signal< sc_lv<8> > matched_out_V_1_payload_B;
sc_signal< sc_logic > matched_out_V_1_sel_rd;
sc_signal< sc_logic > matched_out_V_1_sel_wr;
sc_signal< sc_logic > matched_out_V_1_sel;
sc_signal< sc_logic > matched_out_V_1_load_A;
sc_signal< sc_logic > matched_out_V_1_load_B;
sc_signal< sc_lv<2> > matched_out_V_1_state;
sc_signal< sc_logic > matched_out_V_1_state_cmp_full;
sc_signal< sc_lv<32> > matched_finished_1_data_reg;
sc_signal< sc_lv<32> > matched_finished_1_data_in;
sc_signal< sc_logic > matched_finished_1_vld_reg;
sc_signal< sc_logic > matched_finished_1_vld_in;
sc_signal< sc_logic > matched_finished_1_ack_in;
sc_signal< sc_lv<32> > error_out_1_data_reg;
sc_signal< sc_lv<32> > error_out_1_data_in;
sc_signal< sc_logic > error_out_1_vld_reg;
sc_signal< sc_logic > error_out_1_vld_in;
sc_signal< sc_logic > error_out_1_ack_in;
sc_signal< sc_lv<32> > contacts_size_out_1_data_reg;
sc_signal< sc_lv<32> > contacts_size_out_1_data_in;
sc_signal< sc_logic > contacts_size_out_1_vld_reg;
sc_signal< sc_logic > contacts_size_out_1_vld_in;
sc_signal< sc_logic > contacts_size_out_1_ack_in;
sc_signal< sc_lv<32> > contacts_size;
sc_signal< sc_lv<13> > contacts_address0;
sc_signal< sc_logic > contacts_ce0;
sc_signal< sc_logic > contacts_we0;
sc_signal< sc_lv<8> > contacts_d0;
sc_signal< sc_lv<8> > contacts_q0;
sc_signal< sc_lv<6> > current_database_ite_address0;
sc_signal< sc_logic > current_database_ite_ce0;
sc_signal< sc_logic > current_database_ite_we0;
sc_signal< sc_lv<8> > current_database_ite_q0;
sc_signal< sc_logic > operation_blk_n;
sc_signal< sc_logic > ap_CS_fsm_state2;
sc_signal< sc_logic > contacts_in_V_TDATA_blk_n;
sc_signal< sc_logic > ap_CS_fsm_state15;
sc_signal< sc_logic > ap_CS_fsm_state13;
sc_signal< sc_lv<1> > exitcond9_fu_444_p2;
sc_signal< sc_logic > database_in_V_TDATA_blk_n;
sc_signal< sc_logic > ap_CS_fsm_state6;
sc_signal< sc_lv<1> > exitcond8_fu_329_p2;
sc_signal< sc_logic > matched_out_V_TDATA_blk_n;
sc_signal< sc_logic > ap_CS_fsm_state7;
sc_signal< sc_lv<1> > exitcond7_fu_346_p2;
sc_signal< sc_logic > ap_CS_fsm_state10;
sc_signal< sc_lv<32> > grp_read_fu_98_p2;
sc_signal< sc_lv<8> > i_fu_318_p2;
sc_signal< sc_logic > ap_CS_fsm_state4;
sc_signal< sc_lv<7> > i_2_fu_335_p2;
sc_signal< bool > ap_block_state6;
sc_signal< sc_lv<8> > i_5_fu_352_p2;
sc_signal< sc_lv<8> > i_5_reg_512;
sc_signal< bool > ap_block_state7_io;
sc_signal< sc_lv<13> > tmp_i_fu_362_p3;
sc_signal< sc_lv<13> > tmp_i_reg_517;
sc_signal< sc_lv<8> > cast_fu_370_p1;
sc_signal< sc_lv<7> > i_6_fu_385_p2;
sc_signal< sc_lv<7> > i_6_reg_530;
sc_signal< sc_logic > ap_CS_fsm_state8;
sc_signal< sc_lv<1> > exitcond_i_fu_379_p2;
sc_signal< sc_lv<1> > found_fu_406_p2;
sc_signal< sc_lv<1> > found_1_fu_418_p2;
sc_signal< sc_logic > ap_CS_fsm_state9;
sc_signal< sc_lv<1> > icmp_fu_434_p2;
sc_signal< sc_logic > ap_CS_fsm_state12;
sc_signal< sc_lv<1> > tmp_nbreadreq_fu_151_p3;
sc_signal< sc_lv<7> > i_4_fu_450_p2;
sc_signal< bool > ap_block_state13;
sc_signal< sc_lv<32> > tmp_9_fu_473_p2;
sc_signal< sc_lv<8> > i_3_reg_217;
sc_signal< sc_logic > ap_CS_fsm_state3;
sc_signal< sc_lv<1> > exitcond_fu_312_p2;
sc_signal< sc_lv<7> > i_1_reg_228;
sc_signal< sc_logic > ap_CS_fsm_state5;
sc_signal< sc_lv<1> > tmp_1_nbreadreq_fu_129_p3;
sc_signal< sc_lv<1> > tmp_10_reg_239;
sc_signal< sc_lv<8> > contact_index_assign_reg_251;
sc_signal< sc_lv<7> > i_i_reg_262;
sc_signal< sc_lv<1> > comp_reg_273;
sc_signal< sc_lv<7> > i1_reg_285;
sc_signal< sc_lv<64> > tmp_3_fu_324_p1;
sc_signal< sc_lv<64> > tmp_7_fu_341_p1;
sc_signal< sc_lv<64> > tmp_i_7_fu_391_p1;
sc_signal< sc_lv<64> > tmp_13_i_fu_401_p1;
sc_signal< sc_lv<64> > tmp_s_fu_468_p1;
sc_signal< sc_lv<7> > tmp_11_fu_358_p1;
sc_signal< sc_lv<13> > i_i_cast7_fu_375_p1;
sc_signal< sc_lv<13> > tmp_12_i_fu_396_p2;
sc_signal< sc_lv<1> > tmp_14_i_fu_412_p2;
sc_signal< sc_lv<25> > tmp_2_fu_424_p4;
sc_signal< sc_lv<32> > tmp_6_fu_456_p2;
sc_signal< sc_lv<32> > i1_cast_fu_440_p1;
sc_signal< sc_lv<32> > tmp_8_fu_462_p2;
sc_signal< sc_logic > ap_CS_fsm_state11;
sc_signal< bool > ap_block_state11;
sc_signal< sc_lv<15> > ap_NS_fsm;
static const sc_logic ap_const_logic_1;
static const sc_logic ap_const_logic_0;
static const sc_lv<15> ap_ST_fsm_state1;
static const sc_lv<15> ap_ST_fsm_state2;
static const sc_lv<15> ap_ST_fsm_state3;
static const sc_lv<15> ap_ST_fsm_state4;
static const sc_lv<15> ap_ST_fsm_state5;
static const sc_lv<15> ap_ST_fsm_state6;
static const sc_lv<15> ap_ST_fsm_state7;
static const sc_lv<15> ap_ST_fsm_state8;
static const sc_lv<15> ap_ST_fsm_state9;
static const sc_lv<15> ap_ST_fsm_state10;
static const sc_lv<15> ap_ST_fsm_state11;
static const sc_lv<15> ap_ST_fsm_state12;
static const sc_lv<15> ap_ST_fsm_state13;
static const sc_lv<15> ap_ST_fsm_state14;
static const sc_lv<15> ap_ST_fsm_state15;
static const sc_lv<32> ap_const_lv32_0;
static const sc_lv<1> ap_const_lv1_0;
static const sc_lv<1> ap_const_lv1_1;
static const sc_lv<2> ap_const_lv2_0;
static const sc_lv<2> ap_const_lv2_2;
static const sc_lv<2> ap_const_lv2_3;
static const sc_lv<2> ap_const_lv2_1;
static const sc_lv<32> ap_const_lv32_1;
static const sc_lv<32> ap_const_lv32_E;
static const sc_lv<32> ap_const_lv32_C;
static const sc_lv<32> ap_const_lv32_5;
static const sc_lv<32> ap_const_lv32_6;
static const sc_lv<32> ap_const_lv32_9;
static const int C_S_AXI_DATA_WIDTH;
static const sc_lv<32> ap_const_lv32_2;
static const sc_lv<32> ap_const_lv32_3;
static const bool ap_const_boolean_0;
static const sc_lv<32> ap_const_lv32_7;
static const sc_lv<32> ap_const_lv32_8;
static const sc_lv<32> ap_const_lv32_B;
static const sc_lv<8> ap_const_lv8_0;
static const sc_lv<7> ap_const_lv7_0;
static const sc_lv<32> ap_const_lv32_4;
static const sc_lv<8> ap_const_lv8_80;
static const sc_lv<8> ap_const_lv8_1;
static const sc_lv<7> ap_const_lv7_40;
static const sc_lv<7> ap_const_lv7_1;
static const sc_lv<6> ap_const_lv6_0;
static const sc_lv<32> ap_const_lv32_1F;
static const sc_lv<25> ap_const_lv25_0;
static const sc_lv<32> ap_const_lv32_A;
static const bool ap_const_boolean_1;
// Thread declarations
void thread_ap_var_for_const0();
void thread_ap_clk_no_reset_();
void thread_ap_CS_fsm_state1();
void thread_ap_CS_fsm_state10();
void thread_ap_CS_fsm_state11();
void thread_ap_CS_fsm_state12();
void thread_ap_CS_fsm_state13();
void thread_ap_CS_fsm_state15();
void thread_ap_CS_fsm_state2();
void thread_ap_CS_fsm_state3();
void thread_ap_CS_fsm_state4();
void thread_ap_CS_fsm_state5();
void thread_ap_CS_fsm_state6();
void thread_ap_CS_fsm_state7();
void thread_ap_CS_fsm_state8();
void thread_ap_CS_fsm_state9();
void thread_ap_block_state11();
void thread_ap_block_state13();
void thread_ap_block_state6();
void thread_ap_block_state7_io();
void thread_ap_done();
void thread_ap_idle();
void thread_ap_ready();
void thread_ap_rst_n_inv();
void thread_cast_fu_370_p1();
void thread_contacts_address0();
void thread_contacts_ce0();
void thread_contacts_d0();
void thread_contacts_in_V_TDATA_blk_n();
void thread_contacts_in_V_TREADY();
void thread_contacts_size_out_1_ack_in();
void thread_contacts_size_out_1_data_in();
void thread_contacts_size_out_1_vld_in();
void thread_contacts_we0();
void thread_current_database_ite_address0();
void thread_current_database_ite_ce0();
void thread_current_database_ite_we0();
void thread_database_in_V_TDATA_blk_n();
void thread_database_in_V_TREADY();
void thread_error_out_1_ack_in();
void thread_error_out_1_data_in();
void thread_error_out_1_vld_in();
void thread_exitcond7_fu_346_p2();
void thread_exitcond8_fu_329_p2();
void thread_exitcond9_fu_444_p2();
void thread_exitcond_fu_312_p2();
void thread_exitcond_i_fu_379_p2();
void thread_found_1_fu_418_p2();
void thread_found_fu_406_p2();
void thread_grp_read_fu_98_p2();
void thread_i1_cast_fu_440_p1();
void thread_i_2_fu_335_p2();
void thread_i_4_fu_450_p2();
void thread_i_5_fu_352_p2();
void thread_i_6_fu_385_p2();
void thread_i_fu_318_p2();
void thread_i_i_cast7_fu_375_p1();
void thread_icmp_fu_434_p2();
void thread_matched_finished_1_ack_in();
void thread_matched_finished_1_data_in();
void thread_matched_finished_1_vld_in();
void thread_matched_out_V_1_ack_in();
void thread_matched_out_V_1_ack_out();
void thread_matched_out_V_1_data_out();
void thread_matched_out_V_1_load_A();
void thread_matched_out_V_1_load_B();
void thread_matched_out_V_1_sel();
void thread_matched_out_V_1_state_cmp_full();
void thread_matched_out_V_1_vld_in();
void thread_matched_out_V_1_vld_out();
void thread_matched_out_V_TDATA();
void thread_matched_out_V_TDATA_blk_n();
void thread_matched_out_V_TVALID();
void thread_operation_ap_vld_in_sig();
void thread_operation_blk_n();
void thread_tmp_11_fu_358_p1();
void thread_tmp_12_i_fu_396_p2();
void thread_tmp_13_i_fu_401_p1();
void thread_tmp_14_i_fu_412_p2();
void thread_tmp_1_nbreadreq_fu_129_p3();
void thread_tmp_2_fu_424_p4();
void thread_tmp_3_fu_324_p1();
void thread_tmp_6_fu_456_p2();
void thread_tmp_7_fu_341_p1();
void thread_tmp_8_fu_462_p2();
void thread_tmp_9_fu_473_p2();
void thread_tmp_i_7_fu_391_p1();
void thread_tmp_i_fu_362_p3();
void thread_tmp_nbreadreq_fu_151_p3();
void thread_tmp_s_fu_468_p1();
void thread_ap_NS_fsm();
void thread_hdltv_gen();
};
}
using namespace ap_rtl;
#endif
|
/******************************************************************************
* *
* Copyright (C) 2022 MachineWare GmbH *
* All Rights Reserved *
* *
* This is work is licensed under the terms described in the LICENSE file *
* found in the root directory of this source tree. *
* *
******************************************************************************/
#ifndef VCML_SERIAL_UART_H
#define VCML_SERIAL_UART_H
#include "vcml/core/types.h"
#include "vcml/core/systemc.h"
#include "vcml/core/range.h"
#include "vcml/core/peripheral.h"
#include "vcml/core/model.h"
#include "vcml/protocols/tlm.h"
#include "vcml/protocols/gpio.h"
#include "vcml/protocols/serial.h"
namespace vcml {
namespace serial {
class uart : public peripheral, public serial_host
{
private:
const size_t m_rx_size;
const size_t m_tx_size;
queue<u8> m_rx_fifo;
queue<u8> m_tx_fifo;
u16 m_divisor;
void calibrate();
void update();
u8 read_rbr();
u8 read_ier();
u8 read_iir();
u8 read_lsr();
void write_thr(u8 val);
void write_ier(u8 val);
void write_lcr(u8 val);
void write_fcr(u8 val);
// serial_host
void serial_receive(const serial_target_socket& socket,
serial_payload& tx) override;
public:
enum : baud_t { DEFAULT_BAUD = SERIAL_9600BD };
// clang-format off
enum lsr_status : u8 {
LSR_DR = bit(0), // line status data ready
LSR_OE = bit(1), // line status overrun error
LSR_PE = bit(2), // line status parity error
LSR_THRE = bit(5), // line status transmitter hold empty
LSR_TEMT = bit(6), // line status transmitter empty
};
enum irq_status : u8 {
IRQ_RDA = bit(0), // enable receiver data available irq
IRQ_THRE = bit(1), // enable transmitter hold empty irq
IRQ_RLS = bit(2), // enable receiver line status irq
IRQ_MST = bit(3), // enable modem status irq
};
enum iir_status : u8 {
IIR_NOIP = bit(0), // no interrupt pending
IIR_MST = 0 << 1, // irq modem status
IIR_THRE = 1 << 1, // irq transmitter hold empty
IIR_RDA = 2 << 1, // irq received data available
IIR_RLS = 3 << 1, // irq receiver line status
};
enum lcr_status : u8 {
LCR_WL5 = 0 << 0, // word length 5 bit
LCR_WL6 = 1 << 0, // word length 6 bit
LCR_WL7 = 2 << 0, // word length 7 bit
LCR_WL8 = 3 << 0, // word length 8 bit
LCR_STP = bit(2), // stop bit control
LCR_PEN = bit(3), // parity bit enable
LCR_EPS = bit(4), // even parity select
LCR_SPB = bit(5), // stick parity bit
LCR_BCB = bit(6), // break control bit
LCR_DLAB = bit(7), // divisor latch access bit
};
enum fcr_status : u8 {
FCR_FE = bit(0), // FIFO enable
FCR_CRF = bit(1), // Clear receiver FIFO
FCR_CTF = bit(2), // Clear transmit FIFO
FCR_DMA = bit(3), // DMA mode control
FCR_IT1 = 0 << 6, // IRQ trigger threshold at 1 byte
FCR_IT4 = 1 << 6, // IRQ trigger threshold at 4 bytes
FCR_IT8 = 2 << 6, // IRQ trigger threshold at 8 bytes
FCR_IT14 = 3 << 6, // IRQ trigger threshold at 14 bytes
};
// clang-format on
reg<u8> thr; // transmit hold / receive buffer
reg<u8> ier; // interrupt enable register
reg<u8> iir; // interrupt identify register
reg<u8> lcr; // line control register
reg<u8> mcr; // modem control register
reg<u8> lsr; // line status register
reg<u8> msr; // modem status register
reg<u8> scr; // scratch register
serial_initiator_socket serial_tx;
serial_target_socket serial_rx;
gpio_initiator_socket irq;
tlm_target_socket in;
uart(const sc_module_name& name, size_t rx_fifo_sz, size_t tx_fifo_sz);
virtual ~uart();
VCML_KIND(serial::uart);
virtual void reset() override;
uart() = delete;
uart(const uart&) = delete;
};
class uart8250 : public uart
{
public:
static constexpr size_t RX_FIFO_SIZE = 1;
static constexpr size_t TX_FIFO_SIZE = 1;
uart8250(const sc_module_name& name):
uart(name, RX_FIFO_SIZE, TX_FIFO_SIZE) {};
virtual ~uart8250() = default;
VCML_KIND(serial::uart8250);
};
class uart16550 : public uart
{
public:
static constexpr size_t RX_FIFO_SIZE = 16;
static constexpr size_t TX_FIFO_SIZE = 16;
uart16550(const sc_module_name& name):
uart(name, RX_FIFO_SIZE, TX_FIFO_SIZE) {};
virtual ~uart16550() = default;
VCML_KIND(serial::uart16550);
};
} // namespace serial
} // namespace vcml
#endif
|
/*******************************************************************************
* espintr.cpp -- Copyright 2020 (c) Glenn Ramalho - RFIDo Design
*******************************************************************************
* Description:
* Implements a SystemC module for the ESP32 interrupt management.
*******************************************************************************
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
#include <systemc.h>
#include "info.h"
#include "espintr.h"
#include "soc/soc.h"
#include "esp_intr_alloc.h"
#include "Arduino.h"
void espintr::initialize() {
int i;
for (i = 0; i < ESPM_INTR_TABLE; i = i + 1) {
table_pro[i] = -1;
table_app[i] = -1;
}
for (i = 0; i < XCHAL_NUM_INTERRUPTS; i = i + 1) {
handler_pro[i].fn = NULL;
handler_pro[i].arg = NULL;
handler_app[i].fn = NULL;
handler_app[i].arg = NULL;
}
}
void espintr::catcher() {
uint32_t pro_lvl, app_lvl;
while(true) {
wait();
/* We collect all signals into one set of busses. */
pro_lvl = 0;
app_lvl = 0;
if (ledc_intr_i.read() && table_pro[ETS_LEDC_INTR_SOURCE] != -1)
pro_lvl = pro_lvl | (1<<table_pro[ETS_LEDC_INTR_SOURCE]);
if (ledc_intr_i.read() && table_app[ETS_LEDC_INTR_SOURCE] != -1)
app_lvl = app_lvl | (1<<table_app[ETS_LEDC_INTR_SOURCE]);
/* Once we are done we set the new values for raw and intr. */
raw_pro.write(pro_lvl);
intr_pro.write(mask_pro.read() & pro_lvl);
raw_app.write(app_lvl);
intr_app.write(mask_pro.read() & app_lvl);
}
}
int espintr::get_next(uint32_t edgemask, uint32_t now, uint32_t last) {
/* Any bits that are edge triggered, we take the value for last. Any that
* are not, we take the inverse of now forcing an edge trigger.
*/
uint32_t lm = last & edgemask | ~now & ~edgemask;
/* Priority NMI */
if ((now & (1<<14))>0) return 14;
/* Priority 5 */
if ((now & ~last & (1<<16))>0) return 16; /* Timer style */
if ((now & ~lm & (1<<26))>0) return 26;
if ((now & ~lm & (1<<31))>0) return 31;
/* Priority 4 */
if ((now & ~lm & (1<<24))>0) return 24;
if ((now & ~lm & (1<<25))>0) return 25;
if ((now & ~lm & (1<<28))>0) return 28;
if ((now & ~lm & (1<<30))>0) return 30;
/* Priority 3 */
if ((now & ~last & (1<<11))>0) return 11; /* Profiling */
if ((now & ~last & (1<<15))>0) return 15; /* Timer */
if ((now & ~lm & (1<<22))>0) return 22;
if ((now & ~lm & (1<<23))>0) return 23;
if ((now & ~lm & (1<<27))>0) return 27;
if ((now & ~last & (1<<29))>0) return 29; /* Software */
/* Priority 2 */
if ((now & ~lm & (1<<19))>0) return 19;
if ((now & ~lm & (1<<20))>0) return 20;
if ((now & ~lm & (1<<21))>0) return 21;
/* Priority 1 */
if ((now & ~lm & (1<<0))>0) return 0;
if ((now & ~lm & (1<<1))>0) return 1;
if ((now & ~lm & (1<<2))>0) return 2;
if ((now & ~lm & (1<<3))>0) return 3;
if ((now & ~lm & (1<<4))>0) return 4;
if ((now & ~lm & (1<<5))>0) return 5;
if ((now & ~last & (1<<6))>0) return 6; /* Timer */
if ((now & ~last & (1<<7))>0) return 7; /* Software */
if ((now & ~lm & (1<<8))>0) return 8;
if ((now & ~lm & (1<<9))>0) return 9;
if ((now & ~lm & (1<<10))>0) return 10;
if ((now & ~lm & (1<<12))>0) return 12;
if ((now & ~lm & (1<<13))>0) return 13;
if ((now & ~lm & (1<<17))>0) return 17;
if ((now & ~lm & (1<<18))>0) return 18;
return -1;
}
void espintr::driver_app() {
uint32_t last = 0;
int nextintr;
while(true) {
wait();
nextintr = get_next(edge_interrupt_app.read(), intr_app.read(), last);
last = intr_app.read();
if (nextintr >= 0 && handler_app[nextintr].fn != NULL)
(*handler_pro[nextintr].fn)(handler_pro[nextintr].arg);
}
}
void espintr::driver_pro() {
uint32_t last = 0;
int nextintr;
while(true) {
wait();
nextintr = get_next(edge_interrupt_pro.read(), intr_pro.read(), last);
last = intr_pro.read();
if (nextintr >= 0 && handler_pro[nextintr].fn != NULL)
(*handler_pro[nextintr].fn)(handler_pro[nextintr].arg);
}
}
void espintr::maskupdate() {
if (setunset) mask_pro.write(mask_pro.read() | newmask);
else mask_pro.write(mask_pro.read() & ~newmask);
if (setunset) mask_app.write(mask_app.read() | newmask);
else mask_app.write(mask_app.read() & ~newmask);
}
void espintr::trace(sc_trace_file *tf) {
sc_trace(tf, raw_app, raw_app.name());
sc_trace(tf, raw_pro, raw_pro.name());
sc_trace(tf, mask_app, mask_app.name());
sc_trace(tf, mask_pro, mask_pro.name());
sc_trace(tf, intr_app, intr_app.name());
sc_trace(tf, intr_pro, intr_pro.name());
}
|
/*****************************************************************************
Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
more contributor license agreements. See the NOTICE file distributed
with this work for additional information regarding copyright ownership.
Accellera licenses this file to you under the Apache License, Version 2.0
(the "License"); you may not use this file except in compliance with the
License. You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
implied. See the License for the specific language governing
permissions and limitations under the License.
*****************************************************************************/
/*****************************************************************************
simple_fifo.cpp -- Simple SystemC 2.0 producer/consumer example.
From "An Introduction to System Level Modeling in
SystemC 2.0". By Stuart Swan, Cadence Design Systems.
Available at www.accellera.org
Original Author: Stuart Swan, Cadence Design Systems, 2001-06-18
*****************************************************************************/
/*****************************************************************************
MODIFICATION LOG - modifiers, enter your name, affiliation, date and
changes you are making here.
Name, Affiliation, Date:
Description of Modification:
*****************************************************************************/
#include <systemc.h>
class write_if : virtual public sc_interface
{
public:
virtual void write(char) = 0;
virtual void reset() = 0;
};
class read_if : virtual public sc_interface
{
public:
virtual void read(char &) = 0;
virtual int num_available() = 0;
};
class fifo : public sc_channel, public write_if, public read_if
{
public:
fifo(sc_module_name name) : sc_channel(name), num_elements(0), first(0) {}
void write(char c) {
if (num_elements == max)
wait(read_event);
data[(first + num_elements) % max] = c;
++ num_elements;
write_event.notify();
}
void read(char &c){
if (num_elements == 0)
wait(write_event);
c = data[first];
-- num_elements;
first = (first + 1) % max;
read_event.notify();
}
void reset() { num_elements = first = 0; }
int num_available() { return num_elements;}
private:
enum e { max = 10 };
char data[max];
int num_elements, first;
sc_event write_event, read_event;
};
class producer : public sc_module
{
public:
sc_port<write_if> out;
producer(sc_module_name name) : sc_module(name)
{
SC_THREAD(main);
}
void main()
{
const char *str =
"Visit www.accellera.org and see what SystemC can do for you today!\n";
while (*str)
out->write(*str++);
}
};
class consumer : public sc_module
{
public:
sc_port<read_if> in;
consumer(sc_module_name name) : sc_module(name)
{
SC_THREAD(main);
}
void main()
{
char c;
cout << endl << endl;
while (true) {
in->read(c);
cout << c << flush;
if (in->num_available() == 1)
cout << "<1>" << flush;
if (in->num_available() == 9)
cout << "<9>" << flush;
}
}
};
class top : public sc_module
{
public:
fifo *fifo_inst;
producer *prod_inst;
consumer *cons_inst;
top(sc_module_name name) : sc_module(name)
{
fifo_inst = new fifo("Fifo1");
prod_inst = new producer("Producer1");
prod_inst->out(*fifo_inst);
cons_inst = new consumer("Consumer1");
cons_inst->in(*fifo_inst);
}
};
int sc_main (int, char *[]) {
top top1("Top1");
sc_start();
return 0;
}
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
#ifndef __ZYNQ_UTLRA_PS_E_TLM_H__
#define __ZYNQ_ULTRA_PS_E_TLM_H__
#include "systemc.h"
#include "xtlm.h"
#include "xtlm_adaptors/xaximm_xtlm2tlm.h"
#include "xtlm_adaptors/xaximm_tlm2xtlm.h"
#include "tlm_utils/simple_initiator_socket.h"
#include "tlm_utils/simple_target_socket.h"
#include <vector>
#include "genattr.h"
#include "xilinx_zynqmp.h"
/***************************************************************************************
* Global method, get registered with tlm2xtlm bridge
* This function is called when tlm2xtlm bridge convert tlm payload to xtlm payload.
*
* caller: tlm2xtlm bridge
* purpose: To get master id and other parameters out of genattr_extension
* and use master id to AxUSER PIN of xtlm payload.
*
*
***************************************************************************************/
void get_extensions_from_tlm(xtlm::aximm_payload* xtlm_pay, const tlm::tlm_generic_payload* gp)
{
if((xtlm_pay == NULL) || (gp == NULL))
return;
if((gp->get_command() == tlm::TLM_WRITE_COMMAND) && (xtlm_pay->get_awuser_size() > 0))
{
genattr_extension* ext = NULL;
gp->get_extension(ext);
if(ext == NULL)
return;
//Portion of master ID(master_id[5:0]) are transfered on AxUSER bits(refere Zynq UltraScale+ TRM page.no:414)
uint32_t val = ext->get_master_id() && 0x3F;
unsigned char* ptr = xtlm_pay->get_awuser_ptr();
unsigned int size = xtlm_pay->get_awuser_size();
*ptr = (unsigned char)val;
}
else if((gp->get_command() == tlm::TLM_READ_COMMAND) && (xtlm_pay->get_aruser_size() > 0))
{
genattr_extension* ext = NULL;
gp->get_extension(ext);
if(ext == NULL)
return;
//Portion of master ID(master_id[5:0]) are transfered on AxUSER bits(refere Zynq UltraScale+ TRM page.no:414)
uint32_t val = ext->get_master_id() && 0x3F;
unsigned char* ptr = xtlm_pay->get_aruser_ptr();
unsigned int size = xtlm_pay->get_aruser_size();
*ptr = (unsigned char)val;
}
}
/***************************************************************************************
* Global method, get registered with xtlm2tlm bridge
* This function is called when xtlm2tlm bridge convert xtlm payload to tlm payload.
*
* caller: xtlm2tlm bridge
* purpose: To create and add master id and other parameters to genattr_extension.
* Master id red from AxID PIN of xtlm payload.
*
*
***************************************************************************************/
void add_extensions_to_tlm(const xtlm::aximm_payload* xtlm_pay, tlm::tlm_generic_payload* gp)
{
if(gp == NULL)
return;
uint8_t val = 0;
if((gp->get_command() != tlm::TLM_WRITE_COMMAND) && (gp->get_command() != tlm::TLM_READ_COMMAND))
return;
//portion of master ID bits(master_id[5:0]) are derived from the AXI ID(AWID/ARID). (refere Zynq UltraScale+ TRM page.no:414,415)
//val = (*(uint8_t*)(xtlm_pay->get_axi_id())) && 0x3F;
genattr_extension* ext = new genattr_extension;
ext->set_master_id(val);
gp->set_extension(ext);
gp->set_streaming_width(gp->get_data_length());
if(gp->get_command() != tlm::TLM_WRITE_COMMAND)
{
gp->set_byte_enable_length(0);
gp->set_byte_enable_ptr(0);
}
}
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// //
// File: zynq_ultra_ps_e_tlm.h //
// //
// Description: zynq_ultra_ps_e_tlm class is a sc_module, act as intermediate layer between //
// xilinx_zynqmp qemu wrapper and Vivado generated systemc simulation ip wrapper. //
// it's basically created for supporting tlm based xilinx_zynqmp from xtlm based vivado //
// generated systemc wrapper. this wrapper is live only when SELECTED_SIM_MODEL is set //
// to tlm. it's also act as bridge between vivado wrapper and xilinx_zynqmp wrapper. //
// it fill the the gap between input/output ports of vivado generated wrapper to //
// xilinx_zynqmp wrapper signals. This wrapper is auto generated by ttcl scripts //
// based on IP configuration in vivado. //
// //
// //
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
class zynq_ultra_ps_e_tlm : public sc_core::sc_module {
public:
// Non-AXI ports are declared here
sc_core::sc_in<bool> maxihpm0_fpd_aclk;
sc_core::sc_in<bool> saxihp0_fpd_aclk;
sc_core::sc_in<sc_dt::sc_bv<1> > pl_ps_irq0;
sc_core::sc_out<bool> pl_resetn0;
sc_core::sc_out<bool> pl_clk0;
// Xtlm aximm slave sockets are delcared here. these XTLM sockets will hierachically bound with
// slave sockets defined in vivado generated wrapper.
xtlm::xtlm_aximm_target_socket* S_AXI_HP0_FPD_wr_socket;
xtlm::xtlm_aximm_target_socket* S_AXI_HP0_FPD_rd_socket;
// Xtlm aximm master socket/s is/are delcared here. these XTLM sockets will hierachically bound with
// master sockets defined in vivado generated wrapper.
xtlm::xtlm_aximm_initiator_socket* M_AXI_HPM0_FPD_wr_socket;
xtlm::xtlm_aximm_initiator_socket* M_AXI_HPM0_FPD_rd_socket;
//constructor having three paramters
// 1. module name in sc_module_name objec,
// 2. reference to map object of name and integer value pairs
// 3. reference to map object of name and string value pairs
// All the model parameters (integer and string) which are configuration parameters
// of ZynqUltraScale+ IP propogated from Vivado
zynq_ultra_ps_e_tlm(sc_core::sc_module_name name,
xsc::common::properties&): sc_module(name)//registering module name with parent
,maxihpm0_fpd_aclk("maxihpm0_fpd_aclk")
,saxihp0_fpd_aclk("saxihp0_fpd_aclk")
,pl_ps_irq0("pl_ps_irq0")
,pl_resetn0("pl_resetn0")
,pl_clk0("pl_clk0")
,pl_clk0_clk("pl_clk0_clk", sc_time(10.0,sc_core::SC_NS))//clock period in nanoseconds = 1000/freq(in MZ)
{
//creating instances of xtlm slave sockets
S_AXI_HP0_FPD_wr_socket = new xtlm::xtlm_aximm_target_socket("S_AXI_HP0_FPD_wr_socket", 128);
S_AXI_HP0_FPD_rd_socket = new xtlm::xtlm_aximm_target_socket("S_AXI_HP0_FPD_rd_socket", 128);
//creating instances of xtlm master sockets
M_AXI_HPM0_FPD_wr_socket = new xtlm::xtlm_aximm_initiator_socket("M_AXI_HPM0_FPD_wr_socket", 128);
M_AXI_HPM0_FPD_rd_socket = new xtlm::xtlm_aximm_initiator_socket("M_AXI_HPM0_FPD_rd_socket", 128);
char* tcpip_addr = getenv("COSIM_MACHINE_TCPIP_ADDRESS");
if(tcpip_addr == NULL) {
tcpip_addr = "NO_IP_ADDRESS";
//std::cerr << "ERROR: Environment Variable COSIM_MACHINE_TCPIP_ADDRESS is not specified.\n Please Specify COSIM_MACHINE_TCPIP_ADDRESS for TCP Socket Communication.\n" << std::endl;
//exit(0);
}
char* skt_name = strdup(tcpip_addr);
m_zynqmp_tlm_model = new xilinx_zynqmp("xilinx_zynqmp",skt_name);
m_xtlm2tlm = new xtlm::xaximm_xtlm2tlm*[9];
m_tlm2xtlm = new xtlm::xaximm_tlm2xtlm*[3];
for(int index = 0; index < 9; index++) {
m_xtlm2tlm[index] = NULL;
if(index < 3)
m_tlm2xtlm[index] = NULL;
}
//instantiating XTLM2TLM bridge and stiching it between
//S_AXI_HP0_FPD_wr_socket/rd_socket sockets to s_axi_hp_fpd[0] target socket of Zynqmp Qemu tlm wrapper
m_xtlm2tlm[4] = new xtlm::xaximm_xtlm2tlm("S_AXI_HP0_FPD_xtlm2tlm_bg",128);
S_AXI_HP0_FPD_wr_socket->bind(*m_xtlm2tlm[4]->wr_socket);
S_AXI_HP0_FPD_rd_socket->bind(*m_xtlm2tlm[4]->rd_socket);
m_zynqmp_tlm_model->s_axi_hp_fpd[0]->bind(m_xtlm2tlm[4]->initiator_socket);
//instantiating TLM2XTLM bridge and stiching it between
//s_axi_hpm_fpd[0] initiator socket of zynqmp Qemu tlm wrapper to M_AXI_HPM0_FPD_wr_socket/rd_socket sockets
m_tlm2xtlm[0] = new xtlm::xaximm_tlm2xtlm("M_AXI_HPM0_FPD_tlm2xtlm_bg",128);
m_tlm2xtlm[0]->wr_socket->bind(*M_AXI_HPM0_FPD_wr_socket);
m_tlm2xtlm[0]->rd_socket->bind(*M_AXI_HPM0_FPD_rd_socket);
m_tlm2xtlm[0]->target_socket.bind(*m_zynqmp_tlm_model->s_axi_hpm_fpd[0]);
m_zynqmp_tlm_model->tie_off();
SC_METHOD(pl_ps_irq0_method);
sensitive << pl_ps_irq0 ;
dont_initialize();
SC_METHOD(trigger_pl_clk0_pin);
sensitive << pl_clk0_clk;
dont_initialize();
m_xtlm2tlm[4]->registerUserExtensionHandlerCallback(add_extensions_to_tlm);
m_tlm2xtlm[0]->registerUserExtensionHandlerCallback(&get_extensions_from_tlm);
m_zynqmp_tlm_model->rst(qemu_rst);
}
~zynq_ultra_ps_e_tlm() {
//deleteing dynamically created objects
delete S_AXI_HP0_FPD_wr_socket;
delete S_AXI_HP0_FPD_rd_socket;
delete M_AXI_HPM0_FPD_wr_socket;
delete M_AXI_HPM0_FPD_rd_socket;
delete m_xtlm2tlm[4];
delete m_tlm2xtlm[0];
delete[] m_tlm2xtlm;
delete[] m_xtlm2tlm;
}
SC_HAS_PROCESS(zynq_ultra_ps_e_tlm);
private:
//zynqmp tlm wrapper provided by Edgar
//module with interfaces of standard tlm
//and input/output ports at signal level
xilinx_zynqmp* m_zynqmp_tlm_model;
// Array of Xtlm2tlm Bridges
// Converts Xtlm transactions to tlm transactions
// Bridge's Xtlm wr/rd target sockets binds with
// xtlm initiator sockets of zynq_ultra_ps_e_tlm and tlm simple initiator
// socket with xilinx_zynqmp's target socket
// Array of size 9
xtlm::xaximm_xtlm2tlm **m_xtlm2tlm;
// Array of tlm2xtlm Bridges
// Converts tlm transactions to xtlm transactions
// Bridge's tlm simple target socket binds with
// simple initiator socket of xilinx_zynqmp and xtlm
// socket with xilinx_zynqmp's simple target socket
// Array of size 3
xtlm::xaximm_tlm2xtlm **m_tlm2xtlm;
// sc_clocks for generating pl clocks
// output pins pl_clk0..3 are drived by these clocks
sc_core::sc_clock pl_clk0_clk;
//Method which is sentive to pl_clk0_clk sc_clock object
//pl_clk0 pin written based on pl_clk0_clk clock value
void trigger_pl_clk0_pin() {
pl_clk0.write(pl_clk0_clk.read());
}
void pl_ps_irq0_method() {
int irq = ((pl_ps_irq0.read().to_uint()) & 0xFF);
for(int i = 0; i <8; i++) {
if(irq & (0x1<<i)) {
m_zynqmp_tlm_model->pl2ps_irq[i].write(true);
}
else{
m_zynqmp_tlm_model->pl2ps_irq[i].write(false);
}
}
}
//pl_resetn0 output reset pin get toggle when emio bank 2's 31th signal gets toggled
//EMIO[2] bank 31th(GPIO[95] signal)acts as reset signal to the PL(refer Zynq UltraScale+ TRM, page no:761)
void pl_resetn0_trigger() {
pl_resetn0.write(m_zynqmp_tlm_model->emio[2]->out[31].read());
}
sc_signal<bool> qemu_rst;
void start_of_simulation()
{
//temporary fix to drive the enabled reset pin
pl_resetn0.write(true);
qemu_rst.write(false);
}
};
#endif
|
#ifndef POWERBUTTON_H_
#define POWERBUTTON_H_
#include "systemc.h"
#include "interface.h"
using namespace std;
SC_MODULE(PowerButton){
//port(s) connected to outside
sc_in<bool> pt_pressed;
//port(s) inside the phone
sc_out<bool> shortPress;
sc_out<bool> longPress;
//internal variables
sc_time lastTimeStamp;
sc_time interval_3S;
//constructor
SC_HAS_PROCESS(PowerButton);
PowerButton(sc_module_name name){
shortPress.initialize(false);
longPress.initialize(false);
interval_3S=sc_time(3,SC_SEC);
lastTimeStamp=sc_time_stamp()-interval_3S;
#if defined(DEBUG_POWERBUTTON) || defined(DEBUG)
print("powerButton init");
#endif
SC_METHOD(run);
sensitive<<pt_pressed;
}
void run(){
if(pt_pressed.read()==true){
lastTimeStamp=sc_time_stamp();
longPress.write(false);
shortPress.write(false);
}
else {
sc_time now=sc_time_stamp();
if(now-lastTimeStamp<interval_3S){
#if defined(DEBUG_POWERBUTTON) || defined(DEBUG)
print("short press");
#endif
shortPress.write(true);
}else{
#if defined(DEBUG_POWERBUTTON) || defined(DEBUG)
print("long press");
#endif
longPress.write(true);
}
}
}
//print given string on cout
void print(string s){
cout << "[" << sc_time_stamp() << " / " << sc_delta_count() << "](" << name() << "): " << s << endl;
}
};
#endif
|
// ================================================================
// NVDLA Open Source Project
//
// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
// NVDLA Open Hardware License; Check "LICENSE" which comes with
// this distribution for more information.
// ================================================================
// File Name: NvdlaTopDummy.h
#ifndef _NVDLATOPDUMMY_H_
#define _NVDLATOPDUMMY_H_
#define SC_INCLUDE_DYNAMIC_PROCESSES
#include <systemc.h>
#include <tlm.h>
#include "tlm_utils/multi_passthrough_initiator_socket.h"
#include "tlm_utils/multi_passthrough_target_socket.h"
#include "scsim_common.h"
SCSIM_NAMESPACE_START(cmod)
class NvdlaTopDummy : public sc_module {
public:
SC_HAS_PROCESS(NvdlaTopDummy);
NvdlaTopDummy( sc_module_name module_name );
// Target sockets
tlm_utils::multi_passthrough_target_socket<NvdlaTopDummy> m_target;
private:
void dummy_b_transport(int ID, tlm::tlm_generic_payload& bp, sc_time& delay);
};
SCSIM_NAMESPACE_END()
#endif
|
// ================================================================
// NVDLA Open Source Project
//
// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
// NVDLA Open Hardware License; Check "LICENSE" which comes with
// this distribution for more information.
// ================================================================
// File Name: NvdlaTopDummy.h
#ifndef _NVDLATOPDUMMY_H_
#define _NVDLATOPDUMMY_H_
#define SC_INCLUDE_DYNAMIC_PROCESSES
#include <systemc.h>
#include <tlm.h>
#include "tlm_utils/multi_passthrough_initiator_socket.h"
#include "tlm_utils/multi_passthrough_target_socket.h"
#include "scsim_common.h"
SCSIM_NAMESPACE_START(cmod)
class NvdlaTopDummy : public sc_module {
public:
SC_HAS_PROCESS(NvdlaTopDummy);
NvdlaTopDummy( sc_module_name module_name );
// Target sockets
tlm_utils::multi_passthrough_target_socket<NvdlaTopDummy> m_target;
private:
void dummy_b_transport(int ID, tlm::tlm_generic_payload& bp, sc_time& delay);
};
SCSIM_NAMESPACE_END()
#endif
|
#ifndef TESTBENCH_VBASE_H
#define TESTBENCH_VBASE_H
#include <systemc.h>
#include "verilated.h"
#include "verilated_vcd_sc.h"
#define verilator_trace_enable(vcd_filename, dut) \
if (waves_enabled()) \
{ \
Verilated::traceEverOn(true); \
VerilatedVcdC *v_vcd = new VerilatedVcdC; \
sc_core::sc_time delay_us; \
if (waves_delayed(delay_us)) \
dut->trace_enable (v_vcd, delay_us); \
else \
dut->trace_enable (v_vcd); \
v_vcd->open (vcd_filename); \
this->m_verilate_vcd = v_vcd; \
}
//-----------------------------------------------------------------
// Module
//-----------------------------------------------------------------
class testbench_vbase: public sc_module
{
public:
sc_in <bool> clk;
sc_in <bool> rst;
virtual void set_testcase(int tc) { }
virtual void set_delays(bool en) { }
virtual void set_iterations(int iterations) { }
virtual void set_argcv(int argc, char* argv[]) { }
virtual void process(void) { while (1) wait(); }
virtual void monitor(void) { while (1) wait(); }
SC_HAS_PROCESS(testbench_vbase);
testbench_vbase(sc_module_name name): sc_module(name)
{
SC_CTHREAD(process, clk);
SC_CTHREAD(monitor, clk);
}
virtual void add_trace(sc_trace_file * fp, std::string prefix) { }
virtual void abort(void)
{
cout << "TB: Aborted at " << sc_time_stamp() << endl;
if (m_verilate_vcd)
{
m_verilate_vcd->flush();
m_verilate_vcd->close();
m_verilate_vcd = NULL;
}
}
bool waves_enabled(void)
{
char *s = getenv("ENABLE_WAVES");
if (s && !strcmp(s, "no"))
return false;
else
return true;
}
bool waves_delayed(sc_core::sc_time &delay)
{
char *s = getenv("WAVES_DELAY_US");
if (s != NULL)
{
uint32_t us = strtoul(s, NULL, 0);
printf("WAVES: Delay start until %duS\n", us);
delay = sc_core::sc_time(us, SC_US);
return true;
}
else
return false;
}
std::string getenv_str(std::string name, std::string defval)
{
char *s = getenv(name.c_str());
if (!s || (s && !strcmp(s, "")))
return defval;
else
return std::string(s);
}
protected:
VerilatedVcdC *m_verilate_vcd;
};
#endif
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.3
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _doCorner_HH_
#define _doCorner_HH_
#include "systemc.h"
#include "AESL_pkg.h"
#include "AXIvideo2Mat.h"
#include "rgb2gray.h"
#include "FAST_t_opr.h"
#include "Dilate.h"
#include "PaintMask.h"
#include "Mat2AXIvideo.h"
#include "fifo_w8_d2_A.h"
#include "fifo_w8_d20000_A.h"
#include "start_for_rgb2grapcA.h"
#include "start_for_FAST_t_qcK.h"
#include "start_for_PaintMarcU.h"
#include "start_for_Dilate_U0.h"
#include "start_for_Mat2AXIsc4.h"
#include "doCorner_CTRL_BUS_s_axi.h"
namespace ap_rtl {
template<unsigned int C_S_AXI_CTRL_BUS_ADDR_WIDTH = 4,
unsigned int C_S_AXI_CTRL_BUS_DATA_WIDTH = 32>
struct doCorner : public sc_module {
// Port declarations 38
sc_in< sc_logic > s_axi_CTRL_BUS_AWVALID;
sc_out< sc_logic > s_axi_CTRL_BUS_AWREADY;
sc_in< sc_uint<C_S_AXI_CTRL_BUS_ADDR_WIDTH> > s_axi_CTRL_BUS_AWADDR;
sc_in< sc_logic > s_axi_CTRL_BUS_WVALID;
sc_out< sc_logic > s_axi_CTRL_BUS_WREADY;
sc_in< sc_uint<C_S_AXI_CTRL_BUS_DATA_WIDTH> > s_axi_CTRL_BUS_WDATA;
sc_in< sc_uint<C_S_AXI_CTRL_BUS_DATA_WIDTH/8> > s_axi_CTRL_BUS_WSTRB;
sc_in< sc_logic > s_axi_CTRL_BUS_ARVALID;
sc_out< sc_logic > s_axi_CTRL_BUS_ARREADY;
sc_in< sc_uint<C_S_AXI_CTRL_BUS_ADDR_WIDTH> > s_axi_CTRL_BUS_ARADDR;
sc_out< sc_logic > s_axi_CTRL_BUS_RVALID;
sc_in< sc_logic > s_axi_CTRL_BUS_RREADY;
sc_out< sc_uint<C_S_AXI_CTRL_BUS_DATA_WIDTH> > s_axi_CTRL_BUS_RDATA;
sc_out< sc_lv<2> > s_axi_CTRL_BUS_RRESP;
sc_out< sc_logic > s_axi_CTRL_BUS_BVALID;
sc_in< sc_logic > s_axi_CTRL_BUS_BREADY;
sc_out< sc_lv<2> > s_axi_CTRL_BUS_BRESP;
sc_in_clk ap_clk;
sc_in< sc_logic > ap_rst_n;
sc_out< sc_logic > interrupt;
sc_in< sc_lv<24> > inStream_TDATA;
sc_in< sc_lv<3> > inStream_TKEEP;
sc_in< sc_lv<3> > inStream_TSTRB;
sc_in< sc_lv<1> > inStream_TUSER;
sc_in< sc_lv<1> > inStream_TLAST;
sc_in< sc_lv<1> > inStream_TID;
sc_in< sc_lv<1> > inStream_TDEST;
sc_out< sc_lv<24> > outStream_TDATA;
sc_out< sc_lv<3> > outStream_TKEEP;
sc_out< sc_lv<3> > outStream_TSTRB;
sc_out< sc_lv<1> > outStream_TUSER;
sc_out< sc_lv<1> > outStream_TLAST;
sc_out< sc_lv<1> > outStream_TID;
sc_out< sc_lv<1> > outStream_TDEST;
sc_in< sc_logic > inStream_TVALID;
sc_out< sc_logic > inStream_TREADY;
sc_out< sc_logic > outStream_TVALID;
sc_in< sc_logic > outStream_TREADY;
sc_signal< sc_logic > ap_var_for_const0;
// Module declarations
doCorner(sc_module_name name);
SC_HAS_PROCESS(doCorner);
~doCorner();
sc_trace_file* mVcdFile;
ofstream mHdltvinHandle;
ofstream mHdltvoutHandle;
doCorner_CTRL_BUS_s_axi<C_S_AXI_CTRL_BUS_ADDR_WIDTH,C_S_AXI_CTRL_BUS_DATA_WIDTH>* doCorner_CTRL_BUS_s_axi_U;
AXIvideo2Mat* AXIvideo2Mat_U0;
rgb2gray* rgb2gray_U0;
FAST_t_opr* FAST_t_opr_U0;
Dilate* Dilate_U0;
PaintMask* PaintMask_U0;
Mat2AXIvideo* Mat2AXIvideo_U0;
fifo_w8_d2_A* img_0_data_stream_0_U;
fifo_w8_d2_A* img_0_data_stream_1_U;
fifo_w8_d2_A* img_0_data_stream_2_U;
fifo_w8_d20000_A* img_1_data_stream_0_U;
fifo_w8_d20000_A* img_1_data_stream_1_U;
fifo_w8_d20000_A* img_1_data_stream_2_U;
fifo_w8_d2_A* img_2_data_stream_0_U;
fifo_w8_d2_A* mask_data_stream_0_s_U;
fifo_w8_d2_A* dmask_data_stream_0_U;
fifo_w8_d2_A* img_3_data_stream_0_U;
fifo_w8_d2_A* img_3_data_stream_1_U;
fifo_w8_d2_A* img_3_data_stream_2_U;
start_for_rgb2grapcA* start_for_rgb2grapcA_U;
start_for_FAST_t_qcK* start_for_FAST_t_qcK_U;
start_for_PaintMarcU* start_for_PaintMarcU_U;
start_for_Dilate_U0* start_for_Dilate_U0_U;
start_for_Mat2AXIsc4* start_for_Mat2AXIsc4_U;
sc_signal< sc_logic > ap_rst_n_inv;
sc_signal< sc_logic > ap_start;
sc_signal< sc_logic > ap_ready;
sc_signal< sc_logic > ap_done;
sc_signal< sc_logic > ap_idle;
sc_signal< sc_logic > AXIvideo2Mat_U0_ap_start;
sc_signal< sc_logic > AXIvideo2Mat_U0_ap_done;
sc_signal< sc_logic > AXIvideo2Mat_U0_ap_continue;
sc_signal< sc_logic > AXIvideo2Mat_U0_ap_idle;
sc_signal< sc_logic > AXIvideo2Mat_U0_ap_ready;
sc_signal< sc_logic > AXIvideo2Mat_U0_start_out;
sc_signal< sc_logic > AXIvideo2Mat_U0_start_write;
sc_signal< sc_logic > AXIvideo2Mat_U0_inStream_TREADY;
sc_signal< sc_lv<8> > AXIvideo2Mat_U0_img_data_stream_0_V_din;
sc_signal< sc_logic > AXIvideo2Mat_U0_img_data_stream_0_V_write;
sc_signal< sc_lv<8> > AXIvideo2Mat_U0_img_data_stream_1_V_din;
sc_signal< sc_logic > AXIvideo2Mat_U0_img_data_stream_1_V_write;
sc_signal< sc_lv<8> > AXIvideo2Mat_U0_img_data_stream_2_V_din;
sc_signal< sc_logic > AXIvideo2Mat_U0_img_data_stream_2_V_write;
sc_signal< sc_logic > rgb2gray_U0_ap_start;
sc_signal< sc_logic > rgb2gray_U0_start_full_n;
sc_signal< sc_logic > rgb2gray_U0_ap_done;
sc_signal< sc_logic > rgb2gray_U0_ap_continue;
sc_signal< sc_logic > rgb2gray_U0_ap_idle;
sc_signal< sc_logic > rgb2gray_U0_ap_ready;
sc_signal< sc_logic > rgb2gray_U0_start_out;
sc_signal< sc_logic > rgb2gray_U0_start_write;
sc_signal< sc_logic > rgb2gray_U0_imgIn_data_stream_0_V_read;
sc_signal< sc_logic > rgb2gray_U0_imgIn_data_stream_1_V_read;
sc_signal< sc_logic > rgb2gray_U0_imgIn_data_stream_2_V_read;
sc_signal< sc_lv<8> > rgb2gray_U0_imgOut_3C_data_stream_0_V_din;
sc_signal< sc_logic > rgb2gray_U0_imgOut_3C_data_stream_0_V_write;
sc_signal< sc_lv<8> > rgb2gray_U0_imgOut_3C_data_stream_1_V_din;
sc_signal< sc_logic > rgb2gray_U0_imgOut_3C_data_stream_1_V_write;
sc_signal< sc_lv<8> > rgb2gray_U0_imgOut_3C_data_stream_2_V_din;
sc_signal< sc_logic > rgb2gray_U0_imgOut_3C_data_stream_2_V_write;
sc_signal< sc_lv<8> > rgb2gray_U0_imgOut_1C_data_stream_V_din;
sc_signal< sc_logic > rgb2gray_U0_imgOut_1C_data_stream_V_write;
sc_signal< sc_logic > FAST_t_opr_U0_ap_start;
sc_signal< sc_logic > FAST_t_opr_U0_ap_done;
sc_signal< sc_logic > FAST_t_opr_U0_ap_continue;
sc_signal< sc_logic > FAST_t_opr_U0_ap_idle;
sc_signal< sc_logic > FAST_t_opr_U0_ap_ready;
sc_signal< sc_logic > FAST_t_opr_U0_start_out;
sc_signal< sc_logic > FAST_t_opr_U0_start_write;
sc_signal< sc_logic > FAST_t_opr_U0_p_src_data_stream_V_read;
sc_signal< sc_lv<8> > FAST_t_opr_U0_p_mask_data_stream_V_din;
sc_signal< sc_logic > FAST_t_opr_U0_p_mask_data_stream_V_write;
sc_signal< sc_logic > Dilate_U0_ap_start;
sc_signal< sc_logic > Dilate_U0_ap_done;
sc_signal< sc_logic > Dilate_U0_ap_continue;
sc_signal< sc_logic > Dilate_U0_ap_idle;
sc_signal< sc_logic > Dilate_U0_ap_ready;
sc_signal< sc_logic > Dilate_U0_p_src_data_stream_V_read;
sc_signal< sc_lv<8> > Dilate_U0_p_dst_data_stream_V_din;
sc_signal< sc_logic > Dilate_U0_p_dst_data_stream_V_write;
sc_signal< sc_logic > PaintMask_U0_ap_start;
sc_signal< sc_logic > PaintMask_U0_ap_done;
sc_signal< sc_logic > PaintMask_U0_ap_continue;
sc_signal< sc_logic > PaintMask_U0_ap_idle;
sc_signal< sc_logic > PaintMask_U0_ap_ready;
sc_signal< sc_logic > PaintMask_U0_start_out;
sc_signal< sc_logic > PaintMask_U0_start_write;
sc_signal< sc_logic > PaintMask_U0_p_src_data_stream_0_V_read;
sc_signal< sc_logic > PaintMask_U0_p_src_data_stream_1_V_read;
sc_signal< sc_logic > PaintMask_U0_p_src_data_stream_2_V_read;
sc_signal< sc_logic > PaintMask_U0_p_mask_data_stream_V_read;
sc_signal< sc_lv<8> > PaintMask_U0_p_dst_data_stream_0_V_din;
sc_signal< sc_logic > PaintMask_U0_p_dst_data_stream_0_V_write;
sc_signal< sc_lv<8> > PaintMask_U0_p_dst_data_stream_1_V_din;
sc_signal< sc_logic > PaintMask_U0_p_dst_data_stream_1_V_write;
sc_signal< sc_lv<8> > PaintMask_U0_p_dst_data_stream_2_V_din;
sc_signal< sc_logic > PaintMask_U0_p_dst_data_stream_2_V_write;
sc_signal< sc_logic > Mat2AXIvideo_U0_ap_start;
sc_signal< sc_logic > Mat2AXIvideo_U0_ap_done;
sc_signal< sc_logic > Mat2AXIvideo_U0_ap_continue;
sc_signal< sc_logic > Mat2AXIvideo_U0_ap_idle;
sc_signal< sc_logic > Mat2AXIvideo_U0_ap_ready;
sc_signal< sc_logic > Mat2AXIvideo_U0_img_data_stream_0_V_read;
sc_signal< sc_logic > Mat2AXIvideo_U0_img_data_stream_1_V_read;
sc_signal< sc_logic > Mat2AXIvideo_U0_img_data_stream_2_V_read;
sc_signal< sc_lv<24> > Mat2AXIvideo_U0_outStream_TDATA;
sc_signal< sc_logic > Mat2AXIvideo_U0_outStream_TVALID;
sc_signal< sc_lv<3> > Mat2AXIvideo_U0_outStream_TKEEP;
sc_signal< sc_lv<3> > Mat2AXIvideo_U0_outStream_TSTRB;
sc_signal< sc_lv<1> > Mat2AXIvideo_U0_outStream_TUSER;
sc_signal< sc_lv<1> > Mat2AXIvideo_U0_outStream_TLAST;
sc_signal< sc_lv<1> > Mat2AXIvideo_U0_outStream_TID;
sc_signal< sc_lv<1> > Mat2AXIvideo_U0_outStream_TDEST;
sc_signal< sc_logic > ap_sync_continue;
sc_signal< sc_logic > img_0_data_stream_0_full_n;
sc_signal< sc_lv<8> > img_0_data_stream_0_dout;
sc_signal< sc_logic > img_0_data_stream_0_empty_n;
sc_signal< sc_logic > img_0_data_stream_1_full_n;
sc_signal< sc_lv<8> > img_0_data_stream_1_dout;
sc_signal< sc_logic > img_0_data_stream_1_empty_n;
sc_signal< sc_logic > img_0_data_stream_2_full_n;
sc_signal< sc_lv<8> > img_0_data_stream_2_dout;
sc_signal< sc_logic > img_0_data_stream_2_empty_n;
sc_signal< sc_logic > img_1_data_stream_0_full_n;
sc_signal< sc_lv<8> > img_1_data_stream_0_dout;
sc_signal< sc_logic > img_1_data_stream_0_empty_n;
sc_signal< sc_logic > img_1_data_stream_1_full_n;
sc_signal< sc_lv<8> > img_1_data_stream_1_dout;
sc_signal< sc_logic > img_1_data_stream_1_empty_n;
sc_signal< sc_logic > img_1_data_stream_2_full_n;
sc_signal< sc_lv<8> > img_1_data_stream_2_dout;
sc_signal< sc_logic > img_1_data_stream_2_empty_n;
sc_signal< sc_logic > img_2_data_stream_0_full_n;
sc_signal< sc_lv<8> > img_2_data_stream_0_dout;
sc_signal< sc_logic > img_2_data_stream_0_empty_n;
sc_signal< sc_logic > mask_data_stream_0_s_full_n;
sc_signal< sc_lv<8> > mask_data_stream_0_s_dout;
sc_signal< sc_logic > mask_data_stream_0_s_empty_n;
sc_signal< sc_logic > dmask_data_stream_0_full_n;
sc_signal< sc_lv<8> > dmask_data_stream_0_dout;
sc_signal< sc_logic > dmask_data_stream_0_empty_n;
sc_signal< sc_logic > img_3_data_stream_0_full_n;
sc_signal< sc_lv<8> > img_3_data_stream_0_dout;
sc_signal< sc_logic > img_3_data_stream_0_empty_n;
sc_signal< sc_logic > img_3_data_stream_1_full_n;
sc_signal< sc_lv<8> > img_3_data_stream_1_dout;
sc_signal< sc_logic > img_3_data_stream_1_empty_n;
sc_signal< sc_logic > img_3_data_stream_2_full_n;
sc_signal< sc_lv<8> > img_3_data_stream_2_dout;
sc_signal< sc_logic > img_3_data_stream_2_empty_n;
sc_signal< sc_logic > ap_sync_done;
sc_signal< sc_logic > ap_sync_ready;
sc_signal< sc_lv<1> > start_for_rgb2gray_U0_din;
sc_signal< sc_logic > start_for_rgb2gray_U0_full_n;
sc_signal< sc_lv<1> > start_for_rgb2gray_U0_dout;
sc_signal< sc_logic > start_for_rgb2gray_U0_empty_n;
sc_signal< sc_lv<1> > start_for_FAST_t_opr_U0_din;
sc_signal< sc_logic > start_for_FAST_t_opr_U0_full_n;
sc_signal< sc_lv<1> > start_for_FAST_t_opr_U0_dout;
sc_signal< sc_logic > start_for_FAST_t_opr_U0_empty_n;
sc_signal< sc_lv<1> > start_for_PaintMask_U0_din;
sc_signal< sc_logic > start_for_PaintMask_U0_full_n;
sc_signal< sc_lv<1> > start_for_PaintMask_U0_dout;
sc_signal< sc_logic > start_for_PaintMask_U0_empty_n;
sc_signal< sc_lv<1> > start_for_Dilate_U0_din;
sc_signal< sc_logic > start_for_Dilate_U0_full_n;
sc_signal< sc_lv<1> > start_for_Dilate_U0_dout;
sc_signal< sc_logic > start_for_Dilate_U0_empty_n;
sc_signal< sc_logic > Dilate_U0_start_full_n;
sc_signal< sc_logic > Dilate_U0_start_write;
sc_signal< sc_lv<1> > start_for_Mat2AXIvideo_U0_din;
sc_signal< sc_logic > start_for_Mat2AXIvideo_U0_full_n;
sc_signal< sc_lv<1> > start_for_Mat2AXIvideo_U0_dout;
sc_signal< sc_logic > start_for_Mat2AXIvideo_U0_empty_n;
sc_signal< sc_logic > Mat2AXIvideo_U0_start_full_n;
sc_signal< sc_logic > Mat2AXIvideo_U0_start_write;
static const int C_S_AXI_DATA_WIDTH;
static const int C_S_AXI_WSTRB_WIDTH;
static const int C_S_AXI_ADDR_WIDTH;
static const sc_logic ap_const_logic_1;
static const sc_lv<24> ap_const_lv24_0;
static const sc_lv<3> ap_const_lv3_0;
static const sc_lv<1> ap_const_lv1_0;
static const sc_logic ap_const_logic_0;
// Thread declarations
void thread_ap_var_for_const0();
void thread_AXIvideo2Mat_U0_ap_continue();
void thread_AXIvideo2Mat_U0_ap_start();
void thread_Dilate_U0_ap_continue();
void thread_Dilate_U0_ap_start();
void thread_Dilate_U0_start_full_n();
void thread_Dilate_U0_start_write();
void thread_FAST_t_opr_U0_ap_continue();
void thread_FAST_t_opr_U0_ap_start();
void thread_Mat2AXIvideo_U0_ap_continue();
void thread_Mat2AXIvideo_U0_ap_start();
void thread_Mat2AXIvideo_U0_start_full_n();
void thread_Mat2AXIvideo_U0_start_write();
void thread_PaintMask_U0_ap_continue();
void thread_PaintMask_U0_ap_start();
void thread_ap_done();
void thread_ap_idle();
void thread_ap_ready();
void thread_ap_rst_n_inv();
void thread_ap_sync_continue();
void thread_ap_sync_done();
void thread_ap_sync_ready();
void thread_inStream_TREADY();
void thread_outStream_TDATA();
void thread_outStream_TDEST();
void thread_outStream_TID();
void thread_outStream_TKEEP();
void thread_outStream_TLAST();
void thread_outStream_TSTRB();
void thread_outStream_TUSER();
void thread_outStream_TVALID();
void thread_rgb2gray_U0_ap_continue();
void thread_rgb2gray_U0_ap_start();
void thread_rgb2gray_U0_start_full_n();
void thread_start_for_Dilate_U0_din();
void thread_start_for_FAST_t_opr_U0_din();
void thread_start_for_Mat2AXIvideo_U0_din();
void thread_start_for_PaintMask_U0_din();
void thread_start_for_rgb2gray_U0_din();
void thread_hdltv_gen();
};
}
using namespace ap_rtl;
#endif
|
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD and is protected under U.S. and international copyright
// and other intellectual property laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// AMD, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) AMD shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or AMD had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// AMD products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of AMD products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
#ifndef _icyradio_GND_13_0_H_
#define _icyradio_GND_13_0_H_
#include "xlconstant_v1_1_8.h"
#include "systemc.h"
class icyradio_GND_13_0 : public sc_module {
public:
xlconstant_v1_1_8<32,0> mod;
sc_out< sc_bv<32> > dout;
icyradio_GND_13_0 (sc_core::sc_module_name name);
};
#endif
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
// Version: 2019.2
// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _Block_myproject_axi_exit35_proc_HH_
#define _Block_myproject_axi_exit35_proc_HH_
#include "systemc.h"
#include "AESL_pkg.h"
namespace ap_rtl {
struct Block_myproject_axi_exit35_proc : public sc_module {
// Port declarations 57
sc_in_clk ap_clk;
sc_in< sc_logic > ap_rst;
sc_in< sc_logic > ap_start;
sc_out< sc_logic > ap_done;
sc_in< sc_logic > ap_continue;
sc_out< sc_logic > ap_idle;
sc_out< sc_logic > ap_ready;
sc_in< sc_lv<16> > out_local_V_data_0_V_dout;
sc_in< sc_logic > out_local_V_data_0_V_empty_n;
sc_out< sc_logic > out_local_V_data_0_V_read;
sc_in< sc_lv<16> > out_local_V_data_1_V_dout;
sc_in< sc_logic > out_local_V_data_1_V_empty_n;
sc_out< sc_logic > out_local_V_data_1_V_read;
sc_in< sc_lv<16> > out_local_V_data_2_V_dout;
sc_in< sc_logic > out_local_V_data_2_V_empty_n;
sc_out< sc_logic > out_local_V_data_2_V_read;
sc_in< sc_lv<16> > out_local_V_data_3_V_dout;
sc_in< sc_logic > out_local_V_data_3_V_empty_n;
sc_out< sc_logic > out_local_V_data_3_V_read;
sc_in< sc_lv<16> > out_local_V_data_4_V_dout;
sc_in< sc_logic > out_local_V_data_4_V_empty_n;
sc_out< sc_logic > out_local_V_data_4_V_read;
sc_in< sc_lv<16> > out_local_V_data_5_V_dout;
sc_in< sc_logic > out_local_V_data_5_V_empty_n;
sc_out< sc_logic > out_local_V_data_5_V_read;
sc_in< sc_lv<16> > out_local_V_data_6_V_dout;
sc_in< sc_logic > out_local_V_data_6_V_empty_n;
sc_out< sc_logic > out_local_V_data_6_V_read;
sc_in< sc_lv<16> > out_local_V_data_7_V_dout;
sc_in< sc_logic > out_local_V_data_7_V_empty_n;
sc_out< sc_logic > out_local_V_data_7_V_read;
sc_in< sc_lv<16> > out_local_V_data_8_V_dout;
sc_in< sc_logic > out_local_V_data_8_V_empty_n;
sc_out< sc_logic > out_local_V_data_8_V_read;
sc_in< sc_lv<16> > out_local_V_data_9_V_dout;
sc_in< sc_logic > out_local_V_data_9_V_empty_n;
sc_out< sc_logic > out_local_V_data_9_V_read;
sc_out< sc_lv<16> > tmp_data_V_0;
sc_out< sc_logic > tmp_data_V_0_ap_vld;
sc_out< sc_lv<16> > tmp_data_V_1;
sc_out< sc_logic > tmp_data_V_1_ap_vld;
sc_out< sc_lv<16> > tmp_data_V_2;
sc_out< sc_logic > tmp_data_V_2_ap_vld;
sc_out< sc_lv<16> > tmp_data_V_3;
sc_out< sc_logic > tmp_data_V_3_ap_vld;
sc_out< sc_lv<16> > tmp_data_V_4;
sc_out< sc_logic > tmp_data_V_4_ap_vld;
sc_out< sc_lv<16> > tmp_data_V_5;
sc_out< sc_logic > tmp_data_V_5_ap_vld;
sc_out< sc_lv<16> > tmp_data_V_6;
sc_out< sc_logic > tmp_data_V_6_ap_vld;
sc_out< sc_lv<16> > tmp_data_V_7;
sc_out< sc_logic > tmp_data_V_7_ap_vld;
sc_out< sc_lv<16> > tmp_data_V_8;
sc_out< sc_logic > tmp_data_V_8_ap_vld;
sc_out< sc_lv<16> > tmp_data_V_9;
sc_out< sc_logic > tmp_data_V_9_ap_vld;
// Module declarations
Block_myproject_axi_exit35_proc(sc_module_name name);
SC_HAS_PROCESS(Block_myproject_axi_exit35_proc);
~Block_myproject_axi_exit35_proc();
sc_trace_file* mVcdFile;
sc_signal< sc_logic > ap_done_reg;
sc_signal< sc_lv<1> > ap_CS_fsm;
sc_signal< sc_logic > ap_CS_fsm_state1;
sc_signal< sc_logic > out_local_V_data_0_V_blk_n;
sc_signal< sc_logic > out_local_V_data_1_V_blk_n;
sc_signal< sc_logic > out_local_V_data_2_V_blk_n;
sc_signal< sc_logic > out_local_V_data_3_V_blk_n;
sc_signal< sc_logic > out_local_V_data_4_V_blk_n;
sc_signal< sc_logic > out_local_V_data_5_V_blk_n;
sc_signal< sc_logic > out_local_V_data_6_V_blk_n;
sc_signal< sc_logic > out_local_V_data_7_V_blk_n;
sc_signal< sc_logic > out_local_V_data_8_V_blk_n;
sc_signal< sc_logic > out_local_V_data_9_V_blk_n;
sc_signal< sc_logic > io_acc_block_signal_op12;
sc_signal< bool > ap_block_state1;
sc_signal< sc_lv<16> > tmp_data_V_0_preg;
sc_signal< sc_lv<16> > tmp_data_V_1_preg;
sc_signal< sc_lv<16> > tmp_data_V_2_preg;
sc_signal< sc_lv<16> > tmp_data_V_3_preg;
sc_signal< sc_lv<16> > tmp_data_V_4_preg;
sc_signal< sc_lv<16> > tmp_data_V_5_preg;
sc_signal< sc_lv<16> > tmp_data_V_6_preg;
sc_signal< sc_lv<16> > tmp_data_V_7_preg;
sc_signal< sc_lv<16> > tmp_data_V_8_preg;
sc_signal< sc_lv<16> > tmp_data_V_9_preg;
sc_signal< sc_lv<1> > ap_NS_fsm;
static const sc_logic ap_const_logic_1;
static const sc_logic ap_const_logic_0;
static const sc_lv<1> ap_ST_fsm_state1;
static const sc_lv<32> ap_const_lv32_0;
static const sc_lv<16> ap_const_lv16_0;
static const bool ap_const_boolean_1;
// Thread declarations
void thread_ap_clk_no_reset_();
void thread_ap_CS_fsm_state1();
void thread_ap_block_state1();
void thread_ap_done();
void thread_ap_idle();
void thread_ap_ready();
void thread_io_acc_block_signal_op12();
void thread_out_local_V_data_0_V_blk_n();
void thread_out_local_V_data_0_V_read();
void thread_out_local_V_data_1_V_blk_n();
void thread_out_local_V_data_1_V_read();
void thread_out_local_V_data_2_V_blk_n();
void thread_out_local_V_data_2_V_read();
void thread_out_local_V_data_3_V_blk_n();
void thread_out_local_V_data_3_V_read();
void thread_out_local_V_data_4_V_blk_n();
void thread_out_local_V_data_4_V_read();
void thread_out_local_V_data_5_V_blk_n();
void thread_out_local_V_data_5_V_read();
void thread_out_local_V_data_6_V_blk_n();
void thread_out_local_V_data_6_V_read();
void thread_out_local_V_data_7_V_blk_n();
void thread_out_local_V_data_7_V_read();
void thread_out_local_V_data_8_V_blk_n();
void thread_out_local_V_data_8_V_read();
void thread_out_local_V_data_9_V_blk_n();
void thread_out_local_V_data_9_V_read();
void thread_tmp_data_V_0();
void thread_tmp_data_V_0_ap_vld();
void thread_tmp_data_V_1();
void thread_tmp_data_V_1_ap_vld();
void thread_tmp_data_V_2();
void thread_tmp_data_V_2_ap_vld();
void thread_tmp_data_V_3();
void thread_tmp_data_V_3_ap_vld();
void thread_tmp_data_V_4();
void thread_tmp_data_V_4_ap_vld();
void thread_tmp_data_V_5();
void thread_tmp_data_V_5_ap_vld();
void thread_tmp_data_V_6();
void thread_tmp_data_V_6_ap_vld();
void thread_tmp_data_V_7();
void thread_tmp_data_V_7_ap_vld();
void thread_tmp_data_V_8();
void thread_tmp_data_V_8_ap_vld();
void thread_tmp_data_V_9();
void thread_tmp_data_V_9_ap_vld();
void thread_ap_NS_fsm();
};
}
using namespace ap_rtl;
#endif
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
// Version: 2019.2
// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _Block_myproject_axi_exit35_proc_HH_
#define _Block_myproject_axi_exit35_proc_HH_
#include "systemc.h"
#include "AESL_pkg.h"
namespace ap_rtl {
struct Block_myproject_axi_exit35_proc : public sc_module {
// Port declarations 57
sc_in_clk ap_clk;
sc_in< sc_logic > ap_rst;
sc_in< sc_logic > ap_start;
sc_out< sc_logic > ap_done;
sc_in< sc_logic > ap_continue;
sc_out< sc_logic > ap_idle;
sc_out< sc_logic > ap_ready;
sc_in< sc_lv<16> > out_local_V_data_0_V_dout;
sc_in< sc_logic > out_local_V_data_0_V_empty_n;
sc_out< sc_logic > out_local_V_data_0_V_read;
sc_in< sc_lv<16> > out_local_V_data_1_V_dout;
sc_in< sc_logic > out_local_V_data_1_V_empty_n;
sc_out< sc_logic > out_local_V_data_1_V_read;
sc_in< sc_lv<16> > out_local_V_data_2_V_dout;
sc_in< sc_logic > out_local_V_data_2_V_empty_n;
sc_out< sc_logic > out_local_V_data_2_V_read;
sc_in< sc_lv<16> > out_local_V_data_3_V_dout;
sc_in< sc_logic > out_local_V_data_3_V_empty_n;
sc_out< sc_logic > out_local_V_data_3_V_read;
sc_in< sc_lv<16> > out_local_V_data_4_V_dout;
sc_in< sc_logic > out_local_V_data_4_V_empty_n;
sc_out< sc_logic > out_local_V_data_4_V_read;
sc_in< sc_lv<16> > out_local_V_data_5_V_dout;
sc_in< sc_logic > out_local_V_data_5_V_empty_n;
sc_out< sc_logic > out_local_V_data_5_V_read;
sc_in< sc_lv<16> > out_local_V_data_6_V_dout;
sc_in< sc_logic > out_local_V_data_6_V_empty_n;
sc_out< sc_logic > out_local_V_data_6_V_read;
sc_in< sc_lv<16> > out_local_V_data_7_V_dout;
sc_in< sc_logic > out_local_V_data_7_V_empty_n;
sc_out< sc_logic > out_local_V_data_7_V_read;
sc_in< sc_lv<16> > out_local_V_data_8_V_dout;
sc_in< sc_logic > out_local_V_data_8_V_empty_n;
sc_out< sc_logic > out_local_V_data_8_V_read;
sc_in< sc_lv<16> > out_local_V_data_9_V_dout;
sc_in< sc_logic > out_local_V_data_9_V_empty_n;
sc_out< sc_logic > out_local_V_data_9_V_read;
sc_out< sc_lv<16> > tmp_data_V_0;
sc_out< sc_logic > tmp_data_V_0_ap_vld;
sc_out< sc_lv<16> > tmp_data_V_1;
sc_out< sc_logic > tmp_data_V_1_ap_vld;
sc_out< sc_lv<16> > tmp_data_V_2;
sc_out< sc_logic > tmp_data_V_2_ap_vld;
sc_out< sc_lv<16> > tmp_data_V_3;
sc_out< sc_logic > tmp_data_V_3_ap_vld;
sc_out< sc_lv<16> > tmp_data_V_4;
sc_out< sc_logic > tmp_data_V_4_ap_vld;
sc_out< sc_lv<16> > tmp_data_V_5;
sc_out< sc_logic > tmp_data_V_5_ap_vld;
sc_out< sc_lv<16> > tmp_data_V_6;
sc_out< sc_logic > tmp_data_V_6_ap_vld;
sc_out< sc_lv<16> > tmp_data_V_7;
sc_out< sc_logic > tmp_data_V_7_ap_vld;
sc_out< sc_lv<16> > tmp_data_V_8;
sc_out< sc_logic > tmp_data_V_8_ap_vld;
sc_out< sc_lv<16> > tmp_data_V_9;
sc_out< sc_logic > tmp_data_V_9_ap_vld;
// Module declarations
Block_myproject_axi_exit35_proc(sc_module_name name);
SC_HAS_PROCESS(Block_myproject_axi_exit35_proc);
~Block_myproject_axi_exit35_proc();
sc_trace_file* mVcdFile;
sc_signal< sc_logic > ap_done_reg;
sc_signal< sc_lv<1> > ap_CS_fsm;
sc_signal< sc_logic > ap_CS_fsm_state1;
sc_signal< sc_logic > out_local_V_data_0_V_blk_n;
sc_signal< sc_logic > out_local_V_data_1_V_blk_n;
sc_signal< sc_logic > out_local_V_data_2_V_blk_n;
sc_signal< sc_logic > out_local_V_data_3_V_blk_n;
sc_signal< sc_logic > out_local_V_data_4_V_blk_n;
sc_signal< sc_logic > out_local_V_data_5_V_blk_n;
sc_signal< sc_logic > out_local_V_data_6_V_blk_n;
sc_signal< sc_logic > out_local_V_data_7_V_blk_n;
sc_signal< sc_logic > out_local_V_data_8_V_blk_n;
sc_signal< sc_logic > out_local_V_data_9_V_blk_n;
sc_signal< sc_logic > io_acc_block_signal_op12;
sc_signal< bool > ap_block_state1;
sc_signal< sc_lv<16> > tmp_data_V_0_preg;
sc_signal< sc_lv<16> > tmp_data_V_1_preg;
sc_signal< sc_lv<16> > tmp_data_V_2_preg;
sc_signal< sc_lv<16> > tmp_data_V_3_preg;
sc_signal< sc_lv<16> > tmp_data_V_4_preg;
sc_signal< sc_lv<16> > tmp_data_V_5_preg;
sc_signal< sc_lv<16> > tmp_data_V_6_preg;
sc_signal< sc_lv<16> > tmp_data_V_7_preg;
sc_signal< sc_lv<16> > tmp_data_V_8_preg;
sc_signal< sc_lv<16> > tmp_data_V_9_preg;
sc_signal< sc_lv<1> > ap_NS_fsm;
static const sc_logic ap_const_logic_1;
static const sc_logic ap_const_logic_0;
static const sc_lv<1> ap_ST_fsm_state1;
static const sc_lv<32> ap_const_lv32_0;
static const sc_lv<16> ap_const_lv16_0;
static const bool ap_const_boolean_1;
// Thread declarations
void thread_ap_clk_no_reset_();
void thread_ap_CS_fsm_state1();
void thread_ap_block_state1();
void thread_ap_done();
void thread_ap_idle();
void thread_ap_ready();
void thread_io_acc_block_signal_op12();
void thread_out_local_V_data_0_V_blk_n();
void thread_out_local_V_data_0_V_read();
void thread_out_local_V_data_1_V_blk_n();
void thread_out_local_V_data_1_V_read();
void thread_out_local_V_data_2_V_blk_n();
void thread_out_local_V_data_2_V_read();
void thread_out_local_V_data_3_V_blk_n();
void thread_out_local_V_data_3_V_read();
void thread_out_local_V_data_4_V_blk_n();
void thread_out_local_V_data_4_V_read();
void thread_out_local_V_data_5_V_blk_n();
void thread_out_local_V_data_5_V_read();
void thread_out_local_V_data_6_V_blk_n();
void thread_out_local_V_data_6_V_read();
void thread_out_local_V_data_7_V_blk_n();
void thread_out_local_V_data_7_V_read();
void thread_out_local_V_data_8_V_blk_n();
void thread_out_local_V_data_8_V_read();
void thread_out_local_V_data_9_V_blk_n();
void thread_out_local_V_data_9_V_read();
void thread_tmp_data_V_0();
void thread_tmp_data_V_0_ap_vld();
void thread_tmp_data_V_1();
void thread_tmp_data_V_1_ap_vld();
void thread_tmp_data_V_2();
void thread_tmp_data_V_2_ap_vld();
void thread_tmp_data_V_3();
void thread_tmp_data_V_3_ap_vld();
void thread_tmp_data_V_4();
void thread_tmp_data_V_4_ap_vld();
void thread_tmp_data_V_5();
void thread_tmp_data_V_5_ap_vld();
void thread_tmp_data_V_6();
void thread_tmp_data_V_6_ap_vld();
void thread_tmp_data_V_7();
void thread_tmp_data_V_7_ap_vld();
void thread_tmp_data_V_8();
void thread_tmp_data_V_8_ap_vld();
void thread_tmp_data_V_9();
void thread_tmp_data_V_9_ap_vld();
void thread_ap_NS_fsm();
};
}
using namespace ap_rtl;
#endif
|
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD and is protected under U.S. and international copyright
// and other intellectual property laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// AMD, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) AMD shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or AMD had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// AMD products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of AMD products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
#ifndef _icyradio_GND_15_0_H_
#define _icyradio_GND_15_0_H_
#include "xlconstant_v1_1_8.h"
#include "systemc.h"
class icyradio_GND_15_0 : public sc_module {
public:
xlconstant_v1_1_8<5,0> mod;
sc_out< sc_bv<5> > dout;
icyradio_GND_15_0 (sc_core::sc_module_name name);
};
#endif
|
/// \file
/// Implementation of the class Ilator.
#include <ilang/target-sc/ilator.h>
#include <fstream>
#include <fmt/format.h>
#include <z3++.h>
#include <ilang/config.h>
#include <ilang/ila-mngr/pass.h>
#include <ilang/ila-mngr/u_abs_knob.h>
#include <ilang/ila/ast_hub.h>
#include <ilang/target-smt/z3_expr_adapter.h>
#include <ilang/util/fs.h>
#include <ilang/util/log.h>
/// \namespace ilang
namespace ilang {
//
// static helpers/members
//
static const std::string kDirApp = "app";
static const std::string kDirSrc = "src";
static const std::string kDirInclude = "include";
static const std::string kDirExtern = "extern";
static std::unordered_map<size_t, size_t> kPivotalId;
size_t GetPivotalId(const size_t& id) {
if (auto pos = kPivotalId.find(id); pos == kPivotalId.end()) {
auto new_id = kPivotalId.size();
kPivotalId.insert({id, new_id});
return new_id;
} else {
return pos->second;
}
}
void WriteFile(const std::string& file_path, const fmt::memory_buffer& buff) {
std::ofstream fw(file_path);
ILA_ASSERT(fw.is_open()) << "Fail opening file " << file_path;
fw << to_string(buff);
fw.close();
}
bool HasLoadFromStore(const ExprPtr& expr) {
auto monitor = false;
auto LoadFromStore = [&monitor](const ExprPtr& e) {
if (e->is_op()) {
if (asthub::GetUidExprOp(e) == AstUidExprOp::kLoad) {
monitor |= e->arg(0)->is_op();
}
}
};
expr->DepthFirstVisit(LoadFromStore);
return monitor;
}
//
// Ilator implementation
//
Ilator::Ilator(const InstrLvlAbsPtr& m) : m_(m) {}
Ilator::~Ilator() { Reset(); }
void Ilator::Generate(const std::string& dst, bool opt) {
// sanity checks and initialize
if (!SanityCheck() || !Bootstrap(dst, opt)) {
return;
}
auto status = true;
ILA_INFO << "Start generating SystemC simulator of " << m_;
// non-instruction basics
status &= GenerateIlaBasics(os_portable_append_dir(dst, kDirSrc));
// instruction semantics (decode and updates)
for (auto& instr : absknob::GetInstrTree(m_)) {
status &= GenerateInstrContent(instr, os_portable_append_dir(dst, kDirSrc));
}
// memory updates
status &= GenerateMemoryUpdate(os_portable_append_dir(dst, kDirSrc));
// constant memory
status &= GenerateConstantMemory(os_portable_append_dir(dst, kDirSrc));
// initial condition setup
status &= GenerateInitialSetup(os_portable_append_dir(dst, kDirSrc));
// execution kernel
status &= GenerateExecuteKernel(os_portable_append_dir(dst, kDirSrc));
// shared header (input, state, func., etc.)
status &= GenerateGlobalHeader(os_portable_append_dir(dst, kDirInclude));
// cmake support, e.g., recipe and templates
status &= GenerateBuildSupport(dst);
// clean up if something went wrong
if (status) {
ILA_INFO << "Sucessfully generate SystemC simulator at " << dst;
} else {
ILA_ERROR << "Fail generating simulator at " << dst;
#ifdef NDEBUG
os_portable_remove_directory(dst);
#endif // NDEBUG
}
}
void Ilator::Reset() {
// functions
for (auto f : functions_) {
delete f.second;
}
functions_.clear();
// externs
for (auto f : externs_) {
delete f.second;
}
externs_.clear();
// memory updates
for (auto f : memory_updates_) {
delete f.second;
}
memory_updates_.clear();
// others
source_files_.clear();
const_mems_.clear();
global_vars_.clear();
}
bool Ilator::SanityCheck() const {
// add new check here
return true;
}
bool Ilator::Bootstrap(const std::string& root, bool opt) {
Reset();
auto status = true;
// light-weight preprocessing
if (opt) {
status &= pass::SimplifySyntactic(m_);
status &= pass::RewriteConditionalStore(m_);
}
// create/structure project directory
status &= os_portable_mkdir(root);
status &= os_portable_mkdir(os_portable_append_dir(root, kDirApp));
status &= os_portable_mkdir(os_portable_append_dir(root, kDirExtern));
status &= os_portable_mkdir(os_portable_append_dir(root, kDirInclude));
status &= os_portable_mkdir(os_portable_append_dir(root, kDirSrc));
if (!status) {
os_portable_remove_directory(root);
}
ILA_ERROR_IF(!status) << "Fail bootstraping";
return status;
}
bool Ilator::GenerateIlaBasics(const std::string& dir) {
StrBuff buff;
// include headers
fmt::format_to(buff, "#include <{}.h>\n", GetProjectName());
// generate valid func for each ILA
auto PerIla = [this, &buff](const InstrLvlAbsCnstPtr& m) {
ILA_NOT_NULL(m);
auto valid_expr = m->valid();
if (!valid_expr) {
valid_expr = asthub::BoolConst(true);
ILA_WARN << "Use default (true) valid for " << m;
}
auto valid_func = RegisterFunction(GetValidFuncName(m), valid_expr);
BeginFuncDef(valid_func, buff);
ExprVarMap lut;
ILA_CHECK(RenderExpr(valid_expr, buff, lut));
fmt::format_to(buff, "auto& {universal_name} = {local_name};\n",
fmt::arg("universal_name", GetCxxName(valid_expr)),
fmt::arg("local_name", LookUp(valid_expr, lut)));
EndFuncDef(valid_func, buff);
};
// traverse the hierarchy
m_->DepthFirstVisit(PerIla);
// record and write to file
CommitSource("all_valid_funcs_in_hier.cc", dir, buff);
return true;
}
bool Ilator::GenerateInstrContent(const InstrPtr& instr,
const std::string& dir) {
StrBuff buff;
ExprVarMap lut;
// include headers
fmt::format_to(buff, "#include <{}.h>\n", GetProjectName());
// decode function
auto decode_expr = instr->decode();
auto decode_func = RegisterFunction(GetDecodeFuncName(instr), decode_expr);
BeginFuncDef(decode_func, buff);
lut.clear();
if (!RenderExpr(decode_expr, buff, lut)) {
return false;
}
fmt::format_to(buff, "auto& {universal_name} = {local_name};\n",
fmt::arg("universal_name", GetCxxName(decode_expr)),
fmt::arg("local_name", LookUp(decode_expr, lut)));
EndFuncDef(decode_func, buff);
// next state
auto update_func = RegisterFunction(GetUpdateFuncName(instr));
BeginFuncDef(update_func, buff);
lut.clear();
std::set<ExprPtr> visited;
auto updated_states = instr->updated_states();
for (const auto& s : updated_states) {
// check if visited
auto update_expr = instr->update(s);
if (auto pos = visited.find(update_expr); pos == visited.end()) {
visited.insert(update_expr);
} else {
continue;
}
// create placeholder
if (auto update_expr = instr->update(s); !update_expr->is_mem()) {
if (!RenderExpr(update_expr, buff, lut)) {
return false;
}
fmt::format_to(buff, "auto {local_var}_nxt_holder = {local_var};\n",
fmt::arg("local_var", LookUp(update_expr, lut)));
} else { // memory (one copy for performance, require special handling)
if (HasLoadFromStore(update_expr)) {
return false;
}
auto placeholder = GetLocalVar(lut);
auto [it, status] = lut.try_emplace(update_expr, placeholder);
ILA_ASSERT(status);
auto mem_update_func = RegisterMemoryUpdate(update_expr);
fmt::format_to(buff,
"{mem_type} {placeholder};\n"
"{mem_update_func}({placeholder});\n",
fmt::arg("mem_type", GetCxxType(update_expr)),
fmt::arg("mem_update_func", mem_update_func->name),
fmt::arg("placeholder", placeholder));
// dummy traverse collect related memory operation
StrBuff dummy_buff;
ExprVarMap dummy_lut;
if (!RenderExpr(update_expr, dummy_buff, dummy_lut)) {
return false;
}
}
}
// update state
for (auto& s : updated_states) {
auto curr = instr->host()->state(s);
auto next = instr->update(s);
if (!curr->is_mem()) {
fmt::format_to(buff, "{current} = {next_value}_nxt_holder;\n",
fmt::arg("current", GetCxxName(curr)),
fmt::arg("next_value", LookUp(next, lut)));
} else {
fmt::format_to(buff,
"for (auto& it : {next_value}) {{\n"
" {current}[it.first] = it.second;\n"
"}}\n",
fmt::arg("current", GetCxxName(curr)),
fmt::arg("next_value", LookUp(next, lut)));
}
}
// add update states logging
fmt::format_to(buff, "#ifdef ILATOR_VERBOSE\n");
fmt::format_to(buff, "instr_update_log << \"No.\" << std::dec << GetInstrCntr() << '\\t' << "
"\"{instr_name} state updates:\" << std::endl;\n",
fmt::arg("instr_name", instr->name().str()));
for (auto& s : updated_states) {
auto curr = instr->host()->state(s);
if (!curr->is_mem()) {
fmt::format_to(buff,
"instr_update_log << \" {state_name} => \" << "
"std::hex << \"0x\" << {state_name} << std::endl; \n",
fmt::arg("state_name", GetCxxName(curr)));
} else {
fmt::format_to(buff,
"instr_update_log << \" {state_name} get updated\" "
"<< std::endl;\n",
fmt::arg("state_name", GetCxxName(curr)));
}
}
fmt::format_to(buff, "instr_update_log << std::endl;\n");
fmt::format_to(buff, "#endif\n");
EndFuncDef(update_func, buff);
// record and write to file
CommitSource(fmt::format("idu_{}.cc", instr->name().str()), dir, buff);
return true;
}
bool Ilator::GenerateMemoryUpdate(const std::string& dir) {
// helper for traversing memory updates
class MemUpdateVisiter {
public:
MemUpdateVisiter(Ilator* h, StrBuff& b, ExprVarMap& l)
: host(h), buff_ref(b), lut_ref(l) {}
bool pre(const ExprPtr& expr) {
// stop traversing when reaching memory ITE (stand-alone func)
if (expr->is_mem() && expr->is_op() &&
asthub::GetUidExprOp(expr) == AstUidExprOp::kIfThenElse) {
host->DfsExpr(expr, buff_ref, lut_ref);
return true;
} else {
return false;
}
}
void post(const ExprPtr& expr) { host->DfsExpr(expr, buff_ref, lut_ref); }
Ilator* host;
StrBuff& buff_ref;
ExprVarMap lut_ref;
};
auto RenderMemUpdate = [this](const ExprPtr& e, StrBuff& b, ExprVarMap& l) {
auto mem_visiter = MemUpdateVisiter(this, b, l);
e->DepthFirstVisitPrePost(mem_visiter);
};
// helpers for managing files
int file_cnt = 0;
auto GetMemUpdateFile = [&file_cnt]() {
return fmt::format("memory_update_functions_{}.cc", file_cnt++);
};
StrBuff buff;
auto StartNewFile = [this, &buff]() {
buff.clear();
fmt::format_to(buff, "#include <{}.h>\n", GetProjectName());
};
// start generating
StartNewFile();
ExprVarMap lut;
for (auto mem_update_func_it : memory_updates_) {
auto& mem_update_func = mem_update_func_it.second;
ILA_NOT_NULL(mem_update_func);
auto& mem = mem_update_func->target;
lut.clear();
BeginFuncDef(mem_update_func, buff);
if (asthub::GetUidExprOp(mem) == AstUidExprOp::kStore) {
RenderMemUpdate(mem, buff, lut);
} else { // ite
RenderExpr(mem->arg(0), buff, lut);
auto lut_local_true = lut;
auto& lut_local_false = lut; // reuse
fmt::format_to(buff, "if ({}) {{\n", LookUp(mem->arg(0), lut));
RenderMemUpdate(mem->arg(1), buff, lut_local_true);
fmt::format_to(buff, "}} else {{\n");
RenderMemUpdate(mem->arg(2), buff, lut_local_false);
fmt::format_to(buff, "}}\n");
}
EndFuncDef(mem_update_func, buff);
if (buff.size() > 50000) {
CommitSource(GetMemUpdateFile(), dir, buff);
StartNewFile();
}
}
CommitSource(GetMemUpdateFile(), dir, buff);
return true;
}
bool Ilator::GenerateConstantMemory(const std::string& dir) {
StrBuff buff;
fmt::format_to(buff, "#include <{}.h>\n", GetProjectName());
for (auto& mem : const_mems_) {
auto const_mem = std::dynamic_pointer_cast<ExprConst>(mem);
const auto& val_map = const_mem->val_mem()->val_map();
std::vector<std::string> addr_data_pairs;
for (auto& it : val_map) {
addr_data_pairs.push_back(fmt::format(" {{{addr}, {data}}}",
fmt::arg("addr", it.first),
fmt::arg("data", it.second)));
}
fmt::format_to(
buff,
"{var_type} {project}::{var_name} = {{\n"
"{addr_data_pairs}\n"
"}};\n",
fmt::arg("var_type", GetCxxType(mem)),
fmt::arg("project", GetProjectName()),
fmt::arg("var_name", GetCxxName(mem)),
fmt::arg("addr_data_pairs", fmt::join(addr_data_pairs, ",\n")));
}
CommitSource("constant_memory_def.cc", dir, buff);
return true;
}
bool Ilator::GenerateInitialSetup(const std::string& dir) {
// conjunct all initial condition
auto init = asthub::BoolConst(true);
auto ConjInit = [&init](const InstrLvlAbsCnstPtr& m) {
for (size_t i = 0; i < m->init_num(); i++) {
init = asthub::And(init, m->init(i));
}
};
m_->DepthFirstVisit(ConjInit);
// get value for referred vars
z3::context ctx;
z3::solver solver(ctx);
Z3ExprAdapter gen(ctx);
solver.add(gen.GetExpr(init));
auto res = solver.check();
if (res != z3::sat) {
ILA_ERROR << "Fail finding assignment satisfying initial condition";
return false;
}
std::map<ExprPtr, uint64_t> init_values;
auto model = solver.get_model();
auto refer_vars = absknob::GetVar(init);
for (const auto& var : refer_vars) {
auto var_value = model.eval(gen.GetExpr(var));
try {
#ifndef Z3_LEGACY_API
auto value_holder = var_value.get_numeral_uint64();
#else
__uint64 value_holder;
Z3_get_numeral_uint64(ctx, var_value, &value_holder);
#endif
init_values.emplace(var, value_holder);
} catch (...) {
ILA_ERROR << "Fail getting " << var_value;
return false;
}
}
// gen file
auto init_func = RegisterFunction("setup_initial_condition");
StrBuff buff;
fmt::format_to(buff, "#include <{}.h>\n", GetProjectName());
BeginFuncDef(init_func, buff);
for (auto pair : init_values) {
fmt::format_to(buff, "{var_name} = {var_value};\n",
fmt::arg("var_name", GetCxxName(pair.first)),
fmt::arg("var_value", pair.second));
}
EndFuncDef(init_func, buff);
CommitSource("setup_initial_condition.cc", dir, buff);
return true;
}
bool Ilator::GenerateExecuteKernel(const std::string& dir) {
StrBuff buff;
fmt::format_to( // headers
buff,
"#include <iomanip>\n"
"#include <{project}.h>\n",
fmt::arg("project", GetProjectName()));
fmt::format_to( // logging
buff,
"static int instr_cntr = 0;\n"
"int {project}::GetInstrCntr() {{\n"
" return instr_cntr;\n"
"}}\n"
"void {project}::IncrementInstrCntr() {{\n"
" instr_cntr++;\n"
"}}\n"
"void {project}::LogInstrSequence(const std::string& instr_name) {{\n"
" instr_log << \"Instr No.\" << std::setw(5) << GetInstrCntr() << '\\t';\n"
" instr_log << instr_name << \" is activated\\n\";\n"
" IncrementInstrCntr();\n"
"}}\n",
fmt::arg("project", GetProjectName()));
fmt::format_to(buff, "static bool g_initialized = false;\n");
auto kernel_func = RegisterFunction("compute");
BeginFuncDef(kernel_func, buff);
// setup initial condition
fmt::format_to(buff, "if (!g_initialized) {{\n"
" setup_initial_condition();\n"
" g_initialized = true;\n"
"}}\n");
// read in input value
for (size_t i = 0; i < m_->input_num(); i++) {
fmt::format_to(buff, "{input_name} = {input_name}_in.read();\n",
fmt::arg("input_name", GetCxxName(m_->input(i))));
}
// instruction execution
auto ExecInstr = [this, &buff](const InstrPtr& instr, bool child) {
fmt::format_to(
buff,
"if ({valid_func_name}() && {decode_func_name}()) {{\n"
" {update_func_name}();\n"
" {child_counter}"
"#ifdef ILATOR_VERBOSE\n"
" LogInstrSequence(\"{instr_name}\");\n"
"#endif\n"
"}}\n",
fmt::arg("valid_func_name", GetValidFuncName(instr->host())),
fmt::arg("decode_func_name", GetDecodeFuncName(instr)),
fmt::arg("update_func_name", GetUpdateFuncName(instr)),
fmt::arg("child_counter", (child ? "schedule_counter++;\n" : "")),
fmt::arg("instr_name", instr->name().str()));
};
auto top_instrs = absknob::GetInstr(m_);
auto all_instrs = absknob::GetInstrTree(m_);
// top-level instr
for (auto& instr : top_instrs) {
ExecInstr(instr, false);
}
// child instr
fmt::format_to(buff, "while (1) {{\n"
" int schedule_counter = 0;\n");
std::set<InstrPtr> tops(top_instrs.begin(), top_instrs.end());
for (auto& instr : all_instrs) {
if (tops.find(instr) == tops.end()) {
ExecInstr(instr, true);
}
}
fmt::format_to(buff, " if (schedule_counter == 0) {{\n"
" break;\n"
" }}\n"
"}}\n");
// done
EndFuncDef(kernel_func, buff);
CommitSource("compute.cc", dir, buff);
return true;
}
bool Ilator::GenerateGlobalHeader(const std::string& dir) {
StrBuff buff;
fmt::format_to(buff,
"#include <fstream>\n"
"#include <systemc.h>\n"
#ifdef ILATOR_PRECISE_MEM
"#include <map>\n"
#else
"#include <unordered_map>\n"
#endif
"SC_MODULE({project}) {{\n"
// " extern int instr_cntr;\n"
" std::ofstream instr_log;\n"
" std::ofstream instr_update_log;\n" // add instruction state update logging
" int GetInstrCntr();\n"
" void IncrementInstrCntr();\n"
" void LogInstrSequence(const std::string& instr_name);\n",
fmt::arg("project", GetProjectName()));
// input
for (auto& var : absknob::GetInp(m_)) {
fmt::format_to(buff,
" sc_in<{var_type}> {var_name}_in;\n"
" {var_type} {var_name};\n",
fmt::arg("var_type", GetCxxType(var)),
fmt::arg("var_name", GetCxxName(var)));
}
// state and global vars (e.g., CONCAT)
for (auto& var : absknob::GetSttTree(m_)) {
fmt::format_to(buff, " {var_type} {var_name};\n",
fmt::arg("var_type", GetCxxType(var)),
fmt::arg("var_name", GetCxxName(var)));
}
for (auto& var : global_vars_) {
fmt::format_to(buff, " {var_type} {var_name};\n",
fmt::arg("var_type", GetCxxType(var)),
fmt::arg("var_name", GetCxxName(var)));
}
// memory constant
for (auto& mem : const_mems_) {
fmt::format_to(buff, " static {var_type} {var_name};\n",
fmt::arg("var_type", GetCxxType(mem)),
fmt::arg("var_name", GetCxxName(mem)));
}
// function declaration
for (auto& func : functions_) {
WriteFuncDecl(func.second, buff);
}
for (auto& func : externs_) {
WriteFuncDecl(func.second, buff);
}
for (auto& func : memory_updates_) {
WriteFuncDecl(func.second, buff);
}
// invoke
fmt::format_to(buff,
" SC_HAS_PROCESS({project});\n"
" {project}(sc_module_name name_) : sc_module(name_) {{\n"
" SC_METHOD(compute);\n"
" sensitive",
fmt::arg("project", GetProjectName()));
for (auto& var : absknob::GetInp(m_)) {
fmt::format_to(buff, " << {input_name}_in",
fmt::arg("input_name", GetCxxName(var)));
}
fmt::format_to(buff, ";\n"
" }}\n");
// done
fmt::format_to(buff, "}};\n");
// write to file
auto file_path = os_portable_append_dir(dir, GetProjectName() + ".h");
WriteFile(file_path, buff);
return true;
}
bool Il
|
ator::GenerateBuildSupport(const std::string& dir) {
// CMakeLists.txt
static const char* kCmakeRecipeTemplate =
"# CMakeLists.txt for {project}\n"
"cmake_minimum_required(VERSION 3.14.0)\n"
"project({project} LANGUAGES CXX)\n"
"\n"
"option(ILATOR_VERBOSE \"Enable instruction sequence logging\" OFF)\n"
// "option(ILATOR_INSN_VERBOSE \"Enable instruction state updates logging\" OFF)\n"
"option(JSON_SUPPORT \"Build JSON parser support\" OFF)\n"
"\n"
"find_package(SystemCLanguage CONFIG REQUIRED)\n"
"set(CMAKE_CXX_STANDARD ${{SystemC_CXX_STANDARD}})\n"
"\n"
"aux_source_directory(extern extern_src)\n"
"add_executable({project}\n"
" ${{CMAKE_CURRENT_SOURCE_DIR}}/{dir_app}/main.cc\n"
" ${{extern_src}}\n"
"{source_files}\n"
")\n"
"\n"
"target_include_directories({project} PRIVATE {dir_include})\n"
"target_link_libraries({project} SystemC::systemc)\n"
"if(${{ILATOR_VERBOSE}})\n"
" target_compile_definitions({project} PRIVATE ILATOR_VERBOSE)\n"
"endif()\n"
// "if(${{ILATOR_INSN_VERBOSE}})\n"
// " target_compile_definitions({project} PRIVATE ILATOR_INSN_VERBOSE)\n"
// "endif()\n"
"if(${{JSON_SUPPORT}})\n"
" include(FetchContent)\n"
" FetchContent_Declare(\n"
" json\n"
" GIT_REPOSITORY https://github.com/nlohmann/json.git\n"
" GIT_TAG v3.8.0\n"
" )\n"
" FetchContent_MakeAvailable(json)\n"
" target_link_libraries({project} nlohmann_json::nlohmann_json)\n"
"endif()\n";
std::vector<std::string> src_files;
for (auto& f : source_files_) {
src_files.push_back(
fmt::format(" ${{CMAKE_CURRENT_SOURCE_DIR}}/{dir}/{file}",
fmt::arg("dir", kDirSrc), fmt::arg("file", f)));
}
StrBuff buff;
fmt::format_to(buff, kCmakeRecipeTemplate,
fmt::arg("project", GetProjectName()),
fmt::arg("dir_app", kDirApp),
fmt::arg("source_files", fmt::join(src_files, "\n")),
fmt::arg("dir_include", kDirInclude));
WriteFile(os_portable_append_dir(dir, "CMakeLists.txt"), buff);
// dummy main function if not exist
static const char* kSimEntryTemplate =
"#include <{project}.h>\n\n"
"int sc_main(int argc, char* argv[]) {{\n"
" return 0; \n"
"}}\n";
auto entry_path =
os_portable_append_dir(os_portable_append_dir(dir, kDirApp), "main.cc");
if (!os_portable_exist(entry_path)) {
buff.clear();
fmt::format_to(buff, kSimEntryTemplate,
fmt::arg("project", GetProjectName()));
WriteFile(entry_path, buff);
}
return true;
}
bool Ilator::RenderExpr(const ExprPtr& expr, StrBuff& buff, ExprVarMap& lut) {
class ExprDfsVisiter {
public:
ExprDfsVisiter(Ilator* hi, StrBuff& bi, ExprVarMap& li)
: host(hi), b(bi), l(li) {}
bool pre(const ExprPtr& e) { return l.find(e) != l.end(); }
void post(const ExprPtr& e) { host->DfsExpr(e, b, l); }
Ilator* host;
StrBuff& b;
ExprVarMap& l;
};
try {
auto visiter = ExprDfsVisiter(this, buff, lut);
expr->DepthFirstVisitPrePost(visiter);
} catch (std::exception& err) {
ILA_ERROR << err.what();
return false;
}
return true;
}
Ilator::CxxFunc* Ilator::RegisterFunction(const std::string& func_name,
ExprPtr return_expr) {
auto func = new CxxFunc(func_name, return_expr);
auto [it, status] = functions_.insert({func->name, func});
ILA_ASSERT(status);
return func;
}
Ilator::CxxFunc* Ilator::RegisterExternalFunc(const FuncPtr& func) {
auto func_cxx = new CxxFunc(func->name().str(), func->out());
auto [it, status] = externs_.insert({func_cxx->name, func_cxx});
// uninterpreted function can have multiple occurrence
if (status) {
for (size_t i = 0; i < func->arg_num(); i++) {
it->second->args.push_back(func->arg(i));
}
} else {
delete func_cxx;
}
return it->second;
}
Ilator::CxxFunc* Ilator::RegisterMemoryUpdate(const ExprPtr& mem) {
auto func_cxx = new CxxFunc(GetMemoryFuncName(mem), NULL, mem);
auto [it, status] = memory_updates_.insert({func_cxx->name, func_cxx});
// memory updates can have multiple occurrence
if (!status) {
delete func_cxx;
}
return it->second;
}
void Ilator::BeginFuncDef(Ilator::CxxFunc* func, StrBuff& buff) const {
ILA_ASSERT(func->args.empty()); // no definition for uninterpreted funcs
auto type = (func->ret) ? GetCxxType(func->ret) : GetCxxType(func->ret_type);
auto args = (func->target)
? fmt::format("{}& tmp_memory", GetCxxType(func->target))
: "";
fmt::format_to(buff, "{return_type} {project}::{func_name}({argument}) {{\n",
fmt::arg("return_type", type),
fmt::arg("project", GetProjectName()),
fmt::arg("func_name", func->name), fmt::arg("argument", args));
}
void Ilator::EndFuncDef(Ilator::CxxFunc* func, StrBuff& buff) const {
if (func->ret) {
fmt::format_to(buff, "return {};\n", GetCxxName(func->ret));
}
fmt::format_to(buff, "}}\n");
}
void Ilator::WriteFuncDecl(Ilator::CxxFunc* func, StrBuff& buff) const {
auto type = (func->ret) ? GetCxxType(func->ret) : GetCxxType(func->ret_type);
auto args = (func->target)
? fmt::format("{}& tmp_memory", GetCxxType(func->target))
: "";
if (!func->args.empty()) { // uninterpreted func only
ILA_NOT_NULL(func->ret_type);
std::vector<std::string> arg_list;
for (const auto& a : func->args) {
arg_list.push_back(GetCxxType(a));
}
args = fmt::format("{}", fmt::join(arg_list, ", "));
}
fmt::format_to(buff, " {return_type} {func_name}({argument});\n",
fmt::arg("return_type", type),
fmt::arg("func_name", func->name), fmt::arg("argument", args));
}
void Ilator::CommitSource(const std::string& file_name, const std::string& dir,
const StrBuff& buff) {
auto file_path = os_portable_append_dir(dir, file_name);
auto [it, ret] = source_files_.insert(file_name);
ILA_ASSERT(ret) << "Duplicated source file name " << file_name;
WriteFile(file_path, buff);
}
std::string Ilator::GetCxxType(const SortPtr& sort) {
if (!sort) {
return "void";
} else if (sort->is_bool()) {
return "bool";
} else if (sort->is_bv()) {
return fmt::format("sc_biguint<{}>", sort->bit_width());
} else {
ILA_ASSERT(sort->is_mem());
#ifdef ILATOR_PRECISE_MEM
return fmt::format(
"std::map<sc_biguint<{addr_width}>, sc_biguint<{data_width}>>",
fmt::arg("addr_width", sort->addr_width()),
fmt::arg("data_width", sort->data_width()));
#else
return "std::unordered_map<int, int>";
#endif
}
}
std::string Ilator::GetCxxName(const ExprPtr& expr) {
if (expr->is_var()) {
return fmt::format("{}_{}", expr->host()->name().str(), expr->name().str());
} else {
return fmt::format("univ_var_{}", GetPivotalId(expr->name().id()));
}
}
std::string Ilator::GetValidFuncName(const InstrLvlAbsCnstPtr& m) {
return fmt::format("valid_{host}", fmt::arg("host", m->name().str()));
}
std::string Ilator::GetDecodeFuncName(const InstrPtr& instr) {
return fmt::format("decode_{host}_{instr}",
fmt::arg("host", instr->host()->name().str()),
fmt::arg("instr", instr->name().str()));
}
std::string Ilator::GetUpdateFuncName(const InstrPtr& instr) {
return fmt::format("update_{host}_{instr}",
fmt::arg("host", instr->host()->name().str()),
fmt::arg("instr", instr->name().str()));
}
std::string Ilator::GetMemoryFuncName(const ExprPtr& expr) {
ILA_ASSERT(expr->is_mem());
if (asthub::GetUidExprOp(expr) == AstUidExprOp::kIfThenElse) {
return fmt::format("ite_{}", GetPivotalId(expr->name().id()));
} else {
return fmt::format("store_{}", GetPivotalId(expr->name().id()));
}
}
} // namespace ilang
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
#ifndef _bd_7ded_one_0_H_
#define _bd_7ded_one_0_H_
#include "xlconstant_v1_1.h"
#include "systemc.h"
class bd_7ded_one_0 : public sc_module {
public:
xlconstant_v1_1_5<1,1> mod;
sc_out< sc_bv<1> > dout;
bd_7ded_one_0 (sc_core::sc_module_name name) :sc_module(name), mod("mod") {
mod.dout(dout);
}
};
#endif
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
#ifndef _base_constant_tkeep_tstrb_0_H_
#define _base_constant_tkeep_tstrb_0_H_
#include "xlconstant_v1_1.h"
#include "systemc.h"
class base_constant_tkeep_tstrb_0 : public sc_module {
public:
xlconstant_v1_1_5<8,255> mod;
sc_out< sc_bv<8> > dout;
base_constant_tkeep_tstrb_0 (sc_core::sc_module_name name) :sc_module(name), mod("mod") {
mod.dout(dout);
}
};
#endif
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
#ifndef _base_constant_tkeep_tstrb_0_H_
#define _base_constant_tkeep_tstrb_0_H_
#include "xlconstant_v1_1.h"
#include "systemc.h"
class base_constant_tkeep_tstrb_0 : public sc_module {
public:
xlconstant_v1_1_5<8,255> mod;
sc_out< sc_bv<8> > dout;
base_constant_tkeep_tstrb_0 (sc_core::sc_module_name name) :sc_module(name), mod("mod") {
mod.dout(dout);
}
};
#endif
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
#ifndef _design_1_xlconstant_0_23_H_
#define _design_1_xlconstant_0_23_H_
#include "xlconstant_v1_1_6.h"
#include "systemc.h"
class design_1_xlconstant_0_23 : public sc_module {
public:
xlconstant_v1_1_6<1,0> mod;
sc_out< sc_bv<1> > dout;
design_1_xlconstant_0_23 (sc_core::sc_module_name name) :sc_module(name), mod("mod") {
mod.dout(dout);
}
};
#endif
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
#ifndef _design_1_xlconstant_0_23_H_
#define _design_1_xlconstant_0_23_H_
#include "xlconstant_v1_1_6.h"
#include "systemc.h"
class design_1_xlconstant_0_23 : public sc_module {
public:
xlconstant_v1_1_6<1,0> mod;
sc_out< sc_bv<1> > dout;
design_1_xlconstant_0_23 (sc_core::sc_module_name name) :sc_module(name), mod("mod") {
mod.dout(dout);
}
};
#endif
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
#ifndef _design_1_xlconstant_0_23_H_
#define _design_1_xlconstant_0_23_H_
#include "xlconstant_v1_1_6.h"
#include "systemc.h"
class design_1_xlconstant_0_23 : public sc_module {
public:
xlconstant_v1_1_6<1,0> mod;
sc_out< sc_bv<1> > dout;
design_1_xlconstant_0_23 (sc_core::sc_module_name name) :sc_module(name), mod("mod") {
mod.dout(dout);
}
};
#endif
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
#ifndef _design_1_xlconstant_0_23_H_
#define _design_1_xlconstant_0_23_H_
#include "xlconstant_v1_1_6.h"
#include "systemc.h"
class design_1_xlconstant_0_23 : public sc_module {
public:
xlconstant_v1_1_6<1,0> mod;
sc_out< sc_bv<1> > dout;
design_1_xlconstant_0_23 (sc_core::sc_module_name name) :sc_module(name), mod("mod") {
mod.dout(dout);
}
};
#endif
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.3
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _axis_timestamper_HH_
#define _axis_timestamper_HH_
#include "systemc.h"
#include "AESL_pkg.h"
namespace ap_rtl {
struct axis_timestamper : public sc_module {
// Port declarations 13
sc_in_clk ap_clk;
sc_in< sc_logic > ap_rst_n;
sc_in< sc_lv<64> > data_in_TDATA;
sc_in< sc_logic > data_in_TVALID;
sc_out< sc_logic > data_in_TREADY;
sc_in< sc_lv<8> > data_in_TKEEP;
sc_in< sc_lv<1> > data_in_TLAST;
sc_out< sc_lv<64> > data_out_TDATA;
sc_out< sc_logic > data_out_TVALID;
sc_in< sc_logic > data_out_TREADY;
sc_out< sc_lv<8> > data_out_TKEEP;
sc_out< sc_lv<1> > data_out_TLAST;
sc_in< sc_lv<1> > start_V;
// Module declarations
axis_timestamper(sc_module_name name);
SC_HAS_PROCESS(axis_timestamper);
~axis_timestamper();
sc_trace_file* mVcdFile;
ofstream mHdltvinHandle;
ofstream mHdltvoutHandle;
sc_signal< sc_logic > ap_rst_n_inv;
sc_signal< sc_lv<64> > timestamp_V;
sc_signal< sc_lv<1> > timestamp_flag_V;
sc_signal< sc_logic > data_in_TDATA_blk_n;
sc_signal< sc_lv<1> > ap_CS_fsm;
sc_signal< sc_logic > ap_CS_fsm_state1;
sc_signal< sc_lv<1> > tmp_1_nbreadreq_fu_70_p5;
sc_signal< sc_lv<1> > tmp_2_nbwritereq_fu_82_p5;
sc_signal< sc_logic > data_out_TDATA_blk_n;
sc_signal< sc_lv<64> > out_word_data_V_fu_129_p3;
sc_signal< bool > ap_predicate_op26_read_state1;
sc_signal< bool > ap_block_state1;
sc_signal< bool > ap_predicate_op30_write_state1;
sc_signal< bool > ap_predicate_op35_write_state1;
sc_signal< bool > ap_block_state1_io;
sc_signal< sc_lv<1> > tmp_last_V_fu_158_p1;
sc_signal< sc_lv<64> > tmp_fu_123_p2;
sc_signal< sc_lv<1> > ap_NS_fsm;
sc_signal< bool > ap_condition_87;
sc_signal< bool > ap_condition_125;
static const sc_logic ap_const_logic_1;
static const sc_logic ap_const_logic_0;
static const sc_lv<1> ap_ST_fsm_state1;
static const sc_lv<64> ap_const_lv64_0;
static const sc_lv<1> ap_const_lv1_1;
static const bool ap_const_boolean_1;
static const sc_lv<32> ap_const_lv32_0;
static const sc_lv<1> ap_const_lv1_0;
static const sc_lv<8> ap_const_lv8_FF;
static const sc_lv<64> ap_const_lv64_1;
// Thread declarations
void thread_ap_clk_no_reset_();
void thread_ap_CS_fsm_state1();
void thread_ap_block_state1();
void thread_ap_block_state1_io();
void thread_ap_condition_125();
void thread_ap_condition_87();
void thread_ap_predicate_op26_read_state1();
void thread_ap_predicate_op30_write_state1();
void thread_ap_predicate_op35_write_state1();
void thread_ap_rst_n_inv();
void thread_data_in_TDATA_blk_n();
void thread_data_in_TREADY();
void thread_data_out_TDATA();
void thread_data_out_TDATA_blk_n();
void thread_data_out_TKEEP();
void thread_data_out_TLAST();
void thread_data_out_TVALID();
void thread_out_word_data_V_fu_129_p3();
void thread_tmp_1_nbreadreq_fu_70_p5();
void thread_tmp_2_nbwritereq_fu_82_p5();
void thread_tmp_fu_123_p2();
void thread_tmp_last_V_fu_158_p1();
void thread_ap_NS_fsm();
void thread_hdltv_gen();
};
}
using namespace ap_rtl;
#endif
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.2
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
#ifndef AESL_PKG_HH
#define AESL_PKG_HH
#include "systemc.h"
namespace ap_rtl {
////////////////////////////////////////////////////////////////
// Comparisons
////////////////////////////////////////////////////////////////
template <int T, int W0, int W1>
bool esl_seteq(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
assert(W0>=1 && W1>=1);
if (W0 > W1)
return (i0.range(W1-1, 0) == i1);
else
return (i1.range(W0-1, 0) == i0);
assert(W0 == W1);
return (i0 == i1);
}
template <int T, int W0, int W1>
bool esl_setne(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
assert(W0>=1 && W1>=1);
if (W0 > W1)
return (i0.range(W1-1, 0) != i1);
else
return (i1.range(W0-1, 0) != i0);
assert(W0 == W1);
return (i0 != i1);
}
template <int T, int W0, int W1>
bool esl_seteq(const sc_logic& i0, const sc_logic& i1) {
assert(W0 == W1);
return (i0 == i1);
}
template <int T, int W0, int W1>
bool esl_setne(const sc_logic& i0, const sc_logic& i1) {
assert(W0 == W1);
return (i0 != i1);
}
template <int T, int W0>
bool esl_not(bool i0) {
return (!i0);
}
template <int T, int W0>
sc_logic esl_not(const sc_logic& i0) {
return (~i0);
}
template <int T, int W0, int W1>
bool esl_setle(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
if (!i0.is_01() || !i1.is_01()) return false;
return (sc_biguint<W0>(i0) <= sc_biguint<W1>(i1));
}
template <int T, int W0, int W1>
bool esl_setge(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
if (!i0.is_01() || !i1.is_01()) return false;
return (sc_biguint<W0>(i0) >= sc_biguint<W1>(i1));
}
template <int T, int W0, int W1>
bool esl_setlt(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
if (!i0.is_01() || !i1.is_01()) return false;
return (sc_biguint<W0>(i0) < sc_biguint<W1>(i1));
}
template <int T, int W0, int W1>
bool esl_setgt(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
if (!i0.is_01() || !i1.is_01()) return false;
return (sc_biguint<W0>(i0) > sc_biguint<W1>(i1));
}
template <int T, int W0, int W1>
sc_lv<1> esl_icmp_eq(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
assert(W0 == W1);
if (!i0.is_01() || !i1.is_01()) return sc_lv<1>();
return sc_lv<1>(i0 == i1);
}
template <int T, int W0, int W1>
sc_lv<1> esl_icmp_ne(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
assert(W0 == W1);
if (!i0.is_01() || !i1.is_01()) return sc_lv<1>();
return sc_lv<1>(i0 != i1);
}
template <int T, int W0, int W1>
sc_lv<1> esl_icmp_ugt(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
if (!i0.is_01() || !i1.is_01()) return sc_lv<1>();
return (sc_biguint<W0>(i0) > sc_biguint<W1>(i1));
}
template <int T, int W0, int W1>
sc_lv<1> esl_icmp_uge(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
if (!i0.is_01() || !i1.is_01()) return sc_lv<1>();
return (sc_biguint<W0>(i0) >= sc_biguint<W1>(i1));
}
template <int T, int W0, int W1>
sc_lv<1> esl_icmp_ult(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
if (!i0.is_01() || !i1.is_01()) return sc_lv<1>();
return (sc_biguint<W0>(i0) < sc_biguint<W1>(i1));
}
template <int T, int W0, int W1>
sc_lv<1> esl_icmp_ule(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
if (!i0.is_01() || !i1.is_01()) return sc_lv<1>();
return (sc_biguint<W0>(i0) <= sc_biguint<W1>(i1));
}
template <int T, int W0, int W1>
sc_lv<1> esl_icmp_sgt(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
if (!i0.is_01() || !i1.is_01()) return sc_lv<1>();
return (sc_bigint<W0>(i0) > sc_bigint<W1>(i1));
}
template <int T, int W0, int W1>
sc_lv<1> esl_icmp_sge(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
if (!i0.is_01() || !i1.is_01()) return sc_lv<1>();
return (sc_bigint<W0>(i0) >= sc_bigint<W1>(i1));
}
template <int T, int W0, int W1>
sc_lv<1> esl_icmp_slt(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
if (!i0.is_01() || !i1.is_01()) return sc_lv<1>();
return (sc_bigint<W0>(i0) < sc_bigint<W1>(i1));
}
template <int T, int W0, int W1>
sc_lv<1> esl_icmp_sle(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
if (!i0.is_01() || !i1.is_01()) return sc_lv<1>();
return (sc_bigint<W0>(i0) <= sc_bigint<W1>(i1));
}
template <int T, int W0>
sc_lv<T> esl_trunc(const sc_lv<W0>& i0) {
assert(T <= W0);
return (i0.range(T-1, 0));
}
template <int T, int W0>
sc_lv<T> esl_sext(const sc_lv<W0>& i0) {
assert(T >= W0);
if (!i0.is_01()) return sc_lv<T>();
return ((sc_lv<T>)(sc_bigint<W0>(i0)));
}
template <int T, int W0>
sc_lv<T> esl_zext(const sc_lv<W0>& i0) {
assert(T >= W0);
if (!i0.is_01()) return sc_lv<T>();
return ((sc_lv<T>)(sc_biguint<W0>(i0)));
}
template <int T, int W0>
sc_lv<T> esl_bitcast(const sc_lv<W0>& i0) {
assert(T == W0);
return i0;
}
////////////////////////////////////////////////////////////////
// Conversions
////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////
// Logic/Arithmatic operations
////////////////////////////////////////////////////////////////
template <int T, int W0, int W1>
sc_lv<T> esl_and(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
assert(W0 == W1);
return (i0 & i1);
}
template <int T, int W0, int W1>
sc_lv<T> esl_or(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
assert(W0 == W1);
return (i0 | i1);
}
template <int T, int W0, int W1>
sc_lv<T> esl_xor(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
assert(W0 == W1);
return (i0 ^ i1);
}
template <int T, int W0, int W1>
sc_lv<T> esl_shl(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
//assert(W1 <= 32);
if (!i1.is_01()) return sc_lv<T>();
return (i0 << (unsigned short)i1.to_uint());
}
template <int T, int W0, int W1>
sc_lv<T> esl_lshr(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
//assert(W1 <= 32);
if (!i1.is_01()) return sc_lv<T>();
return (i0 >> (unsigned short)i1.to_uint());
}
template <int T, int W0, int W1>
sc_lv<T> esl_ashr(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
//assert(W1 <= 32);
if (!i0.is_01() || !i1.is_01()) return sc_lv<T>();
return (sc_bigint<W0>(i0) >> (unsigned short)i1.to_uint());
}
template <int T, int W0, int W1>
sc_lv<T> esl_add(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
if (!i0.is_01() || !i1.is_01()) return sc_lv<T>();
return (sc_bigint<W0>(i0) + sc_biguint<W1>(i1));
}
template <int T, int W0, int W1>
sc_lv<T> esl_sub(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
if (!i0.is_01() || !i1.is_01()) return sc_lv<T>();
return (sc_bigint<W0>(i0) - sc_biguint<W1>(i1));
}
template <int T, int W0, int W1>
sc_lv<T> esl_mul_UU(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
if (!i0.is_01() || !i1.is_01()) return sc_lv<T>();
return (sc_biguint<W0>(i0) * sc_biguint<W1>(i1));
}
template <int T, int W0, int W1>
sc_lv<T> esl_mul_SU(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
if (!i0.is_01() || !i1.is_01()) return sc_lv<T>();
return (sc_bigint<W0>(i0) * sc_biguint<W1>(i1));
}
template <int T, int W0, int W1>
sc_lv<T> esl_mul_US(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
if (!i0.is_01() || !i1.is_01()) return sc_lv<T>();
return (sc_biguint<W0>(i0) * sc_bigint<W1>(i1));
}
template <int T, int W0, int W1>
sc_lv<T> esl_mul_SS(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
if (!i0.is_01() || !i1.is_01()) return sc_lv<T>();
return (sc_bigint<W0>(i0) * sc_bigint<W1>(i1));
}
template <int T, int W0, int W1>
sc_lv<T> esl_udiv(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
if (!i0.is_01() || !i1.is_01()) return sc_lv<T>();
sc_biguint<W1> v1(i1);
if (v1.to_uint() == 0) return sc_lv<T>();
return (sc_biguint<W0>(i0) / v1);
}
template <int T, int W0, int W1>
sc_lv<T> esl_sdiv(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
if (!i0.is_01() || !i1.is_01()) return sc_lv<T>();
sc_bigint<W1> v1(i1);
if (v1.to_uint() == 0) return sc_lv<T>();
return (sc_bigint<W0>(i0) / v1);
}
template <int T, int W0, int W1>
sc_lv<T> esl_urem(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
if (!i0.is_01() || !i1.is_01()) return sc_lv<T>();
sc_biguint<W1> v1(i1);
if (v1.to_uint() == 0) return sc_lv<T>();
return (sc_biguint<W0>(i0) % v1);
}
template <int T, int W0, int W1>
sc_lv<T> esl_srem(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
if (!i0.is_01() || !i1.is_01()) return sc_lv<T>();
sc_bigint<W1> v1(i1);
if (v1.to_uint() == 0) return sc_lv<T>();
return (sc_bigint<W0>(i0) % v1);
}
template <int T, int W0>
sc_lv<T> esl_ctlz(const sc_lv<W0>& i0) {
int count = 0;
for (unsigned i = W0-1; i >= 0; --i) {
if (i0[i] == SC_LOGIC_0) count ++;
else break;
}
return count;
}
template <int T, int W0>
sc_lv<T> esl_cttz(const sc_lv<W0>& i0) {
int count = 0;
for (unsigned i = 0; i < W0; ++i) {
if (i0[i] == SC_LOGIC_0) count ++;
else break;
}
return count;
}
////////////////////////////////////////////////////////////////
// Other operations
////////////////////////////////////////////////////////////////
template <int T, int W0, int W1, int W2>
sc_lv<T> esl_select(const sc_lv<W0>& i0,
const sc_lv<W1>& i1, const sc_lv<W2>& i2) {
assert((W0 == 1) && (W1 == W2));
if (!i0[0].is_01()) return sc_lv<T>();
bool flag = (i0[0].to_bool());
return (flag ? i1 : i2);
}
template <int W0, int W1>
inline sc_lv<W0+W1> esl_concat(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
return (i0, i1);
}
template <int T, int W0, int W1>
inline sc_lv<T> esl_bitselect(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
assert(T == 1);
if (!i1.is_01()) return sc_lv<T>();
unsigned int loc = (sc_biguint<W1>(i1)).to_uint();
//assert(W0 >= loc);
if (W0 <= loc)
return sc_lv<T>();
return i0.range(loc, loc);
}
template <int T, int W0, int W1, int W2>
inline sc_lv<T> esl_bitset(const sc_lv<W0>& i0,
const sc_lv<W1>& i1, const sc_lv<W2>& i2) {
assert(T == W0);
if (!i1.is_01()) return sc_lv<T>();
unsigned int loc = (sc_biguint<W1>(i1)).to_uint();
//assert(W0 >= loc);
if (W0 <= loc)
return sc_lv<T>();
sc_lv<W0> res = i0;
res[loc] = i2.or_reduce();
return res;
}
template <int T, int W0, int W1, int W2>
inline sc_lv<T> esl_partselect(const sc_lv<W0>& i0,
const sc_lv<W1>& iLo, const sc_lv<W2>& iHi) {
if (!iLo.is_01() || !iHi.is_01()) return sc_lv<T>();
unsigned int Lo = (sc_biguint<W1>(iLo)).to_uint();
unsigned int Hi = (sc_biguint<W2>(iHi)).to_uint();
unsigned int rsize = abs((int)(Hi-Lo)) + 1;
// Warning out the dont-care situation.
if (Lo >= W0 || Hi >= W0) {
// std::cout << "Warning: partselect out of range!\n";
return sc_lv<T>();
}
assert(W0 >= rsize);
return i0.range(Hi, Lo);
}
template <int T, int W0, int W1, int WLo, int WHi>
inline sc_lv<T> esl_partset(const sc_lv<W0>& i0,
const sc_lv<W1>& i1,
const sc_lv<WLo>& iLo, const sc_lv<WHi>& iHi) {
if (!iLo.is_01() || !iHi.is_01()) return sc_lv<T>();
assert(W0 == T);
unsigned int Lo = (sc_biguint<WLo>(iLo)).to_uint();
unsigned int Hi = (sc_biguint<WHi>(iHi)).to_uint();
unsigned int rsize = abs((int)(Lo-Hi)) + 1;
// Warning out the dont-care situation.
if (Hi >= T || Lo >= T) {
// std::cout << "Warning: partset out of range!\n";
return sc_lv<T>();
}
assert(W0 >= rsize);
sc_lv<T> res = i0;
res.range(Hi, Lo) = ((sc_lv<T>)i1).range(rsize-1, 0);
return res;
}
template <int T, int W0>
sc_lv<T> esl_orreduce(const sc_lv<W0>& i0) {
assert(T == 1);
sc_lv<1> res;
res[0] = i0.or_reduce();
return res;
}
template <int T, int W0>
inline sc_lv<T> esl_andreduce(const sc_lv<W0>& i0) {
assert(T == 1);
sc_lv<1> res;
res[0] = i0.and_reduce();
return res;
}
template <int T, int W0>
inline sc_lv<T> esl_xorreduce(const sc_lv<W0>& i0) {
assert(T == 1);
sc_lv<1> res;
res[0] = i0.xor_reduce();
return res;
}
template <int T, int W0>
inline sc_lv<T> esl_nandreduce(const sc_lv<W0>& i0) {
assert(T == 1);
sc_lv<1> res;
res[0] = i0.nand_reduce();
return res;
}
template <int T, int W0>
inline sc_lv<T> esl_xnorreduce(const sc_lv<W0>& i0) {
assert(T == 1);
sc_lv<1> res;
res[0] = i0.xnor_reduce();
return res;
}
template <int T, int W0>
inline sc_lv<T> esl_norreduce(const sc_lv<W0>& i0) {
assert(T == 1);
sc_lv<1> res;
res[0] = i0.nor_reduce();
return res;
}
////////////////////////////////////////////////////////////////
// Floating point operations
////////////////////////////////////////////////////////////////
struct esl_FP {
static float esl_INTSP(unsigned int x) { return (*(float*)(&(x))); }
static double esl_INTDP(unsigned long long x) { return (*(double*)(&(x))); }
static unsigned int esl_SPINT(float x) { return (*(unsigned int*)(&(x))); }
static unsigned long long esl_DPINT(double x) { return (*(unsigned long long*)(&(x))); }
};
#define esl_LVSP(x) esl_FP::esl_INTSP((x).to_uint())
#define esl_LVDP(x) esl_FP::esl_INTDP((x).to_uint64())
#define esl_sitodp(lv) esl_FP::esl_DPINT(double((lv).to_int()))
#define esl_dptosi(lv) (int(esl_LVDP(lv)))
#define esl_dadd(x, y) \
esl_FP::esl_DPINT(esl_LVDP(x) + esl_LVDP(y))
#define esl_fadd(x, y) \
esl_FP::esl_SPINT(esl_LVSP(x) + esl_LVSP(y))
#define esl_dsub(x, y) \
esl_FP::esl_DPINT(esl_LVDP(x) - esl_LVDP(y))
#define esl_fsub(x, y) \
esl_FP::esl_SPINT(esl_LVSP(x) - esl_LVSP(y))
#define esl_dmul(x, y) \
esl_FP::esl_DPINT(esl_LVDP(x) * esl_LVDP(y))
#define esl_fmul(x, y) \
esl_FP::esl_SPINT(esl_LVSP(x) * esl_LVSP(y))
#define esl_ddiv(x, y) \
esl_FP::esl_DPINT(esl_LVDP(x) / esl_LVDP(y))
#define esl_fdiv(x, y) \
esl_FP::esl_SPINT(esl_LVSP(x) / esl_LVSP(y))
#define esl_drem(x, y) \
esl_FP::esl_DPINT(esl_LVDP(x) % esl_LVDP(y))
#define esl_frem(x, y) \
esl_FP::esl_SPINT(esl_LVSP(x) % esl_LVSP(y))
//#define esl_dsqrt(x) esl_FP::esl_DPINT(sqrt(esl_LVDP(x)))
//#define esl_fsqrt(x) esl_FP::esl_SPINT(sqrt(esl_LVSP(x)))
#define esl_DFCMP_FALSE(x, y) \
(false)
#define esl_DFCMP_ORD(x, y) \
(!isnan(esl_LVDP(x)) & !isnan(esl_LVDP(y)))
#define esl_DFCMP_OEQ(x, y) \
(esl_DFCMP_ORD(x, y) & (esl_LVDP(x) == esl_LVDP(y)))
#define esl_DFCMP_OGT(x, y) \
(esl_DFCMP_ORD(x, y) & (esl_LVDP(x) > esl_LVDP(y)))
#define esl_DFCMP_OGE(x, y) \
(esl_DFCMP_ORD(x, y) & (esl_LVDP(x) >= esl_LVDP(y)))
#define esl_DFCMP_OLT(x, y) \
(esl_DFCMP_ORD(x, y) & (esl_LVDP(x) < esl_LVDP(y)))
#define esl_DFCMP_OLE(x, y) \
(esl_DFCMP_ORD(x, y) & (esl_LVDP(x) <= esl_LVDP(y)))
#define esl_DFCMP_ONE(x, y) \
(esl_DFCMP_UNO(x, y) & (esl_LVDP(x) != esl_LVDP(y)))
#define esl_DFCMP_UNO(x, y) \
(isnan(esl_LVDP(x)) | isnan(esl_LVDP(y)))
#define esl_DFCMP_UEQ(x, y) \
(esl_DFCMP_UNO(x, y) | (esl_LVDP(x) == esl_LVDP(y)))
#define esl_DFCMP_UGT(x, y) \
(esl_DFCMP_UNO(x, y) | (esl_LVDP(x) > esl_LVDP(y)))
#define esl_DFCMP_UGE(x, y) \
(esl_DFCMP_UNO(x, y) | (esl_LVDP(x) >= esl_LVDP(y)))
#define esl_DFCMP_ULT(x, y) \
(esl_DFCMP_UNO(x, y) | (esl_LVDP(x) < esl_LVDP(y)))
#define esl_DFCMP_ULE(x, y) \
(esl_DFCMP_UNO(x, y) | (esl_LVDP(x) <= esl_LVDP(y)))
#define esl_DFCMP_UNE(x, y) \
(esl_DFCMP_UNO(x, y) | (esl_LVDP(x) != esl_LVDP(y)))
#define esl_DFCMP_TRUE(x, y) \
(true)
template <int T, int W0>
sc_lv<T> esl_dsqrt(const sc_lv<W0>& x) {
sc_lv<T> ret = esl_FP::esl_DPINT(sqrt(esl_LVDP(x)));
return ret;
}
template <int T, int W0>
sc_lv<T> esl_fsqrt(const sc_lv<W0>& x) {
sc_lv<T> ret = esl_FP::esl_SPINT(sqrt(esl_LVSP(x)));
return ret;
}
template <int T, int W0, int W1>
sc_lv<T> esl_getelementptr(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
return esl_add<T, W0, W1>(i0, i1);
}
}
#endif
// XSIP watermark, do not delete 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.2
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
#ifndef AESL_PKG_HH
#define AESL_PKG_HH
#include "systemc.h"
namespace ap_rtl {
////////////////////////////////////////////////////////////////
// Comparisons
////////////////////////////////////////////////////////////////
template <int T, int W0, int W1>
bool esl_seteq(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
assert(W0>=1 && W1>=1);
if (W0 > W1)
return (i0.range(W1-1, 0) == i1);
else
return (i1.range(W0-1, 0) == i0);
assert(W0 == W1);
return (i0 == i1);
}
template <int T, int W0, int W1>
bool esl_setne(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
assert(W0>=1 && W1>=1);
if (W0 > W1)
return (i0.range(W1-1, 0) != i1);
else
return (i1.range(W0-1, 0) != i0);
assert(W0 == W1);
return (i0 != i1);
}
template <int T, int W0, int W1>
bool esl_seteq(const sc_logic& i0, const sc_logic& i1) {
assert(W0 == W1);
return (i0 == i1);
}
template <int T, int W0, int W1>
bool esl_setne(const sc_logic& i0, const sc_logic& i1) {
assert(W0 == W1);
return (i0 != i1);
}
template <int T, int W0>
bool esl_not(bool i0) {
return (!i0);
}
template <int T, int W0>
sc_logic esl_not(const sc_logic& i0) {
return (~i0);
}
template <int T, int W0, int W1>
bool esl_setle(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
if (!i0.is_01() || !i1.is_01()) return false;
return (sc_biguint<W0>(i0) <= sc_biguint<W1>(i1));
}
template <int T, int W0, int W1>
bool esl_setge(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
if (!i0.is_01() || !i1.is_01()) return false;
return (sc_biguint<W0>(i0) >= sc_biguint<W1>(i1));
}
template <int T, int W0, int W1>
bool esl_setlt(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
if (!i0.is_01() || !i1.is_01()) return false;
return (sc_biguint<W0>(i0) < sc_biguint<W1>(i1));
}
template <int T, int W0, int W1>
bool esl_setgt(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
if (!i0.is_01() || !i1.is_01()) return false;
return (sc_biguint<W0>(i0) > sc_biguint<W1>(i1));
}
template <int T, int W0, int W1>
sc_lv<1> esl_icmp_eq(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
assert(W0 == W1);
if (!i0.is_01() || !i1.is_01()) return sc_lv<1>();
return sc_lv<1>(i0 == i1);
}
template <int T, int W0, int W1>
sc_lv<1> esl_icmp_ne(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
assert(W0 == W1);
if (!i0.is_01() || !i1.is_01()) return sc_lv<1>();
return sc_lv<1>(i0 != i1);
}
template <int T, int W0, int W1>
sc_lv<1> esl_icmp_ugt(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
if (!i0.is_01() || !i1.is_01()) return sc_lv<1>();
return (sc_biguint<W0>(i0) > sc_biguint<W1>(i1));
}
template <int T, int W0, int W1>
sc_lv<1> esl_icmp_uge(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
if (!i0.is_01() || !i1.is_01()) return sc_lv<1>();
return (sc_biguint<W0>(i0) >= sc_biguint<W1>(i1));
}
template <int T, int W0, int W1>
sc_lv<1> esl_icmp_ult(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
if (!i0.is_01() || !i1.is_01()) return sc_lv<1>();
return (sc_biguint<W0>(i0) < sc_biguint<W1>(i1));
}
template <int T, int W0, int W1>
sc_lv<1> esl_icmp_ule(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
if (!i0.is_01() || !i1.is_01()) return sc_lv<1>();
return (sc_biguint<W0>(i0) <= sc_biguint<W1>(i1));
}
template <int T, int W0, int W1>
sc_lv<1> esl_icmp_sgt(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
if (!i0.is_01() || !i1.is_01()) return sc_lv<1>();
return (sc_bigint<W0>(i0) > sc_bigint<W1>(i1));
}
template <int T, int W0, int W1>
sc_lv<1> esl_icmp_sge(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
if (!i0.is_01() || !i1.is_01()) return sc_lv<1>();
return (sc_bigint<W0>(i0) >= sc_bigint<W1>(i1));
}
template <int T, int W0, int W1>
sc_lv<1> esl_icmp_slt(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
if (!i0.is_01() || !i1.is_01()) return sc_lv<1>();
return (sc_bigint<W0>(i0) < sc_bigint<W1>(i1));
}
template <int T, int W0, int W1>
sc_lv<1> esl_icmp_sle(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
if (!i0.is_01() || !i1.is_01()) return sc_lv<1>();
return (sc_bigint<W0>(i0) <= sc_bigint<W1>(i1));
}
template <int T, int W0>
sc_lv<T> esl_trunc(const sc_lv<W0>& i0) {
assert(T <= W0);
return (i0.range(T-1, 0));
}
template <int T, int W0>
sc_lv<T> esl_sext(const sc_lv<W0>& i0) {
assert(T >= W0);
if (!i0.is_01()) return sc_lv<T>();
return ((sc_lv<T>)(sc_bigint<W0>(i0)));
}
template <int T, int W0>
sc_lv<T> esl_zext(const sc_lv<W0>& i0) {
assert(T >= W0);
if (!i0.is_01()) return sc_lv<T>();
return ((sc_lv<T>)(sc_biguint<W0>(i0)));
}
template <int T, int W0>
sc_lv<T> esl_bitcast(const sc_lv<W0>& i0) {
assert(T == W0);
return i0;
}
////////////////////////////////////////////////////////////////
// Conversions
////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////
// Logic/Arithmatic operations
////////////////////////////////////////////////////////////////
template <int T, int W0, int W1>
sc_lv<T> esl_and(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
assert(W0 == W1);
return (i0 & i1);
}
template <int T, int W0, int W1>
sc_lv<T> esl_or(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
assert(W0 == W1);
return (i0 | i1);
}
template <int T, int W0, int W1>
sc_lv<T> esl_xor(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
assert(W0 == W1);
return (i0 ^ i1);
}
template <int T, int W0, int W1>
sc_lv<T> esl_shl(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
//assert(W1 <= 32);
if (!i1.is_01()) return sc_lv<T>();
return (i0 << (unsigned short)i1.to_uint());
}
template <int T, int W0, int W1>
sc_lv<T> esl_lshr(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
//assert(W1 <= 32);
if (!i1.is_01()) return sc_lv<T>();
return (i0 >> (unsigned short)i1.to_uint());
}
template <int T, int W0, int W1>
sc_lv<T> esl_ashr(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
//assert(W1 <= 32);
if (!i0.is_01() || !i1.is_01()) return sc_lv<T>();
return (sc_bigint<W0>(i0) >> (unsigned short)i1.to_uint());
}
template <int T, int W0, int W1>
sc_lv<T> esl_add(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
if (!i0.is_01() || !i1.is_01()) return sc_lv<T>();
return (sc_bigint<W0>(i0) + sc_biguint<W1>(i1));
}
template <int T, int W0, int W1>
sc_lv<T> esl_sub(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
if (!i0.is_01() || !i1.is_01()) return sc_lv<T>();
return (sc_bigint<W0>(i0) - sc_biguint<W1>(i1));
}
template <int T, int W0, int W1>
sc_lv<T> esl_mul_UU(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
if (!i0.is_01() || !i1.is_01()) return sc_lv<T>();
return (sc_biguint<W0>(i0) * sc_biguint<W1>(i1));
}
template <int T, int W0, int W1>
sc_lv<T> esl_mul_SU(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
if (!i0.is_01() || !i1.is_01()) return sc_lv<T>();
return (sc_bigint<W0>(i0) * sc_biguint<W1>(i1));
}
template <int T, int W0, int W1>
sc_lv<T> esl_mul_US(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
if (!i0.is_01() || !i1.is_01()) return sc_lv<T>();
return (sc_biguint<W0>(i0) * sc_bigint<W1>(i1));
}
template <int T, int W0, int W1>
sc_lv<T> esl_mul_SS(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
if (!i0.is_01() || !i1.is_01()) return sc_lv<T>();
return (sc_bigint<W0>(i0) * sc_bigint<W1>(i1));
}
template <int T, int W0, int W1>
sc_lv<T> esl_udiv(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
if (!i0.is_01() || !i1.is_01()) return sc_lv<T>();
sc_biguint<W1> v1(i1);
if (v1.to_uint() == 0) return sc_lv<T>();
return (sc_biguint<W0>(i0) / v1);
}
template <int T, int W0, int W1>
sc_lv<T> esl_sdiv(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
if (!i0.is_01() || !i1.is_01()) return sc_lv<T>();
sc_bigint<W1> v1(i1);
if (v1.to_uint() == 0) return sc_lv<T>();
return (sc_bigint<W0>(i0) / v1);
}
template <int T, int W0, int W1>
sc_lv<T> esl_urem(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
if (!i0.is_01() || !i1.is_01()) return sc_lv<T>();
sc_biguint<W1> v1(i1);
if (v1.to_uint() == 0) return sc_lv<T>();
return (sc_biguint<W0>(i0) % v1);
}
template <int T, int W0, int W1>
sc_lv<T> esl_srem(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
if (!i0.is_01() || !i1.is_01()) return sc_lv<T>();
sc_bigint<W1> v1(i1);
if (v1.to_uint() == 0) return sc_lv<T>();
return (sc_bigint<W0>(i0) % v1);
}
template <int T, int W0>
sc_lv<T> esl_ctlz(const sc_lv<W0>& i0) {
int count = 0;
for (unsigned i = W0-1; i >= 0; --i) {
if (i0[i] == SC_LOGIC_0) count ++;
else break;
}
return count;
}
template <int T, int W0>
sc_lv<T> esl_cttz(const sc_lv<W0>& i0) {
int count = 0;
for (unsigned i = 0; i < W0; ++i) {
if (i0[i] == SC_LOGIC_0) count ++;
else break;
}
return count;
}
////////////////////////////////////////////////////////////////
// Other operations
////////////////////////////////////////////////////////////////
template <int T, int W0, int W1, int W2>
sc_lv<T> esl_select(const sc_lv<W0>& i0,
const sc_lv<W1>& i1, const sc_lv<W2>& i2) {
assert((W0 == 1) && (W1 == W2));
if (!i0[0].is_01()) return sc_lv<T>();
bool flag = (i0[0].to_bool());
return (flag ? i1 : i2);
}
template <int W0, int W1>
inline sc_lv<W0+W1> esl_concat(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
return (i0, i1);
}
template <int T, int W0, int W1>
inline sc_lv<T> esl_bitselect(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
assert(T == 1);
if (!i1.is_01()) return sc_lv<T>();
unsigned int loc = (sc_biguint<W1>(i1)).to_uint();
//assert(W0 >= loc);
if (W0 <= loc)
return sc_lv<T>();
return i0.range(loc, loc);
}
template <int T, int W0, int W1, int W2>
inline sc_lv<T> esl_bitset(const sc_lv<W0>& i0,
const sc_lv<W1>& i1, const sc_lv<W2>& i2) {
assert(T == W0);
if (!i1.is_01()) return sc_lv<T>();
unsigned int loc = (sc_biguint<W1>(i1)).to_uint();
//assert(W0 >= loc);
if (W0 <= loc)
return sc_lv<T>();
sc_lv<W0> res = i0;
res[loc] = i2.or_reduce();
return res;
}
template <int T, int W0, int W1, int W2>
inline sc_lv<T> esl_partselect(const sc_lv<W0>& i0,
const sc_lv<W1>& iLo, const sc_lv<W2>& iHi) {
if (!iLo.is_01() || !iHi.is_01()) return sc_lv<T>();
unsigned int Lo = (sc_biguint<W1>(iLo)).to_uint();
unsigned int Hi = (sc_biguint<W2>(iHi)).to_uint();
unsigned int rsize = abs((int)(Hi-Lo)) + 1;
// Warning out the dont-care situation.
if (Lo >= W0 || Hi >= W0) {
// std::cout << "Warning: partselect out of range!\n";
return sc_lv<T>();
}
assert(W0 >= rsize);
return i0.range(Hi, Lo);
}
template <int T, int W0, int W1, int WLo, int WHi>
inline sc_lv<T> esl_partset(const sc_lv<W0>& i0,
const sc_lv<W1>& i1,
const sc_lv<WLo>& iLo, const sc_lv<WHi>& iHi) {
if (!iLo.is_01() || !iHi.is_01()) return sc_lv<T>();
assert(W0 == T);
unsigned int Lo = (sc_biguint<WLo>(iLo)).to_uint();
unsigned int Hi = (sc_biguint<WHi>(iHi)).to_uint();
unsigned int rsize = abs((int)(Lo-Hi)) + 1;
// Warning out the dont-care situation.
if (Hi >= T || Lo >= T) {
// std::cout << "Warning: partset out of range!\n";
return sc_lv<T>();
}
assert(W0 >= rsize);
sc_lv<T> res = i0;
res.range(Hi, Lo) = ((sc_lv<T>)i1).range(rsize-1, 0);
return res;
}
template <int T, int W0>
sc_lv<T> esl_orreduce(const sc_lv<W0>& i0) {
assert(T == 1);
sc_lv<1> res;
res[0] = i0.or_reduce();
return res;
}
template <int T, int W0>
inline sc_lv<T> esl_andreduce(const sc_lv<W0>& i0) {
assert(T == 1);
sc_lv<1> res;
res[0] = i0.and_reduce();
return res;
}
template <int T, int W0>
inline sc_lv<T> esl_xorreduce(const sc_lv<W0>& i0) {
assert(T == 1);
sc_lv<1> res;
res[0] = i0.xor_reduce();
return res;
}
template <int T, int W0>
inline sc_lv<T> esl_nandreduce(const sc_lv<W0>& i0) {
assert(T == 1);
sc_lv<1> res;
res[0] = i0.nand_reduce();
return res;
}
template <int T, int W0>
inline sc_lv<T> esl_xnorreduce(const sc_lv<W0>& i0) {
assert(T == 1);
sc_lv<1> res;
res[0] = i0.xnor_reduce();
return res;
}
template <int T, int W0>
inline sc_lv<T> esl_norreduce(const sc_lv<W0>& i0) {
assert(T == 1);
sc_lv<1> res;
res[0] = i0.nor_reduce();
return res;
}
////////////////////////////////////////////////////////////////
// Floating point operations
////////////////////////////////////////////////////////////////
struct esl_FP {
static float esl_INTSP(unsigned int x) { return (*(float*)(&(x))); }
static double esl_INTDP(unsigned long long x) { return (*(double*)(&(x))); }
static unsigned int esl_SPINT(float x) { return (*(unsigned int*)(&(x))); }
static unsigned long long esl_DPINT(double x) { return (*(unsigned long long*)(&(x))); }
};
#define esl_LVSP(x) esl_FP::esl_INTSP((x).to_uint())
#define esl_LVDP(x) esl_FP::esl_INTDP((x).to_uint64())
#define esl_sitodp(lv) esl_FP::esl_DPINT(double((lv).to_int()))
#define esl_dptosi(lv) (int(esl_LVDP(lv)))
#define esl_dadd(x, y) \
esl_FP::esl_DPINT(esl_LVDP(x) + esl_LVDP(y))
#define esl_fadd(x, y) \
esl_FP::esl_SPINT(esl_LVSP(x) + esl_LVSP(y))
#define esl_dsub(x, y) \
esl_FP::esl_DPINT(esl_LVDP(x) - esl_LVDP(y))
#define esl_fsub(x, y) \
esl_FP::esl_SPINT(esl_LVSP(x) - esl_LVSP(y))
#define esl_dmul(x, y) \
esl_FP::esl_DPINT(esl_LVDP(x) * esl_LVDP(y))
#define esl_fmul(x, y) \
esl_FP::esl_SPINT(esl_LVSP(x) * esl_LVSP(y))
#define esl_ddiv(x, y) \
esl_FP::esl_DPINT(esl_LVDP(x) / esl_LVDP(y))
#define esl_fdiv(x, y) \
esl_FP::esl_SPINT(esl_LVSP(x) / esl_LVSP(y))
#define esl_drem(x, y) \
esl_FP::esl_DPINT(esl_LVDP(x) % esl_LVDP(y))
#define esl_frem(x, y) \
esl_FP::esl_SPINT(esl_LVSP(x) % esl_LVSP(y))
//#define esl_dsqrt(x) esl_FP::esl_DPINT(sqrt(esl_LVDP(x)))
//#define esl_fsqrt(x) esl_FP::esl_SPINT(sqrt(esl_LVSP(x)))
#define esl_DFCMP_FALSE(x, y) \
(false)
#define esl_DFCMP_ORD(x, y) \
(!isnan(esl_LVDP(x)) & !isnan(esl_LVDP(y)))
#define esl_DFCMP_OEQ(x, y) \
(esl_DFCMP_ORD(x, y) & (esl_LVDP(x) == esl_LVDP(y)))
#define esl_DFCMP_OGT(x, y) \
(esl_DFCMP_ORD(x, y) & (esl_LVDP(x) > esl_LVDP(y)))
#define esl_DFCMP_OGE(x, y) \
(esl_DFCMP_ORD(x, y) & (esl_LVDP(x) >= esl_LVDP(y)))
#define esl_DFCMP_OLT(x, y) \
(esl_DFCMP_ORD(x, y) & (esl_LVDP(x) < esl_LVDP(y)))
#define esl_DFCMP_OLE(x, y) \
(esl_DFCMP_ORD(x, y) & (esl_LVDP(x) <= esl_LVDP(y)))
#define esl_DFCMP_ONE(x, y) \
(esl_DFCMP_UNO(x, y) & (esl_LVDP(x) != esl_LVDP(y)))
#define esl_DFCMP_UNO(x, y) \
(isnan(esl_LVDP(x)) | isnan(esl_LVDP(y)))
#define esl_DFCMP_UEQ(x, y) \
(esl_DFCMP_UNO(x, y) | (esl_LVDP(x) == esl_LVDP(y)))
#define esl_DFCMP_UGT(x, y) \
(esl_DFCMP_UNO(x, y) | (esl_LVDP(x) > esl_LVDP(y)))
#define esl_DFCMP_UGE(x, y) \
(esl_DFCMP_UNO(x, y) | (esl_LVDP(x) >= esl_LVDP(y)))
#define esl_DFCMP_ULT(x, y) \
(esl_DFCMP_UNO(x, y) | (esl_LVDP(x) < esl_LVDP(y)))
#define esl_DFCMP_ULE(x, y) \
(esl_DFCMP_UNO(x, y) | (esl_LVDP(x) <= esl_LVDP(y)))
#define esl_DFCMP_UNE(x, y) \
(esl_DFCMP_UNO(x, y) | (esl_LVDP(x) != esl_LVDP(y)))
#define esl_DFCMP_TRUE(x, y) \
(true)
template <int T, int W0>
sc_lv<T> esl_dsqrt(const sc_lv<W0>& x) {
sc_lv<T> ret = esl_FP::esl_DPINT(sqrt(esl_LVDP(x)));
return ret;
}
template <int T, int W0>
sc_lv<T> esl_fsqrt(const sc_lv<W0>& x) {
sc_lv<T> ret = esl_FP::esl_SPINT(sqrt(esl_LVSP(x)));
return ret;
}
template <int T, int W0, int W1>
sc_lv<T> esl_getelementptr(const sc_lv<W0>& i0, const sc_lv<W1>& i1) {
return esl_add<T, W0, W1>(i0, i1);
}
}
#endif
// XSIP watermark, do not delete 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2017 Cadence Design Systems, Inc. All rights reserved worldwide.
//
// The code contained herein is the proprietary and confidential information
// of Cadence or its licensors, and is supplied subject to a previously
// executed license and maintenance agreement between Cadence and customer.
// This code is intended for use with Cadence high-level synthesis tools and
// may not be used with other high-level synthesis tools. Permission is only
// granted to distribute the code as indicated. Cadence grants permission for
// customer to distribute a copy of this code to any partner to aid in designing
// or verifying the customer's intellectual property, as long as such
// distribution includes a restriction of no additional distributions from the
// partner, unless the partner receives permission directly from Cadence.
//
// ALL CODE FURNISHED BY CADENCE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY
// KIND, AND CADENCE SPECIFICALLY DISCLAIMS ANY WARRANTY OF NONINFRINGEMENT,
// FITNESS FOR A PARTICULAR PURPOSE OR MERCHANTABILITY. CADENCE SHALL NOT BE
// LIABLE FOR ANY COSTS OF PROCUREMENT OF SUBSTITUTES, LOSS OF PROFITS,
// INTERRUPTION OF BUSINESS, OR FOR ANY OTHER SPECIAL, CONSEQUENTIAL OR
// INCIDENTAL DAMAGES, HOWEVER CAUSED, WHETHER FOR BREACH OF WARRANTY,
// CONTRACT, TORT, NEGLIGENCE, STRICT LIABILITY OR OTHERWISE.
//
////////////////////////////////////////////////////////////////////////////////
#include <systemc.h> // SystemC definitions
#include "system.h" // System module definition
// The pointer that holds the top-level System module instance.
static System * m_system = NULL;
// This function is required by Stratus to support
// SystemC-Verilog co-simulation. This is where an instance of the
// top-level module should be created.
void esc_elaborate()
{
m_system = new System( "system" );
}
// This function is called at the end of simulation by the
// Stratus co-simulation hub. It should delete the top-level
// module instance.
void esc_cleanup()
{
delete m_system;
}
// This function is called by the SystemC kernel for pure SystemC
// simulations.
int sc_main( int argc, char ** argv )
{
// First, we call the esc_initialize function, passing in
// the simulation command-line arguments. This function initializes
// the Stratus simulation environment (such as opening report
// files for later logging and analysis).
esc_initialize( argc, argv );
// Next, we call the esc_elaborate function (defined above)
// which creates the top-level module instance. In a SystemC-Verilog
// co-simulation, the esc_elaborate function is called by the
// simulator during initialization of the co_simulation rather
// than from sc_main.
esc_elaborate();
// Start the simulation. When this function returns, the simulation
// is finished. A simulation is finished when some module (e.g. the
// testbench) calls the esc_stop() function.
sc_start();
// The esc_cleanup function defined above will be automatically
// called before sc_start returns. It should delete the top-level
// module and perform any other cleanup as needed.
return 0; // return status of the simulation.
}
|
#include <systemc.h>
SC_MODULE(nand_gate) {
public:
sc_in<bool> inp_a, inp_b;
sc_out<bool> out;
SC_HAS_PROCESS(nand_gate);
nand_gate(sc_module_name nm);
private:
void nand_main(void);
};
|
#include <systemc.h>
SC_MODULE(nand_gate) {
public:
sc_in<bool> inp_a, inp_b;
sc_out<bool> out;
SC_HAS_PROCESS(nand_gate);
nand_gate(sc_module_name nm);
private:
void nand_main(void);
};
|
#include <systemc.h>
SC_MODULE(nand_gate) {
public:
sc_in<bool> inp_a, inp_b;
sc_out<bool> out;
SC_HAS_PROCESS(nand_gate);
nand_gate(sc_module_name nm);
private:
void nand_main(void);
};
|
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD and is protected under U.S. and international copyright
// and other intellectual property laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// AMD, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) AMD shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or AMD had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// AMD products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of AMD products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
#ifndef _icyradio_VCC_1_1_H_
#define _icyradio_VCC_1_1_H_
#include "xlconstant_v1_1_8.h"
#include "systemc.h"
class icyradio_VCC_1_1 : public sc_module {
public:
xlconstant_v1_1_8<1,1> mod;
sc_out< sc_bv<1> > dout;
icyradio_VCC_1_1 (sc_core::sc_module_name name);
};
#endif
|
/*****************************************************************************
Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
more contributor license agreements. See the NOTICE file distributed
with this work for additional information regarding copyright ownership.
Accellera licenses this file to you under the Apache License, Version 2.0
(the "License"); you may not use this file except in compliance with the
License. You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
implied. See the License for the specific language governing
permissions and limitations under the License.
****************************************************************************/
/**
* @file systemc.h
* @brief include SystemC from within the CCI library
* @author Thomas Goodfellow, OFFIS
* @author Philipp A. Hartmann, OFFIS/Intel
*
* This file provides a local indirection to include SystemC from within
* the CCI library. Prefer this file over direct inclusion of the SystemC
* header inside the CCI implementation(s).
*
* Some features not yet present in some (supported) versions of SystemC
* may require local workarounds, e.g. @ref sc_core::sc_get_current_object()
* (added in SystemC 2.3.1).
*
*/
#ifndef CCI_CORE_SYSTEMC_H_INCLUDED_
#define CCI_CORE_SYSTEMC_H_INCLUDED_
#if defined(_MSC_VER)
#pragma warning( push )
#pragma warning( disable: 4244 )
#pragma warning( disable: 4267 )
#endif
// Required by CCI callback mechanism using sc_unnamed bind argument
#ifndef SC_INCLUDE_DYNAMIC_PROCESSES
# define SC_INCLUDE_DYNAMIC_PROCESSES
#endif
#include <systemc>
#if defined(_MSC_VER)
#pragma warning( pop )
#endif
#ifdef SC_VERSION_HELPER_
# define CCI_VERSION_HELPER_ \
SC_VERSION_HELPER_
# else
# define CCI_VERSION_HELPER_(Major,Minor,Patch) \
(((Major)*100000) + ((Minor)*100) + (Patch))
#endif
#ifdef SC_VERSION_CODE
# define CCI_SYSTEMC_VERSION_CODE_ \
SC_VERSION_CODE
#elif defined(IEEE_1666_SYSTEMC)
# define CCI_SYSTEMC_VERSION_CODE_ \
CCI_VERSION_HELPER_( SC_VERSION_MAJOR \
, SC_VERSION_MINOR \
, SC_VERSION_PATCH )
#else // pre 1666-2011
// assume 2.2.0 for now, eventually guess from SYSTEMC_VERSION (date)
# define CCI_SYSTEMC_VERSION_CODE_ \
CCI_VERSION_HELPER_(2,2,0)
#endif // CCI_SYSTEMC_VERSION_CODE_
// sc_core::sc_get_current_object()
#if CCI_SYSTEMC_VERSION_CODE_ < CCI_VERSION_HELPER_(2,3,1)
namespace sc_core {
inline sc_object* sc_get_current_object()
{
struct dummy_object : sc_object {} dummy;
return dummy.get_parent_object();
}
} // namespace sc_core
#endif // sc_core::sc_get_current_object
#endif // CCI_CORE_SYSTEMC_H_INCLUDED_
|
//
// Copyright 2022 Sergey Khabarov, [email protected]
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
#pragma once
#include <systemc.h>
#include "../river_cfg.h"
#include "icache_lru.h"
#include "dcache_lru.h"
#include "pma.h"
#include "pmp.h"
#include "../core/queue.h"
namespace debugger {
SC_MODULE(CacheTop) {
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
// Control path:
sc_in<bool> i_req_ctrl_valid; // Control request from CPU Core is valid
sc_in<sc_uint<RISCV_ARCH>> i_req_ctrl_addr; // Control request address
sc_out<bool> o_req_ctrl_ready; // Control request from CPU Core is accepted
sc_out<bool> o_resp_ctrl_valid; // ICache response is valid and can be accepted
sc_out<sc_uint<RISCV_ARCH>> o_resp_ctrl_addr; // ICache response address
sc_out<sc_uint<64>> o_resp_ctrl_data; // ICache read data
sc_out<bool> o_resp_ctrl_load_fault; // Bus response ERRSLV or ERRDEC on read
sc_in<bool> i_resp_ctrl_ready; // CPU Core is ready to accept ICache response
// Data path:
sc_in<bool> i_req_data_valid; // Data path request from CPU Core is valid
sc_in<sc_uint<MemopType_Total>> i_req_data_type; // Data write memopy operation flag
sc_in<sc_uint<RISCV_ARCH>> i_req_data_addr; // Memory operation address
sc_in<sc_uint<64>> i_req_data_wdata; // Memory operation write value
sc_in<sc_uint<8>> i_req_data_wstrb; // 8-bytes aligned strob
sc_in<sc_uint<2>> i_req_data_size;
sc_out<bool> o_req_data_ready; // Memory operation request accepted by DCache
sc_out<bool> o_resp_data_valid; // DCache response is ready
sc_out<sc_uint<RISCV_ARCH>> o_resp_data_addr; // DCache response address
sc_out<sc_uint<64>> o_resp_data_data; // DCache response read data
sc_out<bool> o_resp_data_load_fault; // Bus response ERRSLV or ERRDEC on read
sc_out<bool> o_resp_data_store_fault; // Bus response ERRSLV or ERRDEC on write
sc_in<bool> i_resp_data_ready; // CPU Core is ready to accept DCache repsonse
// Memory interface:
sc_in<bool> i_req_mem_ready; // System Bus is ready to accept memory operation request
sc_out<bool> o_req_mem_path; // 1=ctrl; 0=data path
sc_out<bool> o_req_mem_valid; // AXI memory request is valid
sc_out<sc_uint<REQ_MEM_TYPE_BITS>> o_req_mem_type; // AXI memory request type
sc_out<sc_uint<3>> o_req_mem_size; // request size: 0=1 B;...; 7=128 B
sc_out<sc_uint<CFG_CPU_ADDR_BITS>> o_req_mem_addr; // AXI memory request address
sc_out<sc_uint<L1CACHE_BYTES_PER_LINE>> o_req_mem_strob;// Writing strob. 1 bit per Byte (uncached only)
sc_out<sc_biguint<L1CACHE_LINE_BITS>> o_req_mem_data; // Writing data
sc_in<bool> i_resp_mem_valid; // AXI response is valid
sc_in<bool> i_resp_mem_path; // 0=ctrl; 1=data path
sc_in<sc_biguint<L1CACHE_LINE_BITS>> i_resp_mem_data; // Read data
sc_in<bool> i_resp_mem_load_fault; // data load error
sc_in<bool> i_resp_mem_store_fault; // data store error
// PMP interface:
sc_in<bool> i_pmp_ena; // PMP is active in S or U modes or if L/MPRV bit is set in M-mode
sc_in<bool> i_pmp_we; // write enable into PMP
sc_in<sc_uint<CFG_PMP_TBL_WIDTH>> i_pmp_region; // selected PMP region
sc_in<sc_uint<RISCV_ARCH>> i_pmp_start_addr; // PMP region start address
sc_in<sc_uint<RISCV_ARCH>> i_pmp_end_addr; // PMP region end address (inclusive)
sc_in<sc_uint<CFG_PMP_FL_TOTAL>> i_pmp_flags; // {ena, lock, r, w, x}
// $D Snoop interface:
sc_in<bool> i_req_snoop_valid;
sc_in<sc_uint<SNOOP_REQ_TYPE_BITS>> i_req_snoop_type;
sc_out<bool> o_req_snoop_ready;
sc_in<sc_uint<CFG_CPU_ADDR_BITS>> i_req_snoop_addr;
sc_in<bool> i_resp_snoop_ready;
sc_out<bool> o_resp_snoop_valid;
sc_out<sc_biguint<L1CACHE_LINE_BITS>> o_resp_snoop_data;
sc_out<sc_uint<DTAG_FL_TOTAL>> o_resp_snoop_flags;
// Debug signals:
sc_in<bool> i_flushi_valid; // address to clear icache is valid
sc_in<sc_uint<RISCV_ARCH>> i_flushi_addr; // clear ICache address from debug interface
sc_in<bool> i_flushd_valid;
sc_in<sc_uint<RISCV_ARCH>> i_flushd_addr;
sc_out<bool> o_flushd_end;
void comb();
SC_HAS_PROCESS(CacheTop);
CacheTop(sc_module_name name,
bool async_reset,
bool coherence_ena);
virtual ~CacheTop();
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
bool async_reset_;
bool coherence_ena_;
static const int DATA_PATH = 0;
static const int CTRL_PATH = 1;
static const int QUEUE_WIDTH = (CFG_CPU_ADDR_BITS // o_req_mem_addr
+ REQ_MEM_TYPE_BITS // o_req_mem_type
+ 3 // o_req_mem_size
+ 1 // i_resp_mem_path
);
struct CacheOutputType {
sc_signal<bool> req_mem_valid;
sc_signal<sc_uint<REQ_MEM_TYPE_BITS>> req_mem_type;
sc_signal<sc_uint<3>> req_mem_size;
sc_signal<sc_uint<CFG_CPU_ADDR_BITS>> req_mem_addr;
sc_signal<sc_uint<L1CACHE_BYTES_PER_LINE>> req_mem_strob;
sc_signal<sc_biguint<L1CACHE_LINE_BITS>> req_mem_wdata;
sc_signal<sc_uint<CFG_CPU_ADDR_BITS>> mpu_addr;
sc_signal<sc_uint<CFG_CPU_ADDR_BITS>> resp_addr;
};
sc_signal<sc_uint<CFG_CPU_ADDR_BITS>> wb_i_req_ctrl_addr;
sc_signal<sc_uint<CFG_CPU_ADDR_BITS>> wb_i_req_data_addr;
sc_signal<sc_uint<CFG_CPU_ADDR_BITS>> wb_i_flushi_addr;
sc_signal<sc_uint<CFG_CPU_ADDR_BITS>> wb_i_flushd_addr;
CacheOutputType i;
CacheOutputType d;
// Memory Control interface:
sc_signal<bool> w_ctrl_resp_mem_data_valid;
sc_signal<sc_biguint<L1CACHE_LINE_BITS>> wb_ctrl_resp_mem_data;
sc_signal<bool> w_ctrl_resp_mem_load_fault;
sc_signal<bool> w_ctrl_req_ready;
// Memory Data interface:
sc_signal<bool> w_data_resp_mem_data_valid;
sc_signal<sc_biguint<L1CACHE_LINE_BITS>> wb_data_resp_mem_data;
sc_signal<bool> w_data_resp_mem_load_fault;
sc_signal<bool> w_data_req_ready;
sc_signal<bool> w_pma_icached;
sc_signal<bool> w_pma_dcached;
sc_signal<bool> w_pmp_r;
sc_signal<bool> w_pmp_w;
sc_signal<bool> w_pmp_x;
// Queue interface
sc_signal<bool> queue_re_i;
sc_signal<bool> queue_we_i;
sc_signal<sc_biguint<QUEUE_WIDTH>> queue_wdata_i;
sc_signal<sc_biguint<QUEUE_WIDTH>> queue_rdata_o;
sc_signal<bool> queue_full_o;
sc_signal<bool> queue_nempty_o;
ICacheLru *i1;
DCacheLru *d0;
PMA *pma0;
PMP *pmp0;
Queue<2, QUEUE_WIDTH> *queue0;
};
} // namespace debugger
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ===========================================================
#ifndef _sparse_mm_HH_
#define _sparse_mm_HH_
#include "systemc.h"
#include "AESL_pkg.h"
#include "sparse_mm_mul_32s_32s_32_3.h"
#include "sparse_mm_mul_31ns_32s_32_3.h"
namespace ap_rtl {
struct sparse_mm : public sc_module {
// Port declarations 20
sc_in_clk ap_clk;
sc_in< sc_logic > ap_rst;
sc_in< sc_logic > ap_start;
sc_out< sc_logic > ap_done;
sc_out< sc_logic > ap_idle;
sc_out< sc_logic > ap_ready;
sc_out< sc_lv<22> > a_address0;
sc_out< sc_logic > a_ce0;
sc_in< sc_lv<64> > a_q0;
sc_in< sc_lv<32> > a_y;
sc_in< sc_lv<32> > a_x;
sc_out< sc_lv<11> > b_address0;
sc_out< sc_logic > b_ce0;
sc_in< sc_lv<32> > b_q0;
sc_in< sc_lv<32> > b_y;
sc_in< sc_lv<32> > b_x;
sc_out< sc_lv<11> > c_address0;
sc_out< sc_logic > c_ce0;
sc_out< sc_logic > c_we0;
sc_out< sc_lv<32> > c_d0;
// Module declarations
sparse_mm(sc_module_name name);
SC_HAS_PROCESS(sparse_mm);
~sparse_mm();
sc_trace_file* mVcdFile;
ofstream mHdltvinHandle;
ofstream mHdltvoutHandle;
sparse_mm_mul_32s_32s_32_3<1,3,32,32,32>* sparse_mm_mul_32s_32s_32_3_U1;
sparse_mm_mul_31ns_32s_32_3<1,3,31,32,32>* sparse_mm_mul_31ns_32s_32_3_U2;
sparse_mm_mul_32s_32s_32_3<1,3,32,32,32>* sparse_mm_mul_32s_32s_32_3_U3;
sc_signal< sc_lv<18> > ap_CS_fsm;
sc_signal< sc_logic > ap_sig_cseq_ST_st1_fsm_0;
sc_signal< bool > ap_sig_bdd_34;
sc_signal< sc_lv<32> > ibx_cast_fu_145_p1;
sc_signal< sc_lv<32> > ibx_cast_reg_258;
sc_signal< sc_logic > ap_sig_cseq_ST_st2_fsm_1;
sc_signal< bool > ap_sig_bdd_78;
sc_signal< sc_lv<31> > ibx_1_fu_154_p2;
sc_signal< sc_lv<31> > ibx_1_reg_267;
sc_signal< sc_lv<32> > a_i_1_fu_165_p2;
sc_signal< sc_lv<32> > a_i_1_reg_275;
sc_signal< sc_logic > ap_sig_cseq_ST_st3_fsm_2;
sc_signal< bool > ap_sig_bdd_89;
sc_signal< sc_lv<1> > tmp_1_fu_160_p2;
sc_signal< sc_lv<32> > column_cast_fu_190_p1;
sc_signal< sc_lv<32> > column_cast_reg_289;
sc_signal< sc_logic > ap_sig_cseq_ST_st6_fsm_5;
sc_signal< bool > ap_sig_bdd_105;
sc_signal< sc_lv<32> > value_reg_294;
sc_signal< sc_lv<32> > iay_1_fu_204_p2;
sc_signal< sc_lv<32> > iay_1_reg_299;
sc_signal< sc_lv<1> > tmp_6_fu_176_p1;
sc_signal< sc_lv<32> > grp_fu_215_p2;
sc_signal< sc_lv<32> > tmp_8_reg_304;
sc_signal< sc_logic > ap_sig_cseq_ST_st9_fsm_8;
sc_signal< bool > ap_sig_bdd_122;
sc_signal< sc_logic > ap_sig_cseq_ST_st10_fsm_9;
sc_signal< bool > ap_sig_bdd_131;
sc_signal< sc_lv<32> > b_load_reg_314;
sc_signal< sc_logic > ap_sig_cseq_ST_st11_fsm_10;
sc_signal< bool > ap_sig_bdd_139;
sc_signal< sc_lv<32> > grp_fu_228_p2;
sc_signal< sc_lv<32> > tmp_7_reg_319;
sc_signal< sc_logic > ap_sig_cseq_ST_st14_fsm_13;
sc_signal< bool > ap_sig_bdd_148;
sc_signal< sc_lv<32> > sum_1_fu_232_p2;
sc_signal< sc_logic > ap_sig_cseq_ST_st15_fsm_14;
sc_signal< bool > ap_sig_bdd_157;
sc_signal< sc_lv<32> > grp_fu_210_p2;
sc_signal< sc_lv<32> > tmp_3_reg_329;
sc_signal< sc_logic > ap_sig_cseq_ST_st17_fsm_16;
sc_signal< bool > ap_sig_bdd_166;
sc_signal< sc_lv<31> > ibx_reg_90;
sc_signal< sc_lv<32> > a_i_reg_101;
sc_signal< sc_lv<1> > tmp_fu_149_p2;
sc_signal< sc_logic > ap_sig_cseq_ST_st18_fsm_17;
sc_signal< bool > ap_sig_bdd_183;
sc_signal< sc_lv<32> > iay_reg_114;
sc_signal< sc_lv<32> > sum_reg_129;
sc_signal< sc_lv<64> > tmp_2_fu_171_p1;
sc_signal< sc_lv<64> > tmp_s_fu_223_p1;
sc_signal< sc_lv<64> > tmp_4_fu_241_p1;
sc_signal< sc_logic > ap_sig_cseq_ST_st4_fsm_3;
sc_signal< bool > ap_sig_bdd_200;
sc_signal< sc_logic > ap_sig_cseq_ST_st5_fsm_4;
sc_signal< bool > ap_sig_bdd_208;
sc_signal< sc_lv<32> > tmp_fu_149_p1;
sc_signal< sc_lv<31> > column_fu_180_p4;
sc_signal< sc_lv<31> > grp_fu_215_p0;
sc_signal< sc_logic > ap_sig_cseq_ST_st7_fsm_6;
sc_signal< bool > ap_sig_bdd_247;
sc_signal< sc_lv<32> > tmp_9_fu_219_p2;
sc_signal< sc_lv<32> > tmp_5_fu_237_p2;
sc_signal< sc_logic > grp_fu_210_ce;
sc_signal< sc_logic > grp_fu_215_ce;
sc_signal< sc_logic > grp_fu_228_ce;
sc_signal< sc_lv<18> > ap_NS_fsm;
static const sc_logic ap_const_logic_1;
static const sc_logic ap_const_logic_0;
static const sc_lv<18> ap_ST_st1_fsm_0;
static const sc_lv<18> ap_ST_st2_fsm_1;
static const sc_lv<18> ap_ST_st3_fsm_2;
static const sc_lv<18> ap_ST_st4_fsm_3;
static const sc_lv<18> ap_ST_st5_fsm_4;
static const sc_lv<18> ap_ST_st6_fsm_5;
static const sc_lv<18> ap_ST_st7_fsm_6;
static const sc_lv<18> ap_ST_st8_fsm_7;
static const sc_lv<18> ap_ST_st9_fsm_8;
static const sc_lv<18> ap_ST_st10_fsm_9;
static const sc_lv<18> ap_ST_st11_fsm_10;
static const sc_lv<18> ap_ST_st12_fsm_11;
static const sc_lv<18> ap_ST_st13_fsm_12;
static const sc_lv<18> ap_ST_st14_fsm_13;
static const sc_lv<18> ap_ST_st15_fsm_14;
static const sc_lv<18> ap_ST_st16_fsm_15;
static const sc_lv<18> ap_ST_st17_fsm_16;
static const sc_lv<18> ap_ST_st18_fsm_17;
static const sc_lv<32> ap_const_lv32_0;
static const sc_lv<1> ap_const_lv1_1;
static const sc_lv<32> ap_const_lv32_1;
static const sc_lv<32> ap_const_lv32_2;
static const sc_lv<1> ap_const_lv1_0;
static const sc_lv<32> ap_const_lv32_5;
static const sc_lv<32> ap_const_lv32_8;
static const sc_lv<32> ap_const_lv32_9;
static const sc_lv<32> ap_const_lv32_A;
static const sc_lv<32> ap_const_lv32_D;
static const sc_lv<32> ap_const_lv32_E;
static const sc_lv<32> ap_const_lv32_10;
static const sc_lv<31> ap_const_lv31_0;
static const sc_lv<32> ap_const_lv32_11;
static const sc_lv<32> ap_const_lv32_3;
static const sc_lv<32> ap_const_lv32_4;
static const sc_lv<31> ap_const_lv31_1;
static const sc_lv<32> ap_const_lv32_1F;
static const sc_lv<32> ap_const_lv32_20;
static const sc_lv<32> ap_const_lv32_3F;
static const sc_lv<32> ap_const_lv32_6;
// Thread declarations
void thread_ap_clk_no_reset_();
void thread_a_address0();
void thread_a_ce0();
void thread_a_i_1_fu_165_p2();
void thread_ap_done();
void thread_ap_idle();
void thread_ap_ready();
void thread_ap_sig_bdd_105();
void thread_ap_sig_bdd_122();
void thread_ap_sig_bdd_131();
void thread_ap_sig_bdd_139();
void thread_ap_sig_bdd_148();
void thread_ap_sig_bdd_157();
void thread_ap_sig_bdd_166();
void thread_ap_sig_bdd_183();
void thread_ap_sig_bdd_200();
void thread_ap_sig_bdd_208();
void thread_ap_sig_bdd_247();
void thread_ap_sig_bdd_34();
void thread_ap_sig_bdd_78();
void thread_ap_sig_bdd_89();
void thread_ap_sig_cseq_ST_st10_fsm_9();
void thread_ap_sig_cseq_ST_st11_fsm_10();
void thread_ap_sig_cseq_ST_st14_fsm_13();
void thread_ap_sig_cseq_ST_st15_fsm_14();
void thread_ap_sig_cseq_ST_st17_fsm_16();
void thread_ap_sig_cseq_ST_st18_fsm_17();
void thread_ap_sig_cseq_ST_st1_fsm_0();
void thread_ap_sig_cseq_ST_st2_fsm_1();
void thread_ap_sig_cseq_ST_st3_fsm_2();
void thread_ap_sig_cseq_ST_st4_fsm_3();
void thread_ap_sig_cseq_ST_st5_fsm_4();
void thread_ap_sig_cseq_ST_st6_fsm_5();
void thread_ap_sig_cseq_ST_st7_fsm_6();
void thread_ap_sig_cseq_ST_st9_fsm_8();
void thread_b_address0();
void thread_b_ce0();
void thread_c_address0();
void thread_c_ce0();
void thread_c_d0();
void thread_c_we0();
void thread_column_cast_fu_190_p1();
void thread_column_fu_180_p4();
void thread_grp_fu_210_ce();
void thread_grp_fu_215_ce();
void thread_grp_fu_215_p0();
void thread_grp_fu_228_ce();
void thread_iay_1_fu_204_p2();
void thread_ibx_1_fu_154_p2();
void thread_ibx_cast_fu_145_p1();
void thread_sum_1_fu_232_p2();
void thread_tmp_1_fu_160_p2();
void thread_tmp_2_fu_171_p1();
void thread_tmp_4_fu_241_p1();
void thread_tmp_5_fu_237_p2();
void thread_tmp_6_fu_176_p1();
void thread_tmp_9_fu_219_p2();
void thread_tmp_fu_149_p1();
void thread_tmp_fu_149_p2();
void thread_tmp_s_fu_223_p1();
void thread_ap_NS_fsm();
void thread_hdltv_gen();
};
}
using namespace ap_rtl;
#endif
|
#include <vector>
#include "systemc.h"
#include "tlm_utils/simple_initiator_socket.h"
#include "tlm_utils/simple_target_socket.h"
#ifndef INC_MEMORY_H_
#define INC_MEMORY_H_
class MEMORY : public sc_module
{
public:
MEMORY(sc_module_name name);
tlm_utils::simple_target_socket<MEMORY> memory_socket;
private:
void b_transport(tlm::tlm_generic_payload &trans, sc_core::sc_time &delay);
std::vector<uint8_t> dataMemory;
void programLoader(std::array<uint32_t, 4096> &binary);
void loadBinaeyFromHex(std::string filePath = "./binary.hex");
};
#endif //INC_MEMORY_H_
|
/***************************************************************************\
*
*
* ___ ___ ___ ___
* / /\ / /\ / /\ / /\
* / /:/ / /::\ / /::\ / /::\
* / /:/ / /:/\:\ / /:/\:\ / /:/\:\
* / /:/ / /:/~/:/ / /:/~/::\ / /:/~/:/
* / /::\ /__/:/ /:/___ /__/:/ /:/\:\ /__/:/ /:/
* /__/:/\:\ \ \:\/:::::/ \ \:\/:/__\/ \ \:\/:/
* \__\/ \:\ \ \::/~~~~ \ \::/ \ \::/
* \ \:\ \ \:\ \ \:\ \ \:\
* \ \ \ \ \:\ \ \:\ \ \:\
* \__\/ \__\/ \__\/ \__\/
*
*
*
*
* This file is part of TRAP.
*
* TRAP is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this program; if not, write to the
* Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
* or see <http://www.gnu.org/licenses/>.
*
*
*
* (c) Luca Fossati, [email protected], [email protected]
*
\***************************************************************************/
#ifndef PROFINFO_HPP
#define PROFINFO_HPP
#include <string>
#include <systemc.h>
namespace trap{
///Represents all the profiling data which can be
///associated with a single assembly instruction
struct ProfInstruction{
///Name of the assembly instruction (MOV, ADD ...)
std::string name;
///Number of times this instruction is called
unsigned long long numCalls;
///Total number of instructions executed
static unsigned long long numTotalCalls;
///Total time spent in executing the instruction
sc_time time;
///dump these information to a string, in the command separated values (CVS) format
std::string printCsv();
///Prints the description of the informations which describe an instruction, in the command separated values (CVS) format
static std::string printCsvHeader();
///Prints the summary of all the executed instructions, in the command separated values (CVS) format
static std::string printCsvSummary();
///Empty constructor, performs the initialization of the statistics
ProfInstruction();
};
///Represents all the profiling data which can be
///associated with a single function
struct ProfFunction{
///Address of the function
unsigned int address;
///Name of the function
std::string name;
///Number of times this function is called
unsigned long long numCalls;
///Total number of function calls
static unsigned long long numTotalCalls;
///The number of assembly instructions executed in total inside the function
unsigned long long totalNumInstr;
///The number of assembly instructions executed exclusively inside the function
unsigned long long exclNumInstr;
///Total time spent in the function
sc_time totalTime;
///Time spent exclusively in the function
sc_time exclTime;
///Used to coorectly keep track of the increment of the time, instruction count, etc.
///in recursive functions
bool alreadyExamined;
///dump these information to a string, in the command separated values (CVS) format
std::string printCsv();
///Prints the description of the informations which describe a function, in the command separated values (CVS) format
static std::string printCsvHeader();
///Empty constructor, performs the initialization of the statistics
ProfFunction();
};
}
#endif
|
// Copyright (c) 2011-2024 Columbia University, System Level Design Group
// SPDX-License-Identifier: MIT
#ifndef __ESP_SYSTEMC_HPP__
#define __ESP_SYSTEMC_HPP__
// Fixed point
#if defined(SC_FIXED_POINT) || defined(SC_FIXED_POINT_FAST)
// Using SystemC fixed point
#define SC_INCLUDE_FX
#include <systemc.h>
#else
// Using cynw fixed point (default)
#include <systemc.h>
#include <cynw_fixed.h>
#endif
// Channels
#ifdef __CARGO__
// Using CARGO flex channels
#include <flex_channels.hpp>
#else
// Using cynw flex channels (default)
#include <cynw_flex_channels.h>
#endif
#endif // __ESP_SYSTEMC_HPP__
|
/********************************************************************************
* University of L'Aquila - HEPSYCODE Source Code License *
* *
* *
* (c) 2018-2019 Centre of Excellence DEWS All rights reserved *
********************************************************************************
* <one line to give the program's name and a brief idea of what it does.> *
* Copyright (C) 2022 Vittoriano Muttillo, Luigi Pomante * *
* *
* This program is free software: you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation, either version 3 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
********************************************************************************
* *
* Created on: 09/May/2023 *
* Authors: Vittoriano Muttillo, Marco Santic, Luigi Pomante *
* *
* email: [email protected] *
* [email protected] *
* [email protected] *
* *
********************************************************************************
* This code has been developed from an HEPSYCODE model used as demonstrator by *
* University of L'Aquila. *
*******************************************************************************/
#include <systemc.h>
#include "../mainsystem.h"
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <math.h>
#include <unistd.h>
////////////////////////////// GENANN //////////////////
#ifdef __cplusplus
extern "C" {
#endif
#ifndef ann_04_GENANN_RANDOM
/* We use the following for uniform random numbers between 0 and 1.
* If you have a better function, redefine this macro. */
#define ann_04_GENANN_RANDOM() (((double)rand())/RAND_MAX)
#endif
struct ann_04_genann;
typedef double (*ann_04_genann_actfun)(const struct ann_04_genann *ann, double a);
typedef struct ann_04_genann {
/* How many inputs, outputs, and hidden neurons. */
int inputs, hidden_layers, hidden, outputs;
/* Which activation function to use for hidden neurons. Default: gennann_act_sigmoid_cached*/
ann_04_genann_actfun activation_hidden;
/* Which activation function to use for output. Default: gennann_act_sigmoid_cached*/
ann_04_genann_actfun activation_output;
/* Total number of weights, and size of weights buffer. */
int total_weights;
/* Total number of neurons + inputs and size of output buffer. */
int total_neurons;
/* All weights (total_weights long). */
double *weight;
/* Stores input array and output of each neuron (total_neurons long). */
double *output;
/* Stores delta of each hidden and output neuron (total_neurons - inputs long). */
double *delta;
} ann_04_genann;
#ifdef __cplusplus
}
#endif
///////////////////////////////////// GENANN ///////////////////////////
#ifndef ann_04_genann_act
#define ann_04_genann_act_hidden ann_04_genann_act_hidden_indirect
#define ann_04_genann_act_output ann_04_genann_act_output_indirect
#else
#define ann_04_genann_act_hidden ann_04_genann_act
#define ann_04_genann_act_output ann_04_genann_act
#endif
#define ann_04_LOOKUP_SIZE 4096
double ann_04_genann_act_hidden_indirect(const struct ann_04_genann *ann, double a)
{HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) return ann->activation_hidden(ann, a);
}
double ann_04_genann_act_output_indirect(const struct ann_04_genann *ann, double a)
{HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) return ann->activation_output(ann, a);
}
const double ann_04_sigmoid_dom_min = -15.0;
const double ann_04_sigmoid_dom_max = 15.0;
double ann_04_interval;
double ann_04_lookup[ann_04_LOOKUP_SIZE];
#ifdef __GNUC__
#define likely(x) __builtin_expect(!!(x), 1)
#define unlikely(x) __builtin_expect(!!(x), 0)
#define unused __attribute__((unused))
#else
#define likely(x) x
#define unlikely(x) x
#define unused
#pragma warning(disable : 4996) /* For fscanf */
#endif
double ann_04_genann_act_sigmoid(const ann_04_genann *ann unused, double a)
{HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) if (a < -45.0)
{HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) return 0;
HEPSY_S(ann_04_id) }
HEPSY_S(ann_04_id) if (a > 45.0)
{HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) return 1;
HEPSY_S(ann_04_id) }
HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) return 1.0 / (1 + exp(-a));
}
void ann_04_genann_init_sigmoid_lookup(const ann_04_genann *ann)
{HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) const double f = (ann_04_sigmoid_dom_max - ann_04_sigmoid_dom_min) / ann_04_LOOKUP_SIZE;
HEPSY_S(ann_04_id) int i;
HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) ann_04_interval = ann_04_LOOKUP_SIZE / (ann_04_sigmoid_dom_max - ann_04_sigmoid_dom_min);
HEPSY_S(ann_04_id) for (i = 0; i < ann_04_LOOKUP_SIZE; ++i)
{HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) ann_04_lookup[i] = ann_04_genann_act_sigmoid(ann, ann_04_sigmoid_dom_min + f * i);
HEPSY_S(ann_04_id) }
}
double ann_04_genann_act_sigmoid_cached(const ann_04_genann *ann unused, double a)
{HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) assert(!isnan(a));
HEPSY_S(ann_04_id) if (a < ann_04_sigmoid_dom_min)
{HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) return ann_04_lookup[0];
HEPSY_S(ann_04_id) }
HEPSY_S(ann_04_id) if (a >= ann_04_sigmoid_dom_max)
{HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) return ann_04_lookup[ann_04_LOOKUP_SIZE - 1];
HEPSY_S(ann_04_id) }
HEPSY_S(ann_04_id) size_t j = (size_t)((a-ann_04_sigmoid_dom_min)*ann_04_interval+0.5);
/* Because floating point... */
HEPSY_S(ann_04_id) if (unlikely(j >= ann_04_LOOKUP_SIZE))
{HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) return ann_04_lookup[ann_04_LOOKUP_SIZE - 1];
HEPSY_S(ann_04_id) }
HEPSY_S(ann_04_id) return ann_04_lookup[j];
}
double ann_04_genann_act_linear(const struct ann_04_genann *ann unused, double a)
{HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) return a;
}
double ann_04_genann_act_threshold(const struct ann_04_genann *ann unused, double a)
{HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) return a > 0;
}
void ann_04_genann_randomize(ann_04_genann *ann)
{HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) int i;
HEPSY_S(ann_04_id) for (i = 0; i < ann->total_weights; ++i)
{HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) double r = ann_04_GENANN_RANDOM();
/* Sets weights from -0.5 to 0.5. */
HEPSY_S(ann_04_id) ann->weight[i] = r - 0.5;
HEPSY_S(ann_04_id) }
}
ann_04_genann *ann_04_genann_init(int inputs, int hidden_layers, int hidden, int outputs)
{HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) if (hidden_layers < 0)
{HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) return 0;
HEPSY_S(ann_04_id) }
HEPSY_S(ann_04_id) if (inputs < 1)
{HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) return 0;
HEPSY_S(ann_04_id) }
HEPSY_S(ann_04_id) if (outputs < 1)
{HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) return 0;
HEPSY_S(ann_04_id) }
HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) if (hidden_layers > 0 && hidden < 1)
{HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) return 0;
HEPSY_S(ann_04_id) }
HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) const int hidden_weights = hidden_layers ? (inputs+1) * hidden + (hidden_layers-1) * (hidden+1) * hidden : 0;
HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) const int output_weights = (hidden_layers ? (hidden+1) : (inputs+1)) * outputs;
HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) const int total_weights = (hidden_weights + output_weights);
HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) const int total_neurons = (inputs + hidden * hidden_layers + outputs);
/* Allocate extra size for weights, outputs, and deltas. */
HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) const int size = sizeof(ann_04_genann) + sizeof(double) * (total_weights + total_neurons + (total_neurons - inputs));
HEPSY_S(ann_04_id) ann_04_genann *ret = (ann_04_genann *)malloc(size);
HEPSY_S(ann_04_id) if (!ret)
{HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) return 0;
HEPSY_S(ann_04_id) }
HEPSY_S(ann_04_id) ret->inputs = inputs;
HEPSY_S(ann_04_id) ret->hidden_layers = hidden_layers;
HEPSY_S(ann_04_id) ret->hidden = hidden;
HEPSY_S(ann_04_id) ret->outputs = outputs;
HEPSY_S(ann_04_id) ret->total_weights = total_weights;
HEPSY_S(ann_04_id) ret->total_neurons = total_neurons;
/* Set pointers. */
HEPSY_S(ann_04_id) ret->weight = (double*)((char*)ret + sizeof(ann_04_genann));
HEPSY_S(ann_04_id) ret->output = ret->weight + ret->total_weights;
HEPSY_S(ann_04_id) ret->delta = ret->output + ret->total_neurons;
HEPSY_S(ann_04_id) ann_04_genann_randomize(ret);
HEPSY_S(ann_04_id) ret->activation_hidden = ann_04_genann_act_sigmoid_cached;
HEPSY_S(ann_04_id) ret->activation_output = ann_04_genann_act_sigmoid_cached;
HEPSY_S(ann_04_id) ann_04_genann_init_sigmoid_lookup(ret);
HEPSY_S(ann_04_id) return ret;
}
void ann_04_genann_free(ann_04_genann *ann)
{HEPSY_S(ann_04_id)
/* The weight, output, and delta pointers go to the same buffer. */
HEPSY_S(ann_04_id) free(ann);
}
//genann *genann_read(FILE *in)
//genann *genann_copy(genann const *ann)
double const *ann_04_genann_run(ann_04_genann const *ann, double const *inputs)
{HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) double const *w = ann->weight;
HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) double *o = ann->output + ann->inputs;
HEPSY_S(ann_04_id) double const *i = ann->output;
/* Copy the inputs to the scratch area, where we also store each neuron's
* output, for consistency. This way the first layer isn't a special case. */
HEPSY_S(ann_04_id) memcpy(ann->output, inputs, sizeof(double) * ann->inputs);
HEPSY_S(ann_04_id) int h, j, k;
HEPSY_S(ann_04_id) if (!ann->hidden_layers)
{HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) double *ret = o;
HEPSY_S(ann_04_id) for (j = 0; j < ann->outputs; ++j)
{HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) double sum = *w++ * -1.0;
HEPSY_S(ann_04_id) for (k = 0; k < ann->inputs; ++k)
{HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) sum += *w++ * i[k];
HEPSY_S(ann_04_id) }
HEPSY_S(ann_04_id) *o++ = ann_04_genann_act_output(ann, sum);
HEPSY_S(ann_04_id) }
HEPSY_S(ann_04_id) return ret;
HEPSY_S(ann_04_id) }
/* Figure input layer */
HEPSY_S(ann_04_id) for (j = 0; j < ann->hidden; ++j)
{HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) double sum = *w++ * -1.0;
HEPSY_S(ann_04_id) for (k = 0; k < ann->inputs; ++k)
{HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) sum += *w++ * i[k];
HEPSY_S(ann_04_id) }
HEPSY_S(ann_04_id) *o++ = ann_04_genann_act_hidden(ann, sum);
HEPSY_S(ann_04_id) }
HEPSY_S(ann_04_id) i += ann->inputs;
/* Figure hidden layers, if any. */
HEPSY_S(ann_04_id) for (h = 1; h < ann->hidden_layers; ++h)
{HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) for (j = 0; j < ann->hidden; ++j)
{HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) double sum = *w++ * -1.0;
HEPSY_S(ann_04_id) for (k = 0; k < ann->hidden; ++k)
{HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) sum += *w++ * i[k];
HEPSY_S(ann_04_id) }
HEPSY_S(ann_04_id) *o++ = ann_04_genann_act_hidden(ann, sum);
HEPSY_S(ann_04_id) }
HEPSY_S(ann_04_id) i += ann->hidden;
HEPSY_S(ann_04_id) }
double const *ret = o;
/* Figure output layer. */
for (j = 0; j < ann->outputs; ++j) {
double sum = *w++ * -1.0;
for (k = 0; k < ann->hidden; ++k) {
sum += *w++ * i[k];
}
*o++ = ann_04_genann_act_output(ann, sum);
}
/* Sanity check that we used all weights and wrote all outputs. */
assert(w - ann->weight == ann->total_weights);
assert(o - ann->output == ann->total_neurons);
return ret;
}
//void genann_train(genann const *ann, double const *inputs, double const *desired_outputs, double learning_rate)
//void genann_write(genann const *ann, FILE *out)
/////////////////////// ANN ////////////////////////
#define ann_04_NUM_DEV 1 // The equipment is composed of NUM_DEV devices ...
//-----------------------------------------------------------------------------
//
//-----------------------------------------------------------------------------
#define ann_04_MAX_ANN 100 // Maximum MAX_ANN ANN
#define ann_04_ANN_INPUTS 2 // Number of inputs
#define ann_04_ANN_HIDDEN_LAYERS 1 // Number of hidden layers
#define ann_04_ANN_HIDDEN_NEURONS 2 // Number of neurons of every hidden layer
#define ann_04_ANN_OUTPUTS 1 // Number of outputs
//-----------------------------------------------------------------------------
//
//-----------------------------------------------------------------------------
#define ann_04_ANN_EPOCHS 10000
#define ann_04_ANN_DATASET 6
#define ann_04_ANN_LEARNING_RATE 3 // ...
//-----------------------------------------------------------------------------
//
//-----------------------------------------------------------------------------
#define ann_04_MAX_ERROR 0.00756 // 0.009
//-----------------------------------------------------------------------------
//
//-----------------------------------------------------------------------------
static int ann_04_nANN = -1 ; // Number of ANN that have been created
static ann_04_genann * ann_04_ann[ann_04_MAX_ANN] ; // Now up to MAX_ANN ann
//static double ann_04_trainingInput[ann_04_ANN_DATASET][ann_04_ANN_INPUTS] = { {0, 0}, {0, 1}, {1, 0}, {1, 1}, {0, 1}, {0, 0} } ;
//static double ann_04_trainingExpected[ann_04_ANN_DATASET][ann_04_ANN_OUTPUTS] = { {0}, {1}, {1}, {0}, {1}, {0} } ;
static double ann_04_weights[] = {
-3.100438,
-7.155774,
-7.437955,
-8.132828,
-5.583678,
-5.327152,
5.564897,
-12.201226,
11.771879
} ;
// static double input[4][3] = {{0, 0, 1}, {0, 1, 1}, {1, 0, 1}, {1, 1, 1}};
// static double output[4] = {0, 1, 1, 0};
//-----------------------------------------------------------------------------
//
//-----------------------------------------------------------------------------
static int ann_04_annCheck(int index);
static int ann_04_annCreate(int n);
//-----------------------------------------------------------------------------
// Check the correctness of the index of the ANN
//-----------------------------------------------------------------------------
int ann_04_annCheck(int index)
{HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) if ( (index < 0) || (index >= ann_04_nANN) )
{HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) return( EXIT_FAILURE );
HEPSY_S(ann_04_id) }
HEPSY_S(ann_04_id) return( EXIT_SUCCESS );
}
//-----------------------------------------------------------------------------
// Create n ANN
//-----------------------------------------------------------------------------
int ann_04_annCreate(int n)
{HEPSY_S(ann_04_id)
// If already created, or not legal number, or too many ANN, then error
HEPSY_S(ann_04_id) if ( (ann_04_nANN != -1) || (n <= 0) || (n > ann_04_MAX_ANN) )
{HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) return( EXIT_FAILURE );
HEPSY_S(ann_04_id) }
// Create the ANN's
HEPSY_S(ann_04_id) for ( int i = 0; i < n; i++ )
{HEPSY_S(ann_04_id)
// New ANN with ANN_INPUT inputs, ANN_HIDDEN_LAYER hidden layers all with ANN_HIDDEN_NEURON neurons, and ANN_OUTPUT outputs
HEPSY_S(ann_04_id) ann_04_ann[i] = ann_04_genann_init(ann_04_ANN_INPUTS, ann_04_ANN_HIDDEN_LAYERS, ann_04_ANN_HIDDEN_NEURONS, ann_04_ANN_OUTPUTS);
HEPSY_S(ann_04_id) if( ann_04_ann[i] == 0 )
{HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) for (int j = 0; j < i; j++)
{HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) ann_04_genann_free(ann_04_ann[j]) ;
HEPSY_S(ann_04_id) }
HEPSY_S(ann_04_id) return( EXIT_FAILURE );
HEPSY_S(ann_04_id) }
HEPSY_S(ann_04_id) }
HEPSY_S(ann_04_id) ann_04_nANN = n ;
HEPSY_S(ann_04_id) return( EXIT_SUCCESS );
}
////-----------------------------------------------------------------------------
//// Create and train n identical ANN
////-----------------------------------------------------------------------------
//int annCreateAndTrain(int n)
//{
// if ( annCreate(n) != EXIT_SUCCESS )
// return( EXIT_FAILURE );
//
// // Train the ANN's
// for ( int index = 0; index < nANN; index++ )
// for ( int i = 0; i < ANN_EPOCHS; i++ )
// for ( int j = 0; j < ANN_DATASET; j++ )
// genann_train(ann[index], trainingInput[j], trainingExpected[j], ANN_LEARNING_RATE) ;
//
// return( EXIT_SUCCESS );
//}
//-----------------------------------------------------------------------------
// Create n identical ANN and set their weight
//-----------------------------------------------------------------------------
int ann_04_annCreateAndSetWeights(int n)
{HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) if( ann_04_annCreate(n) != EXIT_SUCCESS )
{HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) return( EXIT_FAILURE );
HEPSY_S(ann_04_id) }
// Set weights
HEPSY_S(ann_04_id) for ( int index = 0; index < ann_04_nANN; index++ )
{HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) for ( int i = 0; i < ann_04_ann[index]->total_weights; ++i )
{HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) ann_04_ann[index]->weight[i] = ann_04_weights[i] ;
HEPSY_S(ann_04_id)}
HEPSY_S(ann_04_id)}
HEPSY_S(ann_04_id) return( EXIT_SUCCESS );
}
//-----------------------------------------------------------------------------
// x[2] = x[0] XOR x[1]
//-----------------------------------------------------------------------------
int ann_04_annRun(int index, double x[ann_04_ANN_INPUTS + ann_04_ANN_OUTPUTS])
{HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) if( ann_04_annCheck(index) != EXIT_SUCCESS )
{HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) return( EXIT_FAILURE ) ;
HEPSY_S(ann_04_id) }
HEPSY_S(ann_04_id) x[2] = * ann_04_genann_run(ann_04_ann[index], x) ;
HEPSY_S(ann_04_id) return( EXIT_SUCCESS );
}
////-----------------------------------------------------------------------------
////
////-----------------------------------------------------------------------------
//int annPrintWeights(int index)
//{
// if ( annCheck(index) != EXIT_SUCCESS )
// return( EXIT_FAILURE ) ;
//
//
// printf("\n*** ANN index = %d\n", index) ;
// for ( int i = 0; i < ann[index]->total_weights; ++i )
// printf("*** w%d = %f\n", i, ann[index]->weight[i]) ;
//
// return( EXIT_SUCCESS );
//}
////-----------------------------------------------------------------------------
//// Run the index-th ANN k time on random input and return the numb
|
er of error
////-----------------------------------------------------------------------------
//int annTest(int index, int k)
//{
// int x0; int x1; int y;
// double x[2];
// double xor_ex;
// int error = 0;
//
// if ( annCheck(index) != EXIT_SUCCESS )
// return( -1 ); // less than zero errors <==> the ANN isn't correctly created
//
// for (int i = 0; i < k; i++ )
// {
// x0 = rand() % 2; x[0] = (double)x0;
// x1 = rand() % 2; x[1] = (double)x1;
// y = x0 ^ x1 ;
//
// xor_ex = * genann_run(ann[index], x);
// if ( fabs(xor_ex - (double)y) > MAX_ERROR )
// {
// error++ ;
// printf("@@@ Error: ANN = %d, step = %d, x0 = %d, x1 = %d, y = %d, xor_ex = %f \n", index, i, x0, x1, y, xor_ex) ;
// }
// }
//
// if ( error )
// printf("@@@ ANN = %d: N� of errors = %d\n", index, error) ;
// else
// printf("*** ANN = %d: Test OK\n",index) ;
// return( error );
//}
//-----------------------------------------------------------------------------
//
//-----------------------------------------------------------------------------
void ann_04_annDestroy(void)
{HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) if ( ann_04_nANN == -1 )
{HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) return ;
HEPSY_S(ann_04_id) }
HEPSY_S(ann_04_id) for ( int index = 0; index < ann_04_nANN; index++ )
{HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) ann_04_genann_free(ann_04_ann[index]) ;
HEPSY_S(ann_04_id) }
HEPSY_S(ann_04_id) ann_04_nANN = -1 ;
}
void mainsystem::ann_04_main()
{
// datatype for channels
cleanData_xx_ann_xx_payload cleanData_xx_ann_xx_payload_var;
ann_xx_dataCollector_payload ann_xx_dataCollector_payload_var;
double x[ann_04_ANN_INPUTS + ann_04_ANN_OUTPUTS] ;
//int ann_04_index = 1;
HEPSY_S(ann_04_id) if( ann_04_annCreateAndSetWeights(ann_04_NUM_DEV) != EXIT_SUCCESS )
{HEPSY_S(ann_04_id) // Create and init ANN
HEPSY_S(ann_04_id) printf("Error Weights \n");
HEPSY_S(ann_04_id) }
//implementation
HEPSY_S(ann_04_id) while(1)
{HEPSY_S(ann_04_id)
// content
HEPSY_S(ann_04_id) cleanData_xx_ann_xx_payload_var = cleanData_04_ann_04_channel->read();
HEPSY_S(ann_04_id) ann_xx_dataCollector_payload_var.dev = cleanData_xx_ann_xx_payload_var.dev;
HEPSY_S(ann_04_id) ann_xx_dataCollector_payload_var.step = cleanData_xx_ann_xx_payload_var.step;
HEPSY_S(ann_04_id) ann_xx_dataCollector_payload_var.ex_time = cleanData_xx_ann_xx_payload_var.ex_time;
HEPSY_S(ann_04_id) ann_xx_dataCollector_payload_var.device_i = cleanData_xx_ann_xx_payload_var.device_i;
HEPSY_S(ann_04_id) ann_xx_dataCollector_payload_var.device_v = cleanData_xx_ann_xx_payload_var.device_v;
HEPSY_S(ann_04_id) ann_xx_dataCollector_payload_var.device_t = cleanData_xx_ann_xx_payload_var.device_t;
HEPSY_S(ann_04_id) ann_xx_dataCollector_payload_var.device_r = cleanData_xx_ann_xx_payload_var.device_r;
HEPSY_S(ann_04_id) x[0] = cleanData_xx_ann_xx_payload_var.x_0;
HEPSY_S(ann_04_id) x[1] = cleanData_xx_ann_xx_payload_var.x_1;
HEPSY_S(ann_04_id) x[2] = cleanData_xx_ann_xx_payload_var.x_2;
//u = cleanData_xx_ann_xx_payload_var.step;
HEPSY_S(ann_04_id) ann_xx_dataCollector_payload_var.fault = cleanData_xx_ann_xx_payload_var.fault;
//RUN THE ANN...
// ### P R E D I C T (simple XOR)
// if ( annRun(index, x) != EXIT_SUCCESS ){
// printf("Step = %u Index = %d ANN error.\n", u, index) ;
// }else{
// device[index].fault = x[2] <= 0.5 ? 0 : 1 ;
// }
//u: cycle num
HEPSY_S(ann_04_id) if ( ann_04_annRun(0, x) != EXIT_SUCCESS )
{HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) printf("Step = %d Index = %d ANN error.\n", (int)ann_xx_dataCollector_payload_var.step, (int)ann_xx_dataCollector_payload_var.dev) ;
HEPSY_S(ann_04_id) }
else
{HEPSY_S(ann_04_id)
HEPSY_S(ann_04_id) ann_xx_dataCollector_payload_var.fault = x[2] <= 0.5 ? 0 : 1 ;
HEPSY_S(ann_04_id) }
HEPSY_S(ann_04_id) ann_04_dataCollector_channel->write(ann_xx_dataCollector_payload_var);
HEPSY_P(ann_04_id)
}
}
// END
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
#ifndef __PS_PMC_TLM_H__
#define __PS_PMC_TLM_H__
#include "systemc.h"
#include "xtlm.h"
#include "xtlm_adaptors/xaximm_xtlm2tlm.h"
#include "xtlm_adaptors/xaximm_tlm2xtlm.h"
#include "tlm_utils/simple_initiator_socket.h"
#include "tlm_utils/simple_target_socket.h"
#include <vector>
#include "genattr.h"
#include "xilinx_versal.h"
#include <stdlib.h>
#include "xtlm_simple_interconnect_model.h"
#include "b_transport_converter.h"
#include "utils/xtlm_axis_target_stub.h"
#include "utils/xtlm_axis_initiator_stub.h"
#include "utils/xtlm_aximm_target_stub.h"
#include "utils/xtlm_aximm_initiator_stub.h"
/***************************************************************************************
*
* A Simple Converter which converts Remote-port's simplae_intiator_sockets<32>->b_transport()
* calls to xTLM sockets bn_transport_x() calls..
*
* This is Only specific to remote-port so not creating seperate header for it.
*
***************************************************************************************/
template <int IN_WIDTH, int OUT_WIDTH>
class rptlm2xtlm_converter : public sc_module {
public:
sc_core::sc_in<bool> clk;
tlm::tlm_target_socket<IN_WIDTH> target_socket;
xtlm::xtlm_aximm_initiator_socket wr_socket;
xtlm::xtlm_aximm_initiator_socket rd_socket;
rptlm2xtlm_converter<IN_WIDTH, OUT_WIDTH>(sc_module_name name);//:sc_module(name)
void registerUserExtensionHandlerCallback(
void (*callback)(xtlm::aximm_payload*,
const tlm::tlm_generic_payload*));
private:
b_transport_converter<IN_WIDTH, OUT_WIDTH> m_btrans_conv;
xtlm::xaximm_tlm2xtlm_t<OUT_WIDTH> xtlm_bridge;
void before_end_of_elaboration();
};
/***************************************************************************************
* Global method, get registered with tlm2xtlm bridge
* This function is called when tlm2xtlm bridge convert tlm payload to xtlm payload.
*
* caller: tlm2xtlm bridge
* purpose: To get master id and other parameters out of genattr_extension
* and use master id to AxUSER PIN of xtlm payload.
*
*
***************************************************************************************/
extern void get_extensions_from_tlm(xtlm::aximm_payload* xtlm_pay, const tlm::tlm_generic_payload* gp);
/***************************************************************************************
* Global method, get registered with xtlm2tlm bridge
* This function is called when xtlm2tlm bridge convert xtlm payload to tlm payload.
*
* caller: xtlm2tlm bridge
* purpose: To create and add master id and other parameters to genattr_extension.
* Master id red from AxID PIN of xtlm payload.
*
*
***************************************************************************************/
extern void add_extensions_to_tlm(const xtlm::aximm_payload* xtlm_pay, tlm::tlm_generic_payload* gp);
////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////
// //
// File: versal_cips_v3_0_tlm.h //
// //
// Description: versal_cips_v3_0_1_tlm class is a sc_module, act as intermediate layer between //
// xilinx_zynqmp qemu wrapper and Vivado generated systemc simulation ip wrapper. //
// it's basically created for supporting tlm based xilinx_zynqmp from xtlm based vivado //
// generated systemc wrapper. this wrapper is live only when SELECTED_SIM_MODEL is set //
// to tlm. it's also act as bridge between vivado wrapper and xilinx_zynqmp wrapper. //
// it fill the the gap between input/output ports of vivado generated wrapper to //
// xilinx_zynqmp wrapper signals. This wrapper is auto generated by ttcl scripts //
// based on IP configuration in vivado. //
// //
// //
////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////
template<int INIT_WIDTH, int TARGET_WIDTH>
class tlm_width_conversion;
class versal_cips_v3_0_1_tlm : public sc_core::sc_module {
//Adding Non-AXI port
public:
//Adding SystemC ports to wrapper for pspmc ports in dictionary
sc_core::sc_out < sc_dt::sc_bv< 94 > > gem0_tsu_timer_cnt;
//Adding SystemC ports to wrapper for cpm ports in dictionary
//Adding AXIMM/AXIS interfaces here
//Adding AXIMM/AXIS interfaces here
//constructor having three paramters
// 1. module name in sc_module_name objec,
// 2. reference to map object of name and integer value pairs
// 3. reference to map object of name and string value pairs
// All the model parameters (integer and string) which are configuration parameters
// of ZynqUltraScale+ IP propogated from Vivado
versal_cips_v3_0_1_tlm (sc_core::sc_module_name name, xsc::common_cpp::properties model_param_props);
~versal_cips_v3_0_1_tlm();
SC_HAS_PROCESS(versal_cips_v3_0_1_tlm);
private:
//zynqmp tlm wrapper provided by Edgar
//module with interfaces of standard tlm
//and input/output ports at signal level
xilinx_versal* m_zynq3_tlm_model;
// Array of Xtlm2tlm Bridges
// Converts Xtlm transactions to tlm transactions
// Bridge's Xtlm wr/rd target sockets binds with
// xtlm initiator sockets of zynq_ultra_ps_e_tlm and tlm simple initiator
// socket with xilinx_zynqmp's target socket
// Array of size 11
xtlm::xaximm_xtlm2tlm **m_xtlm2tlm;
void pl_ps_irq_method();
sc_signal<bool> qemu_rst;
void start_of_simulation();
void rwd_tlmmodule_init();
void enable_sim_qdma();
//for stubbing axis interfaces of pcie.. TODO: in future they bind to sim_qdma
sc_signal<sc_bv<16> > dummy_usr_irq_req;
sc_signal<sc_bv<16> > dummy_usr_irq_ack;
std::vector<xtlm::xtlm_axis_target_stub*> axis_slave_stub;
std::vector<xtlm::xtlm_axis_initiator_stub*> axis_master_stub;
std::vector<xtlm::xtlm_aximm_target_stub*> aximm_slave_stub;
std::vector<xtlm::xtlm_aximm_initiator_stub*> aximm_master_stub;
};
#endif
|
#ifndef SYSC_TYPES_H
#define SYSC_TYPES_H
#include <iomanip>
#include <iostream>
#include <systemc.h>
#include "secda_hw_utils.sc.h"
#ifndef DWAIT
#ifndef __SYNTHESIS__
#define DWAIT(x) wait(x)
#else
#define DWAIT(x)
#endif
#endif
#define INITSIGPORT(X, SID) X((std::string(#X) + std::to_string(SID)).c_str())
// Hardware struct to contain output signal and port
struct sc_out_sig {
sc_out<int> oS;
sc_signal<int> iS;
void write(int x) {
oS.write(x);
iS.write(x);
}
int read() { return iS.read(); }
void operator=(int x) { write(x); }
void bind(sc_signal<int> &sig) { oS.bind(sig); }
void operator()(sc_signal<int> &sig) { bind(sig); }
void bind(sc_out<int> &sig) { oS.bind(sig); }
void operator()(sc_out<int> &sig) { bind(sig); }
};
typedef struct _DATA {
sc_uint<32> data;
bool tlast;
void operator=(_DATA _data) {
data = _data.data;
tlast = _data.tlast;
}
inline friend ostream &operator<<(ostream &os, const _DATA &v) {
cout << "data: " << v.data << " tlast: " << v.tlast;
return os;
}
void pack(sc_int<8> a1, sc_int<8> a2, sc_int<8> a3, sc_int<8> a4) {
data.range(7, 0) = a1;
data.range(15, 8) = a2;
data.range(23, 16) = a3;
data.range(31, 24) = a4;
}
} DATA;
typedef struct _SDATA {
sc_int<32> data;
bool tlast;
inline friend ostream &operator<<(ostream &os, const _SDATA &v) {
cout << "data: " << v.data << " tlast: " << v.tlast;
return os;
}
} SDATA;
template <int W>
struct _FDATA {
sc_uint<W> data;
bool tlast;
inline friend ostream &operator<<(ostream &os, const _FDATA &v) {
cout << "data: " << v.data << " tlast: " << v.tlast;
return os;
}
};
struct rm_data2 {
sc_fifo_in<DATA> dout1;
sc_fifo_out<DATA> din1;
// int base_r_addr = 0;
// int mem_r_addr = 0;
// sc_out<bool> mem_start_read;
// sc_in<bool> mem_read_done;
// sc_out<unsigned int> mem_r_addr_p;
// sc_out<unsigned int> mem_r_length_p;
// int base_w_addr = 0;
// int mem_w_addr = 0;
// sc_out<bool> mem_start_write;
// sc_in<bool> mem_write_done;
// sc_out<unsigned int> mem_w_addr_p;
// sc_out<unsigned int> mem_w_length_p;
bool use_sim = false;
int layer = 0;
// this writes to acc and reads from main memory
void generate_reads(int addr, int length) {
// generate trace for ramulator
ofstream file;
std::string filename =
".data/secda_pim/traces/" + std::to_string(layer) + ".trace";
file.open(filename, std::ios_base::app);
int index = 0;
for (int i = 0; i < length; i += 4) {
file << "0x" << std::setfill('0') << std::setw(8) << std::hex
<< (addr + i + 0) << " R" << endl;
// file << "0x" << std::setfill('0') << std::setw(8) << std::hex
// << (addr + i + 1) << " R" << endl;
// file << "0x" << std::setfill('0') << std::setw(8) << std::hex
// << (addr + i + 2) << " R" << endl;
// file << "0x" << std::setfill('0') << std::setw(8) << std::hex
// << (addr + i + 3) << " R" << endl;
}
file.close();
}
void generate_writes(int addr, int length) {
// generate trace for ramulator
ofstream file;
std::string filename =
".data/secda_pim/traces/" + std::to_string(layer) + ".trace";
file.open(filename, std::ios_base::app);
int index = 0;
for (int i = 0; i < length; i += 4) {
file << "0x" << std::setfill('0') << std::setw(8) << std::hex
<< (addr + i + 0) << " W" << endl;
// file << "0x" << std::setfill('0') << std::setw(8) << std::hex
// << (addr + i + 1) << " W" << endl;
// file << "0x" << std::setfill('0') << std::setw(8) << std::hex
// << (addr + i + 2) << " W" << endl;
// file << "0x" << std::setfill('0') << std::setw(8) << std::hex
// << (addr + i + 3) << " W" << endl;
}
file.close();
}
void write(DATA d, int r_addr) {
if (!use_sim) {
// generate_reads(r_addr, 4);
// mem_start_read.write(true);
// mem_r_addr_p.write(r_addr);
// mem_r_length_p.write(4);
// DWAIT(1);
// while (!mem_read_done.read()) DWAIT(1);
// mem_start_read.write(false);
// DWAIT(1);
}
din1.write(d);
}
// this reads from acc and writes to the main memory
DATA read(int w_addr) {
if (!use_sim) {
// generate_writes(w_addr, 4);
// mem_start_write.write(true);
// mem_w_addr_p.write(w_addr);
// mem_w_length_p.write(4);
// DWAIT(1);
// while (!mem_write_done.read()) DWAIT(1);
// mem_start_write.write(false);
// DWAIT(1);
}
return dout1.read();
}
};
template <int W>
using FDATA = _FDATA<W>;
#endif
|
// sub.h: interface for the sub class.
//
//////////////////////////////////////////////////////////////////////
#ifndef _SUB_H_
#define _SUB_H_
#include "systemc.h"
#ifdef INI_CHANNEL
#undef INI_CHANNEL
#endif
#define INI_CHANNEL , clock("clock")\
, in_bool("in_bool")\
, in_float("in_float")\
, in_double("in_double")\
, in_char("in_char")\
, in_uchar("in_uchar")\
, in_short("in_short")\
, in_ushort("in_ushort")\
, in_int("in_int")\
, in_uint("in_uint")\
, in_long("in_long")\
, in_ulong("in_ulong")\
, in_longlong("in_longlong")\
, in_ulonglong("in_ulonglong")\
/*,in_std_string("in_std_string")*/\
, in_sc_bit("in_sc_bit")\
, in_sc_logic("in_sc_logic")\
, in_sc_lv("in_sc_lv")\
, in_sc_bv("in_sc_bv")\
, in_sc_int("in_sc_int")\
, in_sc_uint("in_sc_uint")\
, in_sc_bigint("in_sc_bigint")\
, in_sc_biguint("in_sc_biguint")\
, in_sc_fixed("in_sc_fixed")\
, in_sc_fixed_fast("in_sc_fixed_fast")\
, in_sc_ufixed("in_sc_ufixed")\
, out_bool("out_bool")\
, out_float("out_float")\
, out_double("out_double")\
, out_char("out_char")\
, out_uchar("out_uchar")\
, out_short("out_short")\
, out_ushort("out_ushort")\
, out_int("out_int")\
, out_uint("out_uint")\
, out_long("out_long")\
, out_ulong("out_ulong")\
, out_longlong("out_longlong")\
, out_ulonglong("out_ulonglong")\
/*,out_std_string("out_std_string")*/\
, out_sc_bit("out_sc_bit")\
, out_sc_logic("out_sc_logic")\
, out_sc_lv("out_sc_lv")\
, out_sc_bv("out_sc_bv")\
, out_sc_int("out_sc_int")\
, out_sc_uint("out_sc_uint")\
, out_sc_bigint("out_sc_bigint")\
, out_sc_biguint("out_sc_biguint")\
, out_sc_fixed("out_sc_fixed")\
, out_sc_fixed_fast("out_sc_fixed_fast")\
, out_sc_ufixed("out_sc_ufixed")\
class sub : public sc_module {
// interface
public:
// input
sc_in_clk clock;
sc_in<bool> in_bool;
sc_in<float> in_float;
sc_in<double> in_double;
sc_in<char> in_char;
sc_in<unsigned char> in_uchar;
sc_in<short> in_short;
sc_in<unsigned short> in_ushort;
sc_in<int> in_int;
sc_in<unsigned int> in_uint;
sc_in<long> in_long;
sc_in<unsigned long> in_ulong;
sc_in<long long> in_longlong;
sc_in<unsigned long long > in_ulonglong;
// sc_in<std::string > in_std_string;
sc_in<sc_bit> in_sc_bit;
sc_in<sc_logic> in_sc_logic;
sc_in<sc_lv<16> > in_sc_lv;
sc_in<sc_bv<16> > in_sc_bv;
sc_in<sc_int<16> > in_sc_int;
sc_in<sc_uint<16> > in_sc_uint;
sc_in<sc_bigint<64> > in_sc_bigint;
sc_in<sc_biguint<64> > in_sc_biguint;
sc_in<sc_fixed<16, 10, SC_RND, SC_SAT, 0> > in_sc_fixed;
sc_in<sc_fixed_fast<16, 10, SC_RND, SC_SAT, 0> > in_sc_fixed_fast;
sc_in<sc_ufixed<16, 10, SC_RND, SC_SAT, 0> > in_sc_ufixed;
// output
sc_out<bool> out_bool;
sc_out<float> out_float;
sc_out<double> out_double;
sc_out<char> out_char;
sc_out<unsigned char> out_uchar;
sc_out<short> out_short;
sc_out<unsigned short> out_ushort;
sc_out<int> out_int;
sc_out<unsigned int> out_uint;
sc_out<long> out_long;
sc_out<unsigned long> out_ulong;
sc_out<long long> out_longlong;
sc_out<unsigned long long > out_ulonglong;
// sc_out<std::string > out_std_string;
sc_out<sc_bit> out_sc_bit;
sc_out<sc_logic> out_sc_logic;
sc_out<sc_lv<16> > out_sc_lv;
sc_out<sc_bv<16> > out_sc_bv;
sc_out<sc_int<16> > out_sc_int;
sc_out<sc_uint<16> > out_sc_uint;
sc_out<sc_bigint<64> > out_sc_bigint;
sc_out<sc_biguint<64> > out_sc_biguint;
sc_out<sc_fixed<16, 10, SC_RND, SC_SAT, 0> > out_sc_fixed;
sc_out<sc_fixed_fast<16, 10, SC_RND, SC_SAT, 0> > out_sc_fixed_fast;
sc_out<sc_ufixed<16, 10, SC_RND, SC_SAT, 0> > out_sc_ufixed;
public:
SC_HAS_PROCESS(sub);
sub(sc_module_name name_)
:sc_module(name_)
INI_CHANNEL {
Initialize();
SC_METHOD(Action);
sensitive_pos << clock;
}
virtual ~sub();
public:
void Action();
void Initialize();
void InitPort();
void Reset();
};
#ifdef INI_CHANNEL
#undef INI_CHANNEL
#endif
#endif // !defined(_SUB_H_)
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
// Version: 2020.1
// Copyright (C) 1986-2020 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _Detecteur2_HH_
#define _Detecteur2_HH_
#include "systemc.h"
#include "AESL_pkg.h"
#include "Seuil_calc2.h"
#include "trames_separ2.h"
#include "DOUBLEUR_U.h"
#include "fifo_w8_d1024_A.h"
#include "fifo_w1_d1024_A.h"
namespace ap_rtl {
struct Detecteur2 : public sc_module {
// Port declarations 8
sc_in_clk clock;
sc_in< sc_logic > reset;
sc_in< sc_lv<8> > e_dout;
sc_in< sc_logic > e_empty_n;
sc_out< sc_logic > e_read;
sc_out< sc_lv<8> > s_din;
sc_in< sc_logic > s_full_n;
sc_out< sc_logic > s_write;
sc_signal< sc_logic > ap_var_for_const0;
// Module declarations
Detecteur2(sc_module_name name);
SC_HAS_PROCESS(Detecteur2);
~Detecteur2();
sc_trace_file* mVcdFile;
Seuil_calc2* grp_Seuil_calc2_fu_100;
trames_separ2* grp_trames_separ2_fu_114;
DOUBLEUR_U* grp_DOUBLEUR_U_fu_130;
fifo_w8_d1024_A* dbl2scalc_1_fifo_U;
fifo_w8_d1024_A* dbl2tsep_1_fifo_U;
fifo_w1_d1024_A* detect_1_fifo_U;
sc_signal< sc_logic > grp_Seuil_calc2_fu_100_e_read;
sc_signal< sc_logic > grp_Seuil_calc2_fu_100_detect_din;
sc_signal< sc_logic > grp_Seuil_calc2_fu_100_detect_write;
sc_signal< sc_logic > grp_trames_separ2_fu_114_e_read;
sc_signal< sc_logic > grp_trames_separ2_fu_114_detect_dout;
sc_signal< sc_logic > grp_trames_separ2_fu_114_detect_read;
sc_signal< sc_lv<8> > grp_trames_separ2_fu_114_s_din;
sc_signal< sc_logic > grp_trames_separ2_fu_114_s_write;
sc_signal< sc_logic > grp_DOUBLEUR_U_fu_130_e_read;
sc_signal< sc_lv<8> > grp_DOUBLEUR_U_fu_130_s1_din;
sc_signal< sc_logic > grp_DOUBLEUR_U_fu_130_s1_write;
sc_signal< sc_lv<8> > grp_DOUBLEUR_U_fu_130_s2_din;
sc_signal< sc_logic > grp_DOUBLEUR_U_fu_130_s2_write;
sc_signal< sc_logic > dbl2scalc_1_full_n;
sc_signal< sc_logic > dbl2tsep_1_full_n;
sc_signal< sc_lv<8> > dbl2scalc_1_dout;
sc_signal< sc_logic > dbl2scalc_1_empty_n;
sc_signal< sc_lv<1> > detect_1_din;
sc_signal< sc_logic > detect_1_full_n;
sc_signal< sc_lv<8> > dbl2tsep_1_dout;
sc_signal< sc_logic > dbl2tsep_1_empty_n;
sc_signal< sc_lv<1> > detect_1_dout;
sc_signal< sc_logic > detect_1_empty_n;
static const sc_logic ap_const_logic_1;
static const sc_logic ap_const_logic_0;
// Thread declarations
void thread_ap_var_for_const0();
void thread_detect_1_din();
void thread_e_read();
void thread_grp_trames_separ2_fu_114_detect_dout();
void thread_s_din();
void thread_s_write();
};
}
using namespace ap_rtl;
#endif
|
/**
* @license MIT
* @brief Print stuff for types and structs.
*/
#ifndef HUFFMAN_CODING_PRINT_H
#define HUFFMAN_CODING_PRINT_H
///////////////////////////////////////////////////////////////////////////////
#include <ostream>
#include <vector>
#include <deque>
#include <systemc.h>
///////////////////////////////////////////////////////////////////////////////
namespace huffman_coding {
class binary_ostream {
public:
explicit binary_ostream(std::ostream& os)
: _os(os) {}
template<typename T>
binary_ostream& operator<<(const T& x) {
_os << x;
return *this;
}
binary_ostream& operator<<(std::ostream& (*pf)(std::ostream&)) {
pf(_os);
return *this;
}
template<int W>
binary_ostream& operator<<(const sc_uint<W>& x) {
this->print(x);
return *this;
}
private:
std::ostream& _os;
void print(const sc_uint_base&);
};
template<typename T>
binary_ostream& operator<<(binary_ostream& bos, std::vector<T> v) {
auto iter = v.begin();
auto last = v.end() - 1;
for(; iter != last; iter++){
bos << *iter << std::endl;
}
bos << *last;
return bos;
}
template<typename T>
binary_ostream& operator<<(binary_ostream& bos, std::deque<T> v) {
auto iter = v.begin();
auto last = v.end() - 1;
for(; iter != last; iter++){
bos << *iter << std::endl;
}
bos << *last;
return bos;
}
}
///////////////////////////////////////////////////////////////////////////////
#endif // HUFFMAN_CODING_STRUCTS_H
|
#ifndef RISCV_TOP_H
#define RISCV_TOP_H
#include <systemc.h>
#include "axi4.h"
#include "axi4.h"
class Vriscv_top;
class VerilatedVcdC;
//-------------------------------------------------------------
// riscv_top: RTL wrapper class
//-------------------------------------------------------------
class riscv_top: public sc_module
{
public:
sc_in <bool> clk_in;
sc_in <bool> rst_in;
sc_in <bool> intr_in;
sc_in <uint32_t> reset_vector_in;
sc_in <axi4_slave> axi_i_in;
sc_out <axi4_master> axi_i_out;
sc_in <axi4_slave> axi_d_in;
sc_out <axi4_master> axi_d_out;
//-------------------------------------------------------------
// Constructor
//-------------------------------------------------------------
SC_HAS_PROCESS(riscv_top);
riscv_top(sc_module_name name);
//-------------------------------------------------------------
// Trace
//-------------------------------------------------------------
virtual void add_trace(sc_trace_file *vcd, std::string prefix)
{
#undef TRACE_SIGNAL
#define TRACE_SIGNAL(s) sc_trace(vcd,s,prefix + #s)
TRACE_SIGNAL(clk_in);
TRACE_SIGNAL(rst_in);
TRACE_SIGNAL(intr_in);
TRACE_SIGNAL(reset_vector_in);
TRACE_SIGNAL(axi_i_in);
TRACE_SIGNAL(axi_i_out);
TRACE_SIGNAL(axi_d_in);
TRACE_SIGNAL(axi_d_out);
#undef TRACE_SIGNAL
}
void async_outputs(void);
void trace_rtl(void);
void trace_enable(VerilatedVcdC *p);
void trace_enable(VerilatedVcdC *p, sc_core::sc_time start_time);
//-------------------------------------------------------------
// Signals
//-------------------------------------------------------------
private:
sc_signal <bool> m_clk_in;
sc_signal <bool> m_rst_in;
sc_signal <bool> m_axi_i_awready_in;
sc_signal <bool> m_axi_i_wready_in;
sc_signal <bool> m_axi_i_bvalid_in;
sc_signal <uint32_t> m_axi_i_bresp_in;
sc_signal <uint32_t> m_axi_i_bid_in;
sc_signal <bool> m_axi_i_arready_in;
sc_signal <bool> m_axi_i_rvalid_in;
sc_signal <uint32_t> m_axi_i_rdata_in;
sc_signal <uint32_t> m_axi_i_rresp_in;
sc_signal <uint32_t> m_axi_i_rid_in;
sc_signal <bool> m_axi_i_rlast_in;
sc_signal <bool> m_axi_d_awready_in;
sc_signal <bool> m_axi_d_wready_in;
sc_signal <bool> m_axi_d_bvalid_in;
sc_signal <uint32_t> m_axi_d_bresp_in;
sc_signal <uint32_t> m_axi_d_bid_in;
sc_signal <bool> m_axi_d_arready_in;
sc_signal <bool> m_axi_d_rvalid_in;
sc_signal <uint32_t> m_axi_d_rdata_in;
sc_signal <uint32_t> m_axi_d_rresp_in;
sc_signal <uint32_t> m_axi_d_rid_in;
sc_signal <bool> m_axi_d_rlast_in;
sc_signal <bool> m_intr_in;
sc_signal <uint32_t> m_reset_vector_in;
sc_signal <bool> m_axi_i_awvalid_out;
sc_signal <uint32_t> m_axi_i_awaddr_out;
sc_signal <uint32_t> m_axi_i_awid_out;
sc_signal <uint32_t> m_axi_i_awlen_out;
sc_signal <uint32_t> m_axi_i_awburst_out;
sc_signal <bool> m_axi_i_wvalid_out;
sc_signal <uint32_t> m_axi_i_wdata_out;
sc_signal <uint32_t> m_axi_i_wstrb_out;
sc_signal <bool> m_axi_i_wlast_out;
sc_signal <bool> m_axi_i_bready_out;
sc_signal <bool> m_axi_i_arvalid_out;
sc_signal <uint32_t> m_axi_i_araddr_out;
sc_signal <uint32_t> m_axi_i_arid_out;
sc_signal <uint32_t> m_axi_i_arlen_out;
sc_signal <uint32_t> m_axi_i_arburst_out;
sc_signal <bool> m_axi_i_rready_out;
sc_signal <bool> m_axi_d_awvalid_out;
sc_signal <uint32_t> m_axi_d_awaddr_out;
sc_signal <uint32_t> m_axi_d_awid_out;
sc_signal <uint32_t> m_axi_d_awlen_out;
sc_signal <uint32_t> m_axi_d_awburst_out;
sc_signal <bool> m_axi_d_wvalid_out;
sc_signal <uint32_t> m_axi_d_wdata_out;
sc_signal <uint32_t> m_axi_d_wstrb_out;
sc_signal <bool> m_axi_d_wlast_out;
sc_signal <bool> m_axi_d_bready_out;
sc_signal <bool> m_axi_d_arvalid_out;
sc_signal <uint32_t> m_axi_d_araddr_out;
sc_signal <uint32_t> m_axi_d_arid_out;
sc_signal <uint32_t> m_axi_d_arlen_out;
sc_signal <uint32_t> m_axi_d_arburst_out;
sc_signal <bool> m_axi_d_rready_out;
sc_signal<bool> m_tck;
sc_signal<bool> m_tms;
sc_signal<bool> m_tdi;
sc_signal<bool> m_tdo;
public:
Vriscv_top *m_rtl;
#if VM_TRACE
VerilatedVcdC * m_vcd;
bool m_delay_waves;
sc_core::sc_time m_waves_start;
#endif
};
#endif
|
/******************************************************************************
* *
* Copyright (C) 2024 MachineWare GmbH *
* All Rights Reserved *
* *
* This is work is licensed under the terms described in the LICENSE file *
* found in the root directory of this source tree. *
* *
******************************************************************************/
#ifndef VCML_FIFO_H
#define VCML_FIFO_H
#include "vcml/core/types.h"
#include "vcml/core/systemc.h"
namespace vcml {
template <typename T>
class fifo
{
private:
size_t m_capacity;
std::queue<T> m_queue;
public:
fifo(size_t capacity): m_capacity(capacity), m_queue() {}
~fifo() = default;
size_t capacity() const { return m_capacity; }
size_t num_used() const { return m_queue.size(); }
size_t num_free() const { return m_capacity - m_queue.size(); }
bool empty() const { return m_queue.empty(); }
bool full() const { return m_queue.size() == m_capacity; }
T pop() {
T top = m_queue.front();
m_queue.pop();
return top;
}
bool push(const T& val) {
if (m_queue.size() >= m_capacity)
return false;
m_queue.push(val);
return true;
}
void reset() { std::queue<T>().swap(m_queue); }
};
} // namespace vcml
#endif
|
/*
* Copyright 2018 Sergey Khabarov, [email protected]
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __DEBUGGER_RIVERLIB_EXECUTE_H__
#define __DEBUGGER_RIVERLIB_EXECUTE_H__
#include <systemc.h>
#include "../river_cfg.h"
#include "arith/int_div.h"
#include "arith/int_mul.h"
#include "arith/shift.h"
namespace debugger {
SC_MODULE(InstrExecute) {
sc_in<bool> i_clk;
sc_in<bool> i_nrst; // Reset active LOW
sc_in<bool> i_pipeline_hold; // Hold execution by any reason
sc_in<bool> i_d_valid; // Decoded instruction is valid
sc_in<sc_uint<BUS_ADDR_WIDTH>> i_d_pc; // Instruction pointer on decoded instruction
sc_in<sc_uint<32>> i_d_instr; // Decoded instruction value
sc_in<bool> i_wb_done; // write back done (Used to clear hazardness)
sc_in<bool> i_memop_store; // Store to memory operation
sc_in<bool> i_memop_load; // Load from memoru operation
sc_in<bool> i_memop_sign_ext; // Load memory value with sign extending
sc_in<sc_uint<2>> i_memop_size; // Memory transaction size
sc_in<bool> i_unsigned_op; // Unsigned operands
sc_in<bool> i_rv32; // 32-bits instruction
sc_in<bool> i_compressed; // C-extension (2-bytes length)
sc_in<sc_bv<ISA_Total>> i_isa_type; // Type of the instruction's structure (ISA spec.)
sc_in<sc_bv<Instr_Total>> i_ivec; // One pulse per supported instruction.
sc_in<bool> i_unsup_exception; // Unsupported instruction exception
sc_in<bool> i_dport_npc_write; // Write npc value from debug port
sc_in<sc_uint<BUS_ADDR_WIDTH>> i_dport_npc; // Debug port npc value to write
sc_out<sc_uint<5>> o_radr1; // Integer register index 1
sc_in<sc_uint<RISCV_ARCH>> i_rdata1; // Integer register value 1
sc_out<sc_uint<5>> o_radr2; // Integer register index 2
sc_in<sc_uint<RISCV_ARCH>> i_rdata2; // Integer register value 2
sc_out<sc_uint<5>> o_res_addr; // Address to store result of the instruction (0=do not store)
sc_out<sc_uint<RISCV_ARCH>> o_res_data; // Value to store
sc_out<bool> o_pipeline_hold; // Hold pipeline while 'writeback' not done or multi-clock instruction.
sc_out<sc_uint<12>> o_csr_addr; // CSR address. 0 if not a CSR instruction with xret signals mode switching
sc_out<bool> o_csr_wena; // Write new CSR value
sc_in<sc_uint<RISCV_ARCH>> i_csr_rdata; // CSR current value
sc_out<sc_uint<RISCV_ARCH>> o_csr_wdata; // CSR new value
sc_in<bool> i_trap_valid; // async trap event
sc_in<sc_uint<BUS_ADDR_WIDTH>> i_trap_pc; // jump to address
// exceptions:
sc_out<sc_uint<BUS_ADDR_WIDTH>> o_ex_npc; // npc on before trap
sc_out<bool> o_ex_illegal_instr;
sc_out<bool> o_ex_unalign_store;
sc_out<bool> o_ex_unalign_load;
sc_out<bool> o_ex_breakpoint;
sc_out<bool> o_ex_ecall;
sc_out<bool> o_memop_sign_ext; // Load data with sign extending
sc_out<bool> o_memop_load; // Load data instruction
sc_out<bool> o_memop_store; // Store data instruction
sc_out<sc_uint<2>> o_memop_size; // 0=1bytes; 1=2bytes; 2=4bytes; 3=8bytes
sc_out<sc_uint<BUS_ADDR_WIDTH>> o_memop_addr;// Memory access address
sc_out<bool> o_pre_valid; // pre-latch of valid
sc_out<bool> o_valid; // Output is valid
sc_out<sc_uint<BUS_ADDR_WIDTH>> o_pc; // Valid instruction pointer
sc_out<sc_uint<BUS_ADDR_WIDTH>> o_npc; // Next instruction pointer. Next decoded pc must match to this value or will be ignored.
sc_out<sc_uint<32>> o_instr; // Valid instruction value
sc_out<bool> o_call; // CALL pseudo instruction detected
sc_out<bool> o_ret; // RET pseudoinstruction detected
sc_out<bool> o_mret; // MRET.
sc_out<bool> o_uret; // MRET.
void comb();
void registers();
SC_HAS_PROCESS(InstrExecute);
InstrExecute(sc_module_name name_);
virtual ~InstrExecute();
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
enum EMultiCycleInstruction {
Multi_MUL,
Multi_DIV,
Multi_Total
};
struct multi_arith_type {
sc_signal<sc_uint<RISCV_ARCH>> arr[Multi_Total];
};
struct RegistersType {
sc_signal<bool> d_valid; // Valid decoded instruction latch
sc_signal<sc_uint<BUS_ADDR_WIDTH>> pc;
sc_signal<sc_uint<BUS_ADDR_WIDTH>> npc;
sc_signal<sc_uint<32>> instr;
sc_uint<5> res_addr;
sc_signal<sc_uint<RISCV_ARCH>> res_val;
sc_signal<bool> memop_load;
sc_signal<bool> memop_store;
bool memop_sign_ext;
sc_uint<2> memop_size;
sc_signal<sc_uint<BUS_ADDR_WIDTH>> memop_addr;
sc_signal<sc_uint<5>> multi_res_addr; // latched output reg. address while multi-cycle instruction
sc_signal<sc_uint<BUS_ADDR_WIDTH>> multi_pc; // latched pc-value while multi-cycle instruction
sc_signal<sc_uint<BUS_ADDR_WIDTH>> multi_npc; // latched npc-value while multi-cycle instruction
sc_signal<sc_uint<32>> multi_instr; // Multi-cycle instruction is under processing
sc_signal<bool> multi_ena[Multi_Total]; // Enable pulse for Operation that takes more than 1 clock
sc_signal<bool> multi_rv32; // Long operation with 32-bits operands
sc_signal<bool> multi_unsigned; // Long operation with unsiged operands
sc_signal<bool> multi_residual_high; // Flag for Divider module: 0=divsion output; 1=residual output
// Flag for multiplier: 0=usual; 1=get high bits
sc_signal<bool> multiclock_ena;
sc_signal<sc_uint<RISCV_ARCH>> multi_a1; // Multi-cycle operand 1
sc_signal<sc_uint<RISCV_ARCH>> multi_a2; // Multi-cycle operand 2
sc_signal<sc_uint<5>> hazard_addr0; // Updated register address on previous step
sc_signal<sc_uint<5>> hazard_addr1; // Updated register address on pre-previous step
sc_signal<sc_uint<2>> hazard_depth; // Number of modificated registers that wasn't done yet
sc_signal<bool> call;
sc_signal<bool> ret;
} v, r;
sc_signal<bool> w_hazard_detected;
multi_arith_type wb_arith_res;
sc_signal<bool> w_arith_valid[Multi_Total];
sc_signal<bool> w_arith_busy[Multi_Total];
bool w_exception_store;
bool w_exception_load;
sc_signal<sc_uint<RISCV_ARCH>> wb_shifter_a1; // Shifters operand 1
sc_signal<sc_uint<6>> wb_shifter_a2; // Shifters operand 2
sc_signal<sc_uint<RISCV_ARCH>> wb_sll;
sc_signal<sc_uint<RISCV_ARCH>> wb_sllw;
sc_signal<sc_uint<RISCV_ARCH>> wb_srl;
sc_signal<sc_uint<RISCV_ARCH>> wb_srlw;
sc_signal<sc_uint<RISCV_ARCH>> wb_sra;
sc_signal<sc_uint<RISCV_ARCH>> wb_sraw;
IntMul *mul0;
IntDiv *div0;
Shifter *sh0;
};
} // namespace debugger
#endif // __DEBUGGER_RIVERLIB_EXECUTE_H__
|
//
// Copyright 2022 Sergey Khabarov, [email protected]
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
#pragma once
#include <systemc.h>
#include "../../techmap/mem/ram_cache_bwe_tech.h"
#include "../../techmap/mem/ram_tech.h"
#include "api_core.h"
namespace debugger {
template<int abus = 64, // system bus address width (64 or 32 bits)
int ibits = 6, // lines memory address width (usually 6..8)
int lnbits = 5, // One line bits: log2(bytes_per_line)
int flbits = 4, // total flags number saved with address tag
int snoop = 0> // 0 Snoop port disabled; 1 Enabled (L2 caching)
SC_MODULE(TagMem) {
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
sc_in<sc_uint<abus>> i_addr;
sc_in<sc_uint<(1 << lnbits)>> i_wstrb;
sc_in<sc_biguint<(8 * (1 << lnbits))>> i_wdata;
sc_in<sc_uint<flbits>> i_wflags;
sc_out<sc_uint<abus>> o_raddr;
sc_out<sc_biguint<(8 * (1 << lnbits))>> o_rdata;
sc_out<sc_uint<flbits>> o_rflags;
sc_out<bool> o_hit;
// L2 snoop port, active when snoop = 1
sc_in<sc_uint<abus>> i_snoop_addr;
sc_out<sc_uint<flbits>> o_snoop_flags;
void comb();
void registers();
SC_HAS_PROCESS(TagMem);
TagMem(sc_module_name name,
bool async_reset);
virtual ~TagMem();
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
bool async_reset_;
static const int TAG_BITS = ((abus - ibits) - lnbits);
static const int TAG_WITH_FLAGS = (TAG_BITS + flbits);
struct TagMem_registers {
sc_signal<sc_uint<TAG_BITS>> tagaddr;
sc_signal<sc_uint<ibits>> index;
sc_signal<sc_uint<TAG_BITS>> snoop_tagaddr;
} v, r;
void TagMem_r_reset(TagMem_registers &iv) {
iv.tagaddr = 0;
iv.index = 0;
iv.snoop_tagaddr = 0;
}
sc_signal<sc_uint<ibits>> wb_index;
sc_signal<sc_uint<TAG_WITH_FLAGS>> wb_tago_rdata;
sc_signal<sc_uint<TAG_WITH_FLAGS>> wb_tagi_wdata;
sc_signal<bool> w_tagi_we;
sc_signal<sc_uint<ibits>> wb_snoop_index;
sc_signal<sc_uint<TAG_BITS>> wb_snoop_tagaddr;
sc_signal<sc_uint<TAG_WITH_FLAGS>> wb_tago_snoop_rdata;
ram_cache_bwe_tech<ibits, (8 * (1 << lnbits))> *data0;
ram_tech<ibits, TAG_WITH_FLAGS> *tag0;
ram_tech<ibits, TAG_WITH_FLAGS> *tagsnoop0;
};
template<int abus, int ibits, int lnbits, int flbits, int snoop>
TagMem<abus, ibits, lnbits, flbits, snoop>::TagMem(sc_module_name name,
bool async_reset)
: sc_module(name),
i_clk("i_clk"),
i_nrst("i_nrst"),
i_addr("i_addr"),
i_wstrb("i_wstrb"),
i_wdata("i_wdata"),
i_wflags("i_wflags"),
o_raddr("o_raddr"),
o_rdata("o_rdata"),
o_rflags("o_rflags"),
o_hit("o_hit"),
i_snoop_addr("i_snoop_addr"),
o_snoop_flags("o_snoop_flags") {
async_reset_ = async_reset;
data0 = 0;
tag0 = 0;
tagsnoop0 = 0;
// bwe = byte write enable
data0 = new ram_cache_bwe_tech<ibits,
(8 * (1 << lnbits))>("data0");
data0->i_clk(i_clk);
data0->i_addr(wb_index);
data0->i_wena(i_wstrb);
data0->i_wdata(i_wdata);
data0->o_rdata(o_rdata);
tag0 = new ram_tech<ibits,
TAG_WITH_FLAGS>("tag0");
tag0->i_clk(i_clk);
tag0->i_addr(wb_index);
tag0->i_wena(w_tagi_we);
tag0->i_wdata(wb_tagi_wdata);
tag0->o_rdata(wb_tago_rdata);
// generate
if (snoop) {
tagsnoop0 = new ram_tech<ibits,
TAG_WITH_FLAGS>("tagsnoop0");
tagsnoop0->i_clk(i_clk);
tagsnoop0->i_addr(wb_snoop_index);
tagsnoop0->i_wena(w_tagi_we);
tagsnoop0->i_wdata(wb_tagi_wdata);
tagsnoop0->o_rdata(wb_tago_snoop_rdata);
} else {
wb_tago_snoop_rdata = 0;
}
// endgenerate
SC_METHOD(comb);
sensitive << i_nrst;
sensitive << i_addr;
sensitive << i_wstrb;
sensitive << i_wdata;
sensitive << i_wflags;
sensitive << i_snoop_addr;
sensitive << wb_index;
sensitive << wb_tago_rdata;
sensitive << wb_tagi_wdata;
sensitive << w_tagi_we;
sensitive << wb_snoop_index;
sensitive << wb_snoop_tagaddr;
sensitive << wb_tago_snoop_rdata;
sensitive << r.tagaddr;
sensitive << r.index;
sensitive << r.snoop_tagaddr;
SC_METHOD(registers);
sensitive << i_nrst;
sensitive << i_clk.pos();
}
template<int abus, int ibits, int lnbits, int flbits, int snoop>
TagMem<abus, ibits, lnbits, flbits, snoop>::~TagMem() {
if (data0) {
delete data0;
}
if (tag0) {
delete tag0;
}
if (tagsnoop0) {
delete tagsnoop0;
}
}
template<int abus, int ibits, int lnbits, int flbits, int snoop>
void TagMem<abus, ibits, lnbits, flbits, snoop>::generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd) {
std::string pn(name());
if (o_vcd) {
sc_trace(o_vcd, i_addr, i_addr.name());
sc_trace(o_vcd, i_wstrb, i_wstrb.name());
sc_trace(o_vcd, i_wdata, i_wdata.name());
sc_trace(o_vcd, i_wflags, i_wflags.name());
sc_trace(o_vcd, o_raddr, o_raddr.name());
sc_trace(o_vcd, o_rdata, o_rdata.name());
sc_trace(o_vcd, o_rflags, o_rflags.name());
sc_trace(o_vcd, o_hit, o_hit.name());
sc_trace(o_vcd, i_snoop_addr, i_snoop_addr.name());
sc_trace(o_vcd, o_snoop_flags, o_snoop_flags.name());
sc_trace(o_vcd, r.tagaddr, pn + ".r_tagaddr");
sc_trace(o_vcd, r.index, pn + ".r_index");
sc_trace(o_vcd, r.snoop_tagaddr, pn + ".r_snoop_tagaddr");
}
}
template<int abus, int ibits, int lnbits, int flbits, int snoop>
void TagMem<abus, ibits, lnbits, flbits, snoop>::comb() {
sc_uint<ibits> vb_index;
sc_uint<abus> vb_raddr;
sc_uint<TAG_WITH_FLAGS> vb_tagi_wdata;
bool v_hit;
sc_uint<ibits> vb_snoop_index;
sc_uint<TAG_BITS> vb_snoop_tagaddr;
sc_uint<flbits> vb_snoop_flags;
vb_index = 0;
vb_raddr = 0;
vb_tagi_wdata = 0;
v_hit = 0;
vb_snoop_index = 0;
vb_snoop_tagaddr = 0;
vb_snoop_flags = 0;
v = r;
if (r.tagaddr.read() == wb_tago_rdata.read()((TAG_BITS - 1), 0)) {
v_hit = wb_tago_rdata.read()[TAG_BITS]; // valid bit
}
vb_raddr((abus - 1), (ibits + lnbits)) = wb_tago_rdata.read()((TAG_BITS - 1), 0);
vb_raddr(((ibits + lnbits) - 1), lnbits) = r.index;
vb_index = i_addr.read()(((ibits + lnbits) - 1), lnbits);
vb_tagi_wdata((TAG_BITS - 1), 0) = i_addr.read()((abus - 1), (ibits + lnbits));
vb_tagi_wdata((TAG_WITH_FLAGS - 1), TAG_BITS) = i_wflags;
if (snoop == 1) {
vb_snoop_flags = wb_tago_snoop_rdata.read()((TAG_WITH_FLAGS - 1), TAG_BITS);
vb_snoop_index = i_snoop_addr.read()(((ibits + lnbits) - 1), lnbits);
vb_snoop_tagaddr = i_snoop_addr.read()((abus - 1), (ibits + lnbits));
if (i_wstrb.read().or_reduce() == 1) {
vb_snoop_index = vb_index;
}
if (r.snoop_tagaddr.read() != wb_tago_snoop_rdata.read()((TAG_BITS - 1), 0)) {
vb_snoop_flags = 0;
}
}
v.tagaddr = vb_tagi_wdata((TAG_BITS - 1), 0);
v.index = vb_index;
v.snoop_tagaddr = vb_snoop_tagaddr;
if (!async_reset_ && i_nrst.read() == 0) {
TagMem_r_reset(v);
}
wb_index = vb_index;
w_tagi_we = i_wstrb.read().or_reduce();
wb_tagi_wdata = vb_tagi_wdata;
o_raddr = vb_raddr;
o_rflags = wb_tago_rdata.read()((TAG_WITH_FLAGS - 1), TAG_BITS);
o_hit = v_hit;
wb_snoop_index = vb_snoop_index;
wb_snoop_tagaddr = vb_snoop_tagaddr;
o_snoop_flags = vb_snoop_flags;
}
template<int abus, int ibits, int lnbits, int flbits, int snoop>
void TagMem<abus, ibits, lnbits, flbits, snoop>::registers() {
if (async_reset_ && i_nrst.read() == 0) {
TagMem_r_reset(r);
} else {
r = v;
}
}
} // namespace debugger
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
#ifndef __ZYNQ_UTLRA_PS_E_TLM_H__
#define __ZYNQ_ULTRA_PS_E_TLM_H__
#include "systemc.h"
#include "xtlm.h"
#include "xtlm_adaptors/xaximm_xtlm2tlm.h"
#include "xtlm_adaptors/xaximm_tlm2xtlm.h"
#include "tlm_utils/simple_initiator_socket.h"
#include "tlm_utils/simple_target_socket.h"
#include <vector>
#include "genattr.h"
#include "xilinx_zynqmp_vitis.h"
#include "b_transport_converter.h"
#include "utils/xtlm_aximm_fifo.h"
/***************************************************************************************
*
* A Simple Converter which converts Remote-port's simplae_intiator_sockets<32>->b_transport()
* calls to xTLM sockets bn_transport_x() calls..
*
* This is Only specific to remote-port so not creating seperate header for it.
*
***************************************************************************************/
template <int IN_WIDTH, int OUT_WIDTH>
class rptlm2xtlm_converter : public sc_module{
public:
tlm::tlm_target_socket<IN_WIDTH> target_socket;
xtlm::xtlm_aximm_initiator_socket wr_socket;
xtlm::xtlm_aximm_initiator_socket rd_socket;
rptlm2xtlm_converter<IN_WIDTH, OUT_WIDTH>(sc_module_name name);//:sc_module(name)
void registerUserExtensionHandlerCallback(
void (*callback)(xtlm::aximm_payload*,
const tlm::tlm_generic_payload*));
private:
b_transport_converter<IN_WIDTH, OUT_WIDTH> m_btrans_conv;
xtlm::xaximm_tlm2xtlm_t<OUT_WIDTH> xtlm_bridge;
};
/***************************************************************************************
* Global method, get registered with tlm2xtlm bridge
* This function is called when tlm2xtlm bridge convert tlm payload to xtlm payload.
*
* caller: tlm2xtlm bridge
* purpose: To get master id and other parameters out of genattr_extension
* and use master id to AxUSER PIN of xtlm payload.
*
*
***************************************************************************************/
extern void get_extensions_from_tlm(xtlm::aximm_payload* xtlm_pay, const tlm::tlm_generic_payload* gp);
/***************************************************************************************
* Global method, get registered with xtlm2tlm bridge
* This function is called when xtlm2tlm bridge convert xtlm payload to tlm payload.
*
* caller: xtlm2tlm bridge
* purpose: To create and add master id and other parameters to genattr_extension.
* Master id red from AxID PIN of xtlm payload.
*
*
***************************************************************************************/
extern void add_extensions_to_tlm(const xtlm::aximm_payload* xtlm_pay, tlm::tlm_generic_payload* gp);
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// //
// File: zynq_ultra_ps_e_tlm.h //
// //
// Description: zynq_ultra_ps_e_tlm class is a sc_module, act as intermediate layer between //
// xilinx_zynqmp qemu wrapper and Vivado generated systemc simulation ip wrapper. //
// it's basically created for supporting tlm based xilinx_zynqmp from xtlm based vivado //
// generated systemc wrapper. this wrapper is live only when SELECTED_SIM_MODEL is set //
// to tlm. it's also act as bridge between vivado wrapper and xilinx_zynqmp wrapper. //
// it fill the the gap between input/output ports of vivado generated wrapper to //
// xilinx_zynqmp wrapper signals. This wrapper is auto generated by ttcl scripts //
// based on IP configuration in vivado. //
// //
// //
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
class zynq_ultra_ps_e_tlm : public sc_core::sc_module {
public:
// Non-AXI ports are declared here
sc_core::sc_in<bool> maxihpm0_fpd_aclk;
sc_core::sc_in<bool> saxihp0_fpd_aclk;
sc_core::sc_in<bool> saxihp1_fpd_aclk;
sc_core::sc_in<sc_dt::sc_bv<1> > pl_ps_irq0;
sc_core::sc_out<bool> pl_resetn0;
sc_core::sc_out<bool> pl_clk0;
sc_core::sc_out<bool> pl_clk1;
// Xtlm aximm slave sockets are delcared here. these XTLM sockets will hierachically bound with
// slave sockets defined in vivado generated wrapper.
xtlm::xtlm_aximm_target_socket* S_AXI_HP0_FPD_wr_socket;
xtlm::xtlm_aximm_target_socket* S_AXI_HP0_FPD_rd_socket;
xtlm::xtlm_aximm_target_socket* S_AXI_HP1_FPD_wr_socket;
xtlm::xtlm_aximm_target_socket* S_AXI_HP1_FPD_rd_socket;
// Xtlm aximm master socket/s is/are delcared here. these XTLM sockets will hierachically bound with
// master sockets defined in vivado generated wrapper.
xtlm::xtlm_aximm_initiator_socket* M_AXI_HPM0_FPD_wr_socket;
xtlm::xtlm_aximm_initiator_socket* M_AXI_HPM0_FPD_rd_socket;
//constructor having three paramters
// 1. module name in sc_module_name objec,
// 2. reference to map object of name and integer value pairs
// 3. reference to map object of name and string value pairs
// All the model parameters (integer and string) which are configuration parameters
// of ZynqUltraScale+ IP propogated from Vivado
zynq_ultra_ps_e_tlm (sc_core::sc_module_name name,
xsc::common_cpp::properties&);
~zynq_ultra_ps_e_tlm ();
SC_HAS_PROCESS( zynq_ultra_ps_e_tlm );
private:
//zynqmp tlm wrapper provided by Edgar
//module with interfaces of standard tlm
//and input/output ports at signal level
zynqmp_tlm_vitis::xilinx_zynqmp* m_zynqmp_tlm_model;
// Xtlm2tlm_t Bridges
// Converts Xtlm transactions to tlm transactions
// Bridge's Xtlm wr/rd target sockets binds with
// xtlm initiator sockets of zynq_ultra_ps_e_tlm and tlm simple initiator
// socket with xilinx_zynqmp's target socket
xtlm::xaximm_xtlm2tlm_t<32,32> S_AXI_HP0_FPD_xtlm_brdg;
xtlm::xtlm_aximm_fifo *S_AXI_HP0_FPD_buff;
xtlm::xaximm_xtlm2tlm_t<128,32> S_AXI_HP1_FPD_xtlm_brdg;
xtlm::xtlm_aximm_fifo *S_AXI_HP1_FPD_buff;
// This Bridges converts b_transport to nb_transports and also
// Converts tlm transactions to xtlm transactions.
// Bridge's tlm simple target socket binds with
// simple initiator socket of xilinx_zynqmp and xtlm
// socket with xilinx_zynqmp's simple target socket
rptlm2xtlm_converter<32, 32 > m_rp_bridge_M_AXI_HPM0_FPD;
// sc_clocks for generating pl clocks
// output pins pl_clk0..3 are drived by these clocks
sc_core::sc_clock pl_clk0_clk;
sc_core::sc_clock pl_clk1_clk;
//Method which is sentive to pl_clk0_clk sc_clock object
//pl_clk0 pin written based on pl_clk0_clk clock value
void trigger_pl_clk0_pin();
//Method which is sentive to pl_clk1_clk sc_clock object
//pl_clk1 pin written based on pl_clk1_clk clock value
void trigger_pl_clk1_pin();
void pl_ps_irq0_method();
//pl_resetn0 output reset pin get toggle when emio bank 2's 31th signal gets toggled
//EMIO[2] bank 31th(GPIO[95] signal)acts as reset signal to the PL(refer Zynq UltraScale+ TRM, page no:761)
void pl_resetn0_trigger();
sc_signal<bool> qemu_rst;
void start_of_simulation();
};
#endif
|
// Copyright 2019 Glenn Ramalho - RFIDo Design
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// This code was based off the work from Espressif Systems covered by the
// License:
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <systemc.h>
#include "gn_semaphore.h"
#include "clockpacer.h"
#include "spimod.h"
#include "info.h"
#include "esp32-hal-spi.h"
#include "esp32-hal.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"
#include "rom/ets_sys.h"
#include "esp_attr.h"
//#include "esp_intr.h"
#include "rom/gpio.h"
#include "soc/spi_reg.h"
#include "soc/spi_struct.h"
#include "soc/io_mux_reg.h"
#include "soc/gpio_sig_map.h"
#include "soc/dport_reg.h"
#define SPI_CLK_IDX(p) ((p==0)?SPICLK_OUT_IDX:((p==1)?SPICLK_OUT_IDX:((p==2)?HSPICLK_OUT_IDX:((p==3)?VSPICLK_OUT_IDX:0))))
#define SPI_MISO_IDX(p) ((p==0)?SPIQ_OUT_IDX:((p==1)?SPIQ_OUT_IDX:((p==2)?HSPIQ_OUT_IDX:((p==3)?VSPIQ_OUT_IDX:0))))
#define SPI_MOSI_IDX(p) ((p==0)?SPID_IN_IDX:((p==1)?SPID_IN_IDX:((p==2)?HSPID_IN_IDX:((p==3)?VSPID_IN_IDX:0))))
#define SPI_SPI_SS_IDX(n) ((n==0)?SPICS0_OUT_IDX:((n==1)?SPICS1_OUT_IDX:((n==2)?SPICS2_OUT_IDX:SPICS0_OUT_IDX)))
#define SPI_HSPI_SS_IDX(n) ((n==0)?HSPICS0_OUT_IDX:((n==1)?HSPICS1_OUT_IDX:((n==2)?HSPICS2_OUT_IDX:HSPICS0_OUT_IDX)))
#define SPI_VSPI_SS_IDX(n) ((n==0)?VSPICS0_OUT_IDX:((n==1)?VSPICS1_OUT_IDX:((n==2)?VSPICS2_OUT_IDX:VSPICS0_OUT_IDX)))
#define SPI_SS_IDX(p, n) ((p==0)?SPI_SPI_SS_IDX(n):((p==1)?SPI_SPI_SS_IDX(n):((p==2)?SPI_HSPI_SS_IDX(n):((p==3)?SPI_VSPI_SS_IDX(n):0))))
#define SPI_INUM(u) (2)
#define SPI_INTR_SOURCE(u) ((u==0)?ETS_SPI0_INTR_SOURCE:((u==1)?ETS_SPI1_INTR_SOURCE:((u==2)?ETS_SPI2_INTR_SOURCE:((p==3)?ETS_SPI3_INTR_SOURCE:0))))
struct spi_struct_t {
spi_dev_t * dev;
#if !CONFIG_DISABLE_HAL_LOCKS
xSemaphoreHandle lock;
#endif
uint8_t num;
};
gn_semaphore i_gn_semaphore_spi2("SPI2", 1);
gn_semaphore i_gn_semaphore_spi3("SPI3", 1);
#if CONFIG_DISABLE_HAL_LOCKS
#define SPI_MUTEX_LOCK()
#define SPI_MUTEX_UNLOCK()
static spi_t _spi_bus_array[4] = {
{NULL, 0}, /* The model does not yet support this SPI */
{NULL, 1}, /* The model does not yet support this SPI */
{SPI2, 2},
{SPI3, 3}
};
#else
#define SPI_MUTEX_LOCK() do {} while (xSemaphoreTake(spi->lock, portMAX_DELAY) != pdPASS)
#define SPI_MUTEX_UNLOCK() xSemaphoreGive(spi->lock)
static spi_t _spi_bus_array[4] = {
{NULL, NULL, 0}, /* The model does not yet support this SPI */
{NULL, NULL, 1}, /* The model does not yet support this SPI */
{&SPI2, NULL, 2},
{&SPI3, NULL, 3}
};
#endif
void spiAttachSCK(spi_t * spi, int8_t sck)
{
if(!spi) {
return;
}
else if (spi->dev == NULL) {
PRINTF_INFO("HALSPI", "Attempting to access unsupported SPI%d",
spi->num);
return;
}
if(sck < 0) {
if(spi->num == HSPI) {
sck = 14;
} else if(spi->num == VSPI) {
sck = 18;
} else {
sck = 6;
}
}
pinMode(sck, OUTPUT);
pinMatrixOutAttach(sck, SPI_CLK_IDX(spi->num), false, false);
}
void spiAttachMISO(spi_t * spi, int8_t miso)
{
if(!spi) {
return;
}
else if (spi->dev == NULL) {
PRINTF_INFO("HALSPI", "Attempting to access unsupported SPI%d",
spi->num);
return;
}
if(miso < 0) {
if(spi->num == HSPI) {
miso = 12;
} else if(spi->num == VSPI) {
miso = 19;
} else {
miso = 7;
}
}
SPI_MUTEX_LOCK();
pinMode(miso, INPUT);
pinMatrixInAttach(miso, SPI_MISO_IDX(spi->num), false);
SPI_MUTEX_UNLOCK();
}
void spiAttachMOSI(spi_t * spi, int8_t mosi)
{
if(!spi) {
return;
}
else if (spi->dev == NULL) {
PRINTF_INFO("HALSPI", "Attempting to access unsupported SPI%d",
spi->num);
return;
}
if(mosi < 0) {
if(spi->num == HSPI) {
mosi = 13;
} else if(spi->num == VSPI) {
mosi = 23;
} else {
mosi = 8;
}
}
pinMode(mosi, OUTPUT);
pinMatrixOutAttach(mosi, SPI_MOSI_IDX(spi->num), false, false);
}
void spiDetachSCK(spi_t * spi, int8_t sck)
{
if(!spi) {
return;
}
else if (spi->dev == NULL) {
PRINTF_INFO("HALSPI", "Attempting to access unsupported SPI%d",
spi->num);
return;
}
if(sck < 0) {
if(spi->num == HSPI) {
sck = 14;
} else if(spi->num == VSPI) {
sck = 18;
} else {
sck = 6;
}
}
pinMatrixOutDetach(sck, false, false);
pinMode(sck, INPUT);
}
void spiDetachMISO(spi_t * spi, int8_t miso)
{
if(!spi) {
return;
}
if(miso < 0) {
if(spi->num == HSPI) {
miso = 12;
} else if(spi->num == VSPI) {
miso = 19;
} else {
miso = 7;
}
}
pinMatrixInDetach(SPI_MISO_IDX(spi->num), false, false);
pinMode(miso, INPUT);
}
void spiDetachMOSI(spi_t * spi, int8_t mosi)
{
if(!spi) {
return;
}
else if (spi->dev == NULL) {
PRINTF_INFO("HALSPI", "Attempting to access unsupported SPI%d",
spi->num);
return;
}
if(mosi < 0) {
if(spi->num == HSPI) {
mosi = 13;
} else if(spi->num == VSPI) {
mosi = 23;
} else {
mosi = 8;
}
}
pinMatrixOutDetach(mosi, false, false);
pinMode(mosi, INPUT);
}
void spiAttachSS(spi_t * spi, uint8_t cs_num, int8_t ss)
{
if(!spi) {
return;
}
else if (spi->dev == NULL) {
PRINTF_INFO("HALSPI", "Attempting to access unsupported SPI%d",
spi->num);
return;
}
if(cs_num > 2) {
return;
}
if(ss < 0) {
cs_num = 0;
if(spi->num == HSPI) {
ss = 15;
} else if(spi->num == VSPI) {
ss = 5;
} else {
ss = 11;
}
}
pinMode(ss, OUTPUT);
pinMatrixOutAttach(ss, SPI_SS_IDX(spi->num, cs_num), false, false);
spiEnableSSPins(spi, (1 << cs_num));
}
void spiDetachSS(spi_t * spi, int8_t ss)
{
if(!spi) {
return;
}
else if (spi->dev == NULL) {
PRINTF_INFO("HALSPI", "Attempting to access unsupported SPI%d",
spi->num);
return;
}
if(ss < 0) {
if(spi->num == HSPI) {
ss = 15;
} else if(spi->num == VSPI) {
ss = 5;
} else {
ss = 11;
}
}
pinMatrixOutDetach(ss, false, false);
pinMode(ss, INPUT);
}
void _update(spi_t *spi) {
if (spi->num == HSPI) hspiptr->update();
else if (spi->num == VSPI) vspiptr->update();
}
void _waitdone(spi_t *spi) {
if (spi->num == HSPI) hspiptr->waitdone();
else if (spi->num == VSPI) vspiptr->waitdone();
}
void spiEnableSSPins(spi_t * spi, uint8_t cs_mask)
{
if(!spi) {
return;
}
else if (spi->dev == NULL) {
PRINTF_INFO("HALSPI", "Attempting to access unsupported SPI%d",
spi->num);
return;
}
SPI_MUTEX_LOCK();
spi->dev->pin.val &= ~(cs_mask & SPI_CS_MASK_ALL);
_update(spi);
SPI_MUTEX_UNLOCK();
}
void spiDisableSSPins(spi_t * spi, uint8_t cs_mask)
{
if(!spi) {
return;
}
else if (spi->dev == NULL) {
PRINTF_INFO("HALSPI", "Attempting to access unsupported SPI%d",
spi->num);
return;
}
SPI_MUTEX_LOCK();
spi->dev->pin.val |= (cs_mask & SPI_CS_MASK_ALL);
_update(spi);
SPI_MUTEX_UNLOCK();
}
void spiSSEnable(spi_t * spi)
{
if(!spi) {
return;
}
else if (spi->dev == NULL) {
PRINTF_INFO("HALSPI", "Attempting to access unsupported SPI%d",
spi->num);
return;
}
SPI_MUTEX_LOCK();
spi->dev->user.cs_setup = 1;
spi->dev->user.cs_hold = 1;
_update(spi);
SPI_MUTEX_UNLOCK();
}
void spiSSDisable(spi_t * spi)
{
if(!spi) {
return;
}
else if (spi->dev == NULL) {
PRINTF_INFO("HALSPI", "Attempting to access unsupported SPI%d",
spi->num);
return;
}
SPI_MUTEX_LOCK();
spi->dev->user.cs_setup = 0;
spi->dev->user.cs_hold = 0;
_update(spi);
SPI_MUTEX_UNLOCK();
}
void spiSSSet(spi_t * spi)
{
if(!spi) {
return;
}
else if (spi->dev == NULL) {
PRINTF_INFO("HALSPI", "Attempting to access unsupported SPI%d",
spi->num);
return;
}
SPI_MUTEX_LOCK();
spi->dev->pin.cs_keep_active = 1;
_update(spi);
SPI_MUTEX_UNLOCK();
}
void spiSSClear(spi_t * spi)
{
if(!spi) {
return;
}
else if (spi->dev == NULL) {
PRINTF_INFO("HALSPI", "Attempting to access unsupported SPI%d",
spi->num);
return;
}
SPI_MUTEX_LOCK();
spi->dev->pin.cs_keep_active = 0;
_update(spi);
SPI_MUTEX_UNLOCK();
}
uint32_t spiGetClockDiv(spi_t * spi)
{
if(!spi) {
return 0;
}
else if (spi->dev == NULL) {
PRINTF_INFO("HALSPI", "Attempting to access unsupported SPI%d",
spi->num);
return 0;
}
return spi->dev->clock.val;
}
void spiSetClockDiv(spi_t * spi, uint32_t clockDiv)
{
if(!spi) {
return;
}
else if (spi->dev == NULL) {
PRINTF_INFO("HALSPI", "Attempting to access unsupported SPI%d",
spi->num);
return;
}
SPI_MUTEX_LOCK();
spi->dev->clock.val = clockDiv;
_update(spi);
SPI_MUTEX_UNLOCK();
}
uint8_t spiGetDataMode(spi_t * spi)
{
if(!spi) {
return 0;
}
else if (spi->dev == NULL) {
PRINTF_INFO("HALSPI", "Attempting to access unsupported SPI%d",
spi->num);
return 0;
}
bool idleEdge = spi->dev->pin.ck_idle_edge;
bool outEdge = spi->dev->user.ck_out_edge;
if(idleEdge) {
if(outEdge) {
return SPI_MODE2;
}
return SPI_MODE3;
}
if(outEdge) {
return SPI_MODE1;
}
return SPI_MODE0;
}
void spiSetDataMode(spi_t * spi, uint8_t dataMode)
{
if(!spi) {
return;
}
else if (spi->dev == NULL) {
PRINTF_INFO("HALSPI", "Attempting to access unsupported SPI%d",
spi->num);
return;
}
SPI_MUTEX_LOCK();
switch (dataMode) {
case SPI_MODE1:
spi->dev->pin.ck_idle_edge = 0;
spi->dev->user.ck_out_edge = 1;
break;
case SPI_MODE2:
spi->dev->pin.ck_idle_edge = 1;
spi->dev->user.ck_out_edge = 1;
break;
case SPI_MODE3:
spi->dev->pin.ck_idle_edge = 1;
spi->dev->user.ck_out_edge = 0;
break;
case SPI_MODE0:
default:
spi->dev->pin.ck_idle_edge = 0;
spi->dev->user.ck_out_edge = 0;
break;
}
_update(spi);
SPI_MUTEX_UNLOCK();
}
uint8_t spiGetBitOrder(spi_t * spi)
{
if(!spi) {
return 0;
}
else if (spi->dev == NULL) {
PRINTF_INFO("HALSPI", "Attempting to access unsupported SPI%d",
spi->num);
return 0;
}
return (spi->dev->ctrl.wr_bit_order | spi->dev->ctrl.rd_bit_order) == 0;
}
void spiSetBitOrder(spi_t * spi, uint8_t bitOrder)
{
if(!spi) {
return;
}
else if (spi->dev == NULL) {
PRINTF_INFO("HALSPI", "Attempting to access unsupported SPI%d",
spi->num);
return;
}
SPI_MUTEX_LOCK();
if (SPI_MSBFIRST == bitOrder) {
spi->dev->ctrl.wr_bit_order = 0;
spi->dev->ctrl.rd_bit_order = 0;
} else if (SPI_LSBFIRST == bitOrder) {
spi->dev->ctrl.wr_bit_order = 1;
spi->dev->ctrl.rd_bit_order = 1;
}
_update(spi);
SPI_MUTEX_UNLOCK();
}
static void _on_apb_change(void * arg, apb_change_ev_t ev_type, uint32_t old_apb, uint32_t new_apb)
{
spi_t * spi = (spi_t *)arg;
if(ev_type == APB_BEFORE_CHANGE){
SPI_MUTEX_LOCK();
_waitdone(spi);
} else {
spi->dev->clock.val = spiFrequencyToClockDiv(old_apb / ((spi->dev->clock.clkdiv_pre + 1) * (spi->dev->clock.clkcnt_n + 1)));
_update(spi);
SPI_MUTEX_UNLOCK();
}
}
void spiStopBus(spi_t * spi)
{
if(!spi) {
return;
}
else if (spi->dev == NULL) {
PRINTF_INFO("HALSPI", "Attempting to access unsupported SPI%d",
spi->num);
return;
}
SPI_MUTEX_LOCK();
spi->dev->slave.trans_done = 0;
spi->dev->slave.slave_mode = 0;
spi->dev->pin.val = 0;
spi->dev->user.val = 0;
spi->dev->user1.val = 0;
spi->dev->ctrl.val = 0;
spi->dev->ctrl1.val = 0;
spi->dev->ctrl2.val = 0;
spi->dev->clock.val = 0;
_update(spi);
SPI_MUTEX_UNLOCK();
//removeApbChangeCallback(spi, _on_apb_change);
}
spi_t * spiStartBus(uint8_t spi_num, uint32_t clockDiv, uint8_t dataMode, uint8_t bitOrder)
{
if(spi_num > 3){
return NULL;
}
spi_t * spi = &_spi_bus_array[spi_num];
#if !CONFIG_DISABLE_HAL_LOCKS
if(spi->lock == NULL){
/* Instead of calling xSemaphoreCreateMutex we need to assign one of the
* local semaphores.
*/
if (spi_num == 2) spi->lock = &i_gn_semaphore_spi2;
else if (spi_num == 3) spi->lock = &i_gn_semaphore_spi3;
else return NULL;
}
#endif
if(spi_num == HSPI) {
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI_CLK_EN);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_RST);
} else if(spi_num == VSPI) {
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI_CLK_EN_2);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_RST_2);
} else {
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI_CLK_EN_1);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_RST_1);
}
spiStopBus(spi);
spiSetDataMode(spi, dataMode);
spiSetBitOrder(spi, bitOrder);
spiSetClockDiv(spi, clockDiv);
SPI_MUTEX_LOCK();
spi->dev->user.usr_mosi = 1;
spi->dev->user.usr_miso = 1;
spi->dev->user.doutdin = 1;
int i;
for(i=0; i<16; i++) {
spi->dev->data_buf[i] = 0x00000000;
}
_update(spi);
SPI_MUTEX_UNLOCK();
//addApbChangeCallback(spi, _on_apb_change);
return spi;
}
void spiWaitReady(spi_t * spi)
{
if(!spi) {
return;
}
else if (spi->dev == NULL) {
PRINTF_INFO("HALSPI", "Attempting to access unsupported SPI%d",
spi->num);
return;
}
_waitdone(spi);
}
void spiWrite(spi_t * spi, const uint32_t *data, uint8_t len)
{
if(!spi) {
return;
}
else if (spi->dev == NULL) {
PRINTF_INFO("HALSPI", "Attempting to access unsupported SPI%d",
spi->num);
return;
}
int i;
if(len > 16) {
len = 16;
}
SPI_MUTEX_LOCK();
spi->dev->mosi_dlen.usr_mosi_dbitlen = (len * 32) - 1;
spi->dev->miso_dlen.usr_miso_dbitlen = 0;
for(i=0; i<len; i++) {
spi->dev->data_buf[i] = data[i];
}
spi->dev->cmd.usr = 1;
_update(spi);
_waitdone(spi);
SPI_MUTEX_UNLOCK();
}
void spiTransfer(spi_t * spi, uint32_t *data, uint8_t len)
{
if(!spi) {
return;
}
else if (spi->dev == NULL) {
PRINTF_INFO("HALSPI", "Attempting to access unsupported SPI%d",
spi->num);
return;
}
int i;
if(len > 16) {
len = 16;
}
SPI_MUTEX_LOCK();
spi->dev->mosi_dlen.usr_mosi_dbitlen = (len * 32) - 1;
spi->dev->miso_dlen.usr_miso_dbitlen = (len * 32) - 1;
for(i=0; i<len; i++) {
spi->dev->data_buf[i] = data[i];
}
spi->dev->cmd.usr = 1;
_update(spi);
_waitdone(spi);
for(i=0; i<len; i++) {
data[i] = spi->dev->data_buf[i];
}
SPI_MUTEX_UNLOCK();
}
void spiWriteByte(spi_t * spi, uint8_t data)
{
if(!spi) {
return;
}
else if (spi->dev == NULL) {
PRINTF_INFO("HALSPI", "Attempting to access unsupported SPI%d",
spi->num);
return;
}
SPI_MUTEX_LOCK();
spi->dev->mosi_dlen.usr_mosi_dbitlen = 7;
spi->dev->miso_dlen.usr_miso_dbitlen = 0;
spi->dev->data_buf[0] = data;
spi->dev->cmd.usr = 1;
_update(spi);
_waitdone(spi);
SPI_MUTEX_UNLOCK();
}
uint8_t spiTransferByte(spi_t * spi, uint8_t data)
{
if(!spi) {
return 0;
}
else if (spi->dev == NULL) {
PRINTF_INFO("HALSPI", "Attempting to access unsupported SPI%d",
spi->num);
return 0;
}
SPI_MUTEX_LOCK();
spi->dev->mosi_dlen.usr_mosi_dbitlen = 7;
spi->dev->miso_dlen.usr_miso_dbitlen = 7;
spi->dev->data_buf[0] = data;
spi->dev->cmd.usr = 1;
_update(spi);
_waitdone(spi);
data = spi->dev->data_buf[0] & 0xFF;
SPI_MUTEX_UNLOCK();
return data;
}
static uint32_t __spiTranslate32(uint32_t data)
{
union {
uint32_t l;
uint8_t b[4];
} out;
out.l = data;
return out.b[3] | (out.b[2] << 8) | (out.b[1] << 16) | (out.b[0] << 24);
}
void spiWriteWord(spi_t * spi, uint16_t data)
{
if(!spi) {
return;
}
else if (spi->dev == NULL) {
PRINTF_INFO("HALSPI", "Attempting to access unsupported SPI%d",
spi->num);
return;
}
if(!spi->dev->ctrl.wr_bit_order){
data = (data >> 8) | (data << 8);
}
SPI_MUTEX_LOCK();
spi->dev->mosi_dlen.usr_mosi_dbitlen = 15;
spi->dev->miso_dlen.usr_miso_dbitlen = 0;
spi->dev->data_buf[0] = data;
spi->dev->cmd.usr = 1;
_update(spi);
_waitdone(spi);
SPI_MUTEX_UNLOCK();
}
uint16_t spiTransferWord(spi_t * spi, uint16_t data)
{
if(!spi) {
return 0;
}
else if (spi->dev == NULL) {
PRINTF_INFO("HALSPI", "Attempting to access unsupported SPI%d",
spi->num);
return 0;
}
if(!spi->dev->ctrl.wr_bit_order){
data = (data >> 8) | (data << 8);
}
SPI_MUTEX_LOCK();
spi->dev->mosi_dlen.usr_mosi_dbitlen = 15;
spi->dev->miso_dlen.usr_miso_dbitlen = 15;
spi->dev->data_buf[0] = data;
spi->dev->cmd.usr = 1;
_update(spi);
_waitdone(spi);
data = spi->dev->data_buf[0];
SPI_MUTEX_UNLOCK();
if(!spi->dev->ctrl.rd_bit_order){
data = (data >> 8) | (data << 8);
}
return data;
}
void spiWriteLong(spi_t * spi, uint32_t data)
{
if(!spi) {
return;
}
else if (spi->dev == NULL) {
PRINTF_INFO("HALSPI", "Attempting to access unsupported SPI%d",
spi->num);
return;
}
if(!spi->dev->ctrl.wr_bit_order){
data = __spiTranslate32(data);
}
SPI_MUTEX_LOCK();
spi->dev->mosi_dlen.usr_mosi_dbitlen = 31;
spi->dev->miso_dlen.usr_miso_dbitlen = 0;
spi->dev->data_buf[0] = data;
spi->dev->cmd.usr = 1;
_update(spi);
_waitdone(spi);
SPI_MUTEX_UNLOCK();
}
uint32_t spiTransferLong(spi_t * spi, uint32_t data)
{
if(!spi) {
|
return 0;
}
else if (spi->dev == NULL) {
PRINTF_INFO("HALSPI", "Attempting to access unsupported SPI%d",
spi->num);
return 0;
}
if(!spi->dev->ctrl.wr_bit_order){
data = __spiTranslate32(data);
}
SPI_MUTEX_LOCK();
spi->dev->mosi_dlen.usr_mosi_dbitlen = 31;
spi->dev->miso_dlen.usr_miso_dbitlen = 31;
spi->dev->data_buf[0] = data;
spi->dev->cmd.usr = 1;
_update(spi);
_waitdone(spi);
data = spi->dev->data_buf[0];
SPI_MUTEX_UNLOCK();
if(!spi->dev->ctrl.rd_bit_order){
data = __spiTranslate32(data);
}
return data;
}
static void __spiTransferBytes(spi_t * spi, const uint8_t * data, uint8_t * out, uint32_t bytes)
{
if(!spi) {
return;
}
else if (spi->dev == NULL) {
PRINTF_INFO("HALSPI", "Attempting to access unsupported SPI%d",
spi->num);
return;
}
unsigned int i;
if(bytes > 64) {
bytes = 64;
}
uint32_t words = (bytes + 3) / 4;//16 max
uint32_t wordsBuf[16] = {0,};
uint8_t * bytesBuf = (uint8_t *) wordsBuf;
if(data) {
memcpy(bytesBuf, data, bytes);//copy data to buffer
} else {
memset(bytesBuf, 0xFF, bytes);
}
spi->dev->mosi_dlen.usr_mosi_dbitlen = ((bytes * 8) - 1);
spi->dev->miso_dlen.usr_miso_dbitlen = ((bytes * 8) - 1);
for(i=0; i<words; i++) {
spi->dev->data_buf[i] = wordsBuf[i]; //copy buffer to spi fifo
}
spi->dev->cmd.usr = 1;
_update(spi);
_waitdone(spi);
if(out) {
for(i=0; i<words; i++) {
wordsBuf[i] = spi->dev->data_buf[i];//copy spi fifo to buffer
}
memcpy(out, bytesBuf, bytes);//copy buffer to output
}
}
void spiTransferBytes(spi_t * spi, const uint8_t * data, uint8_t * out, uint32_t size)
{
if(!spi) {
return;
}
else if (spi->dev == NULL) {
PRINTF_INFO("HALSPI", "Attempting to access unsupported SPI%d",
spi->num);
return;
}
SPI_MUTEX_LOCK();
while(size) {
if(size > 64) {
__spiTransferBytes(spi, data, out, 64);
size -= 64;
if(data) {
data += 64;
}
if(out) {
out += 64;
}
} else {
__spiTransferBytes(spi, data, out, size);
size = 0;
}
}
SPI_MUTEX_UNLOCK();
}
void spiTransferBits(spi_t * spi, uint32_t data, uint32_t * out, uint8_t bits)
{
if(!spi) {
return;
}
else if (spi->dev == NULL) {
PRINTF_INFO("HALSPI", "Attempting to access unsupported SPI%d",
spi->num);
return;
}
SPI_MUTEX_LOCK();
spiTransferBitsNL(spi, data, out, bits);
SPI_MUTEX_UNLOCK();
}
/*
* Manual Lock Management
* */
#define MSB_32_SET(var, val) { uint8_t * d = (uint8_t *)&(val); (var) = d[3] | (d[2] << 8) | (d[1] << 16) | (d[0] << 24); }
#define MSB_24_SET(var, val) { uint8_t * d = (uint8_t *)&(val); (var) = d[2] | (d[1] << 8) | (d[0] << 16); }
#define MSB_16_SET(var, val) { (var) = (((val) & 0xFF00) >> 8) | (((val) & 0xFF) << 8); }
#define MSB_PIX_SET(var, val) { uint8_t * d = (uint8_t *)&(val); (var) = d[1] | (d[0] << 8) | (d[3] << 16) | (d[2] << 24); }
void spiTransaction(spi_t * spi, uint32_t clockDiv, uint8_t dataMode, uint8_t bitOrder)
{
if(!spi) {
return;
}
else if (spi->dev == NULL) {
PRINTF_INFO("HALSPI", "Attempting to access unsupported SPI%d",
spi->num);
return;
}
SPI_MUTEX_LOCK();
spi->dev->clock.val = clockDiv;
switch (dataMode) {
case SPI_MODE1:
spi->dev->pin.ck_idle_edge = 0;
spi->dev->user.ck_out_edge = 1;
break;
case SPI_MODE2:
spi->dev->pin.ck_idle_edge = 1;
spi->dev->user.ck_out_edge = 1;
break;
case SPI_MODE3:
spi->dev->pin.ck_idle_edge = 1;
spi->dev->user.ck_out_edge = 0;
break;
case SPI_MODE0:
default:
spi->dev->pin.ck_idle_edge = 0;
spi->dev->user.ck_out_edge = 0;
break;
}
if (SPI_MSBFIRST == bitOrder) {
spi->dev->ctrl.wr_bit_order = 0;
spi->dev->ctrl.rd_bit_order = 0;
} else if (SPI_LSBFIRST == bitOrder) {
spi->dev->ctrl.wr_bit_order = 1;
spi->dev->ctrl.rd_bit_order = 1;
}
_update(spi);
}
void spiSimpleTransaction(spi_t * spi)
{
if(!spi) {
return;
}
else if (spi->dev == NULL) {
PRINTF_INFO("HALSPI", "Attempting to access unsupported SPI%d",
spi->num);
return;
}
SPI_MUTEX_LOCK();
}
void spiEndTransaction(spi_t * spi)
{
if(!spi) {
return;
}
else if (spi->dev == NULL) {
PRINTF_INFO("HALSPI", "Attempting to access unsupported SPI%d",
spi->num);
return;
}
SPI_MUTEX_UNLOCK();
}
void IRAM_ATTR spiWriteByteNL(spi_t * spi, uint8_t data)
{
if(!spi) {
return;
}
else if (spi->dev == NULL) {
PRINTF_INFO("HALSPI", "Attempting to access unsupported SPI%d",
spi->num);
return;
}
spi->dev->mosi_dlen.usr_mosi_dbitlen = 7;
spi->dev->miso_dlen.usr_miso_dbitlen = 0;
spi->dev->data_buf[0] = data;
spi->dev->cmd.usr = 1;
_update(spi);
_waitdone(spi);
}
uint8_t spiTransferByteNL(spi_t * spi, uint8_t data)
{
if(!spi) {
return 0;
}
else if (spi->dev == NULL) {
PRINTF_INFO("HALSPI", "Attempting to access unsupported SPI%d",
spi->num);
return 0;
}
spi->dev->mosi_dlen.usr_mosi_dbitlen = 7;
spi->dev->miso_dlen.usr_miso_dbitlen = 7;
spi->dev->data_buf[0] = data;
spi->dev->cmd.usr = 1;
_update(spi);
_waitdone(spi);
data = spi->dev->data_buf[0] & 0xFF;
return data;
}
void IRAM_ATTR spiWriteShortNL(spi_t * spi, uint16_t data)
{
if(!spi) {
return;
}
else if (spi->dev == NULL) {
PRINTF_INFO("HALSPI", "Attempting to access unsupported SPI%d",
spi->num);
return;
}
if(!spi->dev->ctrl.wr_bit_order){
MSB_16_SET(data, data);
}
spi->dev->mosi_dlen.usr_mosi_dbitlen = 15;
spi->dev->miso_dlen.usr_miso_dbitlen = 0;
spi->dev->data_buf[0] = data;
spi->dev->cmd.usr = 1;
_update(spi);
_waitdone(spi);
}
uint16_t spiTransferShortNL(spi_t * spi, uint16_t data)
{
if(!spi) {
return 0;
}
else if (spi->dev == NULL) {
PRINTF_INFO("HALSPI", "Attempting to access unsupported SPI%d",
spi->num);
return 0;
}
if(!spi->dev->ctrl.wr_bit_order){
MSB_16_SET(data, data);
}
spi->dev->mosi_dlen.usr_mosi_dbitlen = 15;
spi->dev->miso_dlen.usr_miso_dbitlen = 15;
spi->dev->data_buf[0] = data;
spi->dev->cmd.usr = 1;
_update(spi);
_waitdone(spi);
data = spi->dev->data_buf[0] & 0xFFFF;
if(!spi->dev->ctrl.rd_bit_order){
MSB_16_SET(data, data);
}
return data;
}
void IRAM_ATTR spiWriteLongNL(spi_t * spi, uint32_t data)
{
if(!spi) {
return;
}
else if (spi->dev == NULL) {
PRINTF_INFO("HALSPI", "Attempting to access unsupported SPI%d",
spi->num);
return;
}
if(!spi->dev->ctrl.wr_bit_order){
MSB_32_SET(data, data);
}
spi->dev->mosi_dlen.usr_mosi_dbitlen = 31;
spi->dev->miso_dlen.usr_miso_dbitlen = 0;
spi->dev->data_buf[0] = data;
spi->dev->cmd.usr = 1;
_update(spi);
_waitdone(spi);
}
uint32_t spiTransferLongNL(spi_t * spi, uint32_t data)
{
if(!spi) {
return 0;
}
else if (spi->dev == NULL) {
PRINTF_INFO("HALSPI", "Attempting to access unsupported SPI%d",
spi->num);
return 0;
}
if(!spi->dev->ctrl.wr_bit_order){
MSB_32_SET(data, data);
}
spi->dev->mosi_dlen.usr_mosi_dbitlen = 31;
spi->dev->miso_dlen.usr_miso_dbitlen = 31;
spi->dev->data_buf[0] = data;
spi->dev->cmd.usr = 1;
_update(spi);
_waitdone(spi);
data = spi->dev->data_buf[0];
if(!spi->dev->ctrl.rd_bit_order){
MSB_32_SET(data, data);
}
return data;
}
void spiWriteNL(spi_t * spi, const void * data_in, uint32_t len){
size_t longs = len >> 2;
if(len & 3){
longs++;
}
uint32_t * data = (uint32_t*)data_in;
size_t c_len = 0, c_longs = 0;
while(len){
c_len = (len>64)?64:len;
c_longs = (longs > 16)?16:longs;
spi->dev->mosi_dlen.usr_mosi_dbitlen = (c_len*8)-1;
spi->dev->miso_dlen.usr_miso_dbitlen = 0;
for (size_t i=0; i<c_longs; i++) {
spi->dev->data_buf[i] = data[i];
}
spi->dev->cmd.usr = 1;
_update(spi);
_waitdone(spi);
data += c_longs;
longs -= c_longs;
len -= c_len;
}
}
void spiTransferBytesNL(spi_t * spi, const void * data_in, uint8_t * data_out, uint32_t len){
if(!spi) {
return;
}
else if (spi->dev == NULL) {
PRINTF_INFO("HALSPI", "Attempting to access unsupported SPI%d",
spi->num);
return;
}
size_t longs = len >> 2;
if(len & 3){
longs++;
}
uint32_t * data = (uint32_t*)data_in;
uint32_t * result = (uint32_t*)data_out;
size_t c_len = 0, c_longs = 0;
while(len){
c_len = (len>64)?64:len;
c_longs = (longs > 16)?16:longs;
spi->dev->mosi_dlen.usr_mosi_dbitlen = (c_len*8)-1;
spi->dev->miso_dlen.usr_miso_dbitlen = (c_len*8)-1;
if(data){
for (size_t i=0; i<c_longs; i++) {
spi->dev->data_buf[i] = data[i];
}
} else {
for (size_t i=0; i<c_longs; i++) {
spi->dev->data_buf[i] = 0xFFFFFFFF;
}
}
spi->dev->cmd.usr = 1;
_update(spi);
_waitdone(spi);
if(result){
for (size_t i=0; i<c_longs; i++) {
result[i] = spi->dev->data_buf[i];
}
}
if(data){
data += c_longs;
}
if(result){
result += c_longs;
}
longs -= c_longs;
len -= c_len;
}
}
void spiTransferBitsNL(spi_t * spi, uint32_t data, uint32_t * out, uint8_t bits)
{
if(!spi) {
return;
}
else if (spi->dev == NULL) {
PRINTF_INFO("HALSPI", "Attempting to access unsupported SPI%d",
spi->num);
return;
}
if(bits > 32) {
bits = 32;
}
uint32_t bytes = (bits + 7) / 8;//64 max
uint32_t mask = (((uint64_t)1 << bits) - 1) & 0xFFFFFFFF;
data = data & mask;
if(!spi->dev->ctrl.wr_bit_order){
if(bytes == 2) {
MSB_16_SET(data, data);
} else if(bytes == 3) {
MSB_24_SET(data, data);
} else {
MSB_32_SET(data, data);
}
}
spi->dev->mosi_dlen.usr_mosi_dbitlen = (bits - 1);
spi->dev->miso_dlen.usr_miso_dbitlen = (bits - 1);
spi->dev->data_buf[0] = data;
spi->dev->cmd.usr = 1;
_update(spi);
_waitdone(spi);
data = spi->dev->data_buf[0];
if(out) {
*out = data;
if(!spi->dev->ctrl.rd_bit_order){
if(bytes == 2) {
MSB_16_SET(*out, data);
} else if(bytes == 3) {
MSB_24_SET(*out, data);
} else {
MSB_32_SET(*out, data);
}
}
}
}
void IRAM_ATTR spiWritePixelsNL(spi_t * spi, const void * data_in, uint32_t len){
size_t longs = len >> 2;
if(len & 3){
longs++;
}
bool msb = !spi->dev->ctrl.wr_bit_order;
uint32_t * data = (uint32_t*)data_in;
size_t c_len = 0, c_longs = 0, l_bytes = 0;
while(len){
c_len = (len>64)?64:len;
c_longs = (longs > 16)?16:longs;
l_bytes = (c_len & 3);
spi->dev->mosi_dlen.usr_mosi_dbitlen = (c_len*8)-1;
spi->dev->miso_dlen.usr_miso_dbitlen = 0;
for (size_t i=0; i<c_longs; i++) {
if(msb){
if(l_bytes && i == (c_longs - 1)){
if(l_bytes == 2){
MSB_16_SET(spi->dev->data_buf[i], data[i]);
} else {
spi->dev->data_buf[i] = data[i] & 0xFF;
}
} else {
MSB_PIX_SET(spi->dev->data_buf[i], data[i]);
}
} else {
spi->dev->data_buf[i] = data[i];
}
}
spi->dev->cmd.usr = 1;
_update(spi);
_waitdone(spi);
data += c_longs;
longs -= c_longs;
len -= c_len;
}
}
/*
* Clock Calculators
*
* */
typedef union {
uint32_t value;
struct {
uint32_t clkcnt_l: 6; /*it must be equal to spi_clkcnt_N.*/
uint32_t clkcnt_h: 6; /*it must be floor((spi_clkcnt_N+1)/2-1).*/
uint32_t clkcnt_n: 6; /*it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)*/
uint32_t clkdiv_pre: 13; /*it is pre-divider of spi_clk.*/
uint32_t clk_equ_sysclk: 1; /*1: spi_clk is eqaul to system 0: spi_clk is divided from system clock.*/
};
} spiClk_t;
#define ClkRegToFreq(reg) (apb_freq / (((reg)->clkdiv_pre + 1) * ((reg)->clkcnt_n + 1)))
uint32_t spiClockDivToFrequency(uint32_t clockDiv)
{
uint32_t apb_freq = getApbFrequency();
spiClk_t reg = { clockDiv };
return ClkRegToFreq(®);
}
uint32_t abs(uint32_t a) {
long r = abs((long) a);
if (r > UINT32_MAX) return UINT32_MAX;
else return (uint32_t)r;
}
uint32_t spiFrequencyToClockDiv(uint32_t freq)
{
uint32_t apb_freq = getApbFrequency();
if(freq >= apb_freq) {
return SPI_CLK_EQU_SYSCLK;
}
const spiClk_t minFreqReg = { 0x7FFFF000 };
uint32_t minFreq = ClkRegToFreq((spiClk_t*) &minFreqReg);
if(freq < minFreq) {
return minFreqReg.value;
}
uint8_t calN = 1;
spiClk_t bestReg = { 0 };
int32_t bestFreq = 0;
while(calN <= 0x3F) {
spiClk_t reg = { 0 };
int32_t calFreq;
int32_t calPre;
int8_t calPreVari = -2;
reg.clkcnt_n = calN;
while(calPreVari++ <= 1) {
calPre = (((apb_freq / (reg.clkcnt_n + 1)) / freq) - 1) + calPreVari;
if(calPre > 0x1FFF) {
reg.clkdiv_pre = 0x1FFF;
} else if(calPre <= 0) {
reg.clkdiv_pre = 0;
} else {
reg.clkdiv_pre = calPre;
}
reg.clkcnt_l = ((reg.clkcnt_n + 1) / 2);
calFreq = ClkRegToFreq(®);
if(calFreq == (int32_t) freq) {
memcpy(&bestReg, ®, sizeof(bestReg));
break;
} else if(calFreq < (int32_t) freq) {
if(abs(freq - calFreq) < abs(freq - bestFreq)) {
bestFreq = calFreq;
memcpy(&bestReg, ®, sizeof(bestReg));
}
}
}
if(calFreq == (int32_t) freq) {
break;
}
calN++;
}
return bestReg.value;
}
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
// Version: 2019.2.1
// Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _karastuba_mul_templa_HH_
#define _karastuba_mul_templa_HH_
#include "systemc.h"
#include "AESL_pkg.h"
#include "karastuba_mul_templa_4.h"
#include "karastuba_mul_temEe0.h"
namespace ap_rtl {
struct karastuba_mul_templa : public sc_module {
// Port declarations 29
sc_in_clk ap_clk;
sc_in< sc_logic > ap_rst;
sc_in< sc_logic > ap_start;
sc_out< sc_logic > ap_done;
sc_out< sc_logic > ap_idle;
sc_out< sc_logic > ap_ready;
sc_out< sc_lv<5> > lhs0_tmp_digits_data_V_address0;
sc_out< sc_logic > lhs0_tmp_digits_data_V_ce0;
sc_in< sc_lv<64> > lhs0_tmp_digits_data_V_q0;
sc_out< sc_lv<5> > lhs1_tmp_digits_data_V_address0;
sc_out< sc_logic > lhs1_tmp_digits_data_V_ce0;
sc_in< sc_lv<64> > lhs1_tmp_digits_data_V_q0;
sc_out< sc_lv<5> > rhs0_tmp_digits_data_V_address0;
sc_out< sc_logic > rhs0_tmp_digits_data_V_ce0;
sc_in< sc_lv<64> > rhs0_tmp_digits_data_V_q0;
sc_out< sc_lv<5> > rhs1_tmp_digits_data_V_address0;
sc_out< sc_logic > rhs1_tmp_digits_data_V_ce0;
sc_in< sc_lv<64> > rhs1_tmp_digits_data_V_q0;
sc_out< sc_lv<6> > cross_mul_digits_data_V_address0;
sc_out< sc_logic > cross_mul_digits_data_V_ce0;
sc_out< sc_logic > cross_mul_digits_data_V_we0;
sc_out< sc_lv<64> > cross_mul_digits_data_V_d0;
sc_in< sc_lv<64> > cross_mul_digits_data_V_q0;
sc_out< sc_lv<6> > cross_mul_digits_data_V_address1;
sc_out< sc_logic > cross_mul_digits_data_V_ce1;
sc_out< sc_logic > cross_mul_digits_data_V_we1;
sc_out< sc_lv<64> > cross_mul_digits_data_V_d1;
sc_in< sc_lv<64> > cross_mul_digits_data_V_q1;
sc_out< sc_lv<4> > ap_return;
// Module declarations
karastuba_mul_templa(sc_module_name name);
SC_HAS_PROCESS(karastuba_mul_templa);
~karastuba_mul_templa();
sc_trace_file* mVcdFile;
karastuba_mul_temEe0* add0_digits_data_V_U;
karastuba_mul_temEe0* add1_digits_data_V_U;
karastuba_mul_templa_4* grp_karastuba_mul_templa_4_fu_180;
sc_signal< sc_lv<6> > ap_CS_fsm;
sc_signal< sc_logic > ap_CS_fsm_state1;
sc_signal< sc_lv<2> > p_088_0_i_reg_134;
sc_signal< sc_lv<6> > i_0_i_reg_146;
sc_signal< sc_lv<2> > p_088_0_i1_reg_157;
sc_signal< sc_lv<6> > i_0_i2_reg_169;
sc_signal< sc_lv<1> > icmp_ln53_fu_192_p2;
sc_signal< sc_lv<1> > icmp_ln53_reg_326;
sc_signal< sc_logic > ap_CS_fsm_pp0_stage0;
sc_signal< bool > ap_block_state2_pp0_stage0_iter0;
sc_signal< bool > ap_block_state3_pp0_stage0_iter1;
sc_signal< bool > ap_block_state4_pp0_stage0_iter2;
sc_signal< bool > ap_block_state5_pp0_stage0_iter3;
sc_signal< bool > ap_block_state6_pp0_stage0_iter4;
sc_signal< bool > ap_block_pp0_stage0_11001;
sc_signal< sc_lv<1> > icmp_ln53_reg_326_pp0_iter1_reg;
sc_signal< sc_lv<1> > icmp_ln53_reg_326_pp0_iter2_reg;
sc_signal< sc_lv<1> > icmp_ln53_reg_326_pp0_iter3_reg;
sc_signal< sc_lv<6> > i_fu_198_p2;
sc_signal< sc_logic > ap_enable_reg_pp0_iter0;
sc_signal< sc_lv<64> > zext_ln58_fu_204_p1;
sc_signal< sc_lv<64> > zext_ln58_reg_335;
sc_signal< sc_lv<64> > zext_ln58_reg_335_pp0_iter1_reg;
sc_signal< sc_lv<64> > zext_ln58_reg_335_pp0_iter2_reg;
sc_signal< sc_lv<64> > zext_ln58_reg_335_pp0_iter3_reg;
sc_signal< sc_lv<64> > lhs0_tmp_digits_data_6_reg_350;
sc_signal< sc_lv<64> > lhs0_tmp_digits_data_6_reg_350_pp0_iter2_reg;
sc_signal< sc_lv<64> > lhs1_tmp_digits_data_6_reg_356;
sc_signal< sc_lv<64> > lhs1_tmp_digits_data_6_reg_356_pp0_iter2_reg;
sc_signal< sc_lv<65> > add_ln700_fu_216_p2;
sc_signal< sc_lv<65> > add_ln700_reg_362;
sc_signal< sc_lv<64> > add_ln209_6_fu_244_p2;
sc_signal< sc_lv<64> > add_ln209_6_reg_367;
sc_signal< sc_lv<2> > trunc_ln_reg_372;
sc_signal< sc_logic > ap_enable_reg_pp0_iter3;
sc_signal< sc_lv<1> > icmp_ln53_1_fu_259_p2;
sc_signal< sc_lv<1> > icmp_ln53_1_reg_377;
sc_signal< sc_logic > ap_CS_fsm_pp1_stage0;
sc_signal< bool > ap_block_state8_pp1_stage0_iter0;
sc_signal< bool > ap_block_state9_pp1_stage0_iter1;
sc_signal< bool > ap_block_state10_pp1_stage0_iter2;
sc_signal< bool > ap_block_state11_pp1_stage0_iter3;
sc_signal< bool > ap_block_state12_pp1_stage0_iter4;
sc_signal< bool > ap_block_pp1_stage0_11001;
sc_signal< sc_lv<1> > icmp_ln53_1_reg_377_pp1_iter1_reg;
sc_signal< sc_lv<1> > icmp_ln53_1_reg_377_pp1_iter2_reg;
sc_signal< sc_lv<1> > icmp_ln53_1_reg_377_pp1_iter3_reg;
sc_signal< sc_lv<6> > i_23_fu_265_p2;
sc_signal< sc_logic > ap_enable_reg_pp1_iter0;
sc_signal< sc_lv<64> > zext_ln58_1_fu_271_p1;
sc_signal< sc_lv<64> > zext_ln58_1_reg_386;
sc_signal< sc_lv<64> > zext_ln58_1_reg_386_pp1_iter1_reg;
sc_signal< sc_lv<64> > zext_ln58_1_reg_386_pp1_iter2_reg;
sc_signal< sc_lv<64> > zext_ln58_1_reg_386_pp1_iter3_reg;
sc_signal< sc_lv<64> > rhs0_tmp_digits_data_6_reg_401;
sc_signal< sc_lv<64> > rhs0_tmp_digits_data_6_reg_401_pp1_iter2_reg;
sc_signal< sc_lv<64> > rhs1_tmp_digits_data_6_reg_407;
sc_signal< sc_lv<64> > rhs1_tmp_digits_data_6_reg_407_pp1_iter2_reg;
sc_signal< sc_lv<65> > add_ln700_7_fu_283_p2;
sc_signal< sc_lv<65> > add_ln700_7_reg_413;
sc_signal< sc_lv<64> > add_ln209_8_fu_311_p2;
sc_signal< sc_lv<64> > add_ln209_8_reg_418;
sc_signal< sc_lv<2> > trunc_ln858_3_reg_423;
sc_signal< sc_logic > ap_enable_reg_pp1_iter3;
sc_signal< bool > ap_block_pp0_stage0_subdone;
sc_signal< sc_logic > ap_condition_pp0_exit_iter0_state2;
sc_signal< sc_logic > ap_enable_reg_pp0_iter1;
sc_signal< sc_logic > ap_enable_reg_pp0_iter2;
sc_signal< sc_logic > ap_enable_reg_pp0_iter4;
sc_signal< sc_logic > ap_CS_fsm_state7;
sc_signal< bool > ap_block_pp1_stage0_subdone;
sc_signal< sc_logic > ap_condition_pp1_exit_iter0_state8;
sc_signal< sc_logic > ap_enable_reg_pp1_iter1;
sc_signal< sc_logic > ap_enable_reg_pp1_iter2;
sc_signal< sc_logic > ap_enable_reg_pp1_iter4;
sc_signal< sc_lv<5> > add0_digits_data_V_address0;
sc_signal< sc_logic > add0_digits_data_V_ce0;
sc_signal< sc_logic > add0_digits_data_V_we0;
sc_signal< sc_lv<64> > add0_digits_data_V_q0;
sc_signal< sc_lv<5> > add1_digits_data_V_address0;
sc_signal< sc_logic > add1_digits_data_V_ce0;
sc_signal< sc_logic > add1_digits_data_V_we0;
sc_signal< sc_lv<64> > add1_digits_data_V_q0;
sc_signal< sc_logic > grp_karastuba_mul_templa_4_fu_180_ap_start;
sc_signal< sc_logic > grp_karastuba_mul_templa_4_fu_180_ap_done;
sc_signal< sc_logic > grp_karastuba_mul_templa_4_fu_180_ap_idle;
sc_signal< sc_logic > grp_karastuba_mul_templa_4_fu_180_ap_ready;
sc_signal< sc_lv<5> > grp_karastuba_mul_templa_4_fu_180_lhs_digits_data_V_address0;
sc_signal< sc_logic > grp_karastuba_mul_templa_4_fu_180_lhs_digits_data_V_ce0;
sc_signal< sc_lv<5> > grp_karastuba_mul_templa_4_fu_180_rhs_digits_data_V_address0;
sc_signal< sc_logic > grp_karastuba_mul_templa_4_fu_180_rhs_digits_data_V_ce0;
sc_signal< sc_lv<6> > grp_karastuba_mul_templa_4_fu_180_res_digits_data_V_address0;
sc_signal< sc_logic > grp_karastuba_mul_templa_4_fu_180_res_digits_data_V_ce0;
sc_signal< sc_logic > grp_karastuba_mul_templa_4_fu_180_res_digits_data_V_we0;
sc_signal< sc_lv<64> > grp_karastuba_mul_templa_4_fu_180_res_digits_data_V_d0;
sc_signal< sc_lv<6> > grp_karastuba_mul_templa_4_fu_180_res_digits_data_V_address1;
sc_signal< sc_logic > grp_karastuba_mul_templa_4_fu_180_res_digits_data_V_ce1;
sc_signal< sc_logic > grp_karastuba_mul_templa_4_fu_180_res_digits_data_V_we1;
sc_signal< sc_lv<64> > grp_karastuba_mul_templa_4_fu_180_res_digits_data_V_d1;
sc_signal< sc_lv<4> > grp_karastuba_mul_templa_4_fu_180_ap_return;
sc_signal< sc_lv<2> > ap_phi_mux_p_088_0_i_phi_fu_138_p4;
sc_signal< bool > ap_block_pp0_stage0;
sc_signal< sc_lv<2> > ap_phi_mux_p_088_0_i1_phi_fu_161_p4;
sc_signal< bool > ap_block_pp1_stage0;
sc_signal< sc_logic > grp_karastuba_mul_templa_4_fu_180_ap_start_reg;
sc_signal< sc_logic > ap_CS_fsm_state13;
sc_signal< sc_logic > ap_CS_fsm_state14;
sc_signal< sc_lv<65> > zext_ln209_fu_210_p1;
sc_signal< sc_lv<65> > zext_ln700_fu_213_p1;
sc_signal< sc_lv<66> > zext_ln700_10_fu_230_p1;
sc_signal< sc_lv<66> > zext_ln53_fu_222_p1;
sc_signal< sc_lv<64> > zext_ln700_9_fu_226_p1;
sc_signal< sc_lv<64> > add_ln209_fu_239_p2;
sc_signal< sc_lv<66> > tmp_V_fu_233_p2;
sc_signal< sc_lv<65> > zext_ln209_1_fu_277_p1;
sc_signal< sc_lv<65> > zext_ln700_11_fu_280_p1;
sc_signal< sc_lv<66> > zext_ln700_13_fu_297_p1;
sc_signal< sc_lv<66> > zext_ln53_1_fu_289_p1;
sc_signal< sc_lv<64> > zext_ln700_12_fu_293_p1;
sc_signal< sc_lv<64> > add_ln209_7_fu_306_p2;
sc_signal< sc_lv<66> > tmp_V_14_fu_300_p2;
sc_signal< sc_lv<4> > ap_return_preg;
sc_signal< sc_lv<6> > ap_NS_fsm;
sc_signal< sc_logic > ap_idle_pp0;
sc_signal< sc_logic > ap_enable_pp0;
sc_signal< sc_logic > ap_idle_pp1;
sc_signal< sc_logic > ap_enable_pp1;
static const sc_logic ap_const_logic_1;
static const sc_logic ap_const_logic_0;
static const sc_lv<6> ap_ST_fsm_state1;
static const sc_lv<6> ap_ST_fsm_pp0_stage0;
static const sc_lv<6> ap_ST_fsm_state7;
static const sc_lv<6> ap_ST_fsm_pp1_stage0;
static const sc_lv<6> ap_ST_fsm_state13;
static const sc_lv<6> ap_ST_fsm_state14;
static const bool ap_const_boolean_1;
static const sc_lv<32> ap_const_lv32_0;
static const sc_lv<32> ap_const_lv32_1;
static const bool ap_const_boolean_0;
static const sc_lv<1> ap_const_lv1_0;
static const sc_lv<32> ap_const_lv32_3;
static const sc_lv<1> ap_const_lv1_1;
static const sc_lv<32> ap_const_lv32_2;
static const sc_lv<2> ap_const_lv2_0;
static const sc_lv<6> ap_const_lv6_0;
static const sc_lv<32> ap_const_lv32_4;
static const sc_lv<32> ap_const_lv32_5;
static const sc_lv<6> ap_const_lv6_20;
static const sc_lv<6> ap_const_lv6_1;
static const sc_lv<32> ap_const_lv32_40;
static const sc_lv<32> ap_const_lv32_41;
static const sc_lv<4> ap_const_lv4_0;
// Thread declarations
void thread_ap_clk_no_reset_();
void thread_add0_digits_data_V_address0();
void thread_add0_digits_data_V_ce0();
void thread_add0_digits_data_V_we0();
void thread_add1_digits_data_V_address0();
void thread_add1_digits_data_V_ce0();
void thread_add1_digits_data_V_we0();
void thread_add_ln209_6_fu_244_p2();
void thread_add_ln209_7_fu_306_p2();
void thread_add_ln209_8_fu_311_p2();
void thread_add_ln209_fu_239_p2();
void thread_add_ln700_7_fu_283_p2();
void thread_add_ln700_fu_216_p2();
void thread_ap_CS_fsm_pp0_stage0();
void thread_ap_CS_fsm_pp1_stage0();
void thread_ap_CS_fsm_state1();
void thread_ap_CS_fsm_state13();
void thread_ap_CS_fsm_state14();
void thread_ap_CS_fsm_state7();
void thread_ap_block_pp0_stage0();
void thread_ap_block_pp0_stage0_11001();
void thread_ap_block_pp0_stage0_subdone();
void thread_ap_block_pp1_stage0();
void thread_ap_block_pp1_stage0_11001();
void thread_ap_block_pp1_stage0_subdone();
void thread_ap_block_state10_pp1_stage0_iter2();
void thread_ap_block_state11_pp1_stage0_iter3();
void thread_ap_block_state12_pp1_stage0_iter4();
void thread_ap_block_state2_pp0_stage0_iter0();
void thread_ap_block_state3_pp0_stage0_iter1();
void thread_ap_block_state4_pp0_stage0_iter2();
void thread_ap_block_state5_pp0_stage0_iter3();
void thread_ap_block_state6_pp0_stage0_iter4();
void thread_ap_block_state8_pp1_stage0_iter0();
void thread_ap_block_state9_pp1_stage0_iter1();
void thread_ap_condition_pp0_exit_iter0_state2();
void thread_ap_condition_pp1_exit_iter0_state8();
void thread_ap_done();
void thread_ap_enable_pp0();
void thread_ap_enable_pp1();
void thread_ap_idle();
void thread_ap_idle_pp0();
void thread_ap_idle_pp1();
void thread_ap_phi_mux_p_088_0_i1_phi_fu_161_p4();
void thread_ap_phi_mux_p_088_0_i_phi_fu_138_p4();
void thread_ap_ready();
void thread_ap_return();
void thread_cross_mul_digits_data_V_address0();
void thread_cross_mul_digits_data_V_address1();
void thread_cross_mul_digits_data_V_ce0();
void thread_cross_mul_digits_data_V_ce1();
void thread_cross_mul_digits_data_V_d0();
void thread_cross_mul_digits_data_V_d1();
void thread_cross_mul_digits_data_V_we0();
void thread_cross_mul_digits_data_V_we1();
void thread_grp_karastuba_mul_templa_4_fu_180_ap_start();
void thread_i_23_fu_265_p2();
void thread_i_fu_198_p2();
void thread_icmp_ln53_1_fu_259_p2();
void thread_icmp_ln53_fu_192_p2();
void thread_lhs0_tmp_digits_data_V_address0();
void thread_lhs0_tmp_digits_data_V_ce0();
void thread_lhs1_tmp_digits_data_V_address0();
void thread_lhs1_tmp_digits_data_V_ce0();
void thread_rhs0_tmp_digits_data_V_address0();
void thread_rhs0_tmp_digits_data_V_ce0();
void thread_rhs1_tmp_digits_data_V_address0();
void thread_rhs1_tmp_digits_data_V_ce0();
void thread_tmp_V_14_fu_300_p2();
void thread_tmp_V_fu_233_p2();
void thread_zext_ln209_1_fu_277_p1();
void thread_zext_ln209_fu_210_p1();
void thread_zext_ln53_1_fu_289_p1();
void thread_zext_ln53_fu_222_p1();
void thread_zext_ln58_1_fu_271_p1();
void thread_zext_ln58_fu_204_p1();
void thread_zext_ln700_10_fu_230_p1();
void thread_zext_ln700_11_fu_280_p1();
void thread_zext_ln700_12_fu_293_p1();
void thread_zext_ln700_13_fu_297_p1();
void thread_zext_ln700_9_fu_226_p1();
void thread_zext_ln700_fu_213_p1();
void thread_ap_NS_fsm();
};
}
using namespace ap_rtl;
#endif
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
// Version: 2020.1
// Copyright (C) 1986-2020 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _Seuil_calc2_do_gen_HH_
#define _Seuil_calc2_do_gen_HH_
#include "systemc.h"
#include "AESL_pkg.h"
#include "Seuil_calc2_mac_mdEe.h"
#include "Seuil_calc2_mul_meOg.h"
#include "Seuil_calc2_mul_mfYi.h"
namespace ap_rtl {
struct Seuil_calc2_do_gen : public sc_module {
// Port declarations 8
sc_in_clk ap_clk;
sc_in< sc_logic > ap_rst;
sc_in< sc_lv<8> > e_dout;
sc_in< sc_logic > e_empty_n;
sc_out< sc_logic > e_read;
sc_out< sc_logic > detect_din;
sc_in< sc_logic > detect_full_n;
sc_out< sc_logic > detect_write;
// Module declarations
Seuil_calc2_do_gen(sc_module_name name);
SC_HAS_PROCESS(Seuil_calc2_do_gen);
~Seuil_calc2_do_gen();
sc_trace_file* mVcdFile;
Seuil_calc2_mac_mdEe<1,1,8,8,16,17>* Seuil_calc2_mac_mdEe_U22;
Seuil_calc2_mul_meOg<1,1,11,11,22>* Seuil_calc2_mul_meOg_U23;
Seuil_calc2_mul_mfYi<1,1,17,6,27>* Seuil_calc2_mul_mfYi_U24;
sc_signal< sc_logic > e_blk_n;
sc_signal< sc_lv<2> > ap_CS_fsm;
sc_signal< sc_logic > ap_CS_fsm_pp0_stage0;
sc_signal< sc_logic > ap_enable_reg_pp0_iter0;
sc_signal< bool > ap_block_pp0_stage0;
sc_signal< sc_logic > detect_blk_n;
sc_signal< sc_logic > ap_enable_reg_pp0_iter4;
sc_signal< sc_lv<22> > p_0108_0_reg_221;
sc_signal< sc_lv<8> > val_V_reg_876;
sc_signal< bool > ap_block_state2_pp0_stage0_iter0;
sc_signal< bool > ap_block_state3_pp0_stage0_iter1;
sc_signal< bool > ap_block_state4_pp0_stage0_iter2;
sc_signal< bool > ap_block_state5_pp0_stage0_iter3;
sc_signal< bool > ap_block_state6_pp0_stage0_iter4;
sc_signal< bool > ap_block_pp0_stage0_11001;
sc_signal< sc_lv<8> > val_V_reg_876_pp0_iter1_reg;
sc_signal< sc_lv<17> > grp_fu_664_p3;
sc_signal< sc_lv<17> > ret_V_reg_882;
sc_signal< sc_logic > ap_enable_reg_pp0_iter1;
sc_signal< sc_lv<11> > ps_V_fu_437_p2;
sc_signal< sc_lv<11> > ps_V_reg_887;
sc_signal< sc_lv<22> > sum_V_fu_454_p2;
sc_signal< sc_lv<22> > sum_V_reg_892;
sc_signal< sc_logic > ap_enable_reg_pp0_iter2;
sc_signal< sc_lv<17> > res_2_V_fu_476_p3;
sc_signal< sc_lv<17> > res_2_V_reg_897;
sc_signal< sc_lv<22> > ret_V_6_fu_672_p2;
sc_signal< sc_lv<22> > ret_V_6_reg_902;
sc_signal< sc_lv<27> > mul_ln895_fu_678_p2;
sc_signal< sc_lv<27> > mul_ln895_reg_907;
sc_signal< sc_logic > ap_CS_fsm_state1;
sc_signal< bool > ap_block_pp0_stage0_subdone;
sc_signal< sc_logic > ap_enable_reg_pp0_iter3;
sc_signal< sc_lv<22> > ap_phi_mux_p_0108_0_phi_fu_225_p4;
sc_signal< sc_lv<8> > p_0343_0_fu_80;
sc_signal< sc_lv<8> > ap_sig_allocacmp_p_0343_0_load;
sc_signal< sc_lv<8> > x0_V_fu_84;
sc_signal< sc_lv<8> > buffer_1_V_fu_88;
sc_signal< sc_lv<8> > buffer_2_V_fu_92;
sc_signal< sc_lv<8> > buffer_3_V_fu_96;
sc_signal< sc_lv<8> > buffer_4_V_fu_100;
sc_signal< sc_lv<8> > buffer_5_V_fu_104;
sc_signal< sc_lv<8> > buffer_6_V_fu_108;
sc_signal< sc_lv<8> > buffer_7_V_fu_112;
sc_signal< sc_lv<8> > buffer_8_V_fu_116;
sc_signal< sc_lv<8> > buffer_9_V_fu_120;
sc_signal< sc_lv<8> > buffer_10_V_fu_124;
sc_signal< sc_lv<8> > buffer_11_V_fu_128;
sc_signal< sc_lv<8> > buffer_12_V_fu_132;
sc_signal< sc_lv<8> > buffer_13_V_fu_136;
sc_signal< sc_lv<8> > buffer_14_V_fu_140;
sc_signal< sc_lv<8> > buffer_15_V_fu_144;
sc_signal< sc_lv<8> > buffer_16_V_fu_148;
sc_signal< sc_lv<8> > buffer_17_V_fu_152;
sc_signal< sc_lv<8> > buffer_18_V_fu_156;
sc_signal< sc_lv<8> > buffer_19_V_fu_160;
sc_signal< sc_lv<8> > buffer_20_V_fu_164;
sc_signal< sc_lv<8> > buffer_21_V_fu_168;
sc_signal< sc_lv<8> > buffer_22_V_fu_172;
sc_signal< sc_lv<8> > buffer_23_V_fu_176;
sc_signal< sc_lv<8> > buffer_24_V_fu_180;
sc_signal< sc_lv<8> > buffer_25_V_fu_184;
sc_signal< sc_lv<8> > buffer_26_V_fu_188;
sc_signal< sc_lv<8> > buffer_27_V_fu_192;
sc_signal< sc_lv<8> > buffer_28_V_fu_196;
sc_signal< sc_lv<8> > buffer_29_V_fu_200;
sc_signal< sc_lv<8> > buffer_30_V_fu_204;
sc_signal< bool > ap_block_pp0_stage0_01001;
sc_signal< sc_lv<8> > ret_V_5_fu_242_p0;
sc_signal< sc_lv<16> > lhs_V_5_fu_239_p1;
sc_signal< sc_lv<8> > ret_V_5_fu_242_p1;
sc_signal< sc_lv<16> > ret_V_5_fu_242_p2;
sc_signal< sc_lv<9> > zext_ln215_fu_345_p1;
sc_signal< sc_lv<9> > zext_ln215_1_fu_349_p1;
sc_signal< sc_lv<9> > add_ln215_fu_377_p2;
sc_signal< sc_lv<9> > zext_ln215_3_fu_357_p1;
sc_signal< sc_lv<9> > zext_ln215_2_fu_353_p1;
sc_signal< sc_lv<9> > add_ln215_1_fu_387_p2;
sc_signal< sc_lv<10> > zext_ln215_8_fu_383_p1;
sc_signal< sc_lv<10> > zext_ln215_9_fu_393_p1;
sc_signal< sc_lv<10> > add_ln215_2_fu_397_p2;
sc_signal< sc_lv<9> > zext_ln215_5_fu_365_p1;
sc_signal< sc_lv<9> > zext_ln215_4_fu_361_p1;
sc_signal< sc_lv<9> > add_ln215_3_fu_407_p2;
sc_signal< sc_lv<9> > zext_ln215_7_fu_373_p1;
sc_signal< sc_lv<9> > zext_ln215_6_fu_369_p1;
sc_signal< sc_lv<9> > add_ln215_4_fu_417_p2;
sc_signal< sc_lv<10> > zext_ln215_11_fu_413_p1;
sc_signal< sc_lv<10> > zext_ln215_12_fu_423_p1;
sc_signal< sc_lv<10> > add_ln215_5_fu_427_p2;
sc_signal< sc_lv<11> > zext_ln215_10_fu_403_p1;
sc_signal< sc_lv<11> > zext_ln215_13_fu_433_p1;
sc_signal< sc_lv<20> > shl_ln_fu_443_p3;
sc_signal< sc_lv<22> > sext_ln700_fu_450_p1;
sc_signal< sc_lv<17> > trunc_ln_fu_460_p4;
sc_signal< sc_lv<1> > icmp_ln879_fu_470_p2;
sc_signal< sc_lv<27> > zext_ln895_1_fu_649_p1;
sc_signal< sc_lv<1> > icmp_ln895_fu_652_p2;
sc_signal< sc_lv<8> > grp_fu_664_p0;
sc_signal< sc_lv<16> > lhs_V_4_fu_235_p1;
sc_signal< sc_lv<8> > grp_fu_664_p1;
sc_signal< sc_lv<16> > grp_fu_664_p2;
sc_signal< sc_lv<11> > ret_V_6_fu_672_p0;
sc_signal< sc_lv<22> > lhs_V_6_fu_643_p1;
sc_signal< sc_lv<11> > ret_V_6_fu_672_p1;
sc_signal< sc_lv<17> > mul_ln895_fu_678_p0;
sc_signal< sc_lv<6> > mul_ln895_fu_678_p1;
sc_signal< sc_lv<2> > ap_NS_fsm;
sc_signal< sc_logic > ap_idle_pp0;
sc_signal< sc_logic > ap_enable_pp0;
sc_signal< sc_lv<17> > grp_fu_664_p20;
sc_signal< sc_lv<27> > mul_ln895_fu_678_p00;
static const sc_logic ap_const_logic_1;
static const sc_logic ap_const_logic_0;
static const sc_lv<2> ap_ST_fsm_state1;
static const sc_lv<2> ap_ST_fsm_pp0_stage0;
static const bool ap_const_boolean_1;
static const sc_lv<32> ap_const_lv32_1;
static const bool ap_const_boolean_0;
static const sc_lv<32> ap_const_lv32_0;
static const sc_lv<22> ap_const_lv22_0;
static const sc_lv<3> ap_const_lv3_0;
static const sc_lv<32> ap_const_lv32_5;
static const sc_lv<32> ap_const_lv32_15;
static const sc_lv<17> ap_const_lv17_0;
static const sc_lv<17> ap_const_lv17_1F;
static const sc_lv<1> ap_const_lv1_1;
static const sc_lv<27> ap_const_lv27_1B;
// Thread declarations
void thread_ap_clk_no_reset_();
void thread_add_ln215_1_fu_387_p2();
void thread_add_ln215_2_fu_397_p2();
void thread_add_ln215_3_fu_407_p2();
void thread_add_ln215_4_fu_417_p2();
void thread_add_ln215_5_fu_427_p2();
void thread_add_ln215_fu_377_p2();
void thread_ap_CS_fsm_pp0_stage0();
void thread_ap_CS_fsm_state1();
void thread_ap_block_pp0_stage0();
void thread_ap_block_pp0_stage0_01001();
void thread_ap_block_pp0_stage0_11001();
void thread_ap_block_pp0_stage0_subdone();
void thread_ap_block_state2_pp0_stage0_iter0();
void thread_ap_block_state3_pp0_stage0_iter1();
void thread_ap_block_state4_pp0_stage0_iter2();
void thread_ap_block_state5_pp0_stage0_iter3();
void thread_ap_block_state6_pp0_stage0_iter4();
void thread_ap_enable_pp0();
void thread_ap_idle_pp0();
void thread_ap_phi_mux_p_0108_0_phi_fu_225_p4();
void thread_ap_sig_allocacmp_p_0343_0_load();
void thread_detect_blk_n();
void thread_detect_din();
void thread_detect_write();
void thread_e_blk_n();
void thread_e_read();
void thread_grp_fu_664_p0();
void thread_grp_fu_664_p1();
void thread_grp_fu_664_p2();
void thread_grp_fu_664_p20();
void thread_icmp_ln879_fu_470_p2();
void thread_icmp_ln895_fu_652_p2();
void thread_lhs_V_4_fu_235_p1();
void thread_lhs_V_5_fu_239_p1();
void thread_lhs_V_6_fu_643_p1();
void thread_mul_ln895_fu_678_p0();
void thread_mul_ln895_fu_678_p00();
void thread_mul_ln895_fu_678_p1();
void thread_ps_V_fu_437_p2();
void thread_res_2_V_fu_476_p3();
void thread_ret_V_5_fu_242_p0();
void thread_ret_V_5_fu_242_p1();
void thread_ret_V_5_fu_242_p2();
void thread_ret_V_6_fu_672_p0();
void thread_ret_V_6_fu_672_p1();
void thread_sext_ln700_fu_450_p1();
void thread_shl_ln_fu_443_p3();
void thread_sum_V_fu_454_p2();
void thread_trunc_ln_fu_460_p4();
void thread_zext_ln215_10_fu_403_p1();
void thread_zext_ln215_11_fu_413_p1();
void thread_zext_ln215_12_fu_423_p1();
void thread_zext_ln215_13_fu_433_p1();
void thread_zext_ln215_1_fu_349_p1();
void thread_zext_ln215_2_fu_353_p1();
void thread_zext_ln215_3_fu_357_p1();
void thread_zext_ln215_4_fu_361_p1();
void thread_zext_ln215_5_fu_365_p1();
void thread_zext_ln215_6_fu_369_p1();
void thread_zext_ln215_7_fu_373_p1();
void thread_zext_ln215_8_fu_383_p1();
void thread_zext_ln215_9_fu_393_p1();
void thread_zext_ln215_fu_345_p1();
void thread_zext_ln895_1_fu_649_p1();
void thread_ap_NS_fsm();
};
}
using namespace ap_rtl;
#endif
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.3
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _DoCompute_HH_
#define _DoCompute_HH_
#include "systemc.h"
#include "AESL_pkg.h"
#include "Mem2Stream_Batch12.h"
#include "Matrix_Vector_Activa.h"
#include "Matrix_Vector_Activa_3.h"
#include "Matrix_Vector_Activa_2.h"
#include "StreamingDataWidthCo.h"
#include "Matrix_Vector_Activa_1.h"
#include "StreamingDataWidthCo_1.h"
#include "Stream2Mem_Batch.h"
#include "DoCompute_memInSthbi.h"
#include "DoCompute_numRepsibs.h"
#include "DoCompute_out_V3_jbC.h"
#include "DoCompute_inter0_kbM.h"
#include "DoCompute_numRepslbW.h"
#include "DoCompute_inter1_mb6.h"
#include "DoCompute_numRepsncg.h"
#include "DoCompute_inter2_ocq.h"
#include "DoCompute_numRepspcA.h"
#include "DoCompute_wa_in_mqcK.h"
#include "DoCompute_numRepsrcU.h"
#include "DoCompute_wa_out_sc4.h"
#include "DoCompute_numRepstde.h"
#include "DoCompute_memOutSudo.h"
#include "DoCompute_numRepsvdy.h"
#include "start_for_StreamiwdI.h"
#include "start_for_StreamixdS.h"
namespace ap_rtl {
struct DoCompute : public sc_module {
// Port declarations 2938
sc_out< sc_logic > m_axi_in_V_AWVALID;
sc_in< sc_logic > m_axi_in_V_AWREADY;
sc_out< sc_lv<64> > m_axi_in_V_AWADDR;
sc_out< sc_lv<1> > m_axi_in_V_AWID;
sc_out< sc_lv<32> > m_axi_in_V_AWLEN;
sc_out< sc_lv<3> > m_axi_in_V_AWSIZE;
sc_out< sc_lv<2> > m_axi_in_V_AWBURST;
sc_out< sc_lv<2> > m_axi_in_V_AWLOCK;
sc_out< sc_lv<4> > m_axi_in_V_AWCACHE;
sc_out< sc_lv<3> > m_axi_in_V_AWPROT;
sc_out< sc_lv<4> > m_axi_in_V_AWQOS;
sc_out< sc_lv<4> > m_axi_in_V_AWREGION;
sc_out< sc_lv<1> > m_axi_in_V_AWUSER;
sc_out< sc_logic > m_axi_in_V_WVALID;
sc_in< sc_logic > m_axi_in_V_WREADY;
sc_out< sc_lv<64> > m_axi_in_V_WDATA;
sc_out< sc_lv<8> > m_axi_in_V_WSTRB;
sc_out< sc_logic > m_axi_in_V_WLAST;
sc_out< sc_lv<1> > m_axi_in_V_WID;
sc_out< sc_lv<1> > m_axi_in_V_WUSER;
sc_out< sc_logic > m_axi_in_V_ARVALID;
sc_in< sc_logic > m_axi_in_V_ARREADY;
sc_out< sc_lv<64> > m_axi_in_V_ARADDR;
sc_out< sc_lv<1> > m_axi_in_V_ARID;
sc_out< sc_lv<32> > m_axi_in_V_ARLEN;
sc_out< sc_lv<3> > m_axi_in_V_ARSIZE;
sc_out< sc_lv<2> > m_axi_in_V_ARBURST;
sc_out< sc_lv<2> > m_axi_in_V_ARLOCK;
sc_out< sc_lv<4> > m_axi_in_V_ARCACHE;
sc_out< sc_lv<3> > m_axi_in_V_ARPROT;
sc_out< sc_lv<4> > m_axi_in_V_ARQOS;
sc_out< sc_lv<4> > m_axi_in_V_ARREGION;
sc_out< sc_lv<1> > m_axi_in_V_ARUSER;
sc_in< sc_logic > m_axi_in_V_RVALID;
sc_out< sc_logic > m_axi_in_V_RREADY;
sc_in< sc_lv<64> > m_axi_in_V_RDATA;
sc_in< sc_logic > m_axi_in_V_RLAST;
sc_in< sc_lv<1> > m_axi_in_V_RID;
sc_in< sc_lv<1> > m_axi_in_V_RUSER;
sc_in< sc_lv<2> > m_axi_in_V_RRESP;
sc_in< sc_logic > m_axi_in_V_BVALID;
sc_out< sc_logic > m_axi_in_V_BREADY;
sc_in< sc_lv<2> > m_axi_in_V_BRESP;
sc_in< sc_lv<1> > m_axi_in_V_BID;
sc_in< sc_lv<1> > m_axi_in_V_BUSER;
sc_in< sc_lv<61> > in_V1;
sc_in< sc_lv<61> > out_V3;
sc_in< sc_lv<32> > numReps;
sc_out< sc_lv<9> > weights0_m_weights_V_address0;
sc_out< sc_logic > weights0_m_weights_V_ce0;
sc_out< sc_lv<64> > weights0_m_weights_V_d0;
sc_in< sc_lv<64> > weights0_m_weights_V_q0;
sc_out< sc_logic > weights0_m_weights_V_we0;
sc_out< sc_lv<9> > weights0_m_weights_V_address1;
sc_out< sc_logic > weights0_m_weights_V_ce1;
sc_out< sc_lv<64> > weights0_m_weights_V_d1;
sc_in< sc_lv<64> > weights0_m_weights_V_q1;
sc_out< sc_logic > weights0_m_weights_V_we1;
sc_out< sc_lv<9> > weights0_m_weights_V_1_address0;
sc_out< sc_logic > weights0_m_weights_V_1_ce0;
sc_out< sc_lv<64> > weights0_m_weights_V_1_d0;
sc_in< sc_lv<64> > weights0_m_weights_V_1_q0;
sc_out< sc_logic > weights0_m_weights_V_1_we0;
sc_out< sc_lv<9> > weights0_m_weights_V_1_address1;
sc_out< sc_logic > weights0_m_weights_V_1_ce1;
sc_out< sc_lv<64> > weights0_m_weights_V_1_d1;
sc_in< sc_lv<64> > weights0_m_weights_V_1_q1;
sc_out< sc_logic > weights0_m_weights_V_1_we1;
sc_out< sc_lv<9> > weights0_m_weights_V_2_address0;
sc_out< sc_logic > weights0_m_weights_V_2_ce0;
sc_out< sc_lv<64> > weights0_m_weights_V_2_d0;
sc_in< sc_lv<64> > weights0_m_weights_V_2_q0;
sc_out< sc_logic > weights0_m_weights_V_2_we0;
sc_out< sc_lv<9> > weights0_m_weights_V_2_address1;
sc_out< sc_logic > weights0_m_weights_V_2_ce1;
sc_out< sc_lv<64> > weights0_m_weights_V_2_d1;
sc_in< sc_lv<64> > weights0_m_weights_V_2_q1;
sc_out< sc_logic > weights0_m_weights_V_2_we1;
sc_out< sc_lv<9> > weights0_m_weights_V_3_address0;
sc_out< sc_logic > weights0_m_weights_V_3_ce0;
sc_out< sc_lv<64> > weights0_m_weights_V_3_d0;
sc_in< sc_lv<64> > weights0_m_weights_V_3_q0;
sc_out< sc_logic > weights0_m_weights_V_3_we0;
sc_out< sc_lv<9> > weights0_m_weights_V_3_address1;
sc_out< sc_logic > weights0_m_weights_V_3_ce1;
sc_out< sc_lv<64> > weights0_m_weights_V_3_d1;
sc_in< sc_lv<64> > weights0_m_weights_V_3_q1;
sc_out< sc_logic > weights0_m_weights_V_3_we1;
sc_out< sc_lv<9> > weights0_m_weights_V_4_address0;
sc_out< sc_logic > weights0_m_weights_V_4_ce0;
sc_out< sc_lv<64> > weights0_m_weights_V_4_d0;
sc_in< sc_lv<64> > weights0_m_weights_V_4_q0;
sc_out< sc_logic > weights0_m_weights_V_4_we0;
sc_out< sc_lv<9> > weights0_m_weights_V_4_address1;
sc_out< sc_logic > weights0_m_weights_V_4_ce1;
sc_out< sc_lv<64> > weights0_m_weights_V_4_d1;
sc_in< sc_lv<64> > weights0_m_weights_V_4_q1;
sc_out< sc_logic > weights0_m_weights_V_4_we1;
sc_out< sc_lv<9> > weights0_m_weights_V_5_address0;
sc_out< sc_logic > weights0_m_weights_V_5_ce0;
sc_out< sc_lv<64> > weights0_m_weights_V_5_d0;
sc_in< sc_lv<64> > weights0_m_weights_V_5_q0;
sc_out< sc_logic > weights0_m_weights_V_5_we0;
sc_out< sc_lv<9> > weights0_m_weights_V_5_address1;
sc_out< sc_logic > weights0_m_weights_V_5_ce1;
sc_out< sc_lv<64> > weights0_m_weights_V_5_d1;
sc_in< sc_lv<64> > weights0_m_weights_V_5_q1;
sc_out< sc_logic > weights0_m_weights_V_5_we1;
sc_out< sc_lv<9> > weights0_m_weights_V_6_address0;
sc_out< sc_logic > weights0_m_weights_V_6_ce0;
sc_out< sc_lv<64> > weights0_m_weights_V_6_d0;
sc_in< sc_lv<64> > weights0_m_weights_V_6_q0;
sc_out< sc_logic > weights0_m_weights_V_6_we0;
sc_out< sc_lv<9> > weights0_m_weights_V_6_address1;
sc_out< sc_logic > weights0_m_weights_V_6_ce1;
sc_out< sc_lv<64> > weights0_m_weights_V_6_d1;
sc_in< sc_lv<64> > weights0_m_weights_V_6_q1;
sc_out< sc_logic > weights0_m_weights_V_6_we1;
sc_out< sc_lv<9> > weights0_m_weights_V_7_address0;
sc_out< sc_logic > weights0_m_weights_V_7_ce0;
sc_out< sc_lv<64> > weights0_m_weights_V_7_d0;
sc_in< sc_lv<64> > weights0_m_weights_V_7_q0;
sc_out< sc_logic > weights0_m_weights_V_7_we0;
sc_out< sc_lv<9> > weights0_m_weights_V_7_address1;
sc_out< sc_logic > weights0_m_weights_V_7_ce1;
sc_out< sc_lv<64> > weights0_m_weights_V_7_d1;
sc_in< sc_lv<64> > weights0_m_weights_V_7_q1;
sc_out< sc_logic > weights0_m_weights_V_7_we1;
sc_out< sc_lv<9> > weights0_m_weights_V_8_address0;
sc_out< sc_logic > weights0_m_weights_V_8_ce0;
sc_out< sc_lv<64> > weights0_m_weights_V_8_d0;
sc_in< sc_lv<64> > weights0_m_weights_V_8_q0;
sc_out< sc_logic > weights0_m_weights_V_8_we0;
sc_out< sc_lv<9> > weights0_m_weights_V_8_address1;
sc_out< sc_logic > weights0_m_weights_V_8_ce1;
sc_out< sc_lv<64> > weights0_m_weights_V_8_d1;
sc_in< sc_lv<64> > weights0_m_weights_V_8_q1;
sc_out< sc_logic > weights0_m_weights_V_8_we1;
sc_out< sc_lv<9> > weights0_m_weights_V_9_address0;
sc_out< sc_logic > weights0_m_weights_V_9_ce0;
sc_out< sc_lv<64> > weights0_m_weights_V_9_d0;
sc_in< sc_lv<64> > weights0_m_weights_V_9_q0;
sc_out< sc_logic > weights0_m_weights_V_9_we0;
sc_out< sc_lv<9> > weights0_m_weights_V_9_address1;
sc_out< sc_logic > weights0_m_weights_V_9_ce1;
sc_out< sc_lv<64> > weights0_m_weights_V_9_d1;
sc_in< sc_lv<64> > weights0_m_weights_V_9_q1;
sc_out< sc_logic > weights0_m_weights_V_9_we1;
sc_out< sc_lv<9> > weights0_m_weights_V_10_address0;
sc_out< sc_logic > weights0_m_weights_V_10_ce0;
sc_out< sc_lv<64> > weights0_m_weights_V_10_d0;
sc_in< sc_lv<64> > weights0_m_weights_V_10_q0;
sc_out< sc_logic > weights0_m_weights_V_10_we0;
sc_out< sc_lv<9> > weights0_m_weights_V_10_address1;
sc_out< sc_logic > weights0_m_weights_V_10_ce1;
sc_out< sc_lv<64> > weights0_m_weights_V_10_d1;
sc_in< sc_lv<64> > weights0_m_weights_V_10_q1;
sc_out< sc_logic > weights0_m_weights_V_10_we1;
sc_out< sc_lv<9> > weights0_m_weights_V_11_address0;
sc_out< sc_logic > weights0_m_weights_V_11_ce0;
sc_out< sc_lv<64> > weights0_m_weights_V_11_d0;
sc_in< sc_lv<64> > weights0_m_weights_V_11_q0;
sc_out< sc_logic > weights0_m_weights_V_11_we0;
sc_out< sc_lv<9> > weights0_m_weights_V_11_address1;
sc_out< sc_logic > weights0_m_weights_V_11_ce1;
sc_out< sc_lv<64> > weights0_m_weights_V_11_d1;
sc_in< sc_lv<64> > weights0_m_weights_V_11_q1;
sc_out< sc_logic > weights0_m_weights_V_11_we1;
sc_out< sc_lv<9> > weights0_m_weights_V_12_address0;
sc_out< sc_logic > weights0_m_weights_V_12_ce0;
sc_out< sc_lv<64> > weights0_m_weights_V_12_d0;
sc_in< sc_lv<64> > weights0_m_weights_V_12_q0;
sc_out< sc_logic > weights0_m_weights_V_12_we0;
sc_out< sc_lv<9> > weights0_m_weights_V_12_address1;
sc_out< sc_logic > weights0_m_weights_V_12_ce1;
sc_out< sc_lv<64> > weights0_m_weights_V_12_d1;
sc_in< sc_lv<64> > weights0_m_weights_V_12_q1;
sc_out< sc_logic > weights0_m_weights_V_12_we1;
sc_out< sc_lv<9> > weights0_m_weights_V_13_address0;
sc_out< sc_logic > weights0_m_weights_V_13_ce0;
sc_out< sc_lv<64> > weights0_m_weights_V_13_d0;
sc_in< sc_lv<64> > weights0_m_weights_V_13_q0;
sc_out< sc_logic > weights0_m_weights_V_13_we0;
sc_out< sc_lv<9> > weights0_m_weights_V_13_address1;
sc_out< sc_logic > weights0_m_weights_V_13_ce1;
sc_out< sc_lv<64> > weights0_m_weights_V_13_d1;
sc_in< sc_lv<64> > weights0_m_weights_V_13_q1;
sc_out< sc_logic > weights0_m_weights_V_13_we1;
sc_out< sc_lv<9> > weights0_m_weights_V_14_address0;
sc_out< sc_logic > weights0_m_weights_V_14_ce0;
sc_out< sc_lv<64> > weights0_m_weights_V_14_d0;
sc_in< sc_lv<64> > weights0_m_weights_V_14_q0;
sc_out< sc_logic > weights0_m_weights_V_14_we0;
sc_out< sc_lv<9> > weights0_m_weights_V_14_address1;
sc_out< sc_logic > weights0_m_weights_V_14_ce1;
sc_out< sc_lv<64> > weights0_m_weights_V_14_d1;
sc_in< sc_lv<64> > weights0_m_weights_V_14_q1;
sc_out< sc_logic > weights0_m_weights_V_14_we1;
sc_out< sc_lv<9> > weights0_m_weights_V_15_address0;
sc_out< sc_logic > weights0_m_weights_V_15_ce0;
sc_out< sc_lv<64> > weights0_m_weights_V_15_d0;
sc_in< sc_lv<64> > weights0_m_weights_V_15_q0;
sc_out< sc_logic > weights0_m_weights_V_15_we0;
sc_out< sc_lv<9> > weights0_m_weights_V_15_address1;
sc_out< sc_logic > weights0_m_weights_V_15_ce1;
sc_out< sc_lv<64> > weights0_m_weights_V_15_d1;
sc_in< sc_lv<64> > weights0_m_weights_V_15_q1;
sc_out< sc_logic > weights0_m_weights_V_15_we1;
sc_out< sc_lv<9> > weights0_m_weights_V_16_address0;
sc_out< sc_logic > weights0_m_weights_V_16_ce0;
sc_out< sc_lv<64> > weights0_m_weights_V_16_d0;
sc_in< sc_lv<64> > weights0_m_weights_V_16_q0;
sc_out< sc_logic > weights0_m_weights_V_16_we0;
sc_out< sc_lv<9> > weights0_m_weights_V_16_address1;
sc_out< sc_logic > weights0_m_weights_V_16_ce1;
sc_out< sc_lv<64> > weights0_m_weights_V_16_d1;
sc_in< sc_lv<64> > weights0_m_weights_V_16_q1;
sc_out< sc_logic > weights0_m_weights_V_16_we1;
sc_out< sc_lv<9> > weights0_m_weights_V_17_address0;
sc_out< sc_logic > weights0_m_weights_V_17_ce0;
sc_out< sc_lv<64> > weights0_m_weights_V_17_d0;
sc_in< sc_lv<64> > weights0_m_weights_V_17_q0;
sc_out< sc_logic > weights0_m_weights_V_17_we0;
sc_out< sc_lv<9> > weights0_m_weights_V_17_address1;
sc_out< sc_logic > weights0_m_weights_V_17_ce1;
sc_out< sc_lv<64> > weights0_m_weights_V_17_d1;
sc_in< sc_lv<64> > weights0_m_weights_V_17_q1;
sc_out< sc_logic > weights0_m_weights_V_17_we1;
sc_out< sc_lv<9> > weights0_m_weights_V_18_address0;
sc_out< sc_logic > weights0_m_weights_V_18_ce0;
sc_out< sc_lv<64> > weights0_m_weights_V_18_d0;
sc_in< sc_lv<64> > weights0_m_weights_V_18_q0;
sc_out< sc_logic > weights0_m_weights_V_18_we0;
sc_out< sc_lv<9> > weights0_m_weights_V_18_address1;
sc_out< sc_logic > weights0_m_weights_V_18_ce1;
sc_out< sc_lv<64> > weights0_m_weights_V_18_d1;
sc_in< sc_lv<64> > weights0_m_weights_V_18_q1;
sc_out< sc_logic > weights0_m_weights_V_18_we1;
sc_out< sc_lv<9> > weights0_m_weights_V_19_address0;
sc_out< sc_logic > weights0_m_weights_V_19_ce0;
sc_out< sc_lv<64> > weights0_m_weights_V_19_d0;
sc_in< sc_lv<64> > weights0_m_weights_V_19_q0;
sc_out< sc_logic > weights0_m_weights_V_19_we0;
sc_out< sc_lv<9> > weights0_m_weights_V_19_address1;
sc_out< sc_logic > weights0_m_weights_V_19_ce1;
sc_out< sc_lv<64> > weights0_m_weights_V_19_d1;
sc_in< sc_lv<64> > weights0_m_weights_V_19_q1;
sc_out< sc_logic > weights0_m_weights_V_19_we1;
sc_out< sc_lv<9> > weights0_m_weights_V_20_address0;
sc_out< sc_logic > weights0_m_weights_V_20_ce0;
sc_out< sc_lv<64> > weights0_m_weights_V_20_d0;
sc_in< sc_lv<64> > weights0_m_weights_V_20_q0;
sc_out< sc_logic > weights0_m_weights_V_20_we0;
sc_out< sc_lv<9> > weights0_m_weights_V_20_address1;
sc_out< sc_logic > weights0_m_weights_V_20_ce1;
sc_out< sc_lv<64> > weights0_m_weights_V_20_d1;
sc_in< sc_lv<64> > weights0_m_weights_V_20_q1;
sc_out< sc_logic > weights0_m_weights_V_20_we1;
sc_out< sc_lv<9> > weights0_m_weights_V_21_address0;
sc_out< sc_logic > weights0_m_weights_V_21_ce0;
sc_out< sc_lv<64> > weights0_m_weights_V_21_d0;
sc_in< sc_lv<64> > weights0_m_weights_V_21_q0;
sc_out< sc_logic > weights0_m_weights_V_21_we0;
sc_out< sc_lv<9> > weights0_m_weights_V_21_address1;
sc_out< sc_logic > weights0_m_weights_V_21_ce1;
sc_out< sc_lv<64> > weights0_m_weights_V_21_d1;
sc_in< sc_lv<64> > weights0_m_weights_V_21_q1;
sc_out< sc_logic > weights0_m_weights_V_21_we1;
sc_out< sc_lv<9> > weights0_m_weights_V_22_address0;
sc_out< sc_logic > weights0_m_weights_V_22_ce0;
sc_out< sc_lv<64> > weights0_m_weights_V_22_d0;
sc_in< sc_lv<64> > weights0_m_weights_V_22_q0;
sc_out< sc_logic > weights0_m_weights_V_22_we0;
sc_out< sc_lv<9> > weights0_m_weights_V_22_address1;
sc_out< sc_logic > weights0_m_weights_V_22_ce1;
sc_out< sc_lv<64> > weights0_m_weights_V_22_d1;
sc_in< sc_lv<64> > weights0_m_weights_V_22_q1;
sc_out< sc_logic > weights0_m_weights_V_22_we1;
sc_out< sc_lv<9> > weights0_m_weights_V_23_address0;
sc_out< sc_logic > weights0_m_weights_V_23_ce0;
sc_out< sc_lv<64> > weights0_m_weights_V_23_d0;
sc_in< sc_lv<64> > weights0_m_weights_V_23_q0;
sc_out< sc_logic > weights0_m_weights_V_23_we0;
sc_out< sc_lv<9> > weights0_m_weights_V_23_address1;
sc_out< sc_logic > weights0_m_weights_V_23_ce1;
sc_out< sc_lv<64> > weights0_m_weights_V_23_d1;
sc_in< sc_lv<64> > weights0_m_weights_V_23_q1;
sc_out< sc_logic > weights0_m_weights_V_23_we1;
sc_out< sc_lv<9> > weights0_m_weights_V_24_address0;
sc_out< sc_logic > weights0_m_weights_V_24_ce0;
sc_out< sc_lv<64> > weights0_m_weights_V_24_d0;
sc_in< sc_lv<64> > weights0_m_weights_V_24_q0;
sc_out< sc_logic > weights0_m_weights_V_24_we0;
sc_out< sc_lv<9> > weights0_m_weights_V_24_address1;
sc_out< sc_logic > weights0_m_weights_V_24_ce1;
sc_out< sc_lv<64> > weights0_m_weights_V_24_d1;
sc_in< sc_lv<64> > weights0_m_weights_V_24_q1;
sc_out< sc_logic > weights0_m_weights_V_24_we1;
sc_out< sc_lv<9> > weights0_m_weights_V_25_address0;
sc_out< sc_logic > weights0_m_weights_V_25_ce0;
sc_out< sc_lv<64> > weights0_m_weights_V_25_d0;
sc_in< sc_lv<64> > weights0_m_weights_V_25_q0;
sc_out< sc_logic > weights0_m_weights_V_25_we0;
sc_out< sc_lv<9> > weights0_m_weights_V_25_address1;
sc_out< sc_logic > weights0_m_weights_V_25_ce1;
sc_out< sc_lv<64> > weights0_m_weights_V_25_d1;
sc_in< sc_lv<64> > weights0_m_weights_V_25_q1;
sc_out< sc_logic > weights0_m_weights_V_25_we1;
sc_out< sc_lv<9> > weights0_m_weights_V_26_address0;
sc_out< sc_logic > weights0_m_weights_V_26_ce0;
sc_out< sc_lv<64> > weights0_m_weights_V_26_d0;
sc_in< sc_lv<64> > weights0_m_weights_V_26_q0;
sc_out< sc_logic > weights0_m_weights_V_26_we0;
sc_out< sc_lv<9> > weights0_m_weights_V_26_address1;
sc_out< sc_logic > weights0_m_weights_V_26_ce1;
sc_out< sc_lv<64> > weights0_m_weights_V_26_d1;
sc_in< sc_lv<64> > weights0_m_weights_V_26_q1;
sc_out< sc_logic > weights0_m_weights_V_26_we1;
sc_out< sc_lv<9> > weights0_m_weights_V_27_address0;
sc_out< sc_logic > weights0_m_weights_V_27_ce0;
sc_out< sc_lv<64> > weights0_m_weights_V_27_d0;
sc_in< sc_lv<64> > weights0_m_weights_V_27_q0;
sc_out< sc_logic > weights0_m_weights_V_27_we0;
sc_out< sc_lv<9> > weights0_m_weights_V_27_address1;
sc_out< sc_logic > weights0_m_weights_V_27_ce1;
sc_out< sc_lv<64> > weights0_m_weights_V_27_d1;
sc_in< sc_lv<64> > weights0_m_weights_V_27_q1;
sc_out< sc_logic > weights0_m_weights_V_27_we1;
sc_out< sc_lv<9> > weights0_m_weights_V_28_address0;
sc_out< sc_logic > weights0_m_weights_V_28_ce0;
sc_out< sc_lv<64> > weights0_m_weights_V_28_d0;
sc_in< sc_lv<64> > weights0_m_weights_V_28_q0;
sc_out< sc_logic > weights0_m_weights_V_28_we0;
sc_out< sc_lv<9> > weights0_m_weights_V_28_address1;
sc_out< sc_logic > weights0_m_weights_V_28_ce1;
sc_out< sc_lv<64> > weights0_m_weights_V_28_d1;
sc_in< sc_lv<64> > weights0_m_weights_V_28_q1;
sc_out< sc_logic > weights0_m_weights_V_28_we1;
sc_out< sc_lv<9> > weights0_m_weights_V_29_address0;
sc_out< sc_logic > weights0_m_weights_V_29_ce0;
sc_out< sc_lv<64> > weights0_m_weights_V_29_d0;
sc_in< sc_lv<64> > weights0_m_weights_V_29_q0;
sc_out< sc_logic > weights0_m_weights_V_29_we0;
sc_out< sc_lv<9> > weights0_m_weights_V_29_address1;
sc_out< sc_logic > weights0_m_weights_V_29_ce1;
sc_out< sc_lv<64> > weights0_m_weights_V_29_d1;
sc_in< sc_lv<64> > weights0_m_weights_V_29_q1;
sc_out< sc_logic > weights0_m_weights_V_29_we1;
sc_out< sc_lv<9> > weights0_m_weights_V_30_address0;
sc_out< sc_logic > weights0_m_weights_V_30_ce0;
sc_out< sc_lv<64> > weights0_m_weights_V_30_d0;
sc_in< sc_lv<64> > weights0_m_weights_V_30_q0;
sc_out< sc_logic > weights0_m_weights_V_30_we0;
sc_out< sc_lv<9> > weights0_m_weights_V_30_address1;
sc_out< sc_logic > weights0_m_weights_V_30_ce1;
sc_out< sc_lv<64> > weights0_m_weights_V_30_d1;
sc_in< sc_lv<64> > weights0_m_weights_V_30_q1;
sc_out< sc_logic > weights0_m_weights_V_30_we1;
sc_out< sc_lv<9> > weights0_m_weights_V_31_address0;
sc_out< sc_logic > weights0_m_weights_V_31_ce0;
sc_out< sc_lv<64> > weights0_m_weights_V_31_d0;
sc_in< sc_lv<64> > weights0_m_weights_V_31_q0;
sc_out< sc_logic > weights0_m_weights_V_31_we0;
sc_out< sc_lv<9> > weights0_m_weights_V_31_address1;
sc_out< sc_logic > weights0_m_weights_V_31_ce1;
sc_out< sc_lv<64> > weights0_m_weights_V_31_d1;
sc_in< sc_lv<64> > weights0_m_weig
|
hts_V_31_q1;
sc_out< sc_logic > weights0_m_weights_V_31_we1;
sc_out< sc_lv<5> > threshs0_m_threshold_31_address0;
sc_out< sc_logic > threshs0_m_threshold_31_ce0;
sc_out< sc_lv<16> > threshs0_m_threshold_31_d0;
sc_in< sc_lv<16> > threshs0_m_threshold_31_q0;
sc_out< sc_logic > threshs0_m_threshold_31_we0;
sc_out< sc_lv<5> > threshs0_m_threshold_31_address1;
sc_out< sc_logic > threshs0_m_threshold_31_ce1;
sc_out< sc_lv<16> > threshs0_m_threshold_31_d1;
sc_in< sc_lv<16> > threshs0_m_threshold_31_q1;
sc_out< sc_logic > threshs0_m_threshold_31_we1;
sc_out< sc_lv<5> > threshs0_m_threshold_30_address0;
sc_out< sc_logic > threshs0_m_threshold_30_ce0;
sc_out< sc_lv<16> > threshs0_m_threshold_30_d0;
sc_in< sc_lv<16> > threshs0_m_threshold_30_q0;
sc_out< sc_logic > threshs0_m_threshold_30_we0;
sc_out< sc_lv<5> > threshs0_m_threshold_30_address1;
sc_out< sc_logic > threshs0_m_threshold_30_ce1;
sc_out< sc_lv<16> > threshs0_m_threshold_30_d1;
sc_in< sc_lv<16> > threshs0_m_threshold_30_q1;
sc_out< sc_logic > threshs0_m_threshold_30_we1;
sc_out< sc_lv<5> > threshs0_m_threshold_19_address0;
sc_out< sc_logic > threshs0_m_threshold_19_ce0;
sc_out< sc_lv<16> > threshs0_m_threshold_19_d0;
sc_in< sc_lv<16> > threshs0_m_threshold_19_q0;
sc_out< sc_logic > threshs0_m_threshold_19_we0;
sc_out< sc_lv<5> > threshs0_m_threshold_19_address1;
sc_out< sc_logic > threshs0_m_threshold_19_ce1;
sc_out< sc_lv<16> > threshs0_m_threshold_19_d1;
sc_in< sc_lv<16> > threshs0_m_threshold_19_q1;
sc_out< sc_logic > threshs0_m_threshold_19_we1;
sc_out< sc_lv<5> > threshs0_m_threshold_8_address0;
sc_out< sc_logic > threshs0_m_threshold_8_ce0;
sc_out< sc_lv<16> > threshs0_m_threshold_8_d0;
sc_in< sc_lv<16> > threshs0_m_threshold_8_q0;
sc_out< sc_logic > threshs0_m_threshold_8_we0;
sc_out< sc_lv<5> > threshs0_m_threshold_8_address1;
sc_out< sc_logic > threshs0_m_threshold_8_ce1;
sc_out< sc_lv<16> > threshs0_m_threshold_8_d1;
sc_in< sc_lv<16> > threshs0_m_threshold_8_q1;
sc_out< sc_logic > threshs0_m_threshold_8_we1;
sc_out< sc_lv<5> > threshs0_m_threshold_5_address0;
sc_out< sc_logic > threshs0_m_threshold_5_ce0;
sc_out< sc_lv<16> > threshs0_m_threshold_5_d0;
sc_in< sc_lv<16> > threshs0_m_threshold_5_q0;
sc_out< sc_logic > threshs0_m_threshold_5_we0;
sc_out< sc_lv<5> > threshs0_m_threshold_5_address1;
sc_out< sc_logic > threshs0_m_threshold_5_ce1;
sc_out< sc_lv<16> > threshs0_m_threshold_5_d1;
sc_in< sc_lv<16> > threshs0_m_threshold_5_q1;
sc_out< sc_logic > threshs0_m_threshold_5_we1;
sc_out< sc_lv<5> > threshs0_m_threshold_4_address0;
sc_out< sc_logic > threshs0_m_threshold_4_ce0;
sc_out< sc_lv<16> > threshs0_m_threshold_4_d0;
sc_in< sc_lv<16> > threshs0_m_threshold_4_q0;
sc_out< sc_logic > threshs0_m_threshold_4_we0;
sc_out< sc_lv<5> > threshs0_m_threshold_4_address1;
sc_out< sc_logic > threshs0_m_threshold_4_ce1;
sc_out< sc_lv<16> > threshs0_m_threshold_4_d1;
sc_in< sc_lv<16> > threshs0_m_threshold_4_q1;
sc_out< sc_logic > threshs0_m_threshold_4_we1;
sc_out< sc_lv<5> > threshs0_m_threshold_3_address0;
sc_out< sc_logic > threshs0_m_threshold_3_ce0;
sc_out< sc_lv<16> > threshs0_m_threshold_3_d0;
sc_in< sc_lv<16> > threshs0_m_threshold_3_q0;
sc_out< sc_logic > threshs0_m_threshold_3_we0;
sc_out< sc_lv<5> > threshs0_m_threshold_3_address1;
sc_out< sc_logic > threshs0_m_threshold_3_ce1;
sc_out< sc_lv<16> > threshs0_m_threshold_3_d1;
sc_in< sc_lv<16> > threshs0_m_threshold_3_q1;
sc_out< sc_logic > threshs0_m_threshold_3_we1;
sc_out< sc_lv<5> > threshs0_m_threshold_2_address0;
sc_out< sc_logic > threshs0_m_threshold_2_ce0;
sc_out< sc_lv<16> > threshs0_m_threshold_2_d0;
sc_in< sc_lv<16> > threshs0_m_threshold_2_q0;
sc_out< sc_logic > threshs0_m_threshold_2_we0;
sc_out< sc_lv<5> > threshs0_m_threshold_2_address1;
sc_out< sc_logic > threshs0_m_threshold_2_ce1;
sc_out< sc_lv<16> > threshs0_m_threshold_2_d1;
sc_in< sc_lv<16> > threshs0_m_threshold_2_q1;
sc_out< sc_logic > threshs0_m_threshold_2_we1;
sc_out< sc_lv<5> > threshs0_m_threshold_1_address0;
sc_out< sc_logic > threshs0_m_threshold_1_ce0;
sc_out< sc_lv<16> > threshs0_m_threshold_1_d0;
sc_in< sc_lv<16> > threshs0_m_threshold_1_q0;
sc_out< sc_logic > threshs0_m_threshold_1_we0;
sc_out< sc_lv<5> > threshs0_m_threshold_1_address1;
sc_out< sc_logic > threshs0_m_threshold_1_ce1;
sc_out< sc_lv<16> > threshs0_m_threshold_1_d1;
sc_in< sc_lv<16> > threshs0_m_threshold_1_q1;
sc_out< sc_logic > threshs0_m_threshold_1_we1;
sc_out< sc_lv<5> > threshs0_m_threshold_address0;
sc_out< sc_logic > threshs0_m_threshold_ce0;
sc_out< sc_lv<16> > threshs0_m_threshold_d0;
sc_in< sc_lv<16> > threshs0_m_threshold_q0;
sc_out< sc_logic > threshs0_m_threshold_we0;
sc_out< sc_lv<5> > threshs0_m_threshold_address1;
sc_out< sc_logic > threshs0_m_threshold_ce1;
sc_out< sc_lv<16> > threshs0_m_threshold_d1;
sc_in< sc_lv<16> > threshs0_m_threshold_q1;
sc_out< sc_logic > threshs0_m_threshold_we1;
sc_out< sc_lv<5> > threshs0_m_threshold_29_address0;
sc_out< sc_logic > threshs0_m_threshold_29_ce0;
sc_out< sc_lv<16> > threshs0_m_threshold_29_d0;
sc_in< sc_lv<16> > threshs0_m_threshold_29_q0;
sc_out< sc_logic > threshs0_m_threshold_29_we0;
sc_out< sc_lv<5> > threshs0_m_threshold_29_address1;
sc_out< sc_logic > threshs0_m_threshold_29_ce1;
sc_out< sc_lv<16> > threshs0_m_threshold_29_d1;
sc_in< sc_lv<16> > threshs0_m_threshold_29_q1;
sc_out< sc_logic > threshs0_m_threshold_29_we1;
sc_out< sc_lv<5> > threshs0_m_threshold_28_address0;
sc_out< sc_logic > threshs0_m_threshold_28_ce0;
sc_out< sc_lv<16> > threshs0_m_threshold_28_d0;
sc_in< sc_lv<16> > threshs0_m_threshold_28_q0;
sc_out< sc_logic > threshs0_m_threshold_28_we0;
sc_out< sc_lv<5> > threshs0_m_threshold_28_address1;
sc_out< sc_logic > threshs0_m_threshold_28_ce1;
sc_out< sc_lv<16> > threshs0_m_threshold_28_d1;
sc_in< sc_lv<16> > threshs0_m_threshold_28_q1;
sc_out< sc_logic > threshs0_m_threshold_28_we1;
sc_out< sc_lv<5> > threshs0_m_threshold_27_address0;
sc_out< sc_logic > threshs0_m_threshold_27_ce0;
sc_out< sc_lv<16> > threshs0_m_threshold_27_d0;
sc_in< sc_lv<16> > threshs0_m_threshold_27_q0;
sc_out< sc_logic > threshs0_m_threshold_27_we0;
sc_out< sc_lv<5> > threshs0_m_threshold_27_address1;
sc_out< sc_logic > threshs0_m_threshold_27_ce1;
sc_out< sc_lv<16> > threshs0_m_threshold_27_d1;
sc_in< sc_lv<16> > threshs0_m_threshold_27_q1;
sc_out< sc_logic > threshs0_m_threshold_27_we1;
sc_out< sc_lv<5> > threshs0_m_threshold_26_address0;
sc_out< sc_logic > threshs0_m_threshold_26_ce0;
sc_out< sc_lv<16> > threshs0_m_threshold_26_d0;
sc_in< sc_lv<16> > threshs0_m_threshold_26_q0;
sc_out< sc_logic > threshs0_m_threshold_26_we0;
sc_out< sc_lv<5> > threshs0_m_threshold_26_address1;
sc_out< sc_logic > threshs0_m_threshold_26_ce1;
sc_out< sc_lv<16> > threshs0_m_threshold_26_d1;
sc_in< sc_lv<16> > threshs0_m_threshold_26_q1;
sc_out< sc_logic > threshs0_m_threshold_26_we1;
sc_out< sc_lv<5> > threshs0_m_threshold_25_address0;
sc_out< sc_logic > threshs0_m_threshold_25_ce0;
sc_out< sc_lv<16> > threshs0_m_threshold_25_d0;
sc_in< sc_lv<16> > threshs0_m_threshold_25_q0;
sc_out< sc_logic > threshs0_m_threshold_25_we0;
sc_out< sc_lv<5> > threshs0_m_threshold_25_address1;
sc_out< sc_logic > threshs0_m_threshold_25_ce1;
sc_out< sc_lv<16> > threshs0_m_threshold_25_d1;
sc_in< sc_lv<16> > threshs0_m_threshold_25_q1;
sc_out< sc_logic > threshs0_m_threshold_25_we1;
sc_out< sc_lv<5> > threshs0_m_threshold_24_address0;
sc_out< sc_logic > threshs0_m_threshold_24_ce0;
sc_out< sc_lv<16> > threshs0_m_threshold_24_d0;
sc_in< sc_lv<16> > threshs0_m_threshold_24_q0;
sc_out< sc_logic > threshs0_m_threshold_24_we0;
sc_out< sc_lv<5> > threshs0_m_threshold_24_address1;
sc_out< sc_logic > threshs0_m_threshold_24_ce1;
sc_out< sc_lv<16> > threshs0_m_threshold_24_d1;
sc_in< sc_lv<16> > threshs0_m_threshold_24_q1;
sc_out< sc_logic > threshs0_m_threshold_24_we1;
sc_out< sc_lv<5> > threshs0_m_threshold_23_address0;
sc_out< sc_logic > threshs0_m_threshold_23_ce0;
sc_out< sc_lv<16> > threshs0_m_threshold_23_d0;
sc_in< sc_lv<16> > threshs0_m_threshold_23_q0;
sc_out< sc_logic > threshs0_m_threshold_23_we0;
sc_out< sc_lv<5> > threshs0_m_threshold_23_address1;
sc_out< sc_logic > threshs0_m_threshold_23_ce1;
sc_out< sc_lv<16> > threshs0_m_threshold_23_d1;
sc_in< sc_lv<16> > threshs0_m_threshold_23_q1;
sc_out< sc_logic > threshs0_m_threshold_23_we1;
sc_out< sc_lv<5> > threshs0_m_threshold_22_address0;
sc_out< sc_logic > threshs0_m_threshold_22_ce0;
sc_out< sc_lv<16> > threshs0_m_threshold_22_d0;
sc_in< sc_lv<16> > threshs0_m_threshold_22_q0;
sc_out< sc_logic > threshs0_m_threshold_22_we0;
sc_out< sc_lv<5> > threshs0_m_threshold_22_address1;
sc_out< sc_logic > threshs0_m_threshold_22_ce1;
sc_out< sc_lv<16> > threshs0_m_threshold_22_d1;
sc_in< sc_lv<16> > threshs0_m_threshold_22_q1;
sc_out< sc_logic > threshs0_m_threshold_22_we1;
sc_out< sc_lv<5> > threshs0_m_threshold_21_address0;
sc_out< sc_logic > threshs0_m_threshold_21_ce0;
sc_out< sc_lv<16> > threshs0_m_threshold_21_d0;
sc_in< sc_lv<16> > threshs0_m_threshold_21_q0;
sc_out< sc_logic > threshs0_m_threshold_21_we0;
sc_out< sc_lv<5> > threshs0_m_threshold_21_address1;
sc_out< sc_logic > threshs0_m_threshold_21_ce1;
sc_out< sc_lv<16> > threshs0_m_threshold_21_d1;
sc_in< sc_lv<16> > threshs0_m_threshold_21_q1;
sc_out< sc_logic > threshs0_m_threshold_21_we1;
sc_out< sc_lv<5> > threshs0_m_threshold_20_address0;
sc_out< sc_logic > threshs0_m_threshold_20_ce0;
sc_out< sc_lv<16> > threshs0_m_threshold_20_d0;
sc_in< sc_lv<16> > threshs0_m_threshold_20_q0;
sc_out< sc_logic > threshs0_m_threshold_20_we0;
sc_out< sc_lv<5> > threshs0_m_threshold_20_address1;
sc_out< sc_logic > threshs0_m_threshold_20_ce1;
sc_out< sc_lv<16> > threshs0_m_threshold_20_d1;
sc_in< sc_lv<16> > threshs0_m_threshold_20_q1;
sc_out< sc_logic > threshs0_m_threshold_20_we1;
sc_out< sc_lv<5> > threshs0_m_threshold_18_address0;
sc_out< sc_logic > threshs0_m_threshold_18_ce0;
sc_out< sc_lv<16> > threshs0_m_threshold_18_d0;
sc_in< sc_lv<16> > threshs0_m_threshold_18_q0;
sc_out< sc_logic > threshs0_m_threshold_18_we0;
sc_out< sc_lv<5> > threshs0_m_threshold_18_address1;
sc_out< sc_logic > threshs0_m_threshold_18_ce1;
sc_out< sc_lv<16> > threshs0_m_threshold_18_d1;
sc_in< sc_lv<16> > threshs0_m_threshold_18_q1;
sc_out< sc_logic > threshs0_m_threshold_18_we1;
sc_out< sc_lv<5> > threshs0_m_threshold_17_address0;
sc_out< sc_logic > threshs0_m_threshold_17_ce0;
sc_out< sc_lv<16> > threshs0_m_threshold_17_d0;
sc_in< sc_lv<16> > threshs0_m_threshold_17_q0;
sc_out< sc_logic > threshs0_m_threshold_17_we0;
sc_out< sc_lv<5> > threshs0_m_threshold_17_address1;
sc_out< sc_logic > threshs0_m_threshold_17_ce1;
sc_out< sc_lv<16> > threshs0_m_threshold_17_d1;
sc_in< sc_lv<16> > threshs0_m_threshold_17_q1;
sc_out< sc_logic > threshs0_m_threshold_17_we1;
sc_out< sc_lv<5> > threshs0_m_threshold_16_address0;
sc_out< sc_logic > threshs0_m_threshold_16_ce0;
sc_out< sc_lv<16> > threshs0_m_threshold_16_d0;
sc_in< sc_lv<16> > threshs0_m_threshold_16_q0;
sc_out< sc_logic > threshs0_m_threshold_16_we0;
sc_out< sc_lv<5> > threshs0_m_threshold_16_address1;
sc_out< sc_logic > threshs0_m_threshold_16_ce1;
sc_out< sc_lv<16> > threshs0_m_threshold_16_d1;
sc_in< sc_lv<16> > threshs0_m_threshold_16_q1;
sc_out< sc_logic > threshs0_m_threshold_16_we1;
sc_out< sc_lv<5> > threshs0_m_threshold_15_address0;
sc_out< sc_logic > threshs0_m_threshold_15_ce0;
sc_out< sc_lv<16> > threshs0_m_threshold_15_d0;
sc_in< sc_lv<16> > threshs0_m_threshold_15_q0;
sc_out< sc_logic > threshs0_m_threshold_15_we0;
sc_out< sc_lv<5> > threshs0_m_threshold_15_address1;
sc_out< sc_logic > threshs0_m_threshold_15_ce1;
sc_out< sc_lv<16> > threshs0_m_threshold_15_d1;
sc_in< sc_lv<16> > threshs0_m_threshold_15_q1;
sc_out< sc_logic > threshs0_m_threshold_15_we1;
sc_out< sc_lv<5> > threshs0_m_threshold_14_address0;
sc_out< sc_logic > threshs0_m_threshold_14_ce0;
sc_out< sc_lv<16> > threshs0_m_threshold_14_d0;
sc_in< sc_lv<16> > threshs0_m_threshold_14_q0;
sc_out< sc_logic > threshs0_m_threshold_14_we0;
sc_out< sc_lv<5> > threshs0_m_threshold_14_address1;
sc_out< sc_logic > threshs0_m_threshold_14_ce1;
sc_out< sc_lv<16> > threshs0_m_threshold_14_d1;
sc_in< sc_lv<16> > threshs0_m_threshold_14_q1;
sc_out< sc_logic > threshs0_m_threshold_14_we1;
sc_out< sc_lv<5> > threshs0_m_threshold_13_address0;
sc_out< sc_logic > threshs0_m_threshold_13_ce0;
sc_out< sc_lv<16> > threshs0_m_threshold_13_d0;
sc_in< sc_lv<16> > threshs0_m_threshold_13_q0;
sc_out< sc_logic > threshs0_m_threshold_13_we0;
sc_out< sc_lv<5> > threshs0_m_threshold_13_address1;
sc_out< sc_logic > threshs0_m_threshold_13_ce1;
sc_out< sc_lv<16> > threshs0_m_threshold_13_d1;
sc_in< sc_lv<16> > threshs0_m_threshold_13_q1;
sc_out< sc_logic > threshs0_m_threshold_13_we1;
sc_out< sc_lv<5> > threshs0_m_threshold_12_address0;
sc_out< sc_logic > threshs0_m_threshold_12_ce0;
sc_out< sc_lv<16> > threshs0_m_threshold_12_d0;
sc_in< sc_lv<16> > threshs0_m_threshold_12_q0;
sc_out< sc_logic > threshs0_m_threshold_12_we0;
sc_out< sc_lv<5> > threshs0_m_threshold_12_address1;
sc_out< sc_logic > threshs0_m_threshold_12_ce1;
sc_out< sc_lv<16> > threshs0_m_threshold_12_d1;
sc_in< sc_lv<16> > threshs0_m_threshold_12_q1;
sc_out< sc_logic > threshs0_m_threshold_12_we1;
sc_out< sc_lv<5> > threshs0_m_threshold_11_address0;
sc_out< sc_logic > threshs0_m_threshold_11_ce0;
sc_out< sc_lv<16> > threshs0_m_threshold_11_d0;
sc_in< sc_lv<16> > threshs0_m_threshold_11_q0;
sc_out< sc_logic > threshs0_m_threshold_11_we0;
sc_out< sc_lv<5> > threshs0_m_threshold_11_address1;
sc_out< sc_logic > threshs0_m_threshold_11_ce1;
sc_out< sc_lv<16> > threshs0_m_threshold_11_d1;
sc_in< sc_lv<16> > threshs0_m_threshold_11_q1;
sc_out< sc_logic > threshs0_m_threshold_11_we1;
sc_out< sc_lv<5> > threshs0_m_threshold_10_address0;
sc_out< sc_logic > threshs0_m_threshold_10_ce0;
sc_out< sc_lv<16> > threshs0_m_threshold_10_d0;
sc_in< sc_lv<16> > threshs0_m_threshold_10_q0;
sc_out< sc_logic > threshs0_m_threshold_10_we0;
sc_out< sc_lv<5> > threshs0_m_threshold_10_address1;
sc_out< sc_logic > threshs0_m_threshold_10_ce1;
sc_out< sc_lv<16> > threshs0_m_threshold_10_d1;
sc_in< sc_lv<16> > threshs0_m_threshold_10_q1;
sc_out< sc_logic > threshs0_m_threshold_10_we1;
sc_out< sc_lv<5> > threshs0_m_threshold_9_address0;
sc_out< sc_logic > threshs0_m_threshold_9_ce0;
sc_out< sc_lv<16> > threshs0_m_threshold_9_d0;
sc_in< sc_lv<16> > threshs0_m_threshold_9_q0;
sc_out< sc_logic > threshs0_m_threshold_9_we0;
sc_out< sc_lv<5> > threshs0_m_threshold_9_address1;
sc_out< sc_logic > threshs0_m_threshold_9_ce1;
sc_out< sc_lv<16> > threshs0_m_threshold_9_d1;
sc_in< sc_lv<16> > threshs0_m_threshold_9_q1;
sc_out< sc_logic > threshs0_m_threshold_9_we1;
sc_out< sc_lv<5> > threshs0_m_threshold_7_address0;
sc_out< sc_logic > threshs0_m_threshold_7_ce0;
sc_out< sc_lv<16> > threshs0_m_threshold_7_d0;
sc_in< sc_lv<16> > threshs0_m_threshold_7_q0;
sc_out< sc_logic > threshs0_m_threshold_7_we0;
sc_out< sc_lv<5> > threshs0_m_threshold_7_address1;
sc_out< sc_logic > threshs0_m_threshold_7_ce1;
sc_out< sc_lv<16> > threshs0_m_threshold_7_d1;
sc_in< sc_lv<16> > threshs0_m_threshold_7_q1;
sc_out< sc_logic > threshs0_m_threshold_7_we1;
sc_out< sc_lv<5> > threshs0_m_threshold_6_address0;
sc_out< sc_logic > threshs0_m_threshold_6_ce0;
sc_out< sc_lv<16> > threshs0_m_threshold_6_d0;
sc_in< sc_lv<16> > threshs0_m_threshold_6_q0;
sc_out< sc_logic > threshs0_m_threshold_6_we0;
sc_out< sc_lv<5> > threshs0_m_threshold_6_address1;
sc_out< sc_logic > threshs0_m_threshold_6_ce1;
sc_out< sc_lv<16> > threshs0_m_threshold_6_d1;
sc_in< sc_lv<16> > threshs0_m_threshold_6_q1;
sc_out< sc_logic > threshs0_m_threshold_6_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_address0;
sc_out< sc_logic > weights1_m_weights_V_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_q0;
sc_out< sc_logic > weights1_m_weights_V_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_address1;
sc_out< sc_logic > weights1_m_weights_V_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_q1;
sc_out< sc_logic > weights1_m_weights_V_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_1_address0;
sc_out< sc_logic > weights1_m_weights_V_1_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_1_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_1_q0;
sc_out< sc_logic > weights1_m_weights_V_1_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_1_address1;
sc_out< sc_logic > weights1_m_weights_V_1_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_1_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_1_q1;
sc_out< sc_logic > weights1_m_weights_V_1_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_2_address0;
sc_out< sc_logic > weights1_m_weights_V_2_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_2_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_2_q0;
sc_out< sc_logic > weights1_m_weights_V_2_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_2_address1;
sc_out< sc_logic > weights1_m_weights_V_2_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_2_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_2_q1;
sc_out< sc_logic > weights1_m_weights_V_2_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_3_address0;
sc_out< sc_logic > weights1_m_weights_V_3_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_3_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_3_q0;
sc_out< sc_logic > weights1_m_weights_V_3_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_3_address1;
sc_out< sc_logic > weights1_m_weights_V_3_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_3_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_3_q1;
sc_out< sc_logic > weights1_m_weights_V_3_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_4_address0;
sc_out< sc_logic > weights1_m_weights_V_4_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_4_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_4_q0;
sc_out< sc_logic > weights1_m_weights_V_4_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_4_address1;
sc_out< sc_logic > weights1_m_weights_V_4_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_4_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_4_q1;
sc_out< sc_logic > weights1_m_weights_V_4_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_5_address0;
sc_out< sc_logic > weights1_m_weights_V_5_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_5_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_5_q0;
sc_out< sc_logic > weights1_m_weights_V_5_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_5_address1;
sc_out< sc_logic > weights1_m_weights_V_5_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_5_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_5_q1;
sc_out< sc_logic > weights1_m_weights_V_5_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_6_address0;
sc_out< sc_
|
logic > weights1_m_weights_V_6_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_6_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_6_q0;
sc_out< sc_logic > weights1_m_weights_V_6_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_6_address1;
sc_out< sc_logic > weights1_m_weights_V_6_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_6_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_6_q1;
sc_out< sc_logic > weights1_m_weights_V_6_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_7_address0;
sc_out< sc_logic > weights1_m_weights_V_7_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_7_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_7_q0;
sc_out< sc_logic > weights1_m_weights_V_7_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_7_address1;
sc_out< sc_logic > weights1_m_weights_V_7_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_7_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_7_q1;
sc_out< sc_logic > weights1_m_weights_V_7_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_8_address0;
sc_out< sc_logic > weights1_m_weights_V_8_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_8_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_8_q0;
sc_out< sc_logic > weights1_m_weights_V_8_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_8_address1;
sc_out< sc_logic > weights1_m_weights_V_8_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_8_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_8_q1;
sc_out< sc_logic > weights1_m_weights_V_8_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_9_address0;
sc_out< sc_logic > weights1_m_weights_V_9_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_9_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_9_q0;
sc_out< sc_logic > weights1_m_weights_V_9_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_9_address1;
sc_out< sc_logic > weights1_m_weights_V_9_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_9_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_9_q1;
sc_out< sc_logic > weights1_m_weights_V_9_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_10_address0;
sc_out< sc_logic > weights1_m_weights_V_10_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_10_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_10_q0;
sc_out< sc_logic > weights1_m_weights_V_10_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_10_address1;
sc_out< sc_logic > weights1_m_weights_V_10_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_10_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_10_q1;
sc_out< sc_logic > weights1_m_weights_V_10_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_11_address0;
sc_out< sc_logic > weights1_m_weights_V_11_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_11_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_11_q0;
sc_out< sc_logic > weights1_m_weights_V_11_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_11_address1;
sc_out< sc_logic > weights1_m_weights_V_11_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_11_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_11_q1;
sc_out< sc_logic > weights1_m_weights_V_11_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_12_address0;
sc_out< sc_logic > weights1_m_weights_V_12_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_12_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_12_q0;
sc_out< sc_logic > weights1_m_weights_V_12_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_12_address1;
sc_out< sc_logic > weights1_m_weights_V_12_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_12_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_12_q1;
sc_out< sc_logic > weights1_m_weights_V_12_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_13_address0;
sc_out< sc_logic > weights1_m_weights_V_13_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_13_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_13_q0;
sc_out< sc_logic > weights1_m_weights_V_13_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_13_address1;
sc_out< sc_logic > weights1_m_weights_V_13_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_13_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_13_q1;
sc_out< sc_logic > weights1_m_weights_V_13_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_14_address0;
sc_out< sc_logic > weights1_m_weights_V_14_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_14_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_14_q0;
sc_out< sc_logic > weights1_m_weights_V_14_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_14_address1;
sc_out< sc_logic > weights1_m_weights_V_14_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_14_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_14_q1;
sc_out< sc_logic > weights1_m_weights_V_14_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_15_address0;
sc_out< sc_logic > weights1_m_weights_V_15_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_15_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_15_q0;
sc_out< sc_logic > weights1_m_weights_V_15_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_15_address1;
sc_out< sc_logic > weights1_m_weights_V_15_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_15_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_15_q1;
sc_out< sc_logic > weights1_m_weights_V_15_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_16_address0;
sc_out< sc_logic > weights1_m_weights_V_16_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_16_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_16_q0;
sc_out< sc_logic > weights1_m_weights_V_16_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_16_address1;
sc_out< sc_logic > weights1_m_weights_V_16_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_16_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_16_q1;
sc_out< sc_logic > weights1_m_weights_V_16_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_17_address0;
sc_out< sc_logic > weights1_m_weights_V_17_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_17_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_17_q0;
sc_out< sc_logic > weights1_m_weights_V_17_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_17_address1;
sc_out< sc_logic > weights1_m_weights_V_17_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_17_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_17_q1;
sc_out< sc_logic > weights1_m_weights_V_17_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_18_address0;
sc_out< sc_logic > weights1_m_weights_V_18_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_18_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_18_q0;
sc_out< sc_logic > weights1_m_weights_V_18_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_18_address1;
sc_out< sc_logic > weights1_m_weights_V_18_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_18_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_18_q1;
sc_out< sc_logic > weights1_m_weights_V_18_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_19_address0;
sc_out< sc_logic > weights1_m_weights_V_19_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_19_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_19_q0;
sc_out< sc_logic > weights1_m_weights_V_19_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_19_address1;
sc_out< sc_logic > weights1_m_weights_V_19_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_19_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_19_q1;
sc_out< sc_logic > weights1_m_weights_V_19_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_20_address0;
sc_out< sc_logic > weights1_m_weights_V_20_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_20_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_20_q0;
sc_out< sc_logic > weights1_m_weights_V_20_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_20_address1;
sc_out< sc_logic > weights1_m_weights_V_20_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_20_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_20_q1;
sc_out< sc_logic > weights1_m_weights_V_20_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_21_address0;
sc_out< sc_logic > weights1_m_weights_V_21_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_21_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_21_q0;
sc_out< sc_logic > weights1_m_weights_V_21_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_21_address1;
sc_out< sc_logic > weights1_m_weights_V_21_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_21_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_21_q1;
sc_out< sc_logic > weights1_m_weights_V_21_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_22_address0;
sc_out< sc_logic > weights1_m_weights_V_22_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_22_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_22_q0;
sc_out< sc_logic > weights1_m_weights_V_22_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_22_address1;
sc_out< sc_logic > weights1_m_weights_V_22_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_22_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_22_q1;
sc_out< sc_logic > weights1_m_weights_V_22_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_23_address0;
sc_out< sc_logic > weights1_m_weights_V_23_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_23_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_23_q0;
sc_out< sc_logic > weights1_m_weights_V_23_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_23_address1;
sc_out< sc_logic > weights1_m_weights_V_23_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_23_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_23_q1;
sc_out< sc_logic > weights1_m_weights_V_23_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_24_address0;
sc_out< sc_logic > weights1_m_weights_V_24_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_24_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_24_q0;
sc_out< sc_logic > weights1_m_weights_V_24_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_24_address1;
sc_out< sc_logic > weights1_m_weights_V_24_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_24_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_24_q1;
sc_out< sc_logic > weights1_m_weights_V_24_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_25_address0;
sc_out< sc_logic > weights1_m_weights_V_25_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_25_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_25_q0;
sc_out< sc_logic > weights1_m_weights_V_25_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_25_address1;
sc_out< sc_logic > weights1_m_weights_V_25_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_25_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_25_q1;
sc_out< sc_logic > weights1_m_weights_V_25_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_26_address0;
sc_out< sc_logic > weights1_m_weights_V_26_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_26_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_26_q0;
sc_out< sc_logic > weights1_m_weights_V_26_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_26_address1;
sc_out< sc_logic > weights1_m_weights_V_26_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_26_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_26_q1;
sc_out< sc_logic > weights1_m_weights_V_26_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_27_address0;
sc_out< sc_logic > weights1_m_weights_V_27_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_27_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_27_q0;
sc_out< sc_logic > weights1_m_weights_V_27_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_27_address1;
sc_out< sc_logic > weights1_m_weights_V_27_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_27_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_27_q1;
sc_out< sc_logic > weights1_m_weights_V_27_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_28_address0;
sc_out< sc_logic > weights1_m_weights_V_28_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_28_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_28_q0;
sc_out< sc_logic > weights1_m_weights_V_28_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_28_address1;
sc_out< sc_logic > weights1_m_weights_V_28_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_28_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_28_q1;
sc_out< sc_logic > weights1_m_weights_V_28_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_29_address0;
sc_out< sc_logic > weights1_m_weights_V_29_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_29_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_29_q0;
sc_out< sc_logic > weights1_m_weights_V_29_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_29_address1;
sc_out< sc_logic > weights1_m_weights_V_29_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_29_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_29_q1;
sc_out< sc_logic > weights1_m_weights_V_29_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_30_address0;
sc_out< sc_logic > weights1_m_weights_V_30_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_30_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_30_q0;
sc_out< sc_logic > weights1_m_weights_V_30_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_30_address1;
sc_out< sc_logic > weights1_m_weights_V_30_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_30_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_30_q1;
sc_out< sc_logic > weights1_m_weights_V_30_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_31_address0;
sc_out< sc_logic > weights1_m_weights_V_31_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_31_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_31_q0;
sc_out< sc_logic > weights1_m_weights_V_31_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_31_address1;
sc_out< sc_logic > weights1_m_weights_V_31_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_31_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_31_q1;
sc_out< sc_logic > weights1_m_weights_V_31_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_32_address0;
sc_out< sc_logic > weights1_m_weights_V_32_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_32_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_32_q0;
sc_out< sc_logic > weights1_m_weights_V_32_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_32_address1;
sc_out< sc_logic > weights1_m_weights_V_32_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_32_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_32_q1;
sc_out< sc_logic > weights1_m_weights_V_32_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_33_address0;
sc_out< sc_logic > weights1_m_weights_V_33_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_33_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_33_q0;
sc_out< sc_logic > weights1_m_weights_V_33_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_33_address1;
sc_out< sc_logic > weights1_m_weights_V_33_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_33_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_33_q1;
sc_out< sc_logic > weights1_m_weights_V_33_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_34_address0;
sc_out< sc_logic > weights1_m_weights_V_34_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_34_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_34_q0;
sc_out< sc_logic > weights1_m_weights_V_34_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_34_address1;
sc_out< sc_logic > weights1_m_weights_V_34_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_34_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_34_q1;
sc_out< sc_logic > weights1_m_weights_V_34_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_35_address0;
sc_out< sc_logic > weights1_m_weights_V_35_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_35_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_35_q0;
sc_out< sc_logic > weights1_m_weights_V_35_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_35_address1;
sc_out< sc_logic > weights1_m_weights_V_35_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_35_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_35_q1;
sc_out< sc_logic > weights1_m_weights_V_35_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_36_address0;
sc_out< sc_logic > weights1_m_weights_V_36_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_36_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_36_q0;
sc_out< sc_logic > weights1_m_weights_V_36_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_36_address1;
sc_out< sc_logic > weights1_m_weights_V_36_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_36_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_36_q1;
sc_out< sc_logic > weights1_m_weights_V_36_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_37_address0;
sc_out< sc_logic > weights1_m_weights_V_37_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_37_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_37_q0;
sc_out< sc_logic > weights1_m_weights_V_37_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_37_address1;
sc_out< sc_logic > weights1_m_weights_V_37_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_37_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_37_q1;
sc_out< sc_logic > weights1_m_weights_V_37_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_38_address0;
sc_out< sc_logic > weights1_m_weights_V_38_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_38_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_38_q0;
sc_out< sc_logic > weights1_m_weights_V_38_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_38_address1;
sc_out< sc_logic > weights1_m_weights_V_38_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_38_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_38_q1;
sc_out< sc_logic > weights1_m_weights_V_38_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_39_address0;
sc_out< sc_logic > weights1_m_weights_V_39_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_39_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_39_q0;
sc_out< sc_logic > weights1_m_weights_V_39_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_39_address1;
sc_out< sc_logic > weights1_m_weights_V_39_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_39_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_39_q1;
sc_out< sc_logic > weights1_m_weights_V_39_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_40_address0;
sc_out< sc_logic > weights1_m_weights_V_40_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_40_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_40_q0;
sc_out< sc_logic > weights1_m_weights_V_40_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_40_address1;
sc_out< sc_logic > weights1_m_weights_V_40_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_40_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_40_q1;
sc_out< sc_logic > weights1_m_weights_V_40_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_41_address0;
sc_out< sc_logic > weights1_m_weights_V_41_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_41_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_41_q0;
sc_out< sc_logic > weights1_m_weights_V_41_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_41_address1;
sc_out< sc_logic > weights1_m_weights_V_41_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_41_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_41_q1;
sc_out< sc_logic > weights1_m_weights_V_41_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_42_address0;
sc_out< sc_logic > weights1_m_weights_V_42_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_42_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_42_q0;
sc_out< sc_logic > weights1_m_weights_V_42_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_42_address1;
sc_out< sc_logic > weights1_m_weights_V_42_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_42_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_42_q1;
sc_out< sc_logic > weights1_m_weights_V_42_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_43_address0;
sc_out< sc_logic > weights1_m_weights_V_43_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_43_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_43_q0;
sc_out< sc_logic > weights1_m_weights_V_43_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_43_address1;
sc_out< sc_logic > weights1_m_weights_V_43_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_43_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_43_q1;
sc_out< sc_logic > weights1_m_weights_V_43_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_44_
|
address0;
sc_out< sc_logic > weights1_m_weights_V_44_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_44_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_44_q0;
sc_out< sc_logic > weights1_m_weights_V_44_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_44_address1;
sc_out< sc_logic > weights1_m_weights_V_44_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_44_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_44_q1;
sc_out< sc_logic > weights1_m_weights_V_44_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_45_address0;
sc_out< sc_logic > weights1_m_weights_V_45_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_45_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_45_q0;
sc_out< sc_logic > weights1_m_weights_V_45_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_45_address1;
sc_out< sc_logic > weights1_m_weights_V_45_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_45_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_45_q1;
sc_out< sc_logic > weights1_m_weights_V_45_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_46_address0;
sc_out< sc_logic > weights1_m_weights_V_46_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_46_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_46_q0;
sc_out< sc_logic > weights1_m_weights_V_46_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_46_address1;
sc_out< sc_logic > weights1_m_weights_V_46_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_46_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_46_q1;
sc_out< sc_logic > weights1_m_weights_V_46_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_47_address0;
sc_out< sc_logic > weights1_m_weights_V_47_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_47_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_47_q0;
sc_out< sc_logic > weights1_m_weights_V_47_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_47_address1;
sc_out< sc_logic > weights1_m_weights_V_47_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_47_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_47_q1;
sc_out< sc_logic > weights1_m_weights_V_47_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_48_address0;
sc_out< sc_logic > weights1_m_weights_V_48_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_48_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_48_q0;
sc_out< sc_logic > weights1_m_weights_V_48_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_48_address1;
sc_out< sc_logic > weights1_m_weights_V_48_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_48_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_48_q1;
sc_out< sc_logic > weights1_m_weights_V_48_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_49_address0;
sc_out< sc_logic > weights1_m_weights_V_49_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_49_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_49_q0;
sc_out< sc_logic > weights1_m_weights_V_49_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_49_address1;
sc_out< sc_logic > weights1_m_weights_V_49_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_49_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_49_q1;
sc_out< sc_logic > weights1_m_weights_V_49_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_50_address0;
sc_out< sc_logic > weights1_m_weights_V_50_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_50_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_50_q0;
sc_out< sc_logic > weights1_m_weights_V_50_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_50_address1;
sc_out< sc_logic > weights1_m_weights_V_50_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_50_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_50_q1;
sc_out< sc_logic > weights1_m_weights_V_50_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_51_address0;
sc_out< sc_logic > weights1_m_weights_V_51_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_51_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_51_q0;
sc_out< sc_logic > weights1_m_weights_V_51_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_51_address1;
sc_out< sc_logic > weights1_m_weights_V_51_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_51_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_51_q1;
sc_out< sc_logic > weights1_m_weights_V_51_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_52_address0;
sc_out< sc_logic > weights1_m_weights_V_52_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_52_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_52_q0;
sc_out< sc_logic > weights1_m_weights_V_52_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_52_address1;
sc_out< sc_logic > weights1_m_weights_V_52_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_52_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_52_q1;
sc_out< sc_logic > weights1_m_weights_V_52_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_53_address0;
sc_out< sc_logic > weights1_m_weights_V_53_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_53_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_53_q0;
sc_out< sc_logic > weights1_m_weights_V_53_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_53_address1;
sc_out< sc_logic > weights1_m_weights_V_53_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_53_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_53_q1;
sc_out< sc_logic > weights1_m_weights_V_53_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_54_address0;
sc_out< sc_logic > weights1_m_weights_V_54_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_54_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_54_q0;
sc_out< sc_logic > weights1_m_weights_V_54_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_54_address1;
sc_out< sc_logic > weights1_m_weights_V_54_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_54_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_54_q1;
sc_out< sc_logic > weights1_m_weights_V_54_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_55_address0;
sc_out< sc_logic > weights1_m_weights_V_55_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_55_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_55_q0;
sc_out< sc_logic > weights1_m_weights_V_55_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_55_address1;
sc_out< sc_logic > weights1_m_weights_V_55_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_55_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_55_q1;
sc_out< sc_logic > weights1_m_weights_V_55_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_56_address0;
sc_out< sc_logic > weights1_m_weights_V_56_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_56_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_56_q0;
sc_out< sc_logic > weights1_m_weights_V_56_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_56_address1;
sc_out< sc_logic > weights1_m_weights_V_56_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_56_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_56_q1;
sc_out< sc_logic > weights1_m_weights_V_56_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_57_address0;
sc_out< sc_logic > weights1_m_weights_V_57_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_57_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_57_q0;
sc_out< sc_logic > weights1_m_weights_V_57_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_57_address1;
sc_out< sc_logic > weights1_m_weights_V_57_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_57_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_57_q1;
sc_out< sc_logic > weights1_m_weights_V_57_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_58_address0;
sc_out< sc_logic > weights1_m_weights_V_58_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_58_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_58_q0;
sc_out< sc_logic > weights1_m_weights_V_58_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_58_address1;
sc_out< sc_logic > weights1_m_weights_V_58_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_58_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_58_q1;
sc_out< sc_logic > weights1_m_weights_V_58_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_59_address0;
sc_out< sc_logic > weights1_m_weights_V_59_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_59_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_59_q0;
sc_out< sc_logic > weights1_m_weights_V_59_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_59_address1;
sc_out< sc_logic > weights1_m_weights_V_59_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_59_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_59_q1;
sc_out< sc_logic > weights1_m_weights_V_59_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_60_address0;
sc_out< sc_logic > weights1_m_weights_V_60_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_60_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_60_q0;
sc_out< sc_logic > weights1_m_weights_V_60_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_60_address1;
sc_out< sc_logic > weights1_m_weights_V_60_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_60_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_60_q1;
sc_out< sc_logic > weights1_m_weights_V_60_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_61_address0;
sc_out< sc_logic > weights1_m_weights_V_61_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_61_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_61_q0;
sc_out< sc_logic > weights1_m_weights_V_61_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_61_address1;
sc_out< sc_logic > weights1_m_weights_V_61_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_61_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_61_q1;
sc_out< sc_logic > weights1_m_weights_V_61_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_62_address0;
sc_out< sc_logic > weights1_m_weights_V_62_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_62_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_62_q0;
sc_out< sc_logic > weights1_m_weights_V_62_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_62_address1;
sc_out< sc_logic > weights1_m_weights_V_62_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_62_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_62_q1;
sc_out< sc_logic > weights1_m_weights_V_62_we1;
sc_out< sc_lv<9> > weights1_m_weights_V_63_address0;
sc_out< sc_logic > weights1_m_weights_V_63_ce0;
sc_out< sc_lv<32> > weights1_m_weights_V_63_d0;
sc_in< sc_lv<32> > weights1_m_weights_V_63_q0;
sc_out< sc_logic > weights1_m_weights_V_63_we0;
sc_out< sc_lv<9> > weights1_m_weights_V_63_address1;
sc_out< sc_logic > weights1_m_weights_V_63_ce1;
sc_out< sc_lv<32> > weights1_m_weights_V_63_d1;
sc_in< sc_lv<32> > weights1_m_weights_V_63_q1;
sc_out< sc_logic > weights1_m_weights_V_63_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_63_address0;
sc_out< sc_logic > threshs1_m_threshold_63_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_63_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_63_q0;
sc_out< sc_logic > threshs1_m_threshold_63_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_63_address1;
sc_out< sc_logic > threshs1_m_threshold_63_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_63_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_63_q1;
sc_out< sc_logic > threshs1_m_threshold_63_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_62_address0;
sc_out< sc_logic > threshs1_m_threshold_62_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_62_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_62_q0;
sc_out< sc_logic > threshs1_m_threshold_62_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_62_address1;
sc_out< sc_logic > threshs1_m_threshold_62_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_62_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_62_q1;
sc_out< sc_logic > threshs1_m_threshold_62_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_51_address0;
sc_out< sc_logic > threshs1_m_threshold_51_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_51_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_51_q0;
sc_out< sc_logic > threshs1_m_threshold_51_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_51_address1;
sc_out< sc_logic > threshs1_m_threshold_51_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_51_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_51_q1;
sc_out< sc_logic > threshs1_m_threshold_51_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_40_address0;
sc_out< sc_logic > threshs1_m_threshold_40_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_40_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_40_q0;
sc_out< sc_logic > threshs1_m_threshold_40_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_40_address1;
sc_out< sc_logic > threshs1_m_threshold_40_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_40_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_40_q1;
sc_out< sc_logic > threshs1_m_threshold_40_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_29_address0;
sc_out< sc_logic > threshs1_m_threshold_29_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_29_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_29_q0;
sc_out< sc_logic > threshs1_m_threshold_29_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_29_address1;
sc_out< sc_logic > threshs1_m_threshold_29_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_29_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_29_q1;
sc_out< sc_logic > threshs1_m_threshold_29_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_18_address0;
sc_out< sc_logic > threshs1_m_threshold_18_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_18_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_18_q0;
sc_out< sc_logic > threshs1_m_threshold_18_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_18_address1;
sc_out< sc_logic > threshs1_m_threshold_18_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_18_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_18_q1;
sc_out< sc_logic > threshs1_m_threshold_18_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_7_address0;
sc_out< sc_logic > threshs1_m_threshold_7_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_7_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_7_q0;
sc_out< sc_logic > threshs1_m_threshold_7_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_7_address1;
sc_out< sc_logic > threshs1_m_threshold_7_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_7_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_7_q1;
sc_out< sc_logic > threshs1_m_threshold_7_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_2_address0;
sc_out< sc_logic > threshs1_m_threshold_2_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_2_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_2_q0;
sc_out< sc_logic > threshs1_m_threshold_2_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_2_address1;
sc_out< sc_logic > threshs1_m_threshold_2_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_2_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_2_q1;
sc_out< sc_logic > threshs1_m_threshold_2_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_1_address0;
sc_out< sc_logic > threshs1_m_threshold_1_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_1_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_1_q0;
sc_out< sc_logic > threshs1_m_threshold_1_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_1_address1;
sc_out< sc_logic > threshs1_m_threshold_1_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_1_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_1_q1;
sc_out< sc_logic > threshs1_m_threshold_1_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_address0;
sc_out< sc_logic > threshs1_m_threshold_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_q0;
sc_out< sc_logic > threshs1_m_threshold_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_address1;
sc_out< sc_logic > threshs1_m_threshold_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_q1;
sc_out< sc_logic > threshs1_m_threshold_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_61_address0;
sc_out< sc_logic > threshs1_m_threshold_61_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_61_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_61_q0;
sc_out< sc_logic > threshs1_m_threshold_61_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_61_address1;
sc_out< sc_logic > threshs1_m_threshold_61_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_61_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_61_q1;
sc_out< sc_logic > threshs1_m_threshold_61_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_60_address0;
sc_out< sc_logic > threshs1_m_threshold_60_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_60_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_60_q0;
sc_out< sc_logic > threshs1_m_threshold_60_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_60_address1;
sc_out< sc_logic > threshs1_m_threshold_60_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_60_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_60_q1;
sc_out< sc_logic > threshs1_m_threshold_60_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_59_address0;
sc_out< sc_logic > threshs1_m_threshold_59_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_59_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_59_q0;
sc_out< sc_logic > threshs1_m_threshold_59_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_59_address1;
sc_out< sc_logic > threshs1_m_threshold_59_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_59_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_59_q1;
sc_out< sc_logic > threshs1_m_threshold_59_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_58_address0;
sc_out< sc_logic > threshs1_m_threshold_58_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_58_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_58_q0;
sc_out< sc_logic > threshs1_m_threshold_58_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_58_address1;
sc_out< sc_logic > threshs1_m_threshold_58_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_58_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_58_q1;
sc_out< sc_logic > threshs1_m_threshold_58_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_57_address0;
sc_out< sc_logic > threshs1_m_threshold_57_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_57_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_57_q0;
sc_out< sc_logic > threshs1_m_threshold_57_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_57_address1;
sc_out< sc_logic > threshs1_m_threshold_57_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_57_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_57_q1;
sc_out< sc_logic > threshs1_m_threshold_57_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_56_address0;
sc_out< sc_logic > threshs1_m_threshold_56_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_56_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_56_q0;
sc_out< sc_logic > threshs1_m_threshold_56_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_56_address1;
sc_out< sc_logic > threshs1_m_threshold_56_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_56_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_56_q1;
sc_out< sc_logic > threshs1_m_threshold_56_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_55_address0;
sc_out< sc_logic > threshs1_m_threshold_55_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_55_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_55_q0;
sc_out< sc_logic > threshs1_m_threshold_55_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_55_address1;
sc_out< sc_logic > threshs1_m_threshold_55_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_55_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_55_q1;
sc_out< sc_logic > threshs1_m_threshold_55_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_54_address0;
sc_out< sc_logic > threshs1_m_threshold_54_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_54_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_54_q0;
sc_out< sc_logic > threshs1_m_threshold_54_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_54_address1;
sc_out< sc_logic > threshs1_m_threshold_54_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_54_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_54_q1;
sc_out< sc_logic > threshs1_m_threshold_54_we1;
sc_out< sc_lv<4> > threshs1_m_threshold
|
_53_address0;
sc_out< sc_logic > threshs1_m_threshold_53_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_53_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_53_q0;
sc_out< sc_logic > threshs1_m_threshold_53_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_53_address1;
sc_out< sc_logic > threshs1_m_threshold_53_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_53_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_53_q1;
sc_out< sc_logic > threshs1_m_threshold_53_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_52_address0;
sc_out< sc_logic > threshs1_m_threshold_52_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_52_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_52_q0;
sc_out< sc_logic > threshs1_m_threshold_52_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_52_address1;
sc_out< sc_logic > threshs1_m_threshold_52_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_52_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_52_q1;
sc_out< sc_logic > threshs1_m_threshold_52_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_50_address0;
sc_out< sc_logic > threshs1_m_threshold_50_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_50_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_50_q0;
sc_out< sc_logic > threshs1_m_threshold_50_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_50_address1;
sc_out< sc_logic > threshs1_m_threshold_50_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_50_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_50_q1;
sc_out< sc_logic > threshs1_m_threshold_50_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_49_address0;
sc_out< sc_logic > threshs1_m_threshold_49_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_49_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_49_q0;
sc_out< sc_logic > threshs1_m_threshold_49_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_49_address1;
sc_out< sc_logic > threshs1_m_threshold_49_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_49_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_49_q1;
sc_out< sc_logic > threshs1_m_threshold_49_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_48_address0;
sc_out< sc_logic > threshs1_m_threshold_48_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_48_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_48_q0;
sc_out< sc_logic > threshs1_m_threshold_48_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_48_address1;
sc_out< sc_logic > threshs1_m_threshold_48_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_48_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_48_q1;
sc_out< sc_logic > threshs1_m_threshold_48_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_47_address0;
sc_out< sc_logic > threshs1_m_threshold_47_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_47_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_47_q0;
sc_out< sc_logic > threshs1_m_threshold_47_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_47_address1;
sc_out< sc_logic > threshs1_m_threshold_47_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_47_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_47_q1;
sc_out< sc_logic > threshs1_m_threshold_47_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_46_address0;
sc_out< sc_logic > threshs1_m_threshold_46_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_46_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_46_q0;
sc_out< sc_logic > threshs1_m_threshold_46_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_46_address1;
sc_out< sc_logic > threshs1_m_threshold_46_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_46_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_46_q1;
sc_out< sc_logic > threshs1_m_threshold_46_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_45_address0;
sc_out< sc_logic > threshs1_m_threshold_45_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_45_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_45_q0;
sc_out< sc_logic > threshs1_m_threshold_45_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_45_address1;
sc_out< sc_logic > threshs1_m_threshold_45_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_45_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_45_q1;
sc_out< sc_logic > threshs1_m_threshold_45_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_44_address0;
sc_out< sc_logic > threshs1_m_threshold_44_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_44_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_44_q0;
sc_out< sc_logic > threshs1_m_threshold_44_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_44_address1;
sc_out< sc_logic > threshs1_m_threshold_44_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_44_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_44_q1;
sc_out< sc_logic > threshs1_m_threshold_44_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_43_address0;
sc_out< sc_logic > threshs1_m_threshold_43_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_43_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_43_q0;
sc_out< sc_logic > threshs1_m_threshold_43_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_43_address1;
sc_out< sc_logic > threshs1_m_threshold_43_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_43_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_43_q1;
sc_out< sc_logic > threshs1_m_threshold_43_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_42_address0;
sc_out< sc_logic > threshs1_m_threshold_42_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_42_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_42_q0;
sc_out< sc_logic > threshs1_m_threshold_42_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_42_address1;
sc_out< sc_logic > threshs1_m_threshold_42_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_42_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_42_q1;
sc_out< sc_logic > threshs1_m_threshold_42_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_41_address0;
sc_out< sc_logic > threshs1_m_threshold_41_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_41_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_41_q0;
sc_out< sc_logic > threshs1_m_threshold_41_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_41_address1;
sc_out< sc_logic > threshs1_m_threshold_41_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_41_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_41_q1;
sc_out< sc_logic > threshs1_m_threshold_41_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_39_address0;
sc_out< sc_logic > threshs1_m_threshold_39_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_39_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_39_q0;
sc_out< sc_logic > threshs1_m_threshold_39_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_39_address1;
sc_out< sc_logic > threshs1_m_threshold_39_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_39_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_39_q1;
sc_out< sc_logic > threshs1_m_threshold_39_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_38_address0;
sc_out< sc_logic > threshs1_m_threshold_38_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_38_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_38_q0;
sc_out< sc_logic > threshs1_m_threshold_38_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_38_address1;
sc_out< sc_logic > threshs1_m_threshold_38_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_38_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_38_q1;
sc_out< sc_logic > threshs1_m_threshold_38_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_37_address0;
sc_out< sc_logic > threshs1_m_threshold_37_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_37_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_37_q0;
sc_out< sc_logic > threshs1_m_threshold_37_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_37_address1;
sc_out< sc_logic > threshs1_m_threshold_37_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_37_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_37_q1;
sc_out< sc_logic > threshs1_m_threshold_37_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_36_address0;
sc_out< sc_logic > threshs1_m_threshold_36_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_36_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_36_q0;
sc_out< sc_logic > threshs1_m_threshold_36_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_36_address1;
sc_out< sc_logic > threshs1_m_threshold_36_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_36_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_36_q1;
sc_out< sc_logic > threshs1_m_threshold_36_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_35_address0;
sc_out< sc_logic > threshs1_m_threshold_35_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_35_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_35_q0;
sc_out< sc_logic > threshs1_m_threshold_35_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_35_address1;
sc_out< sc_logic > threshs1_m_threshold_35_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_35_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_35_q1;
sc_out< sc_logic > threshs1_m_threshold_35_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_34_address0;
sc_out< sc_logic > threshs1_m_threshold_34_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_34_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_34_q0;
sc_out< sc_logic > threshs1_m_threshold_34_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_34_address1;
sc_out< sc_logic > threshs1_m_threshold_34_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_34_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_34_q1;
sc_out< sc_logic > threshs1_m_threshold_34_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_33_address0;
sc_out< sc_logic > threshs1_m_threshold_33_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_33_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_33_q0;
sc_out< sc_logic > threshs1_m_threshold_33_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_33_address1;
sc_out< sc_logic > threshs1_m_threshold_33_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_33_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_33_q1;
sc_out< sc_logic > threshs1_m_threshold_33_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_32_address0;
sc_out< sc_logic > threshs1_m_threshold_32_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_32_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_32_q0;
sc_out< sc_logic > threshs1_m_threshold_32_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_32_address1;
sc_out< sc_logic > threshs1_m_threshold_32_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_32_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_32_q1;
sc_out< sc_logic > threshs1_m_threshold_32_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_31_address0;
sc_out< sc_logic > threshs1_m_threshold_31_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_31_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_31_q0;
sc_out< sc_logic > threshs1_m_threshold_31_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_31_address1;
sc_out< sc_logic > threshs1_m_threshold_31_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_31_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_31_q1;
sc_out< sc_logic > threshs1_m_threshold_31_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_30_address0;
sc_out< sc_logic > threshs1_m_threshold_30_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_30_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_30_q0;
sc_out< sc_logic > threshs1_m_threshold_30_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_30_address1;
sc_out< sc_logic > threshs1_m_threshold_30_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_30_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_30_q1;
sc_out< sc_logic > threshs1_m_threshold_30_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_28_address0;
sc_out< sc_logic > threshs1_m_threshold_28_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_28_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_28_q0;
sc_out< sc_logic > threshs1_m_threshold_28_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_28_address1;
sc_out< sc_logic > threshs1_m_threshold_28_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_28_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_28_q1;
sc_out< sc_logic > threshs1_m_threshold_28_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_27_address0;
sc_out< sc_logic > threshs1_m_threshold_27_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_27_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_27_q0;
sc_out< sc_logic > threshs1_m_threshold_27_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_27_address1;
sc_out< sc_logic > threshs1_m_threshold_27_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_27_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_27_q1;
sc_out< sc_logic > threshs1_m_threshold_27_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_26_address0;
sc_out< sc_logic > threshs1_m_threshold_26_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_26_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_26_q0;
sc_out< sc_logic > threshs1_m_threshold_26_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_26_address1;
sc_out< sc_logic > threshs1_m_threshold_26_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_26_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_26_q1;
sc_out< sc_logic > threshs1_m_threshold_26_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_25_address0;
sc_out< sc_logic > threshs1_m_threshold_25_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_25_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_25_q0;
sc_out< sc_logic > threshs1_m_threshold_25_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_25_address1;
sc_out< sc_logic > threshs1_m_threshold_25_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_25_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_25_q1;
sc_out< sc_logic > threshs1_m_threshold_25_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_24_address0;
sc_out< sc_logic > threshs1_m_threshold_24_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_24_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_24_q0;
sc_out< sc_logic > threshs1_m_threshold_24_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_24_address1;
sc_out< sc_logic > threshs1_m_threshold_24_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_24_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_24_q1;
sc_out< sc_logic > threshs1_m_threshold_24_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_23_address0;
sc_out< sc_logic > threshs1_m_threshold_23_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_23_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_23_q0;
sc_out< sc_logic > threshs1_m_threshold_23_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_23_address1;
sc_out< sc_logic > threshs1_m_threshold_23_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_23_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_23_q1;
sc_out< sc_logic > threshs1_m_threshold_23_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_22_address0;
sc_out< sc_logic > threshs1_m_threshold_22_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_22_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_22_q0;
sc_out< sc_logic > threshs1_m_threshold_22_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_22_address1;
sc_out< sc_logic > threshs1_m_threshold_22_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_22_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_22_q1;
sc_out< sc_logic > threshs1_m_threshold_22_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_21_address0;
sc_out< sc_logic > threshs1_m_threshold_21_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_21_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_21_q0;
sc_out< sc_logic > threshs1_m_threshold_21_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_21_address1;
sc_out< sc_logic > threshs1_m_threshold_21_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_21_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_21_q1;
sc_out< sc_logic > threshs1_m_threshold_21_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_20_address0;
sc_out< sc_logic > threshs1_m_threshold_20_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_20_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_20_q0;
sc_out< sc_logic > threshs1_m_threshold_20_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_20_address1;
sc_out< sc_logic > threshs1_m_threshold_20_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_20_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_20_q1;
sc_out< sc_logic > threshs1_m_threshold_20_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_19_address0;
sc_out< sc_logic > threshs1_m_threshold_19_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_19_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_19_q0;
sc_out< sc_logic > threshs1_m_threshold_19_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_19_address1;
sc_out< sc_logic > threshs1_m_threshold_19_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_19_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_19_q1;
sc_out< sc_logic > threshs1_m_threshold_19_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_17_address0;
sc_out< sc_logic > threshs1_m_threshold_17_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_17_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_17_q0;
sc_out< sc_logic > threshs1_m_threshold_17_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_17_address1;
sc_out< sc_logic > threshs1_m_threshold_17_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_17_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_17_q1;
sc_out< sc_logic > threshs1_m_threshold_17_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_16_address0;
sc_out< sc_logic > threshs1_m_threshold_16_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_16_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_16_q0;
sc_out< sc_logic > threshs1_m_threshold_16_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_16_address1;
sc_out< sc_logic > threshs1_m_threshold_16_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_16_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_16_q1;
sc_out< sc_logic > threshs1_m_threshold_16_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_15_address0;
sc_out< sc_logic > threshs1_m_threshold_15_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_15_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_15_q0;
sc_out< sc_logic > threshs1_m_threshold_15_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_15_address1;
sc_out< sc_logic > threshs1_m_threshold_15_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_15_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_15_q1;
sc_out< sc_logic > threshs1_m_threshold_15_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_14_address0;
sc_out< sc_logic > threshs1_m_threshold_14_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_14_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_14_q0;
sc_out< sc_logic > threshs1_m_threshold_14_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_14_address1;
sc_out< sc_logic > threshs1_m_threshold_14_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_14_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_14_q1;
sc_out< sc_logic > threshs1_m_threshold_14_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_13_address0;
sc_out< sc_logic > threshs1_m_threshold_13_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_13_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_13_q0;
sc_out< sc_logic > threshs1_m_threshold_13_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_13_address1;
sc_out< sc_logic > threshs1_m_threshold_13_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_13_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_13_q1;
sc_out< sc_logic > threshs1_m_threshold_13_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_12_address0;
sc_out< sc_logic > threshs1_m_threshold_12_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_12_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_12_q0;
sc_out< sc_logic > threshs1_m_threshold_12_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_12_address1;
sc_out< sc_logic > threshs1_m_threshold_12_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_12_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_12_q1;
sc_out< sc_logic > threshs1
|
_m_threshold_12_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_11_address0;
sc_out< sc_logic > threshs1_m_threshold_11_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_11_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_11_q0;
sc_out< sc_logic > threshs1_m_threshold_11_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_11_address1;
sc_out< sc_logic > threshs1_m_threshold_11_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_11_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_11_q1;
sc_out< sc_logic > threshs1_m_threshold_11_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_10_address0;
sc_out< sc_logic > threshs1_m_threshold_10_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_10_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_10_q0;
sc_out< sc_logic > threshs1_m_threshold_10_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_10_address1;
sc_out< sc_logic > threshs1_m_threshold_10_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_10_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_10_q1;
sc_out< sc_logic > threshs1_m_threshold_10_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_9_address0;
sc_out< sc_logic > threshs1_m_threshold_9_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_9_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_9_q0;
sc_out< sc_logic > threshs1_m_threshold_9_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_9_address1;
sc_out< sc_logic > threshs1_m_threshold_9_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_9_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_9_q1;
sc_out< sc_logic > threshs1_m_threshold_9_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_8_address0;
sc_out< sc_logic > threshs1_m_threshold_8_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_8_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_8_q0;
sc_out< sc_logic > threshs1_m_threshold_8_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_8_address1;
sc_out< sc_logic > threshs1_m_threshold_8_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_8_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_8_q1;
sc_out< sc_logic > threshs1_m_threshold_8_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_6_address0;
sc_out< sc_logic > threshs1_m_threshold_6_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_6_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_6_q0;
sc_out< sc_logic > threshs1_m_threshold_6_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_6_address1;
sc_out< sc_logic > threshs1_m_threshold_6_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_6_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_6_q1;
sc_out< sc_logic > threshs1_m_threshold_6_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_5_address0;
sc_out< sc_logic > threshs1_m_threshold_5_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_5_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_5_q0;
sc_out< sc_logic > threshs1_m_threshold_5_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_5_address1;
sc_out< sc_logic > threshs1_m_threshold_5_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_5_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_5_q1;
sc_out< sc_logic > threshs1_m_threshold_5_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_4_address0;
sc_out< sc_logic > threshs1_m_threshold_4_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_4_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_4_q0;
sc_out< sc_logic > threshs1_m_threshold_4_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_4_address1;
sc_out< sc_logic > threshs1_m_threshold_4_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_4_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_4_q1;
sc_out< sc_logic > threshs1_m_threshold_4_we1;
sc_out< sc_lv<4> > threshs1_m_threshold_3_address0;
sc_out< sc_logic > threshs1_m_threshold_3_ce0;
sc_out< sc_lv<16> > threshs1_m_threshold_3_d0;
sc_in< sc_lv<16> > threshs1_m_threshold_3_q0;
sc_out< sc_logic > threshs1_m_threshold_3_we0;
sc_out< sc_lv<4> > threshs1_m_threshold_3_address1;
sc_out< sc_logic > threshs1_m_threshold_3_ce1;
sc_out< sc_lv<16> > threshs1_m_threshold_3_d1;
sc_in< sc_lv<16> > threshs1_m_threshold_3_q1;
sc_out< sc_logic > threshs1_m_threshold_3_we1;
sc_out< sc_lv<9> > weights2_m_weights_V_address0;
sc_out< sc_logic > weights2_m_weights_V_ce0;
sc_out< sc_lv<64> > weights2_m_weights_V_d0;
sc_in< sc_lv<64> > weights2_m_weights_V_q0;
sc_out< sc_logic > weights2_m_weights_V_we0;
sc_out< sc_lv<9> > weights2_m_weights_V_address1;
sc_out< sc_logic > weights2_m_weights_V_ce1;
sc_out< sc_lv<64> > weights2_m_weights_V_d1;
sc_in< sc_lv<64> > weights2_m_weights_V_q1;
sc_out< sc_logic > weights2_m_weights_V_we1;
sc_out< sc_lv<9> > weights2_m_weights_V_1_address0;
sc_out< sc_logic > weights2_m_weights_V_1_ce0;
sc_out< sc_lv<64> > weights2_m_weights_V_1_d0;
sc_in< sc_lv<64> > weights2_m_weights_V_1_q0;
sc_out< sc_logic > weights2_m_weights_V_1_we0;
sc_out< sc_lv<9> > weights2_m_weights_V_1_address1;
sc_out< sc_logic > weights2_m_weights_V_1_ce1;
sc_out< sc_lv<64> > weights2_m_weights_V_1_d1;
sc_in< sc_lv<64> > weights2_m_weights_V_1_q1;
sc_out< sc_logic > weights2_m_weights_V_1_we1;
sc_out< sc_lv<9> > weights2_m_weights_V_2_address0;
sc_out< sc_logic > weights2_m_weights_V_2_ce0;
sc_out< sc_lv<64> > weights2_m_weights_V_2_d0;
sc_in< sc_lv<64> > weights2_m_weights_V_2_q0;
sc_out< sc_logic > weights2_m_weights_V_2_we0;
sc_out< sc_lv<9> > weights2_m_weights_V_2_address1;
sc_out< sc_logic > weights2_m_weights_V_2_ce1;
sc_out< sc_lv<64> > weights2_m_weights_V_2_d1;
sc_in< sc_lv<64> > weights2_m_weights_V_2_q1;
sc_out< sc_logic > weights2_m_weights_V_2_we1;
sc_out< sc_lv<9> > weights2_m_weights_V_3_address0;
sc_out< sc_logic > weights2_m_weights_V_3_ce0;
sc_out< sc_lv<64> > weights2_m_weights_V_3_d0;
sc_in< sc_lv<64> > weights2_m_weights_V_3_q0;
sc_out< sc_logic > weights2_m_weights_V_3_we0;
sc_out< sc_lv<9> > weights2_m_weights_V_3_address1;
sc_out< sc_logic > weights2_m_weights_V_3_ce1;
sc_out< sc_lv<64> > weights2_m_weights_V_3_d1;
sc_in< sc_lv<64> > weights2_m_weights_V_3_q1;
sc_out< sc_logic > weights2_m_weights_V_3_we1;
sc_out< sc_lv<9> > weights2_m_weights_V_4_address0;
sc_out< sc_logic > weights2_m_weights_V_4_ce0;
sc_out< sc_lv<64> > weights2_m_weights_V_4_d0;
sc_in< sc_lv<64> > weights2_m_weights_V_4_q0;
sc_out< sc_logic > weights2_m_weights_V_4_we0;
sc_out< sc_lv<9> > weights2_m_weights_V_4_address1;
sc_out< sc_logic > weights2_m_weights_V_4_ce1;
sc_out< sc_lv<64> > weights2_m_weights_V_4_d1;
sc_in< sc_lv<64> > weights2_m_weights_V_4_q1;
sc_out< sc_logic > weights2_m_weights_V_4_we1;
sc_out< sc_lv<9> > weights2_m_weights_V_5_address0;
sc_out< sc_logic > weights2_m_weights_V_5_ce0;
sc_out< sc_lv<64> > weights2_m_weights_V_5_d0;
sc_in< sc_lv<64> > weights2_m_weights_V_5_q0;
sc_out< sc_logic > weights2_m_weights_V_5_we0;
sc_out< sc_lv<9> > weights2_m_weights_V_5_address1;
sc_out< sc_logic > weights2_m_weights_V_5_ce1;
sc_out< sc_lv<64> > weights2_m_weights_V_5_d1;
sc_in< sc_lv<64> > weights2_m_weights_V_5_q1;
sc_out< sc_logic > weights2_m_weights_V_5_we1;
sc_out< sc_lv<9> > weights2_m_weights_V_6_address0;
sc_out< sc_logic > weights2_m_weights_V_6_ce0;
sc_out< sc_lv<64> > weights2_m_weights_V_6_d0;
sc_in< sc_lv<64> > weights2_m_weights_V_6_q0;
sc_out< sc_logic > weights2_m_weights_V_6_we0;
sc_out< sc_lv<9> > weights2_m_weights_V_6_address1;
sc_out< sc_logic > weights2_m_weights_V_6_ce1;
sc_out< sc_lv<64> > weights2_m_weights_V_6_d1;
sc_in< sc_lv<64> > weights2_m_weights_V_6_q1;
sc_out< sc_logic > weights2_m_weights_V_6_we1;
sc_out< sc_lv<9> > weights2_m_weights_V_7_address0;
sc_out< sc_logic > weights2_m_weights_V_7_ce0;
sc_out< sc_lv<64> > weights2_m_weights_V_7_d0;
sc_in< sc_lv<64> > weights2_m_weights_V_7_q0;
sc_out< sc_logic > weights2_m_weights_V_7_we0;
sc_out< sc_lv<9> > weights2_m_weights_V_7_address1;
sc_out< sc_logic > weights2_m_weights_V_7_ce1;
sc_out< sc_lv<64> > weights2_m_weights_V_7_d1;
sc_in< sc_lv<64> > weights2_m_weights_V_7_q1;
sc_out< sc_logic > weights2_m_weights_V_7_we1;
sc_out< sc_lv<9> > weights2_m_weights_V_8_address0;
sc_out< sc_logic > weights2_m_weights_V_8_ce0;
sc_out< sc_lv<64> > weights2_m_weights_V_8_d0;
sc_in< sc_lv<64> > weights2_m_weights_V_8_q0;
sc_out< sc_logic > weights2_m_weights_V_8_we0;
sc_out< sc_lv<9> > weights2_m_weights_V_8_address1;
sc_out< sc_logic > weights2_m_weights_V_8_ce1;
sc_out< sc_lv<64> > weights2_m_weights_V_8_d1;
sc_in< sc_lv<64> > weights2_m_weights_V_8_q1;
sc_out< sc_logic > weights2_m_weights_V_8_we1;
sc_out< sc_lv<9> > weights2_m_weights_V_9_address0;
sc_out< sc_logic > weights2_m_weights_V_9_ce0;
sc_out< sc_lv<64> > weights2_m_weights_V_9_d0;
sc_in< sc_lv<64> > weights2_m_weights_V_9_q0;
sc_out< sc_logic > weights2_m_weights_V_9_we0;
sc_out< sc_lv<9> > weights2_m_weights_V_9_address1;
sc_out< sc_logic > weights2_m_weights_V_9_ce1;
sc_out< sc_lv<64> > weights2_m_weights_V_9_d1;
sc_in< sc_lv<64> > weights2_m_weights_V_9_q1;
sc_out< sc_logic > weights2_m_weights_V_9_we1;
sc_out< sc_lv<9> > weights2_m_weights_V_10_address0;
sc_out< sc_logic > weights2_m_weights_V_10_ce0;
sc_out< sc_lv<64> > weights2_m_weights_V_10_d0;
sc_in< sc_lv<64> > weights2_m_weights_V_10_q0;
sc_out< sc_logic > weights2_m_weights_V_10_we0;
sc_out< sc_lv<9> > weights2_m_weights_V_10_address1;
sc_out< sc_logic > weights2_m_weights_V_10_ce1;
sc_out< sc_lv<64> > weights2_m_weights_V_10_d1;
sc_in< sc_lv<64> > weights2_m_weights_V_10_q1;
sc_out< sc_logic > weights2_m_weights_V_10_we1;
sc_out< sc_lv<9> > weights2_m_weights_V_11_address0;
sc_out< sc_logic > weights2_m_weights_V_11_ce0;
sc_out< sc_lv<64> > weights2_m_weights_V_11_d0;
sc_in< sc_lv<64> > weights2_m_weights_V_11_q0;
sc_out< sc_logic > weights2_m_weights_V_11_we0;
sc_out< sc_lv<9> > weights2_m_weights_V_11_address1;
sc_out< sc_logic > weights2_m_weights_V_11_ce1;
sc_out< sc_lv<64> > weights2_m_weights_V_11_d1;
sc_in< sc_lv<64> > weights2_m_weights_V_11_q1;
sc_out< sc_logic > weights2_m_weights_V_11_we1;
sc_out< sc_lv<9> > weights2_m_weights_V_12_address0;
sc_out< sc_logic > weights2_m_weights_V_12_ce0;
sc_out< sc_lv<64> > weights2_m_weights_V_12_d0;
sc_in< sc_lv<64> > weights2_m_weights_V_12_q0;
sc_out< sc_logic > weights2_m_weights_V_12_we0;
sc_out< sc_lv<9> > weights2_m_weights_V_12_address1;
sc_out< sc_logic > weights2_m_weights_V_12_ce1;
sc_out< sc_lv<64> > weights2_m_weights_V_12_d1;
sc_in< sc_lv<64> > weights2_m_weights_V_12_q1;
sc_out< sc_logic > weights2_m_weights_V_12_we1;
sc_out< sc_lv<9> > weights2_m_weights_V_13_address0;
sc_out< sc_logic > weights2_m_weights_V_13_ce0;
sc_out< sc_lv<64> > weights2_m_weights_V_13_d0;
sc_in< sc_lv<64> > weights2_m_weights_V_13_q0;
sc_out< sc_logic > weights2_m_weights_V_13_we0;
sc_out< sc_lv<9> > weights2_m_weights_V_13_address1;
sc_out< sc_logic > weights2_m_weights_V_13_ce1;
sc_out< sc_lv<64> > weights2_m_weights_V_13_d1;
sc_in< sc_lv<64> > weights2_m_weights_V_13_q1;
sc_out< sc_logic > weights2_m_weights_V_13_we1;
sc_out< sc_lv<9> > weights2_m_weights_V_14_address0;
sc_out< sc_logic > weights2_m_weights_V_14_ce0;
sc_out< sc_lv<64> > weights2_m_weights_V_14_d0;
sc_in< sc_lv<64> > weights2_m_weights_V_14_q0;
sc_out< sc_logic > weights2_m_weights_V_14_we0;
sc_out< sc_lv<9> > weights2_m_weights_V_14_address1;
sc_out< sc_logic > weights2_m_weights_V_14_ce1;
sc_out< sc_lv<64> > weights2_m_weights_V_14_d1;
sc_in< sc_lv<64> > weights2_m_weights_V_14_q1;
sc_out< sc_logic > weights2_m_weights_V_14_we1;
sc_out< sc_lv<9> > weights2_m_weights_V_15_address0;
sc_out< sc_logic > weights2_m_weights_V_15_ce0;
sc_out< sc_lv<64> > weights2_m_weights_V_15_d0;
sc_in< sc_lv<64> > weights2_m_weights_V_15_q0;
sc_out< sc_logic > weights2_m_weights_V_15_we0;
sc_out< sc_lv<9> > weights2_m_weights_V_15_address1;
sc_out< sc_logic > weights2_m_weights_V_15_ce1;
sc_out< sc_lv<64> > weights2_m_weights_V_15_d1;
sc_in< sc_lv<64> > weights2_m_weights_V_15_q1;
sc_out< sc_logic > weights2_m_weights_V_15_we1;
sc_out< sc_lv<9> > weights2_m_weights_V_16_address0;
sc_out< sc_logic > weights2_m_weights_V_16_ce0;
sc_out< sc_lv<64> > weights2_m_weights_V_16_d0;
sc_in< sc_lv<64> > weights2_m_weights_V_16_q0;
sc_out< sc_logic > weights2_m_weights_V_16_we0;
sc_out< sc_lv<9> > weights2_m_weights_V_16_address1;
sc_out< sc_logic > weights2_m_weights_V_16_ce1;
sc_out< sc_lv<64> > weights2_m_weights_V_16_d1;
sc_in< sc_lv<64> > weights2_m_weights_V_16_q1;
sc_out< sc_logic > weights2_m_weights_V_16_we1;
sc_out< sc_lv<9> > weights2_m_weights_V_17_address0;
sc_out< sc_logic > weights2_m_weights_V_17_ce0;
sc_out< sc_lv<64> > weights2_m_weights_V_17_d0;
sc_in< sc_lv<64> > weights2_m_weights_V_17_q0;
sc_out< sc_logic > weights2_m_weights_V_17_we0;
sc_out< sc_lv<9> > weights2_m_weights_V_17_address1;
sc_out< sc_logic > weights2_m_weights_V_17_ce1;
sc_out< sc_lv<64> > weights2_m_weights_V_17_d1;
sc_in< sc_lv<64> > weights2_m_weights_V_17_q1;
sc_out< sc_logic > weights2_m_weights_V_17_we1;
sc_out< sc_lv<9> > weights2_m_weights_V_18_address0;
sc_out< sc_logic > weights2_m_weights_V_18_ce0;
sc_out< sc_lv<64> > weights2_m_weights_V_18_d0;
sc_in< sc_lv<64> > weights2_m_weights_V_18_q0;
sc_out< sc_logic > weights2_m_weights_V_18_we0;
sc_out< sc_lv<9> > weights2_m_weights_V_18_address1;
sc_out< sc_logic > weights2_m_weights_V_18_ce1;
sc_out< sc_lv<64> > weights2_m_weights_V_18_d1;
sc_in< sc_lv<64> > weights2_m_weights_V_18_q1;
sc_out< sc_logic > weights2_m_weights_V_18_we1;
sc_out< sc_lv<9> > weights2_m_weights_V_19_address0;
sc_out< sc_logic > weights2_m_weights_V_19_ce0;
sc_out< sc_lv<64> > weights2_m_weights_V_19_d0;
sc_in< sc_lv<64> > weights2_m_weights_V_19_q0;
sc_out< sc_logic > weights2_m_weights_V_19_we0;
sc_out< sc_lv<9> > weights2_m_weights_V_19_address1;
sc_out< sc_logic > weights2_m_weights_V_19_ce1;
sc_out< sc_lv<64> > weights2_m_weights_V_19_d1;
sc_in< sc_lv<64> > weights2_m_weights_V_19_q1;
sc_out< sc_logic > weights2_m_weights_V_19_we1;
sc_out< sc_lv<9> > weights2_m_weights_V_20_address0;
sc_out< sc_logic > weights2_m_weights_V_20_ce0;
sc_out< sc_lv<64> > weights2_m_weights_V_20_d0;
sc_in< sc_lv<64> > weights2_m_weights_V_20_q0;
sc_out< sc_logic > weights2_m_weights_V_20_we0;
sc_out< sc_lv<9> > weights2_m_weights_V_20_address1;
sc_out< sc_logic > weights2_m_weights_V_20_ce1;
sc_out< sc_lv<64> > weights2_m_weights_V_20_d1;
sc_in< sc_lv<64> > weights2_m_weights_V_20_q1;
sc_out< sc_logic > weights2_m_weights_V_20_we1;
sc_out< sc_lv<9> > weights2_m_weights_V_21_address0;
sc_out< sc_logic > weights2_m_weights_V_21_ce0;
sc_out< sc_lv<64> > weights2_m_weights_V_21_d0;
sc_in< sc_lv<64> > weights2_m_weights_V_21_q0;
sc_out< sc_logic > weights2_m_weights_V_21_we0;
sc_out< sc_lv<9> > weights2_m_weights_V_21_address1;
sc_out< sc_logic > weights2_m_weights_V_21_ce1;
sc_out< sc_lv<64> > weights2_m_weights_V_21_d1;
sc_in< sc_lv<64> > weights2_m_weights_V_21_q1;
sc_out< sc_logic > weights2_m_weights_V_21_we1;
sc_out< sc_lv<9> > weights2_m_weights_V_22_address0;
sc_out< sc_logic > weights2_m_weights_V_22_ce0;
sc_out< sc_lv<64> > weights2_m_weights_V_22_d0;
sc_in< sc_lv<64> > weights2_m_weights_V_22_q0;
sc_out< sc_logic > weights2_m_weights_V_22_we0;
sc_out< sc_lv<9> > weights2_m_weights_V_22_address1;
sc_out< sc_logic > weights2_m_weights_V_22_ce1;
sc_out< sc_lv<64> > weights2_m_weights_V_22_d1;
sc_in< sc_lv<64> > weights2_m_weights_V_22_q1;
sc_out< sc_logic > weights2_m_weights_V_22_we1;
sc_out< sc_lv<9> > weights2_m_weights_V_23_address0;
sc_out< sc_logic > weights2_m_weights_V_23_ce0;
sc_out< sc_lv<64> > weights2_m_weights_V_23_d0;
sc_in< sc_lv<64> > weights2_m_weights_V_23_q0;
sc_out< sc_logic > weights2_m_weights_V_23_we0;
sc_out< sc_lv<9> > weights2_m_weights_V_23_address1;
sc_out< sc_logic > weights2_m_weights_V_23_ce1;
sc_out< sc_lv<64> > weights2_m_weights_V_23_d1;
sc_in< sc_lv<64> > weights2_m_weights_V_23_q1;
sc_out< sc_logic > weights2_m_weights_V_23_we1;
sc_out< sc_lv<9> > weights2_m_weights_V_24_address0;
sc_out< sc_logic > weights2_m_weights_V_24_ce0;
sc_out< sc_lv<64> > weights2_m_weights_V_24_d0;
sc_in< sc_lv<64> > weights2_m_weights_V_24_q0;
sc_out< sc_logic > weights2_m_weights_V_24_we0;
sc_out< sc_lv<9> > weights2_m_weights_V_24_address1;
sc_out< sc_logic > weights2_m_weights_V_24_ce1;
sc_out< sc_lv<64> > weights2_m_weights_V_24_d1;
sc_in< sc_lv<64> > weights2_m_weights_V_24_q1;
sc_out< sc_logic > weights2_m_weights_V_24_we1;
sc_out< sc_lv<9> > weights2_m_weights_V_25_address0;
sc_out< sc_logic > weights2_m_weights_V_25_ce0;
sc_out< sc_lv<64> > weights2_m_weights_V_25_d0;
sc_in< sc_lv<64> > weights2_m_weights_V_25_q0;
sc_out< sc_logic > weights2_m_weights_V_25_we0;
sc_out< sc_lv<9> > weights2_m_weights_V_25_address1;
sc_out< sc_logic > weights2_m_weights_V_25_ce1;
sc_out< sc_lv<64> > weights2_m_weights_V_25_d1;
sc_in< sc_lv<64> > weights2_m_weights_V_25_q1;
sc_out< sc_logic > weights2_m_weights_V_25_we1;
sc_out< sc_lv<9> > weights2_m_weights_V_26_address0;
sc_out< sc_logic > weights2_m_weights_V_26_ce0;
sc_out< sc_lv<64> > weights2_m_weights_V_26_d0;
sc_in< sc_lv<64> > weights2_m_weights_V_26_q0;
sc_out< sc_logic > weights2_m_weights_V_26_we0;
sc_out< sc_lv<9> > weights2_m_weights_V_26_address1;
sc_out< sc_logic > weights2_m_weights_V_26_ce1;
sc_out< sc_lv<64> > weights2_m_weights_V_26_d1;
sc_in< sc_lv<64> > weights2_m_weights_V_26_q1;
sc_out< sc_logic > weights2_m_weights_V_26_we1;
sc_out< sc_lv<9> > weights2_m_weights_V_27_address0;
sc_out< sc_logic > weights2_m_weights_V_27_ce0;
sc_out< sc_lv<64> > weights2_m_weights_V_27_d0;
sc_in< sc_lv<64> > weights2_m_weights_V_27_q0;
sc_out< sc_logic > weights2_m_weights_V_27_we0;
sc_out< sc_lv<9> > weights2_m_weights_V_27_address1;
sc_out< sc_logic > weights2_m_weights_V_27_ce1;
sc_out< sc_lv<64> > weights2_m_weights_V_27_d1;
sc_in< sc_lv<64> > weights2_m_weights_V_27_q1;
sc_out< sc_logic > weights2_m_weights_V_27_we1;
sc_out< sc_lv<9> > weights2_m_weights_V_28_address0;
sc_out< sc_logic > weights2_m_weights_V_28_ce0;
sc_out< sc_lv<64> > weights2_m_weights_V_28_d0;
sc_in< sc_lv<64> > weights2_m_weights_V_28_q0;
sc_out< sc_logic > weights2_m_weights_V_28_we0;
sc_out< sc_lv<9> > weights2_m_weights_V_28_address1;
sc_out< sc_logic > weights2_m_weights_V_28_ce1;
sc_out< sc_lv<64> > weights2_m_weights_V_28_d1;
sc_in< sc_lv<64> > weights2_m_weights_V_28_q1;
sc_out< sc_logic > weights2_m_weights_V_28_we1;
sc_out< sc_lv<9> > weights2_m_weights_V_29_address0;
sc_out< sc_logic > weights2_m_weights_V_29_ce0;
sc_out< sc_lv<64> > weights2_m_weights_V_29_d0;
sc_in< sc_lv<64> > weights2_m_weights_V_29_q0;
sc_out< sc_logic > weights2_m_weights_V_29_we0;
sc_out< sc_lv<9> > weights2_m_weights_V_29_address1;
sc_out< sc_logic > weights2_m_weights_V_29_ce1;
sc_out< sc_lv<64> > weights2_m_weights_V_29_d1;
sc_in< sc_lv<64> > weights2_m_weights_V_29_q1;
sc_out< sc_logic > weights2_m_weights_V_29_we1;
sc_out< sc_lv<9> > weights2_m_weights_V_30_address0;
sc_out< sc_logic > weights2_m_weig
|
hts_V_30_ce0;
sc_out< sc_lv<64> > weights2_m_weights_V_30_d0;
sc_in< sc_lv<64> > weights2_m_weights_V_30_q0;
sc_out< sc_logic > weights2_m_weights_V_30_we0;
sc_out< sc_lv<9> > weights2_m_weights_V_30_address1;
sc_out< sc_logic > weights2_m_weights_V_30_ce1;
sc_out< sc_lv<64> > weights2_m_weights_V_30_d1;
sc_in< sc_lv<64> > weights2_m_weights_V_30_q1;
sc_out< sc_logic > weights2_m_weights_V_30_we1;
sc_out< sc_lv<9> > weights2_m_weights_V_31_address0;
sc_out< sc_logic > weights2_m_weights_V_31_ce0;
sc_out< sc_lv<64> > weights2_m_weights_V_31_d0;
sc_in< sc_lv<64> > weights2_m_weights_V_31_q0;
sc_out< sc_logic > weights2_m_weights_V_31_we0;
sc_out< sc_lv<9> > weights2_m_weights_V_31_address1;
sc_out< sc_logic > weights2_m_weights_V_31_ce1;
sc_out< sc_lv<64> > weights2_m_weights_V_31_d1;
sc_in< sc_lv<64> > weights2_m_weights_V_31_q1;
sc_out< sc_logic > weights2_m_weights_V_31_we1;
sc_out< sc_lv<5> > threshs2_m_threshold_31_address0;
sc_out< sc_logic > threshs2_m_threshold_31_ce0;
sc_out< sc_lv<16> > threshs2_m_threshold_31_d0;
sc_in< sc_lv<16> > threshs2_m_threshold_31_q0;
sc_out< sc_logic > threshs2_m_threshold_31_we0;
sc_out< sc_lv<5> > threshs2_m_threshold_31_address1;
sc_out< sc_logic > threshs2_m_threshold_31_ce1;
sc_out< sc_lv<16> > threshs2_m_threshold_31_d1;
sc_in< sc_lv<16> > threshs2_m_threshold_31_q1;
sc_out< sc_logic > threshs2_m_threshold_31_we1;
sc_out< sc_lv<5> > threshs2_m_threshold_30_address0;
sc_out< sc_logic > threshs2_m_threshold_30_ce0;
sc_out< sc_lv<16> > threshs2_m_threshold_30_d0;
sc_in< sc_lv<16> > threshs2_m_threshold_30_q0;
sc_out< sc_logic > threshs2_m_threshold_30_we0;
sc_out< sc_lv<5> > threshs2_m_threshold_30_address1;
sc_out< sc_logic > threshs2_m_threshold_30_ce1;
sc_out< sc_lv<16> > threshs2_m_threshold_30_d1;
sc_in< sc_lv<16> > threshs2_m_threshold_30_q1;
sc_out< sc_logic > threshs2_m_threshold_30_we1;
sc_out< sc_lv<5> > threshs2_m_threshold_19_address0;
sc_out< sc_logic > threshs2_m_threshold_19_ce0;
sc_out< sc_lv<16> > threshs2_m_threshold_19_d0;
sc_in< sc_lv<16> > threshs2_m_threshold_19_q0;
sc_out< sc_logic > threshs2_m_threshold_19_we0;
sc_out< sc_lv<5> > threshs2_m_threshold_19_address1;
sc_out< sc_logic > threshs2_m_threshold_19_ce1;
sc_out< sc_lv<16> > threshs2_m_threshold_19_d1;
sc_in< sc_lv<16> > threshs2_m_threshold_19_q1;
sc_out< sc_logic > threshs2_m_threshold_19_we1;
sc_out< sc_lv<5> > threshs2_m_threshold_8_address0;
sc_out< sc_logic > threshs2_m_threshold_8_ce0;
sc_out< sc_lv<16> > threshs2_m_threshold_8_d0;
sc_in< sc_lv<16> > threshs2_m_threshold_8_q0;
sc_out< sc_logic > threshs2_m_threshold_8_we0;
sc_out< sc_lv<5> > threshs2_m_threshold_8_address1;
sc_out< sc_logic > threshs2_m_threshold_8_ce1;
sc_out< sc_lv<16> > threshs2_m_threshold_8_d1;
sc_in< sc_lv<16> > threshs2_m_threshold_8_q1;
sc_out< sc_logic > threshs2_m_threshold_8_we1;
sc_out< sc_lv<5> > threshs2_m_threshold_5_address0;
sc_out< sc_logic > threshs2_m_threshold_5_ce0;
sc_out< sc_lv<16> > threshs2_m_threshold_5_d0;
sc_in< sc_lv<16> > threshs2_m_threshold_5_q0;
sc_out< sc_logic > threshs2_m_threshold_5_we0;
sc_out< sc_lv<5> > threshs2_m_threshold_5_address1;
sc_out< sc_logic > threshs2_m_threshold_5_ce1;
sc_out< sc_lv<16> > threshs2_m_threshold_5_d1;
sc_in< sc_lv<16> > threshs2_m_threshold_5_q1;
sc_out< sc_logic > threshs2_m_threshold_5_we1;
sc_out< sc_lv<5> > threshs2_m_threshold_4_address0;
sc_out< sc_logic > threshs2_m_threshold_4_ce0;
sc_out< sc_lv<16> > threshs2_m_threshold_4_d0;
sc_in< sc_lv<16> > threshs2_m_threshold_4_q0;
sc_out< sc_logic > threshs2_m_threshold_4_we0;
sc_out< sc_lv<5> > threshs2_m_threshold_4_address1;
sc_out< sc_logic > threshs2_m_threshold_4_ce1;
sc_out< sc_lv<16> > threshs2_m_threshold_4_d1;
sc_in< sc_lv<16> > threshs2_m_threshold_4_q1;
sc_out< sc_logic > threshs2_m_threshold_4_we1;
sc_out< sc_lv<5> > threshs2_m_threshold_3_address0;
sc_out< sc_logic > threshs2_m_threshold_3_ce0;
sc_out< sc_lv<16> > threshs2_m_threshold_3_d0;
sc_in< sc_lv<16> > threshs2_m_threshold_3_q0;
sc_out< sc_logic > threshs2_m_threshold_3_we0;
sc_out< sc_lv<5> > threshs2_m_threshold_3_address1;
sc_out< sc_logic > threshs2_m_threshold_3_ce1;
sc_out< sc_lv<16> > threshs2_m_threshold_3_d1;
sc_in< sc_lv<16> > threshs2_m_threshold_3_q1;
sc_out< sc_logic > threshs2_m_threshold_3_we1;
sc_out< sc_lv<5> > threshs2_m_threshold_2_address0;
sc_out< sc_logic > threshs2_m_threshold_2_ce0;
sc_out< sc_lv<16> > threshs2_m_threshold_2_d0;
sc_in< sc_lv<16> > threshs2_m_threshold_2_q0;
sc_out< sc_logic > threshs2_m_threshold_2_we0;
sc_out< sc_lv<5> > threshs2_m_threshold_2_address1;
sc_out< sc_logic > threshs2_m_threshold_2_ce1;
sc_out< sc_lv<16> > threshs2_m_threshold_2_d1;
sc_in< sc_lv<16> > threshs2_m_threshold_2_q1;
sc_out< sc_logic > threshs2_m_threshold_2_we1;
sc_out< sc_lv<5> > threshs2_m_threshold_1_address0;
sc_out< sc_logic > threshs2_m_threshold_1_ce0;
sc_out< sc_lv<16> > threshs2_m_threshold_1_d0;
sc_in< sc_lv<16> > threshs2_m_threshold_1_q0;
sc_out< sc_logic > threshs2_m_threshold_1_we0;
sc_out< sc_lv<5> > threshs2_m_threshold_1_address1;
sc_out< sc_logic > threshs2_m_threshold_1_ce1;
sc_out< sc_lv<16> > threshs2_m_threshold_1_d1;
sc_in< sc_lv<16> > threshs2_m_threshold_1_q1;
sc_out< sc_logic > threshs2_m_threshold_1_we1;
sc_out< sc_lv<5> > threshs2_m_threshold_address0;
sc_out< sc_logic > threshs2_m_threshold_ce0;
sc_out< sc_lv<16> > threshs2_m_threshold_d0;
sc_in< sc_lv<16> > threshs2_m_threshold_q0;
sc_out< sc_logic > threshs2_m_threshold_we0;
sc_out< sc_lv<5> > threshs2_m_threshold_address1;
sc_out< sc_logic > threshs2_m_threshold_ce1;
sc_out< sc_lv<16> > threshs2_m_threshold_d1;
sc_in< sc_lv<16> > threshs2_m_threshold_q1;
sc_out< sc_logic > threshs2_m_threshold_we1;
sc_out< sc_lv<5> > threshs2_m_threshold_29_address0;
sc_out< sc_logic > threshs2_m_threshold_29_ce0;
sc_out< sc_lv<16> > threshs2_m_threshold_29_d0;
sc_in< sc_lv<16> > threshs2_m_threshold_29_q0;
sc_out< sc_logic > threshs2_m_threshold_29_we0;
sc_out< sc_lv<5> > threshs2_m_threshold_29_address1;
sc_out< sc_logic > threshs2_m_threshold_29_ce1;
sc_out< sc_lv<16> > threshs2_m_threshold_29_d1;
sc_in< sc_lv<16> > threshs2_m_threshold_29_q1;
sc_out< sc_logic > threshs2_m_threshold_29_we1;
sc_out< sc_lv<5> > threshs2_m_threshold_28_address0;
sc_out< sc_logic > threshs2_m_threshold_28_ce0;
sc_out< sc_lv<16> > threshs2_m_threshold_28_d0;
sc_in< sc_lv<16> > threshs2_m_threshold_28_q0;
sc_out< sc_logic > threshs2_m_threshold_28_we0;
sc_out< sc_lv<5> > threshs2_m_threshold_28_address1;
sc_out< sc_logic > threshs2_m_threshold_28_ce1;
sc_out< sc_lv<16> > threshs2_m_threshold_28_d1;
sc_in< sc_lv<16> > threshs2_m_threshold_28_q1;
sc_out< sc_logic > threshs2_m_threshold_28_we1;
sc_out< sc_lv<5> > threshs2_m_threshold_27_address0;
sc_out< sc_logic > threshs2_m_threshold_27_ce0;
sc_out< sc_lv<16> > threshs2_m_threshold_27_d0;
sc_in< sc_lv<16> > threshs2_m_threshold_27_q0;
sc_out< sc_logic > threshs2_m_threshold_27_we0;
sc_out< sc_lv<5> > threshs2_m_threshold_27_address1;
sc_out< sc_logic > threshs2_m_threshold_27_ce1;
sc_out< sc_lv<16> > threshs2_m_threshold_27_d1;
sc_in< sc_lv<16> > threshs2_m_threshold_27_q1;
sc_out< sc_logic > threshs2_m_threshold_27_we1;
sc_out< sc_lv<5> > threshs2_m_threshold_26_address0;
sc_out< sc_logic > threshs2_m_threshold_26_ce0;
sc_out< sc_lv<16> > threshs2_m_threshold_26_d0;
sc_in< sc_lv<16> > threshs2_m_threshold_26_q0;
sc_out< sc_logic > threshs2_m_threshold_26_we0;
sc_out< sc_lv<5> > threshs2_m_threshold_26_address1;
sc_out< sc_logic > threshs2_m_threshold_26_ce1;
sc_out< sc_lv<16> > threshs2_m_threshold_26_d1;
sc_in< sc_lv<16> > threshs2_m_threshold_26_q1;
sc_out< sc_logic > threshs2_m_threshold_26_we1;
sc_out< sc_lv<5> > threshs2_m_threshold_25_address0;
sc_out< sc_logic > threshs2_m_threshold_25_ce0;
sc_out< sc_lv<16> > threshs2_m_threshold_25_d0;
sc_in< sc_lv<16> > threshs2_m_threshold_25_q0;
sc_out< sc_logic > threshs2_m_threshold_25_we0;
sc_out< sc_lv<5> > threshs2_m_threshold_25_address1;
sc_out< sc_logic > threshs2_m_threshold_25_ce1;
sc_out< sc_lv<16> > threshs2_m_threshold_25_d1;
sc_in< sc_lv<16> > threshs2_m_threshold_25_q1;
sc_out< sc_logic > threshs2_m_threshold_25_we1;
sc_out< sc_lv<5> > threshs2_m_threshold_24_address0;
sc_out< sc_logic > threshs2_m_threshold_24_ce0;
sc_out< sc_lv<16> > threshs2_m_threshold_24_d0;
sc_in< sc_lv<16> > threshs2_m_threshold_24_q0;
sc_out< sc_logic > threshs2_m_threshold_24_we0;
sc_out< sc_lv<5> > threshs2_m_threshold_24_address1;
sc_out< sc_logic > threshs2_m_threshold_24_ce1;
sc_out< sc_lv<16> > threshs2_m_threshold_24_d1;
sc_in< sc_lv<16> > threshs2_m_threshold_24_q1;
sc_out< sc_logic > threshs2_m_threshold_24_we1;
sc_out< sc_lv<5> > threshs2_m_threshold_23_address0;
sc_out< sc_logic > threshs2_m_threshold_23_ce0;
sc_out< sc_lv<16> > threshs2_m_threshold_23_d0;
sc_in< sc_lv<16> > threshs2_m_threshold_23_q0;
sc_out< sc_logic > threshs2_m_threshold_23_we0;
sc_out< sc_lv<5> > threshs2_m_threshold_23_address1;
sc_out< sc_logic > threshs2_m_threshold_23_ce1;
sc_out< sc_lv<16> > threshs2_m_threshold_23_d1;
sc_in< sc_lv<16> > threshs2_m_threshold_23_q1;
sc_out< sc_logic > threshs2_m_threshold_23_we1;
sc_out< sc_lv<5> > threshs2_m_threshold_22_address0;
sc_out< sc_logic > threshs2_m_threshold_22_ce0;
sc_out< sc_lv<16> > threshs2_m_threshold_22_d0;
sc_in< sc_lv<16> > threshs2_m_threshold_22_q0;
sc_out< sc_logic > threshs2_m_threshold_22_we0;
sc_out< sc_lv<5> > threshs2_m_threshold_22_address1;
sc_out< sc_logic > threshs2_m_threshold_22_ce1;
sc_out< sc_lv<16> > threshs2_m_threshold_22_d1;
sc_in< sc_lv<16> > threshs2_m_threshold_22_q1;
sc_out< sc_logic > threshs2_m_threshold_22_we1;
sc_out< sc_lv<5> > threshs2_m_threshold_21_address0;
sc_out< sc_logic > threshs2_m_threshold_21_ce0;
sc_out< sc_lv<16> > threshs2_m_threshold_21_d0;
sc_in< sc_lv<16> > threshs2_m_threshold_21_q0;
sc_out< sc_logic > threshs2_m_threshold_21_we0;
sc_out< sc_lv<5> > threshs2_m_threshold_21_address1;
sc_out< sc_logic > threshs2_m_threshold_21_ce1;
sc_out< sc_lv<16> > threshs2_m_threshold_21_d1;
sc_in< sc_lv<16> > threshs2_m_threshold_21_q1;
sc_out< sc_logic > threshs2_m_threshold_21_we1;
sc_out< sc_lv<5> > threshs2_m_threshold_20_address0;
sc_out< sc_logic > threshs2_m_threshold_20_ce0;
sc_out< sc_lv<16> > threshs2_m_threshold_20_d0;
sc_in< sc_lv<16> > threshs2_m_threshold_20_q0;
sc_out< sc_logic > threshs2_m_threshold_20_we0;
sc_out< sc_lv<5> > threshs2_m_threshold_20_address1;
sc_out< sc_logic > threshs2_m_threshold_20_ce1;
sc_out< sc_lv<16> > threshs2_m_threshold_20_d1;
sc_in< sc_lv<16> > threshs2_m_threshold_20_q1;
sc_out< sc_logic > threshs2_m_threshold_20_we1;
sc_out< sc_lv<5> > threshs2_m_threshold_18_address0;
sc_out< sc_logic > threshs2_m_threshold_18_ce0;
sc_out< sc_lv<16> > threshs2_m_threshold_18_d0;
sc_in< sc_lv<16> > threshs2_m_threshold_18_q0;
sc_out< sc_logic > threshs2_m_threshold_18_we0;
sc_out< sc_lv<5> > threshs2_m_threshold_18_address1;
sc_out< sc_logic > threshs2_m_threshold_18_ce1;
sc_out< sc_lv<16> > threshs2_m_threshold_18_d1;
sc_in< sc_lv<16> > threshs2_m_threshold_18_q1;
sc_out< sc_logic > threshs2_m_threshold_18_we1;
sc_out< sc_lv<5> > threshs2_m_threshold_17_address0;
sc_out< sc_logic > threshs2_m_threshold_17_ce0;
sc_out< sc_lv<16> > threshs2_m_threshold_17_d0;
sc_in< sc_lv<16> > threshs2_m_threshold_17_q0;
sc_out< sc_logic > threshs2_m_threshold_17_we0;
sc_out< sc_lv<5> > threshs2_m_threshold_17_address1;
sc_out< sc_logic > threshs2_m_threshold_17_ce1;
sc_out< sc_lv<16> > threshs2_m_threshold_17_d1;
sc_in< sc_lv<16> > threshs2_m_threshold_17_q1;
sc_out< sc_logic > threshs2_m_threshold_17_we1;
sc_out< sc_lv<5> > threshs2_m_threshold_16_address0;
sc_out< sc_logic > threshs2_m_threshold_16_ce0;
sc_out< sc_lv<16> > threshs2_m_threshold_16_d0;
sc_in< sc_lv<16> > threshs2_m_threshold_16_q0;
sc_out< sc_logic > threshs2_m_threshold_16_we0;
sc_out< sc_lv<5> > threshs2_m_threshold_16_address1;
sc_out< sc_logic > threshs2_m_threshold_16_ce1;
sc_out< sc_lv<16> > threshs2_m_threshold_16_d1;
sc_in< sc_lv<16> > threshs2_m_threshold_16_q1;
sc_out< sc_logic > threshs2_m_threshold_16_we1;
sc_out< sc_lv<5> > threshs2_m_threshold_15_address0;
sc_out< sc_logic > threshs2_m_threshold_15_ce0;
sc_out< sc_lv<16> > threshs2_m_threshold_15_d0;
sc_in< sc_lv<16> > threshs2_m_threshold_15_q0;
sc_out< sc_logic > threshs2_m_threshold_15_we0;
sc_out< sc_lv<5> > threshs2_m_threshold_15_address1;
sc_out< sc_logic > threshs2_m_threshold_15_ce1;
sc_out< sc_lv<16> > threshs2_m_threshold_15_d1;
sc_in< sc_lv<16> > threshs2_m_threshold_15_q1;
sc_out< sc_logic > threshs2_m_threshold_15_we1;
sc_out< sc_lv<5> > threshs2_m_threshold_14_address0;
sc_out< sc_logic > threshs2_m_threshold_14_ce0;
sc_out< sc_lv<16> > threshs2_m_threshold_14_d0;
sc_in< sc_lv<16> > threshs2_m_threshold_14_q0;
sc_out< sc_logic > threshs2_m_threshold_14_we0;
sc_out< sc_lv<5> > threshs2_m_threshold_14_address1;
sc_out< sc_logic > threshs2_m_threshold_14_ce1;
sc_out< sc_lv<16> > threshs2_m_threshold_14_d1;
sc_in< sc_lv<16> > threshs2_m_threshold_14_q1;
sc_out< sc_logic > threshs2_m_threshold_14_we1;
sc_out< sc_lv<5> > threshs2_m_threshold_13_address0;
sc_out< sc_logic > threshs2_m_threshold_13_ce0;
sc_out< sc_lv<16> > threshs2_m_threshold_13_d0;
sc_in< sc_lv<16> > threshs2_m_threshold_13_q0;
sc_out< sc_logic > threshs2_m_threshold_13_we0;
sc_out< sc_lv<5> > threshs2_m_threshold_13_address1;
sc_out< sc_logic > threshs2_m_threshold_13_ce1;
sc_out< sc_lv<16> > threshs2_m_threshold_13_d1;
sc_in< sc_lv<16> > threshs2_m_threshold_13_q1;
sc_out< sc_logic > threshs2_m_threshold_13_we1;
sc_out< sc_lv<5> > threshs2_m_threshold_12_address0;
sc_out< sc_logic > threshs2_m_threshold_12_ce0;
sc_out< sc_lv<16> > threshs2_m_threshold_12_d0;
sc_in< sc_lv<16> > threshs2_m_threshold_12_q0;
sc_out< sc_logic > threshs2_m_threshold_12_we0;
sc_out< sc_lv<5> > threshs2_m_threshold_12_address1;
sc_out< sc_logic > threshs2_m_threshold_12_ce1;
sc_out< sc_lv<16> > threshs2_m_threshold_12_d1;
sc_in< sc_lv<16> > threshs2_m_threshold_12_q1;
sc_out< sc_logic > threshs2_m_threshold_12_we1;
sc_out< sc_lv<5> > threshs2_m_threshold_11_address0;
sc_out< sc_logic > threshs2_m_threshold_11_ce0;
sc_out< sc_lv<16> > threshs2_m_threshold_11_d0;
sc_in< sc_lv<16> > threshs2_m_threshold_11_q0;
sc_out< sc_logic > threshs2_m_threshold_11_we0;
sc_out< sc_lv<5> > threshs2_m_threshold_11_address1;
sc_out< sc_logic > threshs2_m_threshold_11_ce1;
sc_out< sc_lv<16> > threshs2_m_threshold_11_d1;
sc_in< sc_lv<16> > threshs2_m_threshold_11_q1;
sc_out< sc_logic > threshs2_m_threshold_11_we1;
sc_out< sc_lv<5> > threshs2_m_threshold_10_address0;
sc_out< sc_logic > threshs2_m_threshold_10_ce0;
sc_out< sc_lv<16> > threshs2_m_threshold_10_d0;
sc_in< sc_lv<16> > threshs2_m_threshold_10_q0;
sc_out< sc_logic > threshs2_m_threshold_10_we0;
sc_out< sc_lv<5> > threshs2_m_threshold_10_address1;
sc_out< sc_logic > threshs2_m_threshold_10_ce1;
sc_out< sc_lv<16> > threshs2_m_threshold_10_d1;
sc_in< sc_lv<16> > threshs2_m_threshold_10_q1;
sc_out< sc_logic > threshs2_m_threshold_10_we1;
sc_out< sc_lv<5> > threshs2_m_threshold_9_address0;
sc_out< sc_logic > threshs2_m_threshold_9_ce0;
sc_out< sc_lv<16> > threshs2_m_threshold_9_d0;
sc_in< sc_lv<16> > threshs2_m_threshold_9_q0;
sc_out< sc_logic > threshs2_m_threshold_9_we0;
sc_out< sc_lv<5> > threshs2_m_threshold_9_address1;
sc_out< sc_logic > threshs2_m_threshold_9_ce1;
sc_out< sc_lv<16> > threshs2_m_threshold_9_d1;
sc_in< sc_lv<16> > threshs2_m_threshold_9_q1;
sc_out< sc_logic > threshs2_m_threshold_9_we1;
sc_out< sc_lv<5> > threshs2_m_threshold_7_address0;
sc_out< sc_logic > threshs2_m_threshold_7_ce0;
sc_out< sc_lv<16> > threshs2_m_threshold_7_d0;
sc_in< sc_lv<16> > threshs2_m_threshold_7_q0;
sc_out< sc_logic > threshs2_m_threshold_7_we0;
sc_out< sc_lv<5> > threshs2_m_threshold_7_address1;
sc_out< sc_logic > threshs2_m_threshold_7_ce1;
sc_out< sc_lv<16> > threshs2_m_threshold_7_d1;
sc_in< sc_lv<16> > threshs2_m_threshold_7_q1;
sc_out< sc_logic > threshs2_m_threshold_7_we1;
sc_out< sc_lv<5> > threshs2_m_threshold_6_address0;
sc_out< sc_logic > threshs2_m_threshold_6_ce0;
sc_out< sc_lv<16> > threshs2_m_threshold_6_d0;
sc_in< sc_lv<16> > threshs2_m_threshold_6_q0;
sc_out< sc_logic > threshs2_m_threshold_6_we0;
sc_out< sc_lv<5> > threshs2_m_threshold_6_address1;
sc_out< sc_logic > threshs2_m_threshold_6_ce1;
sc_out< sc_lv<16> > threshs2_m_threshold_6_d1;
sc_in< sc_lv<16> > threshs2_m_threshold_6_q1;
sc_out< sc_logic > threshs2_m_threshold_6_we1;
sc_out< sc_lv<9> > weights3_m_weights_V_address0;
sc_out< sc_logic > weights3_m_weights_V_ce0;
sc_out< sc_lv<8> > weights3_m_weights_V_d0;
sc_in< sc_lv<8> > weights3_m_weights_V_q0;
sc_out< sc_logic > weights3_m_weights_V_we0;
sc_out< sc_lv<9> > weights3_m_weights_V_address1;
sc_out< sc_logic > weights3_m_weights_V_ce1;
sc_out< sc_lv<8> > weights3_m_weights_V_d1;
sc_in< sc_lv<8> > weights3_m_weights_V_q1;
sc_out< sc_logic > weights3_m_weights_V_we1;
sc_out< sc_lv<9> > weights3_m_weights_V_1_address0;
sc_out< sc_logic > weights3_m_weights_V_1_ce0;
sc_out< sc_lv<8> > weights3_m_weights_V_1_d0;
sc_in< sc_lv<8> > weights3_m_weights_V_1_q0;
sc_out< sc_logic > weights3_m_weights_V_1_we0;
sc_out< sc_lv<9> > weights3_m_weights_V_1_address1;
sc_out< sc_logic > weights3_m_weights_V_1_ce1;
sc_out< sc_lv<8> > weights3_m_weights_V_1_d1;
sc_in< sc_lv<8> > weights3_m_weights_V_1_q1;
sc_out< sc_logic > weights3_m_weights_V_1_we1;
sc_out< sc_lv<9> > weights3_m_weights_V_2_address0;
sc_out< sc_logic > weights3_m_weights_V_2_ce0;
sc_out< sc_lv<8> > weights3_m_weights_V_2_d0;
sc_in< sc_lv<8> > weights3_m_weights_V_2_q0;
sc_out< sc_logic > weights3_m_weights_V_2_we0;
sc_out< sc_lv<9> > weights3_m_weights_V_2_address1;
sc_out< sc_logic > weights3_m_weights_V_2_ce1;
sc_out< sc_lv<8> > weights3_m_weights_V_2_d1;
sc_in< sc_lv<8> > weights3_m_weights_V_2_q1;
sc_out< sc_logic > weights3_m_weights_V_2_we1;
sc_out< sc_lv<9> > weights3_m_weights_V_3_address0;
sc_out< sc_logic > weights3_m_weights_V_3_ce0;
sc_out< sc_lv<8> > weights3_m_weights_V_3_d0;
sc_in< sc_lv<8> > weights3_m_weights_V_3_q0;
sc_out< sc_logic > weights3_m_weights_V_3_we0;
sc_out< sc_lv<9> > weights3_m_weights_V_3_address1;
sc_out< sc_logic > weights3_m_weights_V_3_ce1;
sc_out< sc_lv<8> > weights3_m_weights_V_3_d1;
sc_in< sc_lv<8> > weights3_m_weights_V_3_q1;
sc_out< sc_logic > weights3_m_weights_V_3_we1;
sc_out< sc_lv<9> > weights3_m_weights_V_4_address0;
sc_out< sc_logic > weights3_m_weights_V_4_ce0;
sc_out< sc_lv<8> > weights3_m_weights_V_4_d0;
sc_in< sc_lv<8> > weights3_m_weights_V_4_q0;
sc_out< sc_logic
|
> weights3_m_weights_V_4_we0;
sc_out< sc_lv<9> > weights3_m_weights_V_4_address1;
sc_out< sc_logic > weights3_m_weights_V_4_ce1;
sc_out< sc_lv<8> > weights3_m_weights_V_4_d1;
sc_in< sc_lv<8> > weights3_m_weights_V_4_q1;
sc_out< sc_logic > weights3_m_weights_V_4_we1;
sc_out< sc_lv<9> > weights3_m_weights_V_5_address0;
sc_out< sc_logic > weights3_m_weights_V_5_ce0;
sc_out< sc_lv<8> > weights3_m_weights_V_5_d0;
sc_in< sc_lv<8> > weights3_m_weights_V_5_q0;
sc_out< sc_logic > weights3_m_weights_V_5_we0;
sc_out< sc_lv<9> > weights3_m_weights_V_5_address1;
sc_out< sc_logic > weights3_m_weights_V_5_ce1;
sc_out< sc_lv<8> > weights3_m_weights_V_5_d1;
sc_in< sc_lv<8> > weights3_m_weights_V_5_q1;
sc_out< sc_logic > weights3_m_weights_V_5_we1;
sc_out< sc_lv<9> > weights3_m_weights_V_6_address0;
sc_out< sc_logic > weights3_m_weights_V_6_ce0;
sc_out< sc_lv<8> > weights3_m_weights_V_6_d0;
sc_in< sc_lv<8> > weights3_m_weights_V_6_q0;
sc_out< sc_logic > weights3_m_weights_V_6_we0;
sc_out< sc_lv<9> > weights3_m_weights_V_6_address1;
sc_out< sc_logic > weights3_m_weights_V_6_ce1;
sc_out< sc_lv<8> > weights3_m_weights_V_6_d1;
sc_in< sc_lv<8> > weights3_m_weights_V_6_q1;
sc_out< sc_logic > weights3_m_weights_V_6_we1;
sc_out< sc_lv<9> > weights3_m_weights_V_7_address0;
sc_out< sc_logic > weights3_m_weights_V_7_ce0;
sc_out< sc_lv<8> > weights3_m_weights_V_7_d0;
sc_in< sc_lv<8> > weights3_m_weights_V_7_q0;
sc_out< sc_logic > weights3_m_weights_V_7_we0;
sc_out< sc_lv<9> > weights3_m_weights_V_7_address1;
sc_out< sc_logic > weights3_m_weights_V_7_ce1;
sc_out< sc_lv<8> > weights3_m_weights_V_7_d1;
sc_in< sc_lv<8> > weights3_m_weights_V_7_q1;
sc_out< sc_logic > weights3_m_weights_V_7_we1;
sc_out< sc_lv<9> > weights3_m_weights_V_8_address0;
sc_out< sc_logic > weights3_m_weights_V_8_ce0;
sc_out< sc_lv<8> > weights3_m_weights_V_8_d0;
sc_in< sc_lv<8> > weights3_m_weights_V_8_q0;
sc_out< sc_logic > weights3_m_weights_V_8_we0;
sc_out< sc_lv<9> > weights3_m_weights_V_8_address1;
sc_out< sc_logic > weights3_m_weights_V_8_ce1;
sc_out< sc_lv<8> > weights3_m_weights_V_8_d1;
sc_in< sc_lv<8> > weights3_m_weights_V_8_q1;
sc_out< sc_logic > weights3_m_weights_V_8_we1;
sc_out< sc_lv<9> > weights3_m_weights_V_9_address0;
sc_out< sc_logic > weights3_m_weights_V_9_ce0;
sc_out< sc_lv<8> > weights3_m_weights_V_9_d0;
sc_in< sc_lv<8> > weights3_m_weights_V_9_q0;
sc_out< sc_logic > weights3_m_weights_V_9_we0;
sc_out< sc_lv<9> > weights3_m_weights_V_9_address1;
sc_out< sc_logic > weights3_m_weights_V_9_ce1;
sc_out< sc_lv<8> > weights3_m_weights_V_9_d1;
sc_in< sc_lv<8> > weights3_m_weights_V_9_q1;
sc_out< sc_logic > weights3_m_weights_V_9_we1;
sc_out< sc_lv<9> > weights3_m_weights_V_10_address0;
sc_out< sc_logic > weights3_m_weights_V_10_ce0;
sc_out< sc_lv<8> > weights3_m_weights_V_10_d0;
sc_in< sc_lv<8> > weights3_m_weights_V_10_q0;
sc_out< sc_logic > weights3_m_weights_V_10_we0;
sc_out< sc_lv<9> > weights3_m_weights_V_10_address1;
sc_out< sc_logic > weights3_m_weights_V_10_ce1;
sc_out< sc_lv<8> > weights3_m_weights_V_10_d1;
sc_in< sc_lv<8> > weights3_m_weights_V_10_q1;
sc_out< sc_logic > weights3_m_weights_V_10_we1;
sc_out< sc_lv<9> > weights3_m_weights_V_11_address0;
sc_out< sc_logic > weights3_m_weights_V_11_ce0;
sc_out< sc_lv<8> > weights3_m_weights_V_11_d0;
sc_in< sc_lv<8> > weights3_m_weights_V_11_q0;
sc_out< sc_logic > weights3_m_weights_V_11_we0;
sc_out< sc_lv<9> > weights3_m_weights_V_11_address1;
sc_out< sc_logic > weights3_m_weights_V_11_ce1;
sc_out< sc_lv<8> > weights3_m_weights_V_11_d1;
sc_in< sc_lv<8> > weights3_m_weights_V_11_q1;
sc_out< sc_logic > weights3_m_weights_V_11_we1;
sc_out< sc_lv<9> > weights3_m_weights_V_12_address0;
sc_out< sc_logic > weights3_m_weights_V_12_ce0;
sc_out< sc_lv<8> > weights3_m_weights_V_12_d0;
sc_in< sc_lv<8> > weights3_m_weights_V_12_q0;
sc_out< sc_logic > weights3_m_weights_V_12_we0;
sc_out< sc_lv<9> > weights3_m_weights_V_12_address1;
sc_out< sc_logic > weights3_m_weights_V_12_ce1;
sc_out< sc_lv<8> > weights3_m_weights_V_12_d1;
sc_in< sc_lv<8> > weights3_m_weights_V_12_q1;
sc_out< sc_logic > weights3_m_weights_V_12_we1;
sc_out< sc_lv<9> > weights3_m_weights_V_13_address0;
sc_out< sc_logic > weights3_m_weights_V_13_ce0;
sc_out< sc_lv<8> > weights3_m_weights_V_13_d0;
sc_in< sc_lv<8> > weights3_m_weights_V_13_q0;
sc_out< sc_logic > weights3_m_weights_V_13_we0;
sc_out< sc_lv<9> > weights3_m_weights_V_13_address1;
sc_out< sc_logic > weights3_m_weights_V_13_ce1;
sc_out< sc_lv<8> > weights3_m_weights_V_13_d1;
sc_in< sc_lv<8> > weights3_m_weights_V_13_q1;
sc_out< sc_logic > weights3_m_weights_V_13_we1;
sc_out< sc_lv<9> > weights3_m_weights_V_14_address0;
sc_out< sc_logic > weights3_m_weights_V_14_ce0;
sc_out< sc_lv<8> > weights3_m_weights_V_14_d0;
sc_in< sc_lv<8> > weights3_m_weights_V_14_q0;
sc_out< sc_logic > weights3_m_weights_V_14_we0;
sc_out< sc_lv<9> > weights3_m_weights_V_14_address1;
sc_out< sc_logic > weights3_m_weights_V_14_ce1;
sc_out< sc_lv<8> > weights3_m_weights_V_14_d1;
sc_in< sc_lv<8> > weights3_m_weights_V_14_q1;
sc_out< sc_logic > weights3_m_weights_V_14_we1;
sc_out< sc_lv<9> > weights3_m_weights_V_15_address0;
sc_out< sc_logic > weights3_m_weights_V_15_ce0;
sc_out< sc_lv<8> > weights3_m_weights_V_15_d0;
sc_in< sc_lv<8> > weights3_m_weights_V_15_q0;
sc_out< sc_logic > weights3_m_weights_V_15_we0;
sc_out< sc_lv<9> > weights3_m_weights_V_15_address1;
sc_out< sc_logic > weights3_m_weights_V_15_ce1;
sc_out< sc_lv<8> > weights3_m_weights_V_15_d1;
sc_in< sc_lv<8> > weights3_m_weights_V_15_q1;
sc_out< sc_logic > weights3_m_weights_V_15_we1;
sc_out< sc_lv<2> > threshs3_m_threshold_15_address0;
sc_out< sc_logic > threshs3_m_threshold_15_ce0;
sc_out< sc_lv<16> > threshs3_m_threshold_15_d0;
sc_in< sc_lv<16> > threshs3_m_threshold_15_q0;
sc_out< sc_logic > threshs3_m_threshold_15_we0;
sc_out< sc_lv<2> > threshs3_m_threshold_15_address1;
sc_out< sc_logic > threshs3_m_threshold_15_ce1;
sc_out< sc_lv<16> > threshs3_m_threshold_15_d1;
sc_in< sc_lv<16> > threshs3_m_threshold_15_q1;
sc_out< sc_logic > threshs3_m_threshold_15_we1;
sc_out< sc_lv<2> > threshs3_m_threshold_14_address0;
sc_out< sc_logic > threshs3_m_threshold_14_ce0;
sc_out< sc_lv<16> > threshs3_m_threshold_14_d0;
sc_in< sc_lv<16> > threshs3_m_threshold_14_q0;
sc_out< sc_logic > threshs3_m_threshold_14_we0;
sc_out< sc_lv<2> > threshs3_m_threshold_14_address1;
sc_out< sc_logic > threshs3_m_threshold_14_ce1;
sc_out< sc_lv<16> > threshs3_m_threshold_14_d1;
sc_in< sc_lv<16> > threshs3_m_threshold_14_q1;
sc_out< sc_logic > threshs3_m_threshold_14_we1;
sc_out< sc_lv<2> > threshs3_m_threshold_7_address0;
sc_out< sc_logic > threshs3_m_threshold_7_ce0;
sc_out< sc_lv<16> > threshs3_m_threshold_7_d0;
sc_in< sc_lv<16> > threshs3_m_threshold_7_q0;
sc_out< sc_logic > threshs3_m_threshold_7_we0;
sc_out< sc_lv<2> > threshs3_m_threshold_7_address1;
sc_out< sc_logic > threshs3_m_threshold_7_ce1;
sc_out< sc_lv<16> > threshs3_m_threshold_7_d1;
sc_in< sc_lv<16> > threshs3_m_threshold_7_q1;
sc_out< sc_logic > threshs3_m_threshold_7_we1;
sc_out< sc_lv<2> > threshs3_m_threshold_6_address0;
sc_out< sc_logic > threshs3_m_threshold_6_ce0;
sc_out< sc_lv<16> > threshs3_m_threshold_6_d0;
sc_in< sc_lv<16> > threshs3_m_threshold_6_q0;
sc_out< sc_logic > threshs3_m_threshold_6_we0;
sc_out< sc_lv<2> > threshs3_m_threshold_6_address1;
sc_out< sc_logic > threshs3_m_threshold_6_ce1;
sc_out< sc_lv<16> > threshs3_m_threshold_6_d1;
sc_in< sc_lv<16> > threshs3_m_threshold_6_q1;
sc_out< sc_logic > threshs3_m_threshold_6_we1;
sc_out< sc_lv<2> > threshs3_m_threshold_5_address0;
sc_out< sc_logic > threshs3_m_threshold_5_ce0;
sc_out< sc_lv<16> > threshs3_m_threshold_5_d0;
sc_in< sc_lv<16> > threshs3_m_threshold_5_q0;
sc_out< sc_logic > threshs3_m_threshold_5_we0;
sc_out< sc_lv<2> > threshs3_m_threshold_5_address1;
sc_out< sc_logic > threshs3_m_threshold_5_ce1;
sc_out< sc_lv<16> > threshs3_m_threshold_5_d1;
sc_in< sc_lv<16> > threshs3_m_threshold_5_q1;
sc_out< sc_logic > threshs3_m_threshold_5_we1;
sc_out< sc_lv<2> > threshs3_m_threshold_4_address0;
sc_out< sc_logic > threshs3_m_threshold_4_ce0;
sc_out< sc_lv<16> > threshs3_m_threshold_4_d0;
sc_in< sc_lv<16> > threshs3_m_threshold_4_q0;
sc_out< sc_logic > threshs3_m_threshold_4_we0;
sc_out< sc_lv<2> > threshs3_m_threshold_4_address1;
sc_out< sc_logic > threshs3_m_threshold_4_ce1;
sc_out< sc_lv<16> > threshs3_m_threshold_4_d1;
sc_in< sc_lv<16> > threshs3_m_threshold_4_q1;
sc_out< sc_logic > threshs3_m_threshold_4_we1;
sc_out< sc_lv<2> > threshs3_m_threshold_3_address0;
sc_out< sc_logic > threshs3_m_threshold_3_ce0;
sc_out< sc_lv<16> > threshs3_m_threshold_3_d0;
sc_in< sc_lv<16> > threshs3_m_threshold_3_q0;
sc_out< sc_logic > threshs3_m_threshold_3_we0;
sc_out< sc_lv<2> > threshs3_m_threshold_3_address1;
sc_out< sc_logic > threshs3_m_threshold_3_ce1;
sc_out< sc_lv<16> > threshs3_m_threshold_3_d1;
sc_in< sc_lv<16> > threshs3_m_threshold_3_q1;
sc_out< sc_logic > threshs3_m_threshold_3_we1;
sc_out< sc_lv<2> > threshs3_m_threshold_2_address0;
sc_out< sc_logic > threshs3_m_threshold_2_ce0;
sc_out< sc_lv<16> > threshs3_m_threshold_2_d0;
sc_in< sc_lv<16> > threshs3_m_threshold_2_q0;
sc_out< sc_logic > threshs3_m_threshold_2_we0;
sc_out< sc_lv<2> > threshs3_m_threshold_2_address1;
sc_out< sc_logic > threshs3_m_threshold_2_ce1;
sc_out< sc_lv<16> > threshs3_m_threshold_2_d1;
sc_in< sc_lv<16> > threshs3_m_threshold_2_q1;
sc_out< sc_logic > threshs3_m_threshold_2_we1;
sc_out< sc_lv<2> > threshs3_m_threshold_1_address0;
sc_out< sc_logic > threshs3_m_threshold_1_ce0;
sc_out< sc_lv<16> > threshs3_m_threshold_1_d0;
sc_in< sc_lv<16> > threshs3_m_threshold_1_q0;
sc_out< sc_logic > threshs3_m_threshold_1_we0;
sc_out< sc_lv<2> > threshs3_m_threshold_1_address1;
sc_out< sc_logic > threshs3_m_threshold_1_ce1;
sc_out< sc_lv<16> > threshs3_m_threshold_1_d1;
sc_in< sc_lv<16> > threshs3_m_threshold_1_q1;
sc_out< sc_logic > threshs3_m_threshold_1_we1;
sc_out< sc_lv<2> > threshs3_m_threshold_address0;
sc_out< sc_logic > threshs3_m_threshold_ce0;
sc_out< sc_lv<16> > threshs3_m_threshold_d0;
sc_in< sc_lv<16> > threshs3_m_threshold_q0;
sc_out< sc_logic > threshs3_m_threshold_we0;
sc_out< sc_lv<2> > threshs3_m_threshold_address1;
sc_out< sc_logic > threshs3_m_threshold_ce1;
sc_out< sc_lv<16> > threshs3_m_threshold_d1;
sc_in< sc_lv<16> > threshs3_m_threshold_q1;
sc_out< sc_logic > threshs3_m_threshold_we1;
sc_out< sc_lv<2> > threshs3_m_threshold_13_address0;
sc_out< sc_logic > threshs3_m_threshold_13_ce0;
sc_out< sc_lv<16> > threshs3_m_threshold_13_d0;
sc_in< sc_lv<16> > threshs3_m_threshold_13_q0;
sc_out< sc_logic > threshs3_m_threshold_13_we0;
sc_out< sc_lv<2> > threshs3_m_threshold_13_address1;
sc_out< sc_logic > threshs3_m_threshold_13_ce1;
sc_out< sc_lv<16> > threshs3_m_threshold_13_d1;
sc_in< sc_lv<16> > threshs3_m_threshold_13_q1;
sc_out< sc_logic > threshs3_m_threshold_13_we1;
sc_out< sc_lv<2> > threshs3_m_threshold_12_address0;
sc_out< sc_logic > threshs3_m_threshold_12_ce0;
sc_out< sc_lv<16> > threshs3_m_threshold_12_d0;
sc_in< sc_lv<16> > threshs3_m_threshold_12_q0;
sc_out< sc_logic > threshs3_m_threshold_12_we0;
sc_out< sc_lv<2> > threshs3_m_threshold_12_address1;
sc_out< sc_logic > threshs3_m_threshold_12_ce1;
sc_out< sc_lv<16> > threshs3_m_threshold_12_d1;
sc_in< sc_lv<16> > threshs3_m_threshold_12_q1;
sc_out< sc_logic > threshs3_m_threshold_12_we1;
sc_out< sc_lv<2> > threshs3_m_threshold_11_address0;
sc_out< sc_logic > threshs3_m_threshold_11_ce0;
sc_out< sc_lv<16> > threshs3_m_threshold_11_d0;
sc_in< sc_lv<16> > threshs3_m_threshold_11_q0;
sc_out< sc_logic > threshs3_m_threshold_11_we0;
sc_out< sc_lv<2> > threshs3_m_threshold_11_address1;
sc_out< sc_logic > threshs3_m_threshold_11_ce1;
sc_out< sc_lv<16> > threshs3_m_threshold_11_d1;
sc_in< sc_lv<16> > threshs3_m_threshold_11_q1;
sc_out< sc_logic > threshs3_m_threshold_11_we1;
sc_out< sc_lv<2> > threshs3_m_threshold_10_address0;
sc_out< sc_logic > threshs3_m_threshold_10_ce0;
sc_out< sc_lv<16> > threshs3_m_threshold_10_d0;
sc_in< sc_lv<16> > threshs3_m_threshold_10_q0;
sc_out< sc_logic > threshs3_m_threshold_10_we0;
sc_out< sc_lv<2> > threshs3_m_threshold_10_address1;
sc_out< sc_logic > threshs3_m_threshold_10_ce1;
sc_out< sc_lv<16> > threshs3_m_threshold_10_d1;
sc_in< sc_lv<16> > threshs3_m_threshold_10_q1;
sc_out< sc_logic > threshs3_m_threshold_10_we1;
sc_out< sc_lv<2> > threshs3_m_threshold_9_address0;
sc_out< sc_logic > threshs3_m_threshold_9_ce0;
sc_out< sc_lv<16> > threshs3_m_threshold_9_d0;
sc_in< sc_lv<16> > threshs3_m_threshold_9_q0;
sc_out< sc_logic > threshs3_m_threshold_9_we0;
sc_out< sc_lv<2> > threshs3_m_threshold_9_address1;
sc_out< sc_logic > threshs3_m_threshold_9_ce1;
sc_out< sc_lv<16> > threshs3_m_threshold_9_d1;
sc_in< sc_lv<16> > threshs3_m_threshold_9_q1;
sc_out< sc_logic > threshs3_m_threshold_9_we1;
sc_out< sc_lv<2> > threshs3_m_threshold_8_address0;
sc_out< sc_logic > threshs3_m_threshold_8_ce0;
sc_out< sc_lv<16> > threshs3_m_threshold_8_d0;
sc_in< sc_lv<16> > threshs3_m_threshold_8_q0;
sc_out< sc_logic > threshs3_m_threshold_8_we0;
sc_out< sc_lv<2> > threshs3_m_threshold_8_address1;
sc_out< sc_logic > threshs3_m_threshold_8_ce1;
sc_out< sc_lv<16> > threshs3_m_threshold_8_d1;
sc_in< sc_lv<16> > threshs3_m_threshold_8_q1;
sc_out< sc_logic > threshs3_m_threshold_8_we1;
sc_in_clk ap_clk;
sc_in< sc_logic > ap_rst;
sc_in< sc_logic > in_V1_ap_vld;
sc_in< sc_logic > numReps_ap_vld;
sc_in< sc_logic > out_V3_ap_vld;
sc_out< sc_logic > ap_done;
sc_in< sc_logic > ap_start;
sc_out< sc_logic > ap_ready;
sc_out< sc_logic > ap_idle;
sc_in< sc_logic > ap_continue;
sc_signal< sc_logic > ap_var_for_const0;
sc_signal< sc_lv<64> > ap_var_for_const3;
sc_signal< sc_lv<2> > ap_var_for_const1;
sc_signal< sc_logic > ap_var_for_const4;
sc_signal< sc_lv<1> > ap_var_for_const2;
// Module declarations
DoCompute(sc_module_name name);
SC_HAS_PROCESS(DoCompute);
~DoCompute();
sc_trace_file* mVcdFile;
Mem2Stream_Batch12* Mem2Stream_Batch12_U0;
Matrix_Vector_Activa* Matrix_Vector_Activa_U0;
Matrix_Vector_Activa_3* Matrix_Vector_Activa_3_U0;
Matrix_Vector_Activa_2* Matrix_Vector_Activa_2_U0;
StreamingDataWidthCo* StreamingDataWidthCo_U0;
Matrix_Vector_Activa_1* Matrix_Vector_Activa_1_U0;
StreamingDataWidthCo_1* StreamingDataWidthCo_1_U0;
Stream2Mem_Batch* Stream2Mem_Batch_U0;
DoCompute_memInSthbi* memInStrm_V_V_U;
DoCompute_numRepsibs* numReps_channel_U;
DoCompute_out_V3_jbC* out_V3_channel_U;
DoCompute_inter0_kbM* inter0_V_V_U;
DoCompute_numRepslbW* numReps_channel17_U;
DoCompute_inter1_mb6* inter1_V_V_U;
DoCompute_numRepsncg* numReps_channel18_U;
DoCompute_inter2_ocq* inter2_V_V_U;
DoCompute_numRepspcA* numReps_channel19_U;
DoCompute_wa_in_mqcK* wa_in_m_target_V_V_U;
DoCompute_numRepsrcU* numReps_channel20_U;
DoCompute_wa_out_sc4* wa_out_m_buffer_V_V_U;
DoCompute_numRepstde* numReps_channel21_U;
DoCompute_memOutSudo* memOutStrm_V_V_U;
DoCompute_numRepsvdy* numReps_channel22_U;
start_for_StreamiwdI* start_for_StreamiwdI_U;
start_for_StreamixdS* start_for_StreamixdS_U;
sc_signal< sc_logic > Mem2Stream_Batch12_U0_ap_start;
sc_signal< sc_logic > Mem2Stream_Batch12_U0_ap_done;
sc_signal< sc_logic > Mem2Stream_Batch12_U0_ap_continue;
sc_signal< sc_logic > Mem2Stream_Batch12_U0_ap_idle;
sc_signal< sc_logic > Mem2Stream_Batch12_U0_ap_ready;
sc_signal< sc_logic > Mem2Stream_Batch12_U0_m_axi_in_V_AWVALID;
sc_signal< sc_lv<64> > Mem2Stream_Batch12_U0_m_axi_in_V_AWADDR;
sc_signal< sc_lv<1> > Mem2Stream_Batch12_U0_m_axi_in_V_AWID;
sc_signal< sc_lv<32> > Mem2Stream_Batch12_U0_m_axi_in_V_AWLEN;
sc_signal< sc_lv<3> > Mem2Stream_Batch12_U0_m_axi_in_V_AWSIZE;
sc_signal< sc_lv<2> > Mem2Stream_Batch12_U0_m_axi_in_V_AWBURST;
sc_signal< sc_lv<2> > Mem2Stream_Batch12_U0_m_axi_in_V_AWLOCK;
sc_signal< sc_lv<4> > Mem2Stream_Batch12_U0_m_axi_in_V_AWCACHE;
sc_signal< sc_lv<3> > Mem2Stream_Batch12_U0_m_axi_in_V_AWPROT;
sc_signal< sc_lv<4> > Mem2Stream_Batch12_U0_m_axi_in_V_AWQOS;
sc_signal< sc_lv<4> > Mem2Stream_Batch12_U0_m_axi_in_V_AWREGION;
sc_signal< sc_lv<1> > Mem2Stream_Batch12_U0_m_axi_in_V_AWUSER;
sc_signal< sc_logic > Mem2Stream_Batch12_U0_m_axi_in_V_WVALID;
sc_signal< sc_lv<64> > Mem2Stream_Batch12_U0_m_axi_in_V_WDATA;
sc_signal< sc_lv<8> > Mem2Stream_Batch12_U0_m_axi_in_V_WSTRB;
sc_signal< sc_logic > Mem2Stream_Batch12_U0_m_axi_in_V_WLAST;
sc_signal< sc_lv<1> > Mem2Stream_Batch12_U0_m_axi_in_V_WID;
sc_signal< sc_lv<1> > Mem2Stream_Batch12_U0_m_axi_in_V_WUSER;
sc_signal< sc_logic > Mem2Stream_Batch12_U0_m_axi_in_V_ARVALID;
sc_signal< sc_lv<64> > Mem2Stream_Batch12_U0_m_axi_in_V_ARADDR;
sc_signal< sc_lv<1> > Mem2Stream_Batch12_U0_m_axi_in_V_ARID;
sc_signal< sc_lv<32> > Mem2Stream_Batch12_U0_m_axi_in_V_ARLEN;
sc_signal< sc_lv<3> > Mem2Stream_Batch12_U0_m_axi_in_V_ARSIZE;
sc_signal< sc_lv<2> > Mem2Stream_Batch12_U0_m_axi_in_V_ARBURST;
sc_signal< sc_lv<2> > Mem2Stream_Batch12_U0_m_axi_in_V_ARLOCK;
sc_signal< sc_lv<4> > Mem2Stream_Batch12_U0_m_axi_in_V_ARCACHE;
sc_signal< sc_lv<3> > Mem2Stream_Batch12_U0_m_axi_in_V_ARPROT;
sc_signal< sc_lv<4> > Mem2Stream_Batch12_U0_m_axi_in_V_ARQOS;
sc_signal< sc_lv<4> > Mem2Stream_Batch12_U0_m_axi_in_V_ARREGION;
sc_signal< sc_lv<1> > Mem2Stream_Batch12_U0_m_axi_in_V_ARUSER;
sc_signal< sc_logic > Mem2Stream_Batch12_U0_m_axi_in_V_RREADY;
sc_signal< sc_logic > Mem2Stream_Batch12_U0_m_axi_in_V_BREADY;
sc_signal< sc_lv<64> > Mem2Stream_Batch12_U0_memInStrm_V_V_din;
sc_signal< sc_logic > Mem2Stream_Batch12_U0_memInStrm_V_V_write;
sc_signal< sc_lv<32> > Mem2Stream_Batch12_U0_numReps_channel_din;
sc_signal< sc_logic > Mem2Stream_Batch12_U0_numReps_channel_write;
sc_signal< sc_lv<61> > Mem2Stream_Batch12_U0_out_V3_out_din;
sc_signal< sc_logic > Mem2Stream_Batch12_U0_out_V3_out_write;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_ap_start;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_ap_done;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_ap_continue;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_ap_idle;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_ap_ready;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_in_V_V_read;
sc_signal< sc_lv<32> > Matrix_Vector_Activa_U0_out_V_V_din;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_out_V_V_write;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_reps_read;
sc_signal< sc_lv<32> > Matrix_Vector_Activa_U0_reps_out_din;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_reps_out_write;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_U0_weights0_m_weights_V_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_weights0_m_weights_V_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_U0_weights0_m_weights_V_1_address0;
sc_signal< s
|
c_logic > Matrix_Vector_Activa_U0_weights0_m_weights_V_1_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_U0_weights0_m_weights_V_2_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_weights0_m_weights_V_2_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_U0_weights0_m_weights_V_3_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_weights0_m_weights_V_3_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_U0_weights0_m_weights_V_4_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_weights0_m_weights_V_4_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_U0_weights0_m_weights_V_5_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_weights0_m_weights_V_5_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_U0_weights0_m_weights_V_6_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_weights0_m_weights_V_6_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_U0_weights0_m_weights_V_7_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_weights0_m_weights_V_7_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_U0_weights0_m_weights_V_8_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_weights0_m_weights_V_8_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_U0_weights0_m_weights_V_9_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_weights0_m_weights_V_9_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_U0_weights0_m_weights_V_10_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_weights0_m_weights_V_10_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_U0_weights0_m_weights_V_11_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_weights0_m_weights_V_11_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_U0_weights0_m_weights_V_12_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_weights0_m_weights_V_12_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_U0_weights0_m_weights_V_13_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_weights0_m_weights_V_13_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_U0_weights0_m_weights_V_14_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_weights0_m_weights_V_14_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_U0_weights0_m_weights_V_15_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_weights0_m_weights_V_15_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_U0_weights0_m_weights_V_16_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_weights0_m_weights_V_16_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_U0_weights0_m_weights_V_17_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_weights0_m_weights_V_17_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_U0_weights0_m_weights_V_18_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_weights0_m_weights_V_18_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_U0_weights0_m_weights_V_19_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_weights0_m_weights_V_19_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_U0_weights0_m_weights_V_20_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_weights0_m_weights_V_20_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_U0_weights0_m_weights_V_21_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_weights0_m_weights_V_21_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_U0_weights0_m_weights_V_22_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_weights0_m_weights_V_22_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_U0_weights0_m_weights_V_23_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_weights0_m_weights_V_23_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_U0_weights0_m_weights_V_24_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_weights0_m_weights_V_24_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_U0_weights0_m_weights_V_25_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_weights0_m_weights_V_25_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_U0_weights0_m_weights_V_26_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_weights0_m_weights_V_26_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_U0_weights0_m_weights_V_27_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_weights0_m_weights_V_27_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_U0_weights0_m_weights_V_28_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_weights0_m_weights_V_28_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_U0_weights0_m_weights_V_29_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_weights0_m_weights_V_29_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_U0_weights0_m_weights_V_30_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_weights0_m_weights_V_30_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_U0_weights0_m_weights_V_31_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_weights0_m_weights_V_31_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_U0_threshs0_m_threshold_31_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_threshs0_m_threshold_31_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_U0_threshs0_m_threshold_30_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_threshs0_m_threshold_30_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_U0_threshs0_m_threshold_19_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_threshs0_m_threshold_19_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_U0_threshs0_m_threshold_8_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_threshs0_m_threshold_8_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_U0_threshs0_m_threshold_5_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_threshs0_m_threshold_5_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_U0_threshs0_m_threshold_4_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_threshs0_m_threshold_4_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_U0_threshs0_m_threshold_3_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_threshs0_m_threshold_3_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_U0_threshs0_m_threshold_2_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_threshs0_m_threshold_2_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_U0_threshs0_m_threshold_1_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_threshs0_m_threshold_1_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_U0_threshs0_m_threshold_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_threshs0_m_threshold_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_U0_threshs0_m_threshold_29_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_threshs0_m_threshold_29_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_U0_threshs0_m_threshold_28_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_threshs0_m_threshold_28_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_U0_threshs0_m_threshold_27_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_threshs0_m_threshold_27_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_U0_threshs0_m_threshold_26_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_threshs0_m_threshold_26_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_U0_threshs0_m_threshold_25_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_threshs0_m_threshold_25_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_U0_threshs0_m_threshold_24_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_threshs0_m_threshold_24_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_U0_threshs0_m_threshold_23_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_threshs0_m_threshold_23_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_U0_threshs0_m_threshold_22_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_threshs0_m_threshold_22_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_U0_threshs0_m_threshold_21_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_threshs0_m_threshold_21_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_U0_threshs0_m_threshold_20_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_threshs0_m_threshold_20_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_U0_threshs0_m_threshold_18_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_threshs0_m_threshold_18_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_U0_threshs0_m_threshold_17_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_threshs0_m_threshold_17_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_U0_threshs0_m_threshold_16_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_threshs0_m_threshold_16_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_U0_threshs0_m_threshold_15_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_threshs0_m_threshold_15_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_U0_threshs0_m_threshold_14_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_threshs0_m_threshold_14_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_U0_threshs0_m_threshold_13_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_threshs0_m_threshold_13_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_U0_threshs0_m_threshold_12_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_threshs0_m_threshold_12_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_U0_threshs0_m_threshold_11_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_threshs0_m_threshold_11_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_U0_threshs0_m_threshold_10_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_threshs0_m_threshold_10_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_U0_threshs0_m_threshold_9_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_threshs0_m_threshold_9_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_U0_threshs0_m_threshold_7_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_threshs0_m_threshold_7_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_U0_threshs0_m_threshold_6_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_U0_threshs0_m_threshold_6_ce0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_ap_start;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_ap_done;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_ap_continue;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_ap_idle;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_ap_ready;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_in_V_V_read;
sc_signal< sc_lv<64> > Matrix_Vector_Activa_3_U0_out_V_V_din;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_out_V_V_write;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_reps_read;
sc_signal< sc_lv<32> > Matrix_Vector_Activa_3_U0_reps_out_din;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_reps_out_write;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_1_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_1_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_2_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_2_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_3_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_3_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_4_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_4_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_5_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_5_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_6_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_6_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_7_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_7_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_8_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_8_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_9_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_9_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_10_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_10_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_11_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_11_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_12_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_12_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_13_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_13_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_14_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_14_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_15_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_15_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_16_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_16_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_17_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_17_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_18_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_18_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_19_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_19_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_20_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_20_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_21_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_21_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_22_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_22_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_23_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_23_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_24_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_24_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_25_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_25_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_26_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_26_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_27_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_27_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_28_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_28_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_29_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_29_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_30_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_30_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_31_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_31_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_32_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_32_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_33_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_33_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_34_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_34_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_35_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_35_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_36_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_36_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_37_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_37_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_38_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_38_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_39_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_39_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_40_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_40_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_41_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_41_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_42_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_42_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_43_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_43_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_44_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_44_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_45_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_45_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_46_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_46_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_47_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_47_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_48_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_48_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_49_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_49_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_50_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_50_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_51_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_51_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_52_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_52_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_53_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_53_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_54_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_54_ce0;
|
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_55_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_55_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_56_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_56_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_57_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_57_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_58_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_58_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_59_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_59_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_60_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_60_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_61_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_61_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_62_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_62_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_63_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_weights1_m_weights_V_63_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_63_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_63_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_62_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_62_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_51_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_51_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_40_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_40_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_29_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_29_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_18_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_18_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_7_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_7_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_2_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_2_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_1_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_1_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_61_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_61_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_60_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_60_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_59_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_59_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_58_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_58_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_57_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_57_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_56_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_56_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_55_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_55_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_54_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_54_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_53_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_53_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_52_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_52_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_50_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_50_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_49_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_49_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_48_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_48_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_47_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_47_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_46_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_46_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_45_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_45_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_44_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_44_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_43_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_43_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_42_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_42_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_41_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_41_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_39_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_39_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_38_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_38_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_37_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_37_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_36_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_36_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_35_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_35_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_34_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_34_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_33_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_33_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_32_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_32_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_31_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_31_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_30_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_30_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_28_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_28_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_27_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_27_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_26_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_26_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_25_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_25_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_24_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_24_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_23_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_23_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_22_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_22_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_21_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_21_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_20_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_20_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_19_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_19_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_17_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_17_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_16_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_16_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_15_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_15_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_14_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_14_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_13_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_13_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_12_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_12_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_11_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_11_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_10_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_10_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_9_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_9_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_8_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_8_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_6_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_6_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_5_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_5_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_4_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_4_ce0;
sc_signal< sc_lv<4> > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_3_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_3_U0_threshs1_m_threshold_3_ce0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_ap_start;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_ap_ready;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_ap_done;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_ap_continue;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_ap_idle;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_start_out;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_start_write;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_in_V_V_read;
sc_signal< sc_lv<32> > Matrix_Vector_Activa_2_U0_out_V_V_din;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_out_V_V_write;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_reps_read;
sc_signal< sc_lv<32> > Matrix_Vector_Activa_2_U0_reps_out_din;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_reps_out_write;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_1_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_1_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_2_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_2_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_3_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_3_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_4_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_4_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_5_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_5_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_6_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_6_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_7_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_7_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_8_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_8_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_9_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_9_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_10_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_10_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_11_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_11_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_12_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_12_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_13_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_13_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_14_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_14_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_15_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_15_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_16_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_16_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_17_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_17_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_18_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_18_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_19_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_19_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_20_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_20_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_21_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_21_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_22_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_22_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_23_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_23_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_24_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_24_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_25_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_25_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_26_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_26_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_27_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_27_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_28_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_28_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_29_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_29_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_30_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_30_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_31_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_weights2_m_weights_V_31_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_31_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_31_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_30_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_30_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_19_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_19_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_8_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_8_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_5_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_5_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_4_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_4_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_3_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_3_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_2_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_2_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_1_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_1_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_ce0;
sc_signal< sc_lv<5> > Matr
|
ix_Vector_Activa_2_U0_threshs2_m_threshold_29_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_29_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_28_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_28_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_27_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_27_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_26_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_26_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_25_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_25_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_24_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_24_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_23_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_23_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_22_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_22_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_21_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_21_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_20_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_20_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_18_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_18_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_17_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_17_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_16_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_16_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_15_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_15_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_14_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_14_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_13_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_13_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_12_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_12_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_11_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_11_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_10_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_10_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_9_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_9_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_7_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_7_ce0;
sc_signal< sc_lv<5> > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_6_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_2_U0_threshs2_m_threshold_6_ce0;
sc_signal< sc_logic > StreamingDataWidthCo_U0_ap_start;
sc_signal< sc_logic > StreamingDataWidthCo_U0_ap_done;
sc_signal< sc_logic > StreamingDataWidthCo_U0_ap_continue;
sc_signal< sc_logic > StreamingDataWidthCo_U0_ap_idle;
sc_signal< sc_logic > StreamingDataWidthCo_U0_ap_ready;
sc_signal< sc_logic > StreamingDataWidthCo_U0_in_V_V_read;
sc_signal< sc_lv<8> > StreamingDataWidthCo_U0_out_V_V_din;
sc_signal< sc_logic > StreamingDataWidthCo_U0_out_V_V_write;
sc_signal< sc_logic > StreamingDataWidthCo_U0_numReps_read;
sc_signal< sc_lv<32> > StreamingDataWidthCo_U0_numReps_out_din;
sc_signal< sc_logic > StreamingDataWidthCo_U0_numReps_out_write;
sc_signal< sc_logic > Matrix_Vector_Activa_1_U0_ap_start;
sc_signal< sc_logic > Matrix_Vector_Activa_1_U0_ap_ready;
sc_signal< sc_logic > Matrix_Vector_Activa_1_U0_ap_done;
sc_signal< sc_logic > Matrix_Vector_Activa_1_U0_ap_continue;
sc_signal< sc_logic > Matrix_Vector_Activa_1_U0_ap_idle;
sc_signal< sc_logic > Matrix_Vector_Activa_1_U0_start_out;
sc_signal< sc_logic > Matrix_Vector_Activa_1_U0_start_write;
sc_signal< sc_logic > Matrix_Vector_Activa_1_U0_in_V_V_read;
sc_signal< sc_lv<16> > Matrix_Vector_Activa_1_U0_out_V_V_din;
sc_signal< sc_logic > Matrix_Vector_Activa_1_U0_out_V_V_write;
sc_signal< sc_logic > Matrix_Vector_Activa_1_U0_reps_read;
sc_signal< sc_lv<32> > Matrix_Vector_Activa_1_U0_reps_out_din;
sc_signal< sc_logic > Matrix_Vector_Activa_1_U0_reps_out_write;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_1_U0_weights3_m_weights_V_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_1_U0_weights3_m_weights_V_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_1_U0_weights3_m_weights_V_1_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_1_U0_weights3_m_weights_V_1_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_1_U0_weights3_m_weights_V_2_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_1_U0_weights3_m_weights_V_2_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_1_U0_weights3_m_weights_V_3_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_1_U0_weights3_m_weights_V_3_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_1_U0_weights3_m_weights_V_4_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_1_U0_weights3_m_weights_V_4_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_1_U0_weights3_m_weights_V_5_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_1_U0_weights3_m_weights_V_5_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_1_U0_weights3_m_weights_V_6_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_1_U0_weights3_m_weights_V_6_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_1_U0_weights3_m_weights_V_7_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_1_U0_weights3_m_weights_V_7_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_1_U0_weights3_m_weights_V_8_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_1_U0_weights3_m_weights_V_8_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_1_U0_weights3_m_weights_V_9_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_1_U0_weights3_m_weights_V_9_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_1_U0_weights3_m_weights_V_10_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_1_U0_weights3_m_weights_V_10_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_1_U0_weights3_m_weights_V_11_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_1_U0_weights3_m_weights_V_11_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_1_U0_weights3_m_weights_V_12_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_1_U0_weights3_m_weights_V_12_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_1_U0_weights3_m_weights_V_13_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_1_U0_weights3_m_weights_V_13_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_1_U0_weights3_m_weights_V_14_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_1_U0_weights3_m_weights_V_14_ce0;
sc_signal< sc_lv<9> > Matrix_Vector_Activa_1_U0_weights3_m_weights_V_15_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_1_U0_weights3_m_weights_V_15_ce0;
sc_signal< sc_lv<2> > Matrix_Vector_Activa_1_U0_threshs3_m_threshold_15_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_1_U0_threshs3_m_threshold_15_ce0;
sc_signal< sc_lv<2> > Matrix_Vector_Activa_1_U0_threshs3_m_threshold_14_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_1_U0_threshs3_m_threshold_14_ce0;
sc_signal< sc_lv<2> > Matrix_Vector_Activa_1_U0_threshs3_m_threshold_7_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_1_U0_threshs3_m_threshold_7_ce0;
sc_signal< sc_lv<2> > Matrix_Vector_Activa_1_U0_threshs3_m_threshold_6_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_1_U0_threshs3_m_threshold_6_ce0;
sc_signal< sc_lv<2> > Matrix_Vector_Activa_1_U0_threshs3_m_threshold_5_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_1_U0_threshs3_m_threshold_5_ce0;
sc_signal< sc_lv<2> > Matrix_Vector_Activa_1_U0_threshs3_m_threshold_4_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_1_U0_threshs3_m_threshold_4_ce0;
sc_signal< sc_lv<2> > Matrix_Vector_Activa_1_U0_threshs3_m_threshold_3_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_1_U0_threshs3_m_threshold_3_ce0;
sc_signal< sc_lv<2> > Matrix_Vector_Activa_1_U0_threshs3_m_threshold_2_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_1_U0_threshs3_m_threshold_2_ce0;
sc_signal< sc_lv<2> > Matrix_Vector_Activa_1_U0_threshs3_m_threshold_1_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_1_U0_threshs3_m_threshold_1_ce0;
sc_signal< sc_lv<2> > Matrix_Vector_Activa_1_U0_threshs3_m_threshold_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_1_U0_threshs3_m_threshold_ce0;
sc_signal< sc_lv<2> > Matrix_Vector_Activa_1_U0_threshs3_m_threshold_13_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_1_U0_threshs3_m_threshold_13_ce0;
sc_signal< sc_lv<2> > Matrix_Vector_Activa_1_U0_threshs3_m_threshold_12_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_1_U0_threshs3_m_threshold_12_ce0;
sc_signal< sc_lv<2> > Matrix_Vector_Activa_1_U0_threshs3_m_threshold_11_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_1_U0_threshs3_m_threshold_11_ce0;
sc_signal< sc_lv<2> > Matrix_Vector_Activa_1_U0_threshs3_m_threshold_10_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_1_U0_threshs3_m_threshold_10_ce0;
sc_signal< sc_lv<2> > Matrix_Vector_Activa_1_U0_threshs3_m_threshold_9_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_1_U0_threshs3_m_threshold_9_ce0;
sc_signal< sc_lv<2> > Matrix_Vector_Activa_1_U0_threshs3_m_threshold_8_address0;
sc_signal< sc_logic > Matrix_Vector_Activa_1_U0_threshs3_m_threshold_8_ce0;
sc_signal< sc_logic > StreamingDataWidthCo_1_U0_ap_start;
sc_signal< sc_logic > StreamingDataWidthCo_1_U0_ap_done;
sc_signal< sc_logic > StreamingDataWidthCo_1_U0_ap_continue;
sc_signal< sc_logic > StreamingDataWidthCo_1_U0_ap_idle;
sc_signal< sc_logic > StreamingDataWidthCo_1_U0_ap_ready;
sc_signal< sc_logic > StreamingDataWidthCo_1_U0_in_V_V_read;
sc_signal< sc_lv<64> > StreamingDataWidthCo_1_U0_out_V_V_din;
sc_signal< sc_logic > StreamingDataWidthCo_1_U0_out_V_V_write;
sc_signal< sc_logic > StreamingDataWidthCo_1_U0_numReps_read;
sc_signal< sc_lv<32> > StreamingDataWidthCo_1_U0_numReps_out_din;
sc_signal< sc_logic > StreamingDataWidthCo_1_U0_numReps_out_write;
sc_signal< sc_logic > Stream2Mem_Batch_U0_ap_start;
sc_signal< sc_logic > Stream2Mem_Batch_U0_ap_done;
sc_signal< sc_logic > Stream2Mem_Batch_U0_ap_continue;
sc_signal< sc_logic > Stream2Mem_Batch_U0_ap_idle;
sc_signal< sc_logic > Stream2Mem_Batch_U0_ap_ready;
sc_signal< sc_logic > Stream2Mem_Batch_U0_memOutStrm_V_V_read;
sc_signal< sc_logic > Stream2Mem_Batch_U0_m_axi_in_V_AWVALID;
sc_signal< sc_lv<64> > Stream2Mem_Batch_U0_m_axi_in_V_AWADDR;
sc_signal< sc_lv<1> > Stream2Mem_Batch_U0_m_axi_in_V_AWID;
sc_signal< sc_lv<32> > Stream2Mem_Batch_U0_m_axi_in_V_AWLEN;
sc_signal< sc_lv<3> > Stream2Mem_Batch_U0_m_axi_in_V_AWSIZE;
sc_signal< sc_lv<2> > Stream2Mem_Batch_U0_m_axi_in_V_AWBURST;
sc_signal< sc_lv<2> > Stream2Mem_Batch_U0_m_axi_in_V_AWLOCK;
sc_signal< sc_lv<4> > Stream2Mem_Batch_U0_m_axi_in_V_AWCACHE;
sc_signal< sc_lv<3> > Stream2Mem_Batch_U0_m_axi_in_V_AWPROT;
sc_signal< sc_lv<4> > Stream2Mem_Batch_U0_m_axi_in_V_AWQOS;
sc_signal< sc_lv<4> > Stream2Mem_Batch_U0_m_axi_in_V_AWREGION;
sc_signal< sc_lv<1> > Stream2Mem_Batch_U0_m_axi_in_V_AWUSER;
sc_signal< sc_logic > Stream2Mem_Batch_U0_m_axi_in_V_WVALID;
sc_signal< sc_lv<64> > Stream2Mem_Batch_U0_m_axi_in_V_WDATA;
sc_signal< sc_lv<8> > Stream2Mem_Batch_U0_m_axi_in_V_WSTRB;
sc_signal< sc_logic > Stream2Mem_Batch_U0_m_axi_in_V_WLAST;
sc_signal< sc_lv<1> > Stream2Mem_Batch_U0_m_axi_in_V_WID;
sc_signal< sc_lv<1> > Stream2Mem_Batch_U0_m_axi_in_V_WUSER;
sc_signal< sc_logic > Stream2Mem_Batch_U0_m_axi_in_V_ARVALID;
sc_signal< sc_lv<64> > Stream2Mem_Batch_U0_m_axi_in_V_ARADDR;
sc_signal< sc_lv<1> > Stream2Mem_Batch_U0_m_axi_in_V_ARID;
sc_signal< sc_lv<32> > Stream2Mem_Batch_U0_m_axi_in_V_ARLEN;
sc_signal< sc_lv<3> > Stream2Mem_Batch_U0_m_axi_in_V_ARSIZE;
sc_signal< sc_lv<2> > Stream2Mem_Batch_U0_m_axi_in_V_ARBURST;
sc_signal< sc_lv<2> > Stream2Mem_Batch_U0_m_axi_in_V_ARLOCK;
sc_signal< sc_lv<4> > Stream2Mem_Batch_U0_m_axi_in_V_ARCACHE;
sc_signal< sc_lv<3> > Stream2Mem_Batch_U0_m_axi_in_V_ARPROT;
sc_signal< sc_lv<4> > Stream2Mem_Batch_U0_m_axi_in_V_ARQOS;
sc_signal< sc_lv<4> > Stream2Mem_Batch_U0_m_axi_in_V_ARREGION;
sc_signal< sc_lv<1> > Stream2Mem_Batch_U0_m_axi_in_V_ARUSER;
sc_signal< sc_logic > Stream2Mem_Batch_U0_m_axi_in_V_RREADY;
sc_signal< sc_logic > Stream2Mem_Batch_U0_m_axi_in_V_BREADY;
sc_signal< sc_logic > Stream2Mem_Batch_U0_out_V3_read;
sc_signal< sc_logic > Stream2Mem_Batch_U0_numReps_channel22_read;
sc_signal< sc_logic > ap_hs_continue;
sc_signal< sc_logic > memInStrm_V_V_full_n;
sc_signal< sc_lv<64> > memInStrm_V_V_dout;
sc_signal< sc_logic > memInStrm_V_V_empty_n;
sc_signal< sc_logic > numReps_channel_full_n;
sc_signal< sc_lv<32> > numReps_channel_dout;
sc_signal< sc_logic > numReps_channel_empty_n;
sc_signal< sc_logic > out_V3_channel_full_n;
sc_signal< sc_lv<61> > out_V3_channel_dout;
sc_signal< sc_logic > out_V3_channel_empty_n;
sc_signal< sc_logic > inter0_V_V_full_n;
sc_signal< sc_lv<32> > inter0_V_V_dout;
sc_signal< sc_logic > inter0_V_V_empty_n;
sc_signal< sc_logic > numReps_channel17_full_n;
sc_signal< sc_lv<32> > numReps_channel17_dout;
sc_signal< sc_logic > numReps_channel17_empty_n;
sc_signal< sc_logic > inter1_V_V_full_n;
sc_signal< sc_lv<64> > inter1_V_V_dout;
sc_signal< sc_logic > inter1_V_V_empty_n;
sc_signal< sc_logic > numReps_channel18_full_n;
sc_signal< sc_lv<32> > numReps_channel18_dout;
sc_signal< sc_logic > numReps_channel18_empty_n;
sc_signal< sc_logic > inter2_V_V_full_n;
sc_signal< sc_lv<32> > inter2_V_V_dout;
sc_signal< sc_logic > inter2_V_V_empty_n;
sc_signal< sc_logic > numReps_channel19_full_n;
sc_signal< sc_lv<32> > numReps_channel19_dout;
sc_signal< sc_logic > numReps_channel19_empty_n;
sc_signal< sc_logic > wa_in_m_target_V_V_full_n;
sc_signal< sc_lv<8> > wa_in_m_target_V_V_dout;
sc_signal< sc_logic > wa_in_m_target_V_V_empty_n;
sc_signal< sc_logic > numReps_channel20_full_n;
sc_signal< sc_lv<32> > numReps_channel20_dout;
sc_signal< sc_logic > numReps_channel20_empty_n;
sc_signal< sc_logic > wa_out_m_buffer_V_V_full_n;
sc_signal< sc_lv<16> > wa_out_m_buffer_V_V_dout;
sc_signal< sc_logic > wa_out_m_buffer_V_V_empty_n;
sc_signal< sc_logic > numReps_channel21_full_n;
sc_signal< sc_lv<32> > numReps_channel21_dout;
sc_signal< sc_logic > numReps_channel21_empty_n;
sc_signal< sc_logic > memOutStrm_V_V_full_n;
sc_signal< sc_lv<64> > memOutStrm_V_V_dout;
sc_signal< sc_logic > memOutStrm_V_V_empty_n;
sc_signal< sc_logic > numReps_channel22_full_n;
sc_signal< sc_lv<32> > numReps_channel22_dout;
sc_signal< sc_logic > numReps_channel22_empty_n;
sc_signal< sc_logic > ap_hs_done;
sc_signal< sc_logic > ap_hs_ready;
sc_signal< sc_logic > ap_sync_reg_Mem2Stream_Batch12_U0_ap_ready;
sc_signal< sc_logic > ap_sync_Mem2Stream_Batch12_U0_ap_ready;
sc_signal< sc_logic > ap_sync_reg_Matrix_Vector_Activa_U0_ap_ready;
sc_signal< sc_logic > ap_sync_Matrix_Vector_Activa_U0_ap_ready;
sc_signal< sc_logic > ap_sync_reg_Matrix_Vector_Activa_3_U0_ap_ready;
sc_signal< sc_logic > ap_sync_Matrix_Vector_Activa_3_U0_ap_ready;
sc_signal< sc_logic > ap_sync_reg_Matrix_Vector_Activa_2_U0_ap_ready;
sc_signal< sc_logic > ap_sync_Matrix_Vector_Activa_2_U0_ap_ready;
sc_signal< sc_logic > ap_sync_reg_Matrix_Vector_Activa_1_U0_ap_ready;
sc_signal< sc_logic > ap_sync_Matrix_Vector_Activa_1_U0_ap_ready;
sc_signal< sc_logic > ap_sync_Mem2Stream_Batch12_U0_ap_start;
sc_signal< sc_logic > ap_sync_Matrix_Vector_Activa_U0_ap_start;
sc_signal< sc_logic > ap_sync_Matrix_Vector_Activa_3_U0_ap_start;
sc_signal< sc_logic > ap_sync_Matrix_Vector_Activa_2_U0_ap_start;
sc_signal< sc_logic > ap_sync_Matrix_Vector_Activa_1_U0_ap_start;
sc_signal< sc_lv<1> > start_for_StreamingDataWidthCo_U0_din;
sc_signal< sc_logic > start_for_StreamingDataWidthCo_U0_full_n;
sc_signal< sc_lv<1> > start_for_StreamingDataWidthCo_U0_dout;
sc_signal< sc_logic > start_for_StreamingDataWidthCo_U0_empty_n;
sc_signal< sc_lv<1> > start_for_StreamingDataWidthCo_1_U0_din;
sc_signal< sc_logic > start_for_StreamingDataWidthCo_1_U0_full_n;
sc_signal< sc_lv<1> > start_for_StreamingDataWidthCo_1_U0_dout;
sc_signal< sc_logic > start_for_StreamingDataWidthCo_1_U0_empty_n;
static const sc_lv<9> ap_const_lv9_0;
static const sc_logic ap_const_logic_0;
static const sc_lv<64> ap_const_lv64_0;
static const sc_lv<5> ap_const_lv5_0;
static const sc_lv<16> ap_const_lv16_0;
static const sc_lv<32> ap_const_lv32_0;
static const sc_lv<4> ap_const_lv4_0;
static const sc_lv<8> ap_const_lv8_0;
static const sc_lv<2> ap_const_lv2_0;
static const sc_logic ap_const_logic_1;
static const sc_lv<2> ap_const_lv2_1;
static const sc_lv<1> ap_const_lv1_0;
static const sc_lv<1> ap_const_lv1_1;
static const sc_lv<64> ap_const_lv64_1;
// Thread declarations
void thread_ap_var_for_const0();
void thread_ap_var_for_const3();
void thread_ap_var_for_const1();
void thread_ap_var_for_const4();
void thread_ap_var_for_const2();
void thread_ap_clk_no_reset_();
void thread_Matrix_Vector_Activa_1_U0_ap_continue();
void thread_Matrix_Vector_Activa_1_U0_ap_start();
void thread_Matrix_Vector_Activa_2_U0_ap_continue();
void thread_Matrix_Vector_Activa_2_U0_ap_start();
void thread_Matrix_Vector_Activa_3_U0_ap_continue();
void thread_Matrix_Vector_Activa_3_U0_ap_start();
void thread_Matrix_Vector_Activa_U0_ap_continue();
void thread_Matrix_Vector_Activa_U0_ap_start();
void thread_Mem2Stream_Batch12_U0_ap_continue();
void thread_Mem2Stream_Batch12_U0_ap_start();
void thread_Stream2Mem_Batch_U0_ap_continue();
void thread_StreamingDataWidthCo_1_U0_ap_continue();
void thread_StreamingDataWidthCo_1_U0_ap_start();
void thread_StreamingDataWidthCo_U0_ap_continue();
void thread_StreamingDataWidthCo_U0_ap_start();
void thread_ap_done();
void thread_ap_hs_continue();
void thread_ap_hs_done();
void thread_ap_hs_ready();
void thread_ap_idle();
void thread_ap_ready();
void thread_ap_sync_Matrix_Vector_Activa_1_U0_ap_ready();
void thread_ap_sync_Matrix_Vector_Activa_1_U0_ap_start();
void thread_ap_sync_Matrix_Vector_Activa_2_U0_ap_ready();
void thread_ap_sync_Matrix_Vector_Activa_2_U0_ap_start();
void thread_ap_sync_Matrix_Vector_Activa_3_U0_ap_ready();
void thread_ap_sync_Matrix_Vector_Activa_3_U0_ap_start();
void thread_ap_sync_Matrix_Vector_Activa_U0_ap_ready();
void thread_ap_sync_Matrix_V
|
ector_Activa_U0_ap_start();
void thread_ap_sync_Mem2Stream_Batch12_U0_ap_ready();
void thread_ap_sync_Mem2Stream_Batch12_U0_ap_start();
void thread_m_axi_in_V_ARADDR();
void thread_m_axi_in_V_ARBURST();
void thread_m_axi_in_V_ARCACHE();
void thread_m_axi_in_V_ARID();
void thread_m_axi_in_V_ARLEN();
void thread_m_axi_in_V_ARLOCK();
void thread_m_axi_in_V_ARPROT();
void thread_m_axi_in_V_ARQOS();
void thread_m_axi_in_V_ARREGION();
void thread_m_axi_in_V_ARSIZE();
void thread_m_axi_in_V_ARUSER();
void thread_m_axi_in_V_ARVALID();
void thread_m_axi_in_V_AWADDR();
void thread_m_axi_in_V_AWBURST();
void thread_m_axi_in_V_AWCACHE();
void thread_m_axi_in_V_AWID();
void thread_m_axi_in_V_AWLEN();
void thread_m_axi_in_V_AWLOCK();
void thread_m_axi_in_V_AWPROT();
void thread_m_axi_in_V_AWQOS();
void thread_m_axi_in_V_AWREGION();
void thread_m_axi_in_V_AWSIZE();
void thread_m_axi_in_V_AWUSER();
void thread_m_axi_in_V_AWVALID();
void thread_m_axi_in_V_BREADY();
void thread_m_axi_in_V_RREADY();
void thread_m_axi_in_V_WDATA();
void thread_m_axi_in_V_WID();
void thread_m_axi_in_V_WLAST();
void thread_m_axi_in_V_WSTRB();
void thread_m_axi_in_V_WUSER();
void thread_m_axi_in_V_WVALID();
void thread_start_for_StreamingDataWidthCo_1_U0_din();
void thread_start_for_StreamingDataWidthCo_U0_din();
void thread_threshs0_m_threshold_10_address0();
void thread_threshs0_m_threshold_10_address1();
void thread_threshs0_m_threshold_10_ce0();
void thread_threshs0_m_threshold_10_ce1();
void thread_threshs0_m_threshold_10_d0();
void thread_threshs0_m_threshold_10_d1();
void thread_threshs0_m_threshold_10_we0();
void thread_threshs0_m_threshold_10_we1();
void thread_threshs0_m_threshold_11_address0();
void thread_threshs0_m_threshold_11_address1();
void thread_threshs0_m_threshold_11_ce0();
void thread_threshs0_m_threshold_11_ce1();
void thread_threshs0_m_threshold_11_d0();
void thread_threshs0_m_threshold_11_d1();
void thread_threshs0_m_threshold_11_we0();
void thread_threshs0_m_threshold_11_we1();
void thread_threshs0_m_threshold_12_address0();
void thread_threshs0_m_threshold_12_address1();
void thread_threshs0_m_threshold_12_ce0();
void thread_threshs0_m_threshold_12_ce1();
void thread_threshs0_m_threshold_12_d0();
void thread_threshs0_m_threshold_12_d1();
void thread_threshs0_m_threshold_12_we0();
void thread_threshs0_m_threshold_12_we1();
void thread_threshs0_m_threshold_13_address0();
void thread_threshs0_m_threshold_13_address1();
void thread_threshs0_m_threshold_13_ce0();
void thread_threshs0_m_threshold_13_ce1();
void thread_threshs0_m_threshold_13_d0();
void thread_threshs0_m_threshold_13_d1();
void thread_threshs0_m_threshold_13_we0();
void thread_threshs0_m_threshold_13_we1();
void thread_threshs0_m_threshold_14_address0();
void thread_threshs0_m_threshold_14_address1();
void thread_threshs0_m_threshold_14_ce0();
void thread_threshs0_m_threshold_14_ce1();
void thread_threshs0_m_threshold_14_d0();
void thread_threshs0_m_threshold_14_d1();
void thread_threshs0_m_threshold_14_we0();
void thread_threshs0_m_threshold_14_we1();
void thread_threshs0_m_threshold_15_address0();
void thread_threshs0_m_threshold_15_address1();
void thread_threshs0_m_threshold_15_ce0();
void thread_threshs0_m_threshold_15_ce1();
void thread_threshs0_m_threshold_15_d0();
void thread_threshs0_m_threshold_15_d1();
void thread_threshs0_m_threshold_15_we0();
void thread_threshs0_m_threshold_15_we1();
void thread_threshs0_m_threshold_16_address0();
void thread_threshs0_m_threshold_16_address1();
void thread_threshs0_m_threshold_16_ce0();
void thread_threshs0_m_threshold_16_ce1();
void thread_threshs0_m_threshold_16_d0();
void thread_threshs0_m_threshold_16_d1();
void thread_threshs0_m_threshold_16_we0();
void thread_threshs0_m_threshold_16_we1();
void thread_threshs0_m_threshold_17_address0();
void thread_threshs0_m_threshold_17_address1();
void thread_threshs0_m_threshold_17_ce0();
void thread_threshs0_m_threshold_17_ce1();
void thread_threshs0_m_threshold_17_d0();
void thread_threshs0_m_threshold_17_d1();
void thread_threshs0_m_threshold_17_we0();
void thread_threshs0_m_threshold_17_we1();
void thread_threshs0_m_threshold_18_address0();
void thread_threshs0_m_threshold_18_address1();
void thread_threshs0_m_threshold_18_ce0();
void thread_threshs0_m_threshold_18_ce1();
void thread_threshs0_m_threshold_18_d0();
void thread_threshs0_m_threshold_18_d1();
void thread_threshs0_m_threshold_18_we0();
void thread_threshs0_m_threshold_18_we1();
void thread_threshs0_m_threshold_19_address0();
void thread_threshs0_m_threshold_19_address1();
void thread_threshs0_m_threshold_19_ce0();
void thread_threshs0_m_threshold_19_ce1();
void thread_threshs0_m_threshold_19_d0();
void thread_threshs0_m_threshold_19_d1();
void thread_threshs0_m_threshold_19_we0();
void thread_threshs0_m_threshold_19_we1();
void thread_threshs0_m_threshold_1_address0();
void thread_threshs0_m_threshold_1_address1();
void thread_threshs0_m_threshold_1_ce0();
void thread_threshs0_m_threshold_1_ce1();
void thread_threshs0_m_threshold_1_d0();
void thread_threshs0_m_threshold_1_d1();
void thread_threshs0_m_threshold_1_we0();
void thread_threshs0_m_threshold_1_we1();
void thread_threshs0_m_threshold_20_address0();
void thread_threshs0_m_threshold_20_address1();
void thread_threshs0_m_threshold_20_ce0();
void thread_threshs0_m_threshold_20_ce1();
void thread_threshs0_m_threshold_20_d0();
void thread_threshs0_m_threshold_20_d1();
void thread_threshs0_m_threshold_20_we0();
void thread_threshs0_m_threshold_20_we1();
void thread_threshs0_m_threshold_21_address0();
void thread_threshs0_m_threshold_21_address1();
void thread_threshs0_m_threshold_21_ce0();
void thread_threshs0_m_threshold_21_ce1();
void thread_threshs0_m_threshold_21_d0();
void thread_threshs0_m_threshold_21_d1();
void thread_threshs0_m_threshold_21_we0();
void thread_threshs0_m_threshold_21_we1();
void thread_threshs0_m_threshold_22_address0();
void thread_threshs0_m_threshold_22_address1();
void thread_threshs0_m_threshold_22_ce0();
void thread_threshs0_m_threshold_22_ce1();
void thread_threshs0_m_threshold_22_d0();
void thread_threshs0_m_threshold_22_d1();
void thread_threshs0_m_threshold_22_we0();
void thread_threshs0_m_threshold_22_we1();
void thread_threshs0_m_threshold_23_address0();
void thread_threshs0_m_threshold_23_address1();
void thread_threshs0_m_threshold_23_ce0();
void thread_threshs0_m_threshold_23_ce1();
void thread_threshs0_m_threshold_23_d0();
void thread_threshs0_m_threshold_23_d1();
void thread_threshs0_m_threshold_23_we0();
void thread_threshs0_m_threshold_23_we1();
void thread_threshs0_m_threshold_24_address0();
void thread_threshs0_m_threshold_24_address1();
void thread_threshs0_m_threshold_24_ce0();
void thread_threshs0_m_threshold_24_ce1();
void thread_threshs0_m_threshold_24_d0();
void thread_threshs0_m_threshold_24_d1();
void thread_threshs0_m_threshold_24_we0();
void thread_threshs0_m_threshold_24_we1();
void thread_threshs0_m_threshold_25_address0();
void thread_threshs0_m_threshold_25_address1();
void thread_threshs0_m_threshold_25_ce0();
void thread_threshs0_m_threshold_25_ce1();
void thread_threshs0_m_threshold_25_d0();
void thread_threshs0_m_threshold_25_d1();
void thread_threshs0_m_threshold_25_we0();
void thread_threshs0_m_threshold_25_we1();
void thread_threshs0_m_threshold_26_address0();
void thread_threshs0_m_threshold_26_address1();
void thread_threshs0_m_threshold_26_ce0();
void thread_threshs0_m_threshold_26_ce1();
void thread_threshs0_m_threshold_26_d0();
void thread_threshs0_m_threshold_26_d1();
void thread_threshs0_m_threshold_26_we0();
void thread_threshs0_m_threshold_26_we1();
void thread_threshs0_m_threshold_27_address0();
void thread_threshs0_m_threshold_27_address1();
void thread_threshs0_m_threshold_27_ce0();
void thread_threshs0_m_threshold_27_ce1();
void thread_threshs0_m_threshold_27_d0();
void thread_threshs0_m_threshold_27_d1();
void thread_threshs0_m_threshold_27_we0();
void thread_threshs0_m_threshold_27_we1();
void thread_threshs0_m_threshold_28_address0();
void thread_threshs0_m_threshold_28_address1();
void thread_threshs0_m_threshold_28_ce0();
void thread_threshs0_m_threshold_28_ce1();
void thread_threshs0_m_threshold_28_d0();
void thread_threshs0_m_threshold_28_d1();
void thread_threshs0_m_threshold_28_we0();
void thread_threshs0_m_threshold_28_we1();
void thread_threshs0_m_threshold_29_address0();
void thread_threshs0_m_threshold_29_address1();
void thread_threshs0_m_threshold_29_ce0();
void thread_threshs0_m_threshold_29_ce1();
void thread_threshs0_m_threshold_29_d0();
void thread_threshs0_m_threshold_29_d1();
void thread_threshs0_m_threshold_29_we0();
void thread_threshs0_m_threshold_29_we1();
void thread_threshs0_m_threshold_2_address0();
void thread_threshs0_m_threshold_2_address1();
void thread_threshs0_m_threshold_2_ce0();
void thread_threshs0_m_threshold_2_ce1();
void thread_threshs0_m_threshold_2_d0();
void thread_threshs0_m_threshold_2_d1();
void thread_threshs0_m_threshold_2_we0();
void thread_threshs0_m_threshold_2_we1();
void thread_threshs0_m_threshold_30_address0();
void thread_threshs0_m_threshold_30_address1();
void thread_threshs0_m_threshold_30_ce0();
void thread_threshs0_m_threshold_30_ce1();
void thread_threshs0_m_threshold_30_d0();
void thread_threshs0_m_threshold_30_d1();
void thread_threshs0_m_threshold_30_we0();
void thread_threshs0_m_threshold_30_we1();
void thread_threshs0_m_threshold_31_address0();
void thread_threshs0_m_threshold_31_address1();
void thread_threshs0_m_threshold_31_ce0();
void thread_threshs0_m_threshold_31_ce1();
void thread_threshs0_m_threshold_31_d0();
void thread_threshs0_m_threshold_31_d1();
void thread_threshs0_m_threshold_31_we0();
void thread_threshs0_m_threshold_31_we1();
void thread_threshs0_m_threshold_3_address0();
void thread_threshs0_m_threshold_3_address1();
void thread_threshs0_m_threshold_3_ce0();
void thread_threshs0_m_threshold_3_ce1();
void thread_threshs0_m_threshold_3_d0();
void thread_threshs0_m_threshold_3_d1();
void thread_threshs0_m_threshold_3_we0();
void thread_threshs0_m_threshold_3_we1();
void thread_threshs0_m_threshold_4_address0();
void thread_threshs0_m_threshold_4_address1();
void thread_threshs0_m_threshold_4_ce0();
void thread_threshs0_m_threshold_4_ce1();
void thread_threshs0_m_threshold_4_d0();
void thread_threshs0_m_threshold_4_d1();
void thread_threshs0_m_threshold_4_we0();
void thread_threshs0_m_threshold_4_we1();
void thread_threshs0_m_threshold_5_address0();
void thread_threshs0_m_threshold_5_address1();
void thread_threshs0_m_threshold_5_ce0();
void thread_threshs0_m_threshold_5_ce1();
void thread_threshs0_m_threshold_5_d0();
void thread_threshs0_m_threshold_5_d1();
void thread_threshs0_m_threshold_5_we0();
void thread_threshs0_m_threshold_5_we1();
void thread_threshs0_m_threshold_6_address0();
void thread_threshs0_m_threshold_6_address1();
void thread_threshs0_m_threshold_6_ce0();
void thread_threshs0_m_threshold_6_ce1();
void thread_threshs0_m_threshold_6_d0();
void thread_threshs0_m_threshold_6_d1();
void thread_threshs0_m_threshold_6_we0();
void thread_threshs0_m_threshold_6_we1();
void thread_threshs0_m_threshold_7_address0();
void thread_threshs0_m_threshold_7_address1();
void thread_threshs0_m_threshold_7_ce0();
void thread_threshs0_m_threshold_7_ce1();
void thread_threshs0_m_threshold_7_d0();
void thread_threshs0_m_threshold_7_d1();
void thread_threshs0_m_threshold_7_we0();
void thread_threshs0_m_threshold_7_we1();
void thread_threshs0_m_threshold_8_address0();
void thread_threshs0_m_threshold_8_address1();
void thread_threshs0_m_threshold_8_ce0();
void thread_threshs0_m_threshold_8_ce1();
void thread_threshs0_m_threshold_8_d0();
void thread_threshs0_m_threshold_8_d1();
void thread_threshs0_m_threshold_8_we0();
void thread_threshs0_m_threshold_8_we1();
void thread_threshs0_m_threshold_9_address0();
void thread_threshs0_m_threshold_9_address1();
void thread_threshs0_m_threshold_9_ce0();
void thread_threshs0_m_threshold_9_ce1();
void thread_threshs0_m_threshold_9_d0();
void thread_threshs0_m_threshold_9_d1();
void thread_threshs0_m_threshold_9_we0();
void thread_threshs0_m_threshold_9_we1();
void thread_threshs0_m_threshold_address0();
void thread_threshs0_m_threshold_address1();
void thread_threshs0_m_threshold_ce0();
void thread_threshs0_m_threshold_ce1();
void thread_threshs0_m_threshold_d0();
void thread_threshs0_m_threshold_d1();
void thread_threshs0_m_threshold_we0();
void thread_threshs0_m_threshold_we1();
void thread_threshs1_m_threshold_10_address0();
void thread_threshs1_m_threshold_10_address1();
void thread_threshs1_m_threshold_10_ce0();
void thread_threshs1_m_threshold_10_ce1();
void thread_threshs1_m_threshold_10_d0();
void thread_threshs1_m_threshold_10_d1();
void thread_threshs1_m_threshold_10_we0();
void thread_threshs1_m_threshold_10_we1();
void thread_threshs1_m_threshold_11_address0();
void thread_threshs1_m_threshold_11_address1();
void thread_threshs1_m_threshold_11_ce0();
void thread_threshs1_m_threshold_11_ce1();
void thread_threshs1_m_threshold_11_d0();
void thread_threshs1_m_threshold_11_d1();
void thread_threshs1_m_threshold_11_we0();
void thread_threshs1_m_threshold_11_we1();
void thread_threshs1_m_threshold_12_address0();
void thread_threshs1_m_threshold_12_address1();
void thread_threshs1_m_threshold_12_ce0();
void thread_threshs1_m_threshold_12_ce1();
void thread_threshs1_m_threshold_12_d0();
void thread_threshs1_m_threshold_12_d1();
void thread_threshs1_m_threshold_12_we0();
void thread_threshs1_m_threshold_12_we1();
void thread_threshs1_m_threshold_13_address0();
void thread_threshs1_m_threshold_13_address1();
void thread_threshs1_m_threshold_13_ce0();
void thread_threshs1_m_threshold_13_ce1();
void thread_threshs1_m_threshold_13_d0();
void thread_threshs1_m_threshold_13_d1();
void thread_threshs1_m_threshold_13_we0();
void thread_threshs1_m_threshold_13_we1();
void thread_threshs1_m_threshold_14_address0();
void thread_threshs1_m_threshold_14_address1();
void thread_threshs1_m_threshold_14_ce0();
void thread_threshs1_m_threshold_14_ce1();
void thread_threshs1_m_threshold_14_d0();
void thread_threshs1_m_threshold_14_d1();
void thread_threshs1_m_threshold_14_we0();
void thread_threshs1_m_threshold_14_we1();
void thread_threshs1_m_threshold_15_address0();
void thread_threshs1_m_threshold_15_address1();
void thread_threshs1_m_threshold_15_ce0();
void thread_threshs1_m_threshold_15_ce1();
void thread_threshs1_m_threshold_15_d0();
void thread_threshs1_m_threshold_15_d1();
void thread_threshs1_m_threshold_15_we0();
void thread_threshs1_m_threshold_15_we1();
void thread_threshs1_m_threshold_16_address0();
void thread_threshs1_m_threshold_16_address1();
void thread_threshs1_m_threshold_16_ce0();
void thread_threshs1_m_threshold_16_ce1();
void thread_threshs1_m_threshold_16_d0();
void thread_threshs1_m_threshold_16_d1();
void thread_threshs1_m_threshold_16_we0();
void thread_threshs1_m_threshold_16_we1();
void thread_threshs1_m_threshold_17_address0();
void thread_threshs1_m_threshold_17_address1();
void thread_threshs1_m_threshold_17_ce0();
void thread_threshs1_m_threshold_17_ce1();
void thread_threshs1_m_threshold_17_d0();
void thread_threshs1_m_threshold_17_d1();
void thread_threshs1_m_threshold_17_we0();
void thread_threshs1_m_threshold_17_we1();
void thread_threshs1_m_threshold_18_address0();
void thread_threshs1_m_threshold_18_address1();
void thread_threshs1_m_threshold_18_ce0();
void thread_threshs1_m_threshold_18_ce1();
void thread_threshs1_m_threshold_18_d0();
void thread_threshs1_m_threshold_18_d1();
void thread_threshs1_m_threshold_18_we0();
void thread_threshs1_m_threshold_18_we1();
void thread_threshs1_m_threshold_19_address0();
void thread_threshs1_m_threshold_19_address1();
void thread_threshs1_m_threshold_19_ce0();
void thread_threshs1_m_threshold_19_ce1();
void thread_threshs1_m_threshold_19_d0();
void thread_threshs1_m_threshold_19_d1();
void thread_threshs1_m_threshold_19_we0();
void thread_threshs1_m_threshold_19_we1();
void thread_threshs1_m_threshold_1_address0();
void thread_threshs1_m_threshold_1_address1();
void thread_threshs1_m_threshold_1_ce0();
void thread_threshs1_m_threshold_1_ce1();
void thread_threshs1_m_threshold_1_d0();
void thread_threshs1_m_threshold_1_d1();
void thread_threshs1_m_threshold_1_we0();
void thread_threshs1_m_threshold_1_we1();
void thread_threshs1_m_threshold_20_address0();
void thread_threshs1_m_threshold_20_address1();
void thread_threshs1_m_threshold_20_ce0();
void thread_threshs1_m_threshold_20_ce1();
void thread_threshs1_m_threshold_20_d0();
void thread_threshs1_m_threshold_20_d1();
void thread_threshs1_m_threshold_20_we0();
void thread_threshs1_m_threshold_20_we1();
void thread_threshs1_m_threshold_21_address0();
void thread_threshs1_m_threshold_21_address1();
void thread_threshs1_m_threshold_21_ce0();
void thread_threshs1_m_threshold_21_ce1();
void thread_threshs1_m_threshold_21_d0();
void thread_threshs1_m_threshold_21_d1();
void thread_threshs1_m_threshold_21_we0();
void thread_threshs1_m_threshold_21_we1();
void thread_threshs1_m_threshold_22_address0();
void thread_threshs1_m_threshold_22_address1();
void thread_threshs1_m_threshold_22_ce0();
void thread_threshs1_m_threshold_22_ce1();
void thread_threshs1_m_threshold_22_d0();
void thread_threshs1_m_threshold_22_d1();
void thread_threshs1_m_threshold_22_we0();
void thread_threshs1_m_threshold_22_we1();
void thread_threshs1_m_threshold_23_address0();
void thread_threshs1_m_threshold_23_address1();
void thread_threshs1_m_threshold_23_ce0();
void thread_threshs1_m_threshold_23_ce1();
void thread_threshs1_m_threshold_23_d0();
void thread_threshs1_m_threshold_23_d1();
void thread_threshs1_m_threshold_23_we0();
void thread_threshs1_m_threshold_23_we1();
void thread_threshs1_m_threshold_24_address0();
void thread_threshs1_m_threshold_24_address1();
void thread_threshs1_m_threshold_24_ce0();
void thread_threshs1_m_threshold_24_ce1();
void thread_threshs1_m_threshold_24_d0();
void thread_threshs1_m_threshold_24_d1();
void thread_threshs1_m_threshold_24_we0();
void thread_threshs1_m_threshold_24_we1();
void thread_threshs1_m_threshold_25_address0();
void thread_threshs1_m_threshold_25_address1();
void thread_threshs1_m_threshold_25_ce0();
void thread_threshs1_m_threshold_25_ce1();
void thread_threshs1_m_threshol
|
d_25_d0();
void thread_threshs1_m_threshold_25_d1();
void thread_threshs1_m_threshold_25_we0();
void thread_threshs1_m_threshold_25_we1();
void thread_threshs1_m_threshold_26_address0();
void thread_threshs1_m_threshold_26_address1();
void thread_threshs1_m_threshold_26_ce0();
void thread_threshs1_m_threshold_26_ce1();
void thread_threshs1_m_threshold_26_d0();
void thread_threshs1_m_threshold_26_d1();
void thread_threshs1_m_threshold_26_we0();
void thread_threshs1_m_threshold_26_we1();
void thread_threshs1_m_threshold_27_address0();
void thread_threshs1_m_threshold_27_address1();
void thread_threshs1_m_threshold_27_ce0();
void thread_threshs1_m_threshold_27_ce1();
void thread_threshs1_m_threshold_27_d0();
void thread_threshs1_m_threshold_27_d1();
void thread_threshs1_m_threshold_27_we0();
void thread_threshs1_m_threshold_27_we1();
void thread_threshs1_m_threshold_28_address0();
void thread_threshs1_m_threshold_28_address1();
void thread_threshs1_m_threshold_28_ce0();
void thread_threshs1_m_threshold_28_ce1();
void thread_threshs1_m_threshold_28_d0();
void thread_threshs1_m_threshold_28_d1();
void thread_threshs1_m_threshold_28_we0();
void thread_threshs1_m_threshold_28_we1();
void thread_threshs1_m_threshold_29_address0();
void thread_threshs1_m_threshold_29_address1();
void thread_threshs1_m_threshold_29_ce0();
void thread_threshs1_m_threshold_29_ce1();
void thread_threshs1_m_threshold_29_d0();
void thread_threshs1_m_threshold_29_d1();
void thread_threshs1_m_threshold_29_we0();
void thread_threshs1_m_threshold_29_we1();
void thread_threshs1_m_threshold_2_address0();
void thread_threshs1_m_threshold_2_address1();
void thread_threshs1_m_threshold_2_ce0();
void thread_threshs1_m_threshold_2_ce1();
void thread_threshs1_m_threshold_2_d0();
void thread_threshs1_m_threshold_2_d1();
void thread_threshs1_m_threshold_2_we0();
void thread_threshs1_m_threshold_2_we1();
void thread_threshs1_m_threshold_30_address0();
void thread_threshs1_m_threshold_30_address1();
void thread_threshs1_m_threshold_30_ce0();
void thread_threshs1_m_threshold_30_ce1();
void thread_threshs1_m_threshold_30_d0();
void thread_threshs1_m_threshold_30_d1();
void thread_threshs1_m_threshold_30_we0();
void thread_threshs1_m_threshold_30_we1();
void thread_threshs1_m_threshold_31_address0();
void thread_threshs1_m_threshold_31_address1();
void thread_threshs1_m_threshold_31_ce0();
void thread_threshs1_m_threshold_31_ce1();
void thread_threshs1_m_threshold_31_d0();
void thread_threshs1_m_threshold_31_d1();
void thread_threshs1_m_threshold_31_we0();
void thread_threshs1_m_threshold_31_we1();
void thread_threshs1_m_threshold_32_address0();
void thread_threshs1_m_threshold_32_address1();
void thread_threshs1_m_threshold_32_ce0();
void thread_threshs1_m_threshold_32_ce1();
void thread_threshs1_m_threshold_32_d0();
void thread_threshs1_m_threshold_32_d1();
void thread_threshs1_m_threshold_32_we0();
void thread_threshs1_m_threshold_32_we1();
void thread_threshs1_m_threshold_33_address0();
void thread_threshs1_m_threshold_33_address1();
void thread_threshs1_m_threshold_33_ce0();
void thread_threshs1_m_threshold_33_ce1();
void thread_threshs1_m_threshold_33_d0();
void thread_threshs1_m_threshold_33_d1();
void thread_threshs1_m_threshold_33_we0();
void thread_threshs1_m_threshold_33_we1();
void thread_threshs1_m_threshold_34_address0();
void thread_threshs1_m_threshold_34_address1();
void thread_threshs1_m_threshold_34_ce0();
void thread_threshs1_m_threshold_34_ce1();
void thread_threshs1_m_threshold_34_d0();
void thread_threshs1_m_threshold_34_d1();
void thread_threshs1_m_threshold_34_we0();
void thread_threshs1_m_threshold_34_we1();
void thread_threshs1_m_threshold_35_address0();
void thread_threshs1_m_threshold_35_address1();
void thread_threshs1_m_threshold_35_ce0();
void thread_threshs1_m_threshold_35_ce1();
void thread_threshs1_m_threshold_35_d0();
void thread_threshs1_m_threshold_35_d1();
void thread_threshs1_m_threshold_35_we0();
void thread_threshs1_m_threshold_35_we1();
void thread_threshs1_m_threshold_36_address0();
void thread_threshs1_m_threshold_36_address1();
void thread_threshs1_m_threshold_36_ce0();
void thread_threshs1_m_threshold_36_ce1();
void thread_threshs1_m_threshold_36_d0();
void thread_threshs1_m_threshold_36_d1();
void thread_threshs1_m_threshold_36_we0();
void thread_threshs1_m_threshold_36_we1();
void thread_threshs1_m_threshold_37_address0();
void thread_threshs1_m_threshold_37_address1();
void thread_threshs1_m_threshold_37_ce0();
void thread_threshs1_m_threshold_37_ce1();
void thread_threshs1_m_threshold_37_d0();
void thread_threshs1_m_threshold_37_d1();
void thread_threshs1_m_threshold_37_we0();
void thread_threshs1_m_threshold_37_we1();
void thread_threshs1_m_threshold_38_address0();
void thread_threshs1_m_threshold_38_address1();
void thread_threshs1_m_threshold_38_ce0();
void thread_threshs1_m_threshold_38_ce1();
void thread_threshs1_m_threshold_38_d0();
void thread_threshs1_m_threshold_38_d1();
void thread_threshs1_m_threshold_38_we0();
void thread_threshs1_m_threshold_38_we1();
void thread_threshs1_m_threshold_39_address0();
void thread_threshs1_m_threshold_39_address1();
void thread_threshs1_m_threshold_39_ce0();
void thread_threshs1_m_threshold_39_ce1();
void thread_threshs1_m_threshold_39_d0();
void thread_threshs1_m_threshold_39_d1();
void thread_threshs1_m_threshold_39_we0();
void thread_threshs1_m_threshold_39_we1();
void thread_threshs1_m_threshold_3_address0();
void thread_threshs1_m_threshold_3_address1();
void thread_threshs1_m_threshold_3_ce0();
void thread_threshs1_m_threshold_3_ce1();
void thread_threshs1_m_threshold_3_d0();
void thread_threshs1_m_threshold_3_d1();
void thread_threshs1_m_threshold_3_we0();
void thread_threshs1_m_threshold_3_we1();
void thread_threshs1_m_threshold_40_address0();
void thread_threshs1_m_threshold_40_address1();
void thread_threshs1_m_threshold_40_ce0();
void thread_threshs1_m_threshold_40_ce1();
void thread_threshs1_m_threshold_40_d0();
void thread_threshs1_m_threshold_40_d1();
void thread_threshs1_m_threshold_40_we0();
void thread_threshs1_m_threshold_40_we1();
void thread_threshs1_m_threshold_41_address0();
void thread_threshs1_m_threshold_41_address1();
void thread_threshs1_m_threshold_41_ce0();
void thread_threshs1_m_threshold_41_ce1();
void thread_threshs1_m_threshold_41_d0();
void thread_threshs1_m_threshold_41_d1();
void thread_threshs1_m_threshold_41_we0();
void thread_threshs1_m_threshold_41_we1();
void thread_threshs1_m_threshold_42_address0();
void thread_threshs1_m_threshold_42_address1();
void thread_threshs1_m_threshold_42_ce0();
void thread_threshs1_m_threshold_42_ce1();
void thread_threshs1_m_threshold_42_d0();
void thread_threshs1_m_threshold_42_d1();
void thread_threshs1_m_threshold_42_we0();
void thread_threshs1_m_threshold_42_we1();
void thread_threshs1_m_threshold_43_address0();
void thread_threshs1_m_threshold_43_address1();
void thread_threshs1_m_threshold_43_ce0();
void thread_threshs1_m_threshold_43_ce1();
void thread_threshs1_m_threshold_43_d0();
void thread_threshs1_m_threshold_43_d1();
void thread_threshs1_m_threshold_43_we0();
void thread_threshs1_m_threshold_43_we1();
void thread_threshs1_m_threshold_44_address0();
void thread_threshs1_m_threshold_44_address1();
void thread_threshs1_m_threshold_44_ce0();
void thread_threshs1_m_threshold_44_ce1();
void thread_threshs1_m_threshold_44_d0();
void thread_threshs1_m_threshold_44_d1();
void thread_threshs1_m_threshold_44_we0();
void thread_threshs1_m_threshold_44_we1();
void thread_threshs1_m_threshold_45_address0();
void thread_threshs1_m_threshold_45_address1();
void thread_threshs1_m_threshold_45_ce0();
void thread_threshs1_m_threshold_45_ce1();
void thread_threshs1_m_threshold_45_d0();
void thread_threshs1_m_threshold_45_d1();
void thread_threshs1_m_threshold_45_we0();
void thread_threshs1_m_threshold_45_we1();
void thread_threshs1_m_threshold_46_address0();
void thread_threshs1_m_threshold_46_address1();
void thread_threshs1_m_threshold_46_ce0();
void thread_threshs1_m_threshold_46_ce1();
void thread_threshs1_m_threshold_46_d0();
void thread_threshs1_m_threshold_46_d1();
void thread_threshs1_m_threshold_46_we0();
void thread_threshs1_m_threshold_46_we1();
void thread_threshs1_m_threshold_47_address0();
void thread_threshs1_m_threshold_47_address1();
void thread_threshs1_m_threshold_47_ce0();
void thread_threshs1_m_threshold_47_ce1();
void thread_threshs1_m_threshold_47_d0();
void thread_threshs1_m_threshold_47_d1();
void thread_threshs1_m_threshold_47_we0();
void thread_threshs1_m_threshold_47_we1();
void thread_threshs1_m_threshold_48_address0();
void thread_threshs1_m_threshold_48_address1();
void thread_threshs1_m_threshold_48_ce0();
void thread_threshs1_m_threshold_48_ce1();
void thread_threshs1_m_threshold_48_d0();
void thread_threshs1_m_threshold_48_d1();
void thread_threshs1_m_threshold_48_we0();
void thread_threshs1_m_threshold_48_we1();
void thread_threshs1_m_threshold_49_address0();
void thread_threshs1_m_threshold_49_address1();
void thread_threshs1_m_threshold_49_ce0();
void thread_threshs1_m_threshold_49_ce1();
void thread_threshs1_m_threshold_49_d0();
void thread_threshs1_m_threshold_49_d1();
void thread_threshs1_m_threshold_49_we0();
void thread_threshs1_m_threshold_49_we1();
void thread_threshs1_m_threshold_4_address0();
void thread_threshs1_m_threshold_4_address1();
void thread_threshs1_m_threshold_4_ce0();
void thread_threshs1_m_threshold_4_ce1();
void thread_threshs1_m_threshold_4_d0();
void thread_threshs1_m_threshold_4_d1();
void thread_threshs1_m_threshold_4_we0();
void thread_threshs1_m_threshold_4_we1();
void thread_threshs1_m_threshold_50_address0();
void thread_threshs1_m_threshold_50_address1();
void thread_threshs1_m_threshold_50_ce0();
void thread_threshs1_m_threshold_50_ce1();
void thread_threshs1_m_threshold_50_d0();
void thread_threshs1_m_threshold_50_d1();
void thread_threshs1_m_threshold_50_we0();
void thread_threshs1_m_threshold_50_we1();
void thread_threshs1_m_threshold_51_address0();
void thread_threshs1_m_threshold_51_address1();
void thread_threshs1_m_threshold_51_ce0();
void thread_threshs1_m_threshold_51_ce1();
void thread_threshs1_m_threshold_51_d0();
void thread_threshs1_m_threshold_51_d1();
void thread_threshs1_m_threshold_51_we0();
void thread_threshs1_m_threshold_51_we1();
void thread_threshs1_m_threshold_52_address0();
void thread_threshs1_m_threshold_52_address1();
void thread_threshs1_m_threshold_52_ce0();
void thread_threshs1_m_threshold_52_ce1();
void thread_threshs1_m_threshold_52_d0();
void thread_threshs1_m_threshold_52_d1();
void thread_threshs1_m_threshold_52_we0();
void thread_threshs1_m_threshold_52_we1();
void thread_threshs1_m_threshold_53_address0();
void thread_threshs1_m_threshold_53_address1();
void thread_threshs1_m_threshold_53_ce0();
void thread_threshs1_m_threshold_53_ce1();
void thread_threshs1_m_threshold_53_d0();
void thread_threshs1_m_threshold_53_d1();
void thread_threshs1_m_threshold_53_we0();
void thread_threshs1_m_threshold_53_we1();
void thread_threshs1_m_threshold_54_address0();
void thread_threshs1_m_threshold_54_address1();
void thread_threshs1_m_threshold_54_ce0();
void thread_threshs1_m_threshold_54_ce1();
void thread_threshs1_m_threshold_54_d0();
void thread_threshs1_m_threshold_54_d1();
void thread_threshs1_m_threshold_54_we0();
void thread_threshs1_m_threshold_54_we1();
void thread_threshs1_m_threshold_55_address0();
void thread_threshs1_m_threshold_55_address1();
void thread_threshs1_m_threshold_55_ce0();
void thread_threshs1_m_threshold_55_ce1();
void thread_threshs1_m_threshold_55_d0();
void thread_threshs1_m_threshold_55_d1();
void thread_threshs1_m_threshold_55_we0();
void thread_threshs1_m_threshold_55_we1();
void thread_threshs1_m_threshold_56_address0();
void thread_threshs1_m_threshold_56_address1();
void thread_threshs1_m_threshold_56_ce0();
void thread_threshs1_m_threshold_56_ce1();
void thread_threshs1_m_threshold_56_d0();
void thread_threshs1_m_threshold_56_d1();
void thread_threshs1_m_threshold_56_we0();
void thread_threshs1_m_threshold_56_we1();
void thread_threshs1_m_threshold_57_address0();
void thread_threshs1_m_threshold_57_address1();
void thread_threshs1_m_threshold_57_ce0();
void thread_threshs1_m_threshold_57_ce1();
void thread_threshs1_m_threshold_57_d0();
void thread_threshs1_m_threshold_57_d1();
void thread_threshs1_m_threshold_57_we0();
void thread_threshs1_m_threshold_57_we1();
void thread_threshs1_m_threshold_58_address0();
void thread_threshs1_m_threshold_58_address1();
void thread_threshs1_m_threshold_58_ce0();
void thread_threshs1_m_threshold_58_ce1();
void thread_threshs1_m_threshold_58_d0();
void thread_threshs1_m_threshold_58_d1();
void thread_threshs1_m_threshold_58_we0();
void thread_threshs1_m_threshold_58_we1();
void thread_threshs1_m_threshold_59_address0();
void thread_threshs1_m_threshold_59_address1();
void thread_threshs1_m_threshold_59_ce0();
void thread_threshs1_m_threshold_59_ce1();
void thread_threshs1_m_threshold_59_d0();
void thread_threshs1_m_threshold_59_d1();
void thread_threshs1_m_threshold_59_we0();
void thread_threshs1_m_threshold_59_we1();
void thread_threshs1_m_threshold_5_address0();
void thread_threshs1_m_threshold_5_address1();
void thread_threshs1_m_threshold_5_ce0();
void thread_threshs1_m_threshold_5_ce1();
void thread_threshs1_m_threshold_5_d0();
void thread_threshs1_m_threshold_5_d1();
void thread_threshs1_m_threshold_5_we0();
void thread_threshs1_m_threshold_5_we1();
void thread_threshs1_m_threshold_60_address0();
void thread_threshs1_m_threshold_60_address1();
void thread_threshs1_m_threshold_60_ce0();
void thread_threshs1_m_threshold_60_ce1();
void thread_threshs1_m_threshold_60_d0();
void thread_threshs1_m_threshold_60_d1();
void thread_threshs1_m_threshold_60_we0();
void thread_threshs1_m_threshold_60_we1();
void thread_threshs1_m_threshold_61_address0();
void thread_threshs1_m_threshold_61_address1();
void thread_threshs1_m_threshold_61_ce0();
void thread_threshs1_m_threshold_61_ce1();
void thread_threshs1_m_threshold_61_d0();
void thread_threshs1_m_threshold_61_d1();
void thread_threshs1_m_threshold_61_we0();
void thread_threshs1_m_threshold_61_we1();
void thread_threshs1_m_threshold_62_address0();
void thread_threshs1_m_threshold_62_address1();
void thread_threshs1_m_threshold_62_ce0();
void thread_threshs1_m_threshold_62_ce1();
void thread_threshs1_m_threshold_62_d0();
void thread_threshs1_m_threshold_62_d1();
void thread_threshs1_m_threshold_62_we0();
void thread_threshs1_m_threshold_62_we1();
void thread_threshs1_m_threshold_63_address0();
void thread_threshs1_m_threshold_63_address1();
void thread_threshs1_m_threshold_63_ce0();
void thread_threshs1_m_threshold_63_ce1();
void thread_threshs1_m_threshold_63_d0();
void thread_threshs1_m_threshold_63_d1();
void thread_threshs1_m_threshold_63_we0();
void thread_threshs1_m_threshold_63_we1();
void thread_threshs1_m_threshold_6_address0();
void thread_threshs1_m_threshold_6_address1();
void thread_threshs1_m_threshold_6_ce0();
void thread_threshs1_m_threshold_6_ce1();
void thread_threshs1_m_threshold_6_d0();
void thread_threshs1_m_threshold_6_d1();
void thread_threshs1_m_threshold_6_we0();
void thread_threshs1_m_threshold_6_we1();
void thread_threshs1_m_threshold_7_address0();
void thread_threshs1_m_threshold_7_address1();
void thread_threshs1_m_threshold_7_ce0();
void thread_threshs1_m_threshold_7_ce1();
void thread_threshs1_m_threshold_7_d0();
void thread_threshs1_m_threshold_7_d1();
void thread_threshs1_m_threshold_7_we0();
void thread_threshs1_m_threshold_7_we1();
void thread_threshs1_m_threshold_8_address0();
void thread_threshs1_m_threshold_8_address1();
void thread_threshs1_m_threshold_8_ce0();
void thread_threshs1_m_threshold_8_ce1();
void thread_threshs1_m_threshold_8_d0();
void thread_threshs1_m_threshold_8_d1();
void thread_threshs1_m_threshold_8_we0();
void thread_threshs1_m_threshold_8_we1();
void thread_threshs1_m_threshold_9_address0();
void thread_threshs1_m_threshold_9_address1();
void thread_threshs1_m_threshold_9_ce0();
void thread_threshs1_m_threshold_9_ce1();
void thread_threshs1_m_threshold_9_d0();
void thread_threshs1_m_threshold_9_d1();
void thread_threshs1_m_threshold_9_we0();
void thread_threshs1_m_threshold_9_we1();
void thread_threshs1_m_threshold_address0();
void thread_threshs1_m_threshold_address1();
void thread_threshs1_m_threshold_ce0();
void thread_threshs1_m_threshold_ce1();
void thread_threshs1_m_threshold_d0();
void thread_threshs1_m_threshold_d1();
void thread_threshs1_m_threshold_we0();
void thread_threshs1_m_threshold_we1();
void thread_threshs2_m_threshold_10_address0();
void thread_threshs2_m_threshold_10_address1();
void thread_threshs2_m_threshold_10_ce0();
void thread_threshs2_m_threshold_10_ce1();
void thread_threshs2_m_threshold_10_d0();
void thread_threshs2_m_threshold_10_d1();
void thread_threshs2_m_threshold_10_we0();
void thread_threshs2_m_threshold_10_we1();
void thread_threshs2_m_threshold_11_address0();
void thread_threshs2_m_threshold_11_address1();
void thread_threshs2_m_threshold_11_ce0();
void thread_threshs2_m_threshold_11_ce1();
void thread_threshs2_m_threshold_11_d0();
void thread_threshs2_m_threshold_11_d1();
void thread_threshs2_m_threshold_11_we0();
void thread_threshs2_m_threshold_11_we1();
void thread_threshs2_m_threshold_12_address0();
void thread_threshs2_m_threshold_12_address1();
void thread_threshs2_m_threshold_12_ce0();
void thread_threshs2_m_threshold_12_ce1();
void thread_threshs2_m_threshold_12_d0();
void thread_threshs2_m_threshold_12_d1();
void thread_threshs2_m_threshold_12_we0();
void thread_threshs2_m_threshold_12_we1();
void thread_threshs2_m_threshold_13_address0();
void thread_threshs2_m_threshold_13_address1();
void thread_threshs2_m_threshold_13_ce0();
void thread_threshs2_m_threshold_13_ce1();
void thread_threshs2_m_threshold_13_d0();
void thread_threshs2_m_threshold_13_d1();
void thread_threshs2_m_threshold_13_we0();
void thread_threshs2_m_threshold_13_we1();
void thread_threshs2_m_threshold_14_address0();
void thread_threshs2_m_threshold_14_address1();
void thread_threshs2_m_threshold_14_ce0();
void thread_threshs2_m_threshold_14_ce1();
void thread_threshs2_m_threshold_14_d0();
void thread_threshs2_m_threshold_14_d1();
void thread_threshs2_m_threshold_14_we0();
void thread_
|
threshs2_m_threshold_14_we1();
void thread_threshs2_m_threshold_15_address0();
void thread_threshs2_m_threshold_15_address1();
void thread_threshs2_m_threshold_15_ce0();
void thread_threshs2_m_threshold_15_ce1();
void thread_threshs2_m_threshold_15_d0();
void thread_threshs2_m_threshold_15_d1();
void thread_threshs2_m_threshold_15_we0();
void thread_threshs2_m_threshold_15_we1();
void thread_threshs2_m_threshold_16_address0();
void thread_threshs2_m_threshold_16_address1();
void thread_threshs2_m_threshold_16_ce0();
void thread_threshs2_m_threshold_16_ce1();
void thread_threshs2_m_threshold_16_d0();
void thread_threshs2_m_threshold_16_d1();
void thread_threshs2_m_threshold_16_we0();
void thread_threshs2_m_threshold_16_we1();
void thread_threshs2_m_threshold_17_address0();
void thread_threshs2_m_threshold_17_address1();
void thread_threshs2_m_threshold_17_ce0();
void thread_threshs2_m_threshold_17_ce1();
void thread_threshs2_m_threshold_17_d0();
void thread_threshs2_m_threshold_17_d1();
void thread_threshs2_m_threshold_17_we0();
void thread_threshs2_m_threshold_17_we1();
void thread_threshs2_m_threshold_18_address0();
void thread_threshs2_m_threshold_18_address1();
void thread_threshs2_m_threshold_18_ce0();
void thread_threshs2_m_threshold_18_ce1();
void thread_threshs2_m_threshold_18_d0();
void thread_threshs2_m_threshold_18_d1();
void thread_threshs2_m_threshold_18_we0();
void thread_threshs2_m_threshold_18_we1();
void thread_threshs2_m_threshold_19_address0();
void thread_threshs2_m_threshold_19_address1();
void thread_threshs2_m_threshold_19_ce0();
void thread_threshs2_m_threshold_19_ce1();
void thread_threshs2_m_threshold_19_d0();
void thread_threshs2_m_threshold_19_d1();
void thread_threshs2_m_threshold_19_we0();
void thread_threshs2_m_threshold_19_we1();
void thread_threshs2_m_threshold_1_address0();
void thread_threshs2_m_threshold_1_address1();
void thread_threshs2_m_threshold_1_ce0();
void thread_threshs2_m_threshold_1_ce1();
void thread_threshs2_m_threshold_1_d0();
void thread_threshs2_m_threshold_1_d1();
void thread_threshs2_m_threshold_1_we0();
void thread_threshs2_m_threshold_1_we1();
void thread_threshs2_m_threshold_20_address0();
void thread_threshs2_m_threshold_20_address1();
void thread_threshs2_m_threshold_20_ce0();
void thread_threshs2_m_threshold_20_ce1();
void thread_threshs2_m_threshold_20_d0();
void thread_threshs2_m_threshold_20_d1();
void thread_threshs2_m_threshold_20_we0();
void thread_threshs2_m_threshold_20_we1();
void thread_threshs2_m_threshold_21_address0();
void thread_threshs2_m_threshold_21_address1();
void thread_threshs2_m_threshold_21_ce0();
void thread_threshs2_m_threshold_21_ce1();
void thread_threshs2_m_threshold_21_d0();
void thread_threshs2_m_threshold_21_d1();
void thread_threshs2_m_threshold_21_we0();
void thread_threshs2_m_threshold_21_we1();
void thread_threshs2_m_threshold_22_address0();
void thread_threshs2_m_threshold_22_address1();
void thread_threshs2_m_threshold_22_ce0();
void thread_threshs2_m_threshold_22_ce1();
void thread_threshs2_m_threshold_22_d0();
void thread_threshs2_m_threshold_22_d1();
void thread_threshs2_m_threshold_22_we0();
void thread_threshs2_m_threshold_22_we1();
void thread_threshs2_m_threshold_23_address0();
void thread_threshs2_m_threshold_23_address1();
void thread_threshs2_m_threshold_23_ce0();
void thread_threshs2_m_threshold_23_ce1();
void thread_threshs2_m_threshold_23_d0();
void thread_threshs2_m_threshold_23_d1();
void thread_threshs2_m_threshold_23_we0();
void thread_threshs2_m_threshold_23_we1();
void thread_threshs2_m_threshold_24_address0();
void thread_threshs2_m_threshold_24_address1();
void thread_threshs2_m_threshold_24_ce0();
void thread_threshs2_m_threshold_24_ce1();
void thread_threshs2_m_threshold_24_d0();
void thread_threshs2_m_threshold_24_d1();
void thread_threshs2_m_threshold_24_we0();
void thread_threshs2_m_threshold_24_we1();
void thread_threshs2_m_threshold_25_address0();
void thread_threshs2_m_threshold_25_address1();
void thread_threshs2_m_threshold_25_ce0();
void thread_threshs2_m_threshold_25_ce1();
void thread_threshs2_m_threshold_25_d0();
void thread_threshs2_m_threshold_25_d1();
void thread_threshs2_m_threshold_25_we0();
void thread_threshs2_m_threshold_25_we1();
void thread_threshs2_m_threshold_26_address0();
void thread_threshs2_m_threshold_26_address1();
void thread_threshs2_m_threshold_26_ce0();
void thread_threshs2_m_threshold_26_ce1();
void thread_threshs2_m_threshold_26_d0();
void thread_threshs2_m_threshold_26_d1();
void thread_threshs2_m_threshold_26_we0();
void thread_threshs2_m_threshold_26_we1();
void thread_threshs2_m_threshold_27_address0();
void thread_threshs2_m_threshold_27_address1();
void thread_threshs2_m_threshold_27_ce0();
void thread_threshs2_m_threshold_27_ce1();
void thread_threshs2_m_threshold_27_d0();
void thread_threshs2_m_threshold_27_d1();
void thread_threshs2_m_threshold_27_we0();
void thread_threshs2_m_threshold_27_we1();
void thread_threshs2_m_threshold_28_address0();
void thread_threshs2_m_threshold_28_address1();
void thread_threshs2_m_threshold_28_ce0();
void thread_threshs2_m_threshold_28_ce1();
void thread_threshs2_m_threshold_28_d0();
void thread_threshs2_m_threshold_28_d1();
void thread_threshs2_m_threshold_28_we0();
void thread_threshs2_m_threshold_28_we1();
void thread_threshs2_m_threshold_29_address0();
void thread_threshs2_m_threshold_29_address1();
void thread_threshs2_m_threshold_29_ce0();
void thread_threshs2_m_threshold_29_ce1();
void thread_threshs2_m_threshold_29_d0();
void thread_threshs2_m_threshold_29_d1();
void thread_threshs2_m_threshold_29_we0();
void thread_threshs2_m_threshold_29_we1();
void thread_threshs2_m_threshold_2_address0();
void thread_threshs2_m_threshold_2_address1();
void thread_threshs2_m_threshold_2_ce0();
void thread_threshs2_m_threshold_2_ce1();
void thread_threshs2_m_threshold_2_d0();
void thread_threshs2_m_threshold_2_d1();
void thread_threshs2_m_threshold_2_we0();
void thread_threshs2_m_threshold_2_we1();
void thread_threshs2_m_threshold_30_address0();
void thread_threshs2_m_threshold_30_address1();
void thread_threshs2_m_threshold_30_ce0();
void thread_threshs2_m_threshold_30_ce1();
void thread_threshs2_m_threshold_30_d0();
void thread_threshs2_m_threshold_30_d1();
void thread_threshs2_m_threshold_30_we0();
void thread_threshs2_m_threshold_30_we1();
void thread_threshs2_m_threshold_31_address0();
void thread_threshs2_m_threshold_31_address1();
void thread_threshs2_m_threshold_31_ce0();
void thread_threshs2_m_threshold_31_ce1();
void thread_threshs2_m_threshold_31_d0();
void thread_threshs2_m_threshold_31_d1();
void thread_threshs2_m_threshold_31_we0();
void thread_threshs2_m_threshold_31_we1();
void thread_threshs2_m_threshold_3_address0();
void thread_threshs2_m_threshold_3_address1();
void thread_threshs2_m_threshold_3_ce0();
void thread_threshs2_m_threshold_3_ce1();
void thread_threshs2_m_threshold_3_d0();
void thread_threshs2_m_threshold_3_d1();
void thread_threshs2_m_threshold_3_we0();
void thread_threshs2_m_threshold_3_we1();
void thread_threshs2_m_threshold_4_address0();
void thread_threshs2_m_threshold_4_address1();
void thread_threshs2_m_threshold_4_ce0();
void thread_threshs2_m_threshold_4_ce1();
void thread_threshs2_m_threshold_4_d0();
void thread_threshs2_m_threshold_4_d1();
void thread_threshs2_m_threshold_4_we0();
void thread_threshs2_m_threshold_4_we1();
void thread_threshs2_m_threshold_5_address0();
void thread_threshs2_m_threshold_5_address1();
void thread_threshs2_m_threshold_5_ce0();
void thread_threshs2_m_threshold_5_ce1();
void thread_threshs2_m_threshold_5_d0();
void thread_threshs2_m_threshold_5_d1();
void thread_threshs2_m_threshold_5_we0();
void thread_threshs2_m_threshold_5_we1();
void thread_threshs2_m_threshold_6_address0();
void thread_threshs2_m_threshold_6_address1();
void thread_threshs2_m_threshold_6_ce0();
void thread_threshs2_m_threshold_6_ce1();
void thread_threshs2_m_threshold_6_d0();
void thread_threshs2_m_threshold_6_d1();
void thread_threshs2_m_threshold_6_we0();
void thread_threshs2_m_threshold_6_we1();
void thread_threshs2_m_threshold_7_address0();
void thread_threshs2_m_threshold_7_address1();
void thread_threshs2_m_threshold_7_ce0();
void thread_threshs2_m_threshold_7_ce1();
void thread_threshs2_m_threshold_7_d0();
void thread_threshs2_m_threshold_7_d1();
void thread_threshs2_m_threshold_7_we0();
void thread_threshs2_m_threshold_7_we1();
void thread_threshs2_m_threshold_8_address0();
void thread_threshs2_m_threshold_8_address1();
void thread_threshs2_m_threshold_8_ce0();
void thread_threshs2_m_threshold_8_ce1();
void thread_threshs2_m_threshold_8_d0();
void thread_threshs2_m_threshold_8_d1();
void thread_threshs2_m_threshold_8_we0();
void thread_threshs2_m_threshold_8_we1();
void thread_threshs2_m_threshold_9_address0();
void thread_threshs2_m_threshold_9_address1();
void thread_threshs2_m_threshold_9_ce0();
void thread_threshs2_m_threshold_9_ce1();
void thread_threshs2_m_threshold_9_d0();
void thread_threshs2_m_threshold_9_d1();
void thread_threshs2_m_threshold_9_we0();
void thread_threshs2_m_threshold_9_we1();
void thread_threshs2_m_threshold_address0();
void thread_threshs2_m_threshold_address1();
void thread_threshs2_m_threshold_ce0();
void thread_threshs2_m_threshold_ce1();
void thread_threshs2_m_threshold_d0();
void thread_threshs2_m_threshold_d1();
void thread_threshs2_m_threshold_we0();
void thread_threshs2_m_threshold_we1();
void thread_threshs3_m_threshold_10_address0();
void thread_threshs3_m_threshold_10_address1();
void thread_threshs3_m_threshold_10_ce0();
void thread_threshs3_m_threshold_10_ce1();
void thread_threshs3_m_threshold_10_d0();
void thread_threshs3_m_threshold_10_d1();
void thread_threshs3_m_threshold_10_we0();
void thread_threshs3_m_threshold_10_we1();
void thread_threshs3_m_threshold_11_address0();
void thread_threshs3_m_threshold_11_address1();
void thread_threshs3_m_threshold_11_ce0();
void thread_threshs3_m_threshold_11_ce1();
void thread_threshs3_m_threshold_11_d0();
void thread_threshs3_m_threshold_11_d1();
void thread_threshs3_m_threshold_11_we0();
void thread_threshs3_m_threshold_11_we1();
void thread_threshs3_m_threshold_12_address0();
void thread_threshs3_m_threshold_12_address1();
void thread_threshs3_m_threshold_12_ce0();
void thread_threshs3_m_threshold_12_ce1();
void thread_threshs3_m_threshold_12_d0();
void thread_threshs3_m_threshold_12_d1();
void thread_threshs3_m_threshold_12_we0();
void thread_threshs3_m_threshold_12_we1();
void thread_threshs3_m_threshold_13_address0();
void thread_threshs3_m_threshold_13_address1();
void thread_threshs3_m_threshold_13_ce0();
void thread_threshs3_m_threshold_13_ce1();
void thread_threshs3_m_threshold_13_d0();
void thread_threshs3_m_threshold_13_d1();
void thread_threshs3_m_threshold_13_we0();
void thread_threshs3_m_threshold_13_we1();
void thread_threshs3_m_threshold_14_address0();
void thread_threshs3_m_threshold_14_address1();
void thread_threshs3_m_threshold_14_ce0();
void thread_threshs3_m_threshold_14_ce1();
void thread_threshs3_m_threshold_14_d0();
void thread_threshs3_m_threshold_14_d1();
void thread_threshs3_m_threshold_14_we0();
void thread_threshs3_m_threshold_14_we1();
void thread_threshs3_m_threshold_15_address0();
void thread_threshs3_m_threshold_15_address1();
void thread_threshs3_m_threshold_15_ce0();
void thread_threshs3_m_threshold_15_ce1();
void thread_threshs3_m_threshold_15_d0();
void thread_threshs3_m_threshold_15_d1();
void thread_threshs3_m_threshold_15_we0();
void thread_threshs3_m_threshold_15_we1();
void thread_threshs3_m_threshold_1_address0();
void thread_threshs3_m_threshold_1_address1();
void thread_threshs3_m_threshold_1_ce0();
void thread_threshs3_m_threshold_1_ce1();
void thread_threshs3_m_threshold_1_d0();
void thread_threshs3_m_threshold_1_d1();
void thread_threshs3_m_threshold_1_we0();
void thread_threshs3_m_threshold_1_we1();
void thread_threshs3_m_threshold_2_address0();
void thread_threshs3_m_threshold_2_address1();
void thread_threshs3_m_threshold_2_ce0();
void thread_threshs3_m_threshold_2_ce1();
void thread_threshs3_m_threshold_2_d0();
void thread_threshs3_m_threshold_2_d1();
void thread_threshs3_m_threshold_2_we0();
void thread_threshs3_m_threshold_2_we1();
void thread_threshs3_m_threshold_3_address0();
void thread_threshs3_m_threshold_3_address1();
void thread_threshs3_m_threshold_3_ce0();
void thread_threshs3_m_threshold_3_ce1();
void thread_threshs3_m_threshold_3_d0();
void thread_threshs3_m_threshold_3_d1();
void thread_threshs3_m_threshold_3_we0();
void thread_threshs3_m_threshold_3_we1();
void thread_threshs3_m_threshold_4_address0();
void thread_threshs3_m_threshold_4_address1();
void thread_threshs3_m_threshold_4_ce0();
void thread_threshs3_m_threshold_4_ce1();
void thread_threshs3_m_threshold_4_d0();
void thread_threshs3_m_threshold_4_d1();
void thread_threshs3_m_threshold_4_we0();
void thread_threshs3_m_threshold_4_we1();
void thread_threshs3_m_threshold_5_address0();
void thread_threshs3_m_threshold_5_address1();
void thread_threshs3_m_threshold_5_ce0();
void thread_threshs3_m_threshold_5_ce1();
void thread_threshs3_m_threshold_5_d0();
void thread_threshs3_m_threshold_5_d1();
void thread_threshs3_m_threshold_5_we0();
void thread_threshs3_m_threshold_5_we1();
void thread_threshs3_m_threshold_6_address0();
void thread_threshs3_m_threshold_6_address1();
void thread_threshs3_m_threshold_6_ce0();
void thread_threshs3_m_threshold_6_ce1();
void thread_threshs3_m_threshold_6_d0();
void thread_threshs3_m_threshold_6_d1();
void thread_threshs3_m_threshold_6_we0();
void thread_threshs3_m_threshold_6_we1();
void thread_threshs3_m_threshold_7_address0();
void thread_threshs3_m_threshold_7_address1();
void thread_threshs3_m_threshold_7_ce0();
void thread_threshs3_m_threshold_7_ce1();
void thread_threshs3_m_threshold_7_d0();
void thread_threshs3_m_threshold_7_d1();
void thread_threshs3_m_threshold_7_we0();
void thread_threshs3_m_threshold_7_we1();
void thread_threshs3_m_threshold_8_address0();
void thread_threshs3_m_threshold_8_address1();
void thread_threshs3_m_threshold_8_ce0();
void thread_threshs3_m_threshold_8_ce1();
void thread_threshs3_m_threshold_8_d0();
void thread_threshs3_m_threshold_8_d1();
void thread_threshs3_m_threshold_8_we0();
void thread_threshs3_m_threshold_8_we1();
void thread_threshs3_m_threshold_9_address0();
void thread_threshs3_m_threshold_9_address1();
void thread_threshs3_m_threshold_9_ce0();
void thread_threshs3_m_threshold_9_ce1();
void thread_threshs3_m_threshold_9_d0();
void thread_threshs3_m_threshold_9_d1();
void thread_threshs3_m_threshold_9_we0();
void thread_threshs3_m_threshold_9_we1();
void thread_threshs3_m_threshold_address0();
void thread_threshs3_m_threshold_address1();
void thread_threshs3_m_threshold_ce0();
void thread_threshs3_m_threshold_ce1();
void thread_threshs3_m_threshold_d0();
void thread_threshs3_m_threshold_d1();
void thread_threshs3_m_threshold_we0();
void thread_threshs3_m_threshold_we1();
void thread_weights0_m_weights_V_10_address0();
void thread_weights0_m_weights_V_10_address1();
void thread_weights0_m_weights_V_10_ce0();
void thread_weights0_m_weights_V_10_ce1();
void thread_weights0_m_weights_V_10_d0();
void thread_weights0_m_weights_V_10_d1();
void thread_weights0_m_weights_V_10_we0();
void thread_weights0_m_weights_V_10_we1();
void thread_weights0_m_weights_V_11_address0();
void thread_weights0_m_weights_V_11_address1();
void thread_weights0_m_weights_V_11_ce0();
void thread_weights0_m_weights_V_11_ce1();
void thread_weights0_m_weights_V_11_d0();
void thread_weights0_m_weights_V_11_d1();
void thread_weights0_m_weights_V_11_we0();
void thread_weights0_m_weights_V_11_we1();
void thread_weights0_m_weights_V_12_address0();
void thread_weights0_m_weights_V_12_address1();
void thread_weights0_m_weights_V_12_ce0();
void thread_weights0_m_weights_V_12_ce1();
void thread_weights0_m_weights_V_12_d0();
void thread_weights0_m_weights_V_12_d1();
void thread_weights0_m_weights_V_12_we0();
void thread_weights0_m_weights_V_12_we1();
void thread_weights0_m_weights_V_13_address0();
void thread_weights0_m_weights_V_13_address1();
void thread_weights0_m_weights_V_13_ce0();
void thread_weights0_m_weights_V_13_ce1();
void thread_weights0_m_weights_V_13_d0();
void thread_weights0_m_weights_V_13_d1();
void thread_weights0_m_weights_V_13_we0();
void thread_weights0_m_weights_V_13_we1();
void thread_weights0_m_weights_V_14_address0();
void thread_weights0_m_weights_V_14_address1();
void thread_weights0_m_weights_V_14_ce0();
void thread_weights0_m_weights_V_14_ce1();
void thread_weights0_m_weights_V_14_d0();
void thread_weights0_m_weights_V_14_d1();
void thread_weights0_m_weights_V_14_we0();
void thread_weights0_m_weights_V_14_we1();
void thread_weights0_m_weights_V_15_address0();
void thread_weights0_m_weights_V_15_address1();
void thread_weights0_m_weights_V_15_ce0();
void thread_weights0_m_weights_V_15_ce1();
void thread_weights0_m_weights_V_15_d0();
void thread_weights0_m_weights_V_15_d1();
void thread_weights0_m_weights_V_15_we0();
void thread_weights0_m_weights_V_15_we1();
void thread_weights0_m_weights_V_16_address0();
void thread_weights0_m_weights_V_16_address1();
void thread_weights0_m_weights_V_16_ce0();
void thread_weights0_m_weights_V_16_ce1();
void thread_weights0_m_weights_V_16_d0();
void thread_weights0_m_weights_V_16_d1();
void thread_weights0_m_weights_V_16_we0();
void thread_weights0_m_weights_V_16_we1();
void thread_weights0_m_weights_V_17_address0();
void thread_weights0_m_weights_V_17_address1();
void thread_weights0_m_weights_V_17_ce0();
void thread_weights0_m_weights_V_17_ce1();
void thread_weights0_m_weights_V_17_d0();
void thread_weights0_m_weights_V_17_d1();
void thread_weights0_m_weights_V_17_we0();
void thread_weights0_m_weights_V_17_we1();
void thread_weights0_m_weights_V_18_address0();
void thread_weights0_m_weights_V_18_address1();
void thread_weights0_m_weights_V_18_ce0();
void thread_weights0_m_weights_V_18_ce1();
void thread_weights0_m_weights_V_18_d0();
void thread_weights0_m_weights_V_18_d1();
void thread_weights0_m_weights_V_18_we0();
void thread_weights0_m_weights_V_18_we1();
void thread_weights0_m_weights_V_19_address0();
void thread_weights0_m_weights_V_19_address1();
void thread_weights0_m_weights_V_19_ce0();
void thread_weights0_m_weights_V_19_ce
|
1();
void thread_weights0_m_weights_V_19_d0();
void thread_weights0_m_weights_V_19_d1();
void thread_weights0_m_weights_V_19_we0();
void thread_weights0_m_weights_V_19_we1();
void thread_weights0_m_weights_V_1_address0();
void thread_weights0_m_weights_V_1_address1();
void thread_weights0_m_weights_V_1_ce0();
void thread_weights0_m_weights_V_1_ce1();
void thread_weights0_m_weights_V_1_d0();
void thread_weights0_m_weights_V_1_d1();
void thread_weights0_m_weights_V_1_we0();
void thread_weights0_m_weights_V_1_we1();
void thread_weights0_m_weights_V_20_address0();
void thread_weights0_m_weights_V_20_address1();
void thread_weights0_m_weights_V_20_ce0();
void thread_weights0_m_weights_V_20_ce1();
void thread_weights0_m_weights_V_20_d0();
void thread_weights0_m_weights_V_20_d1();
void thread_weights0_m_weights_V_20_we0();
void thread_weights0_m_weights_V_20_we1();
void thread_weights0_m_weights_V_21_address0();
void thread_weights0_m_weights_V_21_address1();
void thread_weights0_m_weights_V_21_ce0();
void thread_weights0_m_weights_V_21_ce1();
void thread_weights0_m_weights_V_21_d0();
void thread_weights0_m_weights_V_21_d1();
void thread_weights0_m_weights_V_21_we0();
void thread_weights0_m_weights_V_21_we1();
void thread_weights0_m_weights_V_22_address0();
void thread_weights0_m_weights_V_22_address1();
void thread_weights0_m_weights_V_22_ce0();
void thread_weights0_m_weights_V_22_ce1();
void thread_weights0_m_weights_V_22_d0();
void thread_weights0_m_weights_V_22_d1();
void thread_weights0_m_weights_V_22_we0();
void thread_weights0_m_weights_V_22_we1();
void thread_weights0_m_weights_V_23_address0();
void thread_weights0_m_weights_V_23_address1();
void thread_weights0_m_weights_V_23_ce0();
void thread_weights0_m_weights_V_23_ce1();
void thread_weights0_m_weights_V_23_d0();
void thread_weights0_m_weights_V_23_d1();
void thread_weights0_m_weights_V_23_we0();
void thread_weights0_m_weights_V_23_we1();
void thread_weights0_m_weights_V_24_address0();
void thread_weights0_m_weights_V_24_address1();
void thread_weights0_m_weights_V_24_ce0();
void thread_weights0_m_weights_V_24_ce1();
void thread_weights0_m_weights_V_24_d0();
void thread_weights0_m_weights_V_24_d1();
void thread_weights0_m_weights_V_24_we0();
void thread_weights0_m_weights_V_24_we1();
void thread_weights0_m_weights_V_25_address0();
void thread_weights0_m_weights_V_25_address1();
void thread_weights0_m_weights_V_25_ce0();
void thread_weights0_m_weights_V_25_ce1();
void thread_weights0_m_weights_V_25_d0();
void thread_weights0_m_weights_V_25_d1();
void thread_weights0_m_weights_V_25_we0();
void thread_weights0_m_weights_V_25_we1();
void thread_weights0_m_weights_V_26_address0();
void thread_weights0_m_weights_V_26_address1();
void thread_weights0_m_weights_V_26_ce0();
void thread_weights0_m_weights_V_26_ce1();
void thread_weights0_m_weights_V_26_d0();
void thread_weights0_m_weights_V_26_d1();
void thread_weights0_m_weights_V_26_we0();
void thread_weights0_m_weights_V_26_we1();
void thread_weights0_m_weights_V_27_address0();
void thread_weights0_m_weights_V_27_address1();
void thread_weights0_m_weights_V_27_ce0();
void thread_weights0_m_weights_V_27_ce1();
void thread_weights0_m_weights_V_27_d0();
void thread_weights0_m_weights_V_27_d1();
void thread_weights0_m_weights_V_27_we0();
void thread_weights0_m_weights_V_27_we1();
void thread_weights0_m_weights_V_28_address0();
void thread_weights0_m_weights_V_28_address1();
void thread_weights0_m_weights_V_28_ce0();
void thread_weights0_m_weights_V_28_ce1();
void thread_weights0_m_weights_V_28_d0();
void thread_weights0_m_weights_V_28_d1();
void thread_weights0_m_weights_V_28_we0();
void thread_weights0_m_weights_V_28_we1();
void thread_weights0_m_weights_V_29_address0();
void thread_weights0_m_weights_V_29_address1();
void thread_weights0_m_weights_V_29_ce0();
void thread_weights0_m_weights_V_29_ce1();
void thread_weights0_m_weights_V_29_d0();
void thread_weights0_m_weights_V_29_d1();
void thread_weights0_m_weights_V_29_we0();
void thread_weights0_m_weights_V_29_we1();
void thread_weights0_m_weights_V_2_address0();
void thread_weights0_m_weights_V_2_address1();
void thread_weights0_m_weights_V_2_ce0();
void thread_weights0_m_weights_V_2_ce1();
void thread_weights0_m_weights_V_2_d0();
void thread_weights0_m_weights_V_2_d1();
void thread_weights0_m_weights_V_2_we0();
void thread_weights0_m_weights_V_2_we1();
void thread_weights0_m_weights_V_30_address0();
void thread_weights0_m_weights_V_30_address1();
void thread_weights0_m_weights_V_30_ce0();
void thread_weights0_m_weights_V_30_ce1();
void thread_weights0_m_weights_V_30_d0();
void thread_weights0_m_weights_V_30_d1();
void thread_weights0_m_weights_V_30_we0();
void thread_weights0_m_weights_V_30_we1();
void thread_weights0_m_weights_V_31_address0();
void thread_weights0_m_weights_V_31_address1();
void thread_weights0_m_weights_V_31_ce0();
void thread_weights0_m_weights_V_31_ce1();
void thread_weights0_m_weights_V_31_d0();
void thread_weights0_m_weights_V_31_d1();
void thread_weights0_m_weights_V_31_we0();
void thread_weights0_m_weights_V_31_we1();
void thread_weights0_m_weights_V_3_address0();
void thread_weights0_m_weights_V_3_address1();
void thread_weights0_m_weights_V_3_ce0();
void thread_weights0_m_weights_V_3_ce1();
void thread_weights0_m_weights_V_3_d0();
void thread_weights0_m_weights_V_3_d1();
void thread_weights0_m_weights_V_3_we0();
void thread_weights0_m_weights_V_3_we1();
void thread_weights0_m_weights_V_4_address0();
void thread_weights0_m_weights_V_4_address1();
void thread_weights0_m_weights_V_4_ce0();
void thread_weights0_m_weights_V_4_ce1();
void thread_weights0_m_weights_V_4_d0();
void thread_weights0_m_weights_V_4_d1();
void thread_weights0_m_weights_V_4_we0();
void thread_weights0_m_weights_V_4_we1();
void thread_weights0_m_weights_V_5_address0();
void thread_weights0_m_weights_V_5_address1();
void thread_weights0_m_weights_V_5_ce0();
void thread_weights0_m_weights_V_5_ce1();
void thread_weights0_m_weights_V_5_d0();
void thread_weights0_m_weights_V_5_d1();
void thread_weights0_m_weights_V_5_we0();
void thread_weights0_m_weights_V_5_we1();
void thread_weights0_m_weights_V_6_address0();
void thread_weights0_m_weights_V_6_address1();
void thread_weights0_m_weights_V_6_ce0();
void thread_weights0_m_weights_V_6_ce1();
void thread_weights0_m_weights_V_6_d0();
void thread_weights0_m_weights_V_6_d1();
void thread_weights0_m_weights_V_6_we0();
void thread_weights0_m_weights_V_6_we1();
void thread_weights0_m_weights_V_7_address0();
void thread_weights0_m_weights_V_7_address1();
void thread_weights0_m_weights_V_7_ce0();
void thread_weights0_m_weights_V_7_ce1();
void thread_weights0_m_weights_V_7_d0();
void thread_weights0_m_weights_V_7_d1();
void thread_weights0_m_weights_V_7_we0();
void thread_weights0_m_weights_V_7_we1();
void thread_weights0_m_weights_V_8_address0();
void thread_weights0_m_weights_V_8_address1();
void thread_weights0_m_weights_V_8_ce0();
void thread_weights0_m_weights_V_8_ce1();
void thread_weights0_m_weights_V_8_d0();
void thread_weights0_m_weights_V_8_d1();
void thread_weights0_m_weights_V_8_we0();
void thread_weights0_m_weights_V_8_we1();
void thread_weights0_m_weights_V_9_address0();
void thread_weights0_m_weights_V_9_address1();
void thread_weights0_m_weights_V_9_ce0();
void thread_weights0_m_weights_V_9_ce1();
void thread_weights0_m_weights_V_9_d0();
void thread_weights0_m_weights_V_9_d1();
void thread_weights0_m_weights_V_9_we0();
void thread_weights0_m_weights_V_9_we1();
void thread_weights0_m_weights_V_address0();
void thread_weights0_m_weights_V_address1();
void thread_weights0_m_weights_V_ce0();
void thread_weights0_m_weights_V_ce1();
void thread_weights0_m_weights_V_d0();
void thread_weights0_m_weights_V_d1();
void thread_weights0_m_weights_V_we0();
void thread_weights0_m_weights_V_we1();
void thread_weights1_m_weights_V_10_address0();
void thread_weights1_m_weights_V_10_address1();
void thread_weights1_m_weights_V_10_ce0();
void thread_weights1_m_weights_V_10_ce1();
void thread_weights1_m_weights_V_10_d0();
void thread_weights1_m_weights_V_10_d1();
void thread_weights1_m_weights_V_10_we0();
void thread_weights1_m_weights_V_10_we1();
void thread_weights1_m_weights_V_11_address0();
void thread_weights1_m_weights_V_11_address1();
void thread_weights1_m_weights_V_11_ce0();
void thread_weights1_m_weights_V_11_ce1();
void thread_weights1_m_weights_V_11_d0();
void thread_weights1_m_weights_V_11_d1();
void thread_weights1_m_weights_V_11_we0();
void thread_weights1_m_weights_V_11_we1();
void thread_weights1_m_weights_V_12_address0();
void thread_weights1_m_weights_V_12_address1();
void thread_weights1_m_weights_V_12_ce0();
void thread_weights1_m_weights_V_12_ce1();
void thread_weights1_m_weights_V_12_d0();
void thread_weights1_m_weights_V_12_d1();
void thread_weights1_m_weights_V_12_we0();
void thread_weights1_m_weights_V_12_we1();
void thread_weights1_m_weights_V_13_address0();
void thread_weights1_m_weights_V_13_address1();
void thread_weights1_m_weights_V_13_ce0();
void thread_weights1_m_weights_V_13_ce1();
void thread_weights1_m_weights_V_13_d0();
void thread_weights1_m_weights_V_13_d1();
void thread_weights1_m_weights_V_13_we0();
void thread_weights1_m_weights_V_13_we1();
void thread_weights1_m_weights_V_14_address0();
void thread_weights1_m_weights_V_14_address1();
void thread_weights1_m_weights_V_14_ce0();
void thread_weights1_m_weights_V_14_ce1();
void thread_weights1_m_weights_V_14_d0();
void thread_weights1_m_weights_V_14_d1();
void thread_weights1_m_weights_V_14_we0();
void thread_weights1_m_weights_V_14_we1();
void thread_weights1_m_weights_V_15_address0();
void thread_weights1_m_weights_V_15_address1();
void thread_weights1_m_weights_V_15_ce0();
void thread_weights1_m_weights_V_15_ce1();
void thread_weights1_m_weights_V_15_d0();
void thread_weights1_m_weights_V_15_d1();
void thread_weights1_m_weights_V_15_we0();
void thread_weights1_m_weights_V_15_we1();
void thread_weights1_m_weights_V_16_address0();
void thread_weights1_m_weights_V_16_address1();
void thread_weights1_m_weights_V_16_ce0();
void thread_weights1_m_weights_V_16_ce1();
void thread_weights1_m_weights_V_16_d0();
void thread_weights1_m_weights_V_16_d1();
void thread_weights1_m_weights_V_16_we0();
void thread_weights1_m_weights_V_16_we1();
void thread_weights1_m_weights_V_17_address0();
void thread_weights1_m_weights_V_17_address1();
void thread_weights1_m_weights_V_17_ce0();
void thread_weights1_m_weights_V_17_ce1();
void thread_weights1_m_weights_V_17_d0();
void thread_weights1_m_weights_V_17_d1();
void thread_weights1_m_weights_V_17_we0();
void thread_weights1_m_weights_V_17_we1();
void thread_weights1_m_weights_V_18_address0();
void thread_weights1_m_weights_V_18_address1();
void thread_weights1_m_weights_V_18_ce0();
void thread_weights1_m_weights_V_18_ce1();
void thread_weights1_m_weights_V_18_d0();
void thread_weights1_m_weights_V_18_d1();
void thread_weights1_m_weights_V_18_we0();
void thread_weights1_m_weights_V_18_we1();
void thread_weights1_m_weights_V_19_address0();
void thread_weights1_m_weights_V_19_address1();
void thread_weights1_m_weights_V_19_ce0();
void thread_weights1_m_weights_V_19_ce1();
void thread_weights1_m_weights_V_19_d0();
void thread_weights1_m_weights_V_19_d1();
void thread_weights1_m_weights_V_19_we0();
void thread_weights1_m_weights_V_19_we1();
void thread_weights1_m_weights_V_1_address0();
void thread_weights1_m_weights_V_1_address1();
void thread_weights1_m_weights_V_1_ce0();
void thread_weights1_m_weights_V_1_ce1();
void thread_weights1_m_weights_V_1_d0();
void thread_weights1_m_weights_V_1_d1();
void thread_weights1_m_weights_V_1_we0();
void thread_weights1_m_weights_V_1_we1();
void thread_weights1_m_weights_V_20_address0();
void thread_weights1_m_weights_V_20_address1();
void thread_weights1_m_weights_V_20_ce0();
void thread_weights1_m_weights_V_20_ce1();
void thread_weights1_m_weights_V_20_d0();
void thread_weights1_m_weights_V_20_d1();
void thread_weights1_m_weights_V_20_we0();
void thread_weights1_m_weights_V_20_we1();
void thread_weights1_m_weights_V_21_address0();
void thread_weights1_m_weights_V_21_address1();
void thread_weights1_m_weights_V_21_ce0();
void thread_weights1_m_weights_V_21_ce1();
void thread_weights1_m_weights_V_21_d0();
void thread_weights1_m_weights_V_21_d1();
void thread_weights1_m_weights_V_21_we0();
void thread_weights1_m_weights_V_21_we1();
void thread_weights1_m_weights_V_22_address0();
void thread_weights1_m_weights_V_22_address1();
void thread_weights1_m_weights_V_22_ce0();
void thread_weights1_m_weights_V_22_ce1();
void thread_weights1_m_weights_V_22_d0();
void thread_weights1_m_weights_V_22_d1();
void thread_weights1_m_weights_V_22_we0();
void thread_weights1_m_weights_V_22_we1();
void thread_weights1_m_weights_V_23_address0();
void thread_weights1_m_weights_V_23_address1();
void thread_weights1_m_weights_V_23_ce0();
void thread_weights1_m_weights_V_23_ce1();
void thread_weights1_m_weights_V_23_d0();
void thread_weights1_m_weights_V_23_d1();
void thread_weights1_m_weights_V_23_we0();
void thread_weights1_m_weights_V_23_we1();
void thread_weights1_m_weights_V_24_address0();
void thread_weights1_m_weights_V_24_address1();
void thread_weights1_m_weights_V_24_ce0();
void thread_weights1_m_weights_V_24_ce1();
void thread_weights1_m_weights_V_24_d0();
void thread_weights1_m_weights_V_24_d1();
void thread_weights1_m_weights_V_24_we0();
void thread_weights1_m_weights_V_24_we1();
void thread_weights1_m_weights_V_25_address0();
void thread_weights1_m_weights_V_25_address1();
void thread_weights1_m_weights_V_25_ce0();
void thread_weights1_m_weights_V_25_ce1();
void thread_weights1_m_weights_V_25_d0();
void thread_weights1_m_weights_V_25_d1();
void thread_weights1_m_weights_V_25_we0();
void thread_weights1_m_weights_V_25_we1();
void thread_weights1_m_weights_V_26_address0();
void thread_weights1_m_weights_V_26_address1();
void thread_weights1_m_weights_V_26_ce0();
void thread_weights1_m_weights_V_26_ce1();
void thread_weights1_m_weights_V_26_d0();
void thread_weights1_m_weights_V_26_d1();
void thread_weights1_m_weights_V_26_we0();
void thread_weights1_m_weights_V_26_we1();
void thread_weights1_m_weights_V_27_address0();
void thread_weights1_m_weights_V_27_address1();
void thread_weights1_m_weights_V_27_ce0();
void thread_weights1_m_weights_V_27_ce1();
void thread_weights1_m_weights_V_27_d0();
void thread_weights1_m_weights_V_27_d1();
void thread_weights1_m_weights_V_27_we0();
void thread_weights1_m_weights_V_27_we1();
void thread_weights1_m_weights_V_28_address0();
void thread_weights1_m_weights_V_28_address1();
void thread_weights1_m_weights_V_28_ce0();
void thread_weights1_m_weights_V_28_ce1();
void thread_weights1_m_weights_V_28_d0();
void thread_weights1_m_weights_V_28_d1();
void thread_weights1_m_weights_V_28_we0();
void thread_weights1_m_weights_V_28_we1();
void thread_weights1_m_weights_V_29_address0();
void thread_weights1_m_weights_V_29_address1();
void thread_weights1_m_weights_V_29_ce0();
void thread_weights1_m_weights_V_29_ce1();
void thread_weights1_m_weights_V_29_d0();
void thread_weights1_m_weights_V_29_d1();
void thread_weights1_m_weights_V_29_we0();
void thread_weights1_m_weights_V_29_we1();
void thread_weights1_m_weights_V_2_address0();
void thread_weights1_m_weights_V_2_address1();
void thread_weights1_m_weights_V_2_ce0();
void thread_weights1_m_weights_V_2_ce1();
void thread_weights1_m_weights_V_2_d0();
void thread_weights1_m_weights_V_2_d1();
void thread_weights1_m_weights_V_2_we0();
void thread_weights1_m_weights_V_2_we1();
void thread_weights1_m_weights_V_30_address0();
void thread_weights1_m_weights_V_30_address1();
void thread_weights1_m_weights_V_30_ce0();
void thread_weights1_m_weights_V_30_ce1();
void thread_weights1_m_weights_V_30_d0();
void thread_weights1_m_weights_V_30_d1();
void thread_weights1_m_weights_V_30_we0();
void thread_weights1_m_weights_V_30_we1();
void thread_weights1_m_weights_V_31_address0();
void thread_weights1_m_weights_V_31_address1();
void thread_weights1_m_weights_V_31_ce0();
void thread_weights1_m_weights_V_31_ce1();
void thread_weights1_m_weights_V_31_d0();
void thread_weights1_m_weights_V_31_d1();
void thread_weights1_m_weights_V_31_we0();
void thread_weights1_m_weights_V_31_we1();
void thread_weights1_m_weights_V_32_address0();
void thread_weights1_m_weights_V_32_address1();
void thread_weights1_m_weights_V_32_ce0();
void thread_weights1_m_weights_V_32_ce1();
void thread_weights1_m_weights_V_32_d0();
void thread_weights1_m_weights_V_32_d1();
void thread_weights1_m_weights_V_32_we0();
void thread_weights1_m_weights_V_32_we1();
void thread_weights1_m_weights_V_33_address0();
void thread_weights1_m_weights_V_33_address1();
void thread_weights1_m_weights_V_33_ce0();
void thread_weights1_m_weights_V_33_ce1();
void thread_weights1_m_weights_V_33_d0();
void thread_weights1_m_weights_V_33_d1();
void thread_weights1_m_weights_V_33_we0();
void thread_weights1_m_weights_V_33_we1();
void thread_weights1_m_weights_V_34_address0();
void thread_weights1_m_weights_V_34_address1();
void thread_weights1_m_weights_V_34_ce0();
void thread_weights1_m_weights_V_34_ce1();
void thread_weights1_m_weights_V_34_d0();
void thread_weights1_m_weights_V_34_d1();
void thread_weights1_m_weights_V_34_we0();
void thread_weights1_m_weights_V_34_we1();
void thread_weights1_m_weights_V_35_address0();
void thread_weights1_m_weights_V_35_address1();
void thread_weights1_m_weights_V_35_ce0();
void thread_weights1_m_weights_V_35_ce1();
void thread_weights1_m_weights_V_35_d0();
void thread_weights1_m_weights_V_35_d1();
void thread_weights1_m_weights_V_35_we0();
void thread_weights1_m_weights_V_35_we1();
void thread_weights1_m_weights_V_36_address0();
void thread_weights1_m_weights_V_36_address1();
void thread_weights1_m_weights_V_36_ce0();
void thread_weights1_m_weights_V_36_ce1();
void thread_weights1_m_weights_V_36_d0();
void thread_weights1_m_weights_V_36_d1();
void thread_weights1_m_weights_V_36_we0();
void thread_weights1_m_weights_V_36_we1();
void thread_weights1_m_weights_V_37_address0();
void thread_weights1_m_weights_V_37_address1();
void thread_weights1_m_weights_V_37_ce0();
void thread_weights1_m_weights_V_37_ce1();
void thread_weights1_m_weights_V_37_d0();
void thread_weights1_m_weights_V_37_d1();
void thread_weights1_m_weights_V_37_we0();
|
void thread_weights1_m_weights_V_37_we1();
void thread_weights1_m_weights_V_38_address0();
void thread_weights1_m_weights_V_38_address1();
void thread_weights1_m_weights_V_38_ce0();
void thread_weights1_m_weights_V_38_ce1();
void thread_weights1_m_weights_V_38_d0();
void thread_weights1_m_weights_V_38_d1();
void thread_weights1_m_weights_V_38_we0();
void thread_weights1_m_weights_V_38_we1();
void thread_weights1_m_weights_V_39_address0();
void thread_weights1_m_weights_V_39_address1();
void thread_weights1_m_weights_V_39_ce0();
void thread_weights1_m_weights_V_39_ce1();
void thread_weights1_m_weights_V_39_d0();
void thread_weights1_m_weights_V_39_d1();
void thread_weights1_m_weights_V_39_we0();
void thread_weights1_m_weights_V_39_we1();
void thread_weights1_m_weights_V_3_address0();
void thread_weights1_m_weights_V_3_address1();
void thread_weights1_m_weights_V_3_ce0();
void thread_weights1_m_weights_V_3_ce1();
void thread_weights1_m_weights_V_3_d0();
void thread_weights1_m_weights_V_3_d1();
void thread_weights1_m_weights_V_3_we0();
void thread_weights1_m_weights_V_3_we1();
void thread_weights1_m_weights_V_40_address0();
void thread_weights1_m_weights_V_40_address1();
void thread_weights1_m_weights_V_40_ce0();
void thread_weights1_m_weights_V_40_ce1();
void thread_weights1_m_weights_V_40_d0();
void thread_weights1_m_weights_V_40_d1();
void thread_weights1_m_weights_V_40_we0();
void thread_weights1_m_weights_V_40_we1();
void thread_weights1_m_weights_V_41_address0();
void thread_weights1_m_weights_V_41_address1();
void thread_weights1_m_weights_V_41_ce0();
void thread_weights1_m_weights_V_41_ce1();
void thread_weights1_m_weights_V_41_d0();
void thread_weights1_m_weights_V_41_d1();
void thread_weights1_m_weights_V_41_we0();
void thread_weights1_m_weights_V_41_we1();
void thread_weights1_m_weights_V_42_address0();
void thread_weights1_m_weights_V_42_address1();
void thread_weights1_m_weights_V_42_ce0();
void thread_weights1_m_weights_V_42_ce1();
void thread_weights1_m_weights_V_42_d0();
void thread_weights1_m_weights_V_42_d1();
void thread_weights1_m_weights_V_42_we0();
void thread_weights1_m_weights_V_42_we1();
void thread_weights1_m_weights_V_43_address0();
void thread_weights1_m_weights_V_43_address1();
void thread_weights1_m_weights_V_43_ce0();
void thread_weights1_m_weights_V_43_ce1();
void thread_weights1_m_weights_V_43_d0();
void thread_weights1_m_weights_V_43_d1();
void thread_weights1_m_weights_V_43_we0();
void thread_weights1_m_weights_V_43_we1();
void thread_weights1_m_weights_V_44_address0();
void thread_weights1_m_weights_V_44_address1();
void thread_weights1_m_weights_V_44_ce0();
void thread_weights1_m_weights_V_44_ce1();
void thread_weights1_m_weights_V_44_d0();
void thread_weights1_m_weights_V_44_d1();
void thread_weights1_m_weights_V_44_we0();
void thread_weights1_m_weights_V_44_we1();
void thread_weights1_m_weights_V_45_address0();
void thread_weights1_m_weights_V_45_address1();
void thread_weights1_m_weights_V_45_ce0();
void thread_weights1_m_weights_V_45_ce1();
void thread_weights1_m_weights_V_45_d0();
void thread_weights1_m_weights_V_45_d1();
void thread_weights1_m_weights_V_45_we0();
void thread_weights1_m_weights_V_45_we1();
void thread_weights1_m_weights_V_46_address0();
void thread_weights1_m_weights_V_46_address1();
void thread_weights1_m_weights_V_46_ce0();
void thread_weights1_m_weights_V_46_ce1();
void thread_weights1_m_weights_V_46_d0();
void thread_weights1_m_weights_V_46_d1();
void thread_weights1_m_weights_V_46_we0();
void thread_weights1_m_weights_V_46_we1();
void thread_weights1_m_weights_V_47_address0();
void thread_weights1_m_weights_V_47_address1();
void thread_weights1_m_weights_V_47_ce0();
void thread_weights1_m_weights_V_47_ce1();
void thread_weights1_m_weights_V_47_d0();
void thread_weights1_m_weights_V_47_d1();
void thread_weights1_m_weights_V_47_we0();
void thread_weights1_m_weights_V_47_we1();
void thread_weights1_m_weights_V_48_address0();
void thread_weights1_m_weights_V_48_address1();
void thread_weights1_m_weights_V_48_ce0();
void thread_weights1_m_weights_V_48_ce1();
void thread_weights1_m_weights_V_48_d0();
void thread_weights1_m_weights_V_48_d1();
void thread_weights1_m_weights_V_48_we0();
void thread_weights1_m_weights_V_48_we1();
void thread_weights1_m_weights_V_49_address0();
void thread_weights1_m_weights_V_49_address1();
void thread_weights1_m_weights_V_49_ce0();
void thread_weights1_m_weights_V_49_ce1();
void thread_weights1_m_weights_V_49_d0();
void thread_weights1_m_weights_V_49_d1();
void thread_weights1_m_weights_V_49_we0();
void thread_weights1_m_weights_V_49_we1();
void thread_weights1_m_weights_V_4_address0();
void thread_weights1_m_weights_V_4_address1();
void thread_weights1_m_weights_V_4_ce0();
void thread_weights1_m_weights_V_4_ce1();
void thread_weights1_m_weights_V_4_d0();
void thread_weights1_m_weights_V_4_d1();
void thread_weights1_m_weights_V_4_we0();
void thread_weights1_m_weights_V_4_we1();
void thread_weights1_m_weights_V_50_address0();
void thread_weights1_m_weights_V_50_address1();
void thread_weights1_m_weights_V_50_ce0();
void thread_weights1_m_weights_V_50_ce1();
void thread_weights1_m_weights_V_50_d0();
void thread_weights1_m_weights_V_50_d1();
void thread_weights1_m_weights_V_50_we0();
void thread_weights1_m_weights_V_50_we1();
void thread_weights1_m_weights_V_51_address0();
void thread_weights1_m_weights_V_51_address1();
void thread_weights1_m_weights_V_51_ce0();
void thread_weights1_m_weights_V_51_ce1();
void thread_weights1_m_weights_V_51_d0();
void thread_weights1_m_weights_V_51_d1();
void thread_weights1_m_weights_V_51_we0();
void thread_weights1_m_weights_V_51_we1();
void thread_weights1_m_weights_V_52_address0();
void thread_weights1_m_weights_V_52_address1();
void thread_weights1_m_weights_V_52_ce0();
void thread_weights1_m_weights_V_52_ce1();
void thread_weights1_m_weights_V_52_d0();
void thread_weights1_m_weights_V_52_d1();
void thread_weights1_m_weights_V_52_we0();
void thread_weights1_m_weights_V_52_we1();
void thread_weights1_m_weights_V_53_address0();
void thread_weights1_m_weights_V_53_address1();
void thread_weights1_m_weights_V_53_ce0();
void thread_weights1_m_weights_V_53_ce1();
void thread_weights1_m_weights_V_53_d0();
void thread_weights1_m_weights_V_53_d1();
void thread_weights1_m_weights_V_53_we0();
void thread_weights1_m_weights_V_53_we1();
void thread_weights1_m_weights_V_54_address0();
void thread_weights1_m_weights_V_54_address1();
void thread_weights1_m_weights_V_54_ce0();
void thread_weights1_m_weights_V_54_ce1();
void thread_weights1_m_weights_V_54_d0();
void thread_weights1_m_weights_V_54_d1();
void thread_weights1_m_weights_V_54_we0();
void thread_weights1_m_weights_V_54_we1();
void thread_weights1_m_weights_V_55_address0();
void thread_weights1_m_weights_V_55_address1();
void thread_weights1_m_weights_V_55_ce0();
void thread_weights1_m_weights_V_55_ce1();
void thread_weights1_m_weights_V_55_d0();
void thread_weights1_m_weights_V_55_d1();
void thread_weights1_m_weights_V_55_we0();
void thread_weights1_m_weights_V_55_we1();
void thread_weights1_m_weights_V_56_address0();
void thread_weights1_m_weights_V_56_address1();
void thread_weights1_m_weights_V_56_ce0();
void thread_weights1_m_weights_V_56_ce1();
void thread_weights1_m_weights_V_56_d0();
void thread_weights1_m_weights_V_56_d1();
void thread_weights1_m_weights_V_56_we0();
void thread_weights1_m_weights_V_56_we1();
void thread_weights1_m_weights_V_57_address0();
void thread_weights1_m_weights_V_57_address1();
void thread_weights1_m_weights_V_57_ce0();
void thread_weights1_m_weights_V_57_ce1();
void thread_weights1_m_weights_V_57_d0();
void thread_weights1_m_weights_V_57_d1();
void thread_weights1_m_weights_V_57_we0();
void thread_weights1_m_weights_V_57_we1();
void thread_weights1_m_weights_V_58_address0();
void thread_weights1_m_weights_V_58_address1();
void thread_weights1_m_weights_V_58_ce0();
void thread_weights1_m_weights_V_58_ce1();
void thread_weights1_m_weights_V_58_d0();
void thread_weights1_m_weights_V_58_d1();
void thread_weights1_m_weights_V_58_we0();
void thread_weights1_m_weights_V_58_we1();
void thread_weights1_m_weights_V_59_address0();
void thread_weights1_m_weights_V_59_address1();
void thread_weights1_m_weights_V_59_ce0();
void thread_weights1_m_weights_V_59_ce1();
void thread_weights1_m_weights_V_59_d0();
void thread_weights1_m_weights_V_59_d1();
void thread_weights1_m_weights_V_59_we0();
void thread_weights1_m_weights_V_59_we1();
void thread_weights1_m_weights_V_5_address0();
void thread_weights1_m_weights_V_5_address1();
void thread_weights1_m_weights_V_5_ce0();
void thread_weights1_m_weights_V_5_ce1();
void thread_weights1_m_weights_V_5_d0();
void thread_weights1_m_weights_V_5_d1();
void thread_weights1_m_weights_V_5_we0();
void thread_weights1_m_weights_V_5_we1();
void thread_weights1_m_weights_V_60_address0();
void thread_weights1_m_weights_V_60_address1();
void thread_weights1_m_weights_V_60_ce0();
void thread_weights1_m_weights_V_60_ce1();
void thread_weights1_m_weights_V_60_d0();
void thread_weights1_m_weights_V_60_d1();
void thread_weights1_m_weights_V_60_we0();
void thread_weights1_m_weights_V_60_we1();
void thread_weights1_m_weights_V_61_address0();
void thread_weights1_m_weights_V_61_address1();
void thread_weights1_m_weights_V_61_ce0();
void thread_weights1_m_weights_V_61_ce1();
void thread_weights1_m_weights_V_61_d0();
void thread_weights1_m_weights_V_61_d1();
void thread_weights1_m_weights_V_61_we0();
void thread_weights1_m_weights_V_61_we1();
void thread_weights1_m_weights_V_62_address0();
void thread_weights1_m_weights_V_62_address1();
void thread_weights1_m_weights_V_62_ce0();
void thread_weights1_m_weights_V_62_ce1();
void thread_weights1_m_weights_V_62_d0();
void thread_weights1_m_weights_V_62_d1();
void thread_weights1_m_weights_V_62_we0();
void thread_weights1_m_weights_V_62_we1();
void thread_weights1_m_weights_V_63_address0();
void thread_weights1_m_weights_V_63_address1();
void thread_weights1_m_weights_V_63_ce0();
void thread_weights1_m_weights_V_63_ce1();
void thread_weights1_m_weights_V_63_d0();
void thread_weights1_m_weights_V_63_d1();
void thread_weights1_m_weights_V_63_we0();
void thread_weights1_m_weights_V_63_we1();
void thread_weights1_m_weights_V_6_address0();
void thread_weights1_m_weights_V_6_address1();
void thread_weights1_m_weights_V_6_ce0();
void thread_weights1_m_weights_V_6_ce1();
void thread_weights1_m_weights_V_6_d0();
void thread_weights1_m_weights_V_6_d1();
void thread_weights1_m_weights_V_6_we0();
void thread_weights1_m_weights_V_6_we1();
void thread_weights1_m_weights_V_7_address0();
void thread_weights1_m_weights_V_7_address1();
void thread_weights1_m_weights_V_7_ce0();
void thread_weights1_m_weights_V_7_ce1();
void thread_weights1_m_weights_V_7_d0();
void thread_weights1_m_weights_V_7_d1();
void thread_weights1_m_weights_V_7_we0();
void thread_weights1_m_weights_V_7_we1();
void thread_weights1_m_weights_V_8_address0();
void thread_weights1_m_weights_V_8_address1();
void thread_weights1_m_weights_V_8_ce0();
void thread_weights1_m_weights_V_8_ce1();
void thread_weights1_m_weights_V_8_d0();
void thread_weights1_m_weights_V_8_d1();
void thread_weights1_m_weights_V_8_we0();
void thread_weights1_m_weights_V_8_we1();
void thread_weights1_m_weights_V_9_address0();
void thread_weights1_m_weights_V_9_address1();
void thread_weights1_m_weights_V_9_ce0();
void thread_weights1_m_weights_V_9_ce1();
void thread_weights1_m_weights_V_9_d0();
void thread_weights1_m_weights_V_9_d1();
void thread_weights1_m_weights_V_9_we0();
void thread_weights1_m_weights_V_9_we1();
void thread_weights1_m_weights_V_address0();
void thread_weights1_m_weights_V_address1();
void thread_weights1_m_weights_V_ce0();
void thread_weights1_m_weights_V_ce1();
void thread_weights1_m_weights_V_d0();
void thread_weights1_m_weights_V_d1();
void thread_weights1_m_weights_V_we0();
void thread_weights1_m_weights_V_we1();
void thread_weights2_m_weights_V_10_address0();
void thread_weights2_m_weights_V_10_address1();
void thread_weights2_m_weights_V_10_ce0();
void thread_weights2_m_weights_V_10_ce1();
void thread_weights2_m_weights_V_10_d0();
void thread_weights2_m_weights_V_10_d1();
void thread_weights2_m_weights_V_10_we0();
void thread_weights2_m_weights_V_10_we1();
void thread_weights2_m_weights_V_11_address0();
void thread_weights2_m_weights_V_11_address1();
void thread_weights2_m_weights_V_11_ce0();
void thread_weights2_m_weights_V_11_ce1();
void thread_weights2_m_weights_V_11_d0();
void thread_weights2_m_weights_V_11_d1();
void thread_weights2_m_weights_V_11_we0();
void thread_weights2_m_weights_V_11_we1();
void thread_weights2_m_weights_V_12_address0();
void thread_weights2_m_weights_V_12_address1();
void thread_weights2_m_weights_V_12_ce0();
void thread_weights2_m_weights_V_12_ce1();
void thread_weights2_m_weights_V_12_d0();
void thread_weights2_m_weights_V_12_d1();
void thread_weights2_m_weights_V_12_we0();
void thread_weights2_m_weights_V_12_we1();
void thread_weights2_m_weights_V_13_address0();
void thread_weights2_m_weights_V_13_address1();
void thread_weights2_m_weights_V_13_ce0();
void thread_weights2_m_weights_V_13_ce1();
void thread_weights2_m_weights_V_13_d0();
void thread_weights2_m_weights_V_13_d1();
void thread_weights2_m_weights_V_13_we0();
void thread_weights2_m_weights_V_13_we1();
void thread_weights2_m_weights_V_14_address0();
void thread_weights2_m_weights_V_14_address1();
void thread_weights2_m_weights_V_14_ce0();
void thread_weights2_m_weights_V_14_ce1();
void thread_weights2_m_weights_V_14_d0();
void thread_weights2_m_weights_V_14_d1();
void thread_weights2_m_weights_V_14_we0();
void thread_weights2_m_weights_V_14_we1();
void thread_weights2_m_weights_V_15_address0();
void thread_weights2_m_weights_V_15_address1();
void thread_weights2_m_weights_V_15_ce0();
void thread_weights2_m_weights_V_15_ce1();
void thread_weights2_m_weights_V_15_d0();
void thread_weights2_m_weights_V_15_d1();
void thread_weights2_m_weights_V_15_we0();
void thread_weights2_m_weights_V_15_we1();
void thread_weights2_m_weights_V_16_address0();
void thread_weights2_m_weights_V_16_address1();
void thread_weights2_m_weights_V_16_ce0();
void thread_weights2_m_weights_V_16_ce1();
void thread_weights2_m_weights_V_16_d0();
void thread_weights2_m_weights_V_16_d1();
void thread_weights2_m_weights_V_16_we0();
void thread_weights2_m_weights_V_16_we1();
void thread_weights2_m_weights_V_17_address0();
void thread_weights2_m_weights_V_17_address1();
void thread_weights2_m_weights_V_17_ce0();
void thread_weights2_m_weights_V_17_ce1();
void thread_weights2_m_weights_V_17_d0();
void thread_weights2_m_weights_V_17_d1();
void thread_weights2_m_weights_V_17_we0();
void thread_weights2_m_weights_V_17_we1();
void thread_weights2_m_weights_V_18_address0();
void thread_weights2_m_weights_V_18_address1();
void thread_weights2_m_weights_V_18_ce0();
void thread_weights2_m_weights_V_18_ce1();
void thread_weights2_m_weights_V_18_d0();
void thread_weights2_m_weights_V_18_d1();
void thread_weights2_m_weights_V_18_we0();
void thread_weights2_m_weights_V_18_we1();
void thread_weights2_m_weights_V_19_address0();
void thread_weights2_m_weights_V_19_address1();
void thread_weights2_m_weights_V_19_ce0();
void thread_weights2_m_weights_V_19_ce1();
void thread_weights2_m_weights_V_19_d0();
void thread_weights2_m_weights_V_19_d1();
void thread_weights2_m_weights_V_19_we0();
void thread_weights2_m_weights_V_19_we1();
void thread_weights2_m_weights_V_1_address0();
void thread_weights2_m_weights_V_1_address1();
void thread_weights2_m_weights_V_1_ce0();
void thread_weights2_m_weights_V_1_ce1();
void thread_weights2_m_weights_V_1_d0();
void thread_weights2_m_weights_V_1_d1();
void thread_weights2_m_weights_V_1_we0();
void thread_weights2_m_weights_V_1_we1();
void thread_weights2_m_weights_V_20_address0();
void thread_weights2_m_weights_V_20_address1();
void thread_weights2_m_weights_V_20_ce0();
void thread_weights2_m_weights_V_20_ce1();
void thread_weights2_m_weights_V_20_d0();
void thread_weights2_m_weights_V_20_d1();
void thread_weights2_m_weights_V_20_we0();
void thread_weights2_m_weights_V_20_we1();
void thread_weights2_m_weights_V_21_address0();
void thread_weights2_m_weights_V_21_address1();
void thread_weights2_m_weights_V_21_ce0();
void thread_weights2_m_weights_V_21_ce1();
void thread_weights2_m_weights_V_21_d0();
void thread_weights2_m_weights_V_21_d1();
void thread_weights2_m_weights_V_21_we0();
void thread_weights2_m_weights_V_21_we1();
void thread_weights2_m_weights_V_22_address0();
void thread_weights2_m_weights_V_22_address1();
void thread_weights2_m_weights_V_22_ce0();
void thread_weights2_m_weights_V_22_ce1();
void thread_weights2_m_weights_V_22_d0();
void thread_weights2_m_weights_V_22_d1();
void thread_weights2_m_weights_V_22_we0();
void thread_weights2_m_weights_V_22_we1();
void thread_weights2_m_weights_V_23_address0();
void thread_weights2_m_weights_V_23_address1();
void thread_weights2_m_weights_V_23_ce0();
void thread_weights2_m_weights_V_23_ce1();
void thread_weights2_m_weights_V_23_d0();
void thread_weights2_m_weights_V_23_d1();
void thread_weights2_m_weights_V_23_we0();
void thread_weights2_m_weights_V_23_we1();
void thread_weights2_m_weights_V_24_address0();
void thread_weights2_m_weights_V_24_address1();
void thread_weights2_m_weights_V_24_ce0();
void thread_weights2_m_weights_V_24_ce1();
void thread_weights2_m_weights_V_24_d0();
void thread_weights2_m_weights_V_24_d1();
void thread_weights2_m_weights_V_24_we0();
void thread_weights2_m_weights_V_24_we1();
void thread_weights2_m_weights_V_25_address0();
void thread_weights2_m_weights_V_25_address1();
void thread_weights2_m_weights_V_25_ce0();
void thread_weights2_m_weights_V_25_ce1();
void thread_weights2_m_weights_V_25_d0();
void thread_weights2_m_weights_V_25_d1();
void thread_weights2_m_weights_V_25_we0();
void thread_weights2_m_weights_V_25_we1();
void thread_weights2_m_weights_V_26_address0();
void thread_weights2_m_weights_V_26_address1();
void thread_weights2_m_weights_V_26_ce0();
void thread_weights2_m_weights_V_26_ce1();
void thread_weights2_m_weights_V_26_d0();
void thread_weights2_m_weights_V_26_d1();
void thread_weights2_m_weights_V_26_we0();
void thread_weights2_m_weights_V_26_we1();
void thread_weights2_m_weights_V_27_address0();
void thread_weigh
|
ts2_m_weights_V_27_address1();
void thread_weights2_m_weights_V_27_ce0();
void thread_weights2_m_weights_V_27_ce1();
void thread_weights2_m_weights_V_27_d0();
void thread_weights2_m_weights_V_27_d1();
void thread_weights2_m_weights_V_27_we0();
void thread_weights2_m_weights_V_27_we1();
void thread_weights2_m_weights_V_28_address0();
void thread_weights2_m_weights_V_28_address1();
void thread_weights2_m_weights_V_28_ce0();
void thread_weights2_m_weights_V_28_ce1();
void thread_weights2_m_weights_V_28_d0();
void thread_weights2_m_weights_V_28_d1();
void thread_weights2_m_weights_V_28_we0();
void thread_weights2_m_weights_V_28_we1();
void thread_weights2_m_weights_V_29_address0();
void thread_weights2_m_weights_V_29_address1();
void thread_weights2_m_weights_V_29_ce0();
void thread_weights2_m_weights_V_29_ce1();
void thread_weights2_m_weights_V_29_d0();
void thread_weights2_m_weights_V_29_d1();
void thread_weights2_m_weights_V_29_we0();
void thread_weights2_m_weights_V_29_we1();
void thread_weights2_m_weights_V_2_address0();
void thread_weights2_m_weights_V_2_address1();
void thread_weights2_m_weights_V_2_ce0();
void thread_weights2_m_weights_V_2_ce1();
void thread_weights2_m_weights_V_2_d0();
void thread_weights2_m_weights_V_2_d1();
void thread_weights2_m_weights_V_2_we0();
void thread_weights2_m_weights_V_2_we1();
void thread_weights2_m_weights_V_30_address0();
void thread_weights2_m_weights_V_30_address1();
void thread_weights2_m_weights_V_30_ce0();
void thread_weights2_m_weights_V_30_ce1();
void thread_weights2_m_weights_V_30_d0();
void thread_weights2_m_weights_V_30_d1();
void thread_weights2_m_weights_V_30_we0();
void thread_weights2_m_weights_V_30_we1();
void thread_weights2_m_weights_V_31_address0();
void thread_weights2_m_weights_V_31_address1();
void thread_weights2_m_weights_V_31_ce0();
void thread_weights2_m_weights_V_31_ce1();
void thread_weights2_m_weights_V_31_d0();
void thread_weights2_m_weights_V_31_d1();
void thread_weights2_m_weights_V_31_we0();
void thread_weights2_m_weights_V_31_we1();
void thread_weights2_m_weights_V_3_address0();
void thread_weights2_m_weights_V_3_address1();
void thread_weights2_m_weights_V_3_ce0();
void thread_weights2_m_weights_V_3_ce1();
void thread_weights2_m_weights_V_3_d0();
void thread_weights2_m_weights_V_3_d1();
void thread_weights2_m_weights_V_3_we0();
void thread_weights2_m_weights_V_3_we1();
void thread_weights2_m_weights_V_4_address0();
void thread_weights2_m_weights_V_4_address1();
void thread_weights2_m_weights_V_4_ce0();
void thread_weights2_m_weights_V_4_ce1();
void thread_weights2_m_weights_V_4_d0();
void thread_weights2_m_weights_V_4_d1();
void thread_weights2_m_weights_V_4_we0();
void thread_weights2_m_weights_V_4_we1();
void thread_weights2_m_weights_V_5_address0();
void thread_weights2_m_weights_V_5_address1();
void thread_weights2_m_weights_V_5_ce0();
void thread_weights2_m_weights_V_5_ce1();
void thread_weights2_m_weights_V_5_d0();
void thread_weights2_m_weights_V_5_d1();
void thread_weights2_m_weights_V_5_we0();
void thread_weights2_m_weights_V_5_we1();
void thread_weights2_m_weights_V_6_address0();
void thread_weights2_m_weights_V_6_address1();
void thread_weights2_m_weights_V_6_ce0();
void thread_weights2_m_weights_V_6_ce1();
void thread_weights2_m_weights_V_6_d0();
void thread_weights2_m_weights_V_6_d1();
void thread_weights2_m_weights_V_6_we0();
void thread_weights2_m_weights_V_6_we1();
void thread_weights2_m_weights_V_7_address0();
void thread_weights2_m_weights_V_7_address1();
void thread_weights2_m_weights_V_7_ce0();
void thread_weights2_m_weights_V_7_ce1();
void thread_weights2_m_weights_V_7_d0();
void thread_weights2_m_weights_V_7_d1();
void thread_weights2_m_weights_V_7_we0();
void thread_weights2_m_weights_V_7_we1();
void thread_weights2_m_weights_V_8_address0();
void thread_weights2_m_weights_V_8_address1();
void thread_weights2_m_weights_V_8_ce0();
void thread_weights2_m_weights_V_8_ce1();
void thread_weights2_m_weights_V_8_d0();
void thread_weights2_m_weights_V_8_d1();
void thread_weights2_m_weights_V_8_we0();
void thread_weights2_m_weights_V_8_we1();
void thread_weights2_m_weights_V_9_address0();
void thread_weights2_m_weights_V_9_address1();
void thread_weights2_m_weights_V_9_ce0();
void thread_weights2_m_weights_V_9_ce1();
void thread_weights2_m_weights_V_9_d0();
void thread_weights2_m_weights_V_9_d1();
void thread_weights2_m_weights_V_9_we0();
void thread_weights2_m_weights_V_9_we1();
void thread_weights2_m_weights_V_address0();
void thread_weights2_m_weights_V_address1();
void thread_weights2_m_weights_V_ce0();
void thread_weights2_m_weights_V_ce1();
void thread_weights2_m_weights_V_d0();
void thread_weights2_m_weights_V_d1();
void thread_weights2_m_weights_V_we0();
void thread_weights2_m_weights_V_we1();
void thread_weights3_m_weights_V_10_address0();
void thread_weights3_m_weights_V_10_address1();
void thread_weights3_m_weights_V_10_ce0();
void thread_weights3_m_weights_V_10_ce1();
void thread_weights3_m_weights_V_10_d0();
void thread_weights3_m_weights_V_10_d1();
void thread_weights3_m_weights_V_10_we0();
void thread_weights3_m_weights_V_10_we1();
void thread_weights3_m_weights_V_11_address0();
void thread_weights3_m_weights_V_11_address1();
void thread_weights3_m_weights_V_11_ce0();
void thread_weights3_m_weights_V_11_ce1();
void thread_weights3_m_weights_V_11_d0();
void thread_weights3_m_weights_V_11_d1();
void thread_weights3_m_weights_V_11_we0();
void thread_weights3_m_weights_V_11_we1();
void thread_weights3_m_weights_V_12_address0();
void thread_weights3_m_weights_V_12_address1();
void thread_weights3_m_weights_V_12_ce0();
void thread_weights3_m_weights_V_12_ce1();
void thread_weights3_m_weights_V_12_d0();
void thread_weights3_m_weights_V_12_d1();
void thread_weights3_m_weights_V_12_we0();
void thread_weights3_m_weights_V_12_we1();
void thread_weights3_m_weights_V_13_address0();
void thread_weights3_m_weights_V_13_address1();
void thread_weights3_m_weights_V_13_ce0();
void thread_weights3_m_weights_V_13_ce1();
void thread_weights3_m_weights_V_13_d0();
void thread_weights3_m_weights_V_13_d1();
void thread_weights3_m_weights_V_13_we0();
void thread_weights3_m_weights_V_13_we1();
void thread_weights3_m_weights_V_14_address0();
void thread_weights3_m_weights_V_14_address1();
void thread_weights3_m_weights_V_14_ce0();
void thread_weights3_m_weights_V_14_ce1();
void thread_weights3_m_weights_V_14_d0();
void thread_weights3_m_weights_V_14_d1();
void thread_weights3_m_weights_V_14_we0();
void thread_weights3_m_weights_V_14_we1();
void thread_weights3_m_weights_V_15_address0();
void thread_weights3_m_weights_V_15_address1();
void thread_weights3_m_weights_V_15_ce0();
void thread_weights3_m_weights_V_15_ce1();
void thread_weights3_m_weights_V_15_d0();
void thread_weights3_m_weights_V_15_d1();
void thread_weights3_m_weights_V_15_we0();
void thread_weights3_m_weights_V_15_we1();
void thread_weights3_m_weights_V_1_address0();
void thread_weights3_m_weights_V_1_address1();
void thread_weights3_m_weights_V_1_ce0();
void thread_weights3_m_weights_V_1_ce1();
void thread_weights3_m_weights_V_1_d0();
void thread_weights3_m_weights_V_1_d1();
void thread_weights3_m_weights_V_1_we0();
void thread_weights3_m_weights_V_1_we1();
void thread_weights3_m_weights_V_2_address0();
void thread_weights3_m_weights_V_2_address1();
void thread_weights3_m_weights_V_2_ce0();
void thread_weights3_m_weights_V_2_ce1();
void thread_weights3_m_weights_V_2_d0();
void thread_weights3_m_weights_V_2_d1();
void thread_weights3_m_weights_V_2_we0();
void thread_weights3_m_weights_V_2_we1();
void thread_weights3_m_weights_V_3_address0();
void thread_weights3_m_weights_V_3_address1();
void thread_weights3_m_weights_V_3_ce0();
void thread_weights3_m_weights_V_3_ce1();
void thread_weights3_m_weights_V_3_d0();
void thread_weights3_m_weights_V_3_d1();
void thread_weights3_m_weights_V_3_we0();
void thread_weights3_m_weights_V_3_we1();
void thread_weights3_m_weights_V_4_address0();
void thread_weights3_m_weights_V_4_address1();
void thread_weights3_m_weights_V_4_ce0();
void thread_weights3_m_weights_V_4_ce1();
void thread_weights3_m_weights_V_4_d0();
void thread_weights3_m_weights_V_4_d1();
void thread_weights3_m_weights_V_4_we0();
void thread_weights3_m_weights_V_4_we1();
void thread_weights3_m_weights_V_5_address0();
void thread_weights3_m_weights_V_5_address1();
void thread_weights3_m_weights_V_5_ce0();
void thread_weights3_m_weights_V_5_ce1();
void thread_weights3_m_weights_V_5_d0();
void thread_weights3_m_weights_V_5_d1();
void thread_weights3_m_weights_V_5_we0();
void thread_weights3_m_weights_V_5_we1();
void thread_weights3_m_weights_V_6_address0();
void thread_weights3_m_weights_V_6_address1();
void thread_weights3_m_weights_V_6_ce0();
void thread_weights3_m_weights_V_6_ce1();
void thread_weights3_m_weights_V_6_d0();
void thread_weights3_m_weights_V_6_d1();
void thread_weights3_m_weights_V_6_we0();
void thread_weights3_m_weights_V_6_we1();
void thread_weights3_m_weights_V_7_address0();
void thread_weights3_m_weights_V_7_address1();
void thread_weights3_m_weights_V_7_ce0();
void thread_weights3_m_weights_V_7_ce1();
void thread_weights3_m_weights_V_7_d0();
void thread_weights3_m_weights_V_7_d1();
void thread_weights3_m_weights_V_7_we0();
void thread_weights3_m_weights_V_7_we1();
void thread_weights3_m_weights_V_8_address0();
void thread_weights3_m_weights_V_8_address1();
void thread_weights3_m_weights_V_8_ce0();
void thread_weights3_m_weights_V_8_ce1();
void thread_weights3_m_weights_V_8_d0();
void thread_weights3_m_weights_V_8_d1();
void thread_weights3_m_weights_V_8_we0();
void thread_weights3_m_weights_V_8_we1();
void thread_weights3_m_weights_V_9_address0();
void thread_weights3_m_weights_V_9_address1();
void thread_weights3_m_weights_V_9_ce0();
void thread_weights3_m_weights_V_9_ce1();
void thread_weights3_m_weights_V_9_d0();
void thread_weights3_m_weights_V_9_d1();
void thread_weights3_m_weights_V_9_we0();
void thread_weights3_m_weights_V_9_we1();
void thread_weights3_m_weights_V_address0();
void thread_weights3_m_weights_V_address1();
void thread_weights3_m_weights_V_ce0();
void thread_weights3_m_weights_V_ce1();
void thread_weights3_m_weights_V_d0();
void thread_weights3_m_weights_V_d1();
void thread_weights3_m_weights_V_we0();
void thread_weights3_m_weights_V_we1();
};
}
using namespace ap_rtl;
#endif
|
//
//------------------------------------------------------------//
// Copyright 2009-2012 Mentor Graphics Corporation //
// All Rights Reserved Worldwid //
// //
// Licensed under the Apache License, Version 2.0 (the //
// "License"); you may not use this file except in //
// compliance with the License. You may obtain a copy of //
// the License at //
// //
// http://www.apache.org/licenses/LICENSE-2.0 //
// //
// Unless required by applicable law or agreed to in //
// writing, software distributed under the License is //
// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR //
// CONDITIONS OF ANY KIND, either express or implied. See //
// the License for the specific language governing //
// permissions and limitations under the License. //
//------------------------------------------------------------//
//-----------------------------------------------------------------------------
// Title: SC Consumer
//
// Topic: Description
//
// A simple SC consumer TLM model that prints received transactions (of type
// ~tlm_generic_payload~ and sends them out its ~ap~ analysis port.
//
// This example uses the ~simple_target_socket~, a derivative of the TLM
// core class, ~tlm_target_socket~. Unlike the ~tlm_target_socket~, the simple
// socket does not require the module to inherit and implement all four
// target socket interface methods. Instead, you only need to register the
// interfaces you actually implement, ~b_transport~ in this case. This is what
// makes these sockets simple, flexible, and convenient.
//
// While trivial in functionality, the model demonstrates use of TLM ports
// to facilitate external communication.
//
// - Users of the model are not coupled to its internal implementation, using
// only the provided TLM port and socket to communicate.
//
// - The model itself does not refer to anything outside its encapsulated
// implementation. It does not know nor care about what might
// be driving its ~in~ socket or who might be listening on its ~ap~
// analysis port.
//-----------------------------------------------------------------------------
// (inline source)
#include <string>
#include <iomanip>
using std::string;
#include <systemc.h>
#include <tlm.h>
using namespace sc_core;
using namespace tlm;
#include "simple_target_socket.h"
using tlm_utils::simple_target_socket;
class consumer : public sc_module
{
public:
simple_target_socket<consumer> in; // defaults to tlm_gp
tlm_analysis_port<tlm_generic_payload> ap;
consumer(sc_module_name nm) : in("in"), ap("ap")
{
in.register_b_transport(this, &consumer::b_transport);
}
virtual void b_transport(tlm_generic_payload &gp, sc_time &t) {
char unsigned *data;
int len;
len = gp.get_data_length();
data = gp.get_data_ptr();
cout << sc_time_stamp() << " [CONSUMER/GP/RECV] ";
cout << "cmd:" << gp.get_command()
<< " addr:" << hex << gp.get_address() << " data:{ ";
for (int i=0; i<len; i++)
cout << hex << (int)*(data+i) << " ";
cout << "}" << endl;
wait(t);
t = SC_ZERO_TIME;
ap.write(gp);
}
};
|
/*****************************************************************************
Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
more contributor license agreements. See the NOTICE file distributed
with this work for additional information regarding copyright ownership.
Accellera licenses this file to you under the Apache License, Version 2.0
(the "License"); you may not use this file except in compliance with the
License. You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
implied. See the License for the specific language governing
permissions and limitations under the License.
****************************************************************************/
#ifndef EXAMPLES_EX20_TRACING_PARAMETER_ACTIVITY_EX20_PARAMETER_OWNER_H_
#define EXAMPLES_EX20_TRACING_PARAMETER_ACTIVITY_EX20_PARAMETER_OWNER_H_
#include <cci_configuration>
#include <systemc.h>
#include "xreport.hpp"
/**
* @class ex20_parameter_owner
* @brief The class declares and defines 'int' and 'float' type cci parameters
*/
SC_MODULE(ex20_parameter_owner) {
public:
/**
* @fn ex20_parameter_owner()
* @brief The class constructor
* @return void
*/
SC_CTOR(ex20_parameter_owner) {
XREPORT("Prior to " << sc_time_stamp());
XREPORT("[OWNER C_TOR] : Creating new integer type cci-parameter with"
" default value 10");
int_param = new cci::cci_param<int>("int_param", 10);
SC_THREAD(run_owner);
}
/**
* @fn void run_owner(void)
* @brief Implementation of SC_THREAD. Sets new value to the int type cci-parameter
* and sets a default value to the float type cci-parameter
* @return void
*/
void run_owner(void) {
while (1) {
XREPORT("@ " << sc_time_stamp());
XREPORT("[OWNER] : Setting new value to the 'int' type param to '15'");
*int_param = 15;
wait(5.0, SC_NS);
XREPORT("@ " << sc_time_stamp());
XREPORT("[OWNER] : Creating new 'double' type cci-parameter with default"
" value : 12.345");
dbl_param = new cci::cci_param<double>("double_param", 12.345);
wait(15.0, SC_NS);
}
}
private:
// Integer-type cci-parameter
cci::cci_param<int>* int_param; ///< An integer cci parameter
// Float-type cci-parameter
cci::cci_param<double>* dbl_param; ///< A double cci parameter
};
// ex20_parameter_owner
#endif // EXAMPLES_EX20_TRACING_PARAMETER_ACTIVITY_EX20_PARAMETER_OWNER_H_
|
/*
** This file is part of gSysC.
**
** gSysC is free software; you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation; either version 2 of the License, or
** (at your option) any later version.
**
** gSysC is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with gSysC with the file ``LICENSE''; if not, write to the Free Software
** Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/*****************************************************************************
Author: Christian J. Eibl
last modified: 2005-01-31
*****************************************************************************
Content:
This class is used for visualization of the structure graphics
of the underlying SystemC project.
It is one of the main elements of gSysC.
*****************************************************************************/
#ifndef GSYS_HIERWIN_H
#define GSYS_HIERWIN_H
#include "systemc.h"
#include <vector>
#include <cmath>
#include <stdio.h>
#include <string>
#include <QtCore/qvariant.h>
#include <QtCore/qrect.h>
#include <QtWidgets/qdialog.h>
#include <QtWidgets/qpushbutton.h>
#include <QtWidgets/qtooltip.h>
#include <QtWidgets/qwhatsthis.h>
#include <QtWidgets/qlayout.h>
#include <QtWidgets/QHBoxLayout>
#include <QtWidgets/qlineedit.h>
#include <QtWidgets/qlabel.h>
#include <QtWidgets/qgroupbox.h>
#include <QtWidgets/QGraphicsScene>
#include <QtWidgets/QGroupBox>
class gsysSignalViewer;
class gsysPort;
class gsysHierarchy;
class gsysConnection;
class gsysCanvasView;
// sectors for direction classification defined
#define N 1
#define NNW 2
#define NW 3
#define WNW 4
#define W 5
#define WSW 6
#define SW 7
#define SSW 8
#define S 9
#define SSE 10
#define SE 11
#define ESE 12
#define E 13
#define ENE 14
#define NE 15
#define NNE 16
using namespace std;
class gsysHierarchyWindow : public QDialog
{
friend class gsysHierarchyTree;
friend class gsysCanvasView;
friend class gsysConnection;
friend class gsysPort;
Q_OBJECT
private:
vector<gsysHierarchy*> hierarchyList;
vector<gsysConnection*> connList; // Connections inside of this level
vector<gsysConnection*> sideConnList; // Connections to outer elements
gsysHierarchyWindow( QWidget* parent, const char* name = 0, bool modal = false, Qt::WindowFlags fl = 0 );
gsysHierarchy* parent;
gsysHierarchy* ownHierarchy;
int dimFactor;
short getSector(QPoint *source, QPoint *dest);
QPoint* normalize(QPoint *p);
void drawSidePort(gsysPort* port, bool left, int nr, int abstand, int portHeight=21);
void drawNetConns(gsysHierarchy* hier);
void drawConnections();
bool drawConnStep(gsysConnection* connection,QPoint *p1, QPoint *p2,int lfdNr);
bool thisLevel(gsysHierarchy* hier);
// values to be read from file 'gsysHViewer.conf'
int sideMargin;
int topMargin;
int horizontalSpace;
int verticalSpace;
int moduleWidth;
int moduleHeight;
char* backgroundColor;
char* moduleColor;
char* moduleWithChild;
char* textColor;
char* inPort;
char* outPort;
char* inoutPort;
char* mmHierConnColor;
bool mmHierConnShow;
bool mmSigPortShow;
void readConfig();
QPushButton *saveButton;
QGroupBox* moveInfos;
QLabel* labelKoordinaten;
QLineEdit* coord;
QLabel* labelTyp;
QLineEdit* lineEditTyp;
QLabel* labelWert;
QLineEdit* lineEditWert;
QHBoxLayout* moveInfosLayout;
char* normalSignal;
char* normalNode;
char* activeSignal;
char* changedSignal;
char* activeChangedSig;
~gsysHierarchyWindow();
gsysCanvasView *canvasView;
bool isInitialized();
void initializeWdw(gsysHierarchy* ownHier, vector<gsysHierarchy*> allHierarchies, vector<gsysConnection*> allConnections, bool toShow = true);
gsysHierarchy* getOwnHier();
public slots:
void saveButton_clicked();
protected:
QVBoxLayout *hierWinLayout;
protected slots:
void languageChange();
};
#endif
|
/*
* Created on: 21. jun. 2019
* Author: Jonathan Horsted Schougaard
*/
#pragma once
#define AP_INT_MAX_W 2048 // Size of "sc_bv<W> data" exceed limit (1024) for ALexNet layer 11x11
#define SC_INCLUDE_FX
#include "hwcore/hf/helperlib.h"
#include <iostream>
#include <string>
#include <systemc.h>
#define SC_STREAM_INTERFACE_CREATE_SOURCE(interface, param) \
DO_PRAGMA(HLS RESOURCE variable = interface core = AXI4Stream metadata = \
param port_map = {{interface##_0 TDATA} {interface##_1 TLAST} {interface##_2 TKEEP}})
#define SC_STREAM_INTERFACE_CREATE_SINK(interface, param) \
DO_PRAGMA(HLS RESOURCE variable = interface core = AXI4Stream metadata = \
param port_map = {{interface##_0 TDATA} {interface##_1 TLAST} {interface##_2 TKEEP}})
#define SC_AXI_INTERFACE_CREATE(interface) \
DO_PRAGMA(HLS resource core = AXI4LiteS metadata = "-bus_bundle slv0" variable = interface)
/*#ifdef __SYNTHESIS__NOT
#define SC_DECL_INTERFACE(name,W) struct name : public hwcore::pipes::DATA_STREAM_t<W>{typedef
hwcore::pipes::DATA_STREAM_t<W> interface_T; } #else #define SC_DECL_INTERFACE(name,W) using name =
hwcore::pipes::DATA_STREAM_t<W> hwcore::pipes::DATA_STREAM_t<W> impl
//#define SC_DECL_INTERFACE(W) SC_DECL_INTERFACE__(W);
//#define SC_DECL_INTERFACE_NAME(name,W)
//#define SC_DECL_INTERFACE__(W) using DATA_STREAM_ ## W = hwcore::pipes::DATA_STREAM_t<W>;
#endif*/
//#define DATA_std_t(W) DATA_STREAM_##W
#define SC_DATA_T(W) SC_DATA_T__(W)
#define SC_DATA_T__(W) SC_DATA_STREAM_T_trait<W>::interface_T
#define SC_DECL_INTERFACE_STD__(W) \
SC_DECL_INTERFACE(SC_DATA_STREAM_##W, W); \
template <> struct SC_DATA_STREAM_T_trait<W> { typedef SC_DATA_STREAM_##W interface_T; };
#define SC_DECL_INTERFACE(name, W) \
struct name : public hwcore::pipes::SC_DATA_STREAM_t<W> { \
typedef hwcore::pipes::SC_DATA_STREAM_t<W> interface_T; \
\
inline name() : SC_DATA_STREAM_t<W>() {} \
\
inline name(const name &ref) { \
data = ref.data; \
tlast = ref.tlast; \
tkeep = ref.tkeep; \
} \
\
inline name(const interface_T &ref) { \
data = ref.data; \
tlast = ref.tlast; \
tkeep = ref.tkeep; \
} \
\
inline name(sc_bv<W> data_, sc_uint<1> tlast_ = 0, sc_uint<W / 8> tkeep_ = 0) { \
data = data_; \
tlast = tlast_; \
tkeep = tkeep_; \
} \
};
/* operator interface_T()\
{\
interface_T tmp;\
tmp.data = data;\
tmp.tlast = tlast;\
tmp.tkeep = tkeep;\
return tmp;\
}\*/
namespace hwcore {
namespace pipes {
template <class T> class sc_fifo_base_dummy {
public:
inline friend void sc_trace(sc_trace_file *tf, const T &v, const std::string &NAME) {}
inline friend std::ostream &operator<<(ostream &os, T const &v) {
// os << "(" << v.data << "," << v.tlast << "," << v.tkeep << ")";//std::boolalpha
return os;
}
};
template <int W, int keepW = 8> class SC_DATA_STREAM_t {
public:
sc_bv<W> data;
sc_uint<1> tlast;
sc_bv<W / keepW> tkeep;
inline SC_DATA_STREAM_t() : data(), tlast(), tkeep() {}
inline SC_DATA_STREAM_t(const SC_DATA_STREAM_t &ref) {
data = ref.data;
tlast = ref.tlast;
tkeep = ref.tkeep;
}
inline SC_DATA_STREAM_t(sc_bv<W> data_, sc_uint<1> tlast_ = 0, sc_uint<W / keepW> tkeep_ = 0) {
data = data_;
tlast = tlast_;
tkeep = tkeep_;
}
template <int pW, int pkeepW = 8> inline void fit(const SC_DATA_STREAM_t<pW, pkeepW> &ref) {
data = 0;
tkeep = 0;
data(pW - 1, 0) = ref.data;
tlast = ref.tlast;
tkeep((pW / 8) - 1, 0) = ref.tkeep;
}
// inline void setData(sc_uint<32> data_)
inline bool operator==(const SC_DATA_STREAM_t &rhs) const {
return (rhs.data == data && rhs.tlast == tlast && rhs.tkeep == tkeep);
}
inline SC_DATA_STREAM_t &operator=(const SC_DATA_STREAM_t &rhs) {
data = rhs.data;
tlast = rhs.tlast;
tkeep = rhs.tkeep;
return *this;
}
inline friend void sc_trace(sc_trace_file *tf, const SC_DATA_STREAM_t &v, const std::string &NAME) {
sc_trace(tf, v.data, NAME + ".data");
sc_trace(tf, v.tlast, NAME + ".tlast");
sc_trace(tf, v.tkeep, NAME + ".tkeep");
}
inline friend std::ostream &operator<<(ostream &os, SC_DATA_STREAM_t const &v) {
os << "(" << v.data << "," << v.tlast << "," << v.tkeep << ")"; // std::boolalpha
return os;
}
inline bool EOP() { return (tlast == 1 && tkeep.get_bit(0) == 0 && tkeep.get_bit((W / keepW) - 1) == 0); }
inline bool EOPRev() {
// warning remove this
return (tlast == 1 && tkeep.get_bit((W / keepW) - 1) == 0);
}
inline void setEOP() {
data = 0;
setKeep(0);
tlast = 1;
}
inline bool unValid() { return (tlast == 0 && tkeep.get_bit(0) == 0); }
inline void setUnvalid(sc_uint<1> _tlast = 0) {
data = 0;
setKeep(0);
tlast = _tlast;
}
inline void setKeep() { tkeep = hwcore::hf::HIGH<sc_uint, W / keepW>(); }
inline void setKeep(int pkg_size) {
for (int i = 0; i < W / keepW; i++) {
#pragma HLS UNROLL
if (i < pkg_size) {
tkeep[i] = 1;
} else {
tkeep[i] = 0;
}
}
}
/*template<int data_W>
void setKeep(sc_bv<W/data_W> keepVal)
{
const int N_new_keep = W/data_W;
const int rate = (data_W/8);
for(int a=0;a<N_new_keep;a++)
{
#pragma HLS UNROLL
for(int b=0;b<rate;b++)
{
#pragma HLS UNROLL
tkeep[(a*rate) + b] = keepVal[a];
}
}
}*/
template <int data_W> inline void setKeep(int keepVal, int index) {
const int N_new_keep = W / data_W;
const int rate = (data_W / keepW);
for (int b = 0; b < rate; b++) {
#pragma HLS UNROLL
tkeep[(index * rate) + b] = keepVal;
}
}
template <int data_W> inline void setKeep(int pkg_size) {
for (int i = 0; i < W / data_W; i++) {
#pragma HLS UNROLL
setKeep<data_W>((i < pkg_size ? 1 : 0), i);
}
}
template <int data_W> inline void setKeepRev(int pkg_size) {
for (int i = 0; i < W / data_W; i++) {
#pragma HLS UNROLL
setKeep<data_W>((i < pkg_size ? 1 : 0), (W / data_W) - i - 1);
}
}
template <int data_W> inline int getKeep(int index) {
const int N_new_keep = W / data_W;
const int rate = (data_W / keepW);
return tkeep.get_bit(index * rate);
}
template <template <int> class data_T, int data_W, int N> inline void getData(data_T<data_W> *out) {
ASSIGNLOOP:
for (int i = 0; i < N; i++) {
#pragma HLS UNROLL
sc_bv<data_W> tmp = data(data_W - 1 + data_W * i, data_W * i);
out[i] = tmp;
}
}
template <template <int> class data_T, int data_W> inline data_T<data_W> getData(int index) {
sc_bv<data_W> tmp = data(data_W - 1 + data_W * index, data_W * index);
return tmp;
}
template <int data_W, int data_P, int N> inline void getDataFixed(sc_fixed<data_W, data_P> out[N]) {
ASSIGNLOOP:
for (int i = 0; i < N; i++) {
#pragma HLS UNROLL
sc_bv<data_W> tmp = data(data_W - 1 + data_W * i, data_W * i);
out[i] = hwcore::hf::bv2fixed<data_W, data_P>(tmp);
}
}
template <int data_W, int data_P, int N> inline void getDatauFixed(sc_ufixed<data_W, data_P> out[N]) {
ASSIGNLOOP:
for (int i = 0; i < N; i++) {
#pragma HLS UNROLL
sc_bv<data_W> tmp = data(data_W - 1 + data_W * i, data_W * i);
out[i] = hwcore::hf::bv2ufixed<data_W, data_P>(tmp);
}
}
template <int data_W, int data_P, int N> inline void getDataFixed(sc_fixed<data_W, data_P, SC_TRN, SC_SAT> out[N]) {
ASSIGNLOOP:
for (int i = 0; i < N; i++) {
#pragma HLS UNROLL
sc_bv<data_W> tmp = data(data_W - 1 + data_W * i, data_W * i);
out[i] = hwcore::hf::bv2fixed<data_W, data_P>(tmp);
}
}
template <int data_P> inline sc_fixed<W, data_P> getDataFixed() { return hwcore::hf::bv2fixed<W, data_P>(data); }
template <template <int> class data_T, int data_W> inline void setData(data_T<data_W> din, int index) {
data(data_W - 1 + data_W * index, data_W * index) = din;
}
template <template <int> class data_T, int data_W, int N> inline void setData(data_T<data_W> din[N]) {
ASSIGNLOOP:
for (int i = 0; i < N; i++) {
#pragma HLS UNROLL
data(data_W - 1 + data_W * i, data_W * i) = din[i];
}
}
template <int data_W, int data_P, int N> inline void setDataFixed(sc_fixed<data_W, data_P> in[N]) {
ASSIGNLOOP:
for (int i = 0; i < N; i++) {
#pragma HLS UNROLL
data(data_W - 1 + data_W * i, data_W * i) = hwcore::hf::fixed2bv<data_W, data_P>(in[i]);
}
}
template <int data_W, int data_P, int N> inline void setDataUfixed(sc_ufixed<data_W, data_P> in[N]) {
ASSIGNLOOP:
for (int i = 0; i < N; i++) {
#pragma HLS UNROLL
data(data_W - 1 + data_W * i, data_W * i) = hwcore::hf::ufixed2bv<data_W, data_P>(in[i]);
}
}
template <int data_W, int data_P, int N> inline void setDataFixed(sc_fixed<data_W, data_P, SC_TRN, SC_SAT> in[N]) {
ASSIGNLOOP:
for (int i = 0; i < N; i++) {
#pragma HLS UNROLL
data(data_W - 1 + data_W * i, data_W * i) = hwcore::hf::fixed2bv<data_W, data_P>(in[i]);
}
}
template <int data_P> inline void setDataFixed(sc_fixed<W, data_P> in) {
data = hwcore::hf::fixed2bv<W, data_P>(in);
}
};
template <typename SC_DATA_STREAM_T1, typename SC_DATA_STREAM_T2>
void SC_DATA_STREAM_copy_info(SC_DATA_STREAM_T1 &dst, SC_DATA_STREAM_T2 &src) {
dst.tlast = src.tlast;
dst.tkeep = src.tkeep;
}
template <int W> struct SC_DATA_STREAM_T_trait { typedef SC_DATA_STREAM_t<W> interface_T; };
#ifdef __SYNTHESIS__
SC_DECL_INTERFACE_STD__(8);
SC_DECL_INTERFACE_STD__(16);
SC_DECL_INTERFACE_STD__(32);
SC_DECL_INTERFACE_STD__(64);
SC_DECL_INTERFACE_STD__(128);
SC_DECL_INTERFACE_STD__(256);
SC_DECL_INTERFACE_STD__(512);
SC_DECL_INTERFACE_STD__(1024);
template <int W> using sc_data_stream_t = typename SC_DATA_STREAM_T_trait<1 * W>::interface_T;
#else
// Clang has easier to understand this one instead of the one needed for synthesis.
template <int W> using sc_data_stream_t = SC_DATA_STREAM_t<W, 8>;
#endif
} // namespace pipes
} // namespace hwcore
#ifdef __RTL_SIMULATION__
template <int W> SC_MODULE(SC_FIFO_IN_TRANS) {
SC_MODULE_CLK_RESET_SIGNAL;
sc_fifo_in<hwcore::pipes::sc_data_stream_t<W> > data_sink;
sc_signal<sc_logic> data_sink_empty_n;
sc_signal<sc_logic> data_sink_read;
sc_signal<sc_lv<W> > data_sink_0_dout;
sc_signal<sc_lv<1> > data_sink_1_dout;
sc_signal<sc_lv<W / 8> > data_sink_2_dout;
sc_signal<sc_logic> data_sink_1_read, data_sink_2_read;
#define SC_FIFO_IN_TRANS_CONNECT(inst, thisinst, port) \
SC_MODULE_LINK(thisinst); \
thisinst.data_sink(port); \
inst.port##_0_dout(thisinst.data_sink_0_dout); \
inst.port##_0_empty_n(thisinst.data_sink_empty_n); \
inst.port##_0_read(thisinst.data_sink_read); \
inst.port##_1_dout(thisinst.data_sink_1_dout); \
inst.port##_1_empty_n(thisinst.data_sink_empty_n); \
inst.port##_2_dout(thisinst.data_sink_2_dout); \
inst.port##_2_empty_n(thisinst.data_sink_empty_n); \
inst.port##_1_read(thisinst.data_sink_1_read); \
inst.port##_2_read(thisinst.data_sink_2_read);
SC_CTOR(SC_FIFO_IN_TRANS) {
SC_CTHREAD(TRANS_thread, clk);
reset_signal_is(reset, true);
}
void TRANS_thread() {
data_sink_empty_n.write(SC_LOGIC_0);
data_sink_0_dout.write(0);
data_sink_1_dout.write(0);
data_sink_2_dout.write(0);
while (true) {
// wait();
data_sink_empty_n.write(SC_LOGIC_0);
data_sink_0_dout.write(0);
data_sink_1_dout.write(0);
data_sink_2_dout.write(0);
hwcore::pipes::sc_data_stream_t<W> tmp = data_sink.read();
data_sink_0_dout.write(tmp.data);
data_sink_1_dout.write(tmp.tlast);
data_sink_2_dout.write(tmp.tkeep);
data_sink_empty_n.write(SC_LOGIC_1);
wait();
while (data_sink_read.read() == SC_LOGIC_0) {
wait();
}
}
}
};
template <int W> SC_MODULE(SC_FIFO_OUT_TRANS) {
SC_MODULE_CLK_RESET_SIGNAL;
sc_fifo_out<hwcore::pipes::sc_data_stream_t<W> > data_source;
sc_signal<sc_logic> data_source_full_n;
sc_signal<sc_logic> data_source_write;
sc_signal<sc_lv<W> > data_source_0_din;
sc_signal<sc_lv<1> > data_source_1_din;
sc_signal<sc_lv<W / 8> > data_source_2_din;
sc_signal<sc_logic> data_source_1_write;
sc_signal<sc_logic> data_source_2_write;
#define SC_FIFO_OUT_TRANS_CONNECT(inst, thisinst, port) \
SC_MODULE_LINK(thisinst); \
thisinst.data_source(port); \
inst.port##_0_full_n(thisinst.data_source_full_n); \
inst.port##_1_full_n(thisinst.data_source_full_n); \
inst.port##_2_full_n(thisinst.data_source_full_n); \
inst.port##_0_write(thisinst.data_source_write); \
inst.port##_0_din(thisinst.data_source_0_din); \
inst.port##_1_din(thisinst.data_source_1_din); \
inst.port##_2_din(thisinst.data_source_2_din); \
inst.port##_1_write(thisinst.data_source_1_write); \
inst.port##_2_write(thisinst.data_source_2_write);
SC_CTOR(SC_FIFO_OUT_TRANS) {
SC_CTHREAD(TRANS_THREAD, clk.pos());
reset_signal_is(reset, true);
}
void TRANS_THREAD() {
data_source_full_n.write(SC_LOGIC_0);
bool full_n = false;
while (true) {
wait();
full_n = !(data_source.num_free() == 0);
if (full_n) {
data_source_full_n.write(SC_LOGIC_1);
if (data_source_write.read() == SC_LOGIC_1) {
hwcore::pipes::sc_data_stream_t<W> tmp;
tmp.data = data_source_0_din.read();
tmp.tlast = data_source_1_din.read();
tmp.tkeep = data_source_2_din.read();
if (data_source.nb_write(tmp)) {
/*full_n = !(data_source.num_free()==0);
data_source_full_n.write(SC_LOGIC_1);*/
}
}
} else {
data_source_full_n.write(SC_LOGIC_0);
}
}
}
};
#endif
//#define SC_DECL_INTERFACE(name,W) struct name : public hwcore::pipes::DATA_STREAM_t<W>{typedef
// hwcore::pipes::DATA_STREAM_t<W> interface_T; }
|
/****************************************************************************
*
* Copyright (c) 2015, Cadence Design Systems. All Rights Reserved.
*
* This file contains confidential information that may not be
* distributed under any circumstances without the written permision
* of Cadence Design Systems.
*
****************************************************************************/
/****************************************************************************
*
* This file contains the dut_type_wrapper module
* for use in the verilog verification wrapper dut_vlwrapper.v
* It creats an instance of the dut module and has threads
* for converting the BEH ports to RTL level ports on the wrapper.
*
****************************************************************************/
#ifndef _DUT_TYPE_WRAP_INCLUDED_
#define _DUT_TYPE_WRAP_INCLUDED_
#include <systemc.h>
#include "dut.h"
// Declaration of wrapper with RTL level ports
SC_MODULE(dut_type_wrapper)
{
public:
sc_in< bool > clk;
sc_in< bool > rst;
sc_out< bool > din_busy;
sc_in< bool > din_vld;
sc_in< sc_uint< 8 > > din_data_a;
sc_in< sc_uint< 8 > > din_data_b;
sc_in< sc_uint< 8 > > din_data_c;
sc_in< sc_uint< 8 > > din_data_d;
sc_in< sc_uint< 8 > > din_data_e;
sc_in< sc_uint< 8 > > din_data_f;
sc_in< sc_uint< 8 > > din_data_g;
sc_in< sc_uint< 8 > > din_data_h;
sc_in< bool > dout_busy;
sc_out< bool > dout_vld;
sc_out< sc_uint< 32 > > dout_data;
// These signals are used to connect structured ports or ports that need
// type conversion to the RTL ports.
sc_signal< input_t > din_data;
// create the netlist
void InitInstances();
void InitThreads();
// delete the netlist
void DeleteInstances();
// The following threads are used to connect structured ports to the actual
// RTL ports.
void thread_din_data();
SC_HAS_PROCESS(dut_type_wrapper);
dut_type_wrapper( sc_module_name name = sc_module_name( sc_gen_unique_name("dut")) )
: sc_module(name)
,clk("clk")
,rst("rst")
,din_busy("din_busy")
,din_vld("din_vld")
,din_data_a("din_data_a"),
din_data_b("din_data_b"),
din_data_c("din_data_c"),
din_data_d("din_data_d"),
din_data_e("din_data_e"),
din_data_f("din_data_f"),
din_data_g("din_data_g"),
din_data_h("din_data_h")
,dout_busy("dout_busy")
,dout_vld("dout_vld")
,dout_data("dout_data")
,dut0(0)
{
InitInstances();
InitThreads();
end_module();
}
// destructor
~dut_type_wrapper()
{
DeleteInstances();
}
protected:
dut* dut0;
};
#endif /* */
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.3
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _Sobel_HH_
#define _Sobel_HH_
#include "systemc.h"
#include "AESL_pkg.h"
#include "Filter2D.h"
namespace ap_rtl {
struct Sobel : public sc_module {
// Port declarations 13
sc_in_clk ap_clk;
sc_in< sc_logic > ap_rst;
sc_in< sc_logic > ap_start;
sc_out< sc_logic > ap_done;
sc_in< sc_logic > ap_continue;
sc_out< sc_logic > ap_idle;
sc_out< sc_logic > ap_ready;
sc_in< sc_lv<8> > p_src_data_stream_V_dout;
sc_in< sc_logic > p_src_data_stream_V_empty_n;
sc_out< sc_logic > p_src_data_stream_V_read;
sc_out< sc_lv<8> > p_dst_data_stream_V_din;
sc_in< sc_logic > p_dst_data_stream_V_full_n;
sc_out< sc_logic > p_dst_data_stream_V_write;
sc_signal< sc_lv<2> > ap_var_for_const0;
sc_signal< sc_lv<2> > ap_var_for_const1;
sc_signal< sc_lv<3> > ap_var_for_const2;
sc_signal< sc_lv<4> > ap_var_for_const3;
sc_signal< sc_lv<2> > ap_var_for_const4;
sc_signal< sc_lv<3> > ap_var_for_const5;
// Module declarations
Sobel(sc_module_name name);
SC_HAS_PROCESS(Sobel);
~Sobel();
sc_trace_file* mVcdFile;
Filter2D* grp_Filter2D_fu_52;
sc_signal< sc_logic > ap_done_reg;
sc_signal< sc_lv<2> > ap_CS_fsm;
sc_signal< sc_logic > ap_CS_fsm_state1;
sc_signal< sc_logic > grp_Filter2D_fu_52_ap_start;
sc_signal< sc_logic > grp_Filter2D_fu_52_ap_done;
sc_signal< sc_logic > grp_Filter2D_fu_52_ap_idle;
sc_signal< sc_logic > grp_Filter2D_fu_52_ap_ready;
sc_signal< sc_logic > grp_Filter2D_fu_52_p_src_data_stream_V_read;
sc_signal< sc_lv<8> > grp_Filter2D_fu_52_p_dst_data_stream_V_din;
sc_signal< sc_logic > grp_Filter2D_fu_52_p_dst_data_stream_V_write;
sc_signal< sc_logic > grp_Filter2D_fu_52_ap_start_reg;
sc_signal< bool > ap_block_state1_ignore_call2;
sc_signal< sc_logic > ap_CS_fsm_state2;
sc_signal< sc_lv<2> > ap_NS_fsm;
sc_signal< bool > ap_block_state1;
static const sc_logic ap_const_logic_1;
static const sc_logic ap_const_logic_0;
static const sc_lv<2> ap_ST_fsm_state1;
static const sc_lv<2> ap_ST_fsm_state2;
static const sc_lv<32> ap_const_lv32_0;
static const sc_lv<32> ap_const_lv32_1;
static const sc_lv<2> ap_const_lv2_0;
static const sc_lv<2> ap_const_lv2_1;
static const sc_lv<3> ap_const_lv3_6;
static const sc_lv<4> ap_const_lv4_2;
static const sc_lv<2> ap_const_lv2_3;
static const sc_lv<3> ap_const_lv3_0;
static const bool ap_const_boolean_1;
// Thread declarations
void thread_ap_var_for_const0();
void thread_ap_var_for_const1();
void thread_ap_var_for_const2();
void thread_ap_var_for_const3();
void thread_ap_var_for_const4();
void thread_ap_var_for_const5();
void thread_ap_clk_no_reset_();
void thread_ap_CS_fsm_state1();
void thread_ap_CS_fsm_state2();
void thread_ap_block_state1();
void thread_ap_block_state1_ignore_call2();
void thread_ap_done();
void thread_ap_idle();
void thread_ap_ready();
void thread_grp_Filter2D_fu_52_ap_start();
void thread_p_dst_data_stream_V_din();
void thread_p_dst_data_stream_V_write();
void thread_p_src_data_stream_V_read();
void thread_ap_NS_fsm();
};
}
using namespace ap_rtl;
#endif
|
#include <systemc.h>
/**
* @brief jpg_output module. Federico Cruz
* It takes the image and compresses it into jpeg format
* It is done in 4 parts:
* 1. Divides the image in 8x8 pixel blocks; for 8-bit grayscale images the a level shift is done by substracting 128 from each pixel.
* 2. Discrete Cosine Transform (DCT) of the 8x8 image.
* 3. Each transformed 8x8 block is divided by a quantization value for each block entry.
* 4. Each quantized 8x8 block is reordered by a Zig-Zag sequence into a array of size 64.
* *5. Entropy compression by variable length encoding (huffman). Used to maximize compression. Not implemented here.
*/
#define PI 3.1415926535897932384626433832795
#define BLOCK_ROWS 8
#define BLOCK_COLS 8
SC_MODULE(jpg_output)
{
//-----------Internal variables-------------------
// const int Block_rows = 8;
// const int Block_cols = 8;
double *image;
int image_rows = 480;
int image_cols = 640;
signed char eob = 127; // end of block
int quantificator[8][8] = {// quantization table
{16, 11, 10, 16, 24, 40, 51, 61},
{12, 12, 14, 19, 26, 58, 60, 55},
{14, 13, 16, 24, 40, 57, 69, 56},
{14, 17, 22, 29, 51, 87, 80, 62},
{18, 22, 37, 56, 68, 109, 103, 77},
{24, 35, 55, 64, 81, 104, 113, 92},
{49, 64, 78, 87, 103, 121, 120, 101},
{72, 92, 95, 98, 112, 100, 103, 99}};
int zigzag_index[64] = {// zigzag table
0, 1, 5, 6, 14, 15, 27, 28,
2, 4, 7, 13, 16, 26, 29, 42,
3, 8, 12, 17, 25, 30, 41, 43,
9, 11, 18, 24, 31, 40, 44, 53,
10, 19, 23, 32, 39, 45, 52, 54,
20, 22, 33, 38, 46, 51, 55, 60,
21, 34, 37, 47, 50, 56, 59, 61,
35, 36, 48, 49, 57, 58, 62, 63};
// Constructor for compressor
SC_HAS_PROCESS(jpg_output);
jpg_output(sc_module_name jpg_compressor, int im_rows = 480, int im_cols = 640) : sc_module(jpg_compressor)
{
if (im_rows % BLOCK_ROWS == 0)
{
image_rows = im_rows;
}
else
{
image_rows = (im_rows / BLOCK_ROWS + 1) * BLOCK_ROWS;
}
if (im_cols % BLOCK_COLS == 0)
{
image_cols = im_cols;
}
else
{
image_cols = (im_cols / BLOCK_COLS + 1) * BLOCK_COLS;
}
image = new double[image_rows * image_cols];
// initialize the image matrix to avoid nan
for (int i = 0; i < (image_rows * image_cols); i++)
{
image[i] = 0;
}
} // End of Constructor
//------------Code Starts Here-------------------------
void input_pixel(int pixel_value, int row, int col)
{
double *i_row = &image[row * image_cols];
i_row[col] = double(pixel_value);
}
void output_pixel(int *Pixel, int row, int col)
{
double *i_row = &image[row * image_cols];
*Pixel = int(i_row[col]);
}
void output_byte(signed char *element, int index)
{
element[index] = image[index];
}
void jpeg_compression(int *output_size)
{
// Level shift
for (int i = 0; i < (image_rows * image_cols); i++)
{
image[i] = image[i] - 128;
}
int number_of_blocks = image_rows * image_cols / (BLOCK_ROWS * BLOCK_COLS);
#ifndef USING_TLM_TB_EN
int block_output[number_of_blocks][BLOCK_ROWS * BLOCK_COLS] = {0};
int block_output_size[number_of_blocks] = {0};
#else
int **block_output = new int *[number_of_blocks];
int *block_output_size = new int[number_of_blocks];
for (int i = 0; i < number_of_blocks; i++)
{
block_output[i] = new int[BLOCK_ROWS * BLOCK_COLS];
}
for (int i = 0; i < number_of_blocks; i++)
{
block_output_size[i] = 0;
for (int j = 0; j < BLOCK_ROWS * BLOCK_COLS; j++)
{
block_output[i][j] = 0;
}
}
#endif // USING_TLM_TB_EN
int block_counter = 0;
*output_size = 0;
for (int row = 0; row < image_rows; row += BLOCK_ROWS)
{
for (int col = 0; col < image_cols; col += BLOCK_COLS)
{
// Divided the image in 8×8 blocks
dct(row, col);
quantization(row, col);
zigzag(row, col, &block_output_size[block_counter], block_output[block_counter]);
*output_size += block_output_size[block_counter] + 1;
block_counter++;
}
}
int output_counter = 0;
for (int block_index = 0; block_index < number_of_blocks; block_index++)
{
for (int out_index = 0; out_index < block_output_size[block_index]; out_index++)
{
image[output_counter] = block_output[block_index][out_index];
output_counter++;
}
image[output_counter] = eob;
output_counter++;
}
#ifdef USING_TLM_TB_EN
for (int i = 0; i < number_of_blocks; i++)
{
delete[] block_output[i];
}
delete[] block_output;
delete[] block_output_size;
#endif // USING_TLM_TB_EN
}
void dct(int row_offset, int col_offset)
{
double cos_table[BLOCK_ROWS][BLOCK_COLS];
// make the cosine table
for (int row = 0; row < BLOCK_ROWS; row++)
{
for (int col = 0; col < BLOCK_COLS; col++)
{
cos_table[row][col] = cos((((2 * row) + 1) * col * PI) / 16);
}
}
double temp = 0.0;
for (int row = row_offset; row < row_offset + BLOCK_ROWS; row++)
{
double *i_row = &image[row * image_cols];
for (int col = col_offset; col < col_offset + BLOCK_COLS; col++)
{
// i_row[col] = cos_table[row-row_offset][col-col_offset];
temp = 0.0;
for (int x = 0; x < 8; x++)
{
double *x_row = &image[(x + row_offset) * image_cols];
for (int y = 0; y < 8; y++)
{
temp += x_row[y + col_offset] * cos_table[x][row - row_offset] * cos_table[y][col - col_offset];
}
}
if ((row - row_offset == 0) && (col - col_offset == 0))
{
temp /= 8.0;
}
else if (((row - row_offset == 0) && (col - col_offset != 0)) || ((row - row_offset != 0) && (col - col_offset == 0)))
{
temp /= (4.0 * sqrt(2.0));
}
else
{
temp /= 4.0;
}
i_row[col] = temp;
}
}
}
void quantization(int row_offset, int col_offset)
{
for (int row = row_offset; row < row_offset + BLOCK_ROWS; row++)
{
double *i_row = &image[row * image_cols];
for (int col = col_offset; col < col_offset + BLOCK_COLS; col++)
{
i_row[col] = round(i_row[col] / quantificator[row - row_offset][col - col_offset]);
}
}
}
void zigzag(int row_offset, int col_offset, int *block_output_size, int *block_output)
{
int index_last_non_zero_value = 0;
// index to last non-zero in a block zigzag array
for (int row = row_offset; row < row_offset + BLOCK_ROWS; row++)
{
double *i_row = &image[row * image_cols];
for (int col = col_offset; col < col_offset + BLOCK_COLS; col++)
{
int temp_index = zigzag_index[(row - row_offset) * 8 + (col - col_offset)];
block_output[temp_index] = i_row[col];
if (i_row[col] != 0 && temp_index > index_last_non_zero_value)
{
index_last_non_zero_value = temp_index + 1;
}
}
}
*block_output_size = index_last_non_zero_value;
}
};
|
#include <systemc.h>
#include <stdio.h>
#include <vector>
#include <string>
#include <stdlib.h>
#include <gtkmm.h>
#include <random>
#include <boost/thread.hpp>
using namespace std;
using namespace Gtk;
using namespace boost;
#include "../gladicapi/data_recorder.h"
#include "../gladicapi/data_check.h"
bool EEP_EOP;
unsigned int finish = 0;
bool link_start = false;
bool link_disable = false;
bool auto_start = false;
//systemc and verilog
bool global_reset = false;
//verilog variables
bool verilog_link_start = false;
bool verilog_link_disable = false;
bool verilog_auto_start = false;
int frquency_nano_second = 500;
vector<string> data_col_store;
data_recorder *REC_TX_SPW;
data_check *COMPARE_SPW;
vector<string> data_col_store0;
data_recorder *REC_TX_SPWSC;
data_check *COMPARE_SPW_RX;
unsigned long int a = 0;
int clock_systemc = 2;
//send data systemC
bool start_send_data_verilog = false;
bool enable_time_code_verilog = false;
bool start_send_data = false;
bool start_tick_data = false;
vector<sc_uint<9> > data_generated_sc;
sc_uint<9> intermediate_systemc;
sc_uint<9> intermediate_sc;
unsigned int data_iteration_sc_aux = 0;
unsigned int data_iteration_sc = 0;
vector<sc_uint<9> > data_generated_verilog;
sc_uint<9> intermediate;
sc_uint<9> intermediate_verilog;
unsigned int data_iteration = 0;
unsigned int data_iteration_vlog = 0;
sc_uint<9> intermediate_data;
void data_rx_sc_o(unsigned int type_char, sc_uint<4> control, sc_uint<4> last_control_sys , sc_uint<10> data , sc_uint<10> timecode_sys);
#include "top_spw.h"
//Data generation
unsigned long int max_data = 255;
std::random_device rd;
std::uniform_int_distribution<unsigned long int> data_in(0,255);
std::uniform_int_distribution<unsigned long int> nchar(1,max_data);//eop-eep
class sc_TOP_SPW;
SC_MODULE(sc_TOP_SPW)
{
sc_clock CLOCK;
sc_signal<bool> RESET;
sc_signal<bool> LINK_START;
sc_signal<bool> LINK_DISABLE;
sc_signal<bool> AUTO_START;
sc_signal<sc_uint<4> > FSM_SPW_OUT;
sc_signal<sc_uint<4> > FSM_TX;
sc_signal<sc_uint<10> > CLOCK_GEN;
sc_signal<bool> E_SEND_DATA;
sc_signal<bool> BUFFER_READY;
sc_signal<sc_uint<9> > DATARX_FLAG;
sc_signal<bool> BUFFER_WRITE;
sc_signal<sc_uint<8> > TIME_OUT;
sc_signal<bool> TICK_OUT;
sc_signal<bool> CONTROL_FLAG_OUT;
sc_signal<uint> DOUT;
sc_signal<uint> SOUT;
sc_signal<uint> DIN;
sc_signal<uint> SIN;
sc_TOP DUT;
SC_CTOR(sc_TOP_SPW) :CLOCK("CLOCK",20,SC_NS),
RESET("RESET"),
LINK_DISABLE("LINK_DISABLE"),
LINK_START("LINK_START"),
AUTO_START("AUTO_START"),
FSM_SPW_OUT("FSM_SPW_OUT"),
CLOCK_GEN("CLOCK_GEN"),
E_SEND_DATA("E_SEND_DATA"),
DOUT("DOUT"),
SOUT("SOUT"),
FSM_TX("FSM_TX"),
DIN("DIN"),
SIN("SIN"),
BUFFER_READY("BUFFER_READY"),
DATARX_FLAG("DATARX_FLAG"),
BUFFER_WRITE("BUFFER_WRITE"),
TIME_OUT("TIME_OUT"),
TICK_OUT("TICK_OUT"),
CONTROL_FLAG_OUT("CONTROL_FLAG_OUT"),
DUT("DUT") {
DUT.CLOCK(CLOCK);
DUT.RESET(RESET);
DUT.LINK_DISABLE(LINK_DISABLE);
DUT.AUTO_START(AUTO_START);
DUT.LINK_START(LINK_START);
DUT.FSM_SPW_OUT(FSM_SPW_OUT);
DUT.CLOCK_GEN(CLOCK_GEN);
DUT.E_SEND_DATA(E_SEND_DATA);
DUT.FSM_TX(FSM_TX);
DUT.DOUT(DOUT);
DUT.SOUT(SOUT);
DUT.DIN(DIN);
DUT.SIN(SIN);
DUT.BUFFER_READY(BUFFER_READY);
DUT.DATARX_FLAG(DATARX_FLAG);
DUT.BUFFER_WRITE(BUFFER_WRITE);
DUT.TIME_OUT(TIME_OUT);
DUT.TICK_OUT(TICK_OUT);
DUT.CONTROL_FLAG_OUT(CONTROL_FLAG_OUT);
cout << "SC_CTOR(sc_TOP_SPW)" << endl;
}
};
Glib::RefPtr<Gtk::Builder> builder;
Gtk::Window *window;
Gtk::Button *BtnFinsihSimulation;
Gtk::Button *BtnLinkEnable;
Gtk::Button *BtnLinkDisable;
Gtk::Button *BtnAutoStart;
Gtk::Button *BtnReset;
Gtk::Button *BtnSpaceWireVerilog;
Gtk::CheckButton *CheckbtnLinkEnable;
Gtk::CheckButton *CheckbtnAutoStart;
Gtk::CheckButton *CheckbtnLinkDisable;
//Execute test
Gtk::Button *BtnSimpleTest;
Gtk::CheckButton *CheckBtnEop;
Gtk::CheckButton *CheckBtnEep;
Gtk::CheckButton *CheckBtnTimeCode;
//Generate data
Gtk::Button *BtnGenerationDataVerilog;
Gtk::CheckButton *CheckBtnEopGenVerilog;
Gtk::CheckButton *CheckBtnEepGenVerilog;
Gtk::CheckButton *CheckBtnTimeCodeGenVerilog;
Gtk::Button *BtnTxFrequency;
Gtk::Entry *EntryFrequency;
Gtk::Button *BtnChangeFrequencyVerilog;
Gtk::Entry *EntryFrequencyVerilog;
Gtk::Button *BtnSendDataScTx;
Gtk::Button *BtnTimeCodeScTx;
Gtk::Button *BtnGenerateDataSc;
Gtk::CheckButton *CheckBtnEepGenSystemC;
Gtk::CheckButton *CheckBtnEopGenSystemC;
Gtk::Label *lblStatus;
sc_TOP_SPW *sn_top;
extern "C" Control_SC* create_object()
{
return new Control_SC;
}
extern "C" void destroy_object( Control_SC* object )
{
delete object;
}
/*GTKMM CONTROL*/
void on_BtnFinsihSimulation_clicked()
{
cout<< "End Simulation" <<endl;
Gtk::Main::quit();
finish = 1;
REC_TX_SPW->endsimulation();
REC_TX_SPWSC->endsimulation();
}
void on_BtnLinkEnable_clicked()
{
link_start = !link_start;
}
void on_BtnLinkDisable_clicked()
{
link_disable = !link_disable;
}
void on_BtnAutoStart_clicked()
{
auto_start = !auto_start;
}
void on_BtnReset_clicked()
{
global_reset = !global_reset;
}
void on_BtnSpaceWireVerilog_clicked()
{
if(!CheckbtnLinkEnable->get_active())
{
verilog_link_start = false;
lblStatus->set_text("LINKENABLE VERILOG IS OFF");
}
if(!CheckbtnAutoStart->get_active())
{
verilog_auto_start = false;
lblStatus->set_text("AUTOSTART VERILOG IS OFF");
}
if(!CheckbtnLinkDisable->get_active())
{
verilog_link_disable = false;
lblStatus->set_text("AUTOSTART VERILOG IS OFF");
}
if(CheckbtnLinkEnable->get_active())
{
verilog_link_start = true;
lblStatus->set_text("LINKENABLE VERILOG IS ON");
}
if(CheckbtnAutoStart->get_active())
{
verilog_auto_start = true;
lblStatus->set_text("AUTOSTART VERILOG IS ON");
}
if(CheckbtnLinkDisable->get_active())
{
verilog_link_disable = true;
lblStatus->set_text("LINKDISABLE VERILOG IS ON");
}
}
void on_BtnSimpleTest_clicked()
{
if(CheckBtnEopGenVerilog->get_active())
{
start_send_data_verilog = true;
}
else
{
start_send_data_verilog = false;
}
if(CheckBtnTimeCodeGenVerilog->get_active())
{
enable_time_code_verilog = true;
}
else
{
enable_time_code_verilog = false;
}
}
void on_BtnGenerationDataVerilog_clicked()
{
data_generated_verilog.clear();
data_iteration=0;
data_iteration_vlog=0;
if(CheckBtnEopGenVerilog->get_active())
{
for(int cnt_max_data = 0; cnt_max_data < max_data;cnt_max_data++)
{
if(cnt_max_data >= 0 && cnt_max_data < max_data)
{
intermediate_verilog(7,0) = data_in(rd);
intermediate_verilog(8,8) = 0;
data_generated_verilog.push_back(intermediate_verilog);
}
intermediate_verilog=0;
}
intermediate_verilog(8,8) = 1;
intermediate_verilog(7,0) = 0;
data_generated_verilog.push_back(intermediate_verilog);
intermediate_verilog=0;
}else if(CheckBtnEepGenVerilog->get_active())
{
for(unsigned int cnt_max_data = 0; cnt_max_data <= max_data;cnt_max_data++)
{
if(cnt_max_data == 0 || cnt_max_data == max_data)
{
intermediate_verilog(8,8) = 1;
intermediate_verilog(7,0) = 1;
}else if(cnt_max_data > 0 && cnt_max_data < max_data)
{
intermediate_verilog(7,0) = data_in(rd);
intermediate_verilog(8,8) = 0;
}
else
{
intermediate_verilog(7,0) = data_in(rd);
intermediate_verilog(8,8) = 0;
}
data_generated_verilog.push_back(intermediate_verilog);
intermediate_verilog=0;
}
intermediate_verilog(7,0) = 1;
intermediate_verilog(8,8) = 1;
data_generated_verilog[nchar(rd)] = intermediate_verilog;
}
}
void on_BtnTxFrequency_clicked()
{
string aux = EntryFrequency->get_text();
switch(atoi(aux.c_str()))
{
case 2:
sn_top->CLOCK_GEN = 1;
lblStatus->set_text("TX CLOCK SYSTEMC SET IN 2MHz");
break;
case 10:
sn_top->CLOCK_GEN = 2;
lblStatus->set_text("TX CLOCK SYSTEMC SET IN 10MHz");
break;
case 20:
sn_top->CLOCK_GEN = 4;
lblStatus->set_text("TX CLOCK SYSTEMC SET IN 20MHz");
break;
case 50:
sn_top->CLOCK_GEN = 8;
lblStatus->set_text("TX CLOCK SYSTEMC SET IN 50MHz");
break;
case 100:
sn_top->CLOCK_GEN = 16;
lblStatus->set_text("TX CLOCK SYSTEMC SET IN 100MHz");
break;
case 150:
sn_top->CLOCK_GEN = 32;
lblStatus->set_text("TX CLOCK SYSTEMC SET IN 150MHz");
break;
case 200:
sn_top->CLOCK_GEN = 64;
lblStatus->set_text("TX CLOCK SYSTEMC SET IN 200MHz");
break;
case 201:
sn_top->CLOCK_GEN = 128;
lblStatus->set_text("TX CLOCK SYSTEMC SET IN 201MHz");
break;
case 250:
sn_top->CLOCK_GEN = 256;
lblStatus->set_text("TX CLOCK SYSTEMC SET IN 250MHz");
break;
case 280:
sn_top->CLOCK_GEN = 512;
lblStatus->set_text("TX CLOCK SYSTEMC SET IN 280MHz");
break;
}
}
void on_BtnTimeCodeScTx_clicked()
{
start_tick_data = !start_tick_data;
if(start_tick_data)
{lblStatus->set_text("TIME CODE ENABLED ON TX SYSTEMC");}
else
{lblStatus->set_text("TIME CODE DISABLED ON TX SYSTEMC");}
}
void on_BtnSendDataScTx_clicked()
{
start_send_data = !start_send_data;
if(start_send_data)
{lblStatus->set_text("SEND DATA ENABLED TX SYSTEMC");}
else
{lblStatus->set_text("SEND DATA DISABLED TX SYSTEMC");}
}
void on_BtnGenerateDataSc_clicked()
{
data_generated_sc.clear();
data_iteration_sc_aux=0;
data_iteration_sc=0;
if(CheckBtnEopGenSystemC->get_active())
{
for(int cnt_max_data = 0; cnt_max_data <= max_data;cnt_max_data++)
{
if(cnt_max_data > 0 && cnt_max_data < max_data)
{
intermediate_sc(7,0) = data_in(rd);
intermediate_sc(8,8) = 0;
}
data_generated_sc.push_back(intermediate_sc);
}
intermediate_sc(8,8) = 1;
intermediate_sc(7,0) = 0;
data_generated_sc.push_back(intermediate_verilog);
intermediate_sc=0;
}else if(CheckBtnEepGenSystemC->get_active())
{
for(unsigned int cnt_max_data = 0; cnt_max_data <= max_data;cnt_max_data++)
{
if(cnt_max_data == 0 || cnt_max_data == max_data)
{
intermediate_sc(8,8) = 1;
intermediate_sc(7,0) = 1;
}else if(cnt_max_data > 0 && cnt_max_data < max_data)
{
intermediate_sc(7,0) = data_in(rd);
intermediate_sc(8,8) = 0;
}
data_generated_sc.push_back(intermediate_sc);
}
intermediate_sc(7,0) = 1;
intermediate_sc(8,8) = 1;
data_generated_sc[nchar(rd)] = intermediate_sc;
}
}
void on_BtnChangeFrequencyVerilog_clicked()
{
string aux = EntryFrequencyVerilog->get_text();
switch(atoi(aux.c_str()))
{
case 2:
frquency_nano_second = 500;
break;
case 10:
frquency_nano_second = 100;
break;
case 20:
frquency_nano_second = 50;
break;
case 50:
frquency_nano_second = 20;
break;
case 100:
frquency_nano_second = 10;
break;
case 150:
frquency_nano_second = 7;
break;
case 200:
frquency_nano_second = 5;
break;
case 201:
frquency_nano_second = 4;
break;
case 250:
frquency_nano_second = 4;
break;
case 280:
frquency_nano_second = 3;
break;
default:
frquency_nano_second = 500;
break;
}
}
void thread_gtkmm_run()
{
//GRAPHICAL INTERFACE
Main Application(true);
builder = Gtk::Builder::create_from_file("SpaceWrireTestSuit.glade");
builder->get_widget("SpaceWireTestStress", window);
builder->get_widget("BtnFinsihSimulation", BtnFinsihSimulation);
builder->get_widget("BtnLinkEnable", BtnLinkEnable);
builder->get_widget("BtnLinkDisable", BtnLinkDisable);
builder->get_widget("BtnAutoStart", BtnAutoStart);
builder->get_widget("BtnReset", BtnReset);
builder->get_widget("BtnSpaceWireVerilog", BtnSpaceWireVerilog);
builder->get_widget("CheckbtnLinkDisable", CheckbtnLinkDisable);
builder->get_widget("CheckbtnAutoStart", CheckbtnAutoStart);
builder->get_widget("CheckbtnLinkEnable", CheckbtnLinkEnable);
builder->get_widget("BtnGenerationDataVerilog", BtnGenerationDataVerilog);
builder->get_widget("BtnSimpleTest", BtnSimpleTest);
builder->get_widget("CheckBtnEopGenVerilog", CheckBtnEopGenVerilog);
builder->get_widget("CheckBtnEepGenVerilog", CheckBtnEepGenVerilog);
builder->get_widget("CheckBtnTimeCodeGenVerilog", CheckBtnTimeCodeGenVerilog);
builder->get_widget("BtnChangeFrequencyVerilog", BtnChangeFrequencyVerilog);
builder->get_widget("EntryFrequencyVerilog", EntryFrequencyVerilog);
builder->get_widget("BtnTxFrequency", BtnTxFrequency);
builder->get_widget("EntryFrequency", EntryFrequency);
builder->get_widget("BtnSendDataScTx", BtnSendDataScTx);
builder->get_widget("BtnTimeCodeScTx", BtnTimeCodeScTx);
builder->get_widget("BtnGenerateDataSc", BtnGenerateDataSc);
builder->get_widget("CheckBtnEepGenSystemC", CheckBtnEepGenSystemC);
builder->get_widget("CheckBtnEopGenSystemC", CheckBtnEopGenSystemC);
builder->get_widget("lblStatus",lblStatus);
BtnFinsihSimulation->signal_clicked().connect(sigc::ptr_fun(&on_BtnFinsihSimulation_clicked));
BtnLinkEnable->signal_clicked().connect(sigc::ptr_fun(&on_BtnLinkEnable_clicked));
BtnLinkDisable->signal_clicked().connect(sigc::ptr_fun(&on_BtnLinkDisable_clicked));
BtnAutoStart->signal_clicked().connect(sigc::ptr_fun(&on_BtnAutoStart_clicked));
BtnReset->signal_clicked().connect(sigc::ptr_fun(&on_BtnReset_clicked));
BtnSpaceWireVerilog->signal_clicked().connect(sigc::ptr_fun(&on_BtnSpaceWireVerilog_clicked));
BtnSimpleTest->signal_clicked().connect(sigc::ptr_fun(&on_BtnSimpleTest_clicked));
BtnChangeFrequencyVerilog->signal_clicked().connect(sigc::ptr_fun(&on_BtnChangeFrequencyVerilog_clicked));
BtnGenerationDataVerilog->signal_clicked().connect(sigc::ptr_fun(&on_BtnGenerationDataVerilog_clicked));
BtnTxFrequency->signal_clicked().connect(sigc::ptr_fun(&on_BtnTxFrequency_clicked));
BtnSendDataScTx->signal_clicked().connect(sigc::ptr_fun(&on_BtnSendDataScTx_clicked));
BtnTimeCodeScTx->signal_clicked().connect(sigc::ptr_fun(&on_BtnTimeCodeScTx_clicked));
BtnGenerateDataSc->signal_clicked().connect(sigc::ptr_fun(&on_BtnGenerateDataSc_clicked));
window->set_title("GLADIC SPACEWIRE TEST TOOL");
Application.run(*window);
}
Control_SC::Control_SC()
{
clock_systemc = 2;
sn_top = new sc_TOP_SPW("sc_TOP_SPW");
boost::thread workerThreadGTKMM(thread_gtkmm_run);
data_col_store.push_back("CONTROL TYPE");
data_col_store.push_back("NUMBER GENERATED");
data_col_store.push_back("NUMBER RECEIVED");
data_col_store.push_back("COMPARE");
data_col_store.push_back("TIME STAMP");
REC_TX_SPW = new data_recorder("test_suit_vlog_sc.html",data_col_store,"test_suit_vlog_sc.html","TX VERILOG 2 RX SYSTEMC");
REC_TX_SPW->initialize();
COMPARE_SPW = new data_check();
data_col_store.clear();
data_col_store0.push_back("CONTROL TYPE");
data_col_store0.push_back("NUMBER GENERATED");
data_col_store0.push_back("NUMBER RECEIVED");
data_col_store0.push_back("COMPARE");
data_col_store0.push_back("TIME STAMP");
REC_TX_SPWSC = new data_recorder("test_suit_sc_vlog.html",data_col_store0,"test_suit_sc_vlog.html","TX SYSTEMC 2 RX VERILOG");
COMPARE_SPW_RX = new data_check();
REC_TX_SPWSC->initialize();
data_col_store0.clear();
}
void Control_SC::init()
{
sn_top->RESET = true;
sn_top->LINK_DISABLE = false;
sn_top->LINK_START = false;
sn_top->AUTO_START = false;
sn_top->E_SEND_DATA = false;
sn_top->CLOCK_GEN = 1;
frquency_nano_second = 500;
}
void autostart()
{
if(auto_start)
{
sn_top->AUTO_START = true;
//lblStatus->set_text("AUTOSTART ENABLED ON TX SYSTEMC");
}
else
{
sn_top->AUTO_START = false;
//lblStatus->set_text("AUTOSTART DISABLED ON TX SYSTEMC");
}
}
void linkstart()
{
if(link_start)
{
sn_top->LINK_START = true;
//lblStatus->set_text("LINKSTART ENABLED ON TX SYSTEMC");
}
else
{
sn_top->LINK_START = false;
//lblStatus->set_text("LINKSTART DISABLED ON TX SYSTEMC");
}
}
void linkdisable()
{
if(link_disable)
{
sn_top->LINK_DISABLE = true;
//lblStatus->set_text("LINKDISABLE ENABLED ON TX SYSTEMC");
}
else
{
sn_top->LINK_DISABLE = false;
//lblStatus->set_text("LINKDISABLE DISABLED ON TX SYSTEMC");
}
}
void send_data_tx_sc()
{
if(start_send_data)
{
sn_top->E_SEND_DATA = true;
}
else
{
sn_top->E_SEND_DATA = false;
}
}
void Control_SC::run_sim()
{
autostart();
linkstart();
linkdisable();
send_data_tx_sc();
sc_start(clock_systemc,SC_NS);
}
/* END OF SIMULATION */
void Control_SC::stop_sim()
{
sc_stop();
}
/* RESET HIGH */
bool Control_SC::reset_set()
{
if(global_reset)
{
sn_top->RESET = false;
}else
{
sn_top->RESET = true;
}
return sn_top->RESET;
}
unsigned int Control_SC::get_value_dout()
{
return sn_top->DOUT.read();
}
unsigned int Control_SC::get_value_sout()
{
return sn_top->SOUT.read();
}
void Control_SC::set_rx_sin(unsigned int strobe)
{
sn_top->SIN = strobe;
}
void Control_SC::set_rx_din(unsigned int data)
{
sn_top->DIN = data;
}
unsigned int Control_SC::get_spw_fsm()
{
return sn_top->FSM_SPW_OUT.read();
}
unsigned int Control_SC::finish_simulation()
{
return finish;
}
//verilog variables
bool Control_SC::verilog_linkenable()
{
return verilog_link_start;
}
bool Control_SC::verilog_autostart()
{
return verilog_auto_start;
}
bool Control_SC::verilog_linkdisable()
{
return verilog_link_disable;
}
float Control_SC::verilog_frequency()
{
return frquency_nano_second;
}
//Test verilog
bool Control_SC::start_tx_test()
{
return start_send_data_verilog;
}
bool Control_SC::enable_time_code_tx_test()
{
return enable_time_code_verilog;
}
void Control_SC::end_tx_test()
{
start_send_data_verilog = enable_time_code_verilog = false;
}
int Control_SC::size_data_test_vlog()
{
return data_generated_verilog.size();
}
int Control_SC::size_data_test_sc()
{
return data_generated_sc.size();
}
unsigned int Control_SC::take_data(unsigned int a)
{
intermediate = data_generated_verilog[a];
return intermediate(8,0);
}
void Control_SC::data_o(unsigned int data, unsigned int pos)
{
sc_uint<9> intermediate = data;
data_col_store0.clear();
if(data_iteration_sc <= data_generated_sc.size()-1)
{
data_col_store0.push_back("DATA");
intermediate_sc=data_generated_sc[pos];
data_col_store0.push_back(intermediate_sc.to_string(SC_HEX));
data_col_store0.push_back(intermediate.to_string(SC_HEX));
data_col_store0.push_back(" ");
COMPARE_SPW_RX->compare_test(&data_col_store0);
data_col_store0.push_back(sc_time_stamp().to_string());
REC_TX_SPWSC->storedata(data_col_store0);
data_iteration_sc++;
}else
{
data_iteration_sc = 0;
}
}
void Control_SC::data_rx_vlog_loopback_o(unsigned int data, unsigned int pos)
{
sc_uint<9> intermediate;
data_col_store.clear();
data_col_store.push_back("DATA");
intermediate = data_generated_verilog[pos];
data_col_store.push_back(intermediate.to_string(SC_HEX));
intermediate = data;
data_col_store.push_back(intermediate(8,0).to_string(SC_HEX));
data_col_store.push_back(" ");
COMPARE_SPW->compare_test(&data_col_store);
data_col_store.push_back(sc_time_stamp().to_string());
REC_TX_SPW->storedata(data_col_store);
}
void data_rx_sc_o(unsigned int type_char, sc_uint<4> control, sc_uint<4> last_control_sys , sc_uint<10> data , sc_uint<10> timecode_sys)
{
data_col_store.clear();
switch(type_char)
{
case 0:
data_col_store.push_back("NULL");
data_col_store.push_back(" - ");
data_col_store.push_back(last_control_sys(2,0).to_string(SC_HEX) + control(2,0).to_string());
data_col_store.push_back(" - ");
data_col_store.push_back(sc_time_stamp().to_string());
REC_TX_SPW->storedata(data_col_store);
break;
case 1:
data_col_store.push_back("FCT");
data_col_store.push_back(" - ");
data_col_store.push_back(last_control_sys(2,0).to_string(SC_HEX) + control(2,0).to_string());
data_col_store.push_back(" - ");
data_col_store.push_back(sc_time_stamp().to_string());
REC_TX_SPW->storedata(data_col_store);
break;
case 2:
data_col_store.push_back("EOP");
intermediate_data = data_generated_verilog[data_iteration];
data_col_store.push_back(intermediate_data.to_string(SC_HEX));
data_col_store.push_back(last_control
|
_sys(2,0).to_string(SC_HEX) + control(2,0).to_string());
data_col_store.push_back(" ");
COMPARE_SPW->compare_test(&data_col_store);
data_iteration++;
data_col_store.push_back(sc_time_stamp().to_string());
REC_TX_SPW->storedata(data_col_store);
break;
case 3:
data_col_store.push_back("EEP");
intermediate_data = data_generated_verilog[data_iteration];
data_col_store.push_back(intermediate_data.to_string(SC_HEX));
data_col_store.push_back(last_control_sys(2,0).to_string(SC_HEX) + control(2,0).to_string());
data_col_store.push_back(" ");
COMPARE_SPW->compare_test(&data_col_store);
data_iteration++;
data_col_store.push_back(sc_time_stamp().to_string());
REC_TX_SPW->storedata(data_col_store);
break;
case 4:
data_col_store.push_back("INVALID CONNECTION");
data_col_store.push_back(" - ");
data_col_store.push_back(last_control_sys(2,0).to_string(SC_HEX) + control(2,0).to_string());
data_col_store.push_back(" - ");
data_col_store.push_back(sc_time_stamp().to_string());
REC_TX_SPW->storedata(data_col_store);
break;
case 5:
data_col_store.push_back("DATA");
intermediate_data = data_generated_verilog[data_iteration];
data_col_store.push_back(intermediate_data.to_string(SC_HEX));
data_col_store.push_back(data(8,0).to_string(SC_HEX));
data_col_store.push_back(" ");
COMPARE_SPW->compare_test(&data_col_store);
data_col_store.push_back(sc_time_stamp().to_string());
REC_TX_SPW->storedata(data_col_store);
data_iteration++;
break;
case 6:
data_col_store.push_back("TIMECODE");
data_col_store.push_back(" - ");
data_col_store.push_back(timecode_sys(7,0).to_string());
data_col_store.push_back(" - ");
data_col_store.push_back(sc_time_stamp().to_string());
REC_TX_SPW->storedata(data_col_store);
break;
}
}
unsigned int Control_SC::clock_tx()
{
return sn_top->DUT.CLOCK_TX_OUT.read();
}
|
/*
* Adder.h
* SystemC_SimpleAdder
*
* Created by Le Gal on 07/05/07.
* Copyright 2007 __MyCompanyName__. All rights reserved.
*
*/
#ifndef _BitsToBytes_
#define _BitsToBytes_
#include "systemc.h"
#include <cstdint>
SC_MODULE(BitsToBytes)
{
public:
sc_in < bool > clock;
sc_in < bool > reset;
sc_fifo_in < sc_uint<1> > e;
sc_fifo_out< sc_uint<8> > s;
SC_CTOR(BitsToBytes)
{
SC_CTHREAD(do_gen, clock.pos());
reset_signal_is(reset,true);
}
private:
void do_gen( )
{
#if 1
while ( true )
{
uint8_t v = 0;
for( uint32_t q = 0; q < 8 ; q += 1 )
{
uint8_t E = e.read();
v = (v << 1) | E;
}
s.write( v );
}
#else
while ( true )
{
uint8_t bits[8];
for( uint32_t q = 0; q < 8 ; q += 1 )
bits[q] = e.read();
uint8_t v = 0;
for( uint32_t q = 0; q < 8 ; q += 1 )
{
v = (v << 1) | bits[q];
}
for( uint32_t q = 0; q < 8 ; q += 1 )
printf("%d", bits[q]);
printf(" = 0x%2.2X\n", v);
s.write( v );
}
#endif
}
};
#endif
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
// Version: 2020.1
// Copyright (C) 1986-2020 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _trames_separ2_do_gen_HH_
#define _trames_separ2_do_gen_HH_
#include "systemc.h"
#include "AESL_pkg.h"
namespace ap_rtl {
struct trames_separ2_do_gen : public sc_module {
// Port declarations 11
sc_in_clk ap_clk;
sc_in< sc_logic > ap_rst;
sc_in< sc_lv<8> > e_dout;
sc_in< sc_logic > e_empty_n;
sc_out< sc_logic > e_read;
sc_in< sc_logic > detect_dout;
sc_in< sc_logic > detect_empty_n;
sc_out< sc_logic > detect_read;
sc_out< sc_lv<8> > s_din;
sc_in< sc_logic > s_full_n;
sc_out< sc_logic > s_write;
// Module declarations
trames_separ2_do_gen(sc_module_name name);
SC_HAS_PROCESS(trames_separ2_do_gen);
~trames_separ2_do_gen();
sc_trace_file* mVcdFile;
sc_signal< sc_logic > e_blk_n;
sc_signal< sc_lv<5> > ap_CS_fsm;
sc_signal< sc_logic > ap_CS_fsm_state2;
sc_signal< sc_logic > ap_CS_fsm_state3;
sc_signal< sc_lv<1> > icmp_ln50_fu_137_p2;
sc_signal< sc_logic > ap_CS_fsm_state4;
sc_signal< sc_lv<1> > icmp_ln55_fu_149_p2;
sc_signal< sc_logic > ap_CS_fsm_state5;
sc_signal< sc_lv<1> > tmp_reg_173;
sc_signal< sc_lv<1> > icmp_ln60_fu_161_p2;
sc_signal< sc_logic > detect_blk_n;
sc_signal< sc_logic > s_blk_n;
sc_signal< sc_lv<1> > grp_read_fu_90_p2;
sc_signal< bool > ap_block_state2;
sc_signal< sc_lv<9> > i_fu_143_p2;
sc_signal< bool > ap_block_state3;
sc_signal< sc_lv<11> > i_1_fu_155_p2;
sc_signal< bool > ap_block_state4;
sc_signal< sc_lv<8> > i_2_fu_167_p2;
sc_signal< bool > ap_predicate_op53_read_state5;
sc_signal< bool > ap_predicate_op54_write_state5;
sc_signal< bool > ap_predicate_op55_read_state5;
sc_signal< bool > ap_block_state5;
sc_signal< sc_lv<9> > i_0_reg_104;
sc_signal< sc_lv<11> > i1_0_reg_115;
sc_signal< sc_lv<8> > i2_0_reg_126;
sc_signal< sc_lv<5> > ap_NS_fsm;
static const sc_logic ap_const_logic_1;
static const sc_logic ap_const_logic_0;
static const sc_lv<5> ap_ST_fsm_state2;
static const sc_lv<5> ap_ST_fsm_state3;
static const sc_lv<5> ap_ST_fsm_state4;
static const sc_lv<5> ap_ST_fsm_state5;
static const bool ap_const_boolean_1;
static const sc_lv<32> ap_const_lv32_1;
static const sc_lv<32> ap_const_lv32_2;
static const sc_lv<1> ap_const_lv1_0;
static const sc_lv<32> ap_const_lv32_3;
static const sc_lv<32> ap_const_lv32_4;
static const sc_lv<1> ap_const_lv1_1;
static const sc_lv<9> ap_const_lv9_0;
static const sc_lv<11> ap_const_lv11_0;
static const sc_lv<8> ap_const_lv8_0;
static const sc_lv<9> ap_const_lv9_100;
static const sc_lv<9> ap_const_lv9_1;
static const sc_lv<11> ap_const_lv11_780;
static const sc_lv<11> ap_const_lv11_1;
static const sc_lv<8> ap_const_lv8_80;
static const sc_lv<8> ap_const_lv8_1;
// Thread declarations
void thread_ap_clk_no_reset_();
void thread_ap_CS_fsm_state2();
void thread_ap_CS_fsm_state3();
void thread_ap_CS_fsm_state4();
void thread_ap_CS_fsm_state5();
void thread_ap_block_state2();
void thread_ap_block_state3();
void thread_ap_block_state4();
void thread_ap_block_state5();
void thread_ap_predicate_op53_read_state5();
void thread_ap_predicate_op54_write_state5();
void thread_ap_predicate_op55_read_state5();
void thread_detect_blk_n();
void thread_detect_read();
void thread_e_blk_n();
void thread_e_read();
void thread_grp_read_fu_90_p2();
void thread_i_1_fu_155_p2();
void thread_i_2_fu_167_p2();
void thread_i_fu_143_p2();
void thread_icmp_ln50_fu_137_p2();
void thread_icmp_ln55_fu_149_p2();
void thread_icmp_ln60_fu_161_p2();
void thread_s_blk_n();
void thread_s_din();
void thread_s_write();
void thread_ap_NS_fsm();
};
}
using namespace ap_rtl;
#endif
|
//
// Created by tobias on 09.03.17.
//
#ifndef PROJECT_SLAVEAGENT_H
#define PROJECT_SLAVEAGENT_H
#include "systemc.h"
#include "../../Interfaces/Interfaces.h"
#include "types_reduced.h"
struct SlaveAgent : public sc_module {
//Sections
enum Sections {
IDLE, READ, WRITE,DONE
};
Sections section;
Sections nextsection;
//clock
master_in<bool> clk;
bool clk_pulse;
//Communication between Master and Agent
blocking_in<bus_resp_t> slave_to_agent;
blocking_out<bus_req_t> agent_to_slave;
//Communication on BUSM
shared_in<master_signals> bus_to_agent;
shared_out<slave_signals> agent_to_bus;
//Variables
bus_req_t agent_to_slave_req;
bus_resp_t slave_to_agent_resp;
slave_signals wb_out;
master_signals wb_in;
//Constructor
SC_HAS_PROCESS(SlaveAgent);
SlaveAgent(sc_module_name name) :
section(IDLE),
nextsection(IDLE) {
SC_THREAD(fsm);
}
void fsm() {
while (true) {
section = nextsection;
if (section == IDLE) {
//std::cout << this->name() << " - SLAVE IDLE" << std::endl;
clk->read(clk_pulse);
this->bus_to_agent->get(wb_in);
if (wb_in.cyc == true && wb_in.stb == true && wb_in.we == false) {
nextsection = READ;
} else if (wb_in.cyc == true && wb_in.stb == true && wb_in.we == true) {
nextsection = WRITE;
}
}
if (section == READ) {
//std::cout << this->name() << " - SLAVE READ" << std::endl;
agent_to_slave_req.trans_type = SINGLE_READ;
agent_to_slave_req.addr = wb_in.addr;
agent_to_slave_req.data = false;
agent_to_slave->write(agent_to_slave_req);
slave_to_agent->read(slave_to_agent_resp);
nextsection = DONE;
}
if (section == WRITE) {
//std::cout << this->name() << " - SLAVE WRITE " << std::endl;
agent_to_slave_req.trans_type = SINGLE_WRITE;
agent_to_slave_req.addr = wb_in.addr;
agent_to_slave_req.data = wb_in.data;
agent_to_slave->write(agent_to_slave_req);
slave_to_agent->read(slave_to_agent_resp);
slave_to_agent_resp.data = false;
nextsection = DONE;
}
if (section == DONE) {
clk->read(clk_pulse);
bus_to_agent->get(wb_in);
if(wb_in.cyc == false && wb_in.stb == false){
wb_out.ack = false;
wb_out.err = false;
wb_out.data = false;
nextsection = IDLE;
}else{
wb_out.ack = true;
wb_out.err = slave_to_agent_resp.ack != OK;
wb_out.data = false;
//Is read? -> put data on bus
if (wb_in.we == false) {
wb_out.data = slave_to_agent_resp.data;
}
}
agent_to_bus->set(wb_out);
}
wait(SC_ZERO_TIME);
}
}
};
#endif //PROJECT_SLAVEAGENT_H
|
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD and is protected under U.S. and international copyright
// and other intellectual property laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// AMD, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) AMD shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or AMD had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// AMD products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of AMD products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
#ifndef _icyradio_GND_2_0_H_
#define _icyradio_GND_2_0_H_
#include "xlconstant_v1_1_8.h"
#include "systemc.h"
class icyradio_GND_2_0 : public sc_module {
public:
xlconstant_v1_1_8<1,0> mod;
sc_out< sc_bv<1> > dout;
icyradio_GND_2_0 (sc_core::sc_module_name name);
};
#endif
|
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7_vip:1.0
// IP Revision: 1
#ifndef __PS7_H__
#define __PS7_H__
#include "systemc.h"
#include "xtlm.h"
#include "xtlm_adaptors/xaximm_xtlm2tlm.h"
#include "xtlm_adaptors/xaximm_tlm2xtlm.h"
#include "tlm_utils/simple_initiator_socket.h"
#include "tlm_utils/simple_target_socket.h"
#include "genattr.h"
#include "xilinx-zynq.h"
#include "b_transport_converter.h"
#include "utils/xtlm_aximm_fifo.h"
/***************************************************************************************
*
* A Simple Converter which converts Remote-port's simplae_intiator_sockets<32>->b_transport()
* calls to xTLM sockets bn_transport_x() calls..
*
* This is Only specific to remote-port so not creating seperate header for it.
*
***************************************************************************************/
template <int IN_WIDTH, int OUT_WIDTH>
class rptlm2xtlm_converter : public sc_module{
public:
tlm::tlm_target_socket<IN_WIDTH> target_socket;
xtlm::xtlm_aximm_initiator_socket wr_socket;
xtlm::xtlm_aximm_initiator_socket rd_socket;
rptlm2xtlm_converter<IN_WIDTH, OUT_WIDTH>(sc_module_name name);//:sc_module(name)
void registerUserExtensionHandlerCallback(
void (*callback)(xtlm::aximm_payload*,
const tlm::tlm_generic_payload*));
private:
b_transport_converter<IN_WIDTH, OUT_WIDTH> m_btrans_conv;
xtlm::xaximm_tlm2xtlm_t<OUT_WIDTH> xtlm_bridge;
};
/***************************************************************************************
* Global method, get registered with tlm2xtlm bridge
* This function is called when tlm2xtlm bridge convert tlm payload to xtlm payload.
*
* caller: tlm2xtlm bridge
* purpose: To get master id and other parameters out of genattr_extension
* and use master id to AxUSER PIN of xtlm payload.
*
*
***************************************************************************************/
extern void get_extensions_from_tlm(xtlm::aximm_payload* xtlm_pay, const tlm::tlm_generic_payload* gp);
/***************************************************************************************
* Global method, get registered with xtlm2tlm bridge
* This function is called when xtlm2tlm bridge convert xtlm payload to tlm payload.
*
* caller: xtlm2tlm bridge
* purpose: To create and add master id and other parameters to genattr_extension.
* Master id red from AxID PIN of xtlm payload.
*
*
***************************************************************************************/
extern void add_extensions_to_tlm(const xtlm::aximm_payload* xtlm_pay, tlm::tlm_generic_payload* gp);
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// //
// File: processing_system7_tlm.h //
// //
// Description: zynq_ultra_ps_e_tlm class is a sc_module, act as intermediate layer between //
// xilinx_zynq qemu wrapper and Vivado generated systemc simulation ip wrapper. //
// it's basically created for supporting tlm based xilinx_zynq from xtlm based vivado //
// generated systemc wrapper. this wrapper is live only when SELECTED_SIM_MODEL is set //
// to tlm. it's also act as bridge between vivado wrapper and xilinx_zynq wrapper. //
// it fill the the gap between input/output ports of vivado generated wrapper to //
// xilinx_zynq wrapper signals. This wrapper is auto generated by ttcl scripts //
// based on IP configuration in vivado. //
// //
// //
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
class processing_system7_v5_5_tlm : public sc_core::sc_module {
public:
// Non-AXI ports are declared here
sc_core::sc_in<bool> I2C0_SDA_I;
sc_core::sc_out<bool> I2C0_SDA_O;
sc_core::sc_out<bool> I2C0_SDA_T;
sc_core::sc_in<bool> I2C0_SCL_I;
sc_core::sc_out<bool> I2C0_SCL_O;
sc_core::sc_out<bool> I2C0_SCL_T;
sc_core::sc_out<bool> TTC0_WAVE0_OUT;
sc_core::sc_out<bool> TTC0_WAVE1_OUT;
sc_core::sc_out<bool> TTC0_WAVE2_OUT;
sc_core::sc_out<sc_dt::sc_bv<2> > USB0_PORT_INDCTL;
sc_core::sc_out<bool> USB0_VBUS_PWRSELECT;
sc_core::sc_in<bool> USB0_VBUS_PWRFAULT;
sc_core::sc_in<bool> M_AXI_GP0_ACLK;
sc_core::sc_out<sc_dt::sc_bv<2> > DMA0_DATYPE;
sc_core::sc_out<bool> DMA0_DAVALID;
sc_core::sc_out<bool> DMA0_DRREADY;
sc_core::sc_out<sc_dt::sc_bv<2> > DMA1_DATYPE;
sc_core::sc_out<bool> DMA1_DAVALID;
sc_core::sc_out<bool> DMA1_DRREADY;
sc_core::sc_in<bool> DMA0_ACLK;
sc_core::sc_in<bool> DMA0_DAREADY;
sc_core::sc_in<bool> DMA0_DRLAST;
sc_core::sc_in<bool> DMA0_DRVALID;
sc_core::sc_in<bool> DMA1_ACLK;
sc_core::sc_in<bool> DMA1_DAREADY;
sc_core::sc_in<bool> DMA1_DRLAST;
sc_core::sc_in<bool> DMA1_DRVALID;
sc_core::sc_in<sc_dt::sc_bv<2> > DMA0_DRTYPE;
sc_core::sc_in<sc_dt::sc_bv<2> > DMA1_DRTYPE;
sc_core::sc_out<bool> FCLK_CLK0;
sc_core::sc_out<bool> FCLK_RESET0_N;
sc_core::sc_inout<sc_dt::sc_bv<54> > MIO;
sc_core::sc_inout<bool> DDR_CAS_n;
sc_core::sc_inout<bool> DDR_CKE;
sc_core::sc_inout<bool> DDR_Clk_n;
sc_core::sc_inout<bool> DDR_Clk;
sc_core::sc_inout<bool> DDR_CS_n;
sc_core::sc_inout<bool> DDR_DRSTB;
sc_core::sc_inout<bool> DDR_ODT;
sc_core::sc_inout<bool> DDR_RAS_n;
sc_core::sc_inout<bool> DDR_WEB;
sc_core::sc_inout<sc_dt::sc_bv<3> > DDR_BankAddr;
sc_core::sc_inout<sc_dt::sc_bv<15> > DDR_Addr;
sc_core::sc_inout<bool> DDR_VRN;
sc_core::sc_inout<bool> DDR_VRP;
sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DM;
sc_core::sc_inout<sc_dt::sc_bv<32> > DDR_DQ;
sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DQS_n;
sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DQS;
sc_core::sc_inout<bool> PS_SRSTB;
sc_core::sc_inout<bool> PS_CLK;
sc_core::sc_inout<bool> PS_PORB;
xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_wr_socket;
xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_rd_socket;
//constructor having three paramters
// 1. module name in sc_module_name objec,
// 2. reference to map object of name and integer value pairs
// 3. reference to map object of name and string value pairs
// All the model parameters (integer and string) which are configuration parameters
// of Processing System 7 IP propogated from Vivado
processing_system7_v5_5_tlm(sc_core::sc_module_name name,
xsc::common_cpp::properties&);
~processing_system7_v5_5_tlm();
SC_HAS_PROCESS(processing_system7_v5_5_tlm);
private:
//zynq tlm wrapper provided by Edgar
//module with interfaces of standard tlm
//and input/output ports at signal level
xilinx_zynq* m_zynq_tlm_model;
// Xtlm2tlm_t Bridges
// Converts Xtlm transactions to tlm transactions
// Bridge's Xtlm wr/rd target sockets binds with
// xtlm initiator sockets of processing_system7_tlm and tlm simple initiator
// socket with xilinx_zynq's target socket
// This Bridges converts b_transport to nb_transports and also
// Converts tlm transactions to xtlm transactions.
// Bridge's tlm simple target socket binds with
// simple initiator socket of xilinx_zynqmp and xtlm
// socket with xilinx_zynq's simple target socket
rptlm2xtlm_converter<32, 32> m_rp_bridge_M_AXI_GP0;
// sc_clocks for generating pl clocks
// output pins FCLK_CLK0..3 are drived by these clocks
sc_core::sc_clock FCLK_CLK0_clk;
//Method which is sentive to FCLK_CLK0_clk sc_clock object
//FCLK_CLK0 pin written based on FCLK_CLK0_clk clock value
void trigger_FCLK_CLK0_pin();
//FCLK_RESET0 output reset pin get toggle when emio bank 2's 31th signal gets toggled
//EMIO[2] bank 31th(GPIO[95] signal)acts as reset signal to the PL(refer Zynq UltraScale+ TRM, page no:761)
void FCLK_RESET0_N_trigger();
sc_signal<bool> qemu_rst;
void start_of_simulation();
xsc::common_cpp::properties prop;
};
#endif
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.3
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
#ifndef _FAST_t_opr_HH_
#define _FAST_t_opr_HH_
#include "systemc.h"
#include "AESL_pkg.h"
#include "min_int_s.h"
#include "max_int_s.h"
#include "reg_int_s.h"
#include "FAST_t_opr_k_buf_dEe.h"
#include "FAST_t_opr_core_bjbC.h"
namespace ap_rtl {
struct FAST_t_opr : public sc_module {
// Port declarations 16
sc_in_clk ap_clk;
sc_in< sc_logic > ap_rst;
sc_in< sc_logic > ap_start;
sc_in< sc_logic > start_full_n;
sc_out< sc_logic > ap_done;
sc_in< sc_logic > ap_continue;
sc_out< sc_logic > ap_idle;
sc_out< sc_logic > ap_ready;
sc_out< sc_logic > start_out;
sc_out< sc_logic > start_write;
sc_in< sc_lv<8> > p_src_data_stream_V_dout;
sc_in< sc_logic > p_src_data_stream_V_empty_n;
sc_out< sc_logic > p_src_data_stream_V_read;
sc_out< sc_lv<8> > p_mask_data_stream_V_din;
sc_in< sc_logic > p_mask_data_stream_V_full_n;
sc_out< sc_logic > p_mask_data_stream_V_write;
sc_signal< sc_lv<32> > ap_var_for_const0;
sc_signal< sc_lv<32> > ap_var_for_const1;
// Module declarations
FAST_t_opr(sc_module_name name);
SC_HAS_PROCESS(FAST_t_opr);
~FAST_t_opr();
sc_trace_file* mVcdFile;
FAST_t_opr_k_buf_dEe* k_buf_val_0_V_U;
FAST_t_opr_k_buf_dEe* k_buf_val_1_V_U;
FAST_t_opr_k_buf_dEe* k_buf_val_2_V_U;
FAST_t_opr_k_buf_dEe* k_buf_val_3_V_U;
FAST_t_opr_k_buf_dEe* k_buf_val_4_V_U;
FAST_t_opr_k_buf_dEe* k_buf_val_5_V_U;
FAST_t_opr_core_bjbC* core_buf_val_0_V_U;
FAST_t_opr_core_bjbC* core_buf_val_1_V_U;
min_int_s* tmp_76_1_min_int_s_fu_581;
min_int_s* tmp_76_3_min_int_s_fu_587;
min_int_s* tmp_76_5_min_int_s_fu_593;
min_int_s* tmp_76_7_min_int_s_fu_599;
min_int_s* tmp_76_9_min_int_s_fu_605;
min_int_s* tmp_76_s_min_int_s_fu_611;
min_int_s* tmp_76_2_min_int_s_fu_617;
min_int_s* tmp_76_4_min_int_s_fu_623;
min_int_s* tmp_83_1_min_int_s_fu_629;
min_int_s* tmp_83_3_min_int_s_fu_635;
min_int_s* tmp_83_5_min_int_s_fu_641;
min_int_s* tmp_83_7_min_int_s_fu_647;
min_int_s* tmp_83_9_min_int_s_fu_653;
min_int_s* tmp_83_s_min_int_s_fu_659;
min_int_s* tmp_83_2_min_int_s_fu_665;
min_int_s* tmp_83_4_min_int_s_fu_671;
min_int_s* tmp_90_1_min_int_s_fu_677;
min_int_s* tmp_90_3_min_int_s_fu_683;
min_int_s* tmp_90_5_min_int_s_fu_689;
min_int_s* tmp_90_7_min_int_s_fu_695;
min_int_s* tmp_90_9_min_int_s_fu_701;
min_int_s* tmp_90_s_min_int_s_fu_707;
min_int_s* tmp_90_2_min_int_s_fu_713;
min_int_s* tmp_90_4_min_int_s_fu_719;
min_int_s* tmp_27_min_int_s_fu_725;
min_int_s* tmp_29_min_int_s_fu_731;
min_int_s* tmp_98_1_min_int_s_fu_737;
min_int_s* tmp_101_1_min_int_s_fu_743;
min_int_s* tmp_98_2_min_int_s_fu_749;
min_int_s* tmp_101_2_min_int_s_fu_755;
min_int_s* b0_min_int_s_fu_761;
min_int_s* b0_1_min_int_s_fu_768;
min_int_s* b0_s_min_int_s_fu_775;
min_int_s* b0_1_1_min_int_s_fu_782;
min_int_s* b0_2_min_int_s_fu_789;
min_int_s* tmp_98_3_min_int_s_fu_796;
min_int_s* tmp_101_3_min_int_s_fu_802;
min_int_s* tmp_98_4_min_int_s_fu_808;
min_int_s* tmp_101_4_min_int_s_fu_814;
min_int_s* tmp_98_5_min_int_s_fu_820;
min_int_s* tmp_101_5_min_int_s_fu_826;
min_int_s* b0_1_2_min_int_s_fu_832;
min_int_s* b0_3_min_int_s_fu_838;
min_int_s* b0_1_3_min_int_s_fu_845;
min_int_s* b0_4_min_int_s_fu_852;
min_int_s* b0_1_4_min_int_s_fu_859;
min_int_s* b0_5_min_int_s_fu_866;
min_int_s* tmp_98_6_min_int_s_fu_873;
min_int_s* tmp_101_6_min_int_s_fu_879;
min_int_s* tmp_98_7_min_int_s_fu_885;
min_int_s* tmp_101_7_min_int_s_fu_891;
min_int_s* b0_1_5_min_int_s_fu_897;
min_int_s* b0_6_min_int_s_fu_903;
min_int_s* b0_1_6_min_int_s_fu_910;
min_int_s* b0_7_min_int_s_fu_917;
min_int_s* b0_1_7_min_int_s_fu_924;
max_int_s* tmp_78_1_max_int_s_fu_931;
max_int_s* tmp_78_3_max_int_s_fu_937;
max_int_s* tmp_78_5_max_int_s_fu_943;
max_int_s* tmp_78_7_max_int_s_fu_949;
max_int_s* tmp_78_9_max_int_s_fu_955;
max_int_s* tmp_78_s_max_int_s_fu_961;
max_int_s* tmp_78_2_max_int_s_fu_967;
max_int_s* tmp_78_4_max_int_s_fu_973;
max_int_s* tmp_85_1_max_int_s_fu_979;
max_int_s* tmp_85_3_max_int_s_fu_985;
max_int_s* tmp_85_5_max_int_s_fu_991;
max_int_s* tmp_85_7_max_int_s_fu_997;
max_int_s* tmp_85_9_max_int_s_fu_1003;
max_int_s* tmp_85_s_max_int_s_fu_1009;
max_int_s* tmp_85_2_max_int_s_fu_1015;
max_int_s* tmp_85_4_max_int_s_fu_1021;
max_int_s* tmp_92_1_max_int_s_fu_1027;
max_int_s* tmp_92_3_max_int_s_fu_1033;
max_int_s* tmp_92_5_max_int_s_fu_1039;
max_int_s* tmp_92_7_max_int_s_fu_1045;
max_int_s* tmp_92_9_max_int_s_fu_1051;
max_int_s* tmp_92_s_max_int_s_fu_1057;
max_int_s* tmp_92_2_max_int_s_fu_1063;
max_int_s* tmp_92_4_max_int_s_fu_1069;
max_int_s* a0_max_int_s_fu_1075;
max_int_s* a0_1_max_int_s_fu_1083;
max_int_s* a0_s_max_int_s_fu_1091;
max_int_s* a0_1_1_max_int_s_fu_1099;
max_int_s* a0_2_max_int_s_fu_1107;
max_int_s* tmp_30_max_int_s_fu_1115;
max_int_s* tmp_31_max_int_s_fu_1122;
max_int_s* tmp_106_1_max_int_s_fu_1129;
max_int_s* tmp_109_1_max_int_s_fu_1136;
max_int_s* tmp_106_2_max_int_s_fu_1143;
max_int_s* tmp_109_2_max_int_s_fu_1150;
max_int_s* a0_1_2_max_int_s_fu_1156;
max_int_s* a0_3_max_int_s_fu_1162;
max_int_s* a0_1_3_max_int_s_fu_1170;
max_int_s* a0_4_max_int_s_fu_1178;
max_int_s* a0_1_4_max_int_s_fu_1186;
max_int_s* a0_5_max_int_s_fu_1194;
max_int_s* tmp_106_3_max_int_s_fu_1202;
max_int_s* tmp_109_3_max_int_s_fu_1209;
max_int_s* tmp_106_4_max_int_s_fu_1216;
max_int_s* tmp_109_4_max_int_s_fu_1223;
max_int_s* tmp_106_5_max_int_s_fu_1230;
max_int_s* tmp_109_5_max_int_s_fu_1237;
max_int_s* a0_1_5_max_int_s_fu_1243;
max_int_s* a0_6_max_int_s_fu_1249;
max_int_s* a0_1_6_max_int_s_fu_1257;
max_int_s* a0_7_max_int_s_fu_1265;
max_int_s* a0_1_7_max_int_s_fu_1273;
max_int_s* tmp_106_6_max_int_s_fu_1281;
max_int_s* tmp_109_6_max_int_s_fu_1288;
max_int_s* tmp_106_7_max_int_s_fu_1295;
max_int_s* tmp_109_7_max_int_s_fu_1302;
max_int_s* tmp_10_max_int_s_fu_1309;
reg_int_s* grp_reg_int_s_fu_3701;
reg_int_s* grp_reg_int_s_fu_3708;
reg_int_s* grp_reg_int_s_fu_3715;
reg_int_s* grp_reg_int_s_fu_3723;
reg_int_s* grp_reg_int_s_fu_3731;
reg_int_s* grp_reg_int_s_fu_3739;
reg_int_s* grp_reg_int_s_fu_3747;
reg_int_s* grp_reg_int_s_fu_3755;
reg_int_s* grp_reg_int_s_fu_3763;
reg_int_s* grp_reg_int_s_fu_3771;
reg_int_s* grp_reg_int_s_fu_3779;
reg_int_s* grp_reg_int_s_fu_3786;
reg_int_s* grp_reg_int_s_fu_3813;
reg_int_s* grp_reg_int_s_fu_3821;
reg_int_s* grp_reg_int_s_fu_3829;
reg_int_s* grp_reg_int_s_fu_3837;
reg_int_s* grp_reg_int_s_fu_3845;
reg_int_s* grp_reg_int_s_fu_3852;
reg_int_s* grp_reg_int_s_fu_3859;
reg_int_s* grp_reg_int_s_fu_3866;
reg_int_s* grp_reg_int_s_fu_3873;
reg_int_s* grp_reg_int_s_fu_3881;
reg_int_s* grp_reg_int_s_fu_3889;
reg_int_s* grp_reg_int_s_fu_3896;
reg_int_s* grp_reg_int_s_fu_3903;
reg_int_s* grp_reg_int_s_fu_3910;
reg_int_s* grp_reg_int_s_fu_3917;
reg_int_s* grp_reg_int_s_fu_3925;
reg_int_s* grp_reg_int_s_fu_3933;
reg_int_s* grp_reg_int_s_fu_3941;
reg_int_s* grp_reg_int_s_fu_3949;
reg_int_s* grp_reg_int_s_fu_3957;
reg_int_s* grp_reg_int_s_fu_3965;
reg_int_s* grp_reg_int_s_fu_3973;
reg_int_s* grp_reg_int_s_fu_3981;
reg_int_s* grp_reg_int_s_fu_3989;
reg_int_s* grp_reg_int_s_fu_3997;
reg_int_s* grp_reg_int_s_fu_4005;
reg_int_s* grp_reg_int_s_fu_4013;
reg_int_s* grp_reg_int_s_fu_4021;
reg_int_s* grp_reg_int_s_fu_4029;
reg_int_s* grp_reg_int_s_fu_4037;
reg_int_s* grp_reg_int_s_fu_4045;
reg_int_s* grp_reg_int_s_fu_4053;
reg_int_s* grp_reg_int_s_fu_4061;
reg_int_s* grp_reg_int_s_fu_4068;
reg_int_s* grp_reg_int_s_fu_4075;
reg_int_s* grp_reg_int_s_fu_4082;
sc_signal< sc_logic > real_start;
sc_signal< sc_logic > start_once_reg;
sc_signal< sc_logic > ap_done_reg;
sc_signal< sc_lv<4> > ap_CS_fsm;
sc_signal< sc_logic > ap_CS_fsm_state1;
sc_signal< sc_logic > internal_ap_ready;
sc_signal< sc_logic > p_src_data_stream_V_blk_n;
sc_signal< sc_logic > ap_CS_fsm_pp0_stage0;
sc_signal< sc_logic > ap_enable_reg_pp0_iter1;
sc_signal< bool > ap_block_pp0_stage0;
sc_signal< sc_lv<1> > exitcond4_reg_4524;
sc_signal< sc_lv<1> > or_cond_reg_4533;
sc_signal< sc_logic > p_mask_data_stream_V_blk_n;
sc_signal< sc_logic > ap_enable_reg_pp0_iter9;
sc_signal< sc_lv<1> > or_cond4_reg_4595;
sc_signal< sc_lv<1> > or_cond4_reg_4595_pp0_iter8_reg;
sc_signal< sc_lv<11> > t_V_3_reg_553;
sc_signal< sc_lv<1> > exitcond3_fu_1315_p2;
sc_signal< sc_logic > ap_CS_fsm_state2;
sc_signal< sc_lv<10> > i_V_fu_1321_p2;
sc_signal< sc_lv<10> > i_V_reg_4500;
sc_signal< sc_lv<1> > tmp_s_fu_1327_p2;
sc_signal< sc_lv<1> > tmp_s_reg_4505;
sc_signal< sc_lv<1> > or_cond1_fu_1339_p2;
sc_signal< sc_lv<1> > or_cond1_reg_4510;
sc_signal< sc_lv<1> > tmp_2_fu_1345_p2;
sc_signal< sc_lv<1> > tmp_2_reg_4514;
sc_signal< sc_lv<1> > icmp_fu_1361_p2;
sc_signal< sc_lv<1> > icmp_reg_4519;
sc_signal< sc_lv<1> > exitcond4_fu_1367_p2;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0;
sc_signal< bool > ap_predicate_op181_read_state4;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9;
sc_signal< bool > ap_block_pp0_stage0_11001;
sc_signal< sc_lv<1> > exitcond4_reg_4524_pp0_iter1_reg;
sc_signal< sc_lv<1> > exitcond4_reg_4524_pp0_iter2_reg;
sc_signal< sc_lv<1> > exitcond4_reg_4524_pp0_iter3_reg;
sc_signal< sc_lv<1> > exitcond4_reg_4524_pp0_iter4_reg;
sc_signal< sc_lv<1> > exitcond4_reg_4524_pp0_iter5_reg;
sc_signal< sc_lv<1> > exitcond4_reg_4524_pp0_iter6_reg;
sc_signal< sc_lv<1> > exitcond4_reg_4524_pp0_iter7_reg;
sc_signal< sc_lv<1> > exitcond4_reg_4524_pp0_iter8_reg;
sc_signal< sc_lv<11> > j_V_fu_1373_p2;
sc_signal< sc_logic > ap_enable_reg_pp0_iter0;
sc_signal< sc_lv<1> > or_cond_fu_1393_p2;
sc_signal< sc_lv<1> > or_cond_reg_4533_pp0_iter1_reg;
sc_signal< sc_lv<1> > or_cond_reg_4533_pp0_iter2_reg;
sc_signal< sc_lv<1> > or_cond_reg_4533_pp0_iter3_reg;
sc_signal< sc_lv<1> > or_cond_reg_4533_pp0_iter4_reg;
sc_signal< sc_lv<1> > or_cond_reg_4533_pp0_iter5_reg;
sc_signal< sc_lv<1> > or_cond_reg_4533_pp0_iter6_reg;
sc_signal< sc_lv<1> > or_cond_reg_4533_pp0_iter7_reg;
sc_signal< sc_lv<1> > or_cond_reg_4533_pp0_iter8_reg;
sc_signal< sc_lv<10> > k_buf_val_0_V_addr_reg_4538;
sc_signal< sc_lv<10> > k_buf_val_1_V_addr_reg_4544;
sc_signal< sc_lv<10> > k_buf_val_2_V_addr_reg_4550;
sc_signal< sc_lv<10> > k_buf_val_3_V_addr_reg_4556;
sc_signal< sc_lv<10> > k_buf_val_4_V_addr_reg_4562;
sc_signal< sc_lv<10> > k_buf_val_5_V_addr_reg_4568;
sc_signal< sc_lv<11> > core_buf_val_0_V_ad_reg_4574;
sc_signal< sc_lv<11> > core_buf_val_1_V_ad_reg_4580;
sc_signal< sc_lv<11> > core_buf_val_1_V_ad_reg_4580_pp0_iter1_reg;
sc_signal< sc_lv<11> > core_buf_val_1_V_ad_reg_4580_pp0_iter2_reg;
sc_signal< sc_lv<11> > core_buf_val_1_V_ad_reg_4580_pp0_iter3_reg;
sc_signal< sc_lv<11> > core_buf_val_1_V_ad_reg_4580_pp0_iter4_reg;
sc_signal< sc_lv<11> > core_buf_val_1_V_ad_reg_4580_pp0_iter5_reg;
sc_signal< sc_lv<11> > core_buf_val_1_V_ad_reg_4580_pp0_iter6_reg;
sc_signal< sc_lv<11> > core_buf_val_1_V_ad_reg_4580_pp0_iter7_reg;
sc_signal< sc_lv<11> > core_buf_val_1_V_ad_reg_4580_pp0_iter8_reg;
sc_signal< sc_lv<1> > tmp_8_fu_1420_p2;
sc_signal< sc_lv<1> > tmp_8_reg_4586;
sc_signal< sc_lv<1> > tmp_8_reg_4586_pp0_iter1_reg;
sc_signal< sc_lv<1> > tmp_8_reg_4586_pp0_iter2_reg;
sc_signal< sc_lv<1> > tmp_8_reg_4586_pp0_iter3_reg;
sc_signal< sc_lv<1> > tmp_8_reg_4586_pp0_iter4_reg;
sc_signal< sc_lv<1> > tmp_8_reg_4586_pp0_iter5_reg;
sc_signal< sc_lv<1> > tmp_8_reg_4586_pp0_iter6_reg;
sc_signal< sc_lv<1> > tmp_8_reg_4586_pp0_iter7_reg;
sc_signal< sc_lv<1> > tmp_8_reg_4586_pp0_iter8_reg;
sc_signal< sc_lv<1> > tmp_12_fu_1426_p2;
sc_signal< sc_lv<1> > tmp_12_reg_4590;
sc_signal< sc_lv<1> > or_cond4_fu_1448_p2;
sc_signal< sc_lv<1> > or_cond4_reg_4595_pp0_iter1_reg;
sc_signal< sc_lv<1> > or_cond4_reg_4595_pp0_iter2_reg;
sc_signal< sc_lv<1> > or_cond4_reg_4595_pp0_iter3_reg;
sc_signal< sc_lv<1> > or_cond4_reg_4595_pp0_iter4_reg;
sc_signal< sc_lv<1> > or_cond4_reg_4595_pp0_iter5_reg;
sc_signal< sc_lv<1> > or_cond4_reg_4595_pp0_iter6_reg;
sc_signal< sc_lv<1> > or_cond4_reg_4595_pp0_iter7_reg;
sc_signal< sc_lv<16> > core_win_val_1_V_1_1_reg_4599;
sc_signal< sc_lv<16> > core_win_val_1_V_1_1_reg_4599_pp0_iter2_reg;
sc_signal< sc_lv<16> > core_win_val_1_V_1_1_reg_4599_pp0_iter3_reg;
sc_signal< sc_lv<16> > core_win_val_1_V_1_1_reg_4599_pp0_iter4_reg;
sc_signal< sc_lv<16> > core_win_val_1_V_1_1_reg_4599_pp0_iter5_reg;
sc_signal< sc_lv<16> > core_win_val_1_V_1_1_reg_4599_pp0_iter6_reg;
sc_signal< sc_lv<16> > core_win_val_1_V_1_1_reg_4599_pp0_iter7_reg;
sc_signal< sc_lv<16> > core_win_val_1_V_1_1_reg_4599_pp0_iter8_reg;
sc_signal< sc_lv<1> > tmp_115_2_fu_1806_p2;
sc_signal< sc_lv<1> > tmp_115_2_reg_4606;
sc_signal< sc_lv<1> > tmp_115_2_reg_4606_pp0_iter2_reg;
sc_signal< sc_lv<1> > tmp_115_2_reg_4606_pp0_iter3_reg;
sc_signal< sc_lv<1> > tmp_115_2_reg_4606_pp0_iter4_reg;
sc_signal< sc_lv<1> > tmp_115_2_reg_4606_pp0_iter5_reg;
sc_signal< sc_lv<1> > tmp_115_2_reg_4606_pp0_iter6_reg;
sc_signal< sc_lv<1> > tmp_115_2_reg_4606_pp0_iter7_reg;
sc_signal< sc_lv<1> > tmp_115_2_reg_4606_pp0_iter8_reg;
sc_signal< sc_lv<1> > tmp_13_fu_1812_p2;
sc_signal< sc_lv<1> > tmp_13_reg_4611;
sc_signal< sc_lv<1> > tmp_13_reg_4611_pp0_iter2_reg;
sc_signal< sc_lv<1> > tmp_13_reg_4611_pp0_iter3_reg;
sc_signal< sc_lv<1> > tmp_13_reg_4611_pp0_iter4_reg;
sc_signal< sc_lv<1> > tmp_13_reg_4611_pp0_iter5_reg;
sc_signal< sc_lv<1> > tmp_13_reg_4611_pp0_iter6_reg;
sc_signal< sc_lv<1> > tmp_13_reg_4611_pp0_iter7_reg;
sc_signal< sc_lv<1> > tmp_13_reg_4611_pp0_iter8_reg;
sc_signal< sc_lv<1> > tmp_14_fu_1818_p2;
sc_signal< sc_lv<1> > tmp_14_reg_4616;
sc_signal< sc_lv<1> > tmp_14_reg_4616_pp0_iter2_reg;
sc_signal< sc_lv<1> > tmp_14_reg_4616_pp0_iter3_reg;
sc_signal< sc_lv<1> > tmp_14_reg_4616_pp0_iter4_reg;
sc_signal< sc_lv<1> > tmp_14_reg_4616_pp0_iter5_reg;
sc_signal< sc_lv<1> > tmp_14_reg_4616_pp0_iter6_reg;
sc_signal< sc_lv<1> > tmp_14_reg_4616_pp0_iter7_reg;
sc_signal< sc_lv<1> > tmp_14_reg_4616_pp0_iter8_reg;
sc_signal< sc_lv<1> > tmp20_fu_1840_p2;
sc_signal< sc_lv<1> > tmp20_reg_4621;
sc_signal< sc_lv<1> > tmp20_reg_4621_pp0_iter2_reg;
sc_signal< sc_lv<1> > tmp20_reg_4621_pp0_iter3_reg;
sc_signal< sc_lv<1> > tmp20_reg_4621_pp0_iter4_reg;
sc_signal< sc_lv<1> > tmp20_reg_4621_pp0_iter5_reg;
sc_signal< sc_lv<1> > tmp20_reg_4621_pp0_iter6_reg;
sc_signal< sc_lv<1> > tmp20_reg_4621_pp0_iter7_reg;
sc_signal< sc_lv<1> > tmp20_reg_4621_pp0_iter8_reg;
sc_signal< sc_lv<9> > ret_V_fu_1931_p2;
sc_signal< sc_lv<9> > ret_V_reg_4626;
sc_signal< sc_lv<9> > ret_V_reg_4626_pp0_iter3_reg;
sc_signal< sc_lv<9> > ret_V_1_fu_1941_p2;
sc_signal< sc_lv<9> > ret_V_1_reg_4631;
sc_signal< sc_lv<9> > ret_V_s_fu_2019_p2;
sc_signal< sc_lv<9> > ret_V_s_reg_4636;
sc_signal< sc_lv<9> > ret_V_1_1_fu_2029_p2;
sc_signal< sc_lv<9> > ret_V_1_1_reg_4641;
sc_signal< sc_lv<9> > ret_V_2_fu_2107_p2;
sc_signal< sc_lv<9> > ret_V_2_reg_4646;
sc_signal< sc_lv<9> > ret_V_1_2_fu_2117_p2;
sc_signal< sc_lv<9> > ret_V_1_2_reg_4651;
sc_signal< sc_lv<9> > ret_V_3_fu_2195_p2;
sc_signal< sc_lv<9> > ret_V_3_reg_4656;
sc_signal< sc_lv<9> > ret_V_1_3_fu_2205_p2;
sc_signal< sc_lv<9> > ret_V_1_3_reg_4661;
sc_signal< sc_lv<9> > ret_V_4_fu_2283_p2;
sc_signal< sc_lv<9> > ret_V_4_reg_4666;
sc_signal< sc_lv<9> > ret_V_1_4_fu_2293_p2;
sc_signal< sc_lv<9> > ret_V_1_4_reg_4671;
sc_signal< sc_lv<9> > ret_V_5_fu_2371_p2;
sc_signal< sc_lv<9> > ret_V_5_reg_4676;
sc_signal< sc_lv<9> > ret_V_1_5_fu_2381_p2;
sc_signal< sc_lv<9> > ret_V_1_5_reg_4681;
sc_signal< sc_lv<9> > ret_V_1_5_reg_4681_pp0_iter3_reg;
sc_signal< sc_lv<9> > ret_V_6_fu_2459_p2;
sc_signal< sc_lv<9> > ret_V_6_reg_4686;
sc_signal< sc_lv<9> > ret_V_1_6_fu_2469_p2;
sc_signal< sc_lv<9> > ret_V_1_6_reg_4691;
sc_signal< sc_lv<9> > ret_V_1_6_reg_4691_pp0_iter3_reg;
sc_signal< sc_lv<9> > ret_V_7_fu_2547_p2;
sc_signal< sc_lv<9> > ret_V_7_reg_4696;
sc_signal< sc_lv<9> > ret_V_1_7_fu_2557_p2;
sc_signal< sc_lv<9> > ret_V_1_7_reg_4701;
sc_signal< sc_lv<9> > ret_V_1_7_reg_4701_pp0_iter3_reg;
sc_signal< sc_lv<1> > or_cond5_fu_2643_p2;
sc_signal< sc_lv<1> > or_cond5_reg_4706;
sc_signal< sc_lv<1> > tmp_69_1_not_fu_2649_p2;
sc_signal< sc_lv<1> > tmp_69_1_not_reg_4712;
sc_signal< sc_lv<1> > tmp_71_1_fu_2655_p2;
sc_signal< sc_lv<1> > tmp_71_1_reg_4717;
sc_signal< sc_lv<1> > or_cond6_fu_2661_p2;
sc_signal< sc_lv<1> > or_cond6_reg_4722;
sc_signal< sc_lv<1> > tmp_69_2_not_fu_2667_p2;
sc_signal< sc_lv<1> > tmp_69_2_not_reg_4727;
sc_signal< sc_lv<1> > tmp_71_2_fu_2673_p2;
sc_signal< sc_lv<1> > tmp_71_2_reg_4732;
sc_signal< sc_lv<1> > or_cond7_fu_2679_p2;
sc_signal< sc_lv<1> > or_cond7_reg_4737;
sc_signal< sc_lv<1> > tmp_69_3_not_fu_2685_p2;
sc_signal< sc_lv<1> > tmp_69_3_not_reg_4742;
sc_signal< sc_lv<1> > tmp_71_3_fu_2691_p2;
sc_signal< sc_lv<1> > tmp_71_3_reg_4747;
sc_signal< sc_lv<1> > or_cond8_fu_2697_p2;
sc_signal< sc_lv<1> > or_cond8_reg_4752;
sc_signal< sc_lv<1> > tmp_69_4_not_fu_2703_p2;
sc_signal< sc_lv<1> > tmp_69_4_not_reg_4757;
sc_signal< sc_lv<1> > tmp_71_4_fu_2709_p2;
sc_signal< sc_lv<1> > tmp_71_4_reg_4762;
sc_signal< sc_lv<1> > or_cond9_fu_2715_p2;
sc_signal< sc_lv<1> > or_cond9_reg_4767;
sc_signal< sc_lv<1> > tmp_69_5_not_fu_2721_p2;
sc_signal< sc_lv<1> > tmp_69_5_not_reg_4772;
sc_signal< sc_lv<1> > tmp_71_5_fu_2727_p2;
sc_signal< sc_lv<1> > tmp_71_5_reg_4777;
sc_signal< sc_lv<1> > or_cond2_fu_2733_p2;
sc_signal< sc_lv<1> > or_cond2_reg_4782;
sc_signal< sc_lv<1> > not_or_cond_fu_2855_p2;
sc_signal< sc_lv<1> > not_or_cond_reg_4787;
sc_signal< sc_lv<4> > count_1_i_2_fu_3141_p3;
sc_signal< sc_lv<4> > count_1_i_2_reg_4792;
sc_signal< sc_lv<1> > tmp_69_3_fu_3149_p2;
sc_signal< sc_lv<1> > tmp_69_3_reg_4798;
sc_signal< sc_lv<1> > tmp_71_11_fu_3155_p2;
sc_signal< sc_lv<1> > tmp_71_11_reg_4804;
sc_signal< sc_lv<1> > tmp_69_4_fu_3161_p2;
sc_signal< sc_lv<1> > tmp_69_4_reg_4810;
sc_signal< sc_lv<1> > tmp_71_12_fu_3167_p2;
sc_signal< sc_lv<1> > tmp_71_12_reg_4816;
sc_signal< sc_lv<1> > or_cond18_fu_3179_p2;
sc_signal< sc_lv<1> > or_cond18_reg_4822;
sc_signal< sc_lv<1> > not_or_cond11_fu_3191
|
_p2;
sc_signal< sc_lv<1> > not_or_cond11_reg_4828;
sc_signal< sc_lv<1> > tmp6_fu_3209_p2;
sc_signal< sc_lv<1> > tmp6_reg_4834;
sc_signal< sc_lv<1> > tmp10_fu_3215_p2;
sc_signal< sc_lv<1> > tmp10_reg_4839;
sc_signal< sc_lv<32> > flag_d_assign_8_fu_3221_p1;
sc_signal< sc_lv<32> > flag_d_assign_8_reg_4844;
sc_signal< sc_lv<32> > flag_d_assign_8_reg_4844_pp0_iter4_reg;
sc_signal< sc_lv<32> > flag_d_assign_8_reg_4844_pp0_iter5_reg;
sc_signal< sc_lv<32> > flag_d_assign_8_reg_4844_pp0_iter6_reg;
sc_signal< sc_lv<32> > flag_d_assign_1_fu_3226_p1;
sc_signal< sc_lv<32> > flag_d_assign_1_reg_4850;
sc_signal< sc_lv<32> > flag_d_assign_1_reg_4850_pp0_iter4_reg;
sc_signal< sc_lv<32> > flag_d_assign_1_reg_4850_pp0_iter5_reg;
sc_signal< sc_lv<32> > flag_d_assign_1_reg_4850_pp0_iter6_reg;
sc_signal< sc_lv<32> > flag_d_assign_9_fu_3231_p1;
sc_signal< sc_lv<32> > flag_d_assign_9_reg_4856;
sc_signal< sc_lv<32> > flag_d_assign_9_reg_4856_pp0_iter4_reg;
sc_signal< sc_lv<32> > flag_d_assign_9_reg_4856_pp0_iter5_reg;
sc_signal< sc_lv<32> > flag_d_assign_2_fu_3236_p1;
sc_signal< sc_lv<32> > flag_d_assign_2_reg_4862;
sc_signal< sc_lv<32> > flag_d_assign_2_reg_4862_pp0_iter4_reg;
sc_signal< sc_lv<32> > flag_d_assign_2_reg_4862_pp0_iter5_reg;
sc_signal< sc_lv<32> > flag_d_assign_10_fu_3241_p1;
sc_signal< sc_lv<32> > flag_d_assign_10_reg_4868;
sc_signal< sc_lv<32> > flag_d_assign_10_reg_4868_pp0_iter4_reg;
sc_signal< sc_lv<32> > flag_d_assign_10_reg_4868_pp0_iter5_reg;
sc_signal< sc_lv<32> > flag_d_assign_10_reg_4868_pp0_iter6_reg;
sc_signal< sc_lv<32> > flag_d_assign_3_fu_3246_p1;
sc_signal< sc_lv<32> > flag_d_assign_3_reg_4874;
sc_signal< sc_lv<32> > flag_d_assign_3_reg_4874_pp0_iter4_reg;
sc_signal< sc_lv<32> > flag_d_assign_3_reg_4874_pp0_iter5_reg;
sc_signal< sc_lv<32> > flag_d_assign_3_reg_4874_pp0_iter6_reg;
sc_signal< sc_lv<32> > flag_d_assign_11_fu_3251_p1;
sc_signal< sc_lv<32> > flag_d_assign_11_reg_4880;
sc_signal< sc_lv<32> > flag_d_assign_11_reg_4880_pp0_iter4_reg;
sc_signal< sc_lv<32> > flag_d_assign_11_reg_4880_pp0_iter5_reg;
sc_signal< sc_lv<32> > flag_d_assign_4_fu_3256_p1;
sc_signal< sc_lv<32> > flag_d_assign_4_reg_4886;
sc_signal< sc_lv<32> > flag_d_assign_4_reg_4886_pp0_iter4_reg;
sc_signal< sc_lv<32> > flag_d_assign_4_reg_4886_pp0_iter5_reg;
sc_signal< sc_lv<32> > flag_d_assign_12_fu_3261_p1;
sc_signal< sc_lv<32> > flag_d_assign_12_reg_4892;
sc_signal< sc_lv<32> > flag_d_assign_12_reg_4892_pp0_iter4_reg;
sc_signal< sc_lv<32> > flag_d_assign_12_reg_4892_pp0_iter5_reg;
sc_signal< sc_lv<32> > flag_d_assign_12_reg_4892_pp0_iter6_reg;
sc_signal< sc_lv<32> > flag_d_assign_12_reg_4892_pp0_iter7_reg;
sc_signal< sc_lv<32> > flag_d_assign_5_fu_3266_p1;
sc_signal< sc_lv<32> > flag_d_assign_5_reg_4898;
sc_signal< sc_lv<32> > flag_d_assign_5_reg_4898_pp0_iter4_reg;
sc_signal< sc_lv<32> > flag_d_assign_5_reg_4898_pp0_iter5_reg;
sc_signal< sc_lv<32> > flag_d_assign_5_reg_4898_pp0_iter6_reg;
sc_signal< sc_lv<32> > flag_d_assign_5_reg_4898_pp0_iter7_reg;
sc_signal< sc_lv<32> > flag_d_assign_6_fu_3271_p1;
sc_signal< sc_lv<32> > flag_d_assign_6_reg_4904;
sc_signal< sc_lv<32> > flag_d_assign_6_reg_4904_pp0_iter4_reg;
sc_signal< sc_lv<32> > flag_d_assign_6_reg_4904_pp0_iter5_reg;
sc_signal< sc_lv<32> > flag_d_assign_6_reg_4904_pp0_iter6_reg;
sc_signal< sc_lv<32> > flag_d_assign_7_fu_3276_p1;
sc_signal< sc_lv<32> > flag_d_assign_7_reg_4910;
sc_signal< sc_lv<32> > flag_d_assign_7_reg_4910_pp0_iter4_reg;
sc_signal< sc_lv<32> > flag_d_assign_7_reg_4910_pp0_iter5_reg;
sc_signal< sc_lv<32> > flag_d_assign_7_reg_4910_pp0_iter6_reg;
sc_signal< sc_lv<32> > flag_d_assign_7_reg_4910_pp0_iter7_reg;
sc_signal< sc_lv<1> > iscorner_2_i_s_fu_3695_p2;
sc_signal< sc_lv<1> > iscorner_2_i_s_reg_4916;
sc_signal< sc_lv<1> > iscorner_2_i_s_reg_4916_pp0_iter4_reg;
sc_signal< sc_lv<1> > iscorner_2_i_s_reg_4916_pp0_iter5_reg;
sc_signal< sc_lv<1> > iscorner_2_i_s_reg_4916_pp0_iter6_reg;
sc_signal< sc_lv<1> > iscorner_2_i_s_reg_4916_pp0_iter7_reg;
sc_signal< sc_lv<1> > iscorner_2_i_s_reg_4916_pp0_iter8_reg;
sc_signal< sc_lv<32> > flag_d_assign_s_fu_3793_p1;
sc_signal< sc_lv<32> > flag_d_assign_s_reg_4920;
sc_signal< sc_lv<32> > flag_d_assign_s_reg_4920_pp0_iter5_reg;
sc_signal< sc_lv<32> > flag_d_assign_13_fu_3798_p1;
sc_signal< sc_lv<32> > flag_d_assign_13_reg_4926;
sc_signal< sc_lv<32> > flag_d_assign_13_reg_4926_pp0_iter5_reg;
sc_signal< sc_lv<32> > flag_d_assign_14_fu_3803_p1;
sc_signal< sc_lv<32> > flag_d_assign_14_reg_4932;
sc_signal< sc_lv<32> > flag_d_assign_14_reg_4932_pp0_iter5_reg;
sc_signal< sc_lv<32> > flag_d_assign_14_reg_4932_pp0_iter6_reg;
sc_signal< sc_lv<32> > flag_d_assign_14_reg_4932_pp0_iter7_reg;
sc_signal< sc_lv<32> > flag_d_assign_15_fu_3808_p1;
sc_signal< sc_lv<32> > flag_d_assign_15_reg_4938;
sc_signal< sc_lv<32> > flag_d_assign_15_reg_4938_pp0_iter5_reg;
sc_signal< sc_lv<32> > flag_d_assign_15_reg_4938_pp0_iter6_reg;
sc_signal< sc_lv<32> > grp_reg_int_s_fu_3701_ap_return;
sc_signal< sc_lv<32> > flag_d_min2_1_reg_4944;
sc_signal< sc_lv<32> > grp_reg_int_s_fu_3708_ap_return;
sc_signal< sc_lv<32> > flag_d_max2_1_reg_4949;
sc_signal< sc_lv<32> > grp_reg_int_s_fu_3779_ap_return;
sc_signal< sc_lv<32> > flag_d_min2_11_reg_4954;
sc_signal< sc_lv<32> > grp_reg_int_s_fu_3786_ap_return;
sc_signal< sc_lv<32> > flag_d_max2_11_reg_4959;
sc_signal< sc_lv<32> > grp_reg_int_s_fu_3845_ap_return;
sc_signal< sc_lv<32> > flag_d_min4_1_reg_4964;
sc_signal< sc_lv<32> > grp_reg_int_s_fu_3852_ap_return;
sc_signal< sc_lv<32> > flag_d_max4_1_reg_4969;
sc_signal< sc_lv<32> > grp_reg_int_s_fu_3859_ap_return;
sc_signal< sc_lv<32> > flag_d_min4_3_reg_4974;
sc_signal< sc_lv<32> > grp_reg_int_s_fu_3866_ap_return;
sc_signal< sc_lv<32> > flag_d_max4_3_reg_4979;
sc_signal< sc_lv<32> > grp_reg_int_s_fu_3889_ap_return;
sc_signal< sc_lv<32> > flag_d_min4_7_reg_4984;
sc_signal< sc_lv<32> > grp_reg_int_s_fu_3896_ap_return;
sc_signal< sc_lv<32> > flag_d_max4_7_reg_4989;
sc_signal< sc_lv<32> > grp_reg_int_s_fu_3903_ap_return;
sc_signal< sc_lv<32> > flag_d_min4_9_reg_4994;
sc_signal< sc_lv<32> > grp_reg_int_s_fu_3910_ap_return;
sc_signal< sc_lv<32> > flag_d_max4_9_reg_4999;
sc_signal< sc_lv<32> > tmp_90_2_min_int_s_fu_713_ap_return;
sc_signal< sc_lv<32> > tmp_90_2_reg_5004;
sc_signal< sc_lv<32> > tmp_92_2_max_int_s_fu_1063_ap_return;
sc_signal< sc_lv<32> > tmp_92_2_reg_5009;
sc_signal< sc_lv<32> > tmp_90_4_min_int_s_fu_719_ap_return;
sc_signal< sc_lv<32> > tmp_90_4_reg_5014;
sc_signal< sc_lv<32> > tmp_92_4_max_int_s_fu_1069_ap_return;
sc_signal< sc_lv<32> > tmp_92_4_reg_5019;
sc_signal< sc_lv<32> > a0_2_max_int_s_fu_1107_ap_return;
sc_signal< sc_lv<32> > a0_2_reg_5024;
sc_signal< sc_lv<32> > tmp_101_2_min_int_s_fu_755_ap_return;
sc_signal< sc_lv<32> > tmp_101_2_reg_5029;
sc_signal< sc_lv<32> > b0_2_min_int_s_fu_789_ap_return;
sc_signal< sc_lv<32> > b0_2_reg_5034;
sc_signal< sc_lv<32> > tmp_109_2_max_int_s_fu_1150_ap_return;
sc_signal< sc_lv<32> > tmp_109_2_reg_5039;
sc_signal< sc_lv<32> > a0_5_max_int_s_fu_1194_ap_return;
sc_signal< sc_lv<32> > a0_5_reg_5044;
sc_signal< sc_lv<32> > tmp_101_5_min_int_s_fu_826_ap_return;
sc_signal< sc_lv<32> > tmp_101_5_reg_5049;
sc_signal< sc_lv<32> > b0_5_min_int_s_fu_866_ap_return;
sc_signal< sc_lv<32> > b0_5_reg_5054;
sc_signal< sc_lv<32> > tmp_109_5_max_int_s_fu_1237_ap_return;
sc_signal< sc_lv<32> > tmp_109_5_reg_5059;
sc_signal< sc_lv<32> > a0_1_7_max_int_s_fu_1273_ap_return;
sc_signal< sc_lv<32> > a0_1_7_reg_5064;
sc_signal< sc_lv<32> > b0_1_7_min_int_s_fu_924_ap_return;
sc_signal< sc_lv<32> > b0_1_7_reg_5069;
sc_signal< bool > ap_block_pp0_stage0_subdone;
sc_signal< sc_logic > ap_enable_reg_pp0_iter2;
sc_signal< sc_logic > ap_condition_pp0_exit_iter1_state4;
sc_signal< sc_logic > ap_enable_reg_pp0_iter3;
sc_signal< sc_logic > ap_enable_reg_pp0_iter4;
sc_signal< sc_logic > ap_enable_reg_pp0_iter5;
sc_signal< sc_logic > ap_enable_reg_pp0_iter6;
sc_signal< sc_logic > ap_enable_reg_pp0_iter7;
sc_signal< sc_logic > ap_enable_reg_pp0_iter8;
sc_signal< sc_lv<10> > k_buf_val_0_V_address0;
sc_signal< sc_logic > k_buf_val_0_V_ce0;
sc_signal< sc_lv<8> > k_buf_val_0_V_q0;
sc_signal< sc_logic > k_buf_val_0_V_ce1;
sc_signal< sc_logic > k_buf_val_0_V_we1;
sc_signal< sc_lv<10> > k_buf_val_1_V_address0;
sc_signal< sc_logic > k_buf_val_1_V_ce0;
sc_signal< sc_lv<8> > k_buf_val_1_V_q0;
sc_signal< sc_logic > k_buf_val_1_V_ce1;
sc_signal< sc_logic > k_buf_val_1_V_we1;
sc_signal< sc_lv<10> > k_buf_val_2_V_address0;
sc_signal< sc_logic > k_buf_val_2_V_ce0;
sc_signal< sc_lv<8> > k_buf_val_2_V_q0;
sc_signal< sc_logic > k_buf_val_2_V_ce1;
sc_signal< sc_logic > k_buf_val_2_V_we1;
sc_signal< sc_lv<10> > k_buf_val_3_V_address0;
sc_signal< sc_logic > k_buf_val_3_V_ce0;
sc_signal< sc_lv<8> > k_buf_val_3_V_q0;
sc_signal< sc_logic > k_buf_val_3_V_ce1;
sc_signal< sc_logic > k_buf_val_3_V_we1;
sc_signal< sc_lv<10> > k_buf_val_4_V_address0;
sc_signal< sc_logic > k_buf_val_4_V_ce0;
sc_signal< sc_lv<8> > k_buf_val_4_V_q0;
sc_signal< sc_logic > k_buf_val_4_V_ce1;
sc_signal< sc_logic > k_buf_val_4_V_we1;
sc_signal< sc_lv<10> > k_buf_val_5_V_address0;
sc_signal< sc_logic > k_buf_val_5_V_ce0;
sc_signal< sc_lv<8> > k_buf_val_5_V_q0;
sc_signal< sc_logic > k_buf_val_5_V_ce1;
sc_signal< sc_logic > k_buf_val_5_V_we1;
sc_signal< sc_lv<11> > core_buf_val_0_V_address0;
sc_signal< sc_logic > core_buf_val_0_V_ce0;
sc_signal< sc_lv<16> > core_buf_val_0_V_q0;
sc_signal< sc_logic > core_buf_val_0_V_ce1;
sc_signal< sc_logic > core_buf_val_0_V_we1;
sc_signal< sc_lv<11> > core_buf_val_1_V_address0;
sc_signal< sc_logic > core_buf_val_1_V_ce0;
sc_signal< sc_lv<16> > core_buf_val_1_V_q0;
sc_signal< sc_logic > core_buf_val_1_V_ce1;
sc_signal< sc_logic > core_buf_val_1_V_we1;
sc_signal< sc_logic > tmp_76_1_min_int_s_fu_581_ap_ready;
sc_signal< sc_lv<32> > tmp_76_1_min_int_s_fu_581_ap_return;
sc_signal< sc_logic > tmp_76_3_min_int_s_fu_587_ap_ready;
sc_signal< sc_lv<32> > tmp_76_3_min_int_s_fu_587_ap_return;
sc_signal< sc_logic > tmp_76_5_min_int_s_fu_593_ap_ready;
sc_signal< sc_lv<32> > tmp_76_5_min_int_s_fu_593_ap_return;
sc_signal< sc_logic > tmp_76_7_min_int_s_fu_599_ap_ready;
sc_signal< sc_lv<32> > tmp_76_7_min_int_s_fu_599_ap_return;
sc_signal< sc_logic > tmp_76_9_min_int_s_fu_605_ap_ready;
sc_signal< sc_lv<32> > tmp_76_9_min_int_s_fu_605_ap_return;
sc_signal< sc_logic > tmp_76_s_min_int_s_fu_611_ap_ready;
sc_signal< sc_lv<32> > tmp_76_s_min_int_s_fu_611_ap_return;
sc_signal< sc_logic > tmp_76_2_min_int_s_fu_617_ap_ready;
sc_signal< sc_lv<32> > tmp_76_2_min_int_s_fu_617_ap_return;
sc_signal< sc_logic > tmp_76_4_min_int_s_fu_623_ap_ready;
sc_signal< sc_lv<32> > tmp_76_4_min_int_s_fu_623_ap_return;
sc_signal< sc_logic > tmp_83_1_min_int_s_fu_629_ap_ready;
sc_signal< sc_lv<32> > tmp_83_1_min_int_s_fu_629_ap_return;
sc_signal< sc_logic > tmp_83_3_min_int_s_fu_635_ap_ready;
sc_signal< sc_lv<32> > tmp_83_3_min_int_s_fu_635_ap_return;
sc_signal< sc_logic > tmp_83_5_min_int_s_fu_641_ap_ready;
sc_signal< sc_lv<32> > tmp_83_5_min_int_s_fu_641_ap_return;
sc_signal< sc_logic > tmp_83_7_min_int_s_fu_647_ap_ready;
sc_signal< sc_lv<32> > tmp_83_7_min_int_s_fu_647_ap_return;
sc_signal< sc_logic > tmp_83_9_min_int_s_fu_653_ap_ready;
sc_signal< sc_lv<32> > tmp_83_9_min_int_s_fu_653_ap_return;
sc_signal< sc_logic > tmp_83_s_min_int_s_fu_659_ap_ready;
sc_signal< sc_lv<32> > tmp_83_s_min_int_s_fu_659_ap_return;
sc_signal< sc_logic > tmp_83_2_min_int_s_fu_665_ap_ready;
sc_signal< sc_lv<32> > tmp_83_2_min_int_s_fu_665_ap_return;
sc_signal< sc_logic > tmp_83_4_min_int_s_fu_671_ap_ready;
sc_signal< sc_lv<32> > tmp_83_4_min_int_s_fu_671_ap_return;
sc_signal< sc_logic > tmp_90_1_min_int_s_fu_677_ap_ready;
sc_signal< sc_lv<32> > tmp_90_1_min_int_s_fu_677_ap_return;
sc_signal< sc_logic > tmp_90_3_min_int_s_fu_683_ap_ready;
sc_signal< sc_lv<32> > tmp_90_3_min_int_s_fu_683_ap_return;
sc_signal< sc_logic > tmp_90_5_min_int_s_fu_689_ap_ready;
sc_signal< sc_lv<32> > tmp_90_5_min_int_s_fu_689_ap_return;
sc_signal< sc_logic > tmp_90_7_min_int_s_fu_695_ap_ready;
sc_signal< sc_lv<32> > tmp_90_7_min_int_s_fu_695_ap_return;
sc_signal< sc_logic > tmp_90_9_min_int_s_fu_701_ap_ready;
sc_signal< sc_lv<32> > tmp_90_9_min_int_s_fu_701_ap_return;
sc_signal< sc_logic > tmp_90_s_min_int_s_fu_707_ap_ready;
sc_signal< sc_lv<32> > tmp_90_s_min_int_s_fu_707_ap_return;
sc_signal< sc_logic > tmp_90_2_min_int_s_fu_713_ap_ready;
sc_signal< sc_logic > tmp_90_4_min_int_s_fu_719_ap_ready;
sc_signal< sc_logic > tmp_27_min_int_s_fu_725_ap_ready;
sc_signal< sc_lv<32> > tmp_27_min_int_s_fu_725_ap_return;
sc_signal< sc_logic > tmp_29_min_int_s_fu_731_ap_ready;
sc_signal< sc_lv<32> > tmp_29_min_int_s_fu_731_ap_return;
sc_signal< sc_logic > tmp_98_1_min_int_s_fu_737_ap_ready;
sc_signal< sc_lv<32> > tmp_98_1_min_int_s_fu_737_ap_return;
sc_signal< sc_logic > tmp_101_1_min_int_s_fu_743_ap_ready;
sc_signal< sc_lv<32> > tmp_101_1_min_int_s_fu_743_ap_return;
sc_signal< sc_logic > tmp_98_2_min_int_s_fu_749_ap_ready;
sc_signal< sc_lv<32> > tmp_98_2_min_int_s_fu_749_ap_return;
sc_signal< sc_logic > tmp_101_2_min_int_s_fu_755_ap_ready;
sc_signal< sc_logic > b0_min_int_s_fu_761_ap_ready;
sc_signal< sc_lv<32> > b0_min_int_s_fu_761_ap_return;
sc_signal< sc_logic > b0_1_min_int_s_fu_768_ap_ready;
sc_signal< sc_lv<32> > b0_1_min_int_s_fu_768_ap_return;
sc_signal< sc_logic > b0_s_min_int_s_fu_775_ap_ready;
sc_signal< sc_lv<32> > b0_s_min_int_s_fu_775_ap_return;
sc_signal< sc_logic > b0_1_1_min_int_s_fu_782_ap_ready;
sc_signal< sc_lv<32> > b0_1_1_min_int_s_fu_782_ap_return;
sc_signal< sc_logic > b0_2_min_int_s_fu_789_ap_ready;
sc_signal< sc_logic > tmp_98_3_min_int_s_fu_796_ap_ready;
sc_signal< sc_lv<32> > tmp_98_3_min_int_s_fu_796_ap_return;
sc_signal< sc_logic > tmp_101_3_min_int_s_fu_802_ap_ready;
sc_signal< sc_lv<32> > tmp_101_3_min_int_s_fu_802_ap_return;
sc_signal< sc_logic > tmp_98_4_min_int_s_fu_808_ap_ready;
sc_signal< sc_lv<32> > tmp_98_4_min_int_s_fu_808_ap_return;
sc_signal< sc_logic > tmp_101_4_min_int_s_fu_814_ap_ready;
sc_signal< sc_lv<32> > tmp_101_4_min_int_s_fu_814_ap_return;
sc_signal< sc_logic > tmp_98_5_min_int_s_fu_820_ap_ready;
sc_signal< sc_lv<32> > tmp_98_5_min_int_s_fu_820_ap_return;
sc_signal< sc_logic > tmp_101_5_min_int_s_fu_826_ap_ready;
sc_signal< sc_logic > b0_1_2_min_int_s_fu_832_ap_ready;
sc_signal< sc_lv<32> > b0_1_2_min_int_s_fu_832_ap_return;
sc_signal< sc_logic > b0_3_min_int_s_fu_838_ap_ready;
sc_signal< sc_lv<32> > b0_3_min_int_s_fu_838_ap_return;
sc_signal< sc_logic > b0_1_3_min_int_s_fu_845_ap_ready;
sc_signal< sc_lv<32> > b0_1_3_min_int_s_fu_845_ap_return;
sc_signal< sc_logic > b0_4_min_int_s_fu_852_ap_ready;
sc_signal< sc_lv<32> > b0_4_min_int_s_fu_852_ap_return;
sc_signal< sc_logic > b0_1_4_min_int_s_fu_859_ap_ready;
sc_signal< sc_lv<32> > b0_1_4_min_int_s_fu_859_ap_return;
sc_signal< sc_logic > b0_5_min_int_s_fu_866_ap_ready;
sc_signal< sc_logic > tmp_98_6_min_int_s_fu_873_ap_ready;
sc_signal< sc_lv<32> > tmp_98_6_min_int_s_fu_873_ap_return;
sc_signal< sc_logic > tmp_101_6_min_int_s_fu_879_ap_ready;
sc_signal< sc_lv<32> > tmp_101_6_min_int_s_fu_879_ap_return;
sc_signal< sc_logic > tmp_98_7_min_int_s_fu_885_ap_ready;
sc_signal< sc_lv<32> > tmp_98_7_min_int_s_fu_885_ap_return;
sc_signal< sc_logic > tmp_101_7_min_int_s_fu_891_ap_ready;
sc_signal< sc_lv<32> > tmp_101_7_min_int_s_fu_891_ap_return;
sc_signal< sc_logic > b0_1_5_min_int_s_fu_897_ap_ready;
sc_signal< sc_lv<32> > b0_1_5_min_int_s_fu_897_ap_return;
sc_signal< sc_logic > b0_6_min_int_s_fu_903_ap_ready;
sc_signal< sc_lv<32> > b0_6_min_int_s_fu_903_ap_return;
sc_signal< sc_logic > b0_1_6_min_int_s_fu_910_ap_ready;
sc_signal< sc_lv<32> > b0_1_6_min_int_s_fu_910_ap_return;
sc_signal< sc_logic > b0_7_min_int_s_fu_917_ap_ready;
sc_signal< sc_lv<32> > b0_7_min_int_s_fu_917_ap_return;
sc_signal< sc_logic > b0_1_7_min_int_s_fu_924_ap_ready;
sc_signal< sc_logic > tmp_78_1_max_int_s_fu_931_ap_ready;
sc_signal< sc_lv<32> > tmp_78_1_max_int_s_fu_931_ap_return;
sc_signal< sc_logic > tmp_78_3_max_int_s_fu_937_ap_ready;
sc_signal< sc_lv<32> > tmp_78_3_max_int_s_fu_937_ap_return;
sc_signal< sc_logic > tmp_78_5_max_int_s_fu_943_ap_ready;
sc_signal< sc_lv<32> > tmp_78_5_max_int_s_fu_943_ap_return;
sc_signal< sc_logic > tmp_78_7_max_int_s_fu_949_ap_ready;
sc_signal< sc_lv<32> > tmp_78_7_max_int_s_fu_949_ap_return;
sc_signal< sc_logic > tmp_78_9_max_int_s_fu_955_ap_ready;
sc_signal< sc_lv<32> > tmp_78_9_max_int_s_fu_955_ap_return;
sc_signal< sc_logic > tmp_78_s_max_int_s_fu_961_ap_ready;
sc_signal< sc_lv<32> > tmp_78_s_max_int_s_fu_961_ap_return;
sc_signal< sc_logic > tmp_78_2_max_int_s_fu_967_ap_ready;
sc_signal< sc_lv<32> > tmp_78_2_max_int_s_fu_967_ap_return;
sc_signal< sc_logic > tmp_78_4_max_int_s_fu_973_ap_ready;
sc_signal< sc_lv<32> > tmp_78_4_max_int_s_fu_973_ap_return;
sc_signal< sc_logic > tmp_85_1_max_int_s_fu_979_ap_ready;
sc_signal< sc_lv<32> > tmp_85_1_max_int_s_fu_979_ap_return;
sc_signal< sc_logic > tmp_85_3_max_int_s_fu_985_ap_ready;
sc_signal< sc_lv<32> > tmp_85_3_max_int_s_fu_985_ap_return;
sc_signal< sc_logic > tmp_85_5_max_int_s_fu_991_ap_ready;
sc_signal< sc_lv<32> > tmp_85_5_max_int_s_fu_991_ap_return;
sc_signal< sc_logic > tmp_85_7_max_int_s_fu_997_ap_ready;
sc_signal< sc_lv<32> > tmp_85_7_max_int_s_fu_997_ap_return;
sc_signal< sc_logic > tmp_85_9_max_int_s_fu_1003_ap_ready;
sc_signal< sc_lv<32> > tmp_85_9_max_int_s_fu_1003_ap_return;
sc_signal< sc_logic > tmp_85_s_max_int_s_fu_1009_ap_ready;
sc_signal< sc_lv<32> > tmp_85_s_max_int_s_fu_1009_ap_return;
sc_signal< sc_logic > tmp_85_2_max_int_s_fu_1015_ap_ready;
sc_signal< sc_lv<32> > tmp_85_2_max_int_s_fu_1015_ap_return;
sc_signal< sc_logic > tmp_85_4_max_int_s_fu_1021_ap_ready;
sc_signal< sc_lv<32> > tmp_85_4_max_int_s_fu_1021_ap_return;
sc_signal< sc_logic > tmp_92_1_max_int_s_fu_1027_ap_ready;
sc_signal< sc_lv<32> > tmp_92_1_max_int_s_fu_1027_ap_return;
sc_signal< sc_logic > tmp_92_3_max_int_s_fu_1033_ap_ready;
sc_signal< sc_lv<32> > tmp_92_3_max_int_s_fu_1033_ap_return;
sc_signal< sc_logic > tmp_92_5_max_int_s_fu_1039_ap_ready;
sc_signal< sc_lv<32> > tmp_92_5_max_int_s_fu_1039_ap_return;
sc_signal< sc_logic > tmp_92_7_max_int_s_fu_1045_ap_ready;
sc_signal< sc_lv<32> > tmp_92_7_max_int_s_fu_1045_ap_return;
sc_signal< sc_logic > tmp_92_9_max_int_s_fu_1051_ap_ready;
sc_signal< sc_lv<32> > tmp_92_9_max_int_s_fu_1051_ap_return;
sc_signal< sc_logic > tmp_92_s_max_int_s_fu_1057_ap_ready;
sc_signal< sc_lv<32> > tmp_92_s_max_int_s_fu_1057_ap_return;
sc_signal< sc_logic > tmp_92_2_max_int_s_fu_1063_ap_ready;
sc_signal< sc_logic > tmp_92_4_max_int_s_fu_1069_ap_ready;
sc_signal< sc_logic > a0_max_int_s_fu_1075_ap_ready;
sc_signal< sc_lv<32> > a0_max_int_s_fu_1075_ap_return;
sc_signal< sc_logic > a0_1_max
|
_int_s_fu_1083_ap_ready;
sc_signal< sc_lv<32> > a0_1_max_int_s_fu_1083_ap_return;
sc_signal< sc_logic > a0_s_max_int_s_fu_1091_ap_ready;
sc_signal< sc_lv<32> > a0_s_max_int_s_fu_1091_ap_return;
sc_signal< sc_logic > a0_1_1_max_int_s_fu_1099_ap_ready;
sc_signal< sc_lv<32> > a0_1_1_max_int_s_fu_1099_ap_return;
sc_signal< sc_logic > a0_2_max_int_s_fu_1107_ap_ready;
sc_signal< sc_logic > tmp_30_max_int_s_fu_1115_ap_ready;
sc_signal< sc_lv<32> > tmp_30_max_int_s_fu_1115_ap_return;
sc_signal< sc_logic > tmp_31_max_int_s_fu_1122_ap_ready;
sc_signal< sc_lv<32> > tmp_31_max_int_s_fu_1122_ap_return;
sc_signal< sc_logic > tmp_106_1_max_int_s_fu_1129_ap_ready;
sc_signal< sc_lv<32> > tmp_106_1_max_int_s_fu_1129_ap_return;
sc_signal< sc_logic > tmp_109_1_max_int_s_fu_1136_ap_ready;
sc_signal< sc_lv<32> > tmp_109_1_max_int_s_fu_1136_ap_return;
sc_signal< sc_logic > tmp_106_2_max_int_s_fu_1143_ap_ready;
sc_signal< sc_lv<32> > tmp_106_2_max_int_s_fu_1143_ap_return;
sc_signal< sc_logic > tmp_109_2_max_int_s_fu_1150_ap_ready;
sc_signal< sc_logic > a0_1_2_max_int_s_fu_1156_ap_ready;
sc_signal< sc_lv<32> > a0_1_2_max_int_s_fu_1156_ap_return;
sc_signal< sc_logic > a0_3_max_int_s_fu_1162_ap_ready;
sc_signal< sc_lv<32> > a0_3_max_int_s_fu_1162_ap_return;
sc_signal< sc_logic > a0_1_3_max_int_s_fu_1170_ap_ready;
sc_signal< sc_lv<32> > a0_1_3_max_int_s_fu_1170_ap_return;
sc_signal< sc_logic > a0_4_max_int_s_fu_1178_ap_ready;
sc_signal< sc_lv<32> > a0_4_max_int_s_fu_1178_ap_return;
sc_signal< sc_logic > a0_1_4_max_int_s_fu_1186_ap_ready;
sc_signal< sc_lv<32> > a0_1_4_max_int_s_fu_1186_ap_return;
sc_signal< sc_logic > a0_5_max_int_s_fu_1194_ap_ready;
sc_signal< sc_logic > tmp_106_3_max_int_s_fu_1202_ap_ready;
sc_signal< sc_lv<32> > tmp_106_3_max_int_s_fu_1202_ap_return;
sc_signal< sc_logic > tmp_109_3_max_int_s_fu_1209_ap_ready;
sc_signal< sc_lv<32> > tmp_109_3_max_int_s_fu_1209_ap_return;
sc_signal< sc_logic > tmp_106_4_max_int_s_fu_1216_ap_ready;
sc_signal< sc_lv<32> > tmp_106_4_max_int_s_fu_1216_ap_return;
sc_signal< sc_logic > tmp_109_4_max_int_s_fu_1223_ap_ready;
sc_signal< sc_lv<32> > tmp_109_4_max_int_s_fu_1223_ap_return;
sc_signal< sc_logic > tmp_106_5_max_int_s_fu_1230_ap_ready;
sc_signal< sc_lv<32> > tmp_106_5_max_int_s_fu_1230_ap_return;
sc_signal< sc_logic > tmp_109_5_max_int_s_fu_1237_ap_ready;
sc_signal< sc_logic > a0_1_5_max_int_s_fu_1243_ap_ready;
sc_signal< sc_lv<32> > a0_1_5_max_int_s_fu_1243_ap_return;
sc_signal< sc_logic > a0_6_max_int_s_fu_1249_ap_ready;
sc_signal< sc_lv<32> > a0_6_max_int_s_fu_1249_ap_return;
sc_signal< sc_logic > a0_1_6_max_int_s_fu_1257_ap_ready;
sc_signal< sc_lv<32> > a0_1_6_max_int_s_fu_1257_ap_return;
sc_signal< sc_logic > a0_7_max_int_s_fu_1265_ap_ready;
sc_signal< sc_lv<32> > a0_7_max_int_s_fu_1265_ap_return;
sc_signal< sc_logic > a0_1_7_max_int_s_fu_1273_ap_ready;
sc_signal< sc_logic > tmp_106_6_max_int_s_fu_1281_ap_ready;
sc_signal< sc_lv<32> > tmp_106_6_max_int_s_fu_1281_ap_return;
sc_signal< sc_logic > tmp_109_6_max_int_s_fu_1288_ap_ready;
sc_signal< sc_lv<32> > tmp_109_6_max_int_s_fu_1288_ap_return;
sc_signal< sc_logic > tmp_106_7_max_int_s_fu_1295_ap_ready;
sc_signal< sc_lv<32> > tmp_106_7_max_int_s_fu_1295_ap_return;
sc_signal< sc_logic > tmp_109_7_max_int_s_fu_1302_ap_ready;
sc_signal< sc_lv<32> > tmp_109_7_max_int_s_fu_1302_ap_return;
sc_signal< sc_logic > tmp_10_max_int_s_fu_1309_ap_ready;
sc_signal< sc_lv<32> > tmp_10_max_int_s_fu_1309_y;
sc_signal< sc_lv<32> > tmp_10_max_int_s_fu_1309_ap_return;
sc_signal< sc_logic > grp_reg_int_s_fu_3701_ap_ce;
sc_signal< bool > ap_predicate_op562_call_state6;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0_ignore_call1;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1_ignore_call1;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2_ignore_call1;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3_ignore_call1;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4_ignore_call1;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call1;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call1;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call1;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8_ignore_call1;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call1;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp562;
sc_signal< sc_logic > grp_reg_int_s_fu_3708_ap_ce;
sc_signal< bool > ap_predicate_op564_call_state6;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0_ignore_call3;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1_ignore_call3;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2_ignore_call3;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3_ignore_call3;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4_ignore_call3;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call3;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call3;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call3;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8_ignore_call3;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call3;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp564;
sc_signal< sc_lv<32> > grp_reg_int_s_fu_3715_ap_return;
sc_signal< sc_logic > grp_reg_int_s_fu_3715_ap_ce;
sc_signal< bool > ap_predicate_op566_call_state6;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0_ignore_call5;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1_ignore_call5;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2_ignore_call5;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3_ignore_call5;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4_ignore_call5;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call5;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call5;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call5;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8_ignore_call5;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call5;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp566;
sc_signal< sc_lv<32> > grp_reg_int_s_fu_3723_ap_return;
sc_signal< sc_logic > grp_reg_int_s_fu_3723_ap_ce;
sc_signal< bool > ap_predicate_op568_call_state6;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0_ignore_call7;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1_ignore_call7;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2_ignore_call7;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3_ignore_call7;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4_ignore_call7;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call7;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call7;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call7;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8_ignore_call7;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call7;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp568;
sc_signal< sc_lv<32> > grp_reg_int_s_fu_3731_ap_return;
sc_signal< sc_logic > grp_reg_int_s_fu_3731_ap_ce;
sc_signal< bool > ap_predicate_op570_call_state6;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0_ignore_call9;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1_ignore_call9;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2_ignore_call9;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3_ignore_call9;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4_ignore_call9;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call9;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call9;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call9;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8_ignore_call9;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call9;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp570;
sc_signal< sc_lv<32> > grp_reg_int_s_fu_3739_ap_return;
sc_signal< sc_logic > grp_reg_int_s_fu_3739_ap_ce;
sc_signal< bool > ap_predicate_op572_call_state6;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0_ignore_call11;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1_ignore_call11;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2_ignore_call11;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3_ignore_call11;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4_ignore_call11;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call11;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call11;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call11;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8_ignore_call11;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call11;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp572;
sc_signal< sc_lv<32> > grp_reg_int_s_fu_3747_ap_return;
sc_signal< sc_logic > grp_reg_int_s_fu_3747_ap_ce;
sc_signal< bool > ap_predicate_op574_call_state6;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0_ignore_call13;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1_ignore_call13;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2_ignore_call13;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3_ignore_call13;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4_ignore_call13;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call13;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call13;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call13;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8_ignore_call13;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call13;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp574;
sc_signal< sc_lv<32> > grp_reg_int_s_fu_3755_ap_return;
sc_signal< sc_logic > grp_reg_int_s_fu_3755_ap_ce;
sc_signal< bool > ap_predicate_op576_call_state6;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0_ignore_call15;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1_ignore_call15;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2_ignore_call15;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3_ignore_call15;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4_ignore_call15;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call15;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call15;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call15;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8_ignore_call15;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call15;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp576;
sc_signal< sc_lv<32> > grp_reg_int_s_fu_3763_ap_return;
sc_signal< sc_logic > grp_reg_int_s_fu_3763_ap_ce;
sc_signal< bool > ap_predicate_op578_call_state6;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0_ignore_call17;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1_ignore_call17;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2_ignore_call17;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3_ignore_call17;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4_ignore_call17;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call17;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call17;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call17;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8_ignore_call17;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call17;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp578;
sc_signal< sc_lv<32> > grp_reg_int_s_fu_3771_ap_return;
sc_signal< sc_logic > grp_reg_int_s_fu_3771_ap_ce;
sc_signal< bool > ap_predicate_op580_call_state6;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0_ignore_call19;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1_ignore_call19;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2_ignore_call19;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3_ignore_call19;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4_ignore_call19;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call19;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call19;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call19;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8_ignore_call19;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call19;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp580;
sc_signal< sc_logic > grp_reg_int_s_fu_3779_ap_ce;
sc_signal< bool > ap_predicate_op582_call_state6;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0_ignore_call21;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1_ignore_call21;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2_ignore_call21;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3_ignore_call21;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4_ignore_call21;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call21;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call21;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call21;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8_ignore_call21;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call21;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp582;
sc_signal< sc_logic > grp_reg_int_s_fu_3786_ap_ce;
sc_signal< bool > ap_predicate_op584_call_state6;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0_ignore_call23;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1_ignore_call23;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2_ignore_call23;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3_ignore_call23;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4_ignore_call23;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call23;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call23;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call23;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8_ignore_call23;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call23;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp584;
sc_signal< sc_lv<32> > grp_reg_int_s_fu_3813_ap_return;
sc_signal< sc_logic > grp_reg_int_s_fu_3813_ap_ce;
sc_signal< bool > ap_predicate_op602_call_state7;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0_ignore_call25;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1_ignore_call25;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2_ignore_call25;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3_ignore_call25;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4_ignore_call25;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call25;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call25;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call25;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8_ignore_call25;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call25;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp602;
sc_signal< sc_lv<32> > grp_reg_int_s_fu_3821_ap_return;
sc_signal< sc_logic > grp_reg_int_s_fu_3821_ap_ce;
sc_signal< bool > ap_predicate_op604_call_state7;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0_ignore_call27;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1_ignore_call27;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2_ignore_call27;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3_ignore_call27;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4_ignore_call27;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call27;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call27;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call27;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8_ignore_call27;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call27;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp604;
sc_signal< sc_lv<32> > grp_reg_int_s_fu_3829_ap_return;
sc_signal< sc_logic > grp_reg_int_s_fu_3829_ap_ce;
sc_signal< bool > ap_predicate_op606_call_state7;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0_ignore_call29;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1_ignore_call29;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2_ignore_call29;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3_ignore_call29;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4_ignore_call29;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call29;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call29;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call29;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8_ignore_call29;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call29;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp606;
sc_signal< sc_lv<32> > grp_reg_int_s_fu_3837_ap_return;
sc_signal< sc_logic > grp_reg_int_s_fu_3837_ap_ce;
sc_signal< bool > ap_predicate_op608_call_state7;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0_ignore_call31;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1_ignore_call31;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2_ignore_call31;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3_ignore_call31;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4_ignore_call31;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call31;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call31;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call31;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8_ignore_call31;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call31;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp608;
sc_signal< sc_logic > grp_reg_int_s_fu_3845_ap_ce;
sc_signal< bool > ap_predicate_op610_call_state7;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0_ignore_call33;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1_ignore_call33;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2_ignore_call33;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3_ignore_call33;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4_ignore_call33;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call33;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call33;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call33;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8_ignore_call33;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call33;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp610;
sc_signal< sc_logic > grp_reg_int_s_fu_3852_ap_ce;
sc_signal< bool > ap_predicate_op612_call_state7;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0_ignore_call35;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1_ignore_call35;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2_ignore_call35;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3_ignore_call35;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4_ignore_call35;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call35;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call35;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call35;
sc_signal< bool > ap_bl
|
ock_state11_pp0_stage0_iter8_ignore_call35;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call35;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp612;
sc_signal< sc_logic > grp_reg_int_s_fu_3859_ap_ce;
sc_signal< bool > ap_predicate_op614_call_state7;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0_ignore_call37;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1_ignore_call37;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2_ignore_call37;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3_ignore_call37;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4_ignore_call37;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call37;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call37;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call37;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8_ignore_call37;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call37;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp614;
sc_signal< sc_logic > grp_reg_int_s_fu_3866_ap_ce;
sc_signal< bool > ap_predicate_op616_call_state7;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0_ignore_call39;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1_ignore_call39;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2_ignore_call39;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3_ignore_call39;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4_ignore_call39;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call39;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call39;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call39;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8_ignore_call39;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call39;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp616;
sc_signal< sc_lv<32> > grp_reg_int_s_fu_3873_ap_return;
sc_signal< sc_logic > grp_reg_int_s_fu_3873_ap_ce;
sc_signal< bool > ap_predicate_op618_call_state7;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0_ignore_call41;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1_ignore_call41;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2_ignore_call41;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3_ignore_call41;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4_ignore_call41;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call41;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call41;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call41;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8_ignore_call41;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call41;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp618;
sc_signal< sc_lv<32> > grp_reg_int_s_fu_3881_ap_return;
sc_signal< sc_logic > grp_reg_int_s_fu_3881_ap_ce;
sc_signal< bool > ap_predicate_op620_call_state7;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0_ignore_call43;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1_ignore_call43;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2_ignore_call43;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3_ignore_call43;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4_ignore_call43;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call43;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call43;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call43;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8_ignore_call43;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call43;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp620;
sc_signal< sc_logic > grp_reg_int_s_fu_3889_ap_ce;
sc_signal< bool > ap_predicate_op622_call_state7;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0_ignore_call45;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1_ignore_call45;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2_ignore_call45;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3_ignore_call45;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4_ignore_call45;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call45;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call45;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call45;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8_ignore_call45;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call45;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp622;
sc_signal< sc_logic > grp_reg_int_s_fu_3896_ap_ce;
sc_signal< bool > ap_predicate_op624_call_state7;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0_ignore_call47;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1_ignore_call47;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2_ignore_call47;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3_ignore_call47;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4_ignore_call47;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call47;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call47;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call47;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8_ignore_call47;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call47;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp624;
sc_signal< sc_logic > grp_reg_int_s_fu_3903_ap_ce;
sc_signal< bool > ap_predicate_op626_call_state7;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0_ignore_call49;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1_ignore_call49;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2_ignore_call49;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3_ignore_call49;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4_ignore_call49;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call49;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call49;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call49;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8_ignore_call49;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call49;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp626;
sc_signal< sc_logic > grp_reg_int_s_fu_3910_ap_ce;
sc_signal< bool > ap_predicate_op628_call_state7;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0_ignore_call51;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1_ignore_call51;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2_ignore_call51;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3_ignore_call51;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4_ignore_call51;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call51;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call51;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call51;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8_ignore_call51;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call51;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp628;
sc_signal< sc_lv<32> > grp_reg_int_s_fu_3917_ap_return;
sc_signal< sc_logic > grp_reg_int_s_fu_3917_ap_ce;
sc_signal< bool > ap_predicate_op644_call_state8;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0_ignore_call53;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1_ignore_call53;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2_ignore_call53;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3_ignore_call53;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4_ignore_call53;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call53;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call53;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call53;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8_ignore_call53;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call53;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp644;
sc_signal< sc_lv<32> > grp_reg_int_s_fu_3925_ap_return;
sc_signal< sc_logic > grp_reg_int_s_fu_3925_ap_ce;
sc_signal< bool > ap_predicate_op646_call_state8;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0_ignore_call55;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1_ignore_call55;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2_ignore_call55;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3_ignore_call55;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4_ignore_call55;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call55;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call55;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call55;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8_ignore_call55;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call55;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp646;
sc_signal< sc_lv<32> > grp_reg_int_s_fu_3933_ap_return;
sc_signal< sc_logic > grp_reg_int_s_fu_3933_ap_ce;
sc_signal< bool > ap_predicate_op648_call_state8;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0_ignore_call57;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1_ignore_call57;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2_ignore_call57;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3_ignore_call57;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4_ignore_call57;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call57;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call57;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call57;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8_ignore_call57;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call57;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp648;
sc_signal< sc_lv<32> > grp_reg_int_s_fu_3941_ap_return;
sc_signal< sc_logic > grp_reg_int_s_fu_3941_ap_ce;
sc_signal< bool > ap_predicate_op650_call_state8;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0_ignore_call59;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1_ignore_call59;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2_ignore_call59;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3_ignore_call59;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4_ignore_call59;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call59;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call59;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call59;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8_ignore_call59;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call59;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp650;
sc_signal< sc_lv<32> > grp_reg_int_s_fu_3949_ap_return;
sc_signal< sc_logic > grp_reg_int_s_fu_3949_ap_ce;
sc_signal< bool > ap_predicate_op652_call_state8;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0_ignore_call61;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1_ignore_call61;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2_ignore_call61;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3_ignore_call61;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4_ignore_call61;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call61;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call61;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call61;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8_ignore_call61;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call61;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp652;
sc_signal< sc_lv<32> > grp_reg_int_s_fu_3957_ap_return;
sc_signal< sc_logic > grp_reg_int_s_fu_3957_ap_ce;
sc_signal< bool > ap_predicate_op654_call_state8;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0_ignore_call63;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1_ignore_call63;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2_ignore_call63;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3_ignore_call63;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4_ignore_call63;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call63;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call63;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call63;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8_ignore_call63;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call63;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp654;
sc_signal< sc_lv<32> > grp_reg_int_s_fu_3965_ap_return;
sc_signal< sc_logic > grp_reg_int_s_fu_3965_ap_ce;
sc_signal< bool > ap_predicate_op656_call_state8;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0_ignore_call65;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1_ignore_call65;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2_ignore_call65;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3_ignore_call65;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4_ignore_call65;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call65;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call65;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call65;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8_ignore_call65;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call65;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp656;
sc_signal< sc_lv<32> > grp_reg_int_s_fu_3973_ap_return;
sc_signal< sc_logic > grp_reg_int_s_fu_3973_ap_ce;
sc_signal< bool > ap_predicate_op658_call_state8;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0_ignore_call67;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1_ignore_call67;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2_ignore_call67;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3_ignore_call67;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4_ignore_call67;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call67;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call67;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call67;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8_ignore_call67;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call67;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp658;
sc_signal< sc_lv<32> > grp_reg_int_s_fu_3981_ap_return;
sc_signal< sc_logic > grp_reg_int_s_fu_3981_ap_ce;
sc_signal< bool > ap_predicate_op660_call_state8;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0_ignore_call69;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1_ignore_call69;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2_ignore_call69;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3_ignore_call69;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4_ignore_call69;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call69;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call69;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call69;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8_ignore_call69;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call69;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp660;
sc_signal< sc_lv<32> > grp_reg_int_s_fu_3989_ap_return;
sc_signal< sc_logic > grp_reg_int_s_fu_3989_ap_ce;
sc_signal< bool > ap_predicate_op662_call_state8;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0_ignore_call71;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1_ignore_call71;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2_ignore_call71;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3_ignore_call71;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4_ignore_call71;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call71;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call71;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call71;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8_ignore_call71;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call71;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp662;
sc_signal< sc_lv<32> > grp_reg_int_s_fu_3997_ap_return;
sc_signal< sc_logic > grp_reg_int_s_fu_3997_ap_ce;
sc_signal< bool > ap_predicate_op664_call_state8;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0_ignore_call73;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1_ignore_call73;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2_ignore_call73;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3_ignore_call73;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4_ignore_call73;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call73;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call73;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call73;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8_ignore_call73;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call73;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp664;
sc_signal< sc_lv<32> > grp_reg_int_s_fu_4005_ap_return;
sc_signal< sc_logic > grp_reg_int_s_fu_4005_ap_ce;
sc_signal< bool > ap_predicate_op666_call_state8;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0_ignore_call75;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1_ignore_call75;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2_ignore_call75;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3_ignore_call75;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4_ignore_call75;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call75;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call75;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call75;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8_ignore_call75;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call75;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp666;
sc_signal< sc_lv<32> > grp_reg_int_s_fu_4013_ap_return;
sc_signal< sc_logic > grp_reg_int_s_fu_4013_ap_ce;
sc_signal< bool > ap_predicate_op680_call_state9;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0_ignore_call77;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1_ignore_call77;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2_ignore_call77;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3_ignore_call77;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4_ignore_call77;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call77;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call77;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call77;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8_ignore_call77;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call77;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp680;
sc_signal< sc_lv<32> > grp_reg_int_s_fu_4021_ap_return;
sc_signal< sc_logic > grp_reg_int_s_fu_4021_ap_ce;
sc_signal< bool > ap_predicate_op682_call_state9;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0_ignore_call79;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1_ignore_call79;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2_ignore_call79;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3_ignore_call79;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4
|
_ignore_call79;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call79;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call79;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call79;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8_ignore_call79;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call79;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp682;
sc_signal< sc_lv<32> > grp_reg_int_s_fu_4029_ap_return;
sc_signal< sc_logic > grp_reg_int_s_fu_4029_ap_ce;
sc_signal< bool > ap_predicate_op684_call_state9;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0_ignore_call81;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1_ignore_call81;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2_ignore_call81;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3_ignore_call81;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4_ignore_call81;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call81;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call81;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call81;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8_ignore_call81;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call81;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp684;
sc_signal< sc_lv<32> > grp_reg_int_s_fu_4037_ap_return;
sc_signal< sc_logic > grp_reg_int_s_fu_4037_ap_ce;
sc_signal< bool > ap_predicate_op686_call_state9;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0_ignore_call83;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1_ignore_call83;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2_ignore_call83;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3_ignore_call83;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4_ignore_call83;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call83;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call83;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call83;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8_ignore_call83;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call83;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp686;
sc_signal< sc_lv<32> > grp_reg_int_s_fu_4045_ap_return;
sc_signal< sc_logic > grp_reg_int_s_fu_4045_ap_ce;
sc_signal< bool > ap_predicate_op688_call_state9;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0_ignore_call85;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1_ignore_call85;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2_ignore_call85;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3_ignore_call85;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4_ignore_call85;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call85;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call85;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call85;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8_ignore_call85;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call85;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp688;
sc_signal< sc_lv<32> > grp_reg_int_s_fu_4053_ap_return;
sc_signal< sc_logic > grp_reg_int_s_fu_4053_ap_ce;
sc_signal< bool > ap_predicate_op690_call_state9;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0_ignore_call87;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1_ignore_call87;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2_ignore_call87;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3_ignore_call87;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4_ignore_call87;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call87;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call87;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call87;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8_ignore_call87;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call87;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp690;
sc_signal< sc_lv<32> > grp_reg_int_s_fu_4061_ap_return;
sc_signal< sc_logic > grp_reg_int_s_fu_4061_ap_ce;
sc_signal< bool > ap_predicate_op723_call_state10;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0_ignore_call89;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1_ignore_call89;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2_ignore_call89;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3_ignore_call89;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4_ignore_call89;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call89;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call89;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call89;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8_ignore_call89;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call89;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp723;
sc_signal< sc_lv<32> > grp_reg_int_s_fu_4068_ap_return;
sc_signal< sc_logic > grp_reg_int_s_fu_4068_ap_ce;
sc_signal< bool > ap_predicate_op724_call_state10;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0_ignore_call91;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1_ignore_call91;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2_ignore_call91;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3_ignore_call91;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4_ignore_call91;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call91;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call91;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call91;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8_ignore_call91;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call91;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp724;
sc_signal< sc_lv<32> > grp_reg_int_s_fu_4075_ap_return;
sc_signal< sc_logic > grp_reg_int_s_fu_4075_ap_ce;
sc_signal< bool > ap_predicate_op725_call_state10;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0_ignore_call93;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1_ignore_call93;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2_ignore_call93;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3_ignore_call93;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4_ignore_call93;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call93;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call93;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call93;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8_ignore_call93;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call93;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp725;
sc_signal< sc_lv<32> > grp_reg_int_s_fu_4082_ap_return;
sc_signal< sc_logic > grp_reg_int_s_fu_4082_ap_ce;
sc_signal< bool > ap_predicate_op726_call_state10;
sc_signal< bool > ap_block_state3_pp0_stage0_iter0_ignore_call95;
sc_signal< bool > ap_block_state4_pp0_stage0_iter1_ignore_call95;
sc_signal< bool > ap_block_state5_pp0_stage0_iter2_ignore_call95;
sc_signal< bool > ap_block_state6_pp0_stage0_iter3_ignore_call95;
sc_signal< bool > ap_block_state7_pp0_stage0_iter4_ignore_call95;
sc_signal< bool > ap_block_state8_pp0_stage0_iter5_ignore_call95;
sc_signal< bool > ap_block_state9_pp0_stage0_iter6_ignore_call95;
sc_signal< bool > ap_block_state10_pp0_stage0_iter7_ignore_call95;
sc_signal< bool > ap_block_state11_pp0_stage0_iter8_ignore_call95;
sc_signal< bool > ap_block_state12_pp0_stage0_iter9_ignore_call95;
sc_signal< bool > ap_block_pp0_stage0_11001_ignoreCallOp726;
sc_signal< sc_lv<10> > t_V_reg_542;
sc_signal< bool > ap_block_state1;
sc_signal< sc_logic > ap_CS_fsm_state13;
sc_signal< sc_lv<16> > ap_phi_mux_core_1_phi_fu_568_p8;
sc_signal< sc_lv<16> > ap_phi_reg_pp0_iter0_core_1_reg_564;
sc_signal< sc_lv<16> > ap_phi_reg_pp0_iter1_core_1_reg_564;
sc_signal< sc_lv<16> > ap_phi_reg_pp0_iter2_core_1_reg_564;
sc_signal< sc_lv<16> > ap_phi_reg_pp0_iter3_core_1_reg_564;
sc_signal< sc_lv<16> > ap_phi_reg_pp0_iter4_core_1_reg_564;
sc_signal< sc_lv<16> > ap_phi_reg_pp0_iter5_core_1_reg_564;
sc_signal< sc_lv<16> > ap_phi_reg_pp0_iter6_core_1_reg_564;
sc_signal< sc_lv<16> > ap_phi_reg_pp0_iter7_core_1_reg_564;
sc_signal< sc_lv<16> > ap_phi_reg_pp0_iter8_core_1_reg_564;
sc_signal< sc_lv<16> > ap_phi_reg_pp0_iter9_core_1_reg_564;
sc_signal< sc_lv<16> > phitmp_fu_4099_p2;
sc_signal< sc_lv<64> > tmp_5_fu_1398_p1;
sc_signal< sc_lv<64> > tmp_6_fu_1408_p1;
sc_signal< bool > ap_block_pp0_stage0_01001;
sc_signal< sc_lv<16> > core_win_val_2_V_1_fu_166;
sc_signal< sc_lv<16> > core_win_val_2_V_2_fu_4112_p3;
sc_signal< sc_lv<16> > core_win_val_2_V_0_fu_170;
sc_signal< sc_lv<16> > core_win_val_1_V_1_fu_174;
sc_signal< sc_lv<16> > core_win_val_1_V_0_fu_178;
sc_signal< sc_lv<16> > core_win_val_0_V_1_fu_182;
sc_signal< sc_lv<16> > core_win_val_0_V_0_fu_186;
sc_signal< sc_lv<8> > win_val_0_V_2_fu_190;
sc_signal< sc_lv<8> > win_val_0_V_2_1_fu_194;
sc_signal< sc_lv<8> > win_val_0_V_3_fu_198;
sc_signal< sc_lv<8> > win_val_0_V_4_fu_202;
sc_signal< sc_lv<8> > win_val_0_V_5_fu_206;
sc_signal< sc_lv<8> > win_val_1_V_1_fu_210;
sc_signal< sc_lv<8> > win_val_1_V_1_1_fu_214;
sc_signal< sc_lv<8> > win_val_1_V_2_fu_218;
sc_signal< sc_lv<8> > win_val_1_V_3_fu_222;
sc_signal< sc_lv<8> > win_val_1_V_4_fu_226;
sc_signal< sc_lv<8> > win_val_1_V_5_fu_230;
sc_signal< sc_lv<8> > win_val_2_V_0_fu_234;
sc_signal< sc_lv<8> > win_val_2_V_0_1_fu_238;
sc_signal< sc_lv<8> > win_val_2_V_1_fu_242;
sc_signal< sc_lv<8> > win_val_2_V_2_fu_246;
sc_signal< sc_lv<8> > win_val_2_V_3_fu_250;
sc_signal< sc_lv<8> > win_val_2_V_4_fu_254;
sc_signal< sc_lv<8> > win_val_2_V_5_fu_258;
sc_signal< sc_lv<8> > win_val_3_V_0_fu_262;
sc_signal< sc_lv<8> > win_val_3_V_0_1_fu_266;
sc_signal< sc_lv<8> > win_val_3_V_1_fu_270;
sc_signal< sc_lv<8> > win_val_3_V_2_fu_274;
sc_signal< sc_lv<8> > win_val_3_V_3_fu_278;
sc_signal< sc_lv<8> > win_val_3_V_4_fu_282;
sc_signal< sc_lv<8> > win_val_3_V_5_fu_286;
sc_signal< sc_lv<8> > win_val_4_V_0_fu_290;
sc_signal< sc_lv<8> > win_val_4_V_0_1_fu_294;
sc_signal< sc_lv<8> > win_val_4_V_1_fu_298;
sc_signal< sc_lv<8> > win_val_4_V_2_fu_302;
sc_signal< sc_lv<8> > win_val_4_V_3_fu_306;
sc_signal< sc_lv<8> > win_val_4_V_4_fu_310;
sc_signal< sc_lv<8> > win_val_4_V_5_fu_314;
sc_signal< sc_lv<8> > win_val_5_V_1_fu_318;
sc_signal< sc_lv<8> > win_val_5_V_1_1_fu_322;
sc_signal< sc_lv<8> > win_val_5_V_2_fu_326;
sc_signal< sc_lv<8> > win_val_5_V_3_fu_330;
sc_signal< sc_lv<8> > win_val_5_V_4_fu_334;
sc_signal< sc_lv<8> > win_val_5_V_5_fu_338;
sc_signal< sc_lv<8> > win_val_6_V_2_fu_342;
sc_signal< sc_lv<8> > win_val_6_V_2_1_fu_346;
sc_signal< sc_lv<8> > win_val_6_V_3_fu_350;
sc_signal< sc_lv<8> > win_val_6_V_4_fu_354;
sc_signal< sc_lv<8> > win_val_6_V_5_fu_358;
sc_signal< sc_lv<1> > tmp_1_fu_1333_p2;
sc_signal< sc_lv<8> > tmp_28_fu_1351_p4;
sc_signal< sc_lv<1> > tmp_32_fu_1379_p3;
sc_signal< sc_lv<1> > rev_fu_1387_p2;
sc_signal< sc_lv<1> > tmp_7_fu_1414_p2;
sc_signal< sc_lv<9> > tmp_50_fu_1432_p4;
sc_signal< sc_lv<1> > icmp1_fu_1442_p2;
sc_signal< sc_lv<1> > tmp_11_fu_1788_p2;
sc_signal< sc_lv<1> > tmp_33_fu_1794_p2;
sc_signal< sc_lv<1> > tmp_115_1_fu_1800_p2;
sc_signal< sc_lv<1> > tmp23_fu_1829_p2;
sc_signal< sc_lv<1> > tmp22_fu_1835_p2;
sc_signal< sc_lv<1> > tmp21_fu_1824_p2;
sc_signal< sc_lv<9> > lhs_V_fu_1923_p1;
sc_signal< sc_lv<9> > rhs_V_fu_1927_p1;
sc_signal< sc_lv<9> > rhs_V_1_fu_1937_p1;
sc_signal< sc_lv<1> > tmp_15_fu_1947_p2;
sc_signal< sc_lv<1> > tmp_16_fu_1953_p2;
sc_signal< sc_lv<1> > tmp_17_fu_1967_p2;
sc_signal< sc_lv<2> > phitmp_i_i_fu_1959_p3;
sc_signal< sc_lv<1> > tmp_18_fu_1981_p2;
sc_signal< sc_lv<1> > tmp_19_fu_1987_p2;
sc_signal< sc_lv<1> > tmp_20_fu_2001_p2;
sc_signal< sc_lv<2> > phitmp1_i_i_fu_1993_p3;
sc_signal< sc_lv<9> > rhs_V_s_fu_2015_p1;
sc_signal< sc_lv<9> > rhs_V_1_1_fu_2025_p1;
sc_signal< sc_lv<1> > tmp_64_1_fu_2035_p2;
sc_signal< sc_lv<1> > tmp_65_1_fu_2041_p2;
sc_signal< sc_lv<1> > tmp_21_fu_2055_p2;
sc_signal< sc_lv<2> > phitmp_i_i_1_fu_2047_p3;
sc_signal< sc_lv<1> > tmp_70_1_fu_2069_p2;
sc_signal< sc_lv<1> > tmp_72_1_fu_2075_p2;
sc_signal< sc_lv<1> > tmp_22_fu_2089_p2;
sc_signal< sc_lv<2> > phitmp1_i_i_1_fu_2081_p3;
sc_signal< sc_lv<9> > rhs_V_2_fu_2103_p1;
sc_signal< sc_lv<9> > rhs_V_1_2_fu_2113_p1;
sc_signal< sc_lv<1> > tmp_64_2_fu_2123_p2;
sc_signal< sc_lv<1> > tmp_65_2_fu_2129_p2;
sc_signal< sc_lv<1> > tmp_37_fu_2143_p2;
sc_signal< sc_lv<2> > phitmp_i_i_2_fu_2135_p3;
sc_signal< sc_lv<1> > tmp_70_2_fu_2157_p2;
sc_signal< sc_lv<1> > tmp_72_2_fu_2163_p2;
sc_signal< sc_lv<1> > tmp_38_fu_2177_p2;
sc_signal< sc_lv<2> > phitmp1_i_i_2_fu_2169_p3;
sc_signal< sc_lv<9> > rhs_V_3_fu_2191_p1;
sc_signal< sc_lv<9> > rhs_V_1_3_fu_2201_p1;
sc_signal< sc_lv<1> > tmp_64_3_fu_2211_p2;
sc_signal< sc_lv<1> > tmp_65_3_fu_2217_p2;
sc_signal< sc_lv<1> > tmp_39_fu_2231_p2;
sc_signal< sc_lv<2> > phitmp_i_i_3_fu_2223_p3;
sc_signal< sc_lv<1> > tmp_70_3_fu_2245_p2;
sc_signal< sc_lv<1> > tmp_72_3_fu_2251_p2;
sc_signal< sc_lv<1> > tmp_40_fu_2265_p2;
sc_signal< sc_lv<2> > phitmp1_i_i_3_fu_2257_p3;
sc_signal< sc_lv<9> > rhs_V_4_fu_2279_p1;
sc_signal< sc_lv<9> > rhs_V_1_4_fu_2289_p1;
sc_signal< sc_lv<1> > tmp_64_4_fu_2299_p2;
sc_signal< sc_lv<1> > tmp_65_4_fu_2305_p2;
sc_signal< sc_lv<1> > tmp_41_fu_2319_p2;
sc_signal< sc_lv<2> > phitmp_i_i_4_fu_2311_p3;
sc_signal< sc_lv<1> > tmp_70_4_fu_2333_p2;
sc_signal< sc_lv<1> > tmp_72_4_fu_2339_p2;
sc_signal< sc_lv<1> > tmp_42_fu_2353_p2;
sc_signal< sc_lv<2> > phitmp1_i_i_4_fu_2345_p3;
sc_signal< sc_lv<9> > rhs_V_5_fu_2367_p1;
sc_signal< sc_lv<9> > rhs_V_1_5_fu_2377_p1;
sc_signal< sc_lv<1> > tmp_64_5_fu_2387_p2;
sc_signal< sc_lv<1> > tmp_65_5_fu_2393_p2;
sc_signal< sc_lv<1> > tmp_43_fu_2407_p2;
sc_signal< sc_lv<2> > phitmp_i_i_5_fu_2399_p3;
sc_signal< sc_lv<1> > tmp_70_5_fu_2421_p2;
sc_signal< sc_lv<1> > tmp_72_5_fu_2427_p2;
sc_signal< sc_lv<1> > tmp_44_fu_2441_p2;
sc_signal< sc_lv<2> > phitmp1_i_i_5_fu_2433_p3;
sc_signal< sc_lv<9> > rhs_V_6_fu_2455_p1;
sc_signal< sc_lv<9> > rhs_V_1_6_fu_2465_p1;
sc_signal< sc_lv<1> > tmp_64_6_fu_2475_p2;
sc_signal< sc_lv<1> > tmp_65_6_fu_2481_p2;
sc_signal< sc_lv<1> > tmp_45_fu_2495_p2;
sc_signal< sc_lv<2> > phitmp_i_i_6_fu_2487_p3;
sc_signal< sc_lv<1> > tmp_70_6_fu_2509_p2;
sc_signal< sc_lv<1> > tmp_72_6_fu_2515_p2;
sc_signal< sc_lv<1> > tmp_46_fu_2529_p2;
sc_signal< sc_lv<2> > phitmp1_i_i_6_fu_2521_p3;
sc_signal< sc_lv<9> > rhs_V_7_fu_2543_p1;
sc_signal< sc_lv<9> > rhs_V_1_7_fu_2553_p1;
sc_signal< sc_lv<1> > tmp_64_7_fu_2563_p2;
sc_signal< sc_lv<1> > tmp_65_7_fu_2569_p2;
sc_signal< sc_lv<1> > tmp_47_fu_2583_p2;
sc_signal< sc_lv<2> > phitmp_i_i_7_fu_2575_p3;
sc_signal< sc_lv<1> > tmp_70_7_fu_2597_p2;
sc_signal< sc_lv<1> > tmp_72_7_fu_2603_p2;
sc_signal< sc_lv<1> > tmp_48_fu_2617_p2;
sc_signal< sc_lv<2> > phitmp1_i_i_7_fu_2609_p3;
sc_signal< sc_lv<2> > flag_val_V_assign_lo_fu_1973_p3;
sc_signal< sc_lv<2> > flag_val_V_assign_lo_2_fu_2061_p3;
sc_signal< sc_lv<1> > tmp_23_fu_2637_p2;
sc_signal< sc_lv<1> > tmp_69_0_not_fu_2631_p2;
sc_signal< sc_lv<2> > flag_val_V_assign_lo_4_fu_2149_p3;
sc_signal< sc_lv<2> > flag_val_V_assign_lo_6_fu_2237_p3;
sc_signal< sc_lv<2> > flag_val_V_assign_lo_8_fu_2325_p3;
sc_signal< sc_lv<2> > flag_val_V_assign_lo_15_fu_2413_p3;
sc_signal< sc_lv<2> > flag_val_V_assign_lo_11_fu_2501_p3;
sc_signal< sc_lv<2> > flag_val_V_assign_lo_13_fu_2589_p3;
sc_signal< sc_lv<1> > tmp_71_6_fu_2745_p2;
sc_signal< sc_lv<1> > tmp_69_6_not_fu_2739_p2;
sc_signal< sc_lv<1> > tmp_24_fu_2773_p2;
sc_signal< sc_lv<4> > phitmp42_op_op_cast_s_fu_2765_p3;
sc_signal< sc_lv<4> > count_1_i_0_op_op_fu_2757_p3;
sc_signal< sc_lv<1> > tmp_25_fu_2795_p2;
sc_signal< sc_lv<4> > phitmp41_op_cast_cas_fu_2787_p3;
sc_signal< sc_lv<4> > count_1_i_2_op_op_fu_2779_p3;
sc_signal< sc_lv<1> > or_cond3_fu_2751_p2;
sc_signal< sc_lv<1> > tmp_26_fu_2817_p2;
sc_signal< sc_lv<4> > phitmp1_cast_cast_ca_fu_2809_p3;
sc_signal< sc_lv<4> > count_1_i_4_op_fu_2801_p3;
sc_signal< sc_lv<2> > flag_val_V_assign_lo_1_fu_2007_p3;
sc_signal< sc_lv<1> > tmp_71_7_fu_2837_p2;
sc_signal< sc_lv<1> > tmp_69_7_not_fu_2831_p2;
sc_signal< sc_lv<4> > count_1_i_6_fu_2823_p3;
sc_signal< sc_lv<1> > or_cond10_fu_2843_p2;
sc_signal< sc_lv<1> > tmp_73_7_fu_2849_p2;
sc_signal< sc_lv<2> > flag_val_V_assign_lo_3_fu_2095_p3;
sc_signal< sc_lv<1> > tmp_69_8_fu_2875_p2;
sc_signal< sc_lv<4> > count_1_i_7_fu_2867_p3;
sc_signal< sc_lv<4> > count_8_fu_2887_p2;
sc_signal< sc_lv<1> > or_cond11_fu_2881_p2;
sc_signal< sc_lv<1> > tmp_73_8_fu_2893_p2;
sc_signal< sc_lv<1> > not_or_cond1_fu_2905_p2;
sc_signal< sc_lv<4> > phitmp2_fu_2899_p2;
sc_signal< sc_lv<2> > flag_val_V_assign_lo_5_fu_2183_p3;
sc_signal< sc_lv<1> > tmp_69_9_fu_2925_p2;
sc_signal< sc_lv<1> > tmp_71_9_fu_2931_p2;
sc_signal< sc_lv<4> > count_1_i_8_fu_2917_p3;
sc_signal< sc_lv<1> > not_or_cond2_demorga_fu_2949_p2;
sc_signal< sc_lv<1> > tmp_73_9_fu_2943_p2;
sc_signal< sc_lv<1> > not_or_cond2_fu_2955_p2;
sc_signal< sc_lv<1> > or_cond12_fu_2937_p2;
sc_signal< sc_lv<2> > flag_val_V_assign_lo_7_fu_2271_p3;
sc_signal< sc_lv<1> > tmp_69_s_fu_2975_p2;
sc_signal< sc_lv<1> > tmp_71_s_fu_2981_p2;
sc_signal< sc_lv<4> > count_1_i_9_fu_2967_p3;
sc_signal< sc_lv<4> > count_s_fu_2993_p2;
sc_signal< sc_lv<1> > not_or_cond3_demorga_fu_3011_p2;
sc_signal< sc_lv<1> > tmp_73_s_fu_2999_p2;
sc_signal< sc_lv<1> > not_or_cond3_fu_3017_p2;
sc_signal< sc_lv<1> > or_cond13_fu_2987_p2;
sc_signal< sc_lv<4> > phitmp3_fu_3005_p2;
sc_signal< sc_lv<2> > flag_val_V_assign_lo_9_fu_2359_p3;
sc_signal< sc_lv<1> > tmp_69_1_fu_3037_p2;
sc_signal< sc_lv<1> > tmp_71_8_fu_3043_p2;
sc_signal< sc_lv<4> > count_1_i_s_fu_3029_p3;
sc_signal< sc_lv<1> > not_or_cond4_demorga_fu_3061_p2;
sc_signal< sc_lv<1> > tmp_73_1_fu_3055_p2;
sc_signal< sc_lv<1> > not_or_cond4_fu_3067_p2;
sc_signal< sc_lv<1> > or_cond14_fu_3049_p2;
sc_signal< sc_lv<2> > flag_val_V_assign_lo_10_fu_2447_p3;
sc_signal< sc_lv<1> > tmp_69_2_fu_3087_p2;
sc_signal< sc_lv<1> > tmp_71_10_fu_3093_p2;
sc_signal< sc_lv<4> > count_1_i_1_fu_3079_p3;
sc_signal< sc_lv<4> > count_1_fu_3105_p2;
sc_signal< sc_lv<1> > not_or_cond12_demorg_fu_3123_p2;
sc_signal< sc_lv<1> > tmp_73_2_fu_3111_p2;
sc_signal< sc_lv<1> > not_or_cond12_fu_3129_p2;
sc_signal< sc_lv<1> > or_cond15_fu_3099_p2;
sc_signal< sc_lv<4> > phitmp4_fu_3117_p2;
sc_signal< sc_lv<2> > flag_val_V_assign_lo_12_fu_2535_p3;
sc_signal< sc_lv<2> > flag_val_V_assign_lo_14_fu_2623_p3;
sc_signal< sc_lv<1> > tmp_69_5_fu_3173_p2;
sc_signal< sc_lv<1> > not_or_cond11_demorg_fu_3185_p2;
sc_signal< sc_lv<1> > iscorner_2_i_7_fu_2861_p2;
sc_signal< sc_lv<1> > p_iscorner_0_i_8_fu_2911_p2;
sc_signal< sc_lv<1> > p_iscorner_0_i_9_fu_2961_p2;
sc_signal< sc_lv<1> > p_iscorner_0_i_s_fu_3023_p2;
sc_
|
signal< sc_lv<1> > tmp8_fu_3203_p2;
sc_signal< sc_lv<1> > tmp7_fu_3197_p2;
sc_signal< sc_lv<1> > p_iscorner_0_i_1_fu_3073_p2;
sc_signal< sc_lv<1> > p_iscorner_0_i_2_fu_3135_p2;
sc_signal< sc_lv<1> > not_or_cond13_demorg_fu_3290_p2;
sc_signal< sc_lv<1> > tmp_73_3_fu_3285_p2;
sc_signal< sc_lv<1> > not_or_cond13_fu_3294_p2;
sc_signal< sc_lv<1> > or_cond16_fu_3281_p2;
sc_signal< sc_lv<4> > count_1_i_3_fu_3306_p3;
sc_signal< sc_lv<5> > count_1_i_3_cast_fu_3313_p1;
sc_signal< sc_lv<5> > count_2_fu_3321_p2;
sc_signal< sc_lv<1> > not_or_cond14_demorg_fu_3339_p2;
sc_signal< sc_lv<1> > tmp_73_4_fu_3327_p2;
sc_signal< sc_lv<1> > not_or_cond14_fu_3343_p2;
sc_signal< sc_lv<1> > or_cond17_fu_3317_p2;
sc_signal< sc_lv<5> > phitmp5_fu_3333_p2;
sc_signal< sc_lv<5> > count_1_i_4_fu_3355_p3;
sc_signal< sc_lv<1> > tmp_73_5_fu_3363_p2;
sc_signal< sc_lv<1> > not_or_cond15_fu_3369_p2;
sc_signal< sc_lv<5> > count_1_i_5_fu_3380_p3;
sc_signal< sc_lv<5> > count_3_fu_3387_p2;
sc_signal< sc_lv<1> > tmp_73_6_fu_3393_p2;
sc_signal< sc_lv<1> > not_or_cond5_fu_3405_p2;
sc_signal< sc_lv<5> > phitmp6_fu_3399_p2;
sc_signal< sc_lv<5> > count_1_i_10_fu_3416_p3;
sc_signal< sc_lv<1> > not_or_cond6_demorga_fu_3429_p2;
sc_signal< sc_lv<1> > tmp_73_10_fu_3423_p2;
sc_signal< sc_lv<1> > not_or_cond6_fu_3433_p2;
sc_signal< sc_lv<5> > count_1_i_11_fu_3445_p3;
sc_signal< sc_lv<5> > count_4_fu_3452_p2;
sc_signal< sc_lv<1> > not_or_cond7_demorga_fu_3470_p2;
sc_signal< sc_lv<1> > tmp_73_11_fu_3458_p2;
sc_signal< sc_lv<1> > not_or_cond7_fu_3474_p2;
sc_signal< sc_lv<5> > phitmp7_fu_3464_p2;
sc_signal< sc_lv<5> > count_1_i_12_fu_3486_p3;
sc_signal< sc_lv<1> > not_or_cond8_demorga_fu_3499_p2;
sc_signal< sc_lv<1> > tmp_73_12_fu_3493_p2;
sc_signal< sc_lv<1> > not_or_cond8_fu_3503_p2;
sc_signal< sc_lv<5> > count_1_i_13_fu_3515_p3;
sc_signal< sc_lv<5> > count_5_fu_3522_p2;
sc_signal< sc_lv<1> > not_or_cond9_demorga_fu_3540_p2;
sc_signal< sc_lv<1> > tmp_73_13_fu_3528_p2;
sc_signal< sc_lv<1> > not_or_cond9_fu_3544_p2;
sc_signal< sc_lv<5> > phitmp8_fu_3534_p2;
sc_signal< sc_lv<5> > count_1_i_14_fu_3556_p3;
sc_signal< sc_lv<1> > not_or_cond10_demorg_fu_3569_p2;
sc_signal< sc_lv<1> > tmp_73_14_fu_3563_p2;
sc_signal< sc_lv<1> > not_or_cond10_fu_3573_p2;
sc_signal< sc_lv<5> > count_1_i_15_fu_3585_p3;
sc_signal< sc_lv<5> > count_6_fu_3592_p2;
sc_signal< sc_lv<1> > tmp_73_15_fu_3598_p2;
sc_signal< sc_lv<5> > phitmp9_fu_3604_p2;
sc_signal< sc_lv<1> > tmp4_fu_3621_p2;
sc_signal< sc_lv<1> > tmp_73_16_fu_3615_p2;
sc_signal< sc_lv<1> > p_iscorner_0_i_3_fu_3300_p2;
sc_signal< sc_lv<1> > p_iscorner_0_i_4_fu_3349_p2;
sc_signal< sc_lv<1> > tmp11_fu_3631_p2;
sc_signal< sc_lv<1> > tmp9_fu_3637_p2;
sc_signal< sc_lv<1> > p_iscorner_0_i_5_fu_3374_p2;
sc_signal< sc_lv<1> > p_iscorner_0_i_6_fu_3410_p2;
sc_signal< sc_lv<1> > p_iscorner_0_i_7_fu_3439_p2;
sc_signal< sc_lv<1> > p_iscorner_0_i_10_fu_3480_p2;
sc_signal< sc_lv<1> > tmp15_fu_3653_p2;
sc_signal< sc_lv<1> > tmp14_fu_3647_p2;
sc_signal< sc_lv<1> > p_iscorner_0_i_11_fu_3509_p2;
sc_signal< sc_lv<1> > p_iscorner_0_i_12_fu_3550_p2;
sc_signal< sc_lv<1> > p_iscorner_0_i_14_fu_3610_p2;
sc_signal< sc_lv<1> > p_iscorner_0_i_15_fu_3625_p2;
sc_signal< sc_lv<1> > tmp19_fu_3671_p2;
sc_signal< sc_lv<1> > p_iscorner_0_i_13_fu_3579_p2;
sc_signal< sc_lv<1> > tmp18_fu_3677_p2;
sc_signal< sc_lv<1> > tmp17_fu_3665_p2;
sc_signal< sc_lv<1> > tmp16_fu_3683_p2;
sc_signal< sc_lv<1> > tmp13_fu_3659_p2;
sc_signal< sc_lv<1> > tmp12_fu_3689_p2;
sc_signal< sc_lv<1> > tmp5_fu_3642_p2;
sc_signal< sc_lv<16> > tmp_49_fu_4095_p1;
sc_signal< sc_lv<1> > tmp_34_fu_4120_p2;
sc_signal< sc_lv<1> > tmp_118_1_fu_4125_p2;
sc_signal< sc_lv<1> > tmp26_fu_4135_p2;
sc_signal< sc_lv<1> > tmp28_fu_4146_p2;
sc_signal< sc_lv<1> > tmp_118_2_fu_4130_p2;
sc_signal< sc_lv<1> > tmp27_fu_4150_p2;
sc_signal< sc_lv<1> > tmp25_fu_4141_p2;
sc_signal< sc_lv<1> > tmp24_fu_4156_p2;
sc_signal< sc_lv<1> > tmp_36_fu_4162_p2;
sc_signal< sc_lv<4> > ap_NS_fsm;
sc_signal< sc_logic > ap_idle_pp0;
sc_signal< sc_logic > ap_enable_pp0;
sc_signal< bool > ap_condition_2362;
static const sc_logic ap_const_logic_1;
static const sc_logic ap_const_logic_0;
static const sc_lv<4> ap_ST_fsm_state1;
static const sc_lv<4> ap_ST_fsm_state2;
static const sc_lv<4> ap_ST_fsm_pp0_stage0;
static const sc_lv<4> ap_ST_fsm_state13;
static const bool ap_const_boolean_1;
static const sc_lv<32> ap_const_lv32_0;
static const sc_lv<32> ap_const_lv32_2;
static const bool ap_const_boolean_0;
static const sc_lv<1> ap_const_lv1_0;
static const sc_lv<1> ap_const_lv1_1;
static const sc_lv<32> ap_const_lv32_1;
static const sc_lv<10> ap_const_lv10_0;
static const sc_lv<32> ap_const_lv32_3;
static const sc_lv<11> ap_const_lv11_0;
static const sc_lv<16> ap_const_lv16_0;
static const sc_lv<32> ap_const_lv32_FFFFFFEC;
static const sc_lv<32> ap_const_lv32_14;
static const sc_lv<10> ap_const_lv10_304;
static const sc_lv<10> ap_const_lv10_1;
static const sc_lv<10> ap_const_lv10_300;
static const sc_lv<10> ap_const_lv10_5;
static const sc_lv<10> ap_const_lv10_6;
static const sc_lv<32> ap_const_lv32_9;
static const sc_lv<8> ap_const_lv8_0;
static const sc_lv<11> ap_const_lv11_404;
static const sc_lv<11> ap_const_lv11_1;
static const sc_lv<32> ap_const_lv32_A;
static const sc_lv<11> ap_const_lv11_5;
static const sc_lv<11> ap_const_lv11_6;
static const sc_lv<9> ap_const_lv9_0;
static const sc_lv<9> ap_const_lv9_14;
static const sc_lv<9> ap_const_lv9_1EC;
static const sc_lv<2> ap_const_lv2_1;
static const sc_lv<2> ap_const_lv2_2;
static const sc_lv<2> ap_const_lv2_0;
static const sc_lv<4> ap_const_lv4_8;
static const sc_lv<4> ap_const_lv4_9;
static const sc_lv<4> ap_const_lv4_6;
static const sc_lv<4> ap_const_lv4_7;
static const sc_lv<4> ap_const_lv4_4;
static const sc_lv<4> ap_const_lv4_5;
static const sc_lv<4> ap_const_lv4_2;
static const sc_lv<4> ap_const_lv4_3;
static const sc_lv<4> ap_const_lv4_1;
static const sc_lv<5> ap_const_lv5_1;
static const sc_lv<5> ap_const_lv5_8;
static const sc_lv<5> ap_const_lv5_2;
static const sc_lv<16> ap_const_lv16_FFFF;
static const sc_lv<8> ap_const_lv8_FF;
// Thread declarations
void thread_ap_var_for_const0();
void thread_ap_var_for_const1();
void thread_ap_clk_no_reset_();
void thread_ap_CS_fsm_pp0_stage0();
void thread_ap_CS_fsm_state1();
void thread_ap_CS_fsm_state13();
void thread_ap_CS_fsm_state2();
void thread_ap_block_pp0_stage0();
void thread_ap_block_pp0_stage0_01001();
void thread_ap_block_pp0_stage0_11001();
void thread_ap_block_pp0_stage0_11001_ignoreCallOp562();
void thread_ap_block_pp0_stage0_11001_ignoreCallOp564();
void thread_ap_block_pp0_stage0_11001_ignoreCallOp566();
void thread_ap_block_pp0_stage0_11001_ignoreCallOp568();
void thread_ap_block_pp0_stage0_11001_ignoreCallOp570();
void thread_ap_block_pp0_stage0_11001_ignoreCallOp572();
void thread_ap_block_pp0_stage0_11001_ignoreCallOp574();
void thread_ap_block_pp0_stage0_11001_ignoreCallOp576();
void thread_ap_block_pp0_stage0_11001_ignoreCallOp578();
void thread_ap_block_pp0_stage0_11001_ignoreCallOp580();
void thread_ap_block_pp0_stage0_11001_ignoreCallOp582();
void thread_ap_block_pp0_stage0_11001_ignoreCallOp584();
void thread_ap_block_pp0_stage0_11001_ignoreCallOp602();
void thread_ap_block_pp0_stage0_11001_ignoreCallOp604();
void thread_ap_block_pp0_stage0_11001_ignoreCallOp606();
void thread_ap_block_pp0_stage0_11001_ignoreCallOp608();
void thread_ap_block_pp0_stage0_11001_ignoreCallOp610();
void thread_ap_block_pp0_stage0_11001_ignoreCallOp612();
void thread_ap_block_pp0_stage0_11001_ignoreCallOp614();
void thread_ap_block_pp0_stage0_11001_ignoreCallOp616();
void thread_ap_block_pp0_stage0_11001_ignoreCallOp618();
void thread_ap_block_pp0_stage0_11001_ignoreCallOp620();
void thread_ap_block_pp0_stage0_11001_ignoreCallOp622();
void thread_ap_block_pp0_stage0_11001_ignoreCallOp624();
void thread_ap_block_pp0_stage0_11001_ignoreCallOp626();
void thread_ap_block_pp0_stage0_11001_ignoreCallOp628();
void thread_ap_block_pp0_stage0_11001_ignoreCallOp644();
void thread_ap_block_pp0_stage0_11001_ignoreCallOp646();
void thread_ap_block_pp0_stage0_11001_ignoreCallOp648();
void thread_ap_block_pp0_stage0_11001_ignoreCallOp650();
void thread_ap_block_pp0_stage0_11001_ignoreCallOp652();
void thread_ap_block_pp0_stage0_11001_ignoreCallOp654();
void thread_ap_block_pp0_stage0_11001_ignoreCallOp656();
void thread_ap_block_pp0_stage0_11001_ignoreCallOp658();
void thread_ap_block_pp0_stage0_11001_ignoreCallOp660();
void thread_ap_block_pp0_stage0_11001_ignoreCallOp662();
void thread_ap_block_pp0_stage0_11001_ignoreCallOp664();
void thread_ap_block_pp0_stage0_11001_ignoreCallOp666();
void thread_ap_block_pp0_stage0_11001_ignoreCallOp680();
void thread_ap_block_pp0_stage0_11001_ignoreCallOp682();
void thread_ap_block_pp0_stage0_11001_ignoreCallOp684();
void thread_ap_block_pp0_stage0_11001_ignoreCallOp686();
void thread_ap_block_pp0_stage0_11001_ignoreCallOp688();
void thread_ap_block_pp0_stage0_11001_ignoreCallOp690();
void thread_ap_block_pp0_stage0_11001_ignoreCallOp723();
void thread_ap_block_pp0_stage0_11001_ignoreCallOp724();
void thread_ap_block_pp0_stage0_11001_ignoreCallOp725();
void thread_ap_block_pp0_stage0_11001_ignoreCallOp726();
void thread_ap_block_pp0_stage0_subdone();
void thread_ap_block_state1();
void thread_ap_block_state10_pp0_stage0_iter7();
void thread_ap_block_state10_pp0_stage0_iter7_ignore_call1();
void thread_ap_block_state10_pp0_stage0_iter7_ignore_call11();
void thread_ap_block_state10_pp0_stage0_iter7_ignore_call13();
void thread_ap_block_state10_pp0_stage0_iter7_ignore_call15();
void thread_ap_block_state10_pp0_stage0_iter7_ignore_call17();
void thread_ap_block_state10_pp0_stage0_iter7_ignore_call19();
void thread_ap_block_state10_pp0_stage0_iter7_ignore_call21();
void thread_ap_block_state10_pp0_stage0_iter7_ignore_call23();
void thread_ap_block_state10_pp0_stage0_iter7_ignore_call25();
void thread_ap_block_state10_pp0_stage0_iter7_ignore_call27();
void thread_ap_block_state10_pp0_stage0_iter7_ignore_call29();
void thread_ap_block_state10_pp0_stage0_iter7_ignore_call3();
void thread_ap_block_state10_pp0_stage0_iter7_ignore_call31();
void thread_ap_block_state10_pp0_stage0_iter7_ignore_call33();
void thread_ap_block_state10_pp0_stage0_iter7_ignore_call35();
void thread_ap_block_state10_pp0_stage0_iter7_ignore_call37();
void thread_ap_block_state10_pp0_stage0_iter7_ignore_call39();
void thread_ap_block_state10_pp0_stage0_iter7_ignore_call41();
void thread_ap_block_state10_pp0_stage0_iter7_ignore_call43();
void thread_ap_block_state10_pp0_stage0_iter7_ignore_call45();
void thread_ap_block_state10_pp0_stage0_iter7_ignore_call47();
void thread_ap_block_state10_pp0_stage0_iter7_ignore_call49();
void thread_ap_block_state10_pp0_stage0_iter7_ignore_call5();
void thread_ap_block_state10_pp0_stage0_iter7_ignore_call51();
void thread_ap_block_state10_pp0_stage0_iter7_ignore_call53();
void thread_ap_block_state10_pp0_stage0_iter7_ignore_call55();
void thread_ap_block_state10_pp0_stage0_iter7_ignore_call57();
void thread_ap_block_state10_pp0_stage0_iter7_ignore_call59();
void thread_ap_block_state10_pp0_stage0_iter7_ignore_call61();
void thread_ap_block_state10_pp0_stage0_iter7_ignore_call63();
void thread_ap_block_state10_pp0_stage0_iter7_ignore_call65();
void thread_ap_block_state10_pp0_stage0_iter7_ignore_call67();
void thread_ap_block_state10_pp0_stage0_iter7_ignore_call69();
void thread_ap_block_state10_pp0_stage0_iter7_ignore_call7();
void thread_ap_block_state10_pp0_stage0_iter7_ignore_call71();
void thread_ap_block_state10_pp0_stage0_iter7_ignore_call73();
void thread_ap_block_state10_pp0_stage0_iter7_ignore_call75();
void thread_ap_block_state10_pp0_stage0_iter7_ignore_call77();
void thread_ap_block_state10_pp0_stage0_iter7_ignore_call79();
void thread_ap_block_state10_pp0_stage0_iter7_ignore_call81();
void thread_ap_block_state10_pp0_stage0_iter7_ignore_call83();
void thread_ap_block_state10_pp0_stage0_iter7_ignore_call85();
void thread_ap_block_state10_pp0_stage0_iter7_ignore_call87();
void thread_ap_block_state10_pp0_stage0_iter7_ignore_call89();
void thread_ap_block_state10_pp0_stage0_iter7_ignore_call9();
void thread_ap_block_state10_pp0_stage0_iter7_ignore_call91();
void thread_ap_block_state10_pp0_stage0_iter7_ignore_call93();
void thread_ap_block_state10_pp0_stage0_iter7_ignore_call95();
void thread_ap_block_state11_pp0_stage0_iter8();
void thread_ap_block_state11_pp0_stage0_iter8_ignore_call1();
void thread_ap_block_state11_pp0_stage0_iter8_ignore_call11();
void thread_ap_block_state11_pp0_stage0_iter8_ignore_call13();
void thread_ap_block_state11_pp0_stage0_iter8_ignore_call15();
void thread_ap_block_state11_pp0_stage0_iter8_ignore_call17();
void thread_ap_block_state11_pp0_stage0_iter8_ignore_call19();
void thread_ap_block_state11_pp0_stage0_iter8_ignore_call21();
void thread_ap_block_state11_pp0_stage0_iter8_ignore_call23();
void thread_ap_block_state11_pp0_stage0_iter8_ignore_call25();
void thread_ap_block_state11_pp0_stage0_iter8_ignore_call27();
void thread_ap_block_state11_pp0_stage0_iter8_ignore_call29();
void thread_ap_block_state11_pp0_stage0_iter8_ignore_call3();
void thread_ap_block_state11_pp0_stage0_iter8_ignore_call31();
void thread_ap_block_state11_pp0_stage0_iter8_ignore_call33();
void thread_ap_block_state11_pp0_stage0_iter8_ignore_call35();
void thread_ap_block_state11_pp0_stage0_iter8_ignore_call37();
void thread_ap_block_state11_pp0_stage0_iter8_ignore_call39();
void thread_ap_block_state11_pp0_stage0_iter8_ignore_call41();
void thread_ap_block_state11_pp0_stage0_iter8_ignore_call43();
void thread_ap_block_state11_pp0_stage0_iter8_ignore_call45();
void thread_ap_block_state11_pp0_stage0_iter8_ignore_call47();
void thread_ap_block_state11_pp0_stage0_iter8_ignore_call49();
void thread_ap_block_state11_pp0_stage0_iter8_ignore_call5();
void thread_ap_block_state11_pp0_stage0_iter8_ignore_call51();
void thread_ap_block_state11_pp0_stage0_iter8_ignore_call53();
void thread_ap_block_state11_pp0_stage0_iter8_ignore_call55();
void thread_ap_block_state11_pp0_stage0_iter8_ignore_call57();
void thread_ap_block_state11_pp0_stage0_iter8_ignore_call59();
void thread_ap_block_state11_pp0_stage0_iter8_ignore_call61();
void thread_ap_block_state11_pp0_stage0_iter8_ignore_call63();
void thread_ap_block_state11_pp0_stage0_iter8_ignore_call65();
void thread_ap_block_state11_pp0_stage0_iter8_ignore_call67();
void thread_ap_block_state11_pp0_stage0_iter8_ignore_call69();
void thread_ap_block_state11_pp0_stage0_iter8_ignore_call7();
void thread_ap_block_state11_pp0_stage0_iter8_ignore_call71();
void thread_ap_block_state11_pp0_stage0_iter8_ignore_call73();
void thread_ap_block_state11_pp0_stage0_iter8_ignore_call75();
void thread_ap_block_state11_pp0_stage0_iter8_ignore_call77();
void thread_ap_block_state11_pp0_stage0_iter8_ignore_call79();
void thread_ap_block_state11_pp0_stage0_iter8_ignore_call81();
void thread_ap_block_state11_pp0_stage0_iter8_ignore_call83();
void thread_ap_block_state11_pp0_stage0_iter8_ignore_call85();
void thread_ap_block_state11_pp0_stage0_iter8_ignore_call87();
void thread_ap_block_state11_pp0_stage0_iter8_ignore_call89();
void thread_ap_block_state11_pp0_stage0_iter8_ignore_call9();
void thread_ap_block_state11_pp0_stage0_iter8_ignore_call91();
void thread_ap_block_state11_pp0_stage0_iter8_ignore_call93();
void thread_ap_block_state11_pp0_stage0_iter8_ignore_call95();
void thread_ap_block_state12_pp0_stage0_iter9();
void thread_ap_block_state12_pp0_stage0_iter9_ignore_call1();
void thread_ap_block_state12_pp0_stage0_iter9_ignore_call11();
void thread_ap_block_state12_pp0_stage0_iter9_ignore_call13();
void thread_ap_block_state12_pp0_stage0_iter9_ignore_call15();
void thread_ap_block_state12_pp0_stage0_iter9_ignore_call17();
void thread_ap_block_state12_pp0_stage0_iter9_ignore_call19();
void thread_ap_block_state12_pp0_stage0_iter9_ignore_call21();
void thread_ap_block_state12_pp0_stage0_iter9_ignore_call23();
void thread_ap_block_state12_pp0_stage0_iter9_ignore_call25();
void thread_ap_block_state12_pp0_stage0_iter9_ignore_call27();
void thread_ap_block_state12_pp0_stage0_iter9_ignore_call29();
void thread_ap_block_state12_pp0_stage0_iter9_ignore_call3();
void thread_ap_block_state12_pp0_stage0_iter9_ignore_call31();
void thread_ap_block_state12_pp0_stage0_iter9_ignore_call33();
void thread_ap_block_state12_pp0_stage0_iter9_ignore_call35();
void thread_ap_block_state12_pp0_stage0_iter9_ignore_call37();
void thread_ap_block_state12_pp0_stage0_iter9_ignore_call39();
void thread_ap_block_state12_pp0_stage0_iter9_ignore_call41();
void thread_ap_block_state12_pp0_stage0_iter9_ignore_call43();
void thread_ap_block_state12_pp0_stage0_iter9_ignore_call45();
void thread_ap_block_state12_pp0_stage0_iter9_ignore_call47();
void thread_ap_block_state12_pp0_stage0_iter9_ignore_call49();
void thread_ap_block_state12_pp0_stage0_iter9_ignore_call5();
void thread_ap_block_state12_pp0_stage0_iter9_ignore_call51();
void thread_ap_block_state12_pp0_stage0_iter9_ignore_call53();
void thread_ap_block_state12_pp0_stage0_iter9_ignore_call55();
void thread_ap_block_state12_pp0_stage0_iter9_ignore_call57();
void thread_ap_block_state12_pp0_stage0_iter9_ignore_call59();
void thread_ap_block_state12_pp0_stage0_iter9_ignore_call61();
void thread_ap_block_state12_pp0_stage0_iter9_ignore_call63();
void thread_ap_block_state12_pp0_stage0_iter9_ignore_call65();
void thread_ap_block_state12_pp0_stage0_iter9_ignore_call67();
void thread_ap_block_state12_pp0_stage0_iter9_ignore_call69();
void thread_ap_block_state12_pp0_stage0_iter9_ignore_call7();
void thread_ap_block_state12_pp0_stage0_iter9_ignore_call71();
void thread_ap_block_state12_pp0_stage0_iter9_ignore_call73();
void thread_ap_block_state12_pp0_stage0_iter9_ignore_call75();
void thread_ap_block_state12_pp0_stage0_iter9_ignore_call77();
void thread_ap_block_state12_pp0_stage0_iter9_ignore_call79();
void thread_ap_block_state12_pp0_stage0_iter9_ignore_call81();
void thread_ap_block_state12_pp0_stage0_iter9_ignore_call83();
void thread_ap_block_state12_pp0_stage0_iter9_ignore_call85();
void thread_ap_block_state12_pp0_stage0_iter9_ignore_call87();
void thread_ap_block_state12_pp0_stage0_iter9_ignore_call89();
void thread_ap_block_state12_pp0_stage0_iter9_ignore_call9();
void thread_ap_block_state12_pp0_stage0_iter9_ignore_call91();
void thread_ap_block_state12_pp0_stage0_iter9_ignore_call93();
void thread_ap_block_state12_pp0_stage0_iter9_ignore_call95();
void thread_ap_block_state3_pp0_stage0_iter0();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call1();
void thread_ap_block_state3_pp0_stage0
|
_iter0_ignore_call11();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call13();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call15();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call17();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call19();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call21();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call23();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call25();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call27();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call29();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call3();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call31();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call33();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call35();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call37();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call39();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call41();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call43();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call45();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call47();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call49();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call5();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call51();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call53();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call55();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call57();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call59();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call61();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call63();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call65();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call67();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call69();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call7();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call71();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call73();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call75();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call77();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call79();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call81();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call83();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call85();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call87();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call89();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call9();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call91();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call93();
void thread_ap_block_state3_pp0_stage0_iter0_ignore_call95();
void thread_ap_block_state4_pp0_stage0_iter1();
void thread_ap_block_state4_pp0_stage0_iter1_ignore_call1();
void thread_ap_block_state4_pp0_stage0_iter1_ignore_call11();
void thread_ap_block_state4_pp0_stage0_iter1_ignore_call13();
void thread_ap_block_state4_pp0_stage0_iter1_ignore_call15();
void thread_ap_block_state4_pp0_stage0_iter1_ignore_call17();
void thread_ap_block_state4_pp0_stage0_iter1_ignore_call19();
void thread_ap_block_state4_pp0_stage0_iter1_ignore_call21();
void thread_ap_block_state4_pp0_stage0_iter1_ignore_call23();
void thread_ap_block_state4_pp0_stage0_iter1_ignore_call25();
void thread_ap_block_state4_pp0_stage0_iter1_ignore_call27();
void thread_ap_block_state4_pp0_stage0_iter1_ignore_call29();
void thread_ap_block_state4_pp0_stage0_iter1_ignore_call3();
void thread_ap_block_state4_pp0_stage0_iter1_ignore_call31();
void thread_ap_block_state4_pp0_stage0_iter1_ignore_call33();
void thread_ap_block_state4_pp0_stage0_iter1_ignore_call35();
void thread_ap_block_state4_pp0_stage0_iter1_ignore_call37();
void thread_ap_block_state4_pp0_stage0_iter1_ignore_call39();
void thread_ap_block_state4_pp0_stage0_iter1_ignore_call41();
void thread_ap_block_state4_pp0_stage0_iter1_ignore_call43();
void thread_ap_block_state4_pp0_stage0_iter1_ignore_call45();
void thread_ap_block_state4_pp0_stage0_iter1_ignore_call47();
void thread_ap_block_state4_pp0_stage0_iter1_ignore_call49();
void thread_ap_block_state4_pp0_stage0_iter1_ignore_call5();
void thread_ap_block_state4_pp0_stage0_iter1_ignore_call51();
void thread_ap_block_state4_pp0_stage0_iter1_ignore_call53();
void thread_ap_block_state4_pp0_stage0_iter1_ignore_call55();
void thread_ap_block_state4_pp0_stage0_iter1_ignore_call57();
void thread_ap_block_state4_pp0_stage0_iter1_ignore_call59();
void thread_ap_block_state4_pp0_stage0_iter1_ignore_call61();
void thread_ap_block_state4_pp0_stage0_iter1_ignore_call63();
void thread_ap_block_state4_pp0_stage0_iter1_ignore_call65();
void thread_ap_block_state4_pp0_stage0_iter1_ignore_call67();
void thread_ap_block_state4_pp0_stage0_iter1_ignore_call69();
void thread_ap_block_state4_pp0_stage0_iter1_ignore_call7();
void thread_ap_block_state4_pp0_stage0_iter1_ignore_call71();
void thread_ap_block_state4_pp0_stage0_iter1_ignore_call73();
void thread_ap_block_state4_pp0_stage0_iter1_ignore_call75();
void thread_ap_block_state4_pp0_stage0_iter1_ignore_call77();
void thread_ap_block_state4_pp0_stage0_iter1_ignore_call79();
void thread_ap_block_state4_pp0_stage0_iter1_ignore_call81();
void thread_ap_block_state4_pp0_stage0_iter1_ignore_call83();
void thread_ap_block_state4_pp0_stage0_iter1_ignore_call85();
void thread_ap_block_state4_pp0_stage0_iter1_ignore_call87();
void thread_ap_block_state4_pp0_stage0_iter1_ignore_call89();
void thread_ap_block_state4_pp0_stage0_iter1_ignore_call9();
void thread_ap_block_state4_pp0_stage0_iter1_ignore_call91();
void thread_ap_block_state4_pp0_stage0_iter1_ignore_call93();
void thread_ap_block_state4_pp0_stage0_iter1_ignore_call95();
void thread_ap_block_state5_pp0_stage0_iter2();
void thread_ap_block_state5_pp0_stage0_iter2_ignore_call1();
void thread_ap_block_state5_pp0_stage0_iter2_ignore_call11();
void thread_ap_block_state5_pp0_stage0_iter2_ignore_call13();
void thread_ap_block_state5_pp0_stage0_iter2_ignore_call15();
void thread_ap_block_state5_pp0_stage0_iter2_ignore_call17();
void thread_ap_block_state5_pp0_stage0_iter2_ignore_call19();
void thread_ap_block_state5_pp0_stage0_iter2_ignore_call21();
void thread_ap_block_state5_pp0_stage0_iter2_ignore_call23();
void thread_ap_block_state5_pp0_stage0_iter2_ignore_call25();
void thread_ap_block_state5_pp0_stage0_iter2_ignore_call27();
void thread_ap_block_state5_pp0_stage0_iter2_ignore_call29();
void thread_ap_block_state5_pp0_stage0_iter2_ignore_call3();
void thread_ap_block_state5_pp0_stage0_iter2_ignore_call31();
void thread_ap_block_state5_pp0_stage0_iter2_ignore_call33();
void thread_ap_block_state5_pp0_stage0_iter2_ignore_call35();
void thread_ap_block_state5_pp0_stage0_iter2_ignore_call37();
void thread_ap_block_state5_pp0_stage0_iter2_ignore_call39();
void thread_ap_block_state5_pp0_stage0_iter2_ignore_call41();
void thread_ap_block_state5_pp0_stage0_iter2_ignore_call43();
void thread_ap_block_state5_pp0_stage0_iter2_ignore_call45();
void thread_ap_block_state5_pp0_stage0_iter2_ignore_call47();
void thread_ap_block_state5_pp0_stage0_iter2_ignore_call49();
void thread_ap_block_state5_pp0_stage0_iter2_ignore_call5();
void thread_ap_block_state5_pp0_stage0_iter2_ignore_call51();
void thread_ap_block_state5_pp0_stage0_iter2_ignore_call53();
void thread_ap_block_state5_pp0_stage0_iter2_ignore_call55();
void thread_ap_block_state5_pp0_stage0_iter2_ignore_call57();
void thread_ap_block_state5_pp0_stage0_iter2_ignore_call59();
void thread_ap_block_state5_pp0_stage0_iter2_ignore_call61();
void thread_ap_block_state5_pp0_stage0_iter2_ignore_call63();
void thread_ap_block_state5_pp0_stage0_iter2_ignore_call65();
void thread_ap_block_state5_pp0_stage0_iter2_ignore_call67();
void thread_ap_block_state5_pp0_stage0_iter2_ignore_call69();
void thread_ap_block_state5_pp0_stage0_iter2_ignore_call7();
void thread_ap_block_state5_pp0_stage0_iter2_ignore_call71();
void thread_ap_block_state5_pp0_stage0_iter2_ignore_call73();
void thread_ap_block_state5_pp0_stage0_iter2_ignore_call75();
void thread_ap_block_state5_pp0_stage0_iter2_ignore_call77();
void thread_ap_block_state5_pp0_stage0_iter2_ignore_call79();
void thread_ap_block_state5_pp0_stage0_iter2_ignore_call81();
void thread_ap_block_state5_pp0_stage0_iter2_ignore_call83();
void thread_ap_block_state5_pp0_stage0_iter2_ignore_call85();
void thread_ap_block_state5_pp0_stage0_iter2_ignore_call87();
void thread_ap_block_state5_pp0_stage0_iter2_ignore_call89();
void thread_ap_block_state5_pp0_stage0_iter2_ignore_call9();
void thread_ap_block_state5_pp0_stage0_iter2_ignore_call91();
void thread_ap_block_state5_pp0_stage0_iter2_ignore_call93();
void thread_ap_block_state5_pp0_stage0_iter2_ignore_call95();
void thread_ap_block_state6_pp0_stage0_iter3();
void thread_ap_block_state6_pp0_stage0_iter3_ignore_call1();
void thread_ap_block_state6_pp0_stage0_iter3_ignore_call11();
void thread_ap_block_state6_pp0_stage0_iter3_ignore_call13();
void thread_ap_block_state6_pp0_stage0_iter3_ignore_call15();
void thread_ap_block_state6_pp0_stage0_iter3_ignore_call17();
void thread_ap_block_state6_pp0_stage0_iter3_ignore_call19();
void thread_ap_block_state6_pp0_stage0_iter3_ignore_call21();
void thread_ap_block_state6_pp0_stage0_iter3_ignore_call23();
void thread_ap_block_state6_pp0_stage0_iter3_ignore_call25();
void thread_ap_block_state6_pp0_stage0_iter3_ignore_call27();
void thread_ap_block_state6_pp0_stage0_iter3_ignore_call29();
void thread_ap_block_state6_pp0_stage0_iter3_ignore_call3();
void thread_ap_block_state6_pp0_stage0_iter3_ignore_call31();
void thread_ap_block_state6_pp0_stage0_iter3_ignore_call33();
void thread_ap_block_state6_pp0_stage0_iter3_ignore_call35();
void thread_ap_block_state6_pp0_stage0_iter3_ignore_call37();
void thread_ap_block_state6_pp0_stage0_iter3_ignore_call39();
void thread_ap_block_state6_pp0_stage0_iter3_ignore_call41();
void thread_ap_block_state6_pp0_stage0_iter3_ignore_call43();
void thread_ap_block_state6_pp0_stage0_iter3_ignore_call45();
void thread_ap_block_state6_pp0_stage0_iter3_ignore_call47();
void thread_ap_block_state6_pp0_stage0_iter3_ignore_call49();
void thread_ap_block_state6_pp0_stage0_iter3_ignore_call5();
void thread_ap_block_state6_pp0_stage0_iter3_ignore_call51();
void thread_ap_block_state6_pp0_stage0_iter3_ignore_call53();
void thread_ap_block_state6_pp0_stage0_iter3_ignore_call55();
void thread_ap_block_state6_pp0_stage0_iter3_ignore_call57();
void thread_ap_block_state6_pp0_stage0_iter3_ignore_call59();
void thread_ap_block_state6_pp0_stage0_iter3_ignore_call61();
void thread_ap_block_state6_pp0_stage0_iter3_ignore_call63();
void thread_ap_block_state6_pp0_stage0_iter3_ignore_call65();
void thread_ap_block_state6_pp0_stage0_iter3_ignore_call67();
void thread_ap_block_state6_pp0_stage0_iter3_ignore_call69();
void thread_ap_block_state6_pp0_stage0_iter3_ignore_call7();
void thread_ap_block_state6_pp0_stage0_iter3_ignore_call71();
void thread_ap_block_state6_pp0_stage0_iter3_ignore_call73();
void thread_ap_block_state6_pp0_stage0_iter3_ignore_call75();
void thread_ap_block_state6_pp0_stage0_iter3_ignore_call77();
void thread_ap_block_state6_pp0_stage0_iter3_ignore_call79();
void thread_ap_block_state6_pp0_stage0_iter3_ignore_call81();
void thread_ap_block_state6_pp0_stage0_iter3_ignore_call83();
void thread_ap_block_state6_pp0_stage0_iter3_ignore_call85();
void thread_ap_block_state6_pp0_stage0_iter3_ignore_call87();
void thread_ap_block_state6_pp0_stage0_iter3_ignore_call89();
void thread_ap_block_state6_pp0_stage0_iter3_ignore_call9();
void thread_ap_block_state6_pp0_stage0_iter3_ignore_call91();
void thread_ap_block_state6_pp0_stage0_iter3_ignore_call93();
void thread_ap_block_state6_pp0_stage0_iter3_ignore_call95();
void thread_ap_block_state7_pp0_stage0_iter4();
void thread_ap_block_state7_pp0_stage0_iter4_ignore_call1();
void thread_ap_block_state7_pp0_stage0_iter4_ignore_call11();
void thread_ap_block_state7_pp0_stage0_iter4_ignore_call13();
void thread_ap_block_state7_pp0_stage0_iter4_ignore_call15();
void thread_ap_block_state7_pp0_stage0_iter4_ignore_call17();
void thread_ap_block_state7_pp0_stage0_iter4_ignore_call19();
void thread_ap_block_state7_pp0_stage0_iter4_ignore_call21();
void thread_ap_block_state7_pp0_stage0_iter4_ignore_call23();
void thread_ap_block_state7_pp0_stage0_iter4_ignore_call25();
void thread_ap_block_state7_pp0_stage0_iter4_ignore_call27();
void thread_ap_block_state7_pp0_stage0_iter4_ignore_call29();
void thread_ap_block_state7_pp0_stage0_iter4_ignore_call3();
void thread_ap_block_state7_pp0_stage0_iter4_ignore_call31();
void thread_ap_block_state7_pp0_stage0_iter4_ignore_call33();
void thread_ap_block_state7_pp0_stage0_iter4_ignore_call35();
void thread_ap_block_state7_pp0_stage0_iter4_ignore_call37();
void thread_ap_block_state7_pp0_stage0_iter4_ignore_call39();
void thread_ap_block_state7_pp0_stage0_iter4_ignore_call41();
void thread_ap_block_state7_pp0_stage0_iter4_ignore_call43();
void thread_ap_block_state7_pp0_stage0_iter4_ignore_call45();
void thread_ap_block_state7_pp0_stage0_iter4_ignore_call47();
void thread_ap_block_state7_pp0_stage0_iter4_ignore_call49();
void thread_ap_block_state7_pp0_stage0_iter4_ignore_call5();
void thread_ap_block_state7_pp0_stage0_iter4_ignore_call51();
void thread_ap_block_state7_pp0_stage0_iter4_ignore_call53();
void thread_ap_block_state7_pp0_stage0_iter4_ignore_call55();
void thread_ap_block_state7_pp0_stage0_iter4_ignore_call57();
void thread_ap_block_state7_pp0_stage0_iter4_ignore_call59();
void thread_ap_block_state7_pp0_stage0_iter4_ignore_call61();
void thread_ap_block_state7_pp0_stage0_iter4_ignore_call63();
void thread_ap_block_state7_pp0_stage0_iter4_ignore_call65();
void thread_ap_block_state7_pp0_stage0_iter4_ignore_call67();
void thread_ap_block_state7_pp0_stage0_iter4_ignore_call69();
void thread_ap_block_state7_pp0_stage0_iter4_ignore_call7();
void thread_ap_block_state7_pp0_stage0_iter4_ignore_call71();
void thread_ap_block_state7_pp0_stage0_iter4_ignore_call73();
void thread_ap_block_state7_pp0_stage0_iter4_ignore_call75();
void thread_ap_block_state7_pp0_stage0_iter4_ignore_call77();
void thread_ap_block_state7_pp0_stage0_iter4_ignore_call79();
void thread_ap_block_state7_pp0_stage0_iter4_ignore_call81();
void thread_ap_block_state7_pp0_stage0_iter4_ignore_call83();
void thread_ap_block_state7_pp0_stage0_iter4_ignore_call85();
void thread_ap_block_state7_pp0_stage0_iter4_ignore_call87();
void thread_ap_block_state7_pp0_stage0_iter4_ignore_call89();
void thread_ap_block_state7_pp0_stage0_iter4_ignore_call9();
void thread_ap_block_state7_pp0_stage0_iter4_ignore_call91();
void thread_ap_block_state7_pp0_stage0_iter4_ignore_call93();
void thread_ap_block_state7_pp0_stage0_iter4_ignore_call95();
void thread_ap_block_state8_pp0_stage0_iter5();
void thread_ap_block_state8_pp0_stage0_iter5_ignore_call1();
void thread_ap_block_state8_pp0_stage0_iter5_ignore_call11();
void thread_ap_block_state8_pp0_stage0_iter5_ignore_call13();
void thread_ap_block_state8_pp0_stage0_iter5_ignore_call15();
void thread_ap_block_state8_pp0_stage0_iter5_ignore_call17();
void thread_ap_block_state8_pp0_stage0_iter5_ignore_call19();
void thread_ap_block_state8_pp0_stage0_iter5_ignore_call21();
void thread_ap_block_state8_pp0_stage0_iter5_ignore_call23();
void thread_ap_block_state8_pp0_stage0_iter5_ignore_call25();
void thread_ap_block_state8_pp0_stage0_iter5_ignore_call27();
void thread_ap_block_state8_pp0_stage0_iter5_ignore_call29();
void thread_ap_block_state8_pp0_stage0_iter5_ignore_call3();
void thread_ap_block_state8_pp0_stage0_iter5_ignore_call31();
void thread_ap_block_state8_pp0_stage0_iter5_ignore_call33();
void thread_ap_block_state8_pp0_stage0_iter5_ignore_call35();
void thread_ap_block_state8_pp0_stage0_iter5_ignore_call37();
void thread_ap_block_state8_pp0_stage0_iter5_ignore_call39();
void thread_ap_block_state8_pp0_stage0_iter5_ignore_call41();
void thread_ap_block_state8_pp0_stage0_iter5_ignore_call43();
void thread_ap_block_state8_pp0_stage0_iter5_ignore_call45();
void thread_ap_block_state8_pp0_stage0_iter5_ignore_call47();
void thread_ap_block_state8_pp0_stage0_iter5_ignore_call49();
void thread_ap_block_state8_pp0_stage0_iter5_ignore_call5();
void thread_ap_block_state8_pp0_stage0_iter5_ignore_call51();
void thread_ap_block_state8_pp0_stage0_iter5_ignore_call53();
void thread_ap_block_state8_pp0_stage0_iter5_ignore_call55();
void thread_ap_block_state8_pp0_stage0_iter5_ignore_call57();
void thread_ap_block_state8_pp0_stage0_iter5_ignore_call59();
void thread_ap_block_state8_pp0_stage0_iter5_ignore_call61();
void thread_ap_block_state8_pp0_stage0_iter5_ignore_call63();
void thread_ap_block_state8_pp0_stage0_iter5_ignore_call65();
void thread_ap_block_state8_pp0_stage0_iter5_ignore_call67();
void thread_ap_block_state8_pp0_stage0_iter5_ignore_call69();
void thread_ap_block_state8_pp0_stage0_iter5_ignore_call7();
void thread_ap_block_state8_pp0_stage0_iter5_ignore_call71();
void thread_ap_block_state8_pp0_stage0_iter5_ignore_call73();
void thread_ap_block_state8_pp0_stage0_iter5_ignore_call75();
void thread_ap_block_state8_pp0_stage0_iter5_ignore_call77();
void thread_ap_block_state8_pp0_stage0_iter5_ignore_call79();
void thread_ap_block_state8_pp0_stage0_iter5_ignore_call81();
void thread_ap_block_state8_pp0_stage0_iter5_ignore_call83();
void thread_ap_block_state8_pp0_stage0_iter5_ignore_call85();
void thread_ap_block_state8_pp0_stage0_iter5_ignore_call87();
void thread_ap_block_state8_pp0_stage0_iter5_ignore_call89();
void thread_ap_block_state8_pp0_stage0_iter5_ignore_call9();
void thread_ap_block_state8_pp0_stage0_iter5_ignore_call91();
void thread_ap_block_state8_pp0_stage0_iter5_ignore_call93();
void thread_ap_block_state8_pp0_stage0_iter5_ignore_call95();
void thread_ap_block_state9_pp0_stage0_iter6();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call1();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call11();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call13();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call15();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call17();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call19();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call21();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call23();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call25();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call27();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call29();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call3();
void thread_ap_block_st
|
ate9_pp0_stage0_iter6_ignore_call31();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call33();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call35();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call37();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call39();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call41();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call43();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call45();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call47();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call49();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call5();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call51();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call53();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call55();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call57();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call59();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call61();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call63();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call65();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call67();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call69();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call7();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call71();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call73();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call75();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call77();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call79();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call81();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call83();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call85();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call87();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call89();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call9();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call91();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call93();
void thread_ap_block_state9_pp0_stage0_iter6_ignore_call95();
void thread_ap_condition_2362();
void thread_ap_condition_pp0_exit_iter1_state4();
void thread_ap_done();
void thread_ap_enable_pp0();
void thread_ap_idle();
void thread_ap_idle_pp0();
void thread_ap_phi_mux_core_1_phi_fu_568_p8();
void thread_ap_phi_reg_pp0_iter0_core_1_reg_564();
void thread_ap_predicate_op181_read_state4();
void thread_ap_predicate_op562_call_state6();
void thread_ap_predicate_op564_call_state6();
void thread_ap_predicate_op566_call_state6();
void thread_ap_predicate_op568_call_state6();
void thread_ap_predicate_op570_call_state6();
void thread_ap_predicate_op572_call_state6();
void thread_ap_predicate_op574_call_state6();
void thread_ap_predicate_op576_call_state6();
void thread_ap_predicate_op578_call_state6();
void thread_ap_predicate_op580_call_state6();
void thread_ap_predicate_op582_call_state6();
void thread_ap_predicate_op584_call_state6();
void thread_ap_predicate_op602_call_state7();
void thread_ap_predicate_op604_call_state7();
void thread_ap_predicate_op606_call_state7();
void thread_ap_predicate_op608_call_state7();
void thread_ap_predicate_op610_call_state7();
void thread_ap_predicate_op612_call_state7();
void thread_ap_predicate_op614_call_state7();
void thread_ap_predicate_op616_call_state7();
void thread_ap_predicate_op618_call_state7();
void thread_ap_predicate_op620_call_state7();
void thread_ap_predicate_op622_call_state7();
void thread_ap_predicate_op624_call_state7();
void thread_ap_predicate_op626_call_state7();
void thread_ap_predicate_op628_call_state7();
void thread_ap_predicate_op644_call_state8();
void thread_ap_predicate_op646_call_state8();
void thread_ap_predicate_op648_call_state8();
void thread_ap_predicate_op650_call_state8();
void thread_ap_predicate_op652_call_state8();
void thread_ap_predicate_op654_call_state8();
void thread_ap_predicate_op656_call_state8();
void thread_ap_predicate_op658_call_state8();
void thread_ap_predicate_op660_call_state8();
void thread_ap_predicate_op662_call_state8();
void thread_ap_predicate_op664_call_state8();
void thread_ap_predicate_op666_call_state8();
void thread_ap_predicate_op680_call_state9();
void thread_ap_predicate_op682_call_state9();
void thread_ap_predicate_op684_call_state9();
void thread_ap_predicate_op686_call_state9();
void thread_ap_predicate_op688_call_state9();
void thread_ap_predicate_op690_call_state9();
void thread_ap_predicate_op723_call_state10();
void thread_ap_predicate_op724_call_state10();
void thread_ap_predicate_op725_call_state10();
void thread_ap_predicate_op726_call_state10();
void thread_ap_ready();
void thread_core_buf_val_0_V_address0();
void thread_core_buf_val_0_V_ce0();
void thread_core_buf_val_0_V_ce1();
void thread_core_buf_val_0_V_we1();
void thread_core_buf_val_1_V_address0();
void thread_core_buf_val_1_V_ce0();
void thread_core_buf_val_1_V_ce1();
void thread_core_buf_val_1_V_we1();
void thread_core_win_val_2_V_2_fu_4112_p3();
void thread_count_1_fu_3105_p2();
void thread_count_1_i_0_op_op_fu_2757_p3();
void thread_count_1_i_10_fu_3416_p3();
void thread_count_1_i_11_fu_3445_p3();
void thread_count_1_i_12_fu_3486_p3();
void thread_count_1_i_13_fu_3515_p3();
void thread_count_1_i_14_fu_3556_p3();
void thread_count_1_i_15_fu_3585_p3();
void thread_count_1_i_1_fu_3079_p3();
void thread_count_1_i_2_fu_3141_p3();
void thread_count_1_i_2_op_op_fu_2779_p3();
void thread_count_1_i_3_cast_fu_3313_p1();
void thread_count_1_i_3_fu_3306_p3();
void thread_count_1_i_4_fu_3355_p3();
void thread_count_1_i_4_op_fu_2801_p3();
void thread_count_1_i_5_fu_3380_p3();
void thread_count_1_i_6_fu_2823_p3();
void thread_count_1_i_7_fu_2867_p3();
void thread_count_1_i_8_fu_2917_p3();
void thread_count_1_i_9_fu_2967_p3();
void thread_count_1_i_s_fu_3029_p3();
void thread_count_2_fu_3321_p2();
void thread_count_3_fu_3387_p2();
void thread_count_4_fu_3452_p2();
void thread_count_5_fu_3522_p2();
void thread_count_6_fu_3592_p2();
void thread_count_8_fu_2887_p2();
void thread_count_s_fu_2993_p2();
void thread_exitcond3_fu_1315_p2();
void thread_exitcond4_fu_1367_p2();
void thread_flag_d_assign_10_fu_3241_p1();
void thread_flag_d_assign_11_fu_3251_p1();
void thread_flag_d_assign_12_fu_3261_p1();
void thread_flag_d_assign_13_fu_3798_p1();
void thread_flag_d_assign_14_fu_3803_p1();
void thread_flag_d_assign_15_fu_3808_p1();
void thread_flag_d_assign_1_fu_3226_p1();
void thread_flag_d_assign_2_fu_3236_p1();
void thread_flag_d_assign_3_fu_3246_p1();
void thread_flag_d_assign_4_fu_3256_p1();
void thread_flag_d_assign_5_fu_3266_p1();
void thread_flag_d_assign_6_fu_3271_p1();
void thread_flag_d_assign_7_fu_3276_p1();
void thread_flag_d_assign_8_fu_3221_p1();
void thread_flag_d_assign_9_fu_3231_p1();
void thread_flag_d_assign_s_fu_3793_p1();
void thread_flag_val_V_assign_lo_10_fu_2447_p3();
void thread_flag_val_V_assign_lo_11_fu_2501_p3();
void thread_flag_val_V_assign_lo_12_fu_2535_p3();
void thread_flag_val_V_assign_lo_13_fu_2589_p3();
void thread_flag_val_V_assign_lo_14_fu_2623_p3();
void thread_flag_val_V_assign_lo_15_fu_2413_p3();
void thread_flag_val_V_assign_lo_1_fu_2007_p3();
void thread_flag_val_V_assign_lo_2_fu_2061_p3();
void thread_flag_val_V_assign_lo_3_fu_2095_p3();
void thread_flag_val_V_assign_lo_4_fu_2149_p3();
void thread_flag_val_V_assign_lo_5_fu_2183_p3();
void thread_flag_val_V_assign_lo_6_fu_2237_p3();
void thread_flag_val_V_assign_lo_7_fu_2271_p3();
void thread_flag_val_V_assign_lo_8_fu_2325_p3();
void thread_flag_val_V_assign_lo_9_fu_2359_p3();
void thread_flag_val_V_assign_lo_fu_1973_p3();
void thread_grp_reg_int_s_fu_3701_ap_ce();
void thread_grp_reg_int_s_fu_3708_ap_ce();
void thread_grp_reg_int_s_fu_3715_ap_ce();
void thread_grp_reg_int_s_fu_3723_ap_ce();
void thread_grp_reg_int_s_fu_3731_ap_ce();
void thread_grp_reg_int_s_fu_3739_ap_ce();
void thread_grp_reg_int_s_fu_3747_ap_ce();
void thread_grp_reg_int_s_fu_3755_ap_ce();
void thread_grp_reg_int_s_fu_3763_ap_ce();
void thread_grp_reg_int_s_fu_3771_ap_ce();
void thread_grp_reg_int_s_fu_3779_ap_ce();
void thread_grp_reg_int_s_fu_3786_ap_ce();
void thread_grp_reg_int_s_fu_3813_ap_ce();
void thread_grp_reg_int_s_fu_3821_ap_ce();
void thread_grp_reg_int_s_fu_3829_ap_ce();
void thread_grp_reg_int_s_fu_3837_ap_ce();
void thread_grp_reg_int_s_fu_3845_ap_ce();
void thread_grp_reg_int_s_fu_3852_ap_ce();
void thread_grp_reg_int_s_fu_3859_ap_ce();
void thread_grp_reg_int_s_fu_3866_ap_ce();
void thread_grp_reg_int_s_fu_3873_ap_ce();
void thread_grp_reg_int_s_fu_3881_ap_ce();
void thread_grp_reg_int_s_fu_3889_ap_ce();
void thread_grp_reg_int_s_fu_3896_ap_ce();
void thread_grp_reg_int_s_fu_3903_ap_ce();
void thread_grp_reg_int_s_fu_3910_ap_ce();
void thread_grp_reg_int_s_fu_3917_ap_ce();
void thread_grp_reg_int_s_fu_3925_ap_ce();
void thread_grp_reg_int_s_fu_3933_ap_ce();
void thread_grp_reg_int_s_fu_3941_ap_ce();
void thread_grp_reg_int_s_fu_3949_ap_ce();
void thread_grp_reg_int_s_fu_3957_ap_ce();
void thread_grp_reg_int_s_fu_3965_ap_ce();
void thread_grp_reg_int_s_fu_3973_ap_ce();
void thread_grp_reg_int_s_fu_3981_ap_ce();
void thread_grp_reg_int_s_fu_3989_ap_ce();
void thread_grp_reg_int_s_fu_3997_ap_ce();
void thread_grp_reg_int_s_fu_4005_ap_ce();
void thread_grp_reg_int_s_fu_4013_ap_ce();
void thread_grp_reg_int_s_fu_4021_ap_ce();
void thread_grp_reg_int_s_fu_4029_ap_ce();
void thread_grp_reg_int_s_fu_4037_ap_ce();
void thread_grp_reg_int_s_fu_4045_ap_ce();
void thread_grp_reg_int_s_fu_4053_ap_ce();
void thread_grp_reg_int_s_fu_4061_ap_ce();
void thread_grp_reg_int_s_fu_4068_ap_ce();
void thread_grp_reg_int_s_fu_4075_ap_ce();
void thread_grp_reg_int_s_fu_4082_ap_ce();
void thread_i_V_fu_1321_p2();
void thread_icmp1_fu_1442_p2();
void thread_icmp_fu_1361_p2();
void thread_internal_ap_ready();
void thread_iscorner_2_i_7_fu_2861_p2();
void thread_iscorner_2_i_s_fu_3695_p2();
void thread_j_V_fu_1373_p2();
void thread_k_buf_val_0_V_address0();
void thread_k_buf_val_0_V_ce0();
void thread_k_buf_val_0_V_ce1();
void thread_k_buf_val_0_V_we1();
void thread_k_buf_val_1_V_address0();
void thread_k_buf_val_1_V_ce0();
void thread_k_buf_val_1_V_ce1();
void thread_k_buf_val_1_V_we1();
void thread_k_buf_val_2_V_address0();
void thread_k_buf_val_2_V_ce0();
void thread_k_buf_val_2_V_ce1();
void thread_k_buf_val_2_V_we1();
void thread_k_buf_val_3_V_address0();
void thread_k_buf_val_3_V_ce0();
void thread_k_buf_val_3_V_ce1();
void thread_k_buf_val_3_V_we1();
void thread_k_buf_val_4_V_address0();
void thread_k_buf_val_4_V_ce0();
void thread_k_buf_val_4_V_ce1();
void thread_k_buf_val_4_V_we1();
void thread_k_buf_val_5_V_address0();
void thread_k_buf_val_5_V_ce0();
void thread_k_buf_val_5_V_ce1();
void thread_k_buf_val_5_V_we1();
void thread_lhs_V_fu_1923_p1();
void thread_not_or_cond10_demorg_fu_3569_p2();
void thread_not_or_cond10_fu_3573_p2();
void thread_not_or_cond11_demorg_fu_3185_p2();
void thread_not_or_cond11_fu_3191_p2();
void thread_not_or_cond12_demorg_fu_3123_p2();
void thread_not_or_cond12_fu_3129_p2();
void thread_not_or_cond13_demorg_fu_3290_p2();
void thread_not_or_cond13_fu_3294_p2();
void thread_not_or_cond14_demorg_fu_3339_p2();
void thread_not_or_cond14_fu_3343_p2();
void thread_not_or_cond15_fu_3369_p2();
void thread_not_or_cond1_fu_2905_p2();
void thread_not_or_cond2_demorga_fu_2949_p2();
void thread_not_or_cond2_fu_2955_p2();
void thread_not_or_cond3_demorga_fu_3011_p2();
void thread_not_or_cond3_fu_3017_p2();
void thread_not_or_cond4_demorga_fu_3061_p2();
void thread_not_or_cond4_fu_3067_p2();
void thread_not_or_cond5_fu_3405_p2();
void thread_not_or_cond6_demorga_fu_3429_p2();
void thread_not_or_cond6_fu_3433_p2();
void thread_not_or_cond7_demorga_fu_3470_p2();
void thread_not_or_cond7_fu_3474_p2();
void thread_not_or_cond8_demorga_fu_3499_p2();
void thread_not_or_cond8_fu_3503_p2();
void thread_not_or_cond9_demorga_fu_3540_p2();
void thread_not_or_cond9_fu_3544_p2();
void thread_not_or_cond_fu_2855_p2();
void thread_or_cond10_fu_2843_p2();
void thread_or_cond11_fu_2881_p2();
void thread_or_cond12_fu_2937_p2();
void thread_or_cond13_fu_2987_p2();
void thread_or_cond14_fu_3049_p2();
void thread_or_cond15_fu_3099_p2();
void thread_or_cond16_fu_3281_p2();
void thread_or_cond17_fu_3317_p2();
void thread_or_cond18_fu_3179_p2();
void thread_or_cond1_fu_1339_p2();
void thread_or_cond2_fu_2733_p2();
void thread_or_cond3_fu_2751_p2();
void thread_or_cond4_fu_1448_p2();
void thread_or_cond5_fu_2643_p2();
void thread_or_cond6_fu_2661_p2();
void thread_or_cond7_fu_2679_p2();
void thread_or_cond8_fu_2697_p2();
void thread_or_cond9_fu_2715_p2();
void thread_or_cond_fu_1393_p2();
void thread_p_iscorner_0_i_10_fu_3480_p2();
void thread_p_iscorner_0_i_11_fu_3509_p2();
void thread_p_iscorner_0_i_12_fu_3550_p2();
void thread_p_iscorner_0_i_13_fu_3579_p2();
void thread_p_iscorner_0_i_14_fu_3610_p2();
void thread_p_iscorner_0_i_15_fu_3625_p2();
void thread_p_iscorner_0_i_1_fu_3073_p2();
void thread_p_iscorner_0_i_2_fu_3135_p2();
void thread_p_iscorner_0_i_3_fu_3300_p2();
void thread_p_iscorner_0_i_4_fu_3349_p2();
void thread_p_iscorner_0_i_5_fu_3374_p2();
void thread_p_iscorner_0_i_6_fu_3410_p2();
void thread_p_iscorner_0_i_7_fu_3439_p2();
void thread_p_iscorner_0_i_8_fu_2911_p2();
void thread_p_iscorner_0_i_9_fu_2961_p2();
void thread_p_iscorner_0_i_s_fu_3023_p2();
void thread_p_mask_data_stream_V_blk_n();
void thread_p_mask_data_stream_V_din();
void thread_p_mask_data_stream_V_write();
void thread_p_src_data_stream_V_blk_n();
void thread_p_src_data_stream_V_read();
void thread_phitmp1_cast_cast_ca_fu_2809_p3();
void thread_phitmp1_i_i_1_fu_2081_p3();
void thread_phitmp1_i_i_2_fu_2169_p3();
void thread_phitmp1_i_i_3_fu_2257_p3();
void thread_phitmp1_i_i_4_fu_2345_p3();
void thread_phitmp1_i_i_5_fu_2433_p3();
void thread_phitmp1_i_i_6_fu_2521_p3();
void thread_phitmp1_i_i_7_fu_2609_p3();
void thread_phitmp1_i_i_fu_1993_p3();
void thread_phitmp2_fu_2899_p2();
void thread_phitmp3_fu_3005_p2();
void thread_phitmp41_op_cast_cas_fu_2787_p3();
void thread_phitmp42_op_op_cast_s_fu_2765_p3();
void thread_phitmp4_fu_3117_p2();
void thread_phitmp5_fu_3333_p2();
void thread_phitmp6_fu_3399_p2();
void thread_phitmp7_fu_3464_p2();
void thread_phitmp8_fu_3534_p2();
void thread_phitmp9_fu_3604_p2();
void thread_phitmp_fu_4099_p2();
void thread_phitmp_i_i_1_fu_2047_p3();
void thread_phitmp_i_i_2_fu_2135_p3();
void thread_phitmp_i_i_3_fu_2223_p3();
void thread_phitmp_i_i_4_fu_2311_p3();
void thread_phitmp_i_i_5_fu_2399_p3();
void thread_phitmp_i_i_6_fu_2487_p3();
void thread_phitmp_i_i_7_fu_2575_p3();
void thread_phitmp_i_i_fu_1959_p3();
void thread_real_start();
void thread_ret_V_1_1_fu_2029_p2();
void thread_ret_V_1_2_fu_2117_p2();
void thread_ret_V_1_3_fu_2205_p2();
void thread_ret_V_1_4_fu_2293_p2();
void thread_ret_V_1_5_fu_2381_p2();
void thread_ret_V_1_6_fu_2469_p2();
void thread_ret_V_1_7_fu_2557_p2();
void thread_ret_V_1_fu_1941_p2();
void thread_ret_V_2_fu_2107_p2();
void thread_ret_V_3_fu_2195_p2();
void thread_ret_V_4_fu_2283_p2();
void thread_ret_V_5_fu_2371_p2();
void thread_ret_V_6_fu_2459_p2();
void thread_ret_V_7_fu_2547_p2();
void thread_ret_V_fu_1931_p2();
void thread_ret_V_s_fu_2019_p2();
void thread_rev_fu_1387_p2();
void thread_rhs_V_1_1_fu_2025_p1();
void thread_rhs_V_1_2_fu_2113_p1();
void thread_rhs_V_1_3_fu_2201_p1();
void thread_rhs_V_1_4_fu_2289_p1();
void thread_rhs_V_1_5_fu_2377_p1();
void thread_rhs_V_1_6_fu_2465_p1();
void thread_rhs_V_1_7_fu_2553_p1();
void thread_rhs_V_1_fu_1937_p1();
void thread_rhs_V_2_fu_2103_p1();
void thread_rhs_V_3_fu_2191_p1();
void thread_rhs_V_4_fu_2279_p1();
void thread_rhs_V_5_fu_2367_p1();
void thread_rhs_V_6_fu_2455_p1();
void thread_rhs_V_7_fu_2543_p1();
void thread_rhs_V_fu_1927_p1();
void thread_rhs_V_s_fu_2015_p1();
void thread_start_out();
void thread_start_write();
void thread_tmp10_fu_3215_p2();
void thread_tmp11_fu_3631_p2();
void thread_tmp12_fu_3689_p2();
void thread_tmp13_fu_3659_p2();
void thread_tmp14_fu_3647_p2();
void thread_tmp15_fu_3653_p2();
void thread_tmp16_fu_3683_p2();
void thread_tmp17_fu_3665_p2();
void thread_tmp18_fu_3677_p2();
void thread_tmp19_fu_3671_p2();
void thread_tmp20_fu_1840_p2();
void thread_tmp21_fu_1824_p2();
void thread_tmp22_fu_1835_p2();
void thread_tmp23_fu_1829_p2();
void thread_tmp24_fu_4156_p2();
void thread_tmp25_fu_4141_p2();
void thread_tmp26_fu_4135_p2();
void thread_tmp27_fu_4150_p2();
void thread_tmp28_fu_4146_p2();
void thread_tmp4_fu_3621_p2();
void thread_tmp5_fu_3642_p2();
void thread_tmp6_fu_3209_p2();
void thread_tmp7_fu_3197_p2();
void thread_tmp8_fu_3203_p2();
void thread_tmp9_fu_3637_p2();
void thread_tmp_10_max_int_s_fu_1309_y();
void thread_tmp_115_1_fu_1800_p2();
void thread_tmp_115_2_fu_1806_p2();
void thread_tmp_118_1_fu_4125_p2();
void thread_tmp_118_2_fu_4130_p2();
void thread_tmp_11_fu_1788_p2();
void thread_tmp_12_fu_1426_p2();
void thread_tmp_13_fu_1812_p2();
void thread_tmp_14_fu_1818_p2();
void thread_tmp_15_fu_1947_p2();
void thread_tmp_16_fu_1953_p2();
void thread_tmp_17_fu_1967_p2();
void thread_tmp_18_fu_1981_p2();
void thread_tmp_19_fu_1987_p2();
void thread_tmp_1_fu_1333_p2();
void thread_tmp_20_fu_2001_p2();
void thread_tmp_21_fu_2055_p2();
void thread_tmp_22_fu_2089_p2();
void thread_tmp_23_fu_2637_p2();
void thread_tmp_24_fu_2773_p2();
void thread_tmp_25_fu_2795_p2();
void thread_tmp_26_fu_2817_p2();
void thread_tmp_28_fu_1351_p4();
void thread_tmp_2_fu_1345_p2();
void thread_tmp_32_fu_1379_p3();
void thread_tmp_33_fu_1794_p2();
void thread_tmp_34_fu_4120_p2();
void thread_tmp_36_fu_4162_p2();
void thread_tmp_37_fu_2143_p2();
void thread_tmp_38_fu_2177_p2();
void thread_tmp_39_fu_2231_p2();
void thread_tmp_40_fu_2265_p2();
void thread_tmp_41_fu_2319_p2();
void thread_tmp_42_fu_2353_p2();
void thread_tmp_43_fu_2407_p2();
void thread_tmp_44_fu_2441_p2();
void thread_tmp_45_fu_2495_p2();
void thread_tmp_46_fu_2529_p2();
void thread_tmp_47_fu_2583_p2();
void thread_tmp_48_fu_2617_p2();
void thread_tmp_49_fu_4095_p1();
void thread_tmp_50_fu_1432_p4();
void thread_tmp_5_fu_1398_p1();
void thread_tmp_64_1_fu_2035_p2();
void thread_tmp_64_2_fu_
|
2123_p2();
void thread_tmp_64_3_fu_2211_p2();
void thread_tmp_64_4_fu_2299_p2();
void thread_tmp_64_5_fu_2387_p2();
void thread_tmp_64_6_fu_2475_p2();
void thread_tmp_64_7_fu_2563_p2();
void thread_tmp_65_1_fu_2041_p2();
void thread_tmp_65_2_fu_2129_p2();
void thread_tmp_65_3_fu_2217_p2();
void thread_tmp_65_4_fu_2305_p2();
void thread_tmp_65_5_fu_2393_p2();
void thread_tmp_65_6_fu_2481_p2();
void thread_tmp_65_7_fu_2569_p2();
void thread_tmp_69_0_not_fu_2631_p2();
void thread_tmp_69_1_fu_3037_p2();
void thread_tmp_69_1_not_fu_2649_p2();
void thread_tmp_69_2_fu_3087_p2();
void thread_tmp_69_2_not_fu_2667_p2();
void thread_tmp_69_3_fu_3149_p2();
void thread_tmp_69_3_not_fu_2685_p2();
void thread_tmp_69_4_fu_3161_p2();
void thread_tmp_69_4_not_fu_2703_p2();
void thread_tmp_69_5_fu_3173_p2();
void thread_tmp_69_5_not_fu_2721_p2();
void thread_tmp_69_6_not_fu_2739_p2();
void thread_tmp_69_7_not_fu_2831_p2();
void thread_tmp_69_8_fu_2875_p2();
void thread_tmp_69_9_fu_2925_p2();
void thread_tmp_69_s_fu_2975_p2();
void thread_tmp_6_fu_1408_p1();
void thread_tmp_70_1_fu_2069_p2();
void thread_tmp_70_2_fu_2157_p2();
void thread_tmp_70_3_fu_2245_p2();
void thread_tmp_70_4_fu_2333_p2();
void thread_tmp_70_5_fu_2421_p2();
void thread_tmp_70_6_fu_2509_p2();
void thread_tmp_70_7_fu_2597_p2();
void thread_tmp_71_10_fu_3093_p2();
void thread_tmp_71_11_fu_3155_p2();
void thread_tmp_71_12_fu_3167_p2();
void thread_tmp_71_1_fu_2655_p2();
void thread_tmp_71_2_fu_2673_p2();
void thread_tmp_71_3_fu_2691_p2();
void thread_tmp_71_4_fu_2709_p2();
void thread_tmp_71_5_fu_2727_p2();
void thread_tmp_71_6_fu_2745_p2();
void thread_tmp_71_7_fu_2837_p2();
void thread_tmp_71_8_fu_3043_p2();
void thread_tmp_71_9_fu_2931_p2();
void thread_tmp_71_s_fu_2981_p2();
void thread_tmp_72_1_fu_2075_p2();
void thread_tmp_72_2_fu_2163_p2();
void thread_tmp_72_3_fu_2251_p2();
void thread_tmp_72_4_fu_2339_p2();
void thread_tmp_72_5_fu_2427_p2();
void thread_tmp_72_6_fu_2515_p2();
void thread_tmp_72_7_fu_2603_p2();
void thread_tmp_73_10_fu_3423_p2();
void thread_tmp_73_11_fu_3458_p2();
void thread_tmp_73_12_fu_3493_p2();
void thread_tmp_73_13_fu_3528_p2();
void thread_tmp_73_14_fu_3563_p2();
void thread_tmp_73_15_fu_3598_p2();
void thread_tmp_73_16_fu_3615_p2();
void thread_tmp_73_1_fu_3055_p2();
void thread_tmp_73_2_fu_3111_p2();
void thread_tmp_73_3_fu_3285_p2();
void thread_tmp_73_4_fu_3327_p2();
void thread_tmp_73_5_fu_3363_p2();
void thread_tmp_73_6_fu_3393_p2();
void thread_tmp_73_7_fu_2849_p2();
void thread_tmp_73_8_fu_2893_p2();
void thread_tmp_73_9_fu_2943_p2();
void thread_tmp_73_s_fu_2999_p2();
void thread_tmp_7_fu_1414_p2();
void thread_tmp_8_fu_1420_p2();
void thread_tmp_s_fu_1327_p2();
void thread_ap_NS_fsm();
};
}
using namespace ap_rtl;
#endif
|
/******************************************************************************
* *
* Copyright (C) 2022 MachineWare GmbH *
* All Rights Reserved *
* *
* This is work is licensed under the terms described in the LICENSE file *
* found in the root directory of this source tree. *
* *
******************************************************************************/
#ifndef VCML_OPENCORES_OCKBD_H
#define VCML_OPENCORES_OCKBD_H
#include "vcml/core/types.h"
#include "vcml/core/systemc.h"
#include "vcml/core/thctl.h"
#include "vcml/core/peripheral.h"
#include "vcml/core/model.h"
#include "vcml/ui/keymap.h"
#include "vcml/ui/console.h"
#include "vcml/properties/property.h"
#include "vcml/protocols/tlm.h"
#include "vcml/protocols/gpio.h"
namespace vcml {
namespace opencores {
class ockbd : public peripheral
{
private:
queue<u8> m_key_fifo;
ui::keyboard m_keyboard;
ui::console m_console;
void update();
void key_event(u32 key, u32 down);
u8 read_khr();
// disabled
ockbd();
ockbd(const ockbd&);
public:
reg<u8> khr;
gpio_initiator_socket irq;
tlm_target_socket in;
property<string> keymap;
property<size_t> fifosize;
ockbd(const sc_module_name& name);
virtual ~ockbd();
VCML_KIND(opencores::ockbd);
protected:
virtual void end_of_simulation() override;
};
} // namespace opencores
} // namespace vcml
#endif
|
//
// Copyright 2022 Sergey Khabarov, [email protected]
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
#pragma once
#include <systemc.h>
#include "../ambalib/types_amba.h"
#include "types_river.h"
#include "river_cfg.h"
namespace debugger {
SC_MODULE(DummyCpu) {
public:
sc_out<axi4_l1_out_type> o_msto;
sc_out<dport_out_type> o_dport;
sc_out<bool> o_flush_l2; // Flush L2 after D$ has been finished
sc_out<bool> o_halted; // CPU halted via debug interface
sc_out<bool> o_available; // CPU was instantitated of stubbed
void comb();
SC_HAS_PROCESS(DummyCpu);
DummyCpu(sc_module_name name);
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
};
} // namespace debugger
|
/************************************************/
// Copyright tlm_noc contributors.
// Author Mike
// SPDX-License-Identifier: Apache-2.0
/************************************************/
#ifndef __HOST_BASE_H__
#define __HOST_BASE_H__
#include <cstdlib>
#include <systemc.h>
#include <queue>
#include <tlm.h>
#include <tlm_utils/simple_initiator_socket.h>
#include "tlm_noc.h"
#include "noc_payload.h"
#include "dumpWave.h"
using namespace std;
using namespace tlm;
using namespace tlm_utils;;
class host_base: public sc_core::sc_module {
SC_HAS_PROCESS(host_base);
public:
// TLM interface
tlm_utils::simple_initiator_socket<host_base> m_port;
// Constructor
host_base(sc_core::sc_module_name name);
// Variables & functions
char sbuff[10000];
char signal[100];
void initiator(gp& trans);
uint8_t* wdata_ptr;
uint8_t* rdata_ptr;
private:
tlm_sync_enum mst_nb_transport_bw(gp& payload, tlm_phase& phase, sc_time& delay);
};
#endif
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.