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|
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// This module compares two bitstreams and automatically determines their
// offset. This is done by iteratively changing bit delay for I_DAT_REF
// every time the number of errors exceeds ERROR_COUNT. The output O_ERROR
// signal is high for at least ERROR_HOLD cycles.
`default_nettype none
// ============================================================================
module comparator #
(
parameter ERROR_COUNT = 8,
parameter ERROR_HOLD = 2500000
)
(
input wire CLK,
input wire RST,
input wire I_DAT_REF,
input wire I_DAT_IOB,
output wire O_ERROR
);
// ============================================================================
// Data latch
reg [2:0] i_dat_ref_sr;
reg [2:0] i_dat_iob_sr;
always @(posedge CLK)
i_dat_ref_sr <= (i_dat_ref_sr << 1) | I_DAT_REF;
always @(posedge CLK)
i_dat_iob_sr <= (i_dat_iob_sr << 1) | I_DAT_IOB;
wire i_dat_ref = i_dat_ref_sr[2];
wire i_dat_iob = i_dat_iob_sr[2];
// ============================================================================
// Shift register for reference data, shift strobe generator.
reg [31:0] sreg;
reg [ 4:0] sreg_sel;
wire sreg_dat;
reg sreg_sh;
always @(posedge CLK)
sreg <= (sreg << 1) | i_dat_ref;
always @(posedge CLK)
if (RST)
sreg_sel <= 0;
else if(sreg_sh)
sreg_sel <= sreg_sel + 1;
assign sreg_dat = sreg[sreg_sel];
// ============================================================================
// Comparator and error counter
wire cmp_err;
reg [31:0] err_cnt;
assign cmp_err = sreg_dat ^ i_dat_iob;
always @(posedge CLK)
if (RST)
err_cnt <= 0;
else if(sreg_sh)
err_cnt <= 0;
else if(cmp_err)
err_cnt <= err_cnt + 1;
always @(posedge CLK)
if (RST)
sreg_sh <= 0;
else if(~sreg_sh && (err_cnt == ERROR_COUNT))
sreg_sh <= 1;
else
sreg_sh <= 0;
// ============================================================================
// Output generator
reg [24:0] o_cnt;
always @(posedge CLK)
if (RST)
o_cnt <= -1;
else if (cmp_err)
o_cnt <= ERROR_HOLD - 2;
else if (~o_cnt[24])
o_cnt <= o_cnt - 1;
assign O_ERROR = !o_cnt[24];
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// [email protected] (c) Analog Devices Inc.
// ***************************************************************************
// ***************************************************************************
`timescale 1ps/1ps
module cf_add (
clk,
data_1,
data_2,
data_3,
data_4,
data_p,
ddata_in,
ddata_out);
parameter DELAY_DATA_WIDTH = 16;
parameter DW = DELAY_DATA_WIDTH - 1;
input clk;
input [24:0] data_1;
input [24:0] data_2;
input [24:0] data_3;
input [24:0] data_4;
output [ 7:0] data_p;
input [DW:0] ddata_in;
output [DW:0] ddata_out;
reg [DW:0] p1_ddata = 'd0;
reg [24:0] p1_data_1 = 'd0;
reg [24:0] p1_data_2 = 'd0;
reg [24:0] p1_data_3 = 'd0;
reg [24:0] p1_data_4 = 'd0;
reg [DW:0] p2_ddata = 'd0;
reg [24:0] p2_data_0 = 'd0;
reg [24:0] p2_data_1 = 'd0;
reg [DW:0] p3_ddata = 'd0;
reg [24:0] p3_data = 'd0;
reg [DW:0] ddata_out = 'd0;
reg [ 7:0] data_p = 'd0;
wire [24:0] p1_data_1_p_s;
wire [24:0] p1_data_1_n_s;
wire [24:0] p1_data_1_s;
wire [24:0] p1_data_2_p_s;
wire [24:0] p1_data_2_n_s;
wire [24:0] p1_data_2_s;
wire [24:0] p1_data_3_p_s;
wire [24:0] p1_data_3_n_s;
wire [24:0] p1_data_3_s;
wire [24:0] p1_data_4_p_s;
wire [24:0] p1_data_4_n_s;
wire [24:0] p1_data_4_s;
assign p1_data_1_p_s = {1'b0, data_1[23:0]};
assign p1_data_1_n_s = ~p1_data_1_p_s + 1'b1;
assign p1_data_1_s = (data_1[24] == 1'b1) ? p1_data_1_n_s : p1_data_1_p_s;
assign p1_data_2_p_s = {1'b0, data_2[23:0]};
assign p1_data_2_n_s = ~p1_data_2_p_s + 1'b1;
assign p1_data_2_s = (data_2[24] == 1'b1) ? p1_data_2_n_s : p1_data_2_p_s;
assign p1_data_3_p_s = {1'b0, data_3[23:0]};
assign p1_data_3_n_s = ~p1_data_3_p_s + 1'b1;
assign p1_data_3_s = (data_3[24] == 1'b1) ? p1_data_3_n_s : p1_data_3_p_s;
assign p1_data_4_p_s = {1'b0, data_4[23:0]};
assign p1_data_4_n_s = ~p1_data_4_p_s + 1'b1;
assign p1_data_4_s = (data_4[24] == 1'b1) ? p1_data_4_n_s : p1_data_4_p_s;
always @(posedge clk) begin
p1_ddata <= ddata_in;
p1_data_1 <= p1_data_1_s;
p1_data_2 <= p1_data_2_s;
p1_data_3 <= p1_data_3_s;
p1_data_4 <= p1_data_4_s;
end
always @(posedge clk) begin
p2_ddata <= p1_ddata;
p2_data_0 <= p1_data_1 + p1_data_2;
p2_data_1 <= p1_data_3 + p1_data_4;
end
always @(posedge clk) begin
p3_ddata <= p2_ddata;
p3_data <= p2_data_0 + p2_data_1;
end
always @(posedge clk) begin
ddata_out <= p3_ddata;
if (p3_data[24] == 1'b1) begin
data_p <= 8'h00;
end else if (p3_data[23:20] == 'd0) begin
data_p <= p3_data[19:12];
end else begin
data_p <= 8'hff;
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
/*
* Copyright (c) 2001 Stephan Boettcher <[email protected]>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// $Id: ldelay2.v,v 1.2 2007/12/06 02:31:10 stevewilliams Exp $
// Test for delays in structural logic. Inertial delays suppress event.
module test;
wire q;
reg a, b;
xor #1 (q, a, b);
reg error;
initial
begin
error = 0;
#2;
@(q);
error = 1;
$display("%0d: FAILED: q=%b", $time, q);
end
initial
begin
// $dumpvars;
a = 0;
b = 1;
#3;
a = 1;
b = 0;
#2;
a = 0;
b = 1;
#3;
if (!error)
$display("PASSED");
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [63:0] crc;
wire [65:0] outData; // From fifo of fifo.v
wire [15:0] inData = crc[15:0];
wire [1:0] inWordPtr = crc[17:16];
wire wrEn = crc[20];
wire [1:0] wrPtr = crc[33:32];
wire [1:0] rdPtr = crc[34:33];
fifo fifo (
// Outputs
.outData (outData[65:0]),
// Inputs
.clk (clk),
.inWordPtr (inWordPtr[1:0]),
.inData (inData[15:0]),
.rdPtr (rdPtr),
.wrPtr (wrPtr),
.wrEn (wrEn));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%b q=%x\n",$time, cyc, crc, outData);
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc==90) begin
if (outData[63:0] != 64'hd9bcbc276f0984ea) $stop;
end
else if (cyc==91) begin
if (outData[63:0] != 64'hef77cd9b13a866f0) $stop;
end
else if (cyc==92) begin
if (outData[63:0] != 64'h2750cd9b13a866f0) $stop;
end
else if (cyc==93) begin
if (outData[63:0] != 64'h4ea0bc276f0984ea) $stop;
end
else if (cyc==94) begin
if (outData[63:0] != 64'h9d41bc276f0984ea) $stop;
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module fifo (/*AUTOARG*/
// Outputs
outData,
// Inputs
clk, inWordPtr, inData, wrPtr, rdPtr, wrEn
);
parameter fifoDepthLog2 = 1;
parameter fifoDepth = 1<<fifoDepthLog2;
`define PTRBITS (fifoDepthLog2+1)
`define PTRBITSM1 fifoDepthLog2
`define PTRBITSM2 (fifoDepthLog2-1)
input clk;
input [1:0] inWordPtr;
input [15:0] inData;
input [`PTRBITSM1:0] wrPtr;
input [`PTRBITSM1:0] rdPtr;
output [65:0] outData;
input wrEn;
reg [65:0] outData;
// verilator lint_off VARHIDDEN
// verilator lint_off LITENDIAN
reg [65:0] fifo[0:fifoDepth-1];
// verilator lint_on LITENDIAN
// verilator lint_on VARHIDDEN
//reg [65:0] temp;
always @(posedge clk) begin
//$write ("we=%x PT=%x ID=%x D=%x\n", wrEn, wrPtr[`PTRBITSM2:0], {1'b0,~inWordPtr,4'b0}, inData[15:0]);
if (wrEn) begin
fifo[ wrPtr[`PTRBITSM2:0] ][{1'b0,~inWordPtr,4'b0}+:16] <= inData[15:0];
// Equivelent to:
//temp = fifo[ wrPtr[`PTRBITSM2:0] ];
//temp [{1'b0,~inWordPtr,4'b0}+:16] = inData[15:0];
//fifo[ wrPtr[`PTRBITSM2:0] ] <= temp;
end
outData <= fifo[rdPtr[`PTRBITSM2:0]];
end
endmodule
|
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/14.0/ip/merlin/altera_avalon_mm_clock_crossing_bridge/altera_avalon_mm_clock_crossing_bridge.v#1 $
// $Revision: #1 $
// $Date: 2014/02/16 $
// $Author: swbranch $
// --------------------------------------
// Avalon-MM clock crossing bridge
//
// Clock crosses MM commands and responses with the
// help of asynchronous FIFOs.
//
// This bridge will stop emitting read commands when
// too many read commands are in flight to avoid
// response FIFO overflow.
// --------------------------------------
`timescale 1 ns / 1 ns
module altera_avalon_mm_clock_crossing_bridge
#(
parameter DATA_WIDTH = 32,
parameter SYMBOL_WIDTH = 8,
parameter HDL_ADDR_WIDTH = 10,
parameter BURSTCOUNT_WIDTH = 1,
parameter COMMAND_FIFO_DEPTH = 4,
parameter RESPONSE_FIFO_DEPTH = 4,
parameter MASTER_SYNC_DEPTH = 2,
parameter SLAVE_SYNC_DEPTH = 2,
// --------------------------------------
// Derived parameters
// --------------------------------------
parameter BYTEEN_WIDTH = DATA_WIDTH / SYMBOL_WIDTH
)
(
input s0_clk,
input s0_reset,
input m0_clk,
input m0_reset,
output s0_waitrequest,
output [DATA_WIDTH-1:0] s0_readdata,
output s0_readdatavalid,
input [BURSTCOUNT_WIDTH-1:0] s0_burstcount,
input [DATA_WIDTH-1:0] s0_writedata,
input [HDL_ADDR_WIDTH-1:0] s0_address,
input s0_write,
input s0_read,
input [BYTEEN_WIDTH-1:0] s0_byteenable,
input s0_debugaccess,
input m0_waitrequest,
input [DATA_WIDTH-1:0] m0_readdata,
input m0_readdatavalid,
output [BURSTCOUNT_WIDTH-1:0] m0_burstcount,
output [DATA_WIDTH-1:0] m0_writedata,
output [HDL_ADDR_WIDTH-1:0] m0_address,
output m0_write,
output m0_read,
output [BYTEEN_WIDTH-1:0] m0_byteenable,
output m0_debugaccess
);
localparam CMD_WIDTH = BURSTCOUNT_WIDTH + DATA_WIDTH + HDL_ADDR_WIDTH
+ BYTEEN_WIDTH
+ 3; // read, write, debugaccess
localparam NUMSYMBOLS = DATA_WIDTH / SYMBOL_WIDTH;
localparam RSP_WIDTH = DATA_WIDTH;
localparam MAX_BURST = (1 << (BURSTCOUNT_WIDTH-1));
localparam COUNTER_WIDTH = log2ceil(RESPONSE_FIFO_DEPTH) + 1;
localparam NON_BURSTING = (MAX_BURST == 1);
localparam BURST_WORDS_W = BURSTCOUNT_WIDTH;
// --------------------------------------
// Signals
// --------------------------------------
wire [CMD_WIDTH-1:0] s0_cmd_payload;
wire [CMD_WIDTH-1:0] m0_cmd_payload;
wire s0_cmd_valid;
wire m0_cmd_valid;
wire m0_internal_write;
wire m0_internal_read;
wire s0_cmd_ready;
wire m0_cmd_ready;
reg [COUNTER_WIDTH-1:0] pending_read_count;
wire [COUNTER_WIDTH-1:0] space_avail;
wire stop_cmd;
reg stop_cmd_r;
wire m0_read_accepted;
wire m0_rsp_ready;
reg old_read;
wire [BURST_WORDS_W-1:0] m0_burstcount_words;
// --------------------------------------
// Command FIFO
// --------------------------------------
(* altera_attribute = "-name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON" *) altera_avalon_dc_fifo
#(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (CMD_WIDTH),
.FIFO_DEPTH (COMMAND_FIFO_DEPTH),
.WR_SYNC_DEPTH (MASTER_SYNC_DEPTH),
.RD_SYNC_DEPTH (SLAVE_SYNC_DEPTH),
.BACKPRESSURE_DURING_RESET (1)
)
cmd_fifo
(
.in_clk (s0_clk),
.in_reset_n (~s0_reset),
.out_clk (m0_clk),
.out_reset_n (~m0_reset),
.in_data (s0_cmd_payload),
.in_valid (s0_cmd_valid),
.in_ready (s0_cmd_ready),
.out_data (m0_cmd_payload),
.out_valid (m0_cmd_valid),
.out_ready (m0_cmd_ready),
.in_startofpacket (1'b0),
.in_endofpacket (1'b0),
.in_empty ('b0),
.in_error ('b0),
.in_channel ('b0),
.in_csr_address ('b0),
.in_csr_read ('b0),
.in_csr_write ('b0),
.in_csr_writedata (32'b0),
.out_csr_address ('b0),
.out_csr_read ('b0),
.out_csr_write ('b0),
.out_csr_writedata (32'b0)
);
// --------------------------------------
// Command payload
// --------------------------------------
assign s0_waitrequest = ~s0_cmd_ready;
assign s0_cmd_valid = s0_write | s0_read;
assign s0_cmd_payload = {s0_address,
s0_burstcount,
s0_read,
s0_write,
s0_writedata,
s0_byteenable,
s0_debugaccess};
assign {m0_address,
m0_burstcount,
m0_internal_read,
m0_internal_write,
m0_writedata,
m0_byteenable,
m0_debugaccess} = m0_cmd_payload;
assign m0_cmd_ready = ~m0_waitrequest &
~(m0_internal_read & stop_cmd_r & ~old_read);
assign m0_write = m0_internal_write & m0_cmd_valid;
assign m0_read = m0_internal_read & m0_cmd_valid & (~stop_cmd_r | old_read);
assign m0_read_accepted = m0_read & ~m0_waitrequest;
// ---------------------------------------------
// the non-bursting case
// ---------------------------------------------
generate if (NON_BURSTING)
begin
always @(posedge m0_clk, posedge m0_reset) begin
if (m0_reset) begin
pending_read_count <= 0;
end
else begin
if (m0_read_accepted & m0_readdatavalid)
pending_read_count <= pending_read_count;
else if (m0_readdatavalid)
pending_read_count <= pending_read_count - 1;
else if (m0_read_accepted)
pending_read_count <= pending_read_count + 1;
end
end
end
// ---------------------------------------------
// the bursting case
// ---------------------------------------------
else begin
assign m0_burstcount_words = m0_burstcount;
always @(posedge m0_clk, posedge m0_reset) begin
if (m0_reset) begin
pending_read_count <= 0;
end
else begin
if (m0_read_accepted & m0_readdatavalid)
pending_read_count <= pending_read_count +
m0_burstcount_words - 1;
else if (m0_readdatavalid)
pending_read_count <= pending_read_count - 1;
else if (m0_read_accepted)
pending_read_count <= pending_read_count +
m0_burstcount_words;
end
end
end
endgenerate
assign stop_cmd = (pending_read_count + 2*MAX_BURST) > space_avail;
always @(posedge m0_clk, posedge m0_reset) begin
if (m0_reset) begin
stop_cmd_r <= 1'b0;
old_read <= 1'b0;
end
else begin
stop_cmd_r <= stop_cmd;
old_read <= m0_read & m0_waitrequest;
end
end
// --------------------------------------
// Response FIFO
// --------------------------------------
(* altera_attribute = "-name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON" *) altera_avalon_dc_fifo
#(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (RSP_WIDTH),
.FIFO_DEPTH (RESPONSE_FIFO_DEPTH),
.WR_SYNC_DEPTH (SLAVE_SYNC_DEPTH),
.RD_SYNC_DEPTH (MASTER_SYNC_DEPTH),
.USE_SPACE_AVAIL_IF (1)
)
rsp_fifo
(
.in_clk (m0_clk),
.in_reset_n (~m0_reset),
.out_clk (s0_clk),
.out_reset_n (~s0_reset),
.in_data (m0_readdata),
.in_valid (m0_readdatavalid),
// ------------------------------------
// must never overflow, or we're in trouble
// (we cannot backpressure the response)
// ------------------------------------
.in_ready (m0_rsp_ready),
.out_data (s0_readdata),
.out_valid (s0_readdatavalid),
.out_ready (1'b1),
.space_avail_data (space_avail),
.in_startofpacket (1'b0),
.in_endofpacket (1'b0),
.in_empty ('b0),
.in_error ('b0),
.in_channel ('b0),
.in_csr_address ('b0),
.in_csr_read ('b0),
.in_csr_write ('b0),
.in_csr_writedata (32'b0),
.out_csr_address ('b0),
.out_csr_read ('b0),
.out_csr_write ('b0),
.out_csr_writedata (32'b0)
);
// synthesis translate_off
always @(posedge m0_clk) begin
if (~m0_rsp_ready & m0_readdatavalid) begin
$display("%t %m: internal error, response fifo overflow", $time);
end
if (pending_read_count > space_avail) begin
$display("%t %m: internal error, too many pending reads", $time);
end
end
// synthesis translate_on
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
integer i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: rd_data_gen.v
// /___/ /\ Date Last Modified:
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This module has all the timing control for generating "compare data"
// to compare the read data from memory.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v1_9_rd_data_gen #
(
parameter TCQ = 100,
parameter FAMILY = "VIRTEX7", // "SPARTAN6", "VIRTEX6"
parameter MEM_TYPE = "DDR3",
parameter nCK_PER_CLK = 4, // DRAM clock : MC clock
parameter MEM_BURST_LEN = 8,
parameter START_ADDR = 32'h00000000,
parameter ADDR_WIDTH = 32,
parameter BL_WIDTH = 6,
parameter DWIDTH = 32,
parameter DATA_PATTERN = "DGEN_ALL", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
parameter NUM_DQ_PINS = 8,
parameter SEL_VICTIM_LINE = 3, // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
parameter COLUMN_WIDTH = 10
)
(
input clk_i, //
input [4:0] rst_i,
input [31:0] prbs_fseed_i,
input [3:0] data_mode_i, // "00" = bram;
input mode_load_i,
input [3:0] vio_instr_mode_value,
output cmd_rdy_o, // ready to receive command. It should assert when data_port is ready at the // beginning and will be deasserted once see the cmd_valid_i is asserted.
// And then it should reasserted when
// it is generating the last_word.
input cmd_valid_i, // when both cmd_valid_i and cmd_rdy_o is high, the command is valid.
output reg cmd_start_o,
// input [ADDR_WIDTH-1:0] m_addr_i, // generated address used to determine data pattern.
input [31:0] simple_data0 ,
input [31:0] simple_data1 ,
input [31:0] simple_data2 ,
input [31:0] simple_data3 ,
input [31:0] simple_data4 ,
input [31:0] simple_data5 ,
input [31:0] simple_data6 ,
input [31:0] simple_data7 ,
input [31:0] fixed_data_i,
input [ADDR_WIDTH-1:0] addr_i, // generated address used to determine data pattern.
input [BL_WIDTH-1:0] bl_i, // generated burst length for control the burst data
output user_bl_cnt_is_1_o,
input data_rdy_i, // connect from mcb_wr_full when used as wr_data_gen in sp6
// connect from mcb_rd_empty when used as rd_data_gen in sp6
// connect from rd_data_valid in v6
// When both data_rdy and data_valid is asserted, the ouput data is valid.
output reg data_valid_o, // connect to wr_en or rd_en and is asserted whenever the
// pattern is available.
// output [DWIDTH-1:0] data_o // generated data pattern NUM_DQ_PINS*nCK_PER_CLK*2-1
output [31:0] tg_st_addr_o,
output [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] data_o // generated data pattern NUM_DQ_PINS*nCK_PER_CLK*2-1
);
//
wire [31:0] prbs_data;
reg cmd_start;
reg [31:0] adata;
reg [31:0] hdata;
reg [31:0] ndata;
reg [31:0] w1data;
reg [NUM_DQ_PINS*4-1:0] v6_w1data;
reg [31:0] w0data;
reg [DWIDTH-1:0] data;
reg cmd_rdy;
reg [BL_WIDTH:0]user_burst_cnt;
reg [31:0] w3data;
reg prefetch;
assign data_port_fifo_rdy = data_rdy_i;
reg user_bl_cnt_is_1;
assign user_bl_cnt_is_1_o = user_bl_cnt_is_1;
always @ (posedge clk_i)
begin
if (data_port_fifo_rdy)
if ((user_burst_cnt == 2 && FAMILY == "SPARTAN6")
|| (user_burst_cnt == 2 && FAMILY == "VIRTEX6")
)
user_bl_cnt_is_1 <= #TCQ 1'b1;
else
user_bl_cnt_is_1 <= #TCQ 1'b0;
end
//reg cmd_start_b;
always @(cmd_valid_i,data_port_fifo_rdy,cmd_rdy,user_bl_cnt_is_1,prefetch)
begin
cmd_start = cmd_valid_i & cmd_rdy & ( data_port_fifo_rdy | prefetch) ;
cmd_start_o = cmd_valid_i & cmd_rdy & ( data_port_fifo_rdy | prefetch) ;
end
// counter to count user burst length
always @( posedge clk_i)
begin
if ( rst_i[0] )
user_burst_cnt <= #TCQ 'd0;
else if(cmd_valid_i && cmd_rdy && ( data_port_fifo_rdy | prefetch) ) begin
// SPATAN6 has maximum of burst length of 64.
if (FAMILY == "SPARTAN6" && bl_i[5:0] == 6'b000000)
begin
user_burst_cnt[6:0] <= #TCQ 7'd64;
user_burst_cnt[BL_WIDTH:7] <= 'b0;
end
else if (FAMILY == "VIRTEX6" && bl_i[BL_WIDTH - 1:0] == {BL_WIDTH {1'b0}})
user_burst_cnt <= #TCQ {1'b1, {BL_WIDTH{1'b0}}};
else
user_burst_cnt <= #TCQ {1'b0,bl_i };
end
else if(data_port_fifo_rdy)
if (user_burst_cnt != 6'd0)
user_burst_cnt <= #TCQ user_burst_cnt - 1'b1;
else
user_burst_cnt <= #TCQ 'd0;
end
// cmd_rdy_o assert when the dat fifo is not full and deassert once cmd_valid_i
// is assert and reassert during the last data
//data_valid_o logic
always @( posedge clk_i)
begin
if ( rst_i[0] )
prefetch <= #TCQ 1'b1;
else if (data_port_fifo_rdy || cmd_start)
prefetch <= #TCQ 1'b0;
else if (user_burst_cnt == 0 && ~data_port_fifo_rdy)
prefetch <= #TCQ 1'b1;
end
assign cmd_rdy_o = cmd_rdy ;
always @( posedge clk_i)
begin
if ( rst_i[0] )
cmd_rdy <= #TCQ 1'b1;
else if (cmd_valid_i && cmd_rdy && (data_port_fifo_rdy || prefetch ))
cmd_rdy <= #TCQ 1'b0;
else if ((data_port_fifo_rdy && user_burst_cnt == 2 && vio_instr_mode_value != 7 ) ||
(data_port_fifo_rdy && user_burst_cnt == 1 && vio_instr_mode_value == 7 ))
cmd_rdy <= #TCQ 1'b1;
end
always @ (data_port_fifo_rdy)
if (FAMILY == "SPARTAN6")
data_valid_o = data_port_fifo_rdy;
else
data_valid_o = data_port_fifo_rdy;
/*
generate
if (FAMILY == "SPARTAN6")
begin : SP6_DGEN
s7ven_data_gen #
(
.TCQ (TCQ),
.DMODE ("READ"),
.nCK_PER_CLK (nCK_PER_CLK),
.FAMILY (FAMILY),
.ADDR_WIDTH (32 ),
.BL_WIDTH (BL_WIDTH ),
.MEM_BURST_LEN (MEM_BURST_LEN),
.DWIDTH (DWIDTH ),
.DATA_PATTERN (DATA_PATTERN ),
.NUM_DQ_PINS (NUM_DQ_PINS ),
.SEL_VICTIM_LINE (SEL_VICTIM_LINE),
.START_ADDR (START_ADDR),
.COLUMN_WIDTH (COLUMN_WIDTH)
)
s7ven_data_gen
(
.clk_i (clk_i ),
.rst_i (rst_i[1] ),
.data_rdy_i (data_rdy_i ),
.mem_init_done_i (1'b1),
.wr_data_mask_gen_i (1'b0),
.prbs_fseed_i (prbs_fseed_i),
.mode_load_i (mode_load_i),
.data_mode_i (data_mode_i ),
.cmd_startA (cmd_start ),
.cmd_startB (cmd_start ),
.cmd_startC (cmd_start ),
.cmd_startD (cmd_start ),
.cmd_startE (cmd_start ),
.m_addr_i (addr_i),//(m_addr_i ),
.simple_data0 (simple_data0),
.simple_data1 (simple_data1),
.simple_data2 (simple_data2),
.simple_data3 (simple_data3),
.simple_data4 (simple_data4),
.simple_data5 (simple_data5),
.simple_data6 (simple_data6),
.simple_data7 (simple_data7),
.fixed_data_i (fixed_data_i),
.addr_i (addr_i ),
.user_burst_cnt (user_burst_cnt),
.fifo_rdy_i (data_port_fifo_rdy ),
.data_o (data_o ),
.data_mask_o (),
.bram_rd_valid_o ()
);
end
endgenerate*/
//generate
//if (FAMILY == "VIRTEX6")
//begin : V_DGEN
mig_7series_v1_9_s7ven_data_gen #
(
.TCQ (TCQ),
.DMODE ("READ"),
.nCK_PER_CLK (nCK_PER_CLK),
.FAMILY (FAMILY),
.MEM_TYPE (MEM_TYPE),
.ADDR_WIDTH (32 ),
.BL_WIDTH (BL_WIDTH ),
.MEM_BURST_LEN (MEM_BURST_LEN),
.DWIDTH (DWIDTH ),
.DATA_PATTERN (DATA_PATTERN ),
.NUM_DQ_PINS (NUM_DQ_PINS ),
.SEL_VICTIM_LINE (SEL_VICTIM_LINE),
.START_ADDR (START_ADDR),
.COLUMN_WIDTH (COLUMN_WIDTH)
)
s7ven_data_gen
(
.clk_i (clk_i ),
.rst_i (rst_i[1] ),
.data_rdy_i (data_rdy_i ),
.mem_init_done_i (1'b1),
.wr_data_mask_gen_i (1'b0),
.prbs_fseed_i (prbs_fseed_i),
.mode_load_i (mode_load_i),
.data_mode_i (data_mode_i ),
.cmd_startA (cmd_start ),
.cmd_startB (cmd_start ),
.cmd_startC (cmd_start ),
.cmd_startD (cmd_start ),
.cmd_startE (cmd_start ),
.m_addr_i (addr_i),//(m_addr_i ),
.simple_data0 (simple_data0),
.simple_data1 (simple_data1),
.simple_data2 (simple_data2),
.simple_data3 (simple_data3),
.simple_data4 (simple_data4),
.simple_data5 (simple_data5),
.simple_data6 (simple_data6),
.simple_data7 (simple_data7),
.fixed_data_i (fixed_data_i),
.addr_i (addr_i ),
.user_burst_cnt (user_burst_cnt),
.fifo_rdy_i (data_port_fifo_rdy ),
.data_o (data_o ),
.tg_st_addr_o (tg_st_addr_o),
.data_mask_o (),
.bram_rd_valid_o ()
);
//end
//endgenerate
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: c2i_fctrl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: c2i_fctrl (cpu-to-io fast control)
// Description: This block is the interface block between SPARC cores
// via the crossbar and the IO subsystem.
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Interface signal list declarations
////////////////////////////////////////////////////////////////////////
module c2i_fctrl (/*AUTOARG*/
// Outputs
iob_pcx_stall_pq, io_mondo_data_wr, mondo_data_bypass_d1,
mondo_addr_creg_mdata0_dec_d1, mondo_addr_creg_mdata1_dec_d1,
mondo_addr_creg_mbusy_dec_d1, cpu_mondo_rd_d1, tap_mondo_rd_d1,
cpu_mondo_rd_d2, cpu_mondo_addr_invld_d2, mondo_data_addr_p0_d1,
cpu_buf_tail_f, cpu_mondo_wr_d2, tap_mondo_acc_addr_invld_d2_f,
tap_mondo_acc_seq_d2_f, mondo_data_addr_p0, mondo_data_addr_p1,
mondo_data0_wr_lo_l, mondo_data0_wr_hi_l, mondo_data1_wr_lo_l,
mondo_data1_wr_hi_l, mondo_source_wr_l, mondo_busy_addr_p0,
mondo_busy_addr_p1, mondo_busy_addr_p2, mondo_busy_wr_p1,
mondo_busy_wr_p2, cpu_buf_wr_l, cpu_buf_tail_ptr,
// Inputs
cpu_rst_l, cpu_clk, tx_sync, rx_sync, pcx_iob_data_rdy_px2,
pcx_iob_vld, pcx_iob_req, pcx_iob_addr, pcx_iob_cputhr,
cpu_buf_head_s, int_buf_hit_hwm, io_mondo_data_wr_s,
io_mondo_data_wr_addr_s, tap_mondo_acc_addr_s,
tap_mondo_acc_seq_s, tap_mondo_wr_s
);
////////////////////////////////////////////////////////////////////////
// Signal declarations
////////////////////////////////////////////////////////////////////////
// Global interface
input cpu_rst_l;
input cpu_clk;
input tx_sync;
input rx_sync;
// Crossbar interface
input pcx_iob_data_rdy_px2;
output iob_pcx_stall_pq;
// c2i fast datapath interface
input pcx_iob_vld;
input [`PCX_RQ_HI-`PCX_RQ_LO:0] pcx_iob_req;
input [`PCX_AD_HI-`PCX_AD_LO:0] pcx_iob_addr;
input [`PCX_CP_HI-`PCX_TH_LO:0] pcx_iob_cputhr;
output io_mondo_data_wr;
output mondo_data_bypass_d1;
output mondo_addr_creg_mdata0_dec_d1;
output mondo_addr_creg_mdata1_dec_d1;
output mondo_addr_creg_mbusy_dec_d1;
output cpu_mondo_rd_d1;
output tap_mondo_rd_d1;
output cpu_mondo_rd_d2;
output cpu_mondo_addr_invld_d2;
output [`IOB_MONDO_DATA_INDEX-1:0] mondo_data_addr_p0_d1;
// c2i slow control interface
input [`IOB_CPU_BUF_INDEX:0] cpu_buf_head_s;
output [`IOB_CPU_BUF_INDEX:0] cpu_buf_tail_f;
// i2c fast control interface
//output cpu_mondo_rd_d2;
output cpu_mondo_wr_d2;
input int_buf_hit_hwm;
// i2c slow control interface
input io_mondo_data_wr_s;
// i2c slow datapath interface
input [`IOB_MONDO_DATA_INDEX-1:0] io_mondo_data_wr_addr_s;
// IOB control interface
input [`IOB_ADDR_WIDTH-1:0] tap_mondo_acc_addr_s;
input tap_mondo_acc_seq_s;
input tap_mondo_wr_s;
output tap_mondo_acc_addr_invld_d2_f;
output tap_mondo_acc_seq_d2_f;
// Mondo data table interface
output [`IOB_MONDO_DATA_INDEX-1:0] mondo_data_addr_p0;
output [`IOB_MONDO_DATA_INDEX-1:0] mondo_data_addr_p1;
output mondo_data0_wr_lo_l;
output mondo_data0_wr_hi_l;
output mondo_data1_wr_lo_l;
output mondo_data1_wr_hi_l;
output mondo_source_wr_l;
output [`IOB_MONDO_DATA_INDEX-1:0] mondo_busy_addr_p0;
output [`IOB_MONDO_DATA_INDEX-1:0] mondo_busy_addr_p1;
output [`IOB_MONDO_DATA_INDEX-1:0] mondo_busy_addr_p2;
output mondo_busy_wr_p1;
output mondo_busy_wr_p2;
// Cpu buffer interface
output cpu_buf_wr_l;
output [`IOB_CPU_BUF_INDEX-1:0] cpu_buf_tail_ptr;
// Internal signals
wire pcx_iob_data_rdy;
wire cpu_mondo_acc;
wire cpu_mondo_rd;
wire cpu_mondo_wr;
wire cpu_mondo_wr_d1;
wire cpu_mondo_addr_creg_mdata0_dec;
wire cpu_mondo_addr_creg_mdata1_dec;
wire cpu_mondo_addr_creg_mbusy_dec;
wire [`IOB_MONDO_DATA_INDEX-1:0] cpu_mondo_data_addr;
wire cpu_mondo_addr_invld;
wire cpu_mondo_addr_creg_mdata0_dec_d1;
wire cpu_mondo_addr_creg_mdata1_dec_d1;
wire cpu_mondo_addr_creg_mbusy_dec_d1;
wire cpu_mondo_addr_invld_d1;
wire [`IOB_MONDO_DATA_INDEX-1:0] io_mondo_data_addr;
wire [`IOB_ADDR_WIDTH-1:0] tap_mondo_acc_addr;
wire tap_mondo_addr_creg_mdata0_dec;
wire tap_mondo_addr_creg_mdata1_dec;
wire tap_mondo_addr_creg_mbusy_dec;
wire [`IOB_MONDO_DATA_INDEX-1:0] tap_mondo_data_addr;
wire tap_mondo_addr_invld;
wire tap_mondo_addr_creg_mdata0_dec_d1;
wire tap_mondo_addr_creg_mdata1_dec_d1;
wire tap_mondo_addr_creg_mbusy_dec_d1;
wire tap_mondo_addr_invld_d1;
wire tap_mondo_addr_invld_d2;
wire tap_mondo_acc_seq;
wire tap_mondo_acc_seq_d1;
wire tap_mondo_acc_seq_d2;
wire tap_mondo_wr;
wire tap_mondo_acc;
wire tap_mondo_rd;
wire mondo_data0_wr;
wire mondo_data0_wr_lo;
wire mondo_data0_wr_hi;
wire mondo_data1_wr;
wire mondo_data1_wr_lo;
wire mondo_data1_wr_hi;
wire mondo_source_wr;
wire mondo_data_wr_d1;
wire [`IOB_MONDO_DATA_INDEX-1:0] mondo_data_addr_p1_d1;
wire cpu_buf_wr;
wire [`IOB_CPU_BUF_INDEX:0] cpu_buf_tail_plus;
wire [`IOB_CPU_BUF_INDEX:0] cpu_buf_tail;
wire [`IOB_CPU_BUF_INDEX:0] cpu_buf_head;
wire [`IOB_CPU_BUF_INDEX:0] cpu_buf_tail_plus8;
wire cpu_buf_hit_hwm;
////////////////////////////////////////////////////////////////////////
// Code starts here
////////////////////////////////////////////////////////////////////////
/*****************************************************************
* Read/Write request to the interrupt status table, mondo data tables,
* and mondo busy table from CPU.
* Write will not update the tables (only generates ack) except the
* mondo busy bit because the entries are read-only by software.
*****************************************************************/
dffrl_ns #(1) pcx_iob_data_rdy_ff (.din(pcx_iob_data_rdy_px2),
.clk(cpu_clk),
.rst_l(cpu_rst_l),
.q(pcx_iob_data_rdy));
// Check address to see if request is mondo data, or mondo busy.
// They are all in the `IOB_INT_CSR space.
assign cpu_mondo_acc = pcx_iob_data_rdy & pcx_iob_vld &
(pcx_iob_addr[`ADDR_MAP_HI:`ADDR_MAP_LO] == `IOB_INT_CSR);
assign cpu_mondo_rd = cpu_mondo_acc & (pcx_iob_req == `LOAD_RQ);
dffrl_ns #(1) cpu_mondo_rd_d1_ff (.din(cpu_mondo_rd),
.clk(cpu_clk),
.rst_l(cpu_rst_l),
.q(cpu_mondo_rd_d1));
dffrl_ns #(1) cpu_mondo_rd_d2_ff (.din(cpu_mondo_rd_d1),
.clk(cpu_clk),
.rst_l(cpu_rst_l),
.q(cpu_mondo_rd_d2));
assign cpu_mondo_wr = cpu_mondo_acc & (pcx_iob_req == `STORE_RQ);
dffrl_ns #(1) cpu_mondo_wr_d1_ff (.din(cpu_mondo_wr),
.clk(cpu_clk),
.rst_l(cpu_rst_l),
.q(cpu_mondo_wr_d1));
dffrl_ns #(1) cpu_mondo_wr_d2_ff (.din(cpu_mondo_wr_d1),
.clk(cpu_clk),
.rst_l(cpu_rst_l),
.q(cpu_mondo_wr_d2));
// Decode address to access interrupt table
iobdg_int_mondo_addr_dec cpu_mondo_addr_dec (.addr_in(pcx_iob_addr),
.thr_id_in(pcx_iob_cputhr),
.creg_mdata0_dec(cpu_mondo_addr_creg_mdata0_dec),
.creg_mdata1_dec(cpu_mondo_addr_creg_mdata1_dec),
.creg_mbusy_dec(cpu_mondo_addr_creg_mbusy_dec),
.mondo_data_addr(cpu_mondo_data_addr),
.addr_invld(cpu_mondo_addr_invld));
dffrl_ns #(1) cpu_mondo_addr_creg_mdata0_dec_d1_ff (.din(cpu_mondo_addr_creg_mdata0_dec),
.clk(cpu_clk),
.rst_l(cpu_rst_l),
.q(cpu_mondo_addr_creg_mdata0_dec_d1));
dffrl_ns #(1) cpu_mondo_addr_creg_mdata1_dec_d1_ff (.din(cpu_mondo_addr_creg_mdata1_dec),
.clk(cpu_clk),
.rst_l(cpu_rst_l),
.q(cpu_mondo_addr_creg_mdata1_dec_d1));
dffrl_ns #(1) cpu_mondo_addr_creg_mbusy_dec_d1_ff (.din(cpu_mondo_addr_creg_mbusy_dec),
.clk(cpu_clk),
.rst_l(cpu_rst_l),
.q(cpu_mondo_addr_creg_mbusy_dec_d1));
dffrl_ns #(1) cpu_mondo_addr_invld_d1_ff (.din(cpu_mondo_addr_invld),
.clk(cpu_clk),
.rst_l(cpu_rst_l),
.q(cpu_mondo_addr_invld_d1));
dffrl_ns #(1) cpu_mondo_addr_invld_d2_ff (.din(cpu_mondo_addr_invld_d1),
.clk(cpu_clk),
.rst_l(cpu_rst_l),
.q(cpu_mondo_addr_invld_d2));
/*****************************************************************
* Write request to the mondo data0, mondo data1, mondo busy table
* from JBI
*****************************************************************/
// Write will be asserted for multiple cycles. That's okay. The
// same entry in the array will be written several times.
dffrle_ns #(1) io_mondo_data_wr_ff (.din(io_mondo_data_wr_s),
.rst_l(cpu_rst_l),
.en(rx_sync),
.clk(cpu_clk),
.q(io_mondo_data_wr));
dffe_ns #(`IOB_MONDO_DATA_INDEX) io_mondo_data_addr_ff (.din(io_mondo_data_wr_addr_s),
.en(rx_sync),
.clk(cpu_clk),
.q(io_mondo_data_addr));
/*****************************************************************
* Read/Write request to the mondo data, mondo busy table from TAP
*****************************************************************/
// Flop address to convert to cpu clock domain
dffe_ns #(`IOB_ADDR_WIDTH) tap_mondo_acc_addr_ff (.din(tap_mondo_acc_addr_s),
.en(rx_sync),
.clk(cpu_clk),
.q(tap_mondo_acc_addr));
// Decode address to access interrupt table, mondo data, mondo busy
// Thread ID is hardwired to zero. TAP should use alias address to access
// mondo data table. If it tries to use the software address, only
// thread 0's entry is accessible.
iobdg_int_mondo_addr_dec tap_mondo_addr_dec (.addr_in(tap_mondo_acc_addr),
.thr_id_in(`IOB_CPUTHR_INDEX'b0),
.creg_mdata0_dec(tap_mondo_addr_creg_mdata0_dec),
.creg_mdata1_dec(tap_mondo_addr_creg_mdata1_dec),
.creg_mbusy_dec(tap_mondo_addr_creg_mbusy_dec),
.mondo_data_addr(tap_mondo_data_addr),
.addr_invld(tap_mondo_addr_invld));
dffrle_ns #(1) tap_mondo_addr_creg_mdata0_dec_d1_ff (.din(tap_mondo_addr_creg_mdata0_dec),
.rst_l(cpu_rst_l),
.en(tap_mondo_acc),
.clk(cpu_clk),
.q(tap_mondo_addr_creg_mdata0_dec_d1));
dffrle_ns #(1) tap_mondo_addr_creg_mdata1_dec_d1_ff (.din(tap_mondo_addr_creg_mdata1_dec),
.rst_l(cpu_rst_l),
.en(tap_mondo_acc),
.clk(cpu_clk),
.q(tap_mondo_addr_creg_mdata1_dec_d1));
dffrle_ns #(1) tap_mondo_addr_creg_mbusy_dec_d1_ff (.din(tap_mondo_addr_creg_mbusy_dec),
.rst_l(cpu_rst_l),
.en(tap_mondo_acc),
.clk(cpu_clk),
.q(tap_mondo_addr_creg_mbusy_dec_d1));
dffrle_ns #(1) tap_mondo_addr_invld_d1_ff (.din(tap_mondo_addr_invld),
.rst_l(cpu_rst_l),
.en(tap_mondo_acc),
.clk(cpu_clk),
.q(tap_mondo_addr_invld_d1));
dffrl_ns #(1) tap_mondo_addr_invld_d2_ff (.din(tap_mondo_addr_invld_d1),
.clk(cpu_clk),
.rst_l(cpu_rst_l),
.q(tap_mondo_addr_invld_d2));
// Send result back to BSC clock domain
dffrle_ns #(1) tap_mondo_acc_addr_invld_d2_f_ff (.din(tap_mondo_addr_invld_d2),
.rst_l(cpu_rst_l),
.en(tx_sync),
.clk(cpu_clk),
.q(tap_mondo_acc_addr_invld_d2_f));
// Flop sequence number to convert to cpu clock domain
dffrle_ns #(1) tap_mondo_acc_seq_ff (.din(tap_mondo_acc_seq_s),
.rst_l(cpu_rst_l),
.en(rx_sync),
.clk(cpu_clk),
.q(tap_mondo_acc_seq));
// Keep track of which sequence number has been serviced
dffrle_ns #(1) tap_mondo_acc_seq_d1_ff (.din(tap_mondo_acc_seq),
.rst_l(cpu_rst_l),
.en(tap_mondo_acc),
.clk(cpu_clk),
.q(tap_mondo_acc_seq_d1));
dffrl_ns #(1) tap_mondo_acc_seq_d2_ff (.din(tap_mondo_acc_seq_d1),
.clk(cpu_clk),
.rst_l(cpu_rst_l),
.q(tap_mondo_acc_seq_d2));
// Send result back to JBUS clock domain
dffrle_ns #(1) tap_mondo_acc_seq_d2_f_ff (.din(tap_mondo_acc_seq_d2),
.rst_l(cpu_rst_l),
.en(tx_sync),
.clk(cpu_clk),
.q(tap_mondo_acc_seq_d2_f));
// Flop write signal to convert to cpu clock domain
dffrle_ns #(1) tap_mondo_wr_ff (.din(tap_mondo_wr_s),
.rst_l(cpu_rst_l),
.en(rx_sync),
.clk(cpu_clk),
.q(tap_mondo_wr));
// CPU read and IO write has higher priority than TAP read/write
assign tap_mondo_acc = ~cpu_mondo_acc &
~io_mondo_data_wr &
(tap_mondo_acc_seq != tap_mondo_acc_seq_d1);
assign tap_mondo_rd = tap_mondo_acc & ~tap_mondo_wr;
dffrl_ns #(1) tap_mondo_rd_d1_ff (.din(tap_mondo_rd),
.clk(cpu_clk),
.rst_l(cpu_rst_l),
.q(tap_mondo_rd_d1));
/*****************************************************************
* Mux out decoded signals depending on CPU or TAP access
*****************************************************************/
assign mondo_addr_creg_mdata0_dec_d1 =
cpu_mondo_rd_d1 ? cpu_mondo_addr_creg_mdata0_dec_d1 :
tap_mondo_addr_creg_mdata0_dec_d1;
assign mondo_addr_creg_mdata1_dec_d1 =
cpu_mondo_rd_d1 ? cpu_mondo_addr_creg_mdata1_dec_d1 :
tap_mondo_addr_creg_mdata1_dec_d1;
assign mondo_addr_creg_mbusy_dec_d1 =
cpu_mondo_rd_d1 ? cpu_mondo_addr_creg_mbusy_dec_d1 :
tap_mondo_addr_creg_mbusy_dec_d1;
/*****************************************************************
* Setup read/write access to mondo data table
*****************************************************************/
assign mondo_data_addr_p0 = cpu_mondo_acc ? cpu_mondo_data_addr :
tap_mondo_data_addr;
assign mondo_data_addr_p1 = io_mondo_data_wr ? io_mondo_data_addr :
tap_mondo_data_addr;
assign mondo_data0_wr = io_mondo_data_wr |
(tap_mondo_acc & tap_mondo_wr & tap_mondo_addr_creg_mdata0_dec);
assign mondo_data0_wr_lo = mondo_data0_wr & ~mondo_data_addr_p1[`IOB_MONDO_DATA_INDEX-1];
assign mondo_data0_wr_hi = mondo_data0_wr & mondo_data_addr_p1[`IOB_MONDO_DATA_INDEX-1];
assign mondo_data1_wr = io_mondo_data_wr |
(tap_mondo_acc & tap_mondo_wr & tap_mondo_addr_creg_mdata1_dec);
assign mondo_data1_wr_lo = mondo_data1_wr & ~mondo_data_addr_p1[`IOB_MONDO_DATA_INDEX-1];
assign mondo_data1_wr_hi = mondo_data1_wr & mondo_data_addr_p1[`IOB_MONDO_DATA_INDEX-1];
assign mondo_source_wr = io_mondo_data_wr |
(tap_mondo_acc & tap_mondo_wr & tap_mondo_addr_creg_mbusy_dec);
assign mondo_data0_wr_lo_l = ~mondo_data0_wr_lo;
assign mondo_data0_wr_hi_l = ~mondo_data0_wr_hi;
assign mondo_data1_wr_lo_l = ~mondo_data1_wr_lo;
assign mondo_data1_wr_hi_l = ~mondo_data1_wr_hi;
assign mondo_source_wr_l = ~mondo_source_wr;
// Bypass detection - Only bypass if io_mondo_data_wr. This bypass
// is for the case when Jbus interrupt updates the
// tables and CPU tries to read the exact same
// entry.
// No need to bypass if TAP is writing because
// TAP access is allowed only if CPU is not
// accessing the tables.
dffrl_ns #(1) mondo_data_wr_d1_ff (.din(io_mondo_data_wr),
.clk(cpu_clk),
.rst_l(cpu_rst_l),
.q(mondo_data_wr_d1));
dff_ns #(`IOB_MONDO_DATA_INDEX) mondo_data_addr_p0_d1_ff (.din(mondo_data_addr_p0),
.clk(cpu_clk),
.q(mondo_data_addr_p0_d1));
dff_ns #(`IOB_MONDO_DATA_INDEX) mondo_data_addr_p1_d1_ff (.din(mondo_data_addr_p1),
.clk(cpu_clk),
.q(mondo_data_addr_p1_d1));
assign mondo_data_bypass_d1 = mondo_data_wr_d1 &
(mondo_data_addr_p0_d1 == mondo_data_addr_p1_d1);
/*****************************************************************
* Setup read/write access to mondo busy
*****************************************************************/
// Need two write ports because JBUS and CPU may write the Busy bit
// at the same time. If they try to write the same entry at the same
// time (which is probably a software bug), JBUS wins.
// Port 0 - CPU or TAP read
// Port 1 - JBUS or TAP write
// Port 2 - CPU write
assign mondo_busy_addr_p0 = mondo_data_addr_p0;
assign mondo_busy_addr_p1 = mondo_data_addr_p1;
assign mondo_busy_addr_p2 = cpu_mondo_data_addr;
assign mondo_busy_wr_p1 = io_mondo_data_wr |
(tap_mondo_acc & tap_mondo_wr & tap_mondo_addr_creg_mbusy_dec);
assign mondo_busy_wr_p2 = cpu_mondo_acc & cpu_mondo_wr & cpu_mondo_addr_creg_mbusy_dec;
/*****************************************************************
* Cpu Buffer Control
*****************************************************************/
assign cpu_buf_wr = pcx_iob_data_rdy & pcx_iob_vld & ~(cpu_mondo_rd | cpu_mondo_wr);
assign cpu_buf_wr_l = ~cpu_buf_wr;
// Tail pointer to cpu buffer
dffrle_ns #(`IOB_CPU_BUF_INDEX+1) cpu_buf_tail_ff (.din(cpu_buf_tail_plus),
.rst_l(cpu_rst_l),
.en(cpu_buf_wr),
.clk(cpu_clk),
.q(cpu_buf_tail));
assign cpu_buf_tail_plus = cpu_buf_tail + 5'b1;
assign cpu_buf_tail_ptr = cpu_buf_tail[`IOB_CPU_BUF_INDEX-1:0];
// Send tail pointer to BSC clock domain
dffrle_ns #(`IOB_CPU_BUF_INDEX+1) cpu_buf_tail_f_ff (.din(cpu_buf_tail),
.rst_l(cpu_rst_l),
.en(tx_sync),
.clk(cpu_clk),
.q(cpu_buf_tail_f));
// Flop head pointer to convert to CPU clock domain
dffrle_ns #(`IOB_CPU_BUF_INDEX+1) cpu_buf_head_ff (.din(cpu_buf_head_s),
.rst_l(cpu_rst_l),
.en(rx_sync),
.clk(cpu_clk),
.q(cpu_buf_head));
/************************************************************************
* __tail incremented here
* flop req | for packet in PX2
* | |
* | | compute __stall sent here
* | | hwm |
* | | | |
* V V V V
* PQ PA PX1 rptr PX2 C1 C2 C3 rtpr
* PQ PA PX1 rptr PX2 C1 C2 C3 rptr
* PQ PA PX1 rptr PX2 C1 C2 C3 rptr
* PQ PA PX1 rptr PX2 C1 C2 C3 rptr
* PQ PA PX1 rptr PX2 C1 C2 C3 rptr
* PQ PA PX1 rptr PX2 C1 C2 C3 rptr
* PQ PA PX1 rptr PX2 C1 C2 C3 rptr
* PQ PA PX1 rptr PX2 C1 C2 C3 rptr
* PQ PA PX1 rptr PX2 C1 C2 C3 rptr
* --> PQ PA
* |
* |
* packet in this PQ is stalled
*
* When the stall is signalled, there can potentially be 8 packets in
* C2, C1, PX2, rptr, PX1, PA, PQ, and PQ-1 that need to be queued in
* the CPU shared buffer.
* Hence, the high water mark is 16 - 8 = 8.
************************************************************************/
// Assert stall to crossbar if we are 7 or less entries away from filling
// up cpu buffer.
assign cpu_buf_tail_plus8 = cpu_buf_tail + 5'b01000;
assign cpu_buf_hit_hwm = ((cpu_buf_tail_plus8[`IOB_CPU_BUF_INDEX] != cpu_buf_head[`IOB_CPU_BUF_INDEX]) &
(cpu_buf_tail_plus8[`IOB_CPU_BUF_INDEX-1:0] >= cpu_buf_head[`IOB_CPU_BUF_INDEX-1:0])) |
((cpu_buf_tail_plus8[`IOB_CPU_BUF_INDEX] == cpu_buf_head[`IOB_CPU_BUF_INDEX]) &
(cpu_buf_tail_plus8[`IOB_CPU_BUF_INDEX-1:0] <= cpu_buf_head[`IOB_CPU_BUF_INDEX-1:0]));
dffrl_ns #(1) iob_pcx_stall_pq_ff (.din(cpu_buf_hit_hwm | int_buf_hit_hwm),
.clk(cpu_clk),
.rst_l(cpu_rst_l),
.q(iob_pcx_stall_pq));
endmodule // c2i_fctrl
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__BUFBUF_16_V
`define SKY130_FD_SC_LS__BUFBUF_16_V
/**
* bufbuf: Double buffer.
*
* Verilog wrapper for bufbuf with size of 16 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__bufbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__bufbuf_16 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__bufbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__bufbuf_16 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__bufbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__BUFBUF_16_V
|
//phase 3: testing LSL, LSR, 32bit
`timescale 1ns/10ps
module ARMStb();
reg [31:0] instrbus;
reg [31:0] instrbusin[0:29];
wire [31:0] iaddrbus, dselect;
reg [31:0] iaddrbusout[0:29], dselectout[0:29];
wire [31:0] dbus;
reg [31:0] databusk, dbusout[0:29];
reg clk, reset;
reg clkd;
reg [31:0] dontcare;
reg [24*8:1] iname[0:29];
integer error, k, ntests;
//all opcode parameters to be used
parameter ADD = 11'b10001011000;
parameter ADDI = 10'b1001000100;
parameter ADDIS = 10'b1011000100;
parameter ADDS = 11'b10101011000;
parameter AND = 11'b10001010000;
parameter ANDI = 10'b1001001000;
parameter ANDIS = 10'b1111001000;
parameter ANDS = 11'b11101010000;
parameter CBNZ = 8'b10110101;
parameter CBZ = 8'b10110100;
parameter EOR = 11'b11001010000;
parameter EORI = 10'b1101001000;
parameter LDUR = 11'b11111000010;
parameter LSL = 11'b11010011011;
parameter LSR = 11'b11010011010;
parameter MOVZ = 9'b110100101;
parameter ORR = 11'b10101010000;
parameter ORRI = 10'b1011001000;
parameter STUR = 11'b11111000000;
parameter SUB = 11'b11001011000;
parameter SUBI = 10'b1101000100;
parameter SUBIS = 10'b1111000100;
parameter SUBS = 11'b11101011000;
parameter B = 6'b000101;
parameter B_EQ = 8'b01010101;
parameter B_NE = 8'b01010110;
parameter B_LT = 8'b01010111;
parameter B_GT = 8'b01011000;
//register parameters
parameter R0 = 5'b00000;
parameter R0_dselect = 32'b00000000000000000000000000000001;
parameter R18 = 5'b10010;
parameter R18_dselect = 32'b00000000000001000000000000000000;
parameter R19 = 5'b10011;
parameter R19_dselect = 32'b00000000000010000000000000000000;
parameter R20 = 5'b10100;
parameter R20_dselect = 32'b00000000000100000000000000000000;
parameter R21 = 5'b10101;
parameter R21_dselect = 32'b00000000001000000000000000000000;
parameter R22 = 5'b10110;
parameter R22_dselect = 32'b00000000010000000000000000000000;
parameter R23 = 5'b10111;
parameter R23_dselect = 32'b00000000100000000000000000000000;
parameter R24 = 5'b11000;
parameter R24_dselect = 32'b00000001000000000000000000000000;
parameter R25 = 5'b11001;
parameter R25_dselect = 32'b00000010000000000000000000000000;
parameter R26 = 5'b11010;
parameter R26_dselect = 32'b00000100000000000000000000000000;
parameter R27 = 5'b11011;
parameter R27_dselect = 32'b00001000000000000000000000000000;
parameter R28 = 5'b11100;
parameter R28_dselect = 32'b00010000000000000000000000000000;
parameter R29 = 5'b11101;
parameter R29_dselect = 32'b00100000000000000000000000000000;
parameter R30 = 5'b11110;
parameter R30_dselect = 32'b01000000000000000000000000000000;
parameter R31 = 5'b11111;
parameter R31_dselect = 32'b10000000000000000000000000000000;
//other parameterz to be used
parameter zeroSham = 6'b000000;
parameter RX = 5'b11111;
parameter oneShamt = 6'b000001;
parameter twoShamt = 6'b000010;
parameter threeShamt = 6'b000011;
parameter eightShamt = 6'b001000;
ARMS dut(.reset(reset),.clk(clk),.iaddrbus(iaddrbus),.ibus(instrbus),.dbus(dbus),.dselect(dselect));
initial begin
dontcare = 32'hx;
//phase 1: testing basic op commands and instruction bus
//* ADDI, R20, R31, #AAA
iname[0] = "ADDI, R20, R31, #AAA";//testing addi, result in R20 = 00000AAA
iaddrbusout[0] = 32'h00000000;
// opcode rm/ALUImm rn rd...
instrbusin[0]={ADDI, 12'hAAA, R31, R20};
dselectout[0] = R20_dselect;
dbusout[0] = 32'h00000AAA;
//* ADDI, R31, R23, #002
iname[1] = "ADDI, R31, R23, #002";//testing addi on R31, result in R31 = 00000000
iaddrbusout[1] = 32'h00000004;
// opcode rm/ALUImm rn rd...
instrbusin[1]={ADDI, 12'h002, R23, R31};
dselectout[1] = R31_dselect;
dbusout[1] = dontcare;
//* ADDI, R0, R23, #002
iname[2] = "ADDI, R0, R23, #002";//testing addi on R0, result in R0 = 00000002
iaddrbusout[2] = 32'h00000008;
// opcode rm/ALUImm rn rd...
instrbusin[2]={ADDI, 12'h002, R23, R0};
dselectout[2] = R0_dselect;
dbusout[2] = 32'h00000002;
//* ORRI, R21, R24, #001
iname[3] = "ORRI, R21, R24, #001";//testing ori, result in R21 = 00000001
iaddrbusout[3] = 32'h0000000C;
// opcode rm/ALUImm rn rd...
instrbusin[3]={ORRI, 12'h001, R24, R21};
dselectout[3] = R21_dselect;
dbusout[3] = 32'h00000001;
//* EORI, R22, R20, #000
iname[4] = "EORI, R22, R20, #000";//testing xori, result in R22 = 00000AAA
iaddrbusout[4] = 32'h00000010;
// opcode rm/ALUImm rn rd...
instrbusin[4]={EORI, 12'h000, R20, R22};
dselectout[4] = R22_dselect;
dbusout[4] = 32'h00000AAA;
//* ANDI, R23, R0, #003
iname[5] = "ANDI, R23, R0, #003";//testing andi, result in R23 = 00000002
iaddrbusout[5] = 32'h00000014;
// opcode rm/ALUImm rn rd...
instrbusin[5]={ANDI, 12'h003, R0, R23};
dselectout[5] = R23_dselect;
dbusout[5] = 32'h00000002;
//* SUBI, R24, R20, #00A
iname[6] = "SUBI, R24, R20, #00A";//testing subi, result in R24 = 00000AA0
iaddrbusout[6] = 32'h00000018;
// opcode rm/ALUImm rn rd...
instrbusin[6]={SUBI, 12'h00A, R20, R24};
dselectout[6] = R24_dselect;
dbusout[6] = 32'h00000AA0;
// op, rd, rn, rm
//* ADD, R25, R20, R0
iname[7] = "ADD, R25, R20, R0";//testing add, result in R25 = 00000AAC
iaddrbusout[7] = 32'h0000001C;
// op, rm, shamt, rn, rd
instrbusin[7]={ADD, R0, zeroSham, R20, R25};
dselectout[7] = R25_dselect;
dbusout[7] = 32'h00000AAC;
// op, rd, rn, rm
//* AND, R26, R20, R22
iname[8] = "AND, R26, R20, R22";//testing and, result in R26 = 00000AAA
iaddrbusout[8] = 32'h00000020;
// op, rm, shamt, rn, rd
instrbusin[8]={AND, R22, zeroSham, R20, R26};
dselectout[8] = R26_dselect;
dbusout[8] = 32'h00000AAA;
// op, rd, rn, rm
//* XOR, R27, R23, R21
iname[9] = "EOR, R27, R23, R21";//testing xor, result in R27 = 00000003
iaddrbusout[9] = 32'h00000024;
// op, rm, shamt, rn, rd
instrbusin[9]={EOR, R21, zeroSham, R23, R27};
dselectout[9] = R27_dselect;
dbusout[9] = 32'h00000003;
// op, rd, rn, rm
//* OR, R28, R25, R23
iname[10] = "ORR, R28, R25, R23";//testing or, result in R28 = 00000AAE
iaddrbusout[10] = 32'h00000028;
// op, rm, shamt, rn, rd
instrbusin[10]={ORR, R23, zeroSham, R25, R28};
dselectout[10] = R28_dselect;
dbusout[10] = 32'h00000AAE;
// op, rd, rn, rm
//* SUB, R29, R20, R22
iname[11] = "SUB, R29, R20, R22";//testing sub, result in R29 = 00000000
iaddrbusout[11] = 32'h0000002C;
// op, rm, shamt, rn, rd
instrbusin[11]={SUB, R22, zeroSham, R20, R29};
dselectout[11] = R29_dselect;
dbusout[11] = 32'h00000000;
// op, rd, rn, aluImm
//* ADDI, R30, R31, #000
iname[12] = "ADDI, R30, R31, #000";//testing addi on R31, result in R30 = 00000000
iaddrbusout[12] = 32'h00000030;
// opcode rm/ALUImm rn rd...
instrbusin[12]={ADDI, 12'h000, R31, R30};
dselectout[12] = R30_dselect;
dbusout[12] = 32'h00000000;
//phase 2: testing basic op codes with the n,z,c flags
// op, rd, rn, aluImm
//* SUBIS,R20, R0, #003
iname[13] = "SUBIS,R20, R0, #003";//testing subis, n flag, result in R20 = FFFFFFFF
iaddrbusout[13] = 32'h00000034;
// opcode rm/ALUImm rn rd...
instrbusin[13] = {SUBIS, 12'h003, R0, R20};
dselectout[13] = dontcare;
dbusout[13] = dontcare;
// op, rd, rn, rm
//* SUBS, R21, R25, R28
iname[14] = "SUBS, R21, R25, R28";//testing subs, n flag, result in R21 = FFFFFFFE
iaddrbusout[14] = 32'h00000038;
// op, rm, shamt, rn, rd
instrbusin[14] = {SUBS, R28, zeroSham, R25, R21};
dselectout[14] = dontcare;
dbusout[14] = dontcare;
// op, rd, rn, aluImm
//* ADDIS,R22, R31, #000
iname[15] = "ADDIS,R22, R31, #000";//testing addis, z flag, result in R22 = 00000000
iaddrbusout[15] = 32'h0000003C;
// opcode rm/ALUImm rn rd...
instrbusin[15] = {ADDIS, 12'h000, R31, R22};
dselectout[15] = dontcare;
dbusout[15] = dontcare;
// op, rd, rn, rm
//* ADDS R23, R20, R23
iname[16] = "ADDS R23, R20, R23";//testing adds, c flag, result in R23 = 00000001
iaddrbusout[16] = 32'h00000040;
// op, rm, shamt, rn, rd
instrbusin[16] = {ADDS, R23, zeroSham, R20, R23};
dselectout[16] = dontcare;
dbusout[16] = dontcare;
// op, rd, rn, aluImm
//* ANDIS,R24, R20, #002
iname[17] = "ANDIS,R24, R20, #002";//testing andis, reseting n,z flags to low, result in R24 = 00000002
iaddrbusout[17] = 32'h00000044;
// opcode rm/ALUImm rn rd...
instrbusin[17] = {ANDIS, 12'h002, R20, R24};
dselectout[17] = dontcare;
dbusout[17] = dontcare;
// op, rd, rn, rm
//* ANDS, R25, R21, R20
iname[18] = "ANDS, R25, R21, R20";//testing ands, n flag, result in R25 = FFFFFFFE
iaddrbusout[18] = 32'h00000048;
// op, rm, shamt, rn, rd
instrbusin[18] = {ANDS, R20, zeroSham, R21, R25};
dselectout[18] = dontcare;
dbusout[18] = dontcare;
//phase 3: testing LSL, LSR
//setting up the register R20 for a test of the LSL
// op, rd, rn, rm
iname[19] ="ADDI, R20, R31, #007";//setting up for left shift, result in R20 = 0000000000000007
iaddrbusout[19] = 64'h0000004C;
// opcode rm/ALUImm rn rd
instrbusin[19] ={ADDI, 12'h007, R31, R20};
dselectout[19] = R20_dselect;
dbusout[19] = 64'h00000007;
// op, rd, rn, rm
iname[20] ="ADDI, R21, R31, #700";//setting up for right shift, n flag, result in R21 = 0000000000000700
iaddrbusout[20] = 64'h00000050;
// opcode rm/ALUImm rn rd
instrbusin[20] ={ADDI, 12'h700, R31, R21};
dselectout[20] = R21_dselect;
dbusout[20] = 64'h00000700;
// op, rd, rn, rm
iname[21] ="AND, R19, R31, R31";//delay, result in R19 = 0000000000000000
iaddrbusout[21] = 64'h00000054;
// op, rm, shamt, rn, rd
instrbusin[21] ={AND, R31, zeroSham, R31, R19};
dselectout[21] = R19_dselect;
dbusout[21] = 64'h00000000;
// op, rd, rn, rm
iname[22] ="AND, R18, R31, R31";//delay, result in R18 = 0000000000000000
iaddrbusout[22] = 64'h00000058;
// op, rm, shamt, rn, rd
instrbusin[22] ={AND, R31, zeroSham, R31, R18};
dselectout[22] = R18_dselect;
dbusout[22] = 64'h00000000;
// op, rd, rn, rm
iname[23] ="LSL, R20, R20, 2";//testing left shift, result in R20 = 0000000000000700
iaddrbusout[23] = 64'h0000005C;
// op, rm, shamt, rn, rd
instrbusin[23] ={LSL, RX, eightShamt, R20, R20};
dselectout[23] = R20_dselect;
dbusout[23] = 64'h00000700;
// op, rd, rn, rm
iname[24] ="LSR, R21, R21, 2";//testing right shift, result in R21 = 0000000000000007
iaddrbusout[24] = 64'h00000060;
// op, rm, shamt, rn, rd
instrbusin[24] ={LSR, RX, eightShamt, R21, R21};
dselectout[24] = R21_dselect;
dbusout[24] = 64'h00000007;
//finishing up
iname[25] = "NOP";//nada
iaddrbusout[25] = 64'h00000064;
instrbusin[25] = 64'b0;
dselectout[25] = dontcare;
dbusout[25] = dontcare;
iname[26] = "NOP";//nada
iaddrbusout[26] = 64'h00000068;
instrbusin[26] = 64'b0;
dselectout[26] = dontcare;
dbusout[26] = dontcare;
iname[27] = "NOP";//nada
iaddrbusout[27] = 64'h0000006C;
instrbusin[27] = 64'b0;
dselectout[27] = dontcare;
dbusout[27] = dontcare;
iname[28] = "NOP";//nada
iaddrbusout[28] = 64'h00000070;
instrbusin[28] = 64'b0;
dselectout[28] = dontcare;
dbusout[28] = dontcare;
iname[29] = "NOP";//nada
iaddrbusout[29] = 64'h00000074;
instrbusin[29] = 64'b0;
dselectout[29] = dontcare;
dbusout[29] = dontcare;
//remember to set k down below to ntests - 1
ntests = 30;
$timeformat(-9,1,"ns",12);
end
//assumes positive edge FF.
//testbench reads databus when clk high, writes databus when clk low.
//assign databus = clkd ? 64'bz : databusk;
//Change inputs in middle of period (falling edge).
initial begin
error = 0;
clkd =1;
clk=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
//databusk = 64'bz;
//extended reset to set up PC MUX
reset = 1;
$display ("reset=%b", reset);
#5
clk=0;
clkd=0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
clk=1;
clkd=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
clk=0;
clkd=0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
$display ("Time=%t\n clk=%b", $realtime, clk);
for (k=0; k<= 29; k=k+1) begin
clk=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
#2
clkd=1;
#3
$display ("Time=%t\n clk=%b", $realtime, clk);
reset = 0;
$display ("reset=%b", reset);
//set dbus and dselect data data for 4th previous instruction
if (k >=4)
//databusk = databusin[k-4];
//check PC for this instruction
if (k >= 0) begin
$display (" Testing PC for instruction %d", k);
$display (" Your iaddrbus = %b", iaddrbus);
$display (" Correct iaddrbus = %b", iaddrbusout[k]);
if (iaddrbusout[k] !== iaddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
//put next instruction on ibus
instrbus=instrbusin[k];
$display (" instrbus=%b%b%b%b%b for instruction %d: %s", instrbus[31:26], instrbus[25:21], instrbus[20:16], instrbus[15:11], instrbus[10:0], k, iname[k]);
//check writeback data address from 4th previous instruction
if ( (k >= 4) && (dselectout[k-4] !== dontcare) ) begin
$display (" Testing writeback data address for instruction %d:", k-4);
$display (" %s", iname[k-4]);
$display (" Your dselect = %b", dselect);
$display (" Correct dselect = %b", dselectout[k-4]);
if (dselectout[k-4] !== dselect) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
//check writeback data from 4th previous instruction
if ( (k >= 4) && (dbusout[k-4] !== dontcare) ) begin
$display (" Testing writeback data for instruction %d:", k-4);
$display (" %s", iname[k-4]);
$display (" Your dbus = %b", dbus);
$display (" Correct dbus = %b", dbusout[k-4]);
if (dbusout[k-4] !== dbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
clk = 0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#2
clkd = 0;
#3
$display ("Time=%t\n clk=%b", $realtime, clk);
end
if ( error !== 0) begin
$display("--------- SIMULATION UNSUCCESFUL - MISMATCHES HAVE OCCURED ----------");
$display(" No. Of Errors = %d", error);
end
if ( error == 0)
$display("---------YOU DID IT!! SIMULATION SUCCESFULLY FINISHED----------");
end
endmodule
|
// CONFIG:
// NUM_COEFF = 34
// PIPLINED = 1
// WARNING: more than enough COEFFICIENTS in array (there are 26, and we only need 17)
module fir (
clk,
reset,
clk_ena,
i_valid,
i_in,
o_valid,
o_out
);
// Data Width
parameter dw = 18; //Data input/output bits
// Number of filter coefficients
parameter N = 34;
parameter N_UNIQ = 17; // ciel(N/2) assuming symmetric filter coefficients
//Number of extra valid cycles needed to align output (i.e. computation pipeline depth + input/output registers
localparam N_VALID_REGS = 41;
input clk;
input reset;
input clk_ena;
input i_valid;
input [dw-1:0] i_in; // signed
output o_valid;
output [dw-1:0] o_out; // signed
// Data Width dervied parameters
localparam dw_add_int = 18; //Internal adder precision bits
localparam dw_mult_int = 36; //Internal multiplier precision bits
localparam scale_factor = 17; //Multiplier normalization shift amount
// Number of extra registers in INPUT_PIPELINE_REG to prevent contention for CHAIN_END's chain adders
localparam N_INPUT_REGS = 34;
// Debug
// initial begin
// $display ("Data Width: %d", dw);
// $display ("Data Width Add Internal: %d", dw_add_int);
// $display ("Data Width Mult Internal: %d", dw_mult_int);
// $display ("Scale Factor: %d", scale_factor);
// end
reg [dw-1:0] COEFFICIENT_0;
reg [dw-1:0] COEFFICIENT_1;
reg [dw-1:0] COEFFICIENT_2;
reg [dw-1:0] COEFFICIENT_3;
reg [dw-1:0] COEFFICIENT_4;
reg [dw-1:0] COEFFICIENT_5;
reg [dw-1:0] COEFFICIENT_6;
reg [dw-1:0] COEFFICIENT_7;
reg [dw-1:0] COEFFICIENT_8;
reg [dw-1:0] COEFFICIENT_9;
reg [dw-1:0] COEFFICIENT_10;
reg [dw-1:0] COEFFICIENT_11;
reg [dw-1:0] COEFFICIENT_12;
reg [dw-1:0] COEFFICIENT_13;
reg [dw-1:0] COEFFICIENT_14;
reg [dw-1:0] COEFFICIENT_15;
reg [dw-1:0] COEFFICIENT_16;
always@(posedge clk) begin
COEFFICIENT_0 <= 18'd88;
COEFFICIENT_1 <= 18'd0;
COEFFICIENT_2 <= -18'd97;
COEFFICIENT_3 <= -18'd197;
COEFFICIENT_4 <= -18'd294;
COEFFICIENT_5 <= -18'd380;
COEFFICIENT_6 <= -18'd447;
COEFFICIENT_7 <= -18'd490;
COEFFICIENT_8 <= -18'd504;
COEFFICIENT_9 <= -18'd481;
COEFFICIENT_10 <= -18'd420;
COEFFICIENT_11 <= -18'd319;
COEFFICIENT_12 <= -18'd178;
COEFFICIENT_13 <= 18'd0;
COEFFICIENT_14 <= 18'd212;
COEFFICIENT_15 <= 18'd451;
COEFFICIENT_16 <= 18'd710;
end
////******************************************************
// *
// * Valid Delay Pipeline
// *
// *****************************************************
//Input valid signal is pipelined to become output valid signal
//Valid registers
reg [N_VALID_REGS-1:0] VALID_PIPELINE_REGS;
always@(posedge clk or posedge reset) begin
if(reset) begin
VALID_PIPELINE_REGS <= 0;
end else begin
if(clk_ena) begin
VALID_PIPELINE_REGS <= {VALID_PIPELINE_REGS[N_VALID_REGS-2:0], i_valid};
end else begin
VALID_PIPELINE_REGS <= VALID_PIPELINE_REGS;
end
end
end
////******************************************************
// *
// * Input Register Pipeline
// *
// *****************************************************
//Pipelined input values
//Input value registers
wire [dw-1:0] INPUT_PIPELINE_REG_0;
wire [dw-1:0] INPUT_PIPELINE_REG_1;
wire [dw-1:0] INPUT_PIPELINE_REG_2;
wire [dw-1:0] INPUT_PIPELINE_REG_3;
wire [dw-1:0] INPUT_PIPELINE_REG_4;
wire [dw-1:0] INPUT_PIPELINE_REG_5;
wire [dw-1:0] INPUT_PIPELINE_REG_6;
wire [dw-1:0] INPUT_PIPELINE_REG_7;
wire [dw-1:0] INPUT_PIPELINE_REG_8;
wire [dw-1:0] INPUT_PIPELINE_REG_9;
wire [dw-1:0] INPUT_PIPELINE_REG_10;
wire [dw-1:0] INPUT_PIPELINE_REG_11;
wire [dw-1:0] INPUT_PIPELINE_REG_12;
wire [dw-1:0] INPUT_PIPELINE_REG_13;
wire [dw-1:0] INPUT_PIPELINE_REG_14;
wire [dw-1:0] INPUT_PIPELINE_REG_15;
wire [dw-1:0] INPUT_PIPELINE_REG_16;
wire [dw-1:0] INPUT_PIPELINE_REG_17;
wire [dw-1:0] INPUT_PIPELINE_REG_18;
wire [dw-1:0] INPUT_PIPELINE_REG_19;
wire [dw-1:0] INPUT_PIPELINE_REG_20;
wire [dw-1:0] INPUT_PIPELINE_REG_21;
wire [dw-1:0] INPUT_PIPELINE_REG_22;
wire [dw-1:0] INPUT_PIPELINE_REG_23;
wire [dw-1:0] INPUT_PIPELINE_REG_24;
wire [dw-1:0] INPUT_PIPELINE_REG_25;
wire [dw-1:0] INPUT_PIPELINE_REG_26;
wire [dw-1:0] INPUT_PIPELINE_REG_27;
wire [dw-1:0] INPUT_PIPELINE_REG_28;
wire [dw-1:0] INPUT_PIPELINE_REG_29;
wire [dw-1:0] INPUT_PIPELINE_REG_30;
wire [dw-1:0] INPUT_PIPELINE_REG_31;
wire [dw-1:0] INPUT_PIPELINE_REG_32;
wire [dw-1:0] INPUT_PIPELINE_REG_33;
input_pipeline in_pipe(
.clk(clk), .clk_ena(clk_ena),
.in_stream(i_in),
.pipeline_reg_0(INPUT_PIPELINE_REG_0),
.pipeline_reg_1(INPUT_PIPELINE_REG_1),
.pipeline_reg_2(INPUT_PIPELINE_REG_2),
.pipeline_reg_3(INPUT_PIPELINE_REG_3),
.pipeline_reg_4(INPUT_PIPELINE_REG_4),
.pipeline_reg_5(INPUT_PIPELINE_REG_5),
.pipeline_reg_6(INPUT_PIPELINE_REG_6),
.pipeline_reg_7(INPUT_PIPELINE_REG_7),
.pipeline_reg_8(INPUT_PIPELINE_REG_8),
.pipeline_reg_9(INPUT_PIPELINE_REG_9),
.pipeline_reg_10(INPUT_PIPELINE_REG_10),
.pipeline_reg_11(INPUT_PIPELINE_REG_11),
.pipeline_reg_12(INPUT_PIPELINE_REG_12),
.pipeline_reg_13(INPUT_PIPELINE_REG_13),
.pipeline_reg_14(INPUT_PIPELINE_REG_14),
.pipeline_reg_15(INPUT_PIPELINE_REG_15),
.pipeline_reg_16(INPUT_PIPELINE_REG_16),
.pipeline_reg_17(INPUT_PIPELINE_REG_17),
.pipeline_reg_18(INPUT_PIPELINE_REG_18),
.pipeline_reg_19(INPUT_PIPELINE_REG_19),
.pipeline_reg_20(INPUT_PIPELINE_REG_20),
.pipeline_reg_21(INPUT_PIPELINE_REG_21),
.pipeline_reg_22(INPUT_PIPELINE_REG_22),
.pipeline_reg_23(INPUT_PIPELINE_REG_23),
.pipeline_reg_24(INPUT_PIPELINE_REG_24),
.pipeline_reg_25(INPUT_PIPELINE_REG_25),
.pipeline_reg_26(INPUT_PIPELINE_REG_26),
.pipeline_reg_27(INPUT_PIPELINE_REG_27),
.pipeline_reg_28(INPUT_PIPELINE_REG_28),
.pipeline_reg_29(INPUT_PIPELINE_REG_29),
.pipeline_reg_30(INPUT_PIPELINE_REG_30),
.pipeline_reg_31(INPUT_PIPELINE_REG_31),
.pipeline_reg_32(INPUT_PIPELINE_REG_32),
.pipeline_reg_33(INPUT_PIPELINE_REG_33),
.reset(reset) );
defparam in_pipe.WIDTH = 18; // = dw
////******************************************************
// *
// * Computation Pipeline
// *
// *****************************************************
// ************************* LEVEL 0 ************************* \\
wire [dw-1:0] L0_output_wires_0;
wire [dw-1:0] L0_output_wires_1;
wire [dw-1:0] L0_output_wires_2;
wire [dw-1:0] L0_output_wires_3;
wire [dw-1:0] L0_output_wires_4;
wire [dw-1:0] L0_output_wires_5;
wire [dw-1:0] L0_output_wires_6;
wire [dw-1:0] L0_output_wires_7;
wire [dw-1:0] L0_output_wires_8;
wire [dw-1:0] L0_output_wires_9;
wire [dw-1:0] L0_output_wires_10;
wire [dw-1:0] L0_output_wires_11;
wire [dw-1:0] L0_output_wires_12;
wire [dw-1:0] L0_output_wires_13;
wire [dw-1:0] L0_output_wires_14;
wire [dw-1:0] L0_output_wires_15;
wire [dw-1:0] L0_output_wires_16;
adder_with_1_reg L0_adder_0and33(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_0),
.datab (INPUT_PIPELINE_REG_33),
.result(L0_output_wires_0)
);
adder_with_1_reg L0_adder_1and32(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_1),
.datab (INPUT_PIPELINE_REG_32),
.result(L0_output_wires_1)
);
adder_with_1_reg L0_adder_2and31(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_2),
.datab (INPUT_PIPELINE_REG_31),
.result(L0_output_wires_2)
);
adder_with_1_reg L0_adder_3and30(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_3),
.datab (INPUT_PIPELINE_REG_30),
.result(L0_output_wires_3)
);
adder_with_1_reg L0_adder_4and29(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_4),
.datab (INPUT_PIPELINE_REG_29),
.result(L0_output_wires_4)
);
adder_with_1_reg L0_adder_5and28(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_5),
.datab (INPUT_PIPELINE_REG_28),
.result(L0_output_wires_5)
);
adder_with_1_reg L0_adder_6and27(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_6),
.datab (INPUT_PIPELINE_REG_27),
.result(L0_output_wires_6)
);
adder_with_1_reg L0_adder_7and26(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_7),
.datab (INPUT_PIPELINE_REG_26),
.result(L0_output_wires_7)
);
adder_with_1_reg L0_adder_8and25(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_8),
.datab (INPUT_PIPELINE_REG_25),
.result(L0_output_wires_8)
);
adder_with_1_reg L0_adder_9and24(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_9),
.datab (INPUT_PIPELINE_REG_24),
.result(L0_output_wires_9)
);
adder_with_1_reg L0_adder_10and23(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_10),
.datab (INPUT_PIPELINE_REG_23),
.result(L0_output_wires_10)
);
adder_with_1_reg L0_adder_11and22(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_11),
.datab (INPUT_PIPELINE_REG_22),
.result(L0_output_wires_11)
);
adder_with_1_reg L0_adder_12and21(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_12),
.datab (INPUT_PIPELINE_REG_21),
.result(L0_output_wires_12)
);
adder_with_1_reg L0_adder_13and20(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_13),
.datab (INPUT_PIPELINE_REG_20),
.result(L0_output_wires_13)
);
adder_with_1_reg L0_adder_14and19(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_14),
.datab (INPUT_PIPELINE_REG_19),
.result(L0_output_wires_14)
);
adder_with_1_reg L0_adder_15and18(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_15),
.datab (INPUT_PIPELINE_REG_18),
.result(L0_output_wires_15)
);
adder_with_1_reg L0_adder_16and17(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_16),
.datab (INPUT_PIPELINE_REG_17),
.result(L0_output_wires_16)
);
// (17 main tree Adders)
// ************************* LEVEL 1 ************************* \\
// **************** Multipliers **************** \\
wire [dw-1:0] L1_mult_wires_0;
wire [dw-1:0] L1_mult_wires_1;
wire [dw-1:0] L1_mult_wires_2;
wire [dw-1:0] L1_mult_wires_3;
wire [dw-1:0] L1_mult_wires_4;
wire [dw-1:0] L1_mult_wires_5;
wire [dw-1:0] L1_mult_wires_6;
wire [dw-1:0] L1_mult_wires_7;
wire [dw-1:0] L1_mult_wires_8;
wire [dw-1:0] L1_mult_wires_9;
wire [dw-1:0] L1_mult_wires_10;
wire [dw-1:0] L1_mult_wires_11;
wire [dw-1:0] L1_mult_wires_12;
wire [dw-1:0] L1_mult_wires_13;
wire [dw-1:0] L1_mult_wires_14;
wire [dw-1:0] L1_mult_wires_15;
wire [dw-1:0] L1_mult_wires_16;
multiplier_with_reg L1_mul_0(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_0),
.datab (COEFFICIENT_0),
.result(L1_mult_wires_0)
);
multiplier_with_reg L1_mul_1(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_1),
.datab (COEFFICIENT_1),
.result(L1_mult_wires_1)
);
multiplier_with_reg L1_mul_2(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_2),
.datab (COEFFICIENT_2),
.result(L1_mult_wires_2)
);
multiplier_with_reg L1_mul_3(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_3),
.datab (COEFFICIENT_3),
.result(L1_mult_wires_3)
);
multiplier_with_reg L1_mul_4(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_4),
.datab (COEFFICIENT_4),
.result(L1_mult_wires_4)
);
multiplier_with_reg L1_mul_5(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_5),
.datab (COEFFICIENT_5),
.result(L1_mult_wires_5)
);
multiplier_with_reg L1_mul_6(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_6),
.datab (COEFFICIENT_6),
.result(L1_mult_wires_6)
);
multiplier_with_reg L1_mul_7(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_7),
.datab (COEFFICIENT_7),
.result(L1_mult_wires_7)
);
multiplier_with_reg L1_mul_8(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_8),
.datab (COEFFICIENT_8),
.result(L1_mult_wires_8)
);
multiplier_with_reg L1_mul_9(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_9),
.datab (COEFFICIENT_9),
.result(L1_mult_wires_9)
);
multiplier_with_reg L1_mul_10(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_10),
.datab (COEFFICIENT_10),
.result(L1_mult_wires_10)
);
multiplier_with_reg L1_mul_11(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_11),
.datab (COEFFICIENT_11),
.result(L1_mult_wires_11)
);
multiplier_with_reg L1_mul_12(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_12),
.datab (COEFFICIENT_12),
.result(L1_mult_wires_12)
);
multiplier_with_reg L1_mul_13(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_13),
.datab (COEFFICIENT_13),
.result(L1_mult_wires_13)
);
multiplier_with_reg L1_mul_14(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_14),
.datab (COEFFICIENT_14),
.result(L1_mult_wires_14)
);
multiplier_with_reg L1_mul_15(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_15),
.datab (COEFFICIENT_15),
.result(L1_mult_wires_15)
);
multiplier_with_reg L1_mul_16(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_16),
.datab (COEFFICIENT_16),
.result(L1_mult_wires_16)
);
// (17 Multipliers)
// **************** Adders **************** \\
wire [dw-1:0] L1_output_wires_0;
wire [dw-1:0] L1_output_wires_1;
wire [dw-1:0] L1_output_wires_2;
wire [dw-1:0] L1_output_wires_3;
wire [dw-1:0] L1_output_wires_4;
wire [dw-1:0] L1_output_wires_5;
wire [dw-1:0] L1_output_wires_6;
wire [dw-1:0] L1_output_wires_7;
wire [dw-1:0] L1_output_wires_8;
adder_with_1_reg L1_adder_0and1(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_mult_wires_0),
.datab (L1_mult_wires_1),
.result(L1_output_wires_0)
);
adder_with_1_reg L1_adder_2and3(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_mult_wires_2),
.datab (L1_mult_wires_3),
.result(L1_output_wires_1)
);
adder_with_1_reg L1_adder_4and5(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_mult_wires_4),
.datab (L1_mult_wires_5),
.result(L1_output_wires_2)
);
adder_with_1_reg L1_adder_6and7(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_mult_wires_6),
.datab (L1_mult_wires_7),
.result(L1_output_wires_3)
);
adder_with_1_reg L1_adder_8and9(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_mult_wires_8),
.datab (L1_mult_wires_9),
.result(L1_output_wires_4)
);
adder_with_1_reg L1_adder_10and11(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_mult_wires_10),
.datab (L1_mult_wires_11),
.result(L1_output_wires_5)
);
adder_with_1_reg L1_adder_12and13(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_mult_wires_12),
.datab (L1_mult_wires_13),
.result(L1_output_wires_6)
);
adder_with_1_reg L1_adder_14and15(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_mult_wires_14),
.datab (L1_mult_wires_15),
.result(L1_output_wires_7)
);
// (8 main tree Adders)
// ********* Byes ******** \\
one_register L1_byereg_for_16(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_mult_wires_16),
.result(L1_output_wires_8)
);
// (1 byes)
// ************************* LEVEL 2 ************************* \\
wire [dw-1:0] L2_output_wires_0;
wire [dw-1:0] L2_output_wires_1;
wire [dw-1:0] L2_output_wires_2;
wire [dw-1:0] L2_output_wires_3;
wire [dw-1:0] L2_output_wires_4;
adder_with_1_reg L2_adder_0and1(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_output_wires_0),
.datab (L1_output_wires_1),
.result(L2_output_wires_0)
);
adder_with_1_reg L2_adder_2and3(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_output_wires_2),
.datab (L1_output_wires_3),
.result(L2_output_wires_1)
);
adder_with_1_reg L2_adder_4and5(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_output_wires_4),
.datab (L1_output_wires_5),
.result(L2_output_wires_2)
);
adder_with_1_reg L2_adder_6and7(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_output_wires_6),
.datab (L1_output_wires_7),
.result(L2_output_wires_3)
);
// (4 main tree Adders)
// ********* Byes ******** \\
one_register L2_byereg_for_8(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_output_wires_8),
.result(L2_output_wires_4)
);
// (1 byes)
// ************************* LEVEL 3 ************************* \\
wire [dw-1:0] L3_output_wires_0;
wire [dw-1:0] L3_output_wires_1;
wire [dw-1:0] L3_output_wires_2;
adder_with_1_reg L3_adder_0and1(
.clk(clk), .clk_ena(clk_ena),
.dataa (L2_output_wires_0),
.datab (L2_output_wires_1),
.result(L3_output_wires_0)
);
adder_with_1_reg L3_adder_2and3(
.clk(clk), .clk_ena(clk_ena),
.dataa (L2_output_wires_2),
.datab (L2_output_wires_3),
.result(L3_output_wires_1)
);
// (2 main tree Adders)
// ********* Byes ******** \\
one_register L3_byereg_for_4(
.clk(clk), .clk_ena(clk_ena),
.dataa (L2_output_wires_4),
.result(L3_output_wires_2)
);
// (1 byes)
// ************************* LEVEL 4 ************************* \\
wire [dw-1:0] L4_output_wires_0;
wire [dw-1:0] L4_output_wires_1;
adder_with_1_reg L4_adder_0and1(
.clk(clk), .clk_ena(clk_ena),
.dataa (L3_output_wires_0),
.datab (L3_output_wires_1),
.result(L4_output_wires_0)
);
// (1 main tree Adders)
// ********* Byes ******** \\
one_register L4_byereg_for_2(
.clk(clk), .clk_ena(clk_ena),
.dataa (L3_output_wires_2),
.result(L4_output_wires_1)
);
// (1 byes)
// ************************* LEVEL 5 ************************* \\
wire [dw-1:0] L5_output_wires_0;
adder_with_1_reg L5_adder_0and1(
.clk(clk), .clk_ena(clk_ena),
.dataa (L4_output_wires_0),
.datab (L4_output_wires_1),
.result(L5_output_wires_0)
);
// (1 main tree Adders)
////******************************************************
// *
// * Output Logic
// *
// *****************************************************
//Actual outputs
assign o_out = L5_output_wires_0;
assign o_valid = VALID_PIPELINE_REGS[N_VALID_REGS-1];
endmodule
module input_pipeline (
clk,
clk_ena,
in_stream,
pipeline_reg_0,
pipeline_reg_1,
pipeline_reg_2,
pipeline_reg_3,
pipeline_reg_4,
pipeline_reg_5,
pipeline_reg_6,
pipeline_reg_7,
pipeline_reg_8,
pipeline_reg_9,
pipeline_reg_10,
pipeline_reg_11,
pipeline_reg_12,
pipeline_reg_13,
pipeline_reg_14,
pipeline_reg_15,
pipeline_reg_16,
pipeline_reg_17,
pipeline_reg_18,
pipeline_reg_19,
pipeline_reg_20,
pipeline_reg_21,
pipeline_reg_22,
pipeline_reg_23,
pipeline_reg_24,
pipeline_reg_25,
pipeline_reg_26,
pipeline_reg_27,
pipeline_reg_28,
pipeline_reg_29,
pipeline_reg_30,
pipeline_reg_31,
pipeline_reg_32,
pipeline_reg_33,
reset);
parameter WIDTH = 1;
//Input value registers
input clk;
input clk_ena;
input [WIDTH-1:0] in_stream;
output [WIDTH-1:0] pipeline_reg_0;
output [WIDTH-1:0] pipeline_reg_1;
output [WIDTH-1:0] pipeline_reg_2;
output [WIDTH-1:0] pipeline_reg_3;
output [WIDTH-1:0] pipeline_reg_4;
output [WIDTH-1:0] pipeline_reg_5;
output [WIDTH-1:0] pipeline_reg_6;
output [WIDTH-1:0] pipeline_reg_7;
output [WIDTH-1:0] pipeline_reg_8;
output [WIDTH-1:0] pipeline_reg_9;
output [WIDTH-1:0] pipeline_reg_10;
output [WIDTH-1:0] pipeline_reg_11;
output [WIDTH-1:0] pipeline_reg_12;
output [WIDTH-1:0] pipeline_reg_13;
output [WIDTH-1:0] pipeline_reg_14;
output [WIDTH-1:0] pipeline_reg_15;
output [WIDTH-1:0] pipeline_reg_16;
output [WIDTH-1:0] pipeline_reg_17;
output [WIDTH-1:0] pipeline_reg_18;
output [WIDTH-1:0] pipeline_reg_19;
output [WIDTH-1:0] pipeline_reg_20;
output [WIDTH-1:0] pipeline_reg_21;
output [WIDTH-1:0] pipeline_reg_22;
output [WIDTH-1:0] pipeline_reg_23;
output [WIDTH-1:0] pipeline_reg_24;
output [WIDTH-1:0] pipeline_reg_25;
output [WIDTH-1:0] pipeline_reg_26;
output [WIDTH-1:0] pipeline_reg_27;
output [WIDTH-1:0] pipeline_reg_28;
output [WIDTH-1:0] pipeline_reg_29;
output [WIDTH-1:0] pipeline_reg_30;
output [WIDTH-1:0] pipeline_reg_31;
output [WIDTH-1:0] pipeline_reg_32;
output [WIDTH-1:0] pipeline_reg_33;
reg [WIDTH-1:0] pipeline_reg_0;
reg [WIDTH-1:0] pipeline_reg_1;
reg [WIDTH-1:0] pipeline_reg_2;
reg [WIDTH-1:0] pipeline_reg_3;
reg [WIDTH-1:0] pipeline_reg_4;
reg [WIDTH-1:0] pipeline_reg_5;
reg [WIDTH-1:0] pipeline_reg_6;
reg [WIDTH-1:0] pipeline_reg_7;
reg [WIDTH-1:0] pipeline_reg_8;
reg [WIDTH-1:0] pipeline_reg_9;
reg [WIDTH-1:0] pipeline_reg_10;
reg [WIDTH-1:0] pipeline_reg_11;
reg [WIDTH-1:0] pipeline_reg_12;
reg [WIDTH-1:0] pipeline_reg_13;
reg [WIDTH-1:0] pipeline_reg_14;
reg [WIDTH-1:0] pipeline_reg_15;
reg [WIDTH-1:0] pipeline_reg_16;
reg [WIDTH-1:0] pipeline_reg_17;
reg [WIDTH-1:0] pipeline_reg_18;
reg [WIDTH-1:0] pipeline_reg_19;
reg [WIDTH-1:0] pipeline_reg_20;
reg [WIDTH-1:0] pipeline_reg_21;
reg [WIDTH-1:0] pipeline_reg_22;
reg [WIDTH-1:0] pipeline_reg_23;
reg [WIDTH-1:0] pipeline_reg_24;
reg [WIDTH-1:0] pipeline_reg_25;
reg [WIDTH-1:0] pipeline_reg_26;
reg [WIDTH-1:0] pipeline_reg_27;
reg [WIDTH-1:0] pipeline_reg_28;
reg [WIDTH-1:0] pipeline_reg_29;
reg [WIDTH-1:0] pipeline_reg_30;
reg [WIDTH-1:0] pipeline_reg_31;
reg [WIDTH-1:0] pipeline_reg_32;
reg [WIDTH-1:0] pipeline_reg_33;
input reset;
always@(posedge clk or posedge reset) begin
if(reset) begin
pipeline_reg_0 <= 0;
pipeline_reg_1 <= 0;
pipeline_reg_2 <= 0;
pipeline_reg_3 <= 0;
pipeline_reg_4 <= 0;
pipeline_reg_5 <= 0;
pipeline_reg_6 <= 0;
pipeline_reg_7 <= 0;
pipeline_reg_8 <= 0;
pipeline_reg_9 <= 0;
pipeline_reg_10 <= 0;
pipeline_reg_11 <= 0;
pipeline_reg_12 <= 0;
pipeline_reg_13 <= 0;
pipeline_reg_14 <= 0;
pipeline_reg_15 <= 0;
pipeline_reg_16 <= 0;
pipeline_reg_17 <= 0;
pipeline_reg_18 <= 0;
pipeline_reg_19 <= 0;
pipeline_reg_20 <= 0;
pipeline_reg_21 <= 0;
pipeline_reg_22 <= 0;
pipeline_reg_23 <= 0;
pipeline_reg_24 <= 0;
pipeline_reg_25 <= 0;
pipeline_reg_26 <= 0;
pipeline_reg_27 <= 0;
pipeline_reg_28 <= 0;
pipeline_reg_29 <= 0;
pipeline_reg_30 <= 0;
pipeline_reg_31 <= 0;
pipeline_reg_32 <= 0;
pipeline_reg_33 <= 0;
end else begin
if(clk_ena) begin
pipeline_reg_0 <= in_stream;
pipeline_reg_1 <= pipeline_reg_0;
pipeline_reg_2 <= pipeline_reg_1;
pipeline_reg_3 <= pipeline_reg_2;
pipeline_reg_4 <= pipeline_reg_3;
pipeline_reg_5 <= pipeline_reg_4;
pipeline_reg_6 <= pipeline_reg_5;
pipeline_reg_7 <= pipeline_reg_6;
pipeline_reg_8 <= pipeline_reg_7;
pipeline_reg_9 <= pipeline_reg_8;
pipeline_reg_10 <= pipeline_reg_9;
pipeline_reg_11 <= pipeline_reg_10;
pipeline_reg_12 <= pipeline_reg_11;
pipeline_reg_13 <= pipeline_reg_12;
pipeline_reg_14 <= pipeline_reg_13;
pipeline_reg_15 <= pipeline_reg_14;
pipeline_reg_16 <= pipeline_reg_15;
pipeline_reg_17 <= pipeline_reg_16;
pipeline_reg_18 <= pipeline_reg_17;
pipeline_reg_19 <= pipeline_reg_18;
pipeline_reg_20 <= pipeline_reg_19;
pipeline_reg_21 <= pipeline_reg_20;
pipeline_reg_22 <= pipeline_reg_21;
pipeline_reg_23 <= pipeline_reg_22;
pipeline_reg_24 <= pipeline_reg_23;
pipeline_reg_25 <= pipeline_reg_24;
pipeline_reg_26 <= pipeline_reg_25;
pipeline_reg_27 <= pipeline_reg_26;
pipeline_reg_28 <= pipeline_reg_27;
pipeline_reg_29 <= pipeline_reg_28;
pipeline_reg_30 <= pipeline_reg_29;
pipeline_reg_31 <= pipeline_reg_30;
pipeline_reg_32 <= pipeline_reg_31;
pipeline_reg_33 <= pipeline_reg_32;
end //else begin
//pipeline_reg_0 <= pipeline_reg_0;
//pipeline_reg_1 <= pipeline_reg_1;
//pipeline_reg_2 <= pipeline_reg_2;
//pipeline_reg_3 <= pipeline_reg_3;
//pipeline_reg_4 <= pipeline_reg_4;
//pipeline_reg_5 <= pipeline_reg_5;
//pipeline_reg_6 <= pipeline_reg_6;
//pipeline_reg_7 <= pipeline_reg_7;
//pipeline_reg_8 <= pipeline_reg_8;
//pipeline_reg_9 <= pipeline_reg_9;
//pipeline_reg_10 <= pipeline_reg_10;
//pipeline_reg_11 <= pipeline_reg_11;
//pipeline_reg_12 <= pipeline_reg_12;
//pipeline_reg_13 <= pipeline_reg_13;
//pipeline_reg_14 <= pipeline_reg_14;
//pipeline_reg_15 <= pipeline_reg_15;
//pipeline_reg_16 <= pipeline_reg_16;
//pipeline_reg_17 <= pipeline_reg_17;
//pipeline_reg_18 <= pipeline_reg_18;
//pipeline_reg_19 <= pipeline_reg_19;
//pipeline_reg_20 <= pipeline_reg_20;
//pipeline_reg_21 <= pipeline_reg_21;
//pipeline_reg_22 <= pipeline_reg_22;
//pipeline_reg_23 <= pipeline_reg_23;
//pipeline_reg_24 <= pipeline_reg_24;
//pipeline_reg_25 <= pipeline_reg_25;
//pipeline_reg_26 <= pipeline_reg_26;
//pipeline_reg_27 <= pipeline_reg_27;
//pipeline_reg_28 <= pipeline_reg_28;
//pipeline_reg_29 <= pipeline_reg_29;
//pipeline_reg_30 <= pipeline_reg_30;
//pipeline_reg_31 <= pipeline_reg_31;
//pipeline_reg_32 <= pipeline_reg_32;
//pipeline_reg_33 <= pipeline_reg_33;
//end
end
end
endmodule
module adder_with_1_reg (
clk,
clk_ena,
dataa,
datab,
result);
input clk;
input clk_ena;
input [17:0] dataa;
input [17:0] datab;
output [17:0] result;
reg [17:0] result;
always @(posedge clk) begin
if(clk_ena) begin
result <= dataa + datab;
end
end
endmodule
module multiplier_with_reg (
clk,
clk_ena,
dataa,
datab,
result);
input clk;
input clk_ena;
input [17:0] dataa;
input [17:0] datab;
output [17:0] result;
reg [17:0] result;
always @(posedge clk) begin
if(clk_ena) begin
result <= dataa * datab;
end
end
endmodule
module one_register (
clk,
clk_ena,
dataa,
result);
input clk;
input clk_ena;
input [17:0] dataa;
output [17:0] result;
reg [17:0] result;
always @(posedge clk) begin
if(clk_ena) begin
result <= dataa;
end
end
endmodule
|
`timescale 1ns / 1ps
module orlink(
input wb_clk,
input wb_rst,
input ifclk_in,
inout [7:0] fifoData_io,
input gotData_in,
input gotRoom_in,
output sloe_out,
output slrd_out,
output slwr_out,
output reg [1:0] fifoAddr_out,
output reg pktEnd_out,
output [31:0] m_wb_adr_o,
output reg [3:0] m_wb_sel_o,
output reg m_wb_we_o,
input [31:0] m_wb_dat_i,
output [31:0] m_wb_dat_o,
output reg m_wb_cyc_o,
output reg m_wb_stb_o,
input m_wb_ack_i,
input m_wb_err_i,
output [2:0] m_wb_cti_o, // Cycle Type Identifier
output [1:0] m_wb_bte_o, // Burst Type Extension
output cpu_stall_o,
output cpu_rst_o,
output [7:0] led
);
parameter IDLE = 0, R_COUNT0 = 1, R_COUNT1 = 2, R_COUNT2 = 3, R_COUNT3 = 4,
READ = 5, READ_WAIT = 6, READ_COUNT = 13,
BEGIN_WRITE = 7, WRITE_WAIT = 8, WRITE = 9, END_WRITE = 10,
WTL_READ1 = 11, WTL_READ2 = 12;
parameter OUT_FIFO = 2'b10, IN_FIFO = 2'b11;
parameter FIFO_READ = 3'b100, FIFO_WRITE = 3'b011, FIFO_NOP = 3'b111; //slwr, slrd, sloe
// FPGAlink state registers
reg [3:0] state, state_n;
reg is_write, is_write_n;
reg is_aligned, is_aligned_n;
reg [7:0] addr, addr_n;
reg [31:0] count, count_n;
// Data registers
reg [7:0] test_reg, test_reg_n;
reg [7:0] wtl_reg, wtl_reg_n;
// Control wires
reg fifoData_out_drive;
reg [7:0] fifoData_out;
reg [2:0] fifoOp;
// Link to WB FIFO
wire [7:0] ltw_din;
reg ltw_wr_en;
reg ltw_rd_en;
wire [31:0] ltw_dout;
wire ltw_full;
wire ltw_empty;
assign ltw_din = fifoData_io;
// WB to Link FIFO
wire [31:0] wtl_din;
reg wtl_wr_en;
reg wtl_rd_en;
wire [7:0] wtl_dout;
wire wtl_full;
wire wtl_empty;
assign fifoData_io = fifoData_out_drive ? fifoData_out : 8'bz;
assign m_wb_cti_o = 0;
assign m_wb_bte_o = 0;
assign sloe_out = fifoOp[0];
assign slrd_out = fifoOp[1];
assign slwr_out = fifoOp[2];
assign cpu_stall_o = test_reg[0];
assign cpu_rst_o = test_reg[1];
always @(*)
begin
case(addr)
0: fifoData_out = test_reg;
1: fifoData_out = wtl_reg;
default: fifoData_out = 8'h00;
endcase
end
always @(*) // asynchronous reset!
begin
state_n = state;
is_write_n = is_write;
is_aligned_n = is_aligned;
addr_n = addr;
count_n = count;
test_reg_n = test_reg;
wtl_reg_n = wtl_reg;
fifoAddr_out = OUT_FIFO;
fifoOp = FIFO_NOP;
pktEnd_out = 1;
fifoData_out_drive = 0;
ltw_wr_en = 0;
wtl_rd_en = 0;
case(state)
IDLE: begin
fifoOp = FIFO_READ;
if (gotData_in)
begin
is_write_n = fifoData_io[7];
addr_n[2:0] = fifoData_io[2:0];
state_n = R_COUNT0;
end
end
R_COUNT0: begin
fifoOp = FIFO_READ;
if (gotData_in)
begin
count_n[31:24] = fifoData_io;
state_n = R_COUNT1;
end
end
R_COUNT1: begin
fifoOp = FIFO_READ;
if (gotData_in)
begin
count_n[23:16] = fifoData_io;
state_n = R_COUNT2;
end
end
R_COUNT2: begin
fifoOp = FIFO_READ;
if (gotData_in)
begin
count_n[15:8] = fifoData_io;
state_n = R_COUNT3;
end
end
R_COUNT3: begin
fifoOp = FIFO_READ;
if (gotData_in)
begin
count_n[7:0] = fifoData_io;
if (is_write)
state_n = BEGIN_WRITE;
else
begin
state_n = READ_WAIT;
end
end
end
BEGIN_WRITE: begin
fifoAddr_out = IN_FIFO;
is_aligned_n = ~(count[0] | count[1] | count[2] | count[3] | count[4] | count[5] | count[6] | count[7] | count[8]);
state_n = WRITE_WAIT;
end
WRITE_WAIT: begin
fifoAddr_out = IN_FIFO;
if (gotRoom_in) // && ready
begin
case (addr)
0: state_n = WRITE;
1: state_n = WTL_READ1;
default: state_n = WRITE;
endcase
end
end
WTL_READ1: begin
fifoAddr_out = IN_FIFO;
if (!wtl_empty) begin
state_n = WTL_READ2;
wtl_rd_en = 1;
end
end
WTL_READ2: begin
fifoAddr_out = IN_FIFO;
wtl_reg_n = wtl_dout;
state_n = WRITE;
end
WRITE: begin
fifoData_out_drive = 1;
fifoOp = FIFO_WRITE;
fifoAddr_out = IN_FIFO;
count_n = count-1;
if (count == 1)
state_n = END_WRITE;
else
state_n = WRITE_WAIT;
end
END_WRITE: begin
pktEnd_out = is_aligned;
fifoAddr_out = IN_FIFO;
state_n = IDLE;
end
READ: begin
fifoOp = FIFO_READ;
if (gotData_in)
begin
case(addr)
0: test_reg_n = fifoData_io;
1: begin
ltw_wr_en = 1;
end
endcase
state_n = READ_COUNT;
end
end
READ_COUNT: begin
count_n = count-1;
if (count == 1)
state_n = IDLE;
else
state_n = READ_WAIT;
end
READ_WAIT: begin
case (addr)
0: state_n = READ;
1: if (!ltw_full) state_n = READ;
default: state_n = READ;
endcase
end
default: begin
state_n = IDLE;
end
endcase
end
always @(posedge ifclk_in or posedge wb_rst) // asynchronous reset!
if (wb_rst)
begin
state <= IDLE;
is_write <= 0;
is_aligned <= 0;
addr <= 8'b0;
count <= 32'b0;
test_reg <= 8'b0;
wtl_reg <= 8'b0;
end
else
begin
state <= state_n;
is_write <= is_write_n;
is_aligned <= is_aligned_n;
addr <= addr_n;
count <= count_n;
test_reg <= test_reg_n;
wtl_reg <= wtl_reg_n;
end
parameter CMD_NOP = 8'h00, CMD_WRITE = 8'h01, CMD_READ = 8'h02, CMD_CRC = 8'h03, CMD_STALL = 8'h04, CMD_RESET = 8'h05;
parameter S_WB_IDLE = 0, S_WB_READ_CMD = 1, S_WB_COUNT_WAIT = 2, S_WB_COUNT_READ = 3,
S_WB_ADR_WAIT = 4, S_WB_ADR_READ = 5, S_WB_WRITE1 = 6, S_WB_WRITE2 = 7,
S_WB_WRITE3 = 8, S_WB_READ1 = 9, S_WB_READ2 = 10, S_WB_READ3 = 11, S_WB_ERR = 12;
reg [3:0] wb_state, wb_state_n;
reg [31:0] wb_cmd, wb_cmd_n;
reg [31:0] wb_count, wb_count_n;
reg [31:0] wb_adr, wb_adr_n;
reg [31:0] wb_dat, wb_dat_n;
assign wtl_din = wb_dat;
assign m_wb_adr_o = wb_adr;
assign m_wb_dat_o = wb_dat;
assign led = {state[3:0], wb_state[3:0]};
always @(*)
begin
wb_state_n = wb_state;
wb_cmd_n = wb_cmd;
wb_count_n = wb_count;
wb_adr_n = wb_adr;
wb_dat_n = wb_dat;
ltw_rd_en = 0;
wtl_wr_en = 0;
m_wb_cyc_o = 0;
m_wb_stb_o = 0;
m_wb_we_o = 0;
m_wb_sel_o = 4'b1111;
case (wb_state)
S_WB_IDLE: begin
if (!ltw_empty) begin
ltw_rd_en = 1;
wb_state_n = S_WB_READ_CMD;
end
end
S_WB_READ_CMD: begin
wb_cmd_n = ltw_dout;
case (ltw_dout[7:0])
CMD_WRITE: wb_state_n = S_WB_COUNT_WAIT;
CMD_READ: wb_state_n = S_WB_COUNT_WAIT;
default: wb_state_n = S_WB_IDLE;
endcase
end
S_WB_COUNT_WAIT: begin
if (!ltw_empty) begin
ltw_rd_en = 1;
wb_state_n = S_WB_COUNT_READ;
end
end
S_WB_COUNT_READ: begin
wb_count_n = ltw_dout;
wb_state_n = S_WB_ADR_WAIT;
end
S_WB_ADR_WAIT: begin
if (!ltw_empty) begin
ltw_rd_en = 1;
wb_state_n = S_WB_ADR_READ;
end
end
S_WB_ADR_READ: begin
wb_adr_n = ltw_dout;
case (wb_cmd[7:0])
CMD_WRITE: wb_state_n = S_WB_WRITE1;
CMD_READ: wb_state_n = S_WB_READ1;
default: wb_state_n = S_WB_IDLE;
endcase
end
S_WB_WRITE1: begin
if (!ltw_empty) begin
ltw_rd_en = 1;
wb_state_n = S_WB_WRITE2;
end
end
S_WB_WRITE2: begin
wb_dat_n = ltw_dout;
wb_state_n = S_WB_WRITE3;
end
S_WB_WRITE3: begin
m_wb_cyc_o = 1;
m_wb_stb_o = 1;
m_wb_we_o = 1;
if (m_wb_ack_i) begin
wb_adr_n = wb_adr+4;
wb_count_n = wb_count-1;
if (wb_count==32'd1)
wb_state_n = S_WB_IDLE;
else
wb_state_n = S_WB_WRITE1;
end
else if (m_wb_err_i) begin
wb_state_n = S_WB_ERR;
end
end
S_WB_READ1: begin
m_wb_cyc_o = 1;
m_wb_stb_o = 1;
if (m_wb_ack_i) begin
wb_dat_n = m_wb_dat_i;
wb_state_n = S_WB_READ2;
end
else if (m_wb_err_i) begin
wb_state_n = S_WB_ERR;
end
end
S_WB_READ2: begin
if (!wtl_full) begin
wb_state_n = S_WB_READ3;
end
end
S_WB_READ3: begin
wtl_wr_en = 1;
wb_adr_n = wb_adr+4;
wb_count_n = wb_count-1;
if (wb_count==32'd1)
wb_state_n = S_WB_IDLE;
else
wb_state_n = S_WB_READ1;
end
S_WB_ERR: begin
end
endcase
end
always @(posedge wb_clk)
begin
if (wb_rst) begin
wb_state <= S_WB_IDLE;
wb_cmd <= 32'd0;
wb_count <= 32'd0;
wb_adr <= 32'd0;
wb_dat <= 32'd0;
end
else begin
wb_state <= wb_state_n;
wb_cmd <= wb_cmd_n;
wb_count <= wb_count_n;
wb_adr <= wb_adr_n;
wb_dat <= wb_dat_n;
end
end
orlink_ltw_fifo link_to_wb_fifo (
.rst (wb_rst),
.wr_clk (ifclk_in),
.rd_clk (wb_clk),
.din (ltw_din),
.wr_en (ltw_wr_en),
.rd_en (ltw_rd_en),
.dout (ltw_dout),
.full (ltw_full),
.empty (ltw_empty)
);
orlink_wtl_fifo wb_to_link_fifo (
.rst (wb_rst),
.wr_clk (wb_clk),
.rd_clk (ifclk_in),
.din (wtl_din),
.wr_en (wtl_wr_en),
.rd_en (wtl_rd_en),
.dout (wtl_dout),
.full (wtl_full),
.empty (wtl_empty)
);
endmodule
|
// $Id: vcr_la_routing_logic.v 1922 2010-04-15 03:47:49Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
Neither the name of the Stanford University nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// lookahead routing logic for VC router
module vcr_la_routing_logic
(clk, reset, router_address, route_port, inc_rc, hop_route_info,
la_route_info);
`include "c_functions.v"
`include "c_constants.v"
// nuber of resource classes (e.g. minimal, adaptive)
parameter num_resource_classes = 2;
// number of routers in each dimension
parameter num_routers_per_dim = 4;
// width required to select individual router in a dimension
localparam dim_addr_width = clogb(num_routers_per_dim);
// number of dimensions in network
parameter num_dimensions = 2;
// width required to select individual router in network
localparam router_addr_width = num_dimensions * dim_addr_width;
// number of nodes per router (a.k.a. consentration factor)
parameter num_nodes_per_router = 1;
// width required to select individual node at current router
localparam node_addr_width = clogb(num_nodes_per_router);
// width of global addresses
localparam addr_width = router_addr_width + node_addr_width;
// connectivity within each dimension
parameter connectivity = `CONNECTIVITY_LINE;
// number of adjacent routers in each dimension
localparam num_neighbors_per_dim
= ((connectivity == `CONNECTIVITY_LINE) ||
(connectivity == `CONNECTIVITY_RING)) ?
2 :
(connectivity == `CONNECTIVITY_FULL) ?
(num_routers_per_dim - 1) :
-1;
// number of input and output ports on router
localparam num_ports
= num_dimensions * num_neighbors_per_dim + num_nodes_per_router;
// width required to select an individual port
localparam port_idx_width = clogb(num_ports);
// width required for lookahead routing information
localparam la_route_info_width
= port_idx_width + ((num_resource_classes > 1) ? 1 : 0);
// select routing function type
parameter routing_type = `ROUTING_TYPE_DOR;
// select order of dimension traversal
parameter dim_order = `DIM_ORDER_ASCENDING;
// current resource class
parameter resource_class = 0;
// total number of bits required for storing routing information
localparam hop_route_info_width
= (resource_class == (num_resource_classes - 1)) ?
addr_width :
(resource_class == (num_resource_classes - 2)) ?
(router_addr_width + addr_width) :
(2 * router_addr_width);
parameter reset_type = `RESET_TYPE_ASYNC;
input clk;
input reset;
// current router's address
input [0:router_addr_width-1] router_address;
// port on which the packet will leave the current router
input [0:port_idx_width-1] route_port;
// will the resource class be incremented at the current router?
input inc_rc;
// routing data
input [0:hop_route_info_width-1] hop_route_info;
// lookahead routing information for next router
output [0:la_route_info_width-1] la_route_info;
wire [0:la_route_info_width-1] la_route_info;
// address of destination router for current resource class
wire [0:router_addr_width-1] dest_router_address;
// address of the downstream router
wire [0:router_addr_width-1] next_router_address;
wire [0:num_dimensions-1] dim_addr_match;
wire [0:num_ports-1] next_route_op;
generate
if(num_resource_classes > 1)
begin
wire next_inc_rc;
if(resource_class == (num_resource_classes - 1))
begin
assign dest_router_address
= hop_route_info[0:router_addr_width-1];
assign next_inc_rc = 1'b0;
end
else
begin
assign dest_router_address
= inc_rc ?
hop_route_info[router_addr_width:2*router_addr_width-1] :
hop_route_info[0:router_addr_width-1];
assign next_inc_rc
= (next_router_address == dest_router_address);
end
assign la_route_info[port_idx_width] = next_inc_rc;
end
else
assign dest_router_address = hop_route_info[0:router_addr_width-1];
case(routing_type)
`ROUTING_TYPE_DOR:
begin
genvar dim;
for(dim = 0; dim < num_dimensions; dim = dim + 1)
begin:dims
wire [0:dim_addr_width-1] dest_dim_addr;
assign dest_dim_addr
= dest_router_address[dim*dim_addr_width:
(dim+1)*dim_addr_width-1];
wire [0:dim_addr_width-1] curr_dim_addr;
assign curr_dim_addr
= router_address[dim*dim_addr_width:
(dim+1)*dim_addr_width-1];
wire [0:dim_addr_width-1] next_dim_addr;
assign dim_addr_match[dim] = (next_dim_addr == dest_dim_addr);
wire dim_sel;
case(dim_order)
`DIM_ORDER_ASCENDING:
begin
if(dim == 0)
assign dim_sel = ~dim_addr_match[dim];
else
assign dim_sel = &dim_addr_match[0:dim-1] &
~dim_addr_match[dim];
end
`DIM_ORDER_DESCENDING:
begin
if(dim == (num_dimensions - 1))
assign dim_sel = ~dim_addr_match[dim];
else
assign dim_sel = ~dim_addr_match[dim] &
dim_addr_match[(dim+1):
(num_dimensions-1)];
end
endcase
wire [0:num_neighbors_per_dim-1] port_dec;
assign next_router_address[dim*dim_addr_width:
(dim+1)*dim_addr_width-1]
= next_dim_addr;
case(connectivity)
`CONNECTIVITY_LINE, `CONNECTIVITY_RING:
begin
wire route_down;
assign route_down
= (route_port == dim*num_neighbors_per_dim);
wire route_up;
assign route_up
= (route_port == dim*num_neighbors_per_dim+1);
// Assemble a delta value for the address segment
// corresponding to the current dimension; the delta
// can have the values -1 (i.e., all ones in two's
// complement), 0 or 1
wire [0:dim_addr_width-1] addr_delta;
if(dim_addr_width > 1)
assign addr_delta[0:dim_addr_width-2]
= {(dim_addr_width-1){route_down}};
assign addr_delta[dim_addr_width-1]
= route_down | route_up;
assign next_dim_addr = curr_dim_addr + addr_delta;
case(connectivity)
`CONNECTIVITY_LINE:
begin
assign port_dec
= {dest_dim_addr < next_dim_addr,
dest_dim_addr > next_dim_addr};
end
`CONNECTIVITY_RING:
begin
// FIXME: add implementation here!
// synopsys translate_off
initial
begin
$display({"ERROR: The lookahead routing ",
"logic module %m does not yet ",
"support ring connectivity ",
"within each dimension."});
$stop;
end
// synopsys translate_on
end
endcase
end
`CONNECTIVITY_FULL:
begin
wire route_dest;
assign route_dest
= (route_port >= (dim*num_neighbors_per_dim)) &&
(route_port <= ((dim+1)*num_neighbors_per_dim-1));
assign next_dim_addr
= route_dest ? dest_dim_addr : curr_dim_addr;
wire [0:num_routers_per_dim-1] dest_dim_addr_dec;
c_decoder
#(.num_ports(num_routers_per_dim))
dest_dim_addr_dec_dec
(.data_in(dest_dim_addr),
.data_out(dest_dim_addr_dec));
wire [0:(2*num_routers_per_dim-1)-1]
dest_dim_addr_dec_repl;
assign dest_dim_addr_dec_repl
= {dest_dim_addr_dec,
dest_dim_addr_dec[0:(num_routers_per_dim-1)-1]};
assign port_dec
= dest_dim_addr_dec_repl[(next_dim_addr+1) +:
num_neighbors_per_dim];
end
endcase
assign next_route_op[dim*num_neighbors_per_dim:
(dim+1)*num_neighbors_per_dim-1]
= port_dec & {num_neighbors_per_dim{dim_sel}};
end
end
endcase
wire eject;
if(resource_class == (num_resource_classes - 1))
assign eject = &dim_addr_match;
else if(resource_class == (num_resource_classes - 2))
assign eject = &dim_addr_match & inc_rc;
else
assign eject = 1'b0;
if(num_nodes_per_router > 1)
begin
wire [0:node_addr_width-1] dest_node_address;
assign dest_node_address
= hop_route_info[hop_route_info_width-node_addr_width:
hop_route_info_width-1];
wire [0:num_nodes_per_router-1] node_sel;
c_decoder
#(.num_ports(num_nodes_per_router))
node_sel_dec
(.data_in(dest_node_address),
.data_out(node_sel));
assign next_route_op[num_ports-num_nodes_per_router:num_ports-1]
= node_sel & {num_nodes_per_router{eject}};
end
else
assign next_route_op[num_ports-1] = eject;
endgenerate
wire [0:port_idx_width-1] next_route_port;
c_encoder
#(.num_ports(num_ports))
next_route_port_enc
(.data_in(next_route_op),
.data_out(next_route_port));
assign la_route_info[0:port_idx_width-1] = next_route_port;
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Store Buffer ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Implements store buffer. ////
//// ////
//// To Do: ////
//// - byte combining ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_sb(
// RISC clock, reset
clk, rst,
// Internal RISC bus (DC<->SB)
dcsb_dat_i, dcsb_adr_i, dcsb_cyc_i, dcsb_stb_i, dcsb_we_i, dcsb_sel_i, dcsb_cab_i,
dcsb_dat_o, dcsb_ack_o, dcsb_err_o,
// BIU bus
sbbiu_dat_o, sbbiu_adr_o, sbbiu_cyc_o, sbbiu_stb_o, sbbiu_we_o, sbbiu_sel_o, sbbiu_cab_o,
sbbiu_dat_i, sbbiu_ack_i, sbbiu_err_i
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
//
// RISC clock, reset
//
input clk; // RISC clock
input rst; // RISC reset
//
// Internal RISC bus (DC<->SB)
//
input [dw-1:0] dcsb_dat_i; // input data bus
input [aw-1:0] dcsb_adr_i; // address bus
input dcsb_cyc_i; // WB cycle
input dcsb_stb_i; // WB strobe
input dcsb_we_i; // WB write enable
input dcsb_cab_i; // CAB input
input [3:0] dcsb_sel_i; // byte selects
output [dw-1:0] dcsb_dat_o; // output data bus
output dcsb_ack_o; // ack output
output dcsb_err_o; // err output
//
// BIU bus
//
output [dw-1:0] sbbiu_dat_o; // output data bus
output [aw-1:0] sbbiu_adr_o; // address bus
output sbbiu_cyc_o; // WB cycle
output sbbiu_stb_o; // WB strobe
output sbbiu_we_o; // WB write enable
output sbbiu_cab_o; // CAB input
output [3:0] sbbiu_sel_o; // byte selects
input [dw-1:0] sbbiu_dat_i; // input data bus
input sbbiu_ack_i; // ack output
input sbbiu_err_i; // err output
`ifdef OR1200_SB_IMPLEMENTED
//
// Internal wires and regs
//
wire [4+dw+aw-1:0] fifo_dat_i; // FIFO data in
wire [4+dw+aw-1:0] fifo_dat_o; // FIFO data out
wire fifo_wr;
wire fifo_rd;
wire fifo_full;
wire fifo_empty;
wire sel_sb;
reg outstanding_store;
reg fifo_wr_ack;
//
// FIFO data in/out
//
assign fifo_dat_i = {dcsb_sel_i, dcsb_dat_i, dcsb_adr_i};
assign {sbbiu_sel_o, sbbiu_dat_o, sbbiu_adr_o} = sel_sb ? fifo_dat_o : {dcsb_sel_i, dcsb_dat_i, dcsb_adr_i};
//
// Control
//
assign fifo_wr = dcsb_cyc_i & dcsb_stb_i & dcsb_we_i & ~fifo_full & ~fifo_wr_ack;
assign fifo_rd = ~outstanding_store;
assign dcsb_dat_o = sbbiu_dat_i;
assign dcsb_ack_o = sel_sb ? fifo_wr_ack : sbbiu_ack_i;
assign dcsb_err_o = sel_sb ? 1'b0 : sbbiu_err_i; // SB never returns error
assign sbbiu_cyc_o = sel_sb ? outstanding_store : dcsb_cyc_i;
assign sbbiu_stb_o = sel_sb ? outstanding_store : dcsb_stb_i;
assign sbbiu_we_o = sel_sb ? 1'b1 : dcsb_we_i;
assign sbbiu_cab_o = sel_sb ? 1'b0 : dcsb_cab_i;
assign sel_sb = ~fifo_empty | (fifo_empty & outstanding_store); // | fifo_wr;
//
// Store buffer FIFO instantiation
//
or1200_sb_fifo or1200_sb_fifo (
.clk_i(clk),
.rst_i(rst),
.dat_i(fifo_dat_i),
.wr_i(fifo_wr),
.rd_i(fifo_rd),
.dat_o(fifo_dat_o),
.full_o(fifo_full),
.empty_o(fifo_empty)
);
//
// fifo_rd
//
always @(posedge clk or posedge rst)
if (rst)
outstanding_store <= #1 1'b0;
else if (sbbiu_ack_i)
outstanding_store <= #1 1'b0;
else if (sel_sb | fifo_wr)
outstanding_store <= #1 1'b1;
//
// fifo_wr_ack
//
always @(posedge clk or posedge rst)
if (rst)
fifo_wr_ack <= #1 1'b0;
else if (fifo_wr)
fifo_wr_ack <= #1 1'b1;
else
fifo_wr_ack <= #1 1'b0;
`else // !OR1200_SB_IMPLEMENTED
assign sbbiu_dat_o = dcsb_dat_i;
assign sbbiu_adr_o = dcsb_adr_i;
assign sbbiu_cyc_o = dcsb_cyc_i;
assign sbbiu_stb_o = dcsb_stb_i;
assign sbbiu_we_o = dcsb_we_i;
assign sbbiu_cab_o = dcsb_cab_i;
assign sbbiu_sel_o = dcsb_sel_i;
assign dcsb_dat_o = sbbiu_dat_i;
assign dcsb_ack_o = sbbiu_ack_i;
assign dcsb_err_o = sbbiu_err_i;
`endif
endmodule
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// --------------------------------------------------------------------------------
//| Avalon ST Idle Remover
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
module altera_avalon_st_idle_remover (
// Interface: clk
input clk,
input reset_n,
// Interface: ST in
output reg in_ready,
input in_valid,
input [7: 0] in_data,
// Interface: ST out
input out_ready,
output reg out_valid,
output reg [7: 0] out_data
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg received_esc;
wire escape_char, idle_char;
// ---------------------------------------------------------------------
//| Thingofamagick
// ---------------------------------------------------------------------
assign idle_char = (in_data == 8'h4a);
assign escape_char = (in_data == 8'h4d);
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
received_esc <= 0;
end else begin
if (in_valid & in_ready) begin
if (escape_char & ~received_esc) begin
received_esc <= 1;
end else if (out_valid) begin
received_esc <= 0;
end
end
end
end
always @* begin
in_ready = out_ready;
//out valid when in_valid. Except when we get idle or escape
//however, if we have received an escape character, then we are valid
out_valid = in_valid & ~idle_char & (received_esc | ~escape_char);
out_data = received_esc ? (in_data ^ 8'h20) : in_data;
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// usbSlaveCyc2Wrap.v ////
//// ////
//// This file is part of the usbhostslave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
//// Top level module wrapper.
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
module usbSlaveCyc2Wrap(
clk_i,
rst_i,
address_i,
data_i,
data_o,
we_i,
strobe_i,
ack_o,
irq,
usbClk,
USBWireVP,
USBWireVM,
USBWireOE_n,
USBFullSpeed,
USBDPlusPullup,
USBDMinusPullup,
vBusDetect
);
input clk_i;
input rst_i;
input [7:0] address_i;
input [7:0] data_i;
output [7:0] data_o;
input we_i;
input strobe_i;
output ack_o;
output irq;
input usbClk;
inout USBWireVP /* synthesis useioff=1 */;
inout USBWireVM /* synthesis useioff=1 */;
output USBWireOE_n /* synthesis useioff=1 */;
output USBFullSpeed /* synthesis useioff=1 */;
output USBDPlusPullup;
output USBDMinusPullup;
input vBusDetect;
wire clk_i;
wire rst_i;
wire [7:0] address_i;
wire [7:0] data_i;
wire [7:0] data_o;
wire irq;
wire usbClk;
wire USBWireDataOutTick;
wire USBWireDataInTick;
wire USBFullSpeed;
//internal wiring
wire slaveSOFRxedIntOut;
wire slaveResetEventIntOut;
wire slaveResumeIntOut;
wire slaveTransDoneIntOut;
wire slaveNAKSentIntOut;
wire slaveVBusDetIntOut;
wire USBWireCtrlOut;
wire [1:0] USBWireDataIn;
wire [1:0] USBWireDataOut;
assign irq = slaveSOFRxedIntOut | slaveResetEventIntOut |
slaveResumeIntOut | slaveTransDoneIntOut |
slaveNAKSentIntOut | slaveVBusDetIntOut;
assign USBWireDataIn = {USBWireVP, USBWireVM};
assign {USBWireVP, USBWireVM} = (USBWireCtrlOut == 1'b1) ? USBWireDataOut : 2'bzz;
assign USBWireOE_n = ~USBWireCtrlOut;
//Parameters declaration:
defparam usbSlaveInst.EP0_FIFO_DEPTH = 64;
parameter EP0_FIFO_DEPTH = 64;
defparam usbSlaveInst.EP0_FIFO_ADDR_WIDTH = 6;
parameter EP0_FIFO_ADDR_WIDTH = 6;
defparam usbSlaveInst.EP1_FIFO_DEPTH = 64;
parameter EP1_FIFO_DEPTH = 64;
defparam usbSlaveInst.EP1_FIFO_ADDR_WIDTH = 6;
parameter EP1_FIFO_ADDR_WIDTH = 6;
defparam usbSlaveInst.EP2_FIFO_DEPTH = 64;
parameter EP2_FIFO_DEPTH = 64;
defparam usbSlaveInst.EP2_FIFO_ADDR_WIDTH = 6;
parameter EP2_FIFO_ADDR_WIDTH = 6;
defparam usbSlaveInst.EP3_FIFO_DEPTH = 64;
parameter EP3_FIFO_DEPTH = 64;
defparam usbSlaveInst.EP3_FIFO_ADDR_WIDTH = 6;
parameter EP3_FIFO_ADDR_WIDTH = 6;
usbSlave usbSlaveInst (
.clk_i(clk_i),
.rst_i(rst_i),
.address_i(address_i),
.data_i(data_i),
.data_o(data_o),
.we_i(we_i),
.strobe_i(strobe_i),
.ack_o(ack_o),
.usbClk(usbClk),
.slaveSOFRxedIntOut(slaveSOFRxedIntOut),
.slaveResetEventIntOut(slaveResetEventIntOut),
.slaveResumeIntOut(slaveResumeIntOut),
.slaveTransDoneIntOut(slaveTransDoneIntOut),
.slaveNAKSentIntOut(slaveNAKSentIntOut),
.slaveVBusDetIntOut(slaveVBusDetIntOut),
.USBWireDataIn(USBWireDataIn),
.USBWireDataInTick(USBWireDataInTick),
.USBWireDataOut(USBWireDataOut),
.USBWireDataOutTick(USBWireDataOutTick),
.USBWireCtrlOut(USBWireCtrlOut),
.USBFullSpeed(USBFullSpeed),
.USBDPlusPullup(USBDPlusPullup),
.USBDMinusPullup(USBDMinusPullup),
.vBusDetect(vBusDetect)
);
endmodule
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010, 2011 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module minimac2_tx(
input phy_tx_clk,
input tx_start,
output reg tx_done,
input [10:0] tx_count,
input [7:0] txb_dat,
output [10:0] txb_adr,
output reg phy_tx_en,
output reg [3:0] phy_tx_data
);
reg phy_tx_en_r;
reg phy_tx_data_sel;
wire [3:0] phy_tx_data_r = phy_tx_data_sel ? txb_dat[7:4] : txb_dat[3:0];
always @(posedge phy_tx_clk) begin
phy_tx_en <= phy_tx_en_r;
phy_tx_data <= phy_tx_data_r;
end
reg [10:0] byte_count;
reg byte_count_reset;
reg byte_count_inc;
always @(posedge phy_tx_clk) begin
if(byte_count_reset)
byte_count <= 11'd0;
else if(byte_count_inc)
byte_count <= byte_count + 11'd1;
end
assign txb_adr = byte_count;
wire byte_count_max = byte_count == tx_count;
parameter IDLE = 2'd0;
parameter SEND_LO = 2'd1;
parameter SEND_HI = 2'd2;
parameter TERMINATE = 2'd3;
reg [1:0] state;
reg [1:0] next_state;
initial state <= IDLE;
always @(posedge phy_tx_clk)
state <= next_state;
always @(*) begin
phy_tx_en_r = 1'b0;
phy_tx_data_sel = 1'b0;
byte_count_reset = 1'b0;
byte_count_inc = 1'b0;
tx_done = 1'b0;
next_state = state;
case(state)
IDLE: begin
byte_count_reset = 1'b1;
if(tx_start)
next_state = SEND_LO;
end
SEND_LO: begin
byte_count_inc = 1'b1;
phy_tx_en_r = 1'b1;
phy_tx_data_sel = 1'b0;
next_state = SEND_HI;
end
SEND_HI: begin
phy_tx_en_r = 1'b1;
phy_tx_data_sel = 1'b1;
if(byte_count_max)
next_state = TERMINATE;
else
next_state = SEND_LO;
end
TERMINATE: begin
byte_count_reset = 1'b1;
tx_done = 1'b1;
next_state = IDLE;
end
endcase
end
endmodule
|
`ifndef _MILISECOND_TIMER_V
`define _MILISECOND_TIMER_V
module milisecond_timer #(
parameter SYS_CLK_KHZ = 50,
parameter DELAY_W = 12
) (
input clk,
input reset,
input delay_start,
input [DELAY_W-1:0] delay_ms,
output delay_fin
);
`define MS_TIMER_SM_W 2
localparam STATE_IDLE = `MS_TIMER_SM_W'h0;
localparam STATE_WAIT = `MS_TIMER_SM_W'h1;
localparam STATE_DONE = `MS_TIMER_SM_W'h2;
localparam SYS_CLK_W = log2(SYS_CLK_KHZ);
reg [`MS_TIMER_SM_W-1:0] timer_state;
reg [DELAY_W-1:0] ms_counter;
reg [DELAY_W-1:0] delay_ms_latched;
reg [SYS_CLK_W-1:0] sys_clk_counter;
assign delay_fin = ( (timer_state==STATE_DONE) && (delay_start==1'b0) ) ? 1'b1 : 1'b0;
always @(posedge clk or posedge reset) begin
if (reset) begin
timer_state <= STATE_IDLE;
delay_ms_latched <= 'b0;
end else begin
case (timer_state)
STATE_IDLE: begin
if (delay_start==1'b1) begin
timer_state <= STATE_WAIT;
delay_ms_latched <= delay_ms;
end
end
STATE_WAIT: begin
if (ms_counter == delay_ms_latched) begin
timer_state <= STATE_DONE;
delay_ms_latched <= 'b0;
end
end
STATE_DONE: begin
if (delay_start==1'b0) begin
timer_state <= STATE_IDLE;
end
end
endcase
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
sys_clk_counter <= 'b0;
ms_counter <= 'b0;
end else begin
if (timer_state==STATE_WAIT) begin
if (sys_clk_counter == SYS_CLK_KHZ ) begin
sys_clk_counter <= 'b0;
ms_counter <= ms_counter + 1;
end else begin
sys_clk_counter <= sys_clk_counter + 1;
end
end else begin
sys_clk_counter <= 'b0;
ms_counter <= 'b0;
end
end
end
function [5:0] log2;
input [31:0] val;
integer i;
begin
for (i=32; i>0; i=i-1) begin
if (val>(32'b1<<(i-1))) begin
log2 = i;
i = 0;
end else begin
log2 = 1;
end
end
end
endfunction
endmodule
`endif
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: test_pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module test_pll (
inclk0,
c0);
input inclk0;
output c0;
wire [5:0] sub_wire0;
wire [0:0] sub_wire4 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire sub_wire2 = inclk0;
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
altpll altpll_component (
.inclk (sub_wire3),
.clk (sub_wire0),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.clk0_divide_by = 5,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 1,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone II",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=test_pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "test_pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL test_pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL test_pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL test_pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL test_pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL test_pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL test_pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL test_pll_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND2B_FUNCTIONAL_V
`define SKY130_FD_SC_LP__NAND2B_FUNCTIONAL_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__nand2b (
Y ,
A_N,
B
);
// Module ports
output Y ;
input A_N;
input B ;
// Local signals
wire not0_out ;
wire or0_out_Y;
// Name Output Other arguments
not not0 (not0_out , B );
or or0 (or0_out_Y, not0_out, A_N );
buf buf0 (Y , or0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND2B_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUX2_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__MUX2_PP_SYMBOL_V
/**
* mux2: 2-input multiplexer.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__mux2 (
//# {{data|Data Signals}}
input A0 ,
input A1 ,
output X ,
//# {{control|Control Signals}}
input S ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUX2_PP_SYMBOL_V
|
module wfid_mux_8to1 (
wr_port_select,
wfid_done_0,
wfid_0,
wfid_done_1,
wfid_1,
wfid_done_2,
wfid_2,
wfid_done_3,
wfid_3,
wfid_done_4,
wfid_4,
wfid_done_5,
wfid_5,
wfid_done_6,
wfid_6,
wfid_done_7,
wfid_7,
muxed_wfid,
muxed_wfid_done
);
output [5:0] muxed_wfid;
output muxed_wfid_done;
input [15:0] wr_port_select;
input wfid_done_0;
input [5:0] wfid_0;
input wfid_done_1;
input [5:0] wfid_1;
input wfid_done_2;
input [5:0] wfid_2;
input wfid_done_3;
input [5:0] wfid_3;
input wfid_done_4;
input [5:0] wfid_4;
input wfid_done_5;
input [5:0] wfid_5;
input wfid_done_6;
input [5:0] wfid_6;
input wfid_done_7;
input [5:0] wfid_7;
reg [5:0] muxed_wfid;
reg muxed_wfid_done;
always @ (
wr_port_select or
wfid_done_0 or
wfid_0 or
wfid_done_1 or
wfid_1 or
wfid_done_2 or
wfid_2 or
wfid_done_3 or
wfid_3 or
wfid_done_4 or
wfid_4 or
wfid_done_5 or
wfid_5 or
wfid_done_6 or
wfid_6 or
wfid_done_7 or
wfid_7
) begin
casex(wr_port_select)
16'h0001:
begin
muxed_wfid_done <= wfid_done_0;
muxed_wfid <= wfid_0;
end
16'h0002:
begin
muxed_wfid_done <= wfid_done_1;
muxed_wfid <= wfid_1;
end
16'h0004:
begin
muxed_wfid_done <= wfid_done_2;
muxed_wfid <= wfid_2;
end
16'h0008:
begin
muxed_wfid_done <= wfid_done_3;
muxed_wfid <= wfid_3;
end
16'h0010:
begin
muxed_wfid_done <= wfid_done_4;
muxed_wfid <= wfid_4;
end
16'h0020:
begin
muxed_wfid_done <= wfid_done_5;
muxed_wfid <= wfid_5;
end
16'h0040:
begin
muxed_wfid_done <= wfid_done_6;
muxed_wfid <= wfid_6;
end
16'h0080:
begin
muxed_wfid_done <= wfid_done_7;
muxed_wfid <= wfid_7;
end
16'h0100:
begin
muxed_wfid_done <= 1'b0;
muxed_wfid <= {6{1'bx}};
end
16'h0000:
begin
muxed_wfid_done <= 1'b0;
muxed_wfid <= {6{1'bx}};
end
default:
begin
muxed_wfid_done <= 1'bx;
muxed_wfid <= {6{1'bx}};
end
endcase
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/11/2016 02:09:05 PM
// Design Name:
// Module Name: Rotate_Mux_Array
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Rotate_Mux_Array
#(parameter SWR=26)
(
input wire [SWR-1:0] Data_i,
input wire select_i,
output wire [SWR-1:0] Data_o
);
genvar j;//Create a variable for the loop FOR
generate for (j=0; j <= SWR-1; j=j+1) begin // generate enough Multiplexers modules for each bit
case (j)
SWR-1-j:begin
assign Data_o[j]=Data_i[SWR-1-j];
end
default:begin
Multiplexer_AC #(.W(1)) rotate_mux(
.ctrl(select_i),
.D0 (Data_i[j]),
.D1 (Data_i[SWR-1-j]),
.S (Data_o[j])
);
end
endcase
end
endgenerate
endmodule
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module splits video in streams for the DE-series boards. *
* *
******************************************************************************/
module Computer_System_Video_In_Subsystem_Edge_Detection_Subsystem_Video_Stream_Splitter (
// Inputs
clk,
reset,
sync_ready,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready_0,
stream_out_ready_1,
stream_select,
// Bidirectional
// Outputs
sync_data,
sync_valid,
stream_in_ready,
stream_out_data_0,
stream_out_startofpacket_0,
stream_out_endofpacket_0,
stream_out_empty_0,
stream_out_valid_0,
stream_out_data_1,
stream_out_startofpacket_1,
stream_out_endofpacket_1,
stream_out_empty_1,
stream_out_valid_1
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 23; // Frame's data width
parameter EW = 1; // Frame's empty width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input sync_ready;
input [DW: 0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [EW: 0] stream_in_empty;
input stream_in_valid;
input stream_out_ready_0;
input stream_out_ready_1;
input stream_select;
// Bidirectional
// Outputs
output reg sync_data;
output reg sync_valid;
output stream_in_ready;
output reg [DW: 0] stream_out_data_0;
output reg stream_out_startofpacket_0;
output reg stream_out_endofpacket_0;
output reg [EW: 0] stream_out_empty_0;
output reg stream_out_valid_0;
output reg [DW: 0] stream_out_data_1;
output reg stream_out_startofpacket_1;
output reg stream_out_endofpacket_1;
output reg [EW: 0] stream_out_empty_1;
output reg stream_out_valid_1;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire enable_setting_stream_select;
// Internal Registers
reg between_frames;
reg stream_select_reg;
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
begin
sync_data <= 1'b0;
sync_valid <= 1'b0;
end
else if (enable_setting_stream_select)
begin
sync_data <= stream_select;
sync_valid <= 1'b1;
end
else if (sync_ready)
sync_valid <= 1'b0;
end
always @(posedge clk)
begin
if (reset)
begin
stream_out_data_0 <= 'h0;
stream_out_startofpacket_0 <= 1'b0;
stream_out_endofpacket_0 <= 1'b0;
stream_out_empty_0 <= 'h0;
stream_out_valid_0 <= 1'b0;
end
else if (stream_in_ready & ~stream_select_reg)
begin
stream_out_data_0 <= stream_in_data;
stream_out_startofpacket_0 <= stream_in_startofpacket;
stream_out_endofpacket_0 <= stream_in_endofpacket;
stream_out_empty_0 <= stream_in_empty;
stream_out_valid_0 <= stream_in_valid;
end
else if (stream_out_ready_0)
stream_out_valid_0 <= 1'b0;
end
always @(posedge clk)
begin
if (reset)
begin
stream_out_data_1 <= 'h0;
stream_out_startofpacket_1 <= 1'b0;
stream_out_endofpacket_1 <= 1'b0;
stream_out_empty_1 <= 'h0;
stream_out_valid_1 <= 1'b0;
end
else if (stream_in_ready & stream_select_reg)
begin
stream_out_data_1 <= stream_in_data;
stream_out_startofpacket_1 <= stream_in_startofpacket;
stream_out_endofpacket_1 <= stream_in_endofpacket;
stream_out_empty_1 <= stream_in_empty;
stream_out_valid_1 <= stream_in_valid;
end
else if (stream_out_ready_1)
stream_out_valid_1 <= 1'b0;
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
between_frames <= 1'b1;
else if (stream_in_ready & stream_in_endofpacket)
between_frames <= 1'b1;
else if (stream_in_ready & stream_in_startofpacket)
between_frames <= 1'b0;
end
always @(posedge clk)
begin
if (reset)
stream_select_reg <= 1'b0;
else if (enable_setting_stream_select)
stream_select_reg <= stream_select;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_in_ready = (stream_select_reg) ?
stream_in_valid & (~stream_out_valid_1 | stream_out_ready_1) :
stream_in_valid & (~stream_out_valid_0 | stream_out_ready_0);
// Internal Assignments
assign enable_setting_stream_select =
(stream_in_ready & stream_in_endofpacket) |
(~(stream_in_ready & stream_in_startofpacket) & between_frames);
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR with generic_baseblocks_v2_1_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_comparator_mask #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
input wire [C_DATA_WIDTH-1:0] M,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar lut_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 2;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] m_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign m_local = M;
end
// Instantiate one generic_baseblocks_v2_1_carry and per level.
for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[lut_cnt] = ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[lut_cnt+1]),
.CIN (carry_local[lut_cnt]),
.S (sel[lut_cnt])
);
end // end for lut_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// OpenCores54 DSP, CPU ////
//// ////
//// Author: Richard Herveille ////
//// [email protected] ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//
// NOTE: Read the pipeline information for the CMPS instruction
//
//
// Xilinx Virtex-E WC: 41 CLB slices @ 130MHz
//
// CVS Log
//
// $Id: oc54_cpu.v,v 1.1.1.1 2002/04/10 09:34:41 rherveille Exp $
//
// $Date: 2002/04/10 09:34:41 $
// $Revision: 1.1.1.1 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: oc54_cpu.v,v $
// Revision 1.1.1.1 2002/04/10 09:34:41 rherveille
// Initial relase OpenCores54x DSP (CPU)
//
module oc54_cpu (
clk_i,
ena_mac_i, ena_alu_i, ena_bs_i, ena_exp_i,
ena_treg_i, ena_acca_i, ena_accb_i,
// mac
mac_sel_xm_i, mac_sel_ym_i, mac_sel_ya_i,
mac_xm_sx_i, mac_ym_sx_i, mac_add_sub_i,
// alu
alu_inst_i, alu_sel_i, alu_doublet_i,
// bs
bs_sel_i, bs_selo_i, l_na_i,
cssu_sel_i, is_cssu_i,
//
exp_sel_i, treg_sel_i,
acca_sel_i, accb_sel_i,
// common
pb_i, cb_i, db_i,
bp_a_i, bp_b_i,
ovm_i, frct_i, smul_i, sxm_i, c16_i, rnd_i,
c_i, tc_i,
asm_i, imm_i,
// outputs
c_alu_o, c_bs_o, tc_cssu_o, tc_alu_o,
ovf_a_o, zf_a_o, ovf_b_o, zf_b_o,
trn_o, eb_o
);
//
// parameters
//
//
// inputs & outputs
//
input clk_i;
input ena_mac_i, ena_alu_i, ena_bs_i, ena_exp_i;
input ena_treg_i, ena_acca_i, ena_accb_i;
input [1:0] mac_sel_xm_i, mac_sel_ym_i, mac_sel_ya_i;
input mac_xm_sx_i, mac_ym_sx_i, mac_add_sub_i;
input [6:0] alu_inst_i;
input [ 1:0] alu_sel_i;
input alu_doublet_i;
input [ 1:0] bs_sel_i, bs_selo_i;
input l_na_i;
input cssu_sel_i, is_cssu_i;
input exp_sel_i, treg_sel_i;
input [ 1:0] acca_sel_i, accb_sel_i;
input [15:0] pb_i, cb_i, db_i;
input bp_a_i, bp_b_i;
input ovm_i, frct_i, smul_i, sxm_i;
input c16_i, rnd_i, c_i, tc_i, asm_i, imm_i;
output c_alu_o, c_bs_o, tc_cssu_o, tc_alu_o;
output ovf_a_o, zf_a_o, ovf_b_o, zf_b_o;
output [15:0] trn_o, eb_o;
//
// variables
//
wire [39:0] acc_a, acc_b, bp_ar, bp_br;
wire [39:0] mac_result, alu_result, bs_result;
wire [15:0] treg;
wire [ 5:0] exp_result;
//
// module body
//
//
// instantiate MAC
oc54_mac cpu_mac(
.clk(clk_i), // clock input
.ena(ena_mac_i), // MAC clock enable input
.a(acc_a), // accumulator A input
.b(acc_b), // accumulator B input
.t(treg), // TREG input
.p(pb_i), // Program Data Bus input
.c(cb_i), // Coefficient Data Bus input
.d(db_i), // Data Bus input
.sel_xm(mac_sel_xm_i), // select multiplier-X input
.sel_ym(mac_sel_ym_i), // select muliplier-Y input
.sel_ya(mac_sel_ya_i), // select adder-Y input
.bp_a(bp_a_i), // bypass accumulator A select input
.bp_b(bp_b_i), // bypass accumulator B select input
.bp_ar(bp_ar), // bypass accumulator A input
.bp_br(bp_br), // bypass accumulator B input
.xm_s(mac_xm_sx_i), // sign extend multiplier x-input
.ym_s(mac_ym_sx_i), // sign extend multiplier y-input
.ovm(ovm_i), // overflow mode input
.frct(frct_i), // fractional mode input
.smul(smul_i), // saturate on multiply input
.add_sub(mac_add_sub_i), // add/subtract input
.result(mac_result) // MAC result output
);
//
// instantiate ALU
oc54_alu cpu_alu(
.clk(clk_i), // clock input
.ena(ena_alu_i), // ALU clock enable input
.inst(alu_inst_i), // ALU instruction
.seli(alu_sel_i), // ALU x-input select
.doublet(alu_doublet_i), // double t {treg, treg}
.a(acc_a), // accumulator A input
.b(acc_b), // accumulator B input
.s(bs_result), // barrel shifter result input
.t(treg), // TREG input
.cb(cb_i), // Coefficient Data Bus input
.bp_a(bp_a_i), // bypass accumulator A select input
.bp_b(bp_b_i), // bypass accumulator B select input
.bp_ar(bp_ar), // bypass accumulator A input
.bp_br(bp_br), // bypass accumulator B input
.c16(c16_i), // c16 (double 16/long-word) input
.sxm(sxm_i), // sign extend mode input
.ci(c_i), // carry input
.tci(tc_i), // test/control flag input
.co(c_alu_o), // ALU carry output
.tco(tc_alu_o), // ALU test/control flag output
.result(alu_result) // ALU result output
);
//
// instantiate barrel shifter
oc54_bshft cpu_bs(
.clk(clk_i), // clock input
.ena(ena_bs_i), // BS clock enable input
.a(acc_a), // accumulator A input
.b(acc_b), // accumulator B input
.cb(cb_i), // Coefficient Data Bus input
.db(db_i), // Data Bus input
.bp_a(bp_a_i), // bypass accumulator A select input
.bp_b(bp_b_i), // bypass accumulator B select input
.bp_ar(bp_ar), // bypass accumulator A input
.bp_br(bp_br), // bypass accumulator B input
.l_na(l_na_i), // BS logical/arithmetic shift mode input
.sxm(sxm_i), // sign extend mode input
.seli(bs_sel_i), // BS operand select input
.selo(bs_selo_i), // BS operator select input
.t(treg[5:0]), // TREG input
.asm(asm_i), // Accumulator Shift Mode input
.imm(imm_i), // Opcode Immediate input
.result(bs_result), // BS result output
.co(c_bs_o) // BS carry output (1 cycle ahead)
);
// instantiate Compare Select Store Unit
oc54_cssu cpu_cssu(
.clk(clk_i), // clock input
.ena(ena_bs_i), // BS/CSSU clock enable input
.sel_acc(cssu_sel_i), // CSSU accumulator select input
.is_cssu(is_cssu_i), // CSSU/NormalShift operation
.a(acc_a), // accumulator A input
.b(acc_b), // accumulator B input
.s(bs_result), // BarrelShifter result input
.tco(tc_cssu_o), // test/control flag output
.trn(trn_o), // Transition register output
.result(eb_o) // Result Data Bus output
);
//
// instantiate Exponent Encoder
oc54_exp cpu_exp_enc(
.clk(clk_i), // clock input
.ena(ena_exp_i), // Exponent Encoder clock enable input
.sel_acc(exp_sel_i), // ExpE. accumulator select input
.a(acc_a), // accumulator A input
.b(acc_b), // accumulator B input
.bp_ar(bp_ar), // bypass accumulator A input
.bp_br(bp_br), // bypass accumulator B input
.bp_a(bp_a_i), // bypass accumulator A select input
.bp_b(bp_b_i), // bypass accumulator B select input
.result(exp_result) // Exponent Encoder result output
);
//
// instantiate Temporary Register
oc54_treg cpu_treg(
.clk(clk_i), // clock input
.ena(ena_treg_i), // treg clock enable input
.seli(treg_sel_i), // treg select input
.we(1'b1), // treg write enable input
.exp(exp_result), // Exponent Encoder Result input
.d(db_i), // Data Bus input
.result(treg) // TREG
);
//
// instantiate accumulators
oc54_acc cpu_acc_a(
.clk(clk_i), // clock input
.ena(ena_acca_i), // accumulator A clock enable input
.seli(acca_sel_i), // accumulator A select input
.we(1'b1), // write enable input
.a(acc_a), // accumulator A input
.b(acc_b), // accumulator B input
.alu(alu_result), // ALU result input
.mac(mac_result), // MAC result input
.ovm(ovm_i), // overflow mode input
.rnd(rnd_i), // mac-rounding input
.zf(zf_a_o), // accumulator A zero flag output
.ovf(ovf_a_o), // accumulator A overflow flag output
.bp_result(bp_ar), // bypass accumulator A output
.result(acc_a) // accumulator A output
);
oc54_acc cpu_acc_b(
.clk(clk_i), // clock input
.ena(ena_accb_i), // accumulator B clock enable input
.seli(accb_sel_i), // accumulator B select input
.we(1'b1), // write enable input
.a(acc_a), // accumulator A input
.b(acc_b), // accumulator B input
.alu(alu_result), // ALU result input
.mac(mac_result), // MAC result input
.ovm(ovm_i), // overflow mode input
.rnd(rnd_i), // mac-rounding input
.zf(zf_b_o), // accumulator B zero flag output
.ovf(ovf_b_o), // accumulator B overflow flag output
.bp_result(bp_br), // bypass accumulator B output
.result(acc_b) // accumulator B output
);
endmodule
/////////////////////////////////////////////////////////////////////
//// ////
//// OpenCores54 DSP, accumulator ////
//// ////
//// Author: Richard Herveille ////
//// [email protected] ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//
// Xilinx Virtex-E WC: 96 CLB slices @ 51MHz
//
// CVS Log
//
// $Id: oc54_acc.v,v 1.1.1.1 2002/04/10 09:34:39 rherveille Exp $
//
// $Date: 2002/04/10 09:34:39 $
// $Revision: 1.1.1.1 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: oc54_acc.v,v $
// Revision 1.1.1.1 2002/04/10 09:34:39 rherveille
// Initial relase OpenCores54x DSP (CPU)
//
module oc54_acc (
clk, ena,
seli, we,
a, b, alu, mac,
ovm, rnd,
zf, ovf,
bp_result, result
);
//
// parameters
//
//
// inputs & outputs
//
input clk;
input ena;
input [ 1:0] seli; // select input
input we; // write enable
input [39:0] a, b, alu, mac; // accumulators, alu, mac input
input ovm, rnd; // overflow mode, saturate, round
output ovf, zf; // carry out, overflow, zero, tc-out
output [39:0] result; // accumulator register output
output [39:0] bp_result; // accumulator register bypass output
reg ovf, zf;
reg [39:0] result;
//
// variables
//
reg [39: 0] sel_r, iresult; // select results, final result
wire iovf;
//
// module body
//
//
// generate input selection
//
// input selection & MAC-rounding
always@(seli or a or b or alu or mac or rnd)
case(seli) // synopsis full_case parallel_case
2'b00: sel_r = a;
2'b01: sel_r = b;
2'b10: sel_r = alu;
2'b11: sel_r = rnd ? (mac + 16'h8000) & 40'hffffff0000 : mac;
endcase
// overflow detection
// no overflow when:
// 1) all guard bits are set (valid negative number)
// 2) no guard bits are set (valid positive number)
assign iovf = 1'b1;// !( sel_r[39:32] || (~sel_r[39:32]) );
// saturation
always@(iovf or ovm or sel_r)
if (ovm & iovf)
if (sel_r[39]) // negate overflow
iresult = 40'hff80000000;
else // positive overflow
iresult = 40'h007fffffff;
else
iresult = sel_r;
//
// generate registers
//
// generate bypass output
assign bp_result = iresult;
// result
always@(posedge clk)
if (ena & we)
result <= iresult;
// ovf, zf
always@(posedge clk)
if (ena & we)
begin
ovf <= iovf;
zf <= ~|iresult;
end
endmodule
/////////////////////////////////////////////////////////////////////
//// ////
//// OpenCores54 DSP, ALU ////
//// ////
//// Author: Richard Herveille ////
//// [email protected] ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//
// Xilinx Virtex-E WC: 617 CLB slices @ 58MHz
//
// CVS Log
//
// $Id: oc54_alu.v,v 1.1.1.1 2002/04/10 09:34:40 rherveille Exp $
//
// $Date: 2002/04/10 09:34:40 $
// $Revision: 1.1.1.1 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: oc54_alu.v,v $
// Revision 1.1.1.1 2002/04/10 09:34:40 rherveille
// Initial relase OpenCores54x DSP (CPU)
//
//// ////
//// OpenCores54 DSP, ALU defines ////
//// ////
//// Author: Richard Herveille ////
//// [email protected] ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: oc54_alu_defines.v,v 1.1.1.1 2002/04/10 09:34:40 rherveille Exp $
//
// $Date: 2002/04/10 09:34:40 $
// $Revision: 1.1.1.1 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: oc54_alu_defines.v,v $
// Revision 1.1.1.1 2002/04/10 09:34:40 rherveille
// Initial relase OpenCores54x DSP (CPU)
//
//
// Encoding: bit[6] always zero
// bit[5:4] instuction type
// - 00: (dual) arithmetic
// - 01: logical (incl. shift)
// - 10: bit-test & compare
// - 11: reserved
// Leonardo-Spectrum seems to like the additional zero bit[6] in
// the encoding scheme. It produces the smallest and fastest code
// like this. (Why ???)
//
//
// arithmetic instructions
//
//
// dual arithmetic instructions
//
//
// logical instructions
//
//
// shift instructions
//
//
// bit test instructions
//
//
// condition codes for CMP-test
//
module oc54_alu (
clk, ena, inst,
seli, doublet,
a, b, s, t, cb,
bp_a, bp_b, bp_ar, bp_br,
c16, sxm, ci, tci,
co, tco,
result
);
//
// parameters
//
//
// inputs & outputs
//
input clk;
input ena;
input [ 6:0] inst; // instruction
input [ 1:0] seli; // input selection
input doublet; // {T, T}
input [39:0] a, b, s; // accumulators + shifter inputs
input [15:0] t, cb; // TREG + c-bus input
input [39:0] bp_ar, bp_br; // bypass a register, bypass b register
input bp_a, bp_b; // bypass select
input c16, sxm; // dual-mode, sign-extend-mode,
input ci, tci; // carry in, tc-in
output co, tco; // carry out, overflow, zero, tc-out
output [39:0] result;
reg co, tco;
reg [39:0] result;
//
// variables
//
reg [39:0] iresult;
reg itco, ico;
reg [39:0] x;
wire [39:0] y;
reg dc16, dci, dtci;
reg [6:0] dinst;
//
// module body
//
//
// generate input selection, barrel-shifter has 1cycle delay
//
always@(posedge clk)
if (ena)
case(seli) // synopsis full_case parallel_case
2'b00 :
if (doublet)
x <= {8'b00000000, t, t}; // is this correct ??
else
x <= {sxm, t};
// PAJ ? x <= { {39-15{sxm ? t[15] : 1'b0}}, t};
2'b01 : x <= bp_a ? bp_ar : a;
2'b10 : x <= bp_b ? bp_br : b;
2'b11 : x <= cb;
// PAJ ? 2'b11 : x <= { {39-15{sxm ? cb[15] : 1'b0}}, cb};
endcase
assign y = s; // second input from barrel-shifter
//
// delay control signals
//
always@(posedge clk)
if (ena)
begin
dc16 <= c16;
dci <= ci;
dtci <= tci;
dinst <= inst;
end
//
// generate ALU
//
always@(dinst or x or y or dc16 or dtci or dci)
begin
/*
ico = dci;
itco = dtci;
iresult = x;
*/
case(dinst) // synopsis full_case parallel_case
//
// Arithmetic instructions
//
7'b0000000 : // absolute value
begin
if (x[39])
iresult = (~x) + 1'b1;
else
iresult = x;
ico = ~|(iresult);
end
7'b0000010 : // ALSO ADDC, ADDS. For ADD, ADDS ci = 1'b0;
begin
iresult = x + y + dci;
ico = iresult[32];
end
7'b0000100 : // ALSO MIN. MAX: x==accA, y==accB, MIN: x==accB, y ==accA
begin
ico = (x > y);
iresult = (x > y) ? x : y;
end
7'b0000001 :
begin
iresult = (~x) + 1'b1;
ico = ~|(iresult);
end
7'b0000011 : // ALSO SUBB, SUBS. For SUB, SUBS ci = 1'b1;
begin
iresult = x - y - ~dci;
ico = iresult[32];
end
7'b0000101 : // subtract conditional (for division)
begin
// FIXME: Is this correct ?? How does SUBC affect the carry bit ?
// iresult = x - y;
ico = iresult[32];
if ( x > 0 )
// iresult = (iresult << 1) + 1'b1;
iresult = ({x[38:0], 1'b0}) + 1'b1;
else
// iresult = x << 1;
iresult = {x[38:0], 1'b0};
end
//
// Dual Precision Arithmetic instructions
//
7'b0001000 :
if (dc16) // dual add result_hi/lo = x_hi/lo + y_hi/lo
begin
iresult[39:16] = x[31:16] + y[31:16];
iresult[15: 0] = x[15: 0] + y[15: 0];
end
else // 32bit add result = x + y
{ico, iresult} = x + y;
7'b0001100 :
if (dc16) // dual subtract result_hi/lo = x_hi/lo - y_hi/lo
begin
iresult[39:16] = x[31:16] - y[31:16];
iresult[15: 0] = x[15: 0] - y[15: 0];
end
else // 32bit subtract result = x - y
begin
iresult = x - y;
ico = iresult[32];
end
7'b0001101 : // ALSO DSUBT: make sure x = {T, T}
if (dc16) // dual reverse sub. result_hi/lo = y_hi/lo - x_hi/lo
begin
iresult[39:16] = y[31:16] - x[31:16];
iresult[15: 0] = y[15: 0] - x[15: 0];
end
else // 32bit reverse sub.result = y - x
begin
iresult = y - x;
ico = iresult[32];
end
7'b0001110 : // DSADT: make sure x = {T, T}
if (dc16)
begin
iresult[39:16] = y[31:16] - x[31:16];
iresult[15: 0] = y[15: 0] + x[15: 0];
end
else
begin
iresult = y - x;
ico = iresult[32];
end
7'b0001001 : // DADST: make sure x = {T, T}
if (dc16)
begin
iresult[39:16] = y[31:16] + x[31:16];
iresult[15: 0] = y[15: 0] - x[15: 0];
end
else
begin
iresult = x + y;
ico = iresult[32];
end
//
// logical instructions
//
7'b0010000 : // CMPL
iresult = ~x;
7'b0010001 :
iresult = x & y;
7'b0010010 :
iresult = x | y;
7'b0010011 :
iresult = x ^ y;
//
// shift instructions
//
7'b0010100 :
begin
iresult[39:32] = 8'b00000000;
iresult[31: 0] = {x[30:0], dci};
ico = x[31];
end
7'b0010101 :
begin
iresult[39:32] = 8'b00000000;
iresult[31: 0] = {x[30:0], dtci};
ico = x[31];
end
7'b0010110 :
begin
iresult[39:32] = 8'b00000000;
iresult[31: 0] = {dci, x[31:1]};
ico = x[0];
end
7'b0010111 :
if (x[31] & x[30])
begin
// iresult = x << 1;
iresult = {x[38:0], 1'b0};
itco = 1'b0;
end
else
begin
iresult = x;
itco = 1'b1;
end
//
// bit test and compare instructions
//
7'b0100000 :
itco = ~|( x[15:0] & y[15:0] );
7'b0100001 : // BIT, BITT y=Smem, x=imm or T
//itco = y[ ~x[3:0] ]; // maybe do ~x at a higher level ??
itco = y[0]; // maybe do ~x at a higher level ??
7'b0100100 : // ALSO CMPM. for CMPM [39:16]==0
itco = ~|(x ^ y);
7'b0100101 :
itco = x < y;
7'b0100110 :
itco = x > y;
7'b0100111 :
itco = |(x ^ y);
//
// NOP
//
default :
begin
ico = dci;
itco = dtci;
iresult = x;
end
endcase
end
//
// generate registers
//
// result
always@(posedge clk)
if (ena)
result <= iresult;
// tco, co
always@(posedge clk)
if (ena)
begin
tco <= itco;
co <= ico;
end
endmodule
/////////////////////////////////////////////////////////////////////
//// ////
//// OpenCores54 DSP, ALU defines ////
//// ////
//// Author: Richard Herveille ////
//// [email protected] ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: oc54_alu_defines.v,v 1.1.1.1 2002/04/10 09:34:40 rherveille Exp $
//
// $Date: 2002/04/10 09:34:40 $
// $Revision: 1.1.1.1 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: oc54_alu_defines.v,v $
// Revision 1.1.1.1 2002/04/10 09:34:40 rherveille
// Initial relase OpenCores54x DSP (CPU)
//
//
// Encoding: bit[6] always zero
// bit[5:4] instuction type
// - 00: (dual) arithmetic
// - 01: logical (incl. shift)
// - 10: bit-test & compare
// - 11: reserved
// Leonardo-Spectrum seems to like the additional zero bit[6] in
// the encoding scheme. It produces the smallest and fastest code
// like this. (Why ???)
//
//
// arithmetic instructions
//
//
// dual arithmetic instructions
//
//
// logical instructions
//
//
// shift instructions
//
//
// bit test instructions
//
//
// condition codes for CMP-test
//
/////////////////////////////////////////////////////////////////////
//// ////
//// OpenCores54 DSP, Barrel Shifter ////
//// ////
//// Author: Richard Herveille ////
//// [email protected] ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//
// Xilinx Virtex-E WC: 348 CLB slices @ 68MHz
//
// CVS Log
//
// $Id: oc54_bshft.v,v 1.1.1.1 2002/04/10 09:34:40 rherveille Exp $
//
// $Date: 2002/04/10 09:34:40 $
// $Revision: 1.1.1.1 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: oc54_bshft.v,v $
// Revision 1.1.1.1 2002/04/10 09:34:40 rherveille
// Initial relase OpenCores54x DSP (CPU)
//
module oc54_bshft (
clk, ena,
a, b, cb, db,
bp_a, bp_b, bp_ar, bp_br,
l_na, sxm, seli, selo,
t, asm, imm,
result, co
);
//
// parameters
//
//
// inputs & outputs
//
input clk;
input ena;
input [39:0] a, b; // accumulator
input [15:0] cb, db; // memory data inputs
input [39:0] bp_ar, bp_br; // bypass a register, bypass b register
input bp_a, bp_b; // bypass select
input sxm; // sign extend mode
input l_na; // logical/not arithmetic shift
input [ 1:0] seli; // select operand (input)
input [ 1:0] selo; // select operator
input [ 5:0] t; // TREG, 6lsbs
input asm; // asm bits
input imm; // 5bit immediate value
output [39:0] result;
output co; // carry out output
reg [39:0] result;
reg co;
//
// variables
//
reg [ 5:0] shift_cnt;
reg [39:0] operand;
//
// module body
//
//
// generate shift count
//
always@(selo or t or asm or imm)
case (selo) // synopsis full_case parallel_case
2'b00: shift_cnt = t;
2'b01: shift_cnt = {asm, asm, asm, asm, asm};
2'b10: shift_cnt = {imm, imm, imm, imm, imm};
2'b11: shift_cnt = {imm, imm, imm, imm, imm};
endcase
//
// generate operand
//
always@(seli or bp_a or a or bp_ar or bp_b or b or bp_br or cb or db)
case (seli) // synopsis full_case parallel_case
2'b00 : operand = bp_b ? bp_br : b;
2'b01 : operand = bp_a ? bp_ar : a;
2'b10 : operand = db; // 16bit operand databus
2'b11 : operand = {cb, db}; // 32bit operand
endcase
//
// generate shifter
//
always@(posedge clk)
if (ena)
if (l_na) // logical shift
if (shift_cnt[5])
begin
result[39:32] <= 8'h0;
//result[31: 0] <= operand[31:0] >> (~shift_cnt[4:0] +1'h1);
result[31: 0] <= operand[31:0] >> 2;//(~shift_cnt[4:0] +1'h1);
//co <= operand[ ~shift_cnt[4:0] ];
co <= operand[0];
end
else if ( ~|shift_cnt[4:0] )
begin
result <= operand;
co <= 1'b0;
end
else
begin
result[39:32] <= 8'h0;
//result[31: 0] <= operand[31:0] << shift_cnt[4:0];
result[31: 0] <= operand[31:0] << 1;// shift_cnt[4:0];
//co <= operand[ 5'h1f - shift_cnt[4:0] ];
co <= operand[0];
end
else // arithmetic shift
if (shift_cnt[5])
begin
if (sxm)
//result <= { {16{operand[39]}} ,operand} >> (~shift_cnt[4:0] +1'h1);
result <= operand >> 4;// (~shift_cnt[4:0] +1'h1);
else
//result <= operand >> (~shift_cnt[4:0] +1'h1);
result <= operand >> 3;// (~shift_cnt[4:0] +1'h1);
//co <= operand[ ~shift_cnt[4:0] ];
co <= operand[0];
end
else
begin
result <= operand << 5;// shift_cnt[4:0];
//result <= operand << shift_cnt[4:0];
//co <= operand[ 6'h27 - shift_cnt[4:0] ];
co <= operand[0];
end
endmodule
/////////////////////////////////////////////////////////////////////
//// ////
//// OpenCores54 DSP, Compare Select and Store Unit (CSSU) ////
//// ////
//// Author: Richard Herveille ////
//// [email protected] ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//
// NOTE: Read the pipeline information for the CMPS instruction
//
//
// Xilinx Virtex-E WC: 41 CLB slices @ 130MHz
//
// CVS Log
//
// $Id: oc54_cssu.v,v 1.1.1.1 2002/04/10 09:34:41 rherveille Exp $
//
// $Date: 2002/04/10 09:34:41 $
// $Revision: 1.1.1.1 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: oc54_cssu.v,v $
// Revision 1.1.1.1 2002/04/10 09:34:41 rherveille
// Initial relase OpenCores54x DSP (CPU)
//
module oc54_cssu (
clk, ena,
sel_acc, is_cssu,
a, b, s,
tco,
trn, result
);
//
// parameters
//
//
// inputs & outputs
//
input clk;
input ena;
input sel_acc; // select input
input is_cssu; // is this a cssu operation ?
input [39:0] a, b, s; // accumulators, shifter input
output tco; // tc-out
output [15:0] trn, result;
reg tco;
reg [15:0] trn, result;
//
// variables
//
wire [31:0] acc; // selected accumulator
wire acc_cmp; // acc[31;16]>acc[15:0] ??
//
// module body
//
//
// generate input selection
//
// input selection
assign acc = sel_acc ? b[39:0] : a[39:0];
assign acc_cmp = acc[31:16] > acc[15:0];
// result
always@(posedge clk)
if (ena)
begin
if (is_cssu)
if (acc_cmp)
result <= acc[31:16];
else
result <= acc[15:0];
else
result <= s[39:0];
if (is_cssu)
trn <= {trn[14:0], ~acc_cmp};
tco <= ~acc_cmp;
end
endmodule
/////////////////////////////////////////////////////////////////////
//// ////
//// OpenCores54 DSP, Exponent Encoder ////
//// ////
//// Author: Richard Herveille ////
//// [email protected] ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//
// Xilinx Virtex-E WC: 116 CLB slices @ 74MHz, pass 4
//
// CVS Log
//
// $Id: oc54_exp.v,v 1.1.1.1 2002/04/10 09:34:41 rherveille Exp $
//
// $Date: 2002/04/10 09:34:41 $
// $Revision: 1.1.1.1 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: oc54_exp.v,v $
// Revision 1.1.1.1 2002/04/10 09:34:41 rherveille
// Initial relase OpenCores54x DSP (CPU)
//
module oc54_exp (
clk, ena,
sel_acc,
a, b,
bp_ar, bp_br,
bp_a, bp_b,
result
);
//
// parameters
//
//
// inputs & outputs
//
input clk;
input ena;
input sel_acc; // select accumulator
input [39:0] a, b; // accumulator inputs
input [39:0] bp_ar, bp_br; // bypass accumulator a / b
input bp_a, bp_b; // bypass selects
output [ 5:0] result;
reg [5:0] result;
//
// variables
//
reg [39:0] acc;
/////////////////
// module body //
///////////////// 34('1') - 1(sign bit) - 8
//
// generate input selection
//
// input selection
always@(posedge clk)
if (ena)
if (sel_acc)
acc <= bp_b ? bp_br : b;
else
acc <= bp_a ? bp_ar : a;
//
// Generate exponent encoder
//
// The result of the exponent encoder is the number of leading
// redundant bits, except the sign-bit, -8. Exp is in the -8 to +31 range.
// 00_0110 -> 11_1001 -> 11_1010
always@(posedge clk)
if (ena)
/*
case (acc) // synopsis full_case parallel_case
//
// positive numbers
//
40'b01??_????_????_????_????_????_????_????_????_????:
result <= 6'h38; // 1 (leading red. bit) - 1 (sign bit) - 8 = -8
40'b001?_????_????_????_????_????_????_????_????_????:
result <= 6'h39; // 2 (leading red. bit) - 1 (sign bit) - 8 = -7
40'b0001_????_????_????_????_????_????_????_????_????:
result <= 6'h3a; // 3 (leading red. bit) - 1 (sign bit) - 8 = -6
40'b0000_1???_????_????_????_????_????_????_????_????:
result <= #1 6'h3b; // 4 (leading red. bit) - 1 (sign bit) - 8 = -5
40'b0000_01??_????_????_????_????_????_????_????_????:
result <= #1 6'h3c; // 5 (leading red. bit) - 1 (sign bit) - 8 = -4
40'b0000_001?_????_????_????_????_????_????_????_????:
result <= #1 6'h3d; // 6 (leading red. bit) - 1 (sign bit) - 8 = -3
40'b0000_0001_????_????_????_????_????_????_????_????:
result <= #1 6'h3e; // 7 (leading red. bit) - 1 (sign bit) - 8 = -2
40'b0000_0000_1???_????_????_????_????_????_????_????:
result <= #1 6'h3f; // 8 (leading red. bit) - 1 (sign bit) - 8 = -1
40'b0000_0000_01??_????_????_????_????_????_????_????:
result <= #1 6'h00; // 9 (leading red. bit) - 1 (sign bit) - 8 = 0
40'b0000_0000_001?_????_????_????_????_????_????_????:
result <= #1 6'h01; //10 (leading red. bit) - 1 (sign bit) - 8 = 1
40'b0000_0000_0001_????_????_????_????_????_????_????:
result <= #1 6'h02; //11 (leading red. bit) - 1 (sign bit) - 8 = 2
40'b0000_0000_0000_1???_????_????_????_????_????_????:
result <= #1 6'h03; //12 (leading red. bit) - 1 (sign bit) - 8 = 3
40'b0000_0000_0000_01??_????_????_????_????_????_????:
result <= #1 6'h04; //13 (leading red. bit) - 1 (sign bit) - 8 = 4
40'b0000_0000_0000_001?_????_????_????_????_????_????:
result <= #1 6'h05; //14 (leading red. bit) - 1 (sign bit) - 8 = 5
40'b0000_0000_0000_0001_????_????_????_????_????_????:
result <= #1 6'h06; //15 (leading red. bit) - 1 (sign bit) - 8 = 6
40'b0000_0000_0000_0000_1???_????_????_????_????_????:
result <= #1 6'h07; //16 (leading red. bit) - 1 (sign bit) - 8 = 7
40'b0000_0000_0000_0000_01??_????_????_????_????_????:
result <= #1 6'h08; //17 (leading red. bit) - 1 (sign bit) - 8 = 8
40'b0000_0000_0000_0000_001?_????_????_????_????_????:
result <= #1 6'h09; //18 (leading red. bit) - 1 (sign bit) - 8 = 9
40'b0000_0000_0000_0000_0001_????_????_????_????_????:
result <= #1 6'h0a; //19 (leading red. bit) - 1 (sign bit) - 8 =10
40'b0000_0000_0000_0000_0000_1???_????_????_????_????:
result <= #1 6'h0b; //20 (leading red. bit) - 1 (sign bit) - 8 =11
40'b0000_0000_0000_0000_0000_01??_????_????_????_????:
result <= #1 6'h0c; //21 (leading red. bit) - 1 (sign bit) - 8 =12
40'b0000_0000_0000_0000_0000_001?_????_????_????_????:
result <= #1 6'h0d; //22 (leading red. bit) - 1 (sign bit) - 8 =13
40'b0000_0000_0000_0000_0000_0001_????_????_????_????:
result <= #1 6'h0e; //23 (leading red. bit) - 1 (sign bit) - 8 =14
40'b0000_0000_0000_0000_0000_0000_1???_????_????_????:
result <= #1 6'h0f; //24 (leading red. bit) - 1 (sign bit) - 8 =15
40'b0000_0000_0000_0000_0000_0000_01??_????_????_????:
result <= #1 6'h10; //25 (leading red. bit) - 1 (sign bit) - 8 =16
40'b0000_0000_0000_0000_0000_0000_001?_????_????_????:
result <= #1 6'h11; //26 (leading red. bit) - 1 (sign bit) - 8 =17
40'b0000_0000_0000_0000_0000_0000_0001_????_????_????:
result <= #1 6'h12; //27 (leading red. bit) - 1 (sign bit) - 8 =18
40'b0000_0000_0000_0000_0000_0000_0000_1???_????_????:
result <= #1 6'h13; //28 (leading red. bit) - 1 (sign bit) - 8 =19
40'b0000_0000_0000_0000_0000_0000_0000_01??_????_????:
result <= #1 6'h14; //29 (leading red. bit) - 1 (sign bit) - 8 =20
40'b0000_0000_0000_0000_0000_0000_0000_001?_????_????:
result <= #1 6'h15; //30 (leading red. bit) - 1 (sign bit) - 8 =21
40'b0000_0000_0000_0000_0000_0000_0000_0001_????_????:
result <= #1 6'h16; //31 (leading red. bit) - 1 (sign bit) - 8 =22
40'b0000_0000_0000_0000_0000_0000_0000_0000_1???_????:
result <= #1 6'h17; //32 (leading red. bit) - 1 (sign bit) - 8 =23
40'b0000_0000_0000_0000_0000_0000_0000_0000_01??_????:
result <= #1 6'h18; //33 (leading red. bit) - 1 (sign bit) - 8 =24
40'b0000_0000_0000_0000_0000_0000_0000_0000_001?_????:
result <= #1 6'h19; //34 (leading red. bit) - 1 (sign bit) - 8 =25
40'b0000_0000_0000_0000_0000_0000_0000_0000_0001_????:
result <= #1 6'h1a; //35 (leading red. bit) - 1 (sign bit) - 8 =26
40'b0000_0000_0000_0000_0000_0000_0000_0000_0000_1???:
result <= #1 6'h1b; //36 (leading red. bit) - 1 (sign bit) - 8 =27
40'b0000_0000_0000_0000_0000_0000_0000_0000_0000_01??:
result <= #1 6'h1c; //37 (leading red. bit) - 1 (sign bit) - 8 =28
40'b0000_0000_0000_0000_0000_0000_0000_0000_0000_001?:
result <= #1 6'h1d; //38 (leading red. bit) - 1 (sign bit) - 8 =29
40'b0000_0000_0000_0000_0000_0000_0000_0000_0000_0001:
result <= #1 6'h1e; //39 (leading red. bit) - 1 (sign bit) - 8 =30
40'b0000_0000_0000_0000_0000_0000_0000_0000_0000_0000:
result <= #1 6'h1f; //40 (leading red. bit) - 1 (sign bit) - 8 =31
//
// negative numbers
//
40'b10??_????_????_????_????_????_????_????_????_????:
result <= #1 6'h38; // 1 (leading red. bit) - 1 (sign bit) - 8 = -8
40'b110?_????_????_????_????_????_????_????_????_????:
result <= #1 6'h39; // 2 (leading red. bit) - 1 (sign bit) - 8 = -7
40'b1110_????_????_????_????_????_????_????_????_????:
result <= #1 6'h3a; // 3 (leading red. bit) - 1 (sign bit) - 8 = -6
40'b1111_0???_????_????_????_????_????_????_????_????:
result <= #1 6'h3b; // 4 (leading red. bit) - 1 (sign bit) - 8 = -5
40'b1111_10??_????_????_????_????_????_????_????_????:
result <= #1 6'h3c; // 5 (leading red. bit) - 1 (sign bit) - 8 = -4
40'b1111_110?_????_????_????_????_????_????_????_????:
result <= #1 6'h3d; // 6 (leading red. bit) - 1 (sign bit) - 8 = -3
40'b1111_1110_????_????_????_????_????_????_????_????:
result <= #1 6'h3e; // 7 (leading red. bit) - 1 (sign bit) - 8 = -2
40'b1111_1111_0???_????_????_????_????_????_????_????:
result <= #1 6'h3f; // 8 (leading red. bit) - 1 (sign bit) - 8 = -1
40'b1111_1111_10??_????_????_????_????_????_????_????:
result <= #1 6'h00; // 9 (leading red. bit) - 1 (sign bit) - 8 = 0
40'b1111_1111_110?_????_????_????_????_????_????_????:
result <= #1 6'h01; //10 (leading red. bit) - 1 (sign bit) - 8 = 1
40'b1111_1111_1110_????_????_????_????_????_????_????:
result <= #1 6'h02; //11 (leading red. bit) - 1 (sign bit) - 8 = 2
40'b1111_1111_1111_0???_????_????_????_????_????_????:
result <= #1 6'h03; //12 (leading red. bit) - 1 (sign bit) - 8 = 3
40'b1111_1111_1111_10??_????_????_????_????_????_????:
result <= #1 6'h04; //13 (leading red. bit) - 1 (sign bit) - 8 = 4
40'b1111_1111_1111_110?_????_????_????_????_????_????:
result <= #1 6'h05; //14 (leading red. bit) - 1 (sign bit) - 8 = 5
40'b1111_1111_1111_1110_????_????_????_????_????_????:
result <= #1 6'h06; //15 (leading red. bit) - 1 (sign bit) - 8 = 6
40'b1111_1111_1111_1111_0???_????_????_????_????_????:
result <= #1 6'h07; //16 (leading red. bit) - 1 (sign bit) - 8 = 7
40'b1111_1111_1111_1111_10??_????_????_????_????_????:
result <= #1 6'h08; //17 (leading red. bit) - 1 (sign bit) - 8 = 8
40'b1111_1111_1111_1111_110?_????_????_????_????_????:
result <= #1 6'h09; //18 (leading red. bit) - 1 (sign bit) - 8 = 9
40'b1111_1111_1111_1111_1110_????_????_????_????_????:
result <= #1 6'h0a; //19 (leading red. bit) - 1 (sign bit) - 8 =10
40'b1111_1111_1111_1111_1111_0???_????_????_????_????:
result <= #1 6'h0b; //20 (leading red. bit) - 1 (sign bit) - 8 =11
40'b1111_1111_1111_1111_1111_10??_????_????_????_????:
result <= #1 6'h0c; //21 (leading red. bit) - 1 (sign bit) - 8 =12
40'b1111_1111_1111_1111_1111_110?_????_????_????_????:
result <= #1 6'h0d; //22 (leading red. bit) - 1 (sign bit) - 8 =13
40'b1111_1111_1111_1111_1111_1110_????_????_????_????:
result <= #1 6'h0e; //23 (leading red. bit) - 1 (sign bit) - 8 =14
40'b1111_1111_1111_1111_1111_1111_0???_????_????_????:
result <= #1 6'h0f; //24 (leading red. bit) - 1 (sign bit) - 8 =15
40'b1111_1111_1111_1111_1111_1111_10??_????_????_????:
result <= #1 6'h10; //25 (leading red. bit) - 1 (sign bit) - 8 =16
40'b1111_1111_1111_1111_1111_1111_110?_????_????_????:
result <= #1 6'h11; //26 (leading red. bit) - 1 (sign bit) - 8 =17
40'b1111_1111_1111_1111_1111_1111_1110_????_????_????:
result <= #1 6'h12; //27 (leading red. bit) - 1 (sign bit) - 8 =18
40'b1111_1111_1111_1111_1111_1111_1111_0???_????_????:
result <= #1 6'h13; //28 (leading red. bit) - 1 (sign bit) - 8 =19
40'b1111_1111_1111_1111_1111_1111_1111_10??_????_????:
result <= #1 6'h14; //29 (leading red. bit) - 1 (sign bit) - 8 =20
40'b1111_1111_1111_1111_1111_1111_1111_110?_????_????:
result <= #1 6'h15; //30 (leading red. bit) - 1 (sign bit) - 8 =21
40'b1111_1111_1111_1111_1111_1111_1111_1110_????_????:
result <= #1 6'h16; //31 (leading red. bit) - 1 (sign bit) - 8 =22
40'b1111_1111_1111_1111_1111_1111_1111_1111_0???_????:
result <= #1 6'h17; //32 (leading red. bit) - 1 (sign bit) - 8 =23
40'b1111_1111_1111_1111_1111_1111_1111_1111_10??_????:
result <= #1 6'h18; //33 (leading red. bit) - 1 (sign bit) - 8 =24
40'b1111_1111_1111_1111_1111_1111_1111_1111_110?_????:
result <= #1 6'h19; //34 (leading red. bit) - 1 (sign bit) - 8 =25
40'b1111_1111_1111_1111_1111_1111_1111_1111_1110_????:
result <= #1 6'h1a; //35 (leading red. bit) - 1 (sign bit) - 8 =26
40'b1111_1111_1111_1111_1111_1111_1111_1111_1111_0???:
result <= #1 6'h1b; //36 (leading red. bit) - 1 (sign bit) - 8 =27
40'b1111_1111_1111_1111_1111_1111_1111_1111_1111_10??:
result <= #1 6'h1c; //37 (leading red. bit) - 1 (sign bit) - 8 =28
40'b1111_1111_1111_1111_1111_1111_1111_1111_1111_110?:
result <= #1 6'h1d; //38 (leading red. bit) - 1 (sign bit) - 8 =29
40'b1111_1111_1111_1111_1111_1111_1111_1111_1111_1110:
result <= #1 6'h1e; //39 (leading red. bit) - 1 (sign bit) - 8 =30
40'b1111_1111_1111_1111_1111_1111_1111_1111_1111_1111:
result <= #1 6'h1f; //40 (leading red. bit) - 1 (sign bit) - 8 =31
endcase
*/
if (acc)
result <= 6'h1f; //40 (leading red. bit) - 1 (sign bit) - 8 =31
else
result <= 6'h1e; //39 (leading red. bit) - 1 (sign bit) - 8 =30
endmodule
/////////////////////////////////////////////////////////////////////
//// ////
//// OpenCores54 DSP, MAC ////
//// ////
//// Author: Richard Herveille ////
//// [email protected] ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//
// Xilinx Virtex-E WC: 296 CLB slices @ 64MHz
//
// CVS Log
//
// $Id: oc54_mac.v,v 1.1.1.1 2002/04/10 09:34:41 rherveille Exp $
//
// $Date: 2002/04/10 09:34:41 $
// $Revision: 1.1.1.1 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: oc54_mac.v,v $
// Revision 1.1.1.1 2002/04/10 09:34:41 rherveille
// Initial relase OpenCores54x DSP (CPU)
//
module oc54_mac (
clk, ena,
a, b, t, p, c, d,
sel_xm, sel_ym, sel_ya,
bp_a, bp_b, bp_ar, bp_br,
xm_s, ym_s,
ovm, frct, smul, add_sub,
result
);
//
// parameters
//
//
// inputs & outputs
//
input clk;
input ena;
input [15:0] t, p, c, d; // TREG, p-bus, c-bus, d-bus inputs
input [39:0] a, b; // accumulator inputs
input [ 1:0] sel_xm, sel_ym, sel_ya; // input selects
input [39:0] bp_ar, bp_br; // bypass accumulator a / b
input bp_a, bp_b; // bypass selects
input xm_s, ym_s; // sign extend xm, ym
input ovm, frct, smul, add_sub;
output [39:0] result;
reg [39:0] result;
//
// variables
//
reg [16:0] xm, ym; // multiplier inputs
reg [39:0] ya; // adder Y-input
reg [33:0] mult_res; // multiplier result
wire [33:0] imult_res; // actual multiplier
reg [39:0] iresult; // mac-result
/////////////////
// module body //
/////////////////
//
// generate input selection
//
wire bit1;
assign bit1 = xm_s ? t[15] : 1'b0;
wire bit2;
assign bit2 = ym_s ? p[15] : 1'b0;
// xm
always@(posedge clk)
begin
if (ena)
case(sel_xm) // synopsis full_case parallel_case
2'b00 : xm <= {bit1, t};
2'b01 : xm <= {bit1, d};
2'b10 : xm <= bp_a ? bp_ar[32:16] : a[32:16];
2'b11 : xm <= 17'h0;
endcase
end
// ym
always@(posedge clk)
if (ena)
case(sel_ym) // synopsis full_case parallel_case
2'b00 : ym <= {bit2, p};
2'b01 : ym <= bp_a ? bp_ar[32:16] : a[32:16];
2'b10 : ym <= {bit2, d};
2'b11 : ym <= {bit2, c};
endcase
// ya
always@(posedge clk)
if (ena)
case(sel_ya) // synopsis full_case parallel_case
2'b00 : ya <= bp_a ? bp_ar : a;
2'b01 : ya <= bp_b ? bp_br : b;
default : ya <= 40'h0;
endcase
//
// generate multiplier
//
assign imult_res = (xm * ym); // actual multiplier
always@(xm or ym or smul or ovm or frct or imult_res)
if (smul && ovm && frct && (xm[15:0] == 16'h8000) && (ym[15:0] == 16'h8000) )
mult_res = 34'h7ffffff;
else if (frct)
mult_res = {imult_res[32:0], 1'b0}; // (imult_res << 1)
else
mult_res = imult_res;
//
// generate mac-unit
//
always@(mult_res or ya or add_sub)
if (add_sub)
iresult = mult_res + ya;
else
iresult = mult_res - ya;
//
// generate registers
//
// result
always@(posedge clk)
if (ena)
result <= iresult;
endmodule
/////////////////////////////////////////////////////////////////////
//// ////
//// OpenCores54 DSP, Temporary Register (TREG) ////
//// ////
//// Author: Richard Herveille ////
//// [email protected] ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//
// NOTE: Read the pipeline information for the CMPS instruction
//
//
// Xilinx Virtex-E WC: 41 CLB slices @ 130MHz
//
// CVS Log
//
// $Id: oc54_treg.v,v 1.1.1.1 2002/04/10 09:34:41 rherveille Exp $
//
// $Date: 2002/04/10 09:34:41 $
// $Revision: 1.1.1.1 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: oc54_treg.v,v $
// Revision 1.1.1.1 2002/04/10 09:34:41 rherveille
// Initial relase OpenCores54x DSP (CPU)
//
module oc54_treg (
clk, ena,
seli, we,
exp, d,
result
);
//
// parameters
//
//
// inputs & outputs
//
input clk;
input ena;
input seli; // select input
input we; // store result
input [5:0] exp; // exponent encoder input
input [15:0] d; // DB input
output [15:0] result;
reg [15:0] result;
//
// variables
//
//
// module body
//
//
// generate input selection
//
// result
always@(posedge clk)
if (ena)
if (we)
result <= seli ? {10'h0, exp} : d;
endmodule
|
(** * Logic: Logic in Coq *)
Set Warnings "-notation-overridden,-parsing,-deprecated-hint-without-locality".
From LF Require Export Tactics.
(** We have seen many examples of factual claims (_propositions_)
and ways of presenting evidence of their truth (_proofs_). In
particular, we have worked extensively with _equality
propositions_ ([e1 = e2]), implications ([P -> Q]), and quantified
propositions ([forall x, P]). In this chapter, we will see how
Coq can be used to carry out other familiar forms of logical
reasoning.
Before diving into details, let's talk a bit about the status of
mathematical statements in Coq. Recall that Coq is a _typed_
language, which means that every sensible expression in its world
has an associated type. Logical claims are no exception: any
statement we might try to prove in Coq has a type, namely [Prop],
the type of _propositions_. We can see this with the [Check]
command: *)
Check (3 = 3) : Prop.
Check (forall n m : nat, n + m = m + n) : Prop.
(** Note that _all_ syntactically well-formed propositions have type
[Prop] in Coq, regardless of whether they are true.
Simply _being_ a proposition is one thing; being _provable_ is
a different thing! *)
Check 2 = 2 : Prop.
Check 3 = 2 : Prop.
Check forall n : nat, n = 2 : Prop.
(** Indeed, propositions not only have types: they are
_first-class_ entities that can be manipulated in all the same
ways as any of the other things in Coq's world. *)
(** So far, we've seen one primary place that propositions can appear:
in [Theorem] (and [Lemma] and [Example]) declarations. *)
Theorem plus_2_2_is_4 :
2 + 2 = 4.
Proof. reflexivity. Qed.
(** But propositions can be used in many other ways. For example, we
can give a name to a proposition using a [Definition], just as we
have given names to other kinds of expressions. *)
Definition plus_claim : Prop := 2 + 2 = 4.
Check plus_claim : Prop.
(** We can later use this name in any situation where a proposition is
expected -- for example, as the claim in a [Theorem] declaration. *)
Theorem plus_claim_is_true :
plus_claim.
Proof. reflexivity. Qed.
(** We can also write _parameterized_ propositions -- that is,
functions that take arguments of some type and return a
proposition. *)
(** For instance, the following function takes a number
and returns a proposition asserting that this number is equal to
three: *)
Definition is_three (n : nat) : Prop :=
n = 3.
Check is_three : nat -> Prop.
(** In Coq, functions that return propositions are said to define
_properties_ of their arguments.
For instance, here's a (polymorphic) property defining the
familiar notion of an _injective function_. *)
Definition injective {A B} (f : A -> B) :=
forall x y : A, f x = f y -> x = y.
Lemma succ_inj : injective S.
Proof.
intros n m H. injection H as H1. apply H1.
Qed.
(** The equality operator [=] is also a function that returns a
[Prop].
The expression [n = m] is syntactic sugar for [eq n m] (defined in
Coq's standard library using the [Notation] mechanism). Because
[eq] can be used with elements of any type, it is also
polymorphic: *)
Check @eq : forall A : Type, A -> A -> Prop.
(** (Notice that we wrote [@eq] instead of [eq]: The type
argument [A] to [eq] is declared as implicit, and we need to turn
off the inference of this implicit argument to see the full type
of [eq].) *)
(* ################################################################# *)
(** * Logical Connectives *)
(* ================================================================= *)
(** ** Conjunction *)
(** The _conjunction_, or _logical and_, of propositions [A] and [B]
is written [A /\ B], representing the claim that both [A] and [B]
are true. *)
Example and_example : 3 + 4 = 7 /\ 2 * 2 = 4.
(** To prove a conjunction, use the [split] tactic. It will generate
two subgoals, one for each part of the statement: *)
Proof.
split.
- (* 3 + 4 = 7 *) reflexivity.
- (* 2 * 2 = 4 *) reflexivity.
Qed.
(** For any propositions [A] and [B], if we assume that [A] is true
and that [B] is true, we can conclude that [A /\ B] is also
true. *)
Lemma and_intro : forall A B : Prop, A -> B -> A /\ B.
Proof.
intros A B HA HB. split.
- apply HA.
- apply HB.
Qed.
(** Since applying a theorem with hypotheses to some goal has the
effect of generating as many subgoals as there are hypotheses for
that theorem, we can apply [and_intro] to achieve the same effect
as [split]. *)
Example and_example' : 3 + 4 = 7 /\ 2 * 2 = 4.
Proof.
apply and_intro.
- (* 3 + 4 = 7 *) reflexivity.
- (* 2 + 2 = 4 *) reflexivity.
Qed.
(** **** Exercise: 2 stars, standard (and_exercise) *)
Example and_exercise :
forall n m : nat, n + m = 0 -> n = 0 /\ m = 0.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** So much for proving conjunctive statements. To go in the other
direction -- i.e., to _use_ a conjunctive hypothesis to help prove
something else -- we employ the [destruct] tactic.
If the proof context contains a hypothesis [H] of the form
[A /\ B], writing [destruct H as [HA HB]] will remove [H] from the
context and add two new hypotheses: [HA], stating that [A] is
true, and [HB], stating that [B] is true. *)
Lemma and_example2 :
forall n m : nat, n = 0 /\ m = 0 -> n + m = 0.
Proof.
(* WORKED IN CLASS *)
intros n m H.
destruct H as [Hn Hm].
rewrite Hn. rewrite Hm.
reflexivity.
Qed.
(** As usual, we can also destruct [H] right when we introduce it,
instead of introducing and then destructing it: *)
Lemma and_example2' :
forall n m : nat, n = 0 /\ m = 0 -> n + m = 0.
Proof.
intros n m [Hn Hm].
rewrite Hn. rewrite Hm.
reflexivity.
Qed.
(** You may wonder why we bothered packing the two hypotheses [n = 0]
and [m = 0] into a single conjunction, since we could have also
stated the theorem with two separate premises: *)
Lemma and_example2'' :
forall n m : nat, n = 0 -> m = 0 -> n + m = 0.
Proof.
intros n m Hn Hm.
rewrite Hn. rewrite Hm.
reflexivity.
Qed.
(** For this specific theorem, both formulations are fine. But
it's important to understand how to work with conjunctive
hypotheses because conjunctions often arise from intermediate
steps in proofs, especially in larger developments. Here's a
simple example: *)
Lemma and_example3 :
forall n m : nat, n + m = 0 -> n * m = 0.
Proof.
(* WORKED IN CLASS *)
intros n m H.
apply and_exercise in H.
destruct H as [Hn Hm].
rewrite Hn. reflexivity.
Qed.
(** Another common situation with conjunctions is that we know
[A /\ B] but in some context we need just [A] or just [B].
In such cases we can do a [destruct] (possibly as part of
an [intros]) and use an underscore pattern [_] to indicate
that the unneeded conjunct should just be thrown away. *)
Lemma proj1 : forall P Q : Prop,
P /\ Q -> P.
Proof.
intros P Q HPQ.
destruct HPQ as [HP _].
apply HP. Qed.
(** **** Exercise: 1 star, standard, optional (proj2) *)
Lemma proj2 : forall P Q : Prop,
P /\ Q -> Q.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Finally, we sometimes need to rearrange the order of conjunctions
and/or the grouping of multi-way conjunctions. The following
commutativity and associativity theorems are handy in such
cases. *)
Theorem and_commut : forall P Q : Prop,
P /\ Q -> Q /\ P.
Proof.
intros P Q [HP HQ].
split.
- (* left *) apply HQ.
- (* right *) apply HP. Qed.
(** **** Exercise: 2 stars, standard (and_assoc)
(In the following proof of associativity, notice how the _nested_
[intros] pattern breaks the hypothesis [H : P /\ (Q /\ R)] down into
[HP : P], [HQ : Q], and [HR : R]. Finish the proof from
there.) *)
Theorem and_assoc : forall P Q R : Prop,
P /\ (Q /\ R) -> (P /\ Q) /\ R.
Proof.
intros P Q R [HP [HQ HR]].
(* FILL IN HERE *) Admitted.
(** [] *)
(** By the way, the infix notation [/\] is actually just syntactic
sugar for [and A B]. That is, [and] is a Coq operator that takes
two propositions as arguments and yields a proposition. *)
Check and : Prop -> Prop -> Prop.
(* ================================================================= *)
(** ** Disjunction *)
(** Another important connective is the _disjunction_, or _logical or_,
of two propositions: [A \/ B] is true when either [A] or [B]
is. (This infix notation stands for [or A B], where [or : Prop ->
Prop -> Prop].) *)
(** To use a disjunctive hypothesis in a proof, we proceed by case
analysis (which, as with other data types like [nat], can be done
explicitly with [destruct] or implicitly with an [intros]
pattern): *)
Lemma factor_is_O:
forall n m : nat, n = 0 \/ m = 0 -> n * m = 0.
Proof.
(* This pattern implicitly does case analysis on
[n = 0 \/ m = 0] *)
intros n m [Hn | Hm].
- (* Here, [n = 0] *)
rewrite Hn. reflexivity.
- (* Here, [m = 0] *)
rewrite Hm. rewrite <- mult_n_O.
reflexivity.
Qed.
(** Conversely, to show that a disjunction holds, it suffices to show
that one of its sides holds. This is done via two tactics, [left]
and [right]. As their names imply, the first one requires proving
the left side of the disjunction, while the second requires
proving its right side. Here is a trivial use... *)
Lemma or_intro_l : forall A B : Prop, A -> A \/ B.
Proof.
intros A B HA.
left.
apply HA.
Qed.
(** ... and here is a slightly more interesting example requiring both
[left] and [right]: *)
Lemma zero_or_succ :
forall n : nat, n = 0 \/ n = S (pred n).
Proof.
(* WORKED IN CLASS *)
intros [|n'].
- left. reflexivity.
- right. reflexivity.
Qed.
(** **** Exercise: 1 star, standard (mult_is_O) *)
Lemma mult_is_O :
forall n m, n * m = 0 -> n = 0 \/ m = 0.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star, standard (or_commut) *)
Theorem or_commut : forall P Q : Prop,
P \/ Q -> Q \/ P.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ================================================================= *)
(** ** Falsehood and Negation
So far, we have mostly been concerned with proving that certain
things are _true_ -- addition is commutative, appending lists is
associative, etc. Of course, we may also be interested in
negative results, demonstrating that some given proposition is
_not_ true. Such statements are expressed with the logical
negation operator [~]. *)
(** To see how negation works, recall the _principle of explosion_
from the [Tactics] chapter, which asserts that, if we assume a
contradiction, then any other proposition can be derived.
Following this intuition, we could define [~ P] ("not [P]") as
[forall Q, P -> Q].
Coq actually makes a slightly different (but equivalent) choice,
defining [~ P] as [P -> False], where [False] is a specific
contradictory proposition defined in the standard library. *)
Module MyNot.
Definition not (P:Prop) := P -> False.
Notation "~ x" := (not x) : type_scope.
Check not : Prop -> Prop.
End MyNot.
(** Since [False] is a contradictory proposition, the principle of
explosion also applies to it. If we get [False] into the proof
context, we can use [destruct] on it to complete any goal: *)
Theorem ex_falso_quodlibet : forall (P:Prop),
False -> P.
Proof.
(* WORKED IN CLASS *)
intros P contra.
destruct contra. Qed.
(** The Latin _ex falso quodlibet_ means, literally, "from falsehood
follows whatever you like"; this is another common name for the
principle of explosion. *)
(** **** Exercise: 2 stars, standard, optional (not_implies_our_not)
Show that Coq's definition of negation implies the intuitive one
mentioned above: *)
Fact not_implies_our_not : forall (P:Prop),
~ P -> (forall (Q:Prop), P -> Q).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Inequality is a frequent enough example of negated statement
that there is a special notation for it, [x <> y]:
Notation "x <> y" := (~(x = y)).
*)
(** We can use [not] to state that [0] and [1] are different elements
of [nat]: *)
Theorem zero_not_one : 0 <> 1.
Proof.
(** The proposition [0 <> 1] is exactly the same as
[~(0 = 1)], that is [not (0 = 1)], which unfolds to
[(0 = 1) -> False]. (We use [unfold not] explicitly here
to illustrate that point, but generally it can be omitted.) *)
unfold not.
(** To prove an inequality, we may assume the opposite
equality... *)
intros contra.
(** ... and deduce a contradiction from it. Here, the
equality [O = S O] contradicts the disjointness of
constructors [O] and [S], so [discriminate] takes care
of it. *)
discriminate contra.
Qed.
(** It takes a little practice to get used to working with negation in
Coq. Even though you can see perfectly well why a statement
involving negation is true, it can be a little tricky at first to
make Coq understand it! Here are proofs of a few familiar facts
to get you warmed up. *)
Theorem not_False :
~ False.
Proof.
unfold not. intros H. destruct H. Qed.
Theorem contradiction_implies_anything : forall P Q : Prop,
(P /\ ~P) -> Q.
Proof.
(* WORKED IN CLASS *)
intros P Q [HP HNA]. unfold not in HNA.
apply HNA in HP. destruct HP. Qed.
Theorem double_neg : forall P : Prop,
P -> ~~P.
Proof.
(* WORKED IN CLASS *)
intros P H. unfold not. intros G. apply G. apply H. Qed.
(** **** Exercise: 2 stars, advanced (double_neg_inf)
Write an informal proof of [double_neg]:
_Theorem_: [P] implies [~~P], for any proposition [P]. *)
(* FILL IN HERE *)
(* Do not modify the following line: *)
Definition manual_grade_for_double_neg_inf : option (nat*string) := None.
(** [] *)
(** **** Exercise: 2 stars, standard, especially useful (contrapositive) *)
Theorem contrapositive : forall (P Q : Prop),
(P -> Q) -> (~Q -> ~P).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star, standard (not_both_true_and_false) *)
Theorem not_both_true_and_false : forall P : Prop,
~ (P /\ ~P).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star, advanced (informal_not_PNP)
Write an informal proof (in English) of the proposition [forall P
: Prop, ~(P /\ ~P)]. *)
(* FILL IN HERE *)
(* Do not modify the following line: *)
Definition manual_grade_for_informal_not_PNP : option (nat*string) := None.
(** [] *)
(** Since inequality involves a negation, it also requires a little
practice to be able to work with it fluently. Here is one useful
trick. If you are trying to prove a goal that is
nonsensical (e.g., the goal state is [false = true]), apply
[ex_falso_quodlibet] to change the goal to [False]. This makes it
easier to use assumptions of the form [~P] that may be available
in the context -- in particular, assumptions of the form
[x<>y]. *)
Theorem not_true_is_false : forall b : bool,
b <> true -> b = false.
Proof.
intros b H.
destruct b eqn:HE.
- (* b = true *)
unfold not in H.
apply ex_falso_quodlibet.
apply H. reflexivity.
- (* b = false *)
reflexivity.
Qed.
(** Since reasoning with [ex_falso_quodlibet] is quite common, Coq
provides a built-in tactic, [exfalso], for applying it. *)
Theorem not_true_is_false' : forall b : bool,
b <> true -> b = false.
Proof.
intros [] H. (* note implicit [destruct b] here *)
- (* b = true *)
unfold not in H.
exfalso. (* <=== *)
apply H. reflexivity.
- (* b = false *) reflexivity.
Qed.
(* ================================================================= *)
(** ** Truth *)
(** Besides [False], Coq's standard library also defines [True], a
proposition that is trivially true. To prove it, we use the
predefined constant [I : True]: *)
Lemma True_is_true : True.
Proof. apply I. Qed.
(** Unlike [False], which is used extensively, [True] is used
relatively rarely, since it is trivial (and therefore
uninteresting) to prove as a goal, and conversely it provides no
useful information as a hypothesis.
But it can be quite useful when defining complex [Prop]s using
conditionals or as a parameter to higher-order [Prop]s. We will
see examples later on. *)
(** As an example, we can demonstrate how to achieve a similar effect
as the [discriminate] tactic, without using it. *)
(** Pattern-matching lets us do different things for different
constructors. If the result of applying two different
constructors were hypothetically equal, then we could use [match]
to convert an unprovable statement (like [False]) to one that is
provable (like [True]). *)
Definition disc_fn (n: nat) : Prop :=
match n with
| O => True
| S _ => False
end.
Theorem disc : forall n, ~ (O = S n).
Proof.
intros n H1.
assert (H2 : disc_fn O). { simpl. apply I. }
rewrite H1 in H2. simpl in H2. apply H2.
Qed.
(** To generalize this to other constructors, we simply have to
provide the appropriate generalization of [disc_fn]. To generalize
it to other conclusions, we can use [exfalso] to replace them. But
the built-in [discriminate] takes care of all this for us. *)
(* ================================================================= *)
(** ** Logical Equivalence *)
(** The handy "if and only if" connective, which asserts that two
propositions have the same truth value, is simply the conjunction
of two implications. *)
Module MyIff.
Definition iff (P Q : Prop) := (P -> Q) /\ (Q -> P).
Notation "P <-> Q" := (iff P Q)
(at level 95, no associativity)
: type_scope.
End MyIff.
Theorem iff_sym : forall P Q : Prop,
(P <-> Q) -> (Q <-> P).
Proof.
(* WORKED IN CLASS *)
intros P Q [HAB HBA].
split.
- (* -> *) apply HBA.
- (* <- *) apply HAB. Qed.
Lemma not_true_iff_false : forall b,
b <> true <-> b = false.
Proof.
(* WORKED IN CLASS *)
intros b. split.
- (* -> *) apply not_true_is_false.
- (* <- *)
intros H. rewrite H. intros H'. discriminate H'.
Qed.
(** **** Exercise: 1 star, standard, optional (iff_properties)
Using the above proof that [<->] is symmetric ([iff_sym]) as
a guide, prove that it is also reflexive and transitive. *)
Theorem iff_refl : forall P : Prop,
P <-> P.
Proof.
(* FILL IN HERE *) Admitted.
Theorem iff_trans : forall P Q R : Prop,
(P <-> Q) -> (Q <-> R) -> (P <-> R).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, standard (or_distributes_over_and) *)
Theorem or_distributes_over_and : forall P Q R : Prop,
P \/ (Q /\ R) <-> (P \/ Q) /\ (P \/ R).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ================================================================= *)
(** ** Setoids and Logical Equivalence *)
(** Some of Coq's tactics treat [iff] statements specially, avoiding
the need for some low-level proof-state manipulation. In
particular, [rewrite] and [reflexivity] can be used with [iff]
statements, not just equalities. To enable this behavior, we have
to import the Coq library that supports it: *)
From Coq Require Import Setoids.Setoid.
(** A "setoid" is a set equipped with an equivalence relation,
that is, a relation that is reflexive, symmetric, and transitive.
When two elements of a set are equivalent according to the
relation, [rewrite] can be used to replace one element with the
other. We've seen that already with the equality relation [=] in
Coq: when [x = y], we can use [rewrite] to replace [x] with [y],
or vice-versa.
Similarly, the logical equivalence relation [<->] is reflexive,
symmetric, and transitive, so we can use it to replace one part of
a proposition with another: if [P <-> Q], then we can use
[rewrite] to replace [P] with [Q], or vice-versa. *)
(** Here is a simple example demonstrating how these tactics work with
[iff]. First, let's prove a couple of basic iff equivalences. *)
Lemma mul_eq_0 : forall n m, n * m = 0 <-> n = 0 \/ m = 0.
Proof.
split.
- apply mult_is_O.
- apply factor_is_O.
Qed.
Theorem or_assoc :
forall P Q R : Prop, P \/ (Q \/ R) <-> (P \/ Q) \/ R.
Proof.
intros P Q R. split.
- intros [H | [H | H]].
+ left. left. apply H.
+ left. right. apply H.
+ right. apply H.
- intros [[H | H] | H].
+ left. apply H.
+ right. left. apply H.
+ right. right. apply H.
Qed.
(** We can now use these facts with [rewrite] and [reflexivity]
to give smooth proofs of statements involving equivalences. For
example, here is a ternary version of the previous [mult_0]
result: *)
Lemma mul_eq_0_ternary :
forall n m p, n * m * p = 0 <-> n = 0 \/ m = 0 \/ p = 0.
Proof.
intros n m p.
rewrite mul_eq_0. rewrite mul_eq_0. rewrite or_assoc.
reflexivity.
Qed.
(** The [apply] tactic can also be used with [<->]. When given an
equivalence as its argument, [apply] tries to guess which
direction of the equivalence will be useful. *)
Lemma apply_iff_example :
forall n m : nat, n * m = 0 -> n = 0 \/ m = 0.
Proof.
intros n m H. apply mul_eq_0. apply H.
Qed.
(* ================================================================= *)
(** ** Existential Quantification *)
(** Another important logical connective is _existential
quantification_. To say that there is some [x] of type [T] such
that some property [P] holds of [x], we write [exists x : T,
P]. As with [forall], the type annotation [: T] can be omitted if
Coq is able to infer from the context what the type of [x] should
be. *)
(** To prove a statement of the form [exists x, P], we must show that
[P] holds for some specific choice of value for [x], known as the
_witness_ of the existential. This is done in two steps: First,
we explicitly tell Coq which witness [t] we have in mind by
invoking the tactic [exists t]. Then we prove that [P] holds after
all occurrences of [x] are replaced by [t]. *)
Definition Even x := exists n : nat, x = double n.
Lemma four_is_even : Even 4.
Proof.
unfold Even. exists 2. reflexivity.
Qed.
(** Conversely, if we have an existential hypothesis [exists x, P] in
the context, we can destruct it to obtain a witness [x] and a
hypothesis stating that [P] holds of [x]. *)
Theorem exists_example_2 : forall n,
(exists m, n = 4 + m) ->
(exists o, n = 2 + o).
Proof.
(* WORKED IN CLASS *)
intros n [m Hm]. (* note implicit [destruct] here *)
exists (2 + m).
apply Hm. Qed.
(** **** Exercise: 1 star, standard, especially useful (dist_not_exists)
Prove that "[P] holds for all [x]" implies "there is no [x] for
which [P] does not hold." (Hint: [destruct H as [x E]] works on
existential assumptions!) *)
Theorem dist_not_exists : forall (X:Type) (P : X -> Prop),
(forall x, P x) -> ~ (exists x, ~ P x).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, standard (dist_exists_or)
Prove that existential quantification distributes over
disjunction. *)
Theorem dist_exists_or : forall (X:Type) (P Q : X -> Prop),
(exists x, P x \/ Q x) <-> (exists x, P x) \/ (exists x, Q x).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ################################################################# *)
(** * Programming with Propositions *)
(** The logical connectives that we have seen provide a rich
vocabulary for defining complex propositions from simpler ones.
To illustrate, let's look at how to express the claim that an
element [x] occurs in a list [l]. Notice that this property has a
simple recursive structure:
- If [l] is the empty list, then [x] cannot occur in it, so the
property "[x] appears in [l]" is simply false.
- Otherwise, [l] has the form [x' :: l']. In this case, [x]
occurs in [l] if either it is equal to [x'] or it occurs in
[l']. *)
(** We can translate this directly into a straightforward recursive
function taking an element and a list and returning a proposition (!): *)
Fixpoint In {A : Type} (x : A) (l : list A) : Prop :=
match l with
| [] => False
| x' :: l' => x' = x \/ In x l'
end.
(** When [In] is applied to a concrete list, it expands into a
concrete sequence of nested disjunctions. *)
Example In_example_1 : In 4 [1; 2; 3; 4; 5].
Proof.
(* WORKED IN CLASS *)
simpl. right. right. right. left. reflexivity.
Qed.
Example In_example_2 :
forall n, In n [2; 4] ->
exists n', n = 2 * n'.
Proof.
(* WORKED IN CLASS *)
simpl.
intros n [H | [H | []]].
- exists 1. rewrite <- H. reflexivity.
- exists 2. rewrite <- H. reflexivity.
Qed.
(** (Notice the use of the empty pattern to discharge the last case
_en passant_.) *)
(** We can also prove more generic, higher-level lemmas about [In].
(Note how [In] starts out applied to a variable and only gets
expanded when we do case analysis on this variable.) *)
Theorem In_map :
forall (A B : Type) (f : A -> B) (l : list A) (x : A),
In x l ->
In (f x) (map f l).
Proof.
intros A B f l x.
induction l as [|x' l' IHl'].
- (* l = nil, contradiction *)
simpl. intros [].
- (* l = x' :: l' *)
simpl. intros [H | H].
+ rewrite H. left. reflexivity.
+ right. apply IHl'. apply H.
Qed.
(** This way of defining propositions recursively, though convenient
in some cases, also has some drawbacks. In particular, it is
subject to Coq's usual restrictions regarding the definition of
recursive functions, e.g., the requirement that they be "obviously
terminating." In the next chapter, we will see how to define
propositions _inductively_, a different technique with its own set
of strengths and limitations. *)
(** **** Exercise: 3 stars, standard (In_map_iff) *)
Theorem In_map_iff :
forall (A B : Type) (f : A -> B) (l : list A) (y : B),
In y (map f l) <->
exists x, f x = y /\ In x l.
Proof.
intros A B f l y. split.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, standard (In_app_iff) *)
Theorem In_app_iff : forall A l l' (a:A),
In a (l++l') <-> In a l \/ In a l'.
Proof.
intros A l. induction l as [|a' l' IH].
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, standard, especially useful (All)
Recall that functions returning propositions can be seen as
_properties_ of their arguments. For instance, if [P] has type
[nat -> Prop], then [P n] states that property [P] holds of [n].
Drawing inspiration from [In], write a recursive function [All]
stating that some property [P] holds of all elements of a list
[l]. To make sure your definition is correct, prove the [All_In]
lemma below. (Of course, your definition should _not_ just
restate the left-hand side of [All_In].) *)
Fixpoint All {T : Type} (P : T -> Prop) (l : list T) : Prop
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
Theorem All_In :
forall T (P : T -> Prop) (l : list T),
(forall x, In x l -> P x) <->
All P l.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, standard, optional (combine_odd_even)
Complete the definition of the [combine_odd_even] function below.
It takes as arguments two properties of numbers, [Podd] and
[Peven], and it should return a property [P] such that [P n] is
equivalent to [Podd n] when [n] is odd and equivalent to [Peven n]
otherwise. *)
Definition combine_odd_even (Podd Peven : nat -> Prop) : nat -> Prop
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
(** To test your definition, prove the following facts: *)
Theorem combine_odd_even_intro :
forall (Podd Peven : nat -> Prop) (n : nat),
(odd n = true -> Podd n) ->
(odd n = false -> Peven n) ->
combine_odd_even Podd Peven n.
Proof.
(* FILL IN HERE *) Admitted.
Theorem combine_odd_even_elim_odd :
forall (Podd Peven : nat -> Prop) (n : nat),
combine_odd_even Podd Peven n ->
odd n = true ->
Podd n.
Proof.
(* FILL IN HERE *) Admitted.
Theorem combine_odd_even_elim_even :
forall (Podd Peven : nat -> Prop) (n : nat),
combine_odd_even Podd Peven n ->
odd n = false ->
Peven n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ################################################################# *)
(** * Applying Theorems to Arguments *)
(** One feature that distinguishes Coq from some other popular
proof assistants (e.g., ACL2 and Isabelle) is that it treats
_proofs_ as first-class objects.
There is a great deal to be said about this, but it is not
necessary to understand it all in detail in order to use Coq.
This section gives just a taste, while a deeper exploration can be
found in the optional chapters [ProofObjects] and
[IndPrinciples]. *)
(** We have seen that we can use [Check] to ask Coq to print the type
of an expression. We can also use it to ask what theorem a
particular identifier refers to. *)
Check plus : nat -> nat -> nat.
Check add_comm : forall n m : nat, n + m = m + n.
(** Coq checks the _statement_ of the [add_comm] theorem (or prints
it for us, if we leave off the part beginning with the colon) in
the same way that it checks the _type_ of any term (e.g., plus)
that we ask it to [Check]. Why? *)
(** The reason is that the identifier [add_comm] actually refers to a
_proof object_, which represents a logical derivation establishing
of the truth of the statement [forall n m : nat, n + m = m + n]. The
type of this object is the proposition which it is a proof of. *)
(** Intuitively, this makes sense because the statement of a
theorem tells us what we can use that theorem for. *)
(** Operationally, this analogy goes even further: by applying a
theorem as if it were a function, i.e., applying it to values and
hypotheses with matching types, we can specialize its result
without having to resort to intermediate assertions. For example,
suppose we wanted to prove the following result: *)
Lemma add_comm3 :
forall x y z, x + (y + z) = (z + y) + x.
(** It appears at first sight that we ought to be able to prove this
by rewriting with [add_comm] twice to make the two sides match.
The problem, however, is that the second [rewrite] will undo the
effect of the first. *)
Proof.
(* WORKED IN CLASS *)
intros x y z.
rewrite add_comm.
rewrite add_comm.
(* We are back where we started... *)
Abort.
(** We saw similar problems back in Chapter [Induction], and saw one
way to work around them by using [assert] to derive a specialized
version of [add_comm] that can be used to rewrite exactly where
we want. *)
Lemma add_comm3_take2 :
forall x y z, x + (y + z) = (z + y) + x.
Proof.
intros x y z.
rewrite add_comm.
assert (H : y + z = z + y).
{ rewrite add_comm. reflexivity. }
rewrite H.
reflexivity.
Qed.
(** A more elegant alternative is to apply [add_comm] directly
to the arguments we want to instantiate it with, in much the same
way as we apply a polymorphic function to a type argument. *)
Lemma add_comm3_take3 :
forall x y z, x + (y + z) = (z + y) + x.
Proof.
intros x y z.
rewrite add_comm.
rewrite (add_comm y z).
reflexivity.
Qed.
(** Let's see another example of using a theorem like a function.
The following theorem says: any list [l] containing some element
must be nonempty. *)
Theorem in_not_nil :
forall A (x : A) (l : list A), In x l -> l <> [].
Proof.
intros A x l H. unfold not. intro Hl.
rewrite Hl in H.
simpl in H.
apply H.
Qed.
(** What makes this interesting is that one quantified variable
([x]) does not appear in the conclusion ([l <> []]). *)
(** We should be able to use this theorem to prove the special case
where [x] is [42]. However, naively, the tactic [apply in_not_nil]
will fail because it cannot infer the value of [x]. *)
Lemma in_not_nil_42 :
forall l : list nat, In 42 l -> l <> [].
Proof.
intros l H.
Fail apply in_not_nil.
Abort.
(** There are several ways to work around this: *)
(** Use [apply ... with ...] *)
Lemma in_not_nil_42_take2 :
forall l : list nat, In 42 l -> l <> [].
Proof.
intros l H.
apply in_not_nil with (x := 42).
apply H.
Qed.
(** Use [apply ... in ...] *)
Lemma in_not_nil_42_take3 :
forall l : list nat, In 42 l -> l <> [].
Proof.
intros l H.
apply in_not_nil in H.
apply H.
Qed.
(** Explicitly apply the lemma to the value for [x]. *)
Lemma in_not_nil_42_take4 :
forall l : list nat, In 42 l -> l <> [].
Proof.
intros l H.
apply (in_not_nil nat 42).
apply H.
Qed.
(** Explicitly apply the lemma to a hypothesis. *)
Lemma in_not_nil_42_take5 :
forall l : list nat, In 42 l -> l <> [].
Proof.
intros l H.
apply (in_not_nil _ _ _ H).
Qed.
(** You can "use theorems as functions" in this way with almost all
tactics that take a theorem name as an argument. Note also that
theorem application uses the same inference mechanisms as function
application; thus, it is possible, for example, to supply
wildcards as arguments to be inferred, or to declare some
hypotheses to a theorem as implicit by default. These features
are illustrated in the proof below. (The details of how this proof
works are not critical -- the goal here is just to illustrate what
can be done.) *)
Example lemma_application_ex :
forall {n : nat} {ns : list nat},
In n (map (fun m => m * 0) ns) ->
n = 0.
Proof.
intros n ns H.
destruct (proj1 _ _ (In_map_iff _ _ _ _ _) H)
as [m [Hm _]].
rewrite mul_0_r in Hm. rewrite <- Hm. reflexivity.
Qed.
(** We will see many more examples in later chapters. *)
(* ################################################################# *)
(** * Coq vs. Set Theory *)
(** Coq's logical core, the _Calculus of Inductive
Constructions_, differs in some important ways from other formal
systems that are used by mathematicians to write down precise and
rigorous definitions and proofs. For example, in the most popular
foundation for paper-and-pencil mathematics, Zermelo-Fraenkel Set
Theory (ZFC), a mathematical object can potentially be a member of
many different sets; a term in Coq's logic, on the other hand, is
a member of at most one type. This difference often leads to
slightly different ways of capturing informal mathematical
concepts, but these are, by and large, about equally natural and
easy to work with. For example, instead of saying that a natural
number [n] belongs to the set of even numbers, we would say in Coq
that [Even n] holds, where [Even : nat -> Prop] is a property
describing even numbers.
We conclude this chapter with a brief discussion of some of the
most significant differences between the two worlds. *)
(* ================================================================= *)
(** ** Functional Extensionality *)
(** Coq's logic is intentionally quite minimal. This means that there
are occasionally some cases where translating standard
mathematical reasoning into Coq can be cumbersome or sometimes
even impossible, unless we enrich the core logic with additional
axioms. *)
(** The equality assertions that we have seen so far mostly have
concerned elements of inductive types ([nat], [bool], etc.). But,
since Coq's equality operator is polymorphic, we can use it at
_any_ type -- in particular, we can write propositions claiming
that two _functions_ are equal to each other: *)
Example function_equality_ex1 :
(fun x => 3 + x) = (fun x => (pred 4) + x).
Proof. reflexivity. Qed.
(** In common mathematical practice, two functions [f] and [g] are
considered equal if they produce the same output on every input:
(forall x, f x = g x) -> f = g
This is known as the principle of _functional extensionality_. *)
(** Informally, an "extensional property" is one that pertains to an
object's observable behavior. Thus, functional extensionality
simply means that a function's identity is completely determined
by what we can observe from it -- i.e., the results we obtain
after applying it. *)
(** However, functional extensionality is not part of Coq's built-in
logic. This means that some apparently "obvious" propositions are
not provable. *)
Example function_equality_ex2 :
(fun x => plus x 1) = (fun x => plus 1 x).
Proof.
(* Stuck *)
Abort.
(** However, we can add functional extensionality to Coq's core using
the [Axiom] command. *)
Axiom functional_extensionality : forall {X Y: Type}
{f g : X -> Y},
(forall (x:X), f x = g x) -> f = g.
(** Defining something as an [Axiom] has the same effect as stating a
theorem and skipping its proof using [Admitted], but it alerts the
reader that this isn't just something we're going to come back and
fill in later! *)
(** We can now invoke functional extensionality in proofs: *)
Example function_equality_ex2 :
(fun x => plus x 1) = (fun x => plus 1 x).
Proof.
apply functional_extensionality. intros x.
apply add_comm.
Qed.
(** Naturally, we must be careful when adding new axioms into Coq's
logic, as this can render it _inconsistent_ -- that is, it may
become possible to prove every proposition, including [False],
[2+2=5], etc.!
Unfortunately, there is no simple way of telling whether an axiom
is safe to add: hard work by highly trained mathematicians is
often required to establish the consistency of any particular
combination of axioms.
Fortunately, it is known that adding functional extensionality, in
particular, _is_ consistent. *)
(** To check whether a particular proof relies on any additional
axioms, use the [Print Assumptions] command:
[Print Assumptions function_equality_ex2]. *)
(* ===>
Axioms:
functional_extensionality :
forall (X Y : Type) (f g : X -> Y),
(forall x : X, f x = g x) -> f = g
(You may also see [add_comm] listed as an assumption, depending
on whether the copy of [Tactics.v] in the local directory has the
proof of [add_comm] filled in.) *)
(** **** Exercise: 4 stars, standard (tr_rev_correct)
One problem with the definition of the list-reversing function
[rev] that we have is that it performs a call to [app] on each
step; running [app] takes time asymptotically linear in the size
of the list, which means that [rev] is asymptotically quadratic.
We can improve this with the following definitions: *)
Fixpoint rev_append {X} (l1 l2 : list X) : list X :=
match l1 with
| [] => l2
| x :: l1' => rev_append l1' (x :: l2)
end.
Definition tr_rev {X} (l : list X) : list X :=
rev_append l [].
(** This version of [rev] is said to be _tail-recursive_, because the
recursive call to the function is the last operation that needs to
be performed (i.e., we don't have to execute [++] after the
recursive call); a decent compiler will generate very efficient
code in this case.
Prove that the two definitions are indeed equivalent. *)
Theorem tr_rev_correct : forall X, @tr_rev X = @rev X.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ================================================================= *)
(** ** Propositions vs. Booleans
We've seen two different ways of expressing logical claims in Coq:
with _booleans_ (of type [bool]), and with _propositions_ (of type
[Prop]).
Here are the key differences between [bool] and [Prop]:
bool Prop
==== ====
decidable? yes no
useable with match? yes no
equalities rewritable? no yes
*)
(** The most essential difference between the two worlds is
_decidability_. Every Coq expression of type [bool] can be
simplified in a finite number of steps to either [true] or
[false] -- i.e., there is a terminating mechanical procedure for
deciding whether or not it is [true]. This means that, for
example, the type [nat -> bool] is inhabited only by functions
that, given a [nat], always return either [true] or [false]; and
this, in turn, means that there is no function in [nat -> bool]
that checks whether a given number is the code of a terminating
Turing machine. By contrast, the type [Prop] includes both
decidable and undecidable mathematical propositions; in
particular, the type [nat -> Prop] does contain functions
representing properties like "the nth Turing machine halts."
The second row in the table above follow directly from this
essential difference. To evaluate a pattern match (or
conditional) on a boolean, we need to know whether the scrutinee
evaluates to [true] or [false]; this only works for [bool], not
[Prop]. The third row highlights another important practical
difference: equality functions like [eqb_nat] that return a
boolean cannot be used directly to justify rewriting, whereas
the propositional [eq] can be. *)
(* ================================================================= *)
(** ** Working with Decidable Properties *)
(** Since [Prop] includes _both_ decidable and undecidable properties,
we have two choices when when we are dealing with a property that
happens to be decidable: we can express it as a boolean
computation or as a function into [Prop].
For instance, to claim that a number [n] is even, we can say
either... *)
(** ... that [even n] evaluates to [true]... *)
Example even_42_bool : even 42 = true.
Proof. reflexivity. Qed.
(** ... or that there exists some [k] such that [n = double k]. *)
Example even_42_prop : Even 42.
Proof. unfold Even. exists 21. reflexivity. Qed.
(** Of course, it would be pretty strange if these two
characterizations of evenness did not describe the same set of
natural numbers! Fortunately, we can prove that they do... *)
(** We first need two helper lemmas. *)
Lemma even_double : forall k, even (double k) = true.
Proof.
intros k. induction k as [|k' IHk'].
- reflexivity.
- simpl. apply IHk'.
Qed.
(** **** Exercise: 3 stars, standard (even_double_conv) *)
Lemma even_double_conv : forall n, exists k,
n = if even n then double k else S (double k).
Proof.
(* Hint: Use the [even_S] lemma from [Induction.v]. *)
(* FILL IN HERE *) Admitted.
(** [] *)
(** Now the main theorem: *)
Theorem even_bool_prop : forall n,
even n = true <-> Even n.
Proof.
intros n. split.
- intros H. destruct (even_double_conv n) as [k Hk].
rewrite Hk. rewrite H. exists k. reflexivity.
- intros [k Hk]. rewrite Hk. apply even_double.
Qed.
(** In view of this theorem, we say that the boolean computation
[even n] is _reflected_ in the truth of the proposition
[exists k, n = double k]. *)
(** Similarly, to state that two numbers [n] and [m] are equal, we can
say either
- (1) that [n =? m] returns [true], or
- (2) that [n = m].
Again, these two notions are equivalent. *)
Theorem eqb_eq : forall n1 n2 : nat,
n1 =? n2 = true <-> n1 = n2.
Proof.
intros n1 n2. split.
- apply eqb_true.
- intros H. rewrite H. rewrite eqb_refl. reflexivity.
Qed.
(** Even when the boolean and propositional formulations of a claim
are equivalent from a purely logical perspective, they are often
not equivalent from the point of view of convenience for some
specific purpose. *)
(** In the case of even numbers above, when proving the
backwards direction of [even_bool_prop] (i.e., [even_double],
going from the propositional to the boolean claim), we used a
simple induction on [k]. On the other hand, the converse (the
[even_double_conv] exercise) required a clever generalization,
since we can't directly prove [(even n = true) -> Even n]. *)
(** We cannot _test_ whether a [Prop] is true or not in a
function definition; as a consequence, the following code fragment
is rejected: *)
Fail
Definition is_even_prime n :=
if n = 2 then true
else false.
(** Coq complains that [n = 2] has type [Prop], while it expects
an element of [bool] (or some other inductive type with two
elements). The reason has to do with the _computational_ nature
of Coq's core language, which is designed so that every function
it can express is computable and total. One reason for this is to
allow the extraction of executable programs from Coq developments.
As a consequence, [Prop] in Coq does _not_ have a universal case
analysis operation telling whether any given proposition is true
or false, since such an operation would allow us to write
non-computable functions.
Beyond the fact that non-computable properties are impossible in
general to phrase as boolean computations, even many _computable_
properties are easier to express using [Prop] than [bool], since
recursive function definitions in Coq are subject to significant
restrictions. For instance, the next chapter shows how to define
the property that a regular expression matches a given string
using [Prop]. Doing the same with [bool] would amount to writing
a regular expression matching algorithm, which would be more
complicated, harder to understand, and harder to reason about than
a simple (non-algorithmic) definition of this property.
Conversely, an important side benefit of stating facts using
booleans is enabling some proof automation through computation
with Coq terms, a technique known as _proof by reflection_.
Consider the following statement: *)
Example even_1000 : Even 1000.
(** The most direct way to prove this is to give the value of [k]
explicitly. *)
Proof. unfold Even. exists 500. reflexivity. Qed.
(** The proof of the corresponding boolean statement is even
simpler (because we don't have to invent the witness: Coq's
computation mechanism does it for us!). *)
Example even_1000' : even 1000 = true.
Proof. reflexivity. Qed.
(** What is interesting is that, since the two notions are equivalent,
we can use the boolean formulation to prove the other one without
mentioning the value 500 explicitly: *)
Example even_1000'' : Even 1000.
Proof. apply even_bool_prop. reflexivity. Qed.
(** Although we haven't gained much in terms of proof-script
size in this case, larger proofs can often be made considerably
simpler by the use of reflection. As an extreme example, a famous
Coq proof of the even more famous _4-color theorem_ uses
reflection to reduce the analysis of hundreds of different cases
to a boolean computation. *)
(** Another notable difference is that the negation of a "boolean
fact" is straightforward to state and prove: simply flip the
expected boolean result. *)
Example not_even_1001 : even 1001 = false.
Proof.
(* WORKED IN CLASS *)
reflexivity.
Qed.
(** In contrast, propositional negation can be more difficult
to work with directly. *)
Example not_even_1001' : ~(Even 1001).
Proof.
(* WORKED IN CLASS *)
rewrite <- even_bool_prop.
unfold not.
simpl.
intro H.
discriminate H.
Qed.
(** Equality provides a complementary example, where it is sometimes
easier to work in the propositional world.
Knowing that [(n =? m) = true] is generally of little direct help in
the middle of a proof involving [n] and [m]; however, if we
convert the statement to the equivalent form [n = m], we can
rewrite with it. *)
Lemma plus_eqb_example : forall n m p : nat,
n =? m = true -> n + p =? m + p = true.
Proof.
(* WORKED IN CLASS *)
intros n m p H.
rewrite eqb_eq in H.
rewrite H.
rewrite eqb_eq.
reflexivity.
Qed.
(** We won't discuss reflection any further for the moment, but it
serves as a good example showing the complementary strengths of
booleans and general propositions, and being able to cross back
and forth between the boolean and propositional worlds will often
be convenient in later chapters. *)
(** **** Exercise: 2 stars, standard (logical_connectives)
The following theorems relate the propositional connectives studied
in this chapter to the corresponding boolean operations. *)
Theorem andb_true_iff : forall b1 b2:bool,
b1 && b2 = true <-> b1 = true /\ b2 = true.
Proof.
(* FILL IN HERE *) Admitted.
Theorem orb_true_iff : forall b1 b2,
b1 || b2 = true <-> b1 = true \/ b2 = true.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star, standard (eqb_neq)
The following theorem is an alternate "negative" formulation of
[eqb_eq] that is more convenient in certain situations. (We'll see
examples in later chapters.) Hint: [not_true_iff_false]. *)
Theorem eqb_neq : forall x y : nat,
x =? y = false <-> x <> y.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, standard (eqb_list)
Given a boolean operator [eqb] for testing equality of elements of
some type [A], we can define a function [eqb_list] for testing
equality of lists with elements in [A]. Complete the definition
of the [eqb_list] function below. To make sure that your
definition is correct, prove the lemma [eqb_list_true_iff]. *)
Fixpoint eqb_list {A : Type} (eqb : A -> A -> bool)
(l1 l2 : list A) : bool
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
Theorem eqb_list_true_iff :
forall A (eqb : A -> A -> bool),
(forall a1 a2, eqb a1 a2 = true <-> a1 = a2) ->
forall l1 l2, eqb_list eqb l1 l2 = true <-> l1 = l2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, standard, especially useful (All_forallb)
Recall the function [forallb], from the exercise
[forall_exists_challenge] in chapter [Tactics]: *)
Fixpoint forallb {X : Type} (test : X -> bool) (l : list X) : bool :=
match l with
| [] => true
| x :: l' => andb (test x) (forallb test l')
end.
(** Prove the theorem below, which relates [forallb] to the [All]
property defined above. *)
Theorem forallb_true_iff : forall X test (l : list X),
forallb test l = true <-> All (fun x => test x = true) l.
Proof.
(* FILL IN HERE *) Admitted.
(** (Ungraded thought question) Are there any important properties of
the function [forallb] which are not captured by this
specification? *)
(* FILL IN HERE
[] *)
(* ================================================================= *)
(** ** Classical vs. Constructive Logic *)
(** We have seen that it is not possible to test whether or not a
proposition [P] holds while defining a Coq function. You may be
surprised to learn that a similar restriction applies to _proofs_!
In other words, the following intuitive reasoning principle is not
derivable in Coq: *)
Definition excluded_middle := forall P : Prop,
P \/ ~ P.
(** To understand operationally why this is the case, recall
that, to prove a statement of the form [P \/ Q], we use the [left]
and [right] tactics, which effectively require knowing which side
of the disjunction holds. But the universally quantified [P] in
[excluded_middle] is an _arbitrary_ proposition, which we know
nothing about. We don't have enough information to choose which
of [left] or [right] to apply, just as Coq doesn't have enough
information to mechanically decide whether [P] holds or not inside
a function. *)
(** However, if we happen to know that [P] is reflected in some
boolean term [b], then knowing whether it holds or not is trivial:
we just have to check the value of [b]. *)
Theorem restricted_excluded_middle : forall P b,
(P <-> b = true) -> P \/ ~ P.
Proof.
intros P [] H.
- left. rewrite H. reflexivity.
- right. rewrite H. intros contra. discriminate contra.
Qed.
(** In particular, the excluded middle is valid for equations [n = m],
between natural numbers [n] and [m]. *)
Theorem restricted_excluded_middle_eq : forall (n m : nat),
n = m \/ n <> m.
Proof.
intros n m.
apply (restricted_excluded_middle (n = m) (n =? m)).
symmetry.
apply eqb_eq.
Qed.
(** It may seem strange that the general excluded middle is not
available by default in Coq, since it is a standard feature of
familiar logics like ZFC. But there is a distinct advantage in
not assuming the excluded middle: statements in Coq make stronger
claims than the analogous statements in standard mathematics.
Notably, when there is a Coq proof of [exists x, P x], it is
always possible to explicitly exhibit a value of [x] for which we
can prove [P x] -- in other words, every proof of existence is
_constructive_. *)
(** Logics like Coq's, which do not assume the excluded middle, are
referred to as _constructive logics_.
More conventional logical systems such as ZFC, in which the
excluded middle does hold for arbitrary propositions, are referred
to as _classical_. *)
(** The following example illustrates why assuming the excluded middle
may lead to non-constructive proofs:
_Claim_: There exist irrational numbers [a] and [b] such that
[a ^ b] ([a] to the power [b]) is rational.
_Proof_: It is not difficult to show that [sqrt 2] is irrational.
If [sqrt 2 ^ sqrt 2] is rational, it suffices to take [a = b =
sqrt 2] and we are done. Otherwise, [sqrt 2 ^ sqrt 2] is
irrational. In this case, we can take [a = sqrt 2 ^ sqrt 2] and
[b = sqrt 2], since [a ^ b = sqrt 2 ^ (sqrt 2 * sqrt 2) = sqrt 2 ^
2 = 2]. []
Do you see what happened here? We used the excluded middle to
consider separately the cases where [sqrt 2 ^ sqrt 2] is rational
and where it is not, without knowing which one actually holds!
Because of that, we finish the proof knowing that such [a] and [b]
exist but we cannot determine what their actual values are (at least,
not from this line of argument).
As useful as constructive logic is, it does have its limitations:
There are many statements that can easily be proven in classical
logic but that have only much more complicated constructive proofs, and
there are some that are known to have no constructive proof at
all! Fortunately, like functional extensionality, the excluded
middle is known to be compatible with Coq's logic, allowing us to
add it safely as an axiom. However, we will not need to do so
here: the results that we cover can be developed entirely
within constructive logic at negligible extra cost.
It takes some practice to understand which proof techniques must
be avoided in constructive reasoning, but arguments by
contradiction, in particular, are infamous for leading to
non-constructive proofs. Here's a typical example: suppose that
we want to show that there exists [x] with some property [P],
i.e., such that [P x]. We start by assuming that our conclusion
is false; that is, [~ exists x, P x]. From this premise, it is not
hard to derive [forall x, ~ P x]. If we manage to show that this
intermediate fact results in a contradiction, we arrive at an
existence proof without ever exhibiting a value of [x] for which
[P x] holds!
The technical flaw here, from a constructive standpoint, is that
we claimed to prove [exists x, P x] using a proof of
[~ ~ (exists x, P x)]. Allowing ourselves to remove double
negations from arbitrary statements is equivalent to assuming the
excluded middle, as shown in one of the exercises below. Thus,
this line of reasoning cannot be encoded in Coq without assuming
additional axioms. *)
(** **** Exercise: 3 stars, standard (excluded_middle_irrefutable)
Proving the consistency of Coq with the general excluded middle
axiom requires complicated reasoning that cannot be carried out
within Coq itself. However, the following theorem implies that it
is always safe to assume a decidability axiom (i.e., an instance
of excluded middle) for any _particular_ Prop [P]. Why? Because
we cannot prove the negation of such an axiom. If we could, we
would have both [~ (P \/ ~P)] and [~ ~ (P \/ ~P)] (since [P]
implies [~ ~ P], by lemma [double_neg], which we proved above),
which would be a contradiction. But since we can't, it is safe
to add [P \/ ~P] as an axiom.
Succinctly: for any proposition P,
[Coq is consistent ==> (Coq + P \/ ~P) is consistent].
(Hint: You may need to come up with a clever assertion as the
next step in the proof.) *)
Theorem excluded_middle_irrefutable: forall (P:Prop),
~ ~ (P \/ ~ P).
Proof.
unfold not. intros P H.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced (not_exists_dist)
It is a theorem of classical logic that the following two
assertions are equivalent:
~ (exists x, ~ P x)
forall x, P x
The [dist_not_exists] theorem above proves one side of this
equivalence. Interestingly, the other direction cannot be proved
in constructive logic. Your job is to show that it is implied by
the excluded middle. *)
Theorem not_exists_dist :
excluded_middle ->
forall (X:Type) (P : X -> Prop),
~ (exists x, ~ P x) -> (forall x, P x).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 5 stars, standard, optional (classical_axioms)
For those who like a challenge, here is an exercise taken from the
Coq'Art book by Bertot and Casteran (p. 123). Each of the
following four statements, together with [excluded_middle], can be
considered as characterizing classical logic. We can't prove any
of them in Coq, but we can consistently add any one of them as an
axiom if we wish to work in classical logic.
Prove that all five propositions (these four plus [excluded_middle])
are equivalent.
Hint: Rather than considering all pairs of statements pairwise,
prove a single circular chain of implications that connects them
all. *)
Definition peirce := forall P Q: Prop,
((P -> Q) -> P) -> P.
Definition double_negation_elimination := forall P:Prop,
~~P -> P.
Definition de_morgan_not_and_not := forall P Q:Prop,
~(~P /\ ~Q) -> P \/ Q.
Definition implies_to_or := forall P Q:Prop,
(P -> Q) -> (~P \/ Q).
(* FILL IN HERE
[] *)
(* 2021-08-11 15:08 *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND3B_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__AND3B_PP_BLACKBOX_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__and3b (
X ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND3B_PP_BLACKBOX_V
|
module register_io
(clk, reset, enable, addr, datain, dataout, debugbus, addr_wr, data_wr, strobe_wr,
rssi_0, rssi_1, rssi_2, rssi_3, threshhold, rssi_wait, reg_0, reg_1, reg_2, reg_3,
debug_en, misc, txmux);
input clk;
input reset;
input wire [1:0] enable;
input wire [6:0] addr;
input wire [31:0] datain;
output reg [31:0] dataout;
output wire [15:0] debugbus;
output reg [6:0] addr_wr;
output reg [31:0] data_wr;
output wire strobe_wr;
input wire [31:0] rssi_0;
input wire [31:0] rssi_1;
input wire [31:0] rssi_2;
input wire [31:0] rssi_3;
output wire [31:0] threshhold;
output wire [31:0] rssi_wait;
input wire [15:0] reg_0;
input wire [15:0] reg_1;
input wire [15:0] reg_2;
input wire [15:0] reg_3;
input wire [3:0] debug_en;
input wire [7:0] misc;
input wire [31:0] txmux;
reg strobe;
wire [31:0] out[2:1];
assign debugbus = {clk, enable, addr[2:0], datain[4:0], dataout[4:0]};
assign threshhold = out[1];
assign rssi_wait = out[2];
assign strobe_wr = strobe;
always @(*)
if (reset | ~enable[1])
begin
strobe <= 0;
dataout <= 0;
end
else
begin
if (enable[0])
begin
//read
if (addr <= 7'd52 && addr > 7'd50)
dataout <= out[addr-7'd50];
else
dataout <= 32'hFFFFFFFF;
strobe <= 0;
end
else
begin
//write
dataout <= dataout;
strobe <= 1;
data_wr <= datain;
addr_wr <= addr;
end
end
//register declarations
/*setting_reg #(50) setting_reg0(.clock(clk),.reset(reset),
.strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[0]));*/
setting_reg #(51) setting_reg1(.clock(clk),.reset(reset),
.strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[1]));
setting_reg #(52) setting_reg2(.clock(clk),.reset(reset),
.strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[2]));
/*setting_reg #(53) setting_reg3(.clock(clk),.reset(reset),
.strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[3]));
setting_reg #(54) setting_reg4(.clock(clk),.reset(reset),
.strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[4]));
setting_reg #(55) setting_reg5(.clock(clk),.reset(reset),
.strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[5]));
setting_reg #(56) setting_reg6(.clock(clk),.reset(reset),
.strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[6]));
setting_reg #(57) setting_reg7(.clock(clk),.reset(reset),
.strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[7]));*/
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A311O_BLACKBOX_V
`define SKY130_FD_SC_HS__A311O_BLACKBOX_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a311o (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A311O_BLACKBOX_V
|
/**
* Implement the FTDI Fast Opto Mode
*/
module ftdi
(
input clock,
input [7:0] read_data,
input read_clock_enable,
input reset, /* active low */
input fscts, /* fast serial clear to send */
output reg ready, /* ready to read new data */
output reg [1:0] state, /* ready to read new data */
output reg fsdi);
reg [9:0] data;
reg new_data;
//reg [1:0] state;
reg [3:0] bit_pos; /* which is the next bit we transmit */
localparam IDLE = 2'h0, WAIT_CTS = 2'h1, DATA = 2'h2;
always @(negedge clock or negedge reset) begin
if (~reset) begin
ready <= 0;
new_data <= 0;
end
else begin
if (state == IDLE) begin
if (~new_data)
if (~ready)
ready <= 1;
else if (read_clock_enable) begin
/* start bit */
data[0] <= 0;
data[8:1] <= read_data;
/* channel bit */
data[9] <= 1;
new_data <= 1;
ready <= 0;
end
end
else
new_data <= 0;
end
end
always @(negedge clock or negedge reset) begin
if (~reset) begin
state <= IDLE;
end
else begin
case (state)
IDLE: begin
fsdi <= 1;
if (new_data) begin
bit_pos <= 0;
if (fscts)
state <= DATA;
else
state <= WAIT_CTS;
end
end
WAIT_CTS: begin
if (fscts)
state <= DATA;
end
DATA: begin
fsdi <= data[bit_pos];
if (bit_pos == 9)
state <= IDLE;
else
bit_pos <= bit_pos + 1;
end
// dummy to handle
2'h3: begin
state <= IDLE;
end
endcase
end
end
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
*/
module add_compare_select (npm, d, pm1, bm1, pm2, bm2);
/**
* WARNING TO DEVELOPER(S)!!!
*
* CHECK/VERIFY THAT THE WIDTH OF ALL THE PATH METRIC BUSES
* ARE THE SAME
*
* SUCH BUSES INCLUDE npm, pm1, pm2, add1, and add2
*
* THE FOLLOWING BUSES ARE NOT INCLUDED: bm1, bm2, add_temp1,
* and add_temp2
*
* NOTE THAT THE WIDTHS OF add_temp1 AND add_temp2 ARE ONE GREATER
* THAN THOSE OF THE PATH METRIC BUSES
*/
// Output signals for the design module
/**
* New path metric - It keeps growing, so reasonable number
* of bits have to be chosen so that npm is unlikely to overflow
* Number of bits chosen = 4
*
* To handle overflows, I have decided to saturate the result
* of the computation at 2^n - 1 = 2^4 - 1 = 15
*/
output [3:0] npm;
// Decision bit from the add-compare-select unit
output d;
// Input signals for the design module
// Current path metric #1 for a set of addition
input [3:0] pm1;
// Branch metric #1 for a set of addition
input [1:0] bm1;
// Current path metric #2 for another set of addition
input [3:0] pm2;
// Branch metric #2 for another set of addition
input [1:0] bm2;
// Declare "reg" signals... that will be assigned values
reg [3:0] npm;
reg d;
/**
* Result of the additions in the first stage of the
* add-compare-select unit
*/
// Result of a set of addition
reg [3:0] add1;
// Result of another set of addition
reg [3:0] add2;
// Temporary storage for a set of addition to check for overflow
reg [4:0] add_temp1;
// Temporary storage for another set of addition to check for overflow
reg [4:0] add_temp2;
// Declare "wire" signals...
// Defining constants: parameter [name_of_constant] = value;
// Maximum value that can be stored in a 4-bit bus
parameter max_add = 4'd15;
/**
* Perform the addition stage of the add-compare-select unit
* Result of a set of addition
*/
always @ (pm1 or bm1)
begin
// Add the operands and temporary store them
add_temp1 = pm1 + bm1;
// Did the (temporary) addition cause an overflow
if(add_temp1 > max_add)
begin
/**
* Yes... An overflow has occurred.
* Saturate the addition to max_add
*/
add1 = max_add;
end
else
begin
/**
* An overflow did not occur with the addition of 2
* numbers. Hence, the result of the addition is the
* sum of the 2 numbers.
*/
add1 = pm1 + bm1;
end
end
/**
* Perform the addition stage of the add-compare-select unit
* Result of another set of addition
*/
always @ (pm2 or bm2)
begin
// Add the operands and temporary store them
add_temp2 = pm2 + bm2;
// Did the (temporary) addition cause an overflow
if(add_temp2 > max_add)
begin
/**
* Yes... An overflow has occurred.
* Saturate the addition to max_add
*/
add2 = max_add;
end
else
begin
/**
* An overflow did not occur with the addition of 2
* numbers. Hence, the result of the addition is the
* sum of the 2 numbers.
*/
add2 = pm2 + bm2;
end
end
// ========================================================
// Perform the compare stage of the add-compare-select unit
always @ (add1 or add2)
begin
if(add1 <= add2)
begin
// Select path 1 ==> d=0
d = 1'b0;
end
else
begin
// Select path 2 ==> d=1
d = 1'b1;
end
end
// ========================================================
// Perform the select stage of the add-compare-select unit
always @ (d or add1 or add2)
begin
if(d)
begin
// Select path 2... add1 < add2
npm = add2;
end
else
begin
// Select path 1... add1 >= add2
npm = add1;
end
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ui_top.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Top level of simple user interface.
`timescale 1 ps / 1 ps
module mig_7series_v1_9_ui_top #
(
parameter TCQ = 100,
parameter APP_DATA_WIDTH = 256,
parameter APP_MASK_WIDTH = 32,
parameter BANK_WIDTH = 3,
parameter COL_WIDTH = 12,
parameter CWL = 5,
parameter DATA_BUF_ADDR_WIDTH = 5,
parameter ECC = "OFF",
parameter ECC_TEST = "OFF",
parameter ORDERING = "NORM",
parameter nCK_PER_CLK = 2,
parameter RANKS = 4,
parameter REG_CTRL = "ON", // "ON" for registered DIMM
parameter RANK_WIDTH = 2,
parameter ROW_WIDTH = 16,
parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN"
)
(/*AUTOARG*/
// Outputs
wr_data_mask, wr_data, use_addr, size, row, raw_not_ecc, rank,
hi_priority, data_buf_addr, col, cmd, bank, app_wdf_rdy, app_rdy,
app_rd_data_valid, app_rd_data_end, app_rd_data,
app_ecc_multiple_err, correct_en, sr_req, app_sr_active, ref_req, app_ref_ack,
zq_req, app_zq_ack,
// Inputs
wr_data_offset, wr_data_en, wr_data_addr, rst, rd_data_offset,
rd_data_end, rd_data_en, rd_data_addr, rd_data, ecc_multiple, clk,
app_wdf_wren, app_wdf_mask, app_wdf_end, app_wdf_data, app_sz,
app_raw_not_ecc, app_hi_pri, app_en, app_cmd, app_addr, accept_ns,
accept, app_correct_en, app_sr_req, sr_active, app_ref_req, ref_ack,
app_zq_req, zq_ack
);
input accept;
localparam ADDR_WIDTH = RANK_WIDTH + BANK_WIDTH + ROW_WIDTH + COL_WIDTH;
// Add a cycle to CWL for the register in RDIMM devices
localparam CWL_M = (REG_CTRL == "ON") ? CWL + 1 : CWL;
input app_correct_en;
output wire correct_en;
assign correct_en = app_correct_en;
input app_sr_req;
output wire sr_req;
assign sr_req = app_sr_req;
input sr_active;
output wire app_sr_active;
assign app_sr_active = sr_active;
input app_ref_req;
output wire ref_req;
assign ref_req = app_ref_req;
input ref_ack;
output wire app_ref_ack;
assign app_ref_ack = ref_ack;
input app_zq_req;
output wire zq_req;
assign zq_req = app_zq_req;
input zq_ack;
output wire app_zq_ack;
assign app_zq_ack = zq_ack;
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input accept_ns; // To ui_cmd0 of ui_cmd.v
input [ADDR_WIDTH-1:0] app_addr; // To ui_cmd0 of ui_cmd.v
input [2:0] app_cmd; // To ui_cmd0 of ui_cmd.v
input app_en; // To ui_cmd0 of ui_cmd.v
input app_hi_pri; // To ui_cmd0 of ui_cmd.v
input [2*nCK_PER_CLK-1:0] app_raw_not_ecc; // To ui_wr_data0 of ui_wr_data.v
input app_sz; // To ui_cmd0 of ui_cmd.v
input [APP_DATA_WIDTH-1:0] app_wdf_data; // To ui_wr_data0 of ui_wr_data.v
input app_wdf_end; // To ui_wr_data0 of ui_wr_data.v
input [APP_MASK_WIDTH-1:0] app_wdf_mask; // To ui_wr_data0 of ui_wr_data.v
input app_wdf_wren; // To ui_wr_data0 of ui_wr_data.v
input clk; // To ui_cmd0 of ui_cmd.v, ...
input [2*nCK_PER_CLK-1:0] ecc_multiple; // To ui_rd_data0 of ui_rd_data.v
input [APP_DATA_WIDTH-1:0] rd_data; // To ui_rd_data0 of ui_rd_data.v
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr; // To ui_rd_data0 of ui_rd_data.v
input rd_data_en; // To ui_rd_data0 of ui_rd_data.v
input rd_data_end; // To ui_rd_data0 of ui_rd_data.v
input rd_data_offset; // To ui_rd_data0 of ui_rd_data.v
input rst; // To ui_cmd0 of ui_cmd.v, ...
input [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr; // To ui_wr_data0 of ui_wr_data.v
input wr_data_en; // To ui_wr_data0 of ui_wr_data.v
input wr_data_offset; // To ui_wr_data0 of ui_wr_data.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [2*nCK_PER_CLK-1:0] app_ecc_multiple_err; // From ui_rd_data0 of ui_rd_data.v
output [APP_DATA_WIDTH-1:0] app_rd_data; // From ui_rd_data0 of ui_rd_data.v
output app_rd_data_end; // From ui_rd_data0 of ui_rd_data.v
output app_rd_data_valid; // From ui_rd_data0 of ui_rd_data.v
output app_rdy; // From ui_cmd0 of ui_cmd.v
output app_wdf_rdy; // From ui_wr_data0 of ui_wr_data.v
output [BANK_WIDTH-1:0] bank; // From ui_cmd0 of ui_cmd.v
output [2:0] cmd; // From ui_cmd0 of ui_cmd.v
output [COL_WIDTH-1:0] col; // From ui_cmd0 of ui_cmd.v
output [DATA_BUF_ADDR_WIDTH-1:0]data_buf_addr;// From ui_cmd0 of ui_cmd.v
output hi_priority; // From ui_cmd0 of ui_cmd.v
output [RANK_WIDTH-1:0] rank; // From ui_cmd0 of ui_cmd.v
output [2*nCK_PER_CLK-1:0] raw_not_ecc; // From ui_wr_data0 of ui_wr_data.v
output [ROW_WIDTH-1:0] row; // From ui_cmd0 of ui_cmd.v
output size; // From ui_cmd0 of ui_cmd.v
output use_addr; // From ui_cmd0 of ui_cmd.v
output [APP_DATA_WIDTH-1:0] wr_data; // From ui_wr_data0 of ui_wr_data.v
output [APP_MASK_WIDTH-1:0] wr_data_mask; // From ui_wr_data0 of ui_wr_data.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [3:0] ram_init_addr; // From ui_rd_data0 of ui_rd_data.v
wire ram_init_done_r; // From ui_rd_data0 of ui_rd_data.v
wire rd_accepted; // From ui_cmd0 of ui_cmd.v
wire rd_buf_full; // From ui_rd_data0 of ui_rd_data.v
wire [DATA_BUF_ADDR_WIDTH-1:0]rd_data_buf_addr_r;// From ui_rd_data0 of ui_rd_data.v
wire wr_accepted; // From ui_cmd0 of ui_cmd.v
wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_buf_addr;// From ui_wr_data0 of ui_wr_data.v
wire wr_req_16; // From ui_wr_data0 of ui_wr_data.v
// End of automatics
// In the UI, the read and write buffers are allowed to be asymmetric to
// to maximize read performance, but the MC's native interface requires
// symmetry, so we zero-fill the write pointer
generate
if(DATA_BUF_ADDR_WIDTH > 4) begin
assign wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:4] = 0;
end
endgenerate
mig_7series_v1_9_ui_cmd #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.ADDR_WIDTH (ADDR_WIDTH),
.BANK_WIDTH (BANK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.RANKS (RANKS),
.MEM_ADDR_ORDER (MEM_ADDR_ORDER))
ui_cmd0
(/*AUTOINST*/
// Outputs
.app_rdy (app_rdy),
.use_addr (use_addr),
.rank (rank[RANK_WIDTH-1:0]),
.bank (bank[BANK_WIDTH-1:0]),
.row (row[ROW_WIDTH-1:0]),
.col (col[COL_WIDTH-1:0]),
.size (size),
.cmd (cmd[2:0]),
.hi_priority (hi_priority),
.rd_accepted (rd_accepted),
.wr_accepted (wr_accepted),
.data_buf_addr (data_buf_addr),
// Inputs
.rst (rst),
.clk (clk),
.accept_ns (accept_ns),
.rd_buf_full (rd_buf_full),
.wr_req_16 (wr_req_16),
.app_addr (app_addr[ADDR_WIDTH-1:0]),
.app_cmd (app_cmd[2:0]),
.app_sz (app_sz),
.app_hi_pri (app_hi_pri),
.app_en (app_en),
.wr_data_buf_addr (wr_data_buf_addr),
.rd_data_buf_addr_r (rd_data_buf_addr_r));
mig_7series_v1_9_ui_wr_data #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.APP_DATA_WIDTH (APP_DATA_WIDTH),
.APP_MASK_WIDTH (APP_MASK_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK),
.ECC (ECC),
.ECC_TEST (ECC_TEST),
.CWL (CWL_M))
ui_wr_data0
(/*AUTOINST*/
// Outputs
.app_wdf_rdy (app_wdf_rdy),
.wr_req_16 (wr_req_16),
.wr_data_buf_addr (wr_data_buf_addr[3:0]),
.wr_data (wr_data[APP_DATA_WIDTH-1:0]),
.wr_data_mask (wr_data_mask[APP_MASK_WIDTH-1:0]),
.raw_not_ecc (raw_not_ecc[2*nCK_PER_CLK-1:0]),
// Inputs
.rst (rst),
.clk (clk),
.app_wdf_data (app_wdf_data[APP_DATA_WIDTH-1:0]),
.app_wdf_mask (app_wdf_mask[APP_MASK_WIDTH-1:0]),
.app_raw_not_ecc (app_raw_not_ecc[2*nCK_PER_CLK-1:0]),
.app_wdf_wren (app_wdf_wren),
.app_wdf_end (app_wdf_end),
.wr_data_offset (wr_data_offset),
.wr_data_addr (wr_data_addr[3:0]),
.wr_data_en (wr_data_en),
.wr_accepted (wr_accepted),
.ram_init_done_r (ram_init_done_r),
.ram_init_addr (ram_init_addr));
mig_7series_v1_9_ui_rd_data #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.APP_DATA_WIDTH (APP_DATA_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK),
.ECC (ECC),
.ORDERING (ORDERING))
ui_rd_data0
(/*AUTOINST*/
// Outputs
.ram_init_done_r (ram_init_done_r),
.ram_init_addr (ram_init_addr),
.app_rd_data_valid (app_rd_data_valid),
.app_rd_data_end (app_rd_data_end),
.app_rd_data (app_rd_data[APP_DATA_WIDTH-1:0]),
.app_ecc_multiple_err (app_ecc_multiple_err[2*nCK_PER_CLK-1:0]),
.rd_buf_full (rd_buf_full),
.rd_data_buf_addr_r (rd_data_buf_addr_r),
// Inputs
.rst (rst),
.clk (clk),
.rd_data_en (rd_data_en),
.rd_data_addr (rd_data_addr),
.rd_data_offset (rd_data_offset),
.rd_data_end (rd_data_end),
.rd_data (rd_data[APP_DATA_WIDTH-1:0]),
.ecc_multiple (ecc_multiple[3:0]),
.rd_accepted (rd_accepted));
endmodule // ui_top
// Local Variables:
// verilog-library-directories:("." "../mc")
// End:
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2009 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
enum integer {
EP_State_IDLE ,
EP_State_CMDSHIFT0 ,
EP_State_CMDSHIFT13 ,
EP_State_CMDSHIFT14 ,
EP_State_CMDSHIFT15 ,
EP_State_CMDSHIFT16 ,
EP_State_DWAIT ,
EP_State_DSHIFT0 ,
EP_State_DSHIFT1 ,
EP_State_DSHIFT15 } m_state_xr, m_state2_xr;
// Beginning of automatic ASCII enum decoding
reg [79:0] m_stateAscii_xr; // Decode of m_state_xr
always @(m_state_xr) begin
case ({m_state_xr})
EP_State_IDLE: m_stateAscii_xr = "idle ";
EP_State_CMDSHIFT0: m_stateAscii_xr = "cmdshift0 ";
EP_State_CMDSHIFT13: m_stateAscii_xr = "cmdshift13";
EP_State_CMDSHIFT14: m_stateAscii_xr = "cmdshift14";
EP_State_CMDSHIFT15: m_stateAscii_xr = "cmdshift15";
EP_State_CMDSHIFT16: m_stateAscii_xr = "cmdshift16";
EP_State_DWAIT: m_stateAscii_xr = "dwait ";
EP_State_DSHIFT0: m_stateAscii_xr = "dshift0 ";
EP_State_DSHIFT1: m_stateAscii_xr = "dshift1 ";
EP_State_DSHIFT15: m_stateAscii_xr = "dshift15 ";
default: m_stateAscii_xr = "%Error ";
endcase
end
// End of automatics
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
//$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b);
if (cyc==1) begin
m_state_xr <= EP_State_IDLE;
m_state2_xr <= EP_State_IDLE;
end
if (cyc==2) begin
if (m_stateAscii_xr != "idle ") $stop;
m_state_xr <= EP_State_CMDSHIFT13;
if (m_state2_xr != EP_State_IDLE) $stop;
m_state2_xr <= EP_State_CMDSHIFT13;
end
if (cyc==3) begin
if (m_stateAscii_xr != "cmdshift13") $stop;
m_state_xr <= EP_State_CMDSHIFT16;
if (m_state2_xr != EP_State_CMDSHIFT13) $stop;
m_state2_xr <= EP_State_CMDSHIFT16;
end
if (cyc==4) begin
if (m_stateAscii_xr != "cmdshift16") $stop;
m_state_xr <= EP_State_DWAIT;
if (m_state2_xr != EP_State_CMDSHIFT16) $stop;
m_state2_xr <= EP_State_DWAIT;
end
if (cyc==9) begin
if (m_stateAscii_xr != "dwait ") $stop;
if (m_state2_xr != EP_State_DWAIT) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module feedforward_dexp_64ns_64ns_64_18_full_dsp
#(parameter
ID = 4,
NUM_STAGE = 18,
din0_WIDTH = 64,
din1_WIDTH = 64,
dout_WIDTH = 64
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [63:0] a_tdata;
wire r_tvalid;
wire [63:0] r_tdata;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
feedforward_ap_dexp_16_full_dsp_64 feedforward_ap_dexp_16_full_dsp_64_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din1_buf1==='bx ? 'b0 : din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din1_buf1 <= din1;
end
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PCIeGen2x8If128_core_top.v
// Version : 3.2
//
// Description: 7-series solution wrapper : Endpoint for PCI Express
//
//
//
//--------------------------------------------------------------------------------
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "PCIeGen2x8If128,pcie_7x_v3_2_1,{LINK_CAP_MAX_LINK_SPEED=2,LINK_CAP_MAX_LINK_WIDTH=8,PCIE_CAP_DEVICE_PORT_TYPE=0000,DEV_CAP_MAX_PAYLOAD_SUPPORTED=1,USER_CLK_FREQ=4,REF_CLK_FREQ=0,MSI_CAP_ON=TRUE,MSI_CAP_MULTIMSGCAP=0,MSI_CAP_MULTIMSG_EXTENSION=0,MSIX_CAP_ON=FALSE,TL_TX_RAM_RADDR_LATENCY=0,TL_TX_RAM_RDATA_LATENCY=2,TL_RX_RAM_RADDR_LATENCY=0,TL_RX_RAM_RDATA_LATENCY=2,TL_RX_RAM_WRITE_LATENCY=0,VC0_TX_LASTPACKET=28,VC0_RX_RAM_LIMIT=3FF,VC0_TOTAL_CREDITS_PH=4,VC0_TOTAL_CREDITS_PD=32,VC0_TOTAL_CREDITS_NPH=4,VC0_TOTAL_CREDITS_NPD=8,VC0_TOTAL_CREDITS_CH=72,VC0_TOTAL_CREDITS_CD=370,VC0_CPL_INFINITE=TRUE,DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT=0,DEV_CAP_EXT_TAG_SUPPORTED=TRUE,LINK_STATUS_SLOT_CLOCK_CONFIG=TRUE,DISABLE_LANE_REVERSAL=TRUE,DISABLE_SCRAMBLING=FALSE,DSN_CAP_ON=TRUE,REVISION_ID=00,VC_CAP_ON=FALSE}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module PCIeGen2x8If128_core_top # (
parameter CFG_VEND_ID = 16'h10EE,
parameter CFG_DEV_ID = 16'h7028,
parameter CFG_REV_ID = 8'h00,
parameter CFG_SUBSYS_VEND_ID = 16'h10EE,
parameter CFG_SUBSYS_ID = 16'h0007,
parameter EXT_PIPE_SIM = "FALSE",
parameter ALLOW_X8_GEN2 = "TRUE",
parameter PIPE_PIPELINE_STAGES = 1,
parameter [11:0] AER_BASE_PTR = 12'h000,
parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE",
parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE",
parameter AER_CAP_MULTIHEADER = "FALSE",
parameter [11:0] AER_CAP_NEXTPTR = 12'h000,
parameter [23:0] AER_CAP_OPTIONAL_ERR_SUPPORT = 24'h000000,
parameter AER_CAP_ON = "FALSE",
parameter AER_CAP_PERMIT_ROOTERR_UPDATE = "FALSE",
parameter [31:0] BAR0 = 32'hFFFFFC00,
parameter [31:0] BAR1 = 32'h00000000,
parameter [31:0] BAR2 = 32'h00000000,
parameter [31:0] BAR3 = 32'h00000000,
parameter [31:0] BAR4 = 32'h00000000,
parameter [31:0] BAR5 = 32'h00000000,
parameter C_DATA_WIDTH = 128,
parameter [31:0] CARDBUS_CIS_POINTER = 32'h00000000,
parameter [23:0] CLASS_CODE = 24'h058000,
parameter CMD_INTX_IMPLEMENTED = "FALSE",
parameter CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE",
parameter [3:0] CPL_TIMEOUT_RANGES_SUPPORTED = 4'h2,
parameter integer DEV_CAP_ENDPOINT_L0S_LATENCY = 0,
parameter integer DEV_CAP_ENDPOINT_L1_LATENCY = 7,
parameter DEV_CAP_EXT_TAG_SUPPORTED = "TRUE",
parameter integer DEV_CAP_MAX_PAYLOAD_SUPPORTED = 1,
parameter integer DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0,
parameter DEV_CAP2_ARI_FORWARDING_SUPPORTED = "FALSE",
parameter DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED = "FALSE",
parameter DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED = "FALSE",
parameter DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED = "FALSE",
parameter DEV_CAP2_CAS128_COMPLETER_SUPPORTED = "FALSE",
parameter [1:0] DEV_CAP2_TPH_COMPLETER_SUPPORTED = 2'b00,
parameter DEV_CONTROL_EXT_TAG_DEFAULT = "FALSE",
parameter DISABLE_LANE_REVERSAL = "TRUE",
parameter DISABLE_RX_POISONED_RESP = "FALSE",
parameter DISABLE_SCRAMBLING = "FALSE",
parameter [11:0] DSN_BASE_PTR = 12'h100,
parameter [11:0] DSN_CAP_NEXTPTR = 12'h000,
parameter DSN_CAP_ON = "TRUE",
parameter [10:0] ENABLE_MSG_ROUTE = 11'b00000000000,
parameter ENABLE_RX_TD_ECRC_TRIM = "FALSE",
parameter [31:0] EXPANSION_ROM = 32'h00000000,
parameter [5:0] EXT_CFG_CAP_PTR = 6'h3F,
parameter [9:0] EXT_CFG_XP_CAP_PTR = 10'h3FF,
parameter [7:0] HEADER_TYPE = 8'h00,
parameter [7:0] INTERRUPT_PIN = 8'h0,
parameter [9:0] LAST_CONFIG_DWORD = 10'h3FF,
parameter LINK_CAP_ASPM_OPTIONALITY = "FALSE",
parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE",
parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE",
parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h2,
parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h8,
parameter LINK_CTRL2_DEEMPHASIS = "FALSE",
parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE",
parameter [3:0] LINK_CTRL2_TARGET_LINK_SPEED = 4'h2,
parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE",
parameter [14:0] LL_ACK_TIMEOUT = 15'h0000,
parameter LL_ACK_TIMEOUT_EN = "FALSE",
parameter integer LL_ACK_TIMEOUT_FUNC = 0,
parameter [14:0] LL_REPLAY_TIMEOUT = 15'h0000,
parameter LL_REPLAY_TIMEOUT_EN = "FALSE",
parameter integer LL_REPLAY_TIMEOUT_FUNC = 1,
parameter [5:0] LTSSM_MAX_LINK_WIDTH = 6'h8,
parameter MSI_CAP_MULTIMSGCAP = 0,
parameter MSI_CAP_MULTIMSG_EXTENSION = 0,
parameter MSI_CAP_ON = "TRUE",
parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "FALSE",
parameter MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE",
parameter MSIX_CAP_ON = "FALSE",
parameter MSIX_CAP_PBA_BIR = 0,
parameter [28:0] MSIX_CAP_PBA_OFFSET = 29'h0,
parameter MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] MSIX_CAP_TABLE_OFFSET = 29'h0,
parameter [10:0] MSIX_CAP_TABLE_SIZE = 11'h000,
parameter [3:0] PCIE_CAP_DEVICE_PORT_TYPE = 4'h0,
parameter [7:0] PCIE_CAP_NEXTPTR = 8'h00,
parameter PM_CAP_DSI = "FALSE",
parameter PM_CAP_D1SUPPORT = "FALSE",
parameter PM_CAP_D2SUPPORT = "FALSE",
parameter [7:0] PM_CAP_NEXTPTR = 8'h48,
parameter [4:0] PM_CAP_PMESUPPORT = 5'h0F,
parameter PM_CSR_NOSOFTRST = "TRUE",
parameter [1:0] PM_DATA_SCALE0 = 2'h0,
parameter [1:0] PM_DATA_SCALE1 = 2'h0,
parameter [1:0] PM_DATA_SCALE2 = 2'h0,
parameter [1:0] PM_DATA_SCALE3 = 2'h0,
parameter [1:0] PM_DATA_SCALE4 = 2'h0,
parameter [1:0] PM_DATA_SCALE5 = 2'h0,
parameter [1:0] PM_DATA_SCALE6 = 2'h0,
parameter [1:0] PM_DATA_SCALE7 = 2'h0,
parameter [7:0] PM_DATA0 = 8'h00,
parameter [7:0] PM_DATA1 = 8'h00,
parameter [7:0] PM_DATA2 = 8'h00,
parameter [7:0] PM_DATA3 = 8'h00,
parameter [7:0] PM_DATA4 = 8'h00,
parameter [7:0] PM_DATA5 = 8'h00,
parameter [7:0] PM_DATA6 = 8'h00,
parameter [7:0] PM_DATA7 = 8'h00,
parameter [11:0] RBAR_BASE_PTR = 12'h000,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR0 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR1 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR2 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR3 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR4 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR5 = 5'h00,
parameter [2:0] RBAR_CAP_INDEX0 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX1 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX2 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX3 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX4 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX5 = 3'h0,
parameter RBAR_CAP_ON = "FALSE",
parameter [31:0] RBAR_CAP_SUP0 = 32'h00001,
parameter [31:0] RBAR_CAP_SUP1 = 32'h00001,
parameter [31:0] RBAR_CAP_SUP2 = 32'h00001,
parameter [31:0] RBAR_CAP_SUP3 = 32'h00001,
parameter [31:0] RBAR_CAP_SUP4 = 32'h00001,
parameter [31:0] RBAR_CAP_SUP5 = 32'h00001,
parameter [2:0] RBAR_NUM = 3'h0,
parameter RECRC_CHK = 0,
parameter RECRC_CHK_TRIM = "FALSE",
parameter REF_CLK_FREQ = 0, // 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1,
parameter KEEP_WIDTH = C_DATA_WIDTH / 8,
parameter TL_RX_RAM_RADDR_LATENCY = 0,
parameter TL_RX_RAM_WRITE_LATENCY = 0,
parameter TL_TX_RAM_RADDR_LATENCY = 0,
parameter TL_TX_RAM_WRITE_LATENCY = 0,
parameter TL_RX_RAM_RDATA_LATENCY = 2,
parameter TL_TX_RAM_RDATA_LATENCY = 2,
parameter TRN_NP_FC = "TRUE",
parameter TRN_DW = "TRUE",
parameter UPCONFIG_CAPABLE = "TRUE",
parameter UPSTREAM_FACING = "TRUE",
parameter UR_ATOMIC = "FALSE",
parameter UR_INV_REQ = "TRUE",
parameter UR_PRS_RESPONSE = "TRUE",
parameter USER_CLK_FREQ = 4,
parameter USER_CLK2_DIV2 = "TRUE",
parameter [11:0] VC_BASE_PTR = 12'h000,
parameter [11:0] VC_CAP_NEXTPTR = 12'h000,
parameter VC_CAP_ON = "FALSE",
parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE",
parameter VC0_CPL_INFINITE = "TRUE",
parameter [12:0] VC0_RX_RAM_LIMIT = 13'h3FF,
parameter VC0_TOTAL_CREDITS_CD = 370,
parameter VC0_TOTAL_CREDITS_CH = 72,
parameter VC0_TOTAL_CREDITS_NPH = 4,
parameter VC0_TOTAL_CREDITS_NPD = 8,
parameter VC0_TOTAL_CREDITS_PD = 32,
parameter VC0_TOTAL_CREDITS_PH = 4,
parameter VC0_TX_LASTPACKET = 28,
parameter [11:0] VSEC_BASE_PTR = 12'h000,
parameter [11:0] VSEC_CAP_NEXTPTR = 12'h000,
parameter VSEC_CAP_ON = "FALSE",
parameter DISABLE_ASPM_L1_TIMER = "FALSE",
parameter DISABLE_BAR_FILTERING = "FALSE",
parameter DISABLE_ID_CHECK = "FALSE",
parameter DISABLE_RX_TC_FILTER = "FALSE",
parameter [7:0] DNSTREAM_LINK_NUM = 8'h00,
parameter [15:0] DSN_CAP_ID = 16'h0003,
parameter [3:0] DSN_CAP_VERSION = 4'h1,
parameter ENTER_RVRY_EI_L0 = "TRUE",
parameter [4:0] INFER_EI = 5'h00,
parameter IS_SWITCH = "FALSE",
parameter LINK_CAP_ASPM_SUPPORT = 1,
parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE",
parameter LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7,
parameter LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7,
parameter LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7,
parameter LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7,
parameter LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7,
parameter LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7,
parameter LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7,
parameter LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7,
parameter LINK_CAP_RSVD_23 = 0,
parameter LINK_CONTROL_RCB = 0,
parameter [7:0] MSI_BASE_PTR = 8'h48,
parameter [7:0] MSI_CAP_ID = 8'h05,
parameter [7:0] MSI_CAP_NEXTPTR = 8'h60,
parameter [7:0] MSIX_BASE_PTR = 8'h9C,
parameter [7:0] MSIX_CAP_ID = 8'h11,
parameter [7:0] MSIX_CAP_NEXTPTR =8'h00,
parameter N_FTS_COMCLK_GEN1 = 255,
parameter N_FTS_COMCLK_GEN2 = 255,
parameter N_FTS_GEN1 = 255,
parameter N_FTS_GEN2 = 255,
parameter [7:0] PCIE_BASE_PTR = 8'h60,
parameter [7:0] PCIE_CAP_CAPABILITY_ID = 8'h10,
parameter [3:0] PCIE_CAP_CAPABILITY_VERSION = 4'h2,
parameter PCIE_CAP_ON = "TRUE",
parameter PCIE_CAP_RSVD_15_14 = 0,
parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE",
parameter PCIE_REVISION = 2,
parameter PL_AUTO_CONFIG = 0,
parameter PL_FAST_TRAIN = "FALSE",
parameter PCIE_EXT_CLK = "FALSE",
parameter PCIE_EXT_GT_COMMON = "FALSE",
parameter EXT_CH_GT_DRP = "FALSE",
parameter TRANSCEIVER_CTRL_STATUS_PORTS = "FALSE",
parameter SHARED_LOGIC_IN_CORE = "FALSE",
parameter [7:0] PM_BASE_PTR = 8'h40,
parameter PM_CAP_AUXCURRENT = 0,
parameter [7:0] PM_CAP_ID = 8'h01,
parameter PM_CAP_ON = "TRUE",
parameter PM_CAP_PME_CLOCK = "FALSE",
parameter PM_CAP_RSVD_04 = 0,
parameter PM_CAP_VERSION = 3,
parameter PM_CSR_BPCCEN = "FALSE",
parameter PM_CSR_B2B3 = "FALSE",
parameter ROOT_CAP_CRS_SW_VISIBILITY = "FALSE",
parameter SELECT_DLL_IF = "FALSE",
parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE",
parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE",
parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE",
parameter SLOT_CAP_HOTPLUG_CAPABLE = "FALSE",
parameter SLOT_CAP_HOTPLUG_SURPRISE = "FALSE",
parameter SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE",
parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE",
parameter [12:0] SLOT_CAP_PHYSICAL_SLOT_NUM = 13'h0000,
parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE",
parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE",
parameter SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0,
parameter [7:0] SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'h00,
parameter integer SPARE_BIT0 = 0,
parameter integer SPARE_BIT1 = 0,
parameter integer SPARE_BIT2 = 0,
parameter integer SPARE_BIT3 = 0,
parameter integer SPARE_BIT4 = 0,
parameter integer SPARE_BIT5 = 0,
parameter integer SPARE_BIT6 = 0,
parameter integer SPARE_BIT7 = 0,
parameter integer SPARE_BIT8 = 0,
parameter [7:0] SPARE_BYTE0 = 8'h00,
parameter [7:0] SPARE_BYTE1 = 8'h00,
parameter [7:0] SPARE_BYTE2 = 8'h00,
parameter [7:0] SPARE_BYTE3 = 8'h00,
parameter [31:0] SPARE_WORD0 = 32'h00000000,
parameter [31:0] SPARE_WORD1 = 32'h00000000,
parameter [31:0] SPARE_WORD2 = 32'h00000000,
parameter [31:0] SPARE_WORD3 = 32'h00000000,
parameter TL_RBYPASS = "FALSE",
parameter TL_TFC_DISABLE = "FALSE",
parameter TL_TX_CHECKS_DISABLE = "FALSE",
parameter EXIT_LOOPBACK_ON_EI = "TRUE",
parameter CFG_ECRC_ERR_CPLSTAT = 0,
parameter [7:0] CAPABILITIES_PTR = 8'h40,
parameter [6:0] CRM_MODULE_RSTS = 7'h00,
parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "TRUE",
parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "TRUE",
parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE",
parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE",
parameter DEV_CAP_RSVD_14_12 = 0,
parameter DEV_CAP_RSVD_17_16 = 0,
parameter DEV_CAP_RSVD_31_29 = 0,
parameter DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE",
parameter [15:0] VC_CAP_ID = 16'h0002,
parameter [3:0] VC_CAP_VERSION = 4'h1,
parameter [15:0] VSEC_CAP_HDR_ID = 16'h1234,
parameter [11:0] VSEC_CAP_HDR_LENGTH = 12'h018,
parameter [3:0] VSEC_CAP_HDR_REVISION = 4'h1,
parameter [15:0] VSEC_CAP_ID = 16'h000B,
parameter VSEC_CAP_IS_LINK_VISIBLE = "TRUE",
parameter [3:0] VSEC_CAP_VERSION = 4'h1,
parameter DISABLE_ERR_MSG = "FALSE",
parameter DISABLE_LOCKED_FILTER = "FALSE",
parameter DISABLE_PPM_FILTER = "FALSE",
parameter ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED = "FALSE",
parameter INTERRUPT_STAT_AUTO = "TRUE",
parameter MPS_FORCE = "FALSE",
parameter [14:0] PM_ASPML0S_TIMEOUT = 15'h0000,
parameter PM_ASPML0S_TIMEOUT_EN = "FALSE",
parameter PM_ASPML0S_TIMEOUT_FUNC = 0,
parameter PM_ASPM_FASTEXIT = "FALSE",
parameter PM_MF = "FALSE",
parameter [1:0] RP_AUTO_SPD = 2'h1,
parameter [4:0] RP_AUTO_SPD_LOOPCNT = 5'h1f,
parameter SIM_VERSION = "1.0",
parameter SSL_MESSAGE_AUTO = "FALSE",
parameter TECRC_EP_INV = "FALSE",
parameter UR_CFG1 = "TRUE",
parameter USE_RID_PINS = "FALSE",
// New Parameters
parameter DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED = "FALSE",
parameter DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED = "FALSE",
parameter DEV_CAP2_LTR_MECHANISM_SUPPORTED = "FALSE",
parameter [1:0] DEV_CAP2_MAX_ENDEND_TLP_PREFIXES = 2'h0,
parameter DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING = "FALSE",
parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE",
parameter [15:0] AER_CAP_ID = 16'h0001,
parameter [3:0] AER_CAP_VERSION = 4'h1,
parameter [15:0] RBAR_CAP_ID = 16'h0015,
parameter [11:0] RBAR_CAP_NEXTPTR = 12'h000,
parameter [3:0] RBAR_CAP_VERSION = 4'h1,
parameter PCIE_USE_MODE = "3.0",
parameter PCIE_GT_DEVICE = "GTX",
parameter PCIE_CHAN_BOND = 0,
parameter PCIE_PLL_SEL = "CPLL",
parameter PCIE_ASYNC_EN = "FALSE",
parameter PCIE_TXBUF_EN = "FALSE",
parameter PL_INTERFACE = "FALSE",
parameter CFG_MGMT_IF = "FALSE",
parameter CFG_CTL_IF = "TRUE",
parameter CFG_STATUS_IF = "TRUE",
parameter RCV_MSG_IF = "FALSE",
parameter CFG_FC_IF = "TRUE",
parameter EXT_PIPE_INTERFACE = "FALSE",
parameter TX_MARGIN_FULL_0 = 7'b1001111,
parameter TX_MARGIN_FULL_1 = 7'b1001110,
parameter TX_MARGIN_FULL_2 = 7'b1001101,
parameter TX_MARGIN_FULL_3 = 7'b1001100,
parameter TX_MARGIN_FULL_4 = 7'b1000011,
parameter TX_MARGIN_LOW_0 = 7'b1000101,
parameter TX_MARGIN_LOW_1 = 7'b1000110,
parameter TX_MARGIN_LOW_2 = 7'b1000011,
parameter TX_MARGIN_LOW_3 = 7'b1000010,
parameter TX_MARGIN_LOW_4 = 7'b1000000
)
(
//----------------------------------------------------------------------------------------------------------------//
// 1. PCI Express (pci_exp) Interface //
//----------------------------------------------------------------------------------------------------------------//
// Tx
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_txn,
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_txp,
// Rx
input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_rxn,
input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_rxp,
//----------------------------------------------------------------------------------------------------------------//
// 2. Clock & GT COMMON Sharing Interface //
//----------------------------------------------------------------------------------------------------------------//
// Shared Logic Internal
output int_pclk_out_slave,
output int_pipe_rxusrclk_out,
output [(LINK_CAP_MAX_LINK_WIDTH-1):0] int_rxoutclk_out,
output int_dclk_out,
output int_userclk1_out,
output int_userclk2_out,
output int_oobclk_out,
output int_mmcm_lock_out,
output [1:0] int_qplllock_out,
output [1:0] int_qplloutclk_out,
output [1:0] int_qplloutrefclk_out,
input [(LINK_CAP_MAX_LINK_WIDTH-1):0] int_pclk_sel_slave,
// Shared Logic External - Clocks
input pipe_pclk_in,
input pipe_rxusrclk_in,
input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pipe_rxoutclk_in,
input pipe_dclk_in,
input pipe_userclk1_in,
input pipe_userclk2_in,
input pipe_oobclk_in,
input pipe_mmcm_lock_in,
output pipe_txoutclk_out,
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pipe_rxoutclk_out,
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pipe_pclk_sel_out,
output pipe_gen3_out,
// Shared Logic External - GT COMMON
input [11:0] qpll_drp_crscode,
input [17:0] qpll_drp_fsm,
input [1:0] qpll_drp_done,
input [1:0] qpll_drp_reset,
input [1:0] qpll_qplllock,
input [1:0] qpll_qplloutclk,
input [1:0] qpll_qplloutrefclk,
output qpll_qplld,
output [1:0] qpll_qpllreset,
output qpll_drp_clk,
output qpll_drp_rst_n,
output qpll_drp_ovrd,
output qpll_drp_gen3,
output qpll_drp_start,
//----------------------------------------------------------------------------------------------------------------//
// 3. AXI-S Interface //
//----------------------------------------------------------------------------------------------------------------//
// Common
output user_clk_out,
output reg user_reset_out,
output user_lnk_up,
output wire user_app_rdy,
// AXI TX
//-----------
output [5:0] tx_buf_av,
output tx_err_drop,
output tx_cfg_req,
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata,
input s_axis_tx_tvalid,
output s_axis_tx_tready,
input [KEEP_WIDTH-1:0] s_axis_tx_tkeep,
input s_axis_tx_tlast,
input [3:0] s_axis_tx_tuser,
input tx_cfg_gnt,
// AXI RX
//-----------
output [C_DATA_WIDTH-1:0] m_axis_rx_tdata,
output m_axis_rx_tvalid,
input m_axis_rx_tready,
output [KEEP_WIDTH-1:0] m_axis_rx_tkeep,
output m_axis_rx_tlast,
output [21:0] m_axis_rx_tuser,
input rx_np_ok,
input rx_np_req,
// Flow Control
output [11:0] fc_cpld,
output [7:0] fc_cplh,
output [11:0] fc_npd,
output [7:0] fc_nph,
output [11:0] fc_pd,
output [7:0] fc_ph,
input [2:0] fc_sel,
//----------------------------------------------------------------------------------------------------------------//
// 4. Configuration (CFG) Interface //
//----------------------------------------------------------------------------------------------------------------//
//------------------------------------------------//
// EP and RP //
//------------------------------------------------//
output wire [31:0] cfg_mgmt_do,
output wire cfg_mgmt_rd_wr_done,
output wire [15:0] cfg_status,
output wire [15:0] cfg_command,
output wire [15:0] cfg_dstatus,
output wire [15:0] cfg_dcommand,
output wire [15:0] cfg_lstatus,
output wire [15:0] cfg_lcommand,
output wire [15:0] cfg_dcommand2,
output [2:0] cfg_pcie_link_state,
output wire cfg_pmcsr_pme_en,
output wire [1:0] cfg_pmcsr_powerstate,
output wire cfg_pmcsr_pme_status,
output wire cfg_received_func_lvl_rst,
// Management Interface
input wire [31:0] cfg_mgmt_di,
input wire [3:0] cfg_mgmt_byte_en,
input wire [9:0] cfg_mgmt_dwaddr,
input wire cfg_mgmt_wr_en,
input wire cfg_mgmt_rd_en,
input wire cfg_mgmt_wr_readonly,
// Error Reporting Interface
input wire cfg_err_ecrc,
input wire cfg_err_ur,
input wire cfg_err_cpl_timeout,
input wire cfg_err_cpl_unexpect,
input wire cfg_err_cpl_abort,
input wire cfg_err_posted,
input wire cfg_err_cor,
input wire cfg_err_atomic_egress_blocked,
input wire cfg_err_internal_cor,
input wire cfg_err_malformed,
input wire cfg_err_mc_blocked,
input wire cfg_err_poisoned,
input wire cfg_err_norecovery,
input wire [47:0] cfg_err_tlp_cpl_header,
output wire cfg_err_cpl_rdy,
input wire cfg_err_locked,
input wire cfg_err_acs,
input wire cfg_err_internal_uncor,
input wire cfg_trn_pending,
input wire cfg_pm_halt_aspm_l0s,
input wire cfg_pm_halt_aspm_l1,
input wire cfg_pm_force_state_en,
input wire [1:0] cfg_pm_force_state,
input wire [63:0] cfg_dsn,
output cfg_msg_received,
output [15:0] cfg_msg_data,
//------------------------------------------------//
// EP Only //
//------------------------------------------------//
// Interrupt Interface Signals
input wire cfg_interrupt,
output wire cfg_interrupt_rdy,
input wire cfg_interrupt_assert,
input wire [7:0] cfg_interrupt_di,
output wire [7:0] cfg_interrupt_do,
output wire [2:0] cfg_interrupt_mmenable,
output wire cfg_interrupt_msienable,
output wire cfg_interrupt_msixenable,
output wire cfg_interrupt_msixfm,
input wire cfg_interrupt_stat,
input wire [4:0] cfg_pciecap_interrupt_msgnum,
output cfg_to_turnoff,
input wire cfg_turnoff_ok,
output wire [7:0] cfg_bus_number,
output wire [4:0] cfg_device_number,
output wire [2:0] cfg_function_number,
input wire cfg_pm_wake,
output wire cfg_msg_received_pm_as_nak,
output wire cfg_msg_received_setslotpowerlimit,
//------------------------------------------------//
// RP Only //
//------------------------------------------------//
input wire cfg_pm_send_pme_to,
input wire [7:0] cfg_ds_bus_number,
input wire [4:0] cfg_ds_device_number,
input wire [2:0] cfg_ds_function_number,
input wire cfg_mgmt_wr_rw1c_as_rw,
output wire cfg_bridge_serr_en,
output wire cfg_slot_control_electromech_il_ctl_pulse,
output wire cfg_root_control_syserr_corr_err_en,
output wire cfg_root_control_syserr_non_fatal_err_en,
output wire cfg_root_control_syserr_fatal_err_en,
output wire cfg_root_control_pme_int_en,
output wire cfg_aer_rooterr_corr_err_reporting_en,
output wire cfg_aer_rooterr_non_fatal_err_reporting_en,
output wire cfg_aer_rooterr_fatal_err_reporting_en,
output wire cfg_aer_rooterr_corr_err_received,
output wire cfg_aer_rooterr_non_fatal_err_received,
output wire cfg_aer_rooterr_fatal_err_received,
output wire cfg_msg_received_err_cor,
output wire cfg_msg_received_err_non_fatal,
output wire cfg_msg_received_err_fatal,
output wire cfg_msg_received_pm_pme,
output wire cfg_msg_received_pme_to_ack,
output wire cfg_msg_received_assert_int_a,
output wire cfg_msg_received_assert_int_b,
output wire cfg_msg_received_assert_int_c,
output wire cfg_msg_received_assert_int_d,
output wire cfg_msg_received_deassert_int_a,
output wire cfg_msg_received_deassert_int_b,
output wire cfg_msg_received_deassert_int_c,
output wire cfg_msg_received_deassert_int_d,
//----------------------------------------------------------------------------------------------------------------//
// 5. Physical Layer Control and Status (PL) Interface //
//----------------------------------------------------------------------------------------------------------------//
//------------------------------------------------//
// EP and RP //
//------------------------------------------------//
input wire [1:0] pl_directed_link_change,
input wire [1:0] pl_directed_link_width,
input wire pl_directed_link_speed,
input wire pl_directed_link_auton,
input wire pl_upstream_prefer_deemph,
output wire pl_sel_lnk_rate,
output wire [1:0] pl_sel_lnk_width,
output wire [5:0] pl_ltssm_state,
output wire [1:0] pl_lane_reversal_mode,
output wire pl_phy_lnk_up,
output wire [2:0] pl_tx_pm_state,
output wire [1:0] pl_rx_pm_state,
output wire pl_link_upcfg_cap,
output wire pl_link_gen2_cap,
output wire pl_link_partner_gen2_supported,
output wire [2:0] pl_initial_link_width,
output wire pl_directed_change_done,
//------------------------------------------------//
// EP Only //
//------------------------------------------------//
output wire pl_received_hot_rst,
//------------------------------------------------//
// RP Only //
//------------------------------------------------//
input wire pl_transmit_hot_rst,
input wire pl_downstream_deemph_source,
//----------------------------------------------------------------------------------------------------------------//
// 6. AER interface //
//----------------------------------------------------------------------------------------------------------------//
input wire [127:0] cfg_err_aer_headerlog,
input wire [4:0] cfg_aer_interrupt_msgnum,
output wire cfg_err_aer_headerlog_set,
output wire cfg_aer_ecrc_check_en,
output wire cfg_aer_ecrc_gen_en,
//----------------------------------------------------------------------------------------------------------------//
// 7. VC interface //
//----------------------------------------------------------------------------------------------------------------//
output wire [6:0] cfg_vc_tcvc_map,
//----------------------------------------------------------------------------------------------------------------//
// PCIe Fast Config: ICAP primitive Interface //
//----------------------------------------------------------------------------------------------------------------//
input wire icap_clk,
input wire icap_csib,
input wire icap_rdwrb,
input wire [31:0] icap_i,
output wire [31:0] icap_o,
input [ 2:0] pipe_txprbssel,
input [ 2:0] pipe_rxprbssel,
input pipe_txprbsforceerr,
input pipe_rxprbscntreset,
input [ 2:0] pipe_loopback,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_rxprbserr,
input [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_txinhibit,
output [4:0] pipe_rst_fsm,
output [11:0] pipe_qrst_fsm,
output [(LINK_CAP_MAX_LINK_WIDTH*5)-1:0] pipe_rate_fsm,
output [(LINK_CAP_MAX_LINK_WIDTH*6)-1:0] pipe_sync_fsm_tx,
output [(LINK_CAP_MAX_LINK_WIDTH*7)-1:0] pipe_sync_fsm_rx,
output [(LINK_CAP_MAX_LINK_WIDTH*7)-1:0] pipe_drp_fsm,
output pipe_rst_idle,
output pipe_qrst_idle,
output pipe_rate_idle,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_eyescandataerror,
output [(LINK_CAP_MAX_LINK_WIDTH*3)-1:0] pipe_rxstatus,
output [(LINK_CAP_MAX_LINK_WIDTH*15)-1:0] pipe_dmonitorout,
output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_cpll_lock,
output [(LINK_CAP_MAX_LINK_WIDTH-1)>>2:0] pipe_qpll_lock,
output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_rxpmaresetdone,
output [(LINK_CAP_MAX_LINK_WIDTH*3)-1:0] pipe_rxbufstatus,
output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_txphaligndone,
output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_txphinitdone,
output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_txdlysresetdone,
output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_rxphaligndone,
output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_rxdlysresetdone,
output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_rxsyncdone,
output [(LINK_CAP_MAX_LINK_WIDTH*8)-1:0] pipe_rxdisperr,
output [(LINK_CAP_MAX_LINK_WIDTH*8)-1:0] pipe_rxnotintable,
output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_rxcommadet,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] gt_ch_drp_rdy,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_0,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_1,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_2,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_3,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_4,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_5,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_6,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_7,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_8,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_9,
output [31:0] pipe_debug,
//--------------Channel DRP---------------------------------
output ext_ch_gt_drpclk,
input [(LINK_CAP_MAX_LINK_WIDTH*9)-1:0] ext_ch_gt_drpaddr,
input [LINK_CAP_MAX_LINK_WIDTH-1:0] ext_ch_gt_drpen,
input [(LINK_CAP_MAX_LINK_WIDTH*16)-1:0] ext_ch_gt_drpdi,
input [LINK_CAP_MAX_LINK_WIDTH-1:0] ext_ch_gt_drpwe,
output [(LINK_CAP_MAX_LINK_WIDTH*16)-1:0] ext_ch_gt_drpdo,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] ext_ch_gt_drprdy,
//----------------------------------------------------------------------------------------------------------------//
// PCIe Fast Config: STARTUP primitive Interface //
//----------------------------------------------------------------------------------------------------------------//
// This input should be used when the startup block is generated exteranl to the PCI Express Core
input startup_eos_in, // 1-bit input: This signal should be driven by the EOS output of the STARTUP primitive.
// These inputs and outputs may be use when the startup block is generated internal to the PCI Express Core.
output startup_cfgclk, // 1-bit output: Configuration main clock output
output startup_cfgmclk, // 1-bit output: Configuration internal oscillator clock output
output startup_eos, // 1-bit output: Active high output signal indicating the End Of Startup
output startup_preq, // 1-bit output: PROGRAM request to fabric output
input startup_clk, // 1-bit input: User start-up clock input
input startup_gsr, // 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
input startup_gts, // 1-bit input: Global 3-state input (GTS cannot be used for the port name)
input startup_keyclearb, // 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
input startup_pack, // 1-bit input: PROGRAM acknowledge input
input startup_usrcclko, // 1-bit input: User CCLK input
input startup_usrcclkts, // 1-bit input: User CCLK 3-state enable input
input startup_usrdoneo, // 1-bit input: User DONE pin output control
input startup_usrdonets, // 1-bit input: User DONE 3-state enable output
//----------------------------------------------------------------------------------------------------------------//
// 8. PCIe DRP (PCIe DRP) Interface //
//----------------------------------------------------------------------------------------------------------------//
input wire pcie_drp_clk,
input wire pcie_drp_en,
input wire pcie_drp_we,
input wire [8:0] pcie_drp_addr,
input wire [15:0] pcie_drp_di,
output wire pcie_drp_rdy,
output wire [15:0] pcie_drp_do,
//----------------------------------------------------------------------------------------------------------------//
// PIPE PORTS to TOP Level For PIPE SIMULATION with 3rd Party IP/BFM/Xilinx BFM
//----------------------------------------------------------------------------------------------------------------//
input wire [ 3:0] common_commands_in,
input wire [24:0] pipe_rx_0_sigs,
input wire [24:0] pipe_rx_1_sigs,
input wire [24:0] pipe_rx_2_sigs,
input wire [24:0] pipe_rx_3_sigs,
input wire [24:0] pipe_rx_4_sigs,
input wire [24:0] pipe_rx_5_sigs,
input wire [24:0] pipe_rx_6_sigs,
input wire [24:0] pipe_rx_7_sigs,
output wire [11:0] common_commands_out,
output wire [22:0] pipe_tx_0_sigs,
output wire [22:0] pipe_tx_1_sigs,
output wire [22:0] pipe_tx_2_sigs,
output wire [22:0] pipe_tx_3_sigs,
output wire [22:0] pipe_tx_4_sigs,
output wire [22:0] pipe_tx_5_sigs,
output wire [22:0] pipe_tx_6_sigs,
output wire [22:0] pipe_tx_7_sigs,
//----------------------------------------------------------------------------------------------------------------//
// 9. System(SYS) Interface //
//----------------------------------------------------------------------------------------------------------------//
input wire pipe_mmcm_rst_n, // Async | Async
input wire sys_clk,
input wire sys_rst_n
);
wire user_clk;
wire user_clk2;
wire pipe_clk;
wire [15:0] cfg_vend_id = CFG_VEND_ID;
wire [15:0] cfg_dev_id = CFG_DEV_ID;
wire [7:0] cfg_rev_id = CFG_REV_ID;
wire [15:0] cfg_subsys_vend_id = CFG_SUBSYS_VEND_ID;
wire [15:0] cfg_subsys_id = CFG_SUBSYS_ID;
// PIPE Interface Wires
wire phy_rdy_n;
wire pipe_rx0_polarity_gt;
wire pipe_rx1_polarity_gt;
wire pipe_rx2_polarity_gt;
wire pipe_rx3_polarity_gt;
wire pipe_rx4_polarity_gt;
wire pipe_rx5_polarity_gt;
wire pipe_rx6_polarity_gt;
wire pipe_rx7_polarity_gt;
wire pipe_tx_deemph_gt;
wire [2:0] pipe_tx_margin_gt;
wire pipe_tx_rate_gt;
wire pipe_tx_rcvr_det_gt;
wire [1:0] pipe_tx0_char_is_k_gt;
wire pipe_tx0_compliance_gt;
wire [15:0] pipe_tx0_data_gt;
wire pipe_tx0_elec_idle_gt;
wire [1:0] pipe_tx0_powerdown_gt;
wire [1:0] pipe_tx1_char_is_k_gt;
wire pipe_tx1_compliance_gt;
wire [15:0] pipe_tx1_data_gt;
wire pipe_tx1_elec_idle_gt;
wire [1:0] pipe_tx1_powerdown_gt;
wire [1:0] pipe_tx2_char_is_k_gt;
wire pipe_tx2_compliance_gt;
wire [15:0] pipe_tx2_data_gt;
wire pipe_tx2_elec_idle_gt;
wire [1:0] pipe_tx2_powerdown_gt;
wire [1:0] pipe_tx3_char_is_k_gt;
wire pipe_tx3_compliance_gt;
wire [15:0] pipe_tx3_data_gt;
wire pipe_tx3_elec_idle_gt;
wire [1:0] pipe_tx3_powerdown_gt;
wire [1:0] pipe_tx4_char_is_k_gt;
wire pipe_tx4_compliance_gt;
wire [15:0] pipe_tx4_data_gt;
wire pipe_tx4_elec_idle_gt;
wire [1:0] pipe_tx4_powerdown_gt;
wire [1:0] pipe_tx5_char_is_k_gt;
wire pipe_tx5_compliance_gt;
wire [15:0] pipe_tx5_data_gt;
wire pipe_tx5_elec_idle_gt;
wire [1:0] pipe_tx5_powerdown_gt;
wire [1:0] pipe_tx6_char_is_k_gt;
wire pipe_tx6_compliance_gt;
wire [15:0] pipe_tx6_data_gt;
wire pipe_tx6_elec_idle_gt;
wire [1:0] pipe_tx6_powerdown_gt;
wire [1:0] pipe_tx7_char_is_k_gt;
wire pipe_tx7_compliance_gt;
wire [15:0] pipe_tx7_data_gt;
wire pipe_tx7_elec_idle_gt;
wire [1:0] pipe_tx7_powerdown_gt;
wire pipe_rx0_chanisaligned_gt;
wire [1:0] pipe_rx0_char_is_k_gt;
wire [15:0] pipe_rx0_data_gt;
wire pipe_rx0_elec_idle_gt;
wire pipe_rx0_phy_status_gt;
wire [2:0] pipe_rx0_status_gt;
wire pipe_rx0_valid_gt;
wire pipe_rx1_chanisaligned_gt;
wire [1:0] pipe_rx1_char_is_k_gt;
wire [15:0] pipe_rx1_data_gt;
wire pipe_rx1_elec_idle_gt;
wire pipe_rx1_phy_status_gt;
wire [2:0] pipe_rx1_status_gt;
wire pipe_rx1_valid_gt;
wire pipe_rx2_chanisaligned_gt;
wire [1:0] pipe_rx2_char_is_k_gt;
wire [15:0] pipe_rx2_data_gt;
wire pipe_rx2_elec_idle_gt;
wire pipe_rx2_phy_status_gt;
wire [2:0] pipe_rx2_status_gt;
wire pipe_rx2_valid_gt;
wire pipe_rx3_chanisaligned_gt;
wire [1:0] pipe_rx3_char_is_k_gt;
wire [15:0] pipe_rx3_data_gt;
wire pipe_rx3_elec_idle_gt;
wire pipe_rx3_phy_status_gt;
wire [2:0] pipe_rx3_status_gt;
wire pipe_rx3_valid_gt;
wire pipe_rx4_chanisaligned_gt;
wire [1:0] pipe_rx4_char_is_k_gt;
wire [15:0] pipe_rx4_data_gt;
wire pipe_rx4_elec_idle_gt;
wire pipe_rx4_phy_status_gt;
wire [2:0] pipe_rx4_status_gt;
wire pipe_rx4_valid_gt;
wire pipe_rx5_chanisaligned_gt;
wire [1:0] pipe_rx5_char_is_k_gt;
wire [15:0] pipe_rx5_data_gt;
wire pipe_rx5_elec_idle_gt;
wire pipe_rx5_phy_status_gt;
wire [2:0] pipe_rx5_status_gt;
wire pipe_rx5_valid_gt;
wire pipe_rx6_chanisaligned_gt;
wire [1:0] pipe_rx6_char_is_k_gt;
wire [15:0] pipe_rx6_data_gt;
wire pipe_rx6_elec_idle_gt;
wire pipe_rx6_phy_status_gt;
wire [2:0] pipe_rx6_status_gt;
wire pipe_rx6_valid_gt;
wire pipe_rx7_chanisaligned_gt;
wire [1:0] pipe_rx7_char_is_k_gt;
wire [15:0] pipe_rx7_data_gt;
wire pipe_rx7_elec_idle_gt;
wire pipe_rx7_phy_status_gt;
wire [2:0] pipe_rx7_status_gt;
wire pipe_rx7_valid_gt;
(* ASYNC_REG = "TRUE" *) reg user_lnk_up_mux;
(* KEEP = "TRUE", ASYNC_REG = "TRUE" *) reg user_lnk_up_int;
reg user_reset_int;
reg bridge_reset_int;
reg bridge_reset_d;
wire user_rst_n;
reg pl_received_hot_rst_q;
wire pl_received_hot_rst_wire;
reg pl_phy_lnk_up_q;
wire pl_phy_lnk_up_wire;
wire sys_or_hot_rst;
wire trn_lnk_up;
wire [5:0] pl_ltssm_state_int;
wire user_app_rdy_req;
localparam TCQ = 100;
localparam ENABLE_FAST_SIM_TRAINING = "TRUE";
assign user_lnk_up = user_lnk_up_int;
assign user_app_rdy = 1'b1;
assign pl_ltssm_state = pl_ltssm_state_int;
assign pl_phy_lnk_up = pl_phy_lnk_up_q;
assign pl_received_hot_rst = pl_received_hot_rst_q;
// Register block outputs pl_received_hot_rst and phy_lnk_up to ease timing on block output
assign sys_or_hot_rst = !sys_rst_n || pl_received_hot_rst_q;
always @(posedge user_clk_out)
begin
if (!sys_rst_n) begin
pl_received_hot_rst_q <= #TCQ 1'b0;
pl_phy_lnk_up_q <= #TCQ 1'b0;
end else begin
pl_received_hot_rst_q <= #TCQ pl_received_hot_rst_wire;
pl_phy_lnk_up_q <= #TCQ pl_phy_lnk_up_wire;
end
end
// Generate user_lnk_up_mux
always @(posedge user_clk_out)
begin
if (!sys_rst_n) begin
user_lnk_up_mux <= #TCQ 1'b0;
end else begin
user_lnk_up_mux <= #TCQ user_lnk_up_int;
end
end
always @(posedge user_clk_out)
begin
if (!sys_rst_n) begin
user_lnk_up_int <= #TCQ 1'b0;
end else begin
user_lnk_up_int <= #TCQ trn_lnk_up;
end
end
// Generate user_reset_out //
// Once user reset output of PCIE and Phy Layer is active, de-assert reset //
// Only assert reset if system reset or hot reset is seen. Keep AXI backend/user application alive otherwise //
//------------------------------------------------------------------------------------------------------------------//
always @(posedge user_clk_out or posedge sys_or_hot_rst)
begin
if (sys_or_hot_rst) begin
user_reset_int <= #TCQ 1'b1;
end else if (user_rst_n && pl_phy_lnk_up_q) begin
user_reset_int <= #TCQ 1'b0;
end
end
// Invert active low reset to active high AXI reset
always @(posedge user_clk_out or posedge sys_or_hot_rst)
begin
if (sys_or_hot_rst) begin
user_reset_out <= #TCQ 1'b1;
end else begin
user_reset_out <= #TCQ user_reset_int;
end
end
always @(posedge user_clk_out or posedge sys_or_hot_rst)
begin
if (sys_or_hot_rst) begin
bridge_reset_int <= #TCQ 1'b1;
end else if (user_rst_n && pl_phy_lnk_up_q) begin
bridge_reset_int <= #TCQ 1'b0;
end
end
// Invert active low reset to active high AXI reset
always @(posedge user_clk_out or posedge sys_or_hot_rst)
begin
if (sys_or_hot_rst) begin
bridge_reset_d <= #TCQ 1'b1;
end else begin
bridge_reset_d <= #TCQ bridge_reset_int;
end
end
//------------------------------------------------------------------------------------------------------------------//
// **** PCI Express Core Wrapper **** //
// The PCI Express Core Wrapper includes the following: //
// 1) AXI Streaming Bridge //
// 2) PCIE 2_1 Hard Block //
// 3) PCIE PIPE Interface Pipeline //
//------------------------------------------------------------------------------------------------------------------//
PCIeGen2x8If128_pcie_top # (
.PIPE_PIPELINE_STAGES ( PIPE_PIPELINE_STAGES ),
.AER_BASE_PTR ( AER_BASE_PTR ),
.AER_CAP_ECRC_CHECK_CAPABLE ( AER_CAP_ECRC_CHECK_CAPABLE ),
.AER_CAP_ECRC_GEN_CAPABLE ( AER_CAP_ECRC_GEN_CAPABLE ),
.AER_CAP_ID ( AER_CAP_ID ),
.AER_CAP_MULTIHEADER ( AER_CAP_MULTIHEADER ),
.AER_CAP_NEXTPTR ( AER_CAP_NEXTPTR ),
.AER_CAP_ON ( AER_CAP_ON ),
.AER_CAP_OPTIONAL_ERR_SUPPORT ( AER_CAP_OPTIONAL_ERR_SUPPORT ),
.AER_CAP_PERMIT_ROOTERR_UPDATE ( AER_CAP_PERMIT_ROOTERR_UPDATE ),
.AER_CAP_VERSION ( AER_CAP_VERSION ),
.ALLOW_X8_GEN2 ( ALLOW_X8_GEN2 ),
.BAR0 ( BAR0 ),
.BAR1 ( BAR1 ),
.BAR2 ( BAR2 ),
.BAR3 ( BAR3 ),
.BAR4 ( BAR4 ),
.BAR5 ( BAR5 ),
.C_DATA_WIDTH ( C_DATA_WIDTH ),
.CAPABILITIES_PTR ( CAPABILITIES_PTR ),
.CARDBUS_CIS_POINTER ( CARDBUS_CIS_POINTER ),
.CFG_ECRC_ERR_CPLSTAT ( CFG_ECRC_ERR_CPLSTAT ),
.CLASS_CODE ( CLASS_CODE ),
.CMD_INTX_IMPLEMENTED ( CMD_INTX_IMPLEMENTED ),
.CPL_TIMEOUT_DISABLE_SUPPORTED ( CPL_TIMEOUT_DISABLE_SUPPORTED ),
.CPL_TIMEOUT_RANGES_SUPPORTED ( CPL_TIMEOUT_RANGES_SUPPORTED ),
.CRM_MODULE_RSTS ( CRM_MODULE_RSTS ),
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ),
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ),
.DEV_CAP_ENDPOINT_L0S_LATENCY ( DEV_CAP_ENDPOINT_L0S_LATENCY ),
.DEV_CAP_ENDPOINT_L1_LATENCY ( DEV_CAP_ENDPOINT_L1_LATENCY ),
.DEV_CAP_EXT_TAG_SUPPORTED ( DEV_CAP_EXT_TAG_SUPPORTED ),
.DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ( DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ),
.DEV_CAP_MAX_PAYLOAD_SUPPORTED ( DEV_CAP_MAX_PAYLOAD_SUPPORTED ),
.DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ( DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ),
.DEV_CAP_ROLE_BASED_ERROR ( DEV_CAP_ROLE_BASED_ERROR ),
.DEV_CAP_RSVD_14_12 ( DEV_CAP_RSVD_14_12 ),
.DEV_CAP_RSVD_17_16 ( DEV_CAP_RSVD_17_16 ),
.DEV_CAP_RSVD_31_29 ( DEV_CAP_RSVD_31_29 ),
.DEV_CONTROL_AUX_POWER_SUPPORTED ( DEV_CONTROL_AUX_POWER_SUPPORTED ),
.DEV_CONTROL_EXT_TAG_DEFAULT ( DEV_CONTROL_EXT_TAG_DEFAULT ),
.DISABLE_ASPM_L1_TIMER ( DISABLE_ASPM_L1_TIMER ),
.DISABLE_BAR_FILTERING ( DISABLE_BAR_FILTERING ),
.DISABLE_ID_CHECK ( DISABLE_ID_CHECK ),
.DISABLE_LANE_REVERSAL ( DISABLE_LANE_REVERSAL ),
.DISABLE_RX_POISONED_RESP ( DISABLE_RX_POISONED_RESP ),
.DISABLE_RX_TC_FILTER ( DISABLE_RX_TC_FILTER ),
.DISABLE_SCRAMBLING ( DISABLE_SCRAMBLING ),
.DNSTREAM_LINK_NUM ( DNSTREAM_LINK_NUM ),
.DSN_BASE_PTR ( DSN_BASE_PTR ),
.DSN_CAP_ID ( DSN_CAP_ID ),
.DSN_CAP_NEXTPTR ( DSN_CAP_NEXTPTR ),
.DSN_CAP_ON ( DSN_CAP_ON ),
.DSN_CAP_VERSION ( DSN_CAP_VERSION ),
.DEV_CAP2_ARI_FORWARDING_SUPPORTED ( DEV_CAP2_ARI_FORWARDING_SUPPORTED ),
.DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED ( DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED ),
.DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED ( DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED ),
.DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED ( DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED ),
.DEV_CAP2_CAS128_COMPLETER_SUPPORTED ( DEV_CAP2_CAS128_COMPLETER_SUPPORTED ),
.DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED ( DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED ),
.DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED ( DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED ),
.DEV_CAP2_LTR_MECHANISM_SUPPORTED ( DEV_CAP2_LTR_MECHANISM_SUPPORTED ),
.DEV_CAP2_MAX_ENDEND_TLP_PREFIXES ( DEV_CAP2_MAX_ENDEND_TLP_PREFIXES ),
.DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING ( DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING ),
.DEV_CAP2_TPH_COMPLETER_SUPPORTED ( DEV_CAP2_TPH_COMPLETER_SUPPORTED ),
.DISABLE_ERR_MSG ( DISABLE_ERR_MSG ),
.DISABLE_LOCKED_FILTER ( DISABLE_LOCKED_FILTER ),
.DISABLE_PPM_FILTER ( DISABLE_PPM_FILTER ),
.ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED ( ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED ),
.ENABLE_MSG_ROUTE ( ENABLE_MSG_ROUTE ),
.ENABLE_RX_TD_ECRC_TRIM ( ENABLE_RX_TD_ECRC_TRIM ),
.ENTER_RVRY_EI_L0 ( ENTER_RVRY_EI_L0 ),
.EXIT_LOOPBACK_ON_EI ( EXIT_LOOPBACK_ON_EI ),
.EXPANSION_ROM ( EXPANSION_ROM ),
.EXT_CFG_CAP_PTR ( EXT_CFG_CAP_PTR ),
.EXT_CFG_XP_CAP_PTR ( EXT_CFG_XP_CAP_PTR ),
.HEADER_TYPE ( HEADER_TYPE ),
.INFER_EI ( INFER_EI ),
.INTERRUPT_PIN ( INTERRUPT_PIN ),
.INTERRUPT_STAT_AUTO ( INTERRUPT_STAT_AUTO ),
.IS_SWITCH ( IS_SWITCH ),
.LAST_CONFIG_DWORD ( LAST_CONFIG_DWORD ),
.LINK_CAP_ASPM_OPTIONALITY ( LINK_CAP_ASPM_OPTIONALITY ),
.LINK_CAP_ASPM_SUPPORT ( LINK_CAP_ASPM_SUPPORT ),
.LINK_CAP_CLOCK_POWER_MANAGEMENT ( LINK_CAP_CLOCK_POWER_MANAGEMENT ),
.LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ( LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ),
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ),
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ),
.LINK_CAP_L0S_EXIT_LATENCY_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_GEN1 ),
.LINK_CAP_L0S_EXIT_LATENCY_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_GEN2 ),
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ),
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ),
.LINK_CAP_L1_EXIT_LATENCY_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_GEN1 ),
.LINK_CAP_L1_EXIT_LATENCY_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_GEN2 ),
.LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ( LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ),
.LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ),
.LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
.LINK_CAP_RSVD_23 ( LINK_CAP_RSVD_23 ),
.LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ( LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ),
.LINK_CONTROL_RCB ( LINK_CONTROL_RCB ),
.LINK_CTRL2_DEEMPHASIS ( LINK_CTRL2_DEEMPHASIS ),
.LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ( LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ),
.LINK_CTRL2_TARGET_LINK_SPEED ( LINK_CTRL2_TARGET_LINK_SPEED ),
.LINK_STATUS_SLOT_CLOCK_CONFIG ( LINK_STATUS_SLOT_CLOCK_CONFIG ),
.LL_ACK_TIMEOUT ( LL_ACK_TIMEOUT ),
.LL_ACK_TIMEOUT_EN ( LL_ACK_TIMEOUT_EN ),
.LL_ACK_TIMEOUT_FUNC ( LL_ACK_TIMEOUT_FUNC ),
.LL_REPLAY_TIMEOUT ( LL_REPLAY_TIMEOUT ),
.LL_REPLAY_TIMEOUT_EN ( LL_REPLAY_TIMEOUT_EN ),
.LL_REPLAY_TIMEOUT_FUNC ( LL_REPLAY_TIMEOUT_FUNC ),
.LTSSM_MAX_LINK_WIDTH ( LTSSM_MAX_LINK_WIDTH ),
.MPS_FORCE ( MPS_FORCE),
.MSI_BASE_PTR ( MSI_BASE_PTR ),
.MSI_CAP_ID ( MSI_CAP_ID ),
.MSI_CAP_MULTIMSGCAP ( MSI_CAP_MULTIMSGCAP ),
.MSI_CAP_MULTIMSG_EXTENSION ( MSI_CAP_MULTIMSG_EXTENSION ),
.MSI_CAP_NEXTPTR ( MSI_CAP_NEXTPTR ),
.MSI_CAP_ON ( MSI_CAP_ON ),
.MSI_CAP_PER_VECTOR_MASKING_CAPABLE ( MSI_CAP_PER_VECTOR_MASKING_CAPABLE ),
.MSI_CAP_64_BIT_ADDR_CAPABLE ( MSI_CAP_64_BIT_ADDR_CAPABLE ),
.MSIX_BASE_PTR ( MSIX_BASE_PTR ),
.MSIX_CAP_ID ( MSIX_CAP_ID ),
.MSIX_CAP_NEXTPTR ( MSIX_CAP_NEXTPTR ),
.MSIX_CAP_ON ( MSIX_CAP_ON ),
.MSIX_CAP_PBA_BIR ( MSIX_CAP_PBA_BIR ),
.MSIX_CAP_PBA_OFFSET ( MSIX_CAP_PBA_OFFSET ),
.MSIX_CAP_TABLE_BIR ( MSIX_CAP_TABLE_BIR ),
.MSIX_CAP_TABLE_OFFSET ( MSIX_CAP_TABLE_OFFSET ),
.MSIX_CAP_TABLE_SIZE ( MSIX_CAP_TABLE_SIZE ),
.N_FTS_COMCLK_GEN1 ( N_FTS_COMCLK_GEN1 ),
.N_FTS_COMCLK_GEN2 ( N_FTS_COMCLK_GEN2 ),
.N_FTS_GEN1 ( N_FTS_GEN1 ),
.N_FTS_GEN2 ( N_FTS_GEN2 ),
.PCIE_BASE_PTR ( PCIE_BASE_PTR ),
.PCIE_CAP_CAPABILITY_ID ( PCIE_CAP_CAPABILITY_ID ),
.PCIE_CAP_CAPABILITY_VERSION ( PCIE_CAP_CAPABILITY_VERSION ),
.PCIE_CAP_DEVICE_PORT_TYPE ( PCIE_CAP_DEVICE_PORT_TYPE ),
.PCIE_CAP_NEXTPTR ( PCIE_CAP_NEXTPTR ),
.PCIE_CAP_ON ( PCIE_CAP_ON ),
.PCIE_CAP_RSVD_15_14 ( PCIE_CAP_RSVD_15_14 ),
.PCIE_CAP_SLOT_IMPLEMENTED ( PCIE_CAP_SLOT_IMPLEMENTED ),
.PCIE_REVISION ( PCIE_REVISION ),
.PL_AUTO_CONFIG ( PL_AUTO_CONFIG ),
// synthesis translate_off
.PL_FAST_TRAIN ( ENABLE_FAST_SIM_TRAINING ),
// synthesis translate_on
.PM_ASPML0S_TIMEOUT ( PM_ASPML0S_TIMEOUT ),
.PM_ASPML0S_TIMEOUT_EN ( PM_ASPML0S_TIMEOUT_EN ),
.PM_ASPML0S_TIMEOUT_FUNC ( PM_ASPML0S_TIMEOUT_FUNC ),
.PM_ASPM_FASTEXIT ( PM_ASPM_FASTEXIT ),
.PM_BASE_PTR ( PM_BASE_PTR ),
.PM_CAP_AUXCURRENT ( PM_CAP_AUXCURRENT ),
.PM_CAP_D1SUPPORT ( PM_CAP_D1SUPPORT ),
.PM_CAP_D2SUPPORT ( PM_CAP_D2SUPPORT ),
.PM_CAP_DSI ( PM_CAP_DSI ),
.PM_CAP_ID ( PM_CAP_ID ),
.PM_CAP_NEXTPTR ( PM_CAP_NEXTPTR ),
.PM_CAP_ON ( PM_CAP_ON ),
.PM_CAP_PME_CLOCK ( PM_CAP_PME_CLOCK ),
.PM_CAP_PMESUPPORT ( PM_CAP_PMESUPPORT ),
.PM_CAP_RSVD_04 ( PM_CAP_RSVD_04 ),
.PM_CAP_VERSION ( PM_CAP_VERSION ),
.PM_CSR_B2B3 ( PM_CSR_B2B3 ),
.PM_CSR_BPCCEN ( PM_CSR_BPCCEN ),
.PM_CSR_NOSOFTRST ( PM_CSR_NOSOFTRST ),
.PM_DATA0 ( PM_DATA0 ),
.PM_DATA1 ( PM_DATA1 ),
.PM_DATA2 ( PM_DATA2 ),
.PM_DATA3 ( PM_DATA3 ),
.PM_DATA4 ( PM_DATA4 ),
.PM_DATA5 ( PM_DATA5 ),
.PM_DATA6 ( PM_DATA6 ),
.PM_DATA7 ( PM_DATA7 ),
.PM_DATA_SCALE0 ( PM_DATA_SCALE0 ),
.PM_DATA_SCALE1 ( PM_DATA_SCALE1 ),
.PM_DATA_SCALE2 ( PM_DATA_SCALE2 ),
.PM_DATA_SCALE3 ( PM_DATA_SCALE3 ),
.PM_DATA_SCALE4 ( PM_DATA_SCALE4 ),
.PM_DATA_SCALE5 ( PM_DATA_SCALE5 ),
.PM_DATA_SCALE6 ( PM_DATA_SCALE6 ),
.PM_DATA_SCALE7 ( PM_DATA_SCALE7 ),
.PM_MF ( PM_MF ),
.RBAR_BASE_PTR ( RBAR_BASE_PTR ),
.RBAR_CAP_CONTROL_ENCODEDBAR0 ( RBAR_CAP_CONTROL_ENCODEDBAR0 ),
.RBAR_CAP_CONTROL_ENCODEDBAR1 ( RBAR_CAP_CONTROL_ENCODEDBAR1 ),
.RBAR_CAP_CONTROL_ENCODEDBAR2 ( RBAR_CAP_CONTROL_ENCODEDBAR2 ),
.RBAR_CAP_CONTROL_ENCODEDBAR3 ( RBAR_CAP_CONTROL_ENCODEDBAR3 ),
.RBAR_CAP_CONTROL_ENCODEDBAR4 ( RBAR_CAP_CONTROL_ENCODEDBAR4 ),
.RBAR_CAP_CONTROL_ENCODEDBAR5 ( RBAR_CAP_CONTROL_ENCODEDBAR5 ),
.RBAR_CAP_ID ( RBAR_CAP_ID),
.RBAR_CAP_INDEX0 ( RBAR_CAP_INDEX0 ),
.RBAR_CAP_INDEX1 ( RBAR_CAP_INDEX1 ),
.RBAR_CAP_INDEX2 ( RBAR_CAP_INDEX2 ),
.RBAR_CAP_INDEX3 ( RBAR_CAP_INDEX3 ),
.RBAR_CAP_INDEX4 ( RBAR_CAP_INDEX4 ),
.RBAR_CAP_INDEX5 ( RBAR_CAP_INDEX5 ),
.RBAR_CAP_NEXTPTR ( RBAR_CAP_NEXTPTR ),
.RBAR_CAP_ON ( RBAR_CAP_ON ),
.RBAR_CAP_SUP0 ( RBAR_CAP_SUP0 ),
.RBAR_CAP_SUP1 ( RBAR_CAP_SUP1 ),
.RBAR_CAP_SUP2 ( RBAR_CAP_SUP2 ),
.RBAR_CAP_SUP3 ( RBAR_CAP_SUP3 ),
.RBAR_CAP_SUP4 ( RBAR_CAP_SUP4 ),
.RBAR_CAP_SUP5 ( RBAR_CAP_SUP5 ),
.RBAR_CAP_VERSION ( RBAR_CAP_VERSION ),
.RBAR_NUM ( RBAR_NUM ),
.RECRC_CHK ( RECRC_CHK ),
.RECRC_CHK_TRIM ( RECRC_CHK_TRIM ),
.ROOT_CAP_CRS_SW_VISIBILITY ( ROOT_CAP_CRS_SW_VISIBILITY ),
.RP_AUTO_SPD ( RP_AUTO_SPD ),
.RP_AUTO_SPD_LOOPCNT ( RP_AUTO_SPD_LOOPCNT ),
.SELECT_DLL_IF ( SELECT_DLL_IF ),
.SLOT_CAP_ATT_BUTTON_PRESENT ( SLOT_CAP_ATT_BUTTON_PRESENT ),
.SLOT_CAP_ATT_INDICATOR_PRESENT ( SLOT_CAP_ATT_INDICATOR_PRESENT ),
.SLOT_CAP_ELEC_INTERLOCK_PRESENT ( SLOT_CAP_ELEC_INTERLOCK_PRESENT ),
.SLOT_CAP_HOTPLUG_CAPABLE ( SLOT_CAP_HOTPLUG_CAPABLE ),
.SLOT_CAP_HOTPLUG_SURPRISE ( SLOT_CAP_HOTPLUG_SURPRISE ),
.SLOT_CAP_MRL_SENSOR_PRESENT ( SLOT_CAP_MRL_SENSOR_PRESENT ),
.SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ( SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ),
.SLOT_CAP_PHYSICAL_SLOT_NUM ( SLOT_CAP_PHYSICAL_SLOT_NUM ),
.SLOT_CAP_POWER_CONTROLLER_PRESENT ( SLOT_CAP_POWER_CONTROLLER_PRESENT ),
.SLOT_CAP_POWER_INDICATOR_PRESENT ( SLOT_CAP_POWER_INDICATOR_PRESENT ),
.SLOT_CAP_SLOT_POWER_LIMIT_SCALE ( SLOT_CAP_SLOT_POWER_LIMIT_SCALE ),
.SLOT_CAP_SLOT_POWER_LIMIT_VALUE ( SLOT_CAP_SLOT_POWER_LIMIT_VALUE ),
.SPARE_BIT0 ( SPARE_BIT0 ),
.SPARE_BIT1 ( SPARE_BIT1 ),
.SPARE_BIT2 ( SPARE_BIT2 ),
.SPARE_BIT3 ( SPARE_BIT3 ),
.SPARE_BIT4 ( SPARE_BIT4 ),
.SPARE_BIT5 ( SPARE_BIT5 ),
.SPARE_BIT6 ( SPARE_BIT6 ),
.SPARE_BIT7 ( SPARE_BIT7 ),
.SPARE_BIT8 ( SPARE_BIT8 ),
.SPARE_BYTE0 ( SPARE_BYTE0 ),
.SPARE_BYTE1 ( SPARE_BYTE1 ),
.SPARE_BYTE2 ( SPARE_BYTE2 ),
.SPARE_BYTE3 ( SPARE_BYTE3 ),
.SPARE_WORD0 ( SPARE_WORD0 ),
.SPARE_WORD1 ( SPARE_WORD1 ),
.SPARE_WORD2 ( SPARE_WORD2 ),
.SPARE_WORD3 ( SPARE_WORD3 ),
.SSL_MESSAGE_AUTO ( SSL_MESSAGE_AUTO ),
.TECRC_EP_INV ( TECRC_EP_INV ),
.TL_RBYPASS ( TL_RBYPASS ),
.TL_RX_RAM_RADDR_LATENCY ( TL_RX_RAM_RADDR_LATENCY ),
.TL_RX_RAM_RDATA_LATENCY ( TL_RX_RAM_RDATA_LATENCY ),
.TL_RX_RAM_WRITE_LATENCY ( TL_RX_RAM_WRITE_LATENCY ),
.TL_TFC_DISABLE ( TL_TFC_DISABLE ),
.TL_TX_CHECKS_DISABLE ( TL_TX_CHECKS_DISABLE ),
.TL_TX_RAM_RADDR_LATENCY ( TL_TX_RAM_RADDR_LATENCY ),
.TL_TX_RAM_RDATA_LATENCY ( TL_TX_RAM_RDATA_LATENCY ),
.TL_TX_RAM_WRITE_LATENCY ( TL_TX_RAM_WRITE_LATENCY ),
.TRN_DW ( TRN_DW ),
.TRN_NP_FC ( TRN_NP_FC ),
.UPCONFIG_CAPABLE ( UPCONFIG_CAPABLE ),
.UPSTREAM_FACING ( UPSTREAM_FACING ),
.UR_ATOMIC ( UR_ATOMIC ),
.UR_CFG1 ( UR_CFG1 ),
.UR_INV_REQ ( UR_INV_REQ ),
.UR_PRS_RESPONSE ( UR_PRS_RESPONSE ),
.USER_CLK2_DIV2 ( USER_CLK2_DIV2 ),
.USER_CLK_FREQ ( USER_CLK_FREQ ),
.USE_RID_PINS ( USE_RID_PINS ),
.VC0_CPL_INFINITE ( VC0_CPL_INFINITE ),
.VC0_RX_RAM_LIMIT ( VC0_RX_RAM_LIMIT ),
.VC0_TOTAL_CREDITS_CD ( VC0_TOTAL_CREDITS_CD ),
.VC0_TOTAL_CREDITS_CH ( VC0_TOTAL_CREDITS_CH ),
.VC0_TOTAL_CREDITS_NPD ( VC0_TOTAL_CREDITS_NPD),
.VC0_TOTAL_CREDITS_NPH ( VC0_TOTAL_CREDITS_NPH ),
.VC0_TOTAL_CREDITS_PD ( VC0_TOTAL_CREDITS_PD ),
.VC0_TOTAL_CREDITS_PH ( VC0_TOTAL_CREDITS_PH ),
.VC0_TX_LASTPACKET ( VC0_TX_LASTPACKET ),
.VC_BASE_PTR ( VC_BASE_PTR ),
.VC_CAP_ID ( VC_CAP_ID ),
.VC_CAP_NEXTPTR ( VC_CAP_NEXTPTR ),
.VC_CAP_ON ( VC_CAP_ON ),
.VC_CAP_REJECT_SNOOP_TRANSACTIONS ( VC_CAP_REJECT_SNOOP_TRANSACTIONS ),
.VC_CAP_VERSION ( VC_CAP_VERSION ),
.VSEC_BASE_PTR ( VSEC_BASE_PTR ),
.VSEC_CAP_HDR_ID ( VSEC_CAP_HDR_ID ),
.VSEC_CAP_HDR_LENGTH ( VSEC_CAP_HDR_LENGTH ),
.VSEC_CAP_HDR_REVISION ( VSEC_CAP_HDR_REVISION ),
.VSEC_CAP_ID ( VSEC_CAP_ID ),
.VSEC_CAP_IS_LINK_VISIBLE ( VSEC_CAP_IS_LINK_VISIBLE ),
.VSEC_CAP_NEXTPTR ( VSEC_CAP_NEXTPTR ),
.VSEC_CAP_ON ( VSEC_CAP_ON ),
.VSEC_CAP_VERSION ( VSEC_CAP_VERSION )
// I/O
) pcie_top_i (
// AXI Interface
.user_clk_out ( user_clk_out ),
.user_reset ( bridge_reset_d ),
.user_lnk_up ( user_lnk_up ),
.user_rst_n ( user_rst_n ),
.trn_lnk_up ( trn_lnk_up ),
.tx_buf_av ( tx_buf_av ),
.tx_err_drop ( tx_err_drop ),
.tx_cfg_req ( tx_cfg_req ),
.s_axis_tx_tready ( s_axis_tx_tready ),
.s_axis_tx_tdata ( s_axis_tx_tdata ),
.s_axis_tx_tkeep ( s_axis_tx_tkeep ),
.s_axis_tx_tuser ( s_axis_tx_tuser ),
.s_axis_tx_tlast ( s_axis_tx_tlast ),
.s_axis_tx_tvalid ( s_axis_tx_tvalid ),
.tx_cfg_gnt ( tx_cfg_gnt ),
.m_axis_rx_tdata ( m_axis_rx_tdata ),
.m_axis_rx_tkeep ( m_axis_rx_tkeep ),
.m_axis_rx_tlast ( m_axis_rx_tlast ),
.m_axis_rx_tvalid ( m_axis_rx_tvalid ),
.m_axis_rx_tready ( m_axis_rx_tready ),
.m_axis_rx_tuser ( m_axis_rx_tuser ),
.rx_np_ok ( rx_np_ok ),
.rx_np_req ( rx_np_req ),
.fc_cpld ( fc_cpld ),
.fc_cplh ( fc_cplh ),
.fc_npd ( fc_npd ),
.fc_nph ( fc_nph ),
.fc_pd ( fc_pd ),
.fc_ph ( fc_ph ),
.fc_sel ( fc_sel ),
.cfg_turnoff_ok ( cfg_turnoff_ok ),
.cfg_received_func_lvl_rst ( cfg_received_func_lvl_rst ),
.cm_rst_n ( 1'b1 ),
.func_lvl_rst_n ( 1'b1 ),
.lnk_clk_en ( ),
.cfg_dev_id ( cfg_dev_id ),
.cfg_vend_id ( cfg_vend_id ),
.cfg_rev_id ( cfg_rev_id ),
.cfg_subsys_id ( cfg_subsys_id ),
.cfg_subsys_vend_id ( cfg_subsys_vend_id ),
.cfg_pciecap_interrupt_msgnum ( cfg_pciecap_interrupt_msgnum ),
.cfg_bridge_serr_en ( cfg_bridge_serr_en ),
.cfg_command_bus_master_enable ( ),
.cfg_command_interrupt_disable ( ),
.cfg_command_io_enable ( ),
.cfg_command_mem_enable ( ),
.cfg_command_serr_en ( ),
.cfg_dev_control_aux_power_en ( ),
.cfg_dev_control_corr_err_reporting_en ( ),
.cfg_dev_control_enable_ro ( ),
.cfg_dev_control_ext_tag_en ( ),
.cfg_dev_control_fatal_err_reporting_en ( ),
.cfg_dev_control_max_payload ( ),
.cfg_dev_control_max_read_req ( ),
.cfg_dev_control_non_fatal_reporting_en ( ),
.cfg_dev_control_no_snoop_en ( ),
.cfg_dev_control_phantom_en ( ),
.cfg_dev_control_ur_err_reporting_en ( ),
.cfg_dev_control2_cpl_timeout_dis ( ),
.cfg_dev_control2_cpl_timeout_val ( ),
.cfg_dev_control2_ari_forward_en ( ),
.cfg_dev_control2_atomic_requester_en ( ),
.cfg_dev_control2_atomic_egress_block ( ),
.cfg_dev_control2_ido_req_en ( ),
.cfg_dev_control2_ido_cpl_en ( ),
.cfg_dev_control2_ltr_en ( ),
.cfg_dev_control2_tlp_prefix_block ( ),
.cfg_dev_status_corr_err_detected ( ),
.cfg_dev_status_fatal_err_detected ( ),
.cfg_dev_status_non_fatal_err_detected ( ),
.cfg_dev_status_ur_detected ( ),
.cfg_mgmt_do ( cfg_mgmt_do ),
.cfg_err_aer_headerlog_set ( cfg_err_aer_headerlog_set ),
.cfg_err_aer_headerlog ( cfg_err_aer_headerlog ),
.cfg_err_cpl_rdy ( cfg_err_cpl_rdy ),
.cfg_interrupt_do ( cfg_interrupt_do ),
.cfg_interrupt_mmenable ( cfg_interrupt_mmenable ),
.cfg_interrupt_msienable ( cfg_interrupt_msienable ),
.cfg_interrupt_msixenable ( cfg_interrupt_msixenable ),
.cfg_interrupt_msixfm ( cfg_interrupt_msixfm ),
.cfg_interrupt_rdy ( cfg_interrupt_rdy ),
.cfg_link_control_rcb ( ),
.cfg_link_control_aspm_control ( ),
.cfg_link_control_auto_bandwidth_int_en ( ),
.cfg_link_control_bandwidth_int_en ( ),
.cfg_link_control_clock_pm_en ( ),
.cfg_link_control_common_clock ( ),
.cfg_link_control_extended_sync ( ),
.cfg_link_control_hw_auto_width_dis ( ),
.cfg_link_control_link_disable ( ),
.cfg_link_control_retrain_link ( ),
.cfg_link_status_auto_bandwidth_status ( ),
.cfg_link_status_bandwidth_status ( ),
.cfg_link_status_current_speed ( ),
.cfg_link_status_dll_active ( ),
.cfg_link_status_link_training ( ),
.cfg_link_status_negotiated_width ( ),
.cfg_msg_data ( cfg_msg_data ),
.cfg_msg_received ( cfg_msg_received ),
.cfg_msg_received_assert_int_a ( cfg_msg_received_assert_int_a ),
.cfg_msg_received_assert_int_b ( cfg_msg_received_assert_int_b ),
.cfg_msg_received_assert_int_c ( cfg_msg_received_assert_int_c ),
.cfg_msg_received_assert_int_d ( cfg_msg_received_assert_int_d ),
.cfg_msg_received_deassert_int_a ( cfg_msg_received_deassert_int_a ),
.cfg_msg_received_deassert_int_b ( cfg_msg_received_deassert_int_b ),
.cfg_msg_received_deassert_int_c ( cfg_msg_received_deassert_int_c ),
.cfg_msg_received_deassert_int_d ( cfg_msg_received_deassert_int_d ),
.cfg_msg_received_err_cor ( cfg_msg_received_err_cor ),
.cfg_msg_received_err_fatal ( cfg_msg_received_err_fatal ),
.cfg_msg_received_err_non_fatal ( cfg_msg_received_err_non_fatal ),
.cfg_msg_received_pm_as_nak ( cfg_msg_received_pm_as_nak ),
.cfg_msg_received_pme_to ( ),
.cfg_msg_received_pme_to_ack ( cfg_msg_received_pme_to_ack ),
.cfg_msg_received_pm_pme ( cfg_msg_received_pm_pme ),
.cfg_msg_received_setslotpowerlimit ( cfg_msg_received_setslotpowerlimit ),
.cfg_msg_received_unlock ( ),
.cfg_to_turnoff ( cfg_to_turnoff ),
.cfg_status ( cfg_status ),
.cfg_command ( cfg_command ),
.cfg_dstatus ( cfg_dstatus ),
.cfg_dcommand ( cfg_dcommand ),
.cfg_lstatus ( cfg_lstatus ),
.cfg_lcommand ( cfg_lcommand ),
.cfg_dcommand2 ( cfg_dcommand2 ),
.cfg_pcie_link_state ( cfg_pcie_link_state ),
.cfg_pmcsr_pme_en ( cfg_pmcsr_pme_en ),
.cfg_pmcsr_powerstate ( cfg_pmcsr_powerstate ),
.cfg_pmcsr_pme_status ( cfg_pmcsr_pme_status ),
.cfg_pm_rcv_as_req_l1_n ( ),
.cfg_pm_rcv_enter_l1_n ( ),
.cfg_pm_rcv_enter_l23_n ( ),
.cfg_pm_rcv_req_ack_n ( ),
.cfg_mgmt_rd_wr_done ( cfg_mgmt_rd_wr_done ),
.cfg_slot_control_electromech_il_ctl_pulse ( cfg_slot_control_electromech_il_ctl_pulse ),
.cfg_root_control_syserr_corr_err_en ( cfg_root_control_syserr_corr_err_en ),
.cfg_root_control_syserr_non_fatal_err_en ( cfg_root_control_syserr_non_fatal_err_en ),
.cfg_root_control_syserr_fatal_err_en ( cfg_root_control_syserr_fatal_err_en ),
.cfg_root_control_pme_int_en ( cfg_root_control_pme_int_en),
.cfg_aer_ecrc_check_en ( cfg_aer_ecrc_check_en ),
.cfg_aer_ecrc_gen_en ( cfg_aer_ecrc_gen_en ),
.cfg_aer_rooterr_corr_err_reporting_en ( cfg_aer_rooterr_corr_err_reporting_en ),
.cfg_aer_rooterr_non_fatal_err_reporting_en ( cfg_aer_rooterr_non_fatal_err_reporting_en ),
.cfg_aer_rooterr_fatal_err_reporting_en ( cfg_aer_rooterr_fatal_err_reporting_en ),
.cfg_aer_rooterr_corr_err_received ( cfg_aer_rooterr_corr_err_received ),
.cfg_aer_rooterr_non_fatal_err_received ( cfg_aer_rooterr_non_fatal_err_received ),
.cfg_aer_rooterr_fatal_err_received ( cfg_aer_rooterr_fatal_err_received ),
.cfg_aer_interrupt_msgnum ( cfg_aer_interrupt_msgnum ),
.cfg_transaction ( ),
.cfg_transaction_addr ( ),
.cfg_transaction_type ( ),
.cfg_vc_tcvc_map ( cfg_vc_tcvc_map ),
.cfg_mgmt_byte_en_n ( ~cfg_mgmt_byte_en ),
.cfg_mgmt_di ( cfg_mgmt_di ),
.cfg_dsn ( cfg_dsn ),
.cfg_mgmt_dwaddr ( cfg_mgmt_dwaddr ),
.cfg_err_acs_n ( 1'b1 ),
.cfg_err_cor_n ( ~cfg_err_cor ),
.cfg_err_cpl_abort_n ( ~cfg_err_cpl_abort ),
.cfg_err_cpl_timeout_n ( ~cfg_err_cpl_timeout ),
.cfg_err_cpl_unexpect_n ( ~cfg_err_cpl_unexpect ),
.cfg_err_ecrc_n ( ~cfg_err_ecrc ),
.cfg_err_locked_n ( ~cfg_err_locked ),
.cfg_err_posted_n ( ~cfg_err_posted ),
.cfg_err_tlp_cpl_header ( cfg_err_tlp_cpl_header ),
.cfg_err_ur_n ( ~cfg_err_ur ),
.cfg_err_malformed_n ( ~cfg_err_malformed ),
.cfg_err_poisoned_n ( ~cfg_err_poisoned ),
.cfg_err_atomic_egress_blocked_n ( ~cfg_err_atomic_egress_blocked ),
.cfg_err_mc_blocked_n ( ~cfg_err_mc_blocked ),
.cfg_err_internal_uncor_n ( ~cfg_err_internal_uncor ),
.cfg_err_internal_cor_n ( ~cfg_err_internal_cor ),
.cfg_err_norecovery_n ( ~cfg_err_norecovery ),
.cfg_interrupt_assert_n ( ~cfg_interrupt_assert ),
.cfg_interrupt_di ( cfg_interrupt_di ),
.cfg_interrupt_n ( ~cfg_interrupt ),
.cfg_interrupt_stat_n ( ~cfg_interrupt_stat ),
.cfg_bus_number ( cfg_bus_number ),
.cfg_device_number ( cfg_device_number ),
.cfg_function_number ( cfg_function_number ),
.cfg_ds_bus_number ( cfg_ds_bus_number ),
.cfg_ds_device_number ( cfg_ds_device_number ),
.cfg_ds_function_number ( cfg_ds_function_number ),
.cfg_pm_send_pme_to_n ( 1'b1 ),
.cfg_pm_wake_n ( ~cfg_pm_wake ),
.cfg_pm_halt_aspm_l0s_n ( ~cfg_pm_halt_aspm_l0s ),
.cfg_pm_halt_aspm_l1_n ( ~cfg_pm_halt_aspm_l1 ),
.cfg_pm_force_state_en_n ( ~cfg_pm_force_state_en),
.cfg_pm_force_state ( cfg_pm_force_state ),
.cfg_force_mps ( 3'b0 ),
.cfg_force_common_clock_off ( 1'b0 ),
.cfg_force_extended_sync_on ( 1'b0 ),
.cfg_port_number ( 8'b0 ),
.cfg_mgmt_rd_en_n ( ~cfg_mgmt_rd_en ),
.cfg_trn_pending ( cfg_trn_pending ),
.cfg_mgmt_wr_en_n ( ~cfg_mgmt_wr_en ),
.cfg_mgmt_wr_readonly_n ( ~cfg_mgmt_wr_readonly ),
.cfg_mgmt_wr_rw1c_as_rw_n ( ~cfg_mgmt_wr_rw1c_as_rw ),
.pl_initial_link_width ( pl_initial_link_width ),
.pl_lane_reversal_mode ( pl_lane_reversal_mode ),
.pl_link_gen2_cap ( pl_link_gen2_cap ),
.pl_link_partner_gen2_supported ( pl_link_partner_gen2_supported ),
.pl_link_upcfg_cap ( pl_link_upcfg_cap ),
.pl_ltssm_state ( pl_ltssm_state_int ),
.pl_phy_lnk_up ( pl_phy_lnk_up_wire ),
.pl_received_hot_rst ( pl_received_hot_rst_wire ),
.pl_rx_pm_state ( pl_rx_pm_state ),
.pl_sel_lnk_rate ( pl_sel_lnk_rate ),
.pl_sel_lnk_width ( pl_sel_lnk_width ),
.pl_tx_pm_state ( pl_tx_pm_state ),
.pl_directed_link_auton ( pl_directed_link_auton ),
.pl_directed_link_change ( pl_directed_link_change ),
.pl_directed_link_speed ( pl_directed_link_speed ),
.pl_directed_link_width ( pl_directed_link_width ),
.pl_downstream_deemph_source ( pl_downstream_deemph_source ),
.pl_upstream_prefer_deemph ( pl_upstream_prefer_deemph ),
.pl_transmit_hot_rst ( pl_transmit_hot_rst ),
.pl_directed_ltssm_new_vld ( 1'b0 ),
.pl_directed_ltssm_new ( 6'b0 ),
.pl_directed_ltssm_stall ( 1'b0 ),
.pl_directed_change_done ( pl_directed_change_done ),
.phy_rdy_n ( phy_rdy_n ),
.dbg_sclr_a ( ),
.dbg_sclr_b ( ),
.dbg_sclr_c ( ),
.dbg_sclr_d ( ),
.dbg_sclr_e ( ),
.dbg_sclr_f ( ),
.dbg_sclr_g ( ),
.dbg_sclr_h ( ),
.dbg_sclr_i ( ),
.dbg_sclr_j ( ),
.dbg_sclr_k ( ),
.dbg_vec_a ( ),
.dbg_vec_b ( ),
.dbg_vec_c ( ),
.pl_dbg_vec ( ),
.trn_rdllp_data ( ),
.trn_rdllp_src_rdy ( ),
.dbg_mode ( 2'b0 ),
.dbg_sub_mode ( 1'b0 ),
.pl_dbg_mode ( 3'b0 ),
.drp_clk ( pcie_drp_clk ),
.drp_do ( pcie_drp_do ),
.drp_rdy ( pcie_drp_rdy ),
.drp_addr ( pcie_drp_addr ),
.drp_en ( pcie_drp_en ),
.drp_di ( pcie_drp_di ),
.drp_we ( pcie_drp_we ),
// Pipe Interface
.pipe_clk ( pipe_clk ),
.user_clk ( user_clk ),
.user_clk2 ( user_clk2 ),
.pipe_rx0_polarity_gt ( pipe_rx0_polarity_gt ),
.pipe_rx1_polarity_gt ( pipe_rx1_polarity_gt ),
.pipe_rx2_polarity_gt ( pipe_rx2_polarity_gt ),
.pipe_rx3_polarity_gt ( pipe_rx3_polarity_gt ),
.pipe_rx4_polarity_gt ( pipe_rx4_polarity_gt ),
.pipe_rx5_polarity_gt ( pipe_rx5_polarity_gt ),
.pipe_rx6_polarity_gt ( pipe_rx6_polarity_gt ),
.pipe_rx7_polarity_gt ( pipe_rx7_polarity_gt ),
.pipe_tx_deemph_gt ( pipe_tx_deemph_gt ),
.pipe_tx_margin_gt ( pipe_tx_margin_gt ),
.pipe_tx_rate_gt ( pipe_tx_rate_gt ),
.pipe_tx_rcvr_det_gt ( pipe_tx_rcvr_det_gt ),
.pipe_tx0_char_is_k_gt ( pipe_tx0_char_is_k_gt ),
.pipe_tx0_compliance_gt ( pipe_tx0_compliance_gt ),
.pipe_tx0_data_gt ( pipe_tx0_data_gt ),
.pipe_tx0_elec_idle_gt ( pipe_tx0_elec_idle_gt ),
.pipe_tx0_powerdown_gt ( pipe_tx0_powerdown_gt ),
.pipe_tx1_char_is_k_gt ( pipe_tx1_char_is_k_gt ),
.pipe_tx1_compliance_gt ( pipe_tx1_compliance_gt ),
.pipe_tx1_data_gt ( pipe_tx1_data_gt ),
.pipe_tx1_elec_idle_gt ( pipe_tx1_elec_idle_gt ),
.pipe_tx1_powerdown_gt ( pipe_tx1_powerdown_gt ),
.pipe_tx2_char_is_k_gt ( pipe_tx2_char_is_k_gt ),
.pipe_tx2_compliance_gt ( pipe_tx2_compliance_gt ),
.pipe_tx2_data_gt ( pipe_tx2_data_gt ),
.pipe_tx2_elec_idle_gt ( pipe_tx2_elec_idle_gt ),
.pipe_tx2_powerdown_gt ( pipe_tx2_powerdown_gt ),
.pipe_tx3_char_is_k_gt ( pipe_tx3_char_is_k_gt ),
.pipe_tx3_compliance_gt ( pipe_tx3_compliance_gt ),
.pipe_tx3_data_gt ( pipe_tx3_data_gt ),
.pipe_tx3_elec_idle_gt ( pipe_tx3_elec_idle_gt ),
.pipe_tx3_powerdown_gt ( pipe_tx3_powerdown_gt ),
.pipe_tx4_char_is_k_gt ( pipe_tx4_char_is_k_gt ),
.pipe_tx4_compliance_gt ( pipe_tx4_compliance_gt ),
.pipe_tx4_data_gt ( pipe_tx4_data_gt ),
.pipe_tx4_elec_idle_gt ( pipe_tx4_elec_idle_gt ),
.pipe_tx4_powerdown_gt ( pipe_tx4_powerdown_gt ),
.pipe_tx5_char_is_k_gt ( pipe_tx5_char_is_k_gt ),
.pipe_tx5_compliance_gt ( pipe_tx5_compliance_gt ),
.pipe_tx5_data_gt ( pipe_tx5_data_gt ),
.pipe_tx5_elec_idle_gt ( pipe_tx5_elec_idle_gt ),
.pipe_tx5_powerdown_gt ( pipe_tx5_powerdown_gt ),
.pipe_tx6_char_is_k_gt ( pipe_tx6_char_is_k_gt ),
.pipe_tx6_compliance_gt ( pipe_tx6_compliance_gt ),
.pipe_tx6_data_gt ( pipe_tx6_data_gt ),
.pipe_tx6_elec_idle_gt ( pipe_tx6_elec_idle_gt ),
.pipe_tx6_powerdown_gt ( pipe_tx6_powerdown_gt ),
.pipe_tx7_char_is_k_gt ( pipe_tx7_char_is_k_gt ),
.pipe_tx7_compliance_gt ( pipe_tx7_compliance_gt ),
.pipe_tx7_data_gt ( pipe_tx7_data_gt ),
.pipe_tx7_elec_idle_gt ( pipe_tx7_elec_idle_gt ),
.pipe_tx7_powerdown_gt ( pipe_tx7_powerdown_gt ),
.pipe_rx0_chanisaligned_gt ( pipe_rx0_chanisaligned_gt ),
.pipe_rx0_char_is_k_gt ( pipe_rx0_char_is_k_gt ),
.pipe_rx0_data_gt ( pipe_rx0_data_gt ),
.pipe_rx0_elec_idle_gt ( pipe_rx0_elec_idle_gt ),
.pipe_rx0_phy_status_gt ( pipe_rx0_phy_status_gt ),
.pipe_rx0_status_gt ( pipe_rx0_status_gt ),
.pipe_rx0_valid_gt ( pipe_rx0_valid_gt ),
.pipe_rx1_chanisaligned_gt ( pipe_rx1_chanisaligned_gt ),
.pipe_rx1_char_is_k_gt ( pipe_rx1_char_is_k_gt ),
.pipe_rx1_data_gt ( pipe_rx1_data_gt ),
.pipe_rx1_elec_idle_gt ( pipe_rx1_elec_idle_gt ),
.pipe_rx1_phy_status_gt ( pipe_rx1_phy_status_gt ),
.pipe_rx1_status_gt ( pipe_rx1_status_gt ),
.pipe_rx1_valid_gt ( pipe_rx1_valid_gt ),
.pipe_rx2_chanisaligned_gt ( pipe_rx2_chanisaligned_gt ),
.pipe_rx2_char_is_k_gt ( pipe_rx2_char_is_k_gt ),
.pipe_rx2_data_gt ( pipe_rx2_data_gt ),
.pipe_rx2_elec_idle_gt ( pipe_rx2_elec_idle_gt ),
.pipe_rx2_phy_status_gt ( pipe_rx2_phy_status_gt ),
.pipe_rx2_status_gt ( pipe_rx2_status_gt ),
.pipe_rx2_valid_gt ( pipe_rx2_valid_gt ),
.pipe_rx3_chanisaligned_gt ( pipe_rx3_chanisaligned_gt ),
.pipe_rx3_char_is_k_gt ( pipe_rx3_char_is_k_gt ),
.pipe_rx3_data_gt ( pipe_rx3_data_gt ),
.pipe_rx3_elec_idle_gt ( pipe_rx3_elec_idle_gt ),
.pipe_rx3_phy_status_gt ( pipe_rx3_phy_status_gt ),
.pipe_rx3_status_gt ( pipe_rx3_status_gt ),
.pipe_rx3_valid_gt ( pipe_rx3_valid_gt ),
.pipe_rx4_chanisaligned_gt ( pipe_rx4_chanisaligned_gt ),
.pipe_rx4_char_is_k_gt ( pipe_rx4_char_is_k_gt ),
.pipe_rx4_data_gt ( pipe_rx4_data_gt ),
.pipe_rx4_elec_idle_gt ( pipe_rx4_elec_idle_gt ),
.pipe_rx4_phy_status_gt ( pipe_rx4_phy_status_gt ),
.pipe_rx4_status_gt ( pipe_rx4_status_gt ),
.pipe_rx4_valid_gt ( pipe_rx4_valid_gt ),
.pipe_rx5_chanisaligned_gt ( pipe_rx5_chanisaligned_gt ),
.pipe_rx5_char_is_k_gt ( pipe_rx5_char_is_k_gt ),
.pipe_rx5_data_gt ( pipe_rx5_data_gt ),
.pipe_rx5_elec_idle_gt ( pipe_rx5_elec_idle_gt ),
.pipe_rx5_phy_status_gt ( pipe_rx5_phy_status_gt ),
.pipe_rx5_status_gt ( pipe_rx5_status_gt ),
.pipe_rx5_valid_gt ( pipe_rx5_valid_gt ),
.pipe_rx6_chanisaligned_gt ( pipe_rx6_chanisaligned_gt ),
.pipe_rx6_char_is_k_gt ( pipe_rx6_char_is_k_gt ),
.pipe_rx6_data_gt ( pipe_rx6_data_gt ),
.pipe_rx6_elec_idle_gt ( pipe_rx6_elec_idle_gt ),
.pipe_rx6_phy_status_gt ( pipe_rx6_phy_status_gt ),
.pipe_rx6_status_gt ( pipe_rx6_status_gt ),
.pipe_rx6_valid_gt ( pipe_rx6_valid_gt ),
.pipe_rx7_chanisaligned_gt ( pipe_rx7_chanisaligned_gt ),
.pipe_rx7_char_is_k_gt ( pipe_rx7_char_is_k_gt ),
.pipe_rx7_data_gt ( pipe_rx7_data_gt ),
.pipe_rx7_elec_idle_gt ( pipe_rx7_elec_idle_gt ),
.pipe_rx7_phy_status_gt ( pipe_rx7_phy_status_gt ),
.pipe_rx7_status_gt ( pipe_rx7_status_gt ),
.pipe_rx7_valid_gt ( pipe_rx7_valid_gt )
);
assign common_commands_out = 12'b0;
assign pipe_tx_0_sigs = 23'b0;
assign pipe_tx_1_sigs = 23'b0;
assign pipe_tx_2_sigs = 23'b0;
assign pipe_tx_3_sigs = 23'b0;
assign pipe_tx_4_sigs = 23'b0;
assign pipe_tx_5_sigs = 23'b0;
assign pipe_tx_6_sigs = 23'b0;
assign pipe_tx_7_sigs = 23'b0;
//------------------------------------------------------------------------------------------------------------------//
// **** V7/K7/A7 GTX Wrapper **** //
// The 7-Series GTX Wrapper includes the following: //
// 1) Virtex-7 GTX //
// 2) Kintex-7 GTX //
// 3) Artix-7 GTP //
//------------------------------------------------------------------------------------------------------------------//
PCIeGen2x8If128_gt_top #(
.LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
.REF_CLK_FREQ ( REF_CLK_FREQ ),
.USER_CLK_FREQ ( USER_CLK_FREQ ),
.USER_CLK2_DIV2 ( USER_CLK2_DIV2 ),
// synthesis translate_off
.PL_FAST_TRAIN ( ENABLE_FAST_SIM_TRAINING ),
// synthesis translate_on
.PCIE_EXT_CLK ( PCIE_EXT_CLK ),
.PCIE_USE_MODE ( PCIE_USE_MODE ),
.PCIE_GT_DEVICE ( PCIE_GT_DEVICE ),
.PCIE_PLL_SEL ( PCIE_PLL_SEL ),
.PCIE_ASYNC_EN ( PCIE_ASYNC_EN ),
.PCIE_TXBUF_EN ( PCIE_TXBUF_EN ),
.PCIE_EXT_GT_COMMON ( PCIE_EXT_GT_COMMON ),
.EXT_CH_GT_DRP ( EXT_CH_GT_DRP ),
.TX_MARGIN_FULL_0 ( TX_MARGIN_FULL_0 ),
.TX_MARGIN_FULL_1 ( TX_MARGIN_FULL_1 ),
.TX_MARGIN_FULL_2 ( TX_MARGIN_FULL_2 ),
.TX_MARGIN_FULL_3 ( TX_MARGIN_FULL_3 ),
.TX_MARGIN_FULL_4 ( TX_MARGIN_FULL_4 ),
.TX_MARGIN_LOW_0 ( TX_MARGIN_LOW_0 ),
.TX_MARGIN_LOW_1 ( TX_MARGIN_LOW_1 ),
.TX_MARGIN_LOW_2 ( TX_MARGIN_LOW_2 ),
.TX_MARGIN_LOW_3 ( TX_MARGIN_LOW_3 ),
.TX_MARGIN_LOW_4 ( TX_MARGIN_LOW_4 ),
.PCIE_CHAN_BOND ( PCIE_CHAN_BOND )
) gt_top_i (
// pl ltssm
.pl_ltssm_state ( pl_ltssm_state_int ),
// Pipe Common Signals
.pipe_tx_rcvr_det ( pipe_tx_rcvr_det_gt ),
.pipe_tx_reset ( 1'b0 ),
.pipe_tx_rate ( pipe_tx_rate_gt ),
.pipe_tx_deemph ( pipe_tx_deemph_gt ),
.pipe_tx_margin ( pipe_tx_margin_gt ),
.pipe_tx_swing ( 1'b0 ),
// Pipe Per-Lane Signals - Lane 0
.pipe_rx0_char_is_k ( pipe_rx0_char_is_k_gt),
.pipe_rx0_data ( pipe_rx0_data_gt ),
.pipe_rx0_valid ( pipe_rx0_valid_gt ),
.pipe_rx0_chanisaligned ( pipe_rx0_chanisaligned_gt ),
.pipe_rx0_status ( pipe_rx0_status_gt ),
.pipe_rx0_phy_status ( pipe_rx0_phy_status_gt ),
.pipe_rx0_elec_idle ( pipe_rx0_elec_idle_gt ),
.pipe_rx0_polarity ( pipe_rx0_polarity_gt ),
.pipe_tx0_compliance ( pipe_tx0_compliance_gt ),
.pipe_tx0_char_is_k ( pipe_tx0_char_is_k_gt ),
.pipe_tx0_data ( pipe_tx0_data_gt ),
.pipe_tx0_elec_idle ( pipe_tx0_elec_idle_gt ),
.pipe_tx0_powerdown ( pipe_tx0_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 1
.pipe_rx1_char_is_k ( pipe_rx1_char_is_k_gt),
.pipe_rx1_data ( pipe_rx1_data_gt ),
.pipe_rx1_valid ( pipe_rx1_valid_gt ),
.pipe_rx1_chanisaligned ( pipe_rx1_chanisaligned_gt ),
.pipe_rx1_status ( pipe_rx1_status_gt ),
.pipe_rx1_phy_status ( pipe_rx1_phy_status_gt ),
.pipe_rx1_elec_idle ( pipe_rx1_elec_idle_gt ),
.pipe_rx1_polarity ( pipe_rx1_polarity_gt ),
.pipe_tx1_compliance ( pipe_tx1_compliance_gt ),
.pipe_tx1_char_is_k ( pipe_tx1_char_is_k_gt ),
.pipe_tx1_data ( pipe_tx1_data_gt ),
.pipe_tx1_elec_idle ( pipe_tx1_elec_idle_gt ),
.pipe_tx1_powerdown ( pipe_tx1_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 2
.pipe_rx2_char_is_k ( pipe_rx2_char_is_k_gt),
.pipe_rx2_data ( pipe_rx2_data_gt ),
.pipe_rx2_valid ( pipe_rx2_valid_gt ),
.pipe_rx2_chanisaligned ( pipe_rx2_chanisaligned_gt ),
.pipe_rx2_status ( pipe_rx2_status_gt ),
.pipe_rx2_phy_status ( pipe_rx2_phy_status_gt ),
.pipe_rx2_elec_idle ( pipe_rx2_elec_idle_gt ),
.pipe_rx2_polarity ( pipe_rx2_polarity_gt ),
.pipe_tx2_compliance ( pipe_tx2_compliance_gt ),
.pipe_tx2_char_is_k ( pipe_tx2_char_is_k_gt ),
.pipe_tx2_data ( pipe_tx2_data_gt ),
.pipe_tx2_elec_idle ( pipe_tx2_elec_idle_gt ),
.pipe_tx2_powerdown ( pipe_tx2_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 3
.pipe_rx3_char_is_k ( pipe_rx3_char_is_k_gt),
.pipe_rx3_data ( pipe_rx3_data_gt ),
.pipe_rx3_valid ( pipe_rx3_valid_gt ),
.pipe_rx3_chanisaligned ( pipe_rx3_chanisaligned_gt ),
.pipe_rx3_status ( pipe_rx3_status_gt ),
.pipe_rx3_phy_status ( pipe_rx3_phy_status_gt ),
.pipe_rx3_elec_idle ( pipe_rx3_elec_idle_gt ),
.pipe_rx3_polarity ( pipe_rx3_polarity_gt ),
.pipe_tx3_compliance ( pipe_tx3_compliance_gt ),
.pipe_tx3_char_is_k ( pipe_tx3_char_is_k_gt ),
.pipe_tx3_data ( pipe_tx3_data_gt ),
.pipe_tx3_elec_idle ( pipe_tx3_elec_idle_gt ),
.pipe_tx3_powerdown ( pipe_tx3_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 4
.pipe_rx4_char_is_k ( pipe_rx4_char_is_k_gt),
.pipe_rx4_data ( pipe_rx4_data_gt ),
.pipe_rx4_valid ( pipe_rx4_valid_gt ),
.pipe_rx4_chanisaligned ( pipe_rx4_chanisaligned_gt ),
.pipe_rx4_status ( pipe_rx4_status_gt ),
.pipe_rx4_phy_status ( pipe_rx4_phy_status_gt ),
.pipe_rx4_elec_idle ( pipe_rx4_elec_idle_gt ),
.pipe_rx4_polarity ( pipe_rx4_polarity_gt ),
.pipe_tx4_compliance ( pipe_tx4_compliance_gt ),
.pipe_tx4_char_is_k ( pipe_tx4_char_is_k_gt ),
.pipe_tx4_data ( pipe_tx4_data_gt ),
.pipe_tx4_elec_idle ( pipe_tx4_elec_idle_gt ),
.pipe_tx4_powerdown ( pipe_tx4_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 5
.pipe_rx5_char_is_k ( pipe_rx5_char_is_k_gt),
.pipe_rx5_data ( pipe_rx5_data_gt ),
.pipe_rx5_valid ( pipe_rx5_valid_gt ),
.pipe_rx5_chanisaligned ( pipe_rx5_chanisaligned_gt ),
.pipe_rx5_status ( pipe_rx5_status_gt ),
.pipe_rx5_phy_status ( pipe_rx5_phy_status_gt ),
.pipe_rx5_elec_idle ( pipe_rx5_elec_idle_gt ),
.pipe_rx5_polarity ( pipe_rx5_polarity_gt ),
.pipe_tx5_compliance ( pipe_tx5_compliance_gt ),
.pipe_tx5_char_is_k ( pipe_tx5_char_is_k_gt ),
.pipe_tx5_data ( pipe_tx5_data_gt ),
.pipe_tx5_elec_idle ( pipe_tx5_elec_idle_gt ),
.pipe_tx5_powerdown ( pipe_tx5_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 6
.pipe_rx6_char_is_k ( pipe_rx6_char_is_k_gt),
.pipe_rx6_data ( pipe_rx6_data_gt ),
.pipe_rx6_valid ( pipe_rx6_valid_gt ),
.pipe_rx6_chanisaligned ( pipe_rx6_chanisaligned_gt ),
.pipe_rx6_status ( pipe_rx6_status_gt ),
.pipe_rx6_phy_status ( pipe_rx6_phy_status_gt ),
.pipe_rx6_elec_idle ( pipe_rx6_elec_idle_gt ),
.pipe_rx6_polarity ( pipe_rx6_polarity_gt ),
.pipe_tx6_compliance ( pipe_tx6_compliance_gt ),
.pipe_tx6_char_is_k ( pipe_tx6_char_is_k_gt ),
.pipe_tx6_data ( pipe_tx6_data_gt ),
.pipe_tx6_elec_idle ( pipe_tx6_elec_idle_gt ),
.pipe_tx6_powerdown ( pipe_tx6_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 7
.pipe_rx7_char_is_k ( pipe_rx7_char_is_k_gt),
.pipe_rx7_data ( pipe_rx7_data_gt ),
.pipe_rx7_valid ( pipe_rx7_valid_gt ),
.pipe_rx7_chanisaligned ( pipe_rx7_chanisaligned_gt ),
.pipe_rx7_status ( pipe_rx7_status_gt ),
.pipe_rx7_phy_status ( pipe_rx7_phy_status_gt ),
.pipe_rx7_elec_idle ( pipe_rx7_elec_idle_gt ),
.pipe_rx7_polarity ( pipe_rx7_polarity_gt ),
.pipe_tx7_compliance ( pipe_tx7_compliance_gt ),
.pipe_tx7_char_is_k ( pipe_tx7_char_is_k_gt ),
.pipe_tx7_data ( pipe_tx7_data_gt ),
.pipe_tx7_elec_idle ( pipe_tx7_elec_idle_gt ),
.pipe_tx7_powerdown ( pipe_tx7_powerdown_gt ),
// PCI Express Signals
.pci_exp_txn ( pci_exp_txn ),
.pci_exp_txp ( pci_exp_txp ),
.pci_exp_rxn ( pci_exp_rxn ),
.pci_exp_rxp ( pci_exp_rxp ),
// Non PIPE Signals
.sys_clk ( sys_clk ),
.sys_rst_n ( sys_rst_n ),
.PIPE_MMCM_RST_N ( pipe_mmcm_rst_n ), // Async | Async
.pipe_clk ( pipe_clk ),
.user_clk ( user_clk ),
.user_clk2 ( user_clk2 ),
.phy_rdy_n ( phy_rdy_n ),
// ---------- Shared Logic Internal------------------
.INT_PCLK_OUT_SLAVE ( int_pclk_out_slave ),
.INT_RXUSRCLK_OUT ( int_pipe_rxusrclk_out ),
.INT_RXOUTCLK_OUT ( int_rxoutclk_out ),
.INT_DCLK_OUT ( int_dclk_out ),
.INT_USERCLK1_OUT ( int_userclk1_out ),
.INT_USERCLK2_OUT ( int_userclk2_out),
.INT_OOBCLK_OUT ( int_oobclk_out),
.INT_MMCM_LOCK_OUT ( int_mmcm_lock_out ),
.INT_QPLLLOCK_OUT ( int_qplllock_out ),
.INT_QPLLOUTCLK_OUT ( int_qplloutclk_out ),
.INT_QPLLOUTREFCLK_OUT ( int_qplloutrefclk_out ),
.INT_PCLK_SEL_SLAVE ( int_pclk_sel_slave ),
// ---------- Shared Logic External------------------
//External Clock Ports
.PIPE_PCLK_IN ( pipe_pclk_in ),
.PIPE_RXUSRCLK_IN ( pipe_rxusrclk_in ),
.PIPE_RXOUTCLK_IN ( pipe_rxoutclk_in ),
.PIPE_DCLK_IN ( pipe_dclk_in ),
.PIPE_USERCLK1_IN ( pipe_userclk1_in ),
.PIPE_USERCLK2_IN ( pipe_userclk2_in ),
.PIPE_OOBCLK_IN ( pipe_oobclk_in ),
.PIPE_MMCM_LOCK_IN ( pipe_mmcm_lock_in ),
.PIPE_TXOUTCLK_OUT ( pipe_txoutclk_out ),
.PIPE_RXOUTCLK_OUT ( pipe_rxoutclk_out ),
.PIPE_PCLK_SEL_OUT ( pipe_pclk_sel_out ),
.PIPE_GEN3_OUT ( pipe_gen3_out ),
//External GT COMMON Ports
.qpll_drp_crscode ( qpll_drp_crscode ),
.qpll_drp_fsm ( qpll_drp_fsm ),
.qpll_drp_done ( qpll_drp_done ),
.qpll_drp_reset ( qpll_drp_reset ),
.qpll_qplllock ( qpll_qplllock ),
.qpll_qplloutclk ( qpll_qplloutclk ),
.qpll_qplloutrefclk ( qpll_qplloutrefclk ),
.qpll_qplld ( qpll_qplld ),
.qpll_qpllreset ( qpll_qpllreset ),
.qpll_drp_clk ( qpll_drp_clk ),
.qpll_drp_rst_n ( qpll_drp_rst_n ),
.qpll_drp_ovrd ( qpll_drp_ovrd ),
.qpll_drp_gen3 ( qpll_drp_gen3),
.qpll_drp_start ( qpll_drp_start ),
//TRANSCEIVER DEBUG EOU
.ext_ch_gt_drpclk ( ext_ch_gt_drpclk ),
.ext_ch_gt_drpaddr ( ext_ch_gt_drpaddr ),
.ext_ch_gt_drpen ( ext_ch_gt_drpen ),
.ext_ch_gt_drpdi ( ext_ch_gt_drpdi ),
.ext_ch_gt_drpwe ( ext_ch_gt_drpwe ),
.ext_ch_gt_drpdo ( ext_ch_gt_drpdo ),
.ext_ch_gt_drprdy ( ext_ch_gt_drprdy ),
//---------- PRBS/Loopback Ports -----------------------
.PIPE_TXPRBSSEL ( pipe_txprbssel ),
.PIPE_RXPRBSSEL ( pipe_rxprbssel ),
.PIPE_TXPRBSFORCEERR ( pipe_txprbsforceerr ),
.PIPE_RXPRBSCNTRESET ( pipe_rxprbscntreset ),
.PIPE_LOOPBACK ( pipe_loopback ),
.PIPE_RXPRBSERR ( pipe_rxprbserr ),
.PIPE_TXINHIBIT ( pipe_txinhibit ),
//---------- Transceiver Debug FSM Ports ---------------------------------
.PIPE_RST_FSM ( pipe_rst_fsm ),
.PIPE_QRST_FSM ( pipe_qrst_fsm ),
.PIPE_RATE_FSM ( pipe_rate_fsm ),
.PIPE_SYNC_FSM_TX ( pipe_sync_fsm_tx ),
.PIPE_SYNC_FSM_RX ( pipe_sync_fsm_rx ),
.PIPE_DRP_FSM ( pipe_drp_fsm ),
.PIPE_RST_IDLE ( pipe_rst_idle ),
.PIPE_QRST_IDLE ( pipe_qrst_idle ),
.PIPE_RATE_IDLE ( pipe_rate_idle ),
.PIPE_EYESCANDATAERROR ( pipe_eyescandataerror ),
.PIPE_RXSTATUS ( pipe_rxstatus ),
.PIPE_DMONITOROUT ( pipe_dmonitorout ),
.PIPE_CPLL_LOCK ( pipe_cpll_lock ),
.PIPE_QPLL_LOCK ( pipe_qpll_lock ),
.PIPE_RXPMARESETDONE ( pipe_rxpmaresetdone ),
.PIPE_RXBUFSTATUS ( pipe_rxbufstatus ),
.PIPE_TXPHALIGNDONE ( pipe_txphaligndone ),
.PIPE_TXPHINITDONE ( pipe_txphinitdone ),
.PIPE_TXDLYSRESETDONE ( pipe_txdlysresetdone ),
.PIPE_RXPHALIGNDONE ( pipe_rxphaligndone ),
.PIPE_RXDLYSRESETDONE ( pipe_rxdlysresetdone ),
.PIPE_RXSYNCDONE ( pipe_rxsyncdone ),
.PIPE_RXDISPERR ( pipe_rxdisperr ),
.PIPE_RXNOTINTABLE ( pipe_rxnotintable ),
.PIPE_RXCOMMADET ( pipe_rxcommadet ),
//---------- JTAG Ports --------------------------------
.PIPE_JTAG_RDY (gt_ch_drp_rdy ),
//---------- Debug Ports -------------------------------
.PIPE_DEBUG_0 ( pipe_debug_0 ),
.PIPE_DEBUG_1 ( pipe_debug_1 ),
.PIPE_DEBUG_2 ( pipe_debug_2 ),
.PIPE_DEBUG_3 ( pipe_debug_3 ),
.PIPE_DEBUG_4 ( pipe_debug_4 ),
.PIPE_DEBUG_5 ( pipe_debug_5 ),
.PIPE_DEBUG_6 ( pipe_debug_6 ),
.PIPE_DEBUG_7 ( pipe_debug_7 ),
.PIPE_DEBUG_8 ( pipe_debug_8 ),
.PIPE_DEBUG_9 ( pipe_debug_9 ),
.PIPE_DEBUG ( pipe_debug )
);
assign common_commands_out = 12'b0;
assign pipe_tx_0_sigs = 23'b0;
assign pipe_tx_1_sigs = 23'b0;
assign pipe_tx_2_sigs = 23'b0;
assign pipe_tx_3_sigs = 23'b0;
assign pipe_tx_4_sigs = 23'b0;
assign pipe_tx_5_sigs = 23'b0;
assign pipe_tx_6_sigs = 23'b0;
assign pipe_tx_7_sigs = 23'b0;
//------------------------------------------------------------------------------------------------------------------//
// Tie-Off Unused Tandem Outputs
assign icap_o = 32'b0;
assign startup_cfgclk = 1'b0;
assign startup_cfgmclk = 1'b0;
assign startup_eos = 1'b0;
assign startup_preq = 1'b0;
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
module reset_extender
#(parameter C_RST_COUNT = 10)
(input CLK,
input RST_BUS,
input RST_LOGIC,
output RST_OUT,
output PENDING_RST);
localparam C_CLOG2_RST_COUNT = clog2s(C_RST_COUNT);
localparam C_CEIL2_RST_COUNT = 1 << C_CLOG2_RST_COUNT;
localparam C_RST_SHIFTREG_DEPTH = 4;
wire [C_CLOG2_RST_COUNT:0] wRstCount;
wire [C_RST_SHIFTREG_DEPTH:0] wRstShiftReg;
assign PENDING_RST = wRstShiftReg != 0;
assign RST_OUT = wRstShiftReg[C_RST_SHIFTREG_DEPTH];
counter
#(// Parameters
.C_MAX_VALUE (C_CEIL2_RST_COUNT),
.C_SAT_VALUE (C_CEIL2_RST_COUNT),
.C_RST_VALUE (C_CEIL2_RST_COUNT - C_RST_COUNT)
/*AUTOINSTPARAM*/)
rst_counter
(// Outputs
.VALUE (wRstCount),
// Inputs
.ENABLE (1'b1),
.RST_IN (RST_BUS | RST_LOGIC),
/*AUTOINST*/
// Inputs
.CLK (CLK));
shiftreg
#(// Parameters
.C_DEPTH (C_RST_SHIFTREG_DEPTH),
.C_WIDTH (1),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
rst_shiftreg
(// Outputs
.RD_DATA (wRstShiftReg),
// Inputs
.RST_IN (0),
.WR_DATA (~wRstCount[C_CLOG2_RST_COUNT]),
/*AUTOINST*/
// Inputs
.CLK (CLK));
endmodule
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7:5.5
// IP Revision: 0
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2014.4" *)
(* CHECK_LICENSE_TYPE = "design_1_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *)
(* CORE_GENERATION_INFO = "design_1_processing_system7_0_0,processing_system7_v5_5_processing_system7,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=processing_system7,x_ipVersion=5.5,x_ipCoreRevision=0,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_EN_EMIO_PJTAG=0,C_EN_EMIO_ENET0=0,C_EN_EMIO_ENET1=0,C_EN_EMIO_TRACE=0,C_INCLUDE_TRACE_BUFFER=0,C_TRACE_BUFFER_FIFO_SIZE=128,USE_TRACE_DATA_EDGE_DETECTOR=0,C_TRACE_PIPELINE_WIDTH=8,C_TRACE_BUFFER_CLOCK_DELAY=12,C_EMIO_GPIO_WIDTH=64,C_INCLUDE_ACP_TRANS_CHECK=0,C_USE_DEFAULT_ACP_USER_VAL=0,C_S_AXI_ACP_ARUSER_VAL=31,C_S_AXI_ACP_AWUSER_VAL=31,C_M_AXI_GP0_ID_WIDTH=12,C_M_AXI_GP0_ENABLE_STATIC_REMAP=0,C_M_AXI_GP1_ID_WIDTH=12,C_M_AXI_GP1_ENABLE_STATIC_REMAP=0,C_S_AXI_GP0_ID_WIDTH=6,C_S_AXI_GP1_ID_WIDTH=6,C_S_AXI_ACP_ID_WIDTH=3,C_S_AXI_HP0_ID_WIDTH=6,C_S_AXI_HP0_DATA_WIDTH=64,C_S_AXI_HP1_ID_WIDTH=6,C_S_AXI_HP1_DATA_WIDTH=64,C_S_AXI_HP2_ID_WIDTH=6,C_S_AXI_HP2_DATA_WIDTH=64,C_S_AXI_HP3_ID_WIDTH=6,C_S_AXI_HP3_DATA_WIDTH=64,C_M_AXI_GP0_THREAD_ID_WIDTH=12,C_M_AXI_GP1_THREAD_ID_WIDTH=12,C_NUM_F2P_INTR_INPUTS=2,C_IRQ_F2P_MODE=DIRECT,C_DQ_WIDTH=32,C_DQS_WIDTH=4,C_DM_WIDTH=4,C_MIO_PRIMITIVE=54,C_TRACE_INTERNAL_WIDTH=2,C_PS7_SI_REV=PRODUCTION,C_FCLK_CLK0_BUF=true,C_FCLK_CLK1_BUF=true,C_FCLK_CLK2_BUF=false,C_FCLK_CLK3_BUF=false,C_PACKAGE_NAME=clg400}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_processing_system7_0_0 (
ENET0_PTP_DELAY_REQ_RX,
ENET0_PTP_DELAY_REQ_TX,
ENET0_PTP_PDELAY_REQ_RX,
ENET0_PTP_PDELAY_REQ_TX,
ENET0_PTP_PDELAY_RESP_RX,
ENET0_PTP_PDELAY_RESP_TX,
ENET0_PTP_SYNC_FRAME_RX,
ENET0_PTP_SYNC_FRAME_TX,
ENET0_SOF_RX,
ENET0_SOF_TX,
I2C0_SDA_I,
I2C0_SDA_O,
I2C0_SDA_T,
I2C0_SCL_I,
I2C0_SCL_O,
I2C0_SCL_T,
SDIO0_WP,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
S_AXI_HP0_ARREADY,
S_AXI_HP0_AWREADY,
S_AXI_HP0_BVALID,
S_AXI_HP0_RLAST,
S_AXI_HP0_RVALID,
S_AXI_HP0_WREADY,
S_AXI_HP0_BRESP,
S_AXI_HP0_RRESP,
S_AXI_HP0_BID,
S_AXI_HP0_RID,
S_AXI_HP0_RDATA,
S_AXI_HP0_RCOUNT,
S_AXI_HP0_WCOUNT,
S_AXI_HP0_RACOUNT,
S_AXI_HP0_WACOUNT,
S_AXI_HP0_ACLK,
S_AXI_HP0_ARVALID,
S_AXI_HP0_AWVALID,
S_AXI_HP0_BREADY,
S_AXI_HP0_RDISSUECAP1_EN,
S_AXI_HP0_RREADY,
S_AXI_HP0_WLAST,
S_AXI_HP0_WRISSUECAP1_EN,
S_AXI_HP0_WVALID,
S_AXI_HP0_ARBURST,
S_AXI_HP0_ARLOCK,
S_AXI_HP0_ARSIZE,
S_AXI_HP0_AWBURST,
S_AXI_HP0_AWLOCK,
S_AXI_HP0_AWSIZE,
S_AXI_HP0_ARPROT,
S_AXI_HP0_AWPROT,
S_AXI_HP0_ARADDR,
S_AXI_HP0_AWADDR,
S_AXI_HP0_ARCACHE,
S_AXI_HP0_ARLEN,
S_AXI_HP0_ARQOS,
S_AXI_HP0_AWCACHE,
S_AXI_HP0_AWLEN,
S_AXI_HP0_AWQOS,
S_AXI_HP0_ARID,
S_AXI_HP0_AWID,
S_AXI_HP0_WID,
S_AXI_HP0_WDATA,
S_AXI_HP0_WSTRB,
IRQ_F2P,
FCLK_CLK0,
FCLK_CLK1,
FCLK_RESET0_N,
FCLK_RESET1_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 DELAY_REQ_RX" *)
output wire ENET0_PTP_DELAY_REQ_RX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 DELAY_REQ_TX" *)
output wire ENET0_PTP_DELAY_REQ_TX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 PDELAY_REQ_RX" *)
output wire ENET0_PTP_PDELAY_REQ_RX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 PDELAY_REQ_TX" *)
output wire ENET0_PTP_PDELAY_REQ_TX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 PDELAY_RESP_RX" *)
output wire ENET0_PTP_PDELAY_RESP_RX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 PDELAY_RESP_TX" *)
output wire ENET0_PTP_PDELAY_RESP_TX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 SYNC_FRAME_RX" *)
output wire ENET0_PTP_SYNC_FRAME_RX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 SYNC_FRAME_TX" *)
output wire ENET0_PTP_SYNC_FRAME_TX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 SOF_RX" *)
output wire ENET0_SOF_RX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 SOF_TX" *)
output wire ENET0_SOF_TX;
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SDA_I" *)
input wire I2C0_SDA_I;
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SDA_O" *)
output wire I2C0_SDA_O;
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SDA_T" *)
output wire I2C0_SDA_T;
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SCL_I" *)
input wire I2C0_SCL_I;
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SCL_O" *)
output wire I2C0_SCL_O;
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SCL_T" *)
output wire I2C0_SCL_T;
(* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 WP" *)
input wire SDIO0_WP;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *)
output wire [1 : 0] USB0_PORT_INDCTL;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *)
output wire USB0_VBUS_PWRSELECT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *)
input wire USB0_VBUS_PWRFAULT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *)
output wire M_AXI_GP0_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *)
output wire M_AXI_GP0_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *)
output wire M_AXI_GP0_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *)
output wire M_AXI_GP0_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *)
output wire M_AXI_GP0_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *)
output wire M_AXI_GP0_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *)
output wire [11 : 0] M_AXI_GP0_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *)
output wire [11 : 0] M_AXI_GP0_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *)
output wire [11 : 0] M_AXI_GP0_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *)
output wire [1 : 0] M_AXI_GP0_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *)
output wire [1 : 0] M_AXI_GP0_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *)
output wire [2 : 0] M_AXI_GP0_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *)
output wire [1 : 0] M_AXI_GP0_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *)
output wire [1 : 0] M_AXI_GP0_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *)
output wire [2 : 0] M_AXI_GP0_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *)
output wire [2 : 0] M_AXI_GP0_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *)
output wire [2 : 0] M_AXI_GP0_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *)
output wire [31 : 0] M_AXI_GP0_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *)
output wire [31 : 0] M_AXI_GP0_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *)
output wire [31 : 0] M_AXI_GP0_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *)
output wire [3 : 0] M_AXI_GP0_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *)
output wire [3 : 0] M_AXI_GP0_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *)
output wire [3 : 0] M_AXI_GP0_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *)
output wire [3 : 0] M_AXI_GP0_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *)
output wire [3 : 0] M_AXI_GP0_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *)
output wire [3 : 0] M_AXI_GP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *)
output wire [3 : 0] M_AXI_GP0_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *)
input wire M_AXI_GP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *)
input wire M_AXI_GP0_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *)
input wire M_AXI_GP0_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *)
input wire M_AXI_GP0_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *)
input wire M_AXI_GP0_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *)
input wire M_AXI_GP0_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *)
input wire M_AXI_GP0_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *)
input wire [11 : 0] M_AXI_GP0_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *)
input wire [11 : 0] M_AXI_GP0_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *)
input wire [1 : 0] M_AXI_GP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *)
input wire [1 : 0] M_AXI_GP0_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *)
input wire [31 : 0] M_AXI_GP0_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARREADY" *)
output wire S_AXI_HP0_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWREADY" *)
output wire S_AXI_HP0_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 BVALID" *)
output wire S_AXI_HP0_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RLAST" *)
output wire S_AXI_HP0_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RVALID" *)
output wire S_AXI_HP0_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WREADY" *)
output wire S_AXI_HP0_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 BRESP" *)
output wire [1 : 0] S_AXI_HP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RRESP" *)
output wire [1 : 0] S_AXI_HP0_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 BID" *)
output wire [5 : 0] S_AXI_HP0_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RID" *)
output wire [5 : 0] S_AXI_HP0_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RDATA" *)
output wire [63 : 0] S_AXI_HP0_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL RCOUNT" *)
output wire [7 : 0] S_AXI_HP0_RCOUNT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL WCOUNT" *)
output wire [7 : 0] S_AXI_HP0_WCOUNT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL RACOUNT" *)
output wire [2 : 0] S_AXI_HP0_RACOUNT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL WACOUNT" *)
output wire [5 : 0] S_AXI_HP0_WACOUNT;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S_AXI_HP0_ACLK CLK" *)
input wire S_AXI_HP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARVALID" *)
input wire S_AXI_HP0_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWVALID" *)
input wire S_AXI_HP0_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 BREADY" *)
input wire S_AXI_HP0_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL RDISSUECAPEN" *)
input wire S_AXI_HP0_RDISSUECAP1_EN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RREADY" *)
input wire S_AXI_HP0_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WLAST" *)
input wire S_AXI_HP0_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL WRISSUECAPEN" *)
input wire S_AXI_HP0_WRISSUECAP1_EN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WVALID" *)
input wire S_AXI_HP0_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARBURST" *)
input wire [1 : 0] S_AXI_HP0_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARLOCK" *)
input wire [1 : 0] S_AXI_HP0_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARSIZE" *)
input wire [2 : 0] S_AXI_HP0_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWBURST" *)
input wire [1 : 0] S_AXI_HP0_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWLOCK" *)
input wire [1 : 0] S_AXI_HP0_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWSIZE" *)
input wire [2 : 0] S_AXI_HP0_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARPROT" *)
input wire [2 : 0] S_AXI_HP0_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWPROT" *)
input wire [2 : 0] S_AXI_HP0_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARADDR" *)
input wire [31 : 0] S_AXI_HP0_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWADDR" *)
input wire [31 : 0] S_AXI_HP0_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARCACHE" *)
input wire [3 : 0] S_AXI_HP0_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARLEN" *)
input wire [3 : 0] S_AXI_HP0_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARQOS" *)
input wire [3 : 0] S_AXI_HP0_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWCACHE" *)
input wire [3 : 0] S_AXI_HP0_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWLEN" *)
input wire [3 : 0] S_AXI_HP0_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWQOS" *)
input wire [3 : 0] S_AXI_HP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARID" *)
input wire [5 : 0] S_AXI_HP0_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWID" *)
input wire [5 : 0] S_AXI_HP0_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WID" *)
input wire [5 : 0] S_AXI_HP0_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WDATA" *)
input wire [63 : 0] S_AXI_HP0_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WSTRB" *)
input wire [7 : 0] S_AXI_HP0_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT" *)
input wire [1 : 0] IRQ_F2P;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *)
output wire FCLK_CLK0;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK1 CLK" *)
output wire FCLK_CLK1;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *)
output wire FCLK_RESET0_N;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET1_N RST" *)
output wire FCLK_RESET1_N;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *)
inout wire [53 : 0] MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *)
inout wire DDR_CAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *)
inout wire DDR_CKE;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *)
inout wire DDR_Clk_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *)
inout wire DDR_Clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *)
inout wire DDR_CS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *)
inout wire DDR_DRSTB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *)
inout wire DDR_ODT;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *)
inout wire DDR_RAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *)
inout wire DDR_WEB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *)
inout wire [2 : 0] DDR_BankAddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *)
inout wire [14 : 0] DDR_Addr;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *)
inout wire DDR_VRN;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *)
inout wire DDR_VRP;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *)
inout wire [3 : 0] DDR_DM;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *)
inout wire [31 : 0] DDR_DQ;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *)
inout wire [3 : 0] DDR_DQS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *)
inout wire [3 : 0] DDR_DQS;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *)
inout wire PS_SRSTB;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *)
inout wire PS_CLK;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *)
inout wire PS_PORB;
processing_system7_v5_5_processing_system7 #(
.C_EN_EMIO_PJTAG(0),
.C_EN_EMIO_ENET0(0),
.C_EN_EMIO_ENET1(0),
.C_EN_EMIO_TRACE(0),
.C_INCLUDE_TRACE_BUFFER(0),
.C_TRACE_BUFFER_FIFO_SIZE(128),
.USE_TRACE_DATA_EDGE_DETECTOR(0),
.C_TRACE_PIPELINE_WIDTH(8),
.C_TRACE_BUFFER_CLOCK_DELAY(12),
.C_EMIO_GPIO_WIDTH(64),
.C_INCLUDE_ACP_TRANS_CHECK(0),
.C_USE_DEFAULT_ACP_USER_VAL(0),
.C_S_AXI_ACP_ARUSER_VAL(31),
.C_S_AXI_ACP_AWUSER_VAL(31),
.C_M_AXI_GP0_ID_WIDTH(12),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP1_ID_WIDTH(12),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
.C_S_AXI_GP0_ID_WIDTH(6),
.C_S_AXI_GP1_ID_WIDTH(6),
.C_S_AXI_ACP_ID_WIDTH(3),
.C_S_AXI_HP0_ID_WIDTH(6),
.C_S_AXI_HP0_DATA_WIDTH(64),
.C_S_AXI_HP1_ID_WIDTH(6),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_ID_WIDTH(6),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_ID_WIDTH(6),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_M_AXI_GP0_THREAD_ID_WIDTH(12),
.C_M_AXI_GP1_THREAD_ID_WIDTH(12),
.C_NUM_F2P_INTR_INPUTS(2),
.C_IRQ_F2P_MODE("DIRECT"),
.C_DQ_WIDTH(32),
.C_DQS_WIDTH(4),
.C_DM_WIDTH(4),
.C_MIO_PRIMITIVE(54),
.C_TRACE_INTERNAL_WIDTH(2),
.C_PS7_SI_REV("PRODUCTION"),
.C_FCLK_CLK0_BUF("true"),
.C_FCLK_CLK1_BUF("true"),
.C_FCLK_CLK2_BUF("false"),
.C_FCLK_CLK3_BUF("false"),
.C_PACKAGE_NAME("clg400")
) inst (
.CAN0_PHY_TX(),
.CAN0_PHY_RX(1'B0),
.CAN1_PHY_TX(),
.CAN1_PHY_RX(1'B0),
.ENET0_GMII_TX_EN(),
.ENET0_GMII_TX_ER(),
.ENET0_MDIO_MDC(),
.ENET0_MDIO_O(),
.ENET0_MDIO_T(),
.ENET0_PTP_DELAY_REQ_RX(ENET0_PTP_DELAY_REQ_RX),
.ENET0_PTP_DELAY_REQ_TX(ENET0_PTP_DELAY_REQ_TX),
.ENET0_PTP_PDELAY_REQ_RX(ENET0_PTP_PDELAY_REQ_RX),
.ENET0_PTP_PDELAY_REQ_TX(ENET0_PTP_PDELAY_REQ_TX),
.ENET0_PTP_PDELAY_RESP_RX(ENET0_PTP_PDELAY_RESP_RX),
.ENET0_PTP_PDELAY_RESP_TX(ENET0_PTP_PDELAY_RESP_TX),
.ENET0_PTP_SYNC_FRAME_RX(ENET0_PTP_SYNC_FRAME_RX),
.ENET0_PTP_SYNC_FRAME_TX(ENET0_PTP_SYNC_FRAME_TX),
.ENET0_SOF_RX(ENET0_SOF_RX),
.ENET0_SOF_TX(ENET0_SOF_TX),
.ENET0_GMII_TXD(),
.ENET0_GMII_COL(1'B0),
.ENET0_GMII_CRS(1'B0),
.ENET0_GMII_RX_CLK(1'B0),
.ENET0_GMII_RX_DV(1'B0),
.ENET0_GMII_RX_ER(1'B0),
.ENET0_GMII_TX_CLK(1'B0),
.ENET0_MDIO_I(1'B0),
.ENET0_EXT_INTIN(1'B0),
.ENET0_GMII_RXD(8'B0),
.ENET1_GMII_TX_EN(),
.ENET1_GMII_TX_ER(),
.ENET1_MDIO_MDC(),
.ENET1_MDIO_O(),
.ENET1_MDIO_T(),
.ENET1_PTP_DELAY_REQ_RX(),
.ENET1_PTP_DELAY_REQ_TX(),
.ENET1_PTP_PDELAY_REQ_RX(),
.ENET1_PTP_PDELAY_REQ_TX(),
.ENET1_PTP_PDELAY_RESP_RX(),
.ENET1_PTP_PDELAY_RESP_TX(),
.ENET1_PTP_SYNC_FRAME_RX(),
.ENET1_PTP_SYNC_FRAME_TX(),
.ENET1_SOF_RX(),
.ENET1_SOF_TX(),
.ENET1_GMII_TXD(),
.ENET1_GMII_COL(1'B0),
.ENET1_GMII_CRS(1'B0),
.ENET1_GMII_RX_CLK(1'B0),
.ENET1_GMII_RX_DV(1'B0),
.ENET1_GMII_RX_ER(1'B0),
.ENET1_GMII_TX_CLK(1'B0),
.ENET1_MDIO_I(1'B0),
.ENET1_EXT_INTIN(1'B0),
.ENET1_GMII_RXD(8'B0),
.GPIO_I(64'B0),
.GPIO_O(),
.GPIO_T(),
.I2C0_SDA_I(I2C0_SDA_I),
.I2C0_SDA_O(I2C0_SDA_O),
.I2C0_SDA_T(I2C0_SDA_T),
.I2C0_SCL_I(I2C0_SCL_I),
.I2C0_SCL_O(I2C0_SCL_O),
.I2C0_SCL_T(I2C0_SCL_T),
.I2C1_SDA_I(1'B0),
.I2C1_SDA_O(),
.I2C1_SDA_T(),
.I2C1_SCL_I(1'B0),
.I2C1_SCL_O(),
.I2C1_SCL_T(),
.PJTAG_TCK(1'B0),
.PJTAG_TMS(1'B0),
.PJTAG_TDI(1'B0),
.PJTAG_TDO(),
.SDIO0_CLK(),
.SDIO0_CLK_FB(1'B0),
.SDIO0_CMD_O(),
.SDIO0_CMD_I(1'B0),
.SDIO0_CMD_T(),
.SDIO0_DATA_I(4'B0),
.SDIO0_DATA_O(),
.SDIO0_DATA_T(),
.SDIO0_LED(),
.SDIO0_CDN(1'B0),
.SDIO0_WP(SDIO0_WP),
.SDIO0_BUSPOW(),
.SDIO0_BUSVOLT(),
.SDIO1_CLK(),
.SDIO1_CLK_FB(1'B0),
.SDIO1_CMD_O(),
.SDIO1_CMD_I(1'B0),
.SDIO1_CMD_T(),
.SDIO1_DATA_I(4'B0),
.SDIO1_DATA_O(),
.SDIO1_DATA_T(),
.SDIO1_LED(),
.SDIO1_CDN(1'B0),
.SDIO1_WP(1'B0),
.SDIO1_BUSPOW(),
.SDIO1_BUSVOLT(),
.SPI0_SCLK_I(1'B0),
.SPI0_SCLK_O(),
.SPI0_SCLK_T(),
.SPI0_MOSI_I(1'B0),
.SPI0_MOSI_O(),
.SPI0_MOSI_T(),
.SPI0_MISO_I(1'B0),
.SPI0_MISO_O(),
.SPI0_MISO_T(),
.SPI0_SS_I(1'B0),
.SPI0_SS_O(),
.SPI0_SS1_O(),
.SPI0_SS2_O(),
.SPI0_SS_T(),
.SPI1_SCLK_I(1'B0),
.SPI1_SCLK_O(),
.SPI1_SCLK_T(),
.SPI1_MOSI_I(1'B0),
.SPI1_MOSI_O(),
.SPI1_MOSI_T(),
.SPI1_MISO_I(1'B0),
.SPI1_MISO_O(),
.SPI1_MISO_T(),
.SPI1_SS_I(1'B0),
.SPI1_SS_O(),
.SPI1_SS1_O(),
.SPI1_SS2_O(),
.SPI1_SS_T(),
.UART0_DTRN(),
.UART0_RTSN(),
.UART0_TX(),
.UART0_CTSN(1'B0),
.UART0_DCDN(1'B0),
.UART0_DSRN(1'B0),
.UART0_RIN(1'B0),
.UART0_RX(1'B1),
.UART1_DTRN(),
.UART1_RTSN(),
.UART1_TX(),
.UART1_CTSN(1'B0),
.UART1_DCDN(1'B0),
.UART1_DSRN(1'B0),
.UART1_RIN(1'B0),
.UART1_RX(1'B1),
.TTC0_WAVE0_OUT(),
.TTC0_WAVE1_OUT(),
.TTC0_WAVE2_OUT(),
.TTC0_CLK0_IN(1'B0),
.TTC0_CLK1_IN(1'B0),
.TTC0_CLK2_IN(1'B0),
.TTC1_WAVE0_OUT(),
.TTC1_WAVE1_OUT(),
.TTC1_WAVE2_OUT(),
.TTC1_CLK0_IN(1'B0),
.TTC1_CLK1_IN(1'B0),
.TTC1_CLK2_IN(1'B0),
.WDT_CLK_IN(1'B0),
.WDT_RST_OUT(),
.TRACE_CLK(1'B0),
.TRACE_CLK_OUT(),
.TRACE_CTL(),
.TRACE_DATA(),
.USB0_PORT_INDCTL(USB0_PORT_INDCTL),
.USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
.USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
.USB1_PORT_INDCTL(),
.USB1_VBUS_PWRSELECT(),
.USB1_VBUS_PWRFAULT(1'B0),
.SRAM_INTIN(1'B0),
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP1_ARVALID(),
.M_AXI_GP1_AWVALID(),
.M_AXI_GP1_BREADY(),
.M_AXI_GP1_RREADY(),
.M_AXI_GP1_WLAST(),
.M_AXI_GP1_WVALID(),
.M_AXI_GP1_ARID(),
.M_AXI_GP1_AWID(),
.M_AXI_GP1_WID(),
.M_AXI_GP1_ARBURST(),
.M_AXI_GP1_ARLOCK(),
.M_AXI_GP1_ARSIZE(),
.M_AXI_GP1_AWBURST(),
.M_AXI_GP1_AWLOCK(),
.M_AXI_GP1_AWSIZE(),
.M_AXI_GP1_ARPROT(),
.M_AXI_GP1_AWPROT(),
.M_AXI_GP1_ARADDR(),
.M_AXI_GP1_AWADDR(),
.M_AXI_GP1_WDATA(),
.M_AXI_GP1_ARCACHE(),
.M_AXI_GP1_ARLEN(),
.M_AXI_GP1_ARQOS(),
.M_AXI_GP1_AWCACHE(),
.M_AXI_GP1_AWLEN(),
.M_AXI_GP1_AWQOS(),
.M_AXI_GP1_WSTRB(),
.M_AXI_GP1_ACLK(1'B0),
.M_AXI_GP1_ARREADY(1'B0),
.M_AXI_GP1_AWREADY(1'B0),
.M_AXI_GP1_BVALID(1'B0),
.M_AXI_GP1_RLAST(1'B0),
.M_AXI_GP1_RVALID(1'B0),
.M_AXI_GP1_WREADY(1'B0),
.M_AXI_GP1_BID(12'B0),
.M_AXI_GP1_RID(12'B0),
.M_AXI_GP1_BRESP(2'B0),
.M_AXI_GP1_RRESP(2'B0),
.M_AXI_GP1_RDATA(32'B0),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(S_AXI_HP0_ARREADY),
.S_AXI_HP0_AWREADY(S_AXI_HP0_AWREADY),
.S_AXI_HP0_BVALID(S_AXI_HP0_BVALID),
.S_AXI_HP0_RLAST(S_AXI_HP0_RLAST),
.S_AXI_HP0_RVALID(S_AXI_HP0_RVALID),
.S_AXI_HP0_WREADY(S_AXI_HP0_WREADY),
.S_AXI_HP0_BRESP(S_AXI_HP0_BRESP),
.S_AXI_HP0_RRESP(S_AXI_HP0_RRESP),
.S_AXI_HP0_BID(S_AXI_HP0_BID),
.S_AXI_HP0_RID(S_AXI_HP0_RID),
.S_AXI_HP0_RDATA(S_AXI_HP0_RDATA),
.S_AXI_HP0_RCOUNT(S_AXI_HP0_RCOUNT),
.S_AXI_HP0_WCOUNT(S_AXI_HP0_WCOUNT),
.S_AXI_HP0_RACOUNT(S_AXI_HP0_RACOUNT),
.S_AXI_HP0_WACOUNT(S_AXI_HP0_WACOUNT),
.S_AXI_HP0_ACLK(S_AXI_HP0_ACLK),
.S_AXI_HP0_ARVALID(S_AXI_HP0_ARVALID),
.S_AXI_HP0_AWVALID(S_AXI_HP0_AWVALID),
.S_AXI_HP0_BREADY(S_AXI_HP0_BREADY),
.S_AXI_HP0_RDISSUECAP1_EN(S_AXI_HP0_RDISSUECAP1_EN),
.S_AXI_HP0_RREADY(S_AXI_HP0_RREADY),
.S_AXI_HP0_WLAST(S_AXI_HP0_WLAST),
.S_AXI_HP0_WRISSUECAP1_EN(S_AXI_HP0_WRISSUECAP1_EN),
.S_AXI_HP0_WVALID(S_AXI_HP0_WVALID),
.S_AXI_HP0_ARBURST(S_AXI_HP0_ARBURST),
.S_AXI_HP0_ARLOCK(S_AXI_HP0_ARLOCK),
.S_AXI_HP0_ARSIZE(S_AXI_HP0_ARSIZE),
.S_AXI_HP0_AWBURST(S_AXI_HP0_AWBURST),
.S_AXI_HP0_AWLOCK(S_AXI_HP0_AWLOCK),
.S_AXI_HP0_AWSIZE(S_AXI_HP0_AWSIZE),
.S_AXI_HP0_ARPROT(S_AXI_HP0_ARPROT),
.S_AXI_HP0_AWPROT(S_AXI_HP0_AWPROT),
.S_AXI_HP0_ARADDR(S_AXI_HP0_ARADDR),
.S_AXI_HP0_AWADDR(S_AXI_HP0_AWADDR),
.S_AXI_HP0_ARCACHE(S_AXI_HP0_ARCACHE),
.S_AXI_HP0_ARLEN(S_AXI_HP0_ARLEN),
.S_AXI_HP0_ARQOS(S_AXI_HP0_ARQOS),
.S_AXI_HP0_AWCACHE(S_AXI_HP0_AWCACHE),
.S_AXI_HP0_AWLEN(S_AXI_HP0_AWLEN),
.S_AXI_HP0_AWQOS(S_AXI_HP0_AWQOS),
.S_AXI_HP0_ARID(S_AXI_HP0_ARID),
.S_AXI_HP0_AWID(S_AXI_HP0_AWID),
.S_AXI_HP0_WID(S_AXI_HP0_WID),
.S_AXI_HP0_WDATA(S_AXI_HP0_WDATA),
.S_AXI_HP0_WSTRB(S_AXI_HP0_WSTRB),
.S_AXI_HP1_ARREADY(),
.S_AXI_HP1_AWREADY(),
.S_AXI_HP1_BVALID(),
.S_AXI_HP1_RLAST(),
.S_AXI_HP1_RVALID(),
.S_AXI_HP1_WREADY(),
.S_AXI_HP1_BRESP(),
.S_AXI_HP1_RRESP(),
.S_AXI_HP1_BID(),
.S_AXI_HP1_RID(),
.S_AXI_HP1_RDATA(),
.S_AXI_HP1_RCOUNT(),
.S_AXI_HP1_WCOUNT(),
.S_AXI_HP1_RACOUNT(),
.S_AXI_HP1_WACOUNT(),
.S_AXI_HP1_ACLK(1'B0),
.S_AXI_HP1_ARVALID(1'B0),
.S_AXI_HP1_AWVALID(1'B0),
.S_AXI_HP1_BREADY(1'B0),
.S_AXI_HP1_RDISSUECAP1_EN(1'B0),
.S_AXI_HP1_RREADY(1'B0),
.S_AXI_HP1_WLAST(1'B0),
.S_AXI_HP1_WRISSUECAP1_EN(1'B0),
.S_AXI_HP1_WVALID(1'B0),
.S_AXI_HP1_ARBURST(2'B0),
.S_AXI_HP1_ARLOCK(2'B0),
.S_AXI_HP1_ARSIZE(3'B0),
.S_AXI_HP1_AWBURST(2'B0),
.S_AXI_HP1_AWLOCK(2'B0),
.S_AXI_HP1_AWSIZE(3'B0),
.S_AXI_HP1_ARPROT(3'B0),
.S_AXI_HP1_AWPROT(3'B0),
.S_AXI_HP1_ARADDR(32'B0),
.S_AXI_HP1_AWADDR(32'B0),
.S_AXI_HP1_ARCACHE(4'B0),
.S_AXI_HP1_ARLEN(4'B0),
.S_AXI_HP1_ARQOS(4'B0),
.S_AXI_HP1_AWCACHE(4'B0),
.S_AXI_HP1_AWLEN(4'B0),
.S_AXI_HP1_AWQOS(4'B0),
.S_AXI_HP1_ARID(6'B0),
.S_AXI_HP1_AWID(6'B0),
.S_AXI_HP1_WID(6'B0),
.S_AXI_HP1_WDATA(64'B0),
.S_AXI_HP1_WSTRB(8'B0),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_RCOUNT(),
.S_AXI_HP2_WCOUNT(),
.S_AXI_HP2_RACOUNT(),
.S_AXI_HP2_WACOUNT(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RDISSUECAP1_EN(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WRISSUECAP1_EN(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_RCOUNT(),
.S_AXI_HP3_WCOUNT(),
.S_AXI_HP3_RACOUNT(),
.S_AXI_HP3_WACOUNT(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RDISSUECAP1_EN(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WRISSUECAP1_EN(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.IRQ_P2F_DMAC_ABORT(),
.IRQ_P2F_DMAC0(),
.IRQ_P2F_DMAC1(),
.IRQ_P2F_DMAC2(),
.IRQ_P2F_DMAC3(),
.IRQ_P2F_DMAC4(),
.IRQ_P2F_DMAC5(),
.IRQ_P2F_DMAC6(),
.IRQ_P2F_DMAC7(),
.IRQ_P2F_SMC(),
.IRQ_P2F_QSPI(),
.IRQ_P2F_CTI(),
.IRQ_P2F_GPIO(),
.IRQ_P2F_USB0(),
.IRQ_P2F_ENET0(),
.IRQ_P2F_ENET_WAKE0(),
.IRQ_P2F_SDIO0(),
.IRQ_P2F_I2C0(),
.IRQ_P2F_SPI0(),
.IRQ_P2F_UART0(),
.IRQ_P2F_CAN0(),
.IRQ_P2F_USB1(),
.IRQ_P2F_ENET1(),
.IRQ_P2F_ENET_WAKE1(),
.IRQ_P2F_SDIO1(),
.IRQ_P2F_I2C1(),
.IRQ_P2F_SPI1(),
.IRQ_P2F_UART1(),
.IRQ_P2F_CAN1(),
.IRQ_F2P(IRQ_F2P),
.Core0_nFIQ(1'B0),
.Core0_nIRQ(1'B0),
.Core1_nFIQ(1'B0),
.Core1_nIRQ(1'B0),
.DMA0_DATYPE(),
.DMA0_DAVALID(),
.DMA0_DRREADY(),
.DMA1_DATYPE(),
.DMA1_DAVALID(),
.DMA1_DRREADY(),
.DMA2_DATYPE(),
.DMA2_DAVALID(),
.DMA2_DRREADY(),
.DMA3_DATYPE(),
.DMA3_DAVALID(),
.DMA3_DRREADY(),
.DMA0_ACLK(1'B0),
.DMA0_DAREADY(1'B0),
.DMA0_DRLAST(1'B0),
.DMA0_DRVALID(1'B0),
.DMA1_ACLK(1'B0),
.DMA1_DAREADY(1'B0),
.DMA1_DRLAST(1'B0),
.DMA1_DRVALID(1'B0),
.DMA2_ACLK(1'B0),
.DMA2_DAREADY(1'B0),
.DMA2_DRLAST(1'B0),
.DMA2_DRVALID(1'B0),
.DMA3_ACLK(1'B0),
.DMA3_DAREADY(1'B0),
.DMA3_DRLAST(1'B0),
.DMA3_DRVALID(1'B0),
.DMA0_DRTYPE(2'B0),
.DMA1_DRTYPE(2'B0),
.DMA2_DRTYPE(2'B0),
.DMA3_DRTYPE(2'B0),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(FCLK_CLK1),
.FCLK_CLK2(),
.FCLK_CLK3(),
.FCLK_CLKTRIG0_N(1'B0),
.FCLK_CLKTRIG1_N(1'B0),
.FCLK_CLKTRIG2_N(1'B0),
.FCLK_CLKTRIG3_N(1'B0),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(FCLK_RESET1_N),
.FCLK_RESET2_N(),
.FCLK_RESET3_N(),
.FTMD_TRACEIN_DATA(32'B0),
.FTMD_TRACEIN_VALID(1'B0),
.FTMD_TRACEIN_CLK(1'B0),
.FTMD_TRACEIN_ATID(4'B0),
.FTMT_F2P_TRIG_0(1'B0),
.FTMT_F2P_TRIGACK_0(),
.FTMT_F2P_TRIG_1(1'B0),
.FTMT_F2P_TRIGACK_1(),
.FTMT_F2P_TRIG_2(1'B0),
.FTMT_F2P_TRIGACK_2(),
.FTMT_F2P_TRIG_3(1'B0),
.FTMT_F2P_TRIGACK_3(),
.FTMT_F2P_DEBUG(32'B0),
.FTMT_P2F_TRIGACK_0(1'B0),
.FTMT_P2F_TRIG_0(),
.FTMT_P2F_TRIGACK_1(1'B0),
.FTMT_P2F_TRIG_1(),
.FTMT_P2F_TRIGACK_2(1'B0),
.FTMT_P2F_TRIG_2(),
.FTMT_P2F_TRIGACK_3(1'B0),
.FTMT_P2F_TRIG_3(),
.FTMT_P2F_DEBUG(),
.FPGA_IDLE_N(1'B0),
.EVENT_EVENTO(),
.EVENT_STANDBYWFE(),
.EVENT_STANDBYWFI(),
.EVENT_EVENTI(1'B0),
.DDR_ARB(4'B0),
.MIO(MIO),
.DDR_CAS_n(DDR_CAS_n),
.DDR_CKE(DDR_CKE),
.DDR_Clk_n(DDR_Clk_n),
.DDR_Clk(DDR_Clk),
.DDR_CS_n(DDR_CS_n),
.DDR_DRSTB(DDR_DRSTB),
.DDR_ODT(DDR_ODT),
.DDR_RAS_n(DDR_RAS_n),
.DDR_WEB(DDR_WEB),
.DDR_BankAddr(DDR_BankAddr),
.DDR_Addr(DDR_Addr),
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_DM(DDR_DM),
.DDR_DQ(DDR_DQ),
.DDR_DQS_n(DDR_DQS_n),
.DDR_DQS(DDR_DQS),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule
|
// --------------------------------------------------------------------------------
//| Avalon ST Packets to MM Master Transaction Component
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
// --------------------------------------------------------------------------------
//| Fast Transaction Master
// --------------------------------------------------------------------------------
module altera_avalon_packets_to_master (
// Interface: clk
input wire clk,
input wire reset_n,
// Interface: ST in
output wire in_ready,
input wire in_valid,
input wire [ 7: 0] in_data,
input wire in_startofpacket,
input wire in_endofpacket,
// Interface: ST out
input wire out_ready,
output wire out_valid,
output wire [ 7: 0] out_data,
output wire out_startofpacket,
output wire out_endofpacket,
// Interface: MM out
output wire [31: 0] address,
input wire [31: 0] readdata,
output wire read,
output wire write,
output wire [ 3: 0] byteenable,
output wire [31: 0] writedata,
input wire waitrequest,
input wire readdatavalid
);
wire [ 35: 0] fifo_readdata;
wire fifo_read;
wire fifo_empty;
wire [ 35: 0] fifo_writedata;
wire fifo_write;
wire fifo_write_waitrequest;
// ---------------------------------------------------------------------
//| Parameter Declarations
// ---------------------------------------------------------------------
parameter EXPORT_MASTER_SIGNALS = 0;
parameter FIFO_DEPTHS = 2;
parameter FIFO_WIDTHU = 1;
parameter FAST_VER = 0;
generate
if (FAST_VER) begin
packets_to_fifo p2f (
.clk (clk),
.reset_n (reset_n),
.in_ready (in_ready),
.in_valid (in_valid),
.in_data (in_data),
.in_startofpacket (in_startofpacket),
.in_endofpacket (in_endofpacket),
.address (address),
.readdata (readdata),
.read (read),
.write (write),
.byteenable (byteenable),
.writedata (writedata),
.waitrequest (waitrequest),
.readdatavalid (readdatavalid),
.fifo_writedata (fifo_writedata),
.fifo_write (fifo_write),
.fifo_write_waitrequest (fifo_write_waitrequest)
);
fifo_to_packet f2p (
.clk (clk),
.reset_n (reset_n),
.out_ready (out_ready),
.out_valid (out_valid),
.out_data (out_data),
.out_startofpacket (out_startofpacket),
.out_endofpacket (out_endofpacket),
.fifo_readdata (fifo_readdata),
.fifo_read (fifo_read),
.fifo_empty (fifo_empty)
);
fifo_buffer #(
.FIFO_DEPTHS(FIFO_DEPTHS),
.FIFO_WIDTHU(FIFO_WIDTHU)
) fb (
.wrclock (clk),
.reset_n (reset_n),
.avalonmm_write_slave_writedata (fifo_writedata),
.avalonmm_write_slave_write (fifo_write),
.avalonmm_write_slave_waitrequest (fifo_write_waitrequest),
.avalonmm_read_slave_readdata (fifo_readdata),
.avalonmm_read_slave_read (fifo_read),
.avalonmm_read_slave_waitrequest (fifo_empty)
);
end else begin
packets_to_master p2m (
.clk (clk),
.reset_n (reset_n),
.in_ready (in_ready),
.in_valid (in_valid),
.in_data (in_data),
.in_startofpacket (in_startofpacket),
.in_endofpacket (in_endofpacket),
.address (address),
.readdata (readdata),
.read (read),
.write (write),
.byteenable (byteenable),
.writedata (writedata),
.waitrequest (waitrequest),
.readdatavalid (readdatavalid),
.out_ready (out_ready),
.out_valid (out_valid),
.out_data (out_data),
.out_startofpacket (out_startofpacket),
.out_endofpacket (out_endofpacket)
);
end
endgenerate
endmodule
module packets_to_fifo (
// Interface: clk
input clk,
input reset_n,
// Interface: ST in
output reg in_ready,
input in_valid,
input [ 7: 0] in_data,
input in_startofpacket,
input in_endofpacket,
// Interface: MM out
output reg [31: 0] address,
input [31: 0] readdata,
output reg read,
output reg write,
output reg [ 3: 0] byteenable,
output reg [31: 0] writedata,
input waitrequest,
input readdatavalid,
// Interface: FIFO
// FIFO data format:
// | sop, eop, [1:0]valid, [31:0]data |
output reg [ 35: 0] fifo_writedata,
output reg fifo_write,
input wire fifo_write_waitrequest
);
// ---------------------------------------------------------------------
//| Command Declarations
// ---------------------------------------------------------------------
localparam CMD_WRITE_NON_INCR = 8'h00;
localparam CMD_WRITE_INCR = 8'h04;
localparam CMD_READ_NON_INCR = 8'h10;
localparam CMD_READ_INCR = 8'h14;
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg [ 3: 0] state;
reg [ 7: 0] command;
reg [ 1: 0] current_byte, byte_avail;
reg [ 15: 0] counter;
reg [ 31: 0] read_data_buffer;
reg [ 31: 0] fifo_data_buffer;
reg in_ready_0;
reg first_trans, last_trans, fifo_sop;
reg [ 3: 0] unshifted_byteenable;
wire enable;
localparam READY = 4'b0000,
GET_EXTRA = 4'b0001,
GET_SIZE1 = 4'b0010,
GET_SIZE2 = 4'b0011,
GET_ADDR1 = 4'b0100,
GET_ADDR2 = 4'b0101,
GET_ADDR3 = 4'b0110,
GET_ADDR4 = 4'b0111,
GET_WRITE_DATA = 4'b1000,
WRITE_WAIT = 4'b1001,
READ_ASSERT = 4'b1010,
READ_CMD_WAIT = 4'b1011,
READ_DATA_WAIT = 4'b1100,
PUSH_FIFO = 4'b1101,
PUSH_FIFO_WAIT = 4'b1110,
FIFO_CMD_WAIT = 4'b1111;
// ---------------------------------------------------------------------
//| Thingofamagick
// ---------------------------------------------------------------------
assign enable = (in_ready & in_valid);
always @* begin
in_ready = in_ready_0;
end
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
in_ready_0 <= 1'b0;
fifo_writedata <= 'b0;
fifo_write <= 1'b0;
fifo_sop <= 1'b0;
read <= 1'b0;
write <= 1'b0;
byteenable <= 'b0;
writedata <= 'b0;
address <= 'b0;
counter <= 'b0;
command <= 'b0;
first_trans <= 1'b0;
last_trans <= 1'b0;
state <= 'b0;
current_byte <= 'b0;
read_data_buffer <= 'b0;
unshifted_byteenable <= 'b0;
byte_avail <= 'b0;
fifo_data_buffer <= 'b0;
end else begin
address[1:0] <= 'b0;
in_ready_0 <= 1'b0;
if (counter > 3) unshifted_byteenable <= 4'b1111;
else if (counter == 3) unshifted_byteenable <= 4'b0111;
else if (counter == 2) unshifted_byteenable <= 4'b0011;
else if (counter == 1) unshifted_byteenable <= 4'b0001;
case (state)
READY : begin
in_ready_0 <= !fifo_write_waitrequest;
fifo_write <= 1'b0;
end
GET_EXTRA : begin
in_ready_0 <= 1'b1;
byteenable <= 'b0;
if (enable) state <= GET_SIZE1;
end
GET_SIZE1 : begin
in_ready_0 <= 1'b1;
//load counter on reads only
counter[15:8] <= command[4]?in_data:8'b0;
if (enable) state <= GET_SIZE2;
end
GET_SIZE2 : begin
in_ready_0 <= 1'b1;
//load counter on reads only
counter[7:0] <= command[4]?in_data:8'b0;
if (enable) state <= GET_ADDR1;
end
GET_ADDR1 : begin
in_ready_0 <= 1'b1;
first_trans <= 1'b1;
last_trans <= 1'b0;
address[31:24] <= in_data;
if (enable) state <= GET_ADDR2;
end
GET_ADDR2 : begin
in_ready_0 <= 1'b1;
address[23:16] <= in_data;
if (enable) state <= GET_ADDR3;
end
GET_ADDR3 : begin
in_ready_0 <= 1'b1;
address[15:8] <= in_data;
if (enable) state <= GET_ADDR4;
end
GET_ADDR4 : begin
in_ready_0 <= 1'b1;
address[7:2] <= in_data[7:2];
current_byte <= in_data[1:0];
if (enable) begin
if (command == CMD_WRITE_NON_INCR | command == CMD_WRITE_INCR) begin
state <= GET_WRITE_DATA; //writes
in_ready_0 <= 1'b1;
end
else if (command == CMD_READ_NON_INCR | command == CMD_READ_INCR) begin
state <= READ_ASSERT; //reads
in_ready_0 <= 1'b0;
end
else begin
//nops
//treat all unrecognized commands as nops as well
in_ready_0 <= 1'b0;
state <= FIFO_CMD_WAIT;
//| sop, eop, [1:0]valid, [31:0]data |
//| 1 , 1 , 2'b11 ,{counter,reserved_byte}|
fifo_writedata[7:0] <= (8'h80 | command);
fifo_writedata[35:8]<= {4'b1111,counter[7:0],counter[15:8],8'b0};
fifo_write <= 1'b1;
counter <= 0;
end
end
end
GET_WRITE_DATA : begin
in_ready_0 <= 1'b1;
if (enable) begin
counter <= counter + 1'b1;
//2 bit, should wrap by itself
current_byte <= current_byte + 1'b1;
if (in_endofpacket || current_byte == 3)
begin
in_ready_0 <= 1'b0;
write <= 1'b1;
state <= WRITE_WAIT;
end
end
if (in_endofpacket) begin
last_trans <= 1'b1;
end
// handle byte writes properly
// drive data pins based on addresses
case (current_byte)
0: begin
writedata[7:0] <= in_data;
byteenable[0] <= 1'b1;
end
1: begin
writedata[15:8] <= in_data;
byteenable[1] <= 1'b1;
end
2: begin
writedata[23:16] <= in_data;
byteenable[2] <= 1'b1;
end
3: begin
writedata[31:24] <= in_data;
byteenable[3] <= 1'b1;
end
endcase
end
WRITE_WAIT : begin
in_ready_0 <= 1'b0;
write <= 1'b1;
if (~waitrequest) begin
write <= 1'b0;
state <= GET_WRITE_DATA;
in_ready_0 <= 1'b1;
byteenable <= 'b0;
if (command[2] == 1'b1) begin
//increment address, but word-align it
address[31:2] <= (address[31:2] + 1'b1);
end
if (last_trans) begin
in_ready_0 <= 1'b0;
state <= FIFO_CMD_WAIT;
//| sop, eop, [1:0]valid, [31:0]data |
//| 1 , 1 , 2'b11 ,{counter,reserved_byte}|
fifo_writedata[7:0] <= (8'h80 | command);
fifo_writedata[35:8]<= {4'b1111,counter[7:0],counter[15:8],8'b0};
fifo_write <= 1'b1;
counter <= 0;
end
end
end
READ_ASSERT : begin
if (current_byte == 3) byteenable <= unshifted_byteenable << 3;
if (current_byte == 2) byteenable <= unshifted_byteenable << 2;
if (current_byte == 1) byteenable <= unshifted_byteenable << 1;
if (current_byte == 0) byteenable <= unshifted_byteenable;
read <= 1'b1;
fifo_write <= 1'b0;
state <= READ_CMD_WAIT;
end
READ_CMD_WAIT : begin
// number of valid byte
case (byteenable)
4'b0000 : byte_avail <= 1'b0;
4'b0001 : byte_avail <= 1'b0;
4'b0010 : byte_avail <= 1'b0;
4'b0100 : byte_avail <= 1'b0;
4'b1000 : byte_avail <= 1'b0;
4'b0011 : byte_avail <= 1'b1;
4'b0110 : byte_avail <= 1'b1;
4'b1100 : byte_avail <= 1'b1;
4'b0111 : byte_avail <= 2'h2;
4'b1110 : byte_avail <= 2'h2;
default : byte_avail <= 2'h3;
endcase
read_data_buffer <= readdata;
read <= 1;
// if readdatavalid, take the data and
// go directly to READ_SEND_ISSUE. This is for fixed
// latency slaves. Ignore waitrequest in this case,
// since this master does not issue pipelined reads.
//
// For variable latency slaves, once waitrequest is low
// the read command is accepted, so deassert read and
// go to READ_DATA_WAIT to wait for readdatavalid
if (readdatavalid) begin
state <= PUSH_FIFO;
read <= 0;
end else begin
if (~waitrequest) begin
state <= READ_DATA_WAIT;
read <= 0;
end
end
end
READ_DATA_WAIT : begin
read_data_buffer <= readdata;
if (readdatavalid) begin
state <= PUSH_FIFO;
end
end
PUSH_FIFO : begin
fifo_write <= 1'b0;
fifo_sop <= 1'b0;
if (first_trans) begin
first_trans <= 1'b0;
fifo_sop <= 1'b1;
end
case (current_byte)
3 : begin
fifo_data_buffer <= read_data_buffer >> 24;
counter <= counter - 1'b1;
end
2 : begin
fifo_data_buffer <= read_data_buffer >> 16;
if (counter == 1) counter <= 0;
else counter <= counter - 2'h2;
end
1 : begin
fifo_data_buffer <= read_data_buffer >> 8;
if (counter < 3) counter <= 0;
else counter <= counter - 2'h3;
end
default : begin
fifo_data_buffer <= read_data_buffer;
if (counter < 4) counter <= 0;
else counter <= counter - 3'h4;
end
endcase
current_byte <= 0;
state <= PUSH_FIFO_WAIT;
end
PUSH_FIFO_WAIT : begin
// pushd return packet with data
fifo_write <= 1'b1;
fifo_writedata <= {fifo_sop,(counter == 0)?1'b1:1'b0,byte_avail,fifo_data_buffer};
// count down on the number of bytes to read
// shift current byte location within word
// if increment address, add it, so the next read
// can use it, if more reads are required
// no more bytes to send - go to READY state
if (counter == 0) begin
state <= FIFO_CMD_WAIT;
end else if (command[2]== 1'b1) begin
//increment address, but word-align it
state <= FIFO_CMD_WAIT;
address[31:2] <= (address[31:2] + 1'b1);
end
end
FIFO_CMD_WAIT : begin
// back pressure if fifo_write_waitrequest
if (!fifo_write_waitrequest) begin
if (counter == 0) begin
state <= READY;
end else begin
state <= READ_ASSERT;
end
fifo_write <= 1'b0;
end
end
endcase
if (enable & in_startofpacket) begin
state <= GET_EXTRA;
command <= in_data;
in_ready_0 <= !fifo_write_waitrequest;
end
end // end else
end // end always block
endmodule
// --------------------------------------------------------------------------------
// FIFO buffer
// --------------------------------------------------------------------------------
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module fifo_buffer_single_clock_fifo (
// inputs:
aclr,
clock,
data,
rdreq,
wrreq,
// outputs:
empty,
full,
q
)
;
parameter FIFO_DEPTHS = 2;
parameter FIFO_WIDTHU = 1;
output empty;
output full;
output [ 35: 0] q;
input aclr;
input clock;
input [ 35: 0] data;
input rdreq;
input wrreq;
wire empty;
wire full;
wire [ 35: 0] q;
scfifo single_clock_fifo
(
.aclr (aclr),
.clock (clock),
.data (data),
.empty (empty),
.full (full),
.q (q),
.rdreq (rdreq),
.wrreq (wrreq)
);
defparam single_clock_fifo.add_ram_output_register = "OFF",
single_clock_fifo.lpm_numwords = FIFO_DEPTHS,
single_clock_fifo.lpm_showahead = "OFF",
single_clock_fifo.lpm_type = "scfifo",
single_clock_fifo.lpm_width = 36,
single_clock_fifo.lpm_widthu = FIFO_WIDTHU,
single_clock_fifo.overflow_checking = "ON",
single_clock_fifo.underflow_checking = "ON",
single_clock_fifo.use_eab = "OFF";
endmodule
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module fifo_buffer_scfifo_with_controls (
// inputs:
clock,
data,
rdreq,
reset_n,
wrreq,
// outputs:
empty,
full,
q
)
;
parameter FIFO_DEPTHS = 2;
parameter FIFO_WIDTHU = 1;
output empty;
output full;
output [ 35: 0] q;
input clock;
input [ 35: 0] data;
input rdreq;
input reset_n;
input wrreq;
wire empty;
wire full;
wire [ 35: 0] q;
wire wrreq_valid;
//the_scfifo, which is an e_instance
fifo_buffer_single_clock_fifo #(
.FIFO_DEPTHS(FIFO_DEPTHS),
.FIFO_WIDTHU(FIFO_WIDTHU)
) the_scfifo (
.aclr (~reset_n),
.clock (clock),
.data (data),
.empty (empty),
.full (full),
.q (q),
.rdreq (rdreq),
.wrreq (wrreq_valid)
);
assign wrreq_valid = wrreq & ~full;
endmodule
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module fifo_buffer (
// inputs:
avalonmm_read_slave_read,
avalonmm_write_slave_write,
avalonmm_write_slave_writedata,
reset_n,
wrclock,
// outputs:
avalonmm_read_slave_readdata,
avalonmm_read_slave_waitrequest,
avalonmm_write_slave_waitrequest
)
;
parameter FIFO_DEPTHS = 2;
parameter FIFO_WIDTHU = 1;
output [ 35: 0] avalonmm_read_slave_readdata;
output avalonmm_read_slave_waitrequest;
output avalonmm_write_slave_waitrequest;
input avalonmm_read_slave_read;
input avalonmm_write_slave_write;
input [ 35: 0] avalonmm_write_slave_writedata;
input reset_n;
input wrclock;
wire [ 35: 0] avalonmm_read_slave_readdata;
wire avalonmm_read_slave_waitrequest;
wire avalonmm_write_slave_waitrequest;
wire clock;
wire [ 35: 0] data;
wire empty;
wire full;
wire [ 35: 0] q;
wire rdreq;
wire wrreq;
//the_scfifo_with_controls, which is an e_instance
fifo_buffer_scfifo_with_controls #(
.FIFO_DEPTHS(FIFO_DEPTHS),
.FIFO_WIDTHU(FIFO_WIDTHU)
) the_scfifo_with_controls
(
.clock (clock),
.data (data),
.empty (empty),
.full (full),
.q (q),
.rdreq (rdreq),
.reset_n (reset_n),
.wrreq (wrreq)
);
//in, which is an e_avalon_slave
//out, which is an e_avalon_slave
assign data = avalonmm_write_slave_writedata;
assign wrreq = avalonmm_write_slave_write;
assign avalonmm_read_slave_readdata = q;
assign rdreq = avalonmm_read_slave_read;
assign clock = wrclock;
assign avalonmm_write_slave_waitrequest = full;
assign avalonmm_read_slave_waitrequest = empty;
endmodule
// --------------------------------------------------------------------------------
// fifo_buffer to Avalon-ST interface
// --------------------------------------------------------------------------------
module fifo_to_packet (
// Interface: clk
input clk,
input reset_n,
// Interface: ST out
input out_ready,
output reg out_valid,
output reg [ 7: 0] out_data,
output reg out_startofpacket,
output reg out_endofpacket,
// Interface: FIFO in
input [ 35: 0] fifo_readdata,
output reg fifo_read,
input fifo_empty
);
reg [ 1: 0] state;
reg enable, sent_all;
reg [ 1: 0] current_byte, byte_end;
reg first_trans, last_trans;
reg [ 23:0] fifo_data_buffer;
localparam POP_FIFO = 2'b00,
POP_FIFO_WAIT = 2'b01,
FIFO_DATA_WAIT = 2'b10,
READ_SEND_ISSUE = 2'b11;
always @* begin
enable = (!fifo_empty & sent_all);
end
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
fifo_data_buffer <= 'b0;
out_startofpacket <= 1'b0;
out_endofpacket <= 1'b0;
out_valid <= 1'b0;
out_data <= 'b0;
state <= 'b0;
fifo_read <= 1'b0;
current_byte <= 'b0;
byte_end <= 'b0;
first_trans <= 1'b0;
last_trans <= 1'b0;
sent_all <= 1'b1;
end else begin
if (out_ready) begin
out_startofpacket <= 1'b0;
out_endofpacket <= 1'b0;
end
case (state)
POP_FIFO : begin
if (out_ready) begin
out_startofpacket <= 1'b0;
out_endofpacket <= 1'b0;
out_valid <= 1'b0;
first_trans <= 1'b0;
last_trans <= 1'b0;
byte_end <= 'b0;
fifo_read <= 1'b0;
sent_all <= 1'b1;
end
// start poping fifo after all data sent and data available
if (enable) begin
fifo_read <= 1'b1;
out_valid <= 1'b0;
state <= POP_FIFO_WAIT;
end
end
POP_FIFO_WAIT : begin
//fifo latency of 1
fifo_read <= 1'b0;
state <= FIFO_DATA_WAIT;
end
FIFO_DATA_WAIT : begin
sent_all <= 1'b0;
first_trans <= fifo_readdata[35];
last_trans <= fifo_readdata[34];
out_data <= fifo_readdata[7:0];
fifo_data_buffer <= fifo_readdata[31:8];
byte_end <= fifo_readdata[33:32];
current_byte <= 1'b1;
out_valid <= 1'b1;
// first byte sop eop handling
if (fifo_readdata[35] & fifo_readdata[34] & (fifo_readdata[33:32] == 0)) begin
first_trans <= 1'b0;
last_trans <= 1'b0;
out_startofpacket <= 1'b1;
out_endofpacket <= 1'b1;
state <= POP_FIFO;
end else if (fifo_readdata[35] & (fifo_readdata[33:32] == 0)) begin
first_trans <= 1'b0;
out_startofpacket <= 1'b1;
state <= POP_FIFO;
end else if (fifo_readdata[35]) begin
first_trans <= 1'b0;
out_startofpacket <= 1'b1;
state <= READ_SEND_ISSUE;
end else if (fifo_readdata[34] & (fifo_readdata[33:32] == 0)) begin
last_trans <= 1'b0;
out_endofpacket <= 1'b1;
state <= POP_FIFO;
end else begin
state <= READ_SEND_ISSUE;
end
end
READ_SEND_ISSUE : begin
out_valid <= 1'b1;
sent_all <= 1'b0;
if (out_ready) begin
out_startofpacket <= 1'b0;
// last byte
if (last_trans & (current_byte == byte_end)) begin
last_trans <= 1'b0;
out_endofpacket <= 1'b1;
state <= POP_FIFO;
end
case (current_byte)
3: begin
out_data <= fifo_data_buffer[23:16];
end
2: begin
out_data <= fifo_data_buffer[15:8];
end
1: begin
out_data <= fifo_data_buffer[7:0];
end
default: begin
//out_data <= fifo_readdata[7:0];
end
endcase
current_byte <= current_byte + 1'b1;
if (current_byte == byte_end) begin
state <= POP_FIFO;
end else begin
state <= READ_SEND_ISSUE;
end
end
end
endcase
end
end
endmodule
// --------------------------------------------------------------------------------
//| Economy Transaction Master
// --------------------------------------------------------------------------------
module packets_to_master (
// Interface: clk
input clk,
input reset_n,
// Interface: ST in
output reg in_ready,
input in_valid,
input [ 7: 0] in_data,
input in_startofpacket,
input in_endofpacket,
// Interface: ST out
input out_ready,
output reg out_valid,
output reg [ 7: 0] out_data,
output reg out_startofpacket,
output reg out_endofpacket,
// Interface: MM out
output reg [31: 0] address,
input [31: 0] readdata,
output reg read,
output reg write,
output reg [ 3: 0] byteenable,
output reg [31: 0] writedata,
input waitrequest,
input readdatavalid
);
// ---------------------------------------------------------------------
//| Parameter Declarations
// ---------------------------------------------------------------------
parameter EXPORT_MASTER_SIGNALS = 0;
// ---------------------------------------------------------------------
//| Command Declarations
// ---------------------------------------------------------------------
localparam CMD_WRITE_NON_INCR = 8'h00;
localparam CMD_WRITE_INCR = 8'h04;
localparam CMD_READ_NON_INCR = 8'h10;
localparam CMD_READ_INCR = 8'h14;
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg [ 3: 0] state;
reg [ 7: 0] command;
reg [ 1: 0] current_byte; //, result_byte;
reg [ 15: 0] counter;
reg [ 23: 0] read_data_buffer;
reg in_ready_0;
reg first_trans, last_trans;
reg [ 3: 0] unshifted_byteenable;
wire enable;
localparam READY = 4'b0000,
GET_EXTRA = 4'b0001,
GET_SIZE1 = 4'b0010,
GET_SIZE2 = 4'b0011,
GET_ADDR1 = 4'b0100,
GET_ADDR2 = 4'b0101,
GET_ADDR3 = 4'b0110,
GET_ADDR4 = 4'b0111,
GET_WRITE_DATA = 4'b1000,
WRITE_WAIT = 4'b1001,
RETURN_PACKET = 4'b1010,
READ_ASSERT = 4'b1011,
READ_CMD_WAIT = 4'b1100,
READ_DATA_WAIT = 4'b1101,
READ_SEND_ISSUE= 4'b1110,
READ_SEND_WAIT = 4'b1111;
// ---------------------------------------------------------------------
//| Thingofamagick
// ---------------------------------------------------------------------
assign enable = (in_ready & in_valid);
always @*
// in_ready = in_ready_0 & out_ready;
in_ready = in_ready_0;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
in_ready_0 <= 1'b0;
out_startofpacket <= 1'b0;
out_endofpacket <= 1'b0;
out_valid <= 1'b0;
out_data <= 'b0;
read <= 1'b0;
write <= 1'b0;
byteenable <= 'b0;
writedata <= 'b0;
address <= 'b0;
counter <= 'b0;
command <= 'b0;
first_trans <= 1'b0;
last_trans <= 1'b0;
state <= 'b0;
current_byte <= 'b0;
// result_byte <= 'b0;
read_data_buffer <= 'b0;
unshifted_byteenable <= 'b0;
end else begin
address[1:0] <= 'b0;
if (out_ready) begin
out_startofpacket <= 1'b0;
out_endofpacket <= 1'b0;
out_valid <= 1'b0;
end
in_ready_0 <= 1'b0;
if (counter >= 3) unshifted_byteenable <= 4'b1111;
else if (counter == 3) unshifted_byteenable <= 4'b0111;
else if (counter == 2) unshifted_byteenable <= 4'b0011;
else if (counter == 1) unshifted_byteenable <= 4'b0001;
case (state)
READY : begin
out_valid <= 1'b0;
in_ready_0 <= 1'b1;
end
GET_EXTRA : begin
in_ready_0 <= 1'b1;
byteenable <= 'b0;
if (enable) state <= GET_SIZE1;
end
GET_SIZE1 : begin
in_ready_0 <= 1'b1;
//load counter on reads only
counter[15:8] <= command[4]?in_data:8'b0;
if (enable) state <= GET_SIZE2;
end
GET_SIZE2 : begin
in_ready_0 <= 1'b1;
//load counter on reads only
counter[7:0] <= command[4]?in_data:8'b0;
if (enable) state <= GET_ADDR1;
end
GET_ADDR1 : begin
in_ready_0 <= 1'b1;
first_trans <= 1'b1;
last_trans <= 1'b0;
address[31:24] <= in_data;
if (enable) state <= GET_ADDR2;
end
GET_ADDR2 : begin
in_ready_0 <= 1'b1;
address[23:16] <= in_data;
if (enable) state <= GET_ADDR3;
end
GET_ADDR3 : begin
in_ready_0 <= 1'b1;
address[15:8] <= in_data;
if (enable) state <= GET_ADDR4;
end
GET_ADDR4 : begin
in_ready_0 <= 1'b1;
address[7:2] <= in_data[7:2];
current_byte <= in_data[1:0];
if (enable) begin
if (command == CMD_WRITE_NON_INCR | command == CMD_WRITE_INCR) begin
state <= GET_WRITE_DATA; //writes
in_ready_0 <= 1'b1;
end
else if (command == CMD_READ_NON_INCR | command == CMD_READ_INCR) begin
state <= READ_ASSERT; //reads
in_ready_0 <= 1'b0;
end
else begin
//nops
//treat all unrecognized commands as nops as well
state <= RETURN_PACKET;
out_startofpacket <= 1'b1;
out_data <= (8'h80 | command);
out_valid <= 1'b1;
current_byte <= 'h0;
in_ready_0 <= 1'b0;
end
end
end
GET_WRITE_DATA : begin
in_ready_0 <= 1;
if (enable) begin
counter <= counter + 1'b1;
//2 bit, should wrap by itself
current_byte <= current_byte + 1'b1;
if (in_endofpacket || current_byte == 3)
begin
in_ready_0 <= 0;
write <= 1'b1;
state <= WRITE_WAIT;
end
end
if (in_endofpacket) begin
last_trans <= 1'b1;
end
// handle byte writes properly
// drive data pins based on addresses
case (current_byte)
0: begin
writedata[7:0] <= in_data;
byteenable[0] <= 1;
end
1: begin
writedata[15:8] <= in_data;
byteenable[1] <= 1;
end
2: begin
writedata[23:16] <= in_data;
byteenable[2] <= 1;
end
3: begin
writedata[31:24] <= in_data;
byteenable[3] <= 1;
end
endcase
end
WRITE_WAIT : begin
in_ready_0 <= 0;
write <= 1'b1;
if (~waitrequest) begin
write <= 1'b0;
state <= GET_WRITE_DATA;
in_ready_0 <= 1;
byteenable <= 'b0;
if (command[2] == 1'b1) begin
//increment address, but word-align it
address[31:2] <= (address[31:2] + 1'b1);
end
if (last_trans) begin
state <= RETURN_PACKET;
out_startofpacket <= 1'b1;
out_data <= (8'h80 | command);
out_valid <= 1'b1;
current_byte <= 'h0;
in_ready_0 <= 1'b0;
end
end
end
RETURN_PACKET : begin
out_valid <= 1'b1;
if (out_ready) begin
case (current_byte)
// 0: begin
// out_startofpacket <= 1'b1;
// out_data <= (8'h80 | command);
// end
0: begin
out_data <= 8'b0;
end
1: begin
out_data <= counter[15:8];
end
2: begin
out_endofpacket <= 1'b1;
out_data <= counter[7:0];
end
default: begin
// out_data <= 8'b0;
// out_startofpacket <= 1'b0;
// out_endofpacket <= 1'b0;
end
endcase
current_byte <= current_byte + 1'b1;
if (current_byte == 3) begin
state <= READY;
out_valid <= 1'b0;
end
else state <= RETURN_PACKET;
end
end
READ_ASSERT : begin
if (current_byte == 3) byteenable <= unshifted_byteenable << 3;
if (current_byte == 2) byteenable <= unshifted_byteenable << 2;
if (current_byte == 1) byteenable <= unshifted_byteenable << 1;
if (current_byte == 0) byteenable <= unshifted_byteenable;
// byteenable <= unshifted_byteenable << current_byte;
read <= 1;
state <= READ_CMD_WAIT;
end
READ_CMD_WAIT : begin
read_data_buffer <= readdata[31:8];
out_data <= readdata[7:0];
read <= 1;
// if readdatavalid, take the data and
// go directly to READ_SEND_ISSUE. This is for fixed
// latency slaves. Ignore waitrequest in this case,
// since this master does not issue pipelined reads.
//
// For variable latency slaves, once waitrequest is low
// the read command is accepted, so deassert read and
// go to READ_DATA_WAIT to wait for readdatavalid
if (readdatavalid) begin
state <= READ_SEND_ISSUE;
read <= 0;
end else begin
if (~waitrequest) begin
state <= READ_DATA_WAIT;
read <= 0;
end
end
end
READ_DATA_WAIT : begin
read_data_buffer <= readdata[31:8];
out_data <= readdata[7:0];
if (readdatavalid) begin
state <= READ_SEND_ISSUE;
end
end
READ_SEND_ISSUE : begin
out_valid <= 1'b1;
out_startofpacket <= 'h0;
out_endofpacket <= 'h0;
if (counter == 1) begin
out_endofpacket <= 1'b1;
end
if (first_trans) begin
first_trans <= 1'b0;
out_startofpacket <= 1'b1;
end
case (current_byte)
3: begin
out_data <= read_data_buffer[23:16];
end
2: begin
out_data <= read_data_buffer[15:8];
end
1: begin
out_data <= read_data_buffer[7:0];
end
default: begin
out_data <= out_data;
end
endcase
state <= READ_SEND_WAIT;
end
READ_SEND_WAIT : begin
out_valid <= 1'b1;
if (out_ready) begin
counter <= counter - 1'b1;
current_byte <= current_byte + 1'b1;
out_valid <= 1'b0;
// count down on the number of bytes to read
// shift current byte location within word
// if increment address, add it, so the next read
// can use it, if more reads are required
// no more bytes to send - go to READY state
if (counter == 1) begin
state <= READY;
// end of current word, but we have more bytes to
// read - go back to READ_ASSERT
end else if (current_byte == 3) begin
if (command[2] == 1'b1) begin
//increment address, but word-align it
address[31:2] <= (address[31:2] + 1'b1);
end
state <= READ_ASSERT;
// continue sending current word
end else begin
state <= READ_SEND_ISSUE;
end
//maybe add in_ready_0 here so we are ready to go
//right away
end
end
endcase
if (enable & in_startofpacket) begin
state <= GET_EXTRA;
command <= in_data;
in_ready_0 <= 1'b1;
end
end // end else
end // end always block
endmodule
|
// (C) 1992-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_custom_add_wrapper(clock, resetn, dataa, datab, result, valid_in, valid_out, stall_in, stall_out, enable);
input clock, resetn;
input valid_in, stall_in;
output valid_out, stall_out;
input enable;
input [36:0] dataa;
input [36:0] datab;
output [37:0] result;
parameter HIGH_CAPACITY = 0;
parameter FLUSH_DENORMS = 0;
parameter HIGH_LATENCY = 0;
parameter ROUNDING_MODE = 0;
parameter FINITE_MATH_ONLY = 1;
parameter REMOVE_STICKY = 1;
// Total Latency = 12-7.
wire [26:0] input_a_mantissa = dataa[26:0];
wire [26:0] input_b_mantissa = datab[26:0];
wire input_a_sign = dataa[36];
wire input_b_sign = datab[36];
wire [8:0] input_a_exponent = dataa[35:27];
wire [8:0] input_b_exponent = datab[35:27];
wire [26:0] left_mantissa;
wire [26:0] right_mantissa;
wire left_sign, right_sign, align_valid_out;
wire [8:0] align_exponent;
wire stall_align;
wire conversion_valid = valid_in;
wire alignment_stall;
assign stall_out = alignment_stall;
acl_fp_custom_align alignment(
.clock(clock),
.resetn(resetn),
.input_a_mantissa(input_a_mantissa),
.input_a_exponent(input_a_exponent),
.input_a_sign(input_a_sign),
.input_b_mantissa(input_b_mantissa),
.input_b_exponent(input_b_exponent),
.input_b_sign(input_b_sign),
.left_mantissa(left_mantissa),
.left_exponent(align_exponent),
.left_sign(left_sign),
.right_mantissa(right_mantissa),
.right_exponent(),
.right_sign(right_sign),
.valid_in(conversion_valid),
.valid_out(align_valid_out),
.stall_in(stall_align),
.stall_out(alignment_stall),
.enable(enable));
defparam alignment.HIGH_CAPACITY = HIGH_CAPACITY;
defparam alignment.FLUSH_DENORMS = FLUSH_DENORMS;
defparam alignment.HIGH_LATENCY = HIGH_LATENCY;
defparam alignment.ROUNDING_MODE = ROUNDING_MODE;
defparam alignment.FINITE_MATH_ONLY = FINITE_MATH_ONLY;
defparam alignment.REMOVE_STICKY = REMOVE_STICKY;
wire [27:0] resulting_mantissa;
wire [8:0] resulting_exponent;
wire resulting_sign;
wire valid_sum;
acl_fp_custom_add_op op(
.clock(clock),
.resetn(resetn),
.left_mantissa(left_mantissa),
.right_mantissa(right_mantissa),
.left_sign(left_sign),
.right_sign(right_sign),
.common_exponent(align_exponent),
.resulting_mantissa(resulting_mantissa),
.resulting_exponent(resulting_exponent),
.resulting_sign(resulting_sign),
.valid_in(align_valid_out),
.valid_out(valid_out),
.stall_in(stall_in),
.stall_out(stall_align),
.enable(enable));
defparam op.HIGH_CAPACITY = HIGH_CAPACITY;
assign result = {resulting_sign, resulting_exponent, resulting_mantissa};
endmodule
|
/*
* WJX1 Execute Unit
* Pipeline: IF D1 D2 E1 E2 M1 M2 WB
*/
`include "CoreDefs.v"
`include "Dc2Tile.v"
`include "DcTile3.v"
`include "IcTile3.v"
`include "RegWGPR.v"
`include "DecWOp.v"
`include "ExOp64_3C.v"
module ExUnitW(
/* verilator lint_off UNUSED */
clock, reset,
extAddr, extData,
extOE, extWR,
extOK,
mmioAddr, mmioData,
mmioOE, mmioWR,
mmioOK
);
input clock; //clock
input reset; //reset
/* External Memory */
output[31:0] extAddr; //external memory address
inout[127:0] extData; //external memory data (read/write)
output extOE; //external output enable
output extWR; //external write
input extOK; //external access is OK
/* External MMIO */
output[31:0] mmioAddr; //external memory address
inout[31:0] mmioData; //external memory data (read/write)
output mmioOE; //external output enable
output mmioWR; //external write
input[1:0] mmioOK; //external access is OK
assign extAddr = 32'hZ;
assign extData = 128'hZ;
assign extOE = 0;
assign extWR = 0;
// assign mmioAddr = 0;
// assign mmioData = 32'hZ;
// assign mmioOE = 0;
// assign mmioWR = 0;
assign mmioAddr = dc2MmioAddr;
assign mmioData = dc2MmioWR ? dc2MmioOutData : 32'hZ;
assign mmioOE = dc2MmioOE;
assign mmioWR = dc2MmioWR;
assign dc2MmioOK = mmioOK;
wire[63:0] regMach; //MACH:MACL
wire[63:0] regMacl; //MACH:MACL
wire[63:0] regPr; //PR
wire[63:0] regSGr; //SGR (Saved R15)
wire[63:0] regFpul; //FPUL
wire[63:0] regFpScr; //FPSCR
wire[63:0] regSr; //SR
wire[63:0] regGbr; //GBR
wire[63:0] regVbr; //VBR
wire[63:0] regSSr; //SSR
wire[63:0] regSPc; //SPC
wire[63:0] regPc; //PC
wire[63:0] regSp; //SP/GR (R15)
reg[63:0] exNextSr2; //SR in
reg[63:0] exNextPr2; //PR in
reg[63:0] exNextPc2; //PC in
reg[63:0] exNextMach2; //MACH:MACL
reg[63:0] exNextMacl2; //MACH:MACL
reg[63:0] exNextGbr2; //GBR
reg[63:0] exNextVbr2; //VBR
reg[63:0] exNextSSr2; //SSR
reg[63:0] exNextSPc2; //SPC
reg[63:0] exNextSGr2; //SGR (Saved R15)
reg[63:0] exNextFpul2; //
reg[63:0] exNextFpScr2; //
reg[63:0] exNextSp2; //
reg tRegExHold; //Execution is held
reg[7:0] regRstTok;
reg[7:0] regNextRstTok;
/* L2 */
reg[63:0] dc2RegInAddr;
reg[127:0] dc2RegInData;
wire[127:0] dc2RegOutData;
wire[1:0] dc2RegOutOK;
reg dc2RegInOE;
reg dc2RegInWR;
reg[4:0] dc2RegInOp;
reg[127:0] dc2MemInData;
wire[127:0] dc2MemOutData;
wire[31:0] dc2MemAddr;
wire dc2MemOE;
wire dc2MemWR;
reg[1:0] dc2MemOK;
//wire[1:0] dc2MemOK;
reg[31:0] dc2MmioInData;
wire[31:0] dc2MmioOutData;
wire[31:0] dc2MmioAddr;
wire dc2MmioOE;
wire dc2MmioWR;
//reg[1:0] dc2MmioOK;
wire[1:0] dc2MmioOK;
Dc2Tile dcl2(
clock, reset,
dc2RegInAddr, dc2RegInData,
dc2RegOutData, dc2RegOutOK,
dc2RegInOE, dc2RegInWR,
dc2RegInOp,
dc2MemInData, dc2MemOutData, dc2MemAddr,
dc2MemOE, dc2MemWR, dc2MemOK,
dc2MmioInData, dc2MmioOutData, dc2MmioAddr,
dc2MmioOE, dc2MmioWR, dc2MmioOK
);
/* DCache */
reg[63:0] dcfRegInAddr;
reg[63:0] dcfRegInData;
wire[63:0] dcfRegOutData;
wire[1:0] dcfRegOutOK;
reg dcfRegInOE;
reg dcfRegInWR;
reg[4:0] dcfRegInOp;
reg[127:0] dcfMemInData;
wire[127:0] dcfMemOutData;
wire[63:0] dcfMemPcAddr;
wire dcfMemPcOE;
wire dcfMemPcWR;
reg[1:0] dcfMemPcOK;
wire[4:0] dcfMemOp;
DcTile3 dcf(
clock, reset,
dcfRegInData, dcfRegOutData,
dcfRegInAddr, dcfRegOutOK,
dcfRegInOE, dcfRegInWR,
dcfRegInOp,
dcfMemInData, dcfMemOutData,
dcfMemPcAddr, dcfMemPcOK,
dcfMemPcOE, dcfMemPcWR,
dcfMemOp
);
/* IF */
reg[63:0] regIfPc; //PC, Fetch
reg[63:0] regIfSr; //SR, Fetch
wire[127:0] regIfPcVal; //PC Instruction Value
wire[1:0] regIfPcOK;
reg[127:0] memIfPcData;
wire[63:0] memIfPcAddr;
wire memIfPcOE;
reg[1:0] memIfPcOK;
IcTile3 icf(clock, reset,
regIfPc,
regIfPcVal, regIfPcOK,
memIfPcData,
memIfPcAddr, memIfPcOE, memIfPcOK);
reg[127:0] regIfPcVal2; //PC Instruction Value
/* D1, D2 */
reg[63:0] regIdPc;
reg[63:0] regIdSr;
reg[15:0] regIdCsFl;
reg[127:0] idIstrWord;
wire[6:0] idRegN1;
wire[6:0] idRegS1;
wire[6:0] idRegT1;
wire[6:0] idRegN2;
wire[6:0] idRegS2;
wire[6:0] idRegT2;
wire[6:0] idRegN3;
wire[6:0] idRegS3;
wire[6:0] idRegT3;
wire[6:0] idRegN4;
wire[6:0] idRegS4;
wire[6:0] idRegT4;
wire[6:0] idRegN5;
wire[6:0] idRegS5;
wire[6:0] idRegT5;
wire[31:0] idImm1;
wire[31:0] idImm2;
wire[31:0] idImm3;
wire[31:0] idImm4;
wire[31:0] idImm5;
wire[7:0] idUCmd1;
wire[7:0] idUCmd2;
wire[7:0] idUCmd3;
wire[7:0] idUCmd4;
wire[7:0] idUCmd5;
wire idStep;
DecWOp decw(
clock, idIstrWord, idStep,
idRegN1, idRegS1, idRegT1, idImm1, idUCmd1,
idRegN2, idRegS2, idRegT2, idImm2, idUCmd2,
idRegN3, idRegS3, idRegT3, idImm3, idUCmd3,
idRegN4, idRegS4, idRegT4, idImm4, idUCmd4,
idRegN5, idRegS5, idRegT5, idImm5, idUCmd5);
wire[63:0] idValN1;
wire[63:0] idValS1;
wire[63:0] idValT1;
wire[63:0] idValN2;
wire[63:0] idValS2;
wire[63:0] idValT2;
wire[63:0] idValN3;
wire[63:0] idValS3;
wire[63:0] idValT3;
wire[63:0] idValN4;
wire[63:0] idValS4;
wire[63:0] idValT4;
wire[63:0] idValN5;
wire[63:0] idValS5;
wire[63:0] idValT5;
reg[6:0] idRegW1;
reg[6:0] idRegW2;
reg[6:0] idRegW3;
reg[6:0] idRegW4;
reg[6:0] idRegW5;
reg[63:0] idValW1;
reg[63:0] idValW2;
reg[63:0] idValW3;
reg[63:0] idValW4;
reg[63:0] idValW5;
reg[63:0] idNextPc;
wire[63:0] idImmb1;
wire[63:0] idImmb2;
wire[63:0] idImmb3;
wire[63:0] idImmb4;
wire[63:0] idImmb5;
assign idImmb1 = { idImm1[31]?32'hFFFFFFFF:32'h00000000, idImm1 };
assign idImmb2 = { idImm2[31]?32'hFFFFFFFF:32'h00000000, idImm2 };
assign idImmb3 = { idImm3[31]?32'hFFFFFFFF:32'h00000000, idImm3 };
assign idImmb4 = { idImm4[31]?32'hFFFFFFFF:32'h00000000, idImm4 };
assign idImmb5 = { idImm5[31]?32'hFFFFFFFF:32'h00000000, idImm5 };
RegWGPR wgpr(
clock, idNextPc,
idRegN1, idRegS1, idRegT1, idRegW1,
idRegN2, idRegS2, idRegT2, idRegW2,
idRegN3, idRegS3, idRegT3, idRegW3,
idRegN4, idRegS4, idRegT4, idRegW4,
idRegN5, idRegS5, idRegT5, idRegW5,
idValN1, idValS1, idValT1, idValW1, idImmb1,
idValN2, idValS2, idValT2, idValW2, idImmb2,
idValN3, idValS3, idValT3, idValW3, idImmb3,
idValN4, idValS4, idValT4, idValW4, idImmb4,
idValN5, idValS5, idValT5, idValW5, idImmb5,
regSr, exNextSr2,
regPr, exNextPr2,
regPc, exNextPc2,
regMach, exNextMach2,
regMacl, exNextMacl2,
regSp, exNextSp2,
regGbr, exNextGbr2,
regVbr, exNextVbr2,
regSSr, exNextSSr2,
regSPc, exNextSPc2,
regSGr, exNextSGr2,
regFpul, exNextFpul2,
regFpScr, exNextFpScr2
);
/* D2 */
reg[63:0] regId2Pc;
reg[63:0] regId2Sr;
reg[15:0] regId2CsFl;
reg[127:0] id2IstrWord;
reg[6:0] id2RegN1;
reg[6:0] id2RegS1;
reg[6:0] id2RegT1;
reg[6:0] id2RegN2;
reg[6:0] id2RegS2;
reg[6:0] id2RegT2;
reg[6:0] id2RegN3;
reg[6:0] id2RegS3;
reg[6:0] id2RegT3;
reg[6:0] id2RegN4;
reg[6:0] id2RegS4;
reg[6:0] id2RegT4;
reg[6:0] id2RegN5;
reg[6:0] id2RegS5;
reg[6:0] id2RegT5;
reg[31:0] id2Imm1;
reg[31:0] id2Imm2;
reg[31:0] id2Imm3;
reg[31:0] id2Imm4;
reg[31:0] id2Imm5;
reg[7:0] id2UCmd1;
reg[7:0] id2UCmd2;
reg[7:0] id2UCmd3;
reg[7:0] id2UCmd4;
reg[7:0] id2UCmd5;
reg id2Step;
reg[63:0] id2ValN1;
reg[63:0] id2ValS1;
reg[63:0] id2ValT1;
reg[63:0] id2ValN2;
reg[63:0] id2ValS2;
reg[63:0] id2ValT2;
reg[63:0] id2ValN3;
reg[63:0] id2ValS3;
reg[63:0] id2ValT3;
reg[63:0] id2ValN4;
reg[63:0] id2ValS4;
reg[63:0] id2ValT4;
reg[63:0] id2ValN5;
reg[63:0] id2ValS5;
reg[63:0] id2ValT5;
/* E1, E2 */
reg[127:0] regExPcVal; //PC Instruction Value
reg[15:0] regExCsFl; //Control State Flags
reg[63:0] tRegGenIdPc; //next PC
reg[63:0] regExPc; //ID PC Value
reg[63:0] regExSr; //ID SR Value
wire[1:0] exRegOutOK;
reg[3:0] exStepPc;
reg[3:0] exStepPc2;
reg[6:0] ex1RegN;
reg[6:0] ex1RegS;
reg[6:0] ex1RegT;
wire[6:0] ex1RegO;
reg[63:0] ex1Imm;
reg[7:0] ex1UCmd;
reg[63:0] ex1RegValN;
reg[63:0] ex1RegValS;
reg[63:0] ex1RegValT;
wire[63:0] ex1RegValO;
reg[6:0] ex2RegN;
reg[6:0] ex2RegS;
reg[6:0] ex2RegT;
wire[6:0] ex2RegO;
reg[63:0] ex2Imm;
reg[7:0] ex2UCmd;
reg[63:0] ex2RegValN;
reg[63:0] ex2RegValS;
reg[63:0] ex2RegValT;
wire[63:0] ex2RegValO;
reg[6:0] ex3RegN;
reg[6:0] ex3RegS;
reg[6:0] ex3RegT;
wire[6:0] ex3RegO;
reg[63:0] ex3Imm;
reg[7:0] ex3UCmd;
reg[63:0] ex3RegValN;
reg[63:0] ex3RegValS;
reg[63:0] ex3RegValT;
wire[63:0] ex3RegValO;
reg[6:0] ex4RegN;
reg[6:0] ex4RegS;
reg[6:0] ex4RegT;
wire[6:0] ex4RegO;
reg[63:0] ex4Imm;
reg[7:0] ex4UCmd;
reg[63:0] ex4RegValN;
reg[63:0] ex4RegValS;
reg[63:0] ex4RegValT;
wire[63:0] ex4RegValO;
reg[6:0] ex5RegN;
reg[6:0] ex5RegS;
reg[6:0] ex5RegT;
wire[6:0] ex5RegO;
reg[63:0] ex5Imm;
reg[7:0] ex5UCmd;
reg[63:0] ex5RegValN;
reg[63:0] ex5RegValS;
reg[63:0] ex5RegValT;
wire[63:0] ex5RegValO;
wire[63:0] exMemAddr; //memory address
wire[63:0] exMemData; //memory data (write)
wire exMemLoad; //load from memory
wire exMemStore; //store to memory
wire[4:0] exMemOpMode; //mem op mode
wire[7:0] exMemOpCmd2; //mem EX chain
wire[63:0] exNextSr; //SR in
wire[63:0] exNextPr; //PR in
wire[63:0] exNextPc; //PC in
wire[63:0] exNextMach; //MACH:MACL
wire[63:0] exNextMacl; //MACH:MACL
wire[63:0] exNextGbr; //GBR
wire[63:0] exNextVbr; //VBR
wire[63:0] exNextSSr; //SSR
wire[63:0] exNextSPc; //SPC
wire[63:0] exNextSGr; //SGR (R15)
wire[63:0] exNextSp; //SP out
ExOp64_3C exop1(
clock, reset,
exStepPc, tRegGenIdPc,
exRegOutOK,
ex1RegS, ex1RegValS,
ex1RegT, ex1RegValT,
ex1RegN, ex1RegValN,
ex1RegO, ex1RegValO,
ex1Imm, ex1UCmd,
ex2RegS, ex2RegValS,
ex2RegT, ex2RegValT,
ex2RegN, ex2RegValN,
ex2RegO, ex2RegValO,
ex2Imm, ex2UCmd,
ex3RegS, ex3RegValS,
ex3RegT, ex3RegValT,
ex3RegN, ex3RegValN,
ex3RegO, ex3RegValO,
ex3Imm, ex3UCmd,
ex4RegS, ex4RegValS,
ex4RegT, ex4RegValT,
ex4RegN, ex4RegValN,
ex4RegO, ex4RegValO,
ex4Imm, ex4UCmd,
ex5RegS, ex5RegValS,
ex5RegT, ex5RegValT,
ex5RegN, ex5RegValN,
ex5RegO, ex5RegValO,
ex5Imm, ex5UCmd,
exMemAddr, exMemData,
exMemLoad, exMemStore,
exMemOpMode, exMemOpCmd2,
regSr, exNextSr,
regPr, exNextPr,
regExPc, exNextPc,
regMach, exNextMach,
regMacl, exNextMacl,
regSp, exNextSp,
regGbr, exNextGbr,
regVbr, exNextVbr,
regSSr, exNextSSr,
regSPc, exNextSPc,
regSGr, exNextSGr
);
/* MA1 */
wire[6:0] ma1RegO1;
wire[63:0] ma1ValO1;
wire[6:0] ma1RegO2;
wire[63:0] ma1ValO2;
wire[6:0] ma1RegO3;
wire[63:0] ma1ValO3;
wire[6:0] ma1RegO4;
wire[63:0] ma1ValO4;
wire[6:0] ma1RegO5;
wire[63:0] ma1ValO5;
/* MA2 */
wire[6:0] ma2RegO1;
wire[63:0] ma2ValO1;
wire[6:0] ma2RegO2;
wire[63:0] ma2ValO2;
wire[6:0] ma2RegO3;
wire[63:0] ma2ValO3;
wire[6:0] ma2RegO4;
wire[63:0] ma2ValO4;
wire[6:0] ma2RegO5;
wire[63:0] ma2ValO5;
always @*
begin
regIdCsFl=0;
regIdCsFl[0]=1; //LE
regIdCsFl[1]=regFpScr[19]; //FPSCR.PR
regIdCsFl[2]=regFpScr[20]; //FPSCR.SZ
regIdCsFl[3]=regFpScr[21]; //FPSCR.FR
regIdCsFl[4]=regFpScr[24]; //FPSCR.VE
regIdCsFl[5]=regSr[31]; //SR.JQ
regIdCsFl[6]=regSr[12]; //SR.DQ
regNextRstTok=8'h55;
if(reset)
regNextRstTok=8'h00;
tRegExHold = 0;
if(regIfPcOK!=UMEM_OK_OK)
tRegExHold = 1;
if(exMemLoad||exMemStore)
begin
if(dcfRegOutOK!=UMEM_OK_OK)
tRegExHold = 1;
end
if(exRegOutOK==UMEM_OK_HOLD)
tRegExHold = 1;
dc2MemInData = 0; //STUB
dc2MemOK = UMEM_OK_READY; //STUB
dc2MmioInData = 0; //STUB
// dc2MmioOK = UMEM_OK_READY; //STUB
// dcfMemPcOK = UMEM_OK_READY;
// memIfPcOK = UMEM_OK_READY;
idNextPc = regIdPc + 16;
tRegGenIdPc = regIfPc + 8;
exStepPc = 4;
exNextSp2 = exNextSp;
exNextFpScr2 = regFpScr;
exNextFpul2 = regFpul;
exNextSr2 = exNextSr;
exNextPr2 = exNextPr;
exNextPc2 = exNextPc;
exNextMach2 = exNextMach;
exNextMacl2 = exNextMacl;
exNextGbr2 = exNextGbr;
exNextVbr2 = exNextVbr;
exNextSSr2 = exNextSSr;
exNextSPc2 = exNextSPc;
exNextSGr2 = exNextSGr;
regIfPcVal2 = regIfPcVal;
end
always @ (posedge clock)
begin
regRstTok <= regNextRstTok;
dcfRegInAddr <= exMemAddr;
dcfRegInData <= exMemData;
dcfRegInOE <= exMemLoad;
dcfRegInWR <= exMemStore;
dcfRegInOp <= exMemOpMode;
// idWbRegO <= wbRegO;
// idWbRegValO <= wbRegValO;
if((exMemLoad||exMemStore) &&
(dcfRegOutOK==UMEM_OK_OK))
begin
// idWbRegO <= idRegN;
// idWbRegValO <= dcfRegOutData[31:0];
end
else
begin
// idWbRegO <= wbRegO;
// idWbRegValO <= wbRegValO;
end
if(memIfPcOE)
begin
$display("ExUnit: memIfPcOE");
dc2RegInAddr <= memIfPcAddr;
dc2RegInData <= 0;
dc2RegInOE <= memIfPcOE;
dc2RegInWR <= 0;
dc2RegInOp <= 1;
memIfPcData <= dc2RegOutData;
memIfPcOK <= dc2RegOutOK;
// $display("ExUnit: memIfPcOE: A=%X D=%X OK=%X",
// memIfPcAddr, dc2RegOutData, dc2RegOutOK);
dcfMemInData <= 128'hX;
if(dcfMemPcOE || dcfMemPcWR)
dcfMemPcOK <= UMEM_OK_HOLD;
else
dcfMemPcOK <= UMEM_OK_READY;
end
else
if(dcfMemPcOE || dcfMemPcWR)
begin
dc2RegInAddr <= dcfMemPcAddr;
dc2RegInData <= dcfMemOutData;
dc2RegInOE <= dcfMemPcOE;
dc2RegInWR <= dcfMemPcWR;
dc2RegInOp <= dcfMemOp;
dcfMemInData <= dc2RegOutData;
dcfMemPcOK <= dc2RegOutOK;
memIfPcData <= 128'hX;
if(memIfPcOE)
memIfPcOK <= UMEM_OK_HOLD;
else
memIfPcOK <= UMEM_OK_READY;
end
else
begin
dc2RegInAddr <= 0;
dc2RegInData <= 0;
dc2RegInOE <= 0;
dc2RegInWR <= 0;
dc2RegInOp <= 1;
end
/* IF */
regIfPc <= exNextPc2;
regIfSr <= exNextSr2;
/* D1 */
regIdPc <= regIfPc;
regIdSr <= regIfSr;
idIstrWord <= regIfPcVal;
/* D2 */
regId2Pc <= regIdPc;
regId2Sr <= regId2Sr;
regId2CsFl <= regId2CsFl;
id2IstrWord <= idIstrWord;
id2RegN1 <= idRegN1;
id2RegS1 <= idRegS1;
id2RegT1 <= idRegT1;
id2RegN2 <= idRegN2;
id2RegS2 <= idRegS2;
id2RegT2 <= idRegT2;
id2RegN3 <= idRegN3;
id2RegS3 <= idRegS3;
id2RegT3 <= idRegT3;
id2RegN4 <= idRegN4;
id2RegS4 <= idRegS4;
id2RegT4 <= idRegT4;
id2RegN5 <= idRegN5;
id2RegS5 <= idRegS5;
id2RegT5 <= idRegT5;
id2Imm1 <= idImm1;
id2Imm2 <= idImm2;
id2Imm3 <= idImm3;
id2Imm4 <= idImm4;
id2Imm5 <= idImm5;
id2UCmd1 <= idUCmd1;
id2UCmd2 <= idUCmd2;
id2UCmd3 <= idUCmd3;
id2UCmd4 <= idUCmd4;
id2UCmd5 <= idUCmd5;
id2Step <= idStep;
id2ValN1 <= idValN1;
id2ValS1 <= idValS1;
id2ValT1 <= idValT1;
id2ValN2 <= idValN2;
id2ValS2 <= idValS2;
id2ValT2 <= idValT2;
id2ValN3 <= idValN3;
id2ValS3 <= idValS3;
id2ValT3 <= idValT3;
id2ValN4 <= idValN4;
id2ValS4 <= idValS4;
id2ValT4 <= idValT4;
id2ValN5 <= idValN5;
id2ValS5 <= idValS5;
id2ValT5 <= idValT5;
/* E1, E2 */
regExPcVal <= id2IstrWord;
regExCsFl <= regId2CsFl;
regExPc <= regId2Pc;
regExSr <= regId2Sr;
// exStepPc <= idStepPc;
// exStepPc2 <= idStepPc2;
ex1RegN <= id2RegN1;
ex1RegS <= id2RegS1;
ex1RegT <= id2RegT1;
ex1RegValN <= id2ValN1;
ex1RegValS <= id2ValS1;
ex1RegValT <= id2ValT1;
// ex1Imm <= id2Imm1;
ex1Imm <= { id2Imm1[31] ? 32'hFFFFFFFF : 32'h0, id2Imm1 };
ex1UCmd <= id2UCmd1;
ex2RegN <= id2RegN2;
ex2RegS <= id2RegS2;
ex2RegT <= id2RegT2;
ex2RegValN <= id2ValN2;
ex2RegValS <= id2ValS2;
ex2RegValT <= id2ValT2;
// ex2Imm <= id2Imm2;
ex2Imm <= { id2Imm2[31] ? 32'hFFFFFFFF : 32'h0, id2Imm2 };
ex2UCmd <= id2UCmd2;
ex3RegN <= id2RegN3;
ex3RegS <= id2RegS3;
ex3RegT <= id2RegT3;
ex3RegValN <= id2ValN3;
ex3RegValS <= id2ValS3;
ex3RegValT <= id2ValT3;
// ex3Imm <= id2Imm3;
ex3Imm <= { id2Imm3[31] ? 32'hFFFFFFFF : 32'h0, id2Imm3 };
ex3UCmd <= id2UCmd3;
ex4RegN <= id2RegN4;
ex4RegS <= id2RegS4;
ex4RegT <= id2RegT4;
ex4RegValN <= id2ValN4;
ex4RegValS <= id2ValS4;
ex4RegValT <= id2ValT4;
// ex4Imm <= id2Imm4;
ex4Imm <= { id2Imm4[31] ? 32'hFFFFFFFF : 32'h0, id2Imm4 };
ex4UCmd <= id2UCmd4;
ex5RegN <= id2RegN5;
ex5RegS <= id2RegS5;
ex5RegT <= id2RegT5;
ex5RegValN <= id2ValN5;
ex5RegValS <= id2ValS5;
ex5RegValT <= id2ValT5;
// ex5Imm <= id2Imm5;
ex5Imm <= { id2Imm5[31] ? 32'hFFFFFFFF : 32'h0, id2Imm5 };
ex5UCmd <= id2UCmd5;
/* M1 */
idRegW1 <= ex1RegO;
idValW1 <= ex1RegValO;
idRegW2 <= ex2RegO;
idRegW3 <= ex3RegO;
idRegW4 <= ex4RegO;
idRegW5 <= ex5RegO;
idValW2 <= ex2RegValO;
idValW3 <= ex3RegValO;
idValW4 <= ex4RegValO;
idValW5 <= ex5RegValO;
/* ma1RegO1;
ma1ValO1;
ma1RegO2;
ma1ValO2;
ma1RegO3;
ma1ValO3;
ma1RegO4;
ma1ValO4;
ma1RegO5;
ma1ValO5; */
/* M2 */
/* WB */
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [31:0] a;
reg [31:0] b;
wire [2:0] bf; buf BF0 (bf[0], a[0]),
BF1 (bf[1], a[1]),
BF2 (bf[2], a[2]);
// verilator lint_off IMPLICIT
not #(0.108) NT0 (nt0, a[0]);
and #1 AN0 (an0, a[0], b[0]);
nand #(2,3) ND0 (nd0, a[0], b[0], b[1]);
or OR0 (or0, a[0], b[0]);
nor NR0 (nr0, a[0], b[0], b[2]);
xor (xo0, a[0], b[0]);
xnor (xn0, a[0], b[0], b[2]);
// verilator lint_on IMPLICIT
parameter BITS=32;
wire [BITS-1:0] ba;
buf BARRAY [BITS-1:0] (ba, a);
`ifdef verilator
specify
specparam CDS_LIBNAME = "foobar";
(nt0 *> nt0) = (0, 0);
endspecify
specify
// delay parameters
specparam
a$A1$Y = 1.0,
b$A0$Z = 1.0;
// path delays
(A1 *> Q) = (a$A1$Y, a$A1$Y);
(A0 *> Q) = (b$A0$Y, a$A0$Z);
endspecify
`endif
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
a <= 32'h18f6b034;
b <= 32'h834bf892;
end
if (cyc==2) begin
a <= 32'h529ab56f;
b <= 32'h7835a237;
if (bf !== 3'b100) $stop;
if (nt0 !== 1'b1) $stop;
if (an0 !== 1'b0) $stop;
if (nd0 !== 1'b1) $stop;
if (or0 !== 1'b0) $stop;
if (nr0 !== 1'b1) $stop;
if (xo0 !== 1'b0) $stop;
if (xn0 !== 1'b1) $stop;
if (ba != 32'h18f6b034) $stop;
end
if (cyc==3) begin
if (bf !== 3'b111) $stop;
if (nt0 !== 1'b0) $stop;
if (an0 !== 1'b1) $stop;
if (nd0 !== 1'b0) $stop;
if (or0 !== 1'b1) $stop;
if (nr0 !== 1'b0) $stop;
if (xo0 !== 1'b0) $stop;
if (xn0 !== 1'b0) $stop;
end
if (cyc==4) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFBBP_PP_SYMBOL_V
`define SKY130_FD_SC_LP__SDFBBP_PP_SYMBOL_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sdfbbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
input SET_B ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFBBP_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O32AI_BEHAVIORAL_V
`define SKY130_FD_SC_MS__O32AI_BEHAVIORAL_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__o32ai (
Y ,
A1,
A2,
A3,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A3, A1, A2 );
nor nor1 (nor1_out , B1, B2 );
or or0 (or0_out_Y, nor1_out, nor0_out);
buf buf0 (Y , or0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O32AI_BEHAVIORAL_V |
//////////////////////////////////////////////////////////////////////////////////
// d_SC_deviders_p_lfs_XOR.v for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: BCH Page Decoder
// Module Name: d_SC_parallel_lfs_XOR_***
// File Name: d_SC_deviders_p_lfs_XOR.v
//
// Version: v1.0.1-256B_T14
//
// Description: Parallel linear feedback shift XOR for data area
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.1
// - minor modification for releasing
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`include "d_SC_parameters.vh"
`timescale 1ns / 1ps
module d_SC_parallel_lfs_XOR_001(i_message, i_cur_remainder, o_nxt_remainder);
input wire [`D_SC_P_LVL-1:0] i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire [`D_SC_GF_ORDER*(`D_SC_P_LVL+1)-1:0] w_parallel_wire;
genvar i;
generate
for (i=0; i<`D_SC_P_LVL; i=i+1)
begin: lfs_XOR_blade_enclosure
d_SC_serial_lfs_XOR_001 lfs_XOR_001_blade(
.i_message(i_message[i]),
.i_cur_remainder(w_parallel_wire[`D_SC_GF_ORDER*(i+2)-1:`D_SC_GF_ORDER*(i+1)]),
.o_nxt_remainder(w_parallel_wire[`D_SC_GF_ORDER*(i+1)-1:`D_SC_GF_ORDER*(i)] ) );
end
endgenerate
assign w_parallel_wire[`D_SC_GF_ORDER*(`D_SC_P_LVL+1)-1:`D_SC_GF_ORDER*(`D_SC_P_LVL)] = i_cur_remainder[`D_SC_GF_ORDER-1:0];
assign o_nxt_remainder[`D_SC_GF_ORDER-1:0] = w_parallel_wire[`D_SC_GF_ORDER-1:0];
endmodule
module d_SC_parallel_lfs_XOR_003(i_message, i_cur_remainder, o_nxt_remainder);
input wire [`D_SC_P_LVL-1:0] i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire [`D_SC_GF_ORDER*(`D_SC_P_LVL+1)-1:0] w_parallel_wire;
genvar i;
generate
for (i=0; i<`D_SC_P_LVL; i=i+1)
begin: lfs_XOR_blade_enclosure
d_SC_serial_lfs_XOR_003 lfs_XOR_003_blade(
.i_message(i_message[i]),
.i_cur_remainder(w_parallel_wire[`D_SC_GF_ORDER*(i+2)-1:`D_SC_GF_ORDER*(i+1)]),
.o_nxt_remainder(w_parallel_wire[`D_SC_GF_ORDER*(i+1)-1:`D_SC_GF_ORDER*(i)] ) );
end
endgenerate
assign w_parallel_wire[`D_SC_GF_ORDER*(`D_SC_P_LVL+1)-1:`D_SC_GF_ORDER*(`D_SC_P_LVL)] = i_cur_remainder[`D_SC_GF_ORDER-1:0];
assign o_nxt_remainder[`D_SC_GF_ORDER-1:0] = w_parallel_wire[`D_SC_GF_ORDER-1:0];
endmodule
module d_SC_parallel_lfs_XOR_005(i_message, i_cur_remainder, o_nxt_remainder);
input wire [`D_SC_P_LVL-1:0] i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire [`D_SC_GF_ORDER*(`D_SC_P_LVL+1)-1:0] w_parallel_wire;
genvar i;
generate
for (i=0; i<`D_SC_P_LVL; i=i+1)
begin: lfs_XOR_blade_enclosure
d_SC_serial_lfs_XOR_005 lfs_XOR_005_blade(
.i_message(i_message[i]),
.i_cur_remainder(w_parallel_wire[`D_SC_GF_ORDER*(i+2)-1:`D_SC_GF_ORDER*(i+1)]),
.o_nxt_remainder(w_parallel_wire[`D_SC_GF_ORDER*(i+1)-1:`D_SC_GF_ORDER*(i)] ) );
end
endgenerate
assign w_parallel_wire[`D_SC_GF_ORDER*(`D_SC_P_LVL+1)-1:`D_SC_GF_ORDER*(`D_SC_P_LVL)] = i_cur_remainder[`D_SC_GF_ORDER-1:0];
assign o_nxt_remainder[`D_SC_GF_ORDER-1:0] = w_parallel_wire[`D_SC_GF_ORDER-1:0];
endmodule
module d_SC_parallel_lfs_XOR_007(i_message, i_cur_remainder, o_nxt_remainder);
input wire [`D_SC_P_LVL-1:0] i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire [`D_SC_GF_ORDER*(`D_SC_P_LVL+1)-1:0] w_parallel_wire;
genvar i;
generate
for (i=0; i<`D_SC_P_LVL; i=i+1)
begin: lfs_XOR_blade_enclosure
d_SC_serial_lfs_XOR_007 lfs_XOR_007_blade(
.i_message(i_message[i]),
.i_cur_remainder(w_parallel_wire[`D_SC_GF_ORDER*(i+2)-1:`D_SC_GF_ORDER*(i+1)]),
.o_nxt_remainder(w_parallel_wire[`D_SC_GF_ORDER*(i+1)-1:`D_SC_GF_ORDER*(i)] ) );
end
endgenerate
assign w_parallel_wire[`D_SC_GF_ORDER*(`D_SC_P_LVL+1)-1:`D_SC_GF_ORDER*(`D_SC_P_LVL)] = i_cur_remainder[`D_SC_GF_ORDER-1:0];
assign o_nxt_remainder[`D_SC_GF_ORDER-1:0] = w_parallel_wire[`D_SC_GF_ORDER-1:0];
endmodule
module d_SC_parallel_lfs_XOR_009(i_message, i_cur_remainder, o_nxt_remainder);
input wire [`D_SC_P_LVL-1:0] i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire [`D_SC_GF_ORDER*(`D_SC_P_LVL+1)-1:0] w_parallel_wire;
genvar i;
generate
for (i=0; i<`D_SC_P_LVL; i=i+1)
begin: lfs_XOR_blade_enclosure
d_SC_serial_lfs_XOR_009 lfs_XOR_009_blade(
.i_message(i_message[i]),
.i_cur_remainder(w_parallel_wire[`D_SC_GF_ORDER*(i+2)-1:`D_SC_GF_ORDER*(i+1)]),
.o_nxt_remainder(w_parallel_wire[`D_SC_GF_ORDER*(i+1)-1:`D_SC_GF_ORDER*(i)] ) );
end
endgenerate
assign w_parallel_wire[`D_SC_GF_ORDER*(`D_SC_P_LVL+1)-1:`D_SC_GF_ORDER*(`D_SC_P_LVL)] = i_cur_remainder[`D_SC_GF_ORDER-1:0];
assign o_nxt_remainder[`D_SC_GF_ORDER-1:0] = w_parallel_wire[`D_SC_GF_ORDER-1:0];
endmodule
module d_SC_parallel_lfs_XOR_011(i_message, i_cur_remainder, o_nxt_remainder);
input wire [`D_SC_P_LVL-1:0] i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire [`D_SC_GF_ORDER*(`D_SC_P_LVL+1)-1:0] w_parallel_wire;
genvar i;
generate
for (i=0; i<`D_SC_P_LVL; i=i+1)
begin: lfs_XOR_blade_enclosure
d_SC_serial_lfs_XOR_011 lfs_XOR_011_blade(
.i_message(i_message[i]),
.i_cur_remainder(w_parallel_wire[`D_SC_GF_ORDER*(i+2)-1:`D_SC_GF_ORDER*(i+1)]),
.o_nxt_remainder(w_parallel_wire[`D_SC_GF_ORDER*(i+1)-1:`D_SC_GF_ORDER*(i)] ) );
end
endgenerate
assign w_parallel_wire[`D_SC_GF_ORDER*(`D_SC_P_LVL+1)-1:`D_SC_GF_ORDER*(`D_SC_P_LVL)] = i_cur_remainder[`D_SC_GF_ORDER-1:0];
assign o_nxt_remainder[`D_SC_GF_ORDER-1:0] = w_parallel_wire[`D_SC_GF_ORDER-1:0];
endmodule
module d_SC_parallel_lfs_XOR_013(i_message, i_cur_remainder, o_nxt_remainder);
input wire [`D_SC_P_LVL-1:0] i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire [`D_SC_GF_ORDER*(`D_SC_P_LVL+1)-1:0] w_parallel_wire;
genvar i;
generate
for (i=0; i<`D_SC_P_LVL; i=i+1)
begin: lfs_XOR_blade_enclosure
d_SC_serial_lfs_XOR_013 lfs_XOR_013_blade(
.i_message(i_message[i]),
.i_cur_remainder(w_parallel_wire[`D_SC_GF_ORDER*(i+2)-1:`D_SC_GF_ORDER*(i+1)]),
.o_nxt_remainder(w_parallel_wire[`D_SC_GF_ORDER*(i+1)-1:`D_SC_GF_ORDER*(i)] ) );
end
endgenerate
assign w_parallel_wire[`D_SC_GF_ORDER*(`D_SC_P_LVL+1)-1:`D_SC_GF_ORDER*(`D_SC_P_LVL)] = i_cur_remainder[`D_SC_GF_ORDER-1:0];
assign o_nxt_remainder[`D_SC_GF_ORDER-1:0] = w_parallel_wire[`D_SC_GF_ORDER-1:0];
endmodule
module d_SC_parallel_lfs_XOR_015(i_message, i_cur_remainder, o_nxt_remainder);
input wire [`D_SC_P_LVL-1:0] i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire [`D_SC_GF_ORDER*(`D_SC_P_LVL+1)-1:0] w_parallel_wire;
genvar i;
generate
for (i=0; i<`D_SC_P_LVL; i=i+1)
begin: lfs_XOR_blade_enclosure
d_SC_serial_lfs_XOR_015 lfs_XOR_015_blade(
.i_message(i_message[i]),
.i_cur_remainder(w_parallel_wire[`D_SC_GF_ORDER*(i+2)-1:`D_SC_GF_ORDER*(i+1)]),
.o_nxt_remainder(w_parallel_wire[`D_SC_GF_ORDER*(i+1)-1:`D_SC_GF_ORDER*(i)] ) );
end
endgenerate
assign w_parallel_wire[`D_SC_GF_ORDER*(`D_SC_P_LVL+1)-1:`D_SC_GF_ORDER*(`D_SC_P_LVL)] = i_cur_remainder[`D_SC_GF_ORDER-1:0];
assign o_nxt_remainder[`D_SC_GF_ORDER-1:0] = w_parallel_wire[`D_SC_GF_ORDER-1:0];
endmodule
module d_SC_parallel_lfs_XOR_017(i_message, i_cur_remainder, o_nxt_remainder);
input wire [`D_SC_P_LVL-1:0] i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire [`D_SC_GF_ORDER*(`D_SC_P_LVL+1)-1:0] w_parallel_wire;
genvar i;
generate
for (i=0; i<`D_SC_P_LVL; i=i+1)
begin: lfs_XOR_blade_enclosure
d_SC_serial_lfs_XOR_017 lfs_XOR_017_blade(
.i_message(i_message[i]),
.i_cur_remainder(w_parallel_wire[`D_SC_GF_ORDER*(i+2)-1:`D_SC_GF_ORDER*(i+1)]),
.o_nxt_remainder(w_parallel_wire[`D_SC_GF_ORDER*(i+1)-1:`D_SC_GF_ORDER*(i)] ) );
end
endgenerate
assign w_parallel_wire[`D_SC_GF_ORDER*(`D_SC_P_LVL+1)-1:`D_SC_GF_ORDER*(`D_SC_P_LVL)] = i_cur_remainder[`D_SC_GF_ORDER-1:0];
assign o_nxt_remainder[`D_SC_GF_ORDER-1:0] = w_parallel_wire[`D_SC_GF_ORDER-1:0];
endmodule
module d_SC_parallel_lfs_XOR_019(i_message, i_cur_remainder, o_nxt_remainder);
input wire [`D_SC_P_LVL-1:0] i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire [`D_SC_GF_ORDER*(`D_SC_P_LVL+1)-1:0] w_parallel_wire;
genvar i;
generate
for (i=0; i<`D_SC_P_LVL; i=i+1)
begin: lfs_XOR_blade_enclosure
d_SC_serial_lfs_XOR_019 lfs_XOR_019_blade(
.i_message(i_message[i]),
.i_cur_remainder(w_parallel_wire[`D_SC_GF_ORDER*(i+2)-1:`D_SC_GF_ORDER*(i+1)]),
.o_nxt_remainder(w_parallel_wire[`D_SC_GF_ORDER*(i+1)-1:`D_SC_GF_ORDER*(i)] ) );
end
endgenerate
assign w_parallel_wire[`D_SC_GF_ORDER*(`D_SC_P_LVL+1)-1:`D_SC_GF_ORDER*(`D_SC_P_LVL)] = i_cur_remainder[`D_SC_GF_ORDER-1:0];
assign o_nxt_remainder[`D_SC_GF_ORDER-1:0] = w_parallel_wire[`D_SC_GF_ORDER-1:0];
endmodule
module d_SC_parallel_lfs_XOR_021(i_message, i_cur_remainder, o_nxt_remainder);
input wire [`D_SC_P_LVL-1:0] i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire [`D_SC_GF_ORDER*(`D_SC_P_LVL+1)-1:0] w_parallel_wire;
genvar i;
generate
for (i=0; i<`D_SC_P_LVL; i=i+1)
begin: lfs_XOR_blade_enclosure
d_SC_serial_lfs_XOR_021 lfs_XOR_021_blade(
.i_message(i_message[i]),
.i_cur_remainder(w_parallel_wire[`D_SC_GF_ORDER*(i+2)-1:`D_SC_GF_ORDER*(i+1)]),
.o_nxt_remainder(w_parallel_wire[`D_SC_GF_ORDER*(i+1)-1:`D_SC_GF_ORDER*(i)] ) );
end
endgenerate
assign w_parallel_wire[`D_SC_GF_ORDER*(`D_SC_P_LVL+1)-1:`D_SC_GF_ORDER*(`D_SC_P_LVL)] = i_cur_remainder[`D_SC_GF_ORDER-1:0];
assign o_nxt_remainder[`D_SC_GF_ORDER-1:0] = w_parallel_wire[`D_SC_GF_ORDER-1:0];
endmodule
module d_SC_parallel_lfs_XOR_023(i_message, i_cur_remainder, o_nxt_remainder);
input wire [`D_SC_P_LVL-1:0] i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire [`D_SC_GF_ORDER*(`D_SC_P_LVL+1)-1:0] w_parallel_wire;
genvar i;
generate
for (i=0; i<`D_SC_P_LVL; i=i+1)
begin: lfs_XOR_blade_enclosure
d_SC_serial_lfs_XOR_023 lfs_XOR_023_blade(
.i_message(i_message[i]),
.i_cur_remainder(w_parallel_wire[`D_SC_GF_ORDER*(i+2)-1:`D_SC_GF_ORDER*(i+1)]),
.o_nxt_remainder(w_parallel_wire[`D_SC_GF_ORDER*(i+1)-1:`D_SC_GF_ORDER*(i)] ) );
end
endgenerate
assign w_parallel_wire[`D_SC_GF_ORDER*(`D_SC_P_LVL+1)-1:`D_SC_GF_ORDER*(`D_SC_P_LVL)] = i_cur_remainder[`D_SC_GF_ORDER-1:0];
assign o_nxt_remainder[`D_SC_GF_ORDER-1:0] = w_parallel_wire[`D_SC_GF_ORDER-1:0];
endmodule
module d_SC_parallel_lfs_XOR_025(i_message, i_cur_remainder, o_nxt_remainder);
input wire [`D_SC_P_LVL-1:0] i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire [`D_SC_GF_ORDER*(`D_SC_P_LVL+1)-1:0] w_parallel_wire;
genvar i;
generate
for (i=0; i<`D_SC_P_LVL; i=i+1)
begin: lfs_XOR_blade_enclosure
d_SC_serial_lfs_XOR_025 lfs_XOR_025_blade(
.i_message(i_message[i]),
.i_cur_remainder(w_parallel_wire[`D_SC_GF_ORDER*(i+2)-1:`D_SC_GF_ORDER*(i+1)]),
.o_nxt_remainder(w_parallel_wire[`D_SC_GF_ORDER*(i+1)-1:`D_SC_GF_ORDER*(i)] ) );
end
endgenerate
assign w_parallel_wire[`D_SC_GF_ORDER*(`D_SC_P_LVL+1)-1:`D_SC_GF_ORDER*(`D_SC_P_LVL)] = i_cur_remainder[`D_SC_GF_ORDER-1:0];
assign o_nxt_remainder[`D_SC_GF_ORDER-1:0] = w_parallel_wire[`D_SC_GF_ORDER-1:0];
endmodule
module d_SC_parallel_lfs_XOR_027(i_message, i_cur_remainder, o_nxt_remainder);
input wire [`D_SC_P_LVL-1:0] i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire [`D_SC_GF_ORDER*(`D_SC_P_LVL+1)-1:0] w_parallel_wire;
genvar i;
generate
for (i=0; i<`D_SC_P_LVL; i=i+1)
begin: lfs_XOR_blade_enclosure
d_SC_serial_lfs_XOR_027 lfs_XOR_027_blade(
.i_message(i_message[i]),
.i_cur_remainder(w_parallel_wire[`D_SC_GF_ORDER*(i+2)-1:`D_SC_GF_ORDER*(i+1)]),
.o_nxt_remainder(w_parallel_wire[`D_SC_GF_ORDER*(i+1)-1:`D_SC_GF_ORDER*(i)] ) );
end
endgenerate
assign w_parallel_wire[`D_SC_GF_ORDER*(`D_SC_P_LVL+1)-1:`D_SC_GF_ORDER*(`D_SC_P_LVL)] = i_cur_remainder[`D_SC_GF_ORDER-1:0];
assign o_nxt_remainder[`D_SC_GF_ORDER-1:0] = w_parallel_wire[`D_SC_GF_ORDER-1:0];
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2007 Corgan Enterprises LLC
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
`include "../../../../usrp/firmware/include/fpga_regs_common.v"
`include "../../../../usrp/firmware/include/fpga_regs_standard.v"
module radar_rx(clk_i,rst_i,ena_i,dbg_i,pulse_num_i,rx_in_i_i,
rx_in_q_i,rx_i_o,rx_q_o,rx_strobe_o);
input clk_i;
input rst_i;
input ena_i;
input dbg_i;
input [15:0] rx_in_i_i;
input [15:0] rx_in_q_i;
input [15:0] pulse_num_i;
output [15:0] rx_i_o;
output [15:0] rx_q_o;
output reg rx_strobe_o;
reg [15:0] count;
always @(posedge clk_i)
if (rst_i | ~ena_i)
count <= 16'b0;
else
count <= count + 16'b1;
wire [31:0] fifo_inp = dbg_i ? {count[15:0],pulse_num_i[15:0]} : {rx_in_i_i,rx_in_q_i};
// Buffer incoming samples every clock
wire [31:0] fifo_out;
reg fifo_ack;
wire fifo_empty;
// Use model if simulating, otherwise Altera Megacell
`ifdef SIMULATION
fifo_1clk #(32, 2048) buffer(.clock(clk_i),.sclr(rst_i),
.data(fifo_inp),.wrreq(ena_i),
.rdreq(fifo_ack),.q(fifo_out),
.empty(fifo_empty));
`else
fifo32_2k buffer(.clock(clk_i),.sclr(rst_i),
.data(fifo_inp),.wrreq(ena_i),
.rdreq(fifo_ack),.q(fifo_out),
.empty(fifo_empty));
`endif
// Write samples to rx_fifo every third clock
`define ST_FIFO_IDLE 3'b001
`define ST_FIFO_STROBE 3'b010
`define ST_FIFO_ACK 3'b100
reg [2:0] state;
always @(posedge clk_i)
if (rst_i)
begin
state <= `ST_FIFO_IDLE;
rx_strobe_o <= 1'b0;
fifo_ack <= 1'b0;
end
else
case (state)
`ST_FIFO_IDLE:
if (!fifo_empty)
begin
// Tell rx_fifo sample is ready
rx_strobe_o <= 1'b1;
state <= `ST_FIFO_STROBE;
end
`ST_FIFO_STROBE:
begin
rx_strobe_o <= 1'b0;
// Ack our FIFO
fifo_ack <= 1'b1;
state <= `ST_FIFO_ACK;
end
`ST_FIFO_ACK:
begin
fifo_ack <= 1'b0;
state <= `ST_FIFO_IDLE;
end
endcase // case(state)
assign rx_i_o = fifo_out[31:16];
assign rx_q_o = fifo_out[15:0];
endmodule // radar_rx
|
// bsg_adder_one_hot
//
// adder whose inputs and outputs are all one hot signals
//
// the adder is by default a modulo adder, so it will wrap around
// if there is a carry out.
//
// if you don't want modulo, then make the output signal wide enough; i.e. set output_width_p>=2*width_p-1
//
`include "bsg_defines.v"
module bsg_adder_one_hot #(parameter `BSG_INV_PARAM(width_p), parameter output_width_p=width_p)
(input [width_p-1:0] a_i
, input [width_p-1:0] b_i
, output [output_width_p-1:0] o
);
genvar i,j;
initial assert (output_width_p >= width_p)
else begin $error("%m: unsupported output_width_p < width_p");
$finish();
end
for (i=0; i < output_width_p; i++) // for each output wire
begin: rof
wire [width_p-1:0] aggregate;
// for each input a_i
// compute what bit is necessary to make it total to i
// including wrap around in the modulo case
for (j=0; j < width_p; j=j+1)
begin: rof2
if (i < j)
begin: rof3
if (output_width_p+i-j < width_p)
assign aggregate[j] = a_i[j] & b_i[output_width_p+i-j];
else
assign aggregate[j] = 1'b0;
end
else
if (i-j < width_p)
assign aggregate[j] = a_i[j] & b_i[i-j];
else
assign aggregate[j] = 1'b0;
end // block: rof2
assign o[i] = | aggregate;
end // block: rof
endmodule
`BSG_ABSTRACT_MODULE(bsg_adder_one_hot)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A21BO_2_V
`define SKY130_FD_SC_HS__A21BO_2_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog wrapper for a21bo with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a21bo.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a21bo_2 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
sky130_fd_sc_hs__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a21bo_2 (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A21BO_2_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
module sky130_fd_io__top_gpio_ovtv2 ( IN, IN_H, TIE_HI_ESD, TIE_LO_ESD, AMUXBUS_A,
AMUXBUS_B, PAD, PAD_A_ESD_0_H, PAD_A_ESD_1_H, PAD_A_NOESD_H,
VCCD, VCCHIB,VDDA, VDDIO, VDDIO_Q, VSSA, VSSD, VSSIO, VSSIO_Q, VSWITCH,
ANALOG_EN, ANALOG_POL, ANALOG_SEL, DM, ENABLE_H, ENABLE_INP_H, ENABLE_VDDA_H, ENABLE_VDDIO, ENABLE_VSWITCH_H, HLD_H_N,
HLD_OVR, IB_MODE_SEL, INP_DIS, OE_N, OUT, SLOW, SLEW_CTL, VTRIP_SEL, HYS_TRIM, VINREF );
input OUT;
input OE_N;
input HLD_H_N;
input ENABLE_H;
input ENABLE_INP_H;
input ENABLE_VDDA_H;
input ENABLE_VDDIO;
input ENABLE_VSWITCH_H;
input INP_DIS;
input VTRIP_SEL;
input HYS_TRIM;
input SLOW;
input [1:0] SLEW_CTL;
input HLD_OVR;
input ANALOG_EN;
input ANALOG_SEL;
input ANALOG_POL;
input [2:0] DM;
input [1:0] IB_MODE_SEL;
input VINREF;
inout VDDIO;
inout VDDIO_Q;
inout VDDA;
inout VCCD;
inout VSWITCH;
inout VCCHIB;
inout VSSA;
inout VSSD;
inout VSSIO_Q;
inout VSSIO;
inout PAD;
inout PAD_A_NOESD_H,PAD_A_ESD_0_H,PAD_A_ESD_1_H;
inout AMUXBUS_A;
inout AMUXBUS_B;
output IN;
output IN_H;
output TIE_HI_ESD, TIE_LO_ESD;
wire hld_h_n_del;
wire hld_h_n_buf;
reg [2:0] dm_final;
reg [1:0] slew_ctl_final;
reg slow_final, vtrip_sel_final, inp_dis_final, out_final, oe_n_final, hld_ovr_final, hys_trim_final, analog_en_final,analog_en_vdda, analog_en_vswitch,analog_en_vddio_q;
reg [1:0] ib_mode_sel_final;
wire [2:0] dm_del;
wire [1:0] slew_ctl_del;
wire [1:0] ib_mode_sel_del;
wire slow_del, vtrip_sel_del, inp_dis_del, out_del, oe_n_del, hld_ovr_del, hys_trim_del;
wire [2:0] dm_buf;
wire [1:0] slew_ctl_buf;
wire [1:0] ib_mode_sel_buf;
wire slow_buf, vtrip_sel_buf, inp_dis_buf, out_buf, oe_n_buf, hld_ovr_buf, hys_trim_buf;
reg notifier_dm, notifier_slow, notifier_oe_n, notifier_out, notifier_vtrip_sel, notifier_hld_ovr, notifier_inp_dis;
reg notifier_slew_ctl, notifier_ib_mode_sel, notifier_hys_trim;
reg notifier_enable_h, notifier, dummy_notifier1;
assign hld_h_n_buf = hld_h_n_del;
assign hld_ovr_buf = hld_ovr_del;
assign dm_buf = dm_del;
assign inp_dis_buf = inp_dis_del;
assign vtrip_sel_buf = vtrip_sel_del;
assign slow_buf = slow_del;
assign oe_n_buf = oe_n_del;
assign out_buf = out_del;
assign ib_mode_sel_buf = ib_mode_sel_del;
assign slew_ctl_buf = slew_ctl_del;
assign hys_trim_buf = hys_trim_del;
specify
( INP_DIS => IN) = (0:0:0 , 0:0:0);
( INP_DIS => IN_H) = (0:0:0 , 0:0:0);
if ( IB_MODE_SEL[1]==1'b0 & IB_MODE_SEL[0]==1'b1 ) ( PAD => IN) = (0:0:0 , 0:0:0);
if ( IB_MODE_SEL[1]==1'b0 & IB_MODE_SEL[0]==1'b1 ) ( PAD => IN_H) = (0:0:0 , 0:0:0);
if ( OE_N==1'b0 & DM[2]==1'b1 & DM[1]==1'b1 & DM[0]==1'b0 & SLOW==1'b0 ) ( OUT => PAD) = (0:0:0 , 0:0:0);
if ( OE_N==1'b0 & DM[2]==1'b1 & DM[1]==1'b1 & DM[0]==1'b0 & SLOW==1'b1 ) ( OUT => PAD) = (0:0:0 , 0:0:0);
if ( OE_N==1'b0 & DM[2]==1'b1 & DM[1]==1'b0 & DM[0]==1'b0 & SLOW==1'b0 ) ( OUT => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( DM[2]==1'b1 & DM[1]==1'b0 & DM[0]==1'b0 & SLOW==1'b1 & SLEW_CTL[1]==1'b0 & SLEW_CTL[0]==1'b0 ) ( OE_N => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( OE_N==1'b0 & DM[2]==1'b1 & DM[1]==1'b1 & DM[0]==1'b1 & SLOW==1'b0 ) ( OUT => PAD ) = (0:0:0 , 0:0:0);
if ( DM[2]==1'b1 & DM[1]==1'b0 & DM[0]==1'b0 & SLOW==1'b1 & SLEW_CTL[1]==1'b0 & SLEW_CTL[0]==1'b1 ) ( OE_N => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( OE_N==1'b0 & DM[2]==1'b1 & DM[1]==1'b1 & DM[0]==1'b1 & SLOW==1'b1 ) ( OUT => PAD) = (0:0:0 , 0:0:0);
if ( OE_N==1'b0 & DM[2]==1'b1 & DM[1]==1'b0 & DM[0]==1'b1 & SLOW==1'b0 ) ( OUT => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( DM[2]==1'b1 & DM[1]==1'b1 & DM[0]==1'b0 & SLOW==1'b0 ) ( OE_N => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( OE_N==1'b0 & DM[2]==1'b1 & DM[1]==1'b0 & DM[0]==1'b1 & SLOW==1'b1 ) ( OUT => PAD ) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( DM[2]==1'b1 & DM[1]==1'b1 & DM[0]==1'b0 & SLOW==1'b1 ) ( OE_N => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( DM[2]==1'b1 & DM[1]==1'b0 & DM[0]==1'b0 & SLOW==1'b1 & SLEW_CTL[1]==1'b1 & SLEW_CTL[0]==1'b0 ) ( OE_N => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( DM[2]==1'b1 & DM[1]==1'b0 & DM[0]==1'b0 & SLOW==1'b0 ) ( OE_N => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( IB_MODE_SEL[1]==1'b1 & HYS_TRIM==1'b0 ) ( PAD => IN) = (0:0:0 , 0:0:0);
if ( IB_MODE_SEL[1]==1'b1 & HYS_TRIM==1'b0 ) ( PAD => IN_H) = (0:0:0 , 0:0:0);
if ( DM[2]==1'b1 & DM[1]==1'b0 & DM[0]==1'b0 & SLOW==1'b1 & SLEW_CTL[1]==1'b1 & SLEW_CTL[0]==1'b1 ) ( OE_N => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( DM[2]==1'b1 & DM[1]==1'b1 & DM[0]==1'b1 & SLOW==1'b0 ) ( OE_N => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( IB_MODE_SEL[1]==1'b1 & HYS_TRIM==1'b1 ) ( PAD => IN) = (0:0:0 , 0:0:0);
if ( IB_MODE_SEL[1]==1'b1 & HYS_TRIM==1'b1 ) ( PAD => IN_H) = (0:0:0 , 0:0:0);
if ( DM[2]==1'b1 & DM[1]==1'b1 & DM[0]==1'b1 & SLOW==1'b1 ) ( OE_N => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( OE_N==1'b0 & DM[2]==1'b1 & DM[1]==1'b0 & DM[0]==1'b0 & SLOW==1'b1 & SLEW_CTL[1]==1'b1 & SLEW_CTL[0]==1'b0 ) ( OUT=> PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( DM[2]==1'b1 & DM[1]==1'b0 & DM[0]==1'b1 & SLOW==1'b0 ) ( OE_N => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( OE_N==1'b0 & DM[2]==1'b1 & DM[1]==1'b0 & DM[0]==1'b0 & SLOW==1'b1 & SLEW_CTL[1]==1'b1 & SLEW_CTL[0]==1'b1 ) ( OUT => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( DM[2]==1'b1 & DM[1]==1'b0 & DM[0]==1'b1 & SLOW==1'b1 ) ( OE_N => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( DM[2]==1'b0 & DM[1]==1'b1 & DM[0]==1'b0 & SLOW==1'b0 ) ( OE_N => PAD ) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( DM[2]==1'b0 & DM[1]==1'b1 & DM[0]==1'b0 & SLOW==1'b1 ) ( OE_N => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( DM[2]==1'b0 & DM[1]==1'b1 & DM[0]==1'b1 & SLOW==1'b0 ) ( OE_N => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( DM[2]==1'b0 & DM[1]==1'b1 & DM[0]==1'b1 & SLOW==1'b1 ) ( OE_N => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( OE_N==1'b0 & DM[2]==1'b0 & DM[1]==1'b1 & DM[0]==1'b0 & SLOW==1'b0 ) ( OUT => PAD) = (0:0:0 , 0:0:0);
if ( OE_N==1'b0 & DM[2]==1'b1 & DM[1]==1'b0 & DM[0]==1'b0 & SLOW==1'b1 & SLEW_CTL[1]==1'b0 & SLEW_CTL[0]==1'b0 ) ( OUT => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( OE_N==1'b0 & DM[2]==1'b0 & DM[1]==1'b1 & DM[0]==1'b0 & SLOW==1'b1 ) ( OUT => PAD) = (0:0:0 , 0:0:0);
if ( OE_N==1'b0 & DM[2]==1'b1 & DM[1]==1'b0 & DM[0]==1'b0 & SLOW==1'b1 & SLEW_CTL[1]==1'b0 & SLEW_CTL[0]==1'b1 ) ( OUT => PAD) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
if ( IB_MODE_SEL[1]==1'b0 & IB_MODE_SEL[0]==1'b0 & VTRIP_SEL==1'b0 ) ( PAD => IN) = (0:0:0 , 0:0:0);
if ( IB_MODE_SEL[1]==1'b0 & IB_MODE_SEL[0]==1'b0 & VTRIP_SEL==1'b0 ) ( PAD => IN_H) = (0:0:0 , 0:0:0);
if ( OE_N==1'b0 & DM[2]==1'b0 & DM[1]==1'b1 & DM[0]==1'b1 & SLOW==1'b0 ) ( OUT => PAD) = (0:0:0 , 0:0:0);
if ( IB_MODE_SEL[1]==1'b0 & IB_MODE_SEL[0]==1'b0 & VTRIP_SEL==1'b1 ) ( PAD => IN) = (0:0:0 , 0:0:0);
if ( IB_MODE_SEL[1]==1'b0 & IB_MODE_SEL[0]==1'b0 & VTRIP_SEL==1'b1 ) ( PAD => IN_H) = (0:0:0 , 0:0:0);
if ( OE_N==1'b0 & DM[2]==1'b0 & DM[1]==1'b1 & DM[0]==1'b1 & SLOW==1'b1 ) ( OUT => PAD) = (0:0:0 , 0:0:0);
$width (negedge HLD_H_N, (15.500:0:15.500));
$width (posedge HLD_H_N, (15.500:0:15.500));
$width (negedge HLD_OVR, (15.500:0:15.500));
$width (posedge HLD_OVR, (15.500:0:15.500));
specparam tsetup = 5;
specparam tsetup1 = 0;
specparam thold = 5;
$setuphold (posedge ENABLE_H, negedge HLD_H_N, tsetup, thold, notifier_enable_h);
$setuphold (posedge ENABLE_VDDIO, posedge ENABLE_H, tsetup1, thold, notifier_enable_h);
$setuphold (negedge ENABLE_H, negedge ENABLE_VDDIO, tsetup1, thold, notifier_enable_h);
$setuphold (negedge HLD_H_N, posedge HLD_OVR, tsetup, thold, notifier_hld_ovr, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, hld_ovr_del);
$setuphold (negedge HLD_H_N, negedge HLD_OVR, tsetup, thold, notifier_hld_ovr, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, hld_ovr_del);
$setuphold (negedge HLD_H_N, posedge DM[2], tsetup, thold, notifier_dm, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, dm_del[2]);
$setuphold (negedge HLD_H_N, negedge DM[2], tsetup, thold, notifier_dm, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, dm_del[2]);
$setuphold (negedge HLD_H_N, posedge DM[1], tsetup, thold, notifier_dm, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, dm_del[1]);
$setuphold (negedge HLD_H_N, negedge DM[1], tsetup, thold, notifier_dm, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, dm_del[1]);
$setuphold (negedge HLD_H_N, posedge DM[0], tsetup, thold, notifier_dm, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, dm_del[0]);
$setuphold (negedge HLD_H_N, negedge DM[0], tsetup, thold, notifier_dm, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, dm_del[0]);
$setuphold (negedge HLD_H_N, posedge INP_DIS, tsetup, thold, notifier_inp_dis, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, inp_dis_del);
$setuphold (negedge HLD_H_N, negedge INP_DIS, tsetup, thold, notifier_inp_dis, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, inp_dis_del);
$setuphold (negedge HLD_H_N, posedge VTRIP_SEL, tsetup, thold, notifier_vtrip_sel, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, vtrip_sel_del);
$setuphold (negedge HLD_H_N, negedge VTRIP_SEL, tsetup, thold, notifier_vtrip_sel, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, vtrip_sel_del);
$setuphold (negedge HLD_H_N, posedge HYS_TRIM, tsetup, thold, notifier_hys_trim, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, hys_trim_del);
$setuphold (negedge HLD_H_N, negedge HYS_TRIM, tsetup, thold, notifier_hys_trim, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, hys_trim_del);
$setuphold (negedge HLD_H_N, posedge SLOW, tsetup, thold, notifier_slow, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, slow_del);
$setuphold (negedge HLD_H_N, negedge SLOW, tsetup, thold, notifier_slow, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, slow_del);
$setuphold (negedge HLD_H_N, posedge OE_N, tsetup, thold, notifier_oe_n, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, oe_n_del);
$setuphold (negedge HLD_H_N, negedge OE_N, tsetup, thold, notifier_oe_n, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, oe_n_del);
$setuphold (negedge HLD_H_N, posedge OUT, tsetup, thold, notifier_out, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, out_del);
$setuphold (negedge HLD_H_N, negedge OUT, tsetup, thold, notifier_out, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, out_del);
$setuphold (negedge HLD_H_N, posedge SLEW_CTL[1], tsetup, thold, notifier_slew_ctl, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, slew_ctl_del[1]);
$setuphold (negedge HLD_H_N, negedge SLEW_CTL[1], tsetup, thold, notifier_slew_ctl, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, slew_ctl_del[1]);
$setuphold (negedge HLD_H_N, posedge SLEW_CTL[0], tsetup, thold, notifier_slew_ctl, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, slew_ctl_del[0]);
$setuphold (negedge HLD_H_N, negedge SLEW_CTL[0], tsetup, thold, notifier_slew_ctl, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, slew_ctl_del[0]);
$setuphold (negedge HLD_H_N, posedge IB_MODE_SEL[1], tsetup, thold, notifier_ib_mode_sel, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, ib_mode_sel_del[1]);
$setuphold (negedge HLD_H_N, negedge IB_MODE_SEL[1], tsetup, thold, notifier_ib_mode_sel, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, ib_mode_sel_del[1]);
$setuphold (negedge HLD_H_N, posedge IB_MODE_SEL[0], tsetup, thold, notifier_ib_mode_sel, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, ib_mode_sel_del[0]);
$setuphold (negedge HLD_H_N, negedge IB_MODE_SEL[0], tsetup, thold, notifier_ib_mode_sel, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, ib_mode_sel_del[0]);
$setuphold (posedge HLD_H_N, posedge HLD_OVR, tsetup, thold, notifier_hld_ovr, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, hld_ovr_del);
$setuphold (posedge HLD_H_N, negedge HLD_OVR, tsetup, thold, notifier_hld_ovr, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, hld_ovr_del);
$setuphold (posedge HLD_H_N, posedge DM[2], tsetup, thold, notifier_dm, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, dm_del[2]);
$setuphold (posedge HLD_H_N, negedge DM[2], tsetup, thold, notifier_dm, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, dm_del[2]);
$setuphold (posedge HLD_H_N, posedge DM[1], tsetup, thold, notifier_dm, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, dm_del[1]);
$setuphold (posedge HLD_H_N, negedge DM[1], tsetup, thold, notifier_dm, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, dm_del[1]);
$setuphold (posedge HLD_H_N, posedge DM[0], tsetup, thold, notifier_dm, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, dm_del[0]);
$setuphold (posedge HLD_H_N, negedge DM[0], tsetup, thold, notifier_dm, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, dm_del[0]);
$setuphold (posedge HLD_H_N, posedge INP_DIS, tsetup, thold, notifier_inp_dis, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, inp_dis_del);
$setuphold (posedge HLD_H_N, negedge INP_DIS, tsetup, thold, notifier_inp_dis, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, inp_dis_del);
$setuphold (posedge HLD_H_N, posedge VTRIP_SEL, tsetup, thold, notifier_vtrip_sel, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, vtrip_sel_del);
$setuphold (posedge HLD_H_N, negedge VTRIP_SEL, tsetup, thold, notifier_vtrip_sel, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, vtrip_sel_del);
$setuphold (posedge HLD_H_N, posedge HYS_TRIM, tsetup, thold, notifier_hys_trim, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, hys_trim_del);
$setuphold (posedge HLD_H_N, negedge HYS_TRIM, tsetup, thold, notifier_hys_trim, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, hys_trim_del);
$setuphold (posedge HLD_H_N, posedge SLOW, tsetup, thold, notifier_slow, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, slow_del);
$setuphold (posedge HLD_H_N, negedge SLOW, tsetup, thold, notifier_slow, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, slow_del);
$setuphold (posedge HLD_H_N, posedge OE_N, tsetup, thold, notifier_oe_n, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, oe_n_del);
$setuphold (posedge HLD_H_N, negedge OE_N, tsetup, thold, notifier_oe_n, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, oe_n_del);
$setuphold (posedge HLD_H_N, posedge OUT, tsetup, thold, notifier_out, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, out_del);
$setuphold (posedge HLD_H_N, negedge OUT, tsetup, thold, notifier_out, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, out_del);
$setuphold (posedge HLD_H_N, posedge SLEW_CTL[1], tsetup, thold, notifier_slew_ctl, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, slew_ctl_del[1]);
$setuphold (posedge HLD_H_N, negedge SLEW_CTL[1], tsetup, thold, notifier_slew_ctl, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, slew_ctl_del[1]);
$setuphold (posedge HLD_H_N, posedge SLEW_CTL[0], tsetup, thold, notifier_slew_ctl, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, slew_ctl_del[0]);
$setuphold (posedge HLD_H_N, negedge SLEW_CTL[0], tsetup, thold, notifier_slew_ctl, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, slew_ctl_del[0]);
$setuphold (posedge HLD_H_N, posedge IB_MODE_SEL[1], tsetup, thold, notifier_ib_mode_sel, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, ib_mode_sel_del[1]);
$setuphold (posedge HLD_H_N, negedge IB_MODE_SEL[1], tsetup, thold, notifier_ib_mode_sel, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, ib_mode_sel_del[1]);
$setuphold (posedge HLD_H_N, posedge IB_MODE_SEL[0], tsetup, thold, notifier_ib_mode_sel, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, ib_mode_sel_del[0]);
$setuphold (posedge HLD_H_N, negedge IB_MODE_SEL[0], tsetup, thold, notifier_ib_mode_sel, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_h_n_del, ib_mode_sel_del[0]);
$setuphold (posedge HLD_OVR, negedge HLD_H_N, tsetup, thold, notifier_hld_ovr, ENABLE_H==1'b1, ENABLE_H==1'b1, hld_ovr_del, hld_h_n_del);
$setuphold (posedge DM[2], negedge HLD_H_N, tsetup, thold, notifier_dm, ENABLE_H==1'b1, ENABLE_H==1'b1, dm_del[2], hld_h_n_del);
$setuphold (posedge DM[1], negedge HLD_H_N, tsetup, thold, notifier_dm, ENABLE_H==1'b1, ENABLE_H==1'b1, dm_del[1], hld_h_n_del);
$setuphold (posedge DM[0], negedge HLD_H_N, tsetup, thold, notifier_dm, ENABLE_H==1'b1, ENABLE_H==1'b1, dm_del[0], hld_h_n_del);
$setuphold (posedge INP_DIS, negedge HLD_H_N, tsetup, thold, notifier_inp_dis, ENABLE_H==1'b1, ENABLE_H==1'b1, inp_dis_del, hld_h_n_del);
$setuphold (posedge VTRIP_SEL, negedge HLD_H_N, tsetup, thold, notifier_vtrip_sel, ENABLE_H==1'b1, ENABLE_H==1'b1, vtrip_sel_del, hld_h_n_del);
$setuphold (posedge HYS_TRIM, negedge HLD_H_N, tsetup, thold, notifier_hys_trim, ENABLE_H==1'b1, ENABLE_H==1'b1, hys_trim_del, hld_h_n_del);
$setuphold (posedge SLOW, negedge HLD_H_N, tsetup, thold, notifier_slow, ENABLE_H==1'b1, ENABLE_H==1'b1, slow_del, hld_h_n_del);
$setuphold (posedge OE_N, negedge HLD_H_N, tsetup, thold, notifier_oe_n, ENABLE_H==1'b1, ENABLE_H==1'b1, oe_n_del, hld_h_n_del);
$setuphold (posedge OUT, negedge HLD_H_N, tsetup, thold, notifier_out, ENABLE_H==1'b1, ENABLE_H==1'b1, out_del, hld_h_n_del);
$setuphold (posedge SLEW_CTL[1], negedge HLD_H_N, tsetup, thold, notifier_slew_ctl, ENABLE_H==1'b1, ENABLE_H==1'b1, slew_ctl_del[1], hld_h_n_del);
$setuphold (posedge SLEW_CTL[0], negedge HLD_H_N, tsetup, thold, notifier_slew_ctl, ENABLE_H==1'b1, ENABLE_H==1'b1, slew_ctl_del[0], hld_h_n_del);
$setuphold (posedge IB_MODE_SEL[1], negedge HLD_H_N, tsetup, thold, notifier_ib_mode_sel, ENABLE_H==1'b1, ENABLE_H==1'b1, ib_mode_sel_del[1], hld_h_n_del);
$setuphold (posedge IB_MODE_SEL[0], negedge HLD_H_N, tsetup, thold, notifier_ib_mode_sel, ENABLE_H==1'b1, ENABLE_H==1'b1, ib_mode_sel_del[0], hld_h_n_del);
endspecify
wire pwr_good_amux = ((hld_h_n_buf===0 || ENABLE_H===0) ? 1:(VCCD===1)) && (VSSD===0) && (VSSA===0) && (VSSIO_Q===0);
wire pwr_good_output_driver = (VDDIO===1) && (VDDIO_Q===1)&& (VSSIO===0) && (VSSD===0) && (VSSA===0) ;
wire pwr_good_hold_ovr_mode = (VDDIO_Q===1) && (VDDIO===1) && (VSSD===0) && (VCCHIB===1);
wire pwr_good_active_mode = (VDDIO_Q===1) && (VDDIO===1) && (VSSD===0) && (VCCD===1);
wire pwr_good_hold_mode = (VDDIO_Q===1) && (VDDIO===1) && (VSSD===0);
wire pwr_good_active_mode_vdda = (VDDA===1) && (VSSD===0) && (VCCD===1);
wire pwr_good_hold_mode_vdda = (VDDA===1) && (VSSD===0);
wire pwr_good_inpbuff_hv = (VDDIO_Q===1) && (inp_dis_final===0 && dm_final!==3'b000 && ib_mode_sel_final===2'b01 ? VCCHIB===1 : 1) && (VSSD===0);
wire pwr_good_inpbuff_lv = (VDDIO_Q===1) && (VSSD===0) && (VCCHIB===1);
wire pwr_good_analog_en_vdda = (VDDA===1) && (VSSD===0) && (VSSA===0) ;
wire pwr_good_analog_en_vddio_q = (VDDIO_Q ===1) && (VSSD===0) && (VSSA===0) ;
wire pwr_good_analog_en_vswitch = (VSWITCH ===1) && (VSSD===0) && (VSSA===0) ;
wire pwr_good_amux_vccd = ((hld_h_n_buf===0 || ENABLE_H===0) ? 1:(VCCD===1));
parameter MAX_WARNING_COUNT = 100;
wire pad_tristate = oe_n_final === 1 || dm_final === 3'b000 || dm_final === 3'b001;
wire x_on_pad = !pwr_good_output_driver
|| (dm_final !== 3'b000 && dm_final !== 3'b001 && oe_n_final===1'bx)
|| (^dm_final[2:0] === 1'bx && oe_n_final===1'b0)
|| (slow_final===1'bx && dm_final !== 3'b000 && dm_final !== 3'b001 && oe_n_final===1'b0)
|| (slow_final===1'b1 && ^slew_ctl_final[1:0] ===1'bx && dm_final === 3'b100 && oe_n_final===1'b0);
`ifdef SKY130_FD_IO_TOP_GPIO_OVTV2_SLOW_BEHV
parameter SLOW_1_DELAY= 70 ;
parameter SLOW_0_DELAY= 40;
`else
parameter SLOW_1_DELAY= 0;
parameter SLOW_0_DELAY= 0;
`endif
`ifdef SKY130_FD_IO_TOP_GPIO_OVTV2_SLEW_BEHV
parameter SLEW_00_DELAY= 127 ;
parameter SLEW_01_DELAY= 109;
parameter SLEW_10_DELAY= 193;
parameter SLEW_11_DELAY= 136;
`else
parameter SLEW_00_DELAY= 0 ;
parameter SLEW_01_DELAY= 0;
parameter SLEW_10_DELAY= 0;
parameter SLEW_11_DELAY= 0;
`endif
integer slow_1_delay,slow_0_delay,slow_delay,slew_00_delay,slew_01_delay,slew_10_delay,slew_11_delay;
initial slow_1_delay = SLOW_1_DELAY;
initial slow_0_delay = SLOW_0_DELAY;
initial slew_00_delay = SLEW_00_DELAY;
initial slew_01_delay = SLEW_01_DELAY;
initial slew_10_delay = SLEW_10_DELAY;
initial slew_11_delay = SLEW_11_DELAY;
always @(*)
begin
if (SLOW===1)
begin
if (DM[2]===1 && DM[1]===0 && DM[0]===0)
begin
`ifdef SKY130_FD_IO_TOP_GPIO_OVTV2_SLEW_BEHV
if (SLEW_CTL[1] ===0 && SLEW_CTL[0] ===0)
slow_delay = slew_00_delay;
else if (SLEW_CTL[1] ===0 && SLEW_CTL[0] ===1)
slow_delay = slew_01_delay;
else if (SLEW_CTL[1] ===1 && SLEW_CTL[0] ===0)
slow_delay = slew_10_delay;
else if (SLEW_CTL[1] ===1 && SLEW_CTL[0] ===1)
slow_delay = slew_11_delay;
`else
slow_delay = slow_1_delay;
`endif
end
else
slow_delay = slow_1_delay;
end
else
slow_delay = slow_0_delay;
end
bufif1 (pull1, strong0) #slow_delay dm2 (PAD, out_final, x_on_pad===1 ? 1'bx : (pad_tristate===0 && dm_final===3'b010));
bufif1 (strong1, pull0) #slow_delay dm3 (PAD, out_final, x_on_pad===1 ? 1'bx : (pad_tristate===0 && dm_final===3'b011));
bufif1 (highz1, strong0) #slow_delay dm4 (PAD, out_final, x_on_pad===1 ? 1'bx : (pad_tristate===0 && dm_final===3'b100));
bufif1 (strong1, highz0) #slow_delay dm5 (PAD, out_final, x_on_pad===1 ? 1'bx : (pad_tristate===0 && dm_final===3'b101));
bufif1 (strong1, strong0) #slow_delay dm6 (PAD, out_final, x_on_pad===1 ? 1'bx : (pad_tristate===0 && dm_final===3'b110));
bufif1 (pull1, pull0) #slow_delay dm7 (PAD, out_final, x_on_pad===1 ? 1'bx : (pad_tristate===0 && dm_final===3'b111));
tran pad_esd_1 (PAD,PAD_A_NOESD_H);
tran pad_esd_2 (PAD,PAD_A_ESD_0_H);
tran pad_esd_3 (PAD,PAD_A_ESD_1_H);
wire x_on_in_hv = (ENABLE_H===0 && ^ENABLE_INP_H===1'bx)
|| (inp_dis_final===1'bx && ^dm_final[2:0]!==1'bx && dm_final !== 3'b000)
|| (^ENABLE_H===1'bx)
|| (inp_dis_final===0 && ^dm_final[2:0] === 1'bx)
|| (^ib_mode_sel_final===1'bx && inp_dis_final===0 && dm_final !== 3'b000)
|| (vtrip_sel_final===1'bx && inp_dis_final===0 && dm_final !== 3'b000 && ib_mode_sel_final===2'b00)
|| (^ENABLE_VDDIO===1'bx && inp_dis_final===0 && dm_final !== 3'b000 && ib_mode_sel_final===2'b01)
|| (ib_mode_sel_final[1]===1'b1 && VINREF !== 1'b1 && inp_dis_final===0 && dm_final !== 3'b000)
|| (ib_mode_sel_final[1]===1'b1 && hys_trim_final===1'bx && inp_dis_final===0 && dm_final !== 3'b000);
wire x_on_in_lv = (ENABLE_H===0 && ^ENABLE_VDDIO===1'bx)
|| (ENABLE_H===0 && ^ENABLE_INP_H===1'bx)
|| (inp_dis_final===1'bx && ^dm_final[2:0]!==1'bx && dm_final !== 3'b000)
|| (^ENABLE_H===1'bx)
|| (inp_dis_final===0 && ^dm_final[2:0] === 1'bx)
|| (^ib_mode_sel_final===1'bx && inp_dis_final===0 && dm_final !== 3'b000)
|| (vtrip_sel_final===1'bx && inp_dis_final===0 && dm_final !== 3'b000 && ib_mode_sel_final===2'b00)
|| (^ENABLE_VDDIO===1'bx && inp_dis_final===0 && dm_final !== 3'b000 )
|| (ib_mode_sel_final[1]===1'b1 && VINREF !== 1'b1 && inp_dis_final===0 && dm_final !== 3'b000)
|| (ib_mode_sel_final[1]===1'b1 && hys_trim_final===1'bx && inp_dis_final===0 && dm_final !== 3'b000);
wire disable_inp_buff = ENABLE_H===1 ? (dm_final===3'b000 || inp_dis_final===1) : ENABLE_INP_H===0;
assign IN_H = (x_on_in_hv===1 || pwr_good_inpbuff_hv===0) ? 1'bx : (disable_inp_buff===1 ? 0 : (^PAD===1'bx ? 1'bx : PAD));
wire disable_inp_buff_lv = ENABLE_H===1 ? (dm_final===3'b000 || inp_dis_final===1) : ENABLE_VDDIO===0;
assign IN = (x_on_in_lv ===1 || pwr_good_inpbuff_lv===0) ? 1'bx : (disable_inp_buff_lv===1 ? 0 : (^PAD===1'bx ? 1'bx : PAD));
assign TIE_HI_ESD = VDDIO===1'b1 ? 1'b1 : 1'bx;
assign TIE_LO_ESD = VSSIO===1'b0 ? 1'b0 : 1'bx;
wire functional_mode_amux = (pwr_good_analog_en_vdda ===1 && pwr_good_analog_en_vddio_q ===1 && pwr_good_analog_en_vswitch ===1 );
wire x_on_analog_en_vdda = (pwr_good_analog_en_vdda !==1
|| (functional_mode_amux ==1 && (ENABLE_H !==0 && ^hld_h_n_buf === 1'bx) || (hld_h_n_buf!== 0 && ^ENABLE_H=== 1'bx) || pwr_good_amux_vccd !==1 )
|| (functional_mode_amux ==1 && (hld_h_n_buf ===1 && ENABLE_H===1 && ^ANALOG_EN === 1'bx && ENABLE_VDDA_H ===1 && ENABLE_VSWITCH_H===1 ) || (hld_h_n_buf ===1 && ENABLE_H===1 && ANALOG_EN ===0 && ^ENABLE_VDDA_H ===1'bx) ));
wire zero_on_analog_en_vdda = ( (pwr_good_analog_en_vdda ===1 && ENABLE_VDDA_H ===0)
|| (pwr_good_analog_en_vdda ===1 && pwr_good_analog_en_vddio_q ===1 && hld_h_n_buf===0)
|| (pwr_good_analog_en_vdda ===1 && pwr_good_analog_en_vddio_q ===1 && ENABLE_H===0)
|| (pwr_good_analog_en_vdda ===1 && pwr_good_analog_en_vddio_q ===1 && pwr_good_amux_vccd && ANALOG_EN===0) );
wire x_on_analog_en_vddio_q = ( pwr_good_analog_en_vddio_q !==1
|| (functional_mode_amux ==1 && (ENABLE_H !==0 && ^hld_h_n_buf === 1'bx) || (hld_h_n_buf!== 0 && ^ENABLE_H=== 1'bx) || pwr_good_amux_vccd !==1 )
|| (functional_mode_amux ==1 && (hld_h_n_buf ===1 && ENABLE_H===1 && ^ANALOG_EN === 1'bx && ENABLE_VDDA_H ===1 && ENABLE_VSWITCH_H===1 ) ));
wire zero_on_analog_en_vddio_q = ( (pwr_good_analog_en_vddio_q ===1 && hld_h_n_buf===0)
|| (pwr_good_analog_en_vddio_q ===1 && ENABLE_H===0)
|| (pwr_good_analog_en_vddio_q ===1 && pwr_good_amux_vccd && ANALOG_EN===0) );
wire x_on_analog_en_vswitch = (pwr_good_analog_en_vswitch !==1
|| (functional_mode_amux ==1 && (ENABLE_H !==0 && ^hld_h_n_buf === 1'bx) || (hld_h_n_buf!== 0 && ^ENABLE_H=== 1'bx) || pwr_good_amux_vccd !==1 )
|| (functional_mode_amux ==1 && (hld_h_n_buf ===1 && ENABLE_H===1 && ^ANALOG_EN === 1'bx && ENABLE_VDDA_H ===1 && ENABLE_VSWITCH_H===1 ) || (hld_h_n_buf ===1 && ENABLE_H===1 && ANALOG_EN ===0 && ^ENABLE_VSWITCH_H ===1'bx) ));
wire zero_on_analog_en_vswitch = ( (pwr_good_analog_en_vswitch ===1 && ENABLE_VSWITCH_H ===0)
|| (pwr_good_analog_en_vswitch ===1 && pwr_good_analog_en_vddio_q ===1 && hld_h_n_buf===0)
|| (pwr_good_analog_en_vswitch ===1 && pwr_good_analog_en_vddio_q ===1 && ENABLE_H===0)
|| (pwr_good_analog_en_vswitch ===1 && pwr_good_analog_en_vddio_q ===1 && pwr_good_amux_vccd && ANALOG_EN===0) );
always @(*)
begin : LATCH_dm
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && ^hld_h_n_buf===1'bx))
begin
dm_final <= 3'bxxx;
end
else if (ENABLE_H===0)
begin
dm_final <= 3'b000;
end
else if (hld_h_n_buf===1)
begin
dm_final <= (^dm_buf[2:0] === 1'bx || !pwr_good_active_mode) ? 3'bxxx : dm_buf;
end
end
always @(notifier_enable_h or notifier_dm)
begin
disable LATCH_dm; dm_final <= 3'bxxx;
end
always @(*)
begin : LATCH_inp_dis
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && ^hld_h_n_buf===1'bx))
begin
inp_dis_final <= 1'bx;
end
else if (ENABLE_H===0)
begin
inp_dis_final <= 1'b1;
end
else if (hld_h_n_buf===1)
begin
inp_dis_final <= (^inp_dis_buf === 1'bx || !pwr_good_active_mode) ? 1'bx : inp_dis_buf;
end
end
always @(notifier_enable_h or notifier_inp_dis)
begin
disable LATCH_inp_dis; inp_dis_final <= 1'bx;
end
always @(*)
begin : LATCH_ib_mode_sel
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && ^hld_h_n_buf===1'bx))
begin
ib_mode_sel_final <= 2'bxx;
end
else if (ENABLE_H===0)
begin
ib_mode_sel_final <= 2'b00;
end
else if (hld_h_n_buf===1)
begin
ib_mode_sel_final <= (^ib_mode_sel_buf[1:0] === 1'bx || !pwr_good_active_mode) ? 2'bxx : ib_mode_sel_buf;
end
end
always @(notifier_enable_h or notifier_ib_mode_sel)
begin
disable LATCH_ib_mode_sel; ib_mode_sel_final <= 2'bxx;
end
always @(*)
begin : LATCH_slew_ctl_final
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && ^hld_h_n_buf===1'bx))
begin
slew_ctl_final <= 2'bxx;
end
else if (ENABLE_H===0)
begin
slew_ctl_final <= 2'b00;
end
else if (hld_h_n_buf===1)
begin
slew_ctl_final <= (^slew_ctl_buf[1:0] === 1'bx || !pwr_good_active_mode) ? 2'bxx : slew_ctl_buf;
end
end
always @(notifier_enable_h or notifier_slew_ctl)
begin
disable LATCH_slew_ctl_final; slew_ctl_final <= 2'bxx;
end
always @(*)
begin : LATCH_vtrip_sel
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && ^hld_h_n_buf===1'bx))
begin
vtrip_sel_final <= 1'bx;
end
else if (ENABLE_H===0)
begin
vtrip_sel_final <= 1'b0;
end
else if (hld_h_n_buf===1)
begin
vtrip_sel_final <= (^vtrip_sel_buf === 1'bx || !pwr_good_active_mode) ? 1'bx : vtrip_sel_buf;
end
end
always @(notifier_enable_h or notifier_vtrip_sel)
begin
disable LATCH_vtrip_sel; vtrip_sel_final <= 1'bx;
end
always @(*)
begin : LATCH_hys_trim
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && ^hld_h_n_buf===1'bx))
begin
hys_trim_final <= 1'bx;
end
else if (ENABLE_H===0)
begin
hys_trim_final <= 1'b0;
end
else if (hld_h_n_buf===1)
begin
hys_trim_final <= (^hys_trim_buf === 1'bx || !pwr_good_active_mode) ? 1'bx : hys_trim_buf;
end
end
always @(notifier_enable_h or notifier_hys_trim)
begin
disable LATCH_hys_trim; hys_trim_final <= 1'bx;
end
always @(*)
begin : LATCH_slow
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && ^hld_h_n_buf===1'bx))
begin
slow_final <= 1'bx;
end
else if (ENABLE_H===0)
begin
slow_final <= 1'b0;
end
else if (hld_h_n_buf===1)
begin
slow_final <= (^slow_buf === 1'bx || !pwr_good_active_mode) ? 1'bx : slow_buf;
end
end
always @(notifier_enable_h or notifier_slow)
begin
disable LATCH_slow; slow_final <= 1'bx;
end
always @(*)
begin : LATCH_hld_ovr
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && ^hld_h_n_buf===1'bx))
begin
hld_ovr_final <= 1'bx;
end
else if (ENABLE_H===0)
begin
hld_ovr_final <= 1'b0;
end
else if (hld_h_n_buf===1)
begin
hld_ovr_final <= (^hld_ovr_buf === 1'bx || !pwr_good_active_mode) ? 1'bx : hld_ovr_buf;
end
end
always @(notifier_enable_h or notifier_hld_ovr)
begin
disable LATCH_hld_ovr; hld_ovr_final <= 1'bx;
end
always @(*)
begin : LATCH_oe_n
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && (^hld_h_n_buf===1'bx || (hld_h_n_buf===0 && hld_ovr_final===1'bx)|| (hld_h_n_buf===1 && hld_ovr_final===1'bx))))
begin
oe_n_final <= 1'bx;
end
else if (ENABLE_H===0)
begin
oe_n_final <= 1'b1;
end
else if (hld_h_n_buf===1 || hld_ovr_final===1)
begin
oe_n_final <= (^oe_n_buf === 1'bx || !pwr_good_hold_ovr_mode) ? 1'bx : oe_n_buf;
end
end
always @(notifier_enable_h or notifier_oe_n)
begin
disable LATCH_oe_n; oe_n_final <= 1'bx;
end
always @(*)
begin : LATCH_out
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && (^hld_h_n_buf===1'bx ||(hld_h_n_buf===0 && hld_ovr_final===1'bx)||(hld_h_n_buf===1 && hld_ovr_final===1'bx))))
begin
out_final <= 1'bx;
end
else if (ENABLE_H===0)
begin
out_final <= 1'b1;
end
else if (hld_h_n_buf===1 || hld_ovr_final===1)
begin
out_final <= (^out_buf === 1'bx || !pwr_good_hold_ovr_mode) ? 1'bx : out_buf;
end
end
always @(notifier_enable_h or notifier_out)
begin
disable LATCH_out; out_final <= 1'bx;
end
always @(*)
begin
if (x_on_analog_en_vdda ===1 )
begin
analog_en_vdda <= 1'bx;
end
else if ( zero_on_analog_en_vdda ===1 )
begin
analog_en_vdda <= 1'b0;
end
else if (x_on_analog_en_vdda !==1 && zero_on_analog_en_vdda !==1)
begin
analog_en_vdda <= ANALOG_EN;
end
if (x_on_analog_en_vddio_q ===1 )
begin
analog_en_vddio_q <= 1'bx;
end
else if ( zero_on_analog_en_vddio_q ===1 )
begin
analog_en_vddio_q <= 1'b0;
end
else if ( x_on_analog_en_vddio_q !==1 && zero_on_analog_en_vddio_q !==1)
begin
analog_en_vddio_q <= ANALOG_EN;
end
if (x_on_analog_en_vswitch ===1 )
begin
analog_en_vswitch <= 1'bx;
end
else if ( zero_on_analog_en_vswitch ===1 )
begin
analog_en_vswitch <= 1'b0;
end
else if (x_on_analog_en_vswitch !==1 && zero_on_analog_en_vswitch !==1)
begin
analog_en_vswitch <= ANALOG_EN;
end
if ( (analog_en_vswitch ===1'bx && analog_en_vdda ===1'bx) || (analog_en_vswitch ===1'bx && analog_en_vddio_q ===1'bx) || (analog_en_vddio_q ===1'bx && analog_en_vdda ===1'bx ) )
begin
analog_en_final <= 1'bx;
end
else if (analog_en_vdda ===1'bx && (analog_en_vddio_q ===1 ||analog_en_vswitch===1 ))
begin
analog_en_final <= 1'bx;
end
else if (analog_en_vddio_q ===1'bx && (analog_en_vdda ===1 ||analog_en_vswitch===1 ))
begin
analog_en_final <= 1'bx;
end
else if (analog_en_vswitch===1'bx && (analog_en_vdda ===1 || analog_en_vddio_q ===1 ))
begin
analog_en_final <= 1'bx;
end
else if ((analog_en_vdda ===0 && analog_en_vddio_q ===0 )|| (analog_en_vdda ===0 && analog_en_vswitch===0 ) || (analog_en_vddio_q ===0 && analog_en_vswitch===0 ))
begin
analog_en_final <=0;
end
else if (analog_en_vdda ===1 && analog_en_vddio_q ===1 && analog_en_vswitch ===1)
begin
analog_en_final <=1;
end
end
wire [2:0] amux_select = {ANALOG_SEL, ANALOG_POL, out_buf};
wire invalid_controls_amux = (analog_en_final===1'bx && inp_dis_final===1)
|| !pwr_good_amux
|| (analog_en_final===1 && ^amux_select[2:0] === 1'bx && inp_dis_final===1);
wire enable_pad_amuxbus_a = invalid_controls_amux ? 1'bx : (amux_select===3'b001 || amux_select===3'b010) && (analog_en_final===1);
wire enable_pad_amuxbus_b = invalid_controls_amux ? 1'bx : (amux_select===3'b101 || amux_select===3'b110) && (analog_en_final===1);
wire enable_pad_vssio_q = invalid_controls_amux ? 1'bx : (amux_select===3'b100 || amux_select===3'b000) && (analog_en_final===1);
wire enable_pad_vddio_q = invalid_controls_amux ? 1'bx : (amux_select===3'b011 || amux_select===3'b111) && (analog_en_final===1);
tranif1 pad_amuxbus_a (PAD, AMUXBUS_A, enable_pad_amuxbus_a);
tranif1 pad_amuxbus_b (PAD, AMUXBUS_B, enable_pad_amuxbus_b);
bufif1 pad_vddio_q (PAD, VDDIO_Q, enable_pad_vddio_q);
bufif1 pad_vssio_q (PAD, VSSIO_Q, enable_pad_vssio_q);
reg dis_err_msgs;
integer msg_count_pad,msg_count_pad1,msg_count_pad2,msg_count_pad3,msg_count_pad4,msg_count_pad5,msg_count_pad6,msg_count_pad7,msg_count_pad8,msg_count_pad9,msg_count_pad10,msg_count_pad11,msg_count_pad12;
initial
begin
dis_err_msgs = 1'b1;
msg_count_pad = 0;
msg_count_pad1 = 0;
msg_count_pad2 = 0;
msg_count_pad3 = 0;
msg_count_pad4 = 0;
msg_count_pad5 = 0;
msg_count_pad6 = 0;
msg_count_pad7 = 0;
msg_count_pad8 = 0;
msg_count_pad9 = 0;
msg_count_pad10 = 0;
msg_count_pad11 = 0;
msg_count_pad12 = 0;
`ifdef SKY130_FD_IO_TOP_GPIO_OVTV2_DIS_ERR_MSGS
`else
#1;
dis_err_msgs = 1'b0;
`endif
end
wire #100 error_enable_vddio = (ENABLE_VDDIO===0 && ENABLE_H===1);
event event_error_enable_vddio;
always @(error_enable_vddio)
begin
if (!dis_err_msgs)
begin
if (error_enable_vddio===1)
begin
msg_count_pad = msg_count_pad + 1;
->event_error_enable_vddio;
if (msg_count_pad <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : Enable_h (= %b) and ENABLE_VDDIO (= %b) are complement of each \other. This is an illegal combination as ENABLE_VDDIO and ENABLE_H are the same input signals IN different power \domains %m", ENABLE_H, ENABLE_VDDIO, $stime);
end
else
if (msg_count_pad == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vdda = ( VDDA===1 && VDDIO_Q !==1 && ENABLE_VDDA_H===1 );
event event_error_vdda;
always @(error_vdda)
begin
if (!dis_err_msgs)
begin
if (error_vdda===1)
begin
msg_count_pad1 = msg_count_pad1 + 1;
->event_error_vdda;
if (msg_count_pad1 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : ENABLE_VDDA_H (= %b) cannot be 1 when VDDA (= %b) and VDDIO_Q (= %b) %m",ENABLE_VDDA_H, VDDA,VDDIO_Q,$stime);
end
else
if (msg_count_pad1 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vdda2 = ( VDDA===1 && VDDIO_Q ===1 && VSWITCH !==1 && ENABLE_H===1 && hld_h_n_buf ===1 && VCCD===1 && ANALOG_EN ===1 );
event event_error_vdda2;
always @(error_vdda2)
begin
if (!dis_err_msgs)
begin
if (error_vdda2===1)
begin
msg_count_pad2 = msg_count_pad2 + 1;
->event_error_vdda2;
if (msg_count_pad2 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : ANALOG_EN (= %b) cannot be 1 when VDDA (= %b) , VDDIO_Q (= %b) , VSWITCH(= %b), ENABLE_H (= %b),hld_h_n_buf (= %b) and VCCD (= %b) %m",ANALOG_EN,VDDA,VDDIO_Q,VSWITCH,ENABLE_H,hld_h_n_buf,VCCD,$stime);
end
else
if (msg_count_pad2 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vdda3 = ( VDDA===1 && VDDIO_Q ===1 && VSWITCH !==1 && ENABLE_H===1 && hld_h_n_buf ===1 && VCCD !==1 );
event event_error_vdda3;
always @(error_vdda3)
begin
if (!dis_err_msgs)
begin
if (error_vdda3===1)
begin
msg_count_pad3 = msg_count_pad3 + 1;
->event_error_vdda3;
if (msg_count_pad3 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : VCCD (= %b) cannot be any value other than 1 when VDDA (= %b) , VDDIO_Q (= %b) , VSWITCH(= %b), ENABLE_H (= %b) and hld_h_n_buf (= %b) %m",VCCD,VDDA,VDDIO_Q,VSWITCH,ENABLE_H,hld_h_n_buf,$stime);
end
else
if (msg_count_pad3 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vswitch1 = (VDDA !==1 && VDDIO_Q !==1 && VSWITCH ===1 && (ENABLE_VSWITCH_H===1)) ;
event event_error_vswitch1;
always @(error_vswitch1)
begin
if (!dis_err_msgs)
begin
if (error_vswitch1===1)
begin
msg_count_pad4 = msg_count_pad4 + 1;
->event_error_vswitch1;
if (msg_count_pad4 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : ENABLE_VSWITCH_H (= %b) cannot be 1 when VDDA (= %b) , VDDIO_Q (= %b) & VSWITCH(= %b) %m",ENABLE_VSWITCH_H,VDDA,VDDIO_Q,VSWITCH,$stime);
end
else
if (msg_count_pad4 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vswitch2 = (VDDA !==1 && VDDIO_Q !==1 && VSWITCH ===1 && VCCD===1 && ANALOG_EN===1);
event event_error_vswitch2;
always @(error_vswitch2)
begin
if (!dis_err_msgs)
begin
if (error_vswitch2===1)
begin
msg_count_pad5 = msg_count_pad5 + 1;
->event_error_vswitch2;
if (msg_count_pad5 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : ANALOG_EN (= %b) cannot be 1 when VDDA (= %b) , VDDIO_Q (= %b) , VSWITCH(= %b) & VCCD(= %b) %m",ANALOG_EN,VDDA,VDDIO_Q,VSWITCH,VCCD,$stime);
end
else
if (msg_count_pad5 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vswitch3 = (VDDA ===1 && VDDIO_Q !==1 && VSWITCH ===1 && ENABLE_VSWITCH_H===1);
event event_error_vswitch3;
always @(error_vswitch3)
begin
if (!dis_err_msgs)
begin
if (error_vswitch3===1)
begin
msg_count_pad6 = msg_count_pad6 + 1;
->event_error_vswitch3;
if (msg_count_pad6 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : ENABLE_VSWITCH_H(= %b) cannot be 1 when VDDA (= %b) , VDDIO_Q (= %b) & VSWITCH(= %b) %m",ENABLE_VSWITCH_H,VDDA,VDDIO_Q,VSWITCH,$stime);
end
else
if (msg_count_pad6 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vswitch4 = (VDDA !==1 && VDDIO_Q ===1 && VSWITCH ===1 && ENABLE_VSWITCH_H===1);
event event_error_vswitch4;
always @(error_vswitch4)
begin
if (!dis_err_msgs)
begin
if (error_vswitch4===1)
begin
msg_count_pad7 = msg_count_pad7 + 1;
->event_error_vswitch4;
if (msg_count_pad7 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : ENABLE_VSWITCH_H(= %b) cannot be 1 when VDDA (= %b) , VDDIO_Q (= %b) & VSWITCH(= %b) %m",ENABLE_VSWITCH_H,VDDA,VDDIO_Q,VSWITCH,$stime);
end
else
if (msg_count_pad7 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vswitch5 = (VDDA !==1 && VDDIO_Q ===1 && VSWITCH ===1 && ENABLE_H ===1 && hld_h_n_buf ===1 && VCCD ===1 && ANALOG_EN===1);
event event_error_vswitch5;
always @(error_vswitch5)
begin
if (!dis_err_msgs)
begin
if (error_vswitch5===1)
begin
msg_count_pad8 = msg_count_pad8 + 1;
->event_error_vswitch5;
if (msg_count_pad8 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : ANALOG_EN(= %b) cannot be 1 when VDDA (= %b) , VDDIO_Q (= %b) , VSWITCH(= %b),ENABLE_H (= %b),hld_h_n_buf (= %b) and VCCD (= %b) %m",ANALOG_EN,VDDA,VDDIO_Q,VSWITCH,ENABLE_H,hld_h_n_buf,VCCD,$stime);
end
else
if (msg_count_pad8 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vddio_q1 = (VDDA !==1 && VDDIO_Q ===1 && VSWITCH !==1 && ENABLE_H ===1 && hld_h_n_buf ===1 && VCCD!==1);
event event_error_vddio_q1;
always @(error_vddio_q1)
begin
if (!dis_err_msgs)
begin
if (error_vddio_q1===1)
begin
msg_count_pad9 = msg_count_pad9 + 1;
->event_error_vddio_q1;
if (msg_count_pad9 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : VCCD(= %b) cannot be any value other than 1 when VDDA (= %b) , VDDIO_Q (= %b) , VSWITCH(= %b),ENABLE_H (= %b) and hld_h_n_buf (= %b) %m",VCCD,VDDA,VDDIO_Q,VSWITCH,ENABLE_H,hld_h_n_buf,$stime);
end
else
if (msg_count_pad9 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vddio_q2 = (VDDA !==1 && VDDIO_Q ===1 && VSWITCH !==1 && ENABLE_H ===1 && hld_h_n_buf ===1 && VCCD ===1 && ANALOG_EN===1);
event event_error_vddio_q2;
always @(error_vddio_q2)
begin
if (!dis_err_msgs)
begin
if (error_vddio_q2===1)
begin
msg_count_pad10 = msg_count_pad10 + 1;
->event_error_vddio_q2;
if (msg_count_pad10 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : ANALOG_EN(= %b) cannot be 1 when VDDA (= %b) , VDDIO_Q (= %b) , VSWITCH(= %b),ENABLE_H (= %b) , hld_h_n_buf (= %b) && VCCD (= %b) %m",ANALOG_EN, VDDA,VDDIO_Q,VSWITCH,ENABLE_H,hld_h_n_buf,VCCD,$stime);
end
else
if (msg_count_pad10 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_supply_good = ( VDDA ===1 && VDDIO_Q ===1 && VSWITCH ===1 && ENABLE_H ===1 && hld_h_n_buf ===1 && VCCD ===1 && ANALOG_EN===1 && ENABLE_VSWITCH_H !==1 && ENABLE_VSWITCH_H !==0 );
event event_error_supply_good;
always @(error_supply_good)
begin
if (!dis_err_msgs)
begin
if (error_supply_good===1)
begin
msg_count_pad11 = msg_count_pad11 + 1;
->event_error_supply_good;
if (msg_count_pad11 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : ENABLE_VSWITCH_H(= %b) should be either 1 or 0 when VDDA (= %b) , VDDIO_Q (= %b) , VSWITCH(= %b), ENABLE_H (= %b), hld_h_n_buf (= %b) ,VCCD (= %b) and ANALOG_EN(= %b) %m",ENABLE_VSWITCH_H, VDDA,VDDIO_Q,VSWITCH,ENABLE_H,hld_h_n_buf,VCCD,ANALOG_EN,$stime);
end
else
if (msg_count_pad11 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vdda_vddioq_vswitch2 = ( VDDA ===1 && VDDIO_Q ===1 && VSWITCH ===1 && ENABLE_H ===1 && hld_h_n_buf ===1 && VCCD ===1 && ANALOG_EN===1 && ENABLE_VDDA_H !==1 && ENABLE_VDDA_H !==0 );
event event_error_vdda_vddioq_vswitch2;
always @(error_vdda_vddioq_vswitch2)
begin
if (!dis_err_msgs)
begin
if (error_vdda_vddioq_vswitch2===1)
begin
msg_count_pad12 = msg_count_pad12 + 1;
->event_error_vdda_vddioq_vswitch2;
if (msg_count_pad12 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpio_ovtv2 : ENABLE_VDDA_H(= %b) should be either 1 or 0 when VDDA (= %b) , VDDIO_Q (= %b) , VSWITCH(= %b), ENABLE_H (= %b), hld_h_n_buf (= %b) ,VCCD (= %b) and ANALOG_EN(= %b) %m",ENABLE_VDDA_H, VDDA,VDDIO_Q,VSWITCH,ENABLE_H,hld_h_n_buf,VCCD,ANALOG_EN,$stime);
end
else
if (msg_count_pad12 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpio_ovtv2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// This is the LVDS/DDR interface
`timescale 1ns/100ps
module cf_adc_if (
// adc interface (clk, data, over-range)
adc_clk_in,
adc_data_in,
adc_or_in,
// interface outputs
adc_clk,
adc_data,
adc_or,
// processor control signals
up_delay_sel,
up_delay_rwn,
up_delay_addr,
up_delay_wdata,
// delay control signals
delay_clk,
delay_ack,
delay_rdata,
delay_locked);
// This parameter controls the buffer type based on the target device.
parameter C_CF_BUFTYPE = 0;
parameter C_CF_7SERIES = 0;
parameter C_CF_VIRTEX6 = 1;
// adc interface (clk, data, over-range)
input adc_clk_in;
input [13:0] adc_data_in;
input adc_or_in;
// interface outputs
output adc_clk;
output [13:0] adc_data;
output adc_or;
// processor control signals
input up_delay_sel;
input up_delay_rwn;
input [ 3:0] up_delay_addr;
input [ 4:0] up_delay_wdata;
// delay control signals
input delay_clk;
output delay_ack;
output [ 4:0] delay_rdata;
output delay_locked;
reg [13:0] adc_data = 'd0;
reg adc_or_d = 'd0;
reg [ 4:0] adc_or_count = 'd0;
reg adc_or = 'd0;
reg [ 7:0] delay_rst_cnt = 'd0;
reg delay_sel_m1 = 'd0;
reg delay_sel_m2 = 'd0;
reg delay_sel_m3 = 'd0;
reg delay_sel = 'd0;
reg delay_rwn = 'd0;
reg [ 3:0] delay_addr = 'd0;
reg [ 4:0] delay_wdata = 'd0;
reg [14:0] delay_ld = 'd0;
reg delay_sel_d = 'd0;
reg delay_sel_2d = 'd0;
reg delay_sel_3d = 'd0;
reg delay_ack = 'd0;
reg [ 4:0] delay_rdata = 'd0;
reg delay_locked = 'd0;
wire delay_preset_s;
wire delay_rst_s;
wire [ 4:0] delay_rdata_s[14:0];
wire delay_locked_s;
wire [13:0] adc_data_ibuf_s;
wire [13:0] adc_data_idelay_s;
wire [13:0] adc_data_s;
wire adc_or_ibuf_s;
wire adc_or_idelay_s;
wire adc_or_s;
wire adc_clk_ibuf_s;
genvar l_inst;
always @(posedge adc_clk) begin
adc_data <= adc_data_s;
adc_or_d <= adc_or_s;
if (adc_or_d == 1'b1) begin
adc_or_count <= 5'h10;
end else if (adc_or_count[4] == 1'b1) begin
adc_or_count <= adc_or_count + 1'b1;
end
adc_or <= adc_or_count[4];
end
// The delay control interface, each delay element can be individually
// addressed, and a delay value can be directly loaded (no INC/DEC stuff)
always @(posedge delay_clk) begin
if ((delay_sel == 1'b1) && (delay_rwn == 1'b0) && (delay_addr == 4'hf)) begin
delay_rst_cnt <= 'd0;
end else if (delay_rst_cnt[7] == 1'b0) begin
delay_rst_cnt <= delay_rst_cnt + 1'b1;
end
delay_sel_m1 <= up_delay_sel;
delay_sel_m2 <= delay_sel_m1;
delay_sel_m3 <= delay_sel_m2;
delay_sel <= delay_sel_m2 & ~delay_sel_m3;
if ((delay_sel_m2 == 1'b1) && (delay_sel_m3 == 1'b0)) begin
delay_rwn <= up_delay_rwn;
delay_addr <= up_delay_addr;
delay_wdata <= up_delay_wdata[4:0];
end
if ((delay_sel == 1'b1) && (delay_rwn == 1'b0)) begin
case (delay_addr)
4'b1110: delay_ld <= 15'h4000;
4'b1101: delay_ld <= 15'h2000;
4'b1100: delay_ld <= 15'h1000;
4'b1011: delay_ld <= 15'h0800;
4'b1010: delay_ld <= 15'h0400;
4'b1001: delay_ld <= 15'h0200;
4'b1000: delay_ld <= 15'h0100;
4'b0111: delay_ld <= 15'h0080;
4'b0110: delay_ld <= 15'h0040;
4'b0101: delay_ld <= 15'h0020;
4'b0100: delay_ld <= 15'h0010;
4'b0011: delay_ld <= 15'h0008;
4'b0010: delay_ld <= 15'h0004;
4'b0001: delay_ld <= 15'h0002;
4'b0000: delay_ld <= 15'h0001;
default: delay_ld <= 15'h0000;
endcase
end else begin
delay_ld <= 15'h0000;
end
delay_sel_d <= delay_sel;
delay_sel_2d <= delay_sel_d;
delay_sel_3d <= delay_sel_2d;
if (delay_sel_3d == 1'b1) begin
delay_ack <= ~delay_ack;
end
case (delay_addr)
4'b1110: delay_rdata <= delay_rdata_s[14];
4'b1101: delay_rdata <= delay_rdata_s[13];
4'b1100: delay_rdata <= delay_rdata_s[12];
4'b1011: delay_rdata <= delay_rdata_s[11];
4'b1010: delay_rdata <= delay_rdata_s[10];
4'b1001: delay_rdata <= delay_rdata_s[ 9];
4'b1000: delay_rdata <= delay_rdata_s[ 8];
4'b0111: delay_rdata <= delay_rdata_s[ 7];
4'b0110: delay_rdata <= delay_rdata_s[ 6];
4'b0101: delay_rdata <= delay_rdata_s[ 5];
4'b0100: delay_rdata <= delay_rdata_s[ 4];
4'b0011: delay_rdata <= delay_rdata_s[ 3];
4'b0010: delay_rdata <= delay_rdata_s[ 2];
4'b0001: delay_rdata <= delay_rdata_s[ 1];
4'b0000: delay_rdata <= delay_rdata_s[ 0];
default: delay_rdata <= 5'd0;
endcase
delay_locked <= delay_locked_s;
end
// The delay elements need calibration from a delay controller and it needs a
// reset (it also asserts locked after the controller is up and running).
assign delay_preset_s = ~delay_rst_cnt[7];
FDPE #(.INIT(1'b1)) i_delayctrl_rst_reg (
.CE (1'b1),
.D (1'b0),
.PRE (delay_preset_s),
.C (delay_clk),
.Q (delay_rst_s));
// The data buffers -
generate
for (l_inst = 0; l_inst <= 13; l_inst = l_inst + 1) begin : g_adc_if
IBUF i_data_ibuf (
.I (adc_data_in[l_inst]),
.O (adc_data_ibuf_s[l_inst]));
(* IODELAY_GROUP = "adc_if_delay_group" *)
IDELAYE2 #(
.CINVCTRL_SEL ("FALSE"),
.DELAY_SRC ("IDATAIN"),
.HIGH_PERFORMANCE_MODE ("FALSE"),
.IDELAY_TYPE ("VAR_LOAD"),
.IDELAY_VALUE (0),
.REFCLK_FREQUENCY (200.0),
.PIPE_SEL ("FALSE"),
.SIGNAL_PATTERN ("DATA"))
i_data_idelay (
.CE (1'b0),
.INC (1'b0),
.DATAIN (1'b0),
.LDPIPEEN (1'b0),
.CINVCTRL (1'b0),
.REGRST (1'b0),
.C (delay_clk),
.IDATAIN (adc_data_ibuf_s[l_inst]),
.DATAOUT (adc_data_idelay_s[l_inst]),
.LD (delay_ld[l_inst]),
.CNTVALUEIN (delay_wdata),
.CNTVALUEOUT (delay_rdata_s[l_inst]));
(* IOB = "true" *)
FDRE i_data_reg (
.R (1'b0),
.CE (1'b1),
.C (adc_clk),
.D (adc_data_idelay_s[l_inst]),
.Q (adc_data_s[l_inst]));
end
endgenerate
// The or buffers -
IBUF i_or_ibuf (
.I (adc_or_in),
.O (adc_or_ibuf_s));
(* IODELAY_GROUP = "adc_if_delay_group" *)
IDELAYE2 #(
.CINVCTRL_SEL ("FALSE"),
.DELAY_SRC ("IDATAIN"),
.HIGH_PERFORMANCE_MODE ("FALSE"),
.IDELAY_TYPE ("VAR_LOAD"),
.IDELAY_VALUE (0),
.REFCLK_FREQUENCY (200.0),
.PIPE_SEL ("FALSE"),
.SIGNAL_PATTERN ("DATA"))
i_or_idelay (
.CE (1'b0),
.INC (1'b0),
.DATAIN (1'b0),
.LDPIPEEN (1'b0),
.CINVCTRL (1'b0),
.REGRST (1'b0),
.C (delay_clk),
.IDATAIN (adc_or_ibuf_s),
.DATAOUT (adc_or_idelay_s),
.LD (delay_ld[14]),
.CNTVALUEIN (delay_wdata),
.CNTVALUEOUT (delay_rdata_s[14]));
(* IOB = "true" *)
FDRE i_or_reg (
.R (1'b0),
.CE (1'b1),
.C (adc_clk),
.D (adc_or_idelay_s),
.Q (adc_or_s));
// The clock buffers -
IBUFG i_clk_ibuf (
.I (adc_clk_in),
.O (adc_clk_ibuf_s));
BUFG i_clk_gbuf (
.I (adc_clk_ibuf_s),
.O (adc_clk));
// The delay controller. Refer to Xilinx doc. for details.
// The GROUP directive controls which delay elements this is associated with.
(* IODELAY_GROUP = "adc_if_delay_group" *)
IDELAYCTRL i_delay_ctrl (
.RST (delay_rst_s),
.REFCLK (delay_clk),
.RDY (delay_locked_s));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/*
read sequence
clk ``\____/````\____/` ..... _/````\____/````\____/` ..... _/````\____/````\____/`
| | | | | | |
start XXXX```````````\__ ....... ____________________________________________________
| | | | | | |
rnw XXXXXX```XXXXXXXXX ....... XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
| | some | | | | |
ready XXXXXXX\__________ clocks __/`````````````````` ....... ```````````\__________
before | |
rdat ------------------ ready -< cell 0 | cell 1 | ....... |last cell>-----------
| | | | | | |
stop XXXXXXX\__________ ....... _____________________ ....... ___________/``````````
^all operations stopped until next start strobe
write sequence
clk ``\____/````\____/` ..... _/````\____/````\____/````\____/````\____/````\____/````\____/````\____/
| | some | | some | | | | | |
start XXXX```````````\__ ....... _____________ .... ______________ .... ________________________________
| | clocks | | clocks | | | | | |
rnw XXXXXX___XXXXXXXXX ....... XXXXXXXXXXXXX .... XXXXXXXXXXXXXX .... XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
| | before | | before | | | | | |
ready XXXXXXX\__________ ....... _/`````````\_ .... __/`````````\_ .... __/`````````\___________________
| | first | | next | | | | | |
wdat XXXXXXXXXXXXXXXXXXXXXXXXXXXX< cell 0 >X .... XX< cell 1 >X .... XX<last cell>XXXXXXXXXXXXXXXXXXX
| | ready | | ready | | | | | |
stop XXXXXXX\__________ ....... _____________ .... ______________ .... ____________/```````````````````
| | strobe | | strobe | | | | | |
clk ``\____/````\____/````\____/````\____/````\____/````\____/````\____/````\____/````\____/````\____/````\____/````\____/``
| | | | | | | | | | | |
ready __________________/`````````\___________________/`````````\___________________/`````````\___________________/`````````\_
| | | | | | | | | | | |
wdat cell 0 | cell 1 | cell 2 | cell 3 |
| | | | | | | | | | | |
sram_adr XXXXXXXXXXXXXXXXXXXXXXXXX| 0 | 1 | 2 |
| | | | | | | | | | | |
sram_dat XXXXXXXXXXXXXXXXXXXXXXXXX| cell 0 | cell 1 | cell 2 |
| | | | | | | | | | | |
sram_we_n```````````````````````````````````\_________/```````````````````\_________/```````````````````\_________/``````````
| BEG | PRE1 | PRE2 | | | | | | | | |
| | | CYC1 | CYC2 | CYC3 | CYC1 | CYC2 | CYC3 | CYC1 | CYC2 | CYC3 |
*/
module sram_control(
clk,
clk2, //latching of SRAM data out
start, // initializing input, address=0
stop, // when all addresses are done, nothing will happen after stop is set, need another start signal
rnw, // 1 - read, 0 - write sequence (latched when start=1)
ready, // strobe. when writing, one mean that data from wdat written to the memory (2^SRAM_ADDR_SIZE strobes total)
// when reading, one mean that data read from memory is on rdat output (2^SRAM_ADDR_SIZE strobes total)
wdat, // input, data to be written to memory
rdat, // output, data last read from memory
SRAM_DQ, // sram inout databus
SRAM_ADDR, // sram address bus
SRAM_UB_N, // sram control signals
SRAM_LB_N, //
SRAM_WE_N, //
SRAM_CE_N, //
SRAM_OE_N //
);
parameter SRAM_DATA_SIZE = 16;
parameter SRAM_ADDR_SIZE = 18;
input clk;
input clk2;
input start,rnw;
output stop;
reg stop;
output ready;
reg ready;
input [SRAM_DATA_SIZE-1:0] wdat;
output [SRAM_DATA_SIZE-1:0] rdat;
reg [SRAM_DATA_SIZE-1:0] rdat;
inout [SRAM_DATA_SIZE-1:0] SRAM_DQ;
reg [SRAM_DATA_SIZE-1:0] SRAM_DQ;
output [SRAM_ADDR_SIZE-1:0] SRAM_ADDR;
wire [SRAM_ADDR_SIZE-1:0] SRAM_ADDR;
output SRAM_UB_N,SRAM_LB_N,SRAM_WE_N,SRAM_CE_N,SRAM_OE_N;
reg SRAM_UB_N,SRAM_LB_N,SRAM_WE_N,SRAM_CE_N,SRAM_OE_N;
reg [SRAM_DATA_SIZE-1:0] wdat2;
reg dbin; //data bus direction control
reg [SRAM_ADDR_SIZE:0] sram_addr_ctr; // one bit bigger to have stop flag
wire [SRAM_ADDR_SIZE:0] sram_addr_nxt; // next sram address
reg [SRAM_DATA_SIZE-1:0] rdat2;
assign SRAM_ADDR = sram_addr_ctr[SRAM_ADDR_SIZE-1:0];
assign sram_addr_nxt = sram_addr_ctr + 1;
// data bus control
always @*
begin
if( dbin )
SRAM_DQ <= 'hZ;
else // !dbin
SRAM_DQ <= wdat2;
end
always @(posedge clk2) // clk2!!!! late latching
begin
rdat2 <= SRAM_DQ;
end
always @(posedge clk)
begin
rdat <= rdat2;
end
always @(posedge clk)
begin
if( ready ) wdat2 <= wdat;
end
reg [3:0] curr_state,next_state;
parameter START_STATE = 4'd00; // reset state
parameter INIT_STATE = 4'd01; // initialization state
parameter READ_BEG = 4'd02; // read branch: prepare signals
parameter READ_PRE = 4'd13;
parameter READ_CYCLE = 4'd03; // read in progress: increment address, set ready, out data, do so until all addresses done
parameter READ_POST = 4'd14;
parameter READ_END = 4'd04; // read end: deassert some signals, go to stop state
parameter WRITE_BEG = 4'd05; // prepare signals
parameter WRITE_PRE1 = 4'd06; // assert ready
parameter WRITE_PRE2 = 4'd07; // capture wdat, negate ready, NO INCREMENT address, next state is WRITE_CYC2
parameter WRITE_CYC1 = 4'd08; // capture wdat, negate ready, increment address
parameter WRITE_CYC2 = 4'd09; // assert SRAM_WE_N, go to WRITE_END if sram_addr_nxt is out of memory region
parameter WRITE_CYC3 = 4'd10; // negate SRAM_WE_N, assert ready (wdat will be captured in WRITE_CYC1)
parameter WRITE_END = 4'd11; // deassert sram control signals, go to STOP_STATE
parameter STOP_STATE = 4'd12; // full stop state
// FSM states
always @*
begin
case( curr_state )
////////////////////////////////////////////////////////////////////////
START_STATE:
next_state = INIT_STATE;
////////////////////////////////////////////////////////////////////////
INIT_STATE:
begin
if( rnw ) // read
next_state = READ_BEG;
else // !rnw - write
next_state = WRITE_BEG;
end
////////////////////////////////////////////////////////////////////////
READ_BEG:
next_state = READ_PRE;
READ_PRE:
next_state = READ_CYCLE;
READ_CYCLE:
if( !sram_addr_ctr[SRAM_ADDR_SIZE] )
next_state = READ_CYCLE;
else
next_state = READ_POST;
READ_POST:
next_state = READ_END;
READ_END:
next_state = STOP_STATE;
////////////////////////////////////////////////////////////////////////
WRITE_BEG:
next_state = WRITE_PRE1;
WRITE_PRE1:
next_state = WRITE_PRE2;
WRITE_PRE2:
next_state = WRITE_CYC2;
WRITE_CYC1:
next_state = WRITE_CYC2;
WRITE_CYC2:
if( !sram_addr_nxt[SRAM_ADDR_SIZE] )
next_state = WRITE_CYC3;
else
next_state = WRITE_END;
WRITE_CYC3:
next_state = WRITE_CYC1;
WRITE_END:
next_state = STOP_STATE;
////////////////////////////////////////////////////////////////////////
STOP_STATE:
next_state = STOP_STATE;
////////////////////////////////////////////////////////////////////////
default:
next_state = STOP_STATE;
endcase
end
// FSM flip-flops
always @(posedge clk)
begin
if( start )
curr_state <= START_STATE;
else
curr_state <= next_state;
end
// FSM outputs
always @(posedge clk)
begin
case( next_state )
////////////////////////////////////////////////////////////////////////
INIT_STATE:
begin
stop <= 1'b0;
SRAM_UB_N <= 1'b1;
SRAM_LB_N <= 1'b1;
SRAM_CE_N <= 1'b1;
SRAM_OE_N <= 1'b1;
SRAM_WE_N <= 1'b1;
dbin <= 1'b1;
sram_addr_ctr <= 0;
ready <= 1'b0;
end
////////////////////////////////////////////////////////////////////////
READ_BEG:
begin
SRAM_UB_N <= 1'b0;
SRAM_LB_N <= 1'b0;
SRAM_CE_N <= 1'b0;
SRAM_OE_N <= 1'b0;
end
READ_PRE:
begin
sram_addr_ctr <= sram_addr_nxt;
end
READ_CYCLE:
begin
ready <= 1'b1;
sram_addr_ctr <= sram_addr_nxt;
end
READ_POST:
begin
ready <= 1'b0; // in read sequence, ready and data are 2 cycles past the actual read.
end
READ_END:
begin
SRAM_UB_N <= 1'b1;
SRAM_LB_N <= 1'b1;
SRAM_CE_N <= 1'b1;
SRAM_OE_N <= 1'b1;
ready <= 1'b0;
end
////////////////////////////////////////////////////////////////////////
WRITE_BEG:
begin
SRAM_UB_N <= 1'b0;
SRAM_LB_N <= 1'b0;
SRAM_CE_N <= 1'b0;
dbin <= 1'b0;
end
WRITE_PRE1:
begin
ready <= 1'b1;
end
WRITE_PRE2:
begin
ready <= 1'b0;
end
WRITE_CYC1:
begin
ready <= 1'b0;
sram_addr_ctr <= sram_addr_nxt;
end
WRITE_CYC2:
begin
SRAM_WE_N <= 1'b0;
end
WRITE_CYC3:
begin
SRAM_WE_N <= 1'b1;
ready <= 1'b1;
end
WRITE_END:
begin
ready <= 1'b0;
SRAM_WE_N <= 1'b1;
SRAM_UB_N <= 1'b1;
SRAM_LB_N <= 1'b1;
SRAM_CE_N <= 1'b1;
end
////////////////////////////////////////////////////////////////////////
STOP_STATE:
begin
stop <= 1'b1;
end
endcase
end
endmodule
|
/*****************************************************************************
* *
* Module: Altera_UP_RS232_Out_Serializer *
* Description: *
* This module writes data to the RS232 UART Port. *
* *
*****************************************************************************/
module Altera_UP_RS232_Out_Serializer (
// Inputs
clk,
reset,
transmit_data,
transmit_data_en,
// Bidirectionals
// Outputs
fifo_write_space,
serial_data_out
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter BAUD_COUNTER_WIDTH = 9;
parameter BAUD_TICK_INCREMENT = 9'd1;
parameter BAUD_TICK_COUNT = 9'd433;
parameter HALF_BAUD_TICK_COUNT = 9'd216;
parameter TOTAL_DATA_WIDTH = 11;
parameter DATA_WIDTH = 9;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DATA_WIDTH:1] transmit_data;
input transmit_data_en;
// Bidirectionals
// Outputs
output reg [7:0] fifo_write_space;
output reg serial_data_out;
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
wire shift_data_reg_en;
wire all_bits_transmitted;
wire read_fifo_en;
wire fifo_is_empty;
wire fifo_is_full;
wire [6:0] fifo_used;
wire [DATA_WIDTH:1] data_from_fifo;
// Internal Registers
reg transmitting_data;
reg [DATA_WIDTH:0] data_out_shift_reg;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
fifo_write_space <= 8'h00;
else
fifo_write_space <= 8'h80 - {fifo_is_full, fifo_used};
end
always @(posedge clk)
begin
if (reset == 1'b1)
serial_data_out <= 1'b1;
else
serial_data_out <= data_out_shift_reg[0];
end
always @(posedge clk)
begin
if (reset == 1'b1)
transmitting_data <= 1'b0;
else if (all_bits_transmitted == 1'b1)
transmitting_data <= 1'b0;
else if (fifo_is_empty == 1'b0)
transmitting_data <= 1'b1;
end
always @(posedge clk)
begin
if (reset == 1'b1)
data_out_shift_reg <= {(DATA_WIDTH + 1){1'b1}};
else if (read_fifo_en)
data_out_shift_reg <= {data_from_fifo, 1'b0};
else if (shift_data_reg_en)
data_out_shift_reg <=
{1'b1, data_out_shift_reg[DATA_WIDTH:1]};
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
assign read_fifo_en =
~transmitting_data & ~fifo_is_empty & ~all_bits_transmitted;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
Altera_UP_RS232_Counters RS232_Out_Counters (
// Inputs
.clk (clk),
.reset (reset),
.reset_counters (~transmitting_data),
// Bidirectionals
// Outputs
.baud_clock_rising_edge (shift_data_reg_en),
.baud_clock_falling_edge (),
.all_bits_transmitted (all_bits_transmitted)
);
defparam
RS232_Out_Counters.BAUD_COUNTER_WIDTH = BAUD_COUNTER_WIDTH,
RS232_Out_Counters.BAUD_TICK_INCREMENT = BAUD_TICK_INCREMENT,
RS232_Out_Counters.BAUD_TICK_COUNT = BAUD_TICK_COUNT,
RS232_Out_Counters.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT,
RS232_Out_Counters.TOTAL_DATA_WIDTH = TOTAL_DATA_WIDTH;
Altera_UP_SYNC_FIFO RS232_Out_FIFO (
// Inputs
.clk (clk),
.reset (reset),
.write_en (transmit_data_en & ~fifo_is_full),
.write_data (transmit_data),
.read_en (read_fifo_en),
// Bidirectionals
// Outputs
.fifo_is_empty (fifo_is_empty),
.fifo_is_full (fifo_is_full),
.words_used (fifo_used),
.read_data (data_from_fifo)
);
defparam
RS232_Out_FIFO.DATA_WIDTH = DATA_WIDTH,
RS232_Out_FIFO.DATA_DEPTH = 128,
RS232_Out_FIFO.ADDR_WIDTH = 7;
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// vim:set shiftwidth=3 softtabstop=3 expandtab:
// $Id: udp_reg_master.v 1965 2007-07-18 01:24:21Z grg $
//
// Module: udp_reg_master.v
// Project: NetFPGA
// Description: User data path register master
//
// Note: Set TIMEOUT_RESULT to specify the return value on timeout.
// This can be used to identify broken rings.
//
// Result: ack_in -> data_in
// timeout -> TIMEOUT_RESULT
// loop complete && !ack_in -> deadbeef
//
///////////////////////////////////////////////////////////////////////////////
module udp_reg_master
#(
parameter TABLE_NUM = 1
)
(
input reg_req_in ,
input reg_rd_wr_L_in ,
input [31:0] reg_addr_in ,
input [31:0] reg_data_in ,
output reg [31:0] reg_rd_data ,
output reg reg_ack ,
input clk ,
input reset ,
output [31:0] data_output_port_lookup_o ,
/*output [31:0] data_output_port_lookup_1_o ,
output [31:0] data_output_port_lookup_2_o ,*/
output [31:0] data_meter_o ,
output [31:0] data_output_queues_o ,
output [31:0] data_config_o ,
output [31:0] addr_output_port_lookup_o ,
/*output [31:0] addr_output_port_lookup_1_o ,
output [31:0] addr_output_port_lookup_2_o ,*/
output [31:0] addr_meter_o ,
output [31:0] addr_output_queues_o ,
output [31:0] addr_config_o ,
output req_output_port_lookup_o ,
/*output req_output_port_lookup_1_o ,
output req_output_port_lookup_2_o ,*/
output req_meter_o ,
output req_output_queues_o ,
output req_config_o ,
output rw_output_port_lookup_o ,
/*output rw_output_port_lookup_1_o ,
output rw_output_port_lookup_2_o ,*/
output rw_meter_o ,
output rw_output_queues_o ,
output rw_config_o ,
input ack_output_port_lookup_i ,
/*input ack_output_port_lookup_1_i ,
input ack_output_port_lookup_2_i ,*/
input ack_meter_i ,
input ack_output_queues_i ,
input ack_config_i ,
input [31:0] data_output_port_lookup_i ,
/*input [31:0] data_output_port_lookup_1_i ,
input [31:0] data_output_port_lookup_2_i ,*/
input [31:0] data_meter_i ,
input [31:0] data_output_queues_i ,
input [31:0] data_config_i
);
assign data_output_port_lookup_o = reg_data_in ;
/*assign data_output_port_lookup_1_o = reg_data_in ;
assign data_output_port_lookup_2_o = reg_data_in ;*/
assign data_meter_o = reg_data_in ;
assign data_output_queues_o = reg_data_in ;
assign data_config_o = reg_data_in ;
assign addr_output_port_lookup_o = reg_addr_in ;
/*assign addr_output_port_lookup_1_o = reg_addr_in ;
assign addr_output_port_lookup_2_o = reg_addr_in ;*/
assign addr_meter_o = reg_addr_in;
assign addr_output_queues_o = reg_addr_in;
assign addr_config_o = reg_addr_in ;
assign req_output_port_lookup_o = (reg_addr_in[`MODULE_ID_POS+`MODULE_ID_WIDTH-1:`MODULE_ID_POS]==`OUTPUT_PORT_LOOKUP_TAG && reg_addr_in[`TABLE_ID_POS+`TABLE_ID_WIDTH-1:`TABLE_ID_POS]<=TABLE_NUM) ? reg_req_in : 0;
/*assign req_output_port_lookup_1_o = (reg_addr_in[`MODULE_ID_POS+`MODULE_ID_WIDTH-1:`MODULE_ID_POS]==`OUTPUT_PORT_LOOKUP_TAG && reg_addr_in[`TABLE_ID_POS+`TABLE_ID_WIDTH-1:`TABLE_ID_POS]==1) ? reg_req_in : 0;
assign req_output_port_lookup_2_o = (reg_addr_in[`MODULE_ID_POS+`MODULE_ID_WIDTH-1:`MODULE_ID_POS]==`OUTPUT_PORT_LOOKUP_TAG && reg_addr_in[`TABLE_ID_POS+`TABLE_ID_WIDTH-1:`TABLE_ID_POS]==2) ? reg_req_in : 0; */
assign req_meter_o = (reg_addr_in[`MODULE_ID_POS+`MODULE_ID_WIDTH-1:`MODULE_ID_POS]==`METER_TAG) ? reg_req_in : 0;
assign req_output_queues_o = (reg_addr_in[`MODULE_ID_POS+`MODULE_ID_WIDTH-1:`MODULE_ID_POS]==`QOS_TAG) ? reg_req_in : 0;
assign req_config_o = (reg_addr_in[`MODULE_ID_POS+`MODULE_ID_WIDTH-1:`MODULE_ID_POS]==`CONFIG) ? reg_req_in : 0;
assign rw_output_port_lookup_o = reg_rd_wr_L_in;
/*assign rw_output_port_lookup_1_o = reg_rd_wr_L_in;
assign rw_output_port_lookup_2_o = reg_rd_wr_L_in; */
assign rw_meter_o = reg_rd_wr_L_in;
assign rw_output_queues_o = reg_rd_wr_L_in;
assign rw_config_o = reg_rd_wr_L_in;
reg [2:0]ack_state;
always@(posedge clk)
if(reset)
ack_state<=0;
else case(ack_state)
0:if(req_output_port_lookup_o | req_meter_o | req_output_queues_o | req_config_o) ack_state<=1;//| req_output_port_lookup_1_o | req_output_port_lookup_2_o
else if(reg_req_in) ack_state<=3;
1:if(ack_output_port_lookup_i | ack_meter_i | ack_output_queues_i | ack_config_i) ack_state<=2;
2:ack_state<=0;
3:ack_state<=0;
default:ack_state<=0;
endcase
always@(posedge clk)
if(reset)
reg_ack <= 0;
else if(ack_state==2 | ack_state==3)
reg_ack<=1;
else reg_ack<=0;
always@(posedge clk)
if(reset)
reg_rd_data<=0;
else if(ack_state==1)
begin
if(ack_output_port_lookup_i) reg_rd_data <= data_output_port_lookup_i;
/*else if(ack_output_port_lookup_1_i) reg_rd_data <= data_output_port_lookup_1_i;
else if(ack_output_port_lookup_2_i) reg_rd_data <= data_output_port_lookup_2_i;*/
else if(ack_meter_i) reg_rd_data <= data_meter_i;
else if(ack_output_queues_i) reg_rd_data <= data_output_queues_i;
else if(ack_config_i) reg_rd_data <= data_config_i;
end
else if(ack_state==3) reg_rd_data<=32'hdeadbeef;
endmodule // unused_reg |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 20 13:52:57 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top affine_block_ieee754_fp_to_uint_0_0 -prefix
// affine_block_ieee754_fp_to_uint_0_0_ affine_block_ieee754_fp_to_uint_0_1_stub.v
// Design : affine_block_ieee754_fp_to_uint_0_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "ieee754_fp_to_uint,Vivado 2016.4" *)
module affine_block_ieee754_fp_to_uint_0_0(x, y)
/* synthesis syn_black_box black_box_pad_pin="x[31:0],y[9:0]" */;
input [31:0]x;
output [9:0]y;
endmodule
|
/*
* VGA top level file
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vga (
// Wishbone signals
input wb_clk_i, // 25 Mhz VDU clock
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input [16:1] wb_adr_i,
input wb_we_i,
input wb_tga_i,
input [ 1:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o,
// VGA pad signals
output [ 3:0] vga_red_o,
output [ 3:0] vga_green_o,
output [ 3:0] vga_blue_o,
output horiz_sync,
output vert_sync,
// CSR SRAM master interface
output [17:1] csrm_adr_o,
output [ 1:0] csrm_sel_o,
output csrm_we_o,
output [15:0] csrm_dat_o,
input [15:0] csrm_dat_i
);
// Registers and nets
//
// csr address
reg [17:1] csr_adr_i;
reg csr_stb_i;
// Config wires
wire [15:0] conf_wb_dat_o;
wire conf_wb_ack_o;
// Mem wires
wire [15:0] mem_wb_dat_o;
wire mem_wb_ack_o;
// LCD wires
wire [17:1] csr_adr_o;
wire [15:0] csr_dat_i;
wire csr_stb_o;
wire v_retrace;
wire vh_retrace;
wire w_vert_sync;
// VGA configuration registers
wire shift_reg1;
wire graphics_alpha;
wire memory_mapping1;
wire [ 1:0] write_mode;
wire [ 1:0] raster_op;
wire read_mode;
wire [ 7:0] bitmask;
wire [ 3:0] set_reset;
wire [ 3:0] enable_set_reset;
wire [ 3:0] map_mask;
wire x_dotclockdiv2;
wire chain_four;
wire [ 1:0] read_map_select;
wire [ 3:0] color_compare;
wire [ 3:0] color_dont_care;
// Wishbone master to SRAM
wire [17:1] wbm_adr_o;
wire [ 1:0] wbm_sel_o;
wire wbm_we_o;
wire [15:0] wbm_dat_o;
wire [15:0] wbm_dat_i;
wire wbm_stb_o;
wire wbm_ack_i;
wire stb;
// CRT wires
wire [ 5:0] cur_start;
wire [ 5:0] cur_end;
wire [15:0] start_addr;
wire [ 4:0] vcursor;
wire [ 6:0] hcursor;
wire [ 6:0] horiz_total;
wire [ 6:0] end_horiz;
wire [ 6:0] st_hor_retr;
wire [ 4:0] end_hor_retr;
wire [ 9:0] vert_total;
wire [ 9:0] end_vert;
wire [ 9:0] st_ver_retr;
wire [ 3:0] end_ver_retr;
// attribute_ctrl wires
wire [3:0] pal_addr;
wire pal_we;
wire [7:0] pal_read;
wire [7:0] pal_write;
// dac_regs wires
wire dac_we;
wire [1:0] dac_read_data_cycle;
wire [7:0] dac_read_data_register;
wire [3:0] dac_read_data;
wire [1:0] dac_write_data_cycle;
wire [7:0] dac_write_data_register;
wire [3:0] dac_write_data;
// Module instances
//
vga_config_iface config_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_dat_i (wb_dat_i),
.wb_dat_o (conf_wb_dat_o),
.wb_adr_i (wb_adr_i[4:1]),
.wb_we_i (wb_we_i),
.wb_sel_i (wb_sel_i),
.wb_stb_i (stb & wb_tga_i),
.wb_ack_o (conf_wb_ack_o),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.x_dotclockdiv2 (x_dotclockdiv2),
.chain_four (chain_four),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.cur_start (cur_start),
.cur_end (cur_end),
.start_addr (start_addr),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_lcd lcd (
.clk (wb_clk_i),
.rst (wb_rst_i),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.csr_adr_o (csr_adr_o),
.csr_dat_i (csr_dat_i),
.csr_stb_o (csr_stb_o),
.vga_red_o (vga_red_o),
.vga_green_o (vga_green_o),
.vga_blue_o (vga_blue_o),
.horiz_sync (horiz_sync),
.vert_sync (w_vert_sync),
.cur_start (cur_start),
.cur_end (cur_end),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.x_dotclockdiv2 (x_dotclockdiv2),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_cpu_mem_iface cpu_mem_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbs_adr_i (wb_adr_i),
.wbs_sel_i (wb_sel_i),
.wbs_we_i (wb_we_i),
.wbs_dat_i (wb_dat_i),
.wbs_dat_o (mem_wb_dat_o),
.wbs_stb_i (stb & !wb_tga_i),
.wbs_ack_o (mem_wb_ack_o),
.wbm_adr_o (wbm_adr_o),
.wbm_sel_o (wbm_sel_o),
.wbm_we_o (wbm_we_o),
.wbm_dat_o (wbm_dat_o),
.wbm_dat_i (wbm_dat_i),
.wbm_stb_o (wbm_stb_o),
.wbm_ack_i (wbm_ack_i),
.chain_four (chain_four),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care)
);
vga_mem_arbitrer mem_arbitrer (
.clk_i (wb_clk_i),
.rst_i (wb_rst_i),
.wb_adr_i (wbm_adr_o),
.wb_sel_i (wbm_sel_o),
.wb_we_i (wbm_we_o),
.wb_dat_i (wbm_dat_o),
.wb_dat_o (wbm_dat_i),
.wb_stb_i (wbm_stb_o),
.wb_ack_o (wbm_ack_i),
.csr_adr_i (csr_adr_i),
.csr_dat_o (csr_dat_i),
.csr_stb_i (csr_stb_i),
.csrm_adr_o (csrm_adr_o),
.csrm_sel_o (csrm_sel_o),
.csrm_we_o (csrm_we_o),
.csrm_dat_o (csrm_dat_o),
.csrm_dat_i (csrm_dat_i)
);
// Continous assignments
assign wb_dat_o = wb_tga_i ? conf_wb_dat_o : mem_wb_dat_o;
assign wb_ack_o = wb_tga_i ? conf_wb_ack_o : mem_wb_ack_o;
assign stb = wb_stb_i & wb_cyc_i;
assign vert_sync = ~graphics_alpha ^ w_vert_sync;
// Behaviour
// csr_adr_i
always @(posedge wb_clk_i)
csr_adr_i <= wb_rst_i ? 17'h0 : csr_adr_o + start_addr[15:1];
// csr_stb_i
always @(posedge wb_clk_i)
csr_stb_i <= wb_rst_i ? 1'b0 : csr_stb_o;
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_afi_slave.v
*
* Date : 2012-11
*
* Description : Model that acts as AFI port interface. It uses AXI3 Slave BFM
* from Cadence.
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_afi_slave (
S_RESETN,
S_ARREADY,
S_AWREADY,
S_BVALID,
S_RLAST,
S_RVALID,
S_WREADY,
S_BRESP,
S_RRESP,
S_RDATA,
S_BID,
S_RID,
S_ACLK,
S_ARVALID,
S_AWVALID,
S_BREADY,
S_RREADY,
S_WLAST,
S_WVALID,
S_ARBURST,
S_ARLOCK,
S_ARSIZE,
S_AWBURST,
S_AWLOCK,
S_AWSIZE,
S_ARPROT,
S_AWPROT,
S_ARADDR,
S_AWADDR,
S_WDATA,
S_ARCACHE,
S_ARLEN,
S_AWCACHE,
S_AWLEN,
S_WSTRB,
S_ARID,
S_AWID,
S_WID,
S_AWQOS,
S_ARQOS,
SW_CLK,
WR_DATA_ACK_OCM,
WR_DATA_ACK_DDR,
WR_ADDR,
WR_DATA,
WR_BYTES,
WR_DATA_VALID_OCM,
WR_DATA_VALID_DDR,
WR_QOS,
RD_REQ_DDR,
RD_REQ_OCM,
RD_ADDR,
RD_DATA_OCM,
RD_DATA_DDR,
RD_BYTES,
RD_QOS,
RD_DATA_VALID_OCM,
RD_DATA_VALID_DDR,
S_RDISSUECAP1_EN,
S_WRISSUECAP1_EN,
S_RCOUNT,
S_WCOUNT,
S_RACOUNT,
S_WACOUNT
);
parameter enable_this_port = 0;
parameter slave_name = "Slave";
parameter data_bus_width = 32;
parameter address_bus_width = 32;
parameter id_bus_width = 6;
parameter slave_base_address = 0;
parameter slave_high_address = 4;
parameter max_outstanding_transactions = 8;
parameter exclusive_access_supported = 0;
`include "processing_system7_bfm_v2_0_5_local_params.v"
/* Local parameters only for this module */
/* Internal counters that are used as Read/Write pointers to the fifo's that store all the transaction info on all channles.
This parameter is used to define the width of these pointers --> depending on Maximum outstanding transactions supported.
1-bit extra width than the no.of.bits needed to represent the outstanding transactions
Extra bit helps in generating the empty and full flags
*/
parameter int_cntr_width = clogb2(max_outstanding_transactions)+1;
/* RESP data */
parameter rsp_fifo_bits = axi_rsp_width+id_bus_width;
parameter rsp_lsb = 0;
parameter rsp_msb = axi_rsp_width-1;
parameter rsp_id_lsb = rsp_msb + 1;
parameter rsp_id_msb = rsp_id_lsb + id_bus_width-1;
input S_RESETN;
output S_ARREADY;
output S_AWREADY;
output S_BVALID;
output S_RLAST;
output S_RVALID;
output S_WREADY;
output [axi_rsp_width-1:0] S_BRESP;
output [axi_rsp_width-1:0] S_RRESP;
output [data_bus_width-1:0] S_RDATA;
output [id_bus_width-1:0] S_BID;
output [id_bus_width-1:0] S_RID;
input S_ACLK;
input S_ARVALID;
input S_AWVALID;
input S_BREADY;
input S_RREADY;
input S_WLAST;
input S_WVALID;
input [axi_brst_type_width-1:0] S_ARBURST;
input [axi_lock_width-1:0] S_ARLOCK;
input [axi_size_width-1:0] S_ARSIZE;
input [axi_brst_type_width-1:0] S_AWBURST;
input [axi_lock_width-1:0] S_AWLOCK;
input [axi_size_width-1:0] S_AWSIZE;
input [axi_prot_width-1:0] S_ARPROT;
input [axi_prot_width-1:0] S_AWPROT;
input [address_bus_width-1:0] S_ARADDR;
input [address_bus_width-1:0] S_AWADDR;
input [data_bus_width-1:0] S_WDATA;
input [axi_cache_width-1:0] S_ARCACHE;
input [axi_cache_width-1:0] S_ARLEN;
input [axi_qos_width-1:0] S_ARQOS;
input [axi_cache_width-1:0] S_AWCACHE;
input [axi_len_width-1:0] S_AWLEN;
input [axi_qos_width-1:0] S_AWQOS;
input [(data_bus_width/8)-1:0] S_WSTRB;
input [id_bus_width-1:0] S_ARID;
input [id_bus_width-1:0] S_AWID;
input [id_bus_width-1:0] S_WID;
input SW_CLK;
input WR_DATA_ACK_DDR, WR_DATA_ACK_OCM;
output WR_DATA_VALID_DDR, WR_DATA_VALID_OCM;
output [max_burst_bits-1:0] WR_DATA;
output [addr_width-1:0] WR_ADDR;
output [max_transfer_bytes_width:0] WR_BYTES;
output reg RD_REQ_OCM, RD_REQ_DDR;
output reg [addr_width-1:0] RD_ADDR;
input [max_burst_bits-1:0] RD_DATA_DDR,RD_DATA_OCM;
output reg[max_transfer_bytes_width:0] RD_BYTES;
input RD_DATA_VALID_OCM,RD_DATA_VALID_DDR;
output [axi_qos_width-1:0] WR_QOS;
output reg [axi_qos_width-1:0] RD_QOS;
input S_RDISSUECAP1_EN;
input S_WRISSUECAP1_EN;
output [7:0] S_RCOUNT;
output [7:0] S_WCOUNT;
output [2:0] S_RACOUNT;
output [5:0] S_WACOUNT;
wire net_ARVALID;
wire net_AWVALID;
wire net_WVALID;
real s_aclk_period;
cdn_axi3_slave_bfm #(slave_name,
data_bus_width,
address_bus_width,
id_bus_width,
slave_base_address,
(slave_high_address- slave_base_address),
max_outstanding_transactions,
0, ///MEMORY_MODEL_MODE,
exclusive_access_supported)
slave (.ACLK (S_ACLK),
.ARESETn (S_RESETN), /// confirm this
// Write Address Channel
.AWID (S_AWID),
.AWADDR (S_AWADDR),
.AWLEN (S_AWLEN),
.AWSIZE (S_AWSIZE),
.AWBURST (S_AWBURST),
.AWLOCK (S_AWLOCK),
.AWCACHE (S_AWCACHE),
.AWPROT (S_AWPROT),
.AWVALID (net_AWVALID),
.AWREADY (S_AWREADY),
// Write Data Channel Signals.
.WID (S_WID),
.WDATA (S_WDATA),
.WSTRB (S_WSTRB),
.WLAST (S_WLAST),
.WVALID (net_WVALID),
.WREADY (S_WREADY),
// Write Response Channel Signals.
.BID (S_BID),
.BRESP (S_BRESP),
.BVALID (S_BVALID),
.BREADY (S_BREADY),
// Read Address Channel Signals.
.ARID (S_ARID),
.ARADDR (S_ARADDR),
.ARLEN (S_ARLEN),
.ARSIZE (S_ARSIZE),
.ARBURST (S_ARBURST),
.ARLOCK (S_ARLOCK),
.ARCACHE (S_ARCACHE),
.ARPROT (S_ARPROT),
.ARVALID (net_ARVALID),
.ARREADY (S_ARREADY),
// Read Data Channel Signals.
.RID (S_RID),
.RDATA (S_RDATA),
.RRESP (S_RRESP),
.RLAST (S_RLAST),
.RVALID (S_RVALID),
.RREADY (S_RREADY));
wire wr_intr_fifo_full;
reg temp_wr_intr_fifo_full;
/* Interconnect WR_FIFO model instance */
processing_system7_bfm_v2_0_5_intr_wr_mem wr_intr_fifo(SW_CLK, S_RESETN, wr_intr_fifo_full, WR_DATA_ACK_OCM, WR_DATA_ACK_DDR, WR_ADDR, WR_DATA, WR_BYTES, WR_QOS, WR_DATA_VALID_OCM, WR_DATA_VALID_DDR);
/* Register the async 'full' signal to S_ACLK clock */
always@(posedge S_ACLK) temp_wr_intr_fifo_full = wr_intr_fifo_full;
/* Latency type and Debug/Error Control */
reg[1:0] latency_type = RANDOM_CASE;
reg DEBUG_INFO = 1;
reg STOP_ON_ERROR = 1'b1;
/* Internal nets/regs for calling slave BFM API's*/
reg [wr_afi_fifo_data_bits-1:0] wr_fifo [0:max_outstanding_transactions-1];
reg [int_cntr_width-1:0] wr_fifo_wr_ptr = 0, wr_fifo_rd_ptr = 0;
wire wr_fifo_empty;
/* Store the awvalid receive time --- necessary for calculating the bresp latency */
reg [7:0] aw_time_cnt = 0,bresp_time_cnt = 0;
real awvalid_receive_time[0:max_outstanding_transactions]; // store the time when a new awvalid is received
reg awvalid_flag[0:max_outstanding_transactions]; // store the time when a new awvalid is received
/* Address Write Channel handshake*/
reg[int_cntr_width-1:0] aw_cnt = 0;//
/* various FIFOs for storing the ADDR channel info */
reg [axi_size_width-1:0] awsize [0:max_outstanding_transactions-1];
reg [axi_prot_width-1:0] awprot [0:max_outstanding_transactions-1];
reg [axi_lock_width-1:0] awlock [0:max_outstanding_transactions-1];
reg [axi_cache_width-1:0] awcache [0:max_outstanding_transactions-1];
reg [axi_brst_type_width-1:0] awbrst [0:max_outstanding_transactions-1];
reg [axi_len_width-1:0] awlen [0:max_outstanding_transactions-1];
reg aw_flag [0:max_outstanding_transactions-1];
reg [addr_width-1:0] awaddr [0:max_outstanding_transactions-1];
reg [id_bus_width-1:0] awid [0:max_outstanding_transactions-1];
reg [axi_qos_width-1:0] awqos [0:max_outstanding_transactions-1];
wire aw_fifo_full; // indicates awvalid_fifo is full (max outstanding transactions reached)
/* internal fifos to store burst write data, ID & strobes*/
reg [(data_bus_width*axi_burst_len)-1:0] burst_data [0:max_outstanding_transactions-1];
reg [max_burst_bytes_width:0] burst_valid_bytes [0:max_outstanding_transactions-1]; /// total valid bytes received in a complete burst transfer
reg wlast_flag [0:max_outstanding_transactions-1]; // flag to indicate WLAST received
wire wd_fifo_full;
/* Write Data Channel and Write Response handshake signals*/
reg [int_cntr_width-1:0] wd_cnt = 0;
reg [(data_bus_width*axi_burst_len)-1:0] aligned_wr_data;
reg [addr_width-1:0] aligned_wr_addr;
reg [max_burst_bytes_width:0] valid_data_bytes;
reg [int_cntr_width-1:0] wr_bresp_cnt = 0;
reg [axi_rsp_width-1:0] bresp;
reg [rsp_fifo_bits-1:0] fifo_bresp [0:max_outstanding_transactions-1]; // store the ID and its corresponding response
reg enable_write_bresp;
reg [int_cntr_width-1:0] rd_bresp_cnt = 0;
integer wr_latency_count;
reg wr_delayed;
wire bresp_fifo_empty;
/* keep track of count values */
reg[7:0] wcount;
reg[5:0] wacount;
/* Qos*/
reg [axi_qos_width-1:0] ar_qos, aw_qos;
initial begin
if(DEBUG_INFO) begin
if(enable_this_port)
$display("[%0d] : %0s : %0s : Port is ENABLED.",$time, DISP_INFO, slave_name);
else
$display("[%0d] : %0s : %0s : Port is DISABLED.",$time, DISP_INFO, slave_name);
end
end
/*--------------------------------------------------------------------------------*/
/* Store the Clock cycle time period */
always@(S_RESETN)
begin
if(S_RESETN) begin
@(posedge S_ACLK);
s_aclk_period = $time;
@(posedge S_ACLK);
s_aclk_period = $time - s_aclk_period;
end
end
/*--------------------------------------------------------------------------------*/
initial slave.set_disable_reset_value_checks(1);
initial begin
repeat(2) @(posedge S_ACLK);
if(!enable_this_port) begin
slave.set_channel_level_info(0);
slave.set_function_level_info(0);
end
slave.RESPONSE_TIMEOUT = 0;
end
/*--------------------------------------------------------------------------------*/
/* Set Latency type to be used */
task set_latency_type;
input[1:0] lat;
begin
if(enable_this_port)
latency_type = lat;
else begin
//if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Port is disabled. 'Latency Profile' will not be set...",$time, DISP_WARN, slave_name);
end
end
endtask
/*--------------------------------------------------------------------------------*/
/* Set ARQoS to be used */
task set_arqos;
input[axi_qos_width-1:0] qos;
begin
if(enable_this_port)
ar_qos = qos;
else begin
if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Port is disabled. 'ARQOS' will not be set...",$time, DISP_WARN, slave_name);
end
end
endtask
/*--------------------------------------------------------------------------------*/
/* Set AWQoS to be used */
task set_awqos;
input[axi_qos_width-1:0] qos;
begin
if(enable_this_port)
aw_qos = qos;
else begin
if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Port is disabled. 'AWQOS' will not be set...",$time, DISP_WARN, slave_name);
end
end
endtask
/*--------------------------------------------------------------------------------*/
/* get the wr latency number */
function [31:0] get_wr_lat_number;
input dummy;
reg[1:0] temp;
begin
case(latency_type)
BEST_CASE : get_wr_lat_number = afi_wr_min;
AVG_CASE : get_wr_lat_number = afi_wr_avg;
WORST_CASE : get_wr_lat_number = afi_wr_max;
default : begin // RANDOM_CASE
temp = $random;
case(temp)
2'b00 : get_wr_lat_number = ($random()%10+ afi_wr_min);
2'b01 : get_wr_lat_number = ($random()%40+ afi_wr_avg);
default : get_wr_lat_number = ($random()%60+ afi_wr_max);
endcase
end
endcase
end
endfunction
/*--------------------------------------------------------------------------------*/
/* get the rd latency number */
function [31:0] get_rd_lat_number;
input dummy;
reg[1:0] temp;
begin
case(latency_type)
BEST_CASE : get_rd_lat_number = afi_rd_min;
AVG_CASE : get_rd_lat_number = afi_rd_avg;
WORST_CASE : get_rd_lat_number = afi_rd_max;
default : begin // RANDOM_CASE
temp = $random;
case(temp)
2'b00 : get_rd_lat_number = ($random()%10+ afi_rd_min);
2'b01 : get_rd_lat_number = ($random()%40+ afi_rd_avg);
default : get_rd_lat_number = ($random()%60+ afi_rd_max);
endcase
end
endcase
end
endfunction
/*--------------------------------------------------------------------------------*/
/* Check for any WRITE/READs when this port is disabled */
always@(S_AWVALID or S_WVALID or S_ARVALID)
begin
if((S_AWVALID | S_WVALID | S_ARVALID) && !enable_this_port) begin
$display("[%0d] : %0s : %0s : Port is disabled. AXI transaction is initiated on this port ...\nSimulation will halt ..",$time, DISP_ERR, slave_name);
$stop;
end
end
/*--------------------------------------------------------------------------------*/
assign net_ARVALID = enable_this_port ? S_ARVALID : 1'b0;
assign net_AWVALID = enable_this_port ? S_AWVALID : 1'b0;
assign net_WVALID = enable_this_port ? S_WVALID : 1'b0;
assign wr_fifo_empty = (wr_fifo_wr_ptr === wr_fifo_rd_ptr)?1'b1: 1'b0;
assign bresp_fifo_empty = (wr_bresp_cnt === rd_bresp_cnt)?1'b1:1'b0;
assign bresp_fifo_full = ((wr_bresp_cnt[int_cntr_width-1] !== rd_bresp_cnt[int_cntr_width-1]) && (wr_bresp_cnt[int_cntr_width-2:0] === rd_bresp_cnt[int_cntr_width-2:0]))?1'b1:1'b0;
assign S_WCOUNT = wcount;
assign S_WACOUNT = wacount;
// FIFO_STATUS (only if AFI port) 1- full
function automatic wrfifo_full ;
input [axi_len_width:0] fifo_space_exp;
integer fifo_space_left;
begin
fifo_space_left = afi_fifo_locations - wcount;
if(fifo_space_left < fifo_space_exp)
wrfifo_full = 1;
else
wrfifo_full = 0;
end
endfunction
/*--------------------------------------------------------------------------------*/
/* Store the awvalid receive time --- necessary for calculating the bresp latency */
always@(negedge S_RESETN or S_AWID or S_AWADDR or S_AWVALID )
begin
if(!S_RESETN)
aw_time_cnt = 0;
else begin
if(S_AWVALID) begin
awvalid_receive_time[aw_time_cnt] = $time;
awvalid_flag[aw_time_cnt] = 1'b1;
aw_time_cnt = aw_time_cnt + 1;
end
end // else
end /// always
/*--------------------------------------------------------------------------------*/
always@(posedge S_ACLK)
begin
if(net_AWVALID && S_AWREADY) begin
if(S_AWQOS === 0) awqos[aw_cnt[int_cntr_width-2:0]] = aw_qos;
else awqos[aw_cnt[int_cntr_width-2:0]] = S_AWQOS;
end
end
/* Address Write Channel handshake*/
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
aw_cnt = 0;
wacount = 0;
end else begin
if(S_AWVALID && !wrfifo_full(S_AWLEN+1)) begin
slave.RECEIVE_WRITE_ADDRESS(0,
id_invalid,
awaddr[aw_cnt[int_cntr_width-2:0]],
awlen[aw_cnt[int_cntr_width-2:0]],
awsize[aw_cnt[int_cntr_width-2:0]],
awbrst[aw_cnt[int_cntr_width-2:0]],
awlock[aw_cnt[int_cntr_width-2:0]],
awcache[aw_cnt[int_cntr_width-2:0]],
awprot[aw_cnt[int_cntr_width-2:0]],
awid[aw_cnt[int_cntr_width-2:0]]); /// sampled valid ID.
aw_flag[aw_cnt[int_cntr_width-2:0]] = 1'b1;
aw_cnt = aw_cnt + 1;
wacount = wacount + 1;
end // if (!aw_fifo_full)
end /// if else
end /// always
/*--------------------------------------------------------------------------------*/
/* Write Data Channel Handshake */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
wd_cnt = 0;
end else begin
if(aw_flag[wd_cnt[int_cntr_width-2:0]]) begin
if(S_WVALID && !wrfifo_full(awlen[wd_cnt[int_cntr_width-2:0]] + 1)) begin
slave.RECEIVE_WRITE_BURST_NO_CHECKS(S_WID, burst_data[wd_cnt[int_cntr_width-2:0]], burst_valid_bytes[wd_cnt[int_cntr_width-2:0]]);
wlast_flag[wd_cnt[int_cntr_width-2:0]] = 1'b1;
wd_cnt = wd_cnt + 1;
end
end else begin
if(!wrfifo_full(axi_burst_len+1) && S_WVALID) begin
slave.RECEIVE_WRITE_BURST_NO_CHECKS(S_WID, burst_data[wd_cnt[int_cntr_width-2:0]], burst_valid_bytes[wd_cnt[int_cntr_width-2:0]]);
wlast_flag[wd_cnt[int_cntr_width-2:0]] = 1'b1;
wd_cnt = wd_cnt + 1;
end
end /// if
end /// else
end /// always
/*--------------------------------------------------------------------------------*/
/* Align the wrap data for write transaction */
task automatic get_wrap_aligned_wr_data;
output [(data_bus_width*axi_burst_len)-1:0] aligned_data;
output [addr_width-1:0] start_addr; /// aligned start address
input [addr_width-1:0] addr;
input [(data_bus_width*axi_burst_len)-1:0] b_data;
input [max_burst_bytes_width:0] v_bytes;
reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data;
integer wrp_bytes;
integer i;
begin
start_addr = (addr/v_bytes) * v_bytes;
wrp_bytes = addr - start_addr;
wrp_data = b_data;
temp_data = 0;
wrp_data = wrp_data << ((data_bus_width*axi_burst_len) - (v_bytes*8));
while(wrp_bytes > 0) begin /// get the data that is wrapped
temp_data = temp_data << 8;
temp_data[7:0] = wrp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8];
wrp_data = wrp_data << 8;
wrp_bytes = wrp_bytes - 1;
end
wrp_bytes = addr - start_addr;
wrp_data = b_data << (wrp_bytes*8);
aligned_data = (temp_data | wrp_data);
end
endtask
/*--------------------------------------------------------------------------------*/
/* Calculate the Response for each read/write transaction */
function [axi_rsp_width-1:0] calculate_resp;
input [addr_width-1:0] awaddr;
input [axi_prot_width-1:0] awprot;
reg [axi_rsp_width-1:0] rsp;
begin
rsp = AXI_OK;
/* Address Decode */
if(decode_address(awaddr) === INVALID_MEM_TYPE) begin
rsp = AXI_SLV_ERR; //slave error
$display("[%0d] : %0s : %0s : AXI Access to Invalid location(0x%0h) ",$time, DISP_ERR, slave_name, awaddr);
end
else if(decode_address(awaddr) === REG_MEM) begin
rsp = AXI_SLV_ERR; //slave error
$display("[%0d] : %0s : %0s : AXI Access to Register Map(0x%0h) is not allowed through this port.",$time, DISP_ERR, slave_name, awaddr);
end
if(secure_access_enabled && awprot[1])
rsp = AXI_DEC_ERR; // decode error
calculate_resp = rsp;
end
endfunction
/*--------------------------------------------------------------------------------*/
reg[max_burst_bits-1:0] temp_wr_data;
/* Store the Write response for each write transaction */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
wr_fifo_wr_ptr = 0;
wcount = 0;
end else begin
enable_write_bresp = aw_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] && wlast_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]];
/* calculate bresp only when AWVALID && WLAST is received */
if(enable_write_bresp) begin
aw_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] = 0;
wlast_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] = 0;
bresp = calculate_resp(awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]], awprot[wr_fifo_wr_ptr[int_cntr_width-2:0]]);
/* Fill AFI_WR_data FIFO */
if(bresp === AXI_OK ) begin
if(awbrst[wr_fifo_wr_ptr[int_cntr_width-2:0]]=== AXI_WRAP) begin /// wrap type? then align the data
get_wrap_aligned_wr_data(aligned_wr_data, aligned_wr_addr, awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]], burst_data[wr_fifo_wr_ptr[int_cntr_width-2:0]],burst_valid_bytes[wr_fifo_wr_ptr[int_cntr_width-2:0]]); /// gives wrapped start address
end else begin
aligned_wr_data = burst_data[wr_fifo_wr_ptr[int_cntr_width-2:0]];
aligned_wr_addr = awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]] ;
end
valid_data_bytes = burst_valid_bytes[wr_fifo_wr_ptr[int_cntr_width-2:0]];
end else
valid_data_bytes = 0;
temp_wr_data = aligned_wr_data;
wr_fifo[wr_fifo_wr_ptr[int_cntr_width-2:0]] = {awqos[wr_fifo_wr_ptr[int_cntr_width-2:0]], awlen[wr_fifo_wr_ptr[int_cntr_width-2:0]], awid[wr_fifo_wr_ptr[int_cntr_width-2:0]], bresp, temp_wr_data, aligned_wr_addr, valid_data_bytes};
wcount = wcount + awlen[wr_fifo_wr_ptr[int_cntr_width-2:0]]+1;
wr_fifo_wr_ptr = wr_fifo_wr_ptr + 1;
end
end // else
end // always
/*--------------------------------------------------------------------------------*/
/* Send Write Response Channel handshake */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
rd_bresp_cnt = 0;
wr_latency_count = get_wr_lat_number(1);
wr_delayed = 0;
bresp_time_cnt = 0;
end else begin
wr_delayed = 1'b0;
if(awvalid_flag[bresp_time_cnt] && (($time - awvalid_receive_time[bresp_time_cnt])/s_aclk_period >= wr_latency_count))
wr_delayed = 1;
if(!bresp_fifo_empty && wr_delayed) begin
slave.SEND_WRITE_RESPONSE(fifo_bresp[rd_bresp_cnt[int_cntr_width-2:0]][rsp_id_msb : rsp_id_lsb], // ID
fifo_bresp[rd_bresp_cnt[int_cntr_width-2:0]][rsp_msb : rsp_lsb] // Response
);
wr_delayed = 0;
awvalid_flag[bresp_time_cnt] = 1'b0;
bresp_time_cnt = bresp_time_cnt+1;
rd_bresp_cnt = rd_bresp_cnt + 1;
wr_latency_count = get_wr_lat_number(1);
end
end // else
end//always
/*--------------------------------------------------------------------------------*/
/* Write Response Channel handshake */
reg wr_int_state;
/* Reading from the wr_fifo and sending to Interconnect fifo*/
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
wr_int_state = 1'b0;
wr_bresp_cnt = 0;
wr_fifo_rd_ptr = 0;
end else begin
case(wr_int_state)
1'b0 : begin
wr_int_state = 1'b0;
if(!temp_wr_intr_fifo_full && !bresp_fifo_full && !wr_fifo_empty) begin
wr_intr_fifo.write_mem({wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_qos_msb:wr_afi_qos_lsb], wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_data_msb:wr_afi_bytes_lsb]}); /// qos, data, address and valid_bytes
wr_int_state = 1'b1;
/* start filling the write response fifo at the same time */
fifo_bresp[wr_bresp_cnt[int_cntr_width-2:0]] = wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_id_msb:wr_afi_rsp_lsb]; // ID and Resp
wcount = wcount - (wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_ln_msb:wr_afi_ln_lsb] + 1); /// burst length
wacount = wacount - 1;
wr_fifo_rd_ptr = wr_fifo_rd_ptr + 1;
wr_bresp_cnt = wr_bresp_cnt+1;
end
end
1'b1 : begin
wr_int_state = 0;
end
endcase
end
end
/*--------------------------------------------------------------------------------*/
/*-------------------------------- WRITE HANDSHAKE END ----------------------------------------*/
/*-------------------------------- READ HANDSHAKE ---------------------------------------------*/
/* READ CHANNELS */
/* Store the arvalid receive time --- necessary for calculating latency in sending the rresp latency */
reg [7:0] ar_time_cnt = 0,rresp_time_cnt = 0;
real arvalid_receive_time[0:max_outstanding_transactions]; // store the time when a new arvalid is received
reg arvalid_flag[0:max_outstanding_transactions]; // store the time when a new arvalid is received
reg [int_cntr_width-1:0] ar_cnt = 0;// counter for arvalid info
/* various FIFOs for storing the ADDR channel info */
reg [axi_size_width-1:0] arsize [0:max_outstanding_transactions-1];
reg [axi_prot_width-1:0] arprot [0:max_outstanding_transactions-1];
reg [axi_brst_type_width-1:0] arbrst [0:max_outstanding_transactions-1];
reg [axi_len_width-1:0] arlen [0:max_outstanding_transactions-1];
reg [axi_cache_width-1:0] arcache [0:max_outstanding_transactions-1];
reg [axi_lock_width-1:0] arlock [0:max_outstanding_transactions-1];
reg ar_flag [0:max_outstanding_transactions-1];
reg [addr_width-1:0] araddr [0:max_outstanding_transactions-1];
reg [id_bus_width-1:0] arid [0:max_outstanding_transactions-1];
reg [axi_qos_width-1:0] arqos [0:max_outstanding_transactions-1];
wire ar_fifo_full; // indicates arvalid_fifo is full (max outstanding transactions reached)
reg [int_cntr_width-1:0] wr_rresp_cnt = 0;
reg [axi_rsp_width-1:0] rresp;
reg [rsp_fifo_bits-1:0] fifo_rresp [0:max_outstanding_transactions-1]; // store the ID and its corresponding response
reg enable_write_rresp;
/* Send Read Response & Data Channel handshake */
integer rd_latency_count;
reg rd_delayed;
reg [rd_afi_fifo_bits-1:0] read_fifo[0:max_outstanding_transactions-1]; /// Read Burst Data, addr, size, burst, len, RID, RRESP, valid_bytes
reg [int_cntr_width-1:0] rd_fifo_wr_ptr = 0, rd_fifo_rd_ptr = 0;
wire read_fifo_full;
reg [7:0] rcount;
reg [2:0] racount;
wire rd_intr_fifo_full, rd_intr_fifo_empty;
wire read_fifo_empty;
/* signals to communicate with interconnect RD_FIFO model */
reg rd_req, invalid_rd_req;
/* REad control Info
56:25 : Address (32)
24:22 : Size (3)
21:20 : BRST (2)
19:16 : LEN (4)
15:10 : RID (6)
9:8 : RRSP (2)
7:0 : byte cnt (8)
*/
reg [rd_info_bits-1:0] read_control_info;
reg [(data_bus_width*axi_burst_len)-1:0] aligned_rd_data;
reg temp_rd_intr_fifo_empty;
processing_system7_bfm_v2_0_5_intr_rd_mem rd_intr_fifo(SW_CLK, S_RESETN, rd_intr_fifo_full, rd_intr_fifo_empty, rd_req, invalid_rd_req, read_control_info , RD_DATA_OCM, RD_DATA_DDR, RD_DATA_VALID_OCM, RD_DATA_VALID_DDR);
assign read_fifo_empty = (rd_fifo_wr_ptr === rd_fifo_rd_ptr)?1'b1: 1'b0;
assign S_RCOUNT = rcount;
assign S_RACOUNT = racount;
/* Register the asynch signal empty coming from Interconnect READ FIFO */
always@(posedge S_ACLK) temp_rd_intr_fifo_empty = rd_intr_fifo_empty;
// FIFO_STATUS (only if AFI port) 1- full
function automatic rdfifo_full ;
input [axi_len_width:0] fifo_space_exp;
integer fifo_space_left;
begin
fifo_space_left = afi_fifo_locations - rcount;
if(fifo_space_left < fifo_space_exp)
rdfifo_full = 1;
else
rdfifo_full = 0;
end
endfunction
/* Store the arvalid receive time --- necessary for calculating the bresp latency */
always@(negedge S_RESETN or S_ARID or S_ARADDR or S_ARVALID )
begin
if(!S_RESETN)
ar_time_cnt = 0;
else begin
if(S_ARVALID) begin
arvalid_receive_time[ar_time_cnt] = $time;
arvalid_flag[ar_time_cnt] = 1'b1;
ar_time_cnt = ar_time_cnt + 1;
end
end // else
end /// always
/*--------------------------------------------------------------------------------*/
always@(posedge S_ACLK)
begin
if(net_ARVALID && S_ARREADY) begin
if(S_ARQOS === 0) arqos[aw_cnt[int_cntr_width-2:0]] = ar_qos;
else arqos[aw_cnt[int_cntr_width-2:0]] = S_ARQOS;
end
end
/* Address Read Channel handshake*/
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
ar_cnt = 0;
racount = 0;
end else begin
if(S_ARVALID && !rdfifo_full(S_ARLEN+1)) begin /// if AFI read fifo is not full
slave.RECEIVE_READ_ADDRESS(0,
id_invalid,
araddr[ar_cnt[int_cntr_width-2:0]],
arlen[ar_cnt[int_cntr_width-2:0]],
arsize[ar_cnt[int_cntr_width-2:0]],
arbrst[ar_cnt[int_cntr_width-2:0]],
arlock[ar_cnt[int_cntr_width-2:0]],
arcache[ar_cnt[int_cntr_width-2:0]],
arprot[ar_cnt[int_cntr_width-2:0]],
arid[ar_cnt[int_cntr_width-2:0]]); /// sampled valid ID.
ar_flag[ar_cnt[int_cntr_width-2:0]] = 1'b1;
ar_cnt = ar_cnt+1;
racount = racount + 1;
end /// if(!ar_fifo_full)
end /// if else
end /// always*/
/*--------------------------------------------------------------------------------*/
/* Align Wrap data for read transaction*/
task automatic get_wrap_aligned_rd_data;
output [(data_bus_width*axi_burst_len)-1:0] aligned_data;
input [addr_width-1:0] addr;
input [(data_bus_width*axi_burst_len)-1:0] b_data;
input [max_burst_bytes_width:0] v_bytes;
reg [addr_width-1:0] start_addr;
reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data;
integer wrp_bytes;
integer i;
begin
start_addr = (addr/v_bytes) * v_bytes;
wrp_bytes = addr - start_addr;
wrp_data = b_data;
temp_data = 0;
while(wrp_bytes > 0) begin /// get the data that is wrapped
temp_data = temp_data >> 8;
temp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8] = wrp_data[7:0];
wrp_data = wrp_data >> 8;
wrp_bytes = wrp_bytes - 1;
end
temp_data = temp_data >> ((data_bus_width*axi_burst_len) - (v_bytes*8));
wrp_bytes = addr - start_addr;
wrp_data = b_data >> (wrp_bytes*8);
aligned_data = (temp_data | wrp_data);
end
endtask
/*--------------------------------------------------------------------------------*/
parameter RD_DATA_REQ = 1'b0, WAIT_RD_VALID = 1'b1;
reg rd_fifo_state;
reg [addr_width-1:0] temp_read_address;
reg [max_burst_bytes_width:0] temp_rd_valid_bytes;
/* get the data from memory && also calculate the rresp*/
always@(negedge S_RESETN or posedge SW_CLK)
begin
if(!S_RESETN)begin
wr_rresp_cnt =0;
rd_fifo_state = RD_DATA_REQ;
temp_rd_valid_bytes = 0;
temp_read_address = 0;
RD_REQ_DDR = 1'b0;
RD_REQ_OCM = 1'b0;
rd_req = 0;
invalid_rd_req= 0;
RD_QOS = 0;
end else begin
case(rd_fifo_state)
RD_DATA_REQ : begin
rd_fifo_state = RD_DATA_REQ;
RD_REQ_DDR = 1'b0;
RD_REQ_OCM = 1'b0;
invalid_rd_req = 0;
if(ar_flag[wr_rresp_cnt[int_cntr_width-2:0]] && !rd_intr_fifo_full) begin /// check the rd_fifo_bytes, interconnect fifo full condition
ar_flag[wr_rresp_cnt[int_cntr_width-2:0]] = 0;
rresp = calculate_resp(araddr[wr_rresp_cnt[int_cntr_width-2:0]],arprot[wr_rresp_cnt[int_cntr_width-2:0]]);
temp_rd_valid_bytes = (arlen[wr_rresp_cnt[int_cntr_width-2:0]]+1)*(2**arsize[wr_rresp_cnt[int_cntr_width-2:0]]);//data_bus_width/8;
if(arbrst[wr_rresp_cnt[int_cntr_width-2:0]] === AXI_WRAP) /// wrap begin
temp_read_address = (araddr[wr_rresp_cnt[int_cntr_width-2:0]]/temp_rd_valid_bytes) * temp_rd_valid_bytes;
else
temp_read_address = araddr[wr_rresp_cnt[int_cntr_width-2:0]];
if(rresp === AXI_OK) begin
case(decode_address(temp_read_address))//decode_address(araddr[wr_rresp_cnt[int_cntr_width-2:0]]);
OCM_MEM : RD_REQ_OCM = 1;
DDR_MEM : RD_REQ_DDR = 1;
default : invalid_rd_req = 1;
endcase
end else
invalid_rd_req = 1;
RD_ADDR = temp_read_address; ///araddr[wr_rresp_cnt[int_cntr_width-2:0]];
RD_BYTES = temp_rd_valid_bytes;
RD_QOS = arqos[wr_rresp_cnt[int_cntr_width-2:0]];
rd_fifo_state = WAIT_RD_VALID;
rd_req = 1;
racount = racount - 1;
read_control_info = {araddr[wr_rresp_cnt[int_cntr_width-2:0]], arsize[wr_rresp_cnt[int_cntr_width-2:0]], arbrst[wr_rresp_cnt[int_cntr_width-2:0]], arlen[wr_rresp_cnt[int_cntr_width-2:0]], arid[wr_rresp_cnt[int_cntr_width-2:0]], rresp, temp_rd_valid_bytes };
wr_rresp_cnt = wr_rresp_cnt + 1;
end
end
WAIT_RD_VALID : begin
rd_fifo_state = WAIT_RD_VALID;
rd_req = 0;
if(RD_DATA_VALID_OCM | RD_DATA_VALID_DDR | invalid_rd_req) begin ///temp_dec == 2'b11) begin
RD_REQ_DDR = 1'b0;
RD_REQ_OCM = 1'b0;
invalid_rd_req = 0;
rd_fifo_state = RD_DATA_REQ;
end
end
endcase
end /// else
end /// always
/*--------------------------------------------------------------------------------*/
/* thread to fill in the AFI RD_FIFO */
reg[rd_afi_fifo_bits-1:0] temp_rd_data;//Read Burst Data, addr, size, burst, len, RID, RRESP, valid bytes
reg tmp_state;
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN)begin
rd_fifo_wr_ptr = 0;
rcount = 0;
tmp_state = 0;
end else begin
case(tmp_state)
0 : begin
tmp_state = 0;
if(!temp_rd_intr_fifo_empty) begin
rd_intr_fifo.read_mem(temp_rd_data);
tmp_state = 1;
end
end
1 : begin
tmp_state = 1;
if(!rdfifo_full(temp_rd_data[rd_afi_ln_msb:rd_afi_ln_lsb]+1)) begin
read_fifo[rd_fifo_wr_ptr[int_cntr_width-2:0]] = temp_rd_data;
rd_fifo_wr_ptr = rd_fifo_wr_ptr + 1;
rcount = rcount + temp_rd_data[rd_afi_ln_msb:rd_afi_ln_lsb]+1; /// Burst length
tmp_state = 0;
end
end
endcase
end
end
/*--------------------------------------------------------------------------------*/
reg[max_burst_bytes_width:0] rd_v_b;
reg[rd_afi_fifo_bits-1:0] tmp_fifo_rd; /// Data, addr, size, burst, len, RID, RRESP,valid_bytes
reg[(data_bus_width*axi_burst_len)-1:0] temp_read_data;
reg[(axi_rsp_width*axi_burst_len)-1:0] temp_read_rsp;
/* Read Data Channel handshake */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN)begin
rd_fifo_rd_ptr = 0;
rd_latency_count = get_rd_lat_number(1);
rd_delayed = 0;
rresp_time_cnt = 0;
rd_v_b = 0;
end else begin
if(arvalid_flag[rresp_time_cnt] && ((($time - arvalid_receive_time[rresp_time_cnt])/s_aclk_period) >= rd_latency_count)) begin
rd_delayed = 1;
end
if(!read_fifo_empty && rd_delayed)begin
rd_delayed = 0;
arvalid_flag[rresp_time_cnt] = 1'b0;
tmp_fifo_rd = read_fifo[rd_fifo_rd_ptr[int_cntr_width-2:0]];
rd_v_b = (tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb]+1)*(2**tmp_fifo_rd[rd_afi_siz_msb : rd_afi_siz_lsb]);
temp_read_data = tmp_fifo_rd[rd_afi_data_msb : rd_afi_data_lsb];
if(tmp_fifo_rd[rd_afi_brst_msb : rd_afi_brst_lsb] === AXI_WRAP) begin
get_wrap_aligned_rd_data(aligned_rd_data, tmp_fifo_rd[rd_afi_addr_msb : rd_afi_addr_lsb], tmp_fifo_rd[rd_afi_data_msb : rd_afi_data_lsb], rd_v_b);
temp_read_data = aligned_rd_data;
end
temp_read_rsp = 0;
repeat(axi_burst_len) begin
temp_read_rsp = temp_read_rsp >> axi_rsp_width;
temp_read_rsp[(axi_rsp_width*axi_burst_len)-1:(axi_rsp_width*axi_burst_len)-axi_rsp_width] = tmp_fifo_rd[rd_afi_rsp_msb : rd_afi_rsp_lsb];
end
slave.SEND_READ_BURST_RESP_CTRL(tmp_fifo_rd[rd_afi_id_msb : rd_afi_id_lsb],
tmp_fifo_rd[rd_afi_addr_msb : rd_afi_addr_lsb],
tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb],
tmp_fifo_rd[rd_afi_siz_msb : rd_afi_siz_lsb],
tmp_fifo_rd[rd_afi_brst_msb : rd_afi_brst_lsb],
temp_read_data,
temp_read_rsp);
rcount = rcount - (tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb]+ 1) ;
rresp_time_cnt = rresp_time_cnt+1;
rd_latency_count = get_rd_lat_number(1);
rd_fifo_rd_ptr = rd_fifo_rd_ptr+1;
end
end /// else
end /// always
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:02:02 05/08/2014
// Design Name:
// Module Name: data_path
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module data_path(
clk,
reset,
MIO_ready,
IorD,
IRWrite,
RegDst,
RegWrite,
MemtoReg,
data2Mem,
data2CPU,
ALUSrcA,
ALUSrcB,
PCSource,
PCWrite,
PCWriteCond,
Beq,
Signext,
ALU_operation,
PC_Current,
Inst_R,
data_out,
M_addr,
zero,
overflow,
WriteEPC,
WriteCause,
WriteCp0,
InTcause,
WriteIen,
Int_en,
intrrupt_en_o
);
input wire clk, reset;
input wire MIO_ready, IorD, RegWrite, IRWrite, PCWrite,
PCWriteCond, Beq, data2Mem, Signext, WriteEPC,
WriteCause, WriteCp0, WriteIen, Int_en;
input wire [ 1: 0] RegDst, ALUSrcA, ALUSrcB;
input wire [ 2: 0] PCSource, MemtoReg;
input wire [ 3: 0] ALU_operation;
input wire [ 4: 0] InTcause;
input wire [31: 0] data2CPU;
output wire [31: 0] intrrupt_en_o;
output reg [31: 0] PC_Current;
output reg [31: 0] Inst_R = 0;
output wire [31: 0] data_out;
output wire [31: 0] M_addr;
output wire zero, overflow;
reg [31: 0] ALU_Out = 32'h0, MDR = 32'h0, ALU_Out2 = 32'h0;
wire [31: 0] reg_outA, reg_outB, r6out; //regs
wire [31: 0] epc_out, c0_r_data;
wire modificative;
//ALU
wire [31: 0] Alu_B, res;
reg [31: 0] Alu_A;
wire [31: 0] rdata_A, rdata_B;
reg [31: 0] w_reg_data;
wire [15: 0] imm;
wire [31: 0] imm_ext;
wire [ 4: 0] shamt;
wire [ 4: 0] reg_Rs_addr_A,reg_Rt_addr_B,reg_rd_addr,reg_Wt_addr;
reg [31: 0] dataToCpu;
always @(posedge clk) dataToCpu <= data2CPU;
assign rst=reset;
// locked inst form memory
always @(posedge clk or posedge rst)begin
if(rst) begin
Inst_R <= 0;
end
else begin
if (IRWrite && MIO_ready)
Inst_R <= data2CPU;
else
Inst_R <= Inst_R;
if (MIO_ready)
MDR <= data2CPU;
ALU_Out <= res;
ALU_Out2 <= ALU_Out;
end
end
//+++++++++++++++++++++++++++++++++++++++++++ signed or unsigned extends
single_signext signext(Signext, imm, imm_ext);
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
alu D1(
.A (Alu_A),
.B (Alu_B),
.ALU_operation (ALU_operation),
.shamt (shamt),
.res (res),
.zero (zero),
.overflow(overflow)
);
Regs reg_files(
.clk (clk),
.rst (rst),
.reg_R_addr_A (reg_Rs_addr_A),
.reg_R_addr_B (reg_Rt_addr_B),
.reg_W_addr (reg_Wt_addr),
.wdata (w_reg_data),
.reg_we (RegWrite),
.rdata_A (rdata_A),
.rdata_B (rdata_B)
);
// Instructions as mfc0 $t1, $11
Coprocessor cp0(
.clk (clk),
.rst (reset),
.c0_rd_addr (reg_rd_addr), // mfc0 $rt, $rd, which is $rt
.c0_wr_addr (reg_rd_addr),
.c0_w_data (rdata_B), // mtc0 $rd, $rt, which is rdata_B
.pc_i (res),
.InTcause (InTcause), //
.c0_reg_we (WriteCp0),
.WriteEPC (WriteEPC),
.WriteCause (WriteCause),
.WriteInt (WriteIen),
.Int_en_i (Int_en),
.Int_en_o (intrrupt_en_o),
.c0_r_data (c0_r_data), // used for instructions mfc0
.epc_o (epc_out) // eret return epc
);
initial begin
PC_Current = 32'h0000_0000;
end
//path with MUX++++++++++++++++++++++++++++++++++++++++++++++++++++++
// reg path
assign reg_Rs_addr_A = Inst_R[25:21]; //REG Source 1 rs
assign reg_Rt_addr_B = Inst_R[20:16]; //REG Source 2 or Destination rt
assign reg_rd_addr = Inst_R[15:11]; //REG Destination rd
assign imm = Inst_R[15: 0]; //Immediate
assign shamt = Inst_R[10: 6];
// reg write data
always @(*) begin
case(MemtoReg)
3'b000: w_reg_data <= ALU_Out; // ALU OP
3'b001: w_reg_data <= MDR; // LW
3'b010: w_reg_data <= {imm,16'h0000}; // lui
3'b011: w_reg_data <= PC_Current; // jr
3'b100: w_reg_data <= c0_r_data; // mfc0
endcase
end
/*
mux4to1_32 mux_w_reg_data(
.a (ALU_Out), //ALU OP
.b (MDR), //LW
.c ({imm,16'h0000}), //lui
.d (PC_Current), // jr
.sel (MemtoReg),
.o (w_reg_data)
);
*/
// reg write port addr
mux4to1_5 mux_w_reg_addr(
.a (reg_Rt_addr_B), //reg addr=IR[21:16]
.b (reg_rd_addr), //reg addr=IR[15:11], LW or lui
.c (5'b11111), //reg addr=$Ra(31) jr
.d (5'b00000), // not use
.sel (RegDst),
.o (reg_Wt_addr)
);
//---------------ALU path
// Alu source A
always @(*) begin
case( ALUSrcA )
2'b00: Alu_A <= PC_Current; // PC
2'b01: Alu_A <= rdata_A; // reg out A
2'b10: Alu_A <= dataToCpu; // Sh
2'b11: Alu_A <= PC_Current - 4; // pc - 4 for syscall
endcase
end
/*
mux3to1_32 mux_Alu_A(
.a (rdata_A), // reg out A
.b (PC_Current), // PC
.c (dataToCpu), // Sh
.d (PC_Current - 4), // pc - 4 for syscall
.sel (ALUSrcA),
.o (Alu_A)
);
*/
mux4to1_32 mux_Alu_B(
.a (rdata_B), //reg out B
.b (32'h00000004), //4 for PC+4
.c (imm_ext), //imm
.d ({{14{imm[15]}},imm,2'b00}), // offset
.sel (ALUSrcB),
.o (Alu_B)
);
//pc Generator
//+++++++++++++++++++++++++++++++++++++++++++++++++
assign modificative = PCWrite || (PCWriteCond && (~(zero || Beq) | (zero && Beq)));
//(PCWriteCond&&zero)
always @(posedge clk or posedge reset) begin
if (reset == 1) // reset
PC_Current <= 32'h00000000;
else if (modificative == 1)begin
case ( PCSource )
3'b000: if (MIO_ready)
PC_Current <= res; // PC+4
3'b001: PC_Current <= ALU_Out; // branch
3'b010: PC_Current <= {PC_Current[31:28],Inst_R[25:0],2'b00}; // jump
3'b011: PC_Current <= res; // jr and jalr
3'b100: PC_Current <= 32'h0000_0004;
3'b101: PC_Current <= epc_out;
endcase
end
end
//---------------memory path
assign data_out = data2Mem? ALU_Out2: rdata_B; //data to store memory or IO
mux2to1_32 mux_M_addr (
.a (ALU_Out), //access memory
.b (PC_Current), //IF
.sel (IorD),
.o (M_addr)
);
endmodule |
//==================================================================================================
// Filename : tb_FPU_PIPELINED_FPADDSUB2_vector_testing.v
// Created On : 2016-09-25 17:59:05
// Last Modified : 2016-09-25 17:59:05
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email : [email protected]
//
// Description :
//
//
//==================================================================================================
//==================================================================================================
// Filename : tb_uut2_vector_testing.v
// Created On : 2016-09-25 12:25:16
// Last Modified : 2016-09-25 12:25:16
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email : [email protected]
//
// Description : Testbench simulating the behavior and stimuli of the FPADD/FPSUB Unit.
//
//
//==================================================================================================
//==================================================================================================
// Filename : tb_uut2_vector_testing.v
// Created On : 2016-09-24 01:24:56
// Last Modified : 2016-09-24 01:24:56
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email : [email protected]
//
// Description : Testbench simulating the behavior and stimuli of the FPADD/FPSUB Unit.
//
//
//==================================================================================================
`timescale 1ns/1ps
module tb_FPU_PIPELINED_FPADDSUB2_vector_testing (); /* this is automatically generated */
localparam PERIOD = 10;
// (*NOTE*) replace reset, clock
parameter W = 32;
parameter EW = 8;
parameter SW = 23;
parameter SWR=26;
parameter EWR = 5; //Single Precision */
// parameter W = 64;
// parameter EW = 11;
// parameter SW = 52;
// parameter SWR = 55;
// parameter EWR = 6;
//////////////////////////////////////////////////////////////////////////////////////////////////////////
//
// MODULE SIGNALS
//
//////////////////////////////////////////////////////////////////////////////////////////////////////////
reg clk;
reg rst;
reg beg_OP;
reg [W-1:0] Data_X;
reg [W-1:0] Data_Y;
reg add_subt;
wire busy;
wire overflow_flag;
wire underflow_flag;
wire zero_flag;
wire [W-1:0] final_result_ieee;
reg [SW-1:0] final_result_ieee_mantissa;
reg [EW-1:0] final_result_ieee_exponent;
reg final_result_ieee_sign;
wire ready;
//Temps for the testbench and verification
reg [SW-1:0] Data_X_mant;
reg [SW-1:0] Data_Y_mant;
reg [EW-1:0] Data_X_exp;
reg [EW-1:0] Data_Y_exp;
reg Data_X_sign;
reg Data_Y_sign;
//////////////////////////////////////////////////////////////////////////////////////////////////////////
//
// TASKS VARIABLES
//
//////////////////////////////////////////////////////////////////////////////////////////////////////////
reg [W-1:0] formatted_number_W;
reg overflow_flag_t, underflow_flag_t;
//reg [EWR-1:0] LZD_raw_val_EWR;
reg [W-1:0] Theoretical_result;
reg [SW-1:0] Theoretical_result_mantissa;
reg [EW-1:0] Theoretical_result_exponent;
reg Theoretical_result_sign;
//////////////////////////////////////////////////////////////////////////////////////////////////////////
//
// STIMULI SIGNALS
//
//////////////////////////////////////////////////////////////////////////////////////////////////////////
reg [W-1:0] Array_IN [0:((2**PERIOD)-1)];
reg [W-1:0] Array_IN_2 [0:((2**PERIOD)-1)];
reg [W-1:0] Array_IN_3 [0:((2**PERIOD)-1)];
integer contador;
integer FileSaveData;
integer logVectorReference;
integer Cont_CLK;
integer Recept;
//////////////////////////////////////////////////////////////////////////////////////////////////////////
//
// END OF DECLARATIONS
//
//////////////////////////////////////////////////////////////////////////////////////////////////////////
FPU_PIPELINED_FPADDSUB #(
.W(W),
.EW(EW),
.SW(SW),
.SWR(SWR),
.EWR(EWR)
) inst_uut (
.clk (clk),
.rst (rst),
.beg_OP (beg_OP),
.Data_X (Data_X),
.Data_Y (Data_Y),
.add_subt (add_subt),
.busy (busy),
.overflow_flag (overflow_flag),
.underflow_flag (underflow_flag),
.zero_flag (zero_flag),
.ready (ready),
.final_result_ieee (final_result_ieee)
);
always begin
#1;
final_result_ieee_mantissa = final_result_ieee[SW-1:0];
final_result_ieee_exponent = final_result_ieee[W-2:SW];
final_result_ieee_sign = final_result_ieee[W-1];
Data_X_mant = Data_X[SW-1:0];
Data_Y_mant = Data_Y[SW-1:0];
Data_X_exp = Data_X[W-2:SW];
Data_Y_exp = Data_Y[W-2:SW];
Data_X_sign = Data_X[W-1];
Data_Y_sign = Data_Y[W-1];
Theoretical_result_mantissa = Theoretical_result[SW-1:0];
Theoretical_result_exponent = Theoretical_result[W-2:SW];
Theoretical_result_sign = Theoretical_result[W-1];
end
// function [EWR-1:0] LZD_raw; // function definition starts here
// input [SWR-1:0] ADD_SUB_RAW;
// integer k;
// begin
// LZD_raw = 0;
// k=SWR-1;
// while(ADD_SUB_RAW[k] == 0) begin
// k = k-1;
// LZD_raw = LZD_raw + 1;
// $display("This is the bit analized %d\n", k);
// $display("This is the bit analized %d\n", ADD_SUB_RAW[k]);
// $display("Number of 0s %d\n", LZD_raw);
// end
// end
// endfunction
initial begin
FileSaveData = $fopen("ResultadoXilinxFLM.txt","w");
logVectorReference = $fopen("output_log.py","w");
rst = 1;
add_subt = 0;
beg_OP = 0;
Data_Y = 0;
Data_X = 0;
Data_X_mant = 0;
Data_Y_mant = 0;
Data_X_exp = 0;
Data_Y_exp = 0;
Data_X_sign = 0;
Data_Y_sign = 0;
//Theoretical_result = 32'hbe1abef8;
//Inicializa las variables del testbench
contador = 0;
Cont_CLK = 0;
#98 rst = 0;
//FPADD_FPSUB(0, Array_IN[3], Array_IN_2[3], formatted_number_W, overflow_flag_t, underflow_flag_t);
end
//**************************** Se lee el archivo txt y se almacena en un arrays***************************************************//
initial begin
$readmemh("Hexadecimal_A.txt", Array_IN);
$readmemh("Hexadecimal_B.txt", Array_IN_2);
$readmemh("Hexadecimal_R.txt", Array_IN_3);
end
//**************************** Transmision de datos de forma paralela ************************************************************//
always @(posedge clk) begin
if (contador == (2**PERIOD)) begin
$fclose(FileSaveData);
$fclose(logVectorReference);
$finish;
end else if(ready) begin
$fwrite(FileSaveData,"%h\n",final_result_ieee);
end
end
always @(negedge clk) begin
#(PERIOD/3);
if(~busy & ~rst) begin
beg_OP = 1;
end
end
always @(posedge clk) begin
#(PERIOD/3);
if(rst) begin
contador = 0;
end
else if(~busy & ~rst) begin
Data_X = Array_IN[contador];
Data_Y = Array_IN_2[contador];
Theoretical_result = Array_IN_3[contador];
contador = contador + 1;
@(posedge clk)
#(PERIOD/3);
Data_X = Array_IN[contador];
Data_Y = Array_IN_2[contador];
Theoretical_result = Array_IN_3[contador];
contador = contador + 1;
@(posedge clk)
#(PERIOD/3);
Data_X = Array_IN[contador];
Data_Y = Array_IN_2[contador];
Theoretical_result = Array_IN_3[contador];
contador = contador + 1;
repeat(3) @(posedge clk);
end
end
// clock
initial begin
clk = 0;
forever #(PERIOD/2) clk = ~clk;
end
//////////////////////////////////////////////////////////////////////////////////////////////////////////
//
// TASKS
//
//////////////////////////////////////////////////////////////////////////////////////////////////////////
task FPADD_FPSUB;
//inputs
input op;
input [W-1:0] Operand1_W;
input [W-1:0] Operand2_W;
//outputs
output [W-1:0] formatted_number_W;
output overflow_flag;
output underflow_flag;
//Temporaries
reg [SW-1:0] Mantissa1_SW;
reg [SW-1:0] Mantissa2_SW;
reg [EW-1:0] Exponent1_EW;
reg [EW-1:0] Exponent2_EW;
reg Sign1;
reg [SW-1:0] Mantissa_M_SW;
reg [EW-1:0] Exponent_M_EW;
reg Sign2;
reg [SW-1:0] Mantissa_m_SW;
reg [EW-1:0] Exponent_m_EW;
reg [SWR-1:0] Mantissa_M_SWR;
reg [SWR-1:0] Mantissa_m_SWR;
reg [SWR-1:0] Mantissa_m_SWR1;
reg [SWR-1:0] norm_Mantissa_SWR;
reg [EW-1:0] Exponent_diff_EW;
reg [SWR:0] raw_Mantissa_SWR1;
reg overflow_flag, underflow_flag;
reg carry_out_exp_oper;
reg gtXY;
reg eqXY;
reg real_sign;
reg real_op;
reg add_overflow;
reg overunder;
reg [SWR-1:0]raw_Mantissa_SWR;
reg [EWR-1:0]LZD_raw_val_EWR;
reg [EW-1:0] U_limit; //Max Normal value of the standar ieee 754
reg [EW-1:0] L_limit; //Min Normal value of the standar ieee 754
reg final_sign;
reg [EW-1:0] exp_mux_D1;
reg [SW-1:0] sgf_mux_D1;
reg [EW-EWR-1:0] LZD_ZFiller;
integer k;
begin
// $display ("%g CPU Write task with address : 0x%h Data : 0x%h",
// $time, address,data);
// $display ("%g -> Driving CE, WR, WR data and ADDRESS on to bus",
// $time);
Sign1 = Operand1_W[W-1];
Sign2 = Operand2_W[W-1];
Exponent1_EW = Operand1_W[EW-1+SW:SW];
Exponent2_EW = Operand2_W[EW-1+SW:SW];
Mantissa1_SW = Operand1_W[SW-1:0];
Mantissa2_SW = Operand2_W[SW-1:0];
//LZD_raw_val_EWR = LZD_raw({3'b000,Operand1_W});
if(EW == 8) begin
assign U_limit = 9'hfe;
assign L_limit = 9'h01;
end
else begin
assign U_limit = 12'b111111111110;
assign L_limit = 12'b000000000001;
end
if(W == 32) begin
assign exp_mux_D1 =8'hff;
assign sgf_mux_D1 =23'd0;
end
else begin
assign exp_mux_D1 =11'hfff;
assign sgf_mux_D1 =52'd0;
end
if (EW == 8) begin
LZD_ZFiller = 3'd0;
end else begin
LZD_ZFiller =5'd0;
end
//@ (posedge clk);
#10;
$fwrite(logVectorReference,"=============INIT STAGE: input signals==============\n");
$fwrite(logVectorReference,"---------First Operator------------\n");
$fwrite(logVectorReference,"FP Format = 0x%30h, Mantissa = 0x%21h, Exponent = 0x%6h, sign = %d\n", Operand1_W, Mantissa1_SW, Exponent1_EW, Sign1);
$fwrite(logVectorReference,"FP Format = %b, Mantissa = %b, Exponent = %b, sign = %b\n", Operand1_W, Mantissa1_SW, Exponent1_EW, Sign1);
$fwrite(logVectorReference,"--------Second Operator------------\n");
$fwrite(logVectorReference,"P Format = 0x%30h, Mantissa = 0x%21h, Exponent = 0x%6h, sign = %d\n", Operand2_W, Mantissa2_SW, Exponent2_EW, Sign2);
$fwrite(logVectorReference,"FP Format = %b, Mantissa = %b, Exponent = %b, sign = %b\n", Operand2_W, Mantissa2_SW, Exponent2_EW, Sign2);
gtXY = ({Exponent1_EW, Mantissa1_SW} > {Exponent2_EW, Mantissa2_SW}) ? 1'b1 : 1'b0;
eqXY = ({Exponent1_EW, Mantissa1_SW} == {Exponent2_EW, Mantissa2_SW}) ? 1'b1 : 1'b0;
real_op = op ^ Sign2 ^ Sign1;
real_sign = (gtXY | ((op | Sign2) & (~op | ~Sign2))) & ( Sign1 | ~(eqXY | gtXY));
if(gtXY == 1) begin
{Exponent_M_EW, Mantissa_M_SW} = {Exponent1_EW , Mantissa1_SW};
{Exponent_m_EW, Mantissa_m_SW} = {Exponent2_EW , Mantissa2_SW};
end
else begin
{Exponent_M_EW, Mantissa_M_SW} = {Exponent2_EW , Mantissa2_SW};
{Exponent_m_EW, Mantissa_m_SW} = {Exponent1_EW , Mantissa1_SW};
end
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"=============INIT STAGE: output signals==============\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"--------------------FLAGS------------------\n");
$fwrite(logVectorReference,"Sign = %d, real_op = %d\n", real_sign, real_op);
$fwrite(logVectorReference,"--------Big Number------------\n");
$fwrite(logVectorReference,"Mantissa_M_SW = 0x%21h, Exponent_M_EW = 0x%6h\n", Mantissa_M_SW, Exponent_M_EW);
$fwrite(logVectorReference,"Mantissa_M_SW = %b, Exponent_M_EW = %b\n", Mantissa_M_SW, Exponent_M_EW);
$fwrite(logVectorReference,"--------Small Number------------\n");
$fwrite(logVectorReference,"Mantissa_m_SW = 0x%21h, Exponent_m_EW = 0x%6h\n", Mantissa_m_SW, Exponent_m_EW);
$fwrite(logVectorReference,"Mantissa_m_SW = %b, Exponent_m_EW = %b\n", Mantissa_m_SW, Exponent_m_EW);
$fwrite(logVectorReference,"======================== ^ ===================\n");
//$fwrite(logVectorReference,"===============INIT STAGE: FROM THE UUT ============\n");
//$fwrite(logVectorReference,"--------------------FLAGS------------------\n");
//$fwrite(logVectorReference,"SIGN_FLAG_EXP = %d, OP_FLAG_INIT = %d\n", uut.SIGN_FLAG_INIT, uut.OP_FLAG_INIT);
// $fwrite(logVectorReference,"--------Big Number------------\n");
// $fwrite(logVectorReference,"Mantissa_M_SW = 0x%21h, Exponent_M_EW = 0x%6h\n", Mantissa_M_SW, Exponent_M_EW);
// $fwrite(logVectorReference,"Mantissa_M_SW = %b, Exponent_M_EW = %b\n", Mantissa_M_SW, Exponent_M_EW);
// $fwrite(logVectorReference,"--------Small Number------------\n");
// $fwrite(logVectorReference,"Mantissa_m_SW = 0x%21h, Exponent_m_EW = 0x%6h\n", Mantissa_m_SW, Exponent_m_EW);
// $fwrite(logVectorReference,"Mantissa_m_SW = %b, Exponent_m_EW = %b\n", Mantissa_m_SW, Exponent_m_EW);
// $fwrite(logVectorReference,"======================== ^ ===================\n");
// $fwrite(logVectorReference,"======================== ^ ===================\n");
// $fwrite(logVectorReference,"======================== ^ ===================\n");
// $fwrite(logVectorReference,"======================== ^ ===================\n");
@ (posedge clk);
Exponent_diff_EW = Exponent_M_EW - Exponent_m_EW;
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"=============EXP STAGE==============\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"--------------------FLAGS------------------\n");
$fwrite(logVectorReference,"Sign = %d, real_op = %d\n", real_sign, real_op);
$fwrite(logVectorReference,"--------Big Number------------\n");
$fwrite(logVectorReference,"Mantissa_M_SW = 0x%21h, Exponent_M_EW = 0x%6h\n", Mantissa_M_SW, Exponent_M_EW);
$fwrite(logVectorReference,"Mantissa_M_SW = %b, Exponent_M_EW = %b\n", Mantissa_M_SW, Exponent_M_EW);
$fwrite(logVectorReference,"--------Small Number------------\n");
$fwrite(logVectorReference,"Mantissa_m_SW = 0x%21h\n", Mantissa_m_SW);
$fwrite(logVectorReference,"Mantissa_m_SW = %b\n", Mantissa_m_SW);
$fwrite(logVectorReference,"--------OPERATION RESULT------------\n");
$fwrite(logVectorReference,"Exponent_diff_EW = Exp M - Exp m = 0x%6h\n", Exponent_diff_EW);
$fwrite(logVectorReference,"Exponent_diff_EW = Exp M - Exp m = %b\n", Exponent_diff_EW);
// $fwrite(logVectorReference,"===============EXP STAGE FROM UUT============\n");
// $fwrite(logVectorReference,"--------------------FLAGS------------------\n");
// $fwrite(logVectorReference,"SIGN_FLAG_EXP = %d, OP_FLAG_EXP = %d\n", uut.SIGN_FLAG_EXP, uut.OP_FLAG_EXP);
// $fwrite(logVectorReference,"--------Big Number------------\n");
// $fwrite(logVectorReference,"DMP_mant_EXP_SW = 0x%21h, Exponent_M_EW = 0x%6h\n", uut.DMP_mant_EXP_SW, uut.DMP_exp_EXP_EW);
// $fwrite(logVectorReference,"DMP_mant_EXP_SW = %b, Exponent_M_EW = %b\n", uut.DMP_mant_EXP_SW, uut.DMP_exp_EXP_EW);
// $fwrite(logVectorReference,"--------Small Number------------\n");
// $fwrite(logVectorReference,"Mantissa_m_SW = 0x%21h\n", uut.DmP_mant_EXP_SW);
// $fwrite(logVectorReference,"Mantissa_m_SW = %b\n", uut.DmP_mant_EXP_SW);
// $fwrite(logVectorReference,"--------OPERATION RESULT------------\n");
// $fwrite(logVectorReference,"Shift_amount_EXP_EW = Exp M - Exp m = 0x%6h\n", uut.Exponent_diff_EW);
// $fwrite(logVectorReference,"Shift_amount_EXP_EW = Exp M - Exp m = %b\n", uut.Exponent_diff_EW);
// $fwrite(logVectorReference,"===============EXP STAGE============\n");
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"=============EXP STAGE==============\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"======================== * ===================\n");
@ (posedge clk);
Mantissa_m_SWR = {1'b1,Mantissa_m_SW, 2'b0} >> Exponent_diff_EW;
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"========== ===SHT1 STAGE==============\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"--------------------FLAGS------------------\n");
$fwrite(logVectorReference,"--------Sign = %d, real_op = %d ----------------\n", real_sign, real_op);
$fwrite(logVectorReference,"--------Big Number------------------------------------\n");
$fwrite(logVectorReference,"--------------Mantissa_M_SW = 0x%21h, Exponent_M_EW = 0x%6h--------\n", Mantissa_M_SW, Exponent_M_EW);
$fwrite(logVectorReference,"--------------Mantissa_M_SW = %b, Exponent_M_EW = %b--------\n", Mantissa_M_SW, Exponent_M_EW);
$fwrite(logVectorReference,"--------------Small Number--------------------\n");
$fwrite(logVectorReference,"--------Mantissa_m_SW hex = 0x%21h--------\n", Mantissa_m_SW);
$fwrite(logVectorReference,"--------Mantissa_m_SW bin = %b----------\n", Mantissa_m_SW);
$fwrite(logVectorReference,"--------------------OPERATION RESULT--------------------\n");
$fwrite(logVectorReference,"--------Shifted mantissa result hex = 0x%24h-------\n", Mantissa_m_SWR);
$fwrite(logVectorReference,"--------Shifted mantissa result bin = %b-------\n", Mantissa_m_SWR);
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"========== ===SHT1 STAGE==============\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"======================== * ===================\n");
@ (posedge clk);
//Our shifter is segmented, hence, the extra clk cycle
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"===================SHT2 STAGE================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"--------------------FLAGS------------------\n");
$fwrite(logVectorReference,"Sign = %d, real_op = %d\n", real_sign, real_op);
$fwrite(logVectorReference,"--------Big Number------------\n");
$fwrite(logVectorReference,"Mantissa_M_SW = 0x%21h, Exponent_M_EW = 0x%6h\n", Mantissa_M_SW, Exponent_M_EW);
$fwrite(logVectorReference,"Mantissa_M_SW = %b, Exponent_M_EW = %b\n", Mantissa_M_SW, Exponent_M_EW);
$fwrite(logVectorReference,"--------OPERATION RESULT------------\n");
$fwrite(logVectorReference,"Shifted Mantissa_m_SWR = 0x%24h\n", Mantissa_m_SWR);
$fwrite(logVectorReference,"Shifted Mantissa_m_SWR = %b\n", Mantissa_m_SWR);
$fwrite(logVectorReference,"===================SHT2 STAGE================\n");
// $fwrite(logVectorReference,"======================== ^ ===================\n");
// $fwrite(logVectorReference,"===================SHT2 STAGE FROM THE UUT================\n");
// $fwrite(logVectorReference,"--------------------FLAGS------------------\n");
// $fwrite(logVectorReference,"Sign = %d, real_op = %d\n", uut.SIGN_FLAG_SHT2, uut.OP_FLAG_SHT2);
// $fwrite(logVectorReference,"--------OPERATION RESULT------------\n");
// $fwrite(logVectorReference,"sftr_idat_SHT2_SWR = 0x%24h\n", uut.sftr_idat_SHT2_SWR);
// $fwrite(logVectorReference,"sftr_odat_SHT2_SWR = %b\n", uut.sftr_odat_SHT2_SWR);
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"===================SHT2 STAGE================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"======================== * ===================\n");
@ (posedge clk);
Mantissa_M_SWR = {1'b1,Mantissa_M_SW, 2'b0};
if (real_op == 1) begin
raw_Mantissa_SWR1 = Mantissa_M_SWR - Mantissa_m_SWR;
$display("Se restan las mantisas\n");
end
else begin
raw_Mantissa_SWR1 = Mantissa_M_SWR + Mantissa_m_SWR;
$display("Se suman las mantisas\n");
end
raw_Mantissa_SWR = raw_Mantissa_SWR1[SWR-1:0];
add_overflow = raw_Mantissa_SWR1[SWR-2];
add_overflow = add_overflow&(~real_op);
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"===================SGF STAGE================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"--------------------FLAGS------------------\n");
$fwrite(logVectorReference,"add_overflw = %d, Sign = %d\n", add_overflow, real_sign);
$fwrite(logVectorReference,"--------Big Number------------\n");
$fwrite(logVectorReference,"Mantissa_M_SW = 0x%24h, Exponent_M_EW = 0x%6h\n", Mantissa_M_SW, Exponent_M_EW);
$fwrite(logVectorReference,"Mantissa_M_SW = %b, Exponent_M_EW = %b\n", Mantissa_M_SW, Exponent_M_EW);
$fwrite(logVectorReference,"Mantissa_M_SW = %26d, Exponent_M_EW = %8d\n", Mantissa_M_SW, Exponent_M_EW);
$fwrite(logVectorReference,"Mantissa_M_SWR = 0x%24h, Exponent_M_EW = 0x%6h\n", Mantissa_M_SWR, Exponent_M_EW);
$fwrite(logVectorReference,"Mantissa_M_SWR = %b, Exponent_M_EW = %b\n", Mantissa_M_SWR, Exponent_M_EW);
$fwrite(logVectorReference,"Mantissa_M_SWR = %26d, Exponent_M_EW = %8d\n", Mantissa_M_SWR, Exponent_M_EW);
$fwrite(logVectorReference,"--------Small Number------------\n");
$fwrite(logVectorReference,"Mantissa hex = 0x%24h\n",Mantissa_m_SWR);
$fwrite(logVectorReference,"Mantissa bin = %b\n",Mantissa_m_SWR);
$fwrite(logVectorReference,"Mantissa bin = %26d\n",Mantissa_m_SWR);
$fwrite(logVectorReference,"--------OPERATION RESULT------------\n");
$fwrite(logVectorReference,"Mantissa operation result = 0x%24h\n", raw_Mantissa_SWR);
$fwrite(logVectorReference,"Mantissa operation result = %b\n", raw_Mantissa_SWR);
$fwrite(logVectorReference,"Mantissa operation result = %26d\n", raw_Mantissa_SWR);
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"===================SGF STAGE================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"======================== * ===================\n");
@ (posedge clk);
LZD_raw_val_EWR = 0;
k=SWR-1;
$display("Mantissa operation result = 0x%h, Mantissa result bin = %b\n", raw_Mantissa_SWR, raw_Mantissa_SWR);
$display("dentro del loop %d, \n", raw_Mantissa_SWR[k]);
while(~raw_Mantissa_SWR[k]) begin
k = k-1;
LZD_raw_val_EWR = LZD_raw_val_EWR + 1;
$display("dentro del loop\n");
end
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"=================== NRM STAGE================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"--------------------FLAGS------------------\n");
$fwrite(logVectorReference,"add_overflw = %d, Sign = %d\n", add_overflow, real_sign);
$fwrite(logVectorReference,"--------Big Number------------\n");
$fwrite(logVectorReference,"Mantisa hex SW = 0x%21h \n", Mantissa_M_SW);
$fwrite(logVectorReference,"Mantisa hex SW = %b\n", Mantissa_M_SW);
$fwrite(logVectorReference,"Mantisa hex SWR = 0x%24h\n", Mantissa_M_SWR);
$fwrite(logVectorReference,"Mantisa hex SWR = %b\n", Mantissa_M_SWR);
$fwrite(logVectorReference,"Exponent = 0x%h\n", Exponent_M_EW);
$fwrite(logVectorReference,"--------OPERATION RESULT------------\n");
$fwrite(logVectorReference,"Mantissa operation result = 0x%24h\n", raw_Mantissa_SWR);
$fwrite(logVectorReference,"Mantissa operation result = 0x%h\n", raw_Mantissa_SWR);
$fwrite(logVectorReference,"Mantissa operation result = %26d\n", raw_Mantissa_SWR);
$fwrite(logVectorReference,"LZD result hex = 0x%h, LZD result hex = %b\n", LZD_raw_val_EWR, LZD_raw_val_EWR);
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"=================== NRM STAGE================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"======================== * ===================\n");
@ (posedge clk);
if (add_overflow) begin
//Signed shift
norm_Mantissa_SWR = raw_Mantissa_SWR >>> 1;
end
else begin
norm_Mantissa_SWR = raw_Mantissa_SWR << LZD_raw_val_EWR;
end
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"=================== NRM2 STAGE================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"--------------------FLAGS------------------\n");
$fwrite(logVectorReference,"add_overflw = %d, sign = %d\n", add_overflow, real_sign);
$fwrite(logVectorReference,"--------Big Number------------\n");
$fwrite(logVectorReference,"Exponent = 0x%6h\n", Exponent_M_EW);
$fwrite(logVectorReference,"Exponent = %b\n", Exponent_M_EW);
$fwrite(logVectorReference,"Exponent = %8d\n", Exponent_M_EW);
$fwrite(logVectorReference,"--------OPERATION RESULT------------\n");
$fwrite(logVectorReference,"Normalized mantissa (shifted) = 0x%24h\n", norm_Mantissa_SWR);
$fwrite(logVectorReference,"Normalized mantissa (shifted) = %b\n", norm_Mantissa_SWR);
$fwrite(logVectorReference,"Normalized mantissa (shifted) = %26d\n", norm_Mantissa_SWR);
$fwrite(logVectorReference,"LZD result hex = 0x%h, LZD result bin = %b\n", LZD_raw_val_EWR, LZD_raw_val_EWR);
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"=================== NRM2 STAGE================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"======================== * ===================\n");
@ (posedge clk);
//We do a second shift over here
//We do the xponent compensation
if (add_overflow) begin
{carry_out_exp_oper,Exponent_M_EW} = Exponent_M_EW - 1;
end
else begin
{carry_out_exp_oper,Exponent_M_EW} = Exponent_M_EW + {LZD_ZFiller,LZD_raw_val_EWR};
end
overflow_flag =({carry_out_exp_oper,Exponent_M_EW} > U_limit) ? 1'b1 : 1'b0;
underflow_flag =({carry_out_exp_oper,Exponent_M_EW} < L_limit) ? 1'b1 : 1'b0;
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"=================== NRM2 STAGE================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"--------------------FLAGS------------------\n");
$fwrite(logVectorReference,"overflow flag = %d, underflow flag = %d, sign flag = %d\n", overflow_flag, underflow_flag, real_sign);
$fwrite(logVectorReference,"--------OPERATION RESULT------------\n");
$fwrite(logVectorReference,"Compensated Exponent = 0x%6h, Normalized mantissa (shifted) = 0x%24h\n", Exponent_M_EW, norm_Mantissa_SWR);
$fwrite(logVectorReference,"Compensated Exponent = %b, Normalized mantissa (shifted) = %b\n", Exponent_M_EW, norm_Mantissa_SWR);
$fwrite(logVectorReference,"Compensated Exponent = %8d, Normalized mantissa (shifted) = %26d\n", Exponent_M_EW, norm_Mantissa_SWR);
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"=================== NRM2 STAGE================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"======================== * ===================\n");
@ (posedge clk);
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"=================== FRMT STAGE================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"La mantisa final sera: 0x%21h\n", norm_Mantissa_SWR[SWR-2:2]);
$fwrite(logVectorReference,"La mantisa final sera: %b\n", norm_Mantissa_SWR[SWR-2:2]);
$fwrite(logVectorReference,"La mantisa final sera: %23d\n", norm_Mantissa_SWR[SWR-2:2]);
$fwrite(logVectorReference,"El exponente final sera: 0x%6h\n", Exponent_M_EW);
$fwrite(logVectorReference,"El exponente final sera: %b\n", Exponent_M_EW);
$fwrite(logVectorReference,"El exponente final sera: %8d\n", Exponent_M_EW);
$fwrite(logVectorReference,"======================== * ===================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"=================== FRMT STAGE================\n");
$fwrite(logVectorReference,"=== \n");
$fwrite(logVectorReference,"======================== * ===================\n");
overunder = overflow_flag | underflow_flag;
case ({overflow_flag,underflow_flag})
2'b00: final_sign=real_sign;
2'b01: final_sign=1'b1;
2'b10: final_sign=1'b0;
default: final_sign=0;
endcase
if (overunder == 0) begin
formatted_number_W = {final_sign, Exponent_M_EW, norm_Mantissa_SWR[SWR-2:2]};
end else begin
formatted_number_W = {final_sign,exp_mux_D1,sgf_mux_D1};
end
$fwrite(logVectorReference,"=================== FRMT STAGE ================\n");
$fwrite(logVectorReference,"--------------------FLAGS------------------\n");
$fwrite(logVectorReference,"overflow flag = %d, underflow flag = %d\n", overflow_flag, underflow_flag);
$fwrite(logVectorReference,"--------OPERATION RESULT------------\n");
$fwrite(logVectorReference,"El resultado final sera: %32h\n", formatted_number_W);
$fwrite(logVectorReference,"El resultado final sera: %b\n", formatted_number_W);
$fwrite(logVectorReference,"El resultado final sera: %32d\n", formatted_number_W);
$fwrite(logVectorReference,"=================== FRMT STAGE ================\n");
end
endtask
endmodule
|
// Version: release . Copyright (C) 2011 XILINX, Inc.
/*-----------------------------------------------------------------------
-- AESL_FPSim_pkg.v:
-- Floating point simulation model for verilog.
--
-----------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Single precision units.
-- FAdd, FSub, FAddSub, FMul, FDiv, FSqrt, FRSqrt, FRecip, Flog
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Double precision units.
-- DAdd, DSub, DAddSub, DMul, DDiv, DSqrt, DRSqrt, DRecip, FLog
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Single precision units.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Single precision Add.
-------------------------------------------------------------------------------
*/
module ACMP_fadd_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FAdd #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FAdd_U (
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fadd(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FAdd #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FAdd_U (
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Single precision Sub.
-------------------------------------------------------------------------------
*/
module ACMP_fsub_comb (din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FSub #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FSub_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fsub(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FSub #(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FSub_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Single precision AddSub.
-------------------------------------------------------------------------------
*/
module ACMP_faddfsub_comb(opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[1:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FAddFSub
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FAddFSub_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_faddfsub(clk, reset, ce, opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[1:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FAddFSub
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FAddFSub_U(
.clk(clk),
.reset(reset),
.ce(ce),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Single precision Mul.
-------------------------------------------------------------------------------
*/
module ACMP_fmul_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FMul
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FMul_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fmul(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FMul
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FMul_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Single precision Div.
-------------------------------------------------------------------------------
*/
module ACMP_fdiv_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FDiv
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FDiv_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fdiv(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FDiv
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FDiv_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Single precision Sqrt.
-------------------------------------------------------------------------------
*/
module ACMP_fsqrt_comb (din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FSqrt
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FSqrt_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fsqrt(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FSqrt
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FSqrt_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Single precision RSqrt.
-------------------------------------------------------------------------------
*/
module ACMP_frsqrt_comb (din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FRSqrt
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FRSqrt_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_frsqrt(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FRSqrt
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FRSqrt_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Single precision Recip.
-------------------------------------------------------------------------------
*/
module ACMP_frecip_comb (din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FRecip
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FRecip_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_frecip(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FRecip
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FRecip_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Single precision Log.
-------------------------------------------------------------------------------
*/
module ACMP_flog_comb (din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FLog
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FLog_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_flog(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_FLog
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_Flog_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Double precision
-------------------------------------------------------------------------------
*/
/*
-------------------------------------------------------------------------------
-- Double precision ADD
-------------------------------------------------------------------------------
*/
module ACMP_dadd_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DAdd
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DAdd_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dadd(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DAdd
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DAdd_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Double precision Sub
-------------------------------------------------------------------------------
*/
module ACMP_dsub_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DSub
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DSub_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dsub(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DSub
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DSub_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Double precision AddSub
-------------------------------------------------------------------------------
*/
module ACMP_dadddsub_comb(opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[1:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DAddDSub
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DAddDSub_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dadddsub(clk, reset, ce, opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[1:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DAddDSub
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DAddDSub_U(
.clk(clk),
.reset(reset),
.ce(ce),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Double precision Mul
-------------------------------------------------------------------------------
*/
module ACMP_dmul_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DMul
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DMul_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dmul(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DMul
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DMul_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Double precision Div
-------------------------------------------------------------------------------
*/
module ACMP_ddiv_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DDiv
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DDiv_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_ddiv(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DDiv
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DDiv_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Double precision Sqrt
-------------------------------------------------------------------------------
*/
module ACMP_dsqrt_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DSqrt
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DSqrt_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dsqrt(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DSqrt
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DSqrt_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Double precision RSqrt
-------------------------------------------------------------------------------
*/
module ACMP_drsqrt_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DRSqrt
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DRSqrt_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_drsqrt(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DRSqrt
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DRSqrt_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Double precision Recip
-------------------------------------------------------------------------------
*/
module ACMP_drecip_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DRecip
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DRecip_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_drecip(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DRecip
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DRecip_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Double precision Log
-------------------------------------------------------------------------------
*/
module ACMP_dlog_comb(din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DLog
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DLog_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dlog(clk, reset, ce, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 13;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 64;
input clk, reset, ce;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[dout_WIDTH-1:0] dout;
AESL_WP_DLog
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DLog_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Single precision Cmp (Comparator)
-------------------------------------------------------------------------------
-- Predicate values:
-- FCMP_FALSE = 0, ///< 0 0 0 0 Always false (always folded)
-- FCMP_OEQ = 1, ///< 0 0 0 1 True if ordered and equal
-- FCMP_OGT = 2, ///< 0 0 1 0 True if ordered and greater than
-- FCMP_OGE = 3, ///< 0 0 1 1 True if ordered and greater than or equal
-- FCMP_OLT = 4, ///< 0 1 0 0 True if ordered and less than
-- FCMP_OLE = 5, ///< 0 1 0 1 True if ordered and less than or equal
-- FCMP_ONE = 6, ///< 0 1 1 0 True if ordered and operands are unequal
-- FCMP_ORD = 7, ///< 0 1 1 1 True if ordered (no nans)
-- FCMP_UNO = 8, ///< 1 0 0 0 True if unordered: isnan(X) | isnan(Y)
-- FCMP_UEQ = 9, ///< 1 0 0 1 True if unordered or equal
-- FCMP_UGT =10, ///< 1 0 1 0 True if unordered or greater than
-- FCMP_UGE =11, ///< 1 0 1 1 True if unordered, greater than, or equal
-- FCMP_ULT =12, ///< 1 1 0 0 True if unordered or less than
-- FCMP_ULE =13, ///< 1 1 0 1 True if unordered, less than, or equal
-- FCMP_UNE =14, ///< 1 1 1 0 True if unordered or not equal
-- FCMP_TRUE =15, ///< 1 1 1 1 Always true (always folded)
*/
module ACMP_fcmp_comb(opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 1;
input[4:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[0:0] dout;
AESL_WP_FCmp
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FCmp_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_fcmp(clk, reset, ce, opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter din1_WIDTH = 32;
parameter dout_WIDTH = 1;
input clk;
input reset, ce;
input[4:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[0:0] dout;
AESL_WP_FCmp
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_FCmp_U(
.clk(clk),
.reset(reset),
.ce(ce),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Double precision Cmp (Comparator)
-------------------------------------------------------------------------------
-- Predicate values:
-- FCMP_FALSE = 0, ///< 0 0 0 0 Always false (always folded)
-- FCMP_OEQ = 1, ///< 0 0 0 1 True if ordered and equal
-- FCMP_OGT = 2, ///< 0 0 1 0 True if ordered and greater than
-- FCMP_OGE = 3, ///< 0 0 1 1 True if ordered and greater than or equal
-- FCMP_OLT = 4, ///< 0 1 0 0 True if ordered and less than
-- FCMP_OLE = 5, ///< 0 1 0 1 True if ordered and less than or equal
-- FCMP_ONE = 6, ///< 0 1 1 0 True if ordered and operands are unequal
-- FCMP_ORD = 7, ///< 0 1 1 1 True if ordered (no nans)
-- FCMP_UNO = 8, ///< 1 0 0 0 True if unordered: isnan(X) | isnan(Y)
-- FCMP_UEQ = 9, ///< 1 0 0 1 True if unordered or equal
-- FCMP_UGT =10, ///< 1 0 1 0 True if unordered or greater than
-- FCMP_UGE =11, ///< 1 0 1 1 True if unordered, greater than, or equal
-- FCMP_ULT =12, ///< 1 1 0 0 True if unordered or less than
-- FCMP_ULE =13, ///< 1 1 0 1 True if unordered, less than, or equal
-- FCMP_UNE =14, ///< 1 1 1 0 True if unordered or not equal
-- FCMP_TRUE =15, ///< 1 1 1 1 Always true (always folded)
*/
module ACMP_dcmp_comb(opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 1;
input[4:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[0:0] dout;
AESL_WP_DCmp
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DCmp_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
module ACMP_dcmp(clk, reset, ce, opcode, din0, din1, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 64;
parameter din1_WIDTH = 64;
parameter dout_WIDTH = 1;
input clk;
input reset, ce;
input[4:0] opcode;
input[din0_WIDTH-1:0] din0;
input[din1_WIDTH-1:0] din1;
output[0:0] dout;
AESL_WP_DCmp
#(NUM_STAGE, din0_WIDTH, din1_WIDTH, dout_WIDTH)
ACMP_DCmp_U(
.clk(clk),
.reset(reset),
.ce(ce),
.opcode(opcode),
.din0(din0),
.din1(din1),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Single precision to int32
-------------------------------------------------------------------------------
*/
module ACMP_fptosi_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SPToSI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SPToSI_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_fptosi(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SPToSI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SPToSI_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Double precision to int32
-------------------------------------------------------------------------------
*/
module ACMP_dptosi_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 64;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_DPToSI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_DPToSI_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_dptosi(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 64;
parameter dout_WIDTH = 32;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_DPToSI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_DPToSI_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Int32 to single precision
-------------------------------------------------------------------------------
*/
module ACMP_sitofp_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SIToSP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SIToDP_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_sitofp(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SIToSP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SIToDP_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Int32 to double precision
-------------------------------------------------------------------------------
*/
module ACMP_sitodp_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SIToDP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SIToDP_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_sitodp(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SIToDP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SIToDP_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Single precision to uint32
-------------------------------------------------------------------------------
*/
module ACMP_fptoui_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SPToUI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SPToUI_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_fptoui(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 32;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SPToUI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_SPToUI_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- Double precision to uint32
-------------------------------------------------------------------------------
*/
module ACMP_dptoui_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 64;
parameter dout_WIDTH = 32;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_DPToUI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_DPToUI_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_dptoui(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 64;
parameter dout_WIDTH = 32;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_DPToUI
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_DPToUI_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- uInt32 to single precision
-------------------------------------------------------------------------------
*/
module ACMP_uitofp_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_UIToSP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_UIToSP_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_uitofp(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_UIToSP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_UIToSP_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- uInt32 to double precision
-------------------------------------------------------------------------------
*/
module ACMP_uitodp_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_UIToDP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_UIToDP_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_uitodp(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_UIToDP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_UIToDP_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- single to double precision
-------------------------------------------------------------------------------
*/
module ACMP_fpext_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SPToDP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_fpext_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_fpext(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_SPToDP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_fpext_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
/*
-------------------------------------------------------------------------------
-- double to single precision
-------------------------------------------------------------------------------
*/
module ACMP_fptrunc_comb(din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_DPToSP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_fptrunc_U(
.clk(1'b1),
.reset(1'b1),
.ce(1'b1),
.din0(din0),
.dout(dout));
endmodule
module ACMP_fptrunc(clk, reset, ce, din0, dout);
parameter ID = 0;
parameter NUM_STAGE = 12;
parameter din0_WIDTH = 32;
parameter dout_WIDTH = 64;
input clk;
input reset, ce;
input[din0_WIDTH-1:0] din0;
output[dout_WIDTH-1:0] dout;
AESL_WP_DPToSP
#(NUM_STAGE, din0_WIDTH, dout_WIDTH)
ACMP_fptrunc_U(
.clk(clk),
.reset(reset),
.ce(ce),
.din0(din0),
.dout(dout));
endmodule
|
//-------------------------------------------------------------------
//-- fsmtx_tb.v
//-- Banco de pruebas para la tranmision de datos
//-------------------------------------------------------------------
//-- BQ September 2015. Written by Juan Gonzalez (Obijuan)
//-------------------------------------------------------------------
//-- GPL License
//-------------------------------------------------------------------
`include "baudgen.vh"
module fsmtx_tb();
//-- Baudios con los que realizar la simulacion
//-- A 300 baudios, la simulacion tarda mas en realizarse porque los
//-- tiempos son mas largos. A 115200 baudios la simulacion es mucho
//-- mas rapida
localparam BAUD = `B115200;
//-- Tics de reloj para envio de datos a esa velocidad
//-- Se multiplica por 2 porque el periodo del reloj es de 2 unidades
localparam BITRATE = (BAUD << 1);
//-- Tics necesarios para enviar una trama serie completa, mas un bit adicional
localparam FRAME = (BITRATE * 11);
//-- Tiempo entre dos bits enviados
localparam FRAME_WAIT = (BITRATE * 4);
//-- Registro para generar la señal de reloj
reg clk = 0;
//-- Linea de tranmision
wire tx;
//-- Simulacion de la señal start
reg start = 0;
//-- Instanciar el componente
fsmtx #(.BAUD(BAUD))
dut(
.clk(clk),
.start(start),
.tx(tx)
);
//-- Generador de reloj. Periodo 2 unidades
always
# 1 clk <= ~clk;
//-- Proceso al inicio
initial begin
//-- Fichero donde almacenar los resultados
$dumpfile("fsmtx_tb.vcd");
$dumpvars(0, fsmtx_tb);
#1 start <= 0;
//-- Enviar primer caracter
#FRAME_WAIT start <= 1;
#(BITRATE * 2) start <=0;
//-- Segundo envio (2 caracteres mas)
#(FRAME_WAIT * 2) start <=1;
#(FRAME * 1) start <=0;
#(FRAME_WAIT * 4) $display("FIN de la simulacion");
$finish;
end
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// CompletionDataChannel for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Kibin Park <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Kibin Park <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: Completion data channel
// Module Name: CompletionDataChannel
// File Name: CompletionDataChannel.v
//
// Version: v1.0.0
//
// Description: Reports completion of an operation
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module CompletionDataChannel
#
(
parameter DataWidth = 32 ,
parameter InnerIFLengthWidth = 16 ,
parameter ThisID = 1
)
(
iClock ,
iReset ,
iSrcLength ,
iSrcTargetID ,
iSrcValid ,
oSrcReady ,
iSrcWriteData ,
iSrcWriteValid ,
iSrcWriteLast ,
oSrcWriteReady ,
oDstWriteData ,
oDstWriteValid ,
oDstWriteLast ,
iDstWriteReady
);
input iClock ;
input iReset ;
// Master side
input [4:0] iSrcTargetID ;
input [InnerIFLengthWidth - 1:0] iSrcLength ;
input iSrcValid ;
output oSrcReady ;
input [DataWidth - 1:0] iSrcWriteData ;
input iSrcWriteValid ;
input iSrcWriteLast ;
output oSrcWriteReady ;
output [DataWidth - 1:0] oDstWriteData ;
output oDstWriteValid ;
output oDstWriteLast ;
input iDstWriteReady ;
reg rSrcWReady ;
reg rDstWValid ;
reg rDstWLast ;
wire wFLenQPushSig ;
wire wFLenQPopSig ;
wire wIsFLenQFull ;
wire wIsFLenQEmpty ;
wire wFLenQDValid ;
wire wFLenQDReady ;
wire [InnerIFLengthWidth - 1:0] wFLenLength ;
wire [4:0] wFTargetID ;
reg [DataWidth - 1:0] rOutData ;
assign wFLenQPushSig = iSrcValid & oSrcReady ;
assign oSrcWriteReady = rSrcWReady ;
assign oDstWriteData = rOutData ;
assign oDstWriteValid = rDstWValid ;
assign oDstWriteLast = rDstWLast ;
assign oSrcReady = !wIsFLenQFull ;
localparam State_Idle = 2'b00;
localparam State_ReportCmplt = 2'b01;
localparam State_Forward = 2'b11;
reg [1:0] rDataChCurState ;
reg [1:0] rDataChNextState;
always @ (posedge iClock)
if (iReset)
rDataChCurState <= State_Idle;
else
rDataChCurState <= rDataChNextState;
always @ (*)
case (rDataChCurState)
State_Idle:
if (wFLenQDValid)
begin
if (wFTargetID == ThisID)
rDataChNextState <= State_ReportCmplt;
else if (wFLenLength == 0)
rDataChNextState <= State_Idle;
else
rDataChNextState <= State_Forward;
end
else
rDataChNextState <= State_Idle;
State_ReportCmplt:
rDataChNextState <= (iDstWriteReady)?State_Idle:State_ReportCmplt;
State_Forward:
rDataChNextState <= (oDstWriteValid && oDstWriteLast && iDstWriteReady)?State_Idle:State_Forward;
default:
rDataChNextState <= State_Idle;
endcase
assign wFLenQDReady = (rDataChCurState == State_Idle);
SCFIFO_64x64_withCount
Inst_ForwardedDataQ
(
.iClock (iClock ),
.iReset (iReset ),
.iPushData ({iSrcLength, iSrcTargetID} ),
.iPushEnable (wFLenQPushSig ),
.oIsFull (wIsFLenQFull ),
.oPopData ({wFLenLength, wFTargetID} ),
.iPopEnable (wFLenQPopSig ),
.oIsEmpty (wIsFLenQEmpty ),
.oDataCount ( )
);
AutoFIFOPopControl
Inst_ForwardedDataQPopControl
(
.iClock (iClock ),
.iReset (iReset ),
.oPopSignal (wFLenQPopSig ),
.iEmpty (wIsFLenQEmpty ),
.oValid (wFLenQDValid ),
.iReady (wFLenQDReady )
);
always @ (*)
case (rDataChCurState)
State_ReportCmplt:
rOutData <= 32'hA5000001;
State_Forward:
rOutData <= iSrcWriteData;
default:
rOutData <= 1'b0;
endcase
always @ (*)
case (rDataChCurState)
State_Forward:
rSrcWReady <= iDstWriteReady;
default:
rSrcWReady <= 1'b0;
endcase
always @ (*)
case (rDataChCurState)
State_ReportCmplt:
rDstWValid <= 1'b1;
State_Forward:
rDstWValid <= iSrcWriteValid;
default:
rDstWValid <= 1'b0;
endcase
always @ (*)
case (rDataChCurState)
State_ReportCmplt:
rDstWLast <= 1'b1;
default:
rDstWLast <= iSrcWriteLast;
endcase
endmodule |
/////////////////////////////////////////////////////////////////////
//// ////
//// Non-restoring unsigned divider ////
//// ////
//// Author: Richard Herveille ////
//// [email protected] ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: div_uu.v,v 1.3 2003/09/17 13:08:53 rherveille Exp $
//
// $Date: 2003/09/17 13:08:53 $
// $Revision: 1.3 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: div_uu.v,v $
// Revision 1.3 2003/09/17 13:08:53 rherveille
// Fixed a bug in the remainder output. Changed a hard value into the required parameter.
// Fixed a bug in the testbench.
//
// Revision 1.2 2002/10/31 13:54:58 rherveille
// Fixed a bug in the remainder output of div_su.v
//
// Revision 1.1.1.1 2002/10/29 20:29:10 rherveille
//
//
//
//synopsys translate_off
`timescale 1ns/10ps
//synopsys translate_on
module zet_div_uu(clk, ena, z, d, q, s, div0, ovf);
//
// parameters
//
parameter z_width = 16;
parameter d_width = z_width /2;
//
// inputs & outputs
//
input clk; // system clock
input ena; // clock enable
input [z_width -1:0] z; // divident
input [d_width -1:0] d; // divisor
output [d_width -1:0] q; // quotient
output [d_width -1:0] s; // remainder
output div0;
output ovf;
reg [d_width-1:0] q;
reg [d_width-1:0] s;
reg div0;
reg ovf;
//
// functions
//
function [z_width:0] gen_s;
input [z_width:0] si;
input [z_width:0] di;
begin
if(si[z_width])
gen_s = {si[z_width-1:0], 1'b0} + di;
else
gen_s = {si[z_width-1:0], 1'b0} - di;
end
endfunction
function [d_width-1:0] gen_q;
input [d_width-1:0] qi;
input [z_width:0] si;
begin
gen_q = {qi[d_width-2:0], ~si[z_width]};
end
endfunction
function [d_width-1:0] assign_s;
input [z_width:0] si;
input [z_width:0] di;
reg [z_width:0] tmp;
begin
if(si[z_width])
tmp = si + di;
else
tmp = si;
assign_s = tmp[z_width-1:z_width-d_width];
end
endfunction
//
// variables
//
reg [d_width-1:0] q_pipe [d_width-1:0];
reg [z_width:0] s_pipe [d_width:0];
reg [z_width:0] d_pipe [d_width:0];
reg [d_width:0] div0_pipe, ovf_pipe;
//
// perform parameter checks
//
// synopsys translate_off
initial
begin
if(d_width !== z_width / 2)
$display("div.v parameter error (d_width != z_width/2).");
end
// synopsys translate_on
integer n0, n1, n2, n3;
// generate divisor (d) pipe
always @(d)
d_pipe[0] <= {1'b0, d, {(z_width-d_width){1'b0}} };
always @(posedge clk)
if(ena)
for(n0=1; n0 <= d_width; n0=n0+1)
d_pipe[n0] <= d_pipe[n0-1];
// generate internal remainder pipe
always @(z)
s_pipe[0] <= z;
always @(posedge clk)
if(ena)
for(n1=1; n1 <= d_width; n1=n1+1)
s_pipe[n1] <= gen_s(s_pipe[n1-1], d_pipe[n1-1]);
// generate quotient pipe
always @(posedge clk)
q_pipe[0] <= 0;
always @(posedge clk)
if(ena)
for(n2=1; n2 < d_width; n2=n2+1)
q_pipe[n2] <= gen_q(q_pipe[n2-1], s_pipe[n2]);
// flags (divide_by_zero, overflow)
always @(z or d)
begin
ovf_pipe[0] <= !(z[z_width-1:d_width] < d);
div0_pipe[0] <= ~|d;
end
always @(posedge clk)
if(ena)
for(n3=1; n3 <= d_width; n3=n3+1)
begin
ovf_pipe[n3] <= ovf_pipe[n3-1];
div0_pipe[n3] <= div0_pipe[n3-1];
end
// assign outputs
always @(posedge clk)
if(ena)
ovf <= ovf_pipe[d_width];
always @(posedge clk)
if(ena)
div0 <= div0_pipe[d_width];
always @(posedge clk)
if(ena)
q <= gen_q(q_pipe[d_width-1], s_pipe[d_width]);
always @(posedge clk)
if(ena)
s <= assign_s(s_pipe[d_width], d_pipe[d_width]);
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="qam_dem_top,hls_ip_2014_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=1,HLS_INPUT_PART=xc6slx45tfgg484-3,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=dataflow,HLS_SYN_CLOCK=8.646000,HLS_SYN_LAT=14,HLS_SYN_TPT=15,HLS_SYN_MEM=1,HLS_SYN_DSP=0,HLS_SYN_FF=436,HLS_SYN_LUT=1285}" *)
module qam_dem_top (
din_i_V,
din_q_V,
dout_mix_i_V,
dout_mix_q_V,
ph_in_i_V,
ph_in_q_V,
ph_out_i_V,
ph_out_q_V,
loop_integ_V,
control_qam_V,
control_lf_p,
control_lf_i,
control_lf_out_gain,
control_reg_clr,
control_reg_init_V,
ap_clk,
ap_rst,
ap_done,
ap_start,
ap_idle,
ap_ready
);
parameter ap_const_lv16_0 = 16'b0000000000000000;
parameter ap_const_lv12_0 = 12'b000000000000;
parameter ap_const_lv28_0 = 28'b0000000000000000000000000000;
parameter ap_const_logic_1 = 1'b1;
parameter ap_true = 1'b1;
parameter ap_const_logic_0 = 1'b0;
input [15:0] din_i_V;
input [15:0] din_q_V;
output [15:0] dout_mix_i_V;
output [15:0] dout_mix_q_V;
input [11:0] ph_in_i_V;
input [11:0] ph_in_q_V;
output [11:0] ph_out_i_V;
output [11:0] ph_out_q_V;
output [27:0] loop_integ_V;
input [1:0] control_qam_V;
input [7:0] control_lf_p;
input [7:0] control_lf_i;
input [7:0] control_lf_out_gain;
input [0:0] control_reg_clr;
input [27:0] control_reg_init_V;
input ap_clk;
input ap_rst;
output ap_done;
input ap_start;
output ap_idle;
output ap_ready;
reg ap_idle;
wire qam_dem_top_mounstrito_U0_ap_start;
wire qam_dem_top_mounstrito_U0_ap_done;
wire qam_dem_top_mounstrito_U0_ap_continue;
wire qam_dem_top_mounstrito_U0_ap_idle;
wire qam_dem_top_mounstrito_U0_ap_ready;
wire [15:0] qam_dem_top_mounstrito_U0_din_i_V;
wire [15:0] qam_dem_top_mounstrito_U0_din_q_V;
wire [15:0] qam_dem_top_mounstrito_U0_dout_mix_i_V;
wire qam_dem_top_mounstrito_U0_dout_mix_i_V_ap_vld;
wire [15:0] qam_dem_top_mounstrito_U0_dout_mix_q_V;
wire qam_dem_top_mounstrito_U0_dout_mix_q_V_ap_vld;
wire [11:0] qam_dem_top_mounstrito_U0_ph_in_i_V;
wire [11:0] qam_dem_top_mounstrito_U0_ph_in_q_V;
wire [11:0] qam_dem_top_mounstrito_U0_ph_out_i_V;
wire qam_dem_top_mounstrito_U0_ph_out_i_V_ap_vld;
wire [11:0] qam_dem_top_mounstrito_U0_ph_out_q_V;
wire qam_dem_top_mounstrito_U0_ph_out_q_V_ap_vld;
wire [27:0] qam_dem_top_mounstrito_U0_loop_integ_V;
wire qam_dem_top_mounstrito_U0_loop_integ_V_ap_vld;
wire [7:0] qam_dem_top_mounstrito_U0_control_lf_p;
wire [7:0] qam_dem_top_mounstrito_U0_control_lf_i;
wire [7:0] qam_dem_top_mounstrito_U0_control_lf_out_gain;
wire [0:0] qam_dem_top_mounstrito_U0_control_reg_clr;
wire [27:0] qam_dem_top_mounstrito_U0_control_reg_init_V;
wire ap_sig_hs_continue;
reg ap_reg_procdone_qam_dem_top_mounstrito_U0 = 1'b0;
reg ap_sig_hs_done;
reg ap_CS;
wire ap_sig_top_allready;
qam_dem_top_mounstrito qam_dem_top_mounstrito_U0(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.ap_start( qam_dem_top_mounstrito_U0_ap_start ),
.ap_done( qam_dem_top_mounstrito_U0_ap_done ),
.ap_continue( qam_dem_top_mounstrito_U0_ap_continue ),
.ap_idle( qam_dem_top_mounstrito_U0_ap_idle ),
.ap_ready( qam_dem_top_mounstrito_U0_ap_ready ),
.din_i_V( qam_dem_top_mounstrito_U0_din_i_V ),
.din_q_V( qam_dem_top_mounstrito_U0_din_q_V ),
.dout_mix_i_V( qam_dem_top_mounstrito_U0_dout_mix_i_V ),
.dout_mix_i_V_ap_vld( qam_dem_top_mounstrito_U0_dout_mix_i_V_ap_vld ),
.dout_mix_q_V( qam_dem_top_mounstrito_U0_dout_mix_q_V ),
.dout_mix_q_V_ap_vld( qam_dem_top_mounstrito_U0_dout_mix_q_V_ap_vld ),
.ph_in_i_V( qam_dem_top_mounstrito_U0_ph_in_i_V ),
.ph_in_q_V( qam_dem_top_mounstrito_U0_ph_in_q_V ),
.ph_out_i_V( qam_dem_top_mounstrito_U0_ph_out_i_V ),
.ph_out_i_V_ap_vld( qam_dem_top_mounstrito_U0_ph_out_i_V_ap_vld ),
.ph_out_q_V( qam_dem_top_mounstrito_U0_ph_out_q_V ),
.ph_out_q_V_ap_vld( qam_dem_top_mounstrito_U0_ph_out_q_V_ap_vld ),
.loop_integ_V( qam_dem_top_mounstrito_U0_loop_integ_V ),
.loop_integ_V_ap_vld( qam_dem_top_mounstrito_U0_loop_integ_V_ap_vld ),
.control_lf_p( qam_dem_top_mounstrito_U0_control_lf_p ),
.control_lf_i( qam_dem_top_mounstrito_U0_control_lf_i ),
.control_lf_out_gain( qam_dem_top_mounstrito_U0_control_lf_out_gain ),
.control_reg_clr( qam_dem_top_mounstrito_U0_control_reg_clr ),
.control_reg_init_V( qam_dem_top_mounstrito_U0_control_reg_init_V )
);
/// ap_reg_procdone_qam_dem_top_mounstrito_U0 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_procdone_qam_dem_top_mounstrito_U0
if (ap_rst == 1'b1) begin
ap_reg_procdone_qam_dem_top_mounstrito_U0 <= ap_const_logic_0;
end else begin
if ((ap_const_logic_1 == ap_sig_hs_done)) begin
ap_reg_procdone_qam_dem_top_mounstrito_U0 <= ap_const_logic_0;
end else if ((qam_dem_top_mounstrito_U0_ap_done == ap_const_logic_1)) begin
ap_reg_procdone_qam_dem_top_mounstrito_U0 <= ap_const_logic_1;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
ap_CS <= ap_const_logic_0;
end
/// ap_idle assign process. ///
always @ (qam_dem_top_mounstrito_U0_ap_idle)
begin
if ((qam_dem_top_mounstrito_U0_ap_idle == ap_const_logic_1)) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// ap_sig_hs_done assign process. ///
always @ (qam_dem_top_mounstrito_U0_ap_done)
begin
if ((qam_dem_top_mounstrito_U0_ap_done == ap_const_logic_1)) begin
ap_sig_hs_done = ap_const_logic_1;
end else begin
ap_sig_hs_done = ap_const_logic_0;
end
end
assign ap_done = ap_sig_hs_done;
assign ap_ready = ap_sig_top_allready;
assign ap_sig_hs_continue = ap_const_logic_1;
assign ap_sig_top_allready = qam_dem_top_mounstrito_U0_ap_ready;
assign dout_mix_i_V = qam_dem_top_mounstrito_U0_dout_mix_i_V;
assign dout_mix_q_V = qam_dem_top_mounstrito_U0_dout_mix_q_V;
assign loop_integ_V = qam_dem_top_mounstrito_U0_loop_integ_V;
assign ph_out_i_V = qam_dem_top_mounstrito_U0_ph_out_i_V;
assign ph_out_q_V = qam_dem_top_mounstrito_U0_ph_out_q_V;
assign qam_dem_top_mounstrito_U0_ap_continue = ap_sig_hs_continue;
assign qam_dem_top_mounstrito_U0_ap_start = ap_start;
assign qam_dem_top_mounstrito_U0_control_lf_i = control_lf_i;
assign qam_dem_top_mounstrito_U0_control_lf_out_gain = control_lf_out_gain;
assign qam_dem_top_mounstrito_U0_control_lf_p = control_lf_p;
assign qam_dem_top_mounstrito_U0_control_reg_clr = control_reg_clr;
assign qam_dem_top_mounstrito_U0_control_reg_init_V = control_reg_init_V;
assign qam_dem_top_mounstrito_U0_din_i_V = din_i_V;
assign qam_dem_top_mounstrito_U0_din_q_V = din_q_V;
assign qam_dem_top_mounstrito_U0_ph_in_i_V = ph_in_i_V;
assign qam_dem_top_mounstrito_U0_ph_in_q_V = ph_in_q_V;
endmodule //qam_dem_top
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR4B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__NOR4B_BEHAVIORAL_PP_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__nor4b (
Y ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out , D_N );
nor nor0 (nor0_out_Y , A, B, C, not0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR4B_BEHAVIORAL_PP_V |
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.20131013
// \ \ Application: netgen
// / / Filename: sum.v
// /___/ /\ Timestamp: Thu Mar 26 23:34:38 2015
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog /home/vka/Programming/VHDL/workspace/sysrek/martix_multiplier/ipcore_dir/tmp/_cg/sum.ngc /home/vka/Programming/VHDL/workspace/sysrek/martix_multiplier/ipcore_dir/tmp/_cg/sum.v
// Device : 3s500efg320-4
// Input file : /home/vka/Programming/VHDL/workspace/sysrek/martix_multiplier/ipcore_dir/tmp/_cg/sum.ngc
// Output file : /home/vka/Programming/VHDL/workspace/sysrek/martix_multiplier/ipcore_dir/tmp/_cg/sum.v
// # of Modules : 1
// Design Name : sum
// Xilinx : /mnt/data/Xilinx/14.7/ISE_DS/ISE/
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module sum (
clk, s, a, b
)/* synthesis syn_black_box syn_noprune=1 */;
input clk;
output [26 : 0] s;
input [25 : 0] a;
input [25 : 0] b;
// synthesis translate_off
wire \blk00000001/sig00000107 ;
wire \blk00000001/sig00000106 ;
wire \blk00000001/sig00000105 ;
wire \blk00000001/sig00000104 ;
wire \blk00000001/sig00000103 ;
wire \blk00000001/sig00000102 ;
wire \blk00000001/sig00000101 ;
wire \blk00000001/sig00000100 ;
wire \blk00000001/sig000000ff ;
wire \blk00000001/sig000000fe ;
wire \blk00000001/sig000000fd ;
wire \blk00000001/sig000000fc ;
wire \blk00000001/sig000000fb ;
wire \blk00000001/sig000000fa ;
wire \blk00000001/sig000000f9 ;
wire \blk00000001/sig000000f8 ;
wire \blk00000001/sig000000f7 ;
wire \blk00000001/sig000000f6 ;
wire \blk00000001/sig000000ec ;
wire \blk00000001/sig000000eb ;
wire \blk00000001/sig000000ea ;
wire \blk00000001/sig000000e9 ;
wire \blk00000001/sig000000e8 ;
wire \blk00000001/sig000000e7 ;
wire \blk00000001/sig000000e6 ;
wire \blk00000001/sig000000e5 ;
wire \blk00000001/sig000000db ;
wire \blk00000001/sig000000d1 ;
wire \blk00000001/sig000000d0 ;
wire \blk00000001/sig000000cf ;
wire \blk00000001/sig000000ce ;
wire \blk00000001/sig000000cd ;
wire \blk00000001/sig000000cc ;
wire \blk00000001/sig000000cb ;
wire \blk00000001/sig000000ca ;
wire \blk00000001/sig000000c9 ;
wire \blk00000001/sig000000c8 ;
wire \blk00000001/sig000000c7 ;
wire \blk00000001/sig000000c6 ;
wire \blk00000001/sig000000c5 ;
wire \blk00000001/sig000000c4 ;
wire \blk00000001/sig000000c3 ;
wire \blk00000001/sig000000c2 ;
wire \blk00000001/sig000000c1 ;
wire \blk00000001/sig000000c0 ;
wire \blk00000001/sig000000bf ;
wire \blk00000001/sig000000be ;
wire \blk00000001/sig000000bd ;
wire \blk00000001/sig000000bc ;
wire \blk00000001/sig000000bb ;
wire \blk00000001/sig000000ba ;
wire \blk00000001/sig000000b9 ;
wire \blk00000001/sig000000b8 ;
wire \blk00000001/sig000000b7 ;
wire \blk00000001/sig000000b6 ;
wire \blk00000001/sig000000b5 ;
wire \blk00000001/sig000000b4 ;
wire \blk00000001/sig000000b3 ;
wire \blk00000001/sig000000b2 ;
wire \blk00000001/sig000000b1 ;
wire \blk00000001/sig000000b0 ;
wire \blk00000001/sig000000af ;
wire \blk00000001/sig000000ae ;
wire \blk00000001/sig000000ad ;
wire \blk00000001/sig000000ac ;
wire \blk00000001/sig000000ab ;
wire \blk00000001/sig000000aa ;
wire \blk00000001/sig000000a9 ;
wire \blk00000001/sig000000a8 ;
wire \blk00000001/sig000000a7 ;
wire \blk00000001/sig000000a6 ;
wire \blk00000001/sig000000a5 ;
wire \blk00000001/sig000000a4 ;
wire \blk00000001/sig000000a3 ;
wire \blk00000001/sig000000a2 ;
wire \blk00000001/sig000000a1 ;
wire \blk00000001/sig000000a0 ;
wire \blk00000001/sig0000009f ;
wire \blk00000001/sig0000009e ;
wire \blk00000001/sig0000009d ;
wire \blk00000001/sig0000009c ;
wire \blk00000001/sig0000009b ;
wire \blk00000001/sig0000009a ;
wire \blk00000001/sig00000099 ;
wire \blk00000001/sig00000098 ;
wire \blk00000001/sig00000097 ;
wire \blk00000001/sig00000096 ;
wire \blk00000001/sig00000095 ;
wire \blk00000001/sig00000094 ;
wire \blk00000001/sig00000093 ;
wire \blk00000001/sig00000092 ;
wire \blk00000001/sig00000091 ;
wire \blk00000001/sig00000090 ;
wire \blk00000001/sig0000008f ;
wire \blk00000001/sig0000008e ;
wire \blk00000001/sig0000008d ;
wire \blk00000001/sig0000008c ;
wire \blk00000001/sig0000008b ;
wire \blk00000001/sig0000008a ;
wire \blk00000001/sig00000089 ;
wire \blk00000001/sig00000088 ;
wire \blk00000001/sig00000087 ;
wire \blk00000001/sig00000086 ;
wire \blk00000001/sig00000085 ;
wire \blk00000001/sig00000084 ;
wire \blk00000001/sig00000083 ;
wire \blk00000001/sig00000082 ;
wire \blk00000001/sig00000081 ;
wire \blk00000001/sig00000080 ;
wire \blk00000001/sig0000007f ;
wire \blk00000001/sig0000007e ;
wire \blk00000001/sig0000007d ;
wire \blk00000001/sig0000007c ;
wire \blk00000001/sig0000007b ;
wire \blk00000001/sig0000007a ;
wire \blk00000001/sig00000079 ;
wire \blk00000001/sig00000078 ;
wire \blk00000001/sig00000077 ;
wire \blk00000001/sig00000076 ;
wire \blk00000001/sig00000075 ;
wire \blk00000001/sig00000074 ;
wire \blk00000001/sig00000073 ;
wire \blk00000001/sig00000072 ;
wire \blk00000001/sig00000071 ;
wire \blk00000001/sig00000070 ;
wire \blk00000001/sig0000006f ;
wire \blk00000001/sig0000006e ;
wire \blk00000001/sig0000006d ;
wire \blk00000001/sig0000006c ;
wire \blk00000001/sig0000006b ;
wire \blk00000001/sig0000006a ;
wire \blk00000001/sig00000069 ;
wire \blk00000001/sig00000068 ;
wire \blk00000001/sig00000067 ;
wire \blk00000001/sig00000066 ;
wire \blk00000001/sig00000065 ;
wire \blk00000001/sig00000064 ;
wire \blk00000001/sig00000063 ;
wire \blk00000001/sig00000062 ;
wire \blk00000001/sig00000061 ;
wire \blk00000001/sig00000060 ;
wire \blk00000001/sig0000005f ;
wire \blk00000001/sig0000005e ;
wire \blk00000001/sig0000005d ;
wire \blk00000001/sig0000005c ;
wire \blk00000001/sig0000005b ;
wire \blk00000001/sig0000005a ;
wire \blk00000001/sig00000059 ;
wire \blk00000001/sig00000058 ;
wire \blk00000001/sig00000057 ;
wire \blk00000001/sig00000056 ;
wire \blk00000001/sig00000055 ;
wire \blk00000001/sig00000054 ;
wire \blk00000001/sig00000053 ;
wire \blk00000001/sig00000052 ;
wire \blk00000001/sig00000051 ;
wire \blk00000001/sig00000050 ;
wire \blk00000001/sig0000004f ;
wire \blk00000001/sig0000004e ;
wire \blk00000001/sig0000004d ;
wire \blk00000001/sig0000004c ;
wire \blk00000001/sig0000004b ;
wire \blk00000001/sig0000004a ;
wire \blk00000001/sig00000049 ;
wire \blk00000001/sig00000048 ;
wire \blk00000001/sig00000047 ;
wire \blk00000001/sig00000046 ;
wire \blk00000001/sig00000045 ;
wire \blk00000001/sig00000044 ;
wire \blk00000001/sig00000043 ;
wire \blk00000001/sig00000042 ;
wire \blk00000001/sig00000041 ;
wire \blk00000001/sig00000040 ;
wire \blk00000001/sig0000003f ;
wire \blk00000001/sig0000003e ;
wire \blk00000001/sig0000003d ;
wire \blk00000001/sig0000003c ;
wire \blk00000001/sig0000003b ;
wire \blk00000001/sig0000003a ;
wire \blk00000001/sig00000039 ;
wire \blk00000001/sig00000038 ;
wire \blk00000001/sig00000037 ;
wire \blk00000001/sig00000036 ;
wire \NLW_blk00000001/blk00000034_O_UNCONNECTED ;
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000d4 (
.C(clk),
.D(\blk00000001/sig000000db ),
.Q(s[9])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000000d3 (
.A0(\blk00000001/sig00000036 ),
.A1(\blk00000001/sig00000036 ),
.A2(\blk00000001/sig00000036 ),
.A3(\blk00000001/sig00000036 ),
.CLK(clk),
.D(\blk00000001/sig000000ad ),
.Q(\blk00000001/sig000000db )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000d2 (
.C(clk),
.D(\blk00000001/sig000000c9 ),
.Q(s[0])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000000d1 (
.A0(\blk00000001/sig00000037 ),
.A1(\blk00000001/sig00000036 ),
.A2(\blk00000001/sig00000036 ),
.A3(\blk00000001/sig00000036 ),
.CLK(clk),
.D(\blk00000001/sig0000004c ),
.Q(\blk00000001/sig000000c9 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000d0 (
.C(clk),
.D(\blk00000001/sig000000ca ),
.Q(s[1])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000000cf (
.A0(\blk00000001/sig00000037 ),
.A1(\blk00000001/sig00000036 ),
.A2(\blk00000001/sig00000036 ),
.A3(\blk00000001/sig00000036 ),
.CLK(clk),
.D(\blk00000001/sig0000004d ),
.Q(\blk00000001/sig000000ca )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ce (
.C(clk),
.D(\blk00000001/sig000000cb ),
.Q(s[2])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000000cd (
.A0(\blk00000001/sig00000037 ),
.A1(\blk00000001/sig00000036 ),
.A2(\blk00000001/sig00000036 ),
.A3(\blk00000001/sig00000036 ),
.CLK(clk),
.D(\blk00000001/sig0000004e ),
.Q(\blk00000001/sig000000cb )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000cc (
.C(clk),
.D(\blk00000001/sig000000cc ),
.Q(s[3])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000000cb (
.A0(\blk00000001/sig00000037 ),
.A1(\blk00000001/sig00000036 ),
.A2(\blk00000001/sig00000036 ),
.A3(\blk00000001/sig00000036 ),
.CLK(clk),
.D(\blk00000001/sig0000004f ),
.Q(\blk00000001/sig000000cc )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ca (
.C(clk),
.D(\blk00000001/sig000000cd ),
.Q(s[4])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000000c9 (
.A0(\blk00000001/sig00000037 ),
.A1(\blk00000001/sig00000036 ),
.A2(\blk00000001/sig00000036 ),
.A3(\blk00000001/sig00000036 ),
.CLK(clk),
.D(\blk00000001/sig00000050 ),
.Q(\blk00000001/sig000000cd )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000c8 (
.C(clk),
.D(\blk00000001/sig000000cf ),
.Q(s[6])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000000c7 (
.A0(\blk00000001/sig00000037 ),
.A1(\blk00000001/sig00000036 ),
.A2(\blk00000001/sig00000036 ),
.A3(\blk00000001/sig00000036 ),
.CLK(clk),
.D(\blk00000001/sig00000052 ),
.Q(\blk00000001/sig000000cf )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000c6 (
.C(clk),
.D(\blk00000001/sig000000d0 ),
.Q(s[7])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000000c5 (
.A0(\blk00000001/sig00000037 ),
.A1(\blk00000001/sig00000036 ),
.A2(\blk00000001/sig00000036 ),
.A3(\blk00000001/sig00000036 ),
.CLK(clk),
.D(\blk00000001/sig00000053 ),
.Q(\blk00000001/sig000000d0 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000c4 (
.C(clk),
.D(\blk00000001/sig000000ce ),
.Q(s[5])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000000c3 (
.A0(\blk00000001/sig00000037 ),
.A1(\blk00000001/sig00000036 ),
.A2(\blk00000001/sig00000036 ),
.A3(\blk00000001/sig00000036 ),
.CLK(clk),
.D(\blk00000001/sig00000051 ),
.Q(\blk00000001/sig000000ce )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000c2 (
.C(clk),
.D(\blk00000001/sig000000d1 ),
.Q(s[8])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000000c1 (
.A0(\blk00000001/sig00000037 ),
.A1(\blk00000001/sig00000036 ),
.A2(\blk00000001/sig00000036 ),
.A3(\blk00000001/sig00000036 ),
.CLK(clk),
.D(\blk00000001/sig00000054 ),
.Q(\blk00000001/sig000000d1 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000c0 (
.C(clk),
.D(\blk00000001/sig000000b7 ),
.Q(\blk00000001/sig000000c0 )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000000bf (
.A0(\blk00000001/sig00000036 ),
.A1(\blk00000001/sig00000036 ),
.A2(\blk00000001/sig00000036 ),
.A3(\blk00000001/sig00000036 ),
.CLK(clk),
.D(\blk00000001/sig0000008b ),
.Q(\blk00000001/sig000000b7 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000be (
.C(clk),
.D(\blk00000001/sig000000b9 ),
.Q(\blk00000001/sig000000c2 )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000000bd (
.A0(\blk00000001/sig00000036 ),
.A1(\blk00000001/sig00000036 ),
.A2(\blk00000001/sig00000036 ),
.A3(\blk00000001/sig00000036 ),
.CLK(clk),
.D(\blk00000001/sig0000008d ),
.Q(\blk00000001/sig000000b9 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000bc (
.C(clk),
.D(\blk00000001/sig000000ba ),
.Q(\blk00000001/sig000000c3 )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000000bb (
.A0(\blk00000001/sig00000036 ),
.A1(\blk00000001/sig00000036 ),
.A2(\blk00000001/sig00000036 ),
.A3(\blk00000001/sig00000036 ),
.CLK(clk),
.D(\blk00000001/sig0000008e ),
.Q(\blk00000001/sig000000ba )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ba (
.C(clk),
.D(\blk00000001/sig000000b8 ),
.Q(\blk00000001/sig000000c1 )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000000b9 (
.A0(\blk00000001/sig00000036 ),
.A1(\blk00000001/sig00000036 ),
.A2(\blk00000001/sig00000036 ),
.A3(\blk00000001/sig00000036 ),
.CLK(clk),
.D(\blk00000001/sig0000008c ),
.Q(\blk00000001/sig000000b8 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000b8 (
.C(clk),
.D(\blk00000001/sig000000bb ),
.Q(\blk00000001/sig000000c4 )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000000b7 (
.A0(\blk00000001/sig00000036 ),
.A1(\blk00000001/sig00000036 ),
.A2(\blk00000001/sig00000036 ),
.A3(\blk00000001/sig00000036 ),
.CLK(clk),
.D(\blk00000001/sig0000008f ),
.Q(\blk00000001/sig000000bb )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000b6 (
.C(clk),
.D(\blk00000001/sig000000bc ),
.Q(\blk00000001/sig000000c5 )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000000b5 (
.A0(\blk00000001/sig00000036 ),
.A1(\blk00000001/sig00000036 ),
.A2(\blk00000001/sig00000036 ),
.A3(\blk00000001/sig00000036 ),
.CLK(clk),
.D(\blk00000001/sig00000090 ),
.Q(\blk00000001/sig000000bc )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000b4 (
.C(clk),
.D(\blk00000001/sig000000be ),
.Q(\blk00000001/sig000000c7 )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000000b3 (
.A0(\blk00000001/sig00000036 ),
.A1(\blk00000001/sig00000036 ),
.A2(\blk00000001/sig00000036 ),
.A3(\blk00000001/sig00000036 ),
.CLK(clk),
.D(\blk00000001/sig00000092 ),
.Q(\blk00000001/sig000000be )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000b2 (
.C(clk),
.D(\blk00000001/sig000000bf ),
.Q(\blk00000001/sig000000c8 )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000000b1 (
.A0(\blk00000001/sig00000036 ),
.A1(\blk00000001/sig00000036 ),
.A2(\blk00000001/sig00000036 ),
.A3(\blk00000001/sig00000036 ),
.CLK(clk),
.D(\blk00000001/sig00000093 ),
.Q(\blk00000001/sig000000bf )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000b0 (
.C(clk),
.D(\blk00000001/sig000000bd ),
.Q(\blk00000001/sig000000c6 )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000000af (
.A0(\blk00000001/sig00000036 ),
.A1(\blk00000001/sig00000036 ),
.A2(\blk00000001/sig00000036 ),
.A3(\blk00000001/sig00000036 ),
.CLK(clk),
.D(\blk00000001/sig00000091 ),
.Q(\blk00000001/sig000000bd )
);
VCC \blk00000001/blk000000ae (
.P(\blk00000001/sig00000037 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk000000ad (
.I0(\blk00000001/sig000000c0 ),
.O(\blk00000001/sig000000fe )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk000000ac (
.I0(\blk00000001/sig000000c8 ),
.O(\blk00000001/sig000000fd )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk000000ab (
.I0(\blk00000001/sig000000c1 ),
.O(\blk00000001/sig000000f6 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk000000aa (
.I0(\blk00000001/sig000000c2 ),
.O(\blk00000001/sig000000f7 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk000000a9 (
.I0(\blk00000001/sig000000c3 ),
.O(\blk00000001/sig000000f8 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk000000a8 (
.I0(\blk00000001/sig000000c4 ),
.O(\blk00000001/sig000000f9 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk000000a7 (
.I0(\blk00000001/sig000000c5 ),
.O(\blk00000001/sig000000fa )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk000000a6 (
.I0(\blk00000001/sig000000c6 ),
.O(\blk00000001/sig000000fb )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk000000a5 (
.I0(\blk00000001/sig000000c7 ),
.O(\blk00000001/sig000000fc )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk000000a4 (
.I0(\blk00000001/sig00000067 ),
.O(\blk00000001/sig000000ac )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk000000a3 (
.I0(\blk00000001/sig0000006f ),
.O(\blk00000001/sig000000ab )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk000000a2 (
.I0(\blk00000001/sig00000068 ),
.O(\blk00000001/sig000000a4 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk000000a1 (
.I0(\blk00000001/sig00000069 ),
.O(\blk00000001/sig000000a5 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk000000a0 (
.I0(\blk00000001/sig0000006a ),
.O(\blk00000001/sig000000a6 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk0000009f (
.I0(\blk00000001/sig0000006b ),
.O(\blk00000001/sig000000a7 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk0000009e (
.I0(\blk00000001/sig0000006c ),
.O(\blk00000001/sig000000a8 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk0000009d (
.I0(\blk00000001/sig0000006d ),
.O(\blk00000001/sig000000a9 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk0000009c (
.I0(\blk00000001/sig0000006e ),
.O(\blk00000001/sig000000aa )
);
FDS #(
.INIT ( 1'b0 ))
\blk00000001/blk0000009b (
.C(clk),
.D(\blk00000001/sig00000038 ),
.S(\blk00000001/sig00000070 ),
.Q(\blk00000001/sig000000b6 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000009a (
.I0(b[0]),
.I1(a[0]),
.O(\blk00000001/sig00000042 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000099 (
.I0(b[9]),
.I1(a[9]),
.O(\blk00000001/sig0000005e )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000098 (
.I0(b[18]),
.I1(a[18]),
.O(\blk00000001/sig00000082 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000097 (
.I0(b[1]),
.I1(a[1]),
.O(\blk00000001/sig00000043 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000096 (
.I0(b[10]),
.I1(a[10]),
.O(\blk00000001/sig0000005f )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000095 (
.I0(b[19]),
.I1(a[19]),
.O(\blk00000001/sig00000083 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000094 (
.I0(b[2]),
.I1(a[2]),
.O(\blk00000001/sig00000044 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000093 (
.I0(b[11]),
.I1(a[11]),
.O(\blk00000001/sig00000060 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000092 (
.I0(b[20]),
.I1(a[20]),
.O(\blk00000001/sig00000084 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000091 (
.I0(b[3]),
.I1(a[3]),
.O(\blk00000001/sig00000045 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000090 (
.I0(b[12]),
.I1(a[12]),
.O(\blk00000001/sig00000061 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000008f (
.I0(b[21]),
.I1(a[21]),
.O(\blk00000001/sig00000085 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000008e (
.I0(b[4]),
.I1(a[4]),
.O(\blk00000001/sig00000046 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000008d (
.I0(b[13]),
.I1(a[13]),
.O(\blk00000001/sig00000062 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000008c (
.I0(b[22]),
.I1(a[22]),
.O(\blk00000001/sig00000086 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000008b (
.I0(b[5]),
.I1(a[5]),
.O(\blk00000001/sig00000047 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000008a (
.I0(b[14]),
.I1(a[14]),
.O(\blk00000001/sig00000063 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000089 (
.I0(b[23]),
.I1(a[23]),
.O(\blk00000001/sig00000087 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000088 (
.I0(b[6]),
.I1(a[6]),
.O(\blk00000001/sig00000048 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000087 (
.I0(b[15]),
.I1(a[15]),
.O(\blk00000001/sig00000064 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000086 (
.I0(b[24]),
.I1(a[24]),
.O(\blk00000001/sig00000088 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000085 (
.I0(b[7]),
.I1(a[7]),
.O(\blk00000001/sig00000049 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000084 (
.I0(b[16]),
.I1(a[16]),
.O(\blk00000001/sig00000065 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000083 (
.I0(b[25]),
.I1(a[25]),
.O(\blk00000001/sig00000089 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000082 (
.I0(b[8]),
.I1(a[8]),
.O(\blk00000001/sig0000004a )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000081 (
.I0(b[17]),
.I1(a[17]),
.O(\blk00000001/sig00000066 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000080 (
.I0(b[25]),
.I1(a[25]),
.O(\blk00000001/sig0000008a )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000007f (
.C(clk),
.D(\blk00000001/sig0000009c ),
.Q(s[10])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000007e (
.C(clk),
.D(\blk00000001/sig0000009d ),
.Q(s[11])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000007d (
.C(clk),
.D(\blk00000001/sig0000009e ),
.Q(s[12])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000007c (
.C(clk),
.D(\blk00000001/sig0000009f ),
.Q(s[13])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000007b (
.C(clk),
.D(\blk00000001/sig000000a0 ),
.Q(s[14])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000007a (
.C(clk),
.D(\blk00000001/sig000000a1 ),
.Q(s[15])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000079 (
.C(clk),
.D(\blk00000001/sig000000a2 ),
.Q(s[16])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000078 (
.C(clk),
.D(\blk00000001/sig000000a3 ),
.Q(s[17])
);
MUXCY \blk00000001/blk00000077 (
.CI(\blk00000001/sig00000036 ),
.DI(a[9]),
.S(\blk00000001/sig0000005e ),
.O(\blk00000001/sig00000055 )
);
XORCY \blk00000001/blk00000076 (
.CI(\blk00000001/sig00000036 ),
.LI(\blk00000001/sig0000005e ),
.O(\blk00000001/sig00000071 )
);
XORCY \blk00000001/blk00000075 (
.CI(\blk00000001/sig0000005c ),
.LI(\blk00000001/sig00000066 ),
.O(\blk00000001/sig00000079 )
);
MUXCY \blk00000001/blk00000074 (
.CI(\blk00000001/sig0000005c ),
.DI(a[17]),
.S(\blk00000001/sig00000066 ),
.O(\blk00000001/sig0000005d )
);
MUXCY \blk00000001/blk00000073 (
.CI(\blk00000001/sig00000055 ),
.DI(a[10]),
.S(\blk00000001/sig0000005f ),
.O(\blk00000001/sig00000056 )
);
XORCY \blk00000001/blk00000072 (
.CI(\blk00000001/sig00000055 ),
.LI(\blk00000001/sig0000005f ),
.O(\blk00000001/sig00000072 )
);
MUXCY \blk00000001/blk00000071 (
.CI(\blk00000001/sig00000056 ),
.DI(a[11]),
.S(\blk00000001/sig00000060 ),
.O(\blk00000001/sig00000057 )
);
XORCY \blk00000001/blk00000070 (
.CI(\blk00000001/sig00000056 ),
.LI(\blk00000001/sig00000060 ),
.O(\blk00000001/sig00000073 )
);
MUXCY \blk00000001/blk0000006f (
.CI(\blk00000001/sig00000057 ),
.DI(a[12]),
.S(\blk00000001/sig00000061 ),
.O(\blk00000001/sig00000058 )
);
XORCY \blk00000001/blk0000006e (
.CI(\blk00000001/sig00000057 ),
.LI(\blk00000001/sig00000061 ),
.O(\blk00000001/sig00000074 )
);
MUXCY \blk00000001/blk0000006d (
.CI(\blk00000001/sig00000058 ),
.DI(a[13]),
.S(\blk00000001/sig00000062 ),
.O(\blk00000001/sig00000059 )
);
XORCY \blk00000001/blk0000006c (
.CI(\blk00000001/sig00000058 ),
.LI(\blk00000001/sig00000062 ),
.O(\blk00000001/sig00000075 )
);
MUXCY \blk00000001/blk0000006b (
.CI(\blk00000001/sig00000059 ),
.DI(a[14]),
.S(\blk00000001/sig00000063 ),
.O(\blk00000001/sig0000005a )
);
XORCY \blk00000001/blk0000006a (
.CI(\blk00000001/sig00000059 ),
.LI(\blk00000001/sig00000063 ),
.O(\blk00000001/sig00000076 )
);
MUXCY \blk00000001/blk00000069 (
.CI(\blk00000001/sig0000005a ),
.DI(a[15]),
.S(\blk00000001/sig00000064 ),
.O(\blk00000001/sig0000005b )
);
XORCY \blk00000001/blk00000068 (
.CI(\blk00000001/sig0000005a ),
.LI(\blk00000001/sig00000064 ),
.O(\blk00000001/sig00000077 )
);
MUXCY \blk00000001/blk00000067 (
.CI(\blk00000001/sig0000005b ),
.DI(a[16]),
.S(\blk00000001/sig00000065 ),
.O(\blk00000001/sig0000005c )
);
XORCY \blk00000001/blk00000066 (
.CI(\blk00000001/sig0000005b ),
.LI(\blk00000001/sig00000065 ),
.O(\blk00000001/sig00000078 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000065 (
.C(clk),
.D(\blk00000001/sig0000005d ),
.Q(\blk00000001/sig00000070 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000064 (
.C(clk),
.D(\blk00000001/sig00000071 ),
.Q(\blk00000001/sig00000067 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000063 (
.C(clk),
.D(\blk00000001/sig00000072 ),
.Q(\blk00000001/sig00000068 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000062 (
.C(clk),
.D(\blk00000001/sig00000073 ),
.Q(\blk00000001/sig00000069 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000061 (
.C(clk),
.D(\blk00000001/sig00000074 ),
.Q(\blk00000001/sig0000006a )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000060 (
.C(clk),
.D(\blk00000001/sig00000075 ),
.Q(\blk00000001/sig0000006b )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000005f (
.C(clk),
.D(\blk00000001/sig00000076 ),
.Q(\blk00000001/sig0000006c )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000005e (
.C(clk),
.D(\blk00000001/sig00000077 ),
.Q(\blk00000001/sig0000006d )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000005d (
.C(clk),
.D(\blk00000001/sig00000078 ),
.Q(\blk00000001/sig0000006e )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000005c (
.C(clk),
.D(\blk00000001/sig00000079 ),
.Q(\blk00000001/sig0000006f )
);
MUXCY \blk00000001/blk0000005b (
.CI(\blk00000001/sig00000036 ),
.DI(a[0]),
.S(\blk00000001/sig00000042 ),
.O(\blk00000001/sig00000039 )
);
XORCY \blk00000001/blk0000005a (
.CI(\blk00000001/sig00000036 ),
.LI(\blk00000001/sig00000042 ),
.O(\blk00000001/sig0000004c )
);
XORCY \blk00000001/blk00000059 (
.CI(\blk00000001/sig00000040 ),
.LI(\blk00000001/sig0000004a ),
.O(\blk00000001/sig00000054 )
);
MUXCY \blk00000001/blk00000058 (
.CI(\blk00000001/sig00000040 ),
.DI(a[8]),
.S(\blk00000001/sig0000004a ),
.O(\blk00000001/sig00000041 )
);
MUXCY \blk00000001/blk00000057 (
.CI(\blk00000001/sig00000039 ),
.DI(a[1]),
.S(\blk00000001/sig00000043 ),
.O(\blk00000001/sig0000003a )
);
XORCY \blk00000001/blk00000056 (
.CI(\blk00000001/sig00000039 ),
.LI(\blk00000001/sig00000043 ),
.O(\blk00000001/sig0000004d )
);
MUXCY \blk00000001/blk00000055 (
.CI(\blk00000001/sig0000003a ),
.DI(a[2]),
.S(\blk00000001/sig00000044 ),
.O(\blk00000001/sig0000003b )
);
XORCY \blk00000001/blk00000054 (
.CI(\blk00000001/sig0000003a ),
.LI(\blk00000001/sig00000044 ),
.O(\blk00000001/sig0000004e )
);
MUXCY \blk00000001/blk00000053 (
.CI(\blk00000001/sig0000003b ),
.DI(a[3]),
.S(\blk00000001/sig00000045 ),
.O(\blk00000001/sig0000003c )
);
XORCY \blk00000001/blk00000052 (
.CI(\blk00000001/sig0000003b ),
.LI(\blk00000001/sig00000045 ),
.O(\blk00000001/sig0000004f )
);
MUXCY \blk00000001/blk00000051 (
.CI(\blk00000001/sig0000003c ),
.DI(a[4]),
.S(\blk00000001/sig00000046 ),
.O(\blk00000001/sig0000003d )
);
XORCY \blk00000001/blk00000050 (
.CI(\blk00000001/sig0000003c ),
.LI(\blk00000001/sig00000046 ),
.O(\blk00000001/sig00000050 )
);
MUXCY \blk00000001/blk0000004f (
.CI(\blk00000001/sig0000003d ),
.DI(a[5]),
.S(\blk00000001/sig00000047 ),
.O(\blk00000001/sig0000003e )
);
XORCY \blk00000001/blk0000004e (
.CI(\blk00000001/sig0000003d ),
.LI(\blk00000001/sig00000047 ),
.O(\blk00000001/sig00000051 )
);
MUXCY \blk00000001/blk0000004d (
.CI(\blk00000001/sig0000003e ),
.DI(a[6]),
.S(\blk00000001/sig00000048 ),
.O(\blk00000001/sig0000003f )
);
XORCY \blk00000001/blk0000004c (
.CI(\blk00000001/sig0000003e ),
.LI(\blk00000001/sig00000048 ),
.O(\blk00000001/sig00000052 )
);
MUXCY \blk00000001/blk0000004b (
.CI(\blk00000001/sig0000003f ),
.DI(a[7]),
.S(\blk00000001/sig00000049 ),
.O(\blk00000001/sig00000040 )
);
XORCY \blk00000001/blk0000004a (
.CI(\blk00000001/sig0000003f ),
.LI(\blk00000001/sig00000049 ),
.O(\blk00000001/sig00000053 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000049 (
.C(clk),
.D(\blk00000001/sig00000041 ),
.Q(\blk00000001/sig0000004b )
);
MUXCY \blk00000001/blk00000048 (
.CI(\blk00000001/sig00000036 ),
.DI(a[18]),
.S(\blk00000001/sig00000082 ),
.O(\blk00000001/sig0000007a )
);
XORCY \blk00000001/blk00000047 (
.CI(\blk00000001/sig00000036 ),
.LI(\blk00000001/sig00000082 ),
.O(\blk00000001/sig0000008b )
);
XORCY \blk00000001/blk00000046 (
.CI(\blk00000001/sig00000081 ),
.LI(\blk00000001/sig0000008a ),
.O(\blk00000001/sig00000093 )
);
MUXCY \blk00000001/blk00000045 (
.CI(\blk00000001/sig0000007a ),
.DI(a[19]),
.S(\blk00000001/sig00000083 ),
.O(\blk00000001/sig0000007b )
);
XORCY \blk00000001/blk00000044 (
.CI(\blk00000001/sig0000007a ),
.LI(\blk00000001/sig00000083 ),
.O(\blk00000001/sig0000008c )
);
MUXCY \blk00000001/blk00000043 (
.CI(\blk00000001/sig0000007b ),
.DI(a[20]),
.S(\blk00000001/sig00000084 ),
.O(\blk00000001/sig0000007c )
);
XORCY \blk00000001/blk00000042 (
.CI(\blk00000001/sig0000007b ),
.LI(\blk00000001/sig00000084 ),
.O(\blk00000001/sig0000008d )
);
MUXCY \blk00000001/blk00000041 (
.CI(\blk00000001/sig0000007c ),
.DI(a[21]),
.S(\blk00000001/sig00000085 ),
.O(\blk00000001/sig0000007d )
);
XORCY \blk00000001/blk00000040 (
.CI(\blk00000001/sig0000007c ),
.LI(\blk00000001/sig00000085 ),
.O(\blk00000001/sig0000008e )
);
MUXCY \blk00000001/blk0000003f (
.CI(\blk00000001/sig0000007d ),
.DI(a[22]),
.S(\blk00000001/sig00000086 ),
.O(\blk00000001/sig0000007e )
);
XORCY \blk00000001/blk0000003e (
.CI(\blk00000001/sig0000007d ),
.LI(\blk00000001/sig00000086 ),
.O(\blk00000001/sig0000008f )
);
MUXCY \blk00000001/blk0000003d (
.CI(\blk00000001/sig0000007e ),
.DI(a[23]),
.S(\blk00000001/sig00000087 ),
.O(\blk00000001/sig0000007f )
);
XORCY \blk00000001/blk0000003c (
.CI(\blk00000001/sig0000007e ),
.LI(\blk00000001/sig00000087 ),
.O(\blk00000001/sig00000090 )
);
MUXCY \blk00000001/blk0000003b (
.CI(\blk00000001/sig0000007f ),
.DI(a[24]),
.S(\blk00000001/sig00000088 ),
.O(\blk00000001/sig00000080 )
);
XORCY \blk00000001/blk0000003a (
.CI(\blk00000001/sig0000007f ),
.LI(\blk00000001/sig00000088 ),
.O(\blk00000001/sig00000091 )
);
MUXCY \blk00000001/blk00000039 (
.CI(\blk00000001/sig00000080 ),
.DI(a[25]),
.S(\blk00000001/sig00000089 ),
.O(\blk00000001/sig00000081 )
);
XORCY \blk00000001/blk00000038 (
.CI(\blk00000001/sig00000080 ),
.LI(\blk00000001/sig00000089 ),
.O(\blk00000001/sig00000092 )
);
MUXCY \blk00000001/blk00000037 (
.CI(\blk00000001/sig000000b6 ),
.DI(\blk00000001/sig00000036 ),
.S(\blk00000001/sig000000fe ),
.O(\blk00000001/sig000000e5 )
);
XORCY \blk00000001/blk00000036 (
.CI(\blk00000001/sig000000b6 ),
.LI(\blk00000001/sig000000fe ),
.O(\blk00000001/sig000000ff )
);
XORCY \blk00000001/blk00000035 (
.CI(\blk00000001/sig000000ec ),
.LI(\blk00000001/sig000000fd ),
.O(\blk00000001/sig00000107 )
);
MUXCY \blk00000001/blk00000034 (
.CI(\blk00000001/sig000000ec ),
.DI(\blk00000001/sig00000036 ),
.S(\blk00000001/sig000000fd ),
.O(\NLW_blk00000001/blk00000034_O_UNCONNECTED )
);
MUXCY \blk00000001/blk00000033 (
.CI(\blk00000001/sig000000e5 ),
.DI(\blk00000001/sig00000036 ),
.S(\blk00000001/sig000000f6 ),
.O(\blk00000001/sig000000e6 )
);
XORCY \blk00000001/blk00000032 (
.CI(\blk00000001/sig000000e5 ),
.LI(\blk00000001/sig000000f6 ),
.O(\blk00000001/sig00000100 )
);
MUXCY \blk00000001/blk00000031 (
.CI(\blk00000001/sig000000e6 ),
.DI(\blk00000001/sig00000036 ),
.S(\blk00000001/sig000000f7 ),
.O(\blk00000001/sig000000e7 )
);
XORCY \blk00000001/blk00000030 (
.CI(\blk00000001/sig000000e6 ),
.LI(\blk00000001/sig000000f7 ),
.O(\blk00000001/sig00000101 )
);
MUXCY \blk00000001/blk0000002f (
.CI(\blk00000001/sig000000e7 ),
.DI(\blk00000001/sig00000036 ),
.S(\blk00000001/sig000000f8 ),
.O(\blk00000001/sig000000e8 )
);
XORCY \blk00000001/blk0000002e (
.CI(\blk00000001/sig000000e7 ),
.LI(\blk00000001/sig000000f8 ),
.O(\blk00000001/sig00000102 )
);
MUXCY \blk00000001/blk0000002d (
.CI(\blk00000001/sig000000e8 ),
.DI(\blk00000001/sig00000036 ),
.S(\blk00000001/sig000000f9 ),
.O(\blk00000001/sig000000e9 )
);
XORCY \blk00000001/blk0000002c (
.CI(\blk00000001/sig000000e8 ),
.LI(\blk00000001/sig000000f9 ),
.O(\blk00000001/sig00000103 )
);
MUXCY \blk00000001/blk0000002b (
.CI(\blk00000001/sig000000e9 ),
.DI(\blk00000001/sig00000036 ),
.S(\blk00000001/sig000000fa ),
.O(\blk00000001/sig000000ea )
);
XORCY \blk00000001/blk0000002a (
.CI(\blk00000001/sig000000e9 ),
.LI(\blk00000001/sig000000fa ),
.O(\blk00000001/sig00000104 )
);
MUXCY \blk00000001/blk00000029 (
.CI(\blk00000001/sig000000ea ),
.DI(\blk00000001/sig00000036 ),
.S(\blk00000001/sig000000fb ),
.O(\blk00000001/sig000000eb )
);
XORCY \blk00000001/blk00000028 (
.CI(\blk00000001/sig000000ea ),
.LI(\blk00000001/sig000000fb ),
.O(\blk00000001/sig00000105 )
);
MUXCY \blk00000001/blk00000027 (
.CI(\blk00000001/sig000000eb ),
.DI(\blk00000001/sig00000036 ),
.S(\blk00000001/sig000000fc ),
.O(\blk00000001/sig000000ec )
);
XORCY \blk00000001/blk00000026 (
.CI(\blk00000001/sig000000eb ),
.LI(\blk00000001/sig000000fc ),
.O(\blk00000001/sig00000106 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000025 (
.C(clk),
.D(\blk00000001/sig000000ff ),
.Q(s[18])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000024 (
.C(clk),
.D(\blk00000001/sig00000100 ),
.Q(s[19])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000023 (
.C(clk),
.D(\blk00000001/sig00000101 ),
.Q(s[20])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000022 (
.C(clk),
.D(\blk00000001/sig00000102 ),
.Q(s[21])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000021 (
.C(clk),
.D(\blk00000001/sig00000103 ),
.Q(s[22])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000020 (
.C(clk),
.D(\blk00000001/sig00000104 ),
.Q(s[23])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001f (
.C(clk),
.D(\blk00000001/sig00000105 ),
.Q(s[24])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001e (
.C(clk),
.D(\blk00000001/sig00000106 ),
.Q(s[25])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001d (
.C(clk),
.D(\blk00000001/sig00000107 ),
.Q(s[26])
);
MUXCY \blk00000001/blk0000001c (
.CI(\blk00000001/sig0000004b ),
.DI(\blk00000001/sig00000036 ),
.S(\blk00000001/sig000000ac ),
.O(\blk00000001/sig00000094 )
);
XORCY \blk00000001/blk0000001b (
.CI(\blk00000001/sig0000004b ),
.LI(\blk00000001/sig000000ac ),
.O(\blk00000001/sig000000ad )
);
XORCY \blk00000001/blk0000001a (
.CI(\blk00000001/sig0000009b ),
.LI(\blk00000001/sig000000ab ),
.O(\blk00000001/sig000000b5 )
);
MUXCY \blk00000001/blk00000019 (
.CI(\blk00000001/sig0000009b ),
.DI(\blk00000001/sig00000036 ),
.S(\blk00000001/sig000000ab ),
.O(\blk00000001/sig00000038 )
);
MUXCY \blk00000001/blk00000018 (
.CI(\blk00000001/sig00000094 ),
.DI(\blk00000001/sig00000036 ),
.S(\blk00000001/sig000000a4 ),
.O(\blk00000001/sig00000095 )
);
XORCY \blk00000001/blk00000017 (
.CI(\blk00000001/sig00000094 ),
.LI(\blk00000001/sig000000a4 ),
.O(\blk00000001/sig000000ae )
);
MUXCY \blk00000001/blk00000016 (
.CI(\blk00000001/sig00000095 ),
.DI(\blk00000001/sig00000036 ),
.S(\blk00000001/sig000000a5 ),
.O(\blk00000001/sig00000096 )
);
XORCY \blk00000001/blk00000015 (
.CI(\blk00000001/sig00000095 ),
.LI(\blk00000001/sig000000a5 ),
.O(\blk00000001/sig000000af )
);
MUXCY \blk00000001/blk00000014 (
.CI(\blk00000001/sig00000096 ),
.DI(\blk00000001/sig00000036 ),
.S(\blk00000001/sig000000a6 ),
.O(\blk00000001/sig00000097 )
);
XORCY \blk00000001/blk00000013 (
.CI(\blk00000001/sig00000096 ),
.LI(\blk00000001/sig000000a6 ),
.O(\blk00000001/sig000000b0 )
);
MUXCY \blk00000001/blk00000012 (
.CI(\blk00000001/sig00000097 ),
.DI(\blk00000001/sig00000036 ),
.S(\blk00000001/sig000000a7 ),
.O(\blk00000001/sig00000098 )
);
XORCY \blk00000001/blk00000011 (
.CI(\blk00000001/sig00000097 ),
.LI(\blk00000001/sig000000a7 ),
.O(\blk00000001/sig000000b1 )
);
MUXCY \blk00000001/blk00000010 (
.CI(\blk00000001/sig00000098 ),
.DI(\blk00000001/sig00000036 ),
.S(\blk00000001/sig000000a8 ),
.O(\blk00000001/sig00000099 )
);
XORCY \blk00000001/blk0000000f (
.CI(\blk00000001/sig00000098 ),
.LI(\blk00000001/sig000000a8 ),
.O(\blk00000001/sig000000b2 )
);
MUXCY \blk00000001/blk0000000e (
.CI(\blk00000001/sig00000099 ),
.DI(\blk00000001/sig00000036 ),
.S(\blk00000001/sig000000a9 ),
.O(\blk00000001/sig0000009a )
);
XORCY \blk00000001/blk0000000d (
.CI(\blk00000001/sig00000099 ),
.LI(\blk00000001/sig000000a9 ),
.O(\blk00000001/sig000000b3 )
);
MUXCY \blk00000001/blk0000000c (
.CI(\blk00000001/sig0000009a ),
.DI(\blk00000001/sig00000036 ),
.S(\blk00000001/sig000000aa ),
.O(\blk00000001/sig0000009b )
);
XORCY \blk00000001/blk0000000b (
.CI(\blk00000001/sig0000009a ),
.LI(\blk00000001/sig000000aa ),
.O(\blk00000001/sig000000b4 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000000a (
.C(clk),
.D(\blk00000001/sig000000ae ),
.Q(\blk00000001/sig0000009c )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000009 (
.C(clk),
.D(\blk00000001/sig000000af ),
.Q(\blk00000001/sig0000009d )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000008 (
.C(clk),
.D(\blk00000001/sig000000b0 ),
.Q(\blk00000001/sig0000009e )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000007 (
.C(clk),
.D(\blk00000001/sig000000b1 ),
.Q(\blk00000001/sig0000009f )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000006 (
.C(clk),
.D(\blk00000001/sig000000b2 ),
.Q(\blk00000001/sig000000a0 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000005 (
.C(clk),
.D(\blk00000001/sig000000b3 ),
.Q(\blk00000001/sig000000a1 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000004 (
.C(clk),
.D(\blk00000001/sig000000b4 ),
.Q(\blk00000001/sig000000a2 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000003 (
.C(clk),
.D(\blk00000001/sig000000b5 ),
.Q(\blk00000001/sig000000a3 )
);
GND \blk00000001/blk00000002 (
.G(\blk00000001/sig00000036 )
);
// synthesis translate_on
endmodule
// synthesis translate_off
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
// synthesis translate_on
|
// (C) 1992-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_arb2
#(
// Configuration
parameter string PIPELINE = "data_stall", // none|data|stall|data_stall|stall_data
parameter integer KEEP_LAST_GRANT = 1, // 0|1 - if one request can last multiple cycles (e.g. write burst), KEEP_LAST_GRANT must be 1
parameter integer NO_STALL_NETWORK = 0, // 0|1 - if one, remove the ability for arb to stall backward - must guarantee no collisions!
// Masters
parameter integer DATA_W = 32, // > 0
parameter integer BURSTCOUNT_W = 4, // > 0
parameter integer ADDRESS_W = 32, // > 0
parameter integer BYTEENA_W = DATA_W / 8, // > 0
parameter integer ID_W = 1 // > 0
)
(
// INPUTS
input logic clock,
input logic resetn,
// INTERFACES
acl_arb_intf m0_intf,
acl_arb_intf m1_intf,
acl_arb_intf mout_intf
);
/////////////////////////////////////////////
// ARCHITECTURE
/////////////////////////////////////////////
// mux_intf acts as an interface immediately after request arbitration
acl_arb_intf #(
.DATA_W( DATA_W ),
.BURSTCOUNT_W( BURSTCOUNT_W ),
.ADDRESS_W( ADDRESS_W ),
.BYTEENA_W( BYTEENA_W ),
.ID_W( ID_W )
)
mux_intf();
// Selector and request arbitration.
logic mux_sel;
assign mux_intf.req = mux_sel ? m1_intf.req : m0_intf.req;
generate
if( KEEP_LAST_GRANT == 1 )
begin
logic last_mux_sel_r;
always_ff @( posedge clock )
last_mux_sel_r <= mux_sel;
always_comb
// Maintain last grant.
if( last_mux_sel_r == 1'b0 && m0_intf.req.request )
mux_sel = 1'b0;
else if( last_mux_sel_r == 1'b1 && m1_intf.req.request )
mux_sel = 1'b1;
// Arbitrarily favor m0.
else
mux_sel = m0_intf.req.request ? 1'b0 : 1'b1;
end
else
begin
// Arbitrarily favor m0.
assign mux_sel = m0_intf.req.request ? 1'b0 : 1'b1;
end
endgenerate
// Stall signal for each upstream master.
generate
if( NO_STALL_NETWORK == 1 )
begin
assign m0_intf.stall = '0;
assign m1_intf.stall = '0;
end
else
begin
assign m0_intf.stall = ( mux_sel & m1_intf.req.request) | mux_intf.stall;
assign m1_intf.stall = (~mux_sel & m0_intf.req.request) | mux_intf.stall;
end
endgenerate
// What happens at the output of the arbitration block? Depends on the pipelining option...
// Each option is responsible for the following:
// 1. Connecting mout_intf.req: request output of the arbitration block
// 2. Connecting mux_intf.stall: upstream (to input masters) stall signal
generate
if( PIPELINE == "none" )
begin
// Purely combinational. Not a single register to be seen.
// Request for downstream blocks.
assign mout_intf.req = mux_intf.req;
// Stall signal from downstream blocks
assign mux_intf.stall = mout_intf.stall;
end
else if( PIPELINE == "data" )
begin
// Standard pipeline register at output. Latency of one cycle.
acl_arb_intf #(
.DATA_W( DATA_W ),
.BURSTCOUNT_W( BURSTCOUNT_W ),
.ADDRESS_W( ADDRESS_W ),
.BYTEENA_W( BYTEENA_W ),
.ID_W( ID_W )
)
pipe_intf();
acl_arb_pipeline_reg #(
.DATA_W( DATA_W ),
.BURSTCOUNT_W( BURSTCOUNT_W ),
.ADDRESS_W( ADDRESS_W ),
.BYTEENA_W( BYTEENA_W ),
.ID_W( ID_W )
)
pipe(
.clock( clock ),
.resetn( resetn ),
.in_intf( mux_intf ),
.out_intf( pipe_intf )
);
// Request for downstream blocks.
assign mout_intf.req = pipe_intf.req;
// Stall signal from downstream blocks.
assign pipe_intf.stall = mout_intf.stall;
end
else if( PIPELINE == "stall" )
begin
// Staging register at output. Min. latency of zero cycles, max. latency of one cycle.
acl_arb_intf #(
.DATA_W( DATA_W ),
.BURSTCOUNT_W( BURSTCOUNT_W ),
.ADDRESS_W( ADDRESS_W ),
.BYTEENA_W( BYTEENA_W ),
.ID_W( ID_W )
)
staging_intf();
acl_arb_staging_reg #(
.DATA_W( DATA_W ),
.BURSTCOUNT_W( BURSTCOUNT_W ),
.ADDRESS_W( ADDRESS_W ),
.BYTEENA_W( BYTEENA_W ),
.ID_W( ID_W )
)
staging(
.clock( clock ),
.resetn( resetn ),
.in_intf( mux_intf ),
.out_intf( staging_intf )
);
// Request for downstream blocks.
assign mout_intf.req = staging_intf.req;
// Stall signal from downstream blocks.
assign staging_intf.stall = mout_intf.stall;
end
else if( PIPELINE == "data_stall" )
begin
// Pipeline register followed by staging register at output. Min. latency
// of one cycle, max. latency of two cycles.
acl_arb_intf #(
.DATA_W( DATA_W ),
.BURSTCOUNT_W( BURSTCOUNT_W ),
.ADDRESS_W( ADDRESS_W ),
.BYTEENA_W( BYTEENA_W ),
.ID_W( ID_W )
)
pipe_intf(), staging_intf();
acl_arb_pipeline_reg #(
.DATA_W( DATA_W ),
.BURSTCOUNT_W( BURSTCOUNT_W ),
.ADDRESS_W( ADDRESS_W ),
.BYTEENA_W( BYTEENA_W ),
.ID_W( ID_W )
)
pipe(
.clock( clock ),
.resetn( resetn ),
.in_intf( mux_intf ),
.out_intf( pipe_intf )
);
acl_arb_staging_reg #(
.DATA_W( DATA_W ),
.BURSTCOUNT_W( BURSTCOUNT_W ),
.ADDRESS_W( ADDRESS_W ),
.BYTEENA_W( BYTEENA_W ),
.ID_W( ID_W )
)
staging(
.clock( clock ),
.resetn( resetn ),
.in_intf( pipe_intf ),
.out_intf( staging_intf )
);
// Request for downstream blocks.
assign mout_intf.req = staging_intf.req;
// Stall signal from downstream blocks.
assign staging_intf.stall = mout_intf.stall;
end
else if( PIPELINE == "stall_data" )
begin
// Staging register followed by pipeline register at output. Min. latency
// of one cycle, max. latency of two cycles.
acl_arb_intf #(
.DATA_W( DATA_W ),
.BURSTCOUNT_W( BURSTCOUNT_W ),
.ADDRESS_W( ADDRESS_W ),
.BYTEENA_W( BYTEENA_W ),
.ID_W( ID_W )
)
staging_intf(), pipe_intf();
acl_arb_staging_reg #(
.DATA_W( DATA_W ),
.BURSTCOUNT_W( BURSTCOUNT_W ),
.ADDRESS_W( ADDRESS_W ),
.BYTEENA_W( BYTEENA_W ),
.ID_W( ID_W )
)
staging(
.clock( clock ),
.resetn( resetn ),
.in_intf( mux_intf ),
.out_intf( staging_intf )
);
acl_arb_pipeline_reg #(
.DATA_W( DATA_W ),
.BURSTCOUNT_W( BURSTCOUNT_W ),
.ADDRESS_W( ADDRESS_W ),
.BYTEENA_W( BYTEENA_W ),
.ID_W( ID_W )
)
pipe(
.clock( clock ),
.resetn( resetn ),
.in_intf( staging_intf ),
.out_intf( pipe_intf )
);
// Request for downstream blocks.
assign mout_intf.req = pipe_intf.req;
// Stall signal from downstream blocks.
assign pipe_intf.stall = mout_intf.stall;
end
endgenerate
endmodule
module acl_arb_pipeline_reg #(
parameter integer DATA_W = 32, // > 0
parameter integer BURSTCOUNT_W = 4, // > 0
parameter integer ADDRESS_W = 32, // > 0
parameter integer BYTEENA_W = DATA_W / 8, // > 0
parameter integer ID_W = 1 // > 0
)
(
input clock,
input resetn,
acl_arb_intf in_intf,
acl_arb_intf out_intf
);
acl_arb_data #(
.DATA_W( DATA_W ),
.BURSTCOUNT_W( BURSTCOUNT_W ),
.ADDRESS_W( ADDRESS_W ),
.BYTEENA_W( BYTEENA_W ),
.ID_W( ID_W )
)
pipe_r();
// Pipeline register.
always @( posedge clock or negedge resetn ) begin
if( !resetn ) begin
pipe_r.req <= 'x; // only signals reset explicitly below need to be reset at all
pipe_r.req.request <= 1'b0;
pipe_r.req.read <= 1'b0;
pipe_r.req.write <= 1'b0;
end else if( !(out_intf.stall & pipe_r.req.request) & in_intf.req.enable) begin
pipe_r.req <= in_intf.req;
end
end
// Request for downstream blocks.
assign out_intf.req.enable = in_intf.req.enable ; //the enable must bypass the register
assign out_intf.req.request = pipe_r.req.request ;
assign out_intf.req.read = pipe_r.req.read ;
assign out_intf.req.write = pipe_r.req.write ;
assign out_intf.req.writedata = pipe_r.req.writedata ;
assign out_intf.req.burstcount = pipe_r.req.burstcount ;
assign out_intf.req.address = pipe_r.req.address ;
assign out_intf.req.byteenable = pipe_r.req.byteenable ;
assign out_intf.req.id = pipe_r.req.id ;
// Upstream stall signal.
assign in_intf.stall = out_intf.stall & pipe_r.req.request;
endmodule
module acl_arb_staging_reg #(
parameter integer DATA_W = 32, // > 0
parameter integer BURSTCOUNT_W = 4, // > 0
parameter integer ADDRESS_W = 32, // > 0
parameter integer BYTEENA_W = DATA_W / 8, // > 0
parameter integer ID_W = 1 // > 0
)
(
input clock,
input resetn,
acl_arb_intf in_intf,
acl_arb_intf out_intf
);
logic stall_r;
acl_arb_data #(
.DATA_W( DATA_W ),
.BURSTCOUNT_W( BURSTCOUNT_W ),
.ADDRESS_W( ADDRESS_W ),
.BYTEENA_W( BYTEENA_W ),
.ID_W( ID_W )
)
staging_r();
// Staging register.
always @( posedge clock or negedge resetn )
if( !resetn )
begin
staging_r.req <= 'x; // only signals reset explicitly below need to be reset at all
staging_r.req.request <= 1'b0;
staging_r.req.read <= 1'b0;
staging_r.req.write <= 1'b0;
end
else if( !stall_r )
staging_r.req <= in_intf.req;
// Stall register.
always @( posedge clock or negedge resetn )
if( !resetn )
stall_r <= 1'b0;
else
stall_r <= out_intf.stall & (stall_r | in_intf.req.request);
// Request for downstream blocks.
assign out_intf.req = stall_r ? staging_r.req : in_intf.req;
// Upstream stall signal.
assign in_intf.stall = stall_r;
endmodule
|
(** * Basics: Functional Programming in Coq *)
(*
[Admitted] is Coq's "escape hatch" that says accept this definition
without proof. We use it to mark the 'holes' in the development
that should be completed as part of your homework exercises. In
practice, [Admitted] is useful when you're incrementally developing
large proofs.
As of Coq 8.4 [admit] is in the standard library, but we include
it here for backwards compatibility.
*)
Definition admit {T: Type} : T. Admitted.
(* ###################################################################### *)
(** * Introduction *)
(** The functional programming style brings programming closer to
mathematics: If a procedure or method has no side effects, then
pretty much all you need to understand about it is how it maps
inputs to outputs -- that is, you can think of its behavior as
just computing a mathematical function. This is one reason for
the word "functional" in "functional programming." This direct
connection between programs and simple mathematical objects
supports both sound informal reasoning and formal proofs of
correctness.
The other sense in which functional programming is "functional" is
that it emphasizes the use of functions (or methods) as
_first-class_ values -- i.e., values that can be passed as
arguments to other functions, returned as results, stored in data
structures, etc. The recognition that functions can be treated as
data in this way enables a host of useful idioms, as we will see.
Other common features of functional languages include _algebraic
data types_ and _pattern matching_, which make it easy to construct
and manipulate rich data structures, and sophisticated
_polymorphic type systems_ that support abstraction and code
reuse. Coq shares all of these features.
*)
(* ###################################################################### *)
(** * Enumerated Types *)
(** One unusual aspect of Coq is that its set of built-in
features is _extremely_ small. For example, instead of providing
the usual palette of atomic data types (booleans, integers,
strings, etc.), Coq offers an extremely powerful mechanism for
defining new data types from scratch -- so powerful that all these
familiar types arise as instances.
Naturally, the Coq distribution comes with an extensive standard
library providing definitions of booleans, numbers, and many
common data structures like lists and hash tables. But there is
nothing magic or primitive about these library definitions: they
are ordinary user code.
To see how this works, let's start with a very simple example. *)
(* ###################################################################### *)
(** ** Days of the Week *)
(** The following declaration tells Coq that we are defining
a new set of data values -- a _type_. *)
Inductive day : Type :=
| monday : day
| tuesday : day
| wednesday : day
| thursday : day
| friday : day
| saturday : day
| sunday : day.
(** The type is called [day], and its members are [monday],
[tuesday], etc. The second through eighth lines of the definition
can be read "[monday] is a [day], [tuesday] is a [day], etc."
Having defined [day], we can write functions that operate on
days. *)
Definition next_weekday (d:day) : day :=
match d with
| monday => tuesday
| tuesday => wednesday
| wednesday => thursday
| thursday => friday
| friday => monday
| saturday => monday
| sunday => monday
end.
(** One thing to note is that the argument and return types of
this function are explicitly declared. Like most functional
programming languages, Coq can often work out these types even if
they are not given explicitly -- i.e., it performs some _type
inference_ -- but we'll always include them to make reading
easier. *)
(** Having defined a function, we should check that it works on
some examples. There are actually three different ways to do this
in Coq. First, we can use the command [Eval compute] to evaluate a
compound expression involving [next_weekday]. *)
Eval compute in (next_weekday friday).
(* ==> monday : day *)
Eval compute in (next_weekday (next_weekday saturday)).
(* ==> tuesday : day *)
(** If you have a computer handy, now would be an excellent
moment to fire up the Coq interpreter under your favorite IDE --
either CoqIde or Proof General -- and try this for yourself. Load
this file ([Basics.v]) from the book's accompanying Coq sources,
find the above example, submit it to Coq, and observe the
result. *)
(** The keyword [compute] tells Coq precisely how to
evaluate the expression we give it. For the moment, [compute] is
the only one we'll need; later on we'll see some alternatives that
are sometimes useful. *)
(** Second, we can record what we _expect_ the result to be in
the form of a Coq example: *)
Example test_next_weekday:
(next_weekday (next_weekday saturday)) = tuesday.
(** This declaration does two things: it makes an
assertion (that the second weekday after [saturday] is [tuesday]),
and it gives the assertion a name that can be used to refer to it
later. *)
(** Having made the assertion, we can also ask Coq to verify it,
like this: *)
Proof. simpl. reflexivity. Qed.
(** The details are not important for now (we'll come back to
them in a bit), but essentially this can be read as "The assertion
we've just made can be proved by observing that both sides of the
equality evaluate to the same thing, after some simplification." *)
(** Third, we can ask Coq to "extract," from a [Definition], a
program in some other, more conventional, programming
language (OCaml, Scheme, or Haskell) with a high-performance
compiler. This facility is very interesting, since it gives us a
way to construct _fully certified_ programs in mainstream
languages. Indeed, this is one of the main uses for which Coq was
developed. We'll come back to this topic in later chapters.
More information can also be found in the Coq'Art book by Bertot
and Casteran, as well as the Coq reference manual. *)
(* ###################################################################### *)
(** ** Booleans *)
(** In a similar way, we can define the type [bool] of booleans,
with members [true] and [false]. *)
Inductive bool : Type :=
| true : bool
| false : bool.
(** Although we are rolling our own booleans here for the sake
of building up everything from scratch, Coq does, of course,
provide a default implementation of the booleans in its standard
library, together with a multitude of useful functions and
lemmas. (Take a look at [Coq.Init.Datatypes] in the Coq library
documentation if you're interested.) Whenever possible, we'll
name our own definitions and theorems so that they exactly
coincide with the ones in the standard library. *)
(** Functions over booleans can be defined in the same way as
above: *)
Definition negb (b:bool) : bool :=
match b with
| true => false
| false => true
end.
Definition andb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => b2
| false => false
end.
Definition orb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => true
| false => b2
end.
(** The last two illustrate the syntax for multi-argument
function definitions. *)
(** The following four "unit tests" constitute a complete
specification -- a truth table -- for the [orb] function: *)
Example test_orb1: (orb true false) = true.
Proof. reflexivity. Qed.
Example test_orb2: (orb false false) = false.
Proof. reflexivity. Qed.
Example test_orb3: (orb false true) = true.
Proof. reflexivity. Qed.
Example test_orb4: (orb true true) = true.
Proof. reflexivity. Qed.
(** (Note that we've dropped the [simpl] in the proofs. It's not
actually needed because [reflexivity] will automatically perform
simplification.) *)
(** _A note on notation_: We use square brackets to delimit
fragments of Coq code in comments in .v files; this convention,
also used by the [coqdoc] documentation tool, keeps them visually
separate from the surrounding text. In the html version of the
files, these pieces of text appear in a [different font]. *)
(** The values [Admitted] and [admit] can be used to fill
a hole in an incomplete definition or proof. We'll use them in the
following exercises. In general, your job in the exercises is
to replace [admit] or [Admitted] with real definitions or proofs. *)
(** **** Exercise: 1 star (nandb) *)
(** Complete the definition of the following function, then make
sure that the [Example] assertions below can each be verified by
Coq. *)
(** This function should return [true] if either or both of
its inputs are [false]. *)
Definition nandb (b1:bool) (b2:bool) : bool :=
(* FILL IN HERE *) admit.
(** Remove "[Admitted.]" and fill in each proof with
"[Proof. reflexivity. Qed.]" *)
Example test_nandb1: (nandb true false) = true.
(* FILL IN HERE *) Admitted.
Example test_nandb2: (nandb false false) = true.
(* FILL IN HERE *) Admitted.
Example test_nandb3: (nandb false true) = true.
(* FILL IN HERE *) Admitted.
Example test_nandb4: (nandb true true) = false.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star (andb3) *)
(** Do the same for the [andb3] function below. This function should
return [true] when all of its inputs are [true], and [false]
otherwise. *)
Definition andb3 (b1:bool) (b2:bool) (b3:bool) : bool :=
(* FILL IN HERE *) admit.
Example test_andb31: (andb3 true true true) = true.
(* FILL IN HERE *) Admitted.
Example test_andb32: (andb3 false true true) = false.
(* FILL IN HERE *) Admitted.
Example test_andb33: (andb3 true false true) = false.
(* FILL IN HERE *) Admitted.
Example test_andb34: (andb3 true true false) = false.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################################### *)
(** ** Function Types *)
(** The [Check] command causes Coq to print the type of an
expression. For example, the type of [negb true] is [bool]. *)
Check true.
(* ===> true : bool *)
Check (negb true).
(* ===> negb true : bool *)
(** Functions like [negb] itself are also data values, just like
[true] and [false]. Their types are called _function types_, and
they are written with arrows. *)
Check negb.
(* ===> negb : bool -> bool *)
(** The type of [negb], written [bool -> bool] and pronounced
"[bool] arrow [bool]," can be read, "Given an input of type
[bool], this function produces an output of type [bool]."
Similarly, the type of [andb], written [bool -> bool -> bool], can
be read, "Given two inputs, both of type [bool], this function
produces an output of type [bool]." *)
(* ###################################################################### *)
(** ** Numbers *)
(** _Technical digression_: Coq provides a fairly sophisticated
_module system_, to aid in organizing large developments. In this
course we won't need most of its features, but one is useful: If
we enclose a collection of declarations between [Module X] and
[End X] markers, then, in the remainder of the file after the
[End], these definitions will be referred to by names like [X.foo]
instead of just [foo]. Here, we use this feature to introduce the
definition of the type [nat] in an inner module so that it does
not shadow the one from the standard library. *)
Module Playground1.
(** The types we have defined so far are examples of "enumerated
types": their definitions explicitly enumerate a finite set of
elements. A more interesting way of defining a type is to give a
collection of "inductive rules" describing its elements. For
example, we can define the natural numbers as follows: *)
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
(** The clauses of this definition can be read:
- [O] is a natural number (note that this is the letter "[O]," not
the numeral "[0]").
- [S] is a "constructor" that takes a natural number and yields
another one -- that is, if [n] is a natural number, then [S n]
is too.
Let's look at this in a little more detail.
Every inductively defined set ([day], [nat], [bool], etc.) is
actually a set of _expressions_. The definition of [nat] says how
expressions in the set [nat] can be constructed:
- the expression [O] belongs to the set [nat];
- if [n] is an expression belonging to the set [nat], then [S n]
is also an expression belonging to the set [nat]; and
- expressions formed in these two ways are the only ones belonging
to the set [nat].
The same rules apply for our definitions of [day] and [bool]. The
annotations we used for their constructors are analogous to the
one for the [O] constructor, and indicate that each of those
constructors doesn't take any arguments. *)
(** These three conditions are the precise force of the
[Inductive] declaration. They imply that the expression [O], the
expression [S O], the expression [S (S O)], the expression
[S (S (S O))], and so on all belong to the set [nat], while other
expressions like [true], [andb true false], and [S (S false)] do
not.
We can write simple functions that pattern match on natural
numbers just as we did above -- for example, the predecessor
function: *)
Definition pred (n : nat) : nat :=
match n with
| O => O
| S n' => n'
end.
(** The second branch can be read: "if [n] has the form [S n']
for some [n'], then return [n']." *)
End Playground1.
Definition minustwo (n : nat) : nat :=
match n with
| O => O
| S O => O
| S (S n') => n'
end.
(** Because natural numbers are such a pervasive form of data,
Coq provides a tiny bit of built-in magic for parsing and printing
them: ordinary arabic numerals can be used as an alternative to
the "unary" notation defined by the constructors [S] and [O]. Coq
prints numbers in arabic form by default: *)
Check (S (S (S (S O)))).
Eval compute in (minustwo 4).
(** The constructor [S] has the type [nat -> nat], just like the
functions [minustwo] and [pred]: *)
Check S.
Check pred.
Check minustwo.
(** These are all things that can be applied to a number to yield a
number. However, there is a fundamental difference: functions
like [pred] and [minustwo] come with _computation rules_ -- e.g.,
the definition of [pred] says that [pred 2] can be simplified to
[1] -- while the definition of [S] has no such behavior attached.
Although it is like a function in the sense that it can be applied
to an argument, it does not _do_ anything at all! *)
(** For most function definitions over numbers, pure pattern
matching is not enough: we also need recursion. For example, to
check that a number [n] is even, we may need to recursively check
whether [n-2] is even. To write such functions, we use the
keyword [Fixpoint]. *)
Fixpoint evenb (n:nat) : bool :=
match n with
| O => true
| S O => false
| S (S n') => evenb n'
end.
(** We can define [oddb] by a similar [Fixpoint] declaration, but here
is a simpler definition that will be a bit easier to work with: *)
Definition oddb (n:nat) : bool := negb (evenb n).
Example test_oddb1: (oddb (S O)) = true.
Proof. reflexivity. Qed.
Example test_oddb2: (oddb (S (S (S (S O))))) = false.
Proof. reflexivity. Qed.
(** Naturally, we can also define multi-argument functions by
recursion. (Once again, we use a module to avoid polluting the
namespace.) *)
Module Playground2.
Fixpoint plus (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus n' m)
end.
(** Adding three to two now gives us five, as we'd expect. *)
Eval compute in (plus (S (S (S O))) (S (S O))).
(** The simplification that Coq performs to reach this conclusion can
be visualized as follows: *)
(* [plus (S (S (S O))) (S (S O))]
==> [S (plus (S (S O)) (S (S O)))] by the second clause of the [match]
==> [S (S (plus (S O) (S (S O))))] by the second clause of the [match]
==> [S (S (S (plus O (S (S O)))))] by the second clause of the [match]
==> [S (S (S (S (S O))))] by the first clause of the [match]
*)
(** As a notational convenience, if two or more arguments have
the same type, they can be written together. In the following
definition, [(n m : nat)] means just the same as if we had written
[(n : nat) (m : nat)]. *)
Fixpoint mult (n m : nat) : nat :=
match n with
| O => O
| S n' => plus m (mult n' m)
end.
Example test_mult1: (mult 3 3) = 9.
Proof. reflexivity. Qed.
(** You can match two expressions at once by putting a comma
between them: *)
Fixpoint minus (n m:nat) : nat :=
match n, m with
| O , _ => O
| S _ , O => n
| S n', S m' => minus n' m'
end.
(** The _ in the first line is a _wildcard pattern_. Writing _ in a
pattern is the same as writing some variable that doesn't get used
on the right-hand side. This avoids the need to invent a bogus
variable name. *)
End Playground2.
Fixpoint exp (base power : nat) : nat :=
match power with
| O => S O
| S p => mult base (exp base p)
end.
(** **** Exercise: 1 star (factorial) *)
(** Recall the standard factorial function:
<<
factorial(0) = 1
factorial(n) = n * factorial(n-1) (if n>0)
>>
Translate this into Coq. *)
Fixpoint factorial (n:nat) : nat :=
(* FILL IN HERE *) admit.
Example test_factorial1: (factorial 3) = 6.
(* FILL IN HERE *) Admitted.
Example test_factorial2: (factorial 5) = (mult 10 12).
(* FILL IN HERE *) Admitted.
(** [] *)
(** We can make numerical expressions a little easier to read and
write by introducing "notations" for addition, multiplication, and
subtraction. *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x - y" := (minus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
Check ((0 + 1) + 1).
(** (The [level], [associativity], and [nat_scope] annotations
control how these notations are treated by Coq's parser. The
details are not important, but interested readers can refer to the
"More on Notation" subsection in the "Optional Material" section at
the end of this chapter.) *)
(** Note that these do not change the definitions we've already
made: they are simply instructions to the Coq parser to accept [x
+ y] in place of [plus x y] and, conversely, to the Coq
pretty-printer to display [plus x y] as [x + y]. *)
(** When we say that Coq comes with nothing built-in, we really
mean it: even equality testing for numbers is a user-defined
operation! *)
(** The [beq_nat] function tests [nat]ural numbers for [eq]uality,
yielding a [b]oolean. Note the use of nested [match]es (we could
also have used a simultaneous match, as we did in [minus].) *)
Fixpoint beq_nat (n m : nat) : bool :=
match n with
| O => match m with
| O => true
| S m' => false
end
| S n' => match m with
| O => false
| S m' => beq_nat n' m'
end
end.
(** Similarly, the [ble_nat] function tests [nat]ural numbers for
[l]ess-or-[e]qual, yielding a [b]oolean. *)
Fixpoint ble_nat (n m : nat) : bool :=
match n with
| O => true
| S n' =>
match m with
| O => false
| S m' => ble_nat n' m'
end
end.
Example test_ble_nat1: (ble_nat 2 2) = true.
Proof. reflexivity. Qed.
Example test_ble_nat2: (ble_nat 2 4) = true.
Proof. reflexivity. Qed.
Example test_ble_nat3: (ble_nat 4 2) = false.
Proof. reflexivity. Qed.
(** **** Exercise: 2 stars (blt_nat) *)
(** The [blt_nat] function tests [nat]ural numbers for [l]ess-[t]han,
yielding a [b]oolean. Instead of making up a new [Fixpoint] for
this one, define it in terms of a previously defined function.
Note: If you have trouble with the [simpl] tactic, try using
[compute], which is like [simpl] on steroids. However, there is a
simple, elegant solution for which [simpl] suffices. *)
Definition blt_nat (n m : nat) : bool :=
(* FILL IN HERE *) admit.
Example test_blt_nat1: (blt_nat 2 2) = false.
(* FILL IN HERE *) Admitted.
Example test_blt_nat2: (blt_nat 2 4) = true.
(* FILL IN HERE *) Admitted.
Example test_blt_nat3: (blt_nat 4 2) = false.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################################### *)
(** * Proof by Simplification *)
(** Now that we've defined a few datatypes and functions, let's
turn to the question of how to state and prove properties of their
behavior. Actually, in a sense, we've already started doing this:
each [Example] in the previous sections makes a precise claim
about the behavior of some function on some particular inputs.
The proofs of these claims were always the same: use [reflexivity]
to check that both sides of the [=] simplify to identical values.
(By the way, it will be useful later to know that
[reflexivity] actually does somewhat more simplification than [simpl]
does -- for example, it tries "unfolding" defined terms, replacing them with
their right-hand sides. The reason for this difference is that,
when reflexivity succeeds, the whole goal is finished and we don't
need to look at whatever expanded expressions [reflexivity] has
found; by contrast, [simpl] is used in situations where we may
have to read and understand the new goal, so we would not want it
blindly expanding definitions.)
The same sort of "proof by simplification" can be used to prove
more interesting properties as well. For example, the fact that
[0] is a "neutral element" for [+] on the left can be proved
just by observing that [0 + n] reduces to [n] no matter what
[n] is, a fact that can be read directly off the definition of [plus].*)
Theorem plus_O_n : forall n : nat, 0 + n = n.
Proof.
intros n. reflexivity. Qed.
(** (_Note_: You may notice that the above statement looks
different in the original source file and the final html output. In Coq
files, we write the [forall] universal quantifier using the
"_forall_" reserved identifier. This gets printed as an
upside-down "A", the familiar symbol used in logic.) *)
(** The form of this theorem and proof are almost exactly the
same as the examples above; there are just a few differences.
First, we've used the keyword [Theorem] instead of
[Example]. Indeed, the difference is purely a matter of
style; the keywords [Example] and [Theorem] (and a few others,
including [Lemma], [Fact], and [Remark]) mean exactly the same
thing to Coq.
Secondly, we've added the quantifier [forall n:nat], so that our
theorem talks about _all_ natural numbers [n]. In order to prove
theorems of this form, we need to to be able to reason by
_assuming_ the existence of an arbitrary natural number [n]. This
is achieved in the proof by [intros n], which moves the quantifier
from the goal to a "context" of current assumptions. In effect, we
start the proof by saying "OK, suppose [n] is some arbitrary number."
The keywords [intros], [simpl], and [reflexivity] are examples of
_tactics_. A tactic is a command that is used between [Proof] and
[Qed] to tell Coq how it should check the correctness of some
claim we are making. We will see several more tactics in the rest
of this lecture, and yet more in future lectures. *)
(** Step through these proofs in Coq and notice how the goal and
context change. *)
Theorem plus_1_l : forall n:nat, 1 + n = S n.
Proof.
intros n. reflexivity. Qed.
Theorem mult_0_l : forall n:nat, 0 * n = 0.
Proof.
intros n. reflexivity. Qed.
(** The [_l] suffix in the names of these theorems is
pronounced "on the left." *)
(* ###################################################################### *)
(** * Proof by Rewriting *)
(** Here is a slightly more interesting theorem: *)
Theorem plus_id_example : forall n m:nat,
n = m ->
n + n = m + m.
(** Instead of making a completely universal claim about all numbers
[n] and [m], this theorem talks about a more specialized property
that only holds when [n = m]. The arrow symbol is pronounced
"implies."
As before, we need to be able to reason by assuming the existence
of some numbers [n] and [m]. We also need to assume the hypothesis
[n = m]. The [intros] tactic will serve to move all three of these
from the goal into assumptions in the current context.
Since [n] and [m] are arbitrary numbers, we can't just use
simplification to prove this theorem. Instead, we prove it by
observing that, if we are assuming [n = m], then we can replace
[n] with [m] in the goal statement and obtain an equality with the
same expression on both sides. The tactic that tells Coq to
perform this replacement is called [rewrite]. *)
Proof.
intros n m. (* move both quantifiers into the context *)
intros H. (* move the hypothesis into the context *)
rewrite -> H. (* Rewrite the goal using the hypothesis *)
reflexivity. Qed.
(** The first line of the proof moves the universally quantified
variables [n] and [m] into the context. The second moves the
hypothesis [n = m] into the context and gives it the (arbitrary)
name [H]. The third tells Coq to rewrite the current goal ([n + n
= m + m]) by replacing the left side of the equality hypothesis
[H] with the right side.
(The arrow symbol in the [rewrite] has nothing to do with
implication: it tells Coq to apply the rewrite from left to right.
To rewrite from right to left, you can use [rewrite <-]. Try
making this change in the above proof and see what difference it
makes in Coq's behavior.) *)
(** **** Exercise: 1 star (plus_id_exercise) *)
(** Remove "[Admitted.]" and fill in the proof. *)
Theorem plus_id_exercise : forall n m o : nat,
n = m -> m = o -> n + m = m + o.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** As we've seen in earlier examples, the [Admitted] command
tells Coq that we want to skip trying to prove this theorem and
just accept it as a given. This can be useful for developing
longer proofs, since we can state subsidiary facts that we believe
will be useful for making some larger argument, use [Admitted] to
accept them on faith for the moment, and continue thinking about
the larger argument until we are sure it makes sense; then we can
go back and fill in the proofs we skipped. Be careful, though:
every time you say [Admitted] (or [admit]) you are leaving a door
open for total nonsense to enter Coq's nice, rigorous, formally
checked world! *)
(** We can also use the [rewrite] tactic with a previously proved
theorem instead of a hypothesis from the context. *)
Theorem mult_0_plus : forall n m : nat,
(0 + n) * m = n * m.
Proof.
intros n m.
rewrite -> plus_O_n.
reflexivity. Qed.
(** **** Exercise: 2 stars (mult_S_1) *)
Theorem mult_S_1 : forall n m : nat,
m = S n ->
m * (1 + n) = m * m.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################################### *)
(** * Proof by Case Analysis *)
(** Of course, not everything can be proved by simple
calculation: In general, unknown, hypothetical values (arbitrary
numbers, booleans, lists, etc.) can block the calculation.
For example, if we try to prove the following fact using the
[simpl] tactic as above, we get stuck. *)
Theorem plus_1_neq_0_firsttry : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n.
simpl. (* does nothing! *)
Abort.
(** The reason for this is that the definitions of both
[beq_nat] and [+] begin by performing a [match] on their first
argument. But here, the first argument to [+] is the unknown
number [n] and the argument to [beq_nat] is the compound
expression [n + 1]; neither can be simplified.
What we need is to be able to consider the possible forms of [n]
separately. If [n] is [O], then we can calculate the final result
of [beq_nat (n + 1) 0] and check that it is, indeed, [false].
And if [n = S n'] for some [n'], then, although we don't know
exactly what number [n + 1] yields, we can calculate that, at
least, it will begin with one [S], and this is enough to calculate
that, again, [beq_nat (n + 1) 0] will yield [false].
The tactic that tells Coq to consider, separately, the cases where
[n = O] and where [n = S n'] is called [destruct]. *)
Theorem plus_1_neq_0 : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n. destruct n as [| n'].
reflexivity.
reflexivity. Qed.
(** The [destruct] generates _two_ subgoals, which we must then
prove, separately, in order to get Coq to accept the theorem as
proved. (No special command is needed for moving from one subgoal
to the other. When the first subgoal has been proved, it just
disappears and we are left with the other "in focus.") In this
proof, each of the subgoals is easily proved by a single use of
[reflexivity].
The annotation "[as [| n']]" is called an _intro pattern_. It
tells Coq what variable names to introduce in each subgoal. In
general, what goes between the square brackets is a _list_ of
lists of names, separated by [|]. Here, the first component is
empty, since the [O] constructor is nullary (it doesn't carry any
data). The second component gives a single name, [n'], since [S]
is a unary constructor.
The [destruct] tactic can be used with any inductively defined
datatype. For example, we use it here to prove that boolean
negation is involutive -- i.e., that negation is its own
inverse. *)
Theorem negb_involutive : forall b : bool,
negb (negb b) = b.
Proof.
intros b. destruct b.
reflexivity.
reflexivity. Qed.
(** Note that the [destruct] here has no [as] clause because
none of the subcases of the [destruct] need to bind any variables,
so there is no need to specify any names. (We could also have
written [as [|]], or [as []].) In fact, we can omit the [as]
clause from _any_ [destruct] and Coq will fill in variable names
automatically. Although this is convenient, it is arguably bad
style, since Coq often makes confusing choices of names when left
to its own devices. *)
(** **** Exercise: 1 star (zero_nbeq_plus_1) *)
Theorem zero_nbeq_plus_1 : forall n : nat,
beq_nat 0 (n + 1) = false.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################################### *)
(** * More Exercises *)
(** **** Exercise: 2 stars (boolean functions) *)
(** Use the tactics you have learned so far to prove the following
theorem about boolean functions. *)
Theorem identity_fn_applied_twice :
forall (f : bool -> bool),
(forall (x : bool), f x = x) ->
forall (b : bool), f (f b) = b.
Proof.
(* FILL IN HERE *) Admitted.
(** Now state and prove a theorem [negation_fn_applied_twice] similar
to the previous one but where the second hypothesis says that the
function [f] has the property that [f x = negb x].*)
(* FILL IN HERE *)
(** **** Exercise: 2 stars (andb_eq_orb) *)
(** Prove the following theorem. (You may want to first prove a
subsidiary lemma or two. Alternatively, remember that you do
not have to introduce all hypotheses at the same time.) *)
Theorem andb_eq_orb :
forall (b c : bool),
(andb b c = orb b c) ->
b = c.
Proof.
(* FILL IN HERE *) Admitted.
(** **** Exercise: 3 stars (binary) *)
(** Consider a different, more efficient representation of natural
numbers using a binary rather than unary system. That is, instead
of saying that each natural number is either zero or the successor
of a natural number, we can say that each binary number is either
- zero,
- twice a binary number, or
- one more than twice a binary number.
(a) First, write an inductive definition of the type [bin]
corresponding to this description of binary numbers.
(Hint: Recall that the definition of [nat] from class,
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
says nothing about what [O] and [S] "mean." It just says "[O] is
in the set called [nat], and if [n] is in the set then so is [S
n]." The interpretation of [O] as zero and [S] as successor/plus
one comes from the way that we _use_ [nat] values, by writing
functions to do things with them, proving things about them, and
so on. Your definition of [bin] should be correspondingly simple;
it is the functions you will write next that will give it
mathematical meaning.)
(b) Next, write an increment function for binary numbers, and a
function to convert binary numbers to unary numbers.
(c) Write some unit tests for your increment and binary-to-unary
functions. Notice that incrementing a binary number and
then converting it to unary should yield the same result as first
converting it to unary and then incrementing.
*)
(* FILL IN HERE *)
(** [] *)
(* ###################################################################### *)
(** * Optional Material *)
(** ** More on Notation *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
(** For each notation-symbol in Coq we can specify its _precedence level_
and its _associativity_. The precedence level n can be specified by the
keywords [at level n] and it is helpful to disambiguate
expressions containing different symbols. The associativity is helpful
to disambiguate expressions containing more occurrences of the same
symbol. For example, the parameters specified above for [+] and [*]
say that the expression [1+2*3*4] is a shorthand for the expression
[(1+((2*3)*4))]. Coq uses precedence levels from 0 to 100, and
_left_, _right_, or _no_ associativity.
Each notation-symbol in Coq is also active in a _notation scope_.
Coq tries to guess what scope you mean, so when you write [S(O*O)]
it guesses [nat_scope], but when you write the cartesian
product (tuple) type [bool*bool] it guesses [type_scope].
Occasionally you have to help it out with percent-notation by
writing [(x*y)%nat], and sometimes in Coq's feedback to you it
will use [%nat] to indicate what scope a notation is in.
Notation scopes also apply to numeral notation (3,4,5, etc.), so you
may sometimes see [0%nat] which means [O], or [0%Z] which means the
Integer zero.
*)
(** ** [Fixpoint]s and Structural Recursion *)
Fixpoint plus' (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus' n' m)
end.
(** When Coq checks this definition, it notes that [plus'] is
"decreasing on 1st argument." What this means is that we are
performing a _structural recursion_ over the argument [n] -- i.e.,
that we make recursive calls only on strictly smaller values of
[n]. This implies that all calls to [plus'] will eventually
terminate. Coq demands that some argument of _every_ [Fixpoint]
definition is "decreasing".
This requirement is a fundamental feature of Coq's design: In
particular, it guarantees that every function that can be defined
in Coq will terminate on all inputs. However, because Coq's
"decreasing analysis" is not very sophisticated, it is sometimes
necessary to write functions in slightly unnatural ways. *)
(** **** Exercise: 2 stars, optional (decreasing) *)
(** To get a concrete sense of this, find a way to write a sensible
[Fixpoint] definition (of a simple function on numbers, say) that
_does_ terminate on all inputs, but that Coq will _not_ accept
because of this restriction. *)
(* FILL IN HERE *)
(** [] *)
(* $Date: 2013-12-03 07:45:41 -0500 (Tue, 03 Dec 2013) $ *)
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 06/30/2009
This block is used to communicate information back and forth between the SGDMA
and the host. When the response port is not set to streaming then this block
will be used to generate interrupts for the host. The address span of this block
differs depending on whether the enhanced features are enabled. The enhanced
features enables sequence number readback capabilties. The address map is as follows:
Enhanced features off:
Bytes Access Type Description
----- ----------- -----------
0-3 R Status(1)
4-7 R/W Control(2)
8-12 R Descriptor Watermark (write watermark[15:0],read watermark [15:0])
13-15 R Response Watermark
16-31 N/A <Reserved>
Enhanced features on:
Bytes Access Type Description
----- ----------- -----------
0-3 R Status(1)
4-7 R/W Control(2)
8-12 R Descriptor Watermark (write watermark[15:0],read watermark [15:0])
13-15 R Response Watermark
16-20 R Sequence Number (write sequence[15:0],read sequence[15:0])
21-31 N/A <Reserved>
(1) Writing to the interrupt bit of the status register clears the interrupt bit (when applicable)
(2) Writing to the software reset bit will clear the entire register (as well as all the registers for the entire SGDMA)
Status Register:
Bits Description
---- -----------
0 Busy
1 Descriptor Buffer Empty
2 Descriptor Buffer Full
3 Response Buffer Empty
4 Response Buffer Full
5 Stop State
6 Reset State
7 Stopped on Error
8 Stopped on Early Termination
9 IRQ
10-15 <Reserved>
15-31 Done count (JSF: Added 06/13/2011)
Control Register:
Bits Description
---- -----------
0 Stop (will also be set if a stop on error/early termination condition occurs)
1 Software Reset
2 Stop on Error
3 Stop on Early Termination
4 Global Interrupt Enable Mask
5 Stop descriptors (stops the dispatcher from issuing more read/write commands)
6-31 <Reserved>
Author: JCJB
Date: 08/18/2010
1.0 - Initial release
1.1 - Removed delayed reset, added set and hold sw_reset
1.2 - Updated the sw_reset register to be set when control[1] is set instead of one cycle after.
This will prevent the read or write masters from starting back up when reset while in the stop state.
1.3 - Added the stop dispatcher bit (5) to the control register
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module csr_block (
clk,
reset,
csr_writedata,
csr_write,
csr_byteenable,
csr_readdata,
csr_read,
csr_address,
csr_irq,
done_strobe,
busy,
descriptor_buffer_empty,
descriptor_buffer_full,
stop_state,
stopped_on_error,
stopped_on_early_termination,
reset_stalled,
stop,
sw_reset,
stop_on_error,
stop_on_early_termination,
stop_descriptors,
sequence_number,
descriptor_watermark,
response_watermark,
response_buffer_empty,
response_buffer_full,
transfer_complete_IRQ_mask,
error_IRQ_mask,
early_termination_IRQ_mask,
error,
early_termination
);
parameter ADDRESS_WIDTH = 3;
localparam CONTROL_REGISTER_ADDRESS = 3'b001;
input clk;
input reset;
input [31:0] csr_writedata;
input csr_write;
input [3:0] csr_byteenable;
output wire [31:0] csr_readdata;
input csr_read;
input [ADDRESS_WIDTH-1:0] csr_address;
output wire csr_irq;
input done_strobe;
input busy;
input descriptor_buffer_empty;
input descriptor_buffer_full;
input stop_state; // when the DMA runs into some error condition and you have enabled the stop on error (or when the stop control bit is written to)
input reset_stalled; // the read or write master could be in the middle of a transfer/burst so it might take a while to flush the buffers
output wire stop;
output reg stopped_on_error;
output reg stopped_on_early_termination;
output reg sw_reset;
output wire stop_on_error;
output wire stop_on_early_termination;
output wire stop_descriptors;
input [31:0] sequence_number;
input [31:0] descriptor_watermark;
input [15:0] response_watermark;
input response_buffer_empty;
input response_buffer_full;
input transfer_complete_IRQ_mask;
input [7:0] error_IRQ_mask;
input early_termination_IRQ_mask;
input [7:0] error;
input early_termination;
/* Internal wires and registers */
wire [31:0] status;
reg [31:0] control;
reg [31:0] readdata;
reg [31:0] readdata_d1;
reg irq; // writing to the status register clears the irq bit
wire set_irq;
wire clear_irq;
reg [15:0] irq_count; // writing to bit 0 clears the counter
wire clear_irq_count;
wire incr_irq_count;
wire set_stopped_on_error;
wire set_stopped_on_early_termination;
wire set_stop;
wire clear_stop;
wire global_interrupt_enable;
wire sw_reset_strobe; // this strobe will be one cycle earlier than sw_reset
wire set_sw_reset;
wire clear_sw_reset;
/********************************************** Registers ***************************************************/
// read latency is 1 cycle
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
readdata_d1 <= 0;
end
else if (csr_read == 1)
begin
readdata_d1 <= readdata;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
control[31:1] <= 0;
end
else
begin
if (sw_reset_strobe == 1) // reset strobe is a strobe due to this sync reset
begin
control[31:1] <= 0;
end
else
begin
if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1))
begin
control[7:1] <= csr_writedata[7:1]; // stop bit will be handled seperately since it can be set by the csr slave port access or the SGDMA hitting an error condition
end
if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[1] == 1))
begin
control[15:8] <= csr_writedata[15:8];
end
if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[2] == 1))
begin
control[23:16] <= csr_writedata[23:16];
end
if ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[3] == 1))
begin
control[31:24] <= csr_writedata[31:24];
end
end
end
end
// control bit 0 (stop) is set by different sources so handling it seperately
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
control[0] <= 0;
end
else
begin
if (sw_reset_strobe == 1)
begin
control[0] <= 0;
end
else
begin
case ({set_stop, clear_stop})
2'b00: control[0] <= control[0];
2'b01: control[0] <= 1'b0;
2'b10: control[0] <= 1'b1;
2'b11: control[0] <= 1'b1; // setting will win, this case happens control[0] is being set to 0 (resume) at the same time an error/early termination stop condition occurs
endcase
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
sw_reset <= 0;
end
else
begin
if (set_sw_reset == 1)
begin
sw_reset <= 1;
end
else if (clear_sw_reset == 1)
begin
sw_reset <= 0;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
stopped_on_error <= 0;
end
else
begin
case ({set_stopped_on_error, clear_stop})
2'b00: stopped_on_error <= stopped_on_error;
2'b01: stopped_on_error <= 1'b0;
2'b10: stopped_on_error <= 1'b1;
2'b11: stopped_on_error <= 1'b0;
endcase
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
stopped_on_early_termination <= 0;
end
else
begin
case ({set_stopped_on_early_termination, clear_stop})
2'b00: stopped_on_early_termination <= stopped_on_early_termination;
2'b01: stopped_on_early_termination <= 1'b0;
2'b10: stopped_on_early_termination <= 1'b1;
2'b11: stopped_on_early_termination <= 1'b0;
endcase
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
irq <= 0;
end
else
begin
if (sw_reset_strobe == 1)
begin
irq <= 0;
end
else
begin
case ({clear_irq, set_irq})
2'b00: irq <= irq;
2'b01: irq <= 1'b1;
2'b10: irq <= 1'b0;
2'b11: irq <= 1'b1; // setting will win over a clear
endcase
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
irq_count <= {16{1'b0}};
end
else
begin
if (sw_reset_strobe == 1)
begin
irq_count <= {16{1'b0}};
end
else
begin
case ({clear_irq_count, incr_irq_count})
2'b00: irq_count <= irq_count;
2'b01: irq_count <= irq_count + 1;
2'b10: irq_count <= {16{1'b0}};
2'b11: irq_count <= {{15{1'b0}}, 1'b1};
endcase
end
end
end
/******************************************** End Registers *************************************************/
/**************************************** Combinational Signals *********************************************/
generate
if (ADDRESS_WIDTH == 3)
begin
always @ (csr_address or status or control or descriptor_watermark or response_watermark or sequence_number)
begin
case (csr_address)
3'b000: readdata = status;
3'b001: readdata = control;
3'b010: readdata = descriptor_watermark;
3'b011: readdata = response_watermark;
default: readdata = sequence_number; // all other addresses will decode to the sequence number
endcase
end
end
else
begin
always @ (csr_address or status or control or descriptor_watermark or response_watermark)
begin
case (csr_address)
3'b000: readdata = status;
3'b001: readdata = control;
3'b010: readdata = descriptor_watermark;
default: readdata = response_watermark; // all other addresses will decode to the response watermark
endcase
end
end
endgenerate
assign clear_irq = (csr_address == 0) & (csr_write == 1) & (csr_byteenable[1] == 1) & (csr_writedata[9] == 1); // this is the IRQ bit
assign set_irq = (global_interrupt_enable == 1) & (done_strobe == 1) & // transfer ended and interrupts are enabled
((transfer_complete_IRQ_mask == 1) | // transfer ended and the transfer complete IRQ is enabled
((error & error_IRQ_mask) != 0) | // transfer ended with an error and this IRQ is enabled
((early_termination & early_termination_IRQ_mask) == 1)); // transfer ended early due to early termination and this IRQ is enabled
assign csr_irq = irq;
// Done count
assign incr_irq_count = set_irq; // Done count just counts the number of interrupts since the last reset
assign clear_irq_count = (csr_address == 0) & (csr_write == 1) & (csr_byteenable[2] == 1) & (csr_writedata[16] == 1); // the LSB irq_count bit
assign clear_stop = (csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1) & (csr_writedata[0] == 0);
assign set_stopped_on_error = (done_strobe == 1) & (stop_on_error == 1) & (error != 0); // when clear_stop is set then the stopped_on_error register will be cleared
assign set_stopped_on_early_termination = (done_strobe == 1) & (stop_on_early_termination == 1) & (early_termination == 1); // when clear_stop is set then the stopped_on_early_termination register will be cleared
assign set_stop = ((csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1) & (csr_writedata[0] == 1)) | // host set the stop bit
(set_stopped_on_error == 1) | // SGDMA setup to stop when an error occurs from the write master
(set_stopped_on_early_termination == 1) ; // SGDMA setup to stop when the write master overflows
assign stop = control[0];
assign set_sw_reset = (csr_address == CONTROL_REGISTER_ADDRESS) & (csr_write == 1) & (csr_byteenable[0] == 1) & (csr_writedata[1] == 1);
assign clear_sw_reset = (sw_reset == 1) & (reset_stalled == 0);
assign sw_reset_strobe = control[1];
assign stop_on_error = control[2];
assign stop_on_early_termination = control[3];
assign global_interrupt_enable = control[4];
assign stop_descriptors = control[5];
assign csr_readdata = readdata_d1;
assign status = {irq_count, {6{1'b0}}, irq, stopped_on_early_termination, stopped_on_error, sw_reset, stop_state, response_buffer_full, response_buffer_empty, descriptor_buffer_full, descriptor_buffer_empty, busy}; // writing to the lower byte of the status register clears the irq bit
/**************************************** Combinational Signals *********************************************/
endmodule
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2021 Cologne Chip AG <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
(* blackbox *)
module CC_PLL #(
parameter REF_CLK = "", // e.g. "10.0"
parameter OUT_CLK = "", // e.g. "50.0"
parameter PERF_MD = "", // LOWPOWER, ECONOMY, SPEED
parameter LOW_JITTER = 1,
parameter CI_FILTER_CONST = 2,
parameter CP_FILTER_CONST = 4
)(
input CLK_REF, CLK_FEEDBACK, USR_CLK_REF,
input USR_LOCKED_STDY_RST,
output USR_PLL_LOCKED_STDY, USR_PLL_LOCKED,
output CLK270, CLK180, CLK90, CLK0, CLK_REF_OUT
);
endmodule
(* blackbox *)
module CC_PLL_ADV #(
parameter [95:0] PLL_CFG_A = 96'bx,
parameter [95:0] PLL_CFG_B = 96'bx
)(
input CLK_REF, CLK_FEEDBACK, USR_CLK_REF,
input USR_LOCKED_STDY_RST, USR_SEL_A_B,
output USR_PLL_LOCKED_STDY, USR_PLL_LOCKED,
output CLK270, CLK180, CLK90, CLK0, CLK_REF_OUT
);
endmodule
(* blackbox *) (* keep *)
module CC_SERDES #(
parameter SERDES_CFG = ""
)(
input [63:0] TX_DATA_I,
input TX_RESET_I,
input TX_PCS_RESET_I,
input TX_PMA_RESET_I,
input PLL_RESET_I,
input TX_POWERDOWN_N_I,
input TX_POLARITY_I,
input [2:0] TX_PRBS_SEL_I,
input TX_PRBS_FORCE_ERR_I,
input TX_8B10B_EN_I,
input [7:0] TX_8B10B_BYPASS_I,
input [7:0] TX_CHAR_IS_K_I,
input [7:0] TX_CHAR_DISPMODE_I,
input [7:0] TX_CHAR_DISPVAL_I,
input TX_ELEC_IDLE_I,
input TX_DETECT_RX_I,
input [2:0] LOOPBACK_I,
input CLK_CORE_TX_I,
input CLK_CORE_RX_I,
input RX_RESET_I,
input RX_PMA_RESET_I,
input RX_EQA_RESET_I,
input RX_CDR_RESET_I,
input RX_PCS_RESET_I,
input RX_BUF_RESET_I,
input RX_POWERDOWN_N_I,
input RX_POLARITY_I,
input [2:0] RX_PRBS_SEL_I,
input RX_PRBS_CNT_RESET_I,
input RX_8B10B_EN_I,
input [7:0] RX_8B10B_BYPASS_I,
input RX_EN_EI_DETECTOR_I,
input RX_COMMA_DETECT_EN_I,
input RX_SLIDE_I,
input RX_MCOMMA_ALIGN_I,
input RX_PCOMMA_ALIGN_I,
input CLK_REG_I,
input REGFILE_WE_I,
input REGFILE_EN_I,
input [7:0] REGFILE_ADDR_I,
input [15:0] REGFILE_DI_I,
input [15:0] REGFILE_MASK_I,
output [63:0] RX_DATA_O,
output [7:0] RX_NOT_IN_TABLE_O,
output [7:0] RX_CHAR_IS_COMMA_O,
output [7:0] RX_CHAR_IS_K_O,
output [7:0] RX_DISP_ERR_O,
output RX_DETECT_DONE_O,
output RX_PRESENT_O,
output TX_BUF_ERR_O,
output TX_RESETDONE_O,
output RX_PRBS_ERR_O,
output RX_BUF_ERR_O,
output RX_BYTE_IS_ALIGNED_O,
output RX_BYTE_REALIGN_O,
output RX_RESETDONE_O,
output RX_EI_EN_O,
output CLK_CORE_RX_O,
output CLK_CORE_PLL_O,
output [15:0] REGFILE_DO_O,
output REGFILE_RDY_O
);
endmodule
(* blackbox *) (* keep *)
module CC_CFG_CTRL(
input [7:0] DATA,
input CLK,
input EN,
input RECFG,
input VALID
);
endmodule
(* blackbox *)
module CC_FIFO_40K (
output A_ECC_1B_ERR,
output B_ECC_1B_ERR,
output A_ECC_2B_ERR,
output B_ECC_2B_ERR,
// FIFO pop port
output [39:0] A_DO,
output [39:0] B_DO,
(* clkbuf_sink *)
input A_CLK,
input A_EN,
// FIFO push port
input [39:0] A_DI,
input [39:0] B_DI,
input [39:0] A_BM,
input [39:0] B_BM,
(* clkbuf_sink *)
input B_CLK,
input B_EN,
input B_WE,
// FIFO control
input F_RST_N,
input [12:0] F_ALMOST_FULL_OFFSET,
input [12:0] F_ALMOST_EMPTY_OFFSET,
// FIFO status signals
output F_FULL,
output F_EMPTY,
output F_ALMOST_FULL,
output F_ALMOST_EMPTY,
output F_RD_ERROR,
output F_WR_ERROR,
output [15:0] F_RD_PTR,
output [15:0] F_WR_PTR
);
// Location format: D(0..N-1)X(0..3)Y(0..7) or UNPLACED
parameter LOC = "UNPLACED";
// Offset configuration
parameter [12:0] ALMOST_FULL_OFFSET = 12'b0;
parameter [12:0] ALMOST_EMPTY_OFFSET = 12'b0;
// Port Widths
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
// RAM and Write Modes
parameter RAM_MODE = "SDP"; // "TPD" or "SDP"
parameter FIFO_MODE = "SYNC"; // "ASYNC" or "SYNC"
// Inverting Control Pins
parameter A_CLK_INV = 1'b0;
parameter B_CLK_INV = 1'b0;
parameter A_EN_INV = 1'b0;
parameter B_EN_INV = 1'b0;
parameter A_WE_INV = 1'b0;
parameter B_WE_INV = 1'b0;
// Output Register
parameter A_DO_REG = 1'b0;
parameter B_DO_REG = 1'b0;
// Error Checking and Correction
parameter A_ECC_EN = 1'b0;
parameter B_ECC_EN = 1'b0;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__OR3_FUNCTIONAL_PP_V
/**
* or3: 3-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__or3 (
VPWR,
VGND,
X ,
A ,
B ,
C
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
input B ;
input C ;
// Local signals
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
or or0 (or0_out_X , B, A, C );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR3_FUNCTIONAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__BUF_FUNCTIONAL_V
`define SKY130_FD_SC_LS__BUF_FUNCTIONAL_V
/**
* buf: Buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__buf (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__BUF_FUNCTIONAL_V |
/*
*
* Copyright (c) 2011 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
module e0 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[1:0],x[31:2]} ^ {x[12:0],x[31:13]} ^ {x[21:0],x[31:22]};
endmodule
module e1 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[5:0],x[31:6]} ^ {x[10:0],x[31:11]} ^ {x[24:0],x[31:25]};
endmodule
module ch (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = z ^ (x & (y ^ z));
endmodule
module maj (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = (x & y) | (z & (x | y));
endmodule
module s0 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:29] = x[6:4] ^ x[17:15];
assign y[28:0] = {x[3:0], x[31:7]} ^ {x[14:0],x[31:18]} ^ x[31:3];
endmodule
module s1 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:22] = x[16:7] ^ x[18:9];
assign y[21:0] = {x[6:0],x[31:17]} ^ {x[8:0],x[31:19]} ^ x[31:10];
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: altpcie_pll_100_125.v
// Megafunction Name(s):
// altpll
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.1 Build 175 10/25/2005 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altpcie_pll_100_125 (
areset,
inclk0,
c0,
locked);
input areset;
input inclk0;
output c0;
output locked;
wire [5:0] sub_wire0;
wire sub_wire2;
wire [0:0] sub_wire3 = 1'h0;
wire [0:0] sub_wire5 = 1'h1;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire locked = sub_wire2;
wire [5:0] sub_wire4 = {sub_wire3, sub_wire3, sub_wire3, sub_wire3, sub_wire3, sub_wire5};
wire sub_wire6 = inclk0;
wire [1:0] sub_wire7 = {sub_wire3, sub_wire6};
wire [3:0] sub_wire8 = {sub_wire3, sub_wire3, sub_wire3, sub_wire3};
altpll altpll_component (
.clkena (sub_wire4),
.inclk (sub_wire7),
.extclkena (sub_wire8),
.areset (areset),
.clk (sub_wire0),
.locked (sub_wire2)
// synopsys translate_off
,
.scanclk (),
.pllena (),
.sclkout1 (),
.sclkout0 (),
.fbin (),
.scandone (),
.clkloss (),
.extclk (),
.clkswitch (),
.pfdena (),
.scanaclr (),
.clkbad (),
.scandata (),
.enable1 (),
.scandataout (),
.enable0 (),
.scanwrite (),
.activeclock (),
.scanread ()
// synopsys translate_on
);
defparam
altpll_component.bandwidth = 500000,
altpll_component.bandwidth_type = "CUSTOM",
altpll_component.clk0_divide_by = 4,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 5,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 10000,
altpll_component.intended_device_family = "Stratix GX",
altpll_component.invalid_lock_multiplier = 5,
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "ENHANCED",
altpll_component.spread_frequency = 0,
altpll_component.valid_lock_multiplier = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "2.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "10"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "5"
// Retrieval info: PRIVATE: DEV_FAMILY STRING "Stratix GX"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "300.000"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "125.000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH NUMERIC "500000"
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "CUSTOM"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "4"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "5"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "10000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix GX"
// Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "ENHANCED"
// Retrieval info: CONSTANT: SPREAD_FREQUENCY NUMERIC "0"
// Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: @extclkena 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @clkena 0 0 1 4 GND 0 0 0 0
// Retrieval info: CONNECT: @clkena 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: @extclkena 0 0 1 2 GND 0 0 0 0
// Retrieval info: CONNECT: @clkena 0 0 1 5 GND 0 0 0 0
// Retrieval info: CONNECT: @clkena 0 0 1 2 GND 0 0 0 0
// Retrieval info: CONNECT: @clkena 0 0 1 0 VCC 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @extclkena 0 0 1 3 GND 0 0 0 0
// Retrieval info: CONNECT: @extclkena 0 0 1 0 GND 0 0 0 0
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @clkena 0 0 1 3 GND 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_100_125.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_100_125.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_100_125.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_100_125.bsf FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_100_125_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_100_125_bb.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_100_125_waveforms.html FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_100_125_wave*.jpg FALSE FALSE
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2015 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
Require Import Nnat ZArith_base ROmega ZArithRing Zdiv Morphisms.
Local Open Scope Z_scope.
(** This file provides results about the Round-Toward-Zero Euclidean
division [Z.quotrem], whose projections are [Z.quot] (noted ÷)
and [Z.rem].
This division and [Z.div] agree only on positive numbers.
Otherwise, [Z.div] performs Round-Toward-Bottom (a.k.a Floor).
This [Z.quot] is compatible with the division of usual
programming languages such as Ocaml. In addition, it has nicer
properties with respect to opposite and other usual operations.
The definition of this division is now in file [BinIntDef],
while most of the results about here are now in the main module
[BinInt.Z], thanks to the generic "Numbers" layer. Remain here:
- some compatibility notation for old names.
- some extra results with less preconditions (in particular
exploiting the arbitrary value of division by 0).
*)
Notation Ndiv_Zquot := N2Z.inj_quot (compat "8.3").
Notation Nmod_Zrem := N2Z.inj_rem (compat "8.3").
Notation Z_quot_rem_eq := Z.quot_rem' (compat "8.3").
Notation Zrem_lt := Z.rem_bound_abs (compat "8.3").
Notation Zquot_unique := Z.quot_unique (compat "8.3").
Notation Zrem_unique := Z.rem_unique (compat "8.3").
Notation Zrem_1_r := Z.rem_1_r (compat "8.3").
Notation Zquot_1_r := Z.quot_1_r (compat "8.3").
Notation Zrem_1_l := Z.rem_1_l (compat "8.3").
Notation Zquot_1_l := Z.quot_1_l (compat "8.3").
Notation Z_quot_same := Z.quot_same (compat "8.3").
Notation Z_quot_mult := Z.quot_mul (compat "8.3").
Notation Zquot_small := Z.quot_small (compat "8.3").
Notation Zrem_small := Z.rem_small (compat "8.3").
Notation Zquot2_quot := Zquot2_quot (compat "8.3").
(** Particular values taken for [a÷0] and [(Z.rem a 0)].
We avise to not rely on these arbitrary values. *)
Lemma Zquot_0_r a : a ÷ 0 = 0.
Proof. now destruct a. Qed.
Lemma Zrem_0_r a : Z.rem a 0 = a.
Proof. now destruct a. Qed.
(** The following results are expressed without the [b<>0] condition
whenever possible. *)
Lemma Zrem_0_l a : Z.rem 0 a = 0.
Proof. now destruct a. Qed.
Lemma Zquot_0_l a : 0÷a = 0.
Proof. now destruct a. Qed.
Hint Resolve Zrem_0_l Zrem_0_r Zquot_0_l Zquot_0_r Z.quot_1_r Z.rem_1_r
: zarith.
Ltac zero_or_not a :=
destruct (Z.eq_decidable a 0) as [->|?];
[rewrite ?Zquot_0_l, ?Zrem_0_l, ?Zquot_0_r, ?Zrem_0_r;
auto with zarith|].
Lemma Z_rem_same a : Z.rem a a = 0.
Proof. zero_or_not a. now apply Z.rem_same. Qed.
Lemma Z_rem_mult a b : Z.rem (a*b) b = 0.
Proof. zero_or_not b. now apply Z.rem_mul. Qed.
(** * Division and Opposite *)
(* The precise equalities that are invalid with "historic" Zdiv. *)
Theorem Zquot_opp_l a b : (-a)÷b = -(a÷b).
Proof. zero_or_not b. now apply Z.quot_opp_l. Qed.
Theorem Zquot_opp_r a b : a÷(-b) = -(a÷b).
Proof. zero_or_not b. now apply Z.quot_opp_r. Qed.
Theorem Zrem_opp_l a b : Z.rem (-a) b = -(Z.rem a b).
Proof. zero_or_not b. now apply Z.rem_opp_l. Qed.
Theorem Zrem_opp_r a b : Z.rem a (-b) = Z.rem a b.
Proof. zero_or_not b. now apply Z.rem_opp_r. Qed.
Theorem Zquot_opp_opp a b : (-a)÷(-b) = a÷b.
Proof. zero_or_not b. now apply Z.quot_opp_opp. Qed.
Theorem Zrem_opp_opp a b : Z.rem (-a) (-b) = -(Z.rem a b).
Proof. zero_or_not b. now apply Z.rem_opp_opp. Qed.
(** The sign of the remainder is the one of [a]. Due to the possible
nullity of [a], a general result is to be stated in the following form:
*)
Theorem Zrem_sgn a b : 0 <= Z.sgn (Z.rem a b) * Z.sgn a.
Proof.
zero_or_not b.
- apply Z.square_nonneg.
- zero_or_not (Z.rem a b).
rewrite Z.rem_sign_nz; trivial. apply Z.square_nonneg.
Qed.
(** This can also be said in a simplier way: *)
Theorem Zrem_sgn2 a b : 0 <= (Z.rem a b) * a.
Proof.
zero_or_not b.
- apply Z.square_nonneg.
- now apply Z.rem_sign_mul.
Qed.
(** Reformulation of [Z.rem_bound_abs] in 2 then 4 particular cases. *)
Theorem Zrem_lt_pos a b : 0<=a -> b<>0 -> 0 <= Z.rem a b < Z.abs b.
Proof.
intros; generalize (Z.rem_nonneg a b) (Z.rem_bound_abs a b);
romega with *.
Qed.
Theorem Zrem_lt_neg a b : a<=0 -> b<>0 -> -Z.abs b < Z.rem a b <= 0.
Proof.
intros; generalize (Z.rem_nonpos a b) (Z.rem_bound_abs a b);
romega with *.
Qed.
Theorem Zrem_lt_pos_pos a b : 0<=a -> 0<b -> 0 <= Z.rem a b < b.
Proof.
intros; generalize (Zrem_lt_pos a b); romega with *.
Qed.
Theorem Zrem_lt_pos_neg a b : 0<=a -> b<0 -> 0 <= Z.rem a b < -b.
Proof.
intros; generalize (Zrem_lt_pos a b); romega with *.
Qed.
Theorem Zrem_lt_neg_pos a b : a<=0 -> 0<b -> -b < Z.rem a b <= 0.
Proof.
intros; generalize (Zrem_lt_neg a b); romega with *.
Qed.
Theorem Zrem_lt_neg_neg a b : a<=0 -> b<0 -> b < Z.rem a b <= 0.
Proof.
intros; generalize (Zrem_lt_neg a b); romega with *.
Qed.
(** * Unicity results *)
Definition Remainder a b r :=
(0 <= a /\ 0 <= r < Z.abs b) \/ (a <= 0 /\ -Z.abs b < r <= 0).
Definition Remainder_alt a b r :=
Z.abs r < Z.abs b /\ 0 <= r * a.
Lemma Remainder_equiv : forall a b r,
Remainder a b r <-> Remainder_alt a b r.
Proof.
unfold Remainder, Remainder_alt; intuition.
- romega with *.
- romega with *.
- rewrite <-(Z.mul_opp_opp). apply Z.mul_nonneg_nonneg; romega.
- assert (0 <= Z.sgn r * Z.sgn a).
{ rewrite <-Z.sgn_mul, Z.sgn_nonneg; auto. }
destruct r; simpl Z.sgn in *; romega with *.
Qed.
Theorem Zquot_mod_unique_full a b q r :
Remainder a b r -> a = b*q + r -> q = a÷b /\ r = Z.rem a b.
Proof.
destruct 1 as [(H,H0)|(H,H0)]; intros.
apply Zdiv_mod_unique with b; auto.
apply Zrem_lt_pos; auto.
romega with *.
rewrite <- H1; apply Z.quot_rem'.
rewrite <- (Z.opp_involutive a).
rewrite Zquot_opp_l, Zrem_opp_l.
generalize (Zdiv_mod_unique b (-q) (-a÷b) (-r) (Z.rem (-a) b)).
generalize (Zrem_lt_pos (-a) b).
rewrite <-Z.quot_rem', Z.mul_opp_r, <-Z.opp_add_distr, <-H1.
romega with *.
Qed.
Theorem Zquot_unique_full a b q r :
Remainder a b r -> a = b*q + r -> q = a÷b.
Proof.
intros; destruct (Zquot_mod_unique_full a b q r); auto.
Qed.
Theorem Zrem_unique_full a b q r :
Remainder a b r -> a = b*q + r -> r = Z.rem a b.
Proof.
intros; destruct (Zquot_mod_unique_full a b q r); auto.
Qed.
(** * Order results about Zrem and Zquot *)
(* Division of positive numbers is positive. *)
Lemma Z_quot_pos a b : 0 <= a -> 0 <= b -> 0 <= a÷b.
Proof. intros. zero_or_not b. apply Z.quot_pos; auto with zarith. Qed.
(** As soon as the divisor is greater or equal than 2,
the division is strictly decreasing. *)
Lemma Z_quot_lt a b : 0 < a -> 2 <= b -> a÷b < a.
Proof. intros. apply Z.quot_lt; auto with zarith. Qed.
(** [<=] is compatible with a positive division. *)
Lemma Z_quot_monotone a b c : 0<=c -> a<=b -> a÷c <= b÷c.
Proof. intros. zero_or_not c. apply Z.quot_le_mono; auto with zarith. Qed.
(** With our choice of division, rounding of (a÷b) is always done toward 0: *)
Lemma Z_mult_quot_le a b : 0 <= a -> 0 <= b*(a÷b) <= a.
Proof. intros. zero_or_not b. apply Z.mul_quot_le; auto with zarith. Qed.
Lemma Z_mult_quot_ge a b : a <= 0 -> a <= b*(a÷b) <= 0.
Proof. intros. zero_or_not b. apply Z.mul_quot_ge; auto with zarith. Qed.
(** The previous inequalities between [b*(a÷b)] and [a] are exact
iff the modulo is zero. *)
Lemma Z_quot_exact_full a b : a = b*(a÷b) <-> Z.rem a b = 0.
Proof. intros. zero_or_not b. intuition. apply Z.quot_exact; auto. Qed.
(** A modulo cannot grow beyond its starting point. *)
Theorem Zrem_le a b : 0 <= a -> 0 <= b -> Z.rem a b <= a.
Proof. intros. zero_or_not b. apply Z.rem_le; auto with zarith. Qed.
(** Some additionnal inequalities about Zdiv. *)
Theorem Zquot_le_upper_bound:
forall a b q, 0 < b -> a <= q*b -> a÷b <= q.
Proof. intros a b q; rewrite Z.mul_comm; apply Z.quot_le_upper_bound. Qed.
Theorem Zquot_lt_upper_bound:
forall a b q, 0 <= a -> 0 < b -> a < q*b -> a÷b < q.
Proof. intros a b q; rewrite Z.mul_comm; apply Z.quot_lt_upper_bound. Qed.
Theorem Zquot_le_lower_bound:
forall a b q, 0 < b -> q*b <= a -> q <= a÷b.
Proof. intros a b q; rewrite Z.mul_comm; apply Z.quot_le_lower_bound. Qed.
Theorem Zquot_sgn: forall a b,
0 <= Z.sgn (a÷b) * Z.sgn a * Z.sgn b.
Proof.
destruct a as [ |a|a]; destruct b as [ |b|b]; simpl; auto with zarith;
unfold Z.quot; simpl; destruct N.pos_div_eucl; simpl; destruct n; simpl; auto with zarith.
Qed.
(** * Relations between usual operations and Zmod and Zdiv *)
(** First, a result that used to be always valid with Zdiv,
but must be restricted here.
For instance, now (9+(-5)*2) rem 2 = -1 <> 1 = 9 rem 2 *)
Lemma Z_rem_plus : forall a b c:Z,
0 <= (a+b*c) * a ->
Z.rem (a + b * c) c = Z.rem a c.
Proof. intros. zero_or_not c. apply Z.rem_add; auto with zarith. Qed.
Lemma Z_quot_plus : forall a b c:Z,
0 <= (a+b*c) * a -> c<>0 ->
(a + b * c) ÷ c = a ÷ c + b.
Proof. intros. apply Z.quot_add; auto with zarith. Qed.
Theorem Z_quot_plus_l: forall a b c : Z,
0 <= (a*b+c)*c -> b<>0 ->
b<>0 -> (a * b + c) ÷ b = a + c ÷ b.
Proof. intros. apply Z.quot_add_l; auto with zarith. Qed.
(** Cancellations. *)
Lemma Zquot_mult_cancel_r : forall a b c:Z,
c<>0 -> (a*c)÷(b*c) = a÷b.
Proof. intros. zero_or_not b. apply Z.quot_mul_cancel_r; auto. Qed.
Lemma Zquot_mult_cancel_l : forall a b c:Z,
c<>0 -> (c*a)÷(c*b) = a÷b.
Proof.
intros. rewrite (Z.mul_comm c b). zero_or_not b.
rewrite (Z.mul_comm b c). apply Z.quot_mul_cancel_l; auto.
Qed.
Lemma Zmult_rem_distr_l: forall a b c,
Z.rem (c*a) (c*b) = c * (Z.rem a b).
Proof.
intros. zero_or_not c. rewrite (Z.mul_comm c b). zero_or_not b.
rewrite (Z.mul_comm b c). apply Z.mul_rem_distr_l; auto.
Qed.
Lemma Zmult_rem_distr_r: forall a b c,
Z.rem (a*c) (b*c) = (Z.rem a b) * c.
Proof.
intros. zero_or_not b. rewrite (Z.mul_comm b c). zero_or_not c.
rewrite (Z.mul_comm c b). apply Z.mul_rem_distr_r; auto.
Qed.
(** Operations modulo. *)
Theorem Zrem_rem: forall a n, Z.rem (Z.rem a n) n = Z.rem a n.
Proof. intros. zero_or_not n. apply Z.rem_rem; auto. Qed.
Theorem Zmult_rem: forall a b n,
Z.rem (a * b) n = Z.rem (Z.rem a n * Z.rem b n) n.
Proof. intros. zero_or_not n. apply Z.mul_rem; auto. Qed.
(** addition and modulo
Generally speaking, unlike with Zdiv, we don't have
(a+b) rem n = (a rem n + b rem n) rem n
for any a and b.
For instance, take (8 + (-10)) rem 3 = -2 whereas
(8 rem 3 + (-10 rem 3)) rem 3 = 1. *)
Theorem Zplus_rem: forall a b n,
0 <= a * b ->
Z.rem (a + b) n = Z.rem (Z.rem a n + Z.rem b n) n.
Proof. intros. zero_or_not n. apply Z.add_rem; auto. Qed.
Lemma Zplus_rem_idemp_l: forall a b n,
0 <= a * b ->
Z.rem (Z.rem a n + b) n = Z.rem (a + b) n.
Proof. intros. zero_or_not n. apply Z.add_rem_idemp_l; auto. Qed.
Lemma Zplus_rem_idemp_r: forall a b n,
0 <= a*b ->
Z.rem (b + Z.rem a n) n = Z.rem (b + a) n.
Proof.
intros. zero_or_not n. apply Z.add_rem_idemp_r; auto.
rewrite Z.mul_comm; auto.
Qed.
Lemma Zmult_rem_idemp_l: forall a b n, Z.rem (Z.rem a n * b) n = Z.rem (a * b) n.
Proof. intros. zero_or_not n. apply Z.mul_rem_idemp_l; auto. Qed.
Lemma Zmult_rem_idemp_r: forall a b n, Z.rem (b * Z.rem a n) n = Z.rem (b * a) n.
Proof. intros. zero_or_not n. apply Z.mul_rem_idemp_r; auto. Qed.
(** Unlike with Zdiv, the following result is true without restrictions. *)
Lemma Zquot_Zquot : forall a b c, (a÷b)÷c = a÷(b*c).
Proof.
intros. zero_or_not b. rewrite Z.mul_comm. zero_or_not c.
rewrite Z.mul_comm. apply Z.quot_quot; auto.
Qed.
(** A last inequality: *)
Theorem Zquot_mult_le:
forall a b c, 0<=a -> 0<=b -> 0<=c -> c*(a÷b) <= (c*a)÷b.
Proof. intros. zero_or_not b. apply Z.quot_mul_le; auto with zarith. Qed.
(** Z.rem is related to divisibility (see more in Znumtheory) *)
Lemma Zrem_divides : forall a b,
Z.rem a b = 0 <-> exists c, a = b*c.
Proof.
intros. zero_or_not b. firstorder.
rewrite Z.rem_divide; trivial.
split; intros (c,Hc); exists c; subst; auto with zarith.
Qed.
(** Particular case : dividing by 2 is related with parity *)
Lemma Zquot2_odd_remainder : forall a,
Remainder a 2 (if Z.odd a then Z.sgn a else 0).
Proof.
intros [ |p|p]. simpl.
left. simpl. auto with zarith.
left. destruct p; simpl; auto with zarith.
right. destruct p; simpl; split; now auto with zarith.
Qed.
Lemma Zrem_odd : forall a, Z.rem a 2 = if Z.odd a then Z.sgn a else 0.
Proof.
intros. symmetry.
apply Zrem_unique_full with (Z.quot2 a).
apply Zquot2_odd_remainder.
apply Zquot2_odd_eqn.
Qed.
Lemma Zrem_even : forall a, Z.rem a 2 = if Z.even a then 0 else Z.sgn a.
Proof.
intros a. rewrite Zrem_odd, Zodd_even_bool. now destruct Z.even.
Qed.
Lemma Zeven_rem : forall a, Z.even a = Z.eqb (Z.rem a 2) 0.
Proof.
intros a. rewrite Zrem_even.
destruct a as [ |p|p]; trivial; now destruct p.
Qed.
Lemma Zodd_rem : forall a, Z.odd a = negb (Z.eqb (Z.rem a 2) 0).
Proof.
intros a. rewrite Zrem_odd.
destruct a as [ |p|p]; trivial; now destruct p.
Qed.
(** * Interaction with "historic" Zdiv *)
(** They agree at least on positive numbers: *)
Theorem Zquotrem_Zdiv_eucl_pos : forall a b:Z, 0 <= a -> 0 < b ->
a÷b = a/b /\ Z.rem a b = a mod b.
Proof.
intros.
apply Zdiv_mod_unique with b.
apply Zrem_lt_pos; auto with zarith.
rewrite Z.abs_eq; auto with *; apply Z_mod_lt; auto with *.
rewrite <- Z_div_mod_eq; auto with *.
symmetry; apply Z.quot_rem; auto with *.
Qed.
Theorem Zquot_Zdiv_pos : forall a b, 0 <= a -> 0 <= b ->
a÷b = a/b.
Proof.
intros a b Ha Hb. Z.le_elim Hb.
- generalize (Zquotrem_Zdiv_eucl_pos a b Ha Hb); intuition.
- subst; now rewrite Zquot_0_r, Zdiv_0_r.
Qed.
Theorem Zrem_Zmod_pos : forall a b, 0 <= a -> 0 < b ->
Z.rem a b = a mod b.
Proof.
intros a b Ha Hb; generalize (Zquotrem_Zdiv_eucl_pos a b Ha Hb);
intuition.
Qed.
(** Modulos are null at the same places *)
Theorem Zrem_Zmod_zero : forall a b, b<>0 ->
(Z.rem a b = 0 <-> a mod b = 0).
Proof.
intros.
rewrite Zrem_divides, Zmod_divides; intuition.
Qed.
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
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//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2.3
// \ \ Application : MIG
// / / Filename : dram_mig.v
// /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
// \ \ / \ Date Created : Tue Sept 21 2010
// \___\/\___\
//
// Device : 7 Series
// Design Name : DDR3 SDRAM
// Purpose :
// Top-level module. This module can be instantiated in the
// system and interconnect as shown in user design wrapper file (user top module).
// In addition to the memory controller, the module instantiates:
// 1. Clock generation/distribution, reset logic
// 2. IDELAY control block
// 3. Debug logic
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module dram_mig #
(
//***************************************************************************
// The following parameters refer to width of various ports
//***************************************************************************
parameter BANK_WIDTH = 3,
// # of memory Bank Address bits.
parameter CK_WIDTH = 1,
// # of CK/CK# outputs to memory.
parameter COL_WIDTH = 10,
// # of memory Column Address bits.
parameter CS_WIDTH = 1,
// # of unique CS outputs to memory.
parameter nCS_PER_RANK = 1,
// # of unique CS outputs per rank for phy
parameter CKE_WIDTH = 1,
// # of CKE outputs to memory.
parameter DATA_BUF_ADDR_WIDTH = 5,
parameter DQ_CNT_WIDTH = 6,
// = ceil(log2(DQ_WIDTH))
parameter DQ_PER_DM = 8,
parameter DM_WIDTH = 8,
// # of DM (data mask)
parameter DQ_WIDTH = 64,
// # of DQ (data)
parameter DQS_WIDTH = 8,
parameter DQS_CNT_WIDTH = 3,
// = ceil(log2(DQS_WIDTH))
parameter DRAM_WIDTH = 8,
// # of DQ per DQS
parameter ECC = "OFF",
parameter DATA_WIDTH = 64,
parameter ECC_TEST = "OFF",
parameter PAYLOAD_WIDTH = (ECC_TEST == "OFF") ? DATA_WIDTH : DQ_WIDTH,
parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN",
//Possible Parameters
//1.BANK_ROW_COLUMN : Address mapping is
// in form of Bank Row Column.
//2.ROW_BANK_COLUMN : Address mapping is
// in the form of Row Bank Column.
//3.TG_TEST : Scrambles Address bits
// for distributed Addressing.
parameter nBANK_MACHS = 4,
parameter RANKS = 1,
// # of Ranks.
parameter ODT_WIDTH = 1,
// # of ODT outputs to memory.
parameter ROW_WIDTH = 16,
// # of memory Row Address bits.
parameter ADDR_WIDTH = 30,
// # = RANK_WIDTH + BANK_WIDTH
// + ROW_WIDTH + COL_WIDTH;
// Chip Select is always tied to low for
// single rank devices
parameter USE_CS_PORT = 1,
// # = 1, When Chip Select (CS#) output is enabled
// = 0, When Chip Select (CS#) output is disabled
// If CS_N disabled, user must connect
// DRAM CS_N input(s) to ground
parameter USE_DM_PORT = 1,
// # = 1, When Data Mask option is enabled
// = 0, When Data Mask option is disbaled
// When Data Mask option is disabled in
// MIG Controller Options page, the logic
// related to Data Mask should not get
// synthesized
parameter USE_ODT_PORT = 1,
// # = 1, When ODT output is enabled
// = 0, When ODT output is disabled
// Parameter configuration for Dynamic ODT support:
// USE_ODT_PORT = 0, RTT_NOM = "DISABLED", RTT_WR = "60/120".
// This configuration allows to save ODT pin mapping from FPGA.
// The user can tie the ODT input of DRAM to HIGH.
parameter IS_CLK_SHARED = "FALSE",
// # = "true" when clock is shared
// = "false" when clock is not shared
parameter PHY_CONTROL_MASTER_BANK = 1,
// The bank index where master PHY_CONTROL resides,
// equal to the PLL residing bank
parameter MEM_DENSITY = "4Gb",
// Indicates the density of the Memory part
// Added for the sake of Vivado simulations
parameter MEM_SPEEDGRADE = "125",
// Indicates the Speed grade of Memory Part
// Added for the sake of Vivado simulations
parameter MEM_DEVICE_WIDTH = 8,
// Indicates the device width of the Memory Part
// Added for the sake of Vivado simulations
//***************************************************************************
// The following parameters are mode register settings
//***************************************************************************
parameter AL = "0",
// DDR3 SDRAM:
// Additive Latency (Mode Register 1).
// # = "0", "CL-1", "CL-2".
// DDR2 SDRAM:
// Additive Latency (Extended Mode Register).
parameter nAL = 0,
// # Additive Latency in number of clock
// cycles.
parameter BURST_MODE = "8",
// DDR3 SDRAM:
// Burst Length (Mode Register 0).
// # = "8", "4", "OTF".
// DDR2 SDRAM:
// Burst Length (Mode Register).
// # = "8", "4".
parameter BURST_TYPE = "SEQ",
// DDR3 SDRAM: Burst Type (Mode Register 0).
// DDR2 SDRAM: Burst Type (Mode Register).
// # = "SEQ" - (Sequential),
// = "INT" - (Interleaved).
parameter CL = 11,
// in number of clock cycles
// DDR3 SDRAM: CAS Latency (Mode Register 0).
// DDR2 SDRAM: CAS Latency (Mode Register).
parameter CWL = 8,
// in number of clock cycles
// DDR3 SDRAM: CAS Write Latency (Mode Register 2).
// DDR2 SDRAM: Can be ignored
parameter OUTPUT_DRV = "HIGH",
// Output Driver Impedance Control (Mode Register 1).
// # = "HIGH" - RZQ/7,
// = "LOW" - RZQ/6.
parameter RTT_NOM = "40",
// RTT_NOM (ODT) (Mode Register 1).
// = "120" - RZQ/2,
// = "60" - RZQ/4,
// = "40" - RZQ/6.
parameter RTT_WR = "OFF",
// RTT_WR (ODT) (Mode Register 2).
// # = "OFF" - Dynamic ODT off,
// = "120" - RZQ/2,
// = "60" - RZQ/4,
parameter ADDR_CMD_MODE = "1T" ,
// # = "1T", "2T".
parameter REG_CTRL = "OFF",
// # = "ON" - RDIMMs,
// = "OFF" - Components, SODIMMs, UDIMMs.
parameter CA_MIRROR = "OFF",
// C/A mirror opt for DDR3 dual rank
parameter VDD_OP_VOLT = "150",
// # = "150" - 1.5V Vdd Memory part
// = "135" - 1.35V Vdd Memory part
//***************************************************************************
// The following parameters are multiplier and divisor factors for PLLE2.
// Based on the selected design frequency these parameters vary.
//***************************************************************************
parameter CLKIN_PERIOD = 5000,
// Input Clock Period
parameter CLKFBOUT_MULT = 8,
// write PLL VCO multiplier
parameter DIVCLK_DIVIDE = 1,
// write PLL VCO divisor
parameter CLKOUT0_PHASE = 337.5,
// Phase for PLL output clock (CLKOUT0)
parameter CLKOUT0_DIVIDE = 2,
// VCO output divisor for PLL output clock (CLKOUT0)
parameter CLKOUT1_DIVIDE = 2,
// VCO output divisor for PLL output clock (CLKOUT1)
parameter CLKOUT2_DIVIDE = 32,
// VCO output divisor for PLL output clock (CLKOUT2)
parameter CLKOUT3_DIVIDE = 8,
// VCO output divisor for PLL output clock (CLKOUT3)
parameter MMCM_VCO = 800,
// Max Freq (MHz) of MMCM VCO
parameter MMCM_MULT_F = 4,
// write MMCM VCO multiplier
parameter MMCM_DIVCLK_DIVIDE = 1,
// write MMCM VCO divisor
//***************************************************************************
// Memory Timing Parameters. These parameters varies based on the selected
// memory part.
//***************************************************************************
parameter tCKE = 5000,
// memory tCKE paramter in pS
parameter tFAW = 32000,
// memory tRAW paramter in pS.
parameter tPRDI = 1_000_000,
// memory tPRDI paramter in pS.
parameter tRAS = 35000,
// memory tRAS paramter in pS.
parameter tRCD = 13750,
// memory tRCD paramter in pS.
parameter tREFI = 7800000,
// memory tREFI paramter in pS.
parameter tRFC = 260000,
// memory tRFC paramter in pS.
parameter tRP = 13750,
// memory tRP paramter in pS.
parameter tRRD = 6000,
// memory tRRD paramter in pS.
parameter tRTP = 7500,
// memory tRTP paramter in pS.
parameter tWTR = 7500,
// memory tWTR paramter in pS.
parameter tZQI = 128_000_000,
// memory tZQI paramter in nS.
parameter tZQCS = 64,
// memory tZQCS paramter in clock cycles.
//***************************************************************************
// Simulation parameters
//***************************************************************************
parameter SIM_BYPASS_INIT_CAL = "OFF",
// # = "OFF" - Complete memory init &
// calibration sequence
// # = "SKIP" - Not supported
// # = "FAST" - Complete memory init & use
// abbreviated calib sequence
parameter SIMULATION = "FALSE",
// Should be TRUE during design simulations and
// FALSE during implementations
//***************************************************************************
// The following parameters varies based on the pin out entered in MIG GUI.
// Do not change any of these parameters directly by editing the RTL.
// Any changes required should be done through GUI and the design regenerated.
//***************************************************************************
parameter BYTE_LANES_B0 = 4'b1111,
// Byte lanes used in an IO column.
parameter BYTE_LANES_B1 = 4'b1110,
// Byte lanes used in an IO column.
parameter BYTE_LANES_B2 = 4'b1111,
// Byte lanes used in an IO column.
parameter BYTE_LANES_B3 = 4'b0000,
// Byte lanes used in an IO column.
parameter BYTE_LANES_B4 = 4'b0000,
// Byte lanes used in an IO column.
parameter DATA_CTL_B0 = 4'b1111,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B1 = 4'b0000,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B2 = 4'b1111,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B3 = 4'b0000,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B4 = 4'b0000,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter PHY_0_BITLANES = 48'h3FE_1FF_1FF_2FF,
parameter PHY_1_BITLANES = 48'hFFE_FF0_CB4_000,
parameter PHY_2_BITLANES = 48'h3FE_3FE_3BF_2FF,
// control/address/data pin mapping parameters
parameter CK_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_11,
parameter ADDR_MAP
= 192'h126_127_132_136_135_133_139_124_131_129_137_134_13A_128_138_13B,
parameter BANK_MAP = 36'h125_12A_12B,
parameter CAS_MAP = 12'h115,
parameter CKE_ODT_BYTE_MAP = 8'h00,
parameter CKE_MAP = 96'h000_000_000_000_000_000_000_117,
parameter ODT_MAP = 96'h000_000_000_000_000_000_000_112,
parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_114,
parameter PARITY_MAP = 12'h000,
parameter RAS_MAP = 12'h11A,
parameter WE_MAP = 12'h11B,
parameter DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_20_21_22_23_03_02_01_00,
parameter DATA0_MAP = 96'h009_000_003_001_007_006_005_002,
parameter DATA1_MAP = 96'h014_018_010_011_017_016_012_013,
parameter DATA2_MAP = 96'h021_022_025_020_027_023_026_028,
parameter DATA3_MAP = 96'h033_039_031_035_032_038_034_037,
parameter DATA4_MAP = 96'h231_238_237_236_233_232_234_239,
parameter DATA5_MAP = 96'h226_227_225_229_221_222_224_228,
parameter DATA6_MAP = 96'h214_215_210_218_217_213_219_212,
parameter DATA7_MAP = 96'h207_203_204_206_202_201_205_209,
parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000,
parameter MASK0_MAP = 108'h000_200_211_223_235_036_024_015_004,
parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter SLOT_0_CONFIG = 8'b0000_0001,
// Mapping of Ranks.
parameter SLOT_1_CONFIG = 8'b0000_0000,
// Mapping of Ranks.
//***************************************************************************
// IODELAY and PHY related parameters
//***************************************************************************
parameter IBUF_LPWR_MODE = "OFF",
// to phy_top
parameter DATA_IO_IDLE_PWRDWN = "ON",
// # = "ON", "OFF"
parameter BANK_TYPE = "HP_IO",
// # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter DATA_IO_PRIM_TYPE = "HP_LP",
// # = "HP_LP", "HR_LP", "DEFAULT"
parameter CKE_ODT_AUX = "FALSE",
parameter USER_REFRESH = "OFF",
parameter WRLVL = "ON",
// # = "ON" - DDR3 SDRAM
// = "OFF" - DDR2 SDRAM.
parameter ORDERING = "NORM",
// # = "NORM", "STRICT", "RELAXED".
parameter CALIB_ROW_ADD = 16'h0000,
// Calibration row address will be used for
// calibration read and write operations
parameter CALIB_COL_ADD = 12'h000,
// Calibration column address will be used for
// calibration read and write operations
parameter CALIB_BA_ADD = 3'h0,
// Calibration bank address will be used for
// calibration read and write operations
parameter TCQ = 100,
parameter IDELAY_ADJ = "ON",
parameter FINE_PER_BIT = "ON",
parameter CENTER_COMP_MODE = "ON",
parameter PI_VAL_ADJ = "ON",
parameter IODELAY_GRP0 = "DRAM_IODELAY_MIG0",
// It is associated to a set of IODELAYs with
// an IDELAYCTRL that have same IODELAY CONTROLLER
// clock frequency (200MHz).
parameter IODELAY_GRP1 = "DRAM_IODELAY_MIG1",
// It is associated to a set of IODELAYs with
// an IDELAYCTRL that have same IODELAY CONTROLLER
// clock frequency (300MHz/400MHz).
parameter SYSCLK_TYPE = "DIFFERENTIAL",
// System clock type DIFFERENTIAL, SINGLE_ENDED,
// NO_BUFFER
parameter REFCLK_TYPE = "USE_SYSTEM_CLOCK",
// Reference clock type DIFFERENTIAL, SINGLE_ENDED,
// NO_BUFFER, USE_SYSTEM_CLOCK
// parameter SYS_RST_PORT = "TRUE",
parameter SYS_RST_PORT = "FALSE",
// "TRUE" - if pin is selected for sys_rst
// and IBUF will be instantiated.
// "FALSE" - if pin is not selected for sys_rst
parameter FPGA_SPEED_GRADE = 2,
// FPGA speed grade
parameter CMD_PIPE_PLUS1 = "ON",
// add pipeline stage between MC and PHY
parameter DRAM_TYPE = "DDR3",
parameter CAL_WIDTH = "HALF",
parameter STARVE_LIMIT = 2,
// # = 2,3,4.
parameter REF_CLK_MMCM_IODELAY_CTRL = "TRUE",
//***************************************************************************
// Referece clock frequency parameters
//***************************************************************************
parameter REFCLK_FREQ = 200.0,
// IODELAYCTRL reference clock frequency
parameter DIFF_TERM_REFCLK = "TRUE",
// Differential Termination for idelay
// reference clock input pins
//***************************************************************************
// System clock frequency parameters
//***************************************************************************
parameter tCK = 1250,
// memory tCK paramter.
// # = Clock Period in pS.
parameter nCK_PER_CLK = 4,
// # of memory CKs per fabric CLK
parameter DIFF_TERM_SYSCLK = "FALSE",
// Differential Termination for System
// clock input pins
//***************************************************************************
// Debug parameters
//***************************************************************************
parameter DEBUG_PORT = "OFF",
// # = "ON" Enable debug signals/controls.
// = "OFF" Disable debug signals/controls.
//***************************************************************************
// Temparature monitor parameter
//***************************************************************************
parameter TEMP_MON_CONTROL = "INTERNAL",
// # = "INTERNAL", "EXTERNAL"
parameter RST_ACT_LOW = 0
// =1 for active low reset,
// =0 for active high.
)
(
// Inouts
inout [DQ_WIDTH-1:0] ddr3_dq,
inout [DQS_WIDTH-1:0] ddr3_dqs_n,
inout [DQS_WIDTH-1:0] ddr3_dqs_p,
// Outputs
output [ROW_WIDTH-1:0] ddr3_addr,
output [BANK_WIDTH-1:0] ddr3_ba,
output ddr3_ras_n,
output ddr3_cas_n,
output ddr3_we_n,
output ddr3_reset_n,
output [CK_WIDTH-1:0] ddr3_ck_p,
output [CK_WIDTH-1:0] ddr3_ck_n,
output [CKE_WIDTH-1:0] ddr3_cke,
output [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_cs_n,
output [DM_WIDTH-1:0] ddr3_dm,
output [ODT_WIDTH-1:0] ddr3_odt,
// Inputs
// Differential system clocks
input sys_clk_p,
input sys_clk_n,
// user interface signals
input [ADDR_WIDTH-1:0] app_addr,
input [2:0] app_cmd,
input app_en,
input [(nCK_PER_CLK*2*PAYLOAD_WIDTH)-1:0] app_wdf_data,
input app_wdf_end,
input [((nCK_PER_CLK*2*PAYLOAD_WIDTH)/8)-1:0] app_wdf_mask,
input app_wdf_wren,
output [(nCK_PER_CLK*2*PAYLOAD_WIDTH)-1:0] app_rd_data,
output app_rd_data_end,
output app_rd_data_valid,
output app_rdy,
output app_wdf_rdy,
input app_sr_req,
input app_ref_req,
input app_zq_req,
output app_sr_active,
output app_ref_ack,
output app_zq_ack,
output ui_clk,
output ui_clk_sync_rst,
output init_calib_complete,
// System reset - Default polarity of sys_rst pin is Active Low.
// System reset polarity will change based on the option
// selected in GUI.
input sys_rst
);
function integer clogb2 (input integer size);
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
localparam BM_CNT_WIDTH = clogb2(nBANK_MACHS);
localparam RANK_WIDTH = clogb2(RANKS);
localparam ECC_WIDTH = (ECC == "OFF")?
0 : (DATA_WIDTH <= 4)?
4 : (DATA_WIDTH <= 10)?
5 : (DATA_WIDTH <= 26)?
6 : (DATA_WIDTH <= 57)?
7 : (DATA_WIDTH <= 120)?
8 : (DATA_WIDTH <= 247)?
9 : 10;
localparam DATA_BUF_OFFSET_WIDTH = 1;
localparam MC_ERR_ADDR_WIDTH = ((CS_WIDTH == 1) ? 0 : RANK_WIDTH)
+ BANK_WIDTH + ROW_WIDTH + COL_WIDTH
+ DATA_BUF_OFFSET_WIDTH;
localparam APP_DATA_WIDTH = 2 * nCK_PER_CLK * PAYLOAD_WIDTH;
localparam APP_MASK_WIDTH = APP_DATA_WIDTH / 8;
localparam TEMP_MON_EN = (SIMULATION == "FALSE") ? "ON" : "OFF";
// Enable or disable the temp monitor module
localparam tTEMPSAMPLE = 10000000; // sample every 10 us
localparam XADC_CLK_PERIOD = 5000; // Use 200 MHz IODELAYCTRL clock
localparam TAPSPERKCLK = (56*MMCM_MULT_F)/nCK_PER_CLK;
// Wire declarations
wire [BM_CNT_WIDTH-1:0] bank_mach_next;
wire clk;
wire [1:0] clk_ref;
wire [1:0] iodelay_ctrl_rdy;
wire clk_ref_in;
wire sys_rst_o;
wire freq_refclk ;
wire mem_refclk ;
wire pll_lock ;
wire sync_pulse;
wire mmcm_ps_clk;
wire poc_sample_pd;
wire psen;
wire psincdec;
wire psdone;
wire iddr_rst;
wire ref_dll_lock;
wire rst_phaser_ref;
wire pll_locked;
wire rst;
wire [(2*nCK_PER_CLK)-1:0] app_ecc_multiple_err;
wire ddr3_parity;
wire sys_clk_i;
wire mmcm_clk;
wire clk_ref_p;
wire clk_ref_n;
wire clk_ref_i;
wire [11:0] device_temp;
wire [11:0] device_temp_i;
// Debug port signals
wire dbg_idel_down_all;
wire dbg_idel_down_cpt;
wire dbg_idel_up_all;
wire dbg_idel_up_cpt;
wire dbg_sel_all_idel_cpt;
wire [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt;
wire dbg_sel_pi_incdec;
wire [DQS_CNT_WIDTH:0] dbg_byte_sel;
wire dbg_pi_f_inc;
wire dbg_pi_f_dec;
wire [5:0] dbg_pi_counter_read_val;
wire [8:0] dbg_po_counter_read_val;
wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_cpt_tap_cnt;
wire [(5*DQS_WIDTH*RANKS)-1:0] dbg_dq_idelay_tap_cnt;
wire [255:0] dbg_calib_top;
wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_cpt_first_edge_cnt;
wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_cpt_second_edge_cnt;
wire [(6*RANKS)-1:0] dbg_rd_data_offset;
wire [255:0] dbg_phy_rdlvl;
wire [99:0] dbg_phy_wrcal;
wire [(6*DQS_WIDTH)-1:0] dbg_final_po_fine_tap_cnt;
wire [(3*DQS_WIDTH)-1:0] dbg_final_po_coarse_tap_cnt;
wire [255:0] dbg_phy_wrlvl;
wire [255:0] dbg_phy_init;
wire [255:0] dbg_prbs_rdlvl;
wire [255:0] dbg_dqs_found_cal;
wire dbg_pi_phaselock_start;
wire dbg_pi_phaselocked_done;
wire dbg_pi_phaselock_err;
wire dbg_pi_dqsfound_start;
wire dbg_pi_dqsfound_done;
wire dbg_pi_dqsfound_err;
wire dbg_wrcal_start;
wire dbg_wrcal_done;
wire dbg_wrcal_err;
wire [11:0] dbg_pi_dqs_found_lanes_phy4lanes;
wire [11:0] dbg_pi_phase_locked_phy4lanes;
wire dbg_oclkdelay_calib_start;
wire dbg_oclkdelay_calib_done;
wire [255:0] dbg_phy_oclkdelay_cal;
wire [(DRAM_WIDTH*16)-1:0] dbg_oclkdelay_rd_data;
wire [DQS_WIDTH-1:0] dbg_rd_data_edge_detect;
wire [(2*nCK_PER_CLK*DQ_WIDTH)-1:0] dbg_rddata;
wire dbg_rddata_valid;
wire [1:0] dbg_rdlvl_done;
wire [1:0] dbg_rdlvl_err;
wire [1:0] dbg_rdlvl_start;
wire [(6*DQS_WIDTH)-1:0] dbg_wrlvl_fine_tap_cnt;
wire [(3*DQS_WIDTH)-1:0] dbg_wrlvl_coarse_tap_cnt;
wire [5:0] dbg_tap_cnt_during_wrlvl;
wire dbg_wl_edge_detect_valid;
wire dbg_wrlvl_done;
wire dbg_wrlvl_err;
wire dbg_wrlvl_start;
reg [63:0] dbg_rddata_r;
reg dbg_rddata_valid_r;
wire [53:0] ocal_tap_cnt;
wire [4:0] dbg_dqs;
wire [8:0] dbg_bit;
wire [8:0] rd_data_edge_detect_r;
wire [53:0] wl_po_fine_cnt;
wire [26:0] wl_po_coarse_cnt;
wire [(6*RANKS)-1:0] dbg_calib_rd_data_offset_1;
wire [(6*RANKS)-1:0] dbg_calib_rd_data_offset_2;
wire [5:0] dbg_data_offset;
wire [5:0] dbg_data_offset_1;
wire [5:0] dbg_data_offset_2;
wire [390:0] ddr3_ila_wrpath_int;
wire [1023:0] ddr3_ila_rdpath_int;
wire [119:0] ddr3_ila_basic_int;
wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_prbs_final_dqs_tap_cnt_r_int;
wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_prbs_first_edge_taps_int;
wire [(6*DQS_WIDTH*RANKS)-1:0] dbg_prbs_second_edge_taps_int;
//***************************************************************************
assign ui_clk = clk;
assign ui_clk_sync_rst = rst;
assign sys_clk_i = 1'b0;
assign clk_ref_i = 1'b0;
generate
if (REFCLK_TYPE == "USE_SYSTEM_CLOCK")
assign clk_ref_in = mmcm_clk;
else
assign clk_ref_in = clk_ref_i;
endgenerate
mig_7series_v2_3_iodelay_ctrl #
(
.TCQ (TCQ),
.IODELAY_GRP0 (IODELAY_GRP0),
.IODELAY_GRP1 (IODELAY_GRP1),
.REFCLK_TYPE (REFCLK_TYPE),
.SYSCLK_TYPE (SYSCLK_TYPE),
.SYS_RST_PORT (SYS_RST_PORT),
.RST_ACT_LOW (RST_ACT_LOW),
.DIFF_TERM_REFCLK (DIFF_TERM_REFCLK),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.REF_CLK_MMCM_IODELAY_CTRL (REF_CLK_MMCM_IODELAY_CTRL)
)
u_iodelay_ctrl
(
// Outputs
.iodelay_ctrl_rdy (iodelay_ctrl_rdy),
.sys_rst_o (sys_rst_o),
.clk_ref (clk_ref),
// Inputs
.clk_ref_p (clk_ref_p),
.clk_ref_n (clk_ref_n),
.clk_ref_i (clk_ref_in),
.sys_rst (sys_rst)
);
mig_7series_v2_3_clk_ibuf #
(
.SYSCLK_TYPE (SYSCLK_TYPE),
.DIFF_TERM_SYSCLK (DIFF_TERM_SYSCLK)
)
u_ddr3_clk_ibuf
(
.sys_clk_p (sys_clk_p),
.sys_clk_n (sys_clk_n),
.sys_clk_i (sys_clk_i),
.mmcm_clk (mmcm_clk)
);
// Temperature monitoring logic
generate
if (TEMP_MON_EN == "ON") begin: temp_mon_enabled
mig_7series_v2_3_tempmon #
(
.TCQ (TCQ),
.TEMP_MON_CONTROL (TEMP_MON_CONTROL),
.XADC_CLK_PERIOD (XADC_CLK_PERIOD),
.tTEMPSAMPLE (tTEMPSAMPLE)
)
u_tempmon
(
.clk (clk),
.xadc_clk (clk_ref[0]),
.rst (rst),
.device_temp_i (device_temp_i),
.device_temp (device_temp)
);
end else begin: temp_mon_disabled
assign device_temp = 'b0;
end
endgenerate
mig_7series_v2_3_infrastructure #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.CLKIN_PERIOD (CLKIN_PERIOD),
.SYSCLK_TYPE (SYSCLK_TYPE),
.CLKFBOUT_MULT (CLKFBOUT_MULT),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKOUT0_PHASE (CLKOUT0_PHASE),
.CLKOUT0_DIVIDE (CLKOUT0_DIVIDE),
.CLKOUT1_DIVIDE (CLKOUT1_DIVIDE),
.CLKOUT2_DIVIDE (CLKOUT2_DIVIDE),
.CLKOUT3_DIVIDE (CLKOUT3_DIVIDE),
.MMCM_VCO (MMCM_VCO),
.MMCM_MULT_F (MMCM_MULT_F),
.MMCM_DIVCLK_DIVIDE (MMCM_DIVCLK_DIVIDE),
.RST_ACT_LOW (RST_ACT_LOW),
.tCK (tCK),
.MEM_TYPE (DRAM_TYPE)
)
u_ddr3_infrastructure
(
// Outputs
.rstdiv0 (rst),
.clk (clk),
.mem_refclk (mem_refclk),
.freq_refclk (freq_refclk),
.sync_pulse (sync_pulse),
.mmcm_ps_clk (mmcm_ps_clk),
.poc_sample_pd (poc_sample_pd),
.psdone (psdone),
.iddr_rst (iddr_rst),
.auxout_clk (),
.ui_addn_clk_0 (),
.ui_addn_clk_1 (),
.ui_addn_clk_2 (),
.ui_addn_clk_3 (),
.ui_addn_clk_4 (),
.pll_locked (pll_locked),
.mmcm_locked (),
.rst_phaser_ref (rst_phaser_ref),
// Inputs
.psen (psen),
.psincdec (psincdec),
.mmcm_clk (mmcm_clk),
.sys_rst (sys_rst_o),
.iodelay_ctrl_rdy (iodelay_ctrl_rdy),
.ref_dll_lock (ref_dll_lock)
);
mig_7series_v2_3_memc_ui_top_std #
(
.TCQ (TCQ),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.AL (AL),
.PAYLOAD_WIDTH (PAYLOAD_WIDTH),
.BANK_WIDTH (BANK_WIDTH),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.BURST_MODE (BURST_MODE),
.BURST_TYPE (BURST_TYPE),
.CA_MIRROR (CA_MIRROR),
.DDR3_VDD_OP_VOLT (VDD_OP_VOLT),
.CK_WIDTH (CK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CMD_PIPE_PLUS1 (CMD_PIPE_PLUS1),
.CS_WIDTH (CS_WIDTH),
.nCS_PER_RANK (nCS_PER_RANK),
.CKE_WIDTH (CKE_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DM_WIDTH (DM_WIDTH),
.DQ_CNT_WIDTH (DQ_CNT_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.DRAM_WIDTH (DRAM_WIDTH),
.ECC (ECC),
.ECC_WIDTH (ECC_WIDTH),
.ECC_TEST (ECC_TEST),
.MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH),
.REFCLK_FREQ (REFCLK_FREQ),
.nAL (nAL),
.nBANK_MACHS (nBANK_MACHS),
.CKE_ODT_AUX (CKE_ODT_AUX),
.nCK_PER_CLK (nCK_PER_CLK),
.ORDERING (ORDERING),
.OUTPUT_DRV (OUTPUT_DRV),
.IBUF_LPWR_MODE (IBUF_LPWR_MODE),
.DATA_IO_IDLE_PWRDWN (DATA_IO_IDLE_PWRDWN),
.BANK_TYPE (BANK_TYPE),
.DATA_IO_PRIM_TYPE (DATA_IO_PRIM_TYPE),
.IODELAY_GRP0 (IODELAY_GRP0),
.IODELAY_GRP1 (IODELAY_GRP1),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.REG_CTRL (REG_CTRL),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.CL (CL),
.CWL (CWL),
.tCK (tCK),
.tCKE (tCKE),
.tFAW (tFAW),
.tPRDI (tPRDI),
.tRAS (tRAS),
.tRCD (tRCD),
.tREFI (tREFI),
.tRFC (tRFC),
.tRP (tRP),
.tRRD (tRRD),
.tRTP (tRTP),
.tWTR (tWTR),
.tZQI (tZQI),
.tZQCS (tZQCS),
.USER_REFRESH (USER_REFRESH),
.TEMP_MON_EN (TEMP_MON_EN),
.WRLVL (WRLVL),
.DEBUG_PORT (DEBUG_PORT),
.CAL_WIDTH (CAL_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.ODT_WIDTH (ODT_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH),
.APP_DATA_WIDTH (APP_DATA_WIDTH),
.APP_MASK_WIDTH (APP_MASK_WIDTH),
.SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL),
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.PHY_0_BITLANES (PHY_0_BITLANES),
.PHY_1_BITLANES (PHY_1_BITLANES),
.PHY_2_BITLANES (PHY_2_BITLANES),
.CK_BYTE_MAP (CK_BYTE_MAP),
.ADDR_MAP (ADDR_MAP),
.BANK_MAP (BANK_MAP),
.CAS_MAP (CAS_MAP),
.CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP),
.CKE_MAP (CKE_MAP),
.ODT_MAP (ODT_MAP),
.CS_MAP (CS_MAP),
.PARITY_MAP (PARITY_MAP),
.RAS_MAP (RAS_MAP),
.WE_MAP (WE_MAP),
.DQS_BYTE_MAP (DQS_BYTE_MAP),
.DATA0_MAP (DATA0_MAP),
.DATA1_MAP (DATA1_MAP),
.DATA2_MAP (DATA2_MAP),
.DATA3_MAP (DATA3_MAP),
.DATA4_MAP (DATA4_MAP),
.DATA5_MAP (DATA5_MAP),
.DATA6_MAP (DATA6_MAP),
.DATA7_MAP (DATA7_MAP),
.DATA8_MAP (DATA8_MAP),
.DATA9_MAP (DATA9_MAP),
.DATA10_MAP (DATA10_MAP),
.DATA11_MAP (DATA11_MAP),
.DATA12_MAP (DATA12_MAP),
.DATA13_MAP (DATA13_MAP),
.DATA14_MAP (DATA14_MAP),
.DATA15_MAP (DATA15_MAP),
.DATA16_MAP (DATA16_MAP),
.DATA17_MAP (DATA17_MAP),
.MASK0_MAP (MASK0_MAP),
.MASK1_MAP (MASK1_MAP),
.CALIB_ROW_ADD (CALIB_ROW_ADD),
.CALIB_COL_ADD (CALIB_COL_ADD),
.CALIB_BA_ADD (CALIB_BA_ADD),
.IDELAY_ADJ (IDELAY_ADJ),
.FINE_PER_BIT (FINE_PER_BIT),
.CENTER_COMP_MODE (CENTER_COMP_MODE),
.PI_VAL_ADJ (PI_VAL_ADJ),
.SLOT_0_CONFIG (SLOT_0_CONFIG),
.SLOT_1_CONFIG (SLOT_1_CONFIG),
.MEM_ADDR_ORDER (MEM_ADDR_ORDER),
.STARVE_LIMIT (STARVE_LIMIT),
.USE_CS_PORT (USE_CS_PORT),
.USE_DM_PORT (USE_DM_PORT),
.USE_ODT_PORT (USE_ODT_PORT),
.MASTER_PHY_CTL (PHY_CONTROL_MASTER_BANK),
.TAPSPERKCLK (TAPSPERKCLK)
)
u_memc_ui_top_std
(
.clk (clk),
.clk_ref (clk_ref),
.mem_refclk (mem_refclk), //memory clock
.freq_refclk (freq_refclk),
.pll_lock (pll_locked),
.sync_pulse (sync_pulse),
.mmcm_ps_clk (mmcm_ps_clk),
.poc_sample_pd (poc_sample_pd),
.psdone (psdone),
.iddr_rst (iddr_rst),
.psen (psen),
.psincdec (psincdec),
.rst (rst),
.rst_phaser_ref (rst_phaser_ref),
.ref_dll_lock (ref_dll_lock),
// Memory interface ports
.ddr_dq (ddr3_dq),
.ddr_dqs_n (ddr3_dqs_n),
.ddr_dqs (ddr3_dqs_p),
.ddr_addr (ddr3_addr),
.ddr_ba (ddr3_ba),
.ddr_cas_n (ddr3_cas_n),
.ddr_ck_n (ddr3_ck_n),
.ddr_ck (ddr3_ck_p),
.ddr_cke (ddr3_cke),
.ddr_cs_n (ddr3_cs_n),
.ddr_dm (ddr3_dm),
.ddr_odt (ddr3_odt),
.ddr_ras_n (ddr3_ras_n),
.ddr_reset_n (ddr3_reset_n),
.ddr_parity (ddr3_parity),
.ddr_we_n (ddr3_we_n),
.bank_mach_next (bank_mach_next),
// Application interface ports
.app_addr (app_addr),
.app_cmd (app_cmd),
.app_en (app_en),
.app_hi_pri (1'b0),
.app_wdf_data (app_wdf_data),
.app_wdf_end (app_wdf_end),
.app_wdf_mask (app_wdf_mask),
.app_wdf_wren (app_wdf_wren),
.app_ecc_multiple_err (app_ecc_multiple_err),
.app_rd_data (app_rd_data),
.app_rd_data_end (app_rd_data_end),
.app_rd_data_valid (app_rd_data_valid),
.app_rdy (app_rdy),
.app_wdf_rdy (app_wdf_rdy),
.app_sr_req (app_sr_req),
.app_sr_active (app_sr_active),
.app_ref_req (app_ref_req),
.app_ref_ack (app_ref_ack),
.app_zq_req (app_zq_req),
.app_zq_ack (app_zq_ack),
.app_raw_not_ecc ({2*nCK_PER_CLK{1'b0}}),
.app_correct_en_i (1'b1),
.device_temp (device_temp),
// Debug logic ports
.dbg_idel_up_all (dbg_idel_up_all),
.dbg_idel_down_all (dbg_idel_down_all),
.dbg_idel_up_cpt (dbg_idel_up_cpt),
.dbg_idel_down_cpt (dbg_idel_down_cpt),
.dbg_sel_idel_cpt (dbg_sel_idel_cpt),
.dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt),
.dbg_sel_pi_incdec (dbg_sel_pi_incdec),
.dbg_sel_po_incdec (dbg_sel_po_incdec),
.dbg_byte_sel (dbg_byte_sel),
.dbg_pi_f_inc (dbg_pi_f_inc),
.dbg_pi_f_dec (dbg_pi_f_dec),
.dbg_po_f_inc (dbg_po_f_inc),
.dbg_po_f_stg23_sel (dbg_po_f_stg23_sel),
.dbg_po_f_dec (dbg_po_f_dec),
.dbg_cpt_tap_cnt (dbg_cpt_tap_cnt),
.dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt),
.dbg_calib_top (dbg_calib_top),
.dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt),
.dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt),
.dbg_rd_data_offset (dbg_rd_data_offset),
.dbg_phy_rdlvl (dbg_phy_rdlvl),
.dbg_phy_wrcal (dbg_phy_wrcal),
.dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt),
.dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt),
.dbg_rd_data_edge_detect (dbg_rd_data_edge_detect),
.dbg_rddata (dbg_rddata),
.dbg_rddata_valid (dbg_rddata_valid),
.dbg_rdlvl_done (dbg_rdlvl_done),
.dbg_rdlvl_err (dbg_rdlvl_err),
.dbg_rdlvl_start (dbg_rdlvl_start),
.dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt),
.dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt),
.dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl),
.dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid),
.dbg_wrlvl_done (dbg_wrlvl_done),
.dbg_wrlvl_err (dbg_wrlvl_err),
.dbg_wrlvl_start (dbg_wrlvl_start),
.dbg_phy_wrlvl (dbg_phy_wrlvl),
.dbg_phy_init (dbg_phy_init),
.dbg_prbs_rdlvl (dbg_prbs_rdlvl),
.dbg_pi_counter_read_val (dbg_pi_counter_read_val),
.dbg_po_counter_read_val (dbg_po_counter_read_val),
.dbg_prbs_final_dqs_tap_cnt_r (dbg_prbs_final_dqs_tap_cnt_r_int),
.dbg_prbs_first_edge_taps (dbg_prbs_first_edge_taps_int),
.dbg_prbs_second_edge_taps (dbg_prbs_second_edge_taps_int),
.dbg_pi_phaselock_start (dbg_pi_phaselock_start),
.dbg_pi_phaselocked_done (dbg_pi_phaselocked_done),
.dbg_pi_phaselock_err (dbg_pi_phaselock_err),
.dbg_pi_phase_locked_phy4lanes (dbg_pi_phase_locked_phy4lanes),
.dbg_pi_dqsfound_start (dbg_pi_dqsfound_start),
.dbg_pi_dqsfound_done (dbg_pi_dqsfound_done),
.dbg_pi_dqsfound_err (dbg_pi_dqsfound_err),
.dbg_pi_dqs_found_lanes_phy4lanes (dbg_pi_dqs_found_lanes_phy4lanes),
.dbg_calib_rd_data_offset_1 (dbg_calib_rd_data_offset_1),
.dbg_calib_rd_data_offset_2 (dbg_calib_rd_data_offset_2),
.dbg_data_offset (dbg_data_offset),
.dbg_data_offset_1 (dbg_data_offset_1),
.dbg_data_offset_2 (dbg_data_offset_2),
.dbg_wrcal_start (dbg_wrcal_start),
.dbg_wrcal_done (dbg_wrcal_done),
.dbg_wrcal_err (dbg_wrcal_err),
.dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal),
.dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data),
.dbg_oclkdelay_calib_start (dbg_oclkdelay_calib_start),
.dbg_oclkdelay_calib_done (dbg_oclkdelay_calib_done),
.dbg_dqs_found_cal (dbg_dqs_found_cal),
.init_calib_complete (init_calib_complete)
);
//*********************************************************************
// Resetting all RTL debug inputs as the debug ports are not enabled
//*********************************************************************
assign dbg_idel_down_all = 1'b0;
assign dbg_idel_down_cpt = 1'b0;
assign dbg_idel_up_all = 1'b0;
assign dbg_idel_up_cpt = 1'b0;
assign dbg_sel_all_idel_cpt = 1'b0;
assign dbg_sel_idel_cpt = 'b0;
assign dbg_byte_sel = 'd0;
assign dbg_sel_pi_incdec = 1'b0;
assign dbg_pi_f_inc = 1'b0;
assign dbg_pi_f_dec = 1'b0;
assign dbg_po_f_inc = 'b0;
assign dbg_po_f_dec = 'b0;
assign dbg_po_f_stg23_sel = 'b0;
assign dbg_sel_po_incdec = 'b0;
endmodule
|
// ==================================================================
// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ------------------------------------------------------------------
// Copyright (c) 2013 by Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// ------------------------------------------------------------------
//
// Permission:
//
// Lattice SG Pte. Ltd. grants permission to use this code
// pursuant to the terms of the Lattice Reference Design License Agreement.
//
//
// Disclaimer:
//
// This VHDL or Verilog source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Lattice provides no warranty
// regarding the use or functionality of this code.
//
// --------------------------------------------------------------------
//
// Lattice SG Pte. Ltd.
// 101 Thomson Road, United Square #07-02
// Singapore 307591
//
//
// TEL: 1-800-Lattice (USA and Canada)
// +65-6631-2000 (Singapore)
// +1-503-268-8001 (other locations)
//
// web: http://www.latticesemi.com/
// email: [email protected]
//
// --------------------------------------------------------------------
//
`timescale 1 ns / 1 ps
module delay_gen150us (/*AUTOARG*/
// Outputs
o_lfsr_256_done,
// Inputs
i_sys_rst, i_sys_clk
);
input i_sys_clk; // To U1 of lfsr_count64.v, ...
input i_sys_rst; // To U1 of lfsr_count64.v, ...
output o_lfsr_256_done; // From U5 of lfsr_count256.v
wire lfsr_64_done_i; // From U1 of lfsr_count64.v
lfsr_count64 U1(/*AUTOINST*/
// Outputs
.o_lfsr_64_done (lfsr_64_done_i),
// Inputs
.i_sys_clk (i_sys_clk),
.i_sys_rst (i_sys_rst));
lfsr_count255 U5(/*AUTOINST*/
// Outputs
.o_lfsr_256_done (o_lfsr_256_done),
// Inputs
.i_sys_clk (lfsr_64_done_i),
.i_sys_rst (i_sys_rst));
endmodule // delay_gen150us
|
/*
*******************************************************************************
*
* FIFO Generator - Verilog Behavioral Model
*
*******************************************************************************
*
* (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information
* of Xilinx, Inc. and is protected under U.S. and
* international copyright and other intellectual property
* laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any
* rights to the materials distributed herewith. Except as
* otherwise provided in a valid license issued to you by
* Xilinx, and to the maximum extent permitted by applicable
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
* (2) Xilinx shall not be liable (whether in contract or tort,
* including negligence, or under any other theory of
* liability) for any loss or damage of any kind or nature
* related to, arising under or in connection with these
* materials, including for any direct, or any indirect,
* special, incidental, or consequential loss or damage
* (including loss of data, profits, goodwill, or any type of
* loss or damage suffered as a result of any action brought
* by a third party) even if such damage or loss was
* reasonably foreseeable or Xilinx had been advised of the
* possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-
* safe, or for use in any application requiring fail-safe
* performance, such as life-support or safety devices or
* systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any
* other applications that could lead to death, personal
* injury, or severe property or environmental damage
* (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and
* liability of any use of Xilinx products in Critical
* Applications, subject only to applicable laws and
* regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
* PART OF THIS FILE AT ALL TIMES.
*
*******************************************************************************
*******************************************************************************
*
* Filename: fifo_generator_vlog_beh.v
*
* Author : Xilinx
*
*******************************************************************************
* Structure:
*
* fifo_generator_vlog_beh.v
* |
* +-fifo_generator_v13_1_3_bhv_ver_as
* |
* +-fifo_generator_v13_1_3_bhv_ver_ss
* |
* +-fifo_generator_v13_1_3_bhv_ver_preload0
*
*******************************************************************************
* Description:
*
* The Verilog behavioral model for the FIFO Generator.
*
* The behavioral model has three parts:
* - The behavioral model for independent clocks FIFOs (_as)
* - The behavioral model for common clock FIFOs (_ss)
* - The "preload logic" block which implements First-word Fall-through
*
*******************************************************************************
* Description:
* The verilog behavioral model for the FIFO generator core.
*
*******************************************************************************
*/
`timescale 1ps/1ps
`ifndef TCQ
`define TCQ 100
`endif
/*******************************************************************************
* Declaration of top-level module
******************************************************************************/
module fifo_generator_vlog_beh
#(
//-----------------------------------------------------------------------
// Generic Declarations
//-----------------------------------------------------------------------
parameter C_COMMON_CLOCK = 0,
parameter C_COUNT_TYPE = 0,
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DEFAULT_VALUE = "",
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_ENABLE_RLOCS = 0,
parameter C_FAMILY = "",
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_BACKUP = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_INT_CLK = 0,
parameter C_HAS_MEMINIT_FILE = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RD_RST = 0,
parameter C_HAS_RST = 1,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_HAS_WR_RST = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_INIT_WR_PNTR_VAL = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_MIF_FILE_NAME = "",
parameter C_OPTIMIZATION_MODE = 0,
parameter C_OVERFLOW_LOW = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PRIM_FIFO_TYPE = "4kx4",
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_FREQ = 1,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_USE_PIPELINE_REG = 0,
parameter C_POWER_SAVING_MODE = 0,
parameter C_USE_FIFO16_FLAGS = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_FREQ = 1,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_WR_RESPONSE_LATENCY = 1,
parameter C_MSGON_VAL = 1,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2,
// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0, // 0: Native Interface, 1: AXI4 Stream, 2: AXI4/AXI3
parameter C_AXI_TYPE = 0, // 1: AXI4, 2: AXI4 Lite, 3: AXI3
parameter C_HAS_AXI_WR_CHANNEL = 0,
parameter C_HAS_AXI_RD_CHANNEL = 0,
parameter C_HAS_SLAVE_CE = 0,
parameter C_HAS_MASTER_CE = 0,
parameter C_ADD_NGC_CONSTRAINT = 0,
parameter C_USE_COMMON_UNDERFLOW = 0,
parameter C_USE_COMMON_OVERFLOW = 0,
parameter C_USE_DEFAULT_SETTINGS = 0,
// AXI Full/Lite
parameter C_AXI_ID_WIDTH = 0,
parameter C_AXI_ADDR_WIDTH = 0,
parameter C_AXI_DATA_WIDTH = 0,
parameter C_AXI_LEN_WIDTH = 8,
parameter C_AXI_LOCK_WIDTH = 2,
parameter C_HAS_AXI_ID = 0,
parameter C_HAS_AXI_AWUSER = 0,
parameter C_HAS_AXI_WUSER = 0,
parameter C_HAS_AXI_BUSER = 0,
parameter C_HAS_AXI_ARUSER = 0,
parameter C_HAS_AXI_RUSER = 0,
parameter C_AXI_ARUSER_WIDTH = 0,
parameter C_AXI_AWUSER_WIDTH = 0,
parameter C_AXI_WUSER_WIDTH = 0,
parameter C_AXI_BUSER_WIDTH = 0,
parameter C_AXI_RUSER_WIDTH = 0,
// AXI Streaming
parameter C_HAS_AXIS_TDATA = 0,
parameter C_HAS_AXIS_TID = 0,
parameter C_HAS_AXIS_TDEST = 0,
parameter C_HAS_AXIS_TUSER = 0,
parameter C_HAS_AXIS_TREADY = 0,
parameter C_HAS_AXIS_TLAST = 0,
parameter C_HAS_AXIS_TSTRB = 0,
parameter C_HAS_AXIS_TKEEP = 0,
parameter C_AXIS_TDATA_WIDTH = 1,
parameter C_AXIS_TID_WIDTH = 1,
parameter C_AXIS_TDEST_WIDTH = 1,
parameter C_AXIS_TUSER_WIDTH = 1,
parameter C_AXIS_TSTRB_WIDTH = 1,
parameter C_AXIS_TKEEP_WIDTH = 1,
// AXI Channel Type
// WACH --> Write Address Channel
// WDCH --> Write Data Channel
// WRCH --> Write Response Channel
// RACH --> Read Address Channel
// RDCH --> Read Data Channel
// AXIS --> AXI Streaming
parameter C_WACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logic
parameter C_WDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_WRCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_RACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_RDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_AXIS_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
// AXI Implementation Type
// 1 = Common Clock Block RAM FIFO
// 2 = Common Clock Distributed RAM FIFO
// 11 = Independent Clock Block RAM FIFO
// 12 = Independent Clock Distributed RAM FIFO
parameter C_IMPLEMENTATION_TYPE_WACH = 0,
parameter C_IMPLEMENTATION_TYPE_WDCH = 0,
parameter C_IMPLEMENTATION_TYPE_WRCH = 0,
parameter C_IMPLEMENTATION_TYPE_RACH = 0,
parameter C_IMPLEMENTATION_TYPE_RDCH = 0,
parameter C_IMPLEMENTATION_TYPE_AXIS = 0,
// AXI FIFO Type
// 0 = Data FIFO
// 1 = Packet FIFO
// 2 = Low Latency Sync FIFO
// 3 = Low Latency Async FIFO
parameter C_APPLICATION_TYPE_WACH = 0,
parameter C_APPLICATION_TYPE_WDCH = 0,
parameter C_APPLICATION_TYPE_WRCH = 0,
parameter C_APPLICATION_TYPE_RACH = 0,
parameter C_APPLICATION_TYPE_RDCH = 0,
parameter C_APPLICATION_TYPE_AXIS = 0,
// AXI Built-in FIFO Primitive Type
// 512x36, 1kx18, 2kx9, 4kx4, etc
parameter C_PRIM_FIFO_TYPE_WACH = "512x36",
parameter C_PRIM_FIFO_TYPE_WDCH = "512x36",
parameter C_PRIM_FIFO_TYPE_WRCH = "512x36",
parameter C_PRIM_FIFO_TYPE_RACH = "512x36",
parameter C_PRIM_FIFO_TYPE_RDCH = "512x36",
parameter C_PRIM_FIFO_TYPE_AXIS = "512x36",
// Enable ECC
// 0 = ECC disabled
// 1 = ECC enabled
parameter C_USE_ECC_WACH = 0,
parameter C_USE_ECC_WDCH = 0,
parameter C_USE_ECC_WRCH = 0,
parameter C_USE_ECC_RACH = 0,
parameter C_USE_ECC_RDCH = 0,
parameter C_USE_ECC_AXIS = 0,
// ECC Error Injection Type
// 0 = No Error Injection
// 1 = Single Bit Error Injection
// 2 = Double Bit Error Injection
// 3 = Single Bit and Double Bit Error Injection
parameter C_ERROR_INJECTION_TYPE_WACH = 0,
parameter C_ERROR_INJECTION_TYPE_WDCH = 0,
parameter C_ERROR_INJECTION_TYPE_WRCH = 0,
parameter C_ERROR_INJECTION_TYPE_RACH = 0,
parameter C_ERROR_INJECTION_TYPE_RDCH = 0,
parameter C_ERROR_INJECTION_TYPE_AXIS = 0,
// Input Data Width
// Accumulation of all AXI input signal's width
parameter C_DIN_WIDTH_WACH = 1,
parameter C_DIN_WIDTH_WDCH = 1,
parameter C_DIN_WIDTH_WRCH = 1,
parameter C_DIN_WIDTH_RACH = 1,
parameter C_DIN_WIDTH_RDCH = 1,
parameter C_DIN_WIDTH_AXIS = 1,
parameter C_WR_DEPTH_WACH = 16,
parameter C_WR_DEPTH_WDCH = 16,
parameter C_WR_DEPTH_WRCH = 16,
parameter C_WR_DEPTH_RACH = 16,
parameter C_WR_DEPTH_RDCH = 16,
parameter C_WR_DEPTH_AXIS = 16,
parameter C_WR_PNTR_WIDTH_WACH = 4,
parameter C_WR_PNTR_WIDTH_WDCH = 4,
parameter C_WR_PNTR_WIDTH_WRCH = 4,
parameter C_WR_PNTR_WIDTH_RACH = 4,
parameter C_WR_PNTR_WIDTH_RDCH = 4,
parameter C_WR_PNTR_WIDTH_AXIS = 4,
parameter C_HAS_DATA_COUNTS_WACH = 0,
parameter C_HAS_DATA_COUNTS_WDCH = 0,
parameter C_HAS_DATA_COUNTS_WRCH = 0,
parameter C_HAS_DATA_COUNTS_RACH = 0,
parameter C_HAS_DATA_COUNTS_RDCH = 0,
parameter C_HAS_DATA_COUNTS_AXIS = 0,
parameter C_HAS_PROG_FLAGS_WACH = 0,
parameter C_HAS_PROG_FLAGS_WDCH = 0,
parameter C_HAS_PROG_FLAGS_WRCH = 0,
parameter C_HAS_PROG_FLAGS_RACH = 0,
parameter C_HAS_PROG_FLAGS_RDCH = 0,
parameter C_HAS_PROG_FLAGS_AXIS = 0,
parameter C_PROG_FULL_TYPE_WACH = 0,
parameter C_PROG_FULL_TYPE_WDCH = 0,
parameter C_PROG_FULL_TYPE_WRCH = 0,
parameter C_PROG_FULL_TYPE_RACH = 0,
parameter C_PROG_FULL_TYPE_RDCH = 0,
parameter C_PROG_FULL_TYPE_AXIS = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = 0,
parameter C_PROG_EMPTY_TYPE_WACH = 0,
parameter C_PROG_EMPTY_TYPE_WDCH = 0,
parameter C_PROG_EMPTY_TYPE_WRCH = 0,
parameter C_PROG_EMPTY_TYPE_RACH = 0,
parameter C_PROG_EMPTY_TYPE_RDCH = 0,
parameter C_PROG_EMPTY_TYPE_AXIS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = 0,
parameter C_REG_SLICE_MODE_WACH = 0,
parameter C_REG_SLICE_MODE_WDCH = 0,
parameter C_REG_SLICE_MODE_WRCH = 0,
parameter C_REG_SLICE_MODE_RACH = 0,
parameter C_REG_SLICE_MODE_RDCH = 0,
parameter C_REG_SLICE_MODE_AXIS = 0
)
(
//------------------------------------------------------------------------------
// Input and Output Declarations
//------------------------------------------------------------------------------
// Conventional FIFO Interface Signals
input backup,
input backup_marker,
input clk,
input rst,
input srst,
input wr_clk,
input wr_rst,
input rd_clk,
input rd_rst,
input [C_DIN_WIDTH-1:0] din,
input wr_en,
input rd_en,
// Optional inputs
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh,
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert,
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate,
input int_clk,
input injectdbiterr,
input injectsbiterr,
input sleep,
output [C_DOUT_WIDTH-1:0] dout,
output full,
output almost_full,
output wr_ack,
output overflow,
output empty,
output almost_empty,
output valid,
output underflow,
output [C_DATA_COUNT_WIDTH-1:0] data_count,
output [C_RD_DATA_COUNT_WIDTH-1:0] rd_data_count,
output [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count,
output prog_full,
output prog_empty,
output sbiterr,
output dbiterr,
output wr_rst_busy,
output rd_rst_busy,
// AXI Global Signal
input m_aclk,
input s_aclk,
input s_aresetn,
input s_aclk_en,
input m_aclk_en,
// AXI Full/Lite Slave Write Channel (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input [C_AXI_LEN_WIDTH-1:0] s_axi_awlen,
input [3-1:0] s_axi_awsize,
input [2-1:0] s_axi_awburst,
input [C_AXI_LOCK_WIDTH-1:0] s_axi_awlock,
input [4-1:0] s_axi_awcache,
input [3-1:0] s_axi_awprot,
input [4-1:0] s_axi_awqos,
input [4-1:0] s_axi_awregion,
input [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
input s_axi_awvalid,
output s_axi_awready,
input [C_AXI_ID_WIDTH-1:0] s_axi_wid,
input [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input s_axi_wlast,
input [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
input s_axi_wvalid,
output s_axi_wready,
output [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output [2-1:0] s_axi_bresp,
output [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
output s_axi_bvalid,
input s_axi_bready,
// AXI Full/Lite Master Write Channel (read side)
output [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output [C_AXI_LEN_WIDTH-1:0] m_axi_awlen,
output [3-1:0] m_axi_awsize,
output [2-1:0] m_axi_awburst,
output [C_AXI_LOCK_WIDTH-1:0] m_axi_awlock,
output [4-1:0] m_axi_awcache,
output [3-1:0] m_axi_awprot,
output [4-1:0] m_axi_awqos,
output [4-1:0] m_axi_awregion,
output [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
output m_axi_awvalid,
input m_axi_awready,
output [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output m_axi_wlast,
output [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
output m_axi_wvalid,
input m_axi_wready,
input [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input [2-1:0] m_axi_bresp,
input [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
input m_axi_bvalid,
output m_axi_bready,
// AXI Full/Lite Slave Read Channel (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input [C_AXI_LEN_WIDTH-1:0] s_axi_arlen,
input [3-1:0] s_axi_arsize,
input [2-1:0] s_axi_arburst,
input [C_AXI_LOCK_WIDTH-1:0] s_axi_arlock,
input [4-1:0] s_axi_arcache,
input [3-1:0] s_axi_arprot,
input [4-1:0] s_axi_arqos,
input [4-1:0] s_axi_arregion,
input [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
input s_axi_arvalid,
output s_axi_arready,
output [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output [2-1:0] s_axi_rresp,
output s_axi_rlast,
output [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
output s_axi_rvalid,
input s_axi_rready,
// AXI Full/Lite Master Read Channel (read side)
output [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output [C_AXI_LEN_WIDTH-1:0] m_axi_arlen,
output [3-1:0] m_axi_arsize,
output [2-1:0] m_axi_arburst,
output [C_AXI_LOCK_WIDTH-1:0] m_axi_arlock,
output [4-1:0] m_axi_arcache,
output [3-1:0] m_axi_arprot,
output [4-1:0] m_axi_arqos,
output [4-1:0] m_axi_arregion,
output [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output m_axi_arvalid,
input m_axi_arready,
input [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input [2-1:0] m_axi_rresp,
input m_axi_rlast,
input [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input m_axi_rvalid,
output m_axi_rready,
// AXI Streaming Slave Signals (Write side)
input s_axis_tvalid,
output s_axis_tready,
input [C_AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input [C_AXIS_TSTRB_WIDTH-1:0] s_axis_tstrb,
input [C_AXIS_TKEEP_WIDTH-1:0] s_axis_tkeep,
input s_axis_tlast,
input [C_AXIS_TID_WIDTH-1:0] s_axis_tid,
input [C_AXIS_TDEST_WIDTH-1:0] s_axis_tdest,
input [C_AXIS_TUSER_WIDTH-1:0] s_axis_tuser,
// AXI Streaming Master Signals (Read side)
output m_axis_tvalid,
input m_axis_tready,
output [C_AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output [C_AXIS_TSTRB_WIDTH-1:0] m_axis_tstrb,
output [C_AXIS_TKEEP_WIDTH-1:0] m_axis_tkeep,
output m_axis_tlast,
output [C_AXIS_TID_WIDTH-1:0] m_axis_tid,
output [C_AXIS_TDEST_WIDTH-1:0] m_axis_tdest,
output [C_AXIS_TUSER_WIDTH-1:0] m_axis_tuser,
// AXI Full/Lite Write Address Channel signals
input axi_aw_injectsbiterr,
input axi_aw_injectdbiterr,
input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_data_count,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_wr_data_count,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_rd_data_count,
output axi_aw_sbiterr,
output axi_aw_dbiterr,
output axi_aw_overflow,
output axi_aw_underflow,
output axi_aw_prog_full,
output axi_aw_prog_empty,
// AXI Full/Lite Write Data Channel signals
input axi_w_injectsbiterr,
input axi_w_injectdbiterr,
input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_data_count,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_wr_data_count,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_rd_data_count,
output axi_w_sbiterr,
output axi_w_dbiterr,
output axi_w_overflow,
output axi_w_underflow,
output axi_w_prog_full,
output axi_w_prog_empty,
// AXI Full/Lite Write Response Channel signals
input axi_b_injectsbiterr,
input axi_b_injectdbiterr,
input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_data_count,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_wr_data_count,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_rd_data_count,
output axi_b_sbiterr,
output axi_b_dbiterr,
output axi_b_overflow,
output axi_b_underflow,
output axi_b_prog_full,
output axi_b_prog_empty,
// AXI Full/Lite Read Address Channel signals
input axi_ar_injectsbiterr,
input axi_ar_injectdbiterr,
input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_full_thresh,
input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_data_count,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_wr_data_count,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_rd_data_count,
output axi_ar_sbiterr,
output axi_ar_dbiterr,
output axi_ar_overflow,
output axi_ar_underflow,
output axi_ar_prog_full,
output axi_ar_prog_empty,
// AXI Full/Lite Read Data Channel Signals
input axi_r_injectsbiterr,
input axi_r_injectdbiterr,
input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_full_thresh,
input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_data_count,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_wr_data_count,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_rd_data_count,
output axi_r_sbiterr,
output axi_r_dbiterr,
output axi_r_overflow,
output axi_r_underflow,
output axi_r_prog_full,
output axi_r_prog_empty,
// AXI Streaming FIFO Related Signals
input axis_injectsbiterr,
input axis_injectdbiterr,
input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_full_thresh,
input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_data_count,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_wr_data_count,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_rd_data_count,
output axis_sbiterr,
output axis_dbiterr,
output axis_overflow,
output axis_underflow,
output axis_prog_full,
output axis_prog_empty
);
wire BACKUP;
wire BACKUP_MARKER;
wire CLK;
wire RST;
wire SRST;
wire WR_CLK;
wire WR_RST;
wire RD_CLK;
wire RD_RST;
wire [C_DIN_WIDTH-1:0] DIN;
wire WR_EN;
wire RD_EN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire INT_CLK;
wire INJECTDBITERR;
wire INJECTSBITERR;
wire SLEEP;
wire [C_DOUT_WIDTH-1:0] DOUT;
wire FULL;
wire ALMOST_FULL;
wire WR_ACK;
wire OVERFLOW;
wire EMPTY;
wire ALMOST_EMPTY;
wire VALID;
wire UNDERFLOW;
wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT;
wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT;
wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT;
wire PROG_FULL;
wire PROG_EMPTY;
wire SBITERR;
wire DBITERR;
wire WR_RST_BUSY;
wire RD_RST_BUSY;
wire M_ACLK;
wire S_ACLK;
wire S_ARESETN;
wire S_ACLK_EN;
wire M_ACLK_EN;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID;
wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR;
wire [C_AXI_LEN_WIDTH-1:0] S_AXI_AWLEN;
wire [3-1:0] S_AXI_AWSIZE;
wire [2-1:0] S_AXI_AWBURST;
wire [C_AXI_LOCK_WIDTH-1:0] S_AXI_AWLOCK;
wire [4-1:0] S_AXI_AWCACHE;
wire [3-1:0] S_AXI_AWPROT;
wire [4-1:0] S_AXI_AWQOS;
wire [4-1:0] S_AXI_AWREGION;
wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER;
wire S_AXI_AWVALID;
wire S_AXI_AWREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID;
wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA;
wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB;
wire S_AXI_WLAST;
wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER;
wire S_AXI_WVALID;
wire S_AXI_WREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID;
wire [2-1:0] S_AXI_BRESP;
wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER;
wire S_AXI_BVALID;
wire S_AXI_BREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID;
wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR;
wire [C_AXI_LEN_WIDTH-1:0] M_AXI_AWLEN;
wire [3-1:0] M_AXI_AWSIZE;
wire [2-1:0] M_AXI_AWBURST;
wire [C_AXI_LOCK_WIDTH-1:0] M_AXI_AWLOCK;
wire [4-1:0] M_AXI_AWCACHE;
wire [3-1:0] M_AXI_AWPROT;
wire [4-1:0] M_AXI_AWQOS;
wire [4-1:0] M_AXI_AWREGION;
wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER;
wire M_AXI_AWVALID;
wire M_AXI_AWREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID;
wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA;
wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB;
wire M_AXI_WLAST;
wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER;
wire M_AXI_WVALID;
wire M_AXI_WREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID;
wire [2-1:0] M_AXI_BRESP;
wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER;
wire M_AXI_BVALID;
wire M_AXI_BREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID;
wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR;
wire [C_AXI_LEN_WIDTH-1:0] S_AXI_ARLEN;
wire [3-1:0] S_AXI_ARSIZE;
wire [2-1:0] S_AXI_ARBURST;
wire [C_AXI_LOCK_WIDTH-1:0] S_AXI_ARLOCK;
wire [4-1:0] S_AXI_ARCACHE;
wire [3-1:0] S_AXI_ARPROT;
wire [4-1:0] S_AXI_ARQOS;
wire [4-1:0] S_AXI_ARREGION;
wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER;
wire S_AXI_ARVALID;
wire S_AXI_ARREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID;
wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA;
wire [2-1:0] S_AXI_RRESP;
wire S_AXI_RLAST;
wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER;
wire S_AXI_RVALID;
wire S_AXI_RREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID;
wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR;
wire [C_AXI_LEN_WIDTH-1:0] M_AXI_ARLEN;
wire [3-1:0] M_AXI_ARSIZE;
wire [2-1:0] M_AXI_ARBURST;
wire [C_AXI_LOCK_WIDTH-1:0] M_AXI_ARLOCK;
wire [4-1:0] M_AXI_ARCACHE;
wire [3-1:0] M_AXI_ARPROT;
wire [4-1:0] M_AXI_ARQOS;
wire [4-1:0] M_AXI_ARREGION;
wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER;
wire M_AXI_ARVALID;
wire M_AXI_ARREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID;
wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA;
wire [2-1:0] M_AXI_RRESP;
wire M_AXI_RLAST;
wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER;
wire M_AXI_RVALID;
wire M_AXI_RREADY;
wire S_AXIS_TVALID;
wire S_AXIS_TREADY;
wire [C_AXIS_TDATA_WIDTH-1:0] S_AXIS_TDATA;
wire [C_AXIS_TSTRB_WIDTH-1:0] S_AXIS_TSTRB;
wire [C_AXIS_TKEEP_WIDTH-1:0] S_AXIS_TKEEP;
wire S_AXIS_TLAST;
wire [C_AXIS_TID_WIDTH-1:0] S_AXIS_TID;
wire [C_AXIS_TDEST_WIDTH-1:0] S_AXIS_TDEST;
wire [C_AXIS_TUSER_WIDTH-1:0] S_AXIS_TUSER;
wire M_AXIS_TVALID;
wire M_AXIS_TREADY;
wire [C_AXIS_TDATA_WIDTH-1:0] M_AXIS_TDATA;
wire [C_AXIS_TSTRB_WIDTH-1:0] M_AXIS_TSTRB;
wire [C_AXIS_TKEEP_WIDTH-1:0] M_AXIS_TKEEP;
wire M_AXIS_TLAST;
wire [C_AXIS_TID_WIDTH-1:0] M_AXIS_TID;
wire [C_AXIS_TDEST_WIDTH-1:0] M_AXIS_TDEST;
wire [C_AXIS_TUSER_WIDTH-1:0] M_AXIS_TUSER;
wire AXI_AW_INJECTSBITERR;
wire AXI_AW_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_RD_DATA_COUNT;
wire AXI_AW_SBITERR;
wire AXI_AW_DBITERR;
wire AXI_AW_OVERFLOW;
wire AXI_AW_UNDERFLOW;
wire AXI_AW_PROG_FULL;
wire AXI_AW_PROG_EMPTY;
wire AXI_W_INJECTSBITERR;
wire AXI_W_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_RD_DATA_COUNT;
wire AXI_W_SBITERR;
wire AXI_W_DBITERR;
wire AXI_W_OVERFLOW;
wire AXI_W_UNDERFLOW;
wire AXI_W_PROG_FULL;
wire AXI_W_PROG_EMPTY;
wire AXI_B_INJECTSBITERR;
wire AXI_B_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_RD_DATA_COUNT;
wire AXI_B_SBITERR;
wire AXI_B_DBITERR;
wire AXI_B_OVERFLOW;
wire AXI_B_UNDERFLOW;
wire AXI_B_PROG_FULL;
wire AXI_B_PROG_EMPTY;
wire AXI_AR_INJECTSBITERR;
wire AXI_AR_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_RD_DATA_COUNT;
wire AXI_AR_SBITERR;
wire AXI_AR_DBITERR;
wire AXI_AR_OVERFLOW;
wire AXI_AR_UNDERFLOW;
wire AXI_AR_PROG_FULL;
wire AXI_AR_PROG_EMPTY;
wire AXI_R_INJECTSBITERR;
wire AXI_R_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_RD_DATA_COUNT;
wire AXI_R_SBITERR;
wire AXI_R_DBITERR;
wire AXI_R_OVERFLOW;
wire AXI_R_UNDERFLOW;
wire AXI_R_PROG_FULL;
wire AXI_R_PROG_EMPTY;
wire AXIS_INJECTSBITERR;
wire AXIS_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_RD_DATA_COUNT;
wire AXIS_SBITERR;
wire AXIS_DBITERR;
wire AXIS_OVERFLOW;
wire AXIS_UNDERFLOW;
wire AXIS_PROG_FULL;
wire AXIS_PROG_EMPTY;
wire [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count_in;
wire wr_rst_int;
wire rd_rst_int;
wire wr_rst_busy_o;
wire wr_rst_busy_ntve;
wire wr_rst_busy_axis;
wire wr_rst_busy_wach;
wire wr_rst_busy_wdch;
wire wr_rst_busy_wrch;
wire wr_rst_busy_rach;
wire wr_rst_busy_rdch;
function integer find_log2;
input integer int_val;
integer i,j;
begin
i = 1;
j = 0;
for (i = 1; i < int_val; i = i*2) begin
j = j + 1;
end
find_log2 = j;
end
endfunction
// Conventional FIFO Interface Signals
assign BACKUP = backup;
assign BACKUP_MARKER = backup_marker;
assign CLK = clk;
assign RST = rst;
assign SRST = srst;
assign WR_CLK = wr_clk;
assign WR_RST = wr_rst;
assign RD_CLK = rd_clk;
assign RD_RST = rd_rst;
assign WR_EN = wr_en;
assign RD_EN = rd_en;
assign INT_CLK = int_clk;
assign INJECTDBITERR = injectdbiterr;
assign INJECTSBITERR = injectsbiterr;
assign SLEEP = sleep;
assign full = FULL;
assign almost_full = ALMOST_FULL;
assign wr_ack = WR_ACK;
assign overflow = OVERFLOW;
assign empty = EMPTY;
assign almost_empty = ALMOST_EMPTY;
assign valid = VALID;
assign underflow = UNDERFLOW;
assign prog_full = PROG_FULL;
assign prog_empty = PROG_EMPTY;
assign sbiterr = SBITERR;
assign dbiterr = DBITERR;
// assign wr_rst_busy = WR_RST_BUSY | wr_rst_busy_o;
assign wr_rst_busy = wr_rst_busy_o;
assign rd_rst_busy = RD_RST_BUSY;
assign M_ACLK = m_aclk;
assign S_ACLK = s_aclk;
assign S_ARESETN = s_aresetn;
assign S_ACLK_EN = s_aclk_en;
assign M_ACLK_EN = m_aclk_en;
assign S_AXI_AWVALID = s_axi_awvalid;
assign s_axi_awready = S_AXI_AWREADY;
assign S_AXI_WLAST = s_axi_wlast;
assign S_AXI_WVALID = s_axi_wvalid;
assign s_axi_wready = S_AXI_WREADY;
assign s_axi_bvalid = S_AXI_BVALID;
assign S_AXI_BREADY = s_axi_bready;
assign m_axi_awvalid = M_AXI_AWVALID;
assign M_AXI_AWREADY = m_axi_awready;
assign m_axi_wlast = M_AXI_WLAST;
assign m_axi_wvalid = M_AXI_WVALID;
assign M_AXI_WREADY = m_axi_wready;
assign M_AXI_BVALID = m_axi_bvalid;
assign m_axi_bready = M_AXI_BREADY;
assign S_AXI_ARVALID = s_axi_arvalid;
assign s_axi_arready = S_AXI_ARREADY;
assign s_axi_rlast = S_AXI_RLAST;
assign s_axi_rvalid = S_AXI_RVALID;
assign S_AXI_RREADY = s_axi_rready;
assign m_axi_arvalid = M_AXI_ARVALID;
assign M_AXI_ARREADY = m_axi_arready;
assign M_AXI_RLAST = m_axi_rlast;
assign M_AXI_RVALID = m_axi_rvalid;
assign m_axi_rready = M_AXI_RREADY;
assign S_AXIS_TVALID = s_axis_tvalid;
assign s_axis_tready = S_AXIS_TREADY;
assign S_AXIS_TLAST = s_axis_tlast;
assign m_axis_tvalid = M_AXIS_TVALID;
assign M_AXIS_TREADY = m_axis_tready;
assign m_axis_tlast = M_AXIS_TLAST;
assign AXI_AW_INJECTSBITERR = axi_aw_injectsbiterr;
assign AXI_AW_INJECTDBITERR = axi_aw_injectdbiterr;
assign axi_aw_sbiterr = AXI_AW_SBITERR;
assign axi_aw_dbiterr = AXI_AW_DBITERR;
assign axi_aw_overflow = AXI_AW_OVERFLOW;
assign axi_aw_underflow = AXI_AW_UNDERFLOW;
assign axi_aw_prog_full = AXI_AW_PROG_FULL;
assign axi_aw_prog_empty = AXI_AW_PROG_EMPTY;
assign AXI_W_INJECTSBITERR = axi_w_injectsbiterr;
assign AXI_W_INJECTDBITERR = axi_w_injectdbiterr;
assign axi_w_sbiterr = AXI_W_SBITERR;
assign axi_w_dbiterr = AXI_W_DBITERR;
assign axi_w_overflow = AXI_W_OVERFLOW;
assign axi_w_underflow = AXI_W_UNDERFLOW;
assign axi_w_prog_full = AXI_W_PROG_FULL;
assign axi_w_prog_empty = AXI_W_PROG_EMPTY;
assign AXI_B_INJECTSBITERR = axi_b_injectsbiterr;
assign AXI_B_INJECTDBITERR = axi_b_injectdbiterr;
assign axi_b_sbiterr = AXI_B_SBITERR;
assign axi_b_dbiterr = AXI_B_DBITERR;
assign axi_b_overflow = AXI_B_OVERFLOW;
assign axi_b_underflow = AXI_B_UNDERFLOW;
assign axi_b_prog_full = AXI_B_PROG_FULL;
assign axi_b_prog_empty = AXI_B_PROG_EMPTY;
assign AXI_AR_INJECTSBITERR = axi_ar_injectsbiterr;
assign AXI_AR_INJECTDBITERR = axi_ar_injectdbiterr;
assign axi_ar_sbiterr = AXI_AR_SBITERR;
assign axi_ar_dbiterr = AXI_AR_DBITERR;
assign axi_ar_overflow = AXI_AR_OVERFLOW;
assign axi_ar_underflow = AXI_AR_UNDERFLOW;
assign axi_ar_prog_full = AXI_AR_PROG_FULL;
assign axi_ar_prog_empty = AXI_AR_PROG_EMPTY;
assign AXI_R_INJECTSBITERR = axi_r_injectsbiterr;
assign AXI_R_INJECTDBITERR = axi_r_injectdbiterr;
assign axi_r_sbiterr = AXI_R_SBITERR;
assign axi_r_dbiterr = AXI_R_DBITERR;
assign axi_r_overflow = AXI_R_OVERFLOW;
assign axi_r_underflow = AXI_R_UNDERFLOW;
assign axi_r_prog_full = AXI_R_PROG_FULL;
assign axi_r_prog_empty = AXI_R_PROG_EMPTY;
assign AXIS_INJECTSBITERR = axis_injectsbiterr;
assign AXIS_INJECTDBITERR = axis_injectdbiterr;
assign axis_sbiterr = AXIS_SBITERR;
assign axis_dbiterr = AXIS_DBITERR;
assign axis_overflow = AXIS_OVERFLOW;
assign axis_underflow = AXIS_UNDERFLOW;
assign axis_prog_full = AXIS_PROG_FULL;
assign axis_prog_empty = AXIS_PROG_EMPTY;
assign DIN = din;
assign PROG_EMPTY_THRESH = prog_empty_thresh;
assign PROG_EMPTY_THRESH_ASSERT = prog_empty_thresh_assert;
assign PROG_EMPTY_THRESH_NEGATE = prog_empty_thresh_negate;
assign PROG_FULL_THRESH = prog_full_thresh;
assign PROG_FULL_THRESH_ASSERT = prog_full_thresh_assert;
assign PROG_FULL_THRESH_NEGATE = prog_full_thresh_negate;
assign dout = DOUT;
assign data_count = DATA_COUNT;
assign rd_data_count = RD_DATA_COUNT;
assign wr_data_count = WR_DATA_COUNT;
assign S_AXI_AWID = s_axi_awid;
assign S_AXI_AWADDR = s_axi_awaddr;
assign S_AXI_AWLEN = s_axi_awlen;
assign S_AXI_AWSIZE = s_axi_awsize;
assign S_AXI_AWBURST = s_axi_awburst;
assign S_AXI_AWLOCK = s_axi_awlock;
assign S_AXI_AWCACHE = s_axi_awcache;
assign S_AXI_AWPROT = s_axi_awprot;
assign S_AXI_AWQOS = s_axi_awqos;
assign S_AXI_AWREGION = s_axi_awregion;
assign S_AXI_AWUSER = s_axi_awuser;
assign S_AXI_WID = s_axi_wid;
assign S_AXI_WDATA = s_axi_wdata;
assign S_AXI_WSTRB = s_axi_wstrb;
assign S_AXI_WUSER = s_axi_wuser;
assign s_axi_bid = S_AXI_BID;
assign s_axi_bresp = S_AXI_BRESP;
assign s_axi_buser = S_AXI_BUSER;
assign m_axi_awid = M_AXI_AWID;
assign m_axi_awaddr = M_AXI_AWADDR;
assign m_axi_awlen = M_AXI_AWLEN;
assign m_axi_awsize = M_AXI_AWSIZE;
assign m_axi_awburst = M_AXI_AWBURST;
assign m_axi_awlock = M_AXI_AWLOCK;
assign m_axi_awcache = M_AXI_AWCACHE;
assign m_axi_awprot = M_AXI_AWPROT;
assign m_axi_awqos = M_AXI_AWQOS;
assign m_axi_awregion = M_AXI_AWREGION;
assign m_axi_awuser = M_AXI_AWUSER;
assign m_axi_wid = M_AXI_WID;
assign m_axi_wdata = M_AXI_WDATA;
assign m_axi_wstrb = M_AXI_WSTRB;
assign m_axi_wuser = M_AXI_WUSER;
assign M_AXI_BID = m_axi_bid;
assign M_AXI_BRESP = m_axi_bresp;
assign M_AXI_BUSER = m_axi_buser;
assign S_AXI_ARID = s_axi_arid;
assign S_AXI_ARADDR = s_axi_araddr;
assign S_AXI_ARLEN = s_axi_arlen;
assign S_AXI_ARSIZE = s_axi_arsize;
assign S_AXI_ARBURST = s_axi_arburst;
assign S_AXI_ARLOCK = s_axi_arlock;
assign S_AXI_ARCACHE = s_axi_arcache;
assign S_AXI_ARPROT = s_axi_arprot;
assign S_AXI_ARQOS = s_axi_arqos;
assign S_AXI_ARREGION = s_axi_arregion;
assign S_AXI_ARUSER = s_axi_aruser;
assign s_axi_rid = S_AXI_RID;
assign s_axi_rdata = S_AXI_RDATA;
assign s_axi_rresp = S_AXI_RRESP;
assign s_axi_ruser = S_AXI_RUSER;
assign m_axi_arid = M_AXI_ARID;
assign m_axi_araddr = M_AXI_ARADDR;
assign m_axi_arlen = M_AXI_ARLEN;
assign m_axi_arsize = M_AXI_ARSIZE;
assign m_axi_arburst = M_AXI_ARBURST;
assign m_axi_arlock = M_AXI_ARLOCK;
assign m_axi_arcache = M_AXI_ARCACHE;
assign m_axi_arprot = M_AXI_ARPROT;
assign m_axi_arqos = M_AXI_ARQOS;
assign m_axi_arregion = M_AXI_ARREGION;
assign m_axi_aruser = M_AXI_ARUSER;
assign M_AXI_RID = m_axi_rid;
assign M_AXI_RDATA = m_axi_rdata;
assign M_AXI_RRESP = m_axi_rresp;
assign M_AXI_RUSER = m_axi_ruser;
assign S_AXIS_TDATA = s_axis_tdata;
assign S_AXIS_TSTRB = s_axis_tstrb;
assign S_AXIS_TKEEP = s_axis_tkeep;
assign S_AXIS_TID = s_axis_tid;
assign S_AXIS_TDEST = s_axis_tdest;
assign S_AXIS_TUSER = s_axis_tuser;
assign m_axis_tdata = M_AXIS_TDATA;
assign m_axis_tstrb = M_AXIS_TSTRB;
assign m_axis_tkeep = M_AXIS_TKEEP;
assign m_axis_tid = M_AXIS_TID;
assign m_axis_tdest = M_AXIS_TDEST;
assign m_axis_tuser = M_AXIS_TUSER;
assign AXI_AW_PROG_FULL_THRESH = axi_aw_prog_full_thresh;
assign AXI_AW_PROG_EMPTY_THRESH = axi_aw_prog_empty_thresh;
assign axi_aw_data_count = AXI_AW_DATA_COUNT;
assign axi_aw_wr_data_count = AXI_AW_WR_DATA_COUNT;
assign axi_aw_rd_data_count = AXI_AW_RD_DATA_COUNT;
assign AXI_W_PROG_FULL_THRESH = axi_w_prog_full_thresh;
assign AXI_W_PROG_EMPTY_THRESH = axi_w_prog_empty_thresh;
assign axi_w_data_count = AXI_W_DATA_COUNT;
assign axi_w_wr_data_count = AXI_W_WR_DATA_COUNT;
assign axi_w_rd_data_count = AXI_W_RD_DATA_COUNT;
assign AXI_B_PROG_FULL_THRESH = axi_b_prog_full_thresh;
assign AXI_B_PROG_EMPTY_THRESH = axi_b_prog_empty_thresh;
assign axi_b_data_count = AXI_B_DATA_COUNT;
assign axi_b_wr_data_count = AXI_B_WR_DATA_COUNT;
assign axi_b_rd_data_count = AXI_B_RD_DATA_COUNT;
assign AXI_AR_PROG_FULL_THRESH = axi_ar_prog_full_thresh;
assign AXI_AR_PROG_EMPTY_THRESH = axi_ar_prog_empty_thresh;
assign axi_ar_data_count = AXI_AR_DATA_COUNT;
assign axi_ar_wr_data_count = AXI_AR_WR_DATA_COUNT;
assign axi_ar_rd_data_count = AXI_AR_RD_DATA_COUNT;
assign AXI_R_PROG_FULL_THRESH = axi_r_prog_full_thresh;
assign AXI_R_PROG_EMPTY_THRESH = axi_r_prog_empty_thresh;
assign axi_r_data_count = AXI_R_DATA_COUNT;
assign axi_r_wr_data_count = AXI_R_WR_DATA_COUNT;
assign axi_r_rd_data_count = AXI_R_RD_DATA_COUNT;
assign AXIS_PROG_FULL_THRESH = axis_prog_full_thresh;
assign AXIS_PROG_EMPTY_THRESH = axis_prog_empty_thresh;
assign axis_data_count = AXIS_DATA_COUNT;
assign axis_wr_data_count = AXIS_WR_DATA_COUNT;
assign axis_rd_data_count = AXIS_RD_DATA_COUNT;
generate if (C_INTERFACE_TYPE == 0) begin : conv_fifo
fifo_generator_v13_1_3_CONV_VER
#(
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_USE_DOUT_RST == 1 ? C_DOUT_RST_VAL : 0),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_FAMILY (C_FAMILY),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RD_RST (C_HAS_RD_RST),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_HAS_WR_RST (C_HAS_WR_RST),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_FREQ (C_RD_FREQ),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_ECC (C_USE_ECC),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE)
)
fifo_generator_v13_1_3_conv_dut
(
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.CLK (CLK),
.RST (RST),
.SRST (SRST),
.WR_CLK (WR_CLK),
.WR_RST (WR_RST),
.RD_CLK (RD_CLK),
.RD_RST (RD_RST),
.DIN (DIN),
.WR_EN (WR_EN),
.RD_EN (RD_EN),
.PROG_EMPTY_THRESH (PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT),
.PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE),
.PROG_FULL_THRESH (PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT),
.PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE),
.INT_CLK (INT_CLK),
.INJECTDBITERR (INJECTDBITERR),
.INJECTSBITERR (INJECTSBITERR),
.DOUT (DOUT),
.FULL (FULL),
.ALMOST_FULL (ALMOST_FULL),
.WR_ACK (WR_ACK),
.OVERFLOW (OVERFLOW),
.EMPTY (EMPTY),
.ALMOST_EMPTY (ALMOST_EMPTY),
.VALID (VALID),
.UNDERFLOW (UNDERFLOW),
.DATA_COUNT (DATA_COUNT),
.RD_DATA_COUNT (RD_DATA_COUNT),
.WR_DATA_COUNT (wr_data_count_in),
.PROG_FULL (PROG_FULL),
.PROG_EMPTY (PROG_EMPTY),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.wr_rst_busy_o (wr_rst_busy_o),
.wr_rst_busy (wr_rst_busy_i),
.rd_rst_busy (rd_rst_busy),
.wr_rst_i_out (wr_rst_int),
.rd_rst_i_out (rd_rst_int)
);
end endgenerate
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
localparam C_AXI_SIZE_WIDTH = 3;
localparam C_AXI_BURST_WIDTH = 2;
localparam C_AXI_CACHE_WIDTH = 4;
localparam C_AXI_PROT_WIDTH = 3;
localparam C_AXI_QOS_WIDTH = 4;
localparam C_AXI_REGION_WIDTH = 4;
localparam C_AXI_BRESP_WIDTH = 2;
localparam C_AXI_RRESP_WIDTH = 2;
localparam IS_AXI_STREAMING = C_INTERFACE_TYPE == 1 ? 1 : 0;
localparam TDATA_OFFSET = C_HAS_AXIS_TDATA == 1 ? C_DIN_WIDTH_AXIS-C_AXIS_TDATA_WIDTH : C_DIN_WIDTH_AXIS;
localparam TSTRB_OFFSET = C_HAS_AXIS_TSTRB == 1 ? TDATA_OFFSET-C_AXIS_TSTRB_WIDTH : TDATA_OFFSET;
localparam TKEEP_OFFSET = C_HAS_AXIS_TKEEP == 1 ? TSTRB_OFFSET-C_AXIS_TKEEP_WIDTH : TSTRB_OFFSET;
localparam TID_OFFSET = C_HAS_AXIS_TID == 1 ? TKEEP_OFFSET-C_AXIS_TID_WIDTH : TKEEP_OFFSET;
localparam TDEST_OFFSET = C_HAS_AXIS_TDEST == 1 ? TID_OFFSET-C_AXIS_TDEST_WIDTH : TID_OFFSET;
localparam TUSER_OFFSET = C_HAS_AXIS_TUSER == 1 ? TDEST_OFFSET-C_AXIS_TUSER_WIDTH : TDEST_OFFSET;
localparam LOG_DEPTH_AXIS = find_log2(C_WR_DEPTH_AXIS);
localparam LOG_WR_DEPTH = find_log2(C_WR_DEPTH);
function [LOG_DEPTH_AXIS-1:0] bin2gray;
input [LOG_DEPTH_AXIS-1:0] x;
begin
bin2gray = x ^ (x>>1);
end
endfunction
function [LOG_DEPTH_AXIS-1:0] gray2bin;
input [LOG_DEPTH_AXIS-1:0] x;
integer i;
begin
gray2bin[LOG_DEPTH_AXIS-1] = x[LOG_DEPTH_AXIS-1];
for(i=LOG_DEPTH_AXIS-2; i>=0; i=i-1) begin
gray2bin[i] = gray2bin[i+1] ^ x[i];
end
end
endfunction
wire [(LOG_WR_DEPTH)-1 : 0] w_cnt_gc_asreg_last;
wire [LOG_WR_DEPTH-1 : 0] w_q [0:C_SYNCHRONIZER_STAGE] ;
wire [LOG_WR_DEPTH-1 : 0] w_q_temp [1:C_SYNCHRONIZER_STAGE] ;
reg [LOG_WR_DEPTH-1 : 0] w_cnt_rd = 0;
reg [LOG_WR_DEPTH-1 : 0] w_cnt = 0;
reg [LOG_WR_DEPTH-1 : 0] w_cnt_gc = 0;
reg [LOG_WR_DEPTH-1 : 0] r_cnt = 0;
wire [LOG_WR_DEPTH : 0] adj_w_cnt_rd_pad;
wire [LOG_WR_DEPTH : 0] r_inv_pad;
wire [LOG_WR_DEPTH-1 : 0] d_cnt;
reg [LOG_WR_DEPTH : 0] d_cnt_pad = 0;
reg adj_w_cnt_rd_pad_0 = 0;
reg r_inv_pad_0 = 0;
genvar l;
generate for (l = 1; ((l <= C_SYNCHRONIZER_STAGE) && (C_HAS_DATA_COUNTS_AXIS == 3 && C_INTERFACE_TYPE == 0) ); l = l + 1) begin : g_cnt_sync_stage
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (LOG_WR_DEPTH)
)
rd_stg_inst
(
.RST (rd_rst_int),
.CLK (RD_CLK),
.DIN (w_q[l-1]),
.DOUT (w_q[l])
);
end endgenerate // gpkt_cnt_sync_stage
generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS == 3) begin : fifo_ic_adapter
assign wr_eop_ad = WR_EN & !(FULL);
assign rd_eop_ad = RD_EN & !(EMPTY);
always @ (posedge wr_rst_int or posedge WR_CLK)
begin
if (wr_rst_int)
w_cnt <= 1'b0;
else if (wr_eop_ad)
w_cnt <= w_cnt + 1;
end
always @ (posedge wr_rst_int or posedge WR_CLK)
begin
if (wr_rst_int)
w_cnt_gc <= 1'b0;
else
w_cnt_gc <= bin2gray(w_cnt);
end
assign w_q[0] = w_cnt_gc;
assign w_cnt_gc_asreg_last = w_q[C_SYNCHRONIZER_STAGE];
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
w_cnt_rd <= 1'b0;
else
w_cnt_rd <= gray2bin(w_cnt_gc_asreg_last);
end
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
r_cnt <= 1'b0;
else if (rd_eop_ad)
r_cnt <= r_cnt + 1;
end
// Take the difference of write and read packet count
// Logic is similar to rd_pe_as
assign adj_w_cnt_rd_pad[LOG_WR_DEPTH : 1] = w_cnt_rd;
assign r_inv_pad[LOG_WR_DEPTH : 1] = ~r_cnt;
assign adj_w_cnt_rd_pad[0] = adj_w_cnt_rd_pad_0;
assign r_inv_pad[0] = r_inv_pad_0;
always @ ( rd_eop_ad )
begin
if (!rd_eop_ad) begin
adj_w_cnt_rd_pad_0 <= 1'b1;
r_inv_pad_0 <= 1'b1;
end else begin
adj_w_cnt_rd_pad_0 <= 1'b0;
r_inv_pad_0 <= 1'b0;
end
end
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
d_cnt_pad <= 1'b0;
else
d_cnt_pad <= adj_w_cnt_rd_pad + r_inv_pad ;
end
assign d_cnt = d_cnt_pad [LOG_WR_DEPTH : 1] ;
assign WR_DATA_COUNT = d_cnt;
end endgenerate // fifo_ic_adapter
generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS != 3) begin : fifo_icn_adapter
assign WR_DATA_COUNT = wr_data_count_in;
end endgenerate // fifo_icn_adapter
wire inverted_reset = ~S_ARESETN;
wire axi_rs_rst;
wire [C_DIN_WIDTH_AXIS-1:0] axis_din ;
wire [C_DIN_WIDTH_AXIS-1:0] axis_dout ;
wire axis_full ;
wire axis_almost_full ;
wire axis_empty ;
wire axis_s_axis_tready;
wire axis_m_axis_tvalid;
wire axis_wr_en ;
wire axis_rd_en ;
wire axis_we ;
wire axis_re ;
wire [C_WR_PNTR_WIDTH_AXIS:0] axis_dc;
reg axis_pkt_read = 1'b0;
wire axis_rd_rst;
wire axis_wr_rst;
generate if (C_INTERFACE_TYPE > 0 && (C_AXIS_TYPE == 1 || C_WACH_TYPE == 1 ||
C_WDCH_TYPE == 1 || C_WRCH_TYPE == 1 || C_RACH_TYPE == 1 || C_RDCH_TYPE == 1)) begin : gaxi_rs_rst
reg rst_d1 = 0 ;
reg rst_d2 = 0 ;
reg [3:0] axi_rst = 4'h0 ;
always @ (posedge inverted_reset or posedge S_ACLK) begin
if (inverted_reset) begin
rst_d1 <= 1'b1;
rst_d2 <= 1'b1;
axi_rst <= 4'hf;
end else begin
rst_d1 <= #`TCQ 1'b0;
rst_d2 <= #`TCQ rst_d1;
axi_rst <= #`TCQ {axi_rst[2:0],1'b0};
end
end
assign axi_rs_rst = axi_rst[3];//rst_d2;
end endgenerate // gaxi_rs_rst
generate if (IS_AXI_STREAMING == 1 && C_AXIS_TYPE == 0) begin : axi_streaming
// Write protection when almost full or prog_full is high
assign axis_we = (C_PROG_FULL_TYPE_AXIS != 0) ? axis_s_axis_tready & S_AXIS_TVALID :
(C_APPLICATION_TYPE_AXIS == 1) ? axis_s_axis_tready & S_AXIS_TVALID : S_AXIS_TVALID;
// Read protection when almost empty or prog_empty is high
assign axis_re = (C_PROG_EMPTY_TYPE_AXIS != 0) ? axis_m_axis_tvalid & M_AXIS_TREADY :
(C_APPLICATION_TYPE_AXIS == 1) ? axis_m_axis_tvalid & M_AXIS_TREADY : M_AXIS_TREADY;
assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? axis_we & S_ACLK_EN : axis_we;
assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? axis_re & M_ACLK_EN : axis_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_AXIS == 2 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_AXIS == 11 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_AXIS),
.C_WR_DEPTH (C_WR_DEPTH_AXIS),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_AXIS),
.C_DOUT_WIDTH (C_DIN_WIDTH_AXIS),
.C_RD_DEPTH (C_WR_DEPTH_AXIS),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_AXIS),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_AXIS),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_AXIS),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_AXIS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS),
.C_USE_ECC (C_USE_ECC_AXIS),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_AXIS),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (C_APPLICATION_TYPE_AXIS == 1 ? 1: 0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_FIFO_TYPE (C_APPLICATION_TYPE_AXIS == 1 ? 0: C_APPLICATION_TYPE_AXIS),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_axis_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (axis_wr_en),
.RD_EN (axis_rd_en),
.PROG_FULL_THRESH (AXIS_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_EMPTY_THRESH (AXIS_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.INJECTDBITERR (AXIS_INJECTDBITERR),
.INJECTSBITERR (AXIS_INJECTSBITERR),
.DIN (axis_din),
.DOUT (axis_dout),
.FULL (axis_full),
.EMPTY (axis_empty),
.ALMOST_FULL (axis_almost_full),
.PROG_FULL (AXIS_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXIS_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (AXIS_OVERFLOW),
.VALID (),
.UNDERFLOW (AXIS_UNDERFLOW),
.DATA_COUNT (axis_dc),
.RD_DATA_COUNT (AXIS_RD_DATA_COUNT),
.WR_DATA_COUNT (AXIS_WR_DATA_COUNT),
.SBITERR (AXIS_SBITERR),
.DBITERR (AXIS_DBITERR),
.wr_rst_busy (wr_rst_busy_axis),
.rd_rst_busy (rd_rst_busy_axis),
.wr_rst_i_out (axis_wr_rst),
.rd_rst_i_out (axis_rd_rst),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign axis_s_axis_tready = (IS_8SERIES == 0) ? ~axis_full : (C_IMPLEMENTATION_TYPE_AXIS == 5 || C_IMPLEMENTATION_TYPE_AXIS == 13) ? ~(axis_full | wr_rst_busy_axis) : ~axis_full;
assign axis_m_axis_tvalid = (C_APPLICATION_TYPE_AXIS != 1) ? ~axis_empty : ~axis_empty & axis_pkt_read;
assign S_AXIS_TREADY = axis_s_axis_tready;
assign M_AXIS_TVALID = axis_m_axis_tvalid;
end endgenerate // axi_streaming
wire axis_wr_eop;
reg axis_wr_eop_d1 = 1'b0;
wire axis_rd_eop;
integer axis_pkt_cnt;
generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 1) begin : gaxis_pkt_fifo_cc
assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;
assign axis_rd_eop = axis_rd_en & axis_dout[0];
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_pkt_read <= 1'b0;
else if (axis_rd_eop && (axis_pkt_cnt == 1) && ~axis_wr_eop_d1)
axis_pkt_read <= 1'b0;
else if ((axis_pkt_cnt > 0) || (axis_almost_full && ~axis_empty))
axis_pkt_read <= 1'b1;
end
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_wr_eop_d1 <= 1'b0;
else
axis_wr_eop_d1 <= axis_wr_eop;
end
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_pkt_cnt <= 0;
else if (axis_wr_eop_d1 && ~axis_rd_eop)
axis_pkt_cnt <= axis_pkt_cnt + 1;
else if (axis_rd_eop && ~axis_wr_eop_d1)
axis_pkt_cnt <= axis_pkt_cnt - 1;
end
end endgenerate // gaxis_pkt_fifo_cc
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_gc = 0;
wire [(LOG_DEPTH_AXIS)-1 : 0] axis_wpkt_cnt_gc_asreg_last;
wire axis_rd_has_rst;
wire [0:C_SYNCHRONIZER_STAGE] axis_af_q ;
wire [LOG_DEPTH_AXIS-1 : 0] wpkt_q [0:C_SYNCHRONIZER_STAGE] ;
wire [1:C_SYNCHRONIZER_STAGE] axis_af_q_temp = 0;
wire [LOG_DEPTH_AXIS-1 : 0] wpkt_q_temp [1:C_SYNCHRONIZER_STAGE] ;
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_rd = 0;
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt = 0;
reg [LOG_DEPTH_AXIS-1 : 0] axis_rpkt_cnt = 0;
wire [LOG_DEPTH_AXIS : 0] adj_axis_wpkt_cnt_rd_pad;
wire [LOG_DEPTH_AXIS : 0] rpkt_inv_pad;
wire [LOG_DEPTH_AXIS-1 : 0] diff_pkt_cnt;
reg [LOG_DEPTH_AXIS : 0] diff_pkt_cnt_pad = 0;
reg adj_axis_wpkt_cnt_rd_pad_0 = 0;
reg rpkt_inv_pad_0 = 0;
wire axis_af_rd ;
generate if (C_HAS_RST == 1) begin : rst_blk_has
assign axis_rd_has_rst = axis_rd_rst;
end endgenerate //rst_blk_has
generate if (C_HAS_RST == 0) begin :rst_blk_no
assign axis_rd_has_rst = 1'b0;
end endgenerate //rst_blk_no
genvar i;
generate for (i = 1; ((i <= C_SYNCHRONIZER_STAGE) && (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) ); i = i + 1) begin : gpkt_cnt_sync_stage
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (LOG_DEPTH_AXIS)
)
rd_stg_inst
(
.RST (axis_rd_has_rst),
.CLK (M_ACLK),
.DIN (wpkt_q[i-1]),
.DOUT (wpkt_q[i])
);
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (1)
)
wr_stg_inst
(
.RST (axis_rd_has_rst),
.CLK (M_ACLK),
.DIN (axis_af_q[i-1]),
.DOUT (axis_af_q[i])
);
end endgenerate // gpkt_cnt_sync_stage
generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) begin : gaxis_pkt_fifo_ic
assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;
assign axis_rd_eop = axis_rd_en & axis_dout[0];
always @ (posedge axis_rd_has_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_pkt_read <= 1'b0;
else if (axis_rd_eop && (diff_pkt_cnt == 1))
axis_pkt_read <= 1'b0;
else if ((diff_pkt_cnt > 0) || (axis_af_rd && ~axis_empty))
axis_pkt_read <= 1'b1;
end
always @ (posedge axis_wr_rst or posedge S_ACLK)
begin
if (axis_wr_rst)
axis_wpkt_cnt <= 1'b0;
else if (axis_wr_eop)
axis_wpkt_cnt <= axis_wpkt_cnt + 1;
end
always @ (posedge axis_wr_rst or posedge S_ACLK)
begin
if (axis_wr_rst)
axis_wpkt_cnt_gc <= 1'b0;
else
axis_wpkt_cnt_gc <= bin2gray(axis_wpkt_cnt);
end
assign wpkt_q[0] = axis_wpkt_cnt_gc;
assign axis_wpkt_cnt_gc_asreg_last = wpkt_q[C_SYNCHRONIZER_STAGE];
assign axis_af_q[0] = axis_almost_full;
//assign axis_af_q[1:C_SYNCHRONIZER_STAGE] = axis_af_q_temp[1:C_SYNCHRONIZER_STAGE];
assign axis_af_rd = axis_af_q[C_SYNCHRONIZER_STAGE];
always @ (posedge axis_rd_has_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_wpkt_cnt_rd <= 1'b0;
else
axis_wpkt_cnt_rd <= gray2bin(axis_wpkt_cnt_gc_asreg_last);
end
always @ (posedge axis_rd_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_rpkt_cnt <= 1'b0;
else if (axis_rd_eop)
axis_rpkt_cnt <= axis_rpkt_cnt + 1;
end
// Take the difference of write and read packet count
// Logic is similar to rd_pe_as
assign adj_axis_wpkt_cnt_rd_pad[LOG_DEPTH_AXIS : 1] = axis_wpkt_cnt_rd;
assign rpkt_inv_pad[LOG_DEPTH_AXIS : 1] = ~axis_rpkt_cnt;
assign adj_axis_wpkt_cnt_rd_pad[0] = adj_axis_wpkt_cnt_rd_pad_0;
assign rpkt_inv_pad[0] = rpkt_inv_pad_0;
always @ ( axis_rd_eop )
begin
if (!axis_rd_eop) begin
adj_axis_wpkt_cnt_rd_pad_0 <= 1'b1;
rpkt_inv_pad_0 <= 1'b1;
end else begin
adj_axis_wpkt_cnt_rd_pad_0 <= 1'b0;
rpkt_inv_pad_0 <= 1'b0;
end
end
always @ (posedge axis_rd_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
diff_pkt_cnt_pad <= 1'b0;
else
diff_pkt_cnt_pad <= adj_axis_wpkt_cnt_rd_pad + rpkt_inv_pad ;
end
assign diff_pkt_cnt = diff_pkt_cnt_pad [LOG_DEPTH_AXIS : 1] ;
end endgenerate // gaxis_pkt_fifo_ic
// Generate the accurate data count for axi stream packet fifo configuration
reg [C_WR_PNTR_WIDTH_AXIS:0] axis_dc_pkt_fifo = 0;
generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 1 && C_APPLICATION_TYPE_AXIS == 1) begin : gdc_pkt
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_dc_pkt_fifo <= 0;
else if (axis_wr_en && (~axis_rd_en))
axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo + 1;
else if (~axis_wr_en && axis_rd_en)
axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo - 1;
end
assign AXIS_DATA_COUNT = axis_dc_pkt_fifo;
end endgenerate // gdc_pkt
generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 0 && C_APPLICATION_TYPE_AXIS == 1) begin : gndc_pkt
assign AXIS_DATA_COUNT = 0;
end endgenerate // gndc_pkt
generate if (IS_AXI_STREAMING == 1 && C_APPLICATION_TYPE_AXIS != 1) begin : gdc
assign AXIS_DATA_COUNT = axis_dc;
end endgenerate // gdc
// Register Slice for Write Address Channel
generate if (C_AXIS_TYPE == 1) begin : gaxis_reg_slice
assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? S_AXIS_TVALID & S_ACLK_EN : S_AXIS_TVALID;
assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? M_AXIS_TREADY & M_ACLK_EN : M_AXIS_TREADY;
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_AXIS),
.C_REG_CONFIG (C_REG_SLICE_MODE_AXIS)
)
axis_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (axis_din),
.S_VALID (axis_wr_en),
.S_READY (S_AXIS_TREADY),
// Master side
.M_PAYLOAD_DATA (axis_dout),
.M_VALID (M_AXIS_TVALID),
.M_READY (axis_rd_en)
);
end endgenerate // gaxis_reg_slice
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDATA == 1) begin : tdata
assign axis_din[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET] = S_AXIS_TDATA;
assign M_AXIS_TDATA = axis_dout[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TSTRB == 1) begin : tstrb
assign axis_din[TDATA_OFFSET-1:TSTRB_OFFSET] = S_AXIS_TSTRB;
assign M_AXIS_TSTRB = axis_dout[TDATA_OFFSET-1:TSTRB_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TKEEP == 1) begin : tkeep
assign axis_din[TSTRB_OFFSET-1:TKEEP_OFFSET] = S_AXIS_TKEEP;
assign M_AXIS_TKEEP = axis_dout[TSTRB_OFFSET-1:TKEEP_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TID == 1) begin : tid
assign axis_din[TKEEP_OFFSET-1:TID_OFFSET] = S_AXIS_TID;
assign M_AXIS_TID = axis_dout[TKEEP_OFFSET-1:TID_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDEST == 1) begin : tdest
assign axis_din[TID_OFFSET-1:TDEST_OFFSET] = S_AXIS_TDEST;
assign M_AXIS_TDEST = axis_dout[TID_OFFSET-1:TDEST_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TUSER == 1) begin : tuser
assign axis_din[TDEST_OFFSET-1:TUSER_OFFSET] = S_AXIS_TUSER;
assign M_AXIS_TUSER = axis_dout[TDEST_OFFSET-1:TUSER_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TLAST == 1) begin : tlast
assign axis_din[0] = S_AXIS_TLAST;
assign M_AXIS_TLAST = axis_dout[0];
end endgenerate
//###########################################################################
// AXI FULL Write Channel (axi_write_channel)
//###########################################################################
localparam IS_AXI_FULL = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE != 2)) ? 1 : 0;
localparam IS_AXI_LITE = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE == 2)) ? 1 : 0;
localparam IS_AXI_FULL_WACH = ((IS_AXI_FULL == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_WDCH = ((IS_AXI_FULL == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_WRCH = ((IS_AXI_FULL == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_RACH = ((IS_AXI_FULL == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_RDCH = ((IS_AXI_FULL == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WACH = ((IS_AXI_LITE == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WDCH = ((IS_AXI_LITE == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WRCH = ((IS_AXI_LITE == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_RACH = ((IS_AXI_LITE == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_RDCH = ((IS_AXI_LITE == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_WR_ADDR_CH = ((IS_AXI_FULL_WACH == 1) || (IS_AXI_LITE_WACH == 1)) ? 1 : 0;
localparam IS_WR_DATA_CH = ((IS_AXI_FULL_WDCH == 1) || (IS_AXI_LITE_WDCH == 1)) ? 1 : 0;
localparam IS_WR_RESP_CH = ((IS_AXI_FULL_WRCH == 1) || (IS_AXI_LITE_WRCH == 1)) ? 1 : 0;
localparam IS_RD_ADDR_CH = ((IS_AXI_FULL_RACH == 1) || (IS_AXI_LITE_RACH == 1)) ? 1 : 0;
localparam IS_RD_DATA_CH = ((IS_AXI_FULL_RDCH == 1) || (IS_AXI_LITE_RDCH == 1)) ? 1 : 0;
localparam AWID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WACH;
localparam AWADDR_OFFSET = AWID_OFFSET - C_AXI_ADDR_WIDTH;
localparam AWLEN_OFFSET = C_AXI_TYPE != 2 ? AWADDR_OFFSET - C_AXI_LEN_WIDTH : AWADDR_OFFSET;
localparam AWSIZE_OFFSET = C_AXI_TYPE != 2 ? AWLEN_OFFSET - C_AXI_SIZE_WIDTH : AWLEN_OFFSET;
localparam AWBURST_OFFSET = C_AXI_TYPE != 2 ? AWSIZE_OFFSET - C_AXI_BURST_WIDTH : AWSIZE_OFFSET;
localparam AWLOCK_OFFSET = C_AXI_TYPE != 2 ? AWBURST_OFFSET - C_AXI_LOCK_WIDTH : AWBURST_OFFSET;
localparam AWCACHE_OFFSET = C_AXI_TYPE != 2 ? AWLOCK_OFFSET - C_AXI_CACHE_WIDTH : AWLOCK_OFFSET;
localparam AWPROT_OFFSET = AWCACHE_OFFSET - C_AXI_PROT_WIDTH;
localparam AWQOS_OFFSET = AWPROT_OFFSET - C_AXI_QOS_WIDTH;
localparam AWREGION_OFFSET = C_AXI_TYPE == 1 ? AWQOS_OFFSET - C_AXI_REGION_WIDTH : AWQOS_OFFSET;
localparam AWUSER_OFFSET = C_HAS_AXI_AWUSER == 1 ? AWREGION_OFFSET-C_AXI_AWUSER_WIDTH : AWREGION_OFFSET;
localparam WID_OFFSET = (C_AXI_TYPE == 3 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WDCH;
localparam WDATA_OFFSET = WID_OFFSET - C_AXI_DATA_WIDTH;
localparam WSTRB_OFFSET = WDATA_OFFSET - C_AXI_DATA_WIDTH/8;
localparam WUSER_OFFSET = C_HAS_AXI_WUSER == 1 ? WSTRB_OFFSET-C_AXI_WUSER_WIDTH : WSTRB_OFFSET;
localparam BID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WRCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WRCH;
localparam BRESP_OFFSET = BID_OFFSET - C_AXI_BRESP_WIDTH;
localparam BUSER_OFFSET = C_HAS_AXI_BUSER == 1 ? BRESP_OFFSET-C_AXI_BUSER_WIDTH : BRESP_OFFSET;
wire [C_DIN_WIDTH_WACH-1:0] wach_din ;
wire [C_DIN_WIDTH_WACH-1:0] wach_dout ;
wire [C_DIN_WIDTH_WACH-1:0] wach_dout_pkt ;
wire wach_full ;
wire wach_almost_full ;
wire wach_prog_full ;
wire wach_empty ;
wire wach_almost_empty ;
wire wach_prog_empty ;
wire [C_DIN_WIDTH_WDCH-1:0] wdch_din ;
wire [C_DIN_WIDTH_WDCH-1:0] wdch_dout ;
wire wdch_full ;
wire wdch_almost_full ;
wire wdch_prog_full ;
wire wdch_empty ;
wire wdch_almost_empty ;
wire wdch_prog_empty ;
wire [C_DIN_WIDTH_WRCH-1:0] wrch_din ;
wire [C_DIN_WIDTH_WRCH-1:0] wrch_dout ;
wire wrch_full ;
wire wrch_almost_full ;
wire wrch_prog_full ;
wire wrch_empty ;
wire wrch_almost_empty ;
wire wrch_prog_empty ;
wire axi_aw_underflow_i;
wire axi_w_underflow_i ;
wire axi_b_underflow_i ;
wire axi_aw_overflow_i ;
wire axi_w_overflow_i ;
wire axi_b_overflow_i ;
wire axi_wr_underflow_i;
wire axi_wr_overflow_i ;
wire wach_s_axi_awready;
wire wach_m_axi_awvalid;
wire wach_wr_en ;
wire wach_rd_en ;
wire wdch_s_axi_wready ;
wire wdch_m_axi_wvalid ;
wire wdch_wr_en ;
wire wdch_rd_en ;
wire wrch_s_axi_bvalid ;
wire wrch_m_axi_bready ;
wire wrch_wr_en ;
wire wrch_rd_en ;
wire txn_count_up ;
wire txn_count_down ;
wire awvalid_en ;
wire awvalid_pkt ;
wire awready_pkt ;
integer wr_pkt_count ;
wire wach_we ;
wire wach_re ;
wire wdch_we ;
wire wdch_re ;
wire wrch_we ;
wire wrch_re ;
generate if (IS_WR_ADDR_CH == 1) begin : axi_write_address_channel
// Write protection when almost full or prog_full is high
assign wach_we = (C_PROG_FULL_TYPE_WACH != 0) ? wach_s_axi_awready & S_AXI_AWVALID : S_AXI_AWVALID;
// Read protection when almost empty or prog_empty is high
assign wach_re = (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH == 1) ?
wach_m_axi_awvalid & awready_pkt & awvalid_en :
(C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH != 1) ?
M_AXI_AWREADY && wach_m_axi_awvalid :
(C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH == 1) ?
awready_pkt & awvalid_en :
(C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH != 1) ?
M_AXI_AWREADY : 1'b0;
assign wach_wr_en = (C_HAS_SLAVE_CE == 1) ? wach_we & S_ACLK_EN : wach_we;
assign wach_rd_en = (C_HAS_MASTER_CE == 1) ? wach_re & M_ACLK_EN : wach_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WACH == 2 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WACH == 11 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WACH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_WR_DEPTH (C_WR_DEPTH_WACH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WACH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WACH),
.C_RD_DEPTH (C_WR_DEPTH_WACH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WACH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WACH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WACH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WACH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH),
.C_USE_ECC (C_USE_ECC_WACH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WACH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE ((C_APPLICATION_TYPE_WACH == 1)?0:C_APPLICATION_TYPE_WACH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 : 0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_wach_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wach_wr_en),
.RD_EN (wach_rd_en),
.PROG_FULL_THRESH (AXI_AW_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_AW_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.INJECTDBITERR (AXI_AW_INJECTDBITERR),
.INJECTSBITERR (AXI_AW_INJECTSBITERR),
.DIN (wach_din),
.DOUT (wach_dout_pkt),
.FULL (wach_full),
.EMPTY (wach_empty),
.ALMOST_FULL (),
.PROG_FULL (AXI_AW_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXI_AW_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_aw_overflow_i),
.VALID (),
.UNDERFLOW (axi_aw_underflow_i),
.DATA_COUNT (AXI_AW_DATA_COUNT),
.RD_DATA_COUNT (AXI_AW_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_AW_WR_DATA_COUNT),
.SBITERR (AXI_AW_SBITERR),
.DBITERR (AXI_AW_DBITERR),
.wr_rst_busy (wr_rst_busy_wach),
.rd_rst_busy (rd_rst_busy_wach),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wach_s_axi_awready = (IS_8SERIES == 0) ? ~wach_full : (C_IMPLEMENTATION_TYPE_WACH == 5 || C_IMPLEMENTATION_TYPE_WACH == 13) ? ~(wach_full | wr_rst_busy_wach) : ~wach_full;
assign wach_m_axi_awvalid = ~wach_empty;
assign S_AXI_AWREADY = wach_s_axi_awready;
assign AXI_AW_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_aw_underflow_i : 0;
assign AXI_AW_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_aw_overflow_i : 0;
end endgenerate // axi_write_address_channel
// Register Slice for Write Address Channel
generate if (C_WACH_TYPE == 1) begin : gwach_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WACH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WACH)
)
wach_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wach_din),
.S_VALID (S_AXI_AWVALID),
.S_READY (S_AXI_AWREADY),
// Master side
.M_PAYLOAD_DATA (wach_dout),
.M_VALID (M_AXI_AWVALID),
.M_READY (M_AXI_AWREADY)
);
end endgenerate // gwach_reg_slice
generate if (C_APPLICATION_TYPE_WACH == 1 && C_HAS_AXI_WR_CHANNEL == 1) begin : axi_mm_pkt_fifo_wr
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WACH),
.C_REG_CONFIG (1)
)
wach_pkt_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (inverted_reset),
// Slave side
.S_PAYLOAD_DATA (wach_dout_pkt),
.S_VALID (awvalid_pkt),
.S_READY (awready_pkt),
// Master side
.M_PAYLOAD_DATA (wach_dout),
.M_VALID (M_AXI_AWVALID),
.M_READY (M_AXI_AWREADY)
);
assign awvalid_pkt = wach_m_axi_awvalid && awvalid_en;
assign txn_count_up = wdch_s_axi_wready && wdch_wr_en && wdch_din[0];
assign txn_count_down = wach_m_axi_awvalid && awready_pkt && awvalid_en;
always@(posedge S_ACLK or posedge inverted_reset) begin
if(inverted_reset == 1) begin
wr_pkt_count <= 0;
end else begin
if(txn_count_up == 1 && txn_count_down == 0) begin
wr_pkt_count <= wr_pkt_count + 1;
end else if(txn_count_up == 0 && txn_count_down == 1) begin
wr_pkt_count <= wr_pkt_count - 1;
end
end
end //Always end
assign awvalid_en = (wr_pkt_count > 0)?1:0;
end endgenerate
generate if (C_APPLICATION_TYPE_WACH != 1) begin : axi_mm_fifo_wr
assign awvalid_en = 1;
assign wach_dout = wach_dout_pkt;
assign M_AXI_AWVALID = wach_m_axi_awvalid;
end
endgenerate
generate if (IS_WR_DATA_CH == 1) begin : axi_write_data_channel
// Write protection when almost full or prog_full is high
assign wdch_we = (C_PROG_FULL_TYPE_WDCH != 0) ? wdch_s_axi_wready & S_AXI_WVALID : S_AXI_WVALID;
// Read protection when almost empty or prog_empty is high
assign wdch_re = (C_PROG_EMPTY_TYPE_WDCH != 0) ? wdch_m_axi_wvalid & M_AXI_WREADY : M_AXI_WREADY;
assign wdch_wr_en = (C_HAS_SLAVE_CE == 1) ? wdch_we & S_ACLK_EN : wdch_we;
assign wdch_rd_en = (C_HAS_MASTER_CE == 1) ? wdch_re & M_ACLK_EN : wdch_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WDCH == 2 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WDCH == 11 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WDCH),
.C_WR_DEPTH (C_WR_DEPTH_WDCH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WDCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WDCH),
.C_RD_DEPTH (C_WR_DEPTH_WDCH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WDCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WDCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WDCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WDCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH),
.C_USE_ECC (C_USE_ECC_WDCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WDCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_WDCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_wdch_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wdch_wr_en),
.RD_EN (wdch_rd_en),
.PROG_FULL_THRESH (AXI_W_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_W_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.INJECTDBITERR (AXI_W_INJECTDBITERR),
.INJECTSBITERR (AXI_W_INJECTSBITERR),
.DIN (wdch_din),
.DOUT (wdch_dout),
.FULL (wdch_full),
.EMPTY (wdch_empty),
.ALMOST_FULL (),
.PROG_FULL (AXI_W_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXI_W_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_w_overflow_i),
.VALID (),
.UNDERFLOW (axi_w_underflow_i),
.DATA_COUNT (AXI_W_DATA_COUNT),
.RD_DATA_COUNT (AXI_W_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_W_WR_DATA_COUNT),
.SBITERR (AXI_W_SBITERR),
.DBITERR (AXI_W_DBITERR),
.wr_rst_busy (wr_rst_busy_wdch),
.rd_rst_busy (rd_rst_busy_wdch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wdch_s_axi_wready = (IS_8SERIES == 0) ? ~wdch_full : (C_IMPLEMENTATION_TYPE_WDCH == 5 || C_IMPLEMENTATION_TYPE_WDCH == 13) ? ~(wdch_full | wr_rst_busy_wdch) : ~wdch_full;
assign wdch_m_axi_wvalid = ~wdch_empty;
assign S_AXI_WREADY = wdch_s_axi_wready;
assign M_AXI_WVALID = wdch_m_axi_wvalid;
assign AXI_W_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_w_underflow_i : 0;
assign AXI_W_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_w_overflow_i : 0;
end endgenerate // axi_write_data_channel
// Register Slice for Write Data Channel
generate if (C_WDCH_TYPE == 1) begin : gwdch_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WDCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WDCH)
)
wdch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wdch_din),
.S_VALID (S_AXI_WVALID),
.S_READY (S_AXI_WREADY),
// Master side
.M_PAYLOAD_DATA (wdch_dout),
.M_VALID (M_AXI_WVALID),
.M_READY (M_AXI_WREADY)
);
end endgenerate // gwdch_reg_slice
generate if (IS_WR_RESP_CH == 1) begin : axi_write_resp_channel
// Write protection when almost full or prog_full is high
assign wrch_we = (C_PROG_FULL_TYPE_WRCH != 0) ? wrch_m_axi_bready & M_AXI_BVALID : M_AXI_BVALID;
// Read protection when almost empty or prog_empty is high
assign wrch_re = (C_PROG_EMPTY_TYPE_WRCH != 0) ? wrch_s_axi_bvalid & S_AXI_BREADY : S_AXI_BREADY;
assign wrch_wr_en = (C_HAS_MASTER_CE == 1) ? wrch_we & M_ACLK_EN : wrch_we;
assign wrch_rd_en = (C_HAS_SLAVE_CE == 1) ? wrch_re & S_ACLK_EN : wrch_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WRCH == 2 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WRCH == 11 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WRCH),
.C_WR_DEPTH (C_WR_DEPTH_WRCH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WRCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WRCH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_RD_DEPTH (C_WR_DEPTH_WRCH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WRCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WRCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WRCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WRCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH),
.C_USE_ECC (C_USE_ECC_WRCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WRCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_WRCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_wrch_dut
(
.CLK (S_ACLK),
.WR_CLK (M_ACLK),
.RD_CLK (S_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wrch_wr_en),
.RD_EN (wrch_rd_en),
.PROG_FULL_THRESH (AXI_B_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_B_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.INJECTDBITERR (AXI_B_INJECTDBITERR),
.INJECTSBITERR (AXI_B_INJECTSBITERR),
.DIN (wrch_din),
.DOUT (wrch_dout),
.FULL (wrch_full),
.EMPTY (wrch_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_B_PROG_FULL),
.PROG_EMPTY (AXI_B_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_b_overflow_i),
.VALID (),
.UNDERFLOW (axi_b_underflow_i),
.DATA_COUNT (AXI_B_DATA_COUNT),
.RD_DATA_COUNT (AXI_B_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_B_WR_DATA_COUNT),
.SBITERR (AXI_B_SBITERR),
.DBITERR (AXI_B_DBITERR),
.wr_rst_busy (wr_rst_busy_wrch),
.rd_rst_busy (rd_rst_busy_wrch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wrch_s_axi_bvalid = ~wrch_empty;
assign wrch_m_axi_bready = (IS_8SERIES == 0) ? ~wrch_full : (C_IMPLEMENTATION_TYPE_WRCH == 5 || C_IMPLEMENTATION_TYPE_WRCH == 13) ? ~(wrch_full | wr_rst_busy_wrch) : ~wrch_full;
assign S_AXI_BVALID = wrch_s_axi_bvalid;
assign M_AXI_BREADY = wrch_m_axi_bready;
assign AXI_B_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_b_underflow_i : 0;
assign AXI_B_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_b_overflow_i : 0;
end endgenerate // axi_write_resp_channel
// Register Slice for Write Response Channel
generate if (C_WRCH_TYPE == 1) begin : gwrch_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WRCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WRCH)
)
wrch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wrch_din),
.S_VALID (M_AXI_BVALID),
.S_READY (M_AXI_BREADY),
// Master side
.M_PAYLOAD_DATA (wrch_dout),
.M_VALID (S_AXI_BVALID),
.M_READY (S_AXI_BREADY)
);
end endgenerate // gwrch_reg_slice
assign axi_wr_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_aw_underflow_i || axi_w_underflow_i || axi_b_underflow_i) : 0;
assign axi_wr_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_aw_overflow_i || axi_w_overflow_i || axi_b_overflow_i) : 0;
generate if (IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output
assign M_AXI_AWADDR = wach_dout[AWID_OFFSET-1:AWADDR_OFFSET];
assign M_AXI_AWLEN = wach_dout[AWADDR_OFFSET-1:AWLEN_OFFSET];
assign M_AXI_AWSIZE = wach_dout[AWLEN_OFFSET-1:AWSIZE_OFFSET];
assign M_AXI_AWBURST = wach_dout[AWSIZE_OFFSET-1:AWBURST_OFFSET];
assign M_AXI_AWLOCK = wach_dout[AWBURST_OFFSET-1:AWLOCK_OFFSET];
assign M_AXI_AWCACHE = wach_dout[AWLOCK_OFFSET-1:AWCACHE_OFFSET];
assign M_AXI_AWPROT = wach_dout[AWCACHE_OFFSET-1:AWPROT_OFFSET];
assign M_AXI_AWQOS = wach_dout[AWPROT_OFFSET-1:AWQOS_OFFSET];
assign wach_din[AWID_OFFSET-1:AWADDR_OFFSET] = S_AXI_AWADDR;
assign wach_din[AWADDR_OFFSET-1:AWLEN_OFFSET] = S_AXI_AWLEN;
assign wach_din[AWLEN_OFFSET-1:AWSIZE_OFFSET] = S_AXI_AWSIZE;
assign wach_din[AWSIZE_OFFSET-1:AWBURST_OFFSET] = S_AXI_AWBURST;
assign wach_din[AWBURST_OFFSET-1:AWLOCK_OFFSET] = S_AXI_AWLOCK;
assign wach_din[AWLOCK_OFFSET-1:AWCACHE_OFFSET] = S_AXI_AWCACHE;
assign wach_din[AWCACHE_OFFSET-1:AWPROT_OFFSET] = S_AXI_AWPROT;
assign wach_din[AWPROT_OFFSET-1:AWQOS_OFFSET] = S_AXI_AWQOS;
end endgenerate // axi_wach_output
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_awregion
assign M_AXI_AWREGION = wach_dout[AWQOS_OFFSET-1:AWREGION_OFFSET];
end endgenerate // axi_awregion
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_awregion
assign M_AXI_AWREGION = 0;
end endgenerate // naxi_awregion
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : axi_awuser
assign M_AXI_AWUSER = wach_dout[AWREGION_OFFSET-1:AWUSER_OFFSET];
end endgenerate // axi_awuser
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 0) begin : naxi_awuser
assign M_AXI_AWUSER = 0;
end endgenerate // naxi_awuser
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_awid
assign M_AXI_AWID = wach_dout[C_DIN_WIDTH_WACH-1:AWID_OFFSET];
end endgenerate //axi_awid
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_awid
assign M_AXI_AWID = 0;
end endgenerate //naxi_awid
generate if (IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output
assign M_AXI_WDATA = wdch_dout[WID_OFFSET-1:WDATA_OFFSET];
assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];
assign M_AXI_WLAST = wdch_dout[0];
assign wdch_din[WID_OFFSET-1:WDATA_OFFSET] = S_AXI_WDATA;
assign wdch_din[WDATA_OFFSET-1:WSTRB_OFFSET] = S_AXI_WSTRB;
assign wdch_din[0] = S_AXI_WLAST;
end endgenerate // axi_wdch_output
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin
assign M_AXI_WID = wdch_dout[C_DIN_WIDTH_WDCH-1:WID_OFFSET];
end endgenerate
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && (C_HAS_AXI_ID == 0 || C_AXI_TYPE != 3)) begin
assign M_AXI_WID = 0;
end endgenerate
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1 ) begin
assign M_AXI_WUSER = wdch_dout[WSTRB_OFFSET-1:WUSER_OFFSET];
end endgenerate
generate if (C_HAS_AXI_WUSER == 0) begin
assign M_AXI_WUSER = 0;
end endgenerate
generate if (IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output
assign S_AXI_BRESP = wrch_dout[BID_OFFSET-1:BRESP_OFFSET];
assign wrch_din[BID_OFFSET-1:BRESP_OFFSET] = M_AXI_BRESP;
end endgenerate // axi_wrch_output
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : axi_buser
assign S_AXI_BUSER = wrch_dout[BRESP_OFFSET-1:BUSER_OFFSET];
end endgenerate // axi_buser
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 0) begin : naxi_buser
assign S_AXI_BUSER = 0;
end endgenerate // naxi_buser
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_bid
assign S_AXI_BID = wrch_dout[C_DIN_WIDTH_WRCH-1:BID_OFFSET];
end endgenerate // axi_bid
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_bid
assign S_AXI_BID = 0 ;
end endgenerate // naxi_bid
generate if (IS_AXI_LITE_WACH == 1 || (IS_AXI_LITE == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output1
assign wach_din = {S_AXI_AWADDR, S_AXI_AWPROT};
assign M_AXI_AWADDR = wach_dout[C_DIN_WIDTH_WACH-1:AWADDR_OFFSET];
assign M_AXI_AWPROT = wach_dout[AWADDR_OFFSET-1:AWPROT_OFFSET];
end endgenerate // axi_wach_output1
generate if (IS_AXI_LITE_WDCH == 1 || (IS_AXI_LITE == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output1
assign wdch_din = {S_AXI_WDATA, S_AXI_WSTRB};
assign M_AXI_WDATA = wdch_dout[C_DIN_WIDTH_WDCH-1:WDATA_OFFSET];
assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];
end endgenerate // axi_wdch_output1
generate if (IS_AXI_LITE_WRCH == 1 || (IS_AXI_LITE == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output1
assign wrch_din = M_AXI_BRESP;
assign S_AXI_BRESP = wrch_dout[C_DIN_WIDTH_WRCH-1:BRESP_OFFSET];
end endgenerate // axi_wrch_output1
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : gwach_din1
assign wach_din[AWREGION_OFFSET-1:AWUSER_OFFSET] = S_AXI_AWUSER;
end endgenerate // gwach_din1
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwach_din2
assign wach_din[C_DIN_WIDTH_WACH-1:AWID_OFFSET] = S_AXI_AWID;
end endgenerate // gwach_din2
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : gwach_din3
assign wach_din[AWQOS_OFFSET-1:AWREGION_OFFSET] = S_AXI_AWREGION;
end endgenerate // gwach_din3
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1) begin : gwdch_din1
assign wdch_din[WSTRB_OFFSET-1:WUSER_OFFSET] = S_AXI_WUSER;
end endgenerate // gwdch_din1
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin : gwdch_din2
assign wdch_din[C_DIN_WIDTH_WDCH-1:WID_OFFSET] = S_AXI_WID;
end endgenerate // gwdch_din2
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : gwrch_din1
assign wrch_din[BRESP_OFFSET-1:BUSER_OFFSET] = M_AXI_BUSER;
end endgenerate // gwrch_din1
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwrch_din2
assign wrch_din[C_DIN_WIDTH_WRCH-1:BID_OFFSET] = M_AXI_BID;
end endgenerate // gwrch_din2
//end of axi_write_channel
//###########################################################################
// AXI FULL Read Channel (axi_read_channel)
//###########################################################################
wire [C_DIN_WIDTH_RACH-1:0] rach_din ;
wire [C_DIN_WIDTH_RACH-1:0] rach_dout ;
wire [C_DIN_WIDTH_RACH-1:0] rach_dout_pkt ;
wire rach_full ;
wire rach_almost_full ;
wire rach_prog_full ;
wire rach_empty ;
wire rach_almost_empty ;
wire rach_prog_empty ;
wire [C_DIN_WIDTH_RDCH-1:0] rdch_din ;
wire [C_DIN_WIDTH_RDCH-1:0] rdch_dout ;
wire rdch_full ;
wire rdch_almost_full ;
wire rdch_prog_full ;
wire rdch_empty ;
wire rdch_almost_empty ;
wire rdch_prog_empty ;
wire axi_ar_underflow_i ;
wire axi_r_underflow_i ;
wire axi_ar_overflow_i ;
wire axi_r_overflow_i ;
wire axi_rd_underflow_i ;
wire axi_rd_overflow_i ;
wire rach_s_axi_arready ;
wire rach_m_axi_arvalid ;
wire rach_wr_en ;
wire rach_rd_en ;
wire rdch_m_axi_rready ;
wire rdch_s_axi_rvalid ;
wire rdch_wr_en ;
wire rdch_rd_en ;
wire arvalid_pkt ;
wire arready_pkt ;
wire arvalid_en ;
wire rdch_rd_ok ;
wire accept_next_pkt ;
integer rdch_free_space ;
integer rdch_commited_space ;
wire rach_we ;
wire rach_re ;
wire rdch_we ;
wire rdch_re ;
localparam ARID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RACH;
localparam ARADDR_OFFSET = ARID_OFFSET - C_AXI_ADDR_WIDTH;
localparam ARLEN_OFFSET = C_AXI_TYPE != 2 ? ARADDR_OFFSET - C_AXI_LEN_WIDTH : ARADDR_OFFSET;
localparam ARSIZE_OFFSET = C_AXI_TYPE != 2 ? ARLEN_OFFSET - C_AXI_SIZE_WIDTH : ARLEN_OFFSET;
localparam ARBURST_OFFSET = C_AXI_TYPE != 2 ? ARSIZE_OFFSET - C_AXI_BURST_WIDTH : ARSIZE_OFFSET;
localparam ARLOCK_OFFSET = C_AXI_TYPE != 2 ? ARBURST_OFFSET - C_AXI_LOCK_WIDTH : ARBURST_OFFSET;
localparam ARCACHE_OFFSET = C_AXI_TYPE != 2 ? ARLOCK_OFFSET - C_AXI_CACHE_WIDTH : ARLOCK_OFFSET;
localparam ARPROT_OFFSET = ARCACHE_OFFSET - C_AXI_PROT_WIDTH;
localparam ARQOS_OFFSET = ARPROT_OFFSET - C_AXI_QOS_WIDTH;
localparam ARREGION_OFFSET = C_AXI_TYPE == 1 ? ARQOS_OFFSET - C_AXI_REGION_WIDTH : ARQOS_OFFSET;
localparam ARUSER_OFFSET = C_HAS_AXI_ARUSER == 1 ? ARREGION_OFFSET-C_AXI_ARUSER_WIDTH : ARREGION_OFFSET;
localparam RID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RDCH;
localparam RDATA_OFFSET = RID_OFFSET - C_AXI_DATA_WIDTH;
localparam RRESP_OFFSET = RDATA_OFFSET - C_AXI_RRESP_WIDTH;
localparam RUSER_OFFSET = C_HAS_AXI_RUSER == 1 ? RRESP_OFFSET-C_AXI_RUSER_WIDTH : RRESP_OFFSET;
generate if (IS_RD_ADDR_CH == 1) begin : axi_read_addr_channel
// Write protection when almost full or prog_full is high
assign rach_we = (C_PROG_FULL_TYPE_RACH != 0) ? rach_s_axi_arready & S_AXI_ARVALID : S_AXI_ARVALID;
// Read protection when almost empty or prog_empty is high
// assign rach_rd_en = (C_PROG_EMPTY_TYPE_RACH != 5) ? rach_m_axi_arvalid & M_AXI_ARREADY : M_AXI_ARREADY && arvalid_en;
assign rach_re = (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH == 1) ?
rach_m_axi_arvalid & arready_pkt & arvalid_en :
(C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH != 1) ?
M_AXI_ARREADY && rach_m_axi_arvalid :
(C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH == 1) ?
arready_pkt & arvalid_en :
(C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH != 1) ?
M_AXI_ARREADY : 1'b0;
assign rach_wr_en = (C_HAS_SLAVE_CE == 1) ? rach_we & S_ACLK_EN : rach_we;
assign rach_rd_en = (C_HAS_MASTER_CE == 1) ? rach_re & M_ACLK_EN : rach_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_RACH == 2 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_RACH == 11 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_RACH),
.C_WR_DEPTH (C_WR_DEPTH_RACH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_RACH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_DOUT_WIDTH (C_DIN_WIDTH_RACH),
.C_RD_DEPTH (C_WR_DEPTH_RACH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_RACH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_RACH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_RACH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_RACH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH),
.C_USE_ECC (C_USE_ECC_RACH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RACH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE ((C_APPLICATION_TYPE_RACH == 1)?0:C_APPLICATION_TYPE_RACH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_rach_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (rach_wr_en),
.RD_EN (rach_rd_en),
.PROG_FULL_THRESH (AXI_AR_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_AR_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.INJECTDBITERR (AXI_AR_INJECTDBITERR),
.INJECTSBITERR (AXI_AR_INJECTSBITERR),
.DIN (rach_din),
.DOUT (rach_dout_pkt),
.FULL (rach_full),
.EMPTY (rach_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_AR_PROG_FULL),
.PROG_EMPTY (AXI_AR_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_ar_overflow_i),
.VALID (),
.UNDERFLOW (axi_ar_underflow_i),
.DATA_COUNT (AXI_AR_DATA_COUNT),
.RD_DATA_COUNT (AXI_AR_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_AR_WR_DATA_COUNT),
.SBITERR (AXI_AR_SBITERR),
.DBITERR (AXI_AR_DBITERR),
.wr_rst_busy (wr_rst_busy_rach),
.rd_rst_busy (rd_rst_busy_rach),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign rach_s_axi_arready = (IS_8SERIES == 0) ? ~rach_full : (C_IMPLEMENTATION_TYPE_RACH == 5 || C_IMPLEMENTATION_TYPE_RACH == 13) ? ~(rach_full | wr_rst_busy_rach) : ~rach_full;
assign rach_m_axi_arvalid = ~rach_empty;
assign S_AXI_ARREADY = rach_s_axi_arready;
assign AXI_AR_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_ar_underflow_i : 0;
assign AXI_AR_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_ar_overflow_i : 0;
end endgenerate // axi_read_addr_channel
// Register Slice for Read Address Channel
generate if (C_RACH_TYPE == 1) begin : grach_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RACH),
.C_REG_CONFIG (C_REG_SLICE_MODE_RACH)
)
rach_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (rach_din),
.S_VALID (S_AXI_ARVALID),
.S_READY (S_AXI_ARREADY),
// Master side
.M_PAYLOAD_DATA (rach_dout),
.M_VALID (M_AXI_ARVALID),
.M_READY (M_AXI_ARREADY)
);
end endgenerate // grach_reg_slice
// Register Slice for Read Address Channel for MM Packet FIFO
generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH == 1) begin : grach_reg_slice_mm_pkt_fifo
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RACH),
.C_REG_CONFIG (1)
)
reg_slice_mm_pkt_fifo_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (inverted_reset),
// Slave side
.S_PAYLOAD_DATA (rach_dout_pkt),
.S_VALID (arvalid_pkt),
.S_READY (arready_pkt),
// Master side
.M_PAYLOAD_DATA (rach_dout),
.M_VALID (M_AXI_ARVALID),
.M_READY (M_AXI_ARREADY)
);
end endgenerate // grach_reg_slice_mm_pkt_fifo
generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH != 1) begin : grach_m_axi_arvalid
assign M_AXI_ARVALID = rach_m_axi_arvalid;
assign rach_dout = rach_dout_pkt;
end endgenerate // grach_m_axi_arvalid
generate if (C_APPLICATION_TYPE_RACH == 1 && C_HAS_AXI_RD_CHANNEL == 1) begin : axi_mm_pkt_fifo_rd
assign rdch_rd_ok = rdch_s_axi_rvalid && rdch_rd_en;
assign arvalid_pkt = rach_m_axi_arvalid && arvalid_en;
assign accept_next_pkt = rach_m_axi_arvalid && arready_pkt && arvalid_en;
always@(posedge S_ACLK or posedge inverted_reset) begin
if(inverted_reset) begin
rdch_commited_space <= 0;
end else begin
if(rdch_rd_ok && !accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space-1;
end else if(!rdch_rd_ok && accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1);
end else if(rdch_rd_ok && accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]);
end
end
end //Always end
always@(*) begin
rdch_free_space <= (C_WR_DEPTH_RDCH-(rdch_commited_space+rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1));
end
assign arvalid_en = (rdch_free_space >= 0)?1:0;
end
endgenerate
generate if (C_APPLICATION_TYPE_RACH != 1) begin : axi_mm_fifo_rd
assign arvalid_en = 1;
end
endgenerate
generate if (IS_RD_DATA_CH == 1) begin : axi_read_data_channel
// Write protection when almost full or prog_full is high
assign rdch_we = (C_PROG_FULL_TYPE_RDCH != 0) ? rdch_m_axi_rready & M_AXI_RVALID : M_AXI_RVALID;
// Read protection when almost empty or prog_empty is high
assign rdch_re = (C_PROG_EMPTY_TYPE_RDCH != 0) ? rdch_s_axi_rvalid & S_AXI_RREADY : S_AXI_RREADY;
assign rdch_wr_en = (C_HAS_MASTER_CE == 1) ? rdch_we & M_ACLK_EN : rdch_we;
assign rdch_rd_en = (C_HAS_SLAVE_CE == 1) ? rdch_re & S_ACLK_EN : rdch_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_RDCH == 2 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_RDCH == 11 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_RDCH),
.C_WR_DEPTH (C_WR_DEPTH_RDCH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_RDCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_RDCH),
.C_RD_DEPTH (C_WR_DEPTH_RDCH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_RDCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_RDCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_RDCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_RDCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH),
.C_USE_ECC (C_USE_ECC_RDCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RDCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_RDCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_rdch_dut
(
.CLK (S_ACLK),
.WR_CLK (M_ACLK),
.RD_CLK (S_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (rdch_wr_en),
.RD_EN (rdch_rd_en),
.PROG_FULL_THRESH (AXI_R_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_R_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.INJECTDBITERR (AXI_R_INJECTDBITERR),
.INJECTSBITERR (AXI_R_INJECTSBITERR),
.DIN (rdch_din),
.DOUT (rdch_dout),
.FULL (rdch_full),
.EMPTY (rdch_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_R_PROG_FULL),
.PROG_EMPTY (AXI_R_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_r_overflow_i),
.VALID (),
.UNDERFLOW (axi_r_underflow_i),
.DATA_COUNT (AXI_R_DATA_COUNT),
.RD_DATA_COUNT (AXI_R_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_R_WR_DATA_COUNT),
.SBITERR (AXI_R_SBITERR),
.DBITERR (AXI_R_DBITERR),
.wr_rst_busy (wr_rst_busy_rdch),
.rd_rst_busy (rd_rst_busy_rdch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign rdch_s_axi_rvalid = ~rdch_empty;
assign rdch_m_axi_rready = (IS_8SERIES == 0) ? ~rdch_full : (C_IMPLEMENTATION_TYPE_RDCH == 5 || C_IMPLEMENTATION_TYPE_RDCH == 13) ? ~(rdch_full | wr_rst_busy_rdch) : ~rdch_full;
assign S_AXI_RVALID = rdch_s_axi_rvalid;
assign M_AXI_RREADY = rdch_m_axi_rready;
assign AXI_R_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_r_underflow_i : 0;
assign AXI_R_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_r_overflow_i : 0;
end endgenerate //axi_read_data_channel
// Register Slice for read Data Channel
generate if (C_RDCH_TYPE == 1) begin : grdch_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RDCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_RDCH)
)
rdch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (rdch_din),
.S_VALID (M_AXI_RVALID),
.S_READY (M_AXI_RREADY),
// Master side
.M_PAYLOAD_DATA (rdch_dout),
.M_VALID (S_AXI_RVALID),
.M_READY (S_AXI_RREADY)
);
end endgenerate // grdch_reg_slice
assign axi_rd_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_ar_underflow_i || axi_r_underflow_i) : 0;
assign axi_rd_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_ar_overflow_i || axi_r_overflow_i) : 0;
generate if (IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) begin : axi_full_rach_output
assign M_AXI_ARADDR = rach_dout[ARID_OFFSET-1:ARADDR_OFFSET];
assign M_AXI_ARLEN = rach_dout[ARADDR_OFFSET-1:ARLEN_OFFSET];
assign M_AXI_ARSIZE = rach_dout[ARLEN_OFFSET-1:ARSIZE_OFFSET];
assign M_AXI_ARBURST = rach_dout[ARSIZE_OFFSET-1:ARBURST_OFFSET];
assign M_AXI_ARLOCK = rach_dout[ARBURST_OFFSET-1:ARLOCK_OFFSET];
assign M_AXI_ARCACHE = rach_dout[ARLOCK_OFFSET-1:ARCACHE_OFFSET];
assign M_AXI_ARPROT = rach_dout[ARCACHE_OFFSET-1:ARPROT_OFFSET];
assign M_AXI_ARQOS = rach_dout[ARPROT_OFFSET-1:ARQOS_OFFSET];
assign rach_din[ARID_OFFSET-1:ARADDR_OFFSET] = S_AXI_ARADDR;
assign rach_din[ARADDR_OFFSET-1:ARLEN_OFFSET] = S_AXI_ARLEN;
assign rach_din[ARLEN_OFFSET-1:ARSIZE_OFFSET] = S_AXI_ARSIZE;
assign rach_din[ARSIZE_OFFSET-1:ARBURST_OFFSET] = S_AXI_ARBURST;
assign rach_din[ARBURST_OFFSET-1:ARLOCK_OFFSET] = S_AXI_ARLOCK;
assign rach_din[ARLOCK_OFFSET-1:ARCACHE_OFFSET] = S_AXI_ARCACHE;
assign rach_din[ARCACHE_OFFSET-1:ARPROT_OFFSET] = S_AXI_ARPROT;
assign rach_din[ARPROT_OFFSET-1:ARQOS_OFFSET] = S_AXI_ARQOS;
end endgenerate // axi_full_rach_output
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_arregion
assign M_AXI_ARREGION = rach_dout[ARQOS_OFFSET-1:ARREGION_OFFSET];
end endgenerate // axi_arregion
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_arregion
assign M_AXI_ARREGION = 0;
end endgenerate // naxi_arregion
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : axi_aruser
assign M_AXI_ARUSER = rach_dout[ARREGION_OFFSET-1:ARUSER_OFFSET];
end endgenerate // axi_aruser
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 0) begin : naxi_aruser
assign M_AXI_ARUSER = 0;
end endgenerate // naxi_aruser
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_arid
assign M_AXI_ARID = rach_dout[C_DIN_WIDTH_RACH-1:ARID_OFFSET];
end endgenerate // axi_arid
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_arid
assign M_AXI_ARID = 0;
end endgenerate // naxi_arid
generate if (IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) begin : axi_full_rdch_output
assign S_AXI_RDATA = rdch_dout[RID_OFFSET-1:RDATA_OFFSET];
assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];
assign S_AXI_RLAST = rdch_dout[0];
assign rdch_din[RID_OFFSET-1:RDATA_OFFSET] = M_AXI_RDATA;
assign rdch_din[RDATA_OFFSET-1:RRESP_OFFSET] = M_AXI_RRESP;
assign rdch_din[0] = M_AXI_RLAST;
end endgenerate // axi_full_rdch_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : axi_full_ruser_output
assign S_AXI_RUSER = rdch_dout[RRESP_OFFSET-1:RUSER_OFFSET];
end endgenerate // axi_full_ruser_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 0) begin : axi_full_nruser_output
assign S_AXI_RUSER = 0;
end endgenerate // axi_full_nruser_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_rid
assign S_AXI_RID = rdch_dout[C_DIN_WIDTH_RDCH-1:RID_OFFSET];
end endgenerate // axi_rid
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_rid
assign S_AXI_RID = 0;
end endgenerate // naxi_rid
generate if (IS_AXI_LITE_RACH == 1 || (IS_AXI_LITE == 1 && C_RACH_TYPE == 1)) begin : axi_lite_rach_output1
assign rach_din = {S_AXI_ARADDR, S_AXI_ARPROT};
assign M_AXI_ARADDR = rach_dout[C_DIN_WIDTH_RACH-1:ARADDR_OFFSET];
assign M_AXI_ARPROT = rach_dout[ARADDR_OFFSET-1:ARPROT_OFFSET];
end endgenerate // axi_lite_rach_output
generate if (IS_AXI_LITE_RDCH == 1 || (IS_AXI_LITE == 1 && C_RDCH_TYPE == 1)) begin : axi_lite_rdch_output1
assign rdch_din = {M_AXI_RDATA, M_AXI_RRESP};
assign S_AXI_RDATA = rdch_dout[C_DIN_WIDTH_RDCH-1:RDATA_OFFSET];
assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];
end endgenerate // axi_lite_rdch_output
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : grach_din1
assign rach_din[ARREGION_OFFSET-1:ARUSER_OFFSET] = S_AXI_ARUSER;
end endgenerate // grach_din1
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grach_din2
assign rach_din[C_DIN_WIDTH_RACH-1:ARID_OFFSET] = S_AXI_ARID;
end endgenerate // grach_din2
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin
assign rach_din[ARQOS_OFFSET-1:ARREGION_OFFSET] = S_AXI_ARREGION;
end endgenerate
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : grdch_din1
assign rdch_din[RRESP_OFFSET-1:RUSER_OFFSET] = M_AXI_RUSER;
end endgenerate // grdch_din1
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grdch_din2
assign rdch_din[C_DIN_WIDTH_RDCH-1:RID_OFFSET] = M_AXI_RID;
end endgenerate // grdch_din2
//end of axi_read_channel
generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_UNDERFLOW == 1) begin : gaxi_comm_uf
assign UNDERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_underflow_i || axi_rd_underflow_i) :
(C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_underflow_i :
(C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_underflow_i : 0;
end endgenerate // gaxi_comm_uf
generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_OVERFLOW == 1) begin : gaxi_comm_of
assign OVERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_overflow_i || axi_rd_overflow_i) :
(C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_overflow_i :
(C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_overflow_i : 0;
end endgenerate // gaxi_comm_of
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
// Pass Through Logic or Wiring Logic
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
// Pass Through Logic for Read Channel
//-------------------------------------------------------------------------
// Wiring logic for Write Address Channel
generate if (C_WACH_TYPE == 2) begin : gwach_pass_through
assign M_AXI_AWID = S_AXI_AWID;
assign M_AXI_AWADDR = S_AXI_AWADDR;
assign M_AXI_AWLEN = S_AXI_AWLEN;
assign M_AXI_AWSIZE = S_AXI_AWSIZE;
assign M_AXI_AWBURST = S_AXI_AWBURST;
assign M_AXI_AWLOCK = S_AXI_AWLOCK;
assign M_AXI_AWCACHE = S_AXI_AWCACHE;
assign M_AXI_AWPROT = S_AXI_AWPROT;
assign M_AXI_AWQOS = S_AXI_AWQOS;
assign M_AXI_AWREGION = S_AXI_AWREGION;
assign M_AXI_AWUSER = S_AXI_AWUSER;
assign S_AXI_AWREADY = M_AXI_AWREADY;
assign M_AXI_AWVALID = S_AXI_AWVALID;
end endgenerate // gwach_pass_through;
// Wiring logic for Write Data Channel
generate if (C_WDCH_TYPE == 2) begin : gwdch_pass_through
assign M_AXI_WID = S_AXI_WID;
assign M_AXI_WDATA = S_AXI_WDATA;
assign M_AXI_WSTRB = S_AXI_WSTRB;
assign M_AXI_WLAST = S_AXI_WLAST;
assign M_AXI_WUSER = S_AXI_WUSER;
assign S_AXI_WREADY = M_AXI_WREADY;
assign M_AXI_WVALID = S_AXI_WVALID;
end endgenerate // gwdch_pass_through;
// Wiring logic for Write Response Channel
generate if (C_WRCH_TYPE == 2) begin : gwrch_pass_through
assign S_AXI_BID = M_AXI_BID;
assign S_AXI_BRESP = M_AXI_BRESP;
assign S_AXI_BUSER = M_AXI_BUSER;
assign M_AXI_BREADY = S_AXI_BREADY;
assign S_AXI_BVALID = M_AXI_BVALID;
end endgenerate // gwrch_pass_through;
//-------------------------------------------------------------------------
// Pass Through Logic for Read Channel
//-------------------------------------------------------------------------
// Wiring logic for Read Address Channel
generate if (C_RACH_TYPE == 2) begin : grach_pass_through
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARQOS = S_AXI_ARQOS;
assign M_AXI_ARREGION = S_AXI_ARREGION;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign S_AXI_ARREADY = M_AXI_ARREADY;
assign M_AXI_ARVALID = S_AXI_ARVALID;
end endgenerate // grach_pass_through;
// Wiring logic for Read Data Channel
generate if (C_RDCH_TYPE == 2) begin : grdch_pass_through
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
end endgenerate // grdch_pass_through;
// Wiring logic for AXI Streaming
generate if (C_AXIS_TYPE == 2) begin : gaxis_pass_through
assign M_AXIS_TDATA = S_AXIS_TDATA;
assign M_AXIS_TSTRB = S_AXIS_TSTRB;
assign M_AXIS_TKEEP = S_AXIS_TKEEP;
assign M_AXIS_TID = S_AXIS_TID;
assign M_AXIS_TDEST = S_AXIS_TDEST;
assign M_AXIS_TUSER = S_AXIS_TUSER;
assign M_AXIS_TLAST = S_AXIS_TLAST;
assign S_AXIS_TREADY = M_AXIS_TREADY;
assign M_AXIS_TVALID = S_AXIS_TVALID;
end endgenerate // gaxis_pass_through;
endmodule //fifo_generator_v13_1_3
/*******************************************************************************
* Declaration of top-level module for Conventional FIFO
******************************************************************************/
module fifo_generator_v13_1_3_CONV_VER
#(
parameter C_COMMON_CLOCK = 0,
parameter C_INTERFACE_TYPE = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_COUNT_TYPE = 0,
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DEFAULT_VALUE = "",
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_ENABLE_RLOCS = 0,
parameter C_FAMILY = "virtex7", //Not allowed in Verilog model
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_BACKUP = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_INT_CLK = 0,
parameter C_HAS_MEMINIT_FILE = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RD_RST = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_HAS_WR_RST = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_INIT_WR_PNTR_VAL = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_MIF_FILE_NAME = "",
parameter C_OPTIMIZATION_MODE = 0,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PRIM_FIFO_TYPE = "",
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_FREQ = 1,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_USE_FIFO16_FLAGS = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_FREQ = 1,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_WR_RESPONSE_LATENCY = 1,
parameter C_MSGON_VAL = 1,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_FIFO_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2,
parameter C_AXI_TYPE = 0
)
(
input BACKUP,
input BACKUP_MARKER,
input CLK,
input RST,
input SRST,
input WR_CLK,
input WR_RST,
input RD_CLK,
input RD_RST,
input [C_DIN_WIDTH-1:0] DIN,
input WR_EN,
input RD_EN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input INT_CLK,
input INJECTDBITERR,
input INJECTSBITERR,
output [C_DOUT_WIDTH-1:0] DOUT,
output FULL,
output ALMOST_FULL,
output WR_ACK,
output OVERFLOW,
output EMPTY,
output ALMOST_EMPTY,
output VALID,
output UNDERFLOW,
output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output PROG_FULL,
output PROG_EMPTY,
output SBITERR,
output DBITERR,
output wr_rst_busy_o,
output wr_rst_busy,
output rd_rst_busy,
output wr_rst_i_out,
output rd_rst_i_out
);
/*
******************************************************************************
* Definition of Parameters
******************************************************************************
* C_COMMON_CLOCK : Common Clock (1), Independent Clocks (0)
* C_COUNT_TYPE : *not used
* C_DATA_COUNT_WIDTH : Width of DATA_COUNT bus
* C_DEFAULT_VALUE : *not used
* C_DIN_WIDTH : Width of DIN bus
* C_DOUT_RST_VAL : Reset value of DOUT
* C_DOUT_WIDTH : Width of DOUT bus
* C_ENABLE_RLOCS : *not used
* C_FAMILY : not used in bhv model
* C_FULL_FLAGS_RST_VAL : Full flags rst val (0 or 1)
* C_HAS_ALMOST_EMPTY : 1=Core has ALMOST_EMPTY flag
* C_HAS_ALMOST_FULL : 1=Core has ALMOST_FULL flag
* C_HAS_BACKUP : *not used
* C_HAS_DATA_COUNT : 1=Core has DATA_COUNT bus
* C_HAS_INT_CLK : not used in bhv model
* C_HAS_MEMINIT_FILE : *not used
* C_HAS_OVERFLOW : 1=Core has OVERFLOW flag
* C_HAS_RD_DATA_COUNT : 1=Core has RD_DATA_COUNT bus
* C_HAS_RD_RST : *not used
* C_HAS_RST : 1=Core has Async Rst
* C_HAS_SRST : 1=Core has Sync Rst
* C_HAS_UNDERFLOW : 1=Core has UNDERFLOW flag
* C_HAS_VALID : 1=Core has VALID flag
* C_HAS_WR_ACK : 1=Core has WR_ACK flag
* C_HAS_WR_DATA_COUNT : 1=Core has WR_DATA_COUNT bus
* C_HAS_WR_RST : *not used
* C_IMPLEMENTATION_TYPE : 0=Common-Clock Bram/Dram
* 1=Common-Clock ShiftRam
* 2=Indep. Clocks Bram/Dram
* 3=Virtex-4 Built-in
* 4=Virtex-5 Built-in
* C_INIT_WR_PNTR_VAL : *not used
* C_MEMORY_TYPE : 1=Block RAM
* 2=Distributed RAM
* 3=Shift RAM
* 4=Built-in FIFO
* C_MIF_FILE_NAME : *not used
* C_OPTIMIZATION_MODE : *not used
* C_OVERFLOW_LOW : 1=OVERFLOW active low
* C_PRELOAD_LATENCY : Latency of read: 0, 1, 2
* C_PRELOAD_REGS : 1=Use output registers
* C_PRIM_FIFO_TYPE : not used in bhv model
* C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold
* C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold
* C_PROG_EMPTY_TYPE : 0=No programmable empty
* 1=Single prog empty thresh constant
* 2=Multiple prog empty thresh constants
* 3=Single prog empty thresh input
* 4=Multiple prog empty thresh inputs
* C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold
* C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold
* C_PROG_FULL_TYPE : 0=No prog full
* 1=Single prog full thresh constant
* 2=Multiple prog full thresh constants
* 3=Single prog full thresh input
* 4=Multiple prog full thresh inputs
* C_RD_DATA_COUNT_WIDTH : Width of RD_DATA_COUNT bus
* C_RD_DEPTH : Depth of read interface (2^N)
* C_RD_FREQ : not used in bhv model
* C_RD_PNTR_WIDTH : always log2(C_RD_DEPTH)
* C_UNDERFLOW_LOW : 1=UNDERFLOW active low
* C_USE_DOUT_RST : 1=Resets DOUT on RST
* C_USE_ECC : Used for error injection purpose
* C_USE_EMBEDDED_REG : 1=Use BRAM embedded output register
* C_USE_FIFO16_FLAGS : not used in bhv model
* C_USE_FWFT_DATA_COUNT : 1=Use extra logic for FWFT data count
* C_VALID_LOW : 1=VALID active low
* C_WR_ACK_LOW : 1=WR_ACK active low
* C_WR_DATA_COUNT_WIDTH : Width of WR_DATA_COUNT bus
* C_WR_DEPTH : Depth of write interface (2^N)
* C_WR_FREQ : not used in bhv model
* C_WR_PNTR_WIDTH : always log2(C_WR_DEPTH)
* C_WR_RESPONSE_LATENCY : *not used
* C_MSGON_VAL : *not used by bhv model
* C_ENABLE_RST_SYNC : 0 = Use WR_RST & RD_RST
* 1 = Use RST
* C_ERROR_INJECTION_TYPE : 0 = No error injection
* 1 = Single bit error injection only
* 2 = Double bit error injection only
* 3 = Single and double bit error injection
******************************************************************************
* Definition of Ports
******************************************************************************
* BACKUP : Not used
* BACKUP_MARKER: Not used
* CLK : Clock
* DIN : Input data bus
* PROG_EMPTY_THRESH : Threshold for Programmable Empty Flag
* PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag
* PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag
* PROG_FULL_THRESH : Threshold for Programmable Full Flag
* PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag
* PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag
* RD_CLK : Read Domain Clock
* RD_EN : Read enable
* RD_RST : Read Reset
* RST : Asynchronous Reset
* SRST : Synchronous Reset
* WR_CLK : Write Domain Clock
* WR_EN : Write enable
* WR_RST : Write Reset
* INT_CLK : Internal Clock
* INJECTSBITERR: Inject Signle bit error
* INJECTDBITERR: Inject Double bit error
* ALMOST_EMPTY : One word remaining in FIFO
* ALMOST_FULL : One empty space remaining in FIFO
* DATA_COUNT : Number of data words in fifo( synchronous to CLK)
* DOUT : Output data bus
* EMPTY : Empty flag
* FULL : Full flag
* OVERFLOW : Last write rejected
* PROG_EMPTY : Programmable Empty Flag
* PROG_FULL : Programmable Full Flag
* RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK)
* UNDERFLOW : Last read rejected
* VALID : Last read acknowledged, DOUT bus VALID
* WR_ACK : Last write acknowledged
* WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK)
* SBITERR : Single Bit ECC Error Detected
* DBITERR : Double Bit ECC Error Detected
******************************************************************************
*/
//----------------------------------------------------------------------------
//- Internal Signals for delayed input signals
//- All the input signals except Clock are delayed by 100 ps and then given to
//- the models.
//----------------------------------------------------------------------------
reg rst_delayed ;
reg empty_fb ;
reg srst_delayed ;
reg wr_rst_delayed ;
reg rd_rst_delayed ;
reg wr_en_delayed ;
reg rd_en_delayed ;
reg [C_DIN_WIDTH-1:0] din_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate_delayed ;
reg injectdbiterr_delayed ;
reg injectsbiterr_delayed ;
wire empty_p0_out;
always @* rst_delayed <= #`TCQ RST ;
always @* empty_fb <= #`TCQ empty_p0_out ;
always @* srst_delayed <= #`TCQ SRST ;
always @* wr_rst_delayed <= #`TCQ WR_RST ;
always @* rd_rst_delayed <= #`TCQ RD_RST ;
always @* din_delayed <= #`TCQ DIN ;
always @* wr_en_delayed <= #`TCQ WR_EN ;
always @* rd_en_delayed <= #`TCQ RD_EN ;
always @* prog_empty_thresh_delayed <= #`TCQ PROG_EMPTY_THRESH ;
always @* prog_empty_thresh_assert_delayed <= #`TCQ PROG_EMPTY_THRESH_ASSERT ;
always @* prog_empty_thresh_negate_delayed <= #`TCQ PROG_EMPTY_THRESH_NEGATE ;
always @* prog_full_thresh_delayed <= #`TCQ PROG_FULL_THRESH ;
always @* prog_full_thresh_assert_delayed <= #`TCQ PROG_FULL_THRESH_ASSERT ;
always @* prog_full_thresh_negate_delayed <= #`TCQ PROG_FULL_THRESH_NEGATE ;
always @* injectdbiterr_delayed <= #`TCQ INJECTDBITERR ;
always @* injectsbiterr_delayed <= #`TCQ INJECTSBITERR ;
/*****************************************************************************
* Derived parameters
****************************************************************************/
//There are 2 Verilog behavioral models
// 0 = Common-Clock FIFO/ShiftRam FIFO
// 1 = Independent Clocks FIFO
// 2 = Low Latency Synchronous FIFO
// 3 = Low Latency Asynchronous FIFO
localparam C_VERILOG_IMPL = (C_FIFO_TYPE == 3) ? 2 :
(C_IMPLEMENTATION_TYPE == 2) ? 1 : 0;
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
//Internal reset signals
reg rd_rst_asreg = 0;
wire rd_rst_asreg_d1;
wire rd_rst_asreg_d2;
reg rd_rst_asreg_d3 = 0;
reg rd_rst_reg = 0;
wire rd_rst_comb;
reg wr_rst_d0 = 0;
reg wr_rst_d1 = 0;
reg wr_rst_d2 = 0;
reg rd_rst_d0 = 0;
reg rd_rst_d1 = 0;
reg rd_rst_d2 = 0;
reg rd_rst_d3 = 0;
reg wrrst_done = 0;
reg rdrst_done = 0;
reg wr_rst_asreg = 0;
wire wr_rst_asreg_d1;
wire wr_rst_asreg_d2;
reg wr_rst_asreg_d3 = 0;
reg rd_rst_wr_d0 = 0;
reg rd_rst_wr_d1 = 0;
reg rd_rst_wr_d2 = 0;
reg wr_rst_reg = 0;
reg rst_active_i = 1'b1;
reg rst_delayed_d1 = 1'b1;
reg rst_delayed_d2 = 1'b1;
wire wr_rst_comb;
wire wr_rst_i;
wire rd_rst_i;
wire rst_i;
//Internal reset signals
reg rst_asreg = 0;
reg srst_asreg = 0;
wire rst_asreg_d1;
wire rst_asreg_d2;
reg srst_asreg_d1 = 0;
reg srst_asreg_d2 = 0;
reg rst_reg = 0;
reg srst_reg = 0;
wire rst_comb;
wire srst_comb;
reg rst_full_gen_i = 0;
reg rst_full_ff_i = 0;
reg [2:0] sckt_ff0_bsy_o_i = {3{1'b0}};
wire RD_CLK_P0_IN;
wire RST_P0_IN;
wire RD_EN_FIFO_IN;
wire RD_EN_P0_IN;
wire ALMOST_EMPTY_FIFO_OUT;
wire ALMOST_FULL_FIFO_OUT;
wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT_FIFO_OUT;
wire [C_DOUT_WIDTH-1:0] DOUT_FIFO_OUT;
wire EMPTY_FIFO_OUT;
wire fifo_empty_fb;
wire FULL_FIFO_OUT;
wire OVERFLOW_FIFO_OUT;
wire PROG_EMPTY_FIFO_OUT;
wire PROG_FULL_FIFO_OUT;
wire VALID_FIFO_OUT;
wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT_FIFO_OUT;
wire UNDERFLOW_FIFO_OUT;
wire WR_ACK_FIFO_OUT;
wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT_FIFO_OUT;
//***************************************************************************
// Internal Signals
// The core uses either the internal_ wires or the preload0_ wires depending
// on whether the core uses Preload0 or not.
// When using preload0, the internal signals connect the internal core to
// the preload logic, and the external core's interfaces are tied to the
// preload0 signals from the preload logic.
//***************************************************************************
wire [C_DOUT_WIDTH-1:0] DATA_P0_OUT;
wire VALID_P0_OUT;
wire EMPTY_P0_OUT;
wire ALMOSTEMPTY_P0_OUT;
reg EMPTY_P0_OUT_Q;
reg ALMOSTEMPTY_P0_OUT_Q;
wire UNDERFLOW_P0_OUT;
wire RDEN_P0_OUT;
wire [C_DOUT_WIDTH-1:0] DATA_P0_IN;
wire EMPTY_P0_IN;
reg [31:0] DATA_COUNT_FWFT;
reg SS_FWFT_WR ;
reg SS_FWFT_RD ;
wire sbiterr_fifo_out;
wire dbiterr_fifo_out;
wire inject_sbit_err;
wire inject_dbit_err;
wire safety_ckt_wr_rst;
wire safety_ckt_rd_rst;
reg sckt_wr_rst_i_q = 1'b0;
wire w_fab_read_data_valid_i;
wire w_read_data_valid_i;
wire w_ram_valid_i;
// Assign 0 if not selected to avoid 'X' propogation to S/DBITERR.
assign inject_sbit_err = ((C_ERROR_INJECTION_TYPE == 1) || (C_ERROR_INJECTION_TYPE == 3)) ?
injectsbiterr_delayed : 0;
assign inject_dbit_err = ((C_ERROR_INJECTION_TYPE == 2) || (C_ERROR_INJECTION_TYPE == 3)) ?
injectdbiterr_delayed : 0;
assign wr_rst_i_out = wr_rst_i;
assign rd_rst_i_out = rd_rst_i;
assign wr_rst_busy_o = wr_rst_busy | rst_full_gen_i | sckt_ff0_bsy_o_i[2];
generate if (C_FULL_FLAGS_RST_VAL == 0 && C_EN_SAFETY_CKT == 1) begin : gsckt_bsy_o
wire clk_i = C_COMMON_CLOCK ? CLK : WR_CLK;
always @ (posedge clk_i)
sckt_ff0_bsy_o_i <= {sckt_ff0_bsy_o_i[1:0],wr_rst_busy};
end endgenerate
// Choose the behavioral model to instantiate based on the C_VERILOG_IMPL
// parameter (1=Independent Clocks, 0=Common Clock)
localparam FULL_FLAGS_RST_VAL = (C_HAS_SRST == 1) ? 0 : C_FULL_FLAGS_RST_VAL;
generate
case (C_VERILOG_IMPL)
0 : begin : block1
//Common Clock Behavioral Model
fifo_generator_v13_1_3_bhv_ver_ss
#(
.C_FAMILY (C_FAMILY),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL ((C_AXI_TYPE == 0 && C_FIFO_TYPE == 1) ? 1 : C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
gen_ss
(
.SAFETY_CKT_WR_RST (safety_ckt_wr_rst),
.CLK (CLK),
.RST (rst_i),
.SRST (srst_delayed),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.USER_EMPTY_FB (empty_fb),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.EMPTY_FB (fifo_empty_fb),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.DATA_COUNT (DATA_COUNT_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.WR_RST_BUSY (wr_rst_busy),
.RD_RST_BUSY (rd_rst_busy),
.SBITERR (sbiterr_fifo_out),
.DBITERR (dbiterr_fifo_out)
);
end
1 : begin : block1
//Independent Clocks Behavioral Model
fifo_generator_v13_1_3_bhv_ver_as
#(
.C_FAMILY (C_FAMILY),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_HAS_RST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE)
)
gen_as
(
.SAFETY_CKT_WR_RST (safety_ckt_wr_rst),
.SAFETY_CKT_RD_RST (safety_ckt_rd_rst),
.WR_CLK (WR_CLK),
.RD_CLK (RD_CLK),
.RST (rst_i),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.USER_EMPTY_FB (EMPTY_P0_OUT),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.EMPTY_FB (fifo_empty_fb),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.SBITERR (sbiterr_fifo_out),
.fab_read_data_valid_i (w_fab_read_data_valid_i),
.read_data_valid_i (w_read_data_valid_i),
.ram_valid_i (w_ram_valid_i),
.DBITERR (dbiterr_fifo_out)
);
end
2 : begin : ll_afifo_inst
fifo_generator_v13_1_3_beh_ver_ll_afifo
#(
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
gen_ll_afifo
(
.DIN (din_delayed),
.RD_CLK (RD_CLK),
.RD_EN (rd_en_delayed),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.WR_CLK (WR_CLK),
.WR_EN (wr_en_delayed),
.DOUT (DOUT),
.EMPTY (EMPTY),
.FULL (FULL)
);
end
default : begin : block1
//Independent Clocks Behavioral Model
fifo_generator_v13_1_3_bhv_ver_as
#(
.C_FAMILY (C_FAMILY),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_HAS_RST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE)
)
gen_as
(
.SAFETY_CKT_WR_RST (safety_ckt_wr_rst),
.SAFETY_CKT_RD_RST (safety_ckt_rd_rst),
.WR_CLK (WR_CLK),
.RD_CLK (RD_CLK),
.RST (rst_i),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.USER_EMPTY_FB (EMPTY_P0_OUT),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.EMPTY_FB (fifo_empty_fb),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.SBITERR (sbiterr_fifo_out),
.DBITERR (dbiterr_fifo_out)
);
end
endcase
endgenerate
//**************************************************************************
// Connect Internal Signals
// (Signals labeled internal_*)
// In the normal case, these signals tie directly to the FIFO's inputs and
// outputs.
// In the case of Preload Latency 0 or 1, there are intermediate
// signals between the internal FIFO and the preload logic.
//**************************************************************************
//***********************************************
// If First-Word Fall-Through, instantiate
// the preload0 (FWFT) module
//***********************************************
wire rd_en_to_fwft_fifo;
wire sbiterr_fwft;
wire dbiterr_fwft;
wire [C_DOUT_WIDTH-1:0] dout_fwft;
wire empty_fwft;
wire rd_en_fifo_in;
wire stage2_reg_en_i;
wire [1:0] valid_stages_i;
wire rst_fwft;
//wire empty_p0_out;
reg [C_SYNCHRONIZER_STAGE-1:0] pkt_empty_sync = 'b1;
localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;
localparam IS_PKT_FIFO = (C_FIFO_TYPE == 1) ? 1 : 0;
localparam IS_AXIS_PKT_FIFO = (C_FIFO_TYPE == 1 && C_AXI_TYPE == 0) ? 1 : 0;
assign rst_fwft = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 1'b0;
generate if (IS_FWFT == 1 && C_FIFO_TYPE != 3) begin : block2
fifo_generator_v13_1_3_bhv_ver_preload0
#(
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_HAS_RST (C_HAS_RST),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_HAS_SRST (C_HAS_SRST),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_USE_ECC (C_USE_ECC),
.C_USERVALID_LOW (C_VALID_LOW),
.C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
fgpl0
(
.SAFETY_CKT_RD_RST(safety_ckt_rd_rst),
.RD_CLK (RD_CLK_P0_IN),
.RD_RST (RST_P0_IN),
.SRST (srst_delayed),
.WR_RST_BUSY (wr_rst_busy),
.RD_RST_BUSY (rd_rst_busy),
.RD_EN (RD_EN_P0_IN),
.FIFOEMPTY (EMPTY_P0_IN),
.FIFODATA (DATA_P0_IN),
.FIFOSBITERR (sbiterr_fifo_out),
.FIFODBITERR (dbiterr_fifo_out),
// Output
.USERDATA (dout_fwft),
.USERVALID (VALID_P0_OUT),
.USEREMPTY (empty_fwft),
.USERALMOSTEMPTY (ALMOSTEMPTY_P0_OUT),
.USERUNDERFLOW (UNDERFLOW_P0_OUT),
.RAMVALID (),
.FIFORDEN (rd_en_fifo_in),
.USERSBITERR (sbiterr_fwft),
.USERDBITERR (dbiterr_fwft),
.STAGE2_REG_EN (stage2_reg_en_i),
.fab_read_data_valid_i_o (w_fab_read_data_valid_i),
.read_data_valid_i_o (w_read_data_valid_i),
.ram_valid_i_o (w_ram_valid_i),
.VALID_STAGES (valid_stages_i)
);
//***********************************************
// Connect inputs to preload (FWFT) module
//***********************************************
//Connect the RD_CLK of the Preload (FWFT) module to CLK if we
// have a common-clock FIFO, or RD_CLK if we have an
// independent clock FIFO
assign RD_CLK_P0_IN = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK);
assign RST_P0_IN = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 0;
assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;
assign EMPTY_P0_IN = C_EN_SAFETY_CKT ? fifo_empty_fb : EMPTY_FIFO_OUT;
assign DATA_P0_IN = DOUT_FIFO_OUT;
//***********************************************
// Connect outputs from preload (FWFT) module
//***********************************************
assign VALID = VALID_P0_OUT ;
assign ALMOST_EMPTY = ALMOSTEMPTY_P0_OUT;
assign UNDERFLOW = UNDERFLOW_P0_OUT ;
assign RD_EN_FIFO_IN = rd_en_fifo_in;
//***********************************************
// Create DATA_COUNT from First-Word Fall-Through
// data count
//***********************************************
assign DATA_COUNT = (C_USE_FWFT_DATA_COUNT == 0)? DATA_COUNT_FIFO_OUT:
(C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] :
DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1];
//***********************************************
// Create DATA_COUNT from First-Word Fall-Through
// data count
//***********************************************
always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin
if (RST_P0_IN) begin
EMPTY_P0_OUT_Q <= 1;
ALMOSTEMPTY_P0_OUT_Q <= 1;
end else begin
EMPTY_P0_OUT_Q <= #`TCQ empty_p0_out;
// EMPTY_P0_OUT_Q <= #`TCQ EMPTY_FIFO_OUT;
ALMOSTEMPTY_P0_OUT_Q <= #`TCQ ALMOSTEMPTY_P0_OUT;
end
end //always
//***********************************************
// logic for common-clock data count when FWFT is selected
//***********************************************
initial begin
SS_FWFT_RD = 1'b0;
DATA_COUNT_FWFT = 0 ;
SS_FWFT_WR = 1'b0 ;
end //initial
//***********************************************
// common-clock data count is implemented as an
// up-down counter. SS_FWFT_WR and SS_FWFT_RD
// are the up/down enables for the counter.
//***********************************************
always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT or empty_p0_out) begin
if (C_VALID_LOW == 1) begin
SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && ~VALID_P0_OUT) : (~empty_p0_out && RD_EN && ~VALID_P0_OUT) ;
end else begin
SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && VALID_P0_OUT) : (~empty_p0_out && RD_EN && VALID_P0_OUT) ;
end
SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT)) ;
end
//***********************************************
// common-clock data count is implemented as an
// up-down counter for FWFT. This always block
// calculates the counter.
//***********************************************
always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin
if (RST_P0_IN) begin
DATA_COUNT_FWFT <= 0;
end else begin
//if (srst_delayed && (C_HAS_SRST == 1) ) begin
if ((srst_delayed | wr_rst_busy | rd_rst_busy) && (C_HAS_SRST == 1) ) begin
DATA_COUNT_FWFT <= #`TCQ 0;
end else begin
case ( {SS_FWFT_WR, SS_FWFT_RD})
2'b00: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;
2'b01: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT - 1 ;
2'b10: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT + 1 ;
2'b11: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;
endcase
end //if SRST
end //IF RST
end //always
end endgenerate // : block2
// AXI Streaming Packet FIFO
reg [C_WR_PNTR_WIDTH-1:0] wr_pkt_count = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count_plus1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count_reg = 0;
reg partial_packet = 0;
reg stage1_eop_d1 = 0;
reg rd_en_fifo_in_d1 = 0;
reg eop_at_stage2 = 0;
reg ram_pkt_empty = 0;
reg ram_pkt_empty_d1 = 0;
wire [C_DOUT_WIDTH-1:0] dout_p0_out;
wire packet_empty_wr;
wire wr_rst_fwft_pkt_fifo;
wire dummy_wr_eop;
wire ram_wr_en_pkt_fifo;
wire wr_eop;
wire ram_rd_en_compare;
wire stage1_eop;
wire pkt_ready_to_read;
wire rd_en_2_stage2;
// Generate Dummy WR_EOP for partial packet (Only for AXI Streaming)
// When Packet EMPTY is high, and FIFO is full, then generate the dummy WR_EOP
// When dummy WR_EOP is high, mask the actual EOP to avoid double increment of
// write packet count
generate if (IS_FWFT == 1 && IS_AXIS_PKT_FIFO == 1) begin // gdummy_wr_eop
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
partial_packet <= 1'b0;
else begin
if (srst_delayed | wr_rst_busy | rd_rst_busy)
partial_packet <= #`TCQ 1'b0;
else if (ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]))
partial_packet <= #`TCQ 1'b1;
else if (partial_packet && din_delayed[0] && ram_wr_en_pkt_fifo)
partial_packet <= #`TCQ 1'b0;
end
end
end endgenerate // gdummy_wr_eop
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1) begin // gpkt_fifo_fwft
assign wr_rst_fwft_pkt_fifo = (C_COMMON_CLOCK == 0) ? wr_rst_i : (C_HAS_RST == 1) ? rst_i:1'b0;
assign dummy_wr_eop = ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]) && (~partial_packet);
assign packet_empty_wr = (C_COMMON_CLOCK == 1) ? empty_p0_out : pkt_empty_sync[C_SYNCHRONIZER_STAGE-1];
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
stage1_eop_d1 <= 1'b0;
rd_en_fifo_in_d1 <= 1'b0;
end else begin
if (srst_delayed | wr_rst_busy | rd_rst_busy) begin
stage1_eop_d1 <= #`TCQ 1'b0;
rd_en_fifo_in_d1 <= #`TCQ 1'b0;
end else begin
stage1_eop_d1 <= #`TCQ stage1_eop;
rd_en_fifo_in_d1 <= #`TCQ rd_en_fifo_in;
end
end
end
assign stage1_eop = (rd_en_fifo_in_d1) ? DOUT_FIFO_OUT[0] : stage1_eop_d1;
assign ram_wr_en_pkt_fifo = wr_en_delayed && (~FULL_FIFO_OUT);
assign wr_eop = ram_wr_en_pkt_fifo && ((din_delayed[0] && (~partial_packet)) || dummy_wr_eop);
assign ram_rd_en_compare = stage2_reg_en_i && stage1_eop;
fifo_generator_v13_1_3_bhv_ver_preload0
#(
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_ECC (C_USE_ECC),
.C_USERVALID_LOW (C_VALID_LOW),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_FIFO_TYPE (2) // Enable low latency fwft logic
)
pkt_fifo_fwft
(
.SAFETY_CKT_RD_RST(safety_ckt_rd_rst),
.RD_CLK (RD_CLK_P0_IN),
.RD_RST (rst_fwft),
.SRST (srst_delayed),
.WR_RST_BUSY (wr_rst_busy),
.RD_RST_BUSY (rd_rst_busy),
.RD_EN (rd_en_delayed),
.FIFOEMPTY (pkt_ready_to_read),
.FIFODATA (dout_fwft),
.FIFOSBITERR (sbiterr_fwft),
.FIFODBITERR (dbiterr_fwft),
// Output
.USERDATA (dout_p0_out),
.USERVALID (),
.USEREMPTY (empty_p0_out),
.USERALMOSTEMPTY (),
.USERUNDERFLOW (),
.RAMVALID (),
.FIFORDEN (rd_en_2_stage2),
.USERSBITERR (SBITERR),
.USERDBITERR (DBITERR),
.STAGE2_REG_EN (),
.VALID_STAGES ()
);
assign pkt_ready_to_read = ~(!(ram_pkt_empty || empty_fwft) && ((valid_stages_i[0] && valid_stages_i[1]) || eop_at_stage2));
assign rd_en_to_fwft_fifo = ~empty_fwft && rd_en_2_stage2;
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
eop_at_stage2 <= 1'b0;
else if (stage2_reg_en_i)
eop_at_stage2 <= #`TCQ stage1_eop;
end
//---------------------------------------------------------------------------
// Write and Read Packet Count
//---------------------------------------------------------------------------
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
wr_pkt_count <= 0;
else if (srst_delayed | wr_rst_busy | rd_rst_busy)
wr_pkt_count <= #`TCQ 0;
else if (wr_eop)
wr_pkt_count <= #`TCQ wr_pkt_count + 1;
end
end endgenerate // gpkt_fifo_fwft
assign DOUT = (C_FIFO_TYPE != 1) ? dout_fwft : dout_p0_out;
assign EMPTY = (C_FIFO_TYPE != 1) ? empty_fwft : empty_p0_out;
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 1) begin // grss_pkt_cnt
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
rd_pkt_count <= 0;
rd_pkt_count_plus1 <= 1;
end else if (srst_delayed | wr_rst_busy | rd_rst_busy) begin
rd_pkt_count <= #`TCQ 0;
rd_pkt_count_plus1 <= #`TCQ 1;
end else if (stage2_reg_en_i && stage1_eop) begin
rd_pkt_count <= #`TCQ rd_pkt_count + 1;
rd_pkt_count_plus1 <= #`TCQ rd_pkt_count_plus1 + 1;
end
end
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
ram_pkt_empty <= 1'b1;
ram_pkt_empty_d1 <= 1'b1;
end else if (SRST | wr_rst_busy | rd_rst_busy) begin
ram_pkt_empty <= #`TCQ 1'b1;
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end else if ((rd_pkt_count == wr_pkt_count) && wr_eop) begin
ram_pkt_empty <= #`TCQ 1'b0;
ram_pkt_empty_d1 <= #`TCQ 1'b0;
end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin
ram_pkt_empty <= #`TCQ 1'b1;
end else if ((rd_pkt_count_plus1 == wr_pkt_count) && ~wr_eop && ~ALMOST_FULL_FIFO_OUT && ram_rd_en_compare) begin
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end
end
end endgenerate //grss_pkt_cnt
localparam SYNC_STAGE_WIDTH = (C_SYNCHRONIZER_STAGE+1)*C_WR_PNTR_WIDTH;
reg [SYNC_STAGE_WIDTH-1:0] wr_pkt_count_q = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pkt_count_b2g = 0;
wire [C_WR_PNTR_WIDTH-1:0] wr_pkt_count_rd;
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 0) begin // gras_pkt_cnt
// Delay the write packet count in write clock domain to accomodate the binary to gray conversion delay
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
wr_pkt_count_b2g <= 0;
else
wr_pkt_count_b2g <= #`TCQ wr_pkt_count;
end
// Synchronize the delayed write packet count in read domain, and also compensate the gray to binay conversion delay
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
wr_pkt_count_q <= 0;
else
wr_pkt_count_q <= #`TCQ {wr_pkt_count_q[SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH-1:0],wr_pkt_count_b2g};
end
always @* begin
if (stage1_eop)
rd_pkt_count <= rd_pkt_count_reg + 1;
else
rd_pkt_count <= rd_pkt_count_reg;
end
assign wr_pkt_count_rd = wr_pkt_count_q[SYNC_STAGE_WIDTH-1:SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH];
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
rd_pkt_count_reg <= 0;
else if (rd_en_fifo_in)
rd_pkt_count_reg <= #`TCQ rd_pkt_count;
end
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
ram_pkt_empty <= 1'b1;
ram_pkt_empty_d1 <= 1'b1;
end else if (rd_pkt_count != wr_pkt_count_rd) begin
ram_pkt_empty <= #`TCQ 1'b0;
ram_pkt_empty_d1 <= #`TCQ 1'b0;
end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin
ram_pkt_empty <= #`TCQ 1'b1;
end else if ((rd_pkt_count == wr_pkt_count_rd) && stage2_reg_en_i) begin
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end
end
// Synchronize the empty in write domain
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
pkt_empty_sync <= 'b1;
else
pkt_empty_sync <= #`TCQ {pkt_empty_sync[C_SYNCHRONIZER_STAGE-2:0], empty_p0_out};
end
end endgenerate //gras_pkt_cnt
generate if (IS_FWFT == 0 || C_FIFO_TYPE == 3) begin : STD_FIFO
//***********************************************
// If NOT First-Word Fall-Through, wire the outputs
// of the internal _ss or _as FIFO directly to the
// output, and do not instantiate the preload0
// module.
//***********************************************
assign RD_CLK_P0_IN = 0;
assign RST_P0_IN = 0;
assign RD_EN_P0_IN = 0;
assign RD_EN_FIFO_IN = rd_en_delayed;
assign DOUT = DOUT_FIFO_OUT;
assign DATA_P0_IN = 0;
assign VALID = VALID_FIFO_OUT;
assign EMPTY = EMPTY_FIFO_OUT;
assign ALMOST_EMPTY = ALMOST_EMPTY_FIFO_OUT;
assign EMPTY_P0_IN = 0;
assign UNDERFLOW = UNDERFLOW_FIFO_OUT;
assign DATA_COUNT = DATA_COUNT_FIFO_OUT;
assign SBITERR = sbiterr_fifo_out;
assign DBITERR = dbiterr_fifo_out;
end endgenerate // STD_FIFO
generate if (IS_FWFT == 1 && C_FIFO_TYPE != 1) begin : NO_PKT_FIFO
assign empty_p0_out = empty_fwft;
assign SBITERR = sbiterr_fwft;
assign DBITERR = dbiterr_fwft;
assign DOUT = dout_fwft;
assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;
end endgenerate // NO_PKT_FIFO
//***********************************************
// Connect user flags to internal signals
//***********************************************
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block3
if (C_COMMON_CLOCK == 0) begin : block_ic
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT);
end //block_ic
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block3
endgenerate
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block30
if (C_COMMON_CLOCK == 0) begin : block_ic
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT);
end
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block30
endgenerate
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block30_both
if (C_COMMON_CLOCK == 0) begin : block_ic_both
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : (RD_DATA_COUNT_FIFO_OUT));
end
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block30_both
endgenerate
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block3_both
if (C_COMMON_CLOCK == 0) begin : block_ic_both
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : (RD_DATA_COUNT_FIFO_OUT));
end //block_ic_both
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block3_both
endgenerate
//If we are not using extra logic for the FWFT data count,
//then connect RD_DATA_COUNT to the RD_DATA_COUNT from the
//internal FIFO instance
generate
if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
endgenerate
//Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal
//FIFO instance
generate
if (C_USE_FWFT_DATA_COUNT==1) begin : block4
assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;
end
else begin : block4
assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;
end
endgenerate
//Connect other flags to the internal FIFO instance
assign FULL = FULL_FIFO_OUT;
assign ALMOST_FULL = ALMOST_FULL_FIFO_OUT;
assign WR_ACK = WR_ACK_FIFO_OUT;
assign OVERFLOW = OVERFLOW_FIFO_OUT;
assign PROG_FULL = PROG_FULL_FIFO_OUT;
assign PROG_EMPTY = PROG_EMPTY_FIFO_OUT;
/**************************************************************************
* find_log2
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function integer find_log2;
input integer int_val;
integer i,j;
begin
i = 1;
j = 0;
for (i = 1; i < int_val; i = i*2) begin
j = j + 1;
end
find_log2 = j;
end
endfunction
// if an asynchronous FIFO has been selected, display a message that the FIFO
// will not be cycle-accurate in simulation
initial begin
if (C_IMPLEMENTATION_TYPE == 2) begin
$display("WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.");
end else if (C_MEMORY_TYPE == 4) begin
$display("FAILURE : Behavioral models do not support built-in FIFO configurations. Please use post-synthesis or post-implement simulation in Vivado.");
$finish;
end
if (C_WR_PNTR_WIDTH != find_log2(C_WR_DEPTH)) begin
$display("FAILURE : C_WR_PNTR_WIDTH is not log2 of C_WR_DEPTH.");
$finish;
end
if (C_RD_PNTR_WIDTH != find_log2(C_RD_DEPTH)) begin
$display("FAILURE : C_RD_PNTR_WIDTH is not log2 of C_RD_DEPTH.");
$finish;
end
if (C_USE_ECC == 1) begin
if (C_DIN_WIDTH != C_DOUT_WIDTH) begin
$display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be equal for ECC configuration.");
$finish;
end
if (C_DIN_WIDTH == 1 && C_ERROR_INJECTION_TYPE > 1) begin
$display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be > 1 for double bit error injection.");
$finish;
end
end
end //initial
/**************************************************************************
* Internal reset logic
**************************************************************************/
assign wr_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? wr_rst_reg : 0;
assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? rd_rst_reg : 0;
assign rst_i = C_HAS_RST ? rst_reg : 0;
wire rst_2_sync;
wire rst_2_sync_safety = (C_ENABLE_RST_SYNC == 1) ? rst_delayed : RD_RST;
wire clk_2_sync = (C_COMMON_CLOCK == 1) ? CLK : WR_CLK;
wire clk_2_sync_safety = (C_COMMON_CLOCK == 1) ? CLK : RD_CLK;
localparam RST_SYNC_STAGES = (C_EN_SAFETY_CKT == 0) ? C_SYNCHRONIZER_STAGE :
(C_COMMON_CLOCK == 1) ? 3 : C_SYNCHRONIZER_STAGE+2;
reg [RST_SYNC_STAGES-1:0] wrst_reg = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] rrst_reg = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] arst_sync_q = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] wrst_q = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] rrst_q = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] rrst_wr = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] wrst_ext = {RST_SYNC_STAGES{1'b0}};
reg [1:0] wrst_cc = {2{1'b0}};
reg [1:0] rrst_cc = {2{1'b0}};
generate
if (C_EN_SAFETY_CKT == 1 && C_INTERFACE_TYPE == 0) begin : grst_safety_ckt
reg[1:0] rst_d1_safety =1;
reg[1:0] rst_d2_safety =1;
reg[1:0] rst_d3_safety =1;
reg[1:0] rst_d4_safety =1;
reg[1:0] rst_d5_safety =1;
reg[1:0] rst_d6_safety =1;
reg[1:0] rst_d7_safety =1;
always@(posedge rst_2_sync_safety or posedge clk_2_sync_safety) begin : prst
if (rst_2_sync_safety == 1'b1) begin
rst_d1_safety <= 1'b1;
rst_d2_safety <= 1'b1;
rst_d3_safety <= 1'b1;
rst_d4_safety <= 1'b1;
rst_d5_safety <= 1'b1;
rst_d6_safety <= 1'b1;
rst_d7_safety <= 1'b1;
end
else begin
rst_d1_safety <= #`TCQ 1'b0;
rst_d2_safety <= #`TCQ rst_d1_safety;
rst_d3_safety <= #`TCQ rst_d2_safety;
rst_d4_safety <= #`TCQ rst_d3_safety;
rst_d5_safety <= #`TCQ rst_d4_safety;
rst_d6_safety <= #`TCQ rst_d5_safety;
rst_d7_safety <= #`TCQ rst_d6_safety;
end //if
end //prst
always@(posedge rst_d7_safety or posedge WR_EN) begin : assert_safety
if(rst_d7_safety == 1 && WR_EN == 1) begin
$display("WARNING:A write attempt has been made within the 7 clock cycles of reset de-assertion. This can lead to data discrepancy when safety circuit is enabled.");
end //if
end //always
end // grst_safety_ckt
endgenerate
// if (C_EN_SAFET_CKT == 1)
// assertion:the reset shud be atleast 3 cycles wide.
generate
reg safety_ckt_wr_rst_i = 1'b0;
if (C_ENABLE_RST_SYNC == 0) begin : gnrst_sync
always @* begin
wr_rst_reg <= wr_rst_delayed;
rd_rst_reg <= rd_rst_delayed;
rst_reg <= 1'b0;
srst_reg <= 1'b0;
end
assign rst_2_sync = wr_rst_delayed;
assign wr_rst_busy = C_EN_SAFETY_CKT ? wr_rst_delayed : 1'b0;
assign rd_rst_busy = C_EN_SAFETY_CKT ? rd_rst_delayed : 1'b0;
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? wr_rst_delayed : 1'b0;
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rd_rst_delayed : 1'b0;
// end : gnrst_sync
end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 0) begin : g7s_ic_rst
reg fifo_wrst_done = 1'b0;
reg fifo_rrst_done = 1'b0;
reg sckt_wrst_i = 1'b0;
reg sckt_wrst_i_q = 1'b0;
reg rd_rst_active = 1'b0;
reg rd_rst_middle = 1'b0;
reg sckt_rd_rst_d1 = 1'b0;
reg [1:0] rst_delayed_ic_w = 2'h0;
wire rst_delayed_ic_w_i;
reg [1:0] rst_delayed_ic_r = 2'h0;
wire rst_delayed_ic_r_i;
wire arst_sync_rst;
wire fifo_rst_done;
wire fifo_rst_active;
assign wr_rst_comb = !wr_rst_asreg_d2 && wr_rst_asreg;
assign rd_rst_comb = C_EN_SAFETY_CKT ? (!rd_rst_asreg_d2 && rd_rst_asreg) || rd_rst_active : !rd_rst_asreg_d2 && rd_rst_asreg;
assign rst_2_sync = rst_delayed_ic_w_i;
assign arst_sync_rst = arst_sync_q[RST_SYNC_STAGES-1];
assign wr_rst_busy = C_EN_SAFETY_CKT ? |arst_sync_q[RST_SYNC_STAGES-1:1] | fifo_rst_active : 1'b0;
assign rd_rst_busy = C_EN_SAFETY_CKT ? safety_ckt_rd_rst : 1'b0;
assign fifo_rst_done = fifo_wrst_done & fifo_rrst_done;
assign fifo_rst_active = sckt_wrst_i | wrst_ext[RST_SYNC_STAGES-1] | rrst_wr[RST_SYNC_STAGES-1];
always @(posedge WR_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1 && C_HAS_RST)
rst_delayed_ic_w <= 2'b11;
else
rst_delayed_ic_w <= #`TCQ {rst_delayed_ic_w[0],1'b0};
end
assign rst_delayed_ic_w_i = rst_delayed_ic_w[1];
always @(posedge RD_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1 && C_HAS_RST)
rst_delayed_ic_r <= 2'b11;
else
rst_delayed_ic_r <= #`TCQ {rst_delayed_ic_r[0],1'b0};
end
assign rst_delayed_ic_r_i = rst_delayed_ic_r[1];
always @(posedge WR_CLK) begin
sckt_wrst_i_q <= #`TCQ sckt_wrst_i;
sckt_wr_rst_i_q <= #`TCQ wr_rst_busy;
safety_ckt_wr_rst_i <= #`TCQ sckt_wrst_i | wr_rst_busy | sckt_wr_rst_i_q;
if (arst_sync_rst && ~fifo_rst_active)
sckt_wrst_i <= #`TCQ 1'b1;
else if (sckt_wrst_i && fifo_rst_done)
sckt_wrst_i <= #`TCQ 1'b0;
else
sckt_wrst_i <= #`TCQ sckt_wrst_i;
if (rrst_wr[RST_SYNC_STAGES-2] & ~rrst_wr[RST_SYNC_STAGES-1])
fifo_rrst_done <= #`TCQ 1'b1;
else if (fifo_rst_done)
fifo_rrst_done <= #`TCQ 1'b0;
else
fifo_rrst_done <= #`TCQ fifo_rrst_done;
if (wrst_ext[RST_SYNC_STAGES-2] & ~wrst_ext[RST_SYNC_STAGES-1])
fifo_wrst_done <= #`TCQ 1'b1;
else if (fifo_rst_done)
fifo_wrst_done <= #`TCQ 1'b0;
else
fifo_wrst_done <= #`TCQ fifo_wrst_done;
end
always @(posedge WR_CLK or posedge rst_delayed_ic_w_i) begin
if (rst_delayed_ic_w_i == 1'b1) begin
wr_rst_asreg <= 1'b1;
end else begin
if (wr_rst_asreg_d1 == 1'b1) begin
wr_rst_asreg <= #`TCQ 1'b0;
end else begin
wr_rst_asreg <= #`TCQ wr_rst_asreg;
end
end
end
always @(posedge WR_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1) begin
wr_rst_asreg <= 1'b1;
end else begin
if (wr_rst_asreg_d1 == 1'b1) begin
wr_rst_asreg <= #`TCQ 1'b0;
end else begin
wr_rst_asreg <= #`TCQ wr_rst_asreg;
end
end
end
always @(posedge WR_CLK) begin
wrst_reg <= #`TCQ {wrst_reg[RST_SYNC_STAGES-2:0],wr_rst_asreg};
wrst_ext <= #`TCQ {wrst_ext[RST_SYNC_STAGES-2:0],sckt_wrst_i};
rrst_wr <= #`TCQ {rrst_wr[RST_SYNC_STAGES-2:0],safety_ckt_rd_rst};
arst_sync_q <= #`TCQ {arst_sync_q[RST_SYNC_STAGES-2:0],rst_delayed_ic_w_i};
end
assign wr_rst_asreg_d1 = wrst_reg[RST_SYNC_STAGES-2];
assign wr_rst_asreg_d2 = C_EN_SAFETY_CKT ? wrst_reg[RST_SYNC_STAGES-1] : wrst_reg[1];
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0;
always @(posedge WR_CLK or posedge wr_rst_comb) begin
if (wr_rst_comb == 1'b1) begin
wr_rst_reg <= 1'b1;
end else begin
wr_rst_reg <= #`TCQ 1'b0;
end
end
always @(posedge RD_CLK or posedge rst_delayed_ic_r_i) begin
if (rst_delayed_ic_r_i == 1'b1) begin
rd_rst_asreg <= 1'b1;
end else begin
if (rd_rst_asreg_d1 == 1'b1) begin
rd_rst_asreg <= #`TCQ 1'b0;
end else begin
rd_rst_asreg <= #`TCQ rd_rst_asreg;
end
end
end
always @(posedge RD_CLK) begin
rrst_reg <= #`TCQ {rrst_reg[RST_SYNC_STAGES-2:0],rd_rst_asreg};
rrst_q <= #`TCQ {rrst_q[RST_SYNC_STAGES-2:0],sckt_wrst_i};
rrst_cc <= #`TCQ {rrst_cc[0],rd_rst_asreg_d2};
sckt_rd_rst_d1 <= #`TCQ safety_ckt_rd_rst;
if (!rd_rst_middle && rrst_reg[1] && !rrst_reg[2]) begin
rd_rst_active <= #`TCQ 1'b1;
rd_rst_middle <= #`TCQ 1'b1;
end else if (safety_ckt_rd_rst)
rd_rst_active <= #`TCQ 1'b0;
else if (sckt_rd_rst_d1 && !safety_ckt_rd_rst)
rd_rst_middle <= #`TCQ 1'b0;
end
assign rd_rst_asreg_d1 = rrst_reg[RST_SYNC_STAGES-2];
assign rd_rst_asreg_d2 = C_EN_SAFETY_CKT ? rrst_reg[RST_SYNC_STAGES-1] : rrst_reg[1];
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rrst_q[2] : 1'b0;
always @(posedge RD_CLK or posedge rd_rst_comb) begin
if (rd_rst_comb == 1'b1) begin
rd_rst_reg <= 1'b1;
end else begin
rd_rst_reg <= #`TCQ 1'b0;
end
end
// end : g7s_ic_rst
end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 1) begin : g7s_cc_rst
reg [1:0] rst_delayed_cc = 2'h0;
wire rst_delayed_cc_i;
assign rst_comb = !rst_asreg_d2 && rst_asreg;
assign rst_2_sync = rst_delayed_cc_i;
assign wr_rst_busy = C_EN_SAFETY_CKT ? |arst_sync_q[RST_SYNC_STAGES-1:1] | wrst_cc[1] : 1'b0;
assign rd_rst_busy = C_EN_SAFETY_CKT ? arst_sync_q[1] | arst_sync_q[RST_SYNC_STAGES-1] | wrst_cc[1] : 1'b0;
always @(posedge CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1)
rst_delayed_cc <= 2'b11;
else
rst_delayed_cc <= #`TCQ {rst_delayed_cc,1'b0};
end
assign rst_delayed_cc_i = rst_delayed_cc[1];
always @(posedge CLK or posedge rst_delayed_cc_i) begin
if (rst_delayed_cc_i == 1'b1) begin
rst_asreg <= 1'b1;
end else begin
if (rst_asreg_d1 == 1'b1) begin
rst_asreg <= #`TCQ 1'b0;
end else begin
rst_asreg <= #`TCQ rst_asreg;
end
end
end
always @(posedge CLK) begin
wrst_reg <= #`TCQ {wrst_reg[RST_SYNC_STAGES-2:0],rst_asreg};
wrst_cc <= #`TCQ {wrst_cc[0],arst_sync_q[RST_SYNC_STAGES-1]};
sckt_wr_rst_i_q <= #`TCQ wr_rst_busy;
safety_ckt_wr_rst_i <= #`TCQ wrst_cc[1] | wr_rst_busy | sckt_wr_rst_i_q;
arst_sync_q <= #`TCQ {arst_sync_q[RST_SYNC_STAGES-2:0],rst_delayed_cc_i};
end
assign rst_asreg_d1 = wrst_reg[RST_SYNC_STAGES-2];
assign rst_asreg_d2 = C_EN_SAFETY_CKT ? wrst_reg[RST_SYNC_STAGES-1] : wrst_reg[1];
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0;
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0;
always @(posedge CLK or posedge rst_comb) begin
if (rst_comb == 1'b1) begin
rst_reg <= 1'b1;
end else begin
rst_reg <= #`TCQ 1'b0;
end
end
// end : g7s_cc_rst
end else if (IS_8SERIES == 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g8s_cc_rst
assign wr_rst_busy = (C_MEMORY_TYPE != 4) ? rst_reg : rst_active_i;
assign rd_rst_busy = rst_reg;
assign rst_2_sync = srst_delayed;
always @* rst_full_ff_i <= rst_reg;
always @* rst_full_gen_i <= C_FULL_FLAGS_RST_VAL == 1 ? rst_active_i : 0;
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? rst_reg | wr_rst_busy | sckt_wr_rst_i_q : 1'b0;
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rst_reg | wr_rst_busy | sckt_wr_rst_i_q : 1'b0;
always @(posedge CLK) begin
rst_delayed_d1 <= #`TCQ srst_delayed;
rst_delayed_d2 <= #`TCQ rst_delayed_d1;
sckt_wr_rst_i_q <= #`TCQ wr_rst_busy;
if (rst_reg || rst_delayed_d2) begin
rst_active_i <= #`TCQ 1'b1;
end else begin
rst_active_i <= #`TCQ rst_reg;
end
end
always @(posedge CLK) begin
if (~rst_reg && srst_delayed) begin
rst_reg <= #`TCQ 1'b1;
end else if (rst_reg) begin
rst_reg <= #`TCQ 1'b0;
end else begin
rst_reg <= #`TCQ rst_reg;
end
end
// end : g8s_cc_rst
end else begin
assign wr_rst_busy = 1'b0;
assign rd_rst_busy = 1'b0;
assign safety_ckt_wr_rst = 1'b0;
assign safety_ckt_rd_rst = 1'b0;
end
endgenerate
generate
if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 1) begin : grstd1
// RST_FULL_GEN replaces the reset falling edge detection used to de-assert
// FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1.
// RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL &
// PROG_FULL
reg rst_d1 = 1'b0;
reg rst_d2 = 1'b0;
reg rst_d3 = 1'b0;
reg rst_d4 = 1'b0;
reg rst_d5 = 1'b0;
always @ (posedge rst_2_sync or posedge clk_2_sync) begin
if (rst_2_sync) begin
rst_d1 <= 1'b1;
rst_d2 <= 1'b1;
rst_d3 <= 1'b1;
rst_d4 <= 1'b1;
end else begin
if (srst_delayed) begin
rst_d1 <= #`TCQ 1'b1;
rst_d2 <= #`TCQ 1'b1;
rst_d3 <= #`TCQ 1'b1;
rst_d4 <= #`TCQ 1'b1;
end else begin
rst_d1 <= #`TCQ wr_rst_busy;
rst_d2 <= #`TCQ rst_d1;
rst_d3 <= #`TCQ rst_d2 | safety_ckt_wr_rst;
rst_d4 <= #`TCQ rst_d3;
end
end
end
always @* rst_full_ff_i <= (C_HAS_SRST == 0) ? rst_d2 : 1'b0 ;
always @* rst_full_gen_i <= rst_d3;
end else if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full
always @* rst_full_ff_i <= (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i;
end
endgenerate // grstd1
endmodule //fifo_generator_v13_1_3_conv_ver
module fifo_generator_v13_1_3_sync_stage
#(
parameter C_WIDTH = 10
)
(
input RST,
input CLK,
input [C_WIDTH-1:0] DIN,
output reg [C_WIDTH-1:0] DOUT = 0
);
always @ (posedge RST or posedge CLK) begin
if (RST)
DOUT <= 0;
else
DOUT <= #`TCQ DIN;
end
endmodule // fifo_generator_v13_1_3_sync_stage
/*******************************************************************************
* Declaration of Independent-Clocks FIFO Module
******************************************************************************/
module fifo_generator_v13_1_3_bhv_ver_as
/***************************************************************************
* Declare user parameters and their defaults
***************************************************************************/
#(
parameter C_FAMILY = "virtex7",
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_USE_ECC = 0,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2
)
/***************************************************************************
* Declare Input and Output Ports
***************************************************************************/
(
input SAFETY_CKT_WR_RST,
input SAFETY_CKT_RD_RST,
input [C_DIN_WIDTH-1:0] DIN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input RD_CLK,
input RD_EN,
input RD_EN_USER,
input RST,
input RST_FULL_GEN,
input RST_FULL_FF,
input WR_RST,
input RD_RST,
input WR_CLK,
input WR_EN,
input INJECTDBITERR,
input INJECTSBITERR,
input USER_EMPTY_FB,
input fab_read_data_valid_i,
input read_data_valid_i,
input ram_valid_i,
output reg ALMOST_EMPTY = 1'b1,
output reg ALMOST_FULL = C_FULL_FLAGS_RST_VAL,
output [C_DOUT_WIDTH-1:0] DOUT,
output reg EMPTY = 1'b1,
output reg EMPTY_FB = 1'b1,
output reg FULL = C_FULL_FLAGS_RST_VAL,
output OVERFLOW,
output PROG_EMPTY,
output PROG_FULL,
output VALID,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output UNDERFLOW,
output WR_ACK,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output SBITERR,
output DBITERR
);
reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;
/***************************************************************************
* Parameters used as constants
**************************************************************************/
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
//When RST is present, set FULL reset value to '1'.
//If core has no RST, make sure FULL powers-on as '0'.
localparam C_DEPTH_RATIO_WR =
(C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;
localparam C_DEPTH_RATIO_RD =
(C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;
localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;
localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;
// C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC
// -----------------|------------------|-----------------|---------------
// 1 | 8 | C_RD_PNTR_WIDTH | 2
// 1 | 4 | C_RD_PNTR_WIDTH | 2
// 1 | 2 | C_RD_PNTR_WIDTH | 2
// 1 | 1 | C_WR_PNTR_WIDTH | 2
// 2 | 1 | C_WR_PNTR_WIDTH | 4
// 4 | 1 | C_WR_PNTR_WIDTH | 8
// 8 | 1 | C_WR_PNTR_WIDTH | 16
localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;
localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);
localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;
localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);
/**************************************************************************
* FIFO Contents Tracking and Data Count Calculations
*************************************************************************/
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
// Local parameters used to determine whether to inject ECC error or not
localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;
localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;
localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;
localparam ENABLE_ERR_INJECTION = C_USE_ECC_1 && SYMMETRIC_PORT && ERR_INJECTION;
// Array that holds the error injection type (single/double bit error) on
// a specific write operation, which is returned on read to corrupt the
// output data.
reg [1:0] ecc_err[C_WR_DEPTH-1:0];
//The amount of data stored in the FIFO at any time is given
// by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK
// domain.
//num_wr_bits is calculated by considering the total words in the FIFO,
// and the state of the read pointer (which may not have yet crossed clock
// domains.)
//num_rd_bits is calculated by considering the total words in the FIFO,
// and the state of the write pointer (which may not have yet crossed clock
// domains.)
reg [31:0] num_wr_bits;
reg [31:0] num_rd_bits;
reg [31:0] next_num_wr_bits;
reg [31:0] next_num_rd_bits;
//The write pointer - tracks write operations
// (Works opposite to core: wr_ptr is a DOWN counter)
reg [31:0] wr_ptr;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0;
wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0;
wire wr_rst_i = WR_RST;
reg wr_rst_d1 =0;
//The read pointer - tracks read operations
// (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)
reg [31:0] rd_ptr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0;
wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0;
wire rd_rst_i = RD_RST;
wire ram_rd_en;
wire empty_int;
wire almost_empty_int;
wire ram_wr_en;
wire full_int;
wire almost_full_int;
reg ram_rd_en_d1 = 1'b0;
reg fab_rd_en_d1 = 1'b0;
// Delayed ram_rd_en is needed only for STD Embedded register option
generate
if (C_PRELOAD_LATENCY == 2) begin : grd_d
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
ram_rd_en_d1 <= 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
end
end
endgenerate
generate
if (C_PRELOAD_LATENCY == 2 && C_USE_EMBEDDED_REG == 3) begin : grd_d1
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
ram_rd_en_d1 <= 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
end
end
endgenerate
// Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation
generate
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : rdg // Read depth greater than write depth
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1:0] = 0;
end else begin : rdl // Read depth lesser than or equal to write depth
assign adj_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
endgenerate
// Generate Empty and Almost Empty
// ram_rd_en used to determine EMPTY should depend on the EMPTY.
assign ram_rd_en = RD_EN & !EMPTY;
assign empty_int = ((adj_wr_pntr_rd == rd_pntr) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+1'h1))));
assign almost_empty_int = ((adj_wr_pntr_rd == (rd_pntr+1'h1)) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+2'h2))));
// Register Empty and Almost Empty
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin
EMPTY <= 1'b1;
ALMOST_EMPTY <= 1'b1;
rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}};
end else begin
rd_data_count_int <= #`TCQ {(adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:0] - rd_pntr[C_RD_PNTR_WIDTH-1:0]), 1'b0};
if (empty_int)
EMPTY <= #`TCQ 1'b1;
else
EMPTY <= #`TCQ 1'b0;
if (!EMPTY) begin
if (almost_empty_int)
ALMOST_EMPTY <= #`TCQ 1'b1;
else
ALMOST_EMPTY <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin
EMPTY_FB <= 1'b1;
end else begin
if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT)
EMPTY_FB <= #`TCQ 1'b1;
else if (empty_int)
EMPTY_FB <= #`TCQ 1'b1;
else
EMPTY_FB <= #`TCQ 1'b0;
end // rd_rst_i
end // always
// Read pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation
generate
if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wdg // Write depth greater than read depth
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1:0] = 0;
end else begin : wdl // Write depth lesser than or equal to read depth
assign adj_rd_pntr_wr = rd_pntr_wr[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end
endgenerate
// Generate FULL and ALMOST_FULL
// ram_wr_en used to determine FULL should depend on the FULL.
assign ram_wr_en = WR_EN & !FULL;
assign full_int = ((adj_rd_pntr_wr == (wr_pntr+1'h1)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+2'h2))));
assign almost_full_int = ((adj_rd_pntr_wr == (wr_pntr+2'h2)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+3'h3))));
// Register FULL and ALMOST_FULL Empty
always @ (posedge WR_CLK or posedge RST_FULL_FF)
begin
if (RST_FULL_FF) begin
FULL <= C_FULL_FLAGS_RST_VAL;
ALMOST_FULL <= C_FULL_FLAGS_RST_VAL;
end else begin
if (full_int) begin
FULL <= #`TCQ 1'b1;
end else begin
FULL <= #`TCQ 1'b0;
end
if (RST_FULL_GEN) begin
ALMOST_FULL <= #`TCQ 1'b0;
end else if (!FULL) begin
if (almost_full_int)
ALMOST_FULL <= #`TCQ 1'b1;
else
ALMOST_FULL <= #`TCQ 1'b0;
end
end // wr_rst_i
end // always
always @ (posedge WR_CLK or posedge wr_rst_i)
begin
if (wr_rst_i) begin
wr_data_count_int <= {C_WR_DATA_COUNT_WIDTH{1'b0}};
end else begin
wr_data_count_int <= #`TCQ {(wr_pntr[C_WR_PNTR_WIDTH-1:0] - adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:0]), 1'b0};
end // wr_rst_i
end // always
// Determine which stage in FWFT registers are valid
reg stage1_valid = 0;
reg stage2_valid = 0;
generate
if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
stage1_valid <= 0;
stage2_valid <= 0;
end else begin
if (!stage1_valid && !stage2_valid) begin
if (!EMPTY)
stage1_valid <= #`TCQ 1'b1;
else
stage1_valid <= #`TCQ 1'b0;
end else if (stage1_valid && !stage2_valid) begin
if (EMPTY) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else if (!stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && !RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end
end else if (stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
end
endgenerate
//Pointers passed into opposite clock domain
reg [31:0] wr_ptr_rdclk;
reg [31:0] wr_ptr_rdclk_next;
reg [31:0] rd_ptr_wrclk;
reg [31:0] rd_ptr_wrclk_next;
//Amount of data stored in the FIFO scaled to the narrowest (deepest) port
// (Do not include data in FWFT stages)
//Used to calculate PROG_EMPTY.
wire [31:0] num_read_words_pe =
num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR);
//Amount of data stored in the FIFO scaled to the narrowest (deepest) port
// (Do not include data in FWFT stages)
//Used to calculate PROG_FULL.
wire [31:0] num_write_words_pf =
num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD);
/**************************
* Read Data Count
*************************/
reg [31:0] num_read_words_dc;
reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;
always @(num_rd_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//If using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain,
// and add two read words for FWFT stages
//This value is only a temporary value and not used in the code.
num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];
end else begin
//If not using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain.
//This value is only a temporary value and not used in the code.
num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/**************************
* Write Data Count
*************************/
reg [31:0] num_write_words_dc;
reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;
always @(num_wr_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//Calculate the Data Count value for the number of write words,
// when using First-Word Fall-Through with extra logic for Data
// Counts. This takes into consideration the number of words that
// are expected to be stored in the FWFT register stages (it always
// assumes they are filled).
//This value is scaled to the Write Domain.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//EXTRA_WORDS_DC is the number of words added to write_words
// due to FWFT.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;
//Trim the write words for use with WR_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];
end else begin
//Calculate the Data Count value for the number of write words, when NOT
// using First-Word Fall-Through with extra logic for Data Counts. This
// calculates only the number of words in the internal FIFO.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//This value is scaled to the Write Domain.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;
//Trim the read words for use with RD_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/***************************************************************************
* Internal registers and wires
**************************************************************************/
//Temporary signals used for calculating the model's outputs. These
//are only used in the assign statements immediately following wire,
//parameter, and function declarations.
wire [C_DOUT_WIDTH-1:0] ideal_dout_out;
wire valid_i;
wire valid_out1;
wire valid_out2;
wire valid_out;
wire underflow_i;
//Ideal FIFO signals. These are the raw output of the behavioral model,
//which behaves like an ideal FIFO.
reg [1:0] err_type = 0;
reg [1:0] err_type_d1 = 0;
reg [1:0] err_type_both = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_both = 0;
reg ideal_wr_ack = 0;
reg ideal_valid = 0;
reg ideal_overflow = C_OVERFLOW_LOW;
reg ideal_underflow = C_UNDERFLOW_LOW;
reg ideal_prog_full = 0;
reg ideal_prog_empty = 1;
reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;
reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;
//Assorted reg values for delayed versions of signals
reg valid_d1 = 0;
reg valid_d2 = 0;
//user specified value for reseting the size of the fifo
reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
//temporary registers for WR_RESPONSE_LATENCY feature
integer tmp_wr_listsize;
integer tmp_rd_listsize;
//Signal for registered version of prog full and empty
//Threshold values for Programmable Flags
integer prog_empty_actual_thresh_assert;
integer prog_empty_actual_thresh_negate;
integer prog_full_actual_thresh_assert;
integer prog_full_actual_thresh_negate;
/****************************************************************************
* Function Declarations
***************************************************************************/
/**************************************************************************
* write_fifo
* This task writes a word to the FIFO memory and updates the
* write pointer.
* FIFO size is relative to write domain.
***************************************************************************/
task write_fifo;
begin
memory[wr_ptr] <= DIN;
wr_pntr <= #`TCQ wr_pntr + 1;
// Store the type of error injection (double/single) on write
case (C_ERROR_INJECTION_TYPE)
3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR};
2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0};
1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR};
default: ecc_err[wr_ptr] <= 0;
endcase
// (Works opposite to core: wr_ptr is a DOWN counter)
if (wr_ptr == 0) begin
wr_ptr <= C_WR_DEPTH - 1;
end else begin
wr_ptr <= wr_ptr - 1;
end
end
endtask // write_fifo
/**************************************************************************
* read_fifo
* This task reads a word from the FIFO memory and updates the read
* pointer. It's output is the ideal_dout bus.
* FIFO size is relative to write domain.
***************************************************************************/
task read_fifo;
integer i;
reg [C_DOUT_WIDTH-1:0] tmp_dout;
reg [C_DIN_WIDTH-1:0] memory_read;
reg [31:0] tmp_rd_ptr;
reg [31:0] rd_ptr_high;
reg [31:0] rd_ptr_low;
reg [1:0] tmp_ecc_err;
begin
rd_pntr <= #`TCQ rd_pntr + 1;
// output is wider than input
if (reads_per_write == 0) begin
tmp_dout = 0;
tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);
for (i = writes_per_read - 1; i >= 0; i = i - 1) begin
tmp_dout = tmp_dout << C_DIN_WIDTH;
tmp_dout = tmp_dout | memory[tmp_rd_ptr];
// (Works opposite to core: rd_ptr is a DOWN counter)
if (tmp_rd_ptr == 0) begin
tmp_rd_ptr = C_WR_DEPTH - 1;
end else begin
tmp_rd_ptr = tmp_rd_ptr - 1;
end
end
// output is symmetric
end else if (reads_per_write == 1) begin
tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];
// Retreive the error injection type. Based on the error injection type
// corrupt the output data.
tmp_ecc_err = ecc_err[rd_ptr];
if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin
if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error
if (C_DOUT_WIDTH == 1) begin
$display("FAILURE : Data width must be >= 2 for double bit error injection.");
$finish;
end else if (C_DOUT_WIDTH == 2)
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};
else
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};
end else begin
tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];
end
err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};
end else begin
err_type <= 0;
end
// input is wider than output
end else begin
rd_ptr_high = rd_ptr >> log2_reads_per_write;
rd_ptr_low = rd_ptr & (reads_per_write - 1);
memory_read = memory[rd_ptr_high];
tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);
end
ideal_dout <= tmp_dout;
// (Works opposite to core: rd_ptr is a DOWN counter)
if (rd_ptr == 0) begin
rd_ptr <= C_RD_DEPTH - 1;
end else begin
rd_ptr <= rd_ptr - 1;
end
end
endtask
/**************************************************************************
* log2_val
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function [31:0] log2_val;
input [31:0] binary_val;
begin
if (binary_val == 8) begin
log2_val = 3;
end else if (binary_val == 4) begin
log2_val = 2;
end else begin
log2_val = 1;
end
end
endfunction
/***********************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***********************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )
begin
case (def_data[7:0])
8'b00000000 :
begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default :
begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1)
begin
if ((index*4)+j < C_DOUT_WIDTH)
begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
/*************************************************************************
* Initialize Signals for clean power-on simulation
*************************************************************************/
initial begin
num_wr_bits = 0;
num_rd_bits = 0;
next_num_wr_bits = 0;
next_num_rd_bits = 0;
rd_ptr = C_RD_DEPTH - 1;
wr_ptr = C_WR_DEPTH - 1;
wr_pntr = 0;
rd_pntr = 0;
rd_ptr_wrclk = rd_ptr;
wr_ptr_rdclk = wr_ptr;
dout_reset_val = hexstr_conv(C_DOUT_RST_VAL);
ideal_dout = dout_reset_val;
err_type = 0;
err_type_d1 = 0;
err_type_both = 0;
ideal_dout_d1 = dout_reset_val;
ideal_wr_ack = 1'b0;
ideal_valid = 1'b0;
valid_d1 = 1'b0;
valid_d2 = 1'b0;
ideal_overflow = C_OVERFLOW_LOW;
ideal_underflow = C_UNDERFLOW_LOW;
ideal_wr_count = 0;
ideal_rd_count = 0;
ideal_prog_full = 1'b0;
ideal_prog_empty = 1'b1;
end
/*************************************************************************
* Connect the module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire RD_CLK;
wire RD_EN;
wire RST;
wire WR_CLK;
wire WR_EN;
*/
//***************************************************************************
// Dout may change behavior based on latency
//***************************************************************************
assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) )?
ideal_dout_d1: ideal_dout;
assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out;
//***************************************************************************
// Assign SBITERR and DBITERR based on latency
//***************************************************************************
assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) &&
(C_PRELOAD_LATENCY == 2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) ) ?
err_type_d1[0]: err_type[0];
assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&
(C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[1]: err_type[1];
//***************************************************************************
// Safety-ckt logic with embedded reg/fabric reg
//***************************************************************************
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
// if (C_HAS_VALID == 1) begin
// assign valid_out = valid_d1;
// end
always@(posedge RD_CLK)
begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK)
begin
if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1)
ram_rd_en_d1 <= #`TCQ 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
end
always@(posedge rst_delayed_sft2 or posedge RD_CLK)
begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end
else begin
if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1[0] <= #`TCQ err_type[0];
err_type_d1[1] <= #`TCQ err_type[1];
end
end
end
end
endgenerate
//***************************************************************************
// Safety-ckt logic with embedded reg + fabric reg
//***************************************************************************
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK) begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK) begin
if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1)
ram_rd_en_d1 <= #`TCQ 1'b0;
else begin
ram_rd_en_d1 <= #`TCQ ram_rd_en;
fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
end
end
always@(posedge rst_delayed_sft2 or posedge RD_CLK) begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both[0] <= #`TCQ err_type[0];
err_type_both[1] <= #`TCQ err_type[1];
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1[0] <= #`TCQ err_type_both[0];
err_type_d1[1] <= #`TCQ err_type_both[1];
end
end
end
end
endgenerate
//***************************************************************************
// Overflow may be active-low
//***************************************************************************
generate
if (C_HAS_OVERFLOW==1) begin : blockOF1
assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;
end
endgenerate
assign PROG_EMPTY = ideal_prog_empty;
assign PROG_FULL = ideal_prog_full;
//***************************************************************************
// Valid may change behavior based on latency or active-low
//***************************************************************************
generate
if (C_HAS_VALID==1) begin : blockVL1
assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid;
assign valid_out1 = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG < 3)?
valid_d1: valid_i;
assign valid_out2 = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG == 3)?
valid_d2: valid_i;
assign valid_out = (C_USE_EMBEDDED_REG == 3) ? valid_out2 : valid_out1;
assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW;
end
endgenerate
//***************************************************************************
// Underflow may change behavior based on latency or active-low
//***************************************************************************
generate
if (C_HAS_UNDERFLOW==1) begin : blockUF1
assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow;
assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;
end
endgenerate
//***************************************************************************
// Write acknowledge may be active low
//***************************************************************************
generate
if (C_HAS_WR_ACK==1) begin : blockWK1
assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;
end
endgenerate
//***************************************************************************
// Generate RD_DATA_COUNT if Use Extra Logic option is selected
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : wdc_fwft_ext
reg [C_PNTR_WIDTH-1:0] adjusted_wr_pntr = 0;
reg [C_PNTR_WIDTH-1:0] adjusted_rd_pntr = 0;
wire [C_PNTR_WIDTH-1:0] diff_wr_rd_tmp;
wire [C_PNTR_WIDTH:0] diff_wr_rd;
reg [C_PNTR_WIDTH:0] wr_data_count_i = 0;
always @* begin
if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin
adjusted_wr_pntr = wr_pntr;
adjusted_rd_pntr = 0;
adjusted_rd_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;
end else if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin
adjusted_rd_pntr = rd_pntr_wr;
adjusted_wr_pntr = 0;
adjusted_wr_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;
end else begin
adjusted_wr_pntr = wr_pntr;
adjusted_rd_pntr = rd_pntr_wr;
end
end // always @*
assign diff_wr_rd_tmp = adjusted_wr_pntr - adjusted_rd_pntr;
assign diff_wr_rd = {1'b0,diff_wr_rd_tmp};
always @ (posedge wr_rst_i or posedge WR_CLK)
begin
if (wr_rst_i)
wr_data_count_i <= 0;
else
wr_data_count_i <= #`TCQ diff_wr_rd + EXTRA_WORDS_DC;
end // always @ (posedge WR_CLK or posedge WR_CLK)
always @* begin
if (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH)
wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:0];
else
wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end // always @*
end // wdc_fwft_ext
endgenerate
//***************************************************************************
// Generate RD_DATA_COUNT if Use Extra Logic option is selected
//***************************************************************************
reg [C_RD_PNTR_WIDTH:0] rdc_fwft_ext_as = 0;
generate if (C_USE_EMBEDDED_REG < 3) begin: rdc_fwft_ext_both
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext
reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp;
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr;
always @* begin
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin
adjusted_wr_pntr_rd = 0;
adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
end else begin
adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
end // always @*
assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;
assign diff_rd_wr = {1'b0,diff_rd_wr_tmp};
always @ (posedge rd_rst_i or posedge RD_CLK)
begin
if (rd_rst_i) begin
rdc_fwft_ext_as <= 0;
end else begin
if (!stage2_valid)
rdc_fwft_ext_as <= #`TCQ 0;
else if (!stage1_valid && stage2_valid)
rdc_fwft_ext_as <= #`TCQ 1;
else
rdc_fwft_ext_as <= #`TCQ diff_rd_wr + 2'h2;
end
end // always @ (posedge WR_CLK or posedge WR_CLK)
end // rdc_fwft_ext
end
endgenerate
generate if (C_USE_EMBEDDED_REG == 3) begin
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext
reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp;
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr;
always @* begin
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin
adjusted_wr_pntr_rd = 0;
adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
end else begin
adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
end // always @*
assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;
assign diff_rd_wr = {1'b0,diff_rd_wr_tmp};
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr_1;
// assign diff_rd_wr_1 = diff_rd_wr +2'h2;
always @ (posedge rd_rst_i or posedge RD_CLK)
begin
if (rd_rst_i) begin
rdc_fwft_ext_as <= #`TCQ 0;
end else begin
//if (fab_read_data_valid_i == 1'b0 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b1)))
// rdc_fwft_ext_as <= 1'b0;
//else if (fab_read_data_valid_i == 1'b1 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1)))
// rdc_fwft_ext_as <= 1'b1;
//else
rdc_fwft_ext_as <= diff_rd_wr + 2'h2 ;
end
end
end
end
endgenerate
//***************************************************************************
// Assign the read data count value only if it is selected,
// otherwise output zeros.
//***************************************************************************
generate
if (C_HAS_RD_DATA_COUNT == 1) begin : grdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = C_USE_FWFT_DATA_COUNT ?
rdc_fwft_ext_as[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH] :
rd_data_count_int[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//***************************************************************************
// Assign the write data count value only if it is selected,
// otherwise output zeros
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1) begin : gwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = (C_USE_FWFT_DATA_COUNT == 1) ?
wdc_fwft_ext_as[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] :
wr_data_count_int[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
/**************************************************************************
* Assorted registers for delayed versions of signals
**************************************************************************/
//Capture delayed version of valid
generate
if (C_HAS_VALID==1) begin : blockVL2
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
valid_d1 <= 1'b0;
valid_d2 <= 1'b0;
end else begin
valid_d1 <= #`TCQ valid_i;
valid_d2 <= #`TCQ valid_d1;
end
// if (C_USE_EMBEDDED_REG == 3 && (C_EN_SAFETY_CKT == 0 || C_EN_SAFETY_CKT == 1 ) begin
// valid_d2 <= #`TCQ valid_d1;
// end
end
end
endgenerate
//Capture delayed version of dout
/**************************************************************************
*embedded/fabric reg with no safety ckt
**************************************************************************/
generate
if (C_USE_EMBEDDED_REG < 3) begin
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout <= #`TCQ dout_reset_val;
end
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0)
err_type_d1 <= #`TCQ 0;
end else if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1 <= #`TCQ err_type;
end
end
end
endgenerate
/**************************************************************************
*embedded + fabric reg with no safety ckt
**************************************************************************/
generate
if (C_USE_EMBEDDED_REG == 3) begin
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout <= #`TCQ dout_reset_val;
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
end else begin
if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both <= #`TCQ err_type;
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1 <= #`TCQ err_type_both;
end
end
end
end
endgenerate
/**************************************************************************
* Overflow and Underflow Flag calculation
* (handled separately because they don't support rst)
**************************************************************************/
generate
if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw
always @(posedge WR_CLK) begin
ideal_overflow <= #`TCQ WR_EN & FULL;
end
end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw
always @(posedge WR_CLK) begin
//ideal_overflow <= #`TCQ WR_EN & (FULL | wr_rst_i);
ideal_overflow <= #`TCQ WR_EN & (FULL );
end
end
endgenerate
generate
if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw
always @(posedge RD_CLK) begin
ideal_underflow <= #`TCQ EMPTY & RD_EN;
end
end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw
always @(posedge RD_CLK) begin
ideal_underflow <= #`TCQ (EMPTY) & RD_EN;
//ideal_underflow <= #`TCQ (rd_rst_i | EMPTY) & RD_EN;
end
end
endgenerate
/**************************************************************************
* Write/Read Pointer Synchronization
**************************************************************************/
localparam NO_OF_SYNC_STAGE_INC_G2B = C_SYNCHRONIZER_STAGE + 1;
wire [C_WR_PNTR_WIDTH-1:0] wr_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];
wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];
genvar gss;
generate for (gss = 1; gss <= NO_OF_SYNC_STAGE_INC_G2B; gss = gss + 1) begin : Sync_stage_inst
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (C_WR_PNTR_WIDTH)
)
rd_stg_inst
(
.RST (rd_rst_i),
.CLK (RD_CLK),
.DIN (wr_pntr_sync_stgs[gss-1]),
.DOUT (wr_pntr_sync_stgs[gss])
);
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (C_RD_PNTR_WIDTH)
)
wr_stg_inst
(
.RST (wr_rst_i),
.CLK (WR_CLK),
.DIN (rd_pntr_sync_stgs[gss-1]),
.DOUT (rd_pntr_sync_stgs[gss])
);
end endgenerate // Sync_stage_inst
assign wr_pntr_sync_stgs[0] = wr_pntr_rd1;
assign rd_pntr_sync_stgs[0] = rd_pntr_wr1;
always@* begin
wr_pntr_rd <= wr_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];
rd_pntr_wr <= rd_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];
end
/**************************************************************************
* Write Domain Logic
**************************************************************************/
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;
always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_wp
if (wr_rst_i == 1'b1 && C_EN_SAFETY_CKT == 0)
wr_pntr <= 0;
else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_WR_RST == 1'b1)
wr_pntr <= #`TCQ 0;
end
always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w
/****** Reset fifo (case 1)***************************************/
if (wr_rst_i == 1'b1) begin
num_wr_bits <= 0;
next_num_wr_bits = 0;
wr_ptr <= C_WR_DEPTH - 1;
rd_ptr_wrclk <= C_RD_DEPTH - 1;
ideal_wr_ack <= 0;
ideal_wr_count <= 0;
tmp_wr_listsize = 0;
rd_ptr_wrclk_next <= 0;
wr_pntr_rd1 <= 0;
end else begin //wr_rst_i==0
wr_pntr_rd1 <= #`TCQ wr_pntr;
//Determine the current number of words in the FIFO
tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :
num_wr_bits/C_DIN_WIDTH;
rd_ptr_wrclk_next = rd_ptr;
if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH
- rd_ptr_wrclk_next);
end else begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);
end
//If this is a write, handle the write by adding the value
// to the linked list, and updating all outputs appropriately
if (WR_EN == 1'b1) begin
if (FULL == 1'b1) begin
//If the FIFO is full, do NOT perform the write,
// update flags accordingly
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD
>= C_FIFO_WR_DEPTH) begin
//write unsuccessful - do not change contents
//Do not acknowledge the write
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is one from full, but reporting full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-1) begin
//No change to FIFO
//Write not successful
ideal_wr_ack <= #`TCQ 0;
//With DEPTH-1 words in the FIFO, it is almost_full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is completely empty, but it is
// reporting FULL for some reason (like reset)
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <=
C_FIFO_WR_DEPTH-2) begin
//No change to FIFO
//Write not successful
ideal_wr_ack <= #`TCQ 0;
//FIFO is really not close to full, so change flag status.
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end //(tmp_wr_listsize == 0)
end else begin
//If the FIFO is full, do NOT perform the write,
// update flags accordingly
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >=
C_FIFO_WR_DEPTH) begin
//write unsuccessful - do not change contents
//Do not acknowledge the write
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is one from full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-1) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//This write is CAUSING the FIFO to go full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is 2 from full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-2) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Still 2 from full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is not close to being full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <
C_FIFO_WR_DEPTH-2) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Not even close to full.
ideal_wr_count <= num_write_words_sized_i;
end
end
end else begin //(WR_EN == 1'b1)
//If user did not attempt a write, then do not
// give ack or err
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end
num_wr_bits <= #`TCQ next_num_wr_bits;
rd_ptr_wrclk <= #`TCQ rd_ptr;
end //wr_rst_i==0
end // gen_fifo_w
/***************************************************************************
* Programmable FULL flags
***************************************************************************/
wire [C_WR_PNTR_WIDTH-1:0] pf_thr_assert_val;
wire [C_WR_PNTR_WIDTH-1:0] pf_thr_negate_val;
generate if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin : FWFT
assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_DC;
assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_DC;
end else begin // STD
assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL;
assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL;
end endgenerate
always @(posedge WR_CLK or posedge wr_rst_i) begin
if (wr_rst_i == 1'b1) begin
diff_pntr <= 0;
end else begin
if (ram_wr_en)
diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr + 2'h1);
else if (!ram_wr_en)
diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr);
end
end
always @(posedge WR_CLK or posedge RST_FULL_FF) begin : gen_pf
if (RST_FULL_FF == 1'b1) begin
ideal_prog_full <= C_FULL_FLAGS_RST_VAL;
end else begin
if (RST_FULL_GEN)
ideal_prog_full <= #`TCQ 0;
//Single Programmable Full Constant Threshold
else if (C_PROG_FULL_TYPE == 1) begin
if (FULL == 0) begin
if (diff_pntr >= pf_thr_assert_val)
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Two Programmable Full Constant Thresholds
end else if (C_PROG_FULL_TYPE == 2) begin
if (FULL == 0) begin
if (diff_pntr >= pf_thr_assert_val)
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < pf_thr_negate_val)
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Single Programmable Full Threshold Input
end else if (C_PROG_FULL_TYPE == 3) begin
if (FULL == 0) begin
if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT
if (diff_pntr >= (PROG_FULL_THRESH - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end else begin // STD
if (diff_pntr >= PROG_FULL_THRESH)
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Two Programmable Full Threshold Inputs
end else if (C_PROG_FULL_TYPE == 4) begin
if (FULL == 0) begin
if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT
if (diff_pntr >= (PROG_FULL_THRESH_ASSERT - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < (PROG_FULL_THRESH_NEGATE - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end else begin // STD
if (diff_pntr >= PROG_FULL_THRESH_ASSERT)
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < PROG_FULL_THRESH_NEGATE)
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
end // C_PROG_FULL_TYPE
end //wr_rst_i==0
end //
/**************************************************************************
* Read Domain Logic
**************************************************************************/
/*********************************************************
* Programmable EMPTY flags
*********************************************************/
//Determine the Assert and Negate thresholds for Programmable Empty
wire [C_RD_PNTR_WIDTH-1:0] pe_thr_assert_val;
wire [C_RD_PNTR_WIDTH-1:0] pe_thr_negate_val;
reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_rd = 0;
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_pe
if (rd_rst_i) begin
diff_pntr_rd <= 0;
ideal_prog_empty <= 1'b1;
end else begin
if (ram_rd_en)
diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr) - 1'h1;
else if (!ram_rd_en)
diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr);
else
diff_pntr_rd <= #`TCQ diff_pntr_rd;
if (C_PROG_EMPTY_TYPE == 1) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else
ideal_prog_empty <= #`TCQ 0;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 2) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else if (diff_pntr_rd > pe_thr_negate_val)
ideal_prog_empty <= #`TCQ 0;
else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 3) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else
ideal_prog_empty <= #`TCQ 0;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 4) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else if (diff_pntr_rd > pe_thr_negate_val)
ideal_prog_empty <= #`TCQ 0;
else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end //C_PROG_EMPTY_TYPE
end
end // gen_pe
generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_thr_input
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH - 2'h2 : PROG_EMPTY_THRESH;
end endgenerate // single_pe_thr_input
generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_thr_input
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH_ASSERT - 2'h2 : PROG_EMPTY_THRESH_ASSERT;
assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH_NEGATE - 2'h2 : PROG_EMPTY_THRESH_NEGATE;
end endgenerate // multiple_pe_thr_input
generate if (C_PROG_EMPTY_TYPE < 3) begin : single_multiple_pe_thr_const
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2'h2 : C_PROG_EMPTY_THRESH_ASSERT_VAL;
assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2'h2 : C_PROG_EMPTY_THRESH_NEGATE_VAL;
end endgenerate // single_multiple_pe_thr_const
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_rp
if (rd_rst_i && C_EN_SAFETY_CKT == 0)
rd_pntr <= 0;
else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_RD_RST == 1'b1)
rd_pntr <= #`TCQ 0;
end
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r_as
/****** Reset fifo (case 1)***************************************/
if (rd_rst_i) begin
num_rd_bits <= 0;
next_num_rd_bits = 0;
rd_ptr <= C_RD_DEPTH -1;
rd_pntr_wr1 <= 0;
wr_ptr_rdclk <= C_WR_DEPTH -1;
// DRAM resets asynchronously
if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1)
ideal_dout <= dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type <= 0;
err_type_d1 <= 0;
err_type_both <= 0;
end
ideal_valid <= 1'b0;
ideal_rd_count <= 0;
end else begin //rd_rst_i==0
rd_pntr_wr1 <= #`TCQ rd_pntr;
//Determine the current number of words in the FIFO
tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :
num_rd_bits/C_DOUT_WIDTH;
wr_ptr_rdclk_next = wr_ptr;
if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH
- wr_ptr_rdclk_next);
end else begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);
end
/*****************************************************************/
// Read Operation - Read Latency 1
/*****************************************************************/
if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin
ideal_valid <= #`TCQ 1'b0;
if (ram_rd_en == 1'b1) begin
if (EMPTY == 1'b1) begin
//If the FIFO is completely empty, and is reporting empty
if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
//If the FIFO is one from empty, but it is reporting empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that FIFO is no longer empty, but is almost empty (has one word left)
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 1)
//If the FIFO is two from empty, and is reporting empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Fifo has two words, so is neither empty or almost empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
//If the FIFO is not close to empty, but is reporting that it is
// Treat the FIFO as empty this time, but unset EMPTY flags.
if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH))
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that the FIFO is No Longer Empty or Almost Empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
end // else: if(ideal_empty == 1'b1)
else //if (ideal_empty == 1'b0)
begin
//If the FIFO is completely full, and we are successfully reading from it
if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH)
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH)
//If the FIFO is not close to being empty
else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH))
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
//If the FIFO is two from empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Fifo is not yet empty. It is going almost_empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
//If the FIFO is one from empty
else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1))
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Note that FIFO is GOING empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 1)
//If the FIFO is completely empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
end // if (ideal_empty == 1'b0)
end //(RD_EN == 1'b1)
else //if (RD_EN == 1'b0)
begin
//If user did not attempt a read, do not give an ack or err
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // else: !if(RD_EN == 1'b1)
/*****************************************************************/
// Read Operation - Read Latency 0
/*****************************************************************/
end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin
ideal_valid <= #`TCQ 1'b0;
if (ram_rd_en == 1'b1) begin
if (EMPTY == 1'b1) begin
//If the FIFO is completely empty, and is reporting empty
if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is one from empty, but it is reporting empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that FIFO is no longer empty, but is almost empty (has one word left)
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is two from empty, and is reporting empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Fifo has two words, so is neither empty or almost empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is not close to empty, but is reporting that it is
// Treat the FIFO as empty this time, but unset EMPTY flags.
end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&
(tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH)) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that the FIFO is No Longer Empty or Almost Empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
end else begin
//If the FIFO is completely full, and we are successfully reading from it
if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is not close to being empty
end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&
(tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is two from empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Fifo is not yet empty. It is going almost_empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is one from empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Note that FIFO is GOING empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is completely empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
end // if (ideal_empty == 1'b0)
end else begin//(RD_EN == 1'b0)
//If user did not attempt a read, do not give an ack or err
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // else: !if(RD_EN == 1'b1)
end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0)
num_rd_bits <= #`TCQ next_num_rd_bits;
wr_ptr_rdclk <= #`TCQ wr_ptr;
end //rd_rst_i==0
end //always gen_fifo_r_as
endmodule // fifo_generator_v13_1_3_bhv_ver_as
/*******************************************************************************
* Declaration of Low Latency Asynchronous FIFO
******************************************************************************/
module fifo_generator_v13_1_3_beh_ver_ll_afifo
/***************************************************************************
* Declare user parameters and their defaults
***************************************************************************/
#(
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_USE_DOUT_RST = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_FIFO_TYPE = 0
)
/***************************************************************************
* Declare Input and Output Ports
***************************************************************************/
(
input [C_DIN_WIDTH-1:0] DIN,
input RD_CLK,
input RD_EN,
input WR_RST,
input RD_RST,
input WR_CLK,
input WR_EN,
output reg [C_DOUT_WIDTH-1:0] DOUT = 0,
output reg EMPTY = 1'b1,
output reg FULL = C_FULL_FLAGS_RST_VAL
);
//-----------------------------------------------------------------------------
// Low Latency Asynchronous FIFO
//-----------------------------------------------------------------------------
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
integer i;
initial begin
for (i = 0; i < C_WR_DEPTH; i = i + 1)
memory[i] = 0;
end
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_ll_afifo = 0;
wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo_q = 0;
reg ll_afifo_full = 1'b0;
reg ll_afifo_empty = 1'b1;
wire write_allow;
wire read_allow;
assign write_allow = WR_EN & ~ll_afifo_full;
assign read_allow = RD_EN & ~ll_afifo_empty;
//-----------------------------------------------------------------------------
// Write Pointer Generation
//-----------------------------------------------------------------------------
always @(posedge WR_CLK or posedge WR_RST) begin
if (WR_RST)
wr_pntr_ll_afifo <= 0;
else if (write_allow)
wr_pntr_ll_afifo <= #`TCQ wr_pntr_ll_afifo + 1;
end
//-----------------------------------------------------------------------------
// Read Pointer Generation
//-----------------------------------------------------------------------------
always @(posedge RD_CLK or posedge RD_RST) begin
if (RD_RST)
rd_pntr_ll_afifo_q <= 0;
else
rd_pntr_ll_afifo_q <= #`TCQ rd_pntr_ll_afifo;
end
assign rd_pntr_ll_afifo = read_allow ? rd_pntr_ll_afifo_q + 1 : rd_pntr_ll_afifo_q;
//-----------------------------------------------------------------------------
// Fill the Memory
//-----------------------------------------------------------------------------
always @(posedge WR_CLK) begin
if (write_allow)
memory[wr_pntr_ll_afifo] <= #`TCQ DIN;
end
//-----------------------------------------------------------------------------
// Generate DOUT
//-----------------------------------------------------------------------------
always @(posedge RD_CLK) begin
DOUT <= #`TCQ memory[rd_pntr_ll_afifo];
end
//-----------------------------------------------------------------------------
// Generate EMPTY
//-----------------------------------------------------------------------------
always @(posedge RD_CLK or posedge RD_RST) begin
if (RD_RST)
ll_afifo_empty <= 1'b1;
else
ll_afifo_empty <= ((wr_pntr_ll_afifo == rd_pntr_ll_afifo_q) |
(read_allow & (wr_pntr_ll_afifo == (rd_pntr_ll_afifo_q + 2'h1))));
end
//-----------------------------------------------------------------------------
// Generate FULL
//-----------------------------------------------------------------------------
always @(posedge WR_CLK or posedge WR_RST) begin
if (WR_RST)
ll_afifo_full <= 1'b1;
else
ll_afifo_full <= ((rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h1)) |
(write_allow & (rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h2))));
end
always @* begin
FULL <= ll_afifo_full;
EMPTY <= ll_afifo_empty;
end
endmodule // fifo_generator_v13_1_3_beh_ver_ll_afifo
/*******************************************************************************
* Declaration of top-level module
******************************************************************************/
module fifo_generator_v13_1_3_bhv_ver_ss
/**************************************************************************
* Declare user parameters and their defaults
*************************************************************************/
#(
parameter C_FAMILY = "virtex7",
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_USE_ECC = 0,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_FIFO_TYPE = 0
)
/**************************************************************************
* Declare Input and Output Ports
*************************************************************************/
(
//Inputs
input SAFETY_CKT_WR_RST,
input CLK,
input [C_DIN_WIDTH-1:0] DIN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input RD_EN,
input RD_EN_USER,
input USER_EMPTY_FB,
input RST,
input RST_FULL_GEN,
input RST_FULL_FF,
input SRST,
input WR_EN,
input INJECTDBITERR,
input INJECTSBITERR,
input WR_RST_BUSY,
input RD_RST_BUSY,
//Outputs
output ALMOST_EMPTY,
output ALMOST_FULL,
output reg [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT = 0,
output [C_DOUT_WIDTH-1:0] DOUT,
output EMPTY,
output reg EMPTY_FB = 1'b1,
output FULL,
output OVERFLOW,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output PROG_EMPTY,
output PROG_FULL,
output VALID,
output UNDERFLOW,
output WR_ACK,
output SBITERR,
output DBITERR
);
reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;
wire [C_RD_PNTR_WIDTH:0] rd_data_count_i_ss;
wire [C_WR_PNTR_WIDTH:0] wr_data_count_i_ss;
reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;
/***************************************************************************
* Parameters used as constants
**************************************************************************/
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
localparam C_DEPTH_RATIO_WR =
(C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;
localparam C_DEPTH_RATIO_RD =
(C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;
//localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;
//localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;
localparam C_GRTR_PNTR_WIDTH = (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH ;
// C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC
// -----------------|------------------|-----------------|---------------
// 1 | 8 | C_RD_PNTR_WIDTH | 2
// 1 | 4 | C_RD_PNTR_WIDTH | 2
// 1 | 2 | C_RD_PNTR_WIDTH | 2
// 1 | 1 | C_WR_PNTR_WIDTH | 2
// 2 | 1 | C_WR_PNTR_WIDTH | 4
// 4 | 1 | C_WR_PNTR_WIDTH | 8
// 8 | 1 | C_WR_PNTR_WIDTH | 16
localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
wire [C_WR_PNTR_WIDTH:0] EXTRA_WORDS_PF = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
//wire [C_RD_PNTR_WIDTH:0] EXTRA_WORDS_PE = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);
localparam EXTRA_WORDS_PF_PARAM = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
//localparam EXTRA_WORDS_PE_PARAM = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);
localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;
localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);
localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;
localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);
//When RST is present, set FULL reset value to '1'.
//If core has no RST, make sure FULL powers-on as '0'.
//The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not
//changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0.
// Therefore, during SRST, all the FULL flags reset to 0.
localparam C_HAS_FAST_FIFO = 0;
localparam C_FIFO_WR_DEPTH = C_WR_DEPTH;
localparam C_FIFO_RD_DEPTH = C_RD_DEPTH;
// Local parameters used to determine whether to inject ECC error or not
localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;
localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;
localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;
localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION;
localparam C_DATA_WIDTH = (ENABLE_ERR_INJECTION == 1) ? (C_DIN_WIDTH+2) : C_DIN_WIDTH;
localparam IS_ASYMMETRY = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 0 : 1;
localparam LESSER_WIDTH = (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
localparam [C_RD_PNTR_WIDTH-1 : 0] DIFF_MAX_RD = {C_RD_PNTR_WIDTH{1'b1}};
localparam [C_WR_PNTR_WIDTH-1 : 0] DIFF_MAX_WR = {C_WR_PNTR_WIDTH{1'b1}};
/**************************************************************************
* FIFO Contents Tracking and Data Count Calculations
*************************************************************************/
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
reg [1:0] ecc_err[C_WR_DEPTH-1:0];
/**************************************************************************
* Internal Registers and wires
*************************************************************************/
//Temporary signals used for calculating the model's outputs. These
//are only used in the assign statements immediately following wire,
//parameter, and function declarations.
wire underflow_i;
wire valid_i;
wire valid_out;
reg [31:0] num_wr_bits;
reg [31:0] num_rd_bits;
reg [31:0] next_num_wr_bits;
reg [31:0] next_num_rd_bits;
//The write pointer - tracks write operations
// (Works opposite to core: wr_ptr is a DOWN counter)
reg [31:0] wr_ptr;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0;
reg wr_rst_d1 =0;
//The read pointer - tracks read operations
// (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)
reg [31:0] rd_ptr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0;
wire ram_rd_en;
wire empty_int;
wire almost_empty_int;
wire ram_wr_en;
wire full_int;
wire almost_full_int;
reg ram_rd_en_reg = 1'b0;
reg ram_rd_en_d1 = 1'b0;
reg fab_rd_en_d1 = 1'b0;
wire srst_rrst_busy;
//Ideal FIFO signals. These are the raw output of the behavioral model,
//which behaves like an ideal FIFO.
reg [1:0] err_type = 0;
reg [1:0] err_type_d1 = 0;
reg [1:0] err_type_both = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_both = 0;
wire [C_DOUT_WIDTH-1:0] ideal_dout_out;
wire fwft_enabled;
reg ideal_wr_ack = 0;
reg ideal_valid = 0;
reg ideal_overflow = C_OVERFLOW_LOW;
reg ideal_underflow = C_UNDERFLOW_LOW;
reg full_i = C_FULL_FLAGS_RST_VAL;
reg full_i_temp = 0;
reg empty_i = 1;
reg almost_full_i = 0;
reg almost_empty_i = 1;
reg prog_full_i = 0;
reg prog_empty_i = 1;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0;
wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd;
wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr;
reg [C_RD_PNTR_WIDTH-1:0] diff_count = 0;
reg write_allow_q = 0;
reg read_allow_q = 0;
reg valid_d1 = 0;
reg valid_both = 0;
reg valid_d2 = 0;
wire rst_i;
wire srst_i;
//user specified value for reseting the size of the fifo
reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
reg [31:0] wr_ptr_rdclk;
reg [31:0] wr_ptr_rdclk_next;
reg [31:0] rd_ptr_wrclk;
reg [31:0] rd_ptr_wrclk_next;
/****************************************************************************
* Function Declarations
***************************************************************************/
/****************************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***************************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) begin
case (def_data[7:0])
8'b00000000 : begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default : begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1) begin
if ((index*4)+j < C_DOUT_WIDTH) begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
/**************************************************************************
* log2_val
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function [31:0] log2_val;
input [31:0] binary_val;
begin
if (binary_val == 8) begin
log2_val = 3;
end else if (binary_val == 4) begin
log2_val = 2;
end else begin
log2_val = 1;
end
end
endfunction
reg ideal_prog_full = 0;
reg ideal_prog_empty = 1;
reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;
reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;
//Assorted reg values for delayed versions of signals
//reg valid_d1 = 0;
//user specified value for reseting the size of the fifo
//reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
//temporary registers for WR_RESPONSE_LATENCY feature
integer tmp_wr_listsize;
integer tmp_rd_listsize;
//Signal for registered version of prog full and empty
//Threshold values for Programmable Flags
integer prog_empty_actual_thresh_assert;
integer prog_empty_actual_thresh_negate;
integer prog_full_actual_thresh_assert;
integer prog_full_actual_thresh_negate;
/**************************************************************************
* write_fifo
* This task writes a word to the FIFO memory and updates the
* write pointer.
* FIFO size is relative to write domain.
***************************************************************************/
task write_fifo;
begin
memory[wr_ptr] <= DIN;
wr_pntr <= #`TCQ wr_pntr + 1;
// Store the type of error injection (double/single) on write
case (C_ERROR_INJECTION_TYPE)
3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR};
2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0};
1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR};
default: ecc_err[wr_ptr] <= 0;
endcase
// (Works opposite to core: wr_ptr is a DOWN counter)
if (wr_ptr == 0) begin
wr_ptr <= C_WR_DEPTH - 1;
end else begin
wr_ptr <= wr_ptr - 1;
end
end
endtask // write_fifo
/**************************************************************************
* read_fifo
* This task reads a word from the FIFO memory and updates the read
* pointer. It's output is the ideal_dout bus.
* FIFO size is relative to write domain.
***************************************************************************/
task read_fifo;
integer i;
reg [C_DOUT_WIDTH-1:0] tmp_dout;
reg [C_DIN_WIDTH-1:0] memory_read;
reg [31:0] tmp_rd_ptr;
reg [31:0] rd_ptr_high;
reg [31:0] rd_ptr_low;
reg [1:0] tmp_ecc_err;
begin
rd_pntr <= #`TCQ rd_pntr + 1;
// output is wider than input
if (reads_per_write == 0) begin
tmp_dout = 0;
tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);
for (i = writes_per_read - 1; i >= 0; i = i - 1) begin
tmp_dout = tmp_dout << C_DIN_WIDTH;
tmp_dout = tmp_dout | memory[tmp_rd_ptr];
// (Works opposite to core: rd_ptr is a DOWN counter)
if (tmp_rd_ptr == 0) begin
tmp_rd_ptr = C_WR_DEPTH - 1;
end else begin
tmp_rd_ptr = tmp_rd_ptr - 1;
end
end
// output is symmetric
end else if (reads_per_write == 1) begin
tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];
// Retreive the error injection type. Based on the error injection type
// corrupt the output data.
tmp_ecc_err = ecc_err[rd_ptr];
if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin
if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error
if (C_DOUT_WIDTH == 1) begin
$display("FAILURE : Data width must be >= 2 for double bit error injection.");
$finish;
end else if (C_DOUT_WIDTH == 2)
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};
else
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};
end else begin
tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];
end
err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};
end else begin
err_type <= 0;
end
// input is wider than output
end else begin
rd_ptr_high = rd_ptr >> log2_reads_per_write;
rd_ptr_low = rd_ptr & (reads_per_write - 1);
memory_read = memory[rd_ptr_high];
tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);
end
ideal_dout <= tmp_dout;
// (Works opposite to core: rd_ptr is a DOWN counter)
if (rd_ptr == 0) begin
rd_ptr <= C_RD_DEPTH - 1;
end else begin
rd_ptr <= rd_ptr - 1;
end
end
endtask
/*************************************************************************
* Initialize Signals for clean power-on simulation
*************************************************************************/
initial begin
num_wr_bits = 0;
num_rd_bits = 0;
next_num_wr_bits = 0;
next_num_rd_bits = 0;
rd_ptr = C_RD_DEPTH - 1;
wr_ptr = C_WR_DEPTH - 1;
wr_pntr = 0;
rd_pntr = 0;
rd_ptr_wrclk = rd_ptr;
wr_ptr_rdclk = wr_ptr;
dout_reset_val = hexstr_conv(C_DOUT_RST_VAL);
ideal_dout = dout_reset_val;
err_type = 0;
err_type_d1 = 0;
err_type_both = 0;
ideal_dout_d1 = dout_reset_val;
ideal_dout_both = dout_reset_val;
ideal_wr_ack = 1'b0;
ideal_valid = 1'b0;
valid_d1 = 1'b0;
valid_both = 1'b0;
ideal_overflow = C_OVERFLOW_LOW;
ideal_underflow = C_UNDERFLOW_LOW;
ideal_wr_count = 0;
ideal_rd_count = 0;
ideal_prog_full = 1'b0;
ideal_prog_empty = 1'b1;
end
/*************************************************************************
* Connect the module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire CLK;
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire RD_EN;
wire RST;
wire WR_EN;
*/
// Assign ALMOST_EPMTY
generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae
assign ALMOST_EMPTY = almost_empty_i;
end else begin : gnae
assign ALMOST_EMPTY = 0;
end endgenerate // gae
// Assign ALMOST_FULL
generate if (C_HAS_ALMOST_FULL==1) begin : gaf
assign ALMOST_FULL = almost_full_i;
end else begin : gnaf
assign ALMOST_FULL = 0;
end endgenerate // gaf
// Dout may change behavior based on latency
localparam C_FWFT_ENABLED = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?
1: 0;
assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?
1: 0;
assign ideal_dout_out= ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))?
ideal_dout_d1: ideal_dout;
assign DOUT = ideal_dout_out;
// Assign SBITERR and DBITERR based on latency
assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) &&
((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[0]: err_type[0];
assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&
((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[1]: err_type[1];
assign EMPTY = empty_i;
assign FULL = full_i;
//saftey_ckt with one register
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && (C_USE_EMBEDDED_REG == 1 || C_USE_EMBEDDED_REG == 2 )) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge CLK)
begin
rst_delayed_sft1 <= #`TCQ rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK)
begin
if( rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
valid_d1 <= #`TCQ 1'b0;
end
else begin
ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));
valid_d1 <= #`TCQ valid_i;
end
end
always@(posedge rst_delayed_sft2 or posedge CLK)
begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end
else if (srst_rrst_busy == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1[0] <= #`TCQ err_type[0];
err_type_d1[1] <= #`TCQ err_type[1];
end
end
end //if
endgenerate
//safety ckt with both registers
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge CLK) begin
rst_delayed_sft1 <= #`TCQ rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK) begin
if (rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
valid_d1 <= #`TCQ 1'b0;
end else begin
ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));
fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
valid_both <= #`TCQ valid_i;
valid_d1 <= #`TCQ valid_both;
end
end
always@(posedge rst_delayed_sft2 or posedge CLK) begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else if (srst_rrst_busy == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both[0] <= #`TCQ err_type[0];
err_type_both[1] <= #`TCQ err_type[1];
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1[0] <= #`TCQ err_type_both[0];
err_type_d1[1] <= #`TCQ err_type_both[1];
end
end
end
end //if
endgenerate
//Overflow may be active-low
generate if (C_HAS_OVERFLOW==1) begin : gof
assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;
end else begin : gnof
assign OVERFLOW = 0;
end endgenerate // gof
assign PROG_EMPTY = prog_empty_i;
assign PROG_FULL = prog_full_i;
//Valid may change behavior based on latency or active-low
generate if (C_HAS_VALID==1) begin : gvalid
assign valid_i = (C_PRELOAD_LATENCY == 0) ? (RD_EN & ~EMPTY) : ideal_valid;
assign valid_out = (C_PRELOAD_LATENCY == 2 && C_MEMORY_TYPE < 2) ?
valid_d1 : valid_i;
assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW;
end else begin : gnvalid
assign VALID = 0;
end endgenerate // gvalid
//Trim data count differently depending on set widths
generate if (C_HAS_DATA_COUNT == 1) begin : gdc
always @* begin
diff_count <= wr_pntr - rd_pntr;
if (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) begin
DATA_COUNT[C_RD_PNTR_WIDTH-1:0] <= diff_count;
DATA_COUNT[C_DATA_COUNT_WIDTH-1] <= 1'b0 ;
end else begin
DATA_COUNT <= diff_count[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH];
end
end
// end else begin : gndc
// always @* DATA_COUNT <= 0;
end endgenerate // gdc
//Underflow may change behavior based on latency or active-low
generate if (C_HAS_UNDERFLOW==1) begin : guf
assign underflow_i = ideal_underflow;
assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;
end else begin : gnuf
assign UNDERFLOW = 0;
end endgenerate // guf
//Write acknowledge may be active low
generate if (C_HAS_WR_ACK==1) begin : gwr_ack
assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;
end else begin : gnwr_ack
assign WR_ACK = 0;
end endgenerate // gwr_ack
/*****************************************************************************
* Internal reset logic
****************************************************************************/
assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_WR_RST : C_HAS_SRST ? (SRST | WR_RST_BUSY) : 0;
assign rst_i = C_HAS_RST ? RST : 0;
assign srst_wrst_busy = srst_i;
assign srst_rrst_busy = srst_i;
/**************************************************************************
* Assorted registers for delayed versions of signals
**************************************************************************/
//Capture delayed version of valid
generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG <3)) begin : blockVL20
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
valid_d1 <= 1'b0;
end else begin
if (srst_rrst_busy) begin
valid_d1 <= #`TCQ 1'b0;
end else begin
valid_d1 <= #`TCQ valid_i;
end
end
end // always @ (posedge CLK or posedge rst_i)
end
endgenerate // blockVL20
generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG == 3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
valid_d1 <= 1'b0;
valid_both <= 1'b0;
end else begin
if (srst_rrst_busy) begin
valid_d1 <= #`TCQ 1'b0;
valid_both <= #`TCQ 1'b0;
end else begin
valid_both <= #`TCQ valid_i;
valid_d1 <= #`TCQ valid_both;
end
end
end // always @ (posedge CLK or posedge rst_i)
end
endgenerate // blockVL20
// Determine which stage in FWFT registers are valid
reg stage1_valid = 0;
reg stage2_valid = 0;
generate
if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc
always @ (posedge CLK or posedge rst_i) begin
if (rst_i) begin
stage1_valid <= #`TCQ 0;
stage2_valid <= #`TCQ 0;
end else begin
if (!stage1_valid && !stage2_valid) begin
if (!EMPTY)
stage1_valid <= #`TCQ 1'b1;
else
stage1_valid <= #`TCQ 1'b0;
end else if (stage1_valid && !stage2_valid) begin
if (EMPTY) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else if (!stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && !RD_EN) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end
end else if (stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
end
endgenerate
//***************************************************************************
// Assign the read data count value only if it is selected,
// otherwise output zeros.
//***************************************************************************
generate
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT ==1) begin : grdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = rd_data_count_i_ss[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//***************************************************************************
// Assign the write data count value only if it is selected,
// otherwise output zeros
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : gwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = wr_data_count_i_ss[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] ;
end
endgenerate
generate
if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//reg ram_rd_en_d1 = 1'b0;
//Capture delayed version of dout
generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG<3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// DRAM and SRAM reset asynchronously
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
ram_rd_en_d1 <= #`TCQ 1'b0;
if (C_USE_DOUT_RST == 1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;
if (srst_rrst_busy) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
// @(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1 ) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1 <= #`TCQ err_type;
end
end
end
end // always
end
endgenerate
//no safety ckt with both registers
generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG==3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
fab_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// DRAM and SRAM reset asynchronously
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end else begin
if (srst_rrst_busy) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
fab_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;
fab_rd_en_d1 <= #`TCQ (ram_rd_en_d1);
if (ram_rd_en_d1 ) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both <= #`TCQ err_type;
end
if (fab_rd_en_d1 ) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1 <= #`TCQ err_type_both;
end
end
end
end // always
end
endgenerate
/**************************************************************************
* Overflow and Underflow Flag calculation
* (handled separately because they don't support rst)
**************************************************************************/
generate if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw
always @(posedge CLK) begin
ideal_overflow <= #`TCQ WR_EN & full_i;
end
end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw
always @(posedge CLK) begin
//ideal_overflow <= #`TCQ WR_EN & (rst_i | full_i);
ideal_overflow <= #`TCQ WR_EN & (WR_RST_BUSY | full_i);
end
end endgenerate // blockOF20
generate if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw
always @(posedge CLK) begin
ideal_underflow <= #`TCQ empty_i & RD_EN;
end
end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw
always @(posedge CLK) begin
//ideal_underflow <= #`TCQ (rst_i | empty_i) & RD_EN;
ideal_underflow <= #`TCQ (RD_RST_BUSY | empty_i) & RD_EN;
end
end endgenerate // blockUF20
/**************************
* Read Data Count
*************************/
reg [31:0] num_read_words_dc;
reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;
always @(num_rd_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//If using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain,
// and add two read words for FWFT stages
//This value is only a temporary value and not used in the code.
num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];
end else begin
//If not using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain.
//This value is only a temporary value and not used in the code.
num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/**************************
* Write Data Count
*************************/
reg [31:0] num_write_words_dc;
reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;
always @(num_wr_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//Calculate the Data Count value for the number of write words,
// when using First-Word Fall-Through with extra logic for Data
// Counts. This takes into consideration the number of words that
// are expected to be stored in the FWFT register stages (it always
// assumes they are filled).
//This value is scaled to the Write Domain.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//EXTRA_WORDS_DC is the number of words added to write_words
// due to FWFT.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;
//Trim the write words for use with WR_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];
end else begin
//Calculate the Data Count value for the number of write words, when NOT
// using First-Word Fall-Through with extra logic for Data Counts. This
// calculates only the number of words in the internal FIFO.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//This value is scaled to the Write Domain.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;
//Trim the read words for use with RD_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/*************************************************************************
* Write and Read Logic
************************************************************************/
wire write_allow;
wire read_allow;
wire read_allow_dc;
wire write_only;
wire read_only;
//wire write_only_q;
reg write_only_q;
//wire read_only_q;
reg read_only_q;
reg full_reg;
reg rst_full_ff_reg1;
reg rst_full_ff_reg2;
wire ram_full_comb;
wire carry;
assign write_allow = WR_EN & ~full_i;
assign read_allow = RD_EN & ~empty_i;
assign read_allow_dc = RD_EN_USER & ~USER_EMPTY_FB;
//assign write_only = write_allow & ~read_allow;
//assign write_only_q = write_allow_q;
//assign read_only = read_allow & ~write_allow;
//assign read_only_q = read_allow_q ;
wire [C_WR_PNTR_WIDTH-1:0] diff_pntr;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_reg1 = 0;
reg [C_RD_PNTR_WIDTH:0] diff_pntr_pe_asym = 0;
wire [C_RD_PNTR_WIDTH:0] adj_wr_pntr_rd_asym ;
wire [C_RD_PNTR_WIDTH:0] rd_pntr_asym;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_pe_reg2 = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_max;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_max;
assign diff_pntr_pe_max = DIFF_MAX_RD;
assign diff_pntr_max = DIFF_MAX_WR;
generate if (IS_ASYMMETRY == 0) begin : diff_pntr_sym
assign write_only = write_allow & ~read_allow;
assign read_only = read_allow & ~write_allow;
end endgenerate
generate if ( IS_ASYMMETRY == 1 && C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : wr_grt_rd
assign read_only = read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]) & ~write_allow;
assign write_only = write_allow & ~(read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (IS_ASYMMETRY ==1 && C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : rd_grt_wr
assign read_only = read_allow & ~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
assign write_only = write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]) & ~read_allow;
end endgenerate
//-----------------------------------------------------------------------------
// Write and Read pointer generation
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i && C_EN_SAFETY_CKT == 0) begin
wr_pntr <= 0;
rd_pntr <= 0;
end else begin
if (srst_i) begin
wr_pntr <= #`TCQ 0;
rd_pntr <= #`TCQ 0;
end else begin
if (write_allow) wr_pntr <= #`TCQ wr_pntr + 1;
if (read_allow) rd_pntr <= #`TCQ rd_pntr + 1;
end
end
end
generate if (C_FIFO_TYPE == 2) begin : gll_dm_dout
always @(posedge CLK) begin
if (write_allow) begin
if (ENABLE_ERR_INJECTION == 1)
memory[wr_pntr] <= #`TCQ {INJECTDBITERR,INJECTSBITERR,DIN};
else
memory[wr_pntr] <= #`TCQ DIN;
end
end
reg [C_DATA_WIDTH-1:0] dout_tmp_q;
reg [C_DATA_WIDTH-1:0] dout_tmp = 0;
reg [C_DATA_WIDTH-1:0] dout_tmp1 = 0;
always @(posedge CLK) begin
dout_tmp_q <= #`TCQ ideal_dout;
end
always @* begin
if (read_allow)
ideal_dout <= memory[rd_pntr];
else
ideal_dout <= dout_tmp_q;
end
end endgenerate // gll_dm_dout
/**************************************************************************
* Write Domain Logic
**************************************************************************/
assign ram_rd_en = RD_EN & !EMPTY;
//reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;
generate if (C_FIFO_TYPE != 2) begin : gnll_din
always @(posedge CLK or posedge rst_i) begin : gen_fifo_w
/****** Reset fifo (case 1)***************************************/
if (rst_i == 1'b1) begin
num_wr_bits <= #`TCQ 0;
next_num_wr_bits = #`TCQ 0;
wr_ptr <= #`TCQ C_WR_DEPTH - 1;
rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1;
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ 0;
tmp_wr_listsize = #`TCQ 0;
rd_ptr_wrclk_next <= #`TCQ 0;
wr_pntr <= #`TCQ 0;
wr_pntr_rd1 <= #`TCQ 0;
end else begin //rst_i==0
if (srst_wrst_busy) begin
num_wr_bits <= #`TCQ 0;
next_num_wr_bits = #`TCQ 0;
wr_ptr <= #`TCQ C_WR_DEPTH - 1;
rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1;
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ 0;
tmp_wr_listsize = #`TCQ 0;
rd_ptr_wrclk_next <= #`TCQ 0;
wr_pntr <= #`TCQ 0;
wr_pntr_rd1 <= #`TCQ 0;
end else begin//srst_i=0
wr_pntr_rd1 <= #`TCQ wr_pntr;
//Determine the current number of words in the FIFO
tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :
num_wr_bits/C_DIN_WIDTH;
rd_ptr_wrclk_next = rd_ptr;
if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH
- rd_ptr_wrclk_next);
end else begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);
end
if (WR_EN == 1'b1) begin
if (FULL == 1'b1) begin
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end else begin
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Not even close to full.
ideal_wr_count <= num_write_words_sized_i;
//end
end
end else begin //(WR_EN == 1'b1)
//If user did not attempt a write, then do not
// give ack or err
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end
num_wr_bits <= #`TCQ next_num_wr_bits;
rd_ptr_wrclk <= #`TCQ rd_ptr;
end //srst_i==0
end //wr_rst_i==0
end // gen_fifo_w
end endgenerate
generate if (C_FIFO_TYPE < 2 && C_MEMORY_TYPE < 2) begin : gnll_dm_dout
always @(posedge CLK) begin
if (rst_i || srst_rrst_busy) begin
if (C_USE_DOUT_RST == 1) begin
ideal_dout <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end
end
end endgenerate
generate if (C_FIFO_TYPE != 2) begin : gnll_dout
always @(posedge CLK or posedge rst_i) begin : gen_fifo_r
/****** Reset fifo (case 1)***************************************/
if (rst_i) begin
num_rd_bits <= #`TCQ 0;
next_num_rd_bits = #`TCQ 0;
rd_ptr <= #`TCQ C_RD_DEPTH -1;
rd_pntr <= #`TCQ 0;
//rd_pntr_wr1 <= #`TCQ 0;
wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1;
// DRAM resets asynchronously
if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)
ideal_dout <= #`TCQ dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type <= #`TCQ 0;
err_type_d1 <= 0;
err_type_both <= 0;
end
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ 0;
end else begin //rd_rst_i==0
if (srst_rrst_busy) begin
num_rd_bits <= #`TCQ 0;
next_num_rd_bits = #`TCQ 0;
rd_ptr <= #`TCQ C_RD_DEPTH -1;
rd_pntr <= #`TCQ 0;
//rd_pntr_wr1 <= #`TCQ 0;
wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1;
// DRAM resets synchronously
if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)
ideal_dout <= #`TCQ dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type <= #`TCQ 0;
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ 0;
end //srst_i
else begin
//rd_pntr_wr1 <= #`TCQ rd_pntr;
//Determine the current number of words in the FIFO
tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :
num_rd_bits/C_DOUT_WIDTH;
wr_ptr_rdclk_next = wr_ptr;
if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH
- wr_ptr_rdclk_next);
end else begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);
end
if (RD_EN == 1'b1) begin
if (EMPTY == 1'b1) begin
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end
else
begin
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
end
num_rd_bits <= #`TCQ next_num_rd_bits;
wr_ptr_rdclk <= #`TCQ wr_ptr;
end //s_rst_i==0
end //rd_rst_i==0
end //always
end endgenerate
//-----------------------------------------------------------------------------
// Generate diff_pntr for PROG_FULL generation
// Generate diff_pntr_pe for PROG_EMPTY generation
//-----------------------------------------------------------------------------
generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 0) begin : reg_write_allow
always @(posedge CLK ) begin
if (rst_i) begin
write_only_q <= 1'b0;
read_only_q <= 1'b0;
diff_pntr_reg1 <= 0;
diff_pntr_pe_reg1 <= 0;
diff_pntr_reg2 <= 0;
diff_pntr_pe_reg2 <= 0;
end else begin
if (srst_i || srst_wrst_busy || srst_rrst_busy) begin
if (srst_rrst_busy) begin
read_only_q <= #`TCQ 1'b0;
diff_pntr_pe_reg1 <= #`TCQ 0;
diff_pntr_pe_reg2 <= #`TCQ 0;
end
if (srst_wrst_busy) begin
write_only_q <= #`TCQ 1'b0;
diff_pntr_reg1 <= #`TCQ 0;
diff_pntr_reg2 <= #`TCQ 0;
end
end else begin
write_only_q <= #`TCQ write_only;
read_only_q <= #`TCQ read_only;
diff_pntr_reg2 <= #`TCQ diff_pntr_reg1;
diff_pntr_pe_reg2 <= #`TCQ diff_pntr_pe_reg1;
// Add 1 to the difference pointer value when only write happens.
if (write_only)
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr + 1;
else
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;
// Add 1 to the difference pointer value when write or both write & read or no write & read happen.
if (read_only)
diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr - 1;
else
diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr;
end
end
end
assign diff_pntr_pe = diff_pntr_pe_reg1;
assign diff_pntr = diff_pntr_reg1;
end endgenerate // reg_write_allow
generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 1) begin : reg_write_allow_asym
assign adj_wr_pntr_rd_asym[C_RD_PNTR_WIDTH:0] = {adj_wr_pntr_rd,1'b1};
assign rd_pntr_asym[C_RD_PNTR_WIDTH:0] = {~rd_pntr,1'b1};
always @(posedge CLK ) begin
if (rst_i) begin
diff_pntr_pe_asym <= 0;
diff_pntr_reg1 <= 0;
full_reg <= 0;
rst_full_ff_reg1 <= 1;
rst_full_ff_reg2 <= 1;
diff_pntr_pe_reg1 <= 0;
end else begin
if (srst_i || srst_wrst_busy || srst_rrst_busy) begin
if (srst_wrst_busy)
diff_pntr_reg1 <= #`TCQ 0;
if (srst_rrst_busy)
full_reg <= #`TCQ 0;
rst_full_ff_reg1 <= #`TCQ 1;
rst_full_ff_reg2 <= #`TCQ 1;
diff_pntr_pe_asym <= #`TCQ 0;
diff_pntr_pe_reg1 <= #`TCQ 0;
end else begin
diff_pntr_pe_asym <= #`TCQ adj_wr_pntr_rd_asym + rd_pntr_asym;
full_reg <= #`TCQ full_i;
rst_full_ff_reg1 <= #`TCQ RST_FULL_FF;
rst_full_ff_reg2 <= #`TCQ rst_full_ff_reg1;
if (~full_i) begin
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;
end
end
end
end
assign carry = (~(|(diff_pntr_pe_asym [C_RD_PNTR_WIDTH : 1])));
assign diff_pntr_pe = (full_reg && ~rst_full_ff_reg2 && carry ) ? diff_pntr_pe_max : diff_pntr_pe_asym[C_RD_PNTR_WIDTH:1];
assign diff_pntr = diff_pntr_reg1;
end endgenerate // reg_write_allow_asym
//-----------------------------------------------------------------------------
// Generate FULL flag
//-----------------------------------------------------------------------------
wire comp0;
wire comp1;
wire going_full;
wire leaving_full;
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gpad
assign adj_rd_pntr_wr [C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr;
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0] = 0;
end endgenerate
generate if (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) begin : gtrim
assign adj_rd_pntr_wr = rd_pntr[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end endgenerate
assign comp1 = (adj_rd_pntr_wr == (wr_pntr + 1'b1));
assign comp0 = (adj_rd_pntr_wr == wr_pntr);
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gf_wp_eq_rp
assign going_full = (comp1 & write_allow & ~read_allow);
assign leaving_full = (comp0 & read_allow) | RST_FULL_GEN;
end endgenerate
// Write data width is bigger than read data width
// Write depth is smaller than read depth
// One write could be equal to 2 or 4 or 8 reads
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gf_asym
assign going_full = (comp1 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));
assign leaving_full = (comp0 & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gf_wp_gt_rp
assign going_full = (comp1 & write_allow & ~read_allow);
assign leaving_full =(comp0 & read_allow) | RST_FULL_GEN;
end endgenerate
assign ram_full_comb = going_full | (~leaving_full & full_i);
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF)
full_i <= C_FULL_FLAGS_RST_VAL;
else if (srst_wrst_busy)
full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else
full_i <= #`TCQ ram_full_comb;
end
//-----------------------------------------------------------------------------
// Generate EMPTY flag
//-----------------------------------------------------------------------------
wire ecomp0;
wire ecomp1;
wire going_empty;
wire leaving_empty;
wire ram_empty_comb;
generate if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : pad
assign adj_wr_pntr_rd [C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0] = 0;
end endgenerate
generate if (C_RD_PNTR_WIDTH <= C_WR_PNTR_WIDTH) begin : trim
assign adj_wr_pntr_rd = wr_pntr[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end endgenerate
assign ecomp1 = (adj_wr_pntr_rd == (rd_pntr + 1'b1));
assign ecomp0 = (adj_wr_pntr_rd == rd_pntr);
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : ge_wp_eq_rp
assign going_empty = (ecomp1 & ~write_allow & read_allow);
assign leaving_empty = (ecomp0 & write_allow);
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : ge_wp_gt_rp
assign going_empty = (ecomp1 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));
assign leaving_empty = (ecomp0 & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : ge_wp_lt_rp
assign going_empty = (ecomp1 & ~write_allow & read_allow);
assign leaving_empty =(ecomp0 & write_allow);
end endgenerate
assign ram_empty_comb = going_empty | (~leaving_empty & empty_i);
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
empty_i <= 1'b1;
else if (srst_rrst_busy)
empty_i <= #`TCQ 1'b1;
else
empty_i <= #`TCQ ram_empty_comb;
end
always @(posedge CLK or posedge rst_i) begin
if (rst_i && C_EN_SAFETY_CKT == 0) begin
EMPTY_FB <= 1'b1;
end else begin
if (srst_rrst_busy || (SAFETY_CKT_WR_RST && C_EN_SAFETY_CKT))
EMPTY_FB <= #`TCQ 1'b1;
else
EMPTY_FB <= #`TCQ ram_empty_comb;
end
end // always
//-----------------------------------------------------------------------------
// Generate Read and write data counts for asymmetic common clock
//-----------------------------------------------------------------------------
reg [C_GRTR_PNTR_WIDTH :0] count_dc = 0;
wire [C_GRTR_PNTR_WIDTH :0] ratio;
wire decr_by_one;
wire incr_by_ratio;
wire incr_by_one;
wire decr_by_ratio;
localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : rd_depth_gt_wr
assign ratio = C_DEPTH_RATIO_RD;
assign decr_by_one = (IS_FWFT == 1)? read_allow_dc : read_allow;
assign incr_by_ratio = write_allow;
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
count_dc <= #`TCQ 0;
else if (srst_wrst_busy)
count_dc <= #`TCQ 0;
else begin
if (decr_by_one) begin
if (!incr_by_ratio)
count_dc <= #`TCQ count_dc - 1;
else
count_dc <= #`TCQ count_dc - 1 + ratio ;
end
else begin
if (!incr_by_ratio)
count_dc <= #`TCQ count_dc ;
else
count_dc <= #`TCQ count_dc + ratio ;
end
end
end
assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc;
assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wr_depth_gt_rd
assign ratio = C_DEPTH_RATIO_WR;
assign incr_by_one = write_allow;
assign decr_by_ratio = (IS_FWFT == 1)? read_allow_dc : read_allow;
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
count_dc <= #`TCQ 0;
else if (srst_wrst_busy)
count_dc <= #`TCQ 0;
else begin
if (incr_by_one) begin
if (!decr_by_ratio)
count_dc <= #`TCQ count_dc + 1;
else
count_dc <= #`TCQ count_dc + 1 - ratio ;
end
else begin
if (!decr_by_ratio)
count_dc <= #`TCQ count_dc ;
else
count_dc <= #`TCQ count_dc - ratio ;
end
end
end
assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc;
assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end endgenerate
//-----------------------------------------------------------------------------
// Generate WR_ACK flag
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
ideal_wr_ack <= 1'b0;
else if (srst_wrst_busy)
ideal_wr_ack <= #`TCQ 1'b0;
else if (WR_EN & ~full_i)
ideal_wr_ack <= #`TCQ 1'b1;
else
ideal_wr_ack <= #`TCQ 1'b0;
end
//-----------------------------------------------------------------------------
// Generate VALID flag
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
ideal_valid <= 1'b0;
else if (srst_rrst_busy)
ideal_valid <= #`TCQ 1'b0;
else if (RD_EN & ~empty_i)
ideal_valid <= #`TCQ 1'b1;
else
ideal_valid <= #`TCQ 1'b0;
end
//-----------------------------------------------------------------------------
// Generate ALMOST_FULL flag
//-----------------------------------------------------------------------------
//generate if (C_HAS_ALMOST_FULL == 1 || C_PROG_FULL_TYPE > 2 || C_PROG_EMPTY_TYPE > 2) begin : gaf_ss
wire fcomp2;
wire going_afull;
wire leaving_afull;
wire ram_afull_comb;
assign fcomp2 = (adj_rd_pntr_wr == (wr_pntr + 2'h2));
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gaf_wp_eq_rp
assign going_afull = (fcomp2 & write_allow & ~read_allow);
assign leaving_afull = (comp1 & read_allow & ~write_allow) | RST_FULL_GEN;
end endgenerate
// Write data width is bigger than read data width
// Write depth is smaller than read depth
// One write could be equal to 2 or 4 or 8 reads
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gaf_asym
assign going_afull = (fcomp2 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));
assign leaving_afull = (comp1 & (~write_allow) & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gaf_wp_gt_rp
assign going_afull = (fcomp2 & write_allow & ~read_allow);
assign leaving_afull =((comp0 | comp1 | fcomp2) & read_allow) | RST_FULL_GEN;
end endgenerate
assign ram_afull_comb = going_afull | (~leaving_afull & almost_full_i);
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF)
almost_full_i <= C_FULL_FLAGS_RST_VAL;
else if (srst_wrst_busy)
almost_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else
almost_full_i <= #`TCQ ram_afull_comb;
end
// end endgenerate // gaf_ss
//-----------------------------------------------------------------------------
// Generate ALMOST_EMPTY flag
//-----------------------------------------------------------------------------
//generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae_ss
wire ecomp2;
wire going_aempty;
wire leaving_aempty;
wire ram_aempty_comb;
assign ecomp2 = (adj_wr_pntr_rd == (rd_pntr + 2'h2));
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gae_wp_eq_rp
assign going_aempty = (ecomp2 & ~write_allow & read_allow);
assign leaving_aempty = (ecomp1 & write_allow & ~read_allow);
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gae_wp_gt_rp
assign going_aempty = (ecomp2 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));
assign leaving_aempty = (ecomp1 & ~read_allow & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gae_wp_lt_rp
assign going_aempty = (ecomp2 & ~write_allow & read_allow);
assign leaving_aempty =((ecomp2 | ecomp1 |ecomp0) & write_allow);
end endgenerate
assign ram_aempty_comb = going_aempty | (~leaving_aempty & almost_empty_i);
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
almost_empty_i <= 1'b1;
else if (srst_rrst_busy)
almost_empty_i <= #`TCQ 1'b1;
else
almost_empty_i <= #`TCQ ram_aempty_comb;
end
// end endgenerate // gae_ss
//-----------------------------------------------------------------------------
// Generate PROG_FULL
//-----------------------------------------------------------------------------
localparam C_PF_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_PF_PARAM : // FWFT
C_PROG_FULL_THRESH_ASSERT_VAL; // STD
localparam C_PF_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_PF_PARAM: // FWFT
C_PROG_FULL_THRESH_NEGATE_VAL; // STD
//-----------------------------------------------------------------------------
// Generate PROG_FULL for single programmable threshold constant
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] temp = C_PF_ASSERT_VAL;
generate if (C_PROG_FULL_TYPE == 1) begin : single_pf_const
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == C_PF_ASSERT_VAL && read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~RST_FULL_GEN ) begin
if (diff_pntr>= C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b1;
else if ((diff_pntr) < C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ 1'b0;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate // single_pf_const
//-----------------------------------------------------------------------------
// Generate PROG_FULL for multiple programmable threshold constants
//-----------------------------------------------------------------------------
generate if (C_PROG_FULL_TYPE == 2) begin : multiple_pf_const
always @(posedge CLK or posedge RST_FULL_FF) begin
//if (RST_FULL_FF)
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == C_PF_NEGATE_VAL && read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~RST_FULL_GEN ) begin
if (diff_pntr >= C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < C_PF_NEGATE_VAL)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate //multiple_pf_const
//-----------------------------------------------------------------------------
// Generate PROG_FULL for single programmable threshold input port
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] pf3_assert_val = (C_PRELOAD_LATENCY == 0) ?
PROG_FULL_THRESH - EXTRA_WORDS_PF: // FWFT
PROG_FULL_THRESH; // STD
generate if (C_PROG_FULL_TYPE == 3) begin : single_pf_input
always @(posedge CLK or posedge RST_FULL_FF) begin//0
//if (RST_FULL_FF)
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin //1
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin//2
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~almost_full_i) begin//3
if (diff_pntr > pf3_assert_val)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == pf3_assert_val) begin//4
if (read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ 1'b1;
end else//4
prog_full_i <= #`TCQ 1'b0;
end else//3
prog_full_i <= #`TCQ prog_full_i;
end //2
else begin//5
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~full_i ) begin//6
if (diff_pntr >= pf3_assert_val )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < pf3_assert_val) begin//7
prog_full_i <= #`TCQ 1'b0;
end//7
end//6
else
prog_full_i <= #`TCQ prog_full_i;
end//5
end//1
end//0
end endgenerate //single_pf_input
//-----------------------------------------------------------------------------
// Generate PROG_FULL for multiple programmable threshold input ports
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] pf_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_FULL_THRESH_ASSERT -EXTRA_WORDS_PF) : // FWFT
PROG_FULL_THRESH_ASSERT; // STD
wire [C_WR_PNTR_WIDTH-1:0] pf_negate_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_FULL_THRESH_NEGATE -EXTRA_WORDS_PF) : // FWFT
PROG_FULL_THRESH_NEGATE; // STD
generate if (C_PROG_FULL_TYPE == 4) begin : multiple_pf_inputs
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~almost_full_i) begin
if (diff_pntr >= pf_assert_val)
prog_full_i <= #`TCQ 1'b1;
else if ((diff_pntr == pf_negate_val && read_only_q) ||
diff_pntr < pf_negate_val)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~full_i ) begin
if (diff_pntr >= pf_assert_val )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < pf_negate_val)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate //multiple_pf_inputs
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY
//-----------------------------------------------------------------------------
localparam C_PE_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2: // FWFT
C_PROG_EMPTY_THRESH_ASSERT_VAL; // STD
localparam C_PE_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2: // FWFT
C_PROG_EMPTY_THRESH_NEGATE_VAL; // STD
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for single programmable threshold constant
//-----------------------------------------------------------------------------
generate if (C_PROG_EMPTY_TYPE == 1) begin : single_pe_const
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == C_PE_ASSERT_VAL && write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (~rst_i ) begin
if (diff_pntr_pe <= C_PE_ASSERT_VAL)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > C_PE_ASSERT_VAL)
prog_empty_i <= #`TCQ 1'b0;
end
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // single_pe_const
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for multiple programmable threshold constants
//-----------------------------------------------------------------------------
generate if (C_PROG_EMPTY_TYPE == 2) begin : multiple_pe_const
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == C_PE_NEGATE_VAL && write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (~rst_i ) begin
if (diff_pntr_pe <= C_PE_ASSERT_VAL )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > C_PE_NEGATE_VAL)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate //multiple_pe_const
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for single programmable threshold input port
//-----------------------------------------------------------------------------
wire [C_RD_PNTR_WIDTH-1:0] pe3_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH -2) : // FWFT
PROG_EMPTY_THRESH; // STD
generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_input
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (~almost_full_i) begin
if (diff_pntr_pe < pe3_assert_val)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == pe3_assert_val) begin
if (write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ 1'b1;
end else
prog_empty_i <= #`TCQ 1'b0;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (diff_pntr_pe <= pe3_assert_val )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > pe3_assert_val)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // single_pe_input
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for multiple programmable threshold input ports
//-----------------------------------------------------------------------------
wire [C_RD_PNTR_WIDTH-1:0] pe4_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH_ASSERT - 2) : // FWFT
PROG_EMPTY_THRESH_ASSERT; // STD
wire [C_RD_PNTR_WIDTH-1:0] pe4_negate_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH_NEGATE - 2) : // FWFT
PROG_EMPTY_THRESH_NEGATE; // STD
generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_inputs
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (~almost_full_i) begin
if (diff_pntr_pe <= pe4_assert_val)
prog_empty_i <= #`TCQ 1'b1;
else if (((diff_pntr_pe == pe4_negate_val) && write_only_q) ||
(diff_pntr_pe > pe4_negate_val)) begin
prog_empty_i <= #`TCQ 1'b0;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (diff_pntr_pe <= pe4_assert_val )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > pe4_negate_val)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // multiple_pe_inputs
endmodule // fifo_generator_v13_1_3_bhv_ver_ss
/**************************************************************************
* First-Word Fall-Through module (preload 0)
**************************************************************************/
module fifo_generator_v13_1_3_bhv_ver_preload0
#(
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_HAS_RST = 0,
parameter C_ENABLE_RST_SYNC = 0,
parameter C_HAS_SRST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USERVALID_LOW = 0,
parameter C_USERUNDERFLOW_LOW = 0,
parameter C_MEMORY_TYPE = 0,
parameter C_FIFO_TYPE = 0
)
(
//Inputs
input SAFETY_CKT_RD_RST,
input RD_CLK,
input RD_RST,
input SRST,
input WR_RST_BUSY,
input RD_RST_BUSY,
input RD_EN,
input FIFOEMPTY,
input [C_DOUT_WIDTH-1:0] FIFODATA,
input FIFOSBITERR,
input FIFODBITERR,
//Outputs
output reg [C_DOUT_WIDTH-1:0] USERDATA,
output USERVALID,
output USERUNDERFLOW,
output USEREMPTY,
output USERALMOSTEMPTY,
output RAMVALID,
output FIFORDEN,
output reg USERSBITERR,
output reg USERDBITERR,
output reg STAGE2_REG_EN,
output fab_read_data_valid_i_o,
output read_data_valid_i_o,
output ram_valid_i_o,
output [1:0] VALID_STAGES
);
//Internal signals
wire preloadstage1;
wire preloadstage2;
reg ram_valid_i;
reg fab_valid;
reg read_data_valid_i;
reg fab_read_data_valid_i;
reg fab_read_data_valid_i_1;
reg ram_valid_i_d;
reg read_data_valid_i_d;
reg fab_read_data_valid_i_d;
wire ram_regout_en;
reg ram_regout_en_d1;
reg ram_regout_en_d2;
wire fab_regout_en;
wire ram_rd_en;
reg empty_i = 1'b1;
reg empty_sckt = 1'b1;
reg sckt_rrst_q = 1'b0;
reg sckt_rrst_done = 1'b0;
reg empty_q = 1'b1;
reg rd_en_q = 1'b0;
reg almost_empty_i = 1'b1;
reg almost_empty_q = 1'b1;
wire rd_rst_i;
wire srst_i;
reg [C_DOUT_WIDTH-1:0] userdata_both;
wire uservalid_both;
wire uservalid_one;
reg user_sbiterr_both = 1'b0;
reg user_dbiterr_both = 1'b0;
assign ram_valid_i_o = ram_valid_i;
assign read_data_valid_i_o = read_data_valid_i;
assign fab_read_data_valid_i_o = fab_read_data_valid_i;
/*************************************************************************
* FUNCTIONS
*************************************************************************/
/*************************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***********************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )
begin
case (def_data[7:0])
8'b00000000 :
begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default :
begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1)
begin
if ((index*4)+j < C_DOUT_WIDTH)
begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
//*************************************************************************
// Set power-on states for regs
//*************************************************************************
initial begin
ram_valid_i = 1'b0;
fab_valid = 1'b0;
read_data_valid_i = 1'b0;
fab_read_data_valid_i = 1'b0;
fab_read_data_valid_i_1 = 1'b0;
USERDATA = hexstr_conv(C_DOUT_RST_VAL);
userdata_both = hexstr_conv(C_DOUT_RST_VAL);
USERSBITERR = 1'b0;
USERDBITERR = 1'b0;
user_sbiterr_both = 1'b0;
user_dbiterr_both = 1'b0;
end //initial
//***************************************************************************
// connect up optional reset
//***************************************************************************
assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0;
assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_RD_RST : C_HAS_SRST ? SRST : 0;
reg sckt_rd_rst_fwft = 1'b0;
reg fwft_rst_done_i = 1'b0;
wire fwft_rst_done;
assign fwft_rst_done = C_EN_SAFETY_CKT ? fwft_rst_done_i : 1'b1;
always @ (posedge RD_CLK) begin
sckt_rd_rst_fwft <= #`TCQ SAFETY_CKT_RD_RST;
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i)
fwft_rst_done_i <= 1'b0;
else if (sckt_rd_rst_fwft & ~SAFETY_CKT_RD_RST)
fwft_rst_done_i <= #`TCQ 1'b1;
end
localparam INVALID = 0;
localparam STAGE1_VALID = 2;
localparam STAGE2_VALID = 1;
localparam BOTH_STAGES_VALID = 3;
reg [1:0] curr_fwft_state = INVALID;
reg [1:0] next_fwft_state = INVALID;
generate if (C_USE_EMBEDDED_REG < 3 && C_FIFO_TYPE != 2) begin
always @* begin
case (curr_fwft_state)
INVALID: begin
if (~FIFOEMPTY)
next_fwft_state <= STAGE1_VALID;
else
next_fwft_state <= INVALID;
end
STAGE1_VALID: begin
if (FIFOEMPTY)
next_fwft_state <= STAGE2_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
STAGE2_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= INVALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE1_VALID;
else if (~FIFOEMPTY && ~RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= STAGE2_VALID;
end
BOTH_STAGES_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE2_VALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
default: next_fwft_state <= INVALID;
endcase
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0)
curr_fwft_state <= INVALID;
else if (srst_i)
curr_fwft_state <= #`TCQ INVALID;
else
curr_fwft_state <= #`TCQ next_fwft_state;
end
always @* begin
case (curr_fwft_state)
INVALID: STAGE2_REG_EN <= 1'b0;
STAGE1_VALID: STAGE2_REG_EN <= 1'b1;
STAGE2_VALID: STAGE2_REG_EN <= 1'b0;
BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;
default: STAGE2_REG_EN <= 1'b0;
endcase
end
assign VALID_STAGES = curr_fwft_state;
//***************************************************************************
// preloadstage2 indicates that stage2 needs to be updated. This is true
// whenever read_data_valid is false, and RAM_valid is true.
//***************************************************************************
assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );
//***************************************************************************
// preloadstage1 indicates that stage1 needs to be updated. This is true
// whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is
// false (indicating that Stage1 needs updating), or preloadstage2 is active
// (indicating that Stage2 is going to update, so Stage1, therefore, must
// also be updated to keep it valid.
//***************************************************************************
assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);
//***************************************************************************
// Calculate RAM_REGOUT_EN
// The output registers are controlled by the ram_regout_en signal.
// These registers should be updated either when the output in Stage2 is
// invalid (preloadstage2), OR when the user is reading, in which case the
// Stage2 value will go invalid unless it is replenished.
//***************************************************************************
assign ram_regout_en = preloadstage2;
//***************************************************************************
// Calculate RAM_RD_EN
// RAM_RD_EN will be asserted whenever the RAM needs to be read in order to
// update the value in Stage1.
// One case when this happens is when preloadstage1=true, which indicates
// that the data in Stage1 or Stage2 is invalid, and needs to automatically
// be updated.
// The other case is when the user is reading from the FIFO, which
// guarantees that Stage1 or Stage2 will be invalid on the next clock
// cycle, unless it is replinished by data from the memory. So, as long
// as the RAM has data in it, a read of the RAM should occur.
//***************************************************************************
assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1;
end
endgenerate // gnll_fifo
reg curr_state = 0;
reg next_state = 0;
reg leaving_empty_fwft = 0;
reg going_empty_fwft = 0;
reg empty_i_q = 0;
reg ram_rd_en_fwft = 0;
generate if (C_FIFO_TYPE == 2) begin : gll_fifo
always @* begin // FSM fo FWFT
case (curr_state)
1'b0: begin
if (~FIFOEMPTY)
next_state <= 1'b1;
else
next_state <= 1'b0;
end
1'b1: begin
if (FIFOEMPTY && RD_EN)
next_state <= 1'b0;
else
next_state <= 1'b1;
end
default: next_state <= 1'b0;
endcase
end
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
empty_i <= 1'b1;
empty_i_q <= 1'b1;
ram_valid_i <= 1'b0;
end else if (srst_i) begin
empty_i <= #`TCQ 1'b1;
empty_i_q <= #`TCQ 1'b1;
ram_valid_i <= #`TCQ 1'b0;
end else begin
empty_i <= #`TCQ going_empty_fwft | (~leaving_empty_fwft & empty_i);
empty_i_q <= #`TCQ FIFOEMPTY;
ram_valid_i <= #`TCQ next_state;
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin
curr_state <= 1'b0;
end else if (srst_i) begin
curr_state <= #`TCQ 1'b0;
end else begin
curr_state <= #`TCQ next_state;
end
end //always
wire fe_of_empty;
assign fe_of_empty = empty_i_q & ~FIFOEMPTY;
always @* begin // Finding leaving empty
case (curr_state)
1'b0: leaving_empty_fwft <= fe_of_empty;
1'b1: leaving_empty_fwft <= 1'b1;
default: leaving_empty_fwft <= 1'b0;
endcase
end
always @* begin // Finding going empty
case (curr_state)
1'b1: going_empty_fwft <= FIFOEMPTY & RD_EN;
default: going_empty_fwft <= 1'b0;
endcase
end
always @* begin // Generating FWFT rd_en
case (curr_state)
1'b0: ram_rd_en_fwft <= ~FIFOEMPTY;
1'b1: ram_rd_en_fwft <= ~FIFOEMPTY & RD_EN;
default: ram_rd_en_fwft <= 1'b0;
endcase
end
assign ram_regout_en = ram_rd_en_fwft;
//assign ram_regout_en_d1 = ram_rd_en_fwft;
//assign ram_regout_en_d2 = ram_rd_en_fwft;
assign ram_rd_en = ram_rd_en_fwft;
end endgenerate // gll_fifo
//***************************************************************************
// Calculate RAMVALID_P0_OUT
// RAMVALID_P0_OUT indicates that the data in Stage1 is valid.
//
// If the RAM is being read from on this clock cycle (ram_rd_en=1), then
// RAMVALID_P0_OUT is certainly going to be true.
// If the RAM is not being read from, but the output registers are being
// updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,
// therefore causing RAMVALID_P0_OUT to be false.
// Otherwise, RAMVALID_P0_OUT will remain unchanged.
//***************************************************************************
// PROCESS regout_valid
generate if (C_FIFO_TYPE < 2) begin : gnll_fifo_ram_valid
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
ram_valid_i <= #`TCQ 1'b0;
end else begin
if (srst_i) begin
// synchronous reset (active high)
ram_valid_i <= #`TCQ 1'b0;
end else begin
if (ram_rd_en == 1'b1) begin
ram_valid_i <= #`TCQ 1'b1;
end else begin
if (ram_regout_en == 1'b1)
ram_valid_i <= #`TCQ 1'b0;
else
ram_valid_i <= #`TCQ ram_valid_i;
end
end //srst_i
end //rd_rst_i
end //always
end endgenerate // gnll_fifo_ram_valid
//***************************************************************************
// Calculate READ_DATA_VALID
// READ_DATA_VALID indicates whether the value in Stage2 is valid or not.
// Stage2 has valid data whenever Stage1 had valid data and
// ram_regout_en_i=1, such that the data in Stage1 is propogated
// into Stage2.
//***************************************************************************
generate if(C_USE_EMBEDDED_REG < 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
read_data_valid_i <= #`TCQ 1'b0;
else
read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN);
end //always
end
endgenerate
//**************************************************************************
// Calculate EMPTY
// Defined as the inverse of READ_DATA_VALID
//
// Description:
//
// If read_data_valid_i indicates that the output is not valid,
// and there is no valid data on the output of the ram to preload it
// with, then we will report empty.
//
// If there is no valid data on the output of the ram and we are
// reading, then the FIFO will go empty.
//
//**************************************************************************
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG < 3) begin : gnll_fifo_empty
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
if (srst_i) begin
// synchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
// rising clock edge
empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN);
end
end
end //always
end endgenerate // gnll_fifo_empty
// Register RD_EN from user to calculate USERUNDERFLOW.
// Register empty_i to calculate USERUNDERFLOW.
always @ (posedge RD_CLK) begin
rd_en_q <= #`TCQ RD_EN;
empty_q <= #`TCQ empty_i;
end //always
//***************************************************************************
// Calculate user_almost_empty
// user_almost_empty is defined such that, unless more words are written
// to the FIFO, the next read will cause the FIFO to go EMPTY.
//
// In most cases, whenever the output registers are updated (due to a user
// read or a preload condition), then user_almost_empty will update to
// whatever RAM_EMPTY is.
//
// The exception is when the output is valid, the user is not reading, and
// Stage1 is not empty. In this condition, Stage1 will be preloaded from the
// memory, so we need to make sure user_almost_empty deasserts properly under
// this condition.
//***************************************************************************
generate if ( C_USE_EMBEDDED_REG < 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin // asynchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin // rising clock edge
if (srst_i) begin // synchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin
if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin
almost_empty_i <= #`TCQ FIFOEMPTY;
end
almost_empty_q <= #`TCQ empty_i;
end
end
end //always
end
endgenerate
// BRAM resets synchronously
generate
if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG < 3) begin
always @ ( posedge rd_rst_i)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else if (fwft_rst_done) begin
if (ram_regout_en) begin
USERDATA <= #`TCQ FIFODATA;
USERSBITERR <= #`TCQ FIFOSBITERR;
USERDBITERR <= #`TCQ FIFODBITERR;
end
end
end
end //always
end //if
endgenerate
//safety ckt with one register
generate
if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK)
begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always @ (posedge RD_CLK)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin //asynchronous reset (active high)
//@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end
else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1) begin
// @(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else if (fwft_rst_done) begin
if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
USERDATA <= #`TCQ FIFODATA;
USERSBITERR <= #`TCQ FIFOSBITERR;
USERDBITERR <= #`TCQ FIFODBITERR;
end
end
end
end //always
end //if
endgenerate
generate if (C_USE_EMBEDDED_REG == 3 && C_FIFO_TYPE != 2) begin
always @* begin
case (curr_fwft_state)
INVALID: begin
if (~FIFOEMPTY)
next_fwft_state <= STAGE1_VALID;
else
next_fwft_state <= INVALID;
end
STAGE1_VALID: begin
if (FIFOEMPTY)
next_fwft_state <= STAGE2_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
STAGE2_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= INVALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE1_VALID;
else if (~FIFOEMPTY && ~RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= STAGE2_VALID;
end
BOTH_STAGES_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE2_VALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
default: next_fwft_state <= INVALID;
endcase
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0)
curr_fwft_state <= INVALID;
else if (srst_i)
curr_fwft_state <= #`TCQ INVALID;
else
curr_fwft_state <= #`TCQ next_fwft_state;
end
always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay
if (rd_rst_i == 1) begin
ram_regout_en_d1 <= #`TCQ 1'b0;
end
else begin
if (srst_i == 1'b1)
ram_regout_en_d1 <= #`TCQ 1'b0;
else
ram_regout_en_d1 <= #`TCQ ram_regout_en;
end
end //always
// assign fab_regout_en = ((ram_regout_en_d1 & ~(ram_regout_en_d2) & empty_i) | (RD_EN & !empty_i));
assign fab_regout_en = ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b0 )? 1'b1: ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1) ? RD_EN : 1'b0;
always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay1
if (rd_rst_i == 1) begin
ram_regout_en_d2 <= #`TCQ 1'b0;
end
else begin
if (srst_i == 1'b1)
ram_regout_en_d2 <= #`TCQ 1'b0;
else
ram_regout_en_d2 <= #`TCQ ram_regout_en_d1;
end
end //always
always @* begin
case (curr_fwft_state)
INVALID: STAGE2_REG_EN <= 1'b0;
STAGE1_VALID: STAGE2_REG_EN <= 1'b1;
STAGE2_VALID: STAGE2_REG_EN <= 1'b0;
BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;
default: STAGE2_REG_EN <= 1'b0;
endcase
end
always @ (posedge RD_CLK) begin
ram_valid_i_d <= #`TCQ ram_valid_i;
read_data_valid_i_d <= #`TCQ read_data_valid_i;
fab_read_data_valid_i_d <= #`TCQ fab_read_data_valid_i;
end
assign VALID_STAGES = curr_fwft_state;
//***************************************************************************
// preloadstage2 indicates that stage2 needs to be updated. This is true
// whenever read_data_valid is false, and RAM_valid is true.
//***************************************************************************
assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );
//***************************************************************************
// preloadstage1 indicates that stage1 needs to be updated. This is true
// whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is
// false (indicating that Stage1 needs updating), or preloadstage2 is active
// (indicating that Stage2 is going to update, so Stage1, therefore, must
// also be updated to keep it valid.
//***************************************************************************
assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);
//***************************************************************************
// Calculate RAM_REGOUT_EN
// The output registers are controlled by the ram_regout_en signal.
// These registers should be updated either when the output in Stage2 is
// invalid (preloadstage2), OR when the user is reading, in which case the
// Stage2 value will go invalid unless it is replenished.
//***************************************************************************
assign ram_regout_en = (ram_valid_i == 1'b1 && (read_data_valid_i == 1'b0 || fab_read_data_valid_i == 1'b0)) ? 1'b1 : (read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1 && ram_valid_i == 1'b1) ? RD_EN : 1'b0;
//***************************************************************************
// Calculate RAM_RD_EN
// RAM_RD_EN will be asserted whenever the RAM needs to be read in order to
// update the value in Stage1.
// One case when this happens is when preloadstage1=true, which indicates
// that the data in Stage1 or Stage2 is invalid, and needs to automatically
// be updated.
// The other case is when the user is reading from the FIFO, which
// guarantees that Stage1 or Stage2 will be invalid on the next clock
// cycle, unless it is replinished by data from the memory. So, as long
// as the RAM has data in it, a read of the RAM should occur.
//***************************************************************************
assign ram_rd_en = ((RD_EN | ~ fab_read_data_valid_i) & ~FIFOEMPTY) | preloadstage1;
end
endgenerate // gnll_fifo
//***************************************************************************
// Calculate RAMVALID_P0_OUT
// RAMVALID_P0_OUT indicates that the data in Stage1 is valid.
//
// If the RAM is being read from on this clock cycle (ram_rd_en=1), then
// RAMVALID_P0_OUT is certainly going to be true.
// If the RAM is not being read from, but the output registers are being
// updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,
// therefore causing RAMVALID_P0_OUT to be false // Otherwise, RAMVALID_P0_OUT will remain unchanged.
//***************************************************************************
// PROCESS regout_valid
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3) begin : gnll_fifo_fab_valid
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
fab_valid <= #`TCQ 1'b0;
end else begin
if (srst_i) begin
// synchronous reset (active high)
fab_valid <= #`TCQ 1'b0;
end else begin
if (ram_regout_en == 1'b1) begin
fab_valid <= #`TCQ 1'b1;
end else begin
if (fab_regout_en == 1'b1)
fab_valid <= #`TCQ 1'b0;
else
fab_valid <= #`TCQ fab_valid;
end
end //srst_i
end //rd_rst_i
end //always
end endgenerate // gnll_fifo_fab_valid
//***************************************************************************
// Calculate READ_DATA_VALID
// READ_DATA_VALID indicates whether the value in Stage2 is valid or not.
// Stage2 has valid data whenever Stage1 had valid data and
// ram_regout_en_i=1, such that the data in Stage1 is propogated
// into Stage2.
//***************************************************************************
generate if(C_USE_EMBEDDED_REG == 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
read_data_valid_i <= #`TCQ 1'b0;
else begin
if (ram_regout_en == 1'b1) begin
read_data_valid_i <= #`TCQ 1'b1;
end else begin
if (fab_regout_en == 1'b1)
read_data_valid_i <= #`TCQ 1'b0;
else
read_data_valid_i <= #`TCQ read_data_valid_i;
end
end
end //always
end
endgenerate
//generate if(C_USE_EMBEDDED_REG == 3) begin
// always @ (posedge RD_CLK or posedge rd_rst_i) begin
// if (rd_rst_i)
// read_data_valid_i <= #`TCQ 1'b0;
// else if (srst_i)
// read_data_valid_i <= #`TCQ 1'b0;
//
// if (ram_regout_en == 1'b1) begin
// fab_read_data_valid_i <= #`TCQ 1'b0;
// end else begin
// if (fab_regout_en == 1'b1)
// fab_read_data_valid_i <= #`TCQ 1'b1;
// else
// fab_read_data_valid_i <= #`TCQ fab_read_data_valid_i;
// end
// end //always
//end
//endgenerate
generate if(C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin :fabout_dvalid
if (rd_rst_i)
fab_read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
fab_read_data_valid_i <= #`TCQ 1'b0;
else
fab_read_data_valid_i <= #`TCQ fab_valid | (fab_read_data_valid_i & ~RD_EN);
end //always
end
endgenerate
always @ (posedge RD_CLK ) begin : proc_del1
begin
fab_read_data_valid_i_1 <= #`TCQ fab_read_data_valid_i;
end
end //always
//**************************************************************************
// Calculate EMPTY
// Defined as the inverse of READ_DATA_VALID
//
// Description:
//
// If read_data_valid_i indicates that the output is not valid,
// and there is no valid data on the output of the ram to preload it
// with, then we will report empty.
//
// If there is no valid data on the output of the ram and we are
// reading, then the FIFO will go empty.
//
//**************************************************************************
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3 ) begin : gnll_fifo_empty_both
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
if (srst_i) begin
// synchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
// rising clock edge
empty_i <= #`TCQ (~fab_valid & ~fab_read_data_valid_i) | (~fab_valid & RD_EN);
end
end
end //always
end endgenerate // gnll_fifo_empty_both
// Register RD_EN from user to calculate USERUNDERFLOW.
// Register empty_i to calculate USERUNDERFLOW.
always @ (posedge RD_CLK) begin
rd_en_q <= #`TCQ RD_EN;
empty_q <= #`TCQ empty_i;
end //always
//***************************************************************************
// Calculate user_almost_empty
// user_almost_empty is defined such that, unless more words are written
// to the FIFO, the next read will cause the FIFO to go EMPTY.
//
// In most cases, whenever the output registers are updated (due to a user
// read or a preload condition), then user_almost_empty will update to
// whatever RAM_EMPTY is.
//
// The exception is when the output is valid, the user is not reading, and
// Stage1 is not empty. In this condition, Stage1 will be preloaded from the
// memory, so we need to make sure user_almost_empty deasserts properly under
// this condition.
//***************************************************************************
reg FIFOEMPTY_1;
generate if (C_USE_EMBEDDED_REG == 3 ) begin
always @(posedge RD_CLK) begin
FIFOEMPTY_1 <= #`TCQ FIFOEMPTY;
end
end
endgenerate
generate if (C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin // asynchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin // rising clock edge
if (srst_i) begin // synchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin
if ((fab_regout_en) | (ram_valid_i & fab_read_data_valid_i & ~RD_EN)) begin
almost_empty_i <= #`TCQ (~ram_valid_i);
end
almost_empty_q <= #`TCQ empty_i;
end
end
end //always
end
endgenerate
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
empty_sckt <= #`TCQ 1'b1;
sckt_rrst_q <= #`TCQ 1'b0;
sckt_rrst_done <= #`TCQ 1'b0;
end else begin
sckt_rrst_q <= #`TCQ SAFETY_CKT_RD_RST;
if (sckt_rrst_q && ~SAFETY_CKT_RD_RST) begin
sckt_rrst_done <= #`TCQ 1'b1;
end else if (sckt_rrst_done) begin
// rising clock edge
empty_sckt <= #`TCQ 1'b0;
end
end
end //always
// assign USEREMPTY = C_EN_SAFETY_CKT ? (sckt_rrst_done ? empty_i : empty_sckt) : empty_i;
assign USEREMPTY = empty_i;
assign USERALMOSTEMPTY = almost_empty_i;
assign FIFORDEN = ram_rd_en;
assign RAMVALID = (C_USE_EMBEDDED_REG == 3)? fab_valid : ram_valid_i;
assign uservalid_both = (C_USERVALID_LOW && C_USE_EMBEDDED_REG == 3) ? ~fab_read_data_valid_i : ((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG == 3) ? fab_read_data_valid_i : 1'b0);
assign uservalid_one = (C_USERVALID_LOW && C_USE_EMBEDDED_REG < 3) ? ~read_data_valid_i :((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG < 3) ? read_data_valid_i : 1'b0);
assign USERVALID = (C_USE_EMBEDDED_REG == 3) ? uservalid_both : uservalid_one;
assign USERUNDERFLOW = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q;
//no safety ckt with both reg
generate
if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end else begin
if (fwft_rst_done) begin
if (ram_regout_en) begin
userdata_both <= #`TCQ FIFODATA;
user_dbiterr_both <= #`TCQ FIFODBITERR;
user_sbiterr_both <= #`TCQ FIFOSBITERR;
end
if (fab_regout_en) begin
USERDATA <= #`TCQ userdata_both;
USERDBITERR <= #`TCQ user_dbiterr_both;
USERSBITERR <= #`TCQ user_sbiterr_both;
end
end
end
end
end //always
end //if
endgenerate
//safety_ckt with both registers
generate
if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK) begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always @ (posedge RD_CLK) begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else if (fwft_rst_done) begin
if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
userdata_both <= #`TCQ FIFODATA;
user_dbiterr_both <= #`TCQ FIFODBITERR;
user_sbiterr_both <= #`TCQ FIFOSBITERR;
end
if (fab_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
USERDATA <= #`TCQ userdata_both;
USERDBITERR <= #`TCQ user_dbiterr_both;
USERSBITERR <= #`TCQ user_sbiterr_both;
end
end
end
end //always
end //if
endgenerate
endmodule //fifo_generator_v13_1_3_bhv_ver_preload0
//-----------------------------------------------------------------------------
//
// Register Slice
// Register one AXI channel on forward and/or reverse signal path
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// reg_slice
//
//--------------------------------------------------------------------------
module fifo_generator_v13_1_3_axic_reg_slice #
(
parameter C_FAMILY = "virtex7",
parameter C_DATA_WIDTH = 32,
parameter C_REG_CONFIG = 32'h00000000
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave side
input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
input wire S_VALID,
output wire S_READY,
// Master side
output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,
output wire M_VALID,
input wire M_READY
);
generate
////////////////////////////////////////////////////////////////////
//
// Both FWD and REV mode
//
////////////////////////////////////////////////////////////////////
if (C_REG_CONFIG == 32'h00000000)
begin
reg [1:0] state;
localparam [1:0]
ZERO = 2'b10,
ONE = 2'b11,
TWO = 2'b01;
reg [C_DATA_WIDTH-1:0] storage_data1 = 0;
reg [C_DATA_WIDTH-1:0] storage_data2 = 0;
reg load_s1;
wire load_s2;
wire load_s1_from_s2;
reg s_ready_i; //local signal of output
wire m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg areset_d1; // Reset delay register
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
// Load storage1 with either slave side data or from storage2
always @(posedge ACLK)
begin
if (load_s1)
if (load_s1_from_s2)
storage_data1 <= storage_data2;
else
storage_data1 <= S_PAYLOAD_DATA;
end
// Load storage2 with slave side data
always @(posedge ACLK)
begin
if (load_s2)
storage_data2 <= S_PAYLOAD_DATA;
end
assign M_PAYLOAD_DATA = storage_data1;
// Always load s2 on a valid transaction even if it's unnecessary
assign load_s2 = S_VALID & s_ready_i;
// Loading s1
always @ *
begin
if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction
// Load when ONE if we both have read and write at the same time
((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||
// Load when TWO and we have a transaction on Master side
((state == TWO) && (M_READY == 1)))
load_s1 = 1'b1;
else
load_s1 = 1'b0;
end // always @ *
assign load_s1_from_s2 = (state == TWO);
// State Machine for handling output signals
always @(posedge ACLK) begin
if (ARESET) begin
s_ready_i <= 1'b0;
state <= ZERO;
end else if (areset_d1) begin
s_ready_i <= 1'b1;
end else begin
case (state)
// No transaction stored locally
ZERO: if (S_VALID) state <= ONE; // Got one so move to ONE
// One transaction stored locally
ONE: begin
if (M_READY & ~S_VALID) state <= ZERO; // Read out one so move to ZERO
if (~M_READY & S_VALID) begin
state <= TWO; // Got another one so move to TWO
s_ready_i <= 1'b0;
end
end
// TWO transaction stored locally
TWO: if (M_READY) begin
state <= ONE; // Read out one so move to ONE
s_ready_i <= 1'b1;
end
endcase // case (state)
end
end // always @ (posedge ACLK)
assign m_valid_i = state[0];
end // if (C_REG_CONFIG == 1)
////////////////////////////////////////////////////////////////////
//
// 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
// Operates same as 1-deep FIFO
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000001)
begin
reg [C_DATA_WIDTH-1:0] storage_data1 = 0;
reg s_ready_i; //local signal of output
reg m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg areset_d1; // Reset delay register
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
// Load storage1 with slave side data
always @(posedge ACLK)
begin
if (ARESET) begin
s_ready_i <= 1'b0;
m_valid_i <= 1'b0;
end else if (areset_d1) begin
s_ready_i <= 1'b1;
end else if (m_valid_i & M_READY) begin
s_ready_i <= 1'b1;
m_valid_i <= 1'b0;
end else if (S_VALID & s_ready_i) begin
s_ready_i <= 1'b0;
m_valid_i <= 1'b1;
end
if (~m_valid_i) begin
storage_data1 <= S_PAYLOAD_DATA;
end
end
assign M_PAYLOAD_DATA = storage_data1;
end // if (C_REG_CONFIG == 7)
else begin : default_case
// Passthrough
assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
assign M_VALID = S_VALID;
assign S_READY = M_READY;
end
endgenerate
endmodule // reg_slice
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: sfifo_112x256_la.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 173 11/01/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module sfifo_112x256_la (
aclr,
clock,
data,
rdreq,
wrreq,
almost_full,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [111:0] data;
input rdreq;
input wrreq;
output almost_full;
output empty;
output full;
output [111:0] q;
output [7:0] usedw;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "192"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "112"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "112"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
// Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "192"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "112"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL "almost_full"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 112 0 INPUT NODEFVAL "data[111..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 112 0 OUTPUT NODEFVAL "q[111..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: usedw 0 0 8 0 OUTPUT NODEFVAL "usedw[7..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 112 0 data 0 0 112 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 112 0 @q 0 0 112 0
// Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_112x256_la.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_112x256_la.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_112x256_la.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_112x256_la.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_112x256_la_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_112x256_la_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/12.1sp1/ip/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_clock_crosser.v $
// $Revision: #1 $
// $Date: 2012/10/10 $
// $Author: swbranch $
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_clock_crosser(
in_clk,
in_reset,
in_ready,
in_valid,
in_data,
out_clk,
out_reset,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter FORWARD_SYNC_DEPTH = 2;
parameter BACKWARD_SYNC_DEPTH = 2;
parameter USE_OUTPUT_PIPELINE = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input in_clk;
input in_reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_clk;
input out_reset;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
// Data is guaranteed valid by control signal clock crossing. Cut data
// buffer false path.
(* altera_attribute = {"-name SUPPRESS_DA_RULE_INTERNAL \"D101,D102\" ; -name SDC_STATEMENT \"set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]\""} *) reg [DATA_WIDTH-1:0] in_data_buffer;
reg [DATA_WIDTH-1:0] out_data_buffer;
reg in_data_toggle;
wire in_data_toggle_returned;
wire out_data_toggle;
reg out_data_toggle_flopped;
wire take_in_data;
wire out_data_taken;
wire out_valid_internal;
wire out_ready_internal;
assign in_ready = ~(in_data_toggle_returned ^ in_data_toggle);
assign take_in_data = in_valid & in_ready;
assign out_valid_internal = out_data_toggle ^ out_data_toggle_flopped;
assign out_data_taken = out_ready_internal & out_valid_internal;
always @(posedge in_clk or posedge in_reset) begin
if (in_reset) begin
in_data_buffer <= 'b0;
in_data_toggle <= 1'b0;
end else begin
if (take_in_data) begin
in_data_toggle <= ~in_data_toggle;
in_data_buffer <= in_data;
end
end //in_reset
end //in_clk always block
always @(posedge out_clk or posedge out_reset) begin
if (out_reset) begin
out_data_toggle_flopped <= 1'b0;
out_data_buffer <= 'b0;
end else begin
out_data_buffer <= in_data_buffer;
if (out_data_taken) begin
out_data_toggle_flopped <= out_data_toggle;
end
end //end if
end //out_clk always block
altera_std_synchronizer #(.depth(FORWARD_SYNC_DEPTH)) in_to_out_synchronizer (
.clk(out_clk),
.reset_n(~out_reset),
.din(in_data_toggle),
.dout(out_data_toggle)
);
altera_std_synchronizer #(.depth(BACKWARD_SYNC_DEPTH)) out_to_in_synchronizer (
.clk(in_clk),
.reset_n(~in_reset),
.din(out_data_toggle_flopped),
.dout(in_data_toggle_returned)
);
generate if (USE_OUTPUT_PIPELINE == 1) begin
altera_avalon_st_pipeline_base
#(
.BITS_PER_SYMBOL(BITS_PER_SYMBOL),
.SYMBOLS_PER_BEAT(SYMBOLS_PER_BEAT)
) output_stage (
.clk(out_clk),
.reset(out_reset),
.in_ready(out_ready_internal),
.in_valid(out_valid_internal),
.in_data(out_data_buffer),
.out_ready(out_ready),
.out_valid(out_valid),
.out_data(out_data)
);
end else begin
assign out_valid = out_valid_internal;
assign out_ready_internal = out_ready;
assign out_data = out_data_buffer;
end
endgenerate
endmodule
|
/*
* FM0 Encoder
*
* By our algorithm, FM0 Encoder can operate in the lowest frequency
*
* The common way to encode FM0 is using clock in double BLF to determine the output sigal of each period
* Our Algorithm does not use the double-BLF clock, it only needs the clock in BLF
*
* The same concept is applied to design Miller Encoder
* The lowest operation frequency makes the Encoding save power dissipation
*
* If enable FM0 Encoder, disable Miller Encoder and vice versa
*/
`timescale 1us / 1ns
module fm0_enc
(
output fm0_data,
output fm0_complete,
input clk_fm0,
input rst_for_new_package,
input send_data,
input en_fm0,
input trext,
input st_enc,
input fg_complete
);
parameter GetData = 3'b000;
parameter Data0p = 3'b001;
parameter Data0n = 3'b010;
parameter Data1p = 3'b011;
parameter Data1n = 3'b100;
reg [2:0]ps; // present state
reg [2:0]ns; // next state
wire clk_fm0_n;
wire en_vcnt; // enable V counter
wire start_enc; // start FM0 encoding
wire send_v; // send V
wire m2o; // output of MUX 2
reg [1:0]data_select;
reg m1o; // output of MUX 1
reg [4:0]v_cnt; // V coumter
reg [1:0]fg_comp_cnt;
assign clk_fm0_n = ~clk_fm0;
assign start_enc = (ps != GetData)? 1'b1 : 1'b0;
assign en_vcnt = (start_enc & (v_cnt != 5'h11))? 1'b1 : 1'b0;
assign send_v = (~trext & (v_cnt == 5'h04))? 1'b1 :
(trext & (v_cnt == 5'h10))? 1'b1 : 1'b0;
assign m2o = send_v? 1'b0 : m1o;
assign fm0_data = (en_fm0 & ~fm0_complete)? m2o : 1'b0;
always@(posedge clk_fm0 or negedge rst_for_new_package) begin
if(~rst_for_new_package) ps <= GetData;
else if(st_enc) ps <= ns;
end
always@(*) begin
case(ps)
GetData : if(~en_fm0) ns = GetData;
else if(en_fm0 & (~send_data)) ns = Data0p;
else ns = Data1p;
Data0p : if(~send_data) ns = Data0p;
else ns = Data1p;
Data0n : if(~send_data) ns = Data0n;
else ns = Data1n;
Data1p : if(~send_data) ns = Data0n;
else ns = Data1n;
Data1n : if(~send_data) ns = Data0p;
else ns = Data1p;
default : ns = GetData;
endcase
end
always@(*) begin
case(ps)
GetData : data_select = 2'h0;
Data0p : data_select = 2'h3;
Data0n : data_select = 2'h2;
Data1p : data_select = 2'h1;
Data1n : data_select = 2'h0;
default : data_select = 2'h0;
endcase
end
always@(*) begin
case(data_select)
2'h0 : m1o = 1'b0;
2'h1 : m1o = 1'b1;
2'h2 : m1o = clk_fm0_n;
2'h3 : m1o = clk_fm0;
endcase
end
always@(posedge clk_fm0 or negedge rst_for_new_package) begin
if(~rst_for_new_package) v_cnt <= 5'h00;
else begin
if(st_enc & en_vcnt) v_cnt <= v_cnt + 5'h01;
end
end
always@(posedge clk_fm0 or negedge rst_for_new_package) begin
if(~rst_for_new_package) fg_comp_cnt <= 2'b0;
else begin
if(fg_comp_cnt == 2'b10) fg_comp_cnt <= fg_comp_cnt;
else if(en_fm0 & fg_complete) fg_comp_cnt <= fg_comp_cnt + 2'b1;
end
end
assign fm0_complete = (fg_comp_cnt == 2'b10)? 1'b1 : 1'b0;
endmodule
|
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: driver_7segment.v
//
// *Module Description:
// Driver for the four-digit, seven-segment LED display.
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 23 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
//----------------------------------------------------------------------------
module driver_7segment (
// OUTPUTs
per_dout, // Peripheral data output
hex0, // outputs to the segments
hex1,
hex2,
hex3,
// INPUTs
mclk, // Main system clock
per_addr, // Peripheral address
per_din, // Peripheral data input
per_en, // Peripheral enable (high active)
per_we, // Peripheral write enable (high active)
puc_rst // Main system reset
);
// OUTPUTs
//=========
output [15:0] per_dout; // Peripheral data output
output [7:0] hex0,hex1,hex2,hex3;
// INPUTs
//=========
input mclk; // Main system clock
input [13:0] per_addr; // Peripheral address
input [15:0] per_din; // Peripheral data input
input per_en; // Peripheral enable (high active)
input [1:0] per_we; // Peripheral write enable (high active)
input puc_rst; // Main system reset
//=============================================================================
// 1) PARAMETER DECLARATION
//=============================================================================
// Register base address (must be aligned to decoder bit width)
parameter [14:0] BASE_ADDR = 15'h0090;
// Decoder bit width (defines how many bits are considered for address decoding)
parameter DEC_WD = 2;
// Register addresses offset
parameter [DEC_WD-1:0] DIGIT0 = 'h0,
DIGIT1 = 'h1,
DIGIT2 = 'h2,
DIGIT3 = 'h3;
// Register one-hot decoder utilities
parameter DEC_SZ = 2**DEC_WD;
parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1};
// Register one-hot decoder
parameter [DEC_SZ-1:0] DIGIT0_D = (BASE_REG << DIGIT0),
DIGIT1_D = (BASE_REG << DIGIT1),
DIGIT2_D = (BASE_REG << DIGIT2),
DIGIT3_D = (BASE_REG << DIGIT3);
//============================================================================
// 2) REGISTER DECODER
//============================================================================
// Local register selection
wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);
// Register local address
wire [DEC_WD-1:0] reg_addr = {1'b0, per_addr[DEC_WD-2:0]};
// Register address decode
wire [DEC_SZ-1:0] reg_dec = (DIGIT0_D & {DEC_SZ{(reg_addr==(DIGIT0 >>1))}}) |
(DIGIT1_D & {DEC_SZ{(reg_addr==(DIGIT1 >>1))}}) |
(DIGIT2_D & {DEC_SZ{(reg_addr==(DIGIT2 >>1))}}) |
(DIGIT3_D & {DEC_SZ{(reg_addr==(DIGIT3 >>1))}});
// Read/Write probes
wire reg_lo_write = per_we[0] & reg_sel;
wire reg_hi_write = per_we[1] & reg_sel;
wire reg_read = ~|per_we & reg_sel;
// Read/Write vectors
wire [DEC_SZ-1:0] reg_hi_wr = reg_dec & {DEC_SZ{reg_hi_write}};
wire [DEC_SZ-1:0] reg_lo_wr = reg_dec & {DEC_SZ{reg_lo_write}};
wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}};
//============================================================================
// 3) REGISTERS
//============================================================================
// DIGIT0 Register
//-----------------
reg [7:0] digit0;
wire digit0_wr = DIGIT0[0] ? reg_hi_wr[DIGIT0] : reg_lo_wr[DIGIT0];
wire [7:0] digit0_nxt = DIGIT0[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) digit0 <= 8'h00;
else if (digit0_wr) digit0 <= digit0_nxt;
// DIGIT1 Register
//-----------------
reg [7:0] digit1;
wire digit1_wr = DIGIT1[0] ? reg_hi_wr[DIGIT1] : reg_lo_wr[DIGIT1];
wire [7:0] digit1_nxt = DIGIT1[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) digit1 <= 8'h00;
else if (digit1_wr) digit1 <= digit1_nxt;
// DIGIT2 Register
//-----------------
reg [7:0] digit2;
wire digit2_wr = DIGIT2[0] ? reg_hi_wr[DIGIT2] : reg_lo_wr[DIGIT2];
wire [7:0] digit2_nxt = DIGIT2[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) digit2 <= 8'h00;
else if (digit2_wr) digit2 <= digit2_nxt;
// DIGIT3 Register
//-----------------
reg [7:0] digit3;
wire digit3_wr = DIGIT3[0] ? reg_hi_wr[DIGIT3] : reg_lo_wr[DIGIT3];
wire [7:0] digit3_nxt = DIGIT3[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) digit3 <= 8'h00;
else if (digit3_wr) digit3 <= digit3_nxt;
//============================================================================
// 4) DATA OUTPUT GENERATION
//============================================================================
// Data output mux
wire [15:0] digit0_rd = (digit0 & {8{reg_rd[DIGIT0]}}) << (8 & {4{DIGIT0[0]}});
wire [15:0] digit1_rd = (digit1 & {8{reg_rd[DIGIT1]}}) << (8 & {4{DIGIT1[0]}});
wire [15:0] digit2_rd = (digit2 & {8{reg_rd[DIGIT2]}}) << (8 & {4{DIGIT2[0]}});
wire [15:0] digit3_rd = (digit3 & {8{reg_rd[DIGIT3]}}) << (8 & {4{DIGIT3[0]}});
wire [15:0] per_dout = digit0_rd |
digit1_rd |
digit2_rd |
digit3_rd;
//============================================================================
// 5) FOUR-DIGIT, SEVEN-SEGMENT LED DISPLAY DRIVER
//============================================================================
// Segment selection
//----------------------------
//////
//////
////// changed by Vadim Akimov, [email protected]
////// because altera DE1 has non-multiplexed 7seg display
bit_reverse revhex0 ( .in(~digit0), .out(hex0) );
bit_reverse revhex1 ( .in(~digit1), .out(hex1) );
bit_reverse revhex2 ( .in(~digit2), .out(hex2) );
bit_reverse revhex3 ( .in(~digit3), .out(hex3) );
endmodule // driver_7segment
module bit_reverse(
input [7:0] in,
output [7:0] out
);
assign out[7:0] = { in[0],in[1],in[2],in[3],in[4],in[5],in[6],in[7] };
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.3 (lin64) Build 1034051 Fri Oct 3 16:31:15 MDT 2014
// Date : Sun Oct 25 15:45:18 2015
// Host : arthas-ubuntu running 64-bit Ubuntu 14.04.3 LTS
// Command : write_verilog -force -mode funcsim
// /home/arthas/git/SHD/SHD.srcs/sources_1/ip/shd_pe_fifo/shd_pe_fifo_funcsim.v
// Design : shd_pe_fifo
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7vx690tffg1761-2
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "fifo_generator_v12_0,Vivado 2014.3" *) (* CHECK_LICENSE_TYPE = "shd_pe_fifo,fifo_generator_v12_0,{}" *)
(* core_generation_info = "shd_pe_fifo,fifo_generator_v12_0,{x_ipProduct=Vivado 2014.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=2,x_ipLanguage=VERILOG,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=12,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=8,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=8,C_ENABLE_RLOCS=0,C_FAMILY=virtex7,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=4kx9,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=4095,C_PROG_FULL_THRESH_NEGATE_VAL=4094,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=12,C_RD_DEPTH=4096,C_RD_FREQ=1,C_RD_PNTR_WIDTH=12,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=12,C_WR_DEPTH=4096,C_WR_FREQ=1,C_WR_PNTR_WIDTH=12,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}" *)
(* NotValidForBitStream *)
module shd_pe_fifo
(rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty);
input rst;
input wr_clk;
input rd_clk;
input [7:0]din;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *) input wr_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *) input rd_en;
output [7:0]dout;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *) output full;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *) output empty;
wire [7:0]din;
wire [7:0]dout;
wire empty;
wire full;
wire rd_clk;
wire rd_en;
wire rst;
wire wr_clk;
wire wr_en;
wire NLW_U0_almost_empty_UNCONNECTED;
wire NLW_U0_almost_full_UNCONNECTED;
wire NLW_U0_axi_ar_dbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_overflow_UNCONNECTED;
wire NLW_U0_axi_ar_prog_empty_UNCONNECTED;
wire NLW_U0_axi_ar_prog_full_UNCONNECTED;
wire NLW_U0_axi_ar_sbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_underflow_UNCONNECTED;
wire NLW_U0_axi_aw_dbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_overflow_UNCONNECTED;
wire NLW_U0_axi_aw_prog_empty_UNCONNECTED;
wire NLW_U0_axi_aw_prog_full_UNCONNECTED;
wire NLW_U0_axi_aw_sbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_underflow_UNCONNECTED;
wire NLW_U0_axi_b_dbiterr_UNCONNECTED;
wire NLW_U0_axi_b_overflow_UNCONNECTED;
wire NLW_U0_axi_b_prog_empty_UNCONNECTED;
wire NLW_U0_axi_b_prog_full_UNCONNECTED;
wire NLW_U0_axi_b_sbiterr_UNCONNECTED;
wire NLW_U0_axi_b_underflow_UNCONNECTED;
wire NLW_U0_axi_r_dbiterr_UNCONNECTED;
wire NLW_U0_axi_r_overflow_UNCONNECTED;
wire NLW_U0_axi_r_prog_empty_UNCONNECTED;
wire NLW_U0_axi_r_prog_full_UNCONNECTED;
wire NLW_U0_axi_r_sbiterr_UNCONNECTED;
wire NLW_U0_axi_r_underflow_UNCONNECTED;
wire NLW_U0_axi_w_dbiterr_UNCONNECTED;
wire NLW_U0_axi_w_overflow_UNCONNECTED;
wire NLW_U0_axi_w_prog_empty_UNCONNECTED;
wire NLW_U0_axi_w_prog_full_UNCONNECTED;
wire NLW_U0_axi_w_sbiterr_UNCONNECTED;
wire NLW_U0_axi_w_underflow_UNCONNECTED;
wire NLW_U0_axis_dbiterr_UNCONNECTED;
wire NLW_U0_axis_overflow_UNCONNECTED;
wire NLW_U0_axis_prog_empty_UNCONNECTED;
wire NLW_U0_axis_prog_full_UNCONNECTED;
wire NLW_U0_axis_sbiterr_UNCONNECTED;
wire NLW_U0_axis_underflow_UNCONNECTED;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_m_axi_arvalid_UNCONNECTED;
wire NLW_U0_m_axi_awvalid_UNCONNECTED;
wire NLW_U0_m_axi_bready_UNCONNECTED;
wire NLW_U0_m_axi_rready_UNCONNECTED;
wire NLW_U0_m_axi_wlast_UNCONNECTED;
wire NLW_U0_m_axi_wvalid_UNCONNECTED;
wire NLW_U0_m_axis_tlast_UNCONNECTED;
wire NLW_U0_m_axis_tvalid_UNCONNECTED;
wire NLW_U0_overflow_UNCONNECTED;
wire NLW_U0_prog_empty_UNCONNECTED;
wire NLW_U0_prog_full_UNCONNECTED;
wire NLW_U0_rd_rst_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_s_axis_tready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire NLW_U0_underflow_UNCONNECTED;
wire NLW_U0_valid_UNCONNECTED;
wire NLW_U0_wr_ack_UNCONNECTED;
wire NLW_U0_wr_rst_busy_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_wr_data_count_UNCONNECTED;
wire [11:0]NLW_U0_data_count_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_araddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_arburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_arlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_aruser_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_awaddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_awburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_awlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awuser_UNCONNECTED;
wire [63:0]NLW_U0_m_axi_wdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_wstrb_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wuser_UNCONNECTED;
wire [7:0]NLW_U0_m_axis_tdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tdest_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tid_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tkeep_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tstrb_UNCONNECTED;
wire [3:0]NLW_U0_m_axis_tuser_UNCONNECTED;
wire [11:0]NLW_U0_rd_data_count_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_buser_UNCONNECTED;
wire [63:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_ruser_UNCONNECTED;
wire [11:0]NLW_U0_wr_data_count_UNCONNECTED;
(* C_ADD_NGC_CONSTRAINT = "0" *)
(* C_APPLICATION_TYPE_AXIS = "0" *)
(* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *)
(* C_APPLICATION_TYPE_WACH = "0" *)
(* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *)
(* C_AXIS_TDATA_WIDTH = "8" *)
(* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *)
(* C_AXIS_TKEEP_WIDTH = "1" *)
(* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *)
(* C_AXIS_TYPE = "0" *)
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *)
(* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_COMMON_CLOCK = "0" *)
(* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "12" *)
(* C_DEFAULT_VALUE = "BlankString" *)
(* C_DIN_WIDTH = "8" *)
(* C_DIN_WIDTH_AXIS = "1" *)
(* C_DIN_WIDTH_RACH = "32" *)
(* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "32" *)
(* C_DIN_WIDTH_WDCH = "64" *)
(* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *)
(* C_DOUT_WIDTH = "8" *)
(* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *)
(* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *)
(* C_ERROR_INJECTION_TYPE_RACH = "0" *)
(* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *)
(* C_ERROR_INJECTION_TYPE_WDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "virtex7" *)
(* C_FULL_FLAGS_RST_VAL = "1" *)
(* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *)
(* C_HAS_AXIS_TDATA = "1" *)
(* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *)
(* C_HAS_AXIS_TKEEP = "0" *)
(* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *)
(* C_HAS_AXIS_TSTRB = "0" *)
(* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *)
(* C_HAS_AXI_AWUSER = "0" *)
(* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_AXI_RD_CHANNEL = "1" *)
(* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *)
(* C_HAS_AXI_WUSER = "0" *)
(* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *)
(* C_HAS_DATA_COUNTS_AXIS = "0" *)
(* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *)
(* C_HAS_DATA_COUNTS_WACH = "0" *)
(* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *)
(* C_HAS_INT_CLK = "0" *)
(* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *)
(* C_HAS_OVERFLOW = "0" *)
(* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *)
(* C_HAS_PROG_FLAGS_RDCH = "0" *)
(* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *)
(* C_HAS_PROG_FLAGS_WRCH = "0" *)
(* C_HAS_RD_DATA_COUNT = "0" *)
(* C_HAS_RD_RST = "0" *)
(* C_HAS_RST = "1" *)
(* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "0" *)
(* C_HAS_UNDERFLOW = "0" *)
(* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *)
(* C_HAS_WR_DATA_COUNT = "0" *)
(* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "2" *)
(* C_IMPLEMENTATION_TYPE_AXIS = "1" *)
(* C_IMPLEMENTATION_TYPE_RACH = "1" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WACH = "1" *)
(* C_IMPLEMENTATION_TYPE_WDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "1" *)
(* C_INIT_WR_PNTR_VAL = "0" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_MEMORY_TYPE = "1" *)
(* C_MIF_FILE_NAME = "BlankString" *)
(* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *)
(* C_OVERFLOW_LOW = "0" *)
(* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "0" *)
(* C_PRELOAD_REGS = "1" *)
(* C_PRIM_FIFO_TYPE = "4kx9" *)
(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *)
(* C_PRIM_FIFO_TYPE_RACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "4" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *)
(* C_PROG_EMPTY_THRESH_NEGATE_VAL = "5" *)
(* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *)
(* C_PROG_EMPTY_TYPE_RACH = "0" *)
(* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *)
(* C_PROG_EMPTY_TYPE_WDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "4095" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *)
(* C_PROG_FULL_THRESH_NEGATE_VAL = "4094" *)
(* C_PROG_FULL_TYPE = "0" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *)
(* C_PROG_FULL_TYPE_RACH = "0" *)
(* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *)
(* C_PROG_FULL_TYPE_WDCH = "0" *)
(* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *)
(* C_RDCH_TYPE = "0" *)
(* C_RD_DATA_COUNT_WIDTH = "12" *)
(* C_RD_DEPTH = "4096" *)
(* C_RD_FREQ = "1" *)
(* C_RD_PNTR_WIDTH = "12" *)
(* C_REG_SLICE_MODE_AXIS = "0" *)
(* C_REG_SLICE_MODE_RACH = "0" *)
(* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *)
(* C_REG_SLICE_MODE_WDCH = "0" *)
(* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SYNCHRONIZER_STAGE = "2" *)
(* C_UNDERFLOW_LOW = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *)
(* C_USE_COMMON_UNDERFLOW = "0" *)
(* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_USE_DOUT_RST = "1" *)
(* C_USE_ECC = "0" *)
(* C_USE_ECC_AXIS = "0" *)
(* C_USE_ECC_RACH = "0" *)
(* C_USE_ECC_RDCH = "0" *)
(* C_USE_ECC_WACH = "0" *)
(* C_USE_ECC_WDCH = "0" *)
(* C_USE_ECC_WRCH = "0" *)
(* C_USE_EMBEDDED_REG = "0" *)
(* C_USE_FIFO16_FLAGS = "0" *)
(* C_USE_FWFT_DATA_COUNT = "0" *)
(* C_USE_PIPELINE_REG = "0" *)
(* C_VALID_LOW = "0" *)
(* C_WACH_TYPE = "0" *)
(* C_WDCH_TYPE = "0" *)
(* C_WRCH_TYPE = "0" *)
(* C_WR_ACK_LOW = "0" *)
(* C_WR_DATA_COUNT_WIDTH = "12" *)
(* C_WR_DEPTH = "4096" *)
(* C_WR_DEPTH_AXIS = "1024" *)
(* C_WR_DEPTH_RACH = "16" *)
(* C_WR_DEPTH_RDCH = "1024" *)
(* C_WR_DEPTH_WACH = "16" *)
(* C_WR_DEPTH_WDCH = "1024" *)
(* C_WR_DEPTH_WRCH = "16" *)
(* C_WR_FREQ = "1" *)
(* C_WR_PNTR_WIDTH = "12" *)
(* C_WR_PNTR_WIDTH_AXIS = "10" *)
(* C_WR_PNTR_WIDTH_RACH = "4" *)
(* C_WR_PNTR_WIDTH_RDCH = "10" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *)
(* C_WR_PNTR_WIDTH_WDCH = "10" *)
(* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_RESPONSE_LATENCY = "1" *)
shd_pe_fifo_fifo_generator_v12_0__parameterized0 U0
(.almost_empty(NLW_U0_almost_empty_UNCONNECTED),
.almost_full(NLW_U0_almost_full_UNCONNECTED),
.axi_ar_data_count(NLW_U0_axi_ar_data_count_UNCONNECTED[4:0]),
.axi_ar_dbiterr(NLW_U0_axi_ar_dbiterr_UNCONNECTED),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_injectsbiterr(1'b0),
.axi_ar_overflow(NLW_U0_axi_ar_overflow_UNCONNECTED),
.axi_ar_prog_empty(NLW_U0_axi_ar_prog_empty_UNCONNECTED),
.axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_prog_full(NLW_U0_axi_ar_prog_full_UNCONNECTED),
.axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_rd_data_count(NLW_U0_axi_ar_rd_data_count_UNCONNECTED[4:0]),
.axi_ar_sbiterr(NLW_U0_axi_ar_sbiterr_UNCONNECTED),
.axi_ar_underflow(NLW_U0_axi_ar_underflow_UNCONNECTED),
.axi_ar_wr_data_count(NLW_U0_axi_ar_wr_data_count_UNCONNECTED[4:0]),
.axi_aw_data_count(NLW_U0_axi_aw_data_count_UNCONNECTED[4:0]),
.axi_aw_dbiterr(NLW_U0_axi_aw_dbiterr_UNCONNECTED),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_overflow(NLW_U0_axi_aw_overflow_UNCONNECTED),
.axi_aw_prog_empty(NLW_U0_axi_aw_prog_empty_UNCONNECTED),
.axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_prog_full(NLW_U0_axi_aw_prog_full_UNCONNECTED),
.axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_rd_data_count(NLW_U0_axi_aw_rd_data_count_UNCONNECTED[4:0]),
.axi_aw_sbiterr(NLW_U0_axi_aw_sbiterr_UNCONNECTED),
.axi_aw_underflow(NLW_U0_axi_aw_underflow_UNCONNECTED),
.axi_aw_wr_data_count(NLW_U0_axi_aw_wr_data_count_UNCONNECTED[4:0]),
.axi_b_data_count(NLW_U0_axi_b_data_count_UNCONNECTED[4:0]),
.axi_b_dbiterr(NLW_U0_axi_b_dbiterr_UNCONNECTED),
.axi_b_injectdbiterr(1'b0),
.axi_b_injectsbiterr(1'b0),
.axi_b_overflow(NLW_U0_axi_b_overflow_UNCONNECTED),
.axi_b_prog_empty(NLW_U0_axi_b_prog_empty_UNCONNECTED),
.axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_prog_full(NLW_U0_axi_b_prog_full_UNCONNECTED),
.axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_rd_data_count(NLW_U0_axi_b_rd_data_count_UNCONNECTED[4:0]),
.axi_b_sbiterr(NLW_U0_axi_b_sbiterr_UNCONNECTED),
.axi_b_underflow(NLW_U0_axi_b_underflow_UNCONNECTED),
.axi_b_wr_data_count(NLW_U0_axi_b_wr_data_count_UNCONNECTED[4:0]),
.axi_r_data_count(NLW_U0_axi_r_data_count_UNCONNECTED[10:0]),
.axi_r_dbiterr(NLW_U0_axi_r_dbiterr_UNCONNECTED),
.axi_r_injectdbiterr(1'b0),
.axi_r_injectsbiterr(1'b0),
.axi_r_overflow(NLW_U0_axi_r_overflow_UNCONNECTED),
.axi_r_prog_empty(NLW_U0_axi_r_prog_empty_UNCONNECTED),
.axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_prog_full(NLW_U0_axi_r_prog_full_UNCONNECTED),
.axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_rd_data_count(NLW_U0_axi_r_rd_data_count_UNCONNECTED[10:0]),
.axi_r_sbiterr(NLW_U0_axi_r_sbiterr_UNCONNECTED),
.axi_r_underflow(NLW_U0_axi_r_underflow_UNCONNECTED),
.axi_r_wr_data_count(NLW_U0_axi_r_wr_data_count_UNCONNECTED[10:0]),
.axi_w_data_count(NLW_U0_axi_w_data_count_UNCONNECTED[10:0]),
.axi_w_dbiterr(NLW_U0_axi_w_dbiterr_UNCONNECTED),
.axi_w_injectdbiterr(1'b0),
.axi_w_injectsbiterr(1'b0),
.axi_w_overflow(NLW_U0_axi_w_overflow_UNCONNECTED),
.axi_w_prog_empty(NLW_U0_axi_w_prog_empty_UNCONNECTED),
.axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_prog_full(NLW_U0_axi_w_prog_full_UNCONNECTED),
.axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_rd_data_count(NLW_U0_axi_w_rd_data_count_UNCONNECTED[10:0]),
.axi_w_sbiterr(NLW_U0_axi_w_sbiterr_UNCONNECTED),
.axi_w_underflow(NLW_U0_axi_w_underflow_UNCONNECTED),
.axi_w_wr_data_count(NLW_U0_axi_w_wr_data_count_UNCONNECTED[10:0]),
.axis_data_count(NLW_U0_axis_data_count_UNCONNECTED[10:0]),
.axis_dbiterr(NLW_U0_axis_dbiterr_UNCONNECTED),
.axis_injectdbiterr(1'b0),
.axis_injectsbiterr(1'b0),
.axis_overflow(NLW_U0_axis_overflow_UNCONNECTED),
.axis_prog_empty(NLW_U0_axis_prog_empty_UNCONNECTED),
.axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_prog_full(NLW_U0_axis_prog_full_UNCONNECTED),
.axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_rd_data_count(NLW_U0_axis_rd_data_count_UNCONNECTED[10:0]),
.axis_sbiterr(NLW_U0_axis_sbiterr_UNCONNECTED),
.axis_underflow(NLW_U0_axis_underflow_UNCONNECTED),
.axis_wr_data_count(NLW_U0_axis_wr_data_count_UNCONNECTED[10:0]),
.backup(1'b0),
.backup_marker(1'b0),
.clk(1'b0),
.data_count(NLW_U0_data_count_UNCONNECTED[11:0]),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.int_clk(1'b0),
.m_aclk(1'b0),
.m_aclk_en(1'b0),
.m_axi_araddr(NLW_U0_m_axi_araddr_UNCONNECTED[31:0]),
.m_axi_arburst(NLW_U0_m_axi_arburst_UNCONNECTED[1:0]),
.m_axi_arcache(NLW_U0_m_axi_arcache_UNCONNECTED[3:0]),
.m_axi_arid(NLW_U0_m_axi_arid_UNCONNECTED[0]),
.m_axi_arlen(NLW_U0_m_axi_arlen_UNCONNECTED[7:0]),
.m_axi_arlock(NLW_U0_m_axi_arlock_UNCONNECTED[0]),
.m_axi_arprot(NLW_U0_m_axi_arprot_UNCONNECTED[2:0]),
.m_axi_arqos(NLW_U0_m_axi_arqos_UNCONNECTED[3:0]),
.m_axi_arready(1'b0),
.m_axi_arregion(NLW_U0_m_axi_arregion_UNCONNECTED[3:0]),
.m_axi_arsize(NLW_U0_m_axi_arsize_UNCONNECTED[2:0]),
.m_axi_aruser(NLW_U0_m_axi_aruser_UNCONNECTED[0]),
.m_axi_arvalid(NLW_U0_m_axi_arvalid_UNCONNECTED),
.m_axi_awaddr(NLW_U0_m_axi_awaddr_UNCONNECTED[31:0]),
.m_axi_awburst(NLW_U0_m_axi_awburst_UNCONNECTED[1:0]),
.m_axi_awcache(NLW_U0_m_axi_awcache_UNCONNECTED[3:0]),
.m_axi_awid(NLW_U0_m_axi_awid_UNCONNECTED[0]),
.m_axi_awlen(NLW_U0_m_axi_awlen_UNCONNECTED[7:0]),
.m_axi_awlock(NLW_U0_m_axi_awlock_UNCONNECTED[0]),
.m_axi_awprot(NLW_U0_m_axi_awprot_UNCONNECTED[2:0]),
.m_axi_awqos(NLW_U0_m_axi_awqos_UNCONNECTED[3:0]),
.m_axi_awready(1'b0),
.m_axi_awregion(NLW_U0_m_axi_awregion_UNCONNECTED[3:0]),
.m_axi_awsize(NLW_U0_m_axi_awsize_UNCONNECTED[2:0]),
.m_axi_awuser(NLW_U0_m_axi_awuser_UNCONNECTED[0]),
.m_axi_awvalid(NLW_U0_m_axi_awvalid_UNCONNECTED),
.m_axi_bid(1'b0),
.m_axi_bready(NLW_U0_m_axi_bready_UNCONNECTED),
.m_axi_bresp({1'b0,1'b0}),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_rid(1'b0),
.m_axi_rlast(1'b0),
.m_axi_rready(NLW_U0_m_axi_rready_UNCONNECTED),
.m_axi_rresp({1'b0,1'b0}),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_wdata(NLW_U0_m_axi_wdata_UNCONNECTED[63:0]),
.m_axi_wid(NLW_U0_m_axi_wid_UNCONNECTED[0]),
.m_axi_wlast(NLW_U0_m_axi_wlast_UNCONNECTED),
.m_axi_wready(1'b0),
.m_axi_wstrb(NLW_U0_m_axi_wstrb_UNCONNECTED[7:0]),
.m_axi_wuser(NLW_U0_m_axi_wuser_UNCONNECTED[0]),
.m_axi_wvalid(NLW_U0_m_axi_wvalid_UNCONNECTED),
.m_axis_tdata(NLW_U0_m_axis_tdata_UNCONNECTED[7:0]),
.m_axis_tdest(NLW_U0_m_axis_tdest_UNCONNECTED[0]),
.m_axis_tid(NLW_U0_m_axis_tid_UNCONNECTED[0]),
.m_axis_tkeep(NLW_U0_m_axis_tkeep_UNCONNECTED[0]),
.m_axis_tlast(NLW_U0_m_axis_tlast_UNCONNECTED),
.m_axis_tready(1'b0),
.m_axis_tstrb(NLW_U0_m_axis_tstrb_UNCONNECTED[0]),
.m_axis_tuser(NLW_U0_m_axis_tuser_UNCONNECTED[3:0]),
.m_axis_tvalid(NLW_U0_m_axis_tvalid_UNCONNECTED),
.overflow(NLW_U0_overflow_UNCONNECTED),
.prog_empty(NLW_U0_prog_empty_UNCONNECTED),
.prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full(NLW_U0_prog_full_UNCONNECTED),
.prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.rd_clk(rd_clk),
.rd_data_count(NLW_U0_rd_data_count_UNCONNECTED[11:0]),
.rd_en(rd_en),
.rd_rst(1'b0),
.rd_rst_busy(NLW_U0_rd_rst_busy_UNCONNECTED),
.rst(rst),
.s_aclk(1'b0),
.s_aclk_en(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arid(1'b0),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlock(1'b0),
.s_axi_arprot({1'b0,1'b0,1'b0}),
.s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awid(1'b0),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlock(1'b0),
.s_axi_awprot({1'b0,1'b0,1'b0}),
.s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_buser(NLW_U0_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[63:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_ruser(NLW_U0_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wid(1'b0),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axis_tdest(1'b0),
.s_axis_tid(1'b0),
.s_axis_tkeep(1'b0),
.s_axis_tlast(1'b0),
.s_axis_tready(NLW_U0_s_axis_tready_UNCONNECTED),
.s_axis_tstrb(1'b0),
.s_axis_tuser({1'b0,1'b0,1'b0,1'b0}),
.s_axis_tvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.sleep(1'b0),
.srst(1'b0),
.underflow(NLW_U0_underflow_UNCONNECTED),
.valid(NLW_U0_valid_UNCONNECTED),
.wr_ack(NLW_U0_wr_ack_UNCONNECTED),
.wr_clk(wr_clk),
.wr_data_count(NLW_U0_wr_data_count_UNCONNECTED[11:0]),
.wr_en(wr_en),
.wr_rst(1'b0),
.wr_rst_busy(NLW_U0_wr_rst_busy_UNCONNECTED));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module shd_pe_fifo_blk_mem_gen_generic_cstr
(D,
WEA,
wr_clk,
tmp_ram_rd_en,
rd_clk,
Q,
O1,
I1,
din);
output [7:0]D;
input [0:0]WEA;
input wr_clk;
input tmp_ram_rd_en;
input rd_clk;
input [0:0]Q;
input [11:0]O1;
input [11:0]I1;
input [7:0]din;
wire [7:0]D;
wire [11:0]I1;
wire [11:0]O1;
wire [0:0]Q;
wire [0:0]WEA;
wire [7:0]din;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
shd_pe_fifo_blk_mem_gen_prim_width \ramloop[0].ram.r
(.D(D),
.I1(I1),
.O1(O1),
.Q(Q),
.WEA(WEA),
.din(din),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module shd_pe_fifo_blk_mem_gen_prim_width
(D,
WEA,
wr_clk,
tmp_ram_rd_en,
rd_clk,
Q,
O1,
I1,
din);
output [7:0]D;
input [0:0]WEA;
input wr_clk;
input tmp_ram_rd_en;
input rd_clk;
input [0:0]Q;
input [11:0]O1;
input [11:0]I1;
input [7:0]din;
wire [7:0]D;
wire [11:0]I1;
wire [11:0]O1;
wire [0:0]Q;
wire [0:0]WEA;
wire [7:0]din;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
shd_pe_fifo_blk_mem_gen_prim_wrapper \prim_noinit.ram
(.D(D),
.I1(I1),
.O1(O1),
.Q(Q),
.WEA(WEA),
.din(din),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module shd_pe_fifo_blk_mem_gen_prim_wrapper
(D,
WEA,
wr_clk,
tmp_ram_rd_en,
rd_clk,
Q,
O1,
I1,
din);
output [7:0]D;
input [0:0]WEA;
input wr_clk;
input tmp_ram_rd_en;
input rd_clk;
input [0:0]Q;
input [11:0]O1;
input [11:0]I1;
input [7:0]din;
wire [7:0]D;
wire [11:0]I1;
wire [11:0]O1;
wire [0:0]Q;
wire [0:0]WEA;
wire [7:0]din;
wire \n_75_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,O1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,I1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(wr_clk),
.CLKBWRCLK(rd_clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],D}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\n_75_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(WEA),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(Q),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({WEA,WEA,WEA,WEA}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module shd_pe_fifo_blk_mem_gen_top
(D,
WEA,
wr_clk,
tmp_ram_rd_en,
rd_clk,
Q,
O1,
I1,
din);
output [7:0]D;
input [0:0]WEA;
input wr_clk;
input tmp_ram_rd_en;
input rd_clk;
input [0:0]Q;
input [11:0]O1;
input [11:0]I1;
input [7:0]din;
wire [7:0]D;
wire [11:0]I1;
wire [11:0]O1;
wire [0:0]Q;
wire [0:0]WEA;
wire [7:0]din;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
shd_pe_fifo_blk_mem_gen_generic_cstr \valid.cstr
(.D(D),
.I1(I1),
.O1(O1),
.Q(Q),
.WEA(WEA),
.din(din),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_2" *)
module shd_pe_fifo_blk_mem_gen_v8_2__parameterized0
(D,
WEA,
wr_clk,
tmp_ram_rd_en,
rd_clk,
Q,
O1,
I1,
din);
output [7:0]D;
input [0:0]WEA;
input wr_clk;
input tmp_ram_rd_en;
input rd_clk;
input [0:0]Q;
input [11:0]O1;
input [11:0]I1;
input [7:0]din;
wire [7:0]D;
wire [11:0]I1;
wire [11:0]O1;
wire [0:0]Q;
wire [0:0]WEA;
wire [7:0]din;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
shd_pe_fifo_blk_mem_gen_v8_2_synth inst_blk_mem_gen
(.D(D),
.I1(I1),
.O1(O1),
.Q(Q),
.WEA(WEA),
.din(din),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_2_synth" *)
module shd_pe_fifo_blk_mem_gen_v8_2_synth
(D,
WEA,
wr_clk,
tmp_ram_rd_en,
rd_clk,
Q,
O1,
I1,
din);
output [7:0]D;
input [0:0]WEA;
input wr_clk;
input tmp_ram_rd_en;
input rd_clk;
input [0:0]Q;
input [11:0]O1;
input [11:0]I1;
input [7:0]din;
wire [7:0]D;
wire [11:0]I1;
wire [11:0]O1;
wire [0:0]Q;
wire [0:0]WEA;
wire [7:0]din;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
shd_pe_fifo_blk_mem_gen_top \gnativebmg.native_blk_mem_gen
(.D(D),
.I1(I1),
.O1(O1),
.Q(Q),
.WEA(WEA),
.din(din),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "clk_x_pntrs" *)
module shd_pe_fifo_clk_x_pntrs
(WR_PNTR_RD,
RD_PNTR_WR,
Q,
I1,
wr_clk,
I2,
rd_clk,
I3);
output [11:0]WR_PNTR_RD;
output [11:0]RD_PNTR_WR;
input [11:0]Q;
input [11:0]I1;
input wr_clk;
input [0:0]I2;
input rd_clk;
input [0:0]I3;
wire [11:0]I1;
wire [0:0]I2;
wire [0:0]I3;
wire [11:0]Q;
wire [11:0]Q_0;
wire [11:0]RD_PNTR_WR;
wire [11:0]WR_PNTR_RD;
wire \n_0_gsync_stage[1].wr_stg_inst ;
wire \n_0_gsync_stage[2].wr_stg_inst ;
wire \n_0_rd_pntr_gc[0]_i_1 ;
wire \n_0_rd_pntr_gc[10]_i_1 ;
wire \n_0_rd_pntr_gc[1]_i_1 ;
wire \n_0_rd_pntr_gc[2]_i_1 ;
wire \n_0_rd_pntr_gc[3]_i_1 ;
wire \n_0_rd_pntr_gc[4]_i_1 ;
wire \n_0_rd_pntr_gc[5]_i_1 ;
wire \n_0_rd_pntr_gc[6]_i_1 ;
wire \n_0_rd_pntr_gc[7]_i_1 ;
wire \n_0_rd_pntr_gc[8]_i_1 ;
wire \n_0_rd_pntr_gc[9]_i_1 ;
wire \n_10_gsync_stage[1].wr_stg_inst ;
wire \n_10_gsync_stage[2].wr_stg_inst ;
wire \n_11_gsync_stage[1].wr_stg_inst ;
wire \n_11_gsync_stage[2].wr_stg_inst ;
wire \n_1_gsync_stage[1].wr_stg_inst ;
wire \n_1_gsync_stage[2].wr_stg_inst ;
wire \n_2_gsync_stage[1].wr_stg_inst ;
wire \n_2_gsync_stage[2].wr_stg_inst ;
wire \n_3_gsync_stage[1].wr_stg_inst ;
wire \n_3_gsync_stage[2].wr_stg_inst ;
wire \n_4_gsync_stage[1].wr_stg_inst ;
wire \n_4_gsync_stage[2].wr_stg_inst ;
wire \n_5_gsync_stage[1].wr_stg_inst ;
wire \n_5_gsync_stage[2].wr_stg_inst ;
wire \n_6_gsync_stage[1].wr_stg_inst ;
wire \n_6_gsync_stage[2].wr_stg_inst ;
wire \n_7_gsync_stage[1].wr_stg_inst ;
wire \n_7_gsync_stage[2].wr_stg_inst ;
wire \n_8_gsync_stage[1].wr_stg_inst ;
wire \n_8_gsync_stage[2].wr_stg_inst ;
wire \n_9_gsync_stage[1].wr_stg_inst ;
wire \n_9_gsync_stage[2].wr_stg_inst ;
wire [11:0]p_0_in;
wire [10:0]p_0_in10_out;
wire rd_clk;
wire [11:0]rd_pntr_gc;
wire wr_clk;
wire [11:0]wr_pntr_gc;
shd_pe_fifo_synchronizer_ff \gsync_stage[1].rd_stg_inst
(.I1(wr_pntr_gc),
.I3(I3),
.Q(Q_0),
.rd_clk(rd_clk));
shd_pe_fifo_synchronizer_ff_3 \gsync_stage[1].wr_stg_inst
(.I1(rd_pntr_gc),
.I2(I2),
.Q({\n_0_gsync_stage[1].wr_stg_inst ,\n_1_gsync_stage[1].wr_stg_inst ,\n_2_gsync_stage[1].wr_stg_inst ,\n_3_gsync_stage[1].wr_stg_inst ,\n_4_gsync_stage[1].wr_stg_inst ,\n_5_gsync_stage[1].wr_stg_inst ,\n_6_gsync_stage[1].wr_stg_inst ,\n_7_gsync_stage[1].wr_stg_inst ,\n_8_gsync_stage[1].wr_stg_inst ,\n_9_gsync_stage[1].wr_stg_inst ,\n_10_gsync_stage[1].wr_stg_inst ,\n_11_gsync_stage[1].wr_stg_inst }),
.wr_clk(wr_clk));
shd_pe_fifo_synchronizer_ff_4 \gsync_stage[2].rd_stg_inst
(.D(Q_0),
.I3(I3),
.p_0_in(p_0_in),
.rd_clk(rd_clk));
shd_pe_fifo_synchronizer_ff_5 \gsync_stage[2].wr_stg_inst
(.D({\n_0_gsync_stage[1].wr_stg_inst ,\n_1_gsync_stage[1].wr_stg_inst ,\n_2_gsync_stage[1].wr_stg_inst ,\n_3_gsync_stage[1].wr_stg_inst ,\n_4_gsync_stage[1].wr_stg_inst ,\n_5_gsync_stage[1].wr_stg_inst ,\n_6_gsync_stage[1].wr_stg_inst ,\n_7_gsync_stage[1].wr_stg_inst ,\n_8_gsync_stage[1].wr_stg_inst ,\n_9_gsync_stage[1].wr_stg_inst ,\n_10_gsync_stage[1].wr_stg_inst ,\n_11_gsync_stage[1].wr_stg_inst }),
.I2(I2),
.O1({\n_1_gsync_stage[2].wr_stg_inst ,\n_2_gsync_stage[2].wr_stg_inst ,\n_3_gsync_stage[2].wr_stg_inst ,\n_4_gsync_stage[2].wr_stg_inst ,\n_5_gsync_stage[2].wr_stg_inst ,\n_6_gsync_stage[2].wr_stg_inst ,\n_7_gsync_stage[2].wr_stg_inst ,\n_8_gsync_stage[2].wr_stg_inst ,\n_9_gsync_stage[2].wr_stg_inst ,\n_10_gsync_stage[2].wr_stg_inst ,\n_11_gsync_stage[2].wr_stg_inst }),
.Q(\n_0_gsync_stage[2].wr_stg_inst ),
.wr_clk(wr_clk));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(\n_11_gsync_stage[2].wr_stg_inst ),
.Q(RD_PNTR_WR[0]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[10]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(\n_1_gsync_stage[2].wr_stg_inst ),
.Q(RD_PNTR_WR[10]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[11]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(\n_0_gsync_stage[2].wr_stg_inst ),
.Q(RD_PNTR_WR[11]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(\n_10_gsync_stage[2].wr_stg_inst ),
.Q(RD_PNTR_WR[1]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(\n_9_gsync_stage[2].wr_stg_inst ),
.Q(RD_PNTR_WR[2]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(\n_8_gsync_stage[2].wr_stg_inst ),
.Q(RD_PNTR_WR[3]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(\n_7_gsync_stage[2].wr_stg_inst ),
.Q(RD_PNTR_WR[4]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(\n_6_gsync_stage[2].wr_stg_inst ),
.Q(RD_PNTR_WR[5]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(\n_5_gsync_stage[2].wr_stg_inst ),
.Q(RD_PNTR_WR[6]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(\n_4_gsync_stage[2].wr_stg_inst ),
.Q(RD_PNTR_WR[7]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(\n_3_gsync_stage[2].wr_stg_inst ),
.Q(RD_PNTR_WR[8]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[9]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(\n_2_gsync_stage[2].wr_stg_inst ),
.Q(RD_PNTR_WR[9]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[0]_i_1
(.I0(I1[0]),
.I1(I1[1]),
.O(\n_0_rd_pntr_gc[0]_i_1 ));
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[10]_i_1
(.I0(I1[10]),
.I1(I1[11]),
.O(\n_0_rd_pntr_gc[10]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[1]_i_1
(.I0(I1[1]),
.I1(I1[2]),
.O(\n_0_rd_pntr_gc[1]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[2]_i_1
(.I0(I1[2]),
.I1(I1[3]),
.O(\n_0_rd_pntr_gc[2]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[3]_i_1
(.I0(I1[3]),
.I1(I1[4]),
.O(\n_0_rd_pntr_gc[3]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[4]_i_1
(.I0(I1[4]),
.I1(I1[5]),
.O(\n_0_rd_pntr_gc[4]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[5]_i_1
(.I0(I1[5]),
.I1(I1[6]),
.O(\n_0_rd_pntr_gc[5]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[6]_i_1
(.I0(I1[6]),
.I1(I1[7]),
.O(\n_0_rd_pntr_gc[6]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[7]_i_1
(.I0(I1[7]),
.I1(I1[8]),
.O(\n_0_rd_pntr_gc[7]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[8]_i_1
(.I0(I1[8]),
.I1(I1[9]),
.O(\n_0_rd_pntr_gc[8]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[9]_i_1
(.I0(I1[9]),
.I1(I1[10]),
.O(\n_0_rd_pntr_gc[9]_i_1 ));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(\n_0_rd_pntr_gc[0]_i_1 ),
.Q(rd_pntr_gc[0]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[10]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(\n_0_rd_pntr_gc[10]_i_1 ),
.Q(rd_pntr_gc[10]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[11]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(I1[11]),
.Q(rd_pntr_gc[11]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(\n_0_rd_pntr_gc[1]_i_1 ),
.Q(rd_pntr_gc[1]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(\n_0_rd_pntr_gc[2]_i_1 ),
.Q(rd_pntr_gc[2]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(\n_0_rd_pntr_gc[3]_i_1 ),
.Q(rd_pntr_gc[3]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(\n_0_rd_pntr_gc[4]_i_1 ),
.Q(rd_pntr_gc[4]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(\n_0_rd_pntr_gc[5]_i_1 ),
.Q(rd_pntr_gc[5]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(\n_0_rd_pntr_gc[6]_i_1 ),
.Q(rd_pntr_gc[6]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(\n_0_rd_pntr_gc[7]_i_1 ),
.Q(rd_pntr_gc[7]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(\n_0_rd_pntr_gc[8]_i_1 ),
.Q(rd_pntr_gc[8]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(\n_0_rd_pntr_gc[9]_i_1 ),
.Q(rd_pntr_gc[9]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(p_0_in[0]),
.Q(WR_PNTR_RD[0]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[10]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(p_0_in[10]),
.Q(WR_PNTR_RD[10]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[11]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(p_0_in[11]),
.Q(WR_PNTR_RD[11]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(p_0_in[1]),
.Q(WR_PNTR_RD[1]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(p_0_in[2]),
.Q(WR_PNTR_RD[2]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(p_0_in[3]),
.Q(WR_PNTR_RD[3]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(p_0_in[4]),
.Q(WR_PNTR_RD[4]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(p_0_in[5]),
.Q(WR_PNTR_RD[5]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(p_0_in[6]),
.Q(WR_PNTR_RD[6]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(p_0_in[7]),
.Q(WR_PNTR_RD[7]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(p_0_in[8]),
.Q(WR_PNTR_RD[8]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(p_0_in[9]),
.Q(WR_PNTR_RD[9]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[0]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(p_0_in10_out[0]));
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[10]_i_1
(.I0(Q[10]),
.I1(Q[11]),
.O(p_0_in10_out[10]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[1]_i_1
(.I0(Q[1]),
.I1(Q[2]),
.O(p_0_in10_out[1]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[2]_i_1
(.I0(Q[2]),
.I1(Q[3]),
.O(p_0_in10_out[2]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[3]_i_1
(.I0(Q[3]),
.I1(Q[4]),
.O(p_0_in10_out[3]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[4]_i_1
(.I0(Q[4]),
.I1(Q[5]),
.O(p_0_in10_out[4]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[5]_i_1
(.I0(Q[5]),
.I1(Q[6]),
.O(p_0_in10_out[5]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[6]_i_1
(.I0(Q[6]),
.I1(Q[7]),
.O(p_0_in10_out[6]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[7]_i_1
(.I0(Q[7]),
.I1(Q[8]),
.O(p_0_in10_out[7]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[8]_i_1
(.I0(Q[8]),
.I1(Q[9]),
.O(p_0_in10_out[8]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[9]_i_1
(.I0(Q[9]),
.I1(Q[10]),
.O(p_0_in10_out[9]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(p_0_in10_out[0]),
.Q(wr_pntr_gc[0]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[10]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(p_0_in10_out[10]),
.Q(wr_pntr_gc[10]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[11]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(Q[11]),
.Q(wr_pntr_gc[11]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(p_0_in10_out[1]),
.Q(wr_pntr_gc[1]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(p_0_in10_out[2]),
.Q(wr_pntr_gc[2]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(p_0_in10_out[3]),
.Q(wr_pntr_gc[3]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(p_0_in10_out[4]),
.Q(wr_pntr_gc[4]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(p_0_in10_out[5]),
.Q(wr_pntr_gc[5]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(p_0_in10_out[6]),
.Q(wr_pntr_gc[6]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(p_0_in10_out[7]),
.Q(wr_pntr_gc[7]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(p_0_in10_out[8]),
.Q(wr_pntr_gc[8]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[9]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(p_0_in10_out[9]),
.Q(wr_pntr_gc[9]));
endmodule
(* ORIG_REF_NAME = "compare" *)
module shd_pe_fifo_compare
(comp1,
Q,
RD_PNTR_WR);
output comp1;
input [11:0]Q;
input [11:0]RD_PNTR_WR;
wire [11:0]Q;
wire [11:0]RD_PNTR_WR;
wire comp1;
wire \n_0_gmux.gm[3].gms.ms ;
wire [5:0]v1_reg;
wire [2:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({\n_0_gmux.gm[3].gms.ms ,\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg[3:0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1
(.I0(Q[0]),
.I1(RD_PNTR_WR[0]),
.I2(Q[1]),
.I3(RD_PNTR_WR[1]),
.O(v1_reg[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1
(.I0(Q[2]),
.I1(RD_PNTR_WR[2]),
.I2(Q[3]),
.I3(RD_PNTR_WR[3]),
.O(v1_reg[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1
(.I0(Q[4]),
.I1(RD_PNTR_WR[4]),
.I2(Q[5]),
.I3(RD_PNTR_WR[5]),
.O(v1_reg[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1
(.I0(Q[6]),
.I1(RD_PNTR_WR[6]),
.I2(Q[7]),
.I3(RD_PNTR_WR[7]),
.O(v1_reg[3]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(\n_0_gmux.gm[3].gms.ms ),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:2],comp1,\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [0]}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:2],1'b0,1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:2],v1_reg[5:4]}));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1
(.I0(Q[8]),
.I1(RD_PNTR_WR[8]),
.I2(Q[9]),
.I3(RD_PNTR_WR[9]),
.O(v1_reg[4]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[5].gms.ms_i_1
(.I0(Q[10]),
.I1(RD_PNTR_WR[10]),
.I2(Q[11]),
.I3(RD_PNTR_WR[11]),
.O(v1_reg[5]));
endmodule
(* ORIG_REF_NAME = "compare" *)
module shd_pe_fifo_compare_0
(comp2,
out,
RD_PNTR_WR);
output comp2;
input [11:0]out;
input [11:0]RD_PNTR_WR;
wire [11:0]RD_PNTR_WR;
wire comp2;
wire \n_0_gmux.gm[3].gms.ms ;
wire [11:0]out;
wire [5:0]v1_reg;
wire [2:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({\n_0_gmux.gm[3].gms.ms ,\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg[3:0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1
(.I0(out[0]),
.I1(RD_PNTR_WR[0]),
.I2(out[1]),
.I3(RD_PNTR_WR[1]),
.O(v1_reg[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1
(.I0(out[2]),
.I1(RD_PNTR_WR[2]),
.I2(out[3]),
.I3(RD_PNTR_WR[3]),
.O(v1_reg[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1
(.I0(out[4]),
.I1(RD_PNTR_WR[4]),
.I2(out[5]),
.I3(RD_PNTR_WR[5]),
.O(v1_reg[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1
(.I0(out[6]),
.I1(RD_PNTR_WR[6]),
.I2(out[7]),
.I3(RD_PNTR_WR[7]),
.O(v1_reg[3]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(\n_0_gmux.gm[3].gms.ms ),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:2],comp2,\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [0]}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:2],1'b0,1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:2],v1_reg[5:4]}));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1
(.I0(out[8]),
.I1(RD_PNTR_WR[8]),
.I2(out[9]),
.I3(RD_PNTR_WR[9]),
.O(v1_reg[4]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[5].gms.ms_i_1
(.I0(out[10]),
.I1(RD_PNTR_WR[10]),
.I2(out[11]),
.I3(RD_PNTR_WR[11]),
.O(v1_reg[5]));
endmodule
(* ORIG_REF_NAME = "compare" *)
module shd_pe_fifo_compare_1
(comp0,
WR_PNTR_RD,
O1);
output comp0;
input [11:0]WR_PNTR_RD;
input [11:0]O1;
wire [11:0]O1;
wire [11:0]WR_PNTR_RD;
wire comp0;
wire \n_0_gmux.gm[3].gms.ms ;
wire [5:0]v1_reg;
wire [2:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({\n_0_gmux.gm[3].gms.ms ,\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg[3:0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1
(.I0(WR_PNTR_RD[0]),
.I1(O1[0]),
.I2(WR_PNTR_RD[1]),
.I3(O1[1]),
.O(v1_reg[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1
(.I0(WR_PNTR_RD[2]),
.I1(O1[2]),
.I2(WR_PNTR_RD[3]),
.I3(O1[3]),
.O(v1_reg[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1
(.I0(WR_PNTR_RD[4]),
.I1(O1[4]),
.I2(WR_PNTR_RD[5]),
.I3(O1[5]),
.O(v1_reg[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1
(.I0(WR_PNTR_RD[6]),
.I1(O1[6]),
.I2(WR_PNTR_RD[7]),
.I3(O1[7]),
.O(v1_reg[3]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(\n_0_gmux.gm[3].gms.ms ),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:2],comp0,\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [0]}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:2],1'b0,1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:2],v1_reg[5:4]}));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1
(.I0(WR_PNTR_RD[8]),
.I1(O1[8]),
.I2(WR_PNTR_RD[9]),
.I3(O1[9]),
.O(v1_reg[4]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[5].gms.ms_i_1
(.I0(WR_PNTR_RD[10]),
.I1(O1[10]),
.I2(WR_PNTR_RD[11]),
.I3(O1[11]),
.O(v1_reg[5]));
endmodule
(* ORIG_REF_NAME = "compare" *)
module shd_pe_fifo_compare_2
(comp1,
WR_PNTR_RD,
out);
output comp1;
input [11:0]WR_PNTR_RD;
input [11:0]out;
wire [11:0]WR_PNTR_RD;
wire comp1;
wire \n_0_gmux.gm[3].gms.ms ;
wire [11:0]out;
wire [5:0]v1_reg;
wire [2:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({\n_0_gmux.gm[3].gms.ms ,\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg[3:0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1
(.I0(WR_PNTR_RD[0]),
.I1(out[0]),
.I2(WR_PNTR_RD[1]),
.I3(out[1]),
.O(v1_reg[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1
(.I0(WR_PNTR_RD[2]),
.I1(out[2]),
.I2(WR_PNTR_RD[3]),
.I3(out[3]),
.O(v1_reg[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1
(.I0(WR_PNTR_RD[4]),
.I1(out[4]),
.I2(WR_PNTR_RD[5]),
.I3(out[5]),
.O(v1_reg[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1
(.I0(WR_PNTR_RD[6]),
.I1(out[6]),
.I2(WR_PNTR_RD[7]),
.I3(out[7]),
.O(v1_reg[3]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(\n_0_gmux.gm[3].gms.ms ),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:2],comp1,\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [0]}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:2],1'b0,1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:2],v1_reg[5:4]}));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1
(.I0(WR_PNTR_RD[8]),
.I1(out[8]),
.I2(WR_PNTR_RD[9]),
.I3(out[9]),
.O(v1_reg[4]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[5].gms.ms_i_1
(.I0(WR_PNTR_RD[10]),
.I1(out[10]),
.I2(WR_PNTR_RD[11]),
.I3(out[11]),
.O(v1_reg[5]));
endmodule
(* ORIG_REF_NAME = "fifo_generator_ramfifo" *)
module shd_pe_fifo_fifo_generator_ramfifo
(dout,
empty,
full,
wr_en,
wr_clk,
rd_clk,
din,
rst,
rd_en);
output [7:0]dout;
output empty;
output full;
input wr_en;
input wr_clk;
input rd_clk;
input [7:0]din;
input rst;
input rd_en;
wire RD_RST;
wire RST;
wire [7:0]din;
wire [7:0]dout;
wire empty;
wire full;
wire \n_1_gntv_or_sync_fifo.gl0.wr ;
wire [11:0]p_0_out;
wire p_15_out;
wire [11:0]p_1_out;
wire [11:0]p_20_out;
wire [11:0]p_9_out;
wire rd_clk;
wire rd_en;
wire [1:0]rd_rst_i;
wire rst;
wire rst_d2;
wire rst_full_gen_i;
wire tmp_ram_rd_en;
wire wr_clk;
wire wr_en;
wire [0:0]wr_rst_i;
shd_pe_fifo_clk_x_pntrs \gntv_or_sync_fifo.gcx.clkx
(.I1(p_20_out),
.I2(wr_rst_i),
.I3(rd_rst_i[1]),
.Q(p_9_out),
.RD_PNTR_WR(p_0_out),
.WR_PNTR_RD(p_1_out),
.rd_clk(rd_clk),
.wr_clk(wr_clk));
shd_pe_fifo_rd_logic \gntv_or_sync_fifo.gl0.rd
(.E(p_15_out),
.O1(p_20_out),
.Q({RD_RST,rd_rst_i[0]}),
.WR_PNTR_RD(p_1_out),
.empty(empty),
.rd_clk(rd_clk),
.rd_en(rd_en),
.tmp_ram_rd_en(tmp_ram_rd_en));
shd_pe_fifo_wr_logic \gntv_or_sync_fifo.gl0.wr
(.O1(p_9_out),
.Q(RST),
.RD_PNTR_WR(p_0_out),
.WEA(\n_1_gntv_or_sync_fifo.gl0.wr ),
.full(full),
.rst_d2(rst_d2),
.rst_full_gen_i(rst_full_gen_i),
.wr_clk(wr_clk),
.wr_en(wr_en));
shd_pe_fifo_memory \gntv_or_sync_fifo.mem
(.E(p_15_out),
.I1(p_20_out),
.O1(p_9_out),
.Q(rd_rst_i[0]),
.WEA(\n_1_gntv_or_sync_fifo.gl0.wr ),
.din(din),
.dout(dout),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
shd_pe_fifo_reset_blk_ramfifo rstblk
(.O1({RD_RST,rd_rst_i}),
.Q({RST,wr_rst_i}),
.rd_clk(rd_clk),
.rst(rst),
.rst_d2(rst_d2),
.rst_full_gen_i(rst_full_gen_i),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "fifo_generator_top" *)
module shd_pe_fifo_fifo_generator_top
(dout,
empty,
full,
wr_en,
wr_clk,
rd_clk,
din,
rst,
rd_en);
output [7:0]dout;
output empty;
output full;
input wr_en;
input wr_clk;
input rd_clk;
input [7:0]din;
input rst;
input rd_en;
wire [7:0]din;
wire [7:0]dout;
wire empty;
wire full;
wire rd_clk;
wire rd_en;
wire rst;
wire wr_clk;
wire wr_en;
shd_pe_fifo_fifo_generator_ramfifo \grf.rf
(.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_en(wr_en));
endmodule
(* ORIG_REF_NAME = "fifo_generator_v12_0" *) (* C_COMMON_CLOCK = "0" *) (* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "12" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "8" *)
(* C_DOUT_RST_VAL = "0" *) (* C_DOUT_WIDTH = "8" *) (* C_ENABLE_RLOCS = "0" *)
(* C_FAMILY = "virtex7" *) (* C_FULL_FLAGS_RST_VAL = "1" *) (* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *) (* C_HAS_BACKUP = "0" *) (* C_HAS_DATA_COUNT = "0" *)
(* C_HAS_INT_CLK = "0" *) (* C_HAS_MEMINIT_FILE = "0" *) (* C_HAS_OVERFLOW = "0" *)
(* C_HAS_RD_DATA_COUNT = "0" *) (* C_HAS_RD_RST = "0" *) (* C_HAS_RST = "1" *)
(* C_HAS_SRST = "0" *) (* C_HAS_UNDERFLOW = "0" *) (* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *) (* C_HAS_WR_DATA_COUNT = "0" *) (* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "2" *) (* C_INIT_WR_PNTR_VAL = "0" *) (* C_MEMORY_TYPE = "1" *)
(* C_MIF_FILE_NAME = "BlankString" *) (* C_OPTIMIZATION_MODE = "0" *) (* C_OVERFLOW_LOW = "0" *)
(* C_PRELOAD_LATENCY = "0" *) (* C_PRELOAD_REGS = "1" *) (* C_PRIM_FIFO_TYPE = "4kx9" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "4" *) (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "5" *) (* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "4095" *) (* C_PROG_FULL_THRESH_NEGATE_VAL = "4094" *) (* C_PROG_FULL_TYPE = "0" *)
(* C_RD_DATA_COUNT_WIDTH = "12" *) (* C_RD_DEPTH = "4096" *) (* C_RD_FREQ = "1" *)
(* C_RD_PNTR_WIDTH = "12" *) (* C_UNDERFLOW_LOW = "0" *) (* C_USE_DOUT_RST = "1" *)
(* C_USE_ECC = "0" *) (* C_USE_EMBEDDED_REG = "0" *) (* C_USE_PIPELINE_REG = "0" *)
(* C_POWER_SAVING_MODE = "0" *) (* C_USE_FIFO16_FLAGS = "0" *) (* C_USE_FWFT_DATA_COUNT = "0" *)
(* C_VALID_LOW = "0" *) (* C_WR_ACK_LOW = "0" *) (* C_WR_DATA_COUNT_WIDTH = "12" *)
(* C_WR_DEPTH = "4096" *) (* C_WR_FREQ = "1" *) (* C_WR_PNTR_WIDTH = "12" *)
(* C_WR_RESPONSE_LATENCY = "1" *) (* C_MSGON_VAL = "1" *) (* C_ENABLE_RST_SYNC = "1" *)
(* C_ERROR_INJECTION_TYPE = "0" *) (* C_SYNCHRONIZER_STAGE = "2" *) (* C_INTERFACE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *) (* C_HAS_AXI_WR_CHANNEL = "1" *) (* C_HAS_AXI_RD_CHANNEL = "1" *)
(* C_HAS_SLAVE_CE = "0" *) (* C_HAS_MASTER_CE = "0" *) (* C_ADD_NGC_CONSTRAINT = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *) (* C_USE_COMMON_UNDERFLOW = "0" *) (* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_AXI_ID_WIDTH = "1" *) (* C_AXI_ADDR_WIDTH = "32" *) (* C_AXI_DATA_WIDTH = "64" *)
(* C_AXI_LEN_WIDTH = "8" *) (* C_AXI_LOCK_WIDTH = "1" *) (* C_HAS_AXI_ID = "0" *)
(* C_HAS_AXI_AWUSER = "0" *) (* C_HAS_AXI_WUSER = "0" *) (* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ARUSER = "0" *) (* C_HAS_AXI_RUSER = "0" *) (* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_WUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_RUSER_WIDTH = "1" *) (* C_HAS_AXIS_TDATA = "1" *) (* C_HAS_AXIS_TID = "0" *)
(* C_HAS_AXIS_TDEST = "0" *) (* C_HAS_AXIS_TUSER = "1" *) (* C_HAS_AXIS_TREADY = "1" *)
(* C_HAS_AXIS_TLAST = "0" *) (* C_HAS_AXIS_TSTRB = "0" *) (* C_HAS_AXIS_TKEEP = "0" *)
(* C_AXIS_TDATA_WIDTH = "8" *) (* C_AXIS_TID_WIDTH = "1" *) (* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *) (* C_AXIS_TSTRB_WIDTH = "1" *) (* C_AXIS_TKEEP_WIDTH = "1" *)
(* C_WACH_TYPE = "0" *) (* C_WDCH_TYPE = "0" *) (* C_WRCH_TYPE = "0" *)
(* C_RACH_TYPE = "0" *) (* C_RDCH_TYPE = "0" *) (* C_AXIS_TYPE = "0" *)
(* C_IMPLEMENTATION_TYPE_WACH = "1" *) (* C_IMPLEMENTATION_TYPE_WDCH = "1" *) (* C_IMPLEMENTATION_TYPE_WRCH = "1" *)
(* C_IMPLEMENTATION_TYPE_RACH = "1" *) (* C_IMPLEMENTATION_TYPE_RDCH = "1" *) (* C_IMPLEMENTATION_TYPE_AXIS = "1" *)
(* C_APPLICATION_TYPE_WACH = "0" *) (* C_APPLICATION_TYPE_WDCH = "0" *) (* C_APPLICATION_TYPE_WRCH = "0" *)
(* C_APPLICATION_TYPE_RACH = "0" *) (* C_APPLICATION_TYPE_RDCH = "0" *) (* C_APPLICATION_TYPE_AXIS = "0" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *) (* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PRIM_FIFO_TYPE_RACH = "512x36" *) (* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *)
(* C_USE_ECC_WACH = "0" *) (* C_USE_ECC_WDCH = "0" *) (* C_USE_ECC_WRCH = "0" *)
(* C_USE_ECC_RACH = "0" *) (* C_USE_ECC_RDCH = "0" *) (* C_USE_ECC_AXIS = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *) (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_ERROR_INJECTION_TYPE_RACH = "0" *) (* C_ERROR_INJECTION_TYPE_RDCH = "0" *) (* C_ERROR_INJECTION_TYPE_AXIS = "0" *)
(* C_DIN_WIDTH_WACH = "32" *) (* C_DIN_WIDTH_WDCH = "64" *) (* C_DIN_WIDTH_WRCH = "2" *)
(* C_DIN_WIDTH_RACH = "32" *) (* C_DIN_WIDTH_RDCH = "64" *) (* C_DIN_WIDTH_AXIS = "1" *)
(* C_WR_DEPTH_WACH = "16" *) (* C_WR_DEPTH_WDCH = "1024" *) (* C_WR_DEPTH_WRCH = "16" *)
(* C_WR_DEPTH_RACH = "16" *) (* C_WR_DEPTH_RDCH = "1024" *) (* C_WR_DEPTH_AXIS = "1024" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *) (* C_WR_PNTR_WIDTH_WDCH = "10" *) (* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_PNTR_WIDTH_RACH = "4" *) (* C_WR_PNTR_WIDTH_RDCH = "10" *) (* C_WR_PNTR_WIDTH_AXIS = "10" *)
(* C_HAS_DATA_COUNTS_WACH = "0" *) (* C_HAS_DATA_COUNTS_WDCH = "0" *) (* C_HAS_DATA_COUNTS_WRCH = "0" *)
(* C_HAS_DATA_COUNTS_RACH = "0" *) (* C_HAS_DATA_COUNTS_RDCH = "0" *) (* C_HAS_DATA_COUNTS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_WACH = "0" *) (* C_HAS_PROG_FLAGS_WDCH = "0" *) (* C_HAS_PROG_FLAGS_WRCH = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *) (* C_HAS_PROG_FLAGS_RDCH = "0" *) (* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *) (* C_PROG_FULL_TYPE_WDCH = "0" *) (* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_PROG_FULL_TYPE_RACH = "0" *) (* C_PROG_FULL_TYPE_RDCH = "0" *) (* C_PROG_FULL_TYPE_AXIS = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *) (* C_PROG_EMPTY_TYPE_WDCH = "0" *) (* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_EMPTY_TYPE_RACH = "0" *) (* C_PROG_EMPTY_TYPE_RDCH = "0" *) (* C_PROG_EMPTY_TYPE_AXIS = "0" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *)
(* C_REG_SLICE_MODE_WACH = "0" *) (* C_REG_SLICE_MODE_WDCH = "0" *) (* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_REG_SLICE_MODE_RACH = "0" *) (* C_REG_SLICE_MODE_RDCH = "0" *) (* C_REG_SLICE_MODE_AXIS = "0" *)
module shd_pe_fifo_fifo_generator_v12_0__parameterized0
(backup,
backup_marker,
clk,
rst,
srst,
wr_clk,
wr_rst,
rd_clk,
rd_rst,
din,
wr_en,
rd_en,
prog_empty_thresh,
prog_empty_thresh_assert,
prog_empty_thresh_negate,
prog_full_thresh,
prog_full_thresh_assert,
prog_full_thresh_negate,
int_clk,
injectdbiterr,
injectsbiterr,
sleep,
dout,
full,
almost_full,
wr_ack,
overflow,
empty,
almost_empty,
valid,
underflow,
data_count,
rd_data_count,
wr_data_count,
prog_full,
prog_empty,
sbiterr,
dbiterr,
wr_rst_busy,
rd_rst_busy,
m_aclk,
s_aclk,
s_aresetn,
m_aclk_en,
s_aclk_en,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awregion,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awregion,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arregion,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arqos,
m_axi_arregion,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tstrb,
s_axis_tkeep,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tstrb,
m_axis_tkeep,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser,
axi_aw_injectsbiterr,
axi_aw_injectdbiterr,
axi_aw_prog_full_thresh,
axi_aw_prog_empty_thresh,
axi_aw_data_count,
axi_aw_wr_data_count,
axi_aw_rd_data_count,
axi_aw_sbiterr,
axi_aw_dbiterr,
axi_aw_overflow,
axi_aw_underflow,
axi_aw_prog_full,
axi_aw_prog_empty,
axi_w_injectsbiterr,
axi_w_injectdbiterr,
axi_w_prog_full_thresh,
axi_w_prog_empty_thresh,
axi_w_data_count,
axi_w_wr_data_count,
axi_w_rd_data_count,
axi_w_sbiterr,
axi_w_dbiterr,
axi_w_overflow,
axi_w_underflow,
axi_w_prog_full,
axi_w_prog_empty,
axi_b_injectsbiterr,
axi_b_injectdbiterr,
axi_b_prog_full_thresh,
axi_b_prog_empty_thresh,
axi_b_data_count,
axi_b_wr_data_count,
axi_b_rd_data_count,
axi_b_sbiterr,
axi_b_dbiterr,
axi_b_overflow,
axi_b_underflow,
axi_b_prog_full,
axi_b_prog_empty,
axi_ar_injectsbiterr,
axi_ar_injectdbiterr,
axi_ar_prog_full_thresh,
axi_ar_prog_empty_thresh,
axi_ar_data_count,
axi_ar_wr_data_count,
axi_ar_rd_data_count,
axi_ar_sbiterr,
axi_ar_dbiterr,
axi_ar_overflow,
axi_ar_underflow,
axi_ar_prog_full,
axi_ar_prog_empty,
axi_r_injectsbiterr,
axi_r_injectdbiterr,
axi_r_prog_full_thresh,
axi_r_prog_empty_thresh,
axi_r_data_count,
axi_r_wr_data_count,
axi_r_rd_data_count,
axi_r_sbiterr,
axi_r_dbiterr,
axi_r_overflow,
axi_r_underflow,
axi_r_prog_full,
axi_r_prog_empty,
axis_injectsbiterr,
axis_injectdbiterr,
axis_prog_full_thresh,
axis_prog_empty_thresh,
axis_data_count,
axis_wr_data_count,
axis_rd_data_count,
axis_sbiterr,
axis_dbiterr,
axis_overflow,
axis_underflow,
axis_prog_full,
axis_prog_empty);
input backup;
input backup_marker;
input clk;
input rst;
input srst;
input wr_clk;
input wr_rst;
input rd_clk;
input rd_rst;
input [7:0]din;
input wr_en;
input rd_en;
input [11:0]prog_empty_thresh;
input [11:0]prog_empty_thresh_assert;
input [11:0]prog_empty_thresh_negate;
input [11:0]prog_full_thresh;
input [11:0]prog_full_thresh_assert;
input [11:0]prog_full_thresh_negate;
input int_clk;
input injectdbiterr;
input injectsbiterr;
input sleep;
output [7:0]dout;
output full;
output almost_full;
output wr_ack;
output overflow;
output empty;
output almost_empty;
output valid;
output underflow;
output [11:0]data_count;
output [11:0]rd_data_count;
output [11:0]wr_data_count;
output prog_full;
output prog_empty;
output sbiterr;
output dbiterr;
output wr_rst_busy;
output rd_rst_busy;
input m_aclk;
input s_aclk;
input s_aresetn;
input m_aclk_en;
input s_aclk_en;
input [0:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [3:0]s_axi_awregion;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [0:0]s_axi_wid;
input [63:0]s_axi_wdata;
input [7:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
output [0:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awqos;
output [3:0]m_axi_awregion;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [0:0]m_axi_wid;
output [63:0]m_axi_wdata;
output [7:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [0:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
input [0:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [3:0]s_axi_arregion;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [0:0]s_axi_rid;
output [63:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
output [0:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arqos;
output [3:0]m_axi_arregion;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [0:0]m_axi_rid;
input [63:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
input s_axis_tvalid;
output s_axis_tready;
input [7:0]s_axis_tdata;
input [0:0]s_axis_tstrb;
input [0:0]s_axis_tkeep;
input s_axis_tlast;
input [0:0]s_axis_tid;
input [0:0]s_axis_tdest;
input [3:0]s_axis_tuser;
output m_axis_tvalid;
input m_axis_tready;
output [7:0]m_axis_tdata;
output [0:0]m_axis_tstrb;
output [0:0]m_axis_tkeep;
output m_axis_tlast;
output [0:0]m_axis_tid;
output [0:0]m_axis_tdest;
output [3:0]m_axis_tuser;
input axi_aw_injectsbiterr;
input axi_aw_injectdbiterr;
input [3:0]axi_aw_prog_full_thresh;
input [3:0]axi_aw_prog_empty_thresh;
output [4:0]axi_aw_data_count;
output [4:0]axi_aw_wr_data_count;
output [4:0]axi_aw_rd_data_count;
output axi_aw_sbiterr;
output axi_aw_dbiterr;
output axi_aw_overflow;
output axi_aw_underflow;
output axi_aw_prog_full;
output axi_aw_prog_empty;
input axi_w_injectsbiterr;
input axi_w_injectdbiterr;
input [9:0]axi_w_prog_full_thresh;
input [9:0]axi_w_prog_empty_thresh;
output [10:0]axi_w_data_count;
output [10:0]axi_w_wr_data_count;
output [10:0]axi_w_rd_data_count;
output axi_w_sbiterr;
output axi_w_dbiterr;
output axi_w_overflow;
output axi_w_underflow;
output axi_w_prog_full;
output axi_w_prog_empty;
input axi_b_injectsbiterr;
input axi_b_injectdbiterr;
input [3:0]axi_b_prog_full_thresh;
input [3:0]axi_b_prog_empty_thresh;
output [4:0]axi_b_data_count;
output [4:0]axi_b_wr_data_count;
output [4:0]axi_b_rd_data_count;
output axi_b_sbiterr;
output axi_b_dbiterr;
output axi_b_overflow;
output axi_b_underflow;
output axi_b_prog_full;
output axi_b_prog_empty;
input axi_ar_injectsbiterr;
input axi_ar_injectdbiterr;
input [3:0]axi_ar_prog_full_thresh;
input [3:0]axi_ar_prog_empty_thresh;
output [4:0]axi_ar_data_count;
output [4:0]axi_ar_wr_data_count;
output [4:0]axi_ar_rd_data_count;
output axi_ar_sbiterr;
output axi_ar_dbiterr;
output axi_ar_overflow;
output axi_ar_underflow;
output axi_ar_prog_full;
output axi_ar_prog_empty;
input axi_r_injectsbiterr;
input axi_r_injectdbiterr;
input [9:0]axi_r_prog_full_thresh;
input [9:0]axi_r_prog_empty_thresh;
output [10:0]axi_r_data_count;
output [10:0]axi_r_wr_data_count;
output [10:0]axi_r_rd_data_count;
output axi_r_sbiterr;
output axi_r_dbiterr;
output axi_r_overflow;
output axi_r_underflow;
output axi_r_prog_full;
output axi_r_prog_empty;
input axis_injectsbiterr;
input axis_injectdbiterr;
input [9:0]axis_prog_full_thresh;
input [9:0]axis_prog_empty_thresh;
output [10:0]axis_data_count;
output [10:0]axis_wr_data_count;
output [10:0]axis_rd_data_count;
output axis_sbiterr;
output axis_dbiterr;
output axis_overflow;
output axis_underflow;
output axis_prog_full;
output axis_prog_empty;
wire \<const0> ;
wire \<const1> ;
wire axi_ar_injectdbiterr;
wire axi_ar_injectsbiterr;
wire [3:0]axi_ar_prog_empty_thresh;
wire [3:0]axi_ar_prog_full_thresh;
wire axi_aw_injectdbiterr;
wire axi_aw_injectsbiterr;
wire [3:0]axi_aw_prog_empty_thresh;
wire [3:0]axi_aw_prog_full_thresh;
wire axi_b_injectdbiterr;
wire axi_b_injectsbiterr;
wire [3:0]axi_b_prog_empty_thresh;
wire [3:0]axi_b_prog_full_thresh;
wire axi_r_injectdbiterr;
wire axi_r_injectsbiterr;
wire [9:0]axi_r_prog_empty_thresh;
wire [9:0]axi_r_prog_full_thresh;
wire axi_w_injectdbiterr;
wire axi_w_injectsbiterr;
wire [9:0]axi_w_prog_empty_thresh;
wire [9:0]axi_w_prog_full_thresh;
wire axis_injectdbiterr;
wire axis_injectsbiterr;
wire [9:0]axis_prog_empty_thresh;
wire [9:0]axis_prog_full_thresh;
wire backup;
wire backup_marker;
wire clk;
wire [7:0]din;
wire [7:0]dout;
wire empty;
wire full;
wire injectdbiterr;
wire injectsbiterr;
wire int_clk;
wire m_aclk;
wire m_aclk_en;
wire m_axi_arready;
wire m_axi_awready;
wire [0:0]m_axi_bid;
wire [1:0]m_axi_bresp;
wire [0:0]m_axi_buser;
wire m_axi_bvalid;
wire [63:0]m_axi_rdata;
wire [0:0]m_axi_rid;
wire m_axi_rlast;
wire [1:0]m_axi_rresp;
wire [0:0]m_axi_ruser;
wire m_axi_rvalid;
wire m_axi_wready;
wire m_axis_tready;
wire [11:0]prog_empty_thresh;
wire [11:0]prog_empty_thresh_assert;
wire [11:0]prog_empty_thresh_negate;
wire [11:0]prog_full_thresh;
wire [11:0]prog_full_thresh_assert;
wire [11:0]prog_full_thresh_negate;
wire rd_clk;
wire rd_en;
wire rd_rst;
wire rst;
wire s_aclk;
wire s_aclk_en;
wire s_aresetn;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire [0:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [0:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire [3:0]s_axi_arregion;
wire [2:0]s_axi_arsize;
wire [0:0]s_axi_aruser;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [0:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [0:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire [3:0]s_axi_awregion;
wire [2:0]s_axi_awsize;
wire [0:0]s_axi_awuser;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_rready;
wire [63:0]s_axi_wdata;
wire [0:0]s_axi_wid;
wire s_axi_wlast;
wire [7:0]s_axi_wstrb;
wire [0:0]s_axi_wuser;
wire s_axi_wvalid;
wire [7:0]s_axis_tdata;
wire [0:0]s_axis_tdest;
wire [0:0]s_axis_tid;
wire [0:0]s_axis_tkeep;
wire s_axis_tlast;
wire [0:0]s_axis_tstrb;
wire [3:0]s_axis_tuser;
wire s_axis_tvalid;
wire srst;
wire wr_clk;
wire wr_en;
wire wr_rst;
assign almost_empty = \<const0> ;
assign almost_full = \<const0> ;
assign axi_ar_data_count[4] = \<const0> ;
assign axi_ar_data_count[3] = \<const0> ;
assign axi_ar_data_count[2] = \<const0> ;
assign axi_ar_data_count[1] = \<const0> ;
assign axi_ar_data_count[0] = \<const0> ;
assign axi_ar_dbiterr = \<const0> ;
assign axi_ar_overflow = \<const0> ;
assign axi_ar_prog_empty = \<const1> ;
assign axi_ar_prog_full = \<const0> ;
assign axi_ar_rd_data_count[4] = \<const0> ;
assign axi_ar_rd_data_count[3] = \<const0> ;
assign axi_ar_rd_data_count[2] = \<const0> ;
assign axi_ar_rd_data_count[1] = \<const0> ;
assign axi_ar_rd_data_count[0] = \<const0> ;
assign axi_ar_sbiterr = \<const0> ;
assign axi_ar_underflow = \<const0> ;
assign axi_ar_wr_data_count[4] = \<const0> ;
assign axi_ar_wr_data_count[3] = \<const0> ;
assign axi_ar_wr_data_count[2] = \<const0> ;
assign axi_ar_wr_data_count[1] = \<const0> ;
assign axi_ar_wr_data_count[0] = \<const0> ;
assign axi_aw_data_count[4] = \<const0> ;
assign axi_aw_data_count[3] = \<const0> ;
assign axi_aw_data_count[2] = \<const0> ;
assign axi_aw_data_count[1] = \<const0> ;
assign axi_aw_data_count[0] = \<const0> ;
assign axi_aw_dbiterr = \<const0> ;
assign axi_aw_overflow = \<const0> ;
assign axi_aw_prog_empty = \<const1> ;
assign axi_aw_prog_full = \<const0> ;
assign axi_aw_rd_data_count[4] = \<const0> ;
assign axi_aw_rd_data_count[3] = \<const0> ;
assign axi_aw_rd_data_count[2] = \<const0> ;
assign axi_aw_rd_data_count[1] = \<const0> ;
assign axi_aw_rd_data_count[0] = \<const0> ;
assign axi_aw_sbiterr = \<const0> ;
assign axi_aw_underflow = \<const0> ;
assign axi_aw_wr_data_count[4] = \<const0> ;
assign axi_aw_wr_data_count[3] = \<const0> ;
assign axi_aw_wr_data_count[2] = \<const0> ;
assign axi_aw_wr_data_count[1] = \<const0> ;
assign axi_aw_wr_data_count[0] = \<const0> ;
assign axi_b_data_count[4] = \<const0> ;
assign axi_b_data_count[3] = \<const0> ;
assign axi_b_data_count[2] = \<const0> ;
assign axi_b_data_count[1] = \<const0> ;
assign axi_b_data_count[0] = \<const0> ;
assign axi_b_dbiterr = \<const0> ;
assign axi_b_overflow = \<const0> ;
assign axi_b_prog_empty = \<const1> ;
assign axi_b_prog_full = \<const0> ;
assign axi_b_rd_data_count[4] = \<const0> ;
assign axi_b_rd_data_count[3] = \<const0> ;
assign axi_b_rd_data_count[2] = \<const0> ;
assign axi_b_rd_data_count[1] = \<const0> ;
assign axi_b_rd_data_count[0] = \<const0> ;
assign axi_b_sbiterr = \<const0> ;
assign axi_b_underflow = \<const0> ;
assign axi_b_wr_data_count[4] = \<const0> ;
assign axi_b_wr_data_count[3] = \<const0> ;
assign axi_b_wr_data_count[2] = \<const0> ;
assign axi_b_wr_data_count[1] = \<const0> ;
assign axi_b_wr_data_count[0] = \<const0> ;
assign axi_r_data_count[10] = \<const0> ;
assign axi_r_data_count[9] = \<const0> ;
assign axi_r_data_count[8] = \<const0> ;
assign axi_r_data_count[7] = \<const0> ;
assign axi_r_data_count[6] = \<const0> ;
assign axi_r_data_count[5] = \<const0> ;
assign axi_r_data_count[4] = \<const0> ;
assign axi_r_data_count[3] = \<const0> ;
assign axi_r_data_count[2] = \<const0> ;
assign axi_r_data_count[1] = \<const0> ;
assign axi_r_data_count[0] = \<const0> ;
assign axi_r_dbiterr = \<const0> ;
assign axi_r_overflow = \<const0> ;
assign axi_r_prog_empty = \<const1> ;
assign axi_r_prog_full = \<const0> ;
assign axi_r_rd_data_count[10] = \<const0> ;
assign axi_r_rd_data_count[9] = \<const0> ;
assign axi_r_rd_data_count[8] = \<const0> ;
assign axi_r_rd_data_count[7] = \<const0> ;
assign axi_r_rd_data_count[6] = \<const0> ;
assign axi_r_rd_data_count[5] = \<const0> ;
assign axi_r_rd_data_count[4] = \<const0> ;
assign axi_r_rd_data_count[3] = \<const0> ;
assign axi_r_rd_data_count[2] = \<const0> ;
assign axi_r_rd_data_count[1] = \<const0> ;
assign axi_r_rd_data_count[0] = \<const0> ;
assign axi_r_sbiterr = \<const0> ;
assign axi_r_underflow = \<const0> ;
assign axi_r_wr_data_count[10] = \<const0> ;
assign axi_r_wr_data_count[9] = \<const0> ;
assign axi_r_wr_data_count[8] = \<const0> ;
assign axi_r_wr_data_count[7] = \<const0> ;
assign axi_r_wr_data_count[6] = \<const0> ;
assign axi_r_wr_data_count[5] = \<const0> ;
assign axi_r_wr_data_count[4] = \<const0> ;
assign axi_r_wr_data_count[3] = \<const0> ;
assign axi_r_wr_data_count[2] = \<const0> ;
assign axi_r_wr_data_count[1] = \<const0> ;
assign axi_r_wr_data_count[0] = \<const0> ;
assign axi_w_data_count[10] = \<const0> ;
assign axi_w_data_count[9] = \<const0> ;
assign axi_w_data_count[8] = \<const0> ;
assign axi_w_data_count[7] = \<const0> ;
assign axi_w_data_count[6] = \<const0> ;
assign axi_w_data_count[5] = \<const0> ;
assign axi_w_data_count[4] = \<const0> ;
assign axi_w_data_count[3] = \<const0> ;
assign axi_w_data_count[2] = \<const0> ;
assign axi_w_data_count[1] = \<const0> ;
assign axi_w_data_count[0] = \<const0> ;
assign axi_w_dbiterr = \<const0> ;
assign axi_w_overflow = \<const0> ;
assign axi_w_prog_empty = \<const1> ;
assign axi_w_prog_full = \<const0> ;
assign axi_w_rd_data_count[10] = \<const0> ;
assign axi_w_rd_data_count[9] = \<const0> ;
assign axi_w_rd_data_count[8] = \<const0> ;
assign axi_w_rd_data_count[7] = \<const0> ;
assign axi_w_rd_data_count[6] = \<const0> ;
assign axi_w_rd_data_count[5] = \<const0> ;
assign axi_w_rd_data_count[4] = \<const0> ;
assign axi_w_rd_data_count[3] = \<const0> ;
assign axi_w_rd_data_count[2] = \<const0> ;
assign axi_w_rd_data_count[1] = \<const0> ;
assign axi_w_rd_data_count[0] = \<const0> ;
assign axi_w_sbiterr = \<const0> ;
assign axi_w_underflow = \<const0> ;
assign axi_w_wr_data_count[10] = \<const0> ;
assign axi_w_wr_data_count[9] = \<const0> ;
assign axi_w_wr_data_count[8] = \<const0> ;
assign axi_w_wr_data_count[7] = \<const0> ;
assign axi_w_wr_data_count[6] = \<const0> ;
assign axi_w_wr_data_count[5] = \<const0> ;
assign axi_w_wr_data_count[4] = \<const0> ;
assign axi_w_wr_data_count[3] = \<const0> ;
assign axi_w_wr_data_count[2] = \<const0> ;
assign axi_w_wr_data_count[1] = \<const0> ;
assign axi_w_wr_data_count[0] = \<const0> ;
assign axis_data_count[10] = \<const0> ;
assign axis_data_count[9] = \<const0> ;
assign axis_data_count[8] = \<const0> ;
assign axis_data_count[7] = \<const0> ;
assign axis_data_count[6] = \<const0> ;
assign axis_data_count[5] = \<const0> ;
assign axis_data_count[4] = \<const0> ;
assign axis_data_count[3] = \<const0> ;
assign axis_data_count[2] = \<const0> ;
assign axis_data_count[1] = \<const0> ;
assign axis_data_count[0] = \<const0> ;
assign axis_dbiterr = \<const0> ;
assign axis_overflow = \<const0> ;
assign axis_prog_empty = \<const1> ;
assign axis_prog_full = \<const0> ;
assign axis_rd_data_count[10] = \<const0> ;
assign axis_rd_data_count[9] = \<const0> ;
assign axis_rd_data_count[8] = \<const0> ;
assign axis_rd_data_count[7] = \<const0> ;
assign axis_rd_data_count[6] = \<const0> ;
assign axis_rd_data_count[5] = \<const0> ;
assign axis_rd_data_count[4] = \<const0> ;
assign axis_rd_data_count[3] = \<const0> ;
assign axis_rd_data_count[2] = \<const0> ;
assign axis_rd_data_count[1] = \<const0> ;
assign axis_rd_data_count[0] = \<const0> ;
assign axis_sbiterr = \<const0> ;
assign axis_underflow = \<const0> ;
assign axis_wr_data_count[10] = \<const0> ;
assign axis_wr_data_count[9] = \<const0> ;
assign axis_wr_data_count[8] = \<const0> ;
assign axis_wr_data_count[7] = \<const0> ;
assign axis_wr_data_count[6] = \<const0> ;
assign axis_wr_data_count[5] = \<const0> ;
assign axis_wr_data_count[4] = \<const0> ;
assign axis_wr_data_count[3] = \<const0> ;
assign axis_wr_data_count[2] = \<const0> ;
assign axis_wr_data_count[1] = \<const0> ;
assign axis_wr_data_count[0] = \<const0> ;
assign data_count[11] = \<const0> ;
assign data_count[10] = \<const0> ;
assign data_count[9] = \<const0> ;
assign data_count[8] = \<const0> ;
assign data_count[7] = \<const0> ;
assign data_count[6] = \<const0> ;
assign data_count[5] = \<const0> ;
assign data_count[4] = \<const0> ;
assign data_count[3] = \<const0> ;
assign data_count[2] = \<const0> ;
assign data_count[1] = \<const0> ;
assign data_count[0] = \<const0> ;
assign dbiterr = \<const0> ;
assign m_axi_araddr[31] = \<const0> ;
assign m_axi_araddr[30] = \<const0> ;
assign m_axi_araddr[29] = \<const0> ;
assign m_axi_araddr[28] = \<const0> ;
assign m_axi_araddr[27] = \<const0> ;
assign m_axi_araddr[26] = \<const0> ;
assign m_axi_araddr[25] = \<const0> ;
assign m_axi_araddr[24] = \<const0> ;
assign m_axi_araddr[23] = \<const0> ;
assign m_axi_araddr[22] = \<const0> ;
assign m_axi_araddr[21] = \<const0> ;
assign m_axi_araddr[20] = \<const0> ;
assign m_axi_araddr[19] = \<const0> ;
assign m_axi_araddr[18] = \<const0> ;
assign m_axi_araddr[17] = \<const0> ;
assign m_axi_araddr[16] = \<const0> ;
assign m_axi_araddr[15] = \<const0> ;
assign m_axi_araddr[14] = \<const0> ;
assign m_axi_araddr[13] = \<const0> ;
assign m_axi_araddr[12] = \<const0> ;
assign m_axi_araddr[11] = \<const0> ;
assign m_axi_araddr[10] = \<const0> ;
assign m_axi_araddr[9] = \<const0> ;
assign m_axi_araddr[8] = \<const0> ;
assign m_axi_araddr[7] = \<const0> ;
assign m_axi_araddr[6] = \<const0> ;
assign m_axi_araddr[5] = \<const0> ;
assign m_axi_araddr[4] = \<const0> ;
assign m_axi_araddr[3] = \<const0> ;
assign m_axi_araddr[2] = \<const0> ;
assign m_axi_araddr[1] = \<const0> ;
assign m_axi_araddr[0] = \<const0> ;
assign m_axi_arburst[1] = \<const0> ;
assign m_axi_arburst[0] = \<const0> ;
assign m_axi_arcache[3] = \<const0> ;
assign m_axi_arcache[2] = \<const0> ;
assign m_axi_arcache[1] = \<const0> ;
assign m_axi_arcache[0] = \<const0> ;
assign m_axi_arid[0] = \<const0> ;
assign m_axi_arlen[7] = \<const0> ;
assign m_axi_arlen[6] = \<const0> ;
assign m_axi_arlen[5] = \<const0> ;
assign m_axi_arlen[4] = \<const0> ;
assign m_axi_arlen[3] = \<const0> ;
assign m_axi_arlen[2] = \<const0> ;
assign m_axi_arlen[1] = \<const0> ;
assign m_axi_arlen[0] = \<const0> ;
assign m_axi_arlock[0] = \<const0> ;
assign m_axi_arprot[2] = \<const0> ;
assign m_axi_arprot[1] = \<const0> ;
assign m_axi_arprot[0] = \<const0> ;
assign m_axi_arqos[3] = \<const0> ;
assign m_axi_arqos[2] = \<const0> ;
assign m_axi_arqos[1] = \<const0> ;
assign m_axi_arqos[0] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[2] = \<const0> ;
assign m_axi_arsize[1] = \<const0> ;
assign m_axi_arsize[0] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_arvalid = \<const0> ;
assign m_axi_awaddr[31] = \<const0> ;
assign m_axi_awaddr[30] = \<const0> ;
assign m_axi_awaddr[29] = \<const0> ;
assign m_axi_awaddr[28] = \<const0> ;
assign m_axi_awaddr[27] = \<const0> ;
assign m_axi_awaddr[26] = \<const0> ;
assign m_axi_awaddr[25] = \<const0> ;
assign m_axi_awaddr[24] = \<const0> ;
assign m_axi_awaddr[23] = \<const0> ;
assign m_axi_awaddr[22] = \<const0> ;
assign m_axi_awaddr[21] = \<const0> ;
assign m_axi_awaddr[20] = \<const0> ;
assign m_axi_awaddr[19] = \<const0> ;
assign m_axi_awaddr[18] = \<const0> ;
assign m_axi_awaddr[17] = \<const0> ;
assign m_axi_awaddr[16] = \<const0> ;
assign m_axi_awaddr[15] = \<const0> ;
assign m_axi_awaddr[14] = \<const0> ;
assign m_axi_awaddr[13] = \<const0> ;
assign m_axi_awaddr[12] = \<const0> ;
assign m_axi_awaddr[11] = \<const0> ;
assign m_axi_awaddr[10] = \<const0> ;
assign m_axi_awaddr[9] = \<const0> ;
assign m_axi_awaddr[8] = \<const0> ;
assign m_axi_awaddr[7] = \<const0> ;
assign m_axi_awaddr[6] = \<const0> ;
assign m_axi_awaddr[5] = \<const0> ;
assign m_axi_awaddr[4] = \<const0> ;
assign m_axi_awaddr[3] = \<const0> ;
assign m_axi_awaddr[2] = \<const0> ;
assign m_axi_awaddr[1] = \<const0> ;
assign m_axi_awaddr[0] = \<const0> ;
assign m_axi_awburst[1] = \<const0> ;
assign m_axi_awburst[0] = \<const0> ;
assign m_axi_awcache[3] = \<const0> ;
assign m_axi_awcache[2] = \<const0> ;
assign m_axi_awcache[1] = \<const0> ;
assign m_axi_awcache[0] = \<const0> ;
assign m_axi_awid[0] = \<const0> ;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3] = \<const0> ;
assign m_axi_awlen[2] = \<const0> ;
assign m_axi_awlen[1] = \<const0> ;
assign m_axi_awlen[0] = \<const0> ;
assign m_axi_awlock[0] = \<const0> ;
assign m_axi_awprot[2] = \<const0> ;
assign m_axi_awprot[1] = \<const0> ;
assign m_axi_awprot[0] = \<const0> ;
assign m_axi_awqos[3] = \<const0> ;
assign m_axi_awqos[2] = \<const0> ;
assign m_axi_awqos[1] = \<const0> ;
assign m_axi_awqos[0] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[2] = \<const0> ;
assign m_axi_awsize[1] = \<const0> ;
assign m_axi_awsize[0] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_awvalid = \<const0> ;
assign m_axi_bready = \<const0> ;
assign m_axi_rready = \<const0> ;
assign m_axi_wdata[63] = \<const0> ;
assign m_axi_wdata[62] = \<const0> ;
assign m_axi_wdata[61] = \<const0> ;
assign m_axi_wdata[60] = \<const0> ;
assign m_axi_wdata[59] = \<const0> ;
assign m_axi_wdata[58] = \<const0> ;
assign m_axi_wdata[57] = \<const0> ;
assign m_axi_wdata[56] = \<const0> ;
assign m_axi_wdata[55] = \<const0> ;
assign m_axi_wdata[54] = \<const0> ;
assign m_axi_wdata[53] = \<const0> ;
assign m_axi_wdata[52] = \<const0> ;
assign m_axi_wdata[51] = \<const0> ;
assign m_axi_wdata[50] = \<const0> ;
assign m_axi_wdata[49] = \<const0> ;
assign m_axi_wdata[48] = \<const0> ;
assign m_axi_wdata[47] = \<const0> ;
assign m_axi_wdata[46] = \<const0> ;
assign m_axi_wdata[45] = \<const0> ;
assign m_axi_wdata[44] = \<const0> ;
assign m_axi_wdata[43] = \<const0> ;
assign m_axi_wdata[42] = \<const0> ;
assign m_axi_wdata[41] = \<const0> ;
assign m_axi_wdata[40] = \<const0> ;
assign m_axi_wdata[39] = \<const0> ;
assign m_axi_wdata[38] = \<const0> ;
assign m_axi_wdata[37] = \<const0> ;
assign m_axi_wdata[36] = \<const0> ;
assign m_axi_wdata[35] = \<const0> ;
assign m_axi_wdata[34] = \<const0> ;
assign m_axi_wdata[33] = \<const0> ;
assign m_axi_wdata[32] = \<const0> ;
assign m_axi_wdata[31] = \<const0> ;
assign m_axi_wdata[30] = \<const0> ;
assign m_axi_wdata[29] = \<const0> ;
assign m_axi_wdata[28] = \<const0> ;
assign m_axi_wdata[27] = \<const0> ;
assign m_axi_wdata[26] = \<const0> ;
assign m_axi_wdata[25] = \<const0> ;
assign m_axi_wdata[24] = \<const0> ;
assign m_axi_wdata[23] = \<const0> ;
assign m_axi_wdata[22] = \<const0> ;
assign m_axi_wdata[21] = \<const0> ;
assign m_axi_wdata[20] = \<const0> ;
assign m_axi_wdata[19] = \<const0> ;
assign m_axi_wdata[18] = \<const0> ;
assign m_axi_wdata[17] = \<const0> ;
assign m_axi_wdata[16] = \<const0> ;
assign m_axi_wdata[15] = \<const0> ;
assign m_axi_wdata[14] = \<const0> ;
assign m_axi_wdata[13] = \<const0> ;
assign m_axi_wdata[12] = \<const0> ;
assign m_axi_wdata[11] = \<const0> ;
assign m_axi_wdata[10] = \<const0> ;
assign m_axi_wdata[9] = \<const0> ;
assign m_axi_wdata[8] = \<const0> ;
assign m_axi_wdata[7] = \<const0> ;
assign m_axi_wdata[6] = \<const0> ;
assign m_axi_wdata[5] = \<const0> ;
assign m_axi_wdata[4] = \<const0> ;
assign m_axi_wdata[3] = \<const0> ;
assign m_axi_wdata[2] = \<const0> ;
assign m_axi_wdata[1] = \<const0> ;
assign m_axi_wdata[0] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast = \<const0> ;
assign m_axi_wstrb[7] = \<const0> ;
assign m_axi_wstrb[6] = \<const0> ;
assign m_axi_wstrb[5] = \<const0> ;
assign m_axi_wstrb[4] = \<const0> ;
assign m_axi_wstrb[3] = \<const0> ;
assign m_axi_wstrb[2] = \<const0> ;
assign m_axi_wstrb[1] = \<const0> ;
assign m_axi_wstrb[0] = \<const0> ;
assign m_axi_wuser[0] = \<const0> ;
assign m_axi_wvalid = \<const0> ;
assign m_axis_tdata[7] = \<const0> ;
assign m_axis_tdata[6] = \<const0> ;
assign m_axis_tdata[5] = \<const0> ;
assign m_axis_tdata[4] = \<const0> ;
assign m_axis_tdata[3] = \<const0> ;
assign m_axis_tdata[2] = \<const0> ;
assign m_axis_tdata[1] = \<const0> ;
assign m_axis_tdata[0] = \<const0> ;
assign m_axis_tdest[0] = \<const0> ;
assign m_axis_tid[0] = \<const0> ;
assign m_axis_tkeep[0] = \<const0> ;
assign m_axis_tlast = \<const0> ;
assign m_axis_tstrb[0] = \<const0> ;
assign m_axis_tuser[3] = \<const0> ;
assign m_axis_tuser[2] = \<const0> ;
assign m_axis_tuser[1] = \<const0> ;
assign m_axis_tuser[0] = \<const0> ;
assign m_axis_tvalid = \<const0> ;
assign overflow = \<const0> ;
assign prog_empty = \<const0> ;
assign prog_full = \<const0> ;
assign rd_data_count[11] = \<const0> ;
assign rd_data_count[10] = \<const0> ;
assign rd_data_count[9] = \<const0> ;
assign rd_data_count[8] = \<const0> ;
assign rd_data_count[7] = \<const0> ;
assign rd_data_count[6] = \<const0> ;
assign rd_data_count[5] = \<const0> ;
assign rd_data_count[4] = \<const0> ;
assign rd_data_count[3] = \<const0> ;
assign rd_data_count[2] = \<const0> ;
assign rd_data_count[1] = \<const0> ;
assign rd_data_count[0] = \<const0> ;
assign rd_rst_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_rdata[63] = \<const0> ;
assign s_axi_rdata[62] = \<const0> ;
assign s_axi_rdata[61] = \<const0> ;
assign s_axi_rdata[60] = \<const0> ;
assign s_axi_rdata[59] = \<const0> ;
assign s_axi_rdata[58] = \<const0> ;
assign s_axi_rdata[57] = \<const0> ;
assign s_axi_rdata[56] = \<const0> ;
assign s_axi_rdata[55] = \<const0> ;
assign s_axi_rdata[54] = \<const0> ;
assign s_axi_rdata[53] = \<const0> ;
assign s_axi_rdata[52] = \<const0> ;
assign s_axi_rdata[51] = \<const0> ;
assign s_axi_rdata[50] = \<const0> ;
assign s_axi_rdata[49] = \<const0> ;
assign s_axi_rdata[48] = \<const0> ;
assign s_axi_rdata[47] = \<const0> ;
assign s_axi_rdata[46] = \<const0> ;
assign s_axi_rdata[45] = \<const0> ;
assign s_axi_rdata[44] = \<const0> ;
assign s_axi_rdata[43] = \<const0> ;
assign s_axi_rdata[42] = \<const0> ;
assign s_axi_rdata[41] = \<const0> ;
assign s_axi_rdata[40] = \<const0> ;
assign s_axi_rdata[39] = \<const0> ;
assign s_axi_rdata[38] = \<const0> ;
assign s_axi_rdata[37] = \<const0> ;
assign s_axi_rdata[36] = \<const0> ;
assign s_axi_rdata[35] = \<const0> ;
assign s_axi_rdata[34] = \<const0> ;
assign s_axi_rdata[33] = \<const0> ;
assign s_axi_rdata[32] = \<const0> ;
assign s_axi_rdata[31] = \<const0> ;
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_wready = \<const0> ;
assign s_axis_tready = \<const0> ;
assign sbiterr = \<const0> ;
assign underflow = \<const0> ;
assign valid = \<const0> ;
assign wr_ack = \<const0> ;
assign wr_data_count[11] = \<const0> ;
assign wr_data_count[10] = \<const0> ;
assign wr_data_count[9] = \<const0> ;
assign wr_data_count[8] = \<const0> ;
assign wr_data_count[7] = \<const0> ;
assign wr_data_count[6] = \<const0> ;
assign wr_data_count[5] = \<const0> ;
assign wr_data_count[4] = \<const0> ;
assign wr_data_count[3] = \<const0> ;
assign wr_data_count[2] = \<const0> ;
assign wr_data_count[1] = \<const0> ;
assign wr_data_count[0] = \<const0> ;
assign wr_rst_busy = \<const0> ;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
shd_pe_fifo_fifo_generator_v12_0_synth inst_fifo_gen
(.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_en(wr_en));
endmodule
(* ORIG_REF_NAME = "fifo_generator_v12_0_synth" *)
module shd_pe_fifo_fifo_generator_v12_0_synth
(dout,
empty,
full,
wr_en,
wr_clk,
rd_clk,
din,
rst,
rd_en);
output [7:0]dout;
output empty;
output full;
input wr_en;
input wr_clk;
input rd_clk;
input [7:0]din;
input rst;
input rd_en;
wire [7:0]din;
wire [7:0]dout;
wire empty;
wire full;
wire rd_clk;
wire rd_en;
wire rst;
wire wr_clk;
wire wr_en;
shd_pe_fifo_fifo_generator_top \gconvfifo.rf
(.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_en(wr_en));
endmodule
(* ORIG_REF_NAME = "memory" *)
module shd_pe_fifo_memory
(dout,
WEA,
wr_clk,
tmp_ram_rd_en,
rd_clk,
Q,
O1,
I1,
din,
E);
output [7:0]dout;
input [0:0]WEA;
input wr_clk;
input tmp_ram_rd_en;
input rd_clk;
input [0:0]Q;
input [11:0]O1;
input [11:0]I1;
input [7:0]din;
input [0:0]E;
wire [0:0]E;
wire [11:0]I1;
wire [11:0]O1;
wire [0:0]Q;
wire [0:0]WEA;
wire [7:0]din;
wire [7:0]dout;
wire [7:0]doutb;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
shd_pe_fifo_blk_mem_gen_v8_2__parameterized0 \gbm.gbmg.gbmga.ngecc.bmg
(.D(doutb),
.I1(I1),
.O1(O1),
.Q(Q),
.WEA(WEA),
.din(din),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[0]
(.C(rd_clk),
.CE(E),
.D(doutb[0]),
.Q(dout[0]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[1]
(.C(rd_clk),
.CE(E),
.D(doutb[1]),
.Q(dout[1]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[2]
(.C(rd_clk),
.CE(E),
.D(doutb[2]),
.Q(dout[2]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[3]
(.C(rd_clk),
.CE(E),
.D(doutb[3]),
.Q(dout[3]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[4]
(.C(rd_clk),
.CE(E),
.D(doutb[4]),
.Q(dout[4]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[5]
(.C(rd_clk),
.CE(E),
.D(doutb[5]),
.Q(dout[5]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[6]
(.C(rd_clk),
.CE(E),
.D(doutb[6]),
.Q(dout[6]),
.R(Q));
FDRE #(
.INIT(1'b0))
\goreg_bm.dout_i_reg[7]
(.C(rd_clk),
.CE(E),
.D(doutb[7]),
.Q(dout[7]),
.R(Q));
endmodule
(* ORIG_REF_NAME = "rd_bin_cntr" *)
module shd_pe_fifo_rd_bin_cntr
(out,
O1,
sel,
rd_clk,
Q);
output [11:0]out;
output [11:0]O1;
input sel;
input rd_clk;
input [0:0]Q;
wire [11:0]O1;
wire [0:0]Q;
wire \n_0_gc0.count[0]_i_2 ;
wire \n_0_gc0.count_reg[0]_i_1 ;
wire \n_0_gc0.count_reg[10]_i_1 ;
wire \n_0_gc0.count_reg[10]_i_2 ;
wire \n_0_gc0.count_reg[11]_i_1 ;
wire \n_0_gc0.count_reg[1]_i_1 ;
wire \n_0_gc0.count_reg[1]_i_2 ;
wire \n_0_gc0.count_reg[2]_i_1 ;
wire \n_0_gc0.count_reg[2]_i_2 ;
wire \n_0_gc0.count_reg[3]_i_1 ;
wire \n_0_gc0.count_reg[3]_i_2 ;
wire \n_0_gc0.count_reg[4]_i_1 ;
wire \n_0_gc0.count_reg[4]_i_2 ;
wire \n_0_gc0.count_reg[5]_i_1 ;
wire \n_0_gc0.count_reg[5]_i_2 ;
wire \n_0_gc0.count_reg[6]_i_1 ;
wire \n_0_gc0.count_reg[6]_i_2 ;
wire \n_0_gc0.count_reg[7]_i_1 ;
wire \n_0_gc0.count_reg[7]_i_2 ;
wire \n_0_gc0.count_reg[8]_i_1 ;
wire \n_0_gc0.count_reg[8]_i_2 ;
wire \n_0_gc0.count_reg[9]_i_1 ;
wire \n_0_gc0.count_reg[9]_i_2 ;
wire [11:0]out;
wire rd_clk;
wire sel;
wire [3:2]\NLW_gc0.count_reg[9]_i_2_CARRY4_CO_UNCONNECTED ;
wire [3:3]\NLW_gc0.count_reg[9]_i_2_CARRY4_DI_UNCONNECTED ;
LUT1 #(
.INIT(2'h1))
\gc0.count[0]_i_2
(.I0(out[0]),
.O(\n_0_gc0.count[0]_i_2 ));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[0]
(.C(rd_clk),
.CE(sel),
.CLR(Q),
.D(out[0]),
.Q(O1[0]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[10]
(.C(rd_clk),
.CE(sel),
.CLR(Q),
.D(out[10]),
.Q(O1[10]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[11]
(.C(rd_clk),
.CE(sel),
.CLR(Q),
.D(out[11]),
.Q(O1[11]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[1]
(.C(rd_clk),
.CE(sel),
.CLR(Q),
.D(out[1]),
.Q(O1[1]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[2]
(.C(rd_clk),
.CE(sel),
.CLR(Q),
.D(out[2]),
.Q(O1[2]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[3]
(.C(rd_clk),
.CE(sel),
.CLR(Q),
.D(out[3]),
.Q(O1[3]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[4]
(.C(rd_clk),
.CE(sel),
.CLR(Q),
.D(out[4]),
.Q(O1[4]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[5]
(.C(rd_clk),
.CE(sel),
.CLR(Q),
.D(out[5]),
.Q(O1[5]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[6]
(.C(rd_clk),
.CE(sel),
.CLR(Q),
.D(out[6]),
.Q(O1[6]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[7]
(.C(rd_clk),
.CE(sel),
.CLR(Q),
.D(out[7]),
.Q(O1[7]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[8]
(.C(rd_clk),
.CE(sel),
.CLR(Q),
.D(out[8]),
.Q(O1[8]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[9]
(.C(rd_clk),
.CE(sel),
.CLR(Q),
.D(out[9]),
.Q(O1[9]));
FDPE #(
.INIT(1'b1))
\gc0.count_reg[0]
(.C(rd_clk),
.CE(sel),
.D(\n_0_gc0.count_reg[0]_i_1 ),
.PRE(Q),
.Q(out[0]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[10]
(.C(rd_clk),
.CE(sel),
.CLR(Q),
.D(\n_0_gc0.count_reg[10]_i_1 ),
.Q(out[10]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[11]
(.C(rd_clk),
.CE(sel),
.CLR(Q),
.D(\n_0_gc0.count_reg[11]_i_1 ),
.Q(out[11]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[1]
(.C(rd_clk),
.CE(sel),
.CLR(Q),
.D(\n_0_gc0.count_reg[1]_i_1 ),
.Q(out[1]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* XILINX_TRANSFORM_PINMAP = "LO:O" *)
CARRY4 \gc0.count_reg[1]_i_2_CARRY4
(.CI(1'b0),
.CO({\n_0_gc0.count_reg[4]_i_2 ,\n_0_gc0.count_reg[3]_i_2 ,\n_0_gc0.count_reg[2]_i_2 ,\n_0_gc0.count_reg[1]_i_2 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b1}),
.O({\n_0_gc0.count_reg[3]_i_1 ,\n_0_gc0.count_reg[2]_i_1 ,\n_0_gc0.count_reg[1]_i_1 ,\n_0_gc0.count_reg[0]_i_1 }),
.S({out[3:1],\n_0_gc0.count[0]_i_2 }));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[2]
(.C(rd_clk),
.CE(sel),
.CLR(Q),
.D(\n_0_gc0.count_reg[2]_i_1 ),
.Q(out[2]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[3]
(.C(rd_clk),
.CE(sel),
.CLR(Q),
.D(\n_0_gc0.count_reg[3]_i_1 ),
.Q(out[3]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[4]
(.C(rd_clk),
.CE(sel),
.CLR(Q),
.D(\n_0_gc0.count_reg[4]_i_1 ),
.Q(out[4]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[5]
(.C(rd_clk),
.CE(sel),
.CLR(Q),
.D(\n_0_gc0.count_reg[5]_i_1 ),
.Q(out[5]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* XILINX_TRANSFORM_PINMAP = "LO:O" *)
CARRY4 \gc0.count_reg[5]_i_2_CARRY4
(.CI(\n_0_gc0.count_reg[4]_i_2 ),
.CO({\n_0_gc0.count_reg[8]_i_2 ,\n_0_gc0.count_reg[7]_i_2 ,\n_0_gc0.count_reg[6]_i_2 ,\n_0_gc0.count_reg[5]_i_2 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\n_0_gc0.count_reg[7]_i_1 ,\n_0_gc0.count_reg[6]_i_1 ,\n_0_gc0.count_reg[5]_i_1 ,\n_0_gc0.count_reg[4]_i_1 }),
.S(out[7:4]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[6]
(.C(rd_clk),
.CE(sel),
.CLR(Q),
.D(\n_0_gc0.count_reg[6]_i_1 ),
.Q(out[6]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[7]
(.C(rd_clk),
.CE(sel),
.CLR(Q),
.D(\n_0_gc0.count_reg[7]_i_1 ),
.Q(out[7]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[8]
(.C(rd_clk),
.CE(sel),
.CLR(Q),
.D(\n_0_gc0.count_reg[8]_i_1 ),
.Q(out[8]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[9]
(.C(rd_clk),
.CE(sel),
.CLR(Q),
.D(\n_0_gc0.count_reg[9]_i_1 ),
.Q(out[9]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* XILINX_TRANSFORM_PINMAP = "LO:O" *)
CARRY4 \gc0.count_reg[9]_i_2_CARRY4
(.CI(\n_0_gc0.count_reg[8]_i_2 ),
.CO({\NLW_gc0.count_reg[9]_i_2_CARRY4_CO_UNCONNECTED [3:2],\n_0_gc0.count_reg[10]_i_2 ,\n_0_gc0.count_reg[9]_i_2 }),
.CYINIT(1'b0),
.DI({\NLW_gc0.count_reg[9]_i_2_CARRY4_DI_UNCONNECTED [3],1'b0,1'b0,1'b0}),
.O({\n_0_gc0.count_reg[11]_i_1 ,\n_0_gc0.count_reg[10]_i_1 ,\n_0_gc0.count_reg[9]_i_1 ,\n_0_gc0.count_reg[8]_i_1 }),
.S(out[11:8]));
endmodule
(* ORIG_REF_NAME = "rd_fwft" *)
module shd_pe_fifo_rd_fwft
(empty,
tmp_ram_rd_en,
O1,
E,
sel,
rd_clk,
Q,
p_18_out,
rd_en);
output empty;
output tmp_ram_rd_en;
output [1:0]O1;
output [0:0]E;
output sel;
input rd_clk;
input [1:0]Q;
input p_18_out;
input rd_en;
wire [0:0]E;
wire [1:0]O1;
wire [1:0]Q;
wire empty;
wire empty_fwft_fb;
wire empty_fwft_i0;
wire [1:0]next_fwft_state;
wire p_18_out;
wire rd_clk;
wire rd_en;
wire sel;
wire tmp_ram_rd_en;
LUT5 #(
.INIT(32'hBABBBBBB))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2
(.I0(Q[0]),
.I1(p_18_out),
.I2(rd_en),
.I3(O1[0]),
.I4(O1[1]),
.O(tmp_ram_rd_en));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_fb_reg
(.C(rd_clk),
.CE(1'b1),
.D(empty_fwft_i0),
.PRE(Q[1]),
.Q(empty_fwft_fb));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT4 #(
.INIT(16'hBA22))
empty_fwft_i_i_1
(.I0(empty_fwft_fb),
.I1(O1[1]),
.I2(rd_en),
.I3(O1[0]),
.O(empty_fwft_i0));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(empty_fwft_i0),
.PRE(Q[1]),
.Q(empty));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT4 #(
.INIT(16'h00BF))
\gc0.count_d1[11]_i_1
(.I0(rd_en),
.I1(O1[0]),
.I2(O1[1]),
.I3(p_18_out),
.O(sel));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'hA2))
\goreg_bm.dout_i[7]_i_1
(.I0(O1[1]),
.I1(O1[0]),
.I2(rd_en),
.O(E));
LUT3 #(
.INIT(8'hBA))
\gpregsm1.curr_fwft_state[0]_i_1
(.I0(O1[1]),
.I1(rd_en),
.I2(O1[0]),
.O(next_fwft_state[0]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT4 #(
.INIT(16'h40FF))
\gpregsm1.curr_fwft_state[1]_i_1
(.I0(rd_en),
.I1(O1[0]),
.I2(O1[1]),
.I3(p_18_out),
.O(next_fwft_state[1]));
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.curr_fwft_state_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(Q[1]),
.D(next_fwft_state[0]),
.Q(O1[0]));
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.curr_fwft_state_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(Q[1]),
.D(next_fwft_state[1]),
.Q(O1[1]));
endmodule
(* ORIG_REF_NAME = "rd_logic" *)
module shd_pe_fifo_rd_logic
(empty,
O1,
tmp_ram_rd_en,
E,
rd_clk,
Q,
WR_PNTR_RD,
rd_en);
output empty;
output [11:0]O1;
output tmp_ram_rd_en;
output [0:0]E;
input rd_clk;
input [1:0]Q;
input [11:0]WR_PNTR_RD;
input rd_en;
wire [0:0]E;
wire [11:0]O1;
wire [1:0]Q;
wire [11:0]WR_PNTR_RD;
wire [0:0]curr_fwft_state;
wire empty;
wire \n_2_gr1.rfwft ;
wire p_14_out;
wire p_18_out;
wire rd_clk;
wire rd_en;
wire [11:0]rd_pntr_plus1;
wire tmp_ram_rd_en;
shd_pe_fifo_rd_fwft \gr1.rfwft
(.E(E),
.O1({\n_2_gr1.rfwft ,curr_fwft_state}),
.Q(Q),
.empty(empty),
.p_18_out(p_18_out),
.rd_clk(rd_clk),
.rd_en(rd_en),
.sel(p_14_out),
.tmp_ram_rd_en(tmp_ram_rd_en));
shd_pe_fifo_rd_status_flags_as \gras.rsts
(.I1({\n_2_gr1.rfwft ,curr_fwft_state}),
.O1(O1),
.Q(Q[1]),
.WR_PNTR_RD(WR_PNTR_RD),
.out(rd_pntr_plus1),
.p_18_out(p_18_out),
.rd_clk(rd_clk),
.rd_en(rd_en));
shd_pe_fifo_rd_bin_cntr rpntr
(.O1(O1),
.Q(Q[1]),
.out(rd_pntr_plus1),
.rd_clk(rd_clk),
.sel(p_14_out));
endmodule
(* ORIG_REF_NAME = "rd_status_flags_as" *)
module shd_pe_fifo_rd_status_flags_as
(p_18_out,
rd_clk,
Q,
WR_PNTR_RD,
O1,
out,
rd_en,
I1);
output p_18_out;
input rd_clk;
input [0:0]Q;
input [11:0]WR_PNTR_RD;
input [11:0]O1;
input [11:0]out;
input rd_en;
input [1:0]I1;
wire [1:0]I1;
wire [11:0]O1;
wire [0:0]Q;
wire [11:0]WR_PNTR_RD;
wire comp0;
wire comp1;
wire n_0_ram_empty_fb_i_i_1;
wire [11:0]out;
wire p_18_out;
wire rd_clk;
wire rd_en;
shd_pe_fifo_compare_1 c0
(.O1(O1),
.WR_PNTR_RD(WR_PNTR_RD),
.comp0(comp0));
shd_pe_fifo_compare_2 c1
(.WR_PNTR_RD(WR_PNTR_RD),
.comp1(comp1),
.out(out));
LUT6 #(
.INIT(64'hAAAAEFFFAAAAAAAA))
ram_empty_fb_i_i_1
(.I0(comp0),
.I1(rd_en),
.I2(I1[0]),
.I3(I1[1]),
.I4(p_18_out),
.I5(comp1),
.O(n_0_ram_empty_fb_i_i_1));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_fb_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(n_0_ram_empty_fb_i_i_1),
.PRE(Q),
.Q(p_18_out));
endmodule
(* ORIG_REF_NAME = "reset_blk_ramfifo" *)
module shd_pe_fifo_reset_blk_ramfifo
(rst_d2,
rst_full_gen_i,
Q,
O1,
wr_clk,
rst,
rd_clk);
output rst_d2;
output rst_full_gen_i;
output [1:0]Q;
output [2:0]O1;
input wr_clk;
input rst;
input rd_clk;
wire [2:0]O1;
wire [1:0]Q;
wire \n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1 ;
wire \n_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1 ;
wire rd_clk;
wire rd_rst_asreg;
wire rd_rst_asreg_d1;
wire rd_rst_asreg_d2;
wire rst;
wire rst_d1;
wire rst_d2;
wire rst_d3;
wire rst_full_gen_i;
wire wr_clk;
wire wr_rst_asreg;
wire wr_rst_asreg_d1;
wire wr_rst_asreg_d2;
FDCE #(
.INIT(1'b0))
\grstd1.grst_full.grst_f.RST_FULL_GEN_reg
(.C(wr_clk),
.CE(1'b1),
.CLR(rst),
.D(rst_d3),
.Q(rst_full_gen_i));
(* ASYNC_REG *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d1_reg
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst),
.Q(rst_d1));
(* ASYNC_REG *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d2_reg
(.C(wr_clk),
.CE(1'b1),
.D(rst_d1),
.PRE(rst),
.Q(rst_d2));
(* ASYNC_REG *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d3_reg
(.C(wr_clk),
.CE(1'b1),
.D(rst_d2),
.PRE(rst),
.Q(rst_d3));
(* ASYNC_REG *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg
(.C(rd_clk),
.CE(1'b1),
.D(rd_rst_asreg),
.Q(rd_rst_asreg_d1),
.R(1'b0));
(* ASYNC_REG *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg
(.C(rd_clk),
.CE(1'b1),
.D(rd_rst_asreg_d1),
.Q(rd_rst_asreg_d2),
.R(1'b0));
(* ASYNC_REG *)
(* msgon = "true" *)
FDPE \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg
(.C(rd_clk),
.CE(rd_rst_asreg_d1),
.D(1'b0),
.PRE(rst),
.Q(rd_rst_asreg));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1
(.I0(rd_rst_asreg),
.I1(rd_rst_asreg_d2),
.O(\n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1 ));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1 ),
.Q(O1[0]));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1 ),
.Q(O1[1]));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1 ),
.Q(O1[2]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg
(.C(wr_clk),
.CE(1'b1),
.D(wr_rst_asreg),
.Q(wr_rst_asreg_d1),
.R(1'b0));
(* ASYNC_REG *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg
(.C(wr_clk),
.CE(1'b1),
.D(wr_rst_asreg_d1),
.Q(wr_rst_asreg_d2),
.R(1'b0));
(* ASYNC_REG *)
(* msgon = "true" *)
FDPE \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg
(.C(wr_clk),
.CE(wr_rst_asreg_d1),
.D(1'b0),
.PRE(rst),
.Q(wr_rst_asreg));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1
(.I0(wr_rst_asreg),
.I1(wr_rst_asreg_d2),
.O(\n_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1 ));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\n_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1 ),
.Q(Q[0]));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\n_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1 ),
.Q(Q[1]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module shd_pe_fifo_synchronizer_ff
(Q,
I1,
rd_clk,
I3);
output [11:0]Q;
input [11:0]I1;
input rd_clk;
input [0:0]I3;
wire [11:0]I1;
wire [0:0]I3;
wire [11:0]Q;
wire rd_clk;
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(I1[0]),
.Q(Q[0]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[10]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(I1[10]),
.Q(Q[10]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[11]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(I1[11]),
.Q(Q[11]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(I1[1]),
.Q(Q[1]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(I1[2]),
.Q(Q[2]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(I1[3]),
.Q(Q[3]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(I1[4]),
.Q(Q[4]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(I1[5]),
.Q(Q[5]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(I1[6]),
.Q(Q[6]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(I1[7]),
.Q(Q[7]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(I1[8]),
.Q(Q[8]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(I1[9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module shd_pe_fifo_synchronizer_ff_3
(Q,
I1,
wr_clk,
I2);
output [11:0]Q;
input [11:0]I1;
input wr_clk;
input [0:0]I2;
wire [11:0]I1;
wire [0:0]I2;
wire [11:0]Q;
wire wr_clk;
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(I1[0]),
.Q(Q[0]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[10]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(I1[10]),
.Q(Q[10]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[11]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(I1[11]),
.Q(Q[11]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(I1[1]),
.Q(Q[1]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(I1[2]),
.Q(Q[2]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(I1[3]),
.Q(Q[3]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(I1[4]),
.Q(Q[4]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(I1[5]),
.Q(Q[5]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(I1[6]),
.Q(Q[6]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(I1[7]),
.Q(Q[7]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(I1[8]),
.Q(Q[8]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[9]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(I1[9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module shd_pe_fifo_synchronizer_ff_4
(p_0_in,
D,
rd_clk,
I3);
output [11:0]p_0_in;
input [11:0]D;
input rd_clk;
input [0:0]I3;
wire [11:0]D;
wire [0:0]I3;
wire \n_0_Q_reg_reg[0] ;
wire \n_0_Q_reg_reg[10] ;
wire \n_0_Q_reg_reg[1] ;
wire \n_0_Q_reg_reg[2] ;
wire \n_0_Q_reg_reg[3] ;
wire \n_0_Q_reg_reg[4] ;
wire \n_0_Q_reg_reg[5] ;
wire \n_0_Q_reg_reg[6] ;
wire \n_0_Q_reg_reg[7] ;
wire \n_0_Q_reg_reg[8] ;
wire \n_0_Q_reg_reg[9] ;
wire [11:0]p_0_in;
wire rd_clk;
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(D[0]),
.Q(\n_0_Q_reg_reg[0] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[10]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(D[10]),
.Q(\n_0_Q_reg_reg[10] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[11]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(D[11]),
.Q(p_0_in[11]));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(D[1]),
.Q(\n_0_Q_reg_reg[1] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(D[2]),
.Q(\n_0_Q_reg_reg[2] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(D[3]),
.Q(\n_0_Q_reg_reg[3] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(D[4]),
.Q(\n_0_Q_reg_reg[4] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(D[5]),
.Q(\n_0_Q_reg_reg[5] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(D[6]),
.Q(\n_0_Q_reg_reg[6] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(D[7]),
.Q(\n_0_Q_reg_reg[7] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(D[8]),
.Q(\n_0_Q_reg_reg[8] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(I3),
.D(D[9]),
.Q(\n_0_Q_reg_reg[9] ));
LUT4 #(
.INIT(16'h6996))
\wr_pntr_bin[0]_i_1
(.I0(\n_0_Q_reg_reg[2] ),
.I1(\n_0_Q_reg_reg[1] ),
.I2(\n_0_Q_reg_reg[0] ),
.I3(p_0_in[3]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_bin[10]_i_1
(.I0(\n_0_Q_reg_reg[10] ),
.I1(p_0_in[11]),
.O(p_0_in[10]));
LUT6 #(
.INIT(64'h6996966996696996))
\wr_pntr_bin[1]_i_1
(.I0(\n_0_Q_reg_reg[2] ),
.I1(\n_0_Q_reg_reg[1] ),
.I2(\n_0_Q_reg_reg[3] ),
.I3(\n_0_Q_reg_reg[5] ),
.I4(p_0_in[6]),
.I5(\n_0_Q_reg_reg[4] ),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h96696996))
\wr_pntr_bin[2]_i_1
(.I0(\n_0_Q_reg_reg[3] ),
.I1(\n_0_Q_reg_reg[5] ),
.I2(p_0_in[6]),
.I3(\n_0_Q_reg_reg[4] ),
.I4(\n_0_Q_reg_reg[2] ),
.O(p_0_in[2]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h6996))
\wr_pntr_bin[3]_i_1
(.I0(\n_0_Q_reg_reg[4] ),
.I1(p_0_in[6]),
.I2(\n_0_Q_reg_reg[5] ),
.I3(\n_0_Q_reg_reg[3] ),
.O(p_0_in[3]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'h96))
\wr_pntr_bin[4]_i_1
(.I0(\n_0_Q_reg_reg[5] ),
.I1(p_0_in[6]),
.I2(\n_0_Q_reg_reg[4] ),
.O(p_0_in[4]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_bin[5]_i_1
(.I0(p_0_in[6]),
.I1(\n_0_Q_reg_reg[5] ),
.O(p_0_in[5]));
LUT6 #(
.INIT(64'h6996966996696996))
\wr_pntr_bin[6]_i_1
(.I0(\n_0_Q_reg_reg[7] ),
.I1(p_0_in[11]),
.I2(\n_0_Q_reg_reg[9] ),
.I3(\n_0_Q_reg_reg[10] ),
.I4(\n_0_Q_reg_reg[8] ),
.I5(\n_0_Q_reg_reg[6] ),
.O(p_0_in[6]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h96696996))
\wr_pntr_bin[7]_i_1
(.I0(\n_0_Q_reg_reg[8] ),
.I1(\n_0_Q_reg_reg[10] ),
.I2(\n_0_Q_reg_reg[9] ),
.I3(p_0_in[11]),
.I4(\n_0_Q_reg_reg[7] ),
.O(p_0_in[7]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h6996))
\wr_pntr_bin[8]_i_1
(.I0(p_0_in[11]),
.I1(\n_0_Q_reg_reg[9] ),
.I2(\n_0_Q_reg_reg[10] ),
.I3(\n_0_Q_reg_reg[8] ),
.O(p_0_in[8]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'h96))
\wr_pntr_bin[9]_i_1
(.I0(\n_0_Q_reg_reg[10] ),
.I1(\n_0_Q_reg_reg[9] ),
.I2(p_0_in[11]),
.O(p_0_in[9]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module shd_pe_fifo_synchronizer_ff_5
(Q,
O1,
D,
wr_clk,
I2);
output [0:0]Q;
output [10:0]O1;
input [11:0]D;
input wr_clk;
input [0:0]I2;
wire [11:0]D;
wire [0:0]I2;
wire [10:0]O1;
wire [0:0]Q;
wire \n_0_Q_reg_reg[0] ;
wire \n_0_Q_reg_reg[10] ;
wire \n_0_Q_reg_reg[1] ;
wire \n_0_Q_reg_reg[2] ;
wire \n_0_Q_reg_reg[3] ;
wire \n_0_Q_reg_reg[4] ;
wire \n_0_Q_reg_reg[5] ;
wire \n_0_Q_reg_reg[6] ;
wire \n_0_Q_reg_reg[7] ;
wire \n_0_Q_reg_reg[8] ;
wire \n_0_Q_reg_reg[9] ;
wire wr_clk;
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(D[0]),
.Q(\n_0_Q_reg_reg[0] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[10]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(D[10]),
.Q(\n_0_Q_reg_reg[10] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[11]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(D[11]),
.Q(Q));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(D[1]),
.Q(\n_0_Q_reg_reg[1] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(D[2]),
.Q(\n_0_Q_reg_reg[2] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(D[3]),
.Q(\n_0_Q_reg_reg[3] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(D[4]),
.Q(\n_0_Q_reg_reg[4] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(D[5]),
.Q(\n_0_Q_reg_reg[5] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(D[6]),
.Q(\n_0_Q_reg_reg[6] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(D[7]),
.Q(\n_0_Q_reg_reg[7] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(D[8]),
.Q(\n_0_Q_reg_reg[8] ));
(* ASYNC_REG *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[9]
(.C(wr_clk),
.CE(1'b1),
.CLR(I2),
.D(D[9]),
.Q(\n_0_Q_reg_reg[9] ));
LUT4 #(
.INIT(16'h6996))
\rd_pntr_bin[0]_i_1
(.I0(\n_0_Q_reg_reg[2] ),
.I1(\n_0_Q_reg_reg[1] ),
.I2(\n_0_Q_reg_reg[0] ),
.I3(O1[3]),
.O(O1[0]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_bin[10]_i_1
(.I0(\n_0_Q_reg_reg[10] ),
.I1(Q),
.O(O1[10]));
LUT6 #(
.INIT(64'h6996966996696996))
\rd_pntr_bin[1]_i_1
(.I0(\n_0_Q_reg_reg[2] ),
.I1(\n_0_Q_reg_reg[1] ),
.I2(\n_0_Q_reg_reg[3] ),
.I3(\n_0_Q_reg_reg[5] ),
.I4(O1[6]),
.I5(\n_0_Q_reg_reg[4] ),
.O(O1[1]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h96696996))
\rd_pntr_bin[2]_i_1
(.I0(\n_0_Q_reg_reg[3] ),
.I1(\n_0_Q_reg_reg[5] ),
.I2(O1[6]),
.I3(\n_0_Q_reg_reg[4] ),
.I4(\n_0_Q_reg_reg[2] ),
.O(O1[2]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h6996))
\rd_pntr_bin[3]_i_1
(.I0(\n_0_Q_reg_reg[4] ),
.I1(O1[6]),
.I2(\n_0_Q_reg_reg[5] ),
.I3(\n_0_Q_reg_reg[3] ),
.O(O1[3]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'h96))
\rd_pntr_bin[4]_i_1
(.I0(\n_0_Q_reg_reg[5] ),
.I1(O1[6]),
.I2(\n_0_Q_reg_reg[4] ),
.O(O1[4]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_bin[5]_i_1
(.I0(O1[6]),
.I1(\n_0_Q_reg_reg[5] ),
.O(O1[5]));
LUT6 #(
.INIT(64'h6996966996696996))
\rd_pntr_bin[6]_i_1
(.I0(\n_0_Q_reg_reg[7] ),
.I1(Q),
.I2(\n_0_Q_reg_reg[9] ),
.I3(\n_0_Q_reg_reg[10] ),
.I4(\n_0_Q_reg_reg[8] ),
.I5(\n_0_Q_reg_reg[6] ),
.O(O1[6]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'h96696996))
\rd_pntr_bin[7]_i_1
(.I0(\n_0_Q_reg_reg[8] ),
.I1(\n_0_Q_reg_reg[10] ),
.I2(\n_0_Q_reg_reg[9] ),
.I3(Q),
.I4(\n_0_Q_reg_reg[7] ),
.O(O1[7]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h6996))
\rd_pntr_bin[8]_i_1
(.I0(Q),
.I1(\n_0_Q_reg_reg[9] ),
.I2(\n_0_Q_reg_reg[10] ),
.I3(\n_0_Q_reg_reg[8] ),
.O(O1[8]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'h96))
\rd_pntr_bin[9]_i_1
(.I0(\n_0_Q_reg_reg[10] ),
.I1(\n_0_Q_reg_reg[9] ),
.I2(Q),
.O(O1[9]));
endmodule
(* ORIG_REF_NAME = "wr_bin_cntr" *)
module shd_pe_fifo_wr_bin_cntr
(out,
Q,
O1,
sel,
wr_clk,
I1);
output [11:0]out;
output [11:0]Q;
output [11:0]O1;
input sel;
input wr_clk;
input [0:0]I1;
wire [0:0]I1;
wire [11:0]O1;
wire [11:0]Q;
wire \n_0_gic0.gc0.count[0]_i_2 ;
wire \n_0_gic0.gc0.count_reg[0]_i_1 ;
wire \n_0_gic0.gc0.count_reg[10]_i_1 ;
wire \n_0_gic0.gc0.count_reg[10]_i_2 ;
wire \n_0_gic0.gc0.count_reg[11]_i_1 ;
wire \n_0_gic0.gc0.count_reg[1]_i_1 ;
wire \n_0_gic0.gc0.count_reg[1]_i_2 ;
wire \n_0_gic0.gc0.count_reg[2]_i_1 ;
wire \n_0_gic0.gc0.count_reg[2]_i_2 ;
wire \n_0_gic0.gc0.count_reg[3]_i_1 ;
wire \n_0_gic0.gc0.count_reg[3]_i_2 ;
wire \n_0_gic0.gc0.count_reg[4]_i_1 ;
wire \n_0_gic0.gc0.count_reg[4]_i_2 ;
wire \n_0_gic0.gc0.count_reg[5]_i_1 ;
wire \n_0_gic0.gc0.count_reg[5]_i_2 ;
wire \n_0_gic0.gc0.count_reg[6]_i_1 ;
wire \n_0_gic0.gc0.count_reg[6]_i_2 ;
wire \n_0_gic0.gc0.count_reg[7]_i_1 ;
wire \n_0_gic0.gc0.count_reg[7]_i_2 ;
wire \n_0_gic0.gc0.count_reg[8]_i_1 ;
wire \n_0_gic0.gc0.count_reg[8]_i_2 ;
wire \n_0_gic0.gc0.count_reg[9]_i_1 ;
wire \n_0_gic0.gc0.count_reg[9]_i_2 ;
wire [11:0]out;
wire sel;
wire wr_clk;
wire [3:2]\NLW_gic0.gc0.count_reg[9]_i_2_CARRY4_CO_UNCONNECTED ;
wire [3:3]\NLW_gic0.gc0.count_reg[9]_i_2_CARRY4_DI_UNCONNECTED ;
LUT1 #(
.INIT(2'h1))
\gic0.gc0.count[0]_i_2
(.I0(out[0]),
.O(\n_0_gic0.gc0.count[0]_i_2 ));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_d1_reg[0]
(.C(wr_clk),
.CE(sel),
.D(out[0]),
.PRE(I1),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[10]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(out[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[11]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(out[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[1]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(out[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[2]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(out[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[3]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(out[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[4]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(out[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[5]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(out[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[6]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(out[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[7]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(out[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[8]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(out[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[9]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(out[9]),
.Q(Q[9]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[0]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(Q[0]),
.Q(O1[0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[10]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(Q[10]),
.Q(O1[10]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[11]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(Q[11]),
.Q(O1[11]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[1]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(Q[1]),
.Q(O1[1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[2]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(Q[2]),
.Q(O1[2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[3]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(Q[3]),
.Q(O1[3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[4]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(Q[4]),
.Q(O1[4]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[5]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(Q[5]),
.Q(O1[5]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[6]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(Q[6]),
.Q(O1[6]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[7]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(Q[7]),
.Q(O1[7]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[8]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(Q[8]),
.Q(O1[8]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[9]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(Q[9]),
.Q(O1[9]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[0]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(\n_0_gic0.gc0.count_reg[0]_i_1 ),
.Q(out[0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[10]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(\n_0_gic0.gc0.count_reg[10]_i_1 ),
.Q(out[10]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[11]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(\n_0_gic0.gc0.count_reg[11]_i_1 ),
.Q(out[11]));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_reg[1]
(.C(wr_clk),
.CE(sel),
.D(\n_0_gic0.gc0.count_reg[1]_i_1 ),
.PRE(I1),
.Q(out[1]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* XILINX_TRANSFORM_PINMAP = "LO:O" *)
CARRY4 \gic0.gc0.count_reg[1]_i_2_CARRY4
(.CI(1'b0),
.CO({\n_0_gic0.gc0.count_reg[4]_i_2 ,\n_0_gic0.gc0.count_reg[3]_i_2 ,\n_0_gic0.gc0.count_reg[2]_i_2 ,\n_0_gic0.gc0.count_reg[1]_i_2 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b1}),
.O({\n_0_gic0.gc0.count_reg[3]_i_1 ,\n_0_gic0.gc0.count_reg[2]_i_1 ,\n_0_gic0.gc0.count_reg[1]_i_1 ,\n_0_gic0.gc0.count_reg[0]_i_1 }),
.S({out[3:1],\n_0_gic0.gc0.count[0]_i_2 }));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[2]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(\n_0_gic0.gc0.count_reg[2]_i_1 ),
.Q(out[2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[3]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(\n_0_gic0.gc0.count_reg[3]_i_1 ),
.Q(out[3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[4]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(\n_0_gic0.gc0.count_reg[4]_i_1 ),
.Q(out[4]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[5]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(\n_0_gic0.gc0.count_reg[5]_i_1 ),
.Q(out[5]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* XILINX_TRANSFORM_PINMAP = "LO:O" *)
CARRY4 \gic0.gc0.count_reg[5]_i_2_CARRY4
(.CI(\n_0_gic0.gc0.count_reg[4]_i_2 ),
.CO({\n_0_gic0.gc0.count_reg[8]_i_2 ,\n_0_gic0.gc0.count_reg[7]_i_2 ,\n_0_gic0.gc0.count_reg[6]_i_2 ,\n_0_gic0.gc0.count_reg[5]_i_2 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\n_0_gic0.gc0.count_reg[7]_i_1 ,\n_0_gic0.gc0.count_reg[6]_i_1 ,\n_0_gic0.gc0.count_reg[5]_i_1 ,\n_0_gic0.gc0.count_reg[4]_i_1 }),
.S(out[7:4]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[6]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(\n_0_gic0.gc0.count_reg[6]_i_1 ),
.Q(out[6]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[7]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(\n_0_gic0.gc0.count_reg[7]_i_1 ),
.Q(out[7]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[8]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(\n_0_gic0.gc0.count_reg[8]_i_1 ),
.Q(out[8]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[9]
(.C(wr_clk),
.CE(sel),
.CLR(I1),
.D(\n_0_gic0.gc0.count_reg[9]_i_1 ),
.Q(out[9]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* XILINX_TRANSFORM_PINMAP = "LO:O" *)
CARRY4 \gic0.gc0.count_reg[9]_i_2_CARRY4
(.CI(\n_0_gic0.gc0.count_reg[8]_i_2 ),
.CO({\NLW_gic0.gc0.count_reg[9]_i_2_CARRY4_CO_UNCONNECTED [3:2],\n_0_gic0.gc0.count_reg[10]_i_2 ,\n_0_gic0.gc0.count_reg[9]_i_2 }),
.CYINIT(1'b0),
.DI({\NLW_gic0.gc0.count_reg[9]_i_2_CARRY4_DI_UNCONNECTED [3],1'b0,1'b0,1'b0}),
.O({\n_0_gic0.gc0.count_reg[11]_i_1 ,\n_0_gic0.gc0.count_reg[10]_i_1 ,\n_0_gic0.gc0.count_reg[9]_i_1 ,\n_0_gic0.gc0.count_reg[8]_i_1 }),
.S(out[11:8]));
endmodule
(* ORIG_REF_NAME = "wr_logic" *)
module shd_pe_fifo_wr_logic
(full,
WEA,
O1,
wr_clk,
rst_d2,
wr_en,
Q,
RD_PNTR_WR,
rst_full_gen_i);
output full;
output [0:0]WEA;
output [11:0]O1;
input wr_clk;
input rst_d2;
input wr_en;
input [0:0]Q;
input [11:0]RD_PNTR_WR;
input rst_full_gen_i;
wire [11:0]O1;
wire [0:0]Q;
wire [11:0]RD_PNTR_WR;
wire [0:0]WEA;
wire full;
wire [11:0]p_8_out;
wire rst_d2;
wire rst_full_gen_i;
wire wr_clk;
wire wr_en;
wire [11:0]wr_pntr_plus2;
shd_pe_fifo_wr_status_flags_as \gwas.wsts
(.Q(p_8_out),
.RD_PNTR_WR(RD_PNTR_WR),
.full(full),
.out(wr_pntr_plus2),
.rst_d2(rst_d2),
.rst_full_gen_i(rst_full_gen_i),
.sel(WEA),
.wr_clk(wr_clk),
.wr_en(wr_en));
shd_pe_fifo_wr_bin_cntr wpntr
(.I1(Q),
.O1(O1),
.Q(p_8_out),
.out(wr_pntr_plus2),
.sel(WEA),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "wr_status_flags_as" *)
module shd_pe_fifo_wr_status_flags_as
(full,
sel,
wr_clk,
rst_d2,
wr_en,
Q,
RD_PNTR_WR,
out,
rst_full_gen_i);
output full;
output sel;
input wr_clk;
input rst_d2;
input wr_en;
input [11:0]Q;
input [11:0]RD_PNTR_WR;
input [11:0]out;
input rst_full_gen_i;
wire [11:0]Q;
wire [11:0]RD_PNTR_WR;
wire comp1;
wire comp2;
wire full;
wire [11:0]out;
wire p_0_out;
wire ram_full_i;
wire rst_d2;
wire rst_full_gen_i;
wire sel;
wire wr_clk;
wire wr_en;
LUT2 #(
.INIT(4'h2))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1
(.I0(wr_en),
.I1(p_0_out),
.O(sel));
shd_pe_fifo_compare c1
(.Q(Q),
.RD_PNTR_WR(RD_PNTR_WR),
.comp1(comp1));
shd_pe_fifo_compare_0 c2
(.RD_PNTR_WR(RD_PNTR_WR),
.comp2(comp2),
.out(out));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_fb_i_reg
(.C(wr_clk),
.CE(1'b1),
.D(ram_full_i),
.PRE(rst_d2),
.Q(p_0_out));
LUT5 #(
.INIT(32'h55550400))
ram_full_i_i_1
(.I0(rst_full_gen_i),
.I1(comp2),
.I2(p_0_out),
.I3(wr_en),
.I4(comp1),
.O(ram_full_i));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_i_reg
(.C(wr_clk),
.CE(1'b1),
.D(ram_full_i),
.PRE(rst_d2),
.Q(full));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/***************************************************************************************************
** fpga_nes/hw/src/hci/hci.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Host communication interface. Accepts packets over a serial connection, interacts with the rest
* of the hw system as specified, and returns the specified data.
***************************************************************************************************/
module hci
(
input wire clk, // 100MHz system clock signal
input wire rst, // reset signal
input wire rx, // rs-232 rx signal
input wire brk, // signal for cpu-intiated debug break
input wire [ 7:0] cpu_din, // cpu data bus (D) [input]
input wire [ 7:0] cpu_dbgreg_in, // cpu debug register read bus
input wire [ 7:0] ppu_vram_din, // ppu data bus [input]
output wire tx, // rs-232 tx signal
output wire active, // dbg block is active (disable CPU)
output reg cpu_r_nw, // cpu R/!W pin
output wire [15:0] cpu_a, // cpu A bus (A)
output reg [ 7:0] cpu_dout, // cpu data bus (D) [output]
output reg [ 3:0] cpu_dbgreg_sel, // selects cpu register to read/write through cpu_dbgreg_in
output reg [ 7:0] cpu_dbgreg_out, // cpu register write value for debug reg writes
output reg cpu_dbgreg_wr, // selects cpu register read/write mode
output reg ppu_vram_wr, // ppu memory write enable signal
output wire [15:0] ppu_vram_a, // ppu memory address
output wire [ 7:0] ppu_vram_dout, // ppu data bus [output]
output wire [39:0] cart_cfg, // cartridge config data (from iNES header)
output wire cart_cfg_upd // pulse on cart_cfg update so cart can reset
);
// Debug packet opcodes.
localparam [7:0] OP_ECHO = 8'h00,
OP_CPU_MEM_RD = 8'h01,
OP_CPU_MEM_WR = 8'h02,
OP_DBG_BRK = 8'h03,
OP_DBG_RUN = 8'h04,
OP_CPU_REG_RD = 8'h05,
OP_CPU_REG_WR = 8'h06,
OP_QUERY_DBG_BRK = 8'h07,
OP_QUERY_ERR_CODE = 8'h08,
OP_PPU_MEM_RD = 8'h09,
OP_PPU_MEM_WR = 8'h0A,
OP_PPU_DISABLE = 8'h0B,
OP_CART_SET_CFG = 8'h0C;
// Error code bit positions.
localparam DBG_UART_PARITY_ERR = 0,
DBG_UNKNOWN_OPCODE = 1;
// Symbolic state representations.
localparam [4:0] S_DISABLED = 5'h00,
S_DECODE = 5'h01,
S_ECHO_STG_0 = 5'h02,
S_ECHO_STG_1 = 5'h03,
S_CPU_MEM_RD_STG_0 = 5'h04,
S_CPU_MEM_RD_STG_1 = 5'h05,
S_CPU_MEM_WR_STG_0 = 5'h06,
S_CPU_MEM_WR_STG_1 = 5'h07,
S_CPU_REG_RD = 5'h08,
S_CPU_REG_WR_STG_0 = 5'h09,
S_CPU_REG_WR_STG_1 = 5'h0A,
S_QUERY_ERR_CODE = 5'h0B,
S_PPU_MEM_RD_STG_0 = 5'h0C,
S_PPU_MEM_RD_STG_1 = 5'h0D,
S_PPU_MEM_WR_STG_0 = 5'h0E,
S_PPU_MEM_WR_STG_1 = 5'h0F,
S_PPU_DISABLE = 5'h10,
S_CART_SET_CFG_STG_0 = 5'h11,
S_CART_SET_CFG_STG_1 = 5'h12;
reg [ 4:0] q_state, d_state;
reg [ 2:0] q_decode_cnt, d_decode_cnt;
reg [16:0] q_execute_cnt, d_execute_cnt;
reg [15:0] q_addr, d_addr;
reg [ 1:0] q_err_code, d_err_code;
reg [39:0] q_cart_cfg, d_cart_cfg;
reg q_cart_cfg_upd, d_cart_cfg_upd;
// UART output buffer FFs.
reg [7:0] q_tx_data, d_tx_data;
reg q_wr_en, d_wr_en;
// UART input signals.
reg rd_en;
wire [7:0] rd_data;
wire rx_empty;
wire tx_full;
wire parity_err;
// Update FF state.
always @(posedge clk)
begin
if (rst)
begin
q_state <= S_DECODE;
q_decode_cnt <= 0;
q_execute_cnt <= 0;
q_addr <= 16'h0000;
q_err_code <= 0;
q_cart_cfg <= 40'h0000000000;
q_cart_cfg_upd <= 1'b0;
q_tx_data <= 8'h00;
q_wr_en <= 1'b0;
end
else
begin
q_state <= d_state;
q_decode_cnt <= d_decode_cnt;
q_execute_cnt <= d_execute_cnt;
q_addr <= d_addr;
q_err_code <= d_err_code;
q_cart_cfg <= d_cart_cfg;
q_cart_cfg_upd <= d_cart_cfg_upd;
q_tx_data <= d_tx_data;
q_wr_en <= d_wr_en;
end
end
// Instantiate the serial controller block.
uart #(.SYS_CLK_FREQ(100000000),
.BAUD_RATE(38400),
.DATA_BITS(8),
.STOP_BITS(1),
.PARITY_MODE(1)) uart_blk
(
.clk(clk),
.reset(rst),
.rx(rx),
.tx_data(q_tx_data),
.rd_en(rd_en),
.wr_en(q_wr_en),
.tx(tx),
.rx_data(rd_data),
.rx_empty(rx_empty),
.tx_full(tx_full),
.parity_err(parity_err)
);
always @*
begin
// Setup default FF updates.
d_state = q_state;
d_decode_cnt = q_decode_cnt;
d_execute_cnt = q_execute_cnt;
d_addr = q_addr;
d_err_code = q_err_code;
d_cart_cfg = q_cart_cfg;
d_cart_cfg_upd = 1'b0;
rd_en = 1'b0;
d_tx_data = 8'h00;
d_wr_en = 1'b0;
// Setup default output regs.
cpu_r_nw = 1'b1;
cpu_dout = rd_data;
cpu_dbgreg_sel = 0;
cpu_dbgreg_out = 0;
cpu_dbgreg_wr = 1'b0;
ppu_vram_wr = 1'b0;
if (parity_err)
d_err_code[DBG_UART_PARITY_ERR] = 1'b1;
case (q_state)
S_DISABLED:
begin
if (brk)
begin
// Received CPU initiated break. Begin active debugging.
d_state = S_DECODE;
end
else if (!rx_empty)
begin
rd_en = 1'b1; // pop opcode off uart fifo
if (rd_data == OP_DBG_BRK)
begin
d_state = S_DECODE;
end
else if (rd_data == OP_QUERY_DBG_BRK)
begin
d_tx_data = 8'h00; // Write "0" over UART to indicate we are not in a debug break
d_wr_en = 1'b1;
end
end
end
S_DECODE:
begin
if (!rx_empty)
begin
rd_en = 1'b1; // pop opcode off uart fifo
d_decode_cnt = 0; // start decode count at 0 for decode stage
// Move to appropriate decode stage based on opcode.
case (rd_data)
OP_ECHO: d_state = S_ECHO_STG_0;
OP_CPU_MEM_RD: d_state = S_CPU_MEM_RD_STG_0;
OP_CPU_MEM_WR: d_state = S_CPU_MEM_WR_STG_0;
OP_DBG_BRK: d_state = S_DECODE;
OP_CPU_REG_RD: d_state = S_CPU_REG_RD;
OP_CPU_REG_WR: d_state = S_CPU_REG_WR_STG_0;
OP_QUERY_ERR_CODE: d_state = S_QUERY_ERR_CODE;
OP_PPU_MEM_RD: d_state = S_PPU_MEM_RD_STG_0;
OP_PPU_MEM_WR: d_state = S_PPU_MEM_WR_STG_0;
OP_PPU_DISABLE: d_state = S_PPU_DISABLE;
OP_CART_SET_CFG: d_state = S_CART_SET_CFG_STG_0;
OP_DBG_RUN:
begin
d_state = S_DISABLED;
end
OP_QUERY_DBG_BRK:
begin
d_tx_data = 8'h01; // Write "1" over UART to indicate we are in a debug break
d_wr_en = 1'b1;
end
default:
begin
// Invalid opcode. Ignore, but set error code.
d_err_code[DBG_UNKNOWN_OPCODE] = 1'b1;
d_state = S_DECODE;
end
endcase
end
end
// --- ECHO ---
// OP_CODE
// CNT_LO
// CNT_HI
// DATA
S_ECHO_STG_0:
begin
if (!rx_empty)
begin
rd_en = 1'b1; // pop packet byte off uart fifo
d_decode_cnt = q_decode_cnt + 3'h1; // advance to next decode stage
if (q_decode_cnt == 0)
begin
// Read CNT_LO into low bits of execute count.
d_execute_cnt = rd_data;
end
else
begin
// Read CNT_HI into high bits of execute count.
d_execute_cnt = { rd_data, q_execute_cnt[7:0] };
d_state = (d_execute_cnt) ? S_ECHO_STG_1 : S_DECODE;
end
end
end
S_ECHO_STG_1:
begin
if (!rx_empty)
begin
rd_en = 1'b1; // pop packet byte off uart fifo
d_execute_cnt = q_execute_cnt - 17'h00001; // advance to next execute stage
// Echo packet DATA byte over uart.
d_tx_data = rd_data;
d_wr_en = 1'b1;
// After last byte of packet, return to decode stage.
if (d_execute_cnt == 0)
d_state = S_DECODE;
end
end
// --- CPU_MEM_RD ---
// OP_CODE
// ADDR_LO
// ADDR_HI
// CNT_LO
// CNT_HI
S_CPU_MEM_RD_STG_0:
begin
if (!rx_empty)
begin
rd_en = 1'b1; // pop packet byte off uart fifo
d_decode_cnt = q_decode_cnt + 3'h1; // advance to next decode stage
if (q_decode_cnt == 0)
begin
// Read ADDR_LO into low bits of addr.
d_addr = rd_data;
end
else if (q_decode_cnt == 1)
begin
// Read ADDR_HI into high bits of addr.
d_addr = { rd_data, q_addr[7:0] };
end
else if (q_decode_cnt == 2)
begin
// Read CNT_LO into low bits of execute count.
d_execute_cnt = rd_data;
end
else
begin
// Read CNT_HI into high bits of execute count. Execute count is shifted by 1:
// use 2 clock cycles per byte read.
d_execute_cnt = { rd_data, q_execute_cnt[7:0], 1'b0 };
d_state = (d_execute_cnt) ? S_CPU_MEM_RD_STG_1 : S_DECODE;
end
end
end
S_CPU_MEM_RD_STG_1:
begin
if (~q_execute_cnt[0])
begin
// Dummy cycle. Allow memory read 1 cycle to return result, and allow uart tx fifo
// 1 cycle to update tx_full setting.
d_execute_cnt = q_execute_cnt - 17'h00001;
end
else
begin
if (!tx_full)
begin
d_execute_cnt = q_execute_cnt - 17'h00001; // advance to next execute stage
d_tx_data = cpu_din; // write data from cpu D bus
d_wr_en = 1'b1; // request uart write
d_addr = q_addr + 16'h0001; // advance to next byte
// After last byte is written to uart, return to decode stage.
if (d_execute_cnt == 0)
d_state = S_DECODE;
end
end
end
// --- CPU_MEM_WR ---
// OP_CODE
// ADDR_LO
// ADDR_HI
// CNT_LO
// CNT_HI
// DATA
S_CPU_MEM_WR_STG_0:
begin
if (!rx_empty)
begin
rd_en = 1'b1; // pop packet byte off uart fifo
d_decode_cnt = q_decode_cnt + 3'h1; // advance to next decode stage
if (q_decode_cnt == 0)
begin
// Read ADDR_LO into low bits of addr.
d_addr = rd_data;
end
else if (q_decode_cnt == 1)
begin
// Read ADDR_HI into high bits of addr.
d_addr = { rd_data, q_addr[7:0] };
end
else if (q_decode_cnt == 2)
begin
// Read CNT_LO into low bits of execute count.
d_execute_cnt = rd_data;
end
else
begin
// Read CNT_HI into high bits of execute count.
d_execute_cnt = { rd_data, q_execute_cnt[7:0] };
d_state = (d_execute_cnt) ? S_CPU_MEM_WR_STG_1 : S_DECODE;
end
end
end
S_CPU_MEM_WR_STG_1:
begin
if (!rx_empty)
begin
rd_en = 1'b1; // pop packet byte off uart fifo
d_execute_cnt = q_execute_cnt - 17'h00001; // advance to next execute stage
d_addr = q_addr + 16'h0001; // advance to next byte
cpu_r_nw = 1'b0;
// After last byte is written to memory, return to decode stage.
if (d_execute_cnt == 0)
d_state = S_DECODE;
end
end
// --- CPU_REG_RD ---
// OP_CODE
// REG_SEL
S_CPU_REG_RD:
begin
if (!rx_empty && !tx_full)
begin
rd_en = 1'b1; // pop REG_SEL byte off uart fifo
cpu_dbgreg_sel = rd_data[3:0]; // select CPU reg based on REG_SEL
d_tx_data = cpu_dbgreg_in; // send reg read results to uart
d_wr_en = 1'b1; // request uart write
d_state = S_DECODE;
end
end
// --- CPU_REG_WR ---
// OP_CODE
// REG_SEL
// DATA
S_CPU_REG_WR_STG_0:
begin
if (!rx_empty)
begin
rd_en = 1'b1;
d_addr = rd_data;
d_state = S_CPU_REG_WR_STG_1;
end
end
S_CPU_REG_WR_STG_1:
begin
if (!rx_empty)
begin
rd_en = 1'b1;
cpu_dbgreg_sel = q_addr[3:0];
cpu_dbgreg_wr = 1'b1;
cpu_dbgreg_out = rd_data;
d_state = S_DECODE;
end
end
// --- QUERY_ERR_CODE ---
// OP_CODE
S_QUERY_ERR_CODE:
begin
if (!tx_full)
begin
d_tx_data = q_err_code; // write current error code
d_wr_en = 1'b1; // request uart write
d_state = S_DECODE;
end
end
// --- PPU_MEM_RD ---
// OP_CODE
// ADDR_LO
// ADDR_HI
// CNT_LO
// CNT_HI
S_PPU_MEM_RD_STG_0:
begin
if (!rx_empty)
begin
rd_en = 1'b1; // pop packet byte off uart fifo
d_decode_cnt = q_decode_cnt + 3'h1; // advance to next decode stage
if (q_decode_cnt == 0)
begin
// Read ADDR_LO into low bits of addr.
d_addr = rd_data;
end
else if (q_decode_cnt == 1)
begin
// Read ADDR_HI into high bits of addr.
d_addr = { rd_data, q_addr[7:0] };
end
else if (q_decode_cnt == 2)
begin
// Read CNT_LO into low bits of execute count.
d_execute_cnt = rd_data;
end
else
begin
// Read CNT_HI into high bits of execute count. Execute count is shifted by 1:
// use 2 clock cycles per byte read.
d_execute_cnt = { rd_data, q_execute_cnt[7:0], 1'b0 };
d_state = (d_execute_cnt) ? S_PPU_MEM_RD_STG_1 : S_DECODE;
end
end
end
S_PPU_MEM_RD_STG_1:
begin
if (~q_execute_cnt[0])
begin
// Dummy cycle. Allow memory read 1 cycle to return result, and allow uart tx fifo
// 1 cycle to update tx_full setting.
d_execute_cnt = q_execute_cnt - 17'h00001;
end
else
begin
if (!tx_full)
begin
d_execute_cnt = q_execute_cnt - 17'h00001; // advance to next execute stage
d_tx_data = ppu_vram_din; // write data from ppu D bus
d_wr_en = 1'b1; // request uart write
d_addr = q_addr + 16'h0001; // advance to next byte
// After last byte is written to uart, return to decode stage.
if (d_execute_cnt == 0)
d_state = S_DECODE;
end
end
end
// --- PPU_MEM_WR ---
// OP_CODE
// ADDR_LO
// ADDR_HI
// CNT_LO
// CNT_HI
// DATA
S_PPU_MEM_WR_STG_0:
begin
if (!rx_empty)
begin
rd_en = 1'b1; // pop packet byte off uart fifo
d_decode_cnt = q_decode_cnt + 3'h1; // advance to next decode stage
if (q_decode_cnt == 0)
begin
// Read ADDR_LO into low bits of addr.
d_addr = rd_data;
end
else if (q_decode_cnt == 1)
begin
// Read ADDR_HI into high bits of addr.
d_addr = { rd_data, q_addr[7:0] };
end
else if (q_decode_cnt == 2)
begin
// Read CNT_LO into low bits of execute count.
d_execute_cnt = rd_data;
end
else
begin
// Read CNT_HI into high bits of execute count.
d_execute_cnt = { rd_data, q_execute_cnt[7:0] };
d_state = (d_execute_cnt) ? S_PPU_MEM_WR_STG_1 : S_DECODE;
end
end
end
S_PPU_MEM_WR_STG_1:
begin
if (!rx_empty)
begin
rd_en = 1'b1; // pop packet byte off uart fifo
d_execute_cnt = q_execute_cnt - 17'h00001; // advance to next execute stage
d_addr = q_addr + 16'h0001; // advance to next byte
ppu_vram_wr = 1'b1;
// After last byte is written to memory, return to decode stage.
if (d_execute_cnt == 0)
d_state = S_DECODE;
end
end
// --- PPU_DISABLE ---
// OP_CODE
S_PPU_DISABLE:
begin
d_decode_cnt = q_decode_cnt + 3'h1; // advance to next decode stage
if (q_decode_cnt == 0)
begin
d_addr = 16'h2000;
end
else if (q_decode_cnt == 1)
begin
// Write 0x2000 to 0.
cpu_r_nw = 1'b0;
cpu_dout = 8'h00;
// Set addr to 0x0000 for one cycle (due to PPU quirk only recognizing register
// interface reads/writes when address bits [15-13] change from 3'b001 from another
// value.
d_addr = 16'h0000;
end
else if (q_decode_cnt == 2)
begin
d_addr = 16'h2001;
end
else if (q_decode_cnt == 3)
begin
// Write 0x2000 to 0.
cpu_r_nw = 1'b0;
cpu_dout = 8'h00;
// Set addr to 0x0000 for one cycle (due to PPU quirk only recognizing register
// interface reads/writes when address bits [15-13] change from 3'b001 from another
// value.
d_addr = 16'h0000;
end
else if (q_decode_cnt == 4)
begin
d_addr = 16'h2002;
end
else if (q_decode_cnt == 5)
begin
// Read 0x2002 to reset PPU byte pointer.
d_addr = 16'h0000;
d_state = S_DECODE;
end
end
// --- CART_SET_CFG ---
// OP_CODE
// iNES byte 4 (16KB PRG-ROM bank count)
// iNES byte 5 (8KB CHR-ROM bank count)
// iNES byte 6 (ROM Control Byte 1)
// iNES byte 7 (ROM Control Byte 2)
// iNES byte 8 (8KB RAM bank count)
S_CART_SET_CFG_STG_0:
begin
d_execute_cnt = 16'h0004;
d_state = S_CART_SET_CFG_STG_1;
end
S_CART_SET_CFG_STG_1:
begin
if (!rx_empty)
begin
rd_en = 1'b1; // pop packet byte off uart fifo
d_execute_cnt = q_execute_cnt - 17'h00001; // advance to next execute stage
d_cart_cfg = { q_cart_cfg[31:0], rd_data };
// After last byte of packet, return to decode stage.
if (q_execute_cnt == 0)
begin
d_state = S_DECODE;
d_cart_cfg_upd = 1'b1;
end
end
end
endcase
end
assign cpu_a = q_addr;
assign active = (q_state != S_DISABLED);
assign ppu_vram_a = q_addr;
assign ppu_vram_dout = rd_data;
assign cart_cfg = q_cart_cfg;
assign cart_cfg_upd = q_cart_cfg_upd;
endmodule
|
module s27 (
G1,
G2,
clk_net,
reset_net,
G3,
G0,
G17);
// Start PIs
input G1;
input G2;
input clk_net;
input reset_net;
input G3;
input G0;
// Start POs
output G17;
// Start wires
wire G1;
wire net_5;
wire net_15;
wire net_27;
wire G17;
wire reset_net;
wire net_14;
wire G3;
wire net_26;
wire clk_net;
wire net_13;
wire G2;
wire net_19;
wire net_3;
wire net_22;
wire net_16;
wire net_6;
wire net_24;
wire net_11;
wire net_1;
wire net_23;
wire net_18;
wire net_12;
wire net_2;
wire net_10;
wire net_8;
wire net_9;
wire net_25;
wire net_21;
wire net_7;
wire net_20;
wire G0;
wire net_4;
wire net_17;
// Start cells
CLKBUF_X2 inst_19 ( .A(net_17), .Z(net_18) );
DFFR_X2 inst_14 ( .RN(net_12), .D(net_10), .QN(net_3), .CK(net_27) );
INV_X1 inst_12 ( .A(net_16), .ZN(G17) );
INV_X4 inst_8 ( .ZN(net_5), .A(net_1) );
NOR2_X4 inst_2 ( .ZN(net_11), .A2(net_9), .A1(net_6) );
NOR2_X4 inst_1 ( .A1(net_14), .ZN(net_8), .A2(G3) );
CLKBUF_X2 inst_21 ( .A(net_19), .Z(net_20) );
CLKBUF_X2 inst_25 ( .A(net_23), .Z(net_24) );
NAND2_X2 inst_7 ( .ZN(net_7), .A1(net_4), .A2(net_3) );
CLKBUF_X2 inst_20 ( .A(net_18), .Z(net_19) );
INV_X1 inst_13 ( .ZN(net_12), .A(reset_net) );
CLKBUF_X2 inst_27 ( .A(net_25), .Z(net_26) );
CLKBUF_X2 inst_26 ( .A(net_17), .Z(net_25) );
NOR3_X4 inst_0 ( .ZN(net_16), .A1(net_11), .A3(net_8), .A2(net_5) );
CLKBUF_X2 inst_18 ( .A(clk_net), .Z(net_17) );
DFFR_X2 inst_15 ( .D(net_16), .RN(net_12), .QN(net_2), .CK(net_19) );
DFFR_X2 inst_16 ( .D(net_13), .RN(net_12), .QN(net_1), .CK(net_24) );
CLKBUF_X2 inst_24 ( .A(net_22), .Z(net_23) );
NOR2_X2 inst_3 ( .ZN(net_14), .A1(net_2), .A2(G0) );
NOR2_X2 inst_6 ( .A1(net_16), .A2(net_15), .ZN(net_13) );
INV_X4 inst_9 ( .ZN(net_9), .A(net_7) );
NOR2_X2 inst_5 ( .ZN(net_10), .A2(net_9), .A1(G2) );
INV_X2 inst_10 ( .ZN(net_4), .A(G1) );
NOR2_X2 inst_4 ( .ZN(net_6), .A1(net_2), .A2(G0) );
CLKBUF_X2 inst_23 ( .A(net_21), .Z(net_22) );
INV_X2 inst_11 ( .ZN(net_15), .A(G0) );
CLKBUF_X2 inst_28 ( .A(net_26), .Z(net_27) );
CLKBUF_X2 inst_22 ( .A(net_20), .Z(net_21) );
endmodule
|
// Copyright 2012 by Alastair M. Robinson
//
// This file is part of Minimig
//
// Minimig is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3 of the License, or
// (at your option) any later version.
//
// Minimig is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//
// A minimal implementation of the Akiko C2P register - 16-bit for now, worry about 32-bit
// width later.
//
// -- AMR --
//
// 2012-03-23 - initial version
module akiko
(
input clk,
input reset,
input [23:1] address_in,
input [15:0] data_in,
output [15:0] data_out,
input rd,
input sel_akiko // $B8xxxx
);
//0xb80038 - just the one register, but 32-bits wide.
reg [127:0] shifter;
reg [6:0] wrpointer;
wire sel;
// address decoding
assign sel = sel_akiko && address_in[7:1]==8'b0011_100; // 0x38
always @(posedge clk)
if (reset)
wrpointer <= 0;
else if (!rd && sel) // write to C2P reg...
begin
case(wrpointer)
0 : shifter[127:112] <= data_in[15:0];
1 : shifter[111:96] <= data_in[15:0];
2 : shifter[95:80] <= data_in[15:0];
3 : shifter[79:64] <= data_in[15:0];
4 : shifter[63:48] <= data_in[15:0];
5 : shifter[47:32] <= data_in[15:0];
6 : shifter[31:16] <= data_in[15:0];
7 : shifter[15:0] <= data_in[15:0];
endcase
wrpointer <= wrpointer + 1;
end
else if (rd && sel) // read from C2P reg
begin
shifter[127:0] <= {shifter[126:0],1'b0};
wrpointer <= 0;
end
assign data_out[15:0] = sel_akiko && rd ? {shifter[127],shifter[119],shifter[111],shifter[103],shifter[95],shifter[87],
shifter[79],shifter[71],shifter[63],shifter[55],shifter[47],shifter[39],shifter[31],
shifter[23],shifter[15],shifter[7]} : 16'b0 ;
endmodule
|
// ======================================================================
// DES encryption/decryption
// algorithm according:FIPS 46-3 specification
// Copyright (C) 2012 Torsten Meissner
//-----------------------------------------------------------------------
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write:the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
// ======================================================================
`timescale 1ns/1ps
module des
(
input reset_i, // async reset
input clk_i, // clock
input mode_i, // des-mode: 0 = encrypt, 1 = decrypt
input [0:63] key_i, // key input
input [0:63] data_i, // data input
input valid_i, // input key/data valid flag
output reg [0:63] data_o, // data output
output valid_o // output data valid flag
);
`include "../../rtl/verilog/des_pkg.v"
// valid, mode register
reg [0:18] valid;
reg [0:17] mode;
// algorithm pipeline register
// key calculation register
reg [0:27] c0;
reg [0:27] c1;
reg [0:27] c2;
reg [0:27] c3;
reg [0:27] c4;
reg [0:27] c5;
reg [0:27] c6;
reg [0:27] c7;
reg [0:27] c8;
reg [0:27] c9;
reg [0:27] c10;
reg [0:27] c11;
reg [0:27] c12;
reg [0:27] c13;
reg [0:27] c14;
reg [0:27] c15;
reg [0:27] c16;
reg [0:27] d0;
reg [0:27] d1;
reg [0:27] d2;
reg [0:27] d3;
reg [0:27] d4;
reg [0:27] d5;
reg [0:27] d6;
reg [0:27] d7;
reg [0:27] d8;
reg [0:27] d9;
reg [0:27] d10;
reg [0:27] d11;
reg [0:27] d12;
reg [0:27] d13;
reg [0:27] d14;
reg [0:27] d15;
reg [0:27] d16;
// key register
wire [0:47] key1;
wire [0:47] key2;
wire [0:47] key3;
wire [0:47] key4;
wire [0:47] key5;
wire [0:47] key6;
wire [0:47] key7;
wire [0:47] key8;
wire [0:47] key9;
wire [0:47] key10;
wire [0:47] key11;
wire [0:47] key12;
wire [0:47] key13;
wire [0:47] key14;
wire [0:47] key15;
wire [0:47] key16;
// register for left, right data blocks
reg [0:31] l;
reg [0:31] l0;
reg [0:31] l1;
reg [0:31] l2;
reg [0:31] l3;
reg [0:31] l4;
reg [0:31] l5;
reg [0:31] l6;
reg [0:31] l7;
reg [0:31] l8;
reg [0:31] l9;
reg [0:31] l10;
reg [0:31] l11;
reg [0:31] l12;
reg [0:31] l13;
reg [0:31] l14;
reg [0:31] l15;
reg [0:31] l16;
reg [0:31] r;
reg [0:31] r0;
reg [0:31] r1;
reg [0:31] r2;
reg [0:31] r3;
reg [0:31] r4;
reg [0:31] r5;
reg [0:31] r6;
reg [0:31] r7;
reg [0:31] r8;
reg [0:31] r9;
reg [0:31] r10;
reg [0:31] r11;
reg [0:31] r12;
reg [0:31] r13;
reg [0:31] r14;
reg [0:31] r15;
reg [0:31] r16;
wire valid_o = valid[18];
// valid, mode register
always @(posedge clk_i, negedge reset_i) begin
if(~reset_i) begin
valid <= 0;
mode <= 0;
end
else begin
// shift registers
valid[1:18] <= valid[0:17];
valid[0] <= valid_i;
mode[1:17] <= mode[0:16];
mode[0] <= mode_i;
end
end
// des algorithm pipeline
always @(posedge clk_i, negedge reset_i) begin
if(~reset_i) begin
l <= 0;
r <= 0;
l0 <= 0;
l1 <= 0;
l2 <= 0;
l3 <= 0;
l4 <= 0;
l5 <= 0;
l6 <= 0;
l7 <= 0;
l8 <= 0;
l9 <= 0;
l10 <= 0;
l11 <= 0;
l12 <= 0;
l13 <= 0;
l14 <= 0;
l15 <= 0;
l16 <= 0;
r0 <= 0;
r1 <= 0;
r2 <= 0;
r3 <= 0;
r4 <= 0;
r5 <= 0;
r6 <= 0;
r7 <= 0;
r8 <= 0;
r9 <= 0;
r10 <= 0;
r11 <= 0;
r12 <= 0;
r13 <= 0;
r14 <= 0;
r15 <= 0;
r16 <= 0;
data_o <= 0;
end
else begin
// output stage
data_o <= ipn({r16, l16});
// 16. stage
l16 <= r15;
r16 <= l15 ^ (f(r15, key16));
// 15. stage
l15 <= r14;
r15 <= l14 ^ (f(r14, key15));
// 14. stage
l14 <= r13;
r14 <= l13 ^ (f(r13, key14));
// 13. stage
l13 <= r12;
r13 <= l12 ^ (f(r12, key13));
// 12. stage
l12 <= r11;
r12 <= l11 ^ (f(r11, key12));
// 11. stage
l11 <= r10;
r11 <= l10 ^ (f(r10, key11));
// 10. stage
l10 <= r9;
r10 <= l9 ^ (f(r9, key10));
// 9. stage
l9 <= r8;
r9 <= l8 ^ (f(r8, key9));
// 8. stage
l8 <= r7;
r8 <= l7 ^ (f(r7, key8));
// 7. stage
l7 <= r6;
r7 <= l6 ^ (f(r6, key7));
// 6. stage
l6 <= r5;
r6 <= l5 ^ (f(r5, key6));
// 5. stage
l5 <= r4;
r5 <= l4 ^ (f(r4, key5));
// 4. stage
l4 <= r3;
r4 <= l3 ^ (f(r3, key4));
// 3. stage
l3 <= r2;
r3 <= l2 ^ (f(r2, key3));
// 2. stage
l2 <= r1;
r2 <= l1 ^ (f(r1, key2));
// 1. stage
l1 <= r0;
r1 <= l0 ^ (f(r0, key1));
// 1. state
l0 <= l;
r0 <= r;
// input stage
l <= ip0(data_i);
r <= ip1(data_i);
end
end
// des key pipeline
always @(posedge clk_i, negedge reset_i) begin
if(~reset_i) begin
c0 <= 0;
c1 <= 0;
c2 <= 0;
c3 <= 0;
c4 <= 0;
c5 <= 0;
c6 <= 0;
c7 <= 0;
c8 <= 0;
c9 <= 0;
c10 <= 0;
c11 <= 0;
c12 <= 0;
c13 <= 0;
c14 <= 0;
c15 <= 0;
c16 <= 0;
d0 <= 0;
d1 <= 0;
d2 <= 0;
d3 <= 0;
d4 <= 0;
d5 <= 0;
d6 <= 0;
d7 <= 0;
d8 <= 0;
d9 <= 0;
d10 <= 0;
d11 <= 0;
d12 <= 0;
d13 <= 0;
d14 <= 0;
d15 <= 0;
d16 <= 0;
end
else begin
// input stage
c0 <= pc1_c(key_i);
d0 <= pc1_d(key_i);
// 1st stage
if (~mode[0]) begin
c1 <= {c0[1:27], c0[0]};
d1 <= {d0[1:27], d0[0]};
end
else begin
c1 <= c0;
d1 <= d0;
end
// 2nd stage
if (~mode[1]) begin
c2 <= {c1[1:27], c1[0]};
d2 <= {d1[1:27], d1[0]};
end
else begin
c2 <= {c1[27], c1[0:26]};
d2 <= {d1[27], d1[0:26]};
end
// 3rd stage
if (~mode[2]) begin
c3 <= {c2[2:27], c2[0:1]};
d3 <= {d2[2:27], d2[0:1]};
end
else begin
c3 <= {c2[26:27], c2[0:25]};
d3 <= {d2[26:27], d2[0:25]};
end
// 4th stage
if (~mode[3]) begin
c4 <= {c3[2:27], c3[0:1]};
d4 <= {d3[2:27], d3[0:1]};
end
else begin
c4 <= {c3[26:27], c3[0:25]};
d4 <= {d3[26:27], d3[0:25]};
end
// 5th stage
if (~mode[4]) begin
c5 <= {c4[2:27], c4[0:1]};
d5 <= {d4[2:27], d4[0:1]};
end
else begin
c5 <= {c4[26:27], c4[0:25]};
d5 <= {d4[26:27], d4[0:25]};
end
// 6. stage
if (~mode[5]) begin
c6 <= {c5[2:27], c5[0:1]};
d6 <= {d5[2:27], d5[0:1]};
end
else begin
c6 <= {c5[26:27], c5[0:25]};
d6 <= {d5[26:27], d5[0:25]};
end
// 7. stage
if (~mode[6]) begin
c7 <= {c6[2:27], c6[0:1]};
d7 <= {d6[2:27], d6[0:1]};
end
else begin
c7 <= {c6[26:27], c6[0:25]};
d7 <= {d6[26:27], d6[0:25]};
end
// 8. stage
if (~mode[7]) begin
c8 <= {c7[2:27], c7[0:1]};
d8 <= {d7[2:27], d7[0:1]};
end
else begin
c8 <= {c7[26:27], c7[0:25]};
d8 <= {d7[26:27], d7[0:25]};
end
// 9. stage
if (~mode[8]) begin
c9 <= {c8[1:27], c8[0]};
d9 <= {d8[1:27], d8[0]};
end
else begin
c9 <= {c8[27], c8[0:26]};
d9 <= {d8[27], d8[0:26]};
end
// 10. stage
if (~mode[9]) begin
c10 <= {c9[2:27], c9[0:1]};
d10 <= {d9[2:27], d9[0:1]};
end
else begin
c10 <= {c9[26:27], c9[0:25]};
d10 <= {d9[26:27], d9[0:25]};
end
// 6. stage
if (~mode[10]) begin
c11 <= {c10[2:27], c10[0:1]};
d11 <= {d10[2:27], d10[0:1]};
end
else begin
c11 <= {c10[26:27], c10[0:25]};
d11 <= {d10[26:27], d10[0:25]};
end
// 6. stage
if (~mode[11]) begin
c12 <= {c11[2:27], c11[0:1]};
d12 <= {d11[2:27], d11[0:1]};
end
else begin
c12 <= {c11[26:27], c11[0:25]};
d12 <= {d11[26:27], d11[0:25]};
end
// 6. stage
if (~mode[12]) begin
c13 <= {c12[2:27], c12[0:1]};
d13 <= {d12[2:27], d12[0:1]};
end
else begin
c13 <= {c12[26:27], c12[0:25]};
d13 <= {d12[26:27], d12[0:25]};
end
// 6. stage
if (~mode[13]) begin
c14 <= {c13[2:27], c13[0:1]};
d14 <= {d13[2:27], d13[0:1]};
end
else begin
c14 <= {c13[26:27], c13[0:25]};
d14 <= {d13[26:27], d13[0:25]};
end
// 6. stage
if (~mode[14]) begin
c15 <= {c14[2:27], c14[0:1]};
d15 <= {d14[2:27], d14[0:1]};
end
else begin
c15 <= {c14[26:27], c14[0:25]};
d15 <= {d14[26:27], d14[0:25]};
end
// 6. stage
if (~mode[15]) begin
c16 <= {c15[1:27], c15[0]};
d16 <= {d15[1:27], d15[0]};
end
else begin
c16 <= {c15[27], c15[0:26]};
d16 <= {d15[27], d15[0:26]};
end
end
end
// key assignments
assign key1 = pc2({c1, d1});
assign key2 = pc2({c2, d2});
assign key3 = pc2({c3, d3});
assign key4 = pc2({c4, d4});
assign key5 = pc2({c5, d5});
assign key6 = pc2({c6, d6});
assign key7 = pc2({c7, d7});
assign key8 = pc2({c8, d8});
assign key9 = pc2({c9, d9});
assign key10 = pc2({c10, d10});
assign key11 = pc2({c11, d11});
assign key12 = pc2({c12, d12});
assign key13 = pc2({c13, d13});
assign key14 = pc2({c14, d14});
assign key15 = pc2({c15, d15});
assign key16 = pc2({c16, d16});
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
(* use_dsp48 = "yes" *) module matrix_mult_mac_mbkb_DSP48_0(
input clk,
input rst,
input ce,
input [8 - 1:0] in0,
input [8 - 1:0] in1,
input [16 - 1:0] in2,
output [16 - 1:0] dout);
wire signed [25 - 1:0] a;
wire signed [18 - 1:0] b;
wire signed [48 - 1:0] c;
wire signed [43 - 1:0] m;
wire signed [48 - 1:0] p;
reg signed [43 - 1:0] m_reg;
reg signed [25 - 1:0] a_reg;
reg signed [18 - 1:0] b_reg;
assign a = $signed(in0);
assign b = $signed(in1);
assign c = $unsigned(in2);
assign m = a_reg * b_reg;
assign p = m_reg + c;
always @(posedge clk) begin
if (ce) begin
m_reg <= m;
a_reg <= a;
b_reg <= b;
end
end
assign dout = p;
endmodule
`timescale 1 ns / 1 ps
module matrix_mult_mac_mbkb(
clk,
reset,
ce,
din0,
din1,
din2,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter din2_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[din2_WIDTH - 1:0] din2;
output[dout_WIDTH - 1:0] dout;
matrix_mult_mac_mbkb_DSP48_0 matrix_mult_mac_mbkb_DSP48_0_U(
.clk( clk ),
.rst( reset ),
.ce( ce ),
.in0( din0 ),
.in1( din1 ),
.in2( din2 ),
.dout( dout ));
endmodule
|
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_b2s_aw_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of ID signals.
// Range: >= 1.
parameter integer C_ID_WIDTH = 4,
// Width of AxADDR
// Range: 32.
parameter integer C_AXI_ADDR_WIDTH = 32
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// AXI Slave Interface
// Slave Interface System Signals
input wire clk ,
input wire reset ,
// Slave Interface Write Address Ports
input wire [C_ID_WIDTH-1:0] s_awid ,
input wire [C_AXI_ADDR_WIDTH-1:0] s_awaddr ,
input wire [7:0] s_awlen ,
input wire [2:0] s_awsize ,
input wire [1:0] s_awburst ,
input wire s_awvalid ,
output wire s_awready ,
output wire m_awvalid ,
output wire [C_AXI_ADDR_WIDTH-1:0] m_awaddr ,
input wire m_awready ,
// Connections to/from axi_protocol_converter_v2_1_b2s_b_channel module
output wire b_push ,
output wire [C_ID_WIDTH-1:0] b_awid ,
output wire [7:0] b_awlen ,
input wire b_full
);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
wire next ;
wire next_pending ;
wire a_push;
wire incr_burst;
reg [C_ID_WIDTH-1:0] s_awid_r;
reg [7:0] s_awlen_r;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// Translate the AXI transaction to the MC transaction(s)
axi_protocol_converter_v2_1_b2s_cmd_translator #
(
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH )
)
cmd_translator_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.s_axaddr ( s_awaddr ) ,
.s_axlen ( s_awlen ) ,
.s_axsize ( s_awsize ) ,
.s_axburst ( s_awburst ) ,
.s_axhandshake ( s_awvalid & a_push ) ,
.m_axaddr ( m_awaddr ) ,
.incr_burst ( incr_burst ) ,
.next ( next ) ,
.next_pending ( next_pending )
);
axi_protocol_converter_v2_1_b2s_wr_cmd_fsm aw_cmd_fsm_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.s_awready ( s_awready ) ,
.s_awvalid ( s_awvalid ) ,
.m_awvalid ( m_awvalid ) ,
.m_awready ( m_awready ) ,
.next ( next ) ,
.next_pending ( next_pending ) ,
.b_push ( b_push ) ,
.b_full ( b_full ) ,
.a_push ( a_push )
);
assign b_awid = s_awid_r;
assign b_awlen = s_awlen_r;
always @(posedge clk) begin
s_awid_r <= s_awid ;
s_awlen_r <= s_awlen ;
end
endmodule
`default_nettype wire
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (clk);
input clk;
reg [7:0] crc;
wire [61:59] ah = crc[5:3];
wire [61:59] bh = ~crc[4:2];
wire [41:2] al = {crc,crc,crc,crc,crc};
wire [41:2] bl = ~{crc[6:0],crc[6:0],crc[6:0],crc[6:0],crc[6:0],crc[6:2]};
reg sel;
wire [61:28] q = ( sel
? func(ah, al)
: func(bh, bl));
function [61:28] func;
input [61:59] inh;
input [41:2] inl;
reg [42:28] func_mid;
reg carry;
begin
carry = &inl[27:2];
func_mid = {1'b0,inl[41:28]} + {14'b0, carry};
func[61:59] = inh + {2'b0, func_mid[42]};
func[58:42] = {17{func_mid[41]}};
func[41:28] = func_mid[41:28];
end
endfunction
integer cyc; initial cyc=1;
always @ (posedge clk) begin
//$write("%d %x\n", cyc, q);
if (cyc!=0) begin
cyc <= cyc + 1;
sel <= ~sel;
crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
if (cyc==1) begin
sel <= 1'b1;
crc <= 8'h12;
end
if (cyc==2) if (q!=34'h100000484) $stop;
if (cyc==3) if (q!=34'h37fffeddb) $stop;
if (cyc==4) if (q!=34'h080001212) $stop;
if (cyc==5) if (q!=34'h1fffff7ef) $stop;
if (cyc==6) if (q!=34'h200000848) $stop;
if (cyc==7) if (q!=34'h380001ebd) $stop;
if (cyc==8) if (q!=34'h07fffe161) $stop;
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
/*
* Copyright 2017 Google Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`define IVERILOG
`include "test_defines.v"
`include "top.v"
module top_test;
localparam WIDTH = 8;
localparam UART_WIDTH = $clog2(WIDTH);
localparam OUTPUT_CNT = 12;
reg clk = 1;
reg uart_clk = 0;
reg receiving = 0;
reg display = 0;
reg [UART_WIDTH-1 : 0] serial_cnt = 0;
reg [WIDTH-1 : 0] serial_data;
reg [WIDTH-1 : 0] expected_output = 80; //'P'
wire uart_tx;
always #2 clk = !clk;
always #8 uart_clk = !uart_clk; //For sim. UART TX clock gets divided by 4
top t(
.clk(clk),
.uart_tx_line(uart_tx));
initial begin
#9999 $display("Test timeout!\n");
#10000 $finish;
end
always @ (posedge uart_clk) begin
if (receiving) begin
if (serial_cnt == WIDTH - 1 ) begin
receiving <= 0;
display <= 1;
end
serial_data[serial_cnt] <= uart_tx;
serial_cnt <= serial_cnt + 1;
end else if (display) begin
if (serial_data == expected_output) begin
$display("%s\ttest pass\n", `TEST_NAME);
$finish;
end else begin
$display("%s\ttest failed!\n", `TEST_NAME);
$finish;
end
display <= 0;
end else begin
if (uart_tx == 0) begin
receiving <= 1;
end
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:46:58 11/16/2015
// Design Name:
// Module Name: AluControl
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module AluControl(
input [1:0] aluOp,
input [5:0] instructionCodeLowBits,
input [5:0] instructionCodeHighBits,
output reg [3:0] aluOperation
);
/*
ALU Operation codes
0: SLL
1: SRL
2: SRA
3: ADD
4: SUB
5: AND
6: OR
7: XOR
8: NOR
9: SLT
AluOp: 00 Store and Load
AluOp: 01 Branch Equal y Not Equal
AluOp: 10 Operaciones Tipo R
AluOp: 11 Operaciones con Immediate
*/
always @(*)begin
case(aluOp)
0: aluOperation<=3;
1: aluOperation<=4;
2: begin
case(instructionCodeLowBits)
6'b000000: aluOperation<=0; //SLL
6'b000010: aluOperation<=1; //SRL
6'b000011: aluOperation<=2; //SRA
6'b000110: aluOperation<=1; //SRLV
6'b000111: aluOperation<=2; //SRAV
6'b000100: aluOperation<=0; //SLLV
6'b100000: aluOperation<=3; //ADD
6'b100010: aluOperation<=4; //SUB
6'b100100: aluOperation<=5; //AND
6'b100101: aluOperation<=6; //OR
6'b100110: aluOperation<=7; //XOR
6'b100111: aluOperation<=8; //NOR
6'b101010: aluOperation<=9; //SLT
default: aluOperation<='hF;
endcase
end
3: begin
case(instructionCodeHighBits)
6'b001000: aluOperation<=3; //ADDI
6'b001100: aluOperation<=5; //ANDI
6'b001101: aluOperation<=6; //ORI
6'b001110: aluOperation<=7; //XORI
6'b001010: aluOperation<=9; //SLTI
default: aluOperation<='hF;
endcase
end
default:aluOperation<='hF;
endcase
end
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module image_filter_Loop_1_proc (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
rows,
cols,
img_1_data_stream_0_V_din,
img_1_data_stream_0_V_full_n,
img_1_data_stream_0_V_write,
img_1_data_stream_1_V_din,
img_1_data_stream_1_V_full_n,
img_1_data_stream_1_V_write,
img_1_data_stream_2_V_din,
img_1_data_stream_2_V_full_n,
img_1_data_stream_2_V_write,
img_0_data_stream_0_V_dout,
img_0_data_stream_0_V_empty_n,
img_0_data_stream_0_V_read,
img_0_data_stream_1_V_dout,
img_0_data_stream_1_V_empty_n,
img_0_data_stream_1_V_read,
img_0_data_stream_2_V_dout,
img_0_data_stream_2_V_empty_n,
img_0_data_stream_2_V_read,
buffer_val_0_address0,
buffer_val_0_ce0,
buffer_val_0_we0,
buffer_val_0_d0,
buffer_val_0_q0,
buffer_val_0_address1,
buffer_val_0_ce1,
buffer_val_0_we1,
buffer_val_0_d1,
buffer_val_0_q1,
buffer_val_1_address0,
buffer_val_1_ce0,
buffer_val_1_we0,
buffer_val_1_d0,
buffer_val_1_q0,
buffer_val_1_address1,
buffer_val_1_ce1,
buffer_val_1_we1,
buffer_val_1_d1,
buffer_val_1_q1,
buffer_val_2_address0,
buffer_val_2_ce0,
buffer_val_2_we0,
buffer_val_2_d0,
buffer_val_2_q0,
buffer_val_2_address1,
buffer_val_2_ce1,
buffer_val_2_we1,
buffer_val_2_d1,
buffer_val_2_q1
);
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st1_fsm_0 = 6'b1;
parameter ap_ST_st2_fsm_1 = 6'b10;
parameter ap_ST_pp0_stg0_fsm_2 = 6'b100;
parameter ap_ST_pp0_stg1_fsm_3 = 6'b1000;
parameter ap_ST_pp0_stg2_fsm_4 = 6'b10000;
parameter ap_ST_st7_fsm_5 = 6'b100000;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv1_1 = 1'b1;
parameter ap_const_lv32_1 = 32'b1;
parameter ap_const_lv32_2 = 32'b10;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv32_3 = 32'b11;
parameter ap_const_lv32_4 = 32'b100;
parameter ap_const_lv32_5 = 32'b101;
parameter ap_const_lv11_0 = 11'b00000000000;
parameter ap_const_lv64_1 = 64'b1;
parameter ap_const_lv64_2 = 64'b10;
parameter ap_const_lv64_0 = 64'b0000000000000000000000000000000000000000000000000000000000000000;
parameter ap_const_lv11_1 = 11'b1;
parameter ap_const_lv32_A = 32'b1010;
parameter ap_const_lv10_0 = 10'b0000000000;
parameter ap_true = 1'b1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [31:0] rows;
input [31:0] cols;
output [7:0] img_1_data_stream_0_V_din;
input img_1_data_stream_0_V_full_n;
output img_1_data_stream_0_V_write;
output [7:0] img_1_data_stream_1_V_din;
input img_1_data_stream_1_V_full_n;
output img_1_data_stream_1_V_write;
output [7:0] img_1_data_stream_2_V_din;
input img_1_data_stream_2_V_full_n;
output img_1_data_stream_2_V_write;
input [7:0] img_0_data_stream_0_V_dout;
input img_0_data_stream_0_V_empty_n;
output img_0_data_stream_0_V_read;
input [7:0] img_0_data_stream_1_V_dout;
input img_0_data_stream_1_V_empty_n;
output img_0_data_stream_1_V_read;
input [7:0] img_0_data_stream_2_V_dout;
input img_0_data_stream_2_V_empty_n;
output img_0_data_stream_2_V_read;
output [1:0] buffer_val_0_address0;
output buffer_val_0_ce0;
output buffer_val_0_we0;
output [7:0] buffer_val_0_d0;
input [7:0] buffer_val_0_q0;
output [1:0] buffer_val_0_address1;
output buffer_val_0_ce1;
output buffer_val_0_we1;
output [7:0] buffer_val_0_d1;
input [7:0] buffer_val_0_q1;
output [1:0] buffer_val_1_address0;
output buffer_val_1_ce0;
output buffer_val_1_we0;
output [7:0] buffer_val_1_d0;
input [7:0] buffer_val_1_q0;
output [1:0] buffer_val_1_address1;
output buffer_val_1_ce1;
output buffer_val_1_we1;
output [7:0] buffer_val_1_d1;
input [7:0] buffer_val_1_q1;
output [1:0] buffer_val_2_address0;
output buffer_val_2_ce0;
output buffer_val_2_we0;
output [7:0] buffer_val_2_d0;
input [7:0] buffer_val_2_q0;
output [1:0] buffer_val_2_address1;
output buffer_val_2_ce1;
output buffer_val_2_we1;
output [7:0] buffer_val_2_d1;
input [7:0] buffer_val_2_q1;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg img_1_data_stream_0_V_write;
reg img_1_data_stream_1_V_write;
reg img_1_data_stream_2_V_write;
reg img_0_data_stream_0_V_read;
reg img_0_data_stream_1_V_read;
reg img_0_data_stream_2_V_read;
reg[1:0] buffer_val_0_address0;
reg buffer_val_0_ce0;
reg buffer_val_0_we0;
reg[7:0] buffer_val_0_d0;
reg buffer_val_0_ce1;
reg buffer_val_0_we1;
reg[1:0] buffer_val_1_address0;
reg buffer_val_1_ce0;
reg buffer_val_1_we0;
reg[7:0] buffer_val_1_d0;
reg buffer_val_1_ce1;
reg buffer_val_1_we1;
reg[1:0] buffer_val_2_address0;
reg buffer_val_2_ce0;
reg buffer_val_2_we0;
reg[7:0] buffer_val_2_d0;
reg[1:0] buffer_val_2_address1;
reg buffer_val_2_ce1;
reg buffer_val_2_we1;
reg ap_done_reg = 1'b0;
(* fsm_encoding = "none" *) reg [5:0] ap_CS_fsm = 6'b1;
reg ap_sig_cseq_ST_st1_fsm_0;
reg ap_sig_bdd_25;
reg [10:0] col_reg_269;
wire [11:0] tmp_fu_281_p1;
reg ap_sig_bdd_104;
wire [11:0] tmp_2_fu_285_p1;
wire [1:0] buffer_val_0_addr_gep_fu_159_p3;
reg [1:0] buffer_val_0_addr_reg_551;
wire [1:0] buffer_val_0_addr_1_gep_fu_167_p3;
reg [1:0] buffer_val_0_addr_1_reg_556;
wire [1:0] buffer_val_1_addr_gep_fu_175_p3;
reg [1:0] buffer_val_1_addr_reg_561;
wire [1:0] buffer_val_1_addr_1_gep_fu_183_p3;
reg [1:0] buffer_val_1_addr_1_reg_566;
wire [1:0] buffer_val_2_addr_gep_fu_191_p3;
reg [1:0] buffer_val_2_addr_reg_571;
wire [1:0] buffer_val_2_addr_1_gep_fu_199_p3;
reg [1:0] buffer_val_2_addr_1_reg_577;
wire [1:0] buffer_val_0_addr_2_gep_fu_207_p3;
reg [1:0] buffer_val_0_addr_2_reg_582;
wire [1:0] buffer_val_1_addr_2_gep_fu_215_p3;
reg [1:0] buffer_val_1_addr_2_reg_587;
wire [1:0] buffer_val_2_addr_2_gep_fu_223_p3;
reg [1:0] buffer_val_2_addr_2_reg_592;
wire [0:0] exitcond2_fu_293_p2;
reg ap_sig_cseq_ST_st2_fsm_1;
reg ap_sig_bdd_134;
wire [10:0] row_1_fu_298_p2;
reg [10:0] row_1_reg_602;
wire [0:0] exitcond1_fu_308_p2;
reg [0:0] exitcond1_reg_607;
reg ap_sig_cseq_ST_pp0_stg0_fsm_2;
reg ap_sig_bdd_145;
reg ap_reg_ppiten_pp0_it0 = 1'b0;
reg ap_sig_bdd_159;
reg ap_reg_ppiten_pp0_it1 = 1'b0;
wire [10:0] col_1_fu_313_p2;
reg [10:0] col_1_reg_611;
wire [0:0] icmp_fu_329_p2;
reg [0:0] icmp_reg_616;
reg [7:0] scl_val_0_reg_624;
reg ap_sig_cseq_ST_pp0_stg1_fsm_3;
reg ap_sig_bdd_180;
reg ap_sig_bdd_190;
reg [7:0] scl_val_1_reg_630;
reg [7:0] p_val_2_reg_636;
reg [7:0] buffer_val_0_load_reg_643;
reg [7:0] buffer_val_1_load_reg_649;
reg [7:0] buffer_val_2_load_reg_655;
reg [7:0] buffer_val_0_load_1_reg_660;
reg [7:0] buffer_val_1_load_1_reg_665;
reg [7:0] buffer_val_2_load_1_reg_670;
wire [0:0] c_fu_335_p2;
reg [0:0] c_reg_675;
wire [0:0] ult_fu_341_p2;
reg [0:0] ult_reg_681;
wire [0:0] rev1_fu_353_p2;
reg [0:0] rev1_reg_686;
wire [0:0] c_1_fu_359_p2;
reg [0:0] c_1_reg_691;
wire [0:0] ult2_fu_365_p2;
reg [0:0] ult2_reg_697;
wire [0:0] rev3_fu_377_p2;
reg [0:0] rev3_reg_702;
wire [0:0] c_2_fu_383_p2;
reg [0:0] c_2_reg_707;
wire [0:0] ult4_fu_389_p2;
reg [0:0] ult4_reg_713;
wire [0:0] ult5_fu_395_p2;
reg [0:0] ult5_reg_718;
wire [7:0] p_val_0_1_fu_427_p3;
reg [7:0] p_val_0_1_reg_723;
reg ap_sig_cseq_ST_pp0_stg2_fsm_4;
reg ap_sig_bdd_230;
wire [7:0] p_val_1_1_fu_460_p3;
reg [7:0] p_val_1_1_reg_728;
wire [7:0] p_val_0_2_fu_499_p3;
reg [7:0] p_val_0_2_reg_733;
wire [0:0] sel_tmp2_fu_505_p2;
reg [0:0] sel_tmp2_reg_738;
wire [7:0] p_val_1_2_fu_510_p3;
reg [7:0] p_val_1_2_reg_744;
wire [7:0] tmp_6_fu_521_p3;
reg [7:0] tmp_6_reg_749;
reg [10:0] row_reg_258;
reg ap_sig_cseq_ST_st7_fsm_5;
reg ap_sig_bdd_257;
reg [10:0] col_phi_fu_273_p4;
wire [11:0] row_cast_fu_289_p1;
wire [11:0] col_cast_fu_304_p1;
wire [9:0] tmp_3_fu_319_p4;
wire [0:0] ult1_fu_347_p2;
wire [0:0] ult3_fu_371_p2;
wire [0:0] rev_fu_401_p2;
wire [0:0] c_0_not_fu_406_p2;
wire [0:0] brmerge1_fu_417_p2;
wire [0:0] brmerge_fu_411_p2;
wire [7:0] buffer_val_0_load_scl_val_0_fu_421_p3;
wire [0:0] rev2_fu_434_p2;
wire [0:0] c_0_not_1_fu_439_p2;
wire [0:0] brmerge1_1_fu_450_p2;
wire [0:0] brmerge_1_fu_444_p2;
wire [7:0] buffer_val_1_load_scl_val_1_fu_454_p3;
wire [0:0] rev4_fu_467_p2;
wire [0:0] c_0_not_2_fu_472_p2;
wire [0:0] rev5_fu_483_p2;
wire [0:0] brmerge1_2_fu_488_p2;
wire [0:0] brmerge_2_fu_477_p2;
wire [7:0] buffer_val_2_load_p_val_2_fu_493_p3;
wire [7:0] sel_tmp9_fu_516_p3;
reg [5:0] ap_NS_fsm;
/// the current state (ap_CS_fsm) of the state machine. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st1_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_done_reg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_done_reg
if (ap_rst == 1'b1) begin
ap_done_reg <= ap_const_logic_0;
end else begin
if ((ap_const_logic_1 == ap_continue)) begin
ap_done_reg <= ap_const_logic_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(exitcond2_fu_293_p2 == ap_const_lv1_0))) begin
ap_done_reg <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp0_it0 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~(ap_sig_bdd_159 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~(exitcond1_fu_308_p2 == ap_const_lv1_0))) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (exitcond2_fu_293_p2 == ap_const_lv1_0))) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp0_it1 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end else begin
if (((exitcond1_reg_607 == ap_const_lv1_0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg2_fsm_4))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_1;
end else if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (exitcond2_fu_293_p2 == ap_const_lv1_0)) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg2_fsm_4) & ~(exitcond1_reg_607 == ap_const_lv1_0)))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond1_reg_607 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_159 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
col_reg_269 <= col_1_reg_611;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (exitcond2_fu_293_p2 == ap_const_lv1_0))) begin
col_reg_269 <= ap_const_lv11_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_104)) begin
row_reg_258 <= ap_const_lv11_0;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st7_fsm_5)) begin
row_reg_258 <= row_1_reg_602;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((exitcond1_reg_607 == ap_const_lv1_0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg1_fsm_3) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_190))) begin
buffer_val_0_load_1_reg_660 <= buffer_val_0_q1;
buffer_val_0_load_reg_643 <= buffer_val_0_q0;
buffer_val_1_load_1_reg_665 <= buffer_val_1_q1;
buffer_val_1_load_reg_649 <= buffer_val_1_q0;
buffer_val_2_load_1_reg_670 <= buffer_val_2_q1;
buffer_val_2_load_reg_655 <= buffer_val_2_q0;
c_1_reg_691 <= c_1_fu_359_p2;
c_2_reg_707 <= c_2_fu_383_p2;
c_reg_675 <= c_fu_335_p2;
p_val_2_reg_636 <= img_0_data_stream_2_V_dout;
rev1_reg_686 <= rev1_fu_353_p2;
rev3_reg_702 <= rev3_fu_377_p2;
scl_val_0_reg_624 <= img_0_data_stream_0_V_dout;
scl_val_1_reg_630 <= img_0_data_stream_1_V_dout;
ult2_reg_697 <= ult2_fu_365_p2;
ult4_reg_713 <= ult4_fu_389_p2;
ult5_reg_718 <= ult5_fu_395_p2;
ult_reg_681 <= ult_fu_341_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_159 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
col_1_reg_611 <= col_1_fu_313_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~(ap_sig_bdd_159 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
exitcond1_reg_607 <= exitcond1_fu_308_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~(ap_sig_bdd_159 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (exitcond1_fu_308_p2 == ap_const_lv1_0))) begin
icmp_reg_616 <= icmp_fu_329_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((exitcond1_reg_607 == ap_const_lv1_0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg2_fsm_4))) begin
p_val_0_1_reg_723 <= p_val_0_1_fu_427_p3;
p_val_0_2_reg_733 <= p_val_0_2_fu_499_p3;
p_val_1_1_reg_728 <= p_val_1_1_fu_460_p3;
p_val_1_2_reg_744 <= p_val_1_2_fu_510_p3;
sel_tmp2_reg_738 <= sel_tmp2_fu_505_p2;
tmp_6_reg_749 <= tmp_6_fu_521_p3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1)) begin
row_1_reg_602 <= row_1_fu_298_p2;
end
end
/// ap_done assign process. ///
always @ (ap_done_reg or exitcond2_fu_293_p2 or ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 == ap_done_reg) | ((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(exitcond2_fu_293_p2 == ap_const_lv1_0)))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_start or ap_sig_cseq_ST_st1_fsm_0)
begin
if ((~(ap_const_logic_1 == ap_start) & (ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0))) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// ap_ready assign process. ///
always @ (exitcond2_fu_293_p2 or ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(exitcond2_fu_293_p2 == ap_const_lv1_0))) begin
ap_ready = ap_const_logic_1;
end else begin
ap_ready = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_pp0_stg0_fsm_2 assign process. ///
always @ (ap_sig_bdd_145)
begin
if (ap_sig_bdd_145) begin
ap_sig_cseq_ST_pp0_stg0_fsm_2 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_pp0_stg0_fsm_2 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_pp0_stg1_fsm_3 assign process. ///
always @ (ap_sig_bdd_180)
begin
if (ap_sig_bdd_180) begin
ap_sig_cseq_ST_pp0_stg1_fsm_3 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_pp0_stg1_fsm_3 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_pp0_stg2_fsm_4 assign process. ///
always @ (ap_sig_bdd_230)
begin
if (ap_sig_bdd_230) begin
ap_sig_cseq_ST_pp0_stg2_fsm_4 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_pp0_stg2_fsm_4 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st1_fsm_0 assign process. ///
always @ (ap_sig_bdd_25)
begin
if (ap_sig_bdd_25) begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st2_fsm_1 assign process. ///
always @ (ap_sig_bdd_134)
begin
if (ap_sig_bdd_134) begin
ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st7_fsm_5 assign process. ///
always @ (ap_sig_bdd_257)
begin
if (ap_sig_bdd_257) begin
ap_sig_cseq_ST_st7_fsm_5 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st7_fsm_5 = ap_const_logic_0;
end
end
/// buffer_val_0_address0 assign process. ///
always @ (buffer_val_0_addr_reg_551 or buffer_val_0_addr_1_reg_556 or ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_reg_ppiten_pp0_it0 or ap_sig_cseq_ST_pp0_stg1_fsm_3 or ap_sig_cseq_ST_pp0_stg2_fsm_4)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg2_fsm_4))) begin
buffer_val_0_address0 = buffer_val_0_addr_1_reg_556;
end else if ((((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg1_fsm_3)))) begin
buffer_val_0_address0 = buffer_val_0_addr_reg_551;
end else begin
buffer_val_0_address0 = 'bx;
end
end
/// buffer_val_0_ce0 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_159 or ap_reg_ppiten_pp0_it1 or ap_sig_cseq_ST_pp0_stg1_fsm_3 or ap_sig_bdd_190 or ap_sig_cseq_ST_pp0_stg2_fsm_4)
begin
if ((((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_159 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg1_fsm_3) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_190)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg2_fsm_4)))) begin
buffer_val_0_ce0 = ap_const_logic_1;
end else begin
buffer_val_0_ce0 = ap_const_logic_0;
end
end
/// buffer_val_0_ce1 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_159 or ap_reg_ppiten_pp0_it1 or ap_sig_cseq_ST_pp0_stg1_fsm_3 or ap_sig_bdd_190)
begin
if ((((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_159 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg1_fsm_3) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_190)))) begin
buffer_val_0_ce1 = ap_const_logic_1;
end else begin
buffer_val_0_ce1 = ap_const_logic_0;
end
end
/// buffer_val_0_d0 assign process. ///
always @ (buffer_val_0_q1 or ap_reg_ppiten_pp0_it0 or ap_sig_cseq_ST_pp0_stg1_fsm_3 or buffer_val_0_load_reg_643 or ap_sig_cseq_ST_pp0_stg2_fsm_4)
begin
if ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0)) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg2_fsm_4)) begin
buffer_val_0_d0 = buffer_val_0_load_reg_643;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg1_fsm_3)) begin
buffer_val_0_d0 = buffer_val_0_q1;
end else begin
buffer_val_0_d0 = 'bx;
end
end else begin
buffer_val_0_d0 = 'bx;
end
end
/// buffer_val_0_we0 assign process. ///
always @ (exitcond1_reg_607 or ap_reg_ppiten_pp0_it0 or ap_sig_cseq_ST_pp0_stg1_fsm_3 or ap_sig_bdd_190 or ap_sig_cseq_ST_pp0_stg2_fsm_4)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond1_reg_607 == ap_const_lv1_0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg1_fsm_3) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_190)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond1_reg_607 == ap_const_lv1_0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg2_fsm_4)))) begin
buffer_val_0_we0 = ap_const_logic_1;
end else begin
buffer_val_0_we0 = ap_const_logic_0;
end
end
/// buffer_val_0_we1 assign process. ///
always @ (exitcond1_reg_607 or ap_reg_ppiten_pp0_it0 or ap_sig_cseq_ST_pp0_stg1_fsm_3 or ap_sig_bdd_190)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond1_reg_607 == ap_const_lv1_0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg1_fsm_3) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_190))) begin
buffer_val_0_we1 = ap_const_logic_1;
end else begin
buffer_val_0_we1 = ap_const_logic_0;
end
end
/// buffer_val_1_address0 assign process. ///
always @ (buffer_val_1_addr_reg_561 or buffer_val_1_addr_1_reg_566 or ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_reg_ppiten_pp0_it0 or ap_sig_cseq_ST_pp0_stg1_fsm_3 or ap_sig_cseq_ST_pp0_stg2_fsm_4)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg2_fsm_4))) begin
buffer_val_1_address0 = buffer_val_1_addr_1_reg_566;
end else if ((((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg1_fsm_3)))) begin
buffer_val_1_address0 = buffer_val_1_addr_reg_561;
end else begin
buffer_val_1_address0 = 'bx;
end
end
/// buffer_val_1_ce0 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_159 or ap_reg_ppiten_pp0_it1 or ap_sig_cseq_ST_pp0_stg1_fsm_3 or ap_sig_bdd_190 or ap_sig_cseq_ST_pp0_stg2_fsm_4)
begin
if ((((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_159 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg1_fsm_3) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_190)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg2_fsm_4)))) begin
buffer_val_1_ce0 = ap_const_logic_1;
end else begin
buffer_val_1_ce0 = ap_const_logic_0;
end
end
/// buffer_val_1_ce1 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_159 or ap_reg_ppiten_pp0_it1 or ap_sig_cseq_ST_pp0_stg1_fsm_3 or ap_sig_bdd_190)
begin
if ((((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_159 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg1_fsm_3) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_190)))) begin
buffer_val_1_ce1 = ap_const_logic_1;
end else begin
buffer_val_1_ce1 = ap_const_logic_0;
end
end
/// buffer_val_1_d0 assign process. ///
always @ (buffer_val_1_q1 or ap_reg_ppiten_pp0_it0 or ap_sig_cseq_ST_pp0_stg1_fsm_3 or buffer_val_1_load_reg_649 or ap_sig_cseq_ST_pp0_stg2_fsm_4)
begin
if ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0)) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg2_fsm_4)) begin
buffer_val_1_d0 = buffer_val_1_load_reg_649;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg1_fsm_3)) begin
buffer_val_1_d0 = buffer_val_1_q1;
end else begin
buffer_val_1_d0 = 'bx;
end
end else begin
buffer_val_1_d0 = 'bx;
end
end
/// buffer_val_1_we0 assign process. ///
always @ (exitcond1_reg_607 or ap_reg_ppiten_pp0_it0 or ap_sig_cseq_ST_pp0_stg1_fsm_3 or ap_sig_bdd_190 or ap_sig_cseq_ST_pp0_stg2_fsm_4)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond1_reg_607 == ap_const_lv1_0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg1_fsm_3) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_190)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond1_reg_607 == ap_const_lv1_0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg2_fsm_4)))) begin
buffer_val_1_we0 = ap_const_logic_1;
end else begin
buffer_val_1_we0 = ap_const_logic_0;
end
end
/// buffer_val_1_we1 assign process. ///
always @ (exitcond1_reg_607 or ap_reg_ppiten_pp0_it0 or ap_sig_cseq_ST_pp0_stg1_fsm_3 or ap_sig_bdd_190)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond1_reg_607 == ap_const_lv1_0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg1_fsm_3) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_190))) begin
buffer_val_1_we1 = ap_const_logic_1;
end else begin
buffer_val_1_we1 = ap_const_logic_0;
end
end
/// buffer_val_2_address0 assign process. ///
always @ (buffer_val_2_addr_reg_571 or buffer_val_2_addr_1_reg_577 or buffer_val_2_addr_2_reg_592 or ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_reg_ppiten_pp0_it0 or ap_sig_cseq_ST_pp0_stg1_fsm_3 or ap_sig_cseq_ST_pp0_stg2_fsm_4)
begin
if ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0)) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg2_fsm_4)) begin
buffer_val_2_address0 = buffer_val_2_addr_2_reg_592;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg1_fsm_3)) begin
buffer_val_2_address0 = buffer_val_2_addr_1_reg_577;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2)) begin
buffer_val_2_address0 = buffer_val_2_addr_reg_571;
end else begin
buffer_val_2_address0 = 'bx;
end
end else begin
buffer_val_2_address0 = 'bx;
end
end
/// buffer_val_2_address1 assign process. ///
always @ (buffer_val_2_addr_reg_571 or buffer_val_2_addr_2_reg_592 or ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_reg_ppiten_pp0_it0 or ap_sig_cseq_ST_pp0_stg1_fsm_3)
begin
if ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0)) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg1_fsm_3)) begin
buffer_val_2_address1 = buffer_val_2_addr_reg_571;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2)) begin
buffer_val_2_address1 = buffer_val_2_addr_2_reg_592;
end else begin
buffer_val_2_address1 = 'bx;
end
end else begin
buffer_val_2_address1 = 'bx;
end
end
/// buffer_val_2_ce0 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_159 or ap_reg_ppiten_pp0_it1 or ap_sig_cseq_ST_pp0_stg1_fsm_3 or ap_sig_bdd_190 or ap_sig_cseq_ST_pp0_stg2_fsm_4)
begin
if ((((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_159 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg1_fsm_3) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_190)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg2_fsm_4)))) begin
buffer_val_2_ce0 = ap_const_logic_1;
end else begin
buffer_val_2_ce0 = ap_const_logic_0;
end
end
/// buffer_val_2_ce1 assign process. ///
always @ (ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_159 or ap_reg_ppiten_pp0_it1 or ap_sig_cseq_ST_pp0_stg1_fsm_3 or ap_sig_bdd_190)
begin
if ((((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_159 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg1_fsm_3) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_190)))) begin
buffer_val_2_ce1 = ap_const_logic_1;
end else begin
buffer_val_2_ce1 = ap_const_logic_0;
end
end
/// buffer_val_2_d0 assign process. ///
always @ (buffer_val_2_q0 or ap_reg_ppiten_pp0_it0 or ap_sig_cseq_ST_pp0_stg1_fsm_3 or p_val_2_reg_636 or ap_sig_cseq_ST_pp0_stg2_fsm_4)
begin
if ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0)) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg2_fsm_4)) begin
buffer_val_2_d0 = p_val_2_reg_636;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg1_fsm_3)) begin
buffer_val_2_d0 = buffer_val_2_q0;
end else begin
buffer_val_2_d0 = 'bx;
end
end else begin
buffer_val_2_d0 = 'bx;
end
end
/// buffer_val_2_we0 assign process. ///
always @ (exitcond1_reg_607 or ap_reg_ppiten_pp0_it0 or ap_sig_cseq_ST_pp0_stg1_fsm_3 or ap_sig_bdd_190 or ap_sig_cseq_ST_pp0_stg2_fsm_4)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond1_reg_607 == ap_const_lv1_0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg1_fsm_3) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_190)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond1_reg_607 == ap_const_lv1_0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg2_fsm_4)))) begin
buffer_val_2_we0 = ap_const_logic_1;
end else begin
buffer_val_2_we0 = ap_const_logic_0;
end
end
/// buffer_val_2_we1 assign process. ///
always @ (exitcond1_reg_607 or ap_reg_ppiten_pp0_it0 or ap_sig_cseq_ST_pp0_stg1_fsm_3 or ap_sig_bdd_190)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond1_reg_607 == ap_const_lv1_0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg1_fsm_3) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_190))) begin
buffer_val_2_we1 = ap_const_logic_1;
end else begin
buffer_val_2_we1 = ap_const_logic_0;
end
end
/// col_phi_fu_273_p4 assign process. ///
always @ (col_reg_269 or exitcond1_reg_607 or ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_reg_ppiten_pp0_it1 or col_1_reg_611)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond1_reg_607 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) begin
col_phi_fu_273_p4 = col_1_reg_611;
end else begin
col_phi_fu_273_p4 = col_reg_269;
end
end
/// img_0_data_stream_0_V_read assign process. ///
always @ (exitcond1_reg_607 or ap_reg_ppiten_pp0_it0 or ap_sig_cseq_ST_pp0_stg1_fsm_3 or ap_sig_bdd_190)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond1_reg_607 == ap_const_lv1_0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg1_fsm_3) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_190))) begin
img_0_data_stream_0_V_read = ap_const_logic_1;
end else begin
img_0_data_stream_0_V_read = ap_const_logic_0;
end
end
/// img_0_data_stream_1_V_read assign process. ///
always @ (exitcond1_reg_607 or ap_reg_ppiten_pp0_it0 or ap_sig_cseq_ST_pp0_stg1_fsm_3 or ap_sig_bdd_190)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond1_reg_607 == ap_const_lv1_0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg1_fsm_3) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_190))) begin
img_0_data_stream_1_V_read = ap_const_logic_1;
end else begin
img_0_data_stream_1_V_read = ap_const_logic_0;
end
end
/// img_0_data_stream_2_V_read assign process. ///
always @ (exitcond1_reg_607 or ap_reg_ppiten_pp0_it0 or ap_sig_cseq_ST_pp0_stg1_fsm_3 or ap_sig_bdd_190)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (exitcond1_reg_607 == ap_const_lv1_0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg1_fsm_3) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_190))) begin
img_0_data_stream_2_V_read = ap_const_logic_1;
end else begin
img_0_data_stream_2_V_read = ap_const_logic_0;
end
end
/// img_1_data_stream_0_V_write assign process. ///
always @ (exitcond1_reg_607 or ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_159 or ap_reg_ppiten_pp0_it1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond1_reg_607 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_159 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
img_1_data_stream_0_V_write = ap_const_logic_1;
end else begin
img_1_data_stream_0_V_write = ap_const_logic_0;
end
end
/// img_1_data_stream_1_V_write assign process. ///
always @ (exitcond1_reg_607 or ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_159 or ap_reg_ppiten_pp0_it1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond1_reg_607 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_159 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
img_1_data_stream_1_V_write = ap_const_logic_1;
end else begin
img_1_data_stream_1_V_write = ap_const_logic_0;
end
end
/// img_1_data_stream_2_V_write assign process. ///
always @ (exitcond1_reg_607 or ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_159 or ap_reg_ppiten_pp0_it1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond1_reg_607 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_159 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
img_1_data_stream_2_V_write = ap_const_logic_1;
end else begin
img_1_data_stream_2_V_write = ap_const_logic_0;
end
end
/// the next state (ap_NS_fsm) of the state machine. ///
always @ (ap_CS_fsm or ap_sig_bdd_104 or exitcond2_fu_293_p2 or exitcond1_fu_308_p2 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_159 or ap_reg_ppiten_pp0_it1 or ap_sig_bdd_190)
begin
case (ap_CS_fsm)
ap_ST_st1_fsm_0 :
begin
if (~ap_sig_bdd_104) begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end else begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end
end
ap_ST_st2_fsm_1 :
begin
if (~(exitcond2_fu_293_p2 == ap_const_lv1_0)) begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end else begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_2;
end
end
ap_ST_pp0_stg0_fsm_2 :
begin
if ((~(ap_sig_bdd_159 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_159 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~(exitcond1_fu_308_p2 == ap_const_lv1_0)))) begin
ap_NS_fsm = ap_ST_pp0_stg1_fsm_3;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_sig_bdd_159 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~(exitcond1_fu_308_p2 == ap_const_lv1_0))) begin
ap_NS_fsm = ap_ST_st7_fsm_5;
end else begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_2;
end
end
ap_ST_pp0_stg1_fsm_3 :
begin
if (~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ap_sig_bdd_190)) begin
ap_NS_fsm = ap_ST_pp0_stg2_fsm_4;
end else begin
ap_NS_fsm = ap_ST_pp0_stg1_fsm_3;
end
end
ap_ST_pp0_stg2_fsm_4 :
begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_2;
end
ap_ST_st7_fsm_5 :
begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end
default :
begin
ap_NS_fsm = 'bx;
end
endcase
end
/// ap_sig_bdd_104 assign process. ///
always @ (ap_start or ap_done_reg)
begin
ap_sig_bdd_104 = ((ap_start == ap_const_logic_0) | (ap_done_reg == ap_const_logic_1));
end
/// ap_sig_bdd_134 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_134 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_1]);
end
/// ap_sig_bdd_145 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_145 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_2]);
end
/// ap_sig_bdd_159 assign process. ///
always @ (img_1_data_stream_0_V_full_n or img_1_data_stream_1_V_full_n or img_1_data_stream_2_V_full_n or exitcond1_reg_607)
begin
ap_sig_bdd_159 = (((img_1_data_stream_0_V_full_n == ap_const_logic_0) & (exitcond1_reg_607 == ap_const_lv1_0)) | ((exitcond1_reg_607 == ap_const_lv1_0) & (img_1_data_stream_1_V_full_n == ap_const_logic_0)) | ((exitcond1_reg_607 == ap_const_lv1_0) & (img_1_data_stream_2_V_full_n == ap_const_logic_0)));
end
/// ap_sig_bdd_180 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_180 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_3]);
end
/// ap_sig_bdd_190 assign process. ///
always @ (img_0_data_stream_0_V_empty_n or img_0_data_stream_1_V_empty_n or img_0_data_stream_2_V_empty_n or exitcond1_reg_607)
begin
ap_sig_bdd_190 = (((exitcond1_reg_607 == ap_const_lv1_0) & (img_0_data_stream_0_V_empty_n == ap_const_logic_0)) | ((exitcond1_reg_607 == ap_const_lv1_0) & (img_0_data_stream_1_V_empty_n == ap_const_logic_0)) | ((exitcond1_reg_607 == ap_const_lv1_0) & (img_0_data_stream_2_V_empty_n == ap_const_logic_0)));
end
/// ap_sig_bdd_230 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_230 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_4]);
end
/// ap_sig_bdd_25 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_25 = (ap_CS_fsm[ap_const_lv32_0] == ap_const_lv1_1);
end
/// ap_sig_bdd_257 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_257 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_5]);
end
assign brmerge1_1_fu_450_p2 = (rev3_reg_702 | c_1_reg_691);
assign brmerge1_2_fu_488_p2 = (rev5_fu_483_p2 | c_2_reg_707);
assign brmerge1_fu_417_p2 = (rev1_reg_686 | c_reg_675);
assign brmerge_1_fu_444_p2 = (rev2_fu_434_p2 | c_0_not_1_fu_439_p2);
assign brmerge_2_fu_477_p2 = (rev4_fu_467_p2 | c_0_not_2_fu_472_p2);
assign brmerge_fu_411_p2 = (rev_fu_401_p2 | c_0_not_fu_406_p2);
assign buffer_val_0_addr_1_gep_fu_167_p3 = ap_const_lv64_2;
assign buffer_val_0_addr_2_gep_fu_207_p3 = ap_const_lv64_0;
assign buffer_val_0_addr_gep_fu_159_p3 = ap_const_lv64_1;
assign buffer_val_0_address1 = buffer_val_0_addr_2_reg_582;
assign buffer_val_0_d1 = img_0_data_stream_0_V_dout;
assign buffer_val_0_load_scl_val_0_fu_421_p3 = ((brmerge1_fu_417_p2)? buffer_val_0_load_reg_643: scl_val_0_reg_624);
assign buffer_val_1_addr_1_gep_fu_183_p3 = ap_const_lv64_2;
assign buffer_val_1_addr_2_gep_fu_215_p3 = ap_const_lv64_0;
assign buffer_val_1_addr_gep_fu_175_p3 = ap_const_lv64_1;
assign buffer_val_1_address1 = buffer_val_1_addr_2_reg_587;
assign buffer_val_1_d1 = img_0_data_stream_1_V_dout;
assign buffer_val_1_load_scl_val_1_fu_454_p3 = ((brmerge1_1_fu_450_p2)? buffer_val_1_load_reg_649: scl_val_1_reg_630);
assign buffer_val_2_addr_1_gep_fu_199_p3 = ap_const_lv64_2;
assign buffer_val_2_addr_2_gep_fu_223_p3 = ap_const_lv64_0;
assign buffer_val_2_addr_gep_fu_191_p3 = ap_const_lv64_1;
assign buffer_val_2_d1 = buffer_val_2_q1;
assign buffer_val_2_load_p_val_2_fu_493_p3 = ((brmerge1_2_fu_488_p2)? buffer_val_2_load_reg_655: p_val_2_reg_636);
assign c_0_not_1_fu_439_p2 = (c_1_reg_691 ^ ap_const_lv1_1);
assign c_0_not_2_fu_472_p2 = (c_2_reg_707 ^ ap_const_lv1_1);
assign c_0_not_fu_406_p2 = (c_reg_675 ^ ap_const_lv1_1);
assign c_1_fu_359_p2 = (buffer_val_1_q1 > img_0_data_stream_1_V_dout? 1'b1: 1'b0);
assign c_2_fu_383_p2 = (buffer_val_2_q1 > img_0_data_stream_2_V_dout? 1'b1: 1'b0);
assign c_fu_335_p2 = (buffer_val_0_q1 > img_0_data_stream_0_V_dout? 1'b1: 1'b0);
assign col_1_fu_313_p2 = (col_phi_fu_273_p4 + ap_const_lv11_1);
assign col_cast_fu_304_p1 = col_phi_fu_273_p4;
assign exitcond1_fu_308_p2 = (col_cast_fu_304_p1 == tmp_2_fu_285_p1? 1'b1: 1'b0);
assign exitcond2_fu_293_p2 = (row_cast_fu_289_p1 == tmp_fu_281_p1? 1'b1: 1'b0);
assign icmp_fu_329_p2 = (tmp_3_fu_319_p4 != ap_const_lv10_0? 1'b1: 1'b0);
assign img_1_data_stream_0_V_din = ((sel_tmp2_reg_738)? p_val_0_1_reg_723: p_val_0_2_reg_733);
assign img_1_data_stream_1_V_din = ((sel_tmp2_reg_738)? p_val_1_1_reg_728: p_val_1_2_reg_744);
assign img_1_data_stream_2_V_din = tmp_6_reg_749;
assign p_val_0_1_fu_427_p3 = ((brmerge_fu_411_p2)? buffer_val_0_load_scl_val_0_fu_421_p3: buffer_val_0_load_1_reg_660);
assign p_val_0_2_fu_499_p3 = ((icmp_reg_616)? p_val_0_1_fu_427_p3: scl_val_0_reg_624);
assign p_val_1_1_fu_460_p3 = ((brmerge_1_fu_444_p2)? buffer_val_1_load_scl_val_1_fu_454_p3: buffer_val_1_load_1_reg_665);
assign p_val_1_2_fu_510_p3 = ((icmp_reg_616)? p_val_1_1_fu_460_p3: scl_val_1_reg_630);
assign rev1_fu_353_p2 = (ult1_fu_347_p2 ^ ap_const_lv1_1);
assign rev2_fu_434_p2 = (ult2_reg_697 ^ ap_const_lv1_1);
assign rev3_fu_377_p2 = (ult3_fu_371_p2 ^ ap_const_lv1_1);
assign rev4_fu_467_p2 = (ult4_reg_713 ^ ap_const_lv1_1);
assign rev5_fu_483_p2 = (ult5_reg_718 ^ ap_const_lv1_1);
assign rev_fu_401_p2 = (ult_reg_681 ^ ap_const_lv1_1);
assign row_1_fu_298_p2 = (row_reg_258 + ap_const_lv11_1);
assign row_cast_fu_289_p1 = row_reg_258;
assign sel_tmp2_fu_505_p2 = (icmp_reg_616 & brmerge_2_fu_477_p2);
assign sel_tmp9_fu_516_p3 = ((icmp_reg_616)? buffer_val_2_load_1_reg_670: p_val_2_reg_636);
assign tmp_2_fu_285_p1 = cols[11:0];
assign tmp_3_fu_319_p4 = {{col_phi_fu_273_p4[ap_const_lv32_A : ap_const_lv32_1]}};
assign tmp_6_fu_521_p3 = ((sel_tmp2_fu_505_p2)? buffer_val_2_load_p_val_2_fu_493_p3: sel_tmp9_fu_516_p3);
assign tmp_fu_281_p1 = rows[11:0];
assign ult1_fu_347_p2 = (img_0_data_stream_0_V_dout < buffer_val_0_q0? 1'b1: 1'b0);
assign ult2_fu_365_p2 = (buffer_val_1_q1 < buffer_val_1_q0? 1'b1: 1'b0);
assign ult3_fu_371_p2 = (img_0_data_stream_1_V_dout < buffer_val_1_q0? 1'b1: 1'b0);
assign ult4_fu_389_p2 = (buffer_val_2_q1 < buffer_val_2_q0? 1'b1: 1'b0);
assign ult5_fu_395_p2 = (img_0_data_stream_2_V_dout < buffer_val_2_q0? 1'b1: 1'b0);
assign ult_fu_341_p2 = (buffer_val_0_q1 < buffer_val_0_q0? 1'b1: 1'b0);
always @ (posedge ap_clk)
begin
buffer_val_0_addr_reg_551[1:0] <= 2'b01;
buffer_val_0_addr_1_reg_556[1:0] <= 2'b10;
buffer_val_1_addr_reg_561[1:0] <= 2'b01;
buffer_val_1_addr_1_reg_566[1:0] <= 2'b10;
buffer_val_2_addr_reg_571[1:0] <= 2'b01;
buffer_val_2_addr_1_reg_577[1:0] <= 2'b10;
buffer_val_0_addr_2_reg_582[1:0] <= 2'b00;
buffer_val_1_addr_2_reg_587[1:0] <= 2'b00;
buffer_val_2_addr_2_reg_592[1:0] <= 2'b00;
end
endmodule //image_filter_Loop_1_proc
|
//==================================================================================================
// Filename : antares_divider.v
// Created On : Thu Sep 3 08:41:07 2015
// Last Modified : Sat Nov 07 12:01:42 2015
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Simón Bolívar
// Email : [email protected]
//
// Description : A multi-cycle divider unit.
// op_div and op_divu MUST BE dis-asserted after the setup
// cycle for normal operation, or the operation will be restarted.
// WARNING: no exception if divisor == 0.
//==================================================================================================
module antares_divider (
input clk,
input rst,
input op_divs,
input op_divu,
input [31:0] dividend,
input [31:0] divisor,
output [31:0] quotient,
output [31:0] remainder,
output div_stall
);
//--------------------------------------------------------------------------
// Signal Declaration: reg
//--------------------------------------------------------------------------
reg active; // 1 while running
reg neg_result; // 1 if the result must be negative
reg neg_remainder; // 1 if the remainder must be negative
reg [4:0] cycle; // number of cycles needed.
reg [31:0] result; // Store the result.
reg [31:0] denominator; // divisor
reg [31:0] residual; // current remainder
//--------------------------------------------------------------------------
// Signal Declaration: wire
//--------------------------------------------------------------------------
wire [32:0] partial_sub; // temp
//--------------------------------------------------------------------------
// assignments
//--------------------------------------------------------------------------
assign quotient = !neg_result ? result : -result;
assign remainder = !neg_remainder ? residual : -residual;
assign div_stall = active;
assign partial_sub = {residual[30:0], result[31]} - denominator; // calculate partial result
//--------------------------------------------------------------------------
// State Machine. This needs 32 cycles to calculate the result.
// The result is loaded after 34 cycles
// The first cycle is setup.
//--------------------------------------------------------------------------
always @(posedge clk) begin
if (rst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
active <= 1'h0;
cycle <= 5'h0;
denominator <= 32'h0;
neg_result <= 1'h0;
neg_remainder <= 1'h0;
residual <= 32'h0;
result <= 32'h0;
// End of automatics
end
else begin
if(op_divs) begin
// Signed division.
cycle <= 5'd31;
result <= (dividend[31] == 1'b0) ? dividend : -dividend;
denominator <= (divisor[31] == 1'b0) ? divisor : -divisor;
residual <= 32'b0;
neg_result <= dividend[31] ^ divisor[31];
neg_remainder <= dividend[31];
active <= 1'b1;
end
else if (op_divu) begin
// Unsigned division.
cycle <= 5'd31;
result <= dividend;
denominator <= divisor;
residual <= 32'b0;
neg_result <= 1'b0;
neg_remainder <= 1'h0;
active <= 1'b1;
end
else if (active) begin
// run a iteration
if(partial_sub[32] == 1'b0) begin
residual <= partial_sub[31:0];
result <= {result[30:0], 1'b1};
end
else begin
residual <= {residual[30:0], result[31]};
result <= {result[30:0], 1'b0};
end
if (cycle == 5'b0) begin
active <= 1'b0;
end
cycle <= cycle - 5'd1;
end
end
end
endmodule // antares_divider
|
// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 24080 $
// $Date: 2011-05-18 19:32:52 +0000 (Wed, 18 May 2011) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module RevertReg(CLK, Q_OUT, D_IN, EN);
parameter width = 1;
parameter init = { width {1'b0} } ;
input CLK;
input EN;
input [width - 1 : 0] D_IN;
output [width - 1 : 0] Q_OUT;
assign Q_OUT = init;
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module bd_350b_slot_2_b_0 (
In0,
In1,
dout
);
input wire [0 : 0] In0;
input wire [0 : 0] In1;
output wire [1 : 0] dout;
xlconcat_v2_1_1_xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(2),
.NUM_PORTS(2)
) inst (
.In0(In0),
.In1(In1),
.In2(1'B0),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule
|
/******************************************************************************/
/* DRAM Controller for VC707 Ryohei Kobayashi */
/* 2016-03-23 */
/******************************************************************************/
`default_nettype none
`include "define.vh"
module DRAMCON(input wire CLK_P,
input wire CLK_N,
input wire RST_X_IN,
////////// User logic interface ports //////////
input wire [1:0] D_REQ, // dram request, load or store
input wire [31:0] D_INITADR, // dram request, initial address
input wire [31:0] D_ELEM, // dram request, the number of elements
input wire [`APPDATA_WIDTH-1:0] D_DIN, //
output wire D_W, //
output reg [`APPDATA_WIDTH-1:0] D_DOUT, //
output reg D_DOUTEN, //
output wire D_BUSY, //
output wire USERCLK, //
output wire RST_O, //
////////// Memory interface ports //////////
inout wire [`DDR3_DATA] DDR3DQ,
inout wire [7:0] DDR3DQS_N,
inout wire [7:0] DDR3DQS_P,
output wire [`DDR3_ADDR] DDR3ADDR,
output wire [2:0] DDR3BA,
output wire DDR3RAS_N,
output wire DDR3CAS_N,
output wire DDR3WE_N,
output wire DDR3RESET_N,
output wire [0:0] DDR3CK_P,
output wire [0:0] DDR3CK_N,
output wire [0:0] DDR3CKE,
output wire [0:0] DDR3CS_N,
output wire [7:0] DDR3DM,
output wire [0:0] DDR3ODT);
function [`APPADDR_WIDTH-1:0] mux;
input [`APPADDR_WIDTH-1:0] a;
input [`APPADDR_WIDTH-1:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction
// inputs of u_dram
reg [`APPADDR_WIDTH-1:0] app_addr;
reg [`DDR3_CMD] app_cmd;
reg app_en;
// reg [`APPDATA_WIDTH-1:0] app_wdf_data;
wire [`APPDATA_WIDTH-1:0] app_wdf_data = D_DIN;
reg app_wdf_wren;
wire app_wdf_end = app_wdf_wren;
wire app_sr_req = 0; // no used
wire app_ref_req = 0; // no used
wire app_zq_req = 0; // no used
// outputs of u_dram
wire [`APPDATA_WIDTH-1:0] app_rd_data;
wire app_rd_data_end;
wire app_rd_data_valid;
wire app_rdy;
wire app_wdf_rdy;
wire app_sr_active; // no used
wire app_ref_ack; // no used
wire app_zq_ack; // no used
wire ui_clk;
wire ui_clk_sync_rst;
wire init_calib_complete;
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
dram u_dram (
// Memory interface ports
.ddr3_addr (DDR3ADDR),
.ddr3_ba (DDR3BA),
.ddr3_cas_n (DDR3CAS_N),
.ddr3_ck_n (DDR3CK_N),
.ddr3_ck_p (DDR3CK_P),
.ddr3_cke (DDR3CKE),
.ddr3_ras_n (DDR3RAS_N),
.ddr3_reset_n (DDR3RESET_N),
.ddr3_we_n (DDR3WE_N),
.ddr3_dq (DDR3DQ),
.ddr3_dqs_n (DDR3DQS_N),
.ddr3_dqs_p (DDR3DQS_P),
.ddr3_cs_n (DDR3CS_N),
.ddr3_dm (DDR3DM),
.ddr3_odt (DDR3ODT),
.sys_clk_p (CLK_P),
.sys_clk_n (CLK_N),
// Application interface ports
.app_addr (app_addr),
.app_cmd (app_cmd),
.app_en (app_en),
.app_wdf_data (app_wdf_data),
.app_wdf_end (app_wdf_end),
.app_wdf_wren (app_wdf_wren),
.app_rd_data (app_rd_data),
.app_rd_data_end (app_rd_data_end),
.app_rd_data_valid (app_rd_data_valid),
.app_rdy (app_rdy),
.app_wdf_rdy (app_wdf_rdy),
.app_sr_req (app_sr_req),
.app_ref_req (app_ref_req),
.app_zq_req (app_zq_req),
.app_sr_active (app_sr_active),
.app_ref_ack (app_ref_ack),
.app_zq_ack (app_zq_ack),
.ui_clk (ui_clk),
.ui_clk_sync_rst (ui_clk_sync_rst),
.init_calib_complete (init_calib_complete),
.app_wdf_mask ({`APPMASK_WIDTH{1'b0}}),
.sys_rst (RST_X_IN)
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
///// READ & WRITE PORT CONTROL (begin) ////////////////////////////////////////////
localparam M_REQ = 0;
localparam M_WRITE = 1;
localparam M_READ = 2;
reg [1:0] mode;
reg [31:0] remain, remain2;
reg rst_o;
always @(posedge ui_clk) rst_o <= (ui_clk_sync_rst || ~init_calib_complete); // High Active
assign USERCLK = ui_clk;
assign RST_O = rst_o;
assign D_BUSY = (mode != M_REQ); // DRAM busy
assign D_W = (mode == M_WRITE && app_rdy && app_wdf_rdy); // store one element
always @(posedge ui_clk) begin
if (RST_O) begin
mode <= M_REQ;
app_addr <= 0;
app_cmd <= 0;
app_en <= 0;
// app_wdf_data <= 0;
app_wdf_wren <= 0;
D_DOUT <= 0;
D_DOUTEN <= 0;
remain <= 0;
remain2 <= 0;
end else begin
case (mode)
///////////////////////////////////////////////////////////////// request
M_REQ: begin
D_DOUTEN <= 0;
case (D_REQ)
`DRAM_REQ_READ: begin ///// READ or LOAD request
app_cmd <= `DRAM_CMD_READ;
mode <= M_READ;
app_wdf_wren <= 0;
app_en <= 1;
app_addr <= D_INITADR; // param, initial address
remain <= D_ELEM; // param, the number of blocks to be read
remain2 <= D_ELEM; // param, the number of blocks to be read
end
`DRAM_REQ_WRITE: begin ///// WRITE or STORE request
app_cmd <= `DRAM_CMD_WRITE;
mode <= M_WRITE;
app_wdf_wren <= 0;
app_en <= 1;
app_addr <= D_INITADR; // param, initial address
remain <= D_ELEM; // the number of blocks to be written
end
default: begin
app_wdf_wren <= 0;
app_en <= 0;
end
endcase
end
///////////////////////////////////////////////////////////////// read
M_READ: begin
if (app_rdy) begin // read request is accepted.
app_addr <= mux((app_addr+8), 0, (app_addr==`MEM_LAST_ADDR));
remain2 <= remain2 - 1;
if (remain2 == 1) app_en <= 0;
end
D_DOUTEN <= app_rd_data_valid; // dram data_out enable
if (app_rd_data_valid) begin
D_DOUT <= app_rd_data;
remain <= remain - 1;
if (remain == 1) mode <= M_REQ;
end
end
///////////////////////////////////////////////////////////////// write
M_WRITE: begin
if (app_rdy && app_wdf_rdy) begin
// app_wdf_data <= D_DIN;
app_wdf_wren <= 1;
app_addr <= mux((app_addr+8), 0, (app_addr==`MEM_LAST_ADDR));
remain <= remain - 1;
if (remain == 1) begin
mode <= M_REQ;
app_en <= 0;
end
end else begin
app_wdf_wren <= 0;
end
end
endcase
end
end
///// READ & WRITE PORT CONTROL (end) ////////////////////////////////////////////
endmodule
`default_nettype wire
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
`define MODE_36 3'b111 // 36 or 32-bit
`define MODE_18 3'b110 // 18 or 16-bit
`define MODE_9 3'b101 // 9 or 8-bit
`define MODE_4 3'b100 // 4-bit
`define MODE_2 3'b010 // 32-bit
`define MODE_1 3'b001 // 32-bit
module \$__QLF_FACTOR_BRAM36_TDP (A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN, C1ADDR, C1DATA, C1EN, CLK1, CLK2, D1ADDR, D1DATA, D1EN);
parameter CFG_ABITS = 10;
parameter CFG_DBITS = 36;
parameter CFG_ENABLE_B = 4;
parameter CFG_ENABLE_D = 4;
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;
parameter [36863:0] INIT = 36864'bx;
input CLK1;
input CLK2;
input [CFG_ABITS-1:0] A1ADDR;
output [CFG_DBITS-1:0] A1DATA;
input A1EN;
input [CFG_ABITS-1:0] B1ADDR;
input [CFG_DBITS-1:0] B1DATA;
input [CFG_ENABLE_B-1:0] B1EN;
input [CFG_ABITS-1:0] C1ADDR;
output [CFG_DBITS-1:0] C1DATA;
input C1EN;
input [CFG_ABITS-1:0] D1ADDR;
input [CFG_DBITS-1:0] D1DATA;
input [CFG_ENABLE_B-1:0] D1EN;
wire FLUSH1;
wire FLUSH2;
wire SPLIT;
wire [15:0] RAM_ID;
wire PL_INIT_i;
wire PL_ENA_i;
wire PL_REN_i;
wire PL_CLK_i;
wire [1:0] PL_WEN_i;
wire [23:0] PL_ADDR_i;
wire [35:0] PL_DATA_i;
reg PL_INIT_o;
reg PL_ENA_o;
reg PL_REN_o;
reg PL_CLK_o;
reg [1:0] PL_WEN_o;
reg [23:0] PL_ADDR_o;
wire [35:0] PL_DATA_o;
wire [14:CFG_ABITS] A1ADDR_CMPL = {15-CFG_ABITS{1'b0}};
wire [14:CFG_ABITS] B1ADDR_CMPL = {15-CFG_ABITS{1'b0}};
wire [14:CFG_ABITS] C1ADDR_CMPL = {15-CFG_ABITS{1'b0}};
wire [14:CFG_ABITS] D1ADDR_CMPL = {15-CFG_ABITS{1'b0}};
wire [14:0] A1ADDR_TOTAL = {A1ADDR_CMPL, A1ADDR};
wire [14:0] B1ADDR_TOTAL = {B1ADDR_CMPL, B1ADDR};
wire [14:0] C1ADDR_TOTAL = {C1ADDR_CMPL, C1ADDR};
wire [14:0] D1ADDR_TOTAL = {D1ADDR_CMPL, D1ADDR};
wire [35:CFG_DBITS] A1DATA_CMPL;
wire [35:CFG_DBITS] C1DATA_CMPL;
wire [35:0] A1DATA_TOTAL = {A1DATA_CMPL, A1DATA};
wire [35:0] C1DATA_TOTAL = {C1DATA_CMPL, C1DATA};
wire [14:0] PORT_A_ADDR;
wire [14:0] PORT_B_ADDR;
case (CFG_DBITS)
1: begin
assign PORT_A_ADDR = A1EN ? A1ADDR_TOTAL : (B1EN ? B1ADDR_TOTAL : 15'd0);
assign PORT_B_ADDR = C1EN ? C1ADDR_TOTAL : (D1EN ? D1ADDR_TOTAL : 15'd0);
defparam _TECHMAP_REPLACE_.WMODE_A1_i = `MODE_1;
defparam _TECHMAP_REPLACE_.WMODE_A2_i = `MODE_1;
defparam _TECHMAP_REPLACE_.RMODE_A1_i = `MODE_1;
defparam _TECHMAP_REPLACE_.RMODE_A2_i = `MODE_1;
defparam _TECHMAP_REPLACE_.WMODE_B1_i = `MODE_1;
defparam _TECHMAP_REPLACE_.WMODE_B2_i = `MODE_1;
defparam _TECHMAP_REPLACE_.RMODE_B1_i = `MODE_1;
defparam _TECHMAP_REPLACE_.RMODE_B2_i = `MODE_1;
end
2: begin
assign PORT_A_ADDR = A1EN ? (A1ADDR_TOTAL << 1) : (B1EN ? (B1ADDR_TOTAL << 1) : 15'd0);
assign PORT_B_ADDR = C1EN ? (C1ADDR_TOTAL << 1) : (D1EN ? (D1ADDR_TOTAL << 1) : 15'd0);
defparam _TECHMAP_REPLACE_.WMODE_A1_i = `MODE_2;
defparam _TECHMAP_REPLACE_.WMODE_A2_i = `MODE_2;
defparam _TECHMAP_REPLACE_.RMODE_A1_i = `MODE_2;
defparam _TECHMAP_REPLACE_.RMODE_A2_i = `MODE_2;
defparam _TECHMAP_REPLACE_.WMODE_B1_i = `MODE_2;
defparam _TECHMAP_REPLACE_.WMODE_B2_i = `MODE_2;
defparam _TECHMAP_REPLACE_.RMODE_B1_i = `MODE_2;
defparam _TECHMAP_REPLACE_.RMODE_B2_i = `MODE_2;
end
4: begin
assign PORT_A_ADDR = A1EN ? (A1ADDR_TOTAL << 2) : (B1EN ? (B1ADDR_TOTAL << 2) : 15'd0);
assign PORT_B_ADDR = C1EN ? (C1ADDR_TOTAL << 2) : (D1EN ? (D1ADDR_TOTAL << 2) : 15'd0);
defparam _TECHMAP_REPLACE_.WMODE_A1_i = `MODE_4;
defparam _TECHMAP_REPLACE_.WMODE_A2_i = `MODE_4;
defparam _TECHMAP_REPLACE_.RMODE_A1_i = `MODE_4;
defparam _TECHMAP_REPLACE_.RMODE_A2_i = `MODE_4;
defparam _TECHMAP_REPLACE_.WMODE_B1_i = `MODE_4;
defparam _TECHMAP_REPLACE_.WMODE_B2_i = `MODE_4;
defparam _TECHMAP_REPLACE_.RMODE_B1_i = `MODE_4;
defparam _TECHMAP_REPLACE_.RMODE_B2_i = `MODE_4;
end
8, 9: begin
assign PORT_A_ADDR = A1EN ? (A1ADDR_TOTAL << 3) : (B1EN ? (B1ADDR_TOTAL << 3) : 15'd0);
assign PORT_B_ADDR = C1EN ? (C1ADDR_TOTAL << 3) : (D1EN ? (D1ADDR_TOTAL << 3) : 15'd0);
defparam _TECHMAP_REPLACE_.WMODE_A1_i = `MODE_9;
defparam _TECHMAP_REPLACE_.WMODE_A2_i = `MODE_9;
defparam _TECHMAP_REPLACE_.RMODE_A1_i = `MODE_9;
defparam _TECHMAP_REPLACE_.RMODE_A2_i = `MODE_9;
defparam _TECHMAP_REPLACE_.WMODE_B1_i = `MODE_9;
defparam _TECHMAP_REPLACE_.WMODE_B2_i = `MODE_9;
defparam _TECHMAP_REPLACE_.RMODE_B1_i = `MODE_9;
defparam _TECHMAP_REPLACE_.RMODE_B2_i = `MODE_9;
end
16, 18: begin
assign PORT_A_ADDR = A1EN ? (A1ADDR_TOTAL << 4) : (B1EN ? (B1ADDR_TOTAL << 4) : 15'd0);
assign PORT_B_ADDR = C1EN ? (C1ADDR_TOTAL << 4) : (D1EN ? (D1ADDR_TOTAL << 4) : 15'd0);
defparam _TECHMAP_REPLACE_.WMODE_A1_i = `MODE_18;
defparam _TECHMAP_REPLACE_.WMODE_A2_i = `MODE_18;
defparam _TECHMAP_REPLACE_.RMODE_A1_i = `MODE_18;
defparam _TECHMAP_REPLACE_.RMODE_A2_i = `MODE_18;
defparam _TECHMAP_REPLACE_.WMODE_B1_i = `MODE_18;
defparam _TECHMAP_REPLACE_.WMODE_B2_i = `MODE_18;
defparam _TECHMAP_REPLACE_.RMODE_B1_i = `MODE_18;
defparam _TECHMAP_REPLACE_.RMODE_B2_i = `MODE_18;
end
32, 36: begin
assign PORT_A_ADDR = A1EN ? (A1ADDR_TOTAL << 5) : (B1EN ? (B1ADDR_TOTAL << 5) : 15'd0);
assign PORT_B_ADDR = C1EN ? (C1ADDR_TOTAL << 5) : (D1EN ? (D1ADDR_TOTAL << 5) : 15'd0);
defparam _TECHMAP_REPLACE_.WMODE_A1_i = `MODE_36;
defparam _TECHMAP_REPLACE_.WMODE_A2_i = `MODE_36;
defparam _TECHMAP_REPLACE_.RMODE_A1_i = `MODE_36;
defparam _TECHMAP_REPLACE_.RMODE_A2_i = `MODE_36;
defparam _TECHMAP_REPLACE_.WMODE_B1_i = `MODE_36;
defparam _TECHMAP_REPLACE_.WMODE_B2_i = `MODE_36;
defparam _TECHMAP_REPLACE_.RMODE_B1_i = `MODE_36;
defparam _TECHMAP_REPLACE_.RMODE_B2_i = `MODE_36;
end
default: begin
assign PORT_A_ADDR = A1EN ? A1ADDR_TOTAL : (B1EN ? B1ADDR_TOTAL : 15'd0);
assign PORT_B_ADDR = C1EN ? C1ADDR_TOTAL : (D1EN ? D1ADDR_TOTAL : 15'd0);
defparam _TECHMAP_REPLACE_.WMODE_A1_i = `MODE_36;
defparam _TECHMAP_REPLACE_.WMODE_A2_i = `MODE_36;
defparam _TECHMAP_REPLACE_.RMODE_A1_i = `MODE_36;
defparam _TECHMAP_REPLACE_.RMODE_A2_i = `MODE_36;
defparam _TECHMAP_REPLACE_.WMODE_B1_i = `MODE_36;
defparam _TECHMAP_REPLACE_.WMODE_B2_i = `MODE_36;
defparam _TECHMAP_REPLACE_.RMODE_B1_i = `MODE_36;
defparam _TECHMAP_REPLACE_.RMODE_B2_i = `MODE_36;
end
endcase
assign SPLIT = 1'b0;
assign FLUSH1 = 1'b0;
assign FLUSH2 = 1'b0;
assign RAM_ID = 16'b0;
assign PL_INIT_i = 1'b0;
assign PL_ENA_i = 1'b0;
assign PL_REN_i = 1'b0;
assign PL_CLK_i = 1'b0;
assign PL_WEN_i = 2'b0;
assign PL_ADDR_i = 24'b0;
assign PL_DATA_i = 36'b0;
TDP_BRAM36 #(
.UPAE1_i(12'd10),
.UPAF1_i(12'd10),
.UPAE2_i(12'd10),
.UPAF2_i(12'd10),
.SYNC_FIFO1_i(1'b0),
.SYNC_FIFO2_i(1'b0),
.FMODE1_i(1'b0),
.FMODE2_i(1'b0),
.POWERDN1_i(1'b0),
.POWERDN2_i(1'b0),
.SLEEP1_i(1'b0),
.SLEEP2_i(1'b0),
.PROTECT1_i(1'b0),
.PROTECT2_i(1'b0),
.SPLIT_i(1'b0)
) _TECHMAP_REPLACE_ (
.WDATA_A1_i(B1DATA[17:0]),
.WDATA_A2_i(B1DATA[35:18]),
.RDATA_A1_o(A1DATA_TOTAL[17:0]),
.RDATA_A2_o(A1DATA_TOTAL[35:18]),
.ADDR_A1_i(PORT_A_ADDR),
.ADDR_A2_i(PORT_A_ADDR),
.CLK_A1_i(CLK1),
.CLK_A2_i(CLK1),
.REN_A1_i(A1EN),
.REN_A2_i(A1EN),
.WEN_A1_i(B1EN[0]),
.WEN_A2_i(B1EN[0]),
.BE_A1_i({B1EN[1],B1EN[0]}),
.BE_A2_i({B1EN[3],B1EN[2]}),
.WDATA_B1_i(D1DATA[17:0]),
.WDATA_B2_i(D1DATA[35:18]),
.RDATA_B1_o(C1DATA_TOTAL[17:0]),
.RDATA_B2_o(C1DATA_TOTAL[35:18]),
.ADDR_B1_i(PORT_B_ADDR),
.ADDR_B2_i(PORT_B_ADDR),
.CLK_B1_i(CLK2),
.CLK_B2_i(CLK2),
.REN_B1_i(C1EN),
.REN_B2_i(C1EN),
.WEN_B1_i(D1EN[0]),
.WEN_B2_i(D1EN[0]),
.BE_B1_i({D1EN[1],D1EN[0]}),
.BE_B2_i({D1EN[3],D1EN[2]}),
.FLUSH1_i(FLUSH1),
.FLUSH2_i(FLUSH2),
.RAM_ID_i(RAM_ID),
.PL_INIT_i(PL_INIT_i),
.PL_ENA_i(PL_ENA_i),
.PL_WEN_i(PL_WEN_i),
.PL_REN_i(PL_REN_i),
.PL_CLK_i(PL_CLK_i),
.PL_ADDR_i(PL_ADDR_i),
.PL_DATA_i(PL_DATA_i),
.PL_INIT_o(PL_INIT_o),
.PL_ENA_o(PL_ENA_o),
.PL_WEN_o(PL_WEN_o),
.PL_REN_o(PL_REN_o),
.PL_CLK_o(PL_CLK_o),
.PL_ADDR_o(),
.PL_DATA_o(PL_DATA_o)
);
endmodule
// ------------------------------------------------------------------------
module \$__QLF_FACTOR_BRAM18_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 10;
parameter CFG_DBITS = 18;
parameter CFG_ENABLE_B = 2;
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;
parameter [18431:0] INIT = 18432'bx;
input CLK2;
input CLK3;
input [CFG_ABITS-1:0] A1ADDR;
output [CFG_DBITS-1:0] A1DATA;
input A1EN;
input [CFG_ABITS-1:0] B1ADDR;
input [CFG_DBITS-1:0] B1DATA;
input [CFG_ENABLE_B-1:0] B1EN;
wire [13:0] A1ADDR_14;
wire [13:0] B1ADDR_14;
//wire [3:0] B1EN_4 = B1EN;
wire [1:0] DIP, DOP;
wire [15:0] DI, DO;
wire [15:0] DOBDO;
wire [1:0] DOPBDOP;
assign A1DATA = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
assign { DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
assign A1ADDR_14[13:CFG_ABITS] = 0;
assign A1ADDR_14[CFG_ABITS-1:0] = A1ADDR;
assign B1ADDR_14[13:CFG_ABITS] = 0;
assign B1ADDR_14[CFG_ABITS-1:0] = B1ADDR;
/*if (CFG_DBITS == 1) begin
assign WRITEDATAWIDTHB = 3'b000;
assign READDATAWIDTHA = 3'b000;
end else if (CFG_DBITS == 2) begin
assign WRITEDATAWIDTHB = 3'b001;
assign READDATAWIDTHA = 3'b001;
end else if (CFG_DBITS > 2 && CFG_DBITS <= 4) begin
assign WRITEDATAWIDTHB = 3'b010;
assign READDATAWIDTHA = 3'b010;
end else if (CFG_DBITS > 4 && CFG_DBITS <= 9) begin
assign WRITEDATAWIDTHB = 3'b011;
assign READDATAWIDTHA = 3'b011;
end else if (CFG_DBITS > 9 && CFG_DBITS <= 18) begin
//assign WRITEDATAWIDTHB = 3'b100;
assign READDATAWIDTHA = 3'b100;
end*/
generate if (CFG_DBITS > 8) begin
TDP_BRAM18 #(
//`include "brams_init_18.vh"
.READ_WIDTH_A(CFG_DBITS),
.READ_WIDTH_B(CFG_DBITS),
.WRITE_WIDTH_A(CFG_DBITS),
.WRITE_WIDTH_B(CFG_DBITS),
) _TECHMAP_REPLACE_ (
.WRITEDATAA(16'hFFFF),
.WRITEDATAAP(2'b11),
.READDATAA(DO[15:0]),
.READDATAAP(DOP[2:0]),
.ADDRA(A1ADDR_14),
.CLOCKA(CLK2),
.READENABLEA(A1EN),
.WRITEENABLEA(1'b0),
.BYTEENABLEA(2'b0),
//.WRITEDATAWIDTHA(3'b0),
//.READDATAWIDTHA(READDATAWIDTHA),
.WRITEDATAB(DI),
.WRITEDATABP(DIP),
.READDATAB(DOBDO),
.READDATABP(DOPBDOP),
.ADDRB(B1ADDR_14),
.CLOCKB(CLK3),
.READENABLEB(1'b0),
.WRITEENABLEB(1'b1),
.BYTEENABLEB(B1EN)
//.WRITEDATAWIDTHB(WRITEDATAWIDTHB),
//.READDATAWIDTHB(3'b0)
);
end else begin
TDP_BRAM18 #(
//`include "brams_init_16.vh"
) _TECHMAP_REPLACE_ (
.WRITEDATAA(16'hFFFF),
.WRITEDATAAP(2'b11),
.READDATAA(DO[15:0]),
.READDATAAP(DOP[2:0]),
.ADDRA(A1ADDR_14),
.CLOCKA(CLK2),
.READENABLEA(A1EN),
.WRITEENABLEA(1'b0),
.BYTEENABLEA(2'b0),
//.WRITEDATAWIDTHA(3'b0),
// .READDATAWIDTHA(READDATAWIDTHA),
.WRITEDATAB(DI),
.WRITEDATABP(DIP),
.READDATAB(DOBDO),
.READDATABP(DOPBDOP),
.ADDRB(B1ADDR_14),
.CLOCKB(CLK3),
.READENABLEB(1'b0),
.WRITEENABLEB(1'b1),
.BYTEENABLEB(B1EN)
//.WRITEDATAWIDTHB(WRITEDATAWIDTHB),
//.READDATAWIDTHB(3'b0)
);
end endgenerate
endmodule
module \$__QLF_FACTOR_BRAM36_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 10;
parameter CFG_DBITS = 36;
parameter CFG_ENABLE_B = 4;
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;
parameter [36863:0] INIT = 36864'bx;
localparam MODE_36 = 3'b111; // 36 or 32-bit
localparam MODE_18 = 3'b110; // 18 or 16-bit
localparam MODE_9 = 3'b101; // 9 or 8-bit
localparam MODE_4 = 3'b100; // 4-bit
localparam MODE_2 = 3'b010; // 32-bit
localparam MODE_1 = 3'b001; // 32-bit
input CLK2;
input CLK3;
input [CFG_ABITS-1:0] A1ADDR;
output [CFG_DBITS-1:0] A1DATA;
input A1EN;
input [CFG_ABITS-1:0] B1ADDR;
input [CFG_DBITS-1:0] B1DATA;
input [CFG_ENABLE_B-1:0] B1EN;
wire [14:0] A1ADDR_15;
wire [14:0] B1ADDR_15;
wire [35:0] DOBDO;
wire [14:CFG_ABITS] A1ADDR_CMPL;
wire [14:CFG_ABITS] B1ADDR_CMPL;
wire [35:CFG_DBITS] A1DATA_CMPL;
wire [35:CFG_DBITS] B1DATA_CMPL;
wire [14:0] A1ADDR_TOTAL;
wire [14:0] B1ADDR_TOTAL;
wire [35:0] A1DATA_TOTAL;
wire [35:0] B1DATA_TOTAL;
wire FLUSH1;
wire FLUSH2;
wire [15:0] RAM_ID;
wire PL_INIT_i;
wire PL_ENA_i;
wire PL_REN_i;
wire PL_CLK_i;
wire [1:0] PL_WEN_i;
wire [23:0] PL_ADDR_i;
wire [35:0] PL_DATA_i;
reg PL_INIT_o;
reg PL_ENA_o;
reg PL_REN_o;
reg PL_CLK_o;
reg [1:0] PL_WEN_o;
reg [23:0] PL_ADDR_o;
wire [35:0] PL_DATA_o;
wire [2:0] WMODE;
wire [2:0] RMODE;
assign A1ADDR_CMPL = {15-CFG_ABITS{1'b0}};
assign B1ADDR_CMPL = {15-CFG_ABITS{1'b0}};
assign A1ADDR_TOTAL = {A1ADDR_CMPL, A1ADDR};
assign B1ADDR_TOTAL = {B1ADDR_CMPL, B1ADDR};
assign A1DATA_TOTAL = {A1DATA_CMPL, A1DATA};
assign B1DATA_TOTAL = {B1DATA_CMPL, B1DATA};
case (CFG_DBITS)
1: begin
assign A1ADDR_15 = A1ADDR_TOTAL;
assign B1ADDR_15 = B1ADDR_TOTAL;
defparam _TECHMAP_REPLACE_.WMODE_A1_i = `MODE_1;
defparam _TECHMAP_REPLACE_.WMODE_A2_i = `MODE_1;
defparam _TECHMAP_REPLACE_.RMODE_A1_i = `MODE_1;
defparam _TECHMAP_REPLACE_.RMODE_A2_i = `MODE_1;
defparam _TECHMAP_REPLACE_.WMODE_B1_i = `MODE_1;
defparam _TECHMAP_REPLACE_.WMODE_B2_i = `MODE_1;
defparam _TECHMAP_REPLACE_.RMODE_B1_i = `MODE_1;
defparam _TECHMAP_REPLACE_.RMODE_B2_i = `MODE_1;
end
2: begin
assign A1ADDR_15 = A1ADDR_TOTAL << 1;
assign B1ADDR_15 = B1ADDR_TOTAL << 1;
defparam _TECHMAP_REPLACE_.WMODE_A1_i = `MODE_2;
defparam _TECHMAP_REPLACE_.WMODE_A2_i = `MODE_2;
defparam _TECHMAP_REPLACE_.RMODE_A1_i = `MODE_2;
defparam _TECHMAP_REPLACE_.RMODE_A2_i = `MODE_2;
defparam _TECHMAP_REPLACE_.WMODE_B1_i = `MODE_2;
defparam _TECHMAP_REPLACE_.WMODE_B2_i = `MODE_2;
defparam _TECHMAP_REPLACE_.RMODE_B1_i = `MODE_2;
defparam _TECHMAP_REPLACE_.RMODE_B2_i = `MODE_2;
end
4: begin
assign A1ADDR_15 = A1ADDR_TOTAL << 2;
assign B1ADDR_15 = B1ADDR_TOTAL << 2;
defparam _TECHMAP_REPLACE_.WMODE_A1_i = `MODE_4;
defparam _TECHMAP_REPLACE_.WMODE_A2_i = `MODE_4;
defparam _TECHMAP_REPLACE_.RMODE_A1_i = `MODE_4;
defparam _TECHMAP_REPLACE_.RMODE_A2_i = `MODE_4;
defparam _TECHMAP_REPLACE_.WMODE_B1_i = `MODE_4;
defparam _TECHMAP_REPLACE_.WMODE_B2_i = `MODE_4;
defparam _TECHMAP_REPLACE_.RMODE_B1_i = `MODE_4;
defparam _TECHMAP_REPLACE_.RMODE_B2_i = `MODE_4;
end
8, 9: begin
assign A1ADDR_15 = A1ADDR_TOTAL << 3;
assign B1ADDR_15 = B1ADDR_TOTAL << 3;
defparam _TECHMAP_REPLACE_.WMODE_A1_i = `MODE_9;
defparam _TECHMAP_REPLACE_.WMODE_A2_i = `MODE_9;
defparam _TECHMAP_REPLACE_.RMODE_A1_i = `MODE_9;
defparam _TECHMAP_REPLACE_.RMODE_A2_i = `MODE_9;
defparam _TECHMAP_REPLACE_.WMODE_B1_i = `MODE_9;
defparam _TECHMAP_REPLACE_.WMODE_B2_i = `MODE_9;
defparam _TECHMAP_REPLACE_.RMODE_B1_i = `MODE_9;
defparam _TECHMAP_REPLACE_.RMODE_B2_i = `MODE_9;
end
16, 18: begin
assign A1ADDR_15 = A1ADDR_TOTAL << 4;
assign B1ADDR_15 = B1ADDR_TOTAL << 4;
defparam _TECHMAP_REPLACE_.WMODE_A1_i = `MODE_18;
defparam _TECHMAP_REPLACE_.WMODE_A2_i = `MODE_18;
defparam _TECHMAP_REPLACE_.RMODE_A1_i = `MODE_18;
defparam _TECHMAP_REPLACE_.RMODE_A2_i = `MODE_18;
defparam _TECHMAP_REPLACE_.WMODE_B1_i = `MODE_18;
defparam _TECHMAP_REPLACE_.WMODE_B2_i = `MODE_18;
defparam _TECHMAP_REPLACE_.RMODE_B1_i = `MODE_18;
defparam _TECHMAP_REPLACE_.RMODE_B2_i = `MODE_18;
end
32, 36: begin
assign A1ADDR_15 = A1ADDR_TOTAL << 5;
assign B1ADDR_15 = B1ADDR_TOTAL << 5;
defparam _TECHMAP_REPLACE_.WMODE_A1_i = `MODE_36;
defparam _TECHMAP_REPLACE_.WMODE_A2_i = `MODE_36;
defparam _TECHMAP_REPLACE_.RMODE_A1_i = `MODE_36;
defparam _TECHMAP_REPLACE_.RMODE_A2_i = `MODE_36;
defparam _TECHMAP_REPLACE_.WMODE_B1_i = `MODE_36;
defparam _TECHMAP_REPLACE_.WMODE_B2_i = `MODE_36;
defparam _TECHMAP_REPLACE_.RMODE_B1_i = `MODE_36;
defparam _TECHMAP_REPLACE_.RMODE_B2_i = `MODE_36;
end
default: begin
assign A1ADDR_15 = A1ADDR_TOTAL;
assign B1ADDR_15 = B1ADDR_TOTAL;
defparam _TECHMAP_REPLACE_.WMODE_A1_i = `MODE_36;
defparam _TECHMAP_REPLACE_.WMODE_A2_i = `MODE_36;
defparam _TECHMAP_REPLACE_.RMODE_A1_i = `MODE_36;
defparam _TECHMAP_REPLACE_.RMODE_A2_i = `MODE_36;
defparam _TECHMAP_REPLACE_.WMODE_B1_i = `MODE_36;
defparam _TECHMAP_REPLACE_.WMODE_B2_i = `MODE_36;
defparam _TECHMAP_REPLACE_.RMODE_B1_i = `MODE_36;
defparam _TECHMAP_REPLACE_.RMODE_B2_i = `MODE_36;
end
endcase
assign FLUSH1 = 1'b0;
assign FLUSH2 = 1'b0;
assign RAM_ID = 16'b0;
assign PL_INIT_i = 1'b0;
assign PL_ENA_i = 1'b0;
assign PL_REN_i = 1'b0;
assign PL_CLK_i = 1'b0;
assign PL_WEN_i = 2'b0;
assign PL_ADDR_i = 24'b0;
assign PL_DATA_i = 36'b0;
TDP_BRAM36 #(
.UPAE1_i(12'd10),
.UPAF1_i(12'd10),
.UPAE2_i(12'd10),
.UPAF2_i(12'd10),
.SYNC_FIFO1_i(1'b0),
.SYNC_FIFO2_i(1'b0),
.FMODE1_i(1'b0),
.FMODE2_i(1'b0),
.POWERDN1_i(1'b0),
.POWERDN2_i(1'b0),
.SLEEP1_i(1'b0),
.SLEEP2_i(1'b0),
.PROTECT1_i(1'b0),
.PROTECT2_i(1'b0),
.SPLIT_i(1'b0)
) _TECHMAP_REPLACE_ (
.WDATA_A1_i(18'h3FFFF),
.WDATA_A2_i(18'h3FFFF),
.RDATA_A1_o(A1DATA_TOTAL[17:0]),
.RDATA_A2_o(A1DATA_TOTAL[35:18]),
.ADDR_A1_i(A1ADDR_15),
.ADDR_A2_i(A1ADDR_15),
.CLK_A1_i(CLK2),
.CLK_A2_i(CLK2),
.REN_A1_i(A1EN),
.REN_A2_i(A1EN),
.WEN_A1_i(1'b0),
.WEN_A2_i(1'b0),
.BE_A1_i({A1EN, A1EN}),
.BE_A2_i({A1EN, A1EN}),
.WDATA_B1_i(B1DATA[17:0]),
.WDATA_B2_i(B1DATA[35:18]),
.RDATA_B1_o(DOBDO[17:0]),
.RDATA_B2_o(DOBDO[35:18]),
.ADDR_B1_i(B1ADDR_15),
.ADDR_B2_i(B1ADDR_15),
.CLK_B1_i(CLK3),
.CLK_B2_i(CLK3),
.REN_B1_i(1'b0),
.REN_B2_i(1'b0),
.WEN_B1_i(B1EN[0]),
.WEN_B2_i(B1EN[0]),
.BE_B1_i(B1EN[1:0]),
.BE_B2_i(B1EN[3:2]),
.FLUSH1_i(FLUSH1),
.FLUSH2_i(FLUSH2),
.RAM_ID_i(RAM_ID),
.PL_INIT_i(PL_INIT_i),
.PL_ENA_i(PL_ENA_i),
.PL_WEN_i(PL_WEN_i),
.PL_REN_i(PL_REN_i),
.PL_CLK_i(PL_CLK_i),
.PL_ADDR_i(PL_ADDR_i),
.PL_DATA_i(PL_DATA_i),
.PL_INIT_o(PL_INIT_o),
.PL_ENA_o(PL_ENA_o),
.PL_WEN_o(PL_WEN_o),
.PL_REN_o(PL_REN_o),
.PL_CLK_o(PL_CLK_o),
.PL_ADDR_o(),
.PL_DATA_o(PL_DATA_o)
);
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sat Nov 19 19:40:17 2016
/////////////////////////////////////////////////////////////
module FPU_PIPELINED_FPADDSUB_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
output [31:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire Shift_reg_FLAGS_7_6, intAS, SIGN_FLAG_EXP, OP_FLAG_EXP, ZERO_FLAG_EXP,
SIGN_FLAG_SHT1, OP_FLAG_SHT1, ZERO_FLAG_SHT1, left_right_SHT2,
SIGN_FLAG_SHT2, OP_FLAG_SHT2, ZERO_FLAG_SHT2, SIGN_FLAG_SHT1SHT2,
ZERO_FLAG_SHT1SHT2, SIGN_FLAG_NRM, ZERO_FLAG_NRM, SIGN_FLAG_SFG,
ZERO_FLAG_SFG, inst_FSM_INPUT_ENABLE_state_next_1_, n463, n464, n465,
n466, n467, n468, n469, n470, n471, n472, n473, n474, n475, n476,
n477, n478, n479, n480, n481, n482, n483, n484, n485, n486, n487,
n488, n489, n490, n491, n492, n493, n494, n495, n496, n497, n498,
n499, n500, n501, n502, n503, n504, n505, n506, n507, n508, n509,
n510, n511, n512, n513, n514, n515, n516, n517, n518, n519, n520,
n521, n522, n523, n524, n525, n526, n527, n528, n529, n530, n531,
n532, n533, n534, n535, n536, n537, n538, n539, n540, n541, n542,
n543, n544, n545, n546, n547, n548, n549, n551, n552, n553, n554,
n555, n556, n557, n558, n559, n560, n561, n562, n563, n564, n565,
n566, n567, n568, n569, n570, n571, n572, n573, n574, n575, n576,
n577, n578, n579, n580, n581, n582, n583, n584, n585, n586, n587,
n588, n589, n590, n591, n592, n593, n594, n595, n596, n597, n598,
n599, n600, n601, n602, n603, n604, n605, n606, n607, n608, n609,
n610, n611, n612, n613, n614, n615, n616, n617, n618, n619, n620,
n621, n622, n623, n624, n625, n626, n627, n628, n629, n630, n631,
n632, n633, n634, n635, n636, n637, n638, n639, n640, n641, n642,
n643, n644, n645, n646, n647, n648, n649, n650, n651, n652, n653,
n654, n655, n656, n657, n658, n659, n660, n661, n662, n663, n664,
n665, n666, n667, n668, n669, n670, n671, n672, n673, n674, n675,
n676, n677, n678, n679, n680, n681, n682, n683, n684, n685, n686,
n687, n688, n689, n690, n691, n692, n693, n694, n695, n696, n697,
n698, n699, n700, n701, n702, n703, n704, n705, n706, n707, n708,
n709, n710, n711, n712, n713, n714, n715, n716, n717, n718, n719,
n720, n721, n722, n723, n724, n725, n726, n727, n728, n729, n730,
n731, n732, n733, n734, n735, n736, n737, n738, n739, n740, n741,
n742, n743, n744, n745, n746, n747, n748, n749, n750, n751, n752,
n753, n754, n755, n756, n757, n758, n759, n760, n761, n762, n763,
n764, n765, n766, n767, n769, n770, n771, n772, n773, n774, n775,
n776, n777, n778, n779, n780, n781, n782, n783, n784, n785, n786,
n787, n788, n789, n790, n791, n792, n793, n794, n795, n796, n797,
n798, n799, n800, n801, n802, n803, n804, n805, n806, n807, n808,
n809, n810, n811, n812, n813, n814, n815, n816, n817, n818, n819,
n820, n821, n822, n823, n824, n825, n826, n827, n828, n829, n830,
n831, n832, n833, n834, n835, n836, n837, n838, n839, n840, n841,
n842, n843, n844, n845, n846, n847, n848, n849, n850, n851, n852,
n853, n854, n855, n856, n857, n858, n859, n860, n861, n862, n863,
n864, n865, n866, n867, n868, n869, n870, n871,
DP_OP_15J48_123_3372_n8, DP_OP_15J48_123_3372_n7,
DP_OP_15J48_123_3372_n6, DP_OP_15J48_123_3372_n5,
DP_OP_15J48_123_3372_n4, intadd_50_B_2_, intadd_50_B_1_,
intadd_50_B_0_, intadd_50_CI, intadd_50_SUM_2_, intadd_50_SUM_1_,
intadd_50_SUM_0_, intadd_50_n3, intadd_50_n2, intadd_50_n1,
DP_OP_285J48_122_2126_n74, DP_OP_285J48_122_2126_n73,
DP_OP_285J48_122_2126_n72, DP_OP_285J48_122_2126_n71,
DP_OP_285J48_122_2126_n70, n873, n874, n875, n876, n877, n878, n879,
n880, n881, n882, n883, n884, n885, n886, n887, n888, n889, n890,
n891, n892, n893, n894, n895, n896, n897, n898, n899, n900, n901,
n902, n903, n904, n905, n906, n907, n908, n909, n910, n911, n912,
n913, n914, n915, n916, n917, n918, n919, n920, n921, n922, n923,
n924, n925, n926, n927, n928, n929, n930, n931, n932, n933, n934,
n935, n936, n937, n938, n939, n940, n941, n942, n943, n944, n945,
n946, n947, n948, n949, n950, n951, n952, n953, n954, n955, n956,
n957, n958, n959, n960, n961, n962, n963, n964, n965, n966, n967,
n968, n969, n970, n971, n972, n973, n974, n975, n976, n977, n978,
n979, n980, n981, n982, n983, n984, n985, n986, n987, n988, n989,
n990, n991, n992, n993, n994, n995, n996, n997, n998, n999, n1000,
n1001, n1002, n1003, n1004, n1005, n1006, n1007, n1008, n1009, n1010,
n1011, n1012, n1013, n1014, n1015, n1016, n1017, n1018, n1019, n1020,
n1021, n1022, n1023, n1024, n1025, n1026, n1027, n1028, n1029, n1030,
n1031, n1032, n1033, n1034, n1035, n1036, n1037, n1038, n1039, n1040,
n1041, n1042, n1043, n1044, n1045, n1046, n1047, n1048, n1049, n1050,
n1051, n1052, n1053, n1054, n1055, n1056, n1057, n1058, n1059, n1060,
n1061, n1062, n1063, n1064, n1065, n1066, n1067, n1068, n1069, n1070,
n1071, n1072, n1073, n1074, n1075, n1076, n1077, n1078, n1079, n1080,
n1081, n1082, n1083, n1084, n1085, n1086, n1087, n1088, n1089, n1090,
n1091, n1092, n1093, n1094, n1095, n1096, n1097, n1098, n1099, n1100,
n1101, n1102, n1103, n1104, n1105, n1106, n1107, n1108, n1109, n1110,
n1111, n1112, n1113, n1114, n1115, n1116, n1117, n1118, n1119, n1120,
n1121, n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129, n1130,
n1131, n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139, n1140,
n1141, n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149, n1150,
n1151, n1152, n1153, n1154, n1155, n1156, n1157, n1158, n1159, n1160,
n1161, n1162, n1163, n1164, n1165, n1166, n1167, n1168, n1169, n1170,
n1171, n1172, n1173, n1174, n1175, n1176, n1177, n1178, n1179, n1180,
n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189, n1190,
n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200,
n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210,
n1211, n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220,
n1221, n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1230,
n1231, n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240,
n1241, n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250,
n1251, n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260,
n1261, n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270,
n1271, n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280,
n1281, n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290,
n1291, n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300,
n1301, n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310,
n1311, n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320,
n1321, n1322, n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330,
n1331, n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340,
n1341, n1342, n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350,
n1351, n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360,
n1361, n1362, n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370,
n1371, n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380,
n1381, n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390,
n1391, n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400,
n1401, n1402, n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410,
n1411, n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420,
n1421, n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430,
n1431, n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440,
n1441, n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450,
n1451, n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460,
n1461, n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470,
n1471, n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1480,
n1481, n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490,
n1491, n1492, n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500,
n1501, n1502, n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510,
n1511, n1512, n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520,
n1521, n1522, n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530,
n1531, n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540,
n1541, n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550,
n1551, n1552, n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560,
n1561, n1562, n1563, n1564, n1565, n1566, n1567, n1568, n1569, n1570,
n1571, n1572, n1573, n1574, n1575, n1576, n1577, n1578, n1579, n1580,
n1581, n1582, n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590,
n1591, n1592, n1593, n1594, n1595, n1596, n1597, n1598, n1599, n1600,
n1601, n1602, n1603, n1604, n1605, n1606, n1607, n1608, n1609, n1610,
n1611, n1612, n1613, n1614, n1615, n1616, n1617, n1618, n1619, n1620,
n1621, n1622, n1623, n1624, n1625, n1626, n1627, n1628, n1629, n1630,
n1631, n1632, n1633, n1634, n1635, n1636, n1637, n1638, n1639, n1640,
n1641, n1642, n1643, n1644, n1645, n1646, n1647, n1648, n1649, n1650,
n1651, n1652, n1653, n1654, n1655, n1656, n1657, n1658, n1659, n1660,
n1661, n1662, n1663, n1664, n1665, n1666, n1667, n1668, n1669, n1670,
n1671, n1672, n1673, n1674, n1675, n1676, n1677, n1678, n1679, n1680,
n1681, n1682, n1683, n1684, n1685, n1686, n1687, n1688, n1689, n1690,
n1691, n1692, n1693, n1694, n1695, n1696, n1697, n1698, n1699, n1700,
n1701, n1702, n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710,
n1711, n1712, n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720,
n1721, n1722, n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1730,
n1731, n1732, n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740,
n1741, n1742, n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750,
n1751, n1752, n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760,
n1761, n1762, n1763, n1764, n1765;
wire [3:0] Shift_reg_FLAGS_7;
wire [31:0] intDX_EWSW;
wire [31:0] intDY_EWSW;
wire [30:0] DMP_EXP_EWSW;
wire [27:0] DmP_EXP_EWSW;
wire [30:0] DMP_SHT1_EWSW;
wire [22:0] DmP_mant_SHT1_SW;
wire [4:0] Shift_amount_SHT1_EWR;
wire [25:0] Raw_mant_NRM_SWR;
wire [25:0] Data_array_SWR;
wire [30:0] DMP_SHT2_EWSW;
wire [4:2] shift_value_SHT2_EWR;
wire [7:0] DMP_exp_NRM2_EW;
wire [7:0] DMP_exp_NRM_EW;
wire [4:0] LZD_output_NRM2_EW;
wire [4:1] exp_rslt_NRM2_EW1;
wire [30:0] DMP_SFG;
wire [25:0] DmP_mant_SFG_SWR;
wire [11:10] DmP_mant_SFG_SWR_signed;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS inst_ShiftRegister_Q_reg_6_ ( .D(n869), .CK(clk), .RN(n1724), .Q(
Shift_reg_FLAGS_7_6), .QN(n928) );
DFFRXLTS inst_ShiftRegister_Q_reg_3_ ( .D(n866), .CK(clk), .RN(n1724), .Q(
Shift_reg_FLAGS_7[3]) );
DFFRXLTS inst_ShiftRegister_Q_reg_2_ ( .D(n865), .CK(clk), .RN(n1763), .Q(
Shift_reg_FLAGS_7[2]), .QN(n1717) );
DFFRXLTS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n830), .CK(clk), .RN(n1728), .Q(
intAS) );
DFFRXLTS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n829), .CK(clk), .RN(n1728), .Q(
left_right_SHT2), .QN(n888) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n764), .CK(clk), .RN(n1734),
.Q(Shift_amount_SHT1_EWR[2]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n763), .CK(clk), .RN(n1734),
.Q(Shift_amount_SHT1_EWR[3]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n762), .CK(clk), .RN(n1734),
.Q(Shift_amount_SHT1_EWR[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_0_ ( .D(n753), .CK(clk), .RN(n1738), .Q(
DMP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_1_ ( .D(n752), .CK(clk), .RN(n1135), .Q(
DMP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_2_ ( .D(n751), .CK(clk), .RN(n1739), .Q(
DMP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_3_ ( .D(n750), .CK(clk), .RN(n1136), .Q(
DMP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_4_ ( .D(n749), .CK(clk), .RN(n1134), .Q(
DMP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_5_ ( .D(n748), .CK(clk), .RN(n1139), .Q(
DMP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_6_ ( .D(n747), .CK(clk), .RN(n1138), .Q(
DMP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_7_ ( .D(n746), .CK(clk), .RN(n1735), .Q(
DMP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_8_ ( .D(n745), .CK(clk), .RN(n1134), .Q(
DMP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_9_ ( .D(n744), .CK(clk), .RN(n1735), .Q(
DMP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_10_ ( .D(n743), .CK(clk), .RN(n1738), .Q(
DMP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_11_ ( .D(n742), .CK(clk), .RN(n1135), .Q(
DMP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_12_ ( .D(n741), .CK(clk), .RN(n1739), .Q(
DMP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_13_ ( .D(n740), .CK(clk), .RN(n1136), .Q(
DMP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_14_ ( .D(n739), .CK(clk), .RN(n1134), .Q(
DMP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_15_ ( .D(n738), .CK(clk), .RN(n1139), .Q(
DMP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_16_ ( .D(n737), .CK(clk), .RN(n1138), .Q(
DMP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_17_ ( .D(n736), .CK(clk), .RN(n1735), .Q(
DMP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_18_ ( .D(n735), .CK(clk), .RN(n1138), .Q(
DMP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_19_ ( .D(n734), .CK(clk), .RN(n1736), .Q(
DMP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_20_ ( .D(n733), .CK(clk), .RN(n1139), .Q(
DMP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_21_ ( .D(n732), .CK(clk), .RN(n1134), .Q(
DMP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_22_ ( .D(n731), .CK(clk), .RN(n1735), .Q(
DMP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_28_ ( .D(n725), .CK(clk), .RN(n1138), .Q(
DMP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_29_ ( .D(n724), .CK(clk), .RN(n1736), .Q(
DMP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_30_ ( .D(n723), .CK(clk), .RN(n1737), .Q(
DMP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n722), .CK(clk), .RN(n1737), .Q(
OP_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n721), .CK(clk), .RN(n1737), .Q(
ZERO_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n720), .CK(clk), .RN(n1737), .Q(
SIGN_FLAG_EXP) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n719), .CK(clk), .RN(n1737), .Q(
DMP_SHT1_EWSW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n718), .CK(clk), .RN(n1737), .Q(
DMP_SHT2_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n716), .CK(clk), .RN(n1737), .Q(
DMP_SHT1_EWSW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n715), .CK(clk), .RN(n1737), .Q(
DMP_SHT2_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n713), .CK(clk), .RN(n1735), .Q(
DMP_SHT1_EWSW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n712), .CK(clk), .RN(n1736), .Q(
DMP_SHT2_EWSW[2]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_2_ ( .D(n711), .CK(clk), .RN(n1738), .Q(
DMP_SFG[2]), .QN(n1700) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n710), .CK(clk), .RN(n1138), .Q(
DMP_SHT1_EWSW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n709), .CK(clk), .RN(n1135), .Q(
DMP_SHT2_EWSW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n707), .CK(clk), .RN(n1739), .Q(
DMP_SHT1_EWSW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n706), .CK(clk), .RN(n1136), .Q(
DMP_SHT2_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n704), .CK(clk), .RN(n1134), .Q(
DMP_SHT1_EWSW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n703), .CK(clk), .RN(n1736), .Q(
DMP_SHT2_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n701), .CK(clk), .RN(n1738), .Q(
DMP_SHT1_EWSW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n700), .CK(clk), .RN(n1138), .Q(
DMP_SHT2_EWSW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n698), .CK(clk), .RN(n1135), .Q(
DMP_SHT1_EWSW[7]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n697), .CK(clk), .RN(n1739), .Q(
DMP_SHT2_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n695), .CK(clk), .RN(n1136), .Q(
DMP_SHT1_EWSW[8]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n694), .CK(clk), .RN(n1134), .Q(
DMP_SHT2_EWSW[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n692), .CK(clk), .RN(n1139), .Q(
DMP_SHT1_EWSW[9]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n691), .CK(clk), .RN(n1138), .Q(
DMP_SHT2_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n689), .CK(clk), .RN(n1740), .Q(
DMP_SHT1_EWSW[10]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n688), .CK(clk), .RN(n1740), .Q(
DMP_SHT2_EWSW[10]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n686), .CK(clk), .RN(n1740), .Q(
DMP_SHT1_EWSW[11]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n685), .CK(clk), .RN(n1740), .Q(
DMP_SHT2_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n683), .CK(clk), .RN(n1740), .Q(
DMP_SHT1_EWSW[12]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n682), .CK(clk), .RN(n1740), .Q(
DMP_SHT2_EWSW[12]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n680), .CK(clk), .RN(n1740), .Q(
DMP_SHT1_EWSW[13]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n679), .CK(clk), .RN(n1740), .Q(
DMP_SHT2_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n677), .CK(clk), .RN(n1740), .Q(
DMP_SHT1_EWSW[14]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n676), .CK(clk), .RN(n1740), .Q(
DMP_SHT2_EWSW[14]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n674), .CK(clk), .RN(n1741), .Q(
DMP_SHT1_EWSW[15]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n673), .CK(clk), .RN(n1741), .Q(
DMP_SHT2_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n671), .CK(clk), .RN(n1741), .Q(
DMP_SHT1_EWSW[16]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n670), .CK(clk), .RN(n1741), .Q(
DMP_SHT2_EWSW[16]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n668), .CK(clk), .RN(n1741), .Q(
DMP_SHT1_EWSW[17]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n667), .CK(clk), .RN(n1741), .Q(
DMP_SHT2_EWSW[17]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n665), .CK(clk), .RN(n1741), .Q(
DMP_SHT1_EWSW[18]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n664), .CK(clk), .RN(n1741), .Q(
DMP_SHT2_EWSW[18]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n662), .CK(clk), .RN(n1741), .Q(
DMP_SHT1_EWSW[19]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n661), .CK(clk), .RN(n1741), .Q(
DMP_SHT2_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n659), .CK(clk), .RN(n1742), .Q(
DMP_SHT1_EWSW[20]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n658), .CK(clk), .RN(n1742), .Q(
DMP_SHT2_EWSW[20]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n656), .CK(clk), .RN(n1742), .Q(
DMP_SHT1_EWSW[21]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n655), .CK(clk), .RN(n1742), .Q(
DMP_SHT2_EWSW[21]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n653), .CK(clk), .RN(n1742), .Q(
DMP_SHT1_EWSW[22]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n652), .CK(clk), .RN(n1742), .Q(
DMP_SHT2_EWSW[22]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n650), .CK(clk), .RN(n1742), .Q(
DMP_SHT1_EWSW[23]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n649), .CK(clk), .RN(n1742), .Q(
DMP_SHT2_EWSW[23]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_23_ ( .D(n648), .CK(clk), .RN(n1742), .Q(
DMP_SFG[23]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n647), .CK(clk), .RN(n1742), .Q(
DMP_exp_NRM_EW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n645), .CK(clk), .RN(n1743), .Q(
DMP_SHT1_EWSW[24]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n644), .CK(clk), .RN(n1743), .Q(
DMP_SHT2_EWSW[24]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_24_ ( .D(n643), .CK(clk), .RN(n1743), .Q(
DMP_SFG[24]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n642), .CK(clk), .RN(n1743), .Q(
DMP_exp_NRM_EW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n640), .CK(clk), .RN(n1743), .Q(
DMP_SHT1_EWSW[25]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n639), .CK(clk), .RN(n1743), .Q(
DMP_SHT2_EWSW[25]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_25_ ( .D(n638), .CK(clk), .RN(n1743), .Q(
DMP_SFG[25]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n637), .CK(clk), .RN(n1743), .Q(
DMP_exp_NRM_EW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n635), .CK(clk), .RN(n1743), .Q(
DMP_SHT1_EWSW[26]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n634), .CK(clk), .RN(n1743), .Q(
DMP_SHT2_EWSW[26]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_26_ ( .D(n633), .CK(clk), .RN(n1744), .Q(
DMP_SFG[26]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n632), .CK(clk), .RN(n1744), .Q(
DMP_exp_NRM_EW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n630), .CK(clk), .RN(n1744), .Q(
DMP_SHT1_EWSW[27]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n629), .CK(clk), .RN(n1744), .Q(
DMP_SHT2_EWSW[27]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_27_ ( .D(n628), .CK(clk), .RN(n1744), .Q(
DMP_SFG[27]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n627), .CK(clk), .RN(n1744), .Q(
DMP_exp_NRM_EW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n625), .CK(clk), .RN(n1744), .Q(
DMP_SHT1_EWSW[28]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n624), .CK(clk), .RN(n1744), .Q(
DMP_SHT2_EWSW[28]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_28_ ( .D(n623), .CK(clk), .RN(n1744), .Q(
DMP_SFG[28]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n622), .CK(clk), .RN(n1744), .Q(
DMP_exp_NRM_EW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n620), .CK(clk), .RN(n1745), .Q(
DMP_SHT1_EWSW[29]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n619), .CK(clk), .RN(n1745), .Q(
DMP_SHT2_EWSW[29]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_29_ ( .D(n618), .CK(clk), .RN(n1745), .Q(
DMP_SFG[29]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n617), .CK(clk), .RN(n1745), .Q(
DMP_exp_NRM_EW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n615), .CK(clk), .RN(n1745), .Q(
DMP_SHT1_EWSW[30]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n614), .CK(clk), .RN(n1745), .Q(
DMP_SHT2_EWSW[30]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_30_ ( .D(n613), .CK(clk), .RN(n1745), .Q(
DMP_SFG[30]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n612), .CK(clk), .RN(n1745), .Q(
DMP_exp_NRM_EW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_0_ ( .D(n610), .CK(clk), .RN(n1745), .Q(
DmP_EXP_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n609), .CK(clk), .RN(n1745), .Q(
DmP_mant_SHT1_SW[0]), .QN(n1715) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_1_ ( .D(n608), .CK(clk), .RN(n1746), .Q(
DmP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_2_ ( .D(n606), .CK(clk), .RN(n1746), .Q(
DmP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_3_ ( .D(n604), .CK(clk), .RN(n1746), .Q(
DmP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_4_ ( .D(n602), .CK(clk), .RN(n1746), .Q(
DmP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_5_ ( .D(n600), .CK(clk), .RN(n1746), .Q(
DmP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_6_ ( .D(n598), .CK(clk), .RN(n1747), .Q(
DmP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_7_ ( .D(n596), .CK(clk), .RN(n1747), .Q(
DmP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_8_ ( .D(n594), .CK(clk), .RN(n1747), .Q(
DmP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_9_ ( .D(n592), .CK(clk), .RN(n1747), .Q(
DmP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_10_ ( .D(n590), .CK(clk), .RN(n1747), .Q(
DmP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_11_ ( .D(n588), .CK(clk), .RN(n1748), .Q(
DmP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_12_ ( .D(n586), .CK(clk), .RN(n1748), .Q(
DmP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_13_ ( .D(n584), .CK(clk), .RN(n1748), .Q(
DmP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_14_ ( .D(n582), .CK(clk), .RN(n1748), .Q(
DmP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_15_ ( .D(n580), .CK(clk), .RN(n1748), .Q(
DmP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_16_ ( .D(n578), .CK(clk), .RN(n1749), .Q(
DmP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_17_ ( .D(n576), .CK(clk), .RN(n1749), .Q(
DmP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_18_ ( .D(n574), .CK(clk), .RN(n1749), .Q(
DmP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_19_ ( .D(n572), .CK(clk), .RN(n1749), .Q(
DmP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_20_ ( .D(n570), .CK(clk), .RN(n1749), .Q(
DmP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_21_ ( .D(n568), .CK(clk), .RN(n1750), .Q(
DmP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_22_ ( .D(n566), .CK(clk), .RN(n1750), .Q(
DmP_EXP_EWSW[22]) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n557), .CK(clk), .RN(n1751), .Q(
ZERO_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n556), .CK(clk), .RN(n1751), .Q(
ZERO_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n555), .CK(clk), .RN(n1751), .Q(
ZERO_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n554), .CK(clk), .RN(n1751), .Q(
ZERO_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n553), .CK(clk), .RN(n1751), .Q(
ZERO_FLAG_SHT1SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n551), .CK(clk), .RN(n1751), .Q(
OP_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n1716), .CK(clk), .RN(n1763), .Q(
OP_FLAG_SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n548), .CK(clk), .RN(n1751), .Q(
SIGN_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n547), .CK(clk), .RN(n1751), .Q(
SIGN_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n546), .CK(clk), .RN(n1751), .Q(
SIGN_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n545), .CK(clk), .RN(n1752), .Q(
SIGN_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n544), .CK(clk), .RN(n1752), .Q(
SIGN_FLAG_SHT1SHT2) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n527), .CK(clk), .RN(n1759), .Q(
Raw_mant_NRM_SWR[15]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n526), .CK(clk), .RN(n1759), .Q(
Raw_mant_NRM_SWR[16]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n524), .CK(clk), .RN(n1759), .Q(
Raw_mant_NRM_SWR[18]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n516), .CK(clk), .RN(n1757), .Q(
LZD_output_NRM2_EW[3]), .QN(n1663) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n514), .CK(clk), .RN(n1757), .Q(
LZD_output_NRM2_EW[2]), .QN(n1665) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n513), .CK(clk), .RN(n1757), .Q(
LZD_output_NRM2_EW[1]), .QN(n1664) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n512), .CK(clk), .RN(n1757), .Q(
LZD_output_NRM2_EW[4]), .QN(n1671) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n488), .CK(clk), .RN(n1755), .Q(
DmP_mant_SFG_SWR[0]), .QN(n922) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n487), .CK(clk), .RN(n1755), .Q(
DmP_mant_SFG_SWR[1]), .QN(n923) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n484), .CK(clk), .RN(n1755), .Q(
DmP_mant_SFG_SWR[4]), .QN(n1673) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n483), .CK(clk), .RN(n1755), .Q(
DmP_mant_SFG_SWR[5]), .QN(n1666) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n482), .CK(clk), .RN(n1755), .Q(
DmP_mant_SFG_SWR[6]), .QN(n1672) );
CMPR32X2TS intadd_50_U4 ( .A(n1700), .B(intadd_50_B_0_), .C(intadd_50_CI),
.CO(intadd_50_n3), .S(intadd_50_SUM_0_) );
CMPR32X2TS intadd_50_U3 ( .A(n1710), .B(intadd_50_B_1_), .C(intadd_50_n3),
.CO(intadd_50_n2), .S(intadd_50_SUM_1_) );
CMPR32X2TS intadd_50_U2 ( .A(n1711), .B(intadd_50_B_2_), .C(intadd_50_n2),
.CO(intadd_50_n1), .S(intadd_50_SUM_2_) );
AFCSIHCONX2TS DP_OP_285J48_122_2126_U78 ( .A(DMP_SFG[8]), .B(
DmP_mant_SFG_SWR_signed[10]), .CS(DP_OP_285J48_122_2126_n74), .CO0N(
DP_OP_285J48_122_2126_n73), .CO1N(DP_OP_285J48_122_2126_n72) );
AFCSHCINX2TS DP_OP_285J48_122_2126_U77 ( .CI1N(DP_OP_285J48_122_2126_n72),
.B(DmP_mant_SFG_SWR_signed[11]), .A(DMP_SFG[9]), .CI0N(
DP_OP_285J48_122_2126_n73), .CS(DP_OP_285J48_122_2126_n74), .CO1(
DP_OP_285J48_122_2126_n70), .CO0(DP_OP_285J48_122_2126_n71) );
DFFRXLTS Ready_reg_Q_reg_0_ ( .D(Shift_reg_FLAGS_7[0]), .CK(clk), .RN(n1728),
.Q(ready) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n559), .CK(clk), .RN(n1750), .Q(
underflow_flag) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n552), .CK(clk), .RN(n1751), .Q(
zero_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n505), .CK(clk), .RN(n1753), .Q(
final_result_ieee[7]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n503), .CK(clk), .RN(n1753), .Q(
final_result_ieee[6]) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n558), .CK(clk), .RN(n1755), .Q(
overflow_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n754), .CK(clk), .RN(n1756), .Q(
final_result_ieee[30]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n543), .CK(clk), .RN(n1756), .Q(
final_result_ieee[31]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n761), .CK(clk), .RN(n1756), .Q(
final_result_ieee[23]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n760), .CK(clk), .RN(n1756), .Q(
final_result_ieee[24]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n759), .CK(clk), .RN(n1756), .Q(
final_result_ieee[25]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n758), .CK(clk), .RN(n1756), .Q(
final_result_ieee[26]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n757), .CK(clk), .RN(n1756), .Q(
final_result_ieee[27]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n756), .CK(clk), .RN(n1756), .Q(
final_result_ieee[28]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n755), .CK(clk), .RN(n1756), .Q(
final_result_ieee[29]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n530), .CK(clk), .RN(n1758), .Q(
Raw_mant_NRM_SWR[12]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n528), .CK(clk), .RN(n1759), .Q(
Raw_mant_NRM_SWR[14]), .QN(n1659) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n827), .CK(clk), .RN(n1728), .Q(
intDY_EWSW[1]), .QN(n1765) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n539), .CK(clk), .RN(n1752), .Q(
Raw_mant_NRM_SWR[3]), .QN(n1647) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n1724), .Q(
inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n1640) );
DFFRX2TS inst_ShiftRegister_Q_reg_5_ ( .D(n868), .CK(clk), .RN(n1724), .Q(
n1636), .QN(n1714) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n858), .CK(clk), .RN(n1725), .Q(
intDX_EWSW[4]), .QN(n1637) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n536), .CK(clk), .RN(n1752), .Q(
Raw_mant_NRM_SWR[6]), .QN(n1702) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n838), .CK(clk), .RN(n1727),
.Q(intDX_EWSW[24]), .QN(n1707) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n837), .CK(clk), .RN(n1727),
.Q(intDX_EWSW[25]), .QN(n1649) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n808), .CK(clk), .RN(n1730),
.Q(intDY_EWSW[20]), .QN(n1688) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n814), .CK(clk), .RN(n1729),
.Q(intDY_EWSW[14]), .QN(n1686) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n815), .CK(clk), .RN(n1729),
.Q(intDY_EWSW[13]), .QN(n1680) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n816), .CK(clk), .RN(n1729),
.Q(intDY_EWSW[12]), .QN(n1685) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n810), .CK(clk), .RN(n1730),
.Q(intDY_EWSW[18]), .QN(n1694) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n811), .CK(clk), .RN(n1730),
.Q(intDY_EWSW[17]), .QN(n1678) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n813), .CK(clk), .RN(n1729),
.Q(intDY_EWSW[15]), .QN(n1643) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n817), .CK(clk), .RN(n1729),
.Q(intDY_EWSW[11]), .QN(n1660) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n820), .CK(clk), .RN(n1729), .Q(
intDY_EWSW[8]), .QN(n1682) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n825), .CK(clk), .RN(n1728), .Q(
intDY_EWSW[3]), .QN(n1677) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n805), .CK(clk), .RN(n1730),
.Q(intDY_EWSW[23]), .QN(n1691) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n806), .CK(clk), .RN(n1730),
.Q(intDY_EWSW[22]), .QN(n1644) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n807), .CK(clk), .RN(n1730),
.Q(intDY_EWSW[21]), .QN(n1681) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n798), .CK(clk), .RN(n1731),
.Q(intDY_EWSW[30]), .QN(n1692) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n799), .CK(clk), .RN(n1731),
.Q(intDY_EWSW[29]), .QN(n1645) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n802), .CK(clk), .RN(n1731),
.Q(intDY_EWSW[26]), .QN(n1689) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n803), .CK(clk), .RN(n1730),
.Q(intDY_EWSW[25]), .QN(n1676) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n846), .CK(clk), .RN(n1726),
.Q(intDX_EWSW[16]), .QN(n1656) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n855), .CK(clk), .RN(n1725), .Q(
intDX_EWSW[7]), .QN(n1638) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n856), .CK(clk), .RN(n1725), .Q(
intDX_EWSW[6]), .QN(n1657) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n857), .CK(clk), .RN(n1725), .Q(
intDX_EWSW[5]), .QN(n1651) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n525), .CK(clk), .RN(n1759), .Q(
Raw_mant_NRM_SWR[17]), .QN(n1674) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n796), .CK(clk), .RN(n1731), .Q(
Data_array_SWR[25]), .QN(n1720) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n795), .CK(clk), .RN(n1731), .Q(
Data_array_SWR[24]), .QN(n1721) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n509), .CK(clk), .RN(n1753), .Q(
final_result_ieee[9]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n520), .CK(clk), .RN(n1759), .Q(
Raw_mant_NRM_SWR[22]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n517), .CK(clk), .RN(n1759), .Q(
Raw_mant_NRM_SWR[25]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n497), .CK(clk), .RN(n1754), .Q(
final_result_ieee[3]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n506), .CK(clk), .RN(n1753), .Q(
final_result_ieee[13]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n542), .CK(clk), .RN(n1758), .Q(
Raw_mant_NRM_SWR[0]), .QN(n1639) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n826), .CK(clk), .RN(n1728), .Q(
intDY_EWSW[2]), .QN(n1683) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n788), .CK(clk), .RN(n1732), .Q(
Data_array_SWR[17]), .QN(n1719) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n859), .CK(clk), .RN(n1725), .Q(
intDX_EWSW[3]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n839), .CK(clk), .RN(n1727),
.Q(intDX_EWSW[23]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n847), .CK(clk), .RN(n1726),
.Q(intDX_EWSW[15]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n841), .CK(clk), .RN(n1727),
.Q(intDX_EWSW[21]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n849), .CK(clk), .RN(n1726),
.Q(intDX_EWSW[13]) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n767), .CK(clk), .RN(n1734), .Q(
shift_value_SHT2_EWR[4]), .QN(n882) );
DFFRX2TS inst_ShiftRegister_Q_reg_0_ ( .D(n863), .CK(clk), .RN(n1724), .Q(
Shift_reg_FLAGS_7[0]), .QN(n1701) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n845), .CK(clk), .RN(n1726),
.Q(intDX_EWSW[17]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n793), .CK(clk), .RN(n1732), .Q(
Data_array_SWR[22]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n533), .CK(clk), .RN(n1758), .Q(
Raw_mant_NRM_SWR[9]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n854), .CK(clk), .RN(n1725), .Q(
intDX_EWSW[8]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n851), .CK(clk), .RN(n1726),
.Q(intDX_EWSW[11]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n532), .CK(clk), .RN(n1758), .Q(
Raw_mant_NRM_SWR[10]), .QN(n881) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n861), .CK(clk), .RN(n1725), .Q(
intDX_EWSW[1]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n853), .CK(clk), .RN(n1725), .Q(
intDX_EWSW[9]) );
DFFRX4TS inst_ShiftRegister_Q_reg_4_ ( .D(n867), .CK(clk), .RN(n1724), .Q(
busy), .QN(n1764) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n770), .CK(clk), .RN(n1731), .Q(
shift_value_SHT2_EWR[2]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n844), .CK(clk), .RN(n1726),
.Q(intDX_EWSW[18]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n794), .CK(clk), .RN(n1732), .Q(
Data_array_SWR[23]), .QN(n1703) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n786), .CK(clk), .RN(n1732), .Q(
Data_array_SWR[15]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n833), .CK(clk), .RN(n1727),
.Q(intDX_EWSW[29]) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n871), .CK(clk), .RN(
n1724), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n843), .CK(clk), .RN(n1726),
.Q(intDX_EWSW[19]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n835), .CK(clk), .RN(n1727),
.Q(intDX_EWSW[27]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n785), .CK(clk), .RN(n1732), .Q(
Data_array_SWR[14]), .QN(n1706) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n783), .CK(clk), .RN(n1733), .Q(
Data_array_SWR[12]), .QN(n1705) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n538), .CK(clk), .RN(n1752), .Q(
Raw_mant_NRM_SWR[4]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n780), .CK(clk), .RN(n1733), .Q(
Data_array_SWR[9]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_7_ ( .D(n696), .CK(clk), .RN(n1763), .Q(
DMP_SFG[7]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n777), .CK(clk), .RN(n1733), .Q(
Data_array_SWR[6]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n778), .CK(clk), .RN(n1733), .Q(
Data_array_SWR[7]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n775), .CK(clk), .RN(n1733), .Q(
Data_array_SWR[4]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n776), .CK(clk), .RN(n1733), .Q(
Data_array_SWR[5]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n831), .CK(clk), .RN(n1728),
.Q(intDX_EWSW[31]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_5_ ( .D(n702), .CK(clk), .RN(n1135), .Q(
DMP_SFG[5]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_1_ ( .D(n714), .CK(clk), .RN(n1737), .Q(
DMP_SFG[1]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_8_ ( .D(n693), .CK(clk), .RN(n1763), .Q(
DMP_SFG[8]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_11_ ( .D(n684), .CK(clk), .RN(n1763), .Q(
DMP_SFG[11]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_18_ ( .D(n663), .CK(clk), .RN(n1761), .Q(
DMP_SFG[18]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_16_ ( .D(n669), .CK(clk), .RN(n1761), .Q(
DMP_SFG[16]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_9_ ( .D(n690), .CK(clk), .RN(n1763), .Q(
DMP_SFG[9]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_6_ ( .D(n699), .CK(clk), .RN(n1763), .Q(
DMP_SFG[6]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_14_ ( .D(n675), .CK(clk), .RN(n1761), .Q(
DMP_SFG[14]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n575), .CK(clk), .RN(n1749), .Q(
DmP_mant_SHT1_SW[17]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_17_ ( .D(n666), .CK(clk), .RN(n1761), .Q(
DMP_SFG[17]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_15_ ( .D(n672), .CK(clk), .RN(n1761), .Q(
DMP_SFG[15]) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n765), .CK(clk), .RN(n1734),
.Q(Shift_amount_SHT1_EWR[1]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_21_ ( .D(n654), .CK(clk), .RN(n1761), .Q(
DMP_SFG[21]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_13_ ( .D(n678), .CK(clk), .RN(n1763), .Q(
DMP_SFG[13]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n626), .CK(clk), .RN(n1757), .Q(
DMP_exp_NRM2_EW[4]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n631), .CK(clk), .RN(n1757), .Q(
DMP_exp_NRM2_EW[3]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n636), .CK(clk), .RN(n1757), .Q(
DMP_exp_NRM2_EW[2]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n641), .CK(clk), .RN(n1757), .Q(
DMP_exp_NRM2_EW[1]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_12_ ( .D(n681), .CK(clk), .RN(n1763), .Q(
DMP_SFG[12]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_10_ ( .D(n687), .CK(clk), .RN(n1763), .Q(
DMP_SFG[10]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_22_ ( .D(n651), .CK(clk), .RN(n1762), .Q(
DMP_SFG[22]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_20_ ( .D(n657), .CK(clk), .RN(n1761), .Q(
DMP_SFG[20]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_19_ ( .D(n660), .CK(clk), .RN(n1761), .Q(
DMP_SFG[19]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_26_ ( .D(n561), .CK(clk), .RN(n1750), .Q(
DmP_EXP_EWSW[26]), .QN(n889) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n478), .CK(clk), .RN(n1762), .Q(
DmP_mant_SFG_SWR[10]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n468), .CK(clk), .RN(n1760), .Q(
DmP_mant_SFG_SWR[20]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n470), .CK(clk), .RN(n1760), .Q(
DmP_mant_SFG_SWR[18]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n479), .CK(clk), .RN(n1762), .Q(
DmP_mant_SFG_SWR[9]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n480), .CK(clk), .RN(n1762), .Q(
DmP_mant_SFG_SWR[8]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_0_ ( .D(n717), .CK(clk), .RN(n1737), .Q(
DMP_SFG[0]), .QN(n886) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n797), .CK(clk), .RN(n1731),
.Q(intDY_EWSW[31]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n473), .CK(clk), .RN(n1762), .Q(
DmP_mant_SFG_SWR[15]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n474), .CK(clk), .RN(n1762), .Q(
DmP_mant_SFG_SWR[14]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n475), .CK(clk), .RN(n1762), .Q(
DmP_mant_SFG_SWR[13]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n476), .CK(clk), .RN(n1762), .Q(
DmP_mant_SFG_SWR[12]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n477), .CK(clk), .RN(n1762), .Q(
DmP_mant_SFG_SWR[11]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n463), .CK(clk), .RN(n1761), .Q(
DmP_mant_SFG_SWR[25]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n464), .CK(clk), .RN(n1761), .Q(
DmP_mant_SFG_SWR[24]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n465), .CK(clk), .RN(n1760), .Q(
DmP_mant_SFG_SWR[23]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n466), .CK(clk), .RN(n1760), .Q(
DmP_mant_SFG_SWR[22]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n467), .CK(clk), .RN(n1760), .Q(
DmP_mant_SFG_SWR[21]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n469), .CK(clk), .RN(n1760), .Q(
DmP_mant_SFG_SWR[19]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n471), .CK(clk), .RN(n1760), .Q(
DmP_mant_SFG_SWR[17]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n472), .CK(clk), .RN(n1760), .Q(
DmP_mant_SFG_SWR[16]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n850), .CK(clk), .RN(n1726),
.Q(intDX_EWSW[12]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n842), .CK(clk), .RN(n1726),
.Q(intDX_EWSW[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n848), .CK(clk), .RN(n1726),
.Q(intDX_EWSW[14]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n840), .CK(clk), .RN(n1727),
.Q(intDX_EWSW[22]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n860), .CK(clk), .RN(n1725), .Q(
intDX_EWSW[2]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n784), .CK(clk), .RN(n1733), .Q(
Data_array_SWR[13]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n832), .CK(clk), .RN(n1727),
.Q(intDX_EWSW[30]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n852), .CK(clk), .RN(n1725),
.Q(intDX_EWSW[10]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n862), .CK(clk), .RN(n1724), .Q(
intDX_EWSW[0]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n782), .CK(clk), .RN(n1733), .Q(
Data_array_SWR[11]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n790), .CK(clk), .RN(n1732), .Q(
Data_array_SWR[19]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n789), .CK(clk), .RN(n1732), .Q(
Data_array_SWR[18]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n779), .CK(clk), .RN(n1733), .Q(
Data_array_SWR[8]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n781), .CK(clk), .RN(n1733), .Q(
Data_array_SWR[10]), .QN(n1713) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n603), .CK(clk), .RN(n1746), .Q(
DmP_mant_SHT1_SW[3]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n593), .CK(clk), .RN(n1747), .Q(
DmP_mant_SHT1_SW[8]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n589), .CK(clk), .RN(n1747), .Q(
DmP_mant_SHT1_SW[10]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n585), .CK(clk), .RN(n1748), .Q(
DmP_mant_SHT1_SW[12]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n565), .CK(clk), .RN(n1750), .Q(
DmP_mant_SHT1_SW[22]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n579), .CK(clk), .RN(n1748), .Q(
DmP_mant_SHT1_SW[15]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_27_ ( .D(n726), .CK(clk), .RN(n1739), .Q(
DMP_EXP_EWSW[27]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_25_ ( .D(n728), .CK(clk), .RN(n1136), .Q(
DMP_EXP_EWSW[25]), .QN(n924) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n607), .CK(clk), .RN(n1746), .Q(
DmP_mant_SHT1_SW[1]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n599), .CK(clk), .RN(n1746), .Q(
DmP_mant_SHT1_SW[5]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_24_ ( .D(n729), .CK(clk), .RN(n1134), .Q(
DMP_EXP_EWSW[24]), .QN(n1648) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_26_ ( .D(n727), .CK(clk), .RN(n1139), .Q(
DMP_EXP_EWSW[26]), .QN(n1650) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n567), .CK(clk), .RN(n1750), .Q(
DmP_mant_SHT1_SW[21]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n605), .CK(clk), .RN(n1746), .Q(
DmP_mant_SHT1_SW[2]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n597), .CK(clk), .RN(n1747), .Q(
DmP_mant_SHT1_SW[6]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n591), .CK(clk), .RN(n1747), .Q(
DmP_mant_SHT1_SW[9]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n587), .CK(clk), .RN(n1748), .Q(
DmP_mant_SHT1_SW[11]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n571), .CK(clk), .RN(n1749), .Q(
DmP_mant_SHT1_SW[19]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n581), .CK(clk), .RN(n1748), .Q(
DmP_mant_SHT1_SW[14]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n601), .CK(clk), .RN(n1746), .Q(
DmP_mant_SHT1_SW[4]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n583), .CK(clk), .RN(n1748), .Q(
DmP_mant_SHT1_SW[13]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n573), .CK(clk), .RN(n1749), .Q(
DmP_mant_SHT1_SW[18]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n595), .CK(clk), .RN(n1747), .Q(
DmP_mant_SHT1_SW[7]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n577), .CK(clk), .RN(n1749), .Q(
DmP_mant_SHT1_SW[16]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n569), .CK(clk), .RN(n1749), .Q(
DmP_mant_SHT1_SW[20]) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n766), .CK(clk), .RN(n1734),
.Q(Shift_amount_SHT1_EWR[0]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_23_ ( .D(n564), .CK(clk), .RN(n1750), .Q(
DmP_EXP_EWSW[23]), .QN(n925) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_24_ ( .D(n563), .CK(clk), .RN(n1750), .Q(
DmP_EXP_EWSW[24]), .QN(n887) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n774), .CK(clk), .RN(n1734), .Q(
Data_array_SWR[3]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n773), .CK(clk), .RN(n1734), .Q(
Data_array_SWR[2]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n772), .CK(clk), .RN(n1734), .Q(
Data_array_SWR[1]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_27_ ( .D(n560), .CK(clk), .RN(n1750), .Q(
DmP_EXP_EWSW[27]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_25_ ( .D(n562), .CK(clk), .RN(n1750), .Q(
DmP_EXP_EWSW[25]), .QN(n1708) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n771), .CK(clk), .RN(n1734), .Q(
Data_array_SWR[0]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n515), .CK(clk), .RN(n1756), .Q(
LZD_output_NRM2_EW[0]), .QN(n878) );
DFFRX1TS inst_ShiftRegister_Q_reg_1_ ( .D(n864), .CK(clk), .RN(n1724), .Q(
Shift_reg_FLAGS_7[1]), .QN(n877) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n523), .CK(clk), .RN(n1760), .Q(
Raw_mant_NRM_SWR[19]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n522), .CK(clk), .RN(n1759), .Q(
Raw_mant_NRM_SWR[20]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n521), .CK(clk), .RN(n1760), .Q(
Raw_mant_NRM_SWR[21]), .QN(n1675) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n519), .CK(clk), .RN(n1759), .Q(
Raw_mant_NRM_SWR[23]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n529), .CK(clk), .RN(n1758), .Q(
Raw_mant_NRM_SWR[13]), .QN(n1704) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n531), .CK(clk), .RN(n1758), .Q(
Raw_mant_NRM_SWR[11]), .QN(n1633) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n504), .CK(clk), .RN(n1753), .Q(
final_result_ieee[14]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n502), .CK(clk), .RN(n1753), .Q(
final_result_ieee[15]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n501), .CK(clk), .RN(n1753), .Q(
final_result_ieee[5]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n500), .CK(clk), .RN(n1753), .Q(
final_result_ieee[16]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n499), .CK(clk), .RN(n1754), .Q(
final_result_ieee[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n498), .CK(clk), .RN(n1754), .Q(
final_result_ieee[17]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n496), .CK(clk), .RN(n1754), .Q(
final_result_ieee[18]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n495), .CK(clk), .RN(n1754), .Q(
final_result_ieee[2]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n494), .CK(clk), .RN(n1754), .Q(
final_result_ieee[19]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n493), .CK(clk), .RN(n1754), .Q(
final_result_ieee[1]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n492), .CK(clk), .RN(n1754), .Q(
final_result_ieee[0]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n491), .CK(clk), .RN(n1754), .Q(
final_result_ieee[20]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n490), .CK(clk), .RN(n1754), .Q(
final_result_ieee[21]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n489), .CK(clk), .RN(n1755), .Q(
final_result_ieee[22]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n510), .CK(clk), .RN(n1752), .Q(
final_result_ieee[11]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n508), .CK(clk), .RN(n1753), .Q(
final_result_ieee[12]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n507), .CK(clk), .RN(n1753), .Q(
final_result_ieee[8]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n511), .CK(clk), .RN(n1752), .Q(
final_result_ieee[10]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n611), .CK(clk), .RN(n1758), .Q(
DMP_exp_NRM2_EW[7]), .QN(n1699) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n616), .CK(clk), .RN(n1758), .Q(
DMP_exp_NRM2_EW[6]), .QN(n1698) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n621), .CK(clk), .RN(n1757), .Q(
DMP_exp_NRM2_EW[5]), .QN(n1670) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n646), .CK(clk), .RN(n1757), .Q(
DMP_exp_NRM2_EW[0]), .QN(n1662) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n541), .CK(clk), .RN(n1758), .Q(
Raw_mant_NRM_SWR[1]), .QN(n1709) );
DFFRX1TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n870), .CK(clk), .RN(
n1724), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n1669) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n540), .CK(clk), .RN(n1752), .Q(
Raw_mant_NRM_SWR[2]), .QN(n1634) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n537), .CK(clk), .RN(n1752), .Q(
Raw_mant_NRM_SWR[5]), .QN(n1654) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_4_ ( .D(n705), .CK(clk), .RN(n1138), .Q(
DMP_SFG[4]), .QN(n1711) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_3_ ( .D(n708), .CK(clk), .RN(n1736), .Q(
DMP_SFG[3]), .QN(n1710) );
DFFRX1TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n769), .CK(clk), .RN(n1731), .Q(
shift_value_SHT2_EWR[3]), .QN(n1652) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n821), .CK(clk), .RN(n1729), .Q(
intDY_EWSW[7]), .QN(n1668) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n836), .CK(clk), .RN(n1727),
.Q(intDX_EWSW[26]), .QN(n1712) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n809), .CK(clk), .RN(n1730),
.Q(intDY_EWSW[19]), .QN(n1646) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n818), .CK(clk), .RN(n1729),
.Q(intDY_EWSW[10]), .QN(n1653) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n828), .CK(clk), .RN(n1728), .Q(
intDY_EWSW[0]), .QN(n1642) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n819), .CK(clk), .RN(n1729), .Q(
intDY_EWSW[9]), .QN(n1679) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n812), .CK(clk), .RN(n1730),
.Q(intDY_EWSW[16]), .QN(n1687) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n822), .CK(clk), .RN(n1729), .Q(
intDY_EWSW[6]), .QN(n1667) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n824), .CK(clk), .RN(n1728), .Q(
intDY_EWSW[4]), .QN(n1684) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n823), .CK(clk), .RN(n1728), .Q(
intDY_EWSW[5]), .QN(n1641) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n834), .CK(clk), .RN(n1727),
.Q(intDX_EWSW[28]), .QN(n1658) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n801), .CK(clk), .RN(n1731),
.Q(intDY_EWSW[27]), .QN(n1693) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n804), .CK(clk), .RN(n1730),
.Q(intDY_EWSW[24]), .QN(n1635) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n800), .CK(clk), .RN(n1731),
.Q(intDY_EWSW[28]), .QN(n1690) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n535), .CK(clk), .RN(n1752), .Q(
Raw_mant_NRM_SWR[7]), .QN(n1655) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n486), .CK(clk), .RN(n1755), .Q(
DmP_mant_SFG_SWR[2]), .QN(n1696) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n485), .CK(clk), .RN(n1755), .Q(
DmP_mant_SFG_SWR[3]), .QN(n1697) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n481), .CK(clk), .RN(n1755), .Q(
DmP_mant_SFG_SWR[7]), .QN(n1695) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n787), .CK(clk), .RN(n1732), .Q(
Data_array_SWR[16]), .QN(n1723) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n791), .CK(clk), .RN(n1732), .Q(
Data_array_SWR[20]), .QN(n1722) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n534), .CK(clk), .RN(n1758), .Q(
Raw_mant_NRM_SWR[8]), .QN(n1632) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n792), .CK(clk), .RN(n1732), .Q(
Data_array_SWR[21]), .QN(n1718) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_23_ ( .D(n730), .CK(clk), .RN(n1738), .Q(
DMP_EXP_EWSW[23]) );
DFFRX2TS SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n549), .CK(clk), .RN(n1762), .Q(n873),
.QN(n1661) );
ADDFX1TS DP_OP_15J48_123_3372_U7 ( .A(n1665), .B(DMP_exp_NRM2_EW[2]), .CI(
DP_OP_15J48_123_3372_n7), .CO(DP_OP_15J48_123_3372_n6), .S(
exp_rslt_NRM2_EW1[2]) );
ADDFX1TS DP_OP_15J48_123_3372_U6 ( .A(n1663), .B(DMP_exp_NRM2_EW[3]), .CI(
DP_OP_15J48_123_3372_n6), .CO(DP_OP_15J48_123_3372_n5), .S(
exp_rslt_NRM2_EW1[3]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n518), .CK(clk), .RN(n1759), .Q(
Raw_mant_NRM_SWR[24]) );
CMPR32X2TS DP_OP_15J48_123_3372_U8 ( .A(n1664), .B(DMP_exp_NRM2_EW[1]), .C(
DP_OP_15J48_123_3372_n8), .CO(DP_OP_15J48_123_3372_n7), .S(
exp_rslt_NRM2_EW1[1]) );
CMPR32X2TS DP_OP_15J48_123_3372_U5 ( .A(n1671), .B(DMP_exp_NRM2_EW[4]), .C(
DP_OP_15J48_123_3372_n5), .CO(DP_OP_15J48_123_3372_n4), .S(
exp_rslt_NRM2_EW1[4]) );
OAI221X1TS U897 ( .A0(n906), .A1(n1394), .B0(n905), .B1(n1393), .C0(n1392),
.Y(n1589) );
AOI222X1TS U898 ( .A0(n1601), .A1(n888), .B0(Data_array_SWR[6]), .B1(n904),
.C0(n1600), .C1(n1604), .Y(n1628) );
OAI2BB2XLTS U899 ( .B0(n1339), .B1(n909), .A0N(Raw_mant_NRM_SWR[16]), .A1N(
n1353), .Y(n966) );
CMPR32X2TS U900 ( .A(DMP_SFG[8]), .B(DmP_mant_SFG_SWR_signed[10]), .C(n1477),
.CO(n1471), .S(n1478) );
AOI222X4TS U901 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n897), .B0(n918), .B1(
DmP_mant_SHT1_SW[19]), .C0(n1313), .C1(DmP_mant_SHT1_SW[20]), .Y(n1376) );
AOI222X4TS U902 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n897), .B0(n917), .B1(
DmP_mant_SHT1_SW[20]), .C0(n1360), .C1(DmP_mant_SHT1_SW[21]), .Y(n1379) );
AOI222X4TS U903 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n897), .B0(n918), .B1(
DmP_mant_SHT1_SW[16]), .C0(n1313), .C1(DmP_mant_SHT1_SW[17]), .Y(n1306) );
AND2X2TS U904 ( .A(beg_OP), .B(n1509), .Y(n1514) );
AOI211X1TS U905 ( .A0(DmP_mant_SHT1_SW[22]), .A1(n914), .B0(n1527), .C0(
n1114), .Y(n1380) );
CMPR32X2TS U906 ( .A(DMP_SFG[7]), .B(n1483), .C(n1482), .CO(n1477), .S(n1484) );
INVX2TS U907 ( .A(n896), .Y(n897) );
INVX2TS U908 ( .A(n883), .Y(n874) );
CMPR32X2TS U909 ( .A(DMP_SFG[6]), .B(n1480), .C(n1479), .CO(n1482), .S(n1481) );
INVX2TS U910 ( .A(n1567), .Y(n1243) );
AOI32X1TS U911 ( .A0(n1057), .A1(n1056), .A2(n1055), .B0(n1054), .B1(n1057),
.Y(n1058) );
NAND3X1TS U912 ( .A(shift_value_SHT2_EWR[2]), .B(n882), .C(
shift_value_SHT2_EWR[3]), .Y(n883) );
BUFX3TS U913 ( .A(Shift_reg_FLAGS_7_6), .Y(n1567) );
NAND2X1TS U914 ( .A(n1698), .B(n1066), .Y(n1092) );
INVX2TS U915 ( .A(n905), .Y(n906) );
INVX2TS U916 ( .A(n1401), .Y(n905) );
NAND2X1TS U917 ( .A(n1670), .B(n1061), .Y(n1065) );
INVX2TS U918 ( .A(n914), .Y(n915) );
NAND2X2TS U919 ( .A(n914), .B(n894), .Y(n1540) );
CMPR32X2TS U920 ( .A(n1462), .B(DMP_SFG[11]), .C(n1461), .CO(n1458), .S(
n1463) );
NAND2X2TS U921 ( .A(n1490), .B(n1218), .Y(n1222) );
CMPR32X2TS U922 ( .A(n1475), .B(DMP_SFG[10]), .C(n1474), .CO(n1461), .S(
n1476) );
BUFX3TS U923 ( .A(Shift_reg_FLAGS_7[1]), .Y(n1576) );
CMPR32X2TS U924 ( .A(n1483), .B(DMP_SFG[7]), .C(n977), .CO(
DP_OP_285J48_122_2126_n74) );
NOR3X1TS U925 ( .A(Raw_mant_NRM_SWR[17]), .B(Raw_mant_NRM_SWR[15]), .C(
Raw_mant_NRM_SWR[16]), .Y(n1118) );
OAI211XLTS U926 ( .A0(n1677), .A1(intDX_EWSW[3]), .B0(n1024), .C0(n1023),
.Y(n1027) );
OAI21XLTS U927 ( .A0(Raw_mant_NRM_SWR[25]), .A1(n935), .B0(n934), .Y(n936)
);
AOI31XLTS U928 ( .A0(n941), .A1(Raw_mant_NRM_SWR[16]), .A2(n1674), .B0(n936),
.Y(n937) );
OAI21XLTS U929 ( .A0(intDX_EWSW[23]), .A1(n1691), .B0(intDX_EWSW[22]), .Y(
n1046) );
OAI211XLTS U930 ( .A0(DMP_SFG[3]), .A1(n1466), .B0(n1464), .C0(DMP_SFG[2]),
.Y(n1465) );
NOR2XLTS U931 ( .A(n1063), .B(n1089), .Y(n1064) );
NOR2XLTS U932 ( .A(DMP_SFG[5]), .B(n1585), .Y(n1469) );
NOR2XLTS U933 ( .A(n1673), .B(n873), .Y(n1198) );
OR2X1TS U934 ( .A(n906), .B(n1127), .Y(n885) );
OAI21XLTS U935 ( .A0(n1654), .A1(n1533), .B0(n968), .Y(n969) );
CLKINVX3TS U936 ( .A(n1555), .Y(n1237) );
NOR2X2TS U937 ( .A(n970), .B(n875), .Y(n1368) );
INVX2TS U938 ( .A(n1090), .Y(n1077) );
CLKINVX3TS U939 ( .A(n1245), .Y(n1568) );
CLKINVX3TS U940 ( .A(n1576), .Y(n914) );
OAI21XLTS U941 ( .A0(n1526), .A1(n908), .B0(n1378), .Y(n792) );
OAI21XLTS U942 ( .A0(n1530), .A1(n910), .B0(n976), .Y(n787) );
OAI21XLTS U943 ( .A0(n1504), .A1(n1060), .B0(n1502), .Y(n870) );
OAI21XLTS U944 ( .A0(n1693), .A1(n1265), .B0(n1252), .Y(n560) );
OAI211XLTS U945 ( .A0(n1343), .A1(n907), .B0(n1342), .C0(n1341), .Y(n773) );
OAI21XLTS U946 ( .A0(n1693), .A1(n1312), .B0(n1285), .Y(n726) );
OAI21XLTS U947 ( .A0(n1537), .A1(n907), .B0(n967), .Y(n779) );
OAI21XLTS U948 ( .A0(n1214), .A1(n1402), .B0(n1213), .Y(n466) );
OAI21XLTS U949 ( .A0(n1596), .A1(n1402), .B0(n1194), .Y(n479) );
OAI211XLTS U950 ( .A0(n1347), .A1(n910), .B0(n1335), .C0(n1334), .Y(n776) );
OAI21XLTS U951 ( .A0(n1634), .A1(n1383), .B0(n1382), .Y(n793) );
OAI211XLTS U952 ( .A0(n1540), .A1(n882), .B0(n1488), .C0(n1226), .Y(n767) );
OAI211XLTS U953 ( .A0(n1069), .A1(n1187), .B0(n1569), .C0(n1068), .Y(n757)
);
OAI21XLTS U954 ( .A0(n1679), .A1(n1261), .B0(n1260), .Y(n592) );
OAI21XLTS U955 ( .A0(n1688), .A1(n1312), .B0(n1305), .Y(n733) );
INVX4TS U956 ( .A(n1661), .Y(n1387) );
OAI21X1TS U957 ( .A0(n1309), .A1(n908), .B0(n1308), .Y(n789) );
OAI211X1TS U958 ( .A0(n1363), .A1(n911), .B0(n1362), .C0(n1361), .Y(n782) );
AOI2BB1X1TS U959 ( .A0N(n1576), .A1N(LZD_output_NRM2_EW[3]), .B0(n1542), .Y(
n516) );
OAI21X1TS U960 ( .A0(n1659), .A1(n875), .B0(n950), .Y(n951) );
OAI21X1TS U961 ( .A0(n1709), .A1(n875), .B0(n1374), .Y(n1375) );
CLKMX2X2TS U962 ( .A(Raw_mant_NRM_SWR[24]), .B(n1432), .S0(n1451), .Y(n518)
);
AO22X1TS U963 ( .A0(n1500), .A1(n1499), .B0(final_result_ieee[30]), .B1(
n1507), .Y(n754) );
AO22X1TS U964 ( .A0(final_result_ieee[10]), .A1(n1610), .B0(n1595), .B1(
n1589), .Y(n511) );
AND2X2TS U965 ( .A(n1499), .B(n1091), .Y(n927) );
INVX4TS U966 ( .A(n1319), .Y(n1566) );
NAND2X4TS U967 ( .A(n1126), .B(n881), .Y(n1219) );
AND2X2TS U968 ( .A(n1699), .B(n1093), .Y(n1094) );
INVX1TS U969 ( .A(n1089), .Y(n1073) );
OAI21X1TS U970 ( .A0(busy), .A1(n1617), .B0(n914), .Y(n829) );
INVX4TS U971 ( .A(n906), .Y(n1617) );
INVX4TS U972 ( .A(n1555), .Y(n1402) );
NOR2X1TS U973 ( .A(n1002), .B(intDY_EWSW[10]), .Y(n1003) );
NOR2X1TS U974 ( .A(n1672), .B(n873), .Y(n1078) );
OAI21X1TS U975 ( .A0(intDX_EWSW[15]), .A1(n1643), .B0(intDX_EWSW[14]), .Y(
n1009) );
OAI21X1TS U976 ( .A0(intDX_EWSW[21]), .A1(n1681), .B0(intDX_EWSW[20]), .Y(
n1039) );
NOR2X1TS U977 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n1385) );
OAI21X1TS U978 ( .A0(n1309), .A1(n911), .B0(n972), .Y(n791) );
OAI211X1TS U979 ( .A0(n1318), .A1(n911), .B0(n1317), .C0(n1316), .Y(n772) );
OAI211X1TS U980 ( .A0(n1339), .A1(n908), .B0(n1338), .C0(n1337), .Y(n777) );
AOI222X1TS U981 ( .A0(Raw_mant_NRM_SWR[16]), .A1(n898), .B0(n918), .B1(
DmP_mant_SHT1_SW[7]), .C0(n1360), .C1(DmP_mant_SHT1_SW[8]), .Y(n1356)
);
OAI21X1TS U982 ( .A0(n1704), .A1(n1533), .B0(n1532), .Y(n1534) );
AND2X2TS U983 ( .A(n965), .B(n1540), .Y(n879) );
OAI21X1TS U984 ( .A0(n1639), .A1(n1222), .B0(n1221), .Y(n1223) );
INVX4TS U985 ( .A(n1531), .Y(n875) );
OAI211X1TS U986 ( .A0(n1495), .A1(n1494), .B0(n1493), .C0(n1492), .Y(n1496)
);
NAND4X1TS U987 ( .A(n1124), .B(n1123), .C(n1221), .D(n1492), .Y(n1125) );
AO22X1TS U988 ( .A0(n1595), .A1(n1590), .B0(final_result_ieee[11]), .B1(
n1701), .Y(n510) );
AO22X1TS U989 ( .A0(n1595), .A1(n1593), .B0(final_result_ieee[8]), .B1(n1610), .Y(n507) );
AO22X1TS U990 ( .A0(n1595), .A1(n1592), .B0(final_result_ieee[12]), .B1(
n1701), .Y(n508) );
AO22X1TS U991 ( .A0(n1595), .A1(n1591), .B0(final_result_ieee[9]), .B1(n1701), .Y(n509) );
AO22X1TS U992 ( .A0(n1595), .A1(n1594), .B0(final_result_ieee[13]), .B1(
n1701), .Y(n506) );
OAI211X1TS U993 ( .A0(n1077), .A1(n1187), .B0(n1569), .C0(n1076), .Y(n755)
);
OAI211X1TS U994 ( .A0(n1073), .A1(n1187), .B0(n1569), .C0(n1072), .Y(n756)
);
OAI211X1TS U995 ( .A0(n1191), .A1(n1610), .B0(n1569), .C0(n1190), .Y(n760)
);
OAI211X1TS U996 ( .A0(n1075), .A1(n1187), .B0(n1569), .C0(n1074), .Y(n758)
);
OAI211X1TS U997 ( .A0(n1071), .A1(n1187), .B0(n1569), .C0(n1070), .Y(n759)
);
OAI211X1TS U998 ( .A0(n1189), .A1(n1610), .B0(n1569), .C0(n1188), .Y(n761)
);
INVX1TS U999 ( .A(n1501), .Y(n1500) );
OAI21X1TS U1000 ( .A0(n1645), .A1(n1568), .B0(n1280), .Y(n724) );
OAI21X1TS U1001 ( .A0(n1644), .A1(n1566), .B0(n1322), .Y(n566) );
OAI21X1TS U1002 ( .A0(n1765), .A1(n1568), .B0(n1273), .Y(n752) );
OAI21X1TS U1003 ( .A0(n1641), .A1(n1279), .B0(n1276), .Y(n748) );
NOR2X6TS U1004 ( .A(n1219), .B(n930), .Y(n957) );
OAI21X1TS U1005 ( .A0(n1690), .A1(n1568), .B0(n1272), .Y(n725) );
OAI21X1TS U1006 ( .A0(n1677), .A1(n1279), .B0(n1059), .Y(n750) );
OAI21X1TS U1007 ( .A0(n1643), .A1(n1301), .B0(n1293), .Y(n738) );
OAI21X1TS U1008 ( .A0(n1668), .A1(n1301), .B0(n1295), .Y(n746) );
OAI21X1TS U1009 ( .A0(n1688), .A1(n1566), .B0(n1320), .Y(n570) );
OAI21X1TS U1010 ( .A0(n1667), .A1(n1261), .B0(n1247), .Y(n598) );
OAI21X1TS U1011 ( .A0(n1678), .A1(n1312), .B0(n1289), .Y(n736) );
OAI21X1TS U1012 ( .A0(n1686), .A1(n1301), .B0(n1288), .Y(n739) );
OAI21X1TS U1013 ( .A0(n1765), .A1(n1261), .B0(n1250), .Y(n608) );
OAI21X1TS U1014 ( .A0(n1646), .A1(n1566), .B0(n1323), .Y(n572) );
OAI21X1TS U1015 ( .A0(n1684), .A1(n1279), .B0(n1275), .Y(n749) );
OAI21X1TS U1016 ( .A0(n1687), .A1(n1265), .B0(n1244), .Y(n578) );
OAI21X1TS U1017 ( .A0(n1646), .A1(n1312), .B0(n1303), .Y(n734) );
OAI21X1TS U1018 ( .A0(n1683), .A1(n1279), .B0(n1278), .Y(n751) );
OAI21X1TS U1019 ( .A0(n1685), .A1(n1265), .B0(n1259), .Y(n586) );
OAI21X1TS U1020 ( .A0(n1694), .A1(n1312), .B0(n1281), .Y(n735) );
OAI21X1TS U1021 ( .A0(n1660), .A1(n1301), .B0(n1292), .Y(n742) );
OAI21X1TS U1022 ( .A0(n1641), .A1(n1261), .B0(n1248), .Y(n600) );
OAI21X1TS U1023 ( .A0(n1679), .A1(n1301), .B0(n1296), .Y(n744) );
OAI21X1TS U1024 ( .A0(n1667), .A1(n1279), .B0(n1277), .Y(n747) );
OAI21X1TS U1025 ( .A0(n1681), .A1(n1566), .B0(n1321), .Y(n568) );
OAI21X1TS U1026 ( .A0(n1660), .A1(n1265), .B0(n1257), .Y(n588) );
OAI21X1TS U1027 ( .A0(n1270), .A1(n1554), .B0(n1267), .Y(n1268) );
OAI21X1TS U1028 ( .A0(n1678), .A1(n1265), .B0(n1241), .Y(n576) );
OAI21X1TS U1029 ( .A0(n1642), .A1(n1261), .B0(n1242), .Y(n610) );
NOR2X6TS U1030 ( .A(Raw_mant_NRM_SWR[12]), .B(n938), .Y(n1126) );
INVX1TS U1031 ( .A(n1284), .Y(n1267) );
OAI21X1TS U1032 ( .A0(n1597), .A1(n1240), .B0(n1197), .Y(n480) );
NAND2BX1TS U1033 ( .AN(n1090), .B(n1064), .Y(n1067) );
OAI21X1TS U1034 ( .A0(n1206), .A1(n1240), .B0(n1205), .Y(n463) );
AOI222X1TS U1035 ( .A0(n1599), .A1(n906), .B0(Data_array_SWR[7]), .B1(n900),
.C0(n1598), .C1(n1112), .Y(n1236) );
AOI222X1TS U1036 ( .A0(n1599), .A1(n905), .B0(Data_array_SWR[7]), .B1(n904),
.C0(n1598), .C1(n1604), .Y(n1630) );
AOI222X1TS U1037 ( .A0(n1603), .A1(n905), .B0(n904), .B1(Data_array_SWR[5]),
.C0(n1602), .C1(n1604), .Y(n1626) );
NOR2X6TS U1038 ( .A(Raw_mant_NRM_SWR[13]), .B(n1122), .Y(n959) );
AOI222X1TS U1039 ( .A0(n1606), .A1(n905), .B0(n904), .B1(Data_array_SWR[4]),
.C0(n1605), .C1(n1604), .Y(n1623) );
OAI21X1TS U1040 ( .A0(n1415), .A1(n1418), .B0(n1419), .Y(n985) );
OAI21X1TS U1041 ( .A0(n1612), .A1(n1402), .B0(n1212), .Y(n464) );
OR2X2TS U1042 ( .A(n1617), .B(n1127), .Y(n884) );
OAI21X1TS U1043 ( .A0(n1216), .A1(n1402), .B0(n1215), .Y(n465) );
NOR2X1TS U1044 ( .A(n1414), .B(n1418), .Y(n986) );
OAI21X1TS U1045 ( .A0(n1038), .A1(n1037), .B0(n1036), .Y(n1056) );
NAND4BX1TS U1046 ( .AN(exp_rslt_NRM2_EW1[4]), .B(n1062), .C(n1075), .D(n1071), .Y(n1063) );
AO22XLTS U1047 ( .A0(n1517), .A1(add_subt), .B0(n1515), .B1(intAS), .Y(n830)
);
BUFX3TS U1048 ( .A(n1527), .Y(n1313) );
AOI32X1TS U1049 ( .A0(Shift_amount_SHT1_EWR[2]), .A1(n1540), .A2(n914), .B0(
shift_value_SHT2_EWR[2]), .B1(n1113), .Y(n1539) );
OAI211X1TS U1050 ( .A0(n995), .A1(n1148), .B0(n994), .C0(n993), .Y(n1000) );
NOR2BX4TS U1051 ( .AN(Shift_amount_SHT1_EWR[0]), .B(n915), .Y(n1527) );
INVX3TS U1052 ( .A(n1620), .Y(n1629) );
OR2X2TS U1053 ( .A(n915), .B(Shift_amount_SHT1_EWR[0]), .Y(n949) );
INVX2TS U1054 ( .A(n1555), .Y(n1240) );
CLKBUFX3TS U1055 ( .A(n1085), .Y(n902) );
OAI211X1TS U1056 ( .A0(intDX_EWSW[8]), .A1(n1682), .B0(n1017), .C0(n1016),
.Y(n1018) );
INVX3TS U1057 ( .A(n989), .Y(n1588) );
NAND2BX1TS U1058 ( .AN(n954), .B(n953), .Y(n956) );
AOI211X1TS U1059 ( .A0(intDY_EWSW[16]), .A1(n1656), .B0(n1045), .C0(n1155),
.Y(n1035) );
CLKBUFX3TS U1060 ( .A(n1390), .Y(n901) );
NOR2X1TS U1061 ( .A(n1186), .B(exp_rslt_NRM2_EW1[1]), .Y(n1062) );
INVX1TS U1062 ( .A(n1118), .Y(n1120) );
OAI211X2TS U1063 ( .A0(intDX_EWSW[12]), .A1(n1685), .B0(n1013), .C0(n1004),
.Y(n1015) );
OAI211X2TS U1064 ( .A0(intDX_EWSW[20]), .A1(n1688), .B0(n1050), .C0(n1034),
.Y(n1045) );
NOR2X1TS U1065 ( .A(n1053), .B(intDY_EWSW[24]), .Y(n991) );
NAND3X1TS U1066 ( .A(n1689), .B(n992), .C(intDX_EWSW[26]), .Y(n994) );
NOR2X4TS U1067 ( .A(shift_value_SHT2_EWR[4]), .B(n1108), .Y(n1085) );
NOR2X1TS U1068 ( .A(n1666), .B(n873), .Y(n1116) );
NAND3X1TS U1069 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1640), .C(
n1669), .Y(n1502) );
INVX2TS U1070 ( .A(n883), .Y(n876) );
INVX4TS U1071 ( .A(Shift_reg_FLAGS_7[2]), .Y(n989) );
CLKINVX2TS U1072 ( .A(Shift_reg_FLAGS_7[3]), .Y(n1386) );
NAND2BX1TS U1073 ( .AN(intDX_EWSW[27]), .B(intDY_EWSW[27]), .Y(n992) );
NOR2X1TS U1074 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[20]), .Y(n953) );
NAND2BX1TS U1075 ( .AN(intDY_EWSW[27]), .B(intDX_EWSW[27]), .Y(n993) );
NAND2BX1TS U1076 ( .AN(intDX_EWSW[21]), .B(intDY_EWSW[21]), .Y(n1034) );
INVX1TS U1077 ( .A(DmP_mant_SFG_SWR[6]), .Y(n1627) );
NAND2BX1TS U1078 ( .AN(intDX_EWSW[19]), .B(intDY_EWSW[19]), .Y(n1042) );
NAND2BX1TS U1079 ( .AN(intDX_EWSW[24]), .B(intDY_EWSW[24]), .Y(n1051) );
INVX1TS U1080 ( .A(DmP_mant_SFG_SWR[4]), .Y(n1622) );
OR2X2TS U1081 ( .A(Raw_mant_NRM_SWR[25]), .B(Raw_mant_NRM_SWR[24]), .Y(n880)
);
NAND2BX1TS U1082 ( .AN(intDX_EWSW[13]), .B(intDY_EWSW[13]), .Y(n1004) );
NAND2BX1TS U1083 ( .AN(Raw_mant_NRM_SWR[9]), .B(n1632), .Y(n930) );
NAND2BX1TS U1084 ( .AN(intDX_EWSW[9]), .B(intDY_EWSW[9]), .Y(n1017) );
NOR2X8TS U1085 ( .A(n948), .B(n1575), .Y(n1531) );
AOI222X4TS U1086 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n897), .B0(n917), .B1(
DmP_mant_SHT1_SW[6]), .C0(n1360), .C1(DmP_mant_SHT1_SW[7]), .Y(n1339)
);
ADDFHX2TS U1087 ( .A(n1450), .B(DMP_SFG[13]), .CI(n1449), .CO(n1456), .S(
n1452) );
ADDFHX2TS U1088 ( .A(n1459), .B(DMP_SFG[12]), .CI(n1458), .CO(n1449), .S(
n1460) );
NAND2BXLTS U1089 ( .AN(intDY_EWSW[9]), .B(intDX_EWSW[9]), .Y(n1006) );
NAND3XLTS U1090 ( .A(n1682), .B(n1017), .C(intDX_EWSW[8]), .Y(n1005) );
AOI21X1TS U1091 ( .A0(n940), .A1(Raw_mant_NRM_SWR[6]), .B0(n939), .Y(n946)
);
NAND2BXLTS U1092 ( .AN(intDX_EWSW[2]), .B(intDY_EWSW[2]), .Y(n1023) );
NAND2BX1TS U1093 ( .AN(n942), .B(n960), .Y(n945) );
INVX2TS U1094 ( .A(n1123), .Y(n942) );
NOR2X4TS U1095 ( .A(n929), .B(n880), .Y(n1489) );
NAND2X1TS U1096 ( .A(Raw_mant_NRM_SWR[12]), .B(n959), .Y(n1123) );
NAND3X1TS U1097 ( .A(n1121), .B(n1491), .C(Raw_mant_NRM_SWR[1]), .Y(n1221)
);
AO21XLTS U1098 ( .A0(n1633), .A1(n1704), .B0(n1122), .Y(n1492) );
INVX4TS U1099 ( .A(n1661), .Y(n1200) );
AOI21X1TS U1100 ( .A0(n1407), .A1(n1410), .B0(n983), .Y(n1415) );
NAND2X1TS U1101 ( .A(n1408), .B(n1410), .Y(n1414) );
NAND2X1TS U1102 ( .A(n1454), .B(n1445), .Y(n1433) );
CLKBUFX2TS U1103 ( .A(n1245), .Y(n1287) );
AOI222X1TS U1104 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n898), .B0(n917), .B1(
DmP_mant_SHT1_SW[3]), .C0(n1360), .C1(DmP_mant_SHT1_SW[4]), .Y(n1347)
);
AOI222X1TS U1105 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n898), .B0(n917), .B1(
DmP_mant_SHT1_SW[2]), .C0(n1360), .C1(DmP_mant_SHT1_SW[3]), .Y(n1343)
);
INVX2TS U1106 ( .A(n1383), .Y(n1353) );
NAND2X2TS U1107 ( .A(n970), .B(n1531), .Y(n1383) );
NOR2X4TS U1108 ( .A(n926), .B(n1501), .Y(n1595) );
AOI222X1TS U1109 ( .A0(n1603), .A1(n1401), .B0(Data_array_SWR[5]), .B1(n900),
.C0(n1602), .C1(n1112), .Y(n1232) );
AO22XLTS U1110 ( .A0(n903), .A1(Data_array_SWR[8]), .B0(n1195), .B1(n905),
.Y(n1196) );
AO22XLTS U1111 ( .A0(n903), .A1(Data_array_SWR[9]), .B0(n1192), .B1(n1617),
.Y(n1193) );
INVX2TS U1112 ( .A(n1415), .Y(n1416) );
INVX2TS U1113 ( .A(n1418), .Y(n1420) );
OAI21X1TS U1114 ( .A0(n1434), .A1(n1437), .B0(n1438), .Y(n1407) );
NOR2X1TS U1115 ( .A(n1433), .B(n1437), .Y(n1408) );
INVX2TS U1116 ( .A(n1434), .Y(n1435) );
INVX2TS U1117 ( .A(n1437), .Y(n1439) );
INVX2TS U1118 ( .A(n1284), .Y(n1265) );
BUFX3TS U1119 ( .A(n1245), .Y(n1263) );
INVX2TS U1120 ( .A(n1284), .Y(n1261) );
NAND4XLTS U1121 ( .A(n1169), .B(n1168), .C(n1167), .D(n1166), .Y(n1179) );
NAND4XLTS U1122 ( .A(n1153), .B(n1152), .C(n1151), .D(n1150), .Y(n1181) );
NAND4XLTS U1123 ( .A(n1177), .B(n1176), .C(n1175), .D(n1174), .Y(n1178) );
INVX2TS U1124 ( .A(n1287), .Y(n1301) );
BUFX3TS U1125 ( .A(n1284), .Y(n1302) );
INVX2TS U1126 ( .A(n1287), .Y(n1312) );
AO22XLTS U1127 ( .A0(n1512), .A1(Data_X[10]), .B0(n1511), .B1(intDX_EWSW[10]), .Y(n852) );
AO22XLTS U1128 ( .A0(n1513), .A1(Data_X[30]), .B0(n1515), .B1(intDX_EWSW[30]), .Y(n832) );
AO22XLTS U1129 ( .A0(n1512), .A1(Data_X[22]), .B0(n1523), .B1(intDX_EWSW[22]), .Y(n840) );
AO22XLTS U1130 ( .A0(n1514), .A1(Data_X[14]), .B0(n1511), .B1(intDX_EWSW[14]), .Y(n848) );
AO22XLTS U1131 ( .A0(n1513), .A1(Data_X[20]), .B0(n1523), .B1(intDX_EWSW[20]), .Y(n842) );
AO22XLTS U1132 ( .A0(n1512), .A1(Data_X[12]), .B0(n1511), .B1(intDX_EWSW[12]), .Y(n850) );
AO22XLTS U1133 ( .A0(n1513), .A1(Data_X[31]), .B0(n1515), .B1(intDX_EWSW[31]), .Y(n831) );
AO22XLTS U1134 ( .A0(n1512), .A1(Data_X[19]), .B0(n1523), .B1(intDX_EWSW[19]), .Y(n843) );
AO22XLTS U1135 ( .A0(n1513), .A1(Data_X[29]), .B0(n1515), .B1(intDX_EWSW[29]), .Y(n833) );
AO22XLTS U1136 ( .A0(n1524), .A1(Data_X[18]), .B0(n1523), .B1(intDX_EWSW[18]), .Y(n844) );
AO22XLTS U1137 ( .A0(n1513), .A1(Data_X[9]), .B0(n1511), .B1(intDX_EWSW[9]),
.Y(n853) );
AO22XLTS U1138 ( .A0(n1512), .A1(Data_X[11]), .B0(n1511), .B1(intDX_EWSW[11]), .Y(n851) );
AO22XLTS U1139 ( .A0(n1513), .A1(Data_X[8]), .B0(n1511), .B1(intDX_EWSW[8]),
.Y(n854) );
AO22XLTS U1140 ( .A0(n1512), .A1(Data_X[17]), .B0(n1523), .B1(intDX_EWSW[17]), .Y(n845) );
AO22XLTS U1141 ( .A0(n1512), .A1(Data_X[13]), .B0(n1511), .B1(intDX_EWSW[13]), .Y(n849) );
AO22XLTS U1142 ( .A0(n1513), .A1(Data_X[21]), .B0(n1523), .B1(intDX_EWSW[21]), .Y(n841) );
AO22XLTS U1143 ( .A0(n1512), .A1(Data_X[15]), .B0(n1523), .B1(intDX_EWSW[15]), .Y(n847) );
AO22XLTS U1144 ( .A0(n1516), .A1(intDY_EWSW[2]), .B0(n1519), .B1(Data_Y[2]),
.Y(n826) );
AO22XLTS U1145 ( .A0(n1520), .A1(Data_X[5]), .B0(n1511), .B1(intDX_EWSW[5]),
.Y(n857) );
AO22XLTS U1146 ( .A0(n1520), .A1(Data_X[6]), .B0(n1511), .B1(intDX_EWSW[6]),
.Y(n856) );
AO22XLTS U1147 ( .A0(n1513), .A1(Data_X[7]), .B0(n1511), .B1(intDX_EWSW[7]),
.Y(n855) );
AO22XLTS U1148 ( .A0(n1512), .A1(Data_X[16]), .B0(n1523), .B1(intDX_EWSW[16]), .Y(n846) );
AO22XLTS U1149 ( .A0(n1522), .A1(intDY_EWSW[29]), .B0(n1521), .B1(Data_Y[29]), .Y(n799) );
AO22XLTS U1150 ( .A0(n1522), .A1(intDY_EWSW[30]), .B0(n1521), .B1(Data_Y[30]), .Y(n798) );
AO22XLTS U1151 ( .A0(n1522), .A1(intDY_EWSW[21]), .B0(n1519), .B1(Data_Y[21]), .Y(n807) );
AO22XLTS U1152 ( .A0(n1522), .A1(intDY_EWSW[22]), .B0(n1520), .B1(Data_Y[22]), .Y(n806) );
AO22XLTS U1153 ( .A0(n1516), .A1(intDY_EWSW[3]), .B0(n1519), .B1(Data_Y[3]),
.Y(n825) );
AO22XLTS U1154 ( .A0(n1516), .A1(intDY_EWSW[8]), .B0(n1520), .B1(Data_Y[8]),
.Y(n820) );
AO22XLTS U1155 ( .A0(n1518), .A1(intDY_EWSW[11]), .B0(n1520), .B1(Data_Y[11]), .Y(n817) );
AO22XLTS U1156 ( .A0(n1518), .A1(intDY_EWSW[15]), .B0(n1521), .B1(Data_Y[15]), .Y(n813) );
AO22XLTS U1157 ( .A0(n1518), .A1(intDY_EWSW[17]), .B0(n1521), .B1(Data_Y[17]), .Y(n811) );
AO22XLTS U1158 ( .A0(n1518), .A1(intDY_EWSW[18]), .B0(n1521), .B1(Data_Y[18]), .Y(n810) );
AO22XLTS U1159 ( .A0(n1518), .A1(intDY_EWSW[12]), .B0(n1519), .B1(Data_Y[12]), .Y(n816) );
AO22XLTS U1160 ( .A0(n1518), .A1(intDY_EWSW[13]), .B0(n1521), .B1(Data_Y[13]), .Y(n815) );
AO22XLTS U1161 ( .A0(n1518), .A1(intDY_EWSW[14]), .B0(n1521), .B1(Data_Y[14]), .Y(n814) );
AO22XLTS U1162 ( .A0(n1518), .A1(intDY_EWSW[20]), .B0(n1519), .B1(Data_Y[20]), .Y(n808) );
AO22XLTS U1163 ( .A0(n1522), .A1(intDY_EWSW[28]), .B0(n1517), .B1(Data_Y[28]), .Y(n800) );
AO22XLTS U1164 ( .A0(n1512), .A1(Data_X[28]), .B0(n1515), .B1(intDX_EWSW[28]), .Y(n834) );
AO22XLTS U1165 ( .A0(n1516), .A1(intDY_EWSW[5]), .B0(n1519), .B1(Data_Y[5]),
.Y(n823) );
AO22XLTS U1166 ( .A0(n1516), .A1(intDY_EWSW[4]), .B0(n1519), .B1(Data_Y[4]),
.Y(n824) );
AO22XLTS U1167 ( .A0(n1516), .A1(intDY_EWSW[6]), .B0(n1519), .B1(Data_Y[6]),
.Y(n822) );
AO22XLTS U1168 ( .A0(n1518), .A1(intDY_EWSW[16]), .B0(n1521), .B1(Data_Y[16]), .Y(n812) );
AO22XLTS U1169 ( .A0(n1516), .A1(intDY_EWSW[9]), .B0(n1520), .B1(Data_Y[9]),
.Y(n819) );
AO22XLTS U1170 ( .A0(n1516), .A1(intDY_EWSW[0]), .B0(n1520), .B1(Data_Y[0]),
.Y(n828) );
AO22XLTS U1171 ( .A0(n1516), .A1(intDY_EWSW[1]), .B0(n1519), .B1(Data_Y[1]),
.Y(n827) );
AO22XLTS U1172 ( .A0(n1516), .A1(intDY_EWSW[10]), .B0(n1520), .B1(Data_Y[10]), .Y(n818) );
AO22XLTS U1173 ( .A0(n1518), .A1(intDY_EWSW[19]), .B0(n1521), .B1(Data_Y[19]), .Y(n809) );
AO22XLTS U1174 ( .A0(n1515), .A1(intDY_EWSW[7]), .B0(n1519), .B1(Data_Y[7]),
.Y(n821) );
AOI222X1TS U1175 ( .A0(intDY_EWSW[4]), .A1(n1637), .B0(n1027), .B1(n1026),
.C0(intDY_EWSW[5]), .C1(n1651), .Y(n1029) );
AOI2BB2XLTS U1176 ( .B0(intDX_EWSW[3]), .B1(n1677), .A0N(intDY_EWSW[2]),
.A1N(n1025), .Y(n1026) );
AOI2BB1XLTS U1177 ( .A0N(n932), .A1N(Raw_mant_NRM_SWR[23]), .B0(
Raw_mant_NRM_SWR[24]), .Y(n935) );
OAI2BB2XLTS U1178 ( .B0(n1008), .B1(n1015), .A0N(n1007), .A1N(n1016), .Y(
n1011) );
NOR2BX1TS U1179 ( .AN(n1019), .B(n1018), .Y(n1033) );
INVX2TS U1180 ( .A(n1015), .Y(n1019) );
INVX2TS U1181 ( .A(n947), .Y(n912) );
CLKAND2X2TS U1182 ( .A(n1101), .B(shift_value_SHT2_EWR[4]), .Y(n1103) );
NAND2X1TS U1183 ( .A(n1101), .B(n882), .Y(n1127) );
NOR2XLTS U1184 ( .A(Raw_mant_NRM_SWR[17]), .B(Raw_mant_NRM_SWR[16]), .Y(n952) );
NOR2XLTS U1185 ( .A(n1040), .B(intDY_EWSW[16]), .Y(n1041) );
AOI211X1TS U1186 ( .A0(intDY_EWSW[28]), .A1(n1658), .B0(n998), .C0(n996),
.Y(n1052) );
NOR2BX1TS U1187 ( .AN(n1035), .B(n1040), .Y(n1036) );
NOR2BX1TS U1188 ( .AN(n1033), .B(n1032), .Y(n1037) );
INVX2TS U1189 ( .A(n1014), .Y(n1038) );
INVX2TS U1190 ( .A(n947), .Y(n896) );
INVX4TS U1191 ( .A(n912), .Y(n913) );
NOR2X1TS U1192 ( .A(n1117), .B(n1116), .Y(intadd_50_B_1_) );
NOR2XLTS U1193 ( .A(n1661), .B(n1115), .Y(n1117) );
NAND4XLTS U1194 ( .A(n1161), .B(n1160), .C(n1159), .D(n1158), .Y(n1180) );
BUFX3TS U1195 ( .A(n1631), .Y(n1555) );
AO21XLTS U1196 ( .A0(n1580), .A1(DMP_SFG[1]), .B0(n1579), .Y(n1185) );
OAI21XLTS U1197 ( .A0(n1633), .A1(n1533), .B0(n1528), .Y(n1529) );
INVX2TS U1198 ( .A(n1504), .Y(n1503) );
CLKMX2X2TS U1199 ( .A(DP_OP_285J48_122_2126_n71), .B(
DP_OP_285J48_122_2126_n70), .S0(DP_OP_285J48_122_2126_n74), .Y(n1474)
);
NAND2X1TS U1200 ( .A(n1662), .B(LZD_output_NRM2_EW[0]), .Y(
DP_OP_15J48_123_3372_n8) );
AOI222X1TS U1201 ( .A0(n1606), .A1(n1401), .B0(Data_array_SWR[4]), .B1(n900),
.C0(n1605), .C1(n1112), .Y(n1234) );
AOI222X1TS U1202 ( .A0(n1195), .A1(n906), .B0(Data_array_SWR[8]), .B1(n900),
.C0(n1207), .C1(n1112), .Y(n1239) );
AOI222X1TS U1203 ( .A0(n1192), .A1(n1401), .B0(Data_array_SWR[9]), .B1(n900),
.C0(n1201), .C1(n1112), .Y(n1228) );
INVX2TS U1204 ( .A(n1489), .Y(n1494) );
AOI21X1TS U1205 ( .A0(n1456), .A1(n986), .B0(n985), .Y(n1404) );
CLKBUFX2TS U1206 ( .A(n1631), .Y(n1620) );
MX2X1TS U1207 ( .A(n1387), .B(OP_FLAG_SHT2), .S0(n1403), .Y(n549) );
AO21XLTS U1208 ( .A0(LZD_output_NRM2_EW[0]), .A1(n914), .B0(n890), .Y(n515)
);
AOI2BB2XLTS U1209 ( .B0(n1572), .B1(n1543), .A0N(Shift_amount_SHT1_EWR[0]),
.A1N(n1552), .Y(n766) );
AO22XLTS U1210 ( .A0(n1572), .A1(DmP_EXP_EWSW[20]), .B0(n1570), .B1(
DmP_mant_SHT1_SW[20]), .Y(n569) );
AO22XLTS U1211 ( .A0(n1572), .A1(DmP_EXP_EWSW[16]), .B0(n1565), .B1(
DmP_mant_SHT1_SW[16]), .Y(n577) );
AO22XLTS U1212 ( .A0(n921), .A1(DmP_EXP_EWSW[7]), .B0(n1564), .B1(
DmP_mant_SHT1_SW[7]), .Y(n595) );
AO22XLTS U1213 ( .A0(n1572), .A1(DmP_EXP_EWSW[18]), .B0(n1565), .B1(
DmP_mant_SHT1_SW[18]), .Y(n573) );
AO22XLTS U1214 ( .A0(n921), .A1(DmP_EXP_EWSW[13]), .B0(n1565), .B1(
DmP_mant_SHT1_SW[13]), .Y(n583) );
AO22XLTS U1215 ( .A0(n1563), .A1(DmP_EXP_EWSW[4]), .B0(n1564), .B1(
DmP_mant_SHT1_SW[4]), .Y(n601) );
AO22XLTS U1216 ( .A0(n921), .A1(DmP_EXP_EWSW[14]), .B0(n1565), .B1(
DmP_mant_SHT1_SW[14]), .Y(n581) );
AO22XLTS U1217 ( .A0(n1572), .A1(DmP_EXP_EWSW[19]), .B0(n1570), .B1(
DmP_mant_SHT1_SW[19]), .Y(n571) );
AO22XLTS U1218 ( .A0(n921), .A1(DmP_EXP_EWSW[11]), .B0(n1565), .B1(
DmP_mant_SHT1_SW[11]), .Y(n587) );
AO22XLTS U1219 ( .A0(n921), .A1(DmP_EXP_EWSW[9]), .B0(n1565), .B1(
DmP_mant_SHT1_SW[9]), .Y(n591) );
AO22XLTS U1220 ( .A0(n1636), .A1(DmP_EXP_EWSW[6]), .B0(n1564), .B1(
DmP_mant_SHT1_SW[6]), .Y(n597) );
AO22XLTS U1221 ( .A0(n1563), .A1(DmP_EXP_EWSW[2]), .B0(n1564), .B1(
DmP_mant_SHT1_SW[2]), .Y(n605) );
AO22XLTS U1222 ( .A0(n1572), .A1(DmP_EXP_EWSW[21]), .B0(n1570), .B1(
DmP_mant_SHT1_SW[21]), .Y(n567) );
AO22XLTS U1223 ( .A0(n1563), .A1(DmP_EXP_EWSW[5]), .B0(n1564), .B1(
DmP_mant_SHT1_SW[5]), .Y(n599) );
AO22XLTS U1224 ( .A0(n1563), .A1(DmP_EXP_EWSW[1]), .B0(n1564), .B1(
DmP_mant_SHT1_SW[1]), .Y(n607) );
AO22XLTS U1225 ( .A0(n921), .A1(DmP_EXP_EWSW[15]), .B0(n1565), .B1(
DmP_mant_SHT1_SW[15]), .Y(n579) );
AO22XLTS U1226 ( .A0(n1572), .A1(DmP_EXP_EWSW[22]), .B0(n1570), .B1(
DmP_mant_SHT1_SW[22]), .Y(n565) );
AO22XLTS U1227 ( .A0(n921), .A1(DmP_EXP_EWSW[12]), .B0(n1565), .B1(
DmP_mant_SHT1_SW[12]), .Y(n585) );
AO22XLTS U1228 ( .A0(n921), .A1(DmP_EXP_EWSW[10]), .B0(n1565), .B1(
DmP_mant_SHT1_SW[10]), .Y(n589) );
AO22XLTS U1229 ( .A0(n921), .A1(DmP_EXP_EWSW[8]), .B0(n1564), .B1(
DmP_mant_SHT1_SW[8]), .Y(n593) );
AO22XLTS U1230 ( .A0(n1563), .A1(DmP_EXP_EWSW[3]), .B0(n1564), .B1(
DmP_mant_SHT1_SW[3]), .Y(n603) );
OAI222X1TS U1231 ( .A0(n1713), .A1(n1540), .B0(n910), .B1(n1537), .C0(n907),
.C1(n1536), .Y(n781) );
AO22XLTS U1232 ( .A0(n1524), .A1(Data_X[0]), .B0(n1510), .B1(intDX_EWSW[0]),
.Y(n862) );
AO22XLTS U1233 ( .A0(n1524), .A1(Data_X[2]), .B0(n1510), .B1(intDX_EWSW[2]),
.Y(n860) );
MX2X1TS U1234 ( .A(n1591), .B(DmP_mant_SFG_SWR[11]), .S0(n1402), .Y(n477) );
MX2X1TS U1235 ( .A(n1589), .B(DmP_mant_SFG_SWR[12]), .S0(n1402), .Y(n476) );
MX2X1TS U1236 ( .A(n1590), .B(DmP_mant_SFG_SWR[13]), .S0(n1402), .Y(n475) );
MX2X1TS U1237 ( .A(n1592), .B(DmP_mant_SFG_SWR[14]), .S0(n1402), .Y(n474) );
MX2X1TS U1238 ( .A(n1594), .B(DmP_mant_SFG_SWR[15]), .S0(n1402), .Y(n473) );
AO22XLTS U1239 ( .A0(n1524), .A1(Data_Y[31]), .B0(n1523), .B1(intDY_EWSW[31]), .Y(n797) );
AO22XLTS U1240 ( .A0(n1555), .A1(DMP_SHT2_EWSW[0]), .B0(n1562), .B1(
DMP_SFG[0]), .Y(n717) );
OAI21XLTS U1241 ( .A0(n1240), .A1(n1236), .B0(n1235), .Y(n470) );
OAI21XLTS U1242 ( .A0(n1240), .A1(n1232), .B0(n1231), .Y(n468) );
MX2X1TS U1243 ( .A(n1593), .B(DmP_mant_SFG_SWR[10]), .S0(n1402), .Y(n478) );
MX2X1TS U1244 ( .A(DMP_SFG[19]), .B(DMP_SHT2_EWSW[19]), .S0(n1555), .Y(n660)
);
MX2X1TS U1245 ( .A(DMP_SFG[20]), .B(DMP_SHT2_EWSW[20]), .S0(n1555), .Y(n657)
);
MX2X1TS U1246 ( .A(DMP_SFG[22]), .B(DMP_SHT2_EWSW[22]), .S0(n1403), .Y(n651)
);
MX2X1TS U1247 ( .A(DMP_SFG[10]), .B(DMP_SHT2_EWSW[10]), .S0(n1555), .Y(n687)
);
MX2X1TS U1248 ( .A(DMP_SFG[12]), .B(DMP_SHT2_EWSW[12]), .S0(n1403), .Y(n681)
);
MX2X1TS U1249 ( .A(DMP_exp_NRM2_EW[1]), .B(DMP_exp_NRM_EW[1]), .S0(n1576),
.Y(n641) );
MX2X1TS U1250 ( .A(DMP_exp_NRM2_EW[2]), .B(DMP_exp_NRM_EW[2]), .S0(n915),
.Y(n636) );
MX2X1TS U1251 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(n1576),
.Y(n631) );
MX2X1TS U1252 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(n915),
.Y(n626) );
MX2X1TS U1253 ( .A(DMP_SFG[13]), .B(DMP_SHT2_EWSW[13]), .S0(n1555), .Y(n678)
);
MX2X1TS U1254 ( .A(DMP_SFG[21]), .B(DMP_SHT2_EWSW[21]), .S0(n1403), .Y(n654)
);
OAI21XLTS U1255 ( .A0(n1691), .A1(n1312), .B0(n1286), .Y(n730) );
AO22XLTS U1256 ( .A0(n1552), .A1(n1547), .B0(n1571), .B1(
Shift_amount_SHT1_EWR[1]), .Y(n765) );
MX2X1TS U1257 ( .A(DMP_SFG[15]), .B(DMP_SHT2_EWSW[15]), .S0(n1624), .Y(n672)
);
MX2X1TS U1258 ( .A(DMP_SFG[17]), .B(DMP_SHT2_EWSW[17]), .S0(n1631), .Y(n666)
);
AO22XLTS U1259 ( .A0(n1572), .A1(DmP_EXP_EWSW[17]), .B0(n1565), .B1(
DmP_mant_SHT1_SW[17]), .Y(n575) );
MX2X1TS U1260 ( .A(DMP_SFG[14]), .B(DMP_SHT2_EWSW[14]), .S0(n1555), .Y(n675)
);
MX2X1TS U1261 ( .A(DMP_SFG[6]), .B(DMP_SHT2_EWSW[6]), .S0(n1403), .Y(n699)
);
MX2X1TS U1262 ( .A(DMP_SFG[9]), .B(DMP_SHT2_EWSW[9]), .S0(n1403), .Y(n690)
);
MX2X1TS U1263 ( .A(DMP_SFG[16]), .B(DMP_SHT2_EWSW[16]), .S0(n1403), .Y(n669)
);
MX2X1TS U1264 ( .A(DMP_SFG[18]), .B(DMP_SHT2_EWSW[18]), .S0(n1403), .Y(n663)
);
MX2X1TS U1265 ( .A(DMP_SFG[11]), .B(DMP_SHT2_EWSW[11]), .S0(n1555), .Y(n684)
);
MX2X1TS U1266 ( .A(DMP_SFG[8]), .B(DMP_SHT2_EWSW[8]), .S0(n1403), .Y(n693)
);
AO22XLTS U1267 ( .A0(n1624), .A1(DMP_SHT2_EWSW[1]), .B0(n1562), .B1(
DMP_SFG[1]), .Y(n714) );
AO22XLTS U1268 ( .A0(n1615), .A1(DMP_SHT2_EWSW[5]), .B0(n1574), .B1(
DMP_SFG[5]), .Y(n702) );
OAI211XLTS U1269 ( .A0(n1343), .A1(n911), .B0(n1330), .C0(n1329), .Y(n775)
);
OAI211XLTS U1270 ( .A0(n1356), .A1(n907), .B0(n1350), .C0(n1349), .Y(n778)
);
MX2X1TS U1271 ( .A(DMP_SFG[7]), .B(DMP_SHT2_EWSW[7]), .S0(n1403), .Y(n696)
);
AOI2BB2XLTS U1272 ( .B0(n1588), .B1(intadd_50_SUM_0_), .A0N(
Raw_mant_NRM_SWR[4]), .A1N(n1584), .Y(n538) );
OAI222X1TS U1273 ( .A0(n1705), .A1(n1540), .B0(n910), .B1(n1536), .C0(n908),
.C1(n1535), .Y(n783) );
OAI222X1TS U1274 ( .A0(n1540), .A1(n1706), .B0(n911), .B1(n1535), .C0(n907),
.C1(n1530), .Y(n785) );
AO22XLTS U1275 ( .A0(n1513), .A1(Data_X[27]), .B0(n1515), .B1(intDX_EWSW[27]), .Y(n835) );
AO22XLTS U1276 ( .A0(n1524), .A1(Data_X[1]), .B0(n1510), .B1(intDX_EWSW[1]),
.Y(n861) );
MX2X1TS U1277 ( .A(Raw_mant_NRM_SWR[10]), .B(n1478), .S0(n1486), .Y(n532) );
MX2X1TS U1278 ( .A(Raw_mant_NRM_SWR[9]), .B(n1484), .S0(n1486), .Y(n533) );
NAND3XLTS U1279 ( .A(busy), .B(Shift_amount_SHT1_EWR[4]), .C(n877), .Y(n1226) );
AO22XLTS U1280 ( .A0(n1513), .A1(Data_X[23]), .B0(n1523), .B1(intDX_EWSW[23]), .Y(n839) );
AO22XLTS U1281 ( .A0(n1524), .A1(Data_X[3]), .B0(n1510), .B1(intDX_EWSW[3]),
.Y(n859) );
CLKMX2X2TS U1282 ( .A(Raw_mant_NRM_SWR[25]), .B(n990), .S0(n1451), .Y(n517)
);
MX2X1TS U1283 ( .A(Raw_mant_NRM_SWR[22]), .B(n1426), .S0(n1451), .Y(n520) );
MX2X1TS U1284 ( .A(Raw_mant_NRM_SWR[17]), .B(n1448), .S0(n1451), .Y(n525) );
AO22XLTS U1285 ( .A0(n1522), .A1(intDY_EWSW[25]), .B0(n1517), .B1(Data_Y[25]), .Y(n803) );
AO22XLTS U1286 ( .A0(n1522), .A1(intDY_EWSW[26]), .B0(n1517), .B1(Data_Y[26]), .Y(n802) );
AO22XLTS U1287 ( .A0(n1522), .A1(intDY_EWSW[23]), .B0(n1517), .B1(Data_Y[23]), .Y(n805) );
AO22XLTS U1288 ( .A0(n1515), .A1(intDX_EWSW[25]), .B0(n1520), .B1(Data_X[25]), .Y(n837) );
AO22XLTS U1289 ( .A0(n1515), .A1(intDX_EWSW[24]), .B0(n1521), .B1(Data_X[24]), .Y(n838) );
MX2X1TS U1290 ( .A(Raw_mant_NRM_SWR[8]), .B(n1481), .S0(n1486), .Y(n534) );
AO22XLTS U1291 ( .A0(n1524), .A1(Data_X[4]), .B0(n1510), .B1(intDX_EWSW[4]),
.Y(n858) );
AO22XLTS U1292 ( .A0(n1522), .A1(intDY_EWSW[24]), .B0(n1517), .B1(Data_Y[24]), .Y(n804) );
AO22XLTS U1293 ( .A0(n1522), .A1(intDY_EWSW[27]), .B0(n1514), .B1(Data_Y[27]), .Y(n801) );
AO22XLTS U1294 ( .A0(n1515), .A1(intDX_EWSW[26]), .B0(n1520), .B1(Data_X[26]), .Y(n836) );
AO22XLTS U1295 ( .A0(n1562), .A1(DMP_SFG[3]), .B0(n1624), .B1(
DMP_SHT2_EWSW[3]), .Y(n708) );
AO22XLTS U1296 ( .A0(n1629), .A1(DMP_SFG[4]), .B0(n1624), .B1(
DMP_SHT2_EWSW[4]), .Y(n705) );
MX2X1TS U1297 ( .A(Raw_mant_NRM_SWR[14]), .B(n1460), .S0(n1486), .Y(n528) );
AO21XLTS U1298 ( .A0(n1577), .A1(n886), .B0(n1580), .Y(n1578) );
AOI2BB2XLTS U1299 ( .B0(beg_OP), .B1(n1640), .A0N(n1640), .A1N(
inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n1060) );
MX2X1TS U1300 ( .A(DMP_exp_NRM2_EW[0]), .B(DMP_exp_NRM_EW[0]), .S0(n1576),
.Y(n646) );
MX2X1TS U1301 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(n915),
.Y(n621) );
MX2X1TS U1302 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(n1576),
.Y(n616) );
MX2X1TS U1303 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(n915),
.Y(n611) );
MX2X1TS U1304 ( .A(Raw_mant_NRM_SWR[12]), .B(n1476), .S0(n1486), .Y(n530) );
AO22XLTS U1305 ( .A0(Shift_reg_FLAGS_7[0]), .A1(ZERO_FLAG_SHT1SHT2), .B0(
n1610), .B1(zero_flag), .Y(n552) );
MX2X1TS U1306 ( .A(Raw_mant_NRM_SWR[11]), .B(n1473), .S0(n1486), .Y(n531) );
MX2X1TS U1307 ( .A(Raw_mant_NRM_SWR[13]), .B(n1463), .S0(n1486), .Y(n529) );
AO21XLTS U1308 ( .A0(LZD_output_NRM2_EW[1]), .A1(n1575), .B0(n1498), .Y(n513) );
MX2X1TS U1309 ( .A(Raw_mant_NRM_SWR[23]), .B(n1429), .S0(n1451), .Y(n519) );
MX2X1TS U1310 ( .A(Raw_mant_NRM_SWR[21]), .B(n1406), .S0(n1451), .Y(n521) );
MX2X1TS U1311 ( .A(Raw_mant_NRM_SWR[20]), .B(n1423), .S0(n1451), .Y(n522) );
MX2X1TS U1312 ( .A(Raw_mant_NRM_SWR[19]), .B(n1413), .S0(n1451), .Y(n523) );
MX2X1TS U1313 ( .A(Raw_mant_NRM_SWR[18]), .B(n1442), .S0(n1451), .Y(n524) );
MX2X1TS U1314 ( .A(Raw_mant_NRM_SWR[16]), .B(n1457), .S0(n1486), .Y(n526) );
MX2X1TS U1315 ( .A(Raw_mant_NRM_SWR[15]), .B(n1452), .S0(n1451), .Y(n527) );
AO22XLTS U1316 ( .A0(Shift_reg_FLAGS_7[1]), .A1(SIGN_FLAG_NRM), .B0(n914),
.B1(SIGN_FLAG_SHT1SHT2), .Y(n544) );
AO22XLTS U1317 ( .A0(n1584), .A1(SIGN_FLAG_SFG), .B0(n1582), .B1(
SIGN_FLAG_NRM), .Y(n545) );
AO22XLTS U1318 ( .A0(n1620), .A1(SIGN_FLAG_SHT2), .B0(n1574), .B1(
SIGN_FLAG_SFG), .Y(n546) );
AO22XLTS U1319 ( .A0(n920), .A1(SIGN_FLAG_SHT1), .B0(n1764), .B1(
SIGN_FLAG_SHT2), .Y(n547) );
AO22XLTS U1320 ( .A0(n921), .A1(SIGN_FLAG_EXP), .B0(n1573), .B1(
SIGN_FLAG_SHT1), .Y(n548) );
AO22XLTS U1321 ( .A0(busy), .A1(OP_FLAG_SHT1), .B0(OP_FLAG_SHT2), .B1(n895),
.Y(n1716) );
AO22XLTS U1322 ( .A0(n1572), .A1(OP_FLAG_EXP), .B0(n1571), .B1(OP_FLAG_SHT1),
.Y(n551) );
AO22XLTS U1323 ( .A0(n915), .A1(ZERO_FLAG_NRM), .B0(n877), .B1(
ZERO_FLAG_SHT1SHT2), .Y(n553) );
AO22XLTS U1324 ( .A0(n1584), .A1(ZERO_FLAG_SFG), .B0(n1717), .B1(
ZERO_FLAG_NRM), .Y(n554) );
AO22XLTS U1325 ( .A0(n1624), .A1(ZERO_FLAG_SHT2), .B0(n1574), .B1(
ZERO_FLAG_SFG), .Y(n555) );
AO22XLTS U1326 ( .A0(n920), .A1(ZERO_FLAG_SHT1), .B0(n1764), .B1(
ZERO_FLAG_SHT2), .Y(n556) );
AO22XLTS U1327 ( .A0(n1572), .A1(ZERO_FLAG_EXP), .B0(n1570), .B1(
ZERO_FLAG_SHT1), .Y(n557) );
OAI21XLTS U1328 ( .A0(n1694), .A1(n1265), .B0(n1254), .Y(n574) );
OAI21XLTS U1329 ( .A0(n1643), .A1(n1265), .B0(n1264), .Y(n580) );
OAI21XLTS U1330 ( .A0(n1686), .A1(n1265), .B0(n1256), .Y(n582) );
OAI21XLTS U1331 ( .A0(n1680), .A1(n1265), .B0(n1262), .Y(n584) );
OAI21XLTS U1332 ( .A0(n1653), .A1(n1265), .B0(n1255), .Y(n590) );
OAI21XLTS U1333 ( .A0(n1682), .A1(n1261), .B0(n1258), .Y(n594) );
OAI21XLTS U1334 ( .A0(n1668), .A1(n1261), .B0(n1253), .Y(n596) );
OAI21XLTS U1335 ( .A0(n1684), .A1(n1261), .B0(n1246), .Y(n602) );
OAI21XLTS U1336 ( .A0(n1677), .A1(n1261), .B0(n1251), .Y(n604) );
OAI21XLTS U1337 ( .A0(n1683), .A1(n1261), .B0(n1249), .Y(n606) );
AO22XLTS U1338 ( .A0(n1563), .A1(DmP_EXP_EWSW[0]), .B0(n1564), .B1(
DmP_mant_SHT1_SW[0]), .Y(n609) );
AO22XLTS U1339 ( .A0(n1588), .A1(DMP_SFG[30]), .B0(n1582), .B1(
DMP_exp_NRM_EW[7]), .Y(n612) );
AO22XLTS U1340 ( .A0(n1615), .A1(DMP_SHT2_EWSW[30]), .B0(n1562), .B1(
DMP_SFG[30]), .Y(n613) );
AO22XLTS U1341 ( .A0(n920), .A1(DMP_SHT1_EWSW[30]), .B0(n1764), .B1(
DMP_SHT2_EWSW[30]), .Y(n614) );
AO22XLTS U1342 ( .A0(n1563), .A1(DMP_EXP_EWSW[30]), .B0(n1564), .B1(
DMP_SHT1_EWSW[30]), .Y(n615) );
AO22XLTS U1343 ( .A0(n1584), .A1(DMP_SFG[29]), .B0(n1582), .B1(
DMP_exp_NRM_EW[6]), .Y(n617) );
AO22XLTS U1344 ( .A0(n1615), .A1(DMP_SHT2_EWSW[29]), .B0(n1562), .B1(
DMP_SFG[29]), .Y(n618) );
AO22XLTS U1345 ( .A0(n920), .A1(DMP_SHT1_EWSW[29]), .B0(n1764), .B1(
DMP_SHT2_EWSW[29]), .Y(n619) );
AO22XLTS U1346 ( .A0(n1563), .A1(DMP_EXP_EWSW[29]), .B0(n1573), .B1(
DMP_SHT1_EWSW[29]), .Y(n620) );
AO22XLTS U1347 ( .A0(n1584), .A1(DMP_SFG[28]), .B0(n1582), .B1(
DMP_exp_NRM_EW[5]), .Y(n622) );
AO22XLTS U1348 ( .A0(n1615), .A1(DMP_SHT2_EWSW[28]), .B0(n1574), .B1(
DMP_SFG[28]), .Y(n623) );
AO22XLTS U1349 ( .A0(n920), .A1(DMP_SHT1_EWSW[28]), .B0(n1764), .B1(
DMP_SHT2_EWSW[28]), .Y(n624) );
AO22XLTS U1350 ( .A0(n1563), .A1(DMP_EXP_EWSW[28]), .B0(n1573), .B1(
DMP_SHT1_EWSW[28]), .Y(n625) );
AO22XLTS U1351 ( .A0(n1584), .A1(DMP_SFG[27]), .B0(n1582), .B1(
DMP_exp_NRM_EW[4]), .Y(n627) );
AO22XLTS U1352 ( .A0(n1615), .A1(DMP_SHT2_EWSW[27]), .B0(n1562), .B1(
DMP_SFG[27]), .Y(n628) );
AO22XLTS U1353 ( .A0(busy), .A1(DMP_SHT1_EWSW[27]), .B0(n1764), .B1(
DMP_SHT2_EWSW[27]), .Y(n629) );
AO22XLTS U1354 ( .A0(n1563), .A1(DMP_EXP_EWSW[27]), .B0(n1573), .B1(
DMP_SHT1_EWSW[27]), .Y(n630) );
AO22XLTS U1355 ( .A0(n1588), .A1(DMP_SFG[26]), .B0(n1582), .B1(
DMP_exp_NRM_EW[3]), .Y(n632) );
AO22XLTS U1356 ( .A0(n1615), .A1(DMP_SHT2_EWSW[26]), .B0(n1562), .B1(
DMP_SFG[26]), .Y(n633) );
AO22XLTS U1357 ( .A0(n1561), .A1(DMP_SHT1_EWSW[26]), .B0(n1764), .B1(
DMP_SHT2_EWSW[26]), .Y(n634) );
AO22XLTS U1358 ( .A0(n1552), .A1(DMP_EXP_EWSW[26]), .B0(n1573), .B1(
DMP_SHT1_EWSW[26]), .Y(n635) );
AO22XLTS U1359 ( .A0(n1588), .A1(DMP_SFG[25]), .B0(n1582), .B1(
DMP_exp_NRM_EW[2]), .Y(n637) );
AO22XLTS U1360 ( .A0(n1615), .A1(DMP_SHT2_EWSW[25]), .B0(n1562), .B1(
DMP_SFG[25]), .Y(n638) );
AO22XLTS U1361 ( .A0(n893), .A1(DMP_SHT1_EWSW[25]), .B0(n894), .B1(
DMP_SHT2_EWSW[25]), .Y(n639) );
AO22XLTS U1362 ( .A0(n1636), .A1(DMP_EXP_EWSW[25]), .B0(n1573), .B1(
DMP_SHT1_EWSW[25]), .Y(n640) );
AO22XLTS U1363 ( .A0(n1584), .A1(DMP_SFG[24]), .B0(n1582), .B1(
DMP_exp_NRM_EW[1]), .Y(n642) );
AO22XLTS U1364 ( .A0(n1615), .A1(DMP_SHT2_EWSW[24]), .B0(n1562), .B1(
DMP_SFG[24]), .Y(n643) );
AO22XLTS U1365 ( .A0(n1561), .A1(DMP_SHT1_EWSW[24]), .B0(n1764), .B1(
DMP_SHT2_EWSW[24]), .Y(n644) );
AO22XLTS U1366 ( .A0(n1636), .A1(DMP_EXP_EWSW[24]), .B0(n1573), .B1(
DMP_SHT1_EWSW[24]), .Y(n645) );
AO22XLTS U1367 ( .A0(n1588), .A1(DMP_SFG[23]), .B0(n1717), .B1(
DMP_exp_NRM_EW[0]), .Y(n647) );
AO22XLTS U1368 ( .A0(n1615), .A1(DMP_SHT2_EWSW[23]), .B0(n1562), .B1(
DMP_SFG[23]), .Y(n648) );
AO22XLTS U1369 ( .A0(n1561), .A1(DMP_SHT1_EWSW[23]), .B0(n894), .B1(
DMP_SHT2_EWSW[23]), .Y(n649) );
AO22XLTS U1370 ( .A0(n1636), .A1(DMP_EXP_EWSW[23]), .B0(n1573), .B1(
DMP_SHT1_EWSW[23]), .Y(n650) );
AO22XLTS U1371 ( .A0(n1561), .A1(DMP_SHT1_EWSW[22]), .B0(n894), .B1(
DMP_SHT2_EWSW[22]), .Y(n652) );
AO22XLTS U1372 ( .A0(n1636), .A1(DMP_EXP_EWSW[22]), .B0(n1573), .B1(
DMP_SHT1_EWSW[22]), .Y(n653) );
AO22XLTS U1373 ( .A0(n1561), .A1(DMP_SHT1_EWSW[21]), .B0(n894), .B1(
DMP_SHT2_EWSW[21]), .Y(n655) );
AO22XLTS U1374 ( .A0(n1636), .A1(DMP_EXP_EWSW[21]), .B0(n1573), .B1(
DMP_SHT1_EWSW[21]), .Y(n656) );
AO22XLTS U1375 ( .A0(n1561), .A1(DMP_SHT1_EWSW[20]), .B0(n894), .B1(
DMP_SHT2_EWSW[20]), .Y(n658) );
AO22XLTS U1376 ( .A0(n1636), .A1(DMP_EXP_EWSW[20]), .B0(n1560), .B1(
DMP_SHT1_EWSW[20]), .Y(n659) );
AO22XLTS U1377 ( .A0(n1561), .A1(DMP_SHT1_EWSW[19]), .B0(n894), .B1(
DMP_SHT2_EWSW[19]), .Y(n661) );
AO22XLTS U1378 ( .A0(n1636), .A1(DMP_EXP_EWSW[19]), .B0(n1560), .B1(
DMP_SHT1_EWSW[19]), .Y(n662) );
AO22XLTS U1379 ( .A0(n1561), .A1(DMP_SHT1_EWSW[18]), .B0(n894), .B1(
DMP_SHT2_EWSW[18]), .Y(n664) );
AO22XLTS U1380 ( .A0(n1636), .A1(DMP_EXP_EWSW[18]), .B0(n1560), .B1(
DMP_SHT1_EWSW[18]), .Y(n665) );
AO22XLTS U1381 ( .A0(n1561), .A1(DMP_SHT1_EWSW[17]), .B0(n894), .B1(
DMP_SHT2_EWSW[17]), .Y(n667) );
AO22XLTS U1382 ( .A0(n1559), .A1(DMP_EXP_EWSW[17]), .B0(n1560), .B1(
DMP_SHT1_EWSW[17]), .Y(n668) );
AO22XLTS U1383 ( .A0(n1561), .A1(DMP_SHT1_EWSW[16]), .B0(n894), .B1(
DMP_SHT2_EWSW[16]), .Y(n670) );
AO22XLTS U1384 ( .A0(n1559), .A1(DMP_EXP_EWSW[16]), .B0(n1560), .B1(
DMP_SHT1_EWSW[16]), .Y(n671) );
AO22XLTS U1385 ( .A0(n893), .A1(DMP_SHT1_EWSW[15]), .B0(n895), .B1(
DMP_SHT2_EWSW[15]), .Y(n673) );
AO22XLTS U1386 ( .A0(n1559), .A1(DMP_EXP_EWSW[15]), .B0(n1560), .B1(
DMP_SHT1_EWSW[15]), .Y(n674) );
AO22XLTS U1387 ( .A0(n893), .A1(DMP_SHT1_EWSW[14]), .B0(n895), .B1(
DMP_SHT2_EWSW[14]), .Y(n676) );
AO22XLTS U1388 ( .A0(n1559), .A1(DMP_EXP_EWSW[14]), .B0(n1560), .B1(
DMP_SHT1_EWSW[14]), .Y(n677) );
AO22XLTS U1389 ( .A0(n893), .A1(DMP_SHT1_EWSW[13]), .B0(n1558), .B1(
DMP_SHT2_EWSW[13]), .Y(n679) );
AO22XLTS U1390 ( .A0(n1559), .A1(DMP_EXP_EWSW[13]), .B0(n1560), .B1(
DMP_SHT1_EWSW[13]), .Y(n680) );
AO22XLTS U1391 ( .A0(n893), .A1(DMP_SHT1_EWSW[12]), .B0(n1558), .B1(
DMP_SHT2_EWSW[12]), .Y(n682) );
AO22XLTS U1392 ( .A0(n1559), .A1(DMP_EXP_EWSW[12]), .B0(n1560), .B1(
DMP_SHT1_EWSW[12]), .Y(n683) );
AO22XLTS U1393 ( .A0(n893), .A1(DMP_SHT1_EWSW[11]), .B0(n1558), .B1(
DMP_SHT2_EWSW[11]), .Y(n685) );
AO22XLTS U1394 ( .A0(n1559), .A1(DMP_EXP_EWSW[11]), .B0(n1560), .B1(
DMP_SHT1_EWSW[11]), .Y(n686) );
AO22XLTS U1395 ( .A0(n893), .A1(DMP_SHT1_EWSW[10]), .B0(n1558), .B1(
DMP_SHT2_EWSW[10]), .Y(n688) );
AO22XLTS U1396 ( .A0(n1559), .A1(DMP_EXP_EWSW[10]), .B0(n1557), .B1(
DMP_SHT1_EWSW[10]), .Y(n689) );
AO22XLTS U1397 ( .A0(n893), .A1(DMP_SHT1_EWSW[9]), .B0(n1558), .B1(
DMP_SHT2_EWSW[9]), .Y(n691) );
AO22XLTS U1398 ( .A0(n1559), .A1(DMP_EXP_EWSW[9]), .B0(n1557), .B1(
DMP_SHT1_EWSW[9]), .Y(n692) );
AO22XLTS U1399 ( .A0(n920), .A1(DMP_SHT1_EWSW[8]), .B0(n1558), .B1(
DMP_SHT2_EWSW[8]), .Y(n694) );
AO22XLTS U1400 ( .A0(n1559), .A1(DMP_EXP_EWSW[8]), .B0(n1557), .B1(
DMP_SHT1_EWSW[8]), .Y(n695) );
AO22XLTS U1401 ( .A0(n920), .A1(DMP_SHT1_EWSW[7]), .B0(n1558), .B1(
DMP_SHT2_EWSW[7]), .Y(n697) );
AO22XLTS U1402 ( .A0(n1556), .A1(DMP_EXP_EWSW[7]), .B0(n1557), .B1(
DMP_SHT1_EWSW[7]), .Y(n698) );
AO22XLTS U1403 ( .A0(busy), .A1(DMP_SHT1_EWSW[6]), .B0(n1558), .B1(
DMP_SHT2_EWSW[6]), .Y(n700) );
AO22XLTS U1404 ( .A0(n1556), .A1(DMP_EXP_EWSW[6]), .B0(n1557), .B1(
DMP_SHT1_EWSW[6]), .Y(n701) );
AO22XLTS U1405 ( .A0(busy), .A1(DMP_SHT1_EWSW[5]), .B0(n1558), .B1(
DMP_SHT2_EWSW[5]), .Y(n703) );
AO22XLTS U1406 ( .A0(n1556), .A1(DMP_EXP_EWSW[5]), .B0(n1557), .B1(
DMP_SHT1_EWSW[5]), .Y(n704) );
AO22XLTS U1407 ( .A0(n920), .A1(DMP_SHT1_EWSW[4]), .B0(n1558), .B1(
DMP_SHT2_EWSW[4]), .Y(n706) );
AO22XLTS U1408 ( .A0(n1556), .A1(DMP_EXP_EWSW[4]), .B0(n1557), .B1(
DMP_SHT1_EWSW[4]), .Y(n707) );
AO22XLTS U1409 ( .A0(n920), .A1(DMP_SHT1_EWSW[3]), .B0(n895), .B1(
DMP_SHT2_EWSW[3]), .Y(n709) );
AO22XLTS U1410 ( .A0(n1556), .A1(DMP_EXP_EWSW[3]), .B0(n1557), .B1(
DMP_SHT1_EWSW[3]), .Y(n710) );
AO22XLTS U1411 ( .A0(n1629), .A1(DMP_SFG[2]), .B0(n1624), .B1(
DMP_SHT2_EWSW[2]), .Y(n711) );
AO22XLTS U1412 ( .A0(n920), .A1(DMP_SHT1_EWSW[2]), .B0(n895), .B1(
DMP_SHT2_EWSW[2]), .Y(n712) );
AO22XLTS U1413 ( .A0(n1556), .A1(DMP_EXP_EWSW[2]), .B0(n1557), .B1(
DMP_SHT1_EWSW[2]), .Y(n713) );
AO22XLTS U1414 ( .A0(busy), .A1(DMP_SHT1_EWSW[1]), .B0(n895), .B1(
DMP_SHT2_EWSW[1]), .Y(n715) );
AO22XLTS U1415 ( .A0(n1556), .A1(DMP_EXP_EWSW[1]), .B0(n1557), .B1(
DMP_SHT1_EWSW[1]), .Y(n716) );
AO22XLTS U1416 ( .A0(busy), .A1(DMP_SHT1_EWSW[0]), .B0(n895), .B1(
DMP_SHT2_EWSW[0]), .Y(n718) );
AO22XLTS U1417 ( .A0(n1556), .A1(DMP_EXP_EWSW[0]), .B0(n1714), .B1(
DMP_SHT1_EWSW[0]), .Y(n719) );
AO22XLTS U1418 ( .A0(n1271), .A1(n1553), .B0(ZERO_FLAG_EXP), .B1(n1554), .Y(
n721) );
AO21XLTS U1419 ( .A0(OP_FLAG_EXP), .A1(n1554), .B0(n1553), .Y(n722) );
OAI21XLTS U1420 ( .A0(n1692), .A1(n1312), .B0(n1283), .Y(n723) );
OAI21XLTS U1421 ( .A0(n1644), .A1(n1312), .B0(n1304), .Y(n731) );
OAI21XLTS U1422 ( .A0(n1681), .A1(n1312), .B0(n1311), .Y(n732) );
OAI21XLTS U1423 ( .A0(n1687), .A1(n1301), .B0(n1300), .Y(n737) );
OAI21XLTS U1424 ( .A0(n1680), .A1(n1301), .B0(n1294), .Y(n740) );
OAI21XLTS U1425 ( .A0(n1685), .A1(n1301), .B0(n1290), .Y(n741) );
OAI21XLTS U1426 ( .A0(n1653), .A1(n1301), .B0(n1298), .Y(n743) );
OAI21XLTS U1427 ( .A0(n1682), .A1(n1301), .B0(n1291), .Y(n745) );
OAI21XLTS U1428 ( .A0(n1642), .A1(n1312), .B0(n1299), .Y(n753) );
AO22XLTS U1429 ( .A0(n1556), .A1(n1146), .B0(n1714), .B1(
Shift_amount_SHT1_EWR[4]), .Y(n762) );
AO22XLTS U1430 ( .A0(n1556), .A1(n1141), .B0(n1714), .B1(
Shift_amount_SHT1_EWR[3]), .Y(n763) );
AO22XLTS U1431 ( .A0(n1552), .A1(n1551), .B0(n1714), .B1(
Shift_amount_SHT1_EWR[2]), .Y(n764) );
AO22XLTS U1432 ( .A0(n1508), .A1(busy), .B0(n1506), .B1(Shift_reg_FLAGS_7[3]), .Y(n866) );
AO22XLTS U1433 ( .A0(n1506), .A1(n1567), .B0(n1508), .B1(n1509), .Y(n869) );
INVX2TS U1434 ( .A(n915), .Y(n1575) );
BUFX3TS U1435 ( .A(left_right_SHT2), .Y(n1401) );
INVX2TS U1436 ( .A(n1368), .Y(n891) );
AND2X4TS U1437 ( .A(n1567), .B(n1058), .Y(n1284) );
BUFX3TS U1438 ( .A(n1284), .Y(n1319) );
BUFX3TS U1439 ( .A(n1084), .Y(n1390) );
CLKINVX3TS U1440 ( .A(rst), .Y(n1137) );
INVX2TS U1441 ( .A(n875), .Y(n890) );
INVX2TS U1442 ( .A(n891), .Y(n892) );
INVX2TS U1443 ( .A(n1764), .Y(n893) );
INVX2TS U1444 ( .A(n893), .Y(n894) );
INVX2TS U1445 ( .A(n893), .Y(n895) );
INVX2TS U1446 ( .A(n896), .Y(n898) );
INVX2TS U1447 ( .A(n884), .Y(n899) );
INVX2TS U1448 ( .A(n884), .Y(n900) );
INVX2TS U1449 ( .A(n885), .Y(n903) );
INVX2TS U1450 ( .A(n885), .Y(n904) );
INVX4TS U1451 ( .A(n1333), .Y(n907) );
INVX4TS U1452 ( .A(n1333), .Y(n908) );
INVX2TS U1453 ( .A(n879), .Y(n909) );
INVX2TS U1454 ( .A(n879), .Y(n910) );
INVX2TS U1455 ( .A(n879), .Y(n911) );
NAND2X1TS U1456 ( .A(n1083), .B(n1082), .Y(n771) );
BUFX3TS U1457 ( .A(n1137), .Y(n1138) );
BUFX3TS U1458 ( .A(n1137), .Y(n1134) );
CLKBUFX3TS U1459 ( .A(n1137), .Y(n1136) );
NOR2X4TS U1460 ( .A(shift_value_SHT2_EWR[4]), .B(n1401), .Y(n1112) );
AOI222X1TS U1461 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n913), .B0(n918), .B1(
DmP_mant_SHT1_SW[15]), .C0(n1360), .C1(DmP_mant_SHT1_SW[16]), .Y(n1373) );
AOI222X1TS U1462 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n913), .B0(n919), .B1(
DmP_mant_SHT1_SW[17]), .C0(n1313), .C1(DmP_mant_SHT1_SW[18]), .Y(n1370) );
AOI222X1TS U1463 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n913), .B0(
DmP_mant_SHT1_SW[14]), .B1(n1313), .C0(n918), .C1(DmP_mant_SHT1_SW[13]), .Y(n1364) );
AOI222X1TS U1464 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n913), .B0(n918), .B1(
DmP_mant_SHT1_SW[11]), .C0(n1360), .C1(DmP_mant_SHT1_SW[12]), .Y(n1367) );
AOI222X1TS U1465 ( .A0(Raw_mant_NRM_SWR[14]), .A1(n913), .B0(n919), .B1(
DmP_mant_SHT1_SW[9]), .C0(n1360), .C1(DmP_mant_SHT1_SW[10]), .Y(n1363)
);
AOI222X4TS U1466 ( .A0(Data_array_SWR[14]), .A1(n902), .B0(
Data_array_SWR[22]), .B1(n876), .C0(Data_array_SWR[18]), .C1(n901),
.Y(n1400) );
AOI222X4TS U1467 ( .A0(Data_array_SWR[23]), .A1(n874), .B0(
Data_array_SWR[19]), .B1(n901), .C0(Data_array_SWR[15]), .C1(n902),
.Y(n1397) );
AOI221X1TS U1468 ( .A0(n1653), .A1(intDX_EWSW[10]), .B0(intDX_EWSW[11]),
.B1(n1660), .C0(n1163), .Y(n1168) );
AOI221X1TS U1469 ( .A0(intDX_EWSW[30]), .A1(n1692), .B0(intDX_EWSW[29]),
.B1(n1645), .C0(n997), .Y(n999) );
AOI221X1TS U1470 ( .A0(n1692), .A1(intDX_EWSW[30]), .B0(intDX_EWSW[17]),
.B1(n1678), .C0(n1154), .Y(n1161) );
NOR2X1TS U1471 ( .A(n1692), .B(intDX_EWSW[30]), .Y(n998) );
OAI211XLTS U1472 ( .A0(n1367), .A1(n910), .B0(n1366), .C0(n1365), .Y(n784)
);
AOI221X1TS U1473 ( .A0(n1683), .A1(intDX_EWSW[2]), .B0(intDX_EWSW[3]), .B1(
n1677), .C0(n1171), .Y(n1176) );
AOI221X1TS U1474 ( .A0(n1644), .A1(intDX_EWSW[22]), .B0(intDX_EWSW[23]),
.B1(n1691), .C0(n1157), .Y(n1158) );
AOI221X1TS U1475 ( .A0(n1686), .A1(intDX_EWSW[14]), .B0(intDX_EWSW[15]),
.B1(n1643), .C0(n1165), .Y(n1166) );
AOI221X1TS U1476 ( .A0(n1688), .A1(intDX_EWSW[20]), .B0(intDX_EWSW[21]),
.B1(n1681), .C0(n1156), .Y(n1159) );
AOI221X1TS U1477 ( .A0(n1685), .A1(intDX_EWSW[12]), .B0(intDX_EWSW[13]),
.B1(n1680), .C0(n1164), .Y(n1167) );
INVX2TS U1478 ( .A(n1595), .Y(n916) );
INVX2TS U1479 ( .A(n1595), .Y(n1611) );
OAI21XLTS U1480 ( .A0(n1240), .A1(n1239), .B0(n1238), .Y(n471) );
OAI21XLTS U1481 ( .A0(n1240), .A1(n1230), .B0(n1229), .Y(n469) );
OAI21XLTS U1482 ( .A0(n1240), .A1(n1234), .B0(n1233), .Y(n467) );
CLKXOR2X2TS U1483 ( .A(n1387), .B(DmP_mant_SFG_SWR[11]), .Y(
DmP_mant_SFG_SWR_signed[11]) );
XOR2X1TS U1484 ( .A(n1387), .B(DmP_mant_SFG_SWR[8]), .Y(n1480) );
XOR2X1TS U1485 ( .A(n1387), .B(DmP_mant_SFG_SWR[9]), .Y(n1483) );
XOR2X1TS U1486 ( .A(n1200), .B(DmP_mant_SFG_SWR[18]), .Y(n981) );
XOR2X1TS U1487 ( .A(n1200), .B(DmP_mant_SFG_SWR[20]), .Y(n984) );
NOR4X4TS U1488 ( .A(n964), .B(n963), .C(n1224), .D(n962), .Y(n970) );
NOR4X2TS U1489 ( .A(n1181), .B(n1180), .C(n1179), .D(n1178), .Y(n1271) );
AFHCINX2TS U1490 ( .CIN(n1427), .B(n1428), .A(DMP_SFG[21]), .S(n1429), .CO(
n1430) );
NOR2X2TS U1491 ( .A(n925), .B(DMP_EXP_EWSW[23]), .Y(n1546) );
AOI21X2TS U1492 ( .A0(Shift_amount_SHT1_EWR[1]), .A1(n877), .B0(n1498), .Y(
n965) );
XNOR2X2TS U1493 ( .A(DMP_exp_NRM2_EW[0]), .B(n878), .Y(n1186) );
BUFX3TS U1494 ( .A(n1137), .Y(n1139) );
OR2X1TS U1495 ( .A(n978), .B(DMP_SFG[14]), .Y(n1454) );
AND2X2TS U1496 ( .A(DMP_SFG[6]), .B(n1480), .Y(n977) );
OAI2BB2XLTS U1497 ( .B0(n1470), .B1(n1469), .A0N(DMP_SFG[5]), .A1N(n1585),
.Y(n1479) );
OAI21XLTS U1498 ( .A0(n1266), .A1(intDX_EWSW[31]), .B0(n1567), .Y(n1182) );
AOI222X4TS U1499 ( .A0(n1601), .A1(left_right_SHT2), .B0(Data_array_SWR[6]),
.B1(n900), .C0(n1600), .C1(n1112), .Y(n1230) );
INVX2TS U1500 ( .A(n949), .Y(n917) );
INVX2TS U1501 ( .A(n949), .Y(n918) );
INVX2TS U1502 ( .A(n949), .Y(n919) );
AOI221X1TS U1503 ( .A0(n1694), .A1(intDX_EWSW[18]), .B0(intDX_EWSW[19]),
.B1(n1646), .C0(n1155), .Y(n1160) );
AOI32X1TS U1504 ( .A0(n1694), .A1(n1042), .A2(intDX_EWSW[18]), .B0(
intDX_EWSW[19]), .B1(n1646), .Y(n1043) );
AOI221X1TS U1505 ( .A0(n1690), .A1(intDX_EWSW[28]), .B0(intDX_EWSW[29]),
.B1(n1645), .C0(n1149), .Y(n1151) );
NOR2X1TS U1506 ( .A(n1645), .B(intDX_EWSW[29]), .Y(n996) );
OAI211XLTS U1507 ( .A0(n1364), .A1(n911), .B0(n1352), .C0(n1351), .Y(n786)
);
NOR3X1TS U1508 ( .A(shift_value_SHT2_EWR[4]), .B(shift_value_SHT2_EWR[2]),
.C(n1652), .Y(n1084) );
INVX2TS U1509 ( .A(n1764), .Y(n920) );
OAI2BB2XLTS U1510 ( .B0(intDY_EWSW[0]), .B1(n1022), .A0N(intDX_EWSW[1]),
.A1N(n1765), .Y(n1024) );
AOI22X1TS U1511 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n941), .B0(n1126), .B1(
Raw_mant_NRM_SWR[10]), .Y(n960) );
NOR2XLTS U1512 ( .A(n1660), .B(intDX_EWSW[11]), .Y(n1002) );
NOR2XLTS U1513 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[9]), .Y(n1220)
);
NOR2X1TS U1514 ( .A(n1678), .B(intDX_EWSW[17]), .Y(n1040) );
BUFX3TS U1515 ( .A(n1636), .Y(n921) );
NOR2X4TS U1516 ( .A(shift_value_SHT2_EWR[4]), .B(n1617), .Y(n1604) );
OAI21XLTS U1517 ( .A0(intDX_EWSW[13]), .A1(n1680), .B0(intDX_EWSW[12]), .Y(
n1001) );
OA22X1TS U1518 ( .A0(n1686), .A1(intDX_EWSW[14]), .B0(n1643), .B1(
intDX_EWSW[15]), .Y(n1013) );
OA22X1TS U1519 ( .A0(n1644), .A1(intDX_EWSW[22]), .B0(n1691), .B1(
intDX_EWSW[23]), .Y(n1050) );
OAI21XLTS U1520 ( .A0(intDX_EWSW[3]), .A1(n1677), .B0(intDX_EWSW[2]), .Y(
n1025) );
NOR2X2TS U1521 ( .A(n1067), .B(n1499), .Y(n926) );
OAI21XLTS U1522 ( .A0(intDX_EWSW[1]), .A1(n1765), .B0(intDX_EWSW[0]), .Y(
n1022) );
AND4X1TS U1523 ( .A(n1090), .B(n1089), .C(exp_rslt_NRM2_EW1[4]), .D(n1088),
.Y(n1091) );
AOI2BB2X1TS U1524 ( .B0(n1000), .B1(n1052), .A0N(n999), .A1N(n998), .Y(n1057) );
OR2X1TS U1525 ( .A(n979), .B(DMP_SFG[15]), .Y(n1445) );
INVX2TS U1526 ( .A(n1101), .Y(n1107) );
OR2X1TS U1527 ( .A(n982), .B(DMP_SFG[17]), .Y(n1410) );
NAND2X2TS U1528 ( .A(n1576), .B(n948), .Y(n1533) );
NOR2X1TS U1529 ( .A(n1079), .B(n1078), .Y(intadd_50_B_2_) );
OAI21XLTS U1530 ( .A0(DmP_EXP_EWSW[25]), .A1(n924), .B0(n1548), .Y(n1549) );
NOR2XLTS U1531 ( .A(n926), .B(SIGN_FLAG_SHT1SHT2), .Y(n1384) );
XOR2X1TS U1532 ( .A(n988), .B(n987), .Y(n990) );
BUFX3TS U1533 ( .A(n1514), .Y(n1524) );
OAI211XLTS U1534 ( .A0(n1373), .A1(n910), .B0(n1372), .C0(n1371), .Y(n788)
);
OAI21XLTS U1535 ( .A0(n1240), .A1(n1228), .B0(n1227), .Y(n472) );
OAI211XLTS U1536 ( .A0(n1347), .A1(n908), .B0(n1346), .C0(n1345), .Y(n774)
);
OAI211XLTS U1537 ( .A0(n1370), .A1(n910), .B0(n1358), .C0(n1357), .Y(n790)
);
NOR2X2TS U1538 ( .A(Raw_mant_NRM_SWR[22]), .B(Raw_mant_NRM_SWR[23]), .Y(n955) );
INVX2TS U1539 ( .A(n955), .Y(n929) );
NOR3X2TS U1540 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[19]), .C(
Raw_mant_NRM_SWR[20]), .Y(n1495) );
NAND2X2TS U1541 ( .A(n1489), .B(n1495), .Y(n931) );
NOR2X2TS U1542 ( .A(Raw_mant_NRM_SWR[18]), .B(n931), .Y(n1119) );
NAND2X2TS U1543 ( .A(n1119), .B(n1118), .Y(n933) );
OR2X4TS U1544 ( .A(n933), .B(Raw_mant_NRM_SWR[14]), .Y(n1122) );
NAND2X2TS U1545 ( .A(n959), .B(n1633), .Y(n938) );
NAND2X4TS U1546 ( .A(n957), .B(n1655), .Y(n1217) );
INVX2TS U1547 ( .A(n1217), .Y(n940) );
INVX2TS U1548 ( .A(n931), .Y(n941) );
AOI21X1TS U1549 ( .A0(n1675), .A1(Raw_mant_NRM_SWR[20]), .B0(
Raw_mant_NRM_SWR[22]), .Y(n932) );
NOR2X2TS U1550 ( .A(n1659), .B(n933), .Y(n964) );
INVX2TS U1551 ( .A(n964), .Y(n934) );
OAI31X1TS U1552 ( .A0(Raw_mant_NRM_SWR[9]), .A1(n938), .A2(n1632), .B0(n937),
.Y(n939) );
OAI32X1TS U1553 ( .A0(Raw_mant_NRM_SWR[3]), .A1(Raw_mant_NRM_SWR[1]), .A2(
n1639), .B0(n1634), .B1(Raw_mant_NRM_SWR[3]), .Y(n943) );
NOR2X6TS U1554 ( .A(Raw_mant_NRM_SWR[6]), .B(n1217), .Y(n1490) );
OAI211X1TS U1555 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n943), .B0(n1490), .C0(
n1654), .Y(n944) );
NAND2BX4TS U1556 ( .AN(n945), .B(n944), .Y(n1497) );
NOR2BX4TS U1557 ( .AN(n946), .B(n1497), .Y(n948) );
INVX2TS U1558 ( .A(n1533), .Y(n947) );
AOI22X1TS U1559 ( .A0(n919), .A1(DmP_mant_SHT1_SW[8]), .B0(n1313), .B1(
DmP_mant_SHT1_SW[9]), .Y(n950) );
AOI21X1TS U1560 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n897), .B0(n951), .Y(n1537)
);
INVX2TS U1561 ( .A(n1540), .Y(n1359) );
CLKBUFX2TS U1562 ( .A(n1359), .Y(n1113) );
BUFX3TS U1563 ( .A(n1113), .Y(n1369) );
AOI21X1TS U1564 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n952), .B0(
Raw_mant_NRM_SWR[19]), .Y(n954) );
AOI21X1TS U1565 ( .A0(n956), .A1(n955), .B0(n880), .Y(n963) );
NOR2X1TS U1566 ( .A(Raw_mant_NRM_SWR[3]), .B(Raw_mant_NRM_SWR[2]), .Y(n1121)
);
NOR2X1TS U1567 ( .A(Raw_mant_NRM_SWR[4]), .B(Raw_mant_NRM_SWR[5]), .Y(n1218)
);
OAI21X1TS U1568 ( .A0(Raw_mant_NRM_SWR[6]), .A1(Raw_mant_NRM_SWR[7]), .B0(
n957), .Y(n958) );
OAI21X2TS U1569 ( .A0(n1121), .A1(n1222), .B0(n958), .Y(n1224) );
INVX2TS U1570 ( .A(n959), .Y(n961) );
OAI31X1TS U1571 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n1633), .A2(n961), .B0(n960), .Y(n962) );
NOR2X4TS U1572 ( .A(n970), .B(n1575), .Y(n1498) );
NOR2X4TS U1573 ( .A(n1369), .B(n965), .Y(n1333) );
BUFX3TS U1574 ( .A(n1313), .Y(n1360) );
AOI21X1TS U1575 ( .A0(n1369), .A1(Data_array_SWR[8]), .B0(n966), .Y(n967) );
AOI22X1TS U1576 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n890), .B0(n1527), .B1(
DmP_mant_SHT1_SW[19]), .Y(n968) );
AOI21X1TS U1577 ( .A0(n919), .A1(DmP_mant_SHT1_SW[18]), .B0(n969), .Y(n1309)
);
OAI22X1TS U1578 ( .A0(n1379), .A1(n907), .B0(n1634), .B1(n891), .Y(n971) );
AOI21X1TS U1579 ( .A0(n1369), .A1(Data_array_SWR[20]), .B0(n971), .Y(n972)
);
AOI22X1TS U1580 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n1531), .B0(
DmP_mant_SHT1_SW[15]), .B1(n1360), .Y(n973) );
OAI2BB1X1TS U1581 ( .A0N(Raw_mant_NRM_SWR[9]), .A1N(n913), .B0(n973), .Y(
n974) );
AOI21X1TS U1582 ( .A0(DmP_mant_SHT1_SW[14]), .A1(n917), .B0(n974), .Y(n1530)
);
OAI22X1TS U1583 ( .A0(n1306), .A1(n907), .B0(n1702), .B1(n891), .Y(n975) );
AOI21X1TS U1584 ( .A0(n1369), .A1(Data_array_SWR[16]), .B0(n975), .Y(n976)
);
XOR2X1TS U1585 ( .A(n1200), .B(DmP_mant_SFG_SWR[24]), .Y(n1431) );
XOR2X1TS U1586 ( .A(n1200), .B(DmP_mant_SFG_SWR[23]), .Y(n1428) );
XOR2X1TS U1587 ( .A(n1200), .B(DmP_mant_SFG_SWR[22]), .Y(n1425) );
XOR2X1TS U1588 ( .A(n1200), .B(DmP_mant_SFG_SWR[21]), .Y(n1405) );
XOR2X1TS U1589 ( .A(n1387), .B(DmP_mant_SFG_SWR[15]), .Y(n1450) );
XOR2X1TS U1590 ( .A(n1387), .B(DmP_mant_SFG_SWR[14]), .Y(n1459) );
XOR2X1TS U1591 ( .A(n1387), .B(DmP_mant_SFG_SWR[13]), .Y(n1462) );
XOR2X1TS U1592 ( .A(n1387), .B(DmP_mant_SFG_SWR[12]), .Y(n1475) );
XOR2X1TS U1593 ( .A(n1200), .B(DmP_mant_SFG_SWR[16]), .Y(n978) );
XOR2X1TS U1594 ( .A(n1200), .B(DmP_mant_SFG_SWR[17]), .Y(n979) );
NOR2X2TS U1595 ( .A(n981), .B(DMP_SFG[16]), .Y(n1437) );
XOR2X1TS U1596 ( .A(n1200), .B(DmP_mant_SFG_SWR[19]), .Y(n982) );
NOR2X2TS U1597 ( .A(n984), .B(DMP_SFG[18]), .Y(n1418) );
NAND2X1TS U1598 ( .A(n978), .B(DMP_SFG[14]), .Y(n1453) );
INVX2TS U1599 ( .A(n1453), .Y(n1443) );
NAND2X1TS U1600 ( .A(n979), .B(DMP_SFG[15]), .Y(n1444) );
INVX2TS U1601 ( .A(n1444), .Y(n980) );
AOI21X1TS U1602 ( .A0(n1445), .A1(n1443), .B0(n980), .Y(n1434) );
NAND2X1TS U1603 ( .A(n981), .B(DMP_SFG[16]), .Y(n1438) );
NAND2X1TS U1604 ( .A(n982), .B(DMP_SFG[17]), .Y(n1409) );
INVX2TS U1605 ( .A(n1409), .Y(n983) );
NAND2X1TS U1606 ( .A(n984), .B(DMP_SFG[18]), .Y(n1419) );
XOR2X1TS U1607 ( .A(n1387), .B(DmP_mant_SFG_SWR[25]), .Y(n987) );
INVX4TS U1608 ( .A(n989), .Y(n1451) );
NOR2X1TS U1609 ( .A(n1676), .B(intDX_EWSW[25]), .Y(n1053) );
AOI22X1TS U1610 ( .A0(intDX_EWSW[25]), .A1(n1676), .B0(intDX_EWSW[24]), .B1(
n991), .Y(n995) );
OAI21X2TS U1611 ( .A0(intDX_EWSW[26]), .A1(n1689), .B0(n992), .Y(n1148) );
NOR3X1TS U1612 ( .A(n1658), .B(n996), .C(intDY_EWSW[28]), .Y(n997) );
OAI2BB2XLTS U1613 ( .B0(intDY_EWSW[12]), .B1(n1001), .A0N(intDX_EWSW[13]),
.A1N(n1680), .Y(n1012) );
AOI22X1TS U1614 ( .A0(intDX_EWSW[11]), .A1(n1660), .B0(intDX_EWSW[10]), .B1(
n1003), .Y(n1008) );
AOI21X1TS U1615 ( .A0(n1006), .A1(n1005), .B0(n1015), .Y(n1007) );
OAI22X1TS U1616 ( .A0(n1653), .A1(intDX_EWSW[10]), .B0(n1660), .B1(
intDX_EWSW[11]), .Y(n1163) );
INVX2TS U1617 ( .A(n1163), .Y(n1016) );
OAI2BB2XLTS U1618 ( .B0(intDY_EWSW[14]), .B1(n1009), .A0N(intDX_EWSW[15]),
.A1N(n1643), .Y(n1010) );
AOI211X1TS U1619 ( .A0(n1013), .A1(n1012), .B0(n1011), .C0(n1010), .Y(n1014)
);
OAI2BB1X1TS U1620 ( .A0N(n1651), .A1N(intDY_EWSW[5]), .B0(intDX_EWSW[4]),
.Y(n1020) );
OAI22X1TS U1621 ( .A0(intDY_EWSW[4]), .A1(n1020), .B0(n1651), .B1(
intDY_EWSW[5]), .Y(n1031) );
OAI2BB1X1TS U1622 ( .A0N(n1638), .A1N(intDY_EWSW[7]), .B0(intDX_EWSW[6]),
.Y(n1021) );
OAI22X1TS U1623 ( .A0(intDY_EWSW[6]), .A1(n1021), .B0(n1638), .B1(
intDY_EWSW[7]), .Y(n1030) );
AOI22X1TS U1624 ( .A0(intDY_EWSW[7]), .A1(n1638), .B0(intDY_EWSW[6]), .B1(
n1657), .Y(n1028) );
OAI32X1TS U1625 ( .A0(n1031), .A1(n1030), .A2(n1029), .B0(n1028), .B1(n1030),
.Y(n1032) );
OAI21X2TS U1626 ( .A0(intDX_EWSW[18]), .A1(n1694), .B0(n1042), .Y(n1155) );
OAI2BB2XLTS U1627 ( .B0(intDY_EWSW[20]), .B1(n1039), .A0N(intDX_EWSW[21]),
.A1N(n1681), .Y(n1049) );
AOI22X1TS U1628 ( .A0(intDX_EWSW[17]), .A1(n1678), .B0(intDX_EWSW[16]), .B1(
n1041), .Y(n1044) );
OAI32X1TS U1629 ( .A0(n1155), .A1(n1045), .A2(n1044), .B0(n1043), .B1(n1045),
.Y(n1048) );
OAI2BB2XLTS U1630 ( .B0(intDY_EWSW[22]), .B1(n1046), .A0N(intDX_EWSW[23]),
.A1N(n1691), .Y(n1047) );
AOI211X1TS U1631 ( .A0(n1050), .A1(n1049), .B0(n1048), .C0(n1047), .Y(n1055)
);
NAND4BBX1TS U1632 ( .AN(n1148), .BN(n1053), .C(n1052), .D(n1051), .Y(n1054)
);
BUFX3TS U1633 ( .A(n1243), .Y(n1554) );
NOR2X4TS U1634 ( .A(n1058), .B(n1554), .Y(n1245) );
INVX2TS U1635 ( .A(n1287), .Y(n1279) );
AOI22X1TS U1636 ( .A0(intDX_EWSW[3]), .A1(n1319), .B0(DMP_EXP_EWSW[3]), .B1(
n1554), .Y(n1059) );
NOR2X2TS U1637 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1669), .Y(n1504) );
INVX2TS U1638 ( .A(exp_rslt_NRM2_EW1[4]), .Y(n1069) );
INVX2TS U1639 ( .A(Shift_reg_FLAGS_7[0]), .Y(n1187) );
INVX2TS U1640 ( .A(DP_OP_15J48_123_3372_n4), .Y(n1061) );
XNOR2X2TS U1641 ( .A(DMP_exp_NRM2_EW[6]), .B(n1065), .Y(n1090) );
INVX2TS U1642 ( .A(exp_rslt_NRM2_EW1[3]), .Y(n1075) );
INVX2TS U1643 ( .A(exp_rslt_NRM2_EW1[2]), .Y(n1071) );
XNOR2X2TS U1644 ( .A(DMP_exp_NRM2_EW[5]), .B(DP_OP_15J48_123_3372_n4), .Y(
n1089) );
INVX2TS U1645 ( .A(n1065), .Y(n1066) );
XNOR2X2TS U1646 ( .A(DMP_exp_NRM2_EW[7]), .B(n1092), .Y(n1499) );
NAND2X2TS U1647 ( .A(n926), .B(Shift_reg_FLAGS_7[0]), .Y(n1569) );
BUFX3TS U1648 ( .A(n1187), .Y(n1507) );
NAND2X1TS U1649 ( .A(n1507), .B(final_result_ieee[27]), .Y(n1068) );
NAND2X1TS U1650 ( .A(n1507), .B(final_result_ieee[25]), .Y(n1070) );
NAND2X1TS U1651 ( .A(n1507), .B(final_result_ieee[28]), .Y(n1072) );
NAND2X1TS U1652 ( .A(n1507), .B(final_result_ieee[26]), .Y(n1074) );
NAND2X1TS U1653 ( .A(n1507), .B(final_result_ieee[29]), .Y(n1076) );
NOR2XLTS U1654 ( .A(n1661), .B(DmP_mant_SFG_SWR[6]), .Y(n1079) );
AOI22X1TS U1655 ( .A0(n1353), .A1(Raw_mant_NRM_SWR[24]), .B0(n1359), .B1(
Data_array_SWR[0]), .Y(n1083) );
NAND2X1TS U1656 ( .A(n913), .B(Raw_mant_NRM_SWR[23]), .Y(n1081) );
AOI22X1TS U1657 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n890), .B0(n1360), .B1(
DmP_mant_SHT1_SW[1]), .Y(n1080) );
OAI211X1TS U1658 ( .A0(n1715), .A1(n949), .B0(n1081), .C0(n1080), .Y(n1340)
);
AOI22X1TS U1659 ( .A0(n1333), .A1(n1340), .B0(n898), .B1(
Raw_mant_NRM_SWR[25]), .Y(n1082) );
NAND2X2TS U1660 ( .A(shift_value_SHT2_EWR[2]), .B(n1652), .Y(n1108) );
AOI22X1TS U1661 ( .A0(Data_array_SWR[14]), .A1(n901), .B0(Data_array_SWR[10]), .B1(n902), .Y(n1087) );
NOR2X4TS U1662 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n1101) );
AOI22X1TS U1663 ( .A0(Data_array_SWR[22]), .A1(n1103), .B0(
Data_array_SWR[18]), .B1(n876), .Y(n1086) );
NAND2X1TS U1664 ( .A(n1087), .B(n1086), .Y(n1601) );
INVX2TS U1665 ( .A(n1108), .Y(n1102) );
AOI22X1TS U1666 ( .A0(Data_array_SWR[23]), .A1(n1102), .B0(
Data_array_SWR[19]), .B1(n1101), .Y(n1133) );
INVX2TS U1667 ( .A(n1133), .Y(n1600) );
AND4X1TS U1668 ( .A(exp_rslt_NRM2_EW1[3]), .B(exp_rslt_NRM2_EW1[2]), .C(
n1186), .D(exp_rslt_NRM2_EW1[1]), .Y(n1088) );
INVX2TS U1669 ( .A(n1092), .Y(n1093) );
OAI2BB1X2TS U1670 ( .A0N(n927), .A1N(n1094), .B0(Shift_reg_FLAGS_7[0]), .Y(
n1501) );
BUFX3TS U1671 ( .A(n1187), .Y(n1607) );
OAI2BB2XLTS U1672 ( .B0(n1230), .B1(n1611), .A0N(final_result_ieee[17]),
.A1N(n1607), .Y(n498) );
AOI22X1TS U1673 ( .A0(Data_array_SWR[15]), .A1(n901), .B0(Data_array_SWR[11]), .B1(n902), .Y(n1096) );
AOI22X1TS U1674 ( .A0(Data_array_SWR[23]), .A1(n1103), .B0(
Data_array_SWR[19]), .B1(n874), .Y(n1095) );
NAND2X1TS U1675 ( .A(n1096), .B(n1095), .Y(n1599) );
AOI22X1TS U1676 ( .A0(Data_array_SWR[22]), .A1(n1102), .B0(
Data_array_SWR[18]), .B1(n1101), .Y(n1130) );
INVX2TS U1677 ( .A(n1130), .Y(n1598) );
OAI2BB2XLTS U1678 ( .B0(n1236), .B1(n1611), .A0N(final_result_ieee[16]),
.A1N(n1607), .Y(n500) );
AOI22X1TS U1679 ( .A0(Data_array_SWR[17]), .A1(n1390), .B0(
Data_array_SWR[13]), .B1(n1085), .Y(n1098) );
AOI22X1TS U1680 ( .A0(Data_array_SWR[21]), .A1(n876), .B0(Data_array_SWR[25]), .B1(n1103), .Y(n1097) );
NAND2X1TS U1681 ( .A(n1098), .B(n1097), .Y(n1192) );
OR2X1TS U1682 ( .A(shift_value_SHT2_EWR[2]), .B(n1652), .Y(n1106) );
OAI222X4TS U1683 ( .A0(n1721), .A1(n1106), .B0(n1722), .B1(n1108), .C0(n1723), .C1(n1107), .Y(n1201) );
OAI2BB2XLTS U1684 ( .B0(n1228), .B1(n1611), .A0N(final_result_ieee[14]),
.A1N(n1607), .Y(n504) );
AOI22X1TS U1685 ( .A0(Data_array_SWR[21]), .A1(n1101), .B0(
Data_array_SWR[25]), .B1(n1102), .Y(n1111) );
AOI22X1TS U1686 ( .A0(Data_array_SWR[13]), .A1(n901), .B0(Data_array_SWR[9]),
.B1(n1085), .Y(n1100) );
NAND2X1TS U1687 ( .A(Data_array_SWR[17]), .B(n874), .Y(n1099) );
OAI211X1TS U1688 ( .A0(n1111), .A1(n882), .B0(n1100), .C0(n1099), .Y(n1603)
);
AO22X1TS U1689 ( .A0(Data_array_SWR[24]), .A1(n1102), .B0(Data_array_SWR[20]), .B1(n1101), .Y(n1602) );
OAI2BB2XLTS U1690 ( .B0(n1232), .B1(n1611), .A0N(final_result_ieee[18]),
.A1N(n1607), .Y(n496) );
AOI22X1TS U1691 ( .A0(Data_array_SWR[12]), .A1(n1085), .B0(
Data_array_SWR[16]), .B1(n1390), .Y(n1105) );
AOI22X1TS U1692 ( .A0(Data_array_SWR[24]), .A1(n1103), .B0(
Data_array_SWR[20]), .B1(n876), .Y(n1104) );
NAND2X1TS U1693 ( .A(n1105), .B(n1104), .Y(n1195) );
OAI222X4TS U1694 ( .A0(n1718), .A1(n1108), .B0(n1719), .B1(n1107), .C0(n1720), .C1(n1106), .Y(n1207) );
OAI2BB2XLTS U1695 ( .B0(n1239), .B1(n1611), .A0N(final_result_ieee[15]),
.A1N(n1607), .Y(n502) );
AOI22X1TS U1696 ( .A0(Data_array_SWR[12]), .A1(n901), .B0(Data_array_SWR[8]),
.B1(n902), .Y(n1110) );
AOI22X1TS U1697 ( .A0(Data_array_SWR[16]), .A1(n874), .B0(
shift_value_SHT2_EWR[4]), .B1(n1602), .Y(n1109) );
NAND2X1TS U1698 ( .A(n1110), .B(n1109), .Y(n1606) );
INVX2TS U1699 ( .A(n1111), .Y(n1605) );
OAI2BB2XLTS U1700 ( .B0(n1234), .B1(n1611), .A0N(final_result_ieee[19]),
.A1N(n1607), .Y(n494) );
AOI21X1TS U1701 ( .A0(n898), .A1(Raw_mant_NRM_SWR[0]), .B0(n918), .Y(n1525)
);
OAI2BB2XLTS U1702 ( .B0(n1525), .B1(n911), .A0N(n1113), .A1N(
Data_array_SWR[25]), .Y(n796) );
OAI22X1TS U1703 ( .A0(n1709), .A1(n1533), .B0(n1639), .B1(n875), .Y(n1114)
);
OAI2BB2XLTS U1704 ( .B0(n1380), .B1(n910), .A0N(n1113), .A1N(
Data_array_SWR[24]), .Y(n795) );
INVX2TS U1705 ( .A(DmP_mant_SFG_SWR[5]), .Y(n1625) );
INVX2TS U1706 ( .A(n1625), .Y(n1115) );
OAI32X1TS U1707 ( .A0(n877), .A1(Raw_mant_NRM_SWR[14]), .A2(n1120), .B0(
n1119), .B1(n914), .Y(n1124) );
INVX2TS U1708 ( .A(n1222), .Y(n1491) );
AOI21X1TS U1709 ( .A0(n1126), .A1(Raw_mant_NRM_SWR[10]), .B0(n1125), .Y(
n1542) );
AOI22X1TS U1710 ( .A0(Data_array_SWR[14]), .A1(n876), .B0(Data_array_SWR[10]), .B1(n1390), .Y(n1129) );
INVX2TS U1711 ( .A(n1127), .Y(n1208) );
AOI22X1TS U1712 ( .A0(Data_array_SWR[6]), .A1(n1085), .B0(Data_array_SWR[2]),
.B1(n1208), .Y(n1128) );
OAI211X1TS U1713 ( .A0(n1130), .A1(n882), .B0(n1129), .C0(n1128), .Y(n1609)
);
AOI22X1TS U1714 ( .A0(Data_array_SWR[23]), .A1(n904), .B0(n1401), .B1(n1609),
.Y(n1216) );
OAI2BB2XLTS U1715 ( .B0(n1216), .B1(n1611), .A0N(final_result_ieee[21]),
.A1N(n1701), .Y(n490) );
AOI22X1TS U1716 ( .A0(Data_array_SWR[15]), .A1(n874), .B0(Data_array_SWR[11]), .B1(n1390), .Y(n1132) );
AOI22X1TS U1717 ( .A0(Data_array_SWR[7]), .A1(n1085), .B0(Data_array_SWR[3]),
.B1(n1208), .Y(n1131) );
OAI211X1TS U1718 ( .A0(n1133), .A1(n882), .B0(n1132), .C0(n1131), .Y(n1608)
);
AOI22X1TS U1719 ( .A0(Data_array_SWR[22]), .A1(n904), .B0(n906), .B1(n1608),
.Y(n1214) );
OAI2BB2XLTS U1720 ( .B0(n1214), .B1(n1611), .A0N(final_result_ieee[20]),
.A1N(n1701), .Y(n491) );
BUFX3TS U1721 ( .A(n1736), .Y(n1741) );
BUFX3TS U1722 ( .A(n1735), .Y(n1759) );
BUFX3TS U1723 ( .A(n1735), .Y(n1740) );
BUFX3TS U1724 ( .A(n1137), .Y(n1739) );
BUFX3TS U1725 ( .A(n1138), .Y(n1760) );
CLKBUFX2TS U1726 ( .A(n1137), .Y(n1135) );
BUFX3TS U1727 ( .A(n1134), .Y(n1746) );
BUFX3TS U1728 ( .A(n1139), .Y(n1747) );
BUFX3TS U1729 ( .A(n1137), .Y(n1744) );
BUFX3TS U1730 ( .A(n1739), .Y(n1748) );
BUFX3TS U1731 ( .A(n1139), .Y(n1743) );
BUFX3TS U1732 ( .A(n1738), .Y(n1749) );
BUFX3TS U1733 ( .A(n1139), .Y(n1762) );
BUFX3TS U1734 ( .A(n1739), .Y(n1761) );
BUFX3TS U1735 ( .A(n1739), .Y(n1742) );
BUFX3TS U1736 ( .A(n1738), .Y(n1745) );
BUFX3TS U1737 ( .A(n1738), .Y(n1733) );
BUFX3TS U1738 ( .A(n1736), .Y(n1750) );
BUFX3TS U1739 ( .A(n1134), .Y(n1751) );
BUFX3TS U1740 ( .A(n1735), .Y(n1754) );
BUFX3TS U1741 ( .A(n1136), .Y(n1753) );
BUFX3TS U1742 ( .A(n1736), .Y(n1763) );
BUFX3TS U1743 ( .A(n1139), .Y(n1756) );
BUFX3TS U1744 ( .A(n1736), .Y(n1732) );
BUFX3TS U1745 ( .A(n1137), .Y(n1738) );
BUFX3TS U1746 ( .A(n1134), .Y(n1755) );
BUFX3TS U1747 ( .A(n1137), .Y(n1736) );
BUFX3TS U1748 ( .A(n1136), .Y(n1731) );
BUFX3TS U1749 ( .A(n1138), .Y(n1737) );
BUFX3TS U1750 ( .A(n1738), .Y(n1728) );
BUFX3TS U1751 ( .A(n1736), .Y(n1727) );
BUFX3TS U1752 ( .A(n1137), .Y(n1735) );
BUFX3TS U1753 ( .A(n1735), .Y(n1730) );
BUFX3TS U1754 ( .A(n1136), .Y(n1757) );
BUFX3TS U1755 ( .A(n1735), .Y(n1758) );
BUFX3TS U1756 ( .A(n1136), .Y(n1729) );
BUFX3TS U1757 ( .A(n1739), .Y(n1752) );
BUFX3TS U1758 ( .A(n1139), .Y(n1726) );
BUFX3TS U1759 ( .A(n1135), .Y(n1734) );
BUFX3TS U1760 ( .A(n1739), .Y(n1725) );
BUFX3TS U1761 ( .A(n1738), .Y(n1724) );
CLKBUFX2TS U1762 ( .A(n1714), .Y(n1571) );
INVX2TS U1763 ( .A(n1571), .Y(n1556) );
NAND2X1TS U1764 ( .A(DmP_EXP_EWSW[25]), .B(n924), .Y(n1548) );
NOR2X1TS U1765 ( .A(n887), .B(DMP_EXP_EWSW[24]), .Y(n1544) );
OAI22X1TS U1766 ( .A0(n1546), .A1(n1544), .B0(DmP_EXP_EWSW[24]), .B1(n1648),
.Y(n1550) );
AOI22X1TS U1767 ( .A0(DMP_EXP_EWSW[25]), .A1(n1708), .B0(n1548), .B1(n1550),
.Y(n1142) );
NOR2X1TS U1768 ( .A(n889), .B(DMP_EXP_EWSW[26]), .Y(n1143) );
AOI21X1TS U1769 ( .A0(DMP_EXP_EWSW[26]), .A1(n889), .B0(n1143), .Y(n1140) );
XNOR2X1TS U1770 ( .A(n1142), .B(n1140), .Y(n1141) );
OAI22X1TS U1771 ( .A0(n1143), .A1(n1142), .B0(DmP_EXP_EWSW[26]), .B1(n1650),
.Y(n1145) );
XNOR2X1TS U1772 ( .A(DmP_EXP_EWSW[27]), .B(DMP_EXP_EWSW[27]), .Y(n1144) );
XOR2X1TS U1773 ( .A(n1145), .B(n1144), .Y(n1146) );
OAI22X1TS U1774 ( .A0(n1765), .A1(intDX_EWSW[1]), .B0(n1676), .B1(
intDX_EWSW[25]), .Y(n1147) );
AOI221X1TS U1775 ( .A0(n1765), .A1(intDX_EWSW[1]), .B0(intDX_EWSW[25]), .B1(
n1676), .C0(n1147), .Y(n1153) );
AOI221X1TS U1776 ( .A0(n1689), .A1(intDX_EWSW[26]), .B0(intDX_EWSW[27]),
.B1(n1693), .C0(n1148), .Y(n1152) );
OAI22X1TS U1777 ( .A0(n1690), .A1(intDX_EWSW[28]), .B0(n1645), .B1(
intDX_EWSW[29]), .Y(n1149) );
AOI2BB2XLTS U1778 ( .B0(intDX_EWSW[7]), .B1(n1668), .A0N(n1668), .A1N(
intDX_EWSW[7]), .Y(n1150) );
OAI22X1TS U1779 ( .A0(n1692), .A1(intDX_EWSW[30]), .B0(n1678), .B1(
intDX_EWSW[17]), .Y(n1154) );
OAI22X1TS U1780 ( .A0(n1688), .A1(intDX_EWSW[20]), .B0(n1681), .B1(
intDX_EWSW[21]), .Y(n1156) );
OAI22X1TS U1781 ( .A0(n1644), .A1(intDX_EWSW[22]), .B0(n1691), .B1(
intDX_EWSW[23]), .Y(n1157) );
OAI22X1TS U1782 ( .A0(n1635), .A1(intDX_EWSW[24]), .B0(n1679), .B1(
intDX_EWSW[9]), .Y(n1162) );
AOI221X1TS U1783 ( .A0(n1635), .A1(intDX_EWSW[24]), .B0(intDX_EWSW[9]), .B1(
n1679), .C0(n1162), .Y(n1169) );
OAI22X1TS U1784 ( .A0(n1685), .A1(intDX_EWSW[12]), .B0(n1680), .B1(
intDX_EWSW[13]), .Y(n1164) );
OAI22X1TS U1785 ( .A0(n1686), .A1(intDX_EWSW[14]), .B0(n1643), .B1(
intDX_EWSW[15]), .Y(n1165) );
OAI22X1TS U1786 ( .A0(n1687), .A1(intDX_EWSW[16]), .B0(n1642), .B1(
intDX_EWSW[0]), .Y(n1170) );
AOI221X1TS U1787 ( .A0(n1687), .A1(intDX_EWSW[16]), .B0(intDX_EWSW[0]), .B1(
n1642), .C0(n1170), .Y(n1177) );
OAI22X1TS U1788 ( .A0(n1683), .A1(intDX_EWSW[2]), .B0(n1677), .B1(
intDX_EWSW[3]), .Y(n1171) );
OAI22X1TS U1789 ( .A0(n1684), .A1(intDX_EWSW[4]), .B0(n1641), .B1(
intDX_EWSW[5]), .Y(n1172) );
AOI221X1TS U1790 ( .A0(n1684), .A1(intDX_EWSW[4]), .B0(intDX_EWSW[5]), .B1(
n1641), .C0(n1172), .Y(n1175) );
OAI22X1TS U1791 ( .A0(n1682), .A1(intDX_EWSW[8]), .B0(n1667), .B1(
intDX_EWSW[6]), .Y(n1173) );
AOI221X1TS U1792 ( .A0(n1682), .A1(intDX_EWSW[8]), .B0(intDX_EWSW[6]), .B1(
n1667), .C0(n1173), .Y(n1174) );
CLKXOR2X2TS U1793 ( .A(intDY_EWSW[31]), .B(intAS), .Y(n1266) );
AOI21X1TS U1794 ( .A0(n1266), .A1(intDX_EWSW[31]), .B0(n1182), .Y(n1553) );
NAND2X1TS U1795 ( .A(n873), .B(DmP_mant_SFG_SWR[2]), .Y(n1183) );
OAI21X1TS U1796 ( .A0(n873), .A1(DmP_mant_SFG_SWR[2]), .B0(n1183), .Y(n1577)
);
NOR2X2TS U1797 ( .A(n1577), .B(n886), .Y(n1580) );
NOR2BX1TS U1798 ( .AN(n1697), .B(n873), .Y(n1184) );
AOI21X1TS U1799 ( .A0(n873), .A1(DmP_mant_SFG_SWR[3]), .B0(n1184), .Y(n1579)
);
OAI21X1TS U1800 ( .A0(n1580), .A1(DMP_SFG[1]), .B0(n1185), .Y(intadd_50_B_0_) );
INVX2TS U1801 ( .A(n1186), .Y(n1189) );
CLKBUFX2TS U1802 ( .A(n1187), .Y(n1610) );
NAND2X1TS U1803 ( .A(n1507), .B(final_result_ieee[23]), .Y(n1188) );
INVX2TS U1804 ( .A(exp_rslt_NRM2_EW1[1]), .Y(n1191) );
NAND2X1TS U1805 ( .A(n1507), .B(final_result_ieee[24]), .Y(n1190) );
AOI21X1TS U1806 ( .A0(n1201), .A1(n1604), .B0(n1193), .Y(n1596) );
NOR2X4TS U1807 ( .A(n1386), .B(Shift_reg_FLAGS_7[0]), .Y(n1631) );
NAND2X1TS U1808 ( .A(n1240), .B(DmP_mant_SFG_SWR[9]), .Y(n1194) );
AOI21X1TS U1809 ( .A0(n1207), .A1(n1604), .B0(n1196), .Y(n1597) );
NAND2X1TS U1810 ( .A(n1240), .B(DmP_mant_SFG_SWR[8]), .Y(n1197) );
NOR2XLTS U1811 ( .A(n1661), .B(DmP_mant_SFG_SWR[4]), .Y(n1199) );
NOR2X1TS U1812 ( .A(n1199), .B(n1198), .Y(intadd_50_CI) );
CLKXOR2X2TS U1813 ( .A(n1200), .B(DmP_mant_SFG_SWR[10]), .Y(
DmP_mant_SFG_SWR_signed[10]) );
INVX2TS U1814 ( .A(n1201), .Y(n1204) );
AOI22X1TS U1815 ( .A0(Data_array_SWR[12]), .A1(n874), .B0(Data_array_SWR[8]),
.B1(n1390), .Y(n1203) );
AOI22X1TS U1816 ( .A0(Data_array_SWR[4]), .A1(n902), .B0(Data_array_SWR[0]),
.B1(n1208), .Y(n1202) );
OAI211X1TS U1817 ( .A0(n1204), .A1(n882), .B0(n1203), .C0(n1202), .Y(n1613)
);
AOI22X1TS U1818 ( .A0(Data_array_SWR[25]), .A1(n904), .B0(n1401), .B1(n1613),
.Y(n1206) );
NAND2X1TS U1819 ( .A(n1237), .B(DmP_mant_SFG_SWR[25]), .Y(n1205) );
INVX2TS U1820 ( .A(n1207), .Y(n1211) );
AOI22X1TS U1821 ( .A0(Data_array_SWR[13]), .A1(n874), .B0(Data_array_SWR[9]),
.B1(n1390), .Y(n1210) );
AOI22X1TS U1822 ( .A0(Data_array_SWR[5]), .A1(n1085), .B0(Data_array_SWR[1]),
.B1(n1208), .Y(n1209) );
OAI211X1TS U1823 ( .A0(n1211), .A1(n882), .B0(n1210), .C0(n1209), .Y(n1616)
);
AOI22X1TS U1824 ( .A0(Data_array_SWR[24]), .A1(n904), .B0(n1401), .B1(n1616),
.Y(n1612) );
NAND2X1TS U1825 ( .A(n1237), .B(DmP_mant_SFG_SWR[24]), .Y(n1212) );
NAND2X1TS U1826 ( .A(n1237), .B(DmP_mant_SFG_SWR[22]), .Y(n1213) );
NAND2X1TS U1827 ( .A(n1237), .B(DmP_mant_SFG_SWR[23]), .Y(n1215) );
OAI22X1TS U1828 ( .A0(n1220), .A1(n1219), .B0(n1218), .B1(n1217), .Y(n1225)
);
OAI31X1TS U1829 ( .A0(n1225), .A1(n1224), .A2(n1223), .B0(n1576), .Y(n1488)
);
NAND2X1TS U1830 ( .A(n1237), .B(DmP_mant_SFG_SWR[16]), .Y(n1227) );
NAND2X1TS U1831 ( .A(n1237), .B(DmP_mant_SFG_SWR[19]), .Y(n1229) );
NAND2X1TS U1832 ( .A(n1237), .B(DmP_mant_SFG_SWR[20]), .Y(n1231) );
NAND2X1TS U1833 ( .A(n1237), .B(DmP_mant_SFG_SWR[21]), .Y(n1233) );
NAND2X1TS U1834 ( .A(n1237), .B(DmP_mant_SFG_SWR[18]), .Y(n1235) );
NAND2X1TS U1835 ( .A(n1237), .B(DmP_mant_SFG_SWR[17]), .Y(n1238) );
CLKBUFX2TS U1836 ( .A(n1243), .Y(n1274) );
BUFX3TS U1837 ( .A(n1274), .Y(n1505) );
AOI22X1TS U1838 ( .A0(intDX_EWSW[17]), .A1(n1245), .B0(DmP_EXP_EWSW[17]),
.B1(n1505), .Y(n1241) );
BUFX3TS U1839 ( .A(n1554), .Y(n1282) );
AOI22X1TS U1840 ( .A0(intDX_EWSW[0]), .A1(n1245), .B0(DmP_EXP_EWSW[0]), .B1(
n1282), .Y(n1242) );
AOI22X1TS U1841 ( .A0(intDX_EWSW[16]), .A1(n1325), .B0(DmP_EXP_EWSW[16]),
.B1(n1243), .Y(n1244) );
BUFX3TS U1842 ( .A(n1245), .Y(n1325) );
AOI22X1TS U1843 ( .A0(intDX_EWSW[4]), .A1(n1325), .B0(DmP_EXP_EWSW[4]), .B1(
n1282), .Y(n1246) );
AOI22X1TS U1844 ( .A0(intDX_EWSW[6]), .A1(n1325), .B0(DmP_EXP_EWSW[6]), .B1(
n1282), .Y(n1247) );
AOI22X1TS U1845 ( .A0(intDX_EWSW[5]), .A1(n1325), .B0(DmP_EXP_EWSW[5]), .B1(
n1243), .Y(n1248) );
AOI22X1TS U1846 ( .A0(intDX_EWSW[2]), .A1(n1325), .B0(DmP_EXP_EWSW[2]), .B1(
n1282), .Y(n1249) );
AOI22X1TS U1847 ( .A0(intDX_EWSW[1]), .A1(n1325), .B0(DmP_EXP_EWSW[1]), .B1(
n1282), .Y(n1250) );
AOI22X1TS U1848 ( .A0(intDX_EWSW[3]), .A1(n1325), .B0(DmP_EXP_EWSW[3]), .B1(
n1282), .Y(n1251) );
AOI22X1TS U1849 ( .A0(DmP_EXP_EWSW[27]), .A1(n1505), .B0(intDX_EWSW[27]),
.B1(n1325), .Y(n1252) );
AOI22X1TS U1850 ( .A0(intDX_EWSW[7]), .A1(n1263), .B0(DmP_EXP_EWSW[7]), .B1(
n1243), .Y(n1253) );
AOI22X1TS U1851 ( .A0(intDX_EWSW[18]), .A1(n1263), .B0(DmP_EXP_EWSW[18]),
.B1(n1243), .Y(n1254) );
AOI22X1TS U1852 ( .A0(intDX_EWSW[10]), .A1(n1263), .B0(DmP_EXP_EWSW[10]),
.B1(n1282), .Y(n1255) );
AOI22X1TS U1853 ( .A0(intDX_EWSW[14]), .A1(n1263), .B0(DmP_EXP_EWSW[14]),
.B1(n1274), .Y(n1256) );
AOI22X1TS U1854 ( .A0(intDX_EWSW[11]), .A1(n1263), .B0(DmP_EXP_EWSW[11]),
.B1(n1274), .Y(n1257) );
AOI22X1TS U1855 ( .A0(intDX_EWSW[8]), .A1(n1263), .B0(DmP_EXP_EWSW[8]), .B1(
n928), .Y(n1258) );
AOI22X1TS U1856 ( .A0(intDX_EWSW[12]), .A1(n1263), .B0(DmP_EXP_EWSW[12]),
.B1(n1274), .Y(n1259) );
AOI22X1TS U1857 ( .A0(intDX_EWSW[9]), .A1(n1263), .B0(DmP_EXP_EWSW[9]), .B1(
n1243), .Y(n1260) );
AOI22X1TS U1858 ( .A0(intDX_EWSW[13]), .A1(n1263), .B0(DmP_EXP_EWSW[13]),
.B1(n928), .Y(n1262) );
AOI22X1TS U1859 ( .A0(intDX_EWSW[15]), .A1(n1263), .B0(DmP_EXP_EWSW[15]),
.B1(n1505), .Y(n1264) );
INVX2TS U1860 ( .A(n1266), .Y(n1270) );
AOI22X1TS U1861 ( .A0(intDX_EWSW[31]), .A1(n1268), .B0(SIGN_FLAG_EXP), .B1(
n1282), .Y(n1269) );
OAI31X1TS U1862 ( .A0(n1271), .A1(n1270), .A2(n1568), .B0(n1269), .Y(n720)
);
BUFX3TS U1863 ( .A(n1274), .Y(n1310) );
AOI22X1TS U1864 ( .A0(intDX_EWSW[28]), .A1(n1319), .B0(DMP_EXP_EWSW[28]),
.B1(n1310), .Y(n1272) );
AOI22X1TS U1865 ( .A0(intDX_EWSW[1]), .A1(n1324), .B0(DMP_EXP_EWSW[1]), .B1(
n1554), .Y(n1273) );
BUFX3TS U1866 ( .A(n1274), .Y(n1297) );
AOI22X1TS U1867 ( .A0(intDX_EWSW[4]), .A1(n1302), .B0(DMP_EXP_EWSW[4]), .B1(
n1297), .Y(n1275) );
AOI22X1TS U1868 ( .A0(intDX_EWSW[5]), .A1(n1324), .B0(DMP_EXP_EWSW[5]), .B1(
n1297), .Y(n1276) );
AOI22X1TS U1869 ( .A0(intDX_EWSW[6]), .A1(n1324), .B0(DMP_EXP_EWSW[6]), .B1(
n1297), .Y(n1277) );
AOI22X1TS U1870 ( .A0(intDX_EWSW[2]), .A1(n1324), .B0(DMP_EXP_EWSW[2]), .B1(
n1554), .Y(n1278) );
AOI22X1TS U1871 ( .A0(intDX_EWSW[29]), .A1(n1319), .B0(DMP_EXP_EWSW[29]),
.B1(n1282), .Y(n1280) );
AOI22X1TS U1872 ( .A0(intDX_EWSW[18]), .A1(n1302), .B0(DMP_EXP_EWSW[18]),
.B1(n1310), .Y(n1281) );
AOI22X1TS U1873 ( .A0(intDX_EWSW[30]), .A1(n1319), .B0(DMP_EXP_EWSW[30]),
.B1(n1282), .Y(n1283) );
CLKBUFX2TS U1874 ( .A(n1284), .Y(n1324) );
AOI22X1TS U1875 ( .A0(DMP_EXP_EWSW[27]), .A1(n1505), .B0(intDX_EWSW[27]),
.B1(n1324), .Y(n1285) );
AOI22X1TS U1876 ( .A0(DMP_EXP_EWSW[23]), .A1(n1505), .B0(intDX_EWSW[23]),
.B1(n1319), .Y(n1286) );
AOI22X1TS U1877 ( .A0(intDX_EWSW[14]), .A1(n1302), .B0(DMP_EXP_EWSW[14]),
.B1(n1310), .Y(n1288) );
AOI22X1TS U1878 ( .A0(intDX_EWSW[17]), .A1(n1302), .B0(DMP_EXP_EWSW[17]),
.B1(n1310), .Y(n1289) );
AOI22X1TS U1879 ( .A0(intDX_EWSW[12]), .A1(n1302), .B0(DMP_EXP_EWSW[12]),
.B1(n1297), .Y(n1290) );
AOI22X1TS U1880 ( .A0(intDX_EWSW[8]), .A1(n1284), .B0(DMP_EXP_EWSW[8]), .B1(
n1297), .Y(n1291) );
AOI22X1TS U1881 ( .A0(intDX_EWSW[11]), .A1(n1302), .B0(DMP_EXP_EWSW[11]),
.B1(n1310), .Y(n1292) );
AOI22X1TS U1882 ( .A0(intDX_EWSW[15]), .A1(n1302), .B0(DMP_EXP_EWSW[15]),
.B1(n1297), .Y(n1293) );
AOI22X1TS U1883 ( .A0(intDX_EWSW[13]), .A1(n1302), .B0(DMP_EXP_EWSW[13]),
.B1(n1297), .Y(n1294) );
AOI22X1TS U1884 ( .A0(intDX_EWSW[7]), .A1(n1284), .B0(DMP_EXP_EWSW[7]), .B1(
n1297), .Y(n1295) );
AOI22X1TS U1885 ( .A0(intDX_EWSW[9]), .A1(n1284), .B0(DMP_EXP_EWSW[9]), .B1(
n1297), .Y(n1296) );
AOI22X1TS U1886 ( .A0(intDX_EWSW[10]), .A1(n1284), .B0(DMP_EXP_EWSW[10]),
.B1(n1297), .Y(n1298) );
AOI22X1TS U1887 ( .A0(intDX_EWSW[0]), .A1(n1319), .B0(DMP_EXP_EWSW[0]), .B1(
n1554), .Y(n1299) );
AOI22X1TS U1888 ( .A0(intDX_EWSW[16]), .A1(n1302), .B0(DMP_EXP_EWSW[16]),
.B1(n1310), .Y(n1300) );
AOI22X1TS U1889 ( .A0(intDX_EWSW[19]), .A1(n1302), .B0(DMP_EXP_EWSW[19]),
.B1(n1310), .Y(n1303) );
AOI22X1TS U1890 ( .A0(intDX_EWSW[22]), .A1(n1319), .B0(DMP_EXP_EWSW[22]),
.B1(n1310), .Y(n1304) );
AOI22X1TS U1891 ( .A0(intDX_EWSW[20]), .A1(n1319), .B0(DMP_EXP_EWSW[20]),
.B1(n1310), .Y(n1305) );
OAI22X1TS U1892 ( .A0(n1306), .A1(n909), .B0(n1702), .B1(n1383), .Y(n1307)
);
AOI21X1TS U1893 ( .A0(n1369), .A1(Data_array_SWR[18]), .B0(n1307), .Y(n1308)
);
AOI22X1TS U1894 ( .A0(intDX_EWSW[21]), .A1(n1319), .B0(DMP_EXP_EWSW[21]),
.B1(n1310), .Y(n1311) );
AOI22X1TS U1895 ( .A0(n898), .A1(Raw_mant_NRM_SWR[24]), .B0(
DmP_mant_SHT1_SW[0]), .B1(n1313), .Y(n1318) );
AOI22X1TS U1896 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n890), .B0(n1527), .B1(
DmP_mant_SHT1_SW[2]), .Y(n1315) );
AOI22X1TS U1897 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n913), .B0(n917), .B1(
DmP_mant_SHT1_SW[1]), .Y(n1314) );
NAND2X1TS U1898 ( .A(n1315), .B(n1314), .Y(n1344) );
AOI22X1TS U1899 ( .A0(n1359), .A1(Data_array_SWR[1]), .B0(n1333), .B1(n1344),
.Y(n1317) );
NAND2X1TS U1900 ( .A(n1353), .B(Raw_mant_NRM_SWR[23]), .Y(n1316) );
AOI22X1TS U1901 ( .A0(intDX_EWSW[20]), .A1(n1245), .B0(DmP_EXP_EWSW[20]),
.B1(n1505), .Y(n1320) );
AOI22X1TS U1902 ( .A0(intDX_EWSW[21]), .A1(n1245), .B0(DmP_EXP_EWSW[21]),
.B1(n1505), .Y(n1321) );
AOI22X1TS U1903 ( .A0(intDX_EWSW[22]), .A1(n1245), .B0(DmP_EXP_EWSW[22]),
.B1(n1505), .Y(n1322) );
AOI22X1TS U1904 ( .A0(intDX_EWSW[19]), .A1(n1245), .B0(DmP_EXP_EWSW[19]),
.B1(n1505), .Y(n1323) );
AOI222X1TS U1905 ( .A0(n1325), .A1(intDX_EWSW[23]), .B0(DmP_EXP_EWSW[23]),
.B1(n1554), .C0(intDY_EWSW[23]), .C1(n1324), .Y(n1326) );
INVX2TS U1906 ( .A(n1326), .Y(n564) );
AOI22X1TS U1907 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n890), .B0(n1527), .B1(
DmP_mant_SHT1_SW[5]), .Y(n1328) );
AOI22X1TS U1908 ( .A0(Raw_mant_NRM_SWR[19]), .A1(n913), .B0(n919), .B1(
DmP_mant_SHT1_SW[4]), .Y(n1327) );
NAND2X1TS U1909 ( .A(n1328), .B(n1327), .Y(n1336) );
AOI22X1TS U1910 ( .A0(n1359), .A1(Data_array_SWR[4]), .B0(n1333), .B1(n1336),
.Y(n1330) );
NAND2X1TS U1911 ( .A(Raw_mant_NRM_SWR[20]), .B(n1353), .Y(n1329) );
AOI22X1TS U1912 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n890), .B0(n1527), .B1(
DmP_mant_SHT1_SW[6]), .Y(n1332) );
AOI22X1TS U1913 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n913), .B0(n917), .B1(
DmP_mant_SHT1_SW[5]), .Y(n1331) );
NAND2X1TS U1914 ( .A(n1332), .B(n1331), .Y(n1348) );
AOI22X1TS U1915 ( .A0(n1359), .A1(Data_array_SWR[5]), .B0(n1333), .B1(n1348),
.Y(n1335) );
NAND2X1TS U1916 ( .A(Raw_mant_NRM_SWR[19]), .B(n1353), .Y(n1334) );
AOI22X1TS U1917 ( .A0(n1369), .A1(Data_array_SWR[6]), .B0(n879), .B1(n1336),
.Y(n1338) );
NAND2X1TS U1918 ( .A(Raw_mant_NRM_SWR[16]), .B(n892), .Y(n1337) );
AOI22X1TS U1919 ( .A0(n1359), .A1(Data_array_SWR[2]), .B0(n879), .B1(n1340),
.Y(n1342) );
NAND2X1TS U1920 ( .A(Raw_mant_NRM_SWR[20]), .B(n892), .Y(n1341) );
AOI22X1TS U1921 ( .A0(n1359), .A1(Data_array_SWR[3]), .B0(n879), .B1(n1344),
.Y(n1346) );
NAND2X1TS U1922 ( .A(Raw_mant_NRM_SWR[19]), .B(n892), .Y(n1345) );
AOI22X1TS U1923 ( .A0(n1359), .A1(Data_array_SWR[7]), .B0(n879), .B1(n1348),
.Y(n1350) );
NAND2X1TS U1924 ( .A(Raw_mant_NRM_SWR[15]), .B(n892), .Y(n1349) );
AOI22X1TS U1925 ( .A0(n1369), .A1(Data_array_SWR[15]), .B0(
Raw_mant_NRM_SWR[7]), .B1(n1368), .Y(n1352) );
AOI2BB2X1TS U1926 ( .B0(Raw_mant_NRM_SWR[9]), .B1(n1353), .A0N(n1373), .A1N(
n907), .Y(n1351) );
AOI22X1TS U1927 ( .A0(n1113), .A1(Data_array_SWR[9]), .B0(
Raw_mant_NRM_SWR[13]), .B1(n892), .Y(n1355) );
AOI2BB2X1TS U1928 ( .B0(Raw_mant_NRM_SWR[15]), .B1(n1353), .A0N(n1363),
.A1N(n907), .Y(n1354) );
OAI211X1TS U1929 ( .A0(n1356), .A1(n910), .B0(n1355), .C0(n1354), .Y(n780)
);
AOI22X1TS U1930 ( .A0(n1369), .A1(Data_array_SWR[19]), .B0(
Raw_mant_NRM_SWR[3]), .B1(n1368), .Y(n1358) );
OA22X1TS U1931 ( .A0(n1654), .A1(n1383), .B0(n1376), .B1(n907), .Y(n1357) );
AOI22X1TS U1932 ( .A0(n1359), .A1(Data_array_SWR[11]), .B0(
Raw_mant_NRM_SWR[11]), .B1(n1368), .Y(n1362) );
OA22X1TS U1933 ( .A0(n1704), .A1(n1383), .B0(n1367), .B1(n908), .Y(n1361) );
AOI22X1TS U1934 ( .A0(n1369), .A1(Data_array_SWR[13]), .B0(
Raw_mant_NRM_SWR[9]), .B1(n1368), .Y(n1366) );
OA22X1TS U1935 ( .A0(n1633), .A1(n1383), .B0(n1364), .B1(n908), .Y(n1365) );
AOI22X1TS U1936 ( .A0(n1369), .A1(Data_array_SWR[17]), .B0(
Raw_mant_NRM_SWR[5]), .B1(n892), .Y(n1372) );
OA22X1TS U1937 ( .A0(n1655), .A1(n1383), .B0(n1370), .B1(n908), .Y(n1371) );
AOI22X1TS U1938 ( .A0(n919), .A1(DmP_mant_SHT1_SW[21]), .B0(n1527), .B1(
DmP_mant_SHT1_SW[22]), .Y(n1374) );
AOI21X1TS U1939 ( .A0(Raw_mant_NRM_SWR[2]), .A1(n898), .B0(n1375), .Y(n1526)
);
OAI22X1TS U1940 ( .A0(n1376), .A1(n909), .B0(n1647), .B1(n1383), .Y(n1377)
);
AOI21X1TS U1941 ( .A0(n1113), .A1(Data_array_SWR[21]), .B0(n1377), .Y(n1378)
);
OAI22X1TS U1942 ( .A0(n1380), .A1(n908), .B0(n1379), .B1(n909), .Y(n1381) );
AOI21X1TS U1943 ( .A0(n1113), .A1(Data_array_SWR[22]), .B0(n1381), .Y(n1382)
);
OAI2BB2XLTS U1944 ( .B0(n1384), .B1(n1501), .A0N(final_result_ieee[31]),
.A1N(n1507), .Y(n543) );
AOI32X4TS U1945 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .A2(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(n1385), .B1(n1669), .Y(n1508)
);
MXI2X1TS U1946 ( .A(n989), .B(n1386), .S0(n1508), .Y(n865) );
BUFX3TS U1947 ( .A(n1631), .Y(n1403) );
AOI22X1TS U1948 ( .A0(Data_array_SWR[23]), .A1(n901), .B0(Data_array_SWR[19]), .B1(n902), .Y(n1399) );
AOI22X1TS U1949 ( .A0(Data_array_SWR[10]), .A1(n899), .B0(Data_array_SWR[15]), .B1(n903), .Y(n1388) );
OAI221X1TS U1950 ( .A0(n906), .A1(n1399), .B0(n1617), .B1(n1400), .C0(n1388),
.Y(n1594) );
AOI22X1TS U1951 ( .A0(Data_array_SWR[22]), .A1(n901), .B0(Data_array_SWR[18]), .B1(n902), .Y(n1396) );
AOI22X1TS U1952 ( .A0(Data_array_SWR[14]), .A1(n903), .B0(Data_array_SWR[11]), .B1(n899), .Y(n1389) );
OAI221X1TS U1953 ( .A0(n1401), .A1(n1396), .B0(n1617), .B1(n1397), .C0(n1389), .Y(n1592) );
AOI222X1TS U1954 ( .A0(Data_array_SWR[21]), .A1(n901), .B0(
Data_array_SWR[17]), .B1(n902), .C0(Data_array_SWR[25]), .C1(n876),
.Y(n1393) );
AOI222X1TS U1955 ( .A0(Data_array_SWR[24]), .A1(n874), .B0(
Data_array_SWR[20]), .B1(n1390), .C0(Data_array_SWR[16]), .C1(n1085),
.Y(n1394) );
AOI22X1TS U1956 ( .A0(Data_array_SWR[12]), .A1(n899), .B0(Data_array_SWR[13]), .B1(n903), .Y(n1391) );
OAI221X1TS U1957 ( .A0(n906), .A1(n1393), .B0(n1617), .B1(n1394), .C0(n1391),
.Y(n1590) );
AOI22X1TS U1958 ( .A0(Data_array_SWR[12]), .A1(n903), .B0(Data_array_SWR[13]), .B1(n899), .Y(n1392) );
AOI22X1TS U1959 ( .A0(Data_array_SWR[14]), .A1(n899), .B0(Data_array_SWR[11]), .B1(n903), .Y(n1395) );
OAI221X1TS U1960 ( .A0(n1401), .A1(n1397), .B0(n905), .B1(n1396), .C0(n1395),
.Y(n1591) );
AOI22X1TS U1961 ( .A0(Data_array_SWR[10]), .A1(n903), .B0(Data_array_SWR[15]), .B1(n899), .Y(n1398) );
OAI221X1TS U1962 ( .A0(n906), .A1(n1400), .B0(n1617), .B1(n1399), .C0(n1398),
.Y(n1593) );
CLKBUFX2TS U1963 ( .A(n1631), .Y(n1624) );
AFHCINX2TS U1964 ( .CIN(n1404), .B(n1405), .A(DMP_SFG[19]), .S(n1406), .CO(
n1424) );
AOI21X1TS U1965 ( .A0(n1456), .A1(n1408), .B0(n1407), .Y(n1412) );
NAND2X1TS U1966 ( .A(n1410), .B(n1409), .Y(n1411) );
XOR2X1TS U1967 ( .A(n1412), .B(n1411), .Y(n1413) );
INVX2TS U1968 ( .A(n1414), .Y(n1417) );
AOI21X1TS U1969 ( .A0(n1456), .A1(n1417), .B0(n1416), .Y(n1422) );
NAND2X1TS U1970 ( .A(n1420), .B(n1419), .Y(n1421) );
XOR2X1TS U1971 ( .A(n1422), .B(n1421), .Y(n1423) );
AFHCONX2TS U1972 ( .A(DMP_SFG[20]), .B(n1425), .CI(n1424), .CON(n1427), .S(
n1426) );
AFHCONX2TS U1973 ( .A(DMP_SFG[22]), .B(n1431), .CI(n1430), .CON(n988), .S(
n1432) );
INVX2TS U1974 ( .A(n1433), .Y(n1436) );
AOI21X1TS U1975 ( .A0(n1456), .A1(n1436), .B0(n1435), .Y(n1441) );
NAND2X1TS U1976 ( .A(n1439), .B(n1438), .Y(n1440) );
XOR2X1TS U1977 ( .A(n1441), .B(n1440), .Y(n1442) );
AOI21X1TS U1978 ( .A0(n1456), .A1(n1454), .B0(n1443), .Y(n1447) );
NAND2X1TS U1979 ( .A(n1445), .B(n1444), .Y(n1446) );
XOR2X1TS U1980 ( .A(n1447), .B(n1446), .Y(n1448) );
NAND2X1TS U1981 ( .A(n1454), .B(n1453), .Y(n1455) );
XNOR2X1TS U1982 ( .A(n1456), .B(n1455), .Y(n1457) );
INVX4TS U1983 ( .A(n989), .Y(n1486) );
INVX2TS U1984 ( .A(intadd_50_B_2_), .Y(n1468) );
INVX2TS U1985 ( .A(intadd_50_B_1_), .Y(n1466) );
INVX2TS U1986 ( .A(intadd_50_CI), .Y(n1464) );
OAI2BB1X1TS U1987 ( .A0N(n1466), .A1N(DMP_SFG[3]), .B0(n1465), .Y(n1467) );
AOI222X1TS U1988 ( .A0(n1468), .A1(DMP_SFG[4]), .B0(n1468), .B1(n1467), .C0(
DMP_SFG[4]), .C1(n1467), .Y(n1470) );
MXI2X2TS U1989 ( .A(n1695), .B(DmP_mant_SFG_SWR[7]), .S0(n873), .Y(n1585) );
XOR2X1TS U1990 ( .A(DMP_SFG[9]), .B(n1471), .Y(n1472) );
XOR2X1TS U1991 ( .A(DmP_mant_SFG_SWR_signed[11]), .B(n1472), .Y(n1473) );
MXI2X1TS U1992 ( .A(DmP_mant_SFG_SWR[1]), .B(n923), .S0(n873), .Y(n1485) );
MXI2X1TS U1993 ( .A(n1709), .B(n1485), .S0(n1486), .Y(n541) );
MXI2X1TS U1994 ( .A(DmP_mant_SFG_SWR[0]), .B(n922), .S0(n1387), .Y(n1487) );
MXI2X1TS U1995 ( .A(n1639), .B(n1487), .S0(n1486), .Y(n542) );
OAI2BB1X1TS U1996 ( .A0N(LZD_output_NRM2_EW[4]), .A1N(n1575), .B0(n1488),
.Y(n512) );
AOI22X1TS U1997 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n1491), .B0(n1490), .B1(
Raw_mant_NRM_SWR[5]), .Y(n1493) );
OAI21X1TS U1998 ( .A0(n1497), .A1(n1496), .B0(n1576), .Y(n1538) );
OAI2BB1X1TS U1999 ( .A0N(LZD_output_NRM2_EW[2]), .A1N(n1575), .B0(n1538),
.Y(n514) );
OA21XLTS U2000 ( .A0(Shift_reg_FLAGS_7[0]), .A1(overflow_flag), .B0(n1501),
.Y(n558) );
AOI22X1TS U2001 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n1503), .B1(n1640), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
NAND2X1TS U2002 ( .A(n1503), .B(n1502), .Y(n871) );
INVX2TS U2003 ( .A(n1508), .Y(n1506) );
AOI22X1TS U2004 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(n1504), .B0(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(n1640), .Y(n1509) );
BUFX3TS U2005 ( .A(n1714), .Y(n1570) );
AOI22X1TS U2006 ( .A0(n1508), .A1(n1505), .B0(n1570), .B1(n1506), .Y(n868)
);
AOI22X1TS U2007 ( .A0(n1508), .A1(n1570), .B0(n895), .B1(n1506), .Y(n867) );
AOI22X1TS U2008 ( .A0(n1508), .A1(n989), .B0(n914), .B1(n1506), .Y(n864) );
AOI22X1TS U2009 ( .A0(n1508), .A1(n914), .B0(n1507), .B1(n1506), .Y(n863) );
INVX2TS U2010 ( .A(n1514), .Y(n1510) );
BUFX3TS U2011 ( .A(n1514), .Y(n1520) );
INVX2TS U2012 ( .A(n1524), .Y(n1511) );
BUFX3TS U2013 ( .A(n1514), .Y(n1513) );
BUFX3TS U2014 ( .A(n1514), .Y(n1517) );
BUFX3TS U2015 ( .A(n1517), .Y(n1512) );
INVX2TS U2016 ( .A(n1524), .Y(n1523) );
INVX2TS U2017 ( .A(n1517), .Y(n1515) );
BUFX3TS U2018 ( .A(n1514), .Y(n1521) );
INVX2TS U2019 ( .A(n1517), .Y(n1516) );
BUFX3TS U2020 ( .A(n1514), .Y(n1519) );
INVX2TS U2021 ( .A(n1517), .Y(n1518) );
INVX2TS U2022 ( .A(n1524), .Y(n1522) );
OAI222X1TS U2023 ( .A0(n1703), .A1(n1540), .B0(n911), .B1(n1526), .C0(n908),
.C1(n1525), .Y(n794) );
AOI22X1TS U2024 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n890), .B0(n1527), .B1(
DmP_mant_SHT1_SW[13]), .Y(n1528) );
AOI21X1TS U2025 ( .A0(n918), .A1(DmP_mant_SHT1_SW[12]), .B0(n1529), .Y(n1535) );
AOI22X1TS U2026 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n1531), .B0(n1313), .B1(
DmP_mant_SHT1_SW[11]), .Y(n1532) );
AOI21X1TS U2027 ( .A0(n919), .A1(DmP_mant_SHT1_SW[10]), .B0(n1534), .Y(n1536) );
NAND2X1TS U2028 ( .A(n1539), .B(n1538), .Y(n770) );
AOI21X1TS U2029 ( .A0(busy), .A1(Shift_amount_SHT1_EWR[3]), .B0(n1576), .Y(
n1541) );
OAI22X1TS U2030 ( .A0(n1542), .A1(n1541), .B0(n1540), .B1(n1652), .Y(n769)
);
INVX2TS U2031 ( .A(n1570), .Y(n1572) );
AOI21X1TS U2032 ( .A0(DMP_EXP_EWSW[23]), .A1(n925), .B0(n1546), .Y(n1543) );
INVX2TS U2033 ( .A(n1571), .Y(n1552) );
AOI21X1TS U2034 ( .A0(DMP_EXP_EWSW[24]), .A1(n887), .B0(n1544), .Y(n1545) );
XNOR2X1TS U2035 ( .A(n1546), .B(n1545), .Y(n1547) );
XNOR2X1TS U2036 ( .A(n1550), .B(n1549), .Y(n1551) );
OAI222X1TS U2037 ( .A0(n1566), .A1(n1707), .B0(n1648), .B1(n1567), .C0(n1635), .C1(n1568), .Y(n729) );
OAI222X1TS U2038 ( .A0(n1566), .A1(n1649), .B0(n924), .B1(n1567), .C0(n1676),
.C1(n1568), .Y(n728) );
OAI222X1TS U2039 ( .A0(n1566), .A1(n1712), .B0(n1650), .B1(n1567), .C0(n1689), .C1(n1568), .Y(n727) );
INVX2TS U2040 ( .A(n1620), .Y(n1562) );
BUFX3TS U2041 ( .A(n1714), .Y(n1557) );
BUFX3TS U2042 ( .A(n895), .Y(n1558) );
BUFX3TS U2043 ( .A(n1631), .Y(n1615) );
INVX2TS U2044 ( .A(n1620), .Y(n1574) );
INVX2TS U2045 ( .A(n1571), .Y(n1559) );
BUFX3TS U2046 ( .A(n1714), .Y(n1560) );
INVX2TS U2047 ( .A(n895), .Y(n1561) );
BUFX3TS U2048 ( .A(n1714), .Y(n1573) );
INVX2TS U2049 ( .A(n989), .Y(n1584) );
BUFX3TS U2050 ( .A(n989), .Y(n1582) );
INVX2TS U2051 ( .A(n1570), .Y(n1563) );
BUFX3TS U2052 ( .A(n1571), .Y(n1564) );
BUFX3TS U2053 ( .A(n1570), .Y(n1565) );
OAI222X1TS U2054 ( .A0(n1568), .A1(n1707), .B0(n887), .B1(n1567), .C0(n1635),
.C1(n1566), .Y(n563) );
OAI222X1TS U2055 ( .A0(n1568), .A1(n1649), .B0(n1708), .B1(n1567), .C0(n1676), .C1(n1566), .Y(n562) );
OAI222X1TS U2056 ( .A0(n1568), .A1(n1712), .B0(n889), .B1(n1567), .C0(n1689),
.C1(n1566), .Y(n561) );
OAI2BB1X1TS U2057 ( .A0N(underflow_flag), .A1N(n1610), .B0(n1569), .Y(n559)
);
AOI22X1TS U2058 ( .A0(n1588), .A1(n1578), .B0(n1634), .B1(n1582), .Y(n540)
);
XOR2X1TS U2059 ( .A(n1579), .B(DMP_SFG[1]), .Y(n1581) );
XNOR2X1TS U2060 ( .A(n1581), .B(n1580), .Y(n1583) );
AOI22X1TS U2061 ( .A0(n1588), .A1(n1583), .B0(n1647), .B1(n1582), .Y(n539)
);
AOI22X1TS U2062 ( .A0(n1588), .A1(intadd_50_SUM_1_), .B0(n1654), .B1(n989),
.Y(n537) );
AOI22X1TS U2063 ( .A0(n1588), .A1(intadd_50_SUM_2_), .B0(n1702), .B1(n989),
.Y(n536) );
XOR2X1TS U2064 ( .A(n1585), .B(DMP_SFG[5]), .Y(n1586) );
XOR2X1TS U2065 ( .A(intadd_50_n1), .B(n1586), .Y(n1587) );
AOI22X1TS U2066 ( .A0(n1588), .A1(n1587), .B0(n1655), .B1(n989), .Y(n535) );
OAI2BB2XLTS U2067 ( .B0(n1596), .B1(n916), .A0N(final_result_ieee[7]), .A1N(
n1701), .Y(n505) );
OAI2BB2XLTS U2068 ( .B0(n1597), .B1(n916), .A0N(final_result_ieee[6]), .A1N(
n1701), .Y(n503) );
OAI2BB2XLTS U2069 ( .B0(n1630), .B1(n1611), .A0N(final_result_ieee[5]),
.A1N(n1607), .Y(n501) );
OAI2BB2XLTS U2070 ( .B0(n1628), .B1(n916), .A0N(final_result_ieee[4]), .A1N(
n1607), .Y(n499) );
OAI2BB2XLTS U2071 ( .B0(n1626), .B1(n916), .A0N(final_result_ieee[3]), .A1N(
n1607), .Y(n497) );
OAI2BB2XLTS U2072 ( .B0(n1623), .B1(n916), .A0N(final_result_ieee[2]), .A1N(
n1607), .Y(n495) );
AOI22X1TS U2073 ( .A0(Data_array_SWR[22]), .A1(n899), .B0(n888), .B1(n1608),
.Y(n1621) );
OAI2BB2XLTS U2074 ( .B0(n1621), .B1(n916), .A0N(final_result_ieee[1]), .A1N(
n1701), .Y(n493) );
AOI22X1TS U2075 ( .A0(Data_array_SWR[23]), .A1(n900), .B0(n905), .B1(n1609),
.Y(n1619) );
OAI2BB2XLTS U2076 ( .B0(n1619), .B1(n916), .A0N(final_result_ieee[0]), .A1N(
n1701), .Y(n492) );
OAI2BB2XLTS U2077 ( .B0(n1612), .B1(n916), .A0N(final_result_ieee[22]),
.A1N(n1610), .Y(n489) );
AOI22X1TS U2078 ( .A0(Data_array_SWR[25]), .A1(n900), .B0(n1617), .B1(n1613),
.Y(n1614) );
AOI22X1TS U2079 ( .A0(n1615), .A1(n1614), .B0(n922), .B1(n1629), .Y(n488) );
AOI22X1TS U2080 ( .A0(Data_array_SWR[24]), .A1(n900), .B0(n1617), .B1(n1616),
.Y(n1618) );
AOI22X1TS U2081 ( .A0(n1620), .A1(n1618), .B0(n923), .B1(n1629), .Y(n487) );
AOI22X1TS U2082 ( .A0(n1620), .A1(n1619), .B0(n1696), .B1(n1629), .Y(n486)
);
AOI22X1TS U2083 ( .A0(n1631), .A1(n1621), .B0(n1697), .B1(n1629), .Y(n485)
);
AOI22X1TS U2084 ( .A0(n1624), .A1(n1623), .B0(n1622), .B1(n1629), .Y(n484)
);
AOI22X1TS U2085 ( .A0(n1631), .A1(n1626), .B0(n1625), .B1(n1629), .Y(n483)
);
AOI22X1TS U2086 ( .A0(n1631), .A1(n1628), .B0(n1627), .B1(n1629), .Y(n482)
);
AOI22X1TS U2087 ( .A0(n1631), .A1(n1630), .B0(n1695), .B1(n1629), .Y(n481)
);
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpadd_approx_syn_constraints_clk10.tcl_GeArN16R4P4_syn.sdf");
endmodule
|
/*
Copyright (c) 2014-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* FPGA top-level module
*/
module fpga (
/*
* Clock: 100MHz
* Reset: Push button, active low
*/
input wire clk,
input wire reset_n,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [7:0] sw,
output wire [7:0] led,
/*
* I2C
*/
inout wire i2c_scl,
inout wire i2c_sda,
/*
* Ethernet: 1000BASE-T RGMII
*/
input wire phy_rx_clk,
input wire [3:0] phy_rxd,
input wire phy_rx_ctl,
output wire phy_tx_clk,
output wire [3:0] phy_txd,
output wire phy_tx_ctl,
output wire phy_reset_n,
input wire phy_int_n,
input wire phy_pme_n,
/*
* UART: 115200 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd
);
// Clock and reset
wire clk_ibufg;
wire clk_bufg;
wire clk_mmcm_out;
// Internal 125 MHz clock
wire clk_int;
wire rst_int;
wire mmcm_rst = ~reset_n;
wire mmcm_locked;
wire mmcm_clkfb;
IBUFG
clk_ibufg_inst(
.I(clk),
.O(clk_ibufg)
);
wire clk90_mmcm_out;
wire clk90_int;
wire clk_200_mmcm_out;
wire clk_200_int;
// MMCM instance
// 100 MHz in, 125 MHz out
// PFD range: 10 MHz to 550 MHz
// VCO range: 600 MHz to 1200 MHz
// M = 10, D = 1 sets Fvco = 1000 MHz (in range)
// Divide by 8 to get output frequency of 125 MHz
// Need two 125 MHz outputs with 90 degree offset
// Also need 200 MHz out for IODELAY
// 1000 / 5 = 200 MHz
MMCME2_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKOUT0_DIVIDE_F(8),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0),
.CLKOUT1_DIVIDE(8),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(90),
.CLKOUT2_DIVIDE(5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(0),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT6_PHASE(0),
.CLKFBOUT_MULT_F(10),
.CLKFBOUT_PHASE(0),
.DIVCLK_DIVIDE(1),
.REF_JITTER1(0.010),
.CLKIN1_PERIOD(10.0),
.STARTUP_WAIT("FALSE"),
.CLKOUT4_CASCADE("FALSE")
)
clk_mmcm_inst (
.CLKIN1(clk_ibufg),
.CLKFBIN(mmcm_clkfb),
.RST(mmcm_rst),
.PWRDWN(1'b0),
.CLKOUT0(clk_mmcm_out),
.CLKOUT0B(),
.CLKOUT1(clk90_mmcm_out),
.CLKOUT1B(),
.CLKOUT2(clk_200_mmcm_out),
.CLKOUT2B(),
.CLKOUT3(),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.CLKFBOUT(mmcm_clkfb),
.CLKFBOUTB(),
.LOCKED(mmcm_locked)
);
BUFG
clk_bufg_inst (
.I(clk_mmcm_out),
.O(clk_int)
);
BUFG
clk90_bufg_inst (
.I(clk90_mmcm_out),
.O(clk90_int)
);
BUFG
clk_200_bufg_inst (
.I(clk_200_mmcm_out),
.O(clk_200_int)
);
sync_reset #(
.N(4)
)
sync_reset_inst (
.clk(clk_int),
.rst(~mmcm_locked),
.out(rst_int)
);
// GPIO
wire btnu_int;
wire btnl_int;
wire btnd_int;
wire btnr_int;
wire btnc_int;
wire [7:0] sw_int;
debounce_switch #(
.WIDTH(13),
.N(4),
.RATE(125000)
)
debounce_switch_inst (
.clk(clk_int),
.rst(rst_int),
.in({btnu,
btnl,
btnd,
btnr,
btnc,
sw}),
.out({btnu_int,
btnl_int,
btnd_int,
btnr_int,
btnc_int,
sw_int})
);
sync_signal #(
.WIDTH(1),
.N(2)
)
sync_signal_inst (
.clk(clk_int),
.in({uart_rxd}),
.out({uart_rxd_int})
);
assign i2c_scl_i = i2c_scl;
assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o;
assign i2c_sda_i = i2c_sda;
assign i2c_sda = i2c_sda_t ? 1'bz : i2c_sda_o;
// IODELAY elements for RGMII interface to PHY
wire [3:0] phy_rxd_delay;
wire phy_rx_ctl_delay;
IDELAYCTRL
idelayctrl_inst
(
.REFCLK(clk_200_int),
.RST(rst_int),
.RDY()
);
IDELAYE2 #(
.IDELAY_TYPE("FIXED")
)
phy_rxd_idelay_0
(
.IDATAIN(phy_rxd[0]),
.DATAOUT(phy_rxd_delay[0]),
.DATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.CINVCTRL(1'b0),
.CNTVALUEIN(5'd0),
.CNTVALUEOUT(),
.LD(1'b0),
.LDPIPEEN(1'b0),
.REGRST(1'b0)
);
IDELAYE2 #(
.IDELAY_TYPE("FIXED")
)
phy_rxd_idelay_1
(
.IDATAIN(phy_rxd[1]),
.DATAOUT(phy_rxd_delay[1]),
.DATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.CINVCTRL(1'b0),
.CNTVALUEIN(5'd0),
.CNTVALUEOUT(),
.LD(1'b0),
.LDPIPEEN(1'b0),
.REGRST(1'b0)
);
IDELAYE2 #(
.IDELAY_TYPE("FIXED")
)
phy_rxd_idelay_2
(
.IDATAIN(phy_rxd[2]),
.DATAOUT(phy_rxd_delay[2]),
.DATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.CINVCTRL(1'b0),
.CNTVALUEIN(5'd0),
.CNTVALUEOUT(),
.LD(1'b0),
.LDPIPEEN(1'b0),
.REGRST(1'b0)
);
IDELAYE2 #(
.IDELAY_TYPE("FIXED")
)
phy_rxd_idelay_3
(
.IDATAIN(phy_rxd[3]),
.DATAOUT(phy_rxd_delay[3]),
.DATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.CINVCTRL(1'b0),
.CNTVALUEIN(5'd0),
.CNTVALUEOUT(),
.LD(1'b0),
.LDPIPEEN(1'b0),
.REGRST(1'b0)
);
IDELAYE2 #(
.IDELAY_TYPE("FIXED")
)
phy_rx_ctl_idelay
(
.IDATAIN(phy_rx_ctl),
.DATAOUT(phy_rx_ctl_delay),
.DATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.CINVCTRL(1'b0),
.CNTVALUEIN(5'd0),
.CNTVALUEOUT(),
.LD(1'b0),
.LDPIPEEN(1'b0),
.REGRST(1'b0)
);
fpga_core
core_inst (
/*
* Clock: 125MHz
* Synchronous reset
*/
.clk(clk_int),
.clk90(clk90_int),
.rst(rst_int),
/*
* GPIO
*/
.btnu(btnu_int),
.btnl(btnl_int),
.btnd(btnd_int),
.btnr(btnr_int),
.btnc(btnc_int),
.sw(sw_int),
.led(led),
/*
* I2C
*/
.i2c_scl_i(i2c_scl_i),
.i2c_scl_o(i2c_scl_o),
.i2c_scl_t(i2c_scl_t),
.i2c_sda_i(i2c_sda_i),
.i2c_sda_o(i2c_sda_o),
.i2c_sda_t(i2c_sda_t),
/*
* Ethernet: 1000BASE-T RGMII
*/
.phy_rx_clk(phy_rx_clk),
.phy_rxd(phy_rxd_delay),
.phy_rx_ctl(phy_rx_ctl_delay),
.phy_tx_clk(phy_tx_clk),
.phy_txd(phy_txd),
.phy_tx_ctl(phy_tx_ctl),
.phy_reset_n(phy_reset_n),
.phy_int_n(phy_int_n),
.phy_pme_n(phy_pme_n),
/*
* UART: 115200 bps, 8N1
*/
.uart_rxd(uart_rxd_int),
.uart_txd(uart_txd)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDLCLKP_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__SDLCLKP_BEHAVIORAL_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_hdll__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hdll__sdlclkp (
GCLK,
SCE ,
GATE,
CLK
);
// Module ports
output GCLK;
input SCE ;
input GATE;
input CLK ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire m0 ;
wire m0n ;
wire clkn ;
wire CLK_delayed ;
wire SCE_delayed ;
wire GATE_delayed ;
wire SCE_gate_delayed;
reg notifier ;
wire awake ;
wire SCE_awake ;
wire GATE_awake ;
// Name Output Other arguments
not not0 (m0n , m0 );
not not1 (clkn , CLK_delayed );
nor nor0 (SCE_gate_delayed, GATE_delayed, SCE_delayed );
sky130_fd_sc_hdll__udp_dlatch$P_pp$PG$N dlatch0 (m0 , SCE_gate_delayed, clkn, notifier, VPWR, VGND);
and and0 (GCLK , m0n, CLK_delayed );
assign awake = ( VPWR === 1'b1 );
assign SCE_awake = ( awake & ( GATE_delayed === 1'b0 ) );
assign GATE_awake = ( awake & ( SCE_delayed === 1'b0 ) );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDLCLKP_BEHAVIORAL_V |
//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 3.91
// \ \ Application : MIG
// / / Filename : rank_mach.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : Virtex-6
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Top level rank machine structural block. This block
// instantiates a configurable number of rank controller blocks.
`timescale 1 ns / 1 ps
module rank_mach #
(
parameter BURST_MODE = "8",
parameter CS_WIDTH = 4,
parameter DRAM_TYPE = "DDR3",
parameter MAINT_PRESCALER_DIV = 40,
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2,
parameter CL = 5,
parameter nFAW = 30,
parameter nREFRESH_BANK = 8,
parameter nRRD = 4,
parameter nWTR = 4,
parameter PERIODIC_RD_TIMER_DIV = 20,
parameter RANK_BM_BV_WIDTH = 16,
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter REFRESH_TIMER_DIV = 39,
parameter PHASE_DETECT = "OFF",
parameter ZQ_TIMER_DIV = 640000
)
(/*AUTOARG*/
// Outputs
periodic_rd_rank_r, periodic_rd_r, maint_req_r, inhbt_act_faw_r,
inhbt_rd_r, wtr_inhbt_config_r, maint_rank_r, maint_zq_r,
// Inputs
wr_this_rank_r, slot_1_present, slot_0_present, sending_row,
sending_col, rst, rd_this_rank_r, rank_busy_r, periodic_rd_ack_r,
maint_wip_r, insert_maint_r1, dfi_init_complete, clk, app_zq_req,
app_ref_req, app_periodic_rd_req, act_this_rank_r
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [RANK_BM_BV_WIDTH-1:0] act_this_rank_r; // To rank_cntrl0 of rank_cntrl.v
input app_periodic_rd_req; // To rank_cntrl0 of rank_cntrl.v
input app_ref_req; // To rank_cntrl0 of rank_cntrl.v
input app_zq_req; // To rank_common0 of rank_common.v
input clk; // To rank_cntrl0 of rank_cntrl.v, ...
input dfi_init_complete; // To rank_cntrl0 of rank_cntrl.v, ...
input insert_maint_r1; // To rank_cntrl0 of rank_cntrl.v, ...
input maint_wip_r; // To rank_common0 of rank_common.v
input periodic_rd_ack_r; // To rank_common0 of rank_common.v
input [(RANKS*nBANK_MACHS)-1:0] rank_busy_r; // To rank_cntrl0 of rank_cntrl.v
input [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r; // To rank_cntrl0 of rank_cntrl.v
input rst; // To rank_cntrl0 of rank_cntrl.v, ...
input [nBANK_MACHS-1:0] sending_col; // To rank_cntrl0 of rank_cntrl.v
input [nBANK_MACHS-1:0] sending_row; // To rank_cntrl0 of rank_cntrl.v
input [7:0] slot_0_present; // To rank_common0 of rank_common.v
input [7:0] slot_1_present; // To rank_common0 of rank_common.v
input [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r; // To rank_cntrl0 of rank_cntrl.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output maint_req_r; // From rank_common0 of rank_common.v
output periodic_rd_r; // From rank_common0 of rank_common.v
output [RANK_WIDTH-1:0] periodic_rd_rank_r; // From rank_common0 of rank_common.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire maint_prescaler_tick_r; // From rank_common0 of rank_common.v
wire refresh_tick; // From rank_common0 of rank_common.v
// End of automatics
output [RANKS-1:0] inhbt_act_faw_r;
output [RANKS-1:0] inhbt_rd_r;
output [RANKS-1:0] wtr_inhbt_config_r;
output [RANK_WIDTH-1:0] maint_rank_r;
output maint_zq_r;
wire [RANKS-1:0] refresh_request;
wire [RANKS-1:0] periodic_rd_request;
wire [RANKS-1:0] clear_periodic_rd_request;
genvar ID;
generate
for (ID=0; ID<RANKS; ID=ID+1) begin:rank_cntrl
rank_cntrl#
(/*AUTOINSTPARAM*/
// Parameters
.BURST_MODE (BURST_MODE),
.ID (ID),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.CL (CL),
.nFAW (nFAW),
.nREFRESH_BANK (nREFRESH_BANK),
.nRRD (nRRD),
.nWTR (nWTR),
.PERIODIC_RD_TIMER_DIV (PERIODIC_RD_TIMER_DIV),
.RANK_BM_BV_WIDTH (RANK_BM_BV_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.PHASE_DETECT (PHASE_DETECT),//to controll periodic reads
.REFRESH_TIMER_DIV (REFRESH_TIMER_DIV))
rank_cntrl0
(.clear_periodic_rd_request (clear_periodic_rd_request[ID]),
.inhbt_act_faw_r (inhbt_act_faw_r[ID]),
.inhbt_rd_r (inhbt_rd_r[ID]),
.periodic_rd_request (periodic_rd_request[ID]),
.refresh_request (refresh_request[ID]),
.wtr_inhbt_config_r (wtr_inhbt_config_r[ID]),
/*AUTOINST*/
// Inputs
.clk (clk),
.rst (rst),
.sending_row (sending_row[nBANK_MACHS-1:0]),
.act_this_rank_r (act_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
.sending_col (sending_col[nBANK_MACHS-1:0]),
.wr_this_rank_r (wr_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
.app_ref_req (app_ref_req),
.dfi_init_complete (dfi_init_complete),
.rank_busy_r (rank_busy_r[(RANKS*nBANK_MACHS)-1:0]),
.refresh_tick (refresh_tick),
.insert_maint_r1 (insert_maint_r1),
.maint_zq_r (maint_zq_r),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.app_periodic_rd_req (app_periodic_rd_req),
.maint_prescaler_tick_r (maint_prescaler_tick_r),
.rd_this_rank_r (rd_this_rank_r[RANK_BM_BV_WIDTH-1:0]));
end
endgenerate
rank_common#
(/*AUTOINSTPARAM*/
// Parameters
.DRAM_TYPE (DRAM_TYPE),
.MAINT_PRESCALER_DIV (MAINT_PRESCALER_DIV),
.nBANK_MACHS (nBANK_MACHS),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.REFRESH_TIMER_DIV (REFRESH_TIMER_DIV),
.ZQ_TIMER_DIV (ZQ_TIMER_DIV))
rank_common0
(.clear_periodic_rd_request (clear_periodic_rd_request[RANKS-1:0]),
/*AUTOINST*/
// Outputs
.maint_prescaler_tick_r (maint_prescaler_tick_r),
.refresh_tick (refresh_tick),
.maint_zq_r (maint_zq_r),
.maint_req_r (maint_req_r),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.periodic_rd_r (periodic_rd_r),
.periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]),
// Inputs
.clk (clk),
.rst (rst),
.dfi_init_complete (dfi_init_complete),
.app_zq_req (app_zq_req),
.insert_maint_r1 (insert_maint_r1),
.refresh_request (refresh_request[RANKS-1:0]),
.maint_wip_r (maint_wip_r),
.slot_0_present (slot_0_present[7:0]),
.slot_1_present (slot_1_present[7:0]),
.periodic_rd_request (periodic_rd_request[RANKS-1:0]),
.periodic_rd_ack_r (periodic_rd_ack_r));
endmodule
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