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`include "assert.vh"
`include "cpu.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 6;
localparam MEM_EXTRA = 4;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("br_table3.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
parameter HAS_FPU = 1;
parameter USE_64B = 1;
reg reset = 0;
wire [63:0] result;
wire [ 1:0] result_type;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.HAS_FPU(HAS_FPU),
.USE_64B(USE_64B),
.MEM_DEPTH(MEM_ADDR)
)
dut
(
.clk(clk),
.reset(reset),
.result(result),
.result_type(result_type),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("br_table3_tb.vcd");
$dumpvars(0, cpu_tb);
if(USE_64B) begin
#90
`assert(result, 12);
`assert(result_type, `i64);
`assert(result_empty, 0);
`assert(trap, `ENDED);
end
else begin
#24
`assert(trap, `NO_64B);
end
$finish;
end
endmodule
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2015 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
Require Import
Bool ZAxioms ZMulOrder ZPow ZDivFloor ZSgnAbs ZParity NZLog.
(** Derived properties of bitwise operations *)
Module Type ZBitsProp
(Import A : ZAxiomsSig')
(Import B : ZMulOrderProp A)
(Import C : ZParityProp A B)
(Import D : ZSgnAbsProp A B)
(Import E : ZPowProp A B C D)
(Import F : ZDivProp A B D)
(Import G : NZLog2Prop A A A B E).
Include BoolEqualityFacts A.
Ltac order_nz := try apply pow_nonzero; order'.
Ltac order_pos' := try apply abs_nonneg; order_pos.
Hint Rewrite div_0_l mod_0_l div_1_r mod_1_r : nz.
(** Some properties of power and division *)
Lemma pow_sub_r : forall a b c, a~=0 -> 0<=c<=b -> a^(b-c) == a^b / a^c.
Proof.
intros a b c Ha (H,H'). rewrite <- (sub_simpl_r b c) at 2.
rewrite pow_add_r; trivial.
rewrite div_mul. reflexivity.
now apply pow_nonzero.
now apply le_0_sub.
Qed.
Lemma pow_div_l : forall a b c, b~=0 -> 0<=c -> a mod b == 0 ->
(a/b)^c == a^c / b^c.
Proof.
intros a b c Hb Hc H. rewrite (div_mod a b Hb) at 2.
rewrite H, add_0_r, pow_mul_l, mul_comm, div_mul. reflexivity.
now apply pow_nonzero.
Qed.
(** An injection from bits [true] and [false] to numbers 1 and 0.
We declare it as a (local) coercion for shorter statements. *)
Definition b2z (b:bool) := if b then 1 else 0.
Local Coercion b2z : bool >-> t.
Instance b2z_wd : Proper (Logic.eq ==> eq) b2z := _.
Lemma exists_div2 a : exists a' (b:bool), a == 2*a' + b.
Proof.
elim (Even_or_Odd a); [intros (a',H)| intros (a',H)].
exists a'. exists false. now nzsimpl.
exists a'. exists true. now simpl.
Qed.
(** We can compact [testbit_odd_0] [testbit_even_0]
[testbit_even_succ] [testbit_odd_succ] in only two lemmas. *)
Lemma testbit_0_r a (b:bool) : testbit (2*a+b) 0 = b.
Proof.
destruct b; simpl; rewrite ?add_0_r.
apply testbit_odd_0.
apply testbit_even_0.
Qed.
Lemma testbit_succ_r a (b:bool) n : 0<=n ->
testbit (2*a+b) (succ n) = testbit a n.
Proof.
destruct b; simpl; rewrite ?add_0_r.
now apply testbit_odd_succ.
now apply testbit_even_succ.
Qed.
(** Alternative caracterisations of [testbit] *)
(** This concise equation could have been taken as specification
for testbit in the interface, but it would have been hard to
implement with little initial knowledge about div and mod *)
Lemma testbit_spec' a n : 0<=n -> a.[n] == (a / 2^n) mod 2.
Proof.
intro Hn. revert a. apply le_ind with (4:=Hn).
solve_proper.
intros a. nzsimpl.
destruct (exists_div2 a) as (a' & b & H). rewrite H at 1.
rewrite testbit_0_r. apply mod_unique with a'; trivial.
left. destruct b; split; simpl; order'.
clear n Hn. intros n Hn IH a.
destruct (exists_div2 a) as (a' & b & H). rewrite H at 1.
rewrite testbit_succ_r, IH by trivial. f_equiv.
rewrite pow_succ_r, <- div_div by order_pos. f_equiv.
apply div_unique with b; trivial.
left. destruct b; split; simpl; order'.
Qed.
(** This caracterisation that uses only basic operations and
power was initially taken as specification for testbit.
We describe [a] as having a low part and a high part, with
the corresponding bit in the middle. This caracterisation
is moderatly complex to implement, but also moderately
usable... *)
Lemma testbit_spec a n : 0<=n ->
exists l h, 0<=l<2^n /\ a == l + (a.[n] + 2*h)*2^n.
Proof.
intro Hn. exists (a mod 2^n). exists (a / 2^n / 2). split.
apply mod_pos_bound; order_pos.
rewrite add_comm, mul_comm, (add_comm a.[n]).
rewrite (div_mod a (2^n)) at 1 by order_nz. do 2 f_equiv.
rewrite testbit_spec' by trivial. apply div_mod. order'.
Qed.
Lemma testbit_true : forall a n, 0<=n ->
(a.[n] = true <-> (a / 2^n) mod 2 == 1).
Proof.
intros a n Hn.
rewrite <- testbit_spec' by trivial.
destruct a.[n]; split; simpl; now try order'.
Qed.
Lemma testbit_false : forall a n, 0<=n ->
(a.[n] = false <-> (a / 2^n) mod 2 == 0).
Proof.
intros a n Hn.
rewrite <- testbit_spec' by trivial.
destruct a.[n]; split; simpl; now try order'.
Qed.
Lemma testbit_eqb : forall a n, 0<=n ->
a.[n] = eqb ((a / 2^n) mod 2) 1.
Proof.
intros a n Hn.
apply eq_true_iff_eq. now rewrite testbit_true, eqb_eq.
Qed.
(** Results about the injection [b2z] *)
Lemma b2z_inj : forall (a0 b0:bool), a0 == b0 -> a0 = b0.
Proof.
intros [|] [|]; simpl; trivial; order'.
Qed.
Lemma add_b2z_double_div2 : forall (a0:bool) a, (a0+2*a)/2 == a.
Proof.
intros a0 a. rewrite mul_comm, div_add by order'.
now rewrite div_small, add_0_l by (destruct a0; split; simpl; order').
Qed.
Lemma add_b2z_double_bit0 : forall (a0:bool) a, (a0+2*a).[0] = a0.
Proof.
intros a0 a. apply b2z_inj.
rewrite testbit_spec' by order.
nzsimpl. rewrite mul_comm, mod_add by order'.
now rewrite mod_small by (destruct a0; split; simpl; order').
Qed.
Lemma b2z_div2 : forall (a0:bool), a0/2 == 0.
Proof.
intros a0. rewrite <- (add_b2z_double_div2 a0 0). now nzsimpl.
Qed.
Lemma b2z_bit0 : forall (a0:bool), a0.[0] = a0.
Proof.
intros a0. rewrite <- (add_b2z_double_bit0 a0 0) at 2. now nzsimpl.
Qed.
(** The specification of testbit by low and high parts is complete *)
Lemma testbit_unique : forall a n (a0:bool) l h,
0<=l<2^n -> a == l + (a0 + 2*h)*2^n -> a.[n] = a0.
Proof.
intros a n a0 l h Hl EQ.
assert (0<=n).
destruct (le_gt_cases 0 n) as [Hn|Hn]; trivial.
rewrite pow_neg_r in Hl by trivial. destruct Hl; order.
apply b2z_inj. rewrite testbit_spec' by trivial.
symmetry. apply mod_unique with h.
left; destruct a0; simpl; split; order'.
symmetry. apply div_unique with l.
now left.
now rewrite add_comm, (add_comm _ a0), mul_comm.
Qed.
(** All bits of number 0 are 0 *)
Lemma bits_0 : forall n, 0.[n] = false.
Proof.
intros n.
destruct (le_gt_cases 0 n).
apply testbit_false; trivial. nzsimpl; order_nz.
now apply testbit_neg_r.
Qed.
(** For negative numbers, we are actually doing two's complement *)
Lemma bits_opp : forall a n, 0<=n -> (-a).[n] = negb (P a).[n].
Proof.
intros a n Hn.
destruct (testbit_spec (-a) n Hn) as (l & h & Hl & EQ).
fold (b2z (-a).[n]) in EQ.
apply negb_sym.
apply testbit_unique with (2^n-l-1) (-h-1).
split.
apply lt_succ_r. rewrite sub_1_r, succ_pred. now apply lt_0_sub.
apply le_succ_l. rewrite sub_1_r, succ_pred. apply le_sub_le_add_r.
rewrite <- (add_0_r (2^n)) at 1. now apply add_le_mono_l.
rewrite <- add_sub_swap, sub_1_r. f_equiv.
apply opp_inj. rewrite opp_add_distr, opp_sub_distr.
rewrite (add_comm _ l), <- add_assoc.
rewrite EQ at 1. apply add_cancel_l.
rewrite <- opp_add_distr.
rewrite <- (mul_1_l (2^n)) at 2. rewrite <- mul_add_distr_r.
rewrite <- mul_opp_l.
f_equiv.
rewrite !opp_add_distr.
rewrite <- mul_opp_r.
rewrite opp_sub_distr, opp_involutive.
rewrite (add_comm h).
rewrite mul_add_distr_l.
rewrite !add_assoc.
apply add_cancel_r.
rewrite mul_1_r.
rewrite add_comm, add_assoc, !add_opp_r, sub_1_r, two_succ, pred_succ.
destruct (-a).[n]; simpl. now rewrite sub_0_r. now nzsimpl'.
Qed.
(** All bits of number (-1) are 1 *)
Lemma bits_m1 : forall n, 0<=n -> (-1).[n] = true.
Proof.
intros. now rewrite bits_opp, one_succ, pred_succ, bits_0.
Qed.
(** Various ways to refer to the lowest bit of a number *)
Lemma bit0_odd : forall a, a.[0] = odd a.
Proof.
intros. symmetry.
destruct (exists_div2 a) as (a' & b & EQ).
rewrite EQ, testbit_0_r, add_comm, odd_add_mul_2.
destruct b; simpl; apply odd_1 || apply odd_0.
Qed.
Lemma bit0_eqb : forall a, a.[0] = eqb (a mod 2) 1.
Proof.
intros a. rewrite testbit_eqb by order. now nzsimpl.
Qed.
Lemma bit0_mod : forall a, a.[0] == a mod 2.
Proof.
intros a. rewrite testbit_spec' by order. now nzsimpl.
Qed.
(** Hence testing a bit is equivalent to shifting and testing parity *)
Lemma testbit_odd : forall a n, a.[n] = odd (a>>n).
Proof.
intros. now rewrite <- bit0_odd, shiftr_spec, add_0_l.
Qed.
(** [log2] gives the highest nonzero bit of positive numbers *)
Lemma bit_log2 : forall a, 0<a -> a.[log2 a] = true.
Proof.
intros a Ha.
assert (Ha' := log2_nonneg a).
destruct (log2_spec_alt a Ha) as (r & EQ & Hr).
rewrite EQ at 1.
rewrite testbit_true, add_comm by trivial.
rewrite <- (mul_1_l (2^log2 a)) at 1.
rewrite div_add by order_nz.
rewrite div_small; trivial.
rewrite add_0_l. apply mod_small. split; order'.
Qed.
Lemma bits_above_log2 : forall a n, 0<=a -> log2 a < n ->
a.[n] = false.
Proof.
intros a n Ha H.
assert (Hn : 0<=n).
transitivity (log2 a). apply log2_nonneg. order'.
rewrite testbit_false by trivial.
rewrite div_small. nzsimpl; order'.
split. order. apply log2_lt_cancel. now rewrite log2_pow2.
Qed.
(** Hence the number of bits of [a] is [1+log2 a]
(see [Pos.size_nat] and [Pos.size]).
*)
(** For negative numbers, things are the other ways around:
log2 gives the highest zero bit (for numbers below -1).
*)
Lemma bit_log2_neg : forall a, a < -1 -> a.[log2 (P (-a))] = false.
Proof.
intros a Ha.
rewrite <- (opp_involutive a) at 1.
rewrite bits_opp.
apply negb_false_iff.
apply bit_log2.
apply opp_lt_mono in Ha. rewrite opp_involutive in Ha.
apply lt_succ_lt_pred. now rewrite <- one_succ.
apply log2_nonneg.
Qed.
Lemma bits_above_log2_neg : forall a n, a < 0 -> log2 (P (-a)) < n ->
a.[n] = true.
Proof.
intros a n Ha H.
assert (Hn : 0<=n).
transitivity (log2 (P (-a))). apply log2_nonneg. order'.
rewrite <- (opp_involutive a), bits_opp, negb_true_iff by trivial.
apply bits_above_log2; trivial.
now rewrite <- opp_succ, opp_nonneg_nonpos, le_succ_l.
Qed.
(** Accesing a high enough bit of a number gives its sign *)
Lemma bits_iff_nonneg : forall a n, log2 (abs a) < n ->
(0<=a <-> a.[n] = false).
Proof.
intros a n Hn. split; intros H.
rewrite abs_eq in Hn; trivial. now apply bits_above_log2.
destruct (le_gt_cases 0 a); trivial.
rewrite abs_neq in Hn by order.
rewrite bits_above_log2_neg in H; try easy.
apply le_lt_trans with (log2 (-a)); trivial.
apply log2_le_mono. apply le_pred_l.
Qed.
Lemma bits_iff_nonneg' : forall a,
0<=a <-> a.[S (log2 (abs a))] = false.
Proof.
intros. apply bits_iff_nonneg. apply lt_succ_diag_r.
Qed.
Lemma bits_iff_nonneg_ex : forall a,
0<=a <-> (exists k, forall m, k<m -> a.[m] = false).
Proof.
intros a. split.
intros Ha. exists (log2 a). intros m Hm. now apply bits_above_log2.
intros (k,Hk). destruct (le_gt_cases k (log2 (abs a))).
now apply bits_iff_nonneg', Hk, lt_succ_r.
apply (bits_iff_nonneg a (S k)).
now apply lt_succ_r, lt_le_incl.
apply Hk. apply lt_succ_diag_r.
Qed.
Lemma bits_iff_neg : forall a n, log2 (abs a) < n ->
(a<0 <-> a.[n] = true).
Proof.
intros a n Hn.
now rewrite lt_nge, <- not_false_iff_true, (bits_iff_nonneg a n).
Qed.
Lemma bits_iff_neg' : forall a, a<0 <-> a.[S (log2 (abs a))] = true.
Proof.
intros. apply bits_iff_neg. apply lt_succ_diag_r.
Qed.
Lemma bits_iff_neg_ex : forall a,
a<0 <-> (exists k, forall m, k<m -> a.[m] = true).
Proof.
intros a. split.
intros Ha. exists (log2 (P (-a))). intros m Hm. now apply bits_above_log2_neg.
intros (k,Hk). destruct (le_gt_cases k (log2 (abs a))).
now apply bits_iff_neg', Hk, lt_succ_r.
apply (bits_iff_neg a (S k)).
now apply lt_succ_r, lt_le_incl.
apply Hk. apply lt_succ_diag_r.
Qed.
(** Testing bits after division or multiplication by a power of two *)
Lemma div2_bits : forall a n, 0<=n -> (a/2).[n] = a.[S n].
Proof.
intros a n Hn.
apply eq_true_iff_eq. rewrite 2 testbit_true by order_pos.
rewrite pow_succ_r by trivial.
now rewrite div_div by order_pos.
Qed.
Lemma div_pow2_bits : forall a n m, 0<=n -> 0<=m -> (a/2^n).[m] = a.[m+n].
Proof.
intros a n m Hn. revert a m. apply le_ind with (4:=Hn).
solve_proper.
intros a m Hm. now nzsimpl.
clear n Hn. intros n Hn IH a m Hm. nzsimpl; trivial.
rewrite <- div_div by order_pos.
now rewrite IH, div2_bits by order_pos.
Qed.
Lemma double_bits_succ : forall a n, (2*a).[S n] = a.[n].
Proof.
intros a n.
destruct (le_gt_cases 0 n) as [Hn|Hn].
now rewrite <- div2_bits, mul_comm, div_mul by order'.
rewrite (testbit_neg_r a n Hn).
apply le_succ_l in Hn. le_elim Hn.
now rewrite testbit_neg_r.
now rewrite Hn, bit0_odd, odd_mul, odd_2.
Qed.
Lemma double_bits : forall a n, (2*a).[n] = a.[P n].
Proof.
intros a n. rewrite <- (succ_pred n) at 1. apply double_bits_succ.
Qed.
Lemma mul_pow2_bits_add : forall a n m, 0<=n -> (a*2^n).[n+m] = a.[m].
Proof.
intros a n m Hn. revert a m. apply le_ind with (4:=Hn).
solve_proper.
intros a m. now nzsimpl.
clear n Hn. intros n Hn IH a m. nzsimpl; trivial.
rewrite mul_assoc, (mul_comm _ 2), <- mul_assoc.
now rewrite double_bits_succ.
Qed.
Lemma mul_pow2_bits : forall a n m, 0<=n -> (a*2^n).[m] = a.[m-n].
Proof.
intros.
rewrite <- (add_simpl_r m n) at 1. rewrite add_sub_swap, add_comm.
now apply mul_pow2_bits_add.
Qed.
Lemma mul_pow2_bits_low : forall a n m, m<n -> (a*2^n).[m] = false.
Proof.
intros.
destruct (le_gt_cases 0 n).
rewrite mul_pow2_bits by trivial.
apply testbit_neg_r. now apply lt_sub_0.
now rewrite pow_neg_r, mul_0_r, bits_0.
Qed.
(** Selecting the low part of a number can be done by a modulo *)
Lemma mod_pow2_bits_high : forall a n m, 0<=n<=m ->
(a mod 2^n).[m] = false.
Proof.
intros a n m (Hn,H).
destruct (mod_pos_bound a (2^n)) as [LE LT]. order_pos.
le_elim LE.
apply bits_above_log2; try order.
apply lt_le_trans with n; trivial.
apply log2_lt_pow2; trivial.
now rewrite <- LE, bits_0.
Qed.
Lemma mod_pow2_bits_low : forall a n m, m<n ->
(a mod 2^n).[m] = a.[m].
Proof.
intros a n m H.
destruct (le_gt_cases 0 m) as [Hm|Hm]; [|now rewrite !testbit_neg_r].
rewrite testbit_eqb; trivial.
rewrite <- (mod_add _ (2^(P (n-m))*(a/2^n))) by order'.
rewrite <- div_add by order_nz.
rewrite (mul_comm _ 2), mul_assoc, <- pow_succ_r, succ_pred.
rewrite mul_comm, mul_assoc, <- pow_add_r, (add_comm m), sub_add; trivial.
rewrite add_comm, <- div_mod by order_nz.
symmetry. apply testbit_eqb; trivial.
apply le_0_sub; order.
now apply lt_le_pred, lt_0_sub.
Qed.
(** We now prove that having the same bits implies equality.
For that we use a notion of equality over functional
streams of bits. *)
Definition eqf (f g:t -> bool) := forall n:t, f n = g n.
Instance eqf_equiv : Equivalence eqf.
Proof.
split; congruence.
Qed.
Local Infix "===" := eqf (at level 70, no associativity).
Instance testbit_eqf : Proper (eq==>eqf) testbit.
Proof.
intros a a' Ha n. now rewrite Ha.
Qed.
(** Only zero corresponds to the always-false stream. *)
Lemma bits_inj_0 :
forall a, (forall n, a.[n] = false) -> a == 0.
Proof.
intros a H. destruct (lt_trichotomy a 0) as [Ha|[Ha|Ha]]; trivial.
apply (bits_above_log2_neg a (S (log2 (P (-a))))) in Ha.
now rewrite H in Ha.
apply lt_succ_diag_r.
apply bit_log2 in Ha. now rewrite H in Ha.
Qed.
(** If two numbers produce the same stream of bits, they are equal. *)
Lemma bits_inj : forall a b, testbit a === testbit b -> a == b.
Proof.
assert (AUX : forall n, 0<=n -> forall a b,
0<=a<2^n -> testbit a === testbit b -> a == b).
intros n Hn. apply le_ind with (4:=Hn).
solve_proper.
intros a b Ha H. rewrite pow_0_r, one_succ, lt_succ_r in Ha.
assert (Ha' : a == 0) by (destruct Ha; order).
rewrite Ha' in *.
symmetry. apply bits_inj_0.
intros m. now rewrite <- H, bits_0.
clear n Hn. intros n Hn IH a b (Ha,Ha') H.
rewrite (div_mod a 2), (div_mod b 2) by order'.
f_equiv; [ | now rewrite <- 2 bit0_mod, H].
f_equiv.
apply IH.
split. apply div_pos; order'.
apply div_lt_upper_bound. order'. now rewrite <- pow_succ_r.
intros m.
destruct (le_gt_cases 0 m).
rewrite 2 div2_bits by trivial. apply H.
now rewrite 2 testbit_neg_r.
intros a b H.
destruct (le_gt_cases 0 a) as [Ha|Ha].
apply (AUX a); trivial. split; trivial.
apply pow_gt_lin_r; order'.
apply succ_inj, opp_inj.
assert (0 <= - S a).
apply opp_le_mono. now rewrite opp_involutive, opp_0, le_succ_l.
apply (AUX (-(S a))); trivial. split; trivial.
apply pow_gt_lin_r; order'.
intros m. destruct (le_gt_cases 0 m).
now rewrite 2 bits_opp, 2 pred_succ, H.
now rewrite 2 testbit_neg_r.
Qed.
Lemma bits_inj_iff : forall a b, testbit a === testbit b <-> a == b.
Proof.
split. apply bits_inj. intros EQ; now rewrite EQ.
Qed.
(** In fact, checking the bits at positive indexes is enough. *)
Lemma bits_inj' : forall a b,
(forall n, 0<=n -> a.[n] = b.[n]) -> a == b.
Proof.
intros a b H. apply bits_inj.
intros n. destruct (le_gt_cases 0 n).
now apply H.
now rewrite 2 testbit_neg_r.
Qed.
Lemma bits_inj_iff' : forall a b, (forall n, 0<=n -> a.[n] = b.[n]) <-> a == b.
Proof.
split. apply bits_inj'. intros EQ n Hn; now rewrite EQ.
Qed.
Ltac bitwise := apply bits_inj'; intros ?m ?Hm; autorewrite with bitwise.
Hint Rewrite lxor_spec lor_spec land_spec ldiff_spec bits_0 : bitwise.
(** The streams of bits that correspond to a numbers are
exactly the ones which are stationary after some point. *)
Lemma are_bits : forall (f:t->bool), Proper (eq==>Logic.eq) f ->
((exists n, forall m, 0<=m -> f m = n.[m]) <->
(exists k, forall m, k<=m -> f m = f k)).
Proof.
intros f Hf. split.
intros (a,H).
destruct (le_gt_cases 0 a).
exists (S (log2 a)). intros m Hm. apply le_succ_l in Hm.
rewrite 2 H, 2 bits_above_log2; trivial using lt_succ_diag_r.
order_pos. apply le_trans with (log2 a); order_pos.
exists (S (log2 (P (-a)))). intros m Hm. apply le_succ_l in Hm.
rewrite 2 H, 2 bits_above_log2_neg; trivial using lt_succ_diag_r.
order_pos. apply le_trans with (log2 (P (-a))); order_pos.
intros (k,Hk).
destruct (lt_ge_cases k 0) as [LT|LE].
case_eq (f 0); intros H0.
exists (-1). intros m Hm. rewrite bits_m1, Hk by order.
symmetry; rewrite <- H0. apply Hk; order.
exists 0. intros m Hm. rewrite bits_0, Hk by order.
symmetry; rewrite <- H0. apply Hk; order.
revert f Hf Hk. apply le_ind with (4:=LE).
(* compat : solve_proper fails here *)
apply proper_sym_impl_iff. exact eq_sym.
clear k LE. intros k k' Hk IH f Hf H. apply IH; trivial.
now setoid_rewrite Hk.
(* /compat *)
intros f Hf H0. destruct (f 0).
exists (-1). intros m Hm. now rewrite bits_m1, H0.
exists 0. intros m Hm. now rewrite bits_0, H0.
clear k LE. intros k LE IH f Hf Hk.
destruct (IH (fun m => f (S m))) as (n, Hn).
solve_proper.
intros m Hm. apply Hk. now rewrite <- succ_le_mono.
exists (f 0 + 2*n). intros m Hm.
le_elim Hm.
rewrite <- (succ_pred m), Hn, <- div2_bits.
rewrite mul_comm, div_add, b2z_div2, add_0_l; trivial. order'.
now rewrite <- lt_succ_r, succ_pred.
now rewrite <- lt_succ_r, succ_pred.
rewrite <- Hm.
symmetry. apply add_b2z_double_bit0.
Qed.
(** * Properties of shifts *)
(** First, a unified specification for [shiftl] : the [shiftl_spec]
below (combined with [testbit_neg_r]) is equivalent to
[shiftl_spec_low] and [shiftl_spec_high]. *)
Lemma shiftl_spec : forall a n m, 0<=m -> (a << n).[m] = a.[m-n].
Proof.
intros.
destruct (le_gt_cases n m).
now apply shiftl_spec_high.
rewrite shiftl_spec_low, testbit_neg_r; trivial. now apply lt_sub_0.
Qed.
(** A shiftl by a negative number is a shiftr, and vice-versa *)
Lemma shiftr_opp_r : forall a n, a >> (-n) == a << n.
Proof.
intros. bitwise. now rewrite shiftr_spec, shiftl_spec, add_opp_r.
Qed.
Lemma shiftl_opp_r : forall a n, a << (-n) == a >> n.
Proof.
intros. bitwise. now rewrite shiftr_spec, shiftl_spec, sub_opp_r.
Qed.
(** Shifts correspond to multiplication or division by a power of two *)
Lemma shiftr_div_pow2 : forall a n, 0<=n -> a >> n == a / 2^n.
Proof.
intros. bitwise. now rewrite shiftr_spec, div_pow2_bits.
Qed.
Lemma shiftr_mul_pow2 : forall a n, n<=0 -> a >> n == a * 2^(-n).
Proof.
intros. bitwise. rewrite shiftr_spec, mul_pow2_bits; trivial.
now rewrite sub_opp_r.
now apply opp_nonneg_nonpos.
Qed.
Lemma shiftl_mul_pow2 : forall a n, 0<=n -> a << n == a * 2^n.
Proof.
intros. bitwise. now rewrite shiftl_spec, mul_pow2_bits.
Qed.
Lemma shiftl_div_pow2 : forall a n, n<=0 -> a << n == a / 2^(-n).
Proof.
intros. bitwise. rewrite shiftl_spec, div_pow2_bits; trivial.
now rewrite add_opp_r.
now apply opp_nonneg_nonpos.
Qed.
(** Shifts are morphisms *)
Instance shiftr_wd : Proper (eq==>eq==>eq) shiftr.
Proof.
intros a a' Ha n n' Hn.
destruct (le_ge_cases n 0) as [H|H]; assert (H':=H); rewrite Hn in H'.
now rewrite 2 shiftr_mul_pow2, Ha, Hn.
now rewrite 2 shiftr_div_pow2, Ha, Hn.
Qed.
Instance shiftl_wd : Proper (eq==>eq==>eq) shiftl.
Proof.
intros a a' Ha n n' Hn. now rewrite <- 2 shiftr_opp_r, Ha, Hn.
Qed.
(** We could also have specified shiftl with an addition on the left. *)
Lemma shiftl_spec_alt : forall a n m, 0<=n -> (a << n).[m+n] = a.[m].
Proof.
intros. now rewrite shiftl_mul_pow2, mul_pow2_bits, add_simpl_r.
Qed.
(** Chaining several shifts. The only case for which
there isn't any simple expression is a true shiftr
followed by a true shiftl.
*)
Lemma shiftl_shiftl : forall a n m, 0<=n ->
(a << n) << m == a << (n+m).
Proof.
intros a n p Hn. bitwise.
rewrite 2 (shiftl_spec _ _ m) by trivial.
rewrite add_comm, sub_add_distr.
destruct (le_gt_cases 0 (m-p)) as [H|H].
now rewrite shiftl_spec.
rewrite 2 testbit_neg_r; trivial.
apply lt_sub_0. now apply lt_le_trans with 0.
Qed.
Lemma shiftr_shiftl_l : forall a n m, 0<=n ->
(a << n) >> m == a << (n-m).
Proof.
intros. now rewrite <- shiftl_opp_r, shiftl_shiftl, add_opp_r.
Qed.
Lemma shiftr_shiftl_r : forall a n m, 0<=n ->
(a << n) >> m == a >> (m-n).
Proof.
intros. now rewrite <- 2 shiftl_opp_r, shiftl_shiftl, opp_sub_distr, add_comm.
Qed.
Lemma shiftr_shiftr : forall a n m, 0<=m ->
(a >> n) >> m == a >> (n+m).
Proof.
intros a n p Hn. bitwise.
rewrite 3 shiftr_spec; trivial.
now rewrite (add_comm n p), add_assoc.
now apply add_nonneg_nonneg.
Qed.
(** shifts and constants *)
Lemma shiftl_1_l : forall n, 1 << n == 2^n.
Proof.
intros n. destruct (le_gt_cases 0 n).
now rewrite shiftl_mul_pow2, mul_1_l.
rewrite shiftl_div_pow2, div_1_l, pow_neg_r; try order.
apply pow_gt_1. order'. now apply opp_pos_neg.
Qed.
Lemma shiftl_0_r : forall a, a << 0 == a.
Proof.
intros. rewrite shiftl_mul_pow2 by order. now nzsimpl.
Qed.
Lemma shiftr_0_r : forall a, a >> 0 == a.
Proof.
intros. now rewrite <- shiftl_opp_r, opp_0, shiftl_0_r.
Qed.
Lemma shiftl_0_l : forall n, 0 << n == 0.
Proof.
intros.
destruct (le_ge_cases 0 n).
rewrite shiftl_mul_pow2 by trivial. now nzsimpl.
rewrite shiftl_div_pow2 by trivial.
rewrite <- opp_nonneg_nonpos in H. nzsimpl; order_nz.
Qed.
Lemma shiftr_0_l : forall n, 0 >> n == 0.
Proof.
intros. now rewrite <- shiftl_opp_r, shiftl_0_l.
Qed.
Lemma shiftl_eq_0_iff : forall a n, 0<=n -> (a << n == 0 <-> a == 0).
Proof.
intros a n Hn.
rewrite shiftl_mul_pow2 by trivial. rewrite eq_mul_0. split.
intros [H | H]; trivial. contradict H; order_nz.
intros H. now left.
Qed.
Lemma shiftr_eq_0_iff : forall a n,
a >> n == 0 <-> a==0 \/ (0<a /\ log2 a < n).
Proof.
intros a n.
destruct (le_gt_cases 0 n) as [Hn|Hn].
rewrite shiftr_div_pow2, div_small_iff by order_nz.
destruct (lt_trichotomy a 0) as [LT|[EQ|LT]].
split.
intros [(H,_)|(H,H')]. order. generalize (pow_nonneg 2 n le_0_2); order.
intros [H|(H,H')]; order.
rewrite EQ. split. now left. intros _; left. split; order_pos.
split. intros [(H,H')|(H,H')]; right. split; trivial.
apply log2_lt_pow2; trivial.
generalize (pow_nonneg 2 n le_0_2); order.
intros [H|(H,H')]. order. left.
split. order. now apply log2_lt_pow2.
rewrite shiftr_mul_pow2 by order. rewrite eq_mul_0.
split; intros [H|H].
now left.
elim (pow_nonzero 2 (-n)); try apply opp_nonneg_nonpos; order'.
now left.
destruct H. generalize (log2_nonneg a); order.
Qed.
Lemma shiftr_eq_0 : forall a n, 0<=a -> log2 a < n -> a >> n == 0.
Proof.
intros a n Ha H. apply shiftr_eq_0_iff.
le_elim Ha. right. now split. now left.
Qed.
(** Properties of [div2]. *)
Lemma div2_div : forall a, div2 a == a/2.
Proof.
intros. rewrite div2_spec, shiftr_div_pow2. now nzsimpl. order'.
Qed.
Instance div2_wd : Proper (eq==>eq) div2.
Proof.
intros a a' Ha. now rewrite 2 div2_div, Ha.
Qed.
Lemma div2_odd : forall a, a == 2*(div2 a) + odd a.
Proof.
intros a. rewrite div2_div, <- bit0_odd, bit0_mod.
apply div_mod. order'.
Qed.
(** Properties of [lxor] and others, directly deduced
from properties of [xorb] and others. *)
Instance lxor_wd : Proper (eq ==> eq ==> eq) lxor.
Proof.
intros a a' Ha b b' Hb. bitwise. now rewrite Ha, Hb.
Qed.
Instance land_wd : Proper (eq ==> eq ==> eq) land.
Proof.
intros a a' Ha b b' Hb. bitwise. now rewrite Ha, Hb.
Qed.
Instance lor_wd : Proper (eq ==> eq ==> eq) lor.
Proof.
intros a a' Ha b b' Hb. bitwise. now rewrite Ha, Hb.
Qed.
Instance ldiff_wd : Proper (eq ==> eq ==> eq) ldiff.
Proof.
intros a a' Ha b b' Hb. bitwise. now rewrite Ha, Hb.
Qed.
Lemma lxor_eq : forall a a', lxor a a' == 0 -> a == a'.
Proof.
intros a a' H. bitwise. apply xorb_eq.
now rewrite <- lxor_spec, H, bits_0.
Qed.
Lemma lxor_nilpotent : forall a, lxor a a == 0.
Proof.
intros. bitwise. apply xorb_nilpotent.
Qed.
Lemma lxor_eq_0_iff : forall a a', lxor a a' == 0 <-> a == a'.
Proof.
split. apply lxor_eq. intros EQ; rewrite EQ; apply lxor_nilpotent.
Qed.
Lemma lxor_0_l : forall a, lxor 0 a == a.
Proof.
intros. bitwise. apply xorb_false_l.
Qed.
Lemma lxor_0_r : forall a, lxor a 0 == a.
Proof.
intros. bitwise. apply xorb_false_r.
Qed.
Lemma lxor_comm : forall a b, lxor a b == lxor b a.
Proof.
intros. bitwise. apply xorb_comm.
Qed.
Lemma lxor_assoc :
forall a b c, lxor (lxor a b) c == lxor a (lxor b c).
Proof.
intros. bitwise. apply xorb_assoc.
Qed.
Lemma lor_0_l : forall a, lor 0 a == a.
Proof.
intros. bitwise. trivial.
Qed.
Lemma lor_0_r : forall a, lor a 0 == a.
Proof.
intros. bitwise. apply orb_false_r.
Qed.
Lemma lor_comm : forall a b, lor a b == lor b a.
Proof.
intros. bitwise. apply orb_comm.
Qed.
Lemma lor_assoc :
forall a b c, lor a (lor b c) == lor (lor a b) c.
Proof.
intros. bitwise. apply orb_assoc.
Qed.
Lemma lor_diag : forall a, lor a a == a.
Proof.
intros. bitwise. apply orb_diag.
Qed.
Lemma lor_eq_0_l : forall a b, lor a b == 0 -> a == 0.
Proof.
intros a b H. bitwise.
apply (orb_false_iff a.[m] b.[m]).
now rewrite <- lor_spec, H, bits_0.
Qed.
Lemma lor_eq_0_iff : forall a b, lor a b == 0 <-> a == 0 /\ b == 0.
Proof.
intros a b. split.
split. now apply lor_eq_0_l in H.
rewrite lor_comm in H. now apply lor_eq_0_l in H.
intros (EQ,EQ'). now rewrite EQ, lor_0_l.
Qed.
Lemma land_0_l : forall a, land 0 a == 0.
Proof.
intros. bitwise. trivial.
Qed.
Lemma land_0_r : forall a, land a 0 == 0.
Proof.
intros. bitwise. apply andb_false_r.
Qed.
Lemma land_comm : forall a b, land a b == land b a.
Proof.
intros. bitwise. apply andb_comm.
Qed.
Lemma land_assoc :
forall a b c, land a (land b c) == land (land a b) c.
Proof.
intros. bitwise. apply andb_assoc.
Qed.
Lemma land_diag : forall a, land a a == a.
Proof.
intros. bitwise. apply andb_diag.
Qed.
Lemma ldiff_0_l : forall a, ldiff 0 a == 0.
Proof.
intros. bitwise. trivial.
Qed.
Lemma ldiff_0_r : forall a, ldiff a 0 == a.
Proof.
intros. bitwise. now rewrite andb_true_r.
Qed.
Lemma ldiff_diag : forall a, ldiff a a == 0.
Proof.
intros. bitwise. apply andb_negb_r.
Qed.
Lemma lor_land_distr_l : forall a b c,
lor (land a b) c == land (lor a c) (lor b c).
Proof.
intros. bitwise. apply orb_andb_distrib_l.
Qed.
Lemma lor_land_distr_r : forall a b c,
lor a (land b c) == land (lor a b) (lor a c).
Proof.
intros. bitwise. apply orb_andb_distrib_r.
Qed.
Lemma land_lor_distr_l : forall a b c,
land (lor a b) c == lor (land a c) (land b c).
Proof.
intros. bitwise. apply andb_orb_distrib_l.
Qed.
Lemma land_lor_distr_r : forall a b c,
land a (lor b c) == lor (land a b) (land a c).
Proof.
intros. bitwise. apply andb_orb_distrib_r.
Qed.
Lemma ldiff_ldiff_l : forall a b c,
ldiff (ldiff a b) c == ldiff a (lor b c).
Proof.
intros. bitwise. now rewrite negb_orb, andb_assoc.
Qed.
Lemma lor_ldiff_and : forall a b,
lor (ldiff a b) (land a b) == a.
Proof.
intros. bitwise.
now rewrite <- andb_orb_distrib_r, orb_comm, orb_negb_r, andb_true_r.
Qed.
Lemma land_ldiff : forall a b,
land (ldiff a b) b == 0.
Proof.
intros. bitwise.
now rewrite <-andb_assoc, (andb_comm (negb _)), andb_negb_r, andb_false_r.
Qed.
(** Properties of [setbit] and [clearbit] *)
Definition setbit a n := lor a (1 << n).
Definition clearbit a n := ldiff a (1 << n).
Lemma setbit_spec' : forall a n, setbit a n == lor a (2^n).
Proof.
intros. unfold setbit. now rewrite shiftl_1_l.
Qed.
Lemma clearbit_spec' : forall a n, clearbit a n == ldiff a (2^n).
Proof.
intros. unfold clearbit. now rewrite shiftl_1_l.
Qed.
Instance setbit_wd : Proper (eq==>eq==>eq) setbit.
Proof. unfold setbit. solve_proper. Qed.
Instance clearbit_wd : Proper (eq==>eq==>eq) clearbit.
Proof. unfold clearbit. solve_proper. Qed.
Lemma pow2_bits_true : forall n, 0<=n -> (2^n).[n] = true.
Proof.
intros. rewrite <- (mul_1_l (2^n)).
now rewrite mul_pow2_bits, sub_diag, bit0_odd, odd_1.
Qed.
Lemma pow2_bits_false : forall n m, n~=m -> (2^n).[m] = false.
Proof.
intros.
destruct (le_gt_cases 0 n); [|now rewrite pow_neg_r, bits_0].
destruct (le_gt_cases n m).
rewrite <- (mul_1_l (2^n)), mul_pow2_bits; trivial.
rewrite <- (succ_pred (m-n)), <- div2_bits.
now rewrite div_small, bits_0 by (split; order').
rewrite <- lt_succ_r, succ_pred, lt_0_sub. order.
rewrite <- (mul_1_l (2^n)), mul_pow2_bits_low; trivial.
Qed.
Lemma pow2_bits_eqb : forall n m, 0<=n -> (2^n).[m] = eqb n m.
Proof.
intros n m Hn. apply eq_true_iff_eq. rewrite eqb_eq. split.
destruct (eq_decidable n m) as [H|H]. trivial.
now rewrite (pow2_bits_false _ _ H).
intros EQ. rewrite EQ. apply pow2_bits_true; order.
Qed.
Lemma setbit_eqb : forall a n m, 0<=n ->
(setbit a n).[m] = eqb n m || a.[m].
Proof.
intros. now rewrite setbit_spec', lor_spec, pow2_bits_eqb, orb_comm.
Qed.
Lemma setbit_iff : forall a n m, 0<=n ->
((setbit a n).[m] = true <-> n==m \/ a.[m] = true).
Proof.
intros. now rewrite setbit_eqb, orb_true_iff, eqb_eq.
Qed.
Lemma setbit_eq : forall a n, 0<=n -> (setbit a n).[n] = true.
Proof.
intros. apply setbit_iff; trivial. now left.
Qed.
Lemma setbit_neq : forall a n m, 0<=n -> n~=m ->
(setbit a n).[m] = a.[m].
Proof.
intros a n m Hn H. rewrite setbit_eqb; trivial.
rewrite <- eqb_eq in H. apply not_true_is_false in H. now rewrite H.
Qed.
Lemma clearbit_eqb : forall a n m,
(clearbit a n).[m] = a.[m] && negb (eqb n m).
Proof.
intros.
destruct (le_gt_cases 0 m); [| now rewrite 2 testbit_neg_r].
rewrite clearbit_spec', ldiff_spec. f_equal. f_equal.
destruct (le_gt_cases 0 n) as [Hn|Hn].
now apply pow2_bits_eqb.
symmetry. rewrite pow_neg_r, bits_0, <- not_true_iff_false, eqb_eq; order.
Qed.
Lemma clearbit_iff : forall a n m,
(clearbit a n).[m] = true <-> a.[m] = true /\ n~=m.
Proof.
intros. rewrite clearbit_eqb, andb_true_iff, <- eqb_eq.
now rewrite negb_true_iff, not_true_iff_false.
Qed.
Lemma clearbit_eq : forall a n, (clearbit a n).[n] = false.
Proof.
intros. rewrite clearbit_eqb, (proj2 (eqb_eq _ _) (eq_refl n)).
apply andb_false_r.
Qed.
Lemma clearbit_neq : forall a n m, n~=m ->
(clearbit a n).[m] = a.[m].
Proof.
intros a n m H. rewrite clearbit_eqb.
rewrite <- eqb_eq in H. apply not_true_is_false in H. rewrite H.
apply andb_true_r.
Qed.
(** Shifts of bitwise operations *)
Lemma shiftl_lxor : forall a b n,
(lxor a b) << n == lxor (a << n) (b << n).
Proof.
intros. bitwise. now rewrite !shiftl_spec, lxor_spec.
Qed.
Lemma shiftr_lxor : forall a b n,
(lxor a b) >> n == lxor (a >> n) (b >> n).
Proof.
intros. bitwise. now rewrite !shiftr_spec, lxor_spec.
Qed.
Lemma shiftl_land : forall a b n,
(land a b) << n == land (a << n) (b << n).
Proof.
intros. bitwise. now rewrite !shiftl_spec, land_spec.
Qed.
Lemma shiftr_land : forall a b n,
(land a b) >> n == land (a >> n) (b >> n).
Proof.
intros. bitwise. now rewrite !shiftr_spec, land_spec.
Qed.
Lemma shiftl_lor : forall a b n,
(lor a b) << n == lor (a << n) (b << n).
Proof.
intros. bitwise. now rewrite !shiftl_spec, lor_spec.
Qed.
Lemma shiftr_lor : forall a b n,
(lor a b) >> n == lor (a >> n) (b >> n).
Proof.
intros. bitwise. now rewrite !shiftr_spec, lor_spec.
Qed.
Lemma shiftl_ldiff : forall a b n,
(ldiff a b) << n == ldiff (a << n) (b << n).
Proof.
intros. bitwise. now rewrite !shiftl_spec, ldiff_spec.
Qed.
Lemma shiftr_ldiff : forall a b n,
(ldiff a b) >> n == ldiff (a >> n) (b >> n).
Proof.
intros. bitwise. now rewrite !shiftr_spec, ldiff_spec.
Qed.
(** For integers, we do have a binary complement function *)
Definition lnot a := P (-a).
Instance lnot_wd : Proper (eq==>eq) lnot.
Proof. unfold lnot. solve_proper. Qed.
Lemma lnot_spec : forall a n, 0<=n -> (lnot a).[n] = negb a.[n].
Proof.
intros. unfold lnot. rewrite <- (opp_involutive a) at 2.
rewrite bits_opp, negb_involutive; trivial.
Qed.
Lemma lnot_involutive : forall a, lnot (lnot a) == a.
Proof.
intros a. bitwise. now rewrite 2 lnot_spec, negb_involutive.
Qed.
Lemma lnot_0 : lnot 0 == -1.
Proof.
unfold lnot. now rewrite opp_0, <- sub_1_r, sub_0_l.
Qed.
Lemma lnot_m1 : lnot (-1) == 0.
Proof.
unfold lnot. now rewrite opp_involutive, one_succ, pred_succ.
Qed.
(** Complement and other operations *)
Lemma lor_m1_r : forall a, lor a (-1) == -1.
Proof.
intros. bitwise. now rewrite bits_m1, orb_true_r.
Qed.
Lemma lor_m1_l : forall a, lor (-1) a == -1.
Proof.
intros. now rewrite lor_comm, lor_m1_r.
Qed.
Lemma land_m1_r : forall a, land a (-1) == a.
Proof.
intros. bitwise. now rewrite bits_m1, andb_true_r.
Qed.
Lemma land_m1_l : forall a, land (-1) a == a.
Proof.
intros. now rewrite land_comm, land_m1_r.
Qed.
Lemma ldiff_m1_r : forall a, ldiff a (-1) == 0.
Proof.
intros. bitwise. now rewrite bits_m1, andb_false_r.
Qed.
Lemma ldiff_m1_l : forall a, ldiff (-1) a == lnot a.
Proof.
intros. bitwise. now rewrite lnot_spec, bits_m1.
Qed.
Lemma lor_lnot_diag : forall a, lor a (lnot a) == -1.
Proof.
intros a. bitwise. rewrite lnot_spec, bits_m1; trivial.
now destruct a.[m].
Qed.
Lemma add_lnot_diag : forall a, a + lnot a == -1.
Proof.
intros a. unfold lnot.
now rewrite add_pred_r, add_opp_r, sub_diag, one_succ, opp_succ, opp_0.
Qed.
Lemma ldiff_land : forall a b, ldiff a b == land a (lnot b).
Proof.
intros. bitwise. now rewrite lnot_spec.
Qed.
Lemma land_lnot_diag : forall a, land a (lnot a) == 0.
Proof.
intros. now rewrite <- ldiff_land, ldiff_diag.
Qed.
Lemma lnot_lor : forall a b, lnot (lor a b) == land (lnot a) (lnot b).
Proof.
intros a b. bitwise. now rewrite !lnot_spec, lor_spec, negb_orb.
Qed.
Lemma lnot_land : forall a b, lnot (land a b) == lor (lnot a) (lnot b).
Proof.
intros a b. bitwise. now rewrite !lnot_spec, land_spec, negb_andb.
Qed.
Lemma lnot_ldiff : forall a b, lnot (ldiff a b) == lor (lnot a) b.
Proof.
intros a b. bitwise.
now rewrite !lnot_spec, ldiff_spec, negb_andb, negb_involutive.
Qed.
Lemma lxor_lnot_lnot : forall a b, lxor (lnot a) (lnot b) == lxor a b.
Proof.
intros a b. bitwise. now rewrite !lnot_spec, xorb_negb_negb.
Qed.
Lemma lnot_lxor_l : forall a b, lnot (lxor a b) == lxor (lnot a) b.
Proof.
intros a b. bitwise. now rewrite !lnot_spec, !lxor_spec, negb_xorb_l.
Qed.
Lemma lnot_lxor_r : forall a b, lnot (lxor a b) == lxor a (lnot b).
Proof.
intros a b. bitwise. now rewrite !lnot_spec, !lxor_spec, negb_xorb_r.
Qed.
Lemma lxor_m1_r : forall a, lxor a (-1) == lnot a.
Proof.
intros. now rewrite <- (lxor_0_r (lnot a)), <- lnot_m1, lxor_lnot_lnot.
Qed.
Lemma lxor_m1_l : forall a, lxor (-1) a == lnot a.
Proof.
intros. now rewrite lxor_comm, lxor_m1_r.
Qed.
Lemma lxor_lor : forall a b, land a b == 0 ->
lxor a b == lor a b.
Proof.
intros a b H. bitwise.
assert (a.[m] && b.[m] = false)
by now rewrite <- land_spec, H, bits_0.
now destruct a.[m], b.[m].
Qed.
Lemma lnot_shiftr : forall a n, 0<=n -> lnot (a >> n) == (lnot a) >> n.
Proof.
intros a n Hn. bitwise.
now rewrite lnot_spec, 2 shiftr_spec, lnot_spec by order_pos.
Qed.
(** [(ones n)] is [2^n-1], the number with [n] digits 1 *)
Definition ones n := P (1<<n).
Instance ones_wd : Proper (eq==>eq) ones.
Proof. unfold ones. solve_proper. Qed.
Lemma ones_equiv : forall n, ones n == P (2^n).
Proof.
intros. unfold ones.
destruct (le_gt_cases 0 n).
now rewrite shiftl_mul_pow2, mul_1_l.
f_equiv. rewrite pow_neg_r; trivial.
rewrite <- shiftr_opp_r. apply shiftr_eq_0_iff. right; split.
order'. rewrite log2_1. now apply opp_pos_neg.
Qed.
Lemma ones_add : forall n m, 0<=n -> 0<=m ->
ones (m+n) == 2^m * ones n + ones m.
Proof.
intros n m Hn Hm. rewrite !ones_equiv.
rewrite <- !sub_1_r, mul_sub_distr_l, mul_1_r, <- pow_add_r by trivial.
rewrite add_sub_assoc, sub_add. reflexivity.
Qed.
Lemma ones_div_pow2 : forall n m, 0<=m<=n -> ones n / 2^m == ones (n-m).
Proof.
intros n m (Hm,H). symmetry. apply div_unique with (ones m).
left. rewrite ones_equiv. split.
rewrite <- lt_succ_r, succ_pred. order_pos.
now rewrite <- le_succ_l, succ_pred.
rewrite <- (sub_add m n) at 1. rewrite (add_comm _ m).
apply ones_add; trivial. now apply le_0_sub.
Qed.
Lemma ones_mod_pow2 : forall n m, 0<=m<=n -> (ones n) mod (2^m) == ones m.
Proof.
intros n m (Hm,H). symmetry. apply mod_unique with (ones (n-m)).
left. rewrite ones_equiv. split.
rewrite <- lt_succ_r, succ_pred. order_pos.
now rewrite <- le_succ_l, succ_pred.
rewrite <- (sub_add m n) at 1. rewrite (add_comm _ m).
apply ones_add; trivial. now apply le_0_sub.
Qed.
Lemma ones_spec_low : forall n m, 0<=m<n -> (ones n).[m] = true.
Proof.
intros n m (Hm,H). apply testbit_true; trivial.
rewrite ones_div_pow2 by (split; order).
rewrite <- (pow_1_r 2). rewrite ones_mod_pow2.
rewrite ones_equiv. now nzsimpl'.
split. order'. apply le_add_le_sub_r. nzsimpl. now apply le_succ_l.
Qed.
Lemma ones_spec_high : forall n m, 0<=n<=m -> (ones n).[m] = false.
Proof.
intros n m (Hn,H). le_elim Hn.
apply bits_above_log2; rewrite ones_equiv.
rewrite <-lt_succ_r, succ_pred; order_pos.
rewrite log2_pred_pow2; trivial. now rewrite <-le_succ_l, succ_pred.
rewrite ones_equiv. now rewrite <- Hn, pow_0_r, one_succ, pred_succ, bits_0.
Qed.
Lemma ones_spec_iff : forall n m, 0<=n ->
((ones n).[m] = true <-> 0<=m<n).
Proof.
intros n m Hn. split. intros H.
destruct (lt_ge_cases m 0) as [Hm|Hm].
now rewrite testbit_neg_r in H.
split; trivial. apply lt_nge. intro H'. rewrite ones_spec_high in H.
discriminate. now split.
apply ones_spec_low.
Qed.
Lemma lor_ones_low : forall a n, 0<=a -> log2 a < n ->
lor a (ones n) == ones n.
Proof.
intros a n Ha H. bitwise. destruct (le_gt_cases n m).
rewrite ones_spec_high, bits_above_log2; try split; trivial.
now apply lt_le_trans with n.
apply le_trans with (log2 a); order_pos.
rewrite ones_spec_low, orb_true_r; try split; trivial.
Qed.
Lemma land_ones : forall a n, 0<=n -> land a (ones n) == a mod 2^n.
Proof.
intros a n Hn. bitwise. destruct (le_gt_cases n m).
rewrite ones_spec_high, mod_pow2_bits_high, andb_false_r;
try split; trivial.
rewrite ones_spec_low, mod_pow2_bits_low, andb_true_r;
try split; trivial.
Qed.
Lemma land_ones_low : forall a n, 0<=a -> log2 a < n ->
land a (ones n) == a.
Proof.
intros a n Ha H.
assert (Hn : 0<=n) by (generalize (log2_nonneg a); order).
rewrite land_ones; trivial. apply mod_small.
split; trivial.
apply log2_lt_cancel. now rewrite log2_pow2.
Qed.
Lemma ldiff_ones_r : forall a n, 0<=n ->
ldiff a (ones n) == (a >> n) << n.
Proof.
intros a n Hn. bitwise. destruct (le_gt_cases n m).
rewrite ones_spec_high, shiftl_spec_high, shiftr_spec; trivial.
rewrite sub_add; trivial. apply andb_true_r.
now apply le_0_sub.
now split.
rewrite ones_spec_low, shiftl_spec_low, andb_false_r;
try split; trivial.
Qed.
Lemma ldiff_ones_r_low : forall a n, 0<=a -> log2 a < n ->
ldiff a (ones n) == 0.
Proof.
intros a n Ha H. bitwise. destruct (le_gt_cases n m).
rewrite ones_spec_high, bits_above_log2; trivial.
now apply lt_le_trans with n.
split; trivial. now apply le_trans with (log2 a); order_pos.
rewrite ones_spec_low, andb_false_r; try split; trivial.
Qed.
Lemma ldiff_ones_l_low : forall a n, 0<=a -> log2 a < n ->
ldiff (ones n) a == lxor a (ones n).
Proof.
intros a n Ha H. bitwise. destruct (le_gt_cases n m).
rewrite ones_spec_high, bits_above_log2; trivial.
now apply lt_le_trans with n.
split; trivial. now apply le_trans with (log2 a); order_pos.
rewrite ones_spec_low, xorb_true_r; try split; trivial.
Qed.
(** Bitwise operations and sign *)
Lemma shiftl_nonneg : forall a n, 0 <= (a << n) <-> 0 <= a.
Proof.
intros a n.
destruct (le_ge_cases 0 n) as [Hn|Hn].
(* 0<=n *)
rewrite 2 bits_iff_nonneg_ex. split; intros (k,Hk).
exists (k-n). intros m Hm.
destruct (le_gt_cases 0 m); [|now rewrite testbit_neg_r].
rewrite <- (add_simpl_r m n), <- (shiftl_spec a n) by order_pos.
apply Hk. now apply lt_sub_lt_add_r.
exists (k+n). intros m Hm.
destruct (le_gt_cases 0 m); [|now rewrite testbit_neg_r].
rewrite shiftl_spec by trivial. apply Hk. now apply lt_add_lt_sub_r.
(* n<=0*)
rewrite <- shiftr_opp_r, 2 bits_iff_nonneg_ex. split; intros (k,Hk).
destruct (le_gt_cases 0 k).
exists (k-n). intros m Hm. apply lt_sub_lt_add_r in Hm.
rewrite <- (add_simpl_r m n), <- add_opp_r, <- (shiftr_spec a (-n)).
now apply Hk. order.
assert (EQ : a >> (-n) == 0).
apply bits_inj'. intros m Hm. rewrite bits_0. apply Hk; order.
apply shiftr_eq_0_iff in EQ.
rewrite <- bits_iff_nonneg_ex. destruct EQ as [EQ|[LT _]]; order.
exists (k+n). intros m Hm.
destruct (le_gt_cases 0 m); [|now rewrite testbit_neg_r].
rewrite shiftr_spec by trivial. apply Hk.
rewrite add_opp_r. now apply lt_add_lt_sub_r.
Qed.
Lemma shiftl_neg : forall a n, (a << n) < 0 <-> a < 0.
Proof.
intros a n. now rewrite 2 lt_nge, shiftl_nonneg.
Qed.
Lemma shiftr_nonneg : forall a n, 0 <= (a >> n) <-> 0 <= a.
Proof.
intros. rewrite <- shiftl_opp_r. apply shiftl_nonneg.
Qed.
Lemma shiftr_neg : forall a n, (a >> n) < 0 <-> a < 0.
Proof.
intros a n. now rewrite 2 lt_nge, shiftr_nonneg.
Qed.
Lemma div2_nonneg : forall a, 0 <= div2 a <-> 0 <= a.
Proof.
intros. rewrite div2_spec. apply shiftr_nonneg.
Qed.
Lemma div2_neg : forall a, div2 a < 0 <-> a < 0.
Proof.
intros a. now rewrite 2 lt_nge, div2_nonneg.
Qed.
Lemma lor_nonneg : forall a b, 0 <= lor a b <-> 0<=a /\ 0<=b.
Proof.
intros a b.
rewrite 3 bits_iff_nonneg_ex. split. intros (k,Hk).
split; exists k; intros m Hm; apply (orb_false_elim a.[m] b.[m]);
rewrite <- lor_spec; now apply Hk.
intros ((k,Hk),(k',Hk')).
destruct (le_ge_cases k k'); [ exists k' | exists k ];
intros m Hm; rewrite lor_spec, Hk, Hk'; trivial; order.
Qed.
Lemma lor_neg : forall a b, lor a b < 0 <-> a < 0 \/ b < 0.
Proof.
intros a b. rewrite 3 lt_nge, lor_nonneg. split.
apply not_and. apply le_decidable.
now intros [H|H] (H',H'').
Qed.
Lemma lnot_nonneg : forall a, 0 <= lnot a <-> a < 0.
Proof.
intros a; unfold lnot.
now rewrite <- opp_succ, opp_nonneg_nonpos, le_succ_l.
Qed.
Lemma lnot_neg : forall a, lnot a < 0 <-> 0 <= a.
Proof.
intros a. now rewrite le_ngt, lt_nge, lnot_nonneg.
Qed.
Lemma land_nonneg : forall a b, 0 <= land a b <-> 0<=a \/ 0<=b.
Proof.
intros a b.
now rewrite <- (lnot_involutive (land a b)), lnot_land, lnot_nonneg,
lor_neg, !lnot_neg.
Qed.
Lemma land_neg : forall a b, land a b < 0 <-> a < 0 /\ b < 0.
Proof.
intros a b.
now rewrite <- (lnot_involutive (land a b)), lnot_land, lnot_neg,
lor_nonneg, !lnot_nonneg.
Qed.
Lemma ldiff_nonneg : forall a b, 0 <= ldiff a b <-> 0<=a \/ b<0.
Proof.
intros. now rewrite ldiff_land, land_nonneg, lnot_nonneg.
Qed.
Lemma ldiff_neg : forall a b, ldiff a b < 0 <-> a<0 /\ 0<=b.
Proof.
intros. now rewrite ldiff_land, land_neg, lnot_neg.
Qed.
Lemma lxor_nonneg : forall a b, 0 <= lxor a b <-> (0<=a <-> 0<=b).
Proof.
assert (H : forall a b, 0<=a -> 0<=b -> 0<=lxor a b).
intros a b. rewrite 3 bits_iff_nonneg_ex. intros (k,Hk) (k', Hk').
destruct (le_ge_cases k k'); [ exists k' | exists k];
intros m Hm; rewrite lxor_spec, Hk, Hk'; trivial; order.
assert (H' : forall a b, 0<=a -> b<0 -> lxor a b<0).
intros a b. rewrite bits_iff_nonneg_ex, 2 bits_iff_neg_ex.
intros (k,Hk) (k', Hk').
destruct (le_ge_cases k k'); [ exists k' | exists k];
intros m Hm; rewrite lxor_spec, Hk, Hk'; trivial; order.
intros a b.
split.
intros Hab. split.
intros Ha. destruct (le_gt_cases 0 b) as [Hb|Hb]; trivial.
generalize (H' _ _ Ha Hb). order.
intros Hb. destruct (le_gt_cases 0 a) as [Ha|Ha]; trivial.
generalize (H' _ _ Hb Ha). rewrite lxor_comm. order.
intros E.
destruct (le_gt_cases 0 a) as [Ha|Ha]. apply H; trivial. apply E; trivial.
destruct (le_gt_cases 0 b) as [Hb|Hb]. apply H; trivial. apply E; trivial.
rewrite <- lxor_lnot_lnot. apply H; now apply lnot_nonneg.
Qed.
(** Bitwise operations and log2 *)
Lemma log2_bits_unique : forall a n,
a.[n] = true ->
(forall m, n<m -> a.[m] = false) ->
log2 a == n.
Proof.
intros a n H H'.
destruct (lt_trichotomy a 0) as [Ha|[Ha|Ha]].
(* a < 0 *)
destruct (proj1 (bits_iff_neg_ex a) Ha) as (k,Hk).
destruct (le_gt_cases n k).
specialize (Hk (S k) (lt_succ_diag_r _)).
rewrite H' in Hk. discriminate. apply lt_succ_r; order.
specialize (H' (S n) (lt_succ_diag_r _)).
rewrite Hk in H'. discriminate. apply lt_succ_r; order.
(* a = 0 *)
now rewrite Ha, bits_0 in H.
(* 0 < a *)
apply le_antisymm; apply le_ngt; intros LT.
specialize (H' _ LT). now rewrite bit_log2 in H'.
now rewrite bits_above_log2 in H by order.
Qed.
Lemma log2_shiftr : forall a n, 0<a -> log2 (a >> n) == max 0 (log2 a - n).
Proof.
intros a n Ha.
destruct (le_gt_cases 0 (log2 a - n));
[rewrite max_r | rewrite max_l]; try order.
apply log2_bits_unique.
now rewrite shiftr_spec, sub_add, bit_log2.
intros m Hm.
destruct (le_gt_cases 0 m); [|now rewrite testbit_neg_r].
rewrite shiftr_spec; trivial. apply bits_above_log2; try order.
now apply lt_sub_lt_add_r.
rewrite lt_sub_lt_add_r, add_0_l in H.
apply log2_nonpos. apply le_lteq; right.
apply shiftr_eq_0_iff. right. now split.
Qed.
Lemma log2_shiftl : forall a n, 0<a -> 0<=n -> log2 (a << n) == log2 a + n.
Proof.
intros a n Ha Hn.
rewrite shiftl_mul_pow2, add_comm by trivial.
now apply log2_mul_pow2.
Qed.
Lemma log2_shiftl' : forall a n, 0<a -> log2 (a << n) == max 0 (log2 a + n).
Proof.
intros a n Ha.
rewrite <- shiftr_opp_r, log2_shiftr by trivial.
destruct (le_gt_cases 0 (log2 a + n));
[rewrite 2 max_r | rewrite 2 max_l]; rewrite ?sub_opp_r; try order.
Qed.
Lemma log2_lor : forall a b, 0<=a -> 0<=b ->
log2 (lor a b) == max (log2 a) (log2 b).
Proof.
assert (AUX : forall a b, 0<=a -> a<=b -> log2 (lor a b) == log2 b).
intros a b Ha H.
le_elim Ha; [|now rewrite <- Ha, lor_0_l].
apply log2_bits_unique.
now rewrite lor_spec, bit_log2, orb_true_r by order.
intros m Hm. assert (H' := log2_le_mono _ _ H).
now rewrite lor_spec, 2 bits_above_log2 by order.
(* main *)
intros a b Ha Hb. destruct (le_ge_cases a b) as [H|H].
rewrite max_r by now apply log2_le_mono.
now apply AUX.
rewrite max_l by now apply log2_le_mono.
rewrite lor_comm. now apply AUX.
Qed.
Lemma log2_land : forall a b, 0<=a -> 0<=b ->
log2 (land a b) <= min (log2 a) (log2 b).
Proof.
assert (AUX : forall a b, 0<=a -> a<=b -> log2 (land a b) <= log2 a).
intros a b Ha Hb.
apply le_ngt. intros LT.
assert (H : 0 <= land a b) by (apply land_nonneg; now left).
le_elim H.
generalize (bit_log2 (land a b) H).
now rewrite land_spec, bits_above_log2.
rewrite <- H in LT. apply log2_lt_cancel in LT; order.
(* main *)
intros a b Ha Hb.
destruct (le_ge_cases a b) as [H|H].
rewrite min_l by now apply log2_le_mono. now apply AUX.
rewrite min_r by now apply log2_le_mono. rewrite land_comm. now apply AUX.
Qed.
Lemma log2_lxor : forall a b, 0<=a -> 0<=b ->
log2 (lxor a b) <= max (log2 a) (log2 b).
Proof.
assert (AUX : forall a b, 0<=a -> a<=b -> log2 (lxor a b) <= log2 b).
intros a b Ha Hb.
apply le_ngt. intros LT.
assert (H : 0 <= lxor a b) by (apply lxor_nonneg; split; order).
le_elim H.
generalize (bit_log2 (lxor a b) H).
rewrite lxor_spec, 2 bits_above_log2; try order. discriminate.
apply le_lt_trans with (log2 b); trivial. now apply log2_le_mono.
rewrite <- H in LT. apply log2_lt_cancel in LT; order.
(* main *)
intros a b Ha Hb.
destruct (le_ge_cases a b) as [H|H].
rewrite max_r by now apply log2_le_mono. now apply AUX.
rewrite max_l by now apply log2_le_mono. rewrite lxor_comm. now apply AUX.
Qed.
(** Bitwise operations and arithmetical operations *)
Local Notation xor3 a b c := (xorb (xorb a b) c).
Local Notation lxor3 a b c := (lxor (lxor a b) c).
Local Notation nextcarry a b c := ((a&&b) || (c && (a||b))).
Local Notation lnextcarry a b c := (lor (land a b) (land c (lor a b))).
Lemma add_bit0 : forall a b, (a+b).[0] = xorb a.[0] b.[0].
Proof.
intros. now rewrite !bit0_odd, odd_add.
Qed.
Lemma add3_bit0 : forall a b c,
(a+b+c).[0] = xor3 a.[0] b.[0] c.[0].
Proof.
intros. now rewrite !add_bit0.
Qed.
Lemma add3_bits_div2 : forall (a0 b0 c0 : bool),
(a0 + b0 + c0)/2 == nextcarry a0 b0 c0.
Proof.
assert (H : 1+1 == 2) by now nzsimpl'.
intros [|] [|] [|]; simpl; rewrite ?add_0_l, ?add_0_r, ?H;
(apply div_same; order') || (apply div_small; split; order') || idtac.
symmetry. apply div_unique with 1. left; split; order'. now nzsimpl'.
Qed.
Lemma add_carry_div2 : forall a b (c0:bool),
(a + b + c0)/2 == a/2 + b/2 + nextcarry a.[0] b.[0] c0.
Proof.
intros.
rewrite <- add3_bits_div2.
rewrite (add_comm ((a/2)+_)).
rewrite <- div_add by order'.
f_equiv.
rewrite <- !div2_div, mul_comm, mul_add_distr_l.
rewrite (div2_odd a), <- bit0_odd at 1.
rewrite (div2_odd b), <- bit0_odd at 1.
rewrite add_shuffle1.
rewrite <-(add_assoc _ _ c0). apply add_comm.
Qed.
(** The main result concerning addition: we express the bits of the sum
in term of bits of [a] and [b] and of some carry stream which is also
recursively determined by another equation.
*)
Lemma add_carry_bits_aux : forall n, 0<=n ->
forall a b (c0:bool), -(2^n) <= a < 2^n -> -(2^n) <= b < 2^n ->
exists c,
a+b+c0 == lxor3 a b c /\ c/2 == lnextcarry a b c /\ c.[0] = c0.
Proof.
intros n Hn. apply le_ind with (4:=Hn).
solve_proper.
(* base *)
intros a b c0. rewrite !pow_0_r, !one_succ, !lt_succ_r, <- !one_succ.
intros (Ha1,Ha2) (Hb1,Hb2).
le_elim Ha1; rewrite <- ?le_succ_l, ?succ_m1 in Ha1;
le_elim Hb1; rewrite <- ?le_succ_l, ?succ_m1 in Hb1.
(* base, a = 0, b = 0 *)
exists c0.
rewrite (le_antisymm _ _ Ha2 Ha1), (le_antisymm _ _ Hb2 Hb1).
rewrite !add_0_l, !lxor_0_l, !lor_0_r, !land_0_r, !lor_0_r.
rewrite b2z_div2, b2z_bit0; now repeat split.
(* base, a = 0, b = -1 *)
exists (-c0). rewrite <- Hb1, (le_antisymm _ _ Ha2 Ha1). repeat split.
rewrite add_0_l, lxor_0_l, lxor_m1_l.
unfold lnot. now rewrite opp_involutive, add_comm, add_opp_r, sub_1_r.
rewrite land_0_l, !lor_0_l, land_m1_r.
symmetry. apply div_unique with c0. left; destruct c0; simpl; split; order'.
now rewrite two_succ, mul_succ_l, mul_1_l, add_opp_r, sub_add.
rewrite bit0_odd, odd_opp; destruct c0; simpl; apply odd_1 || apply odd_0.
(* base, a = -1, b = 0 *)
exists (-c0). rewrite <- Ha1, (le_antisymm _ _ Hb2 Hb1). repeat split.
rewrite add_0_r, lxor_0_r, lxor_m1_l.
unfold lnot. now rewrite opp_involutive, add_comm, add_opp_r, sub_1_r.
rewrite land_0_r, lor_0_r, lor_0_l, land_m1_r.
symmetry. apply div_unique with c0. left; destruct c0; simpl; split; order'.
now rewrite two_succ, mul_succ_l, mul_1_l, add_opp_r, sub_add.
rewrite bit0_odd, odd_opp; destruct c0; simpl; apply odd_1 || apply odd_0.
(* base, a = -1, b = -1 *)
exists (c0 + 2*(-1)). rewrite <- Ha1, <- Hb1. repeat split.
rewrite lxor_m1_l, lnot_m1, lxor_0_l.
now rewrite two_succ, mul_succ_l, mul_1_l, add_comm, add_assoc.
rewrite land_m1_l, lor_m1_l.
apply add_b2z_double_div2.
apply add_b2z_double_bit0.
(* step *)
clear n Hn. intros n Hn IH a b c0 Ha Hb.
set (c1:=nextcarry a.[0] b.[0] c0).
destruct (IH (a/2) (b/2) c1) as (c & IH1 & IH2 & Hc); clear IH.
split.
apply div_le_lower_bound. order'. now rewrite mul_opp_r, <- pow_succ_r.
apply div_lt_upper_bound. order'. now rewrite <- pow_succ_r.
split.
apply div_le_lower_bound. order'. now rewrite mul_opp_r, <- pow_succ_r.
apply div_lt_upper_bound. order'. now rewrite <- pow_succ_r.
exists (c0 + 2*c). repeat split.
(* step, add *)
bitwise.
le_elim Hm.
rewrite <- (succ_pred m), lt_succ_r in Hm.
rewrite <- (succ_pred m), <- !div2_bits, <- 2 lxor_spec by trivial.
f_equiv.
rewrite add_b2z_double_div2, <- IH1. apply add_carry_div2.
rewrite <- Hm.
now rewrite add_b2z_double_bit0, add3_bit0, b2z_bit0.
(* step, carry *)
rewrite add_b2z_double_div2.
bitwise.
le_elim Hm.
rewrite <- (succ_pred m), lt_succ_r in Hm.
rewrite <- (succ_pred m), <- !div2_bits, IH2 by trivial.
autorewrite with bitwise. now rewrite add_b2z_double_div2.
rewrite <- Hm.
now rewrite add_b2z_double_bit0.
(* step, carry0 *)
apply add_b2z_double_bit0.
Qed.
Lemma add_carry_bits : forall a b (c0:bool), exists c,
a+b+c0 == lxor3 a b c /\ c/2 == lnextcarry a b c /\ c.[0] = c0.
Proof.
intros a b c0.
set (n := max (abs a) (abs b)).
apply (add_carry_bits_aux n).
(* positivity *)
unfold n.
destruct (le_ge_cases (abs a) (abs b));
[rewrite max_r|rewrite max_l]; order_pos'.
(* bound for a *)
assert (Ha : abs a < 2^n).
apply lt_le_trans with (2^(abs a)). apply pow_gt_lin_r; order_pos'.
apply pow_le_mono_r. order'. unfold n.
destruct (le_ge_cases (abs a) (abs b));
[rewrite max_r|rewrite max_l]; try order.
apply abs_lt in Ha. destruct Ha; split; order.
(* bound for b *)
assert (Hb : abs b < 2^n).
apply lt_le_trans with (2^(abs b)). apply pow_gt_lin_r; order_pos'.
apply pow_le_mono_r. order'. unfold n.
destruct (le_ge_cases (abs a) (abs b));
[rewrite max_r|rewrite max_l]; try order.
apply abs_lt in Hb. destruct Hb; split; order.
Qed.
(** Particular case : the second bit of an addition *)
Lemma add_bit1 : forall a b,
(a+b).[1] = xor3 a.[1] b.[1] (a.[0] && b.[0]).
Proof.
intros a b.
destruct (add_carry_bits a b false) as (c & EQ1 & EQ2 & Hc).
simpl in EQ1; rewrite add_0_r in EQ1. rewrite EQ1.
autorewrite with bitwise. f_equal.
rewrite one_succ, <- div2_bits, EQ2 by order.
autorewrite with bitwise.
rewrite Hc. simpl. apply orb_false_r.
Qed.
(** In an addition, there will be no carries iff there is
no common bits in the numbers to add *)
Lemma nocarry_equiv : forall a b c,
c/2 == lnextcarry a b c -> c.[0] = false ->
(c == 0 <-> land a b == 0).
Proof.
intros a b c H H'.
split. intros EQ; rewrite EQ in *.
rewrite div_0_l in H by order'.
symmetry in H. now apply lor_eq_0_l in H.
intros EQ. rewrite EQ, lor_0_l in H.
apply bits_inj'. intros n Hn. rewrite bits_0.
apply le_ind with (4:=Hn).
solve_proper.
trivial.
clear n Hn. intros n Hn IH.
rewrite <- div2_bits, H; trivial.
autorewrite with bitwise.
now rewrite IH.
Qed.
(** When there is no common bits, the addition is just a xor *)
Lemma add_nocarry_lxor : forall a b, land a b == 0 ->
a+b == lxor a b.
Proof.
intros a b H.
destruct (add_carry_bits a b false) as (c & EQ1 & EQ2 & Hc).
simpl in EQ1; rewrite add_0_r in EQ1. rewrite EQ1.
apply (nocarry_equiv a b c) in H; trivial.
rewrite H. now rewrite lxor_0_r.
Qed.
(** A null [ldiff] implies being smaller *)
Lemma ldiff_le : forall a b, 0<=b -> ldiff a b == 0 -> 0 <= a <= b.
Proof.
assert (AUX : forall n, 0<=n ->
forall a b, 0 <= a < 2^n -> 0<=b -> ldiff a b == 0 -> a <= b).
intros n Hn. apply le_ind with (4:=Hn); clear n Hn.
solve_proper.
intros a b Ha Hb _. rewrite pow_0_r, one_succ, lt_succ_r in Ha.
setoid_replace a with 0 by (destruct Ha; order'); trivial.
intros n Hn IH a b (Ha,Ha') Hb H.
assert (NEQ : 2 ~= 0) by order'.
rewrite (div_mod a 2 NEQ), (div_mod b 2 NEQ).
apply add_le_mono.
apply mul_le_mono_pos_l; try order'.
apply IH.
split. apply div_pos; order'.
apply div_lt_upper_bound; try order'. now rewrite <- pow_succ_r.
apply div_pos; order'.
rewrite <- (pow_1_r 2), <- 2 shiftr_div_pow2 by order'.
rewrite <- shiftr_ldiff, H, shiftr_div_pow2, pow_1_r, div_0_l; order'.
rewrite <- 2 bit0_mod.
apply bits_inj_iff in H. specialize (H 0).
rewrite ldiff_spec, bits_0 in H.
destruct a.[0], b.[0]; try discriminate; simpl; order'.
(* main *)
intros a b Hb Hd.
assert (Ha : 0<=a).
apply le_ngt; intros Ha'. apply (lt_irrefl 0). rewrite <- Hd at 1.
apply ldiff_neg. now split.
split; trivial. apply (AUX a); try split; trivial. apply pow_gt_lin_r; order'.
Qed.
(** Subtraction can be a ldiff when the opposite ldiff is null. *)
Lemma sub_nocarry_ldiff : forall a b, ldiff b a == 0 ->
a-b == ldiff a b.
Proof.
intros a b H.
apply add_cancel_r with b.
rewrite sub_add.
symmetry.
rewrite add_nocarry_lxor; trivial.
bitwise.
apply bits_inj_iff in H. specialize (H m).
rewrite ldiff_spec, bits_0 in H.
now destruct a.[m], b.[m].
apply land_ldiff.
Qed.
(** Adding numbers with no common bits cannot lead to a much bigger number *)
Lemma add_nocarry_lt_pow2 : forall a b n, land a b == 0 ->
a < 2^n -> b < 2^n -> a+b < 2^n.
Proof.
intros a b n H Ha Hb.
destruct (le_gt_cases a 0) as [Ha'|Ha'].
apply le_lt_trans with (0+b). now apply add_le_mono_r. now nzsimpl.
destruct (le_gt_cases b 0) as [Hb'|Hb'].
apply le_lt_trans with (a+0). now apply add_le_mono_l. now nzsimpl.
rewrite add_nocarry_lxor by order.
destruct (lt_ge_cases 0 (lxor a b)); [|apply le_lt_trans with 0; order_pos].
apply log2_lt_pow2; trivial.
apply log2_lt_pow2 in Ha; trivial.
apply log2_lt_pow2 in Hb; trivial.
apply le_lt_trans with (max (log2 a) (log2 b)).
apply log2_lxor; order.
destruct (le_ge_cases (log2 a) (log2 b));
[rewrite max_r|rewrite max_l]; order.
Qed.
Lemma add_nocarry_mod_lt_pow2 : forall a b n, 0<=n -> land a b == 0 ->
a mod 2^n + b mod 2^n < 2^n.
Proof.
intros a b n Hn H.
apply add_nocarry_lt_pow2.
bitwise.
destruct (le_gt_cases n m).
rewrite mod_pow2_bits_high; now split.
now rewrite !mod_pow2_bits_low, <- land_spec, H, bits_0.
apply mod_pos_bound; order_pos.
apply mod_pos_bound; order_pos.
Qed.
End ZBitsProp.
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : V5-Block Plus for PCI Express
// File : pcie_soft_int.v
//--------------------------------------------------------------------------------
//--------------------------------------------------------------------------------
//--
//-- Description: PCIe Interrupt Module Wrapper for Softcore CMM32 Interrupt
//-- module
//--
//--
//--
//------------------------------------------------------------------------------
`timescale 1ns/1ns
`ifndef Tcq
`define Tcq 1
`endif
module pcie_soft_cf_int
(
// Clock and reset
input wire clk,
input wire rst_n,
input wire cs_is_intr,
input wire grant,
input wire [31:0] cfg_msguaddr,
// PCIe Block Interrupt Ports
input wire msi_enable,
output [3:0] msi_request,
output wire legacy_int_request,
// LocalLink Interrupt Ports
input wire cfg_interrupt_n,
output wire cfg_interrupt_rdy_n,
// NEWINTERRUPT signals
input wire msi_8bit_en,
input wire cfg_interrupt_assert_n,
input wire [7:0] cfg_interrupt_di,
output [2:0] cfg_interrupt_mmenable,
output [7:0] cfg_interrupt_do,
output cfg_interrupt_msienable,
input wire [31:0] msi_laddr,
input wire [31:0] msi_haddr,
input wire [15:0] cfg_command,
input wire [15:0] cfg_msgctrl,
input wire [15:0] cfg_msgdata,
// To Arb
output wire signaledint,
output wire intr_req_valid,
output wire [1:0] intr_req_type,
output wire [7:0] intr_vector
);
wire intr_rdy;
assign cfg_interrupt_rdy_n = ~intr_rdy;
assign cfg_interrupt_msienable = cfg_msgctrl[0]; // adr 0x48
assign legacy_int_request = 0; // tied low to disable in block
// legacy will be generated manually
assign msi_request = 4'd0; // tied low per ug197
assign cfg_interrupt_mmenable = cfg_msgctrl[6:4]; // MSI Cap Structure
assign cfg_interrupt_do = cfg_msgdata[7:0]; // MSI Message Data
// Interrupt controller from softcore
cmm_intr u_cmm_intr (
.clk (clk)
,.rst (~rst_n)
,.signaledint (signaledint) // O
,.intr_req_valid (intr_req_valid) // O
,.intr_req_type (intr_req_type) // O [1:0]
,.intr_rdy (intr_rdy) // O
,.cfg_interrupt_n (cfg_interrupt_n) // I [7:0]
,.cfg_interrupt_assert_n (cfg_interrupt_assert_n) // I
,.cfg_interrupt_di (cfg_interrupt_di) // I [7:0]
,.cfg_interrupt_mmenable (cfg_interrupt_mmenable) // I [2:0]
//,.cfg_interrupt_mmenable (3'b0) // I [2:0]
,.msi_data (cfg_msgdata) // I[15:0]
,.intr_vector (intr_vector) // O [7:0]
,.cfg ( {556'd0, msi_8bit_en ,467'd0} ) // I[1023:0]
,.command (cfg_command) // I [15:0]
,.msi_control (cfg_msgctrl) // I [15:0]
,.msi_laddr (msi_laddr) // I [31:0]
,.msi_haddr (msi_haddr) // I [31:0]
//,.intr_grant (grant) // I
,.intr_grant (grant & cs_is_intr) // I
);
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2013.4
// Copyright (C) 2013 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4_MulnS_0(clk, ce, a, b, p);
input clk;
input ce;
input[16 - 1 : 0] a; // synthesis attribute keep a "true"
input[8 - 1 : 0] b; // synthesis attribute keep b "true"
output[24 - 1 : 0] p;
reg[16 - 1 : 0] a_reg;
reg[8 - 1 : 0] b_reg;
wire [24 - 1 : 0] tmp_product;
reg[24 - 1 : 0] buff0;
reg[24 - 1 : 0] buff1;
assign p = buff1;
assign tmp_product = a_reg * b_reg;
always @ (posedge clk) begin
if (ce) begin
a_reg <= a;
b_reg <= b;
buff0 <= tmp_product;
buff1 <= buff0;
end
end
endmodule
`timescale 1 ns / 1 ps
module nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4_MulnS_0 nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4_MulnS_0_U(
.clk( clk ),
.ce( ce ),
.a( din0 ),
.b( din1 ),
.p( dout ));
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench (
// inputs:
A_cmp_result,
A_ctrl_ld_non_bypass,
A_en,
A_exc_active_no_break_no_crst,
A_exc_allowed,
A_exc_any_active,
A_exc_hbreak_pri1,
A_exc_highest_pri_exc_id,
A_exc_inst_fetch,
A_exc_norm_intr_pri5,
A_st_data,
A_valid,
A_wr_data_unfiltered,
A_wr_dst_reg,
E_add_br_to_taken_history_unfiltered,
M_bht_ptr_unfiltered,
M_bht_wr_data_unfiltered,
M_bht_wr_en_unfiltered,
M_mem_baddr,
M_target_pcb,
M_valid,
W_badaddr_reg,
W_bstatus_reg,
W_dst_regnum,
W_dst_regset,
W_estatus_reg,
W_exception_reg,
W_iw,
W_iw_op,
W_iw_opx,
W_pcb,
W_status_reg,
W_valid,
W_vinst,
W_wr_dst_reg,
clk,
d_address,
d_byteenable,
d_read,
d_readdatavalid,
d_write,
i_address,
i_read,
i_readdatavalid,
reset_n,
// outputs:
A_wr_data_filtered,
E_add_br_to_taken_history_filtered,
M_bht_ptr_filtered,
M_bht_wr_data_filtered,
M_bht_wr_en_filtered,
test_has_ended
)
;
output [ 31: 0] A_wr_data_filtered;
output E_add_br_to_taken_history_filtered;
output [ 7: 0] M_bht_ptr_filtered;
output [ 1: 0] M_bht_wr_data_filtered;
output M_bht_wr_en_filtered;
output test_has_ended;
input A_cmp_result;
input A_ctrl_ld_non_bypass;
input A_en;
input A_exc_active_no_break_no_crst;
input A_exc_allowed;
input A_exc_any_active;
input A_exc_hbreak_pri1;
input [ 31: 0] A_exc_highest_pri_exc_id;
input A_exc_inst_fetch;
input A_exc_norm_intr_pri5;
input [ 31: 0] A_st_data;
input A_valid;
input [ 31: 0] A_wr_data_unfiltered;
input A_wr_dst_reg;
input E_add_br_to_taken_history_unfiltered;
input [ 7: 0] M_bht_ptr_unfiltered;
input [ 1: 0] M_bht_wr_data_unfiltered;
input M_bht_wr_en_unfiltered;
input [ 24: 0] M_mem_baddr;
input [ 24: 0] M_target_pcb;
input M_valid;
input [ 31: 0] W_badaddr_reg;
input [ 31: 0] W_bstatus_reg;
input [ 4: 0] W_dst_regnum;
input [ 5: 0] W_dst_regset;
input [ 31: 0] W_estatus_reg;
input [ 31: 0] W_exception_reg;
input [ 31: 0] W_iw;
input [ 5: 0] W_iw_op;
input [ 5: 0] W_iw_opx;
input [ 24: 0] W_pcb;
input [ 31: 0] W_status_reg;
input W_valid;
input [ 71: 0] W_vinst;
input W_wr_dst_reg;
input clk;
input [ 24: 0] d_address;
input [ 3: 0] d_byteenable;
input d_read;
input d_readdatavalid;
input d_write;
input [ 24: 0] i_address;
input i_read;
input i_readdatavalid;
input reset_n;
wire A_iw_invalid;
reg [ 24: 0] A_mem_baddr;
reg [ 24: 0] A_target_pcb;
wire [ 31: 0] A_wr_data_filtered;
wire A_wr_data_unfiltered_0_is_x;
wire A_wr_data_unfiltered_10_is_x;
wire A_wr_data_unfiltered_11_is_x;
wire A_wr_data_unfiltered_12_is_x;
wire A_wr_data_unfiltered_13_is_x;
wire A_wr_data_unfiltered_14_is_x;
wire A_wr_data_unfiltered_15_is_x;
wire A_wr_data_unfiltered_16_is_x;
wire A_wr_data_unfiltered_17_is_x;
wire A_wr_data_unfiltered_18_is_x;
wire A_wr_data_unfiltered_19_is_x;
wire A_wr_data_unfiltered_1_is_x;
wire A_wr_data_unfiltered_20_is_x;
wire A_wr_data_unfiltered_21_is_x;
wire A_wr_data_unfiltered_22_is_x;
wire A_wr_data_unfiltered_23_is_x;
wire A_wr_data_unfiltered_24_is_x;
wire A_wr_data_unfiltered_25_is_x;
wire A_wr_data_unfiltered_26_is_x;
wire A_wr_data_unfiltered_27_is_x;
wire A_wr_data_unfiltered_28_is_x;
wire A_wr_data_unfiltered_29_is_x;
wire A_wr_data_unfiltered_2_is_x;
wire A_wr_data_unfiltered_30_is_x;
wire A_wr_data_unfiltered_31_is_x;
wire A_wr_data_unfiltered_3_is_x;
wire A_wr_data_unfiltered_4_is_x;
wire A_wr_data_unfiltered_5_is_x;
wire A_wr_data_unfiltered_6_is_x;
wire A_wr_data_unfiltered_7_is_x;
wire A_wr_data_unfiltered_8_is_x;
wire A_wr_data_unfiltered_9_is_x;
wire E_add_br_to_taken_history_filtered;
wire E_add_br_to_taken_history_unfiltered_is_x;
wire [ 7: 0] M_bht_ptr_filtered;
wire M_bht_ptr_unfiltered_0_is_x;
wire M_bht_ptr_unfiltered_1_is_x;
wire M_bht_ptr_unfiltered_2_is_x;
wire M_bht_ptr_unfiltered_3_is_x;
wire M_bht_ptr_unfiltered_4_is_x;
wire M_bht_ptr_unfiltered_5_is_x;
wire M_bht_ptr_unfiltered_6_is_x;
wire M_bht_ptr_unfiltered_7_is_x;
wire [ 1: 0] M_bht_wr_data_filtered;
wire M_bht_wr_data_unfiltered_0_is_x;
wire M_bht_wr_data_unfiltered_1_is_x;
wire M_bht_wr_en_filtered;
wire M_bht_wr_en_unfiltered_is_x;
reg W_cmp_result;
reg W_exc_any_active;
reg [ 31: 0] W_exc_highest_pri_exc_id;
wire W_is_opx_inst;
reg W_iw_invalid;
wire W_op_add;
wire W_op_addi;
wire W_op_and;
wire W_op_andhi;
wire W_op_andi;
wire W_op_beq;
wire W_op_bge;
wire W_op_bgeu;
wire W_op_blt;
wire W_op_bltu;
wire W_op_bne;
wire W_op_br;
wire W_op_break;
wire W_op_bret;
wire W_op_call;
wire W_op_callr;
wire W_op_cmpeq;
wire W_op_cmpeqi;
wire W_op_cmpge;
wire W_op_cmpgei;
wire W_op_cmpgeu;
wire W_op_cmpgeui;
wire W_op_cmplt;
wire W_op_cmplti;
wire W_op_cmpltu;
wire W_op_cmpltui;
wire W_op_cmpne;
wire W_op_cmpnei;
wire W_op_crst;
wire W_op_custom;
wire W_op_div;
wire W_op_divu;
wire W_op_eret;
wire W_op_flushd;
wire W_op_flushda;
wire W_op_flushi;
wire W_op_flushp;
wire W_op_hbreak;
wire W_op_initd;
wire W_op_initda;
wire W_op_initi;
wire W_op_intr;
wire W_op_jmp;
wire W_op_jmpi;
wire W_op_ldb;
wire W_op_ldbio;
wire W_op_ldbu;
wire W_op_ldbuio;
wire W_op_ldh;
wire W_op_ldhio;
wire W_op_ldhu;
wire W_op_ldhuio;
wire W_op_ldl;
wire W_op_ldw;
wire W_op_ldwio;
wire W_op_mul;
wire W_op_muli;
wire W_op_mulxss;
wire W_op_mulxsu;
wire W_op_mulxuu;
wire W_op_nextpc;
wire W_op_nor;
wire W_op_op_rsv02;
wire W_op_op_rsv09;
wire W_op_op_rsv10;
wire W_op_op_rsv17;
wire W_op_op_rsv18;
wire W_op_op_rsv25;
wire W_op_op_rsv26;
wire W_op_op_rsv33;
wire W_op_op_rsv34;
wire W_op_op_rsv41;
wire W_op_op_rsv42;
wire W_op_op_rsv49;
wire W_op_op_rsv57;
wire W_op_op_rsv61;
wire W_op_op_rsv62;
wire W_op_op_rsv63;
wire W_op_opx_rsv00;
wire W_op_opx_rsv10;
wire W_op_opx_rsv15;
wire W_op_opx_rsv17;
wire W_op_opx_rsv21;
wire W_op_opx_rsv25;
wire W_op_opx_rsv33;
wire W_op_opx_rsv34;
wire W_op_opx_rsv35;
wire W_op_opx_rsv42;
wire W_op_opx_rsv43;
wire W_op_opx_rsv44;
wire W_op_opx_rsv47;
wire W_op_opx_rsv50;
wire W_op_opx_rsv51;
wire W_op_opx_rsv55;
wire W_op_opx_rsv56;
wire W_op_opx_rsv60;
wire W_op_opx_rsv63;
wire W_op_or;
wire W_op_orhi;
wire W_op_ori;
wire W_op_rdctl;
wire W_op_rdprs;
wire W_op_ret;
wire W_op_rol;
wire W_op_roli;
wire W_op_ror;
wire W_op_sll;
wire W_op_slli;
wire W_op_sra;
wire W_op_srai;
wire W_op_srl;
wire W_op_srli;
wire W_op_stb;
wire W_op_stbio;
wire W_op_stc;
wire W_op_sth;
wire W_op_sthio;
wire W_op_stw;
wire W_op_stwio;
wire W_op_sub;
wire W_op_sync;
wire W_op_trap;
wire W_op_wrctl;
wire W_op_wrprs;
wire W_op_xor;
wire W_op_xorhi;
wire W_op_xori;
reg [ 31: 0] W_st_data;
reg [ 24: 0] W_target_pcb;
reg W_valid_crst;
reg W_valid_hbreak;
reg W_valid_intr;
reg [ 31: 0] W_wr_data_filtered;
wire test_has_ended;
assign W_op_call = W_iw_op == 0;
assign W_op_jmpi = W_iw_op == 1;
assign W_op_op_rsv02 = W_iw_op == 2;
assign W_op_ldbu = W_iw_op == 3;
assign W_op_addi = W_iw_op == 4;
assign W_op_stb = W_iw_op == 5;
assign W_op_br = W_iw_op == 6;
assign W_op_ldb = W_iw_op == 7;
assign W_op_cmpgei = W_iw_op == 8;
assign W_op_op_rsv09 = W_iw_op == 9;
assign W_op_op_rsv10 = W_iw_op == 10;
assign W_op_ldhu = W_iw_op == 11;
assign W_op_andi = W_iw_op == 12;
assign W_op_sth = W_iw_op == 13;
assign W_op_bge = W_iw_op == 14;
assign W_op_ldh = W_iw_op == 15;
assign W_op_cmplti = W_iw_op == 16;
assign W_op_op_rsv17 = W_iw_op == 17;
assign W_op_op_rsv18 = W_iw_op == 18;
assign W_op_initda = W_iw_op == 19;
assign W_op_ori = W_iw_op == 20;
assign W_op_stw = W_iw_op == 21;
assign W_op_blt = W_iw_op == 22;
assign W_op_ldw = W_iw_op == 23;
assign W_op_cmpnei = W_iw_op == 24;
assign W_op_op_rsv25 = W_iw_op == 25;
assign W_op_op_rsv26 = W_iw_op == 26;
assign W_op_flushda = W_iw_op == 27;
assign W_op_xori = W_iw_op == 28;
assign W_op_stc = W_iw_op == 29;
assign W_op_bne = W_iw_op == 30;
assign W_op_ldl = W_iw_op == 31;
assign W_op_cmpeqi = W_iw_op == 32;
assign W_op_op_rsv33 = W_iw_op == 33;
assign W_op_op_rsv34 = W_iw_op == 34;
assign W_op_ldbuio = W_iw_op == 35;
assign W_op_muli = W_iw_op == 36;
assign W_op_stbio = W_iw_op == 37;
assign W_op_beq = W_iw_op == 38;
assign W_op_ldbio = W_iw_op == 39;
assign W_op_cmpgeui = W_iw_op == 40;
assign W_op_op_rsv41 = W_iw_op == 41;
assign W_op_op_rsv42 = W_iw_op == 42;
assign W_op_ldhuio = W_iw_op == 43;
assign W_op_andhi = W_iw_op == 44;
assign W_op_sthio = W_iw_op == 45;
assign W_op_bgeu = W_iw_op == 46;
assign W_op_ldhio = W_iw_op == 47;
assign W_op_cmpltui = W_iw_op == 48;
assign W_op_op_rsv49 = W_iw_op == 49;
assign W_op_custom = W_iw_op == 50;
assign W_op_initd = W_iw_op == 51;
assign W_op_orhi = W_iw_op == 52;
assign W_op_stwio = W_iw_op == 53;
assign W_op_bltu = W_iw_op == 54;
assign W_op_ldwio = W_iw_op == 55;
assign W_op_rdprs = W_iw_op == 56;
assign W_op_op_rsv57 = W_iw_op == 57;
assign W_op_flushd = W_iw_op == 59;
assign W_op_xorhi = W_iw_op == 60;
assign W_op_op_rsv61 = W_iw_op == 61;
assign W_op_op_rsv62 = W_iw_op == 62;
assign W_op_op_rsv63 = W_iw_op == 63;
assign W_op_opx_rsv00 = (W_iw_opx == 0) & W_is_opx_inst;
assign W_op_eret = (W_iw_opx == 1) & W_is_opx_inst;
assign W_op_roli = (W_iw_opx == 2) & W_is_opx_inst;
assign W_op_rol = (W_iw_opx == 3) & W_is_opx_inst;
assign W_op_flushp = (W_iw_opx == 4) & W_is_opx_inst;
assign W_op_ret = (W_iw_opx == 5) & W_is_opx_inst;
assign W_op_nor = (W_iw_opx == 6) & W_is_opx_inst;
assign W_op_mulxuu = (W_iw_opx == 7) & W_is_opx_inst;
assign W_op_cmpge = (W_iw_opx == 8) & W_is_opx_inst;
assign W_op_bret = (W_iw_opx == 9) & W_is_opx_inst;
assign W_op_opx_rsv10 = (W_iw_opx == 10) & W_is_opx_inst;
assign W_op_ror = (W_iw_opx == 11) & W_is_opx_inst;
assign W_op_flushi = (W_iw_opx == 12) & W_is_opx_inst;
assign W_op_jmp = (W_iw_opx == 13) & W_is_opx_inst;
assign W_op_and = (W_iw_opx == 14) & W_is_opx_inst;
assign W_op_opx_rsv15 = (W_iw_opx == 15) & W_is_opx_inst;
assign W_op_cmplt = (W_iw_opx == 16) & W_is_opx_inst;
assign W_op_opx_rsv17 = (W_iw_opx == 17) & W_is_opx_inst;
assign W_op_slli = (W_iw_opx == 18) & W_is_opx_inst;
assign W_op_sll = (W_iw_opx == 19) & W_is_opx_inst;
assign W_op_wrprs = (W_iw_opx == 20) & W_is_opx_inst;
assign W_op_opx_rsv21 = (W_iw_opx == 21) & W_is_opx_inst;
assign W_op_or = (W_iw_opx == 22) & W_is_opx_inst;
assign W_op_mulxsu = (W_iw_opx == 23) & W_is_opx_inst;
assign W_op_cmpne = (W_iw_opx == 24) & W_is_opx_inst;
assign W_op_opx_rsv25 = (W_iw_opx == 25) & W_is_opx_inst;
assign W_op_srli = (W_iw_opx == 26) & W_is_opx_inst;
assign W_op_srl = (W_iw_opx == 27) & W_is_opx_inst;
assign W_op_nextpc = (W_iw_opx == 28) & W_is_opx_inst;
assign W_op_callr = (W_iw_opx == 29) & W_is_opx_inst;
assign W_op_xor = (W_iw_opx == 30) & W_is_opx_inst;
assign W_op_mulxss = (W_iw_opx == 31) & W_is_opx_inst;
assign W_op_cmpeq = (W_iw_opx == 32) & W_is_opx_inst;
assign W_op_opx_rsv33 = (W_iw_opx == 33) & W_is_opx_inst;
assign W_op_opx_rsv34 = (W_iw_opx == 34) & W_is_opx_inst;
assign W_op_opx_rsv35 = (W_iw_opx == 35) & W_is_opx_inst;
assign W_op_divu = (W_iw_opx == 36) & W_is_opx_inst;
assign W_op_div = (W_iw_opx == 37) & W_is_opx_inst;
assign W_op_rdctl = (W_iw_opx == 38) & W_is_opx_inst;
assign W_op_mul = (W_iw_opx == 39) & W_is_opx_inst;
assign W_op_cmpgeu = (W_iw_opx == 40) & W_is_opx_inst;
assign W_op_initi = (W_iw_opx == 41) & W_is_opx_inst;
assign W_op_opx_rsv42 = (W_iw_opx == 42) & W_is_opx_inst;
assign W_op_opx_rsv43 = (W_iw_opx == 43) & W_is_opx_inst;
assign W_op_opx_rsv44 = (W_iw_opx == 44) & W_is_opx_inst;
assign W_op_trap = (W_iw_opx == 45) & W_is_opx_inst;
assign W_op_wrctl = (W_iw_opx == 46) & W_is_opx_inst;
assign W_op_opx_rsv47 = (W_iw_opx == 47) & W_is_opx_inst;
assign W_op_cmpltu = (W_iw_opx == 48) & W_is_opx_inst;
assign W_op_add = (W_iw_opx == 49) & W_is_opx_inst;
assign W_op_opx_rsv50 = (W_iw_opx == 50) & W_is_opx_inst;
assign W_op_opx_rsv51 = (W_iw_opx == 51) & W_is_opx_inst;
assign W_op_break = (W_iw_opx == 52) & W_is_opx_inst;
assign W_op_hbreak = (W_iw_opx == 53) & W_is_opx_inst;
assign W_op_sync = (W_iw_opx == 54) & W_is_opx_inst;
assign W_op_opx_rsv55 = (W_iw_opx == 55) & W_is_opx_inst;
assign W_op_opx_rsv56 = (W_iw_opx == 56) & W_is_opx_inst;
assign W_op_sub = (W_iw_opx == 57) & W_is_opx_inst;
assign W_op_srai = (W_iw_opx == 58) & W_is_opx_inst;
assign W_op_sra = (W_iw_opx == 59) & W_is_opx_inst;
assign W_op_opx_rsv60 = (W_iw_opx == 60) & W_is_opx_inst;
assign W_op_intr = (W_iw_opx == 61) & W_is_opx_inst;
assign W_op_crst = (W_iw_opx == 62) & W_is_opx_inst;
assign W_op_opx_rsv63 = (W_iw_opx == 63) & W_is_opx_inst;
assign W_is_opx_inst = W_iw_op == 58;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
A_target_pcb <= 0;
else if (A_en)
A_target_pcb <= M_target_pcb;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
A_mem_baddr <= 0;
else if (A_en)
A_mem_baddr <= M_mem_baddr;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_wr_data_filtered <= 0;
else
W_wr_data_filtered <= A_wr_data_filtered;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_st_data <= 0;
else
W_st_data <= A_st_data;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_cmp_result <= 0;
else
W_cmp_result <= A_cmp_result;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_target_pcb <= 0;
else
W_target_pcb <= A_target_pcb;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_valid_hbreak <= 0;
else
W_valid_hbreak <= A_exc_allowed & A_exc_hbreak_pri1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_valid_crst <= 0;
else
W_valid_crst <= A_exc_allowed & 0;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_valid_intr <= 0;
else
W_valid_intr <= A_exc_allowed & A_exc_norm_intr_pri5;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_exc_any_active <= 0;
else
W_exc_any_active <= A_exc_any_active;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_exc_highest_pri_exc_id <= 0;
else
W_exc_highest_pri_exc_id <= A_exc_highest_pri_exc_id;
end
assign A_iw_invalid = A_exc_inst_fetch & A_exc_active_no_break_no_crst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_iw_invalid <= 0;
else
W_iw_invalid <= A_iw_invalid;
end
assign test_has_ended = 1'b0;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//Clearing 'X' data bits
assign A_wr_data_unfiltered_0_is_x = ^(A_wr_data_unfiltered[0]) === 1'bx;
assign A_wr_data_filtered[0] = (A_wr_data_unfiltered_0_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[0];
assign A_wr_data_unfiltered_1_is_x = ^(A_wr_data_unfiltered[1]) === 1'bx;
assign A_wr_data_filtered[1] = (A_wr_data_unfiltered_1_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[1];
assign A_wr_data_unfiltered_2_is_x = ^(A_wr_data_unfiltered[2]) === 1'bx;
assign A_wr_data_filtered[2] = (A_wr_data_unfiltered_2_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[2];
assign A_wr_data_unfiltered_3_is_x = ^(A_wr_data_unfiltered[3]) === 1'bx;
assign A_wr_data_filtered[3] = (A_wr_data_unfiltered_3_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[3];
assign A_wr_data_unfiltered_4_is_x = ^(A_wr_data_unfiltered[4]) === 1'bx;
assign A_wr_data_filtered[4] = (A_wr_data_unfiltered_4_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[4];
assign A_wr_data_unfiltered_5_is_x = ^(A_wr_data_unfiltered[5]) === 1'bx;
assign A_wr_data_filtered[5] = (A_wr_data_unfiltered_5_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[5];
assign A_wr_data_unfiltered_6_is_x = ^(A_wr_data_unfiltered[6]) === 1'bx;
assign A_wr_data_filtered[6] = (A_wr_data_unfiltered_6_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[6];
assign A_wr_data_unfiltered_7_is_x = ^(A_wr_data_unfiltered[7]) === 1'bx;
assign A_wr_data_filtered[7] = (A_wr_data_unfiltered_7_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[7];
assign A_wr_data_unfiltered_8_is_x = ^(A_wr_data_unfiltered[8]) === 1'bx;
assign A_wr_data_filtered[8] = (A_wr_data_unfiltered_8_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[8];
assign A_wr_data_unfiltered_9_is_x = ^(A_wr_data_unfiltered[9]) === 1'bx;
assign A_wr_data_filtered[9] = (A_wr_data_unfiltered_9_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[9];
assign A_wr_data_unfiltered_10_is_x = ^(A_wr_data_unfiltered[10]) === 1'bx;
assign A_wr_data_filtered[10] = (A_wr_data_unfiltered_10_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[10];
assign A_wr_data_unfiltered_11_is_x = ^(A_wr_data_unfiltered[11]) === 1'bx;
assign A_wr_data_filtered[11] = (A_wr_data_unfiltered_11_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[11];
assign A_wr_data_unfiltered_12_is_x = ^(A_wr_data_unfiltered[12]) === 1'bx;
assign A_wr_data_filtered[12] = (A_wr_data_unfiltered_12_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[12];
assign A_wr_data_unfiltered_13_is_x = ^(A_wr_data_unfiltered[13]) === 1'bx;
assign A_wr_data_filtered[13] = (A_wr_data_unfiltered_13_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[13];
assign A_wr_data_unfiltered_14_is_x = ^(A_wr_data_unfiltered[14]) === 1'bx;
assign A_wr_data_filtered[14] = (A_wr_data_unfiltered_14_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[14];
assign A_wr_data_unfiltered_15_is_x = ^(A_wr_data_unfiltered[15]) === 1'bx;
assign A_wr_data_filtered[15] = (A_wr_data_unfiltered_15_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[15];
assign A_wr_data_unfiltered_16_is_x = ^(A_wr_data_unfiltered[16]) === 1'bx;
assign A_wr_data_filtered[16] = (A_wr_data_unfiltered_16_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[16];
assign A_wr_data_unfiltered_17_is_x = ^(A_wr_data_unfiltered[17]) === 1'bx;
assign A_wr_data_filtered[17] = (A_wr_data_unfiltered_17_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[17];
assign A_wr_data_unfiltered_18_is_x = ^(A_wr_data_unfiltered[18]) === 1'bx;
assign A_wr_data_filtered[18] = (A_wr_data_unfiltered_18_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[18];
assign A_wr_data_unfiltered_19_is_x = ^(A_wr_data_unfiltered[19]) === 1'bx;
assign A_wr_data_filtered[19] = (A_wr_data_unfiltered_19_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[19];
assign A_wr_data_unfiltered_20_is_x = ^(A_wr_data_unfiltered[20]) === 1'bx;
assign A_wr_data_filtered[20] = (A_wr_data_unfiltered_20_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[20];
assign A_wr_data_unfiltered_21_is_x = ^(A_wr_data_unfiltered[21]) === 1'bx;
assign A_wr_data_filtered[21] = (A_wr_data_unfiltered_21_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[21];
assign A_wr_data_unfiltered_22_is_x = ^(A_wr_data_unfiltered[22]) === 1'bx;
assign A_wr_data_filtered[22] = (A_wr_data_unfiltered_22_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[22];
assign A_wr_data_unfiltered_23_is_x = ^(A_wr_data_unfiltered[23]) === 1'bx;
assign A_wr_data_filtered[23] = (A_wr_data_unfiltered_23_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[23];
assign A_wr_data_unfiltered_24_is_x = ^(A_wr_data_unfiltered[24]) === 1'bx;
assign A_wr_data_filtered[24] = (A_wr_data_unfiltered_24_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[24];
assign A_wr_data_unfiltered_25_is_x = ^(A_wr_data_unfiltered[25]) === 1'bx;
assign A_wr_data_filtered[25] = (A_wr_data_unfiltered_25_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[25];
assign A_wr_data_unfiltered_26_is_x = ^(A_wr_data_unfiltered[26]) === 1'bx;
assign A_wr_data_filtered[26] = (A_wr_data_unfiltered_26_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[26];
assign A_wr_data_unfiltered_27_is_x = ^(A_wr_data_unfiltered[27]) === 1'bx;
assign A_wr_data_filtered[27] = (A_wr_data_unfiltered_27_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[27];
assign A_wr_data_unfiltered_28_is_x = ^(A_wr_data_unfiltered[28]) === 1'bx;
assign A_wr_data_filtered[28] = (A_wr_data_unfiltered_28_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[28];
assign A_wr_data_unfiltered_29_is_x = ^(A_wr_data_unfiltered[29]) === 1'bx;
assign A_wr_data_filtered[29] = (A_wr_data_unfiltered_29_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[29];
assign A_wr_data_unfiltered_30_is_x = ^(A_wr_data_unfiltered[30]) === 1'bx;
assign A_wr_data_filtered[30] = (A_wr_data_unfiltered_30_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[30];
assign A_wr_data_unfiltered_31_is_x = ^(A_wr_data_unfiltered[31]) === 1'bx;
assign A_wr_data_filtered[31] = (A_wr_data_unfiltered_31_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[31];
//Clearing 'X' data bits
assign E_add_br_to_taken_history_unfiltered_is_x = ^(E_add_br_to_taken_history_unfiltered) === 1'bx;
assign E_add_br_to_taken_history_filtered = E_add_br_to_taken_history_unfiltered_is_x ? 1'b0 : E_add_br_to_taken_history_unfiltered;
//Clearing 'X' data bits
assign M_bht_wr_en_unfiltered_is_x = ^(M_bht_wr_en_unfiltered) === 1'bx;
assign M_bht_wr_en_filtered = M_bht_wr_en_unfiltered_is_x ? 1'b0 : M_bht_wr_en_unfiltered;
//Clearing 'X' data bits
assign M_bht_wr_data_unfiltered_0_is_x = ^(M_bht_wr_data_unfiltered[0]) === 1'bx;
assign M_bht_wr_data_filtered[0] = M_bht_wr_data_unfiltered_0_is_x ? 1'b0 : M_bht_wr_data_unfiltered[0];
assign M_bht_wr_data_unfiltered_1_is_x = ^(M_bht_wr_data_unfiltered[1]) === 1'bx;
assign M_bht_wr_data_filtered[1] = M_bht_wr_data_unfiltered_1_is_x ? 1'b0 : M_bht_wr_data_unfiltered[1];
//Clearing 'X' data bits
assign M_bht_ptr_unfiltered_0_is_x = ^(M_bht_ptr_unfiltered[0]) === 1'bx;
assign M_bht_ptr_filtered[0] = M_bht_ptr_unfiltered_0_is_x ? 1'b0 : M_bht_ptr_unfiltered[0];
assign M_bht_ptr_unfiltered_1_is_x = ^(M_bht_ptr_unfiltered[1]) === 1'bx;
assign M_bht_ptr_filtered[1] = M_bht_ptr_unfiltered_1_is_x ? 1'b0 : M_bht_ptr_unfiltered[1];
assign M_bht_ptr_unfiltered_2_is_x = ^(M_bht_ptr_unfiltered[2]) === 1'bx;
assign M_bht_ptr_filtered[2] = M_bht_ptr_unfiltered_2_is_x ? 1'b0 : M_bht_ptr_unfiltered[2];
assign M_bht_ptr_unfiltered_3_is_x = ^(M_bht_ptr_unfiltered[3]) === 1'bx;
assign M_bht_ptr_filtered[3] = M_bht_ptr_unfiltered_3_is_x ? 1'b0 : M_bht_ptr_unfiltered[3];
assign M_bht_ptr_unfiltered_4_is_x = ^(M_bht_ptr_unfiltered[4]) === 1'bx;
assign M_bht_ptr_filtered[4] = M_bht_ptr_unfiltered_4_is_x ? 1'b0 : M_bht_ptr_unfiltered[4];
assign M_bht_ptr_unfiltered_5_is_x = ^(M_bht_ptr_unfiltered[5]) === 1'bx;
assign M_bht_ptr_filtered[5] = M_bht_ptr_unfiltered_5_is_x ? 1'b0 : M_bht_ptr_unfiltered[5];
assign M_bht_ptr_unfiltered_6_is_x = ^(M_bht_ptr_unfiltered[6]) === 1'bx;
assign M_bht_ptr_filtered[6] = M_bht_ptr_unfiltered_6_is_x ? 1'b0 : M_bht_ptr_unfiltered[6];
assign M_bht_ptr_unfiltered_7_is_x = ^(M_bht_ptr_unfiltered[7]) === 1'bx;
assign M_bht_ptr_filtered[7] = M_bht_ptr_unfiltered_7_is_x ? 1'b0 : M_bht_ptr_unfiltered[7];
always @(posedge clk)
begin
if (reset_n)
if (^(W_wr_dst_reg) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/W_wr_dst_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_wr_dst_reg)
if (^(W_dst_regnum) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/W_dst_regnum is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(W_valid) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/W_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid)
if (^(W_pcb) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/W_pcb is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid)
if (^(W_iw) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/W_iw is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(A_en) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/A_en is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_wr_dst_reg)
if (^(W_dst_regset) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/W_dst_regset is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(M_valid) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/M_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(A_valid) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/A_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (A_valid & A_en & A_wr_dst_reg)
if (^(A_wr_data_unfiltered) === 1'bx)
begin
$write("%0d ns: WARNING: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/A_wr_data_unfiltered is 'x'\n", $time);
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(W_status_reg) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/W_status_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(W_estatus_reg) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/W_estatus_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(W_bstatus_reg) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/W_bstatus_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(W_exception_reg) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/W_exception_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(W_badaddr_reg) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/W_badaddr_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(A_exc_any_active) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/A_exc_any_active is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(i_read) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/i_read is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (i_read)
if (^(i_address) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/i_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_write) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/d_write is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write)
if (^(d_byteenable) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/d_byteenable is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write | d_read)
if (^(d_address) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/d_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_read) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/d_read is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(i_readdatavalid) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/i_readdatavalid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_readdatavalid) === 1'bx)
begin
$write("%0d ns: ERROR: TimeHoldOver_Qsys_nios2_gen2_0_cpu_test_bench/d_readdatavalid is 'x'\n", $time);
$stop;
end
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
//
// assign A_wr_data_filtered = A_wr_data_unfiltered;
//
//
// assign E_add_br_to_taken_history_filtered = E_add_br_to_taken_history_unfiltered;
//
//
// assign M_bht_wr_en_filtered = M_bht_wr_en_unfiltered;
//
//
// assign M_bht_wr_data_filtered = M_bht_wr_data_unfiltered;
//
//
// assign M_bht_ptr_filtered = M_bht_ptr_unfiltered;
//
//synthesis read_comments_as_HDL off
endmodule
|
//
// Copyright (c) 2001 Stephan Gehring
//
// (Modified by Stephan Williams to include PASS/FAIL messages.)
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
module test;
reg [7:0] x;
initial begin
x = 'h4000 + 'hzz; // iverilog doesn't like 'hzz
if (x !== 8'hxx) begin
$display("FAILED -- x = %b", x);
$finish;
end
$display("PASSED");
end
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:
// Design Name:
// Module Name: quick_spi
// Project Name:
// Target Devices:
// Tool Versions:
// Description: spi module with arbitrary data length up to 64 bits,
// i.e it could send 37 or 23 or 11 bits
//
// Dependencies:
//
// Revision:
// Revision 1.0
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
`define LSB_FIRST 0
`define MSB_FIRST 1
`define LITTLE_ENDIAN 0
`define BIG_ENDIAN 1
`define MAX_DATA_WIDTH 64
module quick_spi_hard #
(
// slaves number
parameter NUMBER_OF_SLAVES = 2,
// data transfer parameters (data bus width, words quantity, e.t.c)
parameter INCOMING_DATA_WIDTH = 8,
parameter OUTGOING_DATA_WIDTH = 16,
// bits and bytes order (how outgoing data is popping from buffer)
parameter BITS_ORDER = `MSB_FIRST,
parameter BYTES_ORDER = `LITTLE_ENDIAN,
// extra toggles
parameter EXTRA_WRITE_SCLK_TOGGLES = 6,
parameter EXTRA_READ_SCLK_TOGGLES = 4,
// clock polarity and phase
parameter CPOL = 0,
parameter CPHA = 0,
// idle values
parameter MOSI_IDLE_VALUE = 1'b0
)
(
input wire clk,
input wire reset_n,
input wire enable,
input wire start_transaction,
input wire[NUMBER_OF_SLAVES-1:0] slave,
input wire operation,
output reg end_of_transaction,
output reg[INCOMING_DATA_WIDTH-1:0] incoming_data,
input wire[OUTGOING_DATA_WIDTH-1:0] outgoing_data,
output reg mosi,
input wire miso,
output reg sclk,
output reg[NUMBER_OF_SLAVES-1:0] ss_n);
localparam READ = 1'b0;
localparam WRITE = 1'b1;
localparam READ_SCLK_TOGGLES = (INCOMING_DATA_WIDTH * 2) + 2;
localparam ALL_READ_TOGGLES = EXTRA_READ_SCLK_TOGGLES + READ_SCLK_TOGGLES;
// at least 1, because we could transfer i.e. 6 or 5 bits ()
localparam NUMBER_OF_FULL_BYTES = OUTGOING_DATA_WIDTH > 1 ? (OUTGOING_DATA_WIDTH / 8) : 0;
localparam NUMBER_OF_PARTICULAR_BITS = OUTGOING_DATA_WIDTH > (NUMBER_OF_FULL_BYTES * 8) ? 1 : 0;
localparam NUMBER_OF_BYTES = NUMBER_OF_FULL_BYTES + NUMBER_OF_PARTICULAR_BITS;
localparam MAX_BYTES_INDEX = NUMBER_OF_BYTES - 1;
integer sclk_toggle_count;
integer transaction_toggles;
reg spi_clock_phase;
reg[1:0] state;
localparam IDLE = 2'b00;
localparam ACTIVE = 2'b01;
localparam WAIT = 2'b10;
reg[INCOMING_DATA_WIDTH - 1:0] incoming_data_buffer;
reg[OUTGOING_DATA_WIDTH - 1:0] outgoing_data_buffer;
reg[`MAX_DATA_WIDTH - 1:0] intermediate_buffer;
reg[2:0] bit_counter;
reg[3:0] byte_counter;
always @ (posedge clk)
begin
if(!reset_n)
begin
end_of_transaction <= 1'b0;
mosi <= MOSI_IDLE_VALUE;
sclk <= CPOL;
ss_n <= {NUMBER_OF_SLAVES{1'b1}};
sclk_toggle_count <= 0;
transaction_toggles <= 0;
spi_clock_phase <= ~CPHA;
incoming_data <= {INCOMING_DATA_WIDTH{1'b0}};
incoming_data_buffer <= {INCOMING_DATA_WIDTH{1'b0}};
outgoing_data_buffer <= {OUTGOING_DATA_WIDTH{1'b0}};
state <= IDLE;
bit_counter <= 0;
byte_counter <= 0;
end
else begin
case(state)
IDLE:
begin
if(enable)
begin
bit_counter <= 0;
byte_counter <= 0;
if(start_transaction)
begin
transaction_toggles <= (operation == READ) ? ALL_READ_TOGGLES : EXTRA_WRITE_SCLK_TOGGLES;
intermediate_buffer = put_data(outgoing_data, BYTES_ORDER);
outgoing_data_buffer <= intermediate_buffer[15:0];
state <= ACTIVE;
end
end
end
ACTIVE:
begin
ss_n[slave] <= 1'b0;
spi_clock_phase <= ~spi_clock_phase;
if(ss_n[slave] == 1'b0)
begin
if(sclk_toggle_count < (OUTGOING_DATA_WIDTH * 2) + transaction_toggles)
begin
sclk <= ~sclk;
sclk_toggle_count <= sclk_toggle_count + 1;
end
end
if(spi_clock_phase == 1'b0)
begin
if(operation == READ)
begin
if(sclk_toggle_count > ((OUTGOING_DATA_WIDTH * 2) + EXTRA_READ_SCLK_TOGGLES)-1)
begin
incoming_data_buffer <= incoming_data_buffer >> 1;
incoming_data_buffer[INCOMING_DATA_WIDTH-1] <= miso;
end
end
end
else
begin
if(sclk_toggle_count < (OUTGOING_DATA_WIDTH * 2) - 1)
begin
if(BITS_ORDER == `LSB_FIRST)
begin
mosi <= outgoing_data_buffer[0]; // posiibly here we are passing BITS ORDER
outgoing_data_buffer <= outgoing_data_buffer >> 1;
end
else
begin
bit_counter <= bit_counter + 1;
mosi <= outgoing_data_buffer[7 - bit_counter];
if(bit_counter == 7)
outgoing_data_buffer <= outgoing_data_buffer >> 8;
end
end
end
if(sclk_toggle_count == (OUTGOING_DATA_WIDTH * 2) + transaction_toggles)
begin
ss_n[slave] <= 1'b1;
mosi <= MOSI_IDLE_VALUE;
incoming_data <= incoming_data_buffer;
incoming_data_buffer <= {INCOMING_DATA_WIDTH{1'b0}};
outgoing_data_buffer <= {OUTGOING_DATA_WIDTH{1'b0}};
sclk <= CPOL;
spi_clock_phase <= ~CPHA;
sclk_toggle_count <= 0;
end_of_transaction <= 1'b1;
state <= WAIT;
end
end
WAIT:
begin
incoming_data <= {INCOMING_DATA_WIDTH{1'b0}};
end_of_transaction <= 1'b0;
state <= IDLE;
end
endcase
end
end
function [`MAX_DATA_WIDTH - 1:0] put_data(input reg [`MAX_DATA_WIDTH - 1 : 0] data, input reg order);
reg [`MAX_DATA_WIDTH - 1:0] result;
reg[7:0] shift;
begin
shift = `MAX_DATA_WIDTH - NUMBER_OF_BYTES * 8;
if (order == `BIG_ENDIAN)//`LITTLE_ENDIAN)
begin
result = {data[7:0], data[15:8], data[23:16], data[31:24], data[39:32], data[47:40], data[55:48], data[63:56]};
if(shift > 0)
put_data = result >> shift;
//put_data[NUMBER_OF_BYTES * 8 - 1 : 0] = result[`MAX_DATA_WIDTH - 1 : `MAX_DATA_WIDTH - NUMBER_OF_BYTES * 8];
else put_data = result;
end
else if (order == `LITTLE_ENDIAN)//`BIG_ENDIAN)
begin
put_data = data;
end
end
endfunction
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// This interface includes both the transmit and receive components -
// They both uses the same clock (sourced from the receiving side).
`timescale 1ns/100ps
module axi_ad9361_dev_if (
// physical interface (receive)
rx_clk_in_p,
rx_clk_in_n,
rx_frame_in_p,
rx_frame_in_n,
rx_data_in_p,
rx_data_in_n,
// physical interface (transmit)
tx_clk_out_p,
tx_clk_out_n,
tx_frame_out_p,
tx_frame_out_n,
tx_data_out_p,
tx_data_out_n,
// clock (common to both receive and transmit)
clk,
// receive data path interface
adc_valid,
adc_data_i1,
adc_data_q1,
adc_data_i2,
adc_data_q2,
adc_status,
adc_r1_mode,
// transmit data path interface
dac_valid,
dac_data_i1,
dac_data_q1,
dac_data_i2,
dac_data_q2,
dac_r1_mode,
// delay control signals
delay_clk,
delay_rst,
delay_sel,
delay_rwn,
delay_addr,
delay_wdata,
delay_rdata,
delay_ack_t,
delay_locked,
// chipscope signals
dev_dbg_trigger,
dev_dbg_data);
// this parameter controls the buffer type based on the target device.
parameter PCORE_BUFTYPE = 0;
parameter PCORE_IODELAY_GROUP = "dev_if_delay_group";
localparam PCORE_7SERIES = 0;
localparam PCORE_VIRTEX6 = 1;
// physical interface (receive)
input rx_clk_in_p;
input rx_clk_in_n;
input rx_frame_in_p;
input rx_frame_in_n;
input [ 5:0] rx_data_in_p;
input [ 5:0] rx_data_in_n;
// physical interface (transmit)
output tx_clk_out_p;
output tx_clk_out_n;
output tx_frame_out_p;
output tx_frame_out_n;
output [ 5:0] tx_data_out_p;
output [ 5:0] tx_data_out_n;
// clock (common to both receive and transmit)
output clk;
// receive data path interface
output adc_valid;
output [11:0] adc_data_i1;
output [11:0] adc_data_q1;
output [11:0] adc_data_i2;
output [11:0] adc_data_q2;
output adc_status;
input adc_r1_mode;
// transmit data path interface
input dac_valid;
input [11:0] dac_data_i1;
input [11:0] dac_data_q1;
input [11:0] dac_data_i2;
input [11:0] dac_data_q2;
input dac_r1_mode;
// delay control signals
input delay_clk;
input delay_rst;
input delay_sel;
input delay_rwn;
input [ 7:0] delay_addr;
input [ 4:0] delay_wdata;
output [ 4:0] delay_rdata;
output delay_ack_t;
output delay_locked;
// chipscope signals
output [ 3:0] dev_dbg_trigger;
output [297:0] dev_dbg_data;
// internal registers
reg [ 5:0] rx_data_n = 'd0;
reg rx_frame_n = 'd0;
reg [11:0] rx_data = 'd0;
reg [ 1:0] rx_frame = 'd0;
reg [11:0] rx_data_d = 'd0;
reg [ 1:0] rx_frame_d = 'd0;
reg rx_error_r1 = 'd0;
reg rx_valid_r1 = 'd0;
reg [11:0] rx_data_i_r1 = 'd0;
reg [11:0] rx_data_q_r1 = 'd0;
reg rx_error_r2 = 'd0;
reg rx_valid_r2 = 'd0;
reg [11:0] rx_data_i1_r2 = 'd0;
reg [11:0] rx_data_q1_r2 = 'd0;
reg [11:0] rx_data_i2_r2 = 'd0;
reg [11:0] rx_data_q2_r2 = 'd0;
reg adc_valid = 'd0;
reg [11:0] adc_data_i1 = 'd0;
reg [11:0] adc_data_q1 = 'd0;
reg [11:0] adc_data_i2 = 'd0;
reg [11:0] adc_data_q2 = 'd0;
reg adc_status = 'd0;
reg [ 2:0] tx_data_cnt = 'd0;
reg [11:0] tx_data_i1_d = 'd0;
reg [11:0] tx_data_q1_d = 'd0;
reg [11:0] tx_data_i2_d = 'd0;
reg [11:0] tx_data_q2_d = 'd0;
reg tx_frame = 'd0;
reg [ 5:0] tx_data_p = 'd0;
reg [ 5:0] tx_data_n = 'd0;
reg [ 6:0] delay_ld = 'd0;
reg [ 4:0] delay_rdata = 'd0;
reg delay_ack_t = 'd0;
// internal signals
wire [ 3:0] rx_frame_s;
wire [ 3:0] tx_data_sel_s;
wire [ 4:0] delay_rdata_s[6:0];
wire [ 5:0] rx_data_ibuf_s;
wire [ 5:0] rx_data_idelay_s;
wire [ 5:0] rx_data_p_s;
wire [ 5:0] rx_data_n_s;
wire rx_frame_ibuf_s;
wire rx_frame_idelay_s;
wire rx_frame_p_s;
wire rx_frame_n_s;
wire [ 5:0] tx_data_oddr_s;
wire tx_frame_oddr_s;
wire tx_clk_oddr_s;
wire clk_ibuf_s;
genvar l_inst;
// device debug signals
assign dev_dbg_trigger[0] = rx_frame[0];
assign dev_dbg_trigger[1] = rx_frame[1];
assign dev_dbg_trigger[2] = tx_frame;
assign dev_dbg_trigger[3] = adc_status;
assign dev_dbg_data[ 5: 0] = tx_data_n;
assign dev_dbg_data[ 11: 6] = tx_data_p;
assign dev_dbg_data[ 23: 12] = tx_data_i1_d;
assign dev_dbg_data[ 35: 24] = tx_data_q1_d;
assign dev_dbg_data[ 47: 36] = tx_data_i2_d;
assign dev_dbg_data[ 59: 48] = tx_data_q2_d;
assign dev_dbg_data[ 63: 60] = tx_data_sel_s;
assign dev_dbg_data[ 66: 64] = tx_data_cnt;
assign dev_dbg_data[ 67: 67] = tx_frame;
assign dev_dbg_data[ 68: 68] = dac_r1_mode;
assign dev_dbg_data[ 69: 69] = dac_valid;
assign dev_dbg_data[ 81: 70] = dac_data_i1;
assign dev_dbg_data[ 93: 82] = dac_data_q1;
assign dev_dbg_data[105: 94] = dac_data_i2;
assign dev_dbg_data[117:106] = dac_data_q2;
assign dev_dbg_data[118:118] = rx_frame_p_s;
assign dev_dbg_data[119:119] = rx_frame_n_s;
assign dev_dbg_data[120:120] = rx_frame_n;
assign dev_dbg_data[122:121] = rx_frame;
assign dev_dbg_data[124:123] = rx_frame_d;
assign dev_dbg_data[128:125] = rx_frame_s;
assign dev_dbg_data[134:129] = rx_data_p_s;
assign dev_dbg_data[140:135] = rx_data_n_s;
assign dev_dbg_data[146:141] = rx_data_n;
assign dev_dbg_data[158:147] = rx_data;
assign dev_dbg_data[170:159] = rx_data_d;
assign dev_dbg_data[171:171] = rx_error_r1;
assign dev_dbg_data[172:172] = rx_valid_r1;
assign dev_dbg_data[184:173] = rx_data_i_r1;
assign dev_dbg_data[196:185] = rx_data_q_r1;
assign dev_dbg_data[197:197] = rx_error_r2;
assign dev_dbg_data[198:198] = rx_valid_r2;
assign dev_dbg_data[210:199] = rx_data_i1_r2;
assign dev_dbg_data[222:211] = rx_data_q1_r2;
assign dev_dbg_data[234:223] = rx_data_i2_r2;
assign dev_dbg_data[246:235] = rx_data_q2_r2;
assign dev_dbg_data[247:247] = adc_r1_mode;
assign dev_dbg_data[248:248] = adc_status;
assign dev_dbg_data[249:249] = adc_valid;
assign dev_dbg_data[261:250] = adc_data_i1;
assign dev_dbg_data[273:262] = adc_data_q1;
assign dev_dbg_data[285:274] = adc_data_i2;
assign dev_dbg_data[297:286] = adc_data_q2;
// receive data path interface
assign rx_frame_s = {rx_frame_d, rx_frame};
always @(posedge clk) begin
rx_data_n <= rx_data_n_s;
rx_frame_n <= rx_frame_n_s;
rx_data <= {rx_data_n, rx_data_p_s};
rx_frame <= {rx_frame_n, rx_frame_p_s};
rx_data_d <= rx_data;
rx_frame_d <= rx_frame;
end
// receive data path for single rf, frame is expected to qualify i/q msb only
always @(posedge clk) begin
rx_error_r1 <= ((rx_frame_s == 4'b1100) || (rx_frame_s == 4'b0011)) ? 1'b0 : 1'b1;
rx_valid_r1 <= (rx_frame_s == 4'b1100) ? 1'b1 : 1'b0;
if (rx_frame_s == 4'b1100) begin
rx_data_i_r1 <= {rx_data_d[11:6], rx_data[11:6]};
rx_data_q_r1 <= {rx_data_d[ 5:0], rx_data[ 5:0]};
end
end
// receive data path for dual rf, frame is expected to qualify i/q msb and lsb for rf-1 only
always @(posedge clk) begin
rx_error_r2 <= ((rx_frame_s == 4'b1111) || (rx_frame_s == 4'b1100) ||
(rx_frame_s == 4'b0000) || (rx_frame_s == 4'b0011)) ? 1'b0 : 1'b1;
rx_valid_r2 <= (rx_frame_s == 4'b0000) ? 1'b1 : 1'b0;
if (rx_frame_s == 4'b1111) begin
rx_data_i1_r2 <= {rx_data_d[11:6], rx_data[11:6]};
rx_data_q1_r2 <= {rx_data_d[ 5:0], rx_data[ 5:0]};
end
if (rx_frame_s == 4'b0000) begin
rx_data_i2_r2 <= {rx_data_d[11:6], rx_data[11:6]};
rx_data_q2_r2 <= {rx_data_d[ 5:0], rx_data[ 5:0]};
end
end
// receive data path mux
always @(posedge clk) begin
if (adc_r1_mode == 1'b1) begin
adc_valid <= rx_valid_r1;
adc_data_i1 <= rx_data_i_r1;
adc_data_q1 <= rx_data_q_r1;
adc_data_i2 <= 12'd0;
adc_data_q2 <= 12'd0;
adc_status <= ~rx_error_r1;
end else begin
adc_valid <= rx_valid_r2;
adc_data_i1 <= rx_data_i1_r2;
adc_data_q1 <= rx_data_q1_r2;
adc_data_i2 <= rx_data_i2_r2;
adc_data_q2 <= rx_data_q2_r2;
adc_status <= ~rx_error_r2;
end
end
// transmit data path mux (reverse of what receive does above)
// the count simply selets the data muxing on the ddr outputs
assign tx_data_sel_s = {tx_data_cnt[2], dac_r1_mode, tx_data_cnt[1:0]};
always @(posedge clk) begin
if (dac_valid == 1'b1) begin
tx_data_cnt <= 3'b100;
end else if (tx_data_cnt[2] == 1'b1) begin
tx_data_cnt <= tx_data_cnt + 1'b1;
end
if (dac_valid == 1'b1) begin
tx_data_i1_d <= dac_data_i1;
tx_data_q1_d <= dac_data_q1;
tx_data_i2_d <= dac_data_i2;
tx_data_q2_d <= dac_data_q2;
end
case (tx_data_sel_s)
4'b1111: begin
tx_frame <= 1'b0;
tx_data_p <= tx_data_i1_d[ 5:0];
tx_data_n <= tx_data_q1_d[ 5:0];
end
4'b1110: begin
tx_frame <= 1'b1;
tx_data_p <= tx_data_i1_d[11:6];
tx_data_n <= tx_data_q1_d[11:6];
end
4'b1101: begin
tx_frame <= 1'b0;
tx_data_p <= tx_data_i1_d[ 5:0];
tx_data_n <= tx_data_q1_d[ 5:0];
end
4'b1100: begin
tx_frame <= 1'b1;
tx_data_p <= tx_data_i1_d[11:6];
tx_data_n <= tx_data_q1_d[11:6];
end
4'b1011: begin
tx_frame <= 1'b0;
tx_data_p <= tx_data_i2_d[ 5:0];
tx_data_n <= tx_data_q2_d[ 5:0];
end
4'b1010: begin
tx_frame <= 1'b0;
tx_data_p <= tx_data_i2_d[11:6];
tx_data_n <= tx_data_q2_d[11:6];
end
4'b1001: begin
tx_frame <= 1'b1;
tx_data_p <= tx_data_i1_d[ 5:0];
tx_data_n <= tx_data_q1_d[ 5:0];
end
4'b1000: begin
tx_frame <= 1'b1;
tx_data_p <= tx_data_i1_d[11:6];
tx_data_n <= tx_data_q1_d[11:6];
end
default: begin
tx_frame <= 1'b0;
tx_data_p <= 6'd0;
tx_data_n <= 6'd0;
end
endcase
end
// delay write interface, each delay element can be individually
// addressed, and a delay value can be directly loaded (no inc/dec stuff)
always @(posedge delay_clk) begin
if ((delay_sel == 1'b1) && (delay_rwn == 1'b0)) begin
case (delay_addr)
8'h06: delay_ld <= 7'h40;
8'h05: delay_ld <= 7'h20;
8'h04: delay_ld <= 7'h10;
8'h03: delay_ld <= 7'h08;
8'h02: delay_ld <= 7'h04;
8'h01: delay_ld <= 7'h02;
8'h00: delay_ld <= 7'h01;
default: delay_ld <= 7'h00;
endcase
end else begin
delay_ld <= 7'h00;
end
end
// delay read interface, a delay ack toggle is used to transfer data to the
// processor side- delay locked is independently transferred
always @(posedge delay_clk) begin
case (delay_addr)
8'h06: delay_rdata <= delay_rdata_s[6];
8'h05: delay_rdata <= delay_rdata_s[5];
8'h04: delay_rdata <= delay_rdata_s[4];
8'h03: delay_rdata <= delay_rdata_s[3];
8'h02: delay_rdata <= delay_rdata_s[2];
8'h01: delay_rdata <= delay_rdata_s[1];
8'h00: delay_rdata <= delay_rdata_s[0];
default: delay_rdata <= 5'd0;
endcase
if (delay_sel == 1'b1) begin
delay_ack_t <= ~delay_ack_t;
end
end
// delay controller
(* IODELAY_GROUP = PCORE_IODELAY_GROUP *)
IDELAYCTRL i_delay_ctrl (
.RST (delay_rst),
.REFCLK (delay_clk),
.RDY (delay_locked));
// receive data interface, ibuf -> idelay -> iddr
generate
for (l_inst = 0; l_inst <= 5; l_inst = l_inst + 1) begin: g_rx_data
IBUFDS i_rx_data_ibuf (
.I (rx_data_in_p[l_inst]),
.IB (rx_data_in_n[l_inst]),
.O (rx_data_ibuf_s[l_inst]));
if (PCORE_BUFTYPE == PCORE_VIRTEX6) begin
(* IODELAY_GROUP = PCORE_IODELAY_GROUP *)
IODELAYE1 #(
.CINVCTRL_SEL ("FALSE"),
.DELAY_SRC ("I"),
.HIGH_PERFORMANCE_MODE ("TRUE"),
.IDELAY_TYPE ("VAR_LOADABLE"),
.IDELAY_VALUE (0),
.ODELAY_TYPE ("FIXED"),
.ODELAY_VALUE (0),
.REFCLK_FREQUENCY (200.0),
.SIGNAL_PATTERN ("DATA"))
i_rx_data_idelay (
.T (1'b1),
.CE (1'b0),
.INC (1'b0),
.CLKIN (1'b0),
.DATAIN (1'b0),
.ODATAIN (1'b0),
.CINVCTRL (1'b0),
.C (delay_clk),
.IDATAIN (rx_data_ibuf_s[l_inst]),
.DATAOUT (rx_data_idelay_s[l_inst]),
.RST (delay_ld[l_inst]),
.CNTVALUEIN (delay_wdata),
.CNTVALUEOUT (delay_rdata_s[l_inst]));
end else begin
(* IODELAY_GROUP = PCORE_IODELAY_GROUP *)
IDELAYE2 #(
.CINVCTRL_SEL ("FALSE"),
.DELAY_SRC ("IDATAIN"),
.HIGH_PERFORMANCE_MODE ("FALSE"),
.IDELAY_TYPE ("VAR_LOAD"),
.IDELAY_VALUE (0),
.REFCLK_FREQUENCY (200.0),
.PIPE_SEL ("FALSE"),
.SIGNAL_PATTERN ("DATA"))
i_rx_data_idelay (
.CE (1'b0),
.INC (1'b0),
.DATAIN (1'b0),
.LDPIPEEN (1'b0),
.CINVCTRL (1'b0),
.REGRST (1'b0),
.C (delay_clk),
.IDATAIN (rx_data_ibuf_s[l_inst]),
.DATAOUT (rx_data_idelay_s[l_inst]),
.LD (delay_ld[l_inst]),
.CNTVALUEIN (delay_wdata),
.CNTVALUEOUT (delay_rdata_s[l_inst]));
end
IDDR #(
.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"),
.INIT_Q1 (1'b0),
.INIT_Q2 (1'b0),
.SRTYPE ("ASYNC"))
i_rx_data_iddr (
.CE (1'b1),
.R (1'b0),
.S (1'b0),
.C (clk),
.D (rx_data_idelay_s[l_inst]),
.Q1 (rx_data_p_s[l_inst]),
.Q2 (rx_data_n_s[l_inst]));
end
endgenerate
// receive frame interface, ibuf -> idelay -> iddr
IBUFDS i_rx_frame_ibuf (
.I (rx_frame_in_p),
.IB (rx_frame_in_n),
.O (rx_frame_ibuf_s));
generate
if (PCORE_BUFTYPE == PCORE_VIRTEX6) begin
(* IODELAY_GROUP = PCORE_IODELAY_GROUP *)
IODELAYE1 #(
.CINVCTRL_SEL ("FALSE"),
.DELAY_SRC ("I"),
.HIGH_PERFORMANCE_MODE ("TRUE"),
.IDELAY_TYPE ("VAR_LOADABLE"),
.IDELAY_VALUE (0),
.ODELAY_TYPE ("FIXED"),
.ODELAY_VALUE (0),
.REFCLK_FREQUENCY (200.0),
.SIGNAL_PATTERN ("DATA"))
i_rx_frame_idelay (
.T (1'b1),
.CE (1'b0),
.INC (1'b0),
.CLKIN (1'b0),
.DATAIN (1'b0),
.ODATAIN (1'b0),
.CINVCTRL (1'b0),
.C (delay_clk),
.IDATAIN (rx_frame_ibuf_s),
.DATAOUT (rx_frame_idelay_s),
.RST (delay_ld[6]),
.CNTVALUEIN (delay_wdata),
.CNTVALUEOUT (delay_rdata_s[6]));
end else begin
(* IODELAY_GROUP = PCORE_IODELAY_GROUP *)
IDELAYE2 #(
.CINVCTRL_SEL ("FALSE"),
.DELAY_SRC ("IDATAIN"),
.HIGH_PERFORMANCE_MODE ("FALSE"),
.IDELAY_TYPE ("VAR_LOAD"),
.IDELAY_VALUE (0),
.REFCLK_FREQUENCY (200.0),
.PIPE_SEL ("FALSE"),
.SIGNAL_PATTERN ("DATA"))
i_rx_frame_idelay (
.CE (1'b0),
.INC (1'b0),
.DATAIN (1'b0),
.LDPIPEEN (1'b0),
.CINVCTRL (1'b0),
.REGRST (1'b0),
.C (delay_clk),
.IDATAIN (rx_frame_ibuf_s),
.DATAOUT (rx_frame_idelay_s),
.LD (delay_ld[6]),
.CNTVALUEIN (delay_wdata),
.CNTVALUEOUT (delay_rdata_s[6]));
end
endgenerate
IDDR #(
.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"),
.INIT_Q1 (1'b0),
.INIT_Q2 (1'b0),
.SRTYPE ("ASYNC"))
i_rx_frame_iddr (
.CE (1'b1),
.R (1'b0),
.S (1'b0),
.C (clk),
.D (rx_frame_idelay_s),
.Q1 (rx_frame_p_s),
.Q2 (rx_frame_n_s));
// transmit data interface, oddr -> obuf
generate
for (l_inst = 0; l_inst <= 5; l_inst = l_inst + 1) begin: g_tx_data
ODDR #(
.DDR_CLK_EDGE ("SAME_EDGE"),
.INIT (1'b0),
.SRTYPE ("ASYNC"))
i_tx_data_oddr (
.CE (1'b1),
.R (1'b0),
.S (1'b0),
.C (clk),
.D1 (tx_data_p[l_inst]),
.D2 (tx_data_n[l_inst]),
.Q (tx_data_oddr_s[l_inst]));
OBUFDS i_tx_data_obuf (
.I (tx_data_oddr_s[l_inst]),
.O (tx_data_out_p[l_inst]),
.OB (tx_data_out_n[l_inst]));
end
endgenerate
// transmit frame interface, oddr -> obuf
ODDR #(
.DDR_CLK_EDGE ("SAME_EDGE"),
.INIT (1'b0),
.SRTYPE ("ASYNC"))
i_tx_frame_oddr (
.CE (1'b1),
.R (1'b0),
.S (1'b0),
.C (clk),
.D1 (tx_frame),
.D2 (tx_frame),
.Q (tx_frame_oddr_s));
OBUFDS i_tx_frame_obuf (
.I (tx_frame_oddr_s),
.O (tx_frame_out_p),
.OB (tx_frame_out_n));
// transmit clock interface, oddr -> obuf
ODDR #(
.DDR_CLK_EDGE ("SAME_EDGE"),
.INIT (1'b0),
.SRTYPE ("ASYNC"))
i_tx_clk_oddr (
.CE (1'b1),
.R (1'b0),
.S (1'b0),
.C (clk),
.D1 (1'b0),
.D2 (1'b1),
.Q (tx_clk_oddr_s));
OBUFDS i_tx_clk_obuf (
.I (tx_clk_oddr_s),
.O (tx_clk_out_p),
.OB (tx_clk_out_n));
// device clock interface (receive clock)
IBUFGDS i_rx_clk_ibuf (
.I (rx_clk_in_p),
.IB (rx_clk_in_n),
.O (clk_ibuf_s));
BUFG i_clk_gbuf (
.I (clk_ibuf_s),
.O (clk));
endmodule
// ***************************************************************************
// ***************************************************************************
|
`timescale 1 ns / 1 ps
`default_nettype none
`define WIDTH 32
module j1b(input wire clk,
input wire resetq,
output wire uart0_wr,
output wire uart0_rd,
output wire [7:0] uart_w,
input wire uart0_valid,
input wire [7:0] uart0_data
);
wire io_rd, io_wr;
wire [15:0] mem_addr;
wire mem_wr;
reg [31:0] mem_din;
wire [31:0] dout;
wire [31:0] io_din;
wire [12:0] code_addr;
wire [15:0] insn;
wire [12:0] codeaddr = {1'b0, code_addr[12:1]};
reg [31:0] ram[0:8191] /* verilator public_flat */;
always @(posedge clk) begin
// $display("pc=%x", code_addr * 2);
insn <= code_addr[0] ? ram[codeaddr][31:16] : ram[codeaddr][15:0];
if (mem_wr)
ram[mem_addr[14:2]] <= dout;
mem_din <= ram[mem_addr[14:2]];
end
j1 _j1(
.clk(clk),
.resetq(resetq),
.io_rd(io_rd),
.io_wr(io_wr),
.mem_wr(mem_wr),
.dout(dout),
.mem_din(mem_din),
.io_din(io_din),
.mem_addr(mem_addr),
.code_addr(code_addr),
.insn(insn));
// ###### IO SIGNALS ####################################
reg io_wr_, io_rd_;
/* verilator lint_off UNUSED */
reg [31:0] dout_;
reg [15:0] io_addr_;
/* verilator lint_on UNUSED */
always @(posedge clk) begin
{io_rd_, io_wr_, dout_} <= {io_rd, io_wr, dout};
if (io_rd | io_wr)
io_addr_ <= mem_addr;
end
// ###### UART ##########################################
wire uart0_wr = io_wr_ & io_addr_[12];
wire uart0_rd = io_rd_ & io_addr_[12];
assign uart_w = dout_[7:0];
// always @(posedge clk) begin
// if (uart0_wr)
// $display("--- out %x %c", uart_w, uart_w);
// if (uart0_rd)
// $display("--- in %x %c", uart0_data, uart0_data);
// end
// ###### IO PORTS ######################################
/* bit READ WRITE
1000 12 UART RX UART TX
2000 13 misc.in
*/
assign io_din =
(io_addr_[12] ? {24'd0, uart0_data} : 32'd0) |
(io_addr_[13] ? {28'd0, 1'b0, 1'b0, uart0_valid, 1'b1} : 32'd0);
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Round-Robin Arbiter for R and B channel responses
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// arbiter_resp
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_arbiter_resp #
(
parameter C_FAMILY = "none",
parameter integer C_NUM_S = 4, // Number of requesting Slave ports = [2:16]
parameter integer C_NUM_S_LOG = 2, // Log2(C_NUM_S)
parameter integer C_GRANT_ENC = 0, // Enable encoded grant output
parameter integer C_GRANT_HOT = 1 // Enable 1-hot grant output
)
(
// Global Inputs
input wire ACLK,
input wire ARESET,
// Slave Ports
input wire [C_NUM_S-1:0] S_VALID, // Request from each slave
output wire [C_NUM_S-1:0] S_READY, // Grant response to each slave
// Master Ports
output wire [C_NUM_S_LOG-1:0] M_GRANT_ENC, // Granted slave index (encoded)
output wire [C_NUM_S-1:0] M_GRANT_HOT, // Granted slave index (1-hot)
output wire M_VALID, // Grant event
input wire M_READY
);
// Generates a binary coded from onehotone encoded
function [4:0] f_hot2enc
(
input [16:0] one_hot
);
begin
f_hot2enc[0] = |(one_hot & 17'b01010101010101010);
f_hot2enc[1] = |(one_hot & 17'b01100110011001100);
f_hot2enc[2] = |(one_hot & 17'b01111000011110000);
f_hot2enc[3] = |(one_hot & 17'b01111111100000000);
f_hot2enc[4] = |(one_hot & 17'b10000000000000000);
end
endfunction
(* use_clock_enable = "yes" *)
reg [C_NUM_S-1:0] chosen;
wire [C_NUM_S-1:0] grant_hot;
wire master_selected;
wire active_master;
wire need_arbitration;
wire m_valid_i;
wire [C_NUM_S-1:0] s_ready_i;
wire access_done;
reg [C_NUM_S-1:0] last_rr_hot;
wire [C_NUM_S-1:0] valid_rr;
reg [C_NUM_S-1:0] next_rr_hot;
reg [C_NUM_S*C_NUM_S-1:0] carry_rr;
reg [C_NUM_S*C_NUM_S-1:0] mask_rr;
integer i;
integer j;
integer n;
/////////////////////////////////////////////////////////////////////////////
//
// Implementation of the arbiter outputs independant of arbitration
//
/////////////////////////////////////////////////////////////////////////////
// Mask the current requests with the chosen master
assign grant_hot = chosen & S_VALID;
// See if we have a selected master
assign master_selected = |grant_hot[0+:C_NUM_S];
// See if we have current requests
assign active_master = |S_VALID;
// Access is completed
assign access_done = m_valid_i & M_READY;
// Need to handle if we drive S_ready combinatorial and without an IDLE state
// Drive S_READY on the master who has been chosen when we get a M_READY
assign s_ready_i = {C_NUM_S{M_READY}} & grant_hot[0+:C_NUM_S];
// Drive M_VALID if we have a selected master
assign m_valid_i = master_selected;
// If we have request and not a selected master, we need to arbitrate a new chosen
assign need_arbitration = (active_master & ~master_selected) | access_done;
// need internal signals of the output signals
assign M_VALID = m_valid_i;
assign S_READY = s_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Assign conditional onehot target output signal.
assign M_GRANT_HOT = (C_GRANT_HOT == 1) ? grant_hot[0+:C_NUM_S] : {C_NUM_S{1'b0}};
/////////////////////////////////////////////////////////////////////////////
// Assign conditional encoded target output signal.
assign M_GRANT_ENC = (C_GRANT_ENC == 1) ? f_hot2enc(grant_hot) : {C_NUM_S_LOG{1'b0}};
/////////////////////////////////////////////////////////////////////////////
// Select a new chosen when we need to arbitrate
// If we don't have a new chosen, keep the old one since it's a good chance
// that it will do another request
always @(posedge ACLK)
begin
if (ARESET) begin
chosen <= {C_NUM_S{1'b0}};
last_rr_hot <= {1'b1, {C_NUM_S-1{1'b0}}};
end else if (need_arbitration) begin
chosen <= next_rr_hot;
if (|next_rr_hot) last_rr_hot <= next_rr_hot;
end
end
assign valid_rr = S_VALID;
/////////////////////////////////////////////////////////////////////////////
// Round-robin arbiter
// Selects next request to grant from among inputs with PRIO = 0, if any.
/////////////////////////////////////////////////////////////////////////////
always @ * begin
next_rr_hot = 0;
for (i=0;i<C_NUM_S;i=i+1) begin
n = (i>0) ? (i-1) : (C_NUM_S-1);
carry_rr[i*C_NUM_S] = last_rr_hot[n];
mask_rr[i*C_NUM_S] = ~valid_rr[n];
for (j=1;j<C_NUM_S;j=j+1) begin
n = (i-j > 0) ? (i-j-1) : (C_NUM_S+i-j-1);
carry_rr[i*C_NUM_S+j] = carry_rr[i*C_NUM_S+j-1] | (last_rr_hot[n] & mask_rr[i*C_NUM_S+j-1]);
if (j < C_NUM_S-1) begin
mask_rr[i*C_NUM_S+j] = mask_rr[i*C_NUM_S+j-1] & ~valid_rr[n];
end
end
next_rr_hot[i] = valid_rr[i] & carry_rr[(i+1)*C_NUM_S-1];
end
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
module axi_register_slice (
input clk,
input resetn,
input s_axi_valid,
output s_axi_ready,
input [DATA_WIDTH-1:0] s_axi_data,
output m_axi_valid,
input m_axi_ready,
output [DATA_WIDTH-1:0] m_axi_data
);
parameter DATA_WIDTH = 32;
parameter FORWARD_REGISTERED = 0;
parameter BACKWARD_REGISTERED = 0;
/*
s_axi_data -> bwd_data -> fwd_data(1) -> m_axi_data
s_axi_valid -> bwd_valid -> fwd_valid(1) -> m_axi_valid
s_axi_ready <- bwd_ready(2) <- fwd_ready <- m_axi_ready
(1) FORWARD_REGISTERED inserts a set of FF before m_axi_data and m_axi_valid
(2) BACKWARD_REGISTERED insters a FF before s_axi_ready
*/
wire [DATA_WIDTH-1:0] bwd_data_s;
wire bwd_valid_s;
wire bwd_ready_s;
wire [DATA_WIDTH-1:0] fwd_data_s;
wire fwd_valid_s;
wire fwd_ready_s;
generate if (FORWARD_REGISTERED == 1) begin
reg fwd_valid = 1'b0;
reg [DATA_WIDTH-1:0] fwd_data = 'h00;
assign fwd_ready_s = ~fwd_valid | m_axi_ready;
assign fwd_valid_s = fwd_valid;
assign fwd_data_s = fwd_data;
always @(posedge clk) begin
if (~fwd_valid | m_axi_ready)
fwd_data <= bwd_data_s;
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
fwd_valid <= 1'b0;
end else begin
if (bwd_valid_s)
fwd_valid <= 1'b1;
else if (m_axi_ready)
fwd_valid <= 1'b0;
end
end
end else begin
assign fwd_data_s = bwd_data_s;
assign fwd_valid_s = bwd_valid_s;
assign fwd_ready_s = m_axi_ready;
end
endgenerate
generate if (BACKWARD_REGISTERED == 1) begin
reg bwd_ready = 1'b1;
reg [DATA_WIDTH-1:0] bwd_data = 'h00;
assign bwd_valid_s = ~bwd_ready | s_axi_valid;
assign bwd_data_s = bwd_ready ? s_axi_data : bwd_data;
assign bwd_ready_s = bwd_ready;
always @(posedge clk) begin
if (bwd_ready)
bwd_data <= s_axi_data;
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
bwd_ready <= 1'b1;
end else begin
if (fwd_ready_s)
bwd_ready <= 1'b1;
else if (s_axi_valid)
bwd_ready <= 1'b0;
end
end
end else begin
assign bwd_valid_s = s_axi_valid;
assign bwd_data_s = s_axi_data;
assign bwd_ready_s = fwd_ready_s;
end endgenerate
assign m_axi_data = fwd_data_s;
assign m_axi_valid = fwd_valid_s;
assign s_axi_ready = bwd_ready_s;
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: iodelay_ctrl.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:34:56 $
// \ \ / \ Date Created: Wed Aug 16 2006
// \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
// This module instantiates the IDELAYCTRL primitive, which continously
// calibrates the IODELAY elements in the region to account for varying
// environmental conditions. A 200MHz or 300MHz reference clock (depending
// on the desired IODELAY tap resolution) must be supplied
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: iodelay_ctrl.v,v 1.1 2011/06/02 08:34:56 mishra Exp $
**$Date: 2011/06/02 08:34:56 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/clocking/iodelay_ctrl.v,v $
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v1_9_iodelay_ctrl #
(
parameter TCQ = 100,
// clk->out delay (sim only)
parameter IODELAY_GRP = "IODELAY_MIG",
// May be assigned unique name when
// multiple IP cores used in design
parameter REFCLK_TYPE = "DIFFERENTIAL",
// Reference clock type
// "DIFFERENTIAL","SINGLE_ENDED"
// NO_BUFFER, USE_SYSTEM_CLOCK
parameter SYSCLK_TYPE = "DIFFERENTIAL",
// input clock type
// DIFFERENTIAL, SINGLE_ENDED,
// NO_BUFFER
parameter SYS_RST_PORT = "FALSE",
// "TRUE" - if pin is selected for sys_rst
// and IBUF will be instantiated.
// "FALSE" - if pin is not selected for sys_rst
parameter RST_ACT_LOW = 1,
// Reset input polarity
// (0 = active high, 1 = active low)
parameter DIFF_TERM_REFCLK = "TRUE"
// Differential Termination
)
(
input clk_ref_p,
input clk_ref_n,
input clk_ref_i,
input sys_rst,
output clk_ref,
output sys_rst_o,
output iodelay_ctrl_rdy
);
// # of clock cycles to delay deassertion of reset. Needs to be a fairly
// high number not so much for metastability protection, but to give time
// for reset (i.e. stable clock cycles) to propagate through all state
// machines and to all control signals (i.e. not all control signals have
// resets, instead they rely on base state logic being reset, and the effect
// of that reset propagating through the logic). Need this because we may not
// be getting stable clock cycles while reset asserted (i.e. since reset
// depends on DCM lock status)
// COMMENTED, RC, 01/13/09 - causes pack error in MAP w/ larger #
localparam RST_SYNC_NUM = 15;
// localparam RST_SYNC_NUM = 25;
wire clk_ref_bufg;
wire clk_ref_ibufg;
wire rst_ref;
(* keep = "true", max_fanout = 10 *) reg [RST_SYNC_NUM-1:0] rst_ref_sync_r /* synthesis syn_maxfan = 10 */;
wire rst_tmp_idelay;
wire sys_rst_act_hi;
//***************************************************************************
// If the pin is selected for sys_rst in GUI, IBUF will be instantiated.
// If the pin is not selected in GUI, sys_rst signal is expected to be
// driven internally.
generate
if (SYS_RST_PORT == "TRUE")
IBUF u_sys_rst_ibuf
(
.I (sys_rst),
.O (sys_rst_o)
);
else
assign sys_rst_o = sys_rst;
endgenerate
// Possible inversion of system reset as appropriate
assign sys_rst_act_hi = RST_ACT_LOW ? ~sys_rst_o: sys_rst_o;
//***************************************************************************
// 1) Input buffer for IDELAYCTRL reference clock - handle either a
// differential or single-ended input. Global clock buffer is used to
// drive the rest of FPGA logic.
// 2) For NO_BUFFER option, Reference clock will be driven from internal
// clock i.e., clock is driven from fabric. Input buffers and Global
// clock buffers will not be instaitaed.
// 3) For USE_SYSTEM_CLOCK, input buffer output of system clock will be used
// as the input reference clock. Global clock buffer is used to drive
// the rest of FPGA logic.
//***************************************************************************
generate
if (REFCLK_TYPE == "DIFFERENTIAL") begin: diff_clk_ref
IBUFGDS #
(
.DIFF_TERM (DIFF_TERM_REFCLK),
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_clk_ref
(
.I (clk_ref_p),
.IB (clk_ref_n),
.O (clk_ref_ibufg)
);
BUFG u_bufg_clk_ref
(
.O (clk_ref_bufg),
.I (clk_ref_ibufg)
);
end else if (REFCLK_TYPE == "SINGLE_ENDED") begin : se_clk_ref
IBUFG #
(
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_clk_ref
(
.I (clk_ref_i),
.O (clk_ref_ibufg)
);
BUFG u_bufg_clk_ref
(
.O (clk_ref_bufg),
.I (clk_ref_ibufg)
);
end else if ((REFCLK_TYPE == "NO_BUFFER") ||
(REFCLK_TYPE == "USE_SYSTEM_CLOCK" && SYSCLK_TYPE == "NO_BUFFER")) begin : clk_ref_noibuf_nobuf
assign clk_ref_bufg = clk_ref_i;
end else if (REFCLK_TYPE == "USE_SYSTEM_CLOCK" && SYSCLK_TYPE != "NO_BUFFER") begin : clk_ref_noibuf
BUFG u_bufg_clk_ref
(
.O (clk_ref_bufg),
.I (clk_ref_i)
);
end
endgenerate
//***************************************************************************
// Global clock buffer for IDELAY reference clock
//***************************************************************************
assign clk_ref = clk_ref_bufg;
//*****************************************************************
// IDELAYCTRL reset
// This assumes an external clock signal driving the IDELAYCTRL
// blocks. Otherwise, if a PLL drives IDELAYCTRL, then the PLL
// lock signal will need to be incorporated in this.
//*****************************************************************
// Add PLL lock if PLL drives IDELAYCTRL in user design
assign rst_tmp_idelay = sys_rst_act_hi;
always @(posedge clk_ref_bufg or posedge rst_tmp_idelay)
if (rst_tmp_idelay)
rst_ref_sync_r <= #TCQ {RST_SYNC_NUM{1'b1}};
else
rst_ref_sync_r <= #TCQ rst_ref_sync_r << 1;
assign rst_ref = rst_ref_sync_r[RST_SYNC_NUM-1];
//*****************************************************************
(* IODELAY_GROUP = IODELAY_GRP *) IDELAYCTRL u_idelayctrl
(
.RDY (iodelay_ctrl_rdy),
.REFCLK (clk_ref_bufg),
.RST (rst_ref)
);
endmodule
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`ifdef OVL_ASSERT_ON
wire xzcheck_enable;
`ifdef OVL_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
assign xzcheck_enable = 1'b1;
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
generate
case (property_type)
`OVL_ASSERT_2STATE,
`OVL_ASSERT: begin: assert_checks
assert_zero_one_hot_assert #(
.width(width))
assert_zero_one_hot_assert (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr),
.xzcheck_enable(xzcheck_enable));
end
`OVL_ASSUME_2STATE,
`OVL_ASSUME: begin: assume_checks
assert_zero_one_hot_assume #(
.width(width))
assert_zero_one_hot_assume (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr),
.xzcheck_enable(xzcheck_enable));
end
`OVL_IGNORE: begin: ovl_ignore
//do nothing
end
default: initial ovl_error_t(`OVL_FIRE_2STATE,"");
endcase
endgenerate
`endif
`ifdef OVL_COVER_ON
wire [width-1:0] test_expr_1 = test_expr - {{width-1{1'b0}},1'b1};
reg [width-1:0] one_hots_checked;
always @(posedge clk)
if (`OVL_RESET_SIGNAL != 1'b1)
one_hots_checked <= {width{1'b0}};
else //check for known driven and zero one hot test_expr and update one_hots_checked
one_hots_checked <= ((test_expr ^ test_expr)=={width{1'b0}}) && ((test_expr & test_expr_1) == {width{1'b0}}) ?
one_hots_checked | test_expr : one_hots_checked;
wire all_one_hots_checked;
assign all_one_hots_checked = (one_hots_checked == {width{1'b1}});
generate
if (coverage_level != `OVL_COVER_NONE)
begin: cover_checks
assert_zero_one_hot_cover #(
.width(width),
.OVL_COVER_SANITY_ON(OVL_COVER_SANITY_ON),
.OVL_COVER_CORNER_ON(OVL_COVER_CORNER_ON))
assert_zero_one_hot_cover (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr),
.all_one_hots_checked(all_one_hots_checked));
end
endgenerate
`endif
`endmodule //Required to pair up with already used "`module" in file assert_zero_one_hot.vlib
//Module to be replicated for assert checks
//This module is bound to the PSL vunits with assert checks
module assert_zero_one_hot_assert (clk, reset_n, test_expr, xzcheck_enable);
parameter width = 1;
input clk, reset_n, xzcheck_enable;
input [width-1:0] test_expr;
endmodule
//Module to be replicated for assume checks
//This module is bound to a PSL vunits with assume checks
module assert_zero_one_hot_assume (clk, reset_n, test_expr, xzcheck_enable);
parameter width = 1;
input clk, reset_n, xzcheck_enable;
input [width-1:0] test_expr;
endmodule
//Module to be replicated for cover properties
//This module is bound to a PSL vunit with cover properties
module assert_zero_one_hot_cover (clk, reset_n, test_expr, all_one_hots_checked);
parameter width = 1;
parameter OVL_COVER_SANITY_ON = 1;
parameter OVL_COVER_CORNER_ON = 1;
input clk, reset_n, all_one_hots_checked;
input [width-1:0] test_expr;
endmodule
|
/// date:2016/3/9
/// engineer: ZhaiShaoMin
module dc_download(//input
clk,
rst,
IN_flit_dc,
v_IN_flit_dc,
In_flit_ctrl_dc,
dc_done_access,
//output
v_dc_download,
dc_download_flits,
dc_download_state
);
/////// reply cmd
parameter wbrep_cmd=5'b10000;
parameter C2Hinvrep_cmd=5'b10001;
parameter flushrep_cmd=5'b10010;
parameter ATflurep_cmd=5'b10011;
parameter shrep_cmd=5'b11000;
parameter exrep_cmd=5'b11001;
parameter SH_exrep_cmd=5'b11010;
parameter SCflurep_cmd=5'b11100;
parameter instrep_cmd=5'b10100;
parameter C2Cinvrep_cmd=5'b11011;
parameter nackrep_cmd=5'b10101;
parameter flushfail_rep_cmd=5'b10110;
parameter wbfail_rep_cmd=5'b10111;
//input
input clk;
input rst;
input [15:0] IN_flit_dc; //from IN fifos
input v_IN_flit_dc;
input [1:0] In_flit_ctrl_dc;
input dc_done_access; // from data cache
//output
output v_dc_download; // to data cache
output [143:0] dc_download_flits;
output [1:0] dc_download_state; // to arbiter_IN_node
//
reg [1:0] dc_download_nstate;
reg [1:0] dc_download_cstate;
parameter dc_download_idle=2'b00;
parameter dc_download_busy=2'b01;
parameter dc_download_rdy=2'b10;
reg [15:0] flit_reg1;
reg [15:0] flit_reg2;
reg [15:0] flit_reg3;
reg [15:0] flit_reg4;
reg [15:0] flit_reg5;
reg [15:0] flit_reg6;
reg [15:0] flit_reg7;
reg [15:0] flit_reg8;
reg [15:0] flit_reg9;
assign dc_download_state=dc_download_cstate;
assign dc_download_flits={flit_reg9,flit_reg8,flit_reg7,flit_reg6,flit_reg5,flit_reg4,flit_reg3,flit_reg2,flit_reg1};
reg v_dc_download;
reg en_flit_dc;
reg inc_cnt;
reg fsm_rst;
/// fsm of ic_download
always@(*)
begin
//default values
dc_download_nstate=dc_download_cstate;
v_dc_download=1'b0;
en_flit_dc=1'b0;
inc_cnt=1'b0;
fsm_rst=1'b0;
case(dc_download_cstate)
dc_download_idle:
begin
if(v_IN_flit_dc)
begin
if(IN_flit_dc[9:5]==nackrep_cmd||IN_flit_dc[9:5]==SCflurep_cmd||IN_flit_dc[9:5]==C2Cinvrep_cmd)
dc_download_nstate=dc_download_rdy;
else
dc_download_nstate=dc_download_busy;
en_flit_dc=1'b1;
inc_cnt=1'b1;
end
end
dc_download_busy:
begin
if(v_IN_flit_dc)
begin
if(In_flit_ctrl_dc==2'b11)
begin
// en_flit_dc=1'b1;
dc_download_nstate=dc_download_rdy;
end
en_flit_dc=1'b1;
inc_cnt=1'b1;
end
end
dc_download_rdy:
begin
v_dc_download=1'b1;
if(dc_done_access)
begin
dc_download_nstate=dc_download_idle;
fsm_rst=1'b1;
end
end
endcase
end
reg [3:0] cnt;
reg [8:0] en_flits;
// select right inst_word_in
always@(*)
begin
case(cnt)
4'b0000:en_flits=9'b000000001;
4'b0001:en_flits=9'b000000010;
4'b0010:en_flits=9'b000000100;
4'b0011:en_flits=9'b000001000;
4'b0100:en_flits=9'b000010000;
4'b0101:en_flits=9'b000100000;
4'b0110:en_flits=9'b001000000;
4'b0111:en_flits=9'b010000000;
4'b1000:en_flits=9'b100000000;
default:en_flits=9'b000000000;
endcase
end
// 1st flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg1<=16'h0000;
else if(en_flits[0]&&en_flit_dc)
flit_reg1<=IN_flit_dc;
end
//2ed flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg2<=16'h0000;
else if(en_flits[1]&&en_flit_dc)
flit_reg2<=IN_flit_dc;
end
// 3rd flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg3<=16'h0000;
else if(en_flits[2]&&en_flit_dc)
flit_reg3<=IN_flit_dc;
end
//4th flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg4<=16'h0000;
else if(en_flits[3]&&en_flit_dc)
flit_reg4<=IN_flit_dc;
end
//5th flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg5<=16'h0000;
else if(en_flits[4]&&en_flit_dc)
flit_reg5<=IN_flit_dc;
end
//6th flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg6<=16'h0000;
else if(en_flits[5]&&en_flit_dc)
flit_reg6<=IN_flit_dc;
end
//7th flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg7<=16'h0000;
else if(en_flits[6]&&en_flit_dc)
flit_reg7<=IN_flit_dc;
end
//8th flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg8<=16'h0000;
else if(en_flits[7]&&en_flit_dc)
flit_reg8<=IN_flit_dc;
end
//9th flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg9<=16'h0000;
else if(en_flits[8]&&en_flit_dc)
flit_reg9<=IN_flit_dc;
end
// fsm regs
always@(posedge clk)
begin
if(rst)
dc_download_cstate<=2'b00;
else
dc_download_cstate<=dc_download_nstate;
end
//counter reg
always@(posedge clk)
begin
if(rst||fsm_rst)
cnt<=4'b0000;
else if(inc_cnt)
cnt<=cnt+4'b0001;
end
endmodule |
//altpll_avalon avalon_use_separate_sysclk="NO" CBX_SINGLE_OUTPUT_FILE="ON" CBX_SUBMODULE_USED_PORTS="altpll:areset,clk,locked,inclk" address areset c0 clk locked phasedone read readdata reset write writedata bandwidth_type="AUTO" clk0_divide_by=1 clk0_duty_cycle=50 clk0_multiply_by=1 clk0_phase_shift="-3000" compensate_clock="CLK0" device_family="CYCLONEIVE" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_UNUSED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5
//VERSION_BEGIN 14.0 cbx_altclkbuf 2014:06:17:18:06:03:SJ cbx_altiobuf_bidir 2014:06:17:18:06:03:SJ cbx_altiobuf_in 2014:06:17:18:06:03:SJ cbx_altiobuf_out 2014:06:17:18:06:03:SJ cbx_altpll 2014:06:17:18:06:03:SJ cbx_altpll_avalon 2014:06:17:18:06:03:SJ cbx_cycloneii 2014:06:17:18:06:03:SJ cbx_lpm_add_sub 2014:06:17:18:06:03:SJ cbx_lpm_compare 2014:06:17:18:06:03:SJ cbx_lpm_counter 2014:06:17:18:06:03:SJ cbx_lpm_decode 2014:06:17:18:06:03:SJ cbx_lpm_mux 2014:06:17:18:06:03:SJ cbx_lpm_shiftreg 2014:06:17:18:06:03:SJ cbx_mgl 2014:06:17:18:10:38:SJ cbx_stratix 2014:06:17:18:06:03:SJ cbx_stratixii 2014:06:17:18:06:03:SJ cbx_stratixiii 2014:06:17:18:06:03:SJ cbx_stratixv 2014:06:17:18:06:03:SJ cbx_util_mgl 2014:06:17:18:06:03:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus II License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//altera_std_synchronizer CBX_SINGLE_OUTPUT_FILE="ON" clk din dout reset_n
//VERSION_BEGIN 14.0 cbx_mgl 2014:06:17:18:10:38:SJ cbx_stratixii 2014:06:17:18:06:03:SJ cbx_util_mgl 2014:06:17:18:06:03:SJ VERSION_END
//dffpipe CBX_SINGLE_OUTPUT_FILE="ON" DELAY=3 WIDTH=1 clock clrn d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
//VERSION_BEGIN 14.0 cbx_mgl 2014:06:17:18:10:38:SJ cbx_stratixii 2014:06:17:18:06:03:SJ cbx_util_mgl 2014:06:17:18:06:03:SJ VERSION_END
//synthesis_resources = reg 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"AUTO_SHIFT_REGISTER_RECOGNITION=OFF"} *)
module usb_system_sdram_clk_dffpipe_l2c
(
clock,
clrn,
d,
q) /* synthesis synthesis_clearbox=1 */;
input clock;
input clrn;
input [0:0] d;
output [0:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 clock;
tri1 clrn;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [0:0] dffe4a;
reg [0:0] dffe5a;
reg [0:0] dffe6a;
wire ena;
wire prn;
wire sclr;
// synopsys translate_off
initial
dffe4a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a <= {1{1'b1}};
else if (clrn == 1'b0) dffe4a <= 1'b0;
else if (ena == 1'b1) dffe4a <= (d & (~ sclr));
// synopsys translate_off
initial
dffe5a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe5a <= {1{1'b1}};
else if (clrn == 1'b0) dffe5a <= 1'b0;
else if (ena == 1'b1) dffe5a <= (dffe4a & (~ sclr));
// synopsys translate_off
initial
dffe6a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a <= {1{1'b1}};
else if (clrn == 1'b0) dffe6a <= 1'b0;
else if (ena == 1'b1) dffe6a <= (dffe5a & (~ sclr));
assign
ena = 1'b1,
prn = 1'b1,
q = dffe6a,
sclr = 1'b0;
endmodule //usb_system_sdram_clk_dffpipe_l2c
//synthesis_resources = reg 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module usb_system_sdram_clk_stdsync_sv6
(
clk,
din,
dout,
reset_n) /* synthesis synthesis_clearbox=1 */;
input clk;
input din;
output dout;
input reset_n;
wire [0:0] wire_dffpipe3_q;
usb_system_sdram_clk_dffpipe_l2c dffpipe3
(
.clock(clk),
.clrn(reset_n),
.d(din),
.q(wire_dffpipe3_q));
assign
dout = wire_dffpipe3_q;
endmodule //usb_system_sdram_clk_stdsync_sv6
//altpll bandwidth_type="AUTO" CBX_SINGLE_OUTPUT_FILE="ON" clk0_divide_by=1 clk0_duty_cycle=50 clk0_multiply_by=1 clk0_phase_shift="-3000" compensate_clock="CLK0" device_family="CYCLONEIVE" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_UNUSED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5 areset clk inclk locked
//VERSION_BEGIN 14.0 cbx_altclkbuf 2014:06:17:18:06:03:SJ cbx_altiobuf_bidir 2014:06:17:18:06:03:SJ cbx_altiobuf_in 2014:06:17:18:06:03:SJ cbx_altiobuf_out 2014:06:17:18:06:03:SJ cbx_altpll 2014:06:17:18:06:03:SJ cbx_cycloneii 2014:06:17:18:06:03:SJ cbx_lpm_add_sub 2014:06:17:18:06:03:SJ cbx_lpm_compare 2014:06:17:18:06:03:SJ cbx_lpm_counter 2014:06:17:18:06:03:SJ cbx_lpm_decode 2014:06:17:18:06:03:SJ cbx_lpm_mux 2014:06:17:18:06:03:SJ cbx_mgl 2014:06:17:18:10:38:SJ cbx_stratix 2014:06:17:18:06:03:SJ cbx_stratixii 2014:06:17:18:06:03:SJ cbx_stratixiii 2014:06:17:18:06:03:SJ cbx_stratixv 2014:06:17:18:06:03:SJ cbx_util_mgl 2014:06:17:18:06:03:SJ VERSION_END
//synthesis_resources = cycloneive_pll 1 reg 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"SUPPRESS_DA_RULE_INTERNAL=C104;SUPPRESS_DA_RULE_INTERNAL=R101"} *)
module usb_system_sdram_clk_altpll_l942
(
areset,
clk,
inclk,
locked) /* synthesis synthesis_clearbox=1 */;
input areset;
output [4:0] clk;
input [1:0] inclk;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
tri0 [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg pll_lock_sync;
wire [4:0] wire_pll7_clk;
wire wire_pll7_fbout;
wire wire_pll7_locked;
// synopsys translate_off
initial
pll_lock_sync = 0;
// synopsys translate_on
always @ ( posedge wire_pll7_locked or posedge areset)
if (areset == 1'b1) pll_lock_sync <= 1'b0;
else pll_lock_sync <= 1'b1;
cycloneive_pll pll7
(
.activeclock(),
.areset(areset),
.clk(wire_pll7_clk),
.clkbad(),
.fbin(wire_pll7_fbout),
.fbout(wire_pll7_fbout),
.inclk(inclk),
.locked(wire_pll7_locked),
.phasedone(),
.scandataout(),
.scandone(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clkswitch(1'b0),
.configupdate(1'b0),
.pfdena(1'b1),
.phasecounterselect({3{1'b0}}),
.phasestep(1'b0),
.phaseupdown(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll7.bandwidth_type = "auto",
pll7.clk0_divide_by = 1,
pll7.clk0_duty_cycle = 50,
pll7.clk0_multiply_by = 1,
pll7.clk0_phase_shift = "-3000",
pll7.compensate_clock = "clk0",
pll7.inclk0_input_frequency = 20000,
pll7.operation_mode = "normal",
pll7.pll_type = "auto",
pll7.lpm_type = "cycloneive_pll";
assign
clk = {wire_pll7_clk[4:0]},
locked = (wire_pll7_locked & pll_lock_sync);
endmodule //usb_system_sdram_clk_altpll_l942
//synthesis_resources = cycloneive_pll 1 reg 6
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module usb_system_sdram_clk
(
address,
areset,
c0,
clk,
locked,
phasedone,
read,
readdata,
reset,
write,
writedata) /* synthesis synthesis_clearbox=1 */;
input [1:0] address;
input areset;
output c0;
input clk;
output locked;
output phasedone;
input read;
output [31:0] readdata;
input reset;
input write;
input [31:0] writedata;
wire wire_stdsync2_dout;
wire [4:0] wire_sd1_clk;
wire wire_sd1_locked;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=HIGH"} *)
reg pfdena_reg;
wire wire_pfdena_reg_ena;
reg prev_reset;
wire w_locked;
wire w_pfdena;
wire w_phasedone;
wire w_pll_areset_in;
wire w_reset;
wire w_select_control;
wire w_select_status;
usb_system_sdram_clk_stdsync_sv6 stdsync2
(
.clk(clk),
.din(wire_sd1_locked),
.dout(wire_stdsync2_dout),
.reset_n((~ reset)));
usb_system_sdram_clk_altpll_l942 sd1
(
.areset((w_pll_areset_in | areset)),
.clk(wire_sd1_clk),
.inclk({{1{1'b0}}, clk}),
.locked(wire_sd1_locked));
// synopsys translate_off
initial
pfdena_reg = {1{1'b1}};
// synopsys translate_on
always @ ( posedge clk or posedge reset)
if (reset == 1'b1) pfdena_reg <= {1{1'b1}};
else if (wire_pfdena_reg_ena == 1'b1) pfdena_reg <= writedata[1];
assign
wire_pfdena_reg_ena = (write & w_select_control);
// synopsys translate_off
initial
prev_reset = 0;
// synopsys translate_on
always @ ( posedge clk or posedge reset)
if (reset == 1'b1) prev_reset <= 1'b0;
else prev_reset <= w_reset;
assign
c0 = wire_sd1_clk[0],
locked = wire_sd1_locked,
phasedone = 1'b0,
readdata = {{30{1'b0}}, (read & ((w_select_control & w_pfdena) | (w_select_status & w_phasedone))), (read & ((w_select_control & w_pll_areset_in) | (w_select_status & w_locked)))},
w_locked = wire_stdsync2_dout,
w_pfdena = pfdena_reg,
w_phasedone = 1'b1,
w_pll_areset_in = prev_reset,
w_reset = ((write & w_select_control) & writedata[0]),
w_select_control = ((~ address[1]) & address[0]),
w_select_status = ((~ address[1]) & (~ address[0]));
endmodule //usb_system_sdram_clk
//VALID FILE
|
// megafunction wizard: %ALTECC%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altecc_encoder
// ============================================================
// File Name: alt_ddrx_encoder_40.v
// Megafunction Name(s):
// altecc_encoder
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Internal Build 157 07/06/2009 PN Web Edition
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altecc_encoder CBX_AUTO_BLACKBOX="ALL" device_family="Stratix" lpm_pipeline=1 width_codeword=39 width_dataword=32 clock data q
//VERSION_BEGIN 9.1 cbx_altecc_encoder 2009:06:09:13:39:47:PN cbx_mgl 2009:07:03:02:47:54:PN VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = lut 39
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module alt_ddrx_encoder_40_altecc_encoder_plb
(
clock,
data,
q) ;
input clock;
input [31:0] data;
output [38:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [38:0] output_pipeline0c;
wire aclr;
wire clocken;
wire [31:0] data_wire;
wire [17:0] parity_01_wire;
wire [9:0] parity_02_wire;
wire [4:0] parity_03_wire;
wire [1:0] parity_04_wire;
wire [0:0] parity_05_wire;
wire [5:0] parity_06_wire;
wire [37:0] parity_final_wire;
wire [38:0] q_wire;
// synopsys translate_off
initial
output_pipeline0c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) output_pipeline0c <= 39'b0;
else if (clocken == 1'b1) output_pipeline0c <= q_wire;
assign
aclr = 1'b0,
clocken = 1'b1,
data_wire = data,
parity_01_wire = {(data_wire[30] ^ parity_01_wire[16]), (data_wire[28] ^ parity_01_wire[15]), (data_wire[26] ^ parity_01_wire[14]), (data_wire[25] ^ parity_01_wire[13]), (data_wire[23] ^ parity_01_wire[12]), (data_wire[21] ^ parity_01_wire[11]), (data_wire[19] ^ parity_01_wire[10]), (data_wire[17] ^ parity_01_wire[9]), (data_wire[15] ^ parity_01_wire[8]), (data_wire[13] ^ parity_01_wire[7]), (data_wire[11] ^ parity_01_wire[6]), (data_wire[10] ^ parity_01_wire[5]), (data_wire[8] ^ parity_01_wire[4]), (data_wire[6] ^ parity_01_wire[3]), (data_wire[4] ^ parity_01_wire[2]), (data_wire[3] ^ parity_01_wire[1]), (data_wire[1] ^ parity_01_wire[0]), data_wire[0]},
parity_02_wire = {(data_wire[31] ^ parity_02_wire[8]), ((data_wire[27] ^ data_wire[28]) ^ parity_02_wire[7]), ((data_wire[24] ^ data_wire[25]) ^ parity_02_wire[6]), ((data_wire[20] ^ data_wire[21]) ^ parity_02_wire[5]), ((data_wire[16] ^ data_wire[17]) ^ parity_02_wire[4]), ((data_wire[12] ^ data_wire[13]) ^ parity_02_wire[3]), ((data_wire[9] ^ data_wire[10]) ^ parity_02_wire[2]), ((data_wire[5] ^ data_wire[6]) ^ parity_02_wire[1]), ((data_wire[2] ^ data_wire[3]) ^ parity_02_wire[0]), data_wire[0]},
parity_03_wire = {(((data_wire[29] ^ data_wire[30]) ^ data_wire[31]) ^ parity_03_wire[3]), ((((data_wire[22] ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_03_wire[2]), ((((data_wire[14] ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ parity_03_wire[1]), ((((data_wire[7] ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10]) ^ parity_03_wire[0]), ((data_wire[1] ^ data_wire[2]) ^ data_wire[3])},
parity_04_wire = {((((((((data_wire[18] ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_04_wire[0]), ((((((data_wire[4] ^ data_wire[5]) ^ data_wire[6]) ^ data_wire[7]) ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10])},
parity_05_wire = {((((((((((((((data_wire[11] ^ data_wire[12]) ^ data_wire[13]) ^ data_wire[14]) ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ data_wire[18]) ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25])},
parity_06_wire = {(data_wire[31] ^ parity_06_wire[4]), (data_wire[30] ^ parity_06_wire[3]), (data_wire[29] ^ parity_06_wire[2]), (data_wire[28] ^ parity_06_wire[1]), (data_wire[27] ^ parity_06_wire[0]), data_wire[26]},
parity_final_wire = {(q_wire[37] ^ parity_final_wire[36]), (q_wire[36] ^ parity_final_wire[35]), (q_wire[35] ^ parity_final_wire[34]), (q_wire[34] ^ parity_final_wire[33]), (q_wire[33] ^ parity_final_wire[32]), (q_wire[32] ^ parity_final_wire[31]), (q_wire[31] ^ parity_final_wire[30]), (q_wire[30] ^ parity_final_wire[29]), (q_wire[29] ^ parity_final_wire[28]), (q_wire[28] ^ parity_final_wire[27]), (q_wire[27] ^ parity_final_wire[26]), (q_wire[26] ^ parity_final_wire[25]), (q_wire[25] ^ parity_final_wire[24]), (q_wire[24] ^ parity_final_wire[23]), (q_wire[23] ^ parity_final_wire[22]), (q_wire[22] ^ parity_final_wire[21]), (q_wire[21] ^ parity_final_wire[20]), (q_wire[20] ^ parity_final_wire[19]), (q_wire[19] ^ parity_final_wire[18]), (q_wire[18] ^ parity_final_wire[17]), (q_wire[17] ^ parity_final_wire[16]), (q_wire[16] ^ parity_final_wire[15]), (q_wire[15] ^ parity_final_wire[14]), (q_wire[14] ^ parity_final_wire[13]), (q_wire[13] ^ parity_final_wire[12]), (q_wire[12] ^ parity_final_wire[11]), (q_wire[11] ^ parity_final_wire[10]), (q_wire[10] ^ parity_final_wire[9]), (q_wire[9] ^ parity_final_wire[8]), (q_wire[8] ^ parity_final_wire[7]), (q_wire[7] ^ parity_final_wire[6]), (q_wire[6] ^ parity_final_wire[5]), (q_wire[5] ^ parity_final_wire[4]), (q_wire[4] ^ parity_final_wire[3]), (q_wire[3] ^ parity_final_wire[2]), (q_wire[2] ^ parity_final_wire[1]), (q_wire[1] ^ parity_final_wire[0]), q_wire[0]},
q = output_pipeline0c,
q_wire = {parity_final_wire[37], parity_06_wire[5], parity_05_wire[0], parity_04_wire[1], parity_03_wire[4], parity_02_wire[9], parity_01_wire[17], data_wire};
endmodule //alt_ddrx_encoder_40_altecc_encoder_plb
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module alt_ddrx_encoder_40 (
clock,
data,
q);
input clock;
input [31:0] data;
output [38:0] q;
wire [38:0] sub_wire0;
wire [38:0] q = sub_wire0[38:0];
alt_ddrx_encoder_40_altecc_encoder_plb alt_ddrx_encoder_40_altecc_encoder_plb_component (
.clock (clock),
.data (data),
.q (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix"
// Retrieval info: CONSTANT: lpm_pipeline NUMERIC "1"
// Retrieval info: CONSTANT: width_codeword NUMERIC "39"
// Retrieval info: CONSTANT: width_dataword NUMERIC "32"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 39 0 OUTPUT NODEFVAL "q[38..0]"
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: q 0 0 39 0 @q 0 0 39 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ddrx_encoder_40.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ddrx_encoder_40.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ddrx_encoder_40.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ddrx_encoder_40.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ddrx_encoder_40_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ddrx_encoder_40_bb.v FALSE
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sctag_evicttag_dp.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
`include "sctag.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
// Change 4/7/2003: Added a pin, vuad_idx_c3 to the bottom.
////////////////////////////////////////////////////////////////////////
module sctag_evicttag_dp( /*AUTOARG*/
// Outputs
evicttag_addr_px2, so, evict_addr, sctag_dram_addr, lkup_addr_c1,
mb_write_addr, wb_write_addr, vuad_idx_c3,
// Inputs
wb_read_data, rdma_read_data, mb_read_data, fb_read_data,
arbdp_cam_addr_px2, tagdp_evict_tag_c4, wbctl_wr_addr_sel,
wb_or_rdma_wr_req_en, mbctl_arb_l2rd_en, mbctl_arb_dramrd_en,
fbctl_arb_l2rd_en, mux1_mbsel_px1, arbctl_evict_c4, rclk, si, se,
sehold
);
output [39:0] evicttag_addr_px2;
output so;
output [39:6] evict_addr ; // to the csr block
output [39:5] sctag_dram_addr;
output [39:8] lkup_addr_c1; // address to lkup buffer tags.
output [39:0] mb_write_addr;
output [39:0] wb_write_addr;
output [9:0] vuad_idx_c3; // Bottom.
input [39:6] wb_read_data ; // wr address from wb
input [39:6] rdma_read_data; // wr address from rdmawb
input [39:0] mb_read_data;
input [39:0] fb_read_data;
input [39:0] arbdp_cam_addr_px2;
input [`TAG_WIDTH-1:6] tagdp_evict_tag_c4;
input wbctl_wr_addr_sel ; // sel wb_read_data
input wb_or_rdma_wr_req_en ; // enable wr addr flop.
input mbctl_arb_l2rd_en;
input mbctl_arb_dramrd_en;
input fbctl_arb_l2rd_en;
input mux1_mbsel_px1; // from arbctl
input arbctl_evict_c4;// from arbctl.
input rclk;
input si, se ;
input sehold;
wire [39:0] mbf_addr_px2, fbf_addr_px2;
wire dram_pick_d2;
wire [39:6] evict_rd_data;
wire [39:6] dram_wr_addr;
wire [39:5] dram_read_addr;
wire [39:0] inst_addr_c1;
wire [39:0] inst_addr_c2, inst_addr_c3;
wire [39:0] inst_addr_c4;
wire [39:0] evict_addr_c4;
wire mux1_mbsel_px2_1;
wire mux1_mbsel_px2_2;
wire mux1_mbsel_px2_3;
wire mux1_mbsel_px2_4;
//////////////////////////////
// Arb mux between MB and FB
//////////////////////////////
dff_s #(40) ff_read_mb_tag_reg (.din(mb_read_data[39:0]), .clk(clk_1),
.q(mbf_addr_px2[39:0]), .se(se), .si(), .so());
clken_buf clk_buf1 (.clk(clk_1), .rclk(rclk), .enb_l(~mbctl_arb_l2rd_en), .tmb_l(~se));
dff_s #(40) ff_read_fb_tag_reg (.din(fb_read_data[39:0]), .clk(clk_2),
.q(fbf_addr_px2[39:0]), .se(se), .si(), .so());
clken_buf clk_buf2 (.clk(clk_2), .rclk(rclk), .enb_l(~fbctl_arb_l2rd_en), .tmb_l(~se));
// Change 6/12/2003:
// -created 4 sets fo selects for the evicttag_addr_px2 mux.
// -in the implementation, invert the data before muxing,
// use a 2x or 4x mux and drive the output of the mux
// with a 40x driver.
dff_s #(1) ff_mux1_mbsel_px2_1 (.din(mux1_mbsel_px1), .clk(rclk),
.q(mux1_mbsel_px2_1), .se(se), .si(), .so());
dff_s #(1) ff_mux1_mbsel_px2_2 (.din(mux1_mbsel_px1), .clk(rclk),
.q(mux1_mbsel_px2_2), .se(se), .si(), .so());
dff_s #(1) ff_mux1_mbsel_px2_3 (.din(mux1_mbsel_px1), .clk(rclk),
.q(mux1_mbsel_px2_3), .se(se), .si(), .so());
dff_s #(1) ff_mux1_mbsel_px2_4 (.din(mux1_mbsel_px1), .clk(rclk),
.q(mux1_mbsel_px2_4), .se(se), .si(), .so());
mux2ds #(10) mux_mux1_addr_px2_9_0 (.dout (evicttag_addr_px2[9:0]) ,
.in0(mbf_addr_px2[9:0]), .in1(fbf_addr_px2[9:0] ),
.sel0(mux1_mbsel_px2_1), .sel1(~mux1_mbsel_px2_1)) ;
mux2ds #(10) mux_mux1_addr_px2_19_10 (.dout (evicttag_addr_px2[19:10]) ,
.in0(mbf_addr_px2[19:10]), .in1(fbf_addr_px2[19:10] ),
.sel0(mux1_mbsel_px2_2), .sel1(~mux1_mbsel_px2_2)) ;
mux2ds #(10) mux_mux1_addr_px2_29_20 (.dout (evicttag_addr_px2[29:20]) ,
.in0(mbf_addr_px2[29:20]), .in1(fbf_addr_px2[29:20] ),
.sel0(mux1_mbsel_px2_3), .sel1(~mux1_mbsel_px2_3)) ;
mux2ds #(10) mux_mux1_addr_px2_39_30 (.dout (evicttag_addr_px2[39:30]) ,
.in0(mbf_addr_px2[39:30]), .in1(fbf_addr_px2[39:30] ),
.sel0(mux1_mbsel_px2_4), .sel1(~mux1_mbsel_px2_4)) ;
//////////////////////////////
// dram read addr flop.
//////////////////////////////
dff_s #(35) ff_dram_read_addr (.din(mb_read_data[39:5]), .clk(clk_3),
.q(dram_read_addr[39:5]), .se(se), .si(), .so());
clken_buf clk_buf3 (.clk(clk_3), .rclk(rclk), .enb_l(~mbctl_arb_dramrd_en), .tmb_l(~se));
// dffe #(35) ff_dram_read_addr (.din(mb_read_data[39:5]), .clk(rclk),
// .en(mbctl_arb_dramrd_en),
// .q(dram_read_addr[39:5]), .se(se), .si(), .so());
//////////////////////////////
// MUX Between RDMA and WB addresses.
// and wr addr flop
//////////////////////////////
mux2ds #(34) rdmawb_addr_mux ( .dout ( evict_rd_data[39:6]),
.in0(rdma_read_data[39:6]), // rdma evict addr
.in1(wb_read_data[39:6]), // wb evict addr
.sel0(~wbctl_wr_addr_sel), // sel rdma evict addr
.sel1(wbctl_wr_addr_sel)); // sel wb evict addr.
dff_s #(34) ff_wb_rdma_write_addr (.din(evict_rd_data[39:6]),
.clk(clk_4), .q(dram_wr_addr[39:6]), .se(se), .si(), .so());
clken_buf clk_buf4 (.clk(clk_4), .rclk(rclk), .enb_l(~wb_or_rdma_wr_req_en), .tmb_l(~se));
// dffe #(34) ff_wb_rdma_write_addr (.din(evict_rd_data[39:6]),
// .en(wb_or_rdma_wr_req_en),
// .clk(rclk), .q(dram_wr_addr[39:6]), .se(se), .si(), .so());
assign evict_addr = dram_wr_addr[39:6] ;
// ctl flop. This flop is here for timing reasons.
dff_s #(1) ff_dram_pick_d2(.din(mbctl_arb_dramrd_en), .clk(rclk),
.q(dram_pick_d2), .se(se), .si(), .so());
//////////////////////////////
// Addr to DRAM
//////////////////////////////
mux2ds #(35) dram_addr_mux ( .dout ( sctag_dram_addr[39:5]),
.in0(dram_read_addr[39:5]),
.in1({dram_wr_addr[39:6],1'b0}),
.sel0(dram_pick_d2),
.sel1(~dram_pick_d2));
//////////////////////////////
// CAM addresses.
// mb write addr.
// wb write addr.
//////////////////////////////
// New functionality POST_4.0
// sehold will make ff_lkup_addr_c1 non-transparent.
clken_buf clk_buf5 (.clk(clk_5), .rclk(rclk), .enb_l(sehold), .tmb_l(~se));
dff_s #(40) ff_lkup_addr_c1 (.din(arbdp_cam_addr_px2[39:0]), .clk(clk_5),
.q(inst_addr_c1[39:0]), .se(se), .si(), .so());
assign lkup_addr_c1 = inst_addr_c1[39:8] ;
dff_s #(40) ff_inst_addr_c2 (.din(inst_addr_c1[39:0]), .clk(rclk),
.q(inst_addr_c2[39:0]), .se(se), .si(), .so());
assign mb_write_addr = inst_addr_c2 ;
dff_s #(40) ff_inst_addr_c3 (.din(inst_addr_c2[39:0]), .clk(rclk),
.q(inst_addr_c3[39:0]), .se(se), .si(), .so());
assign vuad_idx_c3 = inst_addr_c3[17:8] ;
dff_s #(40) ff_inst_addr_c4 (.din(inst_addr_c3[39:0]), .clk(rclk),
.q(inst_addr_c4[39:0]), .se(se), .si(), .so());
assign evict_addr_c4[39:18] = tagdp_evict_tag_c4[`TAG_WIDTH-1:6] ;
assign evict_addr_c4[17:6] = inst_addr_c4[17:6] ;
assign evict_addr_c4[5:0] = 6'b0 ;
mux2ds #(40) mux_wbb_wraddr_c3 ( .dout (wb_write_addr[39:0]),
.in0(inst_addr_c4[39:0]), .in1(evict_addr_c4[39:0]),
.sel0(~arbctl_evict_c4), .sel1(arbctl_evict_c4));
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// --------------------------------------------------------------------------------
//| Avalon ST Packets to Bytes Component
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
module altera_avalon_st_packets_to_bytes
//if ENCODING ==0, CHANNEL_WIDTH must be 8
//else CHANNEL_WIDTH can be from 0 to 127
#( parameter CHANNEL_WIDTH = 8,
parameter ENCODING = 0)
(
// Interface: clk
input clk,
input reset_n,
// Interface: ST in with packets
output reg in_ready,
input in_valid,
input [7: 0] in_data,
input [CHANNEL_WIDTH-1: 0] in_channel,
input in_startofpacket,
input in_endofpacket,
// Interface: ST out
input out_ready,
output reg out_valid,
output reg [7: 0] out_data
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
localparam CHN_COUNT = (CHANNEL_WIDTH-1)/7;
localparam CHN_EFFECTIVE = CHANNEL_WIDTH-1;
reg sent_esc, sent_sop, sent_eop;
reg sent_channel_char, channel_escaped, sent_channel;
reg [CHANNEL_WIDTH:0] stored_channel;
reg [4:0] channel_count;
reg [((CHN_EFFECTIVE/7+1)*7)-1:0] stored_varchannel;
reg channel_needs_esc;
wire need_sop, need_eop, need_esc, need_channel;
// ---------------------------------------------------------------------
//| Thingofamagick
// ---------------------------------------------------------------------
assign need_esc = (in_data === 8'h7a |
in_data === 8'h7b |
in_data === 8'h7c |
in_data === 8'h7d );
assign need_eop = (in_endofpacket);
assign need_sop = (in_startofpacket);
generate
if( CHANNEL_WIDTH > 0) begin
wire channel_changed;
assign channel_changed = (in_channel != stored_channel);
assign need_channel = (need_sop | channel_changed);
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
sent_esc <= 0;
sent_sop <= 0;
sent_eop <= 0;
sent_channel <= 0;
channel_escaped <= 0;
sent_channel_char <= 0;
out_data <= 0;
out_valid <= 0;
channel_count <= 0;
channel_needs_esc <= 0;
end else begin
if (out_ready )
out_valid <= 0;
if ((out_ready | ~out_valid) && in_valid )
out_valid <= 1;
if ((out_ready | ~out_valid) && in_valid) begin
if (need_channel & ~sent_channel) begin
if (~sent_channel_char) begin
sent_channel_char <= 1;
out_data <= 8'h7c;
channel_count <= CHN_COUNT[4:0];
stored_varchannel <= in_channel;
if ((ENCODING == 0) | (CHANNEL_WIDTH == 7)) begin
channel_needs_esc <= (in_channel == 8'h7a |
in_channel == 8'h7b |
in_channel == 8'h7c |
in_channel == 8'h7d );
end
end else if (channel_needs_esc & ~channel_escaped) begin
out_data <= 8'h7d;
channel_escaped <= 1;
end else if (~sent_channel) begin
if (ENCODING) begin
// Sending out MSB=1, while not last 7 bits of Channel
if (channel_count > 0) begin
if (channel_needs_esc) out_data <= {1'b1, stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-1:((CHN_EFFECTIVE/7+1)*7)-7]} ^ 8'h20;
else out_data <= {1'b1, stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-1:((CHN_EFFECTIVE/7+1)*7)-7]};
stored_varchannel <= stored_varchannel<<7;
channel_count <= channel_count - 1'b1;
// check whether the last 7 bits need escape or not
if (channel_count ==1 & CHANNEL_WIDTH > 7) begin
channel_needs_esc <=
((stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-8:((CHN_EFFECTIVE/7+1)*7)-14] == 7'h7a)|
(stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-8:((CHN_EFFECTIVE/7+1)*7)-14] == 7'h7b) |
(stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-8:((CHN_EFFECTIVE/7+1)*7)-14] == 7'h7c) |
(stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-8:((CHN_EFFECTIVE/7+1)*7)-14] == 7'h7d) );
end
end else begin
// Sending out MSB=0, last 7 bits of Channel
if (channel_needs_esc) begin
channel_needs_esc <= 0;
out_data <= {1'b0, stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-1:((CHN_EFFECTIVE/7+1)*7)-7]} ^ 8'h20;
end else out_data <= {1'b0, stored_varchannel[((CHN_EFFECTIVE/7+1)*7)-1:((CHN_EFFECTIVE/7+1)*7)-7]};
sent_channel <= 1;
end
end else begin
if (channel_needs_esc) begin
channel_needs_esc <= 0;
out_data <= in_channel ^ 8'h20;
end else out_data <= in_channel;
sent_channel <= 1;
end
end
end else if (need_sop & ~sent_sop) begin
sent_sop <= 1;
out_data <= 8'h7a;
end else if (need_eop & ~sent_eop) begin
sent_eop <= 1;
out_data <= 8'h7b;
end else if (need_esc & ~sent_esc) begin
sent_esc <= 1;
out_data <= 8'h7d;
end else begin
if (sent_esc) out_data <= in_data ^ 8'h20;
else out_data <= in_data;
sent_esc <= 0;
sent_sop <= 0;
sent_eop <= 0;
sent_channel <= 0;
channel_escaped <= 0;
sent_channel_char <= 0;
end
end
end
end
//channel related signals
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
//extra bit in stored_channel to force reset
stored_channel <= {CHANNEL_WIDTH{1'b1}};
end else begin
//update stored_channel only when it is sent out
if (sent_channel) stored_channel <= in_channel;
end
end
always @* begin
// in_ready. Low when:
// back pressured, or when
// we are outputting a control character, which means that one of
// {escape_char, start of packet, end of packet, channel}
// needs to be, but has not yet, been handled.
in_ready = (out_ready | !out_valid) & in_valid & (~need_esc | sent_esc)
& (~need_sop | sent_sop)
& (~need_eop | sent_eop)
& (~need_channel | sent_channel);
end
end else begin
assign need_channel = (need_sop);
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
sent_esc <= 0;
sent_sop <= 0;
sent_eop <= 0;
out_data <= 0;
out_valid <= 0;
sent_channel <= 0;
sent_channel_char <= 0;
end else begin
if (out_ready )
out_valid <= 0;
if ((out_ready | ~out_valid) && in_valid )
out_valid <= 1;
if ((out_ready | ~out_valid) && in_valid) begin
if (need_channel & ~sent_channel) begin
if (~sent_channel_char) begin //Added sent channel 0 before the 1st SOP
sent_channel_char <= 1;
out_data <= 8'h7c;
end else if (~sent_channel) begin
out_data <= 'h0;
sent_channel <= 1;
end
end else if (need_sop & ~sent_sop) begin
sent_sop <= 1;
out_data <= 8'h7a;
end else if (need_eop & ~sent_eop) begin
sent_eop <= 1;
out_data <= 8'h7b;
end else if (need_esc & ~sent_esc) begin
sent_esc <= 1;
out_data <= 8'h7d;
end else begin
if (sent_esc) out_data <= in_data ^ 8'h20;
else out_data <= in_data;
sent_esc <= 0;
sent_sop <= 0;
sent_eop <= 0;
end
end
end
end
always @* begin
in_ready = (out_ready | !out_valid) & in_valid & (~need_esc | sent_esc)
& (~need_sop | sent_sop)
& (~need_eop | sent_eop)
& (~need_channel | sent_channel);
end
end
endgenerate
endmodule
|
// Non-Synthesizable DPI General Purpose IO
//
// This module is useful for setting and reading "pins" from C/C++
//
// Parameters:
// int width_p: bit-width of input and output pins
// bit [width_p-1:0] init_o_p: Initial value of outputs
// int debug_p: Turn on debug messages at compile time (as opposed
// to runtime)
// DPI Functions:
// void bsg_dpi_init(): Initialize this module. Must be called after
// the initial block has been evaluated.
// void bsg_dpi_fini(): Destruct this module. Must be called before
// the final block has been evaluated.
// bit bsg_dpi_get(int index): Get the value of the input pin at index
// bit bsg_dpi_set(int index, bit value): Set the value of the output pin at index
// void bsg_dpi_debug(bit): Set or unset the debug_o output bit. If
// a state change occurs (0->1 or 1->0) then module will print DEBUG
// ENABLED / DEBUG DISABLED. No messages are printed if a state
// change does not occur.
// int bsg_dpi_width(): returns the parameter width_p
`include "bsg_defines.v"
module bsg_nonsynth_dpi_gpio
#(parameter int width_p = 1)
,parameter bit [width_p-1:0] init_o_p = '0
,parameter bit use_input_p = '0
,parameter bit use_output_p = '0
,parameter bit debug_p = '0
)
(output bit [width_p-1:0] gpio_o
,input bit [width_p-1:0] gpio_i
);
bit debug_b;
if(width_p <= 0)
$fatal(1, "BSG ERROR (%M): width_p must be greater than 0");
if(~use_input_p & ~use_output_p)
$fatal(1, "BSG ERROR (%M): GPIO must be configured to use input, output, or both");
// Print module parameters to the console and set the intial debug
// value. We use init_b to track whether the module has been
// initialized.
bit init_b;
initial begin
debug_b = debug_p;
init_b = 0;
gpio_o = init_o_p;
$display("BSG INFO: bsg_nonsynth_dpi_rom (initial begin)");
$display("BSG INFO: Instantiation: %M");
$display("BSG INFO: width_p: %d", width_p);
$display("BSG INFO: init_o_p: %b", init_o_p);
$display("BSG INFO: use_input_p: %b", use_input_p);
$display("BSG INFO: use_output_p: %b", use_output_p);
$display("BSG INFO: debug_p: %d", debug_p);
end
// This assert checks that fini was called before $finish
final begin
if(init_b)
$fatal(1, "BSG ERROR (%M): final block executed before fini() was called");
end
export "DPI-C" function bsg_dpi_init;
export "DPI-C" function bsg_dpi_fini;
export "DPI-C" function bsg_dpi_debug;
export "DPI-C" function bsg_dpi_width;
export "DPI-C" function bsg_dpi_gpio_get;
export "DPI-C" function bsg_dpi_gpio_set;
// Initialize this Manycore DPI Interface
function void bsg_dpi_init();
if(init_b)
$fatal(1, "BSG ERROR (%M): init() already called");
init_b = 1;
endfunction
// Terminate this Manycore DPI Interface
function void bsg_dpi_fini();
if(~init_b)
$fatal(1, "BSG ERROR (%M): fini() already called");
init_b = 0;
endfunction
// Return the parameter width_p
function int bsg_dpi_width();
return width_p;
endfunction
// Set or unset the debug_o output bit. If a state change occurs
// (0->1 or 1->0) then module will print DEBUG ENABLED / DEBUG
// DISABLED. No messages are printed if a state change does not
// occur.
function void bsg_dpi_debug(input bit switch_i);
if(!debug_b & switch_i)
$display("BSG DBGINFO (%M@%t): DEBUG ENABLED", $time);
else if (debug_b & !switch_i)
$display("BSG DBGINFO (%M@%t): DEBUG DISABLED", $time);
debug_b = switch_i;
endfunction
// Get the value of an input pin at the given index.
//
// Fails if an invalid index is accessed
function bit bsg_dpi_gpio_get(input int index);
bit retval;
if(~init_b)
$fatal(1, "BSG ERROR (%M): get() called before init()");
if(~use_input_p)
$fatal(1, "BSG ERROR (%M): get() called but use_input_p is 0");
if(index >= width_p)
$fatal(1, "BSG ERROR (%M): Invalid index %d", index);
retval = gpio_i[index];
if(debug_b)
$display("BSG INFO (%M): Read Index %d, got %b", index, retval);
return retval;
endfunction
// Set the value of an output pin at the given index.
//
// Fails if an invalid index is accessed
function bit bsg_dpi_gpio_set(input int index, input bit value);
if(~init_b)
$fatal(1, "BSG ERROR (%M): get() called before init()");
if(~use_output_p)
$fatal(1, "BSG ERROR (%M): get() called but use_output_p is 0");
if(index >= width_p)
$fatal(1, "BSG ERROR (%M): Invalid index %d", index);
gpio_o[index] = value;
if(debug_b)
$display("BSG INFO (%M): Wrote Index %d, set to %b", index, value);
return gpio_o[index];
endfunction
endmodule
|
/*
* Zet SoC top level file for Altera DE1 board
* Copyright (C) 2009, 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module CoPro80186 (
input fastclk,
// GOP Signals
output [6:1] test,
output [8:2] tp,
input [2:1] sw,
output fcs,
// Tube signals (use 16 out of 22 DIL pins)
input h_phi2,
input [2:0] h_addr,
inout [7:0] h_data,
input h_rdnw,
input h_cs_b,
input h_rst_b,
output h_irq_b,
// Ram Signals
output ram_cs,
output ram_oe,
output ram_wr,
output [18:0] ram_addr,
inout [7:0] ram_data
);
// Registers and nets
wire clk;
wire rst_lck;
wire [15:0] dat_o;
wire [15:0] dat_i;
wire [19:1] adr;
wire we;
wire tga;
wire [ 1:0] sel;
wire stb;
wire cyc;
wire ack;
wire lock;
// wires to BIOS ROM
wire [15:0] rom_dat_o;
wire [15:0] rom_dat_i;
wire rom_tga_i;
wire [19:1] rom_adr_i;
wire [ 1:0] rom_sel_i;
wire rom_we_i;
wire rom_cyc_i;
wire rom_stb_i;
wire rom_ack_o;
// wires to RAM
wire [15:0] ram_dat_o;
wire [15:0] ram_dat_i;
wire ram_tga_i;
wire [19:1] ram_adr_i;
wire [ 1:0] ram_sel_i;
wire ram_we_i;
wire ram_cyc_i;
wire ram_stb_i;
wire ram_ack_o;
// wires to Tube
wire [15:0] tube_dat_o;
wire [15:0] tube_dat_i;
wire tube_tga_i;
wire [19:1] tube_adr_i;
wire [ 1:0] tube_sel_i;
wire tube_we_i;
wire tube_cyc_i;
wire tube_stb_i;
wire tube_ack_o;
wire drq;
wire dack_b;
wire [2:0] p_addr;
wire p_cs_b;
wire [7:0] p_data;
wire p_rd_b;
wire p_wr_b;
wire p_rst_b;
wire p_nmi_b;
wire p_irq_b;
// unused slaves
wire s3_cyc_i;
wire s3_stb_i;
wire s4_cyc_i;
wire s4_stb_i;
wire s5_cyc_i;
wire s5_stb_i;
wire s6_cyc_i;
wire s6_stb_i;
wire s7_cyc_i;
wire s7_stb_i;
wire s9_cyc_i;
wire s9_stb_i;
wire sa_cyc_i;
wire sa_stb_i;
wire def_cyc_i;
wire def_stb_i;
// wires to default stb/ack
wire [15:0] sw_dat_o;
wire [ 7:0] intv;
wire [ 2:0] iid;
wire intr;
wire inta;
wire nmi;
wire nmia;
// Instantiate the module
dcm_49_16 instance_name (
.CLKIN_IN(fastclk),
.CLK0_OUT(clk),
.CLK0_OUT1(),
.CLK2X_OUT()
);
wire rst;
assign rst = !p_rst_b;
bootrom bootrom (
.clk (clk), // Wishbone slave interface
.rst (rst),
.wb_dat_i (rom_dat_i),
.wb_dat_o (rom_dat_o),
.wb_adr_i (rom_adr_i),
.wb_we_i (rom_we_i ),
.wb_tga_i (rom_tga_i),
.wb_stb_i (rom_stb_i),
.wb_cyc_i (rom_cyc_i),
.wb_sel_i (rom_sel_i),
.wb_ack_o (rom_ack_o)
);
wb_sram16 wb_sram16 (
.clk(clk),
.reset(rst),
.wb_dat_i(ram_dat_i),
.wb_dat_o(ram_dat_o),
.wb_adr_i(ram_adr_i),
.wb_we_i(ram_we_i),
.wb_tga_i(ram_tga_i),
.wb_stb_i(ram_stb_i),
.wb_cyc_i(ram_cyc_i),
.wb_sel_i(ram_sel_i),
.wb_ack_o(ram_ack_o),
.sram_adr(ram_addr),
.sram_dat(ram_data),
.sram_be_n({ram_ub_b, ram_lb_b}),
.sram_ce_n(ram_cs),
.sram_oe_n(ram_oe),
.sram_we_n(ram_wr)
);
wb_tube wb_tube_inst(
.clk(clk),
.reset(rst),
.wb_stb_i(tube_stb_i),
.wb_cyc_i(tube_cyc_i),
.wb_ack_o(tube_ack_o),
.wb_we_i(tube_we_i),
.wb_tga_i(tube_tga_i),
.wb_adr_i(tube_adr_i[3:1]),
.wb_sel_i(tube_sel_i),
.wb_dat_i(tube_dat_i),
.wb_dat_o(tube_dat_o),
.tube_adr(p_addr),
.tube_dat(p_data),
.tube_cs_n(p_cs_b),
.tube_rd_n(p_rd_b),
.tube_wr_n(p_wr_b)
);
tube tube_inst(
.h_addr(h_addr),
.h_cs_b(h_cs_b),
.h_data(h_data),
.h_phi2(h_phi2),
.h_rdnw(h_rdnw),
.h_rst_b(h_rst_b),
.h_irq_b(h_irq_b),
.drq(drq),
.dack_b(dack_b),
.p_addr(p_addr),
.p_cs_b(p_cs_b),
.p_data(p_data),
.p_rd_b(p_rd_b),
.p_wr_b(p_wr_b),
.p_rst_b(p_rst_b),
.p_nmi_b(p_nmi_b),
.p_irq_b(p_irq_b)
);
simple_pic pic0 (
.clk (clk),
.rst (rst),
.intv (intv),
.inta (inta),
.intr (intr),
.iid (iid)
);
zet zet (
.pc (),
// Wishbone master interface
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_dat_i (dat_i),
.wb_dat_o (dat_o),
.wb_adr_o (adr),
.wb_we_o (we),
.wb_tga_o (tga),
.wb_sel_o (sel),
.wb_stb_o (stb),
.wb_cyc_o (cyc),
.wb_ack_i (ack),
.wb_tgc_i (intr),
.wb_tgc_o (inta),
.nmi (nmi),
.nmia (nmia)
);
// Interrupt Control Registers (0x20-0x3E)
// &0FF22 - EOI Register
// &0FF38 - INT0 Control Register
// Timer Control Registers (0x50-0x66)
// &0FF52
// &0FF56
// &0FF60
// &0FF62
// &0FF66
// Chip Select Control Registers (0xA0-0xA8)
// &0FFA0
// &0FFA2
// &0FFA4
// &0FFA6
// &0FFA8
// DMA Channel 0 (0xC0 - 0xCA)
// &0FFC0
// &0FFC2
// &0FFC4
// &0FFC6
// &0FFCA
wb_switch #(
.s0_addr_1 (20'b0_1100_0000_0000_0000_000), // bios boot mem 0xc0000 - 0xfffff
.s0_mask_1 (20'b1_1100_0000_0000_0000_000), // bios boot ROM Memory
.s1_addr_1 (20'b0_0000_0000_0000_0000_000), // mem 0x00000-0x7ffff
.s1_mask_1 (20'b1_1000_0000_0000_0000_000), // main memory
.s1_addr_2 (20'b0_1000_0000_0000_0000_000), // mem 0x80000-0xbffff
.s1_mask_2 (20'b1_1100_0000_0000_0000_000), // main memory
.s2_addr_1 (20'b1_0000_1111_1111_0010_000), // io 0xFF20 - 0xFF3E
.s2_mask_1 (20'b1_0000_1111_1111_1110_000), // Interrupt Control Registers
.s3_addr_1 (20'b1_0000_1111_1111_0101_000), // io 0xFF50 - 0xFF56
.s3_mask_1 (20'b1_0000_1111_1111_1111_100), // Timer Control 0 Registers
.s4_addr_1 (20'b1_0000_1111_1111_0101_100), // io 0xFF58 - 0xFF5E
.s4_mask_1 (20'b1_0000_1111_1111_1111_100), // Timer Control 1 Registers
.s5_addr_1 (20'b1_0000_1111_1111_0110_000), // io 0xFF60 - 0xFF66
.s5_mask_1 (20'b1_0000_1111_1111_1111_100), // Timer Control 2 Registers
.s6_addr_1 (20'b1_0000_1111_1111_1010_000), // io 0xFFA0 - 0xFFAF
.s6_mask_1 (20'b1_0000_1111_1111_1111_000), // Chip Select Control Registers
.s7_addr_1 (20'b1_0000_1111_1111_1100_000), // io 0xFFC0 - 0xFFCf
.s7_mask_1 (20'b1_0000_1111_1111_1111_000), // DMA Channel 0
.s8_addr_1 (20'b1_0000_0000_0000_1000_000), // io 0x0080 - 0x008E
.s8_mask_1 (20'b1_0000_1111_1111_1111_000), // Tube ULA
.s9_addr_1 (20'b1_0000_0000_0000_0000_000), // Unused
.s9_mask_1 (20'b1_0000_1111_1111_1111_000), //
.sA_addr_1 (20'b1_0000_0000_0000_0000_000), // Unused
.sA_mask_1 (20'b1_0000_1111_1111_1111_000), //
.sA_addr_2 (20'b1_0000_0000_0000_0000_000), // Unused
.sA_mask_2 (20'b1_0000_1111_1111_1111_000) //
) wbs (
// Master interface
.m_dat_i (dat_o),
.m_dat_o (sw_dat_o),
.m_adr_i ({tga,adr}),
.m_sel_i (sel),
.m_we_i (we),
.m_cyc_i (cyc),
.m_stb_i (stb),
.m_ack_o (ack),
// Slave 0 interface - bios rom
.s0_dat_i (rom_dat_o),
.s0_dat_o (rom_dat_i),
.s0_adr_o ({rom_tga_i,rom_adr_i}),
.s0_sel_o (rom_sel_i),
.s0_we_o (rom_we_i),
.s0_cyc_o (rom_cyc_i),
.s0_stb_o (rom_stb_i),
.s0_ack_i (rom_ack_o),
// Slave 1 interface - main memory
.s1_dat_i (ram_dat_o),
.s1_dat_o (ram_dat_i),
.s1_adr_o ({ram_tga_i,ram_adr_i}),
.s1_sel_o (ram_sel_i),
.s1_we_o (ram_we_i),
.s1_cyc_o (ram_cyc_i),
.s1_stb_o (ram_stb_i),
.s1_ack_i (ram_ack_o),
// Slave 2 interface - Interrupt Control
.s2_dat_i (16'h0000),
.s2_dat_o (),
.s2_adr_o (),
.s2_sel_o (),
.s2_we_o (),
.s2_cyc_o (s2_cyc_i),
.s2_stb_o (s2_stb_i),
.s2_ack_i (s2_cyc_i && s2_stb_i),
// Slave 3 interface - Timer Control 0
.s3_dat_i (16'h0000),
.s3_dat_o (),
.s3_adr_o (),
.s3_sel_o (),
.s3_we_o (),
.s3_cyc_o (s3_cyc_i),
.s3_stb_o (s3_stb_i),
.s3_ack_i (s3_cyc_i && s3_stb_i),
// Slave 4 interface - Timer Control 1
.s4_dat_i (16'h0000),
.s4_dat_o (),
.s4_adr_o (),
.s4_sel_o (),
.s4_we_o (),
.s4_cyc_o (s4_cyc_i),
.s4_stb_o (s4_stb_i),
.s4_ack_i (s4_cyc_i && s4_stb_i),
// Slave 5 interface - Timer Control 2
.s5_dat_i (16'h0000),
.s5_dat_o (),
.s5_adr_o (),
.s5_sel_o (),
.s5_we_o (),
.s5_cyc_o (s5_cyc_i),
.s5_stb_o (s5_stb_i),
.s5_ack_i (s5_cyc_i && s5_stb_i),
// Slave 6 interface - Chip Select Registers
.s6_dat_i (16'h0000),
.s6_dat_o (),
.s6_adr_o (),
.s6_sel_o (),
.s6_we_o (),
.s6_cyc_o (s6_cyc_i),
.s6_stb_o (s6_stb_i),
.s6_ack_i (s6_cyc_i && s6_stb_i),
// Slave 7 interface - DMA Channel 0
.s7_dat_i (16'h0000),
.s7_dat_o (),
.s7_adr_o (),
.s7_sel_o (),
.s7_we_o (),
.s7_cyc_o (s7_cyc_i),
.s7_stb_o (s7_stb_i),
.s7_ack_i (s7_cyc_i && s7_stb_i),
// Slave 8 interface - Tube
.s8_dat_i (tube_dat_o),
.s8_dat_o (tube_dat_i),
.s8_adr_o ({tube_tga_i,tube_adr_i}),
.s8_sel_o (tube_sel_i),
.s8_we_o (tube_we_i),
.s8_cyc_o (tube_cyc_i),
.s8_stb_o (tube_stb_i),
.s8_ack_i (tube_ack_o),
// Slave 9 interface - not connected
.s9_dat_i (16'h0000),
.s9_dat_o (),
.s9_adr_o (),
.s9_sel_o (),
.s9_we_o (),
.s9_cyc_o (s9_cyc_i),
.s9_stb_o (s9_stb_i),
.s9_ack_i (s9_cyc_i && s9_stb_i),
// Slave A interface - not connected
.sA_dat_i (16'h0000),
.sA_dat_o (),
.sA_adr_o (),
.sA_sel_o (),
.sA_we_o (),
.sA_cyc_o (sa_cyc_i),
.sA_stb_o (sa_stb_i),
.sA_ack_i (sa_cyc_i && sa_stb_i),
// Slave B interface - default
.sB_dat_i (16'h0000),
.sB_dat_o (),
.sB_adr_o (),
.sB_sel_o (),
.sB_we_o (),
.sB_cyc_o (def_cyc_i),
.sB_stb_o (def_stb_i),
.sB_ack_i (def_cyc_i & def_stb_i)
);
assign nmi = 0;
assign intv[0] = ~p_irq_b;
assign intv[4:1] = 0;
assign dat_i = nmia ? 16'h0002 :
(inta ? { 13'b0000_0000_0000_1, iid } :
sw_dat_o);
assign test = 0;
assign dack_b = 1;
assign fcs = 0;
assign tp = 0;
endmodule
|
/*
* Copyright (c) 2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This module tests the basic behavior of a tri0 register. We use a ?:
* to turn on/off the driver to the tri0 net and watch its value.
* A tri0 net should pull to 0 when undriven, and follow the driver
* otherwise.
*/
module main;
reg enable, val;
tri0 t0 = (~enable) ? 1'bz : val;
initial begin
enable = 0;
val = 0;
#1 if (t0 !== 1'b0) begin
$display("FAILED -- undriven t0 == %b", t0);
$finish;
end
enable = 1;
#1 if (t0 !== 1'b0) begin
$display("FAILED -- driven-0 t0 == %b", t0);
$finish;
end
val = 1;
#1 if (t0 !== 1'b1) begin
$display("FAILED -- driven-1 t0 == %b", t0);
$finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : bank_compare.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// This block stores the request for this bank machine.
//
// All possible new requests are compared against the request stored
// here. The compare results are shared with the bank machines and
// is used to determine where to enqueue a new request.
`timescale 1ps/1ps
module mig_7series_v4_0_bank_compare #
(parameter BANK_WIDTH = 3,
parameter TCQ = 100,
parameter BURST_MODE = "8",
parameter COL_WIDTH = 12,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter ECC = "OFF",
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter ROW_WIDTH = 16)
(/*AUTOARG*/
// Outputs
req_data_buf_addr_r, req_periodic_rd_r, req_size_r, rd_wr_r,
req_rank_r, req_bank_r, req_row_r, req_wr_r, req_priority_r,
rb_hit_busy_r, rb_hit_busy_ns, row_hit_r, maint_hit, col_addr,
req_ras, req_cas, row_cmd_wr, row_addr, rank_busy_r,
// Inputs
clk, idle_ns, idle_r, data_buf_addr, periodic_rd_insert, size, cmd,
sending_col, rank, periodic_rd_rank_r, bank, row, col, hi_priority,
maint_rank_r, maint_zq_r, maint_sre_r, auto_pre_r, rd_half_rmw, act_wait_r
);
input clk;
input idle_ns;
input idle_r;
input [DATA_BUF_ADDR_WIDTH-1:0]data_buf_addr;
output reg [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_r;
wire [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_ns =
idle_r
? data_buf_addr
: req_data_buf_addr_r;
always @(posedge clk) req_data_buf_addr_r <= #TCQ req_data_buf_addr_ns;
input periodic_rd_insert;
reg req_periodic_rd_r_lcl;
wire req_periodic_rd_ns = idle_ns
? periodic_rd_insert
: req_periodic_rd_r_lcl;
always @(posedge clk) req_periodic_rd_r_lcl <= #TCQ req_periodic_rd_ns;
output wire req_periodic_rd_r;
assign req_periodic_rd_r = req_periodic_rd_r_lcl;
input size;
wire req_size_r_lcl;
generate
if (BURST_MODE == "4") begin : burst_mode_4
assign req_size_r_lcl = 1'b0;
end
else
if (BURST_MODE == "8") begin : burst_mode_8
assign req_size_r_lcl = 1'b1;
end
else
if (BURST_MODE == "OTF") begin : burst_mode_otf
reg req_size;
wire req_size_ns = idle_ns
? (periodic_rd_insert || size)
: req_size;
always @(posedge clk) req_size <= #TCQ req_size_ns;
assign req_size_r_lcl = req_size;
end
endgenerate
output wire req_size_r;
assign req_size_r = req_size_r_lcl;
input [2:0] cmd;
reg [2:0] req_cmd_r;
wire [2:0] req_cmd_ns = idle_ns
? (periodic_rd_insert ? 3'b001 : cmd)
: req_cmd_r;
always @(posedge clk) req_cmd_r <= #TCQ req_cmd_ns;
`ifdef MC_SVA
rd_wr_only_wo_ecc: assert property
(@(posedge clk) ((ECC != "OFF") || idle_ns || ~|req_cmd_ns[2:1]));
`endif
input sending_col;
reg rd_wr_r_lcl;
wire rd_wr_ns = idle_ns
? ((req_cmd_ns[1:0] == 2'b11) || req_cmd_ns[0])
: ~sending_col && rd_wr_r_lcl;
always @(posedge clk) rd_wr_r_lcl <= #TCQ rd_wr_ns;
output wire rd_wr_r;
assign rd_wr_r = rd_wr_r_lcl;
input [RANK_WIDTH-1:0] rank;
input [RANK_WIDTH-1:0] periodic_rd_rank_r;
reg [RANK_WIDTH-1:0] req_rank_r_lcl = {RANK_WIDTH{1'b0}};
reg [RANK_WIDTH-1:0] req_rank_ns = {RANK_WIDTH{1'b0}};
generate
if (RANKS != 1) begin
always @(/*AS*/idle_ns or periodic_rd_insert
or periodic_rd_rank_r or rank or req_rank_r_lcl) req_rank_ns = idle_ns
? periodic_rd_insert
? periodic_rd_rank_r
: rank
: req_rank_r_lcl;
always @(posedge clk) req_rank_r_lcl <= #TCQ req_rank_ns;
end
endgenerate
output wire [RANK_WIDTH-1:0] req_rank_r;
assign req_rank_r = req_rank_r_lcl;
input [BANK_WIDTH-1:0] bank;
reg [BANK_WIDTH-1:0] req_bank_r_lcl;
wire [BANK_WIDTH-1:0] req_bank_ns = idle_ns ? bank : req_bank_r_lcl;
always @(posedge clk) req_bank_r_lcl <= #TCQ req_bank_ns;
output wire[BANK_WIDTH-1:0] req_bank_r;
assign req_bank_r = req_bank_r_lcl;
input [ROW_WIDTH-1:0] row;
reg [ROW_WIDTH-1:0] req_row_r_lcl;
wire [ROW_WIDTH-1:0] req_row_ns = idle_ns ? row : req_row_r_lcl;
always @(posedge clk) req_row_r_lcl <= #TCQ req_row_ns;
output wire [ROW_WIDTH-1:0] req_row_r;
assign req_row_r = req_row_r_lcl;
// Make req_col_r as wide as the max row address. This
// makes it easier to deal with indexing different column widths.
input [COL_WIDTH-1:0] col;
reg [15:0] req_col_r = 16'b0;
wire [COL_WIDTH-1:0] req_col_ns = idle_ns ? col : req_col_r[COL_WIDTH-1:0];
always @(posedge clk) req_col_r[COL_WIDTH-1:0] <= #TCQ req_col_ns;
reg req_wr_r_lcl;
wire req_wr_ns = idle_ns
? ((req_cmd_ns[1:0] == 2'b11) || ~req_cmd_ns[0])
: req_wr_r_lcl;
always @(posedge clk) req_wr_r_lcl <= #TCQ req_wr_ns;
output wire req_wr_r;
assign req_wr_r = req_wr_r_lcl;
input hi_priority;
output reg req_priority_r;
wire req_priority_ns = idle_ns ? hi_priority : req_priority_r;
always @(posedge clk) req_priority_r <= #TCQ req_priority_ns;
wire rank_hit = (req_rank_r_lcl == (periodic_rd_insert
? periodic_rd_rank_r
: rank));
wire bank_hit = (req_bank_r_lcl == bank);
wire rank_bank_hit = rank_hit && bank_hit;
output reg rb_hit_busy_r; // rank-bank hit on non idle row machine
wire rb_hit_busy_ns_lcl;
assign rb_hit_busy_ns_lcl = rank_bank_hit && ~idle_ns;
output wire rb_hit_busy_ns;
assign rb_hit_busy_ns = rb_hit_busy_ns_lcl;
wire row_hit_ns = (req_row_r_lcl == row);
output reg row_hit_r;
always @(posedge clk) rb_hit_busy_r <= #TCQ rb_hit_busy_ns_lcl;
always @(posedge clk) row_hit_r <= #TCQ row_hit_ns;
input [RANK_WIDTH-1:0] maint_rank_r;
input maint_zq_r;
input maint_sre_r;
output wire maint_hit;
assign maint_hit = (req_rank_r_lcl == maint_rank_r) || maint_zq_r || maint_sre_r;
// Assemble column address. Structure to be the same
// width as the row address. This makes it easier
// for the downstream muxing. Depending on the sizes
// of the row and column addresses, fill in as appropriate.
input auto_pre_r;
input rd_half_rmw;
reg [15:0] col_addr_template = 16'b0;
always @(/*AS*/auto_pre_r or rd_half_rmw or req_col_r
or req_size_r_lcl) begin
col_addr_template = req_col_r;
col_addr_template[10] = auto_pre_r && ~rd_half_rmw;
col_addr_template[11] = req_col_r[10];
col_addr_template[12] = req_size_r_lcl;
col_addr_template[13] = req_col_r[11];
end
output wire [ROW_WIDTH-1:0] col_addr;
assign col_addr = col_addr_template[ROW_WIDTH-1:0];
output wire req_ras;
output wire req_cas;
output wire row_cmd_wr;
input act_wait_r;
assign req_ras = 1'b0;
assign req_cas = 1'b1;
assign row_cmd_wr = act_wait_r;
output reg [ROW_WIDTH-1:0] row_addr;
always @(/*AS*/act_wait_r or req_row_r_lcl) begin
row_addr = req_row_r_lcl;
// This causes all precharges to be precharge single bank command.
if (~act_wait_r) row_addr[10] = 1'b0;
end
// Indicate which, if any, rank this bank machine is busy with.
// Not registering the result would probably be more accurate, but
// would create timing issues. This is used for refresh banking, perfect
// accuracy is not required.
localparam ONE = 1;
output reg [RANKS-1:0] rank_busy_r;
wire [RANKS-1:0] rank_busy_ns = {RANKS{~idle_ns}} & (ONE[RANKS-1:0] << req_rank_ns);
always @(posedge clk) rank_busy_r <= #TCQ rank_busy_ns;
endmodule // bank_compare
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__UDP_DLATCH_PR_SYMBOL_V
`define SKY130_FD_SC_MS__UDP_DLATCH_PR_SYMBOL_V
/**
* udp_dlatch$PR: D-latch, gated clear direct / gate active high
* (Q output UDP)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__udp_dlatch$PR (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET,
//# {{clocks|Clocking}}
input GATE
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__UDP_DLATCH_PR_SYMBOL_V
|
// -*- verilog -*-
// Copyright (c) 2012 Ben Reynwar
// Released under MIT License (see LICENSE.txt)
// A qa_wrapper with a splitter and message_stream_combiner
module qa_wrapper
#(
parameter WDTH = 32
)
(
input wire clk,
input wire reset,
input wire [WDTH-1:0] in_data,
input wire in_nd,
output reg [WDTH-1:0] out_data,
output reg out_nd
);
// Separate the input stream into a sample stream and a message stream.
wire [WDTH-1:0] mid1_data;
wire [WDTH-1:0] mid2_data;
wire [WDTH-1:0] staged_data;
wire staged_nd;
wire mid_nd;
wire splitter_error;
wire rst_n;
assign rst_n = ~reset;
split #(2, 1) split_0
(.clk(clk),
.rst_n(rst_n),
.in_data(in_data),
.in_nd(in_nd),
.out_data({mid1_data, mid2_data}),
.out_nd(mid_nd)
);
message_stream_combiner
#(2, 1, WDTH, `COMBINER_BUFFER_LENGTH, `LOG_COMBINER_BUFFER_LENGTH,
`MAX_PACKET_LENGTH, `MSG_LENGTH_WIDTH)
message_stream_combiner_0
(.clk(clk),
.rst_n(rst_n),
.in_data({mid1_data, mid2_data}),
.in_nd({mid_nd, mid_nd}),
.out_data(staged_data),
.out_nd(staged_nd),
.error(combiner_error)
);
always @ (posedge clk)
begin
if (combiner_error)
begin
out_nd <= 1'b1;
out_data <= `ERRORCODE;
end
else
begin
out_nd <= staged_nd;
out_data <= staged_data;
end
end
endmodule |
//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: wr_data_gen.v
// /___/ /\ Date Last Modified:
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose:
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module wr_data_gen #
(
parameter TCQ = 100,
parameter FAMILY = "SPARTAN6", // "SPARTAN6", "VIRTEX6"
parameter MEM_BURST_LEN = 8,
parameter MODE = "WR", //"WR", "RD"
parameter ADDR_WIDTH = 32,
parameter BL_WIDTH = 6,
parameter DWIDTH = 32,
parameter DATA_PATTERN = "DGEN_PRBS", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
parameter NUM_DQ_PINS = 8,
parameter SEL_VICTIM_LINE = 3, // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
parameter COLUMN_WIDTH = 10,
parameter EYE_TEST = "FALSE"
)
(
input clk_i, //
input [4:0] rst_i,
input [31:0] prbs_fseed_i,
input [3:0] data_mode_i, // "00" = bram;
output cmd_rdy_o, // ready to receive command. It should assert when data_port is ready at the // beginning and will be deasserted once see the cmd_valid_i is asserted.
// And then it should reasserted when
// it is generating the last_word.
input cmd_valid_i, // when both cmd_valid_i and cmd_rdy_o is high, the command is valid.
input cmd_validB_i,
input cmd_validC_i,
output last_word_o,
// input [5:0] port_data_counts_i,// connect to data port fifo counts
input [ADDR_WIDTH-1:0] m_addr_i,
input [DWIDTH-1:0] fixed_data_i,
input [ADDR_WIDTH-1:0] addr_i, // generated address used to determine data pattern.
input [BL_WIDTH-1:0] bl_i, // generated burst length for control the burst data
input data_rdy_i, // connect from mcb_wr_full when used as wr_data_gen
// connect from mcb_rd_empty when used as rd_data_gen
// When both data_rdy and data_valid is asserted, the ouput data is valid.
output data_valid_o, // connect to wr_en or rd_en and is asserted whenever the
// pattern is available.
output [DWIDTH-1:0] data_o, // generated data pattern
output reg data_wr_end_o
);
//
reg [DWIDTH-1:0] data;
(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg cmd_rdy,cmd_rdyB, cmd_rdyC,cmd_rdyD,cmd_rdyE,cmd_rdyF;
(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg cmd_start,cmd_startB,cmd_startC,cmd_startD,cmd_startE,cmd_startF;
reg burst_count_reached2;
reg data_valid;
reg [6:0]user_burst_cnt;
reg [2:0] walk_cnt;
wire fifo_not_full;
integer i,j;
reg [31:0] w3data;
assign fifo_not_full = data_rdy_i;
always @( posedge clk_i)
begin
if ((user_burst_cnt == 2 || (cmd_start && bl_i == 1 && FAMILY == "VIRTEX6")) && (fifo_not_full))
data_wr_end_o <= #TCQ 1'b1;
else
data_wr_end_o <= #TCQ 1'b0;
end
always @ (posedge clk_i)
begin
cmd_start <= #TCQ cmd_validC_i & cmd_rdyC ;
cmd_startB <= #TCQ cmd_valid_i & cmd_rdyB;
cmd_startC <= #TCQ cmd_validB_i & cmd_rdyC;
cmd_startD <= #TCQ cmd_validB_i & cmd_rdyD;
cmd_startE <= #TCQ cmd_validB_i & cmd_rdyE;
cmd_startF <= #TCQ cmd_validB_i & cmd_rdyF;
end
// counter to count user burst length
always @( posedge clk_i)
begin
if ( rst_i[0] )
user_burst_cnt <= #TCQ 'd0;
else if(cmd_start)
if (FAMILY == "SPARTAN6") begin
if (bl_i == 6'b000000)
user_burst_cnt <= #TCQ 7'b1000000;
else
user_burst_cnt <= #TCQ bl_i;
end
else
user_burst_cnt <= #TCQ bl_i;
else if(fifo_not_full)
if (user_burst_cnt != 6'd0)
user_burst_cnt <= #TCQ user_burst_cnt - 1'b1;
else
user_burst_cnt <=#TCQ 'd0;
end
reg u_bcount_2;
wire last_word_t;
always @ (posedge clk_i)
begin
if ((user_burst_cnt == 2 && fifo_not_full )|| (cmd_startC && bl_i == 1))
u_bcount_2 <= #TCQ 1'b1;
else if (last_word_o)
u_bcount_2 <= #TCQ 1'b0;
end
assign last_word_o = u_bcount_2 & fifo_not_full;
// cmd_rdy_o assert when the dat fifo is not full and deassert once cmd_valid_i
// is assert and reassert during the last data
assign cmd_rdy_o = cmd_rdy & fifo_not_full;
always @( posedge clk_i)
begin
if ( rst_i[0] )
cmd_rdy <= #TCQ 1'b1;
else if (cmd_start)
if (bl_i == 1)
cmd_rdy <= #TCQ 1'b1;
else
cmd_rdy <= #TCQ 1'b0;
else if ((user_burst_cnt == 6'd2 && fifo_not_full ) )
cmd_rdy <= #TCQ 1'b1;
end
always @( posedge clk_i)
begin
if ( rst_i [0])
cmd_rdyB <= #TCQ 1'b1;
else if (cmd_startB)
if (bl_i == 1)
cmd_rdyB <= #TCQ 1'b1;
else
cmd_rdyB <= #TCQ 1'b0;
else if ((user_burst_cnt == 6'd2 && fifo_not_full ) )
cmd_rdyB <= #TCQ 1'b1;
end
always @( posedge clk_i)
begin
if ( rst_i[0] )
cmd_rdyC <= #TCQ 1'b1;
else if (cmd_startC)
if (bl_i == 1)
cmd_rdyC <= #TCQ 1'b1;
else
cmd_rdyC <= #TCQ 1'b0;
else if ((user_burst_cnt == 6'd2 && fifo_not_full ) )
cmd_rdyC <= #TCQ 1'b1;
end
always @( posedge clk_i)
begin
if ( rst_i[0] )
cmd_rdyD <= #TCQ 1'b1;
else if (cmd_startD)
if (bl_i == 1)
cmd_rdyD <= #TCQ 1'b1;
else
cmd_rdyD <= #TCQ 1'b0;
else if ((user_burst_cnt == 6'd2 && fifo_not_full ) )
cmd_rdyD <= #TCQ 1'b1;
end
always @( posedge clk_i)
begin
if ( rst_i[0] )
cmd_rdyE <= #TCQ 1'b1;
else if (cmd_startE)
if (bl_i == 1)
cmd_rdyE <= #TCQ 1'b1;
else
cmd_rdyE <= #TCQ 1'b0;
else if ((user_burst_cnt == 6'd2 && fifo_not_full ) )
cmd_rdyE <= #TCQ 1'b1;
end
always @( posedge clk_i)
begin
if ( rst_i[0] )
cmd_rdyF <= #TCQ 1'b1;
else if (cmd_startF)
if (bl_i == 1)
cmd_rdyF <= #TCQ 1'b1;
else
cmd_rdyF <= #TCQ 1'b0;
else if ((user_burst_cnt == 6'd2 && fifo_not_full ) )
cmd_rdyF <= #TCQ 1'b1;
end
always @ (posedge clk_i)
begin
if (rst_i[1])
data_valid <= #TCQ 'd0;
else if(cmd_start)
data_valid <= #TCQ 1'b1;
else if (fifo_not_full && user_burst_cnt <= 6'd1)
data_valid <= #TCQ 1'b0;
end
assign data_valid_o = data_valid & fifo_not_full;
generate
if (FAMILY == "SPARTAN6") begin : SP6_WDGEN
sp6_data_gen #
(
.TCQ (TCQ),
.ADDR_WIDTH (32 ),
.BL_WIDTH (BL_WIDTH ),
.DWIDTH (DWIDTH ),
.DATA_PATTERN (DATA_PATTERN ),
.NUM_DQ_PINS (NUM_DQ_PINS ),
.COLUMN_WIDTH (COLUMN_WIDTH)
)
sp6_data_gen
(
.clk_i (clk_i ),
.rst_i (rst_i[1] ),
.data_rdy_i (data_rdy_i ),
.prbs_fseed_i (prbs_fseed_i),
.data_mode_i (data_mode_i ),
.cmd_startA (cmd_start ),
.cmd_startB (cmd_startB ),
.cmd_startC (cmd_startC ),
.cmd_startD (cmd_startD ),
.cmd_startE (cmd_startE ),
.fixed_data_i (fixed_data_i),
.addr_i (addr_i ),
.user_burst_cnt (user_burst_cnt),
.fifo_rdy_i (fifo_not_full ),
.data_o (data_o )
);
end
endgenerate
generate
if (FAMILY == "VIRTEX6") begin : V6_WDGEN
v6_data_gen #
(
.TCQ (TCQ),
.ADDR_WIDTH (32 ),
.BL_WIDTH (BL_WIDTH ),
.DWIDTH (DWIDTH ),
.MEM_BURST_LEN (MEM_BURST_LEN),
.DATA_PATTERN (DATA_PATTERN ),
.NUM_DQ_PINS (NUM_DQ_PINS ),
.SEL_VICTIM_LINE (SEL_VICTIM_LINE),
.COLUMN_WIDTH (COLUMN_WIDTH),
.EYE_TEST (EYE_TEST)
)
v6_data_gen
(
.clk_i (clk_i ),
.rst_i (rst_i[1] ),
.data_rdy_i (data_rdy_i ),
.prbs_fseed_i (prbs_fseed_i),
.data_mode_i (data_mode_i ),
.cmd_startA (cmd_start ),
.cmd_startB (cmd_startB ),
.cmd_startC (cmd_startC ),
.cmd_startD (cmd_startD ),
.cmd_startE (cmd_startE ),
.m_addr_i (m_addr_i ),
.fixed_data_i (fixed_data_i),
.addr_i (addr_i ),
.user_burst_cnt (user_burst_cnt),
.fifo_rdy_i (fifo_not_full ),
.data_o (data_o )
);
end
endgenerate
endmodule
|
module MEM (
input rst,
input FWLS,
input[`RegDataWidth-1:0] reg_data_2,
input[`RegDataWidth-1:0] WB_data,
input[`RegDataWidth-1:0] raw_mem_data,
input ReadMem,
input WriteMem,
input[`RegDataWidth-1:0] mem_addr,
input[`OpcodeWidth-1:0] opcode,
output[`RegDataWidth-1:0] data_to_write_mem,
output[`RegDataWidth-1:0] data_to_reg,
output reg[`ByteSlctWidth-1:0] byte_slct
);
wire[`RegDataWidth-1:0] raw_reg_data;
wire[`ByteSlctWidth-1:0] byte_slct_b;
wire[`ByteSlctWidth-1:0] byte_slct_h;
assign byte_slct_b = `ByteSlctWidth'b1000 >> mem_addr[1:0];
assign byte_slct_h = `ByteSlctWidth'b1100 >> mem_addr[1:0];
always @(*) begin : proc_byte_slct_gen
case (opcode)
`mips_lb : byte_slct <= byte_slct_b;
`mips_lh : byte_slct <= byte_slct_h;
`mips_lw : byte_slct <= `ByteSlctWidth'b1111;
`mips_lbu : byte_slct <= byte_slct_b;
`mips_lhu : byte_slct <= byte_slct_h;
`mips_sb : byte_slct <= byte_slct_b;
`mips_sh : byte_slct <= byte_slct_h;
`mips_sw : byte_slct <= `ByteSlctWidth'b1111;
default : byte_slct <= 0;
endcase
end
mux2x1 #(.data_width(`RegDataWidth)) forwardLS(
.in_0(reg_data_2),
.in_1(WB_data),
.slct(FWLS),
.out(raw_reg_data)
);
WM_ctrl write_control(
.rst(rst),
.raw_reg_data(raw_reg_data),
.opcode(opcode),
.data_to_mem(data_to_write_mem)
);
RM_ctrl read_control(
.rst(rst),
.byte_slct(byte_slct),
.opcode(opcode),
.raw_mem_data(raw_mem_data),
.data_to_reg(data_to_reg)
);
endmodule |
`timescale 1 ps / 1 ps
module alt_mem_ddrx_buffer_manager
# (
parameter
CFG_BUFFER_ADDR_WIDTH = 6
)
(
// port list
ctl_clk,
ctl_reset_n,
// write interface
writeif_ready,
writeif_valid,
writeif_address,
writeif_address_blocked,
// buffer write interface
buffwrite_valid,
buffwrite_address,
// read interface
readif_valid,
readif_address,
// buffer read interface
buffread_valid,
buffread_datavalid,
buffread_address
);
// -----------------------------
// local parameter declarations
// -----------------------------
localparam CTL_BUFFER_DEPTH = two_pow_N(CFG_BUFFER_ADDR_WIDTH);
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk;
input ctl_reset_n;
// write interface
output writeif_ready;
input writeif_valid;
input [CFG_BUFFER_ADDR_WIDTH-1:0] writeif_address;
input writeif_address_blocked;
// buffer write interface
output buffwrite_valid;
output [CFG_BUFFER_ADDR_WIDTH-1:0] buffwrite_address;
// read data interface
input readif_valid;
input [CFG_BUFFER_ADDR_WIDTH-1:0] readif_address;
// buffer read interface
output buffread_valid;
output buffread_datavalid;
output [CFG_BUFFER_ADDR_WIDTH-1:0] buffread_address;
// -----------------------------
// port type declaration
// -----------------------------
wire ctl_clk;
wire ctl_reset_n;
// write interface
reg writeif_ready;
wire writeif_valid;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] writeif_address;
wire writeif_address_blocked;
// buffer write interface
wire buffwrite_valid;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] buffwrite_address;
// read data interface
wire readif_valid;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] readif_address;
// buffer read interface
wire buffread_valid;
reg buffread_datavalid;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] buffread_address;
// -----------------------------
// signal declaration
// -----------------------------
wire writeif_accepted;
reg [CTL_BUFFER_DEPTH-1:0] mux_writeif_ready;
reg [CTL_BUFFER_DEPTH-1:0] buffer_valid_array;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] buffer_valid_counter;
reg err_buffer_valid_counter_overflow;
// -----------------------------
// module definition
// -----------------------------
assign writeif_accepted = writeif_ready & writeif_valid;
assign buffwrite_address = writeif_address;
assign buffwrite_valid = writeif_accepted;
assign buffread_address = readif_address;
assign buffread_valid = readif_valid;
always @ (*)
begin
if (writeif_address_blocked)
begin
// can't write ahead of lowest address currently tracked by dataid array
writeif_ready = 1'b0;
end
else
begin
// buffer is full when every location has been written
writeif_ready = ~&buffer_valid_counter;
end
end
// generate buffread_datavalid.
// data is valid one cycle after adddress is presented to the buffer
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
buffread_datavalid <= 0;
end
else
begin
buffread_datavalid <= buffread_valid;
end
end
// genvar i;
// generate
// for (i = 0; i < CTL_BUFFER_DEPTH; i = i + 1)
// begin : gen_mux_buffer_valid_array_signals
// wire [CFG_BUFFER_ADDR_WIDTH-1:0] gen_buffer_address = i;
// always @ (posedge ctl_clk or negedge ctl_reset_n)
// begin
// if (~ctl_reset_n)
// begin
// //reset state ...
// buffer_valid_array [i] <= 0;
// end
// else
// begin
// //active state ...
// // write & read to same location won't happen on same time
// // write
// if ( (writeif_address == gen_buffer_address) & writeif_accepted)
// begin
// buffer_valid_array[i] <= 1;
// end
// // read
// if ( (readif_address== gen_buffer_address) & readif_valid)
// begin
// buffer_valid_array[i] <= 0;
// end
// end
// end
// always @ (*)
// begin
// // mano - fmax !
// if ( (writeif_address == gen_buffer_address) & buffer_valid_array[i] )
// begin
// mux_writeif_ready[i] = 0;
// end
// else
// begin
// mux_writeif_ready[i] = 1;
// end
// end
// end
// endgenerate
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
buffer_valid_counter <= 0;
err_buffer_valid_counter_overflow <= 0;
end
else
begin
if (writeif_accepted & readif_valid)
begin
// write & read at same time
buffer_valid_counter <= buffer_valid_counter;
end
else if (writeif_accepted)
begin
// write only
{err_buffer_valid_counter_overflow, buffer_valid_counter} <= buffer_valid_counter + 1;
end
else if (readif_valid)
begin
// read only
buffer_valid_counter <= buffer_valid_counter - 1;
end
else
begin
buffer_valid_counter <= buffer_valid_counter;
end
end
end
function integer two_pow_N;
input integer value;
begin
two_pow_N = 2 << (value-1);
end
endfunction
endmodule
//
// assert
//
// - write & read to same location happen on same time
|
// ZX-Evo Base Configuration (c) NedoPC 2008,2009,2010,2011,2012,2013,2014
//
// fetches video data for renderer
/*
This file is part of ZX-Evo Base Configuration firmware.
ZX-Evo Base Configuration firmware is free software:
you can redistribute it and/or modify it under the terms of
the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
ZX-Evo Base Configuration firmware is distributed in the hope that
it will be useful, but WITHOUT ANY WARRANTY; without even
the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with ZX-Evo Base Configuration firmware.
If not, see <http://www.gnu.org/licenses/>.
*/
`include "../include/tune.v"
module video_fetch(
input wire clk, // 28 MHz clock
input wire cend, // general
input wire pre_cend, // synchronization
input wire vpix, // vertical window
input wire fetch_start, // fetching start and stop
input wire fetch_end, //
output reg fetch_sync, // 1 cycle after cend
input wire [15:0] video_data, // video data receiving from dram arbiter
input wire video_strobe, //
output reg video_go, // indicates need for data
output reg [63:0] pic_bits // picture bits -- data for renderer
// currently, video_fetch assigns that there are only 1/8 and 1/4
// bandwidth. !!needs correction for higher bandwidths!!
);
reg [3:0] fetch_sync_ctr; // generates fetch_sync to synchronize
// fetch cycles (each 16 dram cycles long)
// fetch_sync coincides with cend
reg [1:0] fetch_ptr; // pointer to fill pic_bits buffer
reg fetch_ptr_clr; // clears fetch_ptr
reg [15:0] fetch_data [0:3]; // stores data fetched from memory
// fetch window
always @(posedge clk)
if( fetch_start && vpix )
video_go <= 1'b1;
else if( fetch_end )
video_go <= 1'b0;
// fetch sync counter
always @(posedge clk) if( cend )
begin
if( fetch_start )
fetch_sync_ctr <= 0;
else
fetch_sync_ctr <= fetch_sync_ctr + 1;
end
// fetch sync signal
always @(posedge clk)
if( (fetch_sync_ctr==1) && pre_cend )
fetch_sync <= 1'b1;
else
fetch_sync <= 1'b0;
// fetch_ptr clear signal
always @(posedge clk)
if( (fetch_sync_ctr==0) && pre_cend )
fetch_ptr_clr <= 1'b1;
else
fetch_ptr_clr <= 1'b0;
// buffer fill pointer
always @(posedge clk)
if( fetch_ptr_clr )
fetch_ptr <= 0;
else if( video_strobe )
fetch_ptr <= fetch_ptr + 1;
// store fetched data
always @(posedge clk) if( video_strobe )
fetch_data[fetch_ptr] <= video_data;
// pass fetched data to renderer
always @(posedge clk) if( fetch_sync )
begin
pic_bits[ 7:0 ] <= fetch_data[0][15:8 ];
pic_bits[15:8 ] <= fetch_data[0][ 7:0 ];
pic_bits[23:16] <= fetch_data[1][15:8 ];
pic_bits[31:24] <= fetch_data[1][ 7:0 ];
pic_bits[39:32] <= fetch_data[2][15:8 ];
pic_bits[47:40] <= fetch_data[2][ 7:0 ];
pic_bits[55:48] <= fetch_data[3][15:8 ];
pic_bits[63:56] <= fetch_data[3][ 7:0 ];
end
endmodule
|
// Test array variables inside a constant function
module constfunc14();
function [7:0] concat1(input [7:0] value);
reg [3:0] tmp[1:2];
begin
{tmp[1], tmp[2]} = {value[3:0], value[7:4]};
{concat1[3:0], concat1[7:4]} = {tmp[2], tmp[1]};
end
endfunction
function [7:0] concat2(input [7:0] value);
reg [3:0] tmp[1:2];
begin
{tmp[1], tmp[3]} = {value[3:0], value[7:4]};
{concat2[3:0], concat2[7:4]} = {tmp[3], tmp[1]};
end
endfunction
function [7:0] concat3(input [7:0] value);
reg [3:0] tmp[1:2];
begin
{tmp['bx], tmp[1]} = {value[3:0], value[7:4]};
{concat3[3:0], concat3[7:4]} = {tmp['bx], tmp[1]};
end
endfunction
localparam res1 = concat1(8'ha5);
localparam res2 = concat2(8'ha5);
localparam res3 = concat2(8'ha5);
reg failed = 0;
initial begin
$display("%h", res1); if (res1 !== 8'h5a) failed = 1;
$display("%h", res2); if (res2 !== 8'h5x) failed = 1;
$display("%h", res3); if (res3 !== 8'h5x) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
// -*- Mode: Verilog -*-
// Filename : wb_dump.v
// Description : Dump signals for waveform debugging
// Author : Philip Tracton
// Created On : Wed Dec 2 14:22:59 2015
// Last Modified By: Philip Tracton
// Last Modified On: Wed Dec 2 14:22:59 2015
// Update Count : 0
// Status : Unknown, Use with caution!
`include "simulation_includes.vh"
module dump;
reg [(64*8)-1:0] test_name;
initial
begin
test_name = `SIMULATION_NAME;
`ifdef NCVERILOG
//$shm_open("test.shm",0);
$shm_open({test_name,".shm"}, 0);
$shm_probe(`TB,"MAC");
`ifdef SOC
$shm_probe(`PROGRAM_ROM, "MAC");
`endif
`else
$dumpfile({test_name,".vcd"});
$dumpvars(0, `TB);
`ifndef RTL_SIM
$dumpvars(1, adxl362_testbench.adxl362.spi.fifo[0]);
$dumpvars(1, adxl362_testbench.adxl362.spi.fifo[1]);
$dumpvars(1, adxl362_testbench.adxl362.spi.fifo[2]);
$dumpvars(1, adxl362_testbench.adxl362.spi.fifo[3]);
$dumpvars(1, adxl362_testbench.adxl362.spi.fifo[4]);
$dumpvars(1, adxl362_testbench.adxl362.spi.fifo[5]);
$dumpvars(1, adxl362_testbench.adxl362.spi.fifo[6]);
$dumpvars(1, adxl362_testbench.adxl362.spi.fifo[7]);
`endif
`endif
end // initial begin
endmodule // test_top
|
// This is a component of pluto_step, a hardware step waveform generator
// Copyright 2007 Jeff Epler <[email protected]>
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
module stepgen(clk, enable, position, velocity, dirtime, steptime, step, dir, tap);
`define STATE_STEP 0
`define STATE_DIRCHANGE 1
`define STATE_DIRWAIT 2
parameter W=12;
parameter F=10;
parameter T=5;
input clk, enable;
output [W+F-1:0] position; reg [W+F-1:0] position;
input [F:0] velocity;
input [T-1:0] dirtime, steptime;
input [1:0] tap;
output step, dir;
reg step, dir;
reg [T-1:0] timer;
reg [1:0] state;
reg ones;
wire dbit = velocity[F];
wire pbit = (tap == 0 ? position[F]
: (tap == 1 ? position[F+1]
: (tap == 2 ? position[F+2]
: position[F+3])));
wire [W+F-1:0] xvelocity = {{W{velocity[F]}}, {1{velocity[F-1:0]}}};
`ifdef TESTING
// for testing:
initial position = 1'b0;
initial state = `STATE_STEP;
initial timer = 0;
initial dir = 0;
initial ones = 0;
`endif
always @(posedge clk) begin
if(enable) begin
// $display("state=%d timer=%d position=%h velocity=%h dir=%d dbit=%d pbit=%d ones=%d", state, timer, position, xvelocity, dir, dbit, pbit, ones);
if((dir != dbit) && (pbit == ones)) begin
if(state == `STATE_DIRCHANGE) begin
if(timer == 0) begin
dir <= dbit;
timer <= dirtime;
state <= `STATE_DIRWAIT;
end else begin
timer <= timer - 1'd1;
end
end else begin
if(timer == 0) begin
step <= 0;
timer <= dirtime;
state <= `STATE_DIRCHANGE;
end else begin
timer <= timer - 1'd1;
end
end
end else if(state == `STATE_DIRWAIT) begin
if(timer == 0) begin
state <= `STATE_STEP;
end else begin
timer <= timer - 1'd1;
end
end else begin
if(timer == 0) begin
if(pbit != ones) begin
ones <= pbit;
step <= 1'd1;
timer <= steptime;
end else begin
step <= 0;
end
end else begin
timer <= timer - 1'd1;
end
if(dir == dbit)
position <= position + xvelocity;
end
end
end
endmodule
|
// system_mm_interconnect_0.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.0 200 at 2015.05.04.18:11:36
`timescale 1 ps / 1 ps
module system_mm_interconnect_0 (
input wire acl_iface_kernel_clk_clk, // acl_iface_kernel_clk.clk
input wire Erosion_system_clock_reset_reset_reset_bridge_in_reset_reset, // Erosion_system_clock_reset_reset_reset_bridge_in_reset.reset
input wire [29:0] Erosion_system_avm_memgmem0_port_0_0_rw_address, // Erosion_system_avm_memgmem0_port_0_0_rw.address
output wire Erosion_system_avm_memgmem0_port_0_0_rw_waitrequest, // .waitrequest
input wire [4:0] Erosion_system_avm_memgmem0_port_0_0_rw_burstcount, // .burstcount
input wire [31:0] Erosion_system_avm_memgmem0_port_0_0_rw_byteenable, // .byteenable
input wire Erosion_system_avm_memgmem0_port_0_0_rw_read, // .read
output wire [255:0] Erosion_system_avm_memgmem0_port_0_0_rw_readdata, // .readdata
output wire Erosion_system_avm_memgmem0_port_0_0_rw_readdatavalid, // .readdatavalid
input wire Erosion_system_avm_memgmem0_port_0_0_rw_write, // .write
input wire [255:0] Erosion_system_avm_memgmem0_port_0_0_rw_writedata, // .writedata
output wire [29:0] acl_iface_kernel_mem0_address, // acl_iface_kernel_mem0.address
output wire acl_iface_kernel_mem0_write, // .write
output wire acl_iface_kernel_mem0_read, // .read
input wire [255:0] acl_iface_kernel_mem0_readdata, // .readdata
output wire [255:0] acl_iface_kernel_mem0_writedata, // .writedata
output wire [4:0] acl_iface_kernel_mem0_burstcount, // .burstcount
output wire [31:0] acl_iface_kernel_mem0_byteenable, // .byteenable
input wire acl_iface_kernel_mem0_readdatavalid, // .readdatavalid
input wire acl_iface_kernel_mem0_waitrequest, // .waitrequest
output wire acl_iface_kernel_mem0_debugaccess // .debugaccess
);
wire erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_waitrequest; // acl_iface_kernel_mem0_translator:uav_waitrequest -> Erosion_system_avm_memgmem0_port_0_0_rw_translator:uav_waitrequest
wire [9:0] erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_burstcount; // Erosion_system_avm_memgmem0_port_0_0_rw_translator:uav_burstcount -> acl_iface_kernel_mem0_translator:uav_burstcount
wire [255:0] erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_writedata; // Erosion_system_avm_memgmem0_port_0_0_rw_translator:uav_writedata -> acl_iface_kernel_mem0_translator:uav_writedata
wire [29:0] erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_address; // Erosion_system_avm_memgmem0_port_0_0_rw_translator:uav_address -> acl_iface_kernel_mem0_translator:uav_address
wire erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_lock; // Erosion_system_avm_memgmem0_port_0_0_rw_translator:uav_lock -> acl_iface_kernel_mem0_translator:uav_lock
wire erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_write; // Erosion_system_avm_memgmem0_port_0_0_rw_translator:uav_write -> acl_iface_kernel_mem0_translator:uav_write
wire erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_read; // Erosion_system_avm_memgmem0_port_0_0_rw_translator:uav_read -> acl_iface_kernel_mem0_translator:uav_read
wire [255:0] erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_readdata; // acl_iface_kernel_mem0_translator:uav_readdata -> Erosion_system_avm_memgmem0_port_0_0_rw_translator:uav_readdata
wire erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_debugaccess; // Erosion_system_avm_memgmem0_port_0_0_rw_translator:uav_debugaccess -> acl_iface_kernel_mem0_translator:uav_debugaccess
wire [31:0] erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_byteenable; // Erosion_system_avm_memgmem0_port_0_0_rw_translator:uav_byteenable -> acl_iface_kernel_mem0_translator:uav_byteenable
wire erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_readdatavalid; // acl_iface_kernel_mem0_translator:uav_readdatavalid -> Erosion_system_avm_memgmem0_port_0_0_rw_translator:uav_readdatavalid
altera_merlin_master_translator #(
.AV_ADDRESS_W (30),
.AV_DATA_W (256),
.AV_BURSTCOUNT_W (5),
.AV_BYTEENABLE_W (32),
.UAV_ADDRESS_W (30),
.UAV_BURSTCOUNT_W (10),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (32),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (1),
.UAV_CONSTANT_BURST_BEHAVIOR (1),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) erosion_system_avm_memgmem0_port_0_0_rw_translator (
.clk (acl_iface_kernel_clk_clk), // clk.clk
.reset (Erosion_system_clock_reset_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_read), // .read
.uav_write (erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (Erosion_system_avm_memgmem0_port_0_0_rw_address), // avalon_anti_master_0.address
.av_waitrequest (Erosion_system_avm_memgmem0_port_0_0_rw_waitrequest), // .waitrequest
.av_burstcount (Erosion_system_avm_memgmem0_port_0_0_rw_burstcount), // .burstcount
.av_byteenable (Erosion_system_avm_memgmem0_port_0_0_rw_byteenable), // .byteenable
.av_read (Erosion_system_avm_memgmem0_port_0_0_rw_read), // .read
.av_readdata (Erosion_system_avm_memgmem0_port_0_0_rw_readdata), // .readdata
.av_readdatavalid (Erosion_system_avm_memgmem0_port_0_0_rw_readdatavalid), // .readdatavalid
.av_write (Erosion_system_avm_memgmem0_port_0_0_rw_write), // .write
.av_writedata (Erosion_system_avm_memgmem0_port_0_0_rw_writedata), // .writedata
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponserequest (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (30),
.AV_DATA_W (256),
.UAV_DATA_W (256),
.AV_BURSTCOUNT_W (5),
.AV_BYTEENABLE_W (32),
.UAV_BYTEENABLE_W (32),
.UAV_ADDRESS_W (30),
.UAV_BURSTCOUNT_W (10),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (32),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) acl_iface_kernel_mem0_translator (
.clk (acl_iface_kernel_clk_clk), // clk.clk
.reset (Erosion_system_clock_reset_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_address), // avalon_universal_slave_0.address
.uav_burstcount (erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_read), // .read
.uav_write (erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (erosion_system_avm_memgmem0_port_0_0_rw_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (acl_iface_kernel_mem0_address), // avalon_anti_slave_0.address
.av_write (acl_iface_kernel_mem0_write), // .write
.av_read (acl_iface_kernel_mem0_read), // .read
.av_readdata (acl_iface_kernel_mem0_readdata), // .readdata
.av_writedata (acl_iface_kernel_mem0_writedata), // .writedata
.av_burstcount (acl_iface_kernel_mem0_burstcount), // .burstcount
.av_byteenable (acl_iface_kernel_mem0_byteenable), // .byteenable
.av_readdatavalid (acl_iface_kernel_mem0_readdatavalid), // .readdatavalid
.av_waitrequest (acl_iface_kernel_mem0_waitrequest), // .waitrequest
.av_debugaccess (acl_iface_kernel_mem0_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge ([email protected])
// sqrt_pipelined.v
// Created: 4.2.2012
// Modified: 4.5.2012
//
// Implements a fixed-point parameterized pipelined square root
// operation on an unsigned input of any bit length. The number of
// stages in the pipeline is equal to the number of output bits in the
// computation. This pipelien sustains a throughput of one computation
// per clock cycle.
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module sqrt_pipelined
(
input clk, // clock
input reset_n, // asynchronous reset
input start, // optional start signal
input [INPUT_BITS-1:0] radicand, // unsigned radicand
output reg data_valid, // optional data valid signal
output reg [OUTPUT_BITS-1:0] root // unsigned root
);
// WARNING!!! THESE PARAMETERS ARE INTENDED TO BE MODIFIED IN A TOP
// LEVEL MODULE. LOCAL CHANGES HERE WILL, MOST LIKELY, BE
// OVERWRITTEN!
parameter
INPUT_BITS = 16; // number of input bits (any integer)
localparam
OUTPUT_BITS = INPUT_BITS / 2 + INPUT_BITS % 2; // number of output bits
reg [OUTPUT_BITS-1:0] start_gen; // valid data propagation
reg [OUTPUT_BITS*INPUT_BITS-1:0] root_gen; // root values
reg [OUTPUT_BITS*INPUT_BITS-1:0] radicand_gen; // radicand values
wire [OUTPUT_BITS*INPUT_BITS-1:0] mask_gen; // mask values
// This is the first stage of the pipeline.
always @ (posedge clk or negedge reset_n) begin
if (!reset_n) begin
start_gen[0] <= 0;
radicand_gen[INPUT_BITS-1:0] <= 0;
root_gen[INPUT_BITS-1:0] <= 0;
end
else begin
start_gen[0] <= start;
if ( mask_gen[INPUT_BITS-1:0] <= radicand ) begin
radicand_gen[INPUT_BITS-1:0] <= radicand - mask_gen[INPUT_BITS-1:0];
root_gen[INPUT_BITS-1:0] <= mask_gen[INPUT_BITS-1:0];
end
else begin
radicand_gen[INPUT_BITS-1:0] <= radicand;
root_gen[INPUT_BITS-1:0] <= 0;
end
end
end
// Main generate loop to create the masks and pipeline stages.
generate
genvar i;
// Generate all the mask values. These are built up in the
// following fashion:
// LAST MASK: 0x00...001
// 0x00...004 Increasing # OUTPUT_BITS
// 0x00...010 |
// 0x00...040 v
// ...
// FIRST MASK: 0x10...000 # masks == # OUTPUT_BITS
//
// Note that the first mask used can either be of the 0x1... or
// 0x4... variety. This is purely determined by the number of
// computation stages. However, the last mask used will always be
// 0x1 and the second to last mask used will always be 0x4.
for (i = 0; i < OUTPUT_BITS; i = i + 1) begin: mask_4
if (i % 2) // i is odd, this is a 4 mask
assign mask_gen[INPUT_BITS*(OUTPUT_BITS-i)-1:INPUT_BITS*(OUTPUT_BITS-i-1)] = 4 << 4 * (i/2);
else // i is even, this is a 1 mask
assign mask_gen[INPUT_BITS*(OUTPUT_BITS-i)-1:INPUT_BITS*(OUTPUT_BITS-i-1)] = 1 << 4 * (i/2);
end
// Generate all the pipeline stages to compute the square root of
// the input radicand stream. The general approach is to compare
// the current values of the root plus the mask to the
// radicand. If root/mask sum is greater than the radicand,
// subtract the mask and the root from the radicand and store the
// radicand for the next stage. Additionally, the root is
// increased by the value of the mask and stored for the next
// stage. If this test fails, then the radicand and the root
// retain their value through to the next stage. The one weird
// thing is that the mask indices appear to be incremented by one
// additional position. This is not the case, however, because the
// first mask is used in the first stage (always block after the
// generate statement).
for (i = 0; i < OUTPUT_BITS - 1; i = i + 1) begin: pipeline
always @ (posedge clk or negedge reset_n) begin : pipeline_stage
if (!reset_n) begin
start_gen[i+1] <= 0;
radicand_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= 0;
root_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= 0;
end
else begin
start_gen[i+1] <= start_gen[i];
if ((root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] +
mask_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)]) <= radicand_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i]) begin
radicand_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= radicand_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] -
mask_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] -
root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i];
root_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= (root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] >> 1) +
mask_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)];
end
else begin
radicand_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= radicand_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i];
root_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] >> 1;
end
end
end
end
endgenerate
// This is the final stage which just implements a rounding
// operation. This stage could be tacked on as a combinational logic
// stage, but who cares about latency, anyway? This is NOT a true
// rounding stage. In order to add convergent rounding, you need to
// increase the input bit width by 2 (increase the number of
// pipeline stages by 1) and implement rounding in the module that
// instantiates this one.
always @ (posedge clk or negedge reset_n) begin
if (!reset_n) begin
data_valid <= 0;
root <= 0;
end
else begin
data_valid <= start_gen[OUTPUT_BITS-1];
if (root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS] > root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS])
root <= root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS] + 1;
else
root <= root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS];
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2111A_2_V
`define SKY130_FD_SC_LS__O2111A_2_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog wrapper for o2111a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o2111a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o2111a_2 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o2111a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o2111a_2 (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o2111a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2111A_2_V
|
/*
########################################################################
EPIPHANY eLink RX Protocol block
########################################################################
This block takes the parallel output of the input deserializers, locates
valid frame transitions, and decodes the bytes into standard eMesh
protocol (104-bit transactions).
*/
module erx_protocol (/*AUTOARG*/
// Outputs
rx_rd_wait, rx_wr_wait, emesh_rx_access, emesh_rx_write,
emesh_rx_datamode, emesh_rx_ctrlmode, emesh_rx_dstaddr,
emesh_rx_srcaddr, emesh_rx_data,
// Inputs
reset, rx_lclk_div4, rx_frame_par, rx_data_par, emesh_rx_rd_wait,
emesh_rx_wr_wait
);
// System reset input
input reset;
// Parallel interface, 8 eLink bytes at a time
input rx_lclk_div4; // Parallel clock input from IO block
input [7:0] rx_frame_par;
input [63:0] rx_data_par;
output rx_rd_wait; // The wait signals are passed through
output rx_wr_wait; // from the emesh interfaces
// Output to MMU / filter
output emesh_rx_access;
output emesh_rx_write;
output [1:0] emesh_rx_datamode;
output [3:0] emesh_rx_ctrlmode;
output [31:0] emesh_rx_dstaddr;
output [31:0] emesh_rx_srcaddr;
output [31:0] emesh_rx_data;
input emesh_rx_rd_wait;
input emesh_rx_wr_wait;
//#############
//# Configuration bits
//#############
//######################
//# Identify FRAME edges
//######################
reg frame_prev;
reg [2:0] rxalign_in;
reg rxactive_in;
reg [63:0] rx_data_in;
reg [2:0] rxalign_0;
reg rxactive_0;
reg [3:0] ctrlmode_0;
reg [31:0] dstaddr_0;
reg [1:0] datamode_0;
reg write_0;
reg access_0;
reg [31:16] data_0;
reg stream_0;
reg [2:0] rxalign_1;
reg rxactive_1;
reg [3:0] ctrlmode_1;
reg [31:0] dstaddr_1;
reg [1:0] datamode_1;
reg write_1;
reg access_1;
reg [31:0] data_1;
reg [31:0] srcaddr_1;
reg stream_1;
reg [3:0] ctrlmode_2;
reg [31:0] dstaddr_2;
reg [1:0] datamode_2;
reg write_2;
reg access_2;
reg [31:0] data_2;
reg [31:0] srcaddr_2;
reg stream_2;
// Here we handle any alignment of the frame within an 8-cycle group,
// though in theory frames should only start on rising edges??
always @( posedge rx_lclk_div4 or posedge reset)
if(reset)
begin
rxalign_in <= 3'd0;
rxactive_in <= 1'b0;
end
else
begin
frame_prev <= rx_frame_par[0] ; // Capture last bit for next group
rx_data_in <= rx_data_par;
if( ~frame_prev & rx_frame_par[7] ) begin // All 8 bytes are a new frame
rxalign_in <= 3'd7;
rxactive_in <= 1'b1;
end else if( ~rx_frame_par[7] & rx_frame_par[6] ) begin
rxalign_in <= 3'd6;
rxactive_in <= 1'b1;
end else if( ~rx_frame_par[6] & rx_frame_par[5] ) begin
rxalign_in <= 3'd5;
rxactive_in <= 1'b1;
end else if( ~rx_frame_par[5] & rx_frame_par[4] ) begin
rxalign_in <= 3'd4;
rxactive_in <= 1'b1;
end else if( ~rx_frame_par[4] & rx_frame_par[3] ) begin
rxalign_in <= 3'd3;
rxactive_in <= 1'b1;
end else if( ~rx_frame_par[3] & rx_frame_par[2] ) begin
rxalign_in <= 3'd2;
rxactive_in <= 1'b1;
end else if( ~rx_frame_par[2] & rx_frame_par[1] ) begin
rxalign_in <= 3'd1;
rxactive_in <= 1'b1;
end else if( ~rx_frame_par[1] & rx_frame_par[0] ) begin
rxalign_in <= 3'd0;
rxactive_in <= 1'b1;
end else begin
rxactive_in <= 1'd0; // No edge
end
end // always @ ( posedge rx_lclk_div4 )
// 1st cycle
always @( posedge rx_lclk_div4 )
begin
rxactive_0 <= rxactive_in;
rxalign_0 <= rxalign_in;
stream_0 <= 1'b0;
case(rxalign_in[2:0])
3'd7:
begin
ctrlmode_0[3:0] <= rx_data_in[55:52];
dstaddr_0[31:0] <= rx_data_in[51:20];
datamode_0 <= rx_data_in[19:18];
write_0 <= rx_data_in[17];
access_0 <= rx_data_in[16];
data_0[31:16] <= rx_data_in[15:0];
stream_0 <= rx_frame_par[1] & (rxactive_in | stream_0);
end
3'd6:
begin
ctrlmode_0[3:0] <= rx_data_in[47:44];
dstaddr_0[31:0] <= rx_data_in[43:12];
datamode_0 <= rx_data_in[11:10];
write_0 <= rx_data_in[9];
access_0 <= rx_data_in[8];
data_0[31:24] <= rx_data_in[7:0];
stream_0 <= rx_frame_par[0] & (rxactive_in | stream_0);
end
3'd5:
begin
ctrlmode_0 <= rx_data_in[39:36];
dstaddr_0[31:0] <= rx_data_in[35:4];
datamode_0 <= rx_data_in[3:2];
write_0 <= rx_data_in[1];
access_0 <= rx_data_in[0];
end
3'd4:
begin
ctrlmode_0 <= rx_data_in[31:28];
dstaddr_0[31:4] <= rx_data_in[27:0];
end
3'd3:
begin
ctrlmode_0 <= rx_data_in[23:20];
dstaddr_0[31:12] <= rx_data_in[19:0];
end
3'd2:
begin
ctrlmode_0 <= rx_data_in[15:12];
dstaddr_0[31:20] <= rx_data_in[11:0];
end
3'd1:
begin
ctrlmode_0 <= rx_data_in[7:4];
dstaddr_0[31:28] <= rx_data_in[3:0];
end
default: ;
endcase // case (rxalign_in[2:0])
end // always @ ( posedge rx_lclk_div4 )
// 2nd cycle
always @( posedge rx_lclk_div4 ) begin
rxactive_1 <= rxactive_0;
rxalign_1 <= rxalign_0;
// default pass-throughs
ctrlmode_1 <= ctrlmode_0;
dstaddr_1 <= dstaddr_0;
datamode_1 <= datamode_0;
write_1 <= write_0;
access_1 <= access_0;
data_1[31:16] <= data_0[31:16];
stream_1 <= stream_0;
case(rxalign_0)
3'd7: begin
data_1[15:0] <= rx_data_in[63:48];
srcaddr_1 <= rx_data_in[47:16];
end
3'd6: begin
data_1[23:0] <= rx_data_in[63:40];
srcaddr_1 <= rx_data_in[39:8];
end
3'd5: begin
data_1 <= rx_data_in[63:32];
srcaddr_1 <= rx_data_in[31:0];
stream_1 <= rx_frame_par[7] & (rxactive_0 | stream_1);
end
3'd4: begin
dstaddr_1[3:0] <= rx_data_in[63:60];
datamode_1 <= rx_data_in[59:58];
write_1 <= rx_data_in[57];
access_1 <= rx_data_in[56];
data_1 <= rx_data_in[55:24];
srcaddr_1[31:8] <= rx_data_in[23:0];
stream_1 <= rx_frame_par[6] & (rxactive_0 | stream_1);
end
3'd3: begin
dstaddr_1[11:0] <= rx_data_in[63:52];
datamode_1 <= rx_data_in[51:50];
write_1 <= rx_data_in[49];
access_1 <= rx_data_in[48];
data_1 <= rx_data_in[47:16];
srcaddr_1[31:16] <= rx_data_in[15:0];
stream_1 <= rx_frame_par[5] & (rxactive_0 | stream_1);
end
3'd2: begin
dstaddr_1[19:0] <= rx_data_in[63:44];
datamode_1 <= rx_data_in[43:42];
write_1 <= rx_data_in[41];
access_1 <= rx_data_in[40];
data_1 <= rx_data_in[39:8];
srcaddr_1[31:24] <= rx_data_in[7:0];
stream_1 <= rx_frame_par[4] & (rxactive_0 | stream_1);
end
3'd1: begin
dstaddr_1[27:0] <= rx_data_in[63:36];
datamode_1 <= rx_data_in[35:34];
write_1 <= rx_data_in[33];
access_1 <= rx_data_in[32];
data_1 <= rx_data_in[31:0];
stream_1 <= rx_frame_par[3] & (rxactive_0 | stream_1);
end
3'd0: begin
ctrlmode_1 <= rx_data_in[63:60];
dstaddr_1[31:0] <= rx_data_in[59:28];
datamode_1 <= rx_data_in[27:26];
write_1 <= rx_data_in[25];
access_1 <= rx_data_in[24];
data_1[31:8] <= rx_data_in[23:0];
stream_1 <= rx_frame_par[2] & (rxactive_0 | stream_1);
end
endcase
end // always @ ( posedge rx_lclk_div4 )
// 3rd cycle
always @( posedge rx_lclk_div4 ) begin
// default pass-throughs
if(~stream_2)
begin
ctrlmode_2 <= ctrlmode_1;
dstaddr_2 <= dstaddr_1;
datamode_2 <= datamode_1;
write_2 <= write_1;
access_2 <= access_1 & rxactive_1;
end
else
begin
dstaddr_2 <= dstaddr_2 + 32'h00000008;
end
data_2 <= data_1;
srcaddr_2 <= srcaddr_1;
stream_2 <= stream_1;
case( rxalign_1[2:0] )
// 7-5: Full packet is complete in 2nd cycle
3'd4:
srcaddr_2[7:0] <= rx_data_in[63:56];
3'd3:
srcaddr_2[15:0] <= rx_data_in[63:48];
3'd2:
srcaddr_2[23:0] <= rx_data_in[63:40];
3'd1:
srcaddr_2[31:0] <= rx_data_in[63:32];
3'd0:
begin
data_2[7:0] <= rx_data_in[63:56];
srcaddr_2[31:0] <= rx_data_in[55:24];
end
default:;//TODO: include error message
endcase // case ( rxalign_1 )
end // always @ ( posedge rx_lclk_div4 )
/* The spec says reads use the 'data' slot for src address, but apparently
the silicon has not read this spec.
if( write_1 ) begin
srcaddr_2 <= srcaddr_1;
case( rxalign_1 )
// 7-5 Full packet is complete in 2nd cycle
3'd4:
srcaddr_2[7:0] <= rx_data_in[63:56];
3'd3:
srcaddr_2[15:0] <= rx_data_in[63:48];
3'd2:
srcaddr_2[23:0] <= rx_data_in[63:40];
3'd1:
srcaddr_2[31:0] <= rx_data_in[63:32];
3'd0: begin
data_2[7:0] <= rx_data_in[63:56];
srcaddr_2[31:0] <= rx_data_in[55:24];
end
endcase // case ( rxalign_1 )
end else begin // on reads, source addr is in data slot
srcaddr_2 <= data_1;
if( rxalign_1 == )
srcaddr_2[7:0] <= rx_data_in[63:56];
end // else: !if( write_1 )
end // always @ ( posedge rx_lclk_div4 )
*/
// xxx_2 now has one complete transfer
// TODO: Handle burst mode, for now we stop after one xaction
assign emesh_rx_access = access_2;
assign emesh_rx_write = write_2;
assign emesh_rx_datamode = datamode_2;
assign emesh_rx_ctrlmode = ctrlmode_2;
assign emesh_rx_dstaddr = dstaddr_2;
assign emesh_rx_srcaddr = srcaddr_2;
assign emesh_rx_data = data_2;
//################################
//# Wait signal passthrough
//################################
assign rx_rd_wait = emesh_rx_rd_wait;
assign rx_wr_wait = emesh_rx_wr_wait;
endmodule
/*
File: eproto_rx.v
This file is part of the Parallella Project.
Copyright (C) 2014 Adapteva, Inc.
Contributed by Fred Huettig <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O41AI_1_V
`define SKY130_FD_SC_LS__O41AI_1_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog wrapper for o41ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o41ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o41ai_1 (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o41ai_1 (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O41AI_1_V
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/BUFGP.v,v 1.6 2007/05/23 21:43:33 patrickp Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Primary Global Buffer for Driving Clocks or Long Lines
// /___/ /\ Filename : BUFGP.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:14 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module BUFGP (O, I);
`ifdef XIL_TIMING
parameter LOC = " UNPLACED";
`endif
output O;
input I;
buf B1 (O, I);
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03.06.2015 14:58:39
// Design Name:
// Module Name: harness
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "system.vh"
module harness();
parameter X_LOCAL = 2,
Y_LOCAL = 2,
CYCLE = 100,
Tsetup = 15,
Thold = 5;
// -- Señales de interconexion ----------------------------------- >>>>>
reg clk;
reg reset;
// -- puertos de entradas ------------------------------------ >>>>>
wire credit_out_xpos_dout;
wire [`CHANNEL_WIDTH-1:0] channel_xpos_din;
wire credit_out_ypos_dout;
wire [`CHANNEL_WIDTH-1:0] channel_ypos_din;
wire credit_out_xneg_dout;
wire[`CHANNEL_WIDTH-1:0] channel_xneg_din;
wire credit_out_yneg_dout;
wire [`CHANNEL_WIDTH-1:0] channel_yneg_din;
wire credit_out_pe_dout;
wire [`CHANNEL_WIDTH-1:0] channel_pe_din;
// -- puertos de salida -------------------------------------- >>>>>
wire credit_in_xpos_din;
wire [`CHANNEL_WIDTH-1:0] channel_xpos_dout;
wire credit_in_ypos_din;
wire [`CHANNEL_WIDTH-1:0] channel_ypos_dout;
wire credit_in_xneg_din;
wire [`CHANNEL_WIDTH-1:0] channel_xneg_dout;
wire credit_in_yneg_din;
wire [`CHANNEL_WIDTH-1:0] channel_yneg_dout;
wire credit_in_pe_din;
wire [`CHANNEL_WIDTH-1:0] channel_pe_dout;
// -- DUT -------------------------------------------------------- >>>>>
router
#(
.X_LOCAL(X_LOCAL),
.Y_LOCAL(Y_LOCAL)
)
lancetfish_router
(
.clk (clk),
.reset (reset),
// -- puertos de entrada ------------------------------------- >>>>>
.credit_out_xpos_dout (credit_out_xpos_dout),
.channel_xpos_din (channel_xpos_din),
.credit_out_ypos_dout (credit_out_ypos_dout),
.channel_ypos_din (channel_ypos_din),
.credit_out_xneg_dout (credit_out_xneg_dout),
.channel_xneg_din (channel_xneg_din),
.credit_out_yneg_dout (credit_out_yneg_dout),
.channel_yneg_din (channel_yneg_din),
.credit_out_pe_dout (credit_out_pe_dout), // PE
.channel_pe_din (channel_pe_din),
// -- puertos de salida -------------------------------------- >>>>>
.credit_in_xpos_din (credit_in_xpos_din),
.channel_xpos_dout (channel_xpos_dout),
.credit_in_ypos_din (credit_in_ypos_din),
.channel_ypos_dout (channel_ypos_dout),
.credit_in_xneg_din (credit_in_xneg_din),
.channel_xneg_dout (channel_xneg_dout),
.credit_in_yneg_din (credit_in_yneg_din),
.channel_yneg_dout (channel_yneg_dout),
.credit_in_pe_din (credit_in_pe_din), // PE
.channel_pe_dout (channel_pe_dout)
);
// -- Bus Behaivoral Model --------------------------------------- >>>>>
// -- Canal x+ ----------------------------------------------- >>>>>
source
#(
.Thold(Thold)
)
xpos_in_channel
(
.clk (clk),
.credit_in (credit_out_xpos_dout),
.channel_out(channel_xpos_din)
);
sink
#(
.Thold(Thold)
)
xpos_out_channel
(
.clk (clk),
.channel_in (channel_xpos_dout),
.credit_out (credit_in_xpos_din)
);
// -- Canal y+ ----------------------------------------------- >>>>>
source
#(
.Thold(Thold)
)
ypos_in_channel
(
.clk (clk),
.credit_in (credit_out_ypos_dout),
.channel_out(channel_ypos_din)
);
sink
#(
.Thold(Thold)
)
ypos_out_channel
(
.clk (clk),
.channel_in (channel_ypos_dout),
.credit_out (credit_in_ypos_din)
);
// -- Canal x- ----------------------------------------------- >>>>>
source
#(
.Thold(Thold)
)
xneg_in_channel
(
.clk (clk),
.credit_in (credit_out_xneg_dout),
.channel_out(channel_xneg_din)
);
sink
#(
.Thold(Thold)
)
xneg_out_channel
(
.clk (clk),
.channel_in (channel_xneg_dout),
.credit_out (credit_in_xneg_din)
);
// -- Canal x- ----------------------------------------------- >>>>>
source
#(
.Thold(Thold)
)
yneg_in_channel
(
.clk (clk),
.credit_in (credit_out_yneg_dout),
.channel_out(channel_yneg_din)
);
sink
#(
.Thold(Thold)
)
yneg_out_channel
(
.clk (clk),
.channel_in (channel_yneg_dout),
.credit_out (credit_in_yneg_din)
);
// -- Canal pe ------------------------------------------- >>>>>
source
#(
.Thold(Thold)
)
pe_in_channel
(
.clk (clk),
.credit_in (credit_out_pe_dout),
.channel_out(channel_pe_din)
);
sink
#(
.Thold(Thold)
)
pe_out_channel
(
.clk (clk),
.channel_in (channel_pe_dout),
.credit_out (credit_in_pe_din)
);
// -- Clock Generator -------------------------------------------- >>>>>
always
begin
#(CYCLE/2) clk = 1'b0;
#(CYCLE/2) clk = 1'b1;
end
// -- Sync Reset Generator --------------------------------------- >>>>>
task sync_reset;
begin
reset <= 1'b1;
repeat(4)
begin
@(posedge clk);
#(Thold);
end
reset <= 1'b0;
end
endtask : sync_reset
endmodule
|
//////////////////////////////////////////////////////////////////////////////
// This module is a ST wrapper for the soft IP NextGen controller and the MMR
//////////////////////////////////////////////////////////////////////////////
//altera message_off 10230
`include "alt_mem_ddrx_define.iv"
`timescale 1 ps / 1 ps
module alt_mem_ddrx_controller_st_top(
clk,
half_clk,
reset_n,
itf_cmd_ready,
itf_cmd_valid,
itf_cmd,
itf_cmd_address,
itf_cmd_burstlen,
itf_cmd_id,
itf_cmd_priority,
itf_cmd_autopercharge,
itf_cmd_multicast,
itf_wr_data_ready,
itf_wr_data_valid,
itf_wr_data,
itf_wr_data_byte_en,
itf_wr_data_begin,
itf_wr_data_last,
itf_wr_data_id,
itf_rd_data_ready,
itf_rd_data_valid,
itf_rd_data,
itf_rd_data_error,
itf_rd_data_begin,
itf_rd_data_last,
itf_rd_data_id,
afi_rst_n,
afi_cs_n,
afi_cke,
afi_odt,
afi_addr,
afi_ba,
afi_ras_n,
afi_cas_n,
afi_we_n,
afi_dqs_burst,
afi_wdata_valid,
afi_wdata,
afi_dm,
afi_wlat,
afi_rdata_en,
afi_rdata_en_full,
afi_rdata,
afi_rdata_valid,
afi_rrank,
afi_wrank,
afi_rlat,
afi_cal_success,
afi_cal_fail,
afi_cal_req,
afi_init_req,
afi_mem_clk_disable,
afi_cal_byte_lane_sel_n,
afi_ctl_refresh_done,
afi_seq_busy,
afi_ctl_long_idle,
local_init_done,
local_refresh_ack,
local_powerdn_ack,
local_self_rfsh_ack,
local_deep_powerdn_ack,
local_refresh_req,
local_refresh_chip,
local_powerdn_req,
local_self_rfsh_req,
local_self_rfsh_chip,
local_deep_powerdn_req,
local_deep_powerdn_chip,
local_zqcal_req,
local_zqcal_chip,
local_multicast,
local_priority,
ecc_interrupt,
csr_read_req,
csr_write_req,
csr_burst_count,
csr_beginbursttransfer,
csr_addr,
csr_wdata,
csr_rdata,
csr_be,
csr_rdata_valid,
csr_waitrequest,
tbp_empty,
cmd_gen_busy,
sideband_in_refresh
);
//////////////////////////////////////////////////////////////////////////////
parameter LOCAL_SIZE_WIDTH = "";
parameter LOCAL_ADDR_WIDTH = "";
parameter LOCAL_DATA_WIDTH = "";
parameter LOCAL_BE_WIDTH = "";
parameter LOCAL_ID_WIDTH = "";
parameter LOCAL_CS_WIDTH = "";
parameter MEM_IF_ADDR_WIDTH = "";
parameter MEM_IF_CLK_PAIR_COUNT = "";
parameter LOCAL_IF_TYPE = "";
parameter DWIDTH_RATIO = "";
parameter CTL_ODT_ENABLED = "";
parameter CTL_OUTPUT_REGD = "";
parameter CTL_TBP_NUM = "";
parameter WRBUFFER_ADDR_WIDTH = "";
parameter RDBUFFER_ADDR_WIDTH = "";
parameter MAX_PENDING_RD_CMD = 16;
parameter MAX_PENDING_WR_CMD = 8;
parameter MEM_IF_CS_WIDTH = "";
parameter MEM_IF_CHIP = "";
parameter MEM_IF_BANKADDR_WIDTH = "";
parameter MEM_IF_ROW_WIDTH = "";
parameter MEM_IF_COL_WIDTH = "";
parameter MEM_IF_ODT_WIDTH = "";
parameter MEM_IF_DQS_WIDTH = "";
parameter MEM_IF_DWIDTH = "";
parameter MEM_IF_DM_WIDTH = "";
parameter MAX_MEM_IF_CS_WIDTH = "";
parameter MAX_MEM_IF_CHIP = "";
parameter MAX_MEM_IF_BANKADDR_WIDTH = "";
parameter MAX_MEM_IF_ROWADDR_WIDTH = "";
parameter MAX_MEM_IF_COLADDR_WIDTH = "";
parameter MAX_MEM_IF_ODT_WIDTH = "";
parameter MAX_MEM_IF_DQS_WIDTH = "";
parameter MAX_MEM_IF_DQ_WIDTH = "";
parameter MAX_MEM_IF_MASK_WIDTH = "";
parameter MAX_LOCAL_DATA_WIDTH = "";
parameter CFG_TYPE = "";
parameter CFG_INTERFACE_WIDTH = "";
parameter CFG_BURST_LENGTH = "";
parameter CFG_DEVICE_WIDTH = "";
parameter CFG_REORDER_DATA = "";
parameter CFG_DATA_REORDERING_TYPE = "";
parameter CFG_STARVE_LIMIT = "";
parameter CFG_ADDR_ORDER = "";
parameter MEM_CAS_WR_LAT = "";
parameter MEM_ADD_LAT = "";
parameter MEM_TCL = "";
parameter MEM_TRRD = "";
parameter MEM_TFAW = "";
parameter MEM_TRFC = "";
parameter MEM_TREFI = "";
parameter MEM_TRCD = "";
parameter MEM_TRP = "";
parameter MEM_TWR = "";
parameter MEM_TWTR = "";
parameter MEM_TRTP = "";
parameter MEM_TRAS = "";
parameter MEM_TRC = "";
parameter CFG_TCCD = "";
parameter MEM_AUTO_PD_CYCLES = "";
parameter CFG_SELF_RFSH_EXIT_CYCLES = "";
parameter CFG_PDN_EXIT_CYCLES = "";
parameter CFG_POWER_SAVING_EXIT_CYCLES = "";
parameter CFG_MEM_CLK_ENTRY_CYCLES = "";
parameter MEM_TMRD_CK = "";
parameter CTL_ECC_ENABLED = "";
parameter CTL_ECC_RMW_ENABLED = "";
parameter CTL_ECC_MULTIPLES_16_24_40_72 = "";
parameter CFG_GEN_SBE = "";
parameter CFG_GEN_DBE = "";
parameter CFG_ENABLE_INTR = "";
parameter CFG_MASK_SBE_INTR = "";
parameter CFG_MASK_DBE_INTR = "";
parameter CFG_MASK_CORRDROP_INTR = 0;
parameter CFG_CLR_INTR = "";
parameter CTL_USR_REFRESH = "";
parameter CTL_REGDIMM_ENABLED = "";
parameter CTL_ENABLE_BURST_INTERRUPT = "";
parameter CTL_ENABLE_BURST_TERMINATE = "";
parameter CFG_WRITE_ODT_CHIP = "";
parameter CFG_READ_ODT_CHIP = "";
parameter CFG_PORT_WIDTH_WRITE_ODT_CHIP = "";
parameter CFG_PORT_WIDTH_READ_ODT_CHIP = "";
parameter MEM_IF_CKE_WIDTH = "";//check
parameter CTL_CSR_ENABLED = "";
parameter CFG_ENABLE_NO_DM = "";
parameter CSR_ADDR_WIDTH = "";
parameter CSR_DATA_WIDTH = "";
parameter CSR_BE_WIDTH = "";
parameter CFG_ENABLE_DQS_TRACKING = 0;
parameter CFG_WLAT_BUS_WIDTH = 6;
parameter CFG_RLAT_BUS_WIDTH = 6;
parameter CFG_RRANK_BUS_WIDTH = 0;
parameter CFG_WRANK_BUS_WIDTH = 0;
parameter CFG_USE_SHADOW_REGS = 0;
parameter MEM_IF_RD_TO_WR_TURNAROUND_OCT = "";
parameter MEM_IF_WR_TO_RD_TURNAROUND_OCT = "";
parameter CTL_RD_TO_PCH_EXTRA_CLK = 0;
parameter CTL_RD_TO_RD_EXTRA_CLK = 0;
parameter CTL_WR_TO_WR_EXTRA_CLK = 0;
parameter CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK = 0;
parameter CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK = 0;
parameter CTL_ENABLE_WDATA_PATH_LATENCY = 0;
parameter CFG_ECC_DECODER_REG = 0;
parameter CFG_ERRCMD_FIFO_REG = 0;
parameter ENABLE_BURST_MERGE = 0;
//////////////////////////////////////////////////////////////////////////////
localparam CFG_LOCAL_SIZE_WIDTH = LOCAL_SIZE_WIDTH;
localparam CFG_LOCAL_ADDR_WIDTH = LOCAL_ADDR_WIDTH;
localparam CFG_LOCAL_DATA_WIDTH = LOCAL_DATA_WIDTH;
localparam CFG_LOCAL_BE_WIDTH = LOCAL_BE_WIDTH;
localparam CFG_LOCAL_ID_WIDTH = LOCAL_ID_WIDTH;
localparam CFG_LOCAL_IF_TYPE = LOCAL_IF_TYPE;
localparam CFG_MEM_IF_ADDR_WIDTH = MEM_IF_ADDR_WIDTH;
localparam CFG_MEM_IF_CLK_PAIR_COUNT = MEM_IF_CLK_PAIR_COUNT;
localparam CFG_DWIDTH_RATIO = DWIDTH_RATIO;
localparam CFG_ODT_ENABLED = CTL_ODT_ENABLED;
localparam CFG_CTL_TBP_NUM = CTL_TBP_NUM;
localparam CFG_WRBUFFER_ADDR_WIDTH = WRBUFFER_ADDR_WIDTH;
localparam CFG_RDBUFFER_ADDR_WIDTH = RDBUFFER_ADDR_WIDTH;
localparam CFG_MAX_PENDING_RD_CMD = MAX_PENDING_RD_CMD;
localparam CFG_MAX_PENDING_WR_CMD = MAX_PENDING_WR_CMD;
localparam CFG_MEM_IF_CS_WIDTH = MEM_IF_CS_WIDTH;
localparam CFG_MEM_IF_CHIP = MEM_IF_CHIP;
localparam CFG_MEM_IF_BA_WIDTH = MEM_IF_BANKADDR_WIDTH;
localparam CFG_MEM_IF_ROW_WIDTH = MEM_IF_ROW_WIDTH;
localparam CFG_MEM_IF_COL_WIDTH = MEM_IF_COL_WIDTH;
localparam CFG_MEM_IF_CKE_WIDTH = MEM_IF_CKE_WIDTH;
localparam CFG_MEM_IF_ODT_WIDTH = MEM_IF_ODT_WIDTH;
localparam CFG_MEM_IF_DQS_WIDTH = MEM_IF_DQS_WIDTH;
localparam CFG_MEM_IF_DQ_WIDTH = MEM_IF_DWIDTH;
localparam CFG_MEM_IF_DM_WIDTH = MEM_IF_DM_WIDTH;
localparam CFG_COL_ADDR_WIDTH = MEM_IF_COL_WIDTH;
localparam CFG_ROW_ADDR_WIDTH = MEM_IF_ROW_WIDTH;
localparam CFG_BANK_ADDR_WIDTH = MEM_IF_BANKADDR_WIDTH;
localparam CFG_CS_ADDR_WIDTH = LOCAL_CS_WIDTH;
localparam CFG_CAS_WR_LAT = MEM_CAS_WR_LAT;
localparam CFG_ADD_LAT = MEM_ADD_LAT;
localparam CFG_TCL = MEM_TCL;
localparam CFG_TRRD = MEM_TRRD;
localparam CFG_TFAW = MEM_TFAW;
localparam CFG_TRFC = MEM_TRFC;
localparam CFG_TREFI = MEM_TREFI;
localparam CFG_TRCD = MEM_TRCD;
localparam CFG_TRP = MEM_TRP;
localparam CFG_TWR = MEM_TWR;
localparam CFG_TWTR = MEM_TWTR;
localparam CFG_TRTP = MEM_TRTP;
localparam CFG_TRAS = MEM_TRAS;
localparam CFG_TRC = MEM_TRC;
localparam CFG_AUTO_PD_CYCLES = MEM_AUTO_PD_CYCLES;
localparam CFG_TMRD = MEM_TMRD_CK;
localparam CFG_ENABLE_ECC = CTL_ECC_ENABLED;
localparam CFG_ENABLE_AUTO_CORR = CTL_ECC_RMW_ENABLED;
localparam CFG_ECC_MULTIPLES_16_24_40_72 = CTL_ECC_MULTIPLES_16_24_40_72;
localparam CFG_ENABLE_ECC_CODE_OVERWRITES = 1'b1;
localparam CFG_CAL_REQ = 0;
localparam CFG_EXTRA_CTL_CLK_ACT_TO_RDWR = 0;
localparam CFG_EXTRA_CTL_CLK_ACT_TO_PCH = 0;
localparam CFG_EXTRA_CTL_CLK_ACT_TO_ACT = 0;
localparam CFG_EXTRA_CTL_CLK_RD_TO_RD = 0 + CTL_RD_TO_RD_EXTRA_CLK;
localparam CFG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP = 0 + CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK;
localparam CFG_EXTRA_CTL_CLK_RD_TO_WR = 0 + ((MEM_IF_RD_TO_WR_TURNAROUND_OCT / (DWIDTH_RATIO / 2)) + ((MEM_IF_RD_TO_WR_TURNAROUND_OCT % (DWIDTH_RATIO / 2)) > 0 ? 1 : 0)); // Please do not remove the latter calculation
localparam CFG_EXTRA_CTL_CLK_RD_TO_WR_BC = 0 + ((MEM_IF_RD_TO_WR_TURNAROUND_OCT / (DWIDTH_RATIO / 2)) + ((MEM_IF_RD_TO_WR_TURNAROUND_OCT % (DWIDTH_RATIO / 2)) > 0 ? 1 : 0)); // Please do not remove the latter calculation
localparam CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP = 0 + ((MEM_IF_RD_TO_WR_TURNAROUND_OCT / (DWIDTH_RATIO / 2)) + ((MEM_IF_RD_TO_WR_TURNAROUND_OCT % (DWIDTH_RATIO / 2)) > 0 ? 1 : 0)); // Please do not remove the latter calculation
localparam CFG_EXTRA_CTL_CLK_RD_TO_PCH = 0 + CTL_RD_TO_PCH_EXTRA_CLK;
localparam CFG_EXTRA_CTL_CLK_RD_AP_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_WR_TO_WR = 0 + CTL_WR_TO_WR_EXTRA_CLK;
localparam CFG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP = 0 + CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK;
localparam CFG_EXTRA_CTL_CLK_WR_TO_RD = 0 + ((MEM_IF_WR_TO_RD_TURNAROUND_OCT / (DWIDTH_RATIO / 2)) + ((MEM_IF_WR_TO_RD_TURNAROUND_OCT % (DWIDTH_RATIO / 2)) > 0 ? 1 : 0)); // Please do not remove the latter calculation
localparam CFG_EXTRA_CTL_CLK_WR_TO_RD_BC = 0 + ((MEM_IF_WR_TO_RD_TURNAROUND_OCT / (DWIDTH_RATIO / 2)) + ((MEM_IF_WR_TO_RD_TURNAROUND_OCT % (DWIDTH_RATIO / 2)) > 0 ? 1 : 0)); // Please do not remove the latter calculation
localparam CFG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP = 0 + ((MEM_IF_WR_TO_RD_TURNAROUND_OCT / (DWIDTH_RATIO / 2)) + ((MEM_IF_WR_TO_RD_TURNAROUND_OCT % (DWIDTH_RATIO / 2)) > 0 ? 1 : 0)); // Please do not remove the latter calculation
localparam CFG_EXTRA_CTL_CLK_WR_TO_PCH = 0;
localparam CFG_EXTRA_CTL_CLK_WR_AP_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_PCH_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK = 0;
localparam CFG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT = 0;
localparam CFG_EXTRA_CTL_CLK_ARF_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_PDN_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_SRF_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL = 0;
localparam CFG_EXTRA_CTL_CLK_ARF_PERIOD = 0;
localparam CFG_EXTRA_CTL_CLK_PDN_PERIOD = 0;
localparam CFG_OUTPUT_REGD = CTL_OUTPUT_REGD;
localparam CFG_MASK_CORR_DROPPED_INTR = 0;
localparam CFG_USER_RFSH = CTL_USR_REFRESH;
localparam CFG_REGDIMM_ENABLE = CTL_REGDIMM_ENABLED;
localparam CFG_ENABLE_BURST_INTERRUPT = CTL_ENABLE_BURST_INTERRUPT;
localparam CFG_ENABLE_BURST_TERMINATE = CTL_ENABLE_BURST_TERMINATE;
localparam CFG_ENABLE_WDATA_PATH_LATENCY = CTL_ENABLE_WDATA_PATH_LATENCY;
localparam CFG_ENABLE_BURST_MERGE = ENABLE_BURST_MERGE;
localparam CFG_PORT_WIDTH_TYPE = 3;
localparam CFG_PORT_WIDTH_INTERFACE_WIDTH = 8;
localparam CFG_PORT_WIDTH_BURST_LENGTH = 5;
localparam CFG_PORT_WIDTH_DEVICE_WIDTH = 4;
localparam CFG_PORT_WIDTH_REORDER_DATA = 1;
localparam CFG_PORT_WIDTH_STARVE_LIMIT = 6;
localparam CFG_PORT_WIDTH_OUTPUT_REGD = 2;
localparam CFG_PORT_WIDTH_ADDR_ORDER = 2;
localparam CFG_PORT_WIDTH_COL_ADDR_WIDTH = 5;
localparam CFG_PORT_WIDTH_ROW_ADDR_WIDTH = 5;
localparam CFG_PORT_WIDTH_BANK_ADDR_WIDTH = 3;
localparam CFG_PORT_WIDTH_CS_ADDR_WIDTH = 3;
localparam CFG_PORT_WIDTH_CAS_WR_LAT = 4;
localparam CFG_PORT_WIDTH_ADD_LAT = 4;
localparam CFG_PORT_WIDTH_TCL = 4;
localparam CFG_PORT_WIDTH_TRRD = 4;
localparam CFG_PORT_WIDTH_TFAW = 6;
localparam CFG_PORT_WIDTH_TRFC = 8;
localparam CFG_PORT_WIDTH_TREFI = 13;
localparam CFG_PORT_WIDTH_TRCD = 4;
localparam CFG_PORT_WIDTH_TRP = 4;
localparam CFG_PORT_WIDTH_TWR = 4;
localparam CFG_PORT_WIDTH_TWTR = 4;
localparam CFG_PORT_WIDTH_TRTP = 4;
localparam CFG_PORT_WIDTH_TRAS = 5;
localparam CFG_PORT_WIDTH_TRC = 6;
localparam CFG_PORT_WIDTH_TCCD = 4;
localparam CFG_PORT_WIDTH_TMRD = 3;
localparam CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES = 10;
localparam CFG_PORT_WIDTH_PDN_EXIT_CYCLES = 4;
localparam CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES = 4;
localparam CFG_PORT_WIDTH_MEM_CLK_ENTRY_CYCLES = 6;
localparam CFG_PORT_WIDTH_AUTO_PD_CYCLES = 16;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR = 1;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH = 1;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT = 1;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID = 1;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH = 1;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID = 1;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID = 1;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID = 1;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK = 1;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT = 1;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID = 1;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID = 1;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID = 1;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL = 1;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD = 1;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD = 1;
localparam CFG_PORT_WIDTH_ENABLE_ECC = 1;
localparam CFG_PORT_WIDTH_ENABLE_AUTO_CORR = 1;
localparam CFG_PORT_WIDTH_GEN_SBE = 1;
localparam CFG_PORT_WIDTH_GEN_DBE = 1;
localparam CFG_PORT_WIDTH_ENABLE_INTR = 1;
localparam CFG_PORT_WIDTH_MASK_SBE_INTR = 1;
localparam CFG_PORT_WIDTH_MASK_DBE_INTR = 1;
localparam CFG_PORT_WIDTH_CLR_INTR = 1;
localparam CFG_PORT_WIDTH_USER_RFSH = 1;
localparam CFG_PORT_WIDTH_SELF_RFSH = 1;
localparam CFG_PORT_WIDTH_REGDIMM_ENABLE = 1;
localparam CFG_PORT_WIDTH_ENABLE_BURST_INTERRUPT = 1;
localparam CFG_PORT_WIDTH_ENABLE_BURST_TERMINATE = 1;
localparam CFG_RDATA_RETURN_MODE = (CFG_REORDER_DATA == 1) ? "INORDER" : "PASSTHROUGH";
localparam CFG_LPDDR2_ENABLED = (CFG_TYPE == `MMR_TYPE_LPDDR2) ? 1 : 0;
localparam CFG_ADDR_RATE_RATIO = (CFG_LPDDR2_ENABLED == 1) ? 2 : 1;
localparam CFG_AFI_IF_FR_ADDR_WIDTH = (CFG_ADDR_RATE_RATIO * CFG_MEM_IF_ADDR_WIDTH);
localparam STS_PORT_WIDTH_SBE_ERROR = 1;
localparam STS_PORT_WIDTH_DBE_ERROR = 1;
localparam STS_PORT_WIDTH_CORR_DROP_ERROR = 1;
localparam STS_PORT_WIDTH_SBE_COUNT = 8;
localparam STS_PORT_WIDTH_DBE_COUNT = 8;
localparam STS_PORT_WIDTH_CORR_DROP_COUNT = 8;
// We are supposed to use these parameters when the CSR is enabled
// but the MAX_ parameters are not defined
//localparam AFI_CS_WIDTH = (MAX_MEM_IF_CHIP * (CFG_DWIDTH_RATIO / 2));
//localparam AFI_CKE_WIDTH = (MAX_CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO / 2));
//localparam AFI_ODT_WIDTH = (MAX_CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO / 2));
//localparam AFI_ADDR_WIDTH = (MAX_CFG_MEM_IF_ADDR_WIDTH * (CFG_DWIDTH_RATIO / 2));
//localparam AFI_BA_WIDTH = (MAX_CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO / 2));
//localparam AFI_CAL_BYTE_LANE_SEL_N_WIDTH = (CFG_MEM_IF_DQS_WIDTH * MAX_CFG_MEM_IF_CHIP);
localparam AFI_CS_WIDTH = (CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO / 2));
localparam AFI_CKE_WIDTH = (CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_ODT_WIDTH = (CFG_MEM_IF_ODT_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_ADDR_WIDTH = (CFG_AFI_IF_FR_ADDR_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_BA_WIDTH = (CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_CAL_BYTE_LANE_SEL_N_WIDTH = (CFG_MEM_IF_DQS_WIDTH * CFG_MEM_IF_CHIP);
localparam AFI_CMD_WIDTH = (CFG_DWIDTH_RATIO / 2);
localparam AFI_DQS_BURST_WIDTH = (CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_WDATA_VALID_WIDTH = (CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_WDATA_WIDTH = (CFG_MEM_IF_DQ_WIDTH * CFG_DWIDTH_RATIO);
localparam AFI_DM_WIDTH = (CFG_MEM_IF_DM_WIDTH * CFG_DWIDTH_RATIO);
localparam AFI_WLAT_WIDTH = CFG_WLAT_BUS_WIDTH;
localparam AFI_RDATA_EN_WIDTH = (CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_RDATA_WIDTH = (CFG_MEM_IF_DQ_WIDTH * CFG_DWIDTH_RATIO);
localparam AFI_RDATA_VALID_WIDTH = (CFG_DWIDTH_RATIO / 2);
localparam AFI_RRANK_WIDTH = CFG_RRANK_BUS_WIDTH;
localparam AFI_WRANK_WIDTH = CFG_WRANK_BUS_WIDTH;
localparam AFI_RLAT_WIDTH = CFG_RLAT_BUS_WIDTH;
localparam AFI_OTF_BITNUM = 12;
localparam AFI_AUTO_PRECHARGE_BITNUM = 10;
localparam AFI_MEM_CLK_DISABLE_WIDTH = CFG_MEM_IF_CLK_PAIR_COUNT;
//////////////////////////////////////////////////////////////////////////////
// BEGIN PORT SECTION
// Clk and reset signals
input clk;
input half_clk;
input reset_n;
// Command channel
output itf_cmd_ready;
input itf_cmd_valid;
input itf_cmd;
input [CFG_LOCAL_ADDR_WIDTH - 1 : 0] itf_cmd_address;
input [CFG_LOCAL_SIZE_WIDTH - 1 : 0] itf_cmd_burstlen;
input [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_cmd_id;
input itf_cmd_priority;
input itf_cmd_autopercharge;
input itf_cmd_multicast;
// Write data channel
output itf_wr_data_ready;
input itf_wr_data_valid;
input [CFG_LOCAL_DATA_WIDTH - 1 : 0] itf_wr_data;
input [CFG_LOCAL_BE_WIDTH - 1 : 0] itf_wr_data_byte_en;
input itf_wr_data_begin;
input itf_wr_data_last;
input [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_wr_data_id;
// Read data channel
input itf_rd_data_ready;
output itf_rd_data_valid;
output [CFG_LOCAL_DATA_WIDTH - 1 : 0] itf_rd_data;
output itf_rd_data_error;
output itf_rd_data_begin;
output itf_rd_data_last;
output [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_rd_data_id;
// AFI signals
output [AFI_CMD_WIDTH - 1 : 0] afi_rst_n;
output [AFI_CS_WIDTH - 1 : 0] afi_cs_n;
output [AFI_CKE_WIDTH - 1 : 0] afi_cke;
output [AFI_ODT_WIDTH - 1 : 0] afi_odt;
output [AFI_ADDR_WIDTH - 1 : 0] afi_addr;
output [AFI_BA_WIDTH - 1 : 0] afi_ba;
output [AFI_CMD_WIDTH - 1 : 0] afi_ras_n;
output [AFI_CMD_WIDTH - 1 : 0] afi_cas_n;
output [AFI_CMD_WIDTH - 1 : 0] afi_we_n;
output [AFI_DQS_BURST_WIDTH - 1 : 0] afi_dqs_burst;
output [AFI_WDATA_VALID_WIDTH - 1 : 0] afi_wdata_valid;
output [AFI_WDATA_WIDTH - 1 : 0] afi_wdata;
output [AFI_DM_WIDTH - 1 : 0] afi_dm;
input [AFI_WLAT_WIDTH - 1 : 0] afi_wlat;
output [AFI_RDATA_EN_WIDTH - 1 : 0] afi_rdata_en;
output [AFI_RDATA_EN_WIDTH - 1 : 0] afi_rdata_en_full;
output [AFI_RRANK_WIDTH - 1 : 0] afi_rrank;
output [AFI_WRANK_WIDTH - 1 : 0] afi_wrank;
input [AFI_RDATA_WIDTH - 1 : 0] afi_rdata;
input [AFI_RDATA_VALID_WIDTH - 1 : 0] afi_rdata_valid;
input [AFI_RLAT_WIDTH - 1 : 0] afi_rlat;
input afi_cal_success;
input afi_cal_fail;
output afi_cal_req;
output afi_init_req;
output [AFI_MEM_CLK_DISABLE_WIDTH - 1 : 0] afi_mem_clk_disable;
output [AFI_CAL_BYTE_LANE_SEL_N_WIDTH - 1 : 0] afi_cal_byte_lane_sel_n;
output [CFG_MEM_IF_CHIP - 1 : 0] afi_ctl_refresh_done;
input [CFG_MEM_IF_CHIP - 1 : 0] afi_seq_busy;
output [CFG_MEM_IF_CHIP - 1 : 0] afi_ctl_long_idle;
// Sideband signals
output local_init_done;
output local_refresh_ack;
output local_powerdn_ack;
output local_self_rfsh_ack;
output local_deep_powerdn_ack;
input local_refresh_req;
input [CFG_MEM_IF_CHIP - 1 : 0] local_refresh_chip;
input local_powerdn_req;
input local_self_rfsh_req;
input [CFG_MEM_IF_CHIP - 1 : 0] local_self_rfsh_chip;
input local_deep_powerdn_req;
input [CFG_MEM_IF_CHIP - 1 : 0] local_deep_powerdn_chip;
input local_zqcal_req;
input [CFG_MEM_IF_CHIP - 1 : 0] local_zqcal_chip;
input local_multicast;
input local_priority;
// Csr & ecc signals
output ecc_interrupt;
input csr_read_req;
input csr_write_req;
input [1 - 1 : 0] csr_burst_count;
input csr_beginbursttransfer;
input [CSR_ADDR_WIDTH - 1 : 0] csr_addr;
input [CSR_DATA_WIDTH - 1 : 0] csr_wdata;
output [CSR_DATA_WIDTH - 1 : 0] csr_rdata;
input [CSR_BE_WIDTH - 1 : 0] csr_be;
output csr_rdata_valid;
output csr_waitrequest;
// Refresh controller signals
output tbp_empty;
output cmd_gen_busy;
output sideband_in_refresh;
// END PORT SECTION
//////////////////////////////////////////////////////////////////////////////
wire [CFG_PORT_WIDTH_TYPE - 1 : 0] cfg_type;
wire [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
wire [CFG_PORT_WIDTH_ADDR_ORDER - 1 : 0] cfg_addr_order;
wire cfg_enable_ecc;
wire cfg_enable_auto_corr;
wire cfg_gen_sbe;
wire cfg_gen_dbe;
wire cfg_reorder_data;
wire cfg_user_rfsh;
wire cfg_regdimm_enable;
wire cfg_enable_burst_interrupt;
wire cfg_enable_burst_terminate;
wire cfg_enable_dqs_tracking;
wire [CFG_PORT_WIDTH_OUTPUT_REGD - 1 : 0] cfg_output_regd;
wire cfg_enable_no_dm;
wire cfg_enable_ecc_code_overwrites;
wire [CFG_PORT_WIDTH_CAS_WR_LAT - 1 : 0] cfg_cas_wr_lat;
wire [CFG_PORT_WIDTH_ADD_LAT - 1 : 0] cfg_add_lat;
wire [CFG_PORT_WIDTH_TCL - 1 : 0] cfg_tcl;
wire [CFG_PORT_WIDTH_TRRD - 1 : 0] cfg_trrd;
wire [CFG_PORT_WIDTH_TFAW - 1 : 0] cfg_tfaw;
wire [CFG_PORT_WIDTH_TRFC - 1 : 0] cfg_trfc;
wire [CFG_PORT_WIDTH_TREFI - 1 : 0] cfg_trefi;
wire [CFG_PORT_WIDTH_TRCD - 1 : 0] cfg_trcd;
wire [CFG_PORT_WIDTH_TRP - 1 : 0] cfg_trp;
wire [CFG_PORT_WIDTH_TWR - 1 : 0] cfg_twr;
wire [CFG_PORT_WIDTH_TWTR - 1 : 0] cfg_twtr;
wire [CFG_PORT_WIDTH_TRTP - 1 : 0] cfg_trtp;
wire [CFG_PORT_WIDTH_TRAS - 1 : 0] cfg_tras;
wire [CFG_PORT_WIDTH_TRC - 1 : 0] cfg_trc;
wire [CFG_PORT_WIDTH_AUTO_PD_CYCLES - 1 : 0] cfg_auto_pd_cycles;
wire [CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES - 1 : 0] cfg_self_rfsh_exit_cycles;
wire [CFG_PORT_WIDTH_PDN_EXIT_CYCLES - 1 : 0] cfg_pdn_exit_cycles;
wire [CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES - 1 : 0] cfg_power_saving_exit_cycles;
wire [CFG_PORT_WIDTH_MEM_CLK_ENTRY_CYCLES - 1 : 0] cfg_mem_clk_entry_cycles;
wire [CFG_PORT_WIDTH_TMRD - 1 : 0] cfg_tmrd;
wire [CFG_PORT_WIDTH_COL_ADDR_WIDTH - 1 : 0] cfg_col_addr_width;
wire [CFG_PORT_WIDTH_ROW_ADDR_WIDTH - 1 : 0] cfg_row_addr_width;
wire [CFG_PORT_WIDTH_BANK_ADDR_WIDTH - 1 : 0] cfg_bank_addr_width;
wire [CFG_PORT_WIDTH_CS_ADDR_WIDTH - 1 : 0] cfg_cs_addr_width;
wire cfg_enable_intr;
wire cfg_mask_sbe_intr;
wire cfg_mask_dbe_intr;
wire cfg_clr_intr;
wire cfg_cal_req;
wire [4 - 1 : 0] cfg_clock_off;
wire cfg_self_rfsh;
wire cfg_ganged_arf;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR - 1 : 0] cfg_extra_ctl_clk_act_to_rdwr;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH - 1 : 0] cfg_extra_ctl_clk_act_to_pch;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT - 1 : 0] cfg_extra_ctl_clk_act_to_act;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD - 1 : 0] cfg_extra_ctl_clk_rd_to_rd;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_rd_to_rd_diff_chip;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR - 1 : 0] cfg_extra_ctl_clk_rd_to_wr;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC - 1 : 0] cfg_extra_ctl_clk_rd_to_wr_bc;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_rd_to_wr_diff_chip;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH - 1 : 0] cfg_extra_ctl_clk_rd_to_pch;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID - 1 : 0] cfg_extra_ctl_clk_rd_ap_to_valid;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR - 1 : 0] cfg_extra_ctl_clk_wr_to_wr;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_wr_to_wr_diff_chip;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD - 1 : 0] cfg_extra_ctl_clk_wr_to_rd;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC - 1 : 0] cfg_extra_ctl_clk_wr_to_rd_bc;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_wr_to_rd_diff_chip;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH - 1 : 0] cfg_extra_ctl_clk_wr_to_pch;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID - 1 : 0] cfg_extra_ctl_clk_wr_ap_to_valid;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID - 1 : 0] cfg_extra_ctl_clk_pch_to_valid;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID - 1 : 0] cfg_extra_ctl_clk_pch_all_to_valid;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK - 1 : 0] cfg_extra_ctl_clk_act_to_act_diff_bank;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT - 1 : 0] cfg_extra_ctl_clk_four_act_to_act;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID - 1 : 0] cfg_extra_ctl_clk_arf_to_valid;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID - 1 : 0] cfg_extra_ctl_clk_pdn_to_valid;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID - 1 : 0] cfg_extra_ctl_clk_srf_to_valid;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL - 1 : 0] cfg_extra_ctl_clk_srf_to_zq_cal;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD - 1 : 0] cfg_extra_ctl_clk_arf_period;
wire [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD - 1 : 0] cfg_extra_ctl_clk_pdn_period;
wire [CFG_PORT_WIDTH_STARVE_LIMIT - 1 : 0] cfg_starve_limit;
wire [CFG_PORT_WIDTH_WRITE_ODT_CHIP - 1 : 0] cfg_write_odt_chip;
wire [CFG_PORT_WIDTH_READ_ODT_CHIP - 1 : 0] cfg_read_odt_chip;
wire [CFG_PORT_WIDTH_INTERFACE_WIDTH - 1 : 0] cfg_interface_width;
wire [CFG_PORT_WIDTH_DEVICE_WIDTH - 1 : 0] cfg_device_width;
wire [CFG_PORT_WIDTH_TCCD - 1 : 0] cfg_tccd;
wire cfg_mask_corr_dropped_intr;
wire [2 - 1 : 0] cfg_mem_bl;
wire cfg_user_ecc_en;
//ECC related outputs from controller to csr
wire [STS_PORT_WIDTH_SBE_ERROR - 1 : 0] sts_sbe_error;
wire [STS_PORT_WIDTH_DBE_ERROR - 1 : 0] sts_dbe_error;
wire [STS_PORT_WIDTH_SBE_COUNT - 1 : 0] sts_sbe_count;
wire [STS_PORT_WIDTH_DBE_COUNT - 1 : 0] sts_dbe_count;
wire [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_err_addr;
wire [STS_PORT_WIDTH_CORR_DROP_ERROR - 1 : 0] sts_corr_dropped;
wire [STS_PORT_WIDTH_CORR_DROP_COUNT - 1 : 0] sts_corr_dropped_count;
wire [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_corr_dropped_addr;
//
// Reconfiguration Support
//
// cfg_* signals may be reconfigured to different values using the Configuration Status Registers
// - some cfg_* signals are not reconfigurable, and are always assigned to parameters
// - When CSR is not enabled
// - cfg_* signals are assigned to parameters
// - when CSR is enabled
// - cfg_* signals are assigned to csr_* signals
// - csr_* signal generation based on Configuration Registers
// - default value for csr_* signals are based on parameters
// cfg_* signals that are not reconfigurable
assign cfg_type = CFG_TYPE;
assign cfg_interface_width = CFG_INTERFACE_WIDTH;
assign cfg_device_width = CFG_DEVICE_WIDTH;
assign cfg_enable_ecc_code_overwrites = CFG_ENABLE_ECC_CODE_OVERWRITES;
assign cfg_enable_no_dm = CFG_ENABLE_NO_DM;
assign cfg_output_regd = CFG_OUTPUT_REGD;
assign cfg_pdn_exit_cycles = CFG_PDN_EXIT_CYCLES;
assign cfg_power_saving_exit_cycles = CFG_POWER_SAVING_EXIT_CYCLES;
assign cfg_mem_clk_entry_cycles = CFG_MEM_CLK_ENTRY_CYCLES;
assign cfg_self_rfsh_exit_cycles = CFG_SELF_RFSH_EXIT_CYCLES;
assign cfg_tccd = CFG_TCCD;
assign cfg_tmrd = CFG_TMRD;
assign cfg_user_rfsh = CFG_USER_RFSH;
assign cfg_write_odt_chip = CFG_WRITE_ODT_CHIP;
assign cfg_read_odt_chip = CFG_READ_ODT_CHIP;
assign cfg_enable_dqs_tracking = CFG_ENABLE_DQS_TRACKING;
assign cfg_enable_burst_interrupt = CFG_ENABLE_BURST_INTERRUPT;
assign cfg_enable_burst_terminate = CFG_ENABLE_BURST_TERMINATE;
assign cfg_extra_ctl_clk_act_to_rdwr = CFG_EXTRA_CTL_CLK_ACT_TO_RDWR;
assign cfg_extra_ctl_clk_act_to_pch = CFG_EXTRA_CTL_CLK_ACT_TO_PCH;
assign cfg_extra_ctl_clk_act_to_act = CFG_EXTRA_CTL_CLK_ACT_TO_ACT;
assign cfg_extra_ctl_clk_rd_to_rd = CFG_EXTRA_CTL_CLK_RD_TO_RD;
assign cfg_extra_ctl_clk_rd_to_rd_diff_chip = CFG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP;
assign cfg_extra_ctl_clk_rd_to_wr = CFG_EXTRA_CTL_CLK_RD_TO_WR;
assign cfg_extra_ctl_clk_rd_to_wr_bc = CFG_EXTRA_CTL_CLK_RD_TO_WR_BC;
assign cfg_extra_ctl_clk_rd_to_wr_diff_chip = CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP;
assign cfg_extra_ctl_clk_rd_to_pch = CFG_EXTRA_CTL_CLK_RD_TO_PCH;
assign cfg_extra_ctl_clk_rd_ap_to_valid = CFG_EXTRA_CTL_CLK_RD_AP_TO_VALID;
assign cfg_extra_ctl_clk_wr_to_wr = CFG_EXTRA_CTL_CLK_WR_TO_WR;
assign cfg_extra_ctl_clk_wr_to_wr_diff_chip = CFG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP;
assign cfg_extra_ctl_clk_wr_to_rd = CFG_EXTRA_CTL_CLK_WR_TO_RD;
assign cfg_extra_ctl_clk_wr_to_rd_bc = CFG_EXTRA_CTL_CLK_WR_TO_RD_BC;
assign cfg_extra_ctl_clk_wr_to_rd_diff_chip = CFG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP;
assign cfg_extra_ctl_clk_wr_to_pch = CFG_EXTRA_CTL_CLK_WR_TO_PCH;
assign cfg_extra_ctl_clk_wr_ap_to_valid = CFG_EXTRA_CTL_CLK_WR_AP_TO_VALID;
assign cfg_extra_ctl_clk_pch_to_valid = CFG_EXTRA_CTL_CLK_PCH_TO_VALID;
assign cfg_extra_ctl_clk_pch_all_to_valid = CFG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID;
assign cfg_extra_ctl_clk_act_to_act_diff_bank = CFG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK;
assign cfg_extra_ctl_clk_four_act_to_act = CFG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT;
assign cfg_extra_ctl_clk_arf_to_valid = CFG_EXTRA_CTL_CLK_ARF_TO_VALID;
assign cfg_extra_ctl_clk_pdn_to_valid = CFG_EXTRA_CTL_CLK_PDN_TO_VALID;
assign cfg_extra_ctl_clk_srf_to_valid = CFG_EXTRA_CTL_CLK_SRF_TO_VALID;
assign cfg_extra_ctl_clk_srf_to_zq_cal = CFG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL;
assign cfg_extra_ctl_clk_arf_period = CFG_EXTRA_CTL_CLK_ARF_PERIOD;
assign cfg_extra_ctl_clk_pdn_period = CFG_EXTRA_CTL_CLK_PDN_PERIOD;
// cfg_* signals that are reconfigurable
generate
if (CTL_CSR_ENABLED == 1) begin
wire [CFG_PORT_WIDTH_TYPE - 1 : 0] csr_cfg_type;
wire [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] csr_cfg_burst_length;
wire [CFG_PORT_WIDTH_ADDR_ORDER - 1 : 0] csr_cfg_addr_order;
wire csr_cfg_enable_ecc;
wire csr_cfg_enable_auto_corr;
wire csr_cfg_gen_sbe;
wire csr_cfg_gen_dbe;
wire csr_cfg_reorder_data;
wire csr_cfg_regdimm_enable;
wire [CFG_PORT_WIDTH_CAS_WR_LAT - 1 : 0] csr_cfg_cas_wr_lat;
wire [CFG_PORT_WIDTH_ADD_LAT - 1 : 0] csr_cfg_add_lat;
wire [CFG_PORT_WIDTH_TCL - 1 : 0] csr_cfg_tcl;
wire [CFG_PORT_WIDTH_TRRD - 1 : 0] csr_cfg_trrd;
wire [CFG_PORT_WIDTH_TFAW - 1 : 0] csr_cfg_tfaw;
wire [CFG_PORT_WIDTH_TRFC - 1 : 0] csr_cfg_trfc;
wire [CFG_PORT_WIDTH_TREFI - 1 : 0] csr_cfg_trefi;
wire [CFG_PORT_WIDTH_TRCD - 1 : 0] csr_cfg_trcd;
wire [CFG_PORT_WIDTH_TRP - 1 : 0] csr_cfg_trp;
wire [CFG_PORT_WIDTH_TWR - 1 : 0] csr_cfg_twr;
wire [CFG_PORT_WIDTH_TWTR - 1 : 0] csr_cfg_twtr;
wire [CFG_PORT_WIDTH_TRTP - 1 : 0] csr_cfg_trtp;
wire [CFG_PORT_WIDTH_TRAS - 1 : 0] csr_cfg_tras;
wire [CFG_PORT_WIDTH_TRC - 1 : 0] csr_cfg_trc;
wire [CFG_PORT_WIDTH_AUTO_PD_CYCLES - 1 : 0] csr_cfg_auto_pd_cycles;
wire [CFG_PORT_WIDTH_COL_ADDR_WIDTH - 1 : 0] csr_cfg_col_addr_width;
wire [CFG_PORT_WIDTH_ROW_ADDR_WIDTH - 1 : 0] csr_cfg_row_addr_width;
wire [CFG_PORT_WIDTH_BANK_ADDR_WIDTH - 1 : 0] csr_cfg_bank_addr_width;
wire [CFG_PORT_WIDTH_CS_ADDR_WIDTH - 1 : 0] csr_cfg_cs_addr_width;
wire csr_cfg_enable_intr;
wire csr_cfg_mask_sbe_intr;
wire csr_cfg_mask_dbe_intr;
wire csr_cfg_clr_intr;
wire csr_cfg_cal_req;
wire [4 - 1 : 0] csr_cfg_clock_off;
wire csr_cfg_self_rfsh;
wire csr_cfg_ganged_arf;
wire [CFG_PORT_WIDTH_STARVE_LIMIT - 1 : 0] csr_cfg_starve_limit;
wire [CFG_PORT_WIDTH_INTERFACE_WIDTH - 1 : 0] csr_cfg_interface_width;
wire [CFG_PORT_WIDTH_DEVICE_WIDTH - 1 : 0] csr_cfg_device_width;
wire csr_cfg_mask_corr_dropped_intr;
wire [2 - 1 : 0] csr_cfg_mem_bl;
wire csr_cfg_user_ecc_en;
assign cfg_burst_length = csr_cfg_burst_length;
assign cfg_reorder_data = csr_cfg_reorder_data;
assign cfg_starve_limit = csr_cfg_starve_limit;
assign cfg_addr_order = csr_cfg_addr_order;
assign cfg_col_addr_width = csr_cfg_col_addr_width;
assign cfg_row_addr_width = csr_cfg_row_addr_width;
assign cfg_bank_addr_width = csr_cfg_bank_addr_width;
assign cfg_cs_addr_width = csr_cfg_cs_addr_width;
assign cfg_cas_wr_lat = csr_cfg_cas_wr_lat;
assign cfg_add_lat = csr_cfg_add_lat;
assign cfg_tcl = csr_cfg_tcl;
assign cfg_trrd = csr_cfg_trrd;
assign cfg_tfaw = csr_cfg_tfaw;
assign cfg_trfc = csr_cfg_trfc;
assign cfg_trefi = csr_cfg_trefi;
assign cfg_trcd = csr_cfg_trcd;
assign cfg_trp = csr_cfg_trp;
assign cfg_twr = csr_cfg_twr;
assign cfg_twtr = csr_cfg_twtr;
assign cfg_trtp = csr_cfg_trtp;
assign cfg_tras = csr_cfg_tras;
assign cfg_trc = csr_cfg_trc;
assign cfg_enable_ecc = csr_cfg_enable_ecc;
assign cfg_enable_auto_corr = csr_cfg_enable_auto_corr;
assign cfg_gen_sbe = csr_cfg_gen_sbe;
assign cfg_gen_dbe = csr_cfg_gen_dbe;
assign cfg_enable_intr = csr_cfg_enable_intr;
assign cfg_mask_sbe_intr = csr_cfg_mask_sbe_intr;
assign cfg_mask_dbe_intr = csr_cfg_mask_dbe_intr;
assign cfg_mask_corr_dropped_intr = csr_cfg_mask_corr_dropped_intr;
assign cfg_clr_intr = csr_cfg_clr_intr;
assign cfg_regdimm_enable = csr_cfg_regdimm_enable;
assign cfg_cal_req = csr_cfg_cal_req;
assign cfg_auto_pd_cycles = csr_cfg_auto_pd_cycles;
alt_mem_ddrx_csr # (
.CFG_AVALON_ADDR_WIDTH ( CSR_ADDR_WIDTH ),
.CFG_AVALON_DATA_WIDTH ( CSR_DATA_WIDTH ),
.CFG_BURST_LENGTH ( CFG_BURST_LENGTH ),
.CFG_REORDER_DATA ( CFG_REORDER_DATA ),
.CFG_STARVE_LIMIT ( CFG_STARVE_LIMIT ),
.CFG_ADDR_ORDER ( CFG_ADDR_ORDER ),
.CFG_COL_ADDR_WIDTH ( CFG_COL_ADDR_WIDTH ),
.CFG_ROW_ADDR_WIDTH ( CFG_ROW_ADDR_WIDTH ),
.CFG_BANK_ADDR_WIDTH ( CFG_BANK_ADDR_WIDTH ),
.CFG_CS_ADDR_WIDTH ( CFG_CS_ADDR_WIDTH ),
.CFG_CAS_WR_LAT ( CFG_CAS_WR_LAT ),
.CFG_ADD_LAT ( CFG_ADD_LAT ),
.CFG_TCL ( CFG_TCL ),
.CFG_TRRD ( CFG_TRRD ),
.CFG_TFAW ( CFG_TFAW ),
.CFG_TRFC ( CFG_TRFC ),
.CFG_TREFI ( CFG_TREFI ),
.CFG_TRCD ( CFG_TRCD ),
.CFG_TRP ( CFG_TRP ),
.CFG_TWR ( CFG_TWR ),
.CFG_TWTR ( CFG_TWTR ),
.CFG_TRTP ( CFG_TRTP ),
.CFG_TRAS ( CFG_TRAS ),
.CFG_TRC ( CFG_TRC ),
.CFG_AUTO_PD_CYCLES ( CFG_AUTO_PD_CYCLES ),
.CFG_ENABLE_ECC ( CFG_ENABLE_ECC ),
.CTL_ECC_CSR_ENABLED ( CFG_ENABLE_ECC ),
.CFG_ENABLE_AUTO_CORR ( CFG_ENABLE_AUTO_CORR ),
.CFG_REGDIMM_ENABLE ( CFG_REGDIMM_ENABLE ),
.MEM_IF_DQS_WIDTH ( CFG_MEM_IF_DQS_WIDTH )
) register_control_inst (
.avalon_mm_read ( csr_read_req ),
.avalon_mm_write ( csr_write_req ),
.avalon_mm_addr ( csr_addr ),
.avalon_mm_wdata ( csr_wdata ),
.avalon_mm_rdata ( csr_rdata ),
.avalon_mm_be ( csr_be ),
.avalon_mm_waitrequest ( csr_waitrequest ),
.avalon_mm_rdata_valid ( csr_rdata_valid ),
.cfg_burst_length ( csr_cfg_burst_length ),
.cfg_addr_order ( csr_cfg_addr_order ),
.cfg_enable_ecc ( csr_cfg_enable_ecc ),
.cfg_enable_auto_corr ( csr_cfg_enable_auto_corr ),
.cfg_gen_sbe ( csr_cfg_gen_sbe ),
.cfg_gen_dbe ( csr_cfg_gen_dbe ),
.cfg_reorder_data ( csr_cfg_reorder_data ),
.cfg_regdimm_enable ( csr_cfg_regdimm_enable ),
.cfg_cas_wr_lat ( csr_cfg_cas_wr_lat ),
.cfg_add_lat ( csr_cfg_add_lat ),
.cfg_tcl ( csr_cfg_tcl ),
.cfg_trrd ( csr_cfg_trrd ),
.cfg_tfaw ( csr_cfg_tfaw ),
.cfg_trfc ( csr_cfg_trfc ),
.cfg_trefi ( csr_cfg_trefi ),
.cfg_trcd ( csr_cfg_trcd ),
.cfg_trp ( csr_cfg_trp ),
.cfg_twr ( csr_cfg_twr ),
.cfg_twtr ( csr_cfg_twtr ),
.cfg_trtp ( csr_cfg_trtp ),
.cfg_tras ( csr_cfg_tras ),
.cfg_trc ( csr_cfg_trc ),
.cfg_auto_pd_cycles ( csr_cfg_auto_pd_cycles ),
.cfg_col_addr_width ( csr_cfg_col_addr_width ),
.cfg_row_addr_width ( csr_cfg_row_addr_width ),
.cfg_bank_addr_width ( csr_cfg_bank_addr_width ),
.cfg_cs_addr_width ( csr_cfg_cs_addr_width ),
.cfg_enable_intr ( csr_cfg_enable_intr ),
.cfg_mask_sbe_intr ( csr_cfg_mask_sbe_intr ),
.cfg_mask_dbe_intr ( csr_cfg_mask_dbe_intr ),
.cfg_clr_intr ( csr_cfg_clr_intr ),
.cfg_clock_off ( csr_cfg_clock_off ),
.cfg_starve_limit ( csr_cfg_starve_limit ),
.cfg_mask_corr_dropped_intr ( csr_cfg_mask_corr_dropped_intr ),
.cfg_cal_req ( csr_cfg_cal_req ),
.local_power_down_ack ( local_powerdn_ack ),
.local_self_rfsh_ack ( local_self_rfsh_ack ),
.sts_cal_success ( afi_cal_success ),
.sts_cal_fail ( afi_cal_fail ),
.sts_sbe_error ( sts_sbe_error ),
.sts_dbe_error ( sts_dbe_error ),
.sts_sbe_count ( sts_sbe_count ),
.sts_dbe_count ( sts_dbe_count ),
.sts_err_addr ( sts_err_addr ),
.sts_corr_dropped ( sts_corr_dropped ),
.sts_corr_dropped_count ( sts_corr_dropped_count ),
.sts_corr_dropped_addr ( sts_corr_dropped_addr ),
.ctl_clk ( clk ),
.ctl_rst_n ( reset_n )
);
end
else begin
assign csr_rdata = 0;
assign csr_rdata_valid = 0;
assign csr_waitrequest = 0;
assign cfg_burst_length = CFG_BURST_LENGTH;
assign cfg_reorder_data = CFG_REORDER_DATA;
assign cfg_starve_limit = CFG_STARVE_LIMIT;
assign cfg_addr_order = CFG_ADDR_ORDER;
assign cfg_col_addr_width = CFG_COL_ADDR_WIDTH;
assign cfg_row_addr_width = CFG_ROW_ADDR_WIDTH;
assign cfg_bank_addr_width = CFG_BANK_ADDR_WIDTH;
assign cfg_cs_addr_width = CFG_CS_ADDR_WIDTH;
assign cfg_cas_wr_lat = CFG_CAS_WR_LAT;
assign cfg_add_lat = CFG_ADD_LAT;
assign cfg_tcl = CFG_TCL;
assign cfg_trrd = CFG_TRRD;
assign cfg_tfaw = CFG_TFAW;
assign cfg_trfc = CFG_TRFC;
assign cfg_trefi = CFG_TREFI;
assign cfg_trcd = CFG_TRCD;
assign cfg_trp = CFG_TRP;
assign cfg_twr = CFG_TWR;
assign cfg_twtr = CFG_TWTR;
assign cfg_trtp = CFG_TRTP;
assign cfg_tras = CFG_TRAS;
assign cfg_trc = CFG_TRC;
assign cfg_auto_pd_cycles = CFG_AUTO_PD_CYCLES;
assign cfg_enable_ecc = CFG_ENABLE_ECC;
assign cfg_enable_auto_corr = CFG_ENABLE_AUTO_CORR;
assign cfg_gen_sbe = CFG_GEN_SBE;
assign cfg_gen_dbe = CFG_GEN_DBE;
assign cfg_enable_intr = CFG_ENABLE_INTR;
assign cfg_mask_sbe_intr = CFG_MASK_SBE_INTR;
assign cfg_mask_dbe_intr = CFG_MASK_DBE_INTR;
assign cfg_mask_corr_dropped_intr = CFG_MASK_CORR_DROPPED_INTR;
assign cfg_clr_intr = CFG_CLR_INTR;
assign cfg_regdimm_enable = CFG_REGDIMM_ENABLE;
assign cfg_cal_req = CFG_CAL_REQ;
end
endgenerate
// Next Gen Controller
alt_mem_ddrx_controller # (
.CFG_LOCAL_SIZE_WIDTH ( CFG_LOCAL_SIZE_WIDTH ),
.CFG_LOCAL_ADDR_WIDTH ( CFG_LOCAL_ADDR_WIDTH ),
.CFG_LOCAL_DATA_WIDTH ( CFG_LOCAL_DATA_WIDTH ),
.CFG_LOCAL_ID_WIDTH ( CFG_LOCAL_ID_WIDTH ),
.CFG_LOCAL_IF_TYPE ( CFG_LOCAL_IF_TYPE ),
.CFG_MEM_IF_ADDR_WIDTH ( CFG_MEM_IF_ADDR_WIDTH ),
.CFG_MEM_IF_CLK_PAIR_COUNT ( CFG_MEM_IF_CLK_PAIR_COUNT ),
.CFG_DWIDTH_RATIO ( CFG_DWIDTH_RATIO ),
.CFG_ODT_ENABLED ( CFG_ODT_ENABLED ),
.CFG_LPDDR2_ENABLED ( CFG_LPDDR2_ENABLED ),
.CFG_CTL_TBP_NUM ( CFG_CTL_TBP_NUM ),
.CFG_DATA_REORDERING_TYPE ( CFG_DATA_REORDERING_TYPE ),
.CFG_WRBUFFER_ADDR_WIDTH ( CFG_WRBUFFER_ADDR_WIDTH ),
.CFG_RDBUFFER_ADDR_WIDTH ( CFG_RDBUFFER_ADDR_WIDTH ),
.CFG_MAX_PENDING_RD_CMD ( CFG_MAX_PENDING_RD_CMD ),
.CFG_MAX_PENDING_WR_CMD ( CFG_MAX_PENDING_WR_CMD ),
.CFG_ECC_MULTIPLES_16_24_40_72 ( CFG_ECC_MULTIPLES_16_24_40_72 ),
.CFG_MEM_IF_CS_WIDTH ( CFG_MEM_IF_CS_WIDTH ),
.CFG_MEM_IF_CHIP ( CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_BA_WIDTH ( CFG_MEM_IF_BA_WIDTH ),
.CFG_MEM_IF_ROW_WIDTH ( CFG_MEM_IF_ROW_WIDTH ),
.CFG_MEM_IF_COL_WIDTH ( CFG_MEM_IF_COL_WIDTH ),
.CFG_MEM_IF_CKE_WIDTH ( CFG_MEM_IF_CKE_WIDTH ),
.CFG_MEM_IF_ODT_WIDTH ( CFG_MEM_IF_ODT_WIDTH ),
.CFG_MEM_IF_DQS_WIDTH ( CFG_MEM_IF_DQS_WIDTH ),
.CFG_MEM_IF_DQ_WIDTH ( CFG_MEM_IF_DQ_WIDTH ),
.CFG_MEM_IF_DM_WIDTH ( CFG_MEM_IF_DM_WIDTH ),
.CFG_PORT_WIDTH_TYPE ( CFG_PORT_WIDTH_TYPE ),
.CFG_PORT_WIDTH_INTERFACE_WIDTH ( CFG_PORT_WIDTH_INTERFACE_WIDTH ),
.CFG_PORT_WIDTH_BURST_LENGTH ( CFG_PORT_WIDTH_BURST_LENGTH ),
.CFG_PORT_WIDTH_DEVICE_WIDTH ( CFG_PORT_WIDTH_DEVICE_WIDTH ),
.CFG_PORT_WIDTH_REORDER_DATA ( CFG_PORT_WIDTH_REORDER_DATA ),
.CFG_PORT_WIDTH_STARVE_LIMIT ( CFG_PORT_WIDTH_STARVE_LIMIT ),
.CFG_PORT_WIDTH_OUTPUT_REGD ( CFG_PORT_WIDTH_OUTPUT_REGD ),
.CFG_PORT_WIDTH_ADDR_ORDER ( CFG_PORT_WIDTH_ADDR_ORDER ),
.CFG_PORT_WIDTH_COL_ADDR_WIDTH ( CFG_PORT_WIDTH_COL_ADDR_WIDTH ),
.CFG_PORT_WIDTH_ROW_ADDR_WIDTH ( CFG_PORT_WIDTH_ROW_ADDR_WIDTH ),
.CFG_PORT_WIDTH_BANK_ADDR_WIDTH ( CFG_PORT_WIDTH_BANK_ADDR_WIDTH ),
.CFG_PORT_WIDTH_CS_ADDR_WIDTH ( CFG_PORT_WIDTH_CS_ADDR_WIDTH ),
.CFG_PORT_WIDTH_CAS_WR_LAT ( CFG_PORT_WIDTH_CAS_WR_LAT ),
.CFG_PORT_WIDTH_ADD_LAT ( CFG_PORT_WIDTH_ADD_LAT ),
.CFG_PORT_WIDTH_TCL ( CFG_PORT_WIDTH_TCL ),
.CFG_PORT_WIDTH_TRRD ( CFG_PORT_WIDTH_TRRD ),
.CFG_PORT_WIDTH_TFAW ( CFG_PORT_WIDTH_TFAW ),
.CFG_PORT_WIDTH_TRFC ( CFG_PORT_WIDTH_TRFC ),
.CFG_PORT_WIDTH_TREFI ( CFG_PORT_WIDTH_TREFI ),
.CFG_PORT_WIDTH_TRCD ( CFG_PORT_WIDTH_TRCD ),
.CFG_PORT_WIDTH_TRP ( CFG_PORT_WIDTH_TRP ),
.CFG_PORT_WIDTH_TWR ( CFG_PORT_WIDTH_TWR ),
.CFG_PORT_WIDTH_TWTR ( CFG_PORT_WIDTH_TWTR ),
.CFG_PORT_WIDTH_TRTP ( CFG_PORT_WIDTH_TRTP ),
.CFG_PORT_WIDTH_TRAS ( CFG_PORT_WIDTH_TRAS ),
.CFG_PORT_WIDTH_TRC ( CFG_PORT_WIDTH_TRC ),
.CFG_PORT_WIDTH_TCCD ( CFG_PORT_WIDTH_TCCD ),
.CFG_PORT_WIDTH_TMRD ( CFG_PORT_WIDTH_TMRD ),
.CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES ( CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES ),
.CFG_PORT_WIDTH_PDN_EXIT_CYCLES ( CFG_PORT_WIDTH_PDN_EXIT_CYCLES ),
.CFG_PORT_WIDTH_AUTO_PD_CYCLES ( CFG_PORT_WIDTH_AUTO_PD_CYCLES ),
.CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES ( CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES ),
.CFG_PORT_WIDTH_MEM_CLK_ENTRY_CYCLES ( CFG_PORT_WIDTH_MEM_CLK_ENTRY_CYCLES ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD ),
.CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD ( CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD ),
.CFG_PORT_WIDTH_ENABLE_ECC ( CFG_PORT_WIDTH_ENABLE_ECC ),
.CFG_PORT_WIDTH_ENABLE_AUTO_CORR ( CFG_PORT_WIDTH_ENABLE_AUTO_CORR ),
.CFG_PORT_WIDTH_GEN_SBE ( CFG_PORT_WIDTH_GEN_SBE ),
.CFG_PORT_WIDTH_GEN_DBE ( CFG_PORT_WIDTH_GEN_DBE ),
.CFG_PORT_WIDTH_ENABLE_INTR ( CFG_PORT_WIDTH_ENABLE_INTR ),
.CFG_PORT_WIDTH_MASK_SBE_INTR ( CFG_PORT_WIDTH_MASK_SBE_INTR ),
.CFG_PORT_WIDTH_MASK_DBE_INTR ( CFG_PORT_WIDTH_MASK_DBE_INTR ),
.CFG_PORT_WIDTH_CLR_INTR ( CFG_PORT_WIDTH_CLR_INTR ),
.CFG_PORT_WIDTH_USER_RFSH ( CFG_PORT_WIDTH_USER_RFSH ),
.CFG_PORT_WIDTH_SELF_RFSH ( CFG_PORT_WIDTH_SELF_RFSH ),
.CFG_PORT_WIDTH_REGDIMM_ENABLE ( CFG_PORT_WIDTH_REGDIMM_ENABLE ),
.CFG_PORT_WIDTH_ENABLE_BURST_INTERRUPT ( CFG_PORT_WIDTH_ENABLE_BURST_INTERRUPT ),
.CFG_PORT_WIDTH_ENABLE_BURST_TERMINATE ( CFG_PORT_WIDTH_ENABLE_BURST_TERMINATE ),
.CFG_ENABLE_WDATA_PATH_LATENCY ( CFG_ENABLE_WDATA_PATH_LATENCY ),
.CFG_PORT_WIDTH_WRITE_ODT_CHIP ( CFG_PORT_WIDTH_WRITE_ODT_CHIP ),
.CFG_PORT_WIDTH_READ_ODT_CHIP ( CFG_PORT_WIDTH_READ_ODT_CHIP ),
.CFG_WLAT_BUS_WIDTH ( CFG_WLAT_BUS_WIDTH ),
.CFG_RRANK_BUS_WIDTH ( CFG_RRANK_BUS_WIDTH ),
.CFG_WRANK_BUS_WIDTH ( CFG_WRANK_BUS_WIDTH ),
.CFG_USE_SHADOW_REGS ( CFG_USE_SHADOW_REGS ),
.CFG_RDATA_RETURN_MODE ( CFG_RDATA_RETURN_MODE ),
.CFG_ECC_DECODER_REG ( CFG_ECC_DECODER_REG ),
.CFG_ERRCMD_FIFO_REG ( CFG_ERRCMD_FIFO_REG ),
.CFG_ENABLE_BURST_MERGE ( CFG_ENABLE_BURST_MERGE )
) controller_inst (
.ctl_clk ( clk ),
.ctl_reset_n ( reset_n ),
.itf_cmd_ready ( itf_cmd_ready ),
.itf_cmd_valid ( itf_cmd_valid ),
.itf_cmd ( itf_cmd ),
.itf_cmd_address ( itf_cmd_address ),
.itf_cmd_burstlen ( itf_cmd_burstlen ),
.itf_cmd_id ( itf_cmd_id ),
.itf_cmd_priority ( itf_cmd_priority ),
.itf_cmd_autopercharge ( itf_cmd_autopercharge ),
.itf_cmd_multicast ( itf_cmd_multicast ),
.itf_wr_data_ready ( itf_wr_data_ready ),
.itf_wr_data_valid ( itf_wr_data_valid ),
.itf_wr_data ( itf_wr_data ),
.itf_wr_data_byte_en ( itf_wr_data_byte_en ),
.itf_wr_data_begin ( itf_wr_data_begin ),
.itf_wr_data_last ( itf_wr_data_last ),
.itf_wr_data_id ( itf_wr_data_id ),
.itf_rd_data_ready ( itf_rd_data_ready ),
.itf_rd_data_valid ( itf_rd_data_valid ),
.itf_rd_data ( itf_rd_data ),
.itf_rd_data_error ( itf_rd_data_error ),
.itf_rd_data_begin ( itf_rd_data_begin ),
.itf_rd_data_last ( itf_rd_data_last ),
.itf_rd_data_id ( itf_rd_data_id ),
.local_refresh_req ( local_refresh_req ),
.local_refresh_chip ( local_refresh_chip ),
.local_deep_powerdn_req ( local_deep_powerdn_req ),
.local_deep_powerdn_chip ( local_deep_powerdn_chip ),
.local_self_rfsh_req ( local_self_rfsh_req ),
.local_self_rfsh_chip ( local_self_rfsh_chip ),
.local_zqcal_req ( local_zqcal_req ),
.local_zqcal_chip ( local_zqcal_chip ),
.local_refresh_ack ( local_refresh_ack ),
.local_deep_powerdn_ack ( local_deep_powerdn_ack ),
.local_power_down_ack ( local_powerdn_ack ),
.local_self_rfsh_ack ( local_self_rfsh_ack ),
.local_init_done ( local_init_done ),
.afi_cke ( afi_cke ),
.afi_cs_n ( afi_cs_n ),
.afi_ras_n ( afi_ras_n ),
.afi_cas_n ( afi_cas_n ),
.afi_we_n ( afi_we_n ),
.afi_ba ( afi_ba ),
.afi_addr ( afi_addr ),
.afi_odt ( afi_odt ),
.afi_rst_n ( afi_rst_n ),
.afi_dqs_burst ( afi_dqs_burst ),
.afi_wdata_valid ( afi_wdata_valid ),
.afi_wdata ( afi_wdata ),
.afi_dm ( afi_dm ),
.afi_wlat ( afi_wlat ),
.afi_rdata_en ( afi_rdata_en ),
.afi_rdata_en_full ( afi_rdata_en_full ),
.afi_rrank ( afi_rrank ),
.afi_wrank ( afi_wrank ),
.afi_rdata ( afi_rdata ),
.afi_rdata_valid ( afi_rdata_valid ),
.ctl_cal_success ( afi_cal_success ),
.ctl_cal_fail ( afi_cal_fail ),
.ctl_cal_req ( afi_cal_req ),
.ctl_init_req ( afi_init_req ),
.ctl_mem_clk_disable ( afi_mem_clk_disable ),
.ctl_cal_byte_lane_sel_n ( afi_cal_byte_lane_sel_n ),
.cfg_type ( cfg_type ),
.cfg_interface_width ( cfg_interface_width ),
.cfg_burst_length ( cfg_burst_length ),
.cfg_device_width ( cfg_device_width ),
.cfg_reorder_data ( cfg_reorder_data ),
.cfg_starve_limit ( cfg_starve_limit ),
.cfg_output_regd ( cfg_output_regd ),
.cfg_addr_order ( cfg_addr_order ),
.cfg_col_addr_width ( cfg_col_addr_width ),
.cfg_row_addr_width ( cfg_row_addr_width ),
.cfg_bank_addr_width ( cfg_bank_addr_width ),
.cfg_cs_addr_width ( cfg_cs_addr_width ),
.cfg_cas_wr_lat ( cfg_cas_wr_lat ),
.cfg_add_lat ( cfg_add_lat ),
.cfg_tcl ( cfg_tcl ),
.cfg_trrd ( cfg_trrd ),
.cfg_tfaw ( cfg_tfaw ),
.cfg_trfc ( cfg_trfc ),
.cfg_trefi ( cfg_trefi ),
.cfg_trcd ( cfg_trcd ),
.cfg_trp ( cfg_trp ),
.cfg_twr ( cfg_twr ),
.cfg_twtr ( cfg_twtr ),
.cfg_trtp ( cfg_trtp ),
.cfg_tras ( cfg_tras ),
.cfg_trc ( cfg_trc ),
.cfg_tccd ( cfg_tccd ),
.cfg_auto_pd_cycles ( cfg_auto_pd_cycles ),
.cfg_self_rfsh_exit_cycles ( cfg_self_rfsh_exit_cycles ),
.cfg_pdn_exit_cycles ( cfg_pdn_exit_cycles ),
.cfg_power_saving_exit_cycles ( cfg_power_saving_exit_cycles ),
.cfg_mem_clk_entry_cycles ( cfg_mem_clk_entry_cycles ),
.cfg_tmrd ( cfg_tmrd ),
.cfg_enable_ecc ( cfg_enable_ecc ),
.cfg_enable_auto_corr ( cfg_enable_auto_corr ),
.cfg_enable_no_dm ( cfg_enable_no_dm ),
.cfg_enable_ecc_code_overwrites ( cfg_enable_ecc_code_overwrites ),
.cfg_cal_req ( cfg_cal_req ),
.cfg_gen_sbe ( cfg_gen_sbe ),
.cfg_gen_dbe ( cfg_gen_dbe ),
.cfg_enable_intr ( cfg_enable_intr ),
.cfg_mask_sbe_intr ( cfg_mask_sbe_intr ),
.cfg_mask_dbe_intr ( cfg_mask_dbe_intr ),
.cfg_mask_corr_dropped_intr ( cfg_mask_corr_dropped_intr ),
.cfg_clr_intr ( cfg_clr_intr ),
.cfg_user_rfsh ( cfg_user_rfsh ),
.cfg_regdimm_enable ( cfg_regdimm_enable ),
.cfg_enable_burst_interrupt ( cfg_enable_burst_interrupt ),
.cfg_enable_burst_terminate ( cfg_enable_burst_terminate ),
.cfg_write_odt_chip ( cfg_write_odt_chip ),
.cfg_read_odt_chip ( cfg_read_odt_chip ),
.cfg_extra_ctl_clk_act_to_rdwr ( cfg_extra_ctl_clk_act_to_rdwr ),
.cfg_extra_ctl_clk_act_to_pch ( cfg_extra_ctl_clk_act_to_pch ),
.cfg_extra_ctl_clk_act_to_act ( cfg_extra_ctl_clk_act_to_act ),
.cfg_extra_ctl_clk_rd_to_rd ( cfg_extra_ctl_clk_rd_to_rd ),
.cfg_extra_ctl_clk_rd_to_rd_diff_chip ( cfg_extra_ctl_clk_rd_to_rd_diff_chip ),
.cfg_extra_ctl_clk_rd_to_wr ( cfg_extra_ctl_clk_rd_to_wr ),
.cfg_extra_ctl_clk_rd_to_wr_bc ( cfg_extra_ctl_clk_rd_to_wr_bc ),
.cfg_extra_ctl_clk_rd_to_wr_diff_chip ( cfg_extra_ctl_clk_rd_to_wr_diff_chip ),
.cfg_extra_ctl_clk_rd_to_pch ( cfg_extra_ctl_clk_rd_to_pch ),
.cfg_extra_ctl_clk_rd_ap_to_valid ( cfg_extra_ctl_clk_rd_ap_to_valid ),
.cfg_extra_ctl_clk_wr_to_wr ( cfg_extra_ctl_clk_wr_to_wr ),
.cfg_extra_ctl_clk_wr_to_wr_diff_chip ( cfg_extra_ctl_clk_wr_to_wr_diff_chip ),
.cfg_extra_ctl_clk_wr_to_rd ( cfg_extra_ctl_clk_wr_to_rd ),
.cfg_extra_ctl_clk_wr_to_rd_bc ( cfg_extra_ctl_clk_wr_to_rd_bc ),
.cfg_extra_ctl_clk_wr_to_rd_diff_chip ( cfg_extra_ctl_clk_wr_to_rd_diff_chip ),
.cfg_extra_ctl_clk_wr_to_pch ( cfg_extra_ctl_clk_wr_to_pch ),
.cfg_extra_ctl_clk_wr_ap_to_valid ( cfg_extra_ctl_clk_wr_ap_to_valid ),
.cfg_extra_ctl_clk_pch_to_valid ( cfg_extra_ctl_clk_pch_to_valid ),
.cfg_extra_ctl_clk_pch_all_to_valid ( cfg_extra_ctl_clk_pch_all_to_valid ),
.cfg_extra_ctl_clk_act_to_act_diff_bank ( cfg_extra_ctl_clk_act_to_act_diff_bank ),
.cfg_extra_ctl_clk_four_act_to_act ( cfg_extra_ctl_clk_four_act_to_act ),
.cfg_extra_ctl_clk_arf_to_valid ( cfg_extra_ctl_clk_arf_to_valid ),
.cfg_extra_ctl_clk_pdn_to_valid ( cfg_extra_ctl_clk_pdn_to_valid ),
.cfg_extra_ctl_clk_srf_to_valid ( cfg_extra_ctl_clk_srf_to_valid ),
.cfg_extra_ctl_clk_srf_to_zq_cal ( cfg_extra_ctl_clk_srf_to_zq_cal ),
.cfg_extra_ctl_clk_arf_period ( cfg_extra_ctl_clk_arf_period ),
.cfg_extra_ctl_clk_pdn_period ( cfg_extra_ctl_clk_pdn_period ),
.cfg_enable_dqs_tracking ( cfg_enable_dqs_tracking ),
.ecc_interrupt ( ecc_interrupt ),
.sts_sbe_error ( sts_sbe_error ),
.sts_dbe_error ( sts_dbe_error ),
.sts_sbe_count ( sts_sbe_count ),
.sts_dbe_count ( sts_dbe_count ),
.sts_err_addr ( sts_err_addr ),
.sts_corr_dropped ( sts_corr_dropped ),
.sts_corr_dropped_count ( sts_corr_dropped_count ),
.sts_corr_dropped_addr ( sts_corr_dropped_addr ),
.afi_ctl_refresh_done ( afi_ctl_refresh_done ),
.afi_seq_busy ( afi_seq_busy ),
.afi_ctl_long_idle ( afi_ctl_long_idle ),
.itf_rd_data_id_early ( ),
.itf_rd_data_id_early_valid ( ),
.sts_cal_fail ( ),
.sts_cal_success ( ),
.tbp_empty ( tbp_empty ),
.cmd_gen_busy ( cmd_gen_busy ),
.sideband_in_refresh ( sideband_in_refresh )
);
endmodule
|
module premuat3_16(
enable,
inverse,
i_0,
i_1,
i_2,
i_3,
i_4,
i_5,
i_6,
i_7,
i_8,
i_9,
i_10,
i_11,
i_12,
i_13,
i_14,
i_15,
o_0,
o_1,
o_2,
o_3,
o_4,
o_5,
o_6,
o_7,
o_8,
o_9,
o_10,
o_11,
o_12,
o_13,
o_14,
o_15
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input enable;
input inverse;
input signed [27:0] i_0;
input signed [27:0] i_1;
input signed [27:0] i_2;
input signed [27:0] i_3;
input signed [27:0] i_4;
input signed [27:0] i_5;
input signed [27:0] i_6;
input signed [27:0] i_7;
input signed [27:0] i_8;
input signed [27:0] i_9;
input signed [27:0] i_10;
input signed [27:0] i_11;
input signed [27:0] i_12;
input signed [27:0] i_13;
input signed [27:0] i_14;
input signed [27:0] i_15;
output signed [27:0] o_0;
output signed [27:0] o_1;
output signed [27:0] o_2;
output signed [27:0] o_3;
output signed [27:0] o_4;
output signed [27:0] o_5;
output signed [27:0] o_6;
output signed [27:0] o_7;
output signed [27:0] o_8;
output signed [27:0] o_9;
output signed [27:0] o_10;
output signed [27:0] o_11;
output signed [27:0] o_12;
output signed [27:0] o_13;
output signed [27:0] o_14;
output signed [27:0] o_15;
// ********************************************
//
// REG DECLARATION
//
// ********************************************
reg signed [27:0] o1;
reg signed [27:0] o2;
reg signed [27:0] o3;
reg signed [27:0] o4;
reg signed [27:0] o5;
reg signed [27:0] o6;
reg signed [27:0] o7;
reg signed [27:0] o8;
reg signed [27:0] o9;
reg signed [27:0] o10;
reg signed [27:0] o11;
reg signed [27:0] o12;
reg signed [27:0] o13;
reg signed [27:0] o14;
// ********************************************
//
// Combinational Logic
//
// ********************************************
always@(*)
if(inverse)
begin
o1 =i_2;
o2 =i_4;
o3 =i_6;
o4 =i_8;
o5 =i_10;
o6 =i_12;
o7 =i_14;
o8 =i_1;
o9 =i_3;
o10=i_5;
o11=i_7;
o12=i_9;
o13=i_11;
o14=i_13;
end
else
begin
o1 =i_8;
o2 =i_1;
o3 =i_9;
o4 =i_2;
o5 =i_10;
o6 =i_3;
o7 =i_11;
o8 =i_4;
o9 =i_12;
o10=i_5;
o11=i_13;
o12=i_6;
o13=i_14;
o14=i_7;
end
assign o_0=i_0;
assign o_1=enable?o1:i_1;
assign o_2=enable?o2:i_2;
assign o_3=enable?o3:i_3;
assign o_4=enable?o4:i_4;
assign o_5=enable?o5:i_5;
assign o_6=enable?o6:i_6;
assign o_7=enable?o7:i_7;
assign o_8=enable?o8:i_8;
assign o_9=enable?o9:i_9;
assign o_10=enable?o10:i_10;
assign o_11=enable?o11:i_11;
assign o_12=enable?o12:i_12;
assign o_13=enable?o13:i_13;
assign o_14=enable?o14:i_14;
assign o_15=i_15;
endmodule
|
`timescale 1ns/1ns
module usb_rx_sie
(input c,
input c_48,
input oe,
input vp,
input vm,
output [7:0] d,
output dv);
wire bit_d, bit_dv;
wire eop;
usb_rx_nrzi rx_nrzi_inst
(.c_48(c_48), .vp(vp), .vm(vm), .oe(oe), .d(bit_d), .dv(bit_dv), .eop(eop));
// todo: state machine to parse out the bytes and figure out when to
// expect crc16, etc., based on length of the inbound data stream
localparam ST_IDLE = 4'h0;
localparam ST_SYNC = 4'h1;
localparam ST_DATA = 4'h2;
localparam ST_EOP = 4'h3;
localparam ST_CHECK_CRC = 4'h4;
localparam ST_DRAIN = 4'h5; // drains the RX fifo out to busclk domain
localparam ST_DONE = 4'h6;
localparam ST_ERROR = 4'hf;
localparam SW=4, CW=5;
reg [CW+SW-1:0] ctrl;
wire [SW-1:0] state;
wire [SW-1:0] next_state = ctrl[SW+CW-1:CW];
r #(SW) state_r
(.c(c_48), .rst(oe), .en(1'b1), .d(next_state), .q(state));
wire [3:0] bit_cnt;
wire bit_cnt_rst;
r #(4) bit_cnt_r
(.c(c_48), .en(bit_dv), .rst(bit_cnt_rst), .d(bit_cnt+1'b1), .q(bit_cnt));
wire rx_byte_en = bit_dv;
wire [7:0] rx_byte;
r #(8) rx_byte_r
(.c(c_48), .en(rx_byte_en), .rst(1'b0),
.d({bit_d, rx_byte[7:1]}), .q(rx_byte));
wire [6:0] byte_cnt;
wire byte_cnt_en, byte_cnt_rst;
r #(7) byte_cnt_r
(.c(c_48), .en(byte_cnt_en), .rst(byte_cnt_rst),
.d(byte_cnt + 1'b1), .q(byte_cnt));
always @* begin
case (state)
ST_IDLE:
if (bit_dv) ctrl = { ST_SYNC , 5'b00000 };
else ctrl = { ST_IDLE , 5'b00001 };
ST_SYNC:
if (bit_cnt == 4'd8)
if (rx_byte == 8'h80 ) ctrl = { ST_DATA , 5'b00001 };
else ctrl = { ST_ERROR , 5'b00001 };
else ctrl = { ST_SYNC , 5'b00000 };
ST_DATA:
if (eop) ctrl = { ST_EOP , 5'b00001 };
else if (bit_cnt == 4'd8) ctrl = { ST_DATA , 5'b00011 };
else ctrl = { ST_DATA , 5'b00000 };
ST_EOP:
if (byte_cnt == 7'd0) ctrl = { ST_DONE , 5'b00000 }; // bad
else if (byte_cnt == 7'd1) ctrl = { ST_DRAIN , 5'b00100 }; // no crc
else ctrl = { ST_CHECK_CRC, 5'b00000 };
ST_CHECK_CRC: // TODO: actually check CRC
ctrl = { ST_DRAIN , 5'b00100 };
ST_DRAIN: ctrl = { ST_DONE , 5'b00000 };
ST_DONE: ctrl = { ST_IDLE , 5'b00000 };
ST_ERROR: ctrl = { ST_ERROR , 5'b00000 };
default: ctrl = { ST_IDLE , 5'b00000 };
endcase
end
assign bit_cnt_rst = ctrl[0];
wire fifo_wrreq = ctrl[1];
assign byte_cnt_en = ctrl[1];
assign byte_cnt_rst = state == ST_IDLE;
wire fifo_drain_start_48 = state == ST_DRAIN;
wire fifo_drain_start;
sync fifo_drain_start_sync_r
(.in(fifo_drain_start_48), .clk(c), .out(fifo_drain_start));
wire fifo_draining, fifo_rdempty;
r fifo_draining_r
(.c(c), .en(fifo_drain_start), .rst(fifo_rdempty),
.d(1'b1), .q(fifo_draining));
wire pkt_valid;
r pkt_valid_r
(.c(c_48), .en(ctrl[2]), .rst(state == ST_IDLE), .d(1'b1), .q(pkt_valid));
wire pkt_valid_s;
sync pkt_valid_sync_r(.in(pkt_valid), .clk(c), .out(pkt_valid_s));
wire pkt_valid_s_sticky;
r pkt_valid_s_sticky_r
(.c(c), .rst(fifo_rdempty), .en(pkt_valid_s),
.d(1'b1), .q(pkt_valid_s_sticky));
wire xclk_fifo_aclr;
sync xclk_fifo_aclr_sync_r
(.in(oe), .clk(c), .out(xclk_fifo_aclr));
wire [7:0] d_i;
dcfifo
#(.lpm_width(8), .lpm_widthu(7), .lpm_numwords(128), .lpm_showahead("ON"),
.use_eab("ON"), .intended_device_family("CYCLONE V")) xclk_fifo
(.wrclk(c_48), .data(rx_byte), .wrreq(fifo_wrreq),
.rdclk(c), .rdreq(fifo_draining & ~fifo_rdempty),
.q(d_i), .rdempty(fifo_rdempty),
.aclr(xclk_fifo_aclr)); //1'b0));
wire dv_i = pkt_valid_s_sticky & fifo_draining & ~fifo_rdempty;
// delay the output stream one clock to help timing
d1 dv_d1_r(.c(c), .d(dv_i), .q(dv));
d1 #(8) d_d1_r(.c(c), .d(d_i), .q(d));
endmodule
|
(** * Smallstep: Small-step Operational Semantics *)
Require Export Imp.
(** The evaluators we have seen so far (e.g., the ones for
[aexp]s, [bexp]s, and commands) have been formulated in a
"big-step" style -- they specify how a given expression can be
evaluated to its final value (or a command plus a store to a final
store) "all in one big step."
This style is simple and natural for many purposes -- indeed,
Gilles Kahn, who popularized its use, called it _natural
semantics_. But there are some things it does not do well. In
particular, it does not give us a natural way of talking about
_concurrent_ programming languages, where the "semantics" of a
program -- i.e., the essence of how it behaves -- is not just
which input states get mapped to which output states, but also
includes the intermediate states that it passes through along the
way, since these states can also be observed by concurrently
executing code.
Another shortcoming of the big-step style is more technical, but
critical in some situations. To see the issue, suppose we wanted
to define a variant of Imp where variables could hold _either_
numbers _or_ lists of numbers (see the [HoareList] chapter for
details). In the syntax of this extended language, it will be
possible to write strange expressions like [2 + nil], and our
semantics for arithmetic expressions will then need to say
something about how such expressions behave. One
possibility (explored in the [HoareList] chapter) is to maintain
the convention that every arithmetic expressions evaluates to some
number by choosing some way of viewing a list as a number -- e.g.,
by specifying that a list should be interpreted as [0] when it
occurs in a context expecting a number. But this is really a bit
of a hack.
A much more natural approach is simply to say that the behavior of
an expression like [2+nil] is _undefined_ -- it doesn't evaluate
to any result at all. And we can easily do this: we just have to
formulate [aeval] and [beval] as [Inductive] propositions rather
than Fixpoints, so that we can make them partial functions instead
of total ones.
However, now we encounter a serious deficiency. In this language,
a command might _fail_ to map a given starting state to any ending
state for two quite different reasons: either because the
execution gets into an infinite loop or because, at some point,
the program tries to do an operation that makes no sense, such as
adding a number to a list, and none of the evaluation rules can be
applied.
These two outcomes -- nontermination vs. getting stuck in an
erroneous configuration -- are quite different. In particular, we
want to allow the first (permitting the possibility of infinite
loops is the price we pay for the convenience of programming with
general looping constructs like [while]) but prevent the
second (which is just wrong), for example by adding some form of
_typechecking_ to the language. Indeed, this will be a major
topic for the rest of the course. As a first step, we need a
different way of presenting the semantics that allows us to
distinguish nontermination from erroneous "stuck states."
So, for lots of reasons, we'd like to have a finer-grained way of
defining and reasoning about program behaviors. This is the topic
of the present chapter. We replace the "big-step" [eval] relation
with a "small-step" relation that specifies, for a given program,
how the "atomic steps" of computation are performed. *)
(* ########################################################### *)
(** * A Toy Language *)
(** To save space in the discussion, let's go back to an
incredibly simple language containing just constants and
addition. (We use single letters -- [C] and [P] -- for the
constructor names, for brevity.) At the end of the chapter, we'll
see how to apply the same techniques to the full Imp language. *)
Inductive tm : Type :=
| C : nat -> tm (* Constant *)
| P : tm -> tm -> tm. (* Plus *)
Tactic Notation "tm_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "C" | Case_aux c "P" ].
(** Here is a standard evaluator for this language, written in the
same (big-step) style as we've been using up to this point. *)
Fixpoint evalF (t : tm) : nat :=
match t with
| C n => n
| P a1 a2 => evalF a1 + evalF a2
end.
(** Now, here is the same evaluator, written in exactly the same
style, but formulated as an inductively defined relation. Again,
we use the notation [t || n] for "[t] evaluates to [n]." *)
(**
-------- (E_Const)
C n || n
t1 || n1
t2 || n2
---------------------- (E_Plus)
P t1 t2 || C (n1 + n2)
*)
Reserved Notation " t '||' n " (at level 50, left associativity).
Inductive eval : tm -> nat -> Prop :=
| E_Const : forall n,
C n || n
| E_Plus : forall t1 t2 n1 n2,
t1 || n1 ->
t2 || n2 ->
P t1 t2 || (n1 + n2)
where " t '||' n " := (eval t n).
Tactic Notation "eval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Const" | Case_aux c "E_Plus" ].
Module SimpleArith1.
(** Now, here is a small-step version. *)
(**
------------------------------- (ST_PlusConstConst)
P (C n1) (C n2) ==> C (n1 + n2)
t1 ==> t1'
-------------------- (ST_Plus1)
P t1 t2 ==> P t1' t2
t2 ==> t2'
--------------------------- (ST_Plus2)
P (C n1) t2 ==> P (C n1) t2'
*)
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall n1 t2 t2',
t2 ==> t2' ->
P (C n1) t2 ==> P (C n1) t2'
where " t '==>' t' " := (step t t').
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_PlusConstConst"
| Case_aux c "ST_Plus1" | Case_aux c "ST_Plus2" ].
(** Things to notice:
- We are defining just a single reduction step, in which
one [P] node is replaced by its value.
- Each step finds the _leftmost_ [P] node that is ready to
go (both of its operands are constants) and rewrites it in
place. The first rule tells how to rewrite this [P] node
itself; the other two rules tell how to find it.
- A term that is just a constant cannot take a step. *)
(** Let's pause and check a couple of examples of reasoning with
the [step] relation... *)
(** If [t1] can take a step to [t1'], then [P t1 t2] steps
to [P t1' t2]: *)
Example test_step_1 :
P
(P (C 0) (C 3))
(P (C 2) (C 4))
==>
P
(C (0 + 3))
(P (C 2) (C 4)).
Proof.
apply ST_Plus1. apply ST_PlusConstConst. Qed.
(** **** Exercise: 1 star (test_step_2) *)
(** Right-hand sides of sums can take a step only when the
left-hand side is finished: if [t2] can take a step to [t2'],
then [P (C n) t2] steps to [P (C n)
t2']: *)
Example test_step_2 :
P
(C 0)
(P
(C 2)
(P (C 0) (C 3)))
==>
P
(C 0)
(P
(C 2)
(C (0 + 3))).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ########################################################### *)
(** * Relations *)
(** We will be using several different step relations, so it is
helpful to generalize a bit and state a few definitions and
theorems about relations in general. (The optional chapter
[Rel.v] develops some of these ideas in a bit more detail; it may
be useful if the treatment here is too dense.) *)
(** A (binary) _relation_ on a set [X] is a family of propositions
parameterized by two elements of [X] -- i.e., a proposition about
pairs of elements of [X]. *)
Definition relation (X: Type) := X->X->Prop.
(** Our main examples of such relations in this chapter will be
the single-step and multi-step reduction relations on terms, [==>]
and [==>*], but there are many other examples -- some that come to
mind are the "equals," "less than," "less than or equal to," and
"is the square of" relations on numbers, and the "prefix of"
relation on lists and strings. *)
(** One simple property of the [==>] relation is that, like the
evaluation relation for our language of Imp programs, it is
_deterministic_.
_Theorem_: For each [t], there is at most one [t'] such that [t]
steps to [t'] ([t ==> t'] is provable). Formally, this is the
same as saying that [==>] is deterministic. *)
(** _Proof sketch_: We show that if [x] steps to both [y1] and [y2]
then [y1] and [y2] are equal, by induction on a derivation of
[step x y1]. There are several cases to consider, depending on
the last rule used in this derivation and in the given derivation
of [step x y2].
- If both are [ST_PlusConstConst], the result is immediate.
- The cases when both derivations end with [ST_Plus1] or
[ST_Plus2] follow by the induction hypothesis.
- It cannot happen that one is [ST_PlusConstConst] and the other
is [ST_Plus1] or [ST_Plus2], since this would imply that [x] has
the form [P t1 t2] where both [t1] and [t2] are
constants (by [ST_PlusConstConst]) _and_ one of [t1] or [t2] has
the form [P ...].
- Similarly, it cannot happen that one is [ST_Plus1] and the other
is [ST_Plus2], since this would imply that [x] has the form
[P t1 t2] where [t1] has both the form [P t1 t2] and
the form [C n]. [] *)
Definition deterministic {X: Type} (R: relation X) :=
forall x y1 y2 : X, R x y1 -> R x y2 -> y1 = y2.
Theorem step_deterministic:
deterministic step.
Proof.
unfold deterministic. intros x y1 y2 Hy1 Hy2.
generalize dependent y2.
step_cases (induction Hy1) Case; intros y2 Hy2.
Case "ST_PlusConstConst". step_cases (inversion Hy2) SCase.
SCase "ST_PlusConstConst". reflexivity.
SCase "ST_Plus1". inversion H2.
SCase "ST_Plus2". inversion H2.
Case "ST_Plus1". step_cases (inversion Hy2) SCase.
SCase "ST_PlusConstConst". rewrite <- H0 in Hy1. inversion Hy1.
SCase "ST_Plus1".
rewrite <- (IHHy1 t1'0).
reflexivity. assumption.
SCase "ST_Plus2". rewrite <- H in Hy1. inversion Hy1.
Case "ST_Plus2". step_cases (inversion Hy2) SCase.
SCase "ST_PlusConstConst". rewrite <- H1 in Hy1. inversion Hy1.
SCase "ST_Plus1". inversion H2.
SCase "ST_Plus2".
rewrite <- (IHHy1 t2'0).
reflexivity. assumption.
Qed.
(** There is some annoying repetition in this proof.
Each use of [inversion Hy2] results in three subcases,
only one of which is relevant (the one which matches the
current case in the induction on [Hy1]). The other two
subcases need to be dismissed by finding the contradiction
among the hypotheses and doing inversion on it.
There is a tactic called [solve by inversion] defined in [SfLib.v]
that can be of use in such cases. It will solve the goal if it
can be solved by inverting some hypothesis; otherwise, it fails.
(There are variants [solve by inversion 2] and [solve by inversion 3]
that work if two or three consecutive inversions will solve the goal.)
The example below shows how a proof of the previous theorem can be
simplified using this tactic.
*)
Theorem step_deterministic_alt: deterministic step.
Proof.
intros x y1 y2 Hy1 Hy2.
generalize dependent y2.
step_cases (induction Hy1) Case; intros y2 Hy2;
inversion Hy2; subst; try (solve by inversion).
Case "ST_PlusConstConst". reflexivity.
Case "ST_Plus1".
apply IHHy1 in H2. rewrite H2. reflexivity.
Case "ST_Plus2".
apply IHHy1 in H2. rewrite H2. reflexivity.
Qed.
End SimpleArith1.
(* ########################################################### *)
(** ** Values *)
(** Let's take a moment to slightly generalize the way we state the
definition of single-step reduction. *)
(** It is useful to think of the [==>] relation as defining an
_abstract machine_:
- At any moment, the _state_ of the machine is a term.
- A _step_ of the machine is an atomic unit of computation --
here, a single "add" operation.
- The _halting states_ of the machine are ones where there is no
more computation to be done.
*)
(**
We can then execute a term [t] as follows:
- Take [t] as the starting state of the machine.
- Repeatedly use the [==>] relation to find a sequence of
machine states, starting with [t], where each state steps to
the next.
- When no more reduction is possible, "read out" the final state
of the machine as the result of execution. *)
(** Intuitively, it is clear that the final states of the
machine are always terms of the form [C n] for some [n].
We call such terms _values_. *)
Inductive value : tm -> Prop :=
v_const : forall n, value (C n).
(** Having introduced the idea of values, we can use it in the
definition of the [==>] relation to write [ST_Plus2] rule in a
slightly more elegant way: *)
(**
------------------------------- (ST_PlusConstConst)
P (C n1) (C n2) ==> C (n1 + n2)
t1 ==> t1'
-------------------- (ST_Plus1)
P t1 t2 ==> P t1' t2
value v1
t2 ==> t2'
-------------------- (ST_Plus2)
P v1 t2 ==> P v1 t2'
*)
(** Again, the variable names here carry important information:
by convention, [v1] ranges only over values, while [t1] and [t2]
range over arbitrary terms. (Given this convention, the explicit
[value] hypothesis is arguably redundant. We'll keep it for now,
to maintain a close correspondence between the informal and Coq
versions of the rules, but later on we'll drop it in informal
rules, for the sake of brevity.) *)
(** Here are the formal rules: *)
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2)
==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 -> (* <----- n.b. *)
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
where " t '==>' t' " := (step t t').
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_PlusConstConst"
| Case_aux c "ST_Plus1" | Case_aux c "ST_Plus2" ].
(** **** Exercise: 3 stars (redo_determinism) *)
(** As a sanity check on this change, let's re-verify determinism
Proof sketch: We must show that if [x] steps to both [y1] and [y2]
then [y1] and [y2] are equal. Consider the final rules used in
the derivations of [step x y1] and [step x y2].
- If both are [ST_PlusConstConst], the result is immediate.
- It cannot happen that one is [ST_PlusConstConst] and the other
is [ST_Plus1] or [ST_Plus2], since this would imply that [x] has
the form [P t1 t2] where both [t1] and [t2] are
constants (by [ST_PlusConstConst]) AND one of [t1] or [t2] has
the form [P ...].
- Similarly, it cannot happen that one is [ST_Plus1] and the other
is [ST_Plus2], since this would imply that [x] has the form
[P t1 t2] where [t1] both has the form [P t1 t2] and
is a value (hence has the form [C n]).
- The cases when both derivations end with [ST_Plus1] or
[ST_Plus2] follow by the induction hypothesis. [] *)
(** Most of this proof is the same as the one above. But to get
maximum benefit from the exercise you should try to write it from
scratch and just use the earlier one if you get stuck. *)
Theorem step_deterministic :
deterministic step.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ########################################################### *)
(** ** Strong Progress and Normal Forms *)
(** The definition of single-step reduction for our toy language is
fairly simple, but for a larger language it would be pretty easy
to forget one of the rules and create a situation where some term
cannot take a step even though it has not been completely reduced
to a value. The following theorem shows that we did not, in fact,
make such a mistake here. *)
(** _Theorem_ (_Strong Progress_): If [t] is a term, then either [t]
is a value, or there exists a term [t'] such that [t ==> t']. *)
(** _Proof_: By induction on [t].
- Suppose [t = C n]. Then [t] is a [value].
- Suppose [t = P t1 t2], where (by the IH) [t1] is either a
value or can step to some [t1'], and where [t2] is either a
value or can step to some [t2']. We must show [P t1 t2] is
either a value or steps to some [t'].
- If [t1] and [t2] are both values, then [t] can take a step, by
[ST_PlusConstConst].
- If [t1] is a value and [t2] can take a step, then so can [t],
by [ST_Plus2].
- If [t1] can take a step, then so can [t], by [ST_Plus1]. [] *)
Theorem strong_progress : forall t,
value t \/ (exists t', t ==> t').
Proof.
tm_cases (induction t) Case.
Case "C". left. apply v_const.
Case "P". right. inversion IHt1.
SCase "l". inversion IHt2.
SSCase "l". inversion H. inversion H0.
exists (C (n + n0)).
apply ST_PlusConstConst.
SSCase "r". inversion H0 as [t' H1].
exists (P t1 t').
apply ST_Plus2. apply H. apply H1.
SCase "r". inversion H as [t' H0].
exists (P t' t2).
apply ST_Plus1. apply H0. Qed.
(** This important property is called _strong progress_, because
every term either is a value or can "make progress" by stepping to
some other term. (The qualifier "strong" distinguishes it from a
more refined version that we'll see in later chapters, called
simply "progress.") *)
(** The idea of "making progress" can be extended to tell us something
interesting about [value]s: in this language [value]s are exactly
the terms that _cannot_ make progress in this sense.
To state this observation formally, let's begin by giving a name
to terms that cannot make progress. We'll call them _normal
forms_. *)
Definition normal_form {X:Type} (R:relation X) (t:X) : Prop :=
~ exists t', R t t'.
(** This definition actually specifies what it is to be a normal form
for an _arbitrary_ relation [R] over an arbitrary set [X], not
just for the particular single-step reduction relation over terms
that we are interested in at the moment. We'll re-use the same
terminology for talking about other relations later in the
course. *)
(** We can use this terminology to generalize the observation we made
in the strong progress theorem: in this language, normal forms and
values are actually the same thing. *)
Lemma value_is_nf : forall v,
value v -> normal_form step v.
Proof.
unfold normal_form. intros v H. inversion H.
intros contra. inversion contra. inversion H1.
Qed.
Lemma nf_is_value : forall t,
normal_form step t -> value t.
Proof. (* a corollary of [strong_progress]... *)
unfold normal_form. intros t H.
assert (G : value t \/ exists t', t ==> t').
SCase "Proof of assertion". apply strong_progress.
inversion G.
SCase "l". apply H0.
SCase "r". apply ex_falso_quodlibet. apply H. assumption. Qed.
Corollary nf_same_as_value : forall t,
normal_form step t <-> value t.
Proof.
split. apply nf_is_value. apply value_is_nf. Qed.
(** Why is this interesting?
Because [value] is a syntactic concept -- it is defined by looking
at the form of a term -- while [normal_form] is a semantic one --
it is defined by looking at how the term steps. It is not obvious
that these concepts should coincide!
Indeed, we could easily have written the definitions so that they
would not coincide... *)
(* ##################################################### *)
(** We might, for example, mistakenly define [value] so that it
includes some terms that are not finished reducing. *)
Module Temp1.
(* Open an inner module so we can redefine value and step. *)
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n)
| v_funny : forall t1 n2, (* <---- *)
value (P t1 (C n2)).
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
where " t '==>' t' " := (step t t').
(** **** Exercise: 3 stars, advanced (value_not_same_as_normal_form) *)
Lemma value_not_same_as_normal_form :
exists v, value v /\ ~ normal_form step v.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End Temp1.
(* ##################################################### *)
(** Alternatively, we might mistakenly define [step] so that it
permits something designated as a value to reduce further. *)
Module Temp2.
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n).
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_Funny : forall n, (* <---- *)
C n ==> P (C n) (C 0)
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
where " t '==>' t' " := (step t t').
(** **** Exercise: 2 stars, advanced (value_not_same_as_normal_form) *)
Lemma value_not_same_as_normal_form :
exists v, value v /\ ~ normal_form step v.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End Temp2.
(* ########################################################### *)
(** Finally, we might define [value] and [step] so that there is some
term that is not a value but that cannot take a step in the [step]
relation. Such terms are said to be _stuck_. In this case this is
caused by a mistake in the semantics, but we will also see
situations where, even in a correct language definition, it makes
sense to allow some terms to be stuck. *)
Module Temp3.
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n).
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
where " t '==>' t' " := (step t t').
(** (Note that [ST_Plus2] is missing.) *)
(** **** Exercise: 3 stars, advanced (value_not_same_as_normal_form') *)
Lemma value_not_same_as_normal_form :
exists t, ~ value t /\ normal_form step t.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End Temp3.
(* ########################################################### *)
(** *** Additional Exercises *)
Module Temp4.
(** Here is another very simple language whose terms, instead of being
just plus and numbers, are just the booleans true and false and a
conditional expression... *)
Inductive tm : Type :=
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm.
Inductive value : tm -> Prop :=
| v_true : value ttrue
| v_false : value tfalse.
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_IfTrue : forall t1 t2,
tif ttrue t1 t2 ==> t1
| ST_IfFalse : forall t1 t2,
tif tfalse t1 t2 ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
tif t1 t2 t3 ==> tif t1' t2 t3
where " t '==>' t' " := (step t t').
(** **** Exercise: 1 star (smallstep_bools) *)
(** Which of the following propositions are provable? (This is just a
thought exercise, but for an extra challenge feel free to prove
your answers in Coq.) *)
Definition bool_step_prop1 :=
tfalse ==> tfalse.
(* FILL IN HERE *)
Definition bool_step_prop2 :=
tif
ttrue
(tif ttrue ttrue ttrue)
(tif tfalse tfalse tfalse)
==>
ttrue.
(* FILL IN HERE *)
Definition bool_step_prop3 :=
tif
(tif ttrue ttrue ttrue)
(tif ttrue ttrue ttrue)
tfalse
==>
tif
ttrue
(tif ttrue ttrue ttrue)
tfalse.
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars, optional (progress_bool) *)
(** Just as we proved a progress theorem for plus expressions, we can
do so for boolean expressions, as well. *)
Theorem strong_progress : forall t,
value t \/ (exists t', t ==> t').
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional (step_deterministic) *)
Theorem step_deterministic :
deterministic step.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
Module Temp5.
(** **** Exercise: 2 stars (smallstep_bool_shortcut) *)
(** Suppose we want to add a "short circuit" to the step relation for
boolean expressions, so that it can recognize when the [then] and
[else] branches of a conditional are the same value (either
[ttrue] or [tfalse]) and reduce the whole conditional to this
value in a single step, even if the guard has not yet been reduced
to a value. For example, we would like this proposition to be
provable:
tif
(tif ttrue ttrue ttrue)
tfalse
tfalse
==>
tfalse.
*)
(** Write an extra clause for the step relation that achieves this
effect and prove [bool_step_prop4]. *)
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_IfTrue : forall t1 t2,
tif ttrue t1 t2 ==> t1
| ST_IfFalse : forall t1 t2,
tif tfalse t1 t2 ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
tif t1 t2 t3 ==> tif t1' t2 t3
(* FILL IN HERE *)
where " t '==>' t' " := (step t t').
Definition bool_step_prop4 :=
tif
(tif ttrue ttrue ttrue)
tfalse
tfalse
==>
tfalse.
Example bool_step_prop4_holds :
bool_step_prop4.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional (properties_of_altered_step) *)
(** It can be shown that the determinism and strong progress theorems
for the step relation in the lecture notes also hold for the
definition of step given above. After we add the clause
[ST_ShortCircuit]...
- Is the [step] relation still deterministic? Write yes or no and
briefly (1 sentence) explain your answer.
Optional: prove your answer correct in Coq.
*)
(* FILL IN HERE *)
(**
- Does a strong progress theorem hold? Write yes or no and
briefly (1 sentence) explain your answer.
Optional: prove your answer correct in Coq.
*)
(* FILL IN HERE *)
(**
- In general, is there any way we could cause strong progress to
fail if we took away one or more constructors from the original
step relation? Write yes or no and briefly (1 sentence) explain
your answer.
(* FILL IN HERE *)
*)
(** [] *)
End Temp5.
End Temp4.
(* ########################################################### *)
(** * Multi-Step Reduction *)
(** Until now, we've been working with the _single-step reduction_
relation [==>], which formalizes the individual steps of an
_abstract machine_ for executing programs.
We can also use this machine to reduce programs to completion --
to find out what final result they yield. This can be formalized
as follows:
- First, we define a _multi-step reduction relation_ [==>*], which
relates terms [t] and [t'] if [t] can reach [t'] by any number
of single reduction steps (including zero steps!).
- Then we define a "result" of a term [t] as a normal form that
[t] can reach by multi-step reduction. *)
(* ########################################################### *)
(** Since we'll want to reuse the idea of multi-step reduction many
times in this and future chapters, let's take a little extra
trouble here and define it generically.
Given a relation [R], we define a relation [multi R], called the
_multi-step closure of [R]_ as follows: *)
Inductive multi {X:Type} (R: relation X) : relation X :=
| multi_refl : forall (x : X), multi R x x
| multi_step : forall (x y z : X),
R x y ->
multi R y z ->
multi R x z.
(** The effect of this definition is that [multi R] relates two
elements [x] and [y] if either
- [x = y], or else
- there is some sequence [z1], [z2], ..., [zn]
such that
R x z1
R z1 z2
...
R zn y.
Thus, if [R] describes a single-step of computation, [z1],
... [zn] is the sequence of intermediate steps of computation
between [x] and [y].
*)
Tactic Notation "multi_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "multi_refl" | Case_aux c "multi_step" ].
(** We write [==>*] for the [multi step] relation -- i.e., the
relation that relates two terms [t] and [t'] if we can get from
[t] to [t'] using the [step] relation zero or more times. *)
Notation " t '==>*' t' " := (multi step t t') (at level 40).
(** The relation [multi R] has several crucial properties.
First, it is obviously _reflexive_ (that is, [forall x, multi R x
x]). In the case of the [==>*] (i.e. [multi step]) relation, the
intuition is that a term can execute to itself by taking zero
steps of execution.
Second, it contains [R] -- that is, single-step executions are a
particular case of multi-step executions. (It is this fact that
justifies the word "closure" in the term "multi-step closure of
[R].") *)
Theorem multi_R : forall (X:Type) (R:relation X) (x y : X),
R x y -> (multi R) x y.
Proof.
intros X R x y H.
apply multi_step with y. apply H. apply multi_refl. Qed.
(** Third, [multi R] is _transitive_. *)
Theorem multi_trans :
forall (X:Type) (R: relation X) (x y z : X),
multi R x y ->
multi R y z ->
multi R x z.
Proof.
intros X R x y z G H.
multi_cases (induction G) Case.
Case "multi_refl". assumption.
Case "multi_step".
apply multi_step with y. assumption.
apply IHG. assumption. Qed.
(** That is, if [t1==>*t2] and [t2==>*t3], then [t1==>*t3]. *)
(* ########################################################### *)
(** ** Examples *)
Lemma test_multistep_1:
P
(P (C 0) (C 3))
(P (C 2) (C 4))
==>*
C ((0 + 3) + (2 + 4)).
Proof.
apply multi_step with
(P
(C (0 + 3))
(P (C 2) (C 4))).
apply ST_Plus1. apply ST_PlusConstConst.
apply multi_step with
(P
(C (0 + 3))
(C (2 + 4))).
apply ST_Plus2. apply v_const.
apply ST_PlusConstConst.
apply multi_R.
apply ST_PlusConstConst. Qed.
(** Here's an alternate proof that uses [eapply] to avoid explicitly
constructing all the intermediate terms. *)
Lemma test_multistep_1':
P
(P (C 0) (C 3))
(P (C 2) (C 4))
==>*
C ((0 + 3) + (2 + 4)).
Proof.
eapply multi_step. apply ST_Plus1. apply ST_PlusConstConst.
eapply multi_step. apply ST_Plus2. apply v_const.
apply ST_PlusConstConst.
eapply multi_step. apply ST_PlusConstConst.
apply multi_refl. Qed.
(** **** Exercise: 1 star, optional (test_multistep_2) *)
Lemma test_multistep_2:
C 3 ==>* C 3.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star, optional (test_multistep_3) *)
Lemma test_multistep_3:
P (C 0) (C 3)
==>*
P (C 0) (C 3).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars (test_multistep_4) *)
Lemma test_multistep_4:
P
(C 0)
(P
(C 2)
(P (C 0) (C 3)))
==>*
P
(C 0)
(C (2 + (0 + 3))).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ########################################################### *)
(** ** Normal Forms Again *)
(** If [t] reduces to [t'] in zero or more steps and [t'] is a
normal form, we say that "[t'] is a normal form of [t]." *)
Definition step_normal_form := normal_form step.
Definition normal_form_of (t t' : tm) :=
(t ==>* t' /\ step_normal_form t').
(** We have already seen that, for our language, single-step reduction is
deterministic -- i.e., a given term can take a single step in
at most one way. It follows from this that, if [t] can reach
a normal form, then this normal form is unique. In other words, we
can actually pronounce [normal_form t t'] as "[t'] is _the_
normal form of [t]." *)
(** **** Exercise: 3 stars, optional (normal_forms_unique) *)
Theorem normal_forms_unique:
deterministic normal_form_of.
Proof.
unfold deterministic. unfold normal_form_of. intros x y1 y2 P1 P2.
inversion P1 as [P11 P12]; clear P1. inversion P2 as [P21 P22]; clear P2.
generalize dependent y2.
(* We recommend using this initial setup as-is! *)
(* FILL IN HERE *) Admitted.
(** [] *)
(** Indeed, something stronger is true for this language (though not
for all languages): the reduction of _any_ term [t] will
eventually reach a normal form -- i.e., [normal_form_of] is a
_total_ function. Formally, we say the [step] relation is
_normalizing_. *)
Definition normalizing {X:Type} (R:relation X) :=
forall t, exists t',
(multi R) t t' /\ normal_form R t'.
(** To prove that [step] is normalizing, we need a couple of lemmas.
First, we observe that, if [t] reduces to [t'] in many steps, then
the same sequence of reduction steps within [t] is also possible
when [t] appears as the left-hand child of a [P] node, and
similarly when [t] appears as the right-hand child of a [P]
node whose left-hand child is a value. *)
Lemma multistep_congr_1 : forall t1 t1' t2,
t1 ==>* t1' ->
P t1 t2 ==>* P t1' t2.
Proof.
intros t1 t1' t2 H. multi_cases (induction H) Case.
Case "multi_refl". apply multi_refl.
Case "multi_step". apply multi_step with (P y t2).
apply ST_Plus1. apply H.
apply IHmulti. Qed.
(** **** Exercise: 2 stars (multistep_congr_2) *)
Lemma multistep_congr_2 : forall t1 t2 t2',
value t1 ->
t2 ==>* t2' ->
P t1 t2 ==>* P t1 t2'.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** _Theorem_: The [step] function is normalizing -- i.e., for every
[t] there exists some [t'] such that [t] steps to [t'] and [t'] is
a normal form.
_Proof sketch_: By induction on terms. There are two cases to
consider:
- [t = C n] for some [n]. Here [t] doesn't take a step,
and we have [t' = t]. We can derive the left-hand side by
reflexivity and the right-hand side by observing (a) that values
are normal forms (by [nf_same_as_value]) and (b) that [t] is a
value (by [v_const]).
- [t = P t1 t2] for some [t1] and [t2]. By the IH, [t1] and
[t2] have normal forms [t1'] and [t2']. Recall that normal
forms are values (by [nf_same_as_value]); we know that [t1' =
C n1] and [t2' = C n2], for some [n1] and [n2].
We can combine the [==>*] derivations for [t1] and [t2] to prove
that [P t1 t2] reduces in many steps to [C (n1 + n2)].
It is clear that our choice of [t' = C (n1 + n2)] is a
value, which is in turn a normal form. [] *)
Theorem step_normalizing :
normalizing step.
Proof.
unfold normalizing.
tm_cases (induction t) Case.
Case "C".
exists (C n).
split.
SCase "l". apply multi_refl.
SCase "r".
(* We can use [rewrite] with "iff" statements, not
just equalities: *)
rewrite nf_same_as_value. apply v_const.
Case "P".
inversion IHt1 as [t1' H1]; clear IHt1. inversion IHt2 as [t2' H2]; clear IHt2.
inversion H1 as [H11 H12]; clear H1. inversion H2 as [H21 H22]; clear H2.
rewrite nf_same_as_value in H12. rewrite nf_same_as_value in H22.
inversion H12 as [n1]. inversion H22 as [n2].
rewrite <- H in H11.
rewrite <- H0 in H21.
exists (C (n1 + n2)).
split.
SCase "l".
apply multi_trans with (P (C n1) t2).
apply multistep_congr_1. apply H11.
apply multi_trans with
(P (C n1) (C n2)).
apply multistep_congr_2. apply v_const. apply H21.
apply multi_R. apply ST_PlusConstConst.
SCase "r".
rewrite nf_same_as_value. apply v_const. Qed.
(* ########################################################### *)
(** ** Equivalence of Big-Step and Small-Step Reduction *)
(** Having defined the operational semantics of our tiny programming
language in two different styles, it makes sense to ask whether
these definitions actually define the same thing! They do, though
it takes a little work to show it. (The details are left as an
exercise). *)
(** **** Exercise: 3 stars (eval__multistep) *)
Theorem eval__multistep : forall t n,
t || n -> t ==>* C n.
(** The key idea behind the proof comes from the following picture:
P t1 t2 ==> (by ST_Plus1)
P t1' t2 ==> (by ST_Plus1)
P t1'' t2 ==> (by ST_Plus1)
...
P (C n1) t2 ==> (by ST_Plus2)
P (C n1) t2' ==> (by ST_Plus2)
P (C n1) t2'' ==> (by ST_Plus2)
...
P (C n1) (C n2) ==> (by ST_PlusConstConst)
C (n1 + n2)
That is, the multistep reduction of a term of the form [P t1 t2]
proceeds in three phases:
- First, we use [ST_Plus1] some number of times to reduce [t1]
to a normal form, which must (by [nf_same_as_value]) be a
term of the form [C n1] for some [n1].
- Next, we use [ST_Plus2] some number of times to reduce [t2]
to a normal form, which must again be a term of the form [C
n2] for some [n2].
- Finally, we use [ST_PlusConstConst] one time to reduce [P (C
n1) (C n2)] to [C (n1 + n2)]. *)
(** To formalize this intuition, you'll need to use the congruence
lemmas from above (you might want to review them now, so that
you'll be able to recognize when they are useful), plus some basic
properties of [==>*]: that it is reflexive, transitive, and
includes [==>]. *)
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced (eval__multistep_inf) *)
(** Write a detailed informal version of the proof of [eval__multistep].
(* FILL IN HERE *)
[]
*)
(** For the other direction, we need one lemma, which establishes a
relation between single-step reduction and big-step evaluation. *)
(** **** Exercise: 3 stars (step__eval) *)
Lemma step__eval : forall t t' n,
t ==> t' ->
t' || n ->
t || n.
Proof.
intros t t' n Hs. generalize dependent n.
(* FILL IN HERE *) Admitted.
(** [] *)
(** The fact that small-step reduction implies big-step is now
straightforward to prove, once it is stated correctly.
The proof proceeds by induction on the multi-step reduction
sequence that is buried in the hypothesis [normal_form_of t t']. *)
(** Make sure you understand the statement before you start to
work on the proof. *)
(** **** Exercise: 3 stars (multistep__eval) *)
Theorem multistep__eval : forall t t',
normal_form_of t t' -> exists n, t' = C n /\ t || n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ########################################################### *)
(** ** Additional Exercises *)
(** **** Exercise: 3 stars, optional (interp_tm) *)
(** Remember that we also defined big-step evaluation of [tm]s as a
function [evalF]. Prove that it is equivalent to the existing
semantics.
Hint: we just proved that [eval] and [multistep] are
equivalent, so logically it doesn't matter which you choose.
One will be easier than the other, though! *)
Theorem evalF_eval : forall t n,
evalF t = n <-> t || n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars (combined_properties) *)
(** We've considered the arithmetic and conditional expressions
separately. This exercise explores how the two interact. *)
Module Combined.
Inductive tm : Type :=
| C : nat -> tm
| P : tm -> tm -> tm
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm.
Tactic Notation "tm_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "C" | Case_aux c "P"
| Case_aux c "ttrue" | Case_aux c "tfalse" | Case_aux c "tif" ].
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n)
| v_true : value ttrue
| v_false : value tfalse.
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
| ST_IfTrue : forall t1 t2,
tif ttrue t1 t2 ==> t1
| ST_IfFalse : forall t1 t2,
tif tfalse t1 t2 ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
tif t1 t2 t3 ==> tif t1' t2 t3
where " t '==>' t' " := (step t t').
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_PlusConstConst"
| Case_aux c "ST_Plus1" | Case_aux c "ST_Plus2"
| Case_aux c "ST_IfTrue" | Case_aux c "ST_IfFalse" | Case_aux c "ST_If" ].
(** Earlier, we separately proved for both plus- and if-expressions...
- that the step relation was deterministic, and
- a strong progress lemma, stating that every term is either a
value or can take a step.
Prove or disprove these two properties for the combined language. *)
(* FILL IN HERE *)
(** [] *)
End Combined.
(* ########################################################### *)
(** * Small-Step Imp *)
(** For a more serious example, here is the small-step version of the
Imp operational semantics. *)
(** The small-step evaluation relations for arithmetic and boolean
expressions are straightforward extensions of the tiny language
we've been working up to now. To make them easier to read, we
introduce the symbolic notations [==>a] and [==>b], respectively,
for the arithmetic and boolean step relations. *)
Inductive aval : aexp -> Prop :=
av_num : forall n, aval (ANum n).
(** We are not actually going to bother to define boolean
values, since they aren't needed in the definition of [==>b]
below (why?), though they might be if our language were a bit
larger (why?). *)
Reserved Notation " t '/' st '==>a' t' " (at level 40, st at level 39).
Inductive astep : state -> aexp -> aexp -> Prop :=
| AS_Id : forall st i,
AId i / st ==>a ANum (st i)
| AS_Plus : forall st n1 n2,
APlus (ANum n1) (ANum n2) / st ==>a ANum (n1 + n2)
| AS_Plus1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(APlus a1 a2) / st ==>a (APlus a1' a2)
| AS_Plus2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(APlus v1 a2) / st ==>a (APlus v1 a2')
| AS_Minus : forall st n1 n2,
(AMinus (ANum n1) (ANum n2)) / st ==>a (ANum (minus n1 n2))
| AS_Minus1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(AMinus a1 a2) / st ==>a (AMinus a1' a2)
| AS_Minus2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(AMinus v1 a2) / st ==>a (AMinus v1 a2')
| AS_Mult : forall st n1 n2,
(AMult (ANum n1) (ANum n2)) / st ==>a (ANum (mult n1 n2))
| AS_Mult1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(AMult (a1) (a2)) / st ==>a (AMult (a1') (a2))
| AS_Mult2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(AMult v1 a2) / st ==>a (AMult v1 a2')
where " t '/' st '==>a' t' " := (astep st t t').
Reserved Notation " t '/' st '==>b' t' " (at level 40, st at level 39).
Inductive bstep : state -> bexp -> bexp -> Prop :=
| BS_Eq : forall st n1 n2,
(BEq (ANum n1) (ANum n2)) / st ==>b
(if (beq_nat n1 n2) then BTrue else BFalse)
| BS_Eq1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(BEq a1 a2) / st ==>b (BEq a1' a2)
| BS_Eq2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(BEq v1 a2) / st ==>b (BEq v1 a2')
| BS_LtEq : forall st n1 n2,
(BLe (ANum n1) (ANum n2)) / st ==>b
(if (ble_nat n1 n2) then BTrue else BFalse)
| BS_LtEq1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(BLe a1 a2) / st ==>b (BLe a1' a2)
| BS_LtEq2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(BLe v1 a2) / st ==>b (BLe v1 (a2'))
| BS_NotTrue : forall st,
(BNot BTrue) / st ==>b BFalse
| BS_NotFalse : forall st,
(BNot BFalse) / st ==>b BTrue
| BS_NotStep : forall st b1 b1',
b1 / st ==>b b1' ->
(BNot b1) / st ==>b (BNot b1')
| BS_AndTrueTrue : forall st,
(BAnd BTrue BTrue) / st ==>b BTrue
| BS_AndTrueFalse : forall st,
(BAnd BTrue BFalse) / st ==>b BFalse
| BS_AndFalse : forall st b2,
(BAnd BFalse b2) / st ==>b BFalse
| BS_AndTrueStep : forall st b2 b2',
b2 / st ==>b b2' ->
(BAnd BTrue b2) / st ==>b (BAnd BTrue b2')
| BS_AndStep : forall st b1 b1' b2,
b1 / st ==>b b1' ->
(BAnd b1 b2) / st ==>b (BAnd b1' b2)
where " t '/' st '==>b' t' " := (bstep st t t').
(** The semantics of commands is the interesting part. We need two
small tricks to make it work:
- We use [SKIP] as a "command value" -- i.e., a command that
has reached a normal form.
- An assignment command reduces to [SKIP] (and an updated
state).
- The sequencing command waits until its left-hand
subcommand has reduced to [SKIP], then throws it away so
that reduction can continue with the right-hand
subcommand.
- We reduce a [WHILE] command by transforming it into a
conditional followed by the same [WHILE]. *)
(** (There are other ways of achieving the effect of the latter
trick, but they all share the feature that the original [WHILE]
command needs to be saved somewhere while a single copy of the loop
body is being evaluated.) *)
Reserved Notation " t '/' st '==>' t' '/' st' "
(at level 40, st at level 39, t' at level 39).
Inductive cstep : (com * state) -> (com * state) -> Prop :=
| CS_AssStep : forall st i a a',
a / st ==>a a' ->
(i ::= a) / st ==> (i ::= a') / st
| CS_Ass : forall st i n,
(i ::= (ANum n)) / st ==> SKIP / (update st i n)
| CS_SeqStep : forall st c1 c1' st' c2,
c1 / st ==> c1' / st' ->
(c1 ;; c2) / st ==> (c1' ;; c2) / st'
| CS_SeqFinish : forall st c2,
(SKIP ;; c2) / st ==> c2 / st
| CS_IfTrue : forall st c1 c2,
IFB BTrue THEN c1 ELSE c2 FI / st ==> c1 / st
| CS_IfFalse : forall st c1 c2,
IFB BFalse THEN c1 ELSE c2 FI / st ==> c2 / st
| CS_IfStep : forall st b b' c1 c2,
b / st ==>b b' ->
IFB b THEN c1 ELSE c2 FI / st ==> (IFB b' THEN c1 ELSE c2 FI) / st
| CS_While : forall st b c1,
(WHILE b DO c1 END) / st
==> (IFB b THEN (c1;; (WHILE b DO c1 END)) ELSE SKIP FI) / st
where " t '/' st '==>' t' '/' st' " := (cstep (t,st) (t',st')).
(* ########################################################### *)
(** * Concurrent Imp *)
(** Finally, to show the power of this definitional style, let's
enrich Imp with a new form of command that runs two subcommands in
parallel and terminates when both have terminated. To reflect the
unpredictability of scheduling, the actions of the subcommands may
be interleaved in any order, but they share the same memory and
can communicate by reading and writing the same variables. *)
Module CImp.
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
(* New: *)
| CPar : com -> com -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE" | Case_aux c "PAR" ].
Notation "'SKIP'" :=
CSkip.
Notation "x '::=' a" :=
(CAss x a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' b 'THEN' c1 'ELSE' c2 'FI'" :=
(CIf b c1 c2) (at level 80, right associativity).
Notation "'PAR' c1 'WITH' c2 'END'" :=
(CPar c1 c2) (at level 80, right associativity).
Inductive cstep : (com * state) -> (com * state) -> Prop :=
(* Old part *)
| CS_AssStep : forall st i a a',
a / st ==>a a' ->
(i ::= a) / st ==> (i ::= a') / st
| CS_Ass : forall st i n,
(i ::= (ANum n)) / st ==> SKIP / (update st i n)
| CS_SeqStep : forall st c1 c1' st' c2,
c1 / st ==> c1' / st' ->
(c1 ;; c2) / st ==> (c1' ;; c2) / st'
| CS_SeqFinish : forall st c2,
(SKIP ;; c2) / st ==> c2 / st
| CS_IfTrue : forall st c1 c2,
(IFB BTrue THEN c1 ELSE c2 FI) / st ==> c1 / st
| CS_IfFalse : forall st c1 c2,
(IFB BFalse THEN c1 ELSE c2 FI) / st ==> c2 / st
| CS_IfStep : forall st b b' c1 c2,
b /st ==>b b' ->
(IFB b THEN c1 ELSE c2 FI) / st ==> (IFB b' THEN c1 ELSE c2 FI) / st
| CS_While : forall st b c1,
(WHILE b DO c1 END) / st ==>
(IFB b THEN (c1;; (WHILE b DO c1 END)) ELSE SKIP FI) / st
(* New part: *)
| CS_Par1 : forall st c1 c1' c2 st',
c1 / st ==> c1' / st' ->
(PAR c1 WITH c2 END) / st ==> (PAR c1' WITH c2 END) / st'
| CS_Par2 : forall st c1 c2 c2' st',
c2 / st ==> c2' / st' ->
(PAR c1 WITH c2 END) / st ==> (PAR c1 WITH c2' END) / st'
| CS_ParDone : forall st,
(PAR SKIP WITH SKIP END) / st ==> SKIP / st
where " t '/' st '==>' t' '/' st' " := (cstep (t,st) (t',st')).
Definition cmultistep := multi cstep.
Notation " t '/' st '==>*' t' '/' st' " :=
(multi cstep (t,st) (t',st'))
(at level 40, st at level 39, t' at level 39).
(** Among the many interesting properties of this language is the fact
that the following program can terminate with the variable [X] set
to any value... *)
Definition par_loop : com :=
PAR
Y ::= ANum 1
WITH
WHILE BEq (AId Y) (ANum 0) DO
X ::= APlus (AId X) (ANum 1)
END
END.
(** In particular, it can terminate with [X] set to [0]: *)
Example par_loop_example_0:
exists st',
par_loop / empty_state ==>* SKIP / st'
/\ st' X = 0.
Proof.
eapply ex_intro. split.
unfold par_loop.
eapply multi_step. apply CS_Par1.
apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfFalse.
eapply multi_step. apply CS_ParDone.
eapply multi_refl.
reflexivity. Qed.
(** It can also terminate with [X] set to [2]: *)
Example par_loop_example_2:
exists st',
par_loop / empty_state ==>* SKIP / st'
/\ st' X = 2.
Proof.
eapply ex_intro. split.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfTrue.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_SeqFinish.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfTrue.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_Ass.
eapply multi_step. apply CS_Par1. apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_SeqFinish.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfFalse.
eapply multi_step. apply CS_ParDone.
eapply multi_refl.
reflexivity. Qed.
(** More generally... *)
(** **** Exercise: 3 stars, optional *)
Lemma par_body_n__Sn : forall n st,
st X = n /\ st Y = 0 ->
par_loop / st ==>* par_loop / (update st X (S n)).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional *)
Lemma par_body_n : forall n st,
st X = 0 /\ st Y = 0 ->
exists st',
par_loop / st ==>* par_loop / st' /\ st' X = n /\ st' Y = 0.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** ... the above loop can exit with [X] having any value
whatsoever. *)
Theorem par_loop_any_X:
forall n, exists st',
par_loop / empty_state ==>* SKIP / st'
/\ st' X = n.
Proof.
intros n.
destruct (par_body_n n empty_state).
split; unfold update; reflexivity.
rename x into st.
inversion H as [H' [HX HY]]; clear H.
exists (update st Y 1). split.
eapply multi_trans with (par_loop,st). apply H'.
eapply multi_step. apply CS_Par1. apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id. rewrite update_eq.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfFalse.
eapply multi_step. apply CS_ParDone.
apply multi_refl.
rewrite update_neq. assumption. intro X; inversion X.
Qed.
End CImp.
(* ########################################################### *)
(** * A Small-Step Stack Machine *)
(** Last example: a small-step semantics for the stack machine example
from Imp.v. *)
Definition stack := list nat.
Definition prog := list sinstr.
Inductive stack_step : state -> prog * stack -> prog * stack -> Prop :=
| SS_Push : forall st stk n p',
stack_step st (SPush n :: p', stk) (p', n :: stk)
| SS_Load : forall st stk i p',
stack_step st (SLoad i :: p', stk) (p', st i :: stk)
| SS_Plus : forall st stk n m p',
stack_step st (SPlus :: p', n::m::stk) (p', (m+n)::stk)
| SS_Minus : forall st stk n m p',
stack_step st (SMinus :: p', n::m::stk) (p', (m-n)::stk)
| SS_Mult : forall st stk n m p',
stack_step st (SMult :: p', n::m::stk) (p', (m*n)::stk).
Theorem stack_step_deterministic : forall st,
deterministic (stack_step st).
Proof.
unfold deterministic. intros st x y1 y2 H1 H2.
induction H1; inversion H2; reflexivity.
Qed.
Definition stack_multistep st := multi (stack_step st).
(** **** Exercise: 3 stars, advanced (compiler_is_correct) *)
(** Remember the definition of [compile] for [aexp] given in the
[Imp] chapter. We want now to prove [compile] correct with respect
to the stack machine.
State what it means for the compiler to be correct according to
the stack machine small step semantics and then prove it. *)
Definition compiler_is_correct_statement : Prop :=
(* FILL IN HERE *) admit.
Theorem compiler_is_correct : compiler_is_correct_statement.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** $Date: 2014-12-31 15:16:58 -0500 (Wed, 31 Dec 2014) $ *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__BUFBUF_TB_V
`define SKY130_FD_SC_HD__BUFBUF_TB_V
/**
* bufbuf: Double buffer.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__bufbuf.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hd__bufbuf dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__BUFBUF_TB_V
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_sysid_qsys_0 (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1481594924 : 305419896;
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 13 12:44:09 2017
// Host : WK117 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_rst_mig_7series_0_83M_0/system_rst_mig_7series_0_83M_0_stub.v
// Design : system_rst_mig_7series_0_83M_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35ticsg324-1L
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "proc_sys_reset,Vivado 2016.4" *)
module system_rst_mig_7series_0_83M_0(slowest_sync_clk, ext_reset_in, aux_reset_in,
mb_debug_sys_rst, dcm_locked, mb_reset, bus_struct_reset, peripheral_reset,
interconnect_aresetn, peripheral_aresetn)
/* synthesis syn_black_box black_box_pad_pin="slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]" */;
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
output [0:0]bus_struct_reset;
output [0:0]peripheral_reset;
output [0:0]interconnect_aresetn;
output [0:0]peripheral_aresetn;
endmodule
|
//----------------------------------------------------------------------------
//-- Ejemplo de uso del transmisor serie
//-- Envio de la cadena "Hola!..." cada segundo
//----------------------------------------------------------------------------
//-- (C) BQ. September 2015. Written by Juan Gonzalez (Obijuan)
//-- GPL license
//----------------------------------------------------------------------------
//-- Comprobado su funcionamiento a todas las velocidades estandares:
//-- 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200
//----------------------------------------------------------------------------
`include "baudgen.vh"
`include "divider.vh"
//-- Modulo para envio de una cadena por el puerto serie
module scicad2 (input wire clk, //-- Reloj del sistema
output wire tx //-- Salida de datos serie
);
//-- Velocidad a la que hacer las pruebas
parameter BAUD = `B115200;
//- Tiempo de envio
parameter DELAY = `T_1s;
//-- Reset
reg rstn = 0;
//-- Señal de listo del transmisor serie
wire ready;
//-- Dato a transmitir (normal y registrado)
reg [7:0] data;
reg [7:0] data_r;
//-- Señal para indicar al controlador el comienzo de la transmision
//-- de la cadena
reg transmit_r;
wire transmit;
//-- Microordenes
reg cena; //-- Counter enable (cuando cena = 1)
reg start; //-- Transmitir cadena (cuando transmit = 1)
//------------------------------------------------
//-- RUTA DE DATOS
//------------------------------------------------
//-- Inicializador
always @(posedge clk)
rstn <= 1;
//-- Instanciar la Unidad de transmision
uart_tx #(.BAUD(BAUD))
TX0 (
.clk(clk),
.rstn(rstn),
.data(data_r),
.start(start),
.ready(ready),
.tx(tx)
);
//-- Multiplexor con los caracteres de la cadena a transmitir
//-- se seleccionan mediante la señal car_count
always @*
case (car_count)
8'd0: data <= "H";
8'd1: data <= "o";
8'd2: data <= "l";
8'd3: data <= "a";
8'd4: data <= "!";
8'd5: data <= ".";
8'd6: data <= ".";
8'd7: data <= ".";
default: data <= ".";
endcase
//-- Registrar los datos de salida del multiplexor
always @*
data_r <= data;
//-- Contador de caracteres
//-- Cuando la microorden cena esta activada, se incrementa
reg [2:0] car_count;
always @(posedge clk)
if (rstn == 0)
car_count = 0;
else if (cena)
car_count = car_count + 1;
//-- Registrar señal dtr para cumplir con normas diseño sincrono
always @(posedge clk)
transmit_r <= transmit;
//---------------------------
//-- Temporizador
//---------------------------
dividerp1 #(.M(DELAY))
DIV0 ( .clk(clk),
.clk_out(transmit)
);
//----------------------------------------------------
//-- CONTROLADOR
//----------------------------------------------------
localparam IDLE = 0; //-- Reposo
localparam TXCAR = 2'd1; //-- Transmitiendo caracter
localparam NEXT = 2'd2; //-- Preparar transmision del sig caracter
localparam END = 3; //-- Terminar
//-- Registro de estado del automata
reg [1:0] state;
//-- Gestionar el cambio de estado
always @(posedge clk)
if (rstn == 0)
//-- Ir al estado inicial
state <= IDLE;
else
case (state)
//-- Estado inicial. Se sale de este estado al recibirse la
//-- señal de transmit_r, conectada al temporizador de 1s
IDLE:
if (transmit_r == 1) state <= TXCAR;
else state <= IDLE;
//-- Estado de transmision de un caracter. Esperar a que el
//-- transmisor serie este disponible. Cuando lo esta se pasa al
//-- siguiente estado
TXCAR:
if (ready == 1) state <= NEXT;
else state <= TXCAR;
//-- Envio del siguiente caracter. Es un estado transitorio
//-- Cuando se llega al ultimo caracter se pasa para finalizar
//-- la transmision
NEXT:
if (car_count == 7) state <= END;
else state <= TXCAR;
//-- Ultimo estado:finalizacion de la transmision. Se espera hasta
//-- que se haya enviado el ultimo caracter. Cuando ocurre se vuelve
//-- al estado de reposo inicial
END:
//--Esperar a que se termine ultimo caracter
if (ready == 1) state <= IDLE;
else state <= END;
//-- Necesario para evitar latches
default:
state <= IDLE;
endcase
//-- Generacion de las microordenes
always @*
case (state)
IDLE: begin
start <= 0;
cena <= 0;
end
TXCAR: begin
start <= 1;
cena <= 0;
end
NEXT: begin
start <= 0;
cena <= 1;
end
END: begin
start <= 0;
cena <= 0;
end
default: begin
start <= 0;
cena <= 0;
end
endcase
endmodule
|
// ============================================================================
// COPYRIGHT NOTICE
// Copyright 2006 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised by
// a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement from
// Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court 408-826-6000 (other locations)
// Hillsboro, OR 97124 web : http://www.latticesemi.com/
// U.S.A email: [email protected]
// ============================================================================/
// FILE DETAILS
// Project : LatticeMico32
// File : jtag_cores.v
// Title : Instantiates all IP cores on JTAG chain.
// Dependencies : system_conf.v
// Version : 6.0.14
// : modified to use jtagconn for LM32,
// : all technologies 7/10/07
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : No Change
// ============================================================================
`include "system_conf.v"
/////////////////////////////////////////////////////
// jtagconn16 Module Definition
/////////////////////////////////////////////////////
module jtagconn16 (er2_tdo, jtck, jtdi, jshift, jupdate, jrstn, jce2, ip_enable) ;
input er2_tdo ;
output jtck ;
output jtdi ;
output jshift ;
output jupdate ;
output jrstn ;
output jce2 ;
output ip_enable ;
endmodule
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
(* syn_hier="hard" *) module jtag_cores (
// ----- Inputs -------
reg_d,
reg_addr_d,
// ----- Outputs -------
reg_update,
reg_q,
reg_addr_q,
jtck,
jrstn
);
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input [7:0] reg_d;
input [2:0] reg_addr_d;
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
output reg_update;
wire reg_update;
output [7:0] reg_q;
wire [7:0] reg_q;
output [2:0] reg_addr_q;
wire [2:0] reg_addr_q;
output jtck;
wire jtck; /* synthesis syn_keep=1 */
output jrstn;
wire jrstn; /* synthesis syn_keep=1 */
/////////////////////////////////////////////////////
// Instantiations
/////////////////////////////////////////////////////
wire jtdi; /* synthesis syn_keep=1 */
wire er2_tdo2; /* synthesis syn_keep=1 */
wire jshift; /* synthesis syn_keep=1 */
wire jupdate; /* synthesis syn_keep=1 */
wire jce2; /* synthesis syn_keep=1 */
wire ip_enable; /* synthesis syn_keep=1 */
(* JTAG_IP="LM32", IP_ID="0", HUB_ID="0", syn_noprune=1 *) jtagconn16 jtagconn16_lm32_inst (
.er2_tdo (er2_tdo2),
.jtck (jtck),
.jtdi (jtdi),
.jshift (jshift),
.jupdate (jupdate),
.jrstn (jrstn),
.jce2 (jce2),
.ip_enable (ip_enable)
);
(* syn_noprune=1 *) jtag_lm32 jtag_lm32_inst (
.JTCK (jtck),
.JTDI (jtdi),
.JTDO2 (er2_tdo2),
.JSHIFT (jshift),
.JUPDATE (jupdate),
.JRSTN (jrstn),
.JCE2 (jce2),
.JTAGREG_ENABLE (ip_enable),
.CONTROL_DATAN (),
.REG_UPDATE (reg_update),
.REG_D (reg_d),
.REG_ADDR_D (reg_addr_d),
.REG_Q (reg_q),
.REG_ADDR_Q (reg_addr_q)
);
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: cam_fifo.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 16.1.0 Build 196 10/24/2016 SJ Lite Edition
// ************************************************************
//Copyright (C) 2016 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module cam_fifo (
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdusedw);
input [15:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [15:0] q;
output [8:0] rdusedw;
wire [15:0] sub_wire0;
wire [8:0] sub_wire1;
wire [15:0] q = sub_wire0[15:0];
wire [8:0] rdusedw = sub_wire1[8:0];
dcfifo dcfifo_component (
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.rdusedw (sub_wire1),
.aclr (),
.eccstatus (),
.rdempty (),
.rdfull (),
.wrempty (),
.wrfull (),
.wrusedw ());
defparam
dcfifo_component.intended_device_family = "Cyclone V",
dcfifo_component.lpm_numwords = 512,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 16,
dcfifo_component.lpm_widthu = 9,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "512"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "16"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: rdusedw 0 0 9 0 OUTPUT NODEFVAL "rdusedw[8..0]"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: rdusedw 0 0 9 0 @rdusedw 0 0 9 0
// Retrieval info: GEN_FILE: TYPE_NORMAL cam_fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL cam_fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cam_fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cam_fifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cam_fifo_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL cam_fifo_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized OR with generic_baseblocks_v2_1_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_carry_or #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire S,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign COUT = CIN | S;
end else begin : USE_FPGA
wire S_n;
assign S_n = ~S;
MUXCY and_inst
(
.O (COUT),
.CI (CIN),
.DI (1'b1),
.S (S_n)
);
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A22OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__A22OI_BEHAVIORAL_PP_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__a22oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y , nand0_out, nand1_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A22OI_BEHAVIORAL_PP_V |
//////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE SD Card Controller IP Core ////
//// ////
//// sd_controller_wb.v ////
//// ////
//// This file is part of the WISHBONE SD Card ////
//// Controller IP Core project ////
//// http://opencores.org/project,sd_card_controller ////
//// ////
//// Description ////
//// Wishbone interface responsible for comunication with core ////
//// ////
//// Author(s): ////
//// - Marek Czerski, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2013 Authors ////
//// ////
//// Based on original work by ////
//// Adam Edvardsson ([email protected]) ////
//// ////
//// Copyright (C) 2009 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "sd_defines.h"
module sd_controller_wb(
// WISHBONE slave
wb_clk_i,
wb_rst_i,
wb_dat_i,
wb_dat_o,
wb_adr_i,
wb_sel_i,
wb_we_i,
wb_cyc_i,
wb_stb_i,
wb_ack_o,
cmd_start,
data_int_rst,
cmd_int_rst,
argument_reg,
command_reg,
response_0_reg,
response_1_reg,
response_2_reg,
response_3_reg,
software_reset_reg,
cmd_timeout_reg,
data_timeout_reg,
block_size_reg,
controll_setting_reg,
cmd_int_status_reg,
cmd_int_enable_reg,
clock_divider_reg,
block_count_reg,
dma_addr_reg,
data_int_status_reg,
data_int_enable_reg
);
// WISHBONE common
input wb_clk_i; // WISHBONE clock
input wb_rst_i; // WISHBONE reset
input [31:0] wb_dat_i; // WISHBONE data input
output reg [31:0] wb_dat_o; // WISHBONE data output
// WISHBONE error output
// WISHBONE slave
input [7:0] wb_adr_i; // WISHBONE address input
input [3:0] wb_sel_i; // WISHBONE byte select input
input wb_we_i; // WISHBONE write enable input
input wb_cyc_i; // WISHBONE cycle input
input wb_stb_i; // WISHBONE strobe input
output reg wb_ack_o; // WISHBONE acknowledge output
output reg cmd_start;
//Buss accessible registers
output [31:0] argument_reg;
output [`CMD_REG_SIZE-1:0] command_reg;
input wire [31:0] response_0_reg;
input wire [31:0] response_1_reg;
input wire [31:0] response_2_reg;
input wire [31:0] response_3_reg;
output [0:0] software_reset_reg;
output [`CMD_TIMEOUT_W-1:0] cmd_timeout_reg;
output [`DATA_TIMEOUT_W-1:0] data_timeout_reg;
output [`BLKSIZE_W-1:0] block_size_reg;
output [0:0] controll_setting_reg;
input wire [`INT_CMD_SIZE-1:0] cmd_int_status_reg;
output [`INT_CMD_SIZE-1:0] cmd_int_enable_reg;
output [7:0] clock_divider_reg;
input wire [`INT_DATA_SIZE-1:0] data_int_status_reg;
output [`INT_DATA_SIZE-1:0] data_int_enable_reg;
//Register Controll
output reg data_int_rst;
output reg cmd_int_rst;
output [`BLKCNT_W-1:0]block_count_reg;
output [31:0] dma_addr_reg;
wire we;
parameter voltage_controll_reg = `SUPPLY_VOLTAGE_mV;
parameter capabilies_reg = 16'b0000_0000_0000_0000;
assign we = (wb_we_i && ((wb_stb_i && wb_cyc_i) || wb_ack_o)) ? 1'b1 : 1'b0;
byte_en_reg #(32) argument_r(wb_clk_i, wb_rst_i, we && wb_adr_i == `argument, wb_sel_i, wb_dat_i, argument_reg);
byte_en_reg #(`CMD_REG_SIZE) command_r(wb_clk_i, wb_rst_i, we && wb_adr_i == `command, wb_sel_i[(`CMD_REG_SIZE-1)/8:0], wb_dat_i[`CMD_REG_SIZE-1:0], command_reg);
byte_en_reg #(1) reset_r(wb_clk_i, wb_rst_i, we && wb_adr_i == `reset, wb_sel_i[0], wb_dat_i[0], software_reset_reg);
byte_en_reg #(`CMD_TIMEOUT_W) cmd_timeout_r(wb_clk_i, wb_rst_i, we && wb_adr_i == `cmd_timeout, wb_sel_i[(`CMD_TIMEOUT_W-1)/8:0], wb_dat_i[`CMD_TIMEOUT_W-1:0], cmd_timeout_reg);
byte_en_reg #(`DATA_TIMEOUT_W) data_timeout_r(wb_clk_i, wb_rst_i, we && wb_adr_i == `data_timeout, wb_sel_i[(`DATA_TIMEOUT_W-1)/8:0], wb_dat_i[`DATA_TIMEOUT_W-1:0], data_timeout_reg);
byte_en_reg #(`BLKSIZE_W, `RESET_BLOCK_SIZE) block_size_r(wb_clk_i, wb_rst_i, we && wb_adr_i == `blksize, wb_sel_i[(`BLKSIZE_W-1)/8:0], wb_dat_i[`BLKSIZE_W-1:0], block_size_reg);
byte_en_reg #(1) controll_r(wb_clk_i, wb_rst_i, we && wb_adr_i == `controller, wb_sel_i[0], wb_dat_i[0], controll_setting_reg);
byte_en_reg #(`INT_CMD_SIZE) cmd_int_r(wb_clk_i, wb_rst_i, we && wb_adr_i == `cmd_iser, wb_sel_i[(`INT_CMD_SIZE-1)/8:0], wb_dat_i[`INT_CMD_SIZE-1:0], cmd_int_enable_reg);
byte_en_reg #(8) clock_d_r(wb_clk_i, wb_rst_i, we && wb_adr_i == `clock_d, wb_sel_i[0], wb_dat_i[7:0], clock_divider_reg);
byte_en_reg #(`INT_DATA_SIZE) data_int_r(wb_clk_i, wb_rst_i, we && wb_adr_i == `data_iser, wb_sel_i[(`INT_DATA_SIZE-1)/8:0], wb_dat_i[`INT_DATA_SIZE-1:0], data_int_enable_reg);
byte_en_reg #(`BLKCNT_W) block_count_r(wb_clk_i, wb_rst_i, we && wb_adr_i == `blkcnt, wb_sel_i[(`BLKCNT_W-1)/8:0], wb_dat_i[`BLKCNT_W-1:0], block_count_reg);
byte_en_reg #(32) dma_addr_r(wb_clk_i, wb_rst_i, we && wb_adr_i == `dst_src_addr, wb_sel_i[3:0], wb_dat_i, dma_addr_reg);
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)begin
wb_ack_o <= 0;
cmd_start <= 0;
data_int_rst <= 0;
cmd_int_rst <= 0;
end
else
begin
cmd_start <= 0;
data_int_rst <= 0;
cmd_int_rst <= 0;
if ((wb_stb_i & wb_cyc_i) || wb_ack_o)begin
if (wb_we_i) begin
case (wb_adr_i)
`argument: cmd_start <= 1;//only msb triggers xfer
`cmd_isr: cmd_int_rst <= 1;
`data_isr: data_int_rst <= 1;
endcase
end
wb_ack_o <= wb_cyc_i & wb_stb_i & ~wb_ack_o;
end
end
end
always @(posedge wb_clk_i or posedge wb_rst_i)begin
if (wb_rst_i == 1)
wb_dat_o <= 0;
else
if (wb_stb_i & wb_cyc_i) begin //CS
case (wb_adr_i)
`argument: wb_dat_o <= argument_reg;
`command: wb_dat_o <= command_reg;
`resp0: wb_dat_o <= response_0_reg;
`resp1: wb_dat_o <= response_1_reg;
`resp2: wb_dat_o <= response_2_reg;
`resp3: wb_dat_o <= response_3_reg;
`controller: wb_dat_o <= controll_setting_reg;
`blksize: wb_dat_o <= block_size_reg;
`voltage: wb_dat_o <= voltage_controll_reg;
`reset: wb_dat_o <= software_reset_reg;
`cmd_timeout: wb_dat_o <= cmd_timeout_reg;
`data_timeout: wb_dat_o <= data_timeout_reg;
`cmd_isr: wb_dat_o <= cmd_int_status_reg;
`cmd_iser: wb_dat_o <= cmd_int_enable_reg;
`clock_d: wb_dat_o <= clock_divider_reg;
`capa: wb_dat_o <= capabilies_reg;
`data_isr: wb_dat_o <= data_int_status_reg;
`blkcnt: wb_dat_o <= block_count_reg;
`data_iser: wb_dat_o <= data_int_enable_reg;
`dst_src_addr: wb_dat_o <= dma_addr_reg;
endcase
end
end
endmodule
|
module xyz (/*AUTOARG*/
// Inputs
signal_e, signal_b
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [2:0] signal_b; // To u_abc of abc.v
input signal_e; // To u_def of def.v
// End of automatics
/*AUTOOUTPUT*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire signal_c; // From u_abc of abc.v
wire signal_f; // From u_def of def.v
// End of automatics
/* abc AUTO_TEMPLATE
(
// Outputs
.signal_c (signal_c),
// Inputs
.signal_a ({1'b0, signal_f}),
.signal_b (signal_b[2:0]));
*/
abc u_abc
(/*AUTOINST*/
// Outputs
.signal_c (signal_c), // Templated
// Inputs
.signal_a ({1'b0, signal_f}), // Templated
.signal_b (signal_b[2:0])); // Templated
/* def AUTO_TEMPLATE
(// Outputs
.signal_f (signal_f),
// Inputs
.signal_d ({1'b1, signal_c}),
.signal_e ({2'b11, signal_e}));
*/
def u_def
(/*AUTOINST*/
// Outputs
.signal_f (signal_f), // Templated
// Inputs
.signal_d ({1'b1, signal_c}), // Templated
.signal_e ({2'b11, signal_e})); // Templated
endmodule // xyz
module abc (/*AUTOARG*/
// Outputs
signal_c,
// Inputs
signal_a, signal_b
);
input [1:0] signal_a;
input [2:0] signal_b;
output signal_c;
endmodule // abc
module def (/*AUTOARG*/
// Outputs
signal_f,
// Inputs
signal_d, signal_e
);
input [1:0] signal_d;
input [2:0] signal_e;
output signal_f;
endmodule // def
|
// CONFIG:
// NUM_COEFF = 43
// PIPLINED = 1
// WARNING: more than enough COEFFICIENTS in array (there are 26, and we only need 22)
module fir (
clk,
reset,
clk_ena,
i_valid,
i_in,
o_valid,
o_out
);
// Data Width
parameter dw = 18; //Data input/output bits
// Number of filter coefficients
parameter N = 43;
parameter N_UNIQ = 22; // ciel(N/2) assuming symmetric filter coefficients
//Number of extra valid cycles needed to align output (i.e. computation pipeline depth + input/output registers
localparam N_VALID_REGS = 50;
input clk;
input reset;
input clk_ena;
input i_valid;
input [dw-1:0] i_in; // signed
output o_valid;
output [dw-1:0] o_out; // signed
// Data Width dervied parameters
localparam dw_add_int = 18; //Internal adder precision bits
localparam dw_mult_int = 36; //Internal multiplier precision bits
localparam scale_factor = 17; //Multiplier normalization shift amount
// Number of extra registers in INPUT_PIPELINE_REG to prevent contention for CHAIN_END's chain adders
localparam N_INPUT_REGS = 43;
// Debug
// initial begin
// $display ("Data Width: %d", dw);
// $display ("Data Width Add Internal: %d", dw_add_int);
// $display ("Data Width Mult Internal: %d", dw_mult_int);
// $display ("Scale Factor: %d", scale_factor);
// end
reg [dw-1:0] COEFFICIENT_0;
reg [dw-1:0] COEFFICIENT_1;
reg [dw-1:0] COEFFICIENT_2;
reg [dw-1:0] COEFFICIENT_3;
reg [dw-1:0] COEFFICIENT_4;
reg [dw-1:0] COEFFICIENT_5;
reg [dw-1:0] COEFFICIENT_6;
reg [dw-1:0] COEFFICIENT_7;
reg [dw-1:0] COEFFICIENT_8;
reg [dw-1:0] COEFFICIENT_9;
reg [dw-1:0] COEFFICIENT_10;
reg [dw-1:0] COEFFICIENT_11;
reg [dw-1:0] COEFFICIENT_12;
reg [dw-1:0] COEFFICIENT_13;
reg [dw-1:0] COEFFICIENT_14;
reg [dw-1:0] COEFFICIENT_15;
reg [dw-1:0] COEFFICIENT_16;
reg [dw-1:0] COEFFICIENT_17;
reg [dw-1:0] COEFFICIENT_18;
reg [dw-1:0] COEFFICIENT_19;
reg [dw-1:0] COEFFICIENT_20;
reg [dw-1:0] COEFFICIENT_21;
always@(posedge clk) begin
COEFFICIENT_0 <= 18'd88;
COEFFICIENT_1 <= 18'd0;
COEFFICIENT_2 <= -18'd97;
COEFFICIENT_3 <= -18'd197;
COEFFICIENT_4 <= -18'd294;
COEFFICIENT_5 <= -18'd380;
COEFFICIENT_6 <= -18'd447;
COEFFICIENT_7 <= -18'd490;
COEFFICIENT_8 <= -18'd504;
COEFFICIENT_9 <= -18'd481;
COEFFICIENT_10 <= -18'd420;
COEFFICIENT_11 <= -18'd319;
COEFFICIENT_12 <= -18'd178;
COEFFICIENT_13 <= 18'd0;
COEFFICIENT_14 <= 18'd212;
COEFFICIENT_15 <= 18'd451;
COEFFICIENT_16 <= 18'd710;
COEFFICIENT_17 <= 18'd980;
COEFFICIENT_18 <= 18'd1252;
COEFFICIENT_19 <= 18'd1514;
COEFFICIENT_20 <= 18'd1756;
COEFFICIENT_21 <= 18'd1971;
end
////******************************************************
// *
// * Valid Delay Pipeline
// *
// *****************************************************
//Input valid signal is pipelined to become output valid signal
//Valid registers
reg [N_VALID_REGS-1:0] VALID_PIPELINE_REGS;
always@(posedge clk or posedge reset) begin
if(reset) begin
VALID_PIPELINE_REGS <= 0;
end else begin
if(clk_ena) begin
VALID_PIPELINE_REGS <= {VALID_PIPELINE_REGS[N_VALID_REGS-2:0], i_valid};
end else begin
VALID_PIPELINE_REGS <= VALID_PIPELINE_REGS;
end
end
end
////******************************************************
// *
// * Input Register Pipeline
// *
// *****************************************************
//Pipelined input values
//Input value registers
wire [dw-1:0] INPUT_PIPELINE_REG_0;
wire [dw-1:0] INPUT_PIPELINE_REG_1;
wire [dw-1:0] INPUT_PIPELINE_REG_2;
wire [dw-1:0] INPUT_PIPELINE_REG_3;
wire [dw-1:0] INPUT_PIPELINE_REG_4;
wire [dw-1:0] INPUT_PIPELINE_REG_5;
wire [dw-1:0] INPUT_PIPELINE_REG_6;
wire [dw-1:0] INPUT_PIPELINE_REG_7;
wire [dw-1:0] INPUT_PIPELINE_REG_8;
wire [dw-1:0] INPUT_PIPELINE_REG_9;
wire [dw-1:0] INPUT_PIPELINE_REG_10;
wire [dw-1:0] INPUT_PIPELINE_REG_11;
wire [dw-1:0] INPUT_PIPELINE_REG_12;
wire [dw-1:0] INPUT_PIPELINE_REG_13;
wire [dw-1:0] INPUT_PIPELINE_REG_14;
wire [dw-1:0] INPUT_PIPELINE_REG_15;
wire [dw-1:0] INPUT_PIPELINE_REG_16;
wire [dw-1:0] INPUT_PIPELINE_REG_17;
wire [dw-1:0] INPUT_PIPELINE_REG_18;
wire [dw-1:0] INPUT_PIPELINE_REG_19;
wire [dw-1:0] INPUT_PIPELINE_REG_20;
wire [dw-1:0] INPUT_PIPELINE_REG_21;
wire [dw-1:0] INPUT_PIPELINE_REG_22;
wire [dw-1:0] INPUT_PIPELINE_REG_23;
wire [dw-1:0] INPUT_PIPELINE_REG_24;
wire [dw-1:0] INPUT_PIPELINE_REG_25;
wire [dw-1:0] INPUT_PIPELINE_REG_26;
wire [dw-1:0] INPUT_PIPELINE_REG_27;
wire [dw-1:0] INPUT_PIPELINE_REG_28;
wire [dw-1:0] INPUT_PIPELINE_REG_29;
wire [dw-1:0] INPUT_PIPELINE_REG_30;
wire [dw-1:0] INPUT_PIPELINE_REG_31;
wire [dw-1:0] INPUT_PIPELINE_REG_32;
wire [dw-1:0] INPUT_PIPELINE_REG_33;
wire [dw-1:0] INPUT_PIPELINE_REG_34;
wire [dw-1:0] INPUT_PIPELINE_REG_35;
wire [dw-1:0] INPUT_PIPELINE_REG_36;
wire [dw-1:0] INPUT_PIPELINE_REG_37;
wire [dw-1:0] INPUT_PIPELINE_REG_38;
wire [dw-1:0] INPUT_PIPELINE_REG_39;
wire [dw-1:0] INPUT_PIPELINE_REG_40;
wire [dw-1:0] INPUT_PIPELINE_REG_41;
wire [dw-1:0] INPUT_PIPELINE_REG_42;
input_pipeline in_pipe(
.clk(clk), .clk_ena(clk_ena),
.in_stream(i_in),
.pipeline_reg_0(INPUT_PIPELINE_REG_0),
.pipeline_reg_1(INPUT_PIPELINE_REG_1),
.pipeline_reg_2(INPUT_PIPELINE_REG_2),
.pipeline_reg_3(INPUT_PIPELINE_REG_3),
.pipeline_reg_4(INPUT_PIPELINE_REG_4),
.pipeline_reg_5(INPUT_PIPELINE_REG_5),
.pipeline_reg_6(INPUT_PIPELINE_REG_6),
.pipeline_reg_7(INPUT_PIPELINE_REG_7),
.pipeline_reg_8(INPUT_PIPELINE_REG_8),
.pipeline_reg_9(INPUT_PIPELINE_REG_9),
.pipeline_reg_10(INPUT_PIPELINE_REG_10),
.pipeline_reg_11(INPUT_PIPELINE_REG_11),
.pipeline_reg_12(INPUT_PIPELINE_REG_12),
.pipeline_reg_13(INPUT_PIPELINE_REG_13),
.pipeline_reg_14(INPUT_PIPELINE_REG_14),
.pipeline_reg_15(INPUT_PIPELINE_REG_15),
.pipeline_reg_16(INPUT_PIPELINE_REG_16),
.pipeline_reg_17(INPUT_PIPELINE_REG_17),
.pipeline_reg_18(INPUT_PIPELINE_REG_18),
.pipeline_reg_19(INPUT_PIPELINE_REG_19),
.pipeline_reg_20(INPUT_PIPELINE_REG_20),
.pipeline_reg_21(INPUT_PIPELINE_REG_21),
.pipeline_reg_22(INPUT_PIPELINE_REG_22),
.pipeline_reg_23(INPUT_PIPELINE_REG_23),
.pipeline_reg_24(INPUT_PIPELINE_REG_24),
.pipeline_reg_25(INPUT_PIPELINE_REG_25),
.pipeline_reg_26(INPUT_PIPELINE_REG_26),
.pipeline_reg_27(INPUT_PIPELINE_REG_27),
.pipeline_reg_28(INPUT_PIPELINE_REG_28),
.pipeline_reg_29(INPUT_PIPELINE_REG_29),
.pipeline_reg_30(INPUT_PIPELINE_REG_30),
.pipeline_reg_31(INPUT_PIPELINE_REG_31),
.pipeline_reg_32(INPUT_PIPELINE_REG_32),
.pipeline_reg_33(INPUT_PIPELINE_REG_33),
.pipeline_reg_34(INPUT_PIPELINE_REG_34),
.pipeline_reg_35(INPUT_PIPELINE_REG_35),
.pipeline_reg_36(INPUT_PIPELINE_REG_36),
.pipeline_reg_37(INPUT_PIPELINE_REG_37),
.pipeline_reg_38(INPUT_PIPELINE_REG_38),
.pipeline_reg_39(INPUT_PIPELINE_REG_39),
.pipeline_reg_40(INPUT_PIPELINE_REG_40),
.pipeline_reg_41(INPUT_PIPELINE_REG_41),
.pipeline_reg_42(INPUT_PIPELINE_REG_42),
.reset(reset) );
defparam in_pipe.WIDTH = 18; // = dw
////******************************************************
// *
// * Computation Pipeline
// *
// *****************************************************
// ************************* LEVEL 0 ************************* \\
wire [dw-1:0] L0_output_wires_0;
wire [dw-1:0] L0_output_wires_1;
wire [dw-1:0] L0_output_wires_2;
wire [dw-1:0] L0_output_wires_3;
wire [dw-1:0] L0_output_wires_4;
wire [dw-1:0] L0_output_wires_5;
wire [dw-1:0] L0_output_wires_6;
wire [dw-1:0] L0_output_wires_7;
wire [dw-1:0] L0_output_wires_8;
wire [dw-1:0] L0_output_wires_9;
wire [dw-1:0] L0_output_wires_10;
wire [dw-1:0] L0_output_wires_11;
wire [dw-1:0] L0_output_wires_12;
wire [dw-1:0] L0_output_wires_13;
wire [dw-1:0] L0_output_wires_14;
wire [dw-1:0] L0_output_wires_15;
wire [dw-1:0] L0_output_wires_16;
wire [dw-1:0] L0_output_wires_17;
wire [dw-1:0] L0_output_wires_18;
wire [dw-1:0] L0_output_wires_19;
wire [dw-1:0] L0_output_wires_20;
wire [dw-1:0] L0_output_wires_21;
adder_with_1_reg L0_adder_0and42(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_0),
.datab (INPUT_PIPELINE_REG_42),
.result(L0_output_wires_0)
);
adder_with_1_reg L0_adder_1and41(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_1),
.datab (INPUT_PIPELINE_REG_41),
.result(L0_output_wires_1)
);
adder_with_1_reg L0_adder_2and40(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_2),
.datab (INPUT_PIPELINE_REG_40),
.result(L0_output_wires_2)
);
adder_with_1_reg L0_adder_3and39(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_3),
.datab (INPUT_PIPELINE_REG_39),
.result(L0_output_wires_3)
);
adder_with_1_reg L0_adder_4and38(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_4),
.datab (INPUT_PIPELINE_REG_38),
.result(L0_output_wires_4)
);
adder_with_1_reg L0_adder_5and37(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_5),
.datab (INPUT_PIPELINE_REG_37),
.result(L0_output_wires_5)
);
adder_with_1_reg L0_adder_6and36(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_6),
.datab (INPUT_PIPELINE_REG_36),
.result(L0_output_wires_6)
);
adder_with_1_reg L0_adder_7and35(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_7),
.datab (INPUT_PIPELINE_REG_35),
.result(L0_output_wires_7)
);
adder_with_1_reg L0_adder_8and34(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_8),
.datab (INPUT_PIPELINE_REG_34),
.result(L0_output_wires_8)
);
adder_with_1_reg L0_adder_9and33(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_9),
.datab (INPUT_PIPELINE_REG_33),
.result(L0_output_wires_9)
);
adder_with_1_reg L0_adder_10and32(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_10),
.datab (INPUT_PIPELINE_REG_32),
.result(L0_output_wires_10)
);
adder_with_1_reg L0_adder_11and31(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_11),
.datab (INPUT_PIPELINE_REG_31),
.result(L0_output_wires_11)
);
adder_with_1_reg L0_adder_12and30(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_12),
.datab (INPUT_PIPELINE_REG_30),
.result(L0_output_wires_12)
);
adder_with_1_reg L0_adder_13and29(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_13),
.datab (INPUT_PIPELINE_REG_29),
.result(L0_output_wires_13)
);
adder_with_1_reg L0_adder_14and28(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_14),
.datab (INPUT_PIPELINE_REG_28),
.result(L0_output_wires_14)
);
adder_with_1_reg L0_adder_15and27(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_15),
.datab (INPUT_PIPELINE_REG_27),
.result(L0_output_wires_15)
);
adder_with_1_reg L0_adder_16and26(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_16),
.datab (INPUT_PIPELINE_REG_26),
.result(L0_output_wires_16)
);
adder_with_1_reg L0_adder_17and25(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_17),
.datab (INPUT_PIPELINE_REG_25),
.result(L0_output_wires_17)
);
adder_with_1_reg L0_adder_18and24(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_18),
.datab (INPUT_PIPELINE_REG_24),
.result(L0_output_wires_18)
);
adder_with_1_reg L0_adder_19and23(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_19),
.datab (INPUT_PIPELINE_REG_23),
.result(L0_output_wires_19)
);
adder_with_1_reg L0_adder_20and22(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_20),
.datab (INPUT_PIPELINE_REG_22),
.result(L0_output_wires_20)
);
// (21 main tree Adders)
// ********* Byes ******** \\
one_register L0_byereg_for_21(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_21),
.result(L0_output_wires_21)
);
// (1 byes)
// ************************* LEVEL 1 ************************* \\
// **************** Multipliers **************** \\
wire [dw-1:0] L1_mult_wires_0;
wire [dw-1:0] L1_mult_wires_1;
wire [dw-1:0] L1_mult_wires_2;
wire [dw-1:0] L1_mult_wires_3;
wire [dw-1:0] L1_mult_wires_4;
wire [dw-1:0] L1_mult_wires_5;
wire [dw-1:0] L1_mult_wires_6;
wire [dw-1:0] L1_mult_wires_7;
wire [dw-1:0] L1_mult_wires_8;
wire [dw-1:0] L1_mult_wires_9;
wire [dw-1:0] L1_mult_wires_10;
wire [dw-1:0] L1_mult_wires_11;
wire [dw-1:0] L1_mult_wires_12;
wire [dw-1:0] L1_mult_wires_13;
wire [dw-1:0] L1_mult_wires_14;
wire [dw-1:0] L1_mult_wires_15;
wire [dw-1:0] L1_mult_wires_16;
wire [dw-1:0] L1_mult_wires_17;
wire [dw-1:0] L1_mult_wires_18;
wire [dw-1:0] L1_mult_wires_19;
wire [dw-1:0] L1_mult_wires_20;
wire [dw-1:0] L1_mult_wires_21;
multiplier_with_reg L1_mul_0(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_0),
.datab (COEFFICIENT_0),
.result(L1_mult_wires_0)
);
multiplier_with_reg L1_mul_1(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_1),
.datab (COEFFICIENT_1),
.result(L1_mult_wires_1)
);
multiplier_with_reg L1_mul_2(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_2),
.datab (COEFFICIENT_2),
.result(L1_mult_wires_2)
);
multiplier_with_reg L1_mul_3(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_3),
.datab (COEFFICIENT_3),
.result(L1_mult_wires_3)
);
multiplier_with_reg L1_mul_4(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_4),
.datab (COEFFICIENT_4),
.result(L1_mult_wires_4)
);
multiplier_with_reg L1_mul_5(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_5),
.datab (COEFFICIENT_5),
.result(L1_mult_wires_5)
);
multiplier_with_reg L1_mul_6(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_6),
.datab (COEFFICIENT_6),
.result(L1_mult_wires_6)
);
multiplier_with_reg L1_mul_7(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_7),
.datab (COEFFICIENT_7),
.result(L1_mult_wires_7)
);
multiplier_with_reg L1_mul_8(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_8),
.datab (COEFFICIENT_8),
.result(L1_mult_wires_8)
);
multiplier_with_reg L1_mul_9(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_9),
.datab (COEFFICIENT_9),
.result(L1_mult_wires_9)
);
multiplier_with_reg L1_mul_10(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_10),
.datab (COEFFICIENT_10),
.result(L1_mult_wires_10)
);
multiplier_with_reg L1_mul_11(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_11),
.datab (COEFFICIENT_11),
.result(L1_mult_wires_11)
);
multiplier_with_reg L1_mul_12(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_12),
.datab (COEFFICIENT_12),
.result(L1_mult_wires_12)
);
multiplier_with_reg L1_mul_13(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_13),
.datab (COEFFICIENT_13),
.result(L1_mult_wires_13)
);
multiplier_with_reg L1_mul_14(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_14),
.datab (COEFFICIENT_14),
.result(L1_mult_wires_14)
);
multiplier_with_reg L1_mul_15(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_15),
.datab (COEFFICIENT_15),
.result(L1_mult_wires_15)
);
multiplier_with_reg L1_mul_16(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_16),
.datab (COEFFICIENT_16),
.result(L1_mult_wires_16)
);
multiplier_with_reg L1_mul_17(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_17),
.datab (COEFFICIENT_17),
.result(L1_mult_wires_17)
);
multiplier_with_reg L1_mul_18(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_18),
.datab (COEFFICIENT_18),
.result(L1_mult_wires_18)
);
multiplier_with_reg L1_mul_19(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_19),
.datab (COEFFICIENT_19),
.result(L1_mult_wires_19)
);
multiplier_with_reg L1_mul_20(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_20),
.datab (COEFFICIENT_20),
.result(L1_mult_wires_20)
);
multiplier_with_reg L1_mul_21(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_21),
.datab (COEFFICIENT_21),
.result(L1_mult_wires_21)
);
// (22 Multipliers)
// **************** Adders **************** \\
wire [dw-1:0] L1_output_wires_0;
wire [dw-1:0] L1_output_wires_1;
wire [dw-1:0] L1_output_wires_2;
wire [dw-1:0] L1_output_wires_3;
wire [dw-1:0] L1_output_wires_4;
wire [dw-1:0] L1_output_wires_5;
wire [dw-1:0] L1_output_wires_6;
wire [dw-1:0] L1_output_wires_7;
wire [dw-1:0] L1_output_wires_8;
wire [dw-1:0] L1_output_wires_9;
wire [dw-1:0] L1_output_wires_10;
adder_with_1_reg L1_adder_0and1(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_mult_wires_0),
.datab (L1_mult_wires_1),
.result(L1_output_wires_0)
);
adder_with_1_reg L1_adder_2and3(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_mult_wires_2),
.datab (L1_mult_wires_3),
.result(L1_output_wires_1)
);
adder_with_1_reg L1_adder_4and5(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_mult_wires_4),
.datab (L1_mult_wires_5),
.result(L1_output_wires_2)
);
adder_with_1_reg L1_adder_6and7(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_mult_wires_6),
.datab (L1_mult_wires_7),
.result(L1_output_wires_3)
);
adder_with_1_reg L1_adder_8and9(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_mult_wires_8),
.datab (L1_mult_wires_9),
.result(L1_output_wires_4)
);
adder_with_1_reg L1_adder_10and11(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_mult_wires_10),
.datab (L1_mult_wires_11),
.result(L1_output_wires_5)
);
adder_with_1_reg L1_adder_12and13(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_mult_wires_12),
.datab (L1_mult_wires_13),
.result(L1_output_wires_6)
);
adder_with_1_reg L1_adder_14and15(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_mult_wires_14),
.datab (L1_mult_wires_15),
.result(L1_output_wires_7)
);
adder_with_1_reg L1_adder_16and17(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_mult_wires_16),
.datab (L1_mult_wires_17),
.result(L1_output_wires_8)
);
adder_with_1_reg L1_adder_18and19(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_mult_wires_18),
.datab (L1_mult_wires_19),
.result(L1_output_wires_9)
);
adder_with_1_reg L1_adder_20and21(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_mult_wires_20),
.datab (L1_mult_wires_21),
.result(L1_output_wires_10)
);
// (11 main tree Adders)
// ************************* LEVEL 2 ************************* \\
wire [dw-1:0] L2_output_wires_0;
wire [dw-1:0] L2_output_wires_1;
wire [dw-1:0] L2_output_wires_2;
wire [dw-1:0] L2_output_wires_3;
wire [dw-1:0] L2_output_wires_4;
wire [dw-1:0] L2_output_wires_5;
adder_with_1_reg L2_adder_0and1(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_output_wires_0),
.datab (L1_output_wires_1),
.result(L2_output_wires_0)
);
adder_with_1_reg L2_adder_2and3(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_output_wires_2),
.datab (L1_output_wires_3),
.result(L2_output_wires_1)
);
adder_with_1_reg L2_adder_4and5(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_output_wires_4),
.datab (L1_output_wires_5),
.result(L2_output_wires_2)
);
adder_with_1_reg L2_adder_6and7(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_output_wires_6),
.datab (L1_output_wires_7),
.result(L2_output_wires_3)
);
adder_with_1_reg L2_adder_8and9(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_output_wires_8),
.datab (L1_output_wires_9),
.result(L2_output_wires_4)
);
// (5 main tree Adders)
// ********* Byes ******** \\
one_register L2_byereg_for_10(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_output_wires_10),
.result(L2_output_wires_5)
);
// (1 byes)
// ************************* LEVEL 3 ************************* \\
wire [dw-1:0] L3_output_wires_0;
wire [dw-1:0] L3_output_wires_1;
wire [dw-1:0] L3_output_wires_2;
adder_with_1_reg L3_adder_0and1(
.clk(clk), .clk_ena(clk_ena),
.dataa (L2_output_wires_0),
.datab (L2_output_wires_1),
.result(L3_output_wires_0)
);
adder_with_1_reg L3_adder_2and3(
.clk(clk), .clk_ena(clk_ena),
.dataa (L2_output_wires_2),
.datab (L2_output_wires_3),
.result(L3_output_wires_1)
);
adder_with_1_reg L3_adder_4and5(
.clk(clk), .clk_ena(clk_ena),
.dataa (L2_output_wires_4),
.datab (L2_output_wires_5),
.result(L3_output_wires_2)
);
// (3 main tree Adders)
// ************************* LEVEL 4 ************************* \\
wire [dw-1:0] L4_output_wires_0;
wire [dw-1:0] L4_output_wires_1;
adder_with_1_reg L4_adder_0and1(
.clk(clk), .clk_ena(clk_ena),
.dataa (L3_output_wires_0),
.datab (L3_output_wires_1),
.result(L4_output_wires_0)
);
// (1 main tree Adders)
// ********* Byes ******** \\
one_register L4_byereg_for_2(
.clk(clk), .clk_ena(clk_ena),
.dataa (L3_output_wires_2),
.result(L4_output_wires_1)
);
// (1 byes)
// ************************* LEVEL 5 ************************* \\
wire [dw-1:0] L5_output_wires_0;
adder_with_1_reg L5_adder_0and1(
.clk(clk), .clk_ena(clk_ena),
.dataa (L4_output_wires_0),
.datab (L4_output_wires_1),
.result(L5_output_wires_0)
);
// (1 main tree Adders)
////******************************************************
// *
// * Output Logic
// *
// *****************************************************
//Actual outputs
assign o_out = L5_output_wires_0;
assign o_valid = VALID_PIPELINE_REGS[N_VALID_REGS-1];
endmodule
module input_pipeline (
clk,
clk_ena,
in_stream,
pipeline_reg_0,
pipeline_reg_1,
pipeline_reg_2,
pipeline_reg_3,
pipeline_reg_4,
pipeline_reg_5,
pipeline_reg_6,
pipeline_reg_7,
pipeline_reg_8,
pipeline_reg_9,
pipeline_reg_10,
pipeline_reg_11,
pipeline_reg_12,
pipeline_reg_13,
pipeline_reg_14,
pipeline_reg_15,
pipeline_reg_16,
pipeline_reg_17,
pipeline_reg_18,
pipeline_reg_19,
pipeline_reg_20,
pipeline_reg_21,
pipeline_reg_22,
pipeline_reg_23,
pipeline_reg_24,
pipeline_reg_25,
pipeline_reg_26,
pipeline_reg_27,
pipeline_reg_28,
pipeline_reg_29,
pipeline_reg_30,
pipeline_reg_31,
pipeline_reg_32,
pipeline_reg_33,
pipeline_reg_34,
pipeline_reg_35,
pipeline_reg_36,
pipeline_reg_37,
pipeline_reg_38,
pipeline_reg_39,
pipeline_reg_40,
pipeline_reg_41,
pipeline_reg_42,
reset);
parameter WIDTH = 1;
//Input value registers
input clk;
input clk_ena;
input [WIDTH-1:0] in_stream;
output [WIDTH-1:0] pipeline_reg_0;
output [WIDTH-1:0] pipeline_reg_1;
output [WIDTH-1:0] pipeline_reg_2;
output [WIDTH-1:0] pipeline_reg_3;
output [WIDTH-1:0] pipeline_reg_4;
output [WIDTH-1:0] pipeline_reg_5;
output [WIDTH-1:0] pipeline_reg_6;
output [WIDTH-1:0] pipeline_reg_7;
output [WIDTH-1:0] pipeline_reg_8;
output [WIDTH-1:0] pipeline_reg_9;
output [WIDTH-1:0] pipeline_reg_10;
output [WIDTH-1:0] pipeline_reg_11;
output [WIDTH-1:0] pipeline_reg_12;
output [WIDTH-1:0] pipeline_reg_13;
output [WIDTH-1:0] pipeline_reg_14;
output [WIDTH-1:0] pipeline_reg_15;
output [WIDTH-1:0] pipeline_reg_16;
output [WIDTH-1:0] pipeline_reg_17;
output [WIDTH-1:0] pipeline_reg_18;
output [WIDTH-1:0] pipeline_reg_19;
output [WIDTH-1:0] pipeline_reg_20;
output [WIDTH-1:0] pipeline_reg_21;
output [WIDTH-1:0] pipeline_reg_22;
output [WIDTH-1:0] pipeline_reg_23;
output [WIDTH-1:0] pipeline_reg_24;
output [WIDTH-1:0] pipeline_reg_25;
output [WIDTH-1:0] pipeline_reg_26;
output [WIDTH-1:0] pipeline_reg_27;
output [WIDTH-1:0] pipeline_reg_28;
output [WIDTH-1:0] pipeline_reg_29;
output [WIDTH-1:0] pipeline_reg_30;
output [WIDTH-1:0] pipeline_reg_31;
output [WIDTH-1:0] pipeline_reg_32;
output [WIDTH-1:0] pipeline_reg_33;
output [WIDTH-1:0] pipeline_reg_34;
output [WIDTH-1:0] pipeline_reg_35;
output [WIDTH-1:0] pipeline_reg_36;
output [WIDTH-1:0] pipeline_reg_37;
output [WIDTH-1:0] pipeline_reg_38;
output [WIDTH-1:0] pipeline_reg_39;
output [WIDTH-1:0] pipeline_reg_40;
output [WIDTH-1:0] pipeline_reg_41;
output [WIDTH-1:0] pipeline_reg_42;
reg [WIDTH-1:0] pipeline_reg_0;
reg [WIDTH-1:0] pipeline_reg_1;
reg [WIDTH-1:0] pipeline_reg_2;
reg [WIDTH-1:0] pipeline_reg_3;
reg [WIDTH-1:0] pipeline_reg_4;
reg [WIDTH-1:0] pipeline_reg_5;
reg [WIDTH-1:0] pipeline_reg_6;
reg [WIDTH-1:0] pipeline_reg_7;
reg [WIDTH-1:0] pipeline_reg_8;
reg [WIDTH-1:0] pipeline_reg_9;
reg [WIDTH-1:0] pipeline_reg_10;
reg [WIDTH-1:0] pipeline_reg_11;
reg [WIDTH-1:0] pipeline_reg_12;
reg [WIDTH-1:0] pipeline_reg_13;
reg [WIDTH-1:0] pipeline_reg_14;
reg [WIDTH-1:0] pipeline_reg_15;
reg [WIDTH-1:0] pipeline_reg_16;
reg [WIDTH-1:0] pipeline_reg_17;
reg [WIDTH-1:0] pipeline_reg_18;
reg [WIDTH-1:0] pipeline_reg_19;
reg [WIDTH-1:0] pipeline_reg_20;
reg [WIDTH-1:0] pipeline_reg_21;
reg [WIDTH-1:0] pipeline_reg_22;
reg [WIDTH-1:0] pipeline_reg_23;
reg [WIDTH-1:0] pipeline_reg_24;
reg [WIDTH-1:0] pipeline_reg_25;
reg [WIDTH-1:0] pipeline_reg_26;
reg [WIDTH-1:0] pipeline_reg_27;
reg [WIDTH-1:0] pipeline_reg_28;
reg [WIDTH-1:0] pipeline_reg_29;
reg [WIDTH-1:0] pipeline_reg_30;
reg [WIDTH-1:0] pipeline_reg_31;
reg [WIDTH-1:0] pipeline_reg_32;
reg [WIDTH-1:0] pipeline_reg_33;
reg [WIDTH-1:0] pipeline_reg_34;
reg [WIDTH-1:0] pipeline_reg_35;
reg [WIDTH-1:0] pipeline_reg_36;
reg [WIDTH-1:0] pipeline_reg_37;
reg [WIDTH-1:0] pipeline_reg_38;
reg [WIDTH-1:0] pipeline_reg_39;
reg [WIDTH-1:0] pipeline_reg_40;
reg [WIDTH-1:0] pipeline_reg_41;
reg [WIDTH-1:0] pipeline_reg_42;
input reset;
always@(posedge clk or posedge reset) begin
if(reset) begin
pipeline_reg_0 <= 0;
pipeline_reg_1 <= 0;
pipeline_reg_2 <= 0;
pipeline_reg_3 <= 0;
pipeline_reg_4 <= 0;
pipeline_reg_5 <= 0;
pipeline_reg_6 <= 0;
pipeline_reg_7 <= 0;
pipeline_reg_8 <= 0;
pipeline_reg_9 <= 0;
pipeline_reg_10 <= 0;
pipeline_reg_11 <= 0;
pipeline_reg_12 <= 0;
pipeline_reg_13 <= 0;
pipeline_reg_14 <= 0;
pipeline_reg_15 <= 0;
pipeline_reg_16 <= 0;
pipeline_reg_17 <= 0;
pipeline_reg_18 <= 0;
pipeline_reg_19 <= 0;
pipeline_reg_20 <= 0;
pipeline_reg_21 <= 0;
pipeline_reg_22 <= 0;
pipeline_reg_23 <= 0;
pipeline_reg_24 <= 0;
pipeline_reg_25 <= 0;
pipeline_reg_26 <= 0;
pipeline_reg_27 <= 0;
pipeline_reg_28 <= 0;
pipeline_reg_29 <= 0;
pipeline_reg_30 <= 0;
pipeline_reg_31 <= 0;
pipeline_reg_32 <= 0;
pipeline_reg_33 <= 0;
pipeline_reg_34 <= 0;
pipeline_reg_35 <= 0;
pipeline_reg_36 <= 0;
pipeline_reg_37 <= 0;
pipeline_reg_38 <= 0;
pipeline_reg_39 <= 0;
pipeline_reg_40 <= 0;
pipeline_reg_41 <= 0;
pipeline_reg_42 <= 0;
end else begin
if(clk_ena) begin
pipeline_reg_0 <= in_stream;
pipeline_reg_1 <= pipeline_reg_0;
pipeline_reg_2 <= pipeline_reg_1;
pipeline_reg_3 <= pipeline_reg_2;
pipeline_reg_4 <= pipeline_reg_3;
pipeline_reg_5 <= pipeline_reg_4;
pipeline_reg_6 <= pipeline_reg_5;
pipeline_reg_7 <= pipeline_reg_6;
pipeline_reg_8 <= pipeline_reg_7;
pipeline_reg_9 <= pipeline_reg_8;
pipeline_reg_10 <= pipeline_reg_9;
pipeline_reg_11 <= pipeline_reg_10;
pipeline_reg_12 <= pipeline_reg_11;
pipeline_reg_13 <= pipeline_reg_12;
pipeline_reg_14 <= pipeline_reg_13;
pipeline_reg_15 <= pipeline_reg_14;
pipeline_reg_16 <= pipeline_reg_15;
pipeline_reg_17 <= pipeline_reg_16;
pipeline_reg_18 <= pipeline_reg_17;
pipeline_reg_19 <= pipeline_reg_18;
pipeline_reg_20 <= pipeline_reg_19;
pipeline_reg_21 <= pipeline_reg_20;
pipeline_reg_22 <= pipeline_reg_21;
pipeline_reg_23 <= pipeline_reg_22;
pipeline_reg_24 <= pipeline_reg_23;
pipeline_reg_25 <= pipeline_reg_24;
pipeline_reg_26 <= pipeline_reg_25;
pipeline_reg_27 <= pipeline_reg_26;
pipeline_reg_28 <= pipeline_reg_27;
pipeline_reg_29 <= pipeline_reg_28;
pipeline_reg_30 <= pipeline_reg_29;
pipeline_reg_31 <= pipeline_reg_30;
pipeline_reg_32 <= pipeline_reg_31;
pipeline_reg_33 <= pipeline_reg_32;
pipeline_reg_34 <= pipeline_reg_33;
pipeline_reg_35 <= pipeline_reg_34;
pipeline_reg_36 <= pipeline_reg_35;
pipeline_reg_37 <= pipeline_reg_36;
pipeline_reg_38 <= pipeline_reg_37;
pipeline_reg_39 <= pipeline_reg_38;
pipeline_reg_40 <= pipeline_reg_39;
pipeline_reg_41 <= pipeline_reg_40;
pipeline_reg_42 <= pipeline_reg_41;
end //else begin
//pipeline_reg_0 <= pipeline_reg_0;
//pipeline_reg_1 <= pipeline_reg_1;
//pipeline_reg_2 <= pipeline_reg_2;
//pipeline_reg_3 <= pipeline_reg_3;
//pipeline_reg_4 <= pipeline_reg_4;
//pipeline_reg_5 <= pipeline_reg_5;
//pipeline_reg_6 <= pipeline_reg_6;
//pipeline_reg_7 <= pipeline_reg_7;
//pipeline_reg_8 <= pipeline_reg_8;
//pipeline_reg_9 <= pipeline_reg_9;
//pipeline_reg_10 <= pipeline_reg_10;
//pipeline_reg_11 <= pipeline_reg_11;
//pipeline_reg_12 <= pipeline_reg_12;
//pipeline_reg_13 <= pipeline_reg_13;
//pipeline_reg_14 <= pipeline_reg_14;
//pipeline_reg_15 <= pipeline_reg_15;
//pipeline_reg_16 <= pipeline_reg_16;
//pipeline_reg_17 <= pipeline_reg_17;
//pipeline_reg_18 <= pipeline_reg_18;
//pipeline_reg_19 <= pipeline_reg_19;
//pipeline_reg_20 <= pipeline_reg_20;
//pipeline_reg_21 <= pipeline_reg_21;
//pipeline_reg_22 <= pipeline_reg_22;
//pipeline_reg_23 <= pipeline_reg_23;
//pipeline_reg_24 <= pipeline_reg_24;
//pipeline_reg_25 <= pipeline_reg_25;
//pipeline_reg_26 <= pipeline_reg_26;
//pipeline_reg_27 <= pipeline_reg_27;
//pipeline_reg_28 <= pipeline_reg_28;
//pipeline_reg_29 <= pipeline_reg_29;
//pipeline_reg_30 <= pipeline_reg_30;
//pipeline_reg_31 <= pipeline_reg_31;
//pipeline_reg_32 <= pipeline_reg_32;
//pipeline_reg_33 <= pipeline_reg_33;
//pipeline_reg_34 <= pipeline_reg_34;
//pipeline_reg_35 <= pipeline_reg_35;
//pipeline_reg_36 <= pipeline_reg_36;
//pipeline_reg_37 <= pipeline_reg_37;
//pipeline_reg_38 <= pipeline_reg_38;
//pipeline_reg_39 <= pipeline_reg_39;
//pipeline_reg_40 <= pipeline_reg_40;
//pipeline_reg_41 <= pipeline_reg_41;
//pipeline_reg_42 <= pipeline_reg_42;
//end
end
end
endmodule
module adder_with_1_reg (
clk,
clk_ena,
dataa,
datab,
result);
input clk;
input clk_ena;
input [17:0] dataa;
input [17:0] datab;
output [17:0] result;
reg [17:0] result;
always @(posedge clk) begin
if(clk_ena) begin
result <= dataa + datab;
end
end
endmodule
module multiplier_with_reg (
clk,
clk_ena,
dataa,
datab,
result);
input clk;
input clk_ena;
input [17:0] dataa;
input [17:0] datab;
output [17:0] result;
reg [17:0] result;
always @(posedge clk) begin
if(clk_ena) begin
result <= dataa * datab;
end
end
endmodule
module one_register (
clk,
clk_ena,
dataa,
result);
input clk;
input clk_ena;
input [17:0] dataa;
output [17:0] result;
reg [17:0] result;
always @(posedge clk) begin
if(clk_ena) begin
result <= dataa;
end
end
endmodule
|
module etx_core(/*AUTOARG*/
// Outputs
tx_data_slow, tx_frame_slow, txrd_wait, txrr_wait, txwr_wait,
etx_cfg_access, etx_cfg_packet,
// Inputs
nreset, clk, tx_rd_wait, tx_wr_wait, txrd_access, txrd_packet,
txrd_full, txrr_access, txrr_packet, txrr_full, txwr_access,
txwr_packet, txwr_full, etx_cfg_wait
);
parameter AW = 32;
parameter DW = 32;
parameter PW = 104;
parameter RFAW = 6;
parameter ID = 12'h999;
//Clocks,reset,config
input nreset;
input clk;
//IO interface
output [63:0] tx_data_slow;
output [3:0] tx_frame_slow;
input tx_rd_wait;
input tx_wr_wait;
//TXRD
input txrd_access;
input [PW-1:0] txrd_packet;
output txrd_wait;
input txrd_full;//sysclk domain
//TXRR
input txrr_access;
input [PW-1:0] txrr_packet;
output txrr_wait;
input txrr_full;//sysclk domain
//TXWR
input txwr_access;
input [PW-1:0] txwr_packet;
output txwr_wait;
input txwr_full; //sysclk domain
//Configuration Interface (for ERX)
output etx_cfg_access;
output [PW-1:0] etx_cfg_packet;
input etx_cfg_wait;
//for status?
wire[15:0] tx_status;
// End of automatics
/*AUTOINPUT*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire burst_enable; // From etx_cfg of etx_cfg.v
wire cfg_access; // From etx_arbiter of etx_arbiter.v
wire cfg_mmu_access; // From etx_cfg of etx_cfg.v
wire [3:0] ctrlmode; // From etx_cfg of etx_cfg.v
wire ctrlmode_bypass; // From etx_cfg of etx_cfg.v
wire emmu_access; // From etx_mmu of emmu.v
wire [PW-1:0] emmu_packet; // From etx_mmu of emmu.v
wire etx_access; // From etx_arbiter of etx_arbiter.v
wire [PW-1:0] etx_packet; // From etx_arbiter of etx_arbiter.v
wire etx_rd_wait; // From etx_protocol of etx_protocol.v
wire etx_remap_access; // From etx_remap of etx_remap.v
wire [PW-1:0] etx_remap_packet; // From etx_remap of etx_remap.v
wire etx_wait; // From etx_protocol of etx_protocol.v
wire etx_wr_wait; // From etx_protocol of etx_protocol.v
wire [8:0] gpio_data; // From etx_cfg of etx_cfg.v
wire gpio_enable; // From etx_cfg of etx_cfg.v
wire mmu_enable; // From etx_cfg of etx_cfg.v
wire remap_enable; // From etx_cfg of etx_cfg.v
wire tx_access; // From etx_protocol of etx_protocol.v
wire tx_burst; // From etx_protocol of etx_protocol.v
wire tx_enable; // From etx_cfg of etx_cfg.v
// End of automatics
//##################################################################
//# ARBITER (SELECT BETWEEN TX, RX, RR)
//##################################################################
etx_arbiter #(.ID(ID))
etx_arbiter (
/*AUTOINST*/
// Outputs
.txwr_wait (txwr_wait),
.txrd_wait (txrd_wait),
.txrr_wait (txrr_wait),
.etx_access (etx_access),
.cfg_access (cfg_access),
.etx_packet (etx_packet[PW-1:0]),
// Inputs
.clk (clk),
.nreset (nreset),
.txwr_access (txwr_access),
.txwr_packet (txwr_packet[PW-1:0]),
.txrd_access (txrd_access),
.txrd_packet (txrd_packet[PW-1:0]),
.txrr_access (txrr_access),
.txrr_packet (txrr_packet[PW-1:0]),
.etx_wait (etx_wait),
.etx_cfg_wait (etx_cfg_wait));
//##################################################################
//# REMAPPING DESTINATION ADDRESS
//##################################################################
/*etx_remap AUTO_TEMPLATE (
.emesh_\(.*\)_in (etx_\1[]),
.emesh_\(.*\)_out (etx_remap_\1[]),
.remap_en (remap_enable),
);
*/
etx_remap etx_remap (
/*AUTOINST*/
// Outputs
.emesh_access_out(etx_remap_access), // Templated
.emesh_packet_out(etx_remap_packet[PW-1:0]), // Templated
// Inputs
.clk (clk),
.nreset (nreset),
.emesh_access_in(etx_access), // Templated
.emesh_packet_in(etx_packet[PW-1:0]), // Templated
.remap_en (remap_enable), // Templated
.etx_wait (etx_wait));
//##################################################################
//# TABLE LOOKUP ADDRESS TRANSLATION
//##################################################################
/*emmu AUTO_TEMPLATE (.reg_access (cfg_mmu_access),
.reg_packet (etx_packet[PW-1:0]),
.emesh_\(.*\)_in (etx_remap_\1[]),
.emesh_\(.*\)_out (emmu_\1[]),
.mmu_en (mmu_enable),
.\(.*\)_clk (clk),
.emesh_wait_in (etx_wait),
);
*/
emmu etx_mmu (.reg_rdata (), // not used (no readback from MMU)
/*AUTOINST*/
// Outputs
.emesh_access_out (emmu_access), // Templated
.emesh_packet_out (emmu_packet[PW-1:0]), // Templated
// Inputs
.wr_clk (clk), // Templated
.rd_clk (clk), // Templated
.nreset (nreset),
.mmu_en (mmu_enable), // Templated
.reg_access (cfg_mmu_access), // Templated
.reg_packet (etx_packet[PW-1:0]), // Templated
.emesh_access_in (etx_remap_access), // Templated
.emesh_packet_in (etx_remap_packet[PW-1:0]), // Templated
.emesh_wait_in (etx_wait)); // Templated
//##################################################################
//# ELINK PROTOCOL CONVERTER (104 bit-->64 bits)
//##################################################################
/*etx_protocol AUTO_TEMPLATE (
.etx_rd_wait (etx_rd_wait),
.etx_wr_wait (etx_wr_wait),
.etx_wait (etx_wait),
.etx_\(.*\) (emmu_\1[]),
);
*/
etx_protocol #(.ID(ID))
etx_protocol (
/*AUTOINST*/
// Outputs
.etx_rd_wait (etx_rd_wait), // Templated
.etx_wr_wait (etx_wr_wait), // Templated
.etx_wait (etx_wait), // Templated
.tx_burst (tx_burst),
.tx_access (tx_access),
.tx_data_slow (tx_data_slow[63:0]),
.tx_frame_slow (tx_frame_slow[3:0]),
// Inputs
.nreset (nreset),
.clk (clk),
.etx_access (emmu_access), // Templated
.etx_packet (emmu_packet[PW-1:0]), // Templated
.tx_enable (tx_enable),
.burst_enable (burst_enable),
.gpio_data (gpio_data[8:0]),
.gpio_enable (gpio_enable),
.ctrlmode_bypass (ctrlmode_bypass),
.ctrlmode (ctrlmode[3:0]),
.tx_rd_wait (tx_rd_wait),
.tx_wr_wait (tx_wr_wait));
//##################################################################
//# TX CONFIGURATION
//##################################################################
etx_cfg etx_cfg (.tx_status ({7'b0,
tx_burst,
tx_rd_wait,
tx_wr_wait,
txrr_wait,
txrd_wait,
txwr_wait,
txrr_full,
txrd_full,
txwr_full
}),
/*AUTOINST*/
// Outputs
.cfg_mmu_access (cfg_mmu_access),
.etx_cfg_access (etx_cfg_access),
.etx_cfg_packet (etx_cfg_packet[PW-1:0]),
.tx_enable (tx_enable),
.mmu_enable (mmu_enable),
.gpio_enable (gpio_enable),
.remap_enable (remap_enable),
.burst_enable (burst_enable),
.gpio_data (gpio_data[8:0]),
.ctrlmode (ctrlmode[3:0]),
.ctrlmode_bypass (ctrlmode_bypass),
// Inputs
.nreset (nreset),
.clk (clk),
.cfg_access (cfg_access),
.etx_access (etx_access),
.etx_packet (etx_packet[PW-1:0]),
.etx_wait (etx_wait));
endmodule // elink
// Local Variables:
// verilog-library-directories:("." "../../emmu/hdl" "../../memory/hdl" "../../common/hdl")
// End:
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of avfb_logic
//
// Generated
// by: wig
// on: Tue Apr 18 07:50:26 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bugver.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: avfb_logic.v,v 1.1 2006/04/19 07:33:13 wig Exp $
// $Date: 2006/04/19 07:33:13 $
// $Log: avfb_logic.v,v $
// Revision 1.1 2006/04/19 07:33:13 wig
// Updated/added testcase for 20060404c issue. Needs more work!
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.82 2006/04/13 13:31:52 wig Exp
//
// Generator: mix_0.pl Revision: 1.44 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of avfb_logic
//
// No user `defines in this module
`define top_rs_selclk_out2_par_c 'b0 // __I_VectorConv
module avfb_logic
//
// Generated module i_avfb_logic
//
(
top_rs_selclk_out2_par_go
);
// Generated Module Outputs:
output [4:0] top_rs_selclk_out2_par_go;
// Generated Wires:
wire [4:0] top_rs_selclk_out2_par_go;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire [4:0] top_rs_selclk_out2_par; // __W_PORT_SIGNAL_MAP_REQ
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
assign top_rs_selclk_out2_par[4:4] = `top_rs_selclk_out2_par_c;
assign top_rs_selclk_out2_par_go = top_rs_selclk_out2_par; // __I_O_BUS_PORT
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for i_avfb_top_rs
avfb_top_rs i_avfb_top_rs (
.selclk_out2_par_o(top_rs_selclk_out2_par)
);
// End of Generated Instance Port Map for i_avfb_top_rs
endmodule
//
// End of Generated Module rtl of avfb_logic
//
//
//!End of Module/s
// --------------------------------------------------------------
|
(** * Gen: Generalizing Induction Hypotheses *)
(* $Date: 2011-06-07 16:49:17 -0400 (Tue, 07 Jun 2011) $ *)
Require Export Poly.
(** In the previous chapter, we noticed the importance of
controlling the exact form of the induction hypothesis when
carrying out inductive proofs in Coq. In particular, we need to
be careful about which of the assumptions we move (using [intros])
from the goal to the context before invoking the [induction]
tactic. In this short chapter, we consider this point in a little
more depth and introduce one new tactic, called [generalize
dependent], that is sometimes useful in helping massage the
induction hypothesis into the required form.
First, let's review the basic issue. Suppose we want to show that
the [double] function is injective -- i.e., that it always maps
different arguments to different results. The way we _start_ this
proof is a little bit delicate: if we begin it with
intros n. induction n.
]]
all is well. But if we begin it with
intros n m. induction n.
we get stuck in the middle of the inductive case... *)
Theorem double_injective_FAILED : forall n m,
double n = double m ->
n = m.
Proof.
intros n m. induction n as [| n'].
Case "n = O". simpl. intros eq. destruct m as [| m'].
SCase "m = O". reflexivity.
SCase "m = S m'". inversion eq.
Case "n = S n'". intros eq. destruct m as [| m'].
SCase "m = O". inversion eq.
SCase "m = S m'".
assert (n' = m') as H.
SSCase "Proof of assertion".
(* Here we are stuck. We need the assertion in order to
rewrite the final goal (subgoal 2 at this point) to an
identity. But the induction hypothesis, [IHn'], does
not give us [n' = m'] -- there is an extra [S] in the
way -- so the assertion is not provable. *)
Admitted.
(** What went wrong?
The problem is that, at the point we invoke the induction
hypothesis, we have already introduced [m] into the context
-- intuitively, we have told Coq, "Let's consider some particular
[n] and [m]..." and we now have to prove that, if [double n =
double m] for _this particular_ [n] and [m], then [n = m].
The next tactic, [induction n] says to Coq: We are going to show
the goal by induction on [n]. That is, we are going to prove that
the proposition
- [P n] = "if [double n = double m], then [n = m]"
holds for all [n] by showing
- [P O]
(i.e., "if [double O = double m] then [O = m]")
- [P n -> P (S n)]
(i.e., "if [double n = double m] then [n = m]" implies "if
[double (S n) = double m] then [S n = m]").
If we look closely at the second statement, it is saying something
rather strange: it says that, for a _particular_ [m], if we know
- "if [double n = double m] then [n = m]"
then we can prove
- "if [double (S n) = double m] then [S n = m]".
To see why this is strange, let's think of a particular [m] --
say, [5]. The statement is then saying that, if we can prove
- [Q] = "if [double n = 10] then [n = 5]"
then we can prove
- [R] = "if [double (S n) = 10] then [S n = 5]".
But knowing [Q] doesn't give us any help with proving [R]! (If we
tried to prove [R] from [Q], we would say something like "Suppose
[double (S n) = 10]..." but then we'd be stuck: knowing that
[double (S n)] is [10] tells us nothing about whether [double n]
is [10], so [Q] is useless at this point.)
To summarize: Trying to carry out this proof by induction on [n]
when [m] is already in the context doesn't work because we are
trying to prove a relation involving _every_ [n] but just a
_single_ [m]. *)
(** The good proof of [double_injective] leaves [m] in the goal
statement at the point where the [induction] tactic is invoked on
[n]: *)
Theorem double_injective' : forall n m,
double n = double m ->
n = m.
Proof.
intros n. induction n as [| n'].
Case "n = O". simpl. intros m eq. destruct m as [| m'].
SCase "m = O". reflexivity.
SCase "m = S m'". inversion eq.
Case "n = S n'".
(* Notice that both the goal and the induction
hypothesis have changed: the goal asks us to prove
something more general (i.e., to prove the
statement for *every* [m]), but the IH is
correspondingly more flexible, allowing us to
choose any [m] we like when we apply the IH. *)
intros m eq.
(* Now we choose a particular [m] and introduce the
assumption that [double n = double m]. Since we
are doing a case analysis on [n], we need a case
analysis on [m] to keep the two "in sync." *)
destruct m as [| m'].
SCase "m = O". inversion eq. (* The 0 case is trivial *)
SCase "m = S m'".
(* At this point, since we are in the second
branch of the [destruct m], the [m'] mentioned
in the context at this point is actually the
predecessor of the one we started out talking
about. Since we are also in the [S] branch of
the induction, this is perfect: if we
instantiate the generic [m] in the IH with the
[m'] that we are talking about right now (this
instantiation is performed automatically by
[apply]), then [IHn'] gives us exactly what we
need to finish the proof. *)
assert (n' = m') as H.
SSCase "Proof of assertion". apply IHn'.
inversion eq. reflexivity.
rewrite -> H. reflexivity. Qed.
(** What this teaches us is that we need to be careful about using
induction to try to prove something too specific: If we're proving
a property of [n] and [m] by induction on [n], we may need to
leave [m] generic. *)
(** However, this strategy doesn't always apply directly; sometimes a
little rearrangement is needed. Suppose, for example, that we had
decided we wanted to prove [double_injective] by induction on [m]
instead of [n]. *)
Theorem double_injective_take2_FAILED : forall n m,
double n = double m ->
n = m.
Proof.
intros n m. induction m as [| m'].
Case "m = O". simpl. intros eq. destruct n as [| n'].
SCase "n = O". reflexivity.
SCase "n = S n'". inversion eq.
Case "m = S m'". intros eq. destruct n as [| n'].
SCase "n = O". inversion eq.
SCase "n = S n'".
assert (n' = m') as H.
SSCase "Proof of assertion".
(* Here we are stuck again, just like before. *)
Admitted.
(** The problem is that, to do induction on [m], we must first
introduce [n]. (If we simply say [induction m] without
introducing anything first, Coq will automatically introduce
[n] for us!) *)
(** What can we do about this? One possibility is to rewrite the
statement of the lemma so that [m] is quantified before [n]. This
will work, but it's not nice: We don't want to have to mangle the
statements of lemmas to fit the needs of a particular strategy for
proving them -- we want to state them in the most clear and
natural way. *)
(** What we can do instead is to first introduce all the
quantified variables and then _re-generalize_ one or more of
them, taking them out of the context and putting them back at
the beginning of the goal. The [generalize dependent] tactic
does this. *)
Theorem double_injective_take2 : forall n m,
double n = double m ->
n = m.
Proof.
intros n m.
(* [n] and [m] are both in the context *)
generalize dependent n.
(* Now [n] is back in the goal and we can do induction on
[m] and get a sufficiently general IH. *)
induction m as [| m'].
Case "m = O". simpl. intros n eq. destruct n as [| n'].
SCase "n = O". reflexivity.
SCase "n = S n'". inversion eq.
Case "m = S m'". intros n eq. destruct n as [| n'].
SCase "n = O". inversion eq.
SCase "n = S n'".
assert (n' = m') as H.
SSCase "Proof of assertion".
apply IHm'. inversion eq. reflexivity.
rewrite -> H. reflexivity. Qed.
(** Let's look at an informal proof of this theorem. Note that
the proposition we prove by induction leaves [n] quantified,
corresponding to the use of generalize dependent in our formal
proof.
_Theorem_: For any nats [n] and [m], if [double n = double m], then
[n = m].
_Proof_: Let [m] be a [nat]. We prove by induction on [m] that, for
any [n], if [double n = double m] then [n = m].
- First, suppose [m = 0], and suppose [n] is a number such
that [double n = double m]. We must show that [n = 0].
Since [m = 0], by the definition of [double] we have [double n =
0]. There are two cases to consider for [n]. If [n = 0] we are
done, since this is what we wanted to show. Otherwise, if [n = S
n'] for some [n'], we derive a contradiction: by the definition of
[double] we would have [n = S (S (double n'))], but this
contradicts the assumption that [double n = 0].
- Otherwise, suppose [m = S m'] and that [n] is again a number such
that [double n = double m]. We must show that [n = S m'], with
the induction hypothesis that for every number [s], if [double s =
double m'] then [s = m'].
By the fact that [m = S m'] and the definition of [double], we
have [double n = S (S (double m'))]. There are two cases to
consider for [n].
If [n = 0], then by definition [double n = 0], a contradiction.
Thus, we may assume that [n = S n'] for some [n'], and again by
the definition of [double] we have [S (S (double n')) = S (S
(double m'))], which implies by inversion that [double n' = double
m'].
Instantiating the induction hypothesis with [n'] thus allows us to
conclude that [n' = m'], and it follows immediately that [S n' = S
m']. Since [S n' = n] and [S m' = m], this is just what we wanted
to show. [] *)
(** **** Exercise: 3 stars, recommended (gen_dep_practice) *)
(** Carry out this proof by induction on [m]. *)
Theorem plus_n_n_injective_take2 : forall n m, n + n = m + m -> n = m.
Proof.
intros n m H.
generalize dependent n.
induction m as [| m'].
Case "m = 0".
intros n H. destruct n.
reflexivity.
inversion H.
Case "m = S m'".
intros n H. destruct n as [| n'].
inversion H.
assert (n' = m') as H1.
apply IHm'. inversion H.
rewrite <- plus_n_Sm in H1.
rewrite <- plus_n_Sm in H1.
inversion H1. reflexivity.
rewrite H1. reflexivity. Qed.
(** Now prove this by induction on [l]. *)
Theorem index_after_last: forall (n : nat) (X : Type) (l : list X),
length l = n ->
index (S n) l = None.
Proof.
intros n X l H.
generalize dependent n.
induction l as [| x l'].
Case "l = nil".
reflexivity.
Case "l = cons x l'".
intros n H. destruct n as [| n'].
inversion H.
apply IHl'. simpl in H. inversion H. reflexivity. Qed.
(** [] *)
(** **** Exercise: 3 stars, optional (index_after_last_informal) *)
(** Write an informal proof corresponding to your Coq proof
of [index_after_last]:
_Theorem_: For all sets [X], lists [l : list X], and numbers
[n], if [length l = n] then [index (S n) l = None].
_Proof_:
We proceed by induction on l. Consider first the case where
l is an empty list. We are then to prove:
forall n : nat, length [] = n -> index (S n) [] = None
which follows immediately from the definition.
Then we consider that l is not an empty list. Our induction
hypothesis is:
forall n : nat, length l' = n -> index (S n) l' = None
and we must prove:
forall n : nat, length (x :: l') = n -> index (S n) (x :: l') = None
We consider the cases where n is either zero or non-zero. If
zero, it leads to a contradiction. If non-zero we must show
that:
index (S (S n')) (x :: l') = None
We can apply the induction hypothesis here to yield our new
goal:
length l' = n
Now we must simplify the hypothesis for the non-zero case
mentioned above, which is:
length (x :: l') = S n'
Simplification leads to:
S (length l') = S n'
And by this we can prove the goal.
[] *)
(** **** Exercise: 3 stars (gen_dep_practice_opt) *)
(** Prove this by induction on [l]. *)
Theorem length_snoc''' : forall (n : nat) (X : Type)
(v : X) (l : list X),
length l = n -> length (snoc l v) = S n.
Proof.
intros n X v l H.
generalize dependent n.
induction l as [| x l'].
Case "l = nil".
intros n H. simpl in H. simpl. rewrite <- H. reflexivity.
Case "l = cons x l'".
intros n H. destruct n as [| n'].
inversion H.
simpl. simpl in H. inversion H. apply eq_remove_S.
rewrite H1. apply IHl'. apply H1. Qed.
(** [] *)
(** **** Exercise: 3 stars (app_length_cons) *)
(** Prove this by induction on [l1], without using [app_length]. *)
Theorem app_length_cons : forall (X : Type) (l1 l2 : list X)
(x : X) (n : nat),
length (l1 ++ (x :: l2)) = n -> S (length (l1 ++ l2)) = n.
Proof.
intros X l1 l2 x n.
generalize dependent n.
generalize dependent l2.
induction l1 as [| x1 l1'].
Case "l1 = nil".
intros l2 n H. simpl. simpl in H. apply H.
Case "l1 = cons x1 l1'".
intros l2 n H. simpl. destruct n as [| n'].
inversion H.
apply eq_remove_S. apply IHl1'.
simpl in H. inversion H. reflexivity. Qed.
Theorem app_length_cons_r : forall (X : Type) (l1 l2 : list X)
(x : X) (n : nat),
S (length (l1 ++ l2)) = n -> length (l1 ++ (x :: l2)) = n.
Proof.
intros X l1 l2 x n.
generalize dependent n.
generalize dependent l2.
induction l1 as [| x1 l1'].
Case "l1 = nil".
intros l2 n H. simpl. simpl in H. apply H.
Case "l1 = cons x1 l1'".
intros l2 n H. simpl. destruct n as [| n'].
inversion H.
apply eq_remove_S. apply IHl1'.
simpl in H. inversion H. reflexivity. Qed.
(** [] *)
(** **** Exercise: 4 stars, optional (app_length_twice) *)
(** Prove this by induction on [l], without using app_length. *)
(* Theorem app_length_distr : forall (X:Type) (x:X) (l:list X), *)
(* length (l ++ x :: l) = length l + length (x :: l). *)
(* Proof. *)
(* intros X x l. induction l as [| h l']. *)
(* Case "l = nil". reflexivity. *)
(* Case "l = cons h l'". *)
(* simpl. simpl in IHl'. apply eq_remove_S. *)
(* rewrite <- plus_n_Sm. rewrite <- IHl'. unfold length. simpl. *)
Theorem app_length_twice : forall (X:Type) (n:nat) (l:list X),
length l = n -> length (l ++ l) = n + n.
Proof.
intros X n l H.
generalize dependent n.
induction l as [| x l'].
Case "l = nil".
intros n H. inversion H. reflexivity.
Case "l = cons x l'".
intros n H. destruct n.
inversion H.
inversion H. simpl. apply IHl' in H1.
inversion H. rewrite H2. rewrite <- plus_n_Sm.
apply eq_remove_S.
apply app_length_cons_r.
apply eq_remove_S. apply H1. Qed.
(** [] *)
|
/*
Using two large case statements:
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| Module | Partition | Slices* | Slice Reg | LUTs | LUTRAM | BRAM/FIFO | DSP48A1 | BUFG | BUFIO | BUFR | DCM | PLL_ADV | Full Hierarchical |
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| eg_cnt/ | | 9/13 | 13/19 | 15/18 | 0/3 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | eg_cnt |
| +u_cntsh | | 4/4 | 6/6 | 3/3 | 3/3 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | eg_cnt/u_cntsh |
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Using one large case statement:
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| Module | Partition | Slices* | Slice Reg | LUTs | LUTRAM | BRAM/FIFO | DSP48A1 | BUFG | BUFIO | BUFR | DCM | PLL_ADV | Full Hierarchical |
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| eg_cnt/ | | 8/11 | 13/19 | 12/15 | 0/3 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | eg_cnt |
| +u_cntsh | | 3/3 | 6/6 | 3/3 | 3/3 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | eg_cnt/u_cntsh |
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
*/
module eg_cnt(
input clk,
input clk_en,
input rst,
input [14:0] eg_cnt,
input [2:0] state_IV,
input [5:0] rate_IV,
output reg [2:0] state_V,
output reg [5:0] rate_V,
output [2:0] cnt_V,
output reg sum_up
);
localparam ATTACK=3'd0, DECAY1=3'd1, DECAY2=3'd2, RELEASE=3'd7, HOLD=3'd3;
wire [2:0] cnt_out;
assign cnt_V = cnt_out;
reg lsb;
reg [2:0] cnt_in;
reg [3:0] mux_sel;
always @(*) begin
mux_sel = (state_IV == ATTACK && rate_IV[5:2]!=4'hf) ? (rate_IV[5:2]+4'd1): rate_IV[5:2];
case( mux_sel )
4'h0: lsb = eg_cnt[12];
4'h1: lsb = eg_cnt[11];
4'h2: lsb = eg_cnt[10];
4'h3: lsb = eg_cnt[ 9];
4'h4: lsb = eg_cnt[ 8];
4'h5: lsb = eg_cnt[ 7];
4'h6: lsb = eg_cnt[ 6];
4'h7: lsb = eg_cnt[ 5];
4'h8: lsb = eg_cnt[ 4];
4'h9: lsb = eg_cnt[ 3];
4'ha: lsb = eg_cnt[ 2];
4'hb: lsb = eg_cnt[ 1];
default: lsb = eg_cnt[ 0];
endcase
cnt_in =lsb!=cnt_out ? (cnt_out+3'd1) : cnt_out;
end
always @(posedge clk) if( clk_en ) begin
if( rst ) begin
state_V <= RELEASE;
rate_V <= 6'h1F; // should it be 6'h3F? TODO
//cnt_V<= 3'd0;
end
else begin
state_V <= state_IV;
rate_V <= rate_IV;
end
end
jt12_sh/*_rst*/ #( .width(3), .stages(24) ) u_cntsh(
.clk ( clk ),
.clk_en ( clk_en ),
// .rst ( rst ),
.din ( cnt_in ),
.drop ( cnt_out )
);
always @(posedge clk)
if( clk_en )
sum_up <= lsb!=cnt_out;
endmodule // eg_mux |
module test1 ( wire2, wire4 );
output [3:0] wire2;
output [16:0] wire4;
endmodule
// msg2099
module test_top;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire eq; // From test_rcv of test1.v
wire not_eq; // From test_foo of test1.v
wire [16:0] wire4; // From test_rcv of test1.v, ...
// End of automatics
/*
.wire2 (@"(if (equal \\"@\\" \\"rcv\\") \\"eq\\" \\"not_eq\\" )"),
*/
/* test1 AUTO_TEMPLATE "test_\(.*\)" (
.wire2\(\) (@"(if (equal \\"@\\" \\"rcv\\") \\"eq\\" \\"not_eq\\" )"),
); */
test1 test_rcv (/*AUTOINST*/
// Outputs
.wire2 (eq), // Templated
.wire4 (wire4[16:0]));
test1 test_foo (/*AUTOINST*/
// Outputs
.wire2 (not_eq), // Templated
.wire4 (wire4[16:0]));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__TAP_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__TAP_PP_BLACKBOX_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__tap (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__TAP_PP_BLACKBOX_V
|
/*
Copyright (c) 2014-2021 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* FPGA top-level module
*/
module fpga (
/*
* Reset: Push button, active low
*/
input wire reset,
/*
* GPIO
*/
input wire [3:0] sw,
output wire [2:0] led,
/*
* I2C for board management
*/
inout wire i2c_scl,
inout wire i2c_sda,
/*
* Ethernet: QSFP28
*/
output wire qsfp0_tx1_p,
output wire qsfp0_tx1_n,
input wire qsfp0_rx1_p,
input wire qsfp0_rx1_n,
output wire qsfp0_tx2_p,
output wire qsfp0_tx2_n,
input wire qsfp0_rx2_p,
input wire qsfp0_rx2_n,
output wire qsfp0_tx3_p,
output wire qsfp0_tx3_n,
input wire qsfp0_rx3_p,
input wire qsfp0_rx3_n,
output wire qsfp0_tx4_p,
output wire qsfp0_tx4_n,
input wire qsfp0_rx4_p,
input wire qsfp0_rx4_n,
// input wire qsfp0_mgt_refclk_0_p,
// input wire qsfp0_mgt_refclk_0_n,
input wire qsfp0_mgt_refclk_1_p,
input wire qsfp0_mgt_refclk_1_n,
output wire qsfp0_modsell,
output wire qsfp0_resetl,
input wire qsfp0_modprsl,
input wire qsfp0_intl,
output wire qsfp0_lpmode,
output wire qsfp0_refclk_reset,
output wire [1:0] qsfp0_fs,
output wire qsfp1_tx1_p,
output wire qsfp1_tx1_n,
input wire qsfp1_rx1_p,
input wire qsfp1_rx1_n,
output wire qsfp1_tx2_p,
output wire qsfp1_tx2_n,
input wire qsfp1_rx2_p,
input wire qsfp1_rx2_n,
output wire qsfp1_tx3_p,
output wire qsfp1_tx3_n,
input wire qsfp1_rx3_p,
input wire qsfp1_rx3_n,
output wire qsfp1_tx4_p,
output wire qsfp1_tx4_n,
input wire qsfp1_rx4_p,
input wire qsfp1_rx4_n,
// input wire qsfp1_mgt_refclk_0_p,
// input wire qsfp1_mgt_refclk_0_n,
input wire qsfp1_mgt_refclk_1_p,
input wire qsfp1_mgt_refclk_1_n,
output wire qsfp1_modsell,
output wire qsfp1_resetl,
input wire qsfp1_modprsl,
input wire qsfp1_intl,
output wire qsfp1_lpmode,
output wire qsfp1_refclk_reset,
output wire [1:0] qsfp1_fs,
/*
* UART: 500000 bps, 8N1
*/
output wire uart_rxd,
input wire uart_txd
);
// Clock and reset
wire cfgmclk_int;
wire clk_161mhz_ref_int;
// Internal 125 MHz clock
wire clk_125mhz_mmcm_out;
wire clk_125mhz_int;
wire rst_125mhz_int;
// Internal 156.25 MHz clock
wire clk_156mhz_int;
wire rst_156mhz_int;
wire mmcm_rst;
wire mmcm_locked;
wire mmcm_clkfb;
// MMCM instance
// 161.13 MHz in, 125 MHz out
// PFD range: 10 MHz to 500 MHz
// VCO range: 800 MHz to 1600 MHz
// M = 64, D = 11 sets Fvco = 937.5 MHz (in range)
// Divide by 7.5 to get output frequency of 125 MHz
MMCME4_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKOUT0_DIVIDE_F(7.5),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(0),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT6_PHASE(0),
.CLKFBOUT_MULT_F(64),
.CLKFBOUT_PHASE(0),
.DIVCLK_DIVIDE(11),
.REF_JITTER1(0.010),
.CLKIN1_PERIOD(6.206),
.STARTUP_WAIT("FALSE"),
.CLKOUT4_CASCADE("FALSE")
)
clk_mmcm_inst (
.CLKIN1(clk_161mhz_ref_int),
.CLKFBIN(mmcm_clkfb),
.RST(mmcm_rst),
.PWRDWN(1'b0),
.CLKOUT0(clk_125mhz_mmcm_out),
.CLKOUT0B(),
.CLKOUT1(),
.CLKOUT1B(),
.CLKOUT2(),
.CLKOUT2B(),
.CLKOUT3(),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.CLKFBOUT(mmcm_clkfb),
.CLKFBOUTB(),
.LOCKED(mmcm_locked)
);
BUFG
clk_125mhz_bufg_inst (
.I(clk_125mhz_mmcm_out),
.O(clk_125mhz_int)
);
sync_reset #(
.N(4)
)
sync_reset_125mhz_inst (
.clk(clk_125mhz_int),
.rst(~mmcm_locked),
.out(rst_125mhz_int)
);
// GPIO
wire [3:0] sw_int;
debounce_switch #(
.WIDTH(4),
.N(4),
.RATE(156000)
)
debounce_switch_inst (
.clk(clk_156mhz_int),
.rst(rst_156mhz_int),
.in({sw}),
.out({sw_int})
);
wire uart_txd_int;
sync_signal #(
.WIDTH(1),
.N(2)
)
sync_signal_inst (
.clk(clk_156mhz_int),
.in({uart_txd}),
.out({uart_txd_int})
);
// SI570 I2C
wire i2c_scl_i;
wire i2c_scl_o = 1'b1;
wire i2c_scl_t = 1'b1;
wire i2c_sda_i;
wire i2c_sda_o = 1'b1;
wire i2c_sda_t = 1'b1;
assign i2c_scl_i = i2c_scl;
assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o;
assign i2c_sda_i = i2c_sda;
assign i2c_sda = i2c_sda_t ? 1'bz : i2c_sda_o;
// startupe3 instance
wire cfgmclk;
STARTUPE3
startupe3_inst (
.CFGCLK(),
.CFGMCLK(cfgmclk),
.DI(4'd0),
.DO(),
.DTS(1'b1),
.EOS(),
.FCSBO(1'b0),
.FCSBTS(1'b1),
.GSR(1'b0),
.GTS(1'b0),
.KEYCLEARB(1'b1),
.PACK(1'b0),
.PREQ(),
.USRCCLKO(1'b0),
.USRCCLKTS(1'b1),
.USRDONEO(1'b0),
.USRDONETS(1'b1)
);
BUFG
cfgmclk_bufg_inst (
.I(cfgmclk),
.O(cfgmclk_int)
);
// configure SI5335 clock generators
reg qsfp_refclk_reset_reg = 1'b1;
reg sys_reset_reg = 1'b1;
reg [9:0] reset_timer_reg = 0;
assign mmcm_rst = sys_reset_reg;
always @(posedge cfgmclk_int) begin
if (&reset_timer_reg) begin
if (qsfp_refclk_reset_reg) begin
qsfp_refclk_reset_reg <= 1'b0;
reset_timer_reg <= 0;
end else begin
qsfp_refclk_reset_reg <= 1'b0;
sys_reset_reg <= 1'b0;
end
end else begin
reset_timer_reg <= reset_timer_reg + 1;
end
if (!reset) begin
qsfp_refclk_reset_reg <= 1'b1;
sys_reset_reg <= 1'b1;
reset_timer_reg <= 0;
end
end
// XGMII 10G PHY
// QSFP0
assign qsfp0_modsell = 1'b0;
assign qsfp0_resetl = 1'b1;
assign qsfp0_lpmode = 1'b0;
assign qsfp0_refclk_reset = qsfp_refclk_reset_reg;
assign qsfp0_fs = 2'b10;
wire qsfp0_tx_clk_1_int;
wire qsfp0_tx_rst_1_int;
wire [63:0] qsfp0_txd_1_int;
wire [7:0] qsfp0_txc_1_int;
wire qsfp0_rx_clk_1_int;
wire qsfp0_rx_rst_1_int;
wire [63:0] qsfp0_rxd_1_int;
wire [7:0] qsfp0_rxc_1_int;
wire qsfp0_tx_clk_2_int;
wire qsfp0_tx_rst_2_int;
wire [63:0] qsfp0_txd_2_int;
wire [7:0] qsfp0_txc_2_int;
wire qsfp0_rx_clk_2_int;
wire qsfp0_rx_rst_2_int;
wire [63:0] qsfp0_rxd_2_int;
wire [7:0] qsfp0_rxc_2_int;
wire qsfp0_tx_clk_3_int;
wire qsfp0_tx_rst_3_int;
wire [63:0] qsfp0_txd_3_int;
wire [7:0] qsfp0_txc_3_int;
wire qsfp0_rx_clk_3_int;
wire qsfp0_rx_rst_3_int;
wire [63:0] qsfp0_rxd_3_int;
wire [7:0] qsfp0_rxc_3_int;
wire qsfp0_tx_clk_4_int;
wire qsfp0_tx_rst_4_int;
wire [63:0] qsfp0_txd_4_int;
wire [7:0] qsfp0_txc_4_int;
wire qsfp0_rx_clk_4_int;
wire qsfp0_rx_rst_4_int;
wire [63:0] qsfp0_rxd_4_int;
wire [7:0] qsfp0_rxc_4_int;
assign clk_156mhz_int = qsfp0_tx_clk_1_int;
assign rst_156mhz_int = qsfp0_tx_rst_1_int;
wire qsfp0_rx_block_lock_1;
wire qsfp0_rx_block_lock_2;
wire qsfp0_rx_block_lock_3;
wire qsfp0_rx_block_lock_4;
wire qsfp0_gtpowergood;
wire qsfp0_mgt_refclk_1;
wire qsfp0_mgt_refclk_1_int;
wire qsfp0_mgt_refclk_1_bufg;
assign clk_161mhz_ref_int = qsfp0_mgt_refclk_1_bufg;
IBUFDS_GTE4 ibufds_gte4_qsfp0_mgt_refclk_1_inst (
.I (qsfp0_mgt_refclk_1_p),
.IB (qsfp0_mgt_refclk_1_n),
.CEB (1'b0),
.O (qsfp0_mgt_refclk_1),
.ODIV2 (qsfp0_mgt_refclk_1_int)
);
BUFG_GT bufg_gt_refclk_inst (
.CE (qsfp0_gtpowergood),
.CEMASK (1'b1),
.CLR (1'b0),
.CLRMASK (1'b1),
.DIV (3'd0),
.I (qsfp0_mgt_refclk_1_int),
.O (qsfp0_mgt_refclk_1_bufg)
);
wire qsfp0_qpll0lock;
wire qsfp0_qpll0outclk;
wire qsfp0_qpll0outrefclk;
eth_xcvr_phy_wrapper #(
.HAS_COMMON(1)
)
qsfp0_phy_1_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(qsfp0_gtpowergood),
// PLL out
.xcvr_gtrefclk00_in(qsfp0_mgt_refclk_1),
.xcvr_qpll0lock_out(qsfp0_qpll0lock),
.xcvr_qpll0outclk_out(qsfp0_qpll0outclk),
.xcvr_qpll0outrefclk_out(qsfp0_qpll0outrefclk),
// PLL in
.xcvr_qpll0lock_in(1'b0),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(1'b0),
.xcvr_qpll0refclk_in(1'b0),
// Serial data
.xcvr_txp(qsfp0_tx1_p),
.xcvr_txn(qsfp0_tx1_n),
.xcvr_rxp(qsfp0_rx1_p),
.xcvr_rxn(qsfp0_rx1_n),
// PHY connections
.phy_tx_clk(qsfp0_tx_clk_1_int),
.phy_tx_rst(qsfp0_tx_rst_1_int),
.phy_xgmii_txd(qsfp0_txd_1_int),
.phy_xgmii_txc(qsfp0_txc_1_int),
.phy_rx_clk(qsfp0_rx_clk_1_int),
.phy_rx_rst(qsfp0_rx_rst_1_int),
.phy_xgmii_rxd(qsfp0_rxd_1_int),
.phy_xgmii_rxc(qsfp0_rxc_1_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp0_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0)
)
qsfp0_phy_2_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(qsfp0_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(qsfp0_qpll0outclk),
.xcvr_qpll0refclk_in(qsfp0_qpll0outrefclk),
// Serial data
.xcvr_txp(qsfp0_tx2_p),
.xcvr_txn(qsfp0_tx2_n),
.xcvr_rxp(qsfp0_rx2_p),
.xcvr_rxn(qsfp0_rx2_n),
// PHY connections
.phy_tx_clk(qsfp0_tx_clk_2_int),
.phy_tx_rst(qsfp0_tx_rst_2_int),
.phy_xgmii_txd(qsfp0_txd_2_int),
.phy_xgmii_txc(qsfp0_txc_2_int),
.phy_rx_clk(qsfp0_rx_clk_2_int),
.phy_rx_rst(qsfp0_rx_rst_2_int),
.phy_xgmii_rxd(qsfp0_rxd_2_int),
.phy_xgmii_rxc(qsfp0_rxc_2_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp0_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0)
)
qsfp0_phy_3_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(qsfp0_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(qsfp0_qpll0outclk),
.xcvr_qpll0refclk_in(qsfp0_qpll0outrefclk),
// Serial data
.xcvr_txp(qsfp0_tx3_p),
.xcvr_txn(qsfp0_tx3_n),
.xcvr_rxp(qsfp0_rx3_p),
.xcvr_rxn(qsfp0_rx3_n),
// PHY connections
.phy_tx_clk(qsfp0_tx_clk_3_int),
.phy_tx_rst(qsfp0_tx_rst_3_int),
.phy_xgmii_txd(qsfp0_txd_3_int),
.phy_xgmii_txc(qsfp0_txc_3_int),
.phy_rx_clk(qsfp0_rx_clk_3_int),
.phy_rx_rst(qsfp0_rx_rst_3_int),
.phy_xgmii_rxd(qsfp0_rxd_3_int),
.phy_xgmii_rxc(qsfp0_rxc_3_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp0_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0)
)
qsfp0_phy_4_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(qsfp0_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(qsfp0_qpll0outclk),
.xcvr_qpll0refclk_in(qsfp0_qpll0outrefclk),
// Serial data
.xcvr_txp(qsfp0_tx4_p),
.xcvr_txn(qsfp0_tx4_n),
.xcvr_rxp(qsfp0_rx4_p),
.xcvr_rxn(qsfp0_rx4_n),
// PHY connections
.phy_tx_clk(qsfp0_tx_clk_4_int),
.phy_tx_rst(qsfp0_tx_rst_4_int),
.phy_xgmii_txd(qsfp0_txd_4_int),
.phy_xgmii_txc(qsfp0_txc_4_int),
.phy_rx_clk(qsfp0_rx_clk_4_int),
.phy_rx_rst(qsfp0_rx_rst_4_int),
.phy_xgmii_rxd(qsfp0_rxd_4_int),
.phy_xgmii_rxc(qsfp0_rxc_4_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp0_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
// QSFP1
assign qsfp1_modsell = 1'b0;
assign qsfp1_resetl = 1'b1;
assign qsfp1_lpmode = 1'b0;
assign qsfp1_refclk_reset = qsfp_refclk_reset_reg;
assign qsfp1_fs = 2'b10;
wire qsfp1_tx_clk_1_int;
wire qsfp1_tx_rst_1_int;
wire [63:0] qsfp1_txd_1_int;
wire [7:0] qsfp1_txc_1_int;
wire qsfp1_rx_clk_1_int;
wire qsfp1_rx_rst_1_int;
wire [63:0] qsfp1_rxd_1_int;
wire [7:0] qsfp1_rxc_1_int;
wire qsfp1_tx_clk_2_int;
wire qsfp1_tx_rst_2_int;
wire [63:0] qsfp1_txd_2_int;
wire [7:0] qsfp1_txc_2_int;
wire qsfp1_rx_clk_2_int;
wire qsfp1_rx_rst_2_int;
wire [63:0] qsfp1_rxd_2_int;
wire [7:0] qsfp1_rxc_2_int;
wire qsfp1_tx_clk_3_int;
wire qsfp1_tx_rst_3_int;
wire [63:0] qsfp1_txd_3_int;
wire [7:0] qsfp1_txc_3_int;
wire qsfp1_rx_clk_3_int;
wire qsfp1_rx_rst_3_int;
wire [63:0] qsfp1_rxd_3_int;
wire [7:0] qsfp1_rxc_3_int;
wire qsfp1_tx_clk_4_int;
wire qsfp1_tx_rst_4_int;
wire [63:0] qsfp1_txd_4_int;
wire [7:0] qsfp1_txc_4_int;
wire qsfp1_rx_clk_4_int;
wire qsfp1_rx_rst_4_int;
wire [63:0] qsfp1_rxd_4_int;
wire [7:0] qsfp1_rxc_4_int;
wire qsfp1_rx_block_lock_1;
wire qsfp1_rx_block_lock_2;
wire qsfp1_rx_block_lock_3;
wire qsfp1_rx_block_lock_4;
wire qsfp1_mgt_refclk_1;
IBUFDS_GTE4 ibufds_gte4_qsfp1_mgt_refclk_1_inst (
.I (qsfp1_mgt_refclk_1_p),
.IB (qsfp1_mgt_refclk_1_n),
.CEB (1'b0),
.O (qsfp1_mgt_refclk_1),
.ODIV2 ()
);
wire qsfp1_qpll0lock;
wire qsfp1_qpll0outclk;
wire qsfp1_qpll0outrefclk;
eth_xcvr_phy_wrapper #(
.HAS_COMMON(1)
)
qsfp1_phy_1_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(qsfp1_mgt_refclk_1),
.xcvr_qpll0lock_out(qsfp1_qpll0lock),
.xcvr_qpll0outclk_out(qsfp1_qpll0outclk),
.xcvr_qpll0outrefclk_out(qsfp1_qpll0outrefclk),
// PLL in
.xcvr_qpll0lock_in(1'b0),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(1'b0),
.xcvr_qpll0refclk_in(1'b0),
// Serial data
.xcvr_txp(qsfp1_tx1_p),
.xcvr_txn(qsfp1_tx1_n),
.xcvr_rxp(qsfp1_rx1_p),
.xcvr_rxn(qsfp1_rx1_n),
// PHY connections
.phy_tx_clk(qsfp1_tx_clk_1_int),
.phy_tx_rst(qsfp1_tx_rst_1_int),
.phy_xgmii_txd(qsfp1_txd_1_int),
.phy_xgmii_txc(qsfp1_txc_1_int),
.phy_rx_clk(qsfp1_rx_clk_1_int),
.phy_rx_rst(qsfp1_rx_rst_1_int),
.phy_xgmii_rxd(qsfp1_rxd_1_int),
.phy_xgmii_rxc(qsfp1_rxc_1_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp1_rx_block_lock_1),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0)
)
qsfp1_phy_2_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(qsfp1_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(qsfp1_qpll0outclk),
.xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk),
// Serial data
.xcvr_txp(qsfp1_tx2_p),
.xcvr_txn(qsfp1_tx2_n),
.xcvr_rxp(qsfp1_rx2_p),
.xcvr_rxn(qsfp1_rx2_n),
// PHY connections
.phy_tx_clk(qsfp1_tx_clk_2_int),
.phy_tx_rst(qsfp1_tx_rst_2_int),
.phy_xgmii_txd(qsfp1_txd_2_int),
.phy_xgmii_txc(qsfp1_txc_2_int),
.phy_rx_clk(qsfp1_rx_clk_2_int),
.phy_rx_rst(qsfp1_rx_rst_2_int),
.phy_xgmii_rxd(qsfp1_rxd_2_int),
.phy_xgmii_rxc(qsfp1_rxc_2_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp1_rx_block_lock_2),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0)
)
qsfp1_phy_3_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(qsfp1_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(qsfp1_qpll0outclk),
.xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk),
// Serial data
.xcvr_txp(qsfp1_tx3_p),
.xcvr_txn(qsfp1_tx3_n),
.xcvr_rxp(qsfp1_rx3_p),
.xcvr_rxn(qsfp1_rx3_n),
// PHY connections
.phy_tx_clk(qsfp1_tx_clk_3_int),
.phy_tx_rst(qsfp1_tx_rst_3_int),
.phy_xgmii_txd(qsfp1_txd_3_int),
.phy_xgmii_txc(qsfp1_txc_3_int),
.phy_rx_clk(qsfp1_rx_clk_3_int),
.phy_rx_rst(qsfp1_rx_rst_3_int),
.phy_xgmii_rxd(qsfp1_rxd_3_int),
.phy_xgmii_rxc(qsfp1_rxc_3_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp1_rx_block_lock_3),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
eth_xcvr_phy_wrapper #(
.HAS_COMMON(0)
)
qsfp1_phy_4_inst (
.xcvr_ctrl_clk(clk_125mhz_int),
.xcvr_ctrl_rst(rst_125mhz_int),
// Common
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(1'b0),
.xcvr_qpll0lock_out(),
.xcvr_qpll0outclk_out(),
.xcvr_qpll0outrefclk_out(),
// PLL in
.xcvr_qpll0lock_in(qsfp1_qpll0lock),
.xcvr_qpll0reset_out(),
.xcvr_qpll0clk_in(qsfp1_qpll0outclk),
.xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk),
// Serial data
.xcvr_txp(qsfp1_tx4_p),
.xcvr_txn(qsfp1_tx4_n),
.xcvr_rxp(qsfp1_rx4_p),
.xcvr_rxn(qsfp1_rx4_n),
// PHY connections
.phy_tx_clk(qsfp1_tx_clk_4_int),
.phy_tx_rst(qsfp1_tx_rst_4_int),
.phy_xgmii_txd(qsfp1_txd_4_int),
.phy_xgmii_txc(qsfp1_txc_4_int),
.phy_rx_clk(qsfp1_rx_clk_4_int),
.phy_rx_rst(qsfp1_rx_rst_4_int),
.phy_xgmii_rxd(qsfp1_rxd_4_int),
.phy_xgmii_rxc(qsfp1_rxc_4_int),
.phy_tx_bad_block(),
.phy_rx_error_count(),
.phy_rx_bad_block(),
.phy_rx_sequence_error(),
.phy_rx_block_lock(qsfp1_rx_block_lock_4),
.phy_rx_high_ber(),
.phy_tx_prbs31_enable(),
.phy_rx_prbs31_enable()
);
fpga_core
core_inst (
/*
* Clock: 156.25 MHz
* Synchronous reset
*/
.clk(clk_156mhz_int),
.rst(rst_156mhz_int),
/*
* GPIO
*/
.sw(sw_int),
.led(led),
/*
* Ethernet: QSFP28
*/
.qsfp0_tx_clk_1(qsfp0_tx_clk_1_int),
.qsfp0_tx_rst_1(qsfp0_tx_rst_1_int),
.qsfp0_txd_1(qsfp0_txd_1_int),
.qsfp0_txc_1(qsfp0_txc_1_int),
.qsfp0_rx_clk_1(qsfp0_rx_clk_1_int),
.qsfp0_rx_rst_1(qsfp0_rx_rst_1_int),
.qsfp0_rxd_1(qsfp0_rxd_1_int),
.qsfp0_rxc_1(qsfp0_rxc_1_int),
.qsfp0_tx_clk_2(qsfp0_tx_clk_2_int),
.qsfp0_tx_rst_2(qsfp0_tx_rst_2_int),
.qsfp0_txd_2(qsfp0_txd_2_int),
.qsfp0_txc_2(qsfp0_txc_2_int),
.qsfp0_rx_clk_2(qsfp0_rx_clk_2_int),
.qsfp0_rx_rst_2(qsfp0_rx_rst_2_int),
.qsfp0_rxd_2(qsfp0_rxd_2_int),
.qsfp0_rxc_2(qsfp0_rxc_2_int),
.qsfp0_tx_clk_3(qsfp0_tx_clk_3_int),
.qsfp0_tx_rst_3(qsfp0_tx_rst_3_int),
.qsfp0_txd_3(qsfp0_txd_3_int),
.qsfp0_txc_3(qsfp0_txc_3_int),
.qsfp0_rx_clk_3(qsfp0_rx_clk_3_int),
.qsfp0_rx_rst_3(qsfp0_rx_rst_3_int),
.qsfp0_rxd_3(qsfp0_rxd_3_int),
.qsfp0_rxc_3(qsfp0_rxc_3_int),
.qsfp0_tx_clk_4(qsfp0_tx_clk_4_int),
.qsfp0_tx_rst_4(qsfp0_tx_rst_4_int),
.qsfp0_txd_4(qsfp0_txd_4_int),
.qsfp0_txc_4(qsfp0_txc_4_int),
.qsfp0_rx_clk_4(qsfp0_rx_clk_4_int),
.qsfp0_rx_rst_4(qsfp0_rx_rst_4_int),
.qsfp0_rxd_4(qsfp0_rxd_4_int),
.qsfp0_rxc_4(qsfp0_rxc_4_int),
.qsfp1_tx_clk_1(qsfp1_tx_clk_1_int),
.qsfp1_tx_rst_1(qsfp1_tx_rst_1_int),
.qsfp1_txd_1(qsfp1_txd_1_int),
.qsfp1_txc_1(qsfp1_txc_1_int),
.qsfp1_rx_clk_1(qsfp1_rx_clk_1_int),
.qsfp1_rx_rst_1(qsfp1_rx_rst_1_int),
.qsfp1_rxd_1(qsfp1_rxd_1_int),
.qsfp1_rxc_1(qsfp1_rxc_1_int),
.qsfp1_tx_clk_2(qsfp1_tx_clk_2_int),
.qsfp1_tx_rst_2(qsfp1_tx_rst_2_int),
.qsfp1_txd_2(qsfp1_txd_2_int),
.qsfp1_txc_2(qsfp1_txc_2_int),
.qsfp1_rx_clk_2(qsfp1_rx_clk_2_int),
.qsfp1_rx_rst_2(qsfp1_rx_rst_2_int),
.qsfp1_rxd_2(qsfp1_rxd_2_int),
.qsfp1_rxc_2(qsfp1_rxc_2_int),
.qsfp1_tx_clk_3(qsfp1_tx_clk_3_int),
.qsfp1_tx_rst_3(qsfp1_tx_rst_3_int),
.qsfp1_txd_3(qsfp1_txd_3_int),
.qsfp1_txc_3(qsfp1_txc_3_int),
.qsfp1_rx_clk_3(qsfp1_rx_clk_3_int),
.qsfp1_rx_rst_3(qsfp1_rx_rst_3_int),
.qsfp1_rxd_3(qsfp1_rxd_3_int),
.qsfp1_rxc_3(qsfp1_rxc_3_int),
.qsfp1_tx_clk_4(qsfp1_tx_clk_4_int),
.qsfp1_tx_rst_4(qsfp1_tx_rst_4_int),
.qsfp1_txd_4(qsfp1_txd_4_int),
.qsfp1_txc_4(qsfp1_txc_4_int),
.qsfp1_rx_clk_4(qsfp1_rx_clk_4_int),
.qsfp1_rx_rst_4(qsfp1_rx_rst_4_int),
.qsfp1_rxd_4(qsfp1_rxd_4_int),
.qsfp1_rxc_4(qsfp1_rxc_4_int),
/*
* UART: 115200 bps, 8N1
*/
.uart_rxd(uart_rxd),
.uart_txd(uart_txd_int)
);
endmodule
`resetall
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O211A_1_V
`define SKY130_FD_SC_HS__O211A_1_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog wrapper for o211a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o211a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o211a_1 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o211a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o211a_1 (
X ,
A1,
A2,
B1,
C1
);
output X ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o211a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O211A_1_V
|
(** * UseAuto: Theory and Practice of Automation in Coq Proofs *)
(* Chapter written and maintained by Arthur Chargueraud *)
(** In a machine-checked proof, every single detail has to be
justified. This can result in huge proof scripts. Fortunately,
Coq comes with a proof-search mechanism and with several decision
procedures that enable the system to automatically synthesize
simple pieces of proof. Automation is very powerful when set up
appropriately. The purpose of this chapter is to explain the
basics of working of automation.
The chapter is organized in two parts. The first part focuses on a
general mechanism called "proof search." In short, proof search
consists in naively trying to apply lemmas and assumptions in all
possible ways. The second part describes "decision procedures",
which are tactics that are very good at solving proof obligations
that fall in some particular fragment of the logic of Coq.
Many of the examples used in this chapter consist of small lemmas
that have been made up to illustrate particular aspects of automation.
These examples are completely independent from the rest of the Software
Foundations course. This chapter also contains some bigger examples
which are used to explain how to use automation in realistic proofs.
These examples are taken from other chapters of the course (mostly
from STLC), and the proofs that we present make use of the tactics
from the library [LibTactics.v], which is presented in the chapter
[UseTactics]. *)
Require Import Coq.Arith.Arith.
Require Import Coq.Lists.List.
Import ListNotations.
Require Import SfLib.
Require Import Maps.
Require Import Stlc.
Require Import LibTactics.
(* ####################################################### *)
(** * Basic Features of Proof Search *)
(** The idea of proof search is to replace a sequence of tactics
applying lemmas and assumptions with a call to a single tactic,
for example [auto]. This form of proof automation saves a lot of
effort. It typically leads to much shorter proof scripts, and to
scripts that are typically more robust to change. If one makes a
little change to a definition, a proof that exploits automation
probably won't need to be modified at all. Of course, using too
much automation is a bad idea. When a proof script no longer
records the main arguments of a proof, it becomes difficult to fix
it when it gets broken after a change in a definition. Overall, a
reasonable use of automation is generally a big win, as it saves a
lot of time both in building proof scripts and in subsequently
maintaining those proof scripts. *)
(* ####################################################### *)
(** ** Strength of Proof Search *)
(** We are going to study four proof-search tactics: [auto], [eauto],
[iauto] and [jauto]. The tactics [auto] and [eauto] are builtin
in Coq. The tactic [iauto] is a shorthand for the builtin tactic
[try solve [intuition eauto]]. The tactic [jauto] is defined in
the library [LibTactics], and simply performs some preprocessing
of the goal before calling [eauto]. The goal of this chapter is
to explain the general principles of proof search and to give
rule of thumbs for guessing which of the four tactics mentioned
above is best suited for solving a given goal.
Proof search is a compromise between efficiency and
expressiveness, that is, a tradeoff between how complex goals the
tactic can solve and how much time the tactic requires for
terminating. The tactic [auto] builds proofs only by using the
basic tactics [reflexivity], [assumption], and [apply]. The tactic
[eauto] can also exploit [eapply]. The tactic [jauto] extends
[eauto] by being able to open conjunctions and existentials that
occur in the context. The tactic [iauto] is able to deal with
conjunctions, disjunctions, and negation in a quite clever way;
however it is not able to open existentials from the context.
Also, [iauto] usually becomes very slow when the goal involves
several disjunctions.
Note that proof search tactics never perform any rewriting
step (tactics [rewrite], [subst]), nor any case analysis on an
arbitrary data structure or property (tactics [destruct] and
[inversion]), nor any proof by induction (tactic [induction]). So,
proof search is really intended to automate the final steps from
the various branches of a proof. It is not able to discover the
overall structure of a proof. *)
(* ####################################################### *)
(** ** Basics *)
(** The tactic [auto] is able to solve a goal that can be proved
using a sequence of [intros], [apply], [assumption], and [reflexivity].
Two examples follow. The first one shows the ability for
[auto] to call [reflexivity] at any time. In fact, calling
[reflexivity] is always the first thing that [auto] tries to do. *)
Lemma solving_by_reflexivity :
2 + 3 = 5.
Proof. auto. Qed.
(** The second example illustrates a proof where a sequence of
two calls to [apply] are needed. The goal is to prove that
if [Q n] implies [P n] for any [n] and if [Q n] holds for any [n],
then [P 2] holds. *)
Lemma solving_by_apply : forall (P Q : nat->Prop),
(forall n, Q n -> P n) ->
(forall n, Q n) ->
P 2.
Proof. auto. Qed.
(** If we are interested to see which proof [auto] came up with,
one possibility is to look at the generated proof-term,
using the command:
[Print solving_by_apply.]
The proof term is:
[fun (P Q : nat -> Prop) (H : forall n : nat, Q n -> P n) (H0 : forall n : nat, Q n)
=> H 2 (H0 2)]
This essentially means that [auto] applied the hypothesis [H]
(the first one), and then applied the hypothesis [H0] (the
second one).
*)
(** The tactic [auto] can invoke [apply] but not [eapply]. So, [auto]
cannot exploit lemmas whose instantiation cannot be directly
deduced from the proof goal. To exploit such lemmas, one needs to
invoke the tactic [eauto], which is able to call [eapply].
In the following example, the first hypothesis asserts that [P n]
is true when [Q m] is true for some [m], and the goal is to prove
that [Q 1] implies [P 2]. This implication follows direction from
the hypothesis by instantiating [m] as the value [1]. The
following proof script shows that [eauto] successfully solves the
goal, whereas [auto] is not able to do so. *)
Lemma solving_by_eapply : forall (P Q : nat->Prop),
(forall n m, Q m -> P n) ->
Q 1 -> P 2.
Proof. auto. eauto. Qed.
(* ####################################################### *)
(** ** Conjunctions *)
(** So far, we've seen that [eauto] is stronger than [auto] in the
sense that it can deal with [eapply]. In the same way, we are going
to see how [jauto] and [iauto] are stronger than [auto] and [eauto]
in the sense that they provide better support for conjunctions. *)
(** The tactics [auto] and [eauto] can prove a goal of the form
[F /\ F'], where [F] and [F'] are two propositions, as soon as
both [F] and [F'] can be proved in the current context.
An example follows. *)
Lemma solving_conj_goal : forall (P : nat->Prop) (F : Prop),
(forall n, P n) -> F -> F /\ P 2.
Proof. auto. Qed.
(** However, when an assumption is a conjunction, [auto] and [eauto]
are not able to exploit this conjunction. It can be quite
surprising at first that [eauto] can prove very complex goals but
that it fails to prove that [F /\ F'] implies [F]. The tactics
[iauto] and [jauto] are able to decompose conjunctions from the context.
Here is an example. *)
Lemma solving_conj_hyp : forall (F F' : Prop),
F /\ F' -> F.
Proof. auto. eauto. jauto. (* or [iauto] *) Qed.
(** The tactic [jauto] is implemented by first calling a
pre-processing tactic called [jauto_set], and then calling
[eauto]. So, to understand how [jauto] works, one can directly
call the tactic [jauto_set]. *)
Lemma solving_conj_hyp' : forall (F F' : Prop),
F /\ F' -> F.
Proof. intros. jauto_set. eauto. Qed.
(** Next is a more involved goal that can be solved by [iauto] and
[jauto]. *)
Lemma solving_conj_more : forall (P Q R : nat->Prop) (F : Prop),
(F /\ (forall n m, (Q m /\ R n) -> P n)) ->
(F -> R 2) ->
Q 1 ->
P 2 /\ F.
Proof. jauto. (* or [iauto] *) Qed.
(** The strategy of [iauto] and [jauto] is to run a global analysis of
the top-level conjunctions, and then call [eauto]. For this
reason, those tactics are not good at dealing with conjunctions
that occur as the conclusion of some universally quantified
hypothesis. The following example illustrates a general weakness
of Coq proof search mechanisms. *)
Lemma solving_conj_hyp_forall : forall (P Q : nat->Prop),
(forall n, P n /\ Q n) -> P 2.
Proof.
auto. eauto. iauto. jauto.
(* Nothing works, so we have to do some of the work by hand *)
intros. destruct (H 2). auto.
Qed.
(** This situation is slightly disappointing, since automation is
able to prove the following goal, which is very similar. The
only difference is that the universal quantification has been
distributed over the conjunction. *)
Lemma solved_by_jauto : forall (P Q : nat->Prop) (F : Prop),
(forall n, P n) /\ (forall n, Q n) -> P 2.
Proof. jauto. (* or [iauto] *) Qed.
(* ####################################################### *)
(** ** Disjunctions *)
(** The tactics [auto] and [eauto] can handle disjunctions that
occur in the goal. *)
Lemma solving_disj_goal : forall (F F' : Prop),
F -> F \/ F'.
Proof. auto. Qed.
(** However, only [iauto] is able to automate reasoning on the
disjunctions that appear in the context. For example, [iauto] can
prove that [F \/ F'] entails [F' \/ F]. *)
Lemma solving_disj_hyp : forall (F F' : Prop),
F \/ F' -> F' \/ F.
Proof. auto. eauto. jauto. iauto. Qed.
(** More generally, [iauto] can deal with complex combinations of
conjunctions, disjunctions, and negations. Here is an example. *)
Lemma solving_tauto : forall (F1 F2 F3 : Prop),
((~F1 /\ F3) \/ (F2 /\ ~F3)) ->
(F2 -> F1) ->
(F2 -> F3) ->
~F2.
Proof. iauto. Qed.
(** However, the ability of [iauto] to automatically perform a case
analysis on disjunctions comes with a downside: [iauto] may be
very slow. If the context involves several hypotheses with
disjunctions, [iauto] typically generates an exponential number of
subgoals on which [eauto] is called. One major advantage of [jauto]
compared with [iauto] is that it never spends time performing this
kind of case analyses. *)
(* ####################################################### *)
(** ** Existentials *)
(** The tactics [eauto], [iauto], and [jauto] can prove goals whose
conclusion is an existential. For example, if the goal is [exists
x, f x], the tactic [eauto] introduces an existential variable,
say [?25], in place of [x]. The remaining goal is [f ?25], and
[eauto] tries to solve this goal, allowing itself to instantiate
[?25] with any appropriate value. For example, if an assumption [f
2] is available, then the variable [?25] gets instantiated with
[2] and the goal is solved, as shown below. *)
Lemma solving_exists_goal : forall (f : nat->Prop),
f 2 -> exists x, f x.
Proof.
auto. (* observe that [auto] does not deal with existentials, *)
eauto. (* whereas [eauto], [iauto] and [jauto] solve the goal *)
Qed.
(** A major strength of [jauto] over the other proof search tactics is
that it is able to exploit the existentially-quantified
hypotheses, i.e., those of the form [exists x, P]. *)
Lemma solving_exists_hyp : forall (f g : nat->Prop),
(forall x, f x -> g x) ->
(exists a, f a) ->
(exists a, g a).
Proof.
auto. eauto. iauto. (* All of these tactics fail, *)
jauto. (* whereas [jauto] succeeds. *)
(* For the details, run [intros. jauto_set. eauto] *)
Qed.
(* ####################################################### *)
(** ** Negation *)
(** The tactics [auto] and [eauto] suffer from some limitations with
respect to the manipulation of negations, mostly related to the
fact that negation, written [~ P], is defined as [P -> False] but
that the unfolding of this definition is not performed
automatically. Consider the following example. *)
Lemma negation_study_1 : forall (P : nat->Prop),
P 0 -> (forall x, ~ P x) -> False.
Proof.
intros P H0 HX.
eauto. (* It fails to see that [HX] applies *)
unfold not in *. eauto.
Qed.
(** For this reason, the tactics [iauto] and [jauto] systematically
invoke [unfold not in *] as part of their pre-processing. So,
they are able to solve the previous goal right away. *)
Lemma negation_study_2 : forall (P : nat->Prop),
P 0 -> (forall x, ~ P x) -> False.
Proof. jauto. (* or [iauto] *) Qed.
(** We will come back later on to the behavior of proof search with
respect to the unfolding of definitions. *)
(* ####################################################### *)
(** ** Equalities *)
(** Coq's proof-search feature is not good at exploiting equalities.
It can do very basic operations, like exploiting reflexivity
and symmetry, but that's about it. Here is a simple example
that [auto] can solve, by first calling [symmetry] and then
applying the hypothesis. *)
Lemma equality_by_auto : forall (f g : nat->Prop),
(forall x, f x = g x) -> g 2 = f 2.
Proof. auto. Qed.
(** To automate more advanced reasoning on equalities, one should
rather try to use the tactic [congruence], which is presented at
the end of this chapter in the "Decision Procedures" section. *)
(* ####################################################### *)
(** * How Proof Search Works *)
(* ####################################################### *)
(** ** Search Depth *)
(** The tactic [auto] works as follows. It first tries to call
[reflexivity] and [assumption]. If one of these calls solves the
goal, the job is done. Otherwise [auto] tries to apply the most
recently introduced assumption that can be applied to the goal
without producing and error. This application produces
subgoals. There are two possible cases. If the sugboals produced
can be solved by a recursive call to [auto], then the job is done.
Otherwise, if this application produces at least one subgoal that
[auto] cannot solve, then [auto] starts over by trying to apply
the second most recently introduced assumption. It continues in a
similar fashion until it finds a proof or until no assumption
remains to be tried.
It is very important to have a clear idea of the backtracking
process involved in the execution of the [auto] tactic; otherwise
its behavior can be quite puzzling. For example, [auto] is not
able to solve the following triviality. *)
Lemma search_depth_0 :
True /\ True /\ True /\ True /\ True /\ True.
Proof.
auto.
Abort.
(** The reason [auto] fails to solve the goal is because there are
too many conjunctions. If there had been only five of them, [auto]
would have successfully solved the proof, but six is too many.
The tactic [auto] limits the number of lemmas and hypotheses
that can be applied in a proof, so as to ensure that the proof
search eventually terminates. By default, the maximal number
of steps is five. One can specify a different bound, writing
for example [auto 6] to search for a proof involving at most
six steps. For example, [auto 6] would solve the previous lemma.
(Similarly, one can invoke [eauto 6] or [intuition eauto 6].)
The argument [n] of [auto n] is called the "search depth."
The tactic [auto] is simply defined as a shorthand for [auto 5].
The behavior of [auto n] can be summarized as follows. It first
tries to solve the goal using [reflexivity] and [assumption]. If
this fails, it tries to apply a hypothesis (or a lemma that has
been registered in the hint database), and this application
produces a number of sugoals. The tactic [auto (n-1)] is then
called on each of those subgoals. If all the subgoals are solved,
the job is completed, otherwise [auto n] tries to apply a
different hypothesis.
During the process, [auto n] calls [auto (n-1)], which in turn
might call [auto (n-2)], and so on. The tactic [auto 0] only
tries [reflexivity] and [assumption], and does not try to apply
any lemma. Overall, this means that when the maximal number of
steps allowed has been exceeded, the [auto] tactic stops searching
and backtracks to try and investigate other paths. *)
(** The following lemma admits a unique proof that involves exactly
three steps. So, [auto n] proves this goal iff [n] is greater than
three. *)
Lemma search_depth_1 : forall (P : nat->Prop),
P 0 ->
(P 0 -> P 1) ->
(P 1 -> P 2) ->
(P 2).
Proof.
auto 0. (* does not find the proof *)
auto 1. (* does not find the proof *)
auto 2. (* does not find the proof *)
auto 3. (* finds the proof *)
(* more generally, [auto n] solves the goal if [n >= 3] *)
Qed.
(** We can generalize the example by introducing an assumption
asserting that [P k] is derivable from [P (k-1)] for all [k],
and keep the assumption [P 0]. The tactic [auto], which is the
same as [auto 5], is able to derive [P k] for all values of [k]
less than 5. For example, it can prove [P 4]. *)
Lemma search_depth_3 : forall (P : nat->Prop),
(* Hypothesis H1: *) (P 0) ->
(* Hypothesis H2: *) (forall k, P (k-1) -> P k) ->
(* Goal: *) (P 4).
Proof. auto. Qed.
(** However, to prove [P 5], one needs to call at least [auto 6]. *)
Lemma search_depth_4 : forall (P : nat->Prop),
(* Hypothesis H1: *) (P 0) ->
(* Hypothesis H2: *) (forall k, P (k-1) -> P k) ->
(* Goal: *) (P 5).
Proof. auto. auto 6. Qed.
(** Because [auto] looks for proofs at a limited depth, there are
cases where [auto] can prove a goal [F] and can prove a goal
[F'] but cannot prove [F /\ F']. In the following example,
[auto] can prove [P 4] but it is not able to prove [P 4 /\ P 4],
because the splitting of the conjunction consumes one proof step.
To prove the conjunction, one needs to increase the search depth,
using at least [auto 6]. *)
Lemma search_depth_5 : forall (P : nat->Prop),
(* Hypothesis H1: *) (P 0) ->
(* Hypothesis H2: *) (forall k, P (k-1) -> P k) ->
(* Goal: *) (P 4 /\ P 4).
Proof. auto. auto 6. Qed.
(* ####################################################### *)
(** ** Backtracking *)
(** In the previous section, we have considered proofs where
at each step there was a unique assumption that [auto]
could apply. In general, [auto] can have several choices
at every step. The strategy of [auto] consists of trying all
of the possibilities (using a depth-first search exploration).
To illustrate how automation works, we are going to extend the
previous example with an additional assumption asserting that
[P k] is also derivable from [P (k+1)]. Adding this hypothesis
offers a new possibility that [auto] could consider at every step.
There exists a special command that one can use for tracing
all the steps that proof-search considers. To view such a
trace, one should write [debug eauto]. (For some reason, the
command [debug auto] does not exist, so we have to use the
command [debug eauto] instead.) *)
Lemma working_of_auto_1 : forall (P : nat->Prop),
(* Hypothesis H1: *) (P 0) ->
(* Hypothesis H2: *) (forall k, P (k-1) -> P k) ->
(* Hypothesis H3: *) (forall k, P (k+1) -> P k) ->
(* Goal: *) (P 2).
(* Uncomment "debug" in the following line to see the debug trace: *)
Proof. intros P H1 H2 H3. (* debug *) eauto. Qed.
(** The output message produced by [debug eauto] is as follows.
depth=5
depth=4 apply H2
depth=3 apply H2
depth=3 exact H1
The depth indicates the value of [n] with which [eauto n] is
called. The tactics shown in the message indicate that the first
thing that [eauto] has tried to do is to apply [H2]. The effect of
applying [H2] is to replace the goal [P 2] with the goal [P 1].
Then, again, [H2] has been applied, changing the goal [P 1] into
[P 0]. At that point, the goal was exactly the hypothesis [H1].
It seems that [eauto] was quite lucky there, as it never even
tried to use the hypothesis [H3] at any time. The reason is that
[auto] always tried to use the [H2] first. So, let's permute
the hypotheses [H2] and [H3] and see what happens. *)
Lemma working_of_auto_2 : forall (P : nat->Prop),
(* Hypothesis H1: *) (P 0) ->
(* Hypothesis H3: *) (forall k, P (k+1) -> P k) ->
(* Hypothesis H2: *) (forall k, P (k-1) -> P k) ->
(* Goal: *) (P 2).
Proof. intros P H1 H3 H2. (* debug *) eauto. Qed.
(** This time, the output message suggests that the proof search
investigates many possibilities. If we print the proof term:
[Print working_of_auto_2.]
we observe that the proof term refers to [H3]. Thus the proof
is not the simplest one, since only [H2] and [H1] are needed.
In turns out that the proof goes through the proof obligation [P 3],
even though it is not required to do so. The following tree drawing
describes all the goals that [eauto] has been going through.
|5||4||3||2||1||0| -- below, tabulation indicates the depth
[P 2]
-> [P 3]
-> [P 4]
-> [P 5]
-> [P 6]
-> [P 7]
-> [P 5]
-> [P 4]
-> [P 5]
-> [P 3]
--> [P 3]
-> [P 4]
-> [P 5]
-> [P 3]
-> [P 2]
-> [P 3]
-> [P 1]
-> [P 2]
-> [P 3]
-> [P 4]
-> [P 5]
-> [P 3]
-> [P 2]
-> [P 3]
-> [P 1]
-> [P 1]
-> [P 2]
-> [P 3]
-> [P 1]
-> [P 0]
-> !! Done !!
The first few lines read as follows. To prove [P 2], [eauto 5]
has first tried to apply [H3], producing the subgoal [P 3].
To solve it, [eauto 4] has tried again to apply [H3], producing
the goal [P 4]. Similarly, the search goes through [P 5], [P 6]
and [P 7]. When reaching [P 7], the tactic [eauto 0] is called
but as it is not allowed to try and apply any lemma, it fails.
So, we come back to the goal [P 6], and try this time to apply
hypothesis [H2], producing the subgoal [P 5]. Here again,
[eauto 0] fails to solve this goal.
The process goes on and on, until backtracking to [P 3] and trying
to apply [H3] three times in a row, going through [P 2] and [P 1]
and [P 0]. This search tree explains why [eauto] came up with a
proof term starting with an application of [H3]. *)
(* ####################################################### *)
(** ** Adding Hints *)
(** By default, [auto] (and [eauto]) only tries to apply the
hypotheses that appear in the proof context. There are two
possibilities for telling [auto] to exploit a lemma that have
been proved previously: either adding the lemma as an assumption
just before calling [auto], or adding the lemma as a hint, so
that it can be used by every calls to [auto].
The first possibility is useful to have [auto] exploit a lemma
that only serves at this particular point. To add the lemma as
hypothesis, one can type [generalize mylemma; intros], or simply
[lets: mylemma] (the latter requires [LibTactics.v]).
The second possibility is useful for lemmas that need to be
exploited several times. The syntax for adding a lemma as a hint
is [Hint Resolve mylemma]. For example, the lemma asserting than
any number is less than or equal to itself, [forall x, x <= x],
called [Le.le_refl] in the Coq standard library, can be added as a
hint as follows. *)
Hint Resolve Le.le_refl.
(** A convenient shorthand for adding all the constructors of an
inductive datatype as hints is the command [Hint Constructors
mydatatype].
Warning: some lemmas, such as transitivity results, should
not be added as hints as they would very badly affect the
performance of proof search. The description of this problem
and the presentation of a general work-around for transitivity
lemmas appear further on. *)
(* ####################################################### *)
(** ** Integration of Automation in Tactics *)
(** The library "LibTactics" introduces a convenient feature for
invoking automation after calling a tactic. In short, it suffices
to add the symbol star ([*]) to the name of a tactic. For example,
[apply* H] is equivalent to [apply H; auto_star], where [auto_star]
is a tactic that can be defined as needed.
The definition of [auto_star], which determines the meaning of the
star symbol, can be modified whenever needed. Simply write:
Ltac auto_star ::= a_new_definition.
Observe the use of [::=] instead of [:=], which indicates that the
tactic is being rebound to a new definition. So, the default
definition is as follows. *)
Ltac auto_star ::= try solve [ jauto ].
(** Nearly all standard Coq tactics and all the tactics from
"LibTactics" can be called with a star symbol. For example, one
can invoke [subst*], [destruct* H], [inverts* H], [lets* I: H x],
[specializes* H x], and so on... There are two notable exceptions.
The tactic [auto*] is just another name for the tactic
[auto_star]. And the tactic [apply* H] calls [eapply H] (or the
more powerful [applys H] if needed), and then calls [auto_star].
Note that there is no [eapply* H] tactic, use [apply* H]
instead. *)
(** In large developments, it can be convenient to use two degrees of
automation. Typically, one would use a fast tactic, like [auto],
and a slower but more powerful tactic, like [jauto]. To allow for
a smooth coexistence of the two form of automation, [LibTactics.v]
also defines a "tilde" version of tactics, like [apply~ H],
[destruct~ H], [subst~], [auto~] and so on. The meaning of the
tilde symbol is described by the [auto_tilde] tactic, whose
default implementation is [auto]. *)
Ltac auto_tilde ::= auto.
(** In the examples that follow, only [auto_star] is needed. *)
(** An alternative, possibly more efficient version of auto_star is the
following":
Ltac auto_star ::= try solve [ eassumption | auto | jauto ].
With the above definition, [auto_star] first tries to solve the
goal using the assumptions; if it fails, it tries using [auto],
and if this still fails, then it calls [jauto]. Even though
[jauto] is strictly stronger than [eassumption] and [auto], it
makes sense to call these tactics first, because, when the
succeed, they save a lot of time, and when they fail to prove
the goal, they fail very quickly.".
*)
(* ####################################################### *)
(** * Examples of Use of Automation *)
(** Let's see how to use proof search in practice on the main theorems
of the "Software Foundations" course, proving in particular
results such as determinism, preservation and progress. *)
(* ####################################################### *)
(** ** Determinism *)
Module DeterministicImp.
Require Import Imp.
(** Recall the original proof of the determinism lemma for the IMP
language, shown below. *)
Theorem ceval_deterministic: forall c st st1 st2,
c / st \\ st1 ->
c / st \\ st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2.
generalize dependent st2.
(induction E1); intros st2 E2; inversion E2; subst.
- (* E_Skip *) reflexivity.
- (* E_Ass *) reflexivity.
- (* E_Seq *)
assert (st' = st'0) as EQ1.
{ (* Proof of assertion *) apply IHE1_1; assumption. }
subst st'0.
apply IHE1_2. assumption.
(* E_IfTrue *)
- (* b1 reduces to true *)
apply IHE1. assumption.
- (* b1 reduces to false (contradiction) *)
rewrite H in H5. inversion H5.
(* E_IfFalse *)
- (* b1 reduces to true (contradiction) *)
rewrite H in H5. inversion H5.
- (* b1 reduces to false *)
apply IHE1. assumption.
(* E_WhileEnd *)
- (* b1 reduces to true *)
reflexivity.
- (* b1 reduces to false (contradiction) *)
rewrite H in H2. inversion H2.
(* E_WhileLoop *)
- (* b1 reduces to true (contradiction) *)
rewrite H in H4. inversion H4.
- (* b1 reduces to false *)
assert (st' = st'0) as EQ1.
{ (* Proof of assertion *) apply IHE1_1; assumption. }
subst st'0.
apply IHE1_2. assumption.
Qed.
(** Exercise: rewrite this proof using [auto] whenever possible.
(The solution uses [auto] 9 times.) *)
Theorem ceval_deterministic': forall c st st1 st2,
c / st \\ st1 ->
c / st \\ st2 ->
st1 = st2.
Proof.
(* FILL IN HERE *) admit.
Admitted.
(** In fact, using automation is not just a matter of calling [auto]
in place of one or two other tactics. Using automation is about
rethinking the organization of sequences of tactics so as to
minimize the effort involved in writing and maintaining the proof.
This process is eased by the use of the tactics from
[LibTactics.v]. So, before trying to optimize the way automation
is used, let's first rewrite the proof of determinism:
- use [introv H] instead of [intros x H],
- use [gen x] instead of [generalize dependent x],
- use [inverts H] instead of [inversion H; subst],
- use [tryfalse] to handle contradictions, and get rid of
the cases where [beval st b1 = true] and [beval st b1 = false]
both appear in the context,
- stop using [ceval_cases] to label subcases. *)
Theorem ceval_deterministic'': forall c st st1 st2,
c / st \\ st1 ->
c / st \\ st2 ->
st1 = st2.
Proof.
introv E1 E2. gen st2.
induction E1; intros; inverts E2; tryfalse.
- auto.
- auto.
- assert (st' = st'0). auto. subst. auto.
- auto.
- auto.
- auto.
- assert (st' = st'0). auto. subst. auto.
Qed.
(** To obtain a nice clean proof script, we have to remove the calls
[assert (st' = st'0)]. Such a tactic invokation is not nice
because it refers to some variables whose name has been
automatically generated. This kind of tactics tend to be very
brittle. The tactic [assert (st' = st'0)] is used to assert the
conclusion that we want to derive from the induction
hypothesis. So, rather than stating this conclusion explicitly, we
are going to ask Coq to instantiate the induction hypothesis,
using automation to figure out how to instantiate it. The tactic
[forwards], described in [LibTactics.v] precisely helps with
instantiating a fact. So, let's see how it works out on our
example. *)
Theorem ceval_deterministic''': forall c st st1 st2,
c / st \\ st1 ->
c / st \\ st2 ->
st1 = st2.
Proof.
(* Let's replay the proof up to the [assert] tactic. *)
introv E1 E2. gen st2.
induction E1; intros; inverts E2; tryfalse.
- auto.
- auto.
(* We duplicate the goal for comparing different proofs. *)
- dup 4.
(* The old proof: *)
+ assert (st' = st'0). apply IHE1_1. apply H1.
(* produces [H: st' = st'0]. *) skip.
(* The new proof, without automation: *)
+ forwards: IHE1_1. apply H1.
(* produces [H: st' = st'0]. *) skip.
(* The new proof, with automation: *)
+ forwards: IHE1_1. eauto.
(* produces [H: st' = st'0]. *) skip.
(* The new proof, with integrated automation: *)
+ forwards*: IHE1_1.
(* produces [H: st' = st'0]. *) skip.
Abort.
(** To polish the proof script, it remains to factorize the calls
to [auto], using the star symbol. The proof of determinism can then
be rewritten in only four lines, including no more than 10 tactics. *)
Theorem ceval_deterministic'''': forall c st st1 st2,
c / st \\ st1 ->
c / st \\ st2 ->
st1 = st2.
Proof.
introv E1 E2. gen st2.
induction E1; intros; inverts* E2; tryfalse.
- forwards*: IHE1_1. subst*.
- forwards*: IHE1_1. subst*.
Qed.
End DeterministicImp.
(* ####################################################### *)
(** ** Preservation for STLC *)
Module PreservationProgressStlc.
Require Import StlcProp.
Import STLC.
Import STLCProp.
(** Consider the proof of perservation of STLC, shown below.
This proof already uses [eauto] through the triple-dot
mechanism. *)
Theorem preservation : forall t t' T,
has_type empty t T ->
t ==> t' ->
has_type empty t' T.
Proof with eauto.
remember (@empty ty) as Gamma.
intros t t' T HT. generalize dependent t'.
(induction HT); intros t' HE; subst Gamma.
- (* T_Var *)
inversion HE.
- (* T_Abs *)
inversion HE.
- (* T_App *)
inversion HE; subst...
(* The ST_App1 and ST_App2 cases are immediate by induction, and
auto takes care of them *)
+ (* ST_AppAbs *)
apply substitution_preserves_typing with T11...
inversion HT1...
- (* T_True *)
inversion HE.
- (* T_False *)
inversion HE.
- (* T_If *)
inversion HE; subst...
Qed.
(** Exercise: rewrite this proof using tactics from [LibTactics]
and calling automation using the star symbol rather than the
triple-dot notation. More precisely, make use of the tactics
[inverts*] and [applys*] to call [auto*] after a call to
[inverts] or to [applys]. The solution is three lines long.*)
Theorem preservation' : forall t t' T,
has_type empty t T ->
t ==> t' ->
has_type empty t' T.
Proof.
(* FILL IN HERE *) admit.
Admitted.
(* ####################################################### *)
(** ** Progress for STLC *)
(** Consider the proof of the progress theorem. *)
Theorem progress : forall t T,
has_type empty t T ->
value t \/ exists t', t ==> t'.
Proof with eauto.
intros t T Ht.
remember (@empty ty) as Gamma.
(induction Ht); subst Gamma...
- (* T_Var *)
inversion H.
- (* T_App *)
right. destruct IHHt1...
+ (* t1 is a value *)
destruct IHHt2...
* (* t2 is a value *)
inversion H; subst; try solve by inversion.
exists ([x0:=t2]t)...
* (* t2 steps *)
destruct H0 as [t2' Hstp]. exists (tapp t1 t2')...
+ (* t1 steps *)
destruct H as [t1' Hstp]. exists (tapp t1' t2)...
- (* T_If *)
right. destruct IHHt1...
destruct t1; try solve by inversion...
inversion H. exists (tif x0 t2 t3)...
Qed.
(** Exercise: optimize the above proof.
Hint: make use of [destruct*] and [inverts*].
The solution consists of 10 short lines. *)
Theorem progress' : forall t T,
has_type empty t T ->
value t \/ exists t', t ==> t'.
Proof.
(* FILL IN HERE *) admit.
Admitted.
End PreservationProgressStlc.
(* ####################################################### *)
(** ** BigStep and SmallStep *)
Module Semantics.
Require Import Smallstep.
(** Consider the proof relating a small-step reduction judgment
to a big-step reduction judgment. *)
Theorem multistep__eval : forall t v,
normal_form_of t v -> exists n, v = C n /\ t \\ n.
Proof.
intros t v Hnorm.
unfold normal_form_of in Hnorm.
inversion Hnorm as [Hs Hnf]; clear Hnorm.
rewrite nf_same_as_value in Hnf. inversion Hnf. clear Hnf.
exists n. split. reflexivity.
induction Hs; subst.
- (* multi_refl *)
apply E_Const.
- (* multi_step *)
eapply step__eval. eassumption. apply IHHs. reflexivity.
Qed.
(** Our goal is to optimize the above proof. It is generally
easier to isolate inductions into separate lemmas. So,
we are going to first prove an intermediate result
that consists of the judgment over which the induction
is being performed. *)
(** Exercise: prove the following result, using tactics
[introv], [induction] and [subst], and [apply*].
The solution is 3 lines long. *)
Theorem multistep_eval_ind : forall t v,
t ==>* v -> forall n, C n = v -> t \\ n.
Proof.
(* FILL IN HERE *) admit.
Admitted.
(** Exercise: using the lemma above, simplify the proof of
the result [multistep__eval]. You should use the tactics
[introv], [inverts], [split*] and [apply*].
The solution is 2 lines long. *)
Theorem multistep__eval' : forall t v,
normal_form_of t v -> exists n, v = C n /\ t \\ n.
Proof.
(* FILL IN HERE *) admit.
Admitted.
(** If we try to combine the two proofs into a single one,
we will likely fail, because of a limitation of the
[induction] tactic. Indeed, this tactic looses
information when applied to a property whose arguments
are not reduced to variables, such as [t ==>* (C n)].
You will thus need to use the more powerful tactic called
[dependent induction]. This tactic is available only after
importing the [Program] library, as shown below. *)
Require Import Program.
(** Exercise: prove the lemma [multistep__eval] without invoking
the lemma [multistep_eval_ind], that is, by inlining the proof
by induction involved in [multistep_eval_ind], using the
tactic [dependent induction] instead of [induction].
The solution is 5 lines long. *)
Theorem multistep__eval'' : forall t v,
normal_form_of t v -> exists n, v = C n /\ t \\ n.
Proof.
(* FILL IN HERE *) admit.
Admitted.
End Semantics.
(* ####################################################### *)
(** ** Preservation for STLCRef *)
Module PreservationProgressReferences.
Require Import Coq.omega.Omega.
Require Import References.
Import STLCRef.
Hint Resolve store_weakening extends_refl.
(** The proof of preservation for [STLCRef] can be found in chapter
[References]. The optimized proof script is more than twice
shorter. The following material explains how to build the
optimized proof script. The resulting optimized proof script for
the preservation theorem appears afterwards. *)
Theorem preservation : forall ST t t' T st st',
has_type empty ST t T ->
store_well_typed ST st ->
t / st ==> t' / st' ->
exists ST',
(extends ST' ST /\
has_type empty ST' t' T /\
store_well_typed ST' st').
Proof.
(* old: [Proof. with eauto using store_weakening, extends_refl.]
new: [Proof.], and the two lemmas are registered as hints
before the proof of the lemma, possibly inside a section in
order to restrict the scope of the hints. *)
remember (@empty ty) as Gamma. introv Ht. gen t'.
(induction Ht); introv HST Hstep;
(* old: [subst; try (solve by inversion); inversion Hstep; subst;
try (eauto using store_weakening, extends_refl)]
new: [subst Gamma; inverts Hstep; eauto.]
We want to be more precise on what exactly we substitute,
and we do not want to call [try (solve by inversion)] which
is way to slow. *)
subst Gamma; inverts Hstep; eauto.
(* T_App *)
- (* ST_AppAbs *)
(* old:
exists ST. inversion Ht1; subst.
split; try split... eapply substitution_preserves_typing... *)
(* new: we use [inverts] in place of [inversion] and [splits] to
split the conjunction, and [applys*] in place of [eapply...] *)
exists ST. inverts Ht1. splits*. applys* substitution_preserves_typing.
- (* ST_App1 *)
(* old:
eapply IHHt1 in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'... *)
(* new: The tactic [eapply IHHt1 in H0...] applies [IHHt1] to [H0].
But [H0] is only thing that [IHHt1] could be applied to, so
there [eauto] can figure this out on its own. The tactic
[forwards] is used to instantiate all the arguments of [IHHt1],
producing existential variables and subgoals when needed. *)
forwards: IHHt1. eauto. eauto. eauto.
(* At this point, we need to decompose the hypothesis [H] that has
just been created by [forwards]. This is done by the first part
of the preprocessing phase of [jauto]. *)
jauto_set_hyps; intros.
(* It remains to decompose the goal, which is done by the second
part of the preprocessing phase of [jauto]. *)
jauto_set_goal; intros.
(* All the subgoals produced can then be solved by [eauto]. *)
eauto. eauto. eauto.
-(* ST_App2 *)
(* old:
eapply IHHt2 in H5...
inversion H5 as [ST' [Hext [Hty Hsty]]].
exists ST'... *)
(* new: this time, we need to call [forwards] on [IHHt2],
and we call [jauto] right away, by writing [forwards*],
proving the goal in a single tactic! *)
forwards*: IHHt2.
(* The same trick works for many of the other subgoals. *)
- forwards*: IHHt.
- forwards*: IHHt.
- forwards*: IHHt1.
- forwards*: IHHt2.
- forwards*: IHHt1.
- (* T_Ref *)
+ (* ST_RefValue *)
(* old:
exists (ST ++ T1::nil).
inversion HST; subst.
split.
apply extends_app.
split.
replace (TRef T1)
with (TRef (store_Tlookup (length st) (ST ++ T1::nil))).
apply T_Loc.
rewrite <- H. rewrite app_length, plus_comm. simpl. omega.
unfold store_Tlookup. rewrite <- H. rewrite app_nth2; try omega.
rewrite minus_diag. simpl. reflexivity.
apply store_well_typed_app; assumption. *)
(* new: In this proof case, we need to perform an inversion
without removing the hypothesis. The tactic [inverts keep]
serves exactly this purpose. *)
exists (ST ++ T1::nil). inverts keep HST. splits.
(* The proof of the first subgoal needs no change *)
apply extends_app.
(* For the second subgoal, we use the tactic [applys_eq] to avoid
a manual [replace] before [T_loc] can be applied. *)
applys_eq T_Loc 1.
(* To justify the inequality, there is no need to call [rewrite <- H],
because the tactic [omega] is able to exploit [H] on its own.
So, only the rewriting of [app_length] and the call to the
tactic [omega] remain, with a call to [simpl] to unfold the
definition of [app]. *)
rewrite app_length. simpl. omega.
(* The next proof case is hard to polish because it relies on the
lemma [app_nth1] whose statement is not automation-friendly.
We'll come back to this proof case further on. *)
unfold store_Tlookup. rewrite <- H. rewrite* app_nth2.
(* Last, we replace [apply ..; assumption] with [apply* ..] *)
rewrite minus_diag. simpl. reflexivity.
apply* store_well_typed_app.
- forwards*: IHHt.
- (* T_Deref *)
+ (* ST_DerefLoc *)
(* old:
exists ST. split; try split...
destruct HST as [_ Hsty].
replace T11 with (store_Tlookup l ST).
apply Hsty...
inversion Ht; subst... *)
(* new: we start by calling [exists ST] and [splits*]. *)
exists ST. splits*.
(* new: we replace [destruct HST as [_ Hsty]] by the following *)
lets [_ Hsty]: HST.
(* new: then we use the tactic [applys_eq] to avoid the need to
perform a manual [replace] before applying [Hsty]. *)
applys_eq* Hsty 1.
(* new: we then can call [inverts] in place of [inversion;subst] *)
inverts* Ht.
- forwards*: IHHt.
- (* T_Assign *)
+ (* ST_Assign *)
(* old:
exists ST. split; try split...
eapply assign_pres_store_typing...
inversion Ht1; subst... *)
(* new: simply using nicer tactics *)
exists ST. splits*. applys* assign_pres_store_typing. inverts* Ht1.
- forwards*: IHHt1.
- forwards*: IHHt2.
Qed.
(** Let's come back to the proof case that was hard to optimize.
The difficulty comes from the statement of [nth_eq_last], which
takes the form [nth (length l) (l ++ x::nil) d = x]. This lemma is
hard to exploit because its first argument, [length l], mentions
a list [l] that has to be exactly the same as the [l] occuring in
[snoc l x]. In practice, the first argument is often a natural
number [n] that is provably equal to [length l] yet that is not
syntactically equal to [length l]. There is a simple fix for
making [nth_eq_last] easy to apply: introduce the intermediate
variable [n] explicitly, so that the goal becomes
[nth n (snoc l x) d = x], with a premise asserting [n = length l]. *)
Lemma nth_eq_last' : forall (A : Type) (l : list A) (x d : A) (n : nat),
n = length l -> nth n (l ++ x::nil) d = x.
Proof. intros. subst. apply nth_eq_last. Qed.
(** The proof case for [ref] from the preservation theorem then
becomes much easier to prove, because [rewrite nth_eq_last']
now succeeds. *)
Lemma preservation_ref : forall (st:store) (ST : store_ty) T1,
length ST = length st ->
TRef T1 = TRef (store_Tlookup (length st) (ST ++ T1::nil)).
Proof.
intros. dup.
(* A first proof, with an explicit [unfold] *)
unfold store_Tlookup. rewrite* nth_eq_last'.
(* A second proof, with a call to [fequal] *)
fequal. symmetry. apply* nth_eq_last'.
Qed.
(** The optimized proof of preservation is summarized next. *)
Theorem preservation' : forall ST t t' T st st',
has_type empty ST t T ->
store_well_typed ST st ->
t / st ==> t' / st' ->
exists ST',
(extends ST' ST /\
has_type empty ST' t' T /\
store_well_typed ST' st').
Proof.
remember (@empty ty) as Gamma. introv Ht. gen t'.
induction Ht; introv HST Hstep; subst Gamma; inverts Hstep; eauto.
- exists ST. inverts Ht1. splits*. applys* substitution_preserves_typing.
- forwards*: IHHt1.
- forwards*: IHHt2.
- forwards*: IHHt.
- forwards*: IHHt.
- forwards*: IHHt1.
- forwards*: IHHt2.
- forwards*: IHHt1.
- exists (ST ++ T1::nil). inverts keep HST. splits.
apply extends_app.
applys_eq T_Loc 1.
rewrite app_length. simpl. omega.
unfold store_Tlookup. rewrite* nth_eq_last'.
apply* store_well_typed_app.
- forwards*: IHHt.
- exists ST. splits*. lets [_ Hsty]: HST.
applys_eq* Hsty 1. inverts* Ht.
- forwards*: IHHt.
- exists ST. splits*. applys* assign_pres_store_typing. inverts* Ht1.
- forwards*: IHHt1.
- forwards*: IHHt2.
Qed.
(* ####################################################### *)
(** ** Progress for STLCRef *)
(** The proof of progress for [STLCRef] can be found in chapter
[References]. The optimized proof script is, here again, about
half the length. *)
Theorem progress : forall ST t T st,
has_type empty ST t T ->
store_well_typed ST st ->
(value t \/ exists t', exists st', t / st ==> t' / st').
Proof.
introv Ht HST. remember (@empty ty) as Gamma.
induction Ht; subst Gamma; tryfalse; try solve [left*].
- right. destruct* IHHt1 as [K|].
inverts K; inverts Ht1.
destruct* IHHt2.
- right. destruct* IHHt as [K|].
inverts K; try solve [inverts Ht]. eauto.
- right. destruct* IHHt as [K|].
inverts K; try solve [inverts Ht]. eauto.
- right. destruct* IHHt1 as [K|].
inverts K; try solve [inverts Ht1].
destruct* IHHt2 as [M|].
inverts M; try solve [inverts Ht2]. eauto.
- right. destruct* IHHt1 as [K|].
inverts K; try solve [inverts Ht1]. destruct* n.
- right. destruct* IHHt.
- right. destruct* IHHt as [K|].
inverts K; inverts Ht as M.
inverts HST as N. rewrite* N in M.
- right. destruct* IHHt1 as [K|].
destruct* IHHt2.
inverts K; inverts Ht1 as M.
inverts HST as N. rewrite* N in M.
Qed.
End PreservationProgressReferences.
(* ####################################################### *)
(** ** Subtyping *)
Module SubtypingInversion.
Require Import Sub.
(** Consider the inversion lemma for typing judgment
of abstractions in a type system with subtyping. *)
Lemma abs_arrow : forall x S1 s2 T1 T2,
has_type empty (tabs x S1 s2) (TArrow T1 T2) ->
subtype T1 S1
/\ has_type (update empty x S1) s2 T2.
Proof with eauto.
intros x S1 s2 T1 T2 Hty.
apply typing_inversion_abs in Hty.
destruct Hty as [S2 [Hsub Hty]].
apply sub_inversion_arrow in Hsub.
destruct Hsub as [U1 [U2 [Heq [Hsub1 Hsub2]]]].
inversion Heq; subst...
Qed.
(** Exercise: optimize the proof script, using
[introv], [lets] and [inverts*]. In particular,
you will find it useful to replace the pattern
[apply K in H. destruct H as I] with [lets I: K H].
The solution is 4 lines. *)
Lemma abs_arrow' : forall x S1 s2 T1 T2,
has_type empty (tabs x S1 s2) (TArrow T1 T2) ->
subtype T1 S1
/\ has_type (update empty x S1) s2 T2.
Proof.
(* FILL IN HERE *) admit.
Admitted.
(** The lemma [substitution_preserves_typing] has already been used to
illustrate the working of [lets] and [applys] in chapter
[UseTactics]. Optimize further this proof using automation (with
the star symbol), and using the tactic [cases_if']. The solution
is 33 lines). *)
Lemma substitution_preserves_typing : forall Gamma x U v t S,
has_type (update Gamma x U) t S ->
has_type empty v U ->
has_type Gamma ([x:=v]t) S.
Proof.
(* FILL IN HERE *) admit.
Admitted.
End SubtypingInversion.
(* ####################################################### *)
(** * Advanced Topics in Proof Search *)
(* ####################################################### *)
(** ** Stating Lemmas in the Right Way *)
(** Due to its depth-first strategy, [eauto] can get exponentially
slower as the depth search increases, even when a short proof
exists. In general, to make proof search run reasonably fast, one
should avoid using a depth search greater than 5 or 6. Moreover,
one should try to minimize the number of applicable lemmas, and
usually put first the hypotheses whose proof usefully instantiates
the existential variables.
In fact, the ability for [eauto] to solve certain goals actually
depends on the order in which the hypotheses are stated. This point
is illustrated through the following example, in which [P] is
a property of natural numbers. This property is such that
[P n] holds for any [n] as soon as [P m] holds for at least one [m]
different from zero. The goal is to prove that [P 2] implies [P 1].
When the hypothesis about [P] is stated in the form
[forall n m, P m -> m <> 0 -> P n], then [eauto] works. However, with
[forall n m, m <> 0 -> P m -> P n], the tactic [eauto] fails. *)
Lemma order_matters_1 : forall (P : nat->Prop),
(forall n m, P m -> m <> 0 -> P n) -> P 2 -> P 1.
Proof.
eauto. (* Success *)
(* The proof: [intros P H K. eapply H. apply K. auto.] *)
Qed.
Lemma order_matters_2 : forall (P : nat->Prop),
(forall n m, m <> 0 -> P m -> P n) -> P 5 -> P 1.
Proof.
eauto. (* Failure *)
(* To understand why, let us replay the previous proof *)
intros P H K.
eapply H.
(* The application of [eapply] has left two subgoals,
[?X <> 0] and [P ?X], where [?X] is an existential variable. *)
(* Solving the first subgoal is easy for [eauto]: it suffices
to instantiate [?X] as the value [1], which is the simplest
value that satisfies [?X <> 0]. *)
eauto.
(* But then the second goal becomes [P 1], which is where we
started from. So, [eauto] gets stuck at this point. *)
Abort.
(** It is very important to understand that the hypothesis [forall n
m, P m -> m <> 0 -> P n] is eauto-friendly, whereas [forall n m, m
<> 0 -> P m -> P n] really isn't. Guessing a value of [m] for
which [P m] holds and then checking that [m <> 0] holds works well
because there are few values of [m] for which [P m] holds. So, it
is likely that [eauto] comes up with the right one. On the other
hand, guessing a value of [m] for which [m <> 0] and then checking
that [P m] holds does not work well, because there are many values
of [m] that satisfy [m <> 0] but not [P m]. *)
(* ####################################################### *)
(** ** Unfolding of Definitions During Proof-Search *)
(** The use of intermediate definitions is generally encouraged in a
formal development as it usually leads to more concise and more
readable statements. Yet, definitions can make it a little harder
to automate proofs. The problem is that it is not obvious for a
proof search mechanism to know when definitions need to be
unfolded. Note that a naive strategy that consists in unfolding
all definitions before calling proof search does not scale up to
large proofs, so we avoid it. This section introduces a few
techniques for avoiding to manually unfold definitions before
calling proof search. *)
(** To illustrate the treatment of definitions, let [P] be an abstract
property on natural numbers, and let [myFact] be a definition
denoting the proposition [P x] holds for any [x] less than or
equal to 3. *)
Axiom P : nat -> Prop.
Definition myFact := forall x, x <= 3 -> P x.
(** Proving that [myFact] under the assumption that [P x] holds for
any [x] should be trivial. Yet, [auto] fails to prove it unless we
unfold the definition of [myFact] explicitly. *)
Lemma demo_hint_unfold_goal_1 :
(forall x, P x) -> myFact.
Proof.
auto. (* Proof search doesn't know what to do, *)
unfold myFact. auto. (* unless we unfold the definition. *)
Qed.
(** To automate the unfolding of definitions that appear as proof
obligation, one can use the command [Hint Unfold myFact] to tell
Coq that it should always try to unfold [myFact] when [myFact]
appears in the goal. *)
Hint Unfold myFact.
(** This time, automation is able to see through the definition
of [myFact]. *)
Lemma demo_hint_unfold_goal_2 :
(forall x, P x) -> myFact.
Proof. auto. Qed.
(** However, the [Hint Unfold] mechanism only works for unfolding
definitions that appear in the goal. In general, proof search does
not unfold definitions from the context. For example, assume we
want to prove that [P 3] holds under the assumption that [True ->
myFact]. *)
Lemma demo_hint_unfold_context_1 :
(True -> myFact) -> P 3.
Proof.
intros.
auto. (* fails *)
unfold myFact in *. auto. (* succeeds *)
Qed.
(** There is actually one exception to the previous rule: a constant
occuring in an hypothesis is automatically unfolded if the
hypothesis can be directly applied to the current goal. For example,
[auto] can prove [myFact -> P 3], as illustrated below. *)
Lemma demo_hint_unfold_context_2 :
myFact -> P 3.
Proof. auto. Qed.
(* ####################################################### *)
(** ** Automation for Proving Absurd Goals *)
(** In this section, we'll see that lemmas concluding on a negation
are generally not useful as hints, and that lemmas whose
conclusion is [False] can be useful hints but having too many of
them makes proof search inefficient. We'll also see a practical
work-around to the efficiency issue. *)
(** Consider the following lemma, which asserts that a number
less than or equal to 3 is not greater than 3. *)
Parameter le_not_gt : forall x,
(x <= 3) -> ~ (x > 3).
(** Equivalently, one could state that a number greater than three is
not less than or equal to 3. *)
Parameter gt_not_le : forall x,
(x > 3) -> ~ (x <= 3).
(** In fact, both statements are equivalent to a third one stating
that [x <= 3] and [x > 3] are contradictory, in the sense that
they imply [False]. *)
Parameter le_gt_false : forall x,
(x <= 3) -> (x > 3) -> False.
(** The following investigation aim at figuring out which of the three
statments is the most convenient with respect to proof
automation. The following material is enclosed inside a [Section],
so as to restrict the scope of the hints that we are adding. In
other words, after the end of the section, the hints added within
the section will no longer be active.*)
Section DemoAbsurd1.
(** Let's try to add the first lemma, [le_not_gt], as hint,
and see whether we can prove that the proposition
[exists x, x <= 3 /\ x > 3] is absurd. *)
Hint Resolve le_not_gt.
Lemma demo_auto_absurd_1 :
(exists x, x <= 3 /\ x > 3) -> False.
Proof.
intros. jauto_set. (* decomposes the assumption *)
(* debug *) eauto. (* does not see that [le_not_gt] could apply *)
eapply le_not_gt. eauto. eauto.
Qed.
(** The lemma [gt_not_le] is symmetric to [le_not_gt], so it will not
be any better. The third lemma, [le_gt_false], is a more useful
hint, because it concludes on [False], so proof search will try to
apply it when the current goal is [False]. *)
Hint Resolve le_gt_false.
Lemma demo_auto_absurd_2 :
(exists x, x <= 3 /\ x > 3) -> False.
Proof.
dup.
(* detailed version: *)
intros. jauto_set. (* debug *) eauto.
(* short version: *)
jauto.
Qed.
(** In summary, a lemma of the form [H1 -> H2 -> False] is a much more
effective hint than [H1 -> ~ H2], even though the two statments
are equivalent up to the definition of the negation symbol [~]. *)
(** That said, one should be careful with adding lemmas whose
conclusion is [False] as hint. The reason is that whenever
reaching the goal [False], the proof search mechanism will
potentially try to apply all the hints whose conclusion is [False]
before applying the appropriate one. *)
End DemoAbsurd1.
(** Adding lemmas whose conclusion is [False] as hint can be, locally,
a very effective solution. However, this approach does not scale
up for global hints. For most practical applications, it is
reasonable to give the name of the lemmas to be exploited for
deriving a contradiction. The tactic [false H], provided by
[LibTactics] serves that purpose: [false H] replaces the goal
with [False] and calls [eapply H]. Its behavior is described next.
Observe that any of the three statements [le_not_gt], [gt_not_le]
or [le_gt_false] can be used. *)
Lemma demo_false : forall x,
(x <= 3) -> (x > 3) -> 4 = 5.
Proof.
intros. dup 4.
(* A failed proof: *)
- false. eapply le_gt_false.
+ auto. (* here, [auto] does not prove [?x <= 3] by using [H] but
by using the lemma [le_refl : forall x, x <= x]. *)
(* The second subgoal becomes [3 > 3], which is not provable. *)
+ skip.
(* A correct proof: *)
- false. eapply le_gt_false.
+ eauto. (* here, [eauto] uses [H], as expected, to prove [?x <= 3] *)
+ eauto. (* so the second subgoal becomes [x > 3] *)
(* The same proof using [false]: *)
- false le_gt_false. eauto. eauto.
(* The lemmas [le_not_gt] and [gt_not_le] work as well *)
- false le_not_gt. eauto. eauto.
Qed.
(** In the above example, [false le_gt_false; eauto] proves the goal,
but [false le_gt_false; auto] does not, because [auto] does not
correctly instantiate the existential variable. Note that [false*
le_gt_false] would not work either, because the star symbol tries
to call [auto] first. So, there are two possibilities for
completing the proof: either call [false le_gt_false; eauto], or
call [false* (le_gt_false 3)]. *)
(* ####################################################### *)
(** ** Automation for Transitivity Lemmas *)
(** Some lemmas should never be added as hints, because they would
very badly slow down proof search. The typical example is that of
transitivity results. This section describes the problem and
presents a general workaround.
Consider a subtyping relation, written [subtype S T], that relates
two object [S] and [T] of type [typ]. Assume that this relation
has been proved reflexive and transitive. The corresponding lemmas
are named [subtype_refl] and [subtype_trans]. *)
Parameter typ : Type.
Parameter subtype : typ -> typ -> Prop.
Parameter subtype_refl : forall T,
subtype T T.
Parameter subtype_trans : forall S T U,
subtype S T -> subtype T U -> subtype S U.
(** Adding reflexivity as hint is generally a good idea,
so let's add reflexivity of subtyping as hint. *)
Hint Resolve subtype_refl.
(** Adding transitivity as hint is generally a bad idea. To
understand why, let's add it as hint and see what happens.
Because we cannot remove hints once we've added them, we are going
to open a "Section," so as to restrict the scope of the
transitivity hint to that section. *)
Section HintsTransitivity.
Hint Resolve subtype_trans.
(** Now, consider the goal [forall S T, subtype S T], which clearly has
no hope of being solved. Let's call [eauto] on this goal. *)
Lemma transitivity_bad_hint_1 : forall S T,
subtype S T.
Proof.
intros. (* debug *) eauto. (* Investigates 106 applications... *)
Abort.
(** Note that after closing the section, the hint [subtype_trans]
is no longer active. *)
End HintsTransitivity.
(** In the previous example, the proof search has spent a lot of time
trying to apply transitivity and reflexivity in every possible
way. Its process can be summarized as follows. The first goal is
[subtype S T]. Since reflexivity does not apply, [eauto] invokes
transitivity, which produces two subgoals, [subtype S ?X] and
[subtype ?X T]. Solving the first subgoal, [subtype S ?X], is
straightforward, it suffices to apply reflexivity. This unifies
[?X] with [S]. So, the second sugoal, [subtype ?X T],
becomes [subtype S T], which is exactly what we started from...
The problem with the transitivity lemma is that it is applicable
to any goal concluding on a subtyping relation. Because of this,
[eauto] keeps trying to apply it even though it most often doesn't
help to solve the goal. So, one should never add a transitivity
lemma as a hint for proof search. *)
(** There is a general workaround for having automation to exploit
transitivity lemmas without giving up on efficiency. This workaround
relies on a powerful mechanism called "external hint." This
mechanism allows to manually describe the condition under which
a particular lemma should be tried out during proof search.
For the case of transitivity of subtyping, we are going to tell
Coq to try and apply the transitivity lemma on a goal of the form
[subtype S U] only when the proof context already contains an
assumption either of the form [subtype S T] or of the form
[subtype T U]. In other words, we only apply the transitivity
lemma when there is some evidence that this application might
help. To set up this "external hint," one has to write the
following. *)
Hint Extern 1 (subtype ?S ?U) =>
match goal with
| H: subtype S ?T |- _ => apply (@subtype_trans S T U)
| H: subtype ?T U |- _ => apply (@subtype_trans S T U)
end.
(** This hint declaration can be understood as follows.
- "Hint Extern" introduces the hint.
- The number "1" corresponds to a priority for proof search.
It doesn't matter so much what priority is used in practice.
- The pattern [subtype ?S ?U] describes the kind of goal on
which the pattern should apply. The question marks are used
to indicate that the variables [?S] and [?U] should be bound
to some value in the rest of the hint description.
- The construction [match goal with ... end] tries to recognize
patterns in the goal, or in the proof context, or both.
- The first pattern is [H: subtype S ?T |- _]. It indices that
the context should contain an hypothesis [H] of type
[subtype S ?T], where [S] has to be the same as in the goal,
and where [?T] can have any value.
- The symbol [|- _] at the end of [H: subtype S ?T |- _] indicates
that we do not impose further condition on how the proof
obligation has to look like.
- The branch [=> apply (@subtype_trans S T U)] that follows
indicates that if the goal has the form [subtype S U] and if
there exists an hypothesis of the form [subtype S T], then
we should try and apply transitivity lemma instantiated on
the arguments [S], [T] and [U]. (Note: the symbol [@] in front of
[subtype_trans] is only actually needed when the "Implicit Arguments"
feature is activated.)
- The other branch, which corresponds to an hypothesis of the form
[H: subtype ?T U] is symmetrical.
Note: the same external hint can be reused for any other transitive
relation, simply by renaming [subtype] into the name of that relation. *)
(** Let us see an example illustrating how the hint works. *)
Lemma transitivity_workaround_1 : forall T1 T2 T3 T4,
subtype T1 T2 -> subtype T2 T3 -> subtype T3 T4 -> subtype T1 T4.
Proof.
intros. (* debug *) eauto. (* The trace shows the external hint being used *)
Qed.
(** We may also check that the new external hint does not suffer from the
complexity blow up. *)
Lemma transitivity_workaround_2 : forall S T,
subtype S T.
Proof.
intros. (* debug *) eauto. (* Investigates 0 applications *)
Abort.
(* ####################################################### *)
(** * Decision Procedures *)
(** A decision procedure is able to solve proof obligations whose
statement admits a particular form. This section describes three
useful decision procedures. The tactic [omega] handles goals
involving arithmetic and inequalities, but not general
multiplications. The tactic [ring] handles goals involving
arithmetic, including multiplications, but does not support
inequalities. The tactic [congruence] is able to prove equalities
and inequalities by exploiting equalities available in the proof
context. *)
(* ####################################################### *)
(** ** Omega *)
(** The tactic [omega] supports natural numbers (type [nat]) as well as
integers (type [Z], available by including the module [ZArith]).
It supports addition, substraction, equalities and inequalities.
Before using [omega], one needs to import the module [Omega],
as follows. *)
Require Import Omega.
(** Here is an example. Let [x] and [y] be two natural numbers
(they cannot be negative). Assume [y] is less than 4, assume
[x+x+1] is less than [y], and assume [x] is not zero. Then,
it must be the case that [x] is equal to one. *)
Lemma omega_demo_1 : forall (x y : nat),
(y <= 4) -> (x + x + 1 <= y) -> (x <> 0) -> (x = 1).
Proof. intros. omega. Qed.
(** Another example: if [z] is the mean of [x] and [y], and if the
difference between [x] and [y] is at most [4], then the difference
between [x] and [z] is at most 2. *)
Lemma omega_demo_2 : forall (x y z : nat),
(x + y = z + z) -> (x - y <= 4) -> (x - z <= 2).
Proof. intros. omega. Qed.
(** One can proof [False] using [omega] if the mathematical facts
from the context are contradictory. In the following example,
the constraints on the values [x] and [y] cannot be all
satisfied in the same time. *)
Lemma omega_demo_3 : forall (x y : nat),
(x + 5 <= y) -> (y - x < 3) -> False.
Proof. intros. omega. Qed.
(** Note: [omega] can prove a goal by contradiction only if its
conclusion reduces to [False]. The tactic [omega] always fails
when the conclusion is an arbitrary proposition [P], even though
[False] implies any proposition [P] (by [ex_falso_quodlibet]). *)
Lemma omega_demo_4 : forall (x y : nat) (P : Prop),
(x + 5 <= y) -> (y - x < 3) -> P.
Proof.
intros.
(* Calling [omega] at this point fails with the message:
"Omega: Can't solve a goal with proposition variables" *)
(* So, one needs to replace the goal by [False] first. *)
false. omega.
Qed.
(* ####################################################### *)
(** ** Ring *)
(** Compared with [omega], the tactic [ring] adds support for
multiplications, however it gives up the ability to reason on
inequations. Moreover, it supports only integers (type [Z]) and
not natural numbers (type [nat]). Here is an example showing how
to use [ring]. *)
Module RingDemo.
Require Import ZArith.
Open Scope Z_scope.
(* Arithmetic symbols are now interpreted in [Z] *)
Lemma ring_demo : forall (x y z : Z),
x * (y + z) - z * 3 * x
= x * y - 2 * x * z.
Proof. intros. ring. Qed.
End RingDemo.
(* ####################################################### *)
(** ** Congruence *)
(** The tactic [congruence] is able to exploit equalities from the
proof context in order to automatically perform the rewriting
operations necessary to establish a goal. It is slightly more
powerful than the tactic [subst], which can only handle equalities
of the form [x = e] where [x] is a variable and [e] an
expression. *)
Lemma congruence_demo_1 :
forall (f : nat->nat->nat) (g h : nat->nat) (x y z : nat),
f (g x) (g y) = z ->
2 = g x ->
g y = h z ->
f 2 (h z) = z.
Proof. intros. congruence. Qed.
(** Moreover, [congruence] is able to exploit universally quantified
equalities, for example [forall a, g a = h a]. *)
Lemma congruence_demo_2 :
forall (f : nat->nat->nat) (g h : nat->nat) (x y z : nat),
(forall a, g a = h a) ->
f (g x) (g y) = z ->
g x = 2 ->
f 2 (h y) = z.
Proof. congruence. Qed.
(** Next is an example where [congruence] is very useful. *)
Lemma congruence_demo_4 : forall (f g : nat->nat),
(forall a, f a = g a) ->
f (g (g 2)) = g (f (f 2)).
Proof. congruence. Qed.
(** The tactic [congruence] is able to prove a contradiction if the
goal entails an equality that contradicts an inequality available
in the proof context. *)
Lemma congruence_demo_3 :
forall (f g h : nat->nat) (x : nat),
(forall a, f a = h a) ->
g x = f x ->
g x <> h x ->
False.
Proof. congruence. Qed.
(** One of the strengths of [congruence] is that it is a very fast
tactic. So, one should not hesitate to invoke it wherever it might
help. *)
(* ####################################################### *)
(** * Summary *)
(** Let us summarize the main automation tactics available.
- [auto] automatically applies [reflexivity], [assumption], and [apply].
- [eauto] moreover tries [eapply], and in particular can instantiate
existentials in the conclusion.
- [iauto] extends [eauto] with support for negation, conjunctions, and
disjunctions. However, its support for disjunction can make it
exponentially slow.
- [jauto] extends [eauto] with support for negation, conjunctions, and
existential at the head of hypothesis.
- [congruence] helps reasoning about equalities and inequalities.
- [omega] proves arithmetic goals with equalities and inequalities,
but it does not support multiplication.
- [ring] proves arithmetic goals with multiplications, but does not
support inequalities.
In order to set up automation appropriately, keep in mind the following
rule of thumbs:
- automation is all about balance: not enough automation makes proofs
not very robust on change, whereas too much automation makes proofs
very hard to fix when they break.
- if a lemma is not goal directed (i.e., some of its variables do not
occur in its conclusion), then the premises need to be ordered in
such a way that proving the first premises maximizes the chances of
correctly instantiating the variables that do not occur in the conclusion.
- a lemma whose conclusion is [False] should only be added as a local
hint, i.e., as a hint within the current section.
- a transitivity lemma should never be considered as hint; if automation
of transitivity reasoning is really necessary, an [Extern Hint] needs
to be set up.
- a definition usually needs to be accompanied with a [Hint Unfold].
Becoming a master in the black art of automation certainly requires
some investment, however this investment will pay off very quickly.
*)
(** $Date: 2016-05-24 14:00:08 -0400 (Tue, 24 May 2016) $ *)
|
// megafunction wizard: %ALTGX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: alt4gxb
// ============================================================
// File Name: altpcie_serdes_4sgx_x4d_gen1_16p.v
// Megafunction Name(s):
// alt4gxb
//
// Simulation Library Files(s):
// stratixiv_hssi
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 8.1 Internal Build 106 07/20/2008 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2008 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//alt4gxb CBX_AUTO_BLACKBOX="ALL" device_family="Stratix IV" elec_idle_infer_enable="false" enable_0ppm="false" equalizer_ctrl_a_setting=0 equalizer_ctrl_b_setting=0 equalizer_ctrl_c_setting=0 equalizer_ctrl_d_setting=0 equalizer_ctrl_v_setting=0 equalizer_dcgain_setting=1 gxb_analog_power="3.0v" gxb_powerdown_width=1 intended_device_speed_grade=2 loopback_mode="none" number_of_channels=4 number_of_quads=1 operation_mode="duplex" preemphasis_ctrl_1stposttap_setting=3 preemphasis_ctrl_2ndposttap_inv_setting="false" preemphasis_ctrl_2ndposttap_setting=0 preemphasis_ctrl_pretap_inv_setting="false" preemphasis_ctrl_pretap_setting=0 protocol="pcie" receiver_termination="OCT_100_OHMS" reconfig_dprio_mode=1 rx_8b_10b_mode="normal" rx_align_pattern="0101111100" rx_align_pattern_length=10 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="true" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_cdrctrl_enable="true" rx_channel_bonding="x4" rx_channel_width=16 rx_common_mode="0.82v" rx_cru_bandwidth_type="medium" rx_cru_data_rate=800 rx_cru_divide_by=2 rx_cru_inclock0_period=10000 rx_cru_m_divider=25 rx_cru_multiply_by=25 rx_cru_n_divider=2 rx_cru_pfd_clk_select=0 rx_cru_vco_post_scale_divider=2 rx_data_rate=2500 rx_data_rate_remainder=0 rx_datapath_protocol="pipe" rx_digitalreset_port_width=1 rx_dwidth_factor=2 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_force_signal_detect="true" rx_ppmselect=32 rx_rate_match_fifo_mode="normal" rx_rate_match_pattern1="11010000111010000011" rx_rate_match_pattern2="00101111000101111100" rx_rate_match_pattern_size=20 rx_run_length=40 rx_run_length_enable="true" rx_use_align_state_machine="true" rx_use_clkout="false" rx_use_coreclk="false" rx_use_cruclk="true" rx_use_deserializer_double_data_mode="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="true" rx_use_pipe8b10binvpolarity="true" rx_use_rate_match_pattern1_only="false" rx_word_aligner_num_byte=1 starting_channel_number=0 transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_analog_power="1.4v" tx_channel_bonding="x4" tx_channel_width=16 tx_common_mode="0.65v" tx_data_rate=2500 tx_data_rate_remainder=0 tx_digitalreset_port_width=1 tx_dwidth_factor=2 tx_enable_bit_reversal="false" tx_pll_bandwidth_type="high" tx_pll_clock_post_divider=1 tx_pll_data_rate=800 tx_pll_divide_by=2 tx_pll_inclk0_period=10000 tx_pll_m_divider=25 tx_pll_multiply_by=25 tx_pll_n_divider=2 tx_pll_pfd_clk_select=0 tx_pll_vco_post_scale_divider=2 tx_transmit_protocol="pipe" tx_use_coreclk="false" tx_use_double_data_mode="true" tx_use_serializer_double_data_mode="false" use_calibration_block="true" vod_ctrl_setting=4 cal_blk_clk coreclkout gxb_powerdown pipe8b10binvpolarity pipedatavalid pipeelecidle pipephydonestatus pipestatus pll_inclk pll_locked powerdn reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_cruclk rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_freqlocked rx_patterndetect rx_pll_locked rx_syncstatus tx_ctrlenable tx_datain tx_dataout tx_detectrxloop tx_digitalreset tx_forcedispcompliance tx_forceelecidle
//VERSION_BEGIN 8.1 cbx_alt4gxb 2008:07:18:07:31:37:SJ cbx_mgl 2008:07:11:15:23:48:SJ cbx_tgx 2008:05:29:12:23:14:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = stratixiv_hssi_calibration_block 1 stratixiv_hssi_clock_divider 1 stratixiv_hssi_cmu 1 stratixiv_hssi_pll 5 stratixiv_hssi_rx_pcs 4 stratixiv_hssi_rx_pma 4 stratixiv_hssi_tx_pcs 4 stratixiv_hssi_tx_pma 4
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module altpcie_serdes_4sgx_x4d_gen1_16p_alt4gxb_8vc9
(
cal_blk_clk,
coreclkout,
gxb_powerdown,
pipe8b10binvpolarity,
pipedatavalid,
pipeelecidle,
pipephydonestatus,
pipestatus,
pll_inclk,
pll_locked,
powerdn,
reconfig_clk,
reconfig_fromgxb,
reconfig_togxb,
rx_analogreset,
rx_cruclk,
rx_ctrldetect,
rx_datain,
rx_dataout,
rx_digitalreset,
rx_freqlocked,
rx_patterndetect,
rx_pll_locked,
rx_syncstatus,
tx_ctrlenable,
tx_datain,
tx_dataout,
tx_detectrxloop,
tx_digitalreset,
tx_forcedispcompliance,
tx_forceelecidle) /* synthesis synthesis_clearbox=1 */;
input cal_blk_clk;
output [0:0] coreclkout;
input [0:0] gxb_powerdown;
input [3:0] pipe8b10binvpolarity;
output [3:0] pipedatavalid;
output [3:0] pipeelecidle;
output [3:0] pipephydonestatus;
output [11:0] pipestatus;
input pll_inclk;
output [0:0] pll_locked;
input [7:0] powerdn;
input reconfig_clk;
output [0:0] reconfig_fromgxb;
input [2:0] reconfig_togxb;
input [0:0] rx_analogreset;
input [3:0] rx_cruclk;
output [7:0] rx_ctrldetect;
input [3:0] rx_datain;
output [63:0] rx_dataout;
input [0:0] rx_digitalreset;
output [3:0] rx_freqlocked;
output [7:0] rx_patterndetect;
output [3:0] rx_pll_locked;
output [7:0] rx_syncstatus;
input [7:0] tx_ctrlenable;
input [63:0] tx_datain;
output [3:0] tx_dataout;
input [3:0] tx_detectrxloop;
input [0:0] tx_digitalreset;
input [3:0] tx_forcedispcompliance;
input [3:0] tx_forceelecidle;
parameter starting_channel_number = 0;
wire wire_cal_blk0_nonusertocmu;
wire [1:0] wire_central_clk_div0_analogfastrefclkout;
wire [1:0] wire_central_clk_div0_analogrefclkout;
wire wire_central_clk_div0_analogrefclkpulse;
wire wire_central_clk_div0_coreclkout;
wire [99:0] wire_central_clk_div0_dprioout;
wire wire_central_clk_div0_rateswitchdone;
wire wire_central_clk_div0_refclkout;
wire [1:0] wire_cent_unit0_clkdivpowerdn;
wire [599:0] wire_cent_unit0_cmudividerdprioout;
wire [1799:0] wire_cent_unit0_cmuplldprioout;
wire wire_cent_unit0_dpriodisableout;
wire wire_cent_unit0_dprioout;
wire [1:0] wire_cent_unit0_pllpowerdn;
wire [1:0] wire_cent_unit0_pllresetout;
wire wire_cent_unit0_quadresetout;
wire [3:0] wire_cent_unit0_rxadcepowerdown;
wire [3:0] wire_cent_unit0_rxadceresetout;
wire [5:0] wire_cent_unit0_rxanalogresetout;
wire [5:0] wire_cent_unit0_rxcrupowerdown;
wire [5:0] wire_cent_unit0_rxcruresetout;
wire [3:0] wire_cent_unit0_rxdigitalresetout;
wire [5:0] wire_cent_unit0_rxibpowerdown;
wire [1599:0] wire_cent_unit0_rxpcsdprioout;
wire wire_cent_unit0_rxphfifox4byteselout;
wire wire_cent_unit0_rxphfifox4rdenableout;
wire wire_cent_unit0_rxphfifox4wrclkout;
wire wire_cent_unit0_rxphfifox4wrenableout;
wire [1799:0] wire_cent_unit0_rxpmadprioout;
wire [5:0] wire_cent_unit0_txanalogresetout;
wire [3:0] wire_cent_unit0_txctrlout;
wire [31:0] wire_cent_unit0_txdataout;
wire [5:0] wire_cent_unit0_txdetectrxpowerdown;
wire [3:0] wire_cent_unit0_txdigitalresetout;
wire [5:0] wire_cent_unit0_txobpowerdown;
wire [599:0] wire_cent_unit0_txpcsdprioout;
wire wire_cent_unit0_txphfifox4byteselout;
wire wire_cent_unit0_txphfifox4rdclkout;
wire wire_cent_unit0_txphfifox4rdenableout;
wire wire_cent_unit0_txphfifox4wrenableout;
wire [1799:0] wire_cent_unit0_txpmadprioout;
wire [3:0] wire_rx_cdr_pll0_clk;
wire [1:0] wire_rx_cdr_pll0_dataout;
wire [299:0] wire_rx_cdr_pll0_dprioout;
wire wire_rx_cdr_pll0_freqlocked;
wire wire_rx_cdr_pll0_locked;
wire wire_rx_cdr_pll0_pfdrefclkout;
wire [3:0] wire_rx_cdr_pll1_clk;
wire [1:0] wire_rx_cdr_pll1_dataout;
wire [299:0] wire_rx_cdr_pll1_dprioout;
wire wire_rx_cdr_pll1_freqlocked;
wire wire_rx_cdr_pll1_locked;
wire wire_rx_cdr_pll1_pfdrefclkout;
wire [3:0] wire_rx_cdr_pll2_clk;
wire [1:0] wire_rx_cdr_pll2_dataout;
wire [299:0] wire_rx_cdr_pll2_dprioout;
wire wire_rx_cdr_pll2_freqlocked;
wire wire_rx_cdr_pll2_locked;
wire wire_rx_cdr_pll2_pfdrefclkout;
wire [3:0] wire_rx_cdr_pll3_clk;
wire [1:0] wire_rx_cdr_pll3_dataout;
wire [299:0] wire_rx_cdr_pll3_dprioout;
wire wire_rx_cdr_pll3_freqlocked;
wire wire_rx_cdr_pll3_locked;
wire wire_rx_cdr_pll3_pfdrefclkout;
wire [3:0] wire_tx_pll0_clk;
wire [299:0] wire_tx_pll0_dprioout;
wire wire_tx_pll0_locked;
wire wire_receive_pcs0_cdrctrllocktorefclkout;
wire wire_receive_pcs0_coreclkout;
wire [3:0] wire_receive_pcs0_ctrldetect;
wire [39:0] wire_receive_pcs0_dataout;
wire [399:0] wire_receive_pcs0_dprioout;
wire [3:0] wire_receive_pcs0_patterndetect;
wire wire_receive_pcs0_phfifobyteserdisableout;
wire wire_receive_pcs0_phfifoptrsresetout;
wire wire_receive_pcs0_phfifordenableout;
wire wire_receive_pcs0_phfiforesetout;
wire wire_receive_pcs0_phfifowrdisableout;
wire wire_receive_pcs0_pipedatavalid;
wire wire_receive_pcs0_pipeelecidle;
wire wire_receive_pcs0_pipephydonestatus;
wire wire_receive_pcs0_pipestatetransdoneout;
wire [2:0] wire_receive_pcs0_pipestatus;
wire wire_receive_pcs0_rateswitchout;
wire [19:0] wire_receive_pcs0_revparallelfdbkdata;
wire [3:0] wire_receive_pcs0_syncstatus;
wire wire_receive_pcs1_cdrctrllocktorefclkout;
wire wire_receive_pcs1_coreclkout;
wire [3:0] wire_receive_pcs1_ctrldetect;
wire [39:0] wire_receive_pcs1_dataout;
wire [399:0] wire_receive_pcs1_dprioout;
wire [3:0] wire_receive_pcs1_patterndetect;
wire wire_receive_pcs1_phfifobyteserdisableout;
wire wire_receive_pcs1_phfifoptrsresetout;
wire wire_receive_pcs1_phfifordenableout;
wire wire_receive_pcs1_phfiforesetout;
wire wire_receive_pcs1_phfifowrdisableout;
wire wire_receive_pcs1_pipedatavalid;
wire wire_receive_pcs1_pipeelecidle;
wire wire_receive_pcs1_pipephydonestatus;
wire wire_receive_pcs1_pipestatetransdoneout;
wire [2:0] wire_receive_pcs1_pipestatus;
wire wire_receive_pcs1_rateswitchout;
wire [19:0] wire_receive_pcs1_revparallelfdbkdata;
wire [3:0] wire_receive_pcs1_syncstatus;
wire wire_receive_pcs2_cdrctrllocktorefclkout;
wire wire_receive_pcs2_coreclkout;
wire [3:0] wire_receive_pcs2_ctrldetect;
wire [39:0] wire_receive_pcs2_dataout;
wire [399:0] wire_receive_pcs2_dprioout;
wire [3:0] wire_receive_pcs2_patterndetect;
wire wire_receive_pcs2_phfifobyteserdisableout;
wire wire_receive_pcs2_phfifoptrsresetout;
wire wire_receive_pcs2_phfifordenableout;
wire wire_receive_pcs2_phfiforesetout;
wire wire_receive_pcs2_phfifowrdisableout;
wire wire_receive_pcs2_pipedatavalid;
wire wire_receive_pcs2_pipeelecidle;
wire wire_receive_pcs2_pipephydonestatus;
wire wire_receive_pcs2_pipestatetransdoneout;
wire [2:0] wire_receive_pcs2_pipestatus;
wire wire_receive_pcs2_rateswitchout;
wire [19:0] wire_receive_pcs2_revparallelfdbkdata;
wire [3:0] wire_receive_pcs2_syncstatus;
wire wire_receive_pcs3_cdrctrllocktorefclkout;
wire wire_receive_pcs3_coreclkout;
wire [3:0] wire_receive_pcs3_ctrldetect;
wire [39:0] wire_receive_pcs3_dataout;
wire [399:0] wire_receive_pcs3_dprioout;
wire [3:0] wire_receive_pcs3_patterndetect;
wire wire_receive_pcs3_phfifobyteserdisableout;
wire wire_receive_pcs3_phfifoptrsresetout;
wire wire_receive_pcs3_phfifordenableout;
wire wire_receive_pcs3_phfiforesetout;
wire wire_receive_pcs3_phfifowrdisableout;
wire wire_receive_pcs3_pipedatavalid;
wire wire_receive_pcs3_pipeelecidle;
wire wire_receive_pcs3_pipephydonestatus;
wire wire_receive_pcs3_pipestatetransdoneout;
wire [2:0] wire_receive_pcs3_pipestatus;
wire wire_receive_pcs3_rateswitchout;
wire [19:0] wire_receive_pcs3_revparallelfdbkdata;
wire [3:0] wire_receive_pcs3_syncstatus;
wire wire_receive_pma0_clockout;
wire wire_receive_pma0_dataout;
wire [299:0] wire_receive_pma0_dprioout;
wire wire_receive_pma0_locktorefout;
wire [63:0] wire_receive_pma0_recoverdataout;
wire wire_receive_pma0_signaldetect;
wire wire_receive_pma1_clockout;
wire wire_receive_pma1_dataout;
wire [299:0] wire_receive_pma1_dprioout;
wire wire_receive_pma1_locktorefout;
wire [63:0] wire_receive_pma1_recoverdataout;
wire wire_receive_pma1_signaldetect;
wire wire_receive_pma2_clockout;
wire wire_receive_pma2_dataout;
wire [299:0] wire_receive_pma2_dprioout;
wire wire_receive_pma2_locktorefout;
wire [63:0] wire_receive_pma2_recoverdataout;
wire wire_receive_pma2_signaldetect;
wire wire_receive_pma3_clockout;
wire wire_receive_pma3_dataout;
wire [299:0] wire_receive_pma3_dprioout;
wire wire_receive_pma3_locktorefout;
wire [63:0] wire_receive_pma3_recoverdataout;
wire wire_receive_pma3_signaldetect;
wire wire_transmit_pcs0_clkout;
wire wire_transmit_pcs0_coreclkout;
wire [19:0] wire_transmit_pcs0_dataout;
wire [149:0] wire_transmit_pcs0_dprioout;
wire wire_transmit_pcs0_phfiforddisableout;
wire wire_transmit_pcs0_phfiforesetout;
wire wire_transmit_pcs0_phfifowrenableout;
wire [1:0] wire_transmit_pcs0_pipepowerdownout;
wire [3:0] wire_transmit_pcs0_pipepowerstateout;
wire wire_transmit_pcs0_txdetectrx;
wire wire_transmit_pcs1_clkout;
wire wire_transmit_pcs1_coreclkout;
wire [19:0] wire_transmit_pcs1_dataout;
wire [149:0] wire_transmit_pcs1_dprioout;
wire wire_transmit_pcs1_phfiforddisableout;
wire wire_transmit_pcs1_phfiforesetout;
wire wire_transmit_pcs1_phfifowrenableout;
wire [1:0] wire_transmit_pcs1_pipepowerdownout;
wire [3:0] wire_transmit_pcs1_pipepowerstateout;
wire wire_transmit_pcs1_txdetectrx;
wire wire_transmit_pcs2_clkout;
wire wire_transmit_pcs2_coreclkout;
wire [19:0] wire_transmit_pcs2_dataout;
wire [149:0] wire_transmit_pcs2_dprioout;
wire wire_transmit_pcs2_phfiforddisableout;
wire wire_transmit_pcs2_phfiforesetout;
wire wire_transmit_pcs2_phfifowrenableout;
wire [1:0] wire_transmit_pcs2_pipepowerdownout;
wire [3:0] wire_transmit_pcs2_pipepowerstateout;
wire wire_transmit_pcs2_txdetectrx;
wire wire_transmit_pcs3_clkout;
wire wire_transmit_pcs3_coreclkout;
wire [19:0] wire_transmit_pcs3_dataout;
wire [149:0] wire_transmit_pcs3_dprioout;
wire wire_transmit_pcs3_phfiforddisableout;
wire wire_transmit_pcs3_phfiforesetout;
wire wire_transmit_pcs3_phfifowrenableout;
wire [1:0] wire_transmit_pcs3_pipepowerdownout;
wire [3:0] wire_transmit_pcs3_pipepowerstateout;
wire wire_transmit_pcs3_txdetectrx;
wire wire_transmit_pma0_clockout;
wire wire_transmit_pma0_dataout;
wire [299:0] wire_transmit_pma0_dprioout;
wire wire_transmit_pma0_rxdetectvalidout;
wire wire_transmit_pma0_rxfoundout;
wire wire_transmit_pma1_clockout;
wire wire_transmit_pma1_dataout;
wire [299:0] wire_transmit_pma1_dprioout;
wire wire_transmit_pma1_rxdetectvalidout;
wire wire_transmit_pma1_rxfoundout;
wire wire_transmit_pma2_clockout;
wire wire_transmit_pma2_dataout;
wire [299:0] wire_transmit_pma2_dprioout;
wire wire_transmit_pma2_rxdetectvalidout;
wire wire_transmit_pma2_rxfoundout;
wire wire_transmit_pma3_clockout;
wire wire_transmit_pma3_dataout;
wire [299:0] wire_transmit_pma3_dprioout;
wire wire_transmit_pma3_rxdetectvalidout;
wire wire_transmit_pma3_rxfoundout;
wire cal_blk_powerdown;
wire [0:0] cent_unit_clkdivpowerdn;
wire [599:0] cent_unit_cmudividerdprioout;
wire [1799:0] cent_unit_cmuplldprioout;
wire [1:0] cent_unit_pllpowerdn;
wire [1:0] cent_unit_pllresetout;
wire [0:0] cent_unit_quadresetout;
wire [3:0] cent_unit_rxadcepowerdn;
wire [5:0] cent_unit_rxcrupowerdn;
wire [5:0] cent_unit_rxibpowerdn;
wire [1599:0] cent_unit_rxpcsdprioin;
wire [1599:0] cent_unit_rxpcsdprioout;
wire [1799:0] cent_unit_rxpmadprioin;
wire [1799:0] cent_unit_rxpmadprioout;
wire [1199:0] cent_unit_tx_dprioin;
wire [31:0] cent_unit_tx_xgmdataout;
wire [3:0] cent_unit_txctrlout;
wire [3:0] cent_unit_txdetectrxpowerdn;
wire [599:0] cent_unit_txdprioout;
wire [5:0] cent_unit_txobpowerdn;
wire [1799:0] cent_unit_txpmadprioin;
wire [1799:0] cent_unit_txpmadprioout;
wire [3:0] clk_div_clk0in;
wire [599:0] clk_div_cmudividerdprioin;
wire [0:0] clk_div_pclkin;
wire [1:0] cmu_analogfastrefclkout;
wire [1:0] cmu_analogrefclkout;
wire [0:0] cmu_analogrefclkpulse;
wire [0:0] coreclkout_wire;
wire fixedclk;
wire [5:0] fixedclk_in;
wire [0:0] int_hiprateswtichdone;
wire [3:0] int_rx_coreclkout;
wire [3:0] int_rx_phfifobyteserdisable;
wire [3:0] int_rx_phfifoptrsresetout;
wire [3:0] int_rx_phfifordenableout;
wire [3:0] int_rx_phfiforesetout;
wire [3:0] int_rx_phfifowrdisableout;
wire [11:0] int_rx_phfifoxnbytesel;
wire [11:0] int_rx_phfifoxnrdenable;
wire [11:0] int_rx_phfifoxnwrclk;
wire [11:0] int_rx_phfifoxnwrenable;
wire [0:0] int_rxcoreclk;
wire [0:0] int_rxphfifordenable;
wire [0:0] int_rxphfiforeset;
wire [0:0] int_rxphfifox4byteselout;
wire [0:0] int_rxphfifox4rdenableout;
wire [0:0] int_rxphfifox4wrclkout;
wire [0:0] int_rxphfifox4wrenableout;
wire [3:0] int_tx_coreclkout;
wire [3:0] int_tx_phfiforddisableout;
wire [3:0] int_tx_phfiforesetout;
wire [3:0] int_tx_phfifowrenableout;
wire [11:0] int_tx_phfifoxnbytesel;
wire [11:0] int_tx_phfifoxnrdclk;
wire [11:0] int_tx_phfifoxnrdenable;
wire [11:0] int_tx_phfifoxnwrenable;
wire [0:0] int_txcoreclk;
wire [0:0] int_txphfiforddisable;
wire [0:0] int_txphfiforeset;
wire [0:0] int_txphfifowrenable;
wire [0:0] int_txphfifox4byteselout;
wire [0:0] int_txphfifox4rdclkout;
wire [0:0] int_txphfifox4rdenableout;
wire [0:0] int_txphfifox4wrenableout;
wire [0:0] nonusertocmu_out;
wire [3:0] pipedatavalid_out;
wire [3:0] pipeelecidle_out;
wire [9:0] pll0_clkin;
wire [299:0] pll0_dprioin;
wire [299:0] pll0_dprioout;
wire [3:0] pll0_out;
wire [3:0] pll1_out;
wire [7:0] pll_ch_dataout_wire;
wire [1199:0] pll_ch_dprioout;
wire [1799:0] pll_cmuplldprioout;
wire [0:0] pll_inclk_wire;
wire [0:0] pll_locked_out;
wire [0:0] pll_powerdown;
wire [1:0] pllpowerdn_in;
wire [1:0] pllreset_in;
wire [0:0] reconfig_togxb_disable;
wire [0:0] reconfig_togxb_in;
wire [0:0] reconfig_togxb_load;
wire [0:0] refclk_pma;
wire [1:0] refclkdividerdprioin;
wire [3:0] rx_analogreset_in;
wire [5:0] rx_analogreset_out;
wire [3:0] rx_bitslip;
wire [3:0] rx_coreclk_in;
wire [35:0] rx_cruclk_in;
wire [15:0] rx_deserclock_in;
wire [3:0] rx_digitalreset_in;
wire [3:0] rx_digitalreset_out;
wire [11:0] rx_elecidleinfersel;
wire [3:0] rx_enapatternalign;
wire [3:0] rx_freqlocked_wire;
wire [3:0] rx_locktodata;
wire [3:0] rx_locktodata_wire;
wire [3:0] rx_locktorefclk_wire;
wire [63:0] rx_out_wire;
wire [7:0] rx_pcs_rxfound_wire;
wire [1599:0] rx_pcsdprioin_wire;
wire [1599:0] rx_pcsdprioout;
wire [3:0] rx_phfifordenable;
wire [3:0] rx_phfiforeset;
wire [3:0] rx_phfifowrdisable;
wire [3:0] rx_pipestatetransdoneout;
wire [3:0] rx_pldcruclk_in;
wire [15:0] rx_pll_clkout;
wire [3:0] rx_pll_pfdrefclkout_wire;
wire [3:0] rx_plllocked_wire;
wire [3:0] rx_pma_clockout;
wire [3:0] rx_pma_dataout;
wire [3:0] rx_pma_locktorefout;
wire [79:0] rx_pma_recoverdataout_wire;
wire [1799:0] rx_pmadprioin_wire;
wire [1799:0] rx_pmadprioout;
wire [3:0] rx_powerdown;
wire [3:0] rx_powerdown_in;
wire [3:0] rx_prbscidenable;
wire [79:0] rx_revparallelfdbkdata;
wire [3:0] rx_rmfiforeset;
wire [3:0] rx_rxadceresetout;
wire [5:0] rx_rxcruresetout;
wire [3:0] rx_signaldetect_wire;
wire [0:0] rxphfifowrdisable;
wire [299:0] rxpll_dprioin;
wire [5:0] tx_analogreset_out;
wire [3:0] tx_clkout_int_wire;
wire [3:0] tx_coreclk_in;
wire [63:0] tx_datain_wire;
wire [351:0] tx_datainfull;
wire [79:0] tx_dataout_pcs_to_pma;
wire [3:0] tx_digitalreset_in;
wire [3:0] tx_digitalreset_out;
wire [1199:0] tx_dprioin_wire;
wire [7:0] tx_forcedisp_wire;
wire [3:0] tx_invpolarity;
wire [3:0] tx_localrefclk;
wire [3:0] tx_phfiforeset;
wire [3:0] tx_pipedeemph;
wire [11:0] tx_pipemargin;
wire [7:0] tx_pipepowerdownout;
wire [15:0] tx_pipepowerstateout;
wire [3:0] tx_pipeswing;
wire [1799:0] tx_pmadprioin_wire;
wire [1799:0] tx_pmadprioout;
wire [3:0] tx_revparallellpbken;
wire [3:0] tx_rxdetectvalidout;
wire [3:0] tx_rxfoundout;
wire [599:0] tx_txdprioout;
wire [3:0] txdetectrxout;
wire [0:0] w_cent_unit_dpriodisableout1w;
stratixiv_hssi_calibration_block cal_blk0
(
.calibrationstatus(),
.clk(cal_blk_clk),
.enabletestbus(1'b1),
.nonusertocmu(wire_cal_blk0_nonusertocmu),
.powerdn(cal_blk_powerdown)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.testctrl(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
stratixiv_hssi_clock_divider central_clk_div0
(
.analogfastrefclkout(wire_central_clk_div0_analogfastrefclkout),
.analogfastrefclkoutshifted(),
.analogrefclkout(wire_central_clk_div0_analogrefclkout),
.analogrefclkoutshifted(),
.analogrefclkpulse(wire_central_clk_div0_analogrefclkpulse),
.analogrefclkpulseshifted(),
.clk0in(clk_div_clk0in[3:0]),
.coreclkout(wire_central_clk_div0_coreclkout),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(cent_unit_cmudividerdprioout[99:0]),
.dprioout(wire_central_clk_div0_dprioout),
.powerdn(cent_unit_clkdivpowerdn[0]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitchbaseclock(),
.rateswitchdone(wire_central_clk_div0_rateswitchdone),
.rateswitchout(),
.refclkin({2{clk_div_pclkin[0]}}),
.refclkout(wire_central_clk_div0_refclkout)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clk1in({4{1'b0}}),
.rateswitch(1'b0),
.rateswitchbaseclkin({2{1'b0}}),
.rateswitchdonein({2{1'b0}}),
.refclkdig(1'b0),
.vcobypassin(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
central_clk_div0.data_rate = 800,
central_clk_div0.divide_by = 5,
central_clk_div0.divider_type = "CENTRAL_ENHANCED",
central_clk_div0.enable_dynamic_divider = "false",
central_clk_div0.enable_refclk_out = "true",
central_clk_div0.inclk_select = 0,
central_clk_div0.logical_channel_address = 0,
central_clk_div0.pre_divide_by = 1,
central_clk_div0.refclk_divide_by = 2,
central_clk_div0.refclk_multiply_by = 25,
central_clk_div0.refclkin_select = 0,
central_clk_div0.select_local_rate_switch_base_clock = "true",
central_clk_div0.select_local_refclk = "true",
central_clk_div0.sim_analogfastrefclkout_phase_shift = 0,
central_clk_div0.sim_analogrefclkout_phase_shift = 0,
central_clk_div0.sim_coreclkout_phase_shift = 0,
central_clk_div0.sim_refclkout_phase_shift = 0,
central_clk_div0.use_coreclk_out_post_divider = "true",
central_clk_div0.use_refclk_post_divider = "false",
central_clk_div0.use_vco_bypass = "false",
central_clk_div0.lpm_type = "stratixiv_hssi_clock_divider";
stratixiv_hssi_cmu cent_unit0
(
.adet({4{1'b0}}),
.alignstatus(),
.autospdx4configsel(),
.autospdx4rateswitchout(),
.autospdx4spdchg(),
.clkdivpowerdn(wire_cent_unit0_clkdivpowerdn),
.cmudividerdprioin(clk_div_cmudividerdprioin[599:0]),
.cmudividerdprioout(wire_cent_unit0_cmudividerdprioout),
.cmuplldprioin(pll_cmuplldprioout[1799:0]),
.cmuplldprioout(wire_cent_unit0_cmuplldprioout),
.digitaltestout(),
.dpclk(reconfig_clk),
.dpriodisable(reconfig_togxb_disable),
.dpriodisableout(wire_cent_unit0_dpriodisableout),
.dprioin(reconfig_togxb_in),
.dprioload(reconfig_togxb_load),
.dpriooe(),
.dprioout(wire_cent_unit0_dprioout),
.enabledeskew(),
.fiforesetrd(),
.fixedclk(fixedclk_in[5:0]),
.nonuserfromcal(nonusertocmu_out[0]),
.phfifiox4ptrsreset(),
.pllpowerdn(wire_cent_unit0_pllpowerdn),
.pllresetout(wire_cent_unit0_pllresetout),
.quadreset(gxb_powerdown[0]),
.quadresetout(wire_cent_unit0_quadresetout),
.rateswitchdonein(int_hiprateswtichdone[0]),
.rdalign({4{1'b0}}),
.rdenablesync(1'b0),
.recovclk(1'b0),
.refclkdividerdprioin(refclkdividerdprioin[1:0]),
.refclkdividerdprioout(),
.rxadcepowerdown(wire_cent_unit0_rxadcepowerdown),
.rxadceresetout(wire_cent_unit0_rxadceresetout),
.rxanalogreset({{2{1'b0}}, rx_analogreset_in[3:0]}),
.rxanalogresetout(wire_cent_unit0_rxanalogresetout),
.rxclk(refclk_pma[0]),
.rxcoreclk(int_rxcoreclk[0]),
.rxcrupowerdown(wire_cent_unit0_rxcrupowerdown),
.rxcruresetout(wire_cent_unit0_rxcruresetout),
.rxctrl({4{1'b0}}),
.rxctrlout(),
.rxdatain({32{1'b0}}),
.rxdataout(),
.rxdatavalid({4{1'b0}}),
.rxdigitalreset(rx_digitalreset_in[3:0]),
.rxdigitalresetout(wire_cent_unit0_rxdigitalresetout),
.rxdprioout(),
.rxibpowerdown(wire_cent_unit0_rxibpowerdown),
.rxpcsdprioin(cent_unit_rxpcsdprioin[1599:0]),
.rxpcsdprioout(wire_cent_unit0_rxpcsdprioout),
.rxphfifordenable(int_rxphfifordenable[0]),
.rxphfiforeset(int_rxphfiforeset[0]),
.rxphfifowrdisable(rxphfifowrdisable[0]),
.rxphfifox4byteselout(wire_cent_unit0_rxphfifox4byteselout),
.rxphfifox4rdenableout(wire_cent_unit0_rxphfifox4rdenableout),
.rxphfifox4wrclkout(wire_cent_unit0_rxphfifox4wrclkout),
.rxphfifox4wrenableout(wire_cent_unit0_rxphfifox4wrenableout),
.rxpmadprioin(cent_unit_rxpmadprioin[1799:0]),
.rxpmadprioout(wire_cent_unit0_rxpmadprioout),
.rxpowerdown({{2{1'b0}}, rx_powerdown_in[3:0]}),
.rxrunningdisp({4{1'b0}}),
.scanout(),
.syncstatus({4{1'b0}}),
.testout(),
.txanalogresetout(wire_cent_unit0_txanalogresetout),
.txclk(refclk_pma[0]),
.txcoreclk(int_txcoreclk[0]),
.txctrl({4{1'b0}}),
.txctrlout(wire_cent_unit0_txctrlout),
.txdatain({32{1'b0}}),
.txdataout(wire_cent_unit0_txdataout),
.txdetectrxpowerdown(wire_cent_unit0_txdetectrxpowerdown),
.txdigitalreset(tx_digitalreset_in[3:0]),
.txdigitalresetout(wire_cent_unit0_txdigitalresetout),
.txdividerpowerdown(),
.txdprioout(),
.txobpowerdown(wire_cent_unit0_txobpowerdown),
.txpcsdprioin(cent_unit_tx_dprioin[599:0]),
.txpcsdprioout(wire_cent_unit0_txpcsdprioout),
.txphfiforddisable(int_txphfiforddisable[0]),
.txphfiforeset(int_txphfiforeset[0]),
.txphfifowrenable(int_txphfifowrenable[0]),
.txphfifox4byteselout(wire_cent_unit0_txphfifox4byteselout),
.txphfifox4rdclkout(wire_cent_unit0_txphfifox4rdclkout),
.txphfifox4rdenableout(wire_cent_unit0_txphfifox4rdenableout),
.txphfifox4wrenableout(wire_cent_unit0_txphfifox4wrenableout),
.txpllreset({{1{1'b0}}, pll_powerdown[0]}),
.txpmadprioin(cent_unit_txpmadprioin[1799:0]),
.txpmadprioout(wire_cent_unit0_txpmadprioout)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.rateswitch(1'b0),
.rxdprioin({1200{1'b0}}),
.scanclk(1'b0),
.scanin({23{1'b0}}),
.scanmode(1'b0),
.scanshift(1'b0),
.testin({6000{1'b0}}),
.txdprioin({600{1'b0}})
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
cent_unit0.auto_spd_deassert_ph_fifo_rst_count = 8,
cent_unit0.auto_spd_phystatus_notify_count = 14,
cent_unit0.bonded_quad_mode = "none",
cent_unit0.devaddr = ((((starting_channel_number / 4) + 0) % 32) + 1),
cent_unit0.dprio_config_mode = 6'h01,
cent_unit0.in_xaui_mode = "false",
cent_unit0.offset_all_errors_align = "false",
cent_unit0.pipe_auto_speed_nego_enable = "false",
cent_unit0.pipe_freq_scale_mode = "Frequency",
cent_unit0.pma_done_count = 250000,
cent_unit0.portaddr = (((starting_channel_number + 0) / 128) + 1),
cent_unit0.rx0_auto_spd_self_switch_enable = "false",
cent_unit0.rx0_channel_bonding = "x4",
cent_unit0.rx0_clk1_mux_select = "recovered clock",
cent_unit0.rx0_clk2_mux_select = "digital reference clock",
cent_unit0.rx0_ph_fifo_reg_mode = "false",
cent_unit0.rx0_rd_clk_mux_select = "core clock",
cent_unit0.rx0_recovered_clk_mux_select = "recovered clock",
cent_unit0.rx0_reset_clock_output_during_digital_reset = "false",
cent_unit0.rx0_use_double_data_mode = "true",
cent_unit0.tx0_auto_spd_self_switch_enable = "false",
cent_unit0.tx0_channel_bonding = "x4",
cent_unit0.tx0_ph_fifo_reg_mode = "false",
cent_unit0.tx0_rd_clk_mux_select = "cmu_clock_divider",
cent_unit0.tx0_use_double_data_mode = "true",
cent_unit0.tx0_wr_clk_mux_select = "core_clk",
cent_unit0.use_deskew_fifo = "false",
cent_unit0.vcceh_voltage = "3.0V",
cent_unit0.lpm_type = "stratixiv_hssi_cmu";
stratixiv_hssi_pll rx_cdr_pll0
(
.areset(rx_rxcruresetout[0]),
.clk(wire_rx_cdr_pll0_clk),
.datain(rx_pma_dataout[0]),
.dataout(wire_rx_cdr_pll0_dataout),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rxpll_dprioin[299:0]),
.dprioout(wire_rx_cdr_pll0_dprioout),
.freqlocked(wire_rx_cdr_pll0_freqlocked),
.inclk({{1{1'b0}}, rx_cruclk_in[8:0]}),
.locked(wire_rx_cdr_pll0_locked),
.locktorefclk(rx_pma_locktorefout[0]),
.pfdfbclkout(),
.pfdrefclkout(wire_rx_cdr_pll0_pfdrefclkout),
.powerdown(cent_unit_rxcrupowerdn[0]),
.vcobypassout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.earlyeios(1'b0),
.pfdfbclk(1'b0),
.rateswitch(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
rx_cdr_pll0.channel_num = ((starting_channel_number + 0) % 4),
rx_cdr_pll0.charge_pump_current_bits = 0,
rx_cdr_pll0.dprio_config_mode = 6'h01,
rx_cdr_pll0.inclk0_input_period = 10000,
rx_cdr_pll0.inclk1_input_period = 5000,
rx_cdr_pll0.inclk2_input_period = 5000,
rx_cdr_pll0.inclk3_input_period = 5000,
rx_cdr_pll0.inclk4_input_period = 5000,
rx_cdr_pll0.inclk5_input_period = 5000,
rx_cdr_pll0.inclk6_input_period = 5000,
rx_cdr_pll0.inclk7_input_period = 5000,
rx_cdr_pll0.inclk8_input_period = 5000,
rx_cdr_pll0.inclk9_input_period = 5000,
rx_cdr_pll0.loop_filter_c_bits = 0,
rx_cdr_pll0.loop_filter_r_bits = 0,
rx_cdr_pll0.m = 25,
rx_cdr_pll0.n = 2,
rx_cdr_pll0.pd_charge_pump_current_bits = 0,
rx_cdr_pll0.pd_loop_filter_r_bits = 0,
rx_cdr_pll0.pfd_clk_select = 0,
rx_cdr_pll0.pll_type = "RX CDR",
rx_cdr_pll0.protocol_hint = "pcie",
rx_cdr_pll0.use_refclk_pin = "false",
rx_cdr_pll0.vco_data_rate = 800,
rx_cdr_pll0.vco_divide_by = 2,
rx_cdr_pll0.vco_multiply_by = 25,
rx_cdr_pll0.vco_post_scale = 2,
rx_cdr_pll0.lpm_type = "stratixiv_hssi_pll";
stratixiv_hssi_pll rx_cdr_pll1
(
.areset(rx_rxcruresetout[1]),
.clk(wire_rx_cdr_pll1_clk),
.datain(rx_pma_dataout[1]),
.dataout(wire_rx_cdr_pll1_dataout),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rxpll_dprioin[299:0]),
.dprioout(wire_rx_cdr_pll1_dprioout),
.freqlocked(wire_rx_cdr_pll1_freqlocked),
.inclk({{1{1'b0}}, rx_cruclk_in[17:9]}),
.locked(wire_rx_cdr_pll1_locked),
.locktorefclk(rx_pma_locktorefout[1]),
.pfdfbclkout(),
.pfdrefclkout(wire_rx_cdr_pll1_pfdrefclkout),
.powerdown(cent_unit_rxcrupowerdn[1]),
.vcobypassout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.earlyeios(1'b0),
.pfdfbclk(1'b0),
.rateswitch(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
rx_cdr_pll1.channel_num = ((starting_channel_number + 1) % 4),
rx_cdr_pll1.charge_pump_current_bits = 0,
rx_cdr_pll1.dprio_config_mode = 6'h01,
rx_cdr_pll1.inclk0_input_period = 10000,
rx_cdr_pll1.inclk1_input_period = 5000,
rx_cdr_pll1.inclk2_input_period = 5000,
rx_cdr_pll1.inclk3_input_period = 5000,
rx_cdr_pll1.inclk4_input_period = 5000,
rx_cdr_pll1.inclk5_input_period = 5000,
rx_cdr_pll1.inclk6_input_period = 5000,
rx_cdr_pll1.inclk7_input_period = 5000,
rx_cdr_pll1.inclk8_input_period = 5000,
rx_cdr_pll1.inclk9_input_period = 5000,
rx_cdr_pll1.loop_filter_c_bits = 0,
rx_cdr_pll1.loop_filter_r_bits = 0,
rx_cdr_pll1.m = 25,
rx_cdr_pll1.n = 2,
rx_cdr_pll1.pd_charge_pump_current_bits = 0,
rx_cdr_pll1.pd_loop_filter_r_bits = 0,
rx_cdr_pll1.pfd_clk_select = 0,
rx_cdr_pll1.pll_type = "RX CDR",
rx_cdr_pll1.protocol_hint = "pcie",
rx_cdr_pll1.use_refclk_pin = "false",
rx_cdr_pll1.vco_data_rate = 800,
rx_cdr_pll1.vco_divide_by = 2,
rx_cdr_pll1.vco_multiply_by = 25,
rx_cdr_pll1.vco_post_scale = 2,
rx_cdr_pll1.lpm_type = "stratixiv_hssi_pll";
stratixiv_hssi_pll rx_cdr_pll2
(
.areset(rx_rxcruresetout[2]),
.clk(wire_rx_cdr_pll2_clk),
.datain(rx_pma_dataout[2]),
.dataout(wire_rx_cdr_pll2_dataout),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rxpll_dprioin[299:0]),
.dprioout(wire_rx_cdr_pll2_dprioout),
.freqlocked(wire_rx_cdr_pll2_freqlocked),
.inclk({{1{1'b0}}, rx_cruclk_in[26:18]}),
.locked(wire_rx_cdr_pll2_locked),
.locktorefclk(rx_pma_locktorefout[2]),
.pfdfbclkout(),
.pfdrefclkout(wire_rx_cdr_pll2_pfdrefclkout),
.powerdown(cent_unit_rxcrupowerdn[2]),
.vcobypassout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.earlyeios(1'b0),
.pfdfbclk(1'b0),
.rateswitch(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
rx_cdr_pll2.channel_num = ((starting_channel_number + 2) % 4),
rx_cdr_pll2.charge_pump_current_bits = 0,
rx_cdr_pll2.dprio_config_mode = 6'h01,
rx_cdr_pll2.inclk0_input_period = 10000,
rx_cdr_pll2.inclk1_input_period = 5000,
rx_cdr_pll2.inclk2_input_period = 5000,
rx_cdr_pll2.inclk3_input_period = 5000,
rx_cdr_pll2.inclk4_input_period = 5000,
rx_cdr_pll2.inclk5_input_period = 5000,
rx_cdr_pll2.inclk6_input_period = 5000,
rx_cdr_pll2.inclk7_input_period = 5000,
rx_cdr_pll2.inclk8_input_period = 5000,
rx_cdr_pll2.inclk9_input_period = 5000,
rx_cdr_pll2.loop_filter_c_bits = 0,
rx_cdr_pll2.loop_filter_r_bits = 0,
rx_cdr_pll2.m = 25,
rx_cdr_pll2.n = 2,
rx_cdr_pll2.pd_charge_pump_current_bits = 0,
rx_cdr_pll2.pd_loop_filter_r_bits = 0,
rx_cdr_pll2.pfd_clk_select = 0,
rx_cdr_pll2.pll_type = "RX CDR",
rx_cdr_pll2.protocol_hint = "pcie",
rx_cdr_pll2.use_refclk_pin = "false",
rx_cdr_pll2.vco_data_rate = 800,
rx_cdr_pll2.vco_divide_by = 2,
rx_cdr_pll2.vco_multiply_by = 25,
rx_cdr_pll2.vco_post_scale = 2,
rx_cdr_pll2.lpm_type = "stratixiv_hssi_pll";
stratixiv_hssi_pll rx_cdr_pll3
(
.areset(rx_rxcruresetout[3]),
.clk(wire_rx_cdr_pll3_clk),
.datain(rx_pma_dataout[3]),
.dataout(wire_rx_cdr_pll3_dataout),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rxpll_dprioin[299:0]),
.dprioout(wire_rx_cdr_pll3_dprioout),
.freqlocked(wire_rx_cdr_pll3_freqlocked),
.inclk({{1{1'b0}}, rx_cruclk_in[35:27]}),
.locked(wire_rx_cdr_pll3_locked),
.locktorefclk(rx_pma_locktorefout[3]),
.pfdfbclkout(),
.pfdrefclkout(wire_rx_cdr_pll3_pfdrefclkout),
.powerdown(cent_unit_rxcrupowerdn[3]),
.vcobypassout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.earlyeios(1'b0),
.pfdfbclk(1'b0),
.rateswitch(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
rx_cdr_pll3.channel_num = ((starting_channel_number + 3) % 4),
rx_cdr_pll3.charge_pump_current_bits = 0,
rx_cdr_pll3.dprio_config_mode = 6'h01,
rx_cdr_pll3.inclk0_input_period = 10000,
rx_cdr_pll3.inclk1_input_period = 5000,
rx_cdr_pll3.inclk2_input_period = 5000,
rx_cdr_pll3.inclk3_input_period = 5000,
rx_cdr_pll3.inclk4_input_period = 5000,
rx_cdr_pll3.inclk5_input_period = 5000,
rx_cdr_pll3.inclk6_input_period = 5000,
rx_cdr_pll3.inclk7_input_period = 5000,
rx_cdr_pll3.inclk8_input_period = 5000,
rx_cdr_pll3.inclk9_input_period = 5000,
rx_cdr_pll3.loop_filter_c_bits = 0,
rx_cdr_pll3.loop_filter_r_bits = 0,
rx_cdr_pll3.m = 25,
rx_cdr_pll3.n = 2,
rx_cdr_pll3.pd_charge_pump_current_bits = 0,
rx_cdr_pll3.pd_loop_filter_r_bits = 0,
rx_cdr_pll3.pfd_clk_select = 0,
rx_cdr_pll3.pll_type = "RX CDR",
rx_cdr_pll3.protocol_hint = "pcie",
rx_cdr_pll3.use_refclk_pin = "false",
rx_cdr_pll3.vco_data_rate = 800,
rx_cdr_pll3.vco_divide_by = 2,
rx_cdr_pll3.vco_multiply_by = 25,
rx_cdr_pll3.vco_post_scale = 2,
rx_cdr_pll3.lpm_type = "stratixiv_hssi_pll";
stratixiv_hssi_pll tx_pll0
(
.areset(pllreset_in[0]),
.clk(wire_tx_pll0_clk),
.dataout(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(pll0_dprioin[299:0]),
.dprioout(wire_tx_pll0_dprioout),
.freqlocked(),
.inclk({pll0_clkin[9:0]}),
.locked(wire_tx_pll0_locked),
.pfdfbclkout(),
.pfdrefclkout(),
.powerdown(pllpowerdn_in[0]),
.vcobypassout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.datain(1'b0),
.earlyeios(1'b0),
.locktorefclk(1'b1),
.pfdfbclk(1'b0),
.rateswitch(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
tx_pll0.channel_num = 4,
tx_pll0.charge_pump_current_bits = 0,
tx_pll0.dprio_config_mode = 6'h01,
tx_pll0.inclk0_input_period = 10000,
tx_pll0.inclk1_input_period = 5000,
tx_pll0.inclk2_input_period = 5000,
tx_pll0.inclk3_input_period = 5000,
tx_pll0.inclk4_input_period = 5000,
tx_pll0.inclk5_input_period = 5000,
tx_pll0.inclk6_input_period = 5000,
tx_pll0.inclk7_input_period = 5000,
tx_pll0.inclk8_input_period = 5000,
tx_pll0.inclk9_input_period = 5000,
tx_pll0.loop_filter_c_bits = 0,
tx_pll0.loop_filter_r_bits = 0,
tx_pll0.m = 25,
tx_pll0.n = 2,
tx_pll0.pfd_clk_select = 0,
tx_pll0.pll_type = "CMU",
tx_pll0.protocol_hint = "pcie",
tx_pll0.use_refclk_pin = "false",
tx_pll0.vco_data_rate = 0,
tx_pll0.vco_divide_by = 0,
tx_pll0.vco_multiply_by = 0,
tx_pll0.vco_post_scale = 2,
tx_pll0.lpm_type = "stratixiv_hssi_pll";
stratixiv_hssi_rx_pcs receive_pcs0
(
.a1a2size(1'b0),
.a1a2sizeout(),
.a1detect(),
.a2detect(),
.adetectdeskew(),
.alignstatus(1'b0),
.alignstatussync(1'b0),
.alignstatussyncout(),
.autospdrateswitchout(),
.autospdspdchgout(),
.bistdone(),
.bisterr(),
.bitslip(rx_bitslip[0]),
.bitslipboundaryselectout(),
.byteorderalignstatus(),
.cdrctrlearlyeios(),
.cdrctrllocktorefclkout(wire_receive_pcs0_cdrctrllocktorefclkout),
.clkout(),
.coreclk(rx_coreclk_in[0]),
.coreclkout(wire_receive_pcs0_coreclkout),
.ctrldetect(wire_receive_pcs0_ctrldetect),
.datain(rx_pma_recoverdataout_wire[19:0]),
.dataout(wire_receive_pcs0_dataout),
.dataoutfull(),
.digitalreset(rx_digitalreset_out[0]),
.disablefifordin(1'b0),
.disablefifordout(),
.disablefifowrin(1'b0),
.disablefifowrout(),
.disperr(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pcsdprioin_wire[399:0]),
.dprioout(wire_receive_pcs0_dprioout),
.elecidleinfersel(rx_elecidleinfersel[2:0]),
.enabledeskew(1'b0),
.enabyteord(1'b0),
.enapatternalign(rx_enapatternalign[0]),
.errdetect(),
.fifordin(1'b0),
.fifordout(),
.fiforesetrd(1'b0),
.hipdataout(),
.hipdatavalid(),
.hipelecidle(),
.hipphydonestatus(),
.hipstatus(),
.invpol(1'b0),
.iqpphfifobyteselout(),
.iqpphfifoptrsresetout(),
.iqpphfifordenableout(),
.iqpphfifowrclkout(),
.iqpphfifowrenableout(),
.k1detect(),
.k2detect(),
.localrefclk(1'b0),
.masterclk(1'b0),
.parallelfdbk({20{1'b0}}),
.patterndetect(wire_receive_pcs0_patterndetect),
.phfifobyteselout(),
.phfifobyteserdisableout(wire_receive_pcs0_phfifobyteserdisableout),
.phfifooverflow(),
.phfifoptrsresetout(wire_receive_pcs0_phfifoptrsresetout),
.phfifordenable(rx_phfifordenable[0]),
.phfifordenableout(wire_receive_pcs0_phfifordenableout),
.phfiforeset(rx_phfiforeset[0]),
.phfiforesetout(wire_receive_pcs0_phfiforesetout),
.phfifounderflow(),
.phfifowrclkout(),
.phfifowrdisable(rx_phfifowrdisable[0]),
.phfifowrdisableout(wire_receive_pcs0_phfifowrdisableout),
.phfifowrenableout(),
.phfifoxnbytesel(int_rx_phfifoxnbytesel[2:0]),
.phfifoxnrdenable(int_rx_phfifoxnrdenable[2:0]),
.phfifoxnwrclk(int_rx_phfifoxnwrclk[2:0]),
.phfifoxnwrenable(int_rx_phfifoxnwrenable[2:0]),
.pipe8b10binvpolarity(pipe8b10binvpolarity[0]),
.pipebufferstat(),
.pipedatavalid(wire_receive_pcs0_pipedatavalid),
.pipeelecidle(wire_receive_pcs0_pipeelecidle),
.pipephydonestatus(wire_receive_pcs0_pipephydonestatus),
.pipepowerdown(tx_pipepowerdownout[1:0]),
.pipepowerstate(tx_pipepowerstateout[3:0]),
.pipestatetransdoneout(wire_receive_pcs0_pipestatetransdoneout),
.pipestatus(wire_receive_pcs0_pipestatus),
.powerdn(powerdn[1:0]),
.prbscidenable(rx_prbscidenable[0]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitchout(wire_receive_pcs0_rateswitchout),
.rateswitchxndone(int_hiprateswtichdone[0]),
.rdalign(),
.recoveredclk(rx_pma_clockout[0]),
.refclk(refclk_pma[0]),
.revbitorderwa(1'b0),
.revbyteorderwa(1'b0),
.revparallelfdbkdata(wire_receive_pcs0_revparallelfdbkdata),
.rlv(),
.rmfifoalmostempty(),
.rmfifoalmostfull(),
.rmfifodatadeleted(),
.rmfifodatainserted(),
.rmfifoempty(),
.rmfifofull(),
.rmfifordena(1'b0),
.rmfiforeset(rx_rmfiforeset[0]),
.rmfifowrena(1'b0),
.runningdisp(),
.rxdetectvalid(tx_rxdetectvalidout[0]),
.rxfound(rx_pcs_rxfound_wire[1:0]),
.signaldetected(rx_signaldetect_wire[0]),
.syncstatus(wire_receive_pcs0_syncstatus),
.syncstatusdeskew(),
.xauidelcondmetout(),
.xauififoovrout(),
.xauiinsertincompleteout(),
.xauilatencycompout(),
.xgmctrldet(),
.xgmctrlin(1'b0),
.xgmdatain({8{1'b0}}),
.xgmdataout(),
.xgmdatavalid(),
.xgmrunningdisp()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.autospdxnconfigsel({3{1'b0}}),
.autospdxnspdchg({3{1'b0}}),
.cdrctrllocktorefcl(1'b0),
.grayelecidleinferselfromtx({3{1'b0}}),
.hip8b10binvpolarity(1'b0),
.hipelecidleinfersel({3{1'b0}}),
.hippowerdown({2{1'b0}}),
.hiprateswitch(1'b0),
.iqpautospdxnspgchg({2{1'b0}}),
.iqpphfifoxnbytesel({2{1'b0}}),
.iqpphfifoxnptrsreset({2{1'b0}}),
.iqpphfifoxnrdenable({2{1'b0}}),
.iqpphfifoxnwrclk({2{1'b0}}),
.iqpphfifoxnwrenable({2{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrclk(1'b0),
.phfifox4wrenable(1'b0),
.phfifox8bytesel(1'b0),
.phfifox8rdenable(1'b0),
.phfifox8wrclk(1'b0),
.phfifox8wrenable(1'b0),
.phfifoxnptrsreset({3{1'b0}}),
.pipeenrevparallellpbkfromtx(1'b0),
.ppmdetectdividedclk(1'b0),
.ppmdetectrefclk(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rxelecidlerateswitch(1'b0),
.xauidelcondmet(1'b0),
.xauififoovr(1'b0),
.xauiinsertincomplete(1'b0),
.xauilatencycomp(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
receive_pcs0.align_pattern = "0101111100",
receive_pcs0.align_pattern_length = 10,
receive_pcs0.align_to_deskew_pattern_pos_disp_only = "false",
receive_pcs0.allow_align_polarity_inversion = "false",
receive_pcs0.allow_pipe_polarity_inversion = "true",
receive_pcs0.auto_spd_deassert_ph_fifo_rst_count = 8,
receive_pcs0.auto_spd_phystatus_notify_count = 14,
receive_pcs0.auto_spd_self_switch_enable = "false",
receive_pcs0.bit_slip_enable = "false",
receive_pcs0.byte_order_mode = "none",
receive_pcs0.byte_order_pad_pattern = "0",
receive_pcs0.byte_order_pattern = "0",
receive_pcs0.byte_order_pld_ctrl_enable = "false",
receive_pcs0.cdrctrl_bypass_ppm_detector_cycle = 1000,
receive_pcs0.cdrctrl_enable = "true",
receive_pcs0.cdrctrl_mask_cycle = 800,
receive_pcs0.cdrctrl_min_lock_to_ref_cycle = 63,
receive_pcs0.cdrctrl_rxvalid_mask = "true",
receive_pcs0.channel_bonding = "x4",
receive_pcs0.channel_number = ((starting_channel_number + 0) % 4),
receive_pcs0.channel_width = 16,
receive_pcs0.clk1_mux_select = "recovered clock",
receive_pcs0.clk2_mux_select = "digital reference clock",
receive_pcs0.core_clock_0ppm = "false",
receive_pcs0.datapath_low_latency_mode = "false",
receive_pcs0.datapath_protocol = "pipe",
receive_pcs0.dec_8b_10b_compatibility_mode = "true",
receive_pcs0.dec_8b_10b_mode = "normal",
receive_pcs0.dec_8b_10b_polarity_inv_enable = "true",
receive_pcs0.deskew_pattern = "0",
receive_pcs0.disable_auto_idle_insertion = "false",
receive_pcs0.disable_running_disp_in_word_align = "false",
receive_pcs0.disallow_kchar_after_pattern_ordered_set = "false",
receive_pcs0.dprio_config_mode = 6'h01,
receive_pcs0.elec_idle_infer_enable = "false",
receive_pcs0.elec_idle_num_com_detect = 3,
receive_pcs0.enable_bit_reversal = "false",
receive_pcs0.enable_deep_align = "false",
receive_pcs0.enable_deep_align_byte_swap = "false",
receive_pcs0.enable_self_test_mode = "false",
receive_pcs0.enable_true_complement_match_in_word_align = "false",
receive_pcs0.force_signal_detect_dig = "true",
receive_pcs0.hip_enable = "false",
receive_pcs0.infiniband_invalid_code = 0,
receive_pcs0.insert_pad_on_underflow = "false",
receive_pcs0.logical_channel_address = (starting_channel_number + 0),
receive_pcs0.num_align_code_groups_in_ordered_set = 0,
receive_pcs0.num_align_cons_good_data = 16,
receive_pcs0.num_align_cons_pat = 4,
receive_pcs0.num_align_loss_sync_error = 17,
receive_pcs0.ph_fifo_low_latency_enable = "true",
receive_pcs0.ph_fifo_reg_mode = "false",
receive_pcs0.ph_fifo_xn_mapping0 = "none",
receive_pcs0.ph_fifo_xn_mapping1 = "none",
receive_pcs0.ph_fifo_xn_mapping2 = "central",
receive_pcs0.ph_fifo_xn_select = 2,
receive_pcs0.pipe_auto_speed_nego_enable = "false",
receive_pcs0.pipe_freq_scale_mode = "Frequency",
receive_pcs0.pma_done_count = 250000,
receive_pcs0.protocol_hint = "pcie",
receive_pcs0.rate_match_almost_empty_threshold = 11,
receive_pcs0.rate_match_almost_full_threshold = 13,
receive_pcs0.rate_match_back_to_back = "false",
receive_pcs0.rate_match_delete_threshold = 13,
receive_pcs0.rate_match_empty_threshold = 5,
receive_pcs0.rate_match_fifo_mode = "true",
receive_pcs0.rate_match_full_threshold = 20,
receive_pcs0.rate_match_insert_threshold = 11,
receive_pcs0.rate_match_ordered_set_based = "false",
receive_pcs0.rate_match_pattern1 = "11010000111010000011",
receive_pcs0.rate_match_pattern2 = "00101111000101111100",
receive_pcs0.rate_match_pattern_size = 20,
receive_pcs0.rate_match_reset_enable = "false",
receive_pcs0.rate_match_skip_set_based = "true",
receive_pcs0.rate_match_start_threshold = 7,
receive_pcs0.rd_clk_mux_select = "core clock",
receive_pcs0.recovered_clk_mux_select = "recovered clock",
receive_pcs0.run_length = 40,
receive_pcs0.run_length_enable = "true",
receive_pcs0.rx_detect_bypass = "false",
receive_pcs0.rxstatus_error_report_mode = 0,
receive_pcs0.self_test_mode = "incremental",
receive_pcs0.use_alignment_state_machine = "true",
receive_pcs0.use_deserializer_double_data_mode = "false",
receive_pcs0.use_deskew_fifo = "false",
receive_pcs0.use_double_data_mode = "true",
receive_pcs0.use_parallel_loopback = "false",
receive_pcs0.use_rising_edge_triggered_pattern_align = "false",
receive_pcs0.lpm_type = "stratixiv_hssi_rx_pcs";
stratixiv_hssi_rx_pcs receive_pcs1
(
.a1a2size(1'b0),
.a1a2sizeout(),
.a1detect(),
.a2detect(),
.adetectdeskew(),
.alignstatus(1'b0),
.alignstatussync(1'b0),
.alignstatussyncout(),
.autospdrateswitchout(),
.autospdspdchgout(),
.bistdone(),
.bisterr(),
.bitslip(rx_bitslip[1]),
.bitslipboundaryselectout(),
.byteorderalignstatus(),
.cdrctrlearlyeios(),
.cdrctrllocktorefclkout(wire_receive_pcs1_cdrctrllocktorefclkout),
.clkout(),
.coreclk(rx_coreclk_in[1]),
.coreclkout(wire_receive_pcs1_coreclkout),
.ctrldetect(wire_receive_pcs1_ctrldetect),
.datain(rx_pma_recoverdataout_wire[39:20]),
.dataout(wire_receive_pcs1_dataout),
.dataoutfull(),
.digitalreset(rx_digitalreset_out[1]),
.disablefifordin(1'b0),
.disablefifordout(),
.disablefifowrin(1'b0),
.disablefifowrout(),
.disperr(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pcsdprioin_wire[799:400]),
.dprioout(wire_receive_pcs1_dprioout),
.elecidleinfersel(rx_elecidleinfersel[5:3]),
.enabledeskew(1'b0),
.enabyteord(1'b0),
.enapatternalign(rx_enapatternalign[1]),
.errdetect(),
.fifordin(1'b0),
.fifordout(),
.fiforesetrd(1'b0),
.hipdataout(),
.hipdatavalid(),
.hipelecidle(),
.hipphydonestatus(),
.hipstatus(),
.invpol(1'b0),
.iqpphfifobyteselout(),
.iqpphfifoptrsresetout(),
.iqpphfifordenableout(),
.iqpphfifowrclkout(),
.iqpphfifowrenableout(),
.k1detect(),
.k2detect(),
.localrefclk(1'b0),
.masterclk(1'b0),
.parallelfdbk({20{1'b0}}),
.patterndetect(wire_receive_pcs1_patterndetect),
.phfifobyteselout(),
.phfifobyteserdisableout(wire_receive_pcs1_phfifobyteserdisableout),
.phfifooverflow(),
.phfifoptrsresetout(wire_receive_pcs1_phfifoptrsresetout),
.phfifordenable(rx_phfifordenable[1]),
.phfifordenableout(wire_receive_pcs1_phfifordenableout),
.phfiforeset(rx_phfiforeset[1]),
.phfiforesetout(wire_receive_pcs1_phfiforesetout),
.phfifounderflow(),
.phfifowrclkout(),
.phfifowrdisable(rx_phfifowrdisable[1]),
.phfifowrdisableout(wire_receive_pcs1_phfifowrdisableout),
.phfifowrenableout(),
.phfifoxnbytesel(int_rx_phfifoxnbytesel[5:3]),
.phfifoxnrdenable(int_rx_phfifoxnrdenable[5:3]),
.phfifoxnwrclk(int_rx_phfifoxnwrclk[5:3]),
.phfifoxnwrenable(int_rx_phfifoxnwrenable[5:3]),
.pipe8b10binvpolarity(pipe8b10binvpolarity[1]),
.pipebufferstat(),
.pipedatavalid(wire_receive_pcs1_pipedatavalid),
.pipeelecidle(wire_receive_pcs1_pipeelecidle),
.pipephydonestatus(wire_receive_pcs1_pipephydonestatus),
.pipepowerdown(tx_pipepowerdownout[3:2]),
.pipepowerstate(tx_pipepowerstateout[7:4]),
.pipestatetransdoneout(wire_receive_pcs1_pipestatetransdoneout),
.pipestatus(wire_receive_pcs1_pipestatus),
.powerdn(powerdn[3:2]),
.prbscidenable(rx_prbscidenable[1]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitchout(wire_receive_pcs1_rateswitchout),
.rateswitchxndone(int_hiprateswtichdone[0]),
.rdalign(),
.recoveredclk(rx_pma_clockout[1]),
.refclk(refclk_pma[0]),
.revbitorderwa(1'b0),
.revbyteorderwa(1'b0),
.revparallelfdbkdata(wire_receive_pcs1_revparallelfdbkdata),
.rlv(),
.rmfifoalmostempty(),
.rmfifoalmostfull(),
.rmfifodatadeleted(),
.rmfifodatainserted(),
.rmfifoempty(),
.rmfifofull(),
.rmfifordena(1'b0),
.rmfiforeset(rx_rmfiforeset[1]),
.rmfifowrena(1'b0),
.runningdisp(),
.rxdetectvalid(tx_rxdetectvalidout[1]),
.rxfound(rx_pcs_rxfound_wire[3:2]),
.signaldetected(rx_signaldetect_wire[1]),
.syncstatus(wire_receive_pcs1_syncstatus),
.syncstatusdeskew(),
.xauidelcondmetout(),
.xauififoovrout(),
.xauiinsertincompleteout(),
.xauilatencycompout(),
.xgmctrldet(),
.xgmctrlin(1'b0),
.xgmdatain({8{1'b0}}),
.xgmdataout(),
.xgmdatavalid(),
.xgmrunningdisp()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.autospdxnconfigsel({3{1'b0}}),
.autospdxnspdchg({3{1'b0}}),
.cdrctrllocktorefcl(1'b0),
.grayelecidleinferselfromtx({3{1'b0}}),
.hip8b10binvpolarity(1'b0),
.hipelecidleinfersel({3{1'b0}}),
.hippowerdown({2{1'b0}}),
.hiprateswitch(1'b0),
.iqpautospdxnspgchg({2{1'b0}}),
.iqpphfifoxnbytesel({2{1'b0}}),
.iqpphfifoxnptrsreset({2{1'b0}}),
.iqpphfifoxnrdenable({2{1'b0}}),
.iqpphfifoxnwrclk({2{1'b0}}),
.iqpphfifoxnwrenable({2{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrclk(1'b0),
.phfifox4wrenable(1'b0),
.phfifox8bytesel(1'b0),
.phfifox8rdenable(1'b0),
.phfifox8wrclk(1'b0),
.phfifox8wrenable(1'b0),
.phfifoxnptrsreset({3{1'b0}}),
.pipeenrevparallellpbkfromtx(1'b0),
.ppmdetectdividedclk(1'b0),
.ppmdetectrefclk(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rxelecidlerateswitch(1'b0),
.xauidelcondmet(1'b0),
.xauififoovr(1'b0),
.xauiinsertincomplete(1'b0),
.xauilatencycomp(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
receive_pcs1.align_pattern = "0101111100",
receive_pcs1.align_pattern_length = 10,
receive_pcs1.align_to_deskew_pattern_pos_disp_only = "false",
receive_pcs1.allow_align_polarity_inversion = "false",
receive_pcs1.allow_pipe_polarity_inversion = "true",
receive_pcs1.auto_spd_deassert_ph_fifo_rst_count = 8,
receive_pcs1.auto_spd_phystatus_notify_count = 14,
receive_pcs1.auto_spd_self_switch_enable = "false",
receive_pcs1.bit_slip_enable = "false",
receive_pcs1.byte_order_mode = "none",
receive_pcs1.byte_order_pad_pattern = "0",
receive_pcs1.byte_order_pattern = "0",
receive_pcs1.byte_order_pld_ctrl_enable = "false",
receive_pcs1.cdrctrl_bypass_ppm_detector_cycle = 1000,
receive_pcs1.cdrctrl_enable = "true",
receive_pcs1.cdrctrl_mask_cycle = 800,
receive_pcs1.cdrctrl_min_lock_to_ref_cycle = 63,
receive_pcs1.cdrctrl_rxvalid_mask = "true",
receive_pcs1.channel_bonding = "x4",
receive_pcs1.channel_number = ((starting_channel_number + 1) % 4),
receive_pcs1.channel_width = 16,
receive_pcs1.clk1_mux_select = "recovered clock",
receive_pcs1.clk2_mux_select = "digital reference clock",
receive_pcs1.core_clock_0ppm = "false",
receive_pcs1.datapath_low_latency_mode = "false",
receive_pcs1.datapath_protocol = "pipe",
receive_pcs1.dec_8b_10b_compatibility_mode = "true",
receive_pcs1.dec_8b_10b_mode = "normal",
receive_pcs1.dec_8b_10b_polarity_inv_enable = "true",
receive_pcs1.deskew_pattern = "0",
receive_pcs1.disable_auto_idle_insertion = "false",
receive_pcs1.disable_running_disp_in_word_align = "false",
receive_pcs1.disallow_kchar_after_pattern_ordered_set = "false",
receive_pcs1.dprio_config_mode = 6'h01,
receive_pcs1.elec_idle_infer_enable = "false",
receive_pcs1.elec_idle_num_com_detect = 3,
receive_pcs1.enable_bit_reversal = "false",
receive_pcs1.enable_deep_align = "false",
receive_pcs1.enable_deep_align_byte_swap = "false",
receive_pcs1.enable_self_test_mode = "false",
receive_pcs1.enable_true_complement_match_in_word_align = "false",
receive_pcs1.force_signal_detect_dig = "true",
receive_pcs1.hip_enable = "false",
receive_pcs1.infiniband_invalid_code = 0,
receive_pcs1.insert_pad_on_underflow = "false",
receive_pcs1.logical_channel_address = (starting_channel_number + 1),
receive_pcs1.num_align_code_groups_in_ordered_set = 0,
receive_pcs1.num_align_cons_good_data = 16,
receive_pcs1.num_align_cons_pat = 4,
receive_pcs1.num_align_loss_sync_error = 17,
receive_pcs1.ph_fifo_low_latency_enable = "true",
receive_pcs1.ph_fifo_reg_mode = "false",
receive_pcs1.ph_fifo_xn_mapping0 = "none",
receive_pcs1.ph_fifo_xn_mapping1 = "none",
receive_pcs1.ph_fifo_xn_mapping2 = "central",
receive_pcs1.ph_fifo_xn_select = 2,
receive_pcs1.pipe_auto_speed_nego_enable = "false",
receive_pcs1.pipe_freq_scale_mode = "Frequency",
receive_pcs1.pma_done_count = 250000,
receive_pcs1.protocol_hint = "pcie",
receive_pcs1.rate_match_almost_empty_threshold = 11,
receive_pcs1.rate_match_almost_full_threshold = 13,
receive_pcs1.rate_match_back_to_back = "false",
receive_pcs1.rate_match_delete_threshold = 13,
receive_pcs1.rate_match_empty_threshold = 5,
receive_pcs1.rate_match_fifo_mode = "true",
receive_pcs1.rate_match_full_threshold = 20,
receive_pcs1.rate_match_insert_threshold = 11,
receive_pcs1.rate_match_ordered_set_based = "false",
receive_pcs1.rate_match_pattern1 = "11010000111010000011",
receive_pcs1.rate_match_pattern2 = "00101111000101111100",
receive_pcs1.rate_match_pattern_size = 20,
receive_pcs1.rate_match_reset_enable = "false",
receive_pcs1.rate_match_skip_set_based = "true",
receive_pcs1.rate_match_start_threshold = 7,
receive_pcs1.rd_clk_mux_select = "core clock",
receive_pcs1.recovered_clk_mux_select = "recovered clock",
receive_pcs1.run_length = 40,
receive_pcs1.run_length_enable = "true",
receive_pcs1.rx_detect_bypass = "false",
receive_pcs1.rxstatus_error_report_mode = 0,
receive_pcs1.self_test_mode = "incremental",
receive_pcs1.use_alignment_state_machine = "true",
receive_pcs1.use_deserializer_double_data_mode = "false",
receive_pcs1.use_deskew_fifo = "false",
receive_pcs1.use_double_data_mode = "true",
receive_pcs1.use_parallel_loopback = "false",
receive_pcs1.use_rising_edge_triggered_pattern_align = "false",
receive_pcs1.lpm_type = "stratixiv_hssi_rx_pcs";
stratixiv_hssi_rx_pcs receive_pcs2
(
.a1a2size(1'b0),
.a1a2sizeout(),
.a1detect(),
.a2detect(),
.adetectdeskew(),
.alignstatus(1'b0),
.alignstatussync(1'b0),
.alignstatussyncout(),
.autospdrateswitchout(),
.autospdspdchgout(),
.bistdone(),
.bisterr(),
.bitslip(rx_bitslip[2]),
.bitslipboundaryselectout(),
.byteorderalignstatus(),
.cdrctrlearlyeios(),
.cdrctrllocktorefclkout(wire_receive_pcs2_cdrctrllocktorefclkout),
.clkout(),
.coreclk(rx_coreclk_in[2]),
.coreclkout(wire_receive_pcs2_coreclkout),
.ctrldetect(wire_receive_pcs2_ctrldetect),
.datain(rx_pma_recoverdataout_wire[59:40]),
.dataout(wire_receive_pcs2_dataout),
.dataoutfull(),
.digitalreset(rx_digitalreset_out[2]),
.disablefifordin(1'b0),
.disablefifordout(),
.disablefifowrin(1'b0),
.disablefifowrout(),
.disperr(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pcsdprioin_wire[1199:800]),
.dprioout(wire_receive_pcs2_dprioout),
.elecidleinfersel(rx_elecidleinfersel[8:6]),
.enabledeskew(1'b0),
.enabyteord(1'b0),
.enapatternalign(rx_enapatternalign[2]),
.errdetect(),
.fifordin(1'b0),
.fifordout(),
.fiforesetrd(1'b0),
.hipdataout(),
.hipdatavalid(),
.hipelecidle(),
.hipphydonestatus(),
.hipstatus(),
.invpol(1'b0),
.iqpphfifobyteselout(),
.iqpphfifoptrsresetout(),
.iqpphfifordenableout(),
.iqpphfifowrclkout(),
.iqpphfifowrenableout(),
.k1detect(),
.k2detect(),
.localrefclk(1'b0),
.masterclk(1'b0),
.parallelfdbk({20{1'b0}}),
.patterndetect(wire_receive_pcs2_patterndetect),
.phfifobyteselout(),
.phfifobyteserdisableout(wire_receive_pcs2_phfifobyteserdisableout),
.phfifooverflow(),
.phfifoptrsresetout(wire_receive_pcs2_phfifoptrsresetout),
.phfifordenable(rx_phfifordenable[2]),
.phfifordenableout(wire_receive_pcs2_phfifordenableout),
.phfiforeset(rx_phfiforeset[2]),
.phfiforesetout(wire_receive_pcs2_phfiforesetout),
.phfifounderflow(),
.phfifowrclkout(),
.phfifowrdisable(rx_phfifowrdisable[2]),
.phfifowrdisableout(wire_receive_pcs2_phfifowrdisableout),
.phfifowrenableout(),
.phfifoxnbytesel(int_rx_phfifoxnbytesel[8:6]),
.phfifoxnrdenable(int_rx_phfifoxnrdenable[8:6]),
.phfifoxnwrclk(int_rx_phfifoxnwrclk[8:6]),
.phfifoxnwrenable(int_rx_phfifoxnwrenable[8:6]),
.pipe8b10binvpolarity(pipe8b10binvpolarity[2]),
.pipebufferstat(),
.pipedatavalid(wire_receive_pcs2_pipedatavalid),
.pipeelecidle(wire_receive_pcs2_pipeelecidle),
.pipephydonestatus(wire_receive_pcs2_pipephydonestatus),
.pipepowerdown(tx_pipepowerdownout[5:4]),
.pipepowerstate(tx_pipepowerstateout[11:8]),
.pipestatetransdoneout(wire_receive_pcs2_pipestatetransdoneout),
.pipestatus(wire_receive_pcs2_pipestatus),
.powerdn(powerdn[5:4]),
.prbscidenable(rx_prbscidenable[2]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitchout(wire_receive_pcs2_rateswitchout),
.rateswitchxndone(int_hiprateswtichdone[0]),
.rdalign(),
.recoveredclk(rx_pma_clockout[2]),
.refclk(refclk_pma[0]),
.revbitorderwa(1'b0),
.revbyteorderwa(1'b0),
.revparallelfdbkdata(wire_receive_pcs2_revparallelfdbkdata),
.rlv(),
.rmfifoalmostempty(),
.rmfifoalmostfull(),
.rmfifodatadeleted(),
.rmfifodatainserted(),
.rmfifoempty(),
.rmfifofull(),
.rmfifordena(1'b0),
.rmfiforeset(rx_rmfiforeset[2]),
.rmfifowrena(1'b0),
.runningdisp(),
.rxdetectvalid(tx_rxdetectvalidout[2]),
.rxfound(rx_pcs_rxfound_wire[5:4]),
.signaldetected(rx_signaldetect_wire[2]),
.syncstatus(wire_receive_pcs2_syncstatus),
.syncstatusdeskew(),
.xauidelcondmetout(),
.xauififoovrout(),
.xauiinsertincompleteout(),
.xauilatencycompout(),
.xgmctrldet(),
.xgmctrlin(1'b0),
.xgmdatain({8{1'b0}}),
.xgmdataout(),
.xgmdatavalid(),
.xgmrunningdisp()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.autospdxnconfigsel({3{1'b0}}),
.autospdxnspdchg({3{1'b0}}),
.cdrctrllocktorefcl(1'b0),
.grayelecidleinferselfromtx({3{1'b0}}),
.hip8b10binvpolarity(1'b0),
.hipelecidleinfersel({3{1'b0}}),
.hippowerdown({2{1'b0}}),
.hiprateswitch(1'b0),
.iqpautospdxnspgchg({2{1'b0}}),
.iqpphfifoxnbytesel({2{1'b0}}),
.iqpphfifoxnptrsreset({2{1'b0}}),
.iqpphfifoxnrdenable({2{1'b0}}),
.iqpphfifoxnwrclk({2{1'b0}}),
.iqpphfifoxnwrenable({2{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrclk(1'b0),
.phfifox4wrenable(1'b0),
.phfifox8bytesel(1'b0),
.phfifox8rdenable(1'b0),
.phfifox8wrclk(1'b0),
.phfifox8wrenable(1'b0),
.phfifoxnptrsreset({3{1'b0}}),
.pipeenrevparallellpbkfromtx(1'b0),
.ppmdetectdividedclk(1'b0),
.ppmdetectrefclk(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rxelecidlerateswitch(1'b0),
.xauidelcondmet(1'b0),
.xauififoovr(1'b0),
.xauiinsertincomplete(1'b0),
.xauilatencycomp(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
receive_pcs2.align_pattern = "0101111100",
receive_pcs2.align_pattern_length = 10,
receive_pcs2.align_to_deskew_pattern_pos_disp_only = "false",
receive_pcs2.allow_align_polarity_inversion = "false",
receive_pcs2.allow_pipe_polarity_inversion = "true",
receive_pcs2.auto_spd_deassert_ph_fifo_rst_count = 8,
receive_pcs2.auto_spd_phystatus_notify_count = 14,
receive_pcs2.auto_spd_self_switch_enable = "false",
receive_pcs2.bit_slip_enable = "false",
receive_pcs2.byte_order_mode = "none",
receive_pcs2.byte_order_pad_pattern = "0",
receive_pcs2.byte_order_pattern = "0",
receive_pcs2.byte_order_pld_ctrl_enable = "false",
receive_pcs2.cdrctrl_bypass_ppm_detector_cycle = 1000,
receive_pcs2.cdrctrl_enable = "true",
receive_pcs2.cdrctrl_mask_cycle = 800,
receive_pcs2.cdrctrl_min_lock_to_ref_cycle = 63,
receive_pcs2.cdrctrl_rxvalid_mask = "true",
receive_pcs2.channel_bonding = "x4",
receive_pcs2.channel_number = ((starting_channel_number + 2) % 4),
receive_pcs2.channel_width = 16,
receive_pcs2.clk1_mux_select = "recovered clock",
receive_pcs2.clk2_mux_select = "digital reference clock",
receive_pcs2.core_clock_0ppm = "false",
receive_pcs2.datapath_low_latency_mode = "false",
receive_pcs2.datapath_protocol = "pipe",
receive_pcs2.dec_8b_10b_compatibility_mode = "true",
receive_pcs2.dec_8b_10b_mode = "normal",
receive_pcs2.dec_8b_10b_polarity_inv_enable = "true",
receive_pcs2.deskew_pattern = "0",
receive_pcs2.disable_auto_idle_insertion = "false",
receive_pcs2.disable_running_disp_in_word_align = "false",
receive_pcs2.disallow_kchar_after_pattern_ordered_set = "false",
receive_pcs2.dprio_config_mode = 6'h01,
receive_pcs2.elec_idle_infer_enable = "false",
receive_pcs2.elec_idle_num_com_detect = 3,
receive_pcs2.enable_bit_reversal = "false",
receive_pcs2.enable_deep_align = "false",
receive_pcs2.enable_deep_align_byte_swap = "false",
receive_pcs2.enable_self_test_mode = "false",
receive_pcs2.enable_true_complement_match_in_word_align = "false",
receive_pcs2.force_signal_detect_dig = "true",
receive_pcs2.hip_enable = "false",
receive_pcs2.infiniband_invalid_code = 0,
receive_pcs2.insert_pad_on_underflow = "false",
receive_pcs2.logical_channel_address = (starting_channel_number + 2),
receive_pcs2.num_align_code_groups_in_ordered_set = 0,
receive_pcs2.num_align_cons_good_data = 16,
receive_pcs2.num_align_cons_pat = 4,
receive_pcs2.num_align_loss_sync_error = 17,
receive_pcs2.ph_fifo_low_latency_enable = "true",
receive_pcs2.ph_fifo_reg_mode = "false",
receive_pcs2.ph_fifo_xn_mapping0 = "none",
receive_pcs2.ph_fifo_xn_mapping1 = "none",
receive_pcs2.ph_fifo_xn_mapping2 = "central",
receive_pcs2.ph_fifo_xn_select = 2,
receive_pcs2.pipe_auto_speed_nego_enable = "false",
receive_pcs2.pipe_freq_scale_mode = "Frequency",
receive_pcs2.pma_done_count = 250000,
receive_pcs2.protocol_hint = "pcie",
receive_pcs2.rate_match_almost_empty_threshold = 11,
receive_pcs2.rate_match_almost_full_threshold = 13,
receive_pcs2.rate_match_back_to_back = "false",
receive_pcs2.rate_match_delete_threshold = 13,
receive_pcs2.rate_match_empty_threshold = 5,
receive_pcs2.rate_match_fifo_mode = "true",
receive_pcs2.rate_match_full_threshold = 20,
receive_pcs2.rate_match_insert_threshold = 11,
receive_pcs2.rate_match_ordered_set_based = "false",
receive_pcs2.rate_match_pattern1 = "11010000111010000011",
receive_pcs2.rate_match_pattern2 = "00101111000101111100",
receive_pcs2.rate_match_pattern_size = 20,
receive_pcs2.rate_match_reset_enable = "false",
receive_pcs2.rate_match_skip_set_based = "true",
receive_pcs2.rate_match_start_threshold = 7,
receive_pcs2.rd_clk_mux_select = "core clock",
receive_pcs2.recovered_clk_mux_select = "recovered clock",
receive_pcs2.run_length = 40,
receive_pcs2.run_length_enable = "true",
receive_pcs2.rx_detect_bypass = "false",
receive_pcs2.rxstatus_error_report_mode = 0,
receive_pcs2.self_test_mode = "incremental",
receive_pcs2.use_alignment_state_machine = "true",
receive_pcs2.use_deserializer_double_data_mode = "false",
receive_pcs2.use_deskew_fifo = "false",
receive_pcs2.use_double_data_mode = "true",
receive_pcs2.use_parallel_loopback = "false",
receive_pcs2.use_rising_edge_triggered_pattern_align = "false",
receive_pcs2.lpm_type = "stratixiv_hssi_rx_pcs";
stratixiv_hssi_rx_pcs receive_pcs3
(
.a1a2size(1'b0),
.a1a2sizeout(),
.a1detect(),
.a2detect(),
.adetectdeskew(),
.alignstatus(1'b0),
.alignstatussync(1'b0),
.alignstatussyncout(),
.autospdrateswitchout(),
.autospdspdchgout(),
.bistdone(),
.bisterr(),
.bitslip(rx_bitslip[3]),
.bitslipboundaryselectout(),
.byteorderalignstatus(),
.cdrctrlearlyeios(),
.cdrctrllocktorefclkout(wire_receive_pcs3_cdrctrllocktorefclkout),
.clkout(),
.coreclk(rx_coreclk_in[3]),
.coreclkout(wire_receive_pcs3_coreclkout),
.ctrldetect(wire_receive_pcs3_ctrldetect),
.datain(rx_pma_recoverdataout_wire[79:60]),
.dataout(wire_receive_pcs3_dataout),
.dataoutfull(),
.digitalreset(rx_digitalreset_out[3]),
.disablefifordin(1'b0),
.disablefifordout(),
.disablefifowrin(1'b0),
.disablefifowrout(),
.disperr(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pcsdprioin_wire[1599:1200]),
.dprioout(wire_receive_pcs3_dprioout),
.elecidleinfersel(rx_elecidleinfersel[11:9]),
.enabledeskew(1'b0),
.enabyteord(1'b0),
.enapatternalign(rx_enapatternalign[3]),
.errdetect(),
.fifordin(1'b0),
.fifordout(),
.fiforesetrd(1'b0),
.hipdataout(),
.hipdatavalid(),
.hipelecidle(),
.hipphydonestatus(),
.hipstatus(),
.invpol(1'b0),
.iqpphfifobyteselout(),
.iqpphfifoptrsresetout(),
.iqpphfifordenableout(),
.iqpphfifowrclkout(),
.iqpphfifowrenableout(),
.k1detect(),
.k2detect(),
.localrefclk(1'b0),
.masterclk(1'b0),
.parallelfdbk({20{1'b0}}),
.patterndetect(wire_receive_pcs3_patterndetect),
.phfifobyteselout(),
.phfifobyteserdisableout(wire_receive_pcs3_phfifobyteserdisableout),
.phfifooverflow(),
.phfifoptrsresetout(wire_receive_pcs3_phfifoptrsresetout),
.phfifordenable(rx_phfifordenable[3]),
.phfifordenableout(wire_receive_pcs3_phfifordenableout),
.phfiforeset(rx_phfiforeset[3]),
.phfiforesetout(wire_receive_pcs3_phfiforesetout),
.phfifounderflow(),
.phfifowrclkout(),
.phfifowrdisable(rx_phfifowrdisable[3]),
.phfifowrdisableout(wire_receive_pcs3_phfifowrdisableout),
.phfifowrenableout(),
.phfifoxnbytesel(int_rx_phfifoxnbytesel[11:9]),
.phfifoxnrdenable(int_rx_phfifoxnrdenable[11:9]),
.phfifoxnwrclk(int_rx_phfifoxnwrclk[11:9]),
.phfifoxnwrenable(int_rx_phfifoxnwrenable[11:9]),
.pipe8b10binvpolarity(pipe8b10binvpolarity[3]),
.pipebufferstat(),
.pipedatavalid(wire_receive_pcs3_pipedatavalid),
.pipeelecidle(wire_receive_pcs3_pipeelecidle),
.pipephydonestatus(wire_receive_pcs3_pipephydonestatus),
.pipepowerdown(tx_pipepowerdownout[7:6]),
.pipepowerstate(tx_pipepowerstateout[15:12]),
.pipestatetransdoneout(wire_receive_pcs3_pipestatetransdoneout),
.pipestatus(wire_receive_pcs3_pipestatus),
.powerdn(powerdn[7:6]),
.prbscidenable(rx_prbscidenable[3]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitchout(wire_receive_pcs3_rateswitchout),
.rateswitchxndone(int_hiprateswtichdone[0]),
.rdalign(),
.recoveredclk(rx_pma_clockout[3]),
.refclk(refclk_pma[0]),
.revbitorderwa(1'b0),
.revbyteorderwa(1'b0),
.revparallelfdbkdata(wire_receive_pcs3_revparallelfdbkdata),
.rlv(),
.rmfifoalmostempty(),
.rmfifoalmostfull(),
.rmfifodatadeleted(),
.rmfifodatainserted(),
.rmfifoempty(),
.rmfifofull(),
.rmfifordena(1'b0),
.rmfiforeset(rx_rmfiforeset[3]),
.rmfifowrena(1'b0),
.runningdisp(),
.rxdetectvalid(tx_rxdetectvalidout[3]),
.rxfound(rx_pcs_rxfound_wire[7:6]),
.signaldetected(rx_signaldetect_wire[3]),
.syncstatus(wire_receive_pcs3_syncstatus),
.syncstatusdeskew(),
.xauidelcondmetout(),
.xauififoovrout(),
.xauiinsertincompleteout(),
.xauilatencycompout(),
.xgmctrldet(),
.xgmctrlin(1'b0),
.xgmdatain({8{1'b0}}),
.xgmdataout(),
.xgmdatavalid(),
.xgmrunningdisp()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.autospdxnconfigsel({3{1'b0}}),
.autospdxnspdchg({3{1'b0}}),
.cdrctrllocktorefcl(1'b0),
.grayelecidleinferselfromtx({3{1'b0}}),
.hip8b10binvpolarity(1'b0),
.hipelecidleinfersel({3{1'b0}}),
.hippowerdown({2{1'b0}}),
.hiprateswitch(1'b0),
.iqpautospdxnspgchg({2{1'b0}}),
.iqpphfifoxnbytesel({2{1'b0}}),
.iqpphfifoxnptrsreset({2{1'b0}}),
.iqpphfifoxnrdenable({2{1'b0}}),
.iqpphfifoxnwrclk({2{1'b0}}),
.iqpphfifoxnwrenable({2{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrclk(1'b0),
.phfifox4wrenable(1'b0),
.phfifox8bytesel(1'b0),
.phfifox8rdenable(1'b0),
.phfifox8wrclk(1'b0),
.phfifox8wrenable(1'b0),
.phfifoxnptrsreset({3{1'b0}}),
.pipeenrevparallellpbkfromtx(1'b0),
.ppmdetectdividedclk(1'b0),
.ppmdetectrefclk(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rxelecidlerateswitch(1'b0),
.xauidelcondmet(1'b0),
.xauififoovr(1'b0),
.xauiinsertincomplete(1'b0),
.xauilatencycomp(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
receive_pcs3.align_pattern = "0101111100",
receive_pcs3.align_pattern_length = 10,
receive_pcs3.align_to_deskew_pattern_pos_disp_only = "false",
receive_pcs3.allow_align_polarity_inversion = "false",
receive_pcs3.allow_pipe_polarity_inversion = "true",
receive_pcs3.auto_spd_deassert_ph_fifo_rst_count = 8,
receive_pcs3.auto_spd_phystatus_notify_count = 14,
receive_pcs3.auto_spd_self_switch_enable = "false",
receive_pcs3.bit_slip_enable = "false",
receive_pcs3.byte_order_mode = "none",
receive_pcs3.byte_order_pad_pattern = "0",
receive_pcs3.byte_order_pattern = "0",
receive_pcs3.byte_order_pld_ctrl_enable = "false",
receive_pcs3.cdrctrl_bypass_ppm_detector_cycle = 1000,
receive_pcs3.cdrctrl_enable = "true",
receive_pcs3.cdrctrl_mask_cycle = 800,
receive_pcs3.cdrctrl_min_lock_to_ref_cycle = 63,
receive_pcs3.cdrctrl_rxvalid_mask = "true",
receive_pcs3.channel_bonding = "x4",
receive_pcs3.channel_number = ((starting_channel_number + 3) % 4),
receive_pcs3.channel_width = 16,
receive_pcs3.clk1_mux_select = "recovered clock",
receive_pcs3.clk2_mux_select = "digital reference clock",
receive_pcs3.core_clock_0ppm = "false",
receive_pcs3.datapath_low_latency_mode = "false",
receive_pcs3.datapath_protocol = "pipe",
receive_pcs3.dec_8b_10b_compatibility_mode = "true",
receive_pcs3.dec_8b_10b_mode = "normal",
receive_pcs3.dec_8b_10b_polarity_inv_enable = "true",
receive_pcs3.deskew_pattern = "0",
receive_pcs3.disable_auto_idle_insertion = "false",
receive_pcs3.disable_running_disp_in_word_align = "false",
receive_pcs3.disallow_kchar_after_pattern_ordered_set = "false",
receive_pcs3.dprio_config_mode = 6'h01,
receive_pcs3.elec_idle_infer_enable = "false",
receive_pcs3.elec_idle_num_com_detect = 3,
receive_pcs3.enable_bit_reversal = "false",
receive_pcs3.enable_deep_align = "false",
receive_pcs3.enable_deep_align_byte_swap = "false",
receive_pcs3.enable_self_test_mode = "false",
receive_pcs3.enable_true_complement_match_in_word_align = "false",
receive_pcs3.force_signal_detect_dig = "true",
receive_pcs3.hip_enable = "false",
receive_pcs3.infiniband_invalid_code = 0,
receive_pcs3.insert_pad_on_underflow = "false",
receive_pcs3.logical_channel_address = (starting_channel_number + 3),
receive_pcs3.num_align_code_groups_in_ordered_set = 0,
receive_pcs3.num_align_cons_good_data = 16,
receive_pcs3.num_align_cons_pat = 4,
receive_pcs3.num_align_loss_sync_error = 17,
receive_pcs3.ph_fifo_low_latency_enable = "true",
receive_pcs3.ph_fifo_reg_mode = "false",
receive_pcs3.ph_fifo_xn_mapping0 = "none",
receive_pcs3.ph_fifo_xn_mapping1 = "none",
receive_pcs3.ph_fifo_xn_mapping2 = "central",
receive_pcs3.ph_fifo_xn_select = 2,
receive_pcs3.pipe_auto_speed_nego_enable = "false",
receive_pcs3.pipe_freq_scale_mode = "Frequency",
receive_pcs3.pma_done_count = 250000,
receive_pcs3.protocol_hint = "pcie",
receive_pcs3.rate_match_almost_empty_threshold = 11,
receive_pcs3.rate_match_almost_full_threshold = 13,
receive_pcs3.rate_match_back_to_back = "false",
receive_pcs3.rate_match_delete_threshold = 13,
receive_pcs3.rate_match_empty_threshold = 5,
receive_pcs3.rate_match_fifo_mode = "true",
receive_pcs3.rate_match_full_threshold = 20,
receive_pcs3.rate_match_insert_threshold = 11,
receive_pcs3.rate_match_ordered_set_based = "false",
receive_pcs3.rate_match_pattern1 = "11010000111010000011",
receive_pcs3.rate_match_pattern2 = "00101111000101111100",
receive_pcs3.rate_match_pattern_size = 20,
receive_pcs3.rate_match_reset_enable = "false",
receive_pcs3.rate_match_skip_set_based = "true",
receive_pcs3.rate_match_start_threshold = 7,
receive_pcs3.rd_clk_mux_select = "core clock",
receive_pcs3.recovered_clk_mux_select = "recovered clock",
receive_pcs3.run_length = 40,
receive_pcs3.run_length_enable = "true",
receive_pcs3.rx_detect_bypass = "false",
receive_pcs3.rxstatus_error_report_mode = 0,
receive_pcs3.self_test_mode = "incremental",
receive_pcs3.use_alignment_state_machine = "true",
receive_pcs3.use_deserializer_double_data_mode = "false",
receive_pcs3.use_deskew_fifo = "false",
receive_pcs3.use_double_data_mode = "true",
receive_pcs3.use_parallel_loopback = "false",
receive_pcs3.use_rising_edge_triggered_pattern_align = "false",
receive_pcs3.lpm_type = "stratixiv_hssi_rx_pcs";
stratixiv_hssi_rx_pma receive_pma0
(
.adaptdone(),
.adcepowerdn(cent_unit_rxadcepowerdn[0]),
.adcereset(rx_rxadceresetout[0]),
.analogtestbus(),
.clockout(wire_receive_pma0_clockout),
.datain(rx_datain[0]),
.dataout(wire_receive_pma0_dataout),
.deserclock(rx_deserclock_in[3:0]),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pmadprioin_wire[299:0]),
.dprioout(wire_receive_pma0_dprioout),
.freqlock(1'b0),
.ignorephslck(1'b0),
.locktodata(rx_locktodata_wire[0]),
.locktoref(rx_locktorefclk_wire[0]),
.locktorefout(wire_receive_pma0_locktorefout),
.offsetcancellationen(1'b0),
.plllocked(rx_plllocked_wire[0]),
.powerdn(cent_unit_rxibpowerdn[0]),
.ppmdetectclkrel(),
.ppmdetectrefclk(rx_pll_pfdrefclkout_wire[0]),
.recoverdatain(pll_ch_dataout_wire[1:0]),
.recoverdataout(wire_receive_pma0_recoverdataout),
.reverselpbkout(),
.revserialfdbkout(),
.rxpmareset(rx_analogreset_out[0]),
.seriallpbken(1'b0),
.seriallpbkin(1'b0),
.signaldetect(wire_receive_pma0_signaldetect)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.adaptcapture(1'b0),
.adcestandby(1'b0),
.ppmdetectdividedclk(1'b0),
.testbussel({4{1'b0}})
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
receive_pma0.allow_serial_loopback = "false",
receive_pma0.channel_number = ((starting_channel_number + 0) % 4),
receive_pma0.channel_type = "auto",
receive_pma0.common_mode = "0.82V",
receive_pma0.deserialization_factor = 10,
receive_pma0.dprio_config_mode = 6'h01,
receive_pma0.eq_dc_gain = 3,
receive_pma0.eqa_ctrl = 0,
receive_pma0.eqb_ctrl = 0,
receive_pma0.eqc_ctrl = 0,
receive_pma0.eqd_ctrl = 0,
receive_pma0.eqv_ctrl = 0,
receive_pma0.force_signal_detect = "true",
receive_pma0.logical_channel_address = (starting_channel_number + 0),
receive_pma0.low_speed_test_select = 0,
receive_pma0.offset_cancellation = 0,
receive_pma0.protocol_hint = "pcie",
receive_pma0.send_direct_reverse_serial_loopback = "None",
receive_pma0.signal_detect_hysteresis_valid_threshold = 2,
receive_pma0.signal_detect_loss_threshold = 4,
receive_pma0.termination = "OCT 100 Ohms",
receive_pma0.use_deser_double_data_width = "false",
receive_pma0.use_pma_direct = "false",
receive_pma0.lpm_type = "stratixiv_hssi_rx_pma";
stratixiv_hssi_rx_pma receive_pma1
(
.adaptdone(),
.adcepowerdn(cent_unit_rxadcepowerdn[1]),
.adcereset(rx_rxadceresetout[1]),
.analogtestbus(),
.clockout(wire_receive_pma1_clockout),
.datain(rx_datain[1]),
.dataout(wire_receive_pma1_dataout),
.deserclock(rx_deserclock_in[7:4]),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pmadprioin_wire[599:300]),
.dprioout(wire_receive_pma1_dprioout),
.freqlock(1'b0),
.ignorephslck(1'b0),
.locktodata(rx_locktodata_wire[1]),
.locktoref(rx_locktorefclk_wire[1]),
.locktorefout(wire_receive_pma1_locktorefout),
.offsetcancellationen(1'b0),
.plllocked(rx_plllocked_wire[1]),
.powerdn(cent_unit_rxibpowerdn[1]),
.ppmdetectclkrel(),
.ppmdetectrefclk(rx_pll_pfdrefclkout_wire[1]),
.recoverdatain(pll_ch_dataout_wire[3:2]),
.recoverdataout(wire_receive_pma1_recoverdataout),
.reverselpbkout(),
.revserialfdbkout(),
.rxpmareset(rx_analogreset_out[1]),
.seriallpbken(1'b0),
.seriallpbkin(1'b0),
.signaldetect(wire_receive_pma1_signaldetect)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.adaptcapture(1'b0),
.adcestandby(1'b0),
.ppmdetectdividedclk(1'b0),
.testbussel({4{1'b0}})
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
receive_pma1.allow_serial_loopback = "false",
receive_pma1.channel_number = ((starting_channel_number + 1) % 4),
receive_pma1.channel_type = "auto",
receive_pma1.common_mode = "0.82V",
receive_pma1.deserialization_factor = 10,
receive_pma1.dprio_config_mode = 6'h01,
receive_pma1.eq_dc_gain = 3,
receive_pma1.eqa_ctrl = 0,
receive_pma1.eqb_ctrl = 0,
receive_pma1.eqc_ctrl = 0,
receive_pma1.eqd_ctrl = 0,
receive_pma1.eqv_ctrl = 0,
receive_pma1.force_signal_detect = "true",
receive_pma1.logical_channel_address = (starting_channel_number + 1),
receive_pma1.low_speed_test_select = 0,
receive_pma1.offset_cancellation = 0,
receive_pma1.protocol_hint = "pcie",
receive_pma1.send_direct_reverse_serial_loopback = "None",
receive_pma1.signal_detect_hysteresis_valid_threshold = 2,
receive_pma1.signal_detect_loss_threshold = 4,
receive_pma1.termination = "OCT 100 Ohms",
receive_pma1.use_deser_double_data_width = "false",
receive_pma1.use_pma_direct = "false",
receive_pma1.lpm_type = "stratixiv_hssi_rx_pma";
stratixiv_hssi_rx_pma receive_pma2
(
.adaptdone(),
.adcepowerdn(cent_unit_rxadcepowerdn[2]),
.adcereset(rx_rxadceresetout[2]),
.analogtestbus(),
.clockout(wire_receive_pma2_clockout),
.datain(rx_datain[2]),
.dataout(wire_receive_pma2_dataout),
.deserclock(rx_deserclock_in[11:8]),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pmadprioin_wire[899:600]),
.dprioout(wire_receive_pma2_dprioout),
.freqlock(1'b0),
.ignorephslck(1'b0),
.locktodata(rx_locktodata_wire[2]),
.locktoref(rx_locktorefclk_wire[2]),
.locktorefout(wire_receive_pma2_locktorefout),
.offsetcancellationen(1'b0),
.plllocked(rx_plllocked_wire[2]),
.powerdn(cent_unit_rxibpowerdn[2]),
.ppmdetectclkrel(),
.ppmdetectrefclk(rx_pll_pfdrefclkout_wire[2]),
.recoverdatain(pll_ch_dataout_wire[5:4]),
.recoverdataout(wire_receive_pma2_recoverdataout),
.reverselpbkout(),
.revserialfdbkout(),
.rxpmareset(rx_analogreset_out[2]),
.seriallpbken(1'b0),
.seriallpbkin(1'b0),
.signaldetect(wire_receive_pma2_signaldetect)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.adaptcapture(1'b0),
.adcestandby(1'b0),
.ppmdetectdividedclk(1'b0),
.testbussel({4{1'b0}})
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
receive_pma2.allow_serial_loopback = "false",
receive_pma2.channel_number = ((starting_channel_number + 2) % 4),
receive_pma2.channel_type = "auto",
receive_pma2.common_mode = "0.82V",
receive_pma2.deserialization_factor = 10,
receive_pma2.dprio_config_mode = 6'h01,
receive_pma2.eq_dc_gain = 3,
receive_pma2.eqa_ctrl = 0,
receive_pma2.eqb_ctrl = 0,
receive_pma2.eqc_ctrl = 0,
receive_pma2.eqd_ctrl = 0,
receive_pma2.eqv_ctrl = 0,
receive_pma2.force_signal_detect = "true",
receive_pma2.logical_channel_address = (starting_channel_number + 2),
receive_pma2.low_speed_test_select = 0,
receive_pma2.offset_cancellation = 0,
receive_pma2.protocol_hint = "pcie",
receive_pma2.send_direct_reverse_serial_loopback = "None",
receive_pma2.signal_detect_hysteresis_valid_threshold = 2,
receive_pma2.signal_detect_loss_threshold = 4,
receive_pma2.termination = "OCT 100 Ohms",
receive_pma2.use_deser_double_data_width = "false",
receive_pma2.use_pma_direct = "false",
receive_pma2.lpm_type = "stratixiv_hssi_rx_pma";
stratixiv_hssi_rx_pma receive_pma3
(
.adaptdone(),
.adcepowerdn(cent_unit_rxadcepowerdn[3]),
.adcereset(rx_rxadceresetout[3]),
.analogtestbus(),
.clockout(wire_receive_pma3_clockout),
.datain(rx_datain[3]),
.dataout(wire_receive_pma3_dataout),
.deserclock(rx_deserclock_in[15:12]),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pmadprioin_wire[1199:900]),
.dprioout(wire_receive_pma3_dprioout),
.freqlock(1'b0),
.ignorephslck(1'b0),
.locktodata(rx_locktodata_wire[3]),
.locktoref(rx_locktorefclk_wire[3]),
.locktorefout(wire_receive_pma3_locktorefout),
.offsetcancellationen(1'b0),
.plllocked(rx_plllocked_wire[3]),
.powerdn(cent_unit_rxibpowerdn[3]),
.ppmdetectclkrel(),
.ppmdetectrefclk(rx_pll_pfdrefclkout_wire[3]),
.recoverdatain(pll_ch_dataout_wire[7:6]),
.recoverdataout(wire_receive_pma3_recoverdataout),
.reverselpbkout(),
.revserialfdbkout(),
.rxpmareset(rx_analogreset_out[3]),
.seriallpbken(1'b0),
.seriallpbkin(1'b0),
.signaldetect(wire_receive_pma3_signaldetect)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.adaptcapture(1'b0),
.adcestandby(1'b0),
.ppmdetectdividedclk(1'b0),
.testbussel({4{1'b0}})
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
receive_pma3.allow_serial_loopback = "false",
receive_pma3.channel_number = ((starting_channel_number + 3) % 4),
receive_pma3.channel_type = "auto",
receive_pma3.common_mode = "0.82V",
receive_pma3.deserialization_factor = 10,
receive_pma3.dprio_config_mode = 6'h01,
receive_pma3.eq_dc_gain = 3,
receive_pma3.eqa_ctrl = 0,
receive_pma3.eqb_ctrl = 0,
receive_pma3.eqc_ctrl = 0,
receive_pma3.eqd_ctrl = 0,
receive_pma3.eqv_ctrl = 0,
receive_pma3.force_signal_detect = "true",
receive_pma3.logical_channel_address = (starting_channel_number + 3),
receive_pma3.low_speed_test_select = 0,
receive_pma3.offset_cancellation = 0,
receive_pma3.protocol_hint = "pcie",
receive_pma3.send_direct_reverse_serial_loopback = "None",
receive_pma3.signal_detect_hysteresis_valid_threshold = 2,
receive_pma3.signal_detect_loss_threshold = 4,
receive_pma3.termination = "OCT 100 Ohms",
receive_pma3.use_deser_double_data_width = "false",
receive_pma3.use_pma_direct = "false",
receive_pma3.lpm_type = "stratixiv_hssi_rx_pma";
stratixiv_hssi_tx_pcs transmit_pcs0
(
.clkout(wire_transmit_pcs0_clkout),
.coreclk(tx_coreclk_in[0]),
.coreclkout(wire_transmit_pcs0_coreclkout),
.ctrlenable({{2{1'b0}}, tx_ctrlenable[1:0]}),
.datain({{24{1'b0}}, tx_datain_wire[15:0]}),
.datainfull(tx_datainfull[43:0]),
.dataout(wire_transmit_pcs0_dataout),
.detectrxloop(tx_detectrxloop[0]),
.digitalreset(tx_digitalreset_out[0]),
.dispval({{3{1'b0}}, tx_forceelecidle[0]}),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_dprioin_wire[149:0]),
.dprioout(wire_transmit_pcs0_dprioout),
.enrevparallellpbk(tx_revparallellpbken[0]),
.forcedisp({{2{1'b0}}, tx_forcedisp_wire[1:0]}),
.forcedispcompliance(1'b0),
.forceelecidle(tx_forceelecidle[0]),
.grayelecidleinferselout(),
.hiptxclkout(),
.invpol(tx_invpolarity[0]),
.iqpphfifobyteselout(),
.iqpphfifordclkout(),
.iqpphfifordenableout(),
.iqpphfifowrenableout(),
.localrefclk(tx_localrefclk[0]),
.parallelfdbkout(),
.phfifobyteselout(),
.phfifobyteserdisable(int_rx_phfifobyteserdisable[0]),
.phfifooverflow(),
.phfifoptrsreset(int_rx_phfifoptrsresetout[0]),
.phfifordclkout(),
.phfiforddisable(1'b0),
.phfiforddisableout(wire_transmit_pcs0_phfiforddisableout),
.phfifordenableout(),
.phfiforeset(tx_phfiforeset[0]),
.phfiforesetout(wire_transmit_pcs0_phfiforesetout),
.phfifounderflow(),
.phfifowrenable(1'b1),
.phfifowrenableout(wire_transmit_pcs0_phfifowrenableout),
.phfifoxnbytesel(int_tx_phfifoxnbytesel[2:0]),
.phfifoxnrdclk(int_tx_phfifoxnrdclk[2:0]),
.phfifoxnrdenable(int_tx_phfifoxnrdenable[2:0]),
.phfifoxnwrenable(int_tx_phfifoxnwrenable[2:0]),
.pipeenrevparallellpbkout(),
.pipepowerdownout(wire_transmit_pcs0_pipepowerdownout),
.pipepowerstateout(wire_transmit_pcs0_pipepowerstateout),
.pipestatetransdone(rx_pipestatetransdoneout[0]),
.pipetxdeemph(tx_pipedeemph[0]),
.pipetxmargin(tx_pipemargin[2:0]),
.pipetxswing(tx_pipeswing[0]),
.powerdn(powerdn[1:0]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitchout(),
.rdenablesync(),
.refclk(refclk_pma[0]),
.revparallelfdbk(rx_revparallelfdbkdata[19:0]),
.txdetectrx(wire_transmit_pcs0_txdetectrx),
.xgmctrl(cent_unit_txctrlout[0]),
.xgmctrlenable(),
.xgmdatain(cent_unit_tx_xgmdataout[7:0]),
.xgmdataout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.analogreset(1'b0),
.bitslipboundaryselect({5{1'b0}}),
.elecidleinfersel({3{1'b0}}),
.freezptr(1'b0),
.hipdatain({10{1'b0}}),
.hipdetectrxloop(1'b0),
.hipelecidleinfersel({3{1'b0}}),
.hipforceelecidle(1'b0),
.hippowerdn({2{1'b0}}),
.hiptxdeemph(1'b0),
.hiptxmargin({3{1'b0}}),
.iqpphfifoxnbytesel({2{1'b0}}),
.iqpphfifoxnrdclk({2{1'b0}}),
.iqpphfifoxnrdenable({2{1'b0}}),
.iqpphfifoxnwrenable({2{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdclk(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrenable(1'b0),
.phfifoxnbottombytesel(1'b0),
.phfifoxnbottomrdclk(1'b0),
.phfifoxnbottomrdenable(1'b0),
.phfifoxnbottomwrenable(1'b0),
.phfifoxnptrsreset({3{1'b0}}),
.phfifoxntopbytesel(1'b0),
.phfifoxntoprdclk(1'b0),
.phfifoxntoprdenable(1'b0),
.phfifoxntopwrenable(1'b0),
.prbscidenable(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rateswitchxndone(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
transmit_pcs0.allow_polarity_inversion = "false",
transmit_pcs0.auto_spd_self_switch_enable = "false",
transmit_pcs0.channel_bonding = "x4",
transmit_pcs0.channel_number = ((starting_channel_number + 0) % 4),
transmit_pcs0.channel_width = 16,
transmit_pcs0.core_clock_0ppm = "false",
transmit_pcs0.datapath_low_latency_mode = "false",
transmit_pcs0.datapath_protocol = "pipe",
transmit_pcs0.disable_ph_low_latency_mode = "false",
transmit_pcs0.disparity_mode = "new",
transmit_pcs0.dprio_config_mode = 6'h01,
transmit_pcs0.elec_idle_delay = 6,
transmit_pcs0.enable_bit_reversal = "false",
transmit_pcs0.enable_idle_selection = "false",
transmit_pcs0.enable_reverse_parallel_loopback = "true",
transmit_pcs0.enable_self_test_mode = "false",
transmit_pcs0.enable_symbol_swap = "false",
transmit_pcs0.enc_8b_10b_compatibility_mode = "true",
transmit_pcs0.enc_8b_10b_mode = "normal",
transmit_pcs0.force_echar = "false",
transmit_pcs0.force_kchar = "false",
transmit_pcs0.hip_enable = "false",
transmit_pcs0.logical_channel_address = (starting_channel_number + 0),
transmit_pcs0.ph_fifo_reg_mode = "false",
transmit_pcs0.ph_fifo_xn_mapping0 = "none",
transmit_pcs0.ph_fifo_xn_mapping1 = "none",
transmit_pcs0.ph_fifo_xn_mapping2 = "central",
transmit_pcs0.ph_fifo_xn_select = 2,
transmit_pcs0.pipe_auto_speed_nego_enable = "false",
transmit_pcs0.pipe_freq_scale_mode = "Frequency",
transmit_pcs0.prbs_cid_pattern = "false",
transmit_pcs0.protocol_hint = "pcie",
transmit_pcs0.refclk_select = "cmu_clock_divider",
transmit_pcs0.self_test_mode = "incremental",
transmit_pcs0.use_double_data_mode = "true",
transmit_pcs0.use_serializer_double_data_mode = "false",
transmit_pcs0.wr_clk_mux_select = "core_clk",
transmit_pcs0.lpm_type = "stratixiv_hssi_tx_pcs";
stratixiv_hssi_tx_pcs transmit_pcs1
(
.clkout(wire_transmit_pcs1_clkout),
.coreclk(tx_coreclk_in[1]),
.coreclkout(wire_transmit_pcs1_coreclkout),
.ctrlenable({{2{1'b0}}, tx_ctrlenable[3:2]}),
.datain({{24{1'b0}}, tx_datain_wire[31:16]}),
.datainfull(tx_datainfull[87:44]),
.dataout(wire_transmit_pcs1_dataout),
.detectrxloop(tx_detectrxloop[1]),
.digitalreset(tx_digitalreset_out[1]),
.dispval({{3{1'b0}}, tx_forceelecidle[1]}),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_dprioin_wire[299:150]),
.dprioout(wire_transmit_pcs1_dprioout),
.enrevparallellpbk(tx_revparallellpbken[1]),
.forcedisp({{2{1'b0}}, tx_forcedisp_wire[3:2]}),
.forcedispcompliance(1'b0),
.forceelecidle(tx_forceelecidle[1]),
.grayelecidleinferselout(),
.hiptxclkout(),
.invpol(tx_invpolarity[1]),
.iqpphfifobyteselout(),
.iqpphfifordclkout(),
.iqpphfifordenableout(),
.iqpphfifowrenableout(),
.localrefclk(tx_localrefclk[1]),
.parallelfdbkout(),
.phfifobyteselout(),
.phfifobyteserdisable(int_rx_phfifobyteserdisable[1]),
.phfifooverflow(),
.phfifoptrsreset(int_rx_phfifoptrsresetout[1]),
.phfifordclkout(),
.phfiforddisable(1'b0),
.phfiforddisableout(wire_transmit_pcs1_phfiforddisableout),
.phfifordenableout(),
.phfiforeset(tx_phfiforeset[1]),
.phfiforesetout(wire_transmit_pcs1_phfiforesetout),
.phfifounderflow(),
.phfifowrenable(1'b1),
.phfifowrenableout(wire_transmit_pcs1_phfifowrenableout),
.phfifoxnbytesel(int_tx_phfifoxnbytesel[5:3]),
.phfifoxnrdclk(int_tx_phfifoxnrdclk[5:3]),
.phfifoxnrdenable(int_tx_phfifoxnrdenable[5:3]),
.phfifoxnwrenable(int_tx_phfifoxnwrenable[5:3]),
.pipeenrevparallellpbkout(),
.pipepowerdownout(wire_transmit_pcs1_pipepowerdownout),
.pipepowerstateout(wire_transmit_pcs1_pipepowerstateout),
.pipestatetransdone(rx_pipestatetransdoneout[1]),
.pipetxdeemph(tx_pipedeemph[1]),
.pipetxmargin(tx_pipemargin[5:3]),
.pipetxswing(tx_pipeswing[1]),
.powerdn(powerdn[3:2]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitchout(),
.rdenablesync(),
.refclk(refclk_pma[0]),
.revparallelfdbk(rx_revparallelfdbkdata[39:20]),
.txdetectrx(wire_transmit_pcs1_txdetectrx),
.xgmctrl(cent_unit_txctrlout[1]),
.xgmctrlenable(),
.xgmdatain(cent_unit_tx_xgmdataout[15:8]),
.xgmdataout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.analogreset(1'b0),
.bitslipboundaryselect({5{1'b0}}),
.elecidleinfersel({3{1'b0}}),
.freezptr(1'b0),
.hipdatain({10{1'b0}}),
.hipdetectrxloop(1'b0),
.hipelecidleinfersel({3{1'b0}}),
.hipforceelecidle(1'b0),
.hippowerdn({2{1'b0}}),
.hiptxdeemph(1'b0),
.hiptxmargin({3{1'b0}}),
.iqpphfifoxnbytesel({2{1'b0}}),
.iqpphfifoxnrdclk({2{1'b0}}),
.iqpphfifoxnrdenable({2{1'b0}}),
.iqpphfifoxnwrenable({2{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdclk(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrenable(1'b0),
.phfifoxnbottombytesel(1'b0),
.phfifoxnbottomrdclk(1'b0),
.phfifoxnbottomrdenable(1'b0),
.phfifoxnbottomwrenable(1'b0),
.phfifoxnptrsreset({3{1'b0}}),
.phfifoxntopbytesel(1'b0),
.phfifoxntoprdclk(1'b0),
.phfifoxntoprdenable(1'b0),
.phfifoxntopwrenable(1'b0),
.prbscidenable(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rateswitchxndone(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
transmit_pcs1.allow_polarity_inversion = "false",
transmit_pcs1.auto_spd_self_switch_enable = "false",
transmit_pcs1.channel_bonding = "x4",
transmit_pcs1.channel_number = ((starting_channel_number + 1) % 4),
transmit_pcs1.channel_width = 16,
transmit_pcs1.core_clock_0ppm = "false",
transmit_pcs1.datapath_low_latency_mode = "false",
transmit_pcs1.datapath_protocol = "pipe",
transmit_pcs1.disable_ph_low_latency_mode = "false",
transmit_pcs1.disparity_mode = "new",
transmit_pcs1.dprio_config_mode = 6'h01,
transmit_pcs1.elec_idle_delay = 6,
transmit_pcs1.enable_bit_reversal = "false",
transmit_pcs1.enable_idle_selection = "false",
transmit_pcs1.enable_reverse_parallel_loopback = "true",
transmit_pcs1.enable_self_test_mode = "false",
transmit_pcs1.enable_symbol_swap = "false",
transmit_pcs1.enc_8b_10b_compatibility_mode = "true",
transmit_pcs1.enc_8b_10b_mode = "normal",
transmit_pcs1.force_echar = "false",
transmit_pcs1.force_kchar = "false",
transmit_pcs1.hip_enable = "false",
transmit_pcs1.logical_channel_address = (starting_channel_number + 1),
transmit_pcs1.ph_fifo_reg_mode = "false",
transmit_pcs1.ph_fifo_xn_mapping0 = "none",
transmit_pcs1.ph_fifo_xn_mapping1 = "none",
transmit_pcs1.ph_fifo_xn_mapping2 = "central",
transmit_pcs1.ph_fifo_xn_select = 2,
transmit_pcs1.pipe_auto_speed_nego_enable = "false",
transmit_pcs1.pipe_freq_scale_mode = "Frequency",
transmit_pcs1.prbs_cid_pattern = "false",
transmit_pcs1.protocol_hint = "pcie",
transmit_pcs1.refclk_select = "cmu_clock_divider",
transmit_pcs1.self_test_mode = "incremental",
transmit_pcs1.use_double_data_mode = "true",
transmit_pcs1.use_serializer_double_data_mode = "false",
transmit_pcs1.wr_clk_mux_select = "core_clk",
transmit_pcs1.lpm_type = "stratixiv_hssi_tx_pcs";
stratixiv_hssi_tx_pcs transmit_pcs2
(
.clkout(wire_transmit_pcs2_clkout),
.coreclk(tx_coreclk_in[2]),
.coreclkout(wire_transmit_pcs2_coreclkout),
.ctrlenable({{2{1'b0}}, tx_ctrlenable[5:4]}),
.datain({{24{1'b0}}, tx_datain_wire[47:32]}),
.datainfull(tx_datainfull[131:88]),
.dataout(wire_transmit_pcs2_dataout),
.detectrxloop(tx_detectrxloop[2]),
.digitalreset(tx_digitalreset_out[2]),
.dispval({{3{1'b0}}, tx_forceelecidle[2]}),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_dprioin_wire[449:300]),
.dprioout(wire_transmit_pcs2_dprioout),
.enrevparallellpbk(tx_revparallellpbken[2]),
.forcedisp({{2{1'b0}}, tx_forcedisp_wire[5:4]}),
.forcedispcompliance(1'b0),
.forceelecidle(tx_forceelecidle[2]),
.grayelecidleinferselout(),
.hiptxclkout(),
.invpol(tx_invpolarity[2]),
.iqpphfifobyteselout(),
.iqpphfifordclkout(),
.iqpphfifordenableout(),
.iqpphfifowrenableout(),
.localrefclk(tx_localrefclk[2]),
.parallelfdbkout(),
.phfifobyteselout(),
.phfifobyteserdisable(int_rx_phfifobyteserdisable[2]),
.phfifooverflow(),
.phfifoptrsreset(int_rx_phfifoptrsresetout[2]),
.phfifordclkout(),
.phfiforddisable(1'b0),
.phfiforddisableout(wire_transmit_pcs2_phfiforddisableout),
.phfifordenableout(),
.phfiforeset(tx_phfiforeset[2]),
.phfiforesetout(wire_transmit_pcs2_phfiforesetout),
.phfifounderflow(),
.phfifowrenable(1'b1),
.phfifowrenableout(wire_transmit_pcs2_phfifowrenableout),
.phfifoxnbytesel(int_tx_phfifoxnbytesel[8:6]),
.phfifoxnrdclk(int_tx_phfifoxnrdclk[8:6]),
.phfifoxnrdenable(int_tx_phfifoxnrdenable[8:6]),
.phfifoxnwrenable(int_tx_phfifoxnwrenable[8:6]),
.pipeenrevparallellpbkout(),
.pipepowerdownout(wire_transmit_pcs2_pipepowerdownout),
.pipepowerstateout(wire_transmit_pcs2_pipepowerstateout),
.pipestatetransdone(rx_pipestatetransdoneout[2]),
.pipetxdeemph(tx_pipedeemph[2]),
.pipetxmargin(tx_pipemargin[8:6]),
.pipetxswing(tx_pipeswing[2]),
.powerdn(powerdn[5:4]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitchout(),
.rdenablesync(),
.refclk(refclk_pma[0]),
.revparallelfdbk(rx_revparallelfdbkdata[59:40]),
.txdetectrx(wire_transmit_pcs2_txdetectrx),
.xgmctrl(cent_unit_txctrlout[2]),
.xgmctrlenable(),
.xgmdatain(cent_unit_tx_xgmdataout[23:16]),
.xgmdataout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.analogreset(1'b0),
.bitslipboundaryselect({5{1'b0}}),
.elecidleinfersel({3{1'b0}}),
.freezptr(1'b0),
.hipdatain({10{1'b0}}),
.hipdetectrxloop(1'b0),
.hipelecidleinfersel({3{1'b0}}),
.hipforceelecidle(1'b0),
.hippowerdn({2{1'b0}}),
.hiptxdeemph(1'b0),
.hiptxmargin({3{1'b0}}),
.iqpphfifoxnbytesel({2{1'b0}}),
.iqpphfifoxnrdclk({2{1'b0}}),
.iqpphfifoxnrdenable({2{1'b0}}),
.iqpphfifoxnwrenable({2{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdclk(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrenable(1'b0),
.phfifoxnbottombytesel(1'b0),
.phfifoxnbottomrdclk(1'b0),
.phfifoxnbottomrdenable(1'b0),
.phfifoxnbottomwrenable(1'b0),
.phfifoxnptrsreset({3{1'b0}}),
.phfifoxntopbytesel(1'b0),
.phfifoxntoprdclk(1'b0),
.phfifoxntoprdenable(1'b0),
.phfifoxntopwrenable(1'b0),
.prbscidenable(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rateswitchxndone(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
transmit_pcs2.allow_polarity_inversion = "false",
transmit_pcs2.auto_spd_self_switch_enable = "false",
transmit_pcs2.channel_bonding = "x4",
transmit_pcs2.channel_number = ((starting_channel_number + 2) % 4),
transmit_pcs2.channel_width = 16,
transmit_pcs2.core_clock_0ppm = "false",
transmit_pcs2.datapath_low_latency_mode = "false",
transmit_pcs2.datapath_protocol = "pipe",
transmit_pcs2.disable_ph_low_latency_mode = "false",
transmit_pcs2.disparity_mode = "new",
transmit_pcs2.dprio_config_mode = 6'h01,
transmit_pcs2.elec_idle_delay = 6,
transmit_pcs2.enable_bit_reversal = "false",
transmit_pcs2.enable_idle_selection = "false",
transmit_pcs2.enable_reverse_parallel_loopback = "true",
transmit_pcs2.enable_self_test_mode = "false",
transmit_pcs2.enable_symbol_swap = "false",
transmit_pcs2.enc_8b_10b_compatibility_mode = "true",
transmit_pcs2.enc_8b_10b_mode = "normal",
transmit_pcs2.force_echar = "false",
transmit_pcs2.force_kchar = "false",
transmit_pcs2.hip_enable = "false",
transmit_pcs2.logical_channel_address = (starting_channel_number + 2),
transmit_pcs2.ph_fifo_reg_mode = "false",
transmit_pcs2.ph_fifo_xn_mapping0 = "none",
transmit_pcs2.ph_fifo_xn_mapping1 = "none",
transmit_pcs2.ph_fifo_xn_mapping2 = "central",
transmit_pcs2.ph_fifo_xn_select = 2,
transmit_pcs2.pipe_auto_speed_nego_enable = "false",
transmit_pcs2.pipe_freq_scale_mode = "Frequency",
transmit_pcs2.prbs_cid_pattern = "false",
transmit_pcs2.protocol_hint = "pcie",
transmit_pcs2.refclk_select = "cmu_clock_divider",
transmit_pcs2.self_test_mode = "incremental",
transmit_pcs2.use_double_data_mode = "true",
transmit_pcs2.use_serializer_double_data_mode = "false",
transmit_pcs2.wr_clk_mux_select = "core_clk",
transmit_pcs2.lpm_type = "stratixiv_hssi_tx_pcs";
stratixiv_hssi_tx_pcs transmit_pcs3
(
.clkout(wire_transmit_pcs3_clkout),
.coreclk(tx_coreclk_in[3]),
.coreclkout(wire_transmit_pcs3_coreclkout),
.ctrlenable({{2{1'b0}}, tx_ctrlenable[7:6]}),
.datain({{24{1'b0}}, tx_datain_wire[63:48]}),
.datainfull(tx_datainfull[175:132]),
.dataout(wire_transmit_pcs3_dataout),
.detectrxloop(tx_detectrxloop[3]),
.digitalreset(tx_digitalreset_out[3]),
.dispval({{3{1'b0}}, tx_forceelecidle[3]}),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_dprioin_wire[599:450]),
.dprioout(wire_transmit_pcs3_dprioout),
.enrevparallellpbk(tx_revparallellpbken[3]),
.forcedisp({{2{1'b0}}, tx_forcedisp_wire[7:6]}),
.forcedispcompliance(1'b0),
.forceelecidle(tx_forceelecidle[3]),
.grayelecidleinferselout(),
.hiptxclkout(),
.invpol(tx_invpolarity[3]),
.iqpphfifobyteselout(),
.iqpphfifordclkout(),
.iqpphfifordenableout(),
.iqpphfifowrenableout(),
.localrefclk(tx_localrefclk[3]),
.parallelfdbkout(),
.phfifobyteselout(),
.phfifobyteserdisable(int_rx_phfifobyteserdisable[3]),
.phfifooverflow(),
.phfifoptrsreset(int_rx_phfifoptrsresetout[3]),
.phfifordclkout(),
.phfiforddisable(1'b0),
.phfiforddisableout(wire_transmit_pcs3_phfiforddisableout),
.phfifordenableout(),
.phfiforeset(tx_phfiforeset[3]),
.phfiforesetout(wire_transmit_pcs3_phfiforesetout),
.phfifounderflow(),
.phfifowrenable(1'b1),
.phfifowrenableout(wire_transmit_pcs3_phfifowrenableout),
.phfifoxnbytesel(int_tx_phfifoxnbytesel[11:9]),
.phfifoxnrdclk(int_tx_phfifoxnrdclk[11:9]),
.phfifoxnrdenable(int_tx_phfifoxnrdenable[11:9]),
.phfifoxnwrenable(int_tx_phfifoxnwrenable[11:9]),
.pipeenrevparallellpbkout(),
.pipepowerdownout(wire_transmit_pcs3_pipepowerdownout),
.pipepowerstateout(wire_transmit_pcs3_pipepowerstateout),
.pipestatetransdone(rx_pipestatetransdoneout[3]),
.pipetxdeemph(tx_pipedeemph[3]),
.pipetxmargin(tx_pipemargin[11:9]),
.pipetxswing(tx_pipeswing[3]),
.powerdn(powerdn[7:6]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitchout(),
.rdenablesync(),
.refclk(refclk_pma[0]),
.revparallelfdbk(rx_revparallelfdbkdata[79:60]),
.txdetectrx(wire_transmit_pcs3_txdetectrx),
.xgmctrl(cent_unit_txctrlout[3]),
.xgmctrlenable(),
.xgmdatain(cent_unit_tx_xgmdataout[31:24]),
.xgmdataout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.analogreset(1'b0),
.bitslipboundaryselect({5{1'b0}}),
.elecidleinfersel({3{1'b0}}),
.freezptr(1'b0),
.hipdatain({10{1'b0}}),
.hipdetectrxloop(1'b0),
.hipelecidleinfersel({3{1'b0}}),
.hipforceelecidle(1'b0),
.hippowerdn({2{1'b0}}),
.hiptxdeemph(1'b0),
.hiptxmargin({3{1'b0}}),
.iqpphfifoxnbytesel({2{1'b0}}),
.iqpphfifoxnrdclk({2{1'b0}}),
.iqpphfifoxnrdenable({2{1'b0}}),
.iqpphfifoxnwrenable({2{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdclk(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrenable(1'b0),
.phfifoxnbottombytesel(1'b0),
.phfifoxnbottomrdclk(1'b0),
.phfifoxnbottomrdenable(1'b0),
.phfifoxnbottomwrenable(1'b0),
.phfifoxnptrsreset({3{1'b0}}),
.phfifoxntopbytesel(1'b0),
.phfifoxntoprdclk(1'b0),
.phfifoxntoprdenable(1'b0),
.phfifoxntopwrenable(1'b0),
.prbscidenable(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rateswitchxndone(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
transmit_pcs3.allow_polarity_inversion = "false",
transmit_pcs3.auto_spd_self_switch_enable = "false",
transmit_pcs3.channel_bonding = "x4",
transmit_pcs3.channel_number = ((starting_channel_number + 3) % 4),
transmit_pcs3.channel_width = 16,
transmit_pcs3.core_clock_0ppm = "false",
transmit_pcs3.datapath_low_latency_mode = "false",
transmit_pcs3.datapath_protocol = "pipe",
transmit_pcs3.disable_ph_low_latency_mode = "false",
transmit_pcs3.disparity_mode = "new",
transmit_pcs3.dprio_config_mode = 6'h01,
transmit_pcs3.elec_idle_delay = 6,
transmit_pcs3.enable_bit_reversal = "false",
transmit_pcs3.enable_idle_selection = "false",
transmit_pcs3.enable_reverse_parallel_loopback = "true",
transmit_pcs3.enable_self_test_mode = "false",
transmit_pcs3.enable_symbol_swap = "false",
transmit_pcs3.enc_8b_10b_compatibility_mode = "true",
transmit_pcs3.enc_8b_10b_mode = "normal",
transmit_pcs3.force_echar = "false",
transmit_pcs3.force_kchar = "false",
transmit_pcs3.hip_enable = "false",
transmit_pcs3.logical_channel_address = (starting_channel_number + 3),
transmit_pcs3.ph_fifo_reg_mode = "false",
transmit_pcs3.ph_fifo_xn_mapping0 = "none",
transmit_pcs3.ph_fifo_xn_mapping1 = "none",
transmit_pcs3.ph_fifo_xn_mapping2 = "central",
transmit_pcs3.ph_fifo_xn_select = 2,
transmit_pcs3.pipe_auto_speed_nego_enable = "false",
transmit_pcs3.pipe_freq_scale_mode = "Frequency",
transmit_pcs3.prbs_cid_pattern = "false",
transmit_pcs3.protocol_hint = "pcie",
transmit_pcs3.refclk_select = "cmu_clock_divider",
transmit_pcs3.self_test_mode = "incremental",
transmit_pcs3.use_double_data_mode = "true",
transmit_pcs3.use_serializer_double_data_mode = "false",
transmit_pcs3.wr_clk_mux_select = "core_clk",
transmit_pcs3.lpm_type = "stratixiv_hssi_tx_pcs";
stratixiv_hssi_tx_pma transmit_pma0
(
.clockout(wire_transmit_pma0_clockout),
.datain({44'b00000000000000000000000000000000000000000000, tx_dataout_pcs_to_pma[19:0]}),
.dataout(wire_transmit_pma0_dataout),
.detectrxpowerdown(cent_unit_txdetectrxpowerdn[0]),
.dftout(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_pmadprioin_wire[299:0]),
.dprioout(wire_transmit_pma0_dprioout),
.fastrefclk0in({2{1'b0}}),
.fastrefclk1in(cmu_analogfastrefclkout[1:0]),
.fastrefclk2in({2{1'b0}}),
.fastrefclk3in({2{1'b0}}),
.fastrefclk4in(1'b0),
.forceelecidle(tx_forceelecidle[0]),
.powerdn(cent_unit_txobpowerdn[0]),
.refclk0in({2{1'b0}}),
.refclk0inpulse(1'b0),
.refclk1in(cmu_analogrefclkout[1:0]),
.refclk1inpulse(cmu_analogrefclkpulse[0]),
.refclk2in({2{1'b0}}),
.refclk2inpulse(1'b0),
.refclk3in({2{1'b0}}),
.refclk3inpulse(1'b0),
.refclk4in(1'b0),
.refclk4inpulse(1'b0),
.revserialfdbk(1'b0),
.rxdetecten(txdetectrxout[0]),
.rxdetectvalidout(wire_transmit_pma0_rxdetectvalidout),
.rxfoundout(wire_transmit_pma0_rxfoundout),
.seriallpbkout(),
.txpmareset(tx_analogreset_out[0])
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.pclk(1'b0),
.rxdetectclk(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
transmit_pma0.analog_power = "1.4V",
transmit_pma0.channel_number = ((starting_channel_number + 0) % 4),
transmit_pma0.channel_type = "auto",
transmit_pma0.clkin_select = 1,
transmit_pma0.clkmux_delay = "false",
transmit_pma0.common_mode = "0.65V",
transmit_pma0.dprio_config_mode = 6'h01,
transmit_pma0.enable_reverse_serial_loopback = "false",
transmit_pma0.logical_channel_address = (starting_channel_number + 0),
transmit_pma0.low_speed_test_select = 0,
transmit_pma0.preemp_pretap = 0,
transmit_pma0.preemp_pretap_inv = "false",
transmit_pma0.preemp_tap_1 = 3,
transmit_pma0.preemp_tap_2 = 0,
transmit_pma0.preemp_tap_2_inv = "false",
transmit_pma0.protocol_hint = "pcie",
transmit_pma0.rx_detect = 0,
transmit_pma0.serialization_factor = 10,
transmit_pma0.slew_rate = "off",
transmit_pma0.termination = "OCT 100 Ohms",
transmit_pma0.use_pma_direct = "false",
transmit_pma0.use_ser_double_data_mode = "false",
transmit_pma0.vod_selection = 4,
transmit_pma0.lpm_type = "stratixiv_hssi_tx_pma";
stratixiv_hssi_tx_pma transmit_pma1
(
.clockout(wire_transmit_pma1_clockout),
.datain({44'b00000000000000000000000000000000000000000000, tx_dataout_pcs_to_pma[39:20]}),
.dataout(wire_transmit_pma1_dataout),
.detectrxpowerdown(cent_unit_txdetectrxpowerdn[1]),
.dftout(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_pmadprioin_wire[599:300]),
.dprioout(wire_transmit_pma1_dprioout),
.fastrefclk0in({2{1'b0}}),
.fastrefclk1in(cmu_analogfastrefclkout[1:0]),
.fastrefclk2in({2{1'b0}}),
.fastrefclk3in({2{1'b0}}),
.fastrefclk4in(1'b0),
.forceelecidle(tx_forceelecidle[1]),
.powerdn(cent_unit_txobpowerdn[1]),
.refclk0in({2{1'b0}}),
.refclk0inpulse(1'b0),
.refclk1in(cmu_analogrefclkout[1:0]),
.refclk1inpulse(cmu_analogrefclkpulse[0]),
.refclk2in({2{1'b0}}),
.refclk2inpulse(1'b0),
.refclk3in({2{1'b0}}),
.refclk3inpulse(1'b0),
.refclk4in(1'b0),
.refclk4inpulse(1'b0),
.revserialfdbk(1'b0),
.rxdetecten(txdetectrxout[1]),
.rxdetectvalidout(wire_transmit_pma1_rxdetectvalidout),
.rxfoundout(wire_transmit_pma1_rxfoundout),
.seriallpbkout(),
.txpmareset(tx_analogreset_out[1])
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.pclk(1'b0),
.rxdetectclk(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
transmit_pma1.analog_power = "1.4V",
transmit_pma1.channel_number = ((starting_channel_number + 1) % 4),
transmit_pma1.channel_type = "auto",
transmit_pma1.clkin_select = 1,
transmit_pma1.clkmux_delay = "false",
transmit_pma1.common_mode = "0.65V",
transmit_pma1.dprio_config_mode = 6'h01,
transmit_pma1.enable_reverse_serial_loopback = "false",
transmit_pma1.logical_channel_address = (starting_channel_number + 1),
transmit_pma1.low_speed_test_select = 0,
transmit_pma1.preemp_pretap = 0,
transmit_pma1.preemp_pretap_inv = "false",
transmit_pma1.preemp_tap_1 = 3,
transmit_pma1.preemp_tap_2 = 0,
transmit_pma1.preemp_tap_2_inv = "false",
transmit_pma1.protocol_hint = "pcie",
transmit_pma1.rx_detect = 0,
transmit_pma1.serialization_factor = 10,
transmit_pma1.slew_rate = "off",
transmit_pma1.termination = "OCT 100 Ohms",
transmit_pma1.use_pma_direct = "false",
transmit_pma1.use_ser_double_data_mode = "false",
transmit_pma1.vod_selection = 4,
transmit_pma1.lpm_type = "stratixiv_hssi_tx_pma";
stratixiv_hssi_tx_pma transmit_pma2
(
.clockout(wire_transmit_pma2_clockout),
.datain({44'b00000000000000000000000000000000000000000000, tx_dataout_pcs_to_pma[59:40]}),
.dataout(wire_transmit_pma2_dataout),
.detectrxpowerdown(cent_unit_txdetectrxpowerdn[2]),
.dftout(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_pmadprioin_wire[899:600]),
.dprioout(wire_transmit_pma2_dprioout),
.fastrefclk0in({2{1'b0}}),
.fastrefclk1in(cmu_analogfastrefclkout[1:0]),
.fastrefclk2in({2{1'b0}}),
.fastrefclk3in({2{1'b0}}),
.fastrefclk4in(1'b0),
.forceelecidle(tx_forceelecidle[2]),
.powerdn(cent_unit_txobpowerdn[2]),
.refclk0in({2{1'b0}}),
.refclk0inpulse(1'b0),
.refclk1in(cmu_analogrefclkout[1:0]),
.refclk1inpulse(cmu_analogrefclkpulse[0]),
.refclk2in({2{1'b0}}),
.refclk2inpulse(1'b0),
.refclk3in({2{1'b0}}),
.refclk3inpulse(1'b0),
.refclk4in(1'b0),
.refclk4inpulse(1'b0),
.revserialfdbk(1'b0),
.rxdetecten(txdetectrxout[2]),
.rxdetectvalidout(wire_transmit_pma2_rxdetectvalidout),
.rxfoundout(wire_transmit_pma2_rxfoundout),
.seriallpbkout(),
.txpmareset(tx_analogreset_out[2])
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.pclk(1'b0),
.rxdetectclk(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
transmit_pma2.analog_power = "1.4V",
transmit_pma2.channel_number = ((starting_channel_number + 2) % 4),
transmit_pma2.channel_type = "auto",
transmit_pma2.clkin_select = 1,
transmit_pma2.clkmux_delay = "false",
transmit_pma2.common_mode = "0.65V",
transmit_pma2.dprio_config_mode = 6'h01,
transmit_pma2.enable_reverse_serial_loopback = "false",
transmit_pma2.logical_channel_address = (starting_channel_number + 2),
transmit_pma2.low_speed_test_select = 0,
transmit_pma2.preemp_pretap = 0,
transmit_pma2.preemp_pretap_inv = "false",
transmit_pma2.preemp_tap_1 = 3,
transmit_pma2.preemp_tap_2 = 0,
transmit_pma2.preemp_tap_2_inv = "false",
transmit_pma2.protocol_hint = "pcie",
transmit_pma2.rx_detect = 0,
transmit_pma2.serialization_factor = 10,
transmit_pma2.slew_rate = "off",
transmit_pma2.termination = "OCT 100 Ohms",
transmit_pma2.use_pma_direct = "false",
transmit_pma2.use_ser_double_data_mode = "false",
transmit_pma2.vod_selection = 4,
transmit_pma2.lpm_type = "stratixiv_hssi_tx_pma";
stratixiv_hssi_tx_pma transmit_pma3
(
.clockout(wire_transmit_pma3_clockout),
.datain({44'b00000000000000000000000000000000000000000000, tx_dataout_pcs_to_pma[79:60]}),
.dataout(wire_transmit_pma3_dataout),
.detectrxpowerdown(cent_unit_txdetectrxpowerdn[3]),
.dftout(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_pmadprioin_wire[1199:900]),
.dprioout(wire_transmit_pma3_dprioout),
.fastrefclk0in({2{1'b0}}),
.fastrefclk1in(cmu_analogfastrefclkout[1:0]),
.fastrefclk2in({2{1'b0}}),
.fastrefclk3in({2{1'b0}}),
.fastrefclk4in(1'b0),
.forceelecidle(tx_forceelecidle[3]),
.powerdn(cent_unit_txobpowerdn[3]),
.refclk0in({2{1'b0}}),
.refclk0inpulse(1'b0),
.refclk1in(cmu_analogrefclkout[1:0]),
.refclk1inpulse(cmu_analogrefclkpulse[0]),
.refclk2in({2{1'b0}}),
.refclk2inpulse(1'b0),
.refclk3in({2{1'b0}}),
.refclk3inpulse(1'b0),
.refclk4in(1'b0),
.refclk4inpulse(1'b0),
.revserialfdbk(1'b0),
.rxdetecten(txdetectrxout[3]),
.rxdetectvalidout(wire_transmit_pma3_rxdetectvalidout),
.rxfoundout(wire_transmit_pma3_rxfoundout),
.seriallpbkout(),
.txpmareset(tx_analogreset_out[3])
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.pclk(1'b0),
.rxdetectclk(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
transmit_pma3.analog_power = "1.4V",
transmit_pma3.channel_number = ((starting_channel_number + 3) % 4),
transmit_pma3.channel_type = "auto",
transmit_pma3.clkin_select = 1,
transmit_pma3.clkmux_delay = "false",
transmit_pma3.common_mode = "0.65V",
transmit_pma3.dprio_config_mode = 6'h01,
transmit_pma3.enable_reverse_serial_loopback = "false",
transmit_pma3.logical_channel_address = (starting_channel_number + 3),
transmit_pma3.low_speed_test_select = 0,
transmit_pma3.preemp_pretap = 0,
transmit_pma3.preemp_pretap_inv = "false",
transmit_pma3.preemp_tap_1 = 3,
transmit_pma3.preemp_tap_2 = 0,
transmit_pma3.preemp_tap_2_inv = "false",
transmit_pma3.protocol_hint = "pcie",
transmit_pma3.rx_detect = 0,
transmit_pma3.serialization_factor = 10,
transmit_pma3.slew_rate = "off",
transmit_pma3.termination = "OCT 100 Ohms",
transmit_pma3.use_pma_direct = "false",
transmit_pma3.use_ser_double_data_mode = "false",
transmit_pma3.vod_selection = 4,
transmit_pma3.lpm_type = "stratixiv_hssi_tx_pma";
assign
cal_blk_powerdown = 1'b1,
cent_unit_clkdivpowerdn = {wire_cent_unit0_clkdivpowerdn[0]},
cent_unit_cmudividerdprioout = {wire_cent_unit0_cmudividerdprioout},
cent_unit_cmuplldprioout = {wire_cent_unit0_cmuplldprioout},
cent_unit_pllpowerdn = {wire_cent_unit0_pllpowerdn[1:0]},
cent_unit_pllresetout = {wire_cent_unit0_pllresetout[1:0]},
cent_unit_quadresetout = {wire_cent_unit0_quadresetout},
cent_unit_rxadcepowerdn = {wire_cent_unit0_rxadcepowerdown},
cent_unit_rxcrupowerdn = {wire_cent_unit0_rxcrupowerdown[5:0]},
cent_unit_rxibpowerdn = {wire_cent_unit0_rxibpowerdown[5:0]},
cent_unit_rxpcsdprioin = {rx_pcsdprioout[1599:0]},
cent_unit_rxpcsdprioout = {wire_cent_unit0_rxpcsdprioout},
cent_unit_rxpmadprioin = {{2{300'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000}}, rx_pmadprioout[1199:0]},
cent_unit_rxpmadprioout = {wire_cent_unit0_rxpmadprioout},
cent_unit_tx_dprioin = {600'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, tx_txdprioout[599:0]},
cent_unit_tx_xgmdataout = {wire_cent_unit0_txdataout},
cent_unit_txctrlout = {wire_cent_unit0_txctrlout},
cent_unit_txdetectrxpowerdn = {wire_cent_unit0_txdetectrxpowerdown[3:0]},
cent_unit_txdprioout = {wire_cent_unit0_txpcsdprioout},
cent_unit_txobpowerdn = {wire_cent_unit0_txobpowerdown[5:0]},
cent_unit_txpmadprioin = {{2{300'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000}}, tx_pmadprioout[1199:0]},
cent_unit_txpmadprioout = {wire_cent_unit0_txpmadprioout},
clk_div_clk0in = {pll0_out[3:0]},
clk_div_cmudividerdprioin = {100'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, wire_central_clk_div0_dprioout, 400'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000},
clk_div_pclkin = {1'b0},
cmu_analogfastrefclkout = {wire_central_clk_div0_analogfastrefclkout},
cmu_analogrefclkout = {wire_central_clk_div0_analogrefclkout},
cmu_analogrefclkpulse = {wire_central_clk_div0_analogrefclkpulse},
coreclkout = {coreclkout_wire[0]},
coreclkout_wire = {wire_central_clk_div0_coreclkout},
fixedclk = 1'b0,
fixedclk_in = {{2{1'b0}}, {4{fixedclk}}},
int_hiprateswtichdone = {wire_central_clk_div0_rateswitchdone},
int_rx_coreclkout = {wire_receive_pcs3_coreclkout, wire_receive_pcs2_coreclkout, wire_receive_pcs1_coreclkout, wire_receive_pcs0_coreclkout},
int_rx_phfifobyteserdisable = {wire_receive_pcs3_phfifobyteserdisableout, wire_receive_pcs2_phfifobyteserdisableout, wire_receive_pcs1_phfifobyteserdisableout, wire_receive_pcs0_phfifobyteserdisableout},
int_rx_phfifoptrsresetout = {wire_receive_pcs3_phfifoptrsresetout, wire_receive_pcs2_phfifoptrsresetout, wire_receive_pcs1_phfifoptrsresetout, wire_receive_pcs0_phfifoptrsresetout},
int_rx_phfifordenableout = {wire_receive_pcs3_phfifordenableout, wire_receive_pcs2_phfifordenableout, wire_receive_pcs1_phfifordenableout, wire_receive_pcs0_phfifordenableout},
int_rx_phfiforesetout = {wire_receive_pcs3_phfiforesetout, wire_receive_pcs2_phfiforesetout, wire_receive_pcs1_phfiforesetout, wire_receive_pcs0_phfiforesetout},
int_rx_phfifowrdisableout = {wire_receive_pcs3_phfifowrdisableout, wire_receive_pcs2_phfifowrdisableout, wire_receive_pcs1_phfifowrdisableout, wire_receive_pcs0_phfifowrdisableout},
int_rx_phfifoxnbytesel = {int_rxphfifox4byteselout[0], {2{1'b0}}, int_rxphfifox4byteselout[0], {2{1'b0}}, int_rxphfifox4byteselout[0], {2{1'b0}}, int_rxphfifox4byteselout[0], {2{1'b0}}},
int_rx_phfifoxnrdenable = {int_rxphfifox4rdenableout[0], {2{1'b0}}, int_rxphfifox4rdenableout[0], {2{1'b0}}, int_rxphfifox4rdenableout[0], {2{1'b0}}, int_rxphfifox4rdenableout[0], {2{1'b0}}},
int_rx_phfifoxnwrclk = {int_rxphfifox4wrclkout[0], {2{1'b0}}, int_rxphfifox4wrclkout[0], {2{1'b0}}, int_rxphfifox4wrclkout[0], {2{1'b0}}, int_rxphfifox4wrclkout[0], {2{1'b0}}},
int_rx_phfifoxnwrenable = {int_rxphfifox4wrenableout[0], {2{1'b0}}, int_rxphfifox4wrenableout[0], {2{1'b0}}, int_rxphfifox4wrenableout[0], {2{1'b0}}, int_rxphfifox4wrenableout[0], {2{1'b0}}},
int_rxcoreclk = {int_rx_coreclkout[0]},
int_rxphfifordenable = {int_rx_phfifordenableout[0]},
int_rxphfiforeset = {int_rx_phfiforesetout[0]},
int_rxphfifox4byteselout = {wire_cent_unit0_rxphfifox4byteselout},
int_rxphfifox4rdenableout = {wire_cent_unit0_rxphfifox4rdenableout},
int_rxphfifox4wrclkout = {wire_cent_unit0_rxphfifox4wrclkout},
int_rxphfifox4wrenableout = {wire_cent_unit0_rxphfifox4wrenableout},
int_tx_coreclkout = {wire_transmit_pcs3_coreclkout, wire_transmit_pcs2_coreclkout, wire_transmit_pcs1_coreclkout, wire_transmit_pcs0_coreclkout},
int_tx_phfiforddisableout = {wire_transmit_pcs3_phfiforddisableout, wire_transmit_pcs2_phfiforddisableout, wire_transmit_pcs1_phfiforddisableout, wire_transmit_pcs0_phfiforddisableout},
int_tx_phfiforesetout = {wire_transmit_pcs3_phfiforesetout, wire_transmit_pcs2_phfiforesetout, wire_transmit_pcs1_phfiforesetout, wire_transmit_pcs0_phfiforesetout},
int_tx_phfifowrenableout = {wire_transmit_pcs3_phfifowrenableout, wire_transmit_pcs2_phfifowrenableout, wire_transmit_pcs1_phfifowrenableout, wire_transmit_pcs0_phfifowrenableout},
int_tx_phfifoxnbytesel = {int_txphfifox4byteselout[0], {2{1'b0}}, int_txphfifox4byteselout[0], {2{1'b0}}, int_txphfifox4byteselout[0], {2{1'b0}}, int_txphfifox4byteselout[0], {2{1'b0}}},
int_tx_phfifoxnrdclk = {int_txphfifox4rdclkout[0], {2{1'b0}}, int_txphfifox4rdclkout[0], {2{1'b0}}, int_txphfifox4rdclkout[0], {2{1'b0}}, int_txphfifox4rdclkout[0], {2{1'b0}}},
int_tx_phfifoxnrdenable = {int_txphfifox4rdenableout[0], {2{1'b0}}, int_txphfifox4rdenableout[0], {2{1'b0}}, int_txphfifox4rdenableout[0], {2{1'b0}}, int_txphfifox4rdenableout[0], {2{1'b0}}},
int_tx_phfifoxnwrenable = {int_txphfifox4wrenableout[0], {2{1'b0}}, int_txphfifox4wrenableout[0], {2{1'b0}}, int_txphfifox4wrenableout[0], {2{1'b0}}, int_txphfifox4wrenableout[0], {2{1'b0}}},
int_txcoreclk = {int_tx_coreclkout[0]},
int_txphfiforddisable = {int_tx_phfiforddisableout[0]},
int_txphfiforeset = {int_tx_phfiforesetout[0]},
int_txphfifowrenable = {int_tx_phfifowrenableout[0]},
int_txphfifox4byteselout = {wire_cent_unit0_txphfifox4byteselout},
int_txphfifox4rdclkout = {wire_cent_unit0_txphfifox4rdclkout},
int_txphfifox4rdenableout = {wire_cent_unit0_txphfifox4rdenableout},
int_txphfifox4wrenableout = {wire_cent_unit0_txphfifox4wrenableout},
nonusertocmu_out = {wire_cal_blk0_nonusertocmu},
pipedatavalid = {pipedatavalid_out[3:0]},
pipedatavalid_out = {wire_receive_pcs3_pipedatavalid, wire_receive_pcs2_pipedatavalid, wire_receive_pcs1_pipedatavalid, wire_receive_pcs0_pipedatavalid},
pipeelecidle = {pipeelecidle_out[3:0]},
pipeelecidle_out = {wire_receive_pcs3_pipeelecidle, wire_receive_pcs2_pipeelecidle, wire_receive_pcs1_pipeelecidle, wire_receive_pcs0_pipeelecidle},
pipephydonestatus = {wire_receive_pcs3_pipephydonestatus, wire_receive_pcs2_pipephydonestatus, wire_receive_pcs1_pipephydonestatus, wire_receive_pcs0_pipephydonestatus},
pipestatus = {wire_receive_pcs3_pipestatus, wire_receive_pcs2_pipestatus, wire_receive_pcs1_pipestatus, wire_receive_pcs0_pipestatus},
pll0_clkin = {9'b000000000, pll_inclk_wire[0]},
pll0_dprioin = {cent_unit_cmuplldprioout[1499:1200]},
pll0_dprioout = {wire_tx_pll0_dprioout},
pll0_out = {wire_tx_pll0_clk[3:0]},
pll_ch_dataout_wire = {wire_rx_cdr_pll3_dataout, wire_rx_cdr_pll2_dataout, wire_rx_cdr_pll1_dataout, wire_rx_cdr_pll0_dataout},
pll_ch_dprioout = {wire_rx_cdr_pll3_dprioout, wire_rx_cdr_pll2_dprioout, wire_rx_cdr_pll1_dprioout, wire_rx_cdr_pll0_dprioout},
pll_cmuplldprioout = {300'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, pll0_dprioout[299:0], 900'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, pll_ch_dprioout[299:0]},
pll_inclk_wire = {pll_inclk},
pll_locked = {pll_locked_out[0]},
pll_locked_out = {wire_tx_pll0_locked},
pll_powerdown = 1'b0,
pllpowerdn_in = {1'b0, cent_unit_pllpowerdn[0]},
pllreset_in = {1'b0, cent_unit_pllresetout[0]},
reconfig_fromgxb = {wire_cent_unit0_dprioout},
reconfig_togxb_disable = reconfig_togxb[1],
reconfig_togxb_in = reconfig_togxb[0],
reconfig_togxb_load = reconfig_togxb[2],
refclk_pma = {wire_central_clk_div0_refclkout},
rx_analogreset_in = {4{rx_analogreset[0]}},
rx_analogreset_out = {wire_cent_unit0_rxanalogresetout[5:0]},
rx_bitslip = {4{1'b0}},
rx_coreclk_in = {4{coreclkout_wire[0]}},
rx_cruclk_in = {8'b00000000, rx_pldcruclk_in[3], 8'b00000000, rx_pldcruclk_in[2], 8'b00000000, rx_pldcruclk_in[1], 8'b00000000, rx_pldcruclk_in[0]},
rx_ctrldetect = {wire_receive_pcs3_ctrldetect[1:0], wire_receive_pcs2_ctrldetect[1:0], wire_receive_pcs1_ctrldetect[1:0], wire_receive_pcs0_ctrldetect[1:0]},
rx_dataout = {rx_out_wire[63:0]},
rx_deserclock_in = {rx_pll_clkout[15:0]},
rx_digitalreset_in = {4{rx_digitalreset[0]}},
rx_digitalreset_out = {wire_cent_unit0_rxdigitalresetout},
rx_elecidleinfersel = {12{1'b0}},
rx_enapatternalign = {4{1'b0}},
rx_freqlocked = {rx_freqlocked_wire[3:0]},
rx_freqlocked_wire = {wire_rx_cdr_pll3_freqlocked, wire_rx_cdr_pll2_freqlocked, wire_rx_cdr_pll1_freqlocked, wire_rx_cdr_pll0_freqlocked},
rx_locktodata = {4{1'b0}},
rx_locktodata_wire = {rx_locktodata[3:0]},
rx_locktorefclk_wire = {wire_receive_pcs3_cdrctrllocktorefclkout, wire_receive_pcs2_cdrctrllocktorefclkout, wire_receive_pcs1_cdrctrllocktorefclkout, wire_receive_pcs0_cdrctrllocktorefclkout},
rx_out_wire = {wire_receive_pcs3_dataout[15:0], wire_receive_pcs2_dataout[15:0], wire_receive_pcs1_dataout[15:0], wire_receive_pcs0_dataout[15:0]},
rx_patterndetect = {wire_receive_pcs3_patterndetect[1:0], wire_receive_pcs2_patterndetect[1:0], wire_receive_pcs1_patterndetect[1:0], wire_receive_pcs0_patterndetect[1:0]},
rx_pcs_rxfound_wire = {txdetectrxout[3], tx_rxfoundout[3], txdetectrxout[2], tx_rxfoundout[2], txdetectrxout[1], tx_rxfoundout[1], txdetectrxout[0], tx_rxfoundout[0]},
rx_pcsdprioin_wire = {cent_unit_rxpcsdprioout[1599:0]},
rx_pcsdprioout = {wire_receive_pcs3_dprioout, wire_receive_pcs2_dprioout, wire_receive_pcs1_dprioout, wire_receive_pcs0_dprioout},
rx_phfifordenable = {4{1'b1}},
rx_phfiforeset = {4{1'b0}},
rx_phfifowrdisable = {4{1'b0}},
rx_pipestatetransdoneout = {wire_receive_pcs3_pipestatetransdoneout, wire_receive_pcs2_pipestatetransdoneout, wire_receive_pcs1_pipestatetransdoneout, wire_receive_pcs0_pipestatetransdoneout},
rx_pldcruclk_in = {rx_cruclk[3:0]},
rx_pll_clkout = {wire_rx_cdr_pll3_clk, wire_rx_cdr_pll2_clk, wire_rx_cdr_pll1_clk, wire_rx_cdr_pll0_clk},
rx_pll_locked = {rx_plllocked_wire[3:0]},
rx_pll_pfdrefclkout_wire = {wire_rx_cdr_pll3_pfdrefclkout, wire_rx_cdr_pll2_pfdrefclkout, wire_rx_cdr_pll1_pfdrefclkout, wire_rx_cdr_pll0_pfdrefclkout},
rx_plllocked_wire = {wire_rx_cdr_pll3_locked, wire_rx_cdr_pll2_locked, wire_rx_cdr_pll1_locked, wire_rx_cdr_pll0_locked},
rx_pma_clockout = {wire_receive_pma3_clockout, wire_receive_pma2_clockout, wire_receive_pma1_clockout, wire_receive_pma0_clockout},
rx_pma_dataout = {wire_receive_pma3_dataout, wire_receive_pma2_dataout, wire_receive_pma1_dataout, wire_receive_pma0_dataout},
rx_pma_locktorefout = {wire_receive_pma3_locktorefout, wire_receive_pma2_locktorefout, wire_receive_pma1_locktorefout, wire_receive_pma0_locktorefout},
rx_pma_recoverdataout_wire = {wire_receive_pma3_recoverdataout[19:0], wire_receive_pma2_recoverdataout[19:0], wire_receive_pma1_recoverdataout[19:0], wire_receive_pma0_recoverdataout[19:0]},
rx_pmadprioin_wire = {{2{300'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000}}, cent_unit_rxpmadprioout[1199:0]},
rx_pmadprioout = {{2{300'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000}}, wire_receive_pma3_dprioout, wire_receive_pma2_dprioout, wire_receive_pma1_dprioout, wire_receive_pma0_dprioout},
rx_powerdown = {4{1'b0}},
rx_powerdown_in = {rx_powerdown[3:0]},
rx_prbscidenable = {4{1'b0}},
rx_revparallelfdbkdata = {wire_receive_pcs3_revparallelfdbkdata, wire_receive_pcs2_revparallelfdbkdata, wire_receive_pcs1_revparallelfdbkdata, wire_receive_pcs0_revparallelfdbkdata},
rx_rmfiforeset = {4{1'b0}},
rx_rxadceresetout = {wire_cent_unit0_rxadceresetout},
rx_rxcruresetout = {wire_cent_unit0_rxcruresetout[5:0]},
rx_signaldetect_wire = {wire_receive_pma3_signaldetect, wire_receive_pma2_signaldetect, wire_receive_pma1_signaldetect, wire_receive_pma0_signaldetect},
rx_syncstatus = {wire_receive_pcs3_syncstatus[1:0], wire_receive_pcs2_syncstatus[1:0], wire_receive_pcs1_syncstatus[1:0], wire_receive_pcs0_syncstatus[1:0]},
rxphfifowrdisable = {int_rx_phfifowrdisableout[0]},
rxpll_dprioin = {cent_unit_cmuplldprioout[299:0]},
tx_analogreset_out = {wire_cent_unit0_txanalogresetout[5:0]},
tx_clkout_int_wire = {wire_transmit_pcs3_clkout, wire_transmit_pcs2_clkout, wire_transmit_pcs1_clkout, wire_transmit_pcs0_clkout},
tx_coreclk_in = {4{coreclkout_wire[0]}},
tx_datain_wire = {tx_datain[63:0]},
tx_datainfull = {352{1'b0}},
tx_dataout = {wire_transmit_pma3_dataout, wire_transmit_pma2_dataout, wire_transmit_pma1_dataout, wire_transmit_pma0_dataout},
tx_dataout_pcs_to_pma = {wire_transmit_pcs3_dataout, wire_transmit_pcs2_dataout, wire_transmit_pcs1_dataout, wire_transmit_pcs0_dataout},
tx_digitalreset_in = {4{tx_digitalreset[0]}},
tx_digitalreset_out = {wire_cent_unit0_txdigitalresetout},
tx_dprioin_wire = {600'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, cent_unit_txdprioout[599:0]},
tx_forcedisp_wire = {1'b0, tx_forcedispcompliance[3], 1'b0, tx_forcedispcompliance[2], 1'b0, tx_forcedispcompliance[1], 1'b0, tx_forcedispcompliance[0]},
tx_invpolarity = {4{1'b0}},
tx_localrefclk = {wire_transmit_pma3_clockout, wire_transmit_pma2_clockout, wire_transmit_pma1_clockout, wire_transmit_pma0_clockout},
tx_phfiforeset = {4{1'b0}},
tx_pipedeemph = {4{1'b0}},
tx_pipemargin = {12{1'b0}},
tx_pipepowerdownout = {wire_transmit_pcs3_pipepowerdownout, wire_transmit_pcs2_pipepowerdownout, wire_transmit_pcs1_pipepowerdownout, wire_transmit_pcs0_pipepowerdownout},
tx_pipepowerstateout = {wire_transmit_pcs3_pipepowerstateout, wire_transmit_pcs2_pipepowerstateout, wire_transmit_pcs1_pipepowerstateout, wire_transmit_pcs0_pipepowerstateout},
tx_pipeswing = {4{1'b0}},
tx_pmadprioin_wire = {{2{300'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000}}, cent_unit_txpmadprioout[1199:0]},
tx_pmadprioout = {{2{300'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000}}, wire_transmit_pma3_dprioout, wire_transmit_pma2_dprioout, wire_transmit_pma1_dprioout, wire_transmit_pma0_dprioout},
tx_revparallellpbken = {4{1'b0}},
tx_rxdetectvalidout = {wire_transmit_pma3_rxdetectvalidout, wire_transmit_pma2_rxdetectvalidout, wire_transmit_pma1_rxdetectvalidout, wire_transmit_pma0_rxdetectvalidout},
tx_rxfoundout = {wire_transmit_pma3_rxfoundout, wire_transmit_pma2_rxfoundout, wire_transmit_pma1_rxfoundout, wire_transmit_pma0_rxfoundout},
tx_txdprioout = {wire_transmit_pcs3_dprioout, wire_transmit_pcs2_dprioout, wire_transmit_pcs1_dprioout, wire_transmit_pcs0_dprioout},
txdetectrxout = {wire_transmit_pcs3_txdetectrx, wire_transmit_pcs2_txdetectrx, wire_transmit_pcs1_txdetectrx, wire_transmit_pcs0_txdetectrx},
w_cent_unit_dpriodisableout1w = {wire_cent_unit0_dpriodisableout};
endmodule //altpcie_serdes_4sgx_x4d_gen1_16p_alt4gxb_8vc9
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altpcie_serdes_4sgx_x4d_gen1_16p (
cal_blk_clk,
gxb_powerdown,
pipe8b10binvpolarity,
pll_inclk,
powerdn,
reconfig_clk,
reconfig_togxb,
rx_analogreset,
rx_cruclk,
rx_datain,
rx_digitalreset,
tx_ctrlenable,
tx_datain,
tx_detectrxloop,
tx_digitalreset,
tx_forcedispcompliance,
tx_forceelecidle,
coreclkout,
pipedatavalid,
pipeelecidle,
pipephydonestatus,
pipestatus,
pll_locked,
reconfig_fromgxb,
rx_ctrldetect,
rx_dataout,
rx_freqlocked,
rx_patterndetect,
rx_pll_locked,
rx_syncstatus,
tx_dataout)/* synthesis synthesis_clearbox = 1 */;
input cal_blk_clk;
input [0:0] gxb_powerdown;
input [3:0] pipe8b10binvpolarity;
input pll_inclk;
input [7:0] powerdn;
input reconfig_clk;
input [2:0] reconfig_togxb;
input [0:0] rx_analogreset;
input [3:0] rx_cruclk;
input [3:0] rx_datain;
input [0:0] rx_digitalreset;
input [7:0] tx_ctrlenable;
input [63:0] tx_datain;
input [3:0] tx_detectrxloop;
input [0:0] tx_digitalreset;
input [3:0] tx_forcedispcompliance;
input [3:0] tx_forceelecidle;
output [0:0] coreclkout;
output [3:0] pipedatavalid;
output [3:0] pipeelecidle;
output [3:0] pipephydonestatus;
output [11:0] pipestatus;
output [0:0] pll_locked;
output [0:0] reconfig_fromgxb;
output [7:0] rx_ctrldetect;
output [63:0] rx_dataout;
output [3:0] rx_freqlocked;
output [7:0] rx_patterndetect;
output [3:0] rx_pll_locked;
output [7:0] rx_syncstatus;
output [3:0] tx_dataout;
parameter starting_channel_number = 0;
wire [7:0] sub_wire0;
wire [0:0] sub_wire1;
wire [7:0] sub_wire2;
wire [3:0] sub_wire3;
wire [3:0] sub_wire4;
wire [3:0] sub_wire5;
wire [3:0] sub_wire6;
wire [3:0] sub_wire7;
wire [3:0] sub_wire8;
wire [11:0] sub_wire9;
wire [7:0] sub_wire10;
wire [0:0] sub_wire11;
wire [0:0] sub_wire12;
wire [63:0] sub_wire13;
wire [7:0] rx_patterndetect = sub_wire0[7:0];
wire [0:0] coreclkout = sub_wire1[0:0];
wire [7:0] rx_ctrldetect = sub_wire2[7:0];
wire [3:0] pipedatavalid = sub_wire3[3:0];
wire [3:0] pipephydonestatus = sub_wire4[3:0];
wire [3:0] rx_pll_locked = sub_wire5[3:0];
wire [3:0] rx_freqlocked = sub_wire6[3:0];
wire [3:0] tx_dataout = sub_wire7[3:0];
wire [3:0] pipeelecidle = sub_wire8[3:0];
wire [11:0] pipestatus = sub_wire9[11:0];
wire [7:0] rx_syncstatus = sub_wire10[7:0];
wire [0:0] reconfig_fromgxb = sub_wire11[0:0];
wire [0:0] pll_locked = sub_wire12[0:0];
wire [63:0] rx_dataout = sub_wire13[63:0];
altpcie_serdes_4sgx_x4d_gen1_16p_alt4gxb_8vc9 altpcie_serdes_4sgx_x4d_gen1_16p_alt4gxb_8vc9_component (
.tx_forceelecidle (tx_forceelecidle),
.pll_inclk (pll_inclk),
.gxb_powerdown (gxb_powerdown),
.tx_datain (tx_datain),
.rx_cruclk (rx_cruclk),
.cal_blk_clk (cal_blk_clk),
.powerdn (powerdn),
.reconfig_clk (reconfig_clk),
.rx_datain (rx_datain),
.reconfig_togxb (reconfig_togxb),
.tx_ctrlenable (tx_ctrlenable),
.rx_analogreset (rx_analogreset),
.pipe8b10binvpolarity (pipe8b10binvpolarity),
.rx_digitalreset (rx_digitalreset),
.tx_digitalreset (tx_digitalreset),
.tx_forcedispcompliance (tx_forcedispcompliance),
.tx_detectrxloop (tx_detectrxloop),
.rx_patterndetect (sub_wire0),
.coreclkout (sub_wire1),
.rx_ctrldetect (sub_wire2),
.pipedatavalid (sub_wire3),
.pipephydonestatus (sub_wire4),
.rx_pll_locked (sub_wire5),
.rx_freqlocked (sub_wire6),
.tx_dataout (sub_wire7),
.pipeelecidle (sub_wire8),
.pipestatus (sub_wire9),
.rx_syncstatus (sub_wire10),
.reconfig_fromgxb (sub_wire11),
.pll_locked (sub_wire12),
.rx_dataout (sub_wire13));
defparam
altpcie_serdes_4sgx_x4d_gen1_16p_alt4gxb_8vc9_component.starting_channel_number = starting_channel_number;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: NUM_KEYS NUMERIC "0"
// Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
// Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
// Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE STRING "2500.00"
// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE_ENABLE STRING "0"
// Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "2500"
// Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2000"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "100"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "100"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "PCI Express (PIPE)"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "100"
// Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "100"
// Retrieval info: PRIVATE: WIZ_INPUT_A STRING "2500"
// Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
// Retrieval info: PRIVATE: WIZ_INPUT_B STRING "100"
// Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
// Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "PCI Express (PIPE)"
// Retrieval info: PRIVATE: WIZ_RX_VCM STRING "0.82"
// Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "Gen 1-x4"
// Retrieval info: PRIVATE: WIZ_TX_VCM STRING "0.65"
// Retrieval info: PRIVATE: WIZ_VCCHTX STRING "1.4"
// Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
// Retrieval info: PARAMETER: STARTING_CHANNEL_NUMBER NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_A_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_B_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_C_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_D_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_V_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: INTENDED_DEVICE_SPEED_GRADE NUMERIC "2"
// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "none"
// Retrieval info: CONSTANT: LPM_TYPE STRING "alt4gxb"
// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "4"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "3"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_INV_SETTING STRING "false"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_INV_SETTING STRING "false"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: PROTOCOL STRING "pcie"
// Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "1"
// Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal"
// Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100"
// Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10"
// Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
// Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "true"
// Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
// Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "NONE"
// Retrieval info: CONSTANT: RX_CHANNEL_BONDING STRING "x4"
// Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.82v"
// Retrieval info: CONSTANT: RX_CRU_BANDWIDTH_TYPE STRING "Medium"
// Retrieval info: CONSTANT: RX_CRU_INCLOCK0_PERIOD NUMERIC "10000"
// Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "pipe"
// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "2500"
// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
// Retrieval info: CONSTANT: RX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false"
// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "true"
// Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "32"
// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "11010000111010000011"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "00101111000101111100"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "20"
// Retrieval info: CONSTANT: RX_RUN_LENGTH NUMERIC "40"
// Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "true"
// Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true"
// Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "false"
// Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false"
// Retrieval info: CONSTANT: RX_USE_CRUCLK STRING "true"
// Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false"
// Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "true"
// Retrieval info: CONSTANT: RX_USE_PIPE8B10BINVPOLARITY STRING "true"
// Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false"
// Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
// Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal"
// Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false"
// Retrieval info: CONSTANT: TX_ANALOG_POWER STRING "1.4v"
// Retrieval info: CONSTANT: TX_CHANNEL_BONDING STRING "x4"
// Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.65v"
// Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "2500"
// Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
// Retrieval info: CONSTANT: TX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
// Retrieval info: CONSTANT: TX_PLL_BANDWIDTH_TYPE STRING "High"
// Retrieval info: CONSTANT: TX_PLL_INCLK0_PERIOD NUMERIC "10000"
// Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "pipe"
// Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false"
// Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "true"
// Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "4"
// Retrieval info: CONSTANT: elec_idle_infer_enable STRING "false"
// Retrieval info: CONSTANT: enable_0ppm STRING "false"
// Retrieval info: CONSTANT: gxb_analog_power STRING "3.0v"
// Retrieval info: CONSTANT: gxb_powerdown_width NUMERIC "1"
// Retrieval info: CONSTANT: number_of_quads NUMERIC "1"
// Retrieval info: CONSTANT: rx_cdrctrl_enable STRING "true"
// Retrieval info: CONSTANT: rx_cru_data_rate NUMERIC "800"
// Retrieval info: CONSTANT: rx_cru_divide_by NUMERIC "2"
// Retrieval info: CONSTANT: rx_cru_m_divider NUMERIC "25"
// Retrieval info: CONSTANT: rx_cru_multiply_by NUMERIC "25"
// Retrieval info: CONSTANT: rx_cru_n_divider NUMERIC "2"
// Retrieval info: CONSTANT: rx_cru_pfd_clk_select NUMERIC "0"
// Retrieval info: CONSTANT: rx_cru_vco_post_scale_divider NUMERIC "2"
// Retrieval info: CONSTANT: rx_dwidth_factor NUMERIC "2"
// Retrieval info: CONSTANT: rx_word_aligner_num_byte NUMERIC "1"
// Retrieval info: CONSTANT: tx_dwidth_factor NUMERIC "2"
// Retrieval info: CONSTANT: tx_pll_clock_post_divider NUMERIC "1"
// Retrieval info: CONSTANT: tx_pll_data_rate NUMERIC "800"
// Retrieval info: CONSTANT: tx_pll_divide_by NUMERIC "2"
// Retrieval info: CONSTANT: tx_pll_m_divider NUMERIC "25"
// Retrieval info: CONSTANT: tx_pll_multiply_by NUMERIC "25"
// Retrieval info: CONSTANT: tx_pll_n_divider NUMERIC "2"
// Retrieval info: CONSTANT: tx_pll_pfd_clk_select NUMERIC "0"
// Retrieval info: CONSTANT: tx_pll_vco_post_scale_divider NUMERIC "2"
// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
// Retrieval info: USED_PORT: coreclkout 0 0 1 0 OUTPUT NODEFVAL "coreclkout[0..0]"
// Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
// Retrieval info: USED_PORT: pipe8b10binvpolarity 0 0 4 0 INPUT NODEFVAL "pipe8b10binvpolarity[3..0]"
// Retrieval info: USED_PORT: pipedatavalid 0 0 4 0 OUTPUT NODEFVAL "pipedatavalid[3..0]"
// Retrieval info: USED_PORT: pipeelecidle 0 0 4 0 OUTPUT NODEFVAL "pipeelecidle[3..0]"
// Retrieval info: USED_PORT: pipephydonestatus 0 0 4 0 OUTPUT NODEFVAL "pipephydonestatus[3..0]"
// Retrieval info: USED_PORT: pipestatus 0 0 12 0 OUTPUT NODEFVAL "pipestatus[11..0]"
// Retrieval info: USED_PORT: pll_inclk 0 0 0 0 INPUT NODEFVAL "pll_inclk"
// Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
// Retrieval info: USED_PORT: powerdn 0 0 8 0 INPUT NODEFVAL "powerdn[7..0]"
// Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
// Retrieval info: USED_PORT: reconfig_fromgxb 0 0 1 0 OUTPUT NODEFVAL "reconfig_fromgxb[0..0]"
// Retrieval info: USED_PORT: reconfig_togxb 0 0 3 0 INPUT NODEFVAL "reconfig_togxb[2..0]"
// Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
// Retrieval info: USED_PORT: rx_cruclk 0 0 4 0 INPUT GND "rx_cruclk[3..0]"
// Retrieval info: USED_PORT: rx_ctrldetect 0 0 8 0 OUTPUT NODEFVAL "rx_ctrldetect[7..0]"
// Retrieval info: USED_PORT: rx_datain 0 0 4 0 INPUT NODEFVAL "rx_datain[3..0]"
// Retrieval info: USED_PORT: rx_dataout 0 0 64 0 OUTPUT NODEFVAL "rx_dataout[63..0]"
// Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
// Retrieval info: USED_PORT: rx_freqlocked 0 0 4 0 OUTPUT NODEFVAL "rx_freqlocked[3..0]"
// Retrieval info: USED_PORT: rx_patterndetect 0 0 8 0 OUTPUT NODEFVAL "rx_patterndetect[7..0]"
// Retrieval info: USED_PORT: rx_pll_locked 0 0 4 0 OUTPUT NODEFVAL "rx_pll_locked[3..0]"
// Retrieval info: USED_PORT: rx_syncstatus 0 0 8 0 OUTPUT NODEFVAL "rx_syncstatus[7..0]"
// Retrieval info: USED_PORT: tx_ctrlenable 0 0 8 0 INPUT NODEFVAL "tx_ctrlenable[7..0]"
// Retrieval info: USED_PORT: tx_datain 0 0 64 0 INPUT NODEFVAL "tx_datain[63..0]"
// Retrieval info: USED_PORT: tx_dataout 0 0 4 0 OUTPUT NODEFVAL "tx_dataout[3..0]"
// Retrieval info: USED_PORT: tx_detectrxloop 0 0 4 0 INPUT NODEFVAL "tx_detectrxloop[3..0]"
// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
// Retrieval info: USED_PORT: tx_forcedispcompliance 0 0 4 0 INPUT NODEFVAL "tx_forcedispcompliance[3..0]"
// Retrieval info: USED_PORT: tx_forceelecidle 0 0 4 0 INPUT NODEFVAL "tx_forceelecidle[3..0]"
// Retrieval info: CONNECT: @tx_detectrxloop 0 0 4 0 tx_detectrxloop 0 0 4 0
// Retrieval info: CONNECT: @tx_forcedispcompliance 0 0 4 0 tx_forcedispcompliance 0 0 4 0
// Retrieval info: CONNECT: rx_patterndetect 0 0 8 0 @rx_patterndetect 0 0 8 0
// Retrieval info: CONNECT: pipedatavalid 0 0 4 0 @pipedatavalid 0 0 4 0
// Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
// Retrieval info: CONNECT: @powerdn 0 0 8 0 powerdn 0 0 8 0
// Retrieval info: CONNECT: pipeelecidle 0 0 4 0 @pipeelecidle 0 0 4 0
// Retrieval info: CONNECT: rx_ctrldetect 0 0 8 0 @rx_ctrldetect 0 0 8 0
// Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
// Retrieval info: CONNECT: rx_dataout 0 0 64 0 @rx_dataout 0 0 64 0
// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
// Retrieval info: CONNECT: pipestatus 0 0 12 0 @pipestatus 0 0 12 0
// Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
// Retrieval info: CONNECT: rx_pll_locked 0 0 4 0 @rx_pll_locked 0 0 4 0
// Retrieval info: CONNECT: coreclkout 0 0 1 0 @coreclkout 0 0 1 0
// Retrieval info: CONNECT: rx_syncstatus 0 0 8 0 @rx_syncstatus 0 0 8 0
// Retrieval info: CONNECT: @pipe8b10binvpolarity 0 0 4 0 pipe8b10binvpolarity 0 0 4 0
// Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
// Retrieval info: CONNECT: @reconfig_togxb 0 0 3 0 reconfig_togxb 0 0 3 0
// Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
// Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
// Retrieval info: CONNECT: @rx_cruclk 0 0 4 0 rx_cruclk 0 0 4 0
// Retrieval info: CONNECT: @pll_inclk 0 0 0 0 pll_inclk 0 0 0 0
// Retrieval info: CONNECT: @tx_ctrlenable 0 0 8 0 tx_ctrlenable 0 0 8 0
// Retrieval info: CONNECT: tx_dataout 0 0 4 0 @tx_dataout 0 0 4 0
// Retrieval info: CONNECT: @tx_datain 0 0 64 0 tx_datain 0 0 64 0
// Retrieval info: CONNECT: reconfig_fromgxb 0 0 1 0 @reconfig_fromgxb 0 0 1 0
// Retrieval info: CONNECT: rx_freqlocked 0 0 4 0 @rx_freqlocked 0 0 4 0
// Retrieval info: CONNECT: @rx_datain 0 0 4 0 rx_datain 0 0 4 0
// Retrieval info: CONNECT: pipephydonestatus 0 0 4 0 @pipephydonestatus 0 0 4 0
// Retrieval info: CONNECT: @tx_forceelecidle 0 0 4 0 tx_forceelecidle 0 0 4 0
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x4d_gen1_16p.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x4d_gen1_16p.ppf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x4d_gen1_16p.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x4d_gen1_16p.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x4d_gen1_16p.bsf FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x4d_gen1_16p_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x4d_gen1_16p_bb.v TRUE FALSE
// Retrieval info: LIB_FILE: stratixiv_hssi
|
// Copyright 2020 The XLS Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// Writes "ABC" onto the terminal via UART.
`include "xls/uncore_rtl/ice40/uart_transmitter.v"
module top(
input wire clk,
output wire tx_out,
output wire led_left_out,
output wire led_center_out
);
parameter ClocksPerBaud = `DEFAULT_CLOCKS_PER_BAUD;
localparam
Start = 'd0,
TransmitByte0 = 'd1,
TransmitByte1 = 'd2,
Done = 'd3;
localparam StateBits = 2;
reg [StateBits-1:0] state = Start;
reg [7:0] tx_byte = 'hff;
reg tx_byte_valid = 0;
// No external reset pin on IceStick?
reg rst_n = 1;
reg [StateBits-1:0] state_next;
reg [7:0] tx_byte_next;
reg tx_byte_valid_next;
wire tx_byte_done;
assign {led_left_out, led_center_out} = state;
uart_transmitter #(
.ClocksPerBaud(ClocksPerBaud)
) transmitter(
.clk (clk),
.rst_n (rst_n),
.tx_byte (tx_byte),
.tx_byte_valid (tx_byte_valid),
.tx_byte_done_out(tx_byte_done),
.tx_out (tx_out)
);
// State manipulation.
always @(*) begin // verilog_lint: waive always-comb b/72410891
state_next = state;
case (state)
Start: begin
if (tx_byte_done == 0) begin
state_next = TransmitByte0;
end
end
TransmitByte0: begin
if (tx_byte_done && !tx_byte_valid) begin
state_next = TransmitByte1;
end
end
TransmitByte1: begin
if (tx_byte_done && !tx_byte_valid) begin
state_next = Done;
end
end
Done: begin
// Final state.
end
default: begin
state_next = 1'bX;
end
endcase
end
// Non-state updates.
always @(*) begin // verilog_lint: waive always-comb b/72410891
tx_byte_next = tx_byte;
tx_byte_valid_next = tx_byte_valid;
case (state)
Start: begin
tx_byte_next = 'h41; // 'A'
tx_byte_valid_next = 'b1;
end
TransmitByte0: begin
if (tx_byte_done && !tx_byte_valid) begin
tx_byte_next = 'h42; // 'B'
tx_byte_valid_next = 'b1;
end else begin
tx_byte_valid_next = 'b0;
end
end
TransmitByte1: begin
if (tx_byte_done && !tx_byte_valid) begin
tx_byte_next = 'h43; // 'C'
tx_byte_valid_next = 'b1;
end else begin
tx_byte_valid_next = 'b0;
end
end
Done: begin
tx_byte_valid_next = 'b0;
end
default: begin
tx_byte_next = 'hXX;
tx_byte_valid_next = 'bX;
end
endcase
end
always @ (posedge clk) begin
state <= state_next;
tx_byte <= tx_byte_next;
tx_byte_valid <= tx_byte_valid_next;
end
endmodule
|
/***************************************************************************************************
** fpga_nes/hw/src/ppu/ppu_ri.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* External register interface PPU sub-block.
***************************************************************************************************/
module ppu_ri
(
input wire clk_in, // 100MHz system clock signal
input wire rst_in, // reset signal
input wire [ 2:0] sel_in, // register interface reg select
input wire ncs_in, // register interface enable (active low)
input wire r_nw_in, // register interface read/write select
input wire [ 7:0] cpu_d_in, // register interface data in from cpu
input wire [13:0] vram_a_in, // current vram address
input wire [ 7:0] vram_d_in, // data in from vram
input wire [ 7:0] pram_d_in, // data in from palette ram
input wire vblank_in, // high during vertical blank
input wire [ 7:0] spr_ram_d_in, // sprite ram data (for 0x2004 reads)
input wire spr_overflow_in, // more than 8 sprites hit on a scanline during last frame
input wire spr_pri_col_in, // primary object collision in last frame
output wire [ 7:0] cpu_d_out, // register interface data out to cpu
output reg [ 7:0] vram_d_out, // data out to vram
output reg vram_wr_out, // rd/wr select for vram ops
output reg pram_wr_out, // rd/wr select for palette ram ops
output wire [ 2:0] fv_out, // fine vertical scroll register
output wire [ 4:0] vt_out, // vertical tile scroll register
output wire v_out, // vertical name table selection register
output wire [ 2:0] fh_out, // fine horizontal scroll register
output wire [ 4:0] ht_out, // horizontal tile scroll register
output wire h_out, // horizontal name table selection register
output wire s_out, // playfield pattern table selection register
output reg inc_addr_out, // increment vmem addr (due to ri mem access)
output wire inc_addr_amt_out, // amount to increment vmem addr by (0x2002.7)
output wire nvbl_en_out, // enable nmi on vertical blank
output wire vblank_out, // current 2002.7 value for nmi
output wire bg_en_out, // enable background rendering
output wire spr_en_out, // enable sprite rendering
output wire bg_ls_clip_out, // clip playfield from left screen column (8 pixels)
output wire spr_ls_clip_out, // clip sprites from left screen column (8 pixels)
output wire spr_h_out, // 8/16 scanline sprites
output wire spr_pt_sel_out, // pattern table select for sprites (0x2000.3)
output wire upd_cntrs_out, // copy PPU registers to PPU counters
output wire [ 7:0] spr_ram_a_out, // sprite ram address (for 0x2004 reads/writes)
output reg [ 7:0] spr_ram_d_out, // sprite ram data (for 0x2004 writes)
output reg spr_ram_wr_out // sprite ram write enable (for 0x2004 writes)
);
//
// Scroll Registers
//
reg [2:0] q_fv, d_fv; // fine vertical scroll latch
reg [4:0] q_vt, d_vt; // vertical tile index latch
reg q_v, d_v; // vertical name table selection latch
reg [2:0] q_fh, d_fh; // fine horizontal scroll latch
reg [4:0] q_ht, d_ht; // horizontal tile index latch
reg q_h, d_h; // horizontal name table selection latch
reg q_s, d_s; // playfield pattern table selection latch
//
// Output Latches
//
reg [7:0] q_cpu_d_out, d_cpu_d_out; // output data bus latch for 0x2007 reads
reg q_upd_cntrs_out, d_upd_cntrs_out; // output latch for upd_cntrs_out
//
// External State Registers
//
reg q_nvbl_en, d_nvbl_en; // 0x2000[7]: enables an NMI interrupt on vblank
reg q_spr_h, d_spr_h; // 0x2000[5]: select 8/16 scanline high sprites
reg q_spr_pt_sel, d_spr_pt_sel; // 0x2000[3]: sprite pattern table select
reg q_addr_incr, d_addr_incr; // 0x2000[2]: amount to increment addr on 0x2007 access.
// 0: 1 byte, 1: 32 bytes.
reg q_spr_en, d_spr_en; // 0x2001[4]: enables sprite rendering
reg q_bg_en, d_bg_en; // 0x2001[3]: enables background rendering
reg q_spr_ls_clip, d_spr_ls_clip; // 0x2001[2]: left side screen column (8 pixel) object clipping
reg q_bg_ls_clip, d_bg_ls_clip; // 0x2001[1]: left side screen column (8 pixel) bg clipping
reg q_vblank, d_vblank; // 0x2002[7]: indicates a vblank is occurring
//
// Internal State Registers
//
reg q_byte_sel, d_byte_sel; // tracks if next 0x2005/0x2006 write is high or low byte
reg [7:0] q_rd_buf, d_rd_buf; // internal latch for buffered 0x2007 reads
reg q_rd_rdy, d_rd_rdy; // controls q_rd_buf updates
reg [7:0] q_spr_ram_a, d_spr_ram_a; // sprite ram pointer (set on 0x2003 write)
reg q_ncs_in; // last ncs signal (to detect falling edges)
reg q_vblank_in; // last vblank_in signal (to detect falling edges)
always @(posedge clk_in)
begin
if (rst_in)
begin
q_fv <= 2'h0;
q_vt <= 5'h00;
q_v <= 1'h0;
q_fh <= 3'h0;
q_ht <= 5'h00;
q_h <= 1'h0;
q_s <= 1'h0;
q_cpu_d_out <= 8'h00;
q_upd_cntrs_out <= 1'h0;
q_nvbl_en <= 1'h0;
q_spr_h <= 1'h0;
q_spr_pt_sel <= 1'h0;
q_addr_incr <= 1'h0;
q_spr_en <= 1'h0;
q_bg_en <= 1'h0;
q_spr_ls_clip <= 1'h0;
q_bg_ls_clip <= 1'h0;
q_vblank <= 1'h0;
q_byte_sel <= 1'h0;
q_rd_buf <= 8'h00;
q_rd_rdy <= 1'h0;
q_spr_ram_a <= 8'h00;
q_ncs_in <= 1'h1;
q_vblank_in <= 1'h0;
end
else
begin
q_fv <= d_fv;
q_vt <= d_vt;
q_v <= d_v;
q_fh <= d_fh;
q_ht <= d_ht;
q_h <= d_h;
q_s <= d_s;
q_cpu_d_out <= d_cpu_d_out;
q_upd_cntrs_out <= d_upd_cntrs_out;
q_nvbl_en <= d_nvbl_en;
q_spr_h <= d_spr_h;
q_spr_pt_sel <= d_spr_pt_sel;
q_addr_incr <= d_addr_incr;
q_spr_en <= d_spr_en;
q_bg_en <= d_bg_en;
q_spr_ls_clip <= d_spr_ls_clip;
q_bg_ls_clip <= d_bg_ls_clip;
q_vblank <= d_vblank;
q_byte_sel <= d_byte_sel;
q_rd_buf <= d_rd_buf;
q_rd_rdy <= d_rd_rdy;
q_spr_ram_a <= d_spr_ram_a;
q_ncs_in <= ncs_in;
q_vblank_in <= vblank_in;
end
end
always @*
begin
// Default most state to its original value.
d_fv = q_fv;
d_vt = q_vt;
d_v = q_v;
d_fh = q_fh;
d_ht = q_ht;
d_h = q_h;
d_s = q_s;
d_cpu_d_out = q_cpu_d_out;
d_nvbl_en = q_nvbl_en;
d_spr_h = q_spr_h;
d_spr_pt_sel = q_spr_pt_sel;
d_addr_incr = q_addr_incr;
d_spr_en = q_spr_en;
d_bg_en = q_bg_en;
d_spr_ls_clip = q_spr_ls_clip;
d_bg_ls_clip = q_bg_ls_clip;
d_byte_sel = q_byte_sel;
d_spr_ram_a = q_spr_ram_a;
// Update the read buffer if a new read request is ready. This happens one cycle after a read
// of 0x2007.
d_rd_buf = (q_rd_rdy) ? vram_d_in : q_rd_buf;
d_rd_rdy = 1'b0;
// Request a PPU counter update only after second write to 0x2006.
d_upd_cntrs_out = 1'b0;
// Set the vblank status bit on a rising vblank edge. Clear it if vblank is false. Can also
// be cleared by reading 0x2002.
d_vblank = (~q_vblank_in & vblank_in) ? 1'b1 :
(~vblank_in) ? 1'b0 : q_vblank;
// Only request memory writes on write of 0x2007.
vram_wr_out = 1'b0;
vram_d_out = 8'h00;
pram_wr_out = 1'b0;
// Only request VRAM addr increment on access of 0x2007.
inc_addr_out = 1'b0;
spr_ram_d_out = 8'h00;
spr_ram_wr_out = 1'b0;
// Only evaluate RI reads/writes on /CS falling edges. This prevents executing the same
// command multiple times because the CPU runs at a slower clock rate than the PPU.
if (q_ncs_in & ~ncs_in)
begin
if (r_nw_in)
begin
// External register read.
case (sel_in)
3'h2: // 0x2002
begin
d_cpu_d_out = { q_vblank, spr_pri_col_in, spr_overflow_in, 5'b00000 };
d_byte_sel = 1'b0;
d_vblank = 1'b0;
end
3'h4: // 0x2004
begin
d_cpu_d_out = spr_ram_d_in;
end
3'h7: // 0x2007
begin
d_cpu_d_out = (vram_a_in[13:8] == 6'h3F) ? pram_d_in : q_rd_buf;
d_rd_rdy = 1'b1;
inc_addr_out = 1'b1;
end
endcase
end
else
begin
// External register write.
case (sel_in)
3'h0: // 0x2000
begin
d_nvbl_en = cpu_d_in[7];
d_spr_h = cpu_d_in[5];
d_s = cpu_d_in[4];
d_spr_pt_sel = cpu_d_in[3];
d_addr_incr = cpu_d_in[2];
d_v = cpu_d_in[1];
d_h = cpu_d_in[0];
end
3'h1: // 0x2001
begin
d_spr_en = cpu_d_in[4];
d_bg_en = cpu_d_in[3];
d_spr_ls_clip = ~cpu_d_in[2];
d_bg_ls_clip = ~cpu_d_in[1];
end
3'h3: // 0x2003
begin
d_spr_ram_a = cpu_d_in;
end
3'h4: // 0x2004
begin
spr_ram_d_out = cpu_d_in;
spr_ram_wr_out = 1'b1;
d_spr_ram_a = q_spr_ram_a + 8'h01;
end
3'h5: // 0x2005
begin
d_byte_sel = ~q_byte_sel;
if (~q_byte_sel)
begin
// First write.
d_fh = cpu_d_in[2:0];
d_ht = cpu_d_in[7:3];
end
else
begin
// Second write.
d_fv = cpu_d_in[2:0];
d_vt = cpu_d_in[7:3];
end
end
3'h6: // 0x2006
begin
d_byte_sel = ~q_byte_sel;
if (~q_byte_sel)
begin
// First write.
d_fv = { 1'b0, cpu_d_in[5:4] };
d_v = cpu_d_in[3];
d_h = cpu_d_in[2];
d_vt[4:3] = cpu_d_in[1:0];
end
else
begin
// Second write.
d_vt[2:0] = cpu_d_in[7:5];
d_ht = cpu_d_in[4:0];
d_upd_cntrs_out = 1'b1;
end
end
3'h7: // 0x2007
begin
if (vram_a_in[13:8] == 6'h3F)
pram_wr_out = 1'b1;
else
vram_wr_out = 1'b1;
vram_d_out = cpu_d_in;
inc_addr_out = 1'b1;
end
endcase
end
end
end
assign cpu_d_out = (~ncs_in & r_nw_in) ? q_cpu_d_out : 8'h00;
assign fv_out = q_fv;
assign vt_out = q_vt;
assign v_out = q_v;
assign fh_out = q_fh;
assign ht_out = q_ht;
assign h_out = q_h;
assign s_out = q_s;
assign inc_addr_amt_out = q_addr_incr;
assign nvbl_en_out = q_nvbl_en;
assign vblank_out = q_vblank;
assign bg_en_out = q_bg_en;
assign spr_en_out = q_spr_en;
assign bg_ls_clip_out = q_bg_ls_clip;
assign spr_ls_clip_out = q_spr_ls_clip;
assign spr_h_out = q_spr_h;
assign spr_pt_sel_out = q_spr_pt_sel;
assign upd_cntrs_out = q_upd_cntrs_out;
assign spr_ram_a_out = q_spr_ram_a;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_ifu_invctl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
///////////////////////////////////////////////////////////////////////
/*
// Module Name: sparc_ifu_invctl
// Description:
// Control logic for handling invalidations to the icache
//
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "iop.h"
`include "ifu.h"
module sparc_ifu_invctl(/*AUTOARG*/
// Outputs
so, inv_ifc_inv_pending, ifq_icv_wrindex_bf, ifq_icv_wren_bf,
ifq_ict_dec_wrway_bf, ifq_fcl_invreq_bf, ifq_erb_asiway_f,
// Inputs
rclk, se, si, const_cpuid, mbist_icache_write,
lsu_ifu_ld_icache_index, lsu_ifu_ld_pcxpkt_vld,
lsu_ifu_ld_pcxpkt_tid, ifc_inv_ifqadv_i2, ifc_inv_asireq_i2,
ifq_icd_index_bf, ifd_inv_ifqop_i2, ifd_inv_wrway_i2
);
input rclk,
se,
si;
input [2:0] const_cpuid;
input mbist_icache_write;
input [`IC_IDX_HI:5] lsu_ifu_ld_icache_index;
input lsu_ifu_ld_pcxpkt_vld;
input [1:0] lsu_ifu_ld_pcxpkt_tid;
input ifc_inv_ifqadv_i2;
input ifc_inv_asireq_i2;
input [`IC_IDX_HI:5] ifq_icd_index_bf;
input [`CPX_WIDTH-1:0] ifd_inv_ifqop_i2;
input [1:0] ifd_inv_wrway_i2;
output so;
output inv_ifc_inv_pending;
output [`IC_IDX_HI:5] ifq_icv_wrindex_bf;
output [15:0] ifq_icv_wren_bf;
output [3:0] ifq_ict_dec_wrway_bf;
output ifq_fcl_invreq_bf;
output [1:0] ifq_erb_asiway_f;
//----------------------------------------------------------------------
// Local Signals
//----------------------------------------------------------------------
wire [3:0] cpu_sel,
invcpu21_sel_i2;
wire invcpu0_sel_i2;
wire [1:0] inv_vec0,
inv_vec1;
wire [1:0] inv_way0_p1_i2,
inv_way0_p0_i2,
inv_way1_p1_i2,
inv_way1_p0_i2,
invwd0_way_i2,
invwd1_way_i2,
inv0_way_i2,
inv1_way_i2;
wire [1:0] asi_way_f;
wire word0_inv_i2,
word1_inv_i2;
wire ldinv_i2,
ldpkt_i2,
evpkt_i2,
stpkt_i2,
strmack_i2,
imissrtn_i2;
wire invreq_i2,
invalidate_i2,
invalidate_f;
wire invall_i2,
invpa5_i2;
wire [1:0] cpxthrid_i2;
wire [3:0] dcpxthr_i2;
wire [1:0] ldinv_way_i2;
wire [1:0] w0_way_i2,
w1_way_i2,
w0_way_f,
w1_way_f;
wire pick_wr;
wire icv_wrreq_i2;
wire [3:0] wrt_en_wd_i2,
wrt_en_wd_bf,
wrt_en_wd_f;
wire [3:0] w0_dec_way_i2,
w1_dec_way_i2;
wire [3:0] dec_wrway;
wire icvidx_sel_wr_i2,
icvidx_sel_ld_i2,
icvidx_sel_inv_i2;
wire [15:0] wren_i2;
wire [`IC_IDX_HI:6] inv_addr_i2;
wire [`IC_IDX_HI:5] icaddr_i2;
wire missaddr5_i2;
wire missaddr6_i2;
wire [3:0] ldthr,
ldidx_sel_new;
wire [`IC_IDX_HI:5] ldinv_addr_i2,
ldindex0,
ldindex1,
ldindex2,
ldindex3,
ldindex0_nxt,
ldindex1_nxt,
ldindex2_nxt,
ldindex3_nxt;
wire clk;
//
// Code Begins Here
//
assign clk = rclk;
//----------------------------------------------------------------------
// Extract Invalidate Packet For This Core
//----------------------------------------------------------------------
// mux the invalidate vector down to get this processors inv vector
// First ecode cpu id
assign cpu_sel[0] = ~const_cpuid[2] & ~const_cpuid[1];
assign cpu_sel[1] = ~const_cpuid[2] & const_cpuid[1];
assign cpu_sel[2] = const_cpuid[2] & ~const_cpuid[1];
assign cpu_sel[3] = const_cpuid[2] & const_cpuid[1];
// 4:1 follwed by 2:1 to get 8:1, to get invalidate way selects
assign invcpu21_sel_i2 = cpu_sel;
assign invcpu0_sel_i2 = const_cpuid[0];
// First do word 0 for even processors
mux4ds #(1) v0p0_mux(.dout (inv_vec0[0]),
.in0 (ifd_inv_ifqop_i2[1]),
.in1 (ifd_inv_ifqop_i2[9]),
.in2 (ifd_inv_ifqop_i2[17]),
.in3 (ifd_inv_ifqop_i2[25]),
.sel0 (invcpu21_sel_i2[0]),
.sel1 (invcpu21_sel_i2[1]),
.sel2 (invcpu21_sel_i2[2]),
.sel3 (invcpu21_sel_i2[3]));
mux4ds #(2) w0p0_mux(.dout (inv_way0_p0_i2[1:0]),
.in0 (ifd_inv_ifqop_i2[3:2]),
.in1 (ifd_inv_ifqop_i2[11:10]),
.in2 (ifd_inv_ifqop_i2[19:18]),
.in3 (ifd_inv_ifqop_i2[27:26]),
.sel0 (invcpu21_sel_i2[0]),
.sel1 (invcpu21_sel_i2[1]),
.sel2 (invcpu21_sel_i2[2]),
.sel3 (invcpu21_sel_i2[3]));
// word 0 for odd processors
mux4ds #(1) v0p1_mux(.dout (inv_vec0[1]),
.in0 (ifd_inv_ifqop_i2[5]),
.in1 (ifd_inv_ifqop_i2[13]),
.in2 (ifd_inv_ifqop_i2[21]),
.in3 (ifd_inv_ifqop_i2[29]),
.sel0 (invcpu21_sel_i2[0]),
.sel1 (invcpu21_sel_i2[1]),
.sel2 (invcpu21_sel_i2[2]),
.sel3 (invcpu21_sel_i2[3]));
mux4ds #(2) w0p1_mux(.dout (inv_way0_p1_i2[1:0]),
.in0 (ifd_inv_ifqop_i2[7:6]),
.in1 (ifd_inv_ifqop_i2[15:14]),
.in2 (ifd_inv_ifqop_i2[23:22]),
.in3 (ifd_inv_ifqop_i2[31:30]),
.sel0 (invcpu21_sel_i2[0]),
.sel1 (invcpu21_sel_i2[1]),
.sel2 (invcpu21_sel_i2[2]),
.sel3 (invcpu21_sel_i2[3]));
// Word 1
// word 1 for even processors
mux4ds #(1) v1p0_mux(.dout (inv_vec1[0]),
.in0 (ifd_inv_ifqop_i2[57]),
.in1 (ifd_inv_ifqop_i2[65]),
.in2 (ifd_inv_ifqop_i2[73]),
.in3 (ifd_inv_ifqop_i2[81]),
.sel0 (invcpu21_sel_i2[0]),
.sel1 (invcpu21_sel_i2[1]),
.sel2 (invcpu21_sel_i2[2]),
.sel3 (invcpu21_sel_i2[3]));
mux4ds #(2) w1p0_mux(.dout (inv_way1_p0_i2[1:0]),
.in0 (ifd_inv_ifqop_i2[59:58]),
.in1 (ifd_inv_ifqop_i2[67:66]),
.in2 (ifd_inv_ifqop_i2[75:74]),
.in3 (ifd_inv_ifqop_i2[83:82]),
.sel0 (invcpu21_sel_i2[0]),
.sel1 (invcpu21_sel_i2[1]),
.sel2 (invcpu21_sel_i2[2]),
.sel3 (invcpu21_sel_i2[3]));
// word 1 for odd processors
mux4ds #(1) inv_v1p1_mux(.dout (inv_vec1[1]),
.in0 (ifd_inv_ifqop_i2[61]),
.in1 (ifd_inv_ifqop_i2[69]),
.in2 (ifd_inv_ifqop_i2[77]),
.in3 (ifd_inv_ifqop_i2[85]),
.sel0 (invcpu21_sel_i2[0]),
.sel1 (invcpu21_sel_i2[1]),
.sel2 (invcpu21_sel_i2[2]),
.sel3 (invcpu21_sel_i2[3]));
mux4ds #(2) w1p1_mux(.dout (inv_way1_p1_i2[1:0]),
.in0 (ifd_inv_ifqop_i2[63:62]),
.in1 (ifd_inv_ifqop_i2[71:70]),
.in2 (ifd_inv_ifqop_i2[79:78]),
.in3 (ifd_inv_ifqop_i2[87:86]),
.sel0 (invcpu21_sel_i2[0]),
.sel1 (invcpu21_sel_i2[1]),
.sel2 (invcpu21_sel_i2[2]),
.sel3 (invcpu21_sel_i2[3]));
// Mux odd and even values down to a single value for word0 and word1
// dp_mux2es #(1) v0_mux (.dout (word0_inv_i2),
// .in0 (inv_vec0[0]),
// .in1 (inv_vec0[1]),
// .sel (invcpu0_sel_i2));
assign word0_inv_i2 = invcpu0_sel_i2 ? inv_vec0[1] : inv_vec0[0];
// dp_mux2es #(2) w0_mux (.dout (invwd0_way_i2[1:0]),
// .in0 (inv_way0_p0_i2[1:0]),
// .in1 (inv_way0_p1_i2[1:0]),
// .sel (invcpu0_sel_i2));
assign invwd0_way_i2 = invcpu0_sel_i2 ? inv_way0_p1_i2[1:0] :
inv_way0_p0_i2[1:0];
// word1
// dp_mux2es #(1) v1_mux (.dout (word1_inv_i2),
// .in0 (inv_vec1[0]),
// .in1 (inv_vec1[1]),
// .sel (invcpu0_sel_i2));
assign word1_inv_i2 = invcpu0_sel_i2 ? inv_vec1[1] : inv_vec1[0];
// dp_mux2es #(2) w1_mux (.dout (invwd1_way_i2[1:0]),
// .in0 (inv_way1_p0_i2[1:0]),
// .in1 (inv_way1_p1_i2[1:0]),
// .sel (invcpu0_sel_i2));
assign invwd1_way_i2 = invcpu0_sel_i2 ? inv_way1_p1_i2[1:0] :
inv_way1_p0_i2[1:0];
//-----------------------------
// Decode CPX Packet
//-----------------------------
// load
assign ldpkt_i2 = ({ifd_inv_ifqop_i2[`CPX_VLD],
ifd_inv_ifqop_i2[`CPX_REQFIELD]} == `CPX_LDPKT) ?
1'b1 : 1'b0;
assign ldinv_i2 = ldpkt_i2 & ifd_inv_ifqop_i2[`CPX_WYVLD];
assign ldinv_way_i2= ifd_inv_ifqop_i2[`CPX_WY_HI:`CPX_WY_LO];
// ifill
assign imissrtn_i2 = ({ifd_inv_ifqop_i2[`CPX_VLD],
ifd_inv_ifqop_i2[`CPX_REQFIELD]} == `CPX_IFILLPKT) ?
1'b1 : 1'b0;
// store ack
assign stpkt_i2 = ({ifd_inv_ifqop_i2[`CPX_VLD],
ifd_inv_ifqop_i2[`CPX_REQFIELD]} == `CPX_STRPKT) ?
1'b1 : 1'b0;
assign strmack_i2 = ({ifd_inv_ifqop_i2[`CPX_VLD],
ifd_inv_ifqop_i2[`CPX_REQFIELD]} == `CPX_STRMACK) ?
1'b1 : 1'b0;
assign invall_i2 = stpkt_i2 & ifd_inv_ifqop_i2[`CPX_IINV] &
ifc_inv_ifqadv_i2;
assign invpa5_i2 = ifd_inv_ifqop_i2[`CPX_INVPA5];
// evict
assign evpkt_i2 = ({ifd_inv_ifqop_i2[`CPX_VLD],
ifd_inv_ifqop_i2[`CPX_REQFIELD]} == `CPX_EVPKT) ?
1'b1 : 1'b0;
// get thread id and decode
assign cpxthrid_i2 = ifd_inv_ifqop_i2[`CPX_THRFIELD];
assign dcpxthr_i2[0] = ~cpxthrid_i2[1] & ~cpxthrid_i2[0];
assign dcpxthr_i2[1] = ~cpxthrid_i2[1] & cpxthrid_i2[0];
assign dcpxthr_i2[2] = cpxthrid_i2[1] & ~cpxthrid_i2[0];
assign dcpxthr_i2[3] = cpxthrid_i2[1] & cpxthrid_i2[0];
//-----------------------------------------------
// Generate Write Way and Write Enables
//-----------------------------------------------
// decode way for tags
assign dec_wrway[0] = ~ifd_inv_wrway_i2[1] & ~ifd_inv_wrway_i2[0];
assign dec_wrway[1] = ~ifd_inv_wrway_i2[1] & ifd_inv_wrway_i2[0];
assign dec_wrway[2] = ifd_inv_wrway_i2[1] & ~ifd_inv_wrway_i2[0];
assign dec_wrway[3] = ifd_inv_wrway_i2[1] & ifd_inv_wrway_i2[0];
assign ifq_ict_dec_wrway_bf = dec_wrway;
// way for asi
dff_s #(2) asiwayf_reg(.din (ifd_inv_wrway_i2),
.q (asi_way_f),
.clk (clk), .se(se), .si(), .so());
assign ifq_erb_asiway_f = asi_way_f;
// Select which index/way to invalidate
assign icv_wrreq_i2 = imissrtn_i2 | ifc_inv_asireq_i2 | mbist_icache_write;
assign inv0_way_i2 = ~ifc_inv_ifqadv_i2 ? w0_way_f :
ldinv_i2 ? ldinv_way_i2 :
invwd0_way_i2;
assign inv1_way_i2 = ~ifc_inv_ifqadv_i2 ? w1_way_f :
ldinv_i2 ? ldinv_way_i2 :
invwd1_way_i2;
assign pick_wr = (imissrtn_i2 | ifc_inv_asireq_i2) & ifc_inv_ifqadv_i2 |
mbist_icache_write;
assign w0_way_i2 = pick_wr ? ifd_inv_wrway_i2 :
inv0_way_i2;
assign w1_way_i2 = pick_wr ? ifd_inv_wrway_i2 :
inv1_way_i2;
dff_s #(4) wrway_reg(.din ({w0_way_i2, w1_way_i2}),
.q ({w0_way_f, w1_way_f}),
.clk (clk), .se(se), .si(), .so());
// determine the way in the ICV we are writing to
// mux3ds #(2) w0_waymux(.dout (w0_way_i2),
// .in0 (ifd_inv_wrway_i2[1:0]),
// .in1 (invwd0_way_i2[1:0]),
// .in2 (ldinv_way_i2[1:0]),
// .sel0 (icvidx_sel_wr_i2),
// .sel1 (icvidx_sel_inv_i2),
// .sel2 (icvidx_sel_ld_i2));
// mux3ds #(2) w1_waymux(.dout (w1_way_i2),
// .in0 (ifd_inv_wrway_i2[1:0]),
// .in1 (invwd1_way_i2[1:0]),
// .in2 (ldinv_way_i2[1:0]),
// .sel0 (icvidx_sel_wr_i2),
// .sel1 (icvidx_sel_inv_i2),
// .sel2 (icvidx_sel_ld_i2));
// decode write way
assign w0_dec_way_i2[0] = ~w0_way_i2[1] & ~w0_way_i2[0];
assign w0_dec_way_i2[1] = ~w0_way_i2[1] & w0_way_i2[0];
assign w0_dec_way_i2[2] = w0_way_i2[1] & ~w0_way_i2[0];
assign w0_dec_way_i2[3] = w0_way_i2[1] & w0_way_i2[0];
assign w1_dec_way_i2[0] = ~w1_way_i2[1] & ~w1_way_i2[0];
assign w1_dec_way_i2[1] = ~w1_way_i2[1] & w1_way_i2[0];
assign w1_dec_way_i2[2] = w1_way_i2[1] & ~w1_way_i2[0];
assign w1_dec_way_i2[3] = w1_way_i2[1] & w1_way_i2[0];
// determine if valid bit write to top 32B, bot 32B or both
assign wrt_en_wd_i2[0] = word0_inv_i2 & (stpkt_i2 | evpkt_i2 |strmack_i2) &
~inv_addr_i2[6] |
ldinv_i2 & ~ldinv_addr_i2[5] & ~ldinv_addr_i2[6] |
icv_wrreq_i2 & ~missaddr5_i2 & ~missaddr6_i2;
assign wrt_en_wd_i2[1] = word1_inv_i2 & (stpkt_i2 | evpkt_i2 |strmack_i2) &
~inv_addr_i2[6] |
ldinv_i2 & ldinv_addr_i2[5] & ~ldinv_addr_i2[6] |
icv_wrreq_i2 & missaddr5_i2 & ~missaddr6_i2;
assign wrt_en_wd_i2[2] = word0_inv_i2 & (stpkt_i2 | evpkt_i2 |strmack_i2) &
inv_addr_i2[6] |
ldinv_i2 & ~ldinv_addr_i2[5] & ldinv_addr_i2[6] |
icv_wrreq_i2 & ~missaddr5_i2 & missaddr6_i2;
assign wrt_en_wd_i2[3] = word1_inv_i2 & (stpkt_i2 | evpkt_i2 |strmack_i2) &
inv_addr_i2[6] |
ldinv_i2 & ldinv_addr_i2[5] & ldinv_addr_i2[6] |
icv_wrreq_i2 & missaddr5_i2 & missaddr6_i2;
assign wrt_en_wd_bf = ifc_inv_ifqadv_i2 ? wrt_en_wd_i2 :
wrt_en_wd_f;
dff_s #(4) wrten_reg(.din (wrt_en_wd_bf),
.q (wrt_en_wd_f),
.clk (clk), .se(se), .si(), .so());
// Final Write Enable to ICV
assign wren_i2[3:0] = (w0_dec_way_i2 & {4{wrt_en_wd_bf[0]}}) |
{4{invall_i2 & ~invpa5_i2 & ~inv_addr_i2[6]}};
assign wren_i2[7:4] = (w1_dec_way_i2 & {4{wrt_en_wd_bf[1]}}) |
{4{invall_i2 & invpa5_i2 & ~inv_addr_i2[6]}};
assign wren_i2[11:8] = (w0_dec_way_i2 & {4{wrt_en_wd_bf[2]}}) |
{4{invall_i2 & ~invpa5_i2 & inv_addr_i2[6]}};
assign wren_i2[15:12] = (w1_dec_way_i2 & {4{wrt_en_wd_bf[3]}}) |
{4{invall_i2 & invpa5_i2 & inv_addr_i2[6]}};
assign ifq_icv_wren_bf = wren_i2;
// advance the wr way for the ICV array
// mux2ds #(8) wren_mux(.dout (next_wren_i2),
// .in0 (wren_f),
// .in1 (wren_i2),
// .sel0 (~ifc_ifd_ifqadv_i2),
// .sel1 (ifc_ifd_ifqadv_i2));
// assign wren_bf = ifc_inv_ifqadv_i2 ? wren_i2 : wren_f;
// dff #(8) icv_weff(.din (wren_bf),
// .q (wren_f),
// .clk (clk),
// .se (se), .si(), .so());
// assign ifq_icv_wren_bf[7:0] = wren_bf[7:0] & {8{~icvaddr6_i2}};
// assign ifq_icv_wren_bf[15:8] = wren_bf[7:0] & {8{icvaddr6_i2}};
//--------------------------
// Invalidates
//--------------------------
assign invalidate_i2 = (stpkt_i2 | evpkt_i2 | strmack_i2) &
(word0_inv_i2 |
word1_inv_i2 |
ifd_inv_ifqop_i2[`CPX_IINV]) | // all ways
ldinv_i2;
mux2ds #(1) invf_mux(.dout (invreq_i2),
.in0 (invalidate_f),
.in1 (invalidate_i2),
.sel0 (~ifc_inv_ifqadv_i2),
.sel1 (ifc_inv_ifqadv_i2));
dff_s #(1) invf_ff(.din (invreq_i2),
.q (invalidate_f),
.clk (clk),
.se (se), .si(), .so());
// auto invalidate is done during bist
// no need to qualify bist_write with ifqadv_i2 since bist is done
// before anything else.
assign ifq_fcl_invreq_bf = invreq_i2 | mbist_icache_write;
// don't really need to OR with invalidate_f, since this will be
// gone in a cycle
// assign inv_ifc_inv_pending = invalidate_i2 | invalidate_f;
assign inv_ifc_inv_pending = invalidate_i2;
//---------------------------------
// Get the ifill/invalidation index
//---------------------------------
// ifill index
assign icaddr_i2[`IC_IDX_HI:5] = ifq_icd_index_bf[`IC_IDX_HI:5];
assign missaddr5_i2 = ifq_icd_index_bf[5];
assign missaddr6_i2 = ifq_icd_index_bf[6];
// evict invalidate index
// assign inv_addr_i2 = ifqop_i2[117:112];
assign inv_addr_i2 = ifd_inv_ifqop_i2[`CPX_INV_IDX_HI:`CPX_INV_IDX_LO];
// index for invalidates caused by a load
// store dcache index when a load req is made
assign ldthr[0] = ~lsu_ifu_ld_pcxpkt_tid[1] & ~lsu_ifu_ld_pcxpkt_tid[0];
assign ldthr[1] = ~lsu_ifu_ld_pcxpkt_tid[1] & lsu_ifu_ld_pcxpkt_tid[0];
assign ldthr[2] = lsu_ifu_ld_pcxpkt_tid[1] & ~lsu_ifu_ld_pcxpkt_tid[0];
assign ldthr[3] = lsu_ifu_ld_pcxpkt_tid[1] & lsu_ifu_ld_pcxpkt_tid[0];
assign ldidx_sel_new = ldthr & {4{lsu_ifu_ld_pcxpkt_vld}};
// dp_mux2es #(`IC_IDX_SZ) t0_ldidx_mux(.dout (ldindex0_nxt),
// .in0 (ldindex0),
// .in1 (lsu_ifu_ld_icache_index),
// .sel (ldidx_sel_new[0]));
assign ldindex0_nxt = ldidx_sel_new[0] ? lsu_ifu_ld_icache_index :
ldindex0;
// dp_mux2es #(`IC_IDX_SZ) t1_ldidx_mux(.dout (ldindex1_nxt),
// .in0 (ldindex1),
// .in1 (lsu_ifu_ld_icache_index),
// .sel (ldidx_sel_new[1]));
assign ldindex1_nxt = ldidx_sel_new[1] ? lsu_ifu_ld_icache_index :
ldindex1;
// dp_mux2es #(`IC_IDX_SZ) t2_ldidx_mux(.dout (ldindex2_nxt),
// .in0 (ldindex2),
// .in1 (lsu_ifu_ld_icache_index),
// .sel (ldidx_sel_new[2]));
assign ldindex2_nxt = ldidx_sel_new[2] ? lsu_ifu_ld_icache_index :
ldindex2;
// dp_mux2es #(`IC_IDX_SZ) t3_ldidx_mux(.dout (ldindex3_nxt),
// .in0 (ldindex3),
// .in1 (lsu_ifu_ld_icache_index),
// .sel (ldidx_sel_new[3]));
assign ldindex3_nxt = ldidx_sel_new[3] ? lsu_ifu_ld_icache_index :
ldindex3;
dff_s #(`IC_IDX_SZ) ldix0_reg(.din (ldindex0_nxt),
.q (ldindex0),
.clk (clk), .se(se), .si(), .so());
dff_s #(`IC_IDX_SZ) ldix1_reg(.din (ldindex1_nxt),
.q (ldindex1),
.clk (clk), .se(se), .si(), .so());
dff_s #(`IC_IDX_SZ) ldix2_reg(.din (ldindex2_nxt),
.q (ldindex2),
.clk (clk), .se(se), .si(), .so());
dff_s #(`IC_IDX_SZ) ldix3_reg(.din (ldindex3_nxt),
.q (ldindex3),
.clk (clk), .se(se), .si(), .so());
// Pick dcache index corresponding to current thread
mux4ds #(`IC_IDX_SZ) ldinv_mux(.dout (ldinv_addr_i2),
.in0 (ldindex0),
.in1 (ldindex1),
.in2 (ldindex2),
.in3 (ldindex3),
.sel0 (dcpxthr_i2[0]),
.sel1 (dcpxthr_i2[1]),
.sel2 (dcpxthr_i2[2]),
.sel3 (dcpxthr_i2[3]));
// Final Mux for Index
assign icvidx_sel_wr_i2 = imissrtn_i2 | ifc_inv_asireq_i2 |
mbist_icache_write | ~ifc_inv_ifqadv_i2;
assign icvidx_sel_ld_i2 = ldinv_i2 & ifc_inv_ifqadv_i2;
assign icvidx_sel_inv_i2 = ~imissrtn_i2 & ~ldinv_i2 &
~ifc_inv_asireq_i2 & ifc_inv_ifqadv_i2 &
~mbist_icache_write;
mux3ds #(`IC_IDX_SZ) icv_idx_mux(
.dout (ifq_icv_wrindex_bf[`IC_IDX_HI:5]),
.in0 (icaddr_i2[`IC_IDX_HI:5]),
.in1 ({inv_addr_i2[`IC_IDX_HI:6], 1'b0}),
.in2 (ldinv_addr_i2[`IC_IDX_HI:5]),
.sel0 (icvidx_sel_wr_i2),
.sel1 (icvidx_sel_inv_i2),
.sel2 (icvidx_sel_ld_i2));
sink #(`CPX_WIDTH) s0(.in (ifd_inv_ifqop_i2));
endmodule // sparc_ifu_invctl
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_atan(clock, resetn, enable, dataa, result);
input clock, resetn, enable;
input [31:0] dataa;
output [31:0] result;
fp_atan core(
.sysclk(clock),
.reset(~resetn),
.enable(enable),
.signin(dataa[31]),
.exponentin(dataa[30:23]),
.mantissain(dataa[22:0]),
.signout(result[31]),
.exponentout(result[30:23]),
.mantissaout(result[22:0])
);
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:27:15 11/09/2016
// Design Name: Sprite_Controller
// Module Name: C:/Users/yoe/Desktop/Experimento4/Monitor/testSprite.v
// Project Name: Monitor
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Sprite_Controller
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testSprite;
// Inputs
reg [9:0] iColumnCount;
reg [9:0] iRowCount;
reg imask;
reg iEnable;
reg [9:0] iPosX;
reg [9:0] iPosY;
reg [2:0] iColorSprite;
reg [2:0] iColorBack;
// Outputs
wire [2:0] oRGB;
// Instantiate the Unit Under Test (UUT)
Sprite_Controller spriteTest (
.iColumnCount(iColumnCount),
.iRowCount(iRowCount),
.imask(imask),
.iEnable(iEnable),
.iPosX(iPosX),
.iPosY(iPosY),
.iColorSprite(iColorSprite),
.iColorBack(iColorBack),
.oRGB(oRGB)
);
initial begin
// Initialize Inputs
iColumnCount = 0;
iRowCount = 0;
imask = 0;
iEnable = 0;
iPosX = 5;
iPosY = 5;
iColorSprite = 2;
iColorBack = 5;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
always
begin
#10
iColumnCount = iColumnCount + 1;
iRowCount = iRowCount + 1;
{iEnable,imask} = {iEnable,imask} +1;
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_port_32.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Receives data from the tx_engine and buffers the input
// for the RIFFA channel.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module tx_port_32 #(
parameter C_DATA_WIDTH = 9'd32,
parameter C_FIFO_DEPTH = 512,
// Local parameters
parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1)
)
(
input CLK,
input RST,
input [2:0] CONFIG_MAX_PAYLOAD_SIZE, // Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B
output TXN, // Write transaction notification
input TXN_ACK, // Write transaction acknowledged
output [31:0] TXN_LEN, // Write transaction length
output [31:0] TXN_OFF_LAST, // Write transaction offset/last
output [31:0] TXN_DONE_LEN, // Write transaction actual transfer length
output TXN_DONE, // Write transaction done
input TXN_DONE_ACK, // Write transaction actual transfer length read
input [C_DATA_WIDTH-1:0] SG_DATA, // Scatter gather data
input SG_DATA_EMPTY, // Scatter gather buffer empty
output SG_DATA_REN, // Scatter gather data read enable
output SG_RST, // Scatter gather reset
input SG_ERR, // Scatter gather read encountered an error
output TX_REQ, // Outgoing write request
input TX_REQ_ACK, // Outgoing write request acknowledged
output [63:0] TX_ADDR, // Outgoing write high address
output [9:0] TX_LEN, // Outgoing write length (in 32 bit words)
output [C_DATA_WIDTH-1:0] TX_DATA, // Outgoing write data
input TX_DATA_REN, // Outgoing write data read enable
input TX_SENT, // Outgoing write complete
input CHNL_CLK, // Channel write clock
input CHNL_TX, // Channel write receive signal
output CHNL_TX_ACK, // Channel write acknowledgement signal
input CHNL_TX_LAST, // Channel last write
input [31:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [30:0] CHNL_TX_OFF, // Channel write offset
input [C_DATA_WIDTH-1:0] CHNL_TX_DATA, // Channel write data
input CHNL_TX_DATA_VALID, // Channel write data valid
output CHNL_TX_DATA_REN // Channel write data has been recieved
);
`include "functions.vh"
wire wGateRen;
wire wGateEmpty;
wire [C_DATA_WIDTH:0] wGateData;
wire wBufWen;
wire [C_FIFO_DEPTH_WIDTH-1:0] wBufCount;
wire [C_DATA_WIDTH-1:0] wBufData;
wire wTxn;
wire wTxnAck;
wire wTxnLast;
wire [31:0] wTxnLen;
wire [30:0] wTxnOff;
wire [31:0] wTxnWordsRecvd;
wire wTxnDone;
wire wTxnErr;
wire wSgElemRen;
wire wSgElemRdy;
wire wSgElemEmpty;
wire [31:0] wSgElemLen;
wire [63:0] wSgElemAddr;
reg [4:0] rWideRst=0;
reg rRst=0;
// Generate a wide reset from the input reset.
always @ (posedge CLK) begin
rRst <= #1 rWideRst[4];
if (RST)
rWideRst <= #1 5'b11111;
else
rWideRst <= (rWideRst<<1);
end
// Capture channel transaction open/close events as well as channel data.
tx_port_channel_gate_32 #(.C_DATA_WIDTH(C_DATA_WIDTH)) gate (
.RST(rRst),
.RD_CLK(CLK),
.RD_DATA(wGateData),
.RD_EMPTY(wGateEmpty),
.RD_EN(wGateRen),
.CHNL_CLK(CHNL_CLK),
.CHNL_TX(CHNL_TX),
.CHNL_TX_ACK(CHNL_TX_ACK),
.CHNL_TX_LAST(CHNL_TX_LAST),
.CHNL_TX_LEN(CHNL_TX_LEN),
.CHNL_TX_OFF(CHNL_TX_OFF),
.CHNL_TX_DATA(CHNL_TX_DATA),
.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID),
.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN)
);
// Filter transaction events from channel data. Use the events to put only
// the requested amount of data into the port buffer.
tx_port_monitor_32 #(.C_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_FIFO_DEPTH)) monitor (
.RST(rRst),
.CLK(CLK),
.EVT_DATA(wGateData),
.EVT_DATA_EMPTY(wGateEmpty),
.EVT_DATA_RD_EN(wGateRen),
.WR_DATA(wBufData),
.WR_EN(wBufWen),
.WR_COUNT(wBufCount),
.TXN(wTxn),
.ACK(wTxnAck),
.LAST(wTxnLast),
.LEN(wTxnLen),
.OFF(wTxnOff),
.WORDS_RECVD(wTxnWordsRecvd),
.DONE(wTxnDone),
.TX_ERR(SG_ERR)
);
// Buffer the incoming channel data.
tx_port_buffer_32 #(.C_FIFO_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_FIFO_DEPTH)) buffer (
.CLK(CLK),
.RST(rRst | (TXN_DONE & wTxnErr)),
.RD_DATA(TX_DATA),
.RD_EN(TX_DATA_REN),
.WR_DATA(wBufData),
.WR_EN(wBufWen),
.WR_COUNT(wBufCount)
);
// Read the scatter gather buffer address and length, continuously so that
// we have it ready whenever the next buffer is needed.
sg_list_reader_32 #(.C_DATA_WIDTH(C_DATA_WIDTH)) sgListReader (
.CLK(CLK),
.RST(rRst | SG_RST),
.BUF_DATA(SG_DATA),
.BUF_DATA_EMPTY(SG_DATA_EMPTY),
.BUF_DATA_REN(SG_DATA_REN),
.VALID(wSgElemRdy),
.EMPTY(wSgElemEmpty),
.REN(wSgElemRen),
.ADDR(wSgElemAddr),
.LEN(wSgElemLen)
);
// Controls the flow of request to the tx engine for transfers in a transaction.
tx_port_writer writer (
.CLK(CLK),
.RST(rRst),
.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE),
.TXN(TXN),
.TXN_ACK(TXN_ACK),
.TXN_LEN(TXN_LEN),
.TXN_OFF_LAST(TXN_OFF_LAST),
.TXN_DONE_LEN(TXN_DONE_LEN),
.TXN_DONE(TXN_DONE),
.TXN_ERR(wTxnErr),
.TXN_DONE_ACK(TXN_DONE_ACK),
.NEW_TXN(wTxn),
.NEW_TXN_ACK(wTxnAck),
.NEW_TXN_LAST(wTxnLast),
.NEW_TXN_LEN(wTxnLen),
.NEW_TXN_OFF(wTxnOff),
.NEW_TXN_WORDS_RECVD(wTxnWordsRecvd),
.NEW_TXN_DONE(wTxnDone),
.SG_ELEM_ADDR(wSgElemAddr),
.SG_ELEM_LEN(wSgElemLen),
.SG_ELEM_RDY(wSgElemRdy),
.SG_ELEM_EMPTY(wSgElemEmpty),
.SG_ELEM_REN(wSgElemRen),
.SG_RST(SG_RST),
.SG_ERR(SG_ERR),
.TX_REQ(TX_REQ),
.TX_REQ_ACK(TX_REQ_ACK),
.TX_ADDR(TX_ADDR),
.TX_LEN(TX_LEN),
.TX_LAST(),
.TX_SENT(TX_SENT)
);
endmodule
|
/*
* Author : Tom Stanway-Mayers
* Description : Instruction Decoder Stage
* Version: :
* License : Apache License Version 2.0, January 2004
* License URL : http://www.apache.org/licenses/
*/
`include "riscv_defs.v"
module merlin_id_stage
(
// global
input wire clk_i,
input wire reset_i,
// pfu interface
input wire pfu_dav_i, // new fetch available
output wire pfu_ack_o, // ack this fetch
output reg [1:0] pfu_ack_size_o, // ack size
input wire [`RV_SOFID_RANGE] pfu_sofid_i, // first fetch since vectoring
input wire [31:0] pfu_ins_i, // instruction fetched
input wire pfu_ferr_i, // this instruction fetch resulted in error
input wire [`RV_XLEN-1:0] pfu_pc_i, // address of this instruction
// ex stage interface
output reg [`RV_XLEN-1:0] exs_ins_o,
output reg exs_valid_o,
input wire exs_stall_i,
output reg [`RV_SOFID_RANGE] exs_sofid_o,
output reg [1:0] exs_ins_size_o,
output reg exs_ins_uerr_o,
output reg exs_ins_ferr_o,
output reg exs_fencei_o,
output reg exs_wfi_o,
output reg exs_jump_o,
output reg exs_ecall_o,
output reg exs_trap_rtn_o,
output reg [1:0] exs_trap_rtn_mode_o,
output reg exs_cond_o,
output reg [`RV_ZONE_RANGE] exs_zone_o,
output reg exs_link_o,
output wire [`RV_XLEN-1:0] exs_pc_o,
output reg [`RV_ALUOP_RANGE] exs_alu_op_o,
output reg [`RV_XLEN-1:0] exs_operand_left_o,
output reg [`RV_XLEN-1:0] exs_operand_right_o,
output reg [`RV_XLEN-1:0] exs_cmp_right_o,
output wire [`RV_XLEN-1:0] exs_regs1_data_o,
output wire [`RV_XLEN-1:0] exs_regs2_data_o,
output reg [4:0] exs_regd_addr_o,
output reg [2:0] exs_funct3_o,
output reg exs_csr_rd_o,
output reg exs_csr_wr_o,
output reg [11:0] exs_csr_addr_o,
output reg [`RV_XLEN-1:0] exs_csr_wr_data_o,
// write-back interface
input wire exs_regd_cncl_load_i,
input wire exs_regd_wr_i,
input wire [4:0] exs_regd_addr_i,
input wire [`RV_XLEN-1:0] exs_regd_data_i,
// load/store queue interface
input wire lsq_reg_wr_i,
input wire [4:0] lsq_reg_addr_i,
input wire [`RV_XLEN-1:0] lsq_reg_data_i
);
//--------------------------------------------------------------
// interface assignments
// id stage qualifier logic
wire id_stage_en;
wire exs_stall;
// rv32ic instruction expander
wire ins_expanded_valid;
wire rv32ic_ins_uerr;
wire [31:0] ins_expanded;
// instruction mux
wire ins_uerr_d;
reg [31:0] rv32i_ins;
// instruction decoder
wire rv32i_ins_uerr;
wire fencei_d;
wire wfi_d;
wire jump_d;
wire ecall_d;
wire trap_rtn_d;
wire [1:0] trap_rtn_mode_d;
wire [`RV_ZONE_RANGE] zone_d;
wire regd_tgt;
wire [4:0] regd_addr_d;
wire regs1_rd_d;
wire [4:0] regs1_addr_d;
wire regs2_rd_d;
wire [4:0] regs2_addr_d;
wire [`RV_XLEN-1:0] imm_d;
wire link_d;
wire sels1_pc_d;
wire sel_csr_wr_data_imm_d;
wire sels2_imm_d;
wire selcmps2_imm_d;
wire [`RV_ALUOP_RANGE] alu_op_d;
wire [2:0] funct3_d;
wire csr_rd_d;
wire csr_wr_d;
wire [11:0] csr_addr_d;
wire conditional_d;
// id stage stall controller
wire s1_lq_fwd_available;
wire s2_lq_fwd_available;
reg ids_stall;
reg [31:1] reg_loading_vector_q;
// integer register file
wire [`RV_XLEN-1:0] regs1_dout;
wire [`RV_XLEN-1:0] regs2_dout;
// id register stage
reg [`RV_XLEN-1:0] pc_q;
reg [`RV_XLEN-1:0] imm_q;
reg sels1_pc_q;
reg sel_csr_wr_data_imm_q;
reg sels2_imm_q;
reg selcmps2_imm_q;
reg regs1_rd_q;
reg [4:0] regs1_addr_q;
reg regs2_rd_q;
reg [4:0] regs2_addr_q;
// operand forwarding mux
reg [`RV_XLEN-1:0] fwd_mux_regs1_data;
reg [`RV_XLEN-1:0] fwd_mux_regs2_data;
// left operand select mux
// right operand select mux
// right cmp select mux
// csr write data select mux
//--------------------------------------------------------------
//--------------------------------------------------------------
// interface assignments
//--------------------------------------------------------------
assign exs_pc_o = pc_q;
assign exs_regs1_data_o = fwd_mux_regs1_data;
assign exs_regs2_data_o = fwd_mux_regs2_data;
//--------------------------------------------------------------
// id stage qualifier logic
//--------------------------------------------------------------
assign pfu_ack_o = pfu_dav_i & ~ids_stall & ~exs_stall;
assign id_stage_en = pfu_ack_o;
assign exs_stall = exs_stall_i & exs_valid_o;
//--------------------------------------------------------------
// rv32ic instruction expander
//--------------------------------------------------------------
merlin_rv32ic_expander i_merlin_rv32ic_expander (
.ins_i (pfu_ins_i[15:0]),
.ins_rvc_o (ins_expanded_valid),
.ins_err_o (rv32ic_ins_uerr),
.ins_o (ins_expanded)
);
//--------------------------------------------------------------
// instruction mux
//--------------------------------------------------------------
assign ins_uerr_d = rv32i_ins_uerr | (ins_expanded_valid & rv32ic_ins_uerr);
//
always @ (*) begin
if (ins_expanded_valid) begin
pfu_ack_size_o = 2'b01;
rv32i_ins = ins_expanded;
end else begin
pfu_ack_size_o = 2'b10;
rv32i_ins = pfu_ins_i;
end
end
//--------------------------------------------------------------
// instruction decoder
//--------------------------------------------------------------
merlin_rv32i_decoder i_merlin_rv32i_decoder (
// instruction decoder interface
// ingress side
.ins_i (rv32i_ins),
// egress side
.ins_err_o (rv32i_ins_uerr),
.fencei_o (fencei_d),
.wfi_o (wfi_d),
.jump_o (jump_d),
.ecall_o (ecall_d),
.trap_rtn_o (trap_rtn_d),
.trap_rtn_mode_o (trap_rtn_mode_d),
.zone_o (zone_d),
.regd_tgt_o (regd_tgt),
.regd_addr_o (regd_addr_d),
.regs1_rd_o (regs1_rd_d),
.regs1_addr_o (regs1_addr_d),
.regs2_rd_o (regs2_rd_d),
.regs2_addr_o (regs2_addr_d),
.imm_o (imm_d),
.link_o (link_d),
.sels1_pc_o (sels1_pc_d),
.sel_csr_wr_data_imm_o (sel_csr_wr_data_imm_d),
.sels2_imm_o (sels2_imm_d),
.selcmps2_imm_o (selcmps2_imm_d),
.aluop_o (alu_op_d),
.funct3_o (funct3_d),
.csr_rd_o (csr_rd_d),
.csr_wr_o (csr_wr_d),
.csr_addr_o (csr_addr_d),
.conditional_o (conditional_d)
);
//--------------------------------------------------------------
// id stage stall controller
//--------------------------------------------------------------
/* *** RULES ***
* No register can have more than one pending load at any given time
* - This is to prevent the flag being cleared prematuraly by the first load
* No register can be targeted if it has a pending load
*
*/
assign s1_lq_fwd_available = (lsq_reg_wr_i && (lsq_reg_addr_i == regs1_addr_d));
assign s2_lq_fwd_available = (lsq_reg_wr_i && (lsq_reg_addr_i == regs2_addr_d));
//
always @ (*) begin
ids_stall = 1'b0;
//
if (pfu_dav_i) begin
// if reading reg_s1, it's loading, and there's no forward available, then stall
if (regs1_addr_d != 5'b0 && regs1_rd_d &&
reg_loading_vector_q[regs1_addr_d] && !s1_lq_fwd_available) begin
ids_stall = 1'b1;
end
// if reading reg_s2, it's loading, and there's no forward available, then stall
if (regs2_addr_d != 5'b0 && regs2_rd_d &&
reg_loading_vector_q[regs2_addr_d] && !s2_lq_fwd_available) begin
ids_stall = 1'b1;
end
// if targeting reg_d and it's loading, then stall
if (regd_addr_d != 5'b0 && regd_tgt && reg_loading_vector_q[regd_addr_d]) begin
ids_stall = 1'b1;
end
end
end
//
always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin
if (reset_i) begin
reg_loading_vector_q <= 31'b0;
end else begin
if (regd_addr_d != 5'b0 && id_stage_en && zone_d == `RV_ZONE_LOADQ) begin
`RV_ASSERT(reg_loading_vector_q[regd_addr_d] == 1'b0, "Register marked as pending load when already pending.")
reg_loading_vector_q[regd_addr_d] <= 1'b1;
end
if (exs_regd_addr_i != 5'b0 && exs_regd_cncl_load_i) begin
`RV_ASSERT(reg_loading_vector_q[exs_regd_addr_i] == 1'b1, "Load canceled when not pending.")
reg_loading_vector_q[exs_regd_addr_i] <= 1'b0;
end
if (lsq_reg_addr_i != 5'b0 && lsq_reg_wr_i) begin
`RV_ASSERT(reg_loading_vector_q[lsq_reg_addr_i] == 1'b1, "Load written when not pending.")
reg_loading_vector_q[lsq_reg_addr_i] <= 1'b0;
end
end
end
//--------------------------------------------------------------
// integer register file
//--------------------------------------------------------------
merlin_int_regs i_merlin_int_regs (
// global
.clk_i (clk_i),
.reset_i (reset_i),
// write port
.wreg_a_wr_i (exs_regd_wr_i),
.wreg_a_addr_i (exs_regd_addr_i),
.wreg_a_data_i (exs_regd_data_i),
.wreg_b_wr_i (lsq_reg_wr_i),
.wreg_b_addr_i (lsq_reg_addr_i),
.wreg_b_data_i (lsq_reg_data_i),
// read port
.rreg_a_rd_i (regs1_rd_q),
.rreg_a_addr_i (regs1_addr_q),
.rreg_a_data_o (regs1_dout),
.rreg_b_rd_i (regs2_rd_q),
.rreg_b_addr_i (regs2_addr_q),
.rreg_b_data_o (regs2_dout)
);
//--------------------------------------------------------------
// id register stage
//--------------------------------------------------------------
always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin
if (reset_i) begin
exs_valid_o <= 1'b0;
end else begin
if (id_stage_en) begin
exs_valid_o <= 1'b1;
end else if (~exs_stall) begin
exs_valid_o <= 1'b0;
end
end
end
always @ `RV_SYNC_LOGIC_CLOCK(clk_i) begin
if (id_stage_en) begin
exs_ins_o <= { { `RV_XLEN-32 {1'b0} }, pfu_ins_i };
exs_sofid_o <= pfu_sofid_i;
exs_fencei_o <= fencei_d;
exs_wfi_o <= wfi_d;
exs_jump_o <= jump_d;
exs_ecall_o <= ecall_d;
exs_trap_rtn_o <= trap_rtn_d;
exs_trap_rtn_mode_o <= trap_rtn_mode_d;
pc_q <= pfu_pc_i;
exs_ins_size_o <= pfu_ack_size_o;
exs_ins_uerr_o <= ins_uerr_d;
exs_ins_ferr_o <= pfu_ferr_i;
exs_zone_o <= zone_d;
exs_regd_addr_o <= regd_addr_d;
imm_q <= imm_d;
exs_link_o <= link_d;
sels1_pc_q <= sels1_pc_d;
sel_csr_wr_data_imm_q <= sel_csr_wr_data_imm_d;
sels2_imm_q <= sels2_imm_d;
selcmps2_imm_q <= selcmps2_imm_d;
exs_alu_op_o <= alu_op_d;
exs_funct3_o <= funct3_d;
exs_csr_rd_o <= csr_rd_d;
exs_csr_wr_o <= csr_wr_d;
exs_csr_addr_o <= csr_addr_d;
exs_cond_o <= conditional_d;
// register read addr/control delay
regs1_rd_q <= regs1_rd_d;
regs1_addr_q <= regs1_addr_d;
regs2_rd_q <= regs2_rd_d;
regs2_addr_q <= regs2_addr_d;
end
end
//--------------------------------------------------------------
// operand forwarding mux
//--------------------------------------------------------------
// forwarding mux for s1
always @ (*) begin
if (regs1_addr_q == 5'b0) begin
// register x0 is always valid
fwd_mux_regs1_data = regs1_dout;
end else if (exs_regd_wr_i && exs_regd_addr_i == regs1_addr_q) begin
// operand at alu output
fwd_mux_regs1_data = exs_regd_data_i;
end else if (lsq_reg_wr_i && lsq_reg_addr_i == regs1_addr_q) begin
// operand at load queue write-back output
fwd_mux_regs1_data = lsq_reg_data_i;
end else begin
// operand at register file output
fwd_mux_regs1_data = regs1_dout;
end
end
// forwarding mux for s2
always @ (*) begin
if (regs2_addr_q == 5'b0) begin
// register x0 is always valid
fwd_mux_regs2_data = regs2_dout;
end else if (exs_regd_wr_i && exs_regd_addr_i == regs2_addr_q) begin
// operand at alu output
fwd_mux_regs2_data = exs_regd_data_i;
end else if (lsq_reg_wr_i && lsq_reg_addr_i == regs2_addr_q) begin
// operand at load queue write-back output
fwd_mux_regs2_data = lsq_reg_data_i;
end else begin
// operand at register file output
fwd_mux_regs2_data = regs2_dout;
end
end
//--------------------------------------------------------------
// left operand select mux
//--------------------------------------------------------------
always @ (*) begin
if (sels1_pc_q) begin
exs_operand_left_o = pc_q;
end else begin
exs_operand_left_o = fwd_mux_regs1_data;
end
end
//--------------------------------------------------------------
// right operand select mux
//--------------------------------------------------------------
always @ (*) begin
if (sels2_imm_q) begin
exs_operand_right_o = imm_q;
end else begin
exs_operand_right_o = fwd_mux_regs2_data;
end
end
//--------------------------------------------------------------
// right cmp select mux
//--------------------------------------------------------------
always @ (*) begin
if (selcmps2_imm_q) begin
exs_cmp_right_o = imm_q;
end else begin
exs_cmp_right_o = fwd_mux_regs2_data;
end
end
//--------------------------------------------------------------
// csr write data select mux
//--------------------------------------------------------------
always @ (*) begin
if (sel_csr_wr_data_imm_q) begin
exs_csr_wr_data_o = imm_q;
end else begin
exs_csr_wr_data_o = fwd_mux_regs1_data;
end
end
//--------------------------------------------------------------
// assersions
//--------------------------------------------------------------
`ifdef RV_ASSERTS_ON
always @ `RV_SYNC_LOGIC_CLOCK(clk_i) begin
// register file access assertions
`RV_ASSERT(
!(pfu_ack_o == 1'b1 &&
regs1_addr_d != 5'b0 && regs1_rd_d &&
reg_loading_vector_q[regs1_addr_d] && !s1_lq_fwd_available),
"Register read when pending a load."
)
`RV_ASSERT(
!(pfu_ack_o == 1'b1 &&
regs2_addr_d != 5'b0 && regs2_rd_d &&
reg_loading_vector_q[regs2_addr_d] && !s2_lq_fwd_available),
"Register read when pending a load."
)
end
`endif
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_debug_if.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core debug interface. ////
//// ////
//// Author(s): ////
//// - [email protected] ////
//// - Jacob Gorban ////
//// ////
//// Created: 2001/12/02 ////
//// (See log for the revision history) ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: uart_debug_if.v,v $
// Revision 1.1 2006-12-21 16:46:58 vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.5 2002/07/29 21:16:18 gorban
// The uart_defines.v file is included again in sources.
//
// Revision 1.4 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.3 2001/12/19 08:40:03 mohor
// Warnings fixed (unused signals removed).
//
// Revision 1.2 2001/12/12 22:17:30 gorban
// some synthesis bugs fixed
//
// Revision 1.1 2001/12/04 21:14:16 gorban
// committed the debug interface file
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "uart_defines.v"
module uart_debug_if (/*AUTOARG*/
// Outputs
wb_dat32_o,
// Inputs
wb_adr_i, ier, iir, fcr, mcr, lcr, msr,
lsr, rf_count, tf_count, tstate, rstate
) ;
input [`UART_ADDR_WIDTH-1:0] wb_adr_i;
output [31:0] wb_dat32_o;
input [3:0] ier;
input [3:0] iir;
input [1:0] fcr; /// bits 7 and 6 of fcr. Other bits are ignored
input [4:0] mcr;
input [7:0] lcr;
input [7:0] msr;
input [7:0] lsr;
input [`UART_FIFO_COUNTER_W-1:0] rf_count;
input [`UART_FIFO_COUNTER_W-1:0] tf_count;
input [2:0] tstate;
input [3:0] rstate;
wire [`UART_ADDR_WIDTH-1:0] wb_adr_i;
reg [31:0] wb_dat32_o;
always @(/*AUTOSENSE*/fcr or ier or iir or lcr or lsr or mcr or msr
or rf_count or rstate or tf_count or tstate or wb_adr_i)
case (wb_adr_i)
// 8 + 8 + 4 + 4 + 8
5'b01000: wb_dat32_o = {msr,lcr,iir,ier,lsr};
// 5 + 2 + 5 + 4 + 5 + 3
5'b01100: wb_dat32_o = {8'b0, fcr,mcr, rf_count, rstate, tf_count, tstate};
default: wb_dat32_o = 0;
endcase // case(wb_adr_i)
endmodule // uart_debug_if
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKINV_8_V
`define SKY130_FD_SC_LP__CLKINV_8_V
/**
* clkinv: Clock tree inverter.
*
* Verilog wrapper for clkinv with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__clkinv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkinv_8 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkinv_8 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__clkinv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKINV_8_V
|
/*
* Copyright 2017 Google Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`define IVERILOG_SIM
`define TEST_PROG "prog_load_out.list"
`include "top.v"
module top_test_load_out;
localparam WIDTH = 8;
localparam UART_WIDTH = $clog2(WIDTH);
localparam OUTPUT_CNT = 7;
reg clk = 1;
reg uart_clk = 0;
reg receiving = 0;
reg display = 0;
reg [UART_WIDTH-1 : 0] serial_cnt = 0;
reg [WIDTH-1 : 0] serial_data;
wire uart_tx;
reg [WIDTH-1 : 0] expected_output = 0;
always #2 clk = !clk;
always #4 uart_clk = !uart_clk;
top t(
.clk(clk),
.uart_tx_line(uart_tx));
always @ (posedge uart_clk) begin
if (receiving) begin
if (serial_cnt == WIDTH - 1 ) begin
receiving <= 0;
display <= 1;
end
serial_data[serial_cnt] <= uart_tx;
serial_cnt <= serial_cnt + 1;
end else if (display) begin
if (expected_output >= OUTPUT_CNT) begin
$display("Load and output test passed!\n");
$finish;
end
if (serial_data != expected_output) begin
$display("Load and output test failed!\n");
$display("Serial output:%d doesn't match expected_output:%d\n",
serial_data, expected_output);
$finish;
end
expected_output <= expected_output + 1;
display <= 0;
end else begin
if (uart_tx == 0) begin
receiving <= 1;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O31AI_BLACKBOX_V
`define SKY130_FD_SC_HDLL__O31AI_BLACKBOX_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o31ai (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O31AI_BLACKBOX_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
//`timescale 1n/100ps;
module usdrx1_cpld (
// Bank 1.8 V
fmc_dac_db,
fmc_dac_sleep,
fmc_clkd_spi_sclk,
fmc_clkd_spi_csb,
fmc_clkd_spi_sdio,
fmc_clkd_syncn,
fmc_clkd_resetn,
//fmc_clkd_status,
//tbd1
//tbd2
//tbd3
// Bank 3.3 V
dac_db,
dac_sleep,
clkd_spi_sclk,
clkd_spi_csb,
clkd_spi_sdio,
//clkd_status,
clkd_syncn,
clkd_resetn
);
// Bank 1.8 V
input [13:0] fmc_dac_db;
input fmc_dac_sleep;
input fmc_clkd_spi_sclk;
input fmc_clkd_spi_csb;
inout fmc_clkd_spi_sdio;
input fmc_clkd_syncn;
input fmc_clkd_resetn;
//output fmc_clkd_status;
//tbd1;
//tbd2;
//tbd3;
// Bank 3.3 V
output [13:0] dac_db;
output dac_sleep;
output clkd_spi_sclk;
output clkd_spi_csb;
inout clkd_spi_sdio;
//input clkd_status;
output clkd_syncn;
output clkd_resetn;
reg [15:0] cnt ;
reg fpga_to_clkd ; // 1 if fpga sends data to ad9517, 0 if fpga reads data from ad9517
reg spi_r_wn ;
assign dac_db = fmc_dac_db;
assign dac_sleep = fmc_dac_sleep;
assign clkd_spi_sclk = fmc_clkd_spi_sclk;
assign clkd_spi_csb = fmc_clkd_spi_csb;
assign clkd_spi_sdio = fpga_to_clkd ? fmc_clkd_spi_sdio : 1'bZ;
assign fmc_clkd_spi_sdio = fpga_to_clkd ? 1'bZ :clkd_spi_sdio;
assign clkd_syncn = fmc_clkd_syncn;
assign clkd_resetn = fmc_clkd_resetn;
//assign fmc_clkd_status = clkd_status;
always @ (posedge fmc_clkd_spi_sclk or posedge fmc_clkd_spi_csb)
begin
if (fmc_clkd_spi_csb == 1'b1)
begin
cnt <= 0;
spi_r_wn <= 1;
end
else
begin
cnt <= cnt + 1;
if (cnt == 0)
begin
spi_r_wn <= fmc_clkd_spi_sdio;
end
end
end
always @(negedge fmc_clkd_spi_sclk or posedge fmc_clkd_spi_csb)
begin
if (fmc_clkd_spi_csb == 1'b1)
begin
fpga_to_clkd <= 1;
end
else
begin
if (cnt == 16)
begin
fpga_to_clkd <= ~spi_r_wn;
end
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_comparator_static #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 6;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = C_VALUE;
end
// Instantiate one generic_baseblocks_v2_1_carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] );
// Instantiate each LUT level.
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
// MBT 9-7-2014
//
// two element fifo
//
// helpful interface on both input and output
//
// input : ready/valid flow control (rv->&)
// output: valid->yumi flow control ( v->r)
//
// see https://github.com/bespoke-silicon-group/basejump_stl/blob/master/docs/BaseJump_STL_DAC_2018_Camera_Ready.pdf
// to understand the flow control standards in BaseJump STL.
//
// INPUTS: although this module's inputs adheres to
// ready/valid protocol where both sender and receiver
// AND the two signals together to determine
// if transaction happened; in some cases, we
// know that the sender takes into account the
// ready signal before sending out valid, and the
// check is unnecessary. We use ready_THEN_valid_p
// to remove the check if it is unnecessary.
//
//
// note: ~v_o == fifo is empty.
//
`include "bsg_defines.v"
module bsg_two_fifo #(parameter `BSG_INV_PARAM(width_p)
, parameter verbose_p=0
// whether we should allow simultaneous enque and deque on full
, parameter allow_enq_deq_on_full_p=0
// necessarily, if we allow enq on ready low, then
// we are not using a ready/valid protocol
, parameter ready_THEN_valid_p=allow_enq_deq_on_full_p
)
(input clk_i
, input reset_i
// input side
, output ready_o // early
, input [width_p-1:0] data_i // late
, input v_i // late
// output side
, output v_o // early
, output[width_p-1:0] data_o // early
, input yumi_i // late
);
wire deq_i = yumi_i;
wire enq_i;
logic head_r, tail_r;
logic empty_r, full_r;
bsg_mem_1r1w #(.width_p(width_p)
,.els_p(2)
,.read_write_same_addr_p(allow_enq_deq_on_full_p)
) mem_1r1w
(.w_clk_i (clk_i )
,.w_reset_i(reset_i)
,.w_v_i (enq_i )
,.w_addr_i (tail_r )
,.w_data_i (data_i )
,.r_v_i (~empty_r)
,.r_addr_i (head_r )
,.r_data_o (data_o )
);
assign v_o = ~empty_r;
assign ready_o = ~full_r;
if (ready_THEN_valid_p)
assign enq_i = v_i;
else
assign enq_i = v_i & ~full_r;
always_ff @(posedge clk_i)
begin
if (reset_i)
begin
tail_r <= 1'b0;
head_r <= 1'b0;
empty_r <= 1'b1;
full_r <= 1'b0;
end
else
begin
if (enq_i)
tail_r <= ~tail_r;
if (deq_i)
head_r <= ~head_r;
// logic simplifies nicely for 2 element case
empty_r <= ( empty_r & ~enq_i)
| (~full_r & deq_i & ~enq_i);
if (allow_enq_deq_on_full_p)
full_r <= ( ~empty_r & enq_i & ~deq_i)
| ( full_r & ~(deq_i^enq_i));
else
full_r <= ( ~empty_r & enq_i & ~deq_i)
| ( full_r & ~deq_i);
end // else: !if(reset_i)
end // always_ff @
// synopsys translate_off
always_ff @(posedge clk_i)
begin
if (~reset_i)
begin
assert ({empty_r, deq_i} !== 2'b11)
else $error("invalid deque on empty fifo ", empty_r, deq_i);
if (allow_enq_deq_on_full_p)
begin
assert ({full_r,enq_i,deq_i} !== 3'b110)
else $error("invalid enque on full fifo ", full_r, enq_i);
end
else
assert ({full_r,enq_i} !== 2'b11)
else $error("invalid enque on full fifo ", full_r, enq_i);
assert ({full_r,empty_r} !== 2'b11)
else $error ("fifo full and empty at same time ", full_r, empty_r);
end // if (~reset_i)
end // always_ff @
always_ff @(posedge clk_i)
if (verbose_p)
begin
if (enq_i)
$display("### %m enq %x onto fifo",data_i);
if (deq_i)
$display("### %m deq %x from fifo",data_o);
end
// for debugging
wire [31:0] num_elements_debug = full_r + (empty_r==0);
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_two_fifo)
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/);
// IEEE: integer_atom_type
byte d_byte;
shortint d_shortint;
int d_int;
longint d_longint;
integer d_integer;
time d_time;
chandle d_chandle;
// IEEE: integer_atom_type
bit d_bit;
logic d_logic;
reg d_reg;
bit [0:0] d_bit1;
logic [0:0] d_logic1;
reg [0:0] d_reg1;
bit d_bitz;
logic d_logicz;
reg d_regz;
// IEEE: non_integer_type
//UNSUP shortreal d_shortreal;
real d_real;
realtime d_realtime;
initial begin
// below errors might cause spurious warnings
// verilator lint_off WIDTH
d_bitz[0] = 1'b1; // Illegal range
d_logicz[0] = 1'b1; // Illegal range
d_regz[0] = 1'b1; // Illegal range
`ifndef VERILATOR //UNSUPPORTED, it's just a 64 bit int right now
d_chandle[0] = 1'b1; // Illegal
`endif
d_real[0] = 1'b1; // Illegal
d_realtime[0] = 1'b1; // Illegal
// verilator lint_on WIDTH
d_byte[0] = 1'b1; // OK
d_shortint[0] = 1'b1; // OK
d_int[0] = 1'b1; // OK
d_longint[0] = 1'b1; // OK
d_integer[0] = 1'b1; // OK
d_time[0] = 1'b1; // OK
d_bit1[0] = 1'b1; // OK
d_logic1[0] = 1'b1; // OK
d_reg1[0] = 1'b1; // OK
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 08:52:46 2016
/////////////////////////////////////////////////////////////
module FPU_PIPELINED_FPADDSUB_W64_EW11_SW52_SWR55_EWR6 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [63:0] Data_X;
input [63:0] Data_Y;
output [63:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire Shift_reg_FLAGS_7_6, intAS, SIGN_FLAG_EXP, OP_FLAG_EXP, ZERO_FLAG_EXP,
SIGN_FLAG_SHT1, OP_FLAG_SHT1, ZERO_FLAG_SHT1, ADD_OVRFLW_NRM,
left_right_SHT2, bit_shift_SHT2, SIGN_FLAG_SHT2, OP_FLAG_SHT2,
ZERO_FLAG_SHT2, ADD_OVRFLW_NRM2, SIGN_FLAG_SHT1SHT2,
ZERO_FLAG_SHT1SHT2, SIGN_FLAG_NRM, ZERO_FLAG_NRM, SIGN_FLAG_SFG,
OP_FLAG_SFG, ZERO_FLAG_SFG, inst_FSM_INPUT_ENABLE_state_next_1_,
n1102, n1103, n1104, n1105, n1106, n1107, n1108, n1109, n1110, n1111,
n1112, n1113, n1114, n1115, n1116, n1117, n1118, n1119, n1120, n1121,
n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129, n1130, n1131,
n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139, n1140, n1141,
n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149, n1150, n1151,
n1152, n1153, n1154, n1155, n1156, n1157, n1158, n1159, n1160, n1161,
n1162, n1163, n1164, n1165, n1166, n1167, n1168, n1169, n1170, n1171,
n1172, n1173, n1174, n1175, n1176, n1177, n1178, n1179, n1180, n1181,
n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189, n1190, n1191,
n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200, n1201,
n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210, n1211,
n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220, n1221,
n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1230, n1231,
n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240, n1241,
n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250, n1251,
n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260, n1261,
n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270, n1271,
n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280, n1281,
n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290, n1291,
n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300, n1301,
n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310, n1311,
n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320, n1321,
n1322, n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330, n1331,
n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340, n1341,
n1342, n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350, n1351,
n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360, n1361,
n1362, n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370, n1371,
n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380, n1381,
n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1391,
n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400, n1401,
n1402, n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410, n1411,
n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420, n1421,
n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431,
n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441,
n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451,
n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461,
n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470, n1471,
n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1480, n1481,
n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491,
n1492, n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1501,
n1502, n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510, n1511,
n1512, n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520, n1521,
n1522, n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530, n1531,
n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540, n1541,
n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550, n1551,
n1552, n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560, n1561,
n1562, n1563, n1564, n1565, n1566, n1567, n1568, n1569, n1570, n1571,
n1572, n1573, n1574, n1575, n1576, n1577, n1578, n1579, n1580, n1581,
n1582, n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590, n1591,
n1592, n1593, n1594, n1595, n1596, n1597, n1598, n1599, n1600, n1601,
n1602, n1603, n1604, n1605, n1606, n1607, n1608, n1609, n1610, n1611,
n1612, n1613, n1614, n1615, n1616, n1617, n1618, n1619, n1620, n1621,
n1622, n1623, n1624, n1625, n1626, n1627, n1628, n1629, n1630, n1631,
n1632, n1633, n1634, n1635, n1636, n1637, n1638, n1639, n1640, n1641,
n1642, n1643, n1644, n1645, n1646, n1647, n1648, n1649, n1650, n1651,
n1652, n1653, n1654, n1655, n1656, n1657, n1658, n1659, n1660, n1661,
n1662, n1663, n1664, n1665, n1666, n1667, n1668, n1669, n1670, n1671,
n1672, n1673, n1674, n1675, n1676, n1677, n1678, n1679, n1680, n1681,
n1682, n1683, n1684, n1685, n1686, n1687, n1688, n1689, n1690, n1691,
n1692, n1693, n1695, n1696, n1697, n1698, n1699, n1700, n1701, n1702,
n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710, n1711, n1712,
n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720, n1721, n1722,
n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1730, n1731, n1732,
n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740, n1741, n1742,
n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750, n1751, n1752,
n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760, n1761, n1762,
n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770, n1771, n1772,
n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780, n1781, n1782,
n1783, n1784, n1785, n1786, n1787, n1788, n1789, n1790, n1791, n1792,
n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800, n1801, n1802,
n1803, n1804, n1805, n1806, n1807, n1808, n1809, n1810, n1811, n1812,
n1813, n1814, n1815, n1816, n1817, n1818, n1819, n1820, n1821, n1822,
n1823, n1824, n1825, n1826, n1827, n1828, n1829, n1830, n1831, n1832,
n1833, n1834, n1835, n1836, n1837, n1838, n1839, n1840, n1841, n1842,
n1843, n1844, n1845, n1846, n1847, n1848, n1849, n1850, n1851, n1852,
n1853, n1854, n1855, n1856, n1857, n1858, n1859, n1860, n1861, n1862,
n1863, n1864, n1865, n1866, n1867, n1868, n1869, n1870, n1871, n1872,
n1873, n1874, n1875, n1876, n1877, n1878, n1879, n1880, n1881, n1882,
n1883, n1884, n1885, n1886, n1887, n1888, n1889, n1890, n1891, n1892,
DP_OP_15J155_122_2221_n35, n1899, n1900, n1901, n1902, n1903, n1904,
n1905, n1906, n1907, n1908, n1909, n1910, n1911, n1912, n1913, n1914,
n1915, n1916, n1917, n1918, n1919, n1920, n1921, n1922, n1923, n1924,
n1925, n1926, n1927, n1928, n1929, n1930, n1931, n1932, n1933, n1934,
n1935, n1936, n1937, n1938, n1939, n1940, n1941, n1942, n1943, n1944,
n1945, n1946, n1947, n1948, n1949, n1950, n1951, n1952, n1953, n1954,
n1955, n1956, n1957, n1958, n1959, n1960, n1961, n1962, n1963, n1964,
n1965, n1966, n1967, n1968, n1969, n1970, n1971, n1972, n1973, n1974,
n1975, n1976, n1977, n1978, n1979, n1980, n1981, n1982, n1983, n1984,
n1985, n1986, n1987, n1988, n1989, n1990, n1991, n1992, n1993, n1994,
n1995, n1996, n1997, n1998, n1999, n2000, n2001, n2002, n2003, n2004,
n2005, n2006, n2007, n2008, n2009, n2010, n2011, n2012, n2013, n2014,
n2015, n2016, n2017, n2018, n2019, n2020, n2021, n2022, n2023, n2024,
n2025, n2026, n2027, n2028, n2029, n2030, n2031, n2032, n2033, n2034,
n2035, n2036, n2037, n2038, n2039, n2040, n2041, n2042, n2043, n2044,
n2045, n2046, n2047, n2048, n2049, n2050, n2051, n2052, n2053, n2054,
n2055, n2056, n2057, n2058, n2059, n2060, n2061, n2062, n2063, n2064,
n2065, n2066, n2067, n2068, n2069, n2070, n2071, n2072, n2073, n2074,
n2075, n2076, n2077, n2078, n2079, n2080, n2081, n2082, n2083, n2084,
n2085, n2086, n2087, n2088, n2089, n2090, n2091, n2092, n2093, n2094,
n2095, n2096, n2097, n2098, n2099, n2100, n2101, n2102, n2103, n2104,
n2105, n2106, n2107, n2108, n2109, n2110, n2111, n2112, n2113, n2114,
n2115, n2116, n2117, n2118, n2119, n2120, n2121, n2122, n2123, n2124,
n2125, n2126, n2127, n2128, n2129, n2130, n2131, n2132, n2133, n2134,
n2135, n2136, n2137, n2138, n2139, n2140, n2141, n2142, n2143, n2144,
n2145, n2146, n2147, n2148, n2149, n2150, n2151, n2152, n2153, n2154,
n2155, n2156, n2157, n2158, n2159, n2160, n2161, n2162, n2163, n2164,
n2165, n2166, n2167, n2168, n2169, n2170, n2171, n2172, n2173, n2174,
n2175, n2176, n2177, n2178, n2179, n2180, n2181, n2182, n2183, n2184,
n2185, n2186, n2187, n2188, n2189, n2190, n2191, n2192, n2193, n2194,
n2195, n2196, n2197, n2198, n2199, n2200, n2201, n2202, n2203, n2204,
n2205, n2206, n2207, n2208, n2209, n2210, n2211, n2212, n2213, n2214,
n2215, n2216, n2217, n2218, n2219, n2220, n2221, n2222, n2223, n2224,
n2225, n2226, n2227, n2228, n2229, n2230, n2231, n2232, n2233, n2234,
n2235, n2236, n2237, n2238, n2239, n2240, n2241, n2242, n2243, n2244,
n2245, n2246, n2247, n2248, n2249, n2250, n2251, n2252, n2253, n2254,
n2255, n2256, n2257, n2258, n2259, n2260, n2261, n2262, n2263, n2264,
n2265, n2266, n2267, n2268, n2269, n2270, n2271, n2272, n2273, n2274,
n2275, n2276, n2277, n2278, n2279, n2280, n2281, n2282, n2283, n2284,
n2285, n2286, n2287, n2288, n2289, n2290, n2291, n2292, n2293, n2294,
n2295, n2296, n2297, n2298, n2299, n2300, n2301, n2302, n2303, n2304,
n2305, n2306, n2307, n2308, n2309, n2310, n2311, n2312, n2313, n2314,
n2315, n2316, n2317, n2318, n2319, n2320, n2321, n2322, n2323, n2324,
n2325, n2326, n2327, n2328, n2329, n2330, n2331, n2332, n2333, n2334,
n2335, n2336, n2337, n2338, n2339, n2340, n2341, n2342, n2343, n2344,
n2345, n2346, n2347, n2348, n2349, n2350, n2351, n2352, n2353, n2354,
n2355, n2356, n2357, n2358, n2359, n2360, n2361, n2362, n2363, n2364,
n2365, n2366, n2367, n2368, n2369, n2370, n2371, n2372, n2373, n2374,
n2375, n2376, n2377, n2378, n2379, n2380, n2381, n2382, n2383, n2384,
n2385, n2386, n2387, n2388, n2389, n2390, n2391, n2392, n2393, n2394,
n2395, n2396, n2397, n2398, n2399, n2400, n2401, n2402, n2403, n2404,
n2405, n2406, n2407, n2408, n2409, n2410, n2411, n2412, n2413, n2414,
n2415, n2416, n2417, n2418, n2419, n2420, n2421, n2422, n2423, n2424,
n2425, n2426, n2427, n2428, n2429, n2430, n2431, n2432, n2433, n2434,
n2435, n2436, n2437, n2438, n2439, n2440, n2441, n2442, n2443, n2444,
n2445, n2446, n2447, n2448, n2449, n2450, n2451, n2452, n2453, n2454,
n2455, n2456, n2457, n2458, n2459, n2460, n2461, n2462, n2463, n2464,
n2465, n2466, n2467, n2468, n2469, n2470, n2471, n2472, n2473, n2474,
n2475, n2476, n2477, n2478, n2479, n2480, n2481, n2482, n2483, n2484,
n2485, n2486, n2487, n2488, n2489, n2490, n2491, n2492, n2493, n2494,
n2495, n2496, n2497, n2498, n2499, n2500, n2501, n2502, n2503, n2504,
n2505, n2506, n2507, n2508, n2509, n2510, n2511, n2512, n2513, n2514,
n2515, n2516, n2517, n2518, n2519, n2520, n2521, n2522, n2523, n2524,
n2525, n2526, n2527, n2528, n2529, n2530, n2531, n2532, n2533, n2534,
n2535, n2536, n2537, n2538, n2539, n2540, n2541, n2542, n2543, n2544,
n2545, n2546, n2547, n2548, n2549, n2550, n2551, n2552, n2553, n2554,
n2555, n2556, n2557, n2558, n2559, n2560, n2561, n2562, n2563, n2564,
n2565, n2566, n2567, n2568, n2569, n2570, n2571, n2572, n2573, n2574,
n2575, n2576, n2577, n2578, n2579, n2580, n2581, n2582, n2583, n2584,
n2585, n2586, n2587, n2588, n2589, n2590, n2591, n2592, n2593, n2594,
n2595, n2596, n2597, n2598, n2599, n2600, n2601, n2602, n2603, n2604,
n2605, n2606, n2607, n2608, n2609, n2610, n2611, n2612, n2613, n2614,
n2615, n2616, n2617, n2618, n2619, n2620, n2621, n2622, n2623, n2624,
n2625, n2626, n2627, n2628, n2629, n2630, n2631, n2632, n2633, n2634,
n2635, n2636, n2637, n2638, n2639, n2640, n2641, n2642, n2643, n2644,
n2645, n2646, n2647, n2648, n2649, n2650, n2651, n2652, n2653, n2654,
n2655, n2656, n2657, n2658, n2659, n2660, n2661, n2662, n2663, n2664,
n2665, n2666, n2667, n2668, n2669, n2670, n2671, n2672, n2673, n2674,
n2675, n2676, n2677, n2678, n2679, n2680, n2681, n2682, n2683, n2684,
n2685, n2686, n2687, n2688, n2689, n2690, n2691, n2692, n2693, n2694,
n2695, n2696, n2697, n2698, n2699, n2700, n2701, n2702, n2703, n2704,
n2705, n2706, n2707, n2708, n2709, n2710, n2711, n2712, n2713, n2714,
n2715, n2716, n2717, n2718, n2719, n2720, n2721, n2722, n2723, n2724,
n2725, n2726, n2727, n2728, n2729, n2730, n2731, n2732, n2733, n2734,
n2735, n2736, n2737, n2738, n2739, n2740, n2741, n2742, n2743, n2744,
n2745, n2746, n2747, n2748, n2749, n2750, n2751, n2752, n2753, n2754,
n2755, n2756, n2757, n2758, n2759, n2760, n2761, n2762, n2763, n2764,
n2765, n2766, n2767, n2768, n2769, n2770, n2771, n2772, n2773, n2774,
n2775, n2776, n2777, n2778, n2779, n2780, n2781, n2782, n2783, n2784,
n2785, n2786, n2787, n2788, n2789, n2790, n2791, n2792, n2793, n2794,
n2795, n2796, n2797, n2798, n2799, n2800, n2801, n2802, n2803, n2804,
n2805, n2806, n2807, n2808, n2809, n2810, n2811, n2812, n2813, n2814,
n2815, n2816, n2817, n2818, n2819, n2820, n2821, n2822, n2823, n2824,
n2825, n2826, n2827, n2828, n2829, n2830, n2831, n2832, n2833, n2834,
n2835, n2836, n2837, n2838, n2839, n2840, n2841, n2842, n2843, n2844,
n2845, n2846, n2847, n2848, n2849, n2850, n2851, n2852, n2853, n2854,
n2855, n2856, n2857, n2858, n2859, n2860, n2861, n2862, n2863, n2864,
n2865, n2866, n2867, n2868, n2869, n2870, n2871, n2872, n2873, n2874,
n2875, n2876, n2877, n2878, n2879, n2880, n2881, n2882, n2883, n2884,
n2885, n2886, n2887, n2888, n2889, n2890, n2891, n2892, n2893, n2894,
n2895, n2896, n2897, n2898, n2899, n2900, n2901, n2902, n2903, n2904,
n2905, n2906, n2907, n2908, n2909, n2910, n2911, n2912, n2913, n2914,
n2915, n2916, n2917, n2918, n2919, n2920, n2921, n2922, n2923, n2924,
n2925, n2926, n2927, n2928, n2929, n2930, n2931, n2932, n2933, n2934,
n2935, n2936, n2937, n2938, n2939, n2940, n2941, n2942, n2943, n2944,
n2945, n2946, n2947, n2948, n2949, n2950, n2951, n2952, n2953, n2954,
n2955, n2956, n2957, n2958, n2959, n2960, n2961, n2962, n2963, n2964,
n2965, n2966, n2967, n2968, n2969, n2970, n2971, n2972, n2973, n2974,
n2975, n2976, n2977, n2978, n2979, n2980, n2981, n2982, n2983, n2984,
n2985, n2986, n2987, n2988, n2989, n2990, n2991, n2992, n2993, n2994,
n2995, n2996, n2997, n2998, n2999, n3000, n3001, n3002, n3003, n3004,
n3005, n3006, n3007, n3008, n3009, n3010, n3011, n3012, n3013, n3014,
n3015, n3016, n3017, n3018, n3019, n3020, n3021, n3022, n3023, n3024,
n3025, n3026, n3027, n3028, n3029, n3030, n3031, n3032, n3033, n3034,
n3035, n3036, n3037, n3038, n3039, n3040, n3041, n3042, n3043, n3044,
n3045, n3046, n3047, n3048, n3049, n3050, n3051, n3052, n3053, n3054,
n3055, n3056, n3057, n3058, n3059, n3060, n3061, n3062, n3063, n3064,
n3065, n3066, n3067, n3068, n3069, n3070, n3071, n3072, n3073, n3074,
n3075, n3076, n3077, n3078, n3079, n3080, n3081, n3082, n3083, n3084,
n3085, n3086, n3087, n3088, n3089, n3090, n3091, n3092, n3093, n3094,
n3095, n3096, n3097, n3098, n3099, n3100, n3101, n3102, n3103, n3104,
n3105, n3106, n3107, n3108, n3109, n3110, n3111, n3112, n3113, n3114,
n3115, n3116, n3117, n3118, n3119, n3120, n3121, n3122, n3123, n3124,
n3125, n3126, n3127, n3128, n3129, n3130, n3131, n3132, n3133, n3134,
n3135, n3136, n3137, n3138, n3139, n3140, n3141, n3142, n3143, n3144,
n3145, n3146, n3147, n3148, n3149, n3150, n3151, n3152, n3153, n3154,
n3155, n3156, n3157, n3158, n3159, n3160, n3161, n3162, n3163, n3164,
n3165, n3166, n3167, n3168, n3169, n3170, n3171, n3172, n3173, n3174,
n3175, n3176, n3177, n3178, n3179, n3180, n3181, n3182, n3183, n3184,
n3185, n3186, n3187, n3188, n3189, n3190, n3191, n3192, n3193, n3194,
n3195, n3196, n3197, n3198, n3199, n3200, n3201, n3202, n3203, n3204,
n3205, n3206, n3207, n3208, n3209, n3210, n3211, n3212, n3213, n3214,
n3215, n3216, n3217, n3218, n3219, n3220, n3221, n3222, n3223, n3224,
n3225, n3226, n3227, n3228, n3229, n3230, n3231, n3232, n3233, n3234,
n3235, n3236, n3237, n3238, n3239, n3240, n3241, n3242, n3243, n3244,
n3245, n3246, n3247, n3248, n3249, n3250, n3251, n3252, n3253, n3254,
n3255, n3256, n3257, n3258, n3259, n3260, n3261, n3262, n3263, n3264,
n3265, n3266, n3267, n3268, n3269, n3270, n3271, n3272, n3273, n3274,
n3275, n3276, n3277, n3278, n3279, n3280, n3281, n3282, n3283, n3284,
n3285, n3286, n3287, n3288, n3289, n3290, n3291, n3292, n3293, n3294,
n3295, n3296, n3297, n3298, n3299, n3300, n3301, n3302, n3303, n3304,
n3305, n3306, n3307, n3308, n3309, n3310, n3311, n3312, n3313, n3314,
n3315, n3316, n3317, n3318, n3319, n3320, n3321, n3322, n3323, n3324,
n3325, n3326, n3327, n3328, n3329, n3330, n3331, n3332, n3333, n3334,
n3335, n3336, n3337, n3338, n3339, n3340, n3341, n3342, n3343, n3344,
n3345, n3346, n3347, n3348, n3349, n3350, n3351, n3352, n3353, n3354,
n3355, n3356, n3357, n3358, n3359, n3360, n3361, n3362, n3363, n3364,
n3365, n3366, n3367, n3368, n3369, n3370, n3371, n3372, n3373, n3374,
n3375, n3376, n3377, n3378, n3379, n3380, n3381, n3382, n3383, n3384,
n3385, n3386, n3387, n3388, n3389, n3390, n3391, n3392, n3393, n3394,
n3395, n3396, n3397, n3398, n3399, n3400, n3401, n3402, n3403, n3404,
n3405, n3406, n3407, n3408, n3409, n3410, n3411, n3412, n3413, n3414,
n3415, n3416, n3417, n3418, n3419, n3420, n3421, n3422, n3423, n3424,
n3425, n3426, n3427, n3428, n3429, n3430, n3431, n3432, n3433, n3434,
n3435, n3436, n3437, n3438, n3439, n3440, n3441, n3442, n3443, n3444,
n3445, n3446, n3447, n3448, n3449, n3450, n3451, n3452, n3453, n3454,
n3455, n3456, n3457, n3458, n3459, n3460, n3461, n3462, n3463, n3464,
n3465, n3466, n3467, n3468, n3469, n3470, n3471, n3472, n3473, n3474,
n3475, n3476, n3477, n3478, n3479, n3480, n3481, n3482, n3483, n3484,
n3485, n3486, n3487, n3488, n3489, n3490, n3491, n3492, n3493, n3494,
n3495, n3496, n3497, n3498, n3499, n3500, n3501, n3502, n3503, n3504,
n3505, n3506, n3507, n3508, n3509, n3510, n3511, n3512, n3513, n3514,
n3515, n3516, n3517, n3518, n3519, n3520, n3521, n3522, n3523, n3524,
n3525, n3526, n3527, n3528, n3529, n3530, n3531, n3532, n3533, n3534,
n3535, n3536, n3537, n3538, n3539, n3540, n3541, n3542, n3543, n3544,
n3545, n3546, n3547, n3548, n3549, n3550, n3551, n3552, n3553, n3554,
n3555, n3556, n3557, n3558, n3559, n3560, n3561, n3562, n3563, n3564,
n3565, n3566, n3567, n3568, n3569, n3570, n3571, n3572, n3573, n3574,
n3575, n3576, n3577, n3578, n3579, n3580, n3581, n3582, n3583, n3584,
n3585, n3586, n3587, n3588, n3589, n3590, n3591, n3592, n3593, n3594,
n3595, n3596, n3597, n3598, n3599, n3600, n3601, n3602, n3603, n3604,
n3605, n3606, n3607, n3608, n3609, n3610, n3611, n3612, n3613, n3614,
n3615, n3616, n3617, n3618, n3619, n3620, n3621, n3622, n3623, n3624,
n3625, n3626, n3627, n3628, n3629, n3630, n3631, n3632, n3633, n3634,
n3635, n3636, n3637, n3638, n3639, n3640, n3641, n3642, n3643, n3644,
n3645, n3646, n3647, n3648, n3649, n3650, n3651, n3652, n3653, n3654,
n3655, n3656, n3657, n3658, n3659, n3660, n3661, n3662, n3663, n3664,
n3665, n3666, n3667, n3668, n3669, n3670, n3671, n3672, n3673, n3674,
n3675, n3676, n3677, n3678, n3679, n3680, n3681, n3682, n3683, n3684,
n3685, n3686, n3687, n3688, n3689, n3690, n3691, n3692, n3693, n3694,
n3695, n3696, n3697, n3698, n3699, n3700, n3701, n3702, n3704, n3705,
n3706, n3707, n3708, n3709, n3710, n3711, n3712, n3713, n3714, n3715,
n3716, n3717, n3718, n3719, n3720, n3721, n3722, n3723, n3724, n3725,
n3726, n3727, n3728, n3729, n3730, n3731, n3732, n3733, n3734, n3735,
n3736, n3737, n3738, n3739, n3740, n3741, n3742, n3743, n3744, n3745,
n3746, n3747, n3748, n3749, n3750, n3751, n3752, n3753, n3754, n3755,
n3756, n3757, n3758, n3759, n3760, n3761, n3762, n3763, n3764, n3765,
n3766, n3767, n3768, n3769, n3770, n3771, n3772, n3773, n3774, n3775,
n3776, n3777, n3778, n3779, n3780, n3781, n3782, n3783, n3784, n3785,
n3786, n3787, n3788, n3789, n3790, n3791, n3792, n3793, n3794, n3795,
n3796, n3797, n3798, n3799, n3800, n3801, n3802, n3803, n3804, n3805,
n3806, n3807, n3808, n3809, n3810, n3811, n3812, n3813, n3814, n3815,
n3816, n3817, n3818, n3819, n3820, n3821, n3822, n3823, n3824, n3825,
n3826, n3827, n3828, n3829, n3830, n3831, n3832, n3833, n3834, n3835,
n3836, n3837, n3838, n3839, n3840, n3841, n3842, n3843, n3844, n3845,
n3846, n3847, n3848, n3849, n3850, n3851, n3852, n3853, n3854, n3855,
n3856, n3857, n3858, n3859, n3860, n3861, n3862, n3863, n3864, n3865,
n3866, n3867, n3868, n3869, n3870, n3871, n3872, n3873, n3874, n3875,
n3876, n3877, n3878, n3879, n3880, n3881, n3882, n3883, n3884, n3885,
n3886, n3887, n3888, n3889, n3890, n3891, n3892, n3893, n3894, n3895,
n3896, n3897, n3898, n3899, n3900, n3901, n3902, n3903, n3904, n3905,
n3906, n3907, n3908, n3909, n3910, n3911, n3912, n3913, n3914, n3915,
n3916, n3917, n3918, n3919, n3920, n3921, n3922, n3923, n3924, n3925,
n3926, n3927, n3928, n3929, n3930, n3931, n3932, n3933, n3934, n3935,
n3936, n3937, n3938, n3939, n3940, n3941, n3942, n3943, n3944, n3945,
n3946, n3947, n3948, n3949, n3950, n3951, n3952, n3953, n3954, n3955,
n3956, n3957, n3958, n3959, n3960, n3961, n3962, n3963, n3964, n3965,
n3966, n3967, n3968, n3969, n3970, n3971, n3972, n3973, n3974, n3975,
n3976, n3977, n3978, n3979, n3980, n3981, n3982, n3983, n3984, n3985,
n3986, n3987, n3988, n3989, n3990, n3991, n3992, n3993, n3994, n3995,
n3996, n3997, n3998, n3999, n4000, n4001, n4002, n4003, n4004, n4005,
n4006, n4007, n4008, n4009, n4010, n4011, n4012, n4013, n4014, n4015,
n4016, n4017, n4018, n4019, n4020, n4021, n4022, n4023, n4024, n4025,
n4026, n4027, n4028, n4029, n4030, n4031, n4032, n4033, n4034, n4035,
n4036, n4037, n4038, n4039, n4040, n4041, n4042, n4043, n4044, n4045,
n4046, n4047, n4048, n4049, n4050, n4051, n4052, n4053, n4054, n4055,
n4056, n4057, n4058, n4059, n4060, n4061, n4062, n4063, n4064, n4065,
n4066, n4067, n4068, n4069, n4070, n4071, n4072, n4073, n4074, n4075,
n4076, n4077, n4078, n4079, n4080, n4081, n4082, n4083, n4084, n4085,
n4086, n4087, n4088, n4089, n4090, n4091, n4092, n4093, n4094, n4095,
n4096, n4097, n4098, n4099, n4100, n4101, n4102, n4103, n4104, n4105,
n4106, n4107, n4108, n4109, n4110, n4111, n4112, n4113, n4114, n4115,
n4116, n4117, n4118, n4119, n4120, n4121, n4122, n4123, n4124, n4125,
n4126, n4127, n4128, n4129, n4130, n4131, n4132, n4133, n4134, n4135,
n4136, n4137, n4138, n4139, n4140, n4141, n4142, n4143, n4144, n4145,
n4146, n4147, n4148, n4149, n4150, n4151, n4152, n4153, n4154, n4155,
n4156, n4157, n4158, n4159, n4160, n4161, n4162, n4163, n4164, n4165,
n4166, n4167, n4168, n4169, n4170, n4171, n4172, n4173, n4174, n4175,
n4176, n4177, n4178, n4179, n4180, n4181, n4182, n4183, n4184, n4185,
n4186, n4187, n4188, n4189, n4190, n4191, n4192, n4193, n4194, n4195,
n4196, n4197, n4198, n4199, n4200, n4201, n4202, n4203, n4204, n4205,
n4206, n4207, n4208, n4209, n4210, n4211, n4212, n4213, n4214, n4215,
n4216, n4217, n4218, n4219, n4220, n4221, n4222, n4223, n4224, n4225,
n4226, n4227, n4228, n4229, n4230, n4231, n4232, n4233, n4234, n4235,
n4236, n4237, n4238, n4239, n4240, n4241, n4242, n4243, n4244, n4245,
n4246, n4247, n4248, n4249, n4250, n4251, n4252, n4253, n4254, n4255,
n4256, n4257, n4258, n4259, n4260, n4261, n4262, n4263, n4264, n4265,
n4266, n4267, n4268, n4269, n4270, n4271, n4272, n4273, n4274, n4275,
n4276, n4277, n4278, n4279, n4280, n4281, n4282, n4283, n4284, n4285,
n4286, n4287, n4288, n4289, n4290, n4291, n4292, n4293, n4294, n4295,
n4296, n4297, n4298, n4299, n4300, n4301, n4302, n4303, n4304, n4305,
n4306, n4307, n4308, n4309, n4310, n4311, n4312, n4313, n4314, n4315,
n4316, n4317, n4318, n4319, n4320, n4321, n4322, n4323, n4324, n4325,
n4326, n4327, n4328, n4329, n4330, n4331, n4332, n4333, n4334, n4335,
n4336, n4337, n4338, n4339, n4340, n4341, n4342, n4343, n4344, n4345,
n4346, n4347, n4348, n4349, n4350, n4351, n4352, n4353, n4354, n4355,
n4356, n4357, n4358, n4359, n4360, n4361, n4362, n4363, n4364, n4365,
n4366, n4367, n4368, n4369, n4370, n4371, n4372, n4373, n4374, n4375,
n4376, n4377, n4378, n4379, n4380, n4381, n4382, n4383, n4384, n4385,
n4386, n4387, n4388, n4389, n4390, n4391, n4392, n4393, n4394, n4395,
n4396, n4397, n4398, n4399, n4400, n4401, n4402, n4403, n4404, n4405,
n4406, n4407, n4408, n4409, n4410, n4411, n4412, n4413, n4414, n4415,
n4416, n4417, n4418, n4419, n4420, n4421, n4422, n4423, n4424, n4425,
n4426, n4427, n4428, n4429, n4430, n4431, n4432, n4433, n4434, n4435,
n4436, n4437, n4438, n4439, n4440, n4441, n4442, n4443, n4444, n4445,
n4446, n4447, n4448, n4449, n4450, n4451, n4452, n4453, n4454, n4455,
n4456, n4457, n4458, n4459, n4460, n4461, n4462, n4463, n4464, n4465,
n4466, n4467, n4468, n4469, n4470, n4471, n4472, n4473, n4474, n4475,
n4476, n4477, n4478, n4479, n4480, n4481, n4482, n4483, n4484, n4485,
n4486, n4487, n4488, n4489, n4490, n4491, n4492, n4493, n4494, n4495,
n4496, n4497, n4498, n4499, n4500, n4501, n4502, n4503, n4504, n4505,
n4506, n4507, n4508, n4509, n4510, n4511, n4512, n4513, n4514, n4515,
n4516, n4517, n4518, n4519, n4520, n4521, n4522, n4523, n4524, n4525,
n4526, n4527, n4528, n4529, n4530, n4531, n4532, n4533, n4534, n4535,
n4536, n4537, n4538, n4539, n4540, n4541, n4542, n4543, n4544, n4545,
n4546, n4547, n4548, n4549, n4550, n4551, n4552, n4553, n4554, n4555,
n4556, n4557, n4558, n4559, n4560, n4561, n4562, n4563, n4564, n4565,
n4566, n4567, n4568, n4569, n4570, n4571, n4572, n4573, n4574, n4575,
n4576, n4577, n4578, n4579, n4580, n4581, n4582, n4583, n4584, n4585,
n4586, n4587, n4588, n4589, n4590, n4591, n4592, n4593, n4594, n4595,
n4596, n4597, n4598, n4599, n4600, n4601, n4602, n4603, n4604, n4605,
n4606, n4607, n4608, n4609, n4610, n4611, n4612, n4613, n4614, n4615,
n4616, n4617, n4618, n4619, n4620, n4621, n4622, n4623, n4624, n4625,
n4626, n4627, n4628, n4629, n4630, n4631, n4632, n4633, n4634, n4635,
n4636, n4637, n4638, n4639, n4640, n4641, n4642, n4643, n4644, n4645,
n4646, n4647, n4648, n4649, n4650, n4651, n4652, n4653, n4654, n4655,
n4656, n4657, n4658, n4659, n4660, n4661, n4662, n4663, n4664, n4665,
n4666, n4667, n4668, n4669, n4670, n4671, n4672, n4673, n4674, n4675,
n4676, n4677, n4678, n4679, n4680, n4681, n4682, n4683, n4684, n4685,
n4686, n4687, n4688, n4689, n4690, n4691, n4692, n4693, n4694, n4695,
n4696, n4697, n4698, n4699, n4700, n4701, n4702, n4703, n4704, n4705,
n4706, n4707, n4708, n4709, n4710, n4711, n4712, n4713, n4714, n4715,
n4716, n4717, n4718, n4719, n4720, n4721, n4722, n4723, n4724, n4725,
n4726, n4727, n4728, n4729, n4730, n4731, n4732, n4733, n4734, n4735,
n4736, n4737, n4738, n4739, n4740, n4741, n4742, n4743, n4744, n4745,
n4746, n4747, n4748, n4749, n4750, n4751, n4752, n4753, n4754;
wire [3:0] Shift_reg_FLAGS_7;
wire [63:0] intDX_EWSW;
wire [63:0] intDY_EWSW;
wire [62:0] DMP_EXP_EWSW;
wire [57:0] DmP_EXP_EWSW;
wire [62:0] DMP_SHT1_EWSW;
wire [51:0] DmP_mant_SHT1_SW;
wire [5:0] Shift_amount_SHT1_EWR;
wire [54:0] Raw_mant_NRM_SWR;
wire [53:0] Data_array_SWR;
wire [62:0] DMP_SHT2_EWSW;
wire [5:2] shift_value_SHT2_EWR;
wire [10:0] DMP_exp_NRM2_EW;
wire [10:0] DMP_exp_NRM_EW;
wire [5:0] LZD_output_NRM2_EW;
wire [62:0] DMP_SFG;
wire [54:0] DmP_mant_SFG_SWR;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS inst_ShiftRegister_Q_reg_6_ ( .D(n1890), .CK(clk), .RN(n4676), .Q(
Shift_reg_FLAGS_7_6), .QN(n4484) );
DFFRXLTS inst_ShiftRegister_Q_reg_2_ ( .D(n1886), .CK(clk), .RN(n4754), .Q(
Shift_reg_FLAGS_7[2]), .QN(n1901) );
DFFRXLTS inst_ShiftRegister_Q_reg_0_ ( .D(n1884), .CK(clk), .RN(n4754), .Q(
Shift_reg_FLAGS_7[0]) );
DFFRXLTS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n1819), .CK(clk), .RN(n4683), .Q(
intAS) );
DFFRXLTS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n1753), .CK(clk), .RN(n4744),
.Q(left_right_SHT2), .QN(n1903) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_43_ ( .D(n1741), .CK(clk), .RN(n4734), .Q(
Data_array_SWR[42]), .QN(n1945) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_42_ ( .D(n1740), .CK(clk), .RN(n4734), .Q(
Data_array_SWR[41]), .QN(n1947) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_39_ ( .D(n1737), .CK(clk), .RN(n4734), .Q(
Data_array_SWR[38]), .QN(n1943) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_34_ ( .D(n1732), .CK(clk), .RN(n4734), .QN(
n1909) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_5_ ( .D(n1687), .CK(clk), .RN(n4744),
.Q(Shift_amount_SHT1_EWR[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_0_ ( .D(n1675), .CK(clk), .RN(n4689), .Q(
DMP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_1_ ( .D(n1674), .CK(clk), .RN(n4689), .Q(
DMP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_2_ ( .D(n1673), .CK(clk), .RN(n4689), .Q(
DMP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_3_ ( .D(n1672), .CK(clk), .RN(n4690), .Q(
DMP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_4_ ( .D(n1671), .CK(clk), .RN(n4690), .Q(
DMP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_5_ ( .D(n1670), .CK(clk), .RN(n4690), .Q(
DMP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_6_ ( .D(n1669), .CK(clk), .RN(n4690), .Q(
DMP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_7_ ( .D(n1668), .CK(clk), .RN(n4690), .Q(
DMP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_8_ ( .D(n1667), .CK(clk), .RN(n4690), .Q(
DMP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_9_ ( .D(n1666), .CK(clk), .RN(n4690), .Q(
DMP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_10_ ( .D(n1665), .CK(clk), .RN(n4690), .Q(
DMP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_11_ ( .D(n1664), .CK(clk), .RN(n4690), .Q(
DMP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_12_ ( .D(n1663), .CK(clk), .RN(n4690), .Q(
DMP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_13_ ( .D(n1662), .CK(clk), .RN(n4691), .Q(
DMP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_14_ ( .D(n1661), .CK(clk), .RN(n4691), .Q(
DMP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_15_ ( .D(n1660), .CK(clk), .RN(n4691), .Q(
DMP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_16_ ( .D(n1659), .CK(clk), .RN(n4691), .Q(
DMP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_17_ ( .D(n1658), .CK(clk), .RN(n4691), .Q(
DMP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_18_ ( .D(n1657), .CK(clk), .RN(n4691), .Q(
DMP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_19_ ( .D(n1656), .CK(clk), .RN(n4691), .Q(
DMP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_20_ ( .D(n1655), .CK(clk), .RN(n4691), .Q(
DMP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_21_ ( .D(n1654), .CK(clk), .RN(n4691), .Q(
DMP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_22_ ( .D(n1653), .CK(clk), .RN(n4691), .Q(
DMP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_23_ ( .D(n1652), .CK(clk), .RN(n4692), .Q(
DMP_EXP_EWSW[23]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_24_ ( .D(n1651), .CK(clk), .RN(n4692), .Q(
DMP_EXP_EWSW[24]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_25_ ( .D(n1650), .CK(clk), .RN(n4692), .Q(
DMP_EXP_EWSW[25]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_26_ ( .D(n1649), .CK(clk), .RN(n4692), .Q(
DMP_EXP_EWSW[26]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_27_ ( .D(n1648), .CK(clk), .RN(n4692), .Q(
DMP_EXP_EWSW[27]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_28_ ( .D(n1647), .CK(clk), .RN(n4692), .Q(
DMP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_29_ ( .D(n1646), .CK(clk), .RN(n4692), .Q(
DMP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_30_ ( .D(n1645), .CK(clk), .RN(n4692), .Q(
DMP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_31_ ( .D(n1644), .CK(clk), .RN(n4692), .Q(
DMP_EXP_EWSW[31]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_32_ ( .D(n1643), .CK(clk), .RN(n4692), .Q(
DMP_EXP_EWSW[32]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_33_ ( .D(n1642), .CK(clk), .RN(n4693), .Q(
DMP_EXP_EWSW[33]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_34_ ( .D(n1641), .CK(clk), .RN(n4693), .Q(
DMP_EXP_EWSW[34]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_35_ ( .D(n1640), .CK(clk), .RN(n4693), .Q(
DMP_EXP_EWSW[35]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_36_ ( .D(n1639), .CK(clk), .RN(n4693), .Q(
DMP_EXP_EWSW[36]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_37_ ( .D(n1638), .CK(clk), .RN(n4693), .Q(
DMP_EXP_EWSW[37]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_38_ ( .D(n1637), .CK(clk), .RN(n4693), .Q(
DMP_EXP_EWSW[38]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_39_ ( .D(n1636), .CK(clk), .RN(n4693), .Q(
DMP_EXP_EWSW[39]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_40_ ( .D(n1635), .CK(clk), .RN(n4693), .Q(
DMP_EXP_EWSW[40]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_41_ ( .D(n1634), .CK(clk), .RN(n4693), .Q(
DMP_EXP_EWSW[41]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_42_ ( .D(n1633), .CK(clk), .RN(n4693), .Q(
DMP_EXP_EWSW[42]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_43_ ( .D(n1632), .CK(clk), .RN(n4694), .Q(
DMP_EXP_EWSW[43]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_44_ ( .D(n1631), .CK(clk), .RN(n4694), .Q(
DMP_EXP_EWSW[44]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_45_ ( .D(n1630), .CK(clk), .RN(n4694), .Q(
DMP_EXP_EWSW[45]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_46_ ( .D(n1629), .CK(clk), .RN(n4694), .Q(
DMP_EXP_EWSW[46]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_47_ ( .D(n1628), .CK(clk), .RN(n4694), .Q(
DMP_EXP_EWSW[47]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_48_ ( .D(n1627), .CK(clk), .RN(n4694), .Q(
DMP_EXP_EWSW[48]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_49_ ( .D(n1626), .CK(clk), .RN(n4694), .Q(
DMP_EXP_EWSW[49]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_50_ ( .D(n1625), .CK(clk), .RN(n4694), .Q(
DMP_EXP_EWSW[50]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_51_ ( .D(n1624), .CK(clk), .RN(n4694), .Q(
DMP_EXP_EWSW[51]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_52_ ( .D(n1623), .CK(clk), .RN(n4694), .Q(
DMP_EXP_EWSW[52]), .QN(n4606) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_58_ ( .D(n1617), .CK(clk), .RN(n4695), .Q(
DMP_EXP_EWSW[58]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_59_ ( .D(n1616), .CK(clk), .RN(n4695), .Q(
DMP_EXP_EWSW[59]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_60_ ( .D(n1615), .CK(clk), .RN(n4695), .Q(
DMP_EXP_EWSW[60]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_61_ ( .D(n1614), .CK(clk), .RN(n4695), .Q(
DMP_EXP_EWSW[61]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_62_ ( .D(n1613), .CK(clk), .RN(n4695), .Q(
DMP_EXP_EWSW[62]) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n1612), .CK(clk), .RN(n4696), .Q(
OP_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n1611), .CK(clk), .RN(n4696), .Q(
ZERO_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n1610), .CK(clk), .RN(n4696), .Q(
SIGN_FLAG_EXP) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n1609), .CK(clk), .RN(n4696), .Q(
DMP_SHT1_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n1606), .CK(clk), .RN(n4696), .Q(
DMP_SHT1_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n1603), .CK(clk), .RN(n4696), .Q(
DMP_SHT1_EWSW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n1600), .CK(clk), .RN(n4696), .Q(
DMP_SHT1_EWSW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n1597), .CK(clk), .RN(n4696), .Q(
DMP_SHT1_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n1594), .CK(clk), .RN(n4696), .Q(
DMP_SHT1_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n1591), .CK(clk), .RN(n4696), .Q(
DMP_SHT1_EWSW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n1588), .CK(clk), .RN(n4697), .Q(
DMP_SHT1_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n1585), .CK(clk), .RN(n4697), .Q(
DMP_SHT1_EWSW[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n1582), .CK(clk), .RN(n4697), .Q(
DMP_SHT1_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n1579), .CK(clk), .RN(n4697), .Q(
DMP_SHT1_EWSW[10]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n1576), .CK(clk), .RN(n4697), .Q(
DMP_SHT1_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n1573), .CK(clk), .RN(n4697), .Q(
DMP_SHT1_EWSW[12]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n1570), .CK(clk), .RN(n4697), .Q(
DMP_SHT1_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n1567), .CK(clk), .RN(n4697), .Q(
DMP_SHT1_EWSW[14]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n1564), .CK(clk), .RN(n4697), .Q(
DMP_SHT1_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n1561), .CK(clk), .RN(n4697), .Q(
DMP_SHT1_EWSW[16]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n1558), .CK(clk), .RN(n4698), .Q(
DMP_SHT1_EWSW[17]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n1555), .CK(clk), .RN(n4698), .Q(
DMP_SHT1_EWSW[18]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n1552), .CK(clk), .RN(n4698), .Q(
DMP_SHT1_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n1549), .CK(clk), .RN(n4698), .Q(
DMP_SHT1_EWSW[20]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n1546), .CK(clk), .RN(n4698), .Q(
DMP_SHT1_EWSW[21]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n1543), .CK(clk), .RN(n4698), .Q(
DMP_SHT1_EWSW[22]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n1540), .CK(clk), .RN(n4698), .Q(
DMP_SHT1_EWSW[23]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n1537), .CK(clk), .RN(n4698), .Q(
DMP_SHT1_EWSW[24]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n1534), .CK(clk), .RN(n4698), .Q(
DMP_SHT1_EWSW[25]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n1531), .CK(clk), .RN(n4698), .Q(
DMP_SHT1_EWSW[26]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n1528), .CK(clk), .RN(n4699), .Q(
DMP_SHT1_EWSW[27]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n1525), .CK(clk), .RN(n4699), .Q(
DMP_SHT1_EWSW[28]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n1522), .CK(clk), .RN(n4699), .Q(
DMP_SHT1_EWSW[29]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n1519), .CK(clk), .RN(n4699), .Q(
DMP_SHT1_EWSW[30]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_31_ ( .D(n1516), .CK(clk), .RN(n4699), .Q(
DMP_SHT1_EWSW[31]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_32_ ( .D(n1513), .CK(clk), .RN(n4699), .Q(
DMP_SHT1_EWSW[32]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_33_ ( .D(n1510), .CK(clk), .RN(n4699), .Q(
DMP_SHT1_EWSW[33]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_34_ ( .D(n1507), .CK(clk), .RN(n4699), .Q(
DMP_SHT1_EWSW[34]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_35_ ( .D(n1504), .CK(clk), .RN(n4699), .Q(
DMP_SHT1_EWSW[35]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_36_ ( .D(n1501), .CK(clk), .RN(n4699), .Q(
DMP_SHT1_EWSW[36]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_37_ ( .D(n1498), .CK(clk), .RN(n4700), .Q(
DMP_SHT1_EWSW[37]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_37_ ( .D(n1497), .CK(clk), .RN(n4700), .Q(
DMP_SHT2_EWSW[37]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_38_ ( .D(n1495), .CK(clk), .RN(n4700), .Q(
DMP_SHT1_EWSW[38]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_38_ ( .D(n1494), .CK(clk), .RN(n4700), .Q(
DMP_SHT2_EWSW[38]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_39_ ( .D(n1492), .CK(clk), .RN(n4700), .Q(
DMP_SHT1_EWSW[39]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_39_ ( .D(n1491), .CK(clk), .RN(n4700), .Q(
DMP_SHT2_EWSW[39]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_40_ ( .D(n1489), .CK(clk), .RN(n4700), .Q(
DMP_SHT1_EWSW[40]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_40_ ( .D(n1488), .CK(clk), .RN(n4700), .Q(
DMP_SHT2_EWSW[40]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_41_ ( .D(n1486), .CK(clk), .RN(n4700), .Q(
DMP_SHT1_EWSW[41]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_41_ ( .D(n1485), .CK(clk), .RN(n4700), .Q(
DMP_SHT2_EWSW[41]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_42_ ( .D(n1483), .CK(clk), .RN(n4701), .Q(
DMP_SHT1_EWSW[42]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_42_ ( .D(n1482), .CK(clk), .RN(n4701), .Q(
DMP_SHT2_EWSW[42]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_43_ ( .D(n1480), .CK(clk), .RN(n4701), .Q(
DMP_SHT1_EWSW[43]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_43_ ( .D(n1479), .CK(clk), .RN(n4701), .Q(
DMP_SHT2_EWSW[43]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_44_ ( .D(n1477), .CK(clk), .RN(n4701), .Q(
DMP_SHT1_EWSW[44]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_44_ ( .D(n1476), .CK(clk), .RN(n4701), .Q(
DMP_SHT2_EWSW[44]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_45_ ( .D(n1474), .CK(clk), .RN(n4701), .Q(
DMP_SHT1_EWSW[45]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_45_ ( .D(n1473), .CK(clk), .RN(n4701), .Q(
DMP_SHT2_EWSW[45]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_46_ ( .D(n1471), .CK(clk), .RN(n4701), .Q(
DMP_SHT1_EWSW[46]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_46_ ( .D(n1470), .CK(clk), .RN(n4701), .Q(
DMP_SHT2_EWSW[46]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_47_ ( .D(n1468), .CK(clk), .RN(n4702), .Q(
DMP_SHT1_EWSW[47]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_47_ ( .D(n1467), .CK(clk), .RN(n4702), .Q(
DMP_SHT2_EWSW[47]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_48_ ( .D(n1465), .CK(clk), .RN(n4702), .Q(
DMP_SHT1_EWSW[48]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_48_ ( .D(n1464), .CK(clk), .RN(n4702), .Q(
DMP_SHT2_EWSW[48]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_49_ ( .D(n1462), .CK(clk), .RN(n4702), .Q(
DMP_SHT1_EWSW[49]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_49_ ( .D(n1461), .CK(clk), .RN(n4702), .Q(
DMP_SHT2_EWSW[49]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_50_ ( .D(n1459), .CK(clk), .RN(n4702), .Q(
DMP_SHT1_EWSW[50]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_50_ ( .D(n1458), .CK(clk), .RN(n4702), .Q(
DMP_SHT2_EWSW[50]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_51_ ( .D(n1456), .CK(clk), .RN(n4702), .Q(
DMP_SHT1_EWSW[51]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_51_ ( .D(n1455), .CK(clk), .RN(n4702), .Q(
DMP_SHT2_EWSW[51]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_52_ ( .D(n1453), .CK(clk), .RN(n4703), .Q(
DMP_SHT1_EWSW[52]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_52_ ( .D(n1452), .CK(clk), .RN(n4703), .Q(
DMP_SHT2_EWSW[52]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_52_ ( .D(n1451), .CK(clk), .RN(n4703), .Q(
DMP_SFG[52]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n1449), .CK(clk), .RN(n4725), .Q(
DMP_exp_NRM2_EW[0]), .QN(n1939) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_53_ ( .D(n1448), .CK(clk), .RN(n4703), .Q(
DMP_SHT1_EWSW[53]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_53_ ( .D(n1447), .CK(clk), .RN(n4703), .Q(
DMP_SHT2_EWSW[53]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_53_ ( .D(n1446), .CK(clk), .RN(n4703), .Q(
DMP_SFG[53]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n1445), .CK(clk), .RN(n4703), .Q(
DMP_exp_NRM_EW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_54_ ( .D(n1443), .CK(clk), .RN(n4703), .Q(
DMP_SHT1_EWSW[54]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_54_ ( .D(n1442), .CK(clk), .RN(n4703), .Q(
DMP_SHT2_EWSW[54]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_54_ ( .D(n1441), .CK(clk), .RN(n4703), .Q(
DMP_SFG[54]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n1440), .CK(clk), .RN(n4704), .Q(
DMP_exp_NRM_EW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_55_ ( .D(n1438), .CK(clk), .RN(n4704), .Q(
DMP_SHT1_EWSW[55]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_55_ ( .D(n1437), .CK(clk), .RN(n4704), .Q(
DMP_SHT2_EWSW[55]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_55_ ( .D(n1436), .CK(clk), .RN(n4704), .Q(
DMP_SFG[55]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n1435), .CK(clk), .RN(n4704), .Q(
DMP_exp_NRM_EW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_56_ ( .D(n1433), .CK(clk), .RN(n4704), .Q(
DMP_SHT1_EWSW[56]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_56_ ( .D(n1432), .CK(clk), .RN(n4704), .Q(
DMP_SHT2_EWSW[56]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_56_ ( .D(n1431), .CK(clk), .RN(n4704), .Q(
DMP_SFG[56]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n1430), .CK(clk), .RN(n4704), .Q(
DMP_exp_NRM_EW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_57_ ( .D(n1428), .CK(clk), .RN(n4704), .Q(
DMP_SHT1_EWSW[57]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_57_ ( .D(n1427), .CK(clk), .RN(n4705), .Q(
DMP_SHT2_EWSW[57]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_57_ ( .D(n1426), .CK(clk), .RN(n4705), .Q(
DMP_SFG[57]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n1425), .CK(clk), .RN(n4705), .Q(
DMP_exp_NRM_EW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_58_ ( .D(n1423), .CK(clk), .RN(n4705), .Q(
DMP_SHT1_EWSW[58]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_58_ ( .D(n1422), .CK(clk), .RN(n4705), .Q(
DMP_SHT2_EWSW[58]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_58_ ( .D(n1421), .CK(clk), .RN(n4705), .Q(
DMP_SFG[58]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n1420), .CK(clk), .RN(n4705), .Q(
DMP_exp_NRM_EW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_59_ ( .D(n1418), .CK(clk), .RN(n4705), .Q(
DMP_SHT1_EWSW[59]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_59_ ( .D(n1417), .CK(clk), .RN(n4705), .Q(
DMP_SHT2_EWSW[59]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_59_ ( .D(n1416), .CK(clk), .RN(n4705), .Q(
DMP_SFG[59]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n1415), .CK(clk), .RN(n4706), .Q(
DMP_exp_NRM_EW[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_60_ ( .D(n1413), .CK(clk), .RN(n4706), .Q(
DMP_SHT1_EWSW[60]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_60_ ( .D(n1412), .CK(clk), .RN(n4706), .Q(
DMP_SHT2_EWSW[60]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_60_ ( .D(n1411), .CK(clk), .RN(n4706), .Q(
DMP_SFG[60]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_8_ ( .D(n1410), .CK(clk), .RN(n4706), .Q(
DMP_exp_NRM_EW[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_61_ ( .D(n1408), .CK(clk), .RN(n4706), .Q(
DMP_SHT1_EWSW[61]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_61_ ( .D(n1407), .CK(clk), .RN(n4706), .Q(
DMP_SHT2_EWSW[61]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_61_ ( .D(n1406), .CK(clk), .RN(n4706), .Q(
DMP_SFG[61]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_9_ ( .D(n1405), .CK(clk), .RN(n4706), .Q(
DMP_exp_NRM_EW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_62_ ( .D(n1403), .CK(clk), .RN(n4706), .Q(
DMP_SHT1_EWSW[62]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_62_ ( .D(n1402), .CK(clk), .RN(n4707), .Q(
DMP_SHT2_EWSW[62]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_62_ ( .D(n1401), .CK(clk), .RN(n4707), .Q(
DMP_SFG[62]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_10_ ( .D(n1400), .CK(clk), .RN(n4707), .Q(
DMP_exp_NRM_EW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_0_ ( .D(n1398), .CK(clk), .RN(n4707), .Q(
DmP_EXP_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n1397), .CK(clk), .RN(n4707), .Q(
DmP_mant_SHT1_SW[0]), .QN(n4665) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_1_ ( .D(n1396), .CK(clk), .RN(n4707), .Q(
DmP_EXP_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n1395), .CK(clk), .RN(n4707), .Q(
DmP_mant_SHT1_SW[1]), .QN(n4664) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_2_ ( .D(n1394), .CK(clk), .RN(n4707), .Q(
DmP_EXP_EWSW[2]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n1393), .CK(clk), .RN(n4707), .Q(
DmP_mant_SHT1_SW[2]), .QN(n4663) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_3_ ( .D(n1392), .CK(clk), .RN(n4707), .Q(
DmP_EXP_EWSW[3]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n1391), .CK(clk), .RN(n4708), .Q(
DmP_mant_SHT1_SW[3]), .QN(n4662) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_4_ ( .D(n1390), .CK(clk), .RN(n4708), .Q(
DmP_EXP_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n1389), .CK(clk), .RN(n4708), .Q(
DmP_mant_SHT1_SW[4]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_5_ ( .D(n1388), .CK(clk), .RN(n4708), .Q(
DmP_EXP_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n1387), .CK(clk), .RN(n4708), .Q(
DmP_mant_SHT1_SW[5]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_6_ ( .D(n1386), .CK(clk), .RN(n4708), .Q(
DmP_EXP_EWSW[6]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n1385), .CK(clk), .RN(n4708), .Q(
DmP_mant_SHT1_SW[6]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_7_ ( .D(n1384), .CK(clk), .RN(n4708), .Q(
DmP_EXP_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n1383), .CK(clk), .RN(n4708), .Q(
DmP_mant_SHT1_SW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_8_ ( .D(n1382), .CK(clk), .RN(n4708), .Q(
DmP_EXP_EWSW[8]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n1381), .CK(clk), .RN(n4709), .Q(
DmP_mant_SHT1_SW[8]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_9_ ( .D(n1380), .CK(clk), .RN(n4709), .Q(
DmP_EXP_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n1379), .CK(clk), .RN(n4709), .Q(
DmP_mant_SHT1_SW[9]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_10_ ( .D(n1378), .CK(clk), .RN(n4709), .Q(
DmP_EXP_EWSW[10]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n1377), .CK(clk), .RN(n4709),
.Q(DmP_mant_SHT1_SW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_11_ ( .D(n1376), .CK(clk), .RN(n4709), .Q(
DmP_EXP_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n1375), .CK(clk), .RN(n4709),
.Q(DmP_mant_SHT1_SW[11]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_12_ ( .D(n1374), .CK(clk), .RN(n4709), .Q(
DmP_EXP_EWSW[12]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n1373), .CK(clk), .RN(n4709),
.Q(DmP_mant_SHT1_SW[12]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_13_ ( .D(n1372), .CK(clk), .RN(n4709), .Q(
DmP_EXP_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n1371), .CK(clk), .RN(n4710),
.Q(DmP_mant_SHT1_SW[13]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_14_ ( .D(n1370), .CK(clk), .RN(n4710), .Q(
DmP_EXP_EWSW[14]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n1369), .CK(clk), .RN(n4710),
.Q(DmP_mant_SHT1_SW[14]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_15_ ( .D(n1368), .CK(clk), .RN(n4710), .Q(
DmP_EXP_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n1367), .CK(clk), .RN(n4710),
.Q(DmP_mant_SHT1_SW[15]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_16_ ( .D(n1366), .CK(clk), .RN(n4710), .Q(
DmP_EXP_EWSW[16]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n1365), .CK(clk), .RN(n4710),
.Q(DmP_mant_SHT1_SW[16]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_17_ ( .D(n1364), .CK(clk), .RN(n4710), .Q(
DmP_EXP_EWSW[17]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n1363), .CK(clk), .RN(n4710),
.Q(DmP_mant_SHT1_SW[17]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_18_ ( .D(n1362), .CK(clk), .RN(n4710), .Q(
DmP_EXP_EWSW[18]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n1361), .CK(clk), .RN(n4711),
.Q(DmP_mant_SHT1_SW[18]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_19_ ( .D(n1360), .CK(clk), .RN(n4711), .Q(
DmP_EXP_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n1359), .CK(clk), .RN(n4711),
.Q(DmP_mant_SHT1_SW[19]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_20_ ( .D(n1358), .CK(clk), .RN(n4711), .Q(
DmP_EXP_EWSW[20]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n1357), .CK(clk), .RN(n4711),
.Q(DmP_mant_SHT1_SW[20]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_21_ ( .D(n1356), .CK(clk), .RN(n4711), .Q(
DmP_EXP_EWSW[21]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n1355), .CK(clk), .RN(n4711),
.Q(DmP_mant_SHT1_SW[21]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_26_ ( .D(n1346), .CK(clk), .RN(n4712), .Q(
DmP_EXP_EWSW[26]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_26_ ( .D(n1345), .CK(clk), .RN(n4712),
.Q(DmP_mant_SHT1_SW[26]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_27_ ( .D(n1344), .CK(clk), .RN(n4712), .Q(
DmP_EXP_EWSW[27]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_27_ ( .D(n1343), .CK(clk), .RN(n4712),
.Q(DmP_mant_SHT1_SW[27]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_28_ ( .D(n1342), .CK(clk), .RN(n4712), .Q(
DmP_EXP_EWSW[28]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_28_ ( .D(n1341), .CK(clk), .RN(n4712),
.Q(DmP_mant_SHT1_SW[28]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_29_ ( .D(n1340), .CK(clk), .RN(n4712), .Q(
DmP_EXP_EWSW[29]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_29_ ( .D(n1339), .CK(clk), .RN(n4712),
.Q(DmP_mant_SHT1_SW[29]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_30_ ( .D(n1338), .CK(clk), .RN(n4712), .Q(
DmP_EXP_EWSW[30]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_30_ ( .D(n1337), .CK(clk), .RN(n4713),
.Q(DmP_mant_SHT1_SW[30]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_31_ ( .D(n1336), .CK(clk), .RN(n4713), .Q(
DmP_EXP_EWSW[31]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_31_ ( .D(n1335), .CK(clk), .RN(n4713),
.Q(DmP_mant_SHT1_SW[31]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_32_ ( .D(n1334), .CK(clk), .RN(n4713), .Q(
DmP_EXP_EWSW[32]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_32_ ( .D(n1333), .CK(clk), .RN(n4713),
.Q(DmP_mant_SHT1_SW[32]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_33_ ( .D(n1332), .CK(clk), .RN(n4713), .Q(
DmP_EXP_EWSW[33]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_33_ ( .D(n1331), .CK(clk), .RN(n4713),
.Q(DmP_mant_SHT1_SW[33]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_34_ ( .D(n1330), .CK(clk), .RN(n4713), .Q(
DmP_EXP_EWSW[34]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_34_ ( .D(n1329), .CK(clk), .RN(n4713),
.Q(DmP_mant_SHT1_SW[34]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_35_ ( .D(n1328), .CK(clk), .RN(n4713), .Q(
DmP_EXP_EWSW[35]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_35_ ( .D(n1327), .CK(clk), .RN(n4714),
.Q(DmP_mant_SHT1_SW[35]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_36_ ( .D(n1326), .CK(clk), .RN(n4714), .Q(
DmP_EXP_EWSW[36]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_36_ ( .D(n1325), .CK(clk), .RN(n4714),
.Q(DmP_mant_SHT1_SW[36]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_37_ ( .D(n1324), .CK(clk), .RN(n4714), .Q(
DmP_EXP_EWSW[37]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_37_ ( .D(n1323), .CK(clk), .RN(n4714),
.Q(DmP_mant_SHT1_SW[37]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_38_ ( .D(n1322), .CK(clk), .RN(n4714), .Q(
DmP_EXP_EWSW[38]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_38_ ( .D(n1321), .CK(clk), .RN(n4714),
.Q(DmP_mant_SHT1_SW[38]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_39_ ( .D(n1320), .CK(clk), .RN(n4714), .Q(
DmP_EXP_EWSW[39]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_39_ ( .D(n1319), .CK(clk), .RN(n4714),
.Q(DmP_mant_SHT1_SW[39]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_40_ ( .D(n1318), .CK(clk), .RN(n4714), .Q(
DmP_EXP_EWSW[40]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_40_ ( .D(n1317), .CK(clk), .RN(n4715),
.Q(DmP_mant_SHT1_SW[40]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_41_ ( .D(n1316), .CK(clk), .RN(n4715), .Q(
DmP_EXP_EWSW[41]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_41_ ( .D(n1315), .CK(clk), .RN(n4715),
.Q(DmP_mant_SHT1_SW[41]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_42_ ( .D(n1314), .CK(clk), .RN(n4715), .Q(
DmP_EXP_EWSW[42]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_42_ ( .D(n1313), .CK(clk), .RN(n4715),
.Q(DmP_mant_SHT1_SW[42]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_43_ ( .D(n1312), .CK(clk), .RN(n4715), .Q(
DmP_EXP_EWSW[43]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_43_ ( .D(n1311), .CK(clk), .RN(n4715),
.Q(DmP_mant_SHT1_SW[43]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_44_ ( .D(n1310), .CK(clk), .RN(n4715), .Q(
DmP_EXP_EWSW[44]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_44_ ( .D(n1309), .CK(clk), .RN(n4715),
.Q(DmP_mant_SHT1_SW[44]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_45_ ( .D(n1308), .CK(clk), .RN(n4715), .Q(
DmP_EXP_EWSW[45]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_45_ ( .D(n1307), .CK(clk), .RN(n4716),
.Q(DmP_mant_SHT1_SW[45]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_46_ ( .D(n1306), .CK(clk), .RN(n4716), .Q(
DmP_EXP_EWSW[46]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_46_ ( .D(n1305), .CK(clk), .RN(n4716),
.Q(DmP_mant_SHT1_SW[46]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_47_ ( .D(n1304), .CK(clk), .RN(n4716), .Q(
DmP_EXP_EWSW[47]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_47_ ( .D(n1303), .CK(clk), .RN(n4716),
.Q(DmP_mant_SHT1_SW[47]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_48_ ( .D(n1302), .CK(clk), .RN(n4716), .Q(
DmP_EXP_EWSW[48]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_48_ ( .D(n1301), .CK(clk), .RN(n4716),
.Q(DmP_mant_SHT1_SW[48]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_49_ ( .D(n1300), .CK(clk), .RN(n4716), .Q(
DmP_EXP_EWSW[49]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_49_ ( .D(n1299), .CK(clk), .RN(n4716),
.Q(DmP_mant_SHT1_SW[49]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_53_ ( .D(n1293), .CK(clk), .RN(n4717), .Q(
DmP_EXP_EWSW[53]), .QN(n4486) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n1286), .CK(clk), .RN(n4717), .Q(
ZERO_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n1285), .CK(clk), .RN(n4717), .Q(
ZERO_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n1284), .CK(clk), .RN(n4717), .Q(
ZERO_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n1283), .CK(clk), .RN(n4718), .Q(
ZERO_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n1282), .CK(clk), .RN(n4718),
.Q(ZERO_FLAG_SHT1SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n1280), .CK(clk), .RN(n4718), .Q(
OP_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n1279), .CK(clk), .RN(n4718), .Q(
OP_FLAG_SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n1275), .CK(clk), .RN(n4718), .Q(
SIGN_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n1274), .CK(clk), .RN(n4718), .Q(
SIGN_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n1273), .CK(clk), .RN(n4718), .Q(
SIGN_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n1272), .CK(clk), .RN(n4718), .Q(
SIGN_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1271), .CK(clk), .RN(n4718),
.Q(SIGN_FLAG_SHT1SHT2) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n1254), .CK(clk), .RN(n4740), .Q(
Raw_mant_NRM_SWR[15]), .QN(n4521) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n1253), .CK(clk), .RN(n4740), .Q(
Raw_mant_NRM_SWR[16]), .QN(n4615) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n1252), .CK(clk), .RN(n4741), .Q(
Raw_mant_NRM_SWR[17]), .QN(n4588) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n1251), .CK(clk), .RN(n4741), .Q(
Raw_mant_NRM_SWR[18]), .QN(n4591) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n1249), .CK(clk), .RN(n4741), .Q(
Raw_mant_NRM_SWR[20]), .QN(n1994) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n1247), .CK(clk), .RN(n4741), .Q(
Raw_mant_NRM_SWR[22]), .QN(n4577) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n1246), .CK(clk), .RN(n4740), .Q(
Raw_mant_NRM_SWR[23]), .QN(n4667) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n1244), .CK(clk), .RN(n4741), .Q(
Raw_mant_NRM_SWR[25]), .QN(n4585) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_28_ ( .D(n1241), .CK(clk), .RN(n4741), .Q(
Raw_mant_NRM_SWR[28]), .QN(n4611) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_29_ ( .D(n1240), .CK(clk), .RN(n4742), .Q(
Raw_mant_NRM_SWR[29]), .QN(n4593) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_30_ ( .D(n1239), .CK(clk), .RN(n4741), .Q(
Raw_mant_NRM_SWR[30]), .QN(n4666) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_36_ ( .D(n1233), .CK(clk), .RN(n4742), .Q(
Raw_mant_NRM_SWR[36]) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_37_ ( .D(n1232), .CK(clk), .RN(n4743), .Q(
Raw_mant_NRM_SWR[37]), .QN(n4669) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_38_ ( .D(n1231), .CK(clk), .RN(n4743), .Q(
Raw_mant_NRM_SWR[38]), .QN(n4616) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_39_ ( .D(n1230), .CK(clk), .RN(n4743), .Q(
Raw_mant_NRM_SWR[39]), .QN(n4592) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_40_ ( .D(n1229), .CK(clk), .RN(n4743), .Q(
Raw_mant_NRM_SWR[40]) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_42_ ( .D(n1227), .CK(clk), .RN(n4742), .Q(
Raw_mant_NRM_SWR[42]), .QN(n4672) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_43_ ( .D(n1226), .CK(clk), .RN(n4742), .Q(
Raw_mant_NRM_SWR[43]), .QN(n4589) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_44_ ( .D(n1225), .CK(clk), .RN(n4742), .Q(
Raw_mant_NRM_SWR[44]), .QN(n4590) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_45_ ( .D(n1224), .CK(clk), .RN(n4742), .Q(
Raw_mant_NRM_SWR[45]), .QN(n4673) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_47_ ( .D(n1222), .CK(clk), .RN(n4742), .Q(
Raw_mant_NRM_SWR[47]), .QN(n1993) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_14_ ( .D(n1213), .CK(clk), .RN(n2706),
.Q(LZD_output_NRM2_EW[3]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_15_ ( .D(n1211), .CK(clk), .RN(n4725),
.Q(LZD_output_NRM2_EW[4]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_16_ ( .D(n1209), .CK(clk), .RN(n4725),
.Q(LZD_output_NRM2_EW[5]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n1156), .CK(clk), .RN(n4736), .Q(
DmP_mant_SFG_SWR[0]), .QN(n4668) );
DFFRX1TS inst_ShiftRegister_Q_reg_4_ ( .D(n1888), .CK(clk), .RN(n4753), .Q(
n1910), .QN(n4674) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n1261), .CK(clk), .RN(n4740), .Q(
Raw_mant_NRM_SWR[8]), .QN(n4660) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_54_ ( .D(n1102), .CK(clk), .RN(n4726), .Q(
DmP_mant_SFG_SWR[54]), .QN(n4659) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_52_ ( .D(n1104), .CK(clk), .RN(n4734), .Q(
DmP_mant_SFG_SWR[52]), .QN(n4657) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n1154), .CK(clk), .RN(n4727), .Q(
DmP_mant_SFG_SWR[2]), .QN(n4656) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n1141), .CK(clk), .RN(n4728), .Q(
DmP_mant_SFG_SWR[15]), .QN(n4654) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_29_ ( .D(n1127), .CK(clk), .RN(n4729), .Q(
DmP_mant_SFG_SWR[29]), .QN(n4646) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_31_ ( .D(n1125), .CK(clk), .RN(n4730), .Q(
DmP_mant_SFG_SWR[31]), .QN(n4645) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_43_ ( .D(n1113), .CK(clk), .RN(n4731), .Q(
DmP_mant_SFG_SWR[43]), .QN(n4643) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_44_ ( .D(n1112), .CK(clk), .RN(n4731), .Q(
DmP_mant_SFG_SWR[44]), .QN(n4642) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_51_ ( .D(n1105), .CK(clk), .RN(n4733), .Q(
DmP_mant_SFG_SWR[51]), .QN(n4639) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n1144), .CK(clk), .RN(n4728), .Q(
DmP_mant_SFG_SWR[12]), .QN(n4638) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n1142), .CK(clk), .RN(n4728), .Q(
DmP_mant_SFG_SWR[14]), .QN(n4637) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n1146), .CK(clk), .RN(n4727), .Q(
DmP_mant_SFG_SWR[10]), .QN(n4635) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_26_ ( .D(n1130), .CK(clk), .RN(n4729), .Q(
DmP_mant_SFG_SWR[26]), .QN(n4633) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_28_ ( .D(n1128), .CK(clk), .RN(n4729), .Q(
DmP_mant_SFG_SWR[28]), .QN(n4632) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n1256), .CK(clk), .RN(n4739), .Q(
Raw_mant_NRM_SWR[13]), .QN(n4628) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n1260), .CK(clk), .RN(n4740), .Q(
Raw_mant_NRM_SWR[9]), .QN(n4626) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n1259), .CK(clk), .RN(n4740), .Q(
Raw_mant_NRM_SWR[10]), .QN(n4625) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_53_ ( .D(n1103), .CK(clk), .RN(n4736), .Q(
DmP_mant_SFG_SWR[53]), .QN(n4624) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_50_ ( .D(n1106), .CK(clk), .RN(n4733), .Q(
DmP_mant_SFG_SWR[50]), .QN(n4623) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n1267), .CK(clk), .RN(n4737), .Q(
Raw_mant_NRM_SWR[2]), .QN(n4620) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n1264), .CK(clk), .RN(n4739), .Q(
Raw_mant_NRM_SWR[5]), .QN(n4619) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n1265), .CK(clk), .RN(n4739), .Q(
Raw_mant_NRM_SWR[4]), .QN(n4617) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_48_ ( .D(n1108), .CK(clk), .RN(n4732), .Q(
DmP_mant_SFG_SWR[48]), .QN(n4614) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_49_ ( .D(n1107), .CK(clk), .RN(n4732), .Q(
DmP_mant_SFG_SWR[49]), .QN(n4613) );
DFFRX1TS SHT2_STAGE_SHFTVARS2_Q_reg_0_ ( .D(n1754), .CK(clk), .RN(n4689),
.Q(bit_shift_SHT2), .QN(n4612) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n1812), .CK(clk), .RN(n4683),
.Q(intDY_EWSW[6]), .QN(n4579) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n1802), .CK(clk), .RN(n4684),
.Q(intDY_EWSW[16]), .QN(n4578) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n1266), .CK(clk), .RN(n4739), .Q(
Raw_mant_NRM_SWR[3]), .QN(n4576) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n1262), .CK(clk), .RN(n4740), .Q(
Raw_mant_NRM_SWR[7]), .QN(n4575) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_41_ ( .D(n1115), .CK(clk), .RN(n4731), .Q(
DmP_mant_SFG_SWR[41]), .QN(n4573) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_42_ ( .D(n1114), .CK(clk), .RN(n4731), .Q(
DmP_mant_SFG_SWR[42]), .QN(n4572) );
DFFRX1TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n1697), .CK(clk), .RN(n4738),
.Q(shift_value_SHT2_EWR[2]), .QN(n4570) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n1263), .CK(clk), .RN(n4739), .Q(
Raw_mant_NRM_SWR[6]), .QN(n4569) );
DFFRX1TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n1891), .CK(clk), .RN(
n4676), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n4567) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n1790), .CK(clk), .RN(n4686),
.Q(intDY_EWSW[28]), .QN(n4563) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n1792), .CK(clk), .RN(n4685),
.Q(intDY_EWSW[26]), .QN(n4562) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n1794), .CK(clk), .RN(n4685),
.Q(intDY_EWSW[24]), .QN(n4561) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n1796), .CK(clk), .RN(n4685),
.Q(intDY_EWSW[22]), .QN(n4560) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n1798), .CK(clk), .RN(n4685),
.Q(intDY_EWSW[20]), .QN(n4559) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n1800), .CK(clk), .RN(n4685),
.Q(intDY_EWSW[18]), .QN(n4558) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_39_ ( .D(n1117), .CK(clk), .RN(n4730), .Q(
DmP_mant_SFG_SWR[39]), .QN(n4546) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n1152), .CK(clk), .RN(n4727), .Q(
DmP_mant_SFG_SWR[4]), .QN(n4545) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n1150), .CK(clk), .RN(n4727), .Q(
DmP_mant_SFG_SWR[6]), .QN(n4544) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_40_ ( .D(n1116), .CK(clk), .RN(n4730), .Q(
DmP_mant_SFG_SWR[40]), .QN(n4535) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n1695), .CK(clk), .RN(n4726),
.Q(shift_value_SHT2_EWR[4]), .QN(n4534) );
DFFRX1TS inst_ShiftRegister_Q_reg_5_ ( .D(n1889), .CK(clk), .RN(n4676), .Q(
n1953), .QN(n4629) );
DFFRX1TS SHT2_STAGE_SHFTVARS1_Q_reg_5_ ( .D(n1693), .CK(clk), .RN(n4736),
.Q(shift_value_SHT2_EWR[5]), .QN(n4520) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_43_ ( .D(n1775), .CK(clk), .RN(n4687),
.Q(intDY_EWSW[43]), .QN(n4515) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_41_ ( .D(n1777), .CK(clk), .RN(n4687),
.Q(intDY_EWSW[41]), .QN(n4514) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_35_ ( .D(n1783), .CK(clk), .RN(n4686),
.Q(intDY_EWSW[35]), .QN(n4513) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_33_ ( .D(n1785), .CK(clk), .RN(n4686),
.Q(intDY_EWSW[33]), .QN(n4512) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n4676), .Q(
inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n4511) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n1813), .CK(clk), .RN(n4683),
.Q(intDY_EWSW[5]), .QN(n4509) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n1811), .CK(clk), .RN(n4683),
.Q(intDY_EWSW[7]), .QN(n4508) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n1808), .CK(clk), .RN(n4684),
.Q(intDY_EWSW[10]), .QN(n4507) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n1696), .CK(clk), .RN(n4738),
.Q(shift_value_SHT2_EWR[3]), .QN(n4506) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n1255), .CK(clk), .RN(n4739), .Q(
Raw_mant_NRM_SWR[14]), .QN(n4505) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_57_ ( .D(n1761), .CK(clk), .RN(n4688),
.Q(intDY_EWSW[57]), .QN(n4503) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n1787), .CK(clk), .RN(n4686),
.Q(intDY_EWSW[31]), .QN(n4502) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n1789), .CK(clk), .RN(n4686),
.Q(intDY_EWSW[29]), .QN(n4501) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n1795), .CK(clk), .RN(n4685),
.Q(intDY_EWSW[23]), .QN(n4500) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n1797), .CK(clk), .RN(n4685),
.Q(intDY_EWSW[21]), .QN(n4499) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n1805), .CK(clk), .RN(n4684),
.Q(intDY_EWSW[13]), .QN(n4497) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n1791), .CK(clk), .RN(n4685),
.Q(intDY_EWSW[27]), .QN(n4495) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n1793), .CK(clk), .RN(n4685),
.Q(intDY_EWSW[25]), .QN(n4494) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n1799), .CK(clk), .RN(n4685),
.Q(intDY_EWSW[19]), .QN(n4493) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n1801), .CK(clk), .RN(n4684),
.Q(intDY_EWSW[17]), .QN(n4492) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n1809), .CK(clk), .RN(n4684),
.Q(intDY_EWSW[9]), .QN(n4491) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n1155), .CK(clk), .RN(n4736), .Q(
DmP_mant_SFG_SWR[1]), .QN(n4489) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_56_ ( .D(n1827), .CK(clk), .RN(n4682),
.Q(intDX_EWSW[56]), .QN(n4487) );
DFFRX2TS inst_ShiftRegister_Q_reg_1_ ( .D(n1885), .CK(clk), .RN(n4753), .Q(
Shift_reg_FLAGS_7[1]), .QN(n4627) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_54_ ( .D(n1764), .CK(clk), .RN(n4688),
.Q(intDY_EWSW[54]), .QN(n4482) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_55_ ( .D(n1763), .CK(clk), .RN(n4688),
.Q(intDY_EWSW[55]), .QN(n4481) );
DFFRXLTS Ready_reg_Q_reg_0_ ( .D(n1942), .CK(clk), .RN(n4683), .Q(ready) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n1281), .CK(clk), .RN(n4718), .Q(
zero_flag) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1287), .CK(clk), .RN(n4719), .Q(
overflow_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_54_ ( .D(n1684), .CK(clk), .RN(n4720), .Q(
final_result_ieee[54]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_55_ ( .D(n1683), .CK(clk), .RN(n4720), .Q(
final_result_ieee[55]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_58_ ( .D(n1680), .CK(clk), .RN(n4719), .Q(
final_result_ieee[58]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_59_ ( .D(n1679), .CK(clk), .RN(n4719), .Q(
final_result_ieee[59]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n1208), .CK(clk), .RN(n4723), .Q(
final_result_ieee[25]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n1199), .CK(clk), .RN(n4723), .Q(
final_result_ieee[20]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n1198), .CK(clk), .RN(n4722), .Q(
final_result_ieee[30]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n1197), .CK(clk), .RN(n4723), .Q(
final_result_ieee[19]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n1196), .CK(clk), .RN(n4722), .Q(
final_result_ieee[31]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n1195), .CK(clk), .RN(n4723), .Q(
final_result_ieee[18]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_32_ ( .D(n1194), .CK(clk), .RN(n4722), .Q(
final_result_ieee[32]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n1191), .CK(clk), .RN(n4723), .Q(
final_result_ieee[16]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_34_ ( .D(n1190), .CK(clk), .RN(n4722), .Q(
final_result_ieee[34]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n1189), .CK(clk), .RN(n4724), .Q(
final_result_ieee[15]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_35_ ( .D(n1188), .CK(clk), .RN(n4722), .Q(
final_result_ieee[35]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n1187), .CK(clk), .RN(n4724), .Q(
final_result_ieee[14]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_36_ ( .D(n1186), .CK(clk), .RN(n4721), .Q(
final_result_ieee[36]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_37_ ( .D(n1184), .CK(clk), .RN(n4721), .Q(
final_result_ieee[37]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_38_ ( .D(n1182), .CK(clk), .RN(n4721), .Q(
final_result_ieee[38]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_39_ ( .D(n1180), .CK(clk), .RN(n4721), .Q(
final_result_ieee[39]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_40_ ( .D(n1178), .CK(clk), .RN(n4721), .Q(
final_result_ieee[40]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n1167), .CK(clk), .RN(n2705), .Q(
final_result_ieee[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_46_ ( .D(n1166), .CK(clk), .RN(n4720), .Q(
final_result_ieee[46]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n1165), .CK(clk), .RN(n2711), .Q(
final_result_ieee[3]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_47_ ( .D(n1164), .CK(clk), .RN(n4720), .Q(
final_result_ieee[47]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n1163), .CK(clk), .RN(n2708), .Q(
final_result_ieee[2]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_48_ ( .D(n1162), .CK(clk), .RN(n4720), .Q(
final_result_ieee[48]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_52_ ( .D(n1686), .CK(clk), .RN(n4720), .Q(
final_result_ieee[52]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_53_ ( .D(n1685), .CK(clk), .RN(n4720), .Q(
final_result_ieee[53]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_56_ ( .D(n1682), .CK(clk), .RN(n4719), .Q(
final_result_ieee[56]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_57_ ( .D(n1681), .CK(clk), .RN(n4719), .Q(
final_result_ieee[57]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_60_ ( .D(n1678), .CK(clk), .RN(n4719), .Q(
final_result_ieee[60]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_61_ ( .D(n1677), .CK(clk), .RN(n4719), .Q(
final_result_ieee[61]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_62_ ( .D(n1676), .CK(clk), .RN(n4719), .Q(
final_result_ieee[62]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_63_ ( .D(n1270), .CK(clk), .RN(n4719), .Q(
final_result_ieee[63]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n1185), .CK(clk), .RN(n4724), .Q(
final_result_ieee[13]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n1183), .CK(clk), .RN(n4724), .Q(
final_result_ieee[12]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n1181), .CK(clk), .RN(n4724), .Q(
final_result_ieee[11]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n1179), .CK(clk), .RN(n4724), .Q(
final_result_ieee[10]) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1288), .CK(clk), .RN(n4719), .Q(
underflow_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n1207), .CK(clk), .RN(n4723), .Q(
final_result_ieee[24]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n1206), .CK(clk), .RN(n4722), .Q(
final_result_ieee[26]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n1205), .CK(clk), .RN(n4723), .Q(
final_result_ieee[23]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n1204), .CK(clk), .RN(n4722), .Q(
final_result_ieee[27]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n1203), .CK(clk), .RN(n4723), .Q(
final_result_ieee[22]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n1202), .CK(clk), .RN(n4722), .Q(
final_result_ieee[28]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n1201), .CK(clk), .RN(n4723), .Q(
final_result_ieee[21]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n1200), .CK(clk), .RN(n4722), .Q(
final_result_ieee[29]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n1193), .CK(clk), .RN(n4723), .Q(
final_result_ieee[17]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_33_ ( .D(n1192), .CK(clk), .RN(n4722), .Q(
final_result_ieee[33]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n1177), .CK(clk), .RN(n4724), .Q(
final_result_ieee[9]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_41_ ( .D(n1176), .CK(clk), .RN(n4721), .Q(
final_result_ieee[41]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n1175), .CK(clk), .RN(n4724), .Q(
final_result_ieee[8]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_42_ ( .D(n1174), .CK(clk), .RN(n4721), .Q(
final_result_ieee[42]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n1173), .CK(clk), .RN(n4724), .Q(
final_result_ieee[7]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_43_ ( .D(n1172), .CK(clk), .RN(n4721), .Q(
final_result_ieee[43]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n1171), .CK(clk), .RN(n4724), .Q(
final_result_ieee[6]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_44_ ( .D(n1170), .CK(clk), .RN(n4721), .Q(
final_result_ieee[44]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n1169), .CK(clk), .RN(n2707), .Q(
final_result_ieee[5]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_45_ ( .D(n1168), .CK(clk), .RN(n4721), .Q(
final_result_ieee[45]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n1161), .CK(clk), .RN(n2709), .Q(
final_result_ieee[1]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_49_ ( .D(n1160), .CK(clk), .RN(n4720), .Q(
final_result_ieee[49]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n1159), .CK(clk), .RN(n2706), .Q(
final_result_ieee[0]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_50_ ( .D(n1158), .CK(clk), .RN(n4720), .Q(
final_result_ieee[50]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_51_ ( .D(n1157), .CK(clk), .RN(n4720), .Q(
final_result_ieee[51]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n1720), .CK(clk), .RN(n4735), .Q(
Data_array_SWR[22]), .QN(n4622) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n1713), .CK(clk), .RN(n4733), .Q(
Data_array_SWR[15]), .QN(n4621) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_47_ ( .D(n1745), .CK(clk), .RN(n4734), .Q(
Data_array_SWR[46]), .QN(n4608) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_47_ ( .D(n1109), .CK(clk), .RN(n4732), .Q(
DmP_mant_SFG_SWR[47]), .QN(n4640) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_49_ ( .D(n1747), .CK(clk), .RN(n4736), .Q(
Data_array_SWR[48]), .QN(n4610) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_50_ ( .D(n1748), .CK(clk), .RN(n4734), .Q(
Data_array_SWR[49]), .QN(n4609) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_46_ ( .D(n1110), .CK(clk), .RN(n4731), .Q(
DmP_mant_SFG_SWR[46]), .QN(n4658) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_45_ ( .D(n1111), .CK(clk), .RN(n4731), .Q(
DmP_mant_SFG_SWR[45]), .QN(n4641) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_48_ ( .D(n1746), .CK(clk), .RN(n4731), .Q(
Data_array_SWR[47]), .QN(n4607) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_40_ ( .D(n1778), .CK(clk), .RN(n4687),
.Q(intDY_EWSW[40]), .QN(n4599) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_32_ ( .D(n1786), .CK(clk), .RN(n4686),
.Q(intDY_EWSW[32]), .QN(n4565) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_42_ ( .D(n1776), .CK(clk), .RN(n4687),
.Q(intDY_EWSW[42]), .QN(n4600) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_50_ ( .D(n1768), .CK(clk), .RN(n4688),
.Q(intDY_EWSW[50]), .QN(n4581) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_38_ ( .D(n1780), .CK(clk), .RN(n4687),
.Q(intDY_EWSW[38]), .QN(n4596) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_60_ ( .D(n1823), .CK(clk), .RN(n4682),
.Q(intDX_EWSW[60]), .QN(n4583) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_58_ ( .D(n1825), .CK(clk), .RN(n4682),
.Q(intDX_EWSW[58]), .QN(n4582) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_47_ ( .D(n1771), .CK(clk), .RN(n4687),
.Q(intDY_EWSW[47]), .QN(n4528) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_62_ ( .D(n1821), .CK(clk), .RN(n4682),
.Q(intDX_EWSW[62]), .QN(n4504) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_51_ ( .D(n1767), .CK(clk), .RN(n4688),
.Q(intDY_EWSW[51]), .QN(n4603) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n1804), .CK(clk), .RN(n4684),
.Q(intDY_EWSW[14]), .QN(n4557) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_59_ ( .D(n1824), .CK(clk), .RN(n4682),
.Q(intDX_EWSW[59]), .QN(n4524) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_44_ ( .D(n1774), .CK(clk), .RN(n4687),
.Q(intDY_EWSW[44]), .QN(n4601) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_45_ ( .D(n1773), .CK(clk), .RN(n4687),
.Q(intDY_EWSW[45]), .QN(n4527) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_61_ ( .D(n1822), .CK(clk), .RN(n4682),
.Q(intDX_EWSW[61]), .QN(n4568) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_46_ ( .D(n1772), .CK(clk), .RN(n4687),
.Q(intDY_EWSW[46]), .QN(n4602) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n1803), .CK(clk), .RN(n4684),
.Q(intDY_EWSW[15]), .QN(n4498) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_53_ ( .D(n1830), .CK(clk), .RN(n4681),
.Q(intDX_EWSW[53]), .QN(n4531) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n1817), .CK(clk), .RN(n4683),
.Q(intDY_EWSW[1]), .QN(n4595) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n1139), .CK(clk), .RN(n4728), .Q(
DmP_mant_SFG_SWR[17]), .QN(n4551) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n1135), .CK(clk), .RN(n4729), .Q(
DmP_mant_SFG_SWR[21]), .QN(n4550) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_33_ ( .D(n1123), .CK(clk), .RN(n4730), .Q(
DmP_mant_SFG_SWR[33]), .QN(n4548) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_37_ ( .D(n1119), .CK(clk), .RN(n4730), .Q(
DmP_mant_SFG_SWR[37]), .QN(n4547) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n1140), .CK(clk), .RN(n4728), .Q(
DmP_mant_SFG_SWR[16]), .QN(n4543) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n1138), .CK(clk), .RN(n4728), .Q(
DmP_mant_SFG_SWR[18]), .QN(n4542) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n1136), .CK(clk), .RN(n4728), .Q(
DmP_mant_SFG_SWR[20]), .QN(n4541) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n1134), .CK(clk), .RN(n4729), .Q(
DmP_mant_SFG_SWR[22]), .QN(n4540) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_32_ ( .D(n1124), .CK(clk), .RN(n4730), .Q(
DmP_mant_SFG_SWR[32]), .QN(n4539) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_34_ ( .D(n1122), .CK(clk), .RN(n4730), .Q(
DmP_mant_SFG_SWR[34]), .QN(n4538) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_36_ ( .D(n1120), .CK(clk), .RN(n4730), .Q(
DmP_mant_SFG_SWR[36]), .QN(n4537) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_38_ ( .D(n1118), .CK(clk), .RN(n4730), .Q(
DmP_mant_SFG_SWR[38]), .QN(n4536) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_39_ ( .D(n1779), .CK(clk), .RN(n4687),
.Q(intDY_EWSW[39]), .QN(n4526) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_55_ ( .D(n1828), .CK(clk), .RN(n4682),
.Q(intDX_EWSW[55]), .QN(n4532) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_8_ ( .D(n1583), .CK(clk), .RN(n4746), .Q(
DMP_SFG[8]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n1870), .CK(clk), .RN(n4677),
.Q(intDX_EWSW[13]), .QN(n1954) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_41_ ( .D(n1842), .CK(clk), .RN(n4680),
.Q(intDX_EWSW[41]), .QN(n1955) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_24_ ( .D(n1535), .CK(clk), .RN(n4749), .Q(
DMP_SFG[24]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_38_ ( .D(n1845), .CK(clk), .RN(n4680),
.Q(intDX_EWSW[38]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_23_ ( .D(n1538), .CK(clk), .RN(n4749), .Q(
DMP_SFG[23]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_25_ ( .D(n1532), .CK(clk), .RN(n4749), .Q(
DMP_SFG[25]) );
DFFRX4TS SFT2FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1276), .CK(clk), .RN(n4725),
.Q(ADD_OVRFLW_NRM2), .QN(DP_OP_15J155_122_2221_n35) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_7_ ( .D(n1586), .CK(clk), .RN(n4746), .Q(
DMP_SFG[7]) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n1269), .CK(clk), .RN(n4736), .Q(
Raw_mant_NRM_SWR[0]), .QN(n4587) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_41_ ( .D(n1228), .CK(clk), .RN(n4742), .Q(
Raw_mant_NRM_SWR[41]), .QN(n4519) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n1143), .CK(clk), .RN(n4728), .Q(
DmP_mant_SFG_SWR[13]), .QN(n4655) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_36_ ( .D(n1782), .CK(clk), .RN(n4686),
.Q(intDY_EWSW[36]), .QN(n4598) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_49_ ( .D(n1834), .CK(clk), .RN(n4681),
.Q(intDX_EWSW[49]), .QN(n4584) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_52_ ( .D(n1766), .CK(clk), .RN(n4688),
.Q(intDY_EWSW[52]), .QN(n4518) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_54_ ( .D(n1829), .CK(clk), .RN(n4682),
.Q(intDX_EWSW[54]), .QN(n4529) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n1878), .CK(clk), .RN(n4677),
.Q(intDX_EWSW[5]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n1876), .CK(clk), .RN(n4677),
.Q(intDX_EWSW[7]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_47_ ( .D(n1836), .CK(clk), .RN(n4681),
.Q(intDX_EWSW[47]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_37_ ( .D(n1846), .CK(clk), .RN(n4680),
.Q(intDX_EWSW[37]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_52_ ( .D(n1831), .CK(clk), .RN(n4681),
.Q(intDX_EWSW[52]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n1859), .CK(clk), .RN(n4679),
.Q(intDX_EWSW[24]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_48_ ( .D(n1835), .CK(clk), .RN(n4681),
.Q(intDX_EWSW[48]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n1867), .CK(clk), .RN(n4678),
.Q(intDX_EWSW[16]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_40_ ( .D(n1843), .CK(clk), .RN(n4680),
.Q(intDX_EWSW[40]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n1873), .CK(clk), .RN(n4677),
.Q(intDX_EWSW[10]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_32_ ( .D(n1851), .CK(clk), .RN(n4679),
.Q(intDX_EWSW[32]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n1881), .CK(clk), .RN(n4676),
.Q(intDX_EWSW[2]) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n1892), .CK(clk), .RN(
n4676), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_42_ ( .D(n1841), .CK(clk), .RN(n4680),
.Q(intDX_EWSW[42]), .QN(n1971) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_34_ ( .D(n1849), .CK(clk), .RN(n4680),
.Q(intDX_EWSW[34]), .QN(n1965) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_60_ ( .D(n1758), .CK(clk), .RN(n4689),
.Q(intDY_EWSW[60]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n1883), .CK(clk), .RN(n4676),
.Q(intDX_EWSW[0]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_58_ ( .D(n1760), .CK(clk), .RN(n4689),
.Q(intDY_EWSW[58]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n1853), .CK(clk), .RN(n4679),
.Q(intDX_EWSW[30]), .QN(n1979) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n1854), .CK(clk), .RN(n4679),
.Q(intDX_EWSW[29]), .QN(n1991) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n1856), .CK(clk), .RN(n4679),
.Q(intDX_EWSW[27]), .QN(n1984) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n1864), .CK(clk), .RN(n4678),
.Q(intDX_EWSW[19]), .QN(n1980) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n1861), .CK(clk), .RN(n4678),
.Q(intDX_EWSW[22]), .QN(n1970) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_62_ ( .D(n1756), .CK(clk), .RN(n4689),
.Q(intDY_EWSW[62]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_2_ ( .D(n1601), .CK(clk), .RN(n4745), .Q(
DMP_SFG[2]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_52_ ( .D(n1750), .CK(clk), .RN(n4735), .Q(
Data_array_SWR[51]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_53_ ( .D(n1751), .CK(clk), .RN(n4736), .Q(
Data_array_SWR[52]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_54_ ( .D(n1752), .CK(clk), .RN(n4737), .Q(
Data_array_SWR[53]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_16_ ( .D(n1559), .CK(clk), .RN(n4748), .Q(
DMP_SFG[16]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_42_ ( .D(n1481), .CK(clk), .RN(n4752), .Q(
DMP_SFG[42]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_41_ ( .D(n1484), .CK(clk), .RN(n4752), .Q(
DMP_SFG[41]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_39_ ( .D(n1490), .CK(clk), .RN(n4752), .Q(
DMP_SFG[39]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_37_ ( .D(n1496), .CK(clk), .RN(n4752), .Q(
DMP_SFG[37]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_35_ ( .D(n1502), .CK(clk), .RN(n4751), .Q(
DMP_SFG[35]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_33_ ( .D(n1508), .CK(clk), .RN(n4751), .Q(
DMP_SFG[33]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_31_ ( .D(n1514), .CK(clk), .RN(n4751), .Q(
DMP_SFG[31]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_30_ ( .D(n1517), .CK(clk), .RN(n4750), .Q(
DMP_SFG[30]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_29_ ( .D(n1520), .CK(clk), .RN(n4750), .Q(
DMP_SFG[29]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_28_ ( .D(n1523), .CK(clk), .RN(n4750), .Q(
DMP_SFG[28]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_27_ ( .D(n1526), .CK(clk), .RN(n4750), .Q(
DMP_SFG[27]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_26_ ( .D(n1529), .CK(clk), .RN(n4750), .Q(
DMP_SFG[26]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_22_ ( .D(n1541), .CK(clk), .RN(n4749), .Q(
DMP_SFG[22]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_21_ ( .D(n1544), .CK(clk), .RN(n4749), .Q(
DMP_SFG[21]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_20_ ( .D(n1547), .CK(clk), .RN(n4748), .Q(
DMP_SFG[20]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_19_ ( .D(n1550), .CK(clk), .RN(n4748), .Q(
DMP_SFG[19]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_18_ ( .D(n1553), .CK(clk), .RN(n4748), .Q(
DMP_SFG[18]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_17_ ( .D(n1556), .CK(clk), .RN(n4748), .Q(
DMP_SFG[17]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_14_ ( .D(n1565), .CK(clk), .RN(n4747), .Q(
DMP_SFG[14]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_13_ ( .D(n1568), .CK(clk), .RN(n4747), .Q(
DMP_SFG[13]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_11_ ( .D(n1574), .CK(clk), .RN(n4747), .Q(
DMP_SFG[11]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_9_ ( .D(n1580), .CK(clk), .RN(n4746), .Q(
DMP_SFG[9]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_6_ ( .D(n1589), .CK(clk), .RN(n4746), .Q(
DMP_SFG[6]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_5_ ( .D(n1592), .CK(clk), .RN(n4745), .Q(
DMP_SFG[5]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n1258), .CK(clk), .RN(n4740), .Q(
Raw_mant_NRM_SWR[11]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n1721), .CK(clk), .RN(n4733), .Q(
Data_array_SWR[23]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n1722), .CK(clk), .RN(n4732), .Q(
Data_array_SWR[24]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n1723), .CK(clk), .RN(n4738), .Q(
Data_array_SWR[25]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_38_ ( .D(n1736), .CK(clk), .RN(n4735), .Q(
Data_array_SWR[37]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_28_ ( .D(n1726), .CK(clk), .RN(n4732), .Q(
Data_array_SWR[28]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_29_ ( .D(n1727), .CK(clk), .RN(n4739), .Q(
Data_array_SWR[29]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_27_ ( .D(n1725), .CK(clk), .RN(n4733), .Q(
Data_array_SWR[27]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n1712), .CK(clk), .RN(n4735), .Q(
Data_array_SWR[14]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_40_ ( .D(n1738), .CK(clk), .RN(n4731), .Q(
Data_array_SWR[39]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_41_ ( .D(n1739), .CK(clk), .RN(n4737), .Q(
Data_array_SWR[40]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n1716), .CK(clk), .RN(n4735), .Q(
Data_array_SWR[18]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_0_ ( .D(n1607), .CK(clk), .RN(n4744), .Q(
DMP_SFG[0]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_40_ ( .D(n1487), .CK(clk), .RN(n4752), .Q(
DMP_SFG[40]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_38_ ( .D(n1493), .CK(clk), .RN(n4752), .Q(
DMP_SFG[38]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_36_ ( .D(n1499), .CK(clk), .RN(n4752), .Q(
DMP_SFG[36]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_34_ ( .D(n1505), .CK(clk), .RN(n4751), .Q(
DMP_SFG[34]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_32_ ( .D(n1511), .CK(clk), .RN(n4751), .Q(
DMP_SFG[32]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_12_ ( .D(n1571), .CK(clk), .RN(n4747), .Q(
DMP_SFG[12]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_10_ ( .D(n1577), .CK(clk), .RN(n4746), .Q(
DMP_SFG[10]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_4_ ( .D(n1595), .CK(clk), .RN(n4745), .Q(
DMP_SFG[4]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_33_ ( .D(n1850), .CK(clk), .RN(n4679),
.Q(intDX_EWSW[33]), .QN(n1963) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_50_ ( .D(n1457), .CK(clk), .RN(n4754), .Q(
DMP_SFG[50]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_48_ ( .D(n1463), .CK(clk), .RN(n4754), .Q(
DMP_SFG[48]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_46_ ( .D(n1469), .CK(clk), .RN(n4753), .Q(
DMP_SFG[46]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_44_ ( .D(n1475), .CK(clk), .RN(n4753), .Q(
DMP_SFG[44]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_49_ ( .D(n1460), .CK(clk), .RN(n4754), .Q(
DMP_SFG[49]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_47_ ( .D(n1466), .CK(clk), .RN(n4754), .Q(
DMP_SFG[47]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_45_ ( .D(n1472), .CK(clk), .RN(n4753), .Q(
DMP_SFG[45]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_43_ ( .D(n1478), .CK(clk), .RN(n4752), .Q(
DMP_SFG[43]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n1872), .CK(clk), .RN(n4677),
.Q(intDX_EWSW[11]), .QN(n1989) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_51_ ( .D(n1454), .CK(clk), .RN(n4754), .Q(
DMP_SFG[51]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_39_ ( .D(n1844), .CK(clk), .RN(n4680),
.Q(intDX_EWSW[39]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n1707), .CK(clk), .RN(n4737), .Q(
Data_array_SWR[9]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n1706), .CK(clk), .RN(n4731), .Q(
Data_array_SWR[8]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_56_ ( .D(n1762), .CK(clk), .RN(n4688),
.Q(intDY_EWSW[56]), .QN(n1988) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n1709), .CK(clk), .RN(n4733), .Q(
Data_array_SWR[11]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_63_ ( .D(n1820), .CK(clk), .RN(n4682),
.Q(intDX_EWSW[63]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n1250), .CK(clk), .RN(n4741), .Q(
Raw_mant_NRM_SWR[19]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n1869), .CK(clk), .RN(n4678),
.Q(intDX_EWSW[14]), .QN(n1969) );
DFFRX1TS SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n1278), .CK(clk), .RN(n4744), .Q(
OP_FLAG_SFG) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n1703), .CK(clk), .RN(n4737), .Q(
Data_array_SWR[5]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n1705), .CK(clk), .RN(n4733), .Q(
Data_array_SWR[7]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_52_ ( .D(n1294), .CK(clk), .RN(n4717), .Q(
DmP_EXP_EWSW[52]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_57_ ( .D(n1618), .CK(clk), .RN(n4695), .Q(
DMP_EXP_EWSW[57]) );
DFFRX1TS inst_ShiftRegister_Q_reg_3_ ( .D(n1887), .CK(clk), .RN(n4676), .Q(
Shift_reg_FLAGS_7[3]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_15_ ( .D(n1562), .CK(clk), .RN(n4747), .Q(
DMP_SFG[15]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_1_ ( .D(n1604), .CK(clk), .RN(n4745), .Q(
DMP_SFG[1]) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n1689), .CK(clk), .RN(n4738),
.Q(Shift_amount_SHT1_EWR[3]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_25_ ( .D(n1347), .CK(clk), .RN(n4738),
.Q(DmP_mant_SHT1_SW[25]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n1533), .CK(clk), .RN(n4750), .Q(
DMP_SHT2_EWSW[25]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n1536), .CK(clk), .RN(n4749), .Q(
DMP_SHT2_EWSW[24]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n1539), .CK(clk), .RN(n4749), .Q(
DMP_SHT2_EWSW[23]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n1584), .CK(clk), .RN(n4746), .Q(
DMP_SHT2_EWSW[8]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n1587), .CK(clk), .RN(n4746), .Q(
DMP_SHT2_EWSW[7]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n1599), .CK(clk), .RN(n4745), .Q(
DMP_SHT2_EWSW[3]) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n1688), .CK(clk), .RN(n4744),
.Q(Shift_amount_SHT1_EWR[4]) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n1690), .CK(clk), .RN(n4739),
.Q(Shift_amount_SHT1_EWR[2]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_63_ ( .D(n1755), .CK(clk), .RN(n4689),
.Q(intDY_EWSW[63]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_51_ ( .D(n1295), .CK(clk), .RN(n4736),
.Q(DmP_mant_SHT1_SW[51]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_50_ ( .D(n1297), .CK(clk), .RN(n4736),
.Q(DmP_mant_SHT1_SW[50]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n1353), .CK(clk), .RN(n4738),
.Q(DmP_mant_SHT1_SW[22]) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n1691), .CK(clk), .RN(n4739),
.Q(Shift_amount_SHT1_EWR[1]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n1212), .CK(clk), .RN(n2710),
.Q(LZD_output_NRM2_EW[1]) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n1692), .CK(clk), .RN(n4739),
.Q(Shift_amount_SHT1_EWR[0]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n1879), .CK(clk), .RN(n4677),
.Q(intDX_EWSW[4]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n1877), .CK(clk), .RN(n4677),
.Q(intDX_EWSW[6]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n1874), .CK(clk), .RN(n4677),
.Q(intDX_EWSW[9]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_51_ ( .D(n1832), .CK(clk), .RN(n4681),
.Q(intDX_EWSW[51]), .QN(n1958) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n1871), .CK(clk), .RN(n4677),
.Q(intDX_EWSW[12]), .QN(n1961) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n1855), .CK(clk), .RN(n4679),
.Q(intDX_EWSW[28]), .QN(n1986) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n1862), .CK(clk), .RN(n4678),
.Q(intDX_EWSW[21]), .QN(n1966) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_46_ ( .D(n1837), .CK(clk), .RN(n4681),
.Q(intDX_EWSW[46]), .QN(n1975) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n1863), .CK(clk), .RN(n4678),
.Q(intDX_EWSW[20]), .QN(n1962) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_59_ ( .D(n1759), .CK(clk), .RN(n4689),
.Q(intDY_EWSW[59]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_30_ ( .D(n1728), .CK(clk), .RN(n4735), .Q(
Data_array_SWR[30]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_26_ ( .D(n1724), .CK(clk), .RN(n4735), .Q(
Data_array_SWR[26]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n1719), .CK(clk), .RN(n4738), .Q(
Data_array_SWR[21]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n1718), .CK(clk), .RN(n4732), .Q(
Data_array_SWR[20]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n1715), .CK(clk), .RN(n4738), .Q(
Data_array_SWR[17]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n1714), .CK(clk), .RN(n4732), .Q(
Data_array_SWR[16]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_45_ ( .D(n1743), .CK(clk), .RN(n4737), .Q(
Data_array_SWR[44]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_44_ ( .D(n1742), .CK(clk), .RN(n4731), .Q(
Data_array_SWR[43]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n1717), .CK(clk), .RN(n4733), .Q(
Data_array_SWR[19]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n1711), .CK(clk), .RN(n4737), .Q(
Data_array_SWR[13]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n1710), .CK(clk), .RN(n4732), .Q(
Data_array_SWR[12]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_33_ ( .D(n1731), .CK(clk), .RN(n4737), .Q(
Data_array_SWR[33]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_32_ ( .D(n1730), .CK(clk), .RN(n4732), .Q(
Data_array_SWR[32]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_31_ ( .D(n1729), .CK(clk), .RN(n4733), .Q(
Data_array_SWR[31]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n1814), .CK(clk), .RN(n4683),
.Q(intDY_EWSW[4]), .QN(n4554) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n1866), .CK(clk), .RN(n4678),
.Q(intDX_EWSW[17]), .QN(n1983) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n1860), .CK(clk), .RN(n4678),
.Q(intDX_EWSW[23]), .QN(n1973) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n1858), .CK(clk), .RN(n4679),
.Q(intDX_EWSW[25]), .QN(n1952) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n1852), .CK(clk), .RN(n4679),
.Q(intDX_EWSW[31]), .QN(n1981) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_36_ ( .D(n1847), .CK(clk), .RN(n4680),
.Q(intDX_EWSW[36]), .QN(n1968) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n1875), .CK(clk), .RN(n4677),
.Q(intDX_EWSW[8]), .QN(n1950) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n1865), .CK(clk), .RN(n4678),
.Q(intDX_EWSW[18]), .QN(n1990) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n1857), .CK(clk), .RN(n4679),
.Q(intDX_EWSW[26]), .QN(n1957) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_50_ ( .D(n1833), .CK(clk), .RN(n4681),
.Q(intDX_EWSW[50]), .QN(n1956) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_35_ ( .D(n1848), .CK(clk), .RN(n4680),
.Q(intDX_EWSW[35]), .QN(n1967) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_43_ ( .D(n1840), .CK(clk), .RN(n4680),
.Q(intDX_EWSW[43]), .QN(n1972) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_45_ ( .D(n1838), .CK(clk), .RN(n4681),
.Q(intDX_EWSW[45]), .QN(n1974) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_57_ ( .D(n1826), .CK(clk), .RN(n4682),
.Q(intDX_EWSW[57]), .QN(n1985) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_53_ ( .D(n1765), .CK(clk), .RN(n4688),
.Q(intDY_EWSW[53]), .QN(n1987) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n1708), .CK(clk), .RN(n4735), .Q(
Data_array_SWR[10]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n1818), .CK(clk), .RN(n4683),
.Q(intDY_EWSW[0]), .QN(n4490) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n1816), .CK(clk), .RN(n4683),
.Q(intDY_EWSW[2]), .QN(n4553) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_61_ ( .D(n1757), .CK(clk), .RN(n4689),
.Q(intDY_EWSW[61]), .QN(n1992) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n1882), .CK(clk), .RN(n4676),
.Q(intDX_EWSW[1]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_37_ ( .D(n1781), .CK(clk), .RN(n4686),
.Q(intDY_EWSW[37]), .QN(n4525) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n1704), .CK(clk), .RN(n4735), .Q(
Data_array_SWR[6]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_54_ ( .D(n1292), .CK(clk), .RN(n4717), .Q(
DmP_EXP_EWSW[54]), .QN(n1978) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_56_ ( .D(n1290), .CK(clk), .RN(n4717), .Q(
DmP_EXP_EWSW[56]), .QN(n1964) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_55_ ( .D(n1620), .CK(clk), .RN(n4695), .Q(
DMP_EXP_EWSW[55]), .QN(n1960) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n1145), .CK(clk), .RN(n4728), .Q(
DmP_mant_SFG_SWR[11]), .QN(n4650) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_54_ ( .D(n1621), .CK(clk), .RN(n4695), .Q(
DMP_EXP_EWSW[54]), .QN(n4485) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_56_ ( .D(n1619), .CK(clk), .RN(n4695), .Q(
DMP_EXP_EWSW[56]), .QN(n4530) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_53_ ( .D(n1622), .CK(clk), .RN(n4695), .Q(
DMP_EXP_EWSW[53]), .QN(n1959) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_3_ ( .D(n1598), .CK(clk), .RN(n4745), .Q(
DMP_SFG[3]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_37_ ( .D(n1735), .CK(clk), .RN(n4737), .Q(
Data_array_SWR[36]), .QN(n4605) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_36_ ( .D(n1734), .CK(clk), .RN(n4732), .Q(
Data_array_SWR[35]), .QN(n4604) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_35_ ( .D(n1733), .CK(clk), .RN(n4734), .Q(
Data_array_SWR[34]), .QN(n4618) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n1880), .CK(clk), .RN(n4676),
.Q(intDX_EWSW[3]), .QN(n1949) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n1868), .CK(clk), .RN(n4678),
.Q(intDX_EWSW[15]), .QN(n1951) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_48_ ( .D(n1770), .CK(clk), .RN(n4688),
.Q(intDY_EWSW[48]), .QN(n4566) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n1608), .CK(clk), .RN(n4745), .Q(
DMP_SHT2_EWSW[0]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n1605), .CK(clk), .RN(n4745), .Q(
DMP_SHT2_EWSW[1]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n1602), .CK(clk), .RN(n4745), .Q(
DMP_SHT2_EWSW[2]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n1596), .CK(clk), .RN(n4745), .Q(
DMP_SHT2_EWSW[4]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n1593), .CK(clk), .RN(n4746), .Q(
DMP_SHT2_EWSW[5]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n1581), .CK(clk), .RN(n4746), .Q(
DMP_SHT2_EWSW[9]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n1578), .CK(clk), .RN(n4747), .Q(
DMP_SHT2_EWSW[10]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n1575), .CK(clk), .RN(n4747), .Q(
DMP_SHT2_EWSW[11]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n1572), .CK(clk), .RN(n4747), .Q(
DMP_SHT2_EWSW[12]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n1569), .CK(clk), .RN(n4747), .Q(
DMP_SHT2_EWSW[13]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n1566), .CK(clk), .RN(n4747), .Q(
DMP_SHT2_EWSW[14]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n1563), .CK(clk), .RN(n4748), .Q(
DMP_SHT2_EWSW[15]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n1560), .CK(clk), .RN(n4748), .Q(
DMP_SHT2_EWSW[16]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n1557), .CK(clk), .RN(n4748), .Q(
DMP_SHT2_EWSW[17]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n1554), .CK(clk), .RN(n4748), .Q(
DMP_SHT2_EWSW[18]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n1551), .CK(clk), .RN(n4748), .Q(
DMP_SHT2_EWSW[19]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n1548), .CK(clk), .RN(n4749), .Q(
DMP_SHT2_EWSW[20]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n1545), .CK(clk), .RN(n4749), .Q(
DMP_SHT2_EWSW[21]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n1542), .CK(clk), .RN(n4749), .Q(
DMP_SHT2_EWSW[22]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n1527), .CK(clk), .RN(n4750), .Q(
DMP_SHT2_EWSW[27]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n1524), .CK(clk), .RN(n4750), .Q(
DMP_SHT2_EWSW[28]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n1521), .CK(clk), .RN(n4750), .Q(
DMP_SHT2_EWSW[29]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n1518), .CK(clk), .RN(n4751), .Q(
DMP_SHT2_EWSW[30]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_31_ ( .D(n1515), .CK(clk), .RN(n4751), .Q(
DMP_SHT2_EWSW[31]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_32_ ( .D(n1512), .CK(clk), .RN(n4751), .Q(
DMP_SHT2_EWSW[32]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_33_ ( .D(n1509), .CK(clk), .RN(n4751), .Q(
DMP_SHT2_EWSW[33]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_34_ ( .D(n1506), .CK(clk), .RN(n4751), .Q(
DMP_SHT2_EWSW[34]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_35_ ( .D(n1503), .CK(clk), .RN(n4752), .Q(
DMP_SHT2_EWSW[35]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_36_ ( .D(n1500), .CK(clk), .RN(n4752), .Q(
DMP_SHT2_EWSW[36]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_24_ ( .D(n1349), .CK(clk), .RN(n4738),
.Q(DmP_mant_SHT1_SW[24]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_57_ ( .D(n1289), .CK(clk), .RN(n4717), .Q(
DmP_EXP_EWSW[57]) );
DFFRX1TS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n1450), .CK(clk), .RN(n4725), .Q(
DMP_exp_NRM_EW[0]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_55_ ( .D(n1291), .CK(clk), .RN(n4717), .Q(
DmP_EXP_EWSW[55]), .QN(n4488) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_23_ ( .D(n1352), .CK(clk), .RN(n4711), .Q(
DmP_EXP_EWSW[23]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_24_ ( .D(n1350), .CK(clk), .RN(n4711), .Q(
DmP_EXP_EWSW[24]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_25_ ( .D(n1348), .CK(clk), .RN(n4712), .Q(
DmP_EXP_EWSW[25]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_50_ ( .D(n1298), .CK(clk), .RN(n4716), .Q(
DmP_EXP_EWSW[50]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_51_ ( .D(n1296), .CK(clk), .RN(n4717), .Q(
DmP_EXP_EWSW[51]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n1701), .CK(clk), .RN(n4733), .Q(
Data_array_SWR[3]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n1700), .CK(clk), .RN(n4735), .Q(
Data_array_SWR[2]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n1699), .CK(clk), .RN(n4737), .Q(
Data_array_SWR[1]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_26_ ( .D(n1243), .CK(clk), .RN(n4742), .Q(
Raw_mant_NRM_SWR[26]), .QN(n4630) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_27_ ( .D(n1242), .CK(clk), .RN(n4727), .Q(
Raw_mant_NRM_SWR[27]), .QN(n4580) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_31_ ( .D(n1238), .CK(clk), .RN(n4741), .Q(
Raw_mant_NRM_SWR[31]), .QN(n4510) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_32_ ( .D(n1237), .CK(clk), .RN(n4744), .Q(
Raw_mant_NRM_SWR[32]), .QN(n4671) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_33_ ( .D(n1236), .CK(clk), .RN(n4744), .Q(
Raw_mant_NRM_SWR[33]), .QN(n4594) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_34_ ( .D(n1235), .CK(clk), .RN(n4744), .Q(
Raw_mant_NRM_SWR[34]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_35_ ( .D(n1234), .CK(clk), .RN(n4744), .Q(
Raw_mant_NRM_SWR[35]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_46_ ( .D(n1223), .CK(clk), .RN(n4742), .Q(
Raw_mant_NRM_SWR[46]), .QN(n4552) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_49_ ( .D(n1220), .CK(clk), .RN(n4743), .Q(
Raw_mant_NRM_SWR[49]), .QN(n4483) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_50_ ( .D(n1219), .CK(clk), .RN(n4743), .Q(
Raw_mant_NRM_SWR[50]), .QN(n4533) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_51_ ( .D(n1218), .CK(clk), .RN(n4743), .Q(
Raw_mant_NRM_SWR[51]), .QN(n4522) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_52_ ( .D(n1217), .CK(clk), .RN(n4743), .Q(
Raw_mant_NRM_SWR[52]), .QN(n4523) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_53_ ( .D(n1216), .CK(clk), .RN(n4743), .Q(
Raw_mant_NRM_SWR[53]), .QN(n4670) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_54_ ( .D(n1215), .CK(clk), .RN(n4744), .Q(
Raw_mant_NRM_SWR[54]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n1248), .CK(clk), .RN(n4740), .Q(
Raw_mant_NRM_SWR[21]), .QN(n4661) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n1137), .CK(clk), .RN(n4728), .Q(
DmP_mant_SFG_SWR[19]), .QN(n4649) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n1133), .CK(clk), .RN(n4729), .Q(
DmP_mant_SFG_SWR[23]), .QN(n4648) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n1131), .CK(clk), .RN(n4729), .Q(
DmP_mant_SFG_SWR[25]), .QN(n4647) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_35_ ( .D(n1121), .CK(clk), .RN(n4730), .Q(
DmP_mant_SFG_SWR[35]), .QN(n4644) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n1132), .CK(clk), .RN(n4729), .Q(
DmP_mant_SFG_SWR[24]), .QN(n4634) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_30_ ( .D(n1126), .CK(clk), .RN(n4729), .Q(
DmP_mant_SFG_SWR[30]), .QN(n4631) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_34_ ( .D(n1784), .CK(clk), .RN(n4686),
.Q(intDY_EWSW[34]), .QN(n4597) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n1245), .CK(clk), .RN(n4741), .Q(
Raw_mant_NRM_SWR[24]), .QN(n4586) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n1268), .CK(clk), .RN(n4736), .Q(
Raw_mant_NRM_SWR[1]), .QN(n4571) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n1788), .CK(clk), .RN(n4686),
.Q(intDY_EWSW[30]), .QN(n4564) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n1806), .CK(clk), .RN(n4684),
.Q(intDY_EWSW[12]), .QN(n4556) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n1810), .CK(clk), .RN(n4684),
.Q(intDY_EWSW[8]), .QN(n4555) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_27_ ( .D(n1129), .CK(clk), .RN(n4729), .Q(
DmP_mant_SFG_SWR[27]), .QN(n4549) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_49_ ( .D(n1769), .CK(clk), .RN(n4688),
.Q(intDY_EWSW[49]), .QN(n4517) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n1807), .CK(clk), .RN(n4684),
.Q(intDY_EWSW[11]), .QN(n4516) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_44_ ( .D(n1839), .CK(clk), .RN(n4681),
.Q(intDX_EWSW[44]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_13_ ( .D(n1214), .CK(clk), .RN(n2709),
.Q(LZD_output_NRM2_EW[2]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n1257), .CK(clk), .RN(n4740), .Q(
Raw_mant_NRM_SWR[12]), .QN(n4574) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_23_ ( .D(n1351), .CK(clk), .RN(n4738),
.Q(DmP_mant_SHT1_SW[23]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n1590), .CK(clk), .RN(n4746), .Q(
DMP_SHT2_EWSW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n1530), .CK(clk), .RN(n4750), .Q(
DMP_SHT2_EWSW[26]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_22_ ( .D(n1354), .CK(clk), .RN(n4711), .Q(
DmP_EXP_EWSW[22]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n1815), .CK(clk), .RN(n4683),
.Q(intDY_EWSW[3]), .QN(n4496) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_48_ ( .D(n1221), .CK(clk), .RN(n4743), .Q(
Raw_mant_NRM_SWR[48]) );
DFFRX2TS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n1210), .CK(clk), .RN(n2704),
.Q(LZD_output_NRM2_EW[0]) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n1147), .CK(clk), .RN(n4727), .Q(
DmP_mant_SFG_SWR[9]), .QN(n4651) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n1153), .CK(clk), .RN(n4727), .Q(
DmP_mant_SFG_SWR[3]), .QN(n4653) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n1148), .CK(clk), .RN(n4727), .Q(
DmP_mant_SFG_SWR[8]), .QN(n4636) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n1151), .CK(clk), .RN(n4727), .Q(
DmP_mant_SFG_SWR[5]), .QN(n1976) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n1149), .CK(clk), .RN(n4727), .Q(
DmP_mant_SFG_SWR[7]), .QN(n4652) );
DFFRX2TS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n1444), .CK(clk), .RN(n4725), .Q(
DMP_exp_NRM2_EW[1]) );
DFFRX2TS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n1439), .CK(clk), .RN(n4725), .Q(
DMP_exp_NRM2_EW[2]) );
DFFRX2TS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n1434), .CK(clk), .RN(n4725), .Q(
DMP_exp_NRM2_EW[3]) );
DFFRX2TS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n1429), .CK(clk), .RN(n4725), .Q(
DMP_exp_NRM2_EW[4]) );
DFFRX2TS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n1424), .CK(clk), .RN(n4725), .Q(
DMP_exp_NRM2_EW[5]) );
DFFRX2TS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n1419), .CK(clk), .RN(n4726), .Q(
DMP_exp_NRM2_EW[6]) );
DFFRX2TS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n1414), .CK(clk), .RN(n4726), .Q(
DMP_exp_NRM2_EW[7]) );
DFFRX2TS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n1409), .CK(clk), .RN(n4726), .Q(
DMP_exp_NRM2_EW[8]) );
DFFRX2TS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n1404), .CK(clk), .RN(n4726), .Q(
DMP_exp_NRM2_EW[9]) );
DFFRX2TS NRM_STAGE_FLAGS_Q_reg_2_ ( .D(n1277), .CK(clk), .RN(n4726), .Q(
ADD_OVRFLW_NRM) );
DFFRX2TS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n1399), .CK(clk), .RN(n4726),
.Q(DMP_exp_NRM2_EW[10]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_51_ ( .D(n1749), .CK(clk), .RN(n4734), .Q(
Data_array_SWR[50]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_46_ ( .D(n1744), .CK(clk), .RN(n4734), .Q(
Data_array_SWR[45]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n1702), .CK(clk), .RN(n4726), .Q(
Data_array_SWR[4]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n1698), .CK(clk), .RN(n4726), .Q(
Data_array_SWR[0]) );
OAI211X1TS U1897 ( .A0(n3394), .A1(n3584), .B0(n3393), .C0(n3392), .Y(n1710)
);
OAI211X1TS U1898 ( .A0(n3399), .A1(n3584), .B0(n3370), .C0(n3369), .Y(n1742)
);
OAI211X1TS U1899 ( .A0(n3428), .A1(n3584), .B0(n3427), .C0(n3426), .Y(n1714)
);
AOI222X1TS U1900 ( .A0(n4370), .A1(n2785), .B0(Shift_amount_SHT1_EWR[5]),
.B1(n2806), .C0(shift_value_SHT2_EWR[5]), .C1(n2784), .Y(n2786) );
BUFX3TS U1901 ( .A(n3039), .Y(n3051) );
BUFX6TS U1902 ( .A(n3039), .Y(n3047) );
BUFX6TS U1903 ( .A(n2950), .Y(n3049) );
AOI222X4TS U1904 ( .A0(n2958), .A1(Data_array_SWR[32]), .B0(n2938), .B1(
Data_array_SWR[28]), .C0(n3653), .C1(Data_array_SWR[24]), .Y(n2974) );
AOI222X4TS U1905 ( .A0(n2939), .A1(Data_array_SWR[31]), .B0(n2938), .B1(
Data_array_SWR[27]), .C0(n3653), .C1(Data_array_SWR[23]), .Y(n2953) );
CLKBUFX2TS U1906 ( .A(n2314), .Y(n2914) );
BUFX4TS U1907 ( .A(n2892), .Y(n2931) );
BUFX3TS U1908 ( .A(n4477), .Y(n4286) );
AND2X2TS U1909 ( .A(n3697), .B(Shift_reg_FLAGS_7[3]), .Y(n4477) );
BUFX3TS U1910 ( .A(n2955), .Y(n3697) );
CLKBUFX2TS U1911 ( .A(n2310), .Y(n2928) );
INVX2TS U1912 ( .A(n1925), .Y(n1926) );
INVX2TS U1913 ( .A(n4675), .Y(n2955) );
BUFX3TS U1914 ( .A(Shift_reg_FLAGS_7[0]), .Y(n4675) );
OAI2BB2XLTS U1915 ( .B0(n2164), .B1(n2160), .A0N(n2159), .A1N(n2158), .Y(
n2161) );
INVX2TS U1916 ( .A(n3695), .Y(n4479) );
NOR2X1TS U1917 ( .A(n2606), .B(n2365), .Y(n2366) );
OAI2BB2XLTS U1918 ( .B0(intDX_EWSW[30]), .B1(n2231), .A0N(intDY_EWSW[31]),
.A1N(n1981), .Y(n2232) );
OAI2BB2XLTS U1919 ( .B0(intDX_EWSW[28]), .B1(n2225), .A0N(intDY_EWSW[29]),
.A1N(n1991), .Y(n2234) );
CLKBUFX2TS U1920 ( .A(Shift_reg_FLAGS_7[1]), .Y(n4468) );
NOR2X1TS U1921 ( .A(n2536), .B(n2535), .Y(n2778) );
NAND2X2TS U1922 ( .A(n2472), .B(n4505), .Y(n2774) );
NAND2XLTS U1923 ( .A(n2439), .B(n2055), .Y(n2057) );
NOR2X1TS U1924 ( .A(n3876), .B(n2073), .Y(n2075) );
NAND2X1TS U1925 ( .A(n2813), .B(n2135), .Y(n2137) );
NOR2X1TS U1926 ( .A(n3900), .B(n2061), .Y(n2063) );
NOR2X1TS U1927 ( .A(n3997), .B(n2029), .Y(n2031) );
NOR2X1TS U1928 ( .A(n4107), .B(n2013), .Y(n2015) );
NOR2X1TS U1929 ( .A(n3802), .B(n3815), .Y(n2813) );
NOR2X1TS U1930 ( .A(n4080), .B(n2019), .Y(n2021) );
AOI21X1TS U1931 ( .A0(n4210), .A1(n2102), .B0(n2101), .Y(n4130) );
NOR2X1TS U1932 ( .A(n4112), .B(n4192), .Y(n2108) );
XOR2X1TS U1933 ( .A(DP_OP_15J155_122_2221_n35), .B(n2333), .Y(n2338) );
NOR2X2TS U1934 ( .A(Raw_mant_NRM_SWR[54]), .B(Raw_mant_NRM_SWR[53]), .Y(
n2510) );
NOR3XLTS U1935 ( .A(Raw_mant_NRM_SWR[46]), .B(Raw_mant_NRM_SWR[45]), .C(
n4590), .Y(n2509) );
INVX2TS U1936 ( .A(n2496), .Y(n2497) );
NOR2X1TS U1937 ( .A(n3954), .B(n3915), .Y(n2123) );
NOR2X1TS U1938 ( .A(n3953), .B(n2043), .Y(n2045) );
OAI21X1TS U1939 ( .A0(n2717), .A1(n4168), .B0(n2718), .Y(n4116) );
NOR2XLTS U1940 ( .A(n2411), .B(n2112), .Y(n2114) );
OAI211XLTS U1941 ( .A0(n1963), .A1(intDY_EWSW[33]), .B0(n2301), .C0(n2300),
.Y(n2302) );
NOR2X4TS U1942 ( .A(n4506), .B(n4570), .Y(n2405) );
AOI21X1TS U1943 ( .A0(n2576), .A1(n2139), .B0(n2138), .Y(n3847) );
OAI21X2TS U1944 ( .A0(n3862), .A1(n3856), .B0(n3857), .Y(n3871) );
NOR2XLTS U1945 ( .A(n3439), .B(n2692), .Y(n2693) );
OR2X1TS U1946 ( .A(ADD_OVRFLW_NRM2), .B(LZD_output_NRM2_EW[0]), .Y(n2335) );
AOI21X2TS U1947 ( .A0(n3764), .A1(n2091), .B0(n2090), .Y(n3773) );
NOR2XLTS U1948 ( .A(n3374), .B(n4619), .Y(n3150) );
NOR2X1TS U1949 ( .A(n2801), .B(n2518), .Y(n2519) );
CLKINVX6TS U1950 ( .A(n3616), .Y(n3590) );
AFHCINX2TS U1951 ( .CIN(n2344), .B(n2345), .A(DMP_exp_NRM2_EW[3]), .S(n2356),
.CO(n2342) );
OAI21XLTS U1952 ( .A0(n3677), .A1(n4325), .B0(n3686), .Y(n3678) );
INVX2TS U1953 ( .A(n4466), .Y(n2310) );
CLKINVX3TS U1954 ( .A(ADD_OVRFLW_NRM2), .Y(n1918) );
INVX4TS U1955 ( .A(n2397), .Y(n3693) );
INVX2TS U1956 ( .A(n4396), .Y(n4395) );
BUFX3TS U1957 ( .A(n2314), .Y(n2930) );
CLKINVX3TS U1958 ( .A(n1995), .Y(n3459) );
OAI211XLTS U1959 ( .A0(n3222), .A1(n3459), .B0(n3221), .C0(n3220), .Y(n1733)
);
OAI211XLTS U1960 ( .A0(n3560), .A1(n3607), .B0(n3287), .C0(n3286), .Y(n1704)
);
OAI211XLTS U1961 ( .A0(n3321), .A1(n3607), .B0(n3320), .C0(n3319), .Y(n1708)
);
OAI211XLTS U1962 ( .A0(n3343), .A1(n3459), .B0(n3342), .C0(n3341), .Y(n1749)
);
OAI211XLTS U1963 ( .A0(n3422), .A1(n3584), .B0(n3421), .C0(n3420), .Y(n1718)
);
OAI211XLTS U1964 ( .A0(n3559), .A1(n3459), .B0(n3297), .C0(n3296), .Y(n1702)
);
OAI211XLTS U1965 ( .A0(n3570), .A1(n3594), .B0(n3569), .C0(n3568), .Y(n1707)
);
OAI211XLTS U1966 ( .A0(n3388), .A1(n3607), .B0(n3387), .C0(n3386), .Y(n1716)
);
OAI211XLTS U1967 ( .A0(n3391), .A1(n3418), .B0(n3390), .C0(n3389), .Y(n1726)
);
OAI211XLTS U1968 ( .A0(n3199), .A1(n3584), .B0(n3198), .C0(n3197), .Y(n1746)
);
OAI21XLTS U1969 ( .A0(n3625), .A1(n3047), .B0(n3018), .Y(n1200) );
OAI211XLTS U1970 ( .A0(n2810), .A1(n2809), .B0(n2808), .C0(n2807), .Y(n1695)
);
OAI21XLTS U1971 ( .A0(n4527), .A1(n3092), .B0(n2925), .Y(n1308) );
OAI21XLTS U1972 ( .A0(n4596), .A1(n3089), .B0(n3088), .Y(n1322) );
OAI21XLTS U1973 ( .A0(n4502), .A1(n3089), .B0(n2915), .Y(n1336) );
OAI21XLTS U1974 ( .A0(n4499), .A1(n3068), .B0(n3061), .Y(n1356) );
OAI21XLTS U1975 ( .A0(n4557), .A1(n3068), .B0(n2895), .Y(n1370) );
OAI21XLTS U1976 ( .A0(n4508), .A1(n3128), .B0(n3127), .Y(n1384) );
OAI21XLTS U1977 ( .A0(n4490), .A1(n3546), .B0(n2913), .Y(n1398) );
OAI21XLTS U1978 ( .A0(n4603), .A1(n3146), .B0(n3145), .Y(n1624) );
OAI21XLTS U1979 ( .A0(n4596), .A1(n3121), .B0(n3120), .Y(n1637) );
OAI21XLTS U1980 ( .A0(n4516), .A1(n3104), .B0(n2927), .Y(n1664) );
OAI211XLTS U1981 ( .A0(n3356), .A1(n3459), .B0(n3355), .C0(n3354), .Y(n1732)
);
OAI211XLTS U1982 ( .A0(n3304), .A1(n3584), .B0(n3303), .C0(n3302), .Y(n1706)
);
OAI211X1TS U1983 ( .A0(n3444), .A1(n3584), .B0(n3443), .C0(n3442), .Y(n1738)
);
OAI211X1TS U1984 ( .A0(n3452), .A1(n3459), .B0(n3451), .C0(n3450), .Y(n1741)
);
OAI211X1TS U1985 ( .A0(n3460), .A1(n3459), .B0(n3458), .C0(n3457), .Y(n1740)
);
OAI211X1TS U1986 ( .A0(n3585), .A1(n3584), .B0(n3583), .C0(n3582), .Y(n1715)
);
OAI21X1TS U1987 ( .A0(n3343), .A1(n3158), .B0(n2904), .Y(n1751) );
OAI211X1TS U1988 ( .A0(n3595), .A1(n3594), .B0(n3593), .C0(n3592), .Y(n1719)
);
OAI211X1TS U1989 ( .A0(n3403), .A1(n3607), .B0(n3402), .C0(n3401), .Y(n1743)
);
OAI211X1TS U1990 ( .A0(n3564), .A1(n3594), .B0(n3563), .C0(n3562), .Y(n1703)
);
OAI211X1TS U1991 ( .A0(n3332), .A1(n3594), .B0(n3331), .C0(n3330), .Y(n1731)
);
OAI211X1TS U1992 ( .A0(n3266), .A1(n3594), .B0(n3265), .C0(n3264), .Y(n1735)
);
OAI21X1TS U1993 ( .A0(n1935), .A1(n3039), .B0(n2975), .Y(n1203) );
OAI21X1TS U1994 ( .A0(n3621), .A1(n3047), .B0(n3046), .Y(n1202) );
OAI21X1TS U1995 ( .A0(n3626), .A1(n3039), .B0(n2954), .Y(n1201) );
OAI21X1TS U1996 ( .A0(n3629), .A1(n3047), .B0(n3032), .Y(n1192) );
OAI21X1TS U1997 ( .A0(n3051), .A1(n3628), .B0(n3020), .Y(n1177) );
OAI21X1TS U1998 ( .A0(n1936), .A1(n3039), .B0(n3036), .Y(n1161) );
OAI21X1TS U1999 ( .A0(n3627), .A1(n3047), .B0(n2994), .Y(n1176) );
OAI21X1TS U2000 ( .A0(n3619), .A1(n3047), .B0(n2966), .Y(n1206) );
OAI21X1TS U2001 ( .A0(n3632), .A1(n3051), .B0(n2877), .Y(n1160) );
OAI21X1TS U2002 ( .A0(n3633), .A1(n3051), .B0(n2890), .Y(n1168) );
OAI21X1TS U2003 ( .A0(n3051), .A1(n3639), .B0(n3013), .Y(n1175) );
OAI21X1TS U2004 ( .A0(n3620), .A1(n3047), .B0(n3034), .Y(n1207) );
OAI21X1TS U2005 ( .A0(n3051), .A1(n3644), .B0(n2957), .Y(n1173) );
OAI21X1TS U2006 ( .A0(n3647), .A1(n3051), .B0(n3050), .Y(n1159) );
OAI21X1TS U2007 ( .A0(n3642), .A1(n3047), .B0(n2946), .Y(n1172) );
OAI21X1TS U2008 ( .A0(n3638), .A1(n3047), .B0(n3042), .Y(n1174) );
OAI21X1TS U2009 ( .A0(n3635), .A1(n3051), .B0(n2884), .Y(n1170) );
OAI21X1TS U2010 ( .A0(n3622), .A1(n3047), .B0(n3002), .Y(n1204) );
OAI21X1TS U2011 ( .A0(n3646), .A1(n3051), .B0(n2864), .Y(n1158) );
OAI21X1TS U2012 ( .A0(n2732), .A1(n3047), .B0(n2370), .Y(n1157) );
OAI21X1TS U2013 ( .A0(n3051), .A1(n3636), .B0(n2968), .Y(n1171) );
OAI21X1TS U2014 ( .A0(n3630), .A1(n3039), .B0(n3038), .Y(n1193) );
OAI21X1TS U2015 ( .A0(n3623), .A1(n3039), .B0(n3015), .Y(n1205) );
OAI211X1TS U2016 ( .A0(n3616), .A1(n3233), .B0(n3157), .C0(n2570), .Y(n2571)
);
NAND2X6TS U2017 ( .A(n3164), .B(n2695), .Y(n3558) );
BUFX12TS U2018 ( .A(n2950), .Y(n3045) );
OAI21X1TS U2019 ( .A0(n3158), .A1(n3339), .B0(n2832), .Y(n1752) );
INVX3TS U2020 ( .A(n1995), .Y(n3418) );
INVX3TS U2021 ( .A(n1995), .Y(n3607) );
AO22XLTS U2022 ( .A0(n4385), .A1(n4288), .B0(final_result_ieee[34]), .B1(
n4383), .Y(n1190) );
INVX12TS U2023 ( .A(n3174), .Y(n2695) );
AO22XLTS U2024 ( .A0(n4381), .A1(n4328), .B0(final_result_ieee[15]), .B1(
n4377), .Y(n1189) );
OAI2BB1X2TS U2025 ( .A0N(n2148), .A1N(n3979), .B0(n2147), .Y(n1215) );
AO22XLTS U2026 ( .A0(n4385), .A1(n4287), .B0(final_result_ieee[35]), .B1(
n4383), .Y(n1188) );
NOR2X6TS U2027 ( .A(n3693), .B(n1929), .Y(n2950) );
AO22XLTS U2028 ( .A0(n4385), .A1(n4327), .B0(final_result_ieee[16]), .B1(
n4383), .Y(n1191) );
BUFX6TS U2029 ( .A(n2397), .Y(n4390) );
INVX4TS U2030 ( .A(n3680), .Y(n2397) );
NAND2X2TS U2031 ( .A(n2563), .B(n4369), .Y(n4373) );
OAI21X1TS U2032 ( .A0(n2803), .A1(n4374), .B0(n2802), .Y(n1211) );
XNOR2X1TS U2033 ( .A(n3133), .B(n3132), .Y(n3138) );
OAI21X1TS U2034 ( .A0(n2752), .A1(n2520), .B0(n2751), .Y(n1697) );
OAI21X1TS U2035 ( .A0(n2752), .A1(n3382), .B0(n2750), .Y(n1214) );
OAI21X1TS U2036 ( .A0(n4568), .A1(n3546), .B0(n2902), .Y(n1614) );
OAI21X1TS U2037 ( .A0(n4504), .A1(n3546), .B0(n2905), .Y(n1613) );
OAI21X1TS U2038 ( .A0(n4581), .A1(n3146), .B0(n3139), .Y(n1625) );
OAI21X1TS U2039 ( .A0(n4602), .A1(n3146), .B0(n3141), .Y(n1629) );
OAI21X1TS U2040 ( .A0(n4524), .A1(n3546), .B0(n2906), .Y(n1616) );
OAI21X1TS U2041 ( .A0(n4600), .A1(n3121), .B0(n3109), .Y(n1633) );
OAI21X1TS U2042 ( .A0(n4601), .A1(n3146), .B0(n3123), .Y(n1631) );
OAI21X1TS U2043 ( .A0(n4514), .A1(n3121), .B0(n3112), .Y(n1634) );
OAI21X1TS U2044 ( .A0(n4582), .A1(n4465), .B0(n3149), .Y(n1617) );
OAI21X1TS U2045 ( .A0(n4528), .A1(n3146), .B0(n3143), .Y(n1628) );
OAI21X1TS U2046 ( .A0(n4599), .A1(n3121), .B0(n3114), .Y(n1635) );
OAI21X1TS U2047 ( .A0(n4566), .A1(n3146), .B0(n3142), .Y(n1627) );
OAI21X1TS U2048 ( .A0(n4527), .A1(n3146), .B0(n3055), .Y(n1630) );
OAI21X1TS U2049 ( .A0(n4603), .A1(n4465), .B0(n2318), .Y(n1296) );
OAI21X1TS U2050 ( .A0(n4515), .A1(n3146), .B0(n3053), .Y(n1632) );
OAI21X1TS U2051 ( .A0(n4517), .A1(n3146), .B0(n2903), .Y(n1626) );
OAI21X1TS U2052 ( .A0(n4583), .A1(n3546), .B0(n2910), .Y(n1615) );
OAI21X1TS U2053 ( .A0(n4526), .A1(n3121), .B0(n2901), .Y(n1636) );
OAI21X1TS U2054 ( .A0(n4602), .A1(n3092), .B0(n2316), .Y(n1306) );
OAI21X1TS U2055 ( .A0(n4491), .A1(n3128), .B0(n3060), .Y(n1380) );
OAI21X1TS U2056 ( .A0(n4579), .A1(n3128), .B0(n3065), .Y(n1386) );
OAI21X1TS U2057 ( .A0(n4496), .A1(n3104), .B0(n2849), .Y(n1672) );
OAI21X1TS U2058 ( .A0(n4509), .A1(n3128), .B0(n3124), .Y(n1388) );
OAI21X1TS U2059 ( .A0(n4509), .A1(n3104), .B0(n2313), .Y(n1670) );
OAI21X1TS U2060 ( .A0(n4507), .A1(n3128), .B0(n3064), .Y(n1378) );
OAI21X1TS U2061 ( .A0(n4516), .A1(n3128), .B0(n2909), .Y(n1376) );
OAI21X1TS U2062 ( .A0(n4554), .A1(n3128), .B0(n3075), .Y(n1390) );
OAI21X1TS U2063 ( .A0(n4555), .A1(n3128), .B0(n2908), .Y(n1382) );
OAI21X1TS U2064 ( .A0(n4556), .A1(n3068), .B0(n3056), .Y(n1374) );
OAI21X1TS U2065 ( .A0(n4512), .A1(n3121), .B0(n3052), .Y(n1642) );
OAI21X1TS U2066 ( .A0(n4496), .A1(n3128), .B0(n2894), .Y(n1392) );
OAI21X1TS U2067 ( .A0(n4497), .A1(n3068), .B0(n3062), .Y(n1372) );
OAI21X1TS U2068 ( .A0(n4597), .A1(n3121), .B0(n3101), .Y(n1641) );
OAI21X1TS U2069 ( .A0(n4553), .A1(n3128), .B0(n3069), .Y(n1394) );
OAI21X1TS U2070 ( .A0(n4579), .A1(n3104), .B0(n2851), .Y(n1669) );
OAI21X1TS U2071 ( .A0(n4595), .A1(n3546), .B0(n2897), .Y(n1396) );
OAI21X1TS U2072 ( .A0(n4600), .A1(n3092), .B0(n3081), .Y(n1314) );
OAI21X1TS U2073 ( .A0(n4498), .A1(n3068), .B0(n2893), .Y(n1368) );
OAI21X1TS U2074 ( .A0(n4525), .A1(n3089), .B0(n3085), .Y(n1324) );
OAI21X1TS U2075 ( .A0(n4578), .A1(n3068), .B0(n3067), .Y(n1366) );
OAI21X1TS U2076 ( .A0(n4490), .A1(n3146), .B0(n3140), .Y(n1675) );
OAI21X1TS U2077 ( .A0(n4599), .A1(n3089), .B0(n3083), .Y(n1318) );
OAI21X1TS U2078 ( .A0(n4492), .A1(n3068), .B0(n2912), .Y(n1364) );
OAI21X1TS U2079 ( .A0(n4501), .A1(n3080), .B0(n2315), .Y(n1340) );
OAI21X1TS U2080 ( .A0(n4495), .A1(n3080), .B0(n3079), .Y(n1344) );
OAI21X1TS U2081 ( .A0(n4526), .A1(n3089), .B0(n2899), .Y(n1320) );
OAI21X1TS U2082 ( .A0(n4598), .A1(n3121), .B0(n2937), .Y(n1639) );
OAI21X1TS U2083 ( .A0(n4559), .A1(n3068), .B0(n3059), .Y(n1358) );
OAI21X1TS U2084 ( .A0(n4513), .A1(n3121), .B0(n3054), .Y(n1640) );
OAI21X1TS U2085 ( .A0(n4503), .A1(n4467), .B0(n2850), .Y(n1618) );
OAI21X1TS U2086 ( .A0(n4563), .A1(n3080), .B0(n3071), .Y(n1342) );
OAI21X1TS U2087 ( .A0(n4554), .A1(n3104), .B0(n2853), .Y(n1671) );
OAI21X1TS U2088 ( .A0(n4493), .A1(n3068), .B0(n3063), .Y(n1360) );
OAI21X1TS U2089 ( .A0(n4508), .A1(n3104), .B0(n2312), .Y(n1668) );
OAI21X1TS U2090 ( .A0(n4558), .A1(n3068), .B0(n2911), .Y(n1362) );
OAI21X1TS U2091 ( .A0(n4515), .A1(n3092), .B0(n2921), .Y(n1312) );
OAI21X1TS U2092 ( .A0(n4562), .A1(n3080), .B0(n2917), .Y(n1346) );
OAI21X1TS U2093 ( .A0(n4601), .A1(n3092), .B0(n3091), .Y(n1310) );
OAI21X1TS U2094 ( .A0(n4525), .A1(n3121), .B0(n3118), .Y(n1638) );
OAI21X1TS U2095 ( .A0(n4564), .A1(n3080), .B0(n3070), .Y(n1338) );
OAI21X1TS U2096 ( .A0(n4560), .A1(n3117), .B0(n3097), .Y(n1653) );
OAI21X1TS U2097 ( .A0(n4491), .A1(n3104), .B0(n3099), .Y(n1666) );
OAI21X1TS U2098 ( .A0(n4555), .A1(n3104), .B0(n2926), .Y(n1667) );
OAI21X1TS U2099 ( .A0(n4497), .A1(n3104), .B0(n3103), .Y(n1662) );
OAI21X1TS U2100 ( .A0(n4556), .A1(n3104), .B0(n3093), .Y(n1663) );
OAI21X1TS U2101 ( .A0(n4499), .A1(n3117), .B0(n3105), .Y(n1654) );
INVX4TS U2102 ( .A(n3144), .Y(n4465) );
OAI21X1TS U2103 ( .A0(n4578), .A1(n3117), .B0(n3116), .Y(n1659) );
OAI21X1TS U2104 ( .A0(n4498), .A1(n3117), .B0(n2898), .Y(n1660) );
OAI21X1TS U2105 ( .A0(n4493), .A1(n3117), .B0(n3108), .Y(n1656) );
OAI21X1TS U2106 ( .A0(n4492), .A1(n3117), .B0(n2935), .Y(n1658) );
OAI21X1TS U2107 ( .A0(n4558), .A1(n3117), .B0(n2934), .Y(n1657) );
OAI21X1TS U2108 ( .A0(n4559), .A1(n3117), .B0(n3096), .Y(n1655) );
OAI21X1TS U2109 ( .A0(n4557), .A1(n3117), .B0(n2900), .Y(n1661) );
OAI21X1TS U2110 ( .A0(n4500), .A1(n3117), .B0(n2929), .Y(n1652) );
INVX3TS U2111 ( .A(n2930), .Y(n3126) );
INVX3TS U2112 ( .A(n2930), .Y(n3148) );
BUFX6TS U2113 ( .A(n2931), .Y(n3057) );
INVX3TS U2114 ( .A(n2896), .Y(n3128) );
INVX3TS U2115 ( .A(n2930), .Y(n3066) );
INVX3TS U2116 ( .A(n2914), .Y(n3087) );
INVX3TS U2117 ( .A(n2914), .Y(n3078) );
INVX3TS U2118 ( .A(n2914), .Y(n3090) );
INVX3TS U2119 ( .A(n2896), .Y(n3068) );
INVX2TS U2120 ( .A(n2931), .Y(n3080) );
NAND3X1TS U2121 ( .A(n2558), .B(Raw_mant_NRM_SWR[11]), .C(n4574), .Y(n2559)
);
NOR2X1TS U2122 ( .A(n2446), .B(n2359), .Y(n2364) );
NAND2BX1TS U2123 ( .AN(n2349), .B(n2446), .Y(n2350) );
OAI21X1TS U2124 ( .A0(n2732), .A1(n3670), .B0(n2729), .Y(n1103) );
OAI21X1TS U2125 ( .A0(n2732), .A1(n3668), .B0(n2731), .Y(n1155) );
NAND3BX1TS U2126 ( .AN(n2346), .B(n2445), .C(n2356), .Y(n2349) );
NAND3X1TS U2127 ( .A(n2538), .B(Raw_mant_NRM_SWR[37]), .C(n4616), .Y(n2539)
);
OAI21X2TS U2128 ( .A0(n3618), .A1(n4630), .B0(n3173), .Y(n1904) );
OR2X6TS U2129 ( .A(n2131), .B(n2130), .Y(n2574) );
OAI21X1TS U2130 ( .A0(n3682), .A1(n4325), .B0(n3686), .Y(n3683) );
NAND3X1TS U2131 ( .A(n2514), .B(n2523), .C(n2513), .Y(n2515) );
INVX2TS U2132 ( .A(n4452), .Y(n3698) );
AND3X1TS U2133 ( .A(n2690), .B(n4468), .C(n2689), .Y(n3339) );
INVX2TS U2134 ( .A(n4452), .Y(n3702) );
AOI211X2TS U2135 ( .A0(n3649), .A1(n3030), .B0(n3029), .C0(n1917), .Y(n3630)
);
NAND3X1TS U2136 ( .A(n4301), .B(n1908), .C(n4300), .Y(n4380) );
INVX2TS U2137 ( .A(n4452), .Y(n3699) );
INVX2TS U2138 ( .A(n4452), .Y(n4449) );
AO22XLTS U2139 ( .A0(n4429), .A1(add_subt), .B0(n4427), .B1(intAS), .Y(n1819) );
INVX1TS U2140 ( .A(n3681), .Y(n3682) );
INVX3TS U2141 ( .A(n4286), .Y(n4342) );
NAND3X1TS U2142 ( .A(n2357), .B(n2447), .C(n2448), .Y(n2346) );
INVX1TS U2143 ( .A(n3672), .Y(n3673) );
INVX1TS U2144 ( .A(n3676), .Y(n3677) );
NOR2X2TS U2145 ( .A(n2115), .B(n2371), .Y(n2131) );
AND2X2TS U2146 ( .A(n4286), .B(n1927), .Y(n3624) );
INVX1TS U2147 ( .A(n3685), .Y(n3687) );
NOR2X1TS U2148 ( .A(n3028), .B(n3659), .Y(n3029) );
AND2X2TS U2149 ( .A(n4286), .B(n1928), .Y(n3631) );
INVX3TS U2150 ( .A(n4286), .Y(n4349) );
AOI21X1TS U2151 ( .A0(n2438), .A1(n2055), .B0(n2054), .Y(n2056) );
INVX3TS U2152 ( .A(n2520), .Y(n3380) );
OAI211X2TS U2153 ( .A0(n2866), .A1(n4608), .B0(n2645), .C0(n2609), .Y(n2949)
);
INVX3TS U2154 ( .A(n2520), .Y(n3361) );
OAI21X1TS U2155 ( .A0(n2178), .A1(n2177), .B0(n2176), .Y(n2180) );
NOR2X1TS U2156 ( .A(n3365), .B(n4620), .Y(n2566) );
AOI211X1TS U2157 ( .A0(n2235), .A1(n2234), .B0(n2233), .C0(n2232), .Y(n2299)
);
INVX3TS U2158 ( .A(n2520), .Y(n3430) );
OAI211X2TS U2159 ( .A0(n2658), .A1(n4610), .B0(n2401), .C0(n2986), .Y(n3000)
);
BUFX3TS U2160 ( .A(n4418), .Y(n4414) );
INVX3TS U2161 ( .A(n1899), .Y(n3439) );
OAI21X2TS U2162 ( .A0(n3779), .A1(n2071), .B0(n2070), .Y(n2824) );
INVX3TS U2163 ( .A(n1899), .Y(n3611) );
NOR2X1TS U2164 ( .A(n2207), .B(n2206), .Y(n2221) );
OAI211X1TS U2165 ( .A0(intDX_EWSW[61]), .A1(n1992), .B0(n2157), .C0(n2156),
.Y(n2158) );
CLKINVX2TS U2166 ( .A(n3787), .Y(n3788) );
NOR2X1TS U2167 ( .A(n2477), .B(n2484), .Y(n2479) );
OR2X2TS U2168 ( .A(n3696), .B(ADD_OVRFLW_NRM), .Y(n2520) );
AND2X4TS U2169 ( .A(beg_OP), .B(n4400), .Y(n4418) );
AOI211X1TS U2170 ( .A0(intDX_EWSW[16]), .A1(n2273), .B0(n2280), .C0(n2286),
.Y(n2275) );
INVX3TS U2171 ( .A(n4472), .Y(n4441) );
INVX2TS U2172 ( .A(n4472), .Y(n3701) );
AOI211X1TS U2173 ( .A0(intDX_EWSW[52]), .A1(n4518), .B0(n2162), .C0(n2206),
.Y(n2208) );
INVX3TS U2174 ( .A(n2658), .Y(n2981) );
OAI211X2TS U2175 ( .A0(intDY_EWSW[20]), .A1(n1962), .B0(n2291), .C0(n2274),
.Y(n2285) );
NAND3X1TS U2176 ( .A(n2155), .B(n2154), .C(intDY_EWSW[60]), .Y(n2156) );
OAI211X2TS U2177 ( .A0(intDY_EWSW[28]), .A1(n1986), .B0(n2235), .C0(n2226),
.Y(n2294) );
NOR2X1TS U2178 ( .A(n2521), .B(Raw_mant_NRM_SWR[9]), .Y(n2527) );
INVX3TS U2179 ( .A(n2866), .Y(n2982) );
OAI211X2TS U2180 ( .A0(intDY_EWSW[12]), .A1(n1961), .B0(n2272), .C0(n2252),
.Y(n2266) );
CLKXOR2X2TS U2181 ( .A(DP_OP_15J155_122_2221_n35), .B(n2335), .Y(n2339) );
INVX2TS U2182 ( .A(n3828), .Y(n3831) );
INVX2TS U2183 ( .A(n3900), .Y(n3903) );
INVX3TS U2184 ( .A(n4468), .Y(n3696) );
NAND2BX1TS U2185 ( .AN(intDX_EWSW[62]), .B(intDY_EWSW[62]), .Y(n2157) );
INVX1TS U2186 ( .A(Shift_reg_FLAGS_7[2]), .Y(n3695) );
NOR2X1TS U2187 ( .A(Raw_mant_NRM_SWR[23]), .B(Raw_mant_NRM_SWR[21]), .Y(
n2465) );
NOR2X1TS U2188 ( .A(Raw_mant_NRM_SWR[19]), .B(Raw_mant_NRM_SWR[22]), .Y(
n2463) );
NOR2X1TS U2189 ( .A(Raw_mant_NRM_SWR[24]), .B(Raw_mant_NRM_SWR[20]), .Y(
n2464) );
NAND2BX1TS U2190 ( .AN(intDY_EWSW[51]), .B(intDX_EWSW[51]), .Y(n2211) );
NAND2BX1TS U2191 ( .AN(intDY_EWSW[29]), .B(intDX_EWSW[29]), .Y(n2226) );
NAND2BX1TS U2192 ( .AN(intDY_EWSW[32]), .B(intDX_EWSW[32]), .Y(n2301) );
NAND2BX1TS U2193 ( .AN(intDY_EWSW[59]), .B(intDX_EWSW[59]), .Y(n2150) );
INVX3TS U2194 ( .A(Shift_reg_FLAGS_7[1]), .Y(n3382) );
NAND2BX1TS U2195 ( .AN(intDY_EWSW[62]), .B(intDX_EWSW[62]), .Y(n2159) );
NOR2X1TS U2196 ( .A(Raw_mant_NRM_SWR[8]), .B(n4575), .Y(n2521) );
NAND2BX1TS U2197 ( .AN(intDY_EWSW[27]), .B(intDX_EWSW[27]), .Y(n2228) );
OR2X2TS U2198 ( .A(n4520), .B(n4612), .Y(n1908) );
INVX3TS U2199 ( .A(n4484), .Y(n4466) );
NAND2BX1TS U2200 ( .AN(intDY_EWSW[40]), .B(intDX_EWSW[40]), .Y(n2182) );
NAND2BX1TS U2201 ( .AN(intDY_EWSW[21]), .B(intDX_EWSW[21]), .Y(n2274) );
NAND2BX1TS U2202 ( .AN(intDY_EWSW[47]), .B(intDX_EWSW[47]), .Y(n2169) );
NAND2BX1TS U2203 ( .AN(intDY_EWSW[41]), .B(intDX_EWSW[41]), .Y(n2183) );
OAI21X1TS U2204 ( .A0(intDY_EWSW[31]), .A1(n1981), .B0(intDY_EWSW[30]), .Y(
n2231) );
OR2X4TS U2205 ( .A(shift_value_SHT2_EWR[4]), .B(shift_value_SHT2_EWR[5]),
.Y(n2323) );
NAND2BX1TS U2206 ( .AN(intDY_EWSW[19]), .B(intDX_EWSW[19]), .Y(n2282) );
OAI2BB1X2TS U2207 ( .A0N(n3979), .A1N(n3138), .B0(n3137), .Y(n1216) );
NOR2X2TS U2208 ( .A(n3980), .B(n2039), .Y(n2439) );
NOR3X4TS U2209 ( .A(Raw_mant_NRM_SWR[50]), .B(Raw_mant_NRM_SWR[49]), .C(
Raw_mant_NRM_SWR[48]), .Y(n2740) );
NAND2X4TS U2210 ( .A(n2744), .B(n2489), .Y(n2536) );
OAI21X2TS U2211 ( .A0(n4130), .A1(n2106), .B0(n2105), .Y(n2409) );
OAI21X2TS U2212 ( .A0(n3746), .A1(n3740), .B0(n3741), .Y(n3735) );
NOR2X2TS U2213 ( .A(n3780), .B(n2071), .Y(n2823) );
AFHCONX2TS U2214 ( .A(DMP_exp_NRM2_EW[4]), .B(n2343), .CI(n2342), .CON(n2347), .S(n2445) );
OAI21X1TS U2215 ( .A0(n3051), .A1(n3634), .B0(n3004), .Y(n1169) );
AOI21X4TS U2216 ( .A0(n3744), .A1(n2095), .B0(n2094), .Y(n3734) );
OAI21X2TS U2217 ( .A0(n3773), .A1(n2093), .B0(n2092), .Y(n3744) );
OAI21X2TS U2218 ( .A0(n3981), .A1(n2039), .B0(n2038), .Y(n2438) );
NAND2X4TS U2219 ( .A(n2510), .B(n2512), .Y(n2739) );
AND2X4TS U2220 ( .A(n2694), .B(n2693), .Y(n3164) );
OAI211X1TS U2221 ( .A0(n3412), .A1(n3459), .B0(n3411), .C0(n3410), .Y(n1737)
);
AOI21X4TS U2222 ( .A0(n3894), .A1(n2087), .B0(n2086), .Y(n3754) );
OAI21X2TS U2223 ( .A0(n4123), .A1(n2009), .B0(n2008), .Y(n2712) );
OAI21X2TS U2224 ( .A0(n3734), .A1(n2097), .B0(n2096), .Y(n3133) );
OAI21X1TS U2225 ( .A0(n3714), .A1(n2053), .B0(n2052), .Y(n2054) );
OAI21X2TS U2226 ( .A0(n3754), .A1(n2089), .B0(n2088), .Y(n3764) );
OAI21X4TS U2227 ( .A0(n3896), .A1(n3890), .B0(n3891), .Y(n3755) );
OAI21X4TS U2228 ( .A0(n3766), .A1(n3760), .B0(n3761), .Y(n3774) );
NAND2X2TS U2229 ( .A(n2593), .B(n2063), .Y(n3780) );
AOI21X4TS U2230 ( .A0(n3860), .A1(n2083), .B0(n2082), .Y(n3869) );
OAI21X2TS U2231 ( .A0(n3846), .A1(n2081), .B0(n2080), .Y(n3860) );
XOR2X4TS U2232 ( .A(n2100), .B(n4659), .Y(n2148) );
OAI211X1TS U2233 ( .A0(intDY_EWSW[36]), .A1(n1968), .B0(n2197), .C0(n2191),
.Y(n2304) );
OA22X1TS U2234 ( .A0(n1971), .A1(intDY_EWSW[42]), .B0(n1972), .B1(
intDY_EWSW[43]), .Y(n2184) );
CLKAND2X2TS U2235 ( .A(n4639), .B(DMP_SFG[49]), .Y(n2094) );
CLKAND2X2TS U2236 ( .A(n4640), .B(DMP_SFG[45]), .Y(n2086) );
NOR2X1TS U2237 ( .A(n1985), .B(intDY_EWSW[57]), .Y(n2165) );
OAI21XLTS U2238 ( .A0(Raw_mant_NRM_SWR[5]), .A1(n2542), .B0(n4569), .Y(n2548) );
NOR2XLTS U2239 ( .A(Raw_mant_NRM_SWR[4]), .B(n4576), .Y(n2542) );
INVX2TS U2240 ( .A(n4358), .Y(n3934) );
INVX2TS U2241 ( .A(n2371), .Y(n4027) );
CLKAND2X2TS U2242 ( .A(n4624), .B(DMP_SFG[51]), .Y(n2098) );
CLKAND2X2TS U2243 ( .A(n4613), .B(DMP_SFG[47]), .Y(n2090) );
CLKAND2X2TS U2244 ( .A(n4641), .B(DMP_SFG[43]), .Y(n2082) );
BUFX3TS U2245 ( .A(n2930), .Y(n4467) );
NAND2BXLTS U2246 ( .AN(intDY_EWSW[9]), .B(intDX_EWSW[9]), .Y(n2261) );
NOR2X1TS U2247 ( .A(n1989), .B(intDY_EWSW[11]), .Y(n2259) );
NAND2BXLTS U2248 ( .AN(intDY_EWSW[13]), .B(intDX_EWSW[13]), .Y(n2252) );
NAND3XLTS U2249 ( .A(n1950), .B(n2261), .C(intDY_EWSW[8]), .Y(n2263) );
NAND2BXLTS U2250 ( .AN(intDX_EWSW[9]), .B(intDY_EWSW[9]), .Y(n2262) );
NOR2BX1TS U2251 ( .AN(n2189), .B(n2188), .Y(n2194) );
OAI2BB2XLTS U2252 ( .B0(intDX_EWSW[32]), .B1(n2187), .A0N(intDY_EWSW[33]),
.A1N(n1963), .Y(n2189) );
OAI21XLTS U2253 ( .A0(intDY_EWSW[33]), .A1(n1963), .B0(intDY_EWSW[32]), .Y(
n2187) );
OAI2BB2XLTS U2254 ( .B0(intDX_EWSW[34]), .B1(n2190), .A0N(intDY_EWSW[35]),
.A1N(n1967), .Y(n2193) );
OAI21XLTS U2255 ( .A0(intDY_EWSW[35]), .A1(n1967), .B0(intDY_EWSW[34]), .Y(
n2190) );
NOR2X1TS U2256 ( .A(n3790), .B(n3782), .Y(n2133) );
NOR2X1TS U2257 ( .A(n4038), .B(n2434), .Y(n2119) );
NAND2X1TS U2258 ( .A(n2433), .B(n2119), .Y(n2121) );
NOR2X1TS U2259 ( .A(n4067), .B(n4061), .Y(n2117) );
OAI21XLTS U2260 ( .A0(n2418), .A1(n4084), .B0(n2419), .Y(n2109) );
OAI21XLTS U2261 ( .A0(n2019), .A1(n4081), .B0(n2018), .Y(n2020) );
OA22X1TS U2262 ( .A0(n1979), .A1(intDY_EWSW[30]), .B0(n1981), .B1(
intDY_EWSW[31]), .Y(n2235) );
AOI2BB2XLTS U2263 ( .B0(intDY_EWSW[53]), .B1(n2205), .A0N(intDX_EWSW[52]),
.A1N(n2204), .Y(n2207) );
OAI21XLTS U2264 ( .A0(intDY_EWSW[53]), .A1(n2205), .B0(intDY_EWSW[52]), .Y(
n2204) );
OAI21XLTS U2265 ( .A0(intDY_EWSW[55]), .A1(n2216), .B0(intDY_EWSW[54]), .Y(
n2217) );
OAI2BB2XLTS U2266 ( .B0(intDX_EWSW[42]), .B1(n2173), .A0N(intDY_EWSW[43]),
.A1N(n1972), .Y(n2174) );
OAI21XLTS U2267 ( .A0(intDY_EWSW[43]), .A1(n1972), .B0(intDY_EWSW[42]), .Y(
n2173) );
OAI21X1TS U2268 ( .A0(intDY_EWSW[50]), .A1(n1956), .B0(n2211), .Y(n2215) );
NOR2XLTS U2269 ( .A(n2165), .B(intDX_EWSW[56]), .Y(n2149) );
OR2X1TS U2270 ( .A(Raw_mant_NRM_SWR[48]), .B(Raw_mant_NRM_SWR[47]), .Y(n2508) );
NOR2XLTS U2271 ( .A(Raw_mant_NRM_SWR[50]), .B(Raw_mant_NRM_SWR[49]), .Y(
n2507) );
NAND2X1TS U2272 ( .A(n3810), .B(n2069), .Y(n2071) );
NAND2X1TS U2273 ( .A(n4145), .B(n2104), .Y(n2106) );
NOR2X1TS U2274 ( .A(n4156), .B(n4151), .Y(n2104) );
OAI21XLTS U2275 ( .A0(n2013), .A1(n4108), .B0(n2012), .Y(n2014) );
NAND2X1TS U2276 ( .A(n2713), .B(n2015), .Y(n4075) );
NOR2X1TS U2277 ( .A(n2817), .B(n2819), .Y(n2135) );
NAND2X1TS U2278 ( .A(n3718), .B(n2051), .Y(n2053) );
NAND2X1TS U2279 ( .A(n3921), .B(n2123), .Y(n2374) );
OAI21XLTS U2280 ( .A0(n3915), .A1(n3955), .B0(n3916), .Y(n2122) );
OAI21XLTS U2281 ( .A0(n2043), .A1(n3952), .B0(n2042), .Y(n2044) );
NAND2X1TS U2282 ( .A(n3950), .B(n2045), .Y(n3713) );
NOR2X1TS U2283 ( .A(n4357), .B(n4351), .Y(n3921) );
OAI21X1TS U2284 ( .A0(n4351), .A1(n4356), .B0(n4352), .Y(n3920) );
OAI21XLTS U2285 ( .A0(n2035), .A1(n4036), .B0(n2034), .Y(n2036) );
OAI21XLTS U2286 ( .A0(n4192), .A1(n4197), .B0(n4193), .Y(n2107) );
NAND2X1TS U2287 ( .A(n4115), .B(n2108), .Y(n2411) );
CLKAND2X2TS U2288 ( .A(n2674), .B(n2673), .Y(n4326) );
NAND4XLTS U2289 ( .A(n2404), .B(n2403), .C(n2402), .D(n3024), .Y(n3675) );
INVX2TS U2290 ( .A(n4210), .Y(n4240) );
OR2X1TS U2291 ( .A(shift_value_SHT2_EWR[4]), .B(n4520), .Y(n2393) );
CLKAND2X2TS U2292 ( .A(n2322), .B(n2321), .Y(n4314) );
NAND4XLTS U2293 ( .A(n2621), .B(n2620), .C(n2619), .D(n3024), .Y(n3684) );
NAND4XLTS U2294 ( .A(n2661), .B(n2660), .C(n2659), .D(n3024), .Y(n3679) );
NAND4XLTS U2295 ( .A(n2612), .B(n2611), .C(n2610), .D(n3024), .Y(n3690) );
CLKAND2X2TS U2296 ( .A(n3656), .B(n3655), .Y(n4341) );
CLKAND2X2TS U2297 ( .A(n2669), .B(n2668), .Y(n4332) );
OAI21XLTS U2298 ( .A0(n2774), .A1(n4625), .B0(n2773), .Y(n2775) );
OAI21XLTS U2299 ( .A0(n2793), .A1(n4666), .B0(n2759), .Y(n2760) );
NAND3XLTS U2300 ( .A(n2758), .B(n1993), .C(n2757), .Y(n2759) );
NOR2XLTS U2301 ( .A(Raw_mant_NRM_SWR[40]), .B(Raw_mant_NRM_SWR[42]), .Y(
n2738) );
OAI21XLTS U2302 ( .A0(Raw_mant_NRM_SWR[6]), .A1(Raw_mant_NRM_SWR[4]), .B0(
n2733), .Y(n2736) );
AOI21X1TS U2303 ( .A0(n3735), .A1(n3732), .B0(n2145), .Y(n3135) );
OAI21X1TS U2304 ( .A0(n3806), .A1(n2816), .B0(n2815), .Y(n3838) );
OAI21X1TS U2305 ( .A0(n3849), .A1(n2812), .B0(n2811), .Y(n3822) );
INVX2TS U2306 ( .A(n3802), .Y(n3821) );
INVX2TS U2307 ( .A(n2422), .Y(n4011) );
INVX2TS U2308 ( .A(n4099), .Y(n4184) );
INVX2TS U2309 ( .A(n2161), .Y(n2309) );
INVX2TS U2310 ( .A(n3158), .Y(n3551) );
AND3X1TS U2311 ( .A(n3326), .B(n3325), .C(n3324), .Y(n3344) );
OR2X1TS U2312 ( .A(n3365), .B(n4594), .Y(n3329) );
INVX2TS U2313 ( .A(n4024), .Y(n4025) );
OR2X1TS U2314 ( .A(n3618), .B(n4593), .Y(n3167) );
OR2X1TS U2315 ( .A(n3618), .B(n4611), .Y(n3163) );
AND3X1TS U2316 ( .A(n3262), .B(n3261), .C(n3260), .Y(n3473) );
CLKINVX6TS U2317 ( .A(n3558), .Y(n3588) );
AO21XLTS U2318 ( .A0(n3027), .A1(n4298), .B0(n3648), .Y(n1902) );
AO21XLTS U2319 ( .A0(n2971), .A1(n3022), .B0(n2970), .Y(n1900) );
AO21XLTS U2320 ( .A0(n2969), .A1(n3649), .B0(n1916), .Y(n2970) );
NOR2X4TS U2321 ( .A(n2368), .B(n2367), .Y(n4392) );
INVX2TS U2322 ( .A(n2350), .Y(n2351) );
INVX2TS U2323 ( .A(n4107), .Y(n4110) );
INVX2TS U2324 ( .A(n4222), .Y(n4132) );
INVX2TS U2325 ( .A(n4123), .Y(n4221) );
OAI21XLTS U2326 ( .A0(n4157), .A1(n4156), .B0(n4155), .Y(n4159) );
AO21XLTS U2327 ( .A0(n2963), .A1(n4298), .B0(n1917), .Y(n2964) );
AO21XLTS U2328 ( .A0(n2998), .A1(n4298), .B0(n1917), .Y(n2999) );
AO21XLTS U2329 ( .A0(n2947), .A1(n3649), .B0(n1917), .Y(n2948) );
NAND3BXLTS U2330 ( .AN(n2801), .B(n2800), .C(n2799), .Y(n2805) );
OAI21X1TS U2331 ( .A0(n3135), .A1(n3129), .B0(n3130), .Y(n4366) );
NOR2XLTS U2332 ( .A(n4657), .B(DMP_SFG[50]), .Y(n2097) );
NOR2XLTS U2333 ( .A(n4623), .B(DMP_SFG[48]), .Y(n2093) );
NOR2XLTS U2334 ( .A(n4614), .B(DMP_SFG[46]), .Y(n2089) );
OAI21X1TS U2335 ( .A0(n3869), .A1(n2085), .B0(n2084), .Y(n3894) );
NOR2XLTS U2336 ( .A(n4658), .B(DMP_SFG[44]), .Y(n2085) );
NOR2XLTS U2337 ( .A(n4642), .B(DMP_SFG[42]), .Y(n2081) );
OAI21XLTS U2338 ( .A0(n3849), .A1(n3848), .B0(n3847), .Y(n3851) );
INVX2TS U2339 ( .A(n2579), .Y(n3882) );
INVX2TS U2340 ( .A(n2575), .Y(n2578) );
OAI21XLTS U2341 ( .A0(n3781), .A1(n2586), .B0(n2585), .Y(n2589) );
INVX2TS U2342 ( .A(n3810), .Y(n3813) );
INVX2TS U2343 ( .A(n3797), .Y(n3800) );
INVX2TS U2344 ( .A(n3905), .Y(n3791) );
INVX2TS U2345 ( .A(n2594), .Y(n2595) );
INVX2TS U2346 ( .A(n2384), .Y(n3781) );
OAI21XLTS U2347 ( .A0(n3971), .A1(n3970), .B0(n3969), .Y(n3973) );
OAI21XLTS U2348 ( .A0(n4358), .A1(n4357), .B0(n4356), .Y(n4360) );
INVX2TS U2349 ( .A(n2416), .Y(n4085) );
INVX2TS U2350 ( .A(n3057), .Y(n3092) );
INVX2TS U2351 ( .A(n3057), .Y(n3089) );
NAND4XLTS U2352 ( .A(n3497), .B(n3496), .C(n3495), .D(n3494), .Y(n3544) );
NAND4XLTS U2353 ( .A(n3505), .B(n3504), .C(n3503), .D(n3502), .Y(n3543) );
NAND4XLTS U2354 ( .A(n3489), .B(n3488), .C(n3487), .D(n3486), .Y(n3545) );
BUFX3TS U2355 ( .A(n2931), .Y(n3122) );
BUFX3TS U2356 ( .A(n2931), .Y(n3113) );
BUFX3TS U2357 ( .A(n2914), .Y(n3146) );
AND3X1TS U2358 ( .A(n3216), .B(n3215), .C(n3214), .Y(n3356) );
OR2X1TS U2359 ( .A(n3365), .B(n4669), .Y(n3210) );
OR2X1TS U2360 ( .A(n3429), .B(n4519), .Y(n3406) );
OR2X1TS U2361 ( .A(n3429), .B(n4672), .Y(n3409) );
OR2X1TS U2362 ( .A(n3365), .B(n4590), .Y(n3368) );
OR2X1TS U2363 ( .A(n3429), .B(n4589), .Y(n3434) );
AO22XLTS U2364 ( .A0(n4409), .A1(Data_X[45]), .B0(n4408), .B1(intDX_EWSW[45]), .Y(n1838) );
AO22XLTS U2365 ( .A0(n4409), .A1(Data_X[43]), .B0(n4408), .B1(intDX_EWSW[43]), .Y(n1840) );
AO22XLTS U2366 ( .A0(n4406), .A1(Data_X[35]), .B0(n4405), .B1(intDX_EWSW[35]), .Y(n1848) );
AO22XLTS U2367 ( .A0(n4409), .A1(Data_X[50]), .B0(n4408), .B1(intDX_EWSW[50]), .Y(n1833) );
AO22XLTS U2368 ( .A0(n4406), .A1(Data_X[36]), .B0(n4405), .B1(intDX_EWSW[36]), .Y(n1847) );
AO22XLTS U2369 ( .A0(n4409), .A1(Data_X[31]), .B0(n4405), .B1(intDX_EWSW[31]), .Y(n1852) );
AO22XLTS U2370 ( .A0(n4429), .A1(Data_Y[59]), .B0(n4427), .B1(intDY_EWSW[59]), .Y(n1759) );
AO22XLTS U2371 ( .A0(n4409), .A1(Data_X[46]), .B0(n4408), .B1(intDX_EWSW[46]), .Y(n1837) );
AO22XLTS U2372 ( .A0(n4409), .A1(Data_X[51]), .B0(n4427), .B1(intDX_EWSW[51]), .Y(n1832) );
AO22XLTS U2373 ( .A0(n4429), .A1(Data_X[63]), .B0(n4427), .B1(intDX_EWSW[63]), .Y(n1820) );
AO22XLTS U2374 ( .A0(n4406), .A1(Data_X[39]), .B0(n4405), .B1(intDX_EWSW[39]), .Y(n1844) );
AO22XLTS U2375 ( .A0(n4406), .A1(Data_X[33]), .B0(n4405), .B1(intDX_EWSW[33]), .Y(n1850) );
AO22XLTS U2376 ( .A0(n4404), .A1(Data_X[30]), .B0(n4405), .B1(intDX_EWSW[30]), .Y(n1853) );
AO22XLTS U2377 ( .A0(n4429), .A1(Data_Y[58]), .B0(n4427), .B1(intDY_EWSW[58]), .Y(n1760) );
AO22XLTS U2378 ( .A0(n4429), .A1(Data_Y[60]), .B0(n4427), .B1(intDY_EWSW[60]), .Y(n1758) );
AO22XLTS U2379 ( .A0(n4406), .A1(Data_X[34]), .B0(n4405), .B1(intDX_EWSW[34]), .Y(n1849) );
AO22XLTS U2380 ( .A0(n4409), .A1(Data_X[42]), .B0(n4408), .B1(intDX_EWSW[42]), .Y(n1841) );
AO22XLTS U2381 ( .A0(n4406), .A1(Data_X[32]), .B0(n4405), .B1(intDX_EWSW[32]), .Y(n1851) );
AO22XLTS U2382 ( .A0(n4406), .A1(Data_X[40]), .B0(n4408), .B1(intDX_EWSW[40]), .Y(n1843) );
AO22XLTS U2383 ( .A0(n4409), .A1(Data_X[44]), .B0(n4408), .B1(intDX_EWSW[44]), .Y(n1839) );
AO22XLTS U2384 ( .A0(n4409), .A1(Data_X[47]), .B0(n4408), .B1(intDX_EWSW[47]), .Y(n1836) );
AO22XLTS U2385 ( .A0(n4406), .A1(Data_X[38]), .B0(n4405), .B1(intDX_EWSW[38]), .Y(n1845) );
AO22XLTS U2386 ( .A0(n4407), .A1(Data_X[41]), .B0(n4408), .B1(intDX_EWSW[41]), .Y(n1842) );
AO22XLTS U2387 ( .A0(n4428), .A1(intDY_EWSW[1]), .B0(n4410), .B1(Data_Y[1]),
.Y(n1817) );
AO22XLTS U2388 ( .A0(n4413), .A1(intDY_EWSW[15]), .B0(n4416), .B1(Data_Y[15]), .Y(n1803) );
AO22XLTS U2389 ( .A0(n4423), .A1(intDY_EWSW[46]), .B0(n4425), .B1(Data_Y[46]), .Y(n1772) );
AO22XLTS U2390 ( .A0(n4413), .A1(intDX_EWSW[61]), .B0(n4422), .B1(Data_X[61]), .Y(n1822) );
AO22XLTS U2391 ( .A0(n4423), .A1(intDY_EWSW[45]), .B0(n4425), .B1(Data_Y[45]), .Y(n1773) );
AO22XLTS U2392 ( .A0(n4426), .A1(intDY_EWSW[44]), .B0(n4422), .B1(Data_Y[44]), .Y(n1774) );
AO22XLTS U2393 ( .A0(n4411), .A1(intDX_EWSW[59]), .B0(n4425), .B1(Data_X[59]), .Y(n1824) );
AO22XLTS U2394 ( .A0(n4413), .A1(intDY_EWSW[14]), .B0(n4416), .B1(Data_Y[14]), .Y(n1804) );
AO22XLTS U2395 ( .A0(n4426), .A1(intDY_EWSW[51]), .B0(n4424), .B1(Data_Y[51]), .Y(n1767) );
AO22XLTS U2396 ( .A0(n4423), .A1(intDY_EWSW[47]), .B0(n4422), .B1(Data_Y[47]), .Y(n1771) );
AO22XLTS U2397 ( .A0(n4411), .A1(intDX_EWSW[58]), .B0(n4422), .B1(Data_X[58]), .Y(n1825) );
AO22XLTS U2398 ( .A0(n4426), .A1(intDY_EWSW[50]), .B0(n4425), .B1(Data_Y[50]), .Y(n1768) );
AO22XLTS U2399 ( .A0(n4423), .A1(intDY_EWSW[42]), .B0(n4425), .B1(Data_Y[42]), .Y(n1776) );
AO22XLTS U2400 ( .A0(n4413), .A1(intDY_EWSW[17]), .B0(n4410), .B1(Data_Y[17]), .Y(n1801) );
AO22XLTS U2401 ( .A0(n4417), .A1(intDY_EWSW[25]), .B0(n4416), .B1(Data_Y[25]), .Y(n1793) );
AO22XLTS U2402 ( .A0(n4413), .A1(intDY_EWSW[13]), .B0(n4414), .B1(Data_Y[13]), .Y(n1805) );
AO22XLTS U2403 ( .A0(n4417), .A1(intDY_EWSW[23]), .B0(n4416), .B1(Data_Y[23]), .Y(n1795) );
AO22XLTS U2404 ( .A0(n4417), .A1(intDY_EWSW[29]), .B0(n4416), .B1(Data_Y[29]), .Y(n1789) );
AO22XLTS U2405 ( .A0(n4411), .A1(intDY_EWSW[11]), .B0(n4414), .B1(Data_Y[11]), .Y(n1807) );
AO22XLTS U2406 ( .A0(n4423), .A1(intDY_EWSW[49]), .B0(n4425), .B1(Data_Y[49]), .Y(n1769) );
AO22XLTS U2407 ( .A0(n4413), .A1(intDY_EWSW[12]), .B0(n4414), .B1(Data_Y[12]), .Y(n1806) );
AO22XLTS U2408 ( .A0(n4417), .A1(intDY_EWSW[18]), .B0(n4418), .B1(Data_Y[18]), .Y(n1800) );
AO22XLTS U2409 ( .A0(n4417), .A1(intDY_EWSW[20]), .B0(n4418), .B1(Data_Y[20]), .Y(n1798) );
AO22XLTS U2410 ( .A0(n4417), .A1(intDY_EWSW[22]), .B0(n4416), .B1(Data_Y[22]), .Y(n1796) );
AO22XLTS U2411 ( .A0(n4417), .A1(intDY_EWSW[24]), .B0(n4416), .B1(Data_Y[24]), .Y(n1794) );
AO22XLTS U2412 ( .A0(n4419), .A1(intDY_EWSW[26]), .B0(n4416), .B1(Data_Y[26]), .Y(n1792) );
AO22XLTS U2413 ( .A0(n4419), .A1(intDY_EWSW[28]), .B0(n4416), .B1(Data_Y[28]), .Y(n1790) );
AO22XLTS U2414 ( .A0(n4413), .A1(intDY_EWSW[16]), .B0(n4418), .B1(Data_Y[16]), .Y(n1802) );
XOR2XLTS U2415 ( .A(n4268), .B(n4267), .Y(n4270) );
CLKAND2X2TS U2416 ( .A(n4266), .B(n4265), .Y(n4268) );
AOI2BB2XLTS U2417 ( .B0(intDY_EWSW[3]), .B1(n1949), .A0N(intDX_EWSW[2]),
.A1N(n2242), .Y(n2243) );
NAND2BXLTS U2418 ( .AN(intDY_EWSW[2]), .B(intDX_EWSW[2]), .Y(n2241) );
NOR2X1TS U2419 ( .A(n3721), .B(n2380), .Y(n2125) );
NOR2BX1TS U2420 ( .AN(n2255), .B(n2254), .Y(n2256) );
OAI211XLTS U2421 ( .A0(intDY_EWSW[8]), .A1(n1950), .B0(n2261), .C0(n2264),
.Y(n2254) );
INVX2TS U2422 ( .A(n2266), .Y(n2255) );
OAI2BB2XLTS U2423 ( .B0(n2267), .B1(n2266), .A0N(n2265), .A1N(n2264), .Y(
n2270) );
OAI21XLTS U2424 ( .A0(intDY_EWSW[13]), .A1(n1954), .B0(intDY_EWSW[12]), .Y(
n2258) );
OAI21XLTS U2425 ( .A0(intDY_EWSW[15]), .A1(n1951), .B0(intDY_EWSW[14]), .Y(
n2268) );
OAI21XLTS U2426 ( .A0(intDY_EWSW[41]), .A1(n1955), .B0(intDY_EWSW[40]), .Y(
n2172) );
NOR2X1TS U2427 ( .A(n1974), .B(intDY_EWSW[45]), .Y(n2170) );
OAI21XLTS U2428 ( .A0(n4151), .A1(n4155), .B0(n4152), .Y(n2103) );
NOR2X1TS U2429 ( .A(n2374), .B(n2127), .Y(n2129) );
NAND2X1TS U2430 ( .A(n2379), .B(n2125), .Y(n2127) );
NOR2X1TS U2431 ( .A(n4037), .B(n2035), .Y(n2037) );
NAND2X1TS U2432 ( .A(n4035), .B(n2037), .Y(n2039) );
OAI221XLTS U2433 ( .A0(n4501), .A1(intDX_EWSW[29]), .B0(n4559), .B1(
intDX_EWSW[20]), .C0(n3507), .Y(n3512) );
OA22X1TS U2434 ( .A0(n1970), .A1(intDY_EWSW[22]), .B0(n1973), .B1(
intDY_EWSW[23]), .Y(n2291) );
OAI21XLTS U2435 ( .A0(intDY_EWSW[21]), .A1(n1966), .B0(intDY_EWSW[20]), .Y(
n2279) );
OAI2BB2XLTS U2436 ( .B0(intDX_EWSW[22]), .B1(n2287), .A0N(intDY_EWSW[23]),
.A1N(n1973), .Y(n2288) );
OAI21XLTS U2437 ( .A0(intDY_EWSW[23]), .A1(n1973), .B0(intDY_EWSW[22]), .Y(
n2287) );
OAI21XLTS U2438 ( .A0(intDY_EWSW[29]), .A1(n1991), .B0(intDY_EWSW[28]), .Y(
n2225) );
NOR2X1TS U2439 ( .A(n1952), .B(intDY_EWSW[25]), .Y(n2292) );
OAI2BB1X1TS U2440 ( .A0N(n2278), .A1N(n2277), .B0(n2276), .Y(n2298) );
NOR2BX1TS U2441 ( .AN(n2275), .B(n2285), .Y(n2276) );
AOI211XLTS U2442 ( .A0(n2272), .A1(n2271), .B0(n2270), .C0(n2269), .Y(n2277)
);
NAND2BX1TS U2443 ( .AN(n2257), .B(n2256), .Y(n2278) );
OA22X1TS U2444 ( .A0(n1965), .A1(intDY_EWSW[34]), .B0(n1967), .B1(
intDY_EWSW[35]), .Y(n2300) );
OAI21XLTS U2445 ( .A0(n2194), .A1(n2193), .B0(n2192), .Y(n2195) );
NAND3XLTS U2446 ( .A(n1968), .B(n2191), .C(intDY_EWSW[36]), .Y(n2186) );
NOR2X1TS U2447 ( .A(n3828), .B(n2067), .Y(n2069) );
OAI21XLTS U2448 ( .A0(n2005), .A1(n4138), .B0(n2004), .Y(n2006) );
OR2X1TS U2449 ( .A(n2474), .B(Raw_mant_NRM_SWR[9]), .Y(n2471) );
OAI21XLTS U2450 ( .A0(Raw_mant_NRM_SWR[36]), .A1(Raw_mant_NRM_SWR[35]), .B0(
n4519), .Y(n2493) );
NAND3XLTS U2451 ( .A(n2551), .B(Raw_mant_NRM_SWR[32]), .C(n4594), .Y(n2499)
);
NOR2XLTS U2452 ( .A(n2794), .B(n2522), .Y(n2525) );
OAI21XLTS U2453 ( .A0(Raw_mant_NRM_SWR[40]), .A1(n4592), .B0(n4519), .Y(
n2545) );
OAI21XLTS U2454 ( .A0(n2553), .A1(n4593), .B0(n2552), .Y(n2554) );
NAND4XLTS U2455 ( .A(n2754), .B(n2475), .C(n2474), .D(n2473), .Y(n2476) );
NOR2XLTS U2456 ( .A(Raw_mant_NRM_SWR[13]), .B(Raw_mant_NRM_SWR[10]), .Y(
n2473) );
NOR2XLTS U2457 ( .A(Raw_mant_NRM_SWR[14]), .B(Raw_mant_NRM_SWR[9]), .Y(n2475) );
OR2X1TS U2458 ( .A(n2529), .B(Raw_mant_NRM_SWR[35]), .Y(n2787) );
NOR2X1TS U2459 ( .A(n2579), .B(n2581), .Y(n2139) );
OAI21XLTS U2460 ( .A0(n2049), .A1(n3719), .B0(n2048), .Y(n2050) );
NOR2X1TS U2461 ( .A(n2428), .B(n2121), .Y(n2373) );
OAI21X1TS U2462 ( .A0(n2429), .A1(n2121), .B0(n2120), .Y(n2372) );
OAI21XLTS U2463 ( .A0(n2434), .A1(n4039), .B0(n2435), .Y(n2118) );
NAND2X1TS U2464 ( .A(n4002), .B(n2117), .Y(n2428) );
AOI21X1TS U2465 ( .A0(n4001), .A1(n2117), .B0(n2116), .Y(n2429) );
OAI21XLTS U2466 ( .A0(n4061), .A1(n4066), .B0(n4062), .Y(n2116) );
OAI21XLTS U2467 ( .A0(n2029), .A1(n3996), .B0(n2028), .Y(n2030) );
NAND2X1TS U2468 ( .A(n3995), .B(n2031), .Y(n3980) );
AOI21X2TS U2469 ( .A0(n2409), .A1(n2114), .B0(n2113), .Y(n2371) );
NAND2X1TS U2470 ( .A(n2412), .B(n2110), .Y(n2112) );
AOI21X2TS U2471 ( .A0(n2712), .A1(n2025), .B0(n2024), .Y(n2422) );
NOR2X1TS U2472 ( .A(n4075), .B(n2023), .Y(n2025) );
NAND2X1TS U2473 ( .A(n4076), .B(n2021), .Y(n2023) );
AOI211X1TS U2474 ( .A0(intDY_EWSW[46]), .A1(n2181), .B0(n2180), .C0(n2179),
.Y(n2224) );
NAND3X1TS U2475 ( .A(n2208), .B(n2218), .C(n2167), .Y(n2305) );
NAND4X1TS U2476 ( .A(n2185), .B(n2184), .C(n2183), .D(n2182), .Y(n2303) );
NAND3XLTS U2477 ( .A(n2546), .B(n4519), .C(n2505), .Y(n2514) );
MX2X1TS U2478 ( .A(DmP_mant_SHT1_SW[25]), .B(Raw_mant_NRM_SWR[27]), .S0(
n4369), .Y(n3175) );
CLKAND2X2TS U2479 ( .A(n2961), .B(n2960), .Y(n3012) );
NAND4BXLTS U2480 ( .AN(n2445), .B(n2358), .C(n4387), .D(n4386), .Y(n2359) );
NOR2XLTS U2481 ( .A(n2448), .B(n2447), .Y(n2358) );
NOR2BX1TS U2482 ( .AN(LZD_output_NRM2_EW[2]), .B(ADD_OVRFLW_NRM2), .Y(n2333)
);
INVX2TS U2483 ( .A(n4131), .Y(n4223) );
NOR2XLTS U2484 ( .A(n4233), .B(n1999), .Y(n2001) );
OAI21XLTS U2485 ( .A0(n1999), .A1(n4232), .B0(n1998), .Y(n2000) );
INVX2TS U2486 ( .A(n4112), .Y(n4199) );
INVX2TS U2487 ( .A(n4116), .Y(n4117) );
AOI2BB2XLTS U2488 ( .B0(n2788), .B1(Raw_mant_NRM_SWR[34]), .A0N(n2787),
.A1N(n4594), .Y(n2789) );
OR2X1TS U2489 ( .A(Raw_mant_NRM_SWR[24]), .B(Raw_mant_NRM_SWR[23]), .Y(n2487) );
NAND2X1TS U2490 ( .A(n2575), .B(n2139), .Y(n3848) );
OAI21X2TS U2491 ( .A0(n2811), .A1(n2137), .B0(n2136), .Y(n2576) );
OAI21XLTS U2492 ( .A0(n2819), .A1(n3833), .B0(n2820), .Y(n2134) );
NOR2X1TS U2493 ( .A(n2812), .B(n2137), .Y(n2575) );
AOI21X1TS U2494 ( .A0(n2824), .A1(n2075), .B0(n2074), .Y(n2585) );
OAI21XLTS U2495 ( .A0(n2073), .A1(n3877), .B0(n2072), .Y(n2074) );
NAND2X1TS U2496 ( .A(n2823), .B(n2075), .Y(n2586) );
INVX2TS U2497 ( .A(n2817), .Y(n3834) );
NOR2X1TS U2498 ( .A(n3797), .B(n2065), .Y(n3810) );
INVX2TS U2499 ( .A(n3790), .Y(n3906) );
NOR2X1TS U2500 ( .A(n3970), .B(n3964), .Y(n2379) );
AOI21X1TS U2501 ( .A0(n3934), .A1(n2377), .B0(n2376), .Y(n3971) );
INVX2TS U2502 ( .A(n3713), .Y(n3716) );
AOI21X1TS U2503 ( .A0(n4027), .A1(n2373), .B0(n2372), .Y(n4358) );
AOI21X1TS U2504 ( .A0(n4011), .A1(n2439), .B0(n2438), .Y(n3929) );
INVX2TS U2505 ( .A(n4012), .Y(n4026) );
NOR2X1TS U2506 ( .A(n4099), .B(n4094), .Y(n2412) );
AOI221X1TS U2507 ( .A0(n4603), .A1(intDX_EWSW[51]), .B0(intDX_EWSW[52]),
.B1(n4518), .C0(n3477), .Y(n3487) );
AOI221X1TS U2508 ( .A0(n4602), .A1(intDX_EWSW[46]), .B0(intDX_EWSW[47]),
.B1(n4528), .C0(n3492), .Y(n3495) );
NAND4XLTS U2509 ( .A(n3541), .B(n3540), .C(n3539), .D(n3538), .Y(n3542) );
OR2X1TS U2510 ( .A(n3429), .B(n4671), .Y(n3335) );
AND3X1TS U2511 ( .A(n3204), .B(n3203), .C(n3202), .Y(n3403) );
AND3X1TS U2512 ( .A(n3196), .B(n3195), .C(n3194), .Y(n3400) );
AND3X1TS U2513 ( .A(n3278), .B(n3277), .C(n3276), .Y(n3560) );
OR2X1TS U2514 ( .A(n3374), .B(n4575), .Y(n3284) );
INVX2TS U2515 ( .A(n4019), .Y(n4021) );
OR2X1TS U2516 ( .A(n3365), .B(n4628), .Y(n3307) );
OR2X1TS U2517 ( .A(n3374), .B(n4574), .Y(n3314) );
OR2X1TS U2518 ( .A(n3374), .B(n4626), .Y(n3281) );
OR2X1TS U2519 ( .A(n3618), .B(n1994), .Y(n3373) );
INVX2TS U2520 ( .A(n2717), .Y(n2719) );
INVX2TS U2521 ( .A(n2819), .Y(n2821) );
OR2X1TS U2522 ( .A(n3429), .B(n4523), .Y(n2700) );
OR2X1TS U2523 ( .A(n3429), .B(n4522), .Y(n3190) );
OR2X1TS U2524 ( .A(n3429), .B(n4483), .Y(n3193) );
OR2X1TS U2525 ( .A(n3365), .B(n4615), .Y(n3245) );
OR2X1TS U2526 ( .A(n3618), .B(n4591), .Y(n3242) );
OR2X1TS U2527 ( .A(n3618), .B(n4588), .Y(n3239) );
OR2X1TS U2528 ( .A(n3374), .B(n4667), .Y(n3269) );
OR2X1TS U2529 ( .A(n3618), .B(n4585), .Y(n3182) );
OR2X1TS U2530 ( .A(n3374), .B(n4577), .Y(n3272) );
OR2X1TS U2531 ( .A(n3374), .B(n4586), .Y(n3179) );
OR2X4TS U2532 ( .A(n4393), .B(n4392), .Y(n3680) );
OAI21XLTS U2533 ( .A0(n3673), .A1(n4325), .B0(n3686), .Y(n3674) );
OAI21XLTS U2534 ( .A0(n4329), .A1(n4310), .B0(n1931), .Y(n2395) );
OAI21XLTS U2535 ( .A0(n4329), .A1(n4320), .B0(n1931), .Y(n2846) );
OAI211XLTS U2536 ( .A0(n4320), .A1(n4333), .B0(n1931), .C0(n4319), .Y(n4321)
);
OAI211XLTS U2537 ( .A0(n4310), .A1(n4333), .B0(n1931), .C0(n4309), .Y(n4311)
);
BUFX3TS U2538 ( .A(n2397), .Y(n4385) );
OAI211XLTS U2539 ( .A0(n4330), .A1(n4333), .B0(n1931), .C0(n4303), .Y(n4304)
);
BUFX3TS U2540 ( .A(n2397), .Y(n4381) );
NAND3XLTS U2541 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n4511), .C(
n4567), .Y(n4394) );
INVX2TS U2542 ( .A(n4126), .Y(n4128) );
INVX2TS U2543 ( .A(n4038), .Y(n4040) );
OAI21XLTS U2544 ( .A0(n4052), .A1(n4037), .B0(n4036), .Y(n4042) );
INVX2TS U2545 ( .A(n4234), .Y(n4236) );
OAI21XLTS U2546 ( .A0(n4248), .A1(n4233), .B0(n4232), .Y(n4238) );
INVX2TS U2547 ( .A(n4206), .Y(n4208) );
OAI21XLTS U2548 ( .A0(n4240), .A1(n4234), .B0(n4235), .Y(n4212) );
OAI211XLTS U2549 ( .A0(n4314), .A1(n2393), .B0(n2325), .C0(n2324), .Y(n2329)
);
OAI21XLTS U2550 ( .A0(n4166), .A1(n4165), .B0(n4164), .Y(n4171) );
INVX2TS U2551 ( .A(n4192), .Y(n4194) );
OAI21XLTS U2552 ( .A0(n3687), .A1(n4325), .B0(n3686), .Y(n3688) );
OAI21XLTS U2553 ( .A0(n4140), .A1(n4139), .B0(n4138), .Y(n4143) );
INVX2TS U2554 ( .A(n4061), .Y(n4063) );
OAI21XLTS U2555 ( .A0(n4068), .A1(n4067), .B0(n4066), .Y(n4070) );
OAI21XLTS U2556 ( .A0(n4341), .A1(n3659), .B0(n3658), .Y(n3663) );
AND3X1TS U2557 ( .A(n2780), .B(n2779), .C(n2799), .Y(n2782) );
AOI31XLTS U2558 ( .A0(n2755), .A1(n2754), .A2(Raw_mant_NRM_SWR[10]), .B0(
n2753), .Y(n2766) );
INVX2TS U2559 ( .A(n2581), .Y(n2583) );
INVX2TS U2560 ( .A(n3881), .Y(n2580) );
INVX2TS U2561 ( .A(n3815), .Y(n3817) );
INVX2TS U2562 ( .A(n3819), .Y(n3820) );
INVX2TS U2563 ( .A(n2597), .Y(n2599) );
OAI21XLTS U2564 ( .A0(n3849), .A1(n2680), .B0(n2681), .Y(n2602) );
INVX2TS U2565 ( .A(n2680), .Y(n2682) );
OAI21XLTS U2566 ( .A0(n3781), .A1(n2679), .B0(n2678), .Y(n2684) );
OAI21XLTS U2567 ( .A0(n3727), .A1(n3721), .B0(n3722), .Y(n2383) );
INVX2TS U2568 ( .A(n2380), .Y(n2382) );
AOI21X1TS U2569 ( .A0(n3945), .A1(n2379), .B0(n2378), .Y(n3727) );
INVX2TS U2570 ( .A(n3721), .Y(n3723) );
OAI21XLTS U2571 ( .A0(n3968), .A1(n3720), .B0(n3719), .Y(n3725) );
INVX2TS U2572 ( .A(n3964), .Y(n3966) );
INVX2TS U2573 ( .A(n3970), .Y(n3941) );
OAI21XLTS U2574 ( .A0(n3960), .A1(n3954), .B0(n3955), .Y(n3923) );
INVX2TS U2575 ( .A(n3954), .Y(n3956) );
OAI21XLTS U2576 ( .A0(n4355), .A1(n3953), .B0(n3952), .Y(n3958) );
OAI21XLTS U2577 ( .A0(n3929), .A1(n3928), .B0(n3927), .Y(n3932) );
INVX2TS U2578 ( .A(n2434), .Y(n2436) );
INVX2TS U2579 ( .A(n4048), .Y(n4050) );
INVX2TS U2580 ( .A(n4054), .Y(n3986) );
OAI21XLTS U2581 ( .A0(n4033), .A1(n3985), .B0(n3984), .Y(n3988) );
INVX2TS U2582 ( .A(n4067), .Y(n3998) );
OAI21XLTS U2583 ( .A0(n4023), .A1(n3997), .B0(n3996), .Y(n4000) );
INVX2TS U2584 ( .A(n4084), .Y(n2417) );
INVX2TS U2585 ( .A(n4094), .Y(n4096) );
INVX2TS U2586 ( .A(n4183), .Y(n4100) );
INVX2TS U2587 ( .A(n4472), .Y(busy) );
AOI2BB2XLTS U2588 ( .B0(Data_array_SWR[1]), .B1(n3439), .A0N(n3158), .A1N(
n3157), .Y(n3159) );
AOI2BB2XLTS U2589 ( .B0(Data_array_SWR[2]), .B1(n3439), .A0N(n3158), .A1N(
n3156), .Y(n3154) );
MX2X1TS U2590 ( .A(DMP_exp_NRM_EW[0]), .B(DMP_SFG[52]), .S0(n4479), .Y(n1450) );
MX2X1TS U2591 ( .A(DmP_mant_SHT1_SW[24]), .B(DmP_EXP_EWSW[24]), .S0(n4474),
.Y(n1349) );
MX2X1TS U2592 ( .A(DMP_SHT2_EWSW[36]), .B(DMP_SHT1_EWSW[36]), .S0(n3704),
.Y(n1500) );
MX2X1TS U2593 ( .A(DMP_SHT2_EWSW[35]), .B(DMP_SHT1_EWSW[35]), .S0(n3701),
.Y(n1503) );
MX2X1TS U2594 ( .A(DMP_SHT2_EWSW[34]), .B(DMP_SHT1_EWSW[34]), .S0(n4441),
.Y(n1506) );
MX2X1TS U2595 ( .A(DMP_SHT2_EWSW[33]), .B(DMP_SHT1_EWSW[33]), .S0(n3701),
.Y(n1509) );
MX2X1TS U2596 ( .A(DMP_SHT2_EWSW[32]), .B(DMP_SHT1_EWSW[32]), .S0(n4441),
.Y(n1512) );
MX2X1TS U2597 ( .A(DMP_SHT2_EWSW[31]), .B(DMP_SHT1_EWSW[31]), .S0(n3701),
.Y(n1515) );
MX2X1TS U2598 ( .A(DMP_SHT2_EWSW[30]), .B(DMP_SHT1_EWSW[30]), .S0(n4441),
.Y(n1518) );
MX2X1TS U2599 ( .A(DMP_SHT2_EWSW[29]), .B(DMP_SHT1_EWSW[29]), .S0(n4441),
.Y(n1521) );
MX2X1TS U2600 ( .A(DMP_SHT2_EWSW[28]), .B(DMP_SHT1_EWSW[28]), .S0(n3701),
.Y(n1524) );
MX2X1TS U2601 ( .A(DMP_SHT2_EWSW[27]), .B(DMP_SHT1_EWSW[27]), .S0(n4441),
.Y(n1527) );
MX2X1TS U2602 ( .A(DMP_SHT2_EWSW[26]), .B(DMP_SHT1_EWSW[26]), .S0(n3701),
.Y(n1530) );
MX2X1TS U2603 ( .A(DMP_SHT2_EWSW[22]), .B(DMP_SHT1_EWSW[22]), .S0(n4441),
.Y(n1542) );
MX2X1TS U2604 ( .A(DMP_SHT2_EWSW[21]), .B(DMP_SHT1_EWSW[21]), .S0(n3701),
.Y(n1545) );
MX2X1TS U2605 ( .A(DMP_SHT2_EWSW[20]), .B(DMP_SHT1_EWSW[20]), .S0(n4441),
.Y(n1548) );
MX2X1TS U2606 ( .A(DMP_SHT2_EWSW[19]), .B(DMP_SHT1_EWSW[19]), .S0(n3701),
.Y(n1551) );
MX2X1TS U2607 ( .A(DMP_SHT2_EWSW[18]), .B(DMP_SHT1_EWSW[18]), .S0(n4441),
.Y(n1554) );
MX2X1TS U2608 ( .A(DMP_SHT2_EWSW[17]), .B(DMP_SHT1_EWSW[17]), .S0(n1911),
.Y(n1557) );
MX2X1TS U2609 ( .A(DMP_SHT2_EWSW[16]), .B(DMP_SHT1_EWSW[16]), .S0(n1911),
.Y(n1560) );
MX2X1TS U2610 ( .A(DMP_SHT2_EWSW[15]), .B(DMP_SHT1_EWSW[15]), .S0(n1911),
.Y(n1563) );
MX2X1TS U2611 ( .A(DMP_SHT2_EWSW[14]), .B(DMP_SHT1_EWSW[14]), .S0(n1912),
.Y(n1566) );
MX2X1TS U2612 ( .A(DMP_SHT2_EWSW[13]), .B(DMP_SHT1_EWSW[13]), .S0(n1912),
.Y(n1569) );
MX2X1TS U2613 ( .A(DMP_SHT2_EWSW[12]), .B(DMP_SHT1_EWSW[12]), .S0(n1912),
.Y(n1572) );
MX2X1TS U2614 ( .A(DMP_SHT2_EWSW[11]), .B(DMP_SHT1_EWSW[11]), .S0(n1912),
.Y(n1575) );
MX2X1TS U2615 ( .A(DMP_SHT2_EWSW[10]), .B(DMP_SHT1_EWSW[10]), .S0(n4441),
.Y(n1578) );
MX2X1TS U2616 ( .A(DMP_SHT2_EWSW[9]), .B(DMP_SHT1_EWSW[9]), .S0(n3701), .Y(
n1581) );
MX2X1TS U2617 ( .A(DMP_SHT2_EWSW[6]), .B(DMP_SHT1_EWSW[6]), .S0(n3704), .Y(
n1590) );
MX2X1TS U2618 ( .A(DMP_SHT2_EWSW[5]), .B(DMP_SHT1_EWSW[5]), .S0(n3704), .Y(
n1593) );
MX2X1TS U2619 ( .A(DMP_SHT2_EWSW[4]), .B(DMP_SHT1_EWSW[4]), .S0(n3704), .Y(
n1596) );
MX2X1TS U2620 ( .A(DMP_SHT2_EWSW[2]), .B(DMP_SHT1_EWSW[2]), .S0(n3704), .Y(
n1602) );
MX2X1TS U2621 ( .A(DMP_SHT2_EWSW[1]), .B(DMP_SHT1_EWSW[1]), .S0(n3704), .Y(
n1605) );
MX2X1TS U2622 ( .A(DMP_SHT2_EWSW[0]), .B(DMP_SHT1_EWSW[0]), .S0(n3704), .Y(
n1608) );
AO22XLTS U2623 ( .A0(n4426), .A1(intDY_EWSW[48]), .B0(n4425), .B1(Data_Y[48]), .Y(n1770) );
AO22XLTS U2624 ( .A0(n4407), .A1(Data_X[15]), .B0(n4402), .B1(intDX_EWSW[15]), .Y(n1868) );
AO22XLTS U2625 ( .A0(n4406), .A1(Data_X[3]), .B0(n4401), .B1(intDX_EWSW[3]),
.Y(n1880) );
MX2X1TS U2626 ( .A(DMP_SHT2_EWSW[3]), .B(DMP_SFG[3]), .S0(n1915), .Y(n1598)
);
OAI222X1TS U2627 ( .A0(n3666), .A1(n3628), .B0(n3668), .B1(n3627), .C0(n4650), .C1(n3637), .Y(n1145) );
OAI222X1TS U2628 ( .A0(n3670), .A1(n3636), .B0(n3668), .B1(n3635), .C0(n4636), .C1(n3637), .Y(n1148) );
OAI222X1TS U2629 ( .A0(n3643), .A1(n3634), .B0(n3645), .B1(n3633), .C0(n4652), .C1(n3637), .Y(n1149) );
OAI222X1TS U2630 ( .A0(n3643), .A1(n1936), .B0(n3645), .B1(n3632), .C0(n4653), .C1(n4286), .Y(n1153) );
AO22XLTS U2631 ( .A0(n4419), .A1(intDY_EWSW[37]), .B0(n4420), .B1(Data_Y[37]), .Y(n1781) );
AO22XLTS U2632 ( .A0(n4421), .A1(Data_X[1]), .B0(n4401), .B1(intDX_EWSW[1]),
.Y(n1882) );
AO22XLTS U2633 ( .A0(n4429), .A1(Data_Y[61]), .B0(n4428), .B1(intDY_EWSW[61]), .Y(n1757) );
AO22XLTS U2634 ( .A0(n4411), .A1(intDY_EWSW[2]), .B0(n4412), .B1(Data_Y[2]),
.Y(n1816) );
AO22XLTS U2635 ( .A0(n4428), .A1(intDY_EWSW[3]), .B0(n4414), .B1(Data_Y[3]),
.Y(n1815) );
AO22XLTS U2636 ( .A0(n4411), .A1(intDY_EWSW[0]), .B0(n4416), .B1(Data_Y[0]),
.Y(n1818) );
AO22XLTS U2637 ( .A0(n4426), .A1(intDY_EWSW[53]), .B0(n4424), .B1(Data_Y[53]), .Y(n1765) );
AO22XLTS U2638 ( .A0(n4429), .A1(Data_X[57]), .B0(n4427), .B1(intDX_EWSW[57]), .Y(n1826) );
AO22XLTS U2639 ( .A0(n4404), .A1(Data_X[26]), .B0(n4403), .B1(intDX_EWSW[26]), .Y(n1857) );
AO22XLTS U2640 ( .A0(n4407), .A1(Data_X[18]), .B0(n4402), .B1(intDX_EWSW[18]), .Y(n1865) );
AO22XLTS U2641 ( .A0(n4421), .A1(Data_X[8]), .B0(n4401), .B1(intDX_EWSW[8]),
.Y(n1875) );
AO22XLTS U2642 ( .A0(n4404), .A1(Data_X[25]), .B0(n4403), .B1(intDX_EWSW[25]), .Y(n1858) );
AO22XLTS U2643 ( .A0(n4407), .A1(Data_X[23]), .B0(n4403), .B1(intDX_EWSW[23]), .Y(n1860) );
AO22XLTS U2644 ( .A0(n4407), .A1(Data_X[17]), .B0(n4402), .B1(intDX_EWSW[17]), .Y(n1866) );
AO22XLTS U2645 ( .A0(n4428), .A1(intDY_EWSW[4]), .B0(n4412), .B1(Data_Y[4]),
.Y(n1814) );
OAI211X1TS U2646 ( .A0(n3600), .A1(n3599), .B0(n3598), .C0(n3597), .Y(n1724)
);
AO22XLTS U2647 ( .A0(n4407), .A1(Data_X[20]), .B0(n4403), .B1(intDX_EWSW[20]), .Y(n1863) );
AO22XLTS U2648 ( .A0(n4407), .A1(Data_X[21]), .B0(n4403), .B1(intDX_EWSW[21]), .Y(n1862) );
AO22XLTS U2649 ( .A0(n4404), .A1(Data_X[28]), .B0(n4403), .B1(intDX_EWSW[28]), .Y(n1855) );
AO22XLTS U2650 ( .A0(n4404), .A1(Data_X[12]), .B0(n4402), .B1(intDX_EWSW[12]), .Y(n1871) );
AO22XLTS U2651 ( .A0(n4421), .A1(Data_X[9]), .B0(n4401), .B1(intDX_EWSW[9]),
.Y(n1874) );
AO22XLTS U2652 ( .A0(n4415), .A1(Data_X[6]), .B0(n4401), .B1(intDX_EWSW[6]),
.Y(n1877) );
AO22XLTS U2653 ( .A0(n4410), .A1(Data_X[4]), .B0(n4401), .B1(intDX_EWSW[4]),
.Y(n1879) );
MX2X1TS U2654 ( .A(n4372), .B(LZD_output_NRM2_EW[1]), .S0(n4374), .Y(n1212)
);
MX2X1TS U2655 ( .A(n4256), .B(Shift_amount_SHT1_EWR[1]), .S0(n4435), .Y(
n1691) );
MX2X1TS U2656 ( .A(DmP_mant_SHT1_SW[22]), .B(DmP_EXP_EWSW[22]), .S0(n4474),
.Y(n1353) );
MX2X1TS U2657 ( .A(DmP_mant_SHT1_SW[23]), .B(DmP_EXP_EWSW[23]), .S0(n4474),
.Y(n1351) );
MX2X1TS U2658 ( .A(DmP_mant_SHT1_SW[50]), .B(DmP_EXP_EWSW[50]), .S0(n4474),
.Y(n1297) );
MX2X1TS U2659 ( .A(DmP_mant_SHT1_SW[51]), .B(DmP_EXP_EWSW[51]), .S0(n4474),
.Y(n1295) );
AO22XLTS U2660 ( .A0(n4429), .A1(Data_Y[63]), .B0(n4428), .B1(intDY_EWSW[63]), .Y(n1755) );
AO21XLTS U2661 ( .A0(n1995), .A1(n2572), .B0(n2571), .Y(n1698) );
MX2X1TS U2662 ( .A(n4260), .B(Shift_amount_SHT1_EWR[2]), .S0(n4435), .Y(
n1690) );
MX2X1TS U2663 ( .A(Shift_amount_SHT1_EWR[4]), .B(n3707), .S0(n1953), .Y(
n1688) );
MX2X1TS U2664 ( .A(DMP_SHT2_EWSW[3]), .B(DMP_SHT1_EWSW[3]), .S0(n3704), .Y(
n1599) );
MX2X1TS U2665 ( .A(DMP_SHT2_EWSW[7]), .B(DMP_SHT1_EWSW[7]), .S0(n3704), .Y(
n1587) );
MX2X1TS U2666 ( .A(DMP_SHT2_EWSW[8]), .B(DMP_SHT1_EWSW[8]), .S0(n1912), .Y(
n1584) );
MX2X1TS U2667 ( .A(DMP_SHT2_EWSW[23]), .B(DMP_SHT1_EWSW[23]), .S0(n1911),
.Y(n1539) );
MX2X1TS U2668 ( .A(DMP_SHT2_EWSW[24]), .B(DMP_SHT1_EWSW[24]), .S0(n1911),
.Y(n1536) );
MX2X1TS U2669 ( .A(DMP_SHT2_EWSW[25]), .B(DMP_SHT1_EWSW[25]), .S0(n1911),
.Y(n1533) );
MX2X1TS U2670 ( .A(DmP_mant_SHT1_SW[25]), .B(DmP_EXP_EWSW[25]), .S0(n4474),
.Y(n1347) );
MX2X1TS U2671 ( .A(Shift_amount_SHT1_EWR[3]), .B(n4264), .S0(n1953), .Y(
n1689) );
MX2X1TS U2672 ( .A(DMP_exp_NRM2_EW[1]), .B(DMP_exp_NRM_EW[1]), .S0(n4369),
.Y(n1444) );
MX2X1TS U2673 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(n4480),
.Y(n1434) );
MX2X1TS U2674 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(n4480),
.Y(n1424) );
MX2X1TS U2675 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(n4369),
.Y(n1414) );
MX2X1TS U2676 ( .A(DMP_exp_NRM2_EW[9]), .B(DMP_exp_NRM_EW[9]), .S0(n4480),
.Y(n1404) );
MX2X1TS U2677 ( .A(DMP_exp_NRM2_EW[2]), .B(DMP_exp_NRM_EW[2]), .S0(n4480),
.Y(n1439) );
MX2X1TS U2678 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(n4480),
.Y(n1419) );
MX2X1TS U2679 ( .A(DMP_exp_NRM2_EW[8]), .B(DMP_exp_NRM_EW[8]), .S0(n4468),
.Y(n1409) );
MX2X1TS U2680 ( .A(DMP_SHT2_EWSW[1]), .B(DMP_SFG[1]), .S0(n1915), .Y(n1604)
);
MX2X1TS U2681 ( .A(DMP_SHT2_EWSW[15]), .B(DMP_SFG[15]), .S0(n4449), .Y(n1562) );
MX2X1TS U2682 ( .A(DMP_exp_NRM2_EW[10]), .B(DMP_exp_NRM_EW[10]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n1399) );
AO22XLTS U2683 ( .A0(n4399), .A1(n1911), .B0(n4398), .B1(
Shift_reg_FLAGS_7[3]), .Y(n1887) );
AO22XLTS U2684 ( .A0(n4368), .A1(n4367), .B0(ADD_OVRFLW_NRM), .B1(n4478),
.Y(n1277) );
OR2X1TS U2685 ( .A(n4366), .B(DmP_mant_SFG_SWR[54]), .Y(n4368) );
MX2X1TS U2686 ( .A(n4348), .B(DmP_mant_SFG_SWR[5]), .S0(n4349), .Y(n1151) );
OAI222X1TS U2687 ( .A0(n3666), .A1(n3644), .B0(n3640), .B1(n3642), .C0(n4651), .C1(n3637), .Y(n1147) );
MX2X1TS U2688 ( .A(OP_FLAG_SHT2), .B(OP_FLAG_SFG), .S0(n1915), .Y(n1278) );
AO22XLTS U2689 ( .A0(n4407), .A1(Data_X[14]), .B0(n4402), .B1(intDX_EWSW[14]), .Y(n1869) );
XOR2XLTS U2690 ( .A(n4023), .B(n4022), .Y(n4032) );
AO22XLTS U2691 ( .A0(n4426), .A1(intDY_EWSW[56]), .B0(n4424), .B1(Data_Y[56]), .Y(n1762) );
MX2X1TS U2692 ( .A(DMP_SHT2_EWSW[51]), .B(DMP_SFG[51]), .S0(n4449), .Y(n1454) );
AO22XLTS U2693 ( .A0(n4421), .A1(Data_X[11]), .B0(n4402), .B1(intDX_EWSW[11]), .Y(n1872) );
MX2X1TS U2694 ( .A(DMP_SHT2_EWSW[43]), .B(DMP_SFG[43]), .S0(n3699), .Y(n1478) );
MX2X1TS U2695 ( .A(DMP_SHT2_EWSW[45]), .B(DMP_SFG[45]), .S0(n3699), .Y(n1472) );
MX2X1TS U2696 ( .A(DMP_SHT2_EWSW[47]), .B(DMP_SFG[47]), .S0(n4476), .Y(n1466) );
MX2X1TS U2697 ( .A(DMP_SHT2_EWSW[49]), .B(DMP_SFG[49]), .S0(n3698), .Y(n1460) );
MX2X1TS U2698 ( .A(DMP_SHT2_EWSW[44]), .B(DMP_SFG[44]), .S0(n4476), .Y(n1475) );
MX2X1TS U2699 ( .A(DMP_SHT2_EWSW[46]), .B(DMP_SFG[46]), .S0(n4449), .Y(n1469) );
MX2X1TS U2700 ( .A(DMP_SHT2_EWSW[48]), .B(DMP_SFG[48]), .S0(n3702), .Y(n1463) );
MX2X1TS U2701 ( .A(DMP_SHT2_EWSW[50]), .B(DMP_SFG[50]), .S0(n3702), .Y(n1457) );
MX2X1TS U2702 ( .A(DMP_SHT2_EWSW[4]), .B(DMP_SFG[4]), .S0(n1915), .Y(n1595)
);
MX2X1TS U2703 ( .A(DMP_SHT2_EWSW[10]), .B(DMP_SFG[10]), .S0(n3699), .Y(n1577) );
MX2X1TS U2704 ( .A(DMP_SHT2_EWSW[12]), .B(DMP_SFG[12]), .S0(n3698), .Y(n1571) );
MX2X1TS U2705 ( .A(DMP_SHT2_EWSW[32]), .B(DMP_SFG[32]), .S0(n3702), .Y(n1511) );
MX2X1TS U2706 ( .A(DMP_SHT2_EWSW[34]), .B(DMP_SFG[34]), .S0(n3698), .Y(n1505) );
MX2X1TS U2707 ( .A(DMP_SHT2_EWSW[36]), .B(DMP_SFG[36]), .S0(n4476), .Y(n1499) );
MX2X1TS U2708 ( .A(DMP_SHT2_EWSW[38]), .B(DMP_SFG[38]), .S0(n3698), .Y(n1493) );
MX2X1TS U2709 ( .A(DMP_SHT2_EWSW[40]), .B(DMP_SFG[40]), .S0(n4476), .Y(n1487) );
MX2X1TS U2710 ( .A(DMP_SHT2_EWSW[0]), .B(DMP_SFG[0]), .S0(n1915), .Y(n1607)
);
OAI211X1TS U2711 ( .A0(n3556), .A1(n3599), .B0(n3172), .C0(n3171), .Y(n1725)
);
MX2X1TS U2712 ( .A(DMP_SHT2_EWSW[5]), .B(DMP_SFG[5]), .S0(n1914), .Y(n1592)
);
MX2X1TS U2713 ( .A(DMP_SHT2_EWSW[6]), .B(DMP_SFG[6]), .S0(n1914), .Y(n1589)
);
MX2X1TS U2714 ( .A(DMP_SHT2_EWSW[9]), .B(DMP_SFG[9]), .S0(n1914), .Y(n1580)
);
MX2X1TS U2715 ( .A(DMP_SHT2_EWSW[11]), .B(DMP_SFG[11]), .S0(n4476), .Y(n1574) );
MX2X1TS U2716 ( .A(DMP_SHT2_EWSW[13]), .B(DMP_SFG[13]), .S0(n3698), .Y(n1568) );
MX2X1TS U2717 ( .A(DMP_SHT2_EWSW[14]), .B(DMP_SFG[14]), .S0(n4449), .Y(n1565) );
MX2X1TS U2718 ( .A(DMP_SHT2_EWSW[17]), .B(DMP_SFG[17]), .S0(n4476), .Y(n1556) );
MX2X1TS U2719 ( .A(DMP_SHT2_EWSW[18]), .B(DMP_SFG[18]), .S0(n3699), .Y(n1553) );
MX2X1TS U2720 ( .A(DMP_SHT2_EWSW[19]), .B(DMP_SFG[19]), .S0(n3699), .Y(n1550) );
MX2X1TS U2721 ( .A(DMP_SHT2_EWSW[20]), .B(DMP_SFG[20]), .S0(n4449), .Y(n1547) );
MX2X1TS U2722 ( .A(DMP_SHT2_EWSW[21]), .B(DMP_SFG[21]), .S0(n3698), .Y(n1544) );
MX2X1TS U2723 ( .A(DMP_SHT2_EWSW[22]), .B(DMP_SFG[22]), .S0(n3702), .Y(n1541) );
MX2X1TS U2724 ( .A(DMP_SHT2_EWSW[26]), .B(DMP_SFG[26]), .S0(n3702), .Y(n1529) );
MX2X1TS U2725 ( .A(DMP_SHT2_EWSW[27]), .B(DMP_SFG[27]), .S0(n3699), .Y(n1526) );
MX2X1TS U2726 ( .A(DMP_SHT2_EWSW[28]), .B(DMP_SFG[28]), .S0(n1914), .Y(n1523) );
MX2X1TS U2727 ( .A(DMP_SHT2_EWSW[29]), .B(DMP_SFG[29]), .S0(n3702), .Y(n1520) );
MX2X1TS U2728 ( .A(DMP_SHT2_EWSW[30]), .B(DMP_SFG[30]), .S0(n3698), .Y(n1517) );
MX2X1TS U2729 ( .A(DMP_SHT2_EWSW[31]), .B(DMP_SFG[31]), .S0(n3699), .Y(n1514) );
MX2X1TS U2730 ( .A(DMP_SHT2_EWSW[33]), .B(DMP_SFG[33]), .S0(n4449), .Y(n1508) );
MX2X1TS U2731 ( .A(DMP_SHT2_EWSW[35]), .B(DMP_SFG[35]), .S0(n4449), .Y(n1502) );
MX2X1TS U2732 ( .A(DMP_SHT2_EWSW[37]), .B(DMP_SFG[37]), .S0(n4476), .Y(n1496) );
MX2X1TS U2733 ( .A(DMP_SHT2_EWSW[39]), .B(DMP_SFG[39]), .S0(n3699), .Y(n1490) );
MX2X1TS U2734 ( .A(DMP_SHT2_EWSW[41]), .B(DMP_SFG[41]), .S0(n3702), .Y(n1484) );
MX2X1TS U2735 ( .A(DMP_SHT2_EWSW[42]), .B(DMP_SFG[42]), .S0(n4476), .Y(n1481) );
MX2X1TS U2736 ( .A(DMP_SHT2_EWSW[16]), .B(DMP_SFG[16]), .S0(n3702), .Y(n1559) );
MX2X1TS U2737 ( .A(DMP_SHT2_EWSW[2]), .B(DMP_SFG[2]), .S0(n1915), .Y(n1601)
);
AO22XLTS U2738 ( .A0(n4429), .A1(Data_Y[62]), .B0(n4427), .B1(intDY_EWSW[62]), .Y(n1756) );
AO22XLTS U2739 ( .A0(n4418), .A1(Data_X[22]), .B0(n4403), .B1(intDX_EWSW[22]), .Y(n1861) );
AO22XLTS U2740 ( .A0(n4407), .A1(Data_X[19]), .B0(n4402), .B1(intDX_EWSW[19]), .Y(n1864) );
AO22XLTS U2741 ( .A0(n4404), .A1(Data_X[27]), .B0(n4403), .B1(intDX_EWSW[27]), .Y(n1856) );
AO22XLTS U2742 ( .A0(n4404), .A1(Data_X[29]), .B0(n4403), .B1(intDX_EWSW[29]), .Y(n1854) );
AO22XLTS U2743 ( .A0(n4404), .A1(Data_X[0]), .B0(n4427), .B1(intDX_EWSW[0]),
.Y(n1883) );
AO22XLTS U2744 ( .A0(n4421), .A1(Data_X[2]), .B0(n4401), .B1(intDX_EWSW[2]),
.Y(n1881) );
AO22XLTS U2745 ( .A0(n4421), .A1(Data_X[10]), .B0(n4402), .B1(intDX_EWSW[10]), .Y(n1873) );
AO22XLTS U2746 ( .A0(n4407), .A1(Data_X[16]), .B0(n4402), .B1(intDX_EWSW[16]), .Y(n1867) );
AO22XLTS U2747 ( .A0(n4409), .A1(Data_X[48]), .B0(n4408), .B1(intDX_EWSW[48]), .Y(n1835) );
AO22XLTS U2748 ( .A0(n4404), .A1(Data_X[24]), .B0(n4403), .B1(intDX_EWSW[24]), .Y(n1859) );
AO22XLTS U2749 ( .A0(n4429), .A1(Data_X[52]), .B0(n4427), .B1(intDX_EWSW[52]), .Y(n1831) );
AO22XLTS U2750 ( .A0(n4406), .A1(Data_X[37]), .B0(n4405), .B1(intDX_EWSW[37]), .Y(n1846) );
AO22XLTS U2751 ( .A0(n4421), .A1(Data_X[7]), .B0(n4401), .B1(intDX_EWSW[7]),
.Y(n1876) );
AO22XLTS U2752 ( .A0(n4415), .A1(Data_X[5]), .B0(n4401), .B1(intDX_EWSW[5]),
.Y(n1878) );
AO22XLTS U2753 ( .A0(n4411), .A1(intDX_EWSW[54]), .B0(n4414), .B1(Data_X[54]), .Y(n1829) );
AO22XLTS U2754 ( .A0(n4426), .A1(intDY_EWSW[52]), .B0(n4424), .B1(Data_Y[52]), .Y(n1766) );
AO22XLTS U2755 ( .A0(n4417), .A1(intDX_EWSW[49]), .B0(n4414), .B1(Data_X[49]), .Y(n1834) );
AO22XLTS U2756 ( .A0(n4419), .A1(intDY_EWSW[36]), .B0(n4420), .B1(Data_Y[36]), .Y(n1782) );
XOR2XLTS U2757 ( .A(n2822), .B(n2827), .Y(n2831) );
MX2X1TS U2758 ( .A(DMP_SHT2_EWSW[7]), .B(DMP_SFG[7]), .S0(n1914), .Y(n1586)
);
MX2X1TS U2759 ( .A(DMP_SHT2_EWSW[25]), .B(DMP_SFG[25]), .S0(n3698), .Y(n1532) );
MX2X1TS U2760 ( .A(DMP_SHT2_EWSW[23]), .B(DMP_SFG[23]), .S0(n3699), .Y(n1538) );
MX2X1TS U2761 ( .A(DMP_SHT2_EWSW[24]), .B(DMP_SFG[24]), .S0(n4449), .Y(n1535) );
AO22XLTS U2762 ( .A0(n4404), .A1(Data_X[13]), .B0(n4402), .B1(intDX_EWSW[13]), .Y(n1870) );
MX2X1TS U2763 ( .A(DMP_SHT2_EWSW[8]), .B(DMP_SFG[8]), .S0(n1914), .Y(n1583)
);
AO22XLTS U2764 ( .A0(n4413), .A1(intDX_EWSW[55]), .B0(n4414), .B1(Data_X[55]), .Y(n1828) );
AO22XLTS U2765 ( .A0(n4419), .A1(intDY_EWSW[39]), .B0(n4424), .B1(Data_Y[39]), .Y(n1779) );
MX2X1TS U2766 ( .A(n4384), .B(DmP_mant_SFG_SWR[38]), .S0(n3705), .Y(n1118)
);
MX2X1TS U2767 ( .A(n4288), .B(DmP_mant_SFG_SWR[36]), .S0(n4342), .Y(n1120)
);
MX2X1TS U2768 ( .A(n4289), .B(DmP_mant_SFG_SWR[34]), .S0(n3705), .Y(n1122)
);
MX2X1TS U2769 ( .A(n4295), .B(DmP_mant_SFG_SWR[32]), .S0(n4342), .Y(n1124)
);
MX2X1TS U2770 ( .A(n4379), .B(DmP_mant_SFG_SWR[22]), .S0(n4342), .Y(n1134)
);
MX2X1TS U2771 ( .A(n4376), .B(DmP_mant_SFG_SWR[20]), .S0(n4342), .Y(n1136)
);
MX2X1TS U2772 ( .A(n4327), .B(DmP_mant_SFG_SWR[18]), .S0(n4342), .Y(n1138)
);
MX2X1TS U2773 ( .A(n4375), .B(DmP_mant_SFG_SWR[16]), .S0(n4342), .Y(n1140)
);
MX2X1TS U2774 ( .A(n4287), .B(DmP_mant_SFG_SWR[37]), .S0(n4342), .Y(n1119)
);
MX2X1TS U2775 ( .A(n4382), .B(DmP_mant_SFG_SWR[33]), .S0(n4342), .Y(n1123)
);
MX2X1TS U2776 ( .A(n4378), .B(DmP_mant_SFG_SWR[21]), .S0(n4342), .Y(n1135)
);
MX2X1TS U2777 ( .A(n4328), .B(DmP_mant_SFG_SWR[17]), .S0(n4349), .Y(n1139)
);
AO22XLTS U2778 ( .A0(n4413), .A1(intDX_EWSW[53]), .B0(n4425), .B1(Data_X[53]), .Y(n1830) );
AO22XLTS U2779 ( .A0(n4411), .A1(intDX_EWSW[62]), .B0(n4422), .B1(Data_X[62]), .Y(n1821) );
AO22XLTS U2780 ( .A0(n4411), .A1(intDX_EWSW[60]), .B0(n4421), .B1(Data_X[60]), .Y(n1823) );
AO22XLTS U2781 ( .A0(n4423), .A1(intDY_EWSW[38]), .B0(n4420), .B1(Data_Y[38]), .Y(n1780) );
AO22XLTS U2782 ( .A0(n4423), .A1(intDY_EWSW[32]), .B0(n4420), .B1(Data_Y[32]), .Y(n1786) );
AO22XLTS U2783 ( .A0(n4423), .A1(intDY_EWSW[40]), .B0(n4420), .B1(Data_Y[40]), .Y(n1778) );
OAI222X1TS U2784 ( .A0(n3640), .A1(n3644), .B0(n3666), .B1(n3642), .C0(n4641), .C1(n3641), .Y(n1111) );
MX2X1TS U2785 ( .A(n4392), .B(underflow_flag), .S0(n4391), .Y(n1288) );
NOR2XLTS U2786 ( .A(n4392), .B(SIGN_FLAG_SHT1SHT2), .Y(n3671) );
AO22XLTS U2787 ( .A0(n4390), .A1(n4276), .B0(final_result_ieee[48]), .B1(
n4469), .Y(n1162) );
AO22XLTS U2788 ( .A0(n4390), .A1(n4350), .B0(final_result_ieee[2]), .B1(
n4469), .Y(n1163) );
AO22XLTS U2789 ( .A0(n4390), .A1(n4277), .B0(final_result_ieee[47]), .B1(
n4469), .Y(n1164) );
AO22XLTS U2790 ( .A0(n4381), .A1(n4348), .B0(final_result_ieee[3]), .B1(
n4469), .Y(n1165) );
AO22XLTS U2791 ( .A0(n4390), .A1(n4278), .B0(final_result_ieee[46]), .B1(
n4469), .Y(n1166) );
AO22XLTS U2792 ( .A0(n4381), .A1(n4347), .B0(final_result_ieee[4]), .B1(
n4469), .Y(n1167) );
AO22XLTS U2793 ( .A0(n4390), .A1(n4279), .B0(final_result_ieee[40]), .B1(
n4383), .Y(n1178) );
AO22XLTS U2794 ( .A0(n4385), .A1(n4280), .B0(final_result_ieee[39]), .B1(
n4469), .Y(n1180) );
AO22XLTS U2795 ( .A0(n4385), .A1(n4281), .B0(final_result_ieee[38]), .B1(
n4383), .Y(n1182) );
AO22XLTS U2796 ( .A0(n4385), .A1(n4282), .B0(final_result_ieee[37]), .B1(
n4383), .Y(n1184) );
AO22XLTS U2797 ( .A0(n4385), .A1(n4384), .B0(final_result_ieee[36]), .B1(
n4383), .Y(n1186) );
AO22XLTS U2798 ( .A0(n4381), .A1(n4375), .B0(final_result_ieee[14]), .B1(
n4377), .Y(n1187) );
AO22XLTS U2799 ( .A0(n4385), .A1(n4289), .B0(final_result_ieee[32]), .B1(
n4377), .Y(n1194) );
AO22XLTS U2800 ( .A0(n4381), .A1(n4376), .B0(final_result_ieee[18]), .B1(
n4377), .Y(n1195) );
AO22XLTS U2801 ( .A0(n4385), .A1(n4382), .B0(final_result_ieee[31]), .B1(
n4383), .Y(n1196) );
AO22XLTS U2802 ( .A0(n4381), .A1(n4378), .B0(final_result_ieee[19]), .B1(
n4377), .Y(n1197) );
AO22XLTS U2803 ( .A0(n4385), .A1(n4295), .B0(final_result_ieee[30]), .B1(
n4377), .Y(n1198) );
AO22XLTS U2804 ( .A0(n4381), .A1(n4379), .B0(final_result_ieee[20]), .B1(
n4383), .Y(n1199) );
AO22XLTS U2805 ( .A0(n4381), .A1(n4380), .B0(final_result_ieee[25]), .B1(
n4383), .Y(n1208) );
AOI2BB2XLTS U2806 ( .B0(n4390), .B1(n4389), .A0N(n1942), .A1N(
final_result_ieee[59]), .Y(n1679) );
AOI2BB2XLTS U2807 ( .B0(n4390), .B1(n4388), .A0N(n1942), .A1N(
final_result_ieee[58]), .Y(n1680) );
AOI2BB2XLTS U2808 ( .B0(n4390), .B1(n4387), .A0N(n1942), .A1N(
final_result_ieee[55]), .Y(n1683) );
AOI2BB2XLTS U2809 ( .B0(n4390), .B1(n4386), .A0N(n4675), .A1N(
final_result_ieee[54]), .Y(n1684) );
AO22XLTS U2810 ( .A0(n1942), .A1(ZERO_FLAG_SHT1SHT2), .B0(n4469), .B1(
zero_flag), .Y(n1281) );
AO22XLTS U2811 ( .A0(n4426), .A1(intDY_EWSW[55]), .B0(n4424), .B1(Data_Y[55]), .Y(n1763) );
AO22XLTS U2812 ( .A0(n4426), .A1(intDY_EWSW[54]), .B0(n4425), .B1(Data_Y[54]), .Y(n1764) );
AO22XLTS U2813 ( .A0(n4411), .A1(intDX_EWSW[56]), .B0(n4412), .B1(Data_X[56]), .Y(n1827) );
AO22XLTS U2814 ( .A0(n4428), .A1(intDY_EWSW[9]), .B0(n4410), .B1(Data_Y[9]),
.Y(n1809) );
AO22XLTS U2815 ( .A0(n4413), .A1(intDY_EWSW[19]), .B0(n4424), .B1(Data_Y[19]), .Y(n1799) );
AO22XLTS U2816 ( .A0(n4417), .A1(intDY_EWSW[27]), .B0(n4410), .B1(Data_Y[27]), .Y(n1791) );
AO22XLTS U2817 ( .A0(n4417), .A1(intDY_EWSW[21]), .B0(n4420), .B1(Data_Y[21]), .Y(n1797) );
AO22XLTS U2818 ( .A0(n4419), .A1(intDY_EWSW[31]), .B0(n4420), .B1(Data_Y[31]), .Y(n1787) );
AO22XLTS U2819 ( .A0(n4426), .A1(intDY_EWSW[57]), .B0(n4425), .B1(Data_Y[57]), .Y(n1761) );
XOR2XLTS U2820 ( .A(n4186), .B(n4185), .Y(n4191) );
AO22XLTS U2821 ( .A0(n4411), .A1(intDY_EWSW[10]), .B0(n4410), .B1(Data_Y[10]), .Y(n1808) );
AO22XLTS U2822 ( .A0(n4428), .A1(intDY_EWSW[7]), .B0(n4421), .B1(Data_Y[7]),
.Y(n1811) );
AO22XLTS U2823 ( .A0(n4428), .A1(intDY_EWSW[5]), .B0(n4415), .B1(Data_Y[5]),
.Y(n1813) );
AO22XLTS U2824 ( .A0(n4419), .A1(intDY_EWSW[33]), .B0(n4420), .B1(Data_Y[33]), .Y(n1785) );
AO22XLTS U2825 ( .A0(n4419), .A1(intDY_EWSW[35]), .B0(n4420), .B1(Data_Y[35]), .Y(n1783) );
AO22XLTS U2826 ( .A0(n4423), .A1(intDY_EWSW[41]), .B0(n4424), .B1(Data_Y[41]), .Y(n1777) );
AO22XLTS U2827 ( .A0(n4423), .A1(intDY_EWSW[43]), .B0(n4424), .B1(Data_Y[43]), .Y(n1775) );
MX2X1TS U2828 ( .A(n4281), .B(DmP_mant_SFG_SWR[40]), .S0(n3705), .Y(n1116)
);
MX2X1TS U2829 ( .A(n4347), .B(DmP_mant_SFG_SWR[6]), .S0(n4349), .Y(n1150) );
MX2X1TS U2830 ( .A(n4350), .B(DmP_mant_SFG_SWR[4]), .S0(n4349), .Y(n1152) );
MX2X1TS U2831 ( .A(n4282), .B(DmP_mant_SFG_SWR[39]), .S0(n3705), .Y(n1117)
);
MX2X1TS U2832 ( .A(n4380), .B(DmP_mant_SFG_SWR[27]), .S0(n4342), .Y(n1129)
);
AO22XLTS U2833 ( .A0(n4428), .A1(intDY_EWSW[8]), .B0(n4412), .B1(Data_Y[8]),
.Y(n1810) );
AO22XLTS U2834 ( .A0(n4419), .A1(intDY_EWSW[30]), .B0(n4424), .B1(Data_Y[30]), .Y(n1788) );
AOI2BB2XLTS U2835 ( .B0(beg_OP), .B1(n4511), .A0N(n4511), .A1N(
inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n2573) );
XOR2XLTS U2836 ( .A(n4225), .B(n4224), .Y(n4230) );
MX2X1TS U2837 ( .A(n4279), .B(DmP_mant_SFG_SWR[42]), .S0(n3705), .Y(n1114)
);
MX2X1TS U2838 ( .A(n4280), .B(DmP_mant_SFG_SWR[41]), .S0(n3705), .Y(n1115)
);
XOR2XLTS U2839 ( .A(n4114), .B(n4113), .Y(n4122) );
XOR2XLTS U2840 ( .A(n4140), .B(n4129), .Y(n4137) );
XOR2XLTS U2841 ( .A(n4248), .B(n4247), .Y(n4252) );
AO22XLTS U2842 ( .A0(n4428), .A1(intDY_EWSW[6]), .B0(n4410), .B1(Data_Y[6]),
.Y(n1812) );
AO22XLTS U2843 ( .A0(n4419), .A1(intDY_EWSW[34]), .B0(n4420), .B1(Data_Y[34]), .Y(n1784) );
OAI21XLTS U2844 ( .A0(n1899), .A1(n4612), .B0(n3618), .Y(n1754) );
MX2X1TS U2845 ( .A(n4277), .B(DmP_mant_SFG_SWR[49]), .S0(n1914), .Y(n1107)
);
MX2X1TS U2846 ( .A(n4278), .B(DmP_mant_SFG_SWR[48]), .S0(n3705), .Y(n1108)
);
MX2X1TS U2847 ( .A(n4276), .B(DmP_mant_SFG_SWR[50]), .S0(n1915), .Y(n1106)
);
XOR2XLTS U2848 ( .A(n4166), .B(n4154), .Y(n4163) );
XOR2XLTS U2849 ( .A(n4196), .B(n4195), .Y(n4205) );
OAI222X1TS U2850 ( .A0(n3643), .A1(n3639), .B0(n3640), .B1(n3638), .C0(n4635), .C1(n3637), .Y(n1146) );
OAI222X1TS U2851 ( .A0(n3645), .A1(n3639), .B0(n3670), .B1(n3638), .C0(n4642), .C1(n3641), .Y(n1112) );
OAI222X1TS U2852 ( .A0(n3640), .A1(n3628), .B0(n3643), .B1(n3627), .C0(n4643), .C1(n3641), .Y(n1113) );
OAI222X1TS U2853 ( .A0(n3670), .A1(n3647), .B0(n3645), .B1(n3646), .C0(n4656), .C1(n4286), .Y(n1154) );
OAI222X1TS U2854 ( .A0(n3668), .A1(n3647), .B0(n3643), .B1(n3646), .C0(n4657), .C1(n1913), .Y(n1104) );
MX2X1TS U2855 ( .A(n4370), .B(LZD_output_NRM2_EW[5]), .S0(n3382), .Y(n1209)
);
MX2X1TS U2856 ( .A(n4371), .B(LZD_output_NRM2_EW[3]), .S0(n4374), .Y(n1213)
);
AOI22X1TS U2857 ( .A0(n2146), .A1(n4367), .B0(Raw_mant_NRM_SWR[54]), .B1(
n3747), .Y(n2147) );
XOR2XLTS U2858 ( .A(n3734), .B(n3733), .Y(n3739) );
XOR2XLTS U2859 ( .A(n3773), .B(n3772), .Y(n3778) );
XOR2XLTS U2860 ( .A(n3754), .B(n3753), .Y(n3759) );
XOR2XLTS U2861 ( .A(n3869), .B(n3868), .Y(n3875) );
XOR2XLTS U2862 ( .A(n3846), .B(n3845), .Y(n3854) );
XOR2XLTS U2863 ( .A(n2584), .B(n2587), .Y(n2592) );
XOR2XLTS U2864 ( .A(n3884), .B(n3883), .Y(n3889) );
XOR2XLTS U2865 ( .A(n3836), .B(n3835), .Y(n3841) );
XOR2XLTS U2866 ( .A(n3804), .B(n3803), .Y(n3809) );
XOR2XLTS U2867 ( .A(n3814), .B(n3785), .Y(n3796) );
XOR2XLTS U2868 ( .A(n3908), .B(n3907), .Y(n3914) );
XOR2XLTS U2869 ( .A(n3968), .B(n3967), .Y(n3977) );
XOR2XLTS U2870 ( .A(n4355), .B(n4354), .Y(n4364) );
XOR2XLTS U2871 ( .A(n4052), .B(n4051), .Y(n4060) );
XOR2XLTS U2872 ( .A(n4014), .B(n4013), .Y(n4018) );
XOR2XLTS U2873 ( .A(n2421), .B(n2423), .Y(n2427) );
XOR2XLTS U2874 ( .A(n4087), .B(n4086), .Y(n4093) );
AO22XLTS U2875 ( .A0(n4480), .A1(SIGN_FLAG_NRM), .B0(n4627), .B1(
SIGN_FLAG_SHT1SHT2), .Y(n1271) );
AO22XLTS U2876 ( .A0(n1926), .A1(SIGN_FLAG_SFG), .B0(n4478), .B1(
SIGN_FLAG_NRM), .Y(n1272) );
AO22XLTS U2877 ( .A0(n4477), .A1(SIGN_FLAG_SHT2), .B0(n3700), .B1(
SIGN_FLAG_SFG), .Y(n1273) );
AO22XLTS U2878 ( .A0(busy), .A1(SIGN_FLAG_SHT1), .B0(n4475), .B1(
SIGN_FLAG_SHT2), .Y(n1274) );
AO22XLTS U2879 ( .A0(n4474), .A1(SIGN_FLAG_EXP), .B0(n4473), .B1(
SIGN_FLAG_SHT1), .Y(n1275) );
AO22XLTS U2880 ( .A0(busy), .A1(OP_FLAG_SHT1), .B0(n4472), .B1(OP_FLAG_SHT2),
.Y(n1279) );
AO22XLTS U2881 ( .A0(n4471), .A1(OP_FLAG_EXP), .B0(n4470), .B1(OP_FLAG_SHT1),
.Y(n1280) );
AO22XLTS U2882 ( .A0(n4468), .A1(ZERO_FLAG_NRM), .B0(n4627), .B1(
ZERO_FLAG_SHT1SHT2), .Y(n1282) );
AO22XLTS U2883 ( .A0(n1926), .A1(ZERO_FLAG_SFG), .B0(n4478), .B1(
ZERO_FLAG_NRM), .Y(n1283) );
AO22XLTS U2884 ( .A0(n4477), .A1(ZERO_FLAG_SHT2), .B0(n3700), .B1(
ZERO_FLAG_SFG), .Y(n1284) );
AO22XLTS U2885 ( .A0(busy), .A1(ZERO_FLAG_SHT1), .B0(n4475), .B1(
ZERO_FLAG_SHT2), .Y(n1285) );
AO22XLTS U2886 ( .A0(n4471), .A1(ZERO_FLAG_EXP), .B0(n4470), .B1(
ZERO_FLAG_SHT1), .Y(n1286) );
AO22XLTS U2887 ( .A0(n4471), .A1(DmP_EXP_EWSW[49]), .B0(n4470), .B1(
DmP_mant_SHT1_SW[49]), .Y(n1299) );
OAI21XLTS U2888 ( .A0(n4517), .A1(n3092), .B0(n2891), .Y(n1300) );
AO22XLTS U2889 ( .A0(n4471), .A1(DmP_EXP_EWSW[48]), .B0(n4470), .B1(
DmP_mant_SHT1_SW[48]), .Y(n1301) );
AO22XLTS U2890 ( .A0(n4471), .A1(DmP_EXP_EWSW[47]), .B0(n4470), .B1(
DmP_mant_SHT1_SW[47]), .Y(n1303) );
OAI21XLTS U2891 ( .A0(n4528), .A1(n3092), .B0(n2317), .Y(n1304) );
AO22XLTS U2892 ( .A0(n4471), .A1(DmP_EXP_EWSW[46]), .B0(n4470), .B1(
DmP_mant_SHT1_SW[46]), .Y(n1305) );
AO22XLTS U2893 ( .A0(n4471), .A1(DmP_EXP_EWSW[45]), .B0(n4470), .B1(
DmP_mant_SHT1_SW[45]), .Y(n1307) );
AO22XLTS U2894 ( .A0(n4471), .A1(DmP_EXP_EWSW[44]), .B0(n4470), .B1(
DmP_mant_SHT1_SW[44]), .Y(n1309) );
AO22XLTS U2895 ( .A0(n4471), .A1(DmP_EXP_EWSW[43]), .B0(n4470), .B1(
DmP_mant_SHT1_SW[43]), .Y(n1311) );
AO22XLTS U2896 ( .A0(n4471), .A1(DmP_EXP_EWSW[42]), .B0(n4470), .B1(
DmP_mant_SHT1_SW[42]), .Y(n1313) );
AO22XLTS U2897 ( .A0(n4463), .A1(DmP_EXP_EWSW[41]), .B0(n4462), .B1(
DmP_mant_SHT1_SW[41]), .Y(n1315) );
OAI21XLTS U2898 ( .A0(n4514), .A1(n3092), .B0(n3082), .Y(n1316) );
AO22XLTS U2899 ( .A0(n4463), .A1(DmP_EXP_EWSW[40]), .B0(n4462), .B1(
DmP_mant_SHT1_SW[40]), .Y(n1317) );
AO22XLTS U2900 ( .A0(n4463), .A1(DmP_EXP_EWSW[39]), .B0(n4462), .B1(
DmP_mant_SHT1_SW[39]), .Y(n1319) );
AO22XLTS U2901 ( .A0(n4463), .A1(DmP_EXP_EWSW[38]), .B0(n4462), .B1(
DmP_mant_SHT1_SW[38]), .Y(n1321) );
AO22XLTS U2902 ( .A0(n4463), .A1(DmP_EXP_EWSW[37]), .B0(n4462), .B1(
DmP_mant_SHT1_SW[37]), .Y(n1323) );
AO22XLTS U2903 ( .A0(n4463), .A1(DmP_EXP_EWSW[36]), .B0(n4462), .B1(
DmP_mant_SHT1_SW[36]), .Y(n1325) );
OAI21XLTS U2904 ( .A0(n4598), .A1(n3089), .B0(n2920), .Y(n1326) );
AO22XLTS U2905 ( .A0(n4463), .A1(DmP_EXP_EWSW[35]), .B0(n4462), .B1(
DmP_mant_SHT1_SW[35]), .Y(n1327) );
OAI21XLTS U2906 ( .A0(n4513), .A1(n3089), .B0(n2923), .Y(n1328) );
AO22XLTS U2907 ( .A0(n4463), .A1(DmP_EXP_EWSW[34]), .B0(n4462), .B1(
DmP_mant_SHT1_SW[34]), .Y(n1329) );
OAI21XLTS U2908 ( .A0(n4597), .A1(n3089), .B0(n3076), .Y(n1330) );
AO22XLTS U2909 ( .A0(n4463), .A1(DmP_EXP_EWSW[33]), .B0(n4462), .B1(
DmP_mant_SHT1_SW[33]), .Y(n1331) );
OAI21XLTS U2910 ( .A0(n4512), .A1(n3089), .B0(n2922), .Y(n1332) );
AO22XLTS U2911 ( .A0(n4463), .A1(DmP_EXP_EWSW[32]), .B0(n4462), .B1(
DmP_mant_SHT1_SW[32]), .Y(n1333) );
OAI21XLTS U2912 ( .A0(n4565), .A1(n3089), .B0(n3074), .Y(n1334) );
AO22XLTS U2913 ( .A0(n4461), .A1(DmP_EXP_EWSW[31]), .B0(n4460), .B1(
DmP_mant_SHT1_SW[31]), .Y(n1335) );
AO22XLTS U2914 ( .A0(n4461), .A1(DmP_EXP_EWSW[30]), .B0(n4460), .B1(
DmP_mant_SHT1_SW[30]), .Y(n1337) );
AO22XLTS U2915 ( .A0(n4461), .A1(DmP_EXP_EWSW[29]), .B0(n4460), .B1(
DmP_mant_SHT1_SW[29]), .Y(n1339) );
AO22XLTS U2916 ( .A0(n4461), .A1(DmP_EXP_EWSW[28]), .B0(n4460), .B1(
DmP_mant_SHT1_SW[28]), .Y(n1341) );
AO22XLTS U2917 ( .A0(n4461), .A1(DmP_EXP_EWSW[27]), .B0(n4460), .B1(
DmP_mant_SHT1_SW[27]), .Y(n1343) );
AO22XLTS U2918 ( .A0(n4461), .A1(DmP_EXP_EWSW[26]), .B0(n4460), .B1(
DmP_mant_SHT1_SW[26]), .Y(n1345) );
AO22XLTS U2919 ( .A0(n4461), .A1(DmP_EXP_EWSW[21]), .B0(n4460), .B1(
DmP_mant_SHT1_SW[21]), .Y(n1355) );
AO22XLTS U2920 ( .A0(n4461), .A1(DmP_EXP_EWSW[20]), .B0(n4460), .B1(
DmP_mant_SHT1_SW[20]), .Y(n1357) );
AO22XLTS U2921 ( .A0(n4461), .A1(DmP_EXP_EWSW[19]), .B0(n4460), .B1(
DmP_mant_SHT1_SW[19]), .Y(n1359) );
AO22XLTS U2922 ( .A0(n4461), .A1(DmP_EXP_EWSW[18]), .B0(n4460), .B1(
DmP_mant_SHT1_SW[18]), .Y(n1361) );
AO22XLTS U2923 ( .A0(n4457), .A1(DmP_EXP_EWSW[17]), .B0(n4456), .B1(
DmP_mant_SHT1_SW[17]), .Y(n1363) );
AO22XLTS U2924 ( .A0(n4457), .A1(DmP_EXP_EWSW[16]), .B0(n4456), .B1(
DmP_mant_SHT1_SW[16]), .Y(n1365) );
AO22XLTS U2925 ( .A0(n4457), .A1(DmP_EXP_EWSW[15]), .B0(n4456), .B1(
DmP_mant_SHT1_SW[15]), .Y(n1367) );
AO22XLTS U2926 ( .A0(n4457), .A1(DmP_EXP_EWSW[14]), .B0(n4456), .B1(
DmP_mant_SHT1_SW[14]), .Y(n1369) );
AO22XLTS U2927 ( .A0(n4457), .A1(DmP_EXP_EWSW[13]), .B0(n4456), .B1(
DmP_mant_SHT1_SW[13]), .Y(n1371) );
AO22XLTS U2928 ( .A0(n4457), .A1(DmP_EXP_EWSW[12]), .B0(n4456), .B1(
DmP_mant_SHT1_SW[12]), .Y(n1373) );
AO22XLTS U2929 ( .A0(n4457), .A1(DmP_EXP_EWSW[11]), .B0(n4456), .B1(
DmP_mant_SHT1_SW[11]), .Y(n1375) );
AO22XLTS U2930 ( .A0(n4457), .A1(DmP_EXP_EWSW[10]), .B0(n4456), .B1(
DmP_mant_SHT1_SW[10]), .Y(n1377) );
AO22XLTS U2931 ( .A0(n4457), .A1(DmP_EXP_EWSW[9]), .B0(n4456), .B1(
DmP_mant_SHT1_SW[9]), .Y(n1379) );
AO22XLTS U2932 ( .A0(n4457), .A1(DmP_EXP_EWSW[8]), .B0(n4456), .B1(
DmP_mant_SHT1_SW[8]), .Y(n1381) );
AO22XLTS U2933 ( .A0(n4455), .A1(DmP_EXP_EWSW[7]), .B0(n4454), .B1(
DmP_mant_SHT1_SW[7]), .Y(n1383) );
AO22XLTS U2934 ( .A0(n4455), .A1(DmP_EXP_EWSW[6]), .B0(n4454), .B1(
DmP_mant_SHT1_SW[6]), .Y(n1385) );
AO22XLTS U2935 ( .A0(n4455), .A1(DmP_EXP_EWSW[5]), .B0(n4454), .B1(
DmP_mant_SHT1_SW[5]), .Y(n1387) );
AO22XLTS U2936 ( .A0(n4455), .A1(DmP_EXP_EWSW[4]), .B0(n4454), .B1(
DmP_mant_SHT1_SW[4]), .Y(n1389) );
AO22XLTS U2937 ( .A0(n4455), .A1(DmP_EXP_EWSW[3]), .B0(n4454), .B1(
DmP_mant_SHT1_SW[3]), .Y(n1391) );
AO22XLTS U2938 ( .A0(n4455), .A1(DmP_EXP_EWSW[2]), .B0(n4454), .B1(
DmP_mant_SHT1_SW[2]), .Y(n1393) );
AO22XLTS U2939 ( .A0(n4455), .A1(DmP_EXP_EWSW[1]), .B0(n4454), .B1(
DmP_mant_SHT1_SW[1]), .Y(n1395) );
AO22XLTS U2940 ( .A0(n4455), .A1(DmP_EXP_EWSW[0]), .B0(n4454), .B1(
DmP_mant_SHT1_SW[0]), .Y(n1397) );
AO22XLTS U2941 ( .A0(n1926), .A1(DMP_SFG[62]), .B0(n4478), .B1(
DMP_exp_NRM_EW[10]), .Y(n1400) );
AO22XLTS U2942 ( .A0(n4477), .A1(DMP_SHT2_EWSW[62]), .B0(n3700), .B1(
DMP_SFG[62]), .Y(n1401) );
AO22XLTS U2943 ( .A0(n4453), .A1(DMP_SHT1_EWSW[62]), .B0(n4475), .B1(
DMP_SHT2_EWSW[62]), .Y(n1402) );
AO22XLTS U2944 ( .A0(n4455), .A1(DMP_EXP_EWSW[62]), .B0(n4454), .B1(
DMP_SHT1_EWSW[62]), .Y(n1403) );
AO22XLTS U2945 ( .A0(n4479), .A1(DMP_SFG[61]), .B0(n3695), .B1(
DMP_exp_NRM_EW[9]), .Y(n1405) );
AO22XLTS U2946 ( .A0(n1913), .A1(DMP_SHT2_EWSW[61]), .B0(n3700), .B1(
DMP_SFG[61]), .Y(n1406) );
AO22XLTS U2947 ( .A0(busy), .A1(DMP_SHT1_EWSW[61]), .B0(n4475), .B1(
DMP_SHT2_EWSW[61]), .Y(n1407) );
AO22XLTS U2948 ( .A0(n4455), .A1(DMP_EXP_EWSW[61]), .B0(n4454), .B1(
DMP_SHT1_EWSW[61]), .Y(n1408) );
AO22XLTS U2949 ( .A0(n4479), .A1(DMP_SFG[60]), .B0(n3695), .B1(
DMP_exp_NRM_EW[8]), .Y(n1410) );
AO22XLTS U2950 ( .A0(n4477), .A1(DMP_SHT2_EWSW[60]), .B0(n4449), .B1(
DMP_SFG[60]), .Y(n1411) );
AO22XLTS U2951 ( .A0(n1912), .A1(DMP_SHT1_EWSW[60]), .B0(n4475), .B1(
DMP_SHT2_EWSW[60]), .Y(n1412) );
AO22XLTS U2952 ( .A0(n4451), .A1(DMP_EXP_EWSW[60]), .B0(n4450), .B1(
DMP_SHT1_EWSW[60]), .Y(n1413) );
AO22XLTS U2953 ( .A0(n4479), .A1(DMP_SFG[59]), .B0(n1925), .B1(
DMP_exp_NRM_EW[7]), .Y(n1415) );
AO22XLTS U2954 ( .A0(n1913), .A1(DMP_SHT2_EWSW[59]), .B0(n3700), .B1(
DMP_SFG[59]), .Y(n1416) );
AO22XLTS U2955 ( .A0(n1911), .A1(DMP_SHT1_EWSW[59]), .B0(n4674), .B1(
DMP_SHT2_EWSW[59]), .Y(n1417) );
AO22XLTS U2956 ( .A0(n4451), .A1(DMP_EXP_EWSW[59]), .B0(n4450), .B1(
DMP_SHT1_EWSW[59]), .Y(n1418) );
AO22XLTS U2957 ( .A0(n4479), .A1(DMP_SFG[58]), .B0(n1925), .B1(
DMP_exp_NRM_EW[6]), .Y(n1420) );
AO22XLTS U2958 ( .A0(n1913), .A1(DMP_SHT2_EWSW[58]), .B0(n3700), .B1(
DMP_SFG[58]), .Y(n1421) );
AO22XLTS U2959 ( .A0(n4453), .A1(DMP_SHT1_EWSW[58]), .B0(n4472), .B1(
DMP_SHT2_EWSW[58]), .Y(n1422) );
AO22XLTS U2960 ( .A0(n4451), .A1(DMP_EXP_EWSW[58]), .B0(n4450), .B1(
DMP_SHT1_EWSW[58]), .Y(n1423) );
AO22XLTS U2961 ( .A0(n4479), .A1(DMP_SFG[57]), .B0(n4448), .B1(
DMP_exp_NRM_EW[5]), .Y(n1425) );
AO22XLTS U2962 ( .A0(n4452), .A1(DMP_SHT2_EWSW[57]), .B0(n3702), .B1(
DMP_SFG[57]), .Y(n1426) );
AO22XLTS U2963 ( .A0(n4453), .A1(DMP_SHT1_EWSW[57]), .B0(n4472), .B1(
DMP_SHT2_EWSW[57]), .Y(n1427) );
AO22XLTS U2964 ( .A0(n4451), .A1(DMP_EXP_EWSW[57]), .B0(n4450), .B1(
DMP_SHT1_EWSW[57]), .Y(n1428) );
AO22XLTS U2965 ( .A0(n1926), .A1(DMP_SFG[56]), .B0(n4448), .B1(
DMP_exp_NRM_EW[4]), .Y(n1430) );
AO22XLTS U2966 ( .A0(n1913), .A1(DMP_SHT2_EWSW[56]), .B0(n3700), .B1(
DMP_SFG[56]), .Y(n1431) );
AO22XLTS U2967 ( .A0(n4453), .A1(DMP_SHT1_EWSW[56]), .B0(n4472), .B1(
DMP_SHT2_EWSW[56]), .Y(n1432) );
AO22XLTS U2968 ( .A0(n4451), .A1(DMP_EXP_EWSW[56]), .B0(n4450), .B1(
DMP_SHT1_EWSW[56]), .Y(n1433) );
AO22XLTS U2969 ( .A0(n4479), .A1(DMP_SFG[55]), .B0(n4448), .B1(
DMP_exp_NRM_EW[3]), .Y(n1435) );
AO22XLTS U2970 ( .A0(n1913), .A1(DMP_SHT2_EWSW[55]), .B0(n3700), .B1(
DMP_SFG[55]), .Y(n1436) );
AO22XLTS U2971 ( .A0(n4453), .A1(DMP_SHT1_EWSW[55]), .B0(n4472), .B1(
DMP_SHT2_EWSW[55]), .Y(n1437) );
AO22XLTS U2972 ( .A0(n4451), .A1(DMP_EXP_EWSW[55]), .B0(n4450), .B1(
DMP_SHT1_EWSW[55]), .Y(n1438) );
AO22XLTS U2973 ( .A0(n1926), .A1(DMP_SFG[54]), .B0(n1901), .B1(
DMP_exp_NRM_EW[2]), .Y(n1440) );
AO22XLTS U2974 ( .A0(n4477), .A1(DMP_SHT2_EWSW[54]), .B0(n3698), .B1(
DMP_SFG[54]), .Y(n1441) );
AO22XLTS U2975 ( .A0(n4453), .A1(DMP_SHT1_EWSW[54]), .B0(n4472), .B1(
DMP_SHT2_EWSW[54]), .Y(n1442) );
AO22XLTS U2976 ( .A0(n4451), .A1(DMP_EXP_EWSW[54]), .B0(n4450), .B1(
DMP_SHT1_EWSW[54]), .Y(n1443) );
AO22XLTS U2977 ( .A0(n4479), .A1(DMP_SFG[53]), .B0(n1901), .B1(
DMP_exp_NRM_EW[1]), .Y(n1445) );
AO22XLTS U2978 ( .A0(n4452), .A1(DMP_SHT2_EWSW[53]), .B0(n3700), .B1(
DMP_SFG[53]), .Y(n1446) );
AO22XLTS U2979 ( .A0(n4453), .A1(DMP_SHT1_EWSW[53]), .B0(n4447), .B1(
DMP_SHT2_EWSW[53]), .Y(n1447) );
AO22XLTS U2980 ( .A0(n4451), .A1(DMP_EXP_EWSW[53]), .B0(n4450), .B1(
DMP_SHT1_EWSW[53]), .Y(n1448) );
MX2X1TS U2981 ( .A(DMP_exp_NRM2_EW[0]), .B(DMP_exp_NRM_EW[0]), .S0(n4369),
.Y(n1449) );
AO22XLTS U2982 ( .A0(n4452), .A1(DMP_SHT2_EWSW[52]), .B0(n3700), .B1(
DMP_SFG[52]), .Y(n1451) );
AO22XLTS U2983 ( .A0(n4453), .A1(DMP_SHT1_EWSW[52]), .B0(n4447), .B1(
DMP_SHT2_EWSW[52]), .Y(n1452) );
AO22XLTS U2984 ( .A0(n4451), .A1(DMP_EXP_EWSW[52]), .B0(n4450), .B1(
DMP_SHT1_EWSW[52]), .Y(n1453) );
AO22XLTS U2985 ( .A0(n4453), .A1(DMP_SHT1_EWSW[51]), .B0(n4447), .B1(
DMP_SHT2_EWSW[51]), .Y(n1455) );
AO22XLTS U2986 ( .A0(n4451), .A1(DMP_EXP_EWSW[51]), .B0(n4446), .B1(
DMP_SHT1_EWSW[51]), .Y(n1456) );
AO22XLTS U2987 ( .A0(n1912), .A1(DMP_SHT1_EWSW[50]), .B0(n4447), .B1(
DMP_SHT2_EWSW[50]), .Y(n1458) );
AO22XLTS U2988 ( .A0(n4445), .A1(DMP_EXP_EWSW[50]), .B0(n4446), .B1(
DMP_SHT1_EWSW[50]), .Y(n1459) );
AO22XLTS U2989 ( .A0(n4453), .A1(DMP_SHT1_EWSW[49]), .B0(n4472), .B1(
DMP_SHT2_EWSW[49]), .Y(n1461) );
AO22XLTS U2990 ( .A0(n4445), .A1(DMP_EXP_EWSW[49]), .B0(n4446), .B1(
DMP_SHT1_EWSW[49]), .Y(n1462) );
AO22XLTS U2991 ( .A0(busy), .A1(DMP_SHT1_EWSW[48]), .B0(n4444), .B1(
DMP_SHT2_EWSW[48]), .Y(n1464) );
AO22XLTS U2992 ( .A0(n4445), .A1(DMP_EXP_EWSW[48]), .B0(n4446), .B1(
DMP_SHT1_EWSW[48]), .Y(n1465) );
AO22XLTS U2993 ( .A0(busy), .A1(DMP_SHT1_EWSW[47]), .B0(n4444), .B1(
DMP_SHT2_EWSW[47]), .Y(n1467) );
AO22XLTS U2994 ( .A0(n4445), .A1(DMP_EXP_EWSW[47]), .B0(n4446), .B1(
DMP_SHT1_EWSW[47]), .Y(n1468) );
AO22XLTS U2995 ( .A0(busy), .A1(DMP_SHT1_EWSW[46]), .B0(n4444), .B1(
DMP_SHT2_EWSW[46]), .Y(n1470) );
AO22XLTS U2996 ( .A0(n4445), .A1(DMP_EXP_EWSW[46]), .B0(n4446), .B1(
DMP_SHT1_EWSW[46]), .Y(n1471) );
AO22XLTS U2997 ( .A0(n1912), .A1(DMP_SHT1_EWSW[45]), .B0(n4444), .B1(
DMP_SHT2_EWSW[45]), .Y(n1473) );
AO22XLTS U2998 ( .A0(n4445), .A1(DMP_EXP_EWSW[45]), .B0(n4446), .B1(
DMP_SHT1_EWSW[45]), .Y(n1474) );
AO22XLTS U2999 ( .A0(busy), .A1(DMP_SHT1_EWSW[44]), .B0(n4444), .B1(
DMP_SHT2_EWSW[44]), .Y(n1476) );
AO22XLTS U3000 ( .A0(n4445), .A1(DMP_EXP_EWSW[44]), .B0(n4446), .B1(
DMP_SHT1_EWSW[44]), .Y(n1477) );
AO22XLTS U3001 ( .A0(busy), .A1(DMP_SHT1_EWSW[43]), .B0(n4444), .B1(
DMP_SHT2_EWSW[43]), .Y(n1479) );
AO22XLTS U3002 ( .A0(n4445), .A1(DMP_EXP_EWSW[43]), .B0(n4446), .B1(
DMP_SHT1_EWSW[43]), .Y(n1480) );
AO22XLTS U3003 ( .A0(n1910), .A1(DMP_SHT1_EWSW[42]), .B0(n4444), .B1(
DMP_SHT2_EWSW[42]), .Y(n1482) );
AO22XLTS U3004 ( .A0(n4445), .A1(DMP_EXP_EWSW[42]), .B0(n4446), .B1(
DMP_SHT1_EWSW[42]), .Y(n1483) );
AO22XLTS U3005 ( .A0(n1910), .A1(DMP_SHT1_EWSW[41]), .B0(n4444), .B1(
DMP_SHT2_EWSW[41]), .Y(n1485) );
AO22XLTS U3006 ( .A0(n4445), .A1(DMP_EXP_EWSW[41]), .B0(n4443), .B1(
DMP_SHT1_EWSW[41]), .Y(n1486) );
AO22XLTS U3007 ( .A0(n1910), .A1(DMP_SHT1_EWSW[40]), .B0(n4444), .B1(
DMP_SHT2_EWSW[40]), .Y(n1488) );
AO22XLTS U3008 ( .A0(n4442), .A1(DMP_EXP_EWSW[40]), .B0(n4443), .B1(
DMP_SHT1_EWSW[40]), .Y(n1489) );
AO22XLTS U3009 ( .A0(n1910), .A1(DMP_SHT1_EWSW[39]), .B0(n4444), .B1(
DMP_SHT2_EWSW[39]), .Y(n1491) );
AO22XLTS U3010 ( .A0(n4442), .A1(DMP_EXP_EWSW[39]), .B0(n4443), .B1(
DMP_SHT1_EWSW[39]), .Y(n1492) );
AO22XLTS U3011 ( .A0(n4441), .A1(DMP_SHT1_EWSW[38]), .B0(n4447), .B1(
DMP_SHT2_EWSW[38]), .Y(n1494) );
AO22XLTS U3012 ( .A0(n4442), .A1(DMP_EXP_EWSW[38]), .B0(n4443), .B1(
DMP_SHT1_EWSW[38]), .Y(n1495) );
AO22XLTS U3013 ( .A0(n3701), .A1(DMP_SHT1_EWSW[37]), .B0(n4447), .B1(
DMP_SHT2_EWSW[37]), .Y(n1497) );
AO22XLTS U3014 ( .A0(n4442), .A1(DMP_EXP_EWSW[37]), .B0(n4443), .B1(
DMP_SHT1_EWSW[37]), .Y(n1498) );
AO22XLTS U3015 ( .A0(n4442), .A1(DMP_EXP_EWSW[36]), .B0(n4443), .B1(
DMP_SHT1_EWSW[36]), .Y(n1501) );
AO22XLTS U3016 ( .A0(n4442), .A1(DMP_EXP_EWSW[35]), .B0(n4443), .B1(
DMP_SHT1_EWSW[35]), .Y(n1504) );
AO22XLTS U3017 ( .A0(n4442), .A1(DMP_EXP_EWSW[34]), .B0(n4443), .B1(
DMP_SHT1_EWSW[34]), .Y(n1507) );
AO22XLTS U3018 ( .A0(n4442), .A1(DMP_EXP_EWSW[33]), .B0(n4443), .B1(
DMP_SHT1_EWSW[33]), .Y(n1510) );
AO22XLTS U3019 ( .A0(n4442), .A1(DMP_EXP_EWSW[32]), .B0(n4443), .B1(
DMP_SHT1_EWSW[32]), .Y(n1513) );
AO22XLTS U3020 ( .A0(n4442), .A1(DMP_EXP_EWSW[31]), .B0(n4450), .B1(
DMP_SHT1_EWSW[31]), .Y(n1516) );
AO22XLTS U3021 ( .A0(n4440), .A1(DMP_EXP_EWSW[30]), .B0(n4439), .B1(
DMP_SHT1_EWSW[30]), .Y(n1519) );
AO22XLTS U3022 ( .A0(n4440), .A1(DMP_EXP_EWSW[29]), .B0(n4439), .B1(
DMP_SHT1_EWSW[29]), .Y(n1522) );
AO22XLTS U3023 ( .A0(n4440), .A1(DMP_EXP_EWSW[28]), .B0(n4439), .B1(
DMP_SHT1_EWSW[28]), .Y(n1525) );
AO22XLTS U3024 ( .A0(n4440), .A1(DMP_EXP_EWSW[27]), .B0(n4439), .B1(
DMP_SHT1_EWSW[27]), .Y(n1528) );
AO22XLTS U3025 ( .A0(n4440), .A1(DMP_EXP_EWSW[26]), .B0(n4439), .B1(
DMP_SHT1_EWSW[26]), .Y(n1531) );
AO22XLTS U3026 ( .A0(n4440), .A1(DMP_EXP_EWSW[25]), .B0(n4439), .B1(
DMP_SHT1_EWSW[25]), .Y(n1534) );
AO22XLTS U3027 ( .A0(n4440), .A1(DMP_EXP_EWSW[24]), .B0(n4439), .B1(
DMP_SHT1_EWSW[24]), .Y(n1537) );
AO22XLTS U3028 ( .A0(n4440), .A1(DMP_EXP_EWSW[23]), .B0(n4439), .B1(
DMP_SHT1_EWSW[23]), .Y(n1540) );
AO22XLTS U3029 ( .A0(n4440), .A1(DMP_EXP_EWSW[22]), .B0(n4439), .B1(
DMP_SHT1_EWSW[22]), .Y(n1543) );
AO22XLTS U3030 ( .A0(n4440), .A1(DMP_EXP_EWSW[21]), .B0(n4439), .B1(
DMP_SHT1_EWSW[21]), .Y(n1546) );
AO22XLTS U3031 ( .A0(n4438), .A1(DMP_EXP_EWSW[20]), .B0(n4437), .B1(
DMP_SHT1_EWSW[20]), .Y(n1549) );
AO22XLTS U3032 ( .A0(n4438), .A1(DMP_EXP_EWSW[19]), .B0(n4437), .B1(
DMP_SHT1_EWSW[19]), .Y(n1552) );
AO22XLTS U3033 ( .A0(n4438), .A1(DMP_EXP_EWSW[18]), .B0(n4437), .B1(
DMP_SHT1_EWSW[18]), .Y(n1555) );
AO22XLTS U3034 ( .A0(n4438), .A1(DMP_EXP_EWSW[17]), .B0(n4437), .B1(
DMP_SHT1_EWSW[17]), .Y(n1558) );
AO22XLTS U3035 ( .A0(n4438), .A1(DMP_EXP_EWSW[16]), .B0(n4437), .B1(
DMP_SHT1_EWSW[16]), .Y(n1561) );
AO22XLTS U3036 ( .A0(n4438), .A1(DMP_EXP_EWSW[15]), .B0(n4437), .B1(
DMP_SHT1_EWSW[15]), .Y(n1564) );
AO22XLTS U3037 ( .A0(n4438), .A1(DMP_EXP_EWSW[14]), .B0(n4437), .B1(
DMP_SHT1_EWSW[14]), .Y(n1567) );
AO22XLTS U3038 ( .A0(n4438), .A1(DMP_EXP_EWSW[13]), .B0(n4437), .B1(
DMP_SHT1_EWSW[13]), .Y(n1570) );
AO22XLTS U3039 ( .A0(n4438), .A1(DMP_EXP_EWSW[12]), .B0(n4437), .B1(
DMP_SHT1_EWSW[12]), .Y(n1573) );
AO22XLTS U3040 ( .A0(n4438), .A1(DMP_EXP_EWSW[11]), .B0(n4437), .B1(
DMP_SHT1_EWSW[11]), .Y(n1576) );
AO22XLTS U3041 ( .A0(n4436), .A1(DMP_EXP_EWSW[10]), .B0(n4435), .B1(
DMP_SHT1_EWSW[10]), .Y(n1579) );
AO22XLTS U3042 ( .A0(n4436), .A1(DMP_EXP_EWSW[9]), .B0(n4435), .B1(
DMP_SHT1_EWSW[9]), .Y(n1582) );
AO22XLTS U3043 ( .A0(n4436), .A1(DMP_EXP_EWSW[8]), .B0(n4435), .B1(
DMP_SHT1_EWSW[8]), .Y(n1585) );
AO22XLTS U3044 ( .A0(n4436), .A1(DMP_EXP_EWSW[7]), .B0(n4435), .B1(
DMP_SHT1_EWSW[7]), .Y(n1588) );
AO22XLTS U3045 ( .A0(n4436), .A1(DMP_EXP_EWSW[6]), .B0(n4435), .B1(
DMP_SHT1_EWSW[6]), .Y(n1591) );
AO22XLTS U3046 ( .A0(n4436), .A1(DMP_EXP_EWSW[5]), .B0(n4435), .B1(
DMP_SHT1_EWSW[5]), .Y(n1594) );
AO22XLTS U3047 ( .A0(n4436), .A1(DMP_EXP_EWSW[4]), .B0(n4435), .B1(
DMP_SHT1_EWSW[4]), .Y(n1597) );
AO22XLTS U3048 ( .A0(n4436), .A1(DMP_EXP_EWSW[3]), .B0(n4458), .B1(
DMP_SHT1_EWSW[3]), .Y(n1600) );
AO22XLTS U3049 ( .A0(n4436), .A1(DMP_EXP_EWSW[2]), .B0(n4459), .B1(
DMP_SHT1_EWSW[2]), .Y(n1603) );
AO22XLTS U3050 ( .A0(n4436), .A1(DMP_EXP_EWSW[1]), .B0(n4459), .B1(
DMP_SHT1_EWSW[1]), .Y(n1606) );
AO22XLTS U3051 ( .A0(n4474), .A1(DMP_EXP_EWSW[0]), .B0(n4464), .B1(
DMP_SHT1_EWSW[0]), .Y(n1609) );
OAI21XLTS U3052 ( .A0(n3550), .A1(n4432), .B0(n3546), .Y(n3548) );
AO22XLTS U3053 ( .A0(n4434), .A1(n4433), .B0(ZERO_FLAG_EXP), .B1(n4432), .Y(
n1611) );
AO21XLTS U3054 ( .A0(OP_FLAG_EXP), .A1(n4432), .B0(n4433), .Y(n1612) );
OAI21XLTS U3055 ( .A0(n4565), .A1(n2314), .B0(n3100), .Y(n1643) );
OAI21XLTS U3056 ( .A0(n4502), .A1(n2314), .B0(n2932), .Y(n1644) );
OAI21XLTS U3057 ( .A0(n4564), .A1(n2914), .B0(n3094), .Y(n1645) );
OAI21XLTS U3058 ( .A0(n4501), .A1(n2930), .B0(n3102), .Y(n1646) );
OAI21XLTS U3059 ( .A0(n4563), .A1(n2314), .B0(n3095), .Y(n1647) );
OAI21XLTS U3060 ( .A0(n4495), .A1(n2314), .B0(n3107), .Y(n1648) );
OAI21XLTS U3061 ( .A0(n4562), .A1(n2314), .B0(n2933), .Y(n1649) );
OAI21XLTS U3062 ( .A0(n4494), .A1(n2314), .B0(n2936), .Y(n1650) );
OAI21XLTS U3063 ( .A0(n4561), .A1(n2314), .B0(n3098), .Y(n1651) );
OAI21XLTS U3064 ( .A0(n4507), .A1(n2314), .B0(n3111), .Y(n1665) );
OAI21XLTS U3065 ( .A0(n4595), .A1(n2930), .B0(n2848), .Y(n1674) );
MX2X1TS U3066 ( .A(Shift_amount_SHT1_EWR[5]), .B(n3712), .S0(n1953), .Y(
n1687) );
OAI21XLTS U3067 ( .A0(n1899), .A1(n3689), .B0(n3201), .Y(n1753) );
MX2X1TS U3068 ( .A(Shift_reg_FLAGS_7[2]), .B(Shift_reg_FLAGS_7[3]), .S0(
n4399), .Y(n1886) );
AO22XLTS U3069 ( .A0(n4398), .A1(Shift_reg_FLAGS_7_6), .B0(n4399), .B1(n4400), .Y(n1890) );
OR2X4TS U3070 ( .A(n3704), .B(n4468), .Y(n1899) );
INVX2TS U3071 ( .A(n4286), .Y(n3705) );
INVX2TS U3072 ( .A(n1928), .Y(n3689) );
INVX2TS U3073 ( .A(n3008), .Y(n3657) );
OR2X4TS U3074 ( .A(n2311), .B(n4432), .Y(n2314) );
NAND2X1TS U3075 ( .A(n4298), .B(n3652), .Y(n1905) );
NAND2X1TS U3076 ( .A(n4298), .B(n2982), .Y(n1906) );
BUFX3TS U3077 ( .A(n2931), .Y(n3144) );
AND2X4TS U3078 ( .A(n2311), .B(Shift_reg_FLAGS_7_6), .Y(n2892) );
BUFX3TS U3079 ( .A(n2892), .Y(n2896) );
OA21XLTS U3080 ( .A0(n1928), .A1(shift_value_SHT2_EWR[4]), .B0(n1916), .Y(
n1907) );
CLKBUFX3TS U3081 ( .A(n2708), .Y(n2704) );
MXI2X2TS U3082 ( .A(n3596), .B(n3175), .S0(n3174), .Y(n3556) );
MXI2X2TS U3083 ( .A(n3175), .B(n1904), .S0(n3174), .Y(n3600) );
CLKINVX3TS U3084 ( .A(n4480), .Y(n3323) );
CLKINVX3TS U3085 ( .A(n4480), .Y(n3376) );
INVX2TS U3086 ( .A(n4475), .Y(n1911) );
INVX2TS U3087 ( .A(n4475), .Y(n1912) );
INVX2TS U3088 ( .A(n3705), .Y(n1913) );
INVX2TS U3089 ( .A(n1913), .Y(n1914) );
INVX2TS U3090 ( .A(n1913), .Y(n1915) );
INVX2TS U3091 ( .A(n1908), .Y(n1916) );
INVX2TS U3092 ( .A(n1908), .Y(n1917) );
INVX2TS U3093 ( .A(n2988), .Y(n1919) );
INVX2TS U3094 ( .A(n2988), .Y(n1920) );
INVX2TS U3095 ( .A(n1905), .Y(n1921) );
INVX2TS U3096 ( .A(n1905), .Y(n1922) );
INVX2TS U3097 ( .A(n1906), .Y(n1923) );
INVX2TS U3098 ( .A(n1906), .Y(n1924) );
INVX2TS U3099 ( .A(n4479), .Y(n1925) );
INVX2TS U3100 ( .A(left_right_SHT2), .Y(n1927) );
INVX2TS U3101 ( .A(n1927), .Y(n1928) );
INVX2TS U3102 ( .A(n1927), .Y(n1929) );
OAI21X1TS U3103 ( .A0(n4206), .A1(n4235), .B0(n4207), .Y(n2101) );
OAI211X1TS U3104 ( .A0(n3294), .A1(n3418), .B0(n3236), .C0(n3235), .Y(n1701)
);
OAI21XLTS U3105 ( .A0(n4581), .A1(n3092), .B0(n2918), .Y(n1298) );
OAI21XLTS U3106 ( .A0(n4494), .A1(n3080), .B0(n2919), .Y(n1348) );
OAI21XLTS U3107 ( .A0(n4561), .A1(n3080), .B0(n3073), .Y(n1350) );
OAI21XLTS U3108 ( .A0(n4500), .A1(n3080), .B0(n2916), .Y(n1352) );
OAI21XLTS U3109 ( .A0(n4560), .A1(n3080), .B0(n3072), .Y(n1354) );
OAI21XLTS U3110 ( .A0(n4503), .A1(n3080), .B0(n2924), .Y(n1289) );
CLKBUFX3TS U3111 ( .A(n2726), .Y(n2709) );
OAI211XLTS U3112 ( .A0(n2747), .A1(n4505), .B0(n2746), .C0(n2745), .Y(n2749)
);
OR2X1TS U3113 ( .A(n3365), .B(n4505), .Y(n3311) );
CLKINVX3TS U3114 ( .A(n4480), .Y(n3431) );
OAI221X1TS U3115 ( .A0(n4508), .A1(intDX_EWSW[7]), .B0(n4579), .B1(
intDX_EWSW[6]), .C0(n3530), .Y(n3537) );
OAI221XLTS U3116 ( .A0(n4509), .A1(intDX_EWSW[5]), .B0(n4563), .B1(
intDX_EWSW[28]), .C0(n3531), .Y(n3536) );
NAND3X2TS U3117 ( .A(n3167), .B(n3166), .C(n3165), .Y(n3608) );
NAND3X2TS U3118 ( .A(n3347), .B(n3346), .C(n3345), .Y(n3610) );
NAND3X2TS U3119 ( .A(n3182), .B(n3181), .C(n3180), .Y(n3552) );
NAND3X2TS U3120 ( .A(n2810), .B(n2700), .C(n2699), .Y(n3338) );
NAND3X2TS U3121 ( .A(n3242), .B(n3241), .C(n3240), .Y(n3578) );
NAND3X2TS U3122 ( .A(n3373), .B(n3372), .C(n3371), .Y(n3579) );
NAND3X2TS U3123 ( .A(n3179), .B(n3178), .C(n3177), .Y(n3589) );
NAND3X2TS U3124 ( .A(n3190), .B(n3189), .C(n3188), .Y(n3340) );
NAND3X2TS U3125 ( .A(n3225), .B(n3224), .C(n3223), .Y(n3464) );
NAND3X2TS U3126 ( .A(n3248), .B(n3247), .C(n3246), .Y(n3571) );
NAND3X2TS U3127 ( .A(n3269), .B(n3268), .C(n3267), .Y(n3586) );
NAND3X2TS U3128 ( .A(n3281), .B(n3280), .C(n3279), .Y(n3567) );
NAND3X2TS U3129 ( .A(n3284), .B(n3283), .C(n3282), .Y(n3557) );
NAND3X2TS U3130 ( .A(n3311), .B(n3310), .C(n3309), .Y(n3572) );
NAND3X2TS U3131 ( .A(n3314), .B(n3313), .C(n3312), .Y(n3566) );
NAND3X2TS U3132 ( .A(n3406), .B(n3405), .C(n3404), .Y(n3466) );
NAND3X2TS U3133 ( .A(n3409), .B(n3408), .C(n3407), .Y(n3456) );
NAND3X2TS U3134 ( .A(n3434), .B(n3433), .C(n3432), .Y(n3454) );
INVX2TS U3135 ( .A(n3339), .Y(n1930) );
CLKINVX3TS U3136 ( .A(n2658), .Y(n3651) );
CLKINVX3TS U3137 ( .A(n2658), .Y(n2869) );
NAND2X2TS U3138 ( .A(shift_value_SHT2_EWR[3]), .B(bit_shift_SHT2), .Y(n2645)
);
OAI21XLTS U3139 ( .A0(n4331), .A1(n4330), .B0(n4291), .Y(n4284) );
OAI21XLTS U3140 ( .A0(n4331), .A1(n4310), .B0(n4291), .Y(n2841) );
OAI21XLTS U3141 ( .A0(n4331), .A1(n4320), .B0(n4291), .Y(n2837) );
OAI211XLTS U3142 ( .A0(n4320), .A1(n4292), .B0(n4291), .C0(n2675), .Y(n2676)
);
OAI211XLTS U3143 ( .A0(n4330), .A1(n4292), .B0(n4291), .C0(n2670), .Y(n2671)
);
OAI21X4TS U3144 ( .A0(shift_value_SHT2_EWR[4]), .A1(n1903), .B0(n1917), .Y(
n4291) );
INVX2TS U3145 ( .A(n1907), .Y(n1931) );
CLKINVX3TS U3146 ( .A(Shift_reg_FLAGS_7[1]), .Y(n4374) );
OAI221XLTS U3147 ( .A0(n4499), .A1(intDX_EWSW[21]), .B0(n4566), .B1(
intDX_EWSW[48]), .C0(n3515), .Y(n3520) );
AOI211X1TS U3148 ( .A0(intDX_EWSW[48]), .A1(n4566), .B0(n2209), .C0(n2215),
.Y(n2167) );
OAI21XLTS U3149 ( .A0(n4566), .A1(n3092), .B0(n3084), .Y(n1302) );
OAI221X1TS U3150 ( .A0(n4498), .A1(intDX_EWSW[15]), .B0(n4557), .B1(
intDX_EWSW[14]), .C0(n3522), .Y(n3529) );
OAI221X1TS U3151 ( .A0(n4496), .A1(intDX_EWSW[3]), .B0(n4553), .B1(
intDX_EWSW[2]), .C0(n3532), .Y(n3535) );
OAI211XLTS U3152 ( .A0(n2941), .A1(n4604), .B0(n2878), .C0(n3024), .Y(n2879)
);
OAI211XLTS U3153 ( .A0(n4618), .A1(n2941), .B0(n2885), .C0(n3024), .Y(n2886)
);
OAI211XLTS U3154 ( .A0(n2941), .A1(n4605), .B0(n2940), .C0(n3024), .Y(n2942)
);
OAI211XLTS U3155 ( .A0(n4621), .A1(n2988), .B0(n2987), .C0(n3024), .Y(n2989)
);
OAI211XLTS U3156 ( .A0(n3008), .A1(n4622), .B0(n3007), .C0(n3024), .Y(n3009)
);
NAND2X4TS U3157 ( .A(n1916), .B(shift_value_SHT2_EWR[4]), .Y(n3024) );
INVX2TS U3158 ( .A(n3657), .Y(n1932) );
INVX2TS U3159 ( .A(n1932), .Y(n1933) );
INVX2TS U3160 ( .A(n1932), .Y(n1934) );
CLKBUFX3TS U3161 ( .A(n2704), .Y(n2710) );
CLKBUFX3TS U3162 ( .A(n2703), .Y(n2707) );
OAI222X1TS U3163 ( .A0(n4465), .A1(n4531), .B0(n1959), .B1(n4466), .C0(n1987), .C1(n4467), .Y(n1622) );
AOI211X4TS U3164 ( .A0(n4296), .A1(n2843), .B0(n2329), .C0(n2328), .Y(n2732)
);
OAI21XLTS U3165 ( .A0(DmP_EXP_EWSW[55]), .A1(n1960), .B0(n4261), .Y(n4262)
);
CLKINVX3TS U3166 ( .A(n2866), .Y(n2870) );
CLKINVX3TS U3167 ( .A(n2866), .Y(n2959) );
OR2X4TS U3168 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n2866) );
OAI21X2TS U3169 ( .A0(n3000), .A1(n3648), .B0(n3005), .Y(n3644) );
AOI21X2TS U3170 ( .A0(n2949), .A1(n3022), .B0(n2948), .Y(n3626) );
INVX2TS U3171 ( .A(n1900), .Y(n1935) );
AOI21X2TS U3172 ( .A0(n2862), .A1(n3649), .B0(n3648), .Y(n3647) );
INVX2TS U3173 ( .A(n1902), .Y(n1936) );
OAI21X2TS U3174 ( .A0(n3006), .A1(n3648), .B0(n3005), .Y(n3639) );
OAI21X2TS U3175 ( .A0(n4297), .A1(n3648), .B0(n3005), .Y(n3628) );
OAI21X2TS U3176 ( .A0(n2971), .A1(n3648), .B0(n3005), .Y(n3636) );
OAI211X4TS U3177 ( .A0(n2658), .A1(n4609), .B0(n2618), .C0(n2986), .Y(n2971)
);
AOI221X1TS U3178 ( .A0(n4598), .A1(intDX_EWSW[36]), .B0(intDX_EWSW[37]),
.B1(n4525), .C0(n3501), .Y(n3502) );
AOI221X1TS U3179 ( .A0(n4595), .A1(intDX_EWSW[1]), .B0(intDX_EWSW[33]), .B1(
n4512), .C0(n3499), .Y(n3504) );
OAI221X1TS U3180 ( .A0(n4504), .A1(intDY_EWSW[62]), .B0(n4568), .B1(
intDY_EWSW[61]), .C0(n3480), .Y(n3483) );
OAI21XLTS U3181 ( .A0(n4553), .A1(n2930), .B0(n2852), .Y(n1673) );
OAI221XLTS U3182 ( .A0(n4490), .A1(intDX_EWSW[0]), .B0(n4555), .B1(
intDX_EWSW[8]), .C0(n3533), .Y(n3534) );
OAI222X4TS U3183 ( .A0(n4467), .A1(n4531), .B0(n4486), .B1(n4466), .C0(n1987), .C1(n4465), .Y(n1293) );
OAI221X1TS U3184 ( .A0(n4582), .A1(intDY_EWSW[58]), .B0(n4503), .B1(
intDX_EWSW[57]), .C0(n3478), .Y(n3485) );
AOI221X1TS U3185 ( .A0(n4601), .A1(intDX_EWSW[44]), .B0(intDX_EWSW[45]),
.B1(n4527), .C0(n3493), .Y(n3494) );
AOI221X1TS U3186 ( .A0(n4600), .A1(intDX_EWSW[42]), .B0(intDX_EWSW[43]),
.B1(n4515), .C0(n3490), .Y(n3497) );
AOI221X1TS U3187 ( .A0(n4597), .A1(intDX_EWSW[34]), .B0(intDX_EWSW[35]),
.B1(n4513), .C0(n3498), .Y(n3505) );
OAI221XLTS U3188 ( .A0(n4516), .A1(intDX_EWSW[11]), .B0(n4581), .B1(
intDX_EWSW[50]), .C0(n3474), .Y(n3475) );
OAI221X1TS U3189 ( .A0(n4495), .A1(intDX_EWSW[27]), .B0(n4562), .B1(
intDX_EWSW[26]), .C0(n3508), .Y(n3511) );
OAI221X1TS U3190 ( .A0(n4493), .A1(intDX_EWSW[19]), .B0(n4558), .B1(
intDX_EWSW[18]), .C0(n3516), .Y(n3519) );
OAI221X1TS U3191 ( .A0(n4502), .A1(intDX_EWSW[31]), .B0(n4564), .B1(
intDX_EWSW[30]), .C0(n3506), .Y(n3513) );
OAI221XLTS U3192 ( .A0(n4494), .A1(intDX_EWSW[25]), .B0(n4565), .B1(
intDX_EWSW[32]), .C0(n3509), .Y(n3510) );
OAI221X1TS U3193 ( .A0(n4500), .A1(intDX_EWSW[23]), .B0(n4560), .B1(
intDX_EWSW[22]), .C0(n3514), .Y(n3521) );
OAI221XLTS U3194 ( .A0(n4492), .A1(intDX_EWSW[17]), .B0(n4561), .B1(
intDX_EWSW[24]), .C0(n3517), .Y(n3518) );
AOI222X1TS U3195 ( .A0(intDX_EWSW[4]), .A1(n4554), .B0(intDX_EWSW[5]), .B1(
n2245), .C0(n2244), .C1(n2243), .Y(n2249) );
OAI221XLTS U3196 ( .A0(n4497), .A1(intDX_EWSW[13]), .B0(n4554), .B1(
intDX_EWSW[4]), .C0(n3523), .Y(n3528) );
AOI222X4TS U3197 ( .A0(n2939), .A1(Data_array_SWR[33]), .B0(n2938), .B1(
Data_array_SWR[29]), .C0(n3653), .C1(Data_array_SWR[25]), .Y(n2997) );
INVX2TS U3198 ( .A(n1909), .Y(n1937) );
AOI32X1TS U3199 ( .A0(n2151), .A1(n2150), .A2(intDY_EWSW[58]), .B0(
intDY_EWSW[59]), .B1(n4524), .Y(n2152) );
OAI221XLTS U3200 ( .A0(n4583), .A1(intDY_EWSW[60]), .B0(n4524), .B1(
intDY_EWSW[59]), .C0(n3481), .Y(n3482) );
OAI2BB2XLTS U3201 ( .B0(intDX_EWSW[12]), .B1(n2258), .A0N(intDY_EWSW[13]),
.A1N(n1954), .Y(n2271) );
OAI221X1TS U3202 ( .A0(n4507), .A1(intDX_EWSW[10]), .B0(n4556), .B1(
intDX_EWSW[12]), .C0(n3524), .Y(n3527) );
OAI221XLTS U3203 ( .A0(n4491), .A1(intDX_EWSW[9]), .B0(n4578), .B1(
intDX_EWSW[16]), .C0(n3525), .Y(n3526) );
INVX2TS U3204 ( .A(n4340), .Y(n1938) );
INVX2TS U3205 ( .A(n4340), .Y(n4323) );
OAI21XLTS U3206 ( .A0(n2728), .A1(n4458), .B0(n2727), .Y(n1692) );
NOR2BX1TS U3207 ( .AN(LZD_output_NRM2_EW[1]), .B(ADD_OVRFLW_NRM2), .Y(n2334)
);
NOR4X2TS U3208 ( .A(n3545), .B(n3544), .C(n3543), .D(n3542), .Y(n4434) );
CLKINVX3TS U3209 ( .A(n1899), .Y(n3468) );
CLKINVX3TS U3210 ( .A(n1899), .Y(n3604) );
CLKINVX3TS U3211 ( .A(n1899), .Y(n3425) );
CLKINVX3TS U3212 ( .A(n1899), .Y(n3448) );
INVX2TS U3213 ( .A(n1939), .Y(n1940) );
NOR2X2TS U3214 ( .A(n2567), .B(n2566), .Y(n3156) );
INVX2TS U3215 ( .A(n4167), .Y(n4169) );
OAI21XLTS U3216 ( .A0(n4173), .A1(n4167), .B0(n4168), .Y(n2722) );
NOR2X2TS U3217 ( .A(DMP_SFG[8]), .B(DmP_mant_SFG_SWR[10]), .Y(n4167) );
NOR2X2TS U3218 ( .A(n3153), .B(n3152), .Y(n3232) );
NAND3X2TS U3219 ( .A(n3193), .B(n3192), .C(n3191), .Y(n3396) );
NAND3X2TS U3220 ( .A(n3364), .B(n3363), .C(n3362), .Y(n3455) );
NAND3X2TS U3221 ( .A(n3368), .B(n3367), .C(n3366), .Y(n3453) );
NAND3X2TS U3222 ( .A(n3210), .B(n3209), .C(n3208), .Y(n3352) );
NAND3X2TS U3223 ( .A(n3329), .B(n3328), .C(n3327), .Y(n3602) );
NAND3X2TS U3224 ( .A(n3272), .B(n3271), .C(n3270), .Y(n3587) );
NAND3X2TS U3225 ( .A(n3379), .B(n3378), .C(n3377), .Y(n3591) );
NAND3X2TS U3226 ( .A(n3239), .B(n3238), .C(n3237), .Y(n3581) );
NAND3X2TS U3227 ( .A(n3245), .B(n3244), .C(n3243), .Y(n3573) );
NAND3X2TS U3228 ( .A(n3307), .B(n3306), .C(n3305), .Y(n3574) );
NAND3X2TS U3229 ( .A(n3290), .B(n3289), .C(n3288), .Y(n3565) );
NAND3X2TS U3230 ( .A(n3187), .B(n3186), .C(n3185), .Y(n3256) );
NOR2X2TS U3231 ( .A(Raw_mant_NRM_SWR[6]), .B(Raw_mant_NRM_SWR[5]), .Y(n2772)
);
OAI21X2TS U3232 ( .A0(n4310), .A1(n2323), .B0(n2882), .Y(n2730) );
NOR2X2TS U3233 ( .A(n3151), .B(n3150), .Y(n3294) );
CLKINVX3TS U3234 ( .A(n2393), .Y(n3664) );
NOR2X2TS U3235 ( .A(DMP_SFG[15]), .B(DmP_mant_SFG_SWR[17]), .Y(n2418) );
CLKBUFX3TS U3236 ( .A(n2705), .Y(n2706) );
OAI211XLTS U3237 ( .A0(n2856), .A1(n4320), .B0(n2643), .C0(n2642), .Y(n2644)
);
OAI211XLTS U3238 ( .A0(n2856), .A1(n4310), .B0(n2635), .C0(n2634), .Y(n2636)
);
OAI211XLTS U3239 ( .A0(n2856), .A1(n4330), .B0(n2628), .C0(n2627), .Y(n2629)
);
NOR2XLTS U3240 ( .A(n2839), .B(n2856), .Y(n2328) );
NAND2X2TS U3241 ( .A(shift_value_SHT2_EWR[4]), .B(shift_value_SHT2_EWR[5]),
.Y(n2856) );
INVX2TS U3242 ( .A(n4325), .Y(n1941) );
NAND2X4TS U3243 ( .A(n4298), .B(n1928), .Y(n4325) );
AOI222X1TS U3244 ( .A0(n3148), .A1(intDX_EWSW[52]), .B0(DmP_EXP_EWSW[52]),
.B1(n4432), .C0(intDY_EWSW[52]), .C1(n3057), .Y(n2854) );
NOR2X2TS U3245 ( .A(DMP_SFG[3]), .B(DmP_mant_SFG_SWR[5]), .Y(n4206) );
INVX2TS U3246 ( .A(n4469), .Y(n1942) );
NAND2X2TS U3247 ( .A(n2352), .B(n4675), .Y(n4393) );
BUFX3TS U3248 ( .A(n2955), .Y(n4469) );
AOI21X2TS U3249 ( .A0(n3000), .A1(n4296), .B0(n2999), .Y(n3623) );
AOI21X2TS U3250 ( .A0(n3006), .A1(n4296), .B0(n2964), .Y(n3620) );
OAI211X4TS U3251 ( .A0(n2658), .A1(n4607), .B0(n2657), .C0(n2986), .Y(n3006)
);
OAI21X2TS U3252 ( .A0(n2949), .A1(n3648), .B0(n3005), .Y(n3634) );
NAND2X1TS U3253 ( .A(n2490), .B(Raw_mant_NRM_SWR[19]), .Y(n2549) );
BUFX3TS U3254 ( .A(n4674), .Y(n4444) );
OAI21XLTS U3255 ( .A0(n4431), .A1(intDX_EWSW[63]), .B0(n4466), .Y(n4430) );
OR2X1TS U3256 ( .A(n4641), .B(DMP_SFG[43]), .Y(n2083) );
OR2X1TS U3257 ( .A(n4640), .B(DMP_SFG[45]), .Y(n2087) );
OR2X1TS U3258 ( .A(n4613), .B(DMP_SFG[47]), .Y(n2091) );
OR2X1TS U3259 ( .A(n4639), .B(DMP_SFG[49]), .Y(n2095) );
OR2X1TS U3260 ( .A(DMP_SFG[44]), .B(DmP_mant_SFG_SWR[46]), .Y(n3867) );
OR2X1TS U3261 ( .A(DMP_SFG[46]), .B(DmP_mant_SFG_SWR[48]), .Y(n3752) );
OR2X1TS U3262 ( .A(DMP_SFG[48]), .B(DmP_mant_SFG_SWR[50]), .Y(n3771) );
OR2X1TS U3263 ( .A(DMP_SFG[50]), .B(DmP_mant_SFG_SWR[52]), .Y(n3732) );
NOR2X2TS U3264 ( .A(DMP_SFG[32]), .B(DmP_mant_SFG_SWR[34]), .Y(n2680) );
NAND2X1TS U3265 ( .A(DMP_SFG[0]), .B(DmP_mant_SFG_SWR[2]), .Y(n4265) );
INVX2TS U3266 ( .A(n1943), .Y(n1944) );
INVX2TS U3267 ( .A(n1945), .Y(n1946) );
INVX2TS U3268 ( .A(n1947), .Y(n1948) );
NOR2X1TS U3269 ( .A(DMP_SFG[14]), .B(DmP_mant_SFG_SWR[16]), .Y(n2416) );
NOR2X1TS U3270 ( .A(n4542), .B(DMP_SFG[16]), .Y(n2027) );
OAI21X4TS U3271 ( .A0(n2866), .A1(Data_array_SWR[53]), .B0(n2865), .Y(n4330)
);
OAI21X4TS U3272 ( .A0(n2866), .A1(Data_array_SWR[52]), .B0(n2865), .Y(n4310)
);
OAI21X4TS U3273 ( .A0(n2866), .A1(Data_array_SWR[51]), .B0(n2865), .Y(n4320)
);
NOR2X1TS U3274 ( .A(n4545), .B(DMP_SFG[2]), .Y(n1999) );
NAND2X1TS U3275 ( .A(DMP_SFG[2]), .B(DmP_mant_SFG_SWR[4]), .Y(n4235) );
OAI21XLTS U3276 ( .A0(intDX_EWSW[1]), .A1(n2239), .B0(intDX_EWSW[0]), .Y(
n2238) );
NOR2XLTS U3277 ( .A(n2259), .B(intDX_EWSW[10]), .Y(n2260) );
NOR2XLTS U3278 ( .A(n2280), .B(intDX_EWSW[16]), .Y(n2281) );
NOR2XLTS U3279 ( .A(n2209), .B(intDX_EWSW[48]), .Y(n2210) );
NOR2XLTS U3280 ( .A(n2292), .B(intDX_EWSW[24]), .Y(n2227) );
AOI211X2TS U3281 ( .A0(intDX_EWSW[44]), .A1(n2171), .B0(n2170), .C0(n2177),
.Y(n2185) );
NOR2XLTS U3282 ( .A(n2170), .B(intDX_EWSW[44]), .Y(n2168) );
NAND2X1TS U3283 ( .A(n4525), .B(intDX_EWSW[37]), .Y(n2191) );
OAI21XLTS U3284 ( .A0(intDX_EWSW[37]), .A1(n4525), .B0(n2186), .Y(n2196) );
OR2X1TS U3285 ( .A(Raw_mant_NRM_SWR[16]), .B(Raw_mant_NRM_SWR[15]), .Y(n1977) );
OR4X2TS U3286 ( .A(n2305), .B(n2304), .C(n2303), .D(n2302), .Y(n1982) );
AND2X4TS U3287 ( .A(n3176), .B(n3174), .Y(n1995) );
OAI21XLTS U3288 ( .A0(intDY_EWSW[3]), .A1(n1949), .B0(intDY_EWSW[2]), .Y(
n2242) );
OAI21XLTS U3289 ( .A0(Raw_mant_NRM_SWR[50]), .A1(n4483), .B0(n4522), .Y(
n2530) );
OAI21XLTS U3290 ( .A0(n2380), .A1(n3722), .B0(n2381), .Y(n2124) );
INVX2TS U3291 ( .A(n2758), .Y(n2533) );
OAI21XLTS U3292 ( .A0(n2509), .A1(n2508), .B0(n2507), .Y(n2511) );
NOR2X1TS U3293 ( .A(n3720), .B(n2049), .Y(n2051) );
OAI2BB2XLTS U3294 ( .B0(intDX_EWSW[20]), .B1(n2279), .A0N(intDY_EWSW[21]),
.A1N(n1966), .Y(n2290) );
OAI21XLTS U3295 ( .A0(Raw_mant_NRM_SWR[16]), .A1(n4521), .B0(n4588), .Y(
n2537) );
NAND2X1TS U3296 ( .A(n2373), .B(n2129), .Y(n2115) );
OR2X1TS U3297 ( .A(Raw_mant_NRM_SWR[20]), .B(Raw_mant_NRM_SWR[19]), .Y(n2535) );
NOR2XLTS U3298 ( .A(Raw_mant_NRM_SWR[34]), .B(Raw_mant_NRM_SWR[32]), .Y(
n2741) );
NAND2X1TS U3299 ( .A(n3786), .B(n2133), .Y(n2812) );
OAI21X1TS U3300 ( .A0(n2410), .A1(n2112), .B0(n2111), .Y(n2113) );
INVX2TS U3301 ( .A(n4115), .Y(n4118) );
NOR2XLTS U3302 ( .A(n4656), .B(DMP_SFG[0]), .Y(n1997) );
INVX2TS U3303 ( .A(n4156), .Y(n4141) );
OR2X1TS U3304 ( .A(n2555), .B(n2554), .Y(n2556) );
INVX2TS U3305 ( .A(n3782), .Y(n3784) );
INVX2TS U3306 ( .A(n3915), .Y(n3917) );
OR2X1TS U3307 ( .A(n3429), .B(n4533), .Y(n3187) );
OAI21XLTS U3308 ( .A0(n4330), .A1(n4329), .B0(n1931), .Y(n4336) );
OAI211XLTS U3309 ( .A0(n4310), .A1(n4292), .B0(n4291), .C0(n4290), .Y(n4293)
);
INVX2TS U3310 ( .A(n4178), .Y(n4181) );
INVX2TS U3311 ( .A(n2409), .Y(n4173) );
INVX2TS U3312 ( .A(n3876), .Y(n3879) );
INVX2TS U3313 ( .A(n3798), .Y(n3799) );
INVX2TS U3314 ( .A(n2574), .Y(n3849) );
OAI21X1TS U3315 ( .A0(n2041), .A1(n3927), .B0(n2040), .Y(n3949) );
OAI21XLTS U3316 ( .A0(n4055), .A1(n4054), .B0(n4053), .Y(n4057) );
INVX2TS U3317 ( .A(n4080), .Y(n4083) );
OR2X1TS U3318 ( .A(n3374), .B(n4625), .Y(n3290) );
OR2X1TS U3319 ( .A(n3374), .B(n4521), .Y(n3248) );
OR2X1TS U3320 ( .A(n3374), .B(n4661), .Y(n3379) );
OR2X1TS U3321 ( .A(n3618), .B(n4510), .Y(n3347) );
OR2X1TS U3322 ( .A(n3365), .B(n4592), .Y(n3225) );
OR2X1TS U3323 ( .A(n3429), .B(n4673), .Y(n3364) );
OR2X1TS U3324 ( .A(n3429), .B(n4670), .Y(n2698) );
AOI211XLTS U3325 ( .A0(n4338), .A1(n4308), .B0(n2395), .C0(n2394), .Y(n2396)
);
AOI21X2TS U3326 ( .A0(n3133), .A1(n2099), .B0(n2098), .Y(n2100) );
OAI21XLTS U3327 ( .A0(n3940), .A1(n3939), .B0(n3938), .Y(n3943) );
OAI21XLTS U3328 ( .A0(n4044), .A1(n4038), .B0(n4039), .Y(n2437) );
OAI21XLTS U3329 ( .A0(DmP_EXP_EWSW[53]), .A1(n1959), .B0(n4253), .Y(n4254)
);
INVX2TS U3330 ( .A(DmP_mant_SFG_SWR[0]), .Y(n4272) );
CLKBUFX2TS U3331 ( .A(n4414), .Y(n4422) );
AND3X1TS U3332 ( .A(n3213), .B(n3212), .C(n3211), .Y(n3263) );
AFHCINX2TS U3333 ( .CIN(n2347), .B(n2348), .A(DMP_exp_NRM2_EW[5]), .S(n2446),
.CO(n2362) );
BUFX3TS U3334 ( .A(n2930), .Y(n3121) );
BUFX3TS U3335 ( .A(n2930), .Y(n3117) );
BUFX3TS U3336 ( .A(n2930), .Y(n3104) );
AND3X1TS U3337 ( .A(n3231), .B(n3230), .C(n3229), .Y(n3559) );
AND3X1TS U3338 ( .A(n3300), .B(n3299), .C(n3298), .Y(n3570) );
AND3X1TS U3339 ( .A(n3385), .B(n3384), .C(n3383), .Y(n3585) );
INVX2TS U3340 ( .A(n3176), .Y(n3555) );
AND3X1TS U3341 ( .A(n3170), .B(n3169), .C(n3168), .Y(n3391) );
AND3X1TS U3342 ( .A(n3219), .B(n3218), .C(n3217), .Y(n3332) );
AND3X1TS U3343 ( .A(n3360), .B(n3359), .C(n3358), .Y(n3399) );
BUFX3TS U3344 ( .A(n4418), .Y(n4415) );
OAI2BB1X1TS U3345 ( .A0N(n4174), .A1N(n2831), .B0(n2830), .Y(n1228) );
OAI2BB1X1TS U3346 ( .A0N(n4174), .A1N(n2389), .B0(n2388), .Y(n1236) );
NAND2X1TS U3347 ( .A(n4489), .B(n4272), .Y(n4267) );
NAND2X1TS U3348 ( .A(n4656), .B(DMP_SFG[0]), .Y(n1996) );
OAI21X1TS U3349 ( .A0(n4267), .A1(n1997), .B0(n1996), .Y(n4231) );
NOR2X1TS U3350 ( .A(n4653), .B(DMP_SFG[1]), .Y(n4233) );
NAND2X1TS U3351 ( .A(n4653), .B(DMP_SFG[1]), .Y(n4232) );
NAND2X1TS U3352 ( .A(n4545), .B(DMP_SFG[2]), .Y(n1998) );
AOI21X1TS U3353 ( .A0(n4231), .A1(n2001), .B0(n2000), .Y(n4123) );
NOR2X1TS U3354 ( .A(n1976), .B(DMP_SFG[3]), .Y(n4217) );
NOR2X1TS U3355 ( .A(n4544), .B(DMP_SFG[4]), .Y(n2003) );
NOR2X1TS U3356 ( .A(n4217), .B(n2003), .Y(n4125) );
NOR2X1TS U3357 ( .A(n4652), .B(DMP_SFG[5]), .Y(n4139) );
NOR2X1TS U3358 ( .A(n4636), .B(DMP_SFG[6]), .Y(n2005) );
NOR2X1TS U3359 ( .A(n4139), .B(n2005), .Y(n2007) );
NAND2X1TS U3360 ( .A(n4125), .B(n2007), .Y(n2009) );
NAND2X1TS U3361 ( .A(n1976), .B(DMP_SFG[3]), .Y(n4218) );
NAND2X1TS U3362 ( .A(n4544), .B(DMP_SFG[4]), .Y(n2002) );
OAI21X1TS U3363 ( .A0(n2003), .A1(n4218), .B0(n2002), .Y(n4124) );
NAND2X1TS U3364 ( .A(n4652), .B(DMP_SFG[5]), .Y(n4138) );
NAND2X1TS U3365 ( .A(n4636), .B(DMP_SFG[6]), .Y(n2004) );
AOI21X1TS U3366 ( .A0(n4124), .A1(n2007), .B0(n2006), .Y(n2008) );
NOR2X1TS U3367 ( .A(n4651), .B(DMP_SFG[7]), .Y(n4165) );
NOR2X1TS U3368 ( .A(n4635), .B(DMP_SFG[8]), .Y(n2011) );
NOR2X1TS U3369 ( .A(n4165), .B(n2011), .Y(n2713) );
NOR2X1TS U3370 ( .A(n4650), .B(DMP_SFG[9]), .Y(n4107) );
NOR2X1TS U3371 ( .A(n4638), .B(DMP_SFG[10]), .Y(n2013) );
NOR2X1TS U3372 ( .A(n4655), .B(DMP_SFG[11]), .Y(n4178) );
NOR2X1TS U3373 ( .A(n4637), .B(DMP_SFG[12]), .Y(n2017) );
NOR2X1TS U3374 ( .A(n4178), .B(n2017), .Y(n4076) );
NOR2X1TS U3375 ( .A(n4654), .B(DMP_SFG[13]), .Y(n4080) );
NOR2X1TS U3376 ( .A(n4543), .B(DMP_SFG[14]), .Y(n2019) );
NAND2X1TS U3377 ( .A(n4651), .B(DMP_SFG[7]), .Y(n4164) );
NAND2X1TS U3378 ( .A(n4635), .B(DMP_SFG[8]), .Y(n2010) );
OAI21X1TS U3379 ( .A0(n2011), .A1(n4164), .B0(n2010), .Y(n2714) );
NAND2X1TS U3380 ( .A(n4650), .B(DMP_SFG[9]), .Y(n4108) );
NAND2X1TS U3381 ( .A(n4638), .B(DMP_SFG[10]), .Y(n2012) );
AOI21X1TS U3382 ( .A0(n2714), .A1(n2015), .B0(n2014), .Y(n4074) );
NAND2X1TS U3383 ( .A(n4655), .B(DMP_SFG[11]), .Y(n4179) );
NAND2X1TS U3384 ( .A(n4637), .B(DMP_SFG[12]), .Y(n2016) );
OAI21X1TS U3385 ( .A0(n2017), .A1(n4179), .B0(n2016), .Y(n4077) );
NAND2X1TS U3386 ( .A(n4654), .B(DMP_SFG[13]), .Y(n4081) );
NAND2X1TS U3387 ( .A(n4543), .B(DMP_SFG[14]), .Y(n2018) );
AOI21X1TS U3388 ( .A0(n4077), .A1(n2021), .B0(n2020), .Y(n2022) );
OAI21X1TS U3389 ( .A0(n4074), .A1(n2023), .B0(n2022), .Y(n2024) );
NOR2X1TS U3390 ( .A(n4551), .B(DMP_SFG[15]), .Y(n4007) );
NOR2X1TS U3391 ( .A(n4007), .B(n2027), .Y(n3995) );
NOR2X1TS U3392 ( .A(n4649), .B(DMP_SFG[17]), .Y(n3997) );
NOR2X1TS U3393 ( .A(n4541), .B(DMP_SFG[18]), .Y(n2029) );
NOR2X1TS U3394 ( .A(n4550), .B(DMP_SFG[19]), .Y(n3985) );
NOR2X1TS U3395 ( .A(n4540), .B(DMP_SFG[20]), .Y(n2033) );
NOR2X1TS U3396 ( .A(n3985), .B(n2033), .Y(n4035) );
NOR2X1TS U3397 ( .A(n4648), .B(DMP_SFG[21]), .Y(n4037) );
NOR2X1TS U3398 ( .A(n4634), .B(DMP_SFG[22]), .Y(n2035) );
NOR2X1TS U3399 ( .A(n4647), .B(DMP_SFG[23]), .Y(n3928) );
NOR2X1TS U3400 ( .A(n4633), .B(DMP_SFG[24]), .Y(n2041) );
NOR2X1TS U3401 ( .A(n3928), .B(n2041), .Y(n3950) );
NOR2X1TS U3402 ( .A(n4549), .B(DMP_SFG[25]), .Y(n3953) );
NOR2X1TS U3403 ( .A(n4632), .B(DMP_SFG[26]), .Y(n2043) );
NOR2X1TS U3404 ( .A(n4646), .B(DMP_SFG[27]), .Y(n3939) );
NOR2X1TS U3405 ( .A(n4631), .B(DMP_SFG[28]), .Y(n2047) );
NOR2X1TS U3406 ( .A(n3939), .B(n2047), .Y(n3718) );
NOR2X1TS U3407 ( .A(n4645), .B(DMP_SFG[29]), .Y(n3720) );
NOR2X1TS U3408 ( .A(n4539), .B(DMP_SFG[30]), .Y(n2049) );
NOR2X2TS U3409 ( .A(n3713), .B(n2053), .Y(n2055) );
NAND2X1TS U3410 ( .A(n4551), .B(DMP_SFG[15]), .Y(n4008) );
NAND2X1TS U3411 ( .A(n4542), .B(DMP_SFG[16]), .Y(n2026) );
OAI21X1TS U3412 ( .A0(n2027), .A1(n4008), .B0(n2026), .Y(n3994) );
NAND2X1TS U3413 ( .A(n4649), .B(DMP_SFG[17]), .Y(n3996) );
NAND2X1TS U3414 ( .A(n4541), .B(DMP_SFG[18]), .Y(n2028) );
AOI21X1TS U3415 ( .A0(n3994), .A1(n2031), .B0(n2030), .Y(n3981) );
NAND2X1TS U3416 ( .A(n4550), .B(DMP_SFG[19]), .Y(n3984) );
NAND2X1TS U3417 ( .A(n4540), .B(DMP_SFG[20]), .Y(n2032) );
OAI21X1TS U3418 ( .A0(n2033), .A1(n3984), .B0(n2032), .Y(n4034) );
NAND2X1TS U3419 ( .A(n4648), .B(DMP_SFG[21]), .Y(n4036) );
NAND2X1TS U3420 ( .A(n4634), .B(DMP_SFG[22]), .Y(n2034) );
AOI21X1TS U3421 ( .A0(n4034), .A1(n2037), .B0(n2036), .Y(n2038) );
NAND2X1TS U3422 ( .A(n4647), .B(DMP_SFG[23]), .Y(n3927) );
NAND2X1TS U3423 ( .A(n4633), .B(DMP_SFG[24]), .Y(n2040) );
NAND2X1TS U3424 ( .A(n4549), .B(DMP_SFG[25]), .Y(n3952) );
NAND2X1TS U3425 ( .A(n4632), .B(DMP_SFG[26]), .Y(n2042) );
AOI21X1TS U3426 ( .A0(n3949), .A1(n2045), .B0(n2044), .Y(n3714) );
NAND2X1TS U3427 ( .A(n4646), .B(DMP_SFG[27]), .Y(n3938) );
NAND2X1TS U3428 ( .A(n4631), .B(DMP_SFG[28]), .Y(n2046) );
OAI21X1TS U3429 ( .A0(n2047), .A1(n3938), .B0(n2046), .Y(n3717) );
NAND2X1TS U3430 ( .A(n4645), .B(DMP_SFG[29]), .Y(n3719) );
NAND2X1TS U3431 ( .A(n4539), .B(DMP_SFG[30]), .Y(n2048) );
AOI21X1TS U3432 ( .A0(n3717), .A1(n2051), .B0(n2050), .Y(n2052) );
OAI21X4TS U3433 ( .A0(n2422), .A1(n2057), .B0(n2056), .Y(n2384) );
NOR2X1TS U3434 ( .A(n4548), .B(DMP_SFG[31]), .Y(n2679) );
NOR2X1TS U3435 ( .A(n4538), .B(DMP_SFG[32]), .Y(n2059) );
NOR2X1TS U3436 ( .A(n2679), .B(n2059), .Y(n2593) );
NOR2X1TS U3437 ( .A(n4644), .B(DMP_SFG[33]), .Y(n3900) );
NOR2X1TS U3438 ( .A(n4537), .B(DMP_SFG[34]), .Y(n2061) );
NOR2X1TS U3439 ( .A(n4547), .B(DMP_SFG[35]), .Y(n3797) );
NOR2X1TS U3440 ( .A(n4536), .B(DMP_SFG[36]), .Y(n2065) );
NOR2X1TS U3441 ( .A(n4546), .B(DMP_SFG[37]), .Y(n3828) );
NOR2X1TS U3442 ( .A(n4535), .B(DMP_SFG[38]), .Y(n2067) );
NOR2X1TS U3443 ( .A(n4573), .B(DMP_SFG[39]), .Y(n3876) );
NOR2X1TS U3444 ( .A(n4572), .B(DMP_SFG[40]), .Y(n2073) );
NOR2X1TS U3445 ( .A(n4643), .B(DMP_SFG[41]), .Y(n2077) );
NOR2X2TS U3446 ( .A(n2586), .B(n2077), .Y(n2079) );
NAND2X1TS U3447 ( .A(n4548), .B(DMP_SFG[31]), .Y(n2678) );
NAND2X1TS U3448 ( .A(n4538), .B(DMP_SFG[32]), .Y(n2058) );
OAI21X1TS U3449 ( .A0(n2059), .A1(n2678), .B0(n2058), .Y(n2594) );
NAND2X1TS U3450 ( .A(n4644), .B(DMP_SFG[33]), .Y(n3901) );
NAND2X1TS U3451 ( .A(n4537), .B(DMP_SFG[34]), .Y(n2060) );
OAI21X1TS U3452 ( .A0(n2061), .A1(n3901), .B0(n2060), .Y(n2062) );
AOI21X2TS U3453 ( .A0(n2594), .A1(n2063), .B0(n2062), .Y(n3779) );
NAND2X1TS U3454 ( .A(n4547), .B(DMP_SFG[35]), .Y(n3798) );
NAND2X1TS U3455 ( .A(n4536), .B(DMP_SFG[36]), .Y(n2064) );
OAI21X1TS U3456 ( .A0(n2065), .A1(n3798), .B0(n2064), .Y(n3811) );
NAND2X1TS U3457 ( .A(n4546), .B(DMP_SFG[37]), .Y(n3829) );
NAND2X1TS U3458 ( .A(n4535), .B(DMP_SFG[38]), .Y(n2066) );
OAI21X1TS U3459 ( .A0(n2067), .A1(n3829), .B0(n2066), .Y(n2068) );
AOI21X1TS U3460 ( .A0(n3811), .A1(n2069), .B0(n2068), .Y(n2070) );
NAND2X1TS U3461 ( .A(n4573), .B(DMP_SFG[39]), .Y(n3877) );
NAND2X1TS U3462 ( .A(n4572), .B(DMP_SFG[40]), .Y(n2072) );
NAND2X1TS U3463 ( .A(n4643), .B(DMP_SFG[41]), .Y(n2076) );
OAI21X2TS U3464 ( .A0(n2585), .A1(n2077), .B0(n2076), .Y(n2078) );
AOI21X4TS U3465 ( .A0(n2384), .A1(n2079), .B0(n2078), .Y(n3846) );
NAND2X1TS U3466 ( .A(n4642), .B(DMP_SFG[42]), .Y(n2080) );
NAND2X1TS U3467 ( .A(n4658), .B(DMP_SFG[44]), .Y(n2084) );
NAND2X1TS U3468 ( .A(n4614), .B(DMP_SFG[46]), .Y(n2088) );
NAND2X1TS U3469 ( .A(n4623), .B(DMP_SFG[48]), .Y(n2092) );
NAND2X1TS U3470 ( .A(n4657), .B(DMP_SFG[50]), .Y(n2096) );
OR2X1TS U3471 ( .A(n4624), .B(DMP_SFG[51]), .Y(n2099) );
AND2X2TS U3472 ( .A(n1926), .B(OP_FLAG_SFG), .Y(n3979) );
NOR2X1TS U3473 ( .A(DMP_SFG[16]), .B(DmP_mant_SFG_SWR[18]), .Y(n4012) );
NOR2X2TS U3474 ( .A(DMP_SFG[17]), .B(DmP_mant_SFG_SWR[19]), .Y(n4019) );
NOR2X1TS U3475 ( .A(n4012), .B(n4019), .Y(n4002) );
NOR2X2TS U3476 ( .A(DMP_SFG[18]), .B(DmP_mant_SFG_SWR[20]), .Y(n4067) );
NOR2X2TS U3477 ( .A(DMP_SFG[19]), .B(DmP_mant_SFG_SWR[21]), .Y(n4061) );
NOR2X2TS U3478 ( .A(DMP_SFG[20]), .B(DmP_mant_SFG_SWR[22]), .Y(n4054) );
NOR2X2TS U3479 ( .A(DMP_SFG[21]), .B(DmP_mant_SFG_SWR[23]), .Y(n4048) );
NOR2X1TS U3480 ( .A(n4054), .B(n4048), .Y(n2433) );
NOR2X2TS U3481 ( .A(DMP_SFG[22]), .B(DmP_mant_SFG_SWR[24]), .Y(n4038) );
NOR2X2TS U3482 ( .A(DMP_SFG[23]), .B(DmP_mant_SFG_SWR[25]), .Y(n2434) );
NOR2X2TS U3483 ( .A(DMP_SFG[24]), .B(DmP_mant_SFG_SWR[26]), .Y(n4357) );
NOR2X2TS U3484 ( .A(DMP_SFG[25]), .B(DmP_mant_SFG_SWR[27]), .Y(n4351) );
NOR2X2TS U3485 ( .A(DMP_SFG[26]), .B(DmP_mant_SFG_SWR[28]), .Y(n3954) );
NOR2X2TS U3486 ( .A(DMP_SFG[27]), .B(DmP_mant_SFG_SWR[29]), .Y(n3915) );
NOR2X2TS U3487 ( .A(DMP_SFG[28]), .B(DmP_mant_SFG_SWR[30]), .Y(n3970) );
NOR2X2TS U3488 ( .A(DMP_SFG[29]), .B(DmP_mant_SFG_SWR[31]), .Y(n3964) );
NOR2X2TS U3489 ( .A(DMP_SFG[30]), .B(DmP_mant_SFG_SWR[32]), .Y(n3721) );
NOR2X2TS U3490 ( .A(DMP_SFG[31]), .B(DmP_mant_SFG_SWR[33]), .Y(n2380) );
NOR2X1TS U3491 ( .A(DMP_SFG[1]), .B(DmP_mant_SFG_SWR[3]), .Y(n4244) );
NAND2X1TS U3492 ( .A(DMP_SFG[1]), .B(DmP_mant_SFG_SWR[3]), .Y(n4245) );
OAI21X1TS U3493 ( .A0(n4244), .A1(n4265), .B0(n4245), .Y(n4210) );
NOR2X2TS U3494 ( .A(DMP_SFG[2]), .B(DmP_mant_SFG_SWR[4]), .Y(n4234) );
NOR2X1TS U3495 ( .A(n4234), .B(n4206), .Y(n2102) );
NAND2X1TS U3496 ( .A(DMP_SFG[3]), .B(DmP_mant_SFG_SWR[5]), .Y(n4207) );
NOR2X1TS U3497 ( .A(DMP_SFG[4]), .B(DmP_mant_SFG_SWR[6]), .Y(n4131) );
NOR2X2TS U3498 ( .A(DMP_SFG[5]), .B(DmP_mant_SFG_SWR[7]), .Y(n4126) );
NOR2X1TS U3499 ( .A(n4131), .B(n4126), .Y(n4145) );
NOR2X2TS U3500 ( .A(DMP_SFG[6]), .B(DmP_mant_SFG_SWR[8]), .Y(n4156) );
NOR2X2TS U3501 ( .A(DMP_SFG[7]), .B(DmP_mant_SFG_SWR[9]), .Y(n4151) );
NAND2X1TS U3502 ( .A(DMP_SFG[4]), .B(DmP_mant_SFG_SWR[6]), .Y(n4222) );
NAND2X1TS U3503 ( .A(DMP_SFG[5]), .B(DmP_mant_SFG_SWR[7]), .Y(n4127) );
OAI21X1TS U3504 ( .A0(n4126), .A1(n4222), .B0(n4127), .Y(n4144) );
NAND2X1TS U3505 ( .A(DMP_SFG[6]), .B(DmP_mant_SFG_SWR[8]), .Y(n4155) );
NAND2X1TS U3506 ( .A(DMP_SFG[7]), .B(DmP_mant_SFG_SWR[9]), .Y(n4152) );
AOI21X1TS U3507 ( .A0(n4144), .A1(n2104), .B0(n2103), .Y(n2105) );
NOR2X2TS U3508 ( .A(DMP_SFG[9]), .B(DmP_mant_SFG_SWR[11]), .Y(n2717) );
NOR2X1TS U3509 ( .A(n4167), .B(n2717), .Y(n4115) );
NOR2X1TS U3510 ( .A(DMP_SFG[10]), .B(DmP_mant_SFG_SWR[12]), .Y(n4112) );
NOR2X2TS U3511 ( .A(DMP_SFG[11]), .B(DmP_mant_SFG_SWR[13]), .Y(n4192) );
NOR2X1TS U3512 ( .A(DMP_SFG[12]), .B(DmP_mant_SFG_SWR[14]), .Y(n4099) );
NOR2X2TS U3513 ( .A(DMP_SFG[13]), .B(DmP_mant_SFG_SWR[15]), .Y(n4094) );
NOR2X2TS U3514 ( .A(n2416), .B(n2418), .Y(n2110) );
NAND2X1TS U3515 ( .A(DMP_SFG[8]), .B(DmP_mant_SFG_SWR[10]), .Y(n4168) );
NAND2X1TS U3516 ( .A(DMP_SFG[9]), .B(DmP_mant_SFG_SWR[11]), .Y(n2718) );
NAND2X1TS U3517 ( .A(DMP_SFG[10]), .B(DmP_mant_SFG_SWR[12]), .Y(n4197) );
NAND2X1TS U3518 ( .A(DMP_SFG[11]), .B(DmP_mant_SFG_SWR[13]), .Y(n4193) );
AOI21X1TS U3519 ( .A0(n4116), .A1(n2108), .B0(n2107), .Y(n2410) );
NAND2X1TS U3520 ( .A(DMP_SFG[12]), .B(DmP_mant_SFG_SWR[14]), .Y(n4183) );
NAND2X1TS U3521 ( .A(DMP_SFG[13]), .B(DmP_mant_SFG_SWR[15]), .Y(n4095) );
OAI21X1TS U3522 ( .A0(n4094), .A1(n4183), .B0(n4095), .Y(n2413) );
NAND2X1TS U3523 ( .A(DMP_SFG[14]), .B(DmP_mant_SFG_SWR[16]), .Y(n4084) );
NAND2X1TS U3524 ( .A(DMP_SFG[15]), .B(DmP_mant_SFG_SWR[17]), .Y(n2419) );
AOI21X1TS U3525 ( .A0(n2413), .A1(n2110), .B0(n2109), .Y(n2111) );
NAND2X1TS U3526 ( .A(DMP_SFG[16]), .B(DmP_mant_SFG_SWR[18]), .Y(n4024) );
NAND2X1TS U3527 ( .A(DMP_SFG[17]), .B(DmP_mant_SFG_SWR[19]), .Y(n4020) );
OAI21X1TS U3528 ( .A0(n4019), .A1(n4024), .B0(n4020), .Y(n4001) );
NAND2X1TS U3529 ( .A(DMP_SFG[18]), .B(DmP_mant_SFG_SWR[20]), .Y(n4066) );
NAND2X1TS U3530 ( .A(DMP_SFG[19]), .B(DmP_mant_SFG_SWR[21]), .Y(n4062) );
NAND2X1TS U3531 ( .A(DMP_SFG[20]), .B(DmP_mant_SFG_SWR[22]), .Y(n4053) );
NAND2X1TS U3532 ( .A(DMP_SFG[21]), .B(DmP_mant_SFG_SWR[23]), .Y(n4049) );
OAI21X1TS U3533 ( .A0(n4048), .A1(n4053), .B0(n4049), .Y(n2432) );
NAND2X1TS U3534 ( .A(DMP_SFG[22]), .B(DmP_mant_SFG_SWR[24]), .Y(n4039) );
NAND2X1TS U3535 ( .A(DMP_SFG[23]), .B(DmP_mant_SFG_SWR[25]), .Y(n2435) );
AOI21X1TS U3536 ( .A0(n2432), .A1(n2119), .B0(n2118), .Y(n2120) );
NAND2X1TS U3537 ( .A(DMP_SFG[24]), .B(DmP_mant_SFG_SWR[26]), .Y(n4356) );
NAND2X1TS U3538 ( .A(DMP_SFG[25]), .B(DmP_mant_SFG_SWR[27]), .Y(n4352) );
NAND2X1TS U3539 ( .A(DMP_SFG[26]), .B(DmP_mant_SFG_SWR[28]), .Y(n3955) );
NAND2X1TS U3540 ( .A(DMP_SFG[27]), .B(DmP_mant_SFG_SWR[29]), .Y(n3916) );
AOI21X1TS U3541 ( .A0(n3920), .A1(n2123), .B0(n2122), .Y(n2375) );
NAND2X1TS U3542 ( .A(DMP_SFG[28]), .B(DmP_mant_SFG_SWR[30]), .Y(n3969) );
NAND2X1TS U3543 ( .A(DMP_SFG[29]), .B(DmP_mant_SFG_SWR[31]), .Y(n3965) );
OAI21X1TS U3544 ( .A0(n3964), .A1(n3969), .B0(n3965), .Y(n2378) );
NAND2X1TS U3545 ( .A(DMP_SFG[30]), .B(DmP_mant_SFG_SWR[32]), .Y(n3722) );
NAND2X1TS U3546 ( .A(DMP_SFG[31]), .B(DmP_mant_SFG_SWR[33]), .Y(n2381) );
AOI21X1TS U3547 ( .A0(n2378), .A1(n2125), .B0(n2124), .Y(n2126) );
OAI21X1TS U3548 ( .A0(n2375), .A1(n2127), .B0(n2126), .Y(n2128) );
AO21X4TS U3549 ( .A0(n2372), .A1(n2129), .B0(n2128), .Y(n2130) );
NOR2X2TS U3550 ( .A(DMP_SFG[33]), .B(DmP_mant_SFG_SWR[35]), .Y(n2597) );
NOR2X1TS U3551 ( .A(n2680), .B(n2597), .Y(n3786) );
NOR2X1TS U3552 ( .A(DMP_SFG[34]), .B(DmP_mant_SFG_SWR[36]), .Y(n3790) );
NOR2X2TS U3553 ( .A(DMP_SFG[35]), .B(DmP_mant_SFG_SWR[37]), .Y(n3782) );
NOR2X1TS U3554 ( .A(DMP_SFG[36]), .B(DmP_mant_SFG_SWR[38]), .Y(n3802) );
NOR2X2TS U3555 ( .A(DMP_SFG[37]), .B(DmP_mant_SFG_SWR[39]), .Y(n3815) );
NOR2X1TS U3556 ( .A(DMP_SFG[38]), .B(DmP_mant_SFG_SWR[40]), .Y(n2817) );
NOR2X2TS U3557 ( .A(DMP_SFG[39]), .B(DmP_mant_SFG_SWR[41]), .Y(n2819) );
NOR2X1TS U3558 ( .A(DMP_SFG[40]), .B(DmP_mant_SFG_SWR[42]), .Y(n2579) );
NOR2X2TS U3559 ( .A(DMP_SFG[41]), .B(DmP_mant_SFG_SWR[43]), .Y(n2581) );
NOR2X2TS U3560 ( .A(DMP_SFG[42]), .B(DmP_mant_SFG_SWR[44]), .Y(n3842) );
NOR2X2TS U3561 ( .A(n3848), .B(n3842), .Y(n2141) );
NAND2X1TS U3562 ( .A(DMP_SFG[32]), .B(DmP_mant_SFG_SWR[34]), .Y(n2681) );
NAND2X1TS U3563 ( .A(DMP_SFG[33]), .B(DmP_mant_SFG_SWR[35]), .Y(n2598) );
OAI21X1TS U3564 ( .A0(n2597), .A1(n2681), .B0(n2598), .Y(n3787) );
NAND2X1TS U3565 ( .A(DMP_SFG[34]), .B(DmP_mant_SFG_SWR[36]), .Y(n3905) );
NAND2X1TS U3566 ( .A(DMP_SFG[35]), .B(DmP_mant_SFG_SWR[37]), .Y(n3783) );
OAI21X1TS U3567 ( .A0(n3782), .A1(n3905), .B0(n3783), .Y(n2132) );
AOI21X2TS U3568 ( .A0(n3787), .A1(n2133), .B0(n2132), .Y(n2811) );
NAND2X1TS U3569 ( .A(DMP_SFG[36]), .B(DmP_mant_SFG_SWR[38]), .Y(n3819) );
NAND2X1TS U3570 ( .A(DMP_SFG[37]), .B(DmP_mant_SFG_SWR[39]), .Y(n3816) );
OAI21X1TS U3571 ( .A0(n3815), .A1(n3819), .B0(n3816), .Y(n2814) );
NAND2X1TS U3572 ( .A(DMP_SFG[38]), .B(DmP_mant_SFG_SWR[40]), .Y(n3833) );
NAND2X1TS U3573 ( .A(DMP_SFG[39]), .B(DmP_mant_SFG_SWR[41]), .Y(n2820) );
AOI21X1TS U3574 ( .A0(n2814), .A1(n2135), .B0(n2134), .Y(n2136) );
NAND2X1TS U3575 ( .A(DMP_SFG[40]), .B(DmP_mant_SFG_SWR[42]), .Y(n3881) );
NAND2X1TS U3576 ( .A(DMP_SFG[41]), .B(DmP_mant_SFG_SWR[43]), .Y(n2582) );
OAI21X1TS U3577 ( .A0(n2581), .A1(n3881), .B0(n2582), .Y(n2138) );
NAND2X1TS U3578 ( .A(DMP_SFG[42]), .B(DmP_mant_SFG_SWR[44]), .Y(n3843) );
OAI21X2TS U3579 ( .A0(n3847), .A1(n3842), .B0(n3843), .Y(n2140) );
AOI21X4TS U3580 ( .A0(n2574), .A1(n2141), .B0(n2140), .Y(n3862) );
NOR2X1TS U3581 ( .A(DMP_SFG[43]), .B(DmP_mant_SFG_SWR[45]), .Y(n3856) );
NAND2X1TS U3582 ( .A(DMP_SFG[43]), .B(DmP_mant_SFG_SWR[45]), .Y(n3857) );
NAND2X1TS U3583 ( .A(DMP_SFG[44]), .B(DmP_mant_SFG_SWR[46]), .Y(n3866) );
INVX2TS U3584 ( .A(n3866), .Y(n2142) );
AOI21X4TS U3585 ( .A0(n3871), .A1(n3867), .B0(n2142), .Y(n3896) );
NOR2X1TS U3586 ( .A(DMP_SFG[45]), .B(DmP_mant_SFG_SWR[47]), .Y(n3890) );
NAND2X1TS U3587 ( .A(DMP_SFG[45]), .B(DmP_mant_SFG_SWR[47]), .Y(n3891) );
NAND2X1TS U3588 ( .A(DMP_SFG[46]), .B(DmP_mant_SFG_SWR[48]), .Y(n3751) );
INVX2TS U3589 ( .A(n3751), .Y(n2143) );
AOI21X4TS U3590 ( .A0(n3755), .A1(n3752), .B0(n2143), .Y(n3766) );
NOR2X1TS U3591 ( .A(DMP_SFG[47]), .B(DmP_mant_SFG_SWR[49]), .Y(n3760) );
NAND2X1TS U3592 ( .A(DMP_SFG[47]), .B(DmP_mant_SFG_SWR[49]), .Y(n3761) );
NAND2X1TS U3593 ( .A(DMP_SFG[48]), .B(DmP_mant_SFG_SWR[50]), .Y(n3770) );
INVX2TS U3594 ( .A(n3770), .Y(n2144) );
AOI21X4TS U3595 ( .A0(n3774), .A1(n3771), .B0(n2144), .Y(n3746) );
NOR2X1TS U3596 ( .A(DMP_SFG[49]), .B(DmP_mant_SFG_SWR[51]), .Y(n3740) );
NAND2X1TS U3597 ( .A(DMP_SFG[49]), .B(DmP_mant_SFG_SWR[51]), .Y(n3741) );
NAND2X1TS U3598 ( .A(DMP_SFG[50]), .B(DmP_mant_SFG_SWR[52]), .Y(n3731) );
INVX2TS U3599 ( .A(n3731), .Y(n2145) );
NOR2X1TS U3600 ( .A(DMP_SFG[51]), .B(DmP_mant_SFG_SWR[53]), .Y(n3129) );
NAND2X1TS U3601 ( .A(DMP_SFG[51]), .B(DmP_mant_SFG_SWR[53]), .Y(n3130) );
XNOR2X1TS U3602 ( .A(n4366), .B(DmP_mant_SFG_SWR[54]), .Y(n2146) );
INVX2TS U3603 ( .A(n1926), .Y(n4448) );
BUFX3TS U3604 ( .A(n4448), .Y(n3747) );
NOR2X4TS U3605 ( .A(n3747), .B(OP_FLAG_SFG), .Y(n4174) );
BUFX3TS U3606 ( .A(n4174), .Y(n4367) );
INVX2TS U3607 ( .A(intDX_EWSW[60]), .Y(n2155) );
NAND2X1TS U3608 ( .A(n1992), .B(intDX_EWSW[61]), .Y(n2154) );
OAI211X1TS U3609 ( .A0(intDY_EWSW[60]), .A1(n2155), .B0(n2159), .C0(n2154),
.Y(n2164) );
AOI22X1TS U3610 ( .A0(intDY_EWSW[57]), .A1(n1985), .B0(intDY_EWSW[56]), .B1(
n2149), .Y(n2153) );
INVX2TS U3611 ( .A(intDX_EWSW[58]), .Y(n2151) );
OAI21X1TS U3612 ( .A0(intDY_EWSW[58]), .A1(n2151), .B0(n2150), .Y(n2163) );
OA21XLTS U3613 ( .A0(n2153), .A1(n2163), .B0(n2152), .Y(n2160) );
INVX2TS U3614 ( .A(intDX_EWSW[53]), .Y(n2205) );
NOR2X1TS U3615 ( .A(n2205), .B(intDY_EWSW[53]), .Y(n2162) );
INVX2TS U3616 ( .A(intDX_EWSW[55]), .Y(n2216) );
OAI22X1TS U3617 ( .A0(n2216), .A1(intDY_EWSW[55]), .B0(intDY_EWSW[54]), .B1(
n4529), .Y(n2206) );
NOR2BX1TS U3618 ( .AN(intDX_EWSW[56]), .B(intDY_EWSW[56]), .Y(n2166) );
NOR4X2TS U3619 ( .A(n2166), .B(n2165), .C(n2164), .D(n2163), .Y(n2218) );
NOR2X1TS U3620 ( .A(n4584), .B(intDY_EWSW[49]), .Y(n2209) );
NOR2BX1TS U3621 ( .AN(n2169), .B(intDX_EWSW[46]), .Y(n2181) );
AOI22X1TS U3622 ( .A0(intDY_EWSW[45]), .A1(n1974), .B0(intDY_EWSW[44]), .B1(
n2168), .Y(n2178) );
OAI21X1TS U3623 ( .A0(intDY_EWSW[46]), .A1(n1975), .B0(n2169), .Y(n2177) );
INVX2TS U3624 ( .A(intDY_EWSW[44]), .Y(n2171) );
OAI2BB2XLTS U3625 ( .B0(intDX_EWSW[40]), .B1(n2172), .A0N(intDY_EWSW[41]),
.A1N(n1955), .Y(n2175) );
AOI32X1TS U3626 ( .A0(n2185), .A1(n2175), .A2(n2184), .B0(n2174), .B1(n2185),
.Y(n2176) );
NOR2BX1TS U3627 ( .AN(intDY_EWSW[47]), .B(intDX_EWSW[47]), .Y(n2179) );
INVX2TS U3628 ( .A(intDY_EWSW[38]), .Y(n2199) );
NOR2BX1TS U3629 ( .AN(intDX_EWSW[39]), .B(intDY_EWSW[39]), .Y(n2198) );
AOI21X1TS U3630 ( .A0(intDX_EWSW[38]), .A1(n2199), .B0(n2198), .Y(n2197) );
INVX2TS U3631 ( .A(n2300), .Y(n2188) );
INVX2TS U3632 ( .A(n2304), .Y(n2192) );
OAI2BB1X1TS U3633 ( .A0N(n2197), .A1N(n2196), .B0(n2195), .Y(n2203) );
NOR2BX1TS U3634 ( .AN(intDY_EWSW[39]), .B(intDX_EWSW[39]), .Y(n2202) );
NOR3X1TS U3635 ( .A(n2199), .B(n2198), .C(intDX_EWSW[38]), .Y(n2201) );
INVX2TS U3636 ( .A(n2305), .Y(n2200) );
OAI31X1TS U3637 ( .A0(n2203), .A1(n2202), .A2(n2201), .B0(n2200), .Y(n2223)
);
INVX2TS U3638 ( .A(n2208), .Y(n2214) );
AOI22X1TS U3639 ( .A0(intDY_EWSW[49]), .A1(n4584), .B0(intDY_EWSW[48]), .B1(
n2210), .Y(n2213) );
AOI32X1TS U3640 ( .A0(n1956), .A1(n2211), .A2(intDY_EWSW[50]), .B0(
intDY_EWSW[51]), .B1(n1958), .Y(n2212) );
OAI32X1TS U3641 ( .A0(n2215), .A1(n2214), .A2(n2213), .B0(n2212), .B1(n2214),
.Y(n2220) );
OAI2BB2XLTS U3642 ( .B0(intDX_EWSW[54]), .B1(n2217), .A0N(intDY_EWSW[55]),
.A1N(n2216), .Y(n2219) );
OAI31X1TS U3643 ( .A0(n2221), .A1(n2220), .A2(n2219), .B0(n2218), .Y(n2222)
);
OAI221X1TS U3644 ( .A0(n2305), .A1(n2224), .B0(n2303), .B1(n2223), .C0(n2222), .Y(n2308) );
OAI21X1TS U3645 ( .A0(intDY_EWSW[26]), .A1(n1957), .B0(n2228), .Y(n2295) );
AOI22X1TS U3646 ( .A0(n2227), .A1(intDY_EWSW[24]), .B0(intDY_EWSW[25]), .B1(
n1952), .Y(n2230) );
AOI32X1TS U3647 ( .A0(n1957), .A1(n2228), .A2(intDY_EWSW[26]), .B0(
intDY_EWSW[27]), .B1(n1984), .Y(n2229) );
OAI32X1TS U3648 ( .A0(n2295), .A1(n2294), .A2(n2230), .B0(n2229), .B1(n2294),
.Y(n2233) );
INVX2TS U3649 ( .A(intDY_EWSW[5]), .Y(n2245) );
OAI2BB1X1TS U3650 ( .A0N(n2245), .A1N(intDX_EWSW[5]), .B0(intDY_EWSW[4]),
.Y(n2236) );
OAI22X1TS U3651 ( .A0(intDX_EWSW[4]), .A1(n2236), .B0(n2245), .B1(
intDX_EWSW[5]), .Y(n2251) );
INVX2TS U3652 ( .A(intDY_EWSW[7]), .Y(n2247) );
OAI2BB1X1TS U3653 ( .A0N(n2247), .A1N(intDX_EWSW[7]), .B0(intDY_EWSW[6]),
.Y(n2237) );
OAI22X1TS U3654 ( .A0(intDX_EWSW[6]), .A1(n2237), .B0(n2247), .B1(
intDX_EWSW[7]), .Y(n2250) );
INVX2TS U3655 ( .A(intDY_EWSW[1]), .Y(n2239) );
AOI2BB2X1TS U3656 ( .B0(intDX_EWSW[1]), .B1(n2239), .A0N(intDY_EWSW[0]),
.A1N(n2238), .Y(n2240) );
OAI211X1TS U3657 ( .A0(n1949), .A1(intDY_EWSW[3]), .B0(n2241), .C0(n2240),
.Y(n2244) );
INVX2TS U3658 ( .A(intDY_EWSW[6]), .Y(n2246) );
AOI22X1TS U3659 ( .A0(intDX_EWSW[7]), .A1(n2247), .B0(intDX_EWSW[6]), .B1(
n2246), .Y(n2248) );
OAI32X1TS U3660 ( .A0(n2251), .A1(n2250), .A2(n2249), .B0(n2248), .B1(n2250),
.Y(n2257) );
OA22X1TS U3661 ( .A0(n1969), .A1(intDY_EWSW[14]), .B0(n1951), .B1(
intDY_EWSW[15]), .Y(n2272) );
INVX2TS U3662 ( .A(intDY_EWSW[10]), .Y(n2253) );
AOI21X1TS U3663 ( .A0(intDX_EWSW[10]), .A1(n2253), .B0(n2259), .Y(n2264) );
AOI22X1TS U3664 ( .A0(intDY_EWSW[11]), .A1(n1989), .B0(intDY_EWSW[10]), .B1(
n2260), .Y(n2267) );
AOI21X1TS U3665 ( .A0(n2263), .A1(n2262), .B0(n2266), .Y(n2265) );
OAI2BB2XLTS U3666 ( .B0(intDX_EWSW[14]), .B1(n2268), .A0N(intDY_EWSW[15]),
.A1N(n1951), .Y(n2269) );
INVX2TS U3667 ( .A(intDY_EWSW[16]), .Y(n2273) );
NOR2X1TS U3668 ( .A(n1983), .B(intDY_EWSW[17]), .Y(n2280) );
OAI21X1TS U3669 ( .A0(intDY_EWSW[18]), .A1(n1990), .B0(n2282), .Y(n2286) );
AOI22X1TS U3670 ( .A0(n2281), .A1(intDY_EWSW[16]), .B0(intDY_EWSW[17]), .B1(
n1983), .Y(n2284) );
AOI32X1TS U3671 ( .A0(n1990), .A1(n2282), .A2(intDY_EWSW[18]), .B0(
intDY_EWSW[19]), .B1(n1980), .Y(n2283) );
OAI32X1TS U3672 ( .A0(n2286), .A1(n2285), .A2(n2284), .B0(n2283), .B1(n2285),
.Y(n2289) );
AOI211X1TS U3673 ( .A0(n2291), .A1(n2290), .B0(n2289), .C0(n2288), .Y(n2297)
);
NOR2BX1TS U3674 ( .AN(intDX_EWSW[24]), .B(intDY_EWSW[24]), .Y(n2293) );
OR4X2TS U3675 ( .A(n2295), .B(n2294), .C(n2293), .D(n2292), .Y(n2296) );
AOI32X1TS U3676 ( .A0(n2299), .A1(n2298), .A2(n2297), .B0(n2296), .B1(n2299),
.Y(n2306) );
NOR2BX4TS U3677 ( .AN(n2306), .B(n1982), .Y(n2307) );
NOR3BX4TS U3678 ( .AN(n2309), .B(n2308), .C(n2307), .Y(n2311) );
BUFX3TS U3679 ( .A(n2928), .Y(n4432) );
BUFX3TS U3680 ( .A(n2928), .Y(n3110) );
AOI22X1TS U3681 ( .A0(intDX_EWSW[7]), .A1(n3144), .B0(DMP_EXP_EWSW[7]), .B1(
n3110), .Y(n2312) );
AOI22X1TS U3682 ( .A0(intDX_EWSW[5]), .A1(n3144), .B0(DMP_EXP_EWSW[5]), .B1(
n3110), .Y(n2313) );
CLKBUFX2TS U3683 ( .A(n2928), .Y(n2907) );
BUFX3TS U3684 ( .A(n2907), .Y(n3077) );
AOI22X1TS U3685 ( .A0(intDX_EWSW[29]), .A1(n3078), .B0(DmP_EXP_EWSW[29]),
.B1(n3077), .Y(n2315) );
BUFX3TS U3686 ( .A(n2907), .Y(n4397) );
AOI22X1TS U3687 ( .A0(intDX_EWSW[46]), .A1(n3090), .B0(DmP_EXP_EWSW[46]),
.B1(n4397), .Y(n2316) );
AOI22X1TS U3688 ( .A0(intDX_EWSW[47]), .A1(n3090), .B0(DmP_EXP_EWSW[47]),
.B1(n4397), .Y(n2317) );
AOI22X1TS U3689 ( .A0(intDX_EWSW[51]), .A1(n3090), .B0(DmP_EXP_EWSW[51]),
.B1(n4397), .Y(n2318) );
NOR2X1TS U3690 ( .A(n4534), .B(shift_value_SHT2_EWR[5]), .Y(n2392) );
INVX2TS U3691 ( .A(n2392), .Y(n2398) );
INVX2TS U3692 ( .A(n2398), .Y(n4296) );
NOR2X2TS U3693 ( .A(n4506), .B(shift_value_SHT2_EWR[2]), .Y(n2939) );
BUFX3TS U3694 ( .A(n2939), .Y(n3652) );
NOR2X2TS U3695 ( .A(n4570), .B(shift_value_SHT2_EWR[3]), .Y(n2938) );
INVX2TS U3696 ( .A(n2938), .Y(n2658) );
AOI22X1TS U3697 ( .A0(n3652), .A1(Data_array_SWR[25]), .B0(n2869), .B1(
Data_array_SWR[21]), .Y(n2320) );
AOI22X1TS U3698 ( .A0(n2405), .A1(Data_array_SWR[29]), .B0(n2870), .B1(
Data_array_SWR[17]), .Y(n2319) );
NAND2X1TS U3699 ( .A(n2320), .B(n2319), .Y(n2843) );
BUFX3TS U3700 ( .A(n2939), .Y(n2958) );
AOI22X1TS U3701 ( .A0(n2405), .A1(Data_array_SWR[44]), .B0(n2958), .B1(
Data_array_SWR[40]), .Y(n2322) );
AOI22X1TS U3702 ( .A0(n3651), .A1(Data_array_SWR[36]), .B0(n2870), .B1(
Data_array_SWR[33]), .Y(n2321) );
INVX2TS U3703 ( .A(n2393), .Y(n3023) );
INVX2TS U3704 ( .A(n2323), .Y(n4298) );
AOI22X1TS U3705 ( .A0(n1922), .A1(Data_array_SWR[9]), .B0(n1924), .B1(
Data_array_SWR[1]), .Y(n2325) );
BUFX3TS U3706 ( .A(n2405), .Y(n2976) );
NAND2X1TS U3707 ( .A(n4298), .B(n2976), .Y(n3008) );
INVX2TS U3708 ( .A(n2323), .Y(n3649) );
NAND2X1TS U3709 ( .A(n3649), .B(n2981), .Y(n2988) );
AOI22X1TS U3710 ( .A0(n3657), .A1(Data_array_SWR[13]), .B0(n1920), .B1(
Data_array_SWR[5]), .Y(n2324) );
NAND2X1TS U3711 ( .A(n2981), .B(Data_array_SWR[52]), .Y(n2327) );
NAND2X1TS U3712 ( .A(n2982), .B(Data_array_SWR[48]), .Y(n2326) );
NAND3X2TS U3713 ( .A(n2327), .B(n2326), .C(n2645), .Y(n4307) );
INVX2TS U3714 ( .A(n4307), .Y(n2839) );
NOR2BX1TS U3715 ( .AN(LZD_output_NRM2_EW[5]), .B(ADD_OVRFLW_NRM2), .Y(n2330)
);
XOR2X1TS U3716 ( .A(n1918), .B(n2330), .Y(n2348) );
NOR2BX1TS U3717 ( .AN(LZD_output_NRM2_EW[4]), .B(ADD_OVRFLW_NRM2), .Y(n2331)
);
XOR2X1TS U3718 ( .A(n1918), .B(n2331), .Y(n2343) );
NOR2BX1TS U3719 ( .AN(LZD_output_NRM2_EW[3]), .B(ADD_OVRFLW_NRM2), .Y(n2332)
);
XOR2X1TS U3720 ( .A(DP_OP_15J155_122_2221_n35), .B(n2332), .Y(n2345) );
CLKXOR2X2TS U3721 ( .A(DP_OP_15J155_122_2221_n35), .B(n2334), .Y(n2341) );
XNOR2X4TS U3722 ( .A(n2336), .B(ADD_OVRFLW_NRM2), .Y(n2368) );
AFHCONX2TS U3723 ( .A(DMP_exp_NRM2_EW[2]), .B(n2338), .CI(n2337), .CON(n2344), .S(n2357) );
AFHCONX2TS U3724 ( .A(n1940), .B(DP_OP_15J155_122_2221_n35), .CI(n2339),
.CON(n2340), .S(n2447) );
AFHCINX2TS U3725 ( .CIN(n2340), .B(n2341), .A(DMP_exp_NRM2_EW[1]), .S(n2448),
.CO(n2337) );
NAND2X4TS U3726 ( .A(n2368), .B(n2351), .Y(n2352) );
ADDFHX2TS U3727 ( .A(n1918), .B(DMP_exp_NRM2_EW[10]), .CI(n2353), .CO(n2336),
.S(n3691) );
AFHCINX2TS U3728 ( .CIN(n2354), .B(n1918), .A(DMP_exp_NRM2_EW[9]), .S(n2606),
.CO(n2353) );
AFHCONX2TS U3729 ( .A(DMP_exp_NRM2_EW[8]), .B(n1918), .CI(n2355), .CON(n2354), .S(n2449) );
INVX2TS U3730 ( .A(n2356), .Y(n4387) );
INVX2TS U3731 ( .A(n2357), .Y(n4386) );
AFHCINX2TS U3732 ( .CIN(n2360), .B(n1918), .A(DMP_exp_NRM2_EW[7]), .S(n2361),
.CO(n2355) );
INVX2TS U3733 ( .A(n2361), .Y(n4389) );
AFHCONX2TS U3734 ( .A(DMP_exp_NRM2_EW[6]), .B(n1918), .CI(n2362), .CON(n2360), .S(n2363) );
INVX2TS U3735 ( .A(n2363), .Y(n4388) );
NAND4BX1TS U3736 ( .AN(n2449), .B(n2364), .C(n4389), .D(n4388), .Y(n2365) );
NAND2BX2TS U3737 ( .AN(n3691), .B(n2366), .Y(n2367) );
NAND2X4TS U3738 ( .A(n4390), .B(n1928), .Y(n3039) );
INVX2TS U3739 ( .A(n2866), .Y(n3653) );
OR2X2TS U3740 ( .A(n3653), .B(bit_shift_SHT2), .Y(n2865) );
NOR2X1TS U3741 ( .A(n3649), .B(n4612), .Y(n2369) );
BUFX3TS U3742 ( .A(n2369), .Y(n3648) );
INVX2TS U3743 ( .A(n3648), .Y(n2882) );
AOI22X1TS U3744 ( .A0(n2950), .A1(n2730), .B0(final_result_ieee[51]), .B1(
n3697), .Y(n2370) );
INVX2TS U3745 ( .A(n2374), .Y(n2377) );
INVX2TS U3746 ( .A(n2375), .Y(n2376) );
INVX2TS U3747 ( .A(n3971), .Y(n3945) );
NAND2X1TS U3748 ( .A(n2382), .B(n2381), .Y(n2385) );
XNOR2X1TS U3749 ( .A(n2383), .B(n2385), .Y(n2389) );
INVX2TS U3750 ( .A(n2385), .Y(n2386) );
XOR2X1TS U3751 ( .A(n3781), .B(n2386), .Y(n2387) );
BUFX3TS U3752 ( .A(n3979), .Y(n4275) );
AOI22X1TS U3753 ( .A0(n2387), .A1(n4275), .B0(Raw_mant_NRM_SWR[33]), .B1(
n3747), .Y(n2388) );
NAND2X2TS U3754 ( .A(n3649), .B(n3689), .Y(n4340) );
INVX2TS U3755 ( .A(n4325), .Y(n4338) );
AOI22X1TS U3756 ( .A0(n2982), .A1(Data_array_SWR[36]), .B0(n2958), .B1(
Data_array_SWR[44]), .Y(n2391) );
AOI22X1TS U3757 ( .A0(n2981), .A1(Data_array_SWR[40]), .B0(n2405), .B1(
Data_array_SWR[48]), .Y(n2390) );
NAND2X2TS U3758 ( .A(n2391), .B(n2390), .Y(n4308) );
INVX2TS U3759 ( .A(n2392), .Y(n3659) );
NOR2X4TS U3760 ( .A(n3689), .B(n2398), .Y(n4316) );
INVX2TS U3761 ( .A(n4316), .Y(n4329) );
NAND2X2TS U3762 ( .A(n3664), .B(n1927), .Y(n4333) );
NOR2X4TS U3763 ( .A(n1929), .B(n3659), .Y(n4318) );
INVX2TS U3764 ( .A(n4318), .Y(n4331) );
OAI22X1TS U3765 ( .A0(n2839), .A1(n4333), .B0(n4314), .B1(n4331), .Y(n2394)
);
OAI2BB1X1TS U3766 ( .A0N(n1938), .A1N(n2843), .B0(n2396), .Y(n4328) );
BUFX3TS U3767 ( .A(n2955), .Y(n4377) );
AOI22X1TS U3768 ( .A0(n1933), .A1(Data_array_SWR[25]), .B0(n1924), .B1(
Data_array_SWR[13]), .Y(n2404) );
AOI22X1TS U3769 ( .A0(n1922), .A1(Data_array_SWR[21]), .B0(n1919), .B1(
Data_array_SWR[17]), .Y(n2403) );
INVX2TS U3770 ( .A(n3659), .Y(n3022) );
AOI22X1TS U3771 ( .A0(n2976), .A1(Data_array_SWR[40]), .B0(n2981), .B1(
Data_array_SWR[33]), .Y(n2400) );
BUFX3TS U3772 ( .A(n2939), .Y(n2833) );
AOI22X1TS U3773 ( .A0(n2833), .A1(Data_array_SWR[36]), .B0(n2959), .B1(
Data_array_SWR[29]), .Y(n2399) );
NAND2X1TS U3774 ( .A(n2400), .B(n2399), .Y(n2998) );
AOI22X1TS U3775 ( .A0(n2833), .A1(Data_array_SWR[52]), .B0(n2870), .B1(
Data_array_SWR[44]), .Y(n2401) );
NAND2X1TS U3776 ( .A(n2976), .B(bit_shift_SHT2), .Y(n2986) );
AOI22X1TS U3777 ( .A0(n4296), .A1(n2998), .B0(n3023), .B1(n3000), .Y(n2402)
);
BUFX3TS U3778 ( .A(n2405), .Y(n3654) );
AOI22X1TS U3779 ( .A0(n3654), .A1(Data_array_SWR[52]), .B0(n2869), .B1(
Data_array_SWR[44]), .Y(n2407) );
AOI22X1TS U3780 ( .A0(n2833), .A1(Data_array_SWR[48]), .B0(n2870), .B1(
Data_array_SWR[40]), .Y(n2406) );
NAND2X1TS U3781 ( .A(n2407), .B(n2406), .Y(n3672) );
AOI22X1TS U3782 ( .A0(n1929), .A1(n3675), .B0(n4323), .B1(n3672), .Y(n2408)
);
NAND2X2TS U3783 ( .A(n3648), .B(n1927), .Y(n2665) );
NAND2X1TS U3784 ( .A(n2408), .B(n2665), .Y(n4280) );
OAI21X1TS U3785 ( .A0(n4173), .A1(n2411), .B0(n2410), .Y(n4101) );
INVX2TS U3786 ( .A(n4101), .Y(n4188) );
INVX2TS U3787 ( .A(n2412), .Y(n2415) );
INVX2TS U3788 ( .A(n2413), .Y(n2414) );
OAI21X1TS U3789 ( .A0(n4188), .A1(n2415), .B0(n2414), .Y(n4089) );
AOI21X1TS U3790 ( .A0(n4089), .A1(n4085), .B0(n2417), .Y(n2421) );
INVX2TS U3791 ( .A(n2418), .Y(n2420) );
NAND2X1TS U3792 ( .A(n2420), .B(n2419), .Y(n2423) );
INVX2TS U3793 ( .A(n2423), .Y(n2424) );
XNOR2X1TS U3794 ( .A(n4011), .B(n2424), .Y(n2425) );
BUFX3TS U3795 ( .A(n4448), .Y(n4090) );
AOI22X1TS U3796 ( .A0(n2425), .A1(n4275), .B0(Raw_mant_NRM_SWR[17]), .B1(
n4090), .Y(n2426) );
OAI2BB1X1TS U3797 ( .A0N(n4174), .A1N(n2427), .B0(n2426), .Y(n1252) );
INVX2TS U3798 ( .A(n2428), .Y(n2431) );
INVX2TS U3799 ( .A(n2429), .Y(n2430) );
AOI21X1TS U3800 ( .A0(n4027), .A1(n2431), .B0(n2430), .Y(n4055) );
INVX2TS U3801 ( .A(n4055), .Y(n3990) );
AOI21X1TS U3802 ( .A0(n3990), .A1(n2433), .B0(n2432), .Y(n4044) );
NAND2X1TS U3803 ( .A(n2436), .B(n2435), .Y(n2440) );
XNOR2X1TS U3804 ( .A(n2437), .B(n2440), .Y(n2444) );
INVX2TS U3805 ( .A(n3929), .Y(n3951) );
INVX2TS U3806 ( .A(n2440), .Y(n2441) );
XNOR2X1TS U3807 ( .A(n3951), .B(n2441), .Y(n2442) );
AOI22X1TS U3808 ( .A0(n2442), .A1(n4275), .B0(Raw_mant_NRM_SWR[25]), .B1(
n4090), .Y(n2443) );
OAI2BB1X1TS U3809 ( .A0N(n4174), .A1N(n2444), .B0(n2443), .Y(n1244) );
OA22X1TS U3810 ( .A0(n3693), .A1(n2445), .B0(n4675), .B1(
final_result_ieee[56]), .Y(n1682) );
OA22X1TS U3811 ( .A0(n3693), .A1(n2446), .B0(n4675), .B1(
final_result_ieee[57]), .Y(n1681) );
OA22X1TS U3812 ( .A0(n3693), .A1(n2447), .B0(n4675), .B1(
final_result_ieee[52]), .Y(n1686) );
OA22X1TS U3813 ( .A0(n3693), .A1(n2448), .B0(n4675), .B1(
final_result_ieee[53]), .Y(n1685) );
OA22X1TS U3814 ( .A0(n3693), .A1(n2449), .B0(n4675), .B1(
final_result_ieee[60]), .Y(n1678) );
INVX2TS U3815 ( .A(n2740), .Y(n2450) );
NOR2X2TS U3816 ( .A(Raw_mant_NRM_SWR[52]), .B(Raw_mant_NRM_SWR[51]), .Y(
n2512) );
NOR2X6TS U3817 ( .A(n2450), .B(n2739), .Y(n2758) );
NOR2X2TS U3818 ( .A(Raw_mant_NRM_SWR[40]), .B(Raw_mant_NRM_SWR[39]), .Y(
n2504) );
NOR3X1TS U3819 ( .A(Raw_mant_NRM_SWR[42]), .B(Raw_mant_NRM_SWR[36]), .C(
Raw_mant_NRM_SWR[43]), .Y(n2451) );
NAND2X1TS U3820 ( .A(n2504), .B(n2451), .Y(n2455) );
NOR2X1TS U3821 ( .A(Raw_mant_NRM_SWR[45]), .B(Raw_mant_NRM_SWR[44]), .Y(
n2452) );
NAND2X2TS U3822 ( .A(n4552), .B(n2452), .Y(n2757) );
NOR2X1TS U3823 ( .A(Raw_mant_NRM_SWR[41]), .B(Raw_mant_NRM_SWR[47]), .Y(
n2453) );
NOR2X2TS U3824 ( .A(Raw_mant_NRM_SWR[38]), .B(Raw_mant_NRM_SWR[37]), .Y(
n2791) );
NAND2X2TS U3825 ( .A(n2453), .B(n2791), .Y(n2454) );
NOR3X2TS U3826 ( .A(n2455), .B(n2757), .C(n2454), .Y(n2456) );
NAND2X4TS U3827 ( .A(n2758), .B(n2456), .Y(n2529) );
NOR2X1TS U3828 ( .A(Raw_mant_NRM_SWR[35]), .B(Raw_mant_NRM_SWR[34]), .Y(
n2458) );
NOR2X1TS U3829 ( .A(Raw_mant_NRM_SWR[32]), .B(Raw_mant_NRM_SWR[33]), .Y(
n2457) );
NAND2X1TS U3830 ( .A(n2458), .B(n2457), .Y(n2459) );
NOR2X6TS U3831 ( .A(n2529), .B(n2459), .Y(n2496) );
NOR2X1TS U3832 ( .A(Raw_mant_NRM_SWR[29]), .B(Raw_mant_NRM_SWR[28]), .Y(
n2495) );
NOR2X1TS U3833 ( .A(Raw_mant_NRM_SWR[31]), .B(Raw_mant_NRM_SWR[26]), .Y(
n2460) );
NAND2X1TS U3834 ( .A(n2495), .B(n2460), .Y(n2461) );
NOR3X1TS U3835 ( .A(n2461), .B(Raw_mant_NRM_SWR[30]), .C(
Raw_mant_NRM_SWR[27]), .Y(n2462) );
NAND2X4TS U3836 ( .A(n2496), .B(n2462), .Y(n2794) );
NOR2X6TS U3837 ( .A(n2794), .B(Raw_mant_NRM_SWR[25]), .Y(n2762) );
NAND2X1TS U3838 ( .A(n2464), .B(n2463), .Y(n2467) );
NOR2X1TS U3839 ( .A(Raw_mant_NRM_SWR[17]), .B(Raw_mant_NRM_SWR[18]), .Y(
n2770) );
NAND2X1TS U3840 ( .A(n2770), .B(n2465), .Y(n2466) );
NOR2X1TS U3841 ( .A(n2467), .B(n2466), .Y(n2468) );
NAND2X4TS U3842 ( .A(n2762), .B(n2468), .Y(n2517) );
NOR2X4TS U3843 ( .A(n2517), .B(n1977), .Y(n2472) );
NOR2X4TS U3844 ( .A(n2774), .B(Raw_mant_NRM_SWR[13]), .Y(n2755) );
NOR2X2TS U3845 ( .A(Raw_mant_NRM_SWR[12]), .B(Raw_mant_NRM_SWR[11]), .Y(
n2754) );
INVX2TS U3846 ( .A(n2754), .Y(n2469) );
NOR2X1TS U3847 ( .A(n2469), .B(Raw_mant_NRM_SWR[10]), .Y(n2470) );
NAND2X2TS U3848 ( .A(n2755), .B(n2470), .Y(n2783) );
NOR2X1TS U3849 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[7]), .Y(n2474)
);
NOR2X1TS U3850 ( .A(n2783), .B(n2471), .Y(n2483) );
INVX2TS U3851 ( .A(n2755), .Y(n2481) );
INVX2TS U3852 ( .A(n2472), .Y(n2747) );
NOR2X4TS U3853 ( .A(n2747), .B(n2476), .Y(n2733) );
INVX2TS U3854 ( .A(n2772), .Y(n2477) );
NOR2X1TS U3855 ( .A(Raw_mant_NRM_SWR[4]), .B(Raw_mant_NRM_SWR[3]), .Y(n2484)
);
INVX2TS U3856 ( .A(n2517), .Y(n2478) );
AOI22X1TS U3857 ( .A0(n2733), .A1(n2479), .B0(n2478), .B1(
Raw_mant_NRM_SWR[15]), .Y(n2480) );
OAI21X1TS U3858 ( .A0(n2481), .A1(n2754), .B0(n2480), .Y(n2482) );
NOR2X2TS U3859 ( .A(n2483), .B(n2482), .Y(n2781) );
INVX4TS U3860 ( .A(n2733), .Y(n2771) );
NAND2X1TS U3861 ( .A(n2772), .B(n2484), .Y(n2485) );
NOR2X4TS U3862 ( .A(n2771), .B(n2485), .Y(n2804) );
NOR3X1TS U3863 ( .A(Raw_mant_NRM_SWR[2]), .B(n4587), .C(Raw_mant_NRM_SWR[1]),
.Y(n2486) );
NAND2X2TS U3864 ( .A(n2804), .B(n2486), .Y(n2779) );
INVX2TS U3865 ( .A(n2762), .Y(n2488) );
NOR2X4TS U3866 ( .A(n2488), .B(n2487), .Y(n2744) );
NOR2X1TS U3867 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[22]), .Y(
n2489) );
INVX2TS U3868 ( .A(n2536), .Y(n2490) );
NAND2X1TS U3869 ( .A(n2762), .B(Raw_mant_NRM_SWR[24]), .Y(n2491) );
AND2X2TS U3870 ( .A(n2549), .B(n2491), .Y(n2765) );
NOR3X1TS U3871 ( .A(n2757), .B(Raw_mant_NRM_SWR[47]), .C(
Raw_mant_NRM_SWR[43]), .Y(n2492) );
NAND2X1TS U3872 ( .A(n2758), .B(n2492), .Y(n2737) );
NOR2X2TS U3873 ( .A(n2737), .B(Raw_mant_NRM_SWR[42]), .Y(n2546) );
NAND2X1TS U3874 ( .A(n2546), .B(n2504), .Y(n2790) );
INVX2TS U3875 ( .A(n2791), .Y(n2494) );
NOR3X1TS U3876 ( .A(n2790), .B(n2494), .C(n2493), .Y(n2500) );
NAND2X2TS U3877 ( .A(n2496), .B(n4510), .Y(n2793) );
NOR2X2TS U3878 ( .A(n2793), .B(Raw_mant_NRM_SWR[30]), .Y(n2503) );
NAND2X1TS U3879 ( .A(n2503), .B(n2495), .Y(n2756) );
OA22X2TS U3880 ( .A0(n2756), .A1(n4580), .B0(n4510), .B1(n2497), .Y(n2550)
);
NOR2X1TS U3881 ( .A(n2787), .B(Raw_mant_NRM_SWR[34]), .Y(n2551) );
NAND2X1TS U3882 ( .A(n2762), .B(Raw_mant_NRM_SWR[23]), .Y(n2498) );
NAND4BX1TS U3883 ( .AN(n2500), .B(n2550), .C(n2499), .D(n2498), .Y(n2501) );
NOR2X1TS U3884 ( .A(n2536), .B(n1994), .Y(n2734) );
NOR2X1TS U3885 ( .A(n2501), .B(n2734), .Y(n2502) );
NAND3X2TS U3886 ( .A(n2779), .B(n2765), .C(n2502), .Y(n2801) );
INVX2TS U3887 ( .A(n2503), .Y(n2553) );
NOR2X1TS U3888 ( .A(n2553), .B(n4611), .Y(n2743) );
INVX2TS U3889 ( .A(n2504), .Y(n2505) );
NOR3X1TS U3890 ( .A(n2757), .B(Raw_mant_NRM_SWR[47]), .C(n4589), .Y(n2506)
);
NAND2X1TS U3891 ( .A(n2758), .B(n2506), .Y(n2523) );
OAI2BB1X1TS U3892 ( .A0N(n2512), .A1N(n2511), .B0(n2510), .Y(n2513) );
AOI21X1TS U3893 ( .A0(n2743), .A1(n4593), .B0(n2515), .Y(n2516) );
OAI21X1TS U3894 ( .A0(n2517), .A1(n4615), .B0(n2516), .Y(n2518) );
NAND2X2TS U3895 ( .A(n2781), .B(n2519), .Y(n4372) );
NAND2X4TS U3896 ( .A(n4372), .B(n3380), .Y(n2694) );
NAND2X1TS U3897 ( .A(n3382), .B(Shift_amount_SHT1_EWR[1]), .Y(n2691) );
BUFX3TS U3898 ( .A(n4674), .Y(n4475) );
INVX4TS U3899 ( .A(n4475), .Y(n3704) );
AOI21X4TS U3900 ( .A0(n2694), .A1(n2691), .B0(n3611), .Y(n3176) );
NOR2X1TS U3901 ( .A(n2794), .B(n4585), .Y(n2797) );
NAND2X1TS U3902 ( .A(n4586), .B(Raw_mant_NRM_SWR[23]), .Y(n2522) );
INVX2TS U3903 ( .A(n2523), .Y(n2524) );
NOR3X1TS U3904 ( .A(n2797), .B(n2525), .C(n2524), .Y(n2526) );
OA21X2TS U3905 ( .A0(n2783), .A1(n2527), .B0(n2526), .Y(n2767) );
NOR2X1TS U3906 ( .A(Raw_mant_NRM_SWR[2]), .B(n4571), .Y(n2528) );
NAND2X2TS U3907 ( .A(n2804), .B(n2528), .Y(n2799) );
CLKINVX1TS U3908 ( .A(n2529), .Y(n2788) );
NAND2X1TS U3909 ( .A(n4552), .B(Raw_mant_NRM_SWR[45]), .Y(n2532) );
AOI21X1TS U3910 ( .A0(n2530), .A1(n4523), .B0(Raw_mant_NRM_SWR[53]), .Y(
n2531) );
OAI22X1TS U3911 ( .A0(n2533), .A1(n2532), .B0(Raw_mant_NRM_SWR[54]), .B1(
n2531), .Y(n2534) );
AOI21X1TS U3912 ( .A0(n2788), .A1(Raw_mant_NRM_SWR[35]), .B0(n2534), .Y(
n2541) );
NAND3X1TS U3913 ( .A(n2778), .B(n4591), .C(n2537), .Y(n2540) );
INVX2TS U3914 ( .A(n2790), .Y(n2538) );
NAND4X1TS U3915 ( .A(n2799), .B(n2541), .C(n2540), .D(n2539), .Y(n2561) );
INVX2TS U3916 ( .A(n2744), .Y(n2544) );
NAND2X1TS U3917 ( .A(n4577), .B(Raw_mant_NRM_SWR[21]), .Y(n2543) );
NOR2X1TS U3918 ( .A(n2544), .B(n2543), .Y(n2796) );
AOI21X1TS U3919 ( .A0(n2546), .A1(n2545), .B0(n2796), .Y(n2547) );
OA21X2TS U3920 ( .A0(n2771), .A1(n2548), .B0(n2547), .Y(n2764) );
INVX2TS U3921 ( .A(n2549), .Y(n2557) );
INVX2TS U3922 ( .A(n2550), .Y(n2555) );
AOI22X1TS U3923 ( .A0(n2551), .A1(Raw_mant_NRM_SWR[33]), .B0(
Raw_mant_NRM_SWR[47]), .B1(n2758), .Y(n2552) );
AOI21X1TS U3924 ( .A0(n2557), .A1(n1994), .B0(n2556), .Y(n2560) );
INVX2TS U3925 ( .A(n2774), .Y(n2558) );
NAND2X1TS U3926 ( .A(n2558), .B(Raw_mant_NRM_SWR[13]), .Y(n2773) );
NAND4X2TS U3927 ( .A(n2764), .B(n2560), .C(n2773), .D(n2559), .Y(n2748) );
NOR2X2TS U3928 ( .A(n2561), .B(n2748), .Y(n2562) );
NAND2X2TS U3929 ( .A(n2767), .B(n2562), .Y(n2563) );
BUFX3TS U3930 ( .A(Shift_reg_FLAGS_7[1]), .Y(n4369) );
NAND2X1TS U3931 ( .A(n4468), .B(ADD_OVRFLW_NRM), .Y(n2565) );
INVX2TS U3932 ( .A(n2565), .Y(n3322) );
CLKBUFX2TS U3933 ( .A(n3322), .Y(n3381) );
AOI21X1TS U3934 ( .A0(Shift_amount_SHT1_EWR[0]), .A1(n4374), .B0(n3381), .Y(
n2564) );
AND2X8TS U3935 ( .A(n4373), .B(n2564), .Y(n3174) );
OAI22X1TS U3936 ( .A0(n2520), .A1(n4523), .B0(n4369), .B1(n4665), .Y(n2567)
);
INVX2TS U3937 ( .A(n2565), .Y(n3357) );
INVX2TS U3938 ( .A(n3357), .Y(n3365) );
INVX2TS U3939 ( .A(n3156), .Y(n2572) );
NAND2X4TS U3940 ( .A(n3176), .B(n2695), .Y(n3616) );
OAI22X1TS U3941 ( .A0(n2520), .A1(n4522), .B0(n4369), .B1(n4664), .Y(n2569)
);
NOR2X1TS U3942 ( .A(n3365), .B(n4576), .Y(n2568) );
NOR2X2TS U3943 ( .A(n2569), .B(n2568), .Y(n3233) );
CLKBUFX2TS U3944 ( .A(n2520), .Y(n3201) );
INVX2TS U3945 ( .A(n3201), .Y(n2785) );
AOI22X1TS U3946 ( .A0(n2785), .A1(Raw_mant_NRM_SWR[53]), .B0(n3322), .B1(
Raw_mant_NRM_SWR[1]), .Y(n3157) );
AOI22X1TS U3947 ( .A0(Raw_mant_NRM_SWR[54]), .A1(n3308), .B0(n3439), .B1(
Data_array_SWR[0]), .Y(n2570) );
NOR2X2TS U3948 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n4567), .Y(n4396) );
OAI21XLTS U3949 ( .A0(n4396), .A1(n2573), .B0(n4394), .Y(n1891) );
INVX2TS U3950 ( .A(n2576), .Y(n2577) );
OAI21X1TS U3951 ( .A0(n3849), .A1(n2578), .B0(n2577), .Y(n3886) );
AOI21X1TS U3952 ( .A0(n3886), .A1(n3882), .B0(n2580), .Y(n2584) );
NAND2X1TS U3953 ( .A(n2583), .B(n2582), .Y(n2587) );
INVX2TS U3954 ( .A(n2587), .Y(n2588) );
XNOR2X1TS U3955 ( .A(n2589), .B(n2588), .Y(n2590) );
BUFX3TS U3956 ( .A(n4448), .Y(n3974) );
AOI22X1TS U3957 ( .A0(n2590), .A1(n4275), .B0(Raw_mant_NRM_SWR[43]), .B1(
n3974), .Y(n2591) );
OAI2BB1X1TS U3958 ( .A0N(n4174), .A1N(n2592), .B0(n2591), .Y(n1226) );
INVX2TS U3959 ( .A(n2593), .Y(n2596) );
OAI21X1TS U3960 ( .A0(n3781), .A1(n2596), .B0(n2595), .Y(n3904) );
NAND2X1TS U3961 ( .A(n2599), .B(n2598), .Y(n2601) );
INVX2TS U3962 ( .A(n2601), .Y(n2600) );
XNOR2X1TS U3963 ( .A(n3904), .B(n2600), .Y(n2605) );
XNOR2X1TS U3964 ( .A(n2602), .B(n2601), .Y(n2603) );
AOI22X1TS U3965 ( .A0(n2603), .A1(n4367), .B0(Raw_mant_NRM_SWR[35]), .B1(
n3747), .Y(n2604) );
OAI2BB1X1TS U3966 ( .A0N(n3979), .A1N(n2605), .B0(n2604), .Y(n1234) );
OA22X1TS U3967 ( .A0(n3693), .A1(n2606), .B0(n4675), .B1(
final_result_ieee[61]), .Y(n1677) );
AOI22X1TS U3968 ( .A0(n1933), .A1(Data_array_SWR[27]), .B0(n1924), .B1(
Data_array_SWR[15]), .Y(n2612) );
AOI22X1TS U3969 ( .A0(n1922), .A1(Data_array_SWR[23]), .B0(n1919), .B1(
Data_array_SWR[19]), .Y(n2611) );
AOI22X1TS U3970 ( .A0(n3654), .A1(Data_array_SWR[42]), .B0(n2981), .B1(
Data_array_SWR[34]), .Y(n2608) );
AOI22X1TS U3971 ( .A0(n2833), .A1(Data_array_SWR[38]), .B0(n2959), .B1(
Data_array_SWR[31]), .Y(n2607) );
NAND2X1TS U3972 ( .A(n2608), .B(n2607), .Y(n2947) );
NAND2X1TS U3973 ( .A(n3651), .B(Data_array_SWR[50]), .Y(n2609) );
AOI22X1TS U3974 ( .A0(n3022), .A1(n2947), .B0(n3023), .B1(n2949), .Y(n2610)
);
AOI22X1TS U3975 ( .A0(n3654), .A1(Data_array_SWR[50]), .B0(n3651), .B1(n1946), .Y(n2614) );
AOI22X1TS U3976 ( .A0(n3652), .A1(Data_array_SWR[46]), .B0(n2870), .B1(n1944), .Y(n2613) );
NAND2X1TS U3977 ( .A(n2614), .B(n2613), .Y(n3685) );
AOI22X1TS U3978 ( .A0(n1928), .A1(n3690), .B0(n4323), .B1(n3685), .Y(n2615)
);
NAND2X1TS U3979 ( .A(n2615), .B(n2665), .Y(n4282) );
BUFX3TS U3980 ( .A(n2955), .Y(n4383) );
AOI22X1TS U3981 ( .A0(n1934), .A1(Data_array_SWR[26]), .B0(n1924), .B1(
Data_array_SWR[14]), .Y(n2621) );
AOI22X1TS U3982 ( .A0(Data_array_SWR[22]), .A1(n1922), .B0(n1919), .B1(
Data_array_SWR[18]), .Y(n2620) );
AOI22X1TS U3983 ( .A0(n3654), .A1(Data_array_SWR[41]), .B0(n2981), .B1(n1937), .Y(n2617) );
AOI22X1TS U3984 ( .A0(n2833), .A1(Data_array_SWR[37]), .B0(n2959), .B1(
Data_array_SWR[30]), .Y(n2616) );
NAND2X1TS U3985 ( .A(n2617), .B(n2616), .Y(n2969) );
AOI22X1TS U3986 ( .A0(Data_array_SWR[53]), .A1(n2958), .B0(n2870), .B1(
Data_array_SWR[45]), .Y(n2618) );
AOI22X1TS U3987 ( .A0(n4296), .A1(n2969), .B0(n3664), .B1(n2971), .Y(n2619)
);
AOI22X1TS U3988 ( .A0(n3654), .A1(Data_array_SWR[51]), .B0(n2869), .B1(
Data_array_SWR[43]), .Y(n2623) );
AOI22X1TS U3989 ( .A0(n2833), .A1(Data_array_SWR[47]), .B0(n2870), .B1(
Data_array_SWR[39]), .Y(n2622) );
NAND2X1TS U3990 ( .A(n2623), .B(n2622), .Y(n3681) );
AOI22X1TS U3991 ( .A0(n1929), .A1(n3684), .B0(n4323), .B1(n3681), .Y(n2624)
);
NAND2X1TS U3992 ( .A(n2624), .B(n2665), .Y(n4281) );
AOI22X1TS U3993 ( .A0(n2982), .A1(Data_array_SWR[37]), .B0(n2958), .B1(
Data_array_SWR[45]), .Y(n2626) );
AOI22X1TS U3994 ( .A0(n2869), .A1(n1948), .B0(Data_array_SWR[49]), .B1(n2405), .Y(n2625) );
NAND2X2TS U3995 ( .A(n2626), .B(n2625), .Y(n4337) );
AOI22X1TS U3996 ( .A0(n1923), .A1(Data_array_SWR[6]), .B0(n1921), .B1(
Data_array_SWR[14]), .Y(n2628) );
AOI22X1TS U3997 ( .A0(Data_array_SWR[18]), .A1(n1933), .B0(
Data_array_SWR[10]), .B1(n1919), .Y(n2627) );
AOI21X1TS U3998 ( .A0(n3664), .A1(n4337), .B0(n2629), .Y(n2654) );
AOI22X1TS U3999 ( .A0(n2982), .A1(Data_array_SWR[47]), .B0(n2981), .B1(
Data_array_SWR[51]), .Y(n2630) );
NAND2X2TS U4000 ( .A(n2630), .B(n2645), .Y(n4302) );
AOI22X1TS U4001 ( .A0(n2833), .A1(Data_array_SWR[30]), .B0(n2959), .B1(
Data_array_SWR[22]), .Y(n2632) );
AOI22X1TS U4002 ( .A0(n2976), .A1(n1937), .B0(n3651), .B1(Data_array_SWR[26]), .Y(n2631) );
NAND2X1TS U4003 ( .A(n2632), .B(n2631), .Y(n4305) );
AOI22X1TS U4004 ( .A0(n4338), .A1(n4302), .B0(n4318), .B1(n4305), .Y(n2633)
);
NAND2X2TS U4005 ( .A(n3648), .B(n1929), .Y(n3686) );
OAI211X1TS U4006 ( .A0(n1928), .A1(n2654), .B0(n2633), .C0(n3686), .Y(n4347)
);
AOI22X1TS U4007 ( .A0(n1923), .A1(Data_array_SWR[5]), .B0(n1921), .B1(
Data_array_SWR[13]), .Y(n2635) );
AOI22X1TS U4008 ( .A0(n1933), .A1(Data_array_SWR[17]), .B0(n1919), .B1(
Data_array_SWR[9]), .Y(n2634) );
AOI21X1TS U4009 ( .A0(n3664), .A1(n4308), .B0(n2636), .Y(n2667) );
AOI22X1TS U4010 ( .A0(n3652), .A1(Data_array_SWR[29]), .B0(n2982), .B1(
Data_array_SWR[21]), .Y(n2638) );
AOI22X1TS U4011 ( .A0(n2976), .A1(Data_array_SWR[33]), .B0(n2869), .B1(
Data_array_SWR[25]), .Y(n2637) );
NAND2X1TS U4012 ( .A(n2638), .B(n2637), .Y(n4312) );
AOI22X1TS U4013 ( .A0(n4338), .A1(n4307), .B0(n4318), .B1(n4312), .Y(n2639)
);
OAI211X1TS U4014 ( .A0(n1928), .A1(n2667), .B0(n2639), .C0(n3686), .Y(n4348)
);
AOI22X1TS U4015 ( .A0(n2982), .A1(Data_array_SWR[35]), .B0(n2958), .B1(
Data_array_SWR[43]), .Y(n2641) );
AOI22X1TS U4016 ( .A0(n2981), .A1(Data_array_SWR[39]), .B0(n2405), .B1(
Data_array_SWR[47]), .Y(n2640) );
NAND2X2TS U4017 ( .A(n2641), .B(n2640), .Y(n4317) );
AOI22X1TS U4018 ( .A0(n1923), .A1(Data_array_SWR[4]), .B0(n1921), .B1(
Data_array_SWR[12]), .Y(n2643) );
AOI22X1TS U4019 ( .A0(n1933), .A1(Data_array_SWR[16]), .B0(n1919), .B1(
Data_array_SWR[8]), .Y(n2642) );
AOI21X1TS U4020 ( .A0(n3023), .A1(n4317), .B0(n2644), .Y(n2652) );
NAND2X1TS U4021 ( .A(n2981), .B(Data_array_SWR[53]), .Y(n2647) );
NAND2X1TS U4022 ( .A(n2982), .B(Data_array_SWR[49]), .Y(n2646) );
NAND3X2TS U4023 ( .A(n2647), .B(n2646), .C(n2645), .Y(n4315) );
AOI22X1TS U4024 ( .A0(n3652), .A1(Data_array_SWR[28]), .B0(n2959), .B1(
Data_array_SWR[20]), .Y(n2649) );
AOI22X1TS U4025 ( .A0(n2976), .A1(Data_array_SWR[32]), .B0(n3651), .B1(
Data_array_SWR[24]), .Y(n2648) );
NAND2X1TS U4026 ( .A(n2649), .B(n2648), .Y(n4322) );
AOI22X1TS U4027 ( .A0(n4338), .A1(n4315), .B0(n4318), .B1(n4322), .Y(n2650)
);
OAI211X1TS U4028 ( .A0(n1929), .A1(n2652), .B0(n2650), .C0(n3686), .Y(n4350)
);
AOI22X1TS U4029 ( .A0(n4323), .A1(n4315), .B0(n4316), .B1(n4322), .Y(n2651)
);
OAI211X1TS U4030 ( .A0(n2652), .A1(n1927), .B0(n2651), .C0(n2665), .Y(n4276)
);
AOI22X1TS U4031 ( .A0(n4323), .A1(n4302), .B0(n4316), .B1(n4305), .Y(n2653)
);
OAI211X1TS U4032 ( .A0(n2654), .A1(n3689), .B0(n2653), .C0(n2665), .Y(n4278)
);
AOI22X1TS U4033 ( .A0(n1934), .A1(Data_array_SWR[24]), .B0(n1924), .B1(
Data_array_SWR[12]), .Y(n2661) );
AOI22X1TS U4034 ( .A0(n1922), .A1(Data_array_SWR[20]), .B0(n1919), .B1(
Data_array_SWR[16]), .Y(n2660) );
AOI22X1TS U4035 ( .A0(n3654), .A1(Data_array_SWR[39]), .B0(n2981), .B1(
Data_array_SWR[32]), .Y(n2656) );
AOI22X1TS U4036 ( .A0(n2833), .A1(Data_array_SWR[35]), .B0(n2959), .B1(
Data_array_SWR[28]), .Y(n2655) );
NAND2X1TS U4037 ( .A(n2656), .B(n2655), .Y(n2963) );
AOI22X1TS U4038 ( .A0(n2833), .A1(Data_array_SWR[51]), .B0(n2959), .B1(
Data_array_SWR[43]), .Y(n2657) );
AOI22X1TS U4039 ( .A0(n3022), .A1(n2963), .B0(n3664), .B1(n3006), .Y(n2659)
);
AOI22X1TS U4040 ( .A0(Data_array_SWR[53]), .A1(n2405), .B0(n2869), .B1(
Data_array_SWR[45]), .Y(n2663) );
AOI22X1TS U4041 ( .A0(Data_array_SWR[49]), .A1(n2958), .B0(n2959), .B1(n1948), .Y(n2662) );
NAND2X1TS U4042 ( .A(n2663), .B(n2662), .Y(n3676) );
AOI22X1TS U4043 ( .A0(n1929), .A1(n3679), .B0(n4323), .B1(n3676), .Y(n2664)
);
NAND2X1TS U4044 ( .A(n2664), .B(n2665), .Y(n4279) );
AOI22X1TS U4045 ( .A0(n4323), .A1(n4307), .B0(n4316), .B1(n4312), .Y(n2666)
);
OAI211X1TS U4046 ( .A0(n2667), .A1(n3689), .B0(n2666), .C0(n2665), .Y(n4277)
);
AOI22X1TS U4047 ( .A0(n2976), .A1(Data_array_SWR[43]), .B0(n2958), .B1(
Data_array_SWR[39]), .Y(n2669) );
AOI22X1TS U4048 ( .A0(n2869), .A1(Data_array_SWR[35]), .B0(n3653), .B1(
Data_array_SWR[32]), .Y(n2668) );
NAND2X2TS U4049 ( .A(n1929), .B(n3664), .Y(n4292) );
AOI22X1TS U4050 ( .A0(n4318), .A1(n4302), .B0(n4316), .B1(n4337), .Y(n2670)
);
AOI21X1TS U4051 ( .A0(n4338), .A1(n4305), .B0(n2671), .Y(n2672) );
OAI21X1TS U4052 ( .A0(n4332), .A1(n4340), .B0(n2672), .Y(n4295) );
AOI22X1TS U4053 ( .A0(n2405), .A1(Data_array_SWR[45]), .B0(n2958), .B1(n1948), .Y(n2674) );
AOI22X1TS U4054 ( .A0(n2869), .A1(Data_array_SWR[37]), .B0(n2959), .B1(n1937), .Y(n2673) );
AOI22X1TS U4055 ( .A0(n4318), .A1(n4315), .B0(n4316), .B1(n4317), .Y(n2675)
);
AOI21X1TS U4056 ( .A0(n4338), .A1(n4322), .B0(n2676), .Y(n2677) );
OAI21X1TS U4057 ( .A0(n4326), .A1(n4340), .B0(n2677), .Y(n4289) );
NAND2X1TS U4058 ( .A(n2682), .B(n2681), .Y(n2685) );
INVX2TS U4059 ( .A(n2685), .Y(n2683) );
XNOR2X1TS U4060 ( .A(n2684), .B(n2683), .Y(n2688) );
XOR2X1TS U4061 ( .A(n3849), .B(n2685), .Y(n2686) );
AOI22X1TS U4062 ( .A0(n2686), .A1(n4367), .B0(Raw_mant_NRM_SWR[34]), .B1(
n3747), .Y(n2687) );
OAI2BB1X1TS U4063 ( .A0N(n3979), .A1N(n2688), .B0(n2687), .Y(n1235) );
NAND2X1TS U4064 ( .A(n2520), .B(Raw_mant_NRM_SWR[54]), .Y(n2690) );
NAND2X1TS U4065 ( .A(n3361), .B(Raw_mant_NRM_SWR[0]), .Y(n2689) );
INVX2TS U4066 ( .A(n2691), .Y(n2692) );
BUFX3TS U4067 ( .A(n3588), .Y(n3465) );
INVX2TS U4068 ( .A(n3357), .Y(n3429) );
NAND2X1TS U4069 ( .A(n3430), .B(Raw_mant_NRM_SWR[1]), .Y(n2697) );
BUFX3TS U4070 ( .A(Shift_reg_FLAGS_7[1]), .Y(n4480) );
NAND2X1TS U4071 ( .A(n3323), .B(DmP_mant_SHT1_SW[51]), .Y(n2696) );
NAND3X1TS U4072 ( .A(n2698), .B(n2697), .C(n2696), .Y(n3252) );
AOI22X1TS U4073 ( .A0(n1995), .A1(n1930), .B0(n3465), .B1(n3252), .Y(n2702)
);
NAND2X4TS U4074 ( .A(n3164), .B(n3174), .Y(n3158) );
BUFX3TS U4075 ( .A(n3551), .Y(n3435) );
NAND2X1TS U4076 ( .A(n3380), .B(Raw_mant_NRM_SWR[2]), .Y(n2810) );
NAND2X1TS U4077 ( .A(n3696), .B(DmP_mant_SHT1_SW[50]), .Y(n2699) );
AOI22X1TS U4078 ( .A0(n3435), .A1(n3338), .B0(Data_array_SWR[51]), .B1(n3604), .Y(n2701) );
NAND2X1TS U4079 ( .A(n2702), .B(n2701), .Y(n1750) );
INVX2TS U4080 ( .A(rst), .Y(n2726) );
CLKBUFX3TS U4081 ( .A(n2726), .Y(n4754) );
CLKBUFX3TS U4082 ( .A(n4754), .Y(n2703) );
CLKBUFX3TS U4083 ( .A(n2703), .Y(n2708) );
BUFX3TS U4084 ( .A(n2708), .Y(n4706) );
BUFX3TS U4085 ( .A(n2704), .Y(n4705) );
BUFX3TS U4086 ( .A(n2708), .Y(n4704) );
BUFX3TS U4087 ( .A(n2708), .Y(n4703) );
BUFX3TS U4088 ( .A(n2708), .Y(n4702) );
CLKBUFX3TS U4089 ( .A(n2726), .Y(n2711) );
CLKBUFX3TS U4090 ( .A(n2711), .Y(n2705) );
BUFX3TS U4091 ( .A(n2706), .Y(n4700) );
CLKBUFX2TS U4092 ( .A(n4754), .Y(n4753) );
BUFX3TS U4093 ( .A(n4753), .Y(n4752) );
BUFX3TS U4094 ( .A(n2703), .Y(n4751) );
BUFX3TS U4095 ( .A(n2711), .Y(n4699) );
BUFX3TS U4096 ( .A(n2705), .Y(n4717) );
BUFX3TS U4097 ( .A(n2710), .Y(n4716) );
BUFX3TS U4098 ( .A(n2705), .Y(n4715) );
BUFX3TS U4099 ( .A(n2708), .Y(n4714) );
BUFX3TS U4100 ( .A(n2705), .Y(n4712) );
BUFX3TS U4101 ( .A(n2709), .Y(n4711) );
BUFX3TS U4102 ( .A(n2707), .Y(n4710) );
BUFX3TS U4103 ( .A(n2708), .Y(n4709) );
BUFX3TS U4104 ( .A(n2706), .Y(n4708) );
BUFX3TS U4105 ( .A(n2706), .Y(n4707) );
BUFX3TS U4106 ( .A(n2704), .Y(n4680) );
BUFX3TS U4107 ( .A(n2705), .Y(n4679) );
BUFX3TS U4108 ( .A(n2704), .Y(n4678) );
BUFX3TS U4109 ( .A(n2704), .Y(n4677) );
BUFX3TS U4110 ( .A(n2703), .Y(n4749) );
BUFX3TS U4111 ( .A(n2703), .Y(n4748) );
BUFX3TS U4112 ( .A(n2703), .Y(n4747) );
BUFX3TS U4113 ( .A(n2706), .Y(n4697) );
BUFX3TS U4114 ( .A(n2703), .Y(n4746) );
BUFX3TS U4115 ( .A(n2703), .Y(n4750) );
BUFX3TS U4116 ( .A(n2710), .Y(n4696) );
BUFX3TS U4117 ( .A(n2706), .Y(n4695) );
BUFX3TS U4118 ( .A(n2706), .Y(n4694) );
BUFX3TS U4119 ( .A(n2706), .Y(n4693) );
BUFX3TS U4120 ( .A(n2703), .Y(n4692) );
BUFX3TS U4121 ( .A(n2707), .Y(n4691) );
BUFX3TS U4122 ( .A(n2707), .Y(n4690) );
BUFX3TS U4123 ( .A(n2705), .Y(n4718) );
BUFX3TS U4124 ( .A(n2707), .Y(n4685) );
BUFX3TS U4125 ( .A(n2704), .Y(n4676) );
BUFX3TS U4126 ( .A(n2709), .Y(n4738) );
BUFX3TS U4127 ( .A(n2709), .Y(n4689) );
BUFX3TS U4128 ( .A(n2705), .Y(n4737) );
BUFX3TS U4129 ( .A(n2704), .Y(n4739) );
BUFX3TS U4130 ( .A(n2711), .Y(n4729) );
BUFX3TS U4131 ( .A(n2703), .Y(n4681) );
BUFX3TS U4132 ( .A(n2707), .Y(n4684) );
BUFX3TS U4133 ( .A(n2711), .Y(n4682) );
BUFX3TS U4134 ( .A(n2707), .Y(n4688) );
BUFX3TS U4135 ( .A(n2704), .Y(n4683) );
BUFX3TS U4136 ( .A(n2707), .Y(n4686) );
BUFX3TS U4137 ( .A(n2708), .Y(n4687) );
BUFX3TS U4138 ( .A(n2711), .Y(n4731) );
BUFX3TS U4139 ( .A(n2711), .Y(n4732) );
BUFX3TS U4140 ( .A(n2711), .Y(n4733) );
BUFX3TS U4141 ( .A(n2711), .Y(n4735) );
BUFX3TS U4142 ( .A(n2705), .Y(n4723) );
BUFX3TS U4143 ( .A(n2705), .Y(n4719) );
BUFX3TS U4144 ( .A(n2706), .Y(n4720) );
BUFX3TS U4145 ( .A(n2710), .Y(n4721) );
BUFX3TS U4146 ( .A(n2707), .Y(n4722) );
BUFX3TS U4147 ( .A(n2710), .Y(n4724) );
BUFX3TS U4148 ( .A(n2709), .Y(n4745) );
BUFX3TS U4149 ( .A(n2709), .Y(n4741) );
BUFX3TS U4150 ( .A(n2710), .Y(n4725) );
BUFX3TS U4151 ( .A(n2709), .Y(n4744) );
BUFX3TS U4152 ( .A(n2710), .Y(n4734) );
BUFX3TS U4153 ( .A(n2710), .Y(n4727) );
BUFX3TS U4154 ( .A(n2709), .Y(n4743) );
BUFX3TS U4155 ( .A(n2710), .Y(n4726) );
BUFX3TS U4156 ( .A(n2711), .Y(n4742) );
BUFX3TS U4157 ( .A(n3979), .Y(n4271) );
INVX2TS U4158 ( .A(n2712), .Y(n4166) );
INVX2TS U4159 ( .A(n2713), .Y(n2716) );
INVX2TS U4160 ( .A(n2714), .Y(n2715) );
OAI21X1TS U4161 ( .A0(n4166), .A1(n2716), .B0(n2715), .Y(n4111) );
NAND2X1TS U4162 ( .A(n2719), .B(n2718), .Y(n2721) );
INVX2TS U4163 ( .A(n2721), .Y(n2720) );
XNOR2X1TS U4164 ( .A(n4111), .B(n2720), .Y(n2725) );
XNOR2X1TS U4165 ( .A(n2722), .B(n2721), .Y(n2723) );
BUFX3TS U4166 ( .A(n4174), .Y(n4160) );
BUFX3TS U4167 ( .A(n4448), .Y(n4213) );
AOI22X1TS U4168 ( .A0(n2723), .A1(n4160), .B0(Raw_mant_NRM_SWR[11]), .B1(
n4213), .Y(n2724) );
OAI2BB1X1TS U4169 ( .A0N(n4271), .A1N(n2725), .B0(n2724), .Y(n1258) );
BUFX3TS U4170 ( .A(n2726), .Y(n4701) );
BUFX3TS U4171 ( .A(n2726), .Y(n4713) );
BUFX3TS U4172 ( .A(n2726), .Y(n4698) );
BUFX3TS U4173 ( .A(n2726), .Y(n4730) );
BUFX3TS U4174 ( .A(n2726), .Y(n4736) );
BUFX3TS U4175 ( .A(n2709), .Y(n4728) );
BUFX3TS U4176 ( .A(n2726), .Y(n4740) );
NAND2X1TS U4177 ( .A(DmP_EXP_EWSW[52]), .B(n4606), .Y(n4255) );
OA21XLTS U4178 ( .A0(DmP_EXP_EWSW[52]), .A1(n4606), .B0(n4255), .Y(n2728) );
BUFX3TS U4179 ( .A(n4629), .Y(n4458) );
NAND2X1TS U4180 ( .A(n4458), .B(Shift_amount_SHT1_EWR[0]), .Y(n2727) );
INVX2TS U4181 ( .A(n3357), .Y(n3618) );
INVX2TS U4182 ( .A(n3631), .Y(n3643) );
AOI22X1TS U4183 ( .A0(n2730), .A1(n3624), .B0(DmP_mant_SFG_SWR[53]), .B1(
n4349), .Y(n2729) );
INVX2TS U4184 ( .A(n3624), .Y(n3645) );
AOI22X1TS U4185 ( .A0(n2730), .A1(n3631), .B0(DmP_mant_SFG_SWR[1]), .B1(
n4349), .Y(n2731) );
INVX2TS U4186 ( .A(n2734), .Y(n2735) );
OAI211X1TS U4187 ( .A0(n2738), .A1(n2737), .B0(n2736), .C0(n2735), .Y(n2753)
);
INVX2TS U4188 ( .A(n2753), .Y(n2746) );
OAI22X1TS U4189 ( .A0(n2787), .A1(n2741), .B0(n2740), .B1(n2739), .Y(n2742)
);
AOI211X1TS U4190 ( .A0(n2744), .A1(Raw_mant_NRM_SWR[22]), .B0(n2743), .C0(
n2742), .Y(n2745) );
AOI211X1TS U4191 ( .A0(n2755), .A1(Raw_mant_NRM_SWR[12]), .B0(n2749), .C0(
n2748), .Y(n2752) );
NAND2X1TS U4192 ( .A(n3696), .B(LZD_output_NRM2_EW[2]), .Y(n2750) );
NOR2X2TS U4193 ( .A(n3439), .B(n4369), .Y(n2806) );
AOI22X1TS U4194 ( .A0(n2806), .A1(Shift_amount_SHT1_EWR[2]), .B0(
shift_value_SHT2_EWR[2]), .B1(n3611), .Y(n2751) );
NOR3X1TS U4195 ( .A(n2756), .B(Raw_mant_NRM_SWR[27]), .C(n4630), .Y(n2761)
);
AOI211X1TS U4196 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n2762), .B0(n2761), .C0(
n2760), .Y(n2763) );
AND4X1TS U4197 ( .A(n2766), .B(n2765), .C(n2764), .D(n2763), .Y(n2768) );
OAI211X1TS U4198 ( .A0(n2783), .A1(n4660), .B0(n2768), .C0(n2767), .Y(n4371)
);
INVX2TS U4199 ( .A(n1899), .Y(n2784) );
AOI222X1TS U4200 ( .A0(n4371), .A1(n3375), .B0(n2806), .B1(
Shift_amount_SHT1_EWR[3]), .C0(shift_value_SHT2_EWR[3]), .C1(n2784),
.Y(n2769) );
INVX2TS U4201 ( .A(n2769), .Y(n1696) );
NAND3XLTS U4202 ( .A(n4505), .B(n4615), .C(n2770), .Y(n2777) );
AOI21X1TS U4203 ( .A0(n2772), .A1(n4620), .B0(n2771), .Y(n2776) );
AOI211X1TS U4204 ( .A0(n2778), .A1(n2777), .B0(n2776), .C0(n2775), .Y(n2780)
);
OAI211X1TS U4205 ( .A0(n2783), .A1(n4626), .B0(n2782), .C0(n2781), .Y(n4370)
);
INVX2TS U4206 ( .A(n2786), .Y(n1693) );
OAI31X1TS U4207 ( .A0(Raw_mant_NRM_SWR[41]), .A1(n2791), .A2(n2790), .B0(
n2789), .Y(n2798) );
NOR4X1TS U4208 ( .A(Raw_mant_NRM_SWR[30]), .B(Raw_mant_NRM_SWR[29]), .C(
Raw_mant_NRM_SWR[28]), .D(Raw_mant_NRM_SWR[26]), .Y(n2792) );
OAI22X1TS U4209 ( .A0(n2794), .A1(n4577), .B0(n2793), .B1(n2792), .Y(n2795)
);
NOR4X1TS U4210 ( .A(n2798), .B(n2797), .C(n2796), .D(n2795), .Y(n2800) );
AOI21X1TS U4211 ( .A0(n2804), .A1(Raw_mant_NRM_SWR[2]), .B0(n2805), .Y(n2803) );
NAND2X1TS U4212 ( .A(n3696), .B(LZD_output_NRM2_EW[4]), .Y(n2802) );
INVX2TS U4213 ( .A(n2804), .Y(n2809) );
NAND2X1TS U4214 ( .A(n2805), .B(n3361), .Y(n2808) );
AOI22X1TS U4215 ( .A0(n2806), .A1(Shift_amount_SHT1_EWR[4]), .B0(
shift_value_SHT2_EWR[4]), .B1(n3439), .Y(n2807) );
INVX2TS U4216 ( .A(n3822), .Y(n3806) );
INVX2TS U4217 ( .A(n2813), .Y(n2816) );
INVX2TS U4218 ( .A(n2814), .Y(n2815) );
INVX2TS U4219 ( .A(n3833), .Y(n2818) );
AOI21X1TS U4220 ( .A0(n3838), .A1(n3834), .B0(n2818), .Y(n2822) );
NAND2X1TS U4221 ( .A(n2821), .B(n2820), .Y(n2827) );
INVX2TS U4222 ( .A(n2823), .Y(n2826) );
INVX2TS U4223 ( .A(n2824), .Y(n2825) );
OAI21X1TS U4224 ( .A0(n3781), .A1(n2826), .B0(n2825), .Y(n3880) );
INVX2TS U4225 ( .A(n2827), .Y(n2828) );
XNOR2X1TS U4226 ( .A(n3880), .B(n2828), .Y(n2829) );
AOI22X1TS U4227 ( .A0(n2829), .A1(n4275), .B0(Raw_mant_NRM_SWR[41]), .B1(
n3974), .Y(n2830) );
AOI21X1TS U4228 ( .A0(n3611), .A1(Data_array_SWR[53]), .B0(n3381), .Y(n2832)
);
AOI22X1TS U4229 ( .A0(Data_array_SWR[26]), .A1(n2833), .B0(n3651), .B1(
Data_array_SWR[22]), .Y(n2835) );
AOI22X1TS U4230 ( .A0(n3654), .A1(Data_array_SWR[30]), .B0(n2870), .B1(
Data_array_SWR[18]), .Y(n2834) );
NAND2X1TS U4231 ( .A(n2835), .B(n2834), .Y(n2857) );
INVX2TS U4232 ( .A(n4315), .Y(n2844) );
OAI22X1TS U4233 ( .A0(n2844), .A1(n4292), .B0(n4326), .B1(n4329), .Y(n2836)
);
AOI211X1TS U4234 ( .A0(n1938), .A1(n4317), .B0(n2837), .C0(n2836), .Y(n2838)
);
OAI2BB1X1TS U4235 ( .A0N(n1941), .A1N(n2857), .B0(n2838), .Y(n4288) );
OAI22X1TS U4236 ( .A0(n2839), .A1(n4292), .B0(n4314), .B1(n4329), .Y(n2840)
);
AOI211X1TS U4237 ( .A0(n1938), .A1(n4308), .B0(n2841), .C0(n2840), .Y(n2842)
);
OAI2BB1X1TS U4238 ( .A0N(n1941), .A1N(n2843), .B0(n2842), .Y(n4287) );
OAI22X1TS U4239 ( .A0(n2844), .A1(n4333), .B0(n4326), .B1(n4331), .Y(n2845)
);
AOI211X1TS U4240 ( .A0(n1941), .A1(n4317), .B0(n2846), .C0(n2845), .Y(n2847)
);
OAI2BB1X1TS U4241 ( .A0N(n1938), .A1N(n2857), .B0(n2847), .Y(n4327) );
AOI22X1TS U4242 ( .A0(intDX_EWSW[1]), .A1(n3057), .B0(DMP_EXP_EWSW[1]), .B1(
n4432), .Y(n2848) );
AOI22X1TS U4243 ( .A0(intDX_EWSW[3]), .A1(n3057), .B0(DMP_EXP_EWSW[3]), .B1(
n3110), .Y(n2849) );
AOI22X1TS U4244 ( .A0(DMP_EXP_EWSW[57]), .A1(n4397), .B0(intDX_EWSW[57]),
.B1(n3057), .Y(n2850) );
AOI22X1TS U4245 ( .A0(intDX_EWSW[6]), .A1(n3057), .B0(DMP_EXP_EWSW[6]), .B1(
n3110), .Y(n2851) );
AOI22X1TS U4246 ( .A0(intDX_EWSW[2]), .A1(n3057), .B0(DMP_EXP_EWSW[2]), .B1(
n4432), .Y(n2852) );
AOI22X1TS U4247 ( .A0(intDX_EWSW[4]), .A1(n3057), .B0(DMP_EXP_EWSW[4]), .B1(
n3110), .Y(n2853) );
INVX2TS U4248 ( .A(n2854), .Y(n1294) );
INVX2TS U4249 ( .A(n4326), .Y(n2855) );
NAND2X1TS U4250 ( .A(n2855), .B(n3023), .Y(n2861) );
INVX2TS U4251 ( .A(n2856), .Y(n3660) );
AOI22X1TS U4252 ( .A0(n2857), .A1(n4296), .B0(n3660), .B1(n4315), .Y(n2860)
);
AOI22X1TS U4253 ( .A0(n1922), .A1(Data_array_SWR[10]), .B0(n1924), .B1(
Data_array_SWR[2]), .Y(n2859) );
AOI22X1TS U4254 ( .A0(Data_array_SWR[14]), .A1(n1934), .B0(n1920), .B1(
Data_array_SWR[6]), .Y(n2858) );
NAND4X1TS U4255 ( .A(n2861), .B(n2860), .C(n2859), .D(n2858), .Y(n3048) );
INVX2TS U4256 ( .A(n3048), .Y(n3646) );
INVX2TS U4257 ( .A(n4320), .Y(n2862) );
INVX2TS U4258 ( .A(n3647), .Y(n2863) );
AOI22X1TS U4259 ( .A0(n2950), .A1(n2863), .B0(final_result_ieee[50]), .B1(
n3697), .Y(n2864) );
OA21X1TS U4260 ( .A0(Data_array_SWR[50]), .A1(n2866), .B0(n2865), .Y(n3027)
);
AOI22X1TS U4261 ( .A0(n3654), .A1(Data_array_SWR[31]), .B0(n3651), .B1(
Data_array_SWR[23]), .Y(n2868) );
AOI22X1TS U4262 ( .A0(n3652), .A1(Data_array_SWR[27]), .B0(n2870), .B1(
Data_array_SWR[19]), .Y(n2867) );
NAND2X1TS U4263 ( .A(n2868), .B(n2867), .Y(n3021) );
AOI22X1TS U4264 ( .A0(n3027), .A1(n3660), .B0(n4296), .B1(n3021), .Y(n2876)
);
AOI22X1TS U4265 ( .A0(n1920), .A1(Data_array_SWR[7]), .B0(n1924), .B1(
Data_array_SWR[3]), .Y(n2875) );
AOI22X1TS U4266 ( .A0(n1934), .A1(Data_array_SWR[15]), .B0(n1922), .B1(
Data_array_SWR[11]), .Y(n2874) );
AOI22X1TS U4267 ( .A0(n3654), .A1(Data_array_SWR[46]), .B0(n3651), .B1(n1944), .Y(n2872) );
AOI22X1TS U4268 ( .A0(n3652), .A1(n1946), .B0(n2870), .B1(Data_array_SWR[34]), .Y(n2871) );
NAND2X1TS U4269 ( .A(n2872), .B(n2871), .Y(n3030) );
NAND2X1TS U4270 ( .A(n3030), .B(n3023), .Y(n2873) );
NAND4X1TS U4271 ( .A(n2876), .B(n2875), .C(n2874), .D(n2873), .Y(n3035) );
INVX2TS U4272 ( .A(n3035), .Y(n3632) );
AOI22X1TS U4273 ( .A0(n2950), .A1(n1902), .B0(final_result_ieee[49]), .B1(
n3697), .Y(n2877) );
NAND2X1TS U4274 ( .A(n3022), .B(n2976), .Y(n2941) );
AOI22X1TS U4275 ( .A0(n1921), .A1(Data_array_SWR[16]), .B0(n1923), .B1(
Data_array_SWR[8]), .Y(n2878) );
AOI21X1TS U4276 ( .A0(n3664), .A1(n3681), .B0(n2879), .Y(n2881) );
AOI22X1TS U4277 ( .A0(n1934), .A1(Data_array_SWR[20]), .B0(n1920), .B1(
Data_array_SWR[12]), .Y(n2880) );
OAI211X1TS U4278 ( .A0(n2974), .A1(n3659), .B0(n2881), .C0(n2880), .Y(n2967)
);
INVX2TS U4279 ( .A(n2967), .Y(n3635) );
NAND2X2TS U4280 ( .A(n2882), .B(n2323), .Y(n3005) );
INVX2TS U4281 ( .A(n3636), .Y(n2883) );
AOI22X1TS U4282 ( .A0(n2950), .A1(n2883), .B0(final_result_ieee[44]), .B1(
n3697), .Y(n2884) );
AOI22X1TS U4283 ( .A0(n1921), .A1(Data_array_SWR[15]), .B0(n1923), .B1(
Data_array_SWR[7]), .Y(n2885) );
AOI21X1TS U4284 ( .A0(n3664), .A1(n3685), .B0(n2886), .Y(n2888) );
AOI22X1TS U4285 ( .A0(n3657), .A1(Data_array_SWR[19]), .B0(n1920), .B1(
Data_array_SWR[11]), .Y(n2887) );
OAI211X1TS U4286 ( .A0(n2953), .A1(n2398), .B0(n2888), .C0(n2887), .Y(n3003)
);
INVX2TS U4287 ( .A(n3003), .Y(n3633) );
INVX2TS U4288 ( .A(n3634), .Y(n2889) );
AOI22X1TS U4289 ( .A0(n2950), .A1(n2889), .B0(final_result_ieee[45]), .B1(
n3697), .Y(n2890) );
AOI22X1TS U4290 ( .A0(intDX_EWSW[49]), .A1(n3090), .B0(DmP_EXP_EWSW[49]),
.B1(n4397), .Y(n2891) );
AOI22X1TS U4291 ( .A0(intDX_EWSW[15]), .A1(n3066), .B0(DmP_EXP_EWSW[15]),
.B1(n2310), .Y(n2893) );
BUFX3TS U4292 ( .A(n2907), .Y(n3547) );
AOI22X1TS U4293 ( .A0(intDX_EWSW[3]), .A1(n3126), .B0(DmP_EXP_EWSW[3]), .B1(
n3547), .Y(n2894) );
AOI22X1TS U4294 ( .A0(intDX_EWSW[14]), .A1(n3066), .B0(DmP_EXP_EWSW[14]),
.B1(n2310), .Y(n2895) );
INVX4TS U4295 ( .A(n2896), .Y(n3546) );
AOI22X1TS U4296 ( .A0(intDX_EWSW[1]), .A1(n3126), .B0(DmP_EXP_EWSW[1]), .B1(
n3547), .Y(n2897) );
BUFX3TS U4297 ( .A(n2928), .Y(n3115) );
AOI22X1TS U4298 ( .A0(intDX_EWSW[15]), .A1(n2892), .B0(DMP_EXP_EWSW[15]),
.B1(n3115), .Y(n2898) );
BUFX3TS U4299 ( .A(n2907), .Y(n3086) );
AOI22X1TS U4300 ( .A0(intDX_EWSW[39]), .A1(n3078), .B0(DmP_EXP_EWSW[39]),
.B1(n3086), .Y(n2899) );
AOI22X1TS U4301 ( .A0(intDX_EWSW[14]), .A1(n2892), .B0(DMP_EXP_EWSW[14]),
.B1(n3115), .Y(n2900) );
BUFX3TS U4302 ( .A(n4432), .Y(n3119) );
AOI22X1TS U4303 ( .A0(intDX_EWSW[39]), .A1(n3122), .B0(DMP_EXP_EWSW[39]),
.B1(n3119), .Y(n2901) );
AOI22X1TS U4304 ( .A0(intDY_EWSW[61]), .A1(n3148), .B0(DMP_EXP_EWSW[61]),
.B1(n3547), .Y(n2902) );
BUFX3TS U4305 ( .A(n2928), .Y(n3147) );
AOI22X1TS U4306 ( .A0(intDX_EWSW[49]), .A1(n3144), .B0(DMP_EXP_EWSW[49]),
.B1(n3147), .Y(n2903) );
INVX2TS U4307 ( .A(n3252), .Y(n3343) );
BUFX3TS U4308 ( .A(n3588), .Y(n3613) );
AOI22X1TS U4309 ( .A0(n3613), .A1(n1930), .B0(Data_array_SWR[52]), .B1(n3604), .Y(n2904) );
AOI22X1TS U4310 ( .A0(intDY_EWSW[62]), .A1(n3148), .B0(DMP_EXP_EWSW[62]),
.B1(n3547), .Y(n2905) );
AOI22X1TS U4311 ( .A0(intDY_EWSW[59]), .A1(n3148), .B0(DMP_EXP_EWSW[59]),
.B1(n3547), .Y(n2906) );
BUFX3TS U4312 ( .A(n2907), .Y(n3125) );
AOI22X1TS U4313 ( .A0(intDX_EWSW[8]), .A1(n3126), .B0(DmP_EXP_EWSW[8]), .B1(
n3125), .Y(n2908) );
AOI22X1TS U4314 ( .A0(intDX_EWSW[11]), .A1(n3126), .B0(DmP_EXP_EWSW[11]),
.B1(n3125), .Y(n2909) );
AOI22X1TS U4315 ( .A0(intDY_EWSW[60]), .A1(n3148), .B0(DMP_EXP_EWSW[60]),
.B1(n3547), .Y(n2910) );
AOI22X1TS U4316 ( .A0(intDX_EWSW[18]), .A1(n3066), .B0(DmP_EXP_EWSW[18]),
.B1(n2310), .Y(n2911) );
AOI22X1TS U4317 ( .A0(intDX_EWSW[17]), .A1(n3066), .B0(DmP_EXP_EWSW[17]),
.B1(n2310), .Y(n2912) );
AOI22X1TS U4318 ( .A0(intDX_EWSW[0]), .A1(n3148), .B0(DmP_EXP_EWSW[0]), .B1(
n3547), .Y(n2913) );
AOI22X1TS U4319 ( .A0(intDX_EWSW[31]), .A1(n3087), .B0(DmP_EXP_EWSW[31]),
.B1(n3077), .Y(n2915) );
AOI22X1TS U4320 ( .A0(intDX_EWSW[23]), .A1(n3078), .B0(DmP_EXP_EWSW[23]),
.B1(n2310), .Y(n2916) );
AOI22X1TS U4321 ( .A0(intDX_EWSW[26]), .A1(n3078), .B0(DmP_EXP_EWSW[26]),
.B1(n3077), .Y(n2917) );
AOI22X1TS U4322 ( .A0(intDX_EWSW[50]), .A1(n3090), .B0(DmP_EXP_EWSW[50]),
.B1(n4397), .Y(n2918) );
AOI22X1TS U4323 ( .A0(intDX_EWSW[25]), .A1(n3078), .B0(DmP_EXP_EWSW[25]),
.B1(n3547), .Y(n2919) );
AOI22X1TS U4324 ( .A0(intDX_EWSW[36]), .A1(n3087), .B0(DmP_EXP_EWSW[36]),
.B1(n3086), .Y(n2920) );
AOI22X1TS U4325 ( .A0(intDX_EWSW[43]), .A1(n3090), .B0(DmP_EXP_EWSW[43]),
.B1(n3086), .Y(n2921) );
AOI22X1TS U4326 ( .A0(intDX_EWSW[33]), .A1(n3087), .B0(DmP_EXP_EWSW[33]),
.B1(n3077), .Y(n2922) );
AOI22X1TS U4327 ( .A0(intDX_EWSW[35]), .A1(n3087), .B0(DmP_EXP_EWSW[35]),
.B1(n3077), .Y(n2923) );
AOI22X1TS U4328 ( .A0(DmP_EXP_EWSW[57]), .A1(n4397), .B0(intDX_EWSW[57]),
.B1(n3148), .Y(n2924) );
AOI22X1TS U4329 ( .A0(intDX_EWSW[45]), .A1(n3090), .B0(DmP_EXP_EWSW[45]),
.B1(n3086), .Y(n2925) );
AOI22X1TS U4330 ( .A0(intDX_EWSW[8]), .A1(n2892), .B0(DMP_EXP_EWSW[8]), .B1(
n3110), .Y(n2926) );
AOI22X1TS U4331 ( .A0(intDX_EWSW[11]), .A1(n2892), .B0(DMP_EXP_EWSW[11]),
.B1(n3110), .Y(n2927) );
BUFX3TS U4332 ( .A(n2928), .Y(n3106) );
AOI22X1TS U4333 ( .A0(intDX_EWSW[23]), .A1(n2896), .B0(DMP_EXP_EWSW[23]),
.B1(n3106), .Y(n2929) );
AOI22X1TS U4334 ( .A0(intDX_EWSW[31]), .A1(n3113), .B0(DMP_EXP_EWSW[31]),
.B1(n3106), .Y(n2932) );
AOI22X1TS U4335 ( .A0(intDX_EWSW[26]), .A1(n3113), .B0(DMP_EXP_EWSW[26]),
.B1(n3106), .Y(n2933) );
AOI22X1TS U4336 ( .A0(intDX_EWSW[18]), .A1(n2896), .B0(DMP_EXP_EWSW[18]),
.B1(n3115), .Y(n2934) );
AOI22X1TS U4337 ( .A0(intDX_EWSW[17]), .A1(n2896), .B0(DMP_EXP_EWSW[17]),
.B1(n3115), .Y(n2935) );
AOI22X1TS U4338 ( .A0(intDX_EWSW[25]), .A1(n2896), .B0(DMP_EXP_EWSW[25]),
.B1(n3147), .Y(n2936) );
AOI22X1TS U4339 ( .A0(intDX_EWSW[36]), .A1(n3122), .B0(DMP_EXP_EWSW[36]),
.B1(n3119), .Y(n2937) );
AOI22X1TS U4340 ( .A0(n1921), .A1(Data_array_SWR[17]), .B0(n1923), .B1(
Data_array_SWR[9]), .Y(n2940) );
AOI21X1TS U4341 ( .A0(n3023), .A1(n3672), .B0(n2942), .Y(n2944) );
AOI22X1TS U4342 ( .A0(n3657), .A1(Data_array_SWR[21]), .B0(n1920), .B1(
Data_array_SWR[13]), .Y(n2943) );
OAI211X1TS U4343 ( .A0(n2997), .A1(n2398), .B0(n2944), .C0(n2943), .Y(n2956)
);
INVX2TS U4344 ( .A(n2956), .Y(n3642) );
INVX2TS U4345 ( .A(n3644), .Y(n2945) );
AOI22X1TS U4346 ( .A0(n3045), .A1(n2945), .B0(final_result_ieee[43]), .B1(
n3697), .Y(n2946) );
AOI21X1TS U4347 ( .A0(n1934), .A1(Data_array_SWR[34]), .B0(n1917), .Y(n2952)
);
NAND2X1TS U4348 ( .A(n3685), .B(n3022), .Y(n2951) );
OAI211X1TS U4349 ( .A0(n2953), .A1(n2323), .B0(n2952), .C0(n2951), .Y(n3016)
);
BUFX3TS U4350 ( .A(n2955), .Y(n3044) );
AOI22X1TS U4351 ( .A0(n3049), .A1(n3016), .B0(final_result_ieee[21]), .B1(
n3044), .Y(n2954) );
BUFX3TS U4352 ( .A(n2955), .Y(n4391) );
AOI22X1TS U4353 ( .A0(n3049), .A1(n2956), .B0(final_result_ieee[7]), .B1(
n4391), .Y(n2957) );
AOI22X1TS U4354 ( .A0(n2976), .A1(Data_array_SWR[37]), .B0(n2958), .B1(n1937), .Y(n2961) );
AOI22X1TS U4355 ( .A0(n3651), .A1(Data_array_SWR[30]), .B0(n2959), .B1(
Data_array_SWR[26]), .Y(n2960) );
NAND2X1TS U4356 ( .A(n3676), .B(n4296), .Y(n2962) );
OAI211X1TS U4357 ( .A0(n3012), .A1(n2323), .B0(n1908), .C0(n2962), .Y(n3033)
);
INVX2TS U4358 ( .A(n3033), .Y(n3619) );
INVX2TS U4359 ( .A(n3620), .Y(n2965) );
AOI22X1TS U4360 ( .A0(n3045), .A1(n2965), .B0(final_result_ieee[26]), .B1(
n3044), .Y(n2966) );
AOI22X1TS U4361 ( .A0(n3049), .A1(n2967), .B0(final_result_ieee[6]), .B1(
n4391), .Y(n2968) );
AOI21X1TS U4362 ( .A0(n3657), .A1(Data_array_SWR[35]), .B0(n1917), .Y(n2973)
);
NAND2X1TS U4363 ( .A(n3681), .B(n3022), .Y(n2972) );
OAI211X1TS U4364 ( .A0(n2974), .A1(n2323), .B0(n2973), .C0(n2972), .Y(n3043)
);
AOI22X1TS U4365 ( .A0(n3049), .A1(n3043), .B0(final_result_ieee[22]), .B1(
n3044), .Y(n2975) );
NAND2X1TS U4366 ( .A(n3652), .B(Data_array_SWR[34]), .Y(n2980) );
NAND2X1TS U4367 ( .A(n2976), .B(n1944), .Y(n2979) );
NAND2X1TS U4368 ( .A(n2869), .B(Data_array_SWR[31]), .Y(n2978) );
NAND2X1TS U4369 ( .A(n2982), .B(Data_array_SWR[27]), .Y(n2977) );
NAND4X1TS U4370 ( .A(n2980), .B(n2979), .C(n2978), .D(n2977), .Y(n4299) );
INVX2TS U4371 ( .A(n4299), .Y(n2992) );
NAND2X1TS U4372 ( .A(n3652), .B(Data_array_SWR[50]), .Y(n2985) );
NAND2X1TS U4373 ( .A(n3651), .B(Data_array_SWR[46]), .Y(n2984) );
NAND2X1TS U4374 ( .A(n2982), .B(n1946), .Y(n2983) );
NAND4X1TS U4375 ( .A(n2986), .B(n2985), .C(n2984), .D(n2983), .Y(n4297) );
NAND2X1TS U4376 ( .A(n1923), .B(Data_array_SWR[11]), .Y(n2987) );
AOI21X1TS U4377 ( .A0(n3023), .A1(n4297), .B0(n2989), .Y(n2991) );
AOI22X1TS U4378 ( .A0(n1934), .A1(Data_array_SWR[23]), .B0(n1922), .B1(
Data_array_SWR[19]), .Y(n2990) );
OAI211X1TS U4379 ( .A0(n2992), .A1(n3659), .B0(n2991), .C0(n2990), .Y(n3019)
);
INVX2TS U4380 ( .A(n3019), .Y(n3627) );
INVX2TS U4381 ( .A(n3628), .Y(n2993) );
AOI22X1TS U4382 ( .A0(n3045), .A1(n2993), .B0(final_result_ieee[41]), .B1(
n3044), .Y(n2994) );
AOI21X1TS U4383 ( .A0(n1934), .A1(Data_array_SWR[36]), .B0(n1917), .Y(n2996)
);
NAND2X1TS U4384 ( .A(n3672), .B(n4296), .Y(n2995) );
OAI211X1TS U4385 ( .A0(n2997), .A1(n2323), .B0(n2996), .C0(n2995), .Y(n3014)
);
INVX2TS U4386 ( .A(n3014), .Y(n3622) );
INVX2TS U4387 ( .A(n3623), .Y(n3001) );
AOI22X1TS U4388 ( .A0(n3045), .A1(n3001), .B0(final_result_ieee[27]), .B1(
n3044), .Y(n3002) );
AOI22X1TS U4389 ( .A0(n3049), .A1(n3003), .B0(final_result_ieee[5]), .B1(
n4391), .Y(n3004) );
NAND2X1TS U4390 ( .A(n1921), .B(Data_array_SWR[18]), .Y(n3007) );
AOI21X1TS U4391 ( .A0(n3664), .A1(n3676), .B0(n3009), .Y(n3011) );
AOI22X1TS U4392 ( .A0(Data_array_SWR[14]), .A1(n1920), .B0(n1924), .B1(
Data_array_SWR[10]), .Y(n3010) );
OAI211X1TS U4393 ( .A0(n3012), .A1(n2398), .B0(n3011), .C0(n3010), .Y(n3040)
);
AOI22X1TS U4394 ( .A0(n3049), .A1(n3040), .B0(final_result_ieee[8]), .B1(
n4391), .Y(n3013) );
AOI22X1TS U4395 ( .A0(n3045), .A1(n3014), .B0(final_result_ieee[23]), .B1(
n3044), .Y(n3015) );
INVX2TS U4396 ( .A(n3016), .Y(n3625) );
INVX2TS U4397 ( .A(n3626), .Y(n3017) );
AOI22X1TS U4398 ( .A0(n3045), .A1(n3017), .B0(final_result_ieee[29]), .B1(
n3044), .Y(n3018) );
AOI22X1TS U4399 ( .A0(n3049), .A1(n3019), .B0(final_result_ieee[9]), .B1(
n4391), .Y(n3020) );
INVX2TS U4400 ( .A(n3021), .Y(n3026) );
AOI22X1TS U4401 ( .A0(n3027), .A1(n3023), .B0(n3022), .B1(n3030), .Y(n3025)
);
OAI211X1TS U4402 ( .A0(n3026), .A1(n2323), .B0(n3025), .C0(n3024), .Y(n3037)
);
INVX2TS U4403 ( .A(n3037), .Y(n3629) );
INVX2TS U4404 ( .A(n3027), .Y(n3028) );
INVX2TS U4405 ( .A(n3630), .Y(n3031) );
AOI22X1TS U4406 ( .A0(n3045), .A1(n3031), .B0(final_result_ieee[33]), .B1(
n3044), .Y(n3032) );
AOI22X1TS U4407 ( .A0(n3045), .A1(n3033), .B0(final_result_ieee[24]), .B1(
n3044), .Y(n3034) );
AOI22X1TS U4408 ( .A0(n3049), .A1(n3035), .B0(final_result_ieee[1]), .B1(
n4391), .Y(n3036) );
AOI22X1TS U4409 ( .A0(n3049), .A1(n3037), .B0(final_result_ieee[17]), .B1(
n4391), .Y(n3038) );
INVX2TS U4410 ( .A(n3040), .Y(n3638) );
INVX2TS U4411 ( .A(n3639), .Y(n3041) );
AOI22X1TS U4412 ( .A0(n3045), .A1(n3041), .B0(final_result_ieee[42]), .B1(
n3697), .Y(n3042) );
INVX2TS U4413 ( .A(n3043), .Y(n3621) );
AOI22X1TS U4414 ( .A0(n3045), .A1(n1900), .B0(final_result_ieee[28]), .B1(
n3044), .Y(n3046) );
AOI22X1TS U4415 ( .A0(n3049), .A1(n3048), .B0(final_result_ieee[0]), .B1(
n3697), .Y(n3050) );
AOI22X1TS U4416 ( .A0(intDX_EWSW[33]), .A1(n3113), .B0(DMP_EXP_EWSW[33]),
.B1(n3119), .Y(n3052) );
AOI22X1TS U4417 ( .A0(intDX_EWSW[43]), .A1(n3122), .B0(DMP_EXP_EWSW[43]),
.B1(n3147), .Y(n3053) );
AOI22X1TS U4418 ( .A0(intDX_EWSW[35]), .A1(n3122), .B0(DMP_EXP_EWSW[35]),
.B1(n3106), .Y(n3054) );
AOI22X1TS U4419 ( .A0(intDX_EWSW[45]), .A1(n3122), .B0(DMP_EXP_EWSW[45]),
.B1(n3119), .Y(n3055) );
AOI22X1TS U4420 ( .A0(intDX_EWSW[12]), .A1(n3066), .B0(DmP_EXP_EWSW[12]),
.B1(n3125), .Y(n3056) );
AOI222X1TS U4421 ( .A0(n3057), .A1(intDX_EWSW[52]), .B0(DMP_EXP_EWSW[52]),
.B1(n4432), .C0(intDY_EWSW[52]), .C1(n3148), .Y(n3058) );
INVX2TS U4422 ( .A(n3058), .Y(n1623) );
AOI22X1TS U4423 ( .A0(intDX_EWSW[20]), .A1(n3066), .B0(DmP_EXP_EWSW[20]),
.B1(n2310), .Y(n3059) );
AOI22X1TS U4424 ( .A0(intDX_EWSW[9]), .A1(n3126), .B0(DmP_EXP_EWSW[9]), .B1(
n3125), .Y(n3060) );
AOI22X1TS U4425 ( .A0(intDX_EWSW[21]), .A1(n3066), .B0(DmP_EXP_EWSW[21]),
.B1(n2907), .Y(n3061) );
AOI22X1TS U4426 ( .A0(intDX_EWSW[13]), .A1(n3066), .B0(DmP_EXP_EWSW[13]),
.B1(n3125), .Y(n3062) );
AOI22X1TS U4427 ( .A0(intDX_EWSW[19]), .A1(n3066), .B0(DmP_EXP_EWSW[19]),
.B1(n2928), .Y(n3063) );
AOI22X1TS U4428 ( .A0(intDX_EWSW[10]), .A1(n3126), .B0(DmP_EXP_EWSW[10]),
.B1(n3125), .Y(n3064) );
AOI22X1TS U4429 ( .A0(intDX_EWSW[6]), .A1(n3126), .B0(DmP_EXP_EWSW[6]), .B1(
n3125), .Y(n3065) );
AOI22X1TS U4430 ( .A0(intDX_EWSW[16]), .A1(n3066), .B0(DmP_EXP_EWSW[16]),
.B1(n2310), .Y(n3067) );
AOI22X1TS U4431 ( .A0(intDX_EWSW[2]), .A1(n3148), .B0(DmP_EXP_EWSW[2]), .B1(
n3547), .Y(n3069) );
AOI22X1TS U4432 ( .A0(intDX_EWSW[30]), .A1(n3078), .B0(DmP_EXP_EWSW[30]),
.B1(n3077), .Y(n3070) );
AOI22X1TS U4433 ( .A0(intDX_EWSW[28]), .A1(n3078), .B0(DmP_EXP_EWSW[28]),
.B1(n3077), .Y(n3071) );
AOI22X1TS U4434 ( .A0(intDX_EWSW[22]), .A1(n3078), .B0(DmP_EXP_EWSW[22]),
.B1(n2310), .Y(n3072) );
AOI22X1TS U4435 ( .A0(intDX_EWSW[24]), .A1(n3078), .B0(DmP_EXP_EWSW[24]),
.B1(n3077), .Y(n3073) );
AOI22X1TS U4436 ( .A0(intDX_EWSW[32]), .A1(n3087), .B0(DmP_EXP_EWSW[32]),
.B1(n3077), .Y(n3074) );
AOI22X1TS U4437 ( .A0(intDX_EWSW[4]), .A1(n3126), .B0(DmP_EXP_EWSW[4]), .B1(
n3125), .Y(n3075) );
AOI22X1TS U4438 ( .A0(intDX_EWSW[34]), .A1(n3087), .B0(DmP_EXP_EWSW[34]),
.B1(n3086), .Y(n3076) );
AOI22X1TS U4439 ( .A0(intDX_EWSW[27]), .A1(n3078), .B0(DmP_EXP_EWSW[27]),
.B1(n3077), .Y(n3079) );
AOI22X1TS U4440 ( .A0(intDX_EWSW[42]), .A1(n3090), .B0(DmP_EXP_EWSW[42]),
.B1(n3086), .Y(n3081) );
AOI22X1TS U4441 ( .A0(intDX_EWSW[41]), .A1(n3087), .B0(DmP_EXP_EWSW[41]),
.B1(n3086), .Y(n3082) );
AOI22X1TS U4442 ( .A0(intDX_EWSW[40]), .A1(n3087), .B0(DmP_EXP_EWSW[40]),
.B1(n3086), .Y(n3083) );
AOI22X1TS U4443 ( .A0(intDX_EWSW[48]), .A1(n3090), .B0(DmP_EXP_EWSW[48]),
.B1(n4397), .Y(n3084) );
AOI22X1TS U4444 ( .A0(intDX_EWSW[37]), .A1(n3087), .B0(DmP_EXP_EWSW[37]),
.B1(n3086), .Y(n3085) );
AOI22X1TS U4445 ( .A0(intDX_EWSW[38]), .A1(n3087), .B0(DmP_EXP_EWSW[38]),
.B1(n3086), .Y(n3088) );
AOI22X1TS U4446 ( .A0(intDX_EWSW[44]), .A1(n3090), .B0(DmP_EXP_EWSW[44]),
.B1(n4397), .Y(n3091) );
AOI22X1TS U4447 ( .A0(intDX_EWSW[12]), .A1(n2892), .B0(DMP_EXP_EWSW[12]),
.B1(n3110), .Y(n3093) );
AOI22X1TS U4448 ( .A0(intDX_EWSW[30]), .A1(n3113), .B0(DMP_EXP_EWSW[30]),
.B1(n3106), .Y(n3094) );
AOI22X1TS U4449 ( .A0(intDX_EWSW[28]), .A1(n3113), .B0(DMP_EXP_EWSW[28]),
.B1(n3106), .Y(n3095) );
AOI22X1TS U4450 ( .A0(intDX_EWSW[20]), .A1(n2892), .B0(DMP_EXP_EWSW[20]),
.B1(n3115), .Y(n3096) );
AOI22X1TS U4451 ( .A0(intDX_EWSW[22]), .A1(n2931), .B0(DMP_EXP_EWSW[22]),
.B1(n3115), .Y(n3097) );
AOI22X1TS U4452 ( .A0(intDX_EWSW[24]), .A1(n2931), .B0(DMP_EXP_EWSW[24]),
.B1(n3106), .Y(n3098) );
AOI22X1TS U4453 ( .A0(intDX_EWSW[9]), .A1(n2931), .B0(DMP_EXP_EWSW[9]), .B1(
n3110), .Y(n3099) );
AOI22X1TS U4454 ( .A0(intDX_EWSW[32]), .A1(n3113), .B0(DMP_EXP_EWSW[32]),
.B1(n3106), .Y(n3100) );
AOI22X1TS U4455 ( .A0(intDX_EWSW[34]), .A1(n3113), .B0(DMP_EXP_EWSW[34]),
.B1(n3119), .Y(n3101) );
AOI22X1TS U4456 ( .A0(intDX_EWSW[29]), .A1(n3113), .B0(DMP_EXP_EWSW[29]),
.B1(n3106), .Y(n3102) );
AOI22X1TS U4457 ( .A0(intDX_EWSW[13]), .A1(n2892), .B0(DMP_EXP_EWSW[13]),
.B1(n3115), .Y(n3103) );
AOI22X1TS U4458 ( .A0(intDX_EWSW[21]), .A1(n2896), .B0(DMP_EXP_EWSW[21]),
.B1(n3115), .Y(n3105) );
AOI22X1TS U4459 ( .A0(intDX_EWSW[27]), .A1(n3113), .B0(DMP_EXP_EWSW[27]),
.B1(n3106), .Y(n3107) );
AOI22X1TS U4460 ( .A0(intDX_EWSW[19]), .A1(n2896), .B0(DMP_EXP_EWSW[19]),
.B1(n3115), .Y(n3108) );
AOI22X1TS U4461 ( .A0(intDX_EWSW[42]), .A1(n3122), .B0(DMP_EXP_EWSW[42]),
.B1(n3119), .Y(n3109) );
AOI22X1TS U4462 ( .A0(intDX_EWSW[10]), .A1(n2892), .B0(DMP_EXP_EWSW[10]),
.B1(n3110), .Y(n3111) );
AOI22X1TS U4463 ( .A0(intDX_EWSW[41]), .A1(n3122), .B0(DMP_EXP_EWSW[41]),
.B1(n3119), .Y(n3112) );
AOI22X1TS U4464 ( .A0(intDX_EWSW[40]), .A1(n3113), .B0(DMP_EXP_EWSW[40]),
.B1(n3119), .Y(n3114) );
AOI22X1TS U4465 ( .A0(intDX_EWSW[16]), .A1(n2896), .B0(DMP_EXP_EWSW[16]),
.B1(n3115), .Y(n3116) );
AOI22X1TS U4466 ( .A0(intDX_EWSW[37]), .A1(n3122), .B0(DMP_EXP_EWSW[37]),
.B1(n3119), .Y(n3118) );
AOI22X1TS U4467 ( .A0(intDX_EWSW[38]), .A1(n3122), .B0(DMP_EXP_EWSW[38]),
.B1(n3119), .Y(n3120) );
AOI22X1TS U4468 ( .A0(intDX_EWSW[44]), .A1(n3122), .B0(DMP_EXP_EWSW[44]),
.B1(n3147), .Y(n3123) );
AOI22X1TS U4469 ( .A0(intDX_EWSW[5]), .A1(n3126), .B0(DmP_EXP_EWSW[5]), .B1(
n3125), .Y(n3124) );
AOI22X1TS U4470 ( .A0(intDX_EWSW[7]), .A1(n3126), .B0(DmP_EXP_EWSW[7]), .B1(
n3125), .Y(n3127) );
INVX2TS U4471 ( .A(n3129), .Y(n3131) );
NAND2X1TS U4472 ( .A(n3131), .B(n3130), .Y(n3134) );
INVX2TS U4473 ( .A(n3134), .Y(n3132) );
XOR2X1TS U4474 ( .A(n3135), .B(n3134), .Y(n3136) );
BUFX3TS U4475 ( .A(n4174), .Y(n3911) );
AOI22X1TS U4476 ( .A0(n3136), .A1(n3911), .B0(Raw_mant_NRM_SWR[53]), .B1(
n3747), .Y(n3137) );
AOI22X1TS U4477 ( .A0(intDX_EWSW[50]), .A1(n3144), .B0(DMP_EXP_EWSW[50]),
.B1(n3147), .Y(n3139) );
AOI22X1TS U4478 ( .A0(intDX_EWSW[0]), .A1(n3144), .B0(DMP_EXP_EWSW[0]), .B1(
n4432), .Y(n3140) );
AOI22X1TS U4479 ( .A0(intDX_EWSW[46]), .A1(n3144), .B0(DMP_EXP_EWSW[46]),
.B1(n3147), .Y(n3141) );
AOI22X1TS U4480 ( .A0(intDX_EWSW[48]), .A1(n3144), .B0(DMP_EXP_EWSW[48]),
.B1(n3147), .Y(n3142) );
AOI22X1TS U4481 ( .A0(intDX_EWSW[47]), .A1(n3144), .B0(DMP_EXP_EWSW[47]),
.B1(n3147), .Y(n3143) );
AOI22X1TS U4482 ( .A0(intDX_EWSW[51]), .A1(n3144), .B0(DMP_EXP_EWSW[51]),
.B1(n3147), .Y(n3145) );
AOI22X1TS U4483 ( .A0(intDY_EWSW[58]), .A1(n3148), .B0(DMP_EXP_EWSW[58]),
.B1(n3147), .Y(n3149) );
OAI22X1TS U4484 ( .A0(n3201), .A1(n4483), .B0(n4369), .B1(n4662), .Y(n3151)
);
INVX2TS U4485 ( .A(n3357), .Y(n3374) );
INVX2TS U4486 ( .A(n1995), .Y(n3584) );
OAI22X1TS U4487 ( .A0(n3201), .A1(n4533), .B0(n4369), .B1(n4663), .Y(n3153)
);
NOR2X1TS U4488 ( .A(n3365), .B(n4617), .Y(n3152) );
OA22X1TS U4489 ( .A0(n3584), .A1(n3232), .B0(n3233), .B1(n3558), .Y(n3155)
);
OAI211X1TS U4490 ( .A0(n3294), .A1(n3616), .B0(n3155), .C0(n3154), .Y(n1700)
);
OA22X1TS U4491 ( .A0(n3584), .A1(n3233), .B0(n3156), .B1(n3558), .Y(n3160)
);
OAI211X1TS U4492 ( .A0(n3232), .A1(n3616), .B0(n3160), .C0(n3159), .Y(n1699)
);
NAND2X1TS U4493 ( .A(n3380), .B(Raw_mant_NRM_SWR[26]), .Y(n3162) );
NAND2X1TS U4494 ( .A(n4374), .B(DmP_mant_SHT1_SW[26]), .Y(n3161) );
NAND3X1TS U4495 ( .A(n3163), .B(n3162), .C(n3161), .Y(n3596) );
INVX2TS U4496 ( .A(n3164), .Y(n3599) );
NAND2X1TS U4497 ( .A(n3361), .B(Raw_mant_NRM_SWR[25]), .Y(n3166) );
NAND2X1TS U4498 ( .A(n3382), .B(DmP_mant_SHT1_SW[27]), .Y(n3165) );
AOI22X1TS U4499 ( .A0(n1995), .A1(n3608), .B0(Data_array_SWR[27]), .B1(n3448), .Y(n3172) );
BUFX3TS U4500 ( .A(n3590), .Y(n3580) );
INVX2TS U4501 ( .A(n3201), .Y(n3375) );
NAND2X1TS U4502 ( .A(n3375), .B(Raw_mant_NRM_SWR[24]), .Y(n3170) );
NAND2X1TS U4503 ( .A(n3381), .B(Raw_mant_NRM_SWR[30]), .Y(n3169) );
NAND2X1TS U4504 ( .A(n3382), .B(DmP_mant_SHT1_SW[28]), .Y(n3168) );
INVX2TS U4505 ( .A(n3391), .Y(n3612) );
NAND2X1TS U4506 ( .A(n3580), .B(n3612), .Y(n3171) );
AOI22X1TS U4507 ( .A0(n3380), .A1(Raw_mant_NRM_SWR[28]), .B0(
DmP_mant_SHT1_SW[24]), .B1(n3382), .Y(n3173) );
BUFX3TS U4508 ( .A(n3551), .Y(n3441) );
NAND2X1TS U4509 ( .A(n3375), .B(Raw_mant_NRM_SWR[30]), .Y(n3178) );
NAND2X1TS U4510 ( .A(n3382), .B(DmP_mant_SHT1_SW[22]), .Y(n3177) );
AOI22X1TS U4511 ( .A0(n3441), .A1(n3589), .B0(Data_array_SWR[24]), .B1(n3425), .Y(n3184) );
NAND2X1TS U4512 ( .A(n3430), .B(Raw_mant_NRM_SWR[29]), .Y(n3181) );
NAND2X1TS U4513 ( .A(n3431), .B(DmP_mant_SHT1_SW[23]), .Y(n3180) );
NAND2X1TS U4514 ( .A(n3613), .B(n3552), .Y(n3183) );
OAI211X1TS U4515 ( .A0(n3600), .A1(n3555), .B0(n3184), .C0(n3183), .Y(n1722)
);
NAND2X1TS U4516 ( .A(n3430), .B(Raw_mant_NRM_SWR[4]), .Y(n3186) );
NAND2X1TS U4517 ( .A(n3696), .B(DmP_mant_SHT1_SW[48]), .Y(n3185) );
INVX2TS U4518 ( .A(n3256), .Y(n3199) );
NAND2X1TS U4519 ( .A(n3361), .B(Raw_mant_NRM_SWR[3]), .Y(n3189) );
NAND2X1TS U4520 ( .A(n3696), .B(DmP_mant_SHT1_SW[49]), .Y(n3188) );
BUFX3TS U4521 ( .A(n3588), .Y(n3423) );
NAND2X1TS U4522 ( .A(n3430), .B(Raw_mant_NRM_SWR[5]), .Y(n3192) );
NAND2X1TS U4523 ( .A(n3696), .B(DmP_mant_SHT1_SW[47]), .Y(n3191) );
AOI22X1TS U4524 ( .A0(n3580), .A1(n3340), .B0(n3423), .B1(n3396), .Y(n3198)
);
NAND2X1TS U4525 ( .A(n3380), .B(Raw_mant_NRM_SWR[6]), .Y(n3196) );
NAND2X1TS U4526 ( .A(n3357), .B(Raw_mant_NRM_SWR[48]), .Y(n3195) );
NAND2X1TS U4527 ( .A(n3323), .B(DmP_mant_SHT1_SW[46]), .Y(n3194) );
INVX2TS U4528 ( .A(n3400), .Y(n3200) );
AOI22X1TS U4529 ( .A0(n3441), .A1(n3200), .B0(Data_array_SWR[47]), .B1(n3439), .Y(n3197) );
INVX2TS U4530 ( .A(n3396), .Y(n3207) );
BUFX3TS U4531 ( .A(n3590), .Y(n3467) );
BUFX3TS U4532 ( .A(n3588), .Y(n3445) );
AOI22X1TS U4533 ( .A0(n3467), .A1(n3256), .B0(n3445), .B1(n3200), .Y(n3206)
);
BUFX3TS U4534 ( .A(n3551), .Y(n3470) );
INVX2TS U4535 ( .A(n3201), .Y(n3308) );
NAND2X1TS U4536 ( .A(n2785), .B(Raw_mant_NRM_SWR[7]), .Y(n3204) );
NAND2X1TS U4537 ( .A(n3357), .B(Raw_mant_NRM_SWR[47]), .Y(n3203) );
NAND2X1TS U4538 ( .A(n3376), .B(DmP_mant_SHT1_SW[45]), .Y(n3202) );
INVX2TS U4539 ( .A(n3403), .Y(n3395) );
AOI22X1TS U4540 ( .A0(n3470), .A1(n3395), .B0(Data_array_SWR[46]), .B1(n3448), .Y(n3205) );
OAI211X1TS U4541 ( .A0(n3207), .A1(n3459), .B0(n3206), .C0(n3205), .Y(n1745)
);
NAND2X1TS U4542 ( .A(n3361), .B(Raw_mant_NRM_SWR[17]), .Y(n3209) );
NAND2X1TS U4543 ( .A(n3376), .B(DmP_mant_SHT1_SW[35]), .Y(n3208) );
INVX2TS U4544 ( .A(n3352), .Y(n3222) );
NAND2X1TS U4545 ( .A(n3380), .B(Raw_mant_NRM_SWR[16]), .Y(n3213) );
NAND2X1TS U4546 ( .A(n3322), .B(Raw_mant_NRM_SWR[38]), .Y(n3212) );
NAND2X1TS U4547 ( .A(n3323), .B(DmP_mant_SHT1_SW[36]), .Y(n3211) );
INVX2TS U4548 ( .A(n3263), .Y(n3469) );
NAND2X1TS U4549 ( .A(n3430), .B(Raw_mant_NRM_SWR[18]), .Y(n3216) );
NAND2X1TS U4550 ( .A(n3381), .B(Raw_mant_NRM_SWR[36]), .Y(n3215) );
NAND2X1TS U4551 ( .A(n3376), .B(DmP_mant_SHT1_SW[34]), .Y(n3214) );
INVX2TS U4552 ( .A(n3356), .Y(n3226) );
AOI22X1TS U4553 ( .A0(n3467), .A1(n3469), .B0(n3445), .B1(n3226), .Y(n3221)
);
BUFX3TS U4554 ( .A(n3551), .Y(n3449) );
NAND2X1TS U4555 ( .A(n3380), .B(Raw_mant_NRM_SWR[19]), .Y(n3219) );
NAND2X1TS U4556 ( .A(n3322), .B(Raw_mant_NRM_SWR[35]), .Y(n3218) );
NAND2X1TS U4557 ( .A(n3323), .B(DmP_mant_SHT1_SW[33]), .Y(n3217) );
INVX2TS U4558 ( .A(n3332), .Y(n3351) );
AOI22X1TS U4559 ( .A0(n3449), .A1(n3351), .B0(Data_array_SWR[34]), .B1(n3448), .Y(n3220) );
BUFX3TS U4560 ( .A(n3590), .Y(n3447) );
NAND2X1TS U4561 ( .A(n3308), .B(Raw_mant_NRM_SWR[15]), .Y(n3224) );
NAND2X1TS U4562 ( .A(n3323), .B(DmP_mant_SHT1_SW[37]), .Y(n3223) );
AOI22X1TS U4563 ( .A0(n3447), .A1(n3464), .B0(n3423), .B1(n3352), .Y(n3228)
);
AOI22X1TS U4564 ( .A0(n3449), .A1(n3226), .B0(Data_array_SWR[35]), .B1(n3425), .Y(n3227) );
OAI211X1TS U4565 ( .A0(n3263), .A1(n3418), .B0(n3228), .C0(n3227), .Y(n1734)
);
NAND2X1TS U4566 ( .A(n3308), .B(Raw_mant_NRM_SWR[48]), .Y(n3231) );
NAND2X1TS U4567 ( .A(n3322), .B(Raw_mant_NRM_SWR[6]), .Y(n3230) );
NAND2X1TS U4568 ( .A(n3323), .B(DmP_mant_SHT1_SW[4]), .Y(n3229) );
INVX2TS U4569 ( .A(n3559), .Y(n3285) );
INVX2TS U4570 ( .A(n3232), .Y(n3295) );
AOI22X1TS U4571 ( .A0(n3447), .A1(n3285), .B0(n3423), .B1(n3295), .Y(n3236)
);
INVX2TS U4572 ( .A(n3233), .Y(n3234) );
AOI22X1TS U4573 ( .A0(n3449), .A1(n3234), .B0(Data_array_SWR[3]), .B1(n3425),
.Y(n3235) );
NAND2X1TS U4574 ( .A(n3308), .B(Raw_mant_NRM_SWR[37]), .Y(n3238) );
NAND2X1TS U4575 ( .A(n3382), .B(DmP_mant_SHT1_SW[15]), .Y(n3237) );
INVX2TS U4576 ( .A(n3581), .Y(n3251) );
NAND2X1TS U4577 ( .A(n3361), .B(Raw_mant_NRM_SWR[36]), .Y(n3241) );
NAND2X1TS U4578 ( .A(n4374), .B(DmP_mant_SHT1_SW[16]), .Y(n3240) );
NAND2X1TS U4579 ( .A(n2785), .B(Raw_mant_NRM_SWR[38]), .Y(n3244) );
NAND2X1TS U4580 ( .A(n3431), .B(DmP_mant_SHT1_SW[14]), .Y(n3243) );
AOI22X1TS U4581 ( .A0(n3447), .A1(n3578), .B0(n3423), .B1(n3573), .Y(n3250)
);
NAND2X1TS U4582 ( .A(n3308), .B(Raw_mant_NRM_SWR[39]), .Y(n3247) );
NAND2X1TS U4583 ( .A(n3376), .B(DmP_mant_SHT1_SW[13]), .Y(n3246) );
AOI22X1TS U4584 ( .A0(n3449), .A1(n3571), .B0(Data_array_SWR[15]), .B1(n3425), .Y(n3249) );
OAI211X1TS U4585 ( .A0(n3251), .A1(n3418), .B0(n3250), .C0(n3249), .Y(n1713)
);
INVX2TS U4586 ( .A(n3338), .Y(n3255) );
AOI22X1TS U4587 ( .A0(n3467), .A1(n3252), .B0(n3445), .B1(n3340), .Y(n3254)
);
AOI22X1TS U4588 ( .A0(n3470), .A1(n3256), .B0(Data_array_SWR[49]), .B1(n3468), .Y(n3253) );
OAI211X1TS U4589 ( .A0(n3255), .A1(n3459), .B0(n3254), .C0(n3253), .Y(n1748)
);
INVX2TS U4590 ( .A(n3340), .Y(n3259) );
BUFX3TS U4591 ( .A(n3590), .Y(n3603) );
AOI22X1TS U4592 ( .A0(n3603), .A1(n3338), .B0(n3588), .B1(n3256), .Y(n3258)
);
AOI22X1TS U4593 ( .A0(n3435), .A1(n3396), .B0(Data_array_SWR[48]), .B1(n3604), .Y(n3257) );
OAI211X1TS U4594 ( .A0(n3259), .A1(n3607), .B0(n3258), .C0(n3257), .Y(n1747)
);
INVX2TS U4595 ( .A(n3464), .Y(n3266) );
INVX2TS U4596 ( .A(n1995), .Y(n3594) );
NAND2X1TS U4597 ( .A(n2785), .B(Raw_mant_NRM_SWR[14]), .Y(n3262) );
NAND2X1TS U4598 ( .A(n3322), .B(Raw_mant_NRM_SWR[40]), .Y(n3261) );
NAND2X1TS U4599 ( .A(n3323), .B(DmP_mant_SHT1_SW[38]), .Y(n3260) );
OA22X1TS U4600 ( .A0(n3616), .A1(n3473), .B0(n3263), .B1(n3558), .Y(n3265)
);
AOI22X1TS U4601 ( .A0(n3435), .A1(n3352), .B0(Data_array_SWR[36]), .B1(n3604), .Y(n3264) );
INVX2TS U4602 ( .A(n3589), .Y(n3275) );
NAND2X1TS U4603 ( .A(n2785), .B(Raw_mant_NRM_SWR[31]), .Y(n3268) );
NAND2X1TS U4604 ( .A(n3382), .B(DmP_mant_SHT1_SW[21]), .Y(n3267) );
AOI22X1TS U4605 ( .A0(n3603), .A1(n3552), .B0(n3465), .B1(n3586), .Y(n3274)
);
NAND2X1TS U4606 ( .A(n3308), .B(Raw_mant_NRM_SWR[32]), .Y(n3271) );
NAND2X1TS U4607 ( .A(n4374), .B(DmP_mant_SHT1_SW[20]), .Y(n3270) );
AOI22X1TS U4608 ( .A0(n3435), .A1(n3587), .B0(Data_array_SWR[22]), .B1(n3468), .Y(n3273) );
OAI211X1TS U4609 ( .A0(n3275), .A1(n3607), .B0(n3274), .C0(n3273), .Y(n1720)
);
NAND2X1TS U4610 ( .A(n3308), .B(Raw_mant_NRM_SWR[46]), .Y(n3278) );
NAND2X1TS U4611 ( .A(n3322), .B(Raw_mant_NRM_SWR[8]), .Y(n3277) );
NAND2X1TS U4612 ( .A(n3323), .B(DmP_mant_SHT1_SW[6]), .Y(n3276) );
NAND2X1TS U4613 ( .A(n2785), .B(Raw_mant_NRM_SWR[45]), .Y(n3280) );
NAND2X1TS U4614 ( .A(n3431), .B(DmP_mant_SHT1_SW[7]), .Y(n3279) );
NAND2X1TS U4615 ( .A(n3375), .B(Raw_mant_NRM_SWR[47]), .Y(n3283) );
NAND2X1TS U4616 ( .A(n3376), .B(DmP_mant_SHT1_SW[5]), .Y(n3282) );
AOI22X1TS U4617 ( .A0(n3603), .A1(n3567), .B0(n3465), .B1(n3557), .Y(n3287)
);
AOI22X1TS U4618 ( .A0(n3435), .A1(n3285), .B0(Data_array_SWR[6]), .B1(n3468),
.Y(n3286) );
INVX2TS U4619 ( .A(n3567), .Y(n3293) );
NAND2X1TS U4620 ( .A(n3375), .B(Raw_mant_NRM_SWR[44]), .Y(n3289) );
NAND2X1TS U4621 ( .A(n3431), .B(DmP_mant_SHT1_SW[8]), .Y(n3288) );
INVX2TS U4622 ( .A(n3560), .Y(n3301) );
AOI22X1TS U4623 ( .A0(n3447), .A1(n3565), .B0(n3423), .B1(n3301), .Y(n3292)
);
AOI22X1TS U4624 ( .A0(n3449), .A1(n3557), .B0(Data_array_SWR[7]), .B1(n3468),
.Y(n3291) );
OAI211X1TS U4625 ( .A0(n3293), .A1(n3418), .B0(n3292), .C0(n3291), .Y(n1705)
);
INVX2TS U4626 ( .A(n3294), .Y(n3561) );
AOI22X1TS U4627 ( .A0(n3467), .A1(n3557), .B0(n3445), .B1(n3561), .Y(n3297)
);
AOI22X1TS U4628 ( .A0(n3470), .A1(n3295), .B0(n3439), .B1(Data_array_SWR[4]),
.Y(n3296) );
INVX2TS U4629 ( .A(n3565), .Y(n3304) );
NAND2X1TS U4630 ( .A(n3375), .B(Raw_mant_NRM_SWR[43]), .Y(n3300) );
NAND2X1TS U4631 ( .A(n3322), .B(Raw_mant_NRM_SWR[11]), .Y(n3299) );
NAND2X1TS U4632 ( .A(n3323), .B(DmP_mant_SHT1_SW[9]), .Y(n3298) );
INVX2TS U4633 ( .A(n3570), .Y(n3318) );
AOI22X1TS U4634 ( .A0(n3580), .A1(n3318), .B0(n3613), .B1(n3567), .Y(n3303)
);
AOI22X1TS U4635 ( .A0(n3441), .A1(n3301), .B0(Data_array_SWR[8]), .B1(n3425),
.Y(n3302) );
NAND2X1TS U4636 ( .A(n2785), .B(Raw_mant_NRM_SWR[41]), .Y(n3306) );
NAND2X1TS U4637 ( .A(n3376), .B(DmP_mant_SHT1_SW[11]), .Y(n3305) );
INVX2TS U4638 ( .A(n3574), .Y(n3317) );
NAND2X1TS U4639 ( .A(n3375), .B(Raw_mant_NRM_SWR[40]), .Y(n3310) );
NAND2X1TS U4640 ( .A(n3431), .B(DmP_mant_SHT1_SW[12]), .Y(n3309) );
NAND2X1TS U4641 ( .A(n3375), .B(Raw_mant_NRM_SWR[42]), .Y(n3313) );
NAND2X1TS U4642 ( .A(n3376), .B(DmP_mant_SHT1_SW[10]), .Y(n3312) );
AOI22X1TS U4643 ( .A0(n3447), .A1(n3572), .B0(n3423), .B1(n3566), .Y(n3316)
);
AOI22X1TS U4644 ( .A0(n3449), .A1(n3318), .B0(Data_array_SWR[11]), .B1(n3448), .Y(n3315) );
OAI211X1TS U4645 ( .A0(n3317), .A1(n3418), .B0(n3316), .C0(n3315), .Y(n1709)
);
INVX2TS U4646 ( .A(n3566), .Y(n3321) );
AOI22X1TS U4647 ( .A0(n3603), .A1(n3574), .B0(n3465), .B1(n3318), .Y(n3320)
);
AOI22X1TS U4648 ( .A0(n3435), .A1(n3565), .B0(Data_array_SWR[10]), .B1(n3468), .Y(n3319) );
NAND2X1TS U4649 ( .A(n3380), .B(Raw_mant_NRM_SWR[20]), .Y(n3326) );
NAND2X1TS U4650 ( .A(n3322), .B(Raw_mant_NRM_SWR[34]), .Y(n3325) );
NAND2X1TS U4651 ( .A(n3376), .B(DmP_mant_SHT1_SW[32]), .Y(n3324) );
OA22X1TS U4652 ( .A0(n3616), .A1(n3356), .B0(n3344), .B1(n3558), .Y(n3331)
);
NAND2X1TS U4653 ( .A(n3361), .B(Raw_mant_NRM_SWR[21]), .Y(n3328) );
NAND2X1TS U4654 ( .A(n3376), .B(DmP_mant_SHT1_SW[31]), .Y(n3327) );
AOI22X1TS U4655 ( .A0(n3435), .A1(n3602), .B0(Data_array_SWR[33]), .B1(n3604), .Y(n3330) );
AOI22X1TS U4656 ( .A0(n3580), .A1(n3351), .B0(n3423), .B1(n3602), .Y(n3337)
);
NAND2X1TS U4657 ( .A(n3361), .B(Raw_mant_NRM_SWR[22]), .Y(n3334) );
NAND2X1TS U4658 ( .A(n3696), .B(DmP_mant_SHT1_SW[30]), .Y(n3333) );
NAND3X1TS U4659 ( .A(n3335), .B(n3334), .C(n3333), .Y(n3601) );
AOI22X1TS U4660 ( .A0(n3441), .A1(n3601), .B0(Data_array_SWR[32]), .B1(n3425), .Y(n3336) );
OAI211X1TS U4661 ( .A0(n3344), .A1(n3418), .B0(n3337), .C0(n3336), .Y(n1730)
);
AOI22X1TS U4662 ( .A0(n3467), .A1(n1930), .B0(n3445), .B1(n3338), .Y(n3342)
);
AOI22X1TS U4663 ( .A0(n3470), .A1(n3340), .B0(Data_array_SWR[50]), .B1(n3448), .Y(n3341) );
INVX2TS U4664 ( .A(n3602), .Y(n3350) );
INVX2TS U4665 ( .A(n3344), .Y(n3353) );
AOI22X1TS U4666 ( .A0(n3447), .A1(n3353), .B0(n3445), .B1(n3601), .Y(n3349)
);
NAND2X1TS U4667 ( .A(n3430), .B(Raw_mant_NRM_SWR[23]), .Y(n3346) );
NAND2X1TS U4668 ( .A(n4374), .B(DmP_mant_SHT1_SW[29]), .Y(n3345) );
AOI22X1TS U4669 ( .A0(n3449), .A1(n3610), .B0(Data_array_SWR[31]), .B1(n3448), .Y(n3348) );
OAI211X1TS U4670 ( .A0(n3350), .A1(n3418), .B0(n3349), .C0(n3348), .Y(n1729)
);
AOI22X1TS U4671 ( .A0(n3467), .A1(n3352), .B0(n3465), .B1(n3351), .Y(n3355)
);
AOI22X1TS U4672 ( .A0(n3470), .A1(n3353), .B0(n1937), .B1(n3468), .Y(n3354)
);
NAND2X1TS U4673 ( .A(n3380), .B(Raw_mant_NRM_SWR[8]), .Y(n3360) );
NAND2X1TS U4674 ( .A(n3357), .B(Raw_mant_NRM_SWR[46]), .Y(n3359) );
NAND2X1TS U4675 ( .A(n3323), .B(DmP_mant_SHT1_SW[44]), .Y(n3358) );
NAND2X1TS U4676 ( .A(n3430), .B(Raw_mant_NRM_SWR[9]), .Y(n3363) );
NAND2X1TS U4677 ( .A(n3431), .B(DmP_mant_SHT1_SW[43]), .Y(n3362) );
AOI22X1TS U4678 ( .A0(n3580), .A1(n3395), .B0(n3613), .B1(n3455), .Y(n3370)
);
NAND2X1TS U4679 ( .A(n3361), .B(Raw_mant_NRM_SWR[10]), .Y(n3367) );
NAND2X1TS U4680 ( .A(n3431), .B(DmP_mant_SHT1_SW[42]), .Y(n3366) );
AOI22X1TS U4681 ( .A0(n3441), .A1(n3453), .B0(Data_array_SWR[43]), .B1(n3439), .Y(n3369) );
NAND2X1TS U4682 ( .A(n3430), .B(Raw_mant_NRM_SWR[34]), .Y(n3372) );
NAND2X1TS U4683 ( .A(n4374), .B(DmP_mant_SHT1_SW[18]), .Y(n3371) );
INVX2TS U4684 ( .A(n3579), .Y(n3388) );
NAND2X1TS U4685 ( .A(n3308), .B(Raw_mant_NRM_SWR[33]), .Y(n3378) );
NAND2X1TS U4686 ( .A(n3431), .B(DmP_mant_SHT1_SW[19]), .Y(n3377) );
NAND2X1TS U4687 ( .A(n3380), .B(Raw_mant_NRM_SWR[35]), .Y(n3385) );
NAND2X1TS U4688 ( .A(n3381), .B(Raw_mant_NRM_SWR[19]), .Y(n3384) );
NAND2X1TS U4689 ( .A(n4374), .B(DmP_mant_SHT1_SW[17]), .Y(n3383) );
INVX2TS U4690 ( .A(n3585), .Y(n3424) );
AOI22X1TS U4691 ( .A0(n3603), .A1(n3591), .B0(n3465), .B1(n3424), .Y(n3387)
);
AOI22X1TS U4692 ( .A0(n3435), .A1(n3578), .B0(Data_array_SWR[18]), .B1(n3604), .Y(n3386) );
AOI22X1TS U4693 ( .A0(n3447), .A1(n3610), .B0(n3423), .B1(n3608), .Y(n3390)
);
AOI22X1TS U4694 ( .A0(n3441), .A1(n3596), .B0(Data_array_SWR[28]), .B1(n3425), .Y(n3389) );
INVX2TS U4695 ( .A(n3572), .Y(n3394) );
AOI22X1TS U4696 ( .A0(n3580), .A1(n3571), .B0(n3423), .B1(n3574), .Y(n3393)
);
AOI22X1TS U4697 ( .A0(n3441), .A1(n3566), .B0(Data_array_SWR[12]), .B1(n3425), .Y(n3392) );
AOI22X1TS U4698 ( .A0(n3467), .A1(n3396), .B0(n3465), .B1(n3395), .Y(n3398)
);
INVX2TS U4699 ( .A(n3399), .Y(n3446) );
AOI22X1TS U4700 ( .A0(n3470), .A1(n3446), .B0(Data_array_SWR[45]), .B1(n3468), .Y(n3397) );
OAI211X1TS U4701 ( .A0(n3400), .A1(n3459), .B0(n3398), .C0(n3397), .Y(n1744)
);
OA22X1TS U4702 ( .A0(n3616), .A1(n3400), .B0(n3399), .B1(n3558), .Y(n3402)
);
AOI22X1TS U4703 ( .A0(n3435), .A1(n3455), .B0(Data_array_SWR[44]), .B1(n3604), .Y(n3401) );
NAND2X1TS U4704 ( .A(n3430), .B(Raw_mant_NRM_SWR[13]), .Y(n3405) );
NAND2X1TS U4705 ( .A(n3431), .B(DmP_mant_SHT1_SW[39]), .Y(n3404) );
INVX2TS U4706 ( .A(n3466), .Y(n3412) );
NAND2X1TS U4707 ( .A(n3361), .B(Raw_mant_NRM_SWR[12]), .Y(n3408) );
NAND2X1TS U4708 ( .A(n3431), .B(DmP_mant_SHT1_SW[40]), .Y(n3407) );
INVX2TS U4709 ( .A(n3473), .Y(n3440) );
AOI22X1TS U4710 ( .A0(n3467), .A1(n3456), .B0(n3445), .B1(n3440), .Y(n3411)
);
AOI22X1TS U4711 ( .A0(n3470), .A1(n3464), .B0(n1944), .B1(n3448), .Y(n3410)
);
INVX2TS U4712 ( .A(n3552), .Y(n3415) );
AOI22X1TS U4713 ( .A0(n3447), .A1(n1904), .B0(n3445), .B1(n3589), .Y(n3414)
);
AOI22X1TS U4714 ( .A0(n3449), .A1(n3586), .B0(Data_array_SWR[23]), .B1(n3448), .Y(n3413) );
OAI211X1TS U4715 ( .A0(n3415), .A1(n3418), .B0(n3414), .C0(n3413), .Y(n1721)
);
INVX2TS U4716 ( .A(n3591), .Y(n3419) );
AOI22X1TS U4717 ( .A0(n3447), .A1(n3587), .B0(n3445), .B1(n3579), .Y(n3417)
);
AOI22X1TS U4718 ( .A0(n3449), .A1(n3424), .B0(Data_array_SWR[19]), .B1(n3448), .Y(n3416) );
OAI211X1TS U4719 ( .A0(n3419), .A1(n3418), .B0(n3417), .C0(n3416), .Y(n1717)
);
INVX2TS U4720 ( .A(n3587), .Y(n3422) );
AOI22X1TS U4721 ( .A0(n3580), .A1(n3586), .B0(n3613), .B1(n3591), .Y(n3421)
);
AOI22X1TS U4722 ( .A0(n3441), .A1(n3579), .B0(Data_array_SWR[20]), .B1(n3425), .Y(n3420) );
INVX2TS U4723 ( .A(n3578), .Y(n3428) );
AOI22X1TS U4724 ( .A0(n3580), .A1(n3424), .B0(n3423), .B1(n3581), .Y(n3427)
);
AOI22X1TS U4725 ( .A0(n3441), .A1(n3573), .B0(Data_array_SWR[16]), .B1(n3425), .Y(n3426) );
NAND2X1TS U4726 ( .A(n3430), .B(Raw_mant_NRM_SWR[11]), .Y(n3433) );
NAND2X1TS U4727 ( .A(n3376), .B(DmP_mant_SHT1_SW[41]), .Y(n3432) );
INVX2TS U4728 ( .A(n3454), .Y(n3438) );
AOI22X1TS U4729 ( .A0(n3603), .A1(n3453), .B0(n3588), .B1(n3456), .Y(n3437)
);
AOI22X1TS U4730 ( .A0(n3435), .A1(n3466), .B0(Data_array_SWR[40]), .B1(n3604), .Y(n3436) );
OAI211X1TS U4731 ( .A0(n3438), .A1(n3607), .B0(n3437), .C0(n3436), .Y(n1739)
);
INVX2TS U4732 ( .A(n3456), .Y(n3444) );
AOI22X1TS U4733 ( .A0(n3580), .A1(n3454), .B0(n3613), .B1(n3466), .Y(n3443)
);
AOI22X1TS U4734 ( .A0(n3441), .A1(n3440), .B0(Data_array_SWR[39]), .B1(n3439), .Y(n3442) );
INVX2TS U4735 ( .A(n3455), .Y(n3452) );
AOI22X1TS U4736 ( .A0(n3447), .A1(n3446), .B0(n3445), .B1(n3453), .Y(n3451)
);
AOI22X1TS U4737 ( .A0(n3449), .A1(n3454), .B0(n1946), .B1(n3448), .Y(n3450)
);
INVX2TS U4738 ( .A(n3453), .Y(n3460) );
AOI22X1TS U4739 ( .A0(n3467), .A1(n3455), .B0(n3465), .B1(n3454), .Y(n3458)
);
AOI22X1TS U4740 ( .A0(n3470), .A1(n3456), .B0(n1948), .B1(n3468), .Y(n3457)
);
INVX2TS U4741 ( .A(n3573), .Y(n3463) );
AOI22X1TS U4742 ( .A0(n3603), .A1(n3581), .B0(n3465), .B1(n3571), .Y(n3462)
);
AOI22X1TS U4743 ( .A0(n3470), .A1(n3572), .B0(Data_array_SWR[14]), .B1(n3468), .Y(n3461) );
OAI211X1TS U4744 ( .A0(n3463), .A1(n3607), .B0(n3462), .C0(n3461), .Y(n1712)
);
AOI22X1TS U4745 ( .A0(n3467), .A1(n3466), .B0(n3465), .B1(n3464), .Y(n3472)
);
AOI22X1TS U4746 ( .A0(n3470), .A1(n3469), .B0(Data_array_SWR[37]), .B1(n3468), .Y(n3471) );
OAI211X1TS U4747 ( .A0(n3473), .A1(n3607), .B0(n3472), .C0(n3471), .Y(n1736)
);
AOI22X1TS U4748 ( .A0(n4516), .A1(intDX_EWSW[11]), .B0(n4581), .B1(
intDX_EWSW[50]), .Y(n3474) );
AOI221X1TS U4749 ( .A0(intDY_EWSW[49]), .A1(n4584), .B0(n4517), .B1(
intDX_EWSW[49]), .C0(n3475), .Y(n3489) );
OAI22X1TS U4750 ( .A0(n1987), .A1(intDX_EWSW[53]), .B0(n4482), .B1(
intDX_EWSW[54]), .Y(n3476) );
AOI221X1TS U4751 ( .A0(n1987), .A1(intDX_EWSW[53]), .B0(intDX_EWSW[54]),
.B1(n4482), .C0(n3476), .Y(n3488) );
OAI22X1TS U4752 ( .A0(n4603), .A1(intDX_EWSW[51]), .B0(n4518), .B1(
intDX_EWSW[52]), .Y(n3477) );
AOI22X1TS U4753 ( .A0(n4582), .A1(intDY_EWSW[58]), .B0(n4503), .B1(
intDX_EWSW[57]), .Y(n3478) );
AOI22X1TS U4754 ( .A0(n1988), .A1(intDX_EWSW[56]), .B0(n4481), .B1(
intDX_EWSW[55]), .Y(n3479) );
OAI221XLTS U4755 ( .A0(n1988), .A1(intDX_EWSW[56]), .B0(n4481), .B1(
intDX_EWSW[55]), .C0(n3479), .Y(n3484) );
AOI22X1TS U4756 ( .A0(n4504), .A1(intDY_EWSW[62]), .B0(n4568), .B1(
intDY_EWSW[61]), .Y(n3480) );
AOI22X1TS U4757 ( .A0(n4583), .A1(intDY_EWSW[60]), .B0(n4524), .B1(
intDY_EWSW[59]), .Y(n3481) );
NOR4X1TS U4758 ( .A(n3485), .B(n3484), .C(n3483), .D(n3482), .Y(n3486) );
OAI22X1TS U4759 ( .A0(n4600), .A1(intDX_EWSW[42]), .B0(n4515), .B1(
intDX_EWSW[43]), .Y(n3490) );
OAI22X1TS U4760 ( .A0(n4599), .A1(intDX_EWSW[40]), .B0(n4514), .B1(
intDX_EWSW[41]), .Y(n3491) );
AOI221X1TS U4761 ( .A0(n4599), .A1(intDX_EWSW[40]), .B0(intDX_EWSW[41]),
.B1(n4514), .C0(n3491), .Y(n3496) );
OAI22X1TS U4762 ( .A0(n4602), .A1(intDX_EWSW[46]), .B0(n4528), .B1(
intDX_EWSW[47]), .Y(n3492) );
OAI22X1TS U4763 ( .A0(n4601), .A1(intDX_EWSW[44]), .B0(n4527), .B1(
intDX_EWSW[45]), .Y(n3493) );
OAI22X1TS U4764 ( .A0(n4597), .A1(intDX_EWSW[34]), .B0(n4513), .B1(
intDX_EWSW[35]), .Y(n3498) );
OAI22X1TS U4765 ( .A0(n4595), .A1(intDX_EWSW[1]), .B0(n4512), .B1(
intDX_EWSW[33]), .Y(n3499) );
OAI22X1TS U4766 ( .A0(n4596), .A1(intDX_EWSW[38]), .B0(n4526), .B1(
intDX_EWSW[39]), .Y(n3500) );
AOI221X1TS U4767 ( .A0(n4596), .A1(intDX_EWSW[38]), .B0(intDX_EWSW[39]),
.B1(n4526), .C0(n3500), .Y(n3503) );
OAI22X1TS U4768 ( .A0(n4598), .A1(intDX_EWSW[36]), .B0(n4525), .B1(
intDX_EWSW[37]), .Y(n3501) );
AOI22X1TS U4769 ( .A0(n4502), .A1(intDX_EWSW[31]), .B0(n4564), .B1(
intDX_EWSW[30]), .Y(n3506) );
AOI22X1TS U4770 ( .A0(n4501), .A1(intDX_EWSW[29]), .B0(n4559), .B1(
intDX_EWSW[20]), .Y(n3507) );
AOI22X1TS U4771 ( .A0(n4495), .A1(intDX_EWSW[27]), .B0(n4562), .B1(
intDX_EWSW[26]), .Y(n3508) );
AOI22X1TS U4772 ( .A0(n4494), .A1(intDX_EWSW[25]), .B0(n4565), .B1(
intDX_EWSW[32]), .Y(n3509) );
NOR4X1TS U4773 ( .A(n3513), .B(n3512), .C(n3511), .D(n3510), .Y(n3541) );
AOI22X1TS U4774 ( .A0(n4500), .A1(intDX_EWSW[23]), .B0(n4560), .B1(
intDX_EWSW[22]), .Y(n3514) );
AOI22X1TS U4775 ( .A0(n4499), .A1(intDX_EWSW[21]), .B0(n4566), .B1(
intDX_EWSW[48]), .Y(n3515) );
AOI22X1TS U4776 ( .A0(n4493), .A1(intDX_EWSW[19]), .B0(n4558), .B1(
intDX_EWSW[18]), .Y(n3516) );
AOI22X1TS U4777 ( .A0(n4492), .A1(intDX_EWSW[17]), .B0(n4561), .B1(
intDX_EWSW[24]), .Y(n3517) );
NOR4X1TS U4778 ( .A(n3521), .B(n3520), .C(n3519), .D(n3518), .Y(n3540) );
AOI22X1TS U4779 ( .A0(n4498), .A1(intDX_EWSW[15]), .B0(n4557), .B1(
intDX_EWSW[14]), .Y(n3522) );
AOI22X1TS U4780 ( .A0(n4497), .A1(intDX_EWSW[13]), .B0(n4554), .B1(
intDX_EWSW[4]), .Y(n3523) );
AOI22X1TS U4781 ( .A0(n4507), .A1(intDX_EWSW[10]), .B0(n4556), .B1(
intDX_EWSW[12]), .Y(n3524) );
AOI22X1TS U4782 ( .A0(n4491), .A1(intDX_EWSW[9]), .B0(n4578), .B1(
intDX_EWSW[16]), .Y(n3525) );
NOR4X1TS U4783 ( .A(n3529), .B(n3528), .C(n3527), .D(n3526), .Y(n3539) );
AOI22X1TS U4784 ( .A0(n4508), .A1(intDX_EWSW[7]), .B0(n4579), .B1(
intDX_EWSW[6]), .Y(n3530) );
AOI22X1TS U4785 ( .A0(n4509), .A1(intDX_EWSW[5]), .B0(n4563), .B1(
intDX_EWSW[28]), .Y(n3531) );
AOI22X1TS U4786 ( .A0(n4496), .A1(intDX_EWSW[3]), .B0(n4553), .B1(
intDX_EWSW[2]), .Y(n3532) );
AOI22X1TS U4787 ( .A0(n4490), .A1(intDX_EWSW[0]), .B0(n4555), .B1(
intDX_EWSW[8]), .Y(n3533) );
NOR4X1TS U4788 ( .A(n3537), .B(n3536), .C(n3535), .D(n3534), .Y(n3538) );
CLKXOR2X2TS U4789 ( .A(intDY_EWSW[63]), .B(intAS), .Y(n4431) );
INVX2TS U4790 ( .A(n4431), .Y(n3550) );
AOI22X1TS U4791 ( .A0(intDX_EWSW[63]), .A1(n3548), .B0(SIGN_FLAG_EXP), .B1(
n3547), .Y(n3549) );
OAI31X1TS U4792 ( .A0(n4434), .A1(n3550), .A2(n4467), .B0(n3549), .Y(n1610)
);
BUFX3TS U4793 ( .A(n3551), .Y(n3609) );
AOI22X1TS U4794 ( .A0(n3609), .A1(n3552), .B0(Data_array_SWR[25]), .B1(n3611), .Y(n3554) );
NAND2X1TS U4795 ( .A(n3613), .B(n1904), .Y(n3553) );
OAI211X1TS U4796 ( .A0(n3556), .A1(n3555), .B0(n3554), .C0(n3553), .Y(n1723)
);
INVX2TS U4797 ( .A(n3557), .Y(n3564) );
OA22X1TS U4798 ( .A0(n3616), .A1(n3560), .B0(n3559), .B1(n3558), .Y(n3563)
);
AOI22X1TS U4799 ( .A0(n3609), .A1(n3561), .B0(Data_array_SWR[5]), .B1(n3611),
.Y(n3562) );
AOI22X1TS U4800 ( .A0(n3590), .A1(n3566), .B0(n3588), .B1(n3565), .Y(n3569)
);
AOI22X1TS U4801 ( .A0(n3609), .A1(n3567), .B0(Data_array_SWR[9]), .B1(n3611),
.Y(n3568) );
INVX2TS U4802 ( .A(n3571), .Y(n3577) );
AOI22X1TS U4803 ( .A0(n3603), .A1(n3573), .B0(n3588), .B1(n3572), .Y(n3576)
);
AOI22X1TS U4804 ( .A0(n3609), .A1(n3574), .B0(Data_array_SWR[13]), .B1(n3611), .Y(n3575) );
OAI211X1TS U4805 ( .A0(n3577), .A1(n3594), .B0(n3576), .C0(n3575), .Y(n1711)
);
AOI22X1TS U4806 ( .A0(n3580), .A1(n3579), .B0(n3613), .B1(n3578), .Y(n3583)
);
AOI22X1TS U4807 ( .A0(n3609), .A1(n3581), .B0(Data_array_SWR[17]), .B1(n3611), .Y(n3582) );
INVX2TS U4808 ( .A(n3586), .Y(n3595) );
AOI22X1TS U4809 ( .A0(n3590), .A1(n3589), .B0(n3588), .B1(n3587), .Y(n3593)
);
AOI22X1TS U4810 ( .A0(n3609), .A1(n3591), .B0(Data_array_SWR[21]), .B1(n3611), .Y(n3592) );
AOI22X1TS U4811 ( .A0(n3603), .A1(n3608), .B0(Data_array_SWR[26]), .B1(n3604), .Y(n3598) );
NAND2X1TS U4812 ( .A(n1995), .B(n3596), .Y(n3597) );
INVX2TS U4813 ( .A(n3601), .Y(n3617) );
AOI22X1TS U4814 ( .A0(n3603), .A1(n3602), .B0(n3609), .B1(n3612), .Y(n3606)
);
AOI22X1TS U4815 ( .A0(n3613), .A1(n3610), .B0(Data_array_SWR[30]), .B1(n3604), .Y(n3605) );
OAI211X1TS U4816 ( .A0(n3617), .A1(n3607), .B0(n3606), .C0(n3605), .Y(n1728)
);
AOI22X1TS U4817 ( .A0(n1995), .A1(n3610), .B0(n3609), .B1(n3608), .Y(n3615)
);
AOI22X1TS U4818 ( .A0(n3613), .A1(n3612), .B0(Data_array_SWR[29]), .B1(n3611), .Y(n3614) );
OAI211X1TS U4819 ( .A0(n3617), .A1(n3616), .B0(n3615), .C0(n3614), .Y(n1727)
);
OAI21XLTS U4820 ( .A0(Shift_reg_FLAGS_7[1]), .A1(n1918), .B0(n3618), .Y(
n1276) );
INVX2TS U4821 ( .A(n3631), .Y(n3670) );
INVX2TS U4822 ( .A(n3624), .Y(n3668) );
BUFX3TS U4823 ( .A(n4477), .Y(n3641) );
OAI222X1TS U4824 ( .A0(n3670), .A1(n3620), .B0(n3645), .B1(n3619), .C0(n4633), .C1(n3641), .Y(n1130) );
BUFX3TS U4825 ( .A(n4477), .Y(n3637) );
OAI222X1TS U4826 ( .A0(n3668), .A1(n3620), .B0(n3643), .B1(n3619), .C0(n4632), .C1(n3637), .Y(n1128) );
OAI222X1TS U4827 ( .A0(n3666), .A1(n3630), .B0(n3640), .B1(n3629), .C0(n4649), .C1(n3637), .Y(n1137) );
OAI222X1TS U4828 ( .A0(n3645), .A1(n3623), .B0(n3643), .B1(n3622), .C0(n4646), .C1(n3641), .Y(n1127) );
OAI222X1TS U4829 ( .A0(n3643), .A1(n3626), .B0(n3668), .B1(n3625), .C0(n4648), .C1(n3637), .Y(n1133) );
OAI222X1TS U4830 ( .A0(n3640), .A1(n1935), .B0(n3666), .B1(n3621), .C0(n4631), .C1(n3641), .Y(n1126) );
OAI222X1TS U4831 ( .A0(n3666), .A1(n1935), .B0(n3668), .B1(n3621), .C0(n4634), .C1(n3637), .Y(n1132) );
OAI222X1TS U4832 ( .A0(n3670), .A1(n3623), .B0(n3645), .B1(n3622), .C0(n4647), .C1(n3637), .Y(n1131) );
INVX2TS U4833 ( .A(n3624), .Y(n3640) );
OAI222X1TS U4834 ( .A0(n3645), .A1(n3626), .B0(n3666), .B1(n3625), .C0(n4645), .C1(n3641), .Y(n1125) );
OAI222X1TS U4835 ( .A0(n3645), .A1(n3630), .B0(n3670), .B1(n3629), .C0(n4644), .C1(n3641), .Y(n1121) );
INVX2TS U4836 ( .A(n3631), .Y(n3666) );
OAI222X1TS U4837 ( .A0(n3668), .A1(n1936), .B0(n3666), .B1(n3632), .C0(n4639), .C1(n3641), .Y(n1105) );
OAI222X1TS U4838 ( .A0(n3640), .A1(n3634), .B0(n3670), .B1(n3633), .C0(n4640), .C1(n4477), .Y(n1109) );
OAI222X1TS U4839 ( .A0(n3640), .A1(n3636), .B0(n3670), .B1(n3635), .C0(n4658), .C1(n3641), .Y(n1110) );
INVX2TS U4840 ( .A(n4330), .Y(n3650) );
AOI21X1TS U4841 ( .A0(n3650), .A1(n3649), .B0(n2369), .Y(n3667) );
INVX2TS U4842 ( .A(n4332), .Y(n3665) );
AOI22X1TS U4843 ( .A0(n3652), .A1(Data_array_SWR[24]), .B0(n2869), .B1(
Data_array_SWR[20]), .Y(n3656) );
AOI22X1TS U4844 ( .A0(n3654), .A1(Data_array_SWR[28]), .B0(n3653), .B1(
Data_array_SWR[16]), .Y(n3655) );
AOI22X1TS U4845 ( .A0(n1934), .A1(Data_array_SWR[12]), .B0(n1922), .B1(
Data_array_SWR[8]), .Y(n3658) );
AOI22X1TS U4846 ( .A0(n1924), .A1(Data_array_SWR[0]), .B0(n3660), .B1(n4302),
.Y(n3661) );
OAI2BB1X1TS U4847 ( .A0N(Data_array_SWR[4]), .A1N(n1920), .B0(n3661), .Y(
n3662) );
AOI211X1TS U4848 ( .A0(n3665), .A1(n3664), .B0(n3663), .C0(n3662), .Y(n3669)
);
OAI222X1TS U4849 ( .A0(n3666), .A1(n3667), .B0(n4668), .B1(n1913), .C0(n3668), .C1(n3669), .Y(n1156) );
OAI222X1TS U4850 ( .A0(n3643), .A1(n3669), .B0(n4659), .B1(n4286), .C0(n3640), .C1(n3667), .Y(n1102) );
OAI2BB2XLTS U4851 ( .B0(n3671), .B1(n4393), .A0N(final_result_ieee[63]),
.A1N(n4377), .Y(n1270) );
AOI21X1TS U4852 ( .A0(n3675), .A1(n3689), .B0(n3674), .Y(n4345) );
OAI2BB2XLTS U4853 ( .B0(n3680), .B1(n4345), .A0N(final_result_ieee[11]),
.A1N(n4377), .Y(n1181) );
AOI21X1TS U4854 ( .A0(n3679), .A1(n3689), .B0(n3678), .Y(n4346) );
OAI2BB2XLTS U4855 ( .B0(n3680), .B1(n4346), .A0N(final_result_ieee[10]),
.A1N(n4377), .Y(n1179) );
AOI21X1TS U4856 ( .A0(n3684), .A1(n1927), .B0(n3683), .Y(n4344) );
OAI2BB2XLTS U4857 ( .B0(n3693), .B1(n4344), .A0N(final_result_ieee[12]),
.A1N(n4391), .Y(n1183) );
AOI21X1TS U4858 ( .A0(n3690), .A1(n3689), .B0(n3688), .Y(n4343) );
OAI2BB2XLTS U4859 ( .B0(n3693), .B1(n4343), .A0N(final_result_ieee[13]),
.A1N(n4391), .Y(n1185) );
INVX2TS U4860 ( .A(n3691), .Y(n3692) );
OAI2BB2XLTS U4861 ( .B0(n3693), .B1(n3692), .A0N(final_result_ieee[62]),
.A1N(n4377), .Y(n1676) );
NOR2XLTS U4862 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n3694) );
AOI32X4TS U4863 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .A2(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(n3694), .B1(n4567), .Y(n4399)
);
MXI2X1TS U4864 ( .A(n4475), .B(n4458), .S0(n4399), .Y(n1888) );
MXI2X1TS U4865 ( .A(n3696), .B(n3747), .S0(n4399), .Y(n1885) );
MXI2X1TS U4866 ( .A(n3697), .B(n3696), .S0(n4399), .Y(n1884) );
BUFX3TS U4867 ( .A(n4286), .Y(n4452) );
CLKBUFX2TS U4868 ( .A(n4674), .Y(n4447) );
BUFX3TS U4869 ( .A(n4447), .Y(n4472) );
INVX2TS U4870 ( .A(n4452), .Y(n3700) );
NAND2X1TS U4871 ( .A(DmP_EXP_EWSW[55]), .B(n1960), .Y(n4261) );
NOR2X1TS U4872 ( .A(n1978), .B(DMP_EXP_EWSW[54]), .Y(n4257) );
NAND2X1TS U4873 ( .A(DmP_EXP_EWSW[53]), .B(n1959), .Y(n4253) );
AOI22X1TS U4874 ( .A0(DMP_EXP_EWSW[53]), .A1(n4486), .B0(n4255), .B1(n4253),
.Y(n4259) );
OAI22X1TS U4875 ( .A0(n4257), .A1(n4259), .B0(DmP_EXP_EWSW[54]), .B1(n4485),
.Y(n4263) );
AOI22X1TS U4876 ( .A0(DMP_EXP_EWSW[55]), .A1(n4488), .B0(n4261), .B1(n4263),
.Y(n3708) );
NOR2X1TS U4877 ( .A(n1964), .B(DMP_EXP_EWSW[56]), .Y(n3709) );
AOI21X1TS U4878 ( .A0(DMP_EXP_EWSW[56]), .A1(n1964), .B0(n3709), .Y(n3706)
);
XNOR2X1TS U4879 ( .A(n3708), .B(n3706), .Y(n3707) );
OAI22X1TS U4880 ( .A0(n3709), .A1(n3708), .B0(DmP_EXP_EWSW[56]), .B1(n4530),
.Y(n3711) );
XNOR2X1TS U4881 ( .A(DmP_EXP_EWSW[57]), .B(DMP_EXP_EWSW[57]), .Y(n3710) );
XOR2X1TS U4882 ( .A(n3711), .B(n3710), .Y(n3712) );
INVX2TS U4883 ( .A(n3714), .Y(n3715) );
AOI21X1TS U4884 ( .A0(n3951), .A1(n3716), .B0(n3715), .Y(n3940) );
INVX2TS U4885 ( .A(n3940), .Y(n3919) );
AOI21X1TS U4886 ( .A0(n3919), .A1(n3718), .B0(n3717), .Y(n3968) );
NAND2X1TS U4887 ( .A(n3723), .B(n3722), .Y(n3726) );
INVX2TS U4888 ( .A(n3726), .Y(n3724) );
XNOR2X1TS U4889 ( .A(n3725), .B(n3724), .Y(n3730) );
XOR2X1TS U4890 ( .A(n3727), .B(n3726), .Y(n3728) );
AOI22X1TS U4891 ( .A0(n3728), .A1(n4367), .B0(Raw_mant_NRM_SWR[32]), .B1(
n3747), .Y(n3729) );
OAI2BB1X1TS U4892 ( .A0N(n4275), .A1N(n3730), .B0(n3729), .Y(n1237) );
BUFX3TS U4893 ( .A(n3979), .Y(n3855) );
NAND2X1TS U4894 ( .A(n3732), .B(n3731), .Y(n3736) );
INVX2TS U4895 ( .A(n3736), .Y(n3733) );
XNOR2X1TS U4896 ( .A(n3735), .B(n3736), .Y(n3737) );
AOI22X1TS U4897 ( .A0(n3737), .A1(n4367), .B0(Raw_mant_NRM_SWR[52]), .B1(
n3747), .Y(n3738) );
OAI2BB1X1TS U4898 ( .A0N(n3855), .A1N(n3739), .B0(n3738), .Y(n1217) );
INVX2TS U4899 ( .A(n3740), .Y(n3742) );
NAND2X1TS U4900 ( .A(n3742), .B(n3741), .Y(n3745) );
INVX2TS U4901 ( .A(n3745), .Y(n3743) );
XNOR2X1TS U4902 ( .A(n3744), .B(n3743), .Y(n3750) );
XOR2X1TS U4903 ( .A(n3746), .B(n3745), .Y(n3748) );
AOI22X1TS U4904 ( .A0(n3748), .A1(n4367), .B0(Raw_mant_NRM_SWR[51]), .B1(
n3747), .Y(n3749) );
OAI2BB1X1TS U4905 ( .A0N(n3855), .A1N(n3750), .B0(n3749), .Y(n1218) );
NAND2X1TS U4906 ( .A(n3752), .B(n3751), .Y(n3756) );
INVX2TS U4907 ( .A(n3756), .Y(n3753) );
XNOR2X1TS U4908 ( .A(n3755), .B(n3756), .Y(n3757) );
BUFX3TS U4909 ( .A(n4448), .Y(n3872) );
AOI22X1TS U4910 ( .A0(n3757), .A1(n4367), .B0(Raw_mant_NRM_SWR[48]), .B1(
n3872), .Y(n3758) );
OAI2BB1X1TS U4911 ( .A0N(n3855), .A1N(n3759), .B0(n3758), .Y(n1221) );
INVX2TS U4912 ( .A(n3760), .Y(n3762) );
NAND2X1TS U4913 ( .A(n3762), .B(n3761), .Y(n3765) );
INVX2TS U4914 ( .A(n3765), .Y(n3763) );
XNOR2X1TS U4915 ( .A(n3764), .B(n3763), .Y(n3769) );
XOR2X1TS U4916 ( .A(n3766), .B(n3765), .Y(n3767) );
AOI22X1TS U4917 ( .A0(n3767), .A1(n4367), .B0(Raw_mant_NRM_SWR[49]), .B1(
n3872), .Y(n3768) );
OAI2BB1X1TS U4918 ( .A0N(n3855), .A1N(n3769), .B0(n3768), .Y(n1220) );
NAND2X1TS U4919 ( .A(n3771), .B(n3770), .Y(n3775) );
INVX2TS U4920 ( .A(n3775), .Y(n3772) );
XNOR2X1TS U4921 ( .A(n3774), .B(n3775), .Y(n3776) );
AOI22X1TS U4922 ( .A0(n3776), .A1(n3911), .B0(Raw_mant_NRM_SWR[50]), .B1(
n3872), .Y(n3777) );
OAI2BB1X1TS U4923 ( .A0N(n3855), .A1N(n3778), .B0(n3777), .Y(n1219) );
OAI21X1TS U4924 ( .A0(n3781), .A1(n3780), .B0(n3779), .Y(n3801) );
INVX2TS U4925 ( .A(n3801), .Y(n3814) );
NAND2X1TS U4926 ( .A(n3784), .B(n3783), .Y(n3792) );
INVX2TS U4927 ( .A(n3792), .Y(n3785) );
INVX1TS U4928 ( .A(n3786), .Y(n3789) );
OAI21X1TS U4929 ( .A0(n3849), .A1(n3789), .B0(n3788), .Y(n3910) );
AOI21X1TS U4930 ( .A0(n3910), .A1(n3906), .B0(n3791), .Y(n3793) );
XOR2X1TS U4931 ( .A(n3793), .B(n3792), .Y(n3794) );
AOI22X1TS U4932 ( .A0(n3794), .A1(n4367), .B0(Raw_mant_NRM_SWR[37]), .B1(
n3872), .Y(n3795) );
OAI2BB1X1TS U4933 ( .A0N(n3855), .A1N(n3796), .B0(n3795), .Y(n1232) );
AOI21X1TS U4934 ( .A0(n3801), .A1(n3800), .B0(n3799), .Y(n3804) );
NAND2X1TS U4935 ( .A(n3821), .B(n3819), .Y(n3805) );
INVX2TS U4936 ( .A(n3805), .Y(n3803) );
XOR2X1TS U4937 ( .A(n3806), .B(n3805), .Y(n3807) );
BUFX3TS U4938 ( .A(n4174), .Y(n4147) );
AOI22X1TS U4939 ( .A0(n3807), .A1(n4147), .B0(Raw_mant_NRM_SWR[38]), .B1(
n3872), .Y(n3808) );
OAI2BB1X1TS U4940 ( .A0N(n3855), .A1N(n3809), .B0(n3808), .Y(n1231) );
INVX2TS U4941 ( .A(n3811), .Y(n3812) );
OAI21X1TS U4942 ( .A0(n3814), .A1(n3813), .B0(n3812), .Y(n3832) );
NAND2X1TS U4943 ( .A(n3817), .B(n3816), .Y(n3823) );
INVX2TS U4944 ( .A(n3823), .Y(n3818) );
XNOR2X1TS U4945 ( .A(n3832), .B(n3818), .Y(n3827) );
AOI21X1TS U4946 ( .A0(n3822), .A1(n3821), .B0(n3820), .Y(n3824) );
XOR2X1TS U4947 ( .A(n3824), .B(n3823), .Y(n3825) );
AOI22X1TS U4948 ( .A0(n3825), .A1(n3911), .B0(Raw_mant_NRM_SWR[39]), .B1(
n3872), .Y(n3826) );
OAI2BB1X1TS U4949 ( .A0N(n3855), .A1N(n3827), .B0(n3826), .Y(n1230) );
INVX2TS U4950 ( .A(n3829), .Y(n3830) );
AOI21X1TS U4951 ( .A0(n3832), .A1(n3831), .B0(n3830), .Y(n3836) );
NAND2X1TS U4952 ( .A(n3834), .B(n3833), .Y(n3837) );
INVX2TS U4953 ( .A(n3837), .Y(n3835) );
XNOR2X1TS U4954 ( .A(n3838), .B(n3837), .Y(n3839) );
AOI22X1TS U4955 ( .A0(n3839), .A1(n3911), .B0(Raw_mant_NRM_SWR[40]), .B1(
n3872), .Y(n3840) );
OAI2BB1X1TS U4956 ( .A0N(n3855), .A1N(n3841), .B0(n3840), .Y(n1229) );
INVX2TS U4957 ( .A(n3842), .Y(n3844) );
NAND2X1TS U4958 ( .A(n3844), .B(n3843), .Y(n3850) );
INVX2TS U4959 ( .A(n3850), .Y(n3845) );
XNOR2X1TS U4960 ( .A(n3851), .B(n3850), .Y(n3852) );
AOI22X1TS U4961 ( .A0(n3852), .A1(n3911), .B0(Raw_mant_NRM_SWR[44]), .B1(
n3872), .Y(n3853) );
OAI2BB1X1TS U4962 ( .A0N(n3855), .A1N(n3854), .B0(n3853), .Y(n1225) );
BUFX3TS U4963 ( .A(n3979), .Y(n3978) );
INVX2TS U4964 ( .A(n3856), .Y(n3858) );
NAND2X1TS U4965 ( .A(n3858), .B(n3857), .Y(n3861) );
INVX2TS U4966 ( .A(n3861), .Y(n3859) );
XNOR2X1TS U4967 ( .A(n3860), .B(n3859), .Y(n3865) );
XOR2X1TS U4968 ( .A(n3862), .B(n3861), .Y(n3863) );
AOI22X1TS U4969 ( .A0(n3863), .A1(n3911), .B0(Raw_mant_NRM_SWR[45]), .B1(
n3872), .Y(n3864) );
OAI2BB1X1TS U4970 ( .A0N(n3978), .A1N(n3865), .B0(n3864), .Y(n1224) );
NAND2X1TS U4971 ( .A(n3867), .B(n3866), .Y(n3870) );
INVX2TS U4972 ( .A(n3870), .Y(n3868) );
XNOR2X1TS U4973 ( .A(n3871), .B(n3870), .Y(n3873) );
AOI22X1TS U4974 ( .A0(n3873), .A1(n3911), .B0(Raw_mant_NRM_SWR[46]), .B1(
n3872), .Y(n3874) );
OAI2BB1X1TS U4975 ( .A0N(n3978), .A1N(n3875), .B0(n3874), .Y(n1223) );
INVX2TS U4976 ( .A(n3877), .Y(n3878) );
AOI21X1TS U4977 ( .A0(n3880), .A1(n3879), .B0(n3878), .Y(n3884) );
NAND2X1TS U4978 ( .A(n3882), .B(n3881), .Y(n3885) );
INVX2TS U4979 ( .A(n3885), .Y(n3883) );
XNOR2X1TS U4980 ( .A(n3886), .B(n3885), .Y(n3887) );
AOI22X1TS U4981 ( .A0(n3887), .A1(n3911), .B0(Raw_mant_NRM_SWR[42]), .B1(
n3974), .Y(n3888) );
OAI2BB1X1TS U4982 ( .A0N(n3978), .A1N(n3889), .B0(n3888), .Y(n1227) );
INVX2TS U4983 ( .A(n3890), .Y(n3892) );
NAND2X1TS U4984 ( .A(n3892), .B(n3891), .Y(n3895) );
INVX2TS U4985 ( .A(n3895), .Y(n3893) );
XNOR2X1TS U4986 ( .A(n3894), .B(n3893), .Y(n3899) );
XOR2X1TS U4987 ( .A(n3896), .B(n3895), .Y(n3897) );
AOI22X1TS U4988 ( .A0(n3897), .A1(n3911), .B0(Raw_mant_NRM_SWR[47]), .B1(
n3974), .Y(n3898) );
OAI2BB1X1TS U4989 ( .A0N(n3978), .A1N(n3899), .B0(n3898), .Y(n1222) );
INVX2TS U4990 ( .A(n3901), .Y(n3902) );
AOI21X1TS U4991 ( .A0(n3904), .A1(n3903), .B0(n3902), .Y(n3908) );
NAND2X1TS U4992 ( .A(n3906), .B(n3905), .Y(n3909) );
INVX2TS U4993 ( .A(n3909), .Y(n3907) );
XNOR2X1TS U4994 ( .A(n3910), .B(n3909), .Y(n3912) );
AOI22X1TS U4995 ( .A0(n3912), .A1(n3911), .B0(Raw_mant_NRM_SWR[36]), .B1(
n3974), .Y(n3913) );
OAI2BB1X1TS U4996 ( .A0N(n3978), .A1N(n3914), .B0(n3913), .Y(n1233) );
NAND2X1TS U4997 ( .A(n3917), .B(n3916), .Y(n3922) );
INVX2TS U4998 ( .A(n3922), .Y(n3918) );
XNOR2X1TS U4999 ( .A(n3919), .B(n3918), .Y(n3926) );
AOI21X1TS U5000 ( .A0(n3934), .A1(n3921), .B0(n3920), .Y(n3960) );
XNOR2X1TS U5001 ( .A(n3923), .B(n3922), .Y(n3924) );
AOI22X1TS U5002 ( .A0(n3924), .A1(n4147), .B0(Raw_mant_NRM_SWR[29]), .B1(
n3974), .Y(n3925) );
OAI2BB1X1TS U5003 ( .A0N(n3978), .A1N(n3926), .B0(n3925), .Y(n1240) );
INVX2TS U5004 ( .A(n4357), .Y(n3930) );
NAND2X1TS U5005 ( .A(n3930), .B(n4356), .Y(n3933) );
INVX2TS U5006 ( .A(n3933), .Y(n3931) );
XNOR2X1TS U5007 ( .A(n3932), .B(n3931), .Y(n3937) );
XNOR2X1TS U5008 ( .A(n3934), .B(n3933), .Y(n3935) );
AOI22X1TS U5009 ( .A0(n3935), .A1(n4147), .B0(Raw_mant_NRM_SWR[26]), .B1(
n3974), .Y(n3936) );
OAI2BB1X1TS U5010 ( .A0N(n3978), .A1N(n3937), .B0(n3936), .Y(n1243) );
NAND2X1TS U5011 ( .A(n3941), .B(n3969), .Y(n3944) );
INVX2TS U5012 ( .A(n3944), .Y(n3942) );
XNOR2X1TS U5013 ( .A(n3943), .B(n3942), .Y(n3948) );
XNOR2X1TS U5014 ( .A(n3945), .B(n3944), .Y(n3946) );
AOI22X1TS U5015 ( .A0(n3946), .A1(n4147), .B0(Raw_mant_NRM_SWR[30]), .B1(
n3974), .Y(n3947) );
OAI2BB1X1TS U5016 ( .A0N(n3978), .A1N(n3948), .B0(n3947), .Y(n1239) );
AOI21X1TS U5017 ( .A0(n3951), .A1(n3950), .B0(n3949), .Y(n4355) );
NAND2X1TS U5018 ( .A(n3956), .B(n3955), .Y(n3959) );
INVX2TS U5019 ( .A(n3959), .Y(n3957) );
XNOR2X1TS U5020 ( .A(n3958), .B(n3957), .Y(n3963) );
XOR2X1TS U5021 ( .A(n3960), .B(n3959), .Y(n3961) );
AOI22X1TS U5022 ( .A0(n3961), .A1(n4147), .B0(Raw_mant_NRM_SWR[28]), .B1(
n3974), .Y(n3962) );
OAI2BB1X1TS U5023 ( .A0N(n3978), .A1N(n3963), .B0(n3962), .Y(n1241) );
NAND2X1TS U5024 ( .A(n3966), .B(n3965), .Y(n3972) );
INVX2TS U5025 ( .A(n3972), .Y(n3967) );
XNOR2X1TS U5026 ( .A(n3973), .B(n3972), .Y(n3975) );
AOI22X1TS U5027 ( .A0(n3975), .A1(n4147), .B0(Raw_mant_NRM_SWR[31]), .B1(
n3974), .Y(n3976) );
OAI2BB1X1TS U5028 ( .A0N(n3978), .A1N(n3977), .B0(n3976), .Y(n1238) );
BUFX3TS U5029 ( .A(n3979), .Y(n4365) );
INVX2TS U5030 ( .A(n3980), .Y(n3983) );
INVX2TS U5031 ( .A(n3981), .Y(n3982) );
AOI21X1TS U5032 ( .A0(n4011), .A1(n3983), .B0(n3982), .Y(n4033) );
NAND2X1TS U5033 ( .A(n3986), .B(n4053), .Y(n3989) );
INVX2TS U5034 ( .A(n3989), .Y(n3987) );
XNOR2X1TS U5035 ( .A(n3988), .B(n3987), .Y(n3993) );
XNOR2X1TS U5036 ( .A(n3990), .B(n3989), .Y(n3991) );
AOI22X1TS U5037 ( .A0(n3991), .A1(n4147), .B0(Raw_mant_NRM_SWR[22]), .B1(
n4090), .Y(n3992) );
OAI2BB1X1TS U5038 ( .A0N(n4365), .A1N(n3993), .B0(n3992), .Y(n1247) );
AOI21X1TS U5039 ( .A0(n4011), .A1(n3995), .B0(n3994), .Y(n4023) );
NAND2X1TS U5040 ( .A(n3998), .B(n4066), .Y(n4003) );
INVX2TS U5041 ( .A(n4003), .Y(n3999) );
XNOR2X1TS U5042 ( .A(n4000), .B(n3999), .Y(n4006) );
AOI21X1TS U5043 ( .A0(n4027), .A1(n4002), .B0(n4001), .Y(n4068) );
XOR2X1TS U5044 ( .A(n4068), .B(n4003), .Y(n4004) );
AOI22X1TS U5045 ( .A0(n4004), .A1(n4147), .B0(Raw_mant_NRM_SWR[20]), .B1(
n4090), .Y(n4005) );
OAI2BB1X1TS U5046 ( .A0N(n4365), .A1N(n4006), .B0(n4005), .Y(n1249) );
INVX2TS U5047 ( .A(n4007), .Y(n4010) );
INVX2TS U5048 ( .A(n4008), .Y(n4009) );
AOI21X1TS U5049 ( .A0(n4011), .A1(n4010), .B0(n4009), .Y(n4014) );
NAND2X1TS U5050 ( .A(n4026), .B(n4024), .Y(n4015) );
INVX2TS U5051 ( .A(n4015), .Y(n4013) );
XNOR2X1TS U5052 ( .A(n4027), .B(n4015), .Y(n4016) );
AOI22X1TS U5053 ( .A0(n4016), .A1(n4147), .B0(Raw_mant_NRM_SWR[18]), .B1(
n4090), .Y(n4017) );
OAI2BB1X1TS U5054 ( .A0N(n4365), .A1N(n4018), .B0(n4017), .Y(n1251) );
NAND2X1TS U5055 ( .A(n4021), .B(n4020), .Y(n4028) );
INVX2TS U5056 ( .A(n4028), .Y(n4022) );
AOI21X1TS U5057 ( .A0(n4027), .A1(n4026), .B0(n4025), .Y(n4029) );
XOR2X1TS U5058 ( .A(n4029), .B(n4028), .Y(n4030) );
AOI22X1TS U5059 ( .A0(n4030), .A1(n4160), .B0(Raw_mant_NRM_SWR[19]), .B1(
n4090), .Y(n4031) );
OAI2BB1X1TS U5060 ( .A0N(n4365), .A1N(n4032), .B0(n4031), .Y(n1250) );
INVX2TS U5061 ( .A(n4033), .Y(n4065) );
AOI21X1TS U5062 ( .A0(n4065), .A1(n4035), .B0(n4034), .Y(n4052) );
NAND2X1TS U5063 ( .A(n4040), .B(n4039), .Y(n4043) );
INVX2TS U5064 ( .A(n4043), .Y(n4041) );
XNOR2X1TS U5065 ( .A(n4042), .B(n4041), .Y(n4047) );
XOR2X1TS U5066 ( .A(n4044), .B(n4043), .Y(n4045) );
AOI22X1TS U5067 ( .A0(n4045), .A1(n4160), .B0(Raw_mant_NRM_SWR[24]), .B1(
n4090), .Y(n4046) );
OAI2BB1X1TS U5068 ( .A0N(n4365), .A1N(n4047), .B0(n4046), .Y(n1245) );
NAND2X1TS U5069 ( .A(n4050), .B(n4049), .Y(n4056) );
INVX2TS U5070 ( .A(n4056), .Y(n4051) );
XNOR2X1TS U5071 ( .A(n4057), .B(n4056), .Y(n4058) );
AOI22X1TS U5072 ( .A0(n4058), .A1(n4160), .B0(Raw_mant_NRM_SWR[23]), .B1(
n4090), .Y(n4059) );
OAI2BB1X1TS U5073 ( .A0N(n4365), .A1N(n4060), .B0(n4059), .Y(n1246) );
NAND2X1TS U5074 ( .A(n4063), .B(n4062), .Y(n4069) );
INVX2TS U5075 ( .A(n4069), .Y(n4064) );
XNOR2X1TS U5076 ( .A(n4065), .B(n4064), .Y(n4073) );
XNOR2X1TS U5077 ( .A(n4070), .B(n4069), .Y(n4071) );
AOI22X1TS U5078 ( .A0(n4071), .A1(n4160), .B0(Raw_mant_NRM_SWR[21]), .B1(
n4090), .Y(n4072) );
OAI2BB1X1TS U5079 ( .A0N(n4365), .A1N(n4073), .B0(n4072), .Y(n1248) );
OAI21X1TS U5080 ( .A0(n4166), .A1(n4075), .B0(n4074), .Y(n4182) );
INVX2TS U5081 ( .A(n4182), .Y(n4196) );
INVX2TS U5082 ( .A(n4076), .Y(n4079) );
INVX2TS U5083 ( .A(n4077), .Y(n4078) );
OAI21X1TS U5084 ( .A0(n4196), .A1(n4079), .B0(n4078), .Y(n4098) );
INVX2TS U5085 ( .A(n4081), .Y(n4082) );
AOI21X1TS U5086 ( .A0(n4098), .A1(n4083), .B0(n4082), .Y(n4087) );
NAND2X1TS U5087 ( .A(n4085), .B(n4084), .Y(n4088) );
INVX2TS U5088 ( .A(n4088), .Y(n4086) );
XNOR2X1TS U5089 ( .A(n4089), .B(n4088), .Y(n4091) );
AOI22X1TS U5090 ( .A0(n4091), .A1(n4160), .B0(Raw_mant_NRM_SWR[16]), .B1(
n4090), .Y(n4092) );
OAI2BB1X1TS U5091 ( .A0N(n4271), .A1N(n4093), .B0(n4092), .Y(n1253) );
NAND2X1TS U5092 ( .A(n4096), .B(n4095), .Y(n4102) );
INVX2TS U5093 ( .A(n4102), .Y(n4097) );
XNOR2X1TS U5094 ( .A(n4098), .B(n4097), .Y(n4106) );
AOI21X1TS U5095 ( .A0(n4101), .A1(n4184), .B0(n4100), .Y(n4103) );
XOR2X1TS U5096 ( .A(n4103), .B(n4102), .Y(n4104) );
AOI22X1TS U5097 ( .A0(n4104), .A1(n4160), .B0(Raw_mant_NRM_SWR[15]), .B1(
n4213), .Y(n4105) );
OAI2BB1X1TS U5098 ( .A0N(n4365), .A1N(n4106), .B0(n4105), .Y(n1254) );
INVX2TS U5099 ( .A(n4108), .Y(n4109) );
AOI21X1TS U5100 ( .A0(n4111), .A1(n4110), .B0(n4109), .Y(n4114) );
NAND2X1TS U5101 ( .A(n4199), .B(n4197), .Y(n4119) );
INVX2TS U5102 ( .A(n4119), .Y(n4113) );
OAI21X1TS U5103 ( .A0(n4173), .A1(n4118), .B0(n4117), .Y(n4200) );
XNOR2X1TS U5104 ( .A(n4200), .B(n4119), .Y(n4120) );
AOI22X1TS U5105 ( .A0(n4120), .A1(n4160), .B0(Raw_mant_NRM_SWR[12]), .B1(
n4213), .Y(n4121) );
OAI2BB1X1TS U5106 ( .A0N(n4271), .A1N(n4122), .B0(n4121), .Y(n1257) );
AOI21X1TS U5107 ( .A0(n4221), .A1(n4125), .B0(n4124), .Y(n4140) );
NAND2X1TS U5108 ( .A(n4128), .B(n4127), .Y(n4133) );
INVX2TS U5109 ( .A(n4133), .Y(n4129) );
INVX2TS U5110 ( .A(n4130), .Y(n4227) );
AOI21X1TS U5111 ( .A0(n4227), .A1(n4223), .B0(n4132), .Y(n4134) );
XOR2X1TS U5112 ( .A(n4134), .B(n4133), .Y(n4135) );
AOI22X1TS U5113 ( .A0(n4135), .A1(n4160), .B0(Raw_mant_NRM_SWR[7]), .B1(
n4213), .Y(n4136) );
OAI2BB1X1TS U5114 ( .A0N(n4365), .A1N(n4137), .B0(n4136), .Y(n1262) );
NAND2X1TS U5115 ( .A(n4141), .B(n4155), .Y(n4146) );
INVX2TS U5116 ( .A(n4146), .Y(n4142) );
XNOR2X1TS U5117 ( .A(n4143), .B(n4142), .Y(n4150) );
AOI21X1TS U5118 ( .A0(n4227), .A1(n4145), .B0(n4144), .Y(n4157) );
XOR2X1TS U5119 ( .A(n4157), .B(n4146), .Y(n4148) );
AOI22X1TS U5120 ( .A0(n4148), .A1(n4147), .B0(Raw_mant_NRM_SWR[8]), .B1(
n4213), .Y(n4149) );
OAI2BB1X1TS U5121 ( .A0N(n4271), .A1N(n4150), .B0(n4149), .Y(n1261) );
INVX2TS U5122 ( .A(n4151), .Y(n4153) );
NAND2X1TS U5123 ( .A(n4153), .B(n4152), .Y(n4158) );
INVX2TS U5124 ( .A(n4158), .Y(n4154) );
XNOR2X1TS U5125 ( .A(n4159), .B(n4158), .Y(n4161) );
AOI22X1TS U5126 ( .A0(n4161), .A1(n4160), .B0(Raw_mant_NRM_SWR[9]), .B1(
n4213), .Y(n4162) );
OAI2BB1X1TS U5127 ( .A0N(n4271), .A1N(n4163), .B0(n4162), .Y(n1260) );
NAND2X1TS U5128 ( .A(n4169), .B(n4168), .Y(n4172) );
INVX2TS U5129 ( .A(n4172), .Y(n4170) );
XNOR2X1TS U5130 ( .A(n4171), .B(n4170), .Y(n4177) );
XOR2X1TS U5131 ( .A(n4173), .B(n4172), .Y(n4175) );
BUFX3TS U5132 ( .A(n4174), .Y(n4361) );
AOI22X1TS U5133 ( .A0(n4175), .A1(n4361), .B0(Raw_mant_NRM_SWR[10]), .B1(
n4213), .Y(n4176) );
OAI2BB1X1TS U5134 ( .A0N(n4271), .A1N(n4177), .B0(n4176), .Y(n1259) );
INVX2TS U5135 ( .A(n4179), .Y(n4180) );
AOI21X1TS U5136 ( .A0(n4182), .A1(n4181), .B0(n4180), .Y(n4186) );
NAND2X1TS U5137 ( .A(n4184), .B(n4183), .Y(n4187) );
INVX2TS U5138 ( .A(n4187), .Y(n4185) );
XOR2X1TS U5139 ( .A(n4188), .B(n4187), .Y(n4189) );
AOI22X1TS U5140 ( .A0(n4189), .A1(n4361), .B0(Raw_mant_NRM_SWR[14]), .B1(
n4213), .Y(n4190) );
OAI2BB1X1TS U5141 ( .A0N(n4271), .A1N(n4191), .B0(n4190), .Y(n1255) );
NAND2X1TS U5142 ( .A(n4194), .B(n4193), .Y(n4201) );
INVX2TS U5143 ( .A(n4201), .Y(n4195) );
INVX2TS U5144 ( .A(n4197), .Y(n4198) );
AOI21X1TS U5145 ( .A0(n4200), .A1(n4199), .B0(n4198), .Y(n4202) );
XOR2X1TS U5146 ( .A(n4202), .B(n4201), .Y(n4203) );
AOI22X1TS U5147 ( .A0(n4203), .A1(n4361), .B0(Raw_mant_NRM_SWR[13]), .B1(
n4213), .Y(n4204) );
OAI2BB1X1TS U5148 ( .A0N(n4271), .A1N(n4205), .B0(n4204), .Y(n1256) );
NAND2X1TS U5149 ( .A(n4208), .B(n4207), .Y(n4211) );
INVX2TS U5150 ( .A(n4211), .Y(n4209) );
XNOR2X1TS U5151 ( .A(n4221), .B(n4209), .Y(n4216) );
XNOR2X1TS U5152 ( .A(n4212), .B(n4211), .Y(n4214) );
AOI22X1TS U5153 ( .A0(n4214), .A1(n4361), .B0(Raw_mant_NRM_SWR[5]), .B1(
n4213), .Y(n4215) );
OAI2BB1X1TS U5154 ( .A0N(n4275), .A1N(n4216), .B0(n4215), .Y(n1264) );
INVX2TS U5155 ( .A(n4217), .Y(n4220) );
INVX2TS U5156 ( .A(n4218), .Y(n4219) );
AOI21X1TS U5157 ( .A0(n4221), .A1(n4220), .B0(n4219), .Y(n4225) );
NAND2X1TS U5158 ( .A(n4223), .B(n4222), .Y(n4226) );
INVX2TS U5159 ( .A(n4226), .Y(n4224) );
XNOR2X1TS U5160 ( .A(n4227), .B(n4226), .Y(n4228) );
BUFX3TS U5161 ( .A(n4448), .Y(n4478) );
AOI22X1TS U5162 ( .A0(n4228), .A1(n4361), .B0(Raw_mant_NRM_SWR[6]), .B1(
n4478), .Y(n4229) );
OAI2BB1X1TS U5163 ( .A0N(n4275), .A1N(n4230), .B0(n4229), .Y(n1263) );
INVX2TS U5164 ( .A(n4231), .Y(n4248) );
NAND2X1TS U5165 ( .A(n4236), .B(n4235), .Y(n4239) );
INVX2TS U5166 ( .A(n4239), .Y(n4237) );
XNOR2X1TS U5167 ( .A(n4238), .B(n4237), .Y(n4243) );
XOR2X1TS U5168 ( .A(n4240), .B(n4239), .Y(n4241) );
AOI22X1TS U5169 ( .A0(n4241), .A1(n4361), .B0(Raw_mant_NRM_SWR[4]), .B1(
n4478), .Y(n4242) );
OAI2BB1X1TS U5170 ( .A0N(n4275), .A1N(n4243), .B0(n4242), .Y(n1265) );
INVX2TS U5171 ( .A(n4244), .Y(n4246) );
NAND2X1TS U5172 ( .A(n4246), .B(n4245), .Y(n4249) );
INVX2TS U5173 ( .A(n4249), .Y(n4247) );
XOR2X1TS U5174 ( .A(n4249), .B(n4265), .Y(n4250) );
AOI22X1TS U5175 ( .A0(n4250), .A1(n4361), .B0(Raw_mant_NRM_SWR[3]), .B1(
n4478), .Y(n4251) );
OAI2BB1X1TS U5176 ( .A0N(n4271), .A1N(n4252), .B0(n4251), .Y(n1266) );
XNOR2X1TS U5177 ( .A(n4255), .B(n4254), .Y(n4256) );
CLKBUFX2TS U5178 ( .A(n4629), .Y(n4464) );
BUFX3TS U5179 ( .A(n4464), .Y(n4435) );
AOI21X1TS U5180 ( .A0(DMP_EXP_EWSW[54]), .A1(n1978), .B0(n4257), .Y(n4258)
);
XNOR2X1TS U5181 ( .A(n4259), .B(n4258), .Y(n4260) );
XNOR2X1TS U5182 ( .A(n4263), .B(n4262), .Y(n4264) );
OR2X1TS U5183 ( .A(DMP_SFG[0]), .B(DmP_mant_SFG_SWR[2]), .Y(n4266) );
AOI22X1TS U5184 ( .A0(n4268), .A1(n4361), .B0(Raw_mant_NRM_SWR[2]), .B1(
n4478), .Y(n4269) );
OAI2BB1X1TS U5185 ( .A0N(n4271), .A1N(n4270), .B0(n4269), .Y(n1267) );
MXI2X1TS U5186 ( .A(n4587), .B(n4272), .S0(n1926), .Y(n1269) );
XNOR2X1TS U5187 ( .A(DmP_mant_SFG_SWR[1]), .B(n4272), .Y(n4274) );
AOI22X1TS U5188 ( .A0(n4361), .A1(DmP_mant_SFG_SWR[1]), .B0(
Raw_mant_NRM_SWR[1]), .B1(n4478), .Y(n4273) );
OAI2BB1X1TS U5189 ( .A0N(n4275), .A1N(n4274), .B0(n4273), .Y(n1268) );
INVX2TS U5190 ( .A(n4302), .Y(n4334) );
OAI22X1TS U5191 ( .A0(n4334), .A1(n4292), .B0(n4332), .B1(n4329), .Y(n4283)
);
AOI211X1TS U5192 ( .A0(n4323), .A1(n4337), .B0(n4284), .C0(n4283), .Y(n4285)
);
OAI21X1TS U5193 ( .A0(n4341), .A1(n4325), .B0(n4285), .Y(n4384) );
AOI22X1TS U5194 ( .A0(n4318), .A1(n4307), .B0(n4316), .B1(n4308), .Y(n4290)
);
AOI21X1TS U5195 ( .A0(n4338), .A1(n4312), .B0(n4293), .Y(n4294) );
OAI21X1TS U5196 ( .A0(n4314), .A1(n4340), .B0(n4294), .Y(n4382) );
NAND2X1TS U5197 ( .A(n4297), .B(n3022), .Y(n4301) );
NAND2X1TS U5198 ( .A(n4299), .B(n4298), .Y(n4300) );
AOI22X1TS U5199 ( .A0(n4318), .A1(n4337), .B0(n4316), .B1(n4302), .Y(n4303)
);
AOI21X1TS U5200 ( .A0(n1938), .A1(n4305), .B0(n4304), .Y(n4306) );
OAI21X1TS U5201 ( .A0(n4332), .A1(n4325), .B0(n4306), .Y(n4379) );
AOI22X1TS U5202 ( .A0(n4318), .A1(n4308), .B0(n4316), .B1(n4307), .Y(n4309)
);
AOI21X1TS U5203 ( .A0(n1938), .A1(n4312), .B0(n4311), .Y(n4313) );
OAI21X1TS U5204 ( .A0(n4314), .A1(n4325), .B0(n4313), .Y(n4378) );
AOI22X1TS U5205 ( .A0(n4318), .A1(n4317), .B0(n4316), .B1(n4315), .Y(n4319)
);
AOI21X1TS U5206 ( .A0(n1938), .A1(n4322), .B0(n4321), .Y(n4324) );
OAI21X1TS U5207 ( .A0(n4326), .A1(n4325), .B0(n4324), .Y(n4376) );
OAI22X1TS U5208 ( .A0(n4334), .A1(n4333), .B0(n4332), .B1(n4331), .Y(n4335)
);
AOI211X1TS U5209 ( .A0(n4338), .A1(n4337), .B0(n4336), .C0(n4335), .Y(n4339)
);
OAI21X1TS U5210 ( .A0(n4341), .A1(n4340), .B0(n4339), .Y(n4375) );
MXI2X1TS U5211 ( .A(n4343), .B(n4654), .S0(n4349), .Y(n1141) );
MXI2X1TS U5212 ( .A(n4344), .B(n4637), .S0(n4349), .Y(n1142) );
MXI2X1TS U5213 ( .A(n4345), .B(n4655), .S0(n4349), .Y(n1143) );
MXI2X1TS U5214 ( .A(n4346), .B(n4638), .S0(n4349), .Y(n1144) );
INVX2TS U5215 ( .A(n4351), .Y(n4353) );
NAND2X1TS U5216 ( .A(n4353), .B(n4352), .Y(n4359) );
INVX2TS U5217 ( .A(n4359), .Y(n4354) );
XNOR2X1TS U5218 ( .A(n4360), .B(n4359), .Y(n4362) );
AOI22X1TS U5219 ( .A0(n4362), .A1(n4361), .B0(Raw_mant_NRM_SWR[27]), .B1(
n4478), .Y(n4363) );
OAI2BB1X1TS U5220 ( .A0N(n4365), .A1N(n4364), .B0(n4363), .Y(n1242) );
MX2X1TS U5221 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n1429) );
OAI2BB1X1TS U5222 ( .A0N(LZD_output_NRM2_EW[0]), .A1N(n3382), .B0(n4373),
.Y(n1210) );
OA21XLTS U5223 ( .A0(n4675), .A1(overflow_flag), .B0(n4393), .Y(n1287) );
AOI22X1TS U5224 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n4395), .B1(n4511), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
NAND2X1TS U5225 ( .A(n4395), .B(n4394), .Y(n1892) );
INVX2TS U5226 ( .A(n4399), .Y(n4398) );
AOI22X1TS U5227 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(n4396), .B0(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(n4511), .Y(n4400) );
AOI22X1TS U5228 ( .A0(n4399), .A1(n4397), .B0(n4435), .B1(n4398), .Y(n1889)
);
BUFX3TS U5229 ( .A(n4418), .Y(n4412) );
BUFX3TS U5230 ( .A(n4412), .Y(n4404) );
BUFX3TS U5231 ( .A(n4414), .Y(n4410) );
INVX2TS U5232 ( .A(n4410), .Y(n4427) );
BUFX3TS U5233 ( .A(n4415), .Y(n4421) );
INVX2TS U5234 ( .A(n4418), .Y(n4401) );
BUFX3TS U5235 ( .A(n4412), .Y(n4406) );
INVX2TS U5236 ( .A(n4415), .Y(n4402) );
BUFX3TS U5237 ( .A(n4412), .Y(n4407) );
INVX2TS U5238 ( .A(n4418), .Y(n4403) );
INVX2TS U5239 ( .A(n4410), .Y(n4405) );
BUFX3TS U5240 ( .A(n4412), .Y(n4409) );
INVX2TS U5241 ( .A(n4410), .Y(n4408) );
INVX2TS U5242 ( .A(n4415), .Y(n4417) );
BUFX3TS U5243 ( .A(n4412), .Y(n4429) );
INVX2TS U5244 ( .A(n4415), .Y(n4413) );
BUFX3TS U5245 ( .A(n4422), .Y(n4425) );
INVX2TS U5246 ( .A(n4415), .Y(n4411) );
BUFX3TS U5247 ( .A(n4422), .Y(n4416) );
INVX2TS U5248 ( .A(n4415), .Y(n4428) );
BUFX3TS U5249 ( .A(n4412), .Y(n4424) );
BUFX3TS U5250 ( .A(n4414), .Y(n4420) );
INVX2TS U5251 ( .A(n4415), .Y(n4419) );
INVX2TS U5252 ( .A(n4418), .Y(n4423) );
INVX2TS U5253 ( .A(n4421), .Y(n4426) );
OAI222X1TS U5254 ( .A0(n4465), .A1(n4529), .B0(n4485), .B1(n4466), .C0(n4482), .C1(n4467), .Y(n1621) );
OAI222X1TS U5255 ( .A0(n4465), .A1(n4532), .B0(n1960), .B1(n4466), .C0(n4481), .C1(n4467), .Y(n1620) );
OAI222X1TS U5256 ( .A0(n4465), .A1(n4487), .B0(n4530), .B1(n4466), .C0(n1988), .C1(n4467), .Y(n1619) );
AOI21X1TS U5257 ( .A0(n4431), .A1(intDX_EWSW[63]), .B0(n4430), .Y(n4433) );
BUFX3TS U5258 ( .A(n4629), .Y(n4459) );
INVX2TS U5259 ( .A(n4459), .Y(n4436) );
INVX2TS U5260 ( .A(n4459), .Y(n4438) );
BUFX3TS U5261 ( .A(n4458), .Y(n4437) );
INVX2TS U5262 ( .A(n4459), .Y(n4440) );
BUFX3TS U5263 ( .A(n4458), .Y(n4439) );
INVX2TS U5264 ( .A(n4459), .Y(n4442) );
BUFX3TS U5265 ( .A(n4464), .Y(n4450) );
BUFX3TS U5266 ( .A(n4473), .Y(n4443) );
INVX2TS U5267 ( .A(n4459), .Y(n4445) );
BUFX3TS U5268 ( .A(n4459), .Y(n4446) );
INVX2TS U5269 ( .A(n4475), .Y(n4453) );
INVX2TS U5270 ( .A(n4459), .Y(n4451) );
INVX2TS U5271 ( .A(n4452), .Y(n4476) );
CLKBUFX2TS U5272 ( .A(n4629), .Y(n4473) );
INVX2TS U5273 ( .A(n4473), .Y(n4455) );
BUFX3TS U5274 ( .A(n4464), .Y(n4454) );
INVX2TS U5275 ( .A(n4458), .Y(n4457) );
BUFX3TS U5276 ( .A(n4464), .Y(n4456) );
INVX2TS U5277 ( .A(n4458), .Y(n4461) );
BUFX3TS U5278 ( .A(n4459), .Y(n4460) );
INVX2TS U5279 ( .A(n4473), .Y(n4463) );
BUFX3TS U5280 ( .A(n4464), .Y(n4462) );
INVX2TS U5281 ( .A(n4473), .Y(n4471) );
BUFX3TS U5282 ( .A(n4464), .Y(n4470) );
OAI222X1TS U5283 ( .A0(n4467), .A1(n4529), .B0(n1978), .B1(n4466), .C0(n4482), .C1(n4465), .Y(n1292) );
OAI222X1TS U5284 ( .A0(n4467), .A1(n4532), .B0(n4488), .B1(n4466), .C0(n4481), .C1(n4465), .Y(n1291) );
OAI222X1TS U5285 ( .A0(n4467), .A1(n4487), .B0(n1964), .B1(n4466), .C0(n1988), .C1(n4465), .Y(n1290) );
INVX2TS U5286 ( .A(n4473), .Y(n4474) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk10.tcl_syn.sdf");
endmodule
|
/*
* Read rotary/quadrature encoder using the clock
*
*/
module quadrature_decoder(
CLOCK,
RESET,
A,
B,
COUNT_ENABLE,
DIRECTION,
SPEED
);
input CLOCK, RESET, A, B;
output COUNT_ENABLE;
output DIRECTION;
output [3:0] SPEED;
reg [2:0] A_delayed;
reg [2:0] B_delayed;
always @(posedge CLOCK or posedge RESET) begin
if (RESET) begin
A_delayed <= 0;
end else begin
A_delayed <= {A_delayed[1:0], A};
end
end
always @(posedge CLOCK or posedge RESET) begin
if (RESET) begin
B_delayed <= 0;
end else begin
B_delayed <= {B_delayed[1:0], B};
end
end
assign COUNT_ENABLE = A_delayed[1] ^ A_delayed[2] ^ B_delayed[1] ^ B_delayed[2];
assign DIRECTION = A_delayed[1] ^ B_delayed[2];
assign SPEED = 4'd0;
/*
wire count_enable = A_delayed[1] ^ A_delayed[2] ^ B_delayed[1] ^ B_delayed[2];
wire count_direction = A_delayed[1] ^ B_delayed[2];
reg [31:0] total;
always @(posedge CLOCK or posedge RESET) begin
if (RESET) begin
total <= 0;
end
else if (count_enable) begin
// only want a final count between 0 & 27 (x4 for the clicks)
if (count_direction && total < 109) begin
total <= total+1;
end
else if (total > 0) begin
total <= total-1;
end
end
end
wire [31:0] clicks;
assign clicks = total >> 2; // divide by 4 as the encoder has 4 edges per "click"
assign COUNT = clicks[7:0];
*/
endmodule
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: FIFO_DETECTION_YN.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module FIFO_DETECTION_YN (
clock,
data,
rdreq,
sclr,
wrreq,
empty,
full,
q);
input clock;
input [109:0] data;
input rdreq;
input sclr;
input wrreq;
output empty;
output full;
output [109:0] q;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "8"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "0"
// Retrieval info: PRIVATE: Width NUMERIC "110"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "110"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "8"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "110"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "3"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 110 0 INPUT NODEFVAL "data[109..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 110 0 OUTPUT NODEFVAL "q[109..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 110 0 data 0 0 110 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 110 0 @q 0 0 110 0
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_DETECTION_YN.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_DETECTION_YN.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_DETECTION_YN.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_DETECTION_YN.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_DETECTION_YN_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_DETECTION_YN_bb.v TRUE
|
//-----------------------------------------------------------------------------
// File : wb_slave_mem_master.v
// Creation date : 27.07.2017
// Creation time : 14:40:19
// Description : Used to test wishbone cpu wrapper from both master and slave side.
// Created by : TermosPullo
// Tool : Kactus2 3.4.110 32-bit
// Plugin : Verilog generator 2.0e
// This file was generated based on IP-XACT component tut.fi:communication.bridge.test:wb_cpu.bench:1.0
// whose XML file is D:/kactus2Repos/ipxactexamplelib/tut.fi/communication.bridge.test/wb_cpu.bench/1.0/wb_cpu.bench.1.0.xml
//-----------------------------------------------------------------------------
module wb_slave_mem_master #(
parameter ADDR_WIDTH = 16, // The width of the address.
parameter DATA_WIDTH = 32, // The width of both input and output data.
parameter DATA_COUNT = 8, // How many values there are in the register array.
parameter BASE_ADDRESS = 'h0F00 // The first referred address of the master.
) (
// Interface: memory_interface
// Used to test the bridge from controller side.
input [DATA_WIDTH-1:0] mem_data_i, // Data to bridge.
input mem_slave_rdy, // Bridge has executed the transfer.
output reg [ADDR_WIDTH-1:0] mem_address_o, // Target address of a peripheral operation.
output reg [DATA_WIDTH-1:0] mem_data_o, // Data from bridge.
output reg mem_master_rdy, // Data is provided and transfer can be executed.
output reg mem_we_o, // Controllers writes = 1, Controller reads = 0.
// Interface: wb_slave
// Used to test the bridge from the slave side.
input [ADDR_WIDTH-1:0] wb_adr_i, // The address of the data.
input wb_cyc_i, // Asserted by master for transfer.
input [DATA_WIDTH-1:0] wb_dat_i, // Data from master to slave.
input wb_stb_i, // Asserted, when this specific slave is selected.
input wb_we_i, // Write = 1, Read = 0.
output reg wb_ack_o, // Slave asserts acknowledge.
output reg [DATA_WIDTH-1:0] wb_dat_o, // Data from slave to master.
output reg wb_err_o, // Indicates abnormal cycle termination.
// Interface: wb_system
// Grouping for wishbone system signals. The clock and reset are used for all logic
// in this module.
input clk_i, // The mandatory clock, as this is synchronous logic.
input rst_i // The mandatory reset, as this is synchronous logic.
);
// WARNING: EVERYTHING ON AND ABOVE THIS LINE MAY BE OVERWRITTEN BY KACTUS2!!!
localparam AUB = 8;
localparam AU_IN_DATA = DATA_WIDTH/AUB;
// The master state.
reg [1:0] master_state;
// The available states.
parameter [1:0]
S_MASTER_INIT_WRITE = 2'd0,
S_MASTER_WAIT_WRITE = 2'd1,
S_MASTER_INIT_READ = 2'd2,
S_MASTER_WAIT_READ = 2'd3;
reg [DATA_WIDTH-1:0] test_values [DATA_COUNT-1:0];
// Used to index data to data io.
reg [DATA_COUNT:0] value_iterator;
always @(posedge clk_i or posedge rst_i) begin
if(rst_i == 1'b1) begin
// Initialize test_values with data.
test_values[0] = 32'h00000000;
test_values[1] = 32'h10001111;
test_values[2] = 32'h20002222;
test_values[3] = 32'h30003333;
test_values[4] = 32'h40004444;
test_values[5] = 32'h50005555;
test_values[6] = 32'h60006666;
test_values[7] = 32'h70007777;
// Start with testing write.
master_state <= S_MASTER_INIT_WRITE;
// Outputs are zero by default.
mem_address_o <= 0;
mem_data_o <= 0;
mem_master_rdy <= 0;
mem_we_o <= 0;
value_iterator <= 0;
end
else begin
if (master_state == S_MASTER_INIT_WRITE) begin
mem_master_rdy <= 1;
mem_we_o <= 1;
mem_data_o <= test_values[value_iterator];
master_state <= S_MASTER_WAIT_WRITE;
mem_address_o <= ( value_iterator * AU_IN_DATA ) + BASE_ADDRESS;
end
else if (master_state == S_MASTER_WAIT_WRITE) begin
mem_master_rdy <= 0;
if ( mem_slave_rdy == 1 ) begin
master_state <= S_MASTER_INIT_READ;
end
end
else if (master_state == S_MASTER_INIT_READ) begin
mem_master_rdy <= 1;
mem_we_o <= 0;
master_state <= S_MASTER_WAIT_READ;
mem_address_o <= ( value_iterator * AU_IN_DATA ) + BASE_ADDRESS;
end
else if (master_state == S_MASTER_WAIT_READ) begin
mem_master_rdy <= 0;
if ( mem_slave_rdy == 1 ) begin
master_state <= S_MASTER_INIT_WRITE;
// It was read from the same address as was written, so it should be the same data.
if (test_values[value_iterator] != mem_data_i) begin
$display("ERROR: Wrong answer from wrapper: %X Expected: %X", mem_data_i, test_values[value_iterator]);
$stop;
end
if (value_iterator >= DATA_COUNT) begin
$display("SIMULATION COMPLETE");
$stop;
end
value_iterator <= value_iterator + 1;
end
end
else
$display("ERROR: Unkown master_state: %d", master_state);
end
end
// Used to index AUBs to data io.
integer memory_index;
// The slave state.
reg [0:0] slave_state;
// The available states.
parameter [0:0]
S_WAIT = 1'd0, // Waiting for cyc_i & stb_i
S_DEASSERT = 1'd1; // Deassert acknowledgement.
localparam MEMORY_SIZE = DATA_COUNT*4;
reg [AUB-1:0] memory [MEMORY_SIZE-1:0];
always @(posedge clk_i or posedge rst_i) begin
if(rst_i == 1'b1) begin
wb_ack_o <= 0; // Obviously, there is nothing to acknowledge by default.
wb_dat_o <= 0; // No output by default.
wb_err_o <= 0; // No error by default.
slave_state <= S_WAIT; // Wait signals from the masters at reset.
end
else begin
if (slave_state == S_WAIT) begin
// Wait signal from the master.
if (wb_cyc_i == 1 && wb_stb_i == 1) begin
// Master ok, check the address.
if (wb_adr_i < BASE_ADDRESS + MEMORY_SIZE && wb_adr_i >= BASE_ADDRESS) begin
// The specified address in accessible -> proceed.
wb_ack_o <= 1;
if (wb_we_i == 1) begin
// Writing: Pick every byte from the input and place them to correct addresses.
for (memory_index = 0; memory_index < AU_IN_DATA; memory_index = memory_index + 1) begin
memory[wb_adr_i - BASE_ADDRESS + memory_index] <= wb_dat_i[(memory_index*AUB)+:AUB];
end
end
else begin
// Reading: Pick every byte from correct addresses and place them to the output.
for (memory_index = 0; memory_index < AU_IN_DATA; memory_index = memory_index + 1) begin
wb_dat_o[(memory_index*AUB)+:AUB] <= memory[wb_adr_i - BASE_ADDRESS + memory_index];
end
end
end
else begin
// The specified address out-of-scope -> error!
wb_err_o <= 1;
end
// Next thing is to deassert.
slave_state <= S_DEASSERT;
end
end
else if (slave_state == S_DEASSERT) begin
// Deassert acknowlegement, get ready to receive next one.
wb_ack_o <= 0;
wb_err_o <= 0;
slave_state <= S_WAIT;
end
else
$display("ERROR: Unkown slave_state: %d", slave_state);
end
end
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 18.1.0 Build 625 09/12/2018 SJ Lite Edition
// ************************************************************
//Copyright (C) 2018 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll (
areset,
inclk0,
c0,
locked);
input areset;
input inclk0;
output c0;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] sub_wire2 = 1'h0;
wire [4:0] sub_wire3;
wire sub_wire5;
wire sub_wire0 = inclk0;
wire [1:0] sub_wire1 = {sub_wire2, sub_wire0};
wire [0:0] sub_wire4 = sub_wire3[0:0];
wire c0 = sub_wire4;
wire locked = sub_wire5;
altpll altpll_component (
.areset (areset),
.inclk (sub_wire1),
.clk (sub_wire3),
.locked (sub_wire5),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 4,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 41666,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "96.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "24.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "96.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "41666"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Microsoft Research Asia
// Engineer: Jiansong Zhang
//
// Create Date: 21:54:12 04/26/2010
// Design Name: Sora_FRL_RCB
// Module Name: Sora_FRL_RCB
// Project Name:
// Target Devices: Virtex5 LX50T
// Tool versions: ISE10.1.03
// Description: top of Sora FRL module, this is an implementation of Sora fast radio link. Sora FRL is bi-directional that there're
// both transmitter and reciver in this module.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
//More explanantion of IOs is available below
module Sora_FRL_RCB(
//////// Sora FRL interface to FPGA pins ////////
// inputs
input CLK_I_p, //CLK2_p,
input CLK_I_n, //CLK2_n,
input [3:0] DATA_IN_p,
input [3:0] DATA_IN_n,
input MSG_IN_p,
input MSG_IN_n,
input STATUS_IN_p,
input STATUS_IN_n,
// outputs
output CLK_O_p, //CLK1_p,
output CLK_O_n, //CLK1_n,
output [3:0] DATA_OUT_p,
output [3:0] DATA_OUT_n,
output MSG_OUT_p,
output MSG_OUT_n,
output STATUS_OUT_p,
output STATUS_OUT_n,
//////// signals to FPGA internal logic ////////
// reset from FPGA fabric
input rst_in_internal,
output rst_out_internal,
output CLKDIV_R,
// data input from internal logic
input SEND_EN,
input [31:0] DATA_INT_IN,
output RDEN_DATA_INT_IN,
// control message input from internal logic
input [39:0] MSG_INT_IN,
input EMPTY_MSG_INT_IN,
output RDEN_MSG_INT_IN,
// data output to internal logic
output [31:0] DATA_INT_OUT,
output reg WREN_DATA_INT_OUT,
// state message output to internal logic
// modified by Jiansong, 2010-5-27, we do not use FIFO to buf MSG_INT_OUT
output [31:0] MSG_INT_OUT_Data,
output [7:0] MSG_INT_OUT_Addr,
output MSG_Valid,
// debug info
output reg [31:0] TXMSG_MISS_cnt,
output reg [31:0] TXMSG_PASS_cnt,
output Radio_status_error, // indicates error in received status signal from radio moudle
output Sora_FRL_linkup,
output [1:0] LED
);
wire CLK_R;
wire ALMOSTEMPTY, ALMOSTFULL;
wire [31:0] DATA;
wire WREN;
wire [3:0] OSER_OQ;
wire [31:0] DATA_IN;
wire [7:0] MSG_IN;
wire Lock_Status_TX;
wire Lock_Status_RX;
wire LED_CLOCK_0;
wire LED_CLOCK_1;
wire LED_CLOCK_2;
wire LED_CLOCK_3;
wire CLK180;
wire [39:0] MSG;
wire OSER_OQ_MSG,ack_r_one,nack_r_one,BACK_WRONG, BACK_RIGHT;
wire STATUS_IN;
wire STATUS_OUT;
wire SEND_EN_TX;
wire DATA_SEND_EN, MSG_WREN;
// Status signal from adapter
wire rst_in_status;
wire FIFO_FULL_RX;
wire TRAINING_DONE_RCB2Adapter;
wire IDLE_RX;
wire Status_RX_error;
wire STATUS_OUT_MSG_buf;
wire msg_r_p_one;
wire DATA_ALMOSTEMPTY;
// Status signal to adapter
wire TRAINING_DONE_Adapter2RCB;
/////////////////// reset logic /////////////////
wire RST;
// FRL local logic reset
reg [31:0] rst_counter;
reg reset_frl_local;
initial
rst_counter = 32'h0000_0000;
always @ (posedge CLKDIV_R) begin
// a local reset signal is triggered
if (rst_in_internal | rst_in_status) begin
rst_counter <= 32'h0000_0000;
reset_frl_local <= 1'b1;
end else if(rst_counter < 32'h0000_1130) begin // 100us
rst_counter <= rst_counter + 32'h0000_0001;
reset_frl_local <= 1'b1;
end else
reset_frl_local <= 1'b0;
end
// propagate reset signal from status line to RCB internal logic
assign rst_out_internal = rst_in_status;
assign RST = rst_in_internal | rst_in_status | reset_frl_local;
//////////////////////////////////////////////////
assign Sora_FRL_linkup = TRAINING_DONE_Adapter2RCB & TRAINING_DONE_RCB2Adapter;
assign DATA_SEND_EN = ~FIFO_FULL_RX & SEND_EN & TRAINING_DONE_RCB2Adapter; // modified by Jiansong, 2010-5-25, add training done as condition
always@(posedge CLKDIV_R) WREN_DATA_INT_OUT <= ~DATA_ALMOSTEMPTY;
// Determine whether TX will send DATA or MSG.
assign LED[0] = LED_CLOCK_0;
assign LED[1] = LED_CLOCK_1;
Sora_FRL_STATUS_decoder Sora_FRL_STATUS_decoder_RCB_inst(
.clk (CLKDIV_R),
// .rst (rst_in_internal), // no need for a reset signal since there's no internal state
// input from STATUS line
.status_in (STATUS_IN),
// four output states
.RST_state (rst_in_status),
.TRAININGDONE_state (TRAINING_DONE_RCB2Adapter),
.IDLE_state (IDLE_RX), // this signal is used for monitoring
.FIFOFULL_state (FIFO_FULL_RX),
// error state
.error_state (Status_RX_error)
);
Sora_FRL_STATUS_encoder Sora_FRL_STATUS_encoder_RCB_inst(
.clk (CLKDIV_R),
// .rst (rst_in_internal), // reset the Status encoder's state machine
// input from STATUS line
.status_out (STATUS_OUT),
// four output states
// .RST_signal (rst_in_internal | reset_frl_local), // this signal is generated from internal fabric
.RST_signal (rst_in_internal), // this signal is generated from internal fabric
.TRAININGDONE_signal (TRAINING_DONE_Adapter2RCB),
.IDLE_signal (rst_in_status), // this signal informs Status encoder to change its state to IDLE,
// it happens when an RST state is received from Status line
.FIFOFULL_signal (1'b0) // FIFO should not be full on RX path
);
RCB_FRL_TX Sora_FRL_RCB_TX_data_inst (
.RST (RST),
.CLK (CLK_R),
.CLKDIV (CLKDIV_R),
.DATA_IN (DATA_INT_IN),
.OSER_OQ (OSER_OQ),
.SEND_EN (DATA_SEND_EN),
.TRAINING_DONE (TRAINING_DONE_RCB2Adapter),
.RDEN (RDEN_DATA_INT_IN)
);
// debug info
wire TXMSG_MISS;
wire TXMSG_PASS;
always@(posedge CLKDIV_R)begin
if(RST)begin
TXMSG_MISS_cnt <= 32'h0000_0000;
TXMSG_PASS_cnt <= 32'h0000_0000;
end else if(TXMSG_MISS) begin
TXMSG_MISS_cnt <= TXMSG_MISS_cnt + 32'h0000_0001;
TXMSG_PASS_cnt <= TXMSG_PASS_cnt;
end else if(TXMSG_PASS) begin
TXMSG_MISS_cnt <= TXMSG_MISS_cnt;
TXMSG_PASS_cnt <= TXMSG_PASS_cnt + 32'h0000_0001;
end else begin
TXMSG_MISS_cnt <= TXMSG_MISS_cnt;
TXMSG_PASS_cnt <= TXMSG_PASS_cnt;
end
end
RCB_FRL_TX_MSG Sora_FRL_RCB_TX_MSG_inst (
.rst (RST),
.clk (CLK_R),
.clkdiv (CLKDIV_R),
.data_in (MSG_INT_IN[39:0]),
.empty (EMPTY_MSG_INT_IN),
.rden (RDEN_MSG_INT_IN),
.OSER_OQ (OSER_OQ_MSG),
.ack_r_one (ack_r_one), //input feedback from decode module
.nack_r_one (nack_r_one),
.txmsg_miss_one(TXMSG_MISS), // one cycle signal to indicate a TXMSG wasn't correctly received by another Sora-FRL end
.txmsg_pass_one(TXMSG_PASS), // one cycle signal to indicate a TXMSG was correctly received by another Sora-FRL end
.msg_r_p_one (msg_r_p_one),
.msg_r_n_one (msg_r_n_one),
.training_done (TRAINING_DONE_RCB2Adapter)
);
// serial clock output to the 'clock' LVDS channel
// wire TX_CLOCK_PREBUF;
// ODDR #( .DDR_CLK_EDGE("OPPOSITE_EDGE"), .INIT(1'b0), .SRTYPE("ASYNC") )
// ODDR_TX_CLOCK ( .Q(TX_CLOCK_PREBUF), .C(CLK_R), .CE(1'b1), .D1(1'b1), .D2(1'b0), .R(1'b0), .S(1'b0) );
OBUFDS OBUFDS_clock ( .I(CLK_R), .O(CLK_O_p), .OB(CLK_O_n) );
// differential outputs to LVDS channels
OBUFDS OBUFDS_data0 ( .I(OSER_OQ[0]), .O(DATA_OUT_p[0]), .OB(DATA_OUT_n[0]) );
OBUFDS OBUFDS_data1 ( .I(OSER_OQ[1]), .O(DATA_OUT_p[1]), .OB(DATA_OUT_n[1]) );
OBUFDS OBUFDS_data2 ( .I(OSER_OQ[2]), .O(DATA_OUT_p[2]), .OB(DATA_OUT_n[2]) );
OBUFDS OBUFDS_data3 ( .I(OSER_OQ[3]), .O(DATA_OUT_p[3]), .OB(DATA_OUT_n[3]) );
OBUFDS OBUFDS_msg ( .I(OSER_OQ_MSG), .O(MSG_OUT_p), .OB(MSG_OUT_n) );
OBUFDS OBUFDS_status ( .I(STATUS_OUT), .O(STATUS_OUT_p), .OB(STATUS_OUT_n) );
// differential input from the 'status' LVDS channel
IBUFDS #( .DIFF_TERM("FALSE") ) IBUFDS_inst7 ( .I(STATUS_IN_p), .IB(STATUS_IN_n), .O(STATUS_IN) );
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////// clock ///////////////////////////////////////////
// this is a candidate solution, but not used finally because DCM is not stable in this solution:
// the clock source of Sora FRL comes from RAB, that is,
// (1) RAB generates LVDS clock from its local oscillator,
// (2) a serial-rate clock is transmitted together with data channels
// (3) RCB receives the serial-rate clock, using a DCM to generate both serial-rate clock and parallel-rate clock
// the two clocks should be phase synchronized in this way
// (4) both serial-clock and parallel clock are propagated to Iserdes and Oserdes using BUFG
// note: it is not the optimal clock solution since global clock net introduce larger skew than reginal clock net,
// but with current PCB layout, reginal clock solution is not able to be applied since some LVDS channels
// on a same LVDS port are routed to different IO banks (different clcok regions), which should be routed to
// the same IO bank if we use regional clock net (BUFIO can only reach to a single clock region, BUFR can reach
// to its own and two neighbor clock regions)
// differential input from the 'clock' LVDS channel
// wire CLOCK_RX_BUF;
// wire CLOCK_RX_ISERDES_OUT;
// IBUFDS #( .DIFF_TERM("FALSE") ) IBUFDS_inst8 ( .I(CLK_I_p), .IB(CLK_I_n), .O(CLOCK_RX_BUF) );
// //IDELAY IN CLOCK PATH
// IODELAY #( .IDELAY_TYPE("FIXED"), .IDELAY_VALUE(0), .ODELAY_VALUE(0), .REFCLK_FREQUENCY(200.00), .HIGH_PERFORMANCE_MODE("TRUE") )
// IODELAY_CLOCK_RX ( .DATAOUT(CLOCK_RX_ISERDES_OUT), .IDATAIN(CLOCK_RX_BUF), .ODATAIN(1'b0), .DATAIN(1'b0), .T(),
// .CE(1'b0), .INC(1'b0), .C(1'b0), .RST(RST) );
// BUFG BUFG_input ( .I(CLOCK_RX_ISERDES_OUT), .O(clock_input_global) );
// BUFG BUFG_input ( .I(CLOCK_RX_BUF), .O(clock_input_global) );
//
// DCM_FRL DCM_FRL_inst (
// .CLKIN_IN (clock_input_global),
// .RST_IN (rst_in_internal),
// .CLKDV_OUT (CLKDIV_R),
// .CLK0_OUT (CLK_R),
// .LOCKED_OUT ()
// );
// clock solution, it seems serial-clock and parallel clock are not synchronized in phase, the highest frequency will be limited therefore
wire CLK_R1, CLK_R_pre;
// IBUFDS #( .DIFF_TERM("FALSE") ) IBUFDS_inst8 ( .I(CLK_I_p), .IB(CLK_I_n), .O(CLK_R) );
IBUFDS #( .DIFF_TERM("FALSE") ) IBUFDS_inst8 ( .I(CLK_I_p), .IB(CLK_I_n), .O(CLK_R_pre) );
// BUFR #( .BUFR_DIVIDE("1"), .SIM_DEVICE("VIRTEX5") )
// BUFIO_CLK_R ( .O(CLK_R1), .CE(1'b1), .CLR(1'b0), .I(CLK_R_pre) );
// BUFG BUFG_CLK_R (.I(CLK_R1), .O(CLK_R));
BUFG BUFG_CLK_R (.I(CLK_R_pre), .O(CLK_R));
wire CLKDIV_R1;
BUFR #( .BUFR_DIVIDE("4"), .SIM_DEVICE("VIRTEX5") )
// BUFR_inst1( .O(CLKDIV_R1), .CE(1'b1), .CLR(1'b0), .I(CLK_R) );
BUFR_inst1( .O(CLKDIV_R1), .CE(1'b1), .CLR(1'b0), .I(CLK_R_pre) );
BUFG BUFG_CLKDIV_R (.I(CLKDIV_R1), .O(CLKDIV_R));
//////////////////////////////// clock ///////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
RCB_FRL_DDR_8TO1_16CHAN_RX Sora_FRL_RCB_RX_ISerDes_and_Training_inst (
.RXCLK (CLK_R),
.RXCLKDIV (CLKDIV_R),
.RESET (RST),
.IDLY_RESET (RST),
.DATA_RX_P ({DATA_IN_p,MSG_IN_p}),
.DATA_RX_N ({DATA_IN_n,MSG_IN_n}),
.INC_PAD (1'b0),
.DEC_PAD (1'b0),
.DATA_FROM_ISERDES ({DATA_IN[31:0],MSG_IN[7:0]}),
.BITSLIP_PAD (1'b0),
.TAP_00 (),
.TAP_01 (),
.TAP_02 (),
.TAP_03 (),
.TAP_04 (),
.TAP_CLK (),
.TRAINING_DONE (TRAINING_DONE_Adapter2RCB)
);
RCB_FRL_RX Sora_FRL_RCB_RX_data_inst (
.CLKDIV (CLKDIV_R),
// .RDCLK (CLKDIV_R),
.RST (RST),
.DATA_IN (DATA_IN),
.DATA_OUT (DATA_INT_OUT),
.RDEN (~DATA_ALMOSTEMPTY),
.ALMOSTEMPTY (DATA_ALMOSTEMPTY)
// .fifo_WREN (fifo_WREN)
);
assign MSG_Valid = msg_r_p_one; // added by jiansong, 2010-5-27
RCB_FRL_RX_MSG Sora_FRL_RCB_RX_MSG_inst (
.CLKDIV (CLKDIV_R),
.RST (RST),
.DATA_IN (MSG_IN[7:0]),
.DATA_OUT ({MSG_INT_OUT_Addr[7:0],MSG_INT_OUT_Data[31:0]}),
.msg_r_n_one (msg_r_n_one),
.msg_r_p_one (msg_r_p_one),
.nack_r_one (nack_r_one),
.ack_r_one (ack_r_one)
);//these are for the radio board
RCB_FRL_LED_Clock RCB_FRL_LED_Clock_inst (
.Test_Clock_in(CLK_R),
.LED_Clock_out(LED_CLOCK_0),
.RST(RST)
);
RCB_FRL_LED_Clock_DIV RCB_FRL_LED_Clock_DIV_inst (
.Test_Clock_in(CLKDIV_R),
.LED_Clock_out(LED_CLOCK_1),
.RST(RST)
);
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : bank_common.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Common block for the bank machines. Bank_common computes various
// items that cross all of the bank machines. These values are then
// fed back to all of the bank machines. Most of these values have
// to do with a row machine figuring out where it belongs in a queue.
`timescale 1 ps / 1 ps
module mig_7series_v2_3_bank_common #
(
parameter TCQ = 100,
parameter BM_CNT_WIDTH = 2,
parameter LOW_IDLE_CNT = 1,
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2,
parameter nOP_WAIT = 0,
parameter nRFC = 44,
parameter nXSDLL = 512,
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter CWL = 5,
parameter tZQCS = 64
)
(/*AUTOARG*/
// Outputs
accept_internal_r, accept_ns, accept, periodic_rd_insert,
periodic_rd_ack_r, accept_req, rb_hit_busy_cnt, idle, idle_cnt, order_cnt,
adv_order_q, bank_mach_next, op_exit_grant, low_idle_cnt_r, was_wr,
was_priority, maint_wip_r, maint_idle, insert_maint_r,
// Inputs
clk, rst, idle_ns, init_calib_complete, periodic_rd_r, use_addr,
rb_hit_busy_r, idle_r, ordered_r, ordered_issued, head_r, end_rtp,
passing_open_bank, op_exit_req, start_pre_wait, cmd, hi_priority, maint_req_r,
maint_zq_r, maint_sre_r, maint_srx_r, maint_hit, bm_end,
slot_0_present, slot_1_present
);
function integer clogb2 (input integer size); // ceiling logb2
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
localparam ZERO = 0;
localparam ONE = 1;
localparam [BM_CNT_WIDTH-1:0] BM_CNT_ZERO = ZERO[0+:BM_CNT_WIDTH];
localparam [BM_CNT_WIDTH-1:0] BM_CNT_ONE = ONE[0+:BM_CNT_WIDTH];
input clk;
input rst;
input [nBANK_MACHS-1:0] idle_ns;
input init_calib_complete;
wire accept_internal_ns = init_calib_complete && |idle_ns;
output reg accept_internal_r;
always @(posedge clk) accept_internal_r <= accept_internal_ns;
wire periodic_rd_ack_ns;
wire accept_ns_lcl = accept_internal_ns && ~periodic_rd_ack_ns;
output wire accept_ns;
assign accept_ns = accept_ns_lcl;
reg accept_r;
always @(posedge clk) accept_r <= #TCQ accept_ns_lcl;
// Wire to user interface informing user that the request has been accepted.
output wire accept;
assign accept = accept_r;
`ifdef MC_SVA
property none_idle;
@(posedge clk) (init_calib_complete && ~|idle_r);
endproperty
all_bank_machines_busy: cover property (none_idle);
`endif
// periodic_rd_insert tells everyone to mux in the periodic read.
input periodic_rd_r;
reg periodic_rd_ack_r_lcl;
reg periodic_rd_cntr_r ;
always @(posedge clk) begin
if (rst) periodic_rd_cntr_r <= #TCQ 1'b0;
else if (periodic_rd_r && periodic_rd_ack_r_lcl)
periodic_rd_cntr_r <= #TCQ ~periodic_rd_cntr_r;
end
wire internal_periodic_rd_ack_r_lcl = (periodic_rd_cntr_r && periodic_rd_ack_r_lcl);
// wire periodic_rd_insert_lcl = periodic_rd_r && ~periodic_rd_ack_r_lcl;
wire periodic_rd_insert_lcl = periodic_rd_r && ~internal_periodic_rd_ack_r_lcl;
output wire periodic_rd_insert;
assign periodic_rd_insert = periodic_rd_insert_lcl;
// periodic_rd_ack_r acknowledges that the read has been accepted
// into the queue.
assign periodic_rd_ack_ns = periodic_rd_insert_lcl && accept_internal_ns;
always @(posedge clk) periodic_rd_ack_r_lcl <= #TCQ periodic_rd_ack_ns;
output wire periodic_rd_ack_r;
assign periodic_rd_ack_r = periodic_rd_ack_r_lcl;
// accept_req tells all q entries that a request has been accepted.
input use_addr;
wire accept_req_lcl = periodic_rd_ack_r_lcl || (accept_r && use_addr);
output wire accept_req;
assign accept_req = accept_req_lcl;
// Count how many non idle bank machines hit on the rank and bank.
input [nBANK_MACHS-1:0] rb_hit_busy_r;
output reg [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt;
integer i;
always @(/*AS*/rb_hit_busy_r) begin
rb_hit_busy_cnt = BM_CNT_ZERO;
for (i = 0; i < nBANK_MACHS; i = i + 1)
if (rb_hit_busy_r[i]) rb_hit_busy_cnt = rb_hit_busy_cnt + BM_CNT_ONE;
end
// Count the number of idle bank machines.
input [nBANK_MACHS-1:0] idle_r;
output reg [BM_CNT_WIDTH-1:0] idle_cnt;
always @(/*AS*/idle_r) begin
idle_cnt = BM_CNT_ZERO;
for (i = 0; i < nBANK_MACHS; i = i + 1)
if (idle_r[i]) idle_cnt = idle_cnt + BM_CNT_ONE;
end
// Report an overall idle status
output idle;
assign idle = init_calib_complete && &idle_r;
// Count the number of bank machines in the ordering queue.
input [nBANK_MACHS-1:0] ordered_r;
output reg [BM_CNT_WIDTH-1:0] order_cnt;
always @(/*AS*/ordered_r) begin
order_cnt = BM_CNT_ZERO;
for (i = 0; i < nBANK_MACHS; i = i + 1)
if (ordered_r[i]) order_cnt = order_cnt + BM_CNT_ONE;
end
input [nBANK_MACHS-1:0] ordered_issued;
output wire adv_order_q;
assign adv_order_q = |ordered_issued;
// Figure out which bank machine is going to accept the next request.
input [nBANK_MACHS-1:0] head_r;
wire [nBANK_MACHS-1:0] next = idle_r & head_r;
output reg[BM_CNT_WIDTH-1:0] bank_mach_next;
always @(/*AS*/next) begin
bank_mach_next = BM_CNT_ZERO;
for (i = 0; i <= nBANK_MACHS-1; i = i + 1)
if (next[i]) bank_mach_next = i[BM_CNT_WIDTH-1:0];
end
input [nBANK_MACHS-1:0] end_rtp;
input [nBANK_MACHS-1:0] passing_open_bank;
input [nBANK_MACHS-1:0] op_exit_req;
output wire [nBANK_MACHS-1:0] op_exit_grant;
output reg low_idle_cnt_r = 1'b0;
input [nBANK_MACHS-1:0] start_pre_wait;
generate
// In support of open page mode, the following logic
// keeps track of how many "idle" bank machines there
// are. In this case, idle means a bank machine is on
// the idle list, or is in the process of precharging and
// will soon be idle.
if (nOP_WAIT == 0) begin : op_mode_disabled
assign op_exit_grant = {nBANK_MACHS{1'b0}};
end
else begin : op_mode_enabled
reg [BM_CNT_WIDTH:0] idle_cnt_r;
reg [BM_CNT_WIDTH:0] idle_cnt_ns;
always @(/*AS*/accept_req_lcl or idle_cnt_r or passing_open_bank
or rst or start_pre_wait)
if (rst) idle_cnt_ns = nBANK_MACHS;
else begin
idle_cnt_ns = idle_cnt_r - accept_req_lcl;
for (i = 0; i <= nBANK_MACHS-1; i = i + 1) begin
idle_cnt_ns = idle_cnt_ns + passing_open_bank[i];
end
idle_cnt_ns = idle_cnt_ns + |start_pre_wait;
end
always @(posedge clk) idle_cnt_r <= #TCQ idle_cnt_ns;
wire low_idle_cnt_ns = (idle_cnt_ns <= LOW_IDLE_CNT[0+:BM_CNT_WIDTH]);
always @(posedge clk) low_idle_cnt_r <= #TCQ low_idle_cnt_ns;
// This arbiter determines which bank machine should transition
// from open page wait to precharge. Ideally, this process
// would take the oldest waiter, but don't have any reasonable
// way to implement that. Instead, just use simple round robin
// arb with the small enhancement that the most recent bank machine
// to enter open page wait is given lowest priority in the arbiter.
wire upd_last_master = |end_rtp; // should be one bit set at most
mig_7series_v2_3_round_robin_arb #
(.WIDTH (nBANK_MACHS))
op_arb0
(.grant_ns (op_exit_grant[nBANK_MACHS-1:0]),
.grant_r (),
.upd_last_master (upd_last_master),
.current_master (end_rtp[nBANK_MACHS-1:0]),
.clk (clk),
.rst (rst),
.req (op_exit_req[nBANK_MACHS-1:0]),
.disable_grant (1'b0));
end
endgenerate
// Register some command information. This information will be used
// by the bank machines to figure out if there is something behind it
// in the queue that require hi priority.
input [2:0] cmd;
output reg was_wr;
always @(posedge clk) was_wr <= #TCQ
cmd[0] && ~(periodic_rd_r && ~periodic_rd_ack_r_lcl);
input hi_priority;
output reg was_priority;
always @(posedge clk) begin
if (hi_priority)
was_priority <= #TCQ 1'b1;
else
was_priority <= #TCQ 1'b0;
end
// DRAM maintenance (refresh and ZQ) and self-refresh controller
input maint_req_r;
reg maint_wip_r_lcl;
output wire maint_wip_r;
assign maint_wip_r = maint_wip_r_lcl;
wire maint_idle_lcl;
output wire maint_idle;
assign maint_idle = maint_idle_lcl;
input maint_zq_r;
input maint_sre_r;
input maint_srx_r;
input [nBANK_MACHS-1:0] maint_hit;
input [nBANK_MACHS-1:0] bm_end;
wire start_maint;
wire maint_end;
generate begin : maint_controller
// Idle when not (maintenance work in progress (wip), OR maintenance
// starting tick).
assign maint_idle_lcl = ~(maint_req_r || maint_wip_r_lcl);
// Maintenance work in progress starts with maint_reg_r tick, terminated
// with maint_end tick. maint_end tick is generated by the RFC/ZQ/XSDLL timer
// below.
wire maint_wip_ns =
~rst && ~maint_end && (maint_wip_r_lcl || maint_req_r);
always @(posedge clk) maint_wip_r_lcl <= #TCQ maint_wip_ns;
// Keep track of which bank machines hit on the maintenance request
// when the request is made. As bank machines complete, an assertion
// of the bm_end signal clears the correspoding bit in the
// maint_hit_busies_r vector. Eventually, all bits should clear and
// the maintenance operation will proceed. ZQ and self-refresh hit on all
// non idle banks. Refresh hits only on non idle banks with the same rank as
// the refresh request.
wire [nBANK_MACHS-1:0] clear_vector = {nBANK_MACHS{rst}} | bm_end;
wire [nBANK_MACHS-1:0] maint_zq_hits = {nBANK_MACHS{maint_idle_lcl}} &
(maint_hit | {nBANK_MACHS{maint_zq_r}}) & ~idle_ns;
wire [nBANK_MACHS-1:0] maint_sre_hits = {nBANK_MACHS{maint_idle_lcl}} &
(maint_hit | {nBANK_MACHS{maint_sre_r}}) & ~idle_ns;
reg [nBANK_MACHS-1:0] maint_hit_busies_r;
wire [nBANK_MACHS-1:0] maint_hit_busies_ns =
~clear_vector & (maint_hit_busies_r | maint_zq_hits | maint_sre_hits);
always @(posedge clk) maint_hit_busies_r <= #TCQ maint_hit_busies_ns;
// Queue is clear of requests conflicting with maintenance.
wire maint_clear = ~maint_idle_lcl && ~|maint_hit_busies_ns;
// Ready to start sending maintenance commands.
wire maint_rdy = maint_clear;
reg maint_rdy_r1;
reg maint_srx_r1;
always @(posedge clk) maint_rdy_r1 <= #TCQ maint_rdy;
always @(posedge clk) maint_srx_r1 <= #TCQ maint_srx_r;
assign start_maint = maint_rdy && ~maint_rdy_r1 || maint_srx_r && ~maint_srx_r1;
end // block: maint_controller
endgenerate
// Figure out how many maintenance commands to send, and send them.
input [7:0] slot_0_present;
input [7:0] slot_1_present;
reg insert_maint_r_lcl;
output wire insert_maint_r;
assign insert_maint_r = insert_maint_r_lcl;
generate begin : generate_maint_cmds
// Count up how many slots are occupied. This tells
// us how many ZQ, SRE or SRX commands to send out.
reg [RANK_WIDTH:0] present_count;
wire [7:0] present = slot_0_present | slot_1_present;
always @(/*AS*/present) begin
present_count = {RANK_WIDTH{1'b0}};
for (i=0; i<8; i=i+1)
present_count = present_count + {{RANK_WIDTH{1'b0}}, present[i]};
end
// For refresh, there is only a single command sent. For
// ZQ, SRE and SRX, each rank present will receive a command. The counter
// below counts down the number of ranks present.
reg [RANK_WIDTH:0] send_cnt_ns;
reg [RANK_WIDTH:0] send_cnt_r;
always @(/*AS*/maint_zq_r or maint_sre_r or maint_srx_r or present_count
or rst or send_cnt_r or start_maint)
if (rst) send_cnt_ns = 4'b0;
else begin
send_cnt_ns = send_cnt_r;
if (start_maint && (maint_zq_r || maint_sre_r || maint_srx_r)) send_cnt_ns = present_count;
if (|send_cnt_ns)
send_cnt_ns = send_cnt_ns - ONE[RANK_WIDTH-1:0];
end
always @(posedge clk) send_cnt_r <= #TCQ send_cnt_ns;
// Insert a maintenance command for start_maint, or when the sent count
// is not zero.
wire insert_maint_ns = start_maint || |send_cnt_r;
always @(posedge clk) insert_maint_r_lcl <= #TCQ insert_maint_ns;
end // block: generate_maint_cmds
endgenerate
// RFC ZQ XSDLL timer. Generates delay from refresh, self-refresh exit or ZQ
// command until the end of the maintenance operation.
// Compute values for RFC, ZQ and XSDLL periods.
localparam nRFC_CLKS = (nCK_PER_CLK == 1) ?
nRFC :
(nCK_PER_CLK == 2) ?
((nRFC/2) + (nRFC%2)) :
// (nCK_PER_CLK == 4)
((nRFC/4) + ((nRFC%4) ? 1 : 0));
localparam nZQCS_CLKS = (nCK_PER_CLK == 1) ?
tZQCS :
(nCK_PER_CLK == 2) ?
((tZQCS/2) + (tZQCS%2)) :
// (nCK_PER_CLK == 4)
((tZQCS/4) + ((tZQCS%4) ? 1 : 0));
localparam nXSDLL_CLKS = (nCK_PER_CLK == 1) ?
nXSDLL :
(nCK_PER_CLK == 2) ?
((nXSDLL/2) + (nXSDLL%2)) :
// (nCK_PER_CLK == 4)
((nXSDLL/4) + ((nXSDLL%4) ? 1 : 0));
localparam RFC_ZQ_TIMER_WIDTH = clogb2(nXSDLL_CLKS + 1);
localparam THREE = 3;
generate begin : rfc_zq_xsdll_timer
reg [RFC_ZQ_TIMER_WIDTH-1:0] rfc_zq_xsdll_timer_ns;
reg [RFC_ZQ_TIMER_WIDTH-1:0] rfc_zq_xsdll_timer_r;
always @(/*AS*/insert_maint_r_lcl or maint_zq_r or maint_sre_r or maint_srx_r
or rfc_zq_xsdll_timer_r or rst) begin
rfc_zq_xsdll_timer_ns = rfc_zq_xsdll_timer_r;
if (rst) rfc_zq_xsdll_timer_ns = {RFC_ZQ_TIMER_WIDTH{1'b0}};
else if (insert_maint_r_lcl) rfc_zq_xsdll_timer_ns = maint_zq_r ?
nZQCS_CLKS :
maint_sre_r ?
{RFC_ZQ_TIMER_WIDTH{1'b0}} :
maint_srx_r ?
nXSDLL_CLKS :
nRFC_CLKS;
else if (|rfc_zq_xsdll_timer_r) rfc_zq_xsdll_timer_ns =
rfc_zq_xsdll_timer_r - ONE[RFC_ZQ_TIMER_WIDTH-1:0];
end
always @(posedge clk) rfc_zq_xsdll_timer_r <= #TCQ rfc_zq_xsdll_timer_ns;
// Based on rfc_zq_xsdll_timer_r, figure out when to release any bank
// machines waiting to send an activate. Need to add two to the end count.
// One because the counter starts a state after the insert_refresh_r, and
// one more because bm_end to insert_refresh_r is one state shorter
// than bm_end to rts_row.
assign maint_end = (rfc_zq_xsdll_timer_r == THREE[RFC_ZQ_TIMER_WIDTH-1:0]);
end // block: rfc_zq_xsdll_timer
endgenerate
endmodule // bank_common
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : 16 by 32 dual port RAM
// File : ram_16x32_dp.v
// Author : Jim Macleod
// Created : 06-April-2005
// RCS File : $Source: /u/Maxwell/hdl/vga/RCS/ram_16x32_dp.v,v $
// Status : $Id: ram_16x32_dp.v,v 1.1 2005/10/11 21:14:15 fbruno Exp fbruno $
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//
//
/////////////////////////////////////////////////////////////////////////////////
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log: ram_16x32_dp.v,v $
// Revision 1.1 2005/10/11 21:14:15 fbruno
// Initial revision
//
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module ram_16x32_dp
(
input [15:0] data,
input wren,
input [4:0] wraddress,
input [4:0] rdaddress,
input wrclock,
input rdclock,
output reg [15:0] q
);
reg [15:0] mem_a [0:31];
always @(posedge wrclock) if(wren) mem_a[wraddress] <= data;
always @(posedge rdclock) q <= mem_a[rdaddress];
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_ctu_clk_sync_mux.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// ------------------------------------------------------------------
/*
module zsoffi_prim (q_l, so, ck, d, se, sd);
output q_l, so;
input ck, d, se, sd;
reg q_r;
always @ (posedge ck)
q_r <= se ? sd : d;
assign q_l = ~q_r;
assign so = q_r;
endmodule
*/
/*
module bw_clk_zgclk_zinv_32x(clkout ,clkin );
output clkout ;
input clkin ;
supply1 vdd ;
supply0 vss ;
nmos n_0_ (clkout ,clkin ,vss );
pmos p_4_ (clkout ,clkin ,vdd );
nmos n_1_ (clkout ,clkin ,vss );
pmos p_5_ (clkout ,clkin ,vdd );
nmos n_2_ (clkout ,clkin ,vss );
nmos ns0 (vdd ,vss ,vss );
nmos ns1 (vdd ,vss ,vss );
pmos p_6_ (clkout ,clkin ,vdd );
pmos ps0 (vdd ,vss ,vdd );
pmos ps1 (vdd ,vss ,vdd );
nmos n_3_ (clkout ,clkin ,vss );
pmos p_7_ (clkout ,clkin ,vdd );
nmos n_4_ (clkout ,clkin ,vss );
pmos p_0_ (clkout ,clkin ,vdd );
nmos n_5_ (clkout ,clkin ,vss );
pmos p_1_ (clkout ,clkin ,vdd );
nmos n_6_ (clkout ,clkin ,vss );
pmos p_2_ (clkout ,clkin ,vdd );
nmos n_7_ (clkout ,clkin ,vss );
pmos p_3_ (clkout ,clkin ,vdd );
endmodule
module bw_clk_zgclk_inv_320x(clkin ,clkout );
output [9:0] clkout ;
input [9:0] clkin ;
bw_clk_zgclk_zinv_32x x2 (
.clkout (clkout[2] ),
.clkin (clkin[2] ) );
bw_clk_zgclk_zinv_32x x3 (
.clkout (clkout[3] ),
.clkin (clkin[3] ) );
bw_clk_zgclk_zinv_32x x4 (
.clkout (clkout[4] ),
.clkin (clkin[4] ) );
bw_clk_zgclk_zinv_32x x5 (
.clkout (clkout[5] ),
.clkin (clkin[5] ) );
bw_clk_zgclk_zinv_32x x6 (
.clkout (clkout[6] ),
.clkin (clkin[6] ) );
bw_clk_zgclk_zinv_32x x7 (
.clkout (clkout[7] ),
.clkin (clkin[7] ) );
bw_clk_zgclk_zinv_32x x8 (
.clkout (clkout[8] ),
.clkin (clkin[8] ) );
bw_clk_zgclk_zinv_32x x9 (
.clkout (clkout[9] ),
.clkin (clkin[9] ) );
bw_clk_zgclk_zinv_32x x0 (
.clkout (clkout[0] ),
.clkin (clkin[0] ) );
bw_clk_zgclk_zinv_32x x1 (
.clkout (clkout[1] ),
.clkin (clkin[1] ) );
endmodule
module bw_clk_gclk_inv_256x(clkout ,clkin );
output clkout ;
input clkin ;
supply1 vdd ;
supply0 vss ;
bw_clk_zgclk_inv_320x x0 (
.clkin ({vss ,vss ,{8 {clkin }} } ),
.clkout ({vdd ,vdd ,{8 {clkout }} } ) );
endmodule
module bw_clk_zcclk_zinv_16x(clkout ,clkin );
output clkout ;
input clkin ;
supply1 vdd ;
supply0 vss ;
pmos p3 (clkout ,clkin ,vdd );
nmos ns0 (vdd ,vss ,vss );
nmos ns1 (vdd ,vss ,vss );
pmos ps0 (vdd ,vss ,vdd );
pmos ps1 (vdd ,vss ,vdd );
nmos n0 (clkout ,clkin ,vss );
nmos n1 (clkout ,clkin ,vss );
nmos n2 (clkout ,clkin ,vss );
nmos n3 (clkout ,clkin ,vss );
pmos p0 (clkout ,clkin ,vdd );
pmos p1 (clkout ,clkin ,vdd );
pmos p2 (clkout ,clkin ,vdd );
endmodule
module bw_clk_zcclk_inv_128x(clkout ,clkin );
output [7:0] clkout ;
input [7:0] clkin ;
bw_clk_zcclk_zinv_16x x2 (
.clkout (clkout[2] ),
.clkin (clkin[2] ) );
bw_clk_zcclk_zinv_16x x3 (
.clkout (clkout[3] ),
.clkin (clkin[3] ) );
bw_clk_zcclk_zinv_16x x4 (
.clkout (clkout[4] ),
.clkin (clkin[4] ) );
bw_clk_zcclk_zinv_16x x5 (
.clkout (clkout[5] ),
.clkin (clkin[5] ) );
bw_clk_zcclk_zinv_16x x6 (
.clkout (clkout[6] ),
.clkin (clkin[6] ) );
bw_clk_zcclk_zinv_16x x7 (
.clkout (clkout[7] ),
.clkin (clkin[7] ) );
bw_clk_zcclk_zinv_16x x0 (
.clkout (clkout[0] ),
.clkin (clkin[0] ) );
bw_clk_zcclk_zinv_16x x1 (
.clkout (clkout[1] ),
.clkin (clkin[1] ) );
endmodule
module bw_clk_cclk_inv_64x(clkout ,clkin );
output clkout ;
input clkin ;
supply1 vdd ;
supply0 vss ;
bw_clk_zcclk_inv_128x x0 (
.clkout ({vdd ,vdd ,vdd ,vdd ,{4 {clkout }} } ),
.clkin ({vss ,vss ,vss ,vss ,{4 {clkin }} } ) );
endmodule
module bw_ctu_muxi21_16x(s ,d1 ,d0 ,z );
output z ;
input s ;
input d1 ;
input d0 ;
supply1 vdd ;
supply0 vss ;
wire s_l ;
wire net44 ;
wire net48 ;
wire net58 ;
wire net67 ;
nmos MNS (s_l ,s ,vss );
pmos I11 (net44 ,d0 ,vdd );
nmos I12 (net58 ,d0 ,vss );
pmos I15 (net48 ,d1 ,vdd );
pmos I16 (z ,s_l ,net48 );
nmos I17 (net67 ,d1 ,vss );
nmos I18 (z ,s ,net67 );
nmos M0 (z ,s_l ,net58 );
pmos M1 (z ,s ,net44 );
pmos MPS (s_l ,s ,vdd );
endmodule
*/
module bw_ctu_clk_sync_mux_1path(pll_clk_out_l ,muxin0 ,mux_out_l ,in1 ,
selg ,in0 ,pll_clk_out ,clk_out );
output mux_out_l ;
output clk_out ;
input pll_clk_out_l ;
input muxin0 ;
input in1 ;
input selg ;
input in0 ;
input pll_clk_out ;
//supply0 vss ;
wire fout0_l ;
wire fout1_l ;
wire gclk_mux_l ;
wire net22 ;
wire net28 ;
wire clk_out_l ;
wire gclk_mux ;
wire gclk ;
// synopsys translate_off
assign gclk_mux = ~(fout1_l & fout0_l);
assign gclk_mux_l = ~gclk_mux;
assign mux_out_l = ~gclk_mux;
assign clk_out = ~clk_out_l;
assign clk_out_l = ~gclk;
bw_u1_soffi_4x xf0 (
.q_l (fout0_l ),
.so (),
.ck (pll_clk_out ),
.d (in0 ),
.se (1'b0),
.sd () );
bw_u1_soffi_4x xf1 (
.q_l (fout1_l ),
.so (),
.ck (pll_clk_out_l ),
.d (in1 ),
.se (1'b0),
.sd () );
bw_u1_muxi21_4x xmux (
.s (selg ),
.d1 (gclk_mux_l ),
.d0 (muxin0 ),
.z (gclk ) );
// synopsys translate_on
/*
snand2 xnd2 (
.Y (gclk_mux ),
.B (fout1_l ),
.A (fout0_l ) );
sinv xi1 (
.Y (gclk_mux_l ),
.A (gclk_mux ) );
sinv ximo (
.Y (mux_out_l ),
.A (gclk_mux ) );
bw_ctu_muxi21_16x xmux (
.s (selg ),
.d1 (gclk_mux_l ),
.d0 (muxin0 ),
.z (gclk ) );
bw_clk_gclk_inv_256x xcb256 (
.clkout (clk_out ),
.clkin (clk_out_l ) );
bw_u1_soffi_4x xf0 (
.q_l (fout0_l ),
.so (net22 ),
.ck (pll_clk_out ),
.d (in0 ),
.se (vss ),
.sd (vss ) );
bw_u1_soffi_4x xf1 (
.q_l (fout1_l ),
.so (net28 ),
.ck (pll_clk_out_l ),
.d (in1 ),
.se (vss ),
.sd (vss ) );
bw_clk_cclk_inv_64x xcb64 (
.clkout (clk_out_l ),
.clkin (gclk ) );
*/
endmodule
module bw_ctu_clk_sync_mux(jbus_div0 ,jbus_clk_mux_0 ,tcu_sel_jbus ,
jbus_div1 ,dram_clk_mux_0 ,dram_div0 ,dram_div1 ,tcu_sel_dram ,
tcu_sel_cpu ,pll_clk_out ,cmp_div1 ,cmp_div0 ,cmp_clk_mux_0 ,
cmp_gclk_byp ,dram_gclk_byp ,jbus_gclk_byp ,pll_clk_out_l ,
cmp_gclk_out ,dram_gclk_out ,jbus_gclk_out ,jbus_gclk_dup_byp ,
jbus_gclk_dup_out ,jbus_gclk_dupl_mux_0 ,jbus_dup_div0 ,
jbus_dup_div1 ,tcu_sel_jbus_dup );
input [0:0] tcu_sel_jbus ;
input [0:0] tcu_sel_dram ;
input [0:0] tcu_sel_cpu ;
input [0:0] tcu_sel_jbus_dup ;
output cmp_gclk_byp ;
output dram_gclk_byp ;
output jbus_gclk_byp ;
output cmp_gclk_out ;
output dram_gclk_out ;
output jbus_gclk_out ;
output jbus_gclk_dup_byp ;
output jbus_gclk_dup_out ;
input jbus_div0 ;
input jbus_clk_mux_0 ;
input jbus_div1 ;
input dram_clk_mux_0 ;
input dram_div0 ;
input dram_div1 ;
input pll_clk_out ;
input cmp_div1 ;
input cmp_div0 ;
input cmp_clk_mux_0 ;
input pll_clk_out_l ;
input jbus_gclk_dupl_mux_0 ;
input jbus_dup_div0 ;
input jbus_dup_div1 ;
// This is the verilog code for synthesis
// synopsys translate_off
bw_ctu_clk_sync_mux_1path x2 (
.pll_clk_out_l (pll_clk_out_l ),
.muxin0 (jbus_gclk_dupl_mux_0 ),
.mux_out_l (jbus_gclk_dup_byp ),
.in1 (jbus_dup_div1 ),
.selg (tcu_sel_jbus_dup[0] ),
.in0 (jbus_dup_div0 ),
.pll_clk_out (pll_clk_out ),
.clk_out (jbus_gclk_dup_out ) );
bw_ctu_clk_sync_mux_1path xcsm1 (
.pll_clk_out_l (pll_clk_out_l ),
.muxin0 (cmp_clk_mux_0 ),
.mux_out_l (cmp_gclk_byp ),
.in1 (cmp_div1 ),
.selg (tcu_sel_cpu[0] ),
.in0 (cmp_div0 ),
.pll_clk_out (pll_clk_out ),
.clk_out (cmp_gclk_out ) );
bw_ctu_clk_sync_mux_1path x0 (
.pll_clk_out_l (pll_clk_out_l ),
.muxin0 (dram_clk_mux_0 ),
.mux_out_l (dram_gclk_byp ),
.in1 (dram_div1 ),
.selg (tcu_sel_dram[0] ),
.in0 (dram_div0 ),
.pll_clk_out (pll_clk_out ),
.clk_out (dram_gclk_out ) );
bw_ctu_clk_sync_mux_1path x1 (
.pll_clk_out_l (pll_clk_out_l ),
.muxin0 (jbus_clk_mux_0 ),
.mux_out_l (jbus_gclk_byp ),
.in1 (jbus_div1 ),
.selg (tcu_sel_jbus[0] ),
.in0 (jbus_div0 ),
.pll_clk_out (pll_clk_out ),
.clk_out (jbus_gclk_out ) );
// synopsys translate_on
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 4.0
// \ \ Application : MIG
// / / Filename : wiredly.v
// /___/ /\ Date Last Modified : $Date: 2011/06/23 08:25:20 $
// \ \ / \ Date Created : Fri Oct 14 2011
// \___\/\___\
//
// Device : 7Series
// Design Name : DDR2 SDRAM
// Purpose :
// This module provide the definition of a zero ohm component (A, B).
//
// The applications of this component include:
// . Normal operation of a jumper wire (data flowing in both directions)
// This can corrupt data from DRAM to FPGA useful for verifying ECC function.
//
// The component consists of 2 ports:
// . Port A: One side of the pass-through switch
// . Port B: The other side of the pass-through switch
// The model is sensitive to transactions on all ports. Once a transaction
// is detected, all other transactions are ignored for that simulation time
// (i.e. further transactions in that delta time are ignored).
// Model Limitations and Restrictions:
// Signals asserted on the ports of the error injector should not have
// transactions occuring in multiple delta times because the model
// is sensitive to transactions on port A, B ONLY ONCE during
// a simulation time. Thus, once fired, a process will
// not refire if there are multiple transactions occuring in delta times.
// This condition may occur in gate level simulations with
// ZERO delays because transactions may occur in multiple delta times.
//
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1ns / 1ps
module WireDelay # (
parameter Delay_g = 0,
parameter Delay_rd = 0,
parameter ERR_INSERT = "OFF"
)
(
inout A,
inout B,
input reset,
input phy_init_done
);
reg A_r;
reg B_r;
reg B_inv ;
reg line_en;
reg B_nonX;
assign A = A_r;
assign B = B_r;
always @ (*)
begin
if (B === 1'bx)
B_nonX <= $random;
else
B_nonX <= B;
end
always@(*)
begin
if((B_nonX == 'b1) || (B_nonX == 'b0))
B_inv <= #0 ~B_nonX ;
else
B_inv <= #0 'bz ;
end
always @(*) begin
if (!reset) begin
A_r <= 1'bz;
B_r <= 1'bz;
line_en <= 1'b0;
end else begin
if (line_en) begin
B_r <= 1'bz;
if ((ERR_INSERT == "ON") & (phy_init_done))
A_r <= #Delay_rd B_inv;
else
A_r <= #Delay_rd B_nonX;
end else begin
B_r <= #Delay_g A;
A_r <= 1'bz;
end
end
end
always @(A or B) begin
if (!reset) begin
line_en <= 1'b0;
end else if (A !== A_r) begin
line_en <= 1'b0;
end else if (B_r !== B) begin
line_en <= 1'b1;
end else begin
line_en <= line_en;
end
end
endmodule
|
// megafunction wizard: %ALTGX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: alt_c3gxb
// ============================================================
// File Name: altpcie_serdes_3cgx_x2d_gen1_08p.v
// Megafunction Name(s):
// alt_c3gxb
//
// Simulation Library Files(s):
// altera_mf;cycloneiv_hssi
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//alt_c3gxb CBX_AUTO_BLACKBOX="ALL" device_family="Cyclone IV GX" effective_data_rate="2500 Mbps" elec_idle_infer_enable="false" enable_0ppm="false" equalization_setting=1 equalizer_dcgain_setting=1 gxb_powerdown_width=1 loopback_mode="none" number_of_channels=2 number_of_quads=1 operation_mode="duplex" pll_bandwidth_type="auto" pll_control_width=1 pll_divide_by="2" pll_inclk_period=10000 pll_multiply_by="25" pll_pfd_fb_mode="internal" preemphasis_ctrl_1stposttap_setting=18 protocol="pcie" receiver_termination="oct_100_ohms" reconfig_calibration="true" reconfig_dprio_mode=0 reconfig_pll_control_width=1 rx_8b_10b_mode="normal" rx_align_pattern="0101111100" rx_align_pattern_length=10 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="true" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_cdrctrl_enable="true" rx_channel_bonding="x2" rx_channel_width=16 rx_common_mode="0.82v" rx_datapath_protocol="pipe" rx_deskew_pattern="0" rx_digitalreset_port_width=1 rx_dwidth_factor=2 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_enable_self_test_mode="false" rx_force_signal_detect="false" rx_ppmselect=8 rx_rate_match_fifo_mode="normal" rx_rate_match_pattern1="11010000111010000011" rx_rate_match_pattern2="00101111000101111100" rx_rate_match_pattern_size=20 rx_run_length=40 rx_run_length_enable="true" rx_signal_detect_loss_threshold=3 rx_signal_detect_threshold=4 rx_signal_detect_valid_threshold=14 rx_use_align_state_machine="true" rx_use_clkout="false" rx_use_coreclk="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="true" rx_use_external_termination="false" rx_use_pipe8b10binvpolarity="true" rx_word_aligner_num_byte=1 starting_channel_number=0 top_module_name="altpcie_serdes_3cgx_x2d_gen1_08p" transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_bitslip_enable="false" tx_channel_bonding="x2" tx_channel_width=16 tx_clkout_width=2 tx_common_mode="0.65v" tx_digitalreset_port_width=1 tx_dwidth_factor=2 tx_enable_bit_reversal="false" tx_enable_self_test_mode="false" tx_slew_rate="low" tx_transmit_protocol="pipe" tx_use_coreclk="false" tx_use_double_data_mode="true" tx_use_external_termination="false" use_calibration_block="true" vod_ctrl_setting=5 cal_blk_clk coreclkout fixedclk gxb_powerdown pipe8b10binvpolarity pipedatavalid pipeelecidle pipephydonestatus pipestatus pll_areset pll_inclk pll_locked powerdn reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_disperr rx_errdetect rx_freqlocked rx_patterndetect rx_syncstatus tx_ctrlenable tx_datain tx_dataout tx_detectrxloop tx_digitalreset tx_forcedispcompliance tx_forceelecidle intended_device_family="Cyclone IV GX"
//VERSION_BEGIN 10.0SP1 cbx_alt_c3gxb 2010:08:18:21:06:53:SJ cbx_altclkbuf 2010:08:18:21:06:53:SJ cbx_altiobuf_bidir 2010:08:18:21:06:53:SJ cbx_altiobuf_in 2010:08:18:21:06:53:SJ cbx_altiobuf_out 2010:08:18:21:06:53:SJ cbx_altpll 2010:08:18:21:06:53:SJ cbx_cycloneii 2010:08:18:21:06:53:SJ cbx_lpm_add_sub 2010:08:18:21:06:53:SJ cbx_lpm_compare 2010:08:18:21:06:53:SJ cbx_lpm_decode 2010:08:18:21:06:53:SJ cbx_lpm_mux 2010:08:18:21:06:53:SJ cbx_mgl 2010:08:18:21:24:06:SJ cbx_stingray 2010:08:18:21:06:53:SJ cbx_stratix 2010:08:18:21:06:53:SJ cbx_stratixii 2010:08:18:21:06:54:SJ cbx_stratixiii 2010:08:18:21:06:54:SJ cbx_stratixv 2010:08:18:21:06:54:SJ cbx_util_mgl 2010:08:18:21:06:53:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = altpll 1 cycloneiv_hssi_calibration_block 1 cycloneiv_hssi_cmu 1 cycloneiv_hssi_rx_pcs 2 cycloneiv_hssi_rx_pma 2 cycloneiv_hssi_tx_pcs 2 cycloneiv_hssi_tx_pma 2 reg 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"suppress_da_rule_internal=c104"} *)
module altpcie_serdes_3cgx_x2d_gen1_08p_alt_c3gxb_om78
(
cal_blk_clk,
coreclkout,
fixedclk,
gxb_powerdown,
pipe8b10binvpolarity,
pipedatavalid,
pipeelecidle,
pipephydonestatus,
pipestatus,
pll_areset,
pll_inclk,
pll_locked,
powerdn,
reconfig_clk,
reconfig_fromgxb,
reconfig_togxb,
rx_analogreset,
rx_ctrldetect,
rx_datain,
rx_dataout,
rx_digitalreset,
rx_disperr,
rx_errdetect,
rx_freqlocked,
rx_patterndetect,
rx_syncstatus,
tx_ctrlenable,
tx_datain,
tx_dataout,
tx_detectrxloop,
tx_digitalreset,
tx_forcedispcompliance,
tx_forceelecidle) /* synthesis synthesis_clearbox=2 */;
input cal_blk_clk;
output [0:0] coreclkout;
input fixedclk;
input [0:0] gxb_powerdown;
input [1:0] pipe8b10binvpolarity;
output [1:0] pipedatavalid;
output [1:0] pipeelecidle;
output [1:0] pipephydonestatus;
output [5:0] pipestatus;
input [0:0] pll_areset;
input [0:0] pll_inclk;
output [0:0] pll_locked;
input [3:0] powerdn;
input reconfig_clk;
output [4:0] reconfig_fromgxb;
input [3:0] reconfig_togxb;
input [0:0] rx_analogreset;
output [3:0] rx_ctrldetect;
input [1:0] rx_datain;
output [31:0] rx_dataout;
input [0:0] rx_digitalreset;
output [3:0] rx_disperr;
output [3:0] rx_errdetect;
output [1:0] rx_freqlocked;
output [3:0] rx_patterndetect;
output [3:0] rx_syncstatus;
input [3:0] tx_ctrlenable;
input [31:0] tx_datain;
output [1:0] tx_dataout;
input [1:0] tx_detectrxloop;
input [0:0] tx_digitalreset;
input [1:0] tx_forcedispcompliance;
input [1:0] tx_forceelecidle;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 cal_blk_clk;
tri0 fixedclk;
tri0 [0:0] gxb_powerdown;
tri0 [1:0] pipe8b10binvpolarity;
tri0 [0:0] pll_areset;
tri0 [3:0] powerdn;
tri0 reconfig_clk;
tri0 [0:0] rx_analogreset;
tri0 [0:0] rx_digitalreset;
tri0 [3:0] tx_ctrlenable;
tri0 [31:0] tx_datain;
tri0 [1:0] tx_detectrxloop;
tri0 [0:0] tx_digitalreset;
tri0 [1:0] tx_forcedispcompliance;
tri0 [1:0] tx_forceelecidle;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
parameter starting_channel_number = 0;
wire [5:0] wire_pll0_clk;
wire wire_pll0_fref;
wire wire_pll0_icdrclk;
wire wire_pll0_locked;
wire wire_cal_blk0_nonusertocmu;
wire wire_cent_unit0_coreclkout;
wire wire_cent_unit0_dpriodisableout;
wire wire_cent_unit0_dprioout;
wire wire_cent_unit0_quadresetout;
wire wire_cent_unit0_refclkout;
wire [3:0] wire_cent_unit0_rxanalogresetout;
wire [3:0] wire_cent_unit0_rxcrupowerdown;
wire [3:0] wire_cent_unit0_rxdigitalresetout;
wire [3:0] wire_cent_unit0_rxibpowerdown;
wire [1599:0] wire_cent_unit0_rxpcsdprioout;
wire wire_cent_unit0_rxphfifox4byteselout;
wire wire_cent_unit0_rxphfifox4rdenableout;
wire wire_cent_unit0_rxphfifox4wrclkout;
wire wire_cent_unit0_rxphfifox4wrenableout;
wire [1199:0] wire_cent_unit0_rxpmadprioout;
wire [3:0] wire_cent_unit0_txanalogresetout;
wire [3:0] wire_cent_unit0_txdetectrxpowerdown;
wire [3:0] wire_cent_unit0_txdigitalresetout;
wire [3:0] wire_cent_unit0_txdividerpowerdown;
wire [3:0] wire_cent_unit0_txobpowerdown;
wire [599:0] wire_cent_unit0_txpcsdprioout;
wire wire_cent_unit0_txphfifox4byteselout;
wire wire_cent_unit0_txphfifox4rdclkout;
wire wire_cent_unit0_txphfifox4rdenableout;
wire wire_cent_unit0_txphfifox4wrenableout;
wire [1199:0] wire_cent_unit0_txpmadprioout;
wire wire_receive_pcs0_cdrctrlearlyeios;
wire wire_receive_pcs0_cdrctrllocktorefclkout;
wire wire_receive_pcs0_coreclkout;
wire [1:0] wire_receive_pcs0_ctrldetect;
wire [19:0] wire_receive_pcs0_dataout;
wire [1:0] wire_receive_pcs0_disperr;
wire [399:0] wire_receive_pcs0_dprioout;
wire [1:0] wire_receive_pcs0_errdetect;
wire [1:0] wire_receive_pcs0_patterndetect;
wire wire_receive_pcs0_phfifordenableout;
wire wire_receive_pcs0_phfiforesetout;
wire wire_receive_pcs0_phfifowrdisableout;
wire wire_receive_pcs0_pipedatavalid;
wire wire_receive_pcs0_pipeelecidle;
wire wire_receive_pcs0_pipephydonestatus;
wire [2:0] wire_receive_pcs0_pipestatus;
wire [19:0] wire_receive_pcs0_revparallelfdbkdata;
wire [1:0] wire_receive_pcs0_syncstatus;
wire wire_receive_pcs1_cdrctrlearlyeios;
wire wire_receive_pcs1_cdrctrllocktorefclkout;
wire wire_receive_pcs1_coreclkout;
wire [1:0] wire_receive_pcs1_ctrldetect;
wire [19:0] wire_receive_pcs1_dataout;
wire [1:0] wire_receive_pcs1_disperr;
wire [399:0] wire_receive_pcs1_dprioout;
wire [1:0] wire_receive_pcs1_errdetect;
wire [1:0] wire_receive_pcs1_patterndetect;
wire wire_receive_pcs1_phfifordenableout;
wire wire_receive_pcs1_phfiforesetout;
wire wire_receive_pcs1_phfifowrdisableout;
wire wire_receive_pcs1_pipedatavalid;
wire wire_receive_pcs1_pipeelecidle;
wire wire_receive_pcs1_pipephydonestatus;
wire [2:0] wire_receive_pcs1_pipestatus;
wire [19:0] wire_receive_pcs1_revparallelfdbkdata;
wire [1:0] wire_receive_pcs1_syncstatus;
wire [7:0] wire_receive_pma0_analogtestbus;
wire wire_receive_pma0_clockout;
wire [299:0] wire_receive_pma0_dprioout;
wire wire_receive_pma0_freqlocked;
wire wire_receive_pma0_locktorefout;
wire [9:0] wire_receive_pma0_recoverdataout;
wire wire_receive_pma0_signaldetect;
wire [7:0] wire_receive_pma1_analogtestbus;
wire wire_receive_pma1_clockout;
wire [299:0] wire_receive_pma1_dprioout;
wire wire_receive_pma1_freqlocked;
wire wire_receive_pma1_locktorefout;
wire [9:0] wire_receive_pma1_recoverdataout;
wire wire_receive_pma1_signaldetect;
wire wire_transmit_pcs0_coreclkout;
wire [9:0] wire_transmit_pcs0_dataout;
wire [149:0] wire_transmit_pcs0_dprioout;
wire wire_transmit_pcs0_forceelecidleout;
wire [2:0] wire_transmit_pcs0_grayelecidleinferselout;
wire wire_transmit_pcs0_phfiforddisableout;
wire wire_transmit_pcs0_phfiforesetout;
wire wire_transmit_pcs0_phfifowrenableout;
wire wire_transmit_pcs0_pipeenrevparallellpbkout;
wire [1:0] wire_transmit_pcs0_pipepowerdownout;
wire [3:0] wire_transmit_pcs0_pipepowerstateout;
wire wire_transmit_pcs0_txdetectrx;
wire wire_transmit_pcs1_coreclkout;
wire [9:0] wire_transmit_pcs1_dataout;
wire [149:0] wire_transmit_pcs1_dprioout;
wire wire_transmit_pcs1_forceelecidleout;
wire [2:0] wire_transmit_pcs1_grayelecidleinferselout;
wire wire_transmit_pcs1_phfiforddisableout;
wire wire_transmit_pcs1_phfiforesetout;
wire wire_transmit_pcs1_phfifowrenableout;
wire wire_transmit_pcs1_pipeenrevparallellpbkout;
wire [1:0] wire_transmit_pcs1_pipepowerdownout;
wire [3:0] wire_transmit_pcs1_pipepowerstateout;
wire wire_transmit_pcs1_txdetectrx;
wire wire_transmit_pma0_clockout;
wire wire_transmit_pma0_dataout;
wire [299:0] wire_transmit_pma0_dprioout;
wire wire_transmit_pma0_rxdetectvalidout;
wire wire_transmit_pma0_rxfoundout;
wire wire_transmit_pma1_clockout;
wire wire_transmit_pma1_dataout;
wire [299:0] wire_transmit_pma1_dprioout;
wire wire_transmit_pma1_rxdetectvalidout;
wire wire_transmit_pma1_rxfoundout;
reg [0:0] fixedclk_div;
reg [1:0] reconfig_togxb_busy_reg;
wire cal_blk_powerdown;
wire [1:0] cent_unit_quadresetout;
wire [1:0] cent_unit_rxcrupowerdn;
wire [1:0] cent_unit_rxibpowerdn;
wire [799:0] cent_unit_rxpcsdprioin;
wire [799:0] cent_unit_rxpcsdprioout;
wire [599:0] cent_unit_rxpmadprioin;
wire [599:0] cent_unit_rxpmadprioout;
wire [299:0] cent_unit_tx_dprioin;
wire [1:0] cent_unit_txdetectrxpowerdn;
wire [1:0] cent_unit_txdividerpowerdown;
wire [299:0] cent_unit_txdprioout;
wire [1:0] cent_unit_txobpowerdn;
wire [599:0] cent_unit_txpmadprioin;
wire [599:0] cent_unit_txpmadprioout;
wire [0:0] coreclkout_wire;
wire [0:0] fixedclk_div_in;
wire [0:0] fixedclk_enable;
wire [3:0] fixedclk_fast;
wire [0:0] fixedclk_sel;
wire [1:0] fixedclk_to_cmu;
wire [5:0] grayelecidleinfersel_from_tx;
wire [1:0] int_pipeenrevparallellpbkfromtx;
wire [1:0] int_rx_coreclkout;
wire [1:0] int_rx_phfifordenableout;
wire [1:0] int_rx_phfiforesetout;
wire [1:0] int_rx_phfifowrdisableout;
wire [1:0] int_rx_phfifoxnbytesel;
wire [1:0] int_rx_phfifoxnrdenable;
wire [1:0] int_rx_phfifoxnwrclk;
wire [1:0] int_rx_phfifoxnwrenable;
wire [0:0] int_rxcoreclk;
wire [0:0] int_rxphfifordenable;
wire [0:0] int_rxphfiforeset;
wire [0:0] int_rxphfifox4byteselout;
wire [0:0] int_rxphfifox4rdenableout;
wire [0:0] int_rxphfifox4wrclkout;
wire [0:0] int_rxphfifox4wrenableout;
wire [1:0] int_tx_coreclkout;
wire [1:0] int_tx_phfiforddisableout;
wire [1:0] int_tx_phfiforesetout;
wire [1:0] int_tx_phfifowrenableout;
wire [1:0] int_tx_phfifoxnbytesel;
wire [1:0] int_tx_phfifoxnrdclk;
wire [1:0] int_tx_phfifoxnrdenable;
wire [1:0] int_tx_phfifoxnwrenable;
wire [0:0] int_txcoreclk;
wire [0:0] int_txphfiforddisable;
wire [0:0] int_txphfiforeset;
wire [0:0] int_txphfifowrenable;
wire [0:0] int_txphfifox4byteselout;
wire [0:0] int_txphfifox4rdclkout;
wire [0:0] int_txphfifox4rdenableout;
wire [0:0] int_txphfifox4wrenableout;
wire [0:0] nonusertocmu_out;
wire [1:0] pipedatavalid_out;
wire [1:0] pipeelecidle_out;
wire [0:0] pll_powerdown;
wire [0:0] reconfig_togxb_busy;
wire [0:0] reconfig_togxb_disable;
wire [0:0] reconfig_togxb_in;
wire [0:0] reconfig_togxb_load;
wire [0:0] refclk_pma;
wire [1:0] rx_analogreset_in;
wire [1:0] rx_analogreset_out;
wire [1:0] rx_coreclk_in;
wire [1:0] rx_deserclock_in;
wire [1:0] rx_digitalreset_in;
wire [1:0] rx_digitalreset_out;
wire [5:0] rx_elecidleinfersel;
wire [1:0] rx_enapatternalign;
wire [1:0] rx_locktodata;
wire [1:0] rx_locktorefclk_wire;
wire [31:0] rx_out_wire;
wire [3:0] rx_pcs_rxfound_wire;
wire [799:0] rx_pcsdprioin_wire;
wire [799:0] rx_pcsdprioout;
wire [1:0] rx_phfifordenable;
wire [1:0] rx_phfiforeset;
wire [1:0] rx_phfifowrdisable;
wire [1:0] rx_pll_pfdrefclkout_wire;
wire [4:0] rx_pma_analogtestbus;
wire [1:0] rx_pma_clockout;
wire [19:0] rx_pma_recoverdataout_wire;
wire [599:0] rx_pmadprioin_wire;
wire [599:0] rx_pmadprioout;
wire [1:0] rx_powerdown;
wire [1:0] rx_powerdown_in;
wire [1:0] rx_prbscidenable;
wire [39:0] rx_revparallelfdbkdata;
wire [1:0] rx_rmfiforeset;
wire [1:0] rx_signaldetect_wire;
wire [0:0] rxphfifowrdisable;
wire [1:0] tx_analogreset_out;
wire [1:0] tx_clkout_int_wire;
wire [1:0] tx_coreclk_in;
wire [31:0] tx_datain_wire;
wire [19:0] tx_dataout_pcs_to_pma;
wire [1:0] tx_digitalreset_in;
wire [1:0] tx_digitalreset_out;
wire [299:0] tx_dprioin_wire;
wire [3:0] tx_forcedisp_wire;
wire [1:0] tx_invpolarity;
wire [1:0] tx_localrefclk;
wire [1:0] tx_pcs_forceelecidleout;
wire [1:0] tx_phfiforeset;
wire [3:0] tx_pipepowerdownout;
wire [7:0] tx_pipepowerstateout;
wire [1:0] tx_pma_fastrefclk0in;
wire [1:0] tx_pma_refclk0in;
wire [1:0] tx_pma_refclk0inpulse;
wire [599:0] tx_pmadprioin_wire;
wire [599:0] tx_pmadprioout;
wire [1:0] tx_revparallellpbken;
wire [1:0] tx_rxdetectvalidout;
wire [1:0] tx_rxfoundout;
wire [299:0] tx_txdprioout;
wire [1:0] txdataout;
wire [1:0] txdetectrxout;
wire [0:0] w_cent_unit_dpriodisableout1w;
altpll pll0
(
.activeclock(),
.areset(pll_powerdown[0]),
.clk(wire_pll0_clk),
.clkbad(),
.clkloss(),
.enable0(),
.enable1(),
.extclk(),
.fbout(),
.fref(wire_pll0_fref),
.icdrclk(wire_pll0_icdrclk),
.inclk({{1{1'b0}}, pll_inclk[0]}),
.locked(wire_pll0_locked),
.phasedone(),
.scandataout(),
.scandone(),
.sclkout0(),
.sclkout1(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clkena({6{1'b1}}),
.clkswitch(1'b0),
.configupdate(1'b0),
.extclkena({4{1'b1}}),
.fbin(1'b1),
.pfdena(1'b1),
.phasecounterselect({4{1'b1}}),
.phasestep(1'b1),
.phaseupdown(1'b1),
.pllena(1'b1),
.scanaclr(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0),
.scanread(1'b0),
.scanwrite(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll0.bandwidth_type = "AUTO",
pll0.clk0_divide_by = 2,
pll0.clk0_multiply_by = 25,
pll0.clk1_divide_by = 10,
pll0.clk1_multiply_by = 25,
pll0.clk2_divide_by = 10,
pll0.clk2_duty_cycle = 20,
pll0.clk2_multiply_by = 25,
pll0.dpa_divide_by = 2,
pll0.dpa_multiply_by = 25,
pll0.inclk0_input_frequency = 10000,
pll0.operation_mode = "no_compensation",
pll0.intended_device_family = "Cyclone IV GX",
pll0.lpm_type = "altpll";
cycloneiv_hssi_calibration_block cal_blk0
(
.calibrationstatus(),
.clk(cal_blk_clk),
.nonusertocmu(wire_cal_blk0_nonusertocmu),
.powerdn(cal_blk_powerdown)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.testctrl(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
cycloneiv_hssi_cmu cent_unit0
(
.adet({4{1'b0}}),
.alignstatus(),
.coreclkout(wire_cent_unit0_coreclkout),
.digitaltestout(),
.dpclk(reconfig_clk),
.dpriodisable(reconfig_togxb_disable),
.dpriodisableout(wire_cent_unit0_dpriodisableout),
.dprioin(reconfig_togxb_in),
.dprioload(reconfig_togxb_load),
.dpriooe(),
.dprioout(wire_cent_unit0_dprioout),
.enabledeskew(),
.fiforesetrd(),
.fixedclk({{2{1'b0}}, fixedclk_to_cmu[1:0]}),
.nonuserfromcal(nonusertocmu_out[0]),
.quadreset(gxb_powerdown[0]),
.quadresetout(wire_cent_unit0_quadresetout),
.rdalign({4{1'b0}}),
.rdenablesync(1'b0),
.recovclk(1'b0),
.refclkout(wire_cent_unit0_refclkout),
.rxanalogreset({{2{1'b0}}, rx_analogreset_in[1:0]}),
.rxanalogresetout(wire_cent_unit0_rxanalogresetout),
.rxcoreclk(int_rxcoreclk[0]),
.rxcrupowerdown(wire_cent_unit0_rxcrupowerdown),
.rxctrl({4{1'b0}}),
.rxctrlout(),
.rxdatain({32{1'b0}}),
.rxdataout(),
.rxdatavalid({4{1'b0}}),
.rxdigitalreset({{2{1'b0}}, rx_digitalreset_in[1:0]}),
.rxdigitalresetout(wire_cent_unit0_rxdigitalresetout),
.rxibpowerdown(wire_cent_unit0_rxibpowerdown),
.rxpcsdprioin({{800{1'b0}}, cent_unit_rxpcsdprioin[799:0]}),
.rxpcsdprioout(wire_cent_unit0_rxpcsdprioout),
.rxphfifordenable(int_rxphfifordenable[0]),
.rxphfiforeset(int_rxphfiforeset[0]),
.rxphfifowrdisable(rxphfifowrdisable[0]),
.rxphfifox4byteselout(wire_cent_unit0_rxphfifox4byteselout),
.rxphfifox4rdenableout(wire_cent_unit0_rxphfifox4rdenableout),
.rxphfifox4wrclkout(wire_cent_unit0_rxphfifox4wrclkout),
.rxphfifox4wrenableout(wire_cent_unit0_rxphfifox4wrenableout),
.rxpmadprioin({{600{1'b0}}, cent_unit_rxpmadprioin[599:0]}),
.rxpmadprioout(wire_cent_unit0_rxpmadprioout),
.rxpowerdown({{2{1'b0}}, rx_powerdown_in[1:0]}),
.rxrunningdisp({4{1'b0}}),
.syncstatus({4{1'b0}}),
.testout(),
.txanalogresetout(wire_cent_unit0_txanalogresetout),
.txclk(tx_localrefclk[0]),
.txcoreclk(int_txcoreclk[0]),
.txctrl({4{1'b0}}),
.txctrlout(),
.txdatain({32{1'b0}}),
.txdataout(),
.txdetectrxpowerdown(wire_cent_unit0_txdetectrxpowerdown),
.txdigitalreset({{2{1'b0}}, tx_digitalreset_in[1:0]}),
.txdigitalresetout(wire_cent_unit0_txdigitalresetout),
.txdividerpowerdown(wire_cent_unit0_txdividerpowerdown),
.txobpowerdown(wire_cent_unit0_txobpowerdown),
.txpcsdprioin({{300{1'b0}}, cent_unit_tx_dprioin[299:0]}),
.txpcsdprioout(wire_cent_unit0_txpcsdprioout),
.txphfiforddisable(int_txphfiforddisable[0]),
.txphfiforeset(int_txphfiforeset[0]),
.txphfifowrenable(int_txphfifowrenable[0]),
.txphfifox4byteselout(wire_cent_unit0_txphfifox4byteselout),
.txphfifox4rdclkout(wire_cent_unit0_txphfifox4rdclkout),
.txphfifox4rdenableout(wire_cent_unit0_txphfifox4rdenableout),
.txphfifox4wrenableout(wire_cent_unit0_txphfifox4wrenableout),
.txpmadprioin({{600{1'b0}}, cent_unit_txpmadprioin[599:0]}),
.txpmadprioout(wire_cent_unit0_txpmadprioout)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.pmacramtest(1'b0),
.refclkdig(1'b0),
.scanclk(1'b0),
.scanmode(1'b0),
.scanshift(1'b0),
.testin({2000{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cent_unit0.auto_spd_deassert_ph_fifo_rst_count = 8,
cent_unit0.auto_spd_phystatus_notify_count = 14,
cent_unit0.devaddr = ((((starting_channel_number / 4) + 0) % 32) + 1),
cent_unit0.dprio_config_mode = 6'h01,
cent_unit0.in_xaui_mode = "false",
cent_unit0.portaddr = (((starting_channel_number + 0) / 128) + 1),
cent_unit0.rx0_channel_bonding = "x2",
cent_unit0.rx0_clk1_mux_select = "recovered clock",
cent_unit0.rx0_clk2_mux_select = "digital reference clock",
cent_unit0.rx0_ph_fifo_reg_mode = "false",
cent_unit0.rx0_rd_clk_mux_select = "core clock",
cent_unit0.rx0_recovered_clk_mux_select = "recovered clock",
cent_unit0.rx0_reset_clock_output_during_digital_reset = "false",
cent_unit0.rx0_use_double_data_mode = "true",
cent_unit0.tx0_channel_bonding = "x2",
cent_unit0.tx0_rd_clk_mux_select = "central",
cent_unit0.tx0_reset_clock_output_during_digital_reset = "false",
cent_unit0.tx0_use_double_data_mode = "true",
cent_unit0.tx0_wr_clk_mux_select = "core_clk",
cent_unit0.use_coreclk_out_post_divider = "true",
cent_unit0.use_deskew_fifo = "false",
cent_unit0.lpm_type = "cycloneiv_hssi_cmu";
cycloneiv_hssi_rx_pcs receive_pcs0
(
.a1a2size(1'b0),
.a1a2sizeout(),
.a1detect(),
.a2detect(),
.adetectdeskew(),
.alignstatus(1'b0),
.alignstatussync(1'b0),
.alignstatussyncout(),
.bistdone(),
.bisterr(),
.bitslipboundaryselectout(),
.byteorderalignstatus(),
.cdrctrlearlyeios(wire_receive_pcs0_cdrctrlearlyeios),
.cdrctrllocktorefclkout(wire_receive_pcs0_cdrctrllocktorefclkout),
.clkout(),
.coreclk(rx_coreclk_in[0]),
.coreclkout(wire_receive_pcs0_coreclkout),
.ctrldetect(wire_receive_pcs0_ctrldetect),
.datain(rx_pma_recoverdataout_wire[9:0]),
.dataout(wire_receive_pcs0_dataout),
.dataoutfull(),
.digitalreset(rx_digitalreset_out[0]),
.disperr(wire_receive_pcs0_disperr),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pcsdprioin_wire[399:0]),
.dprioout(wire_receive_pcs0_dprioout),
.elecidleinfersel({3{1'b0}}),
.enabledeskew(1'b0),
.enabyteord(1'b0),
.enapatternalign(rx_enapatternalign[0]),
.errdetect(wire_receive_pcs0_errdetect),
.fifordin(1'b0),
.fifordout(),
.fiforesetrd(1'b0),
.grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[2:0]),
.hipdataout(),
.hipdatavalid(),
.hipelecidle(),
.hipphydonestatus(),
.hipstatus(),
.invpol(1'b0),
.k1detect(),
.k2detect(),
.localrefclk(tx_localrefclk[0]),
.masterclk(1'b0),
.parallelfdbk({20{1'b0}}),
.patterndetect(wire_receive_pcs0_patterndetect),
.phfifooverflow(),
.phfifordenable(rx_phfifordenable[0]),
.phfifordenableout(wire_receive_pcs0_phfifordenableout),
.phfiforeset(rx_phfiforeset[0]),
.phfiforesetout(wire_receive_pcs0_phfiforesetout),
.phfifounderflow(),
.phfifowrdisable(rx_phfifowrdisable[0]),
.phfifowrdisableout(wire_receive_pcs0_phfifowrdisableout),
.phfifox4bytesel(int_rx_phfifoxnbytesel[0]),
.phfifox4rdenable(int_rx_phfifoxnrdenable[0]),
.phfifox4wrclk(int_rx_phfifoxnwrclk[0]),
.phfifox4wrenable(int_rx_phfifoxnwrenable[0]),
.pipe8b10binvpolarity(pipe8b10binvpolarity[0]),
.pipebufferstat(),
.pipedatavalid(wire_receive_pcs0_pipedatavalid),
.pipeelecidle(wire_receive_pcs0_pipeelecidle),
.pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[0]),
.pipephydonestatus(wire_receive_pcs0_pipephydonestatus),
.pipepowerdown(tx_pipepowerdownout[1:0]),
.pipepowerstate(tx_pipepowerstateout[3:0]),
.pipestatetransdoneout(),
.pipestatus(wire_receive_pcs0_pipestatus),
.powerdn(powerdn[1:0]),
.prbscidenable(rx_prbscidenable[0]),
.quadreset(cent_unit_quadresetout[0]),
.rdalign(),
.recoveredclk(rx_pma_clockout[0]),
.refclk(refclk_pma[0]),
.revbitorderwa(1'b0),
.revparallelfdbkdata(wire_receive_pcs0_revparallelfdbkdata),
.rlv(),
.rmfifodatadeleted(),
.rmfifodatainserted(),
.rmfifoempty(),
.rmfifofull(),
.rmfifordena(1'b0),
.rmfiforeset(rx_rmfiforeset[0]),
.rmfifowrena(1'b0),
.runningdisp(),
.rxdetectvalid(tx_rxdetectvalidout[0]),
.rxfound(rx_pcs_rxfound_wire[1:0]),
.signaldetect(),
.signaldetected(rx_signaldetect_wire[0]),
.syncstatus(wire_receive_pcs0_syncstatus),
.syncstatusdeskew(),
.xauidelcondmetout(),
.xauififoovrout(),
.xauiinsertincompleteout(),
.xauilatencycompout(),
.xgmctrldet(),
.xgmctrlin(1'b0),
.xgmdatain({8{1'b0}}),
.xgmdataout(),
.xgmdatavalid(),
.xgmrunningdisp()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslip(1'b0),
.cdrctrllocktorefcl(1'b0),
.hip8b10binvpolarity(1'b0),
.hipelecidleinfersel({3{1'b0}}),
.hippowerdown({2{1'b0}}),
.pmatestbusin({8{1'b0}}),
.revbyteorderwa(1'b0),
.wareset(1'b0),
.xauidelcondmet(1'b0),
.xauififoovr(1'b0),
.xauiinsertincomplete(1'b0),
.xauilatencycomp(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pcs0.align_pattern = "0101111100",
receive_pcs0.align_pattern_length = 10,
receive_pcs0.allow_align_polarity_inversion = "false",
receive_pcs0.allow_pipe_polarity_inversion = "true",
receive_pcs0.auto_spd_deassert_ph_fifo_rst_count = 8,
receive_pcs0.auto_spd_phystatus_notify_count = 14,
receive_pcs0.bit_slip_enable = "false",
receive_pcs0.byte_order_invalid_code_or_run_disp_error = "true",
receive_pcs0.byte_order_mode = "none",
receive_pcs0.byte_order_pad_pattern = "0",
receive_pcs0.byte_order_pattern = "0",
receive_pcs0.byte_order_pld_ctrl_enable = "false",
receive_pcs0.cdrctrl_bypass_ppm_detector_cycle = 1000,
receive_pcs0.cdrctrl_cid_mode_enable = "true",
receive_pcs0.cdrctrl_enable = "true",
receive_pcs0.cdrctrl_mask_cycle = 800,
receive_pcs0.cdrctrl_min_lock_to_ref_cycle = 63,
receive_pcs0.cdrctrl_rxvalid_mask = "true",
receive_pcs0.channel_bonding = "x2",
receive_pcs0.channel_number = ((starting_channel_number + 0) % 2),
receive_pcs0.channel_width = 16,
receive_pcs0.clk1_mux_select = "recovered clock",
receive_pcs0.clk2_mux_select = "digital reference clock",
receive_pcs0.core_clock_0ppm = "false",
receive_pcs0.datapath_low_latency_mode = "false",
receive_pcs0.datapath_protocol = "pipe",
receive_pcs0.dec_8b_10b_compatibility_mode = "true",
receive_pcs0.dec_8b_10b_mode = "normal",
receive_pcs0.deskew_pattern = "0",
receive_pcs0.disable_auto_idle_insertion = "false",
receive_pcs0.disable_running_disp_in_word_align = "false",
receive_pcs0.disallow_kchar_after_pattern_ordered_set = "false",
receive_pcs0.dprio_config_mode = 6'h01,
receive_pcs0.elec_idle_gen1_sigdet_enable = "true",
receive_pcs0.elec_idle_infer_enable = "false",
receive_pcs0.elec_idle_num_com_detect = 3,
receive_pcs0.enable_bit_reversal = "false",
receive_pcs0.enable_self_test_mode = "false",
receive_pcs0.force_signal_detect_dig = "true",
receive_pcs0.hip_enable = "false",
receive_pcs0.infiniband_invalid_code = 0,
receive_pcs0.insert_pad_on_underflow = "false",
receive_pcs0.num_align_code_groups_in_ordered_set = 0,
receive_pcs0.num_align_cons_good_data = 16,
receive_pcs0.num_align_cons_pat = 4,
receive_pcs0.num_align_loss_sync_error = 17,
receive_pcs0.ph_fifo_low_latency_enable = "true",
receive_pcs0.ph_fifo_reg_mode = "false",
receive_pcs0.protocol_hint = "pcie",
receive_pcs0.rate_match_back_to_back = "false",
receive_pcs0.rate_match_delete_threshold = 13,
receive_pcs0.rate_match_empty_threshold = 5,
receive_pcs0.rate_match_fifo_mode = "true",
receive_pcs0.rate_match_full_threshold = 20,
receive_pcs0.rate_match_insert_threshold = 11,
receive_pcs0.rate_match_ordered_set_based = "false",
receive_pcs0.rate_match_pattern1 = "11010000111010000011",
receive_pcs0.rate_match_pattern2 = "00101111000101111100",
receive_pcs0.rate_match_pattern_size = 20,
receive_pcs0.rate_match_pipe_enable = "true",
receive_pcs0.rate_match_reset_enable = "false",
receive_pcs0.rate_match_skip_set_based = "true",
receive_pcs0.rate_match_start_threshold = 7,
receive_pcs0.rd_clk_mux_select = "core clock",
receive_pcs0.recovered_clk_mux_select = "recovered clock",
receive_pcs0.run_length = 40,
receive_pcs0.run_length_enable = "true",
receive_pcs0.rx_detect_bypass = "false",
receive_pcs0.rx_phfifo_wait_cnt = 32,
receive_pcs0.rxstatus_error_report_mode = 1,
receive_pcs0.self_test_mode = "incremental",
receive_pcs0.use_alignment_state_machine = "true",
receive_pcs0.use_deskew_fifo = "false",
receive_pcs0.use_double_data_mode = "true",
receive_pcs0.use_parallel_loopback = "false",
receive_pcs0.lpm_type = "cycloneiv_hssi_rx_pcs";
cycloneiv_hssi_rx_pcs receive_pcs1
(
.a1a2size(1'b0),
.a1a2sizeout(),
.a1detect(),
.a2detect(),
.adetectdeskew(),
.alignstatus(1'b0),
.alignstatussync(1'b0),
.alignstatussyncout(),
.bistdone(),
.bisterr(),
.bitslipboundaryselectout(),
.byteorderalignstatus(),
.cdrctrlearlyeios(wire_receive_pcs1_cdrctrlearlyeios),
.cdrctrllocktorefclkout(wire_receive_pcs1_cdrctrllocktorefclkout),
.clkout(),
.coreclk(rx_coreclk_in[1]),
.coreclkout(wire_receive_pcs1_coreclkout),
.ctrldetect(wire_receive_pcs1_ctrldetect),
.datain(rx_pma_recoverdataout_wire[19:10]),
.dataout(wire_receive_pcs1_dataout),
.dataoutfull(),
.digitalreset(rx_digitalreset_out[1]),
.disperr(wire_receive_pcs1_disperr),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pcsdprioin_wire[799:400]),
.dprioout(wire_receive_pcs1_dprioout),
.elecidleinfersel({3{1'b0}}),
.enabledeskew(1'b0),
.enabyteord(1'b0),
.enapatternalign(rx_enapatternalign[1]),
.errdetect(wire_receive_pcs1_errdetect),
.fifordin(1'b0),
.fifordout(),
.fiforesetrd(1'b0),
.grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[5:3]),
.hipdataout(),
.hipdatavalid(),
.hipelecidle(),
.hipphydonestatus(),
.hipstatus(),
.invpol(1'b0),
.k1detect(),
.k2detect(),
.localrefclk(tx_localrefclk[1]),
.masterclk(1'b0),
.parallelfdbk({20{1'b0}}),
.patterndetect(wire_receive_pcs1_patterndetect),
.phfifooverflow(),
.phfifordenable(rx_phfifordenable[1]),
.phfifordenableout(wire_receive_pcs1_phfifordenableout),
.phfiforeset(rx_phfiforeset[1]),
.phfiforesetout(wire_receive_pcs1_phfiforesetout),
.phfifounderflow(),
.phfifowrdisable(rx_phfifowrdisable[1]),
.phfifowrdisableout(wire_receive_pcs1_phfifowrdisableout),
.phfifox4bytesel(int_rx_phfifoxnbytesel[1]),
.phfifox4rdenable(int_rx_phfifoxnrdenable[1]),
.phfifox4wrclk(int_rx_phfifoxnwrclk[1]),
.phfifox4wrenable(int_rx_phfifoxnwrenable[1]),
.pipe8b10binvpolarity(pipe8b10binvpolarity[1]),
.pipebufferstat(),
.pipedatavalid(wire_receive_pcs1_pipedatavalid),
.pipeelecidle(wire_receive_pcs1_pipeelecidle),
.pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[1]),
.pipephydonestatus(wire_receive_pcs1_pipephydonestatus),
.pipepowerdown(tx_pipepowerdownout[3:2]),
.pipepowerstate(tx_pipepowerstateout[7:4]),
.pipestatetransdoneout(),
.pipestatus(wire_receive_pcs1_pipestatus),
.powerdn(powerdn[3:2]),
.prbscidenable(rx_prbscidenable[1]),
.quadreset(cent_unit_quadresetout[0]),
.rdalign(),
.recoveredclk(rx_pma_clockout[1]),
.refclk(refclk_pma[0]),
.revbitorderwa(1'b0),
.revparallelfdbkdata(wire_receive_pcs1_revparallelfdbkdata),
.rlv(),
.rmfifodatadeleted(),
.rmfifodatainserted(),
.rmfifoempty(),
.rmfifofull(),
.rmfifordena(1'b0),
.rmfiforeset(rx_rmfiforeset[1]),
.rmfifowrena(1'b0),
.runningdisp(),
.rxdetectvalid(tx_rxdetectvalidout[1]),
.rxfound(rx_pcs_rxfound_wire[3:2]),
.signaldetect(),
.signaldetected(rx_signaldetect_wire[1]),
.syncstatus(wire_receive_pcs1_syncstatus),
.syncstatusdeskew(),
.xauidelcondmetout(),
.xauififoovrout(),
.xauiinsertincompleteout(),
.xauilatencycompout(),
.xgmctrldet(),
.xgmctrlin(1'b0),
.xgmdatain({8{1'b0}}),
.xgmdataout(),
.xgmdatavalid(),
.xgmrunningdisp()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslip(1'b0),
.cdrctrllocktorefcl(1'b0),
.hip8b10binvpolarity(1'b0),
.hipelecidleinfersel({3{1'b0}}),
.hippowerdown({2{1'b0}}),
.pmatestbusin({8{1'b0}}),
.revbyteorderwa(1'b0),
.wareset(1'b0),
.xauidelcondmet(1'b0),
.xauififoovr(1'b0),
.xauiinsertincomplete(1'b0),
.xauilatencycomp(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pcs1.align_pattern = "0101111100",
receive_pcs1.align_pattern_length = 10,
receive_pcs1.allow_align_polarity_inversion = "false",
receive_pcs1.allow_pipe_polarity_inversion = "true",
receive_pcs1.auto_spd_deassert_ph_fifo_rst_count = 8,
receive_pcs1.auto_spd_phystatus_notify_count = 14,
receive_pcs1.bit_slip_enable = "false",
receive_pcs1.byte_order_invalid_code_or_run_disp_error = "true",
receive_pcs1.byte_order_mode = "none",
receive_pcs1.byte_order_pad_pattern = "0",
receive_pcs1.byte_order_pattern = "0",
receive_pcs1.byte_order_pld_ctrl_enable = "false",
receive_pcs1.cdrctrl_bypass_ppm_detector_cycle = 1000,
receive_pcs1.cdrctrl_cid_mode_enable = "true",
receive_pcs1.cdrctrl_enable = "true",
receive_pcs1.cdrctrl_mask_cycle = 800,
receive_pcs1.cdrctrl_min_lock_to_ref_cycle = 63,
receive_pcs1.cdrctrl_rxvalid_mask = "true",
receive_pcs1.channel_bonding = "x2",
receive_pcs1.channel_number = ((starting_channel_number + 1) % 2),
receive_pcs1.channel_width = 16,
receive_pcs1.clk1_mux_select = "recovered clock",
receive_pcs1.clk2_mux_select = "digital reference clock",
receive_pcs1.core_clock_0ppm = "false",
receive_pcs1.datapath_low_latency_mode = "false",
receive_pcs1.datapath_protocol = "pipe",
receive_pcs1.dec_8b_10b_compatibility_mode = "true",
receive_pcs1.dec_8b_10b_mode = "normal",
receive_pcs1.deskew_pattern = "0",
receive_pcs1.disable_auto_idle_insertion = "false",
receive_pcs1.disable_running_disp_in_word_align = "false",
receive_pcs1.disallow_kchar_after_pattern_ordered_set = "false",
receive_pcs1.dprio_config_mode = 6'h01,
receive_pcs1.elec_idle_gen1_sigdet_enable = "true",
receive_pcs1.elec_idle_infer_enable = "false",
receive_pcs1.elec_idle_num_com_detect = 3,
receive_pcs1.enable_bit_reversal = "false",
receive_pcs1.enable_self_test_mode = "false",
receive_pcs1.force_signal_detect_dig = "true",
receive_pcs1.hip_enable = "false",
receive_pcs1.infiniband_invalid_code = 0,
receive_pcs1.insert_pad_on_underflow = "false",
receive_pcs1.num_align_code_groups_in_ordered_set = 0,
receive_pcs1.num_align_cons_good_data = 16,
receive_pcs1.num_align_cons_pat = 4,
receive_pcs1.num_align_loss_sync_error = 17,
receive_pcs1.ph_fifo_low_latency_enable = "true",
receive_pcs1.ph_fifo_reg_mode = "false",
receive_pcs1.protocol_hint = "pcie",
receive_pcs1.rate_match_back_to_back = "false",
receive_pcs1.rate_match_delete_threshold = 13,
receive_pcs1.rate_match_empty_threshold = 5,
receive_pcs1.rate_match_fifo_mode = "true",
receive_pcs1.rate_match_full_threshold = 20,
receive_pcs1.rate_match_insert_threshold = 11,
receive_pcs1.rate_match_ordered_set_based = "false",
receive_pcs1.rate_match_pattern1 = "11010000111010000011",
receive_pcs1.rate_match_pattern2 = "00101111000101111100",
receive_pcs1.rate_match_pattern_size = 20,
receive_pcs1.rate_match_pipe_enable = "true",
receive_pcs1.rate_match_reset_enable = "false",
receive_pcs1.rate_match_skip_set_based = "true",
receive_pcs1.rate_match_start_threshold = 7,
receive_pcs1.rd_clk_mux_select = "core clock",
receive_pcs1.recovered_clk_mux_select = "recovered clock",
receive_pcs1.run_length = 40,
receive_pcs1.run_length_enable = "true",
receive_pcs1.rx_detect_bypass = "false",
receive_pcs1.rx_phfifo_wait_cnt = 32,
receive_pcs1.rxstatus_error_report_mode = 1,
receive_pcs1.self_test_mode = "incremental",
receive_pcs1.use_alignment_state_machine = "true",
receive_pcs1.use_deskew_fifo = "false",
receive_pcs1.use_double_data_mode = "true",
receive_pcs1.use_parallel_loopback = "false",
receive_pcs1.lpm_type = "cycloneiv_hssi_rx_pcs";
cycloneiv_hssi_rx_pma receive_pma0
(
.analogtestbus(wire_receive_pma0_analogtestbus),
.clockout(wire_receive_pma0_clockout),
.crupowerdn(cent_unit_rxcrupowerdn[0]),
.datain(rx_datain[0]),
.datastrobeout(),
.deserclock(rx_deserclock_in[0]),
.diagnosticlpbkout(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pmadprioin_wire[299:0]),
.dprioout(wire_receive_pma0_dprioout),
.freqlocked(wire_receive_pma0_freqlocked),
.locktodata(((~ reconfig_togxb_busy) & rx_locktodata[0])),
.locktoref(rx_locktorefclk_wire[0]),
.locktorefout(wire_receive_pma0_locktorefout),
.powerdn(cent_unit_rxibpowerdn[0]),
.ppmdetectrefclk(rx_pll_pfdrefclkout_wire[0]),
.recoverdataout(wire_receive_pma0_recoverdataout),
.reverselpbkout(),
.rxpmareset(rx_analogreset_out[0]),
.seriallpbkin(1'b0),
.signaldetect(wire_receive_pma0_signaldetect),
.testbussel(4'b0110)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dpashift(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pma0.allow_serial_loopback = "false",
receive_pma0.channel_number = ((starting_channel_number + 0) % 2),
receive_pma0.common_mode = "0.82V",
receive_pma0.deserialization_factor = 10,
receive_pma0.dprio_config_mode = 6'h01,
receive_pma0.effective_data_rate = "2500 Mbps",
receive_pma0.enable_local_divider = "false",
receive_pma0.enable_ltd = "false",
receive_pma0.enable_ltr = "false",
receive_pma0.enable_pd2_deadzone_detection = "true",
receive_pma0.enable_second_order_loop = "false",
receive_pma0.eq_dc_gain = 3,
receive_pma0.eq_setting = 1,
receive_pma0.force_signal_detect = "false",
receive_pma0.logical_channel_address = (starting_channel_number + 0),
receive_pma0.loop_1_digital_filter = 8,
receive_pma0.offset_cancellation = 1,
receive_pma0.power_down_pd2_clocks = "false",
receive_pma0.ppm_gen1_2_xcnt_en = 1,
receive_pma0.ppm_post_eidle = 0,
receive_pma0.ppmselect = 8,
receive_pma0.protocol_hint = "pcie",
receive_pma0.signal_detect_hysteresis = 4,
receive_pma0.signal_detect_hysteresis_valid_threshold = 14,
receive_pma0.signal_detect_loss_threshold = 3,
receive_pma0.termination = "OCT 85 Ohms",
receive_pma0.use_external_termination = "false",
receive_pma0.lpm_type = "cycloneiv_hssi_rx_pma";
cycloneiv_hssi_rx_pma receive_pma1
(
.analogtestbus(wire_receive_pma1_analogtestbus),
.clockout(wire_receive_pma1_clockout),
.crupowerdn(cent_unit_rxcrupowerdn[1]),
.datain(rx_datain[1]),
.datastrobeout(),
.deserclock(rx_deserclock_in[1]),
.diagnosticlpbkout(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pmadprioin_wire[599:300]),
.dprioout(wire_receive_pma1_dprioout),
.freqlocked(wire_receive_pma1_freqlocked),
.locktodata(((~ reconfig_togxb_busy) & rx_locktodata[1])),
.locktoref(rx_locktorefclk_wire[1]),
.locktorefout(wire_receive_pma1_locktorefout),
.powerdn(cent_unit_rxibpowerdn[1]),
.ppmdetectrefclk(rx_pll_pfdrefclkout_wire[1]),
.recoverdataout(wire_receive_pma1_recoverdataout),
.reverselpbkout(),
.rxpmareset(rx_analogreset_out[1]),
.seriallpbkin(1'b0),
.signaldetect(wire_receive_pma1_signaldetect),
.testbussel(4'b0110)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dpashift(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pma1.allow_serial_loopback = "false",
receive_pma1.channel_number = ((starting_channel_number + 1) % 2),
receive_pma1.common_mode = "0.82V",
receive_pma1.deserialization_factor = 10,
receive_pma1.dprio_config_mode = 6'h01,
receive_pma1.effective_data_rate = "2500 Mbps",
receive_pma1.enable_local_divider = "false",
receive_pma1.enable_ltd = "false",
receive_pma1.enable_ltr = "false",
receive_pma1.enable_pd2_deadzone_detection = "true",
receive_pma1.enable_second_order_loop = "false",
receive_pma1.eq_dc_gain = 3,
receive_pma1.eq_setting = 1,
receive_pma1.force_signal_detect = "false",
receive_pma1.logical_channel_address = (starting_channel_number + 1),
receive_pma1.loop_1_digital_filter = 8,
receive_pma1.offset_cancellation = 1,
receive_pma1.power_down_pd2_clocks = "false",
receive_pma1.ppm_gen1_2_xcnt_en = 1,
receive_pma1.ppm_post_eidle = 0,
receive_pma1.ppmselect = 8,
receive_pma1.protocol_hint = "pcie",
receive_pma1.signal_detect_hysteresis = 4,
receive_pma1.signal_detect_hysteresis_valid_threshold = 14,
receive_pma1.signal_detect_loss_threshold = 3,
receive_pma1.termination = "OCT 85 Ohms",
receive_pma1.use_external_termination = "false",
receive_pma1.lpm_type = "cycloneiv_hssi_rx_pma";
cycloneiv_hssi_tx_pcs transmit_pcs0
(
.clkout(),
.coreclk(tx_coreclk_in[0]),
.coreclkout(wire_transmit_pcs0_coreclkout),
.ctrlenable({tx_ctrlenable[1:0]}),
.datain({{4{1'b0}}, tx_datain_wire[15:0]}),
.dataout(wire_transmit_pcs0_dataout),
.detectrxloop(tx_detectrxloop[0]),
.digitalreset(tx_digitalreset_out[0]),
.dispval({2{tx_forceelecidle[0]}}),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_dprioin_wire[149:0]),
.dprioout(wire_transmit_pcs0_dprioout),
.elecidleinfersel(rx_elecidleinfersel[2:0]),
.enrevparallellpbk(tx_revparallellpbken[0]),
.forcedisp({tx_forcedisp_wire[1:0]}),
.forceelecidle(tx_forceelecidle[0]),
.forceelecidleout(wire_transmit_pcs0_forceelecidleout),
.grayelecidleinferselout(wire_transmit_pcs0_grayelecidleinferselout),
.hiptxclkout(),
.invpol(tx_invpolarity[0]),
.localrefclk(tx_localrefclk[0]),
.parallelfdbkout(),
.phfifooverflow(),
.phfiforddisable(1'b0),
.phfiforddisableout(wire_transmit_pcs0_phfiforddisableout),
.phfiforeset(tx_phfiforeset[0]),
.phfiforesetout(wire_transmit_pcs0_phfiforesetout),
.phfifounderflow(),
.phfifowrenable(1'b1),
.phfifowrenableout(wire_transmit_pcs0_phfifowrenableout),
.phfifox4bytesel(int_tx_phfifoxnbytesel[0]),
.phfifox4rdclk(int_tx_phfifoxnrdclk[0]),
.phfifox4rdenable(int_tx_phfifoxnrdenable[0]),
.phfifox4wrenable(int_tx_phfifoxnwrenable[0]),
.pipeenrevparallellpbkout(wire_transmit_pcs0_pipeenrevparallellpbkout),
.pipepowerdownout(wire_transmit_pcs0_pipepowerdownout),
.pipepowerstateout(wire_transmit_pcs0_pipepowerstateout),
.pipestatetransdone(1'b0),
.powerdn(powerdn[1:0]),
.quadreset(cent_unit_quadresetout[0]),
.rdenablesync(),
.refclk(refclk_pma[0]),
.revparallelfdbk(rx_revparallelfdbkdata[19:0]),
.txdetectrx(wire_transmit_pcs0_txdetectrx),
.xgmctrlenable(),
.xgmdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslipboundaryselect({5{1'b0}}),
.datainfull({22{1'b0}}),
.hipdatain({10{1'b0}}),
.hipdetectrxloop(1'b0),
.hipelecidleinfersel({3{1'b0}}),
.hipforceelecidle(1'b0),
.hippowerdn({2{1'b0}}),
.pipetxswing(1'b0),
.prbscidenable(1'b0),
.xgmctrl(1'b0),
.xgmdatain({8{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pcs0.allow_polarity_inversion = "false",
transmit_pcs0.bitslip_enable = "false",
transmit_pcs0.channel_bonding = "x2",
transmit_pcs0.channel_number = ((starting_channel_number + 0) % 2),
transmit_pcs0.channel_width = 16,
transmit_pcs0.core_clock_0ppm = "false",
transmit_pcs0.datapath_low_latency_mode = "false",
transmit_pcs0.datapath_protocol = "pipe",
transmit_pcs0.disable_ph_low_latency_mode = "false",
transmit_pcs0.disparity_mode = "new",
transmit_pcs0.dprio_config_mode = 6'h01,
transmit_pcs0.elec_idle_delay = 4,
transmit_pcs0.enable_bit_reversal = "false",
transmit_pcs0.enable_idle_selection = "false",
transmit_pcs0.enable_reverse_parallel_loopback = "true",
transmit_pcs0.enable_self_test_mode = "false",
transmit_pcs0.enc_8b_10b_compatibility_mode = "true",
transmit_pcs0.enc_8b_10b_mode = "normal",
transmit_pcs0.hip_enable = "false",
transmit_pcs0.ph_fifo_reg_mode = "false",
transmit_pcs0.prbs_cid_pattern = "false",
transmit_pcs0.protocol_hint = "pcie",
transmit_pcs0.refclk_select = "central",
transmit_pcs0.self_test_mode = "incremental",
transmit_pcs0.use_double_data_mode = "true",
transmit_pcs0.wr_clk_mux_select = "core_clk",
transmit_pcs0.lpm_type = "cycloneiv_hssi_tx_pcs";
cycloneiv_hssi_tx_pcs transmit_pcs1
(
.clkout(),
.coreclk(tx_coreclk_in[1]),
.coreclkout(wire_transmit_pcs1_coreclkout),
.ctrlenable({tx_ctrlenable[3:2]}),
.datain({{4{1'b0}}, tx_datain_wire[31:16]}),
.dataout(wire_transmit_pcs1_dataout),
.detectrxloop(tx_detectrxloop[1]),
.digitalreset(tx_digitalreset_out[1]),
.dispval({2{tx_forceelecidle[1]}}),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_dprioin_wire[299:150]),
.dprioout(wire_transmit_pcs1_dprioout),
.elecidleinfersel(rx_elecidleinfersel[5:3]),
.enrevparallellpbk(tx_revparallellpbken[1]),
.forcedisp({tx_forcedisp_wire[3:2]}),
.forceelecidle(tx_forceelecidle[1]),
.forceelecidleout(wire_transmit_pcs1_forceelecidleout),
.grayelecidleinferselout(wire_transmit_pcs1_grayelecidleinferselout),
.hiptxclkout(),
.invpol(tx_invpolarity[1]),
.localrefclk(tx_localrefclk[1]),
.parallelfdbkout(),
.phfifooverflow(),
.phfiforddisable(1'b0),
.phfiforddisableout(wire_transmit_pcs1_phfiforddisableout),
.phfiforeset(tx_phfiforeset[1]),
.phfiforesetout(wire_transmit_pcs1_phfiforesetout),
.phfifounderflow(),
.phfifowrenable(1'b1),
.phfifowrenableout(wire_transmit_pcs1_phfifowrenableout),
.phfifox4bytesel(int_tx_phfifoxnbytesel[1]),
.phfifox4rdclk(int_tx_phfifoxnrdclk[1]),
.phfifox4rdenable(int_tx_phfifoxnrdenable[1]),
.phfifox4wrenable(int_tx_phfifoxnwrenable[1]),
.pipeenrevparallellpbkout(wire_transmit_pcs1_pipeenrevparallellpbkout),
.pipepowerdownout(wire_transmit_pcs1_pipepowerdownout),
.pipepowerstateout(wire_transmit_pcs1_pipepowerstateout),
.pipestatetransdone(1'b0),
.powerdn(powerdn[3:2]),
.quadreset(cent_unit_quadresetout[0]),
.rdenablesync(),
.refclk(refclk_pma[0]),
.revparallelfdbk(rx_revparallelfdbkdata[39:20]),
.txdetectrx(wire_transmit_pcs1_txdetectrx),
.xgmctrlenable(),
.xgmdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslipboundaryselect({5{1'b0}}),
.datainfull({22{1'b0}}),
.hipdatain({10{1'b0}}),
.hipdetectrxloop(1'b0),
.hipelecidleinfersel({3{1'b0}}),
.hipforceelecidle(1'b0),
.hippowerdn({2{1'b0}}),
.pipetxswing(1'b0),
.prbscidenable(1'b0),
.xgmctrl(1'b0),
.xgmdatain({8{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pcs1.allow_polarity_inversion = "false",
transmit_pcs1.bitslip_enable = "false",
transmit_pcs1.channel_bonding = "x2",
transmit_pcs1.channel_number = ((starting_channel_number + 1) % 2),
transmit_pcs1.channel_width = 16,
transmit_pcs1.core_clock_0ppm = "false",
transmit_pcs1.datapath_low_latency_mode = "false",
transmit_pcs1.datapath_protocol = "pipe",
transmit_pcs1.disable_ph_low_latency_mode = "false",
transmit_pcs1.disparity_mode = "new",
transmit_pcs1.dprio_config_mode = 6'h01,
transmit_pcs1.elec_idle_delay = 4,
transmit_pcs1.enable_bit_reversal = "false",
transmit_pcs1.enable_idle_selection = "false",
transmit_pcs1.enable_reverse_parallel_loopback = "true",
transmit_pcs1.enable_self_test_mode = "false",
transmit_pcs1.enc_8b_10b_compatibility_mode = "true",
transmit_pcs1.enc_8b_10b_mode = "normal",
transmit_pcs1.hip_enable = "false",
transmit_pcs1.ph_fifo_reg_mode = "false",
transmit_pcs1.prbs_cid_pattern = "false",
transmit_pcs1.protocol_hint = "pcie",
transmit_pcs1.refclk_select = "central",
transmit_pcs1.self_test_mode = "incremental",
transmit_pcs1.use_double_data_mode = "true",
transmit_pcs1.wr_clk_mux_select = "core_clk",
transmit_pcs1.lpm_type = "cycloneiv_hssi_tx_pcs";
cycloneiv_hssi_tx_pma transmit_pma0
(
.cgbpowerdn(cent_unit_txdividerpowerdown[0]),
.clockout(wire_transmit_pma0_clockout),
.datain({tx_dataout_pcs_to_pma[9:0]}),
.dataout(wire_transmit_pma0_dataout),
.detectrxpowerdown(cent_unit_txdetectrxpowerdn[0]),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_pmadprioin_wire[299:0]),
.dprioout(wire_transmit_pma0_dprioout),
.fastrefclk0in(tx_pma_fastrefclk0in[0]),
.forceelecidle(tx_pcs_forceelecidleout[0]),
.powerdn(cent_unit_txobpowerdn[0]),
.refclk0in(tx_pma_refclk0in[0]),
.refclk0inpulse(tx_pma_refclk0inpulse[0]),
.reverselpbkin(1'b0),
.rxdetecten(txdetectrxout[0]),
.rxdetectvalidout(wire_transmit_pma0_rxdetectvalidout),
.rxfoundout(wire_transmit_pma0_rxfoundout),
.seriallpbkout(),
.txpmareset(tx_analogreset_out[0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.diagnosticlpbkin(1'b0),
.rxdetectclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pma0.channel_number = ((starting_channel_number + 0) % 2),
transmit_pma0.common_mode = "0.65V",
transmit_pma0.dprio_config_mode = 6'h01,
transmit_pma0.effective_data_rate = "2500 Mbps",
transmit_pma0.enable_reverse_serial_loopback = "false",
transmit_pma0.logical_channel_address = (starting_channel_number + 0),
transmit_pma0.preemp_tap_1 = 18,
transmit_pma0.protocol_hint = "pcie",
transmit_pma0.rx_detect = 0,
transmit_pma0.serialization_factor = 10,
transmit_pma0.slew_rate = "low",
transmit_pma0.termination = "OCT 100 Ohms",
transmit_pma0.use_external_termination = "false",
transmit_pma0.use_rx_detect = "true",
transmit_pma0.vod_selection = 5,
transmit_pma0.lpm_type = "cycloneiv_hssi_tx_pma";
cycloneiv_hssi_tx_pma transmit_pma1
(
.cgbpowerdn(cent_unit_txdividerpowerdown[1]),
.clockout(wire_transmit_pma1_clockout),
.datain({tx_dataout_pcs_to_pma[19:10]}),
.dataout(wire_transmit_pma1_dataout),
.detectrxpowerdown(cent_unit_txdetectrxpowerdn[1]),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_pmadprioin_wire[599:300]),
.dprioout(wire_transmit_pma1_dprioout),
.fastrefclk0in(tx_pma_fastrefclk0in[1]),
.forceelecidle(tx_pcs_forceelecidleout[1]),
.powerdn(cent_unit_txobpowerdn[1]),
.refclk0in(tx_pma_refclk0in[1]),
.refclk0inpulse(tx_pma_refclk0inpulse[1]),
.reverselpbkin(1'b0),
.rxdetecten(txdetectrxout[1]),
.rxdetectvalidout(wire_transmit_pma1_rxdetectvalidout),
.rxfoundout(wire_transmit_pma1_rxfoundout),
.seriallpbkout(),
.txpmareset(tx_analogreset_out[1])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.diagnosticlpbkin(1'b0),
.rxdetectclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pma1.channel_number = ((starting_channel_number + 1) % 2),
transmit_pma1.common_mode = "0.65V",
transmit_pma1.dprio_config_mode = 6'h01,
transmit_pma1.effective_data_rate = "2500 Mbps",
transmit_pma1.enable_reverse_serial_loopback = "false",
transmit_pma1.logical_channel_address = (starting_channel_number + 1),
transmit_pma1.preemp_tap_1 = 18,
transmit_pma1.protocol_hint = "pcie",
transmit_pma1.rx_detect = 0,
transmit_pma1.serialization_factor = 10,
transmit_pma1.slew_rate = "low",
transmit_pma1.termination = "OCT 100 Ohms",
transmit_pma1.use_external_termination = "false",
transmit_pma1.use_rx_detect = "true",
transmit_pma1.vod_selection = 5,
transmit_pma1.lpm_type = "cycloneiv_hssi_tx_pma";
// synopsys translate_off
initial
fixedclk_div = 0;
// synopsys translate_on
always @ ( posedge fixedclk)
fixedclk_div <= (~ fixedclk_div_in);
// synopsys translate_off
initial
reconfig_togxb_busy_reg = 0;
// synopsys translate_on
always @ ( negedge fixedclk)
reconfig_togxb_busy_reg <= {reconfig_togxb_busy_reg[0], reconfig_togxb_busy};
assign
cal_blk_powerdown = 1'b0,
cent_unit_quadresetout = {1'b0, wire_cent_unit0_quadresetout},
cent_unit_rxcrupowerdn = {wire_cent_unit0_rxcrupowerdown[1:0]},
cent_unit_rxibpowerdn = {wire_cent_unit0_rxibpowerdown[1:0]},
cent_unit_rxpcsdprioin = {rx_pcsdprioout[799:0]},
cent_unit_rxpcsdprioout = {wire_cent_unit0_rxpcsdprioout[799:0]},
cent_unit_rxpmadprioin = {rx_pmadprioout[599:0]},
cent_unit_rxpmadprioout = {wire_cent_unit0_rxpmadprioout[599:0]},
cent_unit_tx_dprioin = {tx_txdprioout[299:0]},
cent_unit_txdetectrxpowerdn = {wire_cent_unit0_txdetectrxpowerdown[1:0]},
cent_unit_txdividerpowerdown = {wire_cent_unit0_txdividerpowerdown[1:0]},
cent_unit_txdprioout = {wire_cent_unit0_txpcsdprioout[299:0]},
cent_unit_txobpowerdn = {wire_cent_unit0_txobpowerdown[1:0]},
cent_unit_txpmadprioin = {tx_pmadprioout[599:0]},
cent_unit_txpmadprioout = {wire_cent_unit0_txpmadprioout[599:0]},
coreclkout = {coreclkout_wire[0]},
coreclkout_wire = {wire_cent_unit0_coreclkout},
fixedclk_div_in = fixedclk_div,
fixedclk_enable = reconfig_togxb_busy_reg[0],
fixedclk_fast = {4{1'b1}},
fixedclk_sel = reconfig_togxb_busy_reg[1],
fixedclk_to_cmu = {((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[1]) & fixedclk_div_in) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk)), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[0]) & fixedclk_div_in) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk))},
grayelecidleinfersel_from_tx = {wire_transmit_pcs1_grayelecidleinferselout, wire_transmit_pcs0_grayelecidleinferselout},
int_pipeenrevparallellpbkfromtx = {wire_transmit_pcs1_pipeenrevparallellpbkout, wire_transmit_pcs0_pipeenrevparallellpbkout},
int_rx_coreclkout = {wire_receive_pcs1_coreclkout, wire_receive_pcs0_coreclkout},
int_rx_phfifordenableout = {wire_receive_pcs1_phfifordenableout, wire_receive_pcs0_phfifordenableout},
int_rx_phfiforesetout = {wire_receive_pcs1_phfiforesetout, wire_receive_pcs0_phfiforesetout},
int_rx_phfifowrdisableout = {wire_receive_pcs1_phfifowrdisableout, wire_receive_pcs0_phfifowrdisableout},
int_rx_phfifoxnbytesel = {2{int_rxphfifox4byteselout[0]}},
int_rx_phfifoxnrdenable = {2{int_rxphfifox4rdenableout[0]}},
int_rx_phfifoxnwrclk = {2{int_rxphfifox4wrclkout[0]}},
int_rx_phfifoxnwrenable = {2{int_rxphfifox4wrenableout[0]}},
int_rxcoreclk = {int_rx_coreclkout[0]},
int_rxphfifordenable = {int_rx_phfifordenableout[0]},
int_rxphfiforeset = {int_rx_phfiforesetout[0]},
int_rxphfifox4byteselout = {wire_cent_unit0_rxphfifox4byteselout},
int_rxphfifox4rdenableout = {wire_cent_unit0_rxphfifox4rdenableout},
int_rxphfifox4wrclkout = {wire_cent_unit0_rxphfifox4wrclkout},
int_rxphfifox4wrenableout = {wire_cent_unit0_rxphfifox4wrenableout},
int_tx_coreclkout = {wire_transmit_pcs1_coreclkout, wire_transmit_pcs0_coreclkout},
int_tx_phfiforddisableout = {wire_transmit_pcs1_phfiforddisableout, wire_transmit_pcs0_phfiforddisableout},
int_tx_phfiforesetout = {wire_transmit_pcs1_phfiforesetout, wire_transmit_pcs0_phfiforesetout},
int_tx_phfifowrenableout = {wire_transmit_pcs1_phfifowrenableout, wire_transmit_pcs0_phfifowrenableout},
int_tx_phfifoxnbytesel = {2{int_txphfifox4byteselout[0]}},
int_tx_phfifoxnrdclk = {2{int_txphfifox4rdclkout[0]}},
int_tx_phfifoxnrdenable = {2{int_txphfifox4rdenableout[0]}},
int_tx_phfifoxnwrenable = {2{int_txphfifox4wrenableout[0]}},
int_txcoreclk = {int_tx_coreclkout[0]},
int_txphfiforddisable = {int_tx_phfiforddisableout[0]},
int_txphfiforeset = {int_tx_phfiforesetout[0]},
int_txphfifowrenable = {int_tx_phfifowrenableout[0]},
int_txphfifox4byteselout = {wire_cent_unit0_txphfifox4byteselout},
int_txphfifox4rdclkout = {wire_cent_unit0_txphfifox4rdclkout},
int_txphfifox4rdenableout = {wire_cent_unit0_txphfifox4rdenableout},
int_txphfifox4wrenableout = {wire_cent_unit0_txphfifox4wrenableout},
nonusertocmu_out = {wire_cal_blk0_nonusertocmu},
pipedatavalid = {pipedatavalid_out[1:0]},
pipedatavalid_out = {wire_receive_pcs1_pipedatavalid, wire_receive_pcs0_pipedatavalid},
pipeelecidle = {pipeelecidle_out[1:0]},
pipeelecidle_out = {wire_receive_pcs1_pipeelecidle, wire_receive_pcs0_pipeelecidle},
pipephydonestatus = {wire_receive_pcs1_pipephydonestatus, wire_receive_pcs0_pipephydonestatus},
pipestatus = {wire_receive_pcs1_pipestatus, wire_receive_pcs0_pipestatus},
pll_locked = {wire_pll0_locked},
pll_powerdown = 1'b0,
reconfig_fromgxb = {rx_pma_analogtestbus[4:1], wire_cent_unit0_dprioout},
reconfig_togxb_busy = reconfig_togxb[3],
reconfig_togxb_disable = reconfig_togxb[1],
reconfig_togxb_in = reconfig_togxb[0],
reconfig_togxb_load = reconfig_togxb[2],
refclk_pma = {wire_cent_unit0_refclkout},
rx_analogreset_in = {2{((~ reconfig_togxb_busy) & rx_analogreset[0])}},
rx_analogreset_out = {wire_cent_unit0_rxanalogresetout[1:0]},
rx_coreclk_in = {2{coreclkout_wire[0]}},
rx_ctrldetect = {wire_receive_pcs1_ctrldetect[1:0], wire_receive_pcs0_ctrldetect[1:0]},
rx_dataout = {rx_out_wire[31:0]},
rx_deserclock_in = {2{wire_pll0_icdrclk}},
rx_digitalreset_in = {2{rx_digitalreset[0]}},
rx_digitalreset_out = {wire_cent_unit0_rxdigitalresetout[1:0]},
rx_disperr = {wire_receive_pcs1_disperr[1:0], wire_receive_pcs0_disperr[1:0]},
rx_elecidleinfersel = {6{1'b0}},
rx_enapatternalign = {2{1'b0}},
rx_errdetect = {wire_receive_pcs1_errdetect[1:0], wire_receive_pcs0_errdetect[1:0]},
rx_freqlocked = {(wire_receive_pma1_freqlocked & (~ rx_analogreset[0])), (wire_receive_pma0_freqlocked & (~ rx_analogreset[0]))},
rx_locktodata = {2{1'b0}},
rx_locktorefclk_wire = {wire_receive_pcs1_cdrctrllocktorefclkout, wire_receive_pcs0_cdrctrllocktorefclkout},
rx_out_wire = {wire_receive_pcs1_dataout[15:0], wire_receive_pcs0_dataout[15:0]},
rx_patterndetect = {wire_receive_pcs1_patterndetect[1:0], wire_receive_pcs0_patterndetect[1:0]},
rx_pcs_rxfound_wire = {txdetectrxout[1], tx_rxfoundout[1], txdetectrxout[0], tx_rxfoundout[0]},
rx_pcsdprioin_wire = {cent_unit_rxpcsdprioout[799:0]},
rx_pcsdprioout = {wire_receive_pcs1_dprioout, wire_receive_pcs0_dprioout},
rx_phfifordenable = {2{1'b1}},
rx_phfiforeset = {2{1'b0}},
rx_phfifowrdisable = {2{1'b0}},
rx_pll_pfdrefclkout_wire = {2{wire_pll0_fref}},
rx_pma_analogtestbus = {{3{1'b0}}, wire_receive_pma1_analogtestbus[6], wire_receive_pma0_analogtestbus[6]},
rx_pma_clockout = {wire_receive_pma1_clockout, wire_receive_pma0_clockout},
rx_pma_recoverdataout_wire = {wire_receive_pma1_recoverdataout[9:0], wire_receive_pma0_recoverdataout[9:0]},
rx_pmadprioin_wire = {cent_unit_rxpmadprioout[599:0]},
rx_pmadprioout = {wire_receive_pma1_dprioout, wire_receive_pma0_dprioout},
rx_powerdown = {2{1'b0}},
rx_powerdown_in = {rx_powerdown[1:0]},
rx_prbscidenable = {2{1'b0}},
rx_revparallelfdbkdata = {wire_receive_pcs1_revparallelfdbkdata, wire_receive_pcs0_revparallelfdbkdata},
rx_rmfiforeset = {2{1'b0}},
rx_signaldetect_wire = {wire_receive_pma1_signaldetect, wire_receive_pma0_signaldetect},
rx_syncstatus = {wire_receive_pcs1_syncstatus[1:0], wire_receive_pcs0_syncstatus[1:0]},
rxphfifowrdisable = {int_rx_phfifowrdisableout[0]},
tx_analogreset_out = {wire_cent_unit0_txanalogresetout[1:0]},
tx_coreclk_in = {2{coreclkout_wire[0]}},
tx_datain_wire = {tx_datain[31:0]},
tx_dataout = {txdataout[1:0]},
tx_dataout_pcs_to_pma = {wire_transmit_pcs1_dataout[9:0], wire_transmit_pcs0_dataout[9:0]},
tx_digitalreset_in = {2{tx_digitalreset[0]}},
tx_digitalreset_out = {wire_cent_unit0_txdigitalresetout[1:0]},
tx_dprioin_wire = {cent_unit_txdprioout[299:0]},
tx_forcedisp_wire = {1'b0, tx_forcedispcompliance[1], 1'b0, tx_forcedispcompliance[0]},
tx_invpolarity = {2{1'b0}},
tx_localrefclk = {wire_transmit_pma1_clockout, wire_transmit_pma0_clockout},
tx_pcs_forceelecidleout = {wire_transmit_pcs1_forceelecidleout, wire_transmit_pcs0_forceelecidleout},
tx_phfiforeset = {2{1'b0}},
tx_pipepowerdownout = {wire_transmit_pcs1_pipepowerdownout, wire_transmit_pcs0_pipepowerdownout},
tx_pipepowerstateout = {wire_transmit_pcs1_pipepowerstateout, wire_transmit_pcs0_pipepowerstateout},
tx_pma_fastrefclk0in = {2{wire_pll0_clk[0]}},
tx_pma_refclk0in = {2{wire_pll0_clk[1]}},
tx_pma_refclk0inpulse = {2{wire_pll0_clk[2]}},
tx_pmadprioin_wire = {cent_unit_txpmadprioout[599:0]},
tx_pmadprioout = {wire_transmit_pma1_dprioout, wire_transmit_pma0_dprioout},
tx_revparallellpbken = {2{1'b0}},
tx_rxdetectvalidout = {wire_transmit_pma1_rxdetectvalidout, wire_transmit_pma0_rxdetectvalidout},
tx_rxfoundout = {wire_transmit_pma1_rxfoundout, wire_transmit_pma0_rxfoundout},
tx_txdprioout = {wire_transmit_pcs1_dprioout, wire_transmit_pcs0_dprioout},
txdataout = {wire_transmit_pma1_dataout, wire_transmit_pma0_dataout},
txdetectrxout = {wire_transmit_pcs1_txdetectrx, wire_transmit_pcs0_txdetectrx},
w_cent_unit_dpriodisableout1w = {wire_cent_unit0_dpriodisableout};
initial/*synthesis enable_verilog_initial_construct*/
begin
$display("Warning: MGL_INTERNAL_WARNING: ( The parameter value is not one of the pre-specified values in the value list.) alt_c3gxb|receiver_termination The value assigned is oct_100_ohms and the valid value list is OCT_85_OHMS|OCT_150_OHMS");
end
endmodule //altpcie_serdes_3cgx_x2d_gen1_08p_alt_c3gxb_om78
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altpcie_serdes_3cgx_x2d_gen1_08p (
cal_blk_clk,
fixedclk,
gxb_powerdown,
pipe8b10binvpolarity,
pll_areset,
pll_inclk,
powerdn,
reconfig_clk,
reconfig_togxb,
rx_analogreset,
rx_datain,
rx_digitalreset,
tx_ctrlenable,
tx_datain,
tx_detectrxloop,
tx_digitalreset,
tx_forcedispcompliance,
tx_forceelecidle,
coreclkout,
pipedatavalid,
pipeelecidle,
pipephydonestatus,
pipestatus,
pll_locked,
reconfig_fromgxb,
rx_ctrldetect,
rx_dataout,
rx_disperr,
rx_errdetect,
rx_freqlocked,
rx_patterndetect,
rx_syncstatus,
tx_dataout)/* synthesis synthesis_clearbox = 2 */;
input cal_blk_clk;
input fixedclk;
input [0:0] gxb_powerdown;
input [1:0] pipe8b10binvpolarity;
input [0:0] pll_areset;
input [0:0] pll_inclk;
input [3:0] powerdn;
input reconfig_clk;
input [3:0] reconfig_togxb;
input [0:0] rx_analogreset;
input [1:0] rx_datain;
input [0:0] rx_digitalreset;
input [3:0] tx_ctrlenable;
input [31:0] tx_datain;
input [1:0] tx_detectrxloop;
input [0:0] tx_digitalreset;
input [1:0] tx_forcedispcompliance;
input [1:0] tx_forceelecidle;
output [0:0] coreclkout;
output [1:0] pipedatavalid;
output [1:0] pipeelecidle;
output [1:0] pipephydonestatus;
output [5:0] pipestatus;
output [0:0] pll_locked;
output [4:0] reconfig_fromgxb;
output [3:0] rx_ctrldetect;
output [31:0] rx_dataout;
output [3:0] rx_disperr;
output [3:0] rx_errdetect;
output [1:0] rx_freqlocked;
output [3:0] rx_patterndetect;
output [3:0] rx_syncstatus;
output [1:0] tx_dataout;
parameter starting_channel_number = 0;
wire [3:0] sub_wire0;
wire [1:0] sub_wire1;
wire [0:0] sub_wire2;
wire [4:0] sub_wire3;
wire [1:0] sub_wire4;
wire [5:0] sub_wire5;
wire [3:0] sub_wire6;
wire [3:0] sub_wire7;
wire [0:0] sub_wire8;
wire [31:0] sub_wire9;
wire [3:0] sub_wire10;
wire [1:0] sub_wire11;
wire [1:0] sub_wire12;
wire [3:0] sub_wire13;
wire [1:0] sub_wire14;
wire [3:0] rx_patterndetect = sub_wire0[3:0];
wire [1:0] pipephydonestatus = sub_wire1[1:0];
wire [0:0] pll_locked = sub_wire2[0:0];
wire [4:0] reconfig_fromgxb = sub_wire3[4:0];
wire [1:0] rx_freqlocked = sub_wire4[1:0];
wire [5:0] pipestatus = sub_wire5[5:0];
wire [3:0] rx_disperr = sub_wire6[3:0];
wire [3:0] rx_syncstatus = sub_wire7[3:0];
wire [0:0] coreclkout = sub_wire8[0:0];
wire [31:0] rx_dataout = sub_wire9[31:0];
wire [3:0] rx_errdetect = sub_wire10[3:0];
wire [1:0] pipeelecidle = sub_wire11[1:0];
wire [1:0] tx_dataout = sub_wire12[1:0];
wire [3:0] rx_ctrldetect = sub_wire13[3:0];
wire [1:0] pipedatavalid = sub_wire14[1:0];
altpcie_serdes_3cgx_x2d_gen1_08p_alt_c3gxb_om78 altpcie_serdes_3cgx_x2d_gen1_08p_alt_c3gxb_om78_component (
.reconfig_togxb (reconfig_togxb),
.cal_blk_clk (cal_blk_clk),
.tx_forceelecidle (tx_forceelecidle),
.fixedclk (fixedclk),
.rx_datain (rx_datain),
.rx_digitalreset (rx_digitalreset),
.pll_areset (pll_areset),
.pipe8b10binvpolarity (pipe8b10binvpolarity),
.tx_datain (tx_datain),
.tx_digitalreset (tx_digitalreset),
.gxb_powerdown (gxb_powerdown),
.tx_forcedispcompliance (tx_forcedispcompliance),
.reconfig_clk (reconfig_clk),
.rx_analogreset (rx_analogreset),
.powerdn (powerdn),
.tx_ctrlenable (tx_ctrlenable),
.pll_inclk (pll_inclk),
.tx_detectrxloop (tx_detectrxloop),
.rx_patterndetect (sub_wire0),
.pipephydonestatus (sub_wire1),
.pll_locked (sub_wire2),
.reconfig_fromgxb (sub_wire3),
.rx_freqlocked (sub_wire4),
.pipestatus (sub_wire5),
.rx_disperr (sub_wire6),
.rx_syncstatus (sub_wire7),
.coreclkout (sub_wire8),
.rx_dataout (sub_wire9),
.rx_errdetect (sub_wire10),
.pipeelecidle (sub_wire11),
.tx_dataout (sub_wire12),
.rx_ctrldetect (sub_wire13),
.pipedatavalid (sub_wire14))/* synthesis synthesis_clearbox=2
clearbox_macroname = alt_c3gxb
clearbox_defparam = "effective_data_rate=2500 Mbps;enable_lc_tx_pll=false;enable_pll_inclk_alt_drive_rx_cru=true;enable_pll_inclk_drive_rx_cru=true;equalizer_dcgain_setting=1;gen_reconfig_pll=false;gx_channel_type=;input_clock_frequency=100.0 MHz;intended_device_family=Cyclone IV GX;intended_device_speed_grade=6;intended_device_variant=ANY;loopback_mode=none;lpm_type=alt_c3gxb;number_of_channels=2;operation_mode=duplex;pll_bandwidth_type=Auto;pll_control_width=1;pll_inclk_period=10000;pll_pfd_fb_mode=internal;preemphasis_ctrl_1stposttap_setting=18;protocol=pcie;receiver_termination=oct_100_ohms;reconfig_dprio_mode=0;rx_8b_10b_mode=normal;rx_align_pattern=0101111100;rx_align_pattern_length=10;rx_allow_align_polarity_inversion=false;rx_allow_pipe_polarity_inversion=true;rx_bitslip_enable=false;rx_byte_ordering_mode=NONE;rx_channel_bonding=x2;rx_channel_width=16;rx_common_mode=0.82v;rx_cru_inclock0_period=10000;rx_datapath_protocol=pipe;rx_data_rate=2500;rx_data_rate_remainder=0;rx_digitalreset_port_width=1;rx_enable_bit_reversal=false;rx_enable_lock_to_data_sig=false;rx_enable_lock_to_refclk_sig=false;rx_enable_self_test_mode=false;rx_force_signal_detect=false;rx_ppmselect=8;rx_rate_match_fifo_mode=normal;rx_rate_match_pattern1=11010000111010000011;rx_rate_match_pattern2=00101111000101111100;rx_rate_match_pattern_size=20;rx_run_length=40;rx_run_length_enable=true;rx_signal_detect_threshold=4;rx_use_align_state_machine=true;rx_use_clkout=false;rx_use_coreclk=false;
rx_use_deserializer_double_data_mode=false;rx_use_deskew_fifo=false;rx_use_double_data_mode=true;rx_use_pipe8b10binvpolarity=true;rx_use_rate_match_pattern1_only=false;transmitter_termination=oct_100_ohms;tx_8b_10b_mode=normal;tx_allow_polarity_inversion=false;tx_channel_bonding=x2;tx_channel_width=16;tx_clkout_width=2;tx_common_mode=0.65v;tx_data_rate=2500;tx_data_rate_remainder=0;tx_digitalreset_port_width=1;tx_enable_bit_reversal=false;tx_enable_self_test_mode=false;tx_pll_bandwidth_type=Auto;tx_pll_inclk0_period=10000;tx_pll_type=CMU;tx_slew_rate=low;tx_transmit_protocol=pipe;tx_use_coreclk=false;tx_use_double_data_mode=true;tx_use_serializer_double_data_mode=false;use_calibration_block=true;vod_ctrl_setting=5;coreclkout_control_width=1;elec_idle_infer_enable=false;enable_0ppm=false;equalization_setting=1;gxb_powerdown_width=1;iqtxrxclk_allowed=;number_of_quads=1;pll_divide_by=2;pll_multiply_by=25;reconfig_calibration=true;reconfig_fromgxb_port_width=5;reconfig_pll_control_width=1;reconfig_togxb_port_width=4;rx_cdrctrl_enable=true;rx_deskew_pattern=0;rx_dwidth_factor=2;rx_signal_detect_loss_threshold=3;rx_signal_detect_valid_threshold=14;rx_use_external_termination=false;rx_word_aligner_num_byte=1;top_module_name=altpcie_serdes_3cgx_x2d_gen1_08p;tx_bitslip_enable=FALSE;tx_dwidth_factor=2;tx_use_external_termination=false;" */;
defparam
altpcie_serdes_3cgx_x2d_gen1_08p_alt_c3gxb_om78_component.starting_channel_number = starting_channel_number;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
// Retrieval info: PRIVATE: NUM_KEYS NUMERIC "0"
// Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
// Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
// Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE STRING "2500"
// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE_ENABLE STRING "0"
// Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "2500"
// Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2000"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "100"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "100.0"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "PCI Express (PIPE)"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "100.0"
// Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "100.0 125.0"
// Retrieval info: PRIVATE: WIZ_INPUT_A STRING "2500"
// Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
// Retrieval info: PRIVATE: WIZ_INPUT_B STRING "100.0"
// Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
// Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "PCI Express (PIPE)"
// Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "Gen 1-x2"
// Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
// Retrieval info: PARAMETER: STARTING_CHANNEL_NUMBER NUMERIC "0"
// Retrieval info: CONSTANT: EFFECTIVE_DATA_RATE STRING "2500 Mbps"
// Retrieval info: CONSTANT: ENABLE_LC_TX_PLL STRING "false"
// Retrieval info: CONSTANT: ENABLE_PLL_INCLK_ALT_DRIVE_RX_CRU STRING "true"
// Retrieval info: CONSTANT: ENABLE_PLL_INCLK_DRIVE_RX_CRU STRING "true"
// Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "1"
// Retrieval info: CONSTANT: GEN_RECONFIG_PLL STRING "false"
// Retrieval info: CONSTANT: GX_CHANNEL_TYPE STRING ""
// Retrieval info: CONSTANT: INPUT_CLOCK_FREQUENCY STRING "100.0 MHz"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
// Retrieval info: CONSTANT: INTENDED_DEVICE_SPEED_GRADE STRING "6"
// Retrieval info: CONSTANT: INTENDED_DEVICE_VARIANT STRING "ANY"
// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "none"
// Retrieval info: CONSTANT: LPM_TYPE STRING "alt_c3gxb"
// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "2"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
// Retrieval info: CONSTANT: PLL_BANDWIDTH_TYPE STRING "Auto"
// Retrieval info: CONSTANT: PLL_CONTROL_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: PLL_INCLK_PERIOD NUMERIC "10000"
// Retrieval info: CONSTANT: PLL_PFD_FB_MODE STRING "internal"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "18"
// Retrieval info: CONSTANT: PROTOCOL STRING "pcie"
// Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "0"
// Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal"
// Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100"
// Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10"
// Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
// Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "true"
// Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
// Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "NONE"
// Retrieval info: CONSTANT: RX_CHANNEL_BONDING STRING "x2"
// Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.82v"
// Retrieval info: CONSTANT: RX_CRU_INCLOCK0_PERIOD NUMERIC "10000"
// Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "pipe"
// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "2500"
// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
// Retrieval info: CONSTANT: RX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_SELF_TEST_MODE STRING "false"
// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "false"
// Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "8"
// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "11010000111010000011"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "00101111000101111100"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "20"
// Retrieval info: CONSTANT: RX_RUN_LENGTH NUMERIC "40"
// Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "true"
// Retrieval info: CONSTANT: RX_SIGNAL_DETECT_THRESHOLD NUMERIC "4"
// Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true"
// Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "false"
// Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false"
// Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false"
// Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "true"
// Retrieval info: CONSTANT: RX_USE_PIPE8B10BINVPOLARITY STRING "true"
// Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false"
// Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
// Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal"
// Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false"
// Retrieval info: CONSTANT: TX_CHANNEL_BONDING STRING "x2"
// Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: TX_CLKOUT_WIDTH NUMERIC "2"
// Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.65v"
// Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "2500"
// Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
// Retrieval info: CONSTANT: TX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
// Retrieval info: CONSTANT: TX_ENABLE_SELF_TEST_MODE STRING "false"
// Retrieval info: CONSTANT: TX_PLL_BANDWIDTH_TYPE STRING "Auto"
// Retrieval info: CONSTANT: TX_PLL_INCLK0_PERIOD NUMERIC "10000"
// Retrieval info: CONSTANT: TX_PLL_TYPE STRING "CMU"
// Retrieval info: CONSTANT: TX_SLEW_RATE STRING "low"
// Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "pipe"
// Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false"
// Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "true"
// Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "5"
// Retrieval info: CONSTANT: coreclkout_control_width NUMERIC "1"
// Retrieval info: CONSTANT: elec_idle_infer_enable STRING "false"
// Retrieval info: CONSTANT: enable_0ppm STRING "false"
// Retrieval info: CONSTANT: equalization_setting NUMERIC "1"
// Retrieval info: CONSTANT: gxb_powerdown_width NUMERIC "1"
// Retrieval info: CONSTANT: iqtxrxclk_allowed STRING ""
// Retrieval info: CONSTANT: number_of_quads NUMERIC "1"
// Retrieval info: CONSTANT: pll_divide_by STRING "2"
// Retrieval info: CONSTANT: pll_multiply_by STRING "25"
// Retrieval info: CONSTANT: reconfig_calibration STRING "true"
// Retrieval info: CONSTANT: reconfig_fromgxb_port_width NUMERIC "5"
// Retrieval info: CONSTANT: reconfig_pll_control_width NUMERIC "1"
// Retrieval info: CONSTANT: reconfig_togxb_port_width NUMERIC "4"
// Retrieval info: CONSTANT: rx_cdrctrl_enable STRING "true"
// Retrieval info: CONSTANT: rx_deskew_pattern STRING "0"
// Retrieval info: CONSTANT: rx_dwidth_factor NUMERIC "2"
// Retrieval info: CONSTANT: rx_signal_detect_loss_threshold STRING "3"
// Retrieval info: CONSTANT: rx_signal_detect_valid_threshold STRING "14"
// Retrieval info: CONSTANT: rx_use_external_termination STRING "false"
// Retrieval info: CONSTANT: rx_word_aligner_num_byte NUMERIC "1"
// Retrieval info: CONSTANT: top_module_name STRING "altpcie_serdes_3cgx_x2d_gen1_08p"
// Retrieval info: CONSTANT: tx_bitslip_enable STRING "FALSE"
// Retrieval info: CONSTANT: tx_dwidth_factor NUMERIC "2"
// Retrieval info: CONSTANT: tx_use_external_termination STRING "false"
// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
// Retrieval info: USED_PORT: coreclkout 0 0 1 0 OUTPUT NODEFVAL "coreclkout[0..0]"
// Retrieval info: USED_PORT: fixedclk 0 0 0 0 INPUT NODEFVAL "fixedclk"
// Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
// Retrieval info: USED_PORT: pipe8b10binvpolarity 0 0 2 0 INPUT NODEFVAL "pipe8b10binvpolarity[1..0]"
// Retrieval info: USED_PORT: pipedatavalid 0 0 2 0 OUTPUT NODEFVAL "pipedatavalid[1..0]"
// Retrieval info: USED_PORT: pipeelecidle 0 0 2 0 OUTPUT NODEFVAL "pipeelecidle[1..0]"
// Retrieval info: USED_PORT: pipephydonestatus 0 0 2 0 OUTPUT NODEFVAL "pipephydonestatus[1..0]"
// Retrieval info: USED_PORT: pipestatus 0 0 6 0 OUTPUT NODEFVAL "pipestatus[5..0]"
// Retrieval info: USED_PORT: pll_areset 0 0 1 0 INPUT NODEFVAL "pll_areset[0..0]"
// Retrieval info: USED_PORT: pll_inclk 0 0 1 0 INPUT NODEFVAL "pll_inclk[0..0]"
// Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
// Retrieval info: USED_PORT: powerdn 0 0 4 0 INPUT NODEFVAL "powerdn[3..0]"
// Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
// Retrieval info: USED_PORT: reconfig_fromgxb 0 0 5 0 OUTPUT NODEFVAL "reconfig_fromgxb[4..0]"
// Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 INPUT NODEFVAL "reconfig_togxb[3..0]"
// Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
// Retrieval info: USED_PORT: rx_ctrldetect 0 0 4 0 OUTPUT NODEFVAL "rx_ctrldetect[3..0]"
// Retrieval info: USED_PORT: rx_datain 0 0 2 0 INPUT NODEFVAL "rx_datain[1..0]"
// Retrieval info: USED_PORT: rx_dataout 0 0 32 0 OUTPUT NODEFVAL "rx_dataout[31..0]"
// Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
// Retrieval info: USED_PORT: rx_disperr 0 0 4 0 OUTPUT NODEFVAL "rx_disperr[3..0]"
// Retrieval info: USED_PORT: rx_errdetect 0 0 4 0 OUTPUT NODEFVAL "rx_errdetect[3..0]"
// Retrieval info: USED_PORT: rx_freqlocked 0 0 2 0 OUTPUT NODEFVAL "rx_freqlocked[1..0]"
// Retrieval info: USED_PORT: rx_patterndetect 0 0 4 0 OUTPUT NODEFVAL "rx_patterndetect[3..0]"
// Retrieval info: USED_PORT: rx_syncstatus 0 0 4 0 OUTPUT NODEFVAL "rx_syncstatus[3..0]"
// Retrieval info: USED_PORT: tx_ctrlenable 0 0 4 0 INPUT NODEFVAL "tx_ctrlenable[3..0]"
// Retrieval info: USED_PORT: tx_datain 0 0 32 0 INPUT NODEFVAL "tx_datain[31..0]"
// Retrieval info: USED_PORT: tx_dataout 0 0 2 0 OUTPUT NODEFVAL "tx_dataout[1..0]"
// Retrieval info: USED_PORT: tx_detectrxloop 0 0 2 0 INPUT NODEFVAL "tx_detectrxloop[1..0]"
// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
// Retrieval info: USED_PORT: tx_forcedispcompliance 0 0 2 0 INPUT NODEFVAL "tx_forcedispcompliance[1..0]"
// Retrieval info: USED_PORT: tx_forceelecidle 0 0 2 0 INPUT NODEFVAL "tx_forceelecidle[1..0]"
// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
// Retrieval info: CONNECT: @fixedclk 0 0 0 0 fixedclk 0 0 0 0
// Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
// Retrieval info: CONNECT: @pipe8b10binvpolarity 0 0 2 0 pipe8b10binvpolarity 0 0 2 0
// Retrieval info: CONNECT: @pll_areset 0 0 1 0 pll_areset 0 0 1 0
// Retrieval info: CONNECT: @pll_inclk 0 0 1 0 pll_inclk 0 0 1 0
// Retrieval info: CONNECT: @powerdn 0 0 4 0 powerdn 0 0 4 0
// Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
// Retrieval info: CONNECT: @reconfig_togxb 0 0 4 0 reconfig_togxb 0 0 4 0
// Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
// Retrieval info: CONNECT: @rx_datain 0 0 2 0 rx_datain 0 0 2 0
// Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
// Retrieval info: CONNECT: @tx_ctrlenable 0 0 4 0 tx_ctrlenable 0 0 4 0
// Retrieval info: CONNECT: @tx_datain 0 0 32 0 tx_datain 0 0 32 0
// Retrieval info: CONNECT: @tx_detectrxloop 0 0 2 0 tx_detectrxloop 0 0 2 0
// Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
// Retrieval info: CONNECT: @tx_forcedispcompliance 0 0 2 0 tx_forcedispcompliance 0 0 2 0
// Retrieval info: CONNECT: @tx_forceelecidle 0 0 2 0 tx_forceelecidle 0 0 2 0
// Retrieval info: CONNECT: coreclkout 0 0 1 0 @coreclkout 0 0 1 0
// Retrieval info: CONNECT: pipedatavalid 0 0 2 0 @pipedatavalid 0 0 2 0
// Retrieval info: CONNECT: pipeelecidle 0 0 2 0 @pipeelecidle 0 0 2 0
// Retrieval info: CONNECT: pipephydonestatus 0 0 2 0 @pipephydonestatus 0 0 2 0
// Retrieval info: CONNECT: pipestatus 0 0 6 0 @pipestatus 0 0 6 0
// Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
// Retrieval info: CONNECT: reconfig_fromgxb 0 0 5 0 @reconfig_fromgxb 0 0 5 0
// Retrieval info: CONNECT: rx_ctrldetect 0 0 4 0 @rx_ctrldetect 0 0 4 0
// Retrieval info: CONNECT: rx_dataout 0 0 32 0 @rx_dataout 0 0 32 0
// Retrieval info: CONNECT: rx_disperr 0 0 4 0 @rx_disperr 0 0 4 0
// Retrieval info: CONNECT: rx_errdetect 0 0 4 0 @rx_errdetect 0 0 4 0
// Retrieval info: CONNECT: rx_freqlocked 0 0 2 0 @rx_freqlocked 0 0 2 0
// Retrieval info: CONNECT: rx_patterndetect 0 0 4 0 @rx_patterndetect 0 0 4 0
// Retrieval info: CONNECT: rx_syncstatus 0 0 4 0 @rx_syncstatus 0 0 4 0
// Retrieval info: CONNECT: tx_dataout 0 0 2 0 @tx_dataout 0 0 2 0
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_3cgx_x2d_gen1_08p.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_3cgx_x2d_gen1_08p.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_3cgx_x2d_gen1_08p.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_3cgx_x2d_gen1_08p.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_3cgx_x2d_gen1_08p.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_3cgx_x2d_gen1_08p_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_3cgx_x2d_gen1_08p_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: LIB_FILE: cycloneiv_hssi
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// DDC block
module ddc(input clock,
input reset,
input enable,
input [3:0] rate1,
input [3:0] rate2,
output strobe,
input [31:0] freq,
input [15:0] i_in,
input [15:0] q_in,
output [15:0] i_out,
output [15:0] q_out
);
parameter bw = 16;
parameter zw = 16;
wire [15:0] i_cordic_out, q_cordic_out;
wire [31:0] phase;
wire strobe1, strobe2;
reg [3:0] strobe_ctr1,strobe_ctr2;
always @(posedge clock)
if(reset | ~enable)
strobe_ctr2 <= #1 4'd0;
else if(strobe2)
strobe_ctr2 <= #1 4'd0;
else
strobe_ctr2 <= #1 strobe_ctr2 + 4'd1;
always @(posedge clock)
if(reset | ~enable)
strobe_ctr1 <= #1 4'd0;
else if(strobe1)
strobe_ctr1 <= #1 4'd0;
else if(strobe2)
strobe_ctr1 <= #1 strobe_ctr1 + 4'd1;
assign strobe2 = enable & ( strobe_ctr2 == rate2 );
assign strobe1 = strobe2 & ( strobe_ctr1 == rate1 );
assign strobe = strobe1;
function [2:0] log_ceil;
input [3:0] val;
log_ceil = val[3] ? 3'd4 : val[2] ? 3'd3 : val[1] ? 3'd2 : 3'd1;
endfunction
wire [2:0] shift1 = log_ceil(rate1);
wire [2:0] shift2 = log_ceil(rate2);
cordic #(.bitwidth(bw),.zwidth(zw),.stages(16))
cordic(.clock(clock), .reset(reset), .enable(enable),
.xi(i_in), .yi(q_in), .zi(phase[31:32-zw]),
.xo(i_cordic_out), .yo(q_cordic_out), .zo() );
cic_decim_2stage #(.bw(bw),.N(4))
decim_i(.clock(clock),.reset(reset),.enable(enable),
.strobe1(1'b1),.strobe2(strobe2),.strobe3(strobe1),.shift1(shift2),.shift2(shift1),
.signal_in(i_cordic_out),.signal_out(i_out));
cic_decim_2stage #(.bw(bw),.N(4))
decim_q(.clock(clock),.reset(reset),.enable(enable),
.strobe1(1'b1),.strobe2(strobe2),.strobe3(strobe1),.shift1(shift2),.shift2(shift1),
.signal_in(q_cordic_out),.signal_out(q_out));
phase_acc #(.resolution(32))
nco (.clk(clock),.reset(reset),.enable(enable),
.freq(freq),.phase(phase));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND4B_BLACKBOX_V
`define SKY130_FD_SC_HD__NAND4B_BLACKBOX_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nand4b (
Y ,
A_N,
B ,
C ,
D
);
output Y ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND4B_BLACKBOX_V
|
/*
Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 77].
*/
module top(clk,a,b,c,set);
parameter A_WIDTH = 6 /*4*/;
parameter B_WIDTH = 6 /*3*/;
input set;
input clk;
input signed [(A_WIDTH - 1):0] a;
input signed [(B_WIDTH - 1):0] b;
output signed [(A_WIDTH + B_WIDTH - 1):0] c;
reg [(A_WIDTH + B_WIDTH - 1):0] reg_tmp_c;
assign c = reg_tmp_c;
always @(posedge clk)
begin
if(set)
begin
reg_tmp_c <= 0;
end
else
begin
reg_tmp_c <= a * b + c;
end
end
endmodule
module top2(clk,a,b,c,hold);
parameter A_WIDTH = 6 /*4*/;
parameter B_WIDTH = 6 /*3*/;
input hold;
input clk;
input signed [(A_WIDTH - 1):0] a;
input signed [(B_WIDTH - 1):0] b;
output signed [(A_WIDTH + B_WIDTH - 1):0] c;
reg signed [A_WIDTH-1:0] reg_a;
reg signed [B_WIDTH-1:0] reg_b;
reg [(A_WIDTH + B_WIDTH - 1):0] reg_tmp_c;
assign c = reg_tmp_c;
always @(posedge clk)
begin
if (!hold) begin
reg_a <= a;
reg_b <= b;
reg_tmp_c <= reg_a * reg_b + c;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__UDP_DFF_PR_PP_PG_N_BLACKBOX_V
`define SKY130_FD_SC_HVL__UDP_DFF_PR_PP_PG_N_BLACKBOX_V
/**
* udp_dff$PR_pp$PG$N: Positive edge triggered D flip-flop with active
* high
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N (
Q ,
D ,
CLK ,
RESET ,
NOTIFIER,
VPWR ,
VGND
);
output Q ;
input D ;
input CLK ;
input RESET ;
input NOTIFIER;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__UDP_DFF_PR_PP_PG_N_BLACKBOX_V
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_sin (
enable,
clock,
dataa,
resetn,
result);
input enable;
input clock;
input resetn;
input [31:0] dataa;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
fp_sin fpc_sin(
.sysclk(clock),
.reset(~resetn),
.enable(enable),
.signin(dataa[31]),
.exponentin(dataa[30:23]),
.mantissain(dataa[22:0]),
.signout(sub_wire0[31]),
.exponentout(sub_wire0[30:23]),
.mantissaout(sub_wire0[22:0])
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:20:57 09/06/2015
// Design Name:
// Module Name: FSM_Mult_Function
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FSM_Mult_Function(
//INPUTS
input wire clk,
input wire rst,
input wire beg_FSM, //Be gin the multiply operation
input wire ack_FSM, //Is used in the last state, is an aknowledge signal
//ZERO PHASE EVALUATION SIGNALS
input wire zero_flag_i,
//Sgf_Operation *EVALUATION SIGNALS
input wire Mult_shift_i,
//round decoder EVALUATION SIGNALS
input wire round_flag_i,
//Adder round EV LUATION Signals
input wire Add_Overflow_i,
///////////////////////Load Signals/////////////////////////////////////7
//Oper Start_in load signal
output reg load_0_o,
/*Zero flag, Exp operation underflow, Sgf operation first reg, sign result reg*/
output reg load_1_o,
//Exp operation result,
output reg load_2_o,
//Exp operation Overflow, Sgf operation second reg
output reg load_3_o,
//Adder round register
output reg load_4_o,
//Final result registers
output reg load_5_o,
//Barrel shifter registers
output reg load_6_o,
/////////////////////Multiplexers selector control signals////////////
//Sixth Phase control signals
output reg ctrl_select_a_o,
output reg ctrl_select_b_o,
output reg [1:0] selector_b_o,
output reg ctrl_select_c_o,
//////////////////////Module's control signals/////////////////////////
//Exp operation control signals
output reg exp_op_o,
//Barrel shifter control signals
output reg shift_value_o,
//Internal reset signal
output reg rst_int,
//Ready Signal
output reg ready
);
////////States///////////
//Zero Phase
parameter [3:0] start = 4'd0,//A
load_operands = 4'd1, //B) loads both operands to registers
extra64_1 = 4'd2,
add_exp = 4'd3, //C) Add both operands, evaluate underflow
subt_bias = 4'd4, //D) Subtract bias to the result, evaluate overflow, evaluate zero
mult_overf= 4'd5, //E) Evaluate overflow in Sgf multiplication for normalization case
mult_norn = 4'd6, //F) Overflow normalization, right shift significant and increment exponent
mult_no_norn = 4'd7, //G)No_normalization sgf
round_case = 4'd8, //H) Rounding evaluation. Positive= adder rounding, Negative,=Final load
adder_round = 4'd9, //I) add a 1 to the significand in case of rounding
round_norm = 4'd10, //J) Evaluate overflow in adder for normalization, Positive = normalization, same that F
final_load = 4'd11, //K) Load output registers
ready_flag = 4'd12; //L) Ready flag, wait for ack signal
//State registers
reg [3:0] state_reg, state_next;
//State registers reset and standby logic
always @(posedge clk, posedge rst)
if(rst)
state_reg <= start;
else
state_reg <= state_next;
//Transition and Output Logic
always @*
begin
//STATE DEFAULT BEHAVIOR
state_next = state_reg; //If no changes, keep the value of the register unaltered
load_0_o=0;
/*Zero flag, Exp operation underflow, Sgf operation first reg, sign result reg*/
load_1_o=0;
//Exp operation result,
load_2_o=0;
//Exp operation Overflow, Sgf operation second reg
load_3_o=0;
//Adder round register
load_4_o=0;
//Final result registers
load_5_o=0;
load_6_o=0;
//////////////////////Multiplexers selector control signals////////////
//Sixth Phase control signals
ctrl_select_a_o=0;
ctrl_select_b_o=0;
selector_b_o=2'b0;
ctrl_select_c_o=0;
//////////////////////Module's control signals/////////////////////////
//Exp operation control signals
exp_op_o=0;
//Barrel shifter control signals
shift_value_o=0;
//Internal reset signal
rst_int=0;
//Ready Signal
ready=0;
case(state_reg)
start:
begin
rst_int = 1;
if(beg_FSM)
state_next = load_operands; //Jump to the first state of the machine
end
//First Phase
load_operands:
begin
load_0_o = 1;
state_next = extra64_1;
end
extra64_1:
begin
state_next = add_exp;
end
//Zero Check
add_exp:
begin
load_1_o = 1;
load_2_o = 1;
ctrl_select_a_o = 1;
ctrl_select_b_o = 1;
selector_b_o = 2'b01;
state_next = subt_bias;
end
subt_bias:
begin
load_2_o = 1;
load_3_o = 1;
exp_op_o = 1;
if(zero_flag_i)
state_next = ready_flag;
else
state_next = mult_overf;
end
mult_overf:
begin
if(Mult_shift_i) begin
ctrl_select_b_o =1;
selector_b_o =2'b10;
state_next = mult_norn;
end
else
state_next = mult_no_norn;
end
//Ninth Phase
mult_norn:
begin
shift_value_o =1;
load_6_o = 1;
load_2_o = 1;
load_3_o = 1;
//exp_op_o = 1;
state_next = round_case;
end
mult_no_norn:
begin
shift_value_o =0;
load_6_o = 1;
state_next = round_case;
end
round_case:
begin
if(round_flag_i) begin
ctrl_select_c_o =1;
state_next = adder_round;
end
else
state_next = final_load;
end
adder_round:
begin
load_4_o = 1;
ctrl_select_b_o = 1;
selector_b_o = 2'b01;
state_next = round_norm;
end
round_norm:
begin
load_6_o = 1;
if(Add_Overflow_i)begin
shift_value_o =1;
load_2_o = 1;
load_3_o = 1;
state_next = final_load;
end
else begin
shift_value_o =0;
state_next = final_load;
end
end
final_load:
begin
load_5_o =1;
state_next = ready_flag;
end
ready_flag:
begin
ready = 1;
if(ack_FSM) begin
state_next = start;end
end
default:
begin
state_next =start;end
endcase
end
endmodule
|
`timescale 1 ns / 1 ps
module testbench;
reg rd_clk;
reg [ 7:0] rd_addr;
wire [17:0] rd_data;
wire wr_clk = 0;
wire wr_enable = 0;
wire [ 7:0] wr_addr = 0;
wire [17:0] wr_data = 0;
function [17:0] hash(input [7:0] k);
reg [31:0] x;
begin
x = {k, ~k, k, ~k};
x = x ^ (x << 13);
x = x ^ (x >> 17);
x = x ^ (x << 5);
hash = x;
end
endfunction
myram uut (
.rd_clk (rd_clk ),
.rd_addr (rd_addr ),
.rd_data (rd_data ),
.wr_clk (wr_clk ),
.wr_enable(wr_enable),
.wr_addr (wr_addr ),
.wr_data (wr_data )
);
initial begin
rd_clk = 0;
#1000;
forever #10 rd_clk <= ~rd_clk;
end
integer i;
initial begin
rd_addr <= 0;
@(posedge rd_clk);
for (i = 0; i < 256; i=i+1) begin
rd_addr <= rd_addr + 1;
@(posedge rd_clk);
// $display("%3d %3d", i, rd_data);
if (hash(i) !== rd_data) begin
$display("[%1t] ERROR: addr=%3d, data_mem=%18b, data_ref=%18b", $time, i, rd_data, hash(i));
$stop;
end
end
$display("[%1t] Passed bram2 test.", $time);
$finish;
end
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.2
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module sp_co_ord_delay_actual (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
ap_ready,
phi_0_0_0_V_read,
phi_0_0_1_V_read,
phi_0_1_0_V_read,
phi_0_1_1_V_read,
phi_0_2_0_V_read,
phi_0_2_1_V_read,
phi_0_3_0_V_read,
phi_0_3_1_V_read,
phi_0_4_0_V_read,
phi_0_4_1_V_read,
phi_0_5_0_V_read,
phi_0_5_1_V_read,
phi_0_6_0_V_read,
phi_0_6_1_V_read,
phi_0_7_0_V_read,
phi_0_7_1_V_read,
phi_0_8_0_V_read,
phi_0_8_1_V_read,
phi_1_0_0_V_read,
phi_1_0_1_V_read,
phi_1_1_0_V_read,
phi_1_1_1_V_read,
phi_1_2_0_V_read,
phi_1_2_1_V_read,
phi_1_3_0_V_read,
phi_1_3_1_V_read,
phi_1_4_0_V_read,
phi_1_4_1_V_read,
phi_1_5_0_V_read,
phi_1_5_1_V_read,
phi_1_6_0_V_read,
phi_1_6_1_V_read,
phi_1_7_0_V_read,
phi_1_7_1_V_read,
phi_1_8_0_V_read,
phi_1_8_1_V_read,
phi_2_0_0_V_read,
phi_2_0_1_V_read,
phi_2_1_0_V_read,
phi_2_1_1_V_read,
phi_2_2_0_V_read,
phi_2_2_1_V_read,
phi_2_3_0_V_read,
phi_2_3_1_V_read,
phi_2_4_0_V_read,
phi_2_4_1_V_read,
phi_2_5_0_V_read,
phi_2_5_1_V_read,
phi_2_6_0_V_read,
phi_2_6_1_V_read,
phi_2_7_0_V_read,
phi_2_7_1_V_read,
phi_2_8_0_V_read,
phi_2_8_1_V_read,
phi_3_0_0_V_read,
phi_3_0_1_V_read,
phi_3_1_0_V_read,
phi_3_1_1_V_read,
phi_3_2_0_V_read,
phi_3_2_1_V_read,
phi_3_3_0_V_read,
phi_3_3_1_V_read,
phi_3_4_0_V_read,
phi_3_4_1_V_read,
phi_3_5_0_V_read,
phi_3_5_1_V_read,
phi_3_6_0_V_read,
phi_3_6_1_V_read,
phi_3_7_0_V_read,
phi_3_7_1_V_read,
phi_3_8_0_V_read,
phi_3_8_1_V_read,
phi_4_0_0_V_read,
phi_4_0_1_V_read,
phi_4_1_0_V_read,
phi_4_1_1_V_read,
phi_4_2_0_V_read,
phi_4_2_1_V_read,
phi_4_3_0_V_read,
phi_4_3_1_V_read,
phi_4_4_0_V_read,
phi_4_4_1_V_read,
phi_4_5_0_V_read,
phi_4_5_1_V_read,
phi_4_6_0_V_read,
phi_4_6_1_V_read,
phi_4_7_0_V_read,
phi_4_7_1_V_read,
phi_4_8_0_V_read,
phi_4_8_1_V_read,
cpati_0_0_0_V_read,
cpati_0_0_1_V_read,
cpati_0_1_0_V_read,
cpati_0_1_1_V_read,
cpati_0_2_0_V_read,
cpati_0_2_1_V_read,
cpati_0_3_0_V_read,
cpati_0_3_1_V_read,
cpati_0_4_0_V_read,
cpati_0_4_1_V_read,
cpati_0_5_0_V_read,
cpati_0_5_1_V_read,
cpati_0_6_0_V_read,
cpati_0_6_1_V_read,
cpati_0_7_0_V_read,
cpati_0_7_1_V_read,
cpati_0_8_0_V_read,
cpati_0_8_1_V_read,
cpati_1_0_0_V_read,
cpati_1_0_1_V_read,
cpati_1_1_0_V_read,
cpati_1_1_1_V_read,
cpati_1_2_0_V_read,
cpati_1_2_1_V_read,
cpati_1_3_0_V_read,
cpati_1_3_1_V_read,
cpati_1_4_0_V_read,
cpati_1_4_1_V_read,
cpati_1_5_0_V_read,
cpati_1_5_1_V_read,
cpati_1_6_0_V_read,
cpati_1_6_1_V_read,
cpati_1_7_0_V_read,
cpati_1_7_1_V_read,
cpati_1_8_0_V_read,
cpati_1_8_1_V_read,
cpati_2_0_0_V_read,
cpati_2_0_1_V_read,
cpati_2_1_0_V_read,
cpati_2_1_1_V_read,
cpati_2_2_0_V_read,
cpati_2_2_1_V_read,
cpati_2_3_0_V_read,
cpati_2_3_1_V_read,
cpati_2_4_0_V_read,
cpati_2_4_1_V_read,
cpati_2_5_0_V_read,
cpati_2_5_1_V_read,
cpati_2_6_0_V_read,
cpati_2_6_1_V_read,
cpati_2_7_0_V_read,
cpati_2_7_1_V_read,
cpati_2_8_0_V_read,
cpati_2_8_1_V_read,
cpati_3_0_0_V_read,
cpati_3_0_1_V_read,
cpati_3_1_0_V_read,
cpati_3_1_1_V_read,
cpati_3_2_0_V_read,
cpati_3_2_1_V_read,
cpati_3_3_0_V_read,
cpati_3_3_1_V_read,
cpati_3_4_0_V_read,
cpati_3_4_1_V_read,
cpati_3_5_0_V_read,
cpati_3_5_1_V_read,
cpati_3_6_0_V_read,
cpati_3_6_1_V_read,
cpati_3_7_0_V_read,
cpati_3_7_1_V_read,
cpati_3_8_0_V_read,
cpati_3_8_1_V_read,
cpati_4_0_0_V_read,
cpati_4_0_1_V_read,
cpati_4_1_0_V_read,
cpati_4_1_1_V_read,
cpati_4_2_0_V_read,
cpati_4_2_1_V_read,
cpati_4_3_0_V_read,
cpati_4_3_1_V_read,
cpati_4_4_0_V_read,
cpati_4_4_1_V_read,
cpati_4_5_0_V_read,
cpati_4_5_1_V_read,
cpati_4_6_0_V_read,
cpati_4_6_1_V_read,
cpati_4_7_0_V_read,
cpati_4_7_1_V_read,
cpati_4_8_0_V_read,
cpati_4_8_1_V_read,
ap_return_0,
ap_return_1,
ap_return_2,
ap_return_3,
ap_return_4,
ap_return_5,
ap_return_6,
ap_return_7,
ap_return_8,
ap_return_9,
ap_return_10,
ap_return_11,
ap_return_12,
ap_return_13,
ap_return_14,
ap_return_15,
ap_return_16,
ap_return_17,
ap_return_18,
ap_return_19,
ap_return_20,
ap_return_21,
ap_return_22,
ap_return_23,
ap_return_24,
ap_return_25,
ap_return_26,
ap_return_27,
ap_return_28,
ap_return_29,
ap_return_30,
ap_return_31,
ap_return_32,
ap_return_33,
ap_return_34,
ap_return_35,
ap_return_36,
ap_return_37
);
parameter ap_ST_pp0_stg0_fsm_0 = 1'b1;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output ap_ready;
input [11:0] phi_0_0_0_V_read;
input [11:0] phi_0_0_1_V_read;
input [11:0] phi_0_1_0_V_read;
input [11:0] phi_0_1_1_V_read;
input [11:0] phi_0_2_0_V_read;
input [11:0] phi_0_2_1_V_read;
input [11:0] phi_0_3_0_V_read;
input [11:0] phi_0_3_1_V_read;
input [11:0] phi_0_4_0_V_read;
input [11:0] phi_0_4_1_V_read;
input [11:0] phi_0_5_0_V_read;
input [11:0] phi_0_5_1_V_read;
input [11:0] phi_0_6_0_V_read;
input [11:0] phi_0_6_1_V_read;
input [11:0] phi_0_7_0_V_read;
input [11:0] phi_0_7_1_V_read;
input [11:0] phi_0_8_0_V_read;
input [11:0] phi_0_8_1_V_read;
input [11:0] phi_1_0_0_V_read;
input [11:0] phi_1_0_1_V_read;
input [11:0] phi_1_1_0_V_read;
input [11:0] phi_1_1_1_V_read;
input [11:0] phi_1_2_0_V_read;
input [11:0] phi_1_2_1_V_read;
input [11:0] phi_1_3_0_V_read;
input [11:0] phi_1_3_1_V_read;
input [11:0] phi_1_4_0_V_read;
input [11:0] phi_1_4_1_V_read;
input [11:0] phi_1_5_0_V_read;
input [11:0] phi_1_5_1_V_read;
input [11:0] phi_1_6_0_V_read;
input [11:0] phi_1_6_1_V_read;
input [11:0] phi_1_7_0_V_read;
input [11:0] phi_1_7_1_V_read;
input [11:0] phi_1_8_0_V_read;
input [11:0] phi_1_8_1_V_read;
input [11:0] phi_2_0_0_V_read;
input [11:0] phi_2_0_1_V_read;
input [11:0] phi_2_1_0_V_read;
input [11:0] phi_2_1_1_V_read;
input [11:0] phi_2_2_0_V_read;
input [11:0] phi_2_2_1_V_read;
input [11:0] phi_2_3_0_V_read;
input [11:0] phi_2_3_1_V_read;
input [11:0] phi_2_4_0_V_read;
input [11:0] phi_2_4_1_V_read;
input [11:0] phi_2_5_0_V_read;
input [11:0] phi_2_5_1_V_read;
input [11:0] phi_2_6_0_V_read;
input [11:0] phi_2_6_1_V_read;
input [11:0] phi_2_7_0_V_read;
input [11:0] phi_2_7_1_V_read;
input [11:0] phi_2_8_0_V_read;
input [11:0] phi_2_8_1_V_read;
input [11:0] phi_3_0_0_V_read;
input [11:0] phi_3_0_1_V_read;
input [11:0] phi_3_1_0_V_read;
input [11:0] phi_3_1_1_V_read;
input [11:0] phi_3_2_0_V_read;
input [11:0] phi_3_2_1_V_read;
input [11:0] phi_3_3_0_V_read;
input [11:0] phi_3_3_1_V_read;
input [11:0] phi_3_4_0_V_read;
input [11:0] phi_3_4_1_V_read;
input [11:0] phi_3_5_0_V_read;
input [11:0] phi_3_5_1_V_read;
input [11:0] phi_3_6_0_V_read;
input [11:0] phi_3_6_1_V_read;
input [11:0] phi_3_7_0_V_read;
input [11:0] phi_3_7_1_V_read;
input [11:0] phi_3_8_0_V_read;
input [11:0] phi_3_8_1_V_read;
input [11:0] phi_4_0_0_V_read;
input [11:0] phi_4_0_1_V_read;
input [11:0] phi_4_1_0_V_read;
input [11:0] phi_4_1_1_V_read;
input [11:0] phi_4_2_0_V_read;
input [11:0] phi_4_2_1_V_read;
input [11:0] phi_4_3_0_V_read;
input [11:0] phi_4_3_1_V_read;
input [11:0] phi_4_4_0_V_read;
input [11:0] phi_4_4_1_V_read;
input [11:0] phi_4_5_0_V_read;
input [11:0] phi_4_5_1_V_read;
input [11:0] phi_4_6_0_V_read;
input [11:0] phi_4_6_1_V_read;
input [11:0] phi_4_7_0_V_read;
input [11:0] phi_4_7_1_V_read;
input [11:0] phi_4_8_0_V_read;
input [11:0] phi_4_8_1_V_read;
input [3:0] cpati_0_0_0_V_read;
input [3:0] cpati_0_0_1_V_read;
input [3:0] cpati_0_1_0_V_read;
input [3:0] cpati_0_1_1_V_read;
input [3:0] cpati_0_2_0_V_read;
input [3:0] cpati_0_2_1_V_read;
input [3:0] cpati_0_3_0_V_read;
input [3:0] cpati_0_3_1_V_read;
input [3:0] cpati_0_4_0_V_read;
input [3:0] cpati_0_4_1_V_read;
input [3:0] cpati_0_5_0_V_read;
input [3:0] cpati_0_5_1_V_read;
input [3:0] cpati_0_6_0_V_read;
input [3:0] cpati_0_6_1_V_read;
input [3:0] cpati_0_7_0_V_read;
input [3:0] cpati_0_7_1_V_read;
input [3:0] cpati_0_8_0_V_read;
input [3:0] cpati_0_8_1_V_read;
input [3:0] cpati_1_0_0_V_read;
input [3:0] cpati_1_0_1_V_read;
input [3:0] cpati_1_1_0_V_read;
input [3:0] cpati_1_1_1_V_read;
input [3:0] cpati_1_2_0_V_read;
input [3:0] cpati_1_2_1_V_read;
input [3:0] cpati_1_3_0_V_read;
input [3:0] cpati_1_3_1_V_read;
input [3:0] cpati_1_4_0_V_read;
input [3:0] cpati_1_4_1_V_read;
input [3:0] cpati_1_5_0_V_read;
input [3:0] cpati_1_5_1_V_read;
input [3:0] cpati_1_6_0_V_read;
input [3:0] cpati_1_6_1_V_read;
input [3:0] cpati_1_7_0_V_read;
input [3:0] cpati_1_7_1_V_read;
input [3:0] cpati_1_8_0_V_read;
input [3:0] cpati_1_8_1_V_read;
input [3:0] cpati_2_0_0_V_read;
input [3:0] cpati_2_0_1_V_read;
input [3:0] cpati_2_1_0_V_read;
input [3:0] cpati_2_1_1_V_read;
input [3:0] cpati_2_2_0_V_read;
input [3:0] cpati_2_2_1_V_read;
input [3:0] cpati_2_3_0_V_read;
input [3:0] cpati_2_3_1_V_read;
input [3:0] cpati_2_4_0_V_read;
input [3:0] cpati_2_4_1_V_read;
input [3:0] cpati_2_5_0_V_read;
input [3:0] cpati_2_5_1_V_read;
input [3:0] cpati_2_6_0_V_read;
input [3:0] cpati_2_6_1_V_read;
input [3:0] cpati_2_7_0_V_read;
input [3:0] cpati_2_7_1_V_read;
input [3:0] cpati_2_8_0_V_read;
input [3:0] cpati_2_8_1_V_read;
input [3:0] cpati_3_0_0_V_read;
input [3:0] cpati_3_0_1_V_read;
input [3:0] cpati_3_1_0_V_read;
input [3:0] cpati_3_1_1_V_read;
input [3:0] cpati_3_2_0_V_read;
input [3:0] cpati_3_2_1_V_read;
input [3:0] cpati_3_3_0_V_read;
input [3:0] cpati_3_3_1_V_read;
input [3:0] cpati_3_4_0_V_read;
input [3:0] cpati_3_4_1_V_read;
input [3:0] cpati_3_5_0_V_read;
input [3:0] cpati_3_5_1_V_read;
input [3:0] cpati_3_6_0_V_read;
input [3:0] cpati_3_6_1_V_read;
input [3:0] cpati_3_7_0_V_read;
input [3:0] cpati_3_7_1_V_read;
input [3:0] cpati_3_8_0_V_read;
input [3:0] cpati_3_8_1_V_read;
input [3:0] cpati_4_0_0_V_read;
input [3:0] cpati_4_0_1_V_read;
input [3:0] cpati_4_1_0_V_read;
input [3:0] cpati_4_1_1_V_read;
input [3:0] cpati_4_2_0_V_read;
input [3:0] cpati_4_2_1_V_read;
input [3:0] cpati_4_3_0_V_read;
input [3:0] cpati_4_3_1_V_read;
input [3:0] cpati_4_4_0_V_read;
input [3:0] cpati_4_4_1_V_read;
input [3:0] cpati_4_5_0_V_read;
input [3:0] cpati_4_5_1_V_read;
input [3:0] cpati_4_6_0_V_read;
input [3:0] cpati_4_6_1_V_read;
input [3:0] cpati_4_7_0_V_read;
input [3:0] cpati_4_7_1_V_read;
input [3:0] cpati_4_8_0_V_read;
input [3:0] cpati_4_8_1_V_read;
output [11:0] ap_return_0;
output [11:0] ap_return_1;
output [11:0] ap_return_2;
output [11:0] ap_return_3;
output [11:0] ap_return_4;
output [11:0] ap_return_5;
output [11:0] ap_return_6;
output [11:0] ap_return_7;
output [11:0] ap_return_8;
output [6:0] ap_return_9;
output [6:0] ap_return_10;
output [6:0] ap_return_11;
output [6:0] ap_return_12;
output [6:0] ap_return_13;
output [6:0] ap_return_14;
output [6:0] ap_return_15;
output [6:0] ap_return_16;
output [6:0] ap_return_17;
output [6:0] ap_return_18;
output [6:0] ap_return_19;
output [6:0] ap_return_20;
output [6:0] ap_return_21;
output [6:0] ap_return_22;
output [6:0] ap_return_23;
output [6:0] ap_return_24;
output [6:0] ap_return_25;
output [6:0] ap_return_26;
output [6:0] ap_return_27;
output [6:0] ap_return_28;
output [3:0] ap_return_29;
output [3:0] ap_return_30;
output [3:0] ap_return_31;
output [3:0] ap_return_32;
output [3:0] ap_return_33;
output [3:0] ap_return_34;
output [3:0] ap_return_35;
output [3:0] ap_return_36;
output [3:0] ap_return_37;
reg ap_done;
reg ap_idle;
reg ap_ready;
(* fsm_encoding = "none" *) reg [0:0] ap_CS_fsm;
reg ap_sig_cseq_ST_pp0_stg0_fsm_0;
reg ap_sig_18;
wire ap_reg_ppiten_pp0_it0;
reg ap_reg_ppiten_pp0_it1;
reg ap_reg_ppiten_pp0_it2;
reg ap_reg_ppiten_pp0_it3;
reg [11:0] inst_t_phi_1_V_0_0_1_1;
reg [11:0] inst_t_phi_1_V_0_0_4_1;
reg [11:0] inst_t_phi_1_V_0_0_7_1;
reg [11:0] inst_t_phi_1_V_0_2_4_1;
reg [11:0] inst_t_phi_1_V_0_3_4_1;
reg [11:0] inst_t_phi_1_V_0_4_4_1;
reg [11:0] inst_t_phi_1_V_1_0_1_1;
reg [11:0] inst_t_phi_1_V_1_0_4_1;
reg [11:0] inst_t_phi_1_V_1_0_7_1;
reg [11:0] inst_t_phi_1_V_1_2_1_1;
reg [11:0] inst_t_phi_1_V_1_2_4_1;
reg [11:0] inst_t_phi_1_V_1_3_1_1;
reg [11:0] inst_t_phi_1_V_1_3_4_1;
reg [11:0] inst_t_phi_1_V_1_4_1_1;
reg [11:0] inst_t_phi_1_V_1_4_4_1;
reg [11:0] inst_t_phi_1_V_2_0_1_1;
reg [11:0] inst_t_phi_1_V_2_0_4_1;
reg [11:0] inst_t_phi_1_V_2_0_7_1;
reg [11:0] inst_t_phi_1_V_2_2_1_1;
reg [11:0] inst_t_phi_1_V_2_2_4_1;
reg [11:0] inst_t_phi_1_V_2_3_1_1;
reg [11:0] inst_t_phi_1_V_2_3_4_1;
reg [11:0] inst_t_phi_1_V_2_4_1_1;
reg [11:0] inst_t_phi_1_V_2_4_4_1;
reg [11:0] a_phi_1_0_0_1_1_V_1_fu_1482;
reg [11:0] a_phi_1_0_0_4_1_V_1_fu_1506;
reg [11:0] a_phi_1_0_0_7_1_V_1_fu_1530;
reg [11:0] a_phi_1_0_2_4_1_V_1_fu_1650;
reg [11:0] a_phi_1_0_3_4_1_V_1_fu_1722;
reg [11:0] a_phi_1_0_4_4_1_V_1_fu_1794;
reg [11:0] a_phi_1_1_2_1_1_V_1_fu_1986;
reg [11:0] a_phi_1_1_3_1_1_V_1_fu_2058;
reg [11:0] a_phi_1_1_4_1_1_V_1_fu_2130;
wire [0:0] a_th11i_1_0_0_1_0_V_fu_2566;
wire [0:0] a_th11i_1_0_0_1_1_V_fu_2570;
wire [0:0] a_th11i_1_0_0_1_2_V_fu_2574;
wire [0:0] a_th11i_1_0_0_1_3_V_fu_2578;
wire [0:0] a_thi_1_0_0_4_0_V_fu_2870;
wire [0:0] a_thi_1_0_0_4_1_V_fu_2874;
wire [0:0] a_thi_1_0_0_7_0_V_fu_2894;
wire [0:0] a_thi_1_0_0_7_1_V_fu_2898;
wire [0:0] a_thi_1_0_2_4_0_V_fu_3014;
wire [0:0] a_thi_1_0_2_4_1_V_fu_3018;
wire [0:0] a_thi_1_0_3_4_0_V_fu_3086;
wire [0:0] a_thi_1_0_3_4_1_V_fu_3090;
wire [0:0] a_thi_1_0_4_4_0_V_fu_3158;
wire [0:0] a_thi_1_0_4_4_1_V_fu_3162;
wire [0:0] a_thi_1_1_2_1_0_V_fu_3350;
wire [0:0] a_thi_1_1_2_1_1_V_fu_3354;
wire [0:0] a_thi_1_1_3_1_0_V_fu_3422;
wire [0:0] a_thi_1_1_3_1_1_V_fu_3426;
wire [0:0] a_thi_1_1_4_1_0_V_fu_3494;
wire [0:0] a_thi_1_1_4_1_1_V_fu_3498;
wire [0:0] a_cpati_1_0_0_1_1_V_fu_4542;
wire [0:0] a_cpati_1_0_0_4_1_V_fu_4566;
wire [0:0] a_cpati_1_0_0_7_1_V_fu_4590;
wire [0:0] a_cpati_1_0_2_4_1_V_fu_4710;
wire [0:0] a_cpati_1_0_3_4_1_V_fu_4782;
wire [0:0] a_cpati_1_0_4_4_1_V_fu_4854;
wire [0:0] a_cpati_1_1_2_1_1_V_fu_5046;
wire [0:0] a_cpati_1_1_3_1_1_V_fu_5118;
wire [0:0] a_cpati_1_1_4_1_1_V_fu_5190;
wire [6:0] th11o_2_0_1_0_V_write_assi_fu_22500_p1;
wire [6:0] th11o_2_0_1_1_V_write_assi_fu_22507_p1;
wire [6:0] th11o_2_0_1_2_V_write_assi_fu_22514_p1;
wire [6:0] th11o_2_0_1_3_V_write_assi_fu_22521_p1;
wire [6:0] tho_1_2_1_0_V_write_assign_fu_23144_p1;
wire [6:0] tho_1_2_1_1_V_write_assign_fu_23151_p1;
wire [6:0] tho_1_3_1_0_V_write_assign_fu_23206_p1;
wire [6:0] tho_1_3_1_1_V_write_assign_fu_23213_p1;
wire [6:0] tho_1_4_1_0_V_write_assign_fu_23268_p1;
wire [6:0] tho_1_4_1_1_V_write_assign_fu_23275_p1;
wire [6:0] tho_2_0_4_0_V_write_assign_fu_22744_p1;
wire [6:0] tho_2_0_4_1_V_write_assign_fu_22751_p1;
wire [6:0] tho_2_0_7_0_V_write_assign_fu_22770_p1;
wire [6:0] tho_2_0_7_1_V_write_assign_fu_22777_p1;
wire [6:0] tho_2_2_4_0_V_write_assign_fu_22868_p1;
wire [6:0] tho_2_2_4_1_V_write_assign_fu_22875_p1;
wire [6:0] tho_2_3_4_0_V_write_assign_fu_22930_p1;
wire [6:0] tho_2_3_4_1_V_write_assign_fu_22937_p1;
wire [6:0] tho_2_4_4_0_V_write_assign_fu_22992_p1;
wire [6:0] tho_2_4_4_1_V_write_assign_fu_22999_p1;
wire [3:0] cpato_1_2_1_1_V_write_assi_fu_24464_p1;
wire [3:0] cpato_1_3_1_1_V_write_assi_fu_24522_p1;
wire [3:0] cpato_1_4_1_1_V_write_assi_fu_24580_p1;
wire [3:0] cpato_2_0_1_1_V_write_assi_fu_24062_p1;
wire [3:0] cpato_2_0_4_1_V_write_assi_fu_24084_p1;
wire [3:0] cpato_2_0_7_1_V_write_assi_fu_24106_p1;
wire [3:0] cpato_2_2_4_1_V_write_assi_fu_24200_p1;
wire [3:0] cpato_2_3_4_1_V_write_assi_fu_24258_p1;
wire [3:0] cpato_2_4_4_1_V_write_assi_fu_24316_p1;
reg [0:0] ap_NS_fsm;
reg ap_sig_pprstidle_pp0;
// power-on initialization
initial begin
#0 ap_CS_fsm = 1'b1;
#0 ap_reg_ppiten_pp0_it1 = 1'b0;
#0 ap_reg_ppiten_pp0_it2 = 1'b0;
#0 ap_reg_ppiten_pp0_it3 = 1'b0;
#0 inst_t_phi_1_V_0_0_1_1 = 12'b000000000000;
#0 inst_t_phi_1_V_0_0_4_1 = 12'b000000000000;
#0 inst_t_phi_1_V_0_0_7_1 = 12'b000000000000;
#0 inst_t_phi_1_V_0_2_4_1 = 12'b000000000000;
#0 inst_t_phi_1_V_0_3_4_1 = 12'b000000000000;
#0 inst_t_phi_1_V_0_4_4_1 = 12'b000000000000;
#0 inst_t_phi_1_V_1_0_1_1 = 12'b000000000000;
#0 inst_t_phi_1_V_1_0_4_1 = 12'b000000000000;
#0 inst_t_phi_1_V_1_0_7_1 = 12'b000000000000;
#0 inst_t_phi_1_V_1_2_1_1 = 12'b000000000000;
#0 inst_t_phi_1_V_1_2_4_1 = 12'b000000000000;
#0 inst_t_phi_1_V_1_3_1_1 = 12'b000000000000;
#0 inst_t_phi_1_V_1_3_4_1 = 12'b000000000000;
#0 inst_t_phi_1_V_1_4_1_1 = 12'b000000000000;
#0 inst_t_phi_1_V_1_4_4_1 = 12'b000000000000;
#0 inst_t_phi_1_V_2_0_1_1 = 12'b000000000000;
#0 inst_t_phi_1_V_2_0_4_1 = 12'b000000000000;
#0 inst_t_phi_1_V_2_0_7_1 = 12'b000000000000;
#0 inst_t_phi_1_V_2_2_1_1 = 12'b000000000000;
#0 inst_t_phi_1_V_2_2_4_1 = 12'b000000000000;
#0 inst_t_phi_1_V_2_3_1_1 = 12'b000000000000;
#0 inst_t_phi_1_V_2_3_4_1 = 12'b000000000000;
#0 inst_t_phi_1_V_2_4_1_1 = 12'b000000000000;
#0 inst_t_phi_1_V_2_4_4_1 = 12'b000000000000;
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it1 <= 1'b0;
end else begin
if (((1'b1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0)))) begin
ap_reg_ppiten_pp0_it1 <= ap_start;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it2 <= 1'b0;
end else begin
if (~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0))) begin
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it3 <= 1'b0;
end else begin
if (~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0))) begin
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & (1'b1 == ap_reg_ppiten_pp0_it0) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0)))) begin
a_phi_1_0_0_1_1_V_1_fu_1482 <= inst_t_phi_1_V_0_0_1_1;
a_phi_1_0_0_4_1_V_1_fu_1506 <= inst_t_phi_1_V_0_0_4_1;
a_phi_1_0_0_7_1_V_1_fu_1530 <= inst_t_phi_1_V_0_0_7_1;
a_phi_1_0_2_4_1_V_1_fu_1650 <= inst_t_phi_1_V_0_2_4_1;
a_phi_1_0_3_4_1_V_1_fu_1722 <= inst_t_phi_1_V_0_3_4_1;
a_phi_1_0_4_4_1_V_1_fu_1794 <= inst_t_phi_1_V_0_4_4_1;
a_phi_1_1_2_1_1_V_1_fu_1986 <= inst_t_phi_1_V_1_2_1_1;
a_phi_1_1_3_1_1_V_1_fu_2058 <= inst_t_phi_1_V_1_3_1_1;
a_phi_1_1_4_1_1_V_1_fu_2130 <= inst_t_phi_1_V_1_4_1_1;
inst_t_phi_1_V_0_0_1_1 <= inst_t_phi_1_V_1_0_1_1;
inst_t_phi_1_V_0_0_4_1 <= inst_t_phi_1_V_1_0_4_1;
inst_t_phi_1_V_0_0_7_1 <= inst_t_phi_1_V_1_0_7_1;
inst_t_phi_1_V_0_2_4_1 <= inst_t_phi_1_V_1_2_4_1;
inst_t_phi_1_V_0_3_4_1 <= inst_t_phi_1_V_1_3_4_1;
inst_t_phi_1_V_0_4_4_1 <= inst_t_phi_1_V_1_4_4_1;
inst_t_phi_1_V_1_0_1_1 <= inst_t_phi_1_V_2_0_1_1;
inst_t_phi_1_V_1_0_4_1 <= inst_t_phi_1_V_2_0_4_1;
inst_t_phi_1_V_1_0_7_1 <= inst_t_phi_1_V_2_0_7_1;
inst_t_phi_1_V_1_2_1_1 <= inst_t_phi_1_V_2_2_1_1;
inst_t_phi_1_V_1_2_4_1 <= inst_t_phi_1_V_2_2_4_1;
inst_t_phi_1_V_1_3_1_1 <= inst_t_phi_1_V_2_3_1_1;
inst_t_phi_1_V_1_3_4_1 <= inst_t_phi_1_V_2_3_4_1;
inst_t_phi_1_V_1_4_1_1 <= inst_t_phi_1_V_2_4_1_1;
inst_t_phi_1_V_1_4_4_1 <= inst_t_phi_1_V_2_4_4_1;
inst_t_phi_1_V_2_0_1_1 <= phi_0_1_1_V_read;
inst_t_phi_1_V_2_0_4_1 <= phi_0_4_1_V_read;
inst_t_phi_1_V_2_0_7_1 <= phi_0_7_1_V_read;
inst_t_phi_1_V_2_2_1_1 <= phi_2_1_1_V_read;
inst_t_phi_1_V_2_2_4_1 <= phi_2_4_1_V_read;
inst_t_phi_1_V_2_3_1_1 <= phi_3_1_1_V_read;
inst_t_phi_1_V_2_3_4_1 <= phi_3_4_1_V_read;
inst_t_phi_1_V_2_4_1_1 <= phi_4_1_1_V_read;
inst_t_phi_1_V_2_4_4_1 <= phi_4_4_1_V_read;
end
end
always @ (*) begin
if ((((1'b0 == ap_start) & (1'b1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & (1'b1 == ap_reg_ppiten_pp0_it0)) | ((1'b1 == ap_reg_ppiten_pp0_it3) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0))))) begin
ap_done = 1'b1;
end else begin
ap_done = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_start) & (1'b1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & (1'b0 == ap_reg_ppiten_pp0_it0) & (1'b0 == ap_reg_ppiten_pp0_it1) & (1'b0 == ap_reg_ppiten_pp0_it2) & (1'b0 == ap_reg_ppiten_pp0_it3))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_sig_cseq_ST_pp0_stg0_fsm_0) & (1'b1 == ap_reg_ppiten_pp0_it0) & ~((1'b1 == ap_reg_ppiten_pp0_it0) & (ap_start == 1'b0)))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @ (*) begin
if (ap_sig_18) begin
ap_sig_cseq_ST_pp0_stg0_fsm_0 = 1'b1;
end else begin
ap_sig_cseq_ST_pp0_stg0_fsm_0 = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_start) & (1'b0 == ap_reg_ppiten_pp0_it0) & (1'b0 == ap_reg_ppiten_pp0_it1) & (1'b0 == ap_reg_ppiten_pp0_it2))) begin
ap_sig_pprstidle_pp0 = 1'b1;
end else begin
ap_sig_pprstidle_pp0 = 1'b0;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_pp0_stg0_fsm_0 : begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_0;
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign a_cpati_1_0_0_1_1_V_fu_4542 = 1'b0;
assign a_cpati_1_0_0_4_1_V_fu_4566 = 1'b0;
assign a_cpati_1_0_0_7_1_V_fu_4590 = 1'b0;
assign a_cpati_1_0_2_4_1_V_fu_4710 = 1'b0;
assign a_cpati_1_0_3_4_1_V_fu_4782 = 1'b0;
assign a_cpati_1_0_4_4_1_V_fu_4854 = 1'b0;
assign a_cpati_1_1_2_1_1_V_fu_5046 = 1'b0;
assign a_cpati_1_1_3_1_1_V_fu_5118 = 1'b0;
assign a_cpati_1_1_4_1_1_V_fu_5190 = 1'b0;
assign a_th11i_1_0_0_1_0_V_fu_2566 = 1'b0;
assign a_th11i_1_0_0_1_1_V_fu_2570 = 1'b0;
assign a_th11i_1_0_0_1_2_V_fu_2574 = 1'b0;
assign a_th11i_1_0_0_1_3_V_fu_2578 = 1'b0;
assign a_thi_1_0_0_4_0_V_fu_2870 = 1'b0;
assign a_thi_1_0_0_4_1_V_fu_2874 = 1'b0;
assign a_thi_1_0_0_7_0_V_fu_2894 = 1'b0;
assign a_thi_1_0_0_7_1_V_fu_2898 = 1'b0;
assign a_thi_1_0_2_4_0_V_fu_3014 = 1'b0;
assign a_thi_1_0_2_4_1_V_fu_3018 = 1'b0;
assign a_thi_1_0_3_4_0_V_fu_3086 = 1'b0;
assign a_thi_1_0_3_4_1_V_fu_3090 = 1'b0;
assign a_thi_1_0_4_4_0_V_fu_3158 = 1'b0;
assign a_thi_1_0_4_4_1_V_fu_3162 = 1'b0;
assign a_thi_1_1_2_1_0_V_fu_3350 = 1'b0;
assign a_thi_1_1_2_1_1_V_fu_3354 = 1'b0;
assign a_thi_1_1_3_1_0_V_fu_3422 = 1'b0;
assign a_thi_1_1_3_1_1_V_fu_3426 = 1'b0;
assign a_thi_1_1_4_1_0_V_fu_3494 = 1'b0;
assign a_thi_1_1_4_1_1_V_fu_3498 = 1'b0;
assign ap_reg_ppiten_pp0_it0 = ap_start;
assign ap_return_0 = a_phi_1_1_2_1_1_V_1_fu_1986;
assign ap_return_1 = a_phi_1_1_3_1_1_V_1_fu_2058;
assign ap_return_10 = th11o_2_0_1_1_V_write_assi_fu_22507_p1;
assign ap_return_11 = th11o_2_0_1_2_V_write_assi_fu_22514_p1;
assign ap_return_12 = th11o_2_0_1_3_V_write_assi_fu_22521_p1;
assign ap_return_13 = tho_1_2_1_0_V_write_assign_fu_23144_p1;
assign ap_return_14 = tho_1_2_1_1_V_write_assign_fu_23151_p1;
assign ap_return_15 = tho_1_3_1_0_V_write_assign_fu_23206_p1;
assign ap_return_16 = tho_1_3_1_1_V_write_assign_fu_23213_p1;
assign ap_return_17 = tho_1_4_1_0_V_write_assign_fu_23268_p1;
assign ap_return_18 = tho_1_4_1_1_V_write_assign_fu_23275_p1;
assign ap_return_19 = tho_2_0_4_0_V_write_assign_fu_22744_p1;
assign ap_return_2 = a_phi_1_1_4_1_1_V_1_fu_2130;
assign ap_return_20 = tho_2_0_4_1_V_write_assign_fu_22751_p1;
assign ap_return_21 = tho_2_0_7_0_V_write_assign_fu_22770_p1;
assign ap_return_22 = tho_2_0_7_1_V_write_assign_fu_22777_p1;
assign ap_return_23 = tho_2_2_4_0_V_write_assign_fu_22868_p1;
assign ap_return_24 = tho_2_2_4_1_V_write_assign_fu_22875_p1;
assign ap_return_25 = tho_2_3_4_0_V_write_assign_fu_22930_p1;
assign ap_return_26 = tho_2_3_4_1_V_write_assign_fu_22937_p1;
assign ap_return_27 = tho_2_4_4_0_V_write_assign_fu_22992_p1;
assign ap_return_28 = tho_2_4_4_1_V_write_assign_fu_22999_p1;
assign ap_return_29 = cpato_1_2_1_1_V_write_assi_fu_24464_p1;
assign ap_return_3 = a_phi_1_0_0_1_1_V_1_fu_1482;
assign ap_return_30 = cpato_1_3_1_1_V_write_assi_fu_24522_p1;
assign ap_return_31 = cpato_1_4_1_1_V_write_assi_fu_24580_p1;
assign ap_return_32 = cpato_2_0_1_1_V_write_assi_fu_24062_p1;
assign ap_return_33 = cpato_2_0_4_1_V_write_assi_fu_24084_p1;
assign ap_return_34 = cpato_2_0_7_1_V_write_assi_fu_24106_p1;
assign ap_return_35 = cpato_2_2_4_1_V_write_assi_fu_24200_p1;
assign ap_return_36 = cpato_2_3_4_1_V_write_assi_fu_24258_p1;
assign ap_return_37 = cpato_2_4_4_1_V_write_assi_fu_24316_p1;
assign ap_return_4 = a_phi_1_0_0_4_1_V_1_fu_1506;
assign ap_return_5 = a_phi_1_0_0_7_1_V_1_fu_1530;
assign ap_return_6 = a_phi_1_0_2_4_1_V_1_fu_1650;
assign ap_return_7 = a_phi_1_0_3_4_1_V_1_fu_1722;
assign ap_return_8 = a_phi_1_0_4_4_1_V_1_fu_1794;
assign ap_return_9 = th11o_2_0_1_0_V_write_assi_fu_22500_p1;
always @ (*) begin
ap_sig_18 = (ap_CS_fsm[ap_const_lv32_0] == 1'b1);
end
assign cpato_1_2_1_1_V_write_assi_fu_24464_p1 = a_cpati_1_1_2_1_1_V_fu_5046;
assign cpato_1_3_1_1_V_write_assi_fu_24522_p1 = a_cpati_1_1_3_1_1_V_fu_5118;
assign cpato_1_4_1_1_V_write_assi_fu_24580_p1 = a_cpati_1_1_4_1_1_V_fu_5190;
assign cpato_2_0_1_1_V_write_assi_fu_24062_p1 = a_cpati_1_0_0_1_1_V_fu_4542;
assign cpato_2_0_4_1_V_write_assi_fu_24084_p1 = a_cpati_1_0_0_4_1_V_fu_4566;
assign cpato_2_0_7_1_V_write_assi_fu_24106_p1 = a_cpati_1_0_0_7_1_V_fu_4590;
assign cpato_2_2_4_1_V_write_assi_fu_24200_p1 = a_cpati_1_0_2_4_1_V_fu_4710;
assign cpato_2_3_4_1_V_write_assi_fu_24258_p1 = a_cpati_1_0_3_4_1_V_fu_4782;
assign cpato_2_4_4_1_V_write_assi_fu_24316_p1 = a_cpati_1_0_4_4_1_V_fu_4854;
assign th11o_2_0_1_0_V_write_assi_fu_22500_p1 = a_th11i_1_0_0_1_0_V_fu_2566;
assign th11o_2_0_1_1_V_write_assi_fu_22507_p1 = a_th11i_1_0_0_1_1_V_fu_2570;
assign th11o_2_0_1_2_V_write_assi_fu_22514_p1 = a_th11i_1_0_0_1_2_V_fu_2574;
assign th11o_2_0_1_3_V_write_assi_fu_22521_p1 = a_th11i_1_0_0_1_3_V_fu_2578;
assign tho_1_2_1_0_V_write_assign_fu_23144_p1 = a_thi_1_1_2_1_0_V_fu_3350;
assign tho_1_2_1_1_V_write_assign_fu_23151_p1 = a_thi_1_1_2_1_1_V_fu_3354;
assign tho_1_3_1_0_V_write_assign_fu_23206_p1 = a_thi_1_1_3_1_0_V_fu_3422;
assign tho_1_3_1_1_V_write_assign_fu_23213_p1 = a_thi_1_1_3_1_1_V_fu_3426;
assign tho_1_4_1_0_V_write_assign_fu_23268_p1 = a_thi_1_1_4_1_0_V_fu_3494;
assign tho_1_4_1_1_V_write_assign_fu_23275_p1 = a_thi_1_1_4_1_1_V_fu_3498;
assign tho_2_0_4_0_V_write_assign_fu_22744_p1 = a_thi_1_0_0_4_0_V_fu_2870;
assign tho_2_0_4_1_V_write_assign_fu_22751_p1 = a_thi_1_0_0_4_1_V_fu_2874;
assign tho_2_0_7_0_V_write_assign_fu_22770_p1 = a_thi_1_0_0_7_0_V_fu_2894;
assign tho_2_0_7_1_V_write_assign_fu_22777_p1 = a_thi_1_0_0_7_1_V_fu_2898;
assign tho_2_2_4_0_V_write_assign_fu_22868_p1 = a_thi_1_0_2_4_0_V_fu_3014;
assign tho_2_2_4_1_V_write_assign_fu_22875_p1 = a_thi_1_0_2_4_1_V_fu_3018;
assign tho_2_3_4_0_V_write_assign_fu_22930_p1 = a_thi_1_0_3_4_0_V_fu_3086;
assign tho_2_3_4_1_V_write_assign_fu_22937_p1 = a_thi_1_0_3_4_1_V_fu_3090;
assign tho_2_4_4_0_V_write_assign_fu_22992_p1 = a_thi_1_0_4_4_0_V_fu_3158;
assign tho_2_4_4_1_V_write_assign_fu_22999_p1 = a_thi_1_0_4_4_1_V_fu_3162;
endmodule //sp_co_ord_delay_actual
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:58:10 03/31/2015
// Design Name:
// Module Name: pg_to_bpbg
// bproject Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module pg_to_PG(
input [15:0] p,
input [15:0] g,
output [3:0] bp,
output [3:0] bg
);
assign bg[0]=g[3 ]|p[3 ]&g[2 ]|p[3 ]&p[2 ]&g[1 ]|p[3 ]&p[2 ]&p[1 ]&g[0 ],
bg[1]=g[7 ]|p[7 ]&g[6 ]|p[7 ]&p[6 ]&g[5 ]|p[7 ]&p[6 ]&p[5 ]&g[4 ],
bg[2]=g[11]|p[11]&g[10]|p[11]&p[10]&g[9 ]|p[11]&p[10]&p[9 ]&g[8 ],
bg[3]=g[15]|p[15]&g[14]|p[15]&p[14]&g[13]|p[15]&p[14]&p[13]&g[12];
assign bp[0]=p[3]&p[2]&p[1]&p[0],
bp[1]=p[7]&p[6]&p[5]&p[4],
bp[2]=p[11]&p[10]&p[9]&p[8],
bp[3]=p[15]&p[14]&p[13]&p[12];
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_BEHAVIORAL_PP_V
/**
* lpflow_decapkapwr: Decoupling capacitance filler on keep-alive
* rail.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__lpflow_decapkapwr (
VPWR ,
KAPWR,
VGND ,
VPB ,
VNB
);
// Module ports
input VPWR ;
input KAPWR;
input VGND ;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_BEHAVIORAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__XNOR2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__XNOR2_BEHAVIORAL_PP_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__xnor2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xnor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y , A, B );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, xnor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__XNOR2_BEHAVIORAL_PP_V |