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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND4BB_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__NAND4BB_BEHAVIORAL_PP_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__nand4bb (
Y ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , D, C );
or or0 (or0_out_Y , B_N, A_N, nand0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND4BB_BEHAVIORAL_PP_V |
// DESCRIPTION: Verilator: SystemVerilog interface test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Iztok Jeras.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
logic rst = 1'b1; // reset
integer rst_cnt = 0;
// reset is removed after a delay
always @ (posedge clk)
begin
rst_cnt <= rst_cnt + 1;
rst <= rst_cnt <= 3;
end
// counters
int cnt;
int cnt_src;
int cnt_drn;
// add all counters
assign cnt = cnt_src + cnt_drn + inf.cnt;
// finish report
always @ (posedge clk)
if (cnt == 3*16) begin
$write("*-* All Finished *-*\n");
$finish;
end
// interface instance
handshake inf (
.clk (clk),
.rst (rst)
);
// source instance
source #(
.RW (8),
.RP (8'b11100001)
) source (
.clk (clk),
.rst (rst),
.inf (inf),
.cnt (cnt_src)
);
// drain instance
drain #(
.RW (8),
.RP (8'b11010100)
) drain (
.clk (clk),
.rst (rst),
.inf (inf),
.cnt (cnt_drn)
);
endmodule : t
// interface definition
interface handshake #(
parameter int unsigned WC = 32
)(
input logic clk,
input logic rst
);
// modport signals
logic req; // request
logic grt; // grant
logic inc; // increment
// local signals
integer cnt; // counter
// source
modport src (
output req,
input grt
);
// drain
modport drn (
input req,
output grt
);
// incremet condition
assign inc = req & grt;
// local logic (counter)
always @ (posedge clk, posedge rst)
if (rst) cnt <= '0;
else cnt <= cnt + {31'h0, inc};
endinterface : handshake
// source module
module source #(
// random generator parameters
parameter int unsigned RW=1, // LFSR width
parameter bit [RW-1:0] RP='0, // LFSR polinom
parameter bit [RW-1:0] RR='1 // LFSR reset state
)(
input logic clk,
input logic rst,
handshake.src inf,
output integer cnt
);
// LFSR
logic [RW-1:0] rnd;
// LFSR in Galois form
always @ (posedge clk, posedge rst)
if (rst) rnd <= RR;
else rnd <= {rnd[0], rnd[RW-1:1]} ^ ({RW{rnd[0]}} & RP);
// counter
always @ (posedge clk, posedge rst)
if (rst) cnt <= 32'd0;
else cnt <= cnt + {31'd0, (inf.req & inf.grt)};
// request signal
assign inf.req = rnd[0];
endmodule : source
// drain module
module drain #(
// random generator parameters
parameter int unsigned RW=1, // LFSR width
parameter bit [RW-1:0] RP='0, // LFSR polinom
parameter bit [RW-1:0] RR='1 // LFSR reset state
)(
input logic clk,
input logic rst,
handshake.drn inf,
output integer cnt
);
// LFSR
logic [RW-1:0] rnd;
// LFSR in Galois form
always @ (posedge clk, posedge rst)
if (rst) rnd <= RR;
else rnd <= {rnd[0], rnd[RW-1:1]} ^ ({RW{rnd[0]}} & RP);
// counter
always @ (posedge clk, posedge rst)
if (rst) cnt <= 32'd0;
else cnt <= cnt + {31'd0, (inf.req & inf.grt)};
// grant signal
assign inf.grt = rnd[0];
endmodule : drain
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10036
///////////////////////////////////////////////////////////////////////////////
// Title : DDR controller AFi interfacing block
//
// File : afi_block.v
//
// Abstract : AFi block
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module alt_mem_ddrx_rdwr_data_tmg
# (parameter
CFG_DWIDTH_RATIO = 2,
CFG_MEM_IF_DQ_WIDTH = 8,
CFG_MEM_IF_DQS_WIDTH = 1,
CFG_MEM_IF_DM_WIDTH = 1,
CFG_WLAT_BUS_WIDTH = 6,
CFG_DRAM_WLAT_GROUP = 1,
CFG_DATA_ID_WIDTH = 10,
CFG_WDATA_REG = 0,
CFG_ECC_ENC_REG = 0,
CFG_AFI_INTF_PHASE_NUM = 2,
CFG_PORT_WIDTH_ENABLE_ECC = 1,
CFG_PORT_WIDTH_OUTPUT_REGD = 1
)
(
ctl_clk,
ctl_reset_n,
// configuration
cfg_enable_ecc,
cfg_output_regd,
cfg_output_regd_for_afi_output,
//Arbiter command input
bg_doing_read,
bg_doing_write,
bg_rdwr_data_valid, //Required for user burst length lesser than dram burst length
dataid,
bg_do_rmw_correct,
bg_do_rmw_partial,
//Inputs from ECC/WFIFO blocks
ecc_wdata,
ecc_dm,
//Input from AFI Block
afi_wlat,
//Output from AFI Block
afi_doing_read, //Use to generate rdata_valid signals in PHY
afi_doing_read_full, //AFI 2.0 signal, used by UniPHY for dqs enable control
ecc_wdata_fifo_read,
ecc_wdata_fifo_dataid,
ecc_wdata_fifo_dataid_vector,
ecc_wdata_fifo_rmw_correct,
ecc_wdata_fifo_rmw_partial,
ecc_wdata_fifo_read_first,
ecc_wdata_fifo_dataid_first,
ecc_wdata_fifo_dataid_vector_first,
ecc_wdata_fifo_rmw_correct_first,
ecc_wdata_fifo_rmw_partial_first,
ecc_wdata_fifo_first_vector,
ecc_wdata_fifo_read_last,
ecc_wdata_fifo_dataid_last,
ecc_wdata_fifo_dataid_vector_last,
ecc_wdata_fifo_rmw_correct_last,
ecc_wdata_fifo_rmw_partial_last,
afi_dqs_burst,
afi_wdata_valid,
afi_wdata,
afi_dm
);
localparam integer CFG_WLAT_PIPE_LENGTH = 2**(CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP);
localparam integer CFG_DATAID_ARRAY_DEPTH = 2**CFG_DATA_ID_WIDTH;
integer i;
//=================================================================================================//
// input/output declaration //
//=================================================================================================//
input ctl_clk;
input ctl_reset_n;
// configuration
input [CFG_PORT_WIDTH_ENABLE_ECC-1:0] cfg_enable_ecc;
input [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd;
output [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd_for_afi_output;
//Arbiter command input
input bg_doing_read;
input bg_doing_write;
input bg_rdwr_data_valid;
input [CFG_DATA_ID_WIDTH-1:0] dataid;
input [CFG_AFI_INTF_PHASE_NUM-1:0] bg_do_rmw_correct;
input [CFG_AFI_INTF_PHASE_NUM-1:0] bg_do_rmw_partial;
//Inputs from ECC/WFIFO blocks
input [CFG_MEM_IF_DQ_WIDTH*CFG_DWIDTH_RATIO-1:0] ecc_wdata;
input [(CFG_MEM_IF_DQ_WIDTH*CFG_DWIDTH_RATIO)/(CFG_MEM_IF_DQ_WIDTH/CFG_MEM_IF_DQS_WIDTH)-1:0] ecc_dm;
//Input from AFI Block
input [CFG_WLAT_BUS_WIDTH-1:0] afi_wlat;
//output to AFI block
output [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0] afi_doing_read;
output [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0] afi_doing_read_full;
output [CFG_DRAM_WLAT_GROUP-1:0] ecc_wdata_fifo_read;
output [CFG_DRAM_WLAT_GROUP*CFG_DATA_ID_WIDTH-1:0] ecc_wdata_fifo_dataid;
output [CFG_DRAM_WLAT_GROUP*CFG_DATAID_ARRAY_DEPTH-1:0] ecc_wdata_fifo_dataid_vector;
output [CFG_DRAM_WLAT_GROUP-1:0] ecc_wdata_fifo_rmw_correct;
output [CFG_DRAM_WLAT_GROUP-1:0] ecc_wdata_fifo_rmw_partial;
output ecc_wdata_fifo_read_first;
output [CFG_DATA_ID_WIDTH-1:0] ecc_wdata_fifo_dataid_first;
output [CFG_DATAID_ARRAY_DEPTH-1:0] ecc_wdata_fifo_dataid_vector_first;
output ecc_wdata_fifo_rmw_correct_first;
output ecc_wdata_fifo_rmw_partial_first;
output [CFG_DRAM_WLAT_GROUP-1:0] ecc_wdata_fifo_first_vector;
output ecc_wdata_fifo_read_last;
output [CFG_DATA_ID_WIDTH-1:0] ecc_wdata_fifo_dataid_last;
output [CFG_DATAID_ARRAY_DEPTH-1:0] ecc_wdata_fifo_dataid_vector_last;
output ecc_wdata_fifo_rmw_correct_last;
output ecc_wdata_fifo_rmw_partial_last;
output [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0] afi_dqs_burst;
output [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0] afi_wdata_valid;
output [CFG_MEM_IF_DQ_WIDTH*CFG_DWIDTH_RATIO-1:0] afi_wdata;
output [CFG_MEM_IF_DM_WIDTH*CFG_DWIDTH_RATIO-1:0] afi_dm;
//=================================================================================================//
// reg/wire declaration //
//=================================================================================================//
wire bg_doing_read;
wire bg_doing_write;
wire bg_rdwr_data_valid;
wire [CFG_DATA_ID_WIDTH-1:0] dataid;
wire [CFG_AFI_INTF_PHASE_NUM-1:0] bg_do_rmw_correct;
wire [CFG_AFI_INTF_PHASE_NUM-1:0] bg_do_rmw_partial;
wire [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0] afi_doing_read;
wire [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0] afi_doing_read_full;
wire [CFG_DRAM_WLAT_GROUP-1:0] ecc_wdata_fifo_read;
reg [CFG_DRAM_WLAT_GROUP-1:0] ecc_wdata_fifo_read_r;
wire [CFG_DRAM_WLAT_GROUP*CFG_DATA_ID_WIDTH-1:0] ecc_wdata_fifo_dataid;
wire [CFG_DRAM_WLAT_GROUP*CFG_DATAID_ARRAY_DEPTH-1:0] ecc_wdata_fifo_dataid_vector;
wire [CFG_DRAM_WLAT_GROUP-1:0] ecc_wdata_fifo_rmw_correct;
wire [CFG_DRAM_WLAT_GROUP-1:0] ecc_wdata_fifo_rmw_partial;
wire ecc_wdata_fifo_read_first;
wire [CFG_DATA_ID_WIDTH-1:0] ecc_wdata_fifo_dataid_first;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] ecc_wdata_fifo_dataid_vector_first;
wire ecc_wdata_fifo_rmw_correct_first;
wire ecc_wdata_fifo_rmw_partial_first;
reg [CFG_DRAM_WLAT_GROUP-1:0] ecc_wdata_fifo_first_vector;
wire ecc_wdata_fifo_read_last;
wire [CFG_DATA_ID_WIDTH-1:0] ecc_wdata_fifo_dataid_last;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] ecc_wdata_fifo_dataid_vector_last;
wire ecc_wdata_fifo_rmw_correct_last;
wire ecc_wdata_fifo_rmw_partial_last;
wire [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0] afi_dqs_burst;
wire [CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2)-1:0] afi_wdata_valid;
wire [CFG_MEM_IF_DQ_WIDTH*CFG_DWIDTH_RATIO-1:0] afi_wdata;
wire [CFG_MEM_IF_DM_WIDTH*CFG_DWIDTH_RATIO-1:0] afi_dm;
//Internal signals
reg [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd_for_afi_output_combi [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd_for_wdata_path_combi [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd_for_afi_output_mux [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd_for_wdata_path_mux [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd_for_afi_output;
reg [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd_for_wdata_path;
reg doing_read_combi;
reg doing_read_full_combi;
reg doing_read_r;
reg doing_read_full_r;
reg [CFG_WLAT_PIPE_LENGTH-1:0] doing_write_pipe;
reg [CFG_WLAT_PIPE_LENGTH-1:0] rdwr_data_valid_pipe;
reg [CFG_WLAT_PIPE_LENGTH-1:0] rmw_correct_pipe;
reg [CFG_WLAT_PIPE_LENGTH-1:0] rmw_partial_pipe;
reg [CFG_DATA_ID_WIDTH-1:0] dataid_pipe [CFG_WLAT_PIPE_LENGTH-1:0];
reg [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_vector_pipe [CFG_WLAT_PIPE_LENGTH-1:0];
reg [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_vector;
reg int_dqs_burst;
reg int_dqs_burst_r;
reg int_wdata_valid;
reg int_wdata_valid_r;
reg int_real_wdata_valid;
reg [CFG_DRAM_WLAT_GROUP-1:0] int_ecc_wdata_fifo_read;
reg [CFG_DRAM_WLAT_GROUP-1:0] int_ecc_wdata_fifo_read_r;
reg [CFG_DATA_ID_WIDTH-1:0] int_ecc_wdata_fifo_dataid [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_DATA_ID_WIDTH-1:0] int_ecc_wdata_fifo_dataid_r [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_DATAID_ARRAY_DEPTH-1:0] int_ecc_wdata_fifo_dataid_vector [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_DATAID_ARRAY_DEPTH-1:0] int_ecc_wdata_fifo_dataid_vector_r [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_DRAM_WLAT_GROUP-1:0] int_ecc_wdata_fifo_rmw_correct;
reg [CFG_DRAM_WLAT_GROUP-1:0] int_ecc_wdata_fifo_rmw_correct_r;
reg [CFG_DRAM_WLAT_GROUP-1:0] int_ecc_wdata_fifo_rmw_partial;
reg [CFG_DRAM_WLAT_GROUP-1:0] int_ecc_wdata_fifo_rmw_partial_r;
wire int_do_rmw_correct;
wire int_do_rmw_partial;
// DQS burst logic for half rate design
reg int_dqs_burst_half_rate;
reg int_dqs_burst_half_rate_r;
reg [CFG_DRAM_WLAT_GROUP-1:0] first_afi_wlat;
reg [CFG_DRAM_WLAT_GROUP-1:0] last_afi_wlat;
reg [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0] smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0] largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1:0];
reg smallest_afi_wlat_eq_0;
reg [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0] smallest_afi_wlat_minus_1;
reg [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0] smallest_afi_wlat_minus_2;
reg [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0] smallest_afi_wlat_minus_3;
reg smallest_doing_write_pipe_eq_afi_wlat_minus_0;
reg smallest_doing_write_pipe_eq_afi_wlat_minus_1;
reg smallest_doing_write_pipe_eq_afi_wlat_minus_2;
reg smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1;
reg smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2;
reg [CFG_DATA_ID_WIDTH-1:0] smallest_dataid_pipe_eq_afi_wlat_minus_1;
reg [CFG_DATA_ID_WIDTH-1:0] smallest_dataid_pipe_eq_afi_wlat_minus_2;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] smallest_dataid_vector_pipe_eq_afi_wlat_minus_1;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] smallest_dataid_vector_pipe_eq_afi_wlat_minus_2;
reg smallest_rmw_correct_pipe_eq_afi_wlat_minus_1;
reg smallest_rmw_correct_pipe_eq_afi_wlat_minus_2;
reg smallest_rmw_partial_pipe_eq_afi_wlat_minus_1;
reg smallest_rmw_partial_pipe_eq_afi_wlat_minus_2;
reg smallest_doing_write_pipe_eq_afi_wlat_minus_x;
reg smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x;
reg [CFG_DATA_ID_WIDTH-1:0] smallest_dataid_pipe_eq_afi_wlat_minus_x;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] smallest_dataid_vector_pipe_eq_afi_wlat_minus_x;
reg smallest_rmw_correct_pipe_eq_afi_wlat_minus_x;
reg smallest_rmw_partial_pipe_eq_afi_wlat_minus_x;
reg largest_afi_wlat_eq_0;
reg [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0] largest_afi_wlat_minus_1;
reg [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0] largest_afi_wlat_minus_2;
reg [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0] largest_afi_wlat_minus_3;
reg largest_doing_write_pipe_eq_afi_wlat_minus_0;
reg largest_doing_write_pipe_eq_afi_wlat_minus_1;
reg largest_doing_write_pipe_eq_afi_wlat_minus_2;
reg largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1;
reg largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2;
reg [CFG_DATA_ID_WIDTH-1:0] largest_dataid_pipe_eq_afi_wlat_minus_1;
reg [CFG_DATA_ID_WIDTH-1:0] largest_dataid_pipe_eq_afi_wlat_minus_2;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] largest_dataid_vector_pipe_eq_afi_wlat_minus_1;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] largest_dataid_vector_pipe_eq_afi_wlat_minus_2;
reg largest_rmw_correct_pipe_eq_afi_wlat_minus_1;
reg largest_rmw_correct_pipe_eq_afi_wlat_minus_2;
reg largest_rmw_partial_pipe_eq_afi_wlat_minus_1;
reg largest_rmw_partial_pipe_eq_afi_wlat_minus_2;
reg largest_doing_write_pipe_eq_afi_wlat_minus_x;
reg largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x;
reg [CFG_DATA_ID_WIDTH-1:0] largest_dataid_pipe_eq_afi_wlat_minus_x;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] largest_dataid_vector_pipe_eq_afi_wlat_minus_x;
reg largest_rmw_correct_pipe_eq_afi_wlat_minus_x;
reg largest_rmw_partial_pipe_eq_afi_wlat_minus_x;
reg afi_wlat_eq_0 [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0] afi_wlat_minus_1 [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0] afi_wlat_minus_2 [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_WLAT_BUS_WIDTH/CFG_DRAM_WLAT_GROUP-1:0] afi_wlat_minus_3 [CFG_DRAM_WLAT_GROUP-1:0];
reg doing_write_pipe_eq_afi_wlat_minus_0 [CFG_DRAM_WLAT_GROUP-1:0];
reg doing_write_pipe_eq_afi_wlat_minus_1 [CFG_DRAM_WLAT_GROUP-1:0];
reg doing_write_pipe_eq_afi_wlat_minus_2 [CFG_DRAM_WLAT_GROUP-1:0];
reg rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [CFG_DRAM_WLAT_GROUP-1:0];
reg rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_DATA_ID_WIDTH-1:0] dataid_pipe_eq_afi_wlat_minus_1 [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_DATA_ID_WIDTH-1:0] dataid_pipe_eq_afi_wlat_minus_2 [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_vector_pipe_eq_afi_wlat_minus_1 [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_vector_pipe_eq_afi_wlat_minus_2 [CFG_DRAM_WLAT_GROUP-1:0];
reg rmw_correct_pipe_eq_afi_wlat_minus_1 [CFG_DRAM_WLAT_GROUP-1:0];
reg rmw_correct_pipe_eq_afi_wlat_minus_2 [CFG_DRAM_WLAT_GROUP-1:0];
reg rmw_partial_pipe_eq_afi_wlat_minus_1 [CFG_DRAM_WLAT_GROUP-1:0];
reg rmw_partial_pipe_eq_afi_wlat_minus_2 [CFG_DRAM_WLAT_GROUP-1:0];
reg doing_write_pipe_eq_afi_wlat_minus_x [CFG_DRAM_WLAT_GROUP-1:0];
reg rdwr_data_valid_pipe_eq_afi_wlat_minus_x [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_DATA_ID_WIDTH-1:0] dataid_pipe_eq_afi_wlat_minus_x [CFG_DRAM_WLAT_GROUP-1:0];
reg [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_vector_pipe_eq_afi_wlat_minus_x [CFG_DRAM_WLAT_GROUP-1:0];
reg rmw_correct_pipe_eq_afi_wlat_minus_x [CFG_DRAM_WLAT_GROUP-1:0];
reg rmw_partial_pipe_eq_afi_wlat_minus_x [CFG_DRAM_WLAT_GROUP-1:0];
//=================================================================================================//
// Internal cfg_output_regd //
//=================================================================================================//
generate
genvar N;
for (N = 0;N < CFG_DRAM_WLAT_GROUP;N = N + 1)
begin : output_regd_logic_per_dqs_group
always @ (*)
begin
if (CFG_WDATA_REG || CFG_ECC_ENC_REG)
begin
if (afi_wlat [(N + 1) * (CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP) - 1 : N * (CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP)] <= 1)
begin
// We enable output_regd for signals going to PHY
// because we need to fetch data 2 clock cycles earlier
cfg_output_regd_for_afi_output_combi [N] = 1'b1;
// We disable output_regd for signals going to wdata_path
// because we need to fecth data 2 clock cycles earlier
cfg_output_regd_for_wdata_path_combi [N] = 1'b0;
end
else
begin
cfg_output_regd_for_afi_output_combi [N] = cfg_output_regd;
cfg_output_regd_for_wdata_path_combi [N] = cfg_output_regd;
end
end
else
begin
cfg_output_regd_for_afi_output_combi [N] = cfg_output_regd;
cfg_output_regd_for_wdata_path_combi [N] = cfg_output_regd;
end
end
end
for (N = 1;N < CFG_DRAM_WLAT_GROUP;N = N + 1)
begin : output_regd_mux_logic
always @ (*)
begin
cfg_output_regd_for_afi_output_mux [N] = cfg_output_regd_for_afi_output_combi [N] | cfg_output_regd_for_afi_output_mux [N-1];
cfg_output_regd_for_wdata_path_mux [N] = cfg_output_regd_for_wdata_path_combi [N] | cfg_output_regd_for_wdata_path_mux [N-1];
end
end
endgenerate
always @ (*)
begin
cfg_output_regd_for_afi_output_mux [0] = cfg_output_regd_for_afi_output_combi [0];
cfg_output_regd_for_wdata_path_mux [0] = cfg_output_regd_for_wdata_path_combi [0];
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_output_regd_for_afi_output <= 1'b0;
cfg_output_regd_for_wdata_path <= 1'b0;
end
else
begin
cfg_output_regd_for_afi_output <= cfg_output_regd_for_afi_output_mux [CFG_DRAM_WLAT_GROUP-1];
cfg_output_regd_for_wdata_path <= cfg_output_regd_for_wdata_path_mux [CFG_DRAM_WLAT_GROUP-1];
end
end
//=================================================================================================//
// Read timing logic //
//=================================================================================================//
//*************************************************************************************************//
// afi_doing_read generation logic //
//*************************************************************************************************//
always @(*)
begin
if (bg_doing_read && bg_rdwr_data_valid)
begin
doing_read_combi = 1'b1;
end
else
begin
doing_read_combi = 1'b0;
end
doing_read_full_combi = bg_doing_read;
end
// registered output
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_read_r <= 1'b0;
doing_read_full_r <= 1'b0;
end
else
begin
doing_read_r <= doing_read_combi;
doing_read_full_r <= doing_read_full_combi;
end
end
generate
genvar I;
for (I = 0; I < CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2); I = I + 1)
begin : B
assign afi_doing_read [I] = (cfg_output_regd_for_afi_output) ? doing_read_r : doing_read_combi;
assign afi_doing_read_full [I] = (cfg_output_regd_for_afi_output) ? doing_read_full_r : doing_read_full_combi;
end
endgenerate
//=================================================================================================//
// Write timing logic //
//=================================================================================================//
// Content of pipe shows how long dqs should toggle, used to generate dqs_burst
// content of pipe is also used to generate wdata_valid signal
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_write_pipe <= 0;
end
else
begin
doing_write_pipe <= {doing_write_pipe[CFG_WLAT_PIPE_LENGTH -2 :0],bg_doing_write};
end
end
// content of pipe shows how much data should be read out of the write data FIFO
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
rdwr_data_valid_pipe <= 0;
end
else
begin
rdwr_data_valid_pipe <= {rdwr_data_valid_pipe[CFG_WLAT_PIPE_LENGTH - 2:0],bg_rdwr_data_valid};
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_WLAT_PIPE_LENGTH; i=i+1)
begin
dataid_pipe [i] <= 0;
end
end
else
begin
dataid_pipe [0] <= dataid;
for (i=1; i<CFG_WLAT_PIPE_LENGTH; i=i+1)
begin
dataid_pipe [i] <= dataid_pipe[i-1];
end
end
end
//pre-calculated dataid comparison logic
always @ (*)
begin
for (i=0; i<(CFG_DATAID_ARRAY_DEPTH); i=i+1)
begin
if (dataid == i)
begin
dataid_vector [i] = 1'b1;
end
else
begin
dataid_vector [i] = 1'b0;
end
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
dataid_vector_pipe [0] <= 0;
for (i=1; i<CFG_WLAT_PIPE_LENGTH; i=i+1)
begin
dataid_vector_pipe [i] <= 0;
end
end
else
begin
dataid_vector_pipe [0] <= dataid_vector;
for (i=1; i<CFG_WLAT_PIPE_LENGTH; i=i+1)
begin
dataid_vector_pipe [i] <= dataid_vector_pipe[i-1];
end
end
end
assign int_do_rmw_correct = |bg_do_rmw_correct;
assign int_do_rmw_partial = |bg_do_rmw_partial;
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
rmw_correct_pipe <= 0;
end
else
begin
rmw_correct_pipe <= {rmw_correct_pipe[CFG_WLAT_PIPE_LENGTH - 2:0],int_do_rmw_correct};
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
rmw_partial_pipe <= 0;
end
else
begin
rmw_partial_pipe <= {rmw_partial_pipe[CFG_WLAT_PIPE_LENGTH - 2:0],int_do_rmw_partial};
end
end
// Pre-calculated logic for each DQS group
generate
genvar P;
for (P = 0;P < CFG_DRAM_WLAT_GROUP;P = P + 1)
begin : pre_calculate_logic_per_dqs_group
// afi_wlat for current DQS group
wire [(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP) - 1 : 0] current_afi_wlat = afi_wlat [(P + 1) * (CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP) - 1 : P * (CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP)];
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
afi_wlat_eq_0 [P] <= 1'b0;
afi_wlat_minus_1 [P] <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
afi_wlat_minus_2 [P] <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
afi_wlat_minus_3 [P] <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
end
else
begin
if (current_afi_wlat == 0)
begin
afi_wlat_eq_0 [P] <= 1'b1;
end
else
begin
afi_wlat_eq_0 [P] <= 1'b0;
end
afi_wlat_minus_1 [P] <= current_afi_wlat - 1;
afi_wlat_minus_2 [P] <= current_afi_wlat - 2;
afi_wlat_minus_3 [P] <= current_afi_wlat - 3;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b0;
doing_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
doing_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
else
begin
if (current_afi_wlat == 0)
begin
doing_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b0;
doing_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
doing_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
else if (current_afi_wlat == 1)
begin
if (doing_write_pipe[0])
begin
doing_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b1;
end
else
begin
doing_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b0;
end
if (bg_doing_write)
begin
doing_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
doing_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (bg_doing_write) // we must disable int_cfg_output_regd when (afi_wlat < 2)
begin
doing_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
doing_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
end
else if (current_afi_wlat == 2)
begin
if (doing_write_pipe[1])
begin
doing_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b1;
end
else
begin
doing_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b0;
end
if (doing_write_pipe[0])
begin
doing_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
doing_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (bg_doing_write)
begin
doing_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
doing_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
end
else
begin
if (doing_write_pipe[afi_wlat_minus_1 [P]])
begin
doing_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b1;
end
else
begin
doing_write_pipe_eq_afi_wlat_minus_0 [P] <= 1'b0;
end
if (doing_write_pipe[afi_wlat_minus_2 [P]])
begin
doing_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
doing_write_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (doing_write_pipe[afi_wlat_minus_3 [P]])
begin
doing_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
doing_write_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
else
begin
if (current_afi_wlat == 0)
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
else if (current_afi_wlat == 1)
begin
if (bg_rdwr_data_valid)
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (bg_rdwr_data_valid) // we must disable int_cfg_output_regd when (afi_wlat < 2)
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
end
else if (current_afi_wlat == 2)
begin
if (rdwr_data_valid_pipe[0])
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (bg_rdwr_data_valid)
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
end
else
begin
if (rdwr_data_valid_pipe[afi_wlat_minus_2 [P]])
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (rdwr_data_valid_pipe[afi_wlat_minus_3 [P]])
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
dataid_pipe_eq_afi_wlat_minus_1 [P] <= 0;
dataid_pipe_eq_afi_wlat_minus_2 [P] <= 0;
dataid_vector_pipe_eq_afi_wlat_minus_1 [P] <= 0;
dataid_vector_pipe_eq_afi_wlat_minus_2 [P] <= 0;
end
else
begin
if (current_afi_wlat == 0)
begin
dataid_pipe_eq_afi_wlat_minus_1 [P] <= 0;
dataid_pipe_eq_afi_wlat_minus_2 [P] <= 0;
dataid_vector_pipe_eq_afi_wlat_minus_1 [P] <= 0;
dataid_vector_pipe_eq_afi_wlat_minus_2 [P] <= 0;
end
else if (current_afi_wlat == 1)
begin
dataid_pipe_eq_afi_wlat_minus_1 [P] <= dataid;
dataid_pipe_eq_afi_wlat_minus_2 [P] <= dataid; // we must disable int_cfg_output_regd when (afi_wlat < 2)
dataid_vector_pipe_eq_afi_wlat_minus_1 [P] <= dataid_vector;
dataid_vector_pipe_eq_afi_wlat_minus_2 [P] <= dataid_vector; // we must disable int_cfg_output_regd when (afi_wlat < 2)
end
else if (current_afi_wlat == 2)
begin
dataid_pipe_eq_afi_wlat_minus_1 [P] <= dataid_pipe [0];
dataid_pipe_eq_afi_wlat_minus_2 [P] <= dataid;
dataid_vector_pipe_eq_afi_wlat_minus_1 [P] <= dataid_vector_pipe[0];
dataid_vector_pipe_eq_afi_wlat_minus_2 [P] <= dataid_vector;
end
else
begin
dataid_pipe_eq_afi_wlat_minus_1 [P] <= dataid_pipe [afi_wlat_minus_2 [P]];
dataid_pipe_eq_afi_wlat_minus_2 [P] <= dataid_pipe [afi_wlat_minus_3 [P]];
dataid_vector_pipe_eq_afi_wlat_minus_1 [P] <= dataid_vector_pipe[afi_wlat_minus_2 [P]];
dataid_vector_pipe_eq_afi_wlat_minus_2 [P] <= dataid_vector_pipe[afi_wlat_minus_3 [P]];
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
rmw_correct_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
rmw_correct_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
rmw_partial_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
rmw_partial_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
else
begin
if (current_afi_wlat == 0)
begin
rmw_correct_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
rmw_correct_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
rmw_partial_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
rmw_partial_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
else if (current_afi_wlat == 1)
begin
if (int_do_rmw_correct)
begin
rmw_correct_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
rmw_correct_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (int_do_rmw_partial)
begin
rmw_partial_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
rmw_partial_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (int_do_rmw_correct) // we must disable int_cfg_output_regd when (afi_wlat < 2)
begin
rmw_correct_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
rmw_correct_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
if (int_do_rmw_partial) // we must disable int_cfg_output_regd when (afi_wlat < 2)
begin
rmw_partial_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
rmw_partial_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
end
else if (current_afi_wlat == 2)
begin
if (rmw_correct_pipe[0])
begin
rmw_correct_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
rmw_correct_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (rmw_partial_pipe[0])
begin
rmw_partial_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
rmw_partial_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (int_do_rmw_correct)
begin
rmw_correct_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
rmw_correct_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
if (int_do_rmw_partial)
begin
rmw_partial_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
rmw_partial_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
end
else
begin
if (rmw_correct_pipe[afi_wlat_minus_2 [P]])
begin
rmw_correct_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
rmw_correct_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (rmw_partial_pipe[afi_wlat_minus_2 [P]])
begin
rmw_partial_pipe_eq_afi_wlat_minus_1 [P] <= 1'b1;
end
else
begin
rmw_partial_pipe_eq_afi_wlat_minus_1 [P] <= 1'b0;
end
if (rmw_correct_pipe[afi_wlat_minus_3 [P]])
begin
rmw_correct_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
rmw_correct_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
if (rmw_partial_pipe[afi_wlat_minus_3 [P]])
begin
rmw_partial_pipe_eq_afi_wlat_minus_2 [P] <= 1'b1;
end
else
begin
rmw_partial_pipe_eq_afi_wlat_minus_2 [P] <= 1'b0;
end
end
end
end
always @ (*)
begin
if (CFG_WDATA_REG || CFG_ECC_ENC_REG)
begin
doing_write_pipe_eq_afi_wlat_minus_x [P] = doing_write_pipe_eq_afi_wlat_minus_2 [P];
rdwr_data_valid_pipe_eq_afi_wlat_minus_x [P] = rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [P];
dataid_pipe_eq_afi_wlat_minus_x [P] = dataid_pipe_eq_afi_wlat_minus_2 [P];
dataid_vector_pipe_eq_afi_wlat_minus_x [P] = dataid_vector_pipe_eq_afi_wlat_minus_2 [P];
rmw_correct_pipe_eq_afi_wlat_minus_x [P] = rmw_correct_pipe_eq_afi_wlat_minus_2 [P];
rmw_partial_pipe_eq_afi_wlat_minus_x [P] = rmw_partial_pipe_eq_afi_wlat_minus_2 [P];
end
else
begin
doing_write_pipe_eq_afi_wlat_minus_x [P] = doing_write_pipe_eq_afi_wlat_minus_1 [P];
rdwr_data_valid_pipe_eq_afi_wlat_minus_x [P] = rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [P];
dataid_pipe_eq_afi_wlat_minus_x [P] = dataid_pipe_eq_afi_wlat_minus_1 [P];
dataid_vector_pipe_eq_afi_wlat_minus_x [P] = dataid_vector_pipe_eq_afi_wlat_minus_1 [P];
rmw_correct_pipe_eq_afi_wlat_minus_x [P] = rmw_correct_pipe_eq_afi_wlat_minus_1 [P];
rmw_partial_pipe_eq_afi_wlat_minus_x [P] = rmw_partial_pipe_eq_afi_wlat_minus_1 [P];
end
end
// First vector
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
ecc_wdata_fifo_first_vector [P] <= 1'b0;
end
else
begin
if (current_afi_wlat == smallest_afi_wlat [CFG_DRAM_WLAT_GROUP - 1])
begin
ecc_wdata_fifo_first_vector [P] <= 1'b1;
end
else
begin
ecc_wdata_fifo_first_vector [P] <= 1'b0;
end
end
end
end
for (P = 1;P < CFG_DRAM_WLAT_GROUP;P = P + 1)
begin : afi_wlat_info_logic
// afi_wlat for current DQS group
wire [(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP) - 1 : 0] current_afi_wlat = afi_wlat [(P + 1) * (CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP) - 1 : P * (CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP)];
// Smallest/largest afi_wlat logic
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
smallest_afi_wlat [P] <= 0;
largest_afi_wlat [P] <= 0;
end
else
begin
if (current_afi_wlat < smallest_afi_wlat [P-1])
begin
smallest_afi_wlat [P] <= current_afi_wlat;
end
else
begin
smallest_afi_wlat [P] <= smallest_afi_wlat [P-1];
end
if (current_afi_wlat > largest_afi_wlat [P-1])
begin
largest_afi_wlat [P] <= current_afi_wlat;
end
else
begin
largest_afi_wlat [P] <= largest_afi_wlat [P-1];
end
end
end
end
endgenerate
// Smallest/largest afi_wlat logic
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
smallest_afi_wlat [0] <= 0;
largest_afi_wlat [0] <= 0;
end
else
begin
smallest_afi_wlat [0] <= afi_wlat [(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP) - 1 : 0];
largest_afi_wlat [0] <= afi_wlat [(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP) - 1 : 0];
end
end
generate
if (CFG_DRAM_WLAT_GROUP == 1) // only one group of afi_wlat
begin
always @ (*)
begin
smallest_afi_wlat_eq_0 = afi_wlat_eq_0 [0];
smallest_afi_wlat_minus_1 = afi_wlat_minus_1 [0];
smallest_afi_wlat_minus_2 = afi_wlat_minus_2 [0];
smallest_afi_wlat_minus_3 = afi_wlat_minus_3 [0];
smallest_doing_write_pipe_eq_afi_wlat_minus_0 = doing_write_pipe_eq_afi_wlat_minus_0 [0];
smallest_doing_write_pipe_eq_afi_wlat_minus_1 = doing_write_pipe_eq_afi_wlat_minus_1 [0];
smallest_doing_write_pipe_eq_afi_wlat_minus_2 = doing_write_pipe_eq_afi_wlat_minus_2 [0];
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 = rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [0];
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 = rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [0];
smallest_dataid_pipe_eq_afi_wlat_minus_1 = dataid_pipe_eq_afi_wlat_minus_1 [0];
smallest_dataid_pipe_eq_afi_wlat_minus_2 = dataid_pipe_eq_afi_wlat_minus_2 [0];
smallest_dataid_vector_pipe_eq_afi_wlat_minus_1 = dataid_vector_pipe_eq_afi_wlat_minus_1 [0];
smallest_dataid_vector_pipe_eq_afi_wlat_minus_2 = dataid_vector_pipe_eq_afi_wlat_minus_2 [0];
smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 = rmw_correct_pipe_eq_afi_wlat_minus_1 [0];
smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 = rmw_correct_pipe_eq_afi_wlat_minus_2 [0];
smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 = rmw_partial_pipe_eq_afi_wlat_minus_1 [0];
smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 = rmw_partial_pipe_eq_afi_wlat_minus_2 [0];
smallest_doing_write_pipe_eq_afi_wlat_minus_x = doing_write_pipe_eq_afi_wlat_minus_x [0];
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x = rdwr_data_valid_pipe_eq_afi_wlat_minus_x [0];
smallest_dataid_pipe_eq_afi_wlat_minus_x = dataid_pipe_eq_afi_wlat_minus_x [0];
smallest_dataid_vector_pipe_eq_afi_wlat_minus_x = dataid_vector_pipe_eq_afi_wlat_minus_x [0];
smallest_rmw_correct_pipe_eq_afi_wlat_minus_x = rmw_correct_pipe_eq_afi_wlat_minus_x [0];
smallest_rmw_partial_pipe_eq_afi_wlat_minus_x = rmw_partial_pipe_eq_afi_wlat_minus_x [0];
largest_afi_wlat_eq_0 = afi_wlat_eq_0 [0];
largest_afi_wlat_minus_1 = afi_wlat_minus_1 [0];
largest_afi_wlat_minus_2 = afi_wlat_minus_2 [0];
largest_afi_wlat_minus_3 = afi_wlat_minus_3 [0];
largest_doing_write_pipe_eq_afi_wlat_minus_0 = doing_write_pipe_eq_afi_wlat_minus_0 [0];
largest_doing_write_pipe_eq_afi_wlat_minus_1 = doing_write_pipe_eq_afi_wlat_minus_1 [0];
largest_doing_write_pipe_eq_afi_wlat_minus_2 = doing_write_pipe_eq_afi_wlat_minus_2 [0];
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 = rdwr_data_valid_pipe_eq_afi_wlat_minus_1 [0];
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 = rdwr_data_valid_pipe_eq_afi_wlat_minus_2 [0];
largest_dataid_pipe_eq_afi_wlat_minus_1 = dataid_pipe_eq_afi_wlat_minus_1 [0];
largest_dataid_pipe_eq_afi_wlat_minus_2 = dataid_pipe_eq_afi_wlat_minus_2 [0];
largest_dataid_vector_pipe_eq_afi_wlat_minus_1 = dataid_vector_pipe_eq_afi_wlat_minus_1 [0];
largest_dataid_vector_pipe_eq_afi_wlat_minus_2 = dataid_vector_pipe_eq_afi_wlat_minus_2 [0];
largest_rmw_correct_pipe_eq_afi_wlat_minus_1 = rmw_correct_pipe_eq_afi_wlat_minus_1 [0];
largest_rmw_correct_pipe_eq_afi_wlat_minus_2 = rmw_correct_pipe_eq_afi_wlat_minus_2 [0];
largest_rmw_partial_pipe_eq_afi_wlat_minus_1 = rmw_partial_pipe_eq_afi_wlat_minus_1 [0];
largest_rmw_partial_pipe_eq_afi_wlat_minus_2 = rmw_partial_pipe_eq_afi_wlat_minus_2 [0];
largest_doing_write_pipe_eq_afi_wlat_minus_x = doing_write_pipe_eq_afi_wlat_minus_x [0];
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x = rdwr_data_valid_pipe_eq_afi_wlat_minus_x [0];
largest_dataid_pipe_eq_afi_wlat_minus_x = dataid_pipe_eq_afi_wlat_minus_x [0];
largest_dataid_vector_pipe_eq_afi_wlat_minus_x = dataid_vector_pipe_eq_afi_wlat_minus_x [0];
largest_rmw_correct_pipe_eq_afi_wlat_minus_x = rmw_correct_pipe_eq_afi_wlat_minus_x [0];
largest_rmw_partial_pipe_eq_afi_wlat_minus_x = rmw_partial_pipe_eq_afi_wlat_minus_x [0];
end
end
else
begin
// Pre-calculated logic for smallest/largest afi_wlat (for afi addr/cmd logic)
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
smallest_afi_wlat_eq_0 <= 1'b0;
smallest_afi_wlat_minus_1 <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
smallest_afi_wlat_minus_2 <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
smallest_afi_wlat_minus_3 <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
end
else
begin
if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
begin
smallest_afi_wlat_eq_0 <= 1'b1;
end
else
begin
smallest_afi_wlat_eq_0 <= 1'b0;
end
smallest_afi_wlat_minus_1 <= smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] - 1;
smallest_afi_wlat_minus_2 <= smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] - 2;
smallest_afi_wlat_minus_3 <= smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] - 3;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b0;
smallest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b0;
smallest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
else
begin
if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b0;
smallest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b0;
smallest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
else if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 1)
begin
if (doing_write_pipe[0])
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b1;
end
else
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b0;
end
if (bg_doing_write)
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (bg_doing_write) // we must disable int_cfg_output_regd when (afi_wlat < 2)
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
else if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 2)
begin
if (doing_write_pipe[1])
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b1;
end
else
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b0;
end
if (doing_write_pipe[0])
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (bg_doing_write)
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
else
begin
if (doing_write_pipe[smallest_afi_wlat_minus_1])
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b1;
end
else
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b0;
end
if (doing_write_pipe[smallest_afi_wlat_minus_2])
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (doing_write_pipe[smallest_afi_wlat_minus_3])
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
else
begin
if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
else if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 1)
begin
if (bg_rdwr_data_valid)
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (bg_rdwr_data_valid) // we must disable int_cfg_output_regd when (afi_wlat < 2)
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
else if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 2)
begin
if (rdwr_data_valid_pipe[0])
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (bg_rdwr_data_valid)
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
else
begin
if (rdwr_data_valid_pipe[smallest_afi_wlat_minus_2])
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (rdwr_data_valid_pipe[smallest_afi_wlat_minus_3])
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
smallest_dataid_pipe_eq_afi_wlat_minus_1 <= 0;
smallest_dataid_pipe_eq_afi_wlat_minus_2 <= 0;
smallest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= 0;
smallest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= 0;
end
else
begin
if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
begin
smallest_dataid_pipe_eq_afi_wlat_minus_1 <= 0;
smallest_dataid_pipe_eq_afi_wlat_minus_2 <= 0;
smallest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= 0;
smallest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= 0;
end
else if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 1)
begin
smallest_dataid_pipe_eq_afi_wlat_minus_1 <= dataid;
smallest_dataid_pipe_eq_afi_wlat_minus_2 <= dataid; // we must disable int_cfg_output_regd when (afi_wlat < 2)
smallest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= dataid_vector;
smallest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= dataid_vector; // we must disable int_cfg_output_regd when (afi_wlat < 2)
end
else if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 2)
begin
smallest_dataid_pipe_eq_afi_wlat_minus_1 <= dataid_pipe [0];
smallest_dataid_pipe_eq_afi_wlat_minus_2 <= dataid;
smallest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= dataid_vector_pipe[0];
smallest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= dataid_vector;
end
else
begin
smallest_dataid_pipe_eq_afi_wlat_minus_1 <= dataid_pipe [smallest_afi_wlat_minus_2];
smallest_dataid_pipe_eq_afi_wlat_minus_2 <= dataid_pipe [smallest_afi_wlat_minus_3];
smallest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= dataid_vector_pipe[smallest_afi_wlat_minus_2];
smallest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= dataid_vector_pipe[smallest_afi_wlat_minus_3];
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
else
begin
if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
else if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 1)
begin
if (int_do_rmw_correct)
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (int_do_rmw_partial)
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (int_do_rmw_correct) // we must disable int_cfg_output_regd when (afi_wlat < 2)
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (int_do_rmw_partial) // we must disable int_cfg_output_regd when (afi_wlat < 2)
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
else if (smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 2)
begin
if (rmw_correct_pipe[0])
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (rmw_partial_pipe[0])
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (int_do_rmw_correct)
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (int_do_rmw_partial)
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
else
begin
if (rmw_correct_pipe[smallest_afi_wlat_minus_2])
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (rmw_partial_pipe[smallest_afi_wlat_minus_2])
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (rmw_correct_pipe[smallest_afi_wlat_minus_3])
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (rmw_partial_pipe[smallest_afi_wlat_minus_3])
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
end
end
always @ (*)
begin
if (CFG_WDATA_REG || CFG_ECC_ENC_REG)
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_x = smallest_doing_write_pipe_eq_afi_wlat_minus_2 ;
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x = smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2;
smallest_dataid_pipe_eq_afi_wlat_minus_x = smallest_dataid_pipe_eq_afi_wlat_minus_2 ;
smallest_dataid_vector_pipe_eq_afi_wlat_minus_x = smallest_dataid_vector_pipe_eq_afi_wlat_minus_2 ;
smallest_rmw_correct_pipe_eq_afi_wlat_minus_x = smallest_rmw_correct_pipe_eq_afi_wlat_minus_2 ;
smallest_rmw_partial_pipe_eq_afi_wlat_minus_x = smallest_rmw_partial_pipe_eq_afi_wlat_minus_2 ;
end
else
begin
smallest_doing_write_pipe_eq_afi_wlat_minus_x = smallest_doing_write_pipe_eq_afi_wlat_minus_1 ;
smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x = smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1;
smallest_dataid_pipe_eq_afi_wlat_minus_x = smallest_dataid_pipe_eq_afi_wlat_minus_1 ;
smallest_dataid_vector_pipe_eq_afi_wlat_minus_x = smallest_dataid_vector_pipe_eq_afi_wlat_minus_1 ;
smallest_rmw_correct_pipe_eq_afi_wlat_minus_x = smallest_rmw_correct_pipe_eq_afi_wlat_minus_1 ;
smallest_rmw_partial_pipe_eq_afi_wlat_minus_x = smallest_rmw_partial_pipe_eq_afi_wlat_minus_1 ;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
largest_afi_wlat_eq_0 <= 1'b0;
largest_afi_wlat_minus_1 <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
largest_afi_wlat_minus_2 <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
largest_afi_wlat_minus_3 <= {(CFG_WLAT_BUS_WIDTH / CFG_DRAM_WLAT_GROUP){1'b0}};
end
else
begin
if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
begin
largest_afi_wlat_eq_0 <= 1'b1;
end
else
begin
largest_afi_wlat_eq_0 <= 1'b0;
end
largest_afi_wlat_minus_1 <= largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] - 1;
largest_afi_wlat_minus_2 <= largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] - 2;
largest_afi_wlat_minus_3 <= largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] - 3;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
largest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b0;
largest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b0;
largest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
else
begin
if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
begin
largest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b0;
largest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b0;
largest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
else if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 1)
begin
if (doing_write_pipe[0])
begin
largest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b1;
end
else
begin
largest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b0;
end
if (bg_doing_write)
begin
largest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (bg_doing_write) // we must disable int_cfg_output_regd when (afi_wlat < 2)
begin
largest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
else if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 2)
begin
if (doing_write_pipe[1])
begin
largest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b1;
end
else
begin
largest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b0;
end
if (doing_write_pipe[0])
begin
largest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (bg_doing_write)
begin
largest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
else
begin
if (doing_write_pipe[largest_afi_wlat_minus_1])
begin
largest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b1;
end
else
begin
largest_doing_write_pipe_eq_afi_wlat_minus_0 <= 1'b0;
end
if (doing_write_pipe[largest_afi_wlat_minus_2])
begin
largest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_doing_write_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (doing_write_pipe[largest_afi_wlat_minus_3])
begin
largest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_doing_write_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
else
begin
if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
else if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 1)
begin
if (bg_rdwr_data_valid)
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (bg_rdwr_data_valid) // we must disable int_cfg_output_regd when (afi_wlat < 2)
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
else if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 2)
begin
if (rdwr_data_valid_pipe[0])
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (bg_rdwr_data_valid)
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
else
begin
if (rdwr_data_valid_pipe[largest_afi_wlat_minus_2])
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (rdwr_data_valid_pipe[largest_afi_wlat_minus_3])
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
largest_dataid_pipe_eq_afi_wlat_minus_1 <= 0;
largest_dataid_pipe_eq_afi_wlat_minus_2 <= 0;
largest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= 0;
largest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= 0;
end
else
begin
if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
begin
largest_dataid_pipe_eq_afi_wlat_minus_1 <= 0;
largest_dataid_pipe_eq_afi_wlat_minus_2 <= 0;
largest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= 0;
largest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= 0;
end
else if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 1)
begin
largest_dataid_pipe_eq_afi_wlat_minus_1 <= dataid;
largest_dataid_pipe_eq_afi_wlat_minus_2 <= dataid; // we must disable int_cfg_output_regd when (afi_wlat < 2)
largest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= dataid_vector;
largest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= dataid_vector; // we must disable int_cfg_output_regd when (afi_wlat < 2)
end
else if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 2)
begin
largest_dataid_pipe_eq_afi_wlat_minus_1 <= dataid_pipe [0];
largest_dataid_pipe_eq_afi_wlat_minus_2 <= dataid;
largest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= dataid_vector_pipe[0];
largest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= dataid_vector;
end
else
begin
largest_dataid_pipe_eq_afi_wlat_minus_1 <= dataid_pipe [largest_afi_wlat_minus_2];
largest_dataid_pipe_eq_afi_wlat_minus_2 <= dataid_pipe [largest_afi_wlat_minus_3];
largest_dataid_vector_pipe_eq_afi_wlat_minus_1 <= dataid_vector_pipe[largest_afi_wlat_minus_2];
largest_dataid_vector_pipe_eq_afi_wlat_minus_2 <= dataid_vector_pipe[largest_afi_wlat_minus_3];
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
largest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
largest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
largest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
else
begin
if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 0)
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
largest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
largest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
largest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
else if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 1)
begin
if (int_do_rmw_correct)
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (int_do_rmw_partial)
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (int_do_rmw_correct) // we must disable int_cfg_output_regd when (afi_wlat < 2)
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (int_do_rmw_partial) // we must disable int_cfg_output_regd when (afi_wlat < 2)
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
else if (largest_afi_wlat [CFG_DRAM_WLAT_GROUP-1] == 2)
begin
if (rmw_correct_pipe[0])
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (rmw_partial_pipe[0])
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (int_do_rmw_correct)
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (int_do_rmw_partial)
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
else
begin
if (rmw_correct_pipe[largest_afi_wlat_minus_2])
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (rmw_partial_pipe[largest_afi_wlat_minus_2])
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b1;
end
else
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_1 <= 1'b0;
end
if (rmw_correct_pipe[largest_afi_wlat_minus_3])
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_rmw_correct_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
if (rmw_partial_pipe[largest_afi_wlat_minus_3])
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b1;
end
else
begin
largest_rmw_partial_pipe_eq_afi_wlat_minus_2 <= 1'b0;
end
end
end
end
always @ (*)
begin
if (CFG_WDATA_REG || CFG_ECC_ENC_REG)
begin
largest_doing_write_pipe_eq_afi_wlat_minus_x = largest_doing_write_pipe_eq_afi_wlat_minus_2 ;
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x = largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_2;
largest_dataid_pipe_eq_afi_wlat_minus_x = largest_dataid_pipe_eq_afi_wlat_minus_2 ;
largest_dataid_vector_pipe_eq_afi_wlat_minus_x = largest_dataid_vector_pipe_eq_afi_wlat_minus_2 ;
largest_rmw_correct_pipe_eq_afi_wlat_minus_x = largest_rmw_correct_pipe_eq_afi_wlat_minus_2 ;
largest_rmw_partial_pipe_eq_afi_wlat_minus_x = largest_rmw_partial_pipe_eq_afi_wlat_minus_2 ;
end
else
begin
largest_doing_write_pipe_eq_afi_wlat_minus_x = largest_doing_write_pipe_eq_afi_wlat_minus_1 ;
largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x = largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_1;
largest_dataid_pipe_eq_afi_wlat_minus_x = largest_dataid_pipe_eq_afi_wlat_minus_1 ;
largest_dataid_vector_pipe_eq_afi_wlat_minus_x = largest_dataid_vector_pipe_eq_afi_wlat_minus_1 ;
largest_rmw_correct_pipe_eq_afi_wlat_minus_x = largest_rmw_correct_pipe_eq_afi_wlat_minus_1 ;
largest_rmw_partial_pipe_eq_afi_wlat_minus_x = largest_rmw_partial_pipe_eq_afi_wlat_minus_1 ;
end
end
end
endgenerate
//*************************************************************************************************//
// afi_dqs_burst generation logic //
//*************************************************************************************************//
// high earlier than wdata_valid but ends the same
// for writes only, where dqs should toggle, use doing_write_pipe
always @(*)
begin
if (smallest_afi_wlat_eq_0)
begin
if (bg_doing_write || doing_write_pipe[0])
begin
int_dqs_burst = 1'b1;
end
else
begin
int_dqs_burst = 1'b0;
end
end
else
begin
if (smallest_doing_write_pipe_eq_afi_wlat_minus_1 || smallest_doing_write_pipe_eq_afi_wlat_minus_0)
begin
int_dqs_burst = 1'b1;
end
else
begin
int_dqs_burst = 1'b0;
end
end
end
// registered output
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_dqs_burst_r <= 1'b0;
end
else
begin
int_dqs_burst_r <= int_dqs_burst;
end
end
always @ (*)
begin
if (smallest_afi_wlat_eq_0)
begin
if (doing_write_pipe[0])
begin
int_dqs_burst_half_rate = 1'b1;
end
else
begin
int_dqs_burst_half_rate = 1'b0;
end
end
else
begin
if (doing_write_pipe[smallest_afi_wlat [CFG_DRAM_WLAT_GROUP-1]])
begin
int_dqs_burst_half_rate = 1'b1;
end
else
begin
int_dqs_burst_half_rate = 1'b0;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_dqs_burst_half_rate_r <= 1'b0;
end
else
begin
int_dqs_burst_half_rate_r <= int_dqs_burst_half_rate;
end
end
generate
genvar K;
if (CFG_DWIDTH_RATIO == 2) // fullrate
begin
for (K = 0; K < CFG_MEM_IF_DQS_WIDTH; K = K + 1)
begin : C
assign afi_dqs_burst[K] = (cfg_output_regd_for_afi_output == 1) ? int_dqs_burst_r : int_dqs_burst;
end
end
else if (CFG_DWIDTH_RATIO == 4) // halfrate
begin
for (K = 0; K < CFG_MEM_IF_DQS_WIDTH; K = K + 1)
begin : C
assign afi_dqs_burst[K + CFG_MEM_IF_DQS_WIDTH] = (cfg_output_regd_for_afi_output == 1) ? int_dqs_burst_r : int_dqs_burst ;
assign afi_dqs_burst[K ] = (cfg_output_regd_for_afi_output == 1) ? int_dqs_burst_half_rate_r : int_dqs_burst_half_rate;
end
end
else if (CFG_DWIDTH_RATIO == 8) // quarterrate
begin
for (K = 0; K < CFG_MEM_IF_DQS_WIDTH; K = K + 1)
begin : C
assign afi_dqs_burst[K + CFG_MEM_IF_DQS_WIDTH * 3] = (cfg_output_regd_for_afi_output == 1) ? int_dqs_burst_r : int_dqs_burst ;
assign afi_dqs_burst[K + CFG_MEM_IF_DQS_WIDTH * 2] = (cfg_output_regd_for_afi_output == 1) ? int_dqs_burst_half_rate_r : int_dqs_burst_half_rate;
assign afi_dqs_burst[K + CFG_MEM_IF_DQS_WIDTH * 1] = (cfg_output_regd_for_afi_output == 1) ? int_dqs_burst_half_rate_r : int_dqs_burst_half_rate;
assign afi_dqs_burst[K ] = (cfg_output_regd_for_afi_output == 1) ? int_dqs_burst_half_rate_r : int_dqs_burst_half_rate;
end
end
endgenerate
//*************************************************************************************************//
// afi_wdata_valid generation logic //
//*************************************************************************************************//
always @(*)
begin
if (smallest_afi_wlat_eq_0)
begin
if (doing_write_pipe[0])
begin
int_wdata_valid = 1'b1;
end
else
begin
int_wdata_valid = 1'b0;
end
end
else
begin
if (smallest_doing_write_pipe_eq_afi_wlat_minus_0)
begin
int_wdata_valid = 1'b1;
end
else
begin
int_wdata_valid = 1'b0;
end
end
end
// registered output
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_wdata_valid_r <= 1'b0;
end
else
begin
int_wdata_valid_r <= int_wdata_valid;
end
end
generate
genvar L;
for (L = 0; L < CFG_MEM_IF_DQS_WIDTH*(CFG_DWIDTH_RATIO/2); L = L + 1)
begin : D
assign afi_wdata_valid[L] = (cfg_output_regd_for_afi_output) ? int_wdata_valid_r : int_wdata_valid;
end
endgenerate
//*************************************************************************************************//
// afi_wdata generation logic //
//*************************************************************************************************//
generate
genvar M;
for (M = 0;M < CFG_DRAM_WLAT_GROUP;M = M + 1) // generate wlat logic for each DQS group
begin : wlat_logic_per_dqs_group
//*************************************************************************************************//
// ecc_wdata_fifo_read //
//*************************************************************************************************//
// Indicate when to read from write data buffer
// based on burst_gen signals
always @(*)
begin
if (afi_wlat_eq_0 [M])
begin
if (bg_rdwr_data_valid && bg_doing_write)
begin
int_ecc_wdata_fifo_read [M] = 1'b1;
end
else
begin
int_ecc_wdata_fifo_read [M] = 1'b0;
end
end
else
begin
if (rdwr_data_valid_pipe_eq_afi_wlat_minus_x [M] && doing_write_pipe_eq_afi_wlat_minus_x [M])
begin
int_ecc_wdata_fifo_read [M] = 1'b1;
end
else
begin
int_ecc_wdata_fifo_read [M] = 1'b0;
end
end
end
// Registered output
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_ecc_wdata_fifo_read_r [M] <= 1'b0;
end
else
begin
int_ecc_wdata_fifo_read_r [M] <= int_ecc_wdata_fifo_read [M];
end
end
// Determine write data buffer read signal based on output_regd info
// output_regd info is derived based on afi_wlat value
assign ecc_wdata_fifo_read [M] = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_read_r [M] : int_ecc_wdata_fifo_read [M];
// Registered output
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
ecc_wdata_fifo_read_r [M] <= 1'b0;
end
else
begin
ecc_wdata_fifo_read_r [M] <= ecc_wdata_fifo_read [M];
end
end
//*************************************************************************************************//
// ecc_wdata_fifo_dataid/dataid_vector //
//*************************************************************************************************//
// Dataid generation to write buffer, to indicate which wdata should be passed to AFI
always @(*)
begin
if (afi_wlat_eq_0 [M])
begin
if (bg_rdwr_data_valid && bg_doing_write)
begin
int_ecc_wdata_fifo_dataid [M] = dataid;
int_ecc_wdata_fifo_dataid_vector [M] = dataid_vector;
end
else
begin
int_ecc_wdata_fifo_dataid [M] = {(CFG_DATA_ID_WIDTH){1'b0}};
int_ecc_wdata_fifo_dataid_vector [M] = {(CFG_DATAID_ARRAY_DEPTH){1'b0}};
end
end
else
begin
if (rdwr_data_valid_pipe_eq_afi_wlat_minus_x [M] && doing_write_pipe_eq_afi_wlat_minus_x [M])
begin
int_ecc_wdata_fifo_dataid [M] = dataid_pipe_eq_afi_wlat_minus_x [M];
int_ecc_wdata_fifo_dataid_vector [M] = dataid_vector_pipe_eq_afi_wlat_minus_x [M];
end
else
begin
int_ecc_wdata_fifo_dataid [M] = {(CFG_DATA_ID_WIDTH){1'b0}};
int_ecc_wdata_fifo_dataid_vector [M] = {(CFG_DATAID_ARRAY_DEPTH){1'b0}};
end
end
end
// Registered output
always @ (posedge ctl_clk, negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_ecc_wdata_fifo_dataid_r [M] <= 0;
int_ecc_wdata_fifo_dataid_vector_r [M] <= 0;
end
else
begin
int_ecc_wdata_fifo_dataid_r [M] <= int_ecc_wdata_fifo_dataid [M];
int_ecc_wdata_fifo_dataid_vector_r [M] <= int_ecc_wdata_fifo_dataid_vector [M];
end
end
assign ecc_wdata_fifo_dataid [(M + 1) * CFG_DATA_ID_WIDTH - 1 : M * CFG_DATA_ID_WIDTH ] = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_dataid_r [M] : int_ecc_wdata_fifo_dataid [M];
assign ecc_wdata_fifo_dataid_vector [(M + 1) * CFG_DATAID_ARRAY_DEPTH - 1 : M * CFG_DATAID_ARRAY_DEPTH] = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_dataid_vector_r [M] : int_ecc_wdata_fifo_dataid_vector [M];
//*************************************************************************************************//
// ecc_wdata_fifo_rmw_correct/partial //
//*************************************************************************************************//
// Read modify write info logic
always @(*)
begin
if (afi_wlat_eq_0 [M])
begin
if (bg_rdwr_data_valid && bg_doing_write)
begin
int_ecc_wdata_fifo_rmw_correct [M] = int_do_rmw_correct;
int_ecc_wdata_fifo_rmw_partial [M] = int_do_rmw_partial;
end
else
begin
int_ecc_wdata_fifo_rmw_correct [M] = 1'b0;
int_ecc_wdata_fifo_rmw_partial [M] = 1'b0;
end
end
else
begin
if (rdwr_data_valid_pipe_eq_afi_wlat_minus_x [M] && doing_write_pipe_eq_afi_wlat_minus_x [M])
begin
int_ecc_wdata_fifo_rmw_correct [M] = rmw_correct_pipe_eq_afi_wlat_minus_x [M];
int_ecc_wdata_fifo_rmw_partial [M] = rmw_partial_pipe_eq_afi_wlat_minus_x [M];
end
else
begin
int_ecc_wdata_fifo_rmw_correct [M] = 1'b0;
int_ecc_wdata_fifo_rmw_partial [M] = 1'b0;
end
end
end
always @ (posedge ctl_clk, negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_ecc_wdata_fifo_rmw_correct_r [M] <= 0;
int_ecc_wdata_fifo_rmw_partial_r [M] <= 0;
end
else
begin
int_ecc_wdata_fifo_rmw_correct_r [M] <= int_ecc_wdata_fifo_rmw_correct [M];
int_ecc_wdata_fifo_rmw_partial_r [M] <= int_ecc_wdata_fifo_rmw_partial [M];
end
end
assign ecc_wdata_fifo_rmw_correct [M] = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_rmw_correct_r [M] : int_ecc_wdata_fifo_rmw_correct [M];
assign ecc_wdata_fifo_rmw_partial [M] = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_rmw_partial_r [M] : int_ecc_wdata_fifo_rmw_partial [M];
end
endgenerate
generate
if (CFG_DRAM_WLAT_GROUP == 1) // only one group of afi_wlat
begin
assign ecc_wdata_fifo_read_first = ecc_wdata_fifo_read;
assign ecc_wdata_fifo_dataid_first = ecc_wdata_fifo_dataid;
assign ecc_wdata_fifo_dataid_vector_first = ecc_wdata_fifo_dataid_vector;
assign ecc_wdata_fifo_rmw_correct_first = ecc_wdata_fifo_rmw_correct;
assign ecc_wdata_fifo_rmw_partial_first = ecc_wdata_fifo_rmw_partial;
assign ecc_wdata_fifo_read_last = ecc_wdata_fifo_read;
assign ecc_wdata_fifo_dataid_last = ecc_wdata_fifo_dataid;
assign ecc_wdata_fifo_dataid_vector_last = ecc_wdata_fifo_dataid_vector;
assign ecc_wdata_fifo_rmw_correct_last = ecc_wdata_fifo_rmw_correct;
assign ecc_wdata_fifo_rmw_partial_last = ecc_wdata_fifo_rmw_partial;
end
else
begin
reg ecc_wdata_fifo_read_first_r;
reg int_ecc_wdata_fifo_read_first;
reg int_ecc_wdata_fifo_read_first_r;
reg [CFG_DATA_ID_WIDTH-1:0] int_ecc_wdata_fifo_dataid_first;
reg [CFG_DATA_ID_WIDTH-1:0] int_ecc_wdata_fifo_dataid_first_r;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] int_ecc_wdata_fifo_dataid_vector_first;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] int_ecc_wdata_fifo_dataid_vector_first_r;
reg int_ecc_wdata_fifo_rmw_correct_first;
reg int_ecc_wdata_fifo_rmw_correct_first_r;
reg int_ecc_wdata_fifo_rmw_partial_first;
reg int_ecc_wdata_fifo_rmw_partial_first_r;
reg ecc_wdata_fifo_read_last_r;
reg int_ecc_wdata_fifo_read_last;
reg int_ecc_wdata_fifo_read_last_r;
reg [CFG_DATA_ID_WIDTH-1:0] int_ecc_wdata_fifo_dataid_last;
reg [CFG_DATA_ID_WIDTH-1:0] int_ecc_wdata_fifo_dataid_last_r;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] int_ecc_wdata_fifo_dataid_vector_last;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] int_ecc_wdata_fifo_dataid_vector_last_r;
reg int_ecc_wdata_fifo_rmw_correct_last;
reg int_ecc_wdata_fifo_rmw_correct_last_r;
reg int_ecc_wdata_fifo_rmw_partial_last;
reg int_ecc_wdata_fifo_rmw_partial_last_r;
// Determine first ecc_wdata_fifo_* info
//*************************************************************************************************//
// ecc_wdata_fifo_read //
//*************************************************************************************************//
// Indicate when to read from write data buffer
// based on burst_gen signals
always @(*)
begin
if (smallest_afi_wlat_eq_0)
begin
if (bg_rdwr_data_valid && bg_doing_write)
begin
int_ecc_wdata_fifo_read_first = 1'b1;
end
else
begin
int_ecc_wdata_fifo_read_first = 1'b0;
end
end
else
begin
if (smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x && smallest_doing_write_pipe_eq_afi_wlat_minus_x)
begin
int_ecc_wdata_fifo_read_first = 1'b1;
end
else
begin
int_ecc_wdata_fifo_read_first = 1'b0;
end
end
end
// Registered output
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_ecc_wdata_fifo_read_first_r <= 1'b0;
end
else
begin
int_ecc_wdata_fifo_read_first_r <= int_ecc_wdata_fifo_read_first;
end
end
// Determine write data buffer read signal based on output_regd info
// output_regd info is derived based on afi_wlat value
assign ecc_wdata_fifo_read_first = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_read_first_r : int_ecc_wdata_fifo_read_first;
// Registered output
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
ecc_wdata_fifo_read_first_r <= 1'b0;
end
else
begin
ecc_wdata_fifo_read_first_r <= ecc_wdata_fifo_read_first;
end
end
//*************************************************************************************************//
// ecc_wdata_fifo_dataid/dataid_vector //
//*************************************************************************************************//
// Dataid generation to write buffer, to indicate which wdata should be passed to AFI
always @(*)
begin
if (smallest_afi_wlat_eq_0)
begin
if (bg_rdwr_data_valid && bg_doing_write)
begin
int_ecc_wdata_fifo_dataid_first = dataid;
int_ecc_wdata_fifo_dataid_vector_first = dataid_vector;
end
else
begin
int_ecc_wdata_fifo_dataid_first = {(CFG_DATA_ID_WIDTH){1'b0}};
int_ecc_wdata_fifo_dataid_vector_first = {(CFG_DATAID_ARRAY_DEPTH){1'b0}};
end
end
else
begin
if (smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x && smallest_doing_write_pipe_eq_afi_wlat_minus_x)
begin
int_ecc_wdata_fifo_dataid_first = smallest_dataid_pipe_eq_afi_wlat_minus_x ;
int_ecc_wdata_fifo_dataid_vector_first = smallest_dataid_vector_pipe_eq_afi_wlat_minus_x;
end
else
begin
int_ecc_wdata_fifo_dataid_first = {(CFG_DATA_ID_WIDTH){1'b0}};
int_ecc_wdata_fifo_dataid_vector_first = {(CFG_DATAID_ARRAY_DEPTH){1'b0}};
end
end
end
// Registered output
always @ (posedge ctl_clk, negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_ecc_wdata_fifo_dataid_first_r <= 0;
int_ecc_wdata_fifo_dataid_vector_first_r <= 0;
end
else
begin
int_ecc_wdata_fifo_dataid_first_r <= int_ecc_wdata_fifo_dataid_first ;
int_ecc_wdata_fifo_dataid_vector_first_r <= int_ecc_wdata_fifo_dataid_vector_first;
end
end
assign ecc_wdata_fifo_dataid_first = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_dataid_first_r : int_ecc_wdata_fifo_dataid_first ;
assign ecc_wdata_fifo_dataid_vector_first = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_dataid_vector_first_r : int_ecc_wdata_fifo_dataid_vector_first;
//*************************************************************************************************//
// ecc_wdata_fifo_rmw_correct/partial //
//*************************************************************************************************//
// Read modify write info logic
always @(*)
begin
if (smallest_afi_wlat_eq_0)
begin
if (bg_rdwr_data_valid && bg_doing_write)
begin
int_ecc_wdata_fifo_rmw_correct_first = int_do_rmw_correct;
int_ecc_wdata_fifo_rmw_partial_first = int_do_rmw_partial;
end
else
begin
int_ecc_wdata_fifo_rmw_correct_first = 1'b0;
int_ecc_wdata_fifo_rmw_partial_first = 1'b0;
end
end
else
begin
if (smallest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x && smallest_doing_write_pipe_eq_afi_wlat_minus_x)
begin
int_ecc_wdata_fifo_rmw_correct_first = smallest_rmw_correct_pipe_eq_afi_wlat_minus_x;
int_ecc_wdata_fifo_rmw_partial_first = smallest_rmw_partial_pipe_eq_afi_wlat_minus_x;
end
else
begin
int_ecc_wdata_fifo_rmw_correct_first = 1'b0;
int_ecc_wdata_fifo_rmw_partial_first = 1'b0;
end
end
end
always @ (posedge ctl_clk, negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_ecc_wdata_fifo_rmw_correct_first_r <= 0;
int_ecc_wdata_fifo_rmw_partial_first_r <= 0;
end
else
begin
int_ecc_wdata_fifo_rmw_correct_first_r <= int_ecc_wdata_fifo_rmw_correct_first;
int_ecc_wdata_fifo_rmw_partial_first_r <= int_ecc_wdata_fifo_rmw_partial_first;
end
end
assign ecc_wdata_fifo_rmw_correct_first = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_rmw_correct_first_r : int_ecc_wdata_fifo_rmw_correct_first;
assign ecc_wdata_fifo_rmw_partial_first = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_rmw_partial_first_r : int_ecc_wdata_fifo_rmw_partial_first;
// Determine last ecc_wdata_fifo_* info
//*************************************************************************************************//
// ecc_wdata_fifo_read //
//*************************************************************************************************//
// Indicate when to read from write data buffer
// based on burst_gen signals
always @(*)
begin
if (largest_afi_wlat_eq_0)
begin
if (bg_rdwr_data_valid && bg_doing_write)
begin
int_ecc_wdata_fifo_read_last = 1'b1;
end
else
begin
int_ecc_wdata_fifo_read_last = 1'b0;
end
end
else
begin
if (largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x && largest_doing_write_pipe_eq_afi_wlat_minus_x)
begin
int_ecc_wdata_fifo_read_last = 1'b1;
end
else
begin
int_ecc_wdata_fifo_read_last = 1'b0;
end
end
end
// Registered output
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_ecc_wdata_fifo_read_last_r <= 1'b0;
end
else
begin
int_ecc_wdata_fifo_read_last_r <= int_ecc_wdata_fifo_read_last;
end
end
// Determine write data buffer read signal based on output_regd info
// output_regd info is derived based on afi_wlat value
assign ecc_wdata_fifo_read_last = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_read_last_r : int_ecc_wdata_fifo_read_last;
// Registered output
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
ecc_wdata_fifo_read_last_r <= 1'b0;
end
else
begin
ecc_wdata_fifo_read_last_r <= ecc_wdata_fifo_read_last;
end
end
//*************************************************************************************************//
// ecc_wdata_fifo_dataid/dataid_vector //
//*************************************************************************************************//
// Dataid generation to write buffer, to indicate which wdata should be passed to AFI
always @(*)
begin
if (largest_afi_wlat_eq_0)
begin
if (bg_rdwr_data_valid && bg_doing_write)
begin
int_ecc_wdata_fifo_dataid_last = dataid;
int_ecc_wdata_fifo_dataid_vector_last = dataid_vector;
end
else
begin
int_ecc_wdata_fifo_dataid_last = {(CFG_DATA_ID_WIDTH){1'b0}};
int_ecc_wdata_fifo_dataid_vector_last = {(CFG_DATAID_ARRAY_DEPTH){1'b0}};
end
end
else
begin
if (largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x && largest_doing_write_pipe_eq_afi_wlat_minus_x)
begin
int_ecc_wdata_fifo_dataid_last = largest_dataid_pipe_eq_afi_wlat_minus_x ;
int_ecc_wdata_fifo_dataid_vector_last = largest_dataid_vector_pipe_eq_afi_wlat_minus_x;
end
else
begin
int_ecc_wdata_fifo_dataid_last = {(CFG_DATA_ID_WIDTH){1'b0}};
int_ecc_wdata_fifo_dataid_vector_last = {(CFG_DATAID_ARRAY_DEPTH){1'b0}};
end
end
end
// Registered output
always @ (posedge ctl_clk, negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_ecc_wdata_fifo_dataid_last_r <= 0;
int_ecc_wdata_fifo_dataid_vector_last_r <= 0;
end
else
begin
int_ecc_wdata_fifo_dataid_last_r <= int_ecc_wdata_fifo_dataid_last ;
int_ecc_wdata_fifo_dataid_vector_last_r <= int_ecc_wdata_fifo_dataid_vector_last;
end
end
assign ecc_wdata_fifo_dataid_last = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_dataid_last_r : int_ecc_wdata_fifo_dataid_last ;
assign ecc_wdata_fifo_dataid_vector_last = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_dataid_vector_last_r : int_ecc_wdata_fifo_dataid_vector_last;
//*************************************************************************************************//
// ecc_wdata_fifo_rmw_correct/partial //
//*************************************************************************************************//
// Read modify write info logic
always @(*)
begin
if (largest_afi_wlat_eq_0)
begin
if (bg_rdwr_data_valid && bg_doing_write)
begin
int_ecc_wdata_fifo_rmw_correct_last = int_do_rmw_correct;
int_ecc_wdata_fifo_rmw_partial_last = int_do_rmw_partial;
end
else
begin
int_ecc_wdata_fifo_rmw_correct_last = 1'b0;
int_ecc_wdata_fifo_rmw_partial_last = 1'b0;
end
end
else
begin
if (largest_rdwr_data_valid_pipe_eq_afi_wlat_minus_x && largest_doing_write_pipe_eq_afi_wlat_minus_x)
begin
int_ecc_wdata_fifo_rmw_correct_last = largest_rmw_correct_pipe_eq_afi_wlat_minus_x;
int_ecc_wdata_fifo_rmw_partial_last = largest_rmw_partial_pipe_eq_afi_wlat_minus_x;
end
else
begin
int_ecc_wdata_fifo_rmw_correct_last = 1'b0;
int_ecc_wdata_fifo_rmw_partial_last = 1'b0;
end
end
end
always @ (posedge ctl_clk, negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_ecc_wdata_fifo_rmw_correct_last_r <= 0;
int_ecc_wdata_fifo_rmw_partial_last_r <= 0;
end
else
begin
int_ecc_wdata_fifo_rmw_correct_last_r <= int_ecc_wdata_fifo_rmw_correct_last;
int_ecc_wdata_fifo_rmw_partial_last_r <= int_ecc_wdata_fifo_rmw_partial_last;
end
end
assign ecc_wdata_fifo_rmw_correct_last = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_rmw_correct_last_r : int_ecc_wdata_fifo_rmw_correct_last;
assign ecc_wdata_fifo_rmw_partial_last = (cfg_output_regd_for_wdata_path) ? int_ecc_wdata_fifo_rmw_partial_last_r : int_ecc_wdata_fifo_rmw_partial_last;
end
endgenerate
// No data manipulation on wdata
assign afi_wdata = ecc_wdata;
//*************************************************************************************************//
// afi_dm generation logic //
//*************************************************************************************************//
//Why do we need ecc_dm and rdwr_data_valid to determine DM
// ecc_dm will not get updated till we read another data from wrfifo, so we need to drive DMs based on rdwr_data_valid
//Output registered information already backed in ecc_wdata_fifo_read
// data valid one clock cycle after read
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_real_wdata_valid <= 1'b0;
end
else
begin
if (CFG_WDATA_REG || CFG_ECC_ENC_REG)
begin
int_real_wdata_valid <= ecc_wdata_fifo_read_r;
end
else
begin
int_real_wdata_valid <= ecc_wdata_fifo_read;
end
end
end
generate
genvar J;
for (J = 0; J < CFG_MEM_IF_DM_WIDTH*CFG_DWIDTH_RATIO; J = J + 1)
begin : F
assign afi_dm[J] = ~ecc_dm[J] | ~int_real_wdata_valid;
end
endgenerate
endmodule
|
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: nto1_mux.v
//
// Description: N:1 MUX based on either binary-encoded or one-hot select input
// One-hot mode does not protect against multiple active SEL_ONEHOT inputs.
// Note: All port signals changed to all-upper-case (w.r.t. prior version).
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_nto1_mux #
(
parameter integer C_RATIO = 1, // Range: >=1
parameter integer C_SEL_WIDTH = 1, // Range: >=1; recommended: ceil_log2(C_RATIO)
parameter integer C_DATAOUT_WIDTH = 1, // Range: >=1
parameter integer C_ONEHOT = 0 // Values: 0 = binary-encoded (use SEL); 1 = one-hot (use SEL_ONEHOT)
)
(
input wire [C_RATIO-1:0] SEL_ONEHOT, // One-hot generic_baseblocks_v2_1_0_mux select (only used if C_ONEHOT=1)
input wire [C_SEL_WIDTH-1:0] SEL, // Binary-encoded generic_baseblocks_v2_1_0_mux select (only used if C_ONEHOT=0)
input wire [C_RATIO*C_DATAOUT_WIDTH-1:0] IN, // Data input array (num_selections x data_width)
output wire [C_DATAOUT_WIDTH-1:0] OUT // Data output vector
);
wire [C_DATAOUT_WIDTH*C_RATIO-1:0] carry;
genvar i;
generate
if (C_ONEHOT == 0) begin : gen_encoded
assign carry[C_DATAOUT_WIDTH-1:0] = {C_DATAOUT_WIDTH{(SEL==0)?1'b1:1'b0}} & IN[C_DATAOUT_WIDTH-1:0];
for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_enc
assign carry[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH] =
carry[i*C_DATAOUT_WIDTH-1:(i-1)*C_DATAOUT_WIDTH] |
{C_DATAOUT_WIDTH{(SEL==i)?1'b1:1'b0}} & IN[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH];
end
end else begin : gen_onehot
assign carry[C_DATAOUT_WIDTH-1:0] = {C_DATAOUT_WIDTH{SEL_ONEHOT[0]}} & IN[C_DATAOUT_WIDTH-1:0];
for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_hot
assign carry[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH] =
carry[i*C_DATAOUT_WIDTH-1:(i-1)*C_DATAOUT_WIDTH] |
{C_DATAOUT_WIDTH{SEL_ONEHOT[i]}} & IN[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH];
end
end
endgenerate
assign OUT = carry[C_DATAOUT_WIDTH*C_RATIO-1:
C_DATAOUT_WIDTH*(C_RATIO-1)];
endmodule
`default_nettype wire
|
// Beck Pang
// University of Washington, Seattle
// Apr. 6th, 2015
// EE 471, Lab 1
`include "DFlipFlop.v"
`include "JohnsonCounter.v"
// test bench running on gtkwave
module JohnsonCounter_testBench ();
// connext the two modules
wire clk, rst_n;
wire [3:0] out;
// declare an instance of the AND module
JohnsonCounter myCounter (clk, rst_n, out);
// Running the GUI part of simulation
JohnsonCounter_Tester aTester (clk, rst_n, out);
// file for gtkwave
initial
begin
$dumpfile("JohnsonCounter.vcd");
$dumpvars(1, myCounter);
end
endmodule
module JohnsonCounter_Tester (
output reg clk, rst_n,
input [3:0] out
);
parameter stimDelay = 20;
// generate a clock
always #(stimDelay/2) clk = ~clk;
initial // Response
begin
$display("\t\t clk rst_n \t out \t Time ");
$monitor("\t %b ", out, $time);
clk = 'b0;
end
always @(posedge clk) // Stimulus
begin
rst_n = 'b0;
#stimDelay rst_n = 'b1;
#(32*stimDelay) rst_n = 'b0;
#stimDelay clk = 'b1;
#(32*stimDelay) clk = 'b0;
#stimDelay clk = 'b1;
#(2*stimDelay);
$stop;
$finish;
end
endmodule |
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2015 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
Require Import Morphisms BinInt ZDivEucl.
Local Open Scope Z_scope.
(** * Definitions of division for binary integers, Euclid convention. *)
(** In this convention, the remainder is always positive.
For other conventions, see [Z.div] and [Z.quot] in file [BinIntDef].
To avoid collision with the other divisions, we place this one
under a module.
*)
Module ZEuclid.
Definition modulo a b := Z.modulo a (Z.abs b).
Definition div a b := (Z.sgn b) * (Z.div a (Z.abs b)).
Instance mod_wd : Proper (eq==>eq==>eq) modulo.
Proof. congruence. Qed.
Instance div_wd : Proper (eq==>eq==>eq) div.
Proof. congruence. Qed.
Theorem div_mod a b : b<>0 -> a = b*(div a b) + modulo a b.
Proof.
intros Hb. unfold div, modulo.
rewrite Z.mul_assoc. rewrite Z.sgn_abs. apply Z.div_mod.
now destruct b.
Qed.
Lemma mod_always_pos a b : b<>0 -> 0 <= modulo a b < Z.abs b.
Proof.
intros Hb. unfold modulo.
apply Z.mod_pos_bound.
destruct b; compute; trivial. now destruct Hb.
Qed.
Lemma mod_bound_pos a b : 0<=a -> 0<b -> 0 <= modulo a b < b.
Proof.
intros _ Hb. rewrite <- (Z.abs_eq b) at 3 by Z.order.
apply mod_always_pos. Z.order.
Qed.
Include ZEuclidProp Z Z Z.
End ZEuclid.
|
/*
* Copyright 2012, Homer Hsing <[email protected]>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
module tiny(clk, reset, sel, addr, w, data, out, done);
input clk, reset;
input sel;
input [5:0] addr;
input w;
input [197:0] data;
output [197:0] out;
output done;
/* for FSM */
wire [5:0] fsm_addr;
/* for RAM */
wire [5:0] ram_a_addr, ram_b_addr;
wire [197:0] ram_b_data_in;
wire ram_a_w, ram_b_w;
wire [197:0] ram_a_data_out, ram_b_data_out;
/* for const */
wire [197:0] const0_out, const1_out;
wire const0_effective, const1_effective;
/* for muxer */
wire [197:0] muxer0_out, muxer1_out;
/* for ROM */
wire [8:0] rom_addr;
wire [25:0] rom_q;
/* for PE */
wire [10:0] pe_ctrl;
assign out = ram_a_data_out;
select
select0 (sel, addr, fsm_addr, w, ram_a_addr, ram_a_w);
rom
rom0 (clk, rom_addr, rom_q);
FSM
fsm0 (clk, reset, rom_addr, rom_q, fsm_addr, ram_b_addr, ram_b_w, pe_ctrl, done);
const
const0 (clk, ram_a_addr, const0_out, const0_effective),
const1 (clk, ram_b_addr, const1_out, const1_effective);
ram
ram0 (clk, ram_a_w, ram_a_addr, data, ram_a_data_out, ram_b_w, ram_b_addr[5:0], ram_b_data_in, ram_b_data_out);
muxer
muxer0 (ram_a_data_out, const0_out, const0_effective, muxer0_out),
muxer1 (ram_b_data_out, const1_out, const1_effective, muxer1_out);
PE
pe0 (clk, reset, pe_ctrl, muxer1_out, muxer0_out[193:0], muxer0_out[193:0], ram_b_data_in[193:0]);
assign ram_b_data_in[197:194] = 0;
endmodule
module select(sel, addr_in, addr_fsm_in, w_in, addr_out, w_out);
input sel;
input [5:0] addr_in;
input [5:0] addr_fsm_in;
input w_in;
output [5:0] addr_out;
output w_out;
assign addr_out = sel ? addr_in : addr_fsm_in;
assign w_out = sel & w_in;
endmodule
module muxer(from_ram, from_const, const_effective, out);
input [197:0] from_ram, from_const;
input const_effective;
output [197:0] out;
assign out = const_effective ? from_const : from_ram;
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge ([email protected])
// t_sqrt_pipelined.v
// Created: 4.2.2012
// Modified: 4.5.2012
//
// Testbench for generic sqrt operation
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module t_sqrt_pipelined();
parameter
INPUT_BITS = 4;
localparam
OUTPUT_BITS = INPUT_BITS / 2 + INPUT_BITS % 2;
reg [INPUT_BITS-1:0] radicand;
reg clk, start, reset_n;
wire [OUTPUT_BITS-1:0] root;
wire data_valid;
// wire [7:0] root_good;
sqrt_pipelined
#(
.INPUT_BITS(INPUT_BITS)
)
sqrt_pipelined
(
.clk(clk),
.reset_n(reset_n),
.start(start),
.radicand(radicand),
.data_valid(data_valid),
.root(root)
);
initial begin
radicand = 16'bx; clk = 1'bx; start = 1'bx; reset_n = 1'bx;;
#10 reset_n = 0; clk = 0;
#50 reset_n = 1; radicand = 0;
// #40 radicand = 81; start = 1;
// #10 radicand = 16'bx; start = 0;
#10000 $finish;
end
always
#5 clk = ~clk;
always begin
#10 radicand = radicand + 1; start = 1;
#10 start = 0;
end
// always begin
// #80 start = 1;
// #10 start = 0;
// end
endmodule
|
(** * Poly: Polymorphism and Higher-Order Functions *)
(** In this chapter we continue our development of basic
concepts of functional programming. The critical new ideas are
_polymorphism_ (abstracting functions over the types of the data
they manipulate) and _higher-order functions_ (treating functions
as data).
*)
Require Export Lists.
(* ###################################################### *)
(** * Polymorphism *)
(* ###################################################### *)
(** ** Polymorphic Lists *)
(** For the last couple of chapters, we've been working just
with lists of numbers. Obviously, interesting programs also need
to be able to manipulate lists with elements from other types --
lists of strings, lists of booleans, lists of lists, etc. We
_could_ just define a new inductive datatype for each of these,
for example... *)
Inductive boollist : Type :=
| bool_nil : boollist
| bool_cons : bool -> boollist -> boollist.
(** ... but this would quickly become tedious, partly because we
have to make up different constructor names for each datatype, but
mostly because we would also need to define new versions of all
our list manipulating functions ([length], [rev], etc.) for each
new datatype definition. *)
(** *** *)
(** To avoid all this repetition, Coq supports _polymorphic_
inductive type definitions. For example, here is a _polymorphic
list_ datatype. *)
Inductive list (X:Type) : Type :=
| nil : list X
| cons : X -> list X -> list X.
(** This is exactly like the definition of [natlist] from the
previous chapter, except that the [nat] argument to the [cons]
constructor has been replaced by an arbitrary type [X], a binding
for [X] has been added to the header, and the occurrences of
[natlist] in the types of the constructors have been replaced by
[list X]. (We can re-use the constructor names [nil] and [cons]
because the earlier definition of [natlist] was inside of a
[Module] definition that is now out of scope.) *)
(** What sort of thing is [list] itself? One good way to think
about it is that [list] is a _function_ from [Type]s to
[Inductive] definitions; or, to put it another way, [list] is a
function from [Type]s to [Type]s. For any particular type [X],
the type [list X] is an [Inductive]ly defined set of lists whose
elements are things of type [X]. *)
(** With this definition, when we use the constructors [nil] and
[cons] to build lists, we need to tell Coq the type of the
elements in the lists we are building -- that is, [nil] and [cons]
are now _polymorphic constructors_. Observe the types of these
constructors: *)
Check nil.
(* ===> nil : forall X : Type, list X *)
Check cons.
(* ===> cons : forall X : Type, X -> list X -> list X *)
(** The "[forall X]" in these types can be read as an additional
argument to the constructors that determines the expected types of
the arguments that follow. When [nil] and [cons] are used, these
arguments are supplied in the same way as the others. For
example, the list containing [2] and [1] is written like this: *)
Check (cons nat 2 (cons nat 1 (nil nat))).
(** (We've gone back to writing [nil] and [cons] explicitly here
because we haven't yet defined the [ [] ] and [::] notations for
the new version of lists. We'll do that in a bit.) *)
(** We can now go back and make polymorphic (or "generic")
versions of all the list-processing functions that we wrote
before. Here is [length], for example: *)
(** *** *)
Fixpoint length (X:Type) (l:list X) : nat :=
match l with
| nil => 0
| cons h t => S (length X t)
end.
(** Note that the uses of [nil] and [cons] in [match] patterns
do not require any type annotations: Coq already knows that the list
[l] contains elements of type [X], so there's no reason to include
[X] in the pattern. (More precisely, the type [X] is a parameter
of the whole definition of [list], not of the individual
constructors. We'll come back to this point later.)
As with [nil] and [cons], we can use [length] by applying it first
to a type and then to its list argument: *)
Example test_length1 :
length nat (cons nat 1 (cons nat 2 (nil nat))) = 2.
Proof. reflexivity. Qed.
(** To use our length with other kinds of lists, we simply
instantiate it with an appropriate type parameter: *)
Example test_length2 :
length bool (cons bool true (nil bool)) = 1.
Proof. reflexivity. Qed.
(** *** *)
(** Let's close this subsection by re-implementing a few other
standard list functions on our new polymorphic lists: *)
Fixpoint app (X : Type) (l1 l2 : list X)
: (list X) :=
match l1 with
| nil => l2
| cons h t => cons X h (app X t l2)
end.
Fixpoint snoc (X:Type) (l:list X) (v:X) : (list X) :=
match l with
| nil => cons X v (nil X)
| cons h t => cons X h (snoc X t v)
end.
Fixpoint rev (X:Type) (l:list X) : list X :=
match l with
| nil => nil X
| cons h t => snoc X (rev X t) h
end.
Example test_rev1 :
rev nat (cons nat 1 (cons nat 2 (nil nat)))
= (cons nat 2 (cons nat 1 (nil nat))).
Proof. reflexivity. Qed.
Example test_rev2:
rev bool (nil bool) = nil bool.
Proof. reflexivity. Qed.
Module MumbleBaz.
(** **** Exercise: 2 stars (mumble_grumble) *)
(** Consider the following two inductively defined types. *)
Inductive mumble : Type :=
| a : mumble
| b : mumble -> nat -> mumble
| c : mumble.
Inductive grumble (X:Type) : Type :=
| d : mumble -> grumble X
| e : X -> grumble X.
(** Which of the following are well-typed elements of [grumble X] for
some type [X]?
- [d (b a 5)]
- [d mumble (b a 5)]
- [d bool (b a 5)]
- [e bool true]
- [e mumble (b c 0)]
- [e bool (b c 0)]
- [c]
(* FILL IN HERE *)
*)
(** [] *)
(** **** Exercise: 2 stars (baz_num_elts) *)
(** Consider the following inductive definition: *)
Inductive baz : Type :=
| x : baz -> baz
| y : baz -> bool -> baz.
(** How _many_ elements does the type [baz] have?
(* FILL IN HERE *)
*)
(** [] *)
End MumbleBaz.
(* ###################################################### *)
(** *** Type Annotation Inference *)
(** Let's write the definition of [app] again, but this time we won't
specify the types of any of the arguments. Will Coq still accept
it? *)
Fixpoint app' X l1 l2 : list X :=
match l1 with
| nil => l2
| cons h t => cons X h (app' X t l2)
end.
(** Indeed it will. Let's see what type Coq has assigned to [app']: *)
Check app'.
(* ===> forall X : Type, list X -> list X -> list X *)
Check app.
(* ===> forall X : Type, list X -> list X -> list X *)
(** It has exactly the same type type as [app]. Coq was able to
use a process called _type inference_ to deduce what the types of
[X], [l1], and [l2] must be, based on how they are used. For
example, since [X] is used as an argument to [cons], it must be a
[Type], since [cons] expects a [Type] as its first argument;
matching [l1] with [nil] and [cons] means it must be a [list]; and
so on.
This powerful facility means we don't always have to write
explicit type annotations everywhere, although explicit type
annotations are still quite useful as documentation and sanity
checks. You should try to find a balance in your own code between
too many type annotations (so many that they clutter and distract)
and too few (which forces readers to perform type inference in
their heads in order to understand your code). *)
(* ###################################################### *)
(** *** Type Argument Synthesis *)
(** Whenever we use a polymorphic function, we need to pass it
one or more types in addition to its other arguments. For
example, the recursive call in the body of the [length] function
above must pass along the type [X]. But just like providing
explicit type annotations everywhere, this is heavy and verbose.
Since the second argument to [length] is a list of [X]s, it seems
entirely obvious that the first argument can only be [X] -- why
should we have to write it explicitly?
Fortunately, Coq permits us to avoid this kind of redundancy. In
place of any type argument we can write the "implicit argument"
[_], which can be read as "Please figure out for yourself what
type belongs here." More precisely, when Coq encounters a [_], it
will attempt to _unify_ all locally available information -- the
type of the function being applied, the types of the other
arguments, and the type expected by the context in which the
application appears -- to determine what concrete type should
replace the [_].
This may sound similar to type annotation inference -- and,
indeed, the two procedures rely on the same underlying mechanisms.
Instead of simply omitting the types of some arguments to a
function, like
app' X l1 l2 : list X :=
we can also replace the types with [_], like
app' (X : _) (l1 l2 : _) : list X :=
which tells Coq to attempt to infer the missing information, just
as with argument synthesis.
Using implicit arguments, the [length] function can be written
like this: *)
Fixpoint length' (X:Type) (l:list X) : nat :=
match l with
| nil => 0
| cons h t => S (length' _ t)
end.
(** In this instance, we don't save much by writing [_] instead of
[X]. But in many cases the difference can be significant. For
example, suppose we want to write down a list containing the
numbers [1], [2], and [3]. Instead of writing this... *)
Definition list123 :=
cons nat 1 (cons nat 2 (cons nat 3 (nil nat))).
(** ...we can use argument synthesis to write this: *)
Definition list123' := cons _ 1 (cons _ 2 (cons _ 3 (nil _))).
(* ###################################################### *)
(** *** Implicit Arguments *)
(** In fact, we can go further. To avoid having to sprinkle [_]'s
throughout our programs, we can tell Coq _always_ to infer the
type argument(s) of a given function. The [Arguments] directive
specifies the name of the function or constructor, and then lists
its argument names, with curly braces around any arguments to be
treated as implicit.
*)
Arguments nil {X}.
Arguments cons {X} _ _. (* use underscore for argument position that has no name *)
Arguments length {X} l.
Arguments app {X} l1 l2.
Arguments rev {X} l.
Arguments snoc {X} l v.
(* note: no _ arguments required... *)
Definition list123'' := cons 1 (cons 2 (cons 3 nil)).
Check (length list123'').
(** *** *)
(** Alternatively, we can declare an argument to be implicit while
defining the function itself, by surrounding the argument in curly
braces. For example: *)
Fixpoint length'' {X:Type} (l:list X) : nat :=
match l with
| nil => 0
| cons h t => S (length'' t)
end.
(** (Note that we didn't even have to provide a type argument to
the recursive call to [length'']; indeed, it is invalid to provide
one.) We will use this style whenever possible, although we will
continue to use use explicit [Argument] declarations for
[Inductive] constructors. *)
(** *** *)
(** One small problem with declaring arguments [Implicit] is
that, occasionally, Coq does not have enough local information to
determine a type argument; in such cases, we need to tell Coq that
we want to give the argument explicitly this time, even though
we've globally declared it to be [Implicit]. For example, suppose we
write this: *)
(* Definition mynil := nil. *)
(** If we uncomment this definition, Coq will give us an error,
because it doesn't know what type argument to supply to [nil]. We
can help it by providing an explicit type declaration (so that Coq
has more information available when it gets to the "application"
of [nil]): *)
Definition mynil : list nat := nil.
(** Alternatively, we can force the implicit arguments to be explicit by
prefixing the function name with [@]. *)
Check @nil.
Definition mynil' := @nil nat.
(** *** *)
(** Using argument synthesis and implicit arguments, we can
define convenient notation for lists, as before. Since we have
made the constructor type arguments implicit, Coq will know to
automatically infer these when we use the notations. *)
Notation "x :: y" := (cons x y)
(at level 60, right associativity).
Notation "[ ]" := nil.
Notation "[ x ; .. ; y ]" := (cons x .. (cons y []) ..).
Notation "x ++ y" := (app x y)
(at level 60, right associativity).
(** Now lists can be written just the way we'd hope: *)
Definition list123''' := [1; 2; 3].
(* ###################################################### *)
(** *** Exercises: Polymorphic Lists *)
(** **** Exercise: 2 stars, optional (poly_exercises) *)
(** Here are a few simple exercises, just like ones in the [Lists]
chapter, for practice with polymorphism. Fill in the definitions
and complete the proofs below. *)
Fixpoint repeat {X : Type} (n : X) (count : nat) : list X :=
(* FILL IN HERE *) admit.
Example test_repeat1:
repeat true 2 = cons true (cons true nil).
(* FILL IN HERE *) Admitted.
Theorem nil_app : forall X:Type, forall l:list X,
app [] l = l.
Proof.
(* FILL IN HERE *) Admitted.
Theorem rev_snoc : forall X : Type,
forall v : X,
forall s : list X,
rev (snoc s v) = v :: (rev s).
Proof.
(* FILL IN HERE *) Admitted.
Theorem rev_involutive : forall X : Type, forall l : list X,
rev (rev l) = l.
Proof.
(* FILL IN HERE *) Admitted.
Theorem snoc_with_append : forall X : Type,
forall l1 l2 : list X,
forall v : X,
snoc (l1 ++ l2) v = l1 ++ (snoc l2 v).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################### *)
(** ** Polymorphic Pairs *)
(** Following the same pattern, the type definition we gave in
the last chapter for pairs of numbers can be generalized to
_polymorphic pairs_ (or _products_): *)
Inductive prod (X Y : Type) : Type :=
pair : X -> Y -> prod X Y.
Arguments pair {X} {Y} _ _.
(** As with lists, we make the type arguments implicit and define the
familiar concrete notation. *)
Notation "( x , y )" := (pair x y).
(** We can also use the [Notation] mechanism to define the standard
notation for pair _types_: *)
Notation "X * Y" := (prod X Y) : type_scope.
(** (The annotation [: type_scope] tells Coq that this abbreviation
should be used when parsing types. This avoids a clash with the
multiplication symbol.) *)
(** *** *)
(** A note of caution: it is easy at first to get [(x,y)] and
[X*Y] confused. Remember that [(x,y)] is a _value_ built from two
other values; [X*Y] is a _type_ built from two other types. If
[x] has type [X] and [y] has type [Y], then [(x,y)] has type
[X*Y]. *)
(** The first and second projection functions now look pretty
much as they would in any functional programming language. *)
Definition fst {X Y : Type} (p : X * Y) : X :=
match p with (x,y) => x end.
Definition snd {X Y : Type} (p : X * Y) : Y :=
match p with (x,y) => y end.
(** The following function takes two lists and combines them
into a list of pairs. In many functional programming languages,
it is called [zip]. We call it [combine] for consistency with
Coq's standard library. *)
(** Note that the pair notation can be used both in expressions and in
patterns... *)
Fixpoint combine {X Y : Type} (lx : list X) (ly : list Y)
: list (X*Y) :=
match (lx,ly) with
| ([],_) => []
| (_,[]) => []
| (x::tx, y::ty) => (x,y) :: (combine tx ty)
end.
(** **** Exercise: 1 star, optional (combine_checks) *)
(** Try answering the following questions on paper and
checking your answers in coq:
- What is the type of [combine] (i.e., what does [Check
@combine] print?)
- What does
Eval compute in (combine [1;2] [false;false;true;true]).
print? []
*)
(** **** Exercise: 2 stars (split) *)
(** The function [split] is the right inverse of combine: it takes a
list of pairs and returns a pair of lists. In many functional
programing languages, this function is called [unzip].
Uncomment the material below and fill in the definition of
[split]. Make sure it passes the given unit tests. *)
Fixpoint split
{X Y : Type} (l : list (X*Y))
: (list X) * (list Y) :=
(* FILL IN HERE *) admit.
Example test_split:
split [(1,false);(2,false)] = ([1;2],[false;false]).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################### *)
(** ** Polymorphic Options *)
(** One last polymorphic type for now: _polymorphic options_.
The type declaration generalizes the one for [natoption] in the
previous chapter: *)
Inductive option (X:Type) : Type :=
| Some : X -> option X
| None : option X.
Arguments Some {X} _.
Arguments None {X}.
(** *** *)
(** We can now rewrite the [index] function so that it works
with any type of lists. *)
Fixpoint index {X : Type} (n : nat)
(l : list X) : option X :=
match l with
| [] => None
| a :: l' => if beq_nat n O then Some a else index (pred n) l'
end.
Example test_index1 : index 0 [4;5;6;7] = Some 4.
Proof. reflexivity. Qed.
Example test_index2 : index 1 [[1];[2]] = Some [2].
Proof. reflexivity. Qed.
Example test_index3 : index 2 [true] = None.
Proof. reflexivity. Qed.
(** **** Exercise: 1 star, optional (hd_opt_poly) *)
(** Complete the definition of a polymorphic version of the
[hd_opt] function from the last chapter. Be sure that it
passes the unit tests below. *)
Definition hd_opt {X : Type} (l : list X) : option X :=
(* FILL IN HERE *) admit.
(** Once again, to force the implicit arguments to be explicit,
we can use [@] before the name of the function. *)
Check @hd_opt.
Example test_hd_opt1 : hd_opt [1;2] = Some 1.
(* FILL IN HERE *) Admitted.
Example test_hd_opt2 : hd_opt [[1];[2]] = Some [1].
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################### *)
(** * Functions as Data *)
(* ###################################################### *)
(** ** Higher-Order Functions *)
(** Like many other modern programming languages -- including
all _functional languages_ (ML, Haskell, Scheme, etc.) -- Coq
treats functions as first-class citizens, allowing functions to be
passed as arguments to other functions, returned as results,
stored in data structures, etc.
Functions that manipulate other functions are often called
_higher-order_ functions. Here's a simple one: *)
Definition doit3times {X:Type} (f:X->X) (n:X) : X :=
f (f (f n)).
(** The argument [f] here is itself a function (from [X] to
[X]); the body of [doit3times] applies [f] three times to some
value [n]. *)
Check @doit3times.
(* ===> doit3times : forall X : Type, (X -> X) -> X -> X *)
Example test_doit3times: doit3times minustwo 9 = 3.
Proof. reflexivity. Qed.
Example test_doit3times': doit3times negb true = false.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Partial Application *)
(** In fact, the multiple-argument functions we have already
seen are also examples of passing functions as data. To see why,
recall the type of [plus]. *)
Check plus.
(* ==> nat -> nat -> nat *)
(** Each [->] in this expression is actually a _binary_ operator
on types. (This is the same as saying that Coq primitively
supports only one-argument functions -- do you see why?) This
operator is _right-associative_, so the type of [plus] is really a
shorthand for [nat -> (nat -> nat)] -- i.e., it can be read as
saying that "[plus] is a one-argument function that takes a [nat]
and returns a one-argument function that takes another [nat] and
returns a [nat]." In the examples above, we have always applied
[plus] to both of its arguments at once, but if we like we can
supply just the first. This is called _partial application_. *)
Definition plus3 := plus 3.
Check plus3.
Example test_plus3 : plus3 4 = 7.
Proof. reflexivity. Qed.
Example test_plus3' : doit3times plus3 0 = 9.
Proof. reflexivity. Qed.
Example test_plus3'' : doit3times (plus 3) 0 = 9.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Digression: Currying *)
(** **** Exercise: 2 stars, advanced (currying) *)
(** In Coq, a function [f : A -> B -> C] really has the type [A
-> (B -> C)]. That is, if you give [f] a value of type [A], it
will give you function [f' : B -> C]. If you then give [f'] a
value of type [B], it will return a value of type [C]. This
allows for partial application, as in [plus3]. Processing a list
of arguments with functions that return functions is called
_currying_, in honor of the logician Haskell Curry.
Conversely, we can reinterpret the type [A -> B -> C] as [(A *
B) -> C]. This is called _uncurrying_. With an uncurried binary
function, both arguments must be given at once as a pair; there is
no partial application. *)
(** We can define currying as follows: *)
Definition prod_curry {X Y Z : Type}
(f : X * Y -> Z) (x : X) (y : Y) : Z := f (x, y).
(** As an exercise, define its inverse, [prod_uncurry]. Then prove
the theorems below to show that the two are inverses. *)
Definition prod_uncurry {X Y Z : Type}
(f : X -> Y -> Z) (p : X * Y) : Z :=
(* FILL IN HERE *) admit.
(** (Thought exercise: before running these commands, can you
calculate the types of [prod_curry] and [prod_uncurry]?) *)
Check @prod_curry.
Check @prod_uncurry.
Theorem uncurry_curry : forall (X Y Z : Type) (f : X -> Y -> Z) x y,
prod_curry (prod_uncurry f) x y = f x y.
Proof.
(* FILL IN HERE *) Admitted.
Theorem curry_uncurry : forall (X Y Z : Type)
(f : (X * Y) -> Z) (p : X * Y),
prod_uncurry (prod_curry f) p = f p.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################### *)
(** ** Filter *)
(** Here is a useful higher-order function, which takes a list
of [X]s and a _predicate_ on [X] (a function from [X] to [bool])
and "filters" the list, returning a new list containing just those
elements for which the predicate returns [true]. *)
Fixpoint filter {X:Type} (test: X->bool) (l:list X)
: (list X) :=
match l with
| [] => []
| h :: t => if test h then h :: (filter test t)
else filter test t
end.
(** For example, if we apply [filter] to the predicate [evenb]
and a list of numbers [l], it returns a list containing just the
even members of [l]. *)
Example test_filter1: filter evenb [1;2;3;4] = [2;4].
Proof. reflexivity. Qed.
(** *** *)
Definition length_is_1 {X : Type} (l : list X) : bool :=
beq_nat (length l) 1.
Example test_filter2:
filter length_is_1
[ [1; 2]; [3]; [4]; [5;6;7]; []; [8] ]
= [ [3]; [4]; [8] ].
Proof. reflexivity. Qed.
(** *** *)
(** We can use [filter] to give a concise version of the
[countoddmembers] function from the [Lists] chapter. *)
Definition countoddmembers' (l:list nat) : nat :=
length (filter oddb l).
Example test_countoddmembers'1: countoddmembers' [1;0;3;1;4;5] = 4.
Proof. reflexivity. Qed.
Example test_countoddmembers'2: countoddmembers' [0;2;4] = 0.
Proof. reflexivity. Qed.
Example test_countoddmembers'3: countoddmembers' nil = 0.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Anonymous Functions *)
(** It is a little annoying to be forced to define the function
[length_is_1] and give it a name just to be able to pass it as an
argument to [filter], since we will probably never use it again.
Moreover, this is not an isolated example. When using
higher-order functions, we often want to pass as arguments
"one-off" functions that we will never use again; having to give
each of these functions a name would be tedious.
Fortunately, there is a better way. It is also possible to
construct a function "on the fly" without declaring it at the top
level or giving it a name; this is analogous to the notation we've
been using for writing down constant lists, natural numbers, and
so on. *)
Example test_anon_fun':
doit3times (fun n => n * n) 2 = 256.
Proof. reflexivity. Qed.
(** Here is the motivating example from before, rewritten to use
an anonymous function. *)
Example test_filter2':
filter (fun l => beq_nat (length l) 1)
[ [1; 2]; [3]; [4]; [5;6;7]; []; [8] ]
= [ [3]; [4]; [8] ].
Proof. reflexivity. Qed.
(** **** Exercise: 2 stars (filter_even_gt7) *)
(** Use [filter] (instead of [Fixpoint]) to write a Coq function
[filter_even_gt7] that takes a list of natural numbers as input
and returns a list of just those that are even and greater than
7. *)
Definition filter_even_gt7 (l : list nat) : list nat :=
(* FILL IN HERE *) admit.
Example test_filter_even_gt7_1 :
filter_even_gt7 [1;2;6;9;10;3;12;8] = [10;12;8].
(* FILL IN HERE *) Admitted.
Example test_filter_even_gt7_2 :
filter_even_gt7 [5;2;6;19;129] = [].
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars (partition) *)
(** Use [filter] to write a Coq function [partition]:
partition : forall X : Type,
(X -> bool) -> list X -> list X * list X
Given a set [X], a test function of type [X -> bool] and a [list
X], [partition] should return a pair of lists. The first member of
the pair is the sublist of the original list containing the
elements that satisfy the test, and the second is the sublist
containing those that fail the test. The order of elements in the
two sublists should be the same as their order in the original
list.
*)
Definition partition {X : Type} (test : X -> bool) (l : list X)
: list X * list X :=
(* FILL IN HERE *) admit.
Example test_partition1: partition oddb [1;2;3;4;5] = ([1;3;5], [2;4]).
(* FILL IN HERE *) Admitted.
Example test_partition2: partition (fun x => false) [5;9;0] = ([], [5;9;0]).
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################### *)
(** ** Map *)
(** Another handy higher-order function is called [map]. *)
Fixpoint map {X Y:Type} (f:X->Y) (l:list X)
: (list Y) :=
match l with
| [] => []
| h :: t => (f h) :: (map f t)
end.
(** *** *)
(** It takes a function [f] and a list [ l = [n1, n2, n3, ...] ]
and returns the list [ [f n1, f n2, f n3,...] ], where [f] has
been applied to each element of [l] in turn. For example: *)
Example test_map1: map (plus 3) [2;0;2] = [5;3;5].
Proof. reflexivity. Qed.
(** The element types of the input and output lists need not be
the same ([map] takes _two_ type arguments, [X] and [Y]). This
version of [map] can thus be applied to a list of numbers and a
function from numbers to booleans to yield a list of booleans: *)
Example test_map2: map oddb [2;1;2;5] = [false;true;false;true].
Proof. reflexivity. Qed.
(** It can even be applied to a list of numbers and
a function from numbers to _lists_ of booleans to
yield a list of lists of booleans: *)
Example test_map3:
map (fun n => [evenb n;oddb n]) [2;1;2;5]
= [[true;false];[false;true];[true;false];[false;true]].
Proof. reflexivity. Qed.
(** ** Map for options *)
(** **** Exercise: 3 stars (map_rev) *)
(** Show that [map] and [rev] commute. You may need to define an
auxiliary lemma. *)
Theorem map_rev : forall (X Y : Type) (f : X -> Y) (l : list X),
map f (rev l) = rev (map f l).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars (flat_map) *)
(** The function [map] maps a [list X] to a [list Y] using a function
of type [X -> Y]. We can define a similar function, [flat_map],
which maps a [list X] to a [list Y] using a function [f] of type
[X -> list Y]. Your definition should work by 'flattening' the
results of [f], like so:
flat_map (fun n => [n;n+1;n+2]) [1;5;10]
= [1; 2; 3; 5; 6; 7; 10; 11; 12].
*)
Fixpoint flat_map {X Y:Type} (f:X -> list Y) (l:list X)
: (list Y) :=
(* FILL IN HERE *) admit.
Example test_flat_map1:
flat_map (fun n => [n;n;n]) [1;5;4]
= [1; 1; 1; 5; 5; 5; 4; 4; 4].
(* FILL IN HERE *) Admitted.
(** [] *)
(** Lists are not the only inductive type that we can write a
[map] function for. Here is the definition of [map] for the
[option] type: *)
Definition option_map {X Y : Type} (f : X -> Y) (xo : option X)
: option Y :=
match xo with
| None => None
| Some x => Some (f x)
end.
(** **** Exercise: 2 stars, optional (implicit_args) *)
(** The definitions and uses of [filter] and [map] use implicit
arguments in many places. Replace the curly braces around the
implicit arguments with parentheses, and then fill in explicit
type parameters where necessary and use Coq to check that you've
done so correctly. (This exercise is not to be turned in; it is
probably easiest to do it on a _copy_ of this file that you can
throw away afterwards.) [] *)
(* ###################################################### *)
(** ** Fold *)
(** An even more powerful higher-order function is called
[fold]. This function is the inspiration for the "[reduce]"
operation that lies at the heart of Google's map/reduce
distributed programming framework. *)
Fixpoint fold {X Y:Type} (f: X->Y->Y) (l:list X) (b:Y) : Y :=
match l with
| nil => b
| h :: t => f h (fold f t b)
end.
(** *** *)
(** Intuitively, the behavior of the [fold] operation is to
insert a given binary operator [f] between every pair of elements
in a given list. For example, [ fold plus [1;2;3;4] ] intuitively
means [1+2+3+4]. To make this precise, we also need a "starting
element" that serves as the initial second input to [f]. So, for
example,
fold plus [1;2;3;4] 0
yields
1 + (2 + (3 + (4 + 0))).
Here are some more examples:
*)
Check (fold andb).
(* ===> fold andb : list bool -> bool -> bool *)
Example fold_example1 : fold mult [1;2;3;4] 1 = 24.
Proof. reflexivity. Qed.
Example fold_example2 : fold andb [true;true;false;true] true = false.
Proof. reflexivity. Qed.
Example fold_example3 : fold app [[1];[];[2;3];[4]] [] = [1;2;3;4].
Proof. reflexivity. Qed.
(** **** Exercise: 1 star, advanced (fold_types_different) *)
(** Observe that the type of [fold] is parameterized by _two_ type
variables, [X] and [Y], and the parameter [f] is a binary operator
that takes an [X] and a [Y] and returns a [Y]. Can you think of a
situation where it would be useful for [X] and [Y] to be
different? *)
(* ###################################################### *)
(** ** Functions For Constructing Functions *)
(** Most of the higher-order functions we have talked about so
far take functions as _arguments_. Now let's look at some
examples involving _returning_ functions as the results of other
functions.
To begin, here is a function that takes a value [x] (drawn from
some type [X]) and returns a function from [nat] to [X] that
yields [x] whenever it is called, ignoring its [nat] argument. *)
Definition constfun {X: Type} (x: X) : nat->X :=
fun (k:nat) => x.
Definition ftrue := constfun true.
Example constfun_example1 : ftrue 0 = true.
Proof. reflexivity. Qed.
Example constfun_example2 : (constfun 5) 99 = 5.
Proof. reflexivity. Qed.
(** *** *)
(** Similarly, but a bit more interestingly, here is a function
that takes a function [f] from numbers to some type [X], a number
[k], and a value [x], and constructs a function that behaves
exactly like [f] except that, when called with the argument [k],
it returns [x]. *)
Definition override {X: Type} (f: nat->X) (k:nat) (x:X) : nat->X:=
fun (k':nat) => if beq_nat k k' then x else f k'.
(** For example, we can apply [override] twice to obtain a
function from numbers to booleans that returns [false] on [1] and
[3] and returns [true] on all other arguments. *)
Definition fmostlytrue := override (override ftrue 1 false) 3 false.
(** *** *)
Example override_example1 : fmostlytrue 0 = true.
Proof. reflexivity. Qed.
Example override_example2 : fmostlytrue 1 = false.
Proof. reflexivity. Qed.
Example override_example3 : fmostlytrue 2 = true.
Proof. reflexivity. Qed.
Example override_example4 : fmostlytrue 3 = false.
Proof. reflexivity. Qed.
(** *** *)
(** **** Exercise: 1 star (override_example) *)
(** Before starting to work on the following proof, make sure you
understand exactly what the theorem is saying and can paraphrase
it in your own words. The proof itself is straightforward. *)
Theorem override_example : forall (b:bool),
(override (constfun b) 3 true) 2 = b.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** We'll use function overriding heavily in parts of the rest of the
course, and we will end up needing to know quite a bit about its
properties. To prove these properties, though, we need to know
about a few more of Coq's tactics; developing these is the main
topic of the next chapter. For now, though, let's introduce just
one very useful tactic that will also help us with proving
properties of some of the other functions we have introduced in
this chapter. *)
(* ###################################################### *)
(* ###################################################### *)
(** * The [unfold] Tactic *)
(** Sometimes, a proof will get stuck because Coq doesn't
automatically expand a function call into its definition. (This
is a feature, not a bug: if Coq automatically expanded everything
possible, our proof goals would quickly become enormous -- hard to
read and slow for Coq to manipulate!) *)
Theorem unfold_example_bad : forall m n,
3 + n = m ->
plus3 n + 1 = m + 1.
Proof.
intros m n H.
(* At this point, we'd like to do [rewrite -> H], since
[plus3 n] is definitionally equal to [3 + n]. However,
Coq doesn't automatically expand [plus3 n] to its
definition. *)
Abort.
(** The [unfold] tactic can be used to explicitly replace a
defined name by the right-hand side of its definition. *)
Theorem unfold_example : forall m n,
3 + n = m ->
plus3 n + 1 = m + 1.
Proof.
intros m n H.
unfold plus3.
rewrite -> H.
reflexivity. Qed.
(** Now we can prove a first property of [override]: If we
override a function at some argument [k] and then look up [k], we
get back the overridden value. *)
Theorem override_eq : forall {X:Type} x k (f:nat->X),
(override f k x) k = x.
Proof.
intros X x k f.
unfold override.
rewrite <- beq_nat_refl.
reflexivity. Qed.
(** This proof was straightforward, but note that it requires
[unfold] to expand the definition of [override]. *)
(** **** Exercise: 2 stars (override_neq) *)
Theorem override_neq : forall (X:Type) x1 x2 k1 k2 (f : nat->X),
f k1 = x1 ->
beq_nat k2 k1 = false ->
(override f k2 x2) k1 = x1.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** As the inverse of [unfold], Coq also provides a tactic
[fold], which can be used to "unexpand" a definition. It is used
much less often. *)
(* ##################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 2 stars (fold_length) *)
(** Many common functions on lists can be implemented in terms of
[fold]. For example, here is an alternative definition of [length]: *)
Definition fold_length {X : Type} (l : list X) : nat :=
fold (fun _ n => S n) l 0.
Example test_fold_length1 : fold_length [4;7;0] = 3.
Proof. reflexivity. Qed.
(** Prove the correctness of [fold_length]. *)
Theorem fold_length_correct : forall X (l : list X),
fold_length l = length l.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars (fold_map) *)
(** We can also define [map] in terms of [fold]. Finish [fold_map]
below. *)
Definition fold_map {X Y:Type} (f : X -> Y) (l : list X) : list Y :=
(* FILL IN HERE *) admit.
(** Write down a theorem [fold_map_correct] in Coq stating that
[fold_map] is correct, and prove it. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 2 stars, advanced (index_informal) *)
(** Recall the definition of the [index] function:
Fixpoint index {X : Type} (n : nat) (l : list X) : option X :=
match l with
| [] => None
| a :: l' => if beq_nat n O then Some a else index (pred n) l'
end.
Write an informal proof of the following theorem:
forall X n l, length l = n -> @index X n l = None.
(* FILL IN HERE *)
*)
(** [] *)
(** **** Exercise: 4 stars, advanced (church_numerals) *)
Module Church.
(** In this exercise, we will explore an alternative way of defining
natural numbers, using the so-called _Church numerals_, named
after mathematician Alonzo Church. We can represent a natural
number [n] as a function that takes a function [f] as a parameter
and returns [f] iterated [n] times. More formally, *)
Definition nat := forall X : Type, (X -> X) -> X -> X.
(** Let's see how to write some numbers with this notation. Any
function [f] iterated once shouldn't change. Thus, *)
Definition one : nat :=
fun (X : Type) (f : X -> X) (x : X) => f x.
(** [two] should apply [f] twice to its argument: *)
Definition two : nat :=
fun (X : Type) (f : X -> X) (x : X) => f (f x).
(** [zero] is somewhat trickier: how can we apply a function zero
times? The answer is simple: just leave the argument untouched. *)
Definition zero : nat :=
fun (X : Type) (f : X -> X) (x : X) => x.
(** More generally, a number [n] will be written as [fun X f x => f (f
... (f x) ...)], with [n] occurrences of [f]. Notice in particular
how the [doit3times] function we've defined previously is actually
just the representation of [3]. *)
Definition three : nat := @doit3times.
(** Complete the definitions of the following functions. Make sure
that the corresponding unit tests pass by proving them with
[reflexivity]. *)
(** Successor of a natural number *)
Definition succ (n : nat) : nat :=
(* FILL IN HERE *) admit.
Example succ_1 : succ zero = one.
Proof. (* FILL IN HERE *) Admitted.
Example succ_2 : succ one = two.
Proof. (* FILL IN HERE *) Admitted.
Example succ_3 : succ two = three.
Proof. (* FILL IN HERE *) Admitted.
(** Addition of two natural numbers *)
Definition plus (n m : nat) : nat :=
(* FILL IN HERE *) admit.
Example plus_1 : plus zero one = one.
Proof. (* FILL IN HERE *) Admitted.
Example plus_2 : plus two three = plus three two.
Proof. (* FILL IN HERE *) Admitted.
Example plus_3 :
plus (plus two two) three = plus one (plus three three).
Proof. (* FILL IN HERE *) Admitted.
(** Multiplication *)
Definition mult (n m : nat) : nat :=
(* FILL IN HERE *) admit.
Example mult_1 : mult one one = one.
Proof. (* FILL IN HERE *) Admitted.
Example mult_2 : mult zero (plus three three) = zero.
Proof. (* FILL IN HERE *) Admitted.
Example mult_3 : mult two three = plus three three.
Proof. (* FILL IN HERE *) Admitted.
(** Exponentiation *)
(** Hint: Polymorphism plays a crucial role here. However, choosing
the right type to iterate over can be tricky. If you hit a
"Universe inconsistency" error, try iterating over a different
type: [nat] itself is usually problematic. *)
Definition exp (n m : nat) : nat :=
(* FILL IN HERE *) admit.
Example exp_1 : exp two two = plus two two.
Proof. (* FILL IN HERE *) Admitted.
Example exp_2 : exp three two = plus (mult two (mult two two)) one.
Proof. (* FILL IN HERE *) Admitted.
Example exp_3 : exp three zero = one.
Proof. (* FILL IN HERE *) Admitted.
End Church.
(** [] *)
(** $Date: 2014-12-31 11:17:56 -0500 (Wed, 31 Dec 2014) $ *)
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// IP VLNV: xilinx.com:hls:hls_macc:1.0
// IP Revision: 1909220225
`timescale 1ns/1ps
(* IP_DEFINITION_SOURCE = "HLS" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module zybo_zynq_design_hls_macc_0_0 (
s_axi_HLS_MACC_PERIPH_BUS_AWADDR,
s_axi_HLS_MACC_PERIPH_BUS_AWVALID,
s_axi_HLS_MACC_PERIPH_BUS_AWREADY,
s_axi_HLS_MACC_PERIPH_BUS_WDATA,
s_axi_HLS_MACC_PERIPH_BUS_WSTRB,
s_axi_HLS_MACC_PERIPH_BUS_WVALID,
s_axi_HLS_MACC_PERIPH_BUS_WREADY,
s_axi_HLS_MACC_PERIPH_BUS_BRESP,
s_axi_HLS_MACC_PERIPH_BUS_BVALID,
s_axi_HLS_MACC_PERIPH_BUS_BREADY,
s_axi_HLS_MACC_PERIPH_BUS_ARADDR,
s_axi_HLS_MACC_PERIPH_BUS_ARVALID,
s_axi_HLS_MACC_PERIPH_BUS_ARREADY,
s_axi_HLS_MACC_PERIPH_BUS_RDATA,
s_axi_HLS_MACC_PERIPH_BUS_RRESP,
s_axi_HLS_MACC_PERIPH_BUS_RVALID,
s_axi_HLS_MACC_PERIPH_BUS_RREADY,
ap_clk,
ap_rst_n,
interrupt
);
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS AWADDR" *)
input wire [5 : 0] s_axi_HLS_MACC_PERIPH_BUS_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS AWVALID" *)
input wire s_axi_HLS_MACC_PERIPH_BUS_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS AWREADY" *)
output wire s_axi_HLS_MACC_PERIPH_BUS_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS WDATA" *)
input wire [31 : 0] s_axi_HLS_MACC_PERIPH_BUS_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS WSTRB" *)
input wire [3 : 0] s_axi_HLS_MACC_PERIPH_BUS_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS WVALID" *)
input wire s_axi_HLS_MACC_PERIPH_BUS_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS WREADY" *)
output wire s_axi_HLS_MACC_PERIPH_BUS_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS BRESP" *)
output wire [1 : 0] s_axi_HLS_MACC_PERIPH_BUS_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS BVALID" *)
output wire s_axi_HLS_MACC_PERIPH_BUS_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS BREADY" *)
input wire s_axi_HLS_MACC_PERIPH_BUS_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS ARADDR" *)
input wire [5 : 0] s_axi_HLS_MACC_PERIPH_BUS_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS ARVALID" *)
input wire s_axi_HLS_MACC_PERIPH_BUS_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS ARREADY" *)
output wire s_axi_HLS_MACC_PERIPH_BUS_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS RDATA" *)
output wire [31 : 0] s_axi_HLS_MACC_PERIPH_BUS_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS RRESP" *)
output wire [1 : 0] s_axi_HLS_MACC_PERIPH_BUS_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS RVALID" *)
output wire s_axi_HLS_MACC_PERIPH_BUS_RVALID;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_HLS_MACC_PERIPH_BUS, ADDR_WIDTH 6, DATA_WIDTH 32, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ\
100000000, ID_WIDTH 0, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN zybo_zynq_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_HLS_MACC_PERIPH_BUS RREADY" *)
input wire s_axi_HLS_MACC_PERIPH_BUS_RREADY;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ap_clk, ASSOCIATED_BUSIF s_axi_HLS_MACC_PERIPH_BUS, ASSOCIATED_RESET ap_rst_n, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 100000000, PHASE 0.000,\
CLK_DOMAIN zybo_zynq_design_processing_system7_0_0_FCLK_CLK0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ap_clk CLK" *)
input wire ap_clk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ap_rst_n, POLARITY ACTIVE_LOW, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {RST {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 ap_rst_n RST" *)
input wire ap_rst_n;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME interrupt, SENSITIVITY LEVEL_HIGH, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {INTERRUPT {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, PortWidth 1" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT" *)
output wire interrupt;
hls_macc #(
.C_S_AXI_HLS_MACC_PERIPH_BUS_ADDR_WIDTH(6),
.C_S_AXI_HLS_MACC_PERIPH_BUS_DATA_WIDTH(32)
) inst (
.s_axi_HLS_MACC_PERIPH_BUS_AWADDR(s_axi_HLS_MACC_PERIPH_BUS_AWADDR),
.s_axi_HLS_MACC_PERIPH_BUS_AWVALID(s_axi_HLS_MACC_PERIPH_BUS_AWVALID),
.s_axi_HLS_MACC_PERIPH_BUS_AWREADY(s_axi_HLS_MACC_PERIPH_BUS_AWREADY),
.s_axi_HLS_MACC_PERIPH_BUS_WDATA(s_axi_HLS_MACC_PERIPH_BUS_WDATA),
.s_axi_HLS_MACC_PERIPH_BUS_WSTRB(s_axi_HLS_MACC_PERIPH_BUS_WSTRB),
.s_axi_HLS_MACC_PERIPH_BUS_WVALID(s_axi_HLS_MACC_PERIPH_BUS_WVALID),
.s_axi_HLS_MACC_PERIPH_BUS_WREADY(s_axi_HLS_MACC_PERIPH_BUS_WREADY),
.s_axi_HLS_MACC_PERIPH_BUS_BRESP(s_axi_HLS_MACC_PERIPH_BUS_BRESP),
.s_axi_HLS_MACC_PERIPH_BUS_BVALID(s_axi_HLS_MACC_PERIPH_BUS_BVALID),
.s_axi_HLS_MACC_PERIPH_BUS_BREADY(s_axi_HLS_MACC_PERIPH_BUS_BREADY),
.s_axi_HLS_MACC_PERIPH_BUS_ARADDR(s_axi_HLS_MACC_PERIPH_BUS_ARADDR),
.s_axi_HLS_MACC_PERIPH_BUS_ARVALID(s_axi_HLS_MACC_PERIPH_BUS_ARVALID),
.s_axi_HLS_MACC_PERIPH_BUS_ARREADY(s_axi_HLS_MACC_PERIPH_BUS_ARREADY),
.s_axi_HLS_MACC_PERIPH_BUS_RDATA(s_axi_HLS_MACC_PERIPH_BUS_RDATA),
.s_axi_HLS_MACC_PERIPH_BUS_RRESP(s_axi_HLS_MACC_PERIPH_BUS_RRESP),
.s_axi_HLS_MACC_PERIPH_BUS_RVALID(s_axi_HLS_MACC_PERIPH_BUS_RVALID),
.s_axi_HLS_MACC_PERIPH_BUS_RREADY(s_axi_HLS_MACC_PERIPH_BUS_RREADY),
.ap_clk(ap_clk),
.ap_rst_n(ap_rst_n),
.interrupt(interrupt)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__XNOR3_FUNCTIONAL_V
`define SKY130_FD_SC_MS__XNOR3_FUNCTIONAL_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__xnor3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Local signals
wire xnor0_out_X;
// Name Output Other arguments
xnor xnor0 (xnor0_out_X, A, B, C );
buf buf0 (X , xnor0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__XNOR3_FUNCTIONAL_V |
// Check that the signedness of class properties are handled correctly when
// accessing the property on a class object.
module test;
bit failed = 1'b0;
`define check(x) \
if (!(x)) begin \
$display("FAILED(%0d): ", `__LINE__, `"x`"); \
failed = 1'b1; \
end
class C;
shortint s = -1;
bit [15:0] u = -1;
endclass
C c;
int unsigned x = 10;
int y = 10;
int z;
initial begin
c = new;
// These all evaluate as signed
`check(c.s < 0)
`check($signed(c.u) < 0)
// These all evaluate as unsigned
`check(c.u > 0)
`check({c.s} > 0)
`check($unsigned(c.s) > 0)
`check(c.s > 16'h0)
// In arithmetic expressions if one operand is unsigned all operands are
// considered unsigned
z = c.u + x;
`check(z === 65545)
z = c.u + y;
`check(z === 65545)
z = c.s + x;
`check(z === 65545)
z = c.s + y;
`check(z === 9)
// For ternary operators if one operand is unsigned the result is unsigend
z = x ? c.u : x;
`check(z === 65535)
z = x ? c.u : y;
`check(z === 65535)
z = x ? c.s : x;
`check(z === 65535)
z = x ? c.s : y;
`check(z === -1)
if (!failed) begin
$display("PASSED");
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: INSTITUTO TECNOLOGICO DE COSTA RICA
// Engineer: MAURICIO CARVAJAL DELGADO
//
// Create Date: 10:33:48 03/17/2013
// Design Name:
// Module Name: Transmisor
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//////////////////////////////////////////////////////////////////////////////////
module Transmisor
#(
parameter DBIT = 8 , // #databits
SB_TICK = 16 // #ticks fors top bits
)
(
input wire clk, reset,
input wire tx_start, s_tick,
input wire [7:0] din,
output reg TX_Done=0,
output wire tx
);
// synlbolic s t a t e d e c l a r a t i o n
localparam [1:0]
idle = 2'b00,
start = 2'b01,
data = 2'b10,
stop = 2'b11;
// signal declaratio n
reg [1:0] state_reg=0, state_next=0;
reg [3:0] s_reg=0, s_next=0;
reg [2:0] n_reg=0, n_next=0;
reg [7:0] b_reg=0, b_next=0;
reg tx_reg=1, tx_next=1;
// FSMD state & data registers
always @(posedge clk, posedge reset)
if (reset)
begin
state_reg <= idle;
s_reg <= 0;
n_reg <= 0;
b_reg <= 0 ;
tx_reg <= 1'b1;
end
else
begin
state_reg <= state_next;
s_reg <= s_next;
n_reg <= n_next;
b_reg <= b_next;
tx_reg <= tx_next;
end
// FSMD next_state logic&functional units
always @*
begin
state_next = state_reg;
TX_Done = 1'b0;
s_next = s_reg;
n_next = n_reg;
b_next = b_reg;
tx_next = tx_reg;
case (state_reg)
idle:
begin
tx_next = 1'b1;
if (tx_start)
begin
state_next = start;
s_next =0;
b_next = din;
end
end
start:
begin
tx_next =1'b0;
if (s_tick)
if (s_reg ==15)
begin
state_next = data;
s_next = 0;
n_next = 0;
end
else
s_next = s_reg + 1;
end
data:
begin
tx_next =b_reg[0];
if (s_tick)
if (s_reg == 15)
begin
s_next =0;
b_next = b_reg>>1;
if (n_reg==(DBIT-1))
state_next = stop;
else
n_next = n_reg + 1;
end
else
s_next = s_reg + 1;
end
stop:
begin
tx_next =1'b1;
if (s_tick)
if (s_reg==(SB_TICK-1 ))
begin
state_next = idle;
TX_Done = 1'b1;
end
else
s_next = s_reg+ 1;
end
endcase
end
// output
assign tx = tx_reg;
endmodule
|
module test ();
reg pass = 1'b1;
reg d;
real a = 0.0;
wire real f = a;
always @(d) force f = 0.0;
initial begin
// Verify the initial value.
#1;
if (f != 0.0) begin
$display("Failed initial value, expected 0.0, got %f", f);
pass = 1'b0;
end
// Verify the value can change.
#1 a = 1.0;
if (f != 1.0) begin
$display("Failed value change, expected 1.0, got %f", f);
pass = 1'b0;
end
// Verify that the force changed the value and that the CA is blocked.
#1 d = 0;
#1 a = 1.0;
if (f != 0.0) begin
$display("Failed force holding, expected 0.0, got %f", f);
pass = 1'b0;
end
// Verify that the release propagates the CA value.
#1 release f;
if (f != 1.0) begin
$display("Failed release change, expected 1.0, got %f", f);
pass = 1'b0;
end
// Verify that the value can be changed after a release.
#1 a = 0.0;
if (f != 0.0) begin
$display("Failed release, expected 0.0, got %f", f);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
// Date : Mon May 26 17:47:23 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode synth_stub
// /home/keith/Documents/VHDL-lib/top/stereo_radio/ip/fir_lp_15kHz/fir_lp_15kHz_stub.v
// Design : fir_lp_15kHz
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fir_compiler_v7_1,Vivado 2014.1" *)
module fir_lp_15kHz(aclk, s_axis_data_tvalid, s_axis_data_tready, s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata)
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[15:0],m_axis_data_tvalid,m_axis_data_tdata[47:0]" */;
input aclk;
input s_axis_data_tvalid;
output s_axis_data_tready;
input [15:0]s_axis_data_tdata;
output m_axis_data_tvalid;
output [47:0]m_axis_data_tdata;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ff_jbi_sc2_1.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module ff_jbi_sc2_1(/*AUTOARG*/
// Outputs
jbi_sctag_req_d1, scbuf_jbi_data_d1, jbi_scbuf_ecc_d1,
jbi_sctag_req_vld_d1, scbuf_jbi_ctag_vld_d1, scbuf_jbi_ue_err_d1,
sctag_jbi_iq_dequeue_d1, sctag_jbi_wib_dequeue_d1,
sctag_jbi_por_req_d1, so,
// Inputs
jbi_sctag_req, scbuf_jbi_data, jbi_scbuf_ecc, jbi_sctag_req_vld,
scbuf_jbi_ctag_vld, scbuf_jbi_ue_err, sctag_jbi_iq_dequeue,
sctag_jbi_wib_dequeue, sctag_jbi_por_req, rclk, si, se
);
output [31:0] jbi_sctag_req_d1;
output [31:0] scbuf_jbi_data_d1;
output [6:0] jbi_scbuf_ecc_d1;
output jbi_sctag_req_vld_d1;
output scbuf_jbi_ctag_vld_d1;
output scbuf_jbi_ue_err_d1;
output sctag_jbi_iq_dequeue_d1;
output sctag_jbi_wib_dequeue_d1;
output sctag_jbi_por_req_d1;
input [31:0] jbi_sctag_req;
input [31:0] scbuf_jbi_data;
input [6:0] jbi_scbuf_ecc;
input jbi_sctag_req_vld;
input scbuf_jbi_ctag_vld;
input scbuf_jbi_ue_err;
input sctag_jbi_iq_dequeue;
input sctag_jbi_wib_dequeue;
input sctag_jbi_por_req;
input rclk;
input si, se;
output so;
wire int_scanout;
// connect scanout of the last flop to int_scanout.
// The output of the lockup latch is
// the scanout of this dbb (so)
bw_u1_scanlg_2x so_lockup(.so(so), .sd(int_scanout), .ck(rclk), .se(se));
dff_s #(32) ff_flop_row0 (.q(jbi_sctag_req_d1[31:0]),
.din(jbi_sctag_req[31:0]),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(32) ff_flop_row1 (.q(scbuf_jbi_data_d1[31:0]),
.din(scbuf_jbi_data[31:0]),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(13) ff_flop_row2 (.q({ jbi_scbuf_ecc_d1[6:0],
jbi_sctag_req_vld_d1,
scbuf_jbi_ctag_vld_d1,
scbuf_jbi_ue_err_d1,
sctag_jbi_iq_dequeue_d1,
sctag_jbi_wib_dequeue_d1,
sctag_jbi_por_req_d1}),
.din({ jbi_scbuf_ecc[6:0],
jbi_sctag_req_vld,
scbuf_jbi_ctag_vld,
scbuf_jbi_ue_err,
sctag_jbi_iq_dequeue,
sctag_jbi_wib_dequeue,
sctag_jbi_por_req}),
.clk(rclk), .se(1'b0), .si(), .so() );
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFBBP_BEHAVIORAL_V
`define SKY130_FD_SC_MS__SDFBBP_BEHAVIORAL_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_ms__udp_dff_nsr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__sdfbbp (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire RESET ;
wire SET ;
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire CLK_delayed ;
wire SET_B_delayed ;
wire RESET_B_delayed;
wire mux_out ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
wire cond_D ;
wire cond_SCD ;
wire cond_SCE ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_ms__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK_delayed, mux_out, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
assign cond_D = ( ( SCE_delayed === 1'b0 ) && condb );
assign cond_SCD = ( ( SCE_delayed === 1'b1 ) && condb );
assign cond_SCE = ( ( D_delayed !== SCD_delayed ) && condb );
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFBBP_BEHAVIORAL_V |
`include "lo_simulate.v"
/*
pck0 - input main 24Mhz clock (PLL / 4)
[7:0] adc_d - input data from A/D converter
pwr_lo - output to coil drivers (ssp_clk / 8)
adc_clk - output A/D clock signal
ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)
ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
ssp_clk - output SSP clock signal
ck_1356meg - input unused
ck_1356megb - input unused
ssp_dout - input unused
cross_hi - input unused
cross_lo - input unused
pwr_hi - output unused, tied low
pwr_oe1 - output unused, undefined
pwr_oe2 - output unused, undefined
pwr_oe3 - output unused, undefined
pwr_oe4 - output unused, undefined
dbg - output alias for adc_clk
*/
module testbed_lo_simulate;
reg pck0;
reg [7:0] adc_d;
wire pwr_lo;
wire adc_clk;
wire ck_1356meg;
wire ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
reg cross_lo;
wire cross_hi;
wire dbg;
lo_simulate #(5,200) dut(
.pck0(pck0),
.ck_1356meg(ck_1356meg),
.ck_1356megb(ck_1356megb),
.pwr_lo(pwr_lo),
.pwr_hi(pwr_hi),
.pwr_oe1(pwr_oe1),
.pwr_oe2(pwr_oe2),
.pwr_oe3(pwr_oe3),
.pwr_oe4(pwr_oe4),
.adc_d(adc_d),
.adc_clk(adc_clk),
.ssp_frame(ssp_frame),
.ssp_din(ssp_din),
.ssp_dout(ssp_dout),
.ssp_clk(ssp_clk),
.cross_hi(cross_hi),
.cross_lo(cross_lo),
.dbg(dbg)
);
integer i, counter=0;
// main clock
always #5 pck0 = !pck0;
//cross_lo is not really synced to pck0 but it's roughly pck0/192 (24Mhz/192=125Khz)
task crank_dut;
begin
@(posedge pck0) ;
counter = counter + 1;
if (counter == 192) begin
counter = 0;
ssp_dout = $random;
cross_lo = 1;
end else begin
cross_lo = 0;
end
end
endtask
initial begin
pck0 = 0;
for (i = 0 ; i < 4096 ; i = i + 1) begin
crank_dut;
end
$finish;
end
endmodule // main
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Whitening function of main datapath for HIGHT Crypto Core ////
//// ////
//// This file is part of the HIGHT Crypto Core project ////
//// http://github.com/OpenSoCPlus/hight_crypto_core ////
//// http://www.opencores.org/project,hight ////
//// ////
//// Description ////
//// __description__ ////
//// ////
//// Author(s): ////
//// - JoonSoo Ha, [email protected] ////
//// - Younjoo Kim, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors, OpenSoCPlus and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module WF(
i_op ,
i_wf_in ,
i_wk ,
o_wf_out
);
//=====================================
//
// PARAMETERS
//
//=====================================
//=====================================
//
// I/O PORTS
//
//=====================================
input i_op ;
input[63:0] i_wf_in ;
input[31:0] i_wk ;
output[63:0] o_wf_out ;
//=====================================
//
// REGISTERS
//
//=====================================
//=====================================
//
// WIRES
//
//=====================================
// w_wf_out
wire[63:0] w_wf_out ;
// w_rf_out(7:0)
wire[7:0] w_wf_out7 ;
wire[7:0] w_wf_out6 ;
wire[7:0] w_wf_out5 ;
wire[7:0] w_wf_out4 ;
wire[7:0] w_wf_out3 ;
wire[7:0] w_wf_out2 ;
wire[7:0] w_wf_out1 ;
wire[7:0] w_wf_out0 ;
//=====================================
//
// MAIN
//
//=====================================
assign w_wf_out7 = i_wf_in[63:56];
assign w_wf_out6 = i_wf_in[55:48] ^ i_wk[31:24];
assign w_wf_out5 = i_wf_in[47:40];
assign w_wf_out4 = (i_op == 0) ? (i_wf_in[39:32] + i_wk[23:16]) :
(i_wf_in[39:32] - i_wk[23:16]) ;
assign w_wf_out3 = i_wf_in[31:24];
assign w_wf_out2 = i_wf_in[23:16] ^ i_wk[15:8];
assign w_wf_out1 = i_wf_in[15:8];
assign w_wf_out0 = (i_op == 0) ? (i_wf_in[7:0] + i_wk[7:0]) :
(i_wf_in[7:0] - i_wk[7:0]) ;
assign w_wf_out = {w_wf_out7, w_wf_out6, w_wf_out5, w_wf_out4, w_wf_out3, w_wf_out2, w_wf_out1, w_wf_out0};
assign o_wf_out = w_wf_out;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A31O_2_V
`define SKY130_FD_SC_HD__A31O_2_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog wrapper for a31o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a31o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a31o_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a31o_2 (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A31O_2_V
|
//======================================================================
//
// Design Name: PRESENT Block Cipher
// Module Name: PRESENT_ENCRYPT_PBOX
// Language: Verilog-2001
//
// Description: Permutation Layer (p-Layer or p-box) of PRESENT Encryption
//
// Dependencies: none
//
// Designer: Saied H. Khayat
// Date: 3/2011
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// condition is met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
`timescale 1ns/1ps
module PRESENT_ENCRYPT_PBOX(
output [63:0] odat,
input [63:0] idat
);
assign odat[0 ] = idat[0 ];
assign odat[16] = idat[1 ];
assign odat[32] = idat[2 ];
assign odat[48] = idat[3 ];
assign odat[1 ] = idat[4 ];
assign odat[17] = idat[5 ];
assign odat[33] = idat[6 ];
assign odat[49] = idat[7 ];
assign odat[2 ] = idat[8 ];
assign odat[18] = idat[9 ];
assign odat[34] = idat[10];
assign odat[50] = idat[11];
assign odat[3 ] = idat[12];
assign odat[19] = idat[13];
assign odat[35] = idat[14];
assign odat[51] = idat[15];
assign odat[4 ] = idat[16];
assign odat[20] = idat[17];
assign odat[36] = idat[18];
assign odat[52] = idat[19];
assign odat[5 ] = idat[20];
assign odat[21] = idat[21];
assign odat[37] = idat[22];
assign odat[53] = idat[23];
assign odat[6 ] = idat[24];
assign odat[22] = idat[25];
assign odat[38] = idat[26];
assign odat[54] = idat[27];
assign odat[7 ] = idat[28];
assign odat[23] = idat[29];
assign odat[39] = idat[30];
assign odat[55] = idat[31];
assign odat[8 ] = idat[32];
assign odat[24] = idat[33];
assign odat[40] = idat[34];
assign odat[56] = idat[35];
assign odat[9 ] = idat[36];
assign odat[25] = idat[37];
assign odat[41] = idat[38];
assign odat[57] = idat[39];
assign odat[10] = idat[40];
assign odat[26] = idat[41];
assign odat[42] = idat[42];
assign odat[58] = idat[43];
assign odat[11] = idat[44];
assign odat[27] = idat[45];
assign odat[43] = idat[46];
assign odat[59] = idat[47];
assign odat[12] = idat[48];
assign odat[28] = idat[49];
assign odat[44] = idat[50];
assign odat[60] = idat[51];
assign odat[13] = idat[52];
assign odat[29] = idat[53];
assign odat[45] = idat[54];
assign odat[61] = idat[55];
assign odat[14] = idat[56];
assign odat[30] = idat[57];
assign odat[46] = idat[58];
assign odat[62] = idat[59];
assign odat[15] = idat[60];
assign odat[31] = idat[61];
assign odat[47] = idat[62];
assign odat[63] = idat[63];
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This model counts from 0 to 10. It is instantiated twice in concurrent
// threads to check for race conditions/signal interference.
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020-2021 by Andreas Kuster.
// SPDX-License-Identifier: CC0-1.0
`define STRINGIFY(x) `"x`"
module top
(
input clk,
input rst,
input [31:0] trace_number,
input stop,
output bit [31:0] counter,
output bit done_o
);
initial begin
string number;
string filename;
number.itoa(trace_number);
filename = {`STRINGIFY(`TEST_OBJ_DIR), "/trace", number, ".vcd"};
$display("Writing dumpfile '%s'", filename);
$dumpfile(filename);
$dumpvars();
end
always@(posedge clk) begin
if (rst)
counter <= 0;
else
counter <= counter + 1;
end
always_comb begin
done_o = '0;
if (stop) begin
if (counter >= 5 && stop) begin
done_o = '1;
$stop;
end
end
else begin
if (counter >= 10) begin
done_o = '1;
$finish;
end
end
end
endmodule
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
//////////////////////////////////////////////////////////////////////////////////
// Company: Microsoft Research Asia
// Engineer: Jiansong Zhang
//
// Create Date: 21:39:39 06/01/2009
// Design Name:
// Module Name: tx_engine
// Project Name: Sora
// Target Devices: Virtex5 LX50T
// Tool versions: ISE10.1.03
// Description:
// Purpose: Detects rising and falling edge of input signal and outputs a
// single-cycle signal upon detection
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module edge_detect(
input clk,
input rst,
input in,
output rise_out, //single-shot output
output fall_out); //single-shot output
reg in_reg;
//one pipeline reg for the input signal
always@(posedge clk)begin
if(rst)begin
in_reg <= 1'b0;
end else begin
in_reg <= in;
end
end
//detect the rising edge
assign rise_out = ~in_reg & in;
//detect the falling edge
assign fall_out = in_reg & ~in;
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_ocmc.v
*
* Date : 2012-11
*
* Description : Controller for OCM model
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_ocmc(
rstn,
sw_clk,
/* Goes to port 0 of OCM */
ocm_wr_ack_port0,
ocm_wr_dv_port0,
ocm_rd_req_port0,
ocm_rd_dv_port0,
ocm_wr_addr_port0,
ocm_wr_data_port0,
ocm_wr_bytes_port0,
ocm_rd_addr_port0,
ocm_rd_data_port0,
ocm_rd_bytes_port0,
ocm_wr_qos_port0,
ocm_rd_qos_port0,
/* Goes to port 1 of OCM */
ocm_wr_ack_port1,
ocm_wr_dv_port1,
ocm_rd_req_port1,
ocm_rd_dv_port1,
ocm_wr_addr_port1,
ocm_wr_data_port1,
ocm_wr_bytes_port1,
ocm_rd_addr_port1,
ocm_rd_data_port1,
ocm_rd_bytes_port1,
ocm_wr_qos_port1,
ocm_rd_qos_port1
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input rstn;
input sw_clk;
output ocm_wr_ack_port0;
input ocm_wr_dv_port0;
input ocm_rd_req_port0;
output ocm_rd_dv_port0;
input[addr_width-1:0] ocm_wr_addr_port0;
input[max_burst_bits-1:0] ocm_wr_data_port0;
input[max_burst_bytes_width:0] ocm_wr_bytes_port0;
input[addr_width-1:0] ocm_rd_addr_port0;
output[max_burst_bits-1:0] ocm_rd_data_port0;
input[max_burst_bytes_width:0] ocm_rd_bytes_port0;
input [axi_qos_width-1:0] ocm_wr_qos_port0;
input [axi_qos_width-1:0] ocm_rd_qos_port0;
output ocm_wr_ack_port1;
input ocm_wr_dv_port1;
input ocm_rd_req_port1;
output ocm_rd_dv_port1;
input[addr_width-1:0] ocm_wr_addr_port1;
input[max_burst_bits-1:0] ocm_wr_data_port1;
input[max_burst_bytes_width:0] ocm_wr_bytes_port1;
input[addr_width-1:0] ocm_rd_addr_port1;
output[max_burst_bits-1:0] ocm_rd_data_port1;
input[max_burst_bytes_width:0] ocm_rd_bytes_port1;
input[axi_qos_width-1:0] ocm_wr_qos_port1;
input[axi_qos_width-1:0] ocm_rd_qos_port1;
wire [axi_qos_width-1:0] wr_qos;
wire wr_req;
wire [max_burst_bits-1:0] wr_data;
wire [addr_width-1:0] wr_addr;
wire [max_burst_bytes_width:0] wr_bytes;
reg wr_ack;
wire [axi_qos_width-1:0] rd_qos;
reg [max_burst_bits-1:0] rd_data;
wire [addr_width-1:0] rd_addr;
wire [max_burst_bytes_width:0] rd_bytes;
reg rd_dv;
wire rd_req;
processing_system7_bfm_v2_0_5_arb_wr ocm_write_ports (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(ocm_wr_qos_port0),
.qos2(ocm_wr_qos_port1),
.prt_dv1(ocm_wr_dv_port0),
.prt_dv2(ocm_wr_dv_port1),
.prt_data1(ocm_wr_data_port0),
.prt_data2(ocm_wr_data_port1),
.prt_addr1(ocm_wr_addr_port0),
.prt_addr2(ocm_wr_addr_port1),
.prt_bytes1(ocm_wr_bytes_port0),
.prt_bytes2(ocm_wr_bytes_port1),
.prt_ack1(ocm_wr_ack_port0),
.prt_ack2(ocm_wr_ack_port1),
.prt_qos(wr_qos),
.prt_req(wr_req),
.prt_data(wr_data),
.prt_addr(wr_addr),
.prt_bytes(wr_bytes),
.prt_ack(wr_ack)
);
processing_system7_bfm_v2_0_5_arb_rd ocm_read_ports (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(ocm_rd_qos_port0),
.qos2(ocm_rd_qos_port1),
.prt_req1(ocm_rd_req_port0),
.prt_req2(ocm_rd_req_port1),
.prt_data1(ocm_rd_data_port0),
.prt_data2(ocm_rd_data_port1),
.prt_addr1(ocm_rd_addr_port0),
.prt_addr2(ocm_rd_addr_port1),
.prt_bytes1(ocm_rd_bytes_port0),
.prt_bytes2(ocm_rd_bytes_port1),
.prt_dv1(ocm_rd_dv_port0),
.prt_dv2(ocm_rd_dv_port1),
.prt_qos(rd_qos),
.prt_req(rd_req),
.prt_data(rd_data),
.prt_addr(rd_addr),
.prt_bytes(rd_bytes),
.prt_dv(rd_dv)
);
processing_system7_bfm_v2_0_5_ocm_mem ocm();
reg [1:0] state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
wr_ack <= 0;
rd_dv <= 0;
state <= 2'd0;
end else begin
case(state)
0:begin
state <= 0;
wr_ack <= 0;
rd_dv <= 0;
if(wr_req) begin
ocm.write_mem(wr_data , wr_addr, wr_bytes);
wr_ack <= 1;
state <= 1;
end
if(rd_req) begin
ocm.read_mem(rd_data,rd_addr, rd_bytes);
rd_dv <= 1;
state <= 1;
end
end
1:begin
wr_ack <= 0;
rd_dv <= 0;
state <= 0;
end
endcase
end /// if
end// always
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 8
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_auto_pc_1 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [11 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [11 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [11 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [11 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_8_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(2),
.C_S_AXI_PROTOCOL(0),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(12),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(12'H000),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(12'H000),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(12'H000),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/*###########################################################################
# Function: Single port memory wrapper
# To run without hardware platform dependancy use:
# `define TARGET_CLEAN"
############################################################################
*/
module memory_sp(/*AUTOARG*/
// Outputs
dout,
// Inputs
clk, en, wen, addr, din
);
parameter AW = 14;
parameter DW = 32;
parameter WED = DW/8; //one write enable per byte
parameter MD = 1<<AW;//memory depth
//write-port
input clk; //clock
input en; //memory access
input [WED-1:0] wen; //write enable vector
input [AW-1:0] addr;//address
input [DW-1:0] din; //data input
output [DW-1:0] dout;//data output
`ifdef TARGET_CLEAN
reg [DW-1:0] ram [MD-1:0];
reg [DW-1:0] rd_data;
reg [DW-1:0] dout;
//read port
always @ (posedge clk)
if(en)
dout[DW-1:0] <= ram[addr[AW-1:0]];
//write port
generate
genvar i;
for (i = 0; i < WED; i = i+1) begin: gen_ram
always @(posedge clk)
begin
if (wen[i] & en)
ram[addr[AW-1:0]][(i+1)*8-1:i*8] <= din[(i+1)*8-1:i*8];
end
end
endgenerate
`elsif TARGET_XILINX
//instantiate XILINX BRAM (based on parameter size)
`elsif TARGET_ALTERA
//instantiate ALTERA BRAM (based on paremeter size)
`endif
endmodule // memory_dp
/*
Copyright (C) 2014 Adapteva, Inc.
Contributed by Andreas Olofsson <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_port_128.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Receives data from the tx_engine and buffers the input
// for the RIFFA channel.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module tx_port_128 #(
parameter C_DATA_WIDTH = 9'd128,
parameter C_FIFO_DEPTH = 512,
// Local parameters
parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1)
)
(
input CLK,
input RST,
input [2:0] CONFIG_MAX_PAYLOAD_SIZE, // Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B
output TXN, // Write transaction notification
input TXN_ACK, // Write transaction acknowledged
output [31:0] TXN_LEN, // Write transaction length
output [31:0] TXN_OFF_LAST, // Write transaction offset/last
output [31:0] TXN_DONE_LEN, // Write transaction actual transfer length
output TXN_DONE, // Write transaction done
input TXN_DONE_ACK, // Write transaction actual transfer length read
input [C_DATA_WIDTH-1:0] SG_DATA, // Scatter gather data
input SG_DATA_EMPTY, // Scatter gather buffer empty
output SG_DATA_REN, // Scatter gather data read enable
output SG_RST, // Scatter gather reset
input SG_ERR, // Scatter gather read encountered an error
output TX_REQ, // Outgoing write request
input TX_REQ_ACK, // Outgoing write request acknowledged
output [63:0] TX_ADDR, // Outgoing write high address
output [9:0] TX_LEN, // Outgoing write length (in 32 bit words)
output [C_DATA_WIDTH-1:0] TX_DATA, // Outgoing write data
input TX_DATA_REN, // Outgoing write data read enable
input TX_SENT, // Outgoing write complete
input CHNL_CLK, // Channel write clock
input CHNL_TX, // Channel write receive signal
output CHNL_TX_ACK, // Channel write acknowledgement signal
input CHNL_TX_LAST, // Channel last write
input [31:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [30:0] CHNL_TX_OFF, // Channel write offset
input [C_DATA_WIDTH-1:0] CHNL_TX_DATA, // Channel write data
input CHNL_TX_DATA_VALID, // Channel write data valid
output CHNL_TX_DATA_REN // Channel write data has been recieved
);
`include "functions.vh"
wire wGateRen;
wire wGateEmpty;
wire [C_DATA_WIDTH:0] wGateData;
wire wBufWen;
wire [C_FIFO_DEPTH_WIDTH-1:0] wBufCount;
wire [C_DATA_WIDTH-1:0] wBufData;
wire wTxn;
wire wTxnAck;
wire wTxnLast;
wire [31:0] wTxnLen;
wire [30:0] wTxnOff;
wire [31:0] wTxnWordsRecvd;
wire wTxnDone;
wire wTxnErr;
wire wSgElemRen;
wire wSgElemRdy;
wire wSgElemEmpty;
wire [31:0] wSgElemLen;
wire [63:0] wSgElemAddr;
wire wTxLast;
reg [4:0] rWideRst=0;
reg rRst=0;
// Generate a wide reset from the input reset.
always @ (posedge CLK) begin
rRst <= #1 rWideRst[4];
if (RST)
rWideRst <= #1 5'b11111;
else
rWideRst <= (rWideRst<<1);
end
// Capture channel transaction open/close events as well as channel data.
tx_port_channel_gate_128 #(.C_DATA_WIDTH(C_DATA_WIDTH)) gate (
.RST(rRst),
.RD_CLK(CLK),
.RD_DATA(wGateData),
.RD_EMPTY(wGateEmpty),
.RD_EN(wGateRen),
.CHNL_CLK(CHNL_CLK),
.CHNL_TX(CHNL_TX),
.CHNL_TX_ACK(CHNL_TX_ACK),
.CHNL_TX_LAST(CHNL_TX_LAST),
.CHNL_TX_LEN(CHNL_TX_LEN),
.CHNL_TX_OFF(CHNL_TX_OFF),
.CHNL_TX_DATA(CHNL_TX_DATA),
.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID),
.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN)
);
// Filter transaction events from channel data. Use the events to put only
// the requested amount of data into the port buffer.
tx_port_monitor_128 #(.C_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_FIFO_DEPTH)) monitor (
.RST(rRst),
.CLK(CLK),
.EVT_DATA(wGateData),
.EVT_DATA_EMPTY(wGateEmpty),
.EVT_DATA_RD_EN(wGateRen),
.WR_DATA(wBufData),
.WR_EN(wBufWen),
.WR_COUNT(wBufCount),
.TXN(wTxn),
.ACK(wTxnAck),
.LAST(wTxnLast),
.LEN(wTxnLen),
.OFF(wTxnOff),
.WORDS_RECVD(wTxnWordsRecvd),
.DONE(wTxnDone),
.TX_ERR(SG_ERR)
);
// Buffer the incoming channel data. Also make sure to discard only as
// much data as is needed for a transfer (which may involve non-integral
// packets (i.e. reading only 1, 2, or 3 words out of the packet).
tx_port_buffer_128 #(.C_FIFO_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_FIFO_DEPTH)) buffer (
.CLK(CLK),
.RST(rRst | (TXN_DONE & wTxnErr)),
.RD_DATA(TX_DATA),
.RD_EN(TX_DATA_REN),
.LEN_VALID(TX_REQ_ACK),
.LEN_LSB(TX_LEN[1:0]),
.LEN_LAST(wTxLast),
.WR_DATA(wBufData),
.WR_EN(wBufWen),
.WR_COUNT(wBufCount)
);
// Read the scatter gather buffer address and length, continuously so that
// we have it ready whenever the next buffer is needed.
sg_list_reader_128 #(.C_DATA_WIDTH(C_DATA_WIDTH)) sgListReader (
.CLK(CLK),
.RST(rRst | SG_RST),
.BUF_DATA(SG_DATA),
.BUF_DATA_EMPTY(SG_DATA_EMPTY),
.BUF_DATA_REN(SG_DATA_REN),
.VALID(wSgElemRdy),
.EMPTY(wSgElemEmpty),
.REN(wSgElemRen),
.ADDR(wSgElemAddr),
.LEN(wSgElemLen)
);
// Controls the flow of request to the tx engine for transfers in a transaction.
tx_port_writer writer (
.CLK(CLK),
.RST(rRst),
.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE),
.TXN(TXN),
.TXN_ACK(TXN_ACK),
.TXN_LEN(TXN_LEN),
.TXN_OFF_LAST(TXN_OFF_LAST),
.TXN_DONE_LEN(TXN_DONE_LEN),
.TXN_DONE(TXN_DONE),
.TXN_ERR(wTxnErr),
.TXN_DONE_ACK(TXN_DONE_ACK),
.NEW_TXN(wTxn),
.NEW_TXN_ACK(wTxnAck),
.NEW_TXN_LAST(wTxnLast),
.NEW_TXN_LEN(wTxnLen),
.NEW_TXN_OFF(wTxnOff),
.NEW_TXN_WORDS_RECVD(wTxnWordsRecvd),
.NEW_TXN_DONE(wTxnDone),
.SG_ELEM_ADDR(wSgElemAddr),
.SG_ELEM_LEN(wSgElemLen),
.SG_ELEM_RDY(wSgElemRdy),
.SG_ELEM_EMPTY(wSgElemEmpty),
.SG_ELEM_REN(wSgElemRen),
.SG_RST(SG_RST),
.SG_ERR(SG_ERR),
.TX_REQ(TX_REQ),
.TX_REQ_ACK(TX_REQ_ACK),
.TX_ADDR(TX_ADDR),
.TX_LEN(TX_LEN),
.TX_LAST(wTxLast),
.TX_SENT(TX_SENT)
);
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_optimized_clz_27(dataa, result);
// count the number of leading zeros in the 27-bit mantissa
input [31:0] dataa;
output [31:0] result;
wire all_zero;
acl_fp_custom_clz myclz( .mantissa(dataa[26:0]),
.result(result[4:0]),
.all_zero(all_zero));
assign result[5] = all_zero;
assign result[31:6] = 26'd0;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// verilator lint_off BLKANDNBLK
// verilator lint_off COMBDLY
// verilator lint_off UNOPT
// verilator lint_off UNOPTFLAT
// verilator lint_off MULTIDRIVEN
reg [31:0] runnerm1, runner; initial runner = 0;
reg [31:0] runcount; initial runcount = 0;
reg [31:0] clkrun; initial clkrun = 0;
reg [31:0] clkcount; initial clkcount = 0;
always @ (/*AS*/runner) begin
runnerm1 = runner - 32'd1;
end
reg run0;
always @ (/*AS*/runnerm1) begin
if ((runner & 32'hf)!=0) begin
runcount = runcount + 1;
runner = runnerm1;
$write (" seq runcount=%0d runner =%0x\n",runcount, runnerm1);
end
run0 = (runner[8:4]!=0 && runner[3:0]==0);
end
always @ (posedge run0) begin
// Do something that forces another combo run
clkcount <= clkcount + 1;
runner[8:4] <= runner[8:4] - 1;
runner[3:0] <= 3;
$write ("[%0t] posedge runner=%0x\n", $time, runner);
end
reg [7:0] cyc; initial cyc=0;
always @ (posedge clk) begin
$write("[%0t] %x counts %0x %0x\n",$time,cyc,runcount,clkcount);
cyc <= cyc + 8'd1;
case (cyc)
8'd00: begin
runner <= 0;
end
8'd01: begin
runner <= 32'h35;
end
default: ;
endcase
case (cyc)
8'd02: begin
if (runcount!=32'he) $stop;
if (clkcount!=32'h3) $stop;
end
8'd03: begin
$write("*-* All Finished *-*\n");
$finish;
end
default: ;
endcase
end
endmodule
|
`default_nettype none
module scheduler2_gr
#(
parameter ENTRY_ID = 6'h00
)(
//System
input wire iCLOCK,
input wire inRESET,
//Remove
input wire iFREE_RESTART,
//Commit_Vector
input wire [63:0] iCOMMIT_VECTOR,
//Regist
input wire iREGIST_0_VALID,
input wire [5:0] iREGIST_0_DESTINATION_REGNAME,
input wire [4:0] iREGIST_0_LOGIC_DESTINATION,
input wire [5:0] iREGIST_0_COMMIT_TAG,
input wire iREGIST_1_VALID,
input wire [5:0] iREGIST_1_DESTINATION_REGNAME,
input wire [4:0] iREGIST_1_LOGIC_DESTINATION,
input wire [5:0] iREGIST_1_COMMIT_TAG,
//EXEEND
input wire iEXEND_ADDER_VALID,
input wire [5:0] iEXEND_ADDER_COMMIT_TAG,
input wire [5:0] iEXEND_ADDER_REGNAME,
input wire [31:0] iEXEND_ADDER_DATA,
input wire iEXEND_MULDIV_VALID,
input wire [5:0] iEXEND_MULDIV_COMMIT_TAG,
input wire [5:0] iEXEND_MULDIV_REGNAME,
input wire [31:0] iEXEND_MULDIV_DATA,
input wire iEXEND_LDST_VALID,
input wire [5:0] iEXEND_LDST_COMMIT_TAG,
input wire [5:0] iEXEND_LDST_REGNAME,
input wire [31:0] iEXEND_LDST_DATA,
//Free List Valid
input wire iFREELIST_REGIST_VALID,
//INFO
output wire oINFO_FREELIST_REQ,
output wire oINFO_DATA_VALID,
output wire [31:0] oINFO_DATA
);
localparam PL_MAIN_STT_RESET = 2'h0;
localparam PL_MAIN_STT_INIT = 2'h1;
localparam PL_MAIN_STT_FREELIST = 2'h2;
localparam PL_MAIN_STT_RESERVE = 2'h3;
reg [1:0] b_main_state;
//Cuurent Entry
reg b_entry_valid;
reg [5:0] b_entry_commit_tag;
reg [4:0] b_entry_logic_dest;
reg b_entry_exe_end;
reg [31:0] b_entry_exe_data;
reg b_entry_exe_commit;
//Next Entry
reg b_next_entry_valid;
reg [5:0] b_next_entry_commit_tag;
reg b_next_entry_exe_end;
reg b_next_exe_commit;
wire init_physical_register = ENTRY_ID < 32;
wire pipe0_cuur_entry_register_condition = iREGIST_0_VALID && (iREGIST_0_DESTINATION_REGNAME == ENTRY_ID);// && (b_main_state == PL_MAIN_STT_RESERVE);
wire pipe1_cuur_entry_register_condition = iREGIST_1_VALID && (iREGIST_1_DESTINATION_REGNAME == ENTRY_ID);// && (b_main_state == PL_MAIN_STT_RESERVE);
wire pipe0_next_entry_register_condition = iREGIST_0_VALID && b_entry_valid && (iREGIST_0_LOGIC_DESTINATION == b_entry_logic_dest);
wire pipe1_next_entry_register_condition = (iREGIST_1_VALID && b_entry_valid && (iREGIST_1_LOGIC_DESTINATION == b_entry_logic_dest)) ||
(pipe0_cuur_entry_register_condition && iREGIST_1_VALID && (iREGIST_0_LOGIC_DESTINATION == iREGIST_1_LOGIC_DESTINATION));
wire freelist_req_condition = (b_main_state == PL_MAIN_STT_FREELIST);
wire cuur_commit_reset = freelist_req_condition;
wire cuur_entry_reset = freelist_req_condition || (iFREE_RESTART && (b_main_state == PL_MAIN_STT_RESERVE) && !b_entry_exe_commit);
wire cuur_exe_end_reset = freelist_req_condition || (iFREE_RESTART && (b_main_state == PL_MAIN_STT_RESERVE) && !b_entry_exe_commit);
wire next_commit_reset = freelist_req_condition;
wire next_entry_reset = freelist_req_condition || (iFREE_RESTART && (b_main_state == PL_MAIN_STT_RESERVE || b_main_state == PL_MAIN_STT_INIT) && !b_next_exe_commit);
wire next_exe_end_reset = freelist_req_condition || (iFREE_RESTART && (b_main_state == PL_MAIN_STT_RESERVE || b_main_state == PL_MAIN_STT_INIT) && !b_next_exe_commit);
//init_physical_register && (b_main_state == PL_MAIN_STT_INIT);
/*****************************************************
Main State
*****************************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_main_state <= PL_MAIN_STT_RESET;
end
else begin
case(b_main_state)
PL_MAIN_STT_RESET:
begin
if(init_physical_register)begin
b_main_state <= PL_MAIN_STT_INIT;
end
else begin
b_main_state <= PL_MAIN_STT_FREELIST;
end
end
PL_MAIN_STT_INIT:
begin
if(b_next_entry_exe_end && b_next_exe_commit)begin
b_main_state <= PL_MAIN_STT_FREELIST;
end
end
PL_MAIN_STT_FREELIST:
begin
if(iFREELIST_REGIST_VALID && !iFREE_RESTART)begin
b_main_state <= PL_MAIN_STT_RESERVE;
end
end
PL_MAIN_STT_RESERVE:
begin
if((/*b_entry_valid && b_entry_exe_end && b_entry_exe_data && b_next_entry_valid && b_next_entry_exe_end && b_next_exe_commit*/b_entry_exe_commit && b_next_exe_commit) ||
(iFREE_RESTART && !b_entry_exe_commit))
begin
b_main_state <= PL_MAIN_STT_FREELIST;
end
end
endcase
end
end
/*****************************************************
Current Entry
*****************************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_entry_valid <= 1'b0;
b_entry_commit_tag <= 6'h0;
b_entry_logic_dest <= 5'h0;
end
else if(cuur_entry_reset)begin
b_entry_valid <= 1'b0;
b_entry_commit_tag <= 6'h0;
b_entry_logic_dest <= 5'h0;
end
else begin
if(init_physical_register && b_main_state == PL_MAIN_STT_INIT)begin
b_entry_valid <= 1'b1;
b_entry_commit_tag <= 6'h0;
b_entry_logic_dest <= ENTRY_ID;
end
else if(pipe0_cuur_entry_register_condition)begin
b_entry_valid <= 1'b1;
b_entry_commit_tag <= iREGIST_0_COMMIT_TAG;
b_entry_logic_dest <= iREGIST_0_LOGIC_DESTINATION;
end
else if(pipe1_cuur_entry_register_condition)begin
b_entry_valid <= 1'b1;
b_entry_commit_tag <= iREGIST_1_COMMIT_TAG;
b_entry_logic_dest <= iREGIST_1_LOGIC_DESTINATION;
end
end
end
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_entry_exe_end <= 1'b0;
b_entry_exe_data <= 32'h0;
end
else if(cuur_exe_end_reset)begin
b_entry_exe_end <= 1'b0;
b_entry_exe_data <= 32'h0;
end
else begin
if(!b_entry_exe_end && b_entry_valid)begin
if(init_physical_register && b_main_state == PL_MAIN_STT_INIT)begin
b_entry_exe_end <= 1'b1;
b_entry_exe_data <= 32'h0;
end
else if(iEXEND_ADDER_VALID && b_entry_commit_tag == iEXEND_ADDER_COMMIT_TAG)begin
b_entry_exe_end <= 1'b1;
b_entry_exe_data <= iEXEND_ADDER_DATA;
end
else if(iEXEND_MULDIV_VALID && b_entry_commit_tag == iEXEND_MULDIV_COMMIT_TAG)begin
b_entry_exe_end <= 1'b1;
b_entry_exe_data <= iEXEND_MULDIV_DATA;
end
else if(iEXEND_LDST_VALID && b_entry_commit_tag == iEXEND_LDST_COMMIT_TAG)begin
b_entry_exe_end <= 1'b1;
b_entry_exe_data <= iEXEND_LDST_DATA;
end
end
end
end
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_entry_exe_commit <= 1'b0;
end
else if(cuur_commit_reset)begin
b_entry_exe_commit <= 1'b0;
end
else begin
if(b_entry_valid && b_entry_exe_end && !b_entry_exe_commit)begin
b_entry_exe_commit <= iCOMMIT_VECTOR[b_entry_commit_tag];
end
end
end
/*****************************************************
Next Entry
*****************************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_next_entry_valid <= 1'b0;
b_next_entry_commit_tag <= 6'h0;
end
else if(next_entry_reset)begin
b_next_entry_valid <= 1'b0;
b_next_entry_commit_tag <= 6'h0;
end
else begin
if(pipe0_next_entry_register_condition)begin
b_next_entry_valid <= 1'b1;
b_next_entry_commit_tag <= iREGIST_0_COMMIT_TAG;
end
else if(pipe1_next_entry_register_condition)begin
b_next_entry_valid <= 1'b1;
b_next_entry_commit_tag <= iREGIST_1_COMMIT_TAG;
end
end
end
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_next_entry_exe_end <= 1'b0;
end
else if(next_exe_end_reset)begin
b_next_entry_exe_end <= 1'b0;
end
else begin
if(b_next_entry_valid && iEXEND_ADDER_VALID && b_next_entry_commit_tag == iEXEND_ADDER_COMMIT_TAG)begin
b_next_entry_exe_end <= 1'b1;
end
else if(b_next_entry_valid && iEXEND_MULDIV_VALID && b_next_entry_commit_tag == iEXEND_MULDIV_COMMIT_TAG)begin
b_next_entry_exe_end <= 1'b1;
end
else if(b_next_entry_valid && iEXEND_LDST_VALID && b_next_entry_commit_tag == iEXEND_LDST_COMMIT_TAG)begin
b_next_entry_exe_end <= 1'b1;
end
end
end
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_next_exe_commit <= 1'b0;
end
else if(next_commit_reset)begin
b_next_exe_commit <= 1'b0;
end
else begin
if(b_next_entry_valid && b_next_entry_exe_end && !b_next_exe_commit)begin
b_next_exe_commit <= iCOMMIT_VECTOR[b_next_entry_commit_tag];
end
end
end
//Module Output
assign oINFO_FREELIST_REQ = (b_main_state == PL_MAIN_STT_FREELIST) && !iFREE_RESTART;
assign oINFO_DATA_VALID = b_entry_exe_end && !b_next_entry_exe_end;
assign oINFO_DATA = b_entry_exe_data;
endmodule
`default_nettype wire
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module qsys_sdram_input_efifo_module (
// inputs:
clk,
rd,
reset_n,
wr,
wr_data,
// outputs:
almost_empty,
almost_full,
empty,
full,
rd_data
)
;
output almost_empty;
output almost_full;
output empty;
output full;
output [ 42: 0] rd_data;
input clk;
input rd;
input reset_n;
input wr;
input [ 42: 0] wr_data;
wire almost_empty;
wire almost_full;
wire empty;
reg [ 1: 0] entries;
reg [ 42: 0] entry_0;
reg [ 42: 0] entry_1;
wire full;
reg rd_address;
reg [ 42: 0] rd_data;
wire [ 1: 0] rdwr;
reg wr_address;
assign rdwr = {rd, wr};
assign full = entries == 2;
assign almost_full = entries >= 1;
assign empty = entries == 0;
assign almost_empty = entries <= 1;
always @(entry_0 or entry_1 or rd_address)
begin
case (rd_address) // synthesis parallel_case full_case
1'd0: begin
rd_data = entry_0;
end // 1'd0
1'd1: begin
rd_data = entry_1;
end // 1'd1
default: begin
end // default
endcase // rd_address
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
wr_address <= 0;
rd_address <= 0;
entries <= 0;
end
else
case (rdwr) // synthesis parallel_case full_case
2'd1: begin
// Write data
if (!full)
begin
entries <= entries + 1;
wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);
end
end // 2'd1
2'd2: begin
// Read data
if (!empty)
begin
entries <= entries - 1;
rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);
end
end // 2'd2
2'd3: begin
wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);
rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);
end // 2'd3
default: begin
end // default
endcase // rdwr
end
always @(posedge clk)
begin
//Write data
if (wr & !full)
case (wr_address) // synthesis parallel_case full_case
1'd0: begin
entry_0 <= wr_data;
end // 1'd0
1'd1: begin
entry_1 <= wr_data;
end // 1'd1
default: begin
end // default
endcase // wr_address
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module qsys_sdram (
// inputs:
az_addr,
az_be_n,
az_cs,
az_data,
az_rd_n,
az_wr_n,
clk,
reset_n,
// outputs:
za_data,
za_valid,
za_waitrequest,
zs_addr,
zs_ba,
zs_cas_n,
zs_cke,
zs_cs_n,
zs_dq,
zs_dqm,
zs_ras_n,
zs_we_n
)
;
output [ 15: 0] za_data;
output za_valid;
output za_waitrequest;
output [ 12: 0] zs_addr;
output [ 1: 0] zs_ba;
output zs_cas_n;
output zs_cke;
output zs_cs_n;
inout [ 15: 0] zs_dq;
output [ 1: 0] zs_dqm;
output zs_ras_n;
output zs_we_n;
input [ 23: 0] az_addr;
input [ 1: 0] az_be_n;
input az_cs;
input [ 15: 0] az_data;
input az_rd_n;
input az_wr_n;
input clk;
input reset_n;
wire [ 23: 0] CODE;
reg ack_refresh_request;
reg [ 23: 0] active_addr;
wire [ 1: 0] active_bank;
reg active_cs_n;
reg [ 15: 0] active_data;
reg [ 1: 0] active_dqm;
reg active_rnw;
wire almost_empty;
wire almost_full;
wire bank_match;
wire [ 8: 0] cas_addr;
wire clk_en;
wire [ 3: 0] cmd_all;
wire [ 2: 0] cmd_code;
wire cs_n;
wire csn_decode;
wire csn_match;
wire [ 23: 0] f_addr;
wire [ 1: 0] f_bank;
wire f_cs_n;
wire [ 15: 0] f_data;
wire [ 1: 0] f_dqm;
wire f_empty;
reg f_pop;
wire f_rnw;
wire f_select;
wire [ 42: 0] fifo_read_data;
reg [ 12: 0] i_addr;
reg [ 3: 0] i_cmd;
reg [ 2: 0] i_count;
reg [ 2: 0] i_next;
reg [ 2: 0] i_refs;
reg [ 2: 0] i_state;
reg init_done;
reg [ 12: 0] m_addr /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 1: 0] m_bank /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 3: 0] m_cmd /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 2: 0] m_count;
reg [ 15: 0] m_data /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON ; FAST_OUTPUT_ENABLE_REGISTER=ON" */;
reg [ 1: 0] m_dqm /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 8: 0] m_next;
reg [ 8: 0] m_state;
reg oe /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_ENABLE_REGISTER=ON" */;
wire pending;
wire rd_strobe;
reg [ 2: 0] rd_valid;
reg [ 12: 0] refresh_counter;
reg refresh_request;
wire rnw_match;
wire row_match;
wire [ 23: 0] txt_code;
reg za_cannotrefresh;
reg [ 15: 0] za_data /* synthesis ALTERA_ATTRIBUTE = "FAST_INPUT_REGISTER=ON" */;
reg za_valid;
wire za_waitrequest;
wire [ 12: 0] zs_addr;
wire [ 1: 0] zs_ba;
wire zs_cas_n;
wire zs_cke;
wire zs_cs_n;
wire [ 15: 0] zs_dq;
wire [ 1: 0] zs_dqm;
wire zs_ras_n;
wire zs_we_n;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign {zs_cs_n, zs_ras_n, zs_cas_n, zs_we_n} = m_cmd;
assign zs_addr = m_addr;
assign zs_cke = clk_en;
assign zs_dq = oe?m_data:{16{1'bz}};
assign zs_dqm = m_dqm;
assign zs_ba = m_bank;
assign f_select = f_pop & pending;
assign f_cs_n = 1'b0;
assign cs_n = f_select ? f_cs_n : active_cs_n;
assign csn_decode = cs_n;
assign {f_rnw, f_addr, f_dqm, f_data} = fifo_read_data;
qsys_sdram_input_efifo_module the_qsys_sdram_input_efifo_module
(
.almost_empty (almost_empty),
.almost_full (almost_full),
.clk (clk),
.empty (f_empty),
.full (za_waitrequest),
.rd (f_select),
.rd_data (fifo_read_data),
.reset_n (reset_n),
.wr ((~az_wr_n | ~az_rd_n) & !za_waitrequest),
.wr_data ({az_wr_n, az_addr, az_wr_n ? 2'b0 : az_be_n, az_data})
);
assign f_bank = {f_addr[23],f_addr[9]};
// Refresh/init counter.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
refresh_counter <= 5000;
else if (refresh_counter == 0)
refresh_counter <= 781;
else
refresh_counter <= refresh_counter - 1'b1;
end
// Refresh request signal.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
refresh_request <= 0;
else if (1)
refresh_request <= ((refresh_counter == 0) | refresh_request) & ~ack_refresh_request & init_done;
end
// Generate an Interrupt if two ref_reqs occur before one ack_refresh_request
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
za_cannotrefresh <= 0;
else if (1)
za_cannotrefresh <= (refresh_counter == 0) & refresh_request;
end
// Initialization-done flag.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
init_done <= 0;
else if (1)
init_done <= init_done | (i_state == 3'b101);
end
// **** Init FSM ****
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
i_state <= 3'b000;
i_next <= 3'b000;
i_cmd <= 4'b1111;
i_addr <= {13{1'b1}};
i_count <= {3{1'b0}};
end
else
begin
i_addr <= {13{1'b1}};
case (i_state) // synthesis parallel_case full_case
3'b000: begin
i_cmd <= 4'b1111;
i_refs <= 3'b0;
//Wait for refresh count-down after reset
if (refresh_counter == 0)
i_state <= 3'b001;
end // 3'b000
3'b001: begin
i_state <= 3'b011;
i_cmd <= {{1{1'b0}},3'h2};
i_count <= 0;
i_next <= 3'b010;
end // 3'b001
3'b010: begin
i_cmd <= {{1{1'b0}},3'h1};
i_refs <= i_refs + 1'b1;
i_state <= 3'b011;
i_count <= 3;
// Count up init_refresh_commands
if (i_refs == 3'h1)
i_next <= 3'b111;
else
i_next <= 3'b010;
end // 3'b010
3'b011: begin
i_cmd <= {{1{1'b0}},3'h7};
//WAIT til safe to Proceed...
if (i_count > 1)
i_count <= i_count - 1'b1;
else
i_state <= i_next;
end // 3'b011
3'b101: begin
i_state <= 3'b101;
end // 3'b101
3'b111: begin
i_state <= 3'b011;
i_cmd <= {{1{1'b0}},3'h0};
i_addr <= {{3{1'b0}},1'b0,2'b00,3'h3,4'h0};
i_count <= 4;
i_next <= 3'b101;
end // 3'b111
default: begin
i_state <= 3'b000;
end // default
endcase // i_state
end
end
assign active_bank = {active_addr[23],active_addr[9]};
assign csn_match = active_cs_n == f_cs_n;
assign rnw_match = active_rnw == f_rnw;
assign bank_match = active_bank == f_bank;
assign row_match = {active_addr[22 : 10]} == {f_addr[22 : 10]};
assign pending = csn_match && rnw_match && bank_match && row_match && !f_empty;
assign cas_addr = f_select ? { {4{1'b0}},f_addr[8 : 0] } : { {4{1'b0}},active_addr[8 : 0] };
// **** Main FSM ****
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
m_state <= 9'b000000001;
m_next <= 9'b000000001;
m_cmd <= 4'b1111;
m_bank <= 2'b00;
m_addr <= 13'b0000000000000;
m_data <= 16'b0000000000000000;
m_dqm <= 2'b00;
m_count <= 3'b000;
ack_refresh_request <= 1'b0;
f_pop <= 1'b0;
oe <= 1'b0;
end
else
begin
f_pop <= 1'b0;
oe <= 1'b0;
case (m_state) // synthesis parallel_case full_case
9'b000000001: begin
//Wait for init-fsm to be done...
if (init_done)
begin
//Hold bus if another cycle ended to arf.
if (refresh_request)
m_cmd <= {{1{1'b0}},3'h7};
else
m_cmd <= 4'b1111;
ack_refresh_request <= 1'b0;
//Wait for a read/write request.
if (refresh_request)
begin
m_state <= 9'b001000000;
m_next <= 9'b010000000;
m_count <= 0;
active_cs_n <= 1'b1;
end
else if (!f_empty)
begin
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
m_state <= 9'b000000010;
end
end
else
begin
m_addr <= i_addr;
m_state <= 9'b000000001;
m_next <= 9'b000000001;
m_cmd <= i_cmd;
end
end // 9'b000000001
9'b000000010: begin
m_state <= 9'b000000100;
m_cmd <= {csn_decode,3'h3};
m_bank <= active_bank;
m_addr <= active_addr[22 : 10];
m_data <= active_data;
m_dqm <= active_dqm;
m_count <= 1;
m_next <= active_rnw ? 9'b000001000 : 9'b000010000;
end // 9'b000000010
9'b000000100: begin
// precharge all if arf, else precharge csn_decode
if (m_next == 9'b010000000)
m_cmd <= {{1{1'b0}},3'h7};
else
m_cmd <= {csn_decode,3'h7};
//Count down til safe to Proceed...
if (m_count > 1)
m_count <= m_count - 1'b1;
else
m_state <= m_next;
end // 9'b000000100
9'b000001000: begin
m_cmd <= {csn_decode,3'h5};
m_bank <= f_select ? f_bank : active_bank;
m_dqm <= f_select ? f_dqm : active_dqm;
m_addr <= cas_addr;
//Do we have a transaction pending?
if (pending)
begin
//if we need to ARF, bail, else spin
if (refresh_request)
begin
m_state <= 9'b000000100;
m_next <= 9'b000000001;
m_count <= 2;
end
else
begin
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end
end
else
begin
//correctly end RD spin cycle if fifo mt
if (~pending & f_pop)
m_cmd <= {csn_decode,3'h7};
m_state <= 9'b100000000;
end
end // 9'b000001000
9'b000010000: begin
m_cmd <= {csn_decode,3'h4};
oe <= 1'b1;
m_data <= f_select ? f_data : active_data;
m_dqm <= f_select ? f_dqm : active_dqm;
m_bank <= f_select ? f_bank : active_bank;
m_addr <= cas_addr;
//Do we have a transaction pending?
if (pending)
begin
//if we need to ARF, bail, else spin
if (refresh_request)
begin
m_state <= 9'b000000100;
m_next <= 9'b000000001;
m_count <= 1;
end
else
begin
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end
end
else
begin
//correctly end WR spin cycle if fifo empty
if (~pending & f_pop)
begin
m_cmd <= {csn_decode,3'h7};
oe <= 1'b0;
end
m_state <= 9'b100000000;
end
end // 9'b000010000
9'b000100000: begin
m_cmd <= {csn_decode,3'h7};
//Count down til safe to Proceed...
if (m_count > 1)
m_count <= m_count - 1'b1;
else
begin
m_state <= 9'b001000000;
m_count <= 0;
end
end // 9'b000100000
9'b001000000: begin
m_state <= 9'b000000100;
m_addr <= {13{1'b1}};
// precharge all if arf, else precharge csn_decode
if (refresh_request)
m_cmd <= {{1{1'b0}},3'h2};
else
m_cmd <= {csn_decode,3'h2};
end // 9'b001000000
9'b010000000: begin
ack_refresh_request <= 1'b1;
m_state <= 9'b000000100;
m_cmd <= {{1{1'b0}},3'h1};
m_count <= 3;
m_next <= 9'b000000001;
end // 9'b010000000
9'b100000000: begin
m_cmd <= {csn_decode,3'h7};
//if we need to ARF, bail, else spin
if (refresh_request)
begin
m_state <= 9'b000000100;
m_next <= 9'b000000001;
m_count <= 1;
end
else //wait for fifo to have contents
if (!f_empty)
//Are we 'pending' yet?
if (csn_match && rnw_match && bank_match && row_match)
begin
m_state <= f_rnw ? 9'b000001000 : 9'b000010000;
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end
else
begin
m_state <= 9'b000100000;
m_next <= 9'b000000001;
m_count <= 1;
end
end // 9'b100000000
// synthesis translate_off
default: begin
m_state <= m_state;
m_cmd <= 4'b1111;
f_pop <= 1'b0;
oe <= 1'b0;
end // default
// synthesis translate_on
endcase // m_state
end
end
assign rd_strobe = m_cmd[2 : 0] == 3'h5;
//Track RD Req's based on cas_latency w/shift reg
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
rd_valid <= {3{1'b0}};
else
rd_valid <= (rd_valid << 1) | { {2{1'b0}}, rd_strobe };
end
// Register dq data.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
za_data <= 0;
else
za_data <= zs_dq;
end
// Delay za_valid to match registered data.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
za_valid <= 0;
else if (1)
za_valid <= rd_valid[2];
end
assign cmd_code = m_cmd[2 : 0];
assign cmd_all = m_cmd;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
initial
begin
$write("\n");
$write("This reference design requires a vendor simulation model.\n");
$write("To simulate accesses to SDRAM, you must:\n");
$write(" - Download the vendor model\n");
$write(" - Install the model in the system_sim directory\n");
$write(" - `include the vendor model in the the top-level system file,\n");
$write(" - Instantiate sdram simulation models and wire them to testbench signals\n");
$write(" - Be aware that you may have to disable some timing checks in the vendor model\n");
$write(" (because this simulation is zero-delay based)\n");
$write("\n");
end
assign txt_code = (cmd_code == 3'h0)? 24'h4c4d52 :
(cmd_code == 3'h1)? 24'h415246 :
(cmd_code == 3'h2)? 24'h505245 :
(cmd_code == 3'h3)? 24'h414354 :
(cmd_code == 3'h4)? 24'h205752 :
(cmd_code == 3'h5)? 24'h205244 :
(cmd_code == 3'h6)? 24'h425354 :
(cmd_code == 3'h7)? 24'h4e4f50 :
24'h424144;
assign CODE = &(cmd_all|4'h7) ? 24'h494e48 : txt_code;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
|
//-----------------------------------------------------------------------------
//-- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
//--
//-- This file contains confidential and proprietary information
//-- of Xilinx, Inc. and is protected under U.S. and
//-- international copyright and other intellectual property
//-- laws.
//--
//-- DISCLAIMER
//-- This disclaimer is not a license and does not grant any
//-- rights to the materials distributed herewith. Except as
//-- otherwise provided in a valid license issued to you by
//-- Xilinx, and to the maximum extent permitted by applicable
//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
//-- (2) Xilinx shall not be liable (whether in contract or tort,
//-- including negligence, or under any other theory of
//-- liability) for any loss or damage of any kind or nature
//-- related to, arising under or in connection with these
//-- materials, including for any direct, or any indirect,
//-- special, incidental, or consequential loss or damage
//-- (including loss of data, profits, goodwill, or any type of
//-- loss or damage suffered as a result of any action brought
//-- by a third party) even if such damage or loss was
//-- reasonably foreseeable or Xilinx had been advised of the
//-- possibility of the same.
//--
//-- CRITICAL APPLICATIONS
//-- Xilinx products are not designed or intended to be fail-
//-- safe, or for use in any application requiring fail-safe
//-- performance, such as life-support or safety devices or
//-- systems, Class III medical devices, nuclear facilities,
//-- applications related to the deployment of airbags, or any
//-- other applications that could lead to death, personal
//-- injury, or severe property or environmental damage
//-- (individually and collectively, "Critical
//-- Applications"). Customer assumes the sole risk and
//-- liability of any use of Xilinx products in Critical
//-- Applications, subject only to applicable laws and
//-- regulations governing limitations on product liability.
//--
//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
//-- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//Purpose:
// Synchronous, shallow FIFO that uses simple as a DP Memory.
// This requires about 1/2 the resources as a Distributed RAM DPRAM
// implementation.
//
// This FIFO will have the current data on the output when data is contained
// in the FIFO. When the FIFO is empty, the output data is invalid.
//
//Reference:
//Revision History:
//
//-----------------------------------------------
//
// MODULE: axi_mc_simple_fifo
//
// This is the simplest form of inferring the
// simple/SRL(16/32)CE in a Xilinx FPGA.
//
//-----------------------------------------------
`timescale 1ns / 100ps
`default_nettype none
module mig_7series_v4_0_axi_mc_simple_fifo #
(
parameter C_WIDTH = 8,
parameter C_AWIDTH = 4,
parameter C_DEPTH = 16
)
(
input wire clk, // Main System Clock (Sync FIFO)
input wire rst, // FIFO Counter Reset (Clk
input wire wr_en, // FIFO Write Enable (Clk)
input wire rd_en, // FIFO Read Enable (Clk)
input wire [C_WIDTH-1:0] din, // FIFO Data Input (Clk)
output wire [C_WIDTH-1:0] dout, // FIFO Data Output (Clk)
output wire a_full,
output wire full, // FIFO FULL Status (Clk)
output wire a_empty,
output wire empty // FIFO EMPTY Status (Clk)
);
///////////////////////////////////////
// FIFO Local Parameters
///////////////////////////////////////
localparam [C_AWIDTH-1:0] C_EMPTY = ~(0);
localparam [C_AWIDTH-1:0] C_EMPTY_PRE = (0);
localparam [C_AWIDTH-1:0] C_FULL = C_EMPTY-1;
localparam [C_AWIDTH-1:0] C_FULL_PRE = (C_DEPTH < 8) ? C_FULL-1 : C_FULL-(C_DEPTH/8);
///////////////////////////////////////
// FIFO Internal Signals
///////////////////////////////////////
reg [C_WIDTH-1:0] memory [C_DEPTH-1:0];
reg [C_AWIDTH-1:0] cnt_read;
///////////////////////////////////////
// Main simple FIFO Array
///////////////////////////////////////
always @(posedge clk) begin : BLKSRL
integer i;
if (wr_en) begin
for (i = 0; i < C_DEPTH-1; i = i + 1) begin
memory[i+1] <= memory[i];
end
memory[0] <= din;
end
end
///////////////////////////////////////
// Read Index Counter
// Up/Down Counter
// *** Notice that there is no ***
// *** OVERRUN protection. ***
///////////////////////////////////////
always @(posedge clk) begin
if (rst) cnt_read <= C_EMPTY;
else if ( wr_en & !rd_en) cnt_read <= cnt_read + 1'b1;
else if (!wr_en & rd_en) cnt_read <= cnt_read - 1'b1;
end
///////////////////////////////////////
// Status Flags / Outputs
// These could be registered, but would
// increase logic in order to pre-decode
// FULL/EMPTY status.
///////////////////////////////////////
assign full = (cnt_read == C_FULL);
assign empty = (cnt_read == C_EMPTY);
assign a_full = ((cnt_read >= C_FULL_PRE) && (cnt_read != C_EMPTY));
assign a_empty = (cnt_read == C_EMPTY_PRE);
assign dout = (C_DEPTH == 1) ? memory[0] : memory[cnt_read];
endmodule // axi_mc_simple_fifo
`default_nettype wire
|
/*
Copyright (c) 2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* FPGA top-level module
*/
module fpga (
/*
* Clock: 125MHz LVDS
* Reset: Push button, active low
*/
input wire clk_125mhz_p,
input wire clk_125mhz_n,
input wire reset,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [3:0] sw,
output wire [7:0] led,
/*
* I2C for board management
*/
inout wire i2c_scl,
inout wire i2c_sda,
/*
* Ethernet: QSFP28
*/
input wire qsfp_rx1_p,
input wire qsfp_rx1_n,
input wire qsfp_rx2_p,
input wire qsfp_rx2_n,
input wire qsfp_rx3_n,
input wire qsfp_rx3_p,
input wire qsfp_rx4_p,
input wire qsfp_rx4_n,
output wire qsfp_tx1_p,
output wire qsfp_tx1_n,
output wire qsfp_tx2_p,
output wire qsfp_tx2_n,
output wire qsfp_tx3_p,
output wire qsfp_tx3_n,
output wire qsfp_tx4_p,
output wire qsfp_tx4_n,
input wire qsfp_mgt_refclk_0_p,
input wire qsfp_mgt_refclk_0_n,
// input wire qsfp_mgt_refclk_1_p,
// input wire qsfp_mgt_refclk_1_n,
// output wire qsfp_recclk_p,
// output wire qsfp_recclk_n,
output wire qsfp_modsell,
output wire qsfp_resetl,
input wire qsfp_modprsl,
input wire qsfp_intl,
output wire qsfp_lpmode,
/*
* Ethernet: CFP2 GTY
*/
input wire cfp2_rx0_p,
input wire cfp2_rx0_n,
input wire cfp2_rx1_p,
input wire cfp2_rx1_n,
input wire cfp2_rx2_n,
input wire cfp2_rx2_p,
input wire cfp2_rx3_p,
input wire cfp2_rx3_n,
input wire cfp2_rx4_p,
input wire cfp2_rx4_n,
input wire cfp2_rx5_p,
input wire cfp2_rx5_n,
input wire cfp2_rx6_p,
input wire cfp2_rx6_n,
input wire cfp2_rx7_p,
input wire cfp2_rx7_n,
input wire cfp2_rx8_p,
input wire cfp2_rx8_n,
input wire cfp2_rx9_p,
input wire cfp2_rx9_n,
output wire cfp2_tx0_p,
output wire cfp2_tx0_n,
output wire cfp2_tx1_p,
output wire cfp2_tx1_n,
output wire cfp2_tx2_p,
output wire cfp2_tx2_n,
output wire cfp2_tx3_p,
output wire cfp2_tx3_n,
output wire cfp2_tx4_p,
output wire cfp2_tx4_n,
output wire cfp2_tx5_p,
output wire cfp2_tx5_n,
output wire cfp2_tx6_p,
output wire cfp2_tx6_n,
output wire cfp2_tx7_p,
output wire cfp2_tx7_n,
output wire cfp2_tx8_p,
output wire cfp2_tx8_n,
output wire cfp2_tx9_p,
output wire cfp2_tx9_n,
input wire cfp2_mgt_refclk_0_p,
input wire cfp2_mgt_refclk_0_n,
//input wire cfp2_mgt_refclk_1_p,
//input wire cfp2_mgt_refclk_1_n,
output wire [2:0] cfp2_prg_cntl,
input wire [2:0] cfp2_prg_alrm,
output wire [2:0] cfp2_prtadr,
output wire cfp2_tx_dis,
input wire cfp2_rx_los,
output wire cfp2_mod_lopwr,
output wire cfp2_mod_rstn,
input wire cfp2_mod_abs,
input wire cfp2_glb_alrmn,
output wire cfp2_mdc,
inout wire cfp2_mdio,
/*
* Bullseye GTY
*/
input wire bullseye_rx0_p,
input wire bullseye_rx0_n,
input wire bullseye_rx1_p,
input wire bullseye_rx1_n,
input wire bullseye_rx2_n,
input wire bullseye_rx2_p,
input wire bullseye_rx3_p,
input wire bullseye_rx3_n,
output wire bullseye_tx0_p,
output wire bullseye_tx0_n,
output wire bullseye_tx1_p,
output wire bullseye_tx1_n,
output wire bullseye_tx2_p,
output wire bullseye_tx2_n,
output wire bullseye_tx3_p,
output wire bullseye_tx3_n,
// input wire bullseye_mgt_refclk_0_p,
// input wire bullseye_mgt_refclk_0_n,
input wire bullseye_mgt_refclk_1_p,
input wire bullseye_mgt_refclk_1_n,
/*
* Ethernet: 1000BASE-T SGMII
*/
input wire phy_sgmii_rx_p,
input wire phy_sgmii_rx_n,
output wire phy_sgmii_tx_p,
output wire phy_sgmii_tx_n,
input wire phy_sgmii_clk_p,
input wire phy_sgmii_clk_n,
output wire phy_reset_n,
input wire phy_int_n,
/*
* UART: 115200 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd,
output wire uart_rts,
input wire uart_cts
);
// Clock and reset
wire clk_125mhz_ibufg;
wire clk_125mhz_mmcm_out;
wire clk_62mhz_mmcm_out;
// Internal 125 MHz clock
wire clk_125mhz_int;
wire rst_125mhz_int;
// Internal 62.5 MHz clock
wire clk_62mhz_int;
wire rst_62mhz_int;
wire mmcm_rst = reset;
wire mmcm_locked;
wire mmcm_clkfb;
IBUFGDS #(
.DIFF_TERM("FALSE"),
.IBUF_LOW_PWR("FALSE")
)
clk_125mhz_ibufg_inst (
.O (clk_125mhz_ibufg),
.I (clk_125mhz_p),
.IB (clk_125mhz_n)
);
// MMCM instance
// 125 MHz in, 125 MHz and 62.5 MHz out
// PFD range: 10 MHz to 500 MHz
// VCO range: 600 MHz to 1440 MHz
// M = 5, D = 1 sets Fvco = 625 MHz (in range)
// Divide by 5 to get output frequency of 125 MHz
// Divide by 10 to get output frequency of 62.5 MHz
MMCME3_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKOUT0_DIVIDE_F(5),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0),
.CLKOUT1_DIVIDE(10),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(0),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT6_PHASE(0),
.CLKFBOUT_MULT_F(5),
.CLKFBOUT_PHASE(0),
.DIVCLK_DIVIDE(1),
.REF_JITTER1(0.010),
.CLKIN1_PERIOD(8.0),
.STARTUP_WAIT("FALSE"),
.CLKOUT4_CASCADE("FALSE")
)
clk_mmcm_inst (
.CLKIN1(clk_125mhz_ibufg),
.CLKFBIN(mmcm_clkfb),
.RST(mmcm_rst),
.PWRDWN(1'b0),
.CLKOUT0(clk_125mhz_mmcm_out),
.CLKOUT0B(),
.CLKOUT1(clk_62mhz_mmcm_out),
.CLKOUT1B(),
.CLKOUT2(),
.CLKOUT2B(),
.CLKOUT3(),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.CLKFBOUT(mmcm_clkfb),
.CLKFBOUTB(),
.LOCKED(mmcm_locked)
);
BUFG
clk_125mhz_bufg_inst (
.I(clk_125mhz_mmcm_out),
.O(clk_125mhz_int)
);
BUFG
clk_62mhz_bufg_inst (
.I(clk_62mhz_mmcm_out),
.O(clk_62mhz_int)
);
sync_reset #(
.N(4)
)
sync_reset_125mhz_inst (
.clk(clk_125mhz_int),
.rst(~mmcm_locked),
.out(rst_125mhz_int)
);
sync_reset #(
.N(4)
)
sync_reset_62mhz_inst (
.clk(clk_62mhz_int),
.rst(~mmcm_locked),
.out(rst_62mhz_int)
);
// GPIO
wire btnu_int;
wire btnl_int;
wire btnd_int;
wire btnr_int;
wire btnc_int;
wire [3:0] sw_int;
debounce_switch #(
.WIDTH(9),
.N(4),
.RATE(125000)
)
debounce_switch_inst (
.clk(clk_125mhz_int),
.rst(rst_125mhz_int),
.in({btnu,
btnl,
btnd,
btnr,
btnc,
sw}),
.out({btnu_int,
btnl_int,
btnd_int,
btnr_int,
btnc_int,
sw_int})
);
wire uart_rxd_int;
wire uart_cts_int;
sync_signal #(
.WIDTH(2),
.N(2)
)
sync_signal_inst (
.clk(clk_125mhz_int),
.in({uart_rxd, uart_cts}),
.out({uart_rxd_int, uart_cts_int})
);
wire i2c_scl_i;
wire i2c_scl_o;
wire i2c_scl_t;
wire i2c_sda_i;
wire i2c_sda_o;
wire i2c_sda_t;
assign i2c_scl_i = i2c_scl;
assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o;
assign i2c_sda_i = i2c_sda;
assign i2c_sda = i2c_sda_t ? 1'bz : i2c_sda_o;
// GTY instances
wire gty_drp_clk = clk_62mhz_int;
wire gty_drp_rst = rst_62mhz_int;
wire [7:0] xfcp_mgt_up_tdata;
wire xfcp_mgt_up_tvalid;
wire xfcp_mgt_up_tready;
wire xfcp_mgt_up_tlast;
wire xfcp_mgt_up_tuser;
wire [7:0] xfcp_mgt_down_tdata;
wire xfcp_mgt_down_tvalid;
wire xfcp_mgt_down_tready;
wire xfcp_mgt_down_tlast;
wire xfcp_mgt_down_tuser;
wire [7:0] xfcp_mgt_fifo_up_tdata;
wire xfcp_mgt_fifo_up_tvalid;
wire xfcp_mgt_fifo_up_tready;
wire xfcp_mgt_fifo_up_tlast;
wire xfcp_mgt_fifo_up_tuser;
wire [7:0] xfcp_mgt_fifo_down_tdata;
wire xfcp_mgt_fifo_down_tvalid;
wire xfcp_mgt_fifo_down_tready;
wire xfcp_mgt_fifo_down_tlast;
wire xfcp_mgt_fifo_down_tuser;
wire [7:0] xfcp_qsfp_gty_up_tdata;
wire xfcp_qsfp_gty_up_tvalid;
wire xfcp_qsfp_gty_up_tready;
wire xfcp_qsfp_gty_up_tlast;
wire xfcp_qsfp_gty_up_tuser;
wire [7:0] xfcp_qsfp_gty_down_tdata;
wire xfcp_qsfp_gty_down_tvalid;
wire xfcp_qsfp_gty_down_tready;
wire xfcp_qsfp_gty_down_tlast;
wire xfcp_qsfp_gty_down_tuser;
wire [7:0] xfcp_cfp2_gty_1_up_tdata;
wire xfcp_cfp2_gty_1_up_tvalid;
wire xfcp_cfp2_gty_1_up_tready;
wire xfcp_cfp2_gty_1_up_tlast;
wire xfcp_cfp2_gty_1_up_tuser;
wire [7:0] xfcp_cfp2_gty_1_down_tdata;
wire xfcp_cfp2_gty_1_down_tvalid;
wire xfcp_cfp2_gty_1_down_tready;
wire xfcp_cfp2_gty_1_down_tlast;
wire xfcp_cfp2_gty_1_down_tuser;
wire [7:0] xfcp_cfp2_gty_2_up_tdata;
wire xfcp_cfp2_gty_2_up_tvalid;
wire xfcp_cfp2_gty_2_up_tready;
wire xfcp_cfp2_gty_2_up_tlast;
wire xfcp_cfp2_gty_2_up_tuser;
wire [7:0] xfcp_cfp2_gty_2_down_tdata;
wire xfcp_cfp2_gty_2_down_tvalid;
wire xfcp_cfp2_gty_2_down_tready;
wire xfcp_cfp2_gty_2_down_tlast;
wire xfcp_cfp2_gty_2_down_tuser;
wire [7:0] xfcp_cfp2_gty_3_up_tdata;
wire xfcp_cfp2_gty_3_up_tvalid;
wire xfcp_cfp2_gty_3_up_tready;
wire xfcp_cfp2_gty_3_up_tlast;
wire xfcp_cfp2_gty_3_up_tuser;
wire [7:0] xfcp_cfp2_gty_3_down_tdata;
wire xfcp_cfp2_gty_3_down_tvalid;
wire xfcp_cfp2_gty_3_down_tready;
wire xfcp_cfp2_gty_3_down_tlast;
wire xfcp_cfp2_gty_3_down_tuser;
wire [7:0] xfcp_bullseye_gty_up_tdata;
wire xfcp_bullseye_gty_up_tvalid;
wire xfcp_bullseye_gty_up_tready;
wire xfcp_bullseye_gty_up_tlast;
wire xfcp_bullseye_gty_up_tuser;
wire [7:0] xfcp_bullseye_gty_down_tdata;
wire xfcp_bullseye_gty_down_tvalid;
wire xfcp_bullseye_gty_down_tready;
wire xfcp_bullseye_gty_down_tlast;
wire xfcp_bullseye_gty_down_tuser;
axis_async_fifo #(
.DEPTH(32),
.DATA_WIDTH(8)
)
xfcp_mgt_fifo_down (
// Common reset
.async_rst(rst_125mhz_int | gty_drp_rst),
// AXI input
.s_clk(clk_125mhz_int),
.s_axis_tdata(xfcp_mgt_down_tdata),
.s_axis_tvalid(xfcp_mgt_down_tvalid),
.s_axis_tready(xfcp_mgt_down_tready),
.s_axis_tlast(xfcp_mgt_down_tlast),
.s_axis_tuser(xfcp_mgt_down_tuser),
// AXI output
.m_clk(gty_drp_clk),
.m_axis_tdata(xfcp_mgt_fifo_down_tdata),
.m_axis_tvalid(xfcp_mgt_fifo_down_tvalid),
.m_axis_tready(xfcp_mgt_fifo_down_tready),
.m_axis_tlast(xfcp_mgt_fifo_down_tlast),
.m_axis_tuser(xfcp_mgt_fifo_down_tuser)
);
axis_async_fifo #(
.DEPTH(32),
.DATA_WIDTH(8)
)
xfcp_mgt_fifo_up (
// Common reset
.async_rst(rst_125mhz_int | gty_drp_rst),
// AXI input
.s_clk(gty_drp_clk),
.s_axis_tdata(xfcp_mgt_fifo_up_tdata),
.s_axis_tvalid(xfcp_mgt_fifo_up_tvalid),
.s_axis_tready(xfcp_mgt_fifo_up_tready),
.s_axis_tlast(xfcp_mgt_fifo_up_tlast),
.s_axis_tuser(xfcp_mgt_fifo_up_tuser),
// AXI output
.m_clk(clk_125mhz_int),
.m_axis_tdata(xfcp_mgt_up_tdata),
.m_axis_tvalid(xfcp_mgt_up_tvalid),
.m_axis_tready(xfcp_mgt_up_tready),
.m_axis_tlast(xfcp_mgt_up_tlast),
.m_axis_tuser(xfcp_mgt_up_tuser)
);
xfcp_switch #(
.PORTS(5),
.XFCP_ID_TYPE(16'h0100),
.XFCP_ID_STR("XFCP switch"),
.XFCP_EXT_ID(0),
.XFCP_EXT_ID_STR("GTY QUADs")
)
xfcp_switch_inst (
.clk(gty_drp_clk),
.rst(gty_drp_rst),
.up_xfcp_in_tdata(xfcp_mgt_fifo_down_tdata),
.up_xfcp_in_tvalid(xfcp_mgt_fifo_down_tvalid),
.up_xfcp_in_tready(xfcp_mgt_fifo_down_tready),
.up_xfcp_in_tlast(xfcp_mgt_fifo_down_tlast),
.up_xfcp_in_tuser(xfcp_mgt_fifo_down_tuser),
.up_xfcp_out_tdata(xfcp_mgt_fifo_up_tdata),
.up_xfcp_out_tvalid(xfcp_mgt_fifo_up_tvalid),
.up_xfcp_out_tready(xfcp_mgt_fifo_up_tready),
.up_xfcp_out_tlast(xfcp_mgt_fifo_up_tlast),
.up_xfcp_out_tuser(xfcp_mgt_fifo_up_tuser),
.down_xfcp_in_tdata( {xfcp_bullseye_gty_up_tdata, xfcp_cfp2_gty_3_up_tdata, xfcp_cfp2_gty_2_up_tdata, xfcp_cfp2_gty_1_up_tdata, xfcp_qsfp_gty_up_tdata }),
.down_xfcp_in_tvalid( {xfcp_bullseye_gty_up_tvalid, xfcp_cfp2_gty_3_up_tvalid, xfcp_cfp2_gty_2_up_tvalid, xfcp_cfp2_gty_1_up_tvalid, xfcp_qsfp_gty_up_tvalid }),
.down_xfcp_in_tready( {xfcp_bullseye_gty_up_tready, xfcp_cfp2_gty_3_up_tready, xfcp_cfp2_gty_2_up_tready, xfcp_cfp2_gty_1_up_tready, xfcp_qsfp_gty_up_tready }),
.down_xfcp_in_tlast( {xfcp_bullseye_gty_up_tlast, xfcp_cfp2_gty_3_up_tlast, xfcp_cfp2_gty_2_up_tlast, xfcp_cfp2_gty_1_up_tlast, xfcp_qsfp_gty_up_tlast }),
.down_xfcp_in_tuser( {xfcp_bullseye_gty_up_tuser, xfcp_cfp2_gty_3_up_tuser, xfcp_cfp2_gty_2_up_tuser, xfcp_cfp2_gty_1_up_tuser, xfcp_qsfp_gty_up_tuser }),
.down_xfcp_out_tdata( {xfcp_bullseye_gty_down_tdata, xfcp_cfp2_gty_3_down_tdata, xfcp_cfp2_gty_2_down_tdata, xfcp_cfp2_gty_1_down_tdata, xfcp_qsfp_gty_down_tdata }),
.down_xfcp_out_tvalid({xfcp_bullseye_gty_down_tvalid, xfcp_cfp2_gty_3_down_tvalid, xfcp_cfp2_gty_2_down_tvalid, xfcp_cfp2_gty_1_down_tvalid, xfcp_qsfp_gty_down_tvalid}),
.down_xfcp_out_tready({xfcp_bullseye_gty_down_tready, xfcp_cfp2_gty_3_down_tready, xfcp_cfp2_gty_2_down_tready, xfcp_cfp2_gty_1_down_tready, xfcp_qsfp_gty_down_tready}),
.down_xfcp_out_tlast( {xfcp_bullseye_gty_down_tlast, xfcp_cfp2_gty_3_down_tlast, xfcp_cfp2_gty_2_down_tlast, xfcp_cfp2_gty_1_down_tlast, xfcp_qsfp_gty_down_tlast }),
.down_xfcp_out_tuser( {xfcp_bullseye_gty_down_tuser, xfcp_cfp2_gty_3_down_tuser, xfcp_cfp2_gty_2_down_tuser, xfcp_cfp2_gty_1_down_tuser, xfcp_qsfp_gty_down_tuser })
);
// QSFP GTY
assign qsfp_modsell = 1'b0;
assign qsfp_resetl = 1'b1;
assign qsfp_lpmode = 1'b0;
wire [9:0] qsfp_gty_com_drp_addr;
wire [15:0] qsfp_gty_com_drp_do;
wire [15:0] qsfp_gty_com_drp_di;
wire qsfp_gty_com_drp_en;
wire qsfp_gty_com_drp_we;
wire qsfp_gty_com_drp_rdy;
wire [4*10-1:0] qsfp_gty_drp_addr;
wire [4*16-1:0] qsfp_gty_drp_do;
wire [4*16-1:0] qsfp_gty_drp_di;
wire [4-1:0] qsfp_gty_drp_en;
wire [4-1:0] qsfp_gty_drp_we;
wire [4-1:0] qsfp_gty_drp_rdy;
wire [4-1:0] qsfp_gty_reset;
wire [4-1:0] qsfp_gty_tx_pcs_reset;
wire [4-1:0] qsfp_gty_tx_pma_reset;
wire [4-1:0] qsfp_gty_rx_pcs_reset;
wire [4-1:0] qsfp_gty_rx_pma_reset;
wire [4-1:0] qsfp_gty_rx_dfe_lpm_reset;
wire [4-1:0] qsfp_gty_eyescan_reset;
wire [4-1:0] qsfp_gty_tx_reset_done;
wire [4-1:0] qsfp_gty_tx_pma_reset_done;
wire [4-1:0] qsfp_gty_rx_reset_done;
wire [4-1:0] qsfp_gty_rx_pma_reset_done;
wire qsfp_gty_txusrclk2;
wire [4*4-1:0] qsfp_gty_txprbssel;
wire [4-1:0] qsfp_gty_txprbsforceerr;
wire [4-1:0] qsfp_gty_txpolarity;
wire [4-1:0] qsfp_gty_txelecidle;
wire [4-1:0] qsfp_gty_txinhibit;
wire [4*5-1:0] qsfp_gty_txdiffctrl;
wire [4*7-1:0] qsfp_gty_txmaincursor;
wire [4*5-1:0] qsfp_gty_txpostcursor;
wire [4*5-1:0] qsfp_gty_txprecursor;
wire qsfp_gty_rxusrclk2;
wire [4-1:0] qsfp_gty_rxpolarity;
wire [4-1:0] qsfp_gty_rxprbscntreset;
wire [4*4-1:0] qsfp_gty_rxprbssel;
wire [4-1:0] qsfp_gty_rxprbserr;
wire [4-1:0] qsfp_gty_rxprbslocked;
xfcp_gty_quad #(
.CH(4),
.SW_XFCP_ID_TYPE(16'h0100),
.SW_XFCP_ID_STR("GTY QUAD 127"),
.SW_XFCP_EXT_ID(0),
.SW_XFCP_EXT_ID_STR("QSFP GTY QUAD"),
.COM_XFCP_ID_TYPE(16'h8A82),
.COM_XFCP_ID_STR("GTY COM X0Y3"),
.COM_XFCP_EXT_ID(0),
.COM_XFCP_EXT_ID_STR("QSFP GTY COM"),
.CH_0_XFCP_ID_TYPE(16'h8A83),
.CH_0_XFCP_ID_STR("GTY CH0 X0Y12"),
.CH_0_XFCP_EXT_ID(0),
.CH_0_XFCP_EXT_ID_STR("QSFP CH1"),
.CH_1_XFCP_ID_TYPE(16'h8A83),
.CH_1_XFCP_ID_STR("GTY CH1 X0Y13"),
.CH_1_XFCP_EXT_ID(0),
.CH_1_XFCP_EXT_ID_STR("QSFP CH2"),
.CH_2_XFCP_ID_TYPE(16'h8A83),
.CH_2_XFCP_ID_STR("GTY CH2 X0Y14"),
.CH_2_XFCP_EXT_ID(0),
.CH_2_XFCP_EXT_ID_STR("QSFP CH3"),
.CH_3_XFCP_ID_TYPE(16'h8A83),
.CH_3_XFCP_ID_STR("GTY CH3 X0Y15"),
.CH_3_XFCP_EXT_ID(0),
.CH_3_XFCP_EXT_ID_STR("QSFP CH4"),
.COM_ADDR_WIDTH(10),
.CH_ADDR_WIDTH(10)
)
xfcp_qsfp_gty_quad_inst (
.clk(gty_drp_clk),
.rst(gty_drp_rst),
.up_xfcp_in_tdata(xfcp_qsfp_gty_down_tdata),
.up_xfcp_in_tvalid(xfcp_qsfp_gty_down_tvalid),
.up_xfcp_in_tready(xfcp_qsfp_gty_down_tready),
.up_xfcp_in_tlast(xfcp_qsfp_gty_down_tlast),
.up_xfcp_in_tuser(xfcp_qsfp_gty_down_tuser),
.up_xfcp_out_tdata(xfcp_qsfp_gty_up_tdata),
.up_xfcp_out_tvalid(xfcp_qsfp_gty_up_tvalid),
.up_xfcp_out_tready(xfcp_qsfp_gty_up_tready),
.up_xfcp_out_tlast(xfcp_qsfp_gty_up_tlast),
.up_xfcp_out_tuser(xfcp_qsfp_gty_up_tuser),
.gty_com_drp_addr(qsfp_gty_com_drp_addr),
.gty_com_drp_do(qsfp_gty_com_drp_do),
.gty_com_drp_di(qsfp_gty_com_drp_di),
.gty_com_drp_en(qsfp_gty_com_drp_en),
.gty_com_drp_we(qsfp_gty_com_drp_we),
.gty_com_drp_rdy(qsfp_gty_com_drp_rdy),
.gty_drp_addr(qsfp_gty_drp_addr),
.gty_drp_do(qsfp_gty_drp_do),
.gty_drp_di(qsfp_gty_drp_di),
.gty_drp_en(qsfp_gty_drp_en),
.gty_drp_we(qsfp_gty_drp_we),
.gty_drp_rdy(qsfp_gty_drp_rdy),
.gty_reset(qsfp_gty_reset),
.gty_tx_pcs_reset(qsfp_gty_tx_pcs_reset),
.gty_tx_pma_reset(qsfp_gty_tx_pma_reset),
.gty_rx_pcs_reset(qsfp_gty_rx_pcs_reset),
.gty_rx_pma_reset(qsfp_gty_rx_pma_reset),
.gty_rx_dfe_lpm_reset(qsfp_gty_rx_dfe_lpm_reset),
.gty_eyescan_reset(qsfp_gty_eyescan_reset),
.gty_tx_reset_done(qsfp_gty_tx_reset_done),
.gty_tx_pma_reset_done(qsfp_gty_tx_pma_reset_done),
.gty_rx_reset_done(qsfp_gty_rx_reset_done),
.gty_rx_pma_reset_done(qsfp_gty_rx_pma_reset_done),
.gty_txusrclk2({4{qsfp_gty_txusrclk2}}),
.gty_txprbssel(qsfp_gty_txprbssel),
.gty_txprbsforceerr(qsfp_gty_txprbsforceerr),
.gty_txpolarity(qsfp_gty_txpolarity),
.gty_txelecidle(qsfp_gty_txelecidle),
.gty_txinhibit(qsfp_gty_txinhibit),
.gty_txdiffctrl(qsfp_gty_txdiffctrl),
.gty_txmaincursor(qsfp_gty_txmaincursor),
.gty_txpostcursor(qsfp_gty_txpostcursor),
.gty_txprecursor(qsfp_gty_txprecursor),
.gty_rxusrclk2({4{qsfp_gty_rxusrclk2}}),
.gty_rxpolarity(qsfp_gty_rxpolarity),
.gty_rxprbscntreset(qsfp_gty_rxprbscntreset),
.gty_rxprbssel(qsfp_gty_rxprbssel),
.gty_rxprbserr(qsfp_gty_rxprbserr),
.gty_rxprbslocked(qsfp_gty_rxprbslocked)
);
wire qsfp_mgt_refclk_0;
IBUFDS_GTE3 ibufds_gte3_qsfp_mgt_refclk_0_inst (
.I (qsfp_mgt_refclk_0_p),
.IB (qsfp_mgt_refclk_0_n),
.CEB (1'b0),
.O (qsfp_mgt_refclk_0),
.ODIV2 ()
);
gtwizard_ultrascale_0 gtwizard_ultrascale_0_inst (
.gtyrxn_in ({qsfp_rx4_n, qsfp_rx3_n, qsfp_rx2_n, qsfp_rx1_n}),
.gtyrxp_in ({qsfp_rx4_p, qsfp_rx3_p, qsfp_rx2_p, qsfp_rx1_p}),
.gtytxn_out ({qsfp_tx4_n, qsfp_tx3_n, qsfp_tx2_n, qsfp_tx1_n}),
.gtytxp_out ({qsfp_tx4_p, qsfp_tx3_p, qsfp_tx2_p, qsfp_tx1_p}),
.gtwiz_userclk_tx_reset_in (gty_drp_rst),
.gtwiz_userclk_tx_srcclk_out (),
.gtwiz_userclk_tx_usrclk_out (),
.gtwiz_userclk_tx_usrclk2_out (qsfp_gty_txusrclk2),
.gtwiz_userclk_tx_active_out (),
.gtwiz_userclk_rx_reset_in (gty_drp_rst),
.gtwiz_userclk_rx_srcclk_out (),
.gtwiz_userclk_rx_usrclk_out (),
.gtwiz_userclk_rx_usrclk2_out (qsfp_gty_rxusrclk2),
.gtwiz_userclk_rx_active_out (),
.gtwiz_reset_clk_freerun_in (gty_drp_clk),
.gtwiz_reset_all_in (gty_drp_rst || qsfp_gty_reset),
.gtwiz_reset_tx_pll_and_datapath_in (1'b0),
.gtwiz_reset_tx_datapath_in (1'b0),
.gtwiz_reset_rx_pll_and_datapath_in (1'b0),
.gtwiz_reset_rx_datapath_in (1'b0),
.gtwiz_reset_rx_cdr_stable_out (),
.gtwiz_reset_tx_done_out (),
.gtwiz_reset_rx_done_out (),
.gtwiz_userdata_tx_in ({4{64'd0}}),
.gtwiz_userdata_rx_out (),
.drpaddr_common_in (qsfp_gty_com_drp_addr),
.drpclk_common_in (gty_drp_clk),
.drpdi_common_in (qsfp_gty_com_drp_do),
.drpen_common_in (qsfp_gty_com_drp_en),
.drpwe_common_in (qsfp_gty_com_drp_we),
.gtrefclk00_in (qsfp_mgt_refclk_0),
.drpdo_common_out (qsfp_gty_com_drp_di),
.drprdy_common_out (qsfp_gty_com_drp_rdy),
.qpll0outclk_out (),
.qpll0outrefclk_out (),
.drpaddr_in (qsfp_gty_drp_addr),
.drpclk_in ({4{gty_drp_clk}}),
.drpdi_in (qsfp_gty_drp_do),
.drpen_in (qsfp_gty_drp_en),
.drpwe_in (qsfp_gty_drp_we),
.rxpolarity_in (qsfp_gty_rxpolarity),
.rxprbscntreset_in (qsfp_gty_rxprbscntreset),
.rxprbssel_in (qsfp_gty_rxprbssel),
.txdiffctrl_in (qsfp_gty_txdiffctrl),
.txelecidle_in (qsfp_gty_txelecidle),
.txinhibit_in (qsfp_gty_txinhibit),
.txmaincursor_in (qsfp_gty_txmaincursor),
.txpolarity_in (qsfp_gty_txpolarity),
.txpostcursor_in (qsfp_gty_txpostcursor),
.txprbsforceerr_in (qsfp_gty_txprbsforceerr),
.txprbssel_in (qsfp_gty_txprbssel),
.txprecursor_in (qsfp_gty_txprecursor),
.drpdo_out (qsfp_gty_drp_di),
.drprdy_out (qsfp_gty_drp_rdy),
.gtpowergood_out (),
.eyescandataerror_out (),
.rxprbserr_out (qsfp_gty_rxprbserr),
.rxprbslocked_out (qsfp_gty_rxprbslocked),
.rxpcsreset_in (qsfp_gty_rx_pcs_reset),
.rxpmareset_in (qsfp_gty_rx_pma_reset),
.rxdfelpmreset_in (qsfp_gty_rx_dfe_lpm_reset),
.eyescanreset_in (qsfp_gty_eyescan_reset),
.rxpmaresetdone_out (qsfp_gty_rx_pma_reset_done),
.rxprgdivresetdone_out (),
.rxresetdone_out (qsfp_gty_rx_reset_done),
.txpcsreset_in (qsfp_gty_tx_pcs_reset),
.txpmareset_in (qsfp_gty_tx_pma_reset),
.txpmaresetdone_out (qsfp_gty_tx_pma_reset_done),
.txprgdivresetdone_out (),
.txresetdone_out (qsfp_gty_tx_reset_done)
);
// CFP2 GTY
assign cfp2_prg_cntl = 3'b111;
assign cfp2_prtadr = 3'b000;
assign cfp2_tx_dis = 1'b0;
assign cfp2_mod_lopwr = 1'b0;
assign cfp2_mod_rstn = 1'b1;
assign cfp2_mdc = 1'b0;
assign cfp2_mdio = 1'bz;
wire [3*10-1:0] cfp2_gty_com_drp_addr;
wire [3*16-1:0] cfp2_gty_com_drp_do;
wire [3*16-1:0] cfp2_gty_com_drp_di;
wire [3-1:0] cfp2_gty_com_drp_en;
wire [3-1:0] cfp2_gty_com_drp_we;
wire [3-1:0] cfp2_gty_com_drp_rdy;
wire [10*10-1:0] cfp2_gty_drp_addr;
wire [10*16-1:0] cfp2_gty_drp_do;
wire [10*16-1:0] cfp2_gty_drp_di;
wire [10-1:0] cfp2_gty_drp_en;
wire [10-1:0] cfp2_gty_drp_we;
wire [10-1:0] cfp2_gty_drp_rdy;
wire [10-1:0] cfp2_gty_reset;
wire [10-1:0] cfp2_gty_tx_pcs_reset;
wire [10-1:0] cfp2_gty_tx_pma_reset;
wire [10-1:0] cfp2_gty_rx_pcs_reset;
wire [10-1:0] cfp2_gty_rx_pma_reset;
wire [10-1:0] cfp2_gty_rx_dfe_lpm_reset;
wire [10-1:0] cfp2_gty_eyescan_reset;
wire [10-1:0] cfp2_gty_tx_reset_done;
wire [10-1:0] cfp2_gty_tx_pma_reset_done;
wire [10-1:0] cfp2_gty_rx_reset_done;
wire [10-1:0] cfp2_gty_rx_pma_reset_done;
wire cfp2_gty_txusrclk2;
wire [10*4-1:0] cfp2_gty_txprbssel;
wire [10-1:0] cfp2_gty_txprbsforceerr;
wire [10-1:0] cfp2_gty_txpolarity;
wire [10-1:0] cfp2_gty_txelecidle;
wire [10-1:0] cfp2_gty_txinhibit;
wire [10*5-1:0] cfp2_gty_txdiffctrl;
wire [10*7-1:0] cfp2_gty_txmaincursor;
wire [10*5-1:0] cfp2_gty_txpostcursor;
wire [10*5-1:0] cfp2_gty_txprecursor;
wire cfp2_gty_rxusrclk2;
wire [10-1:0] cfp2_gty_rxpolarity;
wire [10-1:0] cfp2_gty_rxprbscntreset;
wire [10*4-1:0] cfp2_gty_rxprbssel;
wire [10-1:0] cfp2_gty_rxprbserr;
wire [10-1:0] cfp2_gty_rxprbslocked;
xfcp_gty_quad #(
.CH(4),
.SW_XFCP_ID_TYPE(16'h0100),
.SW_XFCP_ID_STR("GTY QUAD 128"),
.SW_XFCP_EXT_ID(0),
.SW_XFCP_EXT_ID_STR("CFP2 GTY QUAD"),
.COM_XFCP_ID_TYPE(16'h8A82),
.COM_XFCP_ID_STR("GTY COM X0Y4"),
.COM_XFCP_EXT_ID(0),
.COM_XFCP_EXT_ID_STR("CFP2 GTY COM"),
.CH_0_XFCP_ID_TYPE(16'h8A83),
.CH_0_XFCP_ID_STR("GTY CH0 X0Y16"),
.CH_0_XFCP_EXT_ID(0),
.CH_0_XFCP_EXT_ID_STR("CFP2 CH9"),
.CH_1_XFCP_ID_TYPE(16'h8A83),
.CH_1_XFCP_ID_STR("GTY CH1 X0Y17"),
.CH_1_XFCP_EXT_ID(0),
.CH_1_XFCP_EXT_ID_STR("CFP2 CH8"),
.CH_2_XFCP_ID_TYPE(16'h8A83),
.CH_2_XFCP_ID_STR("GTY CH2 X0Y18"),
.CH_2_XFCP_EXT_ID(0),
.CH_2_XFCP_EXT_ID_STR("CFP2 CH7"),
.CH_3_XFCP_ID_TYPE(16'h8A83),
.CH_3_XFCP_ID_STR("GTY CH3 X0Y19"),
.CH_3_XFCP_EXT_ID(0),
.CH_3_XFCP_EXT_ID_STR("CFP2 CH4"),
.COM_ADDR_WIDTH(10),
.CH_ADDR_WIDTH(10)
)
xfcp_cfp2_gty_quad_inst_1 (
.clk(gty_drp_clk),
.rst(gty_drp_rst),
.up_xfcp_in_tdata(xfcp_cfp2_gty_1_down_tdata),
.up_xfcp_in_tvalid(xfcp_cfp2_gty_1_down_tvalid),
.up_xfcp_in_tready(xfcp_cfp2_gty_1_down_tready),
.up_xfcp_in_tlast(xfcp_cfp2_gty_1_down_tlast),
.up_xfcp_in_tuser(xfcp_cfp2_gty_1_down_tuser),
.up_xfcp_out_tdata(xfcp_cfp2_gty_1_up_tdata),
.up_xfcp_out_tvalid(xfcp_cfp2_gty_1_up_tvalid),
.up_xfcp_out_tready(xfcp_cfp2_gty_1_up_tready),
.up_xfcp_out_tlast(xfcp_cfp2_gty_1_up_tlast),
.up_xfcp_out_tuser(xfcp_cfp2_gty_1_up_tuser),
.gty_com_drp_addr(cfp2_gty_com_drp_addr[0*10 +: 10]),
.gty_com_drp_do(cfp2_gty_com_drp_do[0*16 +: 16]),
.gty_com_drp_di(cfp2_gty_com_drp_di[0*16 +: 16]),
.gty_com_drp_en(cfp2_gty_com_drp_en[0*1 +: 1]),
.gty_com_drp_we(cfp2_gty_com_drp_we[0*1 +: 1]),
.gty_com_drp_rdy(cfp2_gty_com_drp_rdy[0*1 +: 1]),
.gty_drp_addr(cfp2_gty_drp_addr[0*4*10 +: 4*10]),
.gty_drp_do(cfp2_gty_drp_do[0*4*16 +: 4*16]),
.gty_drp_di(cfp2_gty_drp_di[0*4*16 +: 4*16]),
.gty_drp_en(cfp2_gty_drp_en[0*4*1 +: 4*1]),
.gty_drp_we(cfp2_gty_drp_we[0*4*1 +: 4*1]),
.gty_drp_rdy(cfp2_gty_drp_rdy[0*4*1 +: 4*1]),
.gty_reset(cfp2_gty_reset[0*4*1 +: 4*1]),
.gty_tx_pcs_reset(cfp2_gty_tx_pcs_reset[0*4*1 +: 4*1]),
.gty_tx_pma_reset(cfp2_gty_tx_pma_reset[0*4*1 +: 4*1]),
.gty_rx_pcs_reset(cfp2_gty_rx_pcs_reset[0*4*1 +: 4*1]),
.gty_rx_pma_reset(cfp2_gty_rx_pma_reset[0*4*1 +: 4*1]),
.gty_rx_dfe_lpm_reset(cfp2_gty_rx_dfe_lpm_reset[0*4*1 +: 4*1]),
.gty_eyescan_reset(cfp2_gty_eyescan_reset[0*4*1 +: 4*1]),
.gty_tx_reset_done(cfp2_gty_tx_reset_done[0*4*1 +: 4*1]),
.gty_tx_pma_reset_done(cfp2_gty_tx_pma_reset_done[0*4*1 +: 4*1]),
.gty_rx_reset_done(cfp2_gty_rx_reset_done[0*4*1 +: 4*1]),
.gty_rx_pma_reset_done(cfp2_gty_rx_pma_reset_done[0*4*1 +: 4*1]),
.gty_txusrclk2({4{cfp2_gty_txusrclk2}}),
.gty_txprbssel(cfp2_gty_txprbssel[0*4*4 +: 4*4]),
.gty_txprbsforceerr(cfp2_gty_txprbsforceerr[0*4*1 +: 4*1]),
.gty_txpolarity(cfp2_gty_txpolarity[0*4*1 +: 4*1]),
.gty_txelecidle(cfp2_gty_txelecidle[0*4*1 +: 4*1]),
.gty_txinhibit(cfp2_gty_txinhibit[0*4*1 +: 4*1]),
.gty_txdiffctrl(cfp2_gty_txdiffctrl[0*4*5 +: 4*5]),
.gty_txmaincursor(cfp2_gty_txmaincursor[0*4*7 +: 4*7]),
.gty_txpostcursor(cfp2_gty_txpostcursor[0*4*5 +: 4*5]),
.gty_txprecursor(cfp2_gty_txprecursor[0*4*5 +: 4*5]),
.gty_rxusrclk2({4{cfp2_gty_rxusrclk2}}),
.gty_rxpolarity(cfp2_gty_rxpolarity[0*4*1 +: 4*1]),
.gty_rxprbscntreset(cfp2_gty_rxprbscntreset[0*4*1 +: 4*1]),
.gty_rxprbssel(cfp2_gty_rxprbssel[0*4*4 +: 4*4]),
.gty_rxprbserr(cfp2_gty_rxprbserr[0*4*1 +: 4*1]),
.gty_rxprbslocked(cfp2_gty_rxprbslocked[0*4*1 +: 4*1])
);
xfcp_gty_quad #(
.CH(4),
.SW_XFCP_ID_TYPE(16'h0100),
.SW_XFCP_ID_STR("GTY QUAD 129"),
.SW_XFCP_EXT_ID(0),
.SW_XFCP_EXT_ID_STR("CFP2 GTY QUAD"),
.COM_XFCP_ID_TYPE(16'h8A82),
.COM_XFCP_ID_STR("GTY COM X0Y5"),
.COM_XFCP_EXT_ID(0),
.COM_XFCP_EXT_ID_STR("CFP2 GTY COM"),
.CH_0_XFCP_ID_TYPE(16'h8A83),
.CH_0_XFCP_ID_STR("GTY CH0 X0Y20"),
.CH_0_XFCP_EXT_ID(0),
.CH_0_XFCP_EXT_ID_STR("CFP2 CH6"),
.CH_1_XFCP_ID_TYPE(16'h8A83),
.CH_1_XFCP_ID_STR("GTY CH1 X0Y21"),
.CH_1_XFCP_EXT_ID(0),
.CH_1_XFCP_EXT_ID_STR("CFP2 CH5"),
.CH_2_XFCP_ID_TYPE(16'h8A83),
.CH_2_XFCP_ID_STR("GTY CH2 X0Y22"),
.CH_2_XFCP_EXT_ID(0),
.CH_2_XFCP_EXT_ID_STR("CFP2 CH2"),
.CH_3_XFCP_ID_TYPE(16'h8A83),
.CH_3_XFCP_ID_STR("GTY CH3 X0Y23"),
.CH_3_XFCP_EXT_ID(0),
.CH_3_XFCP_EXT_ID_STR("CFP2 CH1"),
.COM_ADDR_WIDTH(10),
.CH_ADDR_WIDTH(10)
)
xfcp_cfp2_gty_quad_inst_2 (
.clk(gty_drp_clk),
.rst(gty_drp_rst),
.up_xfcp_in_tdata(xfcp_cfp2_gty_2_down_tdata),
.up_xfcp_in_tvalid(xfcp_cfp2_gty_2_down_tvalid),
.up_xfcp_in_tready(xfcp_cfp2_gty_2_down_tready),
.up_xfcp_in_tlast(xfcp_cfp2_gty_2_down_tlast),
.up_xfcp_in_tuser(xfcp_cfp2_gty_2_down_tuser),
.up_xfcp_out_tdata(xfcp_cfp2_gty_2_up_tdata),
.up_xfcp_out_tvalid(xfcp_cfp2_gty_2_up_tvalid),
.up_xfcp_out_tready(xfcp_cfp2_gty_2_up_tready),
.up_xfcp_out_tlast(xfcp_cfp2_gty_2_up_tlast),
.up_xfcp_out_tuser(xfcp_cfp2_gty_2_up_tuser),
.gty_com_drp_addr(cfp2_gty_com_drp_addr[1*10 +: 10]),
.gty_com_drp_do(cfp2_gty_com_drp_do[1*16 +: 16]),
.gty_com_drp_di(cfp2_gty_com_drp_di[1*16 +: 16]),
.gty_com_drp_en(cfp2_gty_com_drp_en[1*1 +: 1]),
.gty_com_drp_we(cfp2_gty_com_drp_we[1*1 +: 1]),
.gty_com_drp_rdy(cfp2_gty_com_drp_rdy[1*1 +: 1]),
.gty_drp_addr(cfp2_gty_drp_addr[1*4*10 +: 4*10]),
.gty_drp_do(cfp2_gty_drp_do[1*4*16 +: 4*16]),
.gty_drp_di(cfp2_gty_drp_di[1*4*16 +: 4*16]),
.gty_drp_en(cfp2_gty_drp_en[1*4*1 +: 4*1]),
.gty_drp_we(cfp2_gty_drp_we[1*4*1 +: 4*1]),
.gty_drp_rdy(cfp2_gty_drp_rdy[1*4*1 +: 4*1]),
.gty_reset(cfp2_gty_reset[1*4*1 +: 4*1]),
.gty_tx_pcs_reset(cfp2_gty_tx_pcs_reset[1*4*1 +: 4*1]),
.gty_tx_pma_reset(cfp2_gty_tx_pma_reset[1*4*1 +: 4*1]),
.gty_rx_pcs_reset(cfp2_gty_rx_pcs_reset[1*4*1 +: 4*1]),
.gty_rx_pma_reset(cfp2_gty_rx_pma_reset[1*4*1 +: 4*1]),
.gty_rx_dfe_lpm_reset(cfp2_gty_rx_dfe_lpm_reset[1*4*1 +: 4*1]),
.gty_eyescan_reset(cfp2_gty_eyescan_reset[1*4*1 +: 4*1]),
.gty_tx_reset_done(cfp2_gty_tx_reset_done[1*4*1 +: 4*1]),
.gty_tx_pma_reset_done(cfp2_gty_tx_pma_reset_done[1*4*1 +: 4*1]),
.gty_rx_reset_done(cfp2_gty_rx_reset_done[1*4*1 +: 4*1]),
.gty_rx_pma_reset_done(cfp2_gty_rx_pma_reset_done[1*4*1 +: 4*1]),
.gty_txusrclk2({4{cfp2_gty_txusrclk2}}),
.gty_txprbssel(cfp2_gty_txprbssel[1*4*4 +: 4*4]),
.gty_txprbsforceerr(cfp2_gty_txprbsforceerr[1*4*1 +: 4*1]),
.gty_txpolarity(cfp2_gty_txpolarity[1*4*1 +: 4*1]),
.gty_txelecidle(cfp2_gty_txelecidle[1*4*1 +: 4*1]),
.gty_txinhibit(cfp2_gty_txinhibit[1*4*1 +: 4*1]),
.gty_txdiffctrl(cfp2_gty_txdiffctrl[1*4*5 +: 4*5]),
.gty_txmaincursor(cfp2_gty_txmaincursor[1*4*7 +: 4*7]),
.gty_txpostcursor(cfp2_gty_txpostcursor[1*4*5 +: 4*5]),
.gty_txprecursor(cfp2_gty_txprecursor[1*4*5 +: 4*5]),
.gty_rxusrclk2({4{cfp2_gty_rxusrclk2}}),
.gty_rxpolarity(cfp2_gty_rxpolarity[1*4*1 +: 4*1]),
.gty_rxprbscntreset(cfp2_gty_rxprbscntreset[1*4*1 +: 4*1]),
.gty_rxprbssel(cfp2_gty_rxprbssel[1*4*4 +: 4*4]),
.gty_rxprbserr(cfp2_gty_rxprbserr[1*4*1 +: 4*1]),
.gty_rxprbslocked(cfp2_gty_rxprbslocked[1*4*1 +: 4*1])
);
xfcp_gty_quad #(
.CH(2),
.SW_XFCP_ID_TYPE(16'h0100),
.SW_XFCP_ID_STR("GTY QUAD 130"),
.SW_XFCP_EXT_ID(0),
.SW_XFCP_EXT_ID_STR("CFP2 GTY QUAD"),
.COM_XFCP_ID_TYPE(16'h8A82),
.COM_XFCP_ID_STR("GTY COM X0Y6"),
.COM_XFCP_EXT_ID(0),
.COM_XFCP_EXT_ID_STR("CFP2 GTY COM"),
.CH_0_XFCP_ID_TYPE(16'h8A83),
.CH_0_XFCP_ID_STR("GTY CH0 X0Y24"),
.CH_0_XFCP_EXT_ID(0),
.CH_0_XFCP_EXT_ID_STR("CFP2 CH3"),
.CH_1_XFCP_ID_TYPE(16'h8A83),
.CH_1_XFCP_ID_STR("GTY CH1 X0Y25"),
.CH_1_XFCP_EXT_ID(0),
.CH_1_XFCP_EXT_ID_STR("CFP2 CH0"),
.COM_ADDR_WIDTH(10),
.CH_ADDR_WIDTH(10)
)
xfcp_cfp2_gty_quad_inst_3 (
.clk(gty_drp_clk),
.rst(gty_drp_rst),
.up_xfcp_in_tdata(xfcp_cfp2_gty_3_down_tdata),
.up_xfcp_in_tvalid(xfcp_cfp2_gty_3_down_tvalid),
.up_xfcp_in_tready(xfcp_cfp2_gty_3_down_tready),
.up_xfcp_in_tlast(xfcp_cfp2_gty_3_down_tlast),
.up_xfcp_in_tuser(xfcp_cfp2_gty_3_down_tuser),
.up_xfcp_out_tdata(xfcp_cfp2_gty_3_up_tdata),
.up_xfcp_out_tvalid(xfcp_cfp2_gty_3_up_tvalid),
.up_xfcp_out_tready(xfcp_cfp2_gty_3_up_tready),
.up_xfcp_out_tlast(xfcp_cfp2_gty_3_up_tlast),
.up_xfcp_out_tuser(xfcp_cfp2_gty_3_up_tuser),
.gty_com_drp_addr(cfp2_gty_com_drp_addr[2*10 +: 10]),
.gty_com_drp_do(cfp2_gty_com_drp_do[2*16 +: 16]),
.gty_com_drp_di(cfp2_gty_com_drp_di[2*16 +: 16]),
.gty_com_drp_en(cfp2_gty_com_drp_en[2*1 +: 1]),
.gty_com_drp_we(cfp2_gty_com_drp_we[2*1 +: 1]),
.gty_com_drp_rdy(cfp2_gty_com_drp_rdy[2*1 +: 1]),
.gty_drp_addr(cfp2_gty_drp_addr[2*4*10 +: 2*10]),
.gty_drp_do(cfp2_gty_drp_do[2*4*16 +: 2*16]),
.gty_drp_di(cfp2_gty_drp_di[2*4*16 +: 2*16]),
.gty_drp_en(cfp2_gty_drp_en[2*4*1 +: 2*1]),
.gty_drp_we(cfp2_gty_drp_we[2*4*1 +: 2*1]),
.gty_drp_rdy(cfp2_gty_drp_rdy[2*4*1 +: 2*1]),
.gty_reset(cfp2_gty_reset[2*4*1 +: 2*1]),
.gty_tx_pcs_reset(cfp2_gty_tx_pcs_reset[2*4*1 +: 2*1]),
.gty_tx_pma_reset(cfp2_gty_tx_pma_reset[2*4*1 +: 2*1]),
.gty_rx_pcs_reset(cfp2_gty_rx_pcs_reset[2*4*1 +: 2*1]),
.gty_rx_pma_reset(cfp2_gty_rx_pma_reset[2*4*1 +: 2*1]),
.gty_rx_dfe_lpm_reset(cfp2_gty_rx_dfe_lpm_reset[2*4*1 +: 2*1]),
.gty_eyescan_reset(cfp2_gty_eyescan_reset[2*4*1 +: 2*1]),
.gty_tx_reset_done(cfp2_gty_tx_reset_done[2*4*1 +: 2*1]),
.gty_tx_pma_reset_done(cfp2_gty_tx_pma_reset_done[2*4*1 +: 2*1]),
.gty_rx_reset_done(cfp2_gty_rx_reset_done[2*4*1 +: 2*1]),
.gty_rx_pma_reset_done(cfp2_gty_rx_pma_reset_done[2*4*1 +: 2*1]),
.gty_txusrclk2({2{cfp2_gty_txusrclk2}}),
.gty_txprbssel(cfp2_gty_txprbssel[2*4*4 +: 2*4]),
.gty_txprbsforceerr(cfp2_gty_txprbsforceerr[2*4*1 +: 2*1]),
.gty_txpolarity(cfp2_gty_txpolarity[2*4*1 +: 2*1]),
.gty_txelecidle(cfp2_gty_txelecidle[2*4*1 +: 2*1]),
.gty_txinhibit(cfp2_gty_txinhibit[2*4*1 +: 2*1]),
.gty_txdiffctrl(cfp2_gty_txdiffctrl[2*4*5 +: 2*5]),
.gty_txmaincursor(cfp2_gty_txmaincursor[2*4*7 +: 2*7]),
.gty_txpostcursor(cfp2_gty_txpostcursor[2*4*5 +: 2*5]),
.gty_txprecursor(cfp2_gty_txprecursor[2*4*5 +: 2*5]),
.gty_rxusrclk2({2{cfp2_gty_rxusrclk2}}),
.gty_rxpolarity(cfp2_gty_rxpolarity[2*4*1 +: 2*1]),
.gty_rxprbscntreset(cfp2_gty_rxprbscntreset[2*4*1 +: 2*1]),
.gty_rxprbssel(cfp2_gty_rxprbssel[2*4*4 +: 2*4]),
.gty_rxprbserr(cfp2_gty_rxprbserr[2*4*1 +: 2*1]),
.gty_rxprbslocked(cfp2_gty_rxprbslocked[2*4*1 +: 2*1])
);
wire cfp2_mgt_refclk_0;
IBUFDS_GTE3 ibufds_gte3_cfp2_mgt_refclk_0_inst (
.I (cfp2_mgt_refclk_0_p),
.IB (cfp2_mgt_refclk_0_n),
.CEB (1'b0),
.O (cfp2_mgt_refclk_0),
.ODIV2 ()
);
gtwizard_ultrascale_1 gtwizard_ultrascale_1_inst (
.gtyrxn_in ({cfp2_rx0_n, cfp2_rx3_n, cfp2_rx1_n, cfp2_rx2_n, cfp2_rx5_n, cfp2_rx6_n, cfp2_rx4_n, cfp2_rx7_n, cfp2_rx8_n, cfp2_rx9_n}),
.gtyrxp_in ({cfp2_rx0_p, cfp2_rx3_p, cfp2_rx1_p, cfp2_rx2_p, cfp2_rx5_p, cfp2_rx6_p, cfp2_rx4_p, cfp2_rx7_p, cfp2_rx8_p, cfp2_rx9_p}),
.gtytxn_out ({cfp2_tx0_n, cfp2_tx3_n, cfp2_tx1_n, cfp2_tx2_n, cfp2_tx5_n, cfp2_tx6_n, cfp2_tx4_n, cfp2_tx7_n, cfp2_tx8_n, cfp2_tx9_n}),
.gtytxp_out ({cfp2_tx0_p, cfp2_tx3_p, cfp2_tx1_p, cfp2_tx2_p, cfp2_tx5_p, cfp2_tx6_p, cfp2_tx4_p, cfp2_tx7_p, cfp2_tx8_p, cfp2_tx9_p}),
.gtwiz_userclk_tx_reset_in (gty_drp_rst),
.gtwiz_userclk_tx_srcclk_out (),
.gtwiz_userclk_tx_usrclk_out (),
.gtwiz_userclk_tx_usrclk2_out (cfp2_gty_txusrclk2),
.gtwiz_userclk_tx_active_out (),
.gtwiz_userclk_rx_reset_in (gty_drp_rst),
.gtwiz_userclk_rx_srcclk_out (),
.gtwiz_userclk_rx_usrclk_out (),
.gtwiz_userclk_rx_usrclk2_out (cfp2_gty_rxusrclk2),
.gtwiz_userclk_rx_active_out (),
.gtwiz_reset_clk_freerun_in (gty_drp_clk),
.gtwiz_reset_all_in (gty_drp_rst || cfp2_gty_reset),
.gtwiz_reset_tx_pll_and_datapath_in (1'b0),
.gtwiz_reset_tx_datapath_in (1'b0),
.gtwiz_reset_rx_pll_and_datapath_in (1'b0),
.gtwiz_reset_rx_datapath_in (1'b0),
.gtwiz_reset_rx_cdr_stable_out (),
.gtwiz_reset_tx_done_out (),
.gtwiz_reset_rx_done_out (),
.gtwiz_userdata_tx_in ({10{64'd0}}),
.gtwiz_userdata_rx_out (),
.drpaddr_common_in (cfp2_gty_com_drp_addr),
.drpclk_common_in ({3{gty_drp_clk}}),
.drpdi_common_in (cfp2_gty_com_drp_do),
.drpen_common_in (cfp2_gty_com_drp_en),
.drpwe_common_in (cfp2_gty_com_drp_we),
.gtrefclk00_in ({3{cfp2_mgt_refclk_0}}),
.drpdo_common_out (cfp2_gty_com_drp_di),
.drprdy_common_out (cfp2_gty_com_drp_rdy),
.qpll0outclk_out (),
.qpll0outrefclk_out (),
.drpaddr_in (cfp2_gty_drp_addr),
.drpclk_in ({10{gty_drp_clk}}),
.drpdi_in (cfp2_gty_drp_do),
.drpen_in (cfp2_gty_drp_en),
.drpwe_in (cfp2_gty_drp_we),
.rxpolarity_in (cfp2_gty_rxpolarity),
.rxprbscntreset_in (cfp2_gty_rxprbscntreset),
.rxprbssel_in (cfp2_gty_rxprbssel),
.txdiffctrl_in (cfp2_gty_txdiffctrl),
.txelecidle_in (cfp2_gty_txelecidle),
.txinhibit_in (cfp2_gty_txinhibit),
.txmaincursor_in (cfp2_gty_txmaincursor),
.txpolarity_in (cfp2_gty_txpolarity),
.txpostcursor_in (cfp2_gty_txpostcursor),
.txprbsforceerr_in (cfp2_gty_txprbsforceerr),
.txprbssel_in (cfp2_gty_txprbssel),
.txprecursor_in (cfp2_gty_txprecursor),
.drpdo_out (cfp2_gty_drp_di),
.drprdy_out (cfp2_gty_drp_rdy),
.gtpowergood_out (),
.eyescandataerror_out (),
.rxprbserr_out (cfp2_gty_rxprbserr),
.rxprbslocked_out (cfp2_gty_rxprbslocked),
.rxpcsreset_in (cfp2_gty_rx_pcs_reset),
.rxpmareset_in (cfp2_gty_rx_pma_reset),
.rxdfelpmreset_in (cfp2_gty_rx_dfe_lpm_reset),
.eyescanreset_in (cfp2_gty_eyescan_reset),
.rxpmaresetdone_out (cfp2_gty_rx_pma_reset_done),
.rxprgdivresetdone_out (),
.rxresetdone_out (cfp2_gty_rx_reset_done),
.txpcsreset_in (cfp2_gty_tx_pcs_reset),
.txpmareset_in (cfp2_gty_tx_pma_reset),
.txpmaresetdone_out (cfp2_gty_tx_pma_reset_done),
.txprgdivresetdone_out (),
.txresetdone_out (cfp2_gty_tx_reset_done)
);
// Bullseye GTY
wire [9:0] bullseye_gty_com_drp_addr;
wire [15:0] bullseye_gty_com_drp_do;
wire [15:0] bullseye_gty_com_drp_di;
wire bullseye_gty_com_drp_en;
wire bullseye_gty_com_drp_we;
wire bullseye_gty_com_drp_rdy;
wire [4*10-1:0] bullseye_gty_drp_addr;
wire [4*16-1:0] bullseye_gty_drp_do;
wire [4*16-1:0] bullseye_gty_drp_di;
wire [4-1:0] bullseye_gty_drp_en;
wire [4-1:0] bullseye_gty_drp_we;
wire [4-1:0] bullseye_gty_drp_rdy;
wire [4-1:0] bullseye_gty_reset;
wire [4-1:0] bullseye_gty_tx_pcs_reset;
wire [4-1:0] bullseye_gty_tx_pma_reset;
wire [4-1:0] bullseye_gty_rx_pcs_reset;
wire [4-1:0] bullseye_gty_rx_pma_reset;
wire [4-1:0] bullseye_gty_rx_dfe_lpm_reset;
wire [4-1:0] bullseye_gty_eyescan_reset;
wire [4-1:0] bullseye_gty_tx_reset_done;
wire [4-1:0] bullseye_gty_tx_pma_reset_done;
wire [4-1:0] bullseye_gty_rx_reset_done;
wire [4-1:0] bullseye_gty_rx_pma_reset_done;
wire bullseye_gty_txusrclk2;
wire [4*4-1:0] bullseye_gty_txprbssel;
wire [4-1:0] bullseye_gty_txprbsforceerr;
wire [4-1:0] bullseye_gty_txpolarity;
wire [4-1:0] bullseye_gty_txelecidle;
wire [4-1:0] bullseye_gty_txinhibit;
wire [4*5-1:0] bullseye_gty_txdiffctrl;
wire [4*7-1:0] bullseye_gty_txmaincursor;
wire [4*5-1:0] bullseye_gty_txpostcursor;
wire [4*5-1:0] bullseye_gty_txprecursor;
wire bullseye_gty_rxusrclk2;
wire [4-1:0] bullseye_gty_rxpolarity;
wire [4-1:0] bullseye_gty_rxprbscntreset;
wire [4*4-1:0] bullseye_gty_rxprbssel;
wire [4-1:0] bullseye_gty_rxprbserr;
wire [4-1:0] bullseye_gty_rxprbslocked;
xfcp_gty_quad #(
.CH(4),
.SW_XFCP_ID_TYPE(16'h0100),
.SW_XFCP_ID_STR("GTY QUAD 126"),
.SW_XFCP_EXT_ID(0),
.SW_XFCP_EXT_ID_STR("BEYE GTY QUAD"),
.COM_XFCP_ID_TYPE(16'h8A82),
.COM_XFCP_ID_STR("GTY COM X0Y2"),
.COM_XFCP_EXT_ID(0),
.COM_XFCP_EXT_ID_STR("BEYE GTY COM"),
.CH_0_XFCP_ID_TYPE(16'h8A83),
.CH_0_XFCP_ID_STR("GTY CH0 X0Y8"),
.CH_0_XFCP_EXT_ID(0),
.CH_0_XFCP_EXT_ID_STR("BEYE CH0"),
.CH_1_XFCP_ID_TYPE(16'h8A83),
.CH_1_XFCP_ID_STR("GTY CH1 X0Y9"),
.CH_1_XFCP_EXT_ID(0),
.CH_1_XFCP_EXT_ID_STR("BEYE CH1"),
.CH_2_XFCP_ID_TYPE(16'h8A83),
.CH_2_XFCP_ID_STR("GTY CH2 X0Y10"),
.CH_2_XFCP_EXT_ID(0),
.CH_2_XFCP_EXT_ID_STR("BEYE CH2"),
.CH_3_XFCP_ID_TYPE(16'h8A83),
.CH_3_XFCP_ID_STR("GTY CH3 X0Y11"),
.CH_3_XFCP_EXT_ID(0),
.CH_3_XFCP_EXT_ID_STR("BEYE CH3"),
.COM_ADDR_WIDTH(10),
.CH_ADDR_WIDTH(10)
)
xfcp_bullseye_gty_quad_inst(
.clk(gty_drp_clk),
.rst(gty_drp_rst),
.up_xfcp_in_tdata(xfcp_bullseye_gty_down_tdata),
.up_xfcp_in_tvalid(xfcp_bullseye_gty_down_tvalid),
.up_xfcp_in_tready(xfcp_bullseye_gty_down_tready),
.up_xfcp_in_tlast(xfcp_bullseye_gty_down_tlast),
.up_xfcp_in_tuser(xfcp_bullseye_gty_down_tuser),
.up_xfcp_out_tdata(xfcp_bullseye_gty_up_tdata),
.up_xfcp_out_tvalid(xfcp_bullseye_gty_up_tvalid),
.up_xfcp_out_tready(xfcp_bullseye_gty_up_tready),
.up_xfcp_out_tlast(xfcp_bullseye_gty_up_tlast),
.up_xfcp_out_tuser(xfcp_bullseye_gty_up_tuser),
.gty_com_drp_addr(bullseye_gty_com_drp_addr),
.gty_com_drp_do(bullseye_gty_com_drp_do),
.gty_com_drp_di(bullseye_gty_com_drp_di),
.gty_com_drp_en(bullseye_gty_com_drp_en),
.gty_com_drp_we(bullseye_gty_com_drp_we),
.gty_com_drp_rdy(bullseye_gty_com_drp_rdy),
.gty_drp_addr(bullseye_gty_drp_addr),
.gty_drp_do(bullseye_gty_drp_do),
.gty_drp_di(bullseye_gty_drp_di),
.gty_drp_en(bullseye_gty_drp_en),
.gty_drp_we(bullseye_gty_drp_we),
.gty_drp_rdy(bullseye_gty_drp_rdy),
.gty_reset(bullseye_gty_reset),
.gty_tx_pcs_reset(bullseye_gty_tx_pcs_reset),
.gty_tx_pma_reset(bullseye_gty_tx_pma_reset),
.gty_rx_pcs_reset(bullseye_gty_rx_pcs_reset),
.gty_rx_pma_reset(bullseye_gty_rx_pma_reset),
.gty_rx_dfe_lpm_reset(bullseye_gty_rx_dfe_lpm_reset),
.gty_eyescan_reset(bullseye_gty_eyescan_reset),
.gty_tx_reset_done(bullseye_gty_tx_reset_done),
.gty_tx_pma_reset_done(bullseye_gty_tx_pma_reset_done),
.gty_rx_reset_done(bullseye_gty_rx_reset_done),
.gty_rx_pma_reset_done(bullseye_gty_rx_pma_reset_done),
.gty_txusrclk2({4{bullseye_gty_txusrclk2}}),
.gty_txprbssel(bullseye_gty_txprbssel),
.gty_txprbsforceerr(bullseye_gty_txprbsforceerr),
.gty_txpolarity(bullseye_gty_txpolarity),
.gty_txelecidle(bullseye_gty_txelecidle),
.gty_txinhibit(bullseye_gty_txinhibit),
.gty_txdiffctrl(bullseye_gty_txdiffctrl),
.gty_txmaincursor(bullseye_gty_txmaincursor),
.gty_txpostcursor(bullseye_gty_txpostcursor),
.gty_txprecursor(bullseye_gty_txprecursor),
.gty_rxusrclk2({4{bullseye_gty_rxusrclk2}}),
.gty_rxpolarity(bullseye_gty_rxpolarity),
.gty_rxprbscntreset(bullseye_gty_rxprbscntreset),
.gty_rxprbssel(bullseye_gty_rxprbssel),
.gty_rxprbserr(bullseye_gty_rxprbserr),
.gty_rxprbslocked(bullseye_gty_rxprbslocked)
);
wire bullseye_mgt_refclk_1;
IBUFDS_GTE3 ibufds_gte3_bullseye_mgt_refclk_1_inst (
.I (bullseye_mgt_refclk_1_p),
.IB (bullseye_mgt_refclk_1_n),
.CEB (1'b0),
.O (bullseye_mgt_refclk_1),
.ODIV2 ()
);
gtwizard_ultrascale_2 gtwizard_ultrascale_2_inst (
.gtyrxn_in ({bullseye_rx3_n, bullseye_rx2_n, bullseye_rx1_n, bullseye_rx0_n}),
.gtyrxp_in ({bullseye_rx3_p, bullseye_rx2_p, bullseye_rx1_p, bullseye_rx0_p}),
.gtytxn_out ({bullseye_tx3_n, bullseye_tx2_n, bullseye_tx1_n, bullseye_tx0_n}),
.gtytxp_out ({bullseye_tx3_p, bullseye_tx2_p, bullseye_tx1_p, bullseye_tx0_p}),
.gtwiz_userclk_tx_reset_in (gty_drp_rst),
.gtwiz_userclk_tx_srcclk_out (),
.gtwiz_userclk_tx_usrclk_out (),
.gtwiz_userclk_tx_usrclk2_out (bullseye_gty_txusrclk2),
.gtwiz_userclk_tx_active_out (),
.gtwiz_userclk_rx_reset_in (gty_drp_rst),
.gtwiz_userclk_rx_srcclk_out (),
.gtwiz_userclk_rx_usrclk_out (),
.gtwiz_userclk_rx_usrclk2_out (bullseye_gty_rxusrclk2),
.gtwiz_userclk_rx_active_out (),
.gtwiz_reset_clk_freerun_in (gty_drp_clk),
.gtwiz_reset_all_in (gty_drp_rst || bullseye_gty_reset),
.gtwiz_reset_tx_pll_and_datapath_in (1'b0),
.gtwiz_reset_tx_datapath_in (1'b0),
.gtwiz_reset_rx_pll_and_datapath_in (1'b0),
.gtwiz_reset_rx_datapath_in (1'b0),
.gtwiz_reset_rx_cdr_stable_out (),
.gtwiz_reset_tx_done_out (),
.gtwiz_reset_rx_done_out (),
.gtwiz_userdata_tx_in ({4{64'd0}}),
.gtwiz_userdata_rx_out (),
.drpaddr_common_in (bullseye_gty_com_drp_addr),
.drpclk_common_in (gty_drp_clk),
.drpdi_common_in (bullseye_gty_com_drp_do),
.drpen_common_in (bullseye_gty_com_drp_en),
.drpwe_common_in (bullseye_gty_com_drp_we),
.gtrefclk01_in (bullseye_mgt_refclk_1),
.drpdo_common_out (bullseye_gty_com_drp_di),
.drprdy_common_out (bullseye_gty_com_drp_rdy),
.qpll1outclk_out (),
.qpll1outrefclk_out (),
.drpaddr_in (bullseye_gty_drp_addr),
.drpclk_in ({4{gty_drp_clk}}),
.drpdi_in (bullseye_gty_drp_do),
.drpen_in (bullseye_gty_drp_en),
.drpwe_in (bullseye_gty_drp_we),
.rxpolarity_in (bullseye_gty_rxpolarity),
.rxprbscntreset_in (bullseye_gty_rxprbscntreset),
.rxprbssel_in (bullseye_gty_rxprbssel),
.txdiffctrl_in (bullseye_gty_txdiffctrl),
.txelecidle_in (bullseye_gty_txelecidle),
.txinhibit_in (bullseye_gty_txinhibit),
.txmaincursor_in (bullseye_gty_txmaincursor),
.txpolarity_in (bullseye_gty_txpolarity),
.txpostcursor_in (bullseye_gty_txpostcursor),
.txprbsforceerr_in (bullseye_gty_txprbsforceerr),
.txprbssel_in (bullseye_gty_txprbssel),
.txprecursor_in (bullseye_gty_txprecursor),
.drpdo_out (bullseye_gty_drp_di),
.drprdy_out (bullseye_gty_drp_rdy),
.gtpowergood_out (),
.eyescandataerror_out (),
.rxprbserr_out (bullseye_gty_rxprbserr),
.rxprbslocked_out (bullseye_gty_rxprbslocked),
.rxpcsreset_in (bullseye_gty_rx_pcs_reset),
.rxpmareset_in (bullseye_gty_rx_pma_reset),
.rxdfelpmreset_in (bullseye_gty_rx_dfe_lpm_reset),
.eyescanreset_in (bullseye_gty_eyescan_reset),
.rxpmaresetdone_out (bullseye_gty_rx_pma_reset_done),
.rxprgdivresetdone_out (),
.rxresetdone_out (bullseye_gty_rx_reset_done),
.txpcsreset_in (bullseye_gty_tx_pcs_reset),
.txpmareset_in (bullseye_gty_tx_pma_reset),
.txpmaresetdone_out (bullseye_gty_tx_pma_reset_done),
.txprgdivresetdone_out (),
.txresetdone_out (bullseye_gty_tx_reset_done)
);
// SGMII interface to PHY
wire phy_gmii_clk_int;
wire phy_gmii_rst_int;
wire phy_gmii_clk_en_int;
wire [7:0] phy_gmii_txd_int;
wire phy_gmii_tx_en_int;
wire phy_gmii_tx_er_int;
wire [7:0] phy_gmii_rxd_int;
wire phy_gmii_rx_dv_int;
wire phy_gmii_rx_er_int;
wire [15:0] gig_eth_pcspma_status_vector;
wire gig_eth_pcspma_status_link_status = gig_eth_pcspma_status_vector[0];
wire gig_eth_pcspma_status_link_synchronization = gig_eth_pcspma_status_vector[1];
wire gig_eth_pcspma_status_rudi_c = gig_eth_pcspma_status_vector[2];
wire gig_eth_pcspma_status_rudi_i = gig_eth_pcspma_status_vector[3];
wire gig_eth_pcspma_status_rudi_invalid = gig_eth_pcspma_status_vector[4];
wire gig_eth_pcspma_status_rxdisperr = gig_eth_pcspma_status_vector[5];
wire gig_eth_pcspma_status_rxnotintable = gig_eth_pcspma_status_vector[6];
wire gig_eth_pcspma_status_phy_link_status = gig_eth_pcspma_status_vector[7];
wire [1:0] gig_eth_pcspma_status_remote_fault_encdg = gig_eth_pcspma_status_vector[9:8];
wire [1:0] gig_eth_pcspma_status_speed = gig_eth_pcspma_status_vector[11:10];
wire gig_eth_pcspma_status_duplex = gig_eth_pcspma_status_vector[12];
wire gig_eth_pcspma_status_remote_fault = gig_eth_pcspma_status_vector[13];
wire [1:0] gig_eth_pcspma_status_pause = gig_eth_pcspma_status_vector[15:14];
wire [4:0] gig_eth_pcspma_config_vector;
assign gig_eth_pcspma_config_vector[4] = 1'b1; // autonegotiation enable
assign gig_eth_pcspma_config_vector[3] = 1'b0; // isolate
assign gig_eth_pcspma_config_vector[2] = 1'b0; // power down
assign gig_eth_pcspma_config_vector[1] = 1'b0; // loopback enable
assign gig_eth_pcspma_config_vector[0] = 1'b0; // unidirectional enable
wire [15:0] gig_eth_pcspma_an_config_vector;
assign gig_eth_pcspma_an_config_vector[15] = 1'b1; // SGMII link status
assign gig_eth_pcspma_an_config_vector[14] = 1'b1; // SGMII Acknowledge
assign gig_eth_pcspma_an_config_vector[13:12] = 2'b01; // full duplex
assign gig_eth_pcspma_an_config_vector[11:10] = 2'b10; // SGMII speed
assign gig_eth_pcspma_an_config_vector[9] = 1'b0; // reserved
assign gig_eth_pcspma_an_config_vector[8:7] = 2'b00; // pause frames - SGMII reserved
assign gig_eth_pcspma_an_config_vector[6] = 1'b0; // reserved
assign gig_eth_pcspma_an_config_vector[5] = 1'b0; // full duplex - SGMII reserved
assign gig_eth_pcspma_an_config_vector[4:1] = 4'b0000; // reserved
assign gig_eth_pcspma_an_config_vector[0] = 1'b1; // SGMII
gig_ethernet_pcs_pma_0
gig_eth_pcspma (
// SGMII
.txp (phy_sgmii_tx_p),
.txn (phy_sgmii_tx_n),
.rxp (phy_sgmii_rx_p),
.rxn (phy_sgmii_rx_n),
// Ref clock from PHY
.refclk625_p (phy_sgmii_clk_p),
.refclk625_n (phy_sgmii_clk_n),
// async reset
.reset (rst_125mhz_int),
// clock and reset outputs
.clk125_out (phy_gmii_clk_int),
.clk625_out (),
.clk312_out (),
.rst_125_out (phy_gmii_rst_int),
.idelay_rdy_out (),
.mmcm_locked_out (),
// MAC clocking
.sgmii_clk_r (),
.sgmii_clk_f (),
.sgmii_clk_en (phy_gmii_clk_en_int),
// Speed control
.speed_is_10_100 (gig_eth_pcspma_status_speed != 2'b10),
.speed_is_100 (gig_eth_pcspma_status_speed == 2'b01),
// Internal GMII
.gmii_txd (phy_gmii_txd_int),
.gmii_tx_en (phy_gmii_tx_en_int),
.gmii_tx_er (phy_gmii_tx_er_int),
.gmii_rxd (phy_gmii_rxd_int),
.gmii_rx_dv (phy_gmii_rx_dv_int),
.gmii_rx_er (phy_gmii_rx_er_int),
.gmii_isolate (),
// Configuration
.configuration_vector (gig_eth_pcspma_config_vector),
.an_interrupt (),
.an_adv_config_vector (gig_eth_pcspma_an_config_vector),
.an_restart_config (1'b0),
// Status
.status_vector (gig_eth_pcspma_status_vector),
.signal_detect (1'b1)
);
fpga_core
core_inst (
/*
* Clock: 125MHz
* Synchronous reset
*/
.clk(clk_125mhz_int),
.rst(rst_125mhz_int),
/*
* GPIO
*/
.btnu(btnu_int),
.btnl(btnl_int),
.btnd(btnd_int),
.btnr(btnr_int),
.btnc(btnc_int),
.sw(sw_int),
.led(led),
/*
* I2C
*/
.i2c_scl_i(i2c_scl_i),
.i2c_scl_o(i2c_scl_o),
.i2c_scl_t(i2c_scl_t),
.i2c_sda_i(i2c_sda_i),
.i2c_sda_o(i2c_sda_o),
.i2c_sda_t(i2c_sda_t),
/*
* Ethernet: 1000BASE-T SGMII
*/
.phy_gmii_clk(phy_gmii_clk_int),
.phy_gmii_rst(phy_gmii_rst_int),
.phy_gmii_clk_en(phy_gmii_clk_en_int),
.phy_gmii_rxd(phy_gmii_rxd_int),
.phy_gmii_rx_dv(phy_gmii_rx_dv_int),
.phy_gmii_rx_er(phy_gmii_rx_er_int),
.phy_gmii_txd(phy_gmii_txd_int),
.phy_gmii_tx_en(phy_gmii_tx_en_int),
.phy_gmii_tx_er(phy_gmii_tx_er_int),
.phy_reset_n(phy_reset_n),
.phy_int_n(phy_int_n),
/*
* UART: 115200 bps, 8N1
*/
.uart_rxd(uart_rxd_int),
.uart_txd(uart_txd),
.uart_rts(uart_rts),
.uart_cts(uart_cts_int),
/*
* Transceiver control
*/
.xfcp_mgt_up_tdata(xfcp_mgt_up_tdata),
.xfcp_mgt_up_tvalid(xfcp_mgt_up_tvalid),
.xfcp_mgt_up_tready(xfcp_mgt_up_tready),
.xfcp_mgt_up_tlast(xfcp_mgt_up_tlast),
.xfcp_mgt_up_tuser(xfcp_mgt_up_tuser),
.xfcp_mgt_down_tdata(xfcp_mgt_down_tdata),
.xfcp_mgt_down_tvalid(xfcp_mgt_down_tvalid),
.xfcp_mgt_down_tready(xfcp_mgt_down_tready),
.xfcp_mgt_down_tlast(xfcp_mgt_down_tlast),
.xfcp_mgt_down_tuser(xfcp_mgt_down_tuser)
);
endmodule
|
module xillybus #(
parameter C_S_AXI_DATA_WIDTH = 32,
parameter C_S_AXI_ADDR_WIDTH = 32,
parameter C_M_AXI_ADDR_WIDTH = 32,
parameter C_M_AXI_DATA_WIDTH = 32,
parameter C_S_AXI_MIN_SIZE = 32'h000001ff,
parameter C_USE_WSTRB = 1,
parameter C_DPHASE_TIMEOUT = 8,
parameter C_BASEADDR = 32'h79c00000,
parameter C_HIGHADDR = 32'h79c0ffff,
parameter C_SLV_AWIDTH = 32,
parameter C_SLV_DWIDTH = 32,
parameter C_MAX_BURST_LEN = 256,
parameter C_NATIVE_DATA_WIDTH = 32
)
(
input S_AXI_ACLK,
input S_AXI_ARESETN,
output Interrupt,
input [(C_S_AXI_ADDR_WIDTH-1):0] S_AXI_AWADDR,
input S_AXI_AWVALID,
input [(C_S_AXI_DATA_WIDTH-1):0] S_AXI_WDATA,
input [((C_S_AXI_DATA_WIDTH/8)-1):0] S_AXI_WSTRB,
input S_AXI_WVALID,
input S_AXI_BREADY,
input [(C_S_AXI_ADDR_WIDTH-1):0] S_AXI_ARADDR,
input S_AXI_ARVALID,
input S_AXI_RREADY,
output S_AXI_ARREADY,
output [(C_S_AXI_DATA_WIDTH-1):0] S_AXI_RDATA,
output [1:0] S_AXI_RRESP,
output S_AXI_RVALID,
output S_AXI_WREADY,
output [1:0] S_AXI_BRESP,
output S_AXI_BVALID,
output S_AXI_AWREADY,
input m_axi_aclk,
input m_axi_aresetn,
input m_axi_arready,
output m_axi_arvalid,
output [(C_M_AXI_ADDR_WIDTH-1):0] m_axi_araddr,
output [3:0] m_axi_arlen,
output [2:0] m_axi_arsize,
output [1:0] m_axi_arburst,
output [2:0] m_axi_arprot,
output [3:0] m_axi_arcache,
output m_axi_rready,
input m_axi_rvalid,
input [(C_M_AXI_DATA_WIDTH-1):0] m_axi_rdata,
input [1:0] m_axi_rresp,
input m_axi_rlast,
input m_axi_awready,
output m_axi_awvalid,
output [(C_M_AXI_ADDR_WIDTH-1):0] m_axi_awaddr,
output [3:0] m_axi_awlen,
output [2:0] m_axi_awsize,
output [1:0] m_axi_awburst,
output [2:0] m_axi_awprot,
output [3:0] m_axi_awcache,
input m_axi_wready,
output m_axi_wvalid,
output [(C_M_AXI_DATA_WIDTH-1):0] m_axi_wdata,
output [((C_M_AXI_DATA_WIDTH/8)-1):0] m_axi_wstrb,
output m_axi_wlast,
output m_axi_bready,
input m_axi_bvalid,
input [1:0] m_axi_bresp,
output xillybus_bus_clk,
output reg xillybus_bus_rst_n,
output [(C_S_AXI_ADDR_WIDTH-1):0] xillybus_S_AXI_AWADDR,
output xillybus_S_AXI_AWVALID,
output [(C_S_AXI_DATA_WIDTH-1):0] xillybus_S_AXI_WDATA,
output [((C_S_AXI_DATA_WIDTH/8)-1):0] xillybus_S_AXI_WSTRB,
output xillybus_S_AXI_WVALID,
output xillybus_S_AXI_BREADY,
output [(C_S_AXI_ADDR_WIDTH-1):0] xillybus_S_AXI_ARADDR,
output xillybus_S_AXI_ARVALID,
output xillybus_S_AXI_RREADY,
input xillybus_S_AXI_ARREADY,
input [(C_S_AXI_DATA_WIDTH-1):0] xillybus_S_AXI_RDATA,
input [1:0] xillybus_S_AXI_RRESP,
input xillybus_S_AXI_RVALID,
input xillybus_S_AXI_WREADY,
input [1:0] xillybus_S_AXI_BRESP,
input xillybus_S_AXI_BVALID,
input xillybus_S_AXI_AWREADY,
output xillybus_M_AXI_ARREADY,
input xillybus_M_AXI_ARVALID,
input [(C_M_AXI_ADDR_WIDTH-1):0] xillybus_M_AXI_ARADDR,
input [3:0] xillybus_M_AXI_ARLEN,
input [2:0] xillybus_M_AXI_ARSIZE,
input [1:0] xillybus_M_AXI_ARBURST,
input [2:0] xillybus_M_AXI_ARPROT,
input [3:0] xillybus_M_AXI_ARCACHE,
input xillybus_M_AXI_RREADY,
output xillybus_M_AXI_RVALID,
output [(C_M_AXI_DATA_WIDTH-1):0] xillybus_M_AXI_RDATA,
output [1:0] xillybus_M_AXI_RRESP,
output xillybus_M_AXI_RLAST,
output xillybus_M_AXI_AWREADY,
input xillybus_M_AXI_AWVALID,
input [(C_M_AXI_ADDR_WIDTH-1):0] xillybus_M_AXI_AWADDR,
input [3:0] xillybus_M_AXI_AWLEN,
input [2:0] xillybus_M_AXI_AWSIZE,
input [1:0] xillybus_M_AXI_AWBURST,
input [2:0] xillybus_M_AXI_AWPROT,
input [3:0] xillybus_M_AXI_AWCACHE,
output xillybus_M_AXI_WREADY,
input xillybus_M_AXI_WVALID,
input [(C_M_AXI_DATA_WIDTH-1):0] xillybus_M_AXI_WDATA,
input [((C_M_AXI_DATA_WIDTH/8)-1):0] xillybus_M_AXI_WSTRB,
input xillybus_M_AXI_WLAST,
input xillybus_M_AXI_BREADY,
output xillybus_M_AXI_BVALID,
output [1:0] xillybus_M_AXI_BRESP,
input xillybus_host_interrupt
);
reg rst_sync;
// S_AXI_ARESETN is possibly completely asyncronous to anything, while
// bus_rst is expected to be synchronous w.r.t. to bus_clk. So it's synced.
always @(posedge S_AXI_ACLK)
begin
xillybus_bus_rst_n <= rst_sync;
rst_sync <= S_AXI_ARESETN;
end
// This module merely connects the AXI signals to the Xillybus core, which
// is external to the processor. This makes it possible to swap the Xillybus
// core without reimplementing the processor.
assign xillybus_bus_clk = S_AXI_ACLK ;
assign xillybus_S_AXI_AWADDR = S_AXI_AWADDR ;
assign xillybus_S_AXI_AWVALID = S_AXI_AWVALID ;
assign xillybus_S_AXI_WDATA = S_AXI_WDATA ;
assign xillybus_S_AXI_WSTRB = S_AXI_WSTRB ;
assign xillybus_S_AXI_WVALID = S_AXI_WVALID ;
assign xillybus_S_AXI_BREADY = S_AXI_BREADY ;
assign xillybus_S_AXI_ARADDR = S_AXI_ARADDR ;
assign xillybus_S_AXI_ARVALID = S_AXI_ARVALID ;
assign xillybus_S_AXI_RREADY = S_AXI_RREADY ;
assign S_AXI_ARREADY = xillybus_S_AXI_ARREADY ;
assign S_AXI_RDATA = xillybus_S_AXI_RDATA ;
assign S_AXI_RRESP = xillybus_S_AXI_RRESP ;
assign S_AXI_RVALID = xillybus_S_AXI_RVALID ;
assign S_AXI_WREADY = xillybus_S_AXI_WREADY ;
assign S_AXI_BRESP = xillybus_S_AXI_BRESP ;
assign S_AXI_BVALID = xillybus_S_AXI_BVALID ;
assign S_AXI_AWREADY = xillybus_S_AXI_AWREADY ;
assign xillybus_M_AXI_ACLK = m_axi_aclk ;
assign xillybus_M_AXI_ARESETN = m_axi_aresetn ;
assign xillybus_M_AXI_ARREADY = m_axi_arready ;
assign m_axi_arvalid = xillybus_M_AXI_ARVALID ;
assign m_axi_araddr = xillybus_M_AXI_ARADDR ;
assign m_axi_arlen = xillybus_M_AXI_ARLEN ;
assign m_axi_arsize = xillybus_M_AXI_ARSIZE ;
assign m_axi_arburst = xillybus_M_AXI_ARBURST ;
assign m_axi_arprot = xillybus_M_AXI_ARPROT ;
assign m_axi_arcache = xillybus_M_AXI_ARCACHE ;
assign m_axi_rready = xillybus_M_AXI_RREADY ;
assign xillybus_M_AXI_RVALID = m_axi_rvalid ;
assign xillybus_M_AXI_RDATA = m_axi_rdata ;
assign xillybus_M_AXI_RRESP = m_axi_rresp ;
assign xillybus_M_AXI_RLAST = m_axi_rlast ;
assign xillybus_M_AXI_AWREADY = m_axi_awready ;
assign m_axi_awvalid = xillybus_M_AXI_AWVALID ;
assign m_axi_awaddr = xillybus_M_AXI_AWADDR ;
assign m_axi_awlen = xillybus_M_AXI_AWLEN ;
assign m_axi_awsize = xillybus_M_AXI_AWSIZE ;
assign m_axi_awburst = xillybus_M_AXI_AWBURST ;
assign m_axi_awprot = xillybus_M_AXI_AWPROT ;
assign m_axi_awcache = xillybus_M_AXI_AWCACHE ;
assign xillybus_M_AXI_WREADY = m_axi_wready ;
assign m_axi_wvalid = xillybus_M_AXI_WVALID ;
assign m_axi_wdata = xillybus_M_AXI_WDATA ;
assign m_axi_wstrb = xillybus_M_AXI_WSTRB ;
assign m_axi_wlast = xillybus_M_AXI_WLAST ;
assign m_axi_bready = xillybus_M_AXI_BREADY ;
assign xillybus_M_AXI_BVALID = m_axi_bvalid ;
assign xillybus_M_AXI_BRESP = m_axi_bresp ;
assign Interrupt = xillybus_host_interrupt;
endmodule |
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_wishbone.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is available in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001, 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.57 2005/02/21 11:35:33 igorm
// Defer indication fixed.
//
// Revision 1.56 2004/04/30 10:30:00 igorm
// Accidently deleted line put back.
//
// Revision 1.55 2004/04/26 15:26:23 igorm
// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
// previous update of the core.
// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
// register. (thanks to Mathias and Torbjorn)
// - Multicast reception was fixed. Thanks to Ulrich Gries
//
// Revision 1.54 2003/11/12 18:24:59 tadejm
// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
//
// Revision 1.53 2003/10/17 07:46:17 markom
// mbist signals updated according to newest convention
//
// Revision 1.52 2003/01/30 14:51:31 mohor
// Reset has priority in some flipflops.
//
// Revision 1.51 2003/01/30 13:36:22 mohor
// A new bug (entered with previous update) fixed. When abort occured sometimes
// data transmission was blocked.
//
// Revision 1.50 2003/01/22 13:49:26 tadejm
// When control packets were received, they were ignored in some cases.
//
// Revision 1.49 2003/01/21 12:09:40 mohor
// When receiving normal data frame and RxFlow control was switched on, RXB
// interrupt was not set.
//
// Revision 1.48 2003/01/20 12:05:26 mohor
// When in full duplex, transmit was sometimes blocked. Fixed.
//
// Revision 1.47 2002/11/22 13:26:21 mohor
// Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
// anywhere. Removed.
//
// Revision 1.46 2002/11/22 01:57:06 mohor
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
// synchronized.
//
// Revision 1.45 2002/11/19 17:33:34 mohor
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
// that a frame was received because of the promiscous mode.
//
// Revision 1.44 2002/11/13 22:21:40 tadejm
// RxError is not generated when small frame reception is enabled and small
// frames are received.
//
// Revision 1.43 2002/10/18 20:53:34 mohor
// case changed to casex.
//
// Revision 1.42 2002/10/18 17:04:20 tadejm
// Changed BIST scan signals.
//
// Revision 1.41 2002/10/18 15:42:09 tadejm
// Igor added WB burst support and repaired BUG when handling TX under-run and retry.
//
// Revision 1.40 2002/10/14 16:07:02 mohor
// TxStatus is written after last access to the TX fifo is finished (in case of abort
// or retry). TxDone is fixed.
//
// Revision 1.39 2002/10/11 15:35:20 mohor
// txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
// TxDone and TxRetry are generated after the current WISHBONE access is
// finished.
//
// Revision 1.38 2002/10/10 16:29:30 mohor
// BIST added.
//
// Revision 1.37 2002/09/11 14:18:46 mohor
// Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.
//
// Revision 1.36 2002/09/10 13:48:46 mohor
// Reception is possible after RxPointer is read and not after BD is read. For
// that reason RxBDReady is changed to RxReady.
// Busy_IRQ interrupt connected. When there is no RxBD ready and frame
// comes, interrupt is generated.
//
// Revision 1.35 2002/09/10 10:35:23 mohor
// Ethernet debug registers removed.
//
// Revision 1.34 2002/09/08 16:31:49 mohor
// Async reset for WB_ACK_O removed (when core was in reset, it was
// impossible to access BDs).
// RxPointers and TxPointers names changed to be more descriptive.
// TxUnderRun synchronized.
//
// Revision 1.33 2002/09/04 18:47:57 mohor
// Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
// changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
// was not used OK.
//
// Revision 1.32 2002/08/14 19:31:48 mohor
// Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
// need to multiply or devide any more.
//
// Revision 1.31 2002/07/25 18:29:01 mohor
// WriteRxDataToMemory signal changed so end of frame (when last word is
// written to fifo) is changed.
//
// Revision 1.30 2002/07/23 15:28:31 mohor
// Ram , used for BDs changed from generic_spram to eth_spram_256x32.
//
// Revision 1.29 2002/07/20 00:41:32 mohor
// ShiftEnded synchronization changed.
//
// Revision 1.28 2002/07/18 16:11:46 mohor
// RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.
//
// Revision 1.27 2002/07/11 02:53:20 mohor
// RxPointer bug fixed.
//
// Revision 1.26 2002/07/10 13:12:38 mohor
// Previous bug wasn't succesfully removed. Now fixed.
//
// Revision 1.25 2002/07/09 23:53:24 mohor
// Master state machine had a bug when switching from master write to
// master read.
//
// Revision 1.24 2002/07/09 20:44:41 mohor
// m_wb_cyc_o signal released after every single transfer.
//
// Revision 1.23 2002/05/03 10:15:50 mohor
// Outputs registered. Reset changed for eth_wishbone module.
//
// Revision 1.22 2002/04/24 08:52:19 mohor
// Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
// bug fixed.
//
// Revision 1.21 2002/03/29 16:18:11 lampret
// Small typo fixed.
//
// Revision 1.20 2002/03/25 16:19:12 mohor
// Any address can be used for Tx and Rx BD pointers. Address does not need
// to be aligned.
//
// Revision 1.19 2002/03/19 12:51:50 mohor
// Comments in Slovene language removed.
//
// Revision 1.18 2002/03/19 12:46:52 mohor
// casex changed with case, fifo reset changed.
//
// Revision 1.17 2002/03/09 16:08:45 mohor
// rx_fifo was not always cleared ok. Fixed.
//
// Revision 1.16 2002/03/09 13:51:20 mohor
// Status was not latched correctly sometimes. Fixed.
//
// Revision 1.15 2002/03/08 06:56:46 mohor
// Big Endian problem when sending frames fixed.
//
// Revision 1.14 2002/03/02 19:12:40 mohor
// Byte ordering changed (Big Endian used). casex changed with case because
// Xilinx Foundation had problems. Tested in HW. It WORKS.
//
// Revision 1.13 2002/02/26 16:59:55 mohor
// Small fixes for external/internal DMA missmatches.
//
// Revision 1.12 2002/02/26 16:22:07 mohor
// Interrupts changed
//
// Revision 1.11 2002/02/15 17:07:39 mohor
// Status was not written correctly when frames were discarted because of
// address mismatch.
//
// Revision 1.10 2002/02/15 12:17:39 mohor
// RxStartFrm cleared when abort or retry comes.
//
// Revision 1.9 2002/02/15 11:59:10 mohor
// Changes that were lost when updating from 1.5 to 1.8 fixed.
//
// Revision 1.8 2002/02/14 20:54:33 billditt
// Addition of new module eth_addrcheck.v
//
// Revision 1.7 2002/02/12 17:03:47 mohor
// RxOverRun added to statuses.
//
// Revision 1.6 2002/02/11 09:18:22 mohor
// Tx status is written back to the BD.
//
// Revision 1.5 2002/02/08 16:21:54 mohor
// Rx status is written back to the BD.
//
// Revision 1.4 2002/02/06 14:10:21 mohor
// non-DMA host interface added. Select the right configutation in eth_defines.
//
// Revision 1.3 2002/02/05 16:44:39 mohor
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
// MHz. Statuses, overrun, control frame transmission and reception still need
// to be fixed.
//
// Revision 1.2 2002/02/01 12:46:51 mohor
// Tx part finished. TxStatus needs to be fixed. Pause request needs to be
// added.
//
// Revision 1.1 2002/01/23 10:47:59 mohor
// Initial version. Equals to eth_wishbonedma.v at this moment.
//
//
//
`include "eth_defines.v"
`include "timescale.v"
module eth_wishbone
(
// WISHBONE common
WB_CLK_I, WB_DAT_I, WB_DAT_O,
// WISHBONE slave
WB_ADR_I, WB_WE_I, WB_ACK_O,
BDCs,
Reset,
// WISHBONE master
m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
`ifdef ETH_WISHBONE_B3
m_wb_cti_o, m_wb_bte_o,
`endif
//TX
MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,
PerPacketPad,
//RX
MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort, RxStatusWriteLatched_sync2,
// Register
r_TxEn, r_RxEn, r_TxBDNum, r_RxFlow, r_PassAll,
// Interrupts
TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
// Rx Status
InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood, AddressMiss,
ReceivedPauseFrm,
// Tx Status
RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, RstDeferLatched, CarrierSenseLost
// Bist
`ifdef ETH_BIST
,
// debug chain signals
mbist_si_i, // bist scan serial in
mbist_so_o, // bist scan serial out
mbist_ctrl_i // bist chain shift control
`endif
);
parameter Tp = 1;
// WISHBONE common
input WB_CLK_I; // WISHBONE clock
input [31:0] WB_DAT_I; // WISHBONE data input
output [31:0] WB_DAT_O; // WISHBONE data output
// WISHBONE slave
input [9:2] WB_ADR_I; // WISHBONE address input
input WB_WE_I; // WISHBONE write enable input
input [3:0] BDCs; // Buffer descriptors are selected
output WB_ACK_O; // WISHBONE acknowledge output
// WISHBONE master
output [29:0] m_wb_adr_o; //
output [3:0] m_wb_sel_o; //
output m_wb_we_o; //
output [31:0] m_wb_dat_o; //
output m_wb_cyc_o; //
output m_wb_stb_o; //
input [31:0] m_wb_dat_i; //
input m_wb_ack_i; //
input m_wb_err_i; //
`ifdef ETH_WISHBONE_B3
output [2:0] m_wb_cti_o; // Cycle Type Identifier
output [1:0] m_wb_bte_o; // Burst Type Extension
reg [2:0] m_wb_cti_o; // Cycle Type Identifier
`endif
input Reset; // Reset signal
// Rx Status signals
input InvalidSymbol; // Invalid symbol was received during reception in 100 Mbps mode
input LatchedCrcError; // CRC error
input RxLateCollision; // Late collision occured while receiving frame
input ShortFrame; // Frame shorter then the minimum size (r_MinFL) was received while small packets are enabled (r_RecSmall)
input DribbleNibble; // Extra nibble received
input ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL
input [15:0] RxLength; // Length of the incoming frame
input LoadRxStatus; // Rx status was loaded
input ReceivedPacketGood;// Received packet's length and CRC are good
input AddressMiss; // When a packet is received AddressMiss status is written to the Rx BD
input r_RxFlow;
input r_PassAll;
input ReceivedPauseFrm;
// Tx Status signals
input [3:0] RetryCntLatched; // Latched Retry Counter
input RetryLimit; // Retry limit reached (Retry Max value + 1 attempts were made)
input LateCollLatched; // Late collision occured
input DeferLatched; // Defer indication (Frame was defered before sucessfully sent)
output RstDeferLatched;
input CarrierSenseLost; // Carrier Sense was lost during the frame transmission
// Tx
input MTxClk; // Transmit clock (from PHY)
input TxUsedData; // Transmit packet used data
input TxRetry; // Transmit packet retry
input TxAbort; // Transmit packet abort
input TxDone; // Transmission ended
output TxStartFrm; // Transmit packet start frame
output TxEndFrm; // Transmit packet end frame
output [7:0] TxData; // Transmit packet data byte
output TxUnderRun; // Transmit packet under-run
output PerPacketCrcEn; // Per packet crc enable
output PerPacketPad; // Per packet pading
// Rx
input MRxClk; // Receive clock (from PHY)
input [7:0] RxData; // Received data byte (from PHY)
input RxValid; //
input RxStartFrm; //
input RxEndFrm; //
input RxAbort; // This signal is set when address doesn't match.
output RxStatusWriteLatched_sync2;
//Register
input r_TxEn; // Transmit enable
input r_RxEn; // Receive enable
input [7:0] r_TxBDNum; // Receive buffer descriptor number
// Interrupts
output TxB_IRQ;
output TxE_IRQ;
output RxB_IRQ;
output RxE_IRQ;
output Busy_IRQ;
// Bist
`ifdef ETH_BIST
input mbist_si_i; // bist scan serial in
output mbist_so_o; // bist scan serial out
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
`endif
reg TxB_IRQ;
reg TxE_IRQ;
reg RxB_IRQ;
reg RxE_IRQ;
reg TxStartFrm;
reg TxEndFrm;
reg [7:0] TxData;
reg TxUnderRun;
reg TxUnderRun_wb;
reg TxBDRead;
wire TxStatusWrite;
reg [1:0] TxValidBytesLatched;
reg [15:0] TxLength;
reg [15:0] LatchedTxLength;
reg [14:11] TxStatus;
reg [14:13] RxStatus;
wire [14:13] RxStatus_s;
reg TxStartFrm_wb;
reg TxRetry_wb;
reg TxAbort_wb;
reg TxDone_wb;
reg TxDone_wb_q;
reg TxAbort_wb_q;
reg TxRetry_wb_q;
reg TxRetryPacket;
reg TxRetryPacket_NotCleared;
reg TxDonePacket;
reg TxDonePacket_NotCleared;
reg TxAbortPacket;
reg TxAbortPacket_NotCleared;
reg RxBDReady;
reg RxReady;
reg TxBDReady;
reg RxBDRead;
reg [31:0] TxDataLatched;
reg [1:0] TxByteCnt;
reg LastWord;
reg ReadTxDataFromFifo_tck;
reg BlockingTxStatusWrite;
reg BlockingTxBDRead;
reg Flop;
reg [7:1] TxBDAddress;
reg [7:1] RxBDAddress;
reg TxRetrySync1;
reg TxAbortSync1;
reg TxDoneSync1;
reg TxAbort_q;
reg TxRetry_q;
reg TxUsedData_q;
reg [31:0] RxDataLatched2;
reg [31:8] RxDataLatched1; // Big Endian Byte Ordering
reg [1:0] RxValidBytes;
reg [1:0] RxByteCnt;
reg LastByteIn;
reg ShiftWillEnd;
reg WriteRxDataToFifo;
reg [15:0] LatchedRxLength;
reg RxAbortLatched;
reg ShiftEnded;
reg RxOverrun;
reg [3:0] BDWrite; // BD Write Enable for access from WISHBONE side
reg BDRead; // BD Read access from WISHBONE side
wire [31:0] RxBDDataIn; // Rx BD data in
wire [31:0] TxBDDataIn; // Tx BD data in
reg TxEndFrm_wb;
wire TxRetryPulse;
wire TxDonePulse;
wire TxAbortPulse;
wire StartRxBDRead;
wire StartTxBDRead;
wire TxIRQEn;
wire WrapTxStatusBit;
wire RxIRQEn;
wire WrapRxStatusBit;
wire [1:0] TxValidBytes;
wire [7:1] TempTxBDAddress;
wire [7:1] TempRxBDAddress;
wire RxStatusWrite;
wire RxBufferFull;
wire RxBufferAlmostEmpty;
wire RxBufferEmpty;
reg WB_ACK_O;
wire [8:0] RxStatusIn;
reg [8:0] RxStatusInLatched;
reg WbEn, WbEn_q;
reg RxEn, RxEn_q;
reg TxEn, TxEn_q;
reg r_TxEn_q;
reg r_RxEn_q;
wire ram_ce;
wire [3:0] ram_we;
wire ram_oe;
reg [7:0] ram_addr;
reg [31:0] ram_di;
wire [31:0] ram_do;
wire StartTxPointerRead;
reg TxPointerRead;
reg TxEn_needed;
reg RxEn_needed;
wire StartRxPointerRead;
reg RxPointerRead;
`ifdef ETH_WISHBONE_B3
assign m_wb_bte_o = 2'b00; // Linear burst
`endif
assign m_wb_stb_o = m_wb_cyc_o;
always @ (posedge WB_CLK_I)
begin
WB_ACK_O <=#Tp (|BDWrite) & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
end
assign WB_DAT_O = ram_do;
// Generic synchronous single-port RAM interface
eth_spram_256x32 bd_ram (
.clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
`ifdef ETH_BIST
,
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
);
assign ram_ce = 1'b1;
assign ram_we = (BDWrite & {4{(WbEn & WbEn_q)}}) | {4{(TxStatusWrite | RxStatusWrite)}};
assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q & (TxBDRead | TxPointerRead) | RxEn & RxEn_q & (RxBDRead | RxPointerRead);
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxEn_needed <=#Tp 1'b0;
else
if(~TxBDReady & r_TxEn & WbEn & ~WbEn_q)
TxEn_needed <=#Tp 1'b1;
else
if(TxPointerRead & TxEn & TxEn_q)
TxEn_needed <=#Tp 1'b0;
end
// Enabling access to the RAM for three devices.
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
begin
WbEn <=#Tp 1'b1;
RxEn <=#Tp 1'b0;
TxEn <=#Tp 1'b0;
ram_addr <=#Tp 8'h0;
ram_di <=#Tp 32'h0;
BDRead <=#Tp 1'b0;
BDWrite <=#Tp 1'b0;
end
else
begin
// Switching between three stages depends on enable signals
case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed}) // synopsys parallel_case
5'b100_10, 5'b100_11 :
begin
WbEn <=#Tp 1'b0;
RxEn <=#Tp 1'b1; // wb access stage and r_RxEn is enabled
TxEn <=#Tp 1'b0;
ram_addr <=#Tp {RxBDAddress, RxPointerRead};
ram_di <=#Tp RxBDDataIn;
end
5'b100_01 :
begin
WbEn <=#Tp 1'b0;
RxEn <=#Tp 1'b0;
TxEn <=#Tp 1'b1; // wb access stage, r_RxEn is disabled but r_TxEn is enabled
ram_addr <=#Tp {TxBDAddress, TxPointerRead};
ram_di <=#Tp TxBDDataIn;
end
5'b010_00, 5'b010_10 :
begin
WbEn <=#Tp 1'b1; // RxEn access stage and r_TxEn is disabled
RxEn <=#Tp 1'b0;
TxEn <=#Tp 1'b0;
ram_addr <=#Tp WB_ADR_I[9:2];
ram_di <=#Tp WB_DAT_I;
BDWrite <=#Tp BDCs[3:0] & {4{WB_WE_I}};
BDRead <=#Tp (|BDCs) & ~WB_WE_I;
end
5'b010_01, 5'b010_11 :
begin
WbEn <=#Tp 1'b0;
RxEn <=#Tp 1'b0;
TxEn <=#Tp 1'b1; // RxEn access stage and r_TxEn is enabled
ram_addr <=#Tp {TxBDAddress, TxPointerRead};
ram_di <=#Tp TxBDDataIn;
end
5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 :
begin
WbEn <=#Tp 1'b1; // TxEn access stage (we always go to wb access stage)
RxEn <=#Tp 1'b0;
TxEn <=#Tp 1'b0;
ram_addr <=#Tp WB_ADR_I[9:2];
ram_di <=#Tp WB_DAT_I;
BDWrite <=#Tp BDCs[3:0] & {4{WB_WE_I}};
BDRead <=#Tp (|BDCs) & ~WB_WE_I;
end
5'b100_00 :
begin
WbEn <=#Tp 1'b0; // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit
end
5'b000_00 :
begin
WbEn <=#Tp 1'b1; // Idle state. We go to WbEn access stage.
RxEn <=#Tp 1'b0;
TxEn <=#Tp 1'b0;
ram_addr <=#Tp WB_ADR_I[9:2];
ram_di <=#Tp WB_DAT_I;
BDWrite <=#Tp BDCs[3:0] & {4{WB_WE_I}};
BDRead <=#Tp (|BDCs) & ~WB_WE_I;
end
endcase
end
end
// Delayed stage signals
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
begin
WbEn_q <=#Tp 1'b0;
RxEn_q <=#Tp 1'b0;
TxEn_q <=#Tp 1'b0;
r_TxEn_q <=#Tp 1'b0;
r_RxEn_q <=#Tp 1'b0;
end
else
begin
WbEn_q <=#Tp WbEn;
RxEn_q <=#Tp RxEn;
TxEn_q <=#Tp TxEn;
r_TxEn_q <=#Tp r_TxEn;
r_RxEn_q <=#Tp r_RxEn;
end
end
// Changes for tx occur every second clock. Flop is used for this manner.
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
Flop <=#Tp 1'b0;
else
if(TxDone | TxAbort | TxRetry_q)
Flop <=#Tp 1'b0;
else
if(TxUsedData)
Flop <=#Tp ~Flop;
end
wire ResetTxBDReady;
assign ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse;
// Latching READY status of the Tx buffer descriptor
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxBDReady <=#Tp 1'b0;
else
if(TxEn & TxEn_q & TxBDRead)
TxBDReady <=#Tp ram_do[15] & (ram_do[31:16] > 4); // TxBDReady is sampled only once at the beginning.
else // Only packets larger then 4 bytes are transmitted.
if(ResetTxBDReady)
TxBDReady <=#Tp 1'b0;
end
// Reading the Tx buffer descriptor
assign StartTxBDRead = (TxRetryPacket_NotCleared | TxStatusWrite) & ~BlockingTxBDRead & ~TxBDReady;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxBDRead <=#Tp 1'b1;
else
if(StartTxBDRead)
TxBDRead <=#Tp 1'b1;
else
if(TxBDReady)
TxBDRead <=#Tp 1'b0;
end
// Reading Tx BD pointer
assign StartTxPointerRead = TxBDRead & TxBDReady;
// Reading Tx BD Pointer
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxPointerRead <=#Tp 1'b0;
else
if(StartTxPointerRead)
TxPointerRead <=#Tp 1'b1;
else
if(TxEn_q)
TxPointerRead <=#Tp 1'b0;
end
// Writing status back to the Tx buffer descriptor
assign TxStatusWrite = (TxDonePacket_NotCleared | TxAbortPacket_NotCleared) & TxEn & TxEn_q & ~BlockingTxStatusWrite;
// Status writing must occur only once. Meanwhile it is blocked.
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
BlockingTxStatusWrite <=#Tp 1'b0;
else
if(~TxDone_wb & ~TxAbort_wb)
BlockingTxStatusWrite <=#Tp 1'b0;
else
if(TxStatusWrite)
BlockingTxStatusWrite <=#Tp 1'b1;
end
reg BlockingTxStatusWrite_sync1;
reg BlockingTxStatusWrite_sync2;
reg BlockingTxStatusWrite_sync3;
// Synchronizing BlockingTxStatusWrite to MTxClk
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
BlockingTxStatusWrite_sync1 <=#Tp 1'b0;
else
BlockingTxStatusWrite_sync1 <=#Tp BlockingTxStatusWrite;
end
// Synchronizing BlockingTxStatusWrite to MTxClk
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
BlockingTxStatusWrite_sync2 <=#Tp 1'b0;
else
BlockingTxStatusWrite_sync2 <=#Tp BlockingTxStatusWrite_sync1;
end
// Synchronizing BlockingTxStatusWrite to MTxClk
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
BlockingTxStatusWrite_sync3 <=#Tp 1'b0;
else
BlockingTxStatusWrite_sync3 <=#Tp BlockingTxStatusWrite_sync2;
end
assign RstDeferLatched = BlockingTxStatusWrite_sync2 & ~BlockingTxStatusWrite_sync3;
// TxBDRead state is activated only once.
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
BlockingTxBDRead <=#Tp 1'b0;
else
if(StartTxBDRead)
BlockingTxBDRead <=#Tp 1'b1;
else
if(~StartTxBDRead & ~TxBDReady)
BlockingTxBDRead <=#Tp 1'b0;
end
// Latching status from the tx buffer descriptor
// Data is avaliable one cycle after the access is started (at that time signal TxEn is not active)
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxStatus <=#Tp 4'h0;
else
if(TxEn & TxEn_q & TxBDRead)
TxStatus <=#Tp ram_do[14:11];
end
reg ReadTxDataFromMemory;
wire WriteRxDataToMemory;
reg MasterWbTX;
reg MasterWbRX;
reg [29:0] m_wb_adr_o;
reg m_wb_cyc_o;
reg [3:0] m_wb_sel_o;
reg m_wb_we_o;
wire TxLengthEq0;
wire TxLengthLt4;
reg BlockingIncrementTxPointer;
reg [31:2] TxPointerMSB;
reg [1:0] TxPointerLSB;
reg [1:0] TxPointerLSB_rst;
reg [31:2] RxPointerMSB;
reg [1:0] RxPointerLSB_rst;
wire RxBurstAcc;
wire RxWordAcc;
wire RxHalfAcc;
wire RxByteAcc;
//Latching length from the buffer descriptor;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxLength <=#Tp 16'h0;
else
if(TxEn & TxEn_q & TxBDRead)
TxLength <=#Tp ram_do[31:16];
else
if(MasterWbTX & m_wb_ack_i)
begin
if(TxLengthLt4)
TxLength <=#Tp 16'h0;
else
if(TxPointerLSB_rst==2'h0)
TxLength <=#Tp TxLength - 3'h4; // Length is subtracted at the data request
else
if(TxPointerLSB_rst==2'h1)
TxLength <=#Tp TxLength - 3'h3; // Length is subtracted at the data request
else
if(TxPointerLSB_rst==2'h2)
TxLength <=#Tp TxLength - 3'h2; // Length is subtracted at the data request
else
if(TxPointerLSB_rst==2'h3)
TxLength <=#Tp TxLength - 3'h1; // Length is subtracted at the data request
end
end
//Latching length from the buffer descriptor;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
LatchedTxLength <=#Tp 16'h0;
else
if(TxEn & TxEn_q & TxBDRead)
LatchedTxLength <=#Tp ram_do[31:16];
end
assign TxLengthEq0 = TxLength == 0;
assign TxLengthLt4 = TxLength < 4;
reg cyc_cleared;
reg IncrTxPointer;
// Latching Tx buffer pointer from buffer descriptor. Only 30 MSB bits are latched
// because TxPointerMSB is only used for word-aligned accesses.
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxPointerMSB <=#Tp 30'h0;
else
if(TxEn & TxEn_q & TxPointerRead)
TxPointerMSB <=#Tp ram_do[31:2];
else
if(IncrTxPointer & ~BlockingIncrementTxPointer)
TxPointerMSB <=#Tp TxPointerMSB + 1'b1; // TxPointer is word-aligned
end
// Latching 2 MSB bits of the buffer descriptor. Since word accesses are performed,
// valid data does not necesserly start at byte 0 (could be byte 0, 1, 2 or 3). This
// signals are used for proper selection of the start byte (TxData and TxByteCnt) are
// set by this two bits.
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxPointerLSB[1:0] <=#Tp 0;
else
if(TxEn & TxEn_q & TxPointerRead)
TxPointerLSB[1:0] <=#Tp ram_do[1:0];
end
// Latching 2 MSB bits of the buffer descriptor.
// After the read access, TxLength needs to be decremented for the number of the valid
// bytes (1 to 4 bytes are valid in the first word). After the first read all bytes are
// valid so this two bits are reset to zero.
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxPointerLSB_rst[1:0] <=#Tp 0;
else
if(TxEn & TxEn_q & TxPointerRead)
TxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
else
if(MasterWbTX & m_wb_ack_i) // After first access pointer is word alligned
TxPointerLSB_rst[1:0] <=#Tp 0;
end
reg [3:0] RxByteSel;
wire MasterAccessFinished;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
BlockingIncrementTxPointer <=#Tp 0;
else
if(MasterAccessFinished)
BlockingIncrementTxPointer <=#Tp 0;
else
if(IncrTxPointer)
BlockingIncrementTxPointer <=#Tp 1'b1;
end
wire TxBufferAlmostFull;
wire TxBufferFull;
wire TxBufferEmpty;
wire TxBufferAlmostEmpty;
wire SetReadTxDataFromMemory;
reg BlockReadTxDataFromMemory;
assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
ReadTxDataFromMemory <=#Tp 1'b0;
else
if(TxLengthEq0 | TxAbortPulse | TxRetryPulse)
ReadTxDataFromMemory <=#Tp 1'b0;
else
if(SetReadTxDataFromMemory)
ReadTxDataFromMemory <=#Tp 1'b1;
end
reg tx_burst_en;
reg rx_burst_en;
wire ReadTxDataFromMemory_2 = ReadTxDataFromMemory & ~BlockReadTxDataFromMemory;
wire tx_burst = ReadTxDataFromMemory_2 & tx_burst_en;
wire [31:0] TxData_wb;
wire ReadTxDataFromFifo_wb;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
BlockReadTxDataFromMemory <=#Tp 1'b0;
else
if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX & (~cyc_cleared) & (!(TxAbortPacket_NotCleared | TxRetryPacket_NotCleared)))
BlockReadTxDataFromMemory <=#Tp 1'b1;
else
if(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket | TxRetryPacket)
BlockReadTxDataFromMemory <=#Tp 1'b0;
end
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
wire [`ETH_TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt;
reg [`ETH_BURST_CNT_WIDTH-1:0] tx_burst_cnt;
reg [`ETH_BURST_CNT_WIDTH-1:0] rx_burst_cnt;
wire rx_burst;
wire enough_data_in_rxfifo_for_burst;
wire enough_data_in_rxfifo_for_burst_plus1;
// Enabling master wishbone access to the memory for two devices TX and RX.
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
begin
MasterWbTX <=#Tp 1'b0;
MasterWbRX <=#Tp 1'b0;
m_wb_adr_o <=#Tp 30'h0;
m_wb_cyc_o <=#Tp 1'b0;
m_wb_we_o <=#Tp 1'b0;
m_wb_sel_o <=#Tp 4'h0;
cyc_cleared<=#Tp 1'b0;
tx_burst_cnt<=#Tp 0;
rx_burst_cnt<=#Tp 0;
IncrTxPointer<=#Tp 1'b0;
tx_burst_en<=#Tp 1'b1;
rx_burst_en<=#Tp 1'b0;
`ifdef ETH_WISHBONE_B3
m_wb_cti_o <=#Tp 3'b0;
`endif
end
else
begin
// Switching between two stages depends on enable signals
casex ({MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished, cyc_cleared, tx_burst, rx_burst}) // synopsys parallel_case
8'b00_10_00_10, // Idle and MRB needed
8'b10_1x_10_1x, // MRB continues
8'b10_10_01_10, // Clear (previously MR) and MRB needed
8'b01_1x_01_1x : // Clear (previously MW) and MRB needed
begin
MasterWbTX <=#Tp 1'b1; // tx burst
MasterWbRX <=#Tp 1'b0;
m_wb_cyc_o <=#Tp 1'b1;
m_wb_we_o <=#Tp 1'b0;
m_wb_sel_o <=#Tp 4'hf;
cyc_cleared<=#Tp 1'b0;
IncrTxPointer<=#Tp 1'b1;
tx_burst_cnt <=#Tp tx_burst_cnt+3'h1;
if(tx_burst_cnt==0)
m_wb_adr_o <=#Tp TxPointerMSB;
else
m_wb_adr_o <=#Tp m_wb_adr_o+1'b1;
if(tx_burst_cnt==(`ETH_BURST_LENGTH-1))
begin
tx_burst_en<=#Tp 1'b0;
`ifdef ETH_WISHBONE_B3
m_wb_cti_o <=#Tp 3'b111;
`endif
end
else
begin
`ifdef ETH_WISHBONE_B3
m_wb_cti_o <=#Tp 3'b010;
`endif
end
end
8'b00_x1_00_x1, // Idle and MWB needed
8'b01_x1_10_x1, // MWB continues
8'b01_01_01_01, // Clear (previously MW) and MWB needed
8'b10_x1_01_x1 : // Clear (previously MR) and MWB needed
begin
MasterWbTX <=#Tp 1'b0; // rx burst
MasterWbRX <=#Tp 1'b1;
m_wb_cyc_o <=#Tp 1'b1;
m_wb_we_o <=#Tp 1'b1;
m_wb_sel_o <=#Tp RxByteSel;
IncrTxPointer<=#Tp 1'b0;
cyc_cleared<=#Tp 1'b0;
rx_burst_cnt <=#Tp rx_burst_cnt+3'h1;
if(rx_burst_cnt==0)
m_wb_adr_o <=#Tp RxPointerMSB;
else
m_wb_adr_o <=#Tp m_wb_adr_o+1'b1;
if(rx_burst_cnt==(`ETH_BURST_LENGTH-1))
begin
rx_burst_en<=#Tp 1'b0;
`ifdef ETH_WISHBONE_B3
m_wb_cti_o <=#Tp 3'b111;
`endif
end
else
begin
`ifdef ETH_WISHBONE_B3
m_wb_cti_o <=#Tp 3'b010;
`endif
end
end
8'b00_x1_00_x0 : // idle and MW is needed (data write to rx buffer)
begin
MasterWbTX <=#Tp 1'b0;
MasterWbRX <=#Tp 1'b1;
m_wb_adr_o <=#Tp RxPointerMSB;
m_wb_cyc_o <=#Tp 1'b1;
m_wb_we_o <=#Tp 1'b1;
m_wb_sel_o <=#Tp RxByteSel;
IncrTxPointer<=#Tp 1'b0;
end
8'b00_10_00_00 : // idle and MR is needed (data read from tx buffer)
begin
MasterWbTX <=#Tp 1'b1;
MasterWbRX <=#Tp 1'b0;
m_wb_adr_o <=#Tp TxPointerMSB;
m_wb_cyc_o <=#Tp 1'b1;
m_wb_we_o <=#Tp 1'b0;
m_wb_sel_o <=#Tp 4'hf;
IncrTxPointer<=#Tp 1'b1;
end
8'b10_10_01_00, // MR and MR is needed (data read from tx buffer)
8'b01_1x_01_0x : // MW and MR is needed (data read from tx buffer)
begin
MasterWbTX <=#Tp 1'b1;
MasterWbRX <=#Tp 1'b0;
m_wb_adr_o <=#Tp TxPointerMSB;
m_wb_cyc_o <=#Tp 1'b1;
m_wb_we_o <=#Tp 1'b0;
m_wb_sel_o <=#Tp 4'hf;
cyc_cleared<=#Tp 1'b0;
IncrTxPointer<=#Tp 1'b1;
end
8'b01_01_01_00, // MW and MW needed (data write to rx buffer)
8'b10_x1_01_x0 : // MR and MW is needed (data write to rx buffer)
begin
MasterWbTX <=#Tp 1'b0;
MasterWbRX <=#Tp 1'b1;
m_wb_adr_o <=#Tp RxPointerMSB;
m_wb_cyc_o <=#Tp 1'b1;
m_wb_we_o <=#Tp 1'b1;
m_wb_sel_o <=#Tp RxByteSel;
cyc_cleared<=#Tp 1'b0;
IncrTxPointer<=#Tp 1'b0;
end
8'b01_01_10_00, // MW and MW needed (cycle is cleared between previous and next access)
8'b01_1x_10_x0, // MW and MW or MR or MRB needed (cycle is cleared between previous and next access)
8'b10_10_10_00, // MR and MR needed (cycle is cleared between previous and next access)
8'b10_x1_10_0x : // MR and MR or MW or MWB (cycle is cleared between previous and next access)
begin
m_wb_cyc_o <=#Tp 1'b0; // whatever and master read or write is needed. We need to clear m_wb_cyc_o before next access is started
cyc_cleared<=#Tp 1'b1;
IncrTxPointer<=#Tp 1'b0;
tx_burst_cnt<=#Tp 0;
tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
rx_burst_cnt<=#Tp 0;
rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst; // Counter is not decremented, yet, so plus1 is used.
`ifdef ETH_WISHBONE_B3
m_wb_cti_o <=#Tp 3'b0;
`endif
end
8'bxx_00_10_00, // whatever and no master read or write is needed (ack or err comes finishing previous access)
8'bxx_00_01_00 : // Between cyc_cleared request was cleared
begin
MasterWbTX <=#Tp 1'b0;
MasterWbRX <=#Tp 1'b0;
m_wb_cyc_o <=#Tp 1'b0;
cyc_cleared<=#Tp 1'b0;
IncrTxPointer<=#Tp 1'b0;
rx_burst_cnt<=#Tp 0;
rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst; // Counter is not decremented, yet, so plus1 is used.
`ifdef ETH_WISHBONE_B3
m_wb_cti_o <=#Tp 3'b0;
`endif
end
8'b00_00_00_00: // whatever and no master read or write is needed (ack or err comes finishing previous access)
begin
tx_burst_cnt<=#Tp 0;
tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
end
default: // Don't touch
begin
MasterWbTX <=#Tp MasterWbTX;
MasterWbRX <=#Tp MasterWbRX;
m_wb_cyc_o <=#Tp m_wb_cyc_o;
m_wb_sel_o <=#Tp m_wb_sel_o;
IncrTxPointer<=#Tp IncrTxPointer;
end
endcase
end
end
wire TxFifoClear;
assign TxFifoClear = (TxAbortPacket | TxRetryPacket);
eth_fifo #(`ETH_TX_FIFO_DATA_WIDTH, `ETH_TX_FIFO_DEPTH, `ETH_TX_FIFO_CNT_WIDTH)
tx_fifo ( .data_in(m_wb_dat_i), .data_out(TxData_wb),
.clk(WB_CLK_I), .reset(Reset),
.write(MasterWbTX & m_wb_ack_i), .read(ReadTxDataFromFifo_wb & ~TxBufferEmpty),
.clear(TxFifoClear), .full(TxBufferFull),
.almost_full(TxBufferAlmostFull), .almost_empty(TxBufferAlmostEmpty),
.empty(TxBufferEmpty), .cnt(txfifo_cnt)
);
reg StartOccured;
reg TxStartFrm_sync1;
reg TxStartFrm_sync2;
reg TxStartFrm_syncb1;
reg TxStartFrm_syncb2;
// Start: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxStartFrm_wb <=#Tp 1'b0;
else
if(TxBDReady & ~StartOccured & (TxBufferFull | TxLengthEq0))
TxStartFrm_wb <=#Tp 1'b1;
else
if(TxStartFrm_syncb2)
TxStartFrm_wb <=#Tp 1'b0;
end
// StartOccured: TxStartFrm_wb occurs only ones at the beginning. Then it's blocked.
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
StartOccured <=#Tp 1'b0;
else
if(TxStartFrm_wb)
StartOccured <=#Tp 1'b1;
else
if(ResetTxBDReady)
StartOccured <=#Tp 1'b0;
end
// Synchronizing TxStartFrm_wb to MTxClk
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxStartFrm_sync1 <=#Tp 1'b0;
else
TxStartFrm_sync1 <=#Tp TxStartFrm_wb;
end
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxStartFrm_sync2 <=#Tp 1'b0;
else
TxStartFrm_sync2 <=#Tp TxStartFrm_sync1;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxStartFrm_syncb1 <=#Tp 1'b0;
else
TxStartFrm_syncb1 <=#Tp TxStartFrm_sync2;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxStartFrm_syncb2 <=#Tp 1'b0;
else
TxStartFrm_syncb2 <=#Tp TxStartFrm_syncb1;
end
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxStartFrm <=#Tp 1'b0;
else
if(TxStartFrm_sync2)
TxStartFrm <=#Tp 1'b1;
else
if(TxUsedData_q | ~TxStartFrm_sync2 & (TxRetry & (~TxRetry_q) | TxAbort & (~TxAbort_q)))
TxStartFrm <=#Tp 1'b0;
end
// End: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
// TxEndFrm_wb: indicator of the end of frame
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxEndFrm_wb <=#Tp 1'b0;
else
if(TxLengthEq0 & TxBufferAlmostEmpty & TxUsedData)
TxEndFrm_wb <=#Tp 1'b1;
else
if(TxRetryPulse | TxDonePulse | TxAbortPulse)
TxEndFrm_wb <=#Tp 1'b0;
end
// Marks which bytes are valid within the word.
assign TxValidBytes = TxLengthLt4 ? TxLength[1:0] : 2'b0;
reg LatchValidBytes;
reg LatchValidBytes_q;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
LatchValidBytes <=#Tp 1'b0;
else
if(TxLengthLt4 & TxBDReady)
LatchValidBytes <=#Tp 1'b1;
else
LatchValidBytes <=#Tp 1'b0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
LatchValidBytes_q <=#Tp 1'b0;
else
LatchValidBytes_q <=#Tp LatchValidBytes;
end
// Latching valid bytes
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxValidBytesLatched <=#Tp 2'h0;
else
if(LatchValidBytes & ~LatchValidBytes_q)
TxValidBytesLatched <=#Tp TxValidBytes;
else
if(TxRetryPulse | TxDonePulse | TxAbortPulse)
TxValidBytesLatched <=#Tp 2'h0;
end
assign TxIRQEn = TxStatus[14];
assign WrapTxStatusBit = TxStatus[13];
assign PerPacketPad = TxStatus[12];
assign PerPacketCrcEn = TxStatus[11];
assign RxIRQEn = RxStatus_s[14];
assign WrapRxStatusBit = RxStatus_s[13];
// Temporary Tx and Rx buffer descriptor address
assign TempTxBDAddress[7:1] = {7{ TxStatusWrite & ~WrapTxStatusBit}} & (TxBDAddress + 1'b1) ; // Tx BD increment or wrap (last BD)
assign TempRxBDAddress[7:1] = {7{ WrapRxStatusBit}} & (r_TxBDNum[6:0]) | // Using first Rx BD
{7{~WrapRxStatusBit}} & (RxBDAddress + 1'b1) ; // Using next Rx BD (incremenrement address)
// Latching Tx buffer descriptor address
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxBDAddress <=#Tp 7'h0;
else if (r_TxEn & (~r_TxEn_q))
TxBDAddress <=#Tp 7'h0;
else if (TxStatusWrite)
TxBDAddress <=#Tp TempTxBDAddress;
end
// Latching Rx buffer descriptor address
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxBDAddress <=#Tp 7'h0;
else if(r_RxEn & (~r_RxEn_q))
RxBDAddress <=#Tp r_TxBDNum[6:0];
else if(RxStatusWrite)
RxBDAddress <=#Tp TempRxBDAddress;
end
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus_s, 4'h0, RxStatusInLatched};
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
// Signals used for various purposes
assign TxRetryPulse = TxRetry_wb & ~TxRetry_wb_q;
assign TxDonePulse = TxDone_wb & ~TxDone_wb_q;
assign TxAbortPulse = TxAbort_wb & ~TxAbort_wb_q;
// Generating delayed signals
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
begin
TxAbort_q <=#Tp 1'b0;
TxRetry_q <=#Tp 1'b0;
TxUsedData_q <=#Tp 1'b0;
end
else
begin
TxAbort_q <=#Tp TxAbort;
TxRetry_q <=#Tp TxRetry;
TxUsedData_q <=#Tp TxUsedData;
end
end
// Generating delayed signals
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
begin
TxDone_wb_q <=#Tp 1'b0;
TxAbort_wb_q <=#Tp 1'b0;
TxRetry_wb_q <=#Tp 1'b0;
end
else
begin
TxDone_wb_q <=#Tp TxDone_wb;
TxAbort_wb_q <=#Tp TxAbort_wb;
TxRetry_wb_q <=#Tp TxRetry_wb;
end
end
reg TxAbortPacketBlocked;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxAbortPacket <=#Tp 1'b0;
else
if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished & (~TxAbortPacketBlocked) |
TxAbort_wb & (~MasterWbTX) & (~TxAbortPacketBlocked))
TxAbortPacket <=#Tp 1'b1;
else
TxAbortPacket <=#Tp 1'b0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxAbortPacket_NotCleared <=#Tp 1'b0;
else
if(TxEn & TxEn_q & TxAbortPacket_NotCleared)
TxAbortPacket_NotCleared <=#Tp 1'b0;
else
if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished & (~TxAbortPacketBlocked) |
TxAbort_wb & (~MasterWbTX) & (~TxAbortPacketBlocked))
TxAbortPacket_NotCleared <=#Tp 1'b1;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxAbortPacketBlocked <=#Tp 1'b0;
else
if(!TxAbort_wb & TxAbort_wb_q)
TxAbortPacketBlocked <=#Tp 1'b0;
else
if(TxAbortPacket)
TxAbortPacketBlocked <=#Tp 1'b1;
end
reg TxRetryPacketBlocked;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxRetryPacket <=#Tp 1'b0;
else
if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxRetryPacketBlocked |
TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
TxRetryPacket <=#Tp 1'b1;
else
TxRetryPacket <=#Tp 1'b0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxRetryPacket_NotCleared <=#Tp 1'b0;
else
if(StartTxBDRead)
TxRetryPacket_NotCleared <=#Tp 1'b0;
else
if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxRetryPacketBlocked |
TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
TxRetryPacket_NotCleared <=#Tp 1'b1;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxRetryPacketBlocked <=#Tp 1'b0;
else
if(!TxRetry_wb & TxRetry_wb_q)
TxRetryPacketBlocked <=#Tp 1'b0;
else
if(TxRetryPacket)
TxRetryPacketBlocked <=#Tp 1'b1;
end
reg TxDonePacketBlocked;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxDonePacket <=#Tp 1'b0;
else
if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxDonePacketBlocked |
TxDone_wb & !MasterWbTX & !TxDonePacketBlocked)
TxDonePacket <=#Tp 1'b1;
else
TxDonePacket <=#Tp 1'b0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxDonePacket_NotCleared <=#Tp 1'b0;
else
if(TxEn & TxEn_q & TxDonePacket_NotCleared)
TxDonePacket_NotCleared <=#Tp 1'b0;
else
if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & (~TxDonePacketBlocked) |
TxDone_wb & !MasterWbTX & (~TxDonePacketBlocked))
TxDonePacket_NotCleared <=#Tp 1'b1;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxDonePacketBlocked <=#Tp 1'b0;
else
if(!TxDone_wb & TxDone_wb_q)
TxDonePacketBlocked <=#Tp 1'b0;
else
if(TxDonePacket)
TxDonePacketBlocked <=#Tp 1'b1;
end
// Indication of the last word
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
LastWord <=#Tp 1'b0;
else
if((TxEndFrm | TxAbort | TxRetry) & Flop)
LastWord <=#Tp 1'b0;
else
if(TxUsedData & Flop & TxByteCnt == 2'h3)
LastWord <=#Tp TxEndFrm_wb;
end
// Tx end frame generation
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxEndFrm <=#Tp 1'b0;
else
if(Flop & TxEndFrm | TxAbort | TxRetry_q)
TxEndFrm <=#Tp 1'b0;
else
if(Flop & LastWord)
begin
case (TxValidBytesLatched) // synopsys parallel_case
1 : TxEndFrm <=#Tp TxByteCnt == 2'h0;
2 : TxEndFrm <=#Tp TxByteCnt == 2'h1;
3 : TxEndFrm <=#Tp TxByteCnt == 2'h2;
0 : TxEndFrm <=#Tp TxByteCnt == 2'h3;
default : TxEndFrm <=#Tp 1'b0;
endcase
end
end
// Tx data selection (latching)
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxData <=#Tp 0;
else
if(TxStartFrm_sync2 & ~TxStartFrm)
case(TxPointerLSB) // synopsys parallel_case
2'h0 : TxData <=#Tp TxData_wb[31:24]; // Big Endian Byte Ordering
2'h1 : TxData <=#Tp TxData_wb[23:16]; // Big Endian Byte Ordering
2'h2 : TxData <=#Tp TxData_wb[15:08]; // Big Endian Byte Ordering
2'h3 : TxData <=#Tp TxData_wb[07:00]; // Big Endian Byte Ordering
endcase
else
if(TxStartFrm & TxUsedData & TxPointerLSB==2'h3)
TxData <=#Tp TxData_wb[31:24]; // Big Endian Byte Ordering
else
if(TxUsedData & Flop)
begin
case(TxByteCnt) // synopsys parallel_case
0 : TxData <=#Tp TxDataLatched[31:24]; // Big Endian Byte Ordering
1 : TxData <=#Tp TxDataLatched[23:16];
2 : TxData <=#Tp TxDataLatched[15:8];
3 : TxData <=#Tp TxDataLatched[7:0];
endcase
end
end
// Latching tx data
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxDataLatched[31:0] <=#Tp 32'h0;
else
if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
TxDataLatched[31:0] <=#Tp TxData_wb[31:0];
end
// Tx under run
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxUnderRun_wb <=#Tp 1'b0;
else
if(TxAbortPulse)
TxUnderRun_wb <=#Tp 1'b0;
else
if(TxBufferEmpty & ReadTxDataFromFifo_wb)
TxUnderRun_wb <=#Tp 1'b1;
end
reg TxUnderRun_sync1;
// Tx under run
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxUnderRun_sync1 <=#Tp 1'b0;
else
if(TxUnderRun_wb)
TxUnderRun_sync1 <=#Tp 1'b1;
else
if(BlockingTxStatusWrite_sync2)
TxUnderRun_sync1 <=#Tp 1'b0;
end
// Tx under run
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxUnderRun <=#Tp 1'b0;
else
if(BlockingTxStatusWrite_sync2)
TxUnderRun <=#Tp 1'b0;
else
if(TxUnderRun_sync1)
TxUnderRun <=#Tp 1'b1;
end
// Tx Byte counter
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxByteCnt <=#Tp 2'h0;
else
if(TxAbort_q | TxRetry_q)
TxByteCnt <=#Tp 2'h0;
else
if(TxStartFrm & ~TxUsedData)
case(TxPointerLSB) // synopsys parallel_case
2'h0 : TxByteCnt <=#Tp 2'h1;
2'h1 : TxByteCnt <=#Tp 2'h2;
2'h2 : TxByteCnt <=#Tp 2'h3;
2'h3 : TxByteCnt <=#Tp 2'h0;
endcase
else
if(TxUsedData & Flop)
TxByteCnt <=#Tp TxByteCnt + 1'b1;
end
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
reg ReadTxDataFromFifo_sync1;
reg ReadTxDataFromFifo_sync2;
reg ReadTxDataFromFifo_sync3;
reg ReadTxDataFromFifo_syncb1;
reg ReadTxDataFromFifo_syncb2;
reg ReadTxDataFromFifo_syncb3;
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
ReadTxDataFromFifo_tck <=#Tp 1'b0;
else
if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 & ~LastWord | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
ReadTxDataFromFifo_tck <=#Tp 1'b1;
else
if(ReadTxDataFromFifo_syncb2 & ~ReadTxDataFromFifo_syncb3)
ReadTxDataFromFifo_tck <=#Tp 1'b0;
end
// Synchronizing TxStartFrm_wb to MTxClk
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
ReadTxDataFromFifo_sync1 <=#Tp 1'b0;
else
ReadTxDataFromFifo_sync1 <=#Tp ReadTxDataFromFifo_tck;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
ReadTxDataFromFifo_sync2 <=#Tp 1'b0;
else
ReadTxDataFromFifo_sync2 <=#Tp ReadTxDataFromFifo_sync1;
end
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
ReadTxDataFromFifo_syncb1 <=#Tp 1'b0;
else
ReadTxDataFromFifo_syncb1 <=#Tp ReadTxDataFromFifo_sync2;
end
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
ReadTxDataFromFifo_syncb2 <=#Tp 1'b0;
else
ReadTxDataFromFifo_syncb2 <=#Tp ReadTxDataFromFifo_syncb1;
end
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
ReadTxDataFromFifo_syncb3 <=#Tp 1'b0;
else
ReadTxDataFromFifo_syncb3 <=#Tp ReadTxDataFromFifo_syncb2;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
ReadTxDataFromFifo_sync3 <=#Tp 1'b0;
else
ReadTxDataFromFifo_sync3 <=#Tp ReadTxDataFromFifo_sync2;
end
assign ReadTxDataFromFifo_wb = ReadTxDataFromFifo_sync2 & ~ReadTxDataFromFifo_sync3;
// End: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
// Synchronizing TxRetry signal (synchronized to WISHBONE clock)
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxRetrySync1 <=#Tp 1'b0;
else
TxRetrySync1 <=#Tp TxRetry;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxRetry_wb <=#Tp 1'b0;
else
TxRetry_wb <=#Tp TxRetrySync1;
end
// Synchronized TxDone_wb signal (synchronized to WISHBONE clock)
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxDoneSync1 <=#Tp 1'b0;
else
TxDoneSync1 <=#Tp TxDone;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxDone_wb <=#Tp 1'b0;
else
TxDone_wb <=#Tp TxDoneSync1;
end
// Synchronizing TxAbort signal (synchronized to WISHBONE clock)
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxAbortSync1 <=#Tp 1'b0;
else
TxAbortSync1 <=#Tp TxAbort;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxAbort_wb <=#Tp 1'b0;
else
TxAbort_wb <=#Tp TxAbortSync1;
end
reg RxAbortSync1;
reg RxAbortSync2;
reg RxAbortSync3;
reg RxAbortSync4;
reg RxAbortSyncb1;
reg RxAbortSyncb2;
assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4 | r_RxEn & ~r_RxEn_q;
// Reading the Rx buffer descriptor
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxBDRead <=#Tp 1'b0;
else
if(StartRxBDRead & ~RxReady)
RxBDRead <=#Tp 1'b1;
else
if(RxBDReady)
RxBDRead <=#Tp 1'b0;
end
// Reading of the next receive buffer descriptor starts after reception status is
// written to the previous one.
// Latching READY status of the Rx buffer descriptor
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxBDReady <=#Tp 1'b0;
else
if(RxPointerRead)
RxBDReady <=#Tp 1'b0;
else
if(RxEn & RxEn_q & RxBDRead)
RxBDReady <=#Tp ram_do[15]; // RxBDReady is sampled only once at the beginning
end
// Latching Rx buffer descriptor status
// Data is avaliable one cycle after the access is started (at that time signal RxEn is not active)
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxStatus <=#Tp 2'h0;
else
if(RxEn & RxEn_q & RxBDRead)
RxStatus <=#Tp ram_do[14:13];
end
// Need the RxStatus 1 cycle early when doing an RxStatusWrite immediately after a read
assign RxStatus_s = (RxEn & RxEn_q & RxBDRead) ? ram_do[14:13] : RxStatus;
// RxReady generation
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxReady <=#Tp 1'b0;
else
if(ShiftEnded | RxAbortSync2 & ~RxAbortSync3 | ~r_RxEn & r_RxEn_q)
RxReady <=#Tp 1'b0;
else
if(RxEn & RxEn_q & RxPointerRead)
RxReady <=#Tp 1'b1;
end
// Reading Rx BD pointer
assign StartRxPointerRead = RxBDRead & RxBDReady;
// Reading Tx BD Pointer
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxPointerRead <=#Tp 1'b0;
else
if(StartRxPointerRead)
RxPointerRead <=#Tp 1'b1;
else
if(RxEn & RxEn_q)
RxPointerRead <=#Tp 1'b0;
end
//Latching Rx buffer pointer from buffer descriptor;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxPointerMSB <=#Tp 30'h0;
else
if(RxEn & RxEn_q & RxPointerRead)
RxPointerMSB <=#Tp ram_do[31:2];
else
if(MasterWbRX & m_wb_ack_i)
RxPointerMSB <=#Tp RxPointerMSB + 1'b1; // Word access (always word access. m_wb_sel_o are used for selecting bytes)
end
//Latching last addresses from buffer descriptor (used as byte-half-word indicator);
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxPointerLSB_rst[1:0] <=#Tp 0;
else
if(MasterWbRX & m_wb_ack_i) // After first write all RxByteSel are active
RxPointerLSB_rst[1:0] <=#Tp 0;
else
if(RxEn & RxEn_q & RxPointerRead)
RxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
end
always @ (RxPointerLSB_rst)
begin
case(RxPointerLSB_rst[1:0]) // synopsys parallel_case
2'h0 : RxByteSel[3:0] = 4'hf;
2'h1 : RxByteSel[3:0] = 4'h7;
2'h2 : RxByteSel[3:0] = 4'h3;
2'h3 : RxByteSel[3:0] = 4'h1;
endcase
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxEn_needed <=#Tp 1'b0;
else
if(~RxReady & r_RxEn & WbEn & ~WbEn_q)
RxEn_needed <=#Tp 1'b1;
else
if(RxPointerRead & RxEn & RxEn_q)
RxEn_needed <=#Tp 1'b0;
end
// Reception status is written back to the buffer descriptor after the end of frame is detected.
assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q;
reg RxEnableWindow;
// Indicating that last byte is being reveived
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
LastByteIn <=#Tp 1'b0;
else
if(ShiftWillEnd & (&RxByteCnt) | RxAbort)
LastByteIn <=#Tp 1'b0;
else
if(RxValid & RxReady & RxEndFrm & ~(&RxByteCnt) & RxEnableWindow)
LastByteIn <=#Tp 1'b1;
end
reg ShiftEnded_rck;
reg ShiftEndedSync1;
reg ShiftEndedSync2;
reg ShiftEndedSync3;
reg ShiftEndedSync_c1;
reg ShiftEndedSync_c2;
wire StartShiftWillEnd;
assign StartShiftWillEnd = LastByteIn | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow;
// Indicating that data reception will end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ShiftWillEnd <=#Tp 1'b0;
else
if(ShiftEnded_rck | RxAbort)
ShiftWillEnd <=#Tp 1'b0;
else
if(StartShiftWillEnd)
ShiftWillEnd <=#Tp 1'b1;
end
// Receive byte counter
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxByteCnt <=#Tp 2'h0;
else
if(ShiftEnded_rck | RxAbort)
RxByteCnt <=#Tp 2'h0;
else
if(RxValid & RxStartFrm & RxReady)
case(RxPointerLSB_rst) // synopsys parallel_case
2'h0 : RxByteCnt <=#Tp 2'h1;
2'h1 : RxByteCnt <=#Tp 2'h2;
2'h2 : RxByteCnt <=#Tp 2'h3;
2'h3 : RxByteCnt <=#Tp 2'h0;
endcase
else
if(RxValid & RxEnableWindow & RxReady | LastByteIn)
RxByteCnt <=#Tp RxByteCnt + 1'b1;
end
// Indicates how many bytes are valid within the last word
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxValidBytes <=#Tp 2'h1;
else
if(RxValid & RxStartFrm)
case(RxPointerLSB_rst) // synopsys parallel_case
2'h0 : RxValidBytes <=#Tp 2'h1;
2'h1 : RxValidBytes <=#Tp 2'h2;
2'h2 : RxValidBytes <=#Tp 2'h3;
2'h3 : RxValidBytes <=#Tp 2'h0;
endcase
else
if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow)
RxValidBytes <=#Tp RxValidBytes + 1'b1;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxDataLatched1 <=#Tp 24'h0;
else
if(RxValid & RxReady & ~LastByteIn)
if(RxStartFrm)
begin
case(RxPointerLSB_rst) // synopsys parallel_case
2'h0: RxDataLatched1[31:24] <=#Tp RxData; // Big Endian Byte Ordering
2'h1: RxDataLatched1[23:16] <=#Tp RxData;
2'h2: RxDataLatched1[15:8] <=#Tp RxData;
2'h3: RxDataLatched1 <=#Tp RxDataLatched1;
endcase
end
else if (RxEnableWindow)
begin
case(RxByteCnt) // synopsys parallel_case
2'h0: RxDataLatched1[31:24] <=#Tp RxData; // Big Endian Byte Ordering
2'h1: RxDataLatched1[23:16] <=#Tp RxData;
2'h2: RxDataLatched1[15:8] <=#Tp RxData;
2'h3: RxDataLatched1 <=#Tp RxDataLatched1;
endcase
end
end
wire SetWriteRxDataToFifo;
// Assembling data that will be written to the rx_fifo
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxDataLatched2 <=#Tp 32'h0;
else
if(SetWriteRxDataToFifo & ~ShiftWillEnd)
RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData}; // Big Endian Byte Ordering
else
if(SetWriteRxDataToFifo & ShiftWillEnd)
case(RxValidBytes) // synopsys parallel_case
0 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData}; // Big Endian Byte Ordering
1 : RxDataLatched2 <=#Tp {RxDataLatched1[31:24], 24'h0};
2 : RxDataLatched2 <=#Tp {RxDataLatched1[31:16], 16'h0};
3 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8], 8'h0};
endcase
end
reg WriteRxDataToFifoSync1;
reg WriteRxDataToFifoSync2;
reg WriteRxDataToFifoSync3;
// Indicating start of the reception process
assign SetWriteRxDataToFifo = (RxValid & RxReady & ~RxStartFrm & RxEnableWindow & (&RxByteCnt)) |
(RxValid & RxReady & RxStartFrm & (&RxPointerLSB_rst)) |
(ShiftWillEnd & LastByteIn & (&RxByteCnt));
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
WriteRxDataToFifo <=#Tp 1'b0;
else
if(SetWriteRxDataToFifo & ~RxAbort)
WriteRxDataToFifo <=#Tp 1'b1;
else
if(WriteRxDataToFifoSync2 | RxAbort)
WriteRxDataToFifo <=#Tp 1'b0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
WriteRxDataToFifoSync1 <=#Tp 1'b0;
else
if(WriteRxDataToFifo)
WriteRxDataToFifoSync1 <=#Tp 1'b1;
else
WriteRxDataToFifoSync1 <=#Tp 1'b0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
WriteRxDataToFifoSync2 <=#Tp 1'b0;
else
WriteRxDataToFifoSync2 <=#Tp WriteRxDataToFifoSync1;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
WriteRxDataToFifoSync3 <=#Tp 1'b0;
else
WriteRxDataToFifoSync3 <=#Tp WriteRxDataToFifoSync2;
end
wire WriteRxDataToFifo_wb;
assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync2 & ~WriteRxDataToFifoSync3;
reg LatchedRxStartFrm;
reg SyncRxStartFrm;
reg SyncRxStartFrm_q;
reg SyncRxStartFrm_q2;
wire RxFifoReset;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
LatchedRxStartFrm <=#Tp 0;
else
if(RxStartFrm & ~SyncRxStartFrm_q)
LatchedRxStartFrm <=#Tp 1;
else
if(SyncRxStartFrm_q)
LatchedRxStartFrm <=#Tp 0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
SyncRxStartFrm <=#Tp 0;
else
if(LatchedRxStartFrm)
SyncRxStartFrm <=#Tp 1;
else
SyncRxStartFrm <=#Tp 0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
SyncRxStartFrm_q <=#Tp 0;
else
SyncRxStartFrm_q <=#Tp SyncRxStartFrm;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
SyncRxStartFrm_q2 <=#Tp 0;
else
SyncRxStartFrm_q2 <=#Tp SyncRxStartFrm_q;
end
assign RxFifoReset = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;
eth_fifo #(`ETH_RX_FIFO_DATA_WIDTH, `ETH_RX_FIFO_DEPTH, `ETH_RX_FIFO_CNT_WIDTH)
rx_fifo (.data_in(RxDataLatched2), .data_out(m_wb_dat_o),
.clk(WB_CLK_I), .reset(Reset),
.write(WriteRxDataToFifo_wb & ~RxBufferFull), .read(MasterWbRX & m_wb_ack_i),
.clear(RxFifoReset), .full(RxBufferFull),
.almost_full(), .almost_empty(RxBufferAlmostEmpty),
.empty(RxBufferEmpty), .cnt(rxfifo_cnt)
);
assign enough_data_in_rxfifo_for_burst = rxfifo_cnt>=`ETH_BURST_LENGTH;
assign enough_data_in_rxfifo_for_burst_plus1 = rxfifo_cnt>`ETH_BURST_LENGTH;
assign WriteRxDataToMemory = ~RxBufferEmpty;
assign rx_burst = rx_burst_en & WriteRxDataToMemory;
// Generation of the end-of-frame signal
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ShiftEnded_rck <=#Tp 1'b0;
else
if(~RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd)
ShiftEnded_rck <=#Tp 1'b1;
else
if(RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2)
ShiftEnded_rck <=#Tp 1'b0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
ShiftEndedSync1 <=#Tp 1'b0;
else
ShiftEndedSync1 <=#Tp ShiftEnded_rck;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
ShiftEndedSync2 <=#Tp 1'b0;
else
ShiftEndedSync2 <=#Tp ShiftEndedSync1;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
ShiftEndedSync3 <=#Tp 1'b0;
else
if(ShiftEndedSync1 & ~ShiftEndedSync2)
ShiftEndedSync3 <=#Tp 1'b1;
else
if(ShiftEnded)
ShiftEndedSync3 <=#Tp 1'b0;
end
// Generation of the end-of-frame signal
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
ShiftEnded <=#Tp 1'b0;
else
if(ShiftEndedSync3 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty & ~ShiftEnded)
ShiftEnded <=#Tp 1'b1;
else
if(RxStatusWrite)
ShiftEnded <=#Tp 1'b0;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ShiftEndedSync_c1 <=#Tp 1'b0;
else
ShiftEndedSync_c1 <=#Tp ShiftEndedSync2;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ShiftEndedSync_c2 <=#Tp 1'b0;
else
ShiftEndedSync_c2 <=#Tp ShiftEndedSync_c1;
end
// Generation of the end-of-frame signal
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxEnableWindow <=#Tp 1'b0;
else
if(RxStartFrm)
RxEnableWindow <=#Tp 1'b1;
else
if(RxEndFrm | RxAbort)
RxEnableWindow <=#Tp 1'b0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxAbortSync1 <=#Tp 1'b0;
else
RxAbortSync1 <=#Tp RxAbortLatched;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxAbortSync2 <=#Tp 1'b0;
else
RxAbortSync2 <=#Tp RxAbortSync1;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxAbortSync3 <=#Tp 1'b0;
else
RxAbortSync3 <=#Tp RxAbortSync2;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxAbortSync4 <=#Tp 1'b0;
else
RxAbortSync4 <=#Tp RxAbortSync3;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxAbortSyncb1 <=#Tp 1'b0;
else
RxAbortSyncb1 <=#Tp RxAbortSync2;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxAbortSyncb2 <=#Tp 1'b0;
else
RxAbortSyncb2 <=#Tp RxAbortSyncb1;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxAbortLatched <=#Tp 1'b0;
else
if(RxAbortSyncb2)
RxAbortLatched <=#Tp 1'b0;
else
if(RxAbort)
RxAbortLatched <=#Tp 1'b1;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
LatchedRxLength[15:0] <=#Tp 16'h0;
else
if(LoadRxStatus)
LatchedRxLength[15:0] <=#Tp RxLength[15:0];
end
assign RxStatusIn = {ReceivedPauseFrm, AddressMiss, RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxStatusInLatched <=#Tp 'h0;
else
if(LoadRxStatus)
RxStatusInLatched <=#Tp RxStatusIn;
end
// Rx overrun
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxOverrun <=#Tp 1'b0;
else
if(RxStatusWrite)
RxOverrun <=#Tp 1'b0;
else
if(RxBufferFull & WriteRxDataToFifo_wb)
RxOverrun <=#Tp 1'b1;
end
wire TxError;
assign TxError = TxUnderRun | RetryLimit | LateCollLatched | CarrierSenseLost;
wire RxError;
// ShortFrame (RxStatusInLatched[2]) can not set an error because short frames
// are aborted when signal r_RecSmall is set to 0 in MODER register.
// AddressMiss is identifying that a frame was received because of the promiscous
// mode and is not an error
assign RxError = (|RxStatusInLatched[6:3]) | (|RxStatusInLatched[1:0]);
reg RxStatusWriteLatched;
reg RxStatusWriteLatched_sync1;
reg RxStatusWriteLatched_sync2;
reg RxStatusWriteLatched_syncb1;
reg RxStatusWriteLatched_syncb2;
// Latching and synchronizing RxStatusWrite signal. This signal is used for clearing the ReceivedPauseFrm signal
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxStatusWriteLatched <=#Tp 1'b0;
else
if(RxStatusWriteLatched_syncb2)
RxStatusWriteLatched <=#Tp 1'b0;
else
if(RxStatusWrite)
RxStatusWriteLatched <=#Tp 1'b1;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
RxStatusWriteLatched_sync1 <=#Tp 1'b0;
RxStatusWriteLatched_sync2 <=#Tp 1'b0;
end
else
begin
RxStatusWriteLatched_sync1 <=#Tp RxStatusWriteLatched;
RxStatusWriteLatched_sync2 <=#Tp RxStatusWriteLatched_sync1;
end
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
begin
RxStatusWriteLatched_syncb1 <=#Tp 1'b0;
RxStatusWriteLatched_syncb2 <=#Tp 1'b0;
end
else
begin
RxStatusWriteLatched_syncb1 <=#Tp RxStatusWriteLatched_sync2;
RxStatusWriteLatched_syncb2 <=#Tp RxStatusWriteLatched_syncb1;
end
end
// Tx Done Interrupt
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxB_IRQ <=#Tp 1'b0;
else
if(TxStatusWrite & TxIRQEn)
TxB_IRQ <=#Tp ~TxError;
else
TxB_IRQ <=#Tp 1'b0;
end
// Tx Error Interrupt
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxE_IRQ <=#Tp 1'b0;
else
if(TxStatusWrite & TxIRQEn)
TxE_IRQ <=#Tp TxError;
else
TxE_IRQ <=#Tp 1'b0;
end
// Rx Done Interrupt
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxB_IRQ <=#Tp 1'b0;
else
if(RxStatusWrite & RxIRQEn & ReceivedPacketGood & (~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow)))
RxB_IRQ <=#Tp (~RxError);
else
RxB_IRQ <=#Tp 1'b0;
end
// Rx Error Interrupt
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxE_IRQ <=#Tp 1'b0;
else
if(RxStatusWrite & RxIRQEn & (~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow)))
RxE_IRQ <=#Tp RxError;
else
RxE_IRQ <=#Tp 1'b0;
end
// Busy Interrupt
reg Busy_IRQ_rck;
reg Busy_IRQ_sync1;
reg Busy_IRQ_sync2;
reg Busy_IRQ_sync3;
reg Busy_IRQ_syncb1;
reg Busy_IRQ_syncb2;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
Busy_IRQ_rck <=#Tp 1'b0;
else
if(RxValid & RxStartFrm & ~RxReady)
Busy_IRQ_rck <=#Tp 1'b1;
else
if(Busy_IRQ_syncb2)
Busy_IRQ_rck <=#Tp 1'b0;
end
always @ (posedge WB_CLK_I)
begin
Busy_IRQ_sync1 <=#Tp Busy_IRQ_rck;
Busy_IRQ_sync2 <=#Tp Busy_IRQ_sync1;
Busy_IRQ_sync3 <=#Tp Busy_IRQ_sync2;
end
always @ (posedge MRxClk)
begin
Busy_IRQ_syncb1 <=#Tp Busy_IRQ_sync2;
Busy_IRQ_syncb2 <=#Tp Busy_IRQ_syncb1;
end
assign Busy_IRQ = Busy_IRQ_sync2 & ~Busy_IRQ_sync3;
endmodule
|
// $Id: rtr_ip_ctrl_mac.v 5188 2012-08-30 00:31:31Z dub $
/*
Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// input port controller
//==============================================================================
module rtr_ip_ctrl_mac
(clk, reset, router_address, channel_in, route_out_ivc_op, route_out_ivc_orc,
flit_valid_out_ivc, flit_last_out_ivc, flit_head_out_ivc, flit_tail_out_ivc,
route_fast_out_op, route_fast_out_orc, flit_valid_fast_out,
flit_head_fast_out, flit_tail_fast_out, flit_sel_fast_out_ivc,
flit_data_out, flit_sel_in_ivc, flit_sent_in, flit_sel_fast_in,
flit_sent_fast_in, flow_ctrl_out, error);
`include "c_functions.v"
`include "c_constants.v"
`include "rtr_constants.v"
//---------------------------------------------------------------------------
// parameters
//---------------------------------------------------------------------------
// total buffer size per port in flits
parameter buffer_size = 32;
// number of message classes (e.g. request, reply)
parameter num_message_classes = 2;
// number of resource classes (e.g. minimal, adaptive)
parameter num_resource_classes = 2;
// number of VCs per class
parameter num_vcs_per_class = 1;
// number of routers in each dimension
parameter num_routers_per_dim = 4;
// number of dimensions in network
parameter num_dimensions = 2;
// number of nodes per router (a.k.a. consentration factor)
parameter num_nodes_per_router = 1;
// connectivity within each dimension
parameter connectivity = `CONNECTIVITY_LINE;
// select packet format
parameter packet_format = `PACKET_FORMAT_EXPLICIT_LENGTH;
// select type of flow control
parameter flow_ctrl_type = `FLOW_CTRL_TYPE_CREDIT;
// maximum payload length (in flits)
// (note: only used if packet_format==`PACKET_FORMAT_EXPLICIT_LENGTH)
parameter max_payload_length = 4;
// minimum payload length (in flits)
// (note: only used if packet_format==`PACKET_FORMAT_EXPLICIT_LENGTH)
parameter min_payload_length = 1;
// enable link power management
parameter enable_link_pm = 1;
// width of flit payload data
parameter flit_data_width = 64;
// filter out illegal destination ports
// (the intent is to allow synthesis to optimize away the logic associated
// with such turns)
parameter restrict_turns = 1;
// store lookahead routing info in pre-decoded form
// (only useful with dual-path routing enable)
parameter predecode_lar_info = 1;
// select routing function type
parameter routing_type = `ROUTING_TYPE_PHASED_DOR;
// select order of dimension traversal
parameter dim_order = `DIM_ORDER_ASCENDING;
// select implementation variant for flit buffer register file
parameter fb_regfile_type = `REGFILE_TYPE_FF_2D;
// select flit buffer management scheme
parameter fb_mgmt_type = `FB_MGMT_TYPE_STATIC;
// improve timing for peek access
parameter fb_fast_peek = 1;
// select whether to exclude full or non-empty VCs from VC allocation
parameter elig_mask = `ELIG_MASK_NONE;
// use explicit pipeline register between flit buffer and crossbar?
parameter explicit_pipeline_register = 1;
// gate flit buffer write port if bypass succeeds
// (requires explicit pipeline register; may increase cycle time)
parameter gate_buffer_write = 0;
// enable dual-path allocation
parameter dual_path_alloc = 0;
// configure error checking logic
parameter error_capture_mode = `ERROR_CAPTURE_MODE_NO_HOLD;
// ID of current input port
parameter port_id = 0;
parameter reset_type = `RESET_TYPE_ASYNC;
//---------------------------------------------------------------------------
// derived parameters
//---------------------------------------------------------------------------
// width required to select individual resource class
localparam resource_class_idx_width = clogb(num_resource_classes);
// total number of packet classes
localparam num_packet_classes = num_message_classes * num_resource_classes;
// number of VCs
localparam num_vcs = num_packet_classes * num_vcs_per_class;
// width required to select individual VC
localparam vc_idx_width = clogb(num_vcs);
// width required to select individual router in a dimension
localparam dim_addr_width = clogb(num_routers_per_dim);
// width required to select individual router in entire network
localparam router_addr_width = num_dimensions * dim_addr_width;
// width required to select individual node at current router
localparam node_addr_width = clogb(num_nodes_per_router);
// width of global addresses
localparam addr_width = router_addr_width + node_addr_width;
// number of adjacent routers in each dimension
localparam num_neighbors_per_dim
= ((connectivity == `CONNECTIVITY_LINE) ||
(connectivity == `CONNECTIVITY_RING)) ?
2 :
(connectivity == `CONNECTIVITY_FULL) ?
(num_routers_per_dim - 1) :
-1;
// number of input and output ports on router
localparam num_ports
= num_dimensions * num_neighbors_per_dim + num_nodes_per_router;
// width required to select an individual port
localparam port_idx_width = clogb(num_ports);
// width of flow control signals
localparam flow_ctrl_width
= (flow_ctrl_type == `FLOW_CTRL_TYPE_CREDIT) ? (1 + vc_idx_width) :
-1;
// number of bits required to represent all possible payload sizes
localparam payload_length_width
= clogb(max_payload_length-min_payload_length+1);
// width required for lookahead routing information
localparam lar_info_width = port_idx_width + resource_class_idx_width;
// total number of bits required for storing routing information
localparam dest_info_width
= (routing_type == `ROUTING_TYPE_PHASED_DOR) ?
(num_resource_classes * router_addr_width + node_addr_width) :
-1;
// total number of bits required for routing-related information
localparam route_info_width = lar_info_width + dest_info_width;
// width of link management signals
localparam link_ctrl_width = enable_link_pm ? 1 : 0;
// width of flit control signals
localparam flit_ctrl_width
= (packet_format == `PACKET_FORMAT_HEAD_TAIL) ?
(1 + vc_idx_width + 1 + 1) :
(packet_format == `PACKET_FORMAT_TAIL_ONLY) ?
(1 + vc_idx_width + 1) :
(packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ?
(1 + vc_idx_width + 1) :
-1;
// channel width
localparam channel_width
= link_ctrl_width + flit_ctrl_width + flit_data_width;
// total number of bits of header information encoded in header flit payload
localparam header_info_width
= (packet_format == `PACKET_FORMAT_HEAD_TAIL) ?
route_info_width :
(packet_format == `PACKET_FORMAT_TAIL_ONLY) ?
route_info_width :
(packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ?
(route_info_width + payload_length_width) :
-1;
// VC allocation is atomic
localparam atomic_vc_allocation = (elig_mask == `ELIG_MASK_USED);
//---------------------------------------------------------------------------
// interface
//---------------------------------------------------------------------------
input clk;
input reset;
// current router's address
input [0:router_addr_width-1] router_address;
// incoming channel
input [0:channel_width-1] channel_in;
// selected output port
output [0:num_vcs*num_ports-1] route_out_ivc_op;
wire [0:num_vcs*num_ports-1] route_out_ivc_op;
// selected output resource class
output [0:num_vcs*num_resource_classes-1] route_out_ivc_orc;
wire [0:num_vcs*num_resource_classes-1] route_out_ivc_orc;
// flit is present
output [0:num_vcs-1] flit_valid_out_ivc;
wire [0:num_vcs-1] flit_valid_out_ivc;
// flit is last remaining flit
output [0:num_vcs-1] flit_last_out_ivc;
wire [0:num_vcs-1] flit_last_out_ivc;
// flit is head flit
output [0:num_vcs-1] flit_head_out_ivc;
wire [0:num_vcs-1] flit_head_out_ivc;
// flit is tail flit
output [0:num_vcs-1] flit_tail_out_ivc;
wire [0:num_vcs-1] flit_tail_out_ivc;
//
output [0:num_ports-1] route_fast_out_op;
wire [0:num_ports-1] route_fast_out_op;
//
output [0:num_resource_classes-1] route_fast_out_orc;
wire [0:num_resource_classes-1] route_fast_out_orc;
//
output flit_valid_fast_out;
wire flit_valid_fast_out;
//
output flit_head_fast_out;
wire flit_head_fast_out;
//
output flit_tail_fast_out;
wire flit_tail_fast_out;
//
output [0:num_vcs-1] flit_sel_fast_out_ivc;
wire [0:num_vcs-1] flit_sel_fast_out_ivc;
// outgoing flit data
output [0:flit_data_width-1] flit_data_out;
wire [0:flit_data_width-1] flit_data_out;
// indicate which VC is candidate for being sent
input [0:num_vcs-1] flit_sel_in_ivc;
// flit was sent
input flit_sent_in;
//
input flit_sel_fast_in;
//
input flit_sent_fast_in;
// outgoing flow control signals
output [0:flow_ctrl_width-1] flow_ctrl_out;
wire [0:flow_ctrl_width-1] flow_ctrl_out;
// internal error condition detected
output error;
wire error;
//---------------------------------------------------------------------------
// channel input staging
//---------------------------------------------------------------------------
wire fb_full;
wire chi_active;
assign chi_active = ~fb_full;
wire chi_flit_valid;
wire chi_flit_head;
wire [0:num_vcs-1] chi_flit_head_ivc;
wire chi_flit_tail;
wire [0:num_vcs-1] chi_flit_tail_ivc;
wire [0:flit_data_width-1] chi_flit_data;
wire [0:num_vcs-1] chi_flit_sel_ivc;
rtr_channel_input
#(.num_vcs(num_vcs),
.packet_format(packet_format),
.max_payload_length(max_payload_length),
.min_payload_length(min_payload_length),
.route_info_width(route_info_width),
.enable_link_pm(enable_link_pm),
.flit_data_width(flit_data_width),
.reset_type(reset_type))
chi
(.clk(clk),
.reset(reset),
.active(chi_active),
.channel_in(channel_in),
.flit_valid_out(chi_flit_valid),
.flit_head_out(chi_flit_head),
.flit_head_out_ivc(chi_flit_head_ivc),
.flit_tail_out(chi_flit_tail),
.flit_tail_out_ivc(chi_flit_tail_ivc),
.flit_data_out(chi_flit_data),
.flit_sel_out_ivc(chi_flit_sel_ivc));
wire [0:header_info_width-1] chi_header_info;
assign chi_header_info = chi_flit_data[0:header_info_width-1];
wire [0:route_info_width-1] chi_route_info;
assign chi_route_info = chi_header_info[0:route_info_width-1];
wire [0:lar_info_width-1] chi_lar_info;
assign chi_lar_info = chi_route_info[0:lar_info_width-1];
wire [0:dest_info_width-1] chi_dest_info;
assign chi_dest_info = chi_route_info[lar_info_width:
lar_info_width+dest_info_width-1];
//---------------------------------------------------------------------------
// global lookahead routing information decoder
//---------------------------------------------------------------------------
wire [0:num_ports-1] gld_route_op;
wire [0:num_resource_classes-1] gld_route_orc;
generate
if(1) begin:gld
wire [0:port_idx_width-1] route_port;
assign route_port = chi_lar_info[0:port_idx_width-1];
wire [0:num_ports-1] route_op;
c_decode
#(.num_ports(num_ports))
route_op_dec
(.data_in(route_port),
.data_out(route_op));
wire [0:num_resource_classes-1] route_orc;
if(num_resource_classes == 1)
assign route_orc = 1'b1;
else if(num_resource_classes > 1)
begin
wire [0:resource_class_idx_width-1] route_rcsel;
assign route_rcsel
= chi_lar_info[port_idx_width:
port_idx_width+resource_class_idx_width-1];
c_decode
#(.num_ports(num_resource_classes))
route_orc_dec
(.data_in(route_rcsel),
.data_out(route_orc));
end
assign gld_route_op = route_op;
assign gld_route_orc = route_orc;
end
endgenerate
//---------------------------------------------------------------------------
// global lookahead routing information update logic
//---------------------------------------------------------------------------
wire [0:lar_info_width-1] glu_lar_info;
generate
if(1) begin:glu
wire [0:router_addr_width-1] next_router_address;
rtr_next_hop_addr
#(.num_resource_classes(num_resource_classes),
.num_routers_per_dim(num_routers_per_dim),
.num_dimensions(num_dimensions),
.num_nodes_per_router(num_nodes_per_router),
.connectivity(connectivity),
.routing_type(routing_type))
nha
(.router_address(router_address),
.dest_info(chi_dest_info),
.lar_info(chi_lar_info),
.next_router_address(next_router_address));
wire [0:num_message_classes-1] sel_mc;
c_reduce_bits
#(.num_ports(num_message_classes),
.width(num_resource_classes*num_vcs_per_class),
.op(`BINARY_OP_OR))
sel_mc_rb
(.data_in(chi_flit_sel_ivc),
.data_out(sel_mc));
wire [0:num_ports-1] route_op;
wire [0:num_resource_classes-1] route_orc;
rtr_routing_logic
#(.num_message_classes(num_message_classes),
.num_resource_classes(num_resource_classes),
.num_routers_per_dim(num_routers_per_dim),
.num_dimensions(num_dimensions),
.num_nodes_per_router(num_nodes_per_router),
.connectivity(connectivity),
.routing_type(routing_type),
.dim_order(dim_order))
rtl
(.router_address(next_router_address),
.sel_mc(sel_mc),
.sel_irc(gld_route_orc),
.dest_info(chi_dest_info),
.route_op(route_op),
.route_orc(route_orc));
wire [0:port_idx_width-1] route_port;
c_encode
#(.num_ports(num_ports))
route_port_enc
(.data_in(route_op),
.data_out(route_port));
wire [0:lar_info_width-1] lar_info;
assign lar_info[0:port_idx_width-1] = route_port;
if(num_resource_classes > 1)
begin
wire [0:resource_class_idx_width-1] route_rcsel;
c_encode
#(.num_ports(num_resource_classes))
route_rcsel_enc
(.data_in(route_orc),
.data_out(route_rcsel));
assign lar_info[port_idx_width:
port_idx_width+resource_class_idx_width-1]
= route_rcsel;
end
assign glu_lar_info = lar_info;
end
endgenerate
//---------------------------------------------------------------------------
// input vc controllers
//---------------------------------------------------------------------------
wire [0:num_vcs-1] fb_pop_tail_ivc;
wire [0:header_info_width-1] fb_pop_next_header_info;
wire [0:num_vcs-1] fb_almost_empty_ivc;
wire [0:num_vcs-1] fb_empty_ivc;
wire [0:num_vcs*lar_info_width-1] llu_lar_info_ivc;
wire [0:num_vcs*3-1] ivcc_errors_ivc;
genvar ivc;
generate
for(ivc = 0; ivc < num_vcs; ivc = ivc + 1)
begin:ivcs
//-------------------------------------------------------------------
// connect inputs
//-------------------------------------------------------------------
wire chi_flit_sel;
assign chi_flit_sel = chi_flit_sel_ivc[ivc];
wire chi_flit_head;
assign chi_flit_head = chi_flit_head_ivc[ivc];
wire chi_flit_tail;
assign chi_flit_tail = chi_flit_tail_ivc[ivc];
wire flit_sel_in;
assign flit_sel_in = flit_sel_in_ivc[ivc];
wire fb_almost_empty;
assign fb_almost_empty = fb_almost_empty_ivc[ivc];
wire fb_pop_tail;
assign fb_pop_tail = fb_pop_tail_ivc[ivc];
wire fb_empty;
assign fb_empty = fb_empty_ivc[ivc];
//-------------------------------------------------------------------
// connect outputs
//-------------------------------------------------------------------
wire flit_valid_out;
assign flit_valid_out_ivc[ivc] = flit_valid_out;
wire flit_last_out;
assign flit_last_out_ivc[ivc] = flit_last_out;
wire flit_head_out;
assign flit_head_out_ivc[ivc] = flit_head_out;
wire flit_tail_out;
assign flit_tail_out_ivc[ivc] = flit_tail_out;
wire [0:lar_info_width-1] llu_lar_info;
assign llu_lar_info_ivc[ivc*lar_info_width:(ivc+1)*lar_info_width-1]
= llu_lar_info;
wire [0:num_ports-1] route_out_op;
assign route_out_ivc_op[ivc*num_ports:(ivc+1)*num_ports-1]
= route_out_op;
wire [0:num_resource_classes-1] route_out_orc;
assign route_out_ivc_orc[ivc*num_resource_classes:
(ivc+1)*num_resource_classes-1]
= route_out_orc;
wire [0:2] ivcc_errors;
assign ivcc_errors_ivc[ivc*3:(ivc+1)*3-1] = ivcc_errors;
//-------------------------------------------------------------------
// flit buffer state
//-------------------------------------------------------------------
wire chi_flit_valid_sel;
assign chi_flit_valid_sel = chi_flit_valid & chi_flit_sel;
wire chi_flit_valid_sel_head;
assign chi_flit_valid_sel_head = chi_flit_valid_sel & chi_flit_head;
if(dual_path_alloc)
begin
assign flit_valid_out = ~fb_empty;
assign flit_last_out = fb_almost_empty;
end
else
begin
assign flit_valid_out = chi_flit_valid_sel | ~fb_empty;
assign flit_last_out
= chi_flit_valid_sel ? fb_empty : fb_almost_empty;
end
//-------------------------------------------------------------------
// track whether frontmost flit is head or tail
//-------------------------------------------------------------------
wire flit_sent_sel_in;
assign flit_sent_sel_in = flit_sent_in & flit_sel_in;
wire flit_sent_sel_fast_in;
assign flit_sent_sel_fast_in = flit_sent_fast_in & chi_flit_sel;
wire ht_flit_head;
if(1) begin:ht
wire pop_active;
assign pop_active = chi_flit_valid | ~fb_empty;
wire flit_head_s, flit_head_q;
if(dual_path_alloc)
assign flit_head_s
= flit_sent_sel_in ? flit_tail_out :
flit_sent_sel_fast_in ? flit_tail_fast_out :
flit_head_q;
else
assign flit_head_s
= flit_sent_sel_in ? flit_tail_out : flit_head_q;
c_dff
#(.width(1),
.reset_type(reset_type),
.reset_value(1'b1))
flit_headq
(.clk(clk),
.reset(reset),
.active(pop_active),
.d(flit_head_s),
.q(flit_head_q));
assign ht_flit_head = flit_head_q;
end
if(dual_path_alloc)
begin
assign flit_head_out = ht_flit_head;
assign flit_tail_out = fb_pop_tail;
end
else
begin
assign flit_head_out = fb_empty ? chi_flit_head : ht_flit_head;
assign flit_tail_out = fb_empty ? chi_flit_tail : fb_pop_tail;
end
//-------------------------------------------------------------------
// track header information for frontmost packet
//-------------------------------------------------------------------
wire [0:num_ports-1] hit_route_op;
wire [0:num_resource_classes-1] hit_route_orc;
wire [0:lar_info_width-1] hit_lar_info;
wire [0:dest_info_width-1] hit_dest_info;
if(1) begin:hit
wire active;
wire capture;
if(atomic_vc_allocation)
begin
assign active = chi_flit_valid & chi_flit_head;
assign capture = chi_flit_valid_sel_head;
end
else
begin
assign active = ~fb_empty | (chi_flit_valid & chi_flit_head);
assign capture = (fb_empty & chi_flit_valid_sel_head) |
(flit_sent_sel_in & flit_tail_out);
end
wire two_plus_flits;
assign two_plus_flits = ~fb_empty & ~fb_almost_empty;
wire [0:route_info_width-1] fb_pop_next_route_info;
assign fb_pop_next_route_info
= fb_pop_next_header_info[0:route_info_width-1];
wire [0:lar_info_width-1] fb_pop_next_lar_info;
assign fb_pop_next_lar_info
= fb_pop_next_route_info[0:lar_info_width-1];
wire [0:num_ports-1] route_op;
wire [0:num_resource_classes-1] route_orc;
wire [0:lar_info_width-1] lar_info;
if(dual_path_alloc && predecode_lar_info)
begin
// NOTE: For dual-path routing, we never have to bypass the
// selected output port from the channel input (which would
// have to go through a decoder first); thus, it makes sense
// to store the port in one-hot form here in order to improve
// timing.
wire [0:num_ports-1] route_op_s, route_op_q;
if(atomic_vc_allocation)
assign route_op_s = capture ? gld_route_op : route_op_q;
else
begin
wire [0:port_idx_width-1] fb_pop_next_route_port;
assign fb_pop_next_route_port
= fb_pop_next_lar_info[0:port_idx_width-1];
wire [0:num_ports-1] pop_next_route_op;
c_decode
#(.num_ports(num_ports))
pop_next_route_op_dec
(.data_in(fb_pop_next_route_port),
.data_out(pop_next_route_op));
assign route_op_s = capture ?
(two_plus_flits ?
pop_next_route_op :
gld_route_op) :
route_op_q;
end
c_dff
#(.width(num_ports),
.reset_type(reset_type))
route_opq
(.clk(clk),
.reset(1'b0),
.active(active),
.d(route_op_s),
.q(route_op_q));
assign route_op = route_op_q;
wire [0:port_idx_width-1] route_port;
c_encode
#(.num_ports(num_ports))
route_port_enc
(.data_in(route_op_q),
.data_out(route_port));
assign lar_info[0:port_idx_width-1] = route_port;
if(num_resource_classes == 1)
assign route_orc = 1'b1;
else if(num_resource_classes > 1)
begin
wire [0:num_resource_classes-1] route_orc_s;
wire [0:num_resource_classes-1] route_orc_q;
if(atomic_vc_allocation)
assign route_orc_s
= capture ? gld_route_orc : route_orc_q;
else
begin
wire [0:resource_class_idx_width-1]
fb_pop_next_route_rcsel;
assign fb_pop_next_route_rcsel
= fb_pop_next_lar_info[port_idx_width:
port_idx_width+
resource_class_idx_width-
1];
wire [0:num_resource_classes-1] pop_next_route_orc;
c_decode
#(.num_ports(num_resource_classes))
pop_next_route_orc_dec
(.data_in(fb_pop_next_route_rcsel),
.data_out(pop_next_route_orc));
assign route_orc_s = capture ?
(two_plus_flits ?
pop_next_route_orc :
gld_route_orc) :
route_orc_q;
end
c_dff
#(.width(num_resource_classes),
.reset_type(reset_type))
route_orcq
(.clk(clk),
.reset(1'b0),
.active(active),
.d(route_orc_s),
.q(route_orc_q));
assign route_orc = route_orc_q;
wire [0:resource_class_idx_width-1] route_rcsel;
c_encode
#(.num_ports(num_resource_classes))
route_rcsel_enc
(.data_in(route_orc_q),
.data_out(route_rcsel));
assign lar_info[port_idx_width:
port_idx_width+
resource_class_idx_width-1]
= route_rcsel;
end
end
else
begin
wire [0:lar_info_width-1] lar_info_s, lar_info_q;
if(atomic_vc_allocation)
assign lar_info_s = capture ? chi_lar_info : lar_info_q;
else
assign lar_info_s = capture ?
(two_plus_flits ?
fb_pop_next_lar_info :
chi_lar_info) :
lar_info_q;
c_dff
#(.width(lar_info_width),
.reset_type(reset_type))
lar_infoq
(.clk(clk),
.reset(1'b0),
.active(active),
.d(lar_info_s),
.q(lar_info_q));
assign lar_info = lar_info_q;
wire [0:port_idx_width-1] route_port;
assign route_port = lar_info_q[0:port_idx_width-1];
c_decode
#(.num_ports(num_ports))
route_op_dec
(.data_in(route_port),
.data_out(route_op));
if(num_resource_classes == 1)
assign route_orc = 1'b1;
else if(num_resource_classes > 1)
begin
wire [0:resource_class_idx_width-1] route_rcsel;
assign route_rcsel
= lar_info_q[port_idx_width:
port_idx_width+
resource_class_idx_width-1];
c_decode
#(.num_ports(num_resource_classes))
route_orc_dec
(.data_in(route_rcsel),
.data_out(route_orc));
end
end
wire [0:dest_info_width-1] dest_info_s, dest_info_q;
if(atomic_vc_allocation)
assign dest_info_s = capture ? chi_dest_info : dest_info_q;
else
begin
wire [0:dest_info_width-1] fb_pop_next_dest_info;
assign fb_pop_next_dest_info
= fb_pop_next_route_info[lar_info_width:
lar_info_width+dest_info_width-1];
assign dest_info_s = capture ?
(two_plus_flits ?
fb_pop_next_dest_info :
chi_dest_info) :
dest_info_q;
end
c_dff
#(.width(dest_info_width),
.reset_type(reset_type))
dest_infoq
(.clk(clk),
.reset(1'b0),
.active(active),
.d(dest_info_s),
.q(dest_info_q));
assign hit_route_op = route_op;
assign hit_route_orc = route_orc;
assign hit_lar_info = lar_info;
assign hit_dest_info = dest_info_q;
end
//-------------------------------------------------------------------
// generate routing control signals
//-------------------------------------------------------------------
wire [0:num_ports-1] route_unmasked_op;
wire [0:num_resource_classes-1] route_unmasked_orc;
if(dual_path_alloc)
begin
assign route_unmasked_op = hit_route_op;
assign route_unmasked_orc = hit_route_orc;
end
else
begin
wire bypass_route_info;
if(atomic_vc_allocation)
assign bypass_route_info = chi_flit_valid_sel_head;
else
assign bypass_route_info = fb_empty & chi_flit_valid_sel_head;
assign route_unmasked_op
= bypass_route_info ? gld_route_op : hit_route_op;
assign route_unmasked_orc
= bypass_route_info ? gld_route_orc : hit_route_orc;
end
wire [0:1] rf_errors;
rtr_route_filter
#(.num_message_classes(num_message_classes),
.num_resource_classes(num_resource_classes),
.num_vcs_per_class(num_vcs_per_class),
.num_ports(num_ports),
.num_neighbors_per_dim(num_neighbors_per_dim),
.num_nodes_per_router(num_nodes_per_router),
.restrict_turns(restrict_turns),
.connectivity(connectivity),
.routing_type(routing_type),
.dim_order(dim_order),
.port_id(port_id),
.vc_id(ivc))
rf
(.clk(clk),
.route_valid(flit_valid_out),
.route_in_op(route_unmasked_op),
.route_in_orc(route_unmasked_orc),
.route_out_op(route_out_op),
.route_out_orc(route_out_orc),
.errors(rf_errors));
wire error_invalid_port;
assign error_invalid_port = rf_errors[0];
wire error_invalid_class;
assign error_invalid_class = rf_errors[1];
//-------------------------------------------------------------------
// local lookahead routing information update logic
//-------------------------------------------------------------------
if(1) begin:llu
wire [0:router_addr_width-1] next_router_address;
rtr_next_hop_addr
#(.num_resource_classes(num_resource_classes),
.num_routers_per_dim(num_routers_per_dim),
.num_dimensions(num_dimensions),
.num_nodes_per_router(num_nodes_per_router),
.connectivity(connectivity),
.routing_type(routing_type))
nha
(.router_address(router_address),
.dest_info(hit_dest_info),
.lar_info(hit_lar_info),
.next_router_address(next_router_address));
wire [0:num_message_classes-1] sel_mc;
c_align
#(.in_width(1),
.out_width(num_message_classes),
.offset((ivc / (num_resource_classes*num_vcs_per_class)) %
num_message_classes))
sel_mc_agn
(.data_in(1'b1),
.dest_in({num_message_classes{1'b0}}),
.data_out(sel_mc));
wire [0:num_ports-1] route_op;
wire [0:num_resource_classes-1] route_orc;
rtr_routing_logic
#(.num_message_classes(num_message_classes),
.num_resource_classes(num_resource_classes),
.num_routers_per_dim(num_routers_per_dim),
.num_dimensions(num_dimensions),
.num_nodes_per_router(num_nodes_per_router),
.connectivity(connectivity),
.routing_type(routing_type),
.dim_order(dim_order))
rtl
(.router_address(next_router_address),
.sel_mc(sel_mc),
.sel_irc(hit_route_orc),
.dest_info(hit_dest_info),
.route_op(route_op),
.route_orc(route_orc));
wire [0:port_idx_width-1] route_port;
c_encode
#(.num_ports(num_ports))
route_port_enc
(.data_in(route_op),
.data_out(route_port));
wire [0:lar_info_width-1] lar_info;
assign lar_info[0:port_idx_width-1] = route_port;
if(num_resource_classes > 1)
begin
wire [0:resource_class_idx_width-1] route_rcsel;
c_encode
#(.num_ports(num_resource_classes))
route_rcsel_enc
(.data_in(route_orc),
.data_out(route_rcsel));
assign lar_info[port_idx_width:
port_idx_width+resource_class_idx_width-1]
= route_rcsel;
end
assign llu_lar_info = lar_info;
end
//-------------------------------------------------------------------
// error checking
//-------------------------------------------------------------------
wire ftc_active;
assign ftc_active = chi_flit_valid;
wire error_invalid_flit_type;
rtr_flit_type_check
#(.reset_type(reset_type))
ftc
(.clk(clk),
.reset(reset),
.active(ftc_active),
.flit_valid(chi_flit_valid_sel),
.flit_head(chi_flit_head),
.flit_tail(chi_flit_tail),
.error(error_invalid_flit_type));
assign ivcc_errors[0] = error_invalid_port;
assign ivcc_errors[1] = error_invalid_class;
assign ivcc_errors[2] = error_invalid_flit_type;
end
endgenerate
//---------------------------------------------------------------------------
// flit buffer
//---------------------------------------------------------------------------
wire fb_all_empty;
assign fb_all_empty = &fb_empty_ivc;
wire alloc_active;
assign alloc_active = chi_flit_valid | ~fb_all_empty;
wire fb_push_active;
assign fb_push_active = chi_flit_valid;
wire fb_push_valid;
assign fb_push_valid = chi_flit_valid;
wire fb_push_head;
assign fb_push_head = chi_flit_head;
wire fb_push_tail;
assign fb_push_tail = chi_flit_tail;
wire [0:num_vcs-1] fb_push_sel_ivc;
assign fb_push_sel_ivc = chi_flit_sel_ivc;
wire [0:flit_data_width-1] fb_push_data;
assign fb_push_data = chi_flit_data;
wire fb_pop_active;
assign fb_pop_active = alloc_active;
wire fb_pop_valid;
wire [0:num_vcs-1] fb_pop_sel_ivc;
generate
if(dual_path_alloc)
begin
assign fb_pop_valid = flit_sent_in | flit_sent_fast_in;
assign fb_pop_sel_ivc
= flit_sel_fast_in ? chi_flit_sel_ivc : flit_sel_in_ivc;
end
else
begin
assign fb_pop_valid = flit_sent_in;
assign fb_pop_sel_ivc = flit_sel_in_ivc;
end
endgenerate
wire [0:flit_data_width-1] fb_pop_data;
wire [0:num_vcs*2-1] fb_errors_ivc;
rtr_flit_buffer
#(.num_vcs(num_vcs),
.buffer_size(buffer_size),
.flit_data_width(flit_data_width),
.header_info_width(header_info_width),
.regfile_type(fb_regfile_type),
.explicit_pipeline_register(explicit_pipeline_register),
.gate_buffer_write(gate_buffer_write),
.mgmt_type(fb_mgmt_type),
.fast_peek(fb_fast_peek),
.atomic_vc_allocation(atomic_vc_allocation),
.enable_bypass(1),
.reset_type(reset_type))
fb
(.clk(clk),
.reset(reset),
.push_active(fb_push_active),
.push_valid(fb_push_valid),
.push_head(fb_push_head),
.push_tail(fb_push_tail),
.push_sel_ivc(fb_push_sel_ivc),
.push_data(fb_push_data),
.pop_active(fb_pop_active),
.pop_valid(fb_pop_valid),
.pop_sel_ivc(fb_pop_sel_ivc),
.pop_data(fb_pop_data),
.pop_tail_ivc(fb_pop_tail_ivc),
.pop_next_header_info(fb_pop_next_header_info),
.almost_empty_ivc(fb_almost_empty_ivc),
.empty_ivc(fb_empty_ivc),
.full(fb_full),
.errors_ivc(fb_errors_ivc));
//---------------------------------------------------------------------------
// generate fast-path control signals
//---------------------------------------------------------------------------
generate
if(dual_path_alloc)
begin:fpc
assign route_fast_out_op = gld_route_op;
assign route_fast_out_orc = gld_route_orc;
assign flit_valid_fast_out = chi_flit_valid;
assign flit_head_fast_out = chi_flit_head;
assign flit_tail_fast_out = chi_flit_tail;
assign flit_sel_fast_out_ivc = chi_flit_sel_ivc;
end
else
begin
assign route_fast_out_op = {num_ports{1'b0}};
assign route_fast_out_orc = {num_resource_classes{1'b0}};
assign flit_valid_fast_out = 1'b0;
assign flit_head_fast_out = 1'b0;
assign flit_tail_fast_out = 1'b0;
assign flit_sel_fast_out_ivc = {num_vcs{1'b0}};
end
endgenerate
//---------------------------------------------------------------------------
// flit buffer read path
//---------------------------------------------------------------------------
wire flit_head_out;
c_select_1ofn
#(.num_ports(num_vcs),
.width(1))
flit_head_out_sel
(.select(flit_sel_in_ivc),
.data_in(flit_head_out_ivc),
.data_out(flit_head_out));
wire [0:num_vcs-1] flit_sel_ivc;
wire flit_sent;
wire flit_head;
wire bypass;
generate
if(dual_path_alloc)
begin
assign flit_sel_ivc
= flit_sel_fast_in ? chi_flit_sel_ivc : flit_sel_in_ivc;
assign flit_sent = flit_sent_in | flit_sent_fast_in;
assign flit_head = flit_sel_fast_in ? chi_flit_head : flit_head_out;
assign bypass = flit_sel_fast_in;
end
else
begin
assign flit_sel_ivc = flit_sel_in_ivc;
assign flit_sent = flit_sent_in;
assign flit_head = flit_head_out;
c_select_1ofn
#(.num_ports(num_vcs),
.width(1))
bypass_sel
(.select(flit_sel_in_ivc),
.data_in(fb_empty_ivc),
.data_out(bypass));
end
endgenerate
wire [0:lar_info_width-1] llu_lar_info;
c_select_1ofn
#(.num_ports(num_vcs),
.width(lar_info_width))
llu_lar_info_sel
(.select(flit_sel_in_ivc),
.data_in(llu_lar_info_ivc),
.data_out(llu_lar_info));
wire flit_head_s, flit_head_q;
assign flit_head_s = flit_head;
c_dff
#(.width(1),
.reset_type(reset_type))
flit_headq
(.clk(clk),
.reset(1'b0),
.active(alloc_active),
.d(flit_head_s),
.q(flit_head_q));
wire [0:lar_info_width-1] lar_info_s, lar_info_q;
assign lar_info_s
= flit_head ? (bypass ? glu_lar_info : llu_lar_info) : lar_info_q;
c_dff
#(.width(lar_info_width),
.reset_type(reset_type))
lar_infoq
(.clk(clk),
.reset(1'b0),
.active(alloc_active),
.d(lar_info_s),
.q(lar_info_q));
assign flit_data_out[0:lar_info_width-1]
= flit_head_q ? lar_info_q : fb_pop_data[0:lar_info_width-1];
assign flit_data_out[lar_info_width:flit_data_width-1]
= fb_pop_data[lar_info_width:flit_data_width-1];
//---------------------------------------------------------------------------
// generate outgoing flow control signals
//---------------------------------------------------------------------------
rtr_flow_ctrl_output
#(.num_vcs(num_vcs),
.flow_ctrl_type(flow_ctrl_type),
.reset_type(reset_type))
fco
(.clk(clk),
.reset(reset),
.active(alloc_active),
.fc_event_valid_in(flit_sent),
.fc_event_sel_in_ivc(flit_sel_ivc),
.flow_ctrl_out(flow_ctrl_out));
//---------------------------------------------------------------------------
// error checking
//---------------------------------------------------------------------------
generate
if(error_capture_mode != `ERROR_CAPTURE_MODE_NONE)
begin
wire [0:num_vcs*3+num_vcs*2-1] errors_s, errors_q;
assign errors_s = {ivcc_errors_ivc, fb_errors_ivc};
c_err_rpt
#(.num_errors(num_vcs*3+num_vcs*2),
.capture_mode(error_capture_mode),
.reset_type(reset_type))
chk
(.clk(clk),
.reset(reset),
.active(1'b1),
.errors_in(errors_s),
.errors_out(errors_q));
assign error = |errors_q;
end
else
assign error = 1'bx;
endgenerate
endmodule
|
//==================================================================================================
// Filename : Testbench_FPUv1_Interface.v
// Created On : 2016-10-31 01:04:16
// Last Modified : 2016-10-31 01:04:28
// Revision :
// Author : Jorge Esteban Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email : [email protected]
//
// Description :
//
//
//==================================================================================================
`timescale 1ns / 1ps
module Testbench_FPU_Mark1();
parameter PERIOD = 10;
`ifdef SINGLE
parameter W = 32;
parameter EW = 8;
parameter SW = 23;
parameter SWR = 26;
parameter EWR = 5;//
`endif
`ifdef DOUBLE
parameter W = 64;
parameter EW = 11;
parameter SW = 52;
parameter SWR = 55;
parameter EWR = 6;
`endif
reg clk;
//INPUT signals
reg rst;
reg begin_operation;
reg ack_operation;
reg [2:0] operation;
//Oper_Start_in signals
reg [W-1:0] Data_1;
reg [W-1:0] Data_2;
reg [1:0] region_flag;
//reg add_subt;
//Round signals signals
reg [1:0] r_mode;
//OUTPUT SIGNALS
wire overflow_flag;
wire underflow_flag;
wire operation_ready;
wire NaN_flag;
wire [W-1:0] op_result;
// LOS CODIGOS PARA LAS OPERACIONES
localparam [2:0] FPADD = 3'b000,
FPSUB = 3'b001,
FPCOS = 3'b010,
FPSEN = 3'b011,
FPMULT = 3'b100;
// LAS REGIONES DEL ANGULO
localparam [1:0] IoIV1 = 2'b00,
II = 2'b01,
III = 2'b10,
IoIV2 = 2'b11;
localparam [1:0] ROUNDING_MODE_TRUNCT = 2'b00,
ROUNDING_MODE_NEG_INF = 2'b01,
ROUNDING_MODE_POS_INF = 2'b10;
`ifdef SINGLE
FPU_Interface_W32_EW8_SW23_SWR26_EWR5 FPU_Interface (
.clk (clk),
.rst (rst),
.begin_operation (begin_operation),
.ack_operation (ack_operation),
.operation (operation),
.region_flag (region_flag),
.Data_1 (Data_1),
.Data_2 (Data_2),
.r_mode (r_mode),
.overflow_flag (overflow_flag),
.underflow_flag (underflow_flag),
.NaN_flag (NaN_flag),
.operation_ready (operation_ready),
.op_result (op_result)
);
`endif
`ifdef DOUBLE
FPU_Interface_W64_EW11_SW52_SWR55_EWR6 FPU_Interface (
.clk (clk),
.rst (rst),
.begin_operation (begin_operation),
.ack_operation (ack_operation),
.operation (operation),
.region_flag (region_flag),
.Data_1 (Data_1),
.Data_2 (Data_2),
.r_mode (r_mode),
.overflow_flag (overflow_flag),
.underflow_flag (underflow_flag),
.NaN_flag (NaN_flag),
.operation_ready (operation_ready),
.op_result (op_result)
);
`endif
reg [W-1:0] Array_IN_1 [0:((2**PERIOD)-1)];
reg [W-1:0] Array_IN_2 [0:((2**PERIOD)-1)];
integer contador;
integer FileSaveData;
initial begin
// Initialize Inputs
clk = 0;
rst = 1;
begin_operation = 0;
ack_operation = 0;
Data_1 = 0;
Data_2 = 0;
`ifdef SINGLE
$display("------------------------SUMA--------------------------");
$display("------------------------ --------------------------");
$display("------------------------SUMA--------------------------");
operation = FPADD;
r_mode = ROUNDING_MODE_TRUNCT;
FileSaveData = $fopen("ADD/SINGLE/RMODE_TRUNCATE/ResultadoXilinxFLM.txt","w");
$readmemh("ADD/SINGLE/Hexadecimal_A.txt", Array_IN_1);
$readmemh("ADD/SINGLE/Hexadecimal_B.txt", Array_IN_2);
run_Arch2(FileSaveData,2**PERIOD);
r_mode = ROUNDING_MODE_NEG_INF;
FileSaveData = $fopen("ADD/SINGLE/RMODE_NEGINF/ResultadoXilinxFLM.txt","w");
$readmemh("ADD/SINGLE/Hexadecimal_A.txt", Array_IN_1);
$readmemh("ADD/SINGLE/Hexadecimal_B.txt", Array_IN_2);
run_Arch2(FileSaveData,2**PERIOD);
r_mode = ROUNDING_MODE_POS_INF;
FileSaveData = $fopen("ADD/SINGLE/RMODE_POSINF/ResultadoXilinxFLM.txt","w");
$readmemh("ADD/SINGLE/Hexadecimal_A.txt", Array_IN_1);
$readmemh("ADD/SINGLE/Hexadecimal_B.txt", Array_IN_2);
run_Arch2(FileSaveData,2**PERIOD);
$display("------------------------RSTA--------------------------");
$display("------------------------ --------------------------");
$display("------------------------RSTA--------------------------");
operation = FPSUB;
r_mode = ROUNDING_MODE_TRUNCT;
FileSaveData = $fopen("SUB/SINGLE/RMODE_TRUNCATE/ResultadoXilinxFLM.txt","w");
$readmemh("SUB/SINGLE/Hexadecimal_A.txt", Array_IN_1);
$readmemh("SUB/SINGLE/Hexadecimal_B.txt", Array_IN_2);
run_Arch2(FileSaveData,2**PERIOD);
r_mode = ROUNDING_MODE_NEG_INF;
FileSaveData = $fopen("SUB/SINGLE/RMODE_NEGINF/ResultadoXilinxFLM.txt","w");
$readmemh("SUB/SINGLE/Hexadecimal_A.txt", Array_IN_1);
$readmemh("SUB/SINGLE/Hexadecimal_B.txt", Array_IN_2);
run_Arch2(FileSaveData,2**PERIOD);
r_mode = ROUNDING_MODE_POS_INF;
FileSaveData = $fopen("SUB/SINGLE/RMODE_POSINF/ResultadoXilinxFLM.txt","w");
$readmemh("SUB/SINGLE/Hexadecimal_A.txt", Array_IN_1);
$readmemh("SUB/SINGLE/Hexadecimal_B.txt", Array_IN_2);
run_Arch2(FileSaveData,2**PERIOD);
$display("------------------------MULT--------------------------");
$display("------------------------ --------------------------");
$display("------------------------MULT--------------------------");
operation = FPMULT;
r_mode = ROUNDING_MODE_TRUNCT;
FileSaveData = $fopen("MULT/SINGLE/RMODE_TRUNCATE/ResultadoXilinxFLM.txt","w");
$readmemh("MULT/SINGLE/Hexadecimal_A.txt", Array_IN_1);
$readmemh("MULT/SINGLE/Hexadecimal_B.txt", Array_IN_2);
run_Arch2(FileSaveData,2**PERIOD);
r_mode = ROUNDING_MODE_NEG_INF;
FileSaveData = $fopen("MULT/SINGLE/RMODE_NEGINF/ResultadoXilinxFLM.txt","w");
$readmemh("MULT/SINGLE/Hexadecimal_A.txt", Array_IN_1);
$readmemh("MULT/SINGLE/Hexadecimal_B.txt", Array_IN_2);
run_Arch2(FileSaveData,2**PERIOD);
r_mode = ROUNDING_MODE_POS_INF;
FileSaveData = $fopen("MULT/SINGLE/RMODE_POSINF/ResultadoXilinxFLM.txt","w");
$readmemh("MULT/SINGLE/Hexadecimal_A.txt", Array_IN_1);
$readmemh("MULT/SINGLE/Hexadecimal_B.txt", Array_IN_2);
run_Arch2(FileSaveData,2**PERIOD);
$display("---------------------REGION I or IV--------------------------");
$display("------------------------ --------------------------");
$display("---------------------REGION I or IV-------------------");
region_flag = IoIV1;
$display("------------------------SENO--------------------------");
$display("------------------------ --------------------------");
$display("------------------------SENO--------------------------");
operation = FPSEN;
r_mode = ROUNDING_MODE_TRUNCT;
FileSaveData = $fopen("SIN/SINGLE/RMODE_TRUNCATE/ResultadoXilinxFLM.txt","w");
$readmemh("SIN/SINGLE/input_angles_hex.txt", Array_IN_1);
run_Arch2(FileSaveData,2**PERIOD);
r_mode = ROUNDING_MODE_NEG_INF;
FileSaveData = $fopen("SIN/SINGLE/RMODE_NEGINF/ResultadoXilinxFLM.txt","w");
$readmemh("SIN/SINGLE/input_angles_hex.txt", Array_IN_1);
run_Arch2(FileSaveData,2**PERIOD);
r_mode = ROUNDING_MODE_POS_INF;
FileSaveData = $fopen("SIN/SINGLE/RMODE_POSINF/ResultadoXilinxFLM.txt","w");
$readmemh("SIN/SINGLE/input_angles_hex.txt", Array_IN_1);
run_Arch2(FileSaveData,2**PERIOD);
$display("------------------------COS--------------------------");
$display("------------------------ --------------------------");
$display("------------------------COS--------------------------");
operation = FPCOS;
r_mode = ROUNDING_MODE_TRUNCT;
FileSaveData = $fopen("COS/SINGLE/RMODE_TRUNCATE/ResultadoXilinxFLM.txt","w");
$readmemh("COS/SINGLE/input_angles_hex.txt", Array_IN_1);
run_Arch2(FileSaveData,2**PERIOD);
r_mode = ROUNDING_MODE_NEG_INF;
FileSaveData = $fopen("COS/SINGLE/RMODE_NEGINF/ResultadoXilinxFLM.txt","w");
$readmemh("COS/SINGLE/input_angles_hex.txt", Array_IN_1);
run_Arch2(FileSaveData,2**PERIOD);
r_mode = ROUNDING_MODE_POS_INF;
FileSaveData = $fopen("COS/SINGLE/RMODE_POSINF/ResultadoXilinxFLM.txt","w");
$readmemh("COS/SINGLE/input_angles_hex.txt", Array_IN_1);
run_Arch2(FileSaveData,2**PERIOD);
`endif
`ifdef DOUBLE
$display("------------------------SUMA--------------------------");
$display("------------------------ --------------------------");
$display("------------------------SUMA--------------------------");
operation = FPADD;
r_mode = ROUNDING_MODE_TRUNCT;
FileSaveData = $fopen("ADD/DOUBLE/RMODE_TRUNCATE/ResultadoXilinxFLM.txt","w");
$readmemh("ADD/DOUBLE/Hexadecimal_A.txt", Array_IN_1);
$readmemh("ADD/DOUBLE/Hexadecimal_B.txt", Array_IN_2);
run_Arch2(FileSaveData,2**PERIOD);
r_mode = ROUNDING_MODE_NEG_INF;
FileSaveData = $fopen("ADD/DOUBLE/RMODE_NEGINF/ResultadoXilinxFLM.txt","w");
$readmemh("ADD/DOUBLE/Hexadecimal_A.txt", Array_IN_1);
$readmemh("ADD/DOUBLE/Hexadecimal_B.txt", Array_IN_2);
run_Arch2(FileSaveData,2**PERIOD);
r_mode = ROUNDING_MODE_POS_INF;
FileSaveData = $fopen("ADD/DOUBLE/RMODE_POSINF/ResultadoXilinxFLM.txt","w");
$readmemh("ADD/DOUBLE/Hexadecimal_A.txt", Array_IN_1);
$readmemh("ADD/DOUBLE/Hexadecimal_B.txt", Array_IN_2);
run_Arch2(FileSaveData,2**PERIOD);
$display("------------------------RSTA--------------------------");
$display("------------------------ --------------------------");
$display("------------------------RSTA--------------------------");
operation = FPSUB;
r_mode = ROUNDING_MODE_TRUNCT;
FileSaveData = $fopen("SUB/DOUBLE/RMODE_TRUNCATE/ResultadoXilinxFLM.txt","w");
$readmemh("SUB/DOUBLE/Hexadecimal_A.txt", Array_IN_1);
$readmemh("SUB/DOUBLE/Hexadecimal_B.txt", Array_IN_2);
run_Arch2(FileSaveData,2**PERIOD);
r_mode = ROUNDING_MODE_NEG_INF;
FileSaveData = $fopen("SUB/DOUBLE/RMODE_NEGINF/ResultadoXilinxFLM.txt","w");
$readmemh("SUB/DOUBLE/Hexadecimal_A.txt", Array_IN_1);
$readmemh("SUB/DOUBLE/Hexadecimal_B.txt", Array_IN_2);
run_Arch2(FileSaveData,2**PERIOD);
r_mode = ROUNDING_MODE_POS_INF;
FileSaveData = $fopen("SUB/DOUBLE/RMODE_POSINF/ResultadoXilinxFLM.txt","w");
$readmemh("SUB/DOUBLE/Hexadecimal_A.txt", Array_IN_1);
$readmemh("SUB/DOUBLE/Hexadecimal_B.txt", Array_IN_2);
run_Arch2(FileSaveData,2**PERIOD);
$display("------------------------MULT--------------------------");
$display("------------------------ --------------------------");
$display("------------------------MULT--------------------------");
operation = FPMULT;
r_mode = ROUNDING_MODE_TRUNCT;
FileSaveData = $fopen("MULT/DOUBLE/RMODE_TRUNCATE/ResultadoXilinxFLM.txt","w");
$readmemh("MULT/DOUBLE/Hexadecimal_A.txt", Array_IN_1);
$readmemh("MULT/DOUBLE/Hexadecimal_B.txt", Array_IN_2);
run_Arch2(FileSaveData,2**PERIOD);
r_mode = ROUNDING_MODE_NEG_INF;
FileSaveData = $fopen("MULT/DOUBLE/RMODE_NEGINF/ResultadoXilinxFLM.txt","w");
$readmemh("MULT/DOUBLE/Hexadecimal_A.txt", Array_IN_1);
$readmemh("MULT/DOUBLE/Hexadecimal_B.txt", Array_IN_2);
run_Arch2(FileSaveData,2**PERIOD);
r_mode = ROUNDING_MODE_POS_INF;
FileSaveData = $fopen("MULT/DOUBLE/RMODE_POSINF/ResultadoXilinxFLM.txt","w");
$readmemh("MULT/DOUBLE/Hexadecimal_A.txt", Array_IN_1);
$readmemh("MULT/DOUBLE/Hexadecimal_B.txt", Array_IN_2);
run_Arch2(FileSaveData,2**PERIOD);
$display("---------------------REGION I or IV--------------------------");
$display("------------------------ --------------------------");
$display("---------------------REGION I or IV-------------------");
region_flag = IoIV1;
$display("------------------------SENO--------------------------");
$display("------------------------ --------------------------");
$display("------------------------SENO--------------------------");
operation = FPSEN;
r_mode = ROUNDING_MODE_TRUNCT;
FileSaveData = $fopen("SIN/DOUBLE/RMODE_TRUNCATE/ResultadoXilinxFLM.txt","w");
$readmemh("SIN/DOUBLE/input_angles_hex.txt", Array_IN_1);
run_Arch2(FileSaveData,2**PERIOD);
r_mode = ROUNDING_MODE_NEG_INF;
FileSaveData = $fopen("SIN/DOUBLE/RMODE_NEGINF/ResultadoXilinxFLM.txt","w");
$readmemh("SIN/DOUBLE/input_angles_hex.txt", Array_IN_1);
run_Arch2(FileSaveData,2**PERIOD);
r_mode = ROUNDING_MODE_POS_INF;
FileSaveData = $fopen("SIN/DOUBLE/RMODE_POSINF/ResultadoXilinxFLM.txt","w");
$readmemh("SIN/DOUBLE/input_angles_hex.txt", Array_IN_1);
run_Arch2(FileSaveData,2**PERIOD);
$display("------------------------COS--------------------------");
$display("------------------------ --------------------------");
$display("------------------------COS--------------------------");
operation = FPCOS;
r_mode = ROUNDING_MODE_TRUNCT;
FileSaveData = $fopen("COS/DOUBLE/RMODE_TRUNCATE/ResultadoXilinxFLM.txt","w");
$readmemh("COS/DOUBLE/input_angles_hex.txt", Array_IN_1);
run_Arch2(FileSaveData,2**PERIOD);
r_mode = ROUNDING_MODE_NEG_INF;
FileSaveData = $fopen("COS/DOUBLE/RMODE_NEGINF/ResultadoXilinxFLM.txt","w");
$readmemh("COS/DOUBLE/input_angles_hex.txt", Array_IN_1);
run_Arch2(FileSaveData,2**PERIOD);
r_mode = ROUNDING_MODE_POS_INF;
FileSaveData = $fopen("COS/DOUBLE/RMODE_POSINF/ResultadoXilinxFLM.txt","w");
$readmemh("COS/DOUBLE/input_angles_hex.txt", Array_IN_1);
run_Arch2(FileSaveData,2**PERIOD);
`endif
#100 rst = 0;
$finish;
//Add stimulus here
end
//******************************* Se ejecuta el CLK ************************
initial forever #5 clk = ~clk;
task run_Arch2;
input integer FDataO;
input integer Vector_size;
begin
rst = 0;
#15 rst = 1;
#15 rst = 0;
begin_operation = 0;
ack_operation = 0;
contador = 0;
repeat(Vector_size) @(negedge clk) begin
//input the new values inside the operator
Data_1 = Array_IN_1[contador];
Data_2 = Array_IN_2[contador];
#(PERIOD/4) begin_operation = 1;
//Wait for the operation operation_ready
@(posedge operation_ready) begin
#(PERIOD+2);
ack_operation = 1;
#4;
$fwrite(FDataO,"%h\n",op_result);
end
@(negedge clk) begin
ack_operation = 0;
end
contador = contador + 1;
end
$fclose(FDataO);
end
endtask
endmodule
|
module lcd (
input clk,
output reg lcd_rs,
output reg lcd_rw,
output reg lcd_e,
output reg [7:4] lcd_d,
output [4:0] mem_addr,
input [7:0] mem_bus
);
parameter n = 24;
parameter j = 17; // Initialization is slow, runs at clk/2^(j+2) ~95Hz
parameter k = 11; // Writing/seeking is fast, clk/2^(k_2) ~6KHz
parameter noop = 6'b010000; // Allows LCD to drive lcd_d, can be safely written any time
reg [n:0] count = 0;
reg [5:0] lcd_state = noop;
reg init = 1; // Start in initialization on power on
reg row = 0; // Writing to top or or bottom row
assign mem_addr = {row, count[k+6:k+3]};
initial count[j+7:j+2] = 11;
always @ (posedge clk) begin
count <= count + 1;
if (init) begin // initalization
case (count[j+7:j+2])
1: lcd_state <= 6'b000010; // function set
2: lcd_state <= 6'b000010;
3: lcd_state <= 6'b001000;
4: lcd_state <= 6'b000000; // display on/off control
5: lcd_state <= 6'b001100;
6: lcd_state <= 6'b000000; // display clear
7: lcd_state <= 6'b000001;
8: lcd_state <= 6'b000000; // entry mode set
9: lcd_state <= 6'b000110;
10: begin init <= ~init; count <= 0; end
endcase
// Write lcd_state to the LCD and turn lcd_e high for the middle half of each lcd_state
{lcd_e,lcd_rs,lcd_rw,lcd_d[7:4]} <= {^count[j+1:j+0] & ~lcd_rw,lcd_state};
end else begin // Continuously update screen from memory
case (count[k+7:k+2])
32: lcd_state <= {3'b001,~row,2'b00}; // Move cursor to begining of next line
33: lcd_state <= 6'b000000;
34: begin count <= 0; row <= ~row; end // Restart and switch which row is being written
default: lcd_state <= {2'b10, ~count[k+2] ? mem_bus[7:4] : mem_bus[3:0]}; // Pull characters from bus
endcase
// Write lcd_state to the LCD and turn lcd_e high for the middle half of each lcd_state
{lcd_e,lcd_rs,lcd_rw,lcd_d[7:4]} <= {^count[k+1:k+0] & ~lcd_rw,lcd_state};
end
end
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__NAND3_FUNCTIONAL_PP_V
/**
* nand3: 3-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__nand3 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , B, A, C );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND3_FUNCTIONAL_PP_V |
// -----------------------------------------------------------
// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Description: Single clock Avalon-ST FIFO.
// -----------------------------------------------------------
`timescale 1 ns / 1 ns
//altera message_off 10036
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
parameter ERROR_WIDTH = 0,
parameter USE_PACKETS = 0,
parameter USE_FILL_LEVEL = 0,
parameter USE_STORE_FORWARD = 0,
parameter USE_ALMOST_FULL_IF = 0,
parameter USE_ALMOST_EMPTY_IF = 0,
// --------------------------------------------------
// Empty latency is defined as the number of cycles
// required for a write to deassert the empty flag.
// For example, a latency of 1 means that the empty
// flag is deasserted on the cycle after a write.
//
// Another way to think of it is the latency for a
// write to propagate to the output.
//
// An empty latency of 0 implies lookahead, which is
// only implemented for the register-based FIFO.
// --------------------------------------------------
parameter EMPTY_LATENCY = 3,
parameter USE_MEMORY_BLOCKS = 1,
// --------------------------------------------------
// Internal Parameters
// --------------------------------------------------
parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
// --------------------------------------------------
// Ports
// --------------------------------------------------
input clk,
input reset,
input [DATA_WIDTH-1: 0] in_data,
input in_valid,
input in_startofpacket,
input in_endofpacket,
input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty,
input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error,
input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel,
output in_ready,
output [DATA_WIDTH-1 : 0] out_data,
output reg out_valid,
output out_startofpacket,
output out_endofpacket,
output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty,
output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error,
output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
input out_ready,
input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address,
input csr_write,
input csr_read,
input [31 : 0] csr_writedata,
output reg [31 : 0] csr_readdata,
output wire almost_full_data,
output wire almost_empty_data
);
// --------------------------------------------------
// Local Parameters
// --------------------------------------------------
localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
localparam DEPTH = FIFO_DEPTH;
localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
// --------------------------------------------------
// Internal Signals
// --------------------------------------------------
genvar i;
reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
reg [ADDR_WIDTH-1 : 0] wr_ptr;
reg [ADDR_WIDTH-1 : 0] rd_ptr;
reg [DEPTH-1 : 0] mem_used;
wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
wire read;
wire write;
reg empty;
reg next_empty;
reg full;
reg next_full;
wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
wire [PAYLOAD_WIDTH-1 : 0] in_payload;
reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
reg [PAYLOAD_WIDTH-1 : 0] out_payload;
reg internal_out_valid;
wire internal_out_ready;
reg [ADDR_WIDTH : 0] fifo_fill_level;
reg [ADDR_WIDTH : 0] fill_level;
reg [ADDR_WIDTH-1 : 0] sop_ptr = 0;
wire [ADDR_WIDTH-1 : 0] curr_sop_ptr;
reg [23:0] almost_full_threshold;
reg [23:0] almost_empty_threshold;
reg [23:0] cut_through_threshold;
reg [15:0] pkt_cnt;
reg drop_on_error_en;
reg error_in_pkt;
reg pkt_has_started;
reg sop_has_left_fifo;
reg fifo_too_small_r;
reg pkt_cnt_eq_zero;
reg pkt_cnt_eq_one;
wire wait_for_threshold;
reg pkt_mode;
wire wait_for_pkt;
wire ok_to_forward;
wire in_pkt_eop_arrive;
wire out_pkt_leave;
wire in_pkt_start;
wire in_pkt_error;
wire drop_on_error;
wire fifo_too_small;
wire out_pkt_sop_leave;
wire [31:0] max_fifo_size;
reg fifo_fill_level_lt_cut_through_threshold;
// --------------------------------------------------
// Define Payload
//
// Icky part where we decide which signals form the
// payload to the FIFO with generate blocks.
// --------------------------------------------------
generate
if (EMPTY_WIDTH > 0) begin : gen_blk1
assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
end
else begin : gen_blk1_else
assign out_empty = in_error;
assign in_packet_signals = {in_startofpacket, in_endofpacket};
assign {out_startofpacket, out_endofpacket} = out_packet_signals;
end
endgenerate
generate
if (USE_PACKETS) begin : gen_blk2
if (ERROR_WIDTH > 0) begin : gen_blk3
if (CHANNEL_WIDTH > 0) begin : gen_blk4
assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk4_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data, in_error};
assign {out_packet_signals, out_data, out_error} = out_payload;
end
end
else begin : gen_blk3_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk5
assign in_payload = {in_packet_signals, in_data, in_channel};
assign {out_packet_signals, out_data, out_channel} = out_payload;
end
else begin : gen_blk5_else
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data};
assign {out_packet_signals, out_data} = out_payload;
end
end
end
else begin : gen_blk2_else
assign out_packet_signals = 0;
if (ERROR_WIDTH > 0) begin : gen_blk6
if (CHANNEL_WIDTH > 0) begin : gen_blk7
assign in_payload = {in_data, in_error, in_channel};
assign {out_data, out_error, out_channel} = out_payload;
end
else begin : gen_blk7_else
assign out_channel = in_channel;
assign in_payload = {in_data, in_error};
assign {out_data, out_error} = out_payload;
end
end
else begin : gen_blk6_else
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin : gen_blk8
assign in_payload = {in_data, in_channel};
assign {out_data, out_channel} = out_payload;
end
else begin : gen_blk8_else
assign out_channel = in_channel;
assign in_payload = in_data;
assign out_data = out_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Memory-based FIFO storage
//
// To allow a ready latency of 0, the read index is
// obtained from the next read pointer and memory
// outputs are unregistered.
//
// If the empty latency is 1, we infer bypass logic
// around the memory so writes propagate to the
// outputs on the next cycle.
//
// Do not change the way this is coded: Quartus needs
// a perfect match to the template, and any attempt to
// refactor the two always blocks into one will break
// memory inference.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk9
if (EMPTY_LATENCY == 1) begin : gen_blk10
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] = in_payload;
internal_out_payload = mem[mem_rd_ptr];
end
end else begin : gen_blk10_else
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] <= in_payload;
internal_out_payload <= mem[mem_rd_ptr];
end
end
assign mem_rd_ptr = next_rd_ptr;
end else begin : gen_blk9_else
// --------------------------------------------------
// Register-based FIFO storage
//
// Uses a shift register as the storage element. Each
// shift register slot has a bit which indicates if
// the slot is occupied (credit to Sam H for the idea).
// The occupancy bits are contiguous and start from the
// lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
// FIFO.
//
// Each slot is enabled during a read or when it
// is unoccupied. New data is always written to every
// going-to-be-empty slot (we keep track of which ones
// are actually useful with the occupancy bits). On a
// read we shift occupied slots.
//
// The exception is the last slot, which always gets
// new data when it is unoccupied.
// --------------------------------------------------
for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
always @(posedge clk or posedge reset) begin
if (reset) begin
mem[i] <= 0;
end
else if (read || !mem_used[i]) begin
if (!mem_used[i+1])
mem[i] <= in_payload;
else
mem[i] <= mem[i+1];
end
end
end
always @(posedge clk, posedge reset) begin
if (reset) begin
mem[DEPTH-1] <= 0;
end
else begin
if (DEPTH == 1) begin
if (write)
mem[DEPTH-1] <= in_payload;
end
else if (!mem_used[DEPTH-1])
mem[DEPTH-1] <= in_payload;
end
end
end
endgenerate
assign read = internal_out_ready && internal_out_valid && ok_to_forward;
assign write = in_ready && in_valid;
// --------------------------------------------------
// Pointer Management
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk11
assign incremented_wr_ptr = wr_ptr + 1'b1;
assign incremented_rd_ptr = rd_ptr + 1'b1;
assign next_wr_ptr = drop_on_error ? curr_sop_ptr : write ? incremented_wr_ptr : wr_ptr;
assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
always @(posedge clk or posedge reset) begin
if (reset) begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else begin
wr_ptr <= next_wr_ptr;
rd_ptr <= next_rd_ptr;
end
end
end else begin : gen_blk11_else
// --------------------------------------------------
// Shift Register Occupancy Bits
//
// Consider a 4-deep FIFO with 2 entries: 0011
// On a read and write, do not modify the bits.
// On a write, left-shift the bits to get 0111.
// On a read, right-shift the bits to get 0001.
//
// Also, on a write we set bit0 (the head), while
// clearing the tail on a read.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[0] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[0] <= 1;
else if (read) begin
if (DEPTH > 1)
mem_used[0] <= mem_used[1];
else
mem_used[0] <= 0;
end
end
end
end
if (DEPTH > 1) begin : gen_blk12
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[DEPTH-1] <= 0;
end
else begin
if (write ^ read) begin
mem_used[DEPTH-1] <= 0;
if (write)
mem_used[DEPTH-1] <= mem_used[DEPTH-2];
end
end
end
end
for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
always @(posedge clk, posedge reset) begin
if (reset) begin
mem_used[i] <= 0;
end
else begin
if (write ^ read) begin
if (write)
mem_used[i] <= mem_used[i-1];
else if (read)
mem_used[i] <= mem_used[i+1];
end
end
end
end
end
endgenerate
// --------------------------------------------------
// Memory FIFO Status Management
//
// Generates the full and empty signals from the
// pointers. The FIFO is full when the next write
// pointer will be equal to the read pointer after
// a write. Reading from a FIFO clears full.
//
// The FIFO is empty when the next read pointer will
// be equal to the write pointer after a read. Writing
// to a FIFO clears empty.
//
// A simultaneous read and write must not change any of
// the empty or full flags unless there is a drop on error event.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk13
always @* begin
next_full = full;
next_empty = empty;
if (read && !write) begin
next_full = 1'b0;
if (incremented_rd_ptr == wr_ptr)
next_empty = 1'b1;
end
if (write && !read) begin
if (!drop_on_error)
next_empty = 1'b0;
else if (curr_sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo
next_empty = 1'b1;
if (incremented_wr_ptr == rd_ptr && !drop_on_error)
next_full = 1'b1;
end
if (write && read && drop_on_error) begin
if (curr_sop_ptr == next_rd_ptr)
next_empty = 1'b1;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
empty <= 1;
full <= 0;
end
else begin
empty <= next_empty;
full <= next_full;
end
end
end else begin : gen_blk13_else
// --------------------------------------------------
// Register FIFO Status Management
//
// Full when the tail occupancy bit is 1. Empty when
// the head occupancy bit is 0.
// --------------------------------------------------
always @* begin
full = mem_used[DEPTH-1];
empty = !mem_used[0];
// ------------------------------------------
// For a single slot FIFO, reading clears the
// full status immediately.
// ------------------------------------------
if (DEPTH == 1)
full = mem_used[0] && !read;
internal_out_payload = mem[0];
// ------------------------------------------
// Writes clear empty immediately for lookahead modes.
// Note that we use in_valid instead of write to avoid
// combinational loops (in lookahead mode, qualifying
// with in_ready is meaningless).
//
// In a 1-deep FIFO, a possible combinational loop runs
// from write -> out_valid -> out_ready -> write
// ------------------------------------------
if (EMPTY_LATENCY == 0) begin
empty = !mem_used[0] && !in_valid;
if (!mem_used[0] && in_valid)
internal_out_payload = in_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Avalon-ST Signals
//
// The in_ready signal is straightforward.
//
// To match memory latency when empty latency > 1,
// out_valid assertions must be delayed by one clock
// cycle.
//
// Note: out_valid deassertions must not be delayed or
// the FIFO will underflow.
// --------------------------------------------------
assign in_ready = !full;
assign internal_out_ready = out_ready || !out_valid;
generate if (EMPTY_LATENCY > 1) begin : gen_blk14
always @(posedge clk or posedge reset) begin
if (reset)
internal_out_valid <= 0;
else begin
internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
if (read) begin
if (incremented_rd_ptr == wr_ptr)
internal_out_valid <= 1'b0;
end
end
end
end else begin : gen_blk14_else
always @* begin
internal_out_valid = !empty & ok_to_forward;
end
end
endgenerate
// --------------------------------------------------
// Single Output Pipeline Stage
//
// This output pipeline stage is enabled if the FIFO's
// empty latency is set to 3 (default). It is disabled
// for all other allowed latencies.
//
// Reason: The memory outputs are unregistered, so we have to
// register the output or fmax will drop if combinatorial
// logic is present on the output datapath.
//
// Q: The Avalon-ST spec says that I have to register my outputs
// But isn't the memory counted as a register?
// A: The path from the address lookup to the memory output is
// slow. Registering the memory outputs is a good idea.
//
// The registers get packed into the memory by the fitter
// which means minimal resources are consumed (the result
// is a altsyncram with registered outputs, available on
// all modern Altera devices).
//
// This output stage acts as an extra slot in the FIFO,
// and complicates the fill level.
// --------------------------------------------------
generate if (EMPTY_LATENCY == 3) begin : gen_blk15
always @(posedge clk or posedge reset) begin
if (reset) begin
out_valid <= 0;
out_payload <= 0;
end
else begin
if (internal_out_ready) begin
out_valid <= internal_out_valid & ok_to_forward;
out_payload <= internal_out_payload;
end
end
end
end
else begin : gen_blk15_else
always @* begin
out_valid = internal_out_valid;
out_payload = internal_out_payload;
end
end
endgenerate
// --------------------------------------------------
// Fill Level
//
// The fill level is calculated from the next write
// and read pointers to avoid unnecessary latency
// and logic.
//
// However, if the store-and-forward mode of the FIFO
// is enabled, the fill level is an up-down counter
// for fmax optimization reasons.
//
// If the output pipeline is enabled, the fill level
// must account for it, or we'll always be off by one.
// This may, or may not be important depending on the
// application.
//
// For now, we'll always calculate the exact fill level
// at the cost of an extra adder when the output stage
// is enabled.
// --------------------------------------------------
generate if (USE_FILL_LEVEL) begin : gen_blk16
wire [31:0] depth32;
assign depth32 = DEPTH;
if (USE_STORE_FORWARD) begin
reg [ADDR_WIDTH : 0] curr_packet_len_less_one;
// --------------------------------------------------
// We only drop on endofpacket. As long as we don't add to the fill
// level on the dropped endofpacket cycle, we can simply subtract
// (packet length - 1) from the fill level for dropped packets.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
curr_packet_len_less_one <= 0;
end else begin
if (write) begin
curr_packet_len_less_one <= curr_packet_len_less_one + 1'b1;
if (in_endofpacket)
curr_packet_len_less_one <= 0;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
fifo_fill_level <= 0;
end else if (drop_on_error) begin
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one;
if (read)
fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one - 1'b1;
end else if (write && !read) begin
fifo_fill_level <= fifo_fill_level + 1'b1;
end else if (read && !write) begin
fifo_fill_level <= fifo_fill_level - 1'b1;
end
end
end else begin
always @(posedge clk or posedge reset) begin
if (reset)
fifo_fill_level <= 0;
else if (next_full & !drop_on_error)
fifo_fill_level <= depth32[ADDR_WIDTH:0];
else begin
fifo_fill_level[ADDR_WIDTH] <= 1'b0;
fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
end
end
end
always @* begin
fill_level = fifo_fill_level;
if (EMPTY_LATENCY == 3)
fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
end
end
else begin : gen_blk16_else
always @* begin
fill_level = 0;
end
end
endgenerate
generate if (USE_ALMOST_FULL_IF) begin : gen_blk17
assign almost_full_data = (fill_level >= almost_full_threshold);
end
else
assign almost_full_data = 0;
endgenerate
generate if (USE_ALMOST_EMPTY_IF) begin : gen_blk18
assign almost_empty_data = (fill_level <= almost_empty_threshold);
end
else
assign almost_empty_data = 0;
endgenerate
// --------------------------------------------------
// Avalon-MM Status & Control Connection Point
//
// Register map:
//
// | Addr | RW | 31 - 0 |
// | 0 | R | Fill level |
//
// The registering of this connection point means
// that there is a cycle of latency between
// reads/writes and the updating of the fill level.
// --------------------------------------------------
generate if (USE_STORE_FORWARD) begin : gen_blk19
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
cut_through_threshold <= 0;
drop_on_error_en <= 0;
csr_readdata <= 0;
pkt_mode <= 1'b1;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 5)
csr_readdata <= {31'b0, drop_on_error_en};
else if (csr_address == 4)
csr_readdata <= {8'b0, cut_through_threshold};
else if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b101)
drop_on_error_en <= csr_writedata[0];
else if(csr_address == 3'b100) begin
cut_through_threshold <= csr_writedata[23:0];
pkt_mode <= (csr_writedata[23:0] == 0);
end
else if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin : gen_blk19_else1
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
csr_readdata <= 0;
end
else begin
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
else if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
else if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
else if (csr_write) begin
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
else if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
end
end
end
end
else begin : gen_blk19_else2
always @(posedge clk or posedge reset) begin
if (reset) begin
csr_readdata <= 0;
end
else if (csr_read) begin
csr_readdata <= 0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
end
end
end
endgenerate
// --------------------------------------------------
// Store and forward logic
// --------------------------------------------------
// if the fifo gets full before the entire packet or the
// cut-threshold condition is met then start sending out
// data in order to avoid dead-lock situation
generate if (USE_STORE_FORWARD) begin : gen_blk20
assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave);
assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) :
~wait_for_threshold) | fifo_too_small_r;
assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket;
assign in_pkt_start = in_valid & in_ready & in_startofpacket;
assign in_pkt_error = in_valid & in_ready & |in_error;
assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket;
assign out_pkt_leave = out_valid & out_ready & out_endofpacket;
assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
// count packets coming and going into the fifo
always @(posedge clk or posedge reset) begin
if (reset) begin
pkt_cnt <= 0;
pkt_has_started <= 0;
sop_has_left_fifo <= 0;
fifo_too_small_r <= 0;
pkt_cnt_eq_zero <= 1'b1;
pkt_cnt_eq_one <= 1'b0;
fifo_fill_level_lt_cut_through_threshold <= 1'b1;
end
else begin
fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
fifo_too_small_r <= fifo_too_small;
if( in_pkt_eop_arrive )
sop_has_left_fifo <= 1'b0;
else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
sop_has_left_fifo <= 1'b1;
if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
pkt_cnt <= pkt_cnt + 1'b1;
pkt_cnt_eq_zero <= 0;
if (pkt_cnt == 0)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
pkt_cnt <= pkt_cnt - 1'b1;
if (pkt_cnt == 1)
pkt_cnt_eq_zero <= 1'b1;
else
pkt_cnt_eq_zero <= 1'b0;
if (pkt_cnt == 2)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
if (in_pkt_start)
pkt_has_started <= 1'b1;
else if (in_pkt_eop_arrive)
pkt_has_started <= 1'b0;
end
end
// drop on error logic
always @(posedge clk or posedge reset) begin
if (reset) begin
sop_ptr <= 0;
error_in_pkt <= 0;
end
else begin
// save the location of the SOP
if ( in_pkt_start )
sop_ptr <= wr_ptr;
// remember if error in pkt
// log error only if packet has already started
if (in_pkt_eop_arrive)
error_in_pkt <= 1'b0;
else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
error_in_pkt <= 1'b1;
end
end
assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive &
~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
assign curr_sop_ptr = (write && in_startofpacket && in_endofpacket) ? wr_ptr : sop_ptr;
end
else begin : gen_blk20_else
assign ok_to_forward = 1'b1;
assign drop_on_error = 1'b0;
if (ADDR_WIDTH <= 1)
assign curr_sop_ptr = 1'b0;
else
assign curr_sop_ptr = {ADDR_WIDTH - 1 { 1'b0 }};
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
reg[31:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i[30:0] << 1;
end
end
endfunction
endmodule
|
// This tests SystemVerilog interfaces
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Iztok Jeras.
module test ();
// error counter
bit err = 0;
logic clk = 1'b1;
logic rst = 1'b1; // reset
integer rst_cnt = 0;
// clock generator
always #5 clk = ~clk;
// reset is removed after a delay
always @ (posedge clk)
begin
rst_cnt <= rst_cnt + 1;
rst <= rst_cnt <= 3;
end
// counters
int cnt;
int cnt_src;
int cnt_drn;
// add all counters
assign cnt = cnt_src + cnt_drn + inf.cnt;
// finish report
initial begin
wait (cnt == 3*16);
if (!err) $display("PASSED");
$finish;
end
// interface instance
handshake inf (
.clk (clk),
.rst (rst)
);
// source instance
source #(
.RW (8),
.RP (8'b11100001)
) source (
.clk (clk),
.rst (rst),
.inf (inf),
.cnt (cnt_src)
);
// drain instance
drain #(
.RW (8),
.RP (8'b11010100)
) drain (
.clk (clk),
.rst (rst),
.inf (inf),
.cnt (cnt_drn)
);
endmodule
// interface definition
interface handshake #(
parameter int unsigned WC = 32
)(
input logic clk,
input logic rst
);
// modport signals
logic req; // request
logic grt; // grant
logic inc; // increment
// local signals
integer cnt; // counter
// source
modport src (
output req,
input grt
);
// drain
modport drn (
input req,
output grt
);
// incremet condition
assign inc = req & grt;
// local logic (counter)
always @ (posedge clk, posedge rst)
if (rst) cnt <= '0;
else cnt <= cnt + inc;
endinterface
// source module
module source #(
// random generator parameters
parameter int unsigned RW=1, // LFSR width
parameter bit [RW-1:0] RP='0, // LFSR polinom
parameter bit [RW-1:0] RR='1 // LFSR reset state
)(
input logic clk,
input logic rst,
handshake.src inf,
output integer cnt
);
// LFSR
logic [RW-1:0] rnd;
// LFSR in Galois form
always @ (posedge clk, posedge rst)
if (rst) rnd <= RR;
else rnd <= {rnd[0], rnd[RW-1:1]} ^ ({RW{rnd[0]}} & RP);
// counter
always @ (posedge clk, posedge rst)
if (rst) cnt <= 32'd0;
else cnt <= cnt + (inf.req & inf.grt);
// request signal
assign inf.req = rnd[0];
endmodule
// drain module
module drain #(
// random generator parameters
parameter int unsigned RW=1, // LFSR width
parameter bit [RW-1:0] RP='0, // LFSR polinom
parameter bit [RW-1:0] RR='1 // LFSR reset state
)(
input logic clk,
input logic rst,
handshake.drn inf,
output integer cnt
);
// LFSR
logic [RW-1:0] rnd;
// LFSR in Galois form
always @ (posedge clk, posedge rst)
if (rst) rnd <= RR;
else rnd <= {rnd[0], rnd[RW-1:1]} ^ ({RW{rnd[0]}} & RP);
// counter
always @ (posedge clk, posedge rst)
if (rst) cnt <= 32'd0;
else cnt <= cnt + (inf.req & inf.grt);
// grant signal
assign inf.grt = rnd[0];
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module sys_rst
(
input cpu_bus_clk,
input cpu_bus_rst_n,
input pcie_perst_n,
input user_reset_out,
input pcie_pl_hot_rst,
input pcie_user_logic_rst,
output pcie_sys_rst_n,
output pcie_user_rst_n
);
localparam LP_PCIE_RST_CNT_WIDTH = 9;
localparam LP_PCIE_RST_CNT = 380;
localparam LP_PCIE_HOT_RST_CNT = 50;
localparam S_RESET = 6'b000001;
localparam S_RESET_CNT = 6'b000010;
localparam S_HOT_RESET = 6'b000100;
localparam S_HOT_RESET_CNT = 6'b001000;
localparam S_HOT_RESET_WAIT = 6'b010000;
localparam S_IDLE = 6'b100000;
reg [5:0] cur_state;
reg [5:0] next_state;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_perst_n;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_perst_n_sync;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_pl_hot_rst;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_pl_hot_rst_sync;
reg [LP_PCIE_RST_CNT_WIDTH-1:0] r_rst_cnt;
reg r_pcie_sys_rst_n;
reg r_pcie_hot_rst;
assign pcie_user_rst_n = ~(user_reset_out | r_pcie_hot_rst);
//assign pcie_user_rst_n = ~(user_reset_out);
assign pcie_sys_rst_n = r_pcie_sys_rst_n;
always @ (posedge cpu_bus_clk)
begin
r_pcie_perst_n_sync <= pcie_perst_n;
r_pcie_perst_n <= r_pcie_perst_n_sync;
r_pcie_pl_hot_rst_sync <= pcie_pl_hot_rst;
r_pcie_pl_hot_rst <= r_pcie_pl_hot_rst_sync;
end
always @ (posedge cpu_bus_clk or negedge cpu_bus_rst_n)
begin
if(cpu_bus_rst_n == 0)
cur_state <= S_RESET;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_RESET: begin
next_state <= S_RESET_CNT;
end
S_RESET_CNT: begin
if(r_pcie_perst_n == 0)
next_state <= S_RESET;
else if(r_rst_cnt == 0)
next_state <= S_IDLE;
else
next_state <= S_RESET_CNT;
end
S_HOT_RESET: begin
next_state <= S_HOT_RESET_CNT;
end
S_HOT_RESET_CNT: begin
if(r_pcie_perst_n == 0)
next_state <= S_RESET;
else if(r_rst_cnt == 0)
next_state <= S_HOT_RESET_WAIT;
else
next_state <= S_HOT_RESET_CNT;
end
S_HOT_RESET_WAIT: begin
if(r_pcie_perst_n == 0)
next_state <= S_RESET;
else if(r_pcie_pl_hot_rst == 1)
next_state <= S_HOT_RESET_WAIT;
else
next_state <= S_IDLE;
end
S_IDLE: begin
if(r_pcie_perst_n == 0)
next_state <= S_RESET;
else if(r_pcie_pl_hot_rst == 1 || pcie_user_logic_rst == 1)
next_state <= S_HOT_RESET;
else
next_state <= S_IDLE;
end
default: begin
next_state <= S_RESET;
end
endcase
end
always @ (posedge cpu_bus_clk)
begin
case(cur_state)
S_RESET: begin
r_rst_cnt <= LP_PCIE_RST_CNT;
end
S_RESET_CNT: begin
r_rst_cnt <= r_rst_cnt - 1'b1;
end
S_HOT_RESET: begin
r_rst_cnt <= LP_PCIE_HOT_RST_CNT;
end
S_HOT_RESET_CNT: begin
r_rst_cnt <= r_rst_cnt - 1'b1;
end
S_HOT_RESET_WAIT: begin
end
S_IDLE: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_RESET: begin
r_pcie_sys_rst_n <= 0;
r_pcie_hot_rst <= 0;
end
S_RESET_CNT: begin
r_pcie_sys_rst_n <= 0;
r_pcie_hot_rst <= 0;
end
S_HOT_RESET: begin
r_pcie_sys_rst_n <= 1;
r_pcie_hot_rst <= 1;
end
S_HOT_RESET_CNT: begin
r_pcie_sys_rst_n <= 1;
r_pcie_hot_rst <= 1;
end
S_HOT_RESET_WAIT: begin
r_pcie_sys_rst_n <= 1;
r_pcie_hot_rst <= 1;
end
S_IDLE: begin
r_pcie_sys_rst_n <= 1;
r_pcie_hot_rst <= 0;
end
default: begin
r_pcie_sys_rst_n <= 0;
r_pcie_hot_rst <= 0;
end
endcase
end
endmodule |
// -----------------------------------------------------------
// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Description: Single clock Avalon-ST FIFO.
// -----------------------------------------------------------
`timescale 1 ns / 1 ns
//altera message_off 10036
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
parameter ERROR_WIDTH = 0,
parameter USE_PACKETS = 0,
parameter USE_FILL_LEVEL = 0,
parameter USE_STORE_FORWARD = 0,
parameter USE_ALMOST_FULL_IF = 0,
parameter USE_ALMOST_EMPTY_IF = 0,
// --------------------------------------------------
// Empty latency is defined as the number of cycles
// required for a write to deassert the empty flag.
// For example, a latency of 1 means that the empty
// flag is deasserted on the cycle after a write.
//
// Another way to think of it is the latency for a
// write to propagate to the output.
//
// An empty latency of 0 implies lookahead, which is
// only implemented for the register-based FIFO.
// --------------------------------------------------
parameter EMPTY_LATENCY = 3,
parameter USE_MEMORY_BLOCKS = 1,
// --------------------------------------------------
// Internal Parameters
// --------------------------------------------------
parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
// --------------------------------------------------
// Ports
// --------------------------------------------------
input clk,
input reset,
input [DATA_WIDTH-1: 0] in_data,
input in_valid,
input in_startofpacket,
input in_endofpacket,
input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty,
input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error,
input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel,
output in_ready,
output [DATA_WIDTH-1 : 0] out_data,
output reg out_valid,
output out_startofpacket,
output out_endofpacket,
output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty,
output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error,
output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
input out_ready,
input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address,
input csr_write,
input csr_read,
input [31 : 0] csr_writedata,
output reg [31 : 0] csr_readdata,
output wire almost_full_data,
output wire almost_empty_data
);
// --------------------------------------------------
// Local Parameters
// --------------------------------------------------
localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
localparam DEPTH = FIFO_DEPTH;
localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
// --------------------------------------------------
// Internal Signals
// --------------------------------------------------
genvar i;
reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
reg [ADDR_WIDTH-1 : 0] wr_ptr;
reg [ADDR_WIDTH-1 : 0] rd_ptr;
reg [DEPTH-1 : 0] mem_used;
wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
wire read;
wire write;
reg empty;
reg next_empty;
reg full;
reg next_full;
wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
wire [PAYLOAD_WIDTH-1 : 0] in_payload;
reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
reg [PAYLOAD_WIDTH-1 : 0] out_payload;
reg internal_out_valid;
wire internal_out_ready;
reg [ADDR_WIDTH : 0] fifo_fill_level;
reg [ADDR_WIDTH : 0] fill_level;
reg [ADDR_WIDTH-1 : 0] sop_ptr = 0;
reg [23:0] almost_full_threshold;
reg [23:0] almost_empty_threshold;
reg [23:0] cut_through_threshold;
reg [15:0] pkt_cnt;
reg [15:0] pkt_cnt_r;
reg [15:0] pkt_cnt_plusone;
reg [15:0] pkt_cnt_minusone;
reg drop_on_error_en;
reg error_in_pkt;
reg pkt_has_started;
reg sop_has_left_fifo;
reg fifo_too_small_r;
reg pkt_cnt_eq_zero;
reg pkt_cnt_eq_one;
reg pkt_cnt_changed;
wire wait_for_threshold;
reg pkt_mode;
wire wait_for_pkt;
wire ok_to_forward;
wire in_pkt_eop_arrive;
wire out_pkt_leave;
wire in_pkt_start;
wire in_pkt_error;
wire drop_on_error;
wire fifo_too_small;
wire out_pkt_sop_leave;
wire [31:0] max_fifo_size;
reg fifo_fill_level_lt_cut_through_threshold;
// --------------------------------------------------
// Define Payload
//
// Icky part where we decide which signals form the
// payload to the FIFO with generate blocks.
// --------------------------------------------------
generate
if (EMPTY_WIDTH > 0) begin
assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
end
else begin
assign out_empty = in_error;
assign in_packet_signals = {in_startofpacket, in_endofpacket};
assign {out_startofpacket, out_endofpacket} = out_packet_signals;
end
endgenerate
generate
if (USE_PACKETS) begin
if (ERROR_WIDTH > 0) begin
if (CHANNEL_WIDTH > 0) begin
assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
end
else begin
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data, in_error};
assign {out_packet_signals, out_data, out_error} = out_payload;
end
end
else begin
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin
assign in_payload = {in_packet_signals, in_data, in_channel};
assign {out_packet_signals, out_data, out_channel} = out_payload;
end
else begin
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data};
assign {out_packet_signals, out_data} = out_payload;
end
end
end
else begin
assign out_packet_signals = 0;
if (ERROR_WIDTH > 0) begin
if (CHANNEL_WIDTH > 0) begin
assign in_payload = {in_data, in_error, in_channel};
assign {out_data, out_error, out_channel} = out_payload;
end
else begin
assign out_channel = in_channel;
assign in_payload = {in_data, in_error};
assign {out_data, out_error} = out_payload;
end
end
else begin
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin
assign in_payload = {in_data, in_channel};
assign {out_data, out_channel} = out_payload;
end
else begin
assign out_channel = in_channel;
assign in_payload = in_data;
assign out_data = out_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Memory-based FIFO storage
//
// To allow a ready latency of 0, the read index is
// obtained from the next read pointer and memory
// outputs are unregistered.
//
// If the empty latency is 1, we infer bypass logic
// around the memory so writes propagate to the
// outputs on the next cycle.
//
// Do not change the way this is coded: Quartus needs
// a perfect match to the template, and any attempt to
// refactor the two always blocks into one will break
// memory inference.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin
if (EMPTY_LATENCY == 1) begin
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] = in_payload;
internal_out_payload = mem[mem_rd_ptr];
end
end else begin
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] <= in_payload;
internal_out_payload <= mem[mem_rd_ptr];
end
end
assign mem_rd_ptr = next_rd_ptr;
end else begin
// --------------------------------------------------
// Register-based FIFO storage
//
// Uses a shift register as the storage element. Each
// shift register slot has a bit which indicates if
// the slot is occupied (credit to Sam H for the idea).
// The occupancy bits are contiguous and start from the
// lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
// FIFO.
//
// Each slot is enabled during a read or when it
// is unoccupied. New data is always written to every
// going-to-be-empty slot (we keep track of which ones
// are actually useful with the occupancy bits). On a
// read we shift occupied slots.
//
// The exception is the last slot, which always gets
// new data when it is unoccupied.
// --------------------------------------------------
for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
always @(posedge clk or posedge reset) begin
if (reset) begin
mem[i] <= 0;
end
else if (read || !mem_used[i]) begin
if (!mem_used[i+1])
mem[i] <= in_payload;
else
mem[i] <= mem[i+1];
end
end
end
always @(posedge clk, posedge reset) begin
if (reset) begin
mem[DEPTH-1] <= 0;
end
else begin
if (!mem_used[DEPTH-1])
mem[DEPTH-1] <= in_payload;
if (DEPTH == 1) begin
if (write)
mem[DEPTH-1] <= in_payload;
end
end
end
end
endgenerate
assign read = internal_out_ready && internal_out_valid && ok_to_forward;
assign write = in_ready && in_valid;
// --------------------------------------------------
// Pointer Management
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin
assign incremented_wr_ptr = wr_ptr + 1'b1;
assign incremented_rd_ptr = rd_ptr + 1'b1;
assign next_wr_ptr = drop_on_error ? sop_ptr : write ? incremented_wr_ptr : wr_ptr;
assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
always @(posedge clk or posedge reset) begin
if (reset) begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else begin
wr_ptr <= next_wr_ptr;
rd_ptr <= next_rd_ptr;
end
end
end else begin
// --------------------------------------------------
// Shift Register Occupancy Bits
//
// Consider a 4-deep FIFO with 2 entries: 0011
// On a read and write, do not modify the bits.
// On a write, left-shift the bits to get 0111.
// On a read, right-shift the bits to get 0001.
//
// Also, on a write we set bit0 (the head), while
// clearing the tail on a read.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[0] <= 0;
end
else begin
if (write ^ read) begin
if (read) begin
if (DEPTH > 1)
mem_used[0] <= mem_used[1];
else
mem_used[0] <= 0;
end
if (write)
mem_used[0] <= 1;
end
end
end
if (DEPTH > 1) begin
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[DEPTH-1] <= 0;
end
else begin
if (write ^ read) begin
mem_used[DEPTH-1] <= 0;
if (write)
mem_used[DEPTH-1] <= mem_used[DEPTH-2];
end
end
end
end
for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
always @(posedge clk, posedge reset) begin
if (reset) begin
mem_used[i] <= 0;
end
else begin
if (write ^ read) begin
if (read)
mem_used[i] <= mem_used[i+1];
if (write)
mem_used[i] <= mem_used[i-1];
end
end
end
end
end
endgenerate
// --------------------------------------------------
// Memory FIFO Status Management
//
// Generates the full and empty signals from the
// pointers. The FIFO is full when the next write
// pointer will be equal to the read pointer after
// a write. Reading from a FIFO clears full.
//
// The FIFO is empty when the next read pointer will
// be equal to the write pointer after a read. Writing
// to a FIFO clears empty.
//
// A simultaneous read and write must not change any of
// the empty or full flags unless there is a drop on error event.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin
always @* begin
next_full = full;
next_empty = empty;
if (read && !write) begin
next_full = 1'b0;
if (incremented_rd_ptr == wr_ptr)
next_empty = 1'b1;
end
if (write && !read) begin
if (!drop_on_error)
next_empty = 1'b0;
else if (sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo
next_empty = 1'b1;
if (incremented_wr_ptr == rd_ptr && !drop_on_error)
next_full = 1'b1;
end
if (write && read && drop_on_error) begin
if (sop_ptr == next_rd_ptr)
next_empty = 1'b1;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
empty <= 1;
full <= 0;
end
else begin
empty <= next_empty;
full <= next_full;
end
end
end else begin
// --------------------------------------------------
// Register FIFO Status Management
//
// Full when the tail occupancy bit is 1. Empty when
// the head occupancy bit is 0.
// --------------------------------------------------
always @* begin
full = mem_used[DEPTH-1];
empty = !mem_used[0];
// ------------------------------------------
// For a single slot FIFO, reading clears the
// full status immediately.
// ------------------------------------------
if (DEPTH == 1)
full = mem_used[0] && !read;
internal_out_payload = mem[0];
// ------------------------------------------
// Writes clear empty immediately for lookahead modes.
// Note that we use in_valid instead of write to avoid
// combinational loops (in lookahead mode, qualifying
// with in_ready is meaningless).
//
// In a 1-deep FIFO, a possible combinational loop runs
// from write -> out_valid -> out_ready -> write
// ------------------------------------------
if (EMPTY_LATENCY == 0) begin
empty = !mem_used[0] && !in_valid;
if (!mem_used[0] && in_valid)
internal_out_payload = in_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Avalon-ST Signals
//
// The in_ready signal is straightforward.
//
// To match memory latency when empty latency > 1,
// out_valid assertions must be delayed by one clock
// cycle.
//
// Note: out_valid deassertions must not be delayed or
// the FIFO will underflow.
// --------------------------------------------------
assign in_ready = !full;
assign internal_out_ready = out_ready || !out_valid;
generate if (EMPTY_LATENCY > 1) begin
always @(posedge clk or posedge reset) begin
if (reset)
internal_out_valid <= 0;
else begin
internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
if (read) begin
if (incremented_rd_ptr == wr_ptr)
internal_out_valid <= 1'b0;
end
end
end
end else begin
always @* begin
internal_out_valid = !empty & ok_to_forward;
end
end
endgenerate
// --------------------------------------------------
// Single Output Pipeline Stage
//
// This output pipeline stage is enabled if the FIFO's
// empty latency is set to 3 (default). It is disabled
// for all other allowed latencies.
//
// Reason: The memory outputs are unregistered, so we have to
// register the output or fmax will drop if combinatorial
// logic is present on the output datapath.
//
// Q: The Avalon-ST spec says that I have to register my outputs
// But isn't the memory counted as a register?
// A: The path from the address lookup to the memory output is
// slow. Registering the memory outputs is a good idea.
//
// The registers get packed into the memory by the fitter
// which means minimal resources are consumed (the result
// is a altsyncram with registered outputs, available on
// all modern Altera devices).
//
// This output stage acts as an extra slot in the FIFO,
// and complicates the fill level.
// --------------------------------------------------
generate if (EMPTY_LATENCY == 3) begin
always @(posedge clk or posedge reset) begin
if (reset) begin
out_valid <= 0;
out_payload <= 0;
end
else begin
if (internal_out_ready) begin
out_valid <= internal_out_valid & ok_to_forward;
out_payload <= internal_out_payload;
end
end
end
end
else begin
always @* begin
out_valid = internal_out_valid;
out_payload = internal_out_payload;
end
end
endgenerate
// --------------------------------------------------
// Fill Level
//
// The fill level is calculated from the next write
// and read pointers to avoid unnecessary latency.
//
// If the output pipeline is enabled, the fill level
// must account for it, or we'll always be off by one.
// This may, or may not be important depending on the
// application.
//
// For now, we'll always calculate the exact fill level
// at the cost of an extra adder when the output stage
// is enabled.
// --------------------------------------------------
generate if (USE_FILL_LEVEL) begin
wire [31:0] depth32;
assign depth32 = DEPTH;
always @(posedge clk or posedge reset) begin
if (reset)
fifo_fill_level <= 0;
else if (next_full & !drop_on_error)
fifo_fill_level <= depth32[ADDR_WIDTH:0];
else begin
fifo_fill_level[ADDR_WIDTH] <= 1'b0;
fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
end
end
always @* begin
fill_level = fifo_fill_level;
if (EMPTY_LATENCY == 3)
fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
end
end
else begin
always @* begin
fill_level = 0;
end
end
endgenerate
generate if (USE_ALMOST_FULL_IF) begin
assign almost_full_data = (fill_level >= almost_full_threshold);
end
else
assign almost_full_data = 0;
endgenerate
generate if (USE_ALMOST_EMPTY_IF) begin
assign almost_empty_data = (fill_level <= almost_empty_threshold);
end
else
assign almost_empty_data = 0;
endgenerate
// --------------------------------------------------
// Avalon-MM Status & Control Connection Point
//
// Register map:
//
// | Addr | RW | 31 - 0 |
// | 0 | R | Fill level |
//
// The registering of this connection point means
// that there is a cycle of latency between
// reads/writes and the updating of the fill level.
// --------------------------------------------------
generate if (USE_STORE_FORWARD) begin
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
cut_through_threshold <= 0;
drop_on_error_en <= 0;
csr_readdata <= 0;
pkt_mode <= 1'b1;
end
else begin
if (csr_write) begin
if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
if(csr_address == 3'b100) begin
cut_through_threshold <= csr_writedata[23:0];
pkt_mode <= (csr_writedata[23:0] == 0);
end
if(csr_address == 3'b101)
drop_on_error_en <= csr_writedata[0];
end
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
if (csr_address == 4)
csr_readdata <= {8'b0, cut_through_threshold};
if (csr_address == 5)
csr_readdata <= {31'b0, drop_on_error_en};
end
end
end
end
else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
csr_readdata <= 0;
end
else begin
if (csr_write) begin
if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
end
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
end
end
end
end
else begin
always @(posedge clk or posedge reset) begin
if (reset) begin
csr_readdata <= 0;
end
else if (csr_read) begin
csr_readdata <= 0;
if (csr_address == 0)
csr_readdata <= fill_level;
end
end
end
endgenerate
// --------------------------------------------------
// Store and forward logic
// --------------------------------------------------
// if the fifo gets full before the entire packet or the
// cut-threshold condition is met then start sending out
// data in order to avoid dead-lock situation
generate if (USE_STORE_FORWARD) begin
assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave);
assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) :
~wait_for_threshold) | fifo_too_small_r;
assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket;
assign in_pkt_start = in_valid & in_ready & in_startofpacket;
assign in_pkt_error = in_valid & in_ready & |in_error;
assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket;
assign out_pkt_leave = out_valid & out_ready & out_endofpacket;
assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
// count packets coming and going into the fifo
always @(posedge clk or posedge reset) begin
if (reset) begin
pkt_cnt <= 0;
pkt_cnt_r <= 0;
pkt_cnt_plusone <= 1;
pkt_cnt_minusone <= 0;
pkt_cnt_changed <= 0;
pkt_has_started <= 0;
sop_has_left_fifo <= 0;
fifo_too_small_r <= 0;
pkt_cnt_eq_zero <= 1'b1;
pkt_cnt_eq_one <= 1'b0;
fifo_fill_level_lt_cut_through_threshold <= 1'b1;
end
else begin
fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
fifo_too_small_r <= fifo_too_small;
pkt_cnt_plusone <= pkt_cnt + 1'b1;
pkt_cnt_minusone <= pkt_cnt - 1'b1;
pkt_cnt_r <= pkt_cnt;
pkt_cnt_changed <= 1'b0;
if( in_pkt_eop_arrive )
sop_has_left_fifo <= 1'b0;
else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
sop_has_left_fifo <= 1'b1;
if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
pkt_cnt_changed <= 1'b1;
pkt_cnt <= pkt_cnt_changed ? pkt_cnt_r : pkt_cnt_plusone;
pkt_cnt_eq_zero <= 0;
if (pkt_cnt == 0)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
pkt_cnt_changed <= 1'b1;
pkt_cnt <= pkt_cnt_changed ? pkt_cnt_r : pkt_cnt_minusone;
if (pkt_cnt == 1)
pkt_cnt_eq_zero <= 1'b1;
else
pkt_cnt_eq_zero <= 1'b0;
if (pkt_cnt == 2)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
if (in_pkt_start)
pkt_has_started <= 1'b1;
else if (in_pkt_eop_arrive)
pkt_has_started <= 1'b0;
end
end
// drop on error logic
always @(posedge clk or posedge reset) begin
if (reset) begin
sop_ptr <= 0;
error_in_pkt <= 0;
end
else begin
// save the location of the SOP
if ( in_pkt_start )
sop_ptr <= wr_ptr;
// remember if error in pkt
// log error only if packet has already started
if (in_pkt_eop_arrive)
error_in_pkt <= 1'b0;
else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
error_in_pkt <= 1'b1;
end
end
assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive &
~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
end
else begin
assign ok_to_forward = 1'b1;
assign drop_on_error = 1'b0;
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
integer i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
|
/*
Copyright (c) 2014-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog-2001
`timescale 1 ns / 1 ps
/*
* Synchronizes an asyncronous signal to a given clock by using a pipeline of
* two registers.
*/
module sync_signal #(
parameter WIDTH=1, // width of the input and output signals
parameter N=2 // depth of synchronizer
)(
input wire clk,
input wire [WIDTH-1:0] in,
output wire [WIDTH-1:0] out
);
reg [WIDTH-1:0] sync_reg[N-1:0];
/*
* The synchronized output is the last register in the pipeline.
*/
assign out = sync_reg[N-1];
integer k;
always @(posedge clk) begin
sync_reg[0] <= in;
for (k = 1; k < N; k = k + 1) begin
sync_reg[k] <= sync_reg[k-1];
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR2B_PP_SYMBOL_V
`define SKY130_FD_SC_LS__OR2B_PP_SYMBOL_V
/**
* or2b: 2-input OR, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__or2b (
//# {{data|Data Signals}}
input A ,
input B_N ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR2B_PP_SYMBOL_V
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR with generic_baseblocks_v2_1_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_comparator_sel_mask #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
input wire [C_DATA_WIDTH-1:0] M,
input wire [C_DATA_WIDTH-1:0] V,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar lut_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 1;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] m_local;
wire [C_FIX_DATA_WIDTH-1:0] v_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign v_local = {V, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign m_local = M;
assign v_local = V;
end
// Instantiate one generic_baseblocks_v2_1_carry and per level.
for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[lut_cnt] = ( ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b0 ) ) |
( ( ( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( v_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ) & ( S == 1'b1 ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[lut_cnt+1]),
.CIN (carry_local[lut_cnt]),
.S (sel[lut_cnt])
);
end // end for lut_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A21BO_4_V
`define SKY130_FD_SC_MS__A21BO_4_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog wrapper for a21bo with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a21bo.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a21bo_4 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a21bo_4 (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A21BO_4_V
|
//
// Generated by Bluespec Compiler, version 2021.07 (build 4cac6eb)
//
//
// Ports:
// Name I/O size props
// RDY_server_reset_request_put O 1 reg
// RDY_server_reset_response_get O 1
// read_rs1 O 64
// read_rs1_port2 O 64
// read_rs2 O 64
// read_rs3 O 64
// CLK I 1 clock
// RST_N I 1 reset
// read_rs1_rs1 I 5
// read_rs1_port2_rs1 I 5
// read_rs2_rs2 I 5
// read_rs3_rs3 I 5
// write_rd_rd I 5
// write_rd_rd_val I 64 reg
// EN_server_reset_request_put I 1
// EN_server_reset_response_get I 1
// EN_write_rd I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkFPR_RegFile(CLK,
RST_N,
EN_server_reset_request_put,
RDY_server_reset_request_put,
EN_server_reset_response_get,
RDY_server_reset_response_get,
read_rs1_rs1,
read_rs1,
read_rs1_port2_rs1,
read_rs1_port2,
read_rs2_rs2,
read_rs2,
read_rs3_rs3,
read_rs3,
write_rd_rd,
write_rd_rd_val,
EN_write_rd);
input CLK;
input RST_N;
// action method server_reset_request_put
input EN_server_reset_request_put;
output RDY_server_reset_request_put;
// action method server_reset_response_get
input EN_server_reset_response_get;
output RDY_server_reset_response_get;
// value method read_rs1
input [4 : 0] read_rs1_rs1;
output [63 : 0] read_rs1;
// value method read_rs1_port2
input [4 : 0] read_rs1_port2_rs1;
output [63 : 0] read_rs1_port2;
// value method read_rs2
input [4 : 0] read_rs2_rs2;
output [63 : 0] read_rs2;
// value method read_rs3
input [4 : 0] read_rs3_rs3;
output [63 : 0] read_rs3;
// action method write_rd
input [4 : 0] write_rd_rd;
input [63 : 0] write_rd_rd_val;
input EN_write_rd;
// signals for module outputs
wire [63 : 0] read_rs1, read_rs1_port2, read_rs2, read_rs3;
wire RDY_server_reset_request_put, RDY_server_reset_response_get;
// register rg_state
reg [1 : 0] rg_state;
reg [1 : 0] rg_state$D_IN;
wire rg_state$EN;
// ports of submodule f_reset_rsps
wire f_reset_rsps$CLR,
f_reset_rsps$DEQ,
f_reset_rsps$EMPTY_N,
f_reset_rsps$ENQ,
f_reset_rsps$FULL_N;
// ports of submodule regfile
wire [63 : 0] regfile$D_IN,
regfile$D_OUT_1,
regfile$D_OUT_2,
regfile$D_OUT_3,
regfile$D_OUT_4;
wire [4 : 0] regfile$ADDR_1,
regfile$ADDR_2,
regfile$ADDR_3,
regfile$ADDR_4,
regfile$ADDR_5,
regfile$ADDR_IN;
wire regfile$WE;
// rule scheduling signals
wire CAN_FIRE_RL_rl_reset_loop,
CAN_FIRE_RL_rl_reset_start,
CAN_FIRE_server_reset_request_put,
CAN_FIRE_server_reset_response_get,
CAN_FIRE_write_rd,
WILL_FIRE_RL_rl_reset_loop,
WILL_FIRE_RL_rl_reset_start,
WILL_FIRE_server_reset_request_put,
WILL_FIRE_server_reset_response_get,
WILL_FIRE_write_rd;
// action method server_reset_request_put
assign RDY_server_reset_request_put = f_reset_rsps$FULL_N ;
assign CAN_FIRE_server_reset_request_put = f_reset_rsps$FULL_N ;
assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ;
// action method server_reset_response_get
assign RDY_server_reset_response_get =
rg_state == 2'd2 && f_reset_rsps$EMPTY_N ;
assign CAN_FIRE_server_reset_response_get =
rg_state == 2'd2 && f_reset_rsps$EMPTY_N ;
assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ;
// value method read_rs1
assign read_rs1 = regfile$D_OUT_4 ;
// value method read_rs1_port2
assign read_rs1_port2 = regfile$D_OUT_3 ;
// value method read_rs2
assign read_rs2 = regfile$D_OUT_2 ;
// value method read_rs3
assign read_rs3 = regfile$D_OUT_1 ;
// action method write_rd
assign CAN_FIRE_write_rd = 1'd1 ;
assign WILL_FIRE_write_rd = EN_write_rd ;
// submodule f_reset_rsps
FIFO20 #(.guarded(1'd1)) f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(f_reset_rsps$ENQ),
.DEQ(f_reset_rsps$DEQ),
.CLR(f_reset_rsps$CLR),
.FULL_N(f_reset_rsps$FULL_N),
.EMPTY_N(f_reset_rsps$EMPTY_N));
// submodule regfile
RegFile #(.addr_width(32'd5),
.data_width(32'd64),
.lo(5'h0),
.hi(5'd31)) regfile(.CLK(CLK),
.ADDR_1(regfile$ADDR_1),
.ADDR_2(regfile$ADDR_2),
.ADDR_3(regfile$ADDR_3),
.ADDR_4(regfile$ADDR_4),
.ADDR_5(regfile$ADDR_5),
.ADDR_IN(regfile$ADDR_IN),
.D_IN(regfile$D_IN),
.WE(regfile$WE),
.D_OUT_1(regfile$D_OUT_1),
.D_OUT_2(regfile$D_OUT_2),
.D_OUT_3(regfile$D_OUT_3),
.D_OUT_4(regfile$D_OUT_4),
.D_OUT_5());
// rule RL_rl_reset_start
assign CAN_FIRE_RL_rl_reset_start = rg_state == 2'd0 ;
assign WILL_FIRE_RL_rl_reset_start = rg_state == 2'd0 ;
// rule RL_rl_reset_loop
assign CAN_FIRE_RL_rl_reset_loop = rg_state == 2'd1 ;
assign WILL_FIRE_RL_rl_reset_loop = rg_state == 2'd1 ;
// register rg_state
always@(EN_server_reset_request_put or
WILL_FIRE_RL_rl_reset_loop or WILL_FIRE_RL_rl_reset_start)
case (1'b1)
EN_server_reset_request_put: rg_state$D_IN = 2'd0;
WILL_FIRE_RL_rl_reset_loop: rg_state$D_IN = 2'd2;
WILL_FIRE_RL_rl_reset_start: rg_state$D_IN = 2'd1;
default: rg_state$D_IN = 2'b10 /* unspecified value */ ;
endcase
assign rg_state$EN =
EN_server_reset_request_put || WILL_FIRE_RL_rl_reset_start ||
WILL_FIRE_RL_rl_reset_loop ;
// submodule f_reset_rsps
assign f_reset_rsps$ENQ = EN_server_reset_request_put ;
assign f_reset_rsps$DEQ = EN_server_reset_response_get ;
assign f_reset_rsps$CLR = 1'b0 ;
// submodule regfile
assign regfile$ADDR_1 = read_rs3_rs3 ;
assign regfile$ADDR_2 = read_rs2_rs2 ;
assign regfile$ADDR_3 = read_rs1_port2_rs1 ;
assign regfile$ADDR_4 = read_rs1_rs1 ;
assign regfile$ADDR_5 = 5'h0 ;
assign regfile$ADDR_IN = write_rd_rd ;
assign regfile$D_IN = write_rd_rd_val ;
assign regfile$WE = EN_write_rd ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
rg_state <= `BSV_ASSIGNMENT_DELAY 2'd0;
end
else
begin
if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
rg_state = 2'h2;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkFPR_RegFile
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module clk_divider(input reset, input wire in_clk,output reg out_clk, input [7:0] ratio);
reg [7:0] counter;
// FIXME maybe should use PLL or switch to double edge version
always @(posedge in_clk or posedge reset)
if(reset)
counter <= #1 8'd0;
else if(counter == 0)
counter <= #1 ratio[7:1] + (ratio[0] & out_clk) - 8'b1;
else
counter <= #1 counter-8'd1;
always @(posedge in_clk or posedge reset)
if(reset)
out_clk <= #1 1'b0;
else if(counter == 0)
out_clk <= #1 ~out_clk;
endmodule // clk_divider
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo_mixed_widths
// ============================================================
// File Name: rxlengthfifo_128x13.v
// Megafunction Name(s):
// dcfifo_mixed_widths
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 173 11/01/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module rxlengthfifo_128x13 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input aclr;
input [14:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [14:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "512"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "15"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "1"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "15"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "15"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
// Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "9"
// Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "15"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 15 0 INPUT NODEFVAL "data[14..0]"
// Retrieval info: USED_PORT: q 0 0 15 0 OUTPUT NODEFVAL "q[14..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 15 0 data 0 0 15 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 15 0 @q 0 0 15 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL rxlengthfifo_128x13.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rxlengthfifo_128x13.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rxlengthfifo_128x13.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rxlengthfifo_128x13.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rxlengthfifo_128x13_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rxlengthfifo_128x13_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
`timescale 1ns / 1ps
module RCB_FRL_OSERDES_MSG(OQ, CLK, CLKDIV, DI, OCE, SR);
output OQ;
input CLK, CLKDIV;
input [7:0] DI;
input OCE, SR;
wire SHIFT1, SHIFT2;
OSERDES OSERDES_inst1 (
.OQ(OQ), // 1-bit data path output
.SHIFTOUT1(), // 1-bit data expansion output
.SHIFTOUT2(), // 1-bit data expansion output
.TQ(), // 1-bit 3-state control output
.CLK(CLK), // 1-bit clock input
.CLKDIV(CLKDIV), // 1-bit divided clock input
.D1(DI[7]), // 1-bit parallel data input
.D2(DI[6]), // 1-bit parallel data input
.D3(DI[5]), // 1-bit parallel data input
.D4(DI[4]), // 1-bit parallel data input
.D5(DI[3]), // 1-bit parallel data input
.D6(DI[2]), // 1-bit parallel data input
.OCE(OCE), // 1-bit clock enable input
.REV(1'b0), // 1-bit reverse SR input
.SHIFTIN1(SHIFT1), // 1-bit data expansion input
.SHIFTIN2(SHIFT2), // 1-bit data expansion input
.SR(SR), // 1-bit set/reset input
.T1(), // 1-bit parallel 3-state input
.T2(), // 1-bit parallel 3-state input
.T3(), // 1-bit parallel 3-state input
.T4(), // 1-bit parallel 3-state input
.TCE(1'b1) // 1-bit 3-state signal clock enable input
);
defparam OSERDES_inst1.DATA_RATE_OQ = "DDR";
defparam OSERDES_inst1.DATA_RATE_TQ = "DDR";
defparam OSERDES_inst1.DATA_WIDTH = 8;
defparam OSERDES_inst1.SERDES_MODE = "MASTER";
defparam OSERDES_inst1.TRISTATE_WIDTH = 1;
OSERDES OSERDES_inst2 (
.OQ(), // 1-bit data path output
.SHIFTOUT1(SHIFT1), // 1-bit data expansion output
.SHIFTOUT2(SHIFT2), // 1-bit data expansion output
.TQ(), // 1-bit 3-state control output
.CLK(CLK), // 1-bit clock input
.CLKDIV(CLKDIV), // 1-bit divided clock input
.D1(), // 1-bit parallel data input
.D2(), // 1-bit parallel data input
.D3(DI[1]), // 1-bit parallel data input
.D4(DI[0]), // 1-bit parallel data input
.D5(), // 1-bit parallel data input
.D6(), // 1-bit parallel data input
.OCE(OCE), // 1-bit clock enable input
.REV(1'b0), // 1-bit reverse SR input
.SHIFTIN1(), // 1-bit data expansion input
.SHIFTIN2(), // 1-bit data expansion input
.SR(SR), // 1-bit set/reset input
.T1(), // 1-bit parallel 3-state input
.T2(), // 1-bit parallel 3-state input
.T3(), // 1-bit parallel 3-state input
.T4(), // 1-bit parallel 3-state input
.TCE(1'b1) // 1-bit 3-state signal clock enable input
);
defparam OSERDES_inst2.DATA_RATE_OQ = "DDR";
defparam OSERDES_inst2.DATA_RATE_TQ = "DDR";
defparam OSERDES_inst2.DATA_WIDTH = 8;
defparam OSERDES_inst2.SERDES_MODE = "SLAVE";
defparam OSERDES_inst2.TRISTATE_WIDTH = 1;
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module ANN_fptrunc_64ns_32_1
#(parameter
ID = 4,
NUM_STAGE = 1,
din0_WIDTH = 64,
dout_WIDTH = 32
)(
input wire [din0_WIDTH-1:0] din0,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire a_tvalid;
wire [63:0] a_tdata;
wire r_tvalid;
wire [31:0] r_tdata;
//------------------------Instantiation------------------
ANN_ap_fptrunc_0_no_dsp_64 ANN_ap_fptrunc_0_no_dsp_64_u (
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign a_tvalid = 1'b1;
assign a_tdata = din0==='bx ? 'b0 : din0;
assign dout = r_tdata;
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_arb2
#(
// Configuration
parameter string PIPELINE = "data_stall", // none|data|stall|data_stall|stall_data
parameter integer KEEP_LAST_GRANT = 1, // 0|1 - if one request can last multiple cycles (e.g. write burst), KEEP_LAST_GRANT must be 1
parameter integer NO_STALL_NETWORK = 0, // 0|1 - if one, remove the ability for arb to stall backward - must guarantee no collisions!
// Masters
parameter integer DATA_W = 32, // > 0
parameter integer BURSTCOUNT_W = 4, // > 0
parameter integer ADDRESS_W = 32, // > 0
parameter integer BYTEENA_W = DATA_W / 8, // > 0
parameter integer ID_W = 1 // > 0
)
(
// INPUTS
input logic clock,
input logic resetn,
// INTERFACES
acl_arb_intf m0_intf,
acl_arb_intf m1_intf,
acl_arb_intf mout_intf
);
/////////////////////////////////////////////
// ARCHITECTURE
/////////////////////////////////////////////
// mux_intf acts as an interface immediately after request arbitration
acl_arb_intf #(
.DATA_W( DATA_W ),
.BURSTCOUNT_W( BURSTCOUNT_W ),
.ADDRESS_W( ADDRESS_W ),
.BYTEENA_W( BYTEENA_W ),
.ID_W( ID_W )
)
mux_intf();
// Selector and request arbitration.
logic mux_sel;
assign mux_intf.req = mux_sel ? m1_intf.req : m0_intf.req;
generate
if( KEEP_LAST_GRANT == 1 )
begin
logic last_mux_sel_r;
always_ff @( posedge clock )
last_mux_sel_r <= mux_sel;
always_comb
// Maintain last grant.
if( last_mux_sel_r == 1'b0 && m0_intf.req.request )
mux_sel = 1'b0;
else if( last_mux_sel_r == 1'b1 && m1_intf.req.request )
mux_sel = 1'b1;
// Arbitrarily favor m0.
else
mux_sel = m0_intf.req.request ? 1'b0 : 1'b1;
end
else
begin
// Arbitrarily favor m0.
assign mux_sel = m0_intf.req.request ? 1'b0 : 1'b1;
end
endgenerate
// Stall signal for each upstream master.
generate
if( NO_STALL_NETWORK == 1 )
begin
assign m0_intf.stall = '0;
assign m1_intf.stall = '0;
end
else
begin
assign m0_intf.stall = ( mux_sel & m1_intf.req.request) | mux_intf.stall;
assign m1_intf.stall = (~mux_sel & m0_intf.req.request) | mux_intf.stall;
end
endgenerate
// What happens at the output of the arbitration block? Depends on the pipelining option...
// Each option is responsible for the following:
// 1. Connecting mout_intf.req: request output of the arbitration block
// 2. Connecting mux_intf.stall: upstream (to input masters) stall signal
generate
if( PIPELINE == "none" )
begin
// Purely combinational. Not a single register to be seen.
// Request for downstream blocks.
assign mout_intf.req = mux_intf.req;
// Stall signal from downstream blocks
assign mux_intf.stall = mout_intf.stall;
end
else if( PIPELINE == "data" )
begin
// Standard pipeline register at output. Latency of one cycle.
acl_arb_intf #(
.DATA_W( DATA_W ),
.BURSTCOUNT_W( BURSTCOUNT_W ),
.ADDRESS_W( ADDRESS_W ),
.BYTEENA_W( BYTEENA_W ),
.ID_W( ID_W )
)
pipe_intf();
acl_arb_pipeline_reg #(
.DATA_W( DATA_W ),
.BURSTCOUNT_W( BURSTCOUNT_W ),
.ADDRESS_W( ADDRESS_W ),
.BYTEENA_W( BYTEENA_W ),
.ID_W( ID_W )
)
pipe(
.clock( clock ),
.resetn( resetn ),
.in_intf( mux_intf ),
.out_intf( pipe_intf )
);
// Request for downstream blocks.
assign mout_intf.req = pipe_intf.req;
// Stall signal from downstream blocks.
assign pipe_intf.stall = mout_intf.stall;
end
else if( PIPELINE == "stall" )
begin
// Staging register at output. Min. latency of zero cycles, max. latency of one cycle.
acl_arb_intf #(
.DATA_W( DATA_W ),
.BURSTCOUNT_W( BURSTCOUNT_W ),
.ADDRESS_W( ADDRESS_W ),
.BYTEENA_W( BYTEENA_W ),
.ID_W( ID_W )
)
staging_intf();
acl_arb_staging_reg #(
.DATA_W( DATA_W ),
.BURSTCOUNT_W( BURSTCOUNT_W ),
.ADDRESS_W( ADDRESS_W ),
.BYTEENA_W( BYTEENA_W ),
.ID_W( ID_W )
)
staging(
.clock( clock ),
.resetn( resetn ),
.in_intf( mux_intf ),
.out_intf( staging_intf )
);
// Request for downstream blocks.
assign mout_intf.req = staging_intf.req;
// Stall signal from downstream blocks.
assign staging_intf.stall = mout_intf.stall;
end
else if( PIPELINE == "data_stall" )
begin
// Pipeline register followed by staging register at output. Min. latency
// of one cycle, max. latency of two cycles.
acl_arb_intf #(
.DATA_W( DATA_W ),
.BURSTCOUNT_W( BURSTCOUNT_W ),
.ADDRESS_W( ADDRESS_W ),
.BYTEENA_W( BYTEENA_W ),
.ID_W( ID_W )
)
pipe_intf(), staging_intf();
acl_arb_pipeline_reg #(
.DATA_W( DATA_W ),
.BURSTCOUNT_W( BURSTCOUNT_W ),
.ADDRESS_W( ADDRESS_W ),
.BYTEENA_W( BYTEENA_W ),
.ID_W( ID_W )
)
pipe(
.clock( clock ),
.resetn( resetn ),
.in_intf( mux_intf ),
.out_intf( pipe_intf )
);
acl_arb_staging_reg #(
.DATA_W( DATA_W ),
.BURSTCOUNT_W( BURSTCOUNT_W ),
.ADDRESS_W( ADDRESS_W ),
.BYTEENA_W( BYTEENA_W ),
.ID_W( ID_W )
)
staging(
.clock( clock ),
.resetn( resetn ),
.in_intf( pipe_intf ),
.out_intf( staging_intf )
);
// Request for downstream blocks.
assign mout_intf.req = staging_intf.req;
// Stall signal from downstream blocks.
assign staging_intf.stall = mout_intf.stall;
end
else if( PIPELINE == "stall_data" )
begin
// Staging register followed by pipeline register at output. Min. latency
// of one cycle, max. latency of two cycles.
acl_arb_intf #(
.DATA_W( DATA_W ),
.BURSTCOUNT_W( BURSTCOUNT_W ),
.ADDRESS_W( ADDRESS_W ),
.BYTEENA_W( BYTEENA_W ),
.ID_W( ID_W )
)
staging_intf(), pipe_intf();
acl_arb_staging_reg #(
.DATA_W( DATA_W ),
.BURSTCOUNT_W( BURSTCOUNT_W ),
.ADDRESS_W( ADDRESS_W ),
.BYTEENA_W( BYTEENA_W ),
.ID_W( ID_W )
)
staging(
.clock( clock ),
.resetn( resetn ),
.in_intf( mux_intf ),
.out_intf( staging_intf )
);
acl_arb_pipeline_reg #(
.DATA_W( DATA_W ),
.BURSTCOUNT_W( BURSTCOUNT_W ),
.ADDRESS_W( ADDRESS_W ),
.BYTEENA_W( BYTEENA_W ),
.ID_W( ID_W )
)
pipe(
.clock( clock ),
.resetn( resetn ),
.in_intf( staging_intf ),
.out_intf( pipe_intf )
);
// Request for downstream blocks.
assign mout_intf.req = pipe_intf.req;
// Stall signal from downstream blocks.
assign pipe_intf.stall = mout_intf.stall;
end
endgenerate
endmodule
module acl_arb_pipeline_reg #(
parameter integer DATA_W = 32, // > 0
parameter integer BURSTCOUNT_W = 4, // > 0
parameter integer ADDRESS_W = 32, // > 0
parameter integer BYTEENA_W = DATA_W / 8, // > 0
parameter integer ID_W = 1 // > 0
)
(
input clock,
input resetn,
acl_arb_intf in_intf,
acl_arb_intf out_intf
);
acl_arb_data #(
.DATA_W( DATA_W ),
.BURSTCOUNT_W( BURSTCOUNT_W ),
.ADDRESS_W( ADDRESS_W ),
.BYTEENA_W( BYTEENA_W ),
.ID_W( ID_W )
)
pipe_r();
// Pipeline register.
always @( posedge clock or negedge resetn )
if( !resetn )
begin
pipe_r.req <= 'x; // only signals reset explicitly below need to be reset at all
pipe_r.req.request <= 1'b0;
pipe_r.req.read <= 1'b0;
pipe_r.req.write <= 1'b0;
end
else if( !(out_intf.stall & pipe_r.req.request) )
pipe_r.req <= in_intf.req;
// Request for downstream blocks.
assign out_intf.req = pipe_r.req;
// Upstream stall signal.
assign in_intf.stall = out_intf.stall & pipe_r.req.request;
endmodule
module acl_arb_staging_reg #(
parameter integer DATA_W = 32, // > 0
parameter integer BURSTCOUNT_W = 4, // > 0
parameter integer ADDRESS_W = 32, // > 0
parameter integer BYTEENA_W = DATA_W / 8, // > 0
parameter integer ID_W = 1 // > 0
)
(
input clock,
input resetn,
acl_arb_intf in_intf,
acl_arb_intf out_intf
);
logic stall_r;
acl_arb_data #(
.DATA_W( DATA_W ),
.BURSTCOUNT_W( BURSTCOUNT_W ),
.ADDRESS_W( ADDRESS_W ),
.BYTEENA_W( BYTEENA_W ),
.ID_W( ID_W )
)
staging_r();
// Staging register.
always @( posedge clock or negedge resetn )
if( !resetn )
begin
staging_r.req <= 'x; // only signals reset explicitly below need to be reset at all
staging_r.req.request <= 1'b0;
staging_r.req.read <= 1'b0;
staging_r.req.write <= 1'b0;
end
else if( !stall_r )
staging_r.req <= in_intf.req;
// Stall register.
always @( posedge clock or negedge resetn )
if( !resetn )
stall_r <= 1'b0;
else
stall_r <= out_intf.stall & (stall_r | in_intf.req.request);
// Request for downstream blocks.
assign out_intf.req = stall_r ? staging_r.req : in_intf.req;
// Upstream stall signal.
assign in_intf.stall = stall_r;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:54:16 03/16/2014
// Design Name:
// Module Name: Core
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Core(
input clk,
input nrst,
output instr,
output IFID_instr,
output IDEX_instr,
output EXMEM_instr,
output MEMWB_instr,
//output reg[31:0] iaddr,
output daddr,
output dout,
output MEMWB_dout,
output wr,
output EXMEM_wr,
output pc,
output IFID_pc,
output IDEX_pc,
output EXMEM_pc,
output reg_din,
output reg_raddr1,
output reg_dout1,
output IDEX_reg_dout1,
output reg_raddr2,
output reg_dout2,
output IDEX_reg_dout2,
output EXMEM_reg_dout2,
output wr_reg,
output EXMEM_wr_reg,
output MEMWB_wr_reg,
output reg_wr_addr,
output ALUOut,
output EXMEM_ALUOut,
output MEMWB_ALUOut,
output ALUOp,
output ALUSrc,
output ALUIn2,
output MemToReg,
output EXMEM_MemToReg,
output MEMWB_MemToReg,
output RegDst,
output EXMEM_RegDst,
output MEMWB_RegDst,
output PCSrc,
output wire[31:0] ram1,
output wire[31:0] ram2,
output wire[31:0] ram3,
output Zero,
output Branch,
output Jump
);
wire[31:0] instr;
reg[31:0] IFID_instr;
reg[31:0] IDEX_instr;
reg[31:0] EXMEM_instr;
reg[31:0] MEMWB_instr;
reg[5:0] daddr;
wire[31:0] dout;
reg[31:0] MEMWB_dout;
reg[3:0] wr;
reg[3:0] EXMEM_wr;
reg[31:0] pc;
reg[31:0] IFID_pc;
reg[31:0] IDEX_pc;
reg[31:0] EXMEM_pc;
wire[31:0] reg_din;
reg[4:0] reg_raddr1;
wire[31:0] reg_dout1;
reg[31:0] IDEX_reg_dout1;
reg[4:0] reg_raddr2;
wire[31:0] reg_dout2;
reg[31:0] IDEX_reg_dout2;
reg[31:0] EXMEM_reg_dout2;
reg wr_reg;
reg EXMEM_wr_reg;
reg MEMWB_wr_reg;
reg[4:0] reg_wr_addr;
reg[31:0] ALUOut;
reg[31:0] EXMEM_ALUOut;
reg[31:0] MEMWB_ALUOut;
reg[3:0] ALUOp;
reg ALUSrc;
reg[31:0] ALUIn2;
reg MemToReg;
reg EXMEM_MemToReg;
reg MEMWB_MemToReg;
reg RegDst;
reg EXMEM_RegDst;
reg MEMWB_RegDst;
reg PCSrc;
reg Zero;
reg Branch;
reg Jump;
//Wires & Regs definitions
//wire[31:0] instr; ->moved to module inputs for debug purposes
//reg[31:0] ALUOut;
//reg[3:0] ALUOp;
//reg ALUSrc;
reg Carry;
//reg RegDst;
//reg MemToReg;
//reg[31:0] ALUIn2;
wire[7:0] din[0:3];
//reg[7:0] pc = 8'b00000000;
//reg[31:0] immediate_extended;
reg[31:0] next_pc;
reg[31:0] j_pc;
reg[31:0] shifted_pc;
reg[4:0] shamt;
/*
reg[4:0] reg_raddr1;
wire[31:0] reg_dout1;
reg[4:0] reg_raddr2;
wire[31:0] reg_dout2;
wire wr_reg;
reg[4:0] reg_wr_addr;
reg[31:0] reg_din;
moved to module outputs for debug purposes
*/
wire nclk;
assign nclk = !(clk);
regfile registers(
clk,
reg_raddr1,
reg_dout1,
reg_raddr2,
reg_dout2,
MEMWB_wr_reg,
reg_wr_addr,
reg_din,
ram1,
ram2,
ram3
);
//Memory instantiations
wire[31:0] dina; //not used since we don't write to imem
//wire[31:0] tmp_instr;
wire z;
assign z = 0;
IMem imem (
nclk, // input clka
z, // input [0 : 0] wea
pc[7:2], // input [5 : 0] addra
dina, // input [31 : 0] dina
instr // output [31 : 0] douta
);
DMem dmem_0 (
nclk, // input clka
EXMEM_wr[0], // input [0 : 0] wea
daddr[5:0], // input [5 : 0] addra
EXMEM_reg_dout2[7:0], // input [7 : 0] dina
dout[7:0] // output [7 : 0] douta
);
DMem dmem_1 (
nclk, // input clka
EXMEM_wr[1], // input [0 : 0] wea
daddr[5:0], // input [5 : 0] addra
EXMEM_reg_dout2[15:8], // input [7 : 0] dina
dout[15:8] // output [7 : 0] douta
);
DMem dmem_2 (
nclk, // input clka
EXMEM_wr[2], // input [0 : 0] wea
daddr[5:0], // input [5 : 0] addra
EXMEM_reg_dout2[23:16], // input [7 : 0] dina
dout[23:16] // output [7 : 0] douta
);
DMem dmem_3 (
nclk, // input clka
EXMEM_wr[3], // input [0 : 0] wea
daddr[5:0], // input [5 : 0] addra
EXMEM_reg_dout2[31:24], // input [7 : 0] dina
dout[31:24] // output [7 : 0] douta
);
reg[31:0] JDest;
reg JR;
always @*
begin
//PCSrc Mux & Jump
//4'b0000 because our memory real pc is 8 bits and 4 MSBs are always 0 in our case
JDest <= JR ? (reg_dout1 << 2) : {4'b0000, instr[25:0], 2'b00};
j_pc <= Jump ? JDest : pc + 32'b100;
shifted_pc <= (({{16{instr[15]}}, instr[15:0]}) << 2) + (pc + 32'b100);
PCSrc <= Branch & Zero;
next_pc <= PCSrc ? shifted_pc : j_pc;
//RegDst Mux
reg_wr_addr <= MEMWB_RegDst ? MEMWB_instr[15:11] : MEMWB_instr[20:16];
reg_raddr1 <= IFID_instr[25:21];
reg_raddr2 <= IFID_instr[20:16];
//ALUSrc Mux
ALUIn2 <= ALUSrc ? {{16{IDEX_instr[15]}}, IDEX_instr[15:0]} : IDEX_reg_dout2; //sign extended
end
//MemToReg Mux
assign reg_din = MEMWB_MemToReg ? MEMWB_dout : MEMWB_ALUOut;
//PC
always @(posedge clk)
begin
if (~nrst)
begin
pc = 32'b0;
Branch <= 0;
Jump <= 0;
//ALUOut <= 32'b0;
end
else
begin
pc = next_pc;
end
end
//Decode
always @(posedge clk)
begin
if (IFID_instr[31:26] == 6'b001000)
ALUOp = 4'b0000;
case (IDEX_instr[31:26])
6'b000000 :
begin
//func
case (IFID_instr[10:0])
11'b00000100000 : //Add
begin
ALUOp = 4'b0000;
end
11'b00000100100 : //And
begin
ALUOp = 4'b0001;
end
11'b00000100101: // OR
begin
ALUOp = 4'b0010;
end
11'b00000100110: // XOR
begin
ALUOp = 4'b0111;
end
11'b00000011010, 11'b00000011011 : // Div, Divu
begin
ALUOp = 4'b0101;
end
11'b00000011000, 11'b00000011001 : // Mult, Multu
begin
ALUOp = 4'b0110;
end
default :
begin
/*case(IFID_instr[5:0])
6'b000000 : //SLL
begin
ALUOp = 4'b0011;
end
endcase*/
end
endcase
end
6'b001101 : //ORI
ALUOp = 4'b0010;
6'b001110 : //XORI
ALUOp = 4'b0111;
6'b001100 : //ANDI
ALUOp = 4'b0000;
6'b001000 , 6'b001001 :
ALUOp = 4'b0000; // ADDI
6'b00100, 6'b000001, 6'b000111, 6'b000110, 6'b000001, 6'b000101 : // BEQ, BGEZ, BGEZAL, BGTZ, BLEZ, BLTZ, BLTZAL, BNE
ALUOp = 4'b0100; // (uses Sub)
6'b100000 : // LB
ALUOp = 4'b0000;
6'b001111 : // LUI
ALUOp = 4'b0000;
6'b100011 : // LW
ALUOp = 4'b0000;
6'b101000 : // SB
ALUOp = 4'b0000;
6'b101011 : // SW
ALUOp = 4'b0000;
/*6'b000011 : //JAL (Save ret addr in $31) Needs Fix
begin
//reg_din <= pc + 3'b100;
//reg_wr_addr = 5'b11111;
wr_reg <= 1;
end*/
default :
//6'b000010 : // Jump
//Nothing (we don't need the alu)
;
endcase
end
//Control
always @(posedge clk)
begin
if (IFID_instr == 32'b0) //NOP
begin
wr_reg <= 0;
wr <= 4'b0000;
Branch <= 0;
Jump <= 0;
Branch <= 0;
end
else
begin
case (IFID_instr[31:26])
6'b000000 :
begin
//func
case (IFID_instr[10:0])
11'b00000100000, 11'b00000100001, 11'b00000100010, 00000100011, 11'b00000100100, 11'b00000100101, 11'b00000100110 : //Add, Addu, Sub, Subu , And, Or, XOR
/*(Note: ALL arithmetic immediate values are sign-extended. After that, they are handled as
signed or unsigned 32 bit numbers, depending upon the instruction. The only difference between
signed and unsigned instructions is that signed instructions can generate an overflow exception
and unsigned instructions can not. )
*/
begin
RegDst <= 1;
ALUSrc <= 0;
//reg_raddr1 <= instr[25:21];
//reg_raddr2 <= instr[20:16];
//reg_wr_addr <<= instr[15:11];
wr_reg <= 1;
MemToReg <= 0;
Branch <= 0;
Jump <= 0;
end
11'b00000000000 : //???????????????
case(IFID_instr[5:0])
6'b000000 : //SLL
begin
RegDst <= 1;
ALUSrc <= 0;
wr_reg <= 1;
MemToReg <= 0;
Branch <= 0;
Jump <= 0;
shamt <= IDEX_instr[10:6];
end
endcase
11'b00000001000 : //JR
if (IFID_instr[20:0] == 21'b1000)
begin
reg_raddr1 <= instr[25:21];
wr_reg <= 0;
wr <= 4'b0000;
Branch <= 0;
Jump <= 1;
//JR <= 1;
end
default:
;
endcase
end
6'b001000, 6'b001001, 6'b001100, 6'b001101, 6'b001101 : //Addi, Addiu, Andi, Ori, Xori
begin
RegDst <= 0;
ALUSrc <= 1; //immediate
//reg_wr_addr <= instr[20:16];
wr_reg <= 1;
MemToReg <= 0;
Branch <= 0;
Jump <= 0;
end
//======================= MEMORY ==========================
6'b100000 : // LB
begin
RegDst <= 0;
ALUSrc <= 1; // immediate
wr[0] <= 0;
wr[1] <= 0;
wr[2] <= 0;
wr[3] <= 0;
//daddr[5:0] <= ALUOut[5:0];
//reg_wr_addr <= instr[20:16];
wr_reg <= 1;
MemToReg <= 1;
PCSrc <= 0;
Branch <= 0;
Jump <= 0;
end
6'b100011 : // LW
begin
RegDst <= 0;
ALUSrc <= 1; //if i=2
wr[0] <= 0;
wr[1] <= 0;
wr[2] <= 0;
wr[3] <= 0;
//daddr[5:0] <= ALUOut[5:0];
//reg_wr_addr <= instr[20:16];
wr_reg <= 1;
MemToReg <= 1;
PCSrc <= 0;
Branch <= 0;
Jump <= 0;
end
6'b101000 : // SB
begin
ALUSrc <= 1; // immediate
wr[0] <= 1;
wr[1] <= 0;
wr[2] <= 0;
wr[3] <= 0;
reg_raddr2 <= IFID_instr[20:16];
wr_reg <= 0;
MemToReg <= 0;
PCSrc <= 0;
Branch <= 0;
Jump <= 0;
end
6'b101011 : // SW
begin
ALUSrc <= 1; // immediate
wr[0] <= 1;
wr[1] <= 1;
wr[2] <= 1;
wr[3] <= 1;
reg_raddr2 <= IFID_instr[20:16];
wr_reg <= 0;
MemToReg <= 0;
PCSrc <= 0;
Branch <= 0;
Jump <= 0;
end
6'b000010 : // Jump
begin
wr_reg <= 0;
wr <= 4'b0000;
Branch <= 0;
Jump <= 1;
JR <= 0;
end
/*6'b000011 : // JAL
begin
wr_reg <= 0;
wr <= 4'b0000;
Branch <= 0;
Jump <= 1;
JR <= 0;
end*/
default :
;
endcase
end
end
//Pipeline
always @(posedge clk)
begin
if (nrst)
begin
MEMWB_instr <= EXMEM_instr;
EXMEM_instr <= IDEX_instr;
IDEX_instr <= IFID_instr;
IFID_instr <= instr;
EXMEM_pc <= IDEX_pc;
IDEX_pc <= IFID_pc;
IFID_pc <= pc;
MEMWB_ALUOut <= EXMEM_ALUOut;
EXMEM_ALUOut <= ALUOut;
IDEX_reg_dout1 <= reg_dout1;
EXMEM_reg_dout2 <= IDEX_reg_dout2;
IDEX_reg_dout2 <= reg_dout2;
MEMWB_wr_reg <= EXMEM_wr_reg;
EXMEM_wr_reg <= wr_reg;
MEMWB_MemToReg <= EXMEM_MemToReg;
EXMEM_MemToReg <= MemToReg;
MEMWB_RegDst <= EXMEM_RegDst;
EXMEM_RegDst <= RegDst;
daddr[5:0] <= ALUOut[5:0];
MEMWB_dout <= dout;
EXMEM_wr <= wr;
end
end
//ALU
//reg[32:0] tmp; //used in add, to compute carry
always @(*)
begin
/*
0000 : add/i/ui/u
0001 : and/i
0010 : or
0011 : sll
0100 : Sub/u
0101 : Div
0110 : Mult
0111 : xor/i
: sllv
: sra
: srl
: srlv
*/
case (ALUOp)
4'b0000 : //Add
begin
ALUOut <= ALUIn2 + IDEX_reg_dout1;
//tmp <= ALUIn2 + reg_dout1;
//ALUOut <= tmp[31:0];
//Carry = tmp[32];
//Set Carry flag if signed!
end
4'b0001 : //And
begin
ALUOut <= IDEX_reg_dout1 & ALUIn2;
end
4'b0010 : // OR
begin
ALUOut <= IDEX_reg_dout1 | ALUIn2;
end
4'b0011 : // SLL
begin
ALUOut <= ALUIn2 << shamt;
end
4'b0100 : // Sub
begin
ALUOut <= IDEX_reg_dout1 - ALUIn2;
Zero <= (ALUOut == 32'b0) ? 1 : 0;
end
/*4'b0101 : // Div, Divu
begin
HI <= reg_dout1 / ALUIn2;
LO <= reg_dout1 % ALUIn2;
end*/
/*4'b0110 : // Mult, Multu
begin
{HI, LO} <= reg_dout1 * ALUIn2;
end*/
4'b0111 : // Xor, Xori
begin
ALUOut <= IDEX_reg_dout1 ^ ALUIn2;
end
default :
;
endcase
end
endmodule
|
//
// by teak gui
//
// Generated on: Sat Nov 9 11:29:49 GMT 2013
//
`timescale 1ns/1ps
// tko31m32_1nm1b0_2apt1o0w1bi0w31b TeakO [
// (1,TeakOConstant 1 0),
// (2,TeakOAppend 1 [(1,0+:1),(0,0+:31)])] [One 31,One 32]
module tko31m32_1nm1b0_2apt1o0w1bi0w31b (i_0r0, i_0r1, i_0a, o_0r0, o_0r1, o_0a, reset);
input [30:0] i_0r0;
input [30:0] i_0r1;
output i_0a;
output [31:0] o_0r0;
output [31:0] o_0r1;
input o_0a;
input reset;
wire go_0;
wire [30:0] gocomp_0;
wire [10:0] simp331_0;
wire [3:0] simp332_0;
wire [1:0] simp333_0;
wire termf_1;
wire termt_1;
OR2 I0 (gocomp_0[0:0], i_0r0[0:0], i_0r1[0:0]);
OR2 I1 (gocomp_0[1:1], i_0r0[1:1], i_0r1[1:1]);
OR2 I2 (gocomp_0[2:2], i_0r0[2:2], i_0r1[2:2]);
OR2 I3 (gocomp_0[3:3], i_0r0[3:3], i_0r1[3:3]);
OR2 I4 (gocomp_0[4:4], i_0r0[4:4], i_0r1[4:4]);
OR2 I5 (gocomp_0[5:5], i_0r0[5:5], i_0r1[5:5]);
OR2 I6 (gocomp_0[6:6], i_0r0[6:6], i_0r1[6:6]);
OR2 I7 (gocomp_0[7:7], i_0r0[7:7], i_0r1[7:7]);
OR2 I8 (gocomp_0[8:8], i_0r0[8:8], i_0r1[8:8]);
OR2 I9 (gocomp_0[9:9], i_0r0[9:9], i_0r1[9:9]);
OR2 I10 (gocomp_0[10:10], i_0r0[10:10], i_0r1[10:10]);
OR2 I11 (gocomp_0[11:11], i_0r0[11:11], i_0r1[11:11]);
OR2 I12 (gocomp_0[12:12], i_0r0[12:12], i_0r1[12:12]);
OR2 I13 (gocomp_0[13:13], i_0r0[13:13], i_0r1[13:13]);
OR2 I14 (gocomp_0[14:14], i_0r0[14:14], i_0r1[14:14]);
OR2 I15 (gocomp_0[15:15], i_0r0[15:15], i_0r1[15:15]);
OR2 I16 (gocomp_0[16:16], i_0r0[16:16], i_0r1[16:16]);
OR2 I17 (gocomp_0[17:17], i_0r0[17:17], i_0r1[17:17]);
OR2 I18 (gocomp_0[18:18], i_0r0[18:18], i_0r1[18:18]);
OR2 I19 (gocomp_0[19:19], i_0r0[19:19], i_0r1[19:19]);
OR2 I20 (gocomp_0[20:20], i_0r0[20:20], i_0r1[20:20]);
OR2 I21 (gocomp_0[21:21], i_0r0[21:21], i_0r1[21:21]);
OR2 I22 (gocomp_0[22:22], i_0r0[22:22], i_0r1[22:22]);
OR2 I23 (gocomp_0[23:23], i_0r0[23:23], i_0r1[23:23]);
OR2 I24 (gocomp_0[24:24], i_0r0[24:24], i_0r1[24:24]);
OR2 I25 (gocomp_0[25:25], i_0r0[25:25], i_0r1[25:25]);
OR2 I26 (gocomp_0[26:26], i_0r0[26:26], i_0r1[26:26]);
OR2 I27 (gocomp_0[27:27], i_0r0[27:27], i_0r1[27:27]);
OR2 I28 (gocomp_0[28:28], i_0r0[28:28], i_0r1[28:28]);
OR2 I29 (gocomp_0[29:29], i_0r0[29:29], i_0r1[29:29]);
OR2 I30 (gocomp_0[30:30], i_0r0[30:30], i_0r1[30:30]);
C3 I31 (simp331_0[0:0], gocomp_0[0:0], gocomp_0[1:1], gocomp_0[2:2]);
C3 I32 (simp331_0[1:1], gocomp_0[3:3], gocomp_0[4:4], gocomp_0[5:5]);
C3 I33 (simp331_0[2:2], gocomp_0[6:6], gocomp_0[7:7], gocomp_0[8:8]);
C3 I34 (simp331_0[3:3], gocomp_0[9:9], gocomp_0[10:10], gocomp_0[11:11]);
C3 I35 (simp331_0[4:4], gocomp_0[12:12], gocomp_0[13:13], gocomp_0[14:14]);
C3 I36 (simp331_0[5:5], gocomp_0[15:15], gocomp_0[16:16], gocomp_0[17:17]);
C3 I37 (simp331_0[6:6], gocomp_0[18:18], gocomp_0[19:19], gocomp_0[20:20]);
C3 I38 (simp331_0[7:7], gocomp_0[21:21], gocomp_0[22:22], gocomp_0[23:23]);
C3 I39 (simp331_0[8:8], gocomp_0[24:24], gocomp_0[25:25], gocomp_0[26:26]);
C3 I40 (simp331_0[9:9], gocomp_0[27:27], gocomp_0[28:28], gocomp_0[29:29]);
BUFF I41 (simp331_0[10:10], gocomp_0[30:30]);
C3 I42 (simp332_0[0:0], simp331_0[0:0], simp331_0[1:1], simp331_0[2:2]);
C3 I43 (simp332_0[1:1], simp331_0[3:3], simp331_0[4:4], simp331_0[5:5]);
C3 I44 (simp332_0[2:2], simp331_0[6:6], simp331_0[7:7], simp331_0[8:8]);
C2 I45 (simp332_0[3:3], simp331_0[9:9], simp331_0[10:10]);
C3 I46 (simp333_0[0:0], simp332_0[0:0], simp332_0[1:1], simp332_0[2:2]);
BUFF I47 (simp333_0[1:1], simp332_0[3:3]);
C2 I48 (go_0, simp333_0[0:0], simp333_0[1:1]);
BUFF I49 (termf_1, go_0);
GND I50 (termt_1);
BUFF I51 (o_0r0[0:0], termf_1);
BUFF I52 (o_0r0[1:1], i_0r0[0:0]);
BUFF I53 (o_0r0[2:2], i_0r0[1:1]);
BUFF I54 (o_0r0[3:3], i_0r0[2:2]);
BUFF I55 (o_0r0[4:4], i_0r0[3:3]);
BUFF I56 (o_0r0[5:5], i_0r0[4:4]);
BUFF I57 (o_0r0[6:6], i_0r0[5:5]);
BUFF I58 (o_0r0[7:7], i_0r0[6:6]);
BUFF I59 (o_0r0[8:8], i_0r0[7:7]);
BUFF I60 (o_0r0[9:9], i_0r0[8:8]);
BUFF I61 (o_0r0[10:10], i_0r0[9:9]);
BUFF I62 (o_0r0[11:11], i_0r0[10:10]);
BUFF I63 (o_0r0[12:12], i_0r0[11:11]);
BUFF I64 (o_0r0[13:13], i_0r0[12:12]);
BUFF I65 (o_0r0[14:14], i_0r0[13:13]);
BUFF I66 (o_0r0[15:15], i_0r0[14:14]);
BUFF I67 (o_0r0[16:16], i_0r0[15:15]);
BUFF I68 (o_0r0[17:17], i_0r0[16:16]);
BUFF I69 (o_0r0[18:18], i_0r0[17:17]);
BUFF I70 (o_0r0[19:19], i_0r0[18:18]);
BUFF I71 (o_0r0[20:20], i_0r0[19:19]);
BUFF I72 (o_0r0[21:21], i_0r0[20:20]);
BUFF I73 (o_0r0[22:22], i_0r0[21:21]);
BUFF I74 (o_0r0[23:23], i_0r0[22:22]);
BUFF I75 (o_0r0[24:24], i_0r0[23:23]);
BUFF I76 (o_0r0[25:25], i_0r0[24:24]);
BUFF I77 (o_0r0[26:26], i_0r0[25:25]);
BUFF I78 (o_0r0[27:27], i_0r0[26:26]);
BUFF I79 (o_0r0[28:28], i_0r0[27:27]);
BUFF I80 (o_0r0[29:29], i_0r0[28:28]);
BUFF I81 (o_0r0[30:30], i_0r0[29:29]);
BUFF I82 (o_0r0[31:31], i_0r0[30:30]);
BUFF I83 (o_0r1[0:0], termt_1);
BUFF I84 (o_0r1[1:1], i_0r1[0:0]);
BUFF I85 (o_0r1[2:2], i_0r1[1:1]);
BUFF I86 (o_0r1[3:3], i_0r1[2:2]);
BUFF I87 (o_0r1[4:4], i_0r1[3:3]);
BUFF I88 (o_0r1[5:5], i_0r1[4:4]);
BUFF I89 (o_0r1[6:6], i_0r1[5:5]);
BUFF I90 (o_0r1[7:7], i_0r1[6:6]);
BUFF I91 (o_0r1[8:8], i_0r1[7:7]);
BUFF I92 (o_0r1[9:9], i_0r1[8:8]);
BUFF I93 (o_0r1[10:10], i_0r1[9:9]);
BUFF I94 (o_0r1[11:11], i_0r1[10:10]);
BUFF I95 (o_0r1[12:12], i_0r1[11:11]);
BUFF I96 (o_0r1[13:13], i_0r1[12:12]);
BUFF I97 (o_0r1[14:14], i_0r1[13:13]);
BUFF I98 (o_0r1[15:15], i_0r1[14:14]);
BUFF I99 (o_0r1[16:16], i_0r1[15:15]);
BUFF I100 (o_0r1[17:17], i_0r1[16:16]);
BUFF I101 (o_0r1[18:18], i_0r1[17:17]);
BUFF I102 (o_0r1[19:19], i_0r1[18:18]);
BUFF I103 (o_0r1[20:20], i_0r1[19:19]);
BUFF I104 (o_0r1[21:21], i_0r1[20:20]);
BUFF I105 (o_0r1[22:22], i_0r1[21:21]);
BUFF I106 (o_0r1[23:23], i_0r1[22:22]);
BUFF I107 (o_0r1[24:24], i_0r1[23:23]);
BUFF I108 (o_0r1[25:25], i_0r1[24:24]);
BUFF I109 (o_0r1[26:26], i_0r1[25:25]);
BUFF I110 (o_0r1[27:27], i_0r1[26:26]);
BUFF I111 (o_0r1[28:28], i_0r1[27:27]);
BUFF I112 (o_0r1[29:29], i_0r1[28:28]);
BUFF I113 (o_0r1[30:30], i_0r1[29:29]);
BUFF I114 (o_0r1[31:31], i_0r1[30:30]);
BUFF I115 (i_0a, o_0a);
endmodule
// tko31m32_1nm1b0_2api0w31bt1o0w1b TeakO [
// (1,TeakOConstant 1 0),
// (2,TeakOAppend 1 [(0,0+:31),(1,0+:1)])] [One 31,One 32]
module tko31m32_1nm1b0_2api0w31bt1o0w1b (i_0r0, i_0r1, i_0a, o_0r0, o_0r1, o_0a, reset);
input [30:0] i_0r0;
input [30:0] i_0r1;
output i_0a;
output [31:0] o_0r0;
output [31:0] o_0r1;
input o_0a;
input reset;
wire go_0;
wire [30:0] gocomp_0;
wire [10:0] simp331_0;
wire [3:0] simp332_0;
wire [1:0] simp333_0;
wire termf_1;
wire termt_1;
OR2 I0 (gocomp_0[0:0], i_0r0[0:0], i_0r1[0:0]);
OR2 I1 (gocomp_0[1:1], i_0r0[1:1], i_0r1[1:1]);
OR2 I2 (gocomp_0[2:2], i_0r0[2:2], i_0r1[2:2]);
OR2 I3 (gocomp_0[3:3], i_0r0[3:3], i_0r1[3:3]);
OR2 I4 (gocomp_0[4:4], i_0r0[4:4], i_0r1[4:4]);
OR2 I5 (gocomp_0[5:5], i_0r0[5:5], i_0r1[5:5]);
OR2 I6 (gocomp_0[6:6], i_0r0[6:6], i_0r1[6:6]);
OR2 I7 (gocomp_0[7:7], i_0r0[7:7], i_0r1[7:7]);
OR2 I8 (gocomp_0[8:8], i_0r0[8:8], i_0r1[8:8]);
OR2 I9 (gocomp_0[9:9], i_0r0[9:9], i_0r1[9:9]);
OR2 I10 (gocomp_0[10:10], i_0r0[10:10], i_0r1[10:10]);
OR2 I11 (gocomp_0[11:11], i_0r0[11:11], i_0r1[11:11]);
OR2 I12 (gocomp_0[12:12], i_0r0[12:12], i_0r1[12:12]);
OR2 I13 (gocomp_0[13:13], i_0r0[13:13], i_0r1[13:13]);
OR2 I14 (gocomp_0[14:14], i_0r0[14:14], i_0r1[14:14]);
OR2 I15 (gocomp_0[15:15], i_0r0[15:15], i_0r1[15:15]);
OR2 I16 (gocomp_0[16:16], i_0r0[16:16], i_0r1[16:16]);
OR2 I17 (gocomp_0[17:17], i_0r0[17:17], i_0r1[17:17]);
OR2 I18 (gocomp_0[18:18], i_0r0[18:18], i_0r1[18:18]);
OR2 I19 (gocomp_0[19:19], i_0r0[19:19], i_0r1[19:19]);
OR2 I20 (gocomp_0[20:20], i_0r0[20:20], i_0r1[20:20]);
OR2 I21 (gocomp_0[21:21], i_0r0[21:21], i_0r1[21:21]);
OR2 I22 (gocomp_0[22:22], i_0r0[22:22], i_0r1[22:22]);
OR2 I23 (gocomp_0[23:23], i_0r0[23:23], i_0r1[23:23]);
OR2 I24 (gocomp_0[24:24], i_0r0[24:24], i_0r1[24:24]);
OR2 I25 (gocomp_0[25:25], i_0r0[25:25], i_0r1[25:25]);
OR2 I26 (gocomp_0[26:26], i_0r0[26:26], i_0r1[26:26]);
OR2 I27 (gocomp_0[27:27], i_0r0[27:27], i_0r1[27:27]);
OR2 I28 (gocomp_0[28:28], i_0r0[28:28], i_0r1[28:28]);
OR2 I29 (gocomp_0[29:29], i_0r0[29:29], i_0r1[29:29]);
OR2 I30 (gocomp_0[30:30], i_0r0[30:30], i_0r1[30:30]);
C3 I31 (simp331_0[0:0], gocomp_0[0:0], gocomp_0[1:1], gocomp_0[2:2]);
C3 I32 (simp331_0[1:1], gocomp_0[3:3], gocomp_0[4:4], gocomp_0[5:5]);
C3 I33 (simp331_0[2:2], gocomp_0[6:6], gocomp_0[7:7], gocomp_0[8:8]);
C3 I34 (simp331_0[3:3], gocomp_0[9:9], gocomp_0[10:10], gocomp_0[11:11]);
C3 I35 (simp331_0[4:4], gocomp_0[12:12], gocomp_0[13:13], gocomp_0[14:14]);
C3 I36 (simp331_0[5:5], gocomp_0[15:15], gocomp_0[16:16], gocomp_0[17:17]);
C3 I37 (simp331_0[6:6], gocomp_0[18:18], gocomp_0[19:19], gocomp_0[20:20]);
C3 I38 (simp331_0[7:7], gocomp_0[21:21], gocomp_0[22:22], gocomp_0[23:23]);
C3 I39 (simp331_0[8:8], gocomp_0[24:24], gocomp_0[25:25], gocomp_0[26:26]);
C3 I40 (simp331_0[9:9], gocomp_0[27:27], gocomp_0[28:28], gocomp_0[29:29]);
BUFF I41 (simp331_0[10:10], gocomp_0[30:30]);
C3 I42 (simp332_0[0:0], simp331_0[0:0], simp331_0[1:1], simp331_0[2:2]);
C3 I43 (simp332_0[1:1], simp331_0[3:3], simp331_0[4:4], simp331_0[5:5]);
C3 I44 (simp332_0[2:2], simp331_0[6:6], simp331_0[7:7], simp331_0[8:8]);
C2 I45 (simp332_0[3:3], simp331_0[9:9], simp331_0[10:10]);
C3 I46 (simp333_0[0:0], simp332_0[0:0], simp332_0[1:1], simp332_0[2:2]);
BUFF I47 (simp333_0[1:1], simp332_0[3:3]);
C2 I48 (go_0, simp333_0[0:0], simp333_0[1:1]);
BUFF I49 (termf_1, go_0);
GND I50 (termt_1);
BUFF I51 (o_0r0[0:0], i_0r0[0:0]);
BUFF I52 (o_0r0[1:1], i_0r0[1:1]);
BUFF I53 (o_0r0[2:2], i_0r0[2:2]);
BUFF I54 (o_0r0[3:3], i_0r0[3:3]);
BUFF I55 (o_0r0[4:4], i_0r0[4:4]);
BUFF I56 (o_0r0[5:5], i_0r0[5:5]);
BUFF I57 (o_0r0[6:6], i_0r0[6:6]);
BUFF I58 (o_0r0[7:7], i_0r0[7:7]);
BUFF I59 (o_0r0[8:8], i_0r0[8:8]);
BUFF I60 (o_0r0[9:9], i_0r0[9:9]);
BUFF I61 (o_0r0[10:10], i_0r0[10:10]);
BUFF I62 (o_0r0[11:11], i_0r0[11:11]);
BUFF I63 (o_0r0[12:12], i_0r0[12:12]);
BUFF I64 (o_0r0[13:13], i_0r0[13:13]);
BUFF I65 (o_0r0[14:14], i_0r0[14:14]);
BUFF I66 (o_0r0[15:15], i_0r0[15:15]);
BUFF I67 (o_0r0[16:16], i_0r0[16:16]);
BUFF I68 (o_0r0[17:17], i_0r0[17:17]);
BUFF I69 (o_0r0[18:18], i_0r0[18:18]);
BUFF I70 (o_0r0[19:19], i_0r0[19:19]);
BUFF I71 (o_0r0[20:20], i_0r0[20:20]);
BUFF I72 (o_0r0[21:21], i_0r0[21:21]);
BUFF I73 (o_0r0[22:22], i_0r0[22:22]);
BUFF I74 (o_0r0[23:23], i_0r0[23:23]);
BUFF I75 (o_0r0[24:24], i_0r0[24:24]);
BUFF I76 (o_0r0[25:25], i_0r0[25:25]);
BUFF I77 (o_0r0[26:26], i_0r0[26:26]);
BUFF I78 (o_0r0[27:27], i_0r0[27:27]);
BUFF I79 (o_0r0[28:28], i_0r0[28:28]);
BUFF I80 (o_0r0[29:29], i_0r0[29:29]);
BUFF I81 (o_0r0[30:30], i_0r0[30:30]);
BUFF I82 (o_0r0[31:31], termf_1);
BUFF I83 (o_0r1[0:0], i_0r1[0:0]);
BUFF I84 (o_0r1[1:1], i_0r1[1:1]);
BUFF I85 (o_0r1[2:2], i_0r1[2:2]);
BUFF I86 (o_0r1[3:3], i_0r1[3:3]);
BUFF I87 (o_0r1[4:4], i_0r1[4:4]);
BUFF I88 (o_0r1[5:5], i_0r1[5:5]);
BUFF I89 (o_0r1[6:6], i_0r1[6:6]);
BUFF I90 (o_0r1[7:7], i_0r1[7:7]);
BUFF I91 (o_0r1[8:8], i_0r1[8:8]);
BUFF I92 (o_0r1[9:9], i_0r1[9:9]);
BUFF I93 (o_0r1[10:10], i_0r1[10:10]);
BUFF I94 (o_0r1[11:11], i_0r1[11:11]);
BUFF I95 (o_0r1[12:12], i_0r1[12:12]);
BUFF I96 (o_0r1[13:13], i_0r1[13:13]);
BUFF I97 (o_0r1[14:14], i_0r1[14:14]);
BUFF I98 (o_0r1[15:15], i_0r1[15:15]);
BUFF I99 (o_0r1[16:16], i_0r1[16:16]);
BUFF I100 (o_0r1[17:17], i_0r1[17:17]);
BUFF I101 (o_0r1[18:18], i_0r1[18:18]);
BUFF I102 (o_0r1[19:19], i_0r1[19:19]);
BUFF I103 (o_0r1[20:20], i_0r1[20:20]);
BUFF I104 (o_0r1[21:21], i_0r1[21:21]);
BUFF I105 (o_0r1[22:22], i_0r1[22:22]);
BUFF I106 (o_0r1[23:23], i_0r1[23:23]);
BUFF I107 (o_0r1[24:24], i_0r1[24:24]);
BUFF I108 (o_0r1[25:25], i_0r1[25:25]);
BUFF I109 (o_0r1[26:26], i_0r1[26:26]);
BUFF I110 (o_0r1[27:27], i_0r1[27:27]);
BUFF I111 (o_0r1[28:28], i_0r1[28:28]);
BUFF I112 (o_0r1[29:29], i_0r1[29:29]);
BUFF I113 (o_0r1[30:30], i_0r1[30:30]);
BUFF I114 (o_0r1[31:31], termt_1);
BUFF I115 (i_0a, o_0a);
endmodule
// tko31m32_1nm1b1_2api0w31bt1o0w1b TeakO [
// (1,TeakOConstant 1 1),
// (2,TeakOAppend 1 [(0,0+:31),(1,0+:1)])] [One 31,One 32]
module tko31m32_1nm1b1_2api0w31bt1o0w1b (i_0r0, i_0r1, i_0a, o_0r0, o_0r1, o_0a, reset);
input [30:0] i_0r0;
input [30:0] i_0r1;
output i_0a;
output [31:0] o_0r0;
output [31:0] o_0r1;
input o_0a;
input reset;
wire go_0;
wire [30:0] gocomp_0;
wire [10:0] simp331_0;
wire [3:0] simp332_0;
wire [1:0] simp333_0;
wire termf_1;
wire termt_1;
OR2 I0 (gocomp_0[0:0], i_0r0[0:0], i_0r1[0:0]);
OR2 I1 (gocomp_0[1:1], i_0r0[1:1], i_0r1[1:1]);
OR2 I2 (gocomp_0[2:2], i_0r0[2:2], i_0r1[2:2]);
OR2 I3 (gocomp_0[3:3], i_0r0[3:3], i_0r1[3:3]);
OR2 I4 (gocomp_0[4:4], i_0r0[4:4], i_0r1[4:4]);
OR2 I5 (gocomp_0[5:5], i_0r0[5:5], i_0r1[5:5]);
OR2 I6 (gocomp_0[6:6], i_0r0[6:6], i_0r1[6:6]);
OR2 I7 (gocomp_0[7:7], i_0r0[7:7], i_0r1[7:7]);
OR2 I8 (gocomp_0[8:8], i_0r0[8:8], i_0r1[8:8]);
OR2 I9 (gocomp_0[9:9], i_0r0[9:9], i_0r1[9:9]);
OR2 I10 (gocomp_0[10:10], i_0r0[10:10], i_0r1[10:10]);
OR2 I11 (gocomp_0[11:11], i_0r0[11:11], i_0r1[11:11]);
OR2 I12 (gocomp_0[12:12], i_0r0[12:12], i_0r1[12:12]);
OR2 I13 (gocomp_0[13:13], i_0r0[13:13], i_0r1[13:13]);
OR2 I14 (gocomp_0[14:14], i_0r0[14:14], i_0r1[14:14]);
OR2 I15 (gocomp_0[15:15], i_0r0[15:15], i_0r1[15:15]);
OR2 I16 (gocomp_0[16:16], i_0r0[16:16], i_0r1[16:16]);
OR2 I17 (gocomp_0[17:17], i_0r0[17:17], i_0r1[17:17]);
OR2 I18 (gocomp_0[18:18], i_0r0[18:18], i_0r1[18:18]);
OR2 I19 (gocomp_0[19:19], i_0r0[19:19], i_0r1[19:19]);
OR2 I20 (gocomp_0[20:20], i_0r0[20:20], i_0r1[20:20]);
OR2 I21 (gocomp_0[21:21], i_0r0[21:21], i_0r1[21:21]);
OR2 I22 (gocomp_0[22:22], i_0r0[22:22], i_0r1[22:22]);
OR2 I23 (gocomp_0[23:23], i_0r0[23:23], i_0r1[23:23]);
OR2 I24 (gocomp_0[24:24], i_0r0[24:24], i_0r1[24:24]);
OR2 I25 (gocomp_0[25:25], i_0r0[25:25], i_0r1[25:25]);
OR2 I26 (gocomp_0[26:26], i_0r0[26:26], i_0r1[26:26]);
OR2 I27 (gocomp_0[27:27], i_0r0[27:27], i_0r1[27:27]);
OR2 I28 (gocomp_0[28:28], i_0r0[28:28], i_0r1[28:28]);
OR2 I29 (gocomp_0[29:29], i_0r0[29:29], i_0r1[29:29]);
OR2 I30 (gocomp_0[30:30], i_0r0[30:30], i_0r1[30:30]);
C3 I31 (simp331_0[0:0], gocomp_0[0:0], gocomp_0[1:1], gocomp_0[2:2]);
C3 I32 (simp331_0[1:1], gocomp_0[3:3], gocomp_0[4:4], gocomp_0[5:5]);
C3 I33 (simp331_0[2:2], gocomp_0[6:6], gocomp_0[7:7], gocomp_0[8:8]);
C3 I34 (simp331_0[3:3], gocomp_0[9:9], gocomp_0[10:10], gocomp_0[11:11]);
C3 I35 (simp331_0[4:4], gocomp_0[12:12], gocomp_0[13:13], gocomp_0[14:14]);
C3 I36 (simp331_0[5:5], gocomp_0[15:15], gocomp_0[16:16], gocomp_0[17:17]);
C3 I37 (simp331_0[6:6], gocomp_0[18:18], gocomp_0[19:19], gocomp_0[20:20]);
C3 I38 (simp331_0[7:7], gocomp_0[21:21], gocomp_0[22:22], gocomp_0[23:23]);
C3 I39 (simp331_0[8:8], gocomp_0[24:24], gocomp_0[25:25], gocomp_0[26:26]);
C3 I40 (simp331_0[9:9], gocomp_0[27:27], gocomp_0[28:28], gocomp_0[29:29]);
BUFF I41 (simp331_0[10:10], gocomp_0[30:30]);
C3 I42 (simp332_0[0:0], simp331_0[0:0], simp331_0[1:1], simp331_0[2:2]);
C3 I43 (simp332_0[1:1], simp331_0[3:3], simp331_0[4:4], simp331_0[5:5]);
C3 I44 (simp332_0[2:2], simp331_0[6:6], simp331_0[7:7], simp331_0[8:8]);
C2 I45 (simp332_0[3:3], simp331_0[9:9], simp331_0[10:10]);
C3 I46 (simp333_0[0:0], simp332_0[0:0], simp332_0[1:1], simp332_0[2:2]);
BUFF I47 (simp333_0[1:1], simp332_0[3:3]);
C2 I48 (go_0, simp333_0[0:0], simp333_0[1:1]);
BUFF I49 (termt_1, go_0);
GND I50 (termf_1);
BUFF I51 (o_0r0[0:0], i_0r0[0:0]);
BUFF I52 (o_0r0[1:1], i_0r0[1:1]);
BUFF I53 (o_0r0[2:2], i_0r0[2:2]);
BUFF I54 (o_0r0[3:3], i_0r0[3:3]);
BUFF I55 (o_0r0[4:4], i_0r0[4:4]);
BUFF I56 (o_0r0[5:5], i_0r0[5:5]);
BUFF I57 (o_0r0[6:6], i_0r0[6:6]);
BUFF I58 (o_0r0[7:7], i_0r0[7:7]);
BUFF I59 (o_0r0[8:8], i_0r0[8:8]);
BUFF I60 (o_0r0[9:9], i_0r0[9:9]);
BUFF I61 (o_0r0[10:10], i_0r0[10:10]);
BUFF I62 (o_0r0[11:11], i_0r0[11:11]);
BUFF I63 (o_0r0[12:12], i_0r0[12:12]);
BUFF I64 (o_0r0[13:13], i_0r0[13:13]);
BUFF I65 (o_0r0[14:14], i_0r0[14:14]);
BUFF I66 (o_0r0[15:15], i_0r0[15:15]);
BUFF I67 (o_0r0[16:16], i_0r0[16:16]);
BUFF I68 (o_0r0[17:17], i_0r0[17:17]);
BUFF I69 (o_0r0[18:18], i_0r0[18:18]);
BUFF I70 (o_0r0[19:19], i_0r0[19:19]);
BUFF I71 (o_0r0[20:20], i_0r0[20:20]);
BUFF I72 (o_0r0[21:21], i_0r0[21:21]);
BUFF I73 (o_0r0[22:22], i_0r0[22:22]);
BUFF I74 (o_0r0[23:23], i_0r0[23:23]);
BUFF I75 (o_0r0[24:24], i_0r0[24:24]);
BUFF I76 (o_0r0[25:25], i_0r0[25:25]);
BUFF I77 (o_0r0[26:26], i_0r0[26:26]);
BUFF I78 (o_0r0[27:27], i_0r0[27:27]);
BUFF I79 (o_0r0[28:28], i_0r0[28:28]);
BUFF I80 (o_0r0[29:29], i_0r0[29:29]);
BUFF I81 (o_0r0[30:30], i_0r0[30:30]);
BUFF I82 (o_0r0[31:31], termf_1);
BUFF I83 (o_0r1[0:0], i_0r1[0:0]);
BUFF I84 (o_0r1[1:1], i_0r1[1:1]);
BUFF I85 (o_0r1[2:2], i_0r1[2:2]);
BUFF I86 (o_0r1[3:3], i_0r1[3:3]);
BUFF I87 (o_0r1[4:4], i_0r1[4:4]);
BUFF I88 (o_0r1[5:5], i_0r1[5:5]);
BUFF I89 (o_0r1[6:6], i_0r1[6:6]);
BUFF I90 (o_0r1[7:7], i_0r1[7:7]);
BUFF I91 (o_0r1[8:8], i_0r1[8:8]);
BUFF I92 (o_0r1[9:9], i_0r1[9:9]);
BUFF I93 (o_0r1[10:10], i_0r1[10:10]);
BUFF I94 (o_0r1[11:11], i_0r1[11:11]);
BUFF I95 (o_0r1[12:12], i_0r1[12:12]);
BUFF I96 (o_0r1[13:13], i_0r1[13:13]);
BUFF I97 (o_0r1[14:14], i_0r1[14:14]);
BUFF I98 (o_0r1[15:15], i_0r1[15:15]);
BUFF I99 (o_0r1[16:16], i_0r1[16:16]);
BUFF I100 (o_0r1[17:17], i_0r1[17:17]);
BUFF I101 (o_0r1[18:18], i_0r1[18:18]);
BUFF I102 (o_0r1[19:19], i_0r1[19:19]);
BUFF I103 (o_0r1[20:20], i_0r1[20:20]);
BUFF I104 (o_0r1[21:21], i_0r1[21:21]);
BUFF I105 (o_0r1[22:22], i_0r1[22:22]);
BUFF I106 (o_0r1[23:23], i_0r1[23:23]);
BUFF I107 (o_0r1[24:24], i_0r1[24:24]);
BUFF I108 (o_0r1[25:25], i_0r1[25:25]);
BUFF I109 (o_0r1[26:26], i_0r1[26:26]);
BUFF I110 (o_0r1[27:27], i_0r1[27:27]);
BUFF I111 (o_0r1[28:28], i_0r1[28:28]);
BUFF I112 (o_0r1[29:29], i_0r1[29:29]);
BUFF I113 (o_0r1[30:30], i_0r1[30:30]);
BUFF I114 (o_0r1[31:31], termt_1);
BUFF I115 (i_0a, o_0a);
endmodule
// tkvi32_wo0w32_ro0w32o0w31o1w31o1w31 TeakV "i" 32 [] [0] [0,0,1,1] [Many [32],Many [0],Many [0,0,0,0]
// ,Many [32,31,31,31]]
module tkvi32_wo0w32_ro0w32o0w31o1w31o1w31 (wg_0r0, wg_0r1, wg_0a, wd_0r, wd_0a, rg_0r, rg_0a, rg_1r, rg_1a, rg_2r, rg_2a, rg_3r, rg_3a, rd_0r0, rd_0r1, rd_0a, rd_1r0, rd_1r1, rd_1a, rd_2r0, rd_2r1, rd_2a, rd_3r0, rd_3r1, rd_3a, reset);
input [31:0] wg_0r0;
input [31:0] wg_0r1;
output wg_0a;
output wd_0r;
input wd_0a;
input rg_0r;
output rg_0a;
input rg_1r;
output rg_1a;
input rg_2r;
output rg_2a;
input rg_3r;
output rg_3a;
output [31:0] rd_0r0;
output [31:0] rd_0r1;
input rd_0a;
output [30:0] rd_1r0;
output [30:0] rd_1r1;
input rd_1a;
output [30:0] rd_2r0;
output [30:0] rd_2r1;
input rd_2a;
output [30:0] rd_3r0;
output [30:0] rd_3r1;
input rd_3a;
input reset;
wire [31:0] wf_0;
wire [31:0] wt_0;
wire [31:0] df_0;
wire [31:0] dt_0;
wire wc_0;
wire [31:0] wacks_0;
wire [31:0] wenr_0;
wire [31:0] wen_0;
wire anyread_0;
wire nreset_0;
wire [31:0] drlgf_0;
wire [31:0] drlgt_0;
wire [31:0] comp0_0;
wire [10:0] simp2381_0;
wire [3:0] simp2382_0;
wire [1:0] simp2383_0;
wire conwigc_0;
wire conwigcanw_0;
wire [31:0] conwgit_0;
wire [31:0] conwgif_0;
wire conwig_0;
wire [10:0] simp4071_0;
wire [3:0] simp4072_0;
wire [1:0] simp4073_0;
wire [2:0] simp6581_0;
INV I0 (nreset_0, reset);
AND2 I1 (wen_0[0:0], wenr_0[0:0], nreset_0);
AND2 I2 (wen_0[1:1], wenr_0[1:1], nreset_0);
AND2 I3 (wen_0[2:2], wenr_0[2:2], nreset_0);
AND2 I4 (wen_0[3:3], wenr_0[3:3], nreset_0);
AND2 I5 (wen_0[4:4], wenr_0[4:4], nreset_0);
AND2 I6 (wen_0[5:5], wenr_0[5:5], nreset_0);
AND2 I7 (wen_0[6:6], wenr_0[6:6], nreset_0);
AND2 I8 (wen_0[7:7], wenr_0[7:7], nreset_0);
AND2 I9 (wen_0[8:8], wenr_0[8:8], nreset_0);
AND2 I10 (wen_0[9:9], wenr_0[9:9], nreset_0);
AND2 I11 (wen_0[10:10], wenr_0[10:10], nreset_0);
AND2 I12 (wen_0[11:11], wenr_0[11:11], nreset_0);
AND2 I13 (wen_0[12:12], wenr_0[12:12], nreset_0);
AND2 I14 (wen_0[13:13], wenr_0[13:13], nreset_0);
AND2 I15 (wen_0[14:14], wenr_0[14:14], nreset_0);
AND2 I16 (wen_0[15:15], wenr_0[15:15], nreset_0);
AND2 I17 (wen_0[16:16], wenr_0[16:16], nreset_0);
AND2 I18 (wen_0[17:17], wenr_0[17:17], nreset_0);
AND2 I19 (wen_0[18:18], wenr_0[18:18], nreset_0);
AND2 I20 (wen_0[19:19], wenr_0[19:19], nreset_0);
AND2 I21 (wen_0[20:20], wenr_0[20:20], nreset_0);
AND2 I22 (wen_0[21:21], wenr_0[21:21], nreset_0);
AND2 I23 (wen_0[22:22], wenr_0[22:22], nreset_0);
AND2 I24 (wen_0[23:23], wenr_0[23:23], nreset_0);
AND2 I25 (wen_0[24:24], wenr_0[24:24], nreset_0);
AND2 I26 (wen_0[25:25], wenr_0[25:25], nreset_0);
AND2 I27 (wen_0[26:26], wenr_0[26:26], nreset_0);
AND2 I28 (wen_0[27:27], wenr_0[27:27], nreset_0);
AND2 I29 (wen_0[28:28], wenr_0[28:28], nreset_0);
AND2 I30 (wen_0[29:29], wenr_0[29:29], nreset_0);
AND2 I31 (wen_0[30:30], wenr_0[30:30], nreset_0);
AND2 I32 (wen_0[31:31], wenr_0[31:31], nreset_0);
AND2 I33 (drlgf_0[0:0], wf_0[0:0], wen_0[0:0]);
AND2 I34 (drlgf_0[1:1], wf_0[1:1], wen_0[1:1]);
AND2 I35 (drlgf_0[2:2], wf_0[2:2], wen_0[2:2]);
AND2 I36 (drlgf_0[3:3], wf_0[3:3], wen_0[3:3]);
AND2 I37 (drlgf_0[4:4], wf_0[4:4], wen_0[4:4]);
AND2 I38 (drlgf_0[5:5], wf_0[5:5], wen_0[5:5]);
AND2 I39 (drlgf_0[6:6], wf_0[6:6], wen_0[6:6]);
AND2 I40 (drlgf_0[7:7], wf_0[7:7], wen_0[7:7]);
AND2 I41 (drlgf_0[8:8], wf_0[8:8], wen_0[8:8]);
AND2 I42 (drlgf_0[9:9], wf_0[9:9], wen_0[9:9]);
AND2 I43 (drlgf_0[10:10], wf_0[10:10], wen_0[10:10]);
AND2 I44 (drlgf_0[11:11], wf_0[11:11], wen_0[11:11]);
AND2 I45 (drlgf_0[12:12], wf_0[12:12], wen_0[12:12]);
AND2 I46 (drlgf_0[13:13], wf_0[13:13], wen_0[13:13]);
AND2 I47 (drlgf_0[14:14], wf_0[14:14], wen_0[14:14]);
AND2 I48 (drlgf_0[15:15], wf_0[15:15], wen_0[15:15]);
AND2 I49 (drlgf_0[16:16], wf_0[16:16], wen_0[16:16]);
AND2 I50 (drlgf_0[17:17], wf_0[17:17], wen_0[17:17]);
AND2 I51 (drlgf_0[18:18], wf_0[18:18], wen_0[18:18]);
AND2 I52 (drlgf_0[19:19], wf_0[19:19], wen_0[19:19]);
AND2 I53 (drlgf_0[20:20], wf_0[20:20], wen_0[20:20]);
AND2 I54 (drlgf_0[21:21], wf_0[21:21], wen_0[21:21]);
AND2 I55 (drlgf_0[22:22], wf_0[22:22], wen_0[22:22]);
AND2 I56 (drlgf_0[23:23], wf_0[23:23], wen_0[23:23]);
AND2 I57 (drlgf_0[24:24], wf_0[24:24], wen_0[24:24]);
AND2 I58 (drlgf_0[25:25], wf_0[25:25], wen_0[25:25]);
AND2 I59 (drlgf_0[26:26], wf_0[26:26], wen_0[26:26]);
AND2 I60 (drlgf_0[27:27], wf_0[27:27], wen_0[27:27]);
AND2 I61 (drlgf_0[28:28], wf_0[28:28], wen_0[28:28]);
AND2 I62 (drlgf_0[29:29], wf_0[29:29], wen_0[29:29]);
AND2 I63 (drlgf_0[30:30], wf_0[30:30], wen_0[30:30]);
AND2 I64 (drlgf_0[31:31], wf_0[31:31], wen_0[31:31]);
AND2 I65 (drlgt_0[0:0], wt_0[0:0], wen_0[0:0]);
AND2 I66 (drlgt_0[1:1], wt_0[1:1], wen_0[1:1]);
AND2 I67 (drlgt_0[2:2], wt_0[2:2], wen_0[2:2]);
AND2 I68 (drlgt_0[3:3], wt_0[3:3], wen_0[3:3]);
AND2 I69 (drlgt_0[4:4], wt_0[4:4], wen_0[4:4]);
AND2 I70 (drlgt_0[5:5], wt_0[5:5], wen_0[5:5]);
AND2 I71 (drlgt_0[6:6], wt_0[6:6], wen_0[6:6]);
AND2 I72 (drlgt_0[7:7], wt_0[7:7], wen_0[7:7]);
AND2 I73 (drlgt_0[8:8], wt_0[8:8], wen_0[8:8]);
AND2 I74 (drlgt_0[9:9], wt_0[9:9], wen_0[9:9]);
AND2 I75 (drlgt_0[10:10], wt_0[10:10], wen_0[10:10]);
AND2 I76 (drlgt_0[11:11], wt_0[11:11], wen_0[11:11]);
AND2 I77 (drlgt_0[12:12], wt_0[12:12], wen_0[12:12]);
AND2 I78 (drlgt_0[13:13], wt_0[13:13], wen_0[13:13]);
AND2 I79 (drlgt_0[14:14], wt_0[14:14], wen_0[14:14]);
AND2 I80 (drlgt_0[15:15], wt_0[15:15], wen_0[15:15]);
AND2 I81 (drlgt_0[16:16], wt_0[16:16], wen_0[16:16]);
AND2 I82 (drlgt_0[17:17], wt_0[17:17], wen_0[17:17]);
AND2 I83 (drlgt_0[18:18], wt_0[18:18], wen_0[18:18]);
AND2 I84 (drlgt_0[19:19], wt_0[19:19], wen_0[19:19]);
AND2 I85 (drlgt_0[20:20], wt_0[20:20], wen_0[20:20]);
AND2 I86 (drlgt_0[21:21], wt_0[21:21], wen_0[21:21]);
AND2 I87 (drlgt_0[22:22], wt_0[22:22], wen_0[22:22]);
AND2 I88 (drlgt_0[23:23], wt_0[23:23], wen_0[23:23]);
AND2 I89 (drlgt_0[24:24], wt_0[24:24], wen_0[24:24]);
AND2 I90 (drlgt_0[25:25], wt_0[25:25], wen_0[25:25]);
AND2 I91 (drlgt_0[26:26], wt_0[26:26], wen_0[26:26]);
AND2 I92 (drlgt_0[27:27], wt_0[27:27], wen_0[27:27]);
AND2 I93 (drlgt_0[28:28], wt_0[28:28], wen_0[28:28]);
AND2 I94 (drlgt_0[29:29], wt_0[29:29], wen_0[29:29]);
AND2 I95 (drlgt_0[30:30], wt_0[30:30], wen_0[30:30]);
AND2 I96 (drlgt_0[31:31], wt_0[31:31], wen_0[31:31]);
NOR2 I97 (df_0[0:0], dt_0[0:0], drlgt_0[0:0]);
NOR2 I98 (df_0[1:1], dt_0[1:1], drlgt_0[1:1]);
NOR2 I99 (df_0[2:2], dt_0[2:2], drlgt_0[2:2]);
NOR2 I100 (df_0[3:3], dt_0[3:3], drlgt_0[3:3]);
NOR2 I101 (df_0[4:4], dt_0[4:4], drlgt_0[4:4]);
NOR2 I102 (df_0[5:5], dt_0[5:5], drlgt_0[5:5]);
NOR2 I103 (df_0[6:6], dt_0[6:6], drlgt_0[6:6]);
NOR2 I104 (df_0[7:7], dt_0[7:7], drlgt_0[7:7]);
NOR2 I105 (df_0[8:8], dt_0[8:8], drlgt_0[8:8]);
NOR2 I106 (df_0[9:9], dt_0[9:9], drlgt_0[9:9]);
NOR2 I107 (df_0[10:10], dt_0[10:10], drlgt_0[10:10]);
NOR2 I108 (df_0[11:11], dt_0[11:11], drlgt_0[11:11]);
NOR2 I109 (df_0[12:12], dt_0[12:12], drlgt_0[12:12]);
NOR2 I110 (df_0[13:13], dt_0[13:13], drlgt_0[13:13]);
NOR2 I111 (df_0[14:14], dt_0[14:14], drlgt_0[14:14]);
NOR2 I112 (df_0[15:15], dt_0[15:15], drlgt_0[15:15]);
NOR2 I113 (df_0[16:16], dt_0[16:16], drlgt_0[16:16]);
NOR2 I114 (df_0[17:17], dt_0[17:17], drlgt_0[17:17]);
NOR2 I115 (df_0[18:18], dt_0[18:18], drlgt_0[18:18]);
NOR2 I116 (df_0[19:19], dt_0[19:19], drlgt_0[19:19]);
NOR2 I117 (df_0[20:20], dt_0[20:20], drlgt_0[20:20]);
NOR2 I118 (df_0[21:21], dt_0[21:21], drlgt_0[21:21]);
NOR2 I119 (df_0[22:22], dt_0[22:22], drlgt_0[22:22]);
NOR2 I120 (df_0[23:23], dt_0[23:23], drlgt_0[23:23]);
NOR2 I121 (df_0[24:24], dt_0[24:24], drlgt_0[24:24]);
NOR2 I122 (df_0[25:25], dt_0[25:25], drlgt_0[25:25]);
NOR2 I123 (df_0[26:26], dt_0[26:26], drlgt_0[26:26]);
NOR2 I124 (df_0[27:27], dt_0[27:27], drlgt_0[27:27]);
NOR2 I125 (df_0[28:28], dt_0[28:28], drlgt_0[28:28]);
NOR2 I126 (df_0[29:29], dt_0[29:29], drlgt_0[29:29]);
NOR2 I127 (df_0[30:30], dt_0[30:30], drlgt_0[30:30]);
NOR2 I128 (df_0[31:31], dt_0[31:31], drlgt_0[31:31]);
NOR3 I129 (dt_0[0:0], df_0[0:0], drlgf_0[0:0], reset);
NOR3 I130 (dt_0[1:1], df_0[1:1], drlgf_0[1:1], reset);
NOR3 I131 (dt_0[2:2], df_0[2:2], drlgf_0[2:2], reset);
NOR3 I132 (dt_0[3:3], df_0[3:3], drlgf_0[3:3], reset);
NOR3 I133 (dt_0[4:4], df_0[4:4], drlgf_0[4:4], reset);
NOR3 I134 (dt_0[5:5], df_0[5:5], drlgf_0[5:5], reset);
NOR3 I135 (dt_0[6:6], df_0[6:6], drlgf_0[6:6], reset);
NOR3 I136 (dt_0[7:7], df_0[7:7], drlgf_0[7:7], reset);
NOR3 I137 (dt_0[8:8], df_0[8:8], drlgf_0[8:8], reset);
NOR3 I138 (dt_0[9:9], df_0[9:9], drlgf_0[9:9], reset);
NOR3 I139 (dt_0[10:10], df_0[10:10], drlgf_0[10:10], reset);
NOR3 I140 (dt_0[11:11], df_0[11:11], drlgf_0[11:11], reset);
NOR3 I141 (dt_0[12:12], df_0[12:12], drlgf_0[12:12], reset);
NOR3 I142 (dt_0[13:13], df_0[13:13], drlgf_0[13:13], reset);
NOR3 I143 (dt_0[14:14], df_0[14:14], drlgf_0[14:14], reset);
NOR3 I144 (dt_0[15:15], df_0[15:15], drlgf_0[15:15], reset);
NOR3 I145 (dt_0[16:16], df_0[16:16], drlgf_0[16:16], reset);
NOR3 I146 (dt_0[17:17], df_0[17:17], drlgf_0[17:17], reset);
NOR3 I147 (dt_0[18:18], df_0[18:18], drlgf_0[18:18], reset);
NOR3 I148 (dt_0[19:19], df_0[19:19], drlgf_0[19:19], reset);
NOR3 I149 (dt_0[20:20], df_0[20:20], drlgf_0[20:20], reset);
NOR3 I150 (dt_0[21:21], df_0[21:21], drlgf_0[21:21], reset);
NOR3 I151 (dt_0[22:22], df_0[22:22], drlgf_0[22:22], reset);
NOR3 I152 (dt_0[23:23], df_0[23:23], drlgf_0[23:23], reset);
NOR3 I153 (dt_0[24:24], df_0[24:24], drlgf_0[24:24], reset);
NOR3 I154 (dt_0[25:25], df_0[25:25], drlgf_0[25:25], reset);
NOR3 I155 (dt_0[26:26], df_0[26:26], drlgf_0[26:26], reset);
NOR3 I156 (dt_0[27:27], df_0[27:27], drlgf_0[27:27], reset);
NOR3 I157 (dt_0[28:28], df_0[28:28], drlgf_0[28:28], reset);
NOR3 I158 (dt_0[29:29], df_0[29:29], drlgf_0[29:29], reset);
NOR3 I159 (dt_0[30:30], df_0[30:30], drlgf_0[30:30], reset);
NOR3 I160 (dt_0[31:31], df_0[31:31], drlgf_0[31:31], reset);
AO22 I161 (wacks_0[0:0], drlgf_0[0:0], df_0[0:0], drlgt_0[0:0], dt_0[0:0]);
AO22 I162 (wacks_0[1:1], drlgf_0[1:1], df_0[1:1], drlgt_0[1:1], dt_0[1:1]);
AO22 I163 (wacks_0[2:2], drlgf_0[2:2], df_0[2:2], drlgt_0[2:2], dt_0[2:2]);
AO22 I164 (wacks_0[3:3], drlgf_0[3:3], df_0[3:3], drlgt_0[3:3], dt_0[3:3]);
AO22 I165 (wacks_0[4:4], drlgf_0[4:4], df_0[4:4], drlgt_0[4:4], dt_0[4:4]);
AO22 I166 (wacks_0[5:5], drlgf_0[5:5], df_0[5:5], drlgt_0[5:5], dt_0[5:5]);
AO22 I167 (wacks_0[6:6], drlgf_0[6:6], df_0[6:6], drlgt_0[6:6], dt_0[6:6]);
AO22 I168 (wacks_0[7:7], drlgf_0[7:7], df_0[7:7], drlgt_0[7:7], dt_0[7:7]);
AO22 I169 (wacks_0[8:8], drlgf_0[8:8], df_0[8:8], drlgt_0[8:8], dt_0[8:8]);
AO22 I170 (wacks_0[9:9], drlgf_0[9:9], df_0[9:9], drlgt_0[9:9], dt_0[9:9]);
AO22 I171 (wacks_0[10:10], drlgf_0[10:10], df_0[10:10], drlgt_0[10:10], dt_0[10:10]);
AO22 I172 (wacks_0[11:11], drlgf_0[11:11], df_0[11:11], drlgt_0[11:11], dt_0[11:11]);
AO22 I173 (wacks_0[12:12], drlgf_0[12:12], df_0[12:12], drlgt_0[12:12], dt_0[12:12]);
AO22 I174 (wacks_0[13:13], drlgf_0[13:13], df_0[13:13], drlgt_0[13:13], dt_0[13:13]);
AO22 I175 (wacks_0[14:14], drlgf_0[14:14], df_0[14:14], drlgt_0[14:14], dt_0[14:14]);
AO22 I176 (wacks_0[15:15], drlgf_0[15:15], df_0[15:15], drlgt_0[15:15], dt_0[15:15]);
AO22 I177 (wacks_0[16:16], drlgf_0[16:16], df_0[16:16], drlgt_0[16:16], dt_0[16:16]);
AO22 I178 (wacks_0[17:17], drlgf_0[17:17], df_0[17:17], drlgt_0[17:17], dt_0[17:17]);
AO22 I179 (wacks_0[18:18], drlgf_0[18:18], df_0[18:18], drlgt_0[18:18], dt_0[18:18]);
AO22 I180 (wacks_0[19:19], drlgf_0[19:19], df_0[19:19], drlgt_0[19:19], dt_0[19:19]);
AO22 I181 (wacks_0[20:20], drlgf_0[20:20], df_0[20:20], drlgt_0[20:20], dt_0[20:20]);
AO22 I182 (wacks_0[21:21], drlgf_0[21:21], df_0[21:21], drlgt_0[21:21], dt_0[21:21]);
AO22 I183 (wacks_0[22:22], drlgf_0[22:22], df_0[22:22], drlgt_0[22:22], dt_0[22:22]);
AO22 I184 (wacks_0[23:23], drlgf_0[23:23], df_0[23:23], drlgt_0[23:23], dt_0[23:23]);
AO22 I185 (wacks_0[24:24], drlgf_0[24:24], df_0[24:24], drlgt_0[24:24], dt_0[24:24]);
AO22 I186 (wacks_0[25:25], drlgf_0[25:25], df_0[25:25], drlgt_0[25:25], dt_0[25:25]);
AO22 I187 (wacks_0[26:26], drlgf_0[26:26], df_0[26:26], drlgt_0[26:26], dt_0[26:26]);
AO22 I188 (wacks_0[27:27], drlgf_0[27:27], df_0[27:27], drlgt_0[27:27], dt_0[27:27]);
AO22 I189 (wacks_0[28:28], drlgf_0[28:28], df_0[28:28], drlgt_0[28:28], dt_0[28:28]);
AO22 I190 (wacks_0[29:29], drlgf_0[29:29], df_0[29:29], drlgt_0[29:29], dt_0[29:29]);
AO22 I191 (wacks_0[30:30], drlgf_0[30:30], df_0[30:30], drlgt_0[30:30], dt_0[30:30]);
AO22 I192 (wacks_0[31:31], drlgf_0[31:31], df_0[31:31], drlgt_0[31:31], dt_0[31:31]);
OR2 I193 (comp0_0[0:0], wg_0r0[0:0], wg_0r1[0:0]);
OR2 I194 (comp0_0[1:1], wg_0r0[1:1], wg_0r1[1:1]);
OR2 I195 (comp0_0[2:2], wg_0r0[2:2], wg_0r1[2:2]);
OR2 I196 (comp0_0[3:3], wg_0r0[3:3], wg_0r1[3:3]);
OR2 I197 (comp0_0[4:4], wg_0r0[4:4], wg_0r1[4:4]);
OR2 I198 (comp0_0[5:5], wg_0r0[5:5], wg_0r1[5:5]);
OR2 I199 (comp0_0[6:6], wg_0r0[6:6], wg_0r1[6:6]);
OR2 I200 (comp0_0[7:7], wg_0r0[7:7], wg_0r1[7:7]);
OR2 I201 (comp0_0[8:8], wg_0r0[8:8], wg_0r1[8:8]);
OR2 I202 (comp0_0[9:9], wg_0r0[9:9], wg_0r1[9:9]);
OR2 I203 (comp0_0[10:10], wg_0r0[10:10], wg_0r1[10:10]);
OR2 I204 (comp0_0[11:11], wg_0r0[11:11], wg_0r1[11:11]);
OR2 I205 (comp0_0[12:12], wg_0r0[12:12], wg_0r1[12:12]);
OR2 I206 (comp0_0[13:13], wg_0r0[13:13], wg_0r1[13:13]);
OR2 I207 (comp0_0[14:14], wg_0r0[14:14], wg_0r1[14:14]);
OR2 I208 (comp0_0[15:15], wg_0r0[15:15], wg_0r1[15:15]);
OR2 I209 (comp0_0[16:16], wg_0r0[16:16], wg_0r1[16:16]);
OR2 I210 (comp0_0[17:17], wg_0r0[17:17], wg_0r1[17:17]);
OR2 I211 (comp0_0[18:18], wg_0r0[18:18], wg_0r1[18:18]);
OR2 I212 (comp0_0[19:19], wg_0r0[19:19], wg_0r1[19:19]);
OR2 I213 (comp0_0[20:20], wg_0r0[20:20], wg_0r1[20:20]);
OR2 I214 (comp0_0[21:21], wg_0r0[21:21], wg_0r1[21:21]);
OR2 I215 (comp0_0[22:22], wg_0r0[22:22], wg_0r1[22:22]);
OR2 I216 (comp0_0[23:23], wg_0r0[23:23], wg_0r1[23:23]);
OR2 I217 (comp0_0[24:24], wg_0r0[24:24], wg_0r1[24:24]);
OR2 I218 (comp0_0[25:25], wg_0r0[25:25], wg_0r1[25:25]);
OR2 I219 (comp0_0[26:26], wg_0r0[26:26], wg_0r1[26:26]);
OR2 I220 (comp0_0[27:27], wg_0r0[27:27], wg_0r1[27:27]);
OR2 I221 (comp0_0[28:28], wg_0r0[28:28], wg_0r1[28:28]);
OR2 I222 (comp0_0[29:29], wg_0r0[29:29], wg_0r1[29:29]);
OR2 I223 (comp0_0[30:30], wg_0r0[30:30], wg_0r1[30:30]);
OR2 I224 (comp0_0[31:31], wg_0r0[31:31], wg_0r1[31:31]);
C3 I225 (simp2381_0[0:0], comp0_0[0:0], comp0_0[1:1], comp0_0[2:2]);
C3 I226 (simp2381_0[1:1], comp0_0[3:3], comp0_0[4:4], comp0_0[5:5]);
C3 I227 (simp2381_0[2:2], comp0_0[6:6], comp0_0[7:7], comp0_0[8:8]);
C3 I228 (simp2381_0[3:3], comp0_0[9:9], comp0_0[10:10], comp0_0[11:11]);
C3 I229 (simp2381_0[4:4], comp0_0[12:12], comp0_0[13:13], comp0_0[14:14]);
C3 I230 (simp2381_0[5:5], comp0_0[15:15], comp0_0[16:16], comp0_0[17:17]);
C3 I231 (simp2381_0[6:6], comp0_0[18:18], comp0_0[19:19], comp0_0[20:20]);
C3 I232 (simp2381_0[7:7], comp0_0[21:21], comp0_0[22:22], comp0_0[23:23]);
C3 I233 (simp2381_0[8:8], comp0_0[24:24], comp0_0[25:25], comp0_0[26:26]);
C3 I234 (simp2381_0[9:9], comp0_0[27:27], comp0_0[28:28], comp0_0[29:29]);
C2 I235 (simp2381_0[10:10], comp0_0[30:30], comp0_0[31:31]);
C3 I236 (simp2382_0[0:0], simp2381_0[0:0], simp2381_0[1:1], simp2381_0[2:2]);
C3 I237 (simp2382_0[1:1], simp2381_0[3:3], simp2381_0[4:4], simp2381_0[5:5]);
C3 I238 (simp2382_0[2:2], simp2381_0[6:6], simp2381_0[7:7], simp2381_0[8:8]);
C2 I239 (simp2382_0[3:3], simp2381_0[9:9], simp2381_0[10:10]);
C3 I240 (simp2383_0[0:0], simp2382_0[0:0], simp2382_0[1:1], simp2382_0[2:2]);
BUFF I241 (simp2383_0[1:1], simp2382_0[3:3]);
C2 I242 (wc_0, simp2383_0[0:0], simp2383_0[1:1]);
AND2 I243 (conwgif_0[0:0], wg_0r0[0:0], conwig_0);
AND2 I244 (conwgif_0[1:1], wg_0r0[1:1], conwig_0);
AND2 I245 (conwgif_0[2:2], wg_0r0[2:2], conwig_0);
AND2 I246 (conwgif_0[3:3], wg_0r0[3:3], conwig_0);
AND2 I247 (conwgif_0[4:4], wg_0r0[4:4], conwig_0);
AND2 I248 (conwgif_0[5:5], wg_0r0[5:5], conwig_0);
AND2 I249 (conwgif_0[6:6], wg_0r0[6:6], conwig_0);
AND2 I250 (conwgif_0[7:7], wg_0r0[7:7], conwig_0);
AND2 I251 (conwgif_0[8:8], wg_0r0[8:8], conwig_0);
AND2 I252 (conwgif_0[9:9], wg_0r0[9:9], conwig_0);
AND2 I253 (conwgif_0[10:10], wg_0r0[10:10], conwig_0);
AND2 I254 (conwgif_0[11:11], wg_0r0[11:11], conwig_0);
AND2 I255 (conwgif_0[12:12], wg_0r0[12:12], conwig_0);
AND2 I256 (conwgif_0[13:13], wg_0r0[13:13], conwig_0);
AND2 I257 (conwgif_0[14:14], wg_0r0[14:14], conwig_0);
AND2 I258 (conwgif_0[15:15], wg_0r0[15:15], conwig_0);
AND2 I259 (conwgif_0[16:16], wg_0r0[16:16], conwig_0);
AND2 I260 (conwgif_0[17:17], wg_0r0[17:17], conwig_0);
AND2 I261 (conwgif_0[18:18], wg_0r0[18:18], conwig_0);
AND2 I262 (conwgif_0[19:19], wg_0r0[19:19], conwig_0);
AND2 I263 (conwgif_0[20:20], wg_0r0[20:20], conwig_0);
AND2 I264 (conwgif_0[21:21], wg_0r0[21:21], conwig_0);
AND2 I265 (conwgif_0[22:22], wg_0r0[22:22], conwig_0);
AND2 I266 (conwgif_0[23:23], wg_0r0[23:23], conwig_0);
AND2 I267 (conwgif_0[24:24], wg_0r0[24:24], conwig_0);
AND2 I268 (conwgif_0[25:25], wg_0r0[25:25], conwig_0);
AND2 I269 (conwgif_0[26:26], wg_0r0[26:26], conwig_0);
AND2 I270 (conwgif_0[27:27], wg_0r0[27:27], conwig_0);
AND2 I271 (conwgif_0[28:28], wg_0r0[28:28], conwig_0);
AND2 I272 (conwgif_0[29:29], wg_0r0[29:29], conwig_0);
AND2 I273 (conwgif_0[30:30], wg_0r0[30:30], conwig_0);
AND2 I274 (conwgif_0[31:31], wg_0r0[31:31], conwig_0);
AND2 I275 (conwgit_0[0:0], wg_0r1[0:0], conwig_0);
AND2 I276 (conwgit_0[1:1], wg_0r1[1:1], conwig_0);
AND2 I277 (conwgit_0[2:2], wg_0r1[2:2], conwig_0);
AND2 I278 (conwgit_0[3:3], wg_0r1[3:3], conwig_0);
AND2 I279 (conwgit_0[4:4], wg_0r1[4:4], conwig_0);
AND2 I280 (conwgit_0[5:5], wg_0r1[5:5], conwig_0);
AND2 I281 (conwgit_0[6:6], wg_0r1[6:6], conwig_0);
AND2 I282 (conwgit_0[7:7], wg_0r1[7:7], conwig_0);
AND2 I283 (conwgit_0[8:8], wg_0r1[8:8], conwig_0);
AND2 I284 (conwgit_0[9:9], wg_0r1[9:9], conwig_0);
AND2 I285 (conwgit_0[10:10], wg_0r1[10:10], conwig_0);
AND2 I286 (conwgit_0[11:11], wg_0r1[11:11], conwig_0);
AND2 I287 (conwgit_0[12:12], wg_0r1[12:12], conwig_0);
AND2 I288 (conwgit_0[13:13], wg_0r1[13:13], conwig_0);
AND2 I289 (conwgit_0[14:14], wg_0r1[14:14], conwig_0);
AND2 I290 (conwgit_0[15:15], wg_0r1[15:15], conwig_0);
AND2 I291 (conwgit_0[16:16], wg_0r1[16:16], conwig_0);
AND2 I292 (conwgit_0[17:17], wg_0r1[17:17], conwig_0);
AND2 I293 (conwgit_0[18:18], wg_0r1[18:18], conwig_0);
AND2 I294 (conwgit_0[19:19], wg_0r1[19:19], conwig_0);
AND2 I295 (conwgit_0[20:20], wg_0r1[20:20], conwig_0);
AND2 I296 (conwgit_0[21:21], wg_0r1[21:21], conwig_0);
AND2 I297 (conwgit_0[22:22], wg_0r1[22:22], conwig_0);
AND2 I298 (conwgit_0[23:23], wg_0r1[23:23], conwig_0);
AND2 I299 (conwgit_0[24:24], wg_0r1[24:24], conwig_0);
AND2 I300 (conwgit_0[25:25], wg_0r1[25:25], conwig_0);
AND2 I301 (conwgit_0[26:26], wg_0r1[26:26], conwig_0);
AND2 I302 (conwgit_0[27:27], wg_0r1[27:27], conwig_0);
AND2 I303 (conwgit_0[28:28], wg_0r1[28:28], conwig_0);
AND2 I304 (conwgit_0[29:29], wg_0r1[29:29], conwig_0);
AND2 I305 (conwgit_0[30:30], wg_0r1[30:30], conwig_0);
AND2 I306 (conwgit_0[31:31], wg_0r1[31:31], conwig_0);
BUFF I307 (conwigc_0, wc_0);
AO22 I308 (conwig_0, conwigc_0, conwigcanw_0, conwigc_0, conwig_0);
NOR2 I309 (conwigcanw_0, anyread_0, conwig_0);
BUFF I310 (wf_0[0:0], conwgif_0[0:0]);
BUFF I311 (wt_0[0:0], conwgit_0[0:0]);
BUFF I312 (wenr_0[0:0], wc_0);
BUFF I313 (wf_0[1:1], conwgif_0[1:1]);
BUFF I314 (wt_0[1:1], conwgit_0[1:1]);
BUFF I315 (wenr_0[1:1], wc_0);
BUFF I316 (wf_0[2:2], conwgif_0[2:2]);
BUFF I317 (wt_0[2:2], conwgit_0[2:2]);
BUFF I318 (wenr_0[2:2], wc_0);
BUFF I319 (wf_0[3:3], conwgif_0[3:3]);
BUFF I320 (wt_0[3:3], conwgit_0[3:3]);
BUFF I321 (wenr_0[3:3], wc_0);
BUFF I322 (wf_0[4:4], conwgif_0[4:4]);
BUFF I323 (wt_0[4:4], conwgit_0[4:4]);
BUFF I324 (wenr_0[4:4], wc_0);
BUFF I325 (wf_0[5:5], conwgif_0[5:5]);
BUFF I326 (wt_0[5:5], conwgit_0[5:5]);
BUFF I327 (wenr_0[5:5], wc_0);
BUFF I328 (wf_0[6:6], conwgif_0[6:6]);
BUFF I329 (wt_0[6:6], conwgit_0[6:6]);
BUFF I330 (wenr_0[6:6], wc_0);
BUFF I331 (wf_0[7:7], conwgif_0[7:7]);
BUFF I332 (wt_0[7:7], conwgit_0[7:7]);
BUFF I333 (wenr_0[7:7], wc_0);
BUFF I334 (wf_0[8:8], conwgif_0[8:8]);
BUFF I335 (wt_0[8:8], conwgit_0[8:8]);
BUFF I336 (wenr_0[8:8], wc_0);
BUFF I337 (wf_0[9:9], conwgif_0[9:9]);
BUFF I338 (wt_0[9:9], conwgit_0[9:9]);
BUFF I339 (wenr_0[9:9], wc_0);
BUFF I340 (wf_0[10:10], conwgif_0[10:10]);
BUFF I341 (wt_0[10:10], conwgit_0[10:10]);
BUFF I342 (wenr_0[10:10], wc_0);
BUFF I343 (wf_0[11:11], conwgif_0[11:11]);
BUFF I344 (wt_0[11:11], conwgit_0[11:11]);
BUFF I345 (wenr_0[11:11], wc_0);
BUFF I346 (wf_0[12:12], conwgif_0[12:12]);
BUFF I347 (wt_0[12:12], conwgit_0[12:12]);
BUFF I348 (wenr_0[12:12], wc_0);
BUFF I349 (wf_0[13:13], conwgif_0[13:13]);
BUFF I350 (wt_0[13:13], conwgit_0[13:13]);
BUFF I351 (wenr_0[13:13], wc_0);
BUFF I352 (wf_0[14:14], conwgif_0[14:14]);
BUFF I353 (wt_0[14:14], conwgit_0[14:14]);
BUFF I354 (wenr_0[14:14], wc_0);
BUFF I355 (wf_0[15:15], conwgif_0[15:15]);
BUFF I356 (wt_0[15:15], conwgit_0[15:15]);
BUFF I357 (wenr_0[15:15], wc_0);
BUFF I358 (wf_0[16:16], conwgif_0[16:16]);
BUFF I359 (wt_0[16:16], conwgit_0[16:16]);
BUFF I360 (wenr_0[16:16], wc_0);
BUFF I361 (wf_0[17:17], conwgif_0[17:17]);
BUFF I362 (wt_0[17:17], conwgit_0[17:17]);
BUFF I363 (wenr_0[17:17], wc_0);
BUFF I364 (wf_0[18:18], conwgif_0[18:18]);
BUFF I365 (wt_0[18:18], conwgit_0[18:18]);
BUFF I366 (wenr_0[18:18], wc_0);
BUFF I367 (wf_0[19:19], conwgif_0[19:19]);
BUFF I368 (wt_0[19:19], conwgit_0[19:19]);
BUFF I369 (wenr_0[19:19], wc_0);
BUFF I370 (wf_0[20:20], conwgif_0[20:20]);
BUFF I371 (wt_0[20:20], conwgit_0[20:20]);
BUFF I372 (wenr_0[20:20], wc_0);
BUFF I373 (wf_0[21:21], conwgif_0[21:21]);
BUFF I374 (wt_0[21:21], conwgit_0[21:21]);
BUFF I375 (wenr_0[21:21], wc_0);
BUFF I376 (wf_0[22:22], conwgif_0[22:22]);
BUFF I377 (wt_0[22:22], conwgit_0[22:22]);
BUFF I378 (wenr_0[22:22], wc_0);
BUFF I379 (wf_0[23:23], conwgif_0[23:23]);
BUFF I380 (wt_0[23:23], conwgit_0[23:23]);
BUFF I381 (wenr_0[23:23], wc_0);
BUFF I382 (wf_0[24:24], conwgif_0[24:24]);
BUFF I383 (wt_0[24:24], conwgit_0[24:24]);
BUFF I384 (wenr_0[24:24], wc_0);
BUFF I385 (wf_0[25:25], conwgif_0[25:25]);
BUFF I386 (wt_0[25:25], conwgit_0[25:25]);
BUFF I387 (wenr_0[25:25], wc_0);
BUFF I388 (wf_0[26:26], conwgif_0[26:26]);
BUFF I389 (wt_0[26:26], conwgit_0[26:26]);
BUFF I390 (wenr_0[26:26], wc_0);
BUFF I391 (wf_0[27:27], conwgif_0[27:27]);
BUFF I392 (wt_0[27:27], conwgit_0[27:27]);
BUFF I393 (wenr_0[27:27], wc_0);
BUFF I394 (wf_0[28:28], conwgif_0[28:28]);
BUFF I395 (wt_0[28:28], conwgit_0[28:28]);
BUFF I396 (wenr_0[28:28], wc_0);
BUFF I397 (wf_0[29:29], conwgif_0[29:29]);
BUFF I398 (wt_0[29:29], conwgit_0[29:29]);
BUFF I399 (wenr_0[29:29], wc_0);
BUFF I400 (wf_0[30:30], conwgif_0[30:30]);
BUFF I401 (wt_0[30:30], conwgit_0[30:30]);
BUFF I402 (wenr_0[30:30], wc_0);
BUFF I403 (wf_0[31:31], conwgif_0[31:31]);
BUFF I404 (wt_0[31:31], conwgit_0[31:31]);
BUFF I405 (wenr_0[31:31], wc_0);
C3 I406 (simp4071_0[0:0], conwig_0, wacks_0[0:0], wacks_0[1:1]);
C3 I407 (simp4071_0[1:1], wacks_0[2:2], wacks_0[3:3], wacks_0[4:4]);
C3 I408 (simp4071_0[2:2], wacks_0[5:5], wacks_0[6:6], wacks_0[7:7]);
C3 I409 (simp4071_0[3:3], wacks_0[8:8], wacks_0[9:9], wacks_0[10:10]);
C3 I410 (simp4071_0[4:4], wacks_0[11:11], wacks_0[12:12], wacks_0[13:13]);
C3 I411 (simp4071_0[5:5], wacks_0[14:14], wacks_0[15:15], wacks_0[16:16]);
C3 I412 (simp4071_0[6:6], wacks_0[17:17], wacks_0[18:18], wacks_0[19:19]);
C3 I413 (simp4071_0[7:7], wacks_0[20:20], wacks_0[21:21], wacks_0[22:22]);
C3 I414 (simp4071_0[8:8], wacks_0[23:23], wacks_0[24:24], wacks_0[25:25]);
C3 I415 (simp4071_0[9:9], wacks_0[26:26], wacks_0[27:27], wacks_0[28:28]);
C3 I416 (simp4071_0[10:10], wacks_0[29:29], wacks_0[30:30], wacks_0[31:31]);
C3 I417 (simp4072_0[0:0], simp4071_0[0:0], simp4071_0[1:1], simp4071_0[2:2]);
C3 I418 (simp4072_0[1:1], simp4071_0[3:3], simp4071_0[4:4], simp4071_0[5:5]);
C3 I419 (simp4072_0[2:2], simp4071_0[6:6], simp4071_0[7:7], simp4071_0[8:8]);
C2 I420 (simp4072_0[3:3], simp4071_0[9:9], simp4071_0[10:10]);
C3 I421 (simp4073_0[0:0], simp4072_0[0:0], simp4072_0[1:1], simp4072_0[2:2]);
BUFF I422 (simp4073_0[1:1], simp4072_0[3:3]);
C2 I423 (wd_0r, simp4073_0[0:0], simp4073_0[1:1]);
AND2 I424 (rd_0r0[0:0], df_0[0:0], rg_0r);
AND2 I425 (rd_0r0[1:1], df_0[1:1], rg_0r);
AND2 I426 (rd_0r0[2:2], df_0[2:2], rg_0r);
AND2 I427 (rd_0r0[3:3], df_0[3:3], rg_0r);
AND2 I428 (rd_0r0[4:4], df_0[4:4], rg_0r);
AND2 I429 (rd_0r0[5:5], df_0[5:5], rg_0r);
AND2 I430 (rd_0r0[6:6], df_0[6:6], rg_0r);
AND2 I431 (rd_0r0[7:7], df_0[7:7], rg_0r);
AND2 I432 (rd_0r0[8:8], df_0[8:8], rg_0r);
AND2 I433 (rd_0r0[9:9], df_0[9:9], rg_0r);
AND2 I434 (rd_0r0[10:10], df_0[10:10], rg_0r);
AND2 I435 (rd_0r0[11:11], df_0[11:11], rg_0r);
AND2 I436 (rd_0r0[12:12], df_0[12:12], rg_0r);
AND2 I437 (rd_0r0[13:13], df_0[13:13], rg_0r);
AND2 I438 (rd_0r0[14:14], df_0[14:14], rg_0r);
AND2 I439 (rd_0r0[15:15], df_0[15:15], rg_0r);
AND2 I440 (rd_0r0[16:16], df_0[16:16], rg_0r);
AND2 I441 (rd_0r0[17:17], df_0[17:17], rg_0r);
AND2 I442 (rd_0r0[18:18], df_0[18:18], rg_0r);
AND2 I443 (rd_0r0[19:19], df_0[19:19], rg_0r);
AND2 I444 (rd_0r0[20:20], df_0[20:20], rg_0r);
AND2 I445 (rd_0r0[21:21], df_0[21:21], rg_0r);
AND2 I446 (rd_0r0[22:22], df_0[22:22], rg_0r);
AND2 I447 (rd_0r0[23:23], df_0[23:23], rg_0r);
AND2 I448 (rd_0r0[24:24], df_0[24:24], rg_0r);
AND2 I449 (rd_0r0[25:25], df_0[25:25], rg_0r);
AND2 I450 (rd_0r0[26:26], df_0[26:26], rg_0r);
AND2 I451 (rd_0r0[27:27], df_0[27:27], rg_0r);
AND2 I452 (rd_0r0[28:28], df_0[28:28], rg_0r);
AND2 I453 (rd_0r0[29:29], df_0[29:29], rg_0r);
AND2 I454 (rd_0r0[30:30], df_0[30:30], rg_0r);
AND2 I455 (rd_0r0[31:31], df_0[31:31], rg_0r);
AND2 I456 (rd_1r0[0:0], df_0[0:0], rg_1r);
AND2 I457 (rd_1r0[1:1], df_0[1:1], rg_1r);
AND2 I458 (rd_1r0[2:2], df_0[2:2], rg_1r);
AND2 I459 (rd_1r0[3:3], df_0[3:3], rg_1r);
AND2 I460 (rd_1r0[4:4], df_0[4:4], rg_1r);
AND2 I461 (rd_1r0[5:5], df_0[5:5], rg_1r);
AND2 I462 (rd_1r0[6:6], df_0[6:6], rg_1r);
AND2 I463 (rd_1r0[7:7], df_0[7:7], rg_1r);
AND2 I464 (rd_1r0[8:8], df_0[8:8], rg_1r);
AND2 I465 (rd_1r0[9:9], df_0[9:9], rg_1r);
AND2 I466 (rd_1r0[10:10], df_0[10:10], rg_1r);
AND2 I467 (rd_1r0[11:11], df_0[11:11], rg_1r);
AND2 I468 (rd_1r0[12:12], df_0[12:12], rg_1r);
AND2 I469 (rd_1r0[13:13], df_0[13:13], rg_1r);
AND2 I470 (rd_1r0[14:14], df_0[14:14], rg_1r);
AND2 I471 (rd_1r0[15:15], df_0[15:15], rg_1r);
AND2 I472 (rd_1r0[16:16], df_0[16:16], rg_1r);
AND2 I473 (rd_1r0[17:17], df_0[17:17], rg_1r);
AND2 I474 (rd_1r0[18:18], df_0[18:18], rg_1r);
AND2 I475 (rd_1r0[19:19], df_0[19:19], rg_1r);
AND2 I476 (rd_1r0[20:20], df_0[20:20], rg_1r);
AND2 I477 (rd_1r0[21:21], df_0[21:21], rg_1r);
AND2 I478 (rd_1r0[22:22], df_0[22:22], rg_1r);
AND2 I479 (rd_1r0[23:23], df_0[23:23], rg_1r);
AND2 I480 (rd_1r0[24:24], df_0[24:24], rg_1r);
AND2 I481 (rd_1r0[25:25], df_0[25:25], rg_1r);
AND2 I482 (rd_1r0[26:26], df_0[26:26], rg_1r);
AND2 I483 (rd_1r0[27:27], df_0[27:27], rg_1r);
AND2 I484 (rd_1r0[28:28], df_0[28:28], rg_1r);
AND2 I485 (rd_1r0[29:29], df_0[29:29], rg_1r);
AND2 I486 (rd_1r0[30:30], df_0[30:30], rg_1r);
AND2 I487 (rd_2r0[0:0], df_0[1:1], rg_2r);
AND2 I488 (rd_2r0[1:1], df_0[2:2], rg_2r);
AND2 I489 (rd_2r0[2:2], df_0[3:3], rg_2r);
AND2 I490 (rd_2r0[3:3], df_0[4:4], rg_2r);
AND2 I491 (rd_2r0[4:4], df_0[5:5], rg_2r);
AND2 I492 (rd_2r0[5:5], df_0[6:6], rg_2r);
AND2 I493 (rd_2r0[6:6], df_0[7:7], rg_2r);
AND2 I494 (rd_2r0[7:7], df_0[8:8], rg_2r);
AND2 I495 (rd_2r0[8:8], df_0[9:9], rg_2r);
AND2 I496 (rd_2r0[9:9], df_0[10:10], rg_2r);
AND2 I497 (rd_2r0[10:10], df_0[11:11], rg_2r);
AND2 I498 (rd_2r0[11:11], df_0[12:12], rg_2r);
AND2 I499 (rd_2r0[12:12], df_0[13:13], rg_2r);
AND2 I500 (rd_2r0[13:13], df_0[14:14], rg_2r);
AND2 I501 (rd_2r0[14:14], df_0[15:15], rg_2r);
AND2 I502 (rd_2r0[15:15], df_0[16:16], rg_2r);
AND2 I503 (rd_2r0[16:16], df_0[17:17], rg_2r);
AND2 I504 (rd_2r0[17:17], df_0[18:18], rg_2r);
AND2 I505 (rd_2r0[18:18], df_0[19:19], rg_2r);
AND2 I506 (rd_2r0[19:19], df_0[20:20], rg_2r);
AND2 I507 (rd_2r0[20:20], df_0[21:21], rg_2r);
AND2 I508 (rd_2r0[21:21], df_0[22:22], rg_2r);
AND2 I509 (rd_2r0[22:22], df_0[23:23], rg_2r);
AND2 I510 (rd_2r0[23:23], df_0[24:24], rg_2r);
AND2 I511 (rd_2r0[24:24], df_0[25:25], rg_2r);
AND2 I512 (rd_2r0[25:25], df_0[26:26], rg_2r);
AND2 I513 (rd_2r0[26:26], df_0[27:27], rg_2r);
AND2 I514 (rd_2r0[27:27], df_0[28:28], rg_2r);
AND2 I515 (rd_2r0[28:28], df_0[29:29], rg_2r);
AND2 I516 (rd_2r0[29:29], df_0[30:30], rg_2r);
AND2 I517 (rd_2r0[30:30], df_0[31:31], rg_2r);
AND2 I518 (rd_3r0[0:0], df_0[1:1], rg_3r);
AND2 I519 (rd_3r0[1:1], df_0[2:2], rg_3r);
AND2 I520 (rd_3r0[2:2], df_0[3:3], rg_3r);
AND2 I521 (rd_3r0[3:3], df_0[4:4], rg_3r);
AND2 I522 (rd_3r0[4:4], df_0[5:5], rg_3r);
AND2 I523 (rd_3r0[5:5], df_0[6:6], rg_3r);
AND2 I524 (rd_3r0[6:6], df_0[7:7], rg_3r);
AND2 I525 (rd_3r0[7:7], df_0[8:8], rg_3r);
AND2 I526 (rd_3r0[8:8], df_0[9:9], rg_3r);
AND2 I527 (rd_3r0[9:9], df_0[10:10], rg_3r);
AND2 I528 (rd_3r0[10:10], df_0[11:11], rg_3r);
AND2 I529 (rd_3r0[11:11], df_0[12:12], rg_3r);
AND2 I530 (rd_3r0[12:12], df_0[13:13], rg_3r);
AND2 I531 (rd_3r0[13:13], df_0[14:14], rg_3r);
AND2 I532 (rd_3r0[14:14], df_0[15:15], rg_3r);
AND2 I533 (rd_3r0[15:15], df_0[16:16], rg_3r);
AND2 I534 (rd_3r0[16:16], df_0[17:17], rg_3r);
AND2 I535 (rd_3r0[17:17], df_0[18:18], rg_3r);
AND2 I536 (rd_3r0[18:18], df_0[19:19], rg_3r);
AND2 I537 (rd_3r0[19:19], df_0[20:20], rg_3r);
AND2 I538 (rd_3r0[20:20], df_0[21:21], rg_3r);
AND2 I539 (rd_3r0[21:21], df_0[22:22], rg_3r);
AND2 I540 (rd_3r0[22:22], df_0[23:23], rg_3r);
AND2 I541 (rd_3r0[23:23], df_0[24:24], rg_3r);
AND2 I542 (rd_3r0[24:24], df_0[25:25], rg_3r);
AND2 I543 (rd_3r0[25:25], df_0[26:26], rg_3r);
AND2 I544 (rd_3r0[26:26], df_0[27:27], rg_3r);
AND2 I545 (rd_3r0[27:27], df_0[28:28], rg_3r);
AND2 I546 (rd_3r0[28:28], df_0[29:29], rg_3r);
AND2 I547 (rd_3r0[29:29], df_0[30:30], rg_3r);
AND2 I548 (rd_3r0[30:30], df_0[31:31], rg_3r);
AND2 I549 (rd_0r1[0:0], dt_0[0:0], rg_0r);
AND2 I550 (rd_0r1[1:1], dt_0[1:1], rg_0r);
AND2 I551 (rd_0r1[2:2], dt_0[2:2], rg_0r);
AND2 I552 (rd_0r1[3:3], dt_0[3:3], rg_0r);
AND2 I553 (rd_0r1[4:4], dt_0[4:4], rg_0r);
AND2 I554 (rd_0r1[5:5], dt_0[5:5], rg_0r);
AND2 I555 (rd_0r1[6:6], dt_0[6:6], rg_0r);
AND2 I556 (rd_0r1[7:7], dt_0[7:7], rg_0r);
AND2 I557 (rd_0r1[8:8], dt_0[8:8], rg_0r);
AND2 I558 (rd_0r1[9:9], dt_0[9:9], rg_0r);
AND2 I559 (rd_0r1[10:10], dt_0[10:10], rg_0r);
AND2 I560 (rd_0r1[11:11], dt_0[11:11], rg_0r);
AND2 I561 (rd_0r1[12:12], dt_0[12:12], rg_0r);
AND2 I562 (rd_0r1[13:13], dt_0[13:13], rg_0r);
AND2 I563 (rd_0r1[14:14], dt_0[14:14], rg_0r);
AND2 I564 (rd_0r1[15:15], dt_0[15:15], rg_0r);
AND2 I565 (rd_0r1[16:16], dt_0[16:16], rg_0r);
AND2 I566 (rd_0r1[17:17], dt_0[17:17], rg_0r);
AND2 I567 (rd_0r1[18:18], dt_0[18:18], rg_0r);
AND2 I568 (rd_0r1[19:19], dt_0[19:19], rg_0r);
AND2 I569 (rd_0r1[20:20], dt_0[20:20], rg_0r);
AND2 I570 (rd_0r1[21:21], dt_0[21:21], rg_0r);
AND2 I571 (rd_0r1[22:22], dt_0[22:22], rg_0r);
AND2 I572 (rd_0r1[23:23], dt_0[23:23], rg_0r);
AND2 I573 (rd_0r1[24:24], dt_0[24:24], rg_0r);
AND2 I574 (rd_0r1[25:25], dt_0[25:25], rg_0r);
AND2 I575 (rd_0r1[26:26], dt_0[26:26], rg_0r);
AND2 I576 (rd_0r1[27:27], dt_0[27:27], rg_0r);
AND2 I577 (rd_0r1[28:28], dt_0[28:28], rg_0r);
AND2 I578 (rd_0r1[29:29], dt_0[29:29], rg_0r);
AND2 I579 (rd_0r1[30:30], dt_0[30:30], rg_0r);
AND2 I580 (rd_0r1[31:31], dt_0[31:31], rg_0r);
AND2 I581 (rd_1r1[0:0], dt_0[0:0], rg_1r);
AND2 I582 (rd_1r1[1:1], dt_0[1:1], rg_1r);
AND2 I583 (rd_1r1[2:2], dt_0[2:2], rg_1r);
AND2 I584 (rd_1r1[3:3], dt_0[3:3], rg_1r);
AND2 I585 (rd_1r1[4:4], dt_0[4:4], rg_1r);
AND2 I586 (rd_1r1[5:5], dt_0[5:5], rg_1r);
AND2 I587 (rd_1r1[6:6], dt_0[6:6], rg_1r);
AND2 I588 (rd_1r1[7:7], dt_0[7:7], rg_1r);
AND2 I589 (rd_1r1[8:8], dt_0[8:8], rg_1r);
AND2 I590 (rd_1r1[9:9], dt_0[9:9], rg_1r);
AND2 I591 (rd_1r1[10:10], dt_0[10:10], rg_1r);
AND2 I592 (rd_1r1[11:11], dt_0[11:11], rg_1r);
AND2 I593 (rd_1r1[12:12], dt_0[12:12], rg_1r);
AND2 I594 (rd_1r1[13:13], dt_0[13:13], rg_1r);
AND2 I595 (rd_1r1[14:14], dt_0[14:14], rg_1r);
AND2 I596 (rd_1r1[15:15], dt_0[15:15], rg_1r);
AND2 I597 (rd_1r1[16:16], dt_0[16:16], rg_1r);
AND2 I598 (rd_1r1[17:17], dt_0[17:17], rg_1r);
AND2 I599 (rd_1r1[18:18], dt_0[18:18], rg_1r);
AND2 I600 (rd_1r1[19:19], dt_0[19:19], rg_1r);
AND2 I601 (rd_1r1[20:20], dt_0[20:20], rg_1r);
AND2 I602 (rd_1r1[21:21], dt_0[21:21], rg_1r);
AND2 I603 (rd_1r1[22:22], dt_0[22:22], rg_1r);
AND2 I604 (rd_1r1[23:23], dt_0[23:23], rg_1r);
AND2 I605 (rd_1r1[24:24], dt_0[24:24], rg_1r);
AND2 I606 (rd_1r1[25:25], dt_0[25:25], rg_1r);
AND2 I607 (rd_1r1[26:26], dt_0[26:26], rg_1r);
AND2 I608 (rd_1r1[27:27], dt_0[27:27], rg_1r);
AND2 I609 (rd_1r1[28:28], dt_0[28:28], rg_1r);
AND2 I610 (rd_1r1[29:29], dt_0[29:29], rg_1r);
AND2 I611 (rd_1r1[30:30], dt_0[30:30], rg_1r);
AND2 I612 (rd_2r1[0:0], dt_0[1:1], rg_2r);
AND2 I613 (rd_2r1[1:1], dt_0[2:2], rg_2r);
AND2 I614 (rd_2r1[2:2], dt_0[3:3], rg_2r);
AND2 I615 (rd_2r1[3:3], dt_0[4:4], rg_2r);
AND2 I616 (rd_2r1[4:4], dt_0[5:5], rg_2r);
AND2 I617 (rd_2r1[5:5], dt_0[6:6], rg_2r);
AND2 I618 (rd_2r1[6:6], dt_0[7:7], rg_2r);
AND2 I619 (rd_2r1[7:7], dt_0[8:8], rg_2r);
AND2 I620 (rd_2r1[8:8], dt_0[9:9], rg_2r);
AND2 I621 (rd_2r1[9:9], dt_0[10:10], rg_2r);
AND2 I622 (rd_2r1[10:10], dt_0[11:11], rg_2r);
AND2 I623 (rd_2r1[11:11], dt_0[12:12], rg_2r);
AND2 I624 (rd_2r1[12:12], dt_0[13:13], rg_2r);
AND2 I625 (rd_2r1[13:13], dt_0[14:14], rg_2r);
AND2 I626 (rd_2r1[14:14], dt_0[15:15], rg_2r);
AND2 I627 (rd_2r1[15:15], dt_0[16:16], rg_2r);
AND2 I628 (rd_2r1[16:16], dt_0[17:17], rg_2r);
AND2 I629 (rd_2r1[17:17], dt_0[18:18], rg_2r);
AND2 I630 (rd_2r1[18:18], dt_0[19:19], rg_2r);
AND2 I631 (rd_2r1[19:19], dt_0[20:20], rg_2r);
AND2 I632 (rd_2r1[20:20], dt_0[21:21], rg_2r);
AND2 I633 (rd_2r1[21:21], dt_0[22:22], rg_2r);
AND2 I634 (rd_2r1[22:22], dt_0[23:23], rg_2r);
AND2 I635 (rd_2r1[23:23], dt_0[24:24], rg_2r);
AND2 I636 (rd_2r1[24:24], dt_0[25:25], rg_2r);
AND2 I637 (rd_2r1[25:25], dt_0[26:26], rg_2r);
AND2 I638 (rd_2r1[26:26], dt_0[27:27], rg_2r);
AND2 I639 (rd_2r1[27:27], dt_0[28:28], rg_2r);
AND2 I640 (rd_2r1[28:28], dt_0[29:29], rg_2r);
AND2 I641 (rd_2r1[29:29], dt_0[30:30], rg_2r);
AND2 I642 (rd_2r1[30:30], dt_0[31:31], rg_2r);
AND2 I643 (rd_3r1[0:0], dt_0[1:1], rg_3r);
AND2 I644 (rd_3r1[1:1], dt_0[2:2], rg_3r);
AND2 I645 (rd_3r1[2:2], dt_0[3:3], rg_3r);
AND2 I646 (rd_3r1[3:3], dt_0[4:4], rg_3r);
AND2 I647 (rd_3r1[4:4], dt_0[5:5], rg_3r);
AND2 I648 (rd_3r1[5:5], dt_0[6:6], rg_3r);
AND2 I649 (rd_3r1[6:6], dt_0[7:7], rg_3r);
AND2 I650 (rd_3r1[7:7], dt_0[8:8], rg_3r);
AND2 I651 (rd_3r1[8:8], dt_0[9:9], rg_3r);
AND2 I652 (rd_3r1[9:9], dt_0[10:10], rg_3r);
AND2 I653 (rd_3r1[10:10], dt_0[11:11], rg_3r);
AND2 I654 (rd_3r1[11:11], dt_0[12:12], rg_3r);
AND2 I655 (rd_3r1[12:12], dt_0[13:13], rg_3r);
AND2 I656 (rd_3r1[13:13], dt_0[14:14], rg_3r);
AND2 I657 (rd_3r1[14:14], dt_0[15:15], rg_3r);
AND2 I658 (rd_3r1[15:15], dt_0[16:16], rg_3r);
AND2 I659 (rd_3r1[16:16], dt_0[17:17], rg_3r);
AND2 I660 (rd_3r1[17:17], dt_0[18:18], rg_3r);
AND2 I661 (rd_3r1[18:18], dt_0[19:19], rg_3r);
AND2 I662 (rd_3r1[19:19], dt_0[20:20], rg_3r);
AND2 I663 (rd_3r1[20:20], dt_0[21:21], rg_3r);
AND2 I664 (rd_3r1[21:21], dt_0[22:22], rg_3r);
AND2 I665 (rd_3r1[22:22], dt_0[23:23], rg_3r);
AND2 I666 (rd_3r1[23:23], dt_0[24:24], rg_3r);
AND2 I667 (rd_3r1[24:24], dt_0[25:25], rg_3r);
AND2 I668 (rd_3r1[25:25], dt_0[26:26], rg_3r);
AND2 I669 (rd_3r1[26:26], dt_0[27:27], rg_3r);
AND2 I670 (rd_3r1[27:27], dt_0[28:28], rg_3r);
AND2 I671 (rd_3r1[28:28], dt_0[29:29], rg_3r);
AND2 I672 (rd_3r1[29:29], dt_0[30:30], rg_3r);
AND2 I673 (rd_3r1[30:30], dt_0[31:31], rg_3r);
NOR3 I674 (simp6581_0[0:0], rg_0r, rg_1r, rg_2r);
NOR3 I675 (simp6581_0[1:1], rg_3r, rg_0a, rg_1a);
NOR2 I676 (simp6581_0[2:2], rg_2a, rg_3a);
NAND3 I677 (anyread_0, simp6581_0[0:0], simp6581_0[1:1], simp6581_0[2:2]);
BUFF I678 (wg_0a, wd_0a);
BUFF I679 (rg_0a, rd_0a);
BUFF I680 (rg_1a, rd_1a);
BUFF I681 (rg_2a, rd_2a);
BUFF I682 (rg_3a, rd_3a);
endmodule
// tko30m32_1nm2b0_2apt1o0w2bi0w30b TeakO [
// (1,TeakOConstant 2 0),
// (2,TeakOAppend 1 [(1,0+:2),(0,0+:30)])] [One 30,One 32]
module tko30m32_1nm2b0_2apt1o0w2bi0w30b (i_0r0, i_0r1, i_0a, o_0r0, o_0r1, o_0a, reset);
input [29:0] i_0r0;
input [29:0] i_0r1;
output i_0a;
output [31:0] o_0r0;
output [31:0] o_0r1;
input o_0a;
input reset;
wire go_0;
wire [29:0] gocomp_0;
wire [9:0] simp321_0;
wire [3:0] simp322_0;
wire [1:0] simp323_0;
wire [1:0] termf_1;
wire [1:0] termt_1;
OR2 I0 (gocomp_0[0:0], i_0r0[0:0], i_0r1[0:0]);
OR2 I1 (gocomp_0[1:1], i_0r0[1:1], i_0r1[1:1]);
OR2 I2 (gocomp_0[2:2], i_0r0[2:2], i_0r1[2:2]);
OR2 I3 (gocomp_0[3:3], i_0r0[3:3], i_0r1[3:3]);
OR2 I4 (gocomp_0[4:4], i_0r0[4:4], i_0r1[4:4]);
OR2 I5 (gocomp_0[5:5], i_0r0[5:5], i_0r1[5:5]);
OR2 I6 (gocomp_0[6:6], i_0r0[6:6], i_0r1[6:6]);
OR2 I7 (gocomp_0[7:7], i_0r0[7:7], i_0r1[7:7]);
OR2 I8 (gocomp_0[8:8], i_0r0[8:8], i_0r1[8:8]);
OR2 I9 (gocomp_0[9:9], i_0r0[9:9], i_0r1[9:9]);
OR2 I10 (gocomp_0[10:10], i_0r0[10:10], i_0r1[10:10]);
OR2 I11 (gocomp_0[11:11], i_0r0[11:11], i_0r1[11:11]);
OR2 I12 (gocomp_0[12:12], i_0r0[12:12], i_0r1[12:12]);
OR2 I13 (gocomp_0[13:13], i_0r0[13:13], i_0r1[13:13]);
OR2 I14 (gocomp_0[14:14], i_0r0[14:14], i_0r1[14:14]);
OR2 I15 (gocomp_0[15:15], i_0r0[15:15], i_0r1[15:15]);
OR2 I16 (gocomp_0[16:16], i_0r0[16:16], i_0r1[16:16]);
OR2 I17 (gocomp_0[17:17], i_0r0[17:17], i_0r1[17:17]);
OR2 I18 (gocomp_0[18:18], i_0r0[18:18], i_0r1[18:18]);
OR2 I19 (gocomp_0[19:19], i_0r0[19:19], i_0r1[19:19]);
OR2 I20 (gocomp_0[20:20], i_0r0[20:20], i_0r1[20:20]);
OR2 I21 (gocomp_0[21:21], i_0r0[21:21], i_0r1[21:21]);
OR2 I22 (gocomp_0[22:22], i_0r0[22:22], i_0r1[22:22]);
OR2 I23 (gocomp_0[23:23], i_0r0[23:23], i_0r1[23:23]);
OR2 I24 (gocomp_0[24:24], i_0r0[24:24], i_0r1[24:24]);
OR2 I25 (gocomp_0[25:25], i_0r0[25:25], i_0r1[25:25]);
OR2 I26 (gocomp_0[26:26], i_0r0[26:26], i_0r1[26:26]);
OR2 I27 (gocomp_0[27:27], i_0r0[27:27], i_0r1[27:27]);
OR2 I28 (gocomp_0[28:28], i_0r0[28:28], i_0r1[28:28]);
OR2 I29 (gocomp_0[29:29], i_0r0[29:29], i_0r1[29:29]);
C3 I30 (simp321_0[0:0], gocomp_0[0:0], gocomp_0[1:1], gocomp_0[2:2]);
C3 I31 (simp321_0[1:1], gocomp_0[3:3], gocomp_0[4:4], gocomp_0[5:5]);
C3 I32 (simp321_0[2:2], gocomp_0[6:6], gocomp_0[7:7], gocomp_0[8:8]);
C3 I33 (simp321_0[3:3], gocomp_0[9:9], gocomp_0[10:10], gocomp_0[11:11]);
C3 I34 (simp321_0[4:4], gocomp_0[12:12], gocomp_0[13:13], gocomp_0[14:14]);
C3 I35 (simp321_0[5:5], gocomp_0[15:15], gocomp_0[16:16], gocomp_0[17:17]);
C3 I36 (simp321_0[6:6], gocomp_0[18:18], gocomp_0[19:19], gocomp_0[20:20]);
C3 I37 (simp321_0[7:7], gocomp_0[21:21], gocomp_0[22:22], gocomp_0[23:23]);
C3 I38 (simp321_0[8:8], gocomp_0[24:24], gocomp_0[25:25], gocomp_0[26:26]);
C3 I39 (simp321_0[9:9], gocomp_0[27:27], gocomp_0[28:28], gocomp_0[29:29]);
C3 I40 (simp322_0[0:0], simp321_0[0:0], simp321_0[1:1], simp321_0[2:2]);
C3 I41 (simp322_0[1:1], simp321_0[3:3], simp321_0[4:4], simp321_0[5:5]);
C3 I42 (simp322_0[2:2], simp321_0[6:6], simp321_0[7:7], simp321_0[8:8]);
BUFF I43 (simp322_0[3:3], simp321_0[9:9]);
C3 I44 (simp323_0[0:0], simp322_0[0:0], simp322_0[1:1], simp322_0[2:2]);
BUFF I45 (simp323_0[1:1], simp322_0[3:3]);
C2 I46 (go_0, simp323_0[0:0], simp323_0[1:1]);
BUFF I47 (termf_1[0:0], go_0);
BUFF I48 (termf_1[1:1], go_0);
GND I49 (termt_1[0:0]);
GND I50 (termt_1[1:1]);
BUFF I51 (o_0r0[0:0], termf_1[0:0]);
BUFF I52 (o_0r0[1:1], termf_1[1:1]);
BUFF I53 (o_0r0[2:2], i_0r0[0:0]);
BUFF I54 (o_0r0[3:3], i_0r0[1:1]);
BUFF I55 (o_0r0[4:4], i_0r0[2:2]);
BUFF I56 (o_0r0[5:5], i_0r0[3:3]);
BUFF I57 (o_0r0[6:6], i_0r0[4:4]);
BUFF I58 (o_0r0[7:7], i_0r0[5:5]);
BUFF I59 (o_0r0[8:8], i_0r0[6:6]);
BUFF I60 (o_0r0[9:9], i_0r0[7:7]);
BUFF I61 (o_0r0[10:10], i_0r0[8:8]);
BUFF I62 (o_0r0[11:11], i_0r0[9:9]);
BUFF I63 (o_0r0[12:12], i_0r0[10:10]);
BUFF I64 (o_0r0[13:13], i_0r0[11:11]);
BUFF I65 (o_0r0[14:14], i_0r0[12:12]);
BUFF I66 (o_0r0[15:15], i_0r0[13:13]);
BUFF I67 (o_0r0[16:16], i_0r0[14:14]);
BUFF I68 (o_0r0[17:17], i_0r0[15:15]);
BUFF I69 (o_0r0[18:18], i_0r0[16:16]);
BUFF I70 (o_0r0[19:19], i_0r0[17:17]);
BUFF I71 (o_0r0[20:20], i_0r0[18:18]);
BUFF I72 (o_0r0[21:21], i_0r0[19:19]);
BUFF I73 (o_0r0[22:22], i_0r0[20:20]);
BUFF I74 (o_0r0[23:23], i_0r0[21:21]);
BUFF I75 (o_0r0[24:24], i_0r0[22:22]);
BUFF I76 (o_0r0[25:25], i_0r0[23:23]);
BUFF I77 (o_0r0[26:26], i_0r0[24:24]);
BUFF I78 (o_0r0[27:27], i_0r0[25:25]);
BUFF I79 (o_0r0[28:28], i_0r0[26:26]);
BUFF I80 (o_0r0[29:29], i_0r0[27:27]);
BUFF I81 (o_0r0[30:30], i_0r0[28:28]);
BUFF I82 (o_0r0[31:31], i_0r0[29:29]);
BUFF I83 (o_0r1[0:0], termt_1[0:0]);
BUFF I84 (o_0r1[1:1], termt_1[1:1]);
BUFF I85 (o_0r1[2:2], i_0r1[0:0]);
BUFF I86 (o_0r1[3:3], i_0r1[1:1]);
BUFF I87 (o_0r1[4:4], i_0r1[2:2]);
BUFF I88 (o_0r1[5:5], i_0r1[3:3]);
BUFF I89 (o_0r1[6:6], i_0r1[4:4]);
BUFF I90 (o_0r1[7:7], i_0r1[5:5]);
BUFF I91 (o_0r1[8:8], i_0r1[6:6]);
BUFF I92 (o_0r1[9:9], i_0r1[7:7]);
BUFF I93 (o_0r1[10:10], i_0r1[8:8]);
BUFF I94 (o_0r1[11:11], i_0r1[9:9]);
BUFF I95 (o_0r1[12:12], i_0r1[10:10]);
BUFF I96 (o_0r1[13:13], i_0r1[11:11]);
BUFF I97 (o_0r1[14:14], i_0r1[12:12]);
BUFF I98 (o_0r1[15:15], i_0r1[13:13]);
BUFF I99 (o_0r1[16:16], i_0r1[14:14]);
BUFF I100 (o_0r1[17:17], i_0r1[15:15]);
BUFF I101 (o_0r1[18:18], i_0r1[16:16]);
BUFF I102 (o_0r1[19:19], i_0r1[17:17]);
BUFF I103 (o_0r1[20:20], i_0r1[18:18]);
BUFF I104 (o_0r1[21:21], i_0r1[19:19]);
BUFF I105 (o_0r1[22:22], i_0r1[20:20]);
BUFF I106 (o_0r1[23:23], i_0r1[21:21]);
BUFF I107 (o_0r1[24:24], i_0r1[22:22]);
BUFF I108 (o_0r1[25:25], i_0r1[23:23]);
BUFF I109 (o_0r1[26:26], i_0r1[24:24]);
BUFF I110 (o_0r1[27:27], i_0r1[25:25]);
BUFF I111 (o_0r1[28:28], i_0r1[26:26]);
BUFF I112 (o_0r1[29:29], i_0r1[27:27]);
BUFF I113 (o_0r1[30:30], i_0r1[28:28]);
BUFF I114 (o_0r1[31:31], i_0r1[29:29]);
BUFF I115 (i_0a, o_0a);
endmodule
// tko30m32_1nm2b0_2api0w30bt1o0w2b TeakO [
// (1,TeakOConstant 2 0),
// (2,TeakOAppend 1 [(0,0+:30),(1,0+:2)])] [One 30,One 32]
module tko30m32_1nm2b0_2api0w30bt1o0w2b (i_0r0, i_0r1, i_0a, o_0r0, o_0r1, o_0a, reset);
input [29:0] i_0r0;
input [29:0] i_0r1;
output i_0a;
output [31:0] o_0r0;
output [31:0] o_0r1;
input o_0a;
input reset;
wire go_0;
wire [29:0] gocomp_0;
wire [9:0] simp321_0;
wire [3:0] simp322_0;
wire [1:0] simp323_0;
wire [1:0] termf_1;
wire [1:0] termt_1;
OR2 I0 (gocomp_0[0:0], i_0r0[0:0], i_0r1[0:0]);
OR2 I1 (gocomp_0[1:1], i_0r0[1:1], i_0r1[1:1]);
OR2 I2 (gocomp_0[2:2], i_0r0[2:2], i_0r1[2:2]);
OR2 I3 (gocomp_0[3:3], i_0r0[3:3], i_0r1[3:3]);
OR2 I4 (gocomp_0[4:4], i_0r0[4:4], i_0r1[4:4]);
OR2 I5 (gocomp_0[5:5], i_0r0[5:5], i_0r1[5:5]);
OR2 I6 (gocomp_0[6:6], i_0r0[6:6], i_0r1[6:6]);
OR2 I7 (gocomp_0[7:7], i_0r0[7:7], i_0r1[7:7]);
OR2 I8 (gocomp_0[8:8], i_0r0[8:8], i_0r1[8:8]);
OR2 I9 (gocomp_0[9:9], i_0r0[9:9], i_0r1[9:9]);
OR2 I10 (gocomp_0[10:10], i_0r0[10:10], i_0r1[10:10]);
OR2 I11 (gocomp_0[11:11], i_0r0[11:11], i_0r1[11:11]);
OR2 I12 (gocomp_0[12:12], i_0r0[12:12], i_0r1[12:12]);
OR2 I13 (gocomp_0[13:13], i_0r0[13:13], i_0r1[13:13]);
OR2 I14 (gocomp_0[14:14], i_0r0[14:14], i_0r1[14:14]);
OR2 I15 (gocomp_0[15:15], i_0r0[15:15], i_0r1[15:15]);
OR2 I16 (gocomp_0[16:16], i_0r0[16:16], i_0r1[16:16]);
OR2 I17 (gocomp_0[17:17], i_0r0[17:17], i_0r1[17:17]);
OR2 I18 (gocomp_0[18:18], i_0r0[18:18], i_0r1[18:18]);
OR2 I19 (gocomp_0[19:19], i_0r0[19:19], i_0r1[19:19]);
OR2 I20 (gocomp_0[20:20], i_0r0[20:20], i_0r1[20:20]);
OR2 I21 (gocomp_0[21:21], i_0r0[21:21], i_0r1[21:21]);
OR2 I22 (gocomp_0[22:22], i_0r0[22:22], i_0r1[22:22]);
OR2 I23 (gocomp_0[23:23], i_0r0[23:23], i_0r1[23:23]);
OR2 I24 (gocomp_0[24:24], i_0r0[24:24], i_0r1[24:24]);
OR2 I25 (gocomp_0[25:25], i_0r0[25:25], i_0r1[25:25]);
OR2 I26 (gocomp_0[26:26], i_0r0[26:26], i_0r1[26:26]);
OR2 I27 (gocomp_0[27:27], i_0r0[27:27], i_0r1[27:27]);
OR2 I28 (gocomp_0[28:28], i_0r0[28:28], i_0r1[28:28]);
OR2 I29 (gocomp_0[29:29], i_0r0[29:29], i_0r1[29:29]);
C3 I30 (simp321_0[0:0], gocomp_0[0:0], gocomp_0[1:1], gocomp_0[2:2]);
C3 I31 (simp321_0[1:1], gocomp_0[3:3], gocomp_0[4:4], gocomp_0[5:5]);
C3 I32 (simp321_0[2:2], gocomp_0[6:6], gocomp_0[7:7], gocomp_0[8:8]);
C3 I33 (simp321_0[3:3], gocomp_0[9:9], gocomp_0[10:10], gocomp_0[11:11]);
C3 I34 (simp321_0[4:4], gocomp_0[12:12], gocomp_0[13:13], gocomp_0[14:14]);
C3 I35 (simp321_0[5:5], gocomp_0[15:15], gocomp_0[16:16], gocomp_0[17:17]);
C3 I36 (simp321_0[6:6], gocomp_0[18:18], gocomp_0[19:19], gocomp_0[20:20]);
C3 I37 (simp321_0[7:7], gocomp_0[21:21], gocomp_0[22:22], gocomp_0[23:23]);
C3 I38 (simp321_0[8:8], gocomp_0[24:24], gocomp_0[25:25], gocomp_0[26:26]);
C3 I39 (simp321_0[9:9], gocomp_0[27:27], gocomp_0[28:28], gocomp_0[29:29]);
C3 I40 (simp322_0[0:0], simp321_0[0:0], simp321_0[1:1], simp321_0[2:2]);
C3 I41 (simp322_0[1:1], simp321_0[3:3], simp321_0[4:4], simp321_0[5:5]);
C3 I42 (simp322_0[2:2], simp321_0[6:6], simp321_0[7:7], simp321_0[8:8]);
BUFF I43 (simp322_0[3:3], simp321_0[9:9]);
C3 I44 (simp323_0[0:0], simp322_0[0:0], simp322_0[1:1], simp322_0[2:2]);
BUFF I45 (simp323_0[1:1], simp322_0[3:3]);
C2 I46 (go_0, simp323_0[0:0], simp323_0[1:1]);
BUFF I47 (termf_1[0:0], go_0);
BUFF I48 (termf_1[1:1], go_0);
GND I49 (termt_1[0:0]);
GND I50 (termt_1[1:1]);
BUFF I51 (o_0r0[0:0], i_0r0[0:0]);
BUFF I52 (o_0r0[1:1], i_0r0[1:1]);
BUFF I53 (o_0r0[2:2], i_0r0[2:2]);
BUFF I54 (o_0r0[3:3], i_0r0[3:3]);
BUFF I55 (o_0r0[4:4], i_0r0[4:4]);
BUFF I56 (o_0r0[5:5], i_0r0[5:5]);
BUFF I57 (o_0r0[6:6], i_0r0[6:6]);
BUFF I58 (o_0r0[7:7], i_0r0[7:7]);
BUFF I59 (o_0r0[8:8], i_0r0[8:8]);
BUFF I60 (o_0r0[9:9], i_0r0[9:9]);
BUFF I61 (o_0r0[10:10], i_0r0[10:10]);
BUFF I62 (o_0r0[11:11], i_0r0[11:11]);
BUFF I63 (o_0r0[12:12], i_0r0[12:12]);
BUFF I64 (o_0r0[13:13], i_0r0[13:13]);
BUFF I65 (o_0r0[14:14], i_0r0[14:14]);
BUFF I66 (o_0r0[15:15], i_0r0[15:15]);
BUFF I67 (o_0r0[16:16], i_0r0[16:16]);
BUFF I68 (o_0r0[17:17], i_0r0[17:17]);
BUFF I69 (o_0r0[18:18], i_0r0[18:18]);
BUFF I70 (o_0r0[19:19], i_0r0[19:19]);
BUFF I71 (o_0r0[20:20], i_0r0[20:20]);
BUFF I72 (o_0r0[21:21], i_0r0[21:21]);
BUFF I73 (o_0r0[22:22], i_0r0[22:22]);
BUFF I74 (o_0r0[23:23], i_0r0[23:23]);
BUFF I75 (o_0r0[24:24], i_0r0[24:24]);
BUFF I76 (o_0r0[25:25], i_0r0[25:25]);
BUFF I77 (o_0r0[26:26], i_0r0[26:26]);
BUFF I78 (o_0r0[27:27], i_0r0[27:27]);
BUFF I79 (o_0r0[28:28], i_0r0[28:28]);
BUFF I80 (o_0r0[29:29], i_0r0[29:29]);
BUFF I81 (o_0r0[30:30], termf_1[0:0]);
BUFF I82 (o_0r0[31:31], termf_1[1:1]);
BUFF I83 (o_0r1[0:0], i_0r1[0:0]);
BUFF I84 (o_0r1[1:1], i_0r1[1:1]);
BUFF I85 (o_0r1[2:2], i_0r1[2:2]);
BUFF I86 (o_0r1[3:3], i_0r1[3:3]);
BUFF I87 (o_0r1[4:4], i_0r1[4:4]);
BUFF I88 (o_0r1[5:5], i_0r1[5:5]);
BUFF I89 (o_0r1[6:6], i_0r1[6:6]);
BUFF I90 (o_0r1[7:7], i_0r1[7:7]);
BUFF I91 (o_0r1[8:8], i_0r1[8:8]);
BUFF I92 (o_0r1[9:9], i_0r1[9:9]);
BUFF I93 (o_0r1[10:10], i_0r1[10:10]);
BUFF I94 (o_0r1[11:11], i_0r1[11:11]);
BUFF I95 (o_0r1[12:12], i_0r1[12:12]);
BUFF I96 (o_0r1[13:13], i_0r1[13:13]);
BUFF I97 (o_0r1[14:14], i_0r1[14:14]);
BUFF I98 (o_0r1[15:15], i_0r1[15:15]);
BUFF I99 (o_0r1[16:16], i_0r1[16:16]);
BUFF I100 (o_0r1[17:17], i_0r1[17:17]);
BUFF I101 (o_0r1[18:18], i_0r1[18:18]);
BUFF I102 (o_0r1[19:19], i_0r1[19:19]);
BUFF I103 (o_0r1[20:20], i_0r1[20:20]);
BUFF I104 (o_0r1[21:21], i_0r1[21:21]);
BUFF I105 (o_0r1[22:22], i_0r1[22:22]);
BUFF I106 (o_0r1[23:23], i_0r1[23:23]);
BUFF I107 (o_0r1[24:24], i_0r1[24:24]);
BUFF I108 (o_0r1[25:25], i_0r1[25:25]);
BUFF I109 (o_0r1[26:26], i_0r1[26:26]);
BUFF I110 (o_0r1[27:27], i_0r1[27:27]);
BUFF I111 (o_0r1[28:28], i_0r1[28:28]);
BUFF I112 (o_0r1[29:29], i_0r1[29:29]);
BUFF I113 (o_0r1[30:30], termt_1[0:0]);
BUFF I114 (o_0r1[31:31], termt_1[1:1]);
BUFF I115 (i_0a, o_0a);
endmodule
// tko30m32_1nm2b3_2api0w30bt1o0w2b TeakO [
// (1,TeakOConstant 2 3),
// (2,TeakOAppend 1 [(0,0+:30),(1,0+:2)])] [One 30,One 32]
module tko30m32_1nm2b3_2api0w30bt1o0w2b (i_0r0, i_0r1, i_0a, o_0r0, o_0r1, o_0a, reset);
input [29:0] i_0r0;
input [29:0] i_0r1;
output i_0a;
output [31:0] o_0r0;
output [31:0] o_0r1;
input o_0a;
input reset;
wire go_0;
wire [29:0] gocomp_0;
wire [9:0] simp321_0;
wire [3:0] simp322_0;
wire [1:0] simp323_0;
wire [1:0] termf_1;
wire [1:0] termt_1;
OR2 I0 (gocomp_0[0:0], i_0r0[0:0], i_0r1[0:0]);
OR2 I1 (gocomp_0[1:1], i_0r0[1:1], i_0r1[1:1]);
OR2 I2 (gocomp_0[2:2], i_0r0[2:2], i_0r1[2:2]);
OR2 I3 (gocomp_0[3:3], i_0r0[3:3], i_0r1[3:3]);
OR2 I4 (gocomp_0[4:4], i_0r0[4:4], i_0r1[4:4]);
OR2 I5 (gocomp_0[5:5], i_0r0[5:5], i_0r1[5:5]);
OR2 I6 (gocomp_0[6:6], i_0r0[6:6], i_0r1[6:6]);
OR2 I7 (gocomp_0[7:7], i_0r0[7:7], i_0r1[7:7]);
OR2 I8 (gocomp_0[8:8], i_0r0[8:8], i_0r1[8:8]);
OR2 I9 (gocomp_0[9:9], i_0r0[9:9], i_0r1[9:9]);
OR2 I10 (gocomp_0[10:10], i_0r0[10:10], i_0r1[10:10]);
OR2 I11 (gocomp_0[11:11], i_0r0[11:11], i_0r1[11:11]);
OR2 I12 (gocomp_0[12:12], i_0r0[12:12], i_0r1[12:12]);
OR2 I13 (gocomp_0[13:13], i_0r0[13:13], i_0r1[13:13]);
OR2 I14 (gocomp_0[14:14], i_0r0[14:14], i_0r1[14:14]);
OR2 I15 (gocomp_0[15:15], i_0r0[15:15], i_0r1[15:15]);
OR2 I16 (gocomp_0[16:16], i_0r0[16:16], i_0r1[16:16]);
OR2 I17 (gocomp_0[17:17], i_0r0[17:17], i_0r1[17:17]);
OR2 I18 (gocomp_0[18:18], i_0r0[18:18], i_0r1[18:18]);
OR2 I19 (gocomp_0[19:19], i_0r0[19:19], i_0r1[19:19]);
OR2 I20 (gocomp_0[20:20], i_0r0[20:20], i_0r1[20:20]);
OR2 I21 (gocomp_0[21:21], i_0r0[21:21], i_0r1[21:21]);
OR2 I22 (gocomp_0[22:22], i_0r0[22:22], i_0r1[22:22]);
OR2 I23 (gocomp_0[23:23], i_0r0[23:23], i_0r1[23:23]);
OR2 I24 (gocomp_0[24:24], i_0r0[24:24], i_0r1[24:24]);
OR2 I25 (gocomp_0[25:25], i_0r0[25:25], i_0r1[25:25]);
OR2 I26 (gocomp_0[26:26], i_0r0[26:26], i_0r1[26:26]);
OR2 I27 (gocomp_0[27:27], i_0r0[27:27], i_0r1[27:27]);
OR2 I28 (gocomp_0[28:28], i_0r0[28:28], i_0r1[28:28]);
OR2 I29 (gocomp_0[29:29], i_0r0[29:29], i_0r1[29:29]);
C3 I30 (simp321_0[0:0], gocomp_0[0:0], gocomp_0[1:1], gocomp_0[2:2]);
C3 I31 (simp321_0[1:1], gocomp_0[3:3], gocomp_0[4:4], gocomp_0[5:5]);
C3 I32 (simp321_0[2:2], gocomp_0[6:6], gocomp_0[7:7], gocomp_0[8:8]);
C3 I33 (simp321_0[3:3], gocomp_0[9:9], gocomp_0[10:10], gocomp_0[11:11]);
C3 I34 (simp321_0[4:4], gocomp_0[12:12], gocomp_0[13:13], gocomp_0[14:14]);
C3 I35 (simp321_0[5:5], gocomp_0[15:15], gocomp_0[16:16], gocomp_0[17:17]);
C3 I36 (simp321_0[6:6], gocomp_0[18:18], gocomp_0[19:19], gocomp_0[20:20]);
C3 I37 (simp321_0[7:7], gocomp_0[21:21], gocomp_0[22:22], gocomp_0[23:23]);
C3 I38 (simp321_0[8:8], gocomp_0[24:24], gocomp_0[25:25], gocomp_0[26:26]);
C3 I39 (simp321_0[9:9], gocomp_0[27:27], gocomp_0[28:28], gocomp_0[29:29]);
C3 I40 (simp322_0[0:0], simp321_0[0:0], simp321_0[1:1], simp321_0[2:2]);
C3 I41 (simp322_0[1:1], simp321_0[3:3], simp321_0[4:4], simp321_0[5:5]);
C3 I42 (simp322_0[2:2], simp321_0[6:6], simp321_0[7:7], simp321_0[8:8]);
BUFF I43 (simp322_0[3:3], simp321_0[9:9]);
C3 I44 (simp323_0[0:0], simp322_0[0:0], simp322_0[1:1], simp322_0[2:2]);
BUFF I45 (simp323_0[1:1], simp322_0[3:3]);
C2 I46 (go_0, simp323_0[0:0], simp323_0[1:1]);
BUFF I47 (termt_1[0:0], go_0);
BUFF I48 (termt_1[1:1], go_0);
GND I49 (termf_1[0:0]);
GND I50 (termf_1[1:1]);
BUFF I51 (o_0r0[0:0], i_0r0[0:0]);
BUFF I52 (o_0r0[1:1], i_0r0[1:1]);
BUFF I53 (o_0r0[2:2], i_0r0[2:2]);
BUFF I54 (o_0r0[3:3], i_0r0[3:3]);
BUFF I55 (o_0r0[4:4], i_0r0[4:4]);
BUFF I56 (o_0r0[5:5], i_0r0[5:5]);
BUFF I57 (o_0r0[6:6], i_0r0[6:6]);
BUFF I58 (o_0r0[7:7], i_0r0[7:7]);
BUFF I59 (o_0r0[8:8], i_0r0[8:8]);
BUFF I60 (o_0r0[9:9], i_0r0[9:9]);
BUFF I61 (o_0r0[10:10], i_0r0[10:10]);
BUFF I62 (o_0r0[11:11], i_0r0[11:11]);
BUFF I63 (o_0r0[12:12], i_0r0[12:12]);
BUFF I64 (o_0r0[13:13], i_0r0[13:13]);
BUFF I65 (o_0r0[14:14], i_0r0[14:14]);
BUFF I66 (o_0r0[15:15], i_0r0[15:15]);
BUFF I67 (o_0r0[16:16], i_0r0[16:16]);
BUFF I68 (o_0r0[17:17], i_0r0[17:17]);
BUFF I69 (o_0r0[18:18], i_0r0[18:18]);
BUFF I70 (o_0r0[19:19], i_0r0[19:19]);
BUFF I71 (o_0r0[20:20], i_0r0[20:20]);
BUFF I72 (o_0r0[21:21], i_0r0[21:21]);
BUFF I73 (o_0r0[22:22], i_0r0[22:22]);
BUFF I74 (o_0r0[23:23], i_0r0[23:23]);
BUFF I75 (o_0r0[24:24], i_0r0[24:24]);
BUFF I76 (o_0r0[25:25], i_0r0[25:25]);
BUFF I77 (o_0r0[26:26], i_0r0[26:26]);
BUFF I78 (o_0r0[27:27], i_0r0[27:27]);
BUFF I79 (o_0r0[28:28], i_0r0[28:28]);
BUFF I80 (o_0r0[29:29], i_0r0[29:29]);
BUFF I81 (o_0r0[30:30], termf_1[0:0]);
BUFF I82 (o_0r0[31:31], termf_1[1:1]);
BUFF I83 (o_0r1[0:0], i_0r1[0:0]);
BUFF I84 (o_0r1[1:1], i_0r1[1:1]);
BUFF I85 (o_0r1[2:2], i_0r1[2:2]);
BUFF I86 (o_0r1[3:3], i_0r1[3:3]);
BUFF I87 (o_0r1[4:4], i_0r1[4:4]);
BUFF I88 (o_0r1[5:5], i_0r1[5:5]);
BUFF I89 (o_0r1[6:6], i_0r1[6:6]);
BUFF I90 (o_0r1[7:7], i_0r1[7:7]);
BUFF I91 (o_0r1[8:8], i_0r1[8:8]);
BUFF I92 (o_0r1[9:9], i_0r1[9:9]);
BUFF I93 (o_0r1[10:10], i_0r1[10:10]);
BUFF I94 (o_0r1[11:11], i_0r1[11:11]);
BUFF I95 (o_0r1[12:12], i_0r1[12:12]);
BUFF I96 (o_0r1[13:13], i_0r1[13:13]);
BUFF I97 (o_0r1[14:14], i_0r1[14:14]);
BUFF I98 (o_0r1[15:15], i_0r1[15:15]);
BUFF I99 (o_0r1[16:16], i_0r1[16:16]);
BUFF I100 (o_0r1[17:17], i_0r1[17:17]);
BUFF I101 (o_0r1[18:18], i_0r1[18:18]);
BUFF I102 (o_0r1[19:19], i_0r1[19:19]);
BUFF I103 (o_0r1[20:20], i_0r1[20:20]);
BUFF I104 (o_0r1[21:21], i_0r1[21:21]);
BUFF I105 (o_0r1[22:22], i_0r1[22:22]);
BUFF I106 (o_0r1[23:23], i_0r1[23:23]);
BUFF I107 (o_0r1[24:24], i_0r1[24:24]);
BUFF I108 (o_0r1[25:25], i_0r1[25:25]);
BUFF I109 (o_0r1[26:26], i_0r1[26:26]);
BUFF I110 (o_0r1[27:27], i_0r1[27:27]);
BUFF I111 (o_0r1[28:28], i_0r1[28:28]);
BUFF I112 (o_0r1[29:29], i_0r1[29:29]);
BUFF I113 (o_0r1[30:30], termt_1[0:0]);
BUFF I114 (o_0r1[31:31], termt_1[1:1]);
BUFF I115 (i_0a, o_0a);
endmodule
// tkvi32_wo0w32_ro0w32o0w30o2w30o2w30 TeakV "i" 32 [] [0] [0,0,2,2] [Many [32],Many [0],Many [0,0,0,0]
// ,Many [32,30,30,30]]
module tkvi32_wo0w32_ro0w32o0w30o2w30o2w30 (wg_0r0, wg_0r1, wg_0a, wd_0r, wd_0a, rg_0r, rg_0a, rg_1r, rg_1a, rg_2r, rg_2a, rg_3r, rg_3a, rd_0r0, rd_0r1, rd_0a, rd_1r0, rd_1r1, rd_1a, rd_2r0, rd_2r1, rd_2a, rd_3r0, rd_3r1, rd_3a, reset);
input [31:0] wg_0r0;
input [31:0] wg_0r1;
output wg_0a;
output wd_0r;
input wd_0a;
input rg_0r;
output rg_0a;
input rg_1r;
output rg_1a;
input rg_2r;
output rg_2a;
input rg_3r;
output rg_3a;
output [31:0] rd_0r0;
output [31:0] rd_0r1;
input rd_0a;
output [29:0] rd_1r0;
output [29:0] rd_1r1;
input rd_1a;
output [29:0] rd_2r0;
output [29:0] rd_2r1;
input rd_2a;
output [29:0] rd_3r0;
output [29:0] rd_3r1;
input rd_3a;
input reset;
wire [31:0] wf_0;
wire [31:0] wt_0;
wire [31:0] df_0;
wire [31:0] dt_0;
wire wc_0;
wire [31:0] wacks_0;
wire [31:0] wenr_0;
wire [31:0] wen_0;
wire anyread_0;
wire nreset_0;
wire [31:0] drlgf_0;
wire [31:0] drlgt_0;
wire [31:0] comp0_0;
wire [10:0] simp2381_0;
wire [3:0] simp2382_0;
wire [1:0] simp2383_0;
wire conwigc_0;
wire conwigcanw_0;
wire [31:0] conwgit_0;
wire [31:0] conwgif_0;
wire conwig_0;
wire [10:0] simp4071_0;
wire [3:0] simp4072_0;
wire [1:0] simp4073_0;
wire [2:0] simp6521_0;
INV I0 (nreset_0, reset);
AND2 I1 (wen_0[0:0], wenr_0[0:0], nreset_0);
AND2 I2 (wen_0[1:1], wenr_0[1:1], nreset_0);
AND2 I3 (wen_0[2:2], wenr_0[2:2], nreset_0);
AND2 I4 (wen_0[3:3], wenr_0[3:3], nreset_0);
AND2 I5 (wen_0[4:4], wenr_0[4:4], nreset_0);
AND2 I6 (wen_0[5:5], wenr_0[5:5], nreset_0);
AND2 I7 (wen_0[6:6], wenr_0[6:6], nreset_0);
AND2 I8 (wen_0[7:7], wenr_0[7:7], nreset_0);
AND2 I9 (wen_0[8:8], wenr_0[8:8], nreset_0);
AND2 I10 (wen_0[9:9], wenr_0[9:9], nreset_0);
AND2 I11 (wen_0[10:10], wenr_0[10:10], nreset_0);
AND2 I12 (wen_0[11:11], wenr_0[11:11], nreset_0);
AND2 I13 (wen_0[12:12], wenr_0[12:12], nreset_0);
AND2 I14 (wen_0[13:13], wenr_0[13:13], nreset_0);
AND2 I15 (wen_0[14:14], wenr_0[14:14], nreset_0);
AND2 I16 (wen_0[15:15], wenr_0[15:15], nreset_0);
AND2 I17 (wen_0[16:16], wenr_0[16:16], nreset_0);
AND2 I18 (wen_0[17:17], wenr_0[17:17], nreset_0);
AND2 I19 (wen_0[18:18], wenr_0[18:18], nreset_0);
AND2 I20 (wen_0[19:19], wenr_0[19:19], nreset_0);
AND2 I21 (wen_0[20:20], wenr_0[20:20], nreset_0);
AND2 I22 (wen_0[21:21], wenr_0[21:21], nreset_0);
AND2 I23 (wen_0[22:22], wenr_0[22:22], nreset_0);
AND2 I24 (wen_0[23:23], wenr_0[23:23], nreset_0);
AND2 I25 (wen_0[24:24], wenr_0[24:24], nreset_0);
AND2 I26 (wen_0[25:25], wenr_0[25:25], nreset_0);
AND2 I27 (wen_0[26:26], wenr_0[26:26], nreset_0);
AND2 I28 (wen_0[27:27], wenr_0[27:27], nreset_0);
AND2 I29 (wen_0[28:28], wenr_0[28:28], nreset_0);
AND2 I30 (wen_0[29:29], wenr_0[29:29], nreset_0);
AND2 I31 (wen_0[30:30], wenr_0[30:30], nreset_0);
AND2 I32 (wen_0[31:31], wenr_0[31:31], nreset_0);
AND2 I33 (drlgf_0[0:0], wf_0[0:0], wen_0[0:0]);
AND2 I34 (drlgf_0[1:1], wf_0[1:1], wen_0[1:1]);
AND2 I35 (drlgf_0[2:2], wf_0[2:2], wen_0[2:2]);
AND2 I36 (drlgf_0[3:3], wf_0[3:3], wen_0[3:3]);
AND2 I37 (drlgf_0[4:4], wf_0[4:4], wen_0[4:4]);
AND2 I38 (drlgf_0[5:5], wf_0[5:5], wen_0[5:5]);
AND2 I39 (drlgf_0[6:6], wf_0[6:6], wen_0[6:6]);
AND2 I40 (drlgf_0[7:7], wf_0[7:7], wen_0[7:7]);
AND2 I41 (drlgf_0[8:8], wf_0[8:8], wen_0[8:8]);
AND2 I42 (drlgf_0[9:9], wf_0[9:9], wen_0[9:9]);
AND2 I43 (drlgf_0[10:10], wf_0[10:10], wen_0[10:10]);
AND2 I44 (drlgf_0[11:11], wf_0[11:11], wen_0[11:11]);
AND2 I45 (drlgf_0[12:12], wf_0[12:12], wen_0[12:12]);
AND2 I46 (drlgf_0[13:13], wf_0[13:13], wen_0[13:13]);
AND2 I47 (drlgf_0[14:14], wf_0[14:14], wen_0[14:14]);
AND2 I48 (drlgf_0[15:15], wf_0[15:15], wen_0[15:15]);
AND2 I49 (drlgf_0[16:16], wf_0[16:16], wen_0[16:16]);
AND2 I50 (drlgf_0[17:17], wf_0[17:17], wen_0[17:17]);
AND2 I51 (drlgf_0[18:18], wf_0[18:18], wen_0[18:18]);
AND2 I52 (drlgf_0[19:19], wf_0[19:19], wen_0[19:19]);
AND2 I53 (drlgf_0[20:20], wf_0[20:20], wen_0[20:20]);
AND2 I54 (drlgf_0[21:21], wf_0[21:21], wen_0[21:21]);
AND2 I55 (drlgf_0[22:22], wf_0[22:22], wen_0[22:22]);
AND2 I56 (drlgf_0[23:23], wf_0[23:23], wen_0[23:23]);
AND2 I57 (drlgf_0[24:24], wf_0[24:24], wen_0[24:24]);
AND2 I58 (drlgf_0[25:25], wf_0[25:25], wen_0[25:25]);
AND2 I59 (drlgf_0[26:26], wf_0[26:26], wen_0[26:26]);
AND2 I60 (drlgf_0[27:27], wf_0[27:27], wen_0[27:27]);
AND2 I61 (drlgf_0[28:28], wf_0[28:28], wen_0[28:28]);
AND2 I62 (drlgf_0[29:29], wf_0[29:29], wen_0[29:29]);
AND2 I63 (drlgf_0[30:30], wf_0[30:30], wen_0[30:30]);
AND2 I64 (drlgf_0[31:31], wf_0[31:31], wen_0[31:31]);
AND2 I65 (drlgt_0[0:0], wt_0[0:0], wen_0[0:0]);
AND2 I66 (drlgt_0[1:1], wt_0[1:1], wen_0[1:1]);
AND2 I67 (drlgt_0[2:2], wt_0[2:2], wen_0[2:2]);
AND2 I68 (drlgt_0[3:3], wt_0[3:3], wen_0[3:3]);
AND2 I69 (drlgt_0[4:4], wt_0[4:4], wen_0[4:4]);
AND2 I70 (drlgt_0[5:5], wt_0[5:5], wen_0[5:5]);
AND2 I71 (drlgt_0[6:6], wt_0[6:6], wen_0[6:6]);
AND2 I72 (drlgt_0[7:7], wt_0[7:7], wen_0[7:7]);
AND2 I73 (drlgt_0[8:8], wt_0[8:8], wen_0[8:8]);
AND2 I74 (drlgt_0[9:9], wt_0[9:9], wen_0[9:9]);
AND2 I75 (drlgt_0[10:10], wt_0[10:10], wen_0[10:10]);
AND2 I76 (drlgt_0[11:11], wt_0[11:11], wen_0[11:11]);
AND2 I77 (drlgt_0[12:12], wt_0[12:12], wen_0[12:12]);
AND2 I78 (drlgt_0[13:13], wt_0[13:13], wen_0[13:13]);
AND2 I79 (drlgt_0[14:14], wt_0[14:14], wen_0[14:14]);
AND2 I80 (drlgt_0[15:15], wt_0[15:15], wen_0[15:15]);
AND2 I81 (drlgt_0[16:16], wt_0[16:16], wen_0[16:16]);
AND2 I82 (drlgt_0[17:17], wt_0[17:17], wen_0[17:17]);
AND2 I83 (drlgt_0[18:18], wt_0[18:18], wen_0[18:18]);
AND2 I84 (drlgt_0[19:19], wt_0[19:19], wen_0[19:19]);
AND2 I85 (drlgt_0[20:20], wt_0[20:20], wen_0[20:20]);
AND2 I86 (drlgt_0[21:21], wt_0[21:21], wen_0[21:21]);
AND2 I87 (drlgt_0[22:22], wt_0[22:22], wen_0[22:22]);
AND2 I88 (drlgt_0[23:23], wt_0[23:23], wen_0[23:23]);
AND2 I89 (drlgt_0[24:24], wt_0[24:24], wen_0[24:24]);
AND2 I90 (drlgt_0[25:25], wt_0[25:25], wen_0[25:25]);
AND2 I91 (drlgt_0[26:26], wt_0[26:26], wen_0[26:26]);
AND2 I92 (drlgt_0[27:27], wt_0[27:27], wen_0[27:27]);
AND2 I93 (drlgt_0[28:28], wt_0[28:28], wen_0[28:28]);
AND2 I94 (drlgt_0[29:29], wt_0[29:29], wen_0[29:29]);
AND2 I95 (drlgt_0[30:30], wt_0[30:30], wen_0[30:30]);
AND2 I96 (drlgt_0[31:31], wt_0[31:31], wen_0[31:31]);
NOR2 I97 (df_0[0:0], dt_0[0:0], drlgt_0[0:0]);
NOR2 I98 (df_0[1:1], dt_0[1:1], drlgt_0[1:1]);
NOR2 I99 (df_0[2:2], dt_0[2:2], drlgt_0[2:2]);
NOR2 I100 (df_0[3:3], dt_0[3:3], drlgt_0[3:3]);
NOR2 I101 (df_0[4:4], dt_0[4:4], drlgt_0[4:4]);
NOR2 I102 (df_0[5:5], dt_0[5:5], drlgt_0[5:5]);
NOR2 I103 (df_0[6:6], dt_0[6:6], drlgt_0[6:6]);
NOR2 I104 (df_0[7:7], dt_0[7:7], drlgt_0[7:7]);
NOR2 I105 (df_0[8:8], dt_0[8:8], drlgt_0[8:8]);
NOR2 I106 (df_0[9:9], dt_0[9:9], drlgt_0[9:9]);
NOR2 I107 (df_0[10:10], dt_0[10:10], drlgt_0[10:10]);
NOR2 I108 (df_0[11:11], dt_0[11:11], drlgt_0[11:11]);
NOR2 I109 (df_0[12:12], dt_0[12:12], drlgt_0[12:12]);
NOR2 I110 (df_0[13:13], dt_0[13:13], drlgt_0[13:13]);
NOR2 I111 (df_0[14:14], dt_0[14:14], drlgt_0[14:14]);
NOR2 I112 (df_0[15:15], dt_0[15:15], drlgt_0[15:15]);
NOR2 I113 (df_0[16:16], dt_0[16:16], drlgt_0[16:16]);
NOR2 I114 (df_0[17:17], dt_0[17:17], drlgt_0[17:17]);
NOR2 I115 (df_0[18:18], dt_0[18:18], drlgt_0[18:18]);
NOR2 I116 (df_0[19:19], dt_0[19:19], drlgt_0[19:19]);
NOR2 I117 (df_0[20:20], dt_0[20:20], drlgt_0[20:20]);
NOR2 I118 (df_0[21:21], dt_0[21:21], drlgt_0[21:21]);
NOR2 I119 (df_0[22:22], dt_0[22:22], drlgt_0[22:22]);
NOR2 I120 (df_0[23:23], dt_0[23:23], drlgt_0[23:23]);
NOR2 I121 (df_0[24:24], dt_0[24:24], drlgt_0[24:24]);
NOR2 I122 (df_0[25:25], dt_0[25:25], drlgt_0[25:25]);
NOR2 I123 (df_0[26:26], dt_0[26:26], drlgt_0[26:26]);
NOR2 I124 (df_0[27:27], dt_0[27:27], drlgt_0[27:27]);
NOR2 I125 (df_0[28:28], dt_0[28:28], drlgt_0[28:28]);
NOR2 I126 (df_0[29:29], dt_0[29:29], drlgt_0[29:29]);
NOR2 I127 (df_0[30:30], dt_0[30:30], drlgt_0[30:30]);
NOR2 I128 (df_0[31:31], dt_0[31:31], drlgt_0[31:31]);
NOR3 I129 (dt_0[0:0], df_0[0:0], drlgf_0[0:0], reset);
NOR3 I130 (dt_0[1:1], df_0[1:1], drlgf_0[1:1], reset);
NOR3 I131 (dt_0[2:2], df_0[2:2], drlgf_0[2:2], reset);
NOR3 I132 (dt_0[3:3], df_0[3:3], drlgf_0[3:3], reset);
NOR3 I133 (dt_0[4:4], df_0[4:4], drlgf_0[4:4], reset);
NOR3 I134 (dt_0[5:5], df_0[5:5], drlgf_0[5:5], reset);
NOR3 I135 (dt_0[6:6], df_0[6:6], drlgf_0[6:6], reset);
NOR3 I136 (dt_0[7:7], df_0[7:7], drlgf_0[7:7], reset);
NOR3 I137 (dt_0[8:8], df_0[8:8], drlgf_0[8:8], reset);
NOR3 I138 (dt_0[9:9], df_0[9:9], drlgf_0[9:9], reset);
NOR3 I139 (dt_0[10:10], df_0[10:10], drlgf_0[10:10], reset);
NOR3 I140 (dt_0[11:11], df_0[11:11], drlgf_0[11:11], reset);
NOR3 I141 (dt_0[12:12], df_0[12:12], drlgf_0[12:12], reset);
NOR3 I142 (dt_0[13:13], df_0[13:13], drlgf_0[13:13], reset);
NOR3 I143 (dt_0[14:14], df_0[14:14], drlgf_0[14:14], reset);
NOR3 I144 (dt_0[15:15], df_0[15:15], drlgf_0[15:15], reset);
NOR3 I145 (dt_0[16:16], df_0[16:16], drlgf_0[16:16], reset);
NOR3 I146 (dt_0[17:17], df_0[17:17], drlgf_0[17:17], reset);
NOR3 I147 (dt_0[18:18], df_0[18:18], drlgf_0[18:18], reset);
NOR3 I148 (dt_0[19:19], df_0[19:19], drlgf_0[19:19], reset);
NOR3 I149 (dt_0[20:20], df_0[20:20], drlgf_0[20:20], reset);
NOR3 I150 (dt_0[21:21], df_0[21:21], drlgf_0[21:21], reset);
NOR3 I151 (dt_0[22:22], df_0[22:22], drlgf_0[22:22], reset);
NOR3 I152 (dt_0[23:23], df_0[23:23], drlgf_0[23:23], reset);
NOR3 I153 (dt_0[24:24], df_0[24:24], drlgf_0[24:24], reset);
NOR3 I154 (dt_0[25:25], df_0[25:25], drlgf_0[25:25], reset);
NOR3 I155 (dt_0[26:26], df_0[26:26], drlgf_0[26:26], reset);
NOR3 I156 (dt_0[27:27], df_0[27:27], drlgf_0[27:27], reset);
NOR3 I157 (dt_0[28:28], df_0[28:28], drlgf_0[28:28], reset);
NOR3 I158 (dt_0[29:29], df_0[29:29], drlgf_0[29:29], reset);
NOR3 I159 (dt_0[30:30], df_0[30:30], drlgf_0[30:30], reset);
NOR3 I160 (dt_0[31:31], df_0[31:31], drlgf_0[31:31], reset);
AO22 I161 (wacks_0[0:0], drlgf_0[0:0], df_0[0:0], drlgt_0[0:0], dt_0[0:0]);
AO22 I162 (wacks_0[1:1], drlgf_0[1:1], df_0[1:1], drlgt_0[1:1], dt_0[1:1]);
AO22 I163 (wacks_0[2:2], drlgf_0[2:2], df_0[2:2], drlgt_0[2:2], dt_0[2:2]);
AO22 I164 (wacks_0[3:3], drlgf_0[3:3], df_0[3:3], drlgt_0[3:3], dt_0[3:3]);
AO22 I165 (wacks_0[4:4], drlgf_0[4:4], df_0[4:4], drlgt_0[4:4], dt_0[4:4]);
AO22 I166 (wacks_0[5:5], drlgf_0[5:5], df_0[5:5], drlgt_0[5:5], dt_0[5:5]);
AO22 I167 (wacks_0[6:6], drlgf_0[6:6], df_0[6:6], drlgt_0[6:6], dt_0[6:6]);
AO22 I168 (wacks_0[7:7], drlgf_0[7:7], df_0[7:7], drlgt_0[7:7], dt_0[7:7]);
AO22 I169 (wacks_0[8:8], drlgf_0[8:8], df_0[8:8], drlgt_0[8:8], dt_0[8:8]);
AO22 I170 (wacks_0[9:9], drlgf_0[9:9], df_0[9:9], drlgt_0[9:9], dt_0[9:9]);
AO22 I171 (wacks_0[10:10], drlgf_0[10:10], df_0[10:10], drlgt_0[10:10], dt_0[10:10]);
AO22 I172 (wacks_0[11:11], drlgf_0[11:11], df_0[11:11], drlgt_0[11:11], dt_0[11:11]);
AO22 I173 (wacks_0[12:12], drlgf_0[12:12], df_0[12:12], drlgt_0[12:12], dt_0[12:12]);
AO22 I174 (wacks_0[13:13], drlgf_0[13:13], df_0[13:13], drlgt_0[13:13], dt_0[13:13]);
AO22 I175 (wacks_0[14:14], drlgf_0[14:14], df_0[14:14], drlgt_0[14:14], dt_0[14:14]);
AO22 I176 (wacks_0[15:15], drlgf_0[15:15], df_0[15:15], drlgt_0[15:15], dt_0[15:15]);
AO22 I177 (wacks_0[16:16], drlgf_0[16:16], df_0[16:16], drlgt_0[16:16], dt_0[16:16]);
AO22 I178 (wacks_0[17:17], drlgf_0[17:17], df_0[17:17], drlgt_0[17:17], dt_0[17:17]);
AO22 I179 (wacks_0[18:18], drlgf_0[18:18], df_0[18:18], drlgt_0[18:18], dt_0[18:18]);
AO22 I180 (wacks_0[19:19], drlgf_0[19:19], df_0[19:19], drlgt_0[19:19], dt_0[19:19]);
AO22 I181 (wacks_0[20:20], drlgf_0[20:20], df_0[20:20], drlgt_0[20:20], dt_0[20:20]);
AO22 I182 (wacks_0[21:21], drlgf_0[21:21], df_0[21:21], drlgt_0[21:21], dt_0[21:21]);
AO22 I183 (wacks_0[22:22], drlgf_0[22:22], df_0[22:22], drlgt_0[22:22], dt_0[22:22]);
AO22 I184 (wacks_0[23:23], drlgf_0[23:23], df_0[23:23], drlgt_0[23:23], dt_0[23:23]);
AO22 I185 (wacks_0[24:24], drlgf_0[24:24], df_0[24:24], drlgt_0[24:24], dt_0[24:24]);
AO22 I186 (wacks_0[25:25], drlgf_0[25:25], df_0[25:25], drlgt_0[25:25], dt_0[25:25]);
AO22 I187 (wacks_0[26:26], drlgf_0[26:26], df_0[26:26], drlgt_0[26:26], dt_0[26:26]);
AO22 I188 (wacks_0[27:27], drlgf_0[27:27], df_0[27:27], drlgt_0[27:27], dt_0[27:27]);
AO22 I189 (wacks_0[28:28], drlgf_0[28:28], df_0[28:28], drlgt_0[28:28], dt_0[28:28]);
AO22 I190 (wacks_0[29:29], drlgf_0[29:29], df_0[29:29], drlgt_0[29:29], dt_0[29:29]);
AO22 I191 (wacks_0[30:30], drlgf_0[30:30], df_0[30:30], drlgt_0[30:30], dt_0[30:30]);
AO22 I192 (wacks_0[31:31], drlgf_0[31:31], df_0[31:31], drlgt_0[31:31], dt_0[31:31]);
OR2 I193 (comp0_0[0:0], wg_0r0[0:0], wg_0r1[0:0]);
OR2 I194 (comp0_0[1:1], wg_0r0[1:1], wg_0r1[1:1]);
OR2 I195 (comp0_0[2:2], wg_0r0[2:2], wg_0r1[2:2]);
OR2 I196 (comp0_0[3:3], wg_0r0[3:3], wg_0r1[3:3]);
OR2 I197 (comp0_0[4:4], wg_0r0[4:4], wg_0r1[4:4]);
OR2 I198 (comp0_0[5:5], wg_0r0[5:5], wg_0r1[5:5]);
OR2 I199 (comp0_0[6:6], wg_0r0[6:6], wg_0r1[6:6]);
OR2 I200 (comp0_0[7:7], wg_0r0[7:7], wg_0r1[7:7]);
OR2 I201 (comp0_0[8:8], wg_0r0[8:8], wg_0r1[8:8]);
OR2 I202 (comp0_0[9:9], wg_0r0[9:9], wg_0r1[9:9]);
OR2 I203 (comp0_0[10:10], wg_0r0[10:10], wg_0r1[10:10]);
OR2 I204 (comp0_0[11:11], wg_0r0[11:11], wg_0r1[11:11]);
OR2 I205 (comp0_0[12:12], wg_0r0[12:12], wg_0r1[12:12]);
OR2 I206 (comp0_0[13:13], wg_0r0[13:13], wg_0r1[13:13]);
OR2 I207 (comp0_0[14:14], wg_0r0[14:14], wg_0r1[14:14]);
OR2 I208 (comp0_0[15:15], wg_0r0[15:15], wg_0r1[15:15]);
OR2 I209 (comp0_0[16:16], wg_0r0[16:16], wg_0r1[16:16]);
OR2 I210 (comp0_0[17:17], wg_0r0[17:17], wg_0r1[17:17]);
OR2 I211 (comp0_0[18:18], wg_0r0[18:18], wg_0r1[18:18]);
OR2 I212 (comp0_0[19:19], wg_0r0[19:19], wg_0r1[19:19]);
OR2 I213 (comp0_0[20:20], wg_0r0[20:20], wg_0r1[20:20]);
OR2 I214 (comp0_0[21:21], wg_0r0[21:21], wg_0r1[21:21]);
OR2 I215 (comp0_0[22:22], wg_0r0[22:22], wg_0r1[22:22]);
OR2 I216 (comp0_0[23:23], wg_0r0[23:23], wg_0r1[23:23]);
OR2 I217 (comp0_0[24:24], wg_0r0[24:24], wg_0r1[24:24]);
OR2 I218 (comp0_0[25:25], wg_0r0[25:25], wg_0r1[25:25]);
OR2 I219 (comp0_0[26:26], wg_0r0[26:26], wg_0r1[26:26]);
OR2 I220 (comp0_0[27:27], wg_0r0[27:27], wg_0r1[27:27]);
OR2 I221 (comp0_0[28:28], wg_0r0[28:28], wg_0r1[28:28]);
OR2 I222 (comp0_0[29:29], wg_0r0[29:29], wg_0r1[29:29]);
OR2 I223 (comp0_0[30:30], wg_0r0[30:30], wg_0r1[30:30]);
OR2 I224 (comp0_0[31:31], wg_0r0[31:31], wg_0r1[31:31]);
C3 I225 (simp2381_0[0:0], comp0_0[0:0], comp0_0[1:1], comp0_0[2:2]);
C3 I226 (simp2381_0[1:1], comp0_0[3:3], comp0_0[4:4], comp0_0[5:5]);
C3 I227 (simp2381_0[2:2], comp0_0[6:6], comp0_0[7:7], comp0_0[8:8]);
C3 I228 (simp2381_0[3:3], comp0_0[9:9], comp0_0[10:10], comp0_0[11:11]);
C3 I229 (simp2381_0[4:4], comp0_0[12:12], comp0_0[13:13], comp0_0[14:14]);
C3 I230 (simp2381_0[5:5], comp0_0[15:15], comp0_0[16:16], comp0_0[17:17]);
C3 I231 (simp2381_0[6:6], comp0_0[18:18], comp0_0[19:19], comp0_0[20:20]);
C3 I232 (simp2381_0[7:7], comp0_0[21:21], comp0_0[22:22], comp0_0[23:23]);
C3 I233 (simp2381_0[8:8], comp0_0[24:24], comp0_0[25:25], comp0_0[26:26]);
C3 I234 (simp2381_0[9:9], comp0_0[27:27], comp0_0[28:28], comp0_0[29:29]);
C2 I235 (simp2381_0[10:10], comp0_0[30:30], comp0_0[31:31]);
C3 I236 (simp2382_0[0:0], simp2381_0[0:0], simp2381_0[1:1], simp2381_0[2:2]);
C3 I237 (simp2382_0[1:1], simp2381_0[3:3], simp2381_0[4:4], simp2381_0[5:5]);
C3 I238 (simp2382_0[2:2], simp2381_0[6:6], simp2381_0[7:7], simp2381_0[8:8]);
C2 I239 (simp2382_0[3:3], simp2381_0[9:9], simp2381_0[10:10]);
C3 I240 (simp2383_0[0:0], simp2382_0[0:0], simp2382_0[1:1], simp2382_0[2:2]);
BUFF I241 (simp2383_0[1:1], simp2382_0[3:3]);
C2 I242 (wc_0, simp2383_0[0:0], simp2383_0[1:1]);
AND2 I243 (conwgif_0[0:0], wg_0r0[0:0], conwig_0);
AND2 I244 (conwgif_0[1:1], wg_0r0[1:1], conwig_0);
AND2 I245 (conwgif_0[2:2], wg_0r0[2:2], conwig_0);
AND2 I246 (conwgif_0[3:3], wg_0r0[3:3], conwig_0);
AND2 I247 (conwgif_0[4:4], wg_0r0[4:4], conwig_0);
AND2 I248 (conwgif_0[5:5], wg_0r0[5:5], conwig_0);
AND2 I249 (conwgif_0[6:6], wg_0r0[6:6], conwig_0);
AND2 I250 (conwgif_0[7:7], wg_0r0[7:7], conwig_0);
AND2 I251 (conwgif_0[8:8], wg_0r0[8:8], conwig_0);
AND2 I252 (conwgif_0[9:9], wg_0r0[9:9], conwig_0);
AND2 I253 (conwgif_0[10:10], wg_0r0[10:10], conwig_0);
AND2 I254 (conwgif_0[11:11], wg_0r0[11:11], conwig_0);
AND2 I255 (conwgif_0[12:12], wg_0r0[12:12], conwig_0);
AND2 I256 (conwgif_0[13:13], wg_0r0[13:13], conwig_0);
AND2 I257 (conwgif_0[14:14], wg_0r0[14:14], conwig_0);
AND2 I258 (conwgif_0[15:15], wg_0r0[15:15], conwig_0);
AND2 I259 (conwgif_0[16:16], wg_0r0[16:16], conwig_0);
AND2 I260 (conwgif_0[17:17], wg_0r0[17:17], conwig_0);
AND2 I261 (conwgif_0[18:18], wg_0r0[18:18], conwig_0);
AND2 I262 (conwgif_0[19:19], wg_0r0[19:19], conwig_0);
AND2 I263 (conwgif_0[20:20], wg_0r0[20:20], conwig_0);
AND2 I264 (conwgif_0[21:21], wg_0r0[21:21], conwig_0);
AND2 I265 (conwgif_0[22:22], wg_0r0[22:22], conwig_0);
AND2 I266 (conwgif_0[23:23], wg_0r0[23:23], conwig_0);
AND2 I267 (conwgif_0[24:24], wg_0r0[24:24], conwig_0);
AND2 I268 (conwgif_0[25:25], wg_0r0[25:25], conwig_0);
AND2 I269 (conwgif_0[26:26], wg_0r0[26:26], conwig_0);
AND2 I270 (conwgif_0[27:27], wg_0r0[27:27], conwig_0);
AND2 I271 (conwgif_0[28:28], wg_0r0[28:28], conwig_0);
AND2 I272 (conwgif_0[29:29], wg_0r0[29:29], conwig_0);
AND2 I273 (conwgif_0[30:30], wg_0r0[30:30], conwig_0);
AND2 I274 (conwgif_0[31:31], wg_0r0[31:31], conwig_0);
AND2 I275 (conwgit_0[0:0], wg_0r1[0:0], conwig_0);
AND2 I276 (conwgit_0[1:1], wg_0r1[1:1], conwig_0);
AND2 I277 (conwgit_0[2:2], wg_0r1[2:2], conwig_0);
AND2 I278 (conwgit_0[3:3], wg_0r1[3:3], conwig_0);
AND2 I279 (conwgit_0[4:4], wg_0r1[4:4], conwig_0);
AND2 I280 (conwgit_0[5:5], wg_0r1[5:5], conwig_0);
AND2 I281 (conwgit_0[6:6], wg_0r1[6:6], conwig_0);
AND2 I282 (conwgit_0[7:7], wg_0r1[7:7], conwig_0);
AND2 I283 (conwgit_0[8:8], wg_0r1[8:8], conwig_0);
AND2 I284 (conwgit_0[9:9], wg_0r1[9:9], conwig_0);
AND2 I285 (conwgit_0[10:10], wg_0r1[10:10], conwig_0);
AND2 I286 (conwgit_0[11:11], wg_0r1[11:11], conwig_0);
AND2 I287 (conwgit_0[12:12], wg_0r1[12:12], conwig_0);
AND2 I288 (conwgit_0[13:13], wg_0r1[13:13], conwig_0);
AND2 I289 (conwgit_0[14:14], wg_0r1[14:14], conwig_0);
AND2 I290 (conwgit_0[15:15], wg_0r1[15:15], conwig_0);
AND2 I291 (conwgit_0[16:16], wg_0r1[16:16], conwig_0);
AND2 I292 (conwgit_0[17:17], wg_0r1[17:17], conwig_0);
AND2 I293 (conwgit_0[18:18], wg_0r1[18:18], conwig_0);
AND2 I294 (conwgit_0[19:19], wg_0r1[19:19], conwig_0);
AND2 I295 (conwgit_0[20:20], wg_0r1[20:20], conwig_0);
AND2 I296 (conwgit_0[21:21], wg_0r1[21:21], conwig_0);
AND2 I297 (conwgit_0[22:22], wg_0r1[22:22], conwig_0);
AND2 I298 (conwgit_0[23:23], wg_0r1[23:23], conwig_0);
AND2 I299 (conwgit_0[24:24], wg_0r1[24:24], conwig_0);
AND2 I300 (conwgit_0[25:25], wg_0r1[25:25], conwig_0);
AND2 I301 (conwgit_0[26:26], wg_0r1[26:26], conwig_0);
AND2 I302 (conwgit_0[27:27], wg_0r1[27:27], conwig_0);
AND2 I303 (conwgit_0[28:28], wg_0r1[28:28], conwig_0);
AND2 I304 (conwgit_0[29:29], wg_0r1[29:29], conwig_0);
AND2 I305 (conwgit_0[30:30], wg_0r1[30:30], conwig_0);
AND2 I306 (conwgit_0[31:31], wg_0r1[31:31], conwig_0);
BUFF I307 (conwigc_0, wc_0);
AO22 I308 (conwig_0, conwigc_0, conwigcanw_0, conwigc_0, conwig_0);
NOR2 I309 (conwigcanw_0, anyread_0, conwig_0);
BUFF I310 (wf_0[0:0], conwgif_0[0:0]);
BUFF I311 (wt_0[0:0], conwgit_0[0:0]);
BUFF I312 (wenr_0[0:0], wc_0);
BUFF I313 (wf_0[1:1], conwgif_0[1:1]);
BUFF I314 (wt_0[1:1], conwgit_0[1:1]);
BUFF I315 (wenr_0[1:1], wc_0);
BUFF I316 (wf_0[2:2], conwgif_0[2:2]);
BUFF I317 (wt_0[2:2], conwgit_0[2:2]);
BUFF I318 (wenr_0[2:2], wc_0);
BUFF I319 (wf_0[3:3], conwgif_0[3:3]);
BUFF I320 (wt_0[3:3], conwgit_0[3:3]);
BUFF I321 (wenr_0[3:3], wc_0);
BUFF I322 (wf_0[4:4], conwgif_0[4:4]);
BUFF I323 (wt_0[4:4], conwgit_0[4:4]);
BUFF I324 (wenr_0[4:4], wc_0);
BUFF I325 (wf_0[5:5], conwgif_0[5:5]);
BUFF I326 (wt_0[5:5], conwgit_0[5:5]);
BUFF I327 (wenr_0[5:5], wc_0);
BUFF I328 (wf_0[6:6], conwgif_0[6:6]);
BUFF I329 (wt_0[6:6], conwgit_0[6:6]);
BUFF I330 (wenr_0[6:6], wc_0);
BUFF I331 (wf_0[7:7], conwgif_0[7:7]);
BUFF I332 (wt_0[7:7], conwgit_0[7:7]);
BUFF I333 (wenr_0[7:7], wc_0);
BUFF I334 (wf_0[8:8], conwgif_0[8:8]);
BUFF I335 (wt_0[8:8], conwgit_0[8:8]);
BUFF I336 (wenr_0[8:8], wc_0);
BUFF I337 (wf_0[9:9], conwgif_0[9:9]);
BUFF I338 (wt_0[9:9], conwgit_0[9:9]);
BUFF I339 (wenr_0[9:9], wc_0);
BUFF I340 (wf_0[10:10], conwgif_0[10:10]);
BUFF I341 (wt_0[10:10], conwgit_0[10:10]);
BUFF I342 (wenr_0[10:10], wc_0);
BUFF I343 (wf_0[11:11], conwgif_0[11:11]);
BUFF I344 (wt_0[11:11], conwgit_0[11:11]);
BUFF I345 (wenr_0[11:11], wc_0);
BUFF I346 (wf_0[12:12], conwgif_0[12:12]);
BUFF I347 (wt_0[12:12], conwgit_0[12:12]);
BUFF I348 (wenr_0[12:12], wc_0);
BUFF I349 (wf_0[13:13], conwgif_0[13:13]);
BUFF I350 (wt_0[13:13], conwgit_0[13:13]);
BUFF I351 (wenr_0[13:13], wc_0);
BUFF I352 (wf_0[14:14], conwgif_0[14:14]);
BUFF I353 (wt_0[14:14], conwgit_0[14:14]);
BUFF I354 (wenr_0[14:14], wc_0);
BUFF I355 (wf_0[15:15], conwgif_0[15:15]);
BUFF I356 (wt_0[15:15], conwgit_0[15:15]);
BUFF I357 (wenr_0[15:15], wc_0);
BUFF I358 (wf_0[16:16], conwgif_0[16:16]);
BUFF I359 (wt_0[16:16], conwgit_0[16:16]);
BUFF I360 (wenr_0[16:16], wc_0);
BUFF I361 (wf_0[17:17], conwgif_0[17:17]);
BUFF I362 (wt_0[17:17], conwgit_0[17:17]);
BUFF I363 (wenr_0[17:17], wc_0);
BUFF I364 (wf_0[18:18], conwgif_0[18:18]);
BUFF I365 (wt_0[18:18], conwgit_0[18:18]);
BUFF I366 (wenr_0[18:18], wc_0);
BUFF I367 (wf_0[19:19], conwgif_0[19:19]);
BUFF I368 (wt_0[19:19], conwgit_0[19:19]);
BUFF I369 (wenr_0[19:19], wc_0);
BUFF I370 (wf_0[20:20], conwgif_0[20:20]);
BUFF I371 (wt_0[20:20], conwgit_0[20:20]);
BUFF I372 (wenr_0[20:20], wc_0);
BUFF I373 (wf_0[21:21], conwgif_0[21:21]);
BUFF I374 (wt_0[21:21], conwgit_0[21:21]);
BUFF I375 (wenr_0[21:21], wc_0);
BUFF I376 (wf_0[22:22], conwgif_0[22:22]);
BUFF I377 (wt_0[22:22], conwgit_0[22:22]);
BUFF I378 (wenr_0[22:22], wc_0);
BUFF I379 (wf_0[23:23], conwgif_0[23:23]);
BUFF I380 (wt_0[23:23], conwgit_0[23:23]);
BUFF I381 (wenr_0[23:23], wc_0);
BUFF I382 (wf_0[24:24], conwgif_0[24:24]);
BUFF I383 (wt_0[24:24], conwgit_0[24:24]);
BUFF I384 (wenr_0[24:24], wc_0);
BUFF I385 (wf_0[25:25], conwgif_0[25:25]);
BUFF I386 (wt_0[25:25], conwgit_0[25:25]);
BUFF I387 (wenr_0[25:25], wc_0);
BUFF I388 (wf_0[26:26], conwgif_0[26:26]);
BUFF I389 (wt_0[26:26], conwgit_0[26:26]);
BUFF I390 (wenr_0[26:26], wc_0);
BUFF I391 (wf_0[27:27], conwgif_0[27:27]);
BUFF I392 (wt_0[27:27], conwgit_0[27:27]);
BUFF I393 (wenr_0[27:27], wc_0);
BUFF I394 (wf_0[28:28], conwgif_0[28:28]);
BUFF I395 (wt_0[28:28], conwgit_0[28:28]);
BUFF I396 (wenr_0[28:28], wc_0);
BUFF I397 (wf_0[29:29], conwgif_0[29:29]);
BUFF I398 (wt_0[29:29], conwgit_0[29:29]);
BUFF I399 (wenr_0[29:29], wc_0);
BUFF I400 (wf_0[30:30], conwgif_0[30:30]);
BUFF I401 (wt_0[30:30], conwgit_0[30:30]);
BUFF I402 (wenr_0[30:30], wc_0);
BUFF I403 (wf_0[31:31], conwgif_0[31:31]);
BUFF I404 (wt_0[31:31], conwgit_0[31:31]);
BUFF I405 (wenr_0[31:31], wc_0);
C3 I406 (simp4071_0[0:0], conwig_0, wacks_0[0:0], wacks_0[1:1]);
C3 I407 (simp4071_0[1:1], wacks_0[2:2], wacks_0[3:3], wacks_0[4:4]);
C3 I408 (simp4071_0[2:2], wacks_0[5:5], wacks_0[6:6], wacks_0[7:7]);
C3 I409 (simp4071_0[3:3], wacks_0[8:8], wacks_0[9:9], wacks_0[10:10]);
C3 I410 (simp4071_0[4:4], wacks_0[11:11], wacks_0[12:12], wacks_0[13:13]);
C3 I411 (simp4071_0[5:5], wacks_0[14:14], wacks_0[15:15], wacks_0[16:16]);
C3 I412 (simp4071_0[6:6], wacks_0[17:17], wacks_0[18:18], wacks_0[19:19]);
C3 I413 (simp4071_0[7:7], wacks_0[20:20], wacks_0[21:21], wacks_0[22:22]);
C3 I414 (simp4071_0[8:8], wacks_0[23:23], wacks_0[24:24], wacks_0[25:25]);
C3 I415 (simp4071_0[9:9], wacks_0[26:26], wacks_0[27:27], wacks_0[28:28]);
C3 I416 (simp4071_0[10:10], wacks_0[29:29], wacks_0[30:30], wacks_0[31:31]);
C3 I417 (simp4072_0[0:0], simp4071_0[0:0], simp4071_0[1:1], simp4071_0[2:2]);
C3 I418 (simp4072_0[1:1], simp4071_0[3:3], simp4071_0[4:4], simp4071_0[5:5]);
C3 I419 (simp4072_0[2:2], simp4071_0[6:6], simp4071_0[7:7], simp4071_0[8:8]);
C2 I420 (simp4072_0[3:3], simp4071_0[9:9], simp4071_0[10:10]);
C3 I421 (simp4073_0[0:0], simp4072_0[0:0], simp4072_0[1:1], simp4072_0[2:2]);
BUFF I422 (simp4073_0[1:1], simp4072_0[3:3]);
C2 I423 (wd_0r, simp4073_0[0:0], simp4073_0[1:1]);
AND2 I424 (rd_0r0[0:0], df_0[0:0], rg_0r);
AND2 I425 (rd_0r0[1:1], df_0[1:1], rg_0r);
AND2 I426 (rd_0r0[2:2], df_0[2:2], rg_0r);
AND2 I427 (rd_0r0[3:3], df_0[3:3], rg_0r);
AND2 I428 (rd_0r0[4:4], df_0[4:4], rg_0r);
AND2 I429 (rd_0r0[5:5], df_0[5:5], rg_0r);
AND2 I430 (rd_0r0[6:6], df_0[6:6], rg_0r);
AND2 I431 (rd_0r0[7:7], df_0[7:7], rg_0r);
AND2 I432 (rd_0r0[8:8], df_0[8:8], rg_0r);
AND2 I433 (rd_0r0[9:9], df_0[9:9], rg_0r);
AND2 I434 (rd_0r0[10:10], df_0[10:10], rg_0r);
AND2 I435 (rd_0r0[11:11], df_0[11:11], rg_0r);
AND2 I436 (rd_0r0[12:12], df_0[12:12], rg_0r);
AND2 I437 (rd_0r0[13:13], df_0[13:13], rg_0r);
AND2 I438 (rd_0r0[14:14], df_0[14:14], rg_0r);
AND2 I439 (rd_0r0[15:15], df_0[15:15], rg_0r);
AND2 I440 (rd_0r0[16:16], df_0[16:16], rg_0r);
AND2 I441 (rd_0r0[17:17], df_0[17:17], rg_0r);
AND2 I442 (rd_0r0[18:18], df_0[18:18], rg_0r);
AND2 I443 (rd_0r0[19:19], df_0[19:19], rg_0r);
AND2 I444 (rd_0r0[20:20], df_0[20:20], rg_0r);
AND2 I445 (rd_0r0[21:21], df_0[21:21], rg_0r);
AND2 I446 (rd_0r0[22:22], df_0[22:22], rg_0r);
AND2 I447 (rd_0r0[23:23], df_0[23:23], rg_0r);
AND2 I448 (rd_0r0[24:24], df_0[24:24], rg_0r);
AND2 I449 (rd_0r0[25:25], df_0[25:25], rg_0r);
AND2 I450 (rd_0r0[26:26], df_0[26:26], rg_0r);
AND2 I451 (rd_0r0[27:27], df_0[27:27], rg_0r);
AND2 I452 (rd_0r0[28:28], df_0[28:28], rg_0r);
AND2 I453 (rd_0r0[29:29], df_0[29:29], rg_0r);
AND2 I454 (rd_0r0[30:30], df_0[30:30], rg_0r);
AND2 I455 (rd_0r0[31:31], df_0[31:31], rg_0r);
AND2 I456 (rd_1r0[0:0], df_0[0:0], rg_1r);
AND2 I457 (rd_1r0[1:1], df_0[1:1], rg_1r);
AND2 I458 (rd_1r0[2:2], df_0[2:2], rg_1r);
AND2 I459 (rd_1r0[3:3], df_0[3:3], rg_1r);
AND2 I460 (rd_1r0[4:4], df_0[4:4], rg_1r);
AND2 I461 (rd_1r0[5:5], df_0[5:5], rg_1r);
AND2 I462 (rd_1r0[6:6], df_0[6:6], rg_1r);
AND2 I463 (rd_1r0[7:7], df_0[7:7], rg_1r);
AND2 I464 (rd_1r0[8:8], df_0[8:8], rg_1r);
AND2 I465 (rd_1r0[9:9], df_0[9:9], rg_1r);
AND2 I466 (rd_1r0[10:10], df_0[10:10], rg_1r);
AND2 I467 (rd_1r0[11:11], df_0[11:11], rg_1r);
AND2 I468 (rd_1r0[12:12], df_0[12:12], rg_1r);
AND2 I469 (rd_1r0[13:13], df_0[13:13], rg_1r);
AND2 I470 (rd_1r0[14:14], df_0[14:14], rg_1r);
AND2 I471 (rd_1r0[15:15], df_0[15:15], rg_1r);
AND2 I472 (rd_1r0[16:16], df_0[16:16], rg_1r);
AND2 I473 (rd_1r0[17:17], df_0[17:17], rg_1r);
AND2 I474 (rd_1r0[18:18], df_0[18:18], rg_1r);
AND2 I475 (rd_1r0[19:19], df_0[19:19], rg_1r);
AND2 I476 (rd_1r0[20:20], df_0[20:20], rg_1r);
AND2 I477 (rd_1r0[21:21], df_0[21:21], rg_1r);
AND2 I478 (rd_1r0[22:22], df_0[22:22], rg_1r);
AND2 I479 (rd_1r0[23:23], df_0[23:23], rg_1r);
AND2 I480 (rd_1r0[24:24], df_0[24:24], rg_1r);
AND2 I481 (rd_1r0[25:25], df_0[25:25], rg_1r);
AND2 I482 (rd_1r0[26:26], df_0[26:26], rg_1r);
AND2 I483 (rd_1r0[27:27], df_0[27:27], rg_1r);
AND2 I484 (rd_1r0[28:28], df_0[28:28], rg_1r);
AND2 I485 (rd_1r0[29:29], df_0[29:29], rg_1r);
AND2 I486 (rd_2r0[0:0], df_0[2:2], rg_2r);
AND2 I487 (rd_2r0[1:1], df_0[3:3], rg_2r);
AND2 I488 (rd_2r0[2:2], df_0[4:4], rg_2r);
AND2 I489 (rd_2r0[3:3], df_0[5:5], rg_2r);
AND2 I490 (rd_2r0[4:4], df_0[6:6], rg_2r);
AND2 I491 (rd_2r0[5:5], df_0[7:7], rg_2r);
AND2 I492 (rd_2r0[6:6], df_0[8:8], rg_2r);
AND2 I493 (rd_2r0[7:7], df_0[9:9], rg_2r);
AND2 I494 (rd_2r0[8:8], df_0[10:10], rg_2r);
AND2 I495 (rd_2r0[9:9], df_0[11:11], rg_2r);
AND2 I496 (rd_2r0[10:10], df_0[12:12], rg_2r);
AND2 I497 (rd_2r0[11:11], df_0[13:13], rg_2r);
AND2 I498 (rd_2r0[12:12], df_0[14:14], rg_2r);
AND2 I499 (rd_2r0[13:13], df_0[15:15], rg_2r);
AND2 I500 (rd_2r0[14:14], df_0[16:16], rg_2r);
AND2 I501 (rd_2r0[15:15], df_0[17:17], rg_2r);
AND2 I502 (rd_2r0[16:16], df_0[18:18], rg_2r);
AND2 I503 (rd_2r0[17:17], df_0[19:19], rg_2r);
AND2 I504 (rd_2r0[18:18], df_0[20:20], rg_2r);
AND2 I505 (rd_2r0[19:19], df_0[21:21], rg_2r);
AND2 I506 (rd_2r0[20:20], df_0[22:22], rg_2r);
AND2 I507 (rd_2r0[21:21], df_0[23:23], rg_2r);
AND2 I508 (rd_2r0[22:22], df_0[24:24], rg_2r);
AND2 I509 (rd_2r0[23:23], df_0[25:25], rg_2r);
AND2 I510 (rd_2r0[24:24], df_0[26:26], rg_2r);
AND2 I511 (rd_2r0[25:25], df_0[27:27], rg_2r);
AND2 I512 (rd_2r0[26:26], df_0[28:28], rg_2r);
AND2 I513 (rd_2r0[27:27], df_0[29:29], rg_2r);
AND2 I514 (rd_2r0[28:28], df_0[30:30], rg_2r);
AND2 I515 (rd_2r0[29:29], df_0[31:31], rg_2r);
AND2 I516 (rd_3r0[0:0], df_0[2:2], rg_3r);
AND2 I517 (rd_3r0[1:1], df_0[3:3], rg_3r);
AND2 I518 (rd_3r0[2:2], df_0[4:4], rg_3r);
AND2 I519 (rd_3r0[3:3], df_0[5:5], rg_3r);
AND2 I520 (rd_3r0[4:4], df_0[6:6], rg_3r);
AND2 I521 (rd_3r0[5:5], df_0[7:7], rg_3r);
AND2 I522 (rd_3r0[6:6], df_0[8:8], rg_3r);
AND2 I523 (rd_3r0[7:7], df_0[9:9], rg_3r);
AND2 I524 (rd_3r0[8:8], df_0[10:10], rg_3r);
AND2 I525 (rd_3r0[9:9], df_0[11:11], rg_3r);
AND2 I526 (rd_3r0[10:10], df_0[12:12], rg_3r);
AND2 I527 (rd_3r0[11:11], df_0[13:13], rg_3r);
AND2 I528 (rd_3r0[12:12], df_0[14:14], rg_3r);
AND2 I529 (rd_3r0[13:13], df_0[15:15], rg_3r);
AND2 I530 (rd_3r0[14:14], df_0[16:16], rg_3r);
AND2 I531 (rd_3r0[15:15], df_0[17:17], rg_3r);
AND2 I532 (rd_3r0[16:16], df_0[18:18], rg_3r);
AND2 I533 (rd_3r0[17:17], df_0[19:19], rg_3r);
AND2 I534 (rd_3r0[18:18], df_0[20:20], rg_3r);
AND2 I535 (rd_3r0[19:19], df_0[21:21], rg_3r);
AND2 I536 (rd_3r0[20:20], df_0[22:22], rg_3r);
AND2 I537 (rd_3r0[21:21], df_0[23:23], rg_3r);
AND2 I538 (rd_3r0[22:22], df_0[24:24], rg_3r);
AND2 I539 (rd_3r0[23:23], df_0[25:25], rg_3r);
AND2 I540 (rd_3r0[24:24], df_0[26:26], rg_3r);
AND2 I541 (rd_3r0[25:25], df_0[27:27], rg_3r);
AND2 I542 (rd_3r0[26:26], df_0[28:28], rg_3r);
AND2 I543 (rd_3r0[27:27], df_0[29:29], rg_3r);
AND2 I544 (rd_3r0[28:28], df_0[30:30], rg_3r);
AND2 I545 (rd_3r0[29:29], df_0[31:31], rg_3r);
AND2 I546 (rd_0r1[0:0], dt_0[0:0], rg_0r);
AND2 I547 (rd_0r1[1:1], dt_0[1:1], rg_0r);
AND2 I548 (rd_0r1[2:2], dt_0[2:2], rg_0r);
AND2 I549 (rd_0r1[3:3], dt_0[3:3], rg_0r);
AND2 I550 (rd_0r1[4:4], dt_0[4:4], rg_0r);
AND2 I551 (rd_0r1[5:5], dt_0[5:5], rg_0r);
AND2 I552 (rd_0r1[6:6], dt_0[6:6], rg_0r);
AND2 I553 (rd_0r1[7:7], dt_0[7:7], rg_0r);
AND2 I554 (rd_0r1[8:8], dt_0[8:8], rg_0r);
AND2 I555 (rd_0r1[9:9], dt_0[9:9], rg_0r);
AND2 I556 (rd_0r1[10:10], dt_0[10:10], rg_0r);
AND2 I557 (rd_0r1[11:11], dt_0[11:11], rg_0r);
AND2 I558 (rd_0r1[12:12], dt_0[12:12], rg_0r);
AND2 I559 (rd_0r1[13:13], dt_0[13:13], rg_0r);
AND2 I560 (rd_0r1[14:14], dt_0[14:14], rg_0r);
AND2 I561 (rd_0r1[15:15], dt_0[15:15], rg_0r);
AND2 I562 (rd_0r1[16:16], dt_0[16:16], rg_0r);
AND2 I563 (rd_0r1[17:17], dt_0[17:17], rg_0r);
AND2 I564 (rd_0r1[18:18], dt_0[18:18], rg_0r);
AND2 I565 (rd_0r1[19:19], dt_0[19:19], rg_0r);
AND2 I566 (rd_0r1[20:20], dt_0[20:20], rg_0r);
AND2 I567 (rd_0r1[21:21], dt_0[21:21], rg_0r);
AND2 I568 (rd_0r1[22:22], dt_0[22:22], rg_0r);
AND2 I569 (rd_0r1[23:23], dt_0[23:23], rg_0r);
AND2 I570 (rd_0r1[24:24], dt_0[24:24], rg_0r);
AND2 I571 (rd_0r1[25:25], dt_0[25:25], rg_0r);
AND2 I572 (rd_0r1[26:26], dt_0[26:26], rg_0r);
AND2 I573 (rd_0r1[27:27], dt_0[27:27], rg_0r);
AND2 I574 (rd_0r1[28:28], dt_0[28:28], rg_0r);
AND2 I575 (rd_0r1[29:29], dt_0[29:29], rg_0r);
AND2 I576 (rd_0r1[30:30], dt_0[30:30], rg_0r);
AND2 I577 (rd_0r1[31:31], dt_0[31:31], rg_0r);
AND2 I578 (rd_1r1[0:0], dt_0[0:0], rg_1r);
AND2 I579 (rd_1r1[1:1], dt_0[1:1], rg_1r);
AND2 I580 (rd_1r1[2:2], dt_0[2:2], rg_1r);
AND2 I581 (rd_1r1[3:3], dt_0[3:3], rg_1r);
AND2 I582 (rd_1r1[4:4], dt_0[4:4], rg_1r);
AND2 I583 (rd_1r1[5:5], dt_0[5:5], rg_1r);
AND2 I584 (rd_1r1[6:6], dt_0[6:6], rg_1r);
AND2 I585 (rd_1r1[7:7], dt_0[7:7], rg_1r);
AND2 I586 (rd_1r1[8:8], dt_0[8:8], rg_1r);
AND2 I587 (rd_1r1[9:9], dt_0[9:9], rg_1r);
AND2 I588 (rd_1r1[10:10], dt_0[10:10], rg_1r);
AND2 I589 (rd_1r1[11:11], dt_0[11:11], rg_1r);
AND2 I590 (rd_1r1[12:12], dt_0[12:12], rg_1r);
AND2 I591 (rd_1r1[13:13], dt_0[13:13], rg_1r);
AND2 I592 (rd_1r1[14:14], dt_0[14:14], rg_1r);
AND2 I593 (rd_1r1[15:15], dt_0[15:15], rg_1r);
AND2 I594 (rd_1r1[16:16], dt_0[16:16], rg_1r);
AND2 I595 (rd_1r1[17:17], dt_0[17:17], rg_1r);
AND2 I596 (rd_1r1[18:18], dt_0[18:18], rg_1r);
AND2 I597 (rd_1r1[19:19], dt_0[19:19], rg_1r);
AND2 I598 (rd_1r1[20:20], dt_0[20:20], rg_1r);
AND2 I599 (rd_1r1[21:21], dt_0[21:21], rg_1r);
AND2 I600 (rd_1r1[22:22], dt_0[22:22], rg_1r);
AND2 I601 (rd_1r1[23:23], dt_0[23:23], rg_1r);
AND2 I602 (rd_1r1[24:24], dt_0[24:24], rg_1r);
AND2 I603 (rd_1r1[25:25], dt_0[25:25], rg_1r);
AND2 I604 (rd_1r1[26:26], dt_0[26:26], rg_1r);
AND2 I605 (rd_1r1[27:27], dt_0[27:27], rg_1r);
AND2 I606 (rd_1r1[28:28], dt_0[28:28], rg_1r);
AND2 I607 (rd_1r1[29:29], dt_0[29:29], rg_1r);
AND2 I608 (rd_2r1[0:0], dt_0[2:2], rg_2r);
AND2 I609 (rd_2r1[1:1], dt_0[3:3], rg_2r);
AND2 I610 (rd_2r1[2:2], dt_0[4:4], rg_2r);
AND2 I611 (rd_2r1[3:3], dt_0[5:5], rg_2r);
AND2 I612 (rd_2r1[4:4], dt_0[6:6], rg_2r);
AND2 I613 (rd_2r1[5:5], dt_0[7:7], rg_2r);
AND2 I614 (rd_2r1[6:6], dt_0[8:8], rg_2r);
AND2 I615 (rd_2r1[7:7], dt_0[9:9], rg_2r);
AND2 I616 (rd_2r1[8:8], dt_0[10:10], rg_2r);
AND2 I617 (rd_2r1[9:9], dt_0[11:11], rg_2r);
AND2 I618 (rd_2r1[10:10], dt_0[12:12], rg_2r);
AND2 I619 (rd_2r1[11:11], dt_0[13:13], rg_2r);
AND2 I620 (rd_2r1[12:12], dt_0[14:14], rg_2r);
AND2 I621 (rd_2r1[13:13], dt_0[15:15], rg_2r);
AND2 I622 (rd_2r1[14:14], dt_0[16:16], rg_2r);
AND2 I623 (rd_2r1[15:15], dt_0[17:17], rg_2r);
AND2 I624 (rd_2r1[16:16], dt_0[18:18], rg_2r);
AND2 I625 (rd_2r1[17:17], dt_0[19:19], rg_2r);
AND2 I626 (rd_2r1[18:18], dt_0[20:20], rg_2r);
AND2 I627 (rd_2r1[19:19], dt_0[21:21], rg_2r);
AND2 I628 (rd_2r1[20:20], dt_0[22:22], rg_2r);
AND2 I629 (rd_2r1[21:21], dt_0[23:23], rg_2r);
AND2 I630 (rd_2r1[22:22], dt_0[24:24], rg_2r);
AND2 I631 (rd_2r1[23:23], dt_0[25:25], rg_2r);
AND2 I632 (rd_2r1[24:24], dt_0[26:26], rg_2r);
AND2 I633 (rd_2r1[25:25], dt_0[27:27], rg_2r);
AND2 I634 (rd_2r1[26:26], dt_0[28:28], rg_2r);
AND2 I635 (rd_2r1[27:27], dt_0[29:29], rg_2r);
AND2 I636 (rd_2r1[28:28], dt_0[30:30], rg_2r);
AND2 I637 (rd_2r1[29:29], dt_0[31:31], rg_2r);
AND2 I638 (rd_3r1[0:0], dt_0[2:2], rg_3r);
AND2 I639 (rd_3r1[1:1], dt_0[3:3], rg_3r);
AND2 I640 (rd_3r1[2:2], dt_0[4:4], rg_3r);
AND2 I641 (rd_3r1[3:3], dt_0[5:5], rg_3r);
AND2 I642 (rd_3r1[4:4], dt_0[6:6], rg_3r);
AND2 I643 (rd_3r1[5:5], dt_0[7:7], rg_3r);
AND2 I644 (rd_3r1[6:6], dt_0[8:8], rg_3r);
AND2 I645 (rd_3r1[7:7], dt_0[9:9], rg_3r);
AND2 I646 (rd_3r1[8:8], dt_0[10:10], rg_3r);
AND2 I647 (rd_3r1[9:9], dt_0[11:11], rg_3r);
AND2 I648 (rd_3r1[10:10], dt_0[12:12], rg_3r);
AND2 I649 (rd_3r1[11:11], dt_0[13:13], rg_3r);
AND2 I650 (rd_3r1[12:12], dt_0[14:14], rg_3r);
AND2 I651 (rd_3r1[13:13], dt_0[15:15], rg_3r);
AND2 I652 (rd_3r1[14:14], dt_0[16:16], rg_3r);
AND2 I653 (rd_3r1[15:15], dt_0[17:17], rg_3r);
AND2 I654 (rd_3r1[16:16], dt_0[18:18], rg_3r);
AND2 I655 (rd_3r1[17:17], dt_0[19:19], rg_3r);
AND2 I656 (rd_3r1[18:18], dt_0[20:20], rg_3r);
AND2 I657 (rd_3r1[19:19], dt_0[21:21], rg_3r);
AND2 I658 (rd_3r1[20:20], dt_0[22:22], rg_3r);
AND2 I659 (rd_3r1[21:21], dt_0[23:23], rg_3r);
AND2 I660 (rd_3r1[22:22], dt_0[24:24], rg_3r);
AND2 I661 (rd_3r1[23:23], dt_0[25:25], rg_3r);
AND2 I662 (rd_3r1[24:24], dt_0[26:26], rg_3r);
AND2 I663 (rd_3r1[25:25], dt_0[27:27], rg_3r);
AND2 I664 (rd_3r1[26:26], dt_0[28:28], rg_3r);
AND2 I665 (rd_3r1[27:27], dt_0[29:29], rg_3r);
AND2 I666 (rd_3r1[28:28], dt_0[30:30], rg_3r);
AND2 I667 (rd_3r1[29:29], dt_0[31:31], rg_3r);
NOR3 I668 (simp6521_0[0:0], rg_0r, rg_1r, rg_2r);
NOR3 I669 (simp6521_0[1:1], rg_3r, rg_0a, rg_1a);
NOR2 I670 (simp6521_0[2:2], rg_2a, rg_3a);
NAND3 I671 (anyread_0, simp6521_0[0:0], simp6521_0[1:1], simp6521_0[2:2]);
BUFF I672 (wg_0a, wd_0a);
BUFF I673 (rg_0a, rd_0a);
BUFF I674 (rg_1a, rd_1a);
BUFF I675 (rg_2a, rd_2a);
BUFF I676 (rg_3a, rd_3a);
endmodule
// tkm4x32b TeakM [Many [32,32,32,32],One 32]
module tkm4x32b (i_0r0, i_0r1, i_0a, i_1r0, i_1r1, i_1a, i_2r0, i_2r1, i_2a, i_3r0, i_3r1, i_3a, o_0r0, o_0r1, o_0a, reset);
input [31:0] i_0r0;
input [31:0] i_0r1;
output i_0a;
input [31:0] i_1r0;
input [31:0] i_1r1;
output i_1a;
input [31:0] i_2r0;
input [31:0] i_2r1;
output i_2a;
input [31:0] i_3r0;
input [31:0] i_3r1;
output i_3a;
output [31:0] o_0r0;
output [31:0] o_0r1;
input o_0a;
input reset;
wire [31:0] gfint_0;
wire [31:0] gfint_1;
wire [31:0] gfint_2;
wire [31:0] gfint_3;
wire [31:0] gtint_0;
wire [31:0] gtint_1;
wire [31:0] gtint_2;
wire [31:0] gtint_3;
wire choice_0;
wire choice_1;
wire choice_2;
wire choice_3;
wire anychoice_0;
wire icomp_0;
wire icomp_1;
wire icomp_2;
wire icomp_3;
wire nchosen_0;
wire [1:0] simp181_0;
wire [1:0] simp191_0;
wire [1:0] simp201_0;
wire [1:0] simp211_0;
wire [1:0] simp221_0;
wire [1:0] simp231_0;
wire [1:0] simp241_0;
wire [1:0] simp251_0;
wire [1:0] simp261_0;
wire [1:0] simp271_0;
wire [1:0] simp281_0;
wire [1:0] simp291_0;
wire [1:0] simp301_0;
wire [1:0] simp311_0;
wire [1:0] simp321_0;
wire [1:0] simp331_0;
wire [1:0] simp341_0;
wire [1:0] simp351_0;
wire [1:0] simp361_0;
wire [1:0] simp371_0;
wire [1:0] simp381_0;
wire [1:0] simp391_0;
wire [1:0] simp401_0;
wire [1:0] simp411_0;
wire [1:0] simp421_0;
wire [1:0] simp431_0;
wire [1:0] simp441_0;
wire [1:0] simp451_0;
wire [1:0] simp461_0;
wire [1:0] simp471_0;
wire [1:0] simp481_0;
wire [1:0] simp491_0;
wire [1:0] simp501_0;
wire [1:0] simp511_0;
wire [1:0] simp521_0;
wire [1:0] simp531_0;
wire [1:0] simp541_0;
wire [1:0] simp551_0;
wire [1:0] simp561_0;
wire [1:0] simp571_0;
wire [1:0] simp581_0;
wire [1:0] simp591_0;
wire [1:0] simp601_0;
wire [1:0] simp611_0;
wire [1:0] simp621_0;
wire [1:0] simp631_0;
wire [1:0] simp641_0;
wire [1:0] simp651_0;
wire [1:0] simp661_0;
wire [1:0] simp671_0;
wire [1:0] simp681_0;
wire [1:0] simp691_0;
wire [1:0] simp701_0;
wire [1:0] simp711_0;
wire [1:0] simp721_0;
wire [1:0] simp731_0;
wire [1:0] simp741_0;
wire [1:0] simp751_0;
wire [1:0] simp761_0;
wire [1:0] simp771_0;
wire [1:0] simp781_0;
wire [1:0] simp791_0;
wire [1:0] simp801_0;
wire [1:0] simp811_0;
wire [31:0] comp0_0;
wire [10:0] simp3711_0;
wire [3:0] simp3712_0;
wire [1:0] simp3713_0;
wire [31:0] comp1_0;
wire [10:0] simp4051_0;
wire [3:0] simp4052_0;
wire [1:0] simp4053_0;
wire [31:0] comp2_0;
wire [10:0] simp4391_0;
wire [3:0] simp4392_0;
wire [1:0] simp4393_0;
wire [31:0] comp3_0;
wire [10:0] simp4731_0;
wire [3:0] simp4732_0;
wire [1:0] simp4733_0;
wire [1:0] simp4781_0;
NOR3 I0 (simp181_0[0:0], gfint_0[0:0], gfint_1[0:0], gfint_2[0:0]);
INV I1 (simp181_0[1:1], gfint_3[0:0]);
NAND2 I2 (o_0r0[0:0], simp181_0[0:0], simp181_0[1:1]);
NOR3 I3 (simp191_0[0:0], gfint_0[1:1], gfint_1[1:1], gfint_2[1:1]);
INV I4 (simp191_0[1:1], gfint_3[1:1]);
NAND2 I5 (o_0r0[1:1], simp191_0[0:0], simp191_0[1:1]);
NOR3 I6 (simp201_0[0:0], gfint_0[2:2], gfint_1[2:2], gfint_2[2:2]);
INV I7 (simp201_0[1:1], gfint_3[2:2]);
NAND2 I8 (o_0r0[2:2], simp201_0[0:0], simp201_0[1:1]);
NOR3 I9 (simp211_0[0:0], gfint_0[3:3], gfint_1[3:3], gfint_2[3:3]);
INV I10 (simp211_0[1:1], gfint_3[3:3]);
NAND2 I11 (o_0r0[3:3], simp211_0[0:0], simp211_0[1:1]);
NOR3 I12 (simp221_0[0:0], gfint_0[4:4], gfint_1[4:4], gfint_2[4:4]);
INV I13 (simp221_0[1:1], gfint_3[4:4]);
NAND2 I14 (o_0r0[4:4], simp221_0[0:0], simp221_0[1:1]);
NOR3 I15 (simp231_0[0:0], gfint_0[5:5], gfint_1[5:5], gfint_2[5:5]);
INV I16 (simp231_0[1:1], gfint_3[5:5]);
NAND2 I17 (o_0r0[5:5], simp231_0[0:0], simp231_0[1:1]);
NOR3 I18 (simp241_0[0:0], gfint_0[6:6], gfint_1[6:6], gfint_2[6:6]);
INV I19 (simp241_0[1:1], gfint_3[6:6]);
NAND2 I20 (o_0r0[6:6], simp241_0[0:0], simp241_0[1:1]);
NOR3 I21 (simp251_0[0:0], gfint_0[7:7], gfint_1[7:7], gfint_2[7:7]);
INV I22 (simp251_0[1:1], gfint_3[7:7]);
NAND2 I23 (o_0r0[7:7], simp251_0[0:0], simp251_0[1:1]);
NOR3 I24 (simp261_0[0:0], gfint_0[8:8], gfint_1[8:8], gfint_2[8:8]);
INV I25 (simp261_0[1:1], gfint_3[8:8]);
NAND2 I26 (o_0r0[8:8], simp261_0[0:0], simp261_0[1:1]);
NOR3 I27 (simp271_0[0:0], gfint_0[9:9], gfint_1[9:9], gfint_2[9:9]);
INV I28 (simp271_0[1:1], gfint_3[9:9]);
NAND2 I29 (o_0r0[9:9], simp271_0[0:0], simp271_0[1:1]);
NOR3 I30 (simp281_0[0:0], gfint_0[10:10], gfint_1[10:10], gfint_2[10:10]);
INV I31 (simp281_0[1:1], gfint_3[10:10]);
NAND2 I32 (o_0r0[10:10], simp281_0[0:0], simp281_0[1:1]);
NOR3 I33 (simp291_0[0:0], gfint_0[11:11], gfint_1[11:11], gfint_2[11:11]);
INV I34 (simp291_0[1:1], gfint_3[11:11]);
NAND2 I35 (o_0r0[11:11], simp291_0[0:0], simp291_0[1:1]);
NOR3 I36 (simp301_0[0:0], gfint_0[12:12], gfint_1[12:12], gfint_2[12:12]);
INV I37 (simp301_0[1:1], gfint_3[12:12]);
NAND2 I38 (o_0r0[12:12], simp301_0[0:0], simp301_0[1:1]);
NOR3 I39 (simp311_0[0:0], gfint_0[13:13], gfint_1[13:13], gfint_2[13:13]);
INV I40 (simp311_0[1:1], gfint_3[13:13]);
NAND2 I41 (o_0r0[13:13], simp311_0[0:0], simp311_0[1:1]);
NOR3 I42 (simp321_0[0:0], gfint_0[14:14], gfint_1[14:14], gfint_2[14:14]);
INV I43 (simp321_0[1:1], gfint_3[14:14]);
NAND2 I44 (o_0r0[14:14], simp321_0[0:0], simp321_0[1:1]);
NOR3 I45 (simp331_0[0:0], gfint_0[15:15], gfint_1[15:15], gfint_2[15:15]);
INV I46 (simp331_0[1:1], gfint_3[15:15]);
NAND2 I47 (o_0r0[15:15], simp331_0[0:0], simp331_0[1:1]);
NOR3 I48 (simp341_0[0:0], gfint_0[16:16], gfint_1[16:16], gfint_2[16:16]);
INV I49 (simp341_0[1:1], gfint_3[16:16]);
NAND2 I50 (o_0r0[16:16], simp341_0[0:0], simp341_0[1:1]);
NOR3 I51 (simp351_0[0:0], gfint_0[17:17], gfint_1[17:17], gfint_2[17:17]);
INV I52 (simp351_0[1:1], gfint_3[17:17]);
NAND2 I53 (o_0r0[17:17], simp351_0[0:0], simp351_0[1:1]);
NOR3 I54 (simp361_0[0:0], gfint_0[18:18], gfint_1[18:18], gfint_2[18:18]);
INV I55 (simp361_0[1:1], gfint_3[18:18]);
NAND2 I56 (o_0r0[18:18], simp361_0[0:0], simp361_0[1:1]);
NOR3 I57 (simp371_0[0:0], gfint_0[19:19], gfint_1[19:19], gfint_2[19:19]);
INV I58 (simp371_0[1:1], gfint_3[19:19]);
NAND2 I59 (o_0r0[19:19], simp371_0[0:0], simp371_0[1:1]);
NOR3 I60 (simp381_0[0:0], gfint_0[20:20], gfint_1[20:20], gfint_2[20:20]);
INV I61 (simp381_0[1:1], gfint_3[20:20]);
NAND2 I62 (o_0r0[20:20], simp381_0[0:0], simp381_0[1:1]);
NOR3 I63 (simp391_0[0:0], gfint_0[21:21], gfint_1[21:21], gfint_2[21:21]);
INV I64 (simp391_0[1:1], gfint_3[21:21]);
NAND2 I65 (o_0r0[21:21], simp391_0[0:0], simp391_0[1:1]);
NOR3 I66 (simp401_0[0:0], gfint_0[22:22], gfint_1[22:22], gfint_2[22:22]);
INV I67 (simp401_0[1:1], gfint_3[22:22]);
NAND2 I68 (o_0r0[22:22], simp401_0[0:0], simp401_0[1:1]);
NOR3 I69 (simp411_0[0:0], gfint_0[23:23], gfint_1[23:23], gfint_2[23:23]);
INV I70 (simp411_0[1:1], gfint_3[23:23]);
NAND2 I71 (o_0r0[23:23], simp411_0[0:0], simp411_0[1:1]);
NOR3 I72 (simp421_0[0:0], gfint_0[24:24], gfint_1[24:24], gfint_2[24:24]);
INV I73 (simp421_0[1:1], gfint_3[24:24]);
NAND2 I74 (o_0r0[24:24], simp421_0[0:0], simp421_0[1:1]);
NOR3 I75 (simp431_0[0:0], gfint_0[25:25], gfint_1[25:25], gfint_2[25:25]);
INV I76 (simp431_0[1:1], gfint_3[25:25]);
NAND2 I77 (o_0r0[25:25], simp431_0[0:0], simp431_0[1:1]);
NOR3 I78 (simp441_0[0:0], gfint_0[26:26], gfint_1[26:26], gfint_2[26:26]);
INV I79 (simp441_0[1:1], gfint_3[26:26]);
NAND2 I80 (o_0r0[26:26], simp441_0[0:0], simp441_0[1:1]);
NOR3 I81 (simp451_0[0:0], gfint_0[27:27], gfint_1[27:27], gfint_2[27:27]);
INV I82 (simp451_0[1:1], gfint_3[27:27]);
NAND2 I83 (o_0r0[27:27], simp451_0[0:0], simp451_0[1:1]);
NOR3 I84 (simp461_0[0:0], gfint_0[28:28], gfint_1[28:28], gfint_2[28:28]);
INV I85 (simp461_0[1:1], gfint_3[28:28]);
NAND2 I86 (o_0r0[28:28], simp461_0[0:0], simp461_0[1:1]);
NOR3 I87 (simp471_0[0:0], gfint_0[29:29], gfint_1[29:29], gfint_2[29:29]);
INV I88 (simp471_0[1:1], gfint_3[29:29]);
NAND2 I89 (o_0r0[29:29], simp471_0[0:0], simp471_0[1:1]);
NOR3 I90 (simp481_0[0:0], gfint_0[30:30], gfint_1[30:30], gfint_2[30:30]);
INV I91 (simp481_0[1:1], gfint_3[30:30]);
NAND2 I92 (o_0r0[30:30], simp481_0[0:0], simp481_0[1:1]);
NOR3 I93 (simp491_0[0:0], gfint_0[31:31], gfint_1[31:31], gfint_2[31:31]);
INV I94 (simp491_0[1:1], gfint_3[31:31]);
NAND2 I95 (o_0r0[31:31], simp491_0[0:0], simp491_0[1:1]);
NOR3 I96 (simp501_0[0:0], gtint_0[0:0], gtint_1[0:0], gtint_2[0:0]);
INV I97 (simp501_0[1:1], gtint_3[0:0]);
NAND2 I98 (o_0r1[0:0], simp501_0[0:0], simp501_0[1:1]);
NOR3 I99 (simp511_0[0:0], gtint_0[1:1], gtint_1[1:1], gtint_2[1:1]);
INV I100 (simp511_0[1:1], gtint_3[1:1]);
NAND2 I101 (o_0r1[1:1], simp511_0[0:0], simp511_0[1:1]);
NOR3 I102 (simp521_0[0:0], gtint_0[2:2], gtint_1[2:2], gtint_2[2:2]);
INV I103 (simp521_0[1:1], gtint_3[2:2]);
NAND2 I104 (o_0r1[2:2], simp521_0[0:0], simp521_0[1:1]);
NOR3 I105 (simp531_0[0:0], gtint_0[3:3], gtint_1[3:3], gtint_2[3:3]);
INV I106 (simp531_0[1:1], gtint_3[3:3]);
NAND2 I107 (o_0r1[3:3], simp531_0[0:0], simp531_0[1:1]);
NOR3 I108 (simp541_0[0:0], gtint_0[4:4], gtint_1[4:4], gtint_2[4:4]);
INV I109 (simp541_0[1:1], gtint_3[4:4]);
NAND2 I110 (o_0r1[4:4], simp541_0[0:0], simp541_0[1:1]);
NOR3 I111 (simp551_0[0:0], gtint_0[5:5], gtint_1[5:5], gtint_2[5:5]);
INV I112 (simp551_0[1:1], gtint_3[5:5]);
NAND2 I113 (o_0r1[5:5], simp551_0[0:0], simp551_0[1:1]);
NOR3 I114 (simp561_0[0:0], gtint_0[6:6], gtint_1[6:6], gtint_2[6:6]);
INV I115 (simp561_0[1:1], gtint_3[6:6]);
NAND2 I116 (o_0r1[6:6], simp561_0[0:0], simp561_0[1:1]);
NOR3 I117 (simp571_0[0:0], gtint_0[7:7], gtint_1[7:7], gtint_2[7:7]);
INV I118 (simp571_0[1:1], gtint_3[7:7]);
NAND2 I119 (o_0r1[7:7], simp571_0[0:0], simp571_0[1:1]);
NOR3 I120 (simp581_0[0:0], gtint_0[8:8], gtint_1[8:8], gtint_2[8:8]);
INV I121 (simp581_0[1:1], gtint_3[8:8]);
NAND2 I122 (o_0r1[8:8], simp581_0[0:0], simp581_0[1:1]);
NOR3 I123 (simp591_0[0:0], gtint_0[9:9], gtint_1[9:9], gtint_2[9:9]);
INV I124 (simp591_0[1:1], gtint_3[9:9]);
NAND2 I125 (o_0r1[9:9], simp591_0[0:0], simp591_0[1:1]);
NOR3 I126 (simp601_0[0:0], gtint_0[10:10], gtint_1[10:10], gtint_2[10:10]);
INV I127 (simp601_0[1:1], gtint_3[10:10]);
NAND2 I128 (o_0r1[10:10], simp601_0[0:0], simp601_0[1:1]);
NOR3 I129 (simp611_0[0:0], gtint_0[11:11], gtint_1[11:11], gtint_2[11:11]);
INV I130 (simp611_0[1:1], gtint_3[11:11]);
NAND2 I131 (o_0r1[11:11], simp611_0[0:0], simp611_0[1:1]);
NOR3 I132 (simp621_0[0:0], gtint_0[12:12], gtint_1[12:12], gtint_2[12:12]);
INV I133 (simp621_0[1:1], gtint_3[12:12]);
NAND2 I134 (o_0r1[12:12], simp621_0[0:0], simp621_0[1:1]);
NOR3 I135 (simp631_0[0:0], gtint_0[13:13], gtint_1[13:13], gtint_2[13:13]);
INV I136 (simp631_0[1:1], gtint_3[13:13]);
NAND2 I137 (o_0r1[13:13], simp631_0[0:0], simp631_0[1:1]);
NOR3 I138 (simp641_0[0:0], gtint_0[14:14], gtint_1[14:14], gtint_2[14:14]);
INV I139 (simp641_0[1:1], gtint_3[14:14]);
NAND2 I140 (o_0r1[14:14], simp641_0[0:0], simp641_0[1:1]);
NOR3 I141 (simp651_0[0:0], gtint_0[15:15], gtint_1[15:15], gtint_2[15:15]);
INV I142 (simp651_0[1:1], gtint_3[15:15]);
NAND2 I143 (o_0r1[15:15], simp651_0[0:0], simp651_0[1:1]);
NOR3 I144 (simp661_0[0:0], gtint_0[16:16], gtint_1[16:16], gtint_2[16:16]);
INV I145 (simp661_0[1:1], gtint_3[16:16]);
NAND2 I146 (o_0r1[16:16], simp661_0[0:0], simp661_0[1:1]);
NOR3 I147 (simp671_0[0:0], gtint_0[17:17], gtint_1[17:17], gtint_2[17:17]);
INV I148 (simp671_0[1:1], gtint_3[17:17]);
NAND2 I149 (o_0r1[17:17], simp671_0[0:0], simp671_0[1:1]);
NOR3 I150 (simp681_0[0:0], gtint_0[18:18], gtint_1[18:18], gtint_2[18:18]);
INV I151 (simp681_0[1:1], gtint_3[18:18]);
NAND2 I152 (o_0r1[18:18], simp681_0[0:0], simp681_0[1:1]);
NOR3 I153 (simp691_0[0:0], gtint_0[19:19], gtint_1[19:19], gtint_2[19:19]);
INV I154 (simp691_0[1:1], gtint_3[19:19]);
NAND2 I155 (o_0r1[19:19], simp691_0[0:0], simp691_0[1:1]);
NOR3 I156 (simp701_0[0:0], gtint_0[20:20], gtint_1[20:20], gtint_2[20:20]);
INV I157 (simp701_0[1:1], gtint_3[20:20]);
NAND2 I158 (o_0r1[20:20], simp701_0[0:0], simp701_0[1:1]);
NOR3 I159 (simp711_0[0:0], gtint_0[21:21], gtint_1[21:21], gtint_2[21:21]);
INV I160 (simp711_0[1:1], gtint_3[21:21]);
NAND2 I161 (o_0r1[21:21], simp711_0[0:0], simp711_0[1:1]);
NOR3 I162 (simp721_0[0:0], gtint_0[22:22], gtint_1[22:22], gtint_2[22:22]);
INV I163 (simp721_0[1:1], gtint_3[22:22]);
NAND2 I164 (o_0r1[22:22], simp721_0[0:0], simp721_0[1:1]);
NOR3 I165 (simp731_0[0:0], gtint_0[23:23], gtint_1[23:23], gtint_2[23:23]);
INV I166 (simp731_0[1:1], gtint_3[23:23]);
NAND2 I167 (o_0r1[23:23], simp731_0[0:0], simp731_0[1:1]);
NOR3 I168 (simp741_0[0:0], gtint_0[24:24], gtint_1[24:24], gtint_2[24:24]);
INV I169 (simp741_0[1:1], gtint_3[24:24]);
NAND2 I170 (o_0r1[24:24], simp741_0[0:0], simp741_0[1:1]);
NOR3 I171 (simp751_0[0:0], gtint_0[25:25], gtint_1[25:25], gtint_2[25:25]);
INV I172 (simp751_0[1:1], gtint_3[25:25]);
NAND2 I173 (o_0r1[25:25], simp751_0[0:0], simp751_0[1:1]);
NOR3 I174 (simp761_0[0:0], gtint_0[26:26], gtint_1[26:26], gtint_2[26:26]);
INV I175 (simp761_0[1:1], gtint_3[26:26]);
NAND2 I176 (o_0r1[26:26], simp761_0[0:0], simp761_0[1:1]);
NOR3 I177 (simp771_0[0:0], gtint_0[27:27], gtint_1[27:27], gtint_2[27:27]);
INV I178 (simp771_0[1:1], gtint_3[27:27]);
NAND2 I179 (o_0r1[27:27], simp771_0[0:0], simp771_0[1:1]);
NOR3 I180 (simp781_0[0:0], gtint_0[28:28], gtint_1[28:28], gtint_2[28:28]);
INV I181 (simp781_0[1:1], gtint_3[28:28]);
NAND2 I182 (o_0r1[28:28], simp781_0[0:0], simp781_0[1:1]);
NOR3 I183 (simp791_0[0:0], gtint_0[29:29], gtint_1[29:29], gtint_2[29:29]);
INV I184 (simp791_0[1:1], gtint_3[29:29]);
NAND2 I185 (o_0r1[29:29], simp791_0[0:0], simp791_0[1:1]);
NOR3 I186 (simp801_0[0:0], gtint_0[30:30], gtint_1[30:30], gtint_2[30:30]);
INV I187 (simp801_0[1:1], gtint_3[30:30]);
NAND2 I188 (o_0r1[30:30], simp801_0[0:0], simp801_0[1:1]);
NOR3 I189 (simp811_0[0:0], gtint_0[31:31], gtint_1[31:31], gtint_2[31:31]);
INV I190 (simp811_0[1:1], gtint_3[31:31]);
NAND2 I191 (o_0r1[31:31], simp811_0[0:0], simp811_0[1:1]);
AND2 I192 (gtint_0[0:0], choice_0, i_0r1[0:0]);
AND2 I193 (gtint_0[1:1], choice_0, i_0r1[1:1]);
AND2 I194 (gtint_0[2:2], choice_0, i_0r1[2:2]);
AND2 I195 (gtint_0[3:3], choice_0, i_0r1[3:3]);
AND2 I196 (gtint_0[4:4], choice_0, i_0r1[4:4]);
AND2 I197 (gtint_0[5:5], choice_0, i_0r1[5:5]);
AND2 I198 (gtint_0[6:6], choice_0, i_0r1[6:6]);
AND2 I199 (gtint_0[7:7], choice_0, i_0r1[7:7]);
AND2 I200 (gtint_0[8:8], choice_0, i_0r1[8:8]);
AND2 I201 (gtint_0[9:9], choice_0, i_0r1[9:9]);
AND2 I202 (gtint_0[10:10], choice_0, i_0r1[10:10]);
AND2 I203 (gtint_0[11:11], choice_0, i_0r1[11:11]);
AND2 I204 (gtint_0[12:12], choice_0, i_0r1[12:12]);
AND2 I205 (gtint_0[13:13], choice_0, i_0r1[13:13]);
AND2 I206 (gtint_0[14:14], choice_0, i_0r1[14:14]);
AND2 I207 (gtint_0[15:15], choice_0, i_0r1[15:15]);
AND2 I208 (gtint_0[16:16], choice_0, i_0r1[16:16]);
AND2 I209 (gtint_0[17:17], choice_0, i_0r1[17:17]);
AND2 I210 (gtint_0[18:18], choice_0, i_0r1[18:18]);
AND2 I211 (gtint_0[19:19], choice_0, i_0r1[19:19]);
AND2 I212 (gtint_0[20:20], choice_0, i_0r1[20:20]);
AND2 I213 (gtint_0[21:21], choice_0, i_0r1[21:21]);
AND2 I214 (gtint_0[22:22], choice_0, i_0r1[22:22]);
AND2 I215 (gtint_0[23:23], choice_0, i_0r1[23:23]);
AND2 I216 (gtint_0[24:24], choice_0, i_0r1[24:24]);
AND2 I217 (gtint_0[25:25], choice_0, i_0r1[25:25]);
AND2 I218 (gtint_0[26:26], choice_0, i_0r1[26:26]);
AND2 I219 (gtint_0[27:27], choice_0, i_0r1[27:27]);
AND2 I220 (gtint_0[28:28], choice_0, i_0r1[28:28]);
AND2 I221 (gtint_0[29:29], choice_0, i_0r1[29:29]);
AND2 I222 (gtint_0[30:30], choice_0, i_0r1[30:30]);
AND2 I223 (gtint_0[31:31], choice_0, i_0r1[31:31]);
AND2 I224 (gtint_1[0:0], choice_1, i_1r1[0:0]);
AND2 I225 (gtint_1[1:1], choice_1, i_1r1[1:1]);
AND2 I226 (gtint_1[2:2], choice_1, i_1r1[2:2]);
AND2 I227 (gtint_1[3:3], choice_1, i_1r1[3:3]);
AND2 I228 (gtint_1[4:4], choice_1, i_1r1[4:4]);
AND2 I229 (gtint_1[5:5], choice_1, i_1r1[5:5]);
AND2 I230 (gtint_1[6:6], choice_1, i_1r1[6:6]);
AND2 I231 (gtint_1[7:7], choice_1, i_1r1[7:7]);
AND2 I232 (gtint_1[8:8], choice_1, i_1r1[8:8]);
AND2 I233 (gtint_1[9:9], choice_1, i_1r1[9:9]);
AND2 I234 (gtint_1[10:10], choice_1, i_1r1[10:10]);
AND2 I235 (gtint_1[11:11], choice_1, i_1r1[11:11]);
AND2 I236 (gtint_1[12:12], choice_1, i_1r1[12:12]);
AND2 I237 (gtint_1[13:13], choice_1, i_1r1[13:13]);
AND2 I238 (gtint_1[14:14], choice_1, i_1r1[14:14]);
AND2 I239 (gtint_1[15:15], choice_1, i_1r1[15:15]);
AND2 I240 (gtint_1[16:16], choice_1, i_1r1[16:16]);
AND2 I241 (gtint_1[17:17], choice_1, i_1r1[17:17]);
AND2 I242 (gtint_1[18:18], choice_1, i_1r1[18:18]);
AND2 I243 (gtint_1[19:19], choice_1, i_1r1[19:19]);
AND2 I244 (gtint_1[20:20], choice_1, i_1r1[20:20]);
AND2 I245 (gtint_1[21:21], choice_1, i_1r1[21:21]);
AND2 I246 (gtint_1[22:22], choice_1, i_1r1[22:22]);
AND2 I247 (gtint_1[23:23], choice_1, i_1r1[23:23]);
AND2 I248 (gtint_1[24:24], choice_1, i_1r1[24:24]);
AND2 I249 (gtint_1[25:25], choice_1, i_1r1[25:25]);
AND2 I250 (gtint_1[26:26], choice_1, i_1r1[26:26]);
AND2 I251 (gtint_1[27:27], choice_1, i_1r1[27:27]);
AND2 I252 (gtint_1[28:28], choice_1, i_1r1[28:28]);
AND2 I253 (gtint_1[29:29], choice_1, i_1r1[29:29]);
AND2 I254 (gtint_1[30:30], choice_1, i_1r1[30:30]);
AND2 I255 (gtint_1[31:31], choice_1, i_1r1[31:31]);
AND2 I256 (gtint_2[0:0], choice_2, i_2r1[0:0]);
AND2 I257 (gtint_2[1:1], choice_2, i_2r1[1:1]);
AND2 I258 (gtint_2[2:2], choice_2, i_2r1[2:2]);
AND2 I259 (gtint_2[3:3], choice_2, i_2r1[3:3]);
AND2 I260 (gtint_2[4:4], choice_2, i_2r1[4:4]);
AND2 I261 (gtint_2[5:5], choice_2, i_2r1[5:5]);
AND2 I262 (gtint_2[6:6], choice_2, i_2r1[6:6]);
AND2 I263 (gtint_2[7:7], choice_2, i_2r1[7:7]);
AND2 I264 (gtint_2[8:8], choice_2, i_2r1[8:8]);
AND2 I265 (gtint_2[9:9], choice_2, i_2r1[9:9]);
AND2 I266 (gtint_2[10:10], choice_2, i_2r1[10:10]);
AND2 I267 (gtint_2[11:11], choice_2, i_2r1[11:11]);
AND2 I268 (gtint_2[12:12], choice_2, i_2r1[12:12]);
AND2 I269 (gtint_2[13:13], choice_2, i_2r1[13:13]);
AND2 I270 (gtint_2[14:14], choice_2, i_2r1[14:14]);
AND2 I271 (gtint_2[15:15], choice_2, i_2r1[15:15]);
AND2 I272 (gtint_2[16:16], choice_2, i_2r1[16:16]);
AND2 I273 (gtint_2[17:17], choice_2, i_2r1[17:17]);
AND2 I274 (gtint_2[18:18], choice_2, i_2r1[18:18]);
AND2 I275 (gtint_2[19:19], choice_2, i_2r1[19:19]);
AND2 I276 (gtint_2[20:20], choice_2, i_2r1[20:20]);
AND2 I277 (gtint_2[21:21], choice_2, i_2r1[21:21]);
AND2 I278 (gtint_2[22:22], choice_2, i_2r1[22:22]);
AND2 I279 (gtint_2[23:23], choice_2, i_2r1[23:23]);
AND2 I280 (gtint_2[24:24], choice_2, i_2r1[24:24]);
AND2 I281 (gtint_2[25:25], choice_2, i_2r1[25:25]);
AND2 I282 (gtint_2[26:26], choice_2, i_2r1[26:26]);
AND2 I283 (gtint_2[27:27], choice_2, i_2r1[27:27]);
AND2 I284 (gtint_2[28:28], choice_2, i_2r1[28:28]);
AND2 I285 (gtint_2[29:29], choice_2, i_2r1[29:29]);
AND2 I286 (gtint_2[30:30], choice_2, i_2r1[30:30]);
AND2 I287 (gtint_2[31:31], choice_2, i_2r1[31:31]);
AND2 I288 (gtint_3[0:0], choice_3, i_3r1[0:0]);
AND2 I289 (gtint_3[1:1], choice_3, i_3r1[1:1]);
AND2 I290 (gtint_3[2:2], choice_3, i_3r1[2:2]);
AND2 I291 (gtint_3[3:3], choice_3, i_3r1[3:3]);
AND2 I292 (gtint_3[4:4], choice_3, i_3r1[4:4]);
AND2 I293 (gtint_3[5:5], choice_3, i_3r1[5:5]);
AND2 I294 (gtint_3[6:6], choice_3, i_3r1[6:6]);
AND2 I295 (gtint_3[7:7], choice_3, i_3r1[7:7]);
AND2 I296 (gtint_3[8:8], choice_3, i_3r1[8:8]);
AND2 I297 (gtint_3[9:9], choice_3, i_3r1[9:9]);
AND2 I298 (gtint_3[10:10], choice_3, i_3r1[10:10]);
AND2 I299 (gtint_3[11:11], choice_3, i_3r1[11:11]);
AND2 I300 (gtint_3[12:12], choice_3, i_3r1[12:12]);
AND2 I301 (gtint_3[13:13], choice_3, i_3r1[13:13]);
AND2 I302 (gtint_3[14:14], choice_3, i_3r1[14:14]);
AND2 I303 (gtint_3[15:15], choice_3, i_3r1[15:15]);
AND2 I304 (gtint_3[16:16], choice_3, i_3r1[16:16]);
AND2 I305 (gtint_3[17:17], choice_3, i_3r1[17:17]);
AND2 I306 (gtint_3[18:18], choice_3, i_3r1[18:18]);
AND2 I307 (gtint_3[19:19], choice_3, i_3r1[19:19]);
AND2 I308 (gtint_3[20:20], choice_3, i_3r1[20:20]);
AND2 I309 (gtint_3[21:21], choice_3, i_3r1[21:21]);
AND2 I310 (gtint_3[22:22], choice_3, i_3r1[22:22]);
AND2 I311 (gtint_3[23:23], choice_3, i_3r1[23:23]);
AND2 I312 (gtint_3[24:24], choice_3, i_3r1[24:24]);
AND2 I313 (gtint_3[25:25], choice_3, i_3r1[25:25]);
AND2 I314 (gtint_3[26:26], choice_3, i_3r1[26:26]);
AND2 I315 (gtint_3[27:27], choice_3, i_3r1[27:27]);
AND2 I316 (gtint_3[28:28], choice_3, i_3r1[28:28]);
AND2 I317 (gtint_3[29:29], choice_3, i_3r1[29:29]);
AND2 I318 (gtint_3[30:30], choice_3, i_3r1[30:30]);
AND2 I319 (gtint_3[31:31], choice_3, i_3r1[31:31]);
AND2 I320 (gfint_0[0:0], choice_0, i_0r0[0:0]);
AND2 I321 (gfint_0[1:1], choice_0, i_0r0[1:1]);
AND2 I322 (gfint_0[2:2], choice_0, i_0r0[2:2]);
AND2 I323 (gfint_0[3:3], choice_0, i_0r0[3:3]);
AND2 I324 (gfint_0[4:4], choice_0, i_0r0[4:4]);
AND2 I325 (gfint_0[5:5], choice_0, i_0r0[5:5]);
AND2 I326 (gfint_0[6:6], choice_0, i_0r0[6:6]);
AND2 I327 (gfint_0[7:7], choice_0, i_0r0[7:7]);
AND2 I328 (gfint_0[8:8], choice_0, i_0r0[8:8]);
AND2 I329 (gfint_0[9:9], choice_0, i_0r0[9:9]);
AND2 I330 (gfint_0[10:10], choice_0, i_0r0[10:10]);
AND2 I331 (gfint_0[11:11], choice_0, i_0r0[11:11]);
AND2 I332 (gfint_0[12:12], choice_0, i_0r0[12:12]);
AND2 I333 (gfint_0[13:13], choice_0, i_0r0[13:13]);
AND2 I334 (gfint_0[14:14], choice_0, i_0r0[14:14]);
AND2 I335 (gfint_0[15:15], choice_0, i_0r0[15:15]);
AND2 I336 (gfint_0[16:16], choice_0, i_0r0[16:16]);
AND2 I337 (gfint_0[17:17], choice_0, i_0r0[17:17]);
AND2 I338 (gfint_0[18:18], choice_0, i_0r0[18:18]);
AND2 I339 (gfint_0[19:19], choice_0, i_0r0[19:19]);
AND2 I340 (gfint_0[20:20], choice_0, i_0r0[20:20]);
AND2 I341 (gfint_0[21:21], choice_0, i_0r0[21:21]);
AND2 I342 (gfint_0[22:22], choice_0, i_0r0[22:22]);
AND2 I343 (gfint_0[23:23], choice_0, i_0r0[23:23]);
AND2 I344 (gfint_0[24:24], choice_0, i_0r0[24:24]);
AND2 I345 (gfint_0[25:25], choice_0, i_0r0[25:25]);
AND2 I346 (gfint_0[26:26], choice_0, i_0r0[26:26]);
AND2 I347 (gfint_0[27:27], choice_0, i_0r0[27:27]);
AND2 I348 (gfint_0[28:28], choice_0, i_0r0[28:28]);
AND2 I349 (gfint_0[29:29], choice_0, i_0r0[29:29]);
AND2 I350 (gfint_0[30:30], choice_0, i_0r0[30:30]);
AND2 I351 (gfint_0[31:31], choice_0, i_0r0[31:31]);
AND2 I352 (gfint_1[0:0], choice_1, i_1r0[0:0]);
AND2 I353 (gfint_1[1:1], choice_1, i_1r0[1:1]);
AND2 I354 (gfint_1[2:2], choice_1, i_1r0[2:2]);
AND2 I355 (gfint_1[3:3], choice_1, i_1r0[3:3]);
AND2 I356 (gfint_1[4:4], choice_1, i_1r0[4:4]);
AND2 I357 (gfint_1[5:5], choice_1, i_1r0[5:5]);
AND2 I358 (gfint_1[6:6], choice_1, i_1r0[6:6]);
AND2 I359 (gfint_1[7:7], choice_1, i_1r0[7:7]);
AND2 I360 (gfint_1[8:8], choice_1, i_1r0[8:8]);
AND2 I361 (gfint_1[9:9], choice_1, i_1r0[9:9]);
AND2 I362 (gfint_1[10:10], choice_1, i_1r0[10:10]);
AND2 I363 (gfint_1[11:11], choice_1, i_1r0[11:11]);
AND2 I364 (gfint_1[12:12], choice_1, i_1r0[12:12]);
AND2 I365 (gfint_1[13:13], choice_1, i_1r0[13:13]);
AND2 I366 (gfint_1[14:14], choice_1, i_1r0[14:14]);
AND2 I367 (gfint_1[15:15], choice_1, i_1r0[15:15]);
AND2 I368 (gfint_1[16:16], choice_1, i_1r0[16:16]);
AND2 I369 (gfint_1[17:17], choice_1, i_1r0[17:17]);
AND2 I370 (gfint_1[18:18], choice_1, i_1r0[18:18]);
AND2 I371 (gfint_1[19:19], choice_1, i_1r0[19:19]);
AND2 I372 (gfint_1[20:20], choice_1, i_1r0[20:20]);
AND2 I373 (gfint_1[21:21], choice_1, i_1r0[21:21]);
AND2 I374 (gfint_1[22:22], choice_1, i_1r0[22:22]);
AND2 I375 (gfint_1[23:23], choice_1, i_1r0[23:23]);
AND2 I376 (gfint_1[24:24], choice_1, i_1r0[24:24]);
AND2 I377 (gfint_1[25:25], choice_1, i_1r0[25:25]);
AND2 I378 (gfint_1[26:26], choice_1, i_1r0[26:26]);
AND2 I379 (gfint_1[27:27], choice_1, i_1r0[27:27]);
AND2 I380 (gfint_1[28:28], choice_1, i_1r0[28:28]);
AND2 I381 (gfint_1[29:29], choice_1, i_1r0[29:29]);
AND2 I382 (gfint_1[30:30], choice_1, i_1r0[30:30]);
AND2 I383 (gfint_1[31:31], choice_1, i_1r0[31:31]);
AND2 I384 (gfint_2[0:0], choice_2, i_2r0[0:0]);
AND2 I385 (gfint_2[1:1], choice_2, i_2r0[1:1]);
AND2 I386 (gfint_2[2:2], choice_2, i_2r0[2:2]);
AND2 I387 (gfint_2[3:3], choice_2, i_2r0[3:3]);
AND2 I388 (gfint_2[4:4], choice_2, i_2r0[4:4]);
AND2 I389 (gfint_2[5:5], choice_2, i_2r0[5:5]);
AND2 I390 (gfint_2[6:6], choice_2, i_2r0[6:6]);
AND2 I391 (gfint_2[7:7], choice_2, i_2r0[7:7]);
AND2 I392 (gfint_2[8:8], choice_2, i_2r0[8:8]);
AND2 I393 (gfint_2[9:9], choice_2, i_2r0[9:9]);
AND2 I394 (gfint_2[10:10], choice_2, i_2r0[10:10]);
AND2 I395 (gfint_2[11:11], choice_2, i_2r0[11:11]);
AND2 I396 (gfint_2[12:12], choice_2, i_2r0[12:12]);
AND2 I397 (gfint_2[13:13], choice_2, i_2r0[13:13]);
AND2 I398 (gfint_2[14:14], choice_2, i_2r0[14:14]);
AND2 I399 (gfint_2[15:15], choice_2, i_2r0[15:15]);
AND2 I400 (gfint_2[16:16], choice_2, i_2r0[16:16]);
AND2 I401 (gfint_2[17:17], choice_2, i_2r0[17:17]);
AND2 I402 (gfint_2[18:18], choice_2, i_2r0[18:18]);
AND2 I403 (gfint_2[19:19], choice_2, i_2r0[19:19]);
AND2 I404 (gfint_2[20:20], choice_2, i_2r0[20:20]);
AND2 I405 (gfint_2[21:21], choice_2, i_2r0[21:21]);
AND2 I406 (gfint_2[22:22], choice_2, i_2r0[22:22]);
AND2 I407 (gfint_2[23:23], choice_2, i_2r0[23:23]);
AND2 I408 (gfint_2[24:24], choice_2, i_2r0[24:24]);
AND2 I409 (gfint_2[25:25], choice_2, i_2r0[25:25]);
AND2 I410 (gfint_2[26:26], choice_2, i_2r0[26:26]);
AND2 I411 (gfint_2[27:27], choice_2, i_2r0[27:27]);
AND2 I412 (gfint_2[28:28], choice_2, i_2r0[28:28]);
AND2 I413 (gfint_2[29:29], choice_2, i_2r0[29:29]);
AND2 I414 (gfint_2[30:30], choice_2, i_2r0[30:30]);
AND2 I415 (gfint_2[31:31], choice_2, i_2r0[31:31]);
AND2 I416 (gfint_3[0:0], choice_3, i_3r0[0:0]);
AND2 I417 (gfint_3[1:1], choice_3, i_3r0[1:1]);
AND2 I418 (gfint_3[2:2], choice_3, i_3r0[2:2]);
AND2 I419 (gfint_3[3:3], choice_3, i_3r0[3:3]);
AND2 I420 (gfint_3[4:4], choice_3, i_3r0[4:4]);
AND2 I421 (gfint_3[5:5], choice_3, i_3r0[5:5]);
AND2 I422 (gfint_3[6:6], choice_3, i_3r0[6:6]);
AND2 I423 (gfint_3[7:7], choice_3, i_3r0[7:7]);
AND2 I424 (gfint_3[8:8], choice_3, i_3r0[8:8]);
AND2 I425 (gfint_3[9:9], choice_3, i_3r0[9:9]);
AND2 I426 (gfint_3[10:10], choice_3, i_3r0[10:10]);
AND2 I427 (gfint_3[11:11], choice_3, i_3r0[11:11]);
AND2 I428 (gfint_3[12:12], choice_3, i_3r0[12:12]);
AND2 I429 (gfint_3[13:13], choice_3, i_3r0[13:13]);
AND2 I430 (gfint_3[14:14], choice_3, i_3r0[14:14]);
AND2 I431 (gfint_3[15:15], choice_3, i_3r0[15:15]);
AND2 I432 (gfint_3[16:16], choice_3, i_3r0[16:16]);
AND2 I433 (gfint_3[17:17], choice_3, i_3r0[17:17]);
AND2 I434 (gfint_3[18:18], choice_3, i_3r0[18:18]);
AND2 I435 (gfint_3[19:19], choice_3, i_3r0[19:19]);
AND2 I436 (gfint_3[20:20], choice_3, i_3r0[20:20]);
AND2 I437 (gfint_3[21:21], choice_3, i_3r0[21:21]);
AND2 I438 (gfint_3[22:22], choice_3, i_3r0[22:22]);
AND2 I439 (gfint_3[23:23], choice_3, i_3r0[23:23]);
AND2 I440 (gfint_3[24:24], choice_3, i_3r0[24:24]);
AND2 I441 (gfint_3[25:25], choice_3, i_3r0[25:25]);
AND2 I442 (gfint_3[26:26], choice_3, i_3r0[26:26]);
AND2 I443 (gfint_3[27:27], choice_3, i_3r0[27:27]);
AND2 I444 (gfint_3[28:28], choice_3, i_3r0[28:28]);
AND2 I445 (gfint_3[29:29], choice_3, i_3r0[29:29]);
AND2 I446 (gfint_3[30:30], choice_3, i_3r0[30:30]);
AND2 I447 (gfint_3[31:31], choice_3, i_3r0[31:31]);
OR2 I448 (comp0_0[0:0], i_0r0[0:0], i_0r1[0:0]);
OR2 I449 (comp0_0[1:1], i_0r0[1:1], i_0r1[1:1]);
OR2 I450 (comp0_0[2:2], i_0r0[2:2], i_0r1[2:2]);
OR2 I451 (comp0_0[3:3], i_0r0[3:3], i_0r1[3:3]);
OR2 I452 (comp0_0[4:4], i_0r0[4:4], i_0r1[4:4]);
OR2 I453 (comp0_0[5:5], i_0r0[5:5], i_0r1[5:5]);
OR2 I454 (comp0_0[6:6], i_0r0[6:6], i_0r1[6:6]);
OR2 I455 (comp0_0[7:7], i_0r0[7:7], i_0r1[7:7]);
OR2 I456 (comp0_0[8:8], i_0r0[8:8], i_0r1[8:8]);
OR2 I457 (comp0_0[9:9], i_0r0[9:9], i_0r1[9:9]);
OR2 I458 (comp0_0[10:10], i_0r0[10:10], i_0r1[10:10]);
OR2 I459 (comp0_0[11:11], i_0r0[11:11], i_0r1[11:11]);
OR2 I460 (comp0_0[12:12], i_0r0[12:12], i_0r1[12:12]);
OR2 I461 (comp0_0[13:13], i_0r0[13:13], i_0r1[13:13]);
OR2 I462 (comp0_0[14:14], i_0r0[14:14], i_0r1[14:14]);
OR2 I463 (comp0_0[15:15], i_0r0[15:15], i_0r1[15:15]);
OR2 I464 (comp0_0[16:16], i_0r0[16:16], i_0r1[16:16]);
OR2 I465 (comp0_0[17:17], i_0r0[17:17], i_0r1[17:17]);
OR2 I466 (comp0_0[18:18], i_0r0[18:18], i_0r1[18:18]);
OR2 I467 (comp0_0[19:19], i_0r0[19:19], i_0r1[19:19]);
OR2 I468 (comp0_0[20:20], i_0r0[20:20], i_0r1[20:20]);
OR2 I469 (comp0_0[21:21], i_0r0[21:21], i_0r1[21:21]);
OR2 I470 (comp0_0[22:22], i_0r0[22:22], i_0r1[22:22]);
OR2 I471 (comp0_0[23:23], i_0r0[23:23], i_0r1[23:23]);
OR2 I472 (comp0_0[24:24], i_0r0[24:24], i_0r1[24:24]);
OR2 I473 (comp0_0[25:25], i_0r0[25:25], i_0r1[25:25]);
OR2 I474 (comp0_0[26:26], i_0r0[26:26], i_0r1[26:26]);
OR2 I475 (comp0_0[27:27], i_0r0[27:27], i_0r1[27:27]);
OR2 I476 (comp0_0[28:28], i_0r0[28:28], i_0r1[28:28]);
OR2 I477 (comp0_0[29:29], i_0r0[29:29], i_0r1[29:29]);
OR2 I478 (comp0_0[30:30], i_0r0[30:30], i_0r1[30:30]);
OR2 I479 (comp0_0[31:31], i_0r0[31:31], i_0r1[31:31]);
C3 I480 (simp3711_0[0:0], comp0_0[0:0], comp0_0[1:1], comp0_0[2:2]);
C3 I481 (simp3711_0[1:1], comp0_0[3:3], comp0_0[4:4], comp0_0[5:5]);
C3 I482 (simp3711_0[2:2], comp0_0[6:6], comp0_0[7:7], comp0_0[8:8]);
C3 I483 (simp3711_0[3:3], comp0_0[9:9], comp0_0[10:10], comp0_0[11:11]);
C3 I484 (simp3711_0[4:4], comp0_0[12:12], comp0_0[13:13], comp0_0[14:14]);
C3 I485 (simp3711_0[5:5], comp0_0[15:15], comp0_0[16:16], comp0_0[17:17]);
C3 I486 (simp3711_0[6:6], comp0_0[18:18], comp0_0[19:19], comp0_0[20:20]);
C3 I487 (simp3711_0[7:7], comp0_0[21:21], comp0_0[22:22], comp0_0[23:23]);
C3 I488 (simp3711_0[8:8], comp0_0[24:24], comp0_0[25:25], comp0_0[26:26]);
C3 I489 (simp3711_0[9:9], comp0_0[27:27], comp0_0[28:28], comp0_0[29:29]);
C2 I490 (simp3711_0[10:10], comp0_0[30:30], comp0_0[31:31]);
C3 I491 (simp3712_0[0:0], simp3711_0[0:0], simp3711_0[1:1], simp3711_0[2:2]);
C3 I492 (simp3712_0[1:1], simp3711_0[3:3], simp3711_0[4:4], simp3711_0[5:5]);
C3 I493 (simp3712_0[2:2], simp3711_0[6:6], simp3711_0[7:7], simp3711_0[8:8]);
C2 I494 (simp3712_0[3:3], simp3711_0[9:9], simp3711_0[10:10]);
C3 I495 (simp3713_0[0:0], simp3712_0[0:0], simp3712_0[1:1], simp3712_0[2:2]);
BUFF I496 (simp3713_0[1:1], simp3712_0[3:3]);
C2 I497 (icomp_0, simp3713_0[0:0], simp3713_0[1:1]);
OR2 I498 (comp1_0[0:0], i_1r0[0:0], i_1r1[0:0]);
OR2 I499 (comp1_0[1:1], i_1r0[1:1], i_1r1[1:1]);
OR2 I500 (comp1_0[2:2], i_1r0[2:2], i_1r1[2:2]);
OR2 I501 (comp1_0[3:3], i_1r0[3:3], i_1r1[3:3]);
OR2 I502 (comp1_0[4:4], i_1r0[4:4], i_1r1[4:4]);
OR2 I503 (comp1_0[5:5], i_1r0[5:5], i_1r1[5:5]);
OR2 I504 (comp1_0[6:6], i_1r0[6:6], i_1r1[6:6]);
OR2 I505 (comp1_0[7:7], i_1r0[7:7], i_1r1[7:7]);
OR2 I506 (comp1_0[8:8], i_1r0[8:8], i_1r1[8:8]);
OR2 I507 (comp1_0[9:9], i_1r0[9:9], i_1r1[9:9]);
OR2 I508 (comp1_0[10:10], i_1r0[10:10], i_1r1[10:10]);
OR2 I509 (comp1_0[11:11], i_1r0[11:11], i_1r1[11:11]);
OR2 I510 (comp1_0[12:12], i_1r0[12:12], i_1r1[12:12]);
OR2 I511 (comp1_0[13:13], i_1r0[13:13], i_1r1[13:13]);
OR2 I512 (comp1_0[14:14], i_1r0[14:14], i_1r1[14:14]);
OR2 I513 (comp1_0[15:15], i_1r0[15:15], i_1r1[15:15]);
OR2 I514 (comp1_0[16:16], i_1r0[16:16], i_1r1[16:16]);
OR2 I515 (comp1_0[17:17], i_1r0[17:17], i_1r1[17:17]);
OR2 I516 (comp1_0[18:18], i_1r0[18:18], i_1r1[18:18]);
OR2 I517 (comp1_0[19:19], i_1r0[19:19], i_1r1[19:19]);
OR2 I518 (comp1_0[20:20], i_1r0[20:20], i_1r1[20:20]);
OR2 I519 (comp1_0[21:21], i_1r0[21:21], i_1r1[21:21]);
OR2 I520 (comp1_0[22:22], i_1r0[22:22], i_1r1[22:22]);
OR2 I521 (comp1_0[23:23], i_1r0[23:23], i_1r1[23:23]);
OR2 I522 (comp1_0[24:24], i_1r0[24:24], i_1r1[24:24]);
OR2 I523 (comp1_0[25:25], i_1r0[25:25], i_1r1[25:25]);
OR2 I524 (comp1_0[26:26], i_1r0[26:26], i_1r1[26:26]);
OR2 I525 (comp1_0[27:27], i_1r0[27:27], i_1r1[27:27]);
OR2 I526 (comp1_0[28:28], i_1r0[28:28], i_1r1[28:28]);
OR2 I527 (comp1_0[29:29], i_1r0[29:29], i_1r1[29:29]);
OR2 I528 (comp1_0[30:30], i_1r0[30:30], i_1r1[30:30]);
OR2 I529 (comp1_0[31:31], i_1r0[31:31], i_1r1[31:31]);
C3 I530 (simp4051_0[0:0], comp1_0[0:0], comp1_0[1:1], comp1_0[2:2]);
C3 I531 (simp4051_0[1:1], comp1_0[3:3], comp1_0[4:4], comp1_0[5:5]);
C3 I532 (simp4051_0[2:2], comp1_0[6:6], comp1_0[7:7], comp1_0[8:8]);
C3 I533 (simp4051_0[3:3], comp1_0[9:9], comp1_0[10:10], comp1_0[11:11]);
C3 I534 (simp4051_0[4:4], comp1_0[12:12], comp1_0[13:13], comp1_0[14:14]);
C3 I535 (simp4051_0[5:5], comp1_0[15:15], comp1_0[16:16], comp1_0[17:17]);
C3 I536 (simp4051_0[6:6], comp1_0[18:18], comp1_0[19:19], comp1_0[20:20]);
C3 I537 (simp4051_0[7:7], comp1_0[21:21], comp1_0[22:22], comp1_0[23:23]);
C3 I538 (simp4051_0[8:8], comp1_0[24:24], comp1_0[25:25], comp1_0[26:26]);
C3 I539 (simp4051_0[9:9], comp1_0[27:27], comp1_0[28:28], comp1_0[29:29]);
C2 I540 (simp4051_0[10:10], comp1_0[30:30], comp1_0[31:31]);
C3 I541 (simp4052_0[0:0], simp4051_0[0:0], simp4051_0[1:1], simp4051_0[2:2]);
C3 I542 (simp4052_0[1:1], simp4051_0[3:3], simp4051_0[4:4], simp4051_0[5:5]);
C3 I543 (simp4052_0[2:2], simp4051_0[6:6], simp4051_0[7:7], simp4051_0[8:8]);
C2 I544 (simp4052_0[3:3], simp4051_0[9:9], simp4051_0[10:10]);
C3 I545 (simp4053_0[0:0], simp4052_0[0:0], simp4052_0[1:1], simp4052_0[2:2]);
BUFF I546 (simp4053_0[1:1], simp4052_0[3:3]);
C2 I547 (icomp_1, simp4053_0[0:0], simp4053_0[1:1]);
OR2 I548 (comp2_0[0:0], i_2r0[0:0], i_2r1[0:0]);
OR2 I549 (comp2_0[1:1], i_2r0[1:1], i_2r1[1:1]);
OR2 I550 (comp2_0[2:2], i_2r0[2:2], i_2r1[2:2]);
OR2 I551 (comp2_0[3:3], i_2r0[3:3], i_2r1[3:3]);
OR2 I552 (comp2_0[4:4], i_2r0[4:4], i_2r1[4:4]);
OR2 I553 (comp2_0[5:5], i_2r0[5:5], i_2r1[5:5]);
OR2 I554 (comp2_0[6:6], i_2r0[6:6], i_2r1[6:6]);
OR2 I555 (comp2_0[7:7], i_2r0[7:7], i_2r1[7:7]);
OR2 I556 (comp2_0[8:8], i_2r0[8:8], i_2r1[8:8]);
OR2 I557 (comp2_0[9:9], i_2r0[9:9], i_2r1[9:9]);
OR2 I558 (comp2_0[10:10], i_2r0[10:10], i_2r1[10:10]);
OR2 I559 (comp2_0[11:11], i_2r0[11:11], i_2r1[11:11]);
OR2 I560 (comp2_0[12:12], i_2r0[12:12], i_2r1[12:12]);
OR2 I561 (comp2_0[13:13], i_2r0[13:13], i_2r1[13:13]);
OR2 I562 (comp2_0[14:14], i_2r0[14:14], i_2r1[14:14]);
OR2 I563 (comp2_0[15:15], i_2r0[15:15], i_2r1[15:15]);
OR2 I564 (comp2_0[16:16], i_2r0[16:16], i_2r1[16:16]);
OR2 I565 (comp2_0[17:17], i_2r0[17:17], i_2r1[17:17]);
OR2 I566 (comp2_0[18:18], i_2r0[18:18], i_2r1[18:18]);
OR2 I567 (comp2_0[19:19], i_2r0[19:19], i_2r1[19:19]);
OR2 I568 (comp2_0[20:20], i_2r0[20:20], i_2r1[20:20]);
OR2 I569 (comp2_0[21:21], i_2r0[21:21], i_2r1[21:21]);
OR2 I570 (comp2_0[22:22], i_2r0[22:22], i_2r1[22:22]);
OR2 I571 (comp2_0[23:23], i_2r0[23:23], i_2r1[23:23]);
OR2 I572 (comp2_0[24:24], i_2r0[24:24], i_2r1[24:24]);
OR2 I573 (comp2_0[25:25], i_2r0[25:25], i_2r1[25:25]);
OR2 I574 (comp2_0[26:26], i_2r0[26:26], i_2r1[26:26]);
OR2 I575 (comp2_0[27:27], i_2r0[27:27], i_2r1[27:27]);
OR2 I576 (comp2_0[28:28], i_2r0[28:28], i_2r1[28:28]);
OR2 I577 (comp2_0[29:29], i_2r0[29:29], i_2r1[29:29]);
OR2 I578 (comp2_0[30:30], i_2r0[30:30], i_2r1[30:30]);
OR2 I579 (comp2_0[31:31], i_2r0[31:31], i_2r1[31:31]);
C3 I580 (simp4391_0[0:0], comp2_0[0:0], comp2_0[1:1], comp2_0[2:2]);
C3 I581 (simp4391_0[1:1], comp2_0[3:3], comp2_0[4:4], comp2_0[5:5]);
C3 I582 (simp4391_0[2:2], comp2_0[6:6], comp2_0[7:7], comp2_0[8:8]);
C3 I583 (simp4391_0[3:3], comp2_0[9:9], comp2_0[10:10], comp2_0[11:11]);
C3 I584 (simp4391_0[4:4], comp2_0[12:12], comp2_0[13:13], comp2_0[14:14]);
C3 I585 (simp4391_0[5:5], comp2_0[15:15], comp2_0[16:16], comp2_0[17:17]);
C3 I586 (simp4391_0[6:6], comp2_0[18:18], comp2_0[19:19], comp2_0[20:20]);
C3 I587 (simp4391_0[7:7], comp2_0[21:21], comp2_0[22:22], comp2_0[23:23]);
C3 I588 (simp4391_0[8:8], comp2_0[24:24], comp2_0[25:25], comp2_0[26:26]);
C3 I589 (simp4391_0[9:9], comp2_0[27:27], comp2_0[28:28], comp2_0[29:29]);
C2 I590 (simp4391_0[10:10], comp2_0[30:30], comp2_0[31:31]);
C3 I591 (simp4392_0[0:0], simp4391_0[0:0], simp4391_0[1:1], simp4391_0[2:2]);
C3 I592 (simp4392_0[1:1], simp4391_0[3:3], simp4391_0[4:4], simp4391_0[5:5]);
C3 I593 (simp4392_0[2:2], simp4391_0[6:6], simp4391_0[7:7], simp4391_0[8:8]);
C2 I594 (simp4392_0[3:3], simp4391_0[9:9], simp4391_0[10:10]);
C3 I595 (simp4393_0[0:0], simp4392_0[0:0], simp4392_0[1:1], simp4392_0[2:2]);
BUFF I596 (simp4393_0[1:1], simp4392_0[3:3]);
C2 I597 (icomp_2, simp4393_0[0:0], simp4393_0[1:1]);
OR2 I598 (comp3_0[0:0], i_3r0[0:0], i_3r1[0:0]);
OR2 I599 (comp3_0[1:1], i_3r0[1:1], i_3r1[1:1]);
OR2 I600 (comp3_0[2:2], i_3r0[2:2], i_3r1[2:2]);
OR2 I601 (comp3_0[3:3], i_3r0[3:3], i_3r1[3:3]);
OR2 I602 (comp3_0[4:4], i_3r0[4:4], i_3r1[4:4]);
OR2 I603 (comp3_0[5:5], i_3r0[5:5], i_3r1[5:5]);
OR2 I604 (comp3_0[6:6], i_3r0[6:6], i_3r1[6:6]);
OR2 I605 (comp3_0[7:7], i_3r0[7:7], i_3r1[7:7]);
OR2 I606 (comp3_0[8:8], i_3r0[8:8], i_3r1[8:8]);
OR2 I607 (comp3_0[9:9], i_3r0[9:9], i_3r1[9:9]);
OR2 I608 (comp3_0[10:10], i_3r0[10:10], i_3r1[10:10]);
OR2 I609 (comp3_0[11:11], i_3r0[11:11], i_3r1[11:11]);
OR2 I610 (comp3_0[12:12], i_3r0[12:12], i_3r1[12:12]);
OR2 I611 (comp3_0[13:13], i_3r0[13:13], i_3r1[13:13]);
OR2 I612 (comp3_0[14:14], i_3r0[14:14], i_3r1[14:14]);
OR2 I613 (comp3_0[15:15], i_3r0[15:15], i_3r1[15:15]);
OR2 I614 (comp3_0[16:16], i_3r0[16:16], i_3r1[16:16]);
OR2 I615 (comp3_0[17:17], i_3r0[17:17], i_3r1[17:17]);
OR2 I616 (comp3_0[18:18], i_3r0[18:18], i_3r1[18:18]);
OR2 I617 (comp3_0[19:19], i_3r0[19:19], i_3r1[19:19]);
OR2 I618 (comp3_0[20:20], i_3r0[20:20], i_3r1[20:20]);
OR2 I619 (comp3_0[21:21], i_3r0[21:21], i_3r1[21:21]);
OR2 I620 (comp3_0[22:22], i_3r0[22:22], i_3r1[22:22]);
OR2 I621 (comp3_0[23:23], i_3r0[23:23], i_3r1[23:23]);
OR2 I622 (comp3_0[24:24], i_3r0[24:24], i_3r1[24:24]);
OR2 I623 (comp3_0[25:25], i_3r0[25:25], i_3r1[25:25]);
OR2 I624 (comp3_0[26:26], i_3r0[26:26], i_3r1[26:26]);
OR2 I625 (comp3_0[27:27], i_3r0[27:27], i_3r1[27:27]);
OR2 I626 (comp3_0[28:28], i_3r0[28:28], i_3r1[28:28]);
OR2 I627 (comp3_0[29:29], i_3r0[29:29], i_3r1[29:29]);
OR2 I628 (comp3_0[30:30], i_3r0[30:30], i_3r1[30:30]);
OR2 I629 (comp3_0[31:31], i_3r0[31:31], i_3r1[31:31]);
C3 I630 (simp4731_0[0:0], comp3_0[0:0], comp3_0[1:1], comp3_0[2:2]);
C3 I631 (simp4731_0[1:1], comp3_0[3:3], comp3_0[4:4], comp3_0[5:5]);
C3 I632 (simp4731_0[2:2], comp3_0[6:6], comp3_0[7:7], comp3_0[8:8]);
C3 I633 (simp4731_0[3:3], comp3_0[9:9], comp3_0[10:10], comp3_0[11:11]);
C3 I634 (simp4731_0[4:4], comp3_0[12:12], comp3_0[13:13], comp3_0[14:14]);
C3 I635 (simp4731_0[5:5], comp3_0[15:15], comp3_0[16:16], comp3_0[17:17]);
C3 I636 (simp4731_0[6:6], comp3_0[18:18], comp3_0[19:19], comp3_0[20:20]);
C3 I637 (simp4731_0[7:7], comp3_0[21:21], comp3_0[22:22], comp3_0[23:23]);
C3 I638 (simp4731_0[8:8], comp3_0[24:24], comp3_0[25:25], comp3_0[26:26]);
C3 I639 (simp4731_0[9:9], comp3_0[27:27], comp3_0[28:28], comp3_0[29:29]);
C2 I640 (simp4731_0[10:10], comp3_0[30:30], comp3_0[31:31]);
C3 I641 (simp4732_0[0:0], simp4731_0[0:0], simp4731_0[1:1], simp4731_0[2:2]);
C3 I642 (simp4732_0[1:1], simp4731_0[3:3], simp4731_0[4:4], simp4731_0[5:5]);
C3 I643 (simp4732_0[2:2], simp4731_0[6:6], simp4731_0[7:7], simp4731_0[8:8]);
C2 I644 (simp4732_0[3:3], simp4731_0[9:9], simp4731_0[10:10]);
C3 I645 (simp4733_0[0:0], simp4732_0[0:0], simp4732_0[1:1], simp4732_0[2:2]);
BUFF I646 (simp4733_0[1:1], simp4732_0[3:3]);
C2 I647 (icomp_3, simp4733_0[0:0], simp4733_0[1:1]);
C2R I648 (choice_0, icomp_0, nchosen_0, reset);
C2R I649 (choice_1, icomp_1, nchosen_0, reset);
C2R I650 (choice_2, icomp_2, nchosen_0, reset);
C2R I651 (choice_3, icomp_3, nchosen_0, reset);
NOR3 I652 (simp4781_0[0:0], choice_0, choice_1, choice_2);
INV I653 (simp4781_0[1:1], choice_3);
NAND2 I654 (anychoice_0, simp4781_0[0:0], simp4781_0[1:1]);
NOR2 I655 (nchosen_0, anychoice_0, o_0a);
C2R I656 (i_0a, choice_0, o_0a, reset);
C2R I657 (i_1a, choice_1, o_0a, reset);
C2R I658 (i_2a, choice_2, o_0a, reset);
C2R I659 (i_3a, choice_3, o_0a, reset);
endmodule
// tkj32m32_0 TeakJ [Many [32,0],One 32]
module tkj32m32_0 (i_0r0, i_0r1, i_0a, i_1r, i_1a, o_0r0, o_0r1, o_0a, reset);
input [31:0] i_0r0;
input [31:0] i_0r1;
output i_0a;
input i_1r;
output i_1a;
output [31:0] o_0r0;
output [31:0] o_0r1;
input o_0a;
input reset;
wire icomplete_0;
wire [31:0] joinf_0;
wire [31:0] joint_0;
BUFF I0 (joinf_0[0:0], i_0r0[0:0]);
BUFF I1 (joinf_0[1:1], i_0r0[1:1]);
BUFF I2 (joinf_0[2:2], i_0r0[2:2]);
BUFF I3 (joinf_0[3:3], i_0r0[3:3]);
BUFF I4 (joinf_0[4:4], i_0r0[4:4]);
BUFF I5 (joinf_0[5:5], i_0r0[5:5]);
BUFF I6 (joinf_0[6:6], i_0r0[6:6]);
BUFF I7 (joinf_0[7:7], i_0r0[7:7]);
BUFF I8 (joinf_0[8:8], i_0r0[8:8]);
BUFF I9 (joinf_0[9:9], i_0r0[9:9]);
BUFF I10 (joinf_0[10:10], i_0r0[10:10]);
BUFF I11 (joinf_0[11:11], i_0r0[11:11]);
BUFF I12 (joinf_0[12:12], i_0r0[12:12]);
BUFF I13 (joinf_0[13:13], i_0r0[13:13]);
BUFF I14 (joinf_0[14:14], i_0r0[14:14]);
BUFF I15 (joinf_0[15:15], i_0r0[15:15]);
BUFF I16 (joinf_0[16:16], i_0r0[16:16]);
BUFF I17 (joinf_0[17:17], i_0r0[17:17]);
BUFF I18 (joinf_0[18:18], i_0r0[18:18]);
BUFF I19 (joinf_0[19:19], i_0r0[19:19]);
BUFF I20 (joinf_0[20:20], i_0r0[20:20]);
BUFF I21 (joinf_0[21:21], i_0r0[21:21]);
BUFF I22 (joinf_0[22:22], i_0r0[22:22]);
BUFF I23 (joinf_0[23:23], i_0r0[23:23]);
BUFF I24 (joinf_0[24:24], i_0r0[24:24]);
BUFF I25 (joinf_0[25:25], i_0r0[25:25]);
BUFF I26 (joinf_0[26:26], i_0r0[26:26]);
BUFF I27 (joinf_0[27:27], i_0r0[27:27]);
BUFF I28 (joinf_0[28:28], i_0r0[28:28]);
BUFF I29 (joinf_0[29:29], i_0r0[29:29]);
BUFF I30 (joinf_0[30:30], i_0r0[30:30]);
BUFF I31 (joinf_0[31:31], i_0r0[31:31]);
BUFF I32 (joint_0[0:0], i_0r1[0:0]);
BUFF I33 (joint_0[1:1], i_0r1[1:1]);
BUFF I34 (joint_0[2:2], i_0r1[2:2]);
BUFF I35 (joint_0[3:3], i_0r1[3:3]);
BUFF I36 (joint_0[4:4], i_0r1[4:4]);
BUFF I37 (joint_0[5:5], i_0r1[5:5]);
BUFF I38 (joint_0[6:6], i_0r1[6:6]);
BUFF I39 (joint_0[7:7], i_0r1[7:7]);
BUFF I40 (joint_0[8:8], i_0r1[8:8]);
BUFF I41 (joint_0[9:9], i_0r1[9:9]);
BUFF I42 (joint_0[10:10], i_0r1[10:10]);
BUFF I43 (joint_0[11:11], i_0r1[11:11]);
BUFF I44 (joint_0[12:12], i_0r1[12:12]);
BUFF I45 (joint_0[13:13], i_0r1[13:13]);
BUFF I46 (joint_0[14:14], i_0r1[14:14]);
BUFF I47 (joint_0[15:15], i_0r1[15:15]);
BUFF I48 (joint_0[16:16], i_0r1[16:16]);
BUFF I49 (joint_0[17:17], i_0r1[17:17]);
BUFF I50 (joint_0[18:18], i_0r1[18:18]);
BUFF I51 (joint_0[19:19], i_0r1[19:19]);
BUFF I52 (joint_0[20:20], i_0r1[20:20]);
BUFF I53 (joint_0[21:21], i_0r1[21:21]);
BUFF I54 (joint_0[22:22], i_0r1[22:22]);
BUFF I55 (joint_0[23:23], i_0r1[23:23]);
BUFF I56 (joint_0[24:24], i_0r1[24:24]);
BUFF I57 (joint_0[25:25], i_0r1[25:25]);
BUFF I58 (joint_0[26:26], i_0r1[26:26]);
BUFF I59 (joint_0[27:27], i_0r1[27:27]);
BUFF I60 (joint_0[28:28], i_0r1[28:28]);
BUFF I61 (joint_0[29:29], i_0r1[29:29]);
BUFF I62 (joint_0[30:30], i_0r1[30:30]);
BUFF I63 (joint_0[31:31], i_0r1[31:31]);
BUFF I64 (icomplete_0, i_1r);
C2 I65 (o_0r0[0:0], joinf_0[0:0], icomplete_0);
C2 I66 (o_0r1[0:0], joint_0[0:0], icomplete_0);
BUFF I67 (o_0r0[1:1], joinf_0[1:1]);
BUFF I68 (o_0r0[2:2], joinf_0[2:2]);
BUFF I69 (o_0r0[3:3], joinf_0[3:3]);
BUFF I70 (o_0r0[4:4], joinf_0[4:4]);
BUFF I71 (o_0r0[5:5], joinf_0[5:5]);
BUFF I72 (o_0r0[6:6], joinf_0[6:6]);
BUFF I73 (o_0r0[7:7], joinf_0[7:7]);
BUFF I74 (o_0r0[8:8], joinf_0[8:8]);
BUFF I75 (o_0r0[9:9], joinf_0[9:9]);
BUFF I76 (o_0r0[10:10], joinf_0[10:10]);
BUFF I77 (o_0r0[11:11], joinf_0[11:11]);
BUFF I78 (o_0r0[12:12], joinf_0[12:12]);
BUFF I79 (o_0r0[13:13], joinf_0[13:13]);
BUFF I80 (o_0r0[14:14], joinf_0[14:14]);
BUFF I81 (o_0r0[15:15], joinf_0[15:15]);
BUFF I82 (o_0r0[16:16], joinf_0[16:16]);
BUFF I83 (o_0r0[17:17], joinf_0[17:17]);
BUFF I84 (o_0r0[18:18], joinf_0[18:18]);
BUFF I85 (o_0r0[19:19], joinf_0[19:19]);
BUFF I86 (o_0r0[20:20], joinf_0[20:20]);
BUFF I87 (o_0r0[21:21], joinf_0[21:21]);
BUFF I88 (o_0r0[22:22], joinf_0[22:22]);
BUFF I89 (o_0r0[23:23], joinf_0[23:23]);
BUFF I90 (o_0r0[24:24], joinf_0[24:24]);
BUFF I91 (o_0r0[25:25], joinf_0[25:25]);
BUFF I92 (o_0r0[26:26], joinf_0[26:26]);
BUFF I93 (o_0r0[27:27], joinf_0[27:27]);
BUFF I94 (o_0r0[28:28], joinf_0[28:28]);
BUFF I95 (o_0r0[29:29], joinf_0[29:29]);
BUFF I96 (o_0r0[30:30], joinf_0[30:30]);
BUFF I97 (o_0r0[31:31], joinf_0[31:31]);
BUFF I98 (o_0r1[1:1], joint_0[1:1]);
BUFF I99 (o_0r1[2:2], joint_0[2:2]);
BUFF I100 (o_0r1[3:3], joint_0[3:3]);
BUFF I101 (o_0r1[4:4], joint_0[4:4]);
BUFF I102 (o_0r1[5:5], joint_0[5:5]);
BUFF I103 (o_0r1[6:6], joint_0[6:6]);
BUFF I104 (o_0r1[7:7], joint_0[7:7]);
BUFF I105 (o_0r1[8:8], joint_0[8:8]);
BUFF I106 (o_0r1[9:9], joint_0[9:9]);
BUFF I107 (o_0r1[10:10], joint_0[10:10]);
BUFF I108 (o_0r1[11:11], joint_0[11:11]);
BUFF I109 (o_0r1[12:12], joint_0[12:12]);
BUFF I110 (o_0r1[13:13], joint_0[13:13]);
BUFF I111 (o_0r1[14:14], joint_0[14:14]);
BUFF I112 (o_0r1[15:15], joint_0[15:15]);
BUFF I113 (o_0r1[16:16], joint_0[16:16]);
BUFF I114 (o_0r1[17:17], joint_0[17:17]);
BUFF I115 (o_0r1[18:18], joint_0[18:18]);
BUFF I116 (o_0r1[19:19], joint_0[19:19]);
BUFF I117 (o_0r1[20:20], joint_0[20:20]);
BUFF I118 (o_0r1[21:21], joint_0[21:21]);
BUFF I119 (o_0r1[22:22], joint_0[22:22]);
BUFF I120 (o_0r1[23:23], joint_0[23:23]);
BUFF I121 (o_0r1[24:24], joint_0[24:24]);
BUFF I122 (o_0r1[25:25], joint_0[25:25]);
BUFF I123 (o_0r1[26:26], joint_0[26:26]);
BUFF I124 (o_0r1[27:27], joint_0[27:27]);
BUFF I125 (o_0r1[28:28], joint_0[28:28]);
BUFF I126 (o_0r1[29:29], joint_0[29:29]);
BUFF I127 (o_0r1[30:30], joint_0[30:30]);
BUFF I128 (o_0r1[31:31], joint_0[31:31]);
BUFF I129 (i_0a, o_0a);
BUFF I130 (i_1a, o_0a);
endmodule
// tko28m32_1nm4b0_2apt1o0w4bi0w28b TeakO [
// (1,TeakOConstant 4 0),
// (2,TeakOAppend 1 [(1,0+:4),(0,0+:28)])] [One 28,One 32]
module tko28m32_1nm4b0_2apt1o0w4bi0w28b (i_0r0, i_0r1, i_0a, o_0r0, o_0r1, o_0a, reset);
input [27:0] i_0r0;
input [27:0] i_0r1;
output i_0a;
output [31:0] o_0r0;
output [31:0] o_0r1;
input o_0a;
input reset;
wire go_0;
wire [27:0] gocomp_0;
wire [9:0] simp301_0;
wire [3:0] simp302_0;
wire [1:0] simp303_0;
wire [3:0] termf_1;
wire [3:0] termt_1;
OR2 I0 (gocomp_0[0:0], i_0r0[0:0], i_0r1[0:0]);
OR2 I1 (gocomp_0[1:1], i_0r0[1:1], i_0r1[1:1]);
OR2 I2 (gocomp_0[2:2], i_0r0[2:2], i_0r1[2:2]);
OR2 I3 (gocomp_0[3:3], i_0r0[3:3], i_0r1[3:3]);
OR2 I4 (gocomp_0[4:4], i_0r0[4:4], i_0r1[4:4]);
OR2 I5 (gocomp_0[5:5], i_0r0[5:5], i_0r1[5:5]);
OR2 I6 (gocomp_0[6:6], i_0r0[6:6], i_0r1[6:6]);
OR2 I7 (gocomp_0[7:7], i_0r0[7:7], i_0r1[7:7]);
OR2 I8 (gocomp_0[8:8], i_0r0[8:8], i_0r1[8:8]);
OR2 I9 (gocomp_0[9:9], i_0r0[9:9], i_0r1[9:9]);
OR2 I10 (gocomp_0[10:10], i_0r0[10:10], i_0r1[10:10]);
OR2 I11 (gocomp_0[11:11], i_0r0[11:11], i_0r1[11:11]);
OR2 I12 (gocomp_0[12:12], i_0r0[12:12], i_0r1[12:12]);
OR2 I13 (gocomp_0[13:13], i_0r0[13:13], i_0r1[13:13]);
OR2 I14 (gocomp_0[14:14], i_0r0[14:14], i_0r1[14:14]);
OR2 I15 (gocomp_0[15:15], i_0r0[15:15], i_0r1[15:15]);
OR2 I16 (gocomp_0[16:16], i_0r0[16:16], i_0r1[16:16]);
OR2 I17 (gocomp_0[17:17], i_0r0[17:17], i_0r1[17:17]);
OR2 I18 (gocomp_0[18:18], i_0r0[18:18], i_0r1[18:18]);
OR2 I19 (gocomp_0[19:19], i_0r0[19:19], i_0r1[19:19]);
OR2 I20 (gocomp_0[20:20], i_0r0[20:20], i_0r1[20:20]);
OR2 I21 (gocomp_0[21:21], i_0r0[21:21], i_0r1[21:21]);
OR2 I22 (gocomp_0[22:22], i_0r0[22:22], i_0r1[22:22]);
OR2 I23 (gocomp_0[23:23], i_0r0[23:23], i_0r1[23:23]);
OR2 I24 (gocomp_0[24:24], i_0r0[24:24], i_0r1[24:24]);
OR2 I25 (gocomp_0[25:25], i_0r0[25:25], i_0r1[25:25]);
OR2 I26 (gocomp_0[26:26], i_0r0[26:26], i_0r1[26:26]);
OR2 I27 (gocomp_0[27:27], i_0r0[27:27], i_0r1[27:27]);
C3 I28 (simp301_0[0:0], gocomp_0[0:0], gocomp_0[1:1], gocomp_0[2:2]);
C3 I29 (simp301_0[1:1], gocomp_0[3:3], gocomp_0[4:4], gocomp_0[5:5]);
C3 I30 (simp301_0[2:2], gocomp_0[6:6], gocomp_0[7:7], gocomp_0[8:8]);
C3 I31 (simp301_0[3:3], gocomp_0[9:9], gocomp_0[10:10], gocomp_0[11:11]);
C3 I32 (simp301_0[4:4], gocomp_0[12:12], gocomp_0[13:13], gocomp_0[14:14]);
C3 I33 (simp301_0[5:5], gocomp_0[15:15], gocomp_0[16:16], gocomp_0[17:17]);
C3 I34 (simp301_0[6:6], gocomp_0[18:18], gocomp_0[19:19], gocomp_0[20:20]);
C3 I35 (simp301_0[7:7], gocomp_0[21:21], gocomp_0[22:22], gocomp_0[23:23]);
C3 I36 (simp301_0[8:8], gocomp_0[24:24], gocomp_0[25:25], gocomp_0[26:26]);
BUFF I37 (simp301_0[9:9], gocomp_0[27:27]);
C3 I38 (simp302_0[0:0], simp301_0[0:0], simp301_0[1:1], simp301_0[2:2]);
C3 I39 (simp302_0[1:1], simp301_0[3:3], simp301_0[4:4], simp301_0[5:5]);
C3 I40 (simp302_0[2:2], simp301_0[6:6], simp301_0[7:7], simp301_0[8:8]);
BUFF I41 (simp302_0[3:3], simp301_0[9:9]);
C3 I42 (simp303_0[0:0], simp302_0[0:0], simp302_0[1:1], simp302_0[2:2]);
BUFF I43 (simp303_0[1:1], simp302_0[3:3]);
C2 I44 (go_0, simp303_0[0:0], simp303_0[1:1]);
BUFF I45 (termf_1[0:0], go_0);
BUFF I46 (termf_1[1:1], go_0);
BUFF I47 (termf_1[2:2], go_0);
BUFF I48 (termf_1[3:3], go_0);
GND I49 (termt_1[0:0]);
GND I50 (termt_1[1:1]);
GND I51 (termt_1[2:2]);
GND I52 (termt_1[3:3]);
BUFF I53 (o_0r0[0:0], termf_1[0:0]);
BUFF I54 (o_0r0[1:1], termf_1[1:1]);
BUFF I55 (o_0r0[2:2], termf_1[2:2]);
BUFF I56 (o_0r0[3:3], termf_1[3:3]);
BUFF I57 (o_0r0[4:4], i_0r0[0:0]);
BUFF I58 (o_0r0[5:5], i_0r0[1:1]);
BUFF I59 (o_0r0[6:6], i_0r0[2:2]);
BUFF I60 (o_0r0[7:7], i_0r0[3:3]);
BUFF I61 (o_0r0[8:8], i_0r0[4:4]);
BUFF I62 (o_0r0[9:9], i_0r0[5:5]);
BUFF I63 (o_0r0[10:10], i_0r0[6:6]);
BUFF I64 (o_0r0[11:11], i_0r0[7:7]);
BUFF I65 (o_0r0[12:12], i_0r0[8:8]);
BUFF I66 (o_0r0[13:13], i_0r0[9:9]);
BUFF I67 (o_0r0[14:14], i_0r0[10:10]);
BUFF I68 (o_0r0[15:15], i_0r0[11:11]);
BUFF I69 (o_0r0[16:16], i_0r0[12:12]);
BUFF I70 (o_0r0[17:17], i_0r0[13:13]);
BUFF I71 (o_0r0[18:18], i_0r0[14:14]);
BUFF I72 (o_0r0[19:19], i_0r0[15:15]);
BUFF I73 (o_0r0[20:20], i_0r0[16:16]);
BUFF I74 (o_0r0[21:21], i_0r0[17:17]);
BUFF I75 (o_0r0[22:22], i_0r0[18:18]);
BUFF I76 (o_0r0[23:23], i_0r0[19:19]);
BUFF I77 (o_0r0[24:24], i_0r0[20:20]);
BUFF I78 (o_0r0[25:25], i_0r0[21:21]);
BUFF I79 (o_0r0[26:26], i_0r0[22:22]);
BUFF I80 (o_0r0[27:27], i_0r0[23:23]);
BUFF I81 (o_0r0[28:28], i_0r0[24:24]);
BUFF I82 (o_0r0[29:29], i_0r0[25:25]);
BUFF I83 (o_0r0[30:30], i_0r0[26:26]);
BUFF I84 (o_0r0[31:31], i_0r0[27:27]);
BUFF I85 (o_0r1[0:0], termt_1[0:0]);
BUFF I86 (o_0r1[1:1], termt_1[1:1]);
BUFF I87 (o_0r1[2:2], termt_1[2:2]);
BUFF I88 (o_0r1[3:3], termt_1[3:3]);
BUFF I89 (o_0r1[4:4], i_0r1[0:0]);
BUFF I90 (o_0r1[5:5], i_0r1[1:1]);
BUFF I91 (o_0r1[6:6], i_0r1[2:2]);
BUFF I92 (o_0r1[7:7], i_0r1[3:3]);
BUFF I93 (o_0r1[8:8], i_0r1[4:4]);
BUFF I94 (o_0r1[9:9], i_0r1[5:5]);
BUFF I95 (o_0r1[10:10], i_0r1[6:6]);
BUFF I96 (o_0r1[11:11], i_0r1[7:7]);
BUFF I97 (o_0r1[12:12], i_0r1[8:8]);
BUFF I98 (o_0r1[13:13], i_0r1[9:9]);
BUFF I99 (o_0r1[14:14], i_0r1[10:10]);
BUFF I100 (o_0r1[15:15], i_0r1[11:11]);
BUFF I101 (o_0r1[16:16], i_0r1[12:12]);
BUFF I102 (o_0r1[17:17], i_0r1[13:13]);
BUFF I103 (o_0r1[18:18], i_0r1[14:14]);
BUFF I104 (o_0r1[19:19], i_0r1[15:15]);
BUFF I105 (o_0r1[20:20], i_0r1[16:16]);
BUFF I106 (o_0r1[21:21], i_0r1[17:17]);
BUFF I107 (o_0r1[22:22], i_0r1[18:18]);
BUFF I108 (o_0r1[23:23], i_0r1[19:19]);
BUFF I109 (o_0r1[24:24], i_0r1[20:20]);
BUFF I110 (o_0r1[25:25], i_0r1[21:21]);
BUFF I111 (o_0r1[26:26], i_0r1[22:22]);
BUFF I112 (o_0r1[27:27], i_0r1[23:23]);
BUFF I113 (o_0r1[28:28], i_0r1[24:24]);
BUFF I114 (o_0r1[29:29], i_0r1[25:25]);
BUFF I115 (o_0r1[30:30], i_0r1[26:26]);
BUFF I116 (o_0r1[31:31], i_0r1[27:27]);
BUFF I117 (i_0a, o_0a);
endmodule
// tko28m32_1nm4b0_2api0w28bt1o0w4b TeakO [
// (1,TeakOConstant 4 0),
// (2,TeakOAppend 1 [(0,0+:28),(1,0+:4)])] [One 28,One 32]
module tko28m32_1nm4b0_2api0w28bt1o0w4b (i_0r0, i_0r1, i_0a, o_0r0, o_0r1, o_0a, reset);
input [27:0] i_0r0;
input [27:0] i_0r1;
output i_0a;
output [31:0] o_0r0;
output [31:0] o_0r1;
input o_0a;
input reset;
wire go_0;
wire [27:0] gocomp_0;
wire [9:0] simp301_0;
wire [3:0] simp302_0;
wire [1:0] simp303_0;
wire [3:0] termf_1;
wire [3:0] termt_1;
OR2 I0 (gocomp_0[0:0], i_0r0[0:0], i_0r1[0:0]);
OR2 I1 (gocomp_0[1:1], i_0r0[1:1], i_0r1[1:1]);
OR2 I2 (gocomp_0[2:2], i_0r0[2:2], i_0r1[2:2]);
OR2 I3 (gocomp_0[3:3], i_0r0[3:3], i_0r1[3:3]);
OR2 I4 (gocomp_0[4:4], i_0r0[4:4], i_0r1[4:4]);
OR2 I5 (gocomp_0[5:5], i_0r0[5:5], i_0r1[5:5]);
OR2 I6 (gocomp_0[6:6], i_0r0[6:6], i_0r1[6:6]);
OR2 I7 (gocomp_0[7:7], i_0r0[7:7], i_0r1[7:7]);
OR2 I8 (gocomp_0[8:8], i_0r0[8:8], i_0r1[8:8]);
OR2 I9 (gocomp_0[9:9], i_0r0[9:9], i_0r1[9:9]);
OR2 I10 (gocomp_0[10:10], i_0r0[10:10], i_0r1[10:10]);
OR2 I11 (gocomp_0[11:11], i_0r0[11:11], i_0r1[11:11]);
OR2 I12 (gocomp_0[12:12], i_0r0[12:12], i_0r1[12:12]);
OR2 I13 (gocomp_0[13:13], i_0r0[13:13], i_0r1[13:13]);
OR2 I14 (gocomp_0[14:14], i_0r0[14:14], i_0r1[14:14]);
OR2 I15 (gocomp_0[15:15], i_0r0[15:15], i_0r1[15:15]);
OR2 I16 (gocomp_0[16:16], i_0r0[16:16], i_0r1[16:16]);
OR2 I17 (gocomp_0[17:17], i_0r0[17:17], i_0r1[17:17]);
OR2 I18 (gocomp_0[18:18], i_0r0[18:18], i_0r1[18:18]);
OR2 I19 (gocomp_0[19:19], i_0r0[19:19], i_0r1[19:19]);
OR2 I20 (gocomp_0[20:20], i_0r0[20:20], i_0r1[20:20]);
OR2 I21 (gocomp_0[21:21], i_0r0[21:21], i_0r1[21:21]);
OR2 I22 (gocomp_0[22:22], i_0r0[22:22], i_0r1[22:22]);
OR2 I23 (gocomp_0[23:23], i_0r0[23:23], i_0r1[23:23]);
OR2 I24 (gocomp_0[24:24], i_0r0[24:24], i_0r1[24:24]);
OR2 I25 (gocomp_0[25:25], i_0r0[25:25], i_0r1[25:25]);
OR2 I26 (gocomp_0[26:26], i_0r0[26:26], i_0r1[26:26]);
OR2 I27 (gocomp_0[27:27], i_0r0[27:27], i_0r1[27:27]);
C3 I28 (simp301_0[0:0], gocomp_0[0:0], gocomp_0[1:1], gocomp_0[2:2]);
C3 I29 (simp301_0[1:1], gocomp_0[3:3], gocomp_0[4:4], gocomp_0[5:5]);
C3 I30 (simp301_0[2:2], gocomp_0[6:6], gocomp_0[7:7], gocomp_0[8:8]);
C3 I31 (simp301_0[3:3], gocomp_0[9:9], gocomp_0[10:10], gocomp_0[11:11]);
C3 I32 (simp301_0[4:4], gocomp_0[12:12], gocomp_0[13:13], gocomp_0[14:14]);
C3 I33 (simp301_0[5:5], gocomp_0[15:15], gocomp_0[16:16], gocomp_0[17:17]);
C3 I34 (simp301_0[6:6], gocomp_0[18:18], gocomp_0[19:19], gocomp_0[20:20]);
C3 I35 (simp301_0[7:7], gocomp_0[21:21], gocomp_0[22:22], gocomp_0[23:23]);
C3 I36 (simp301_0[8:8], gocomp_0[24:24], gocomp_0[25:25], gocomp_0[26:26]);
BUFF I37 (simp301_0[9:9], gocomp_0[27:27]);
C3 I38 (simp302_0[0:0], simp301_0[0:0], simp301_0[1:1], simp301_0[2:2]);
C3 I39 (simp302_0[1:1], simp301_0[3:3], simp301_0[4:4], simp301_0[5:5]);
C3 I40 (simp302_0[2:2], simp301_0[6:6], simp301_0[7:7], simp301_0[8:8]);
BUFF I41 (simp302_0[3:3], simp301_0[9:9]);
C3 I42 (simp303_0[0:0], simp302_0[0:0], simp302_0[1:1], simp302_0[2:2]);
BUFF I43 (simp303_0[1:1], simp302_0[3:3]);
C2 I44 (go_0, simp303_0[0:0], simp303_0[1:1]);
BUFF I45 (termf_1[0:0], go_0);
BUFF I46 (termf_1[1:1], go_0);
BUFF I47 (termf_1[2:2], go_0);
BUFF I48 (termf_1[3:3], go_0);
GND I49 (termt_1[0:0]);
GND I50 (termt_1[1:1]);
GND I51 (termt_1[2:2]);
GND I52 (termt_1[3:3]);
BUFF I53 (o_0r0[0:0], i_0r0[0:0]);
BUFF I54 (o_0r0[1:1], i_0r0[1:1]);
BUFF I55 (o_0r0[2:2], i_0r0[2:2]);
BUFF I56 (o_0r0[3:3], i_0r0[3:3]);
BUFF I57 (o_0r0[4:4], i_0r0[4:4]);
BUFF I58 (o_0r0[5:5], i_0r0[5:5]);
BUFF I59 (o_0r0[6:6], i_0r0[6:6]);
BUFF I60 (o_0r0[7:7], i_0r0[7:7]);
BUFF I61 (o_0r0[8:8], i_0r0[8:8]);
BUFF I62 (o_0r0[9:9], i_0r0[9:9]);
BUFF I63 (o_0r0[10:10], i_0r0[10:10]);
BUFF I64 (o_0r0[11:11], i_0r0[11:11]);
BUFF I65 (o_0r0[12:12], i_0r0[12:12]);
BUFF I66 (o_0r0[13:13], i_0r0[13:13]);
BUFF I67 (o_0r0[14:14], i_0r0[14:14]);
BUFF I68 (o_0r0[15:15], i_0r0[15:15]);
BUFF I69 (o_0r0[16:16], i_0r0[16:16]);
BUFF I70 (o_0r0[17:17], i_0r0[17:17]);
BUFF I71 (o_0r0[18:18], i_0r0[18:18]);
BUFF I72 (o_0r0[19:19], i_0r0[19:19]);
BUFF I73 (o_0r0[20:20], i_0r0[20:20]);
BUFF I74 (o_0r0[21:21], i_0r0[21:21]);
BUFF I75 (o_0r0[22:22], i_0r0[22:22]);
BUFF I76 (o_0r0[23:23], i_0r0[23:23]);
BUFF I77 (o_0r0[24:24], i_0r0[24:24]);
BUFF I78 (o_0r0[25:25], i_0r0[25:25]);
BUFF I79 (o_0r0[26:26], i_0r0[26:26]);
BUFF I80 (o_0r0[27:27], i_0r0[27:27]);
BUFF I81 (o_0r0[28:28], termf_1[0:0]);
BUFF I82 (o_0r0[29:29], termf_1[1:1]);
BUFF I83 (o_0r0[30:30], termf_1[2:2]);
BUFF I84 (o_0r0[31:31], termf_1[3:3]);
BUFF I85 (o_0r1[0:0], i_0r1[0:0]);
BUFF I86 (o_0r1[1:1], i_0r1[1:1]);
BUFF I87 (o_0r1[2:2], i_0r1[2:2]);
BUFF I88 (o_0r1[3:3], i_0r1[3:3]);
BUFF I89 (o_0r1[4:4], i_0r1[4:4]);
BUFF I90 (o_0r1[5:5], i_0r1[5:5]);
BUFF I91 (o_0r1[6:6], i_0r1[6:6]);
BUFF I92 (o_0r1[7:7], i_0r1[7:7]);
BUFF I93 (o_0r1[8:8], i_0r1[8:8]);
BUFF I94 (o_0r1[9:9], i_0r1[9:9]);
BUFF I95 (o_0r1[10:10], i_0r1[10:10]);
BUFF I96 (o_0r1[11:11], i_0r1[11:11]);
BUFF I97 (o_0r1[12:12], i_0r1[12:12]);
BUFF I98 (o_0r1[13:13], i_0r1[13:13]);
BUFF I99 (o_0r1[14:14], i_0r1[14:14]);
BUFF I100 (o_0r1[15:15], i_0r1[15:15]);
BUFF I101 (o_0r1[16:16], i_0r1[16:16]);
BUFF I102 (o_0r1[17:17], i_0r1[17:17]);
BUFF I103 (o_0r1[18:18], i_0r1[18:18]);
BUFF I104 (o_0r1[19:19], i_0r1[19:19]);
BUFF I105 (o_0r1[20:20], i_0r1[20:20]);
BUFF I106 (o_0r1[21:21], i_0r1[21:21]);
BUFF I107 (o_0r1[22:22], i_0r1[22:22]);
BUFF I108 (o_0r1[23:23], i_0r1[23:23]);
BUFF I109 (o_0r1[24:24], i_0r1[24:24]);
BUFF I110 (o_0r1[25:25], i_0r1[25:25]);
BUFF I111 (o_0r1[26:26], i_0r1[26:26]);
BUFF I112 (o_0r1[27:27], i_0r1[27:27]);
BUFF I113 (o_0r1[28:28], termt_1[0:0]);
BUFF I114 (o_0r1[29:29], termt_1[1:1]);
BUFF I115 (o_0r1[30:30], termt_1[2:2]);
BUFF I116 (o_0r1[31:31], termt_1[3:3]);
BUFF I117 (i_0a, o_0a);
endmodule
// tko28m32_1nm4bf_2api0w28bt1o0w4b TeakO [
// (1,TeakOConstant 4 15),
// (2,TeakOAppend 1 [(0,0+:28),(1,0+:4)])] [One 28,One 32]
module tko28m32_1nm4bf_2api0w28bt1o0w4b (i_0r0, i_0r1, i_0a, o_0r0, o_0r1, o_0a, reset);
input [27:0] i_0r0;
input [27:0] i_0r1;
output i_0a;
output [31:0] o_0r0;
output [31:0] o_0r1;
input o_0a;
input reset;
wire go_0;
wire [27:0] gocomp_0;
wire [9:0] simp301_0;
wire [3:0] simp302_0;
wire [1:0] simp303_0;
wire [3:0] termf_1;
wire [3:0] termt_1;
OR2 I0 (gocomp_0[0:0], i_0r0[0:0], i_0r1[0:0]);
OR2 I1 (gocomp_0[1:1], i_0r0[1:1], i_0r1[1:1]);
OR2 I2 (gocomp_0[2:2], i_0r0[2:2], i_0r1[2:2]);
OR2 I3 (gocomp_0[3:3], i_0r0[3:3], i_0r1[3:3]);
OR2 I4 (gocomp_0[4:4], i_0r0[4:4], i_0r1[4:4]);
OR2 I5 (gocomp_0[5:5], i_0r0[5:5], i_0r1[5:5]);
OR2 I6 (gocomp_0[6:6], i_0r0[6:6], i_0r1[6:6]);
OR2 I7 (gocomp_0[7:7], i_0r0[7:7], i_0r1[7:7]);
OR2 I8 (gocomp_0[8:8], i_0r0[8:8], i_0r1[8:8]);
OR2 I9 (gocomp_0[9:9], i_0r0[9:9], i_0r1[9:9]);
OR2 I10 (gocomp_0[10:10], i_0r0[10:10], i_0r1[10:10]);
OR2 I11 (gocomp_0[11:11], i_0r0[11:11], i_0r1[11:11]);
OR2 I12 (gocomp_0[12:12], i_0r0[12:12], i_0r1[12:12]);
OR2 I13 (gocomp_0[13:13], i_0r0[13:13], i_0r1[13:13]);
OR2 I14 (gocomp_0[14:14], i_0r0[14:14], i_0r1[14:14]);
OR2 I15 (gocomp_0[15:15], i_0r0[15:15], i_0r1[15:15]);
OR2 I16 (gocomp_0[16:16], i_0r0[16:16], i_0r1[16:16]);
OR2 I17 (gocomp_0[17:17], i_0r0[17:17], i_0r1[17:17]);
OR2 I18 (gocomp_0[18:18], i_0r0[18:18], i_0r1[18:18]);
OR2 I19 (gocomp_0[19:19], i_0r0[19:19], i_0r1[19:19]);
OR2 I20 (gocomp_0[20:20], i_0r0[20:20], i_0r1[20:20]);
OR2 I21 (gocomp_0[21:21], i_0r0[21:21], i_0r1[21:21]);
OR2 I22 (gocomp_0[22:22], i_0r0[22:22], i_0r1[22:22]);
OR2 I23 (gocomp_0[23:23], i_0r0[23:23], i_0r1[23:23]);
OR2 I24 (gocomp_0[24:24], i_0r0[24:24], i_0r1[24:24]);
OR2 I25 (gocomp_0[25:25], i_0r0[25:25], i_0r1[25:25]);
OR2 I26 (gocomp_0[26:26], i_0r0[26:26], i_0r1[26:26]);
OR2 I27 (gocomp_0[27:27], i_0r0[27:27], i_0r1[27:27]);
C3 I28 (simp301_0[0:0], gocomp_0[0:0], gocomp_0[1:1], gocomp_0[2:2]);
C3 I29 (simp301_0[1:1], gocomp_0[3:3], gocomp_0[4:4], gocomp_0[5:5]);
C3 I30 (simp301_0[2:2], gocomp_0[6:6], gocomp_0[7:7], gocomp_0[8:8]);
C3 I31 (simp301_0[3:3], gocomp_0[9:9], gocomp_0[10:10], gocomp_0[11:11]);
C3 I32 (simp301_0[4:4], gocomp_0[12:12], gocomp_0[13:13], gocomp_0[14:14]);
C3 I33 (simp301_0[5:5], gocomp_0[15:15], gocomp_0[16:16], gocomp_0[17:17]);
C3 I34 (simp301_0[6:6], gocomp_0[18:18], gocomp_0[19:19], gocomp_0[20:20]);
C3 I35 (simp301_0[7:7], gocomp_0[21:21], gocomp_0[22:22], gocomp_0[23:23]);
C3 I36 (simp301_0[8:8], gocomp_0[24:24], gocomp_0[25:25], gocomp_0[26:26]);
BUFF I37 (simp301_0[9:9], gocomp_0[27:27]);
C3 I38 (simp302_0[0:0], simp301_0[0:0], simp301_0[1:1], simp301_0[2:2]);
C3 I39 (simp302_0[1:1], simp301_0[3:3], simp301_0[4:4], simp301_0[5:5]);
C3 I40 (simp302_0[2:2], simp301_0[6:6], simp301_0[7:7], simp301_0[8:8]);
BUFF I41 (simp302_0[3:3], simp301_0[9:9]);
C3 I42 (simp303_0[0:0], simp302_0[0:0], simp302_0[1:1], simp302_0[2:2]);
BUFF I43 (simp303_0[1:1], simp302_0[3:3]);
C2 I44 (go_0, simp303_0[0:0], simp303_0[1:1]);
BUFF I45 (termt_1[0:0], go_0);
BUFF I46 (termt_1[1:1], go_0);
BUFF I47 (termt_1[2:2], go_0);
BUFF I48 (termt_1[3:3], go_0);
GND I49 (termf_1[0:0]);
GND I50 (termf_1[1:1]);
GND I51 (termf_1[2:2]);
GND I52 (termf_1[3:3]);
BUFF I53 (o_0r0[0:0], i_0r0[0:0]);
BUFF I54 (o_0r0[1:1], i_0r0[1:1]);
BUFF I55 (o_0r0[2:2], i_0r0[2:2]);
BUFF I56 (o_0r0[3:3], i_0r0[3:3]);
BUFF I57 (o_0r0[4:4], i_0r0[4:4]);
BUFF I58 (o_0r0[5:5], i_0r0[5:5]);
BUFF I59 (o_0r0[6:6], i_0r0[6:6]);
BUFF I60 (o_0r0[7:7], i_0r0[7:7]);
BUFF I61 (o_0r0[8:8], i_0r0[8:8]);
BUFF I62 (o_0r0[9:9], i_0r0[9:9]);
BUFF I63 (o_0r0[10:10], i_0r0[10:10]);
BUFF I64 (o_0r0[11:11], i_0r0[11:11]);
BUFF I65 (o_0r0[12:12], i_0r0[12:12]);
BUFF I66 (o_0r0[13:13], i_0r0[13:13]);
BUFF I67 (o_0r0[14:14], i_0r0[14:14]);
BUFF I68 (o_0r0[15:15], i_0r0[15:15]);
BUFF I69 (o_0r0[16:16], i_0r0[16:16]);
BUFF I70 (o_0r0[17:17], i_0r0[17:17]);
BUFF I71 (o_0r0[18:18], i_0r0[18:18]);
BUFF I72 (o_0r0[19:19], i_0r0[19:19]);
BUFF I73 (o_0r0[20:20], i_0r0[20:20]);
BUFF I74 (o_0r0[21:21], i_0r0[21:21]);
BUFF I75 (o_0r0[22:22], i_0r0[22:22]);
BUFF I76 (o_0r0[23:23], i_0r0[23:23]);
BUFF I77 (o_0r0[24:24], i_0r0[24:24]);
BUFF I78 (o_0r0[25:25], i_0r0[25:25]);
BUFF I79 (o_0r0[26:26], i_0r0[26:26]);
BUFF I80 (o_0r0[27:27], i_0r0[27:27]);
BUFF I81 (o_0r0[28:28], termf_1[0:0]);
BUFF I82 (o_0r0[29:29], termf_1[1:1]);
BUFF I83 (o_0r0[30:30], termf_1[2:2]);
BUFF I84 (o_0r0[31:31], termf_1[3:3]);
BUFF I85 (o_0r1[0:0], i_0r1[0:0]);
BUFF I86 (o_0r1[1:1], i_0r1[1:1]);
BUFF I87 (o_0r1[2:2], i_0r1[2:2]);
BUFF I88 (o_0r1[3:3], i_0r1[3:3]);
BUFF I89 (o_0r1[4:4], i_0r1[4:4]);
BUFF I90 (o_0r1[5:5], i_0r1[5:5]);
BUFF I91 (o_0r1[6:6], i_0r1[6:6]);
BUFF I92 (o_0r1[7:7], i_0r1[7:7]);
BUFF I93 (o_0r1[8:8], i_0r1[8:8]);
BUFF I94 (o_0r1[9:9], i_0r1[9:9]);
BUFF I95 (o_0r1[10:10], i_0r1[10:10]);
BUFF I96 (o_0r1[11:11], i_0r1[11:11]);
BUFF I97 (o_0r1[12:12], i_0r1[12:12]);
BUFF I98 (o_0r1[13:13], i_0r1[13:13]);
BUFF I99 (o_0r1[14:14], i_0r1[14:14]);
BUFF I100 (o_0r1[15:15], i_0r1[15:15]);
BUFF I101 (o_0r1[16:16], i_0r1[16:16]);
BUFF I102 (o_0r1[17:17], i_0r1[17:17]);
BUFF I103 (o_0r1[18:18], i_0r1[18:18]);
BUFF I104 (o_0r1[19:19], i_0r1[19:19]);
BUFF I105 (o_0r1[20:20], i_0r1[20:20]);
BUFF I106 (o_0r1[21:21], i_0r1[21:21]);
BUFF I107 (o_0r1[22:22], i_0r1[22:22]);
BUFF I108 (o_0r1[23:23], i_0r1[23:23]);
BUFF I109 (o_0r1[24:24], i_0r1[24:24]);
BUFF I110 (o_0r1[25:25], i_0r1[25:25]);
BUFF I111 (o_0r1[26:26], i_0r1[26:26]);
BUFF I112 (o_0r1[27:27], i_0r1[27:27]);
BUFF I113 (o_0r1[28:28], termt_1[0:0]);
BUFF I114 (o_0r1[29:29], termt_1[1:1]);
BUFF I115 (o_0r1[30:30], termt_1[2:2]);
BUFF I116 (o_0r1[31:31], termt_1[3:3]);
BUFF I117 (i_0a, o_0a);
endmodule
// tkvi32_wo0w32_ro0w32o0w28o4w28o4w28 TeakV "i" 32 [] [0] [0,0,4,4] [Many [32],Many [0],Many [0,0,0,0]
// ,Many [32,28,28,28]]
module tkvi32_wo0w32_ro0w32o0w28o4w28o4w28 (wg_0r0, wg_0r1, wg_0a, wd_0r, wd_0a, rg_0r, rg_0a, rg_1r, rg_1a, rg_2r, rg_2a, rg_3r, rg_3a, rd_0r0, rd_0r1, rd_0a, rd_1r0, rd_1r1, rd_1a, rd_2r0, rd_2r1, rd_2a, rd_3r0, rd_3r1, rd_3a, reset);
input [31:0] wg_0r0;
input [31:0] wg_0r1;
output wg_0a;
output wd_0r;
input wd_0a;
input rg_0r;
output rg_0a;
input rg_1r;
output rg_1a;
input rg_2r;
output rg_2a;
input rg_3r;
output rg_3a;
output [31:0] rd_0r0;
output [31:0] rd_0r1;
input rd_0a;
output [27:0] rd_1r0;
output [27:0] rd_1r1;
input rd_1a;
output [27:0] rd_2r0;
output [27:0] rd_2r1;
input rd_2a;
output [27:0] rd_3r0;
output [27:0] rd_3r1;
input rd_3a;
input reset;
wire [31:0] wf_0;
wire [31:0] wt_0;
wire [31:0] df_0;
wire [31:0] dt_0;
wire wc_0;
wire [31:0] wacks_0;
wire [31:0] wenr_0;
wire [31:0] wen_0;
wire anyread_0;
wire nreset_0;
wire [31:0] drlgf_0;
wire [31:0] drlgt_0;
wire [31:0] comp0_0;
wire [10:0] simp2381_0;
wire [3:0] simp2382_0;
wire [1:0] simp2383_0;
wire conwigc_0;
wire conwigcanw_0;
wire [31:0] conwgit_0;
wire [31:0] conwgif_0;
wire conwig_0;
wire [10:0] simp4071_0;
wire [3:0] simp4072_0;
wire [1:0] simp4073_0;
wire [2:0] simp6401_0;
INV I0 (nreset_0, reset);
AND2 I1 (wen_0[0:0], wenr_0[0:0], nreset_0);
AND2 I2 (wen_0[1:1], wenr_0[1:1], nreset_0);
AND2 I3 (wen_0[2:2], wenr_0[2:2], nreset_0);
AND2 I4 (wen_0[3:3], wenr_0[3:3], nreset_0);
AND2 I5 (wen_0[4:4], wenr_0[4:4], nreset_0);
AND2 I6 (wen_0[5:5], wenr_0[5:5], nreset_0);
AND2 I7 (wen_0[6:6], wenr_0[6:6], nreset_0);
AND2 I8 (wen_0[7:7], wenr_0[7:7], nreset_0);
AND2 I9 (wen_0[8:8], wenr_0[8:8], nreset_0);
AND2 I10 (wen_0[9:9], wenr_0[9:9], nreset_0);
AND2 I11 (wen_0[10:10], wenr_0[10:10], nreset_0);
AND2 I12 (wen_0[11:11], wenr_0[11:11], nreset_0);
AND2 I13 (wen_0[12:12], wenr_0[12:12], nreset_0);
AND2 I14 (wen_0[13:13], wenr_0[13:13], nreset_0);
AND2 I15 (wen_0[14:14], wenr_0[14:14], nreset_0);
AND2 I16 (wen_0[15:15], wenr_0[15:15], nreset_0);
AND2 I17 (wen_0[16:16], wenr_0[16:16], nreset_0);
AND2 I18 (wen_0[17:17], wenr_0[17:17], nreset_0);
AND2 I19 (wen_0[18:18], wenr_0[18:18], nreset_0);
AND2 I20 (wen_0[19:19], wenr_0[19:19], nreset_0);
AND2 I21 (wen_0[20:20], wenr_0[20:20], nreset_0);
AND2 I22 (wen_0[21:21], wenr_0[21:21], nreset_0);
AND2 I23 (wen_0[22:22], wenr_0[22:22], nreset_0);
AND2 I24 (wen_0[23:23], wenr_0[23:23], nreset_0);
AND2 I25 (wen_0[24:24], wenr_0[24:24], nreset_0);
AND2 I26 (wen_0[25:25], wenr_0[25:25], nreset_0);
AND2 I27 (wen_0[26:26], wenr_0[26:26], nreset_0);
AND2 I28 (wen_0[27:27], wenr_0[27:27], nreset_0);
AND2 I29 (wen_0[28:28], wenr_0[28:28], nreset_0);
AND2 I30 (wen_0[29:29], wenr_0[29:29], nreset_0);
AND2 I31 (wen_0[30:30], wenr_0[30:30], nreset_0);
AND2 I32 (wen_0[31:31], wenr_0[31:31], nreset_0);
AND2 I33 (drlgf_0[0:0], wf_0[0:0], wen_0[0:0]);
AND2 I34 (drlgf_0[1:1], wf_0[1:1], wen_0[1:1]);
AND2 I35 (drlgf_0[2:2], wf_0[2:2], wen_0[2:2]);
AND2 I36 (drlgf_0[3:3], wf_0[3:3], wen_0[3:3]);
AND2 I37 (drlgf_0[4:4], wf_0[4:4], wen_0[4:4]);
AND2 I38 (drlgf_0[5:5], wf_0[5:5], wen_0[5:5]);
AND2 I39 (drlgf_0[6:6], wf_0[6:6], wen_0[6:6]);
AND2 I40 (drlgf_0[7:7], wf_0[7:7], wen_0[7:7]);
AND2 I41 (drlgf_0[8:8], wf_0[8:8], wen_0[8:8]);
AND2 I42 (drlgf_0[9:9], wf_0[9:9], wen_0[9:9]);
AND2 I43 (drlgf_0[10:10], wf_0[10:10], wen_0[10:10]);
AND2 I44 (drlgf_0[11:11], wf_0[11:11], wen_0[11:11]);
AND2 I45 (drlgf_0[12:12], wf_0[12:12], wen_0[12:12]);
AND2 I46 (drlgf_0[13:13], wf_0[13:13], wen_0[13:13]);
AND2 I47 (drlgf_0[14:14], wf_0[14:14], wen_0[14:14]);
AND2 I48 (drlgf_0[15:15], wf_0[15:15], wen_0[15:15]);
AND2 I49 (drlgf_0[16:16], wf_0[16:16], wen_0[16:16]);
AND2 I50 (drlgf_0[17:17], wf_0[17:17], wen_0[17:17]);
AND2 I51 (drlgf_0[18:18], wf_0[18:18], wen_0[18:18]);
AND2 I52 (drlgf_0[19:19], wf_0[19:19], wen_0[19:19]);
AND2 I53 (drlgf_0[20:20], wf_0[20:20], wen_0[20:20]);
AND2 I54 (drlgf_0[21:21], wf_0[21:21], wen_0[21:21]);
AND2 I55 (drlgf_0[22:22], wf_0[22:22], wen_0[22:22]);
AND2 I56 (drlgf_0[23:23], wf_0[23:23], wen_0[23:23]);
AND2 I57 (drlgf_0[24:24], wf_0[24:24], wen_0[24:24]);
AND2 I58 (drlgf_0[25:25], wf_0[25:25], wen_0[25:25]);
AND2 I59 (drlgf_0[26:26], wf_0[26:26], wen_0[26:26]);
AND2 I60 (drlgf_0[27:27], wf_0[27:27], wen_0[27:27]);
AND2 I61 (drlgf_0[28:28], wf_0[28:28], wen_0[28:28]);
AND2 I62 (drlgf_0[29:29], wf_0[29:29], wen_0[29:29]);
AND2 I63 (drlgf_0[30:30], wf_0[30:30], wen_0[30:30]);
AND2 I64 (drlgf_0[31:31], wf_0[31:31], wen_0[31:31]);
AND2 I65 (drlgt_0[0:0], wt_0[0:0], wen_0[0:0]);
AND2 I66 (drlgt_0[1:1], wt_0[1:1], wen_0[1:1]);
AND2 I67 (drlgt_0[2:2], wt_0[2:2], wen_0[2:2]);
AND2 I68 (drlgt_0[3:3], wt_0[3:3], wen_0[3:3]);
AND2 I69 (drlgt_0[4:4], wt_0[4:4], wen_0[4:4]);
AND2 I70 (drlgt_0[5:5], wt_0[5:5], wen_0[5:5]);
AND2 I71 (drlgt_0[6:6], wt_0[6:6], wen_0[6:6]);
AND2 I72 (drlgt_0[7:7], wt_0[7:7], wen_0[7:7]);
AND2 I73 (drlgt_0[8:8], wt_0[8:8], wen_0[8:8]);
AND2 I74 (drlgt_0[9:9], wt_0[9:9], wen_0[9:9]);
AND2 I75 (drlgt_0[10:10], wt_0[10:10], wen_0[10:10]);
AND2 I76 (drlgt_0[11:11], wt_0[11:11], wen_0[11:11]);
AND2 I77 (drlgt_0[12:12], wt_0[12:12], wen_0[12:12]);
AND2 I78 (drlgt_0[13:13], wt_0[13:13], wen_0[13:13]);
AND2 I79 (drlgt_0[14:14], wt_0[14:14], wen_0[14:14]);
AND2 I80 (drlgt_0[15:15], wt_0[15:15], wen_0[15:15]);
AND2 I81 (drlgt_0[16:16], wt_0[16:16], wen_0[16:16]);
AND2 I82 (drlgt_0[17:17], wt_0[17:17], wen_0[17:17]);
AND2 I83 (drlgt_0[18:18], wt_0[18:18], wen_0[18:18]);
AND2 I84 (drlgt_0[19:19], wt_0[19:19], wen_0[19:19]);
AND2 I85 (drlgt_0[20:20], wt_0[20:20], wen_0[20:20]);
AND2 I86 (drlgt_0[21:21], wt_0[21:21], wen_0[21:21]);
AND2 I87 (drlgt_0[22:22], wt_0[22:22], wen_0[22:22]);
AND2 I88 (drlgt_0[23:23], wt_0[23:23], wen_0[23:23]);
AND2 I89 (drlgt_0[24:24], wt_0[24:24], wen_0[24:24]);
AND2 I90 (drlgt_0[25:25], wt_0[25:25], wen_0[25:25]);
AND2 I91 (drlgt_0[26:26], wt_0[26:26], wen_0[26:26]);
AND2 I92 (drlgt_0[27:27], wt_0[27:27], wen_0[27:27]);
AND2 I93 (drlgt_0[28:28], wt_0[28:28], wen_0[28:28]);
AND2 I94 (drlgt_0[29:29], wt_0[29:29], wen_0[29:29]);
AND2 I95 (drlgt_0[30:30], wt_0[30:30], wen_0[30:30]);
AND2 I96 (drlgt_0[31:31], wt_0[31:31], wen_0[31:31]);
NOR2 I97 (df_0[0:0], dt_0[0:0], drlgt_0[0:0]);
NOR2 I98 (df_0[1:1], dt_0[1:1], drlgt_0[1:1]);
NOR2 I99 (df_0[2:2], dt_0[2:2], drlgt_0[2:2]);
NOR2 I100 (df_0[3:3], dt_0[3:3], drlgt_0[3:3]);
NOR2 I101 (df_0[4:4], dt_0[4:4], drlgt_0[4:4]);
NOR2 I102 (df_0[5:5], dt_0[5:5], drlgt_0[5:5]);
NOR2 I103 (df_0[6:6], dt_0[6:6], drlgt_0[6:6]);
NOR2 I104 (df_0[7:7], dt_0[7:7], drlgt_0[7:7]);
NOR2 I105 (df_0[8:8], dt_0[8:8], drlgt_0[8:8]);
NOR2 I106 (df_0[9:9], dt_0[9:9], drlgt_0[9:9]);
NOR2 I107 (df_0[10:10], dt_0[10:10], drlgt_0[10:10]);
NOR2 I108 (df_0[11:11], dt_0[11:11], drlgt_0[11:11]);
NOR2 I109 (df_0[12:12], dt_0[12:12], drlgt_0[12:12]);
NOR2 I110 (df_0[13:13], dt_0[13:13], drlgt_0[13:13]);
NOR2 I111 (df_0[14:14], dt_0[14:14], drlgt_0[14:14]);
NOR2 I112 (df_0[15:15], dt_0[15:15], drlgt_0[15:15]);
NOR2 I113 (df_0[16:16], dt_0[16:16], drlgt_0[16:16]);
NOR2 I114 (df_0[17:17], dt_0[17:17], drlgt_0[17:17]);
NOR2 I115 (df_0[18:18], dt_0[18:18], drlgt_0[18:18]);
NOR2 I116 (df_0[19:19], dt_0[19:19], drlgt_0[19:19]);
NOR2 I117 (df_0[20:20], dt_0[20:20], drlgt_0[20:20]);
NOR2 I118 (df_0[21:21], dt_0[21:21], drlgt_0[21:21]);
NOR2 I119 (df_0[22:22], dt_0[22:22], drlgt_0[22:22]);
NOR2 I120 (df_0[23:23], dt_0[23:23], drlgt_0[23:23]);
NOR2 I121 (df_0[24:24], dt_0[24:24], drlgt_0[24:24]);
NOR2 I122 (df_0[25:25], dt_0[25:25], drlgt_0[25:25]);
NOR2 I123 (df_0[26:26], dt_0[26:26], drlgt_0[26:26]);
NOR2 I124 (df_0[27:27], dt_0[27:27], drlgt_0[27:27]);
NOR2 I125 (df_0[28:28], dt_0[28:28], drlgt_0[28:28]);
NOR2 I126 (df_0[29:29], dt_0[29:29], drlgt_0[29:29]);
NOR2 I127 (df_0[30:30], dt_0[30:30], drlgt_0[30:30]);
NOR2 I128 (df_0[31:31], dt_0[31:31], drlgt_0[31:31]);
NOR3 I129 (dt_0[0:0], df_0[0:0], drlgf_0[0:0], reset);
NOR3 I130 (dt_0[1:1], df_0[1:1], drlgf_0[1:1], reset);
NOR3 I131 (dt_0[2:2], df_0[2:2], drlgf_0[2:2], reset);
NOR3 I132 (dt_0[3:3], df_0[3:3], drlgf_0[3:3], reset);
NOR3 I133 (dt_0[4:4], df_0[4:4], drlgf_0[4:4], reset);
NOR3 I134 (dt_0[5:5], df_0[5:5], drlgf_0[5:5], reset);
NOR3 I135 (dt_0[6:6], df_0[6:6], drlgf_0[6:6], reset);
NOR3 I136 (dt_0[7:7], df_0[7:7], drlgf_0[7:7], reset);
NOR3 I137 (dt_0[8:8], df_0[8:8], drlgf_0[8:8], reset);
NOR3 I138 (dt_0[9:9], df_0[9:9], drlgf_0[9:9], reset);
NOR3 I139 (dt_0[10:10], df_0[10:10], drlgf_0[10:10], reset);
NOR3 I140 (dt_0[11:11], df_0[11:11], drlgf_0[11:11], reset);
NOR3 I141 (dt_0[12:12], df_0[12:12], drlgf_0[12:12], reset);
NOR3 I142 (dt_0[13:13], df_0[13:13], drlgf_0[13:13], reset);
NOR3 I143 (dt_0[14:14], df_0[14:14], drlgf_0[14:14], reset);
NOR3 I144 (dt_0[15:15], df_0[15:15], drlgf_0[15:15], reset);
NOR3 I145 (dt_0[16:16], df_0[16:16], drlgf_0[16:16], reset);
NOR3 I146 (dt_0[17:17], df_0[17:17], drlgf_0[17:17], reset);
NOR3 I147 (dt_0[18:18], df_0[18:18], drlgf_0[18:18], reset);
NOR3 I148 (dt_0[19:19], df_0[19:19], drlgf_0[19:19], reset);
NOR3 I149 (dt_0[20:20], df_0[20:20], drlgf_0[20:20], reset);
NOR3 I150 (dt_0[21:21], df_0[21:21], drlgf_0[21:21], reset);
NOR3 I151 (dt_0[22:22], df_0[22:22], drlgf_0[22:22], reset);
NOR3 I152 (dt_0[23:23], df_0[23:23], drlgf_0[23:23], reset);
NOR3 I153 (dt_0[24:24], df_0[24:24], drlgf_0[24:24], reset);
NOR3 I154 (dt_0[25:25], df_0[25:25], drlgf_0[25:25], reset);
NOR3 I155 (dt_0[26:26], df_0[26:26], drlgf_0[26:26], reset);
NOR3 I156 (dt_0[27:27], df_0[27:27], drlgf_0[27:27], reset);
NOR3 I157 (dt_0[28:28], df_0[28:28], drlgf_0[28:28], reset);
NOR3 I158 (dt_0[29:29], df_0[29:29], drlgf_0[29:29], reset);
NOR3 I159 (dt_0[30:30], df_0[30:30], drlgf_0[30:30], reset);
NOR3 I160 (dt_0[31:31], df_0[31:31], drlgf_0[31:31], reset);
AO22 I161 (wacks_0[0:0], drlgf_0[0:0], df_0[0:0], drlgt_0[0:0], dt_0[0:0]);
AO22 I162 (wacks_0[1:1], drlgf_0[1:1], df_0[1:1], drlgt_0[1:1], dt_0[1:1]);
AO22 I163 (wacks_0[2:2], drlgf_0[2:2], df_0[2:2], drlgt_0[2:2], dt_0[2:2]);
AO22 I164 (wacks_0[3:3], drlgf_0[3:3], df_0[3:3], drlgt_0[3:3], dt_0[3:3]);
AO22 I165 (wacks_0[4:4], drlgf_0[4:4], df_0[4:4], drlgt_0[4:4], dt_0[4:4]);
AO22 I166 (wacks_0[5:5], drlgf_0[5:5], df_0[5:5], drlgt_0[5:5], dt_0[5:5]);
AO22 I167 (wacks_0[6:6], drlgf_0[6:6], df_0[6:6], drlgt_0[6:6], dt_0[6:6]);
AO22 I168 (wacks_0[7:7], drlgf_0[7:7], df_0[7:7], drlgt_0[7:7], dt_0[7:7]);
AO22 I169 (wacks_0[8:8], drlgf_0[8:8], df_0[8:8], drlgt_0[8:8], dt_0[8:8]);
AO22 I170 (wacks_0[9:9], drlgf_0[9:9], df_0[9:9], drlgt_0[9:9], dt_0[9:9]);
AO22 I171 (wacks_0[10:10], drlgf_0[10:10], df_0[10:10], drlgt_0[10:10], dt_0[10:10]);
AO22 I172 (wacks_0[11:11], drlgf_0[11:11], df_0[11:11], drlgt_0[11:11], dt_0[11:11]);
AO22 I173 (wacks_0[12:12], drlgf_0[12:12], df_0[12:12], drlgt_0[12:12], dt_0[12:12]);
AO22 I174 (wacks_0[13:13], drlgf_0[13:13], df_0[13:13], drlgt_0[13:13], dt_0[13:13]);
AO22 I175 (wacks_0[14:14], drlgf_0[14:14], df_0[14:14], drlgt_0[14:14], dt_0[14:14]);
AO22 I176 (wacks_0[15:15], drlgf_0[15:15], df_0[15:15], drlgt_0[15:15], dt_0[15:15]);
AO22 I177 (wacks_0[16:16], drlgf_0[16:16], df_0[16:16], drlgt_0[16:16], dt_0[16:16]);
AO22 I178 (wacks_0[17:17], drlgf_0[17:17], df_0[17:17], drlgt_0[17:17], dt_0[17:17]);
AO22 I179 (wacks_0[18:18], drlgf_0[18:18], df_0[18:18], drlgt_0[18:18], dt_0[18:18]);
AO22 I180 (wacks_0[19:19], drlgf_0[19:19], df_0[19:19], drlgt_0[19:19], dt_0[19:19]);
AO22 I181 (wacks_0[20:20], drlgf_0[20:20], df_0[20:20], drlgt_0[20:20], dt_0[20:20]);
AO22 I182 (wacks_0[21:21], drlgf_0[21:21], df_0[21:21], drlgt_0[21:21], dt_0[21:21]);
AO22 I183 (wacks_0[22:22], drlgf_0[22:22], df_0[22:22], drlgt_0[22:22], dt_0[22:22]);
AO22 I184 (wacks_0[23:23], drlgf_0[23:23], df_0[23:23], drlgt_0[23:23], dt_0[23:23]);
AO22 I185 (wacks_0[24:24], drlgf_0[24:24], df_0[24:24], drlgt_0[24:24], dt_0[24:24]);
AO22 I186 (wacks_0[25:25], drlgf_0[25:25], df_0[25:25], drlgt_0[25:25], dt_0[25:25]);
AO22 I187 (wacks_0[26:26], drlgf_0[26:26], df_0[26:26], drlgt_0[26:26], dt_0[26:26]);
AO22 I188 (wacks_0[27:27], drlgf_0[27:27], df_0[27:27], drlgt_0[27:27], dt_0[27:27]);
AO22 I189 (wacks_0[28:28], drlgf_0[28:28], df_0[28:28], drlgt_0[28:28], dt_0[28:28]);
AO22 I190 (wacks_0[29:29], drlgf_0[29:29], df_0[29:29], drlgt_0[29:29], dt_0[29:29]);
AO22 I191 (wacks_0[30:30], drlgf_0[30:30], df_0[30:30], drlgt_0[30:30], dt_0[30:30]);
AO22 I192 (wacks_0[31:31], drlgf_0[31:31], df_0[31:31], drlgt_0[31:31], dt_0[31:31]);
OR2 I193 (comp0_0[0:0], wg_0r0[0:0], wg_0r1[0:0]);
OR2 I194 (comp0_0[1:1], wg_0r0[1:1], wg_0r1[1:1]);
OR2 I195 (comp0_0[2:2], wg_0r0[2:2], wg_0r1[2:2]);
OR2 I196 (comp0_0[3:3], wg_0r0[3:3], wg_0r1[3:3]);
OR2 I197 (comp0_0[4:4], wg_0r0[4:4], wg_0r1[4:4]);
OR2 I198 (comp0_0[5:5], wg_0r0[5:5], wg_0r1[5:5]);
OR2 I199 (comp0_0[6:6], wg_0r0[6:6], wg_0r1[6:6]);
OR2 I200 (comp0_0[7:7], wg_0r0[7:7], wg_0r1[7:7]);
OR2 I201 (comp0_0[8:8], wg_0r0[8:8], wg_0r1[8:8]);
OR2 I202 (comp0_0[9:9], wg_0r0[9:9], wg_0r1[9:9]);
OR2 I203 (comp0_0[10:10], wg_0r0[10:10], wg_0r1[10:10]);
OR2 I204 (comp0_0[11:11], wg_0r0[11:11], wg_0r1[11:11]);
OR2 I205 (comp0_0[12:12], wg_0r0[12:12], wg_0r1[12:12]);
OR2 I206 (comp0_0[13:13], wg_0r0[13:13], wg_0r1[13:13]);
OR2 I207 (comp0_0[14:14], wg_0r0[14:14], wg_0r1[14:14]);
OR2 I208 (comp0_0[15:15], wg_0r0[15:15], wg_0r1[15:15]);
OR2 I209 (comp0_0[16:16], wg_0r0[16:16], wg_0r1[16:16]);
OR2 I210 (comp0_0[17:17], wg_0r0[17:17], wg_0r1[17:17]);
OR2 I211 (comp0_0[18:18], wg_0r0[18:18], wg_0r1[18:18]);
OR2 I212 (comp0_0[19:19], wg_0r0[19:19], wg_0r1[19:19]);
OR2 I213 (comp0_0[20:20], wg_0r0[20:20], wg_0r1[20:20]);
OR2 I214 (comp0_0[21:21], wg_0r0[21:21], wg_0r1[21:21]);
OR2 I215 (comp0_0[22:22], wg_0r0[22:22], wg_0r1[22:22]);
OR2 I216 (comp0_0[23:23], wg_0r0[23:23], wg_0r1[23:23]);
OR2 I217 (comp0_0[24:24], wg_0r0[24:24], wg_0r1[24:24]);
OR2 I218 (comp0_0[25:25], wg_0r0[25:25], wg_0r1[25:25]);
OR2 I219 (comp0_0[26:26], wg_0r0[26:26], wg_0r1[26:26]);
OR2 I220 (comp0_0[27:27], wg_0r0[27:27], wg_0r1[27:27]);
OR2 I221 (comp0_0[28:28], wg_0r0[28:28], wg_0r1[28:28]);
OR2 I222 (comp0_0[29:29], wg_0r0[29:29], wg_0r1[29:29]);
OR2 I223 (comp0_0[30:30], wg_0r0[30:30], wg_0r1[30:30]);
OR2 I224 (comp0_0[31:31], wg_0r0[31:31], wg_0r1[31:31]);
C3 I225 (simp2381_0[0:0], comp0_0[0:0], comp0_0[1:1], comp0_0[2:2]);
C3 I226 (simp2381_0[1:1], comp0_0[3:3], comp0_0[4:4], comp0_0[5:5]);
C3 I227 (simp2381_0[2:2], comp0_0[6:6], comp0_0[7:7], comp0_0[8:8]);
C3 I228 (simp2381_0[3:3], comp0_0[9:9], comp0_0[10:10], comp0_0[11:11]);
C3 I229 (simp2381_0[4:4], comp0_0[12:12], comp0_0[13:13], comp0_0[14:14]);
C3 I230 (simp2381_0[5:5], comp0_0[15:15], comp0_0[16:16], comp0_0[17:17]);
C3 I231 (simp2381_0[6:6], comp0_0[18:18], comp0_0[19:19], comp0_0[20:20]);
C3 I232 (simp2381_0[7:7], comp0_0[21:21], comp0_0[22:22], comp0_0[23:23]);
C3 I233 (simp2381_0[8:8], comp0_0[24:24], comp0_0[25:25], comp0_0[26:26]);
C3 I234 (simp2381_0[9:9], comp0_0[27:27], comp0_0[28:28], comp0_0[29:29]);
C2 I235 (simp2381_0[10:10], comp0_0[30:30], comp0_0[31:31]);
C3 I236 (simp2382_0[0:0], simp2381_0[0:0], simp2381_0[1:1], simp2381_0[2:2]);
C3 I237 (simp2382_0[1:1], simp2381_0[3:3], simp2381_0[4:4], simp2381_0[5:5]);
C3 I238 (simp2382_0[2:2], simp2381_0[6:6], simp2381_0[7:7], simp2381_0[8:8]);
C2 I239 (simp2382_0[3:3], simp2381_0[9:9], simp2381_0[10:10]);
C3 I240 (simp2383_0[0:0], simp2382_0[0:0], simp2382_0[1:1], simp2382_0[2:2]);
BUFF I241 (simp2383_0[1:1], simp2382_0[3:3]);
C2 I242 (wc_0, simp2383_0[0:0], simp2383_0[1:1]);
AND2 I243 (conwgif_0[0:0], wg_0r0[0:0], conwig_0);
AND2 I244 (conwgif_0[1:1], wg_0r0[1:1], conwig_0);
AND2 I245 (conwgif_0[2:2], wg_0r0[2:2], conwig_0);
AND2 I246 (conwgif_0[3:3], wg_0r0[3:3], conwig_0);
AND2 I247 (conwgif_0[4:4], wg_0r0[4:4], conwig_0);
AND2 I248 (conwgif_0[5:5], wg_0r0[5:5], conwig_0);
AND2 I249 (conwgif_0[6:6], wg_0r0[6:6], conwig_0);
AND2 I250 (conwgif_0[7:7], wg_0r0[7:7], conwig_0);
AND2 I251 (conwgif_0[8:8], wg_0r0[8:8], conwig_0);
AND2 I252 (conwgif_0[9:9], wg_0r0[9:9], conwig_0);
AND2 I253 (conwgif_0[10:10], wg_0r0[10:10], conwig_0);
AND2 I254 (conwgif_0[11:11], wg_0r0[11:11], conwig_0);
AND2 I255 (conwgif_0[12:12], wg_0r0[12:12], conwig_0);
AND2 I256 (conwgif_0[13:13], wg_0r0[13:13], conwig_0);
AND2 I257 (conwgif_0[14:14], wg_0r0[14:14], conwig_0);
AND2 I258 (conwgif_0[15:15], wg_0r0[15:15], conwig_0);
AND2 I259 (conwgif_0[16:16], wg_0r0[16:16], conwig_0);
AND2 I260 (conwgif_0[17:17], wg_0r0[17:17], conwig_0);
AND2 I261 (conwgif_0[18:18], wg_0r0[18:18], conwig_0);
AND2 I262 (conwgif_0[19:19], wg_0r0[19:19], conwig_0);
AND2 I263 (conwgif_0[20:20], wg_0r0[20:20], conwig_0);
AND2 I264 (conwgif_0[21:21], wg_0r0[21:21], conwig_0);
AND2 I265 (conwgif_0[22:22], wg_0r0[22:22], conwig_0);
AND2 I266 (conwgif_0[23:23], wg_0r0[23:23], conwig_0);
AND2 I267 (conwgif_0[24:24], wg_0r0[24:24], conwig_0);
AND2 I268 (conwgif_0[25:25], wg_0r0[25:25], conwig_0);
AND2 I269 (conwgif_0[26:26], wg_0r0[26:26], conwig_0);
AND2 I270 (conwgif_0[27:27], wg_0r0[27:27], conwig_0);
AND2 I271 (conwgif_0[28:28], wg_0r0[28:28], conwig_0);
AND2 I272 (conwgif_0[29:29], wg_0r0[29:29], conwig_0);
AND2 I273 (conwgif_0[30:30], wg_0r0[30:30], conwig_0);
AND2 I274 (conwgif_0[31:31], wg_0r0[31:31], conwig_0);
AND2 I275 (conwgit_0[0:0], wg_0r1[0:0], conwig_0);
AND2 I276 (conwgit_0[1:1], wg_0r1[1:1], conwig_0);
AND2 I277 (conwgit_0[2:2], wg_0r1[2:2], conwig_0);
AND2 I278 (conwgit_0[3:3], wg_0r1[3:3], conwig_0);
AND2 I279 (conwgit_0[4:4], wg_0r1[4:4], conwig_0);
AND2 I280 (conwgit_0[5:5], wg_0r1[5:5], conwig_0);
AND2 I281 (conwgit_0[6:6], wg_0r1[6:6], conwig_0);
AND2 I282 (conwgit_0[7:7], wg_0r1[7:7], conwig_0);
AND2 I283 (conwgit_0[8:8], wg_0r1[8:8], conwig_0);
AND2 I284 (conwgit_0[9:9], wg_0r1[9:9], conwig_0);
AND2 I285 (conwgit_0[10:10], wg_0r1[10:10], conwig_0);
AND2 I286 (conwgit_0[11:11], wg_0r1[11:11], conwig_0);
AND2 I287 (conwgit_0[12:12], wg_0r1[12:12], conwig_0);
AND2 I288 (conwgit_0[13:13], wg_0r1[13:13], conwig_0);
AND2 I289 (conwgit_0[14:14], wg_0r1[14:14], conwig_0);
AND2 I290 (conwgit_0[15:15], wg_0r1[15:15], conwig_0);
AND2 I291 (conwgit_0[16:16], wg_0r1[16:16], conwig_0);
AND2 I292 (conwgit_0[17:17], wg_0r1[17:17], conwig_0);
AND2 I293 (conwgit_0[18:18], wg_0r1[18:18], conwig_0);
AND2 I294 (conwgit_0[19:19], wg_0r1[19:19], conwig_0);
AND2 I295 (conwgit_0[20:20], wg_0r1[20:20], conwig_0);
AND2 I296 (conwgit_0[21:21], wg_0r1[21:21], conwig_0);
AND2 I297 (conwgit_0[22:22], wg_0r1[22:22], conwig_0);
AND2 I298 (conwgit_0[23:23], wg_0r1[23:23], conwig_0);
AND2 I299 (conwgit_0[24:24], wg_0r1[24:24], conwig_0);
AND2 I300 (conwgit_0[25:25], wg_0r1[25:25], conwig_0);
AND2 I301 (conwgit_0[26:26], wg_0r1[26:26], conwig_0);
AND2 I302 (conwgit_0[27:27], wg_0r1[27:27], conwig_0);
AND2 I303 (conwgit_0[28:28], wg_0r1[28:28], conwig_0);
AND2 I304 (conwgit_0[29:29], wg_0r1[29:29], conwig_0);
AND2 I305 (conwgit_0[30:30], wg_0r1[30:30], conwig_0);
AND2 I306 (conwgit_0[31:31], wg_0r1[31:31], conwig_0);
BUFF I307 (conwigc_0, wc_0);
AO22 I308 (conwig_0, conwigc_0, conwigcanw_0, conwigc_0, conwig_0);
NOR2 I309 (conwigcanw_0, anyread_0, conwig_0);
BUFF I310 (wf_0[0:0], conwgif_0[0:0]);
BUFF I311 (wt_0[0:0], conwgit_0[0:0]);
BUFF I312 (wenr_0[0:0], wc_0);
BUFF I313 (wf_0[1:1], conwgif_0[1:1]);
BUFF I314 (wt_0[1:1], conwgit_0[1:1]);
BUFF I315 (wenr_0[1:1], wc_0);
BUFF I316 (wf_0[2:2], conwgif_0[2:2]);
BUFF I317 (wt_0[2:2], conwgit_0[2:2]);
BUFF I318 (wenr_0[2:2], wc_0);
BUFF I319 (wf_0[3:3], conwgif_0[3:3]);
BUFF I320 (wt_0[3:3], conwgit_0[3:3]);
BUFF I321 (wenr_0[3:3], wc_0);
BUFF I322 (wf_0[4:4], conwgif_0[4:4]);
BUFF I323 (wt_0[4:4], conwgit_0[4:4]);
BUFF I324 (wenr_0[4:4], wc_0);
BUFF I325 (wf_0[5:5], conwgif_0[5:5]);
BUFF I326 (wt_0[5:5], conwgit_0[5:5]);
BUFF I327 (wenr_0[5:5], wc_0);
BUFF I328 (wf_0[6:6], conwgif_0[6:6]);
BUFF I329 (wt_0[6:6], conwgit_0[6:6]);
BUFF I330 (wenr_0[6:6], wc_0);
BUFF I331 (wf_0[7:7], conwgif_0[7:7]);
BUFF I332 (wt_0[7:7], conwgit_0[7:7]);
BUFF I333 (wenr_0[7:7], wc_0);
BUFF I334 (wf_0[8:8], conwgif_0[8:8]);
BUFF I335 (wt_0[8:8], conwgit_0[8:8]);
BUFF I336 (wenr_0[8:8], wc_0);
BUFF I337 (wf_0[9:9], conwgif_0[9:9]);
BUFF I338 (wt_0[9:9], conwgit_0[9:9]);
BUFF I339 (wenr_0[9:9], wc_0);
BUFF I340 (wf_0[10:10], conwgif_0[10:10]);
BUFF I341 (wt_0[10:10], conwgit_0[10:10]);
BUFF I342 (wenr_0[10:10], wc_0);
BUFF I343 (wf_0[11:11], conwgif_0[11:11]);
BUFF I344 (wt_0[11:11], conwgit_0[11:11]);
BUFF I345 (wenr_0[11:11], wc_0);
BUFF I346 (wf_0[12:12], conwgif_0[12:12]);
BUFF I347 (wt_0[12:12], conwgit_0[12:12]);
BUFF I348 (wenr_0[12:12], wc_0);
BUFF I349 (wf_0[13:13], conwgif_0[13:13]);
BUFF I350 (wt_0[13:13], conwgit_0[13:13]);
BUFF I351 (wenr_0[13:13], wc_0);
BUFF I352 (wf_0[14:14], conwgif_0[14:14]);
BUFF I353 (wt_0[14:14], conwgit_0[14:14]);
BUFF I354 (wenr_0[14:14], wc_0);
BUFF I355 (wf_0[15:15], conwgif_0[15:15]);
BUFF I356 (wt_0[15:15], conwgit_0[15:15]);
BUFF I357 (wenr_0[15:15], wc_0);
BUFF I358 (wf_0[16:16], conwgif_0[16:16]);
BUFF I359 (wt_0[16:16], conwgit_0[16:16]);
BUFF I360 (wenr_0[16:16], wc_0);
BUFF I361 (wf_0[17:17], conwgif_0[17:17]);
BUFF I362 (wt_0[17:17], conwgit_0[17:17]);
BUFF I363 (wenr_0[17:17], wc_0);
BUFF I364 (wf_0[18:18], conwgif_0[18:18]);
BUFF I365 (wt_0[18:18], conwgit_0[18:18]);
BUFF I366 (wenr_0[18:18], wc_0);
BUFF I367 (wf_0[19:19], conwgif_0[19:19]);
BUFF I368 (wt_0[19:19], conwgit_0[19:19]);
BUFF I369 (wenr_0[19:19], wc_0);
BUFF I370 (wf_0[20:20], conwgif_0[20:20]);
BUFF I371 (wt_0[20:20], conwgit_0[20:20]);
BUFF I372 (wenr_0[20:20], wc_0);
BUFF I373 (wf_0[21:21], conwgif_0[21:21]);
BUFF I374 (wt_0[21:21], conwgit_0[21:21]);
BUFF I375 (wenr_0[21:21], wc_0);
BUFF I376 (wf_0[22:22], conwgif_0[22:22]);
BUFF I377 (wt_0[22:22], conwgit_0[22:22]);
BUFF I378 (wenr_0[22:22], wc_0);
BUFF I379 (wf_0[23:23], conwgif_0[23:23]);
BUFF I380 (wt_0[23:23], conwgit_0[23:23]);
BUFF I381 (wenr_0[23:23], wc_0);
BUFF I382 (wf_0[24:24], conwgif_0[24:24]);
BUFF I383 (wt_0[24:24], conwgit_0[24:24]);
BUFF I384 (wenr_0[24:24], wc_0);
BUFF I385 (wf_0[25:25], conwgif_0[25:25]);
BUFF I386 (wt_0[25:25], conwgit_0[25:25]);
BUFF I387 (wenr_0[25:25], wc_0);
BUFF I388 (wf_0[26:26], conwgif_0[26:26]);
BUFF I389 (wt_0[26:26], conwgit_0[26:26]);
BUFF I390 (wenr_0[26:26], wc_0);
BUFF I391 (wf_0[27:27], conwgif_0[27:27]);
BUFF I392 (wt_0[27:27], conwgit_0[27:27]);
BUFF I393 (wenr_0[27:27], wc_0);
BUFF I394 (wf_0[28:28], conwgif_0[28:28]);
BUFF I395 (wt_0[28:28], conwgit_0[28:28]);
BUFF I396 (wenr_0[28:28], wc_0);
BUFF I397 (wf_0[29:29], conwgif_0[29:29]);
BUFF I398 (wt_0[29:29], conwgit_0[29:29]);
BUFF I399 (wenr_0[29:29], wc_0);
BUFF I400 (wf_0[30:30], conwgif_0[30:30]);
BUFF I401 (wt_0[30:30], conwgit_0[30:30]);
BUFF I402 (wenr_0[30:30], wc_0);
BUFF I403 (wf_0[31:31], conwgif_0[31:31]);
BUFF I404 (wt_0[31:31], conwgit_0[31:31]);
BUFF I405 (wenr_0[31:31], wc_0);
C3 I406 (simp4071_0[0:0], conwig_0, wacks_0[0:0], wacks_0[1:1]);
C3 I407 (simp4071_0[1:1], wacks_0[2:2], wacks_0[3:3], wacks_0[4:4]);
C3 I408 (simp4071_0[2:2], wacks_0[5:5], wacks_0[6:6], wacks_0[7:7]);
C3 I409 (simp4071_0[3:3], wacks_0[8:8], wacks_0[9:9], wacks_0[10:10]);
C3 I410 (simp4071_0[4:4], wacks_0[11:11], wacks_0[12:12], wacks_0[13:13]);
C3 I411 (simp4071_0[5:5], wacks_0[14:14], wacks_0[15:15], wacks_0[16:16]);
C3 I412 (simp4071_0[6:6], wacks_0[17:17], wacks_0[18:18], wacks_0[19:19]);
C3 I413 (simp4071_0[7:7], wacks_0[20:20], wacks_0[21:21], wacks_0[22:22]);
C3 I414 (simp4071_0[8:8], wacks_0[23:23], wacks_0[24:24], wacks_0[25:25]);
C3 I415 (simp4071_0[9:9], wacks_0[26:26], wacks_0[27:27], wacks_0[28:28]);
C3 I416 (simp4071_0[10:10], wacks_0[29:29], wacks_0[30:30], wacks_0[31:31]);
C3 I417 (simp4072_0[0:0], simp4071_0[0:0], simp4071_0[1:1], simp4071_0[2:2]);
C3 I418 (simp4072_0[1:1], simp4071_0[3:3], simp4071_0[4:4], simp4071_0[5:5]);
C3 I419 (simp4072_0[2:2], simp4071_0[6:6], simp4071_0[7:7], simp4071_0[8:8]);
C2 I420 (simp4072_0[3:3], simp4071_0[9:9], simp4071_0[10:10]);
C3 I421 (simp4073_0[0:0], simp4072_0[0:0], simp4072_0[1:1], simp4072_0[2:2]);
BUFF I422 (simp4073_0[1:1], simp4072_0[3:3]);
C2 I423 (wd_0r, simp4073_0[0:0], simp4073_0[1:1]);
AND2 I424 (rd_0r0[0:0], df_0[0:0], rg_0r);
AND2 I425 (rd_0r0[1:1], df_0[1:1], rg_0r);
AND2 I426 (rd_0r0[2:2], df_0[2:2], rg_0r);
AND2 I427 (rd_0r0[3:3], df_0[3:3], rg_0r);
AND2 I428 (rd_0r0[4:4], df_0[4:4], rg_0r);
AND2 I429 (rd_0r0[5:5], df_0[5:5], rg_0r);
AND2 I430 (rd_0r0[6:6], df_0[6:6], rg_0r);
AND2 I431 (rd_0r0[7:7], df_0[7:7], rg_0r);
AND2 I432 (rd_0r0[8:8], df_0[8:8], rg_0r);
AND2 I433 (rd_0r0[9:9], df_0[9:9], rg_0r);
AND2 I434 (rd_0r0[10:10], df_0[10:10], rg_0r);
AND2 I435 (rd_0r0[11:11], df_0[11:11], rg_0r);
AND2 I436 (rd_0r0[12:12], df_0[12:12], rg_0r);
AND2 I437 (rd_0r0[13:13], df_0[13:13], rg_0r);
AND2 I438 (rd_0r0[14:14], df_0[14:14], rg_0r);
AND2 I439 (rd_0r0[15:15], df_0[15:15], rg_0r);
AND2 I440 (rd_0r0[16:16], df_0[16:16], rg_0r);
AND2 I441 (rd_0r0[17:17], df_0[17:17], rg_0r);
AND2 I442 (rd_0r0[18:18], df_0[18:18], rg_0r);
AND2 I443 (rd_0r0[19:19], df_0[19:19], rg_0r);
AND2 I444 (rd_0r0[20:20], df_0[20:20], rg_0r);
AND2 I445 (rd_0r0[21:21], df_0[21:21], rg_0r);
AND2 I446 (rd_0r0[22:22], df_0[22:22], rg_0r);
AND2 I447 (rd_0r0[23:23], df_0[23:23], rg_0r);
AND2 I448 (rd_0r0[24:24], df_0[24:24], rg_0r);
AND2 I449 (rd_0r0[25:25], df_0[25:25], rg_0r);
AND2 I450 (rd_0r0[26:26], df_0[26:26], rg_0r);
AND2 I451 (rd_0r0[27:27], df_0[27:27], rg_0r);
AND2 I452 (rd_0r0[28:28], df_0[28:28], rg_0r);
AND2 I453 (rd_0r0[29:29], df_0[29:29], rg_0r);
AND2 I454 (rd_0r0[30:30], df_0[30:30], rg_0r);
AND2 I455 (rd_0r0[31:31], df_0[31:31], rg_0r);
AND2 I456 (rd_1r0[0:0], df_0[0:0], rg_1r);
AND2 I457 (rd_1r0[1:1], df_0[1:1], rg_1r);
AND2 I458 (rd_1r0[2:2], df_0[2:2], rg_1r);
AND2 I459 (rd_1r0[3:3], df_0[3:3], rg_1r);
AND2 I460 (rd_1r0[4:4], df_0[4:4], rg_1r);
AND2 I461 (rd_1r0[5:5], df_0[5:5], rg_1r);
AND2 I462 (rd_1r0[6:6], df_0[6:6], rg_1r);
AND2 I463 (rd_1r0[7:7], df_0[7:7], rg_1r);
AND2 I464 (rd_1r0[8:8], df_0[8:8], rg_1r);
AND2 I465 (rd_1r0[9:9], df_0[9:9], rg_1r);
AND2 I466 (rd_1r0[10:10], df_0[10:10], rg_1r);
AND2 I467 (rd_1r0[11:11], df_0[11:11], rg_1r);
AND2 I468 (rd_1r0[12:12], df_0[12:12], rg_1r);
AND2 I469 (rd_1r0[13:13], df_0[13:13], rg_1r);
AND2 I470 (rd_1r0[14:14], df_0[14:14], rg_1r);
AND2 I471 (rd_1r0[15:15], df_0[15:15], rg_1r);
AND2 I472 (rd_1r0[16:16], df_0[16:16], rg_1r);
AND2 I473 (rd_1r0[17:17], df_0[17:17], rg_1r);
AND2 I474 (rd_1r0[18:18], df_0[18:18], rg_1r);
AND2 I475 (rd_1r0[19:19], df_0[19:19], rg_1r);
AND2 I476 (rd_1r0[20:20], df_0[20:20], rg_1r);
AND2 I477 (rd_1r0[21:21], df_0[21:21], rg_1r);
AND2 I478 (rd_1r0[22:22], df_0[22:22], rg_1r);
AND2 I479 (rd_1r0[23:23], df_0[23:23], rg_1r);
AND2 I480 (rd_1r0[24:24], df_0[24:24], rg_1r);
AND2 I481 (rd_1r0[25:25], df_0[25:25], rg_1r);
AND2 I482 (rd_1r0[26:26], df_0[26:26], rg_1r);
AND2 I483 (rd_1r0[27:27], df_0[27:27], rg_1r);
AND2 I484 (rd_2r0[0:0], df_0[4:4], rg_2r);
AND2 I485 (rd_2r0[1:1], df_0[5:5], rg_2r);
AND2 I486 (rd_2r0[2:2], df_0[6:6], rg_2r);
AND2 I487 (rd_2r0[3:3], df_0[7:7], rg_2r);
AND2 I488 (rd_2r0[4:4], df_0[8:8], rg_2r);
AND2 I489 (rd_2r0[5:5], df_0[9:9], rg_2r);
AND2 I490 (rd_2r0[6:6], df_0[10:10], rg_2r);
AND2 I491 (rd_2r0[7:7], df_0[11:11], rg_2r);
AND2 I492 (rd_2r0[8:8], df_0[12:12], rg_2r);
AND2 I493 (rd_2r0[9:9], df_0[13:13], rg_2r);
AND2 I494 (rd_2r0[10:10], df_0[14:14], rg_2r);
AND2 I495 (rd_2r0[11:11], df_0[15:15], rg_2r);
AND2 I496 (rd_2r0[12:12], df_0[16:16], rg_2r);
AND2 I497 (rd_2r0[13:13], df_0[17:17], rg_2r);
AND2 I498 (rd_2r0[14:14], df_0[18:18], rg_2r);
AND2 I499 (rd_2r0[15:15], df_0[19:19], rg_2r);
AND2 I500 (rd_2r0[16:16], df_0[20:20], rg_2r);
AND2 I501 (rd_2r0[17:17], df_0[21:21], rg_2r);
AND2 I502 (rd_2r0[18:18], df_0[22:22], rg_2r);
AND2 I503 (rd_2r0[19:19], df_0[23:23], rg_2r);
AND2 I504 (rd_2r0[20:20], df_0[24:24], rg_2r);
AND2 I505 (rd_2r0[21:21], df_0[25:25], rg_2r);
AND2 I506 (rd_2r0[22:22], df_0[26:26], rg_2r);
AND2 I507 (rd_2r0[23:23], df_0[27:27], rg_2r);
AND2 I508 (rd_2r0[24:24], df_0[28:28], rg_2r);
AND2 I509 (rd_2r0[25:25], df_0[29:29], rg_2r);
AND2 I510 (rd_2r0[26:26], df_0[30:30], rg_2r);
AND2 I511 (rd_2r0[27:27], df_0[31:31], rg_2r);
AND2 I512 (rd_3r0[0:0], df_0[4:4], rg_3r);
AND2 I513 (rd_3r0[1:1], df_0[5:5], rg_3r);
AND2 I514 (rd_3r0[2:2], df_0[6:6], rg_3r);
AND2 I515 (rd_3r0[3:3], df_0[7:7], rg_3r);
AND2 I516 (rd_3r0[4:4], df_0[8:8], rg_3r);
AND2 I517 (rd_3r0[5:5], df_0[9:9], rg_3r);
AND2 I518 (rd_3r0[6:6], df_0[10:10], rg_3r);
AND2 I519 (rd_3r0[7:7], df_0[11:11], rg_3r);
AND2 I520 (rd_3r0[8:8], df_0[12:12], rg_3r);
AND2 I521 (rd_3r0[9:9], df_0[13:13], rg_3r);
AND2 I522 (rd_3r0[10:10], df_0[14:14], rg_3r);
AND2 I523 (rd_3r0[11:11], df_0[15:15], rg_3r);
AND2 I524 (rd_3r0[12:12], df_0[16:16], rg_3r);
AND2 I525 (rd_3r0[13:13], df_0[17:17], rg_3r);
AND2 I526 (rd_3r0[14:14], df_0[18:18], rg_3r);
AND2 I527 (rd_3r0[15:15], df_0[19:19], rg_3r);
AND2 I528 (rd_3r0[16:16], df_0[20:20], rg_3r);
AND2 I529 (rd_3r0[17:17], df_0[21:21], rg_3r);
AND2 I530 (rd_3r0[18:18], df_0[22:22], rg_3r);
AND2 I531 (rd_3r0[19:19], df_0[23:23], rg_3r);
AND2 I532 (rd_3r0[20:20], df_0[24:24], rg_3r);
AND2 I533 (rd_3r0[21:21], df_0[25:25], rg_3r);
AND2 I534 (rd_3r0[22:22], df_0[26:26], rg_3r);
AND2 I535 (rd_3r0[23:23], df_0[27:27], rg_3r);
AND2 I536 (rd_3r0[24:24], df_0[28:28], rg_3r);
AND2 I537 (rd_3r0[25:25], df_0[29:29], rg_3r);
AND2 I538 (rd_3r0[26:26], df_0[30:30], rg_3r);
AND2 I539 (rd_3r0[27:27], df_0[31:31], rg_3r);
AND2 I540 (rd_0r1[0:0], dt_0[0:0], rg_0r);
AND2 I541 (rd_0r1[1:1], dt_0[1:1], rg_0r);
AND2 I542 (rd_0r1[2:2], dt_0[2:2], rg_0r);
AND2 I543 (rd_0r1[3:3], dt_0[3:3], rg_0r);
AND2 I544 (rd_0r1[4:4], dt_0[4:4], rg_0r);
AND2 I545 (rd_0r1[5:5], dt_0[5:5], rg_0r);
AND2 I546 (rd_0r1[6:6], dt_0[6:6], rg_0r);
AND2 I547 (rd_0r1[7:7], dt_0[7:7], rg_0r);
AND2 I548 (rd_0r1[8:8], dt_0[8:8], rg_0r);
AND2 I549 (rd_0r1[9:9], dt_0[9:9], rg_0r);
AND2 I550 (rd_0r1[10:10], dt_0[10:10], rg_0r);
AND2 I551 (rd_0r1[11:11], dt_0[11:11], rg_0r);
AND2 I552 (rd_0r1[12:12], dt_0[12:12], rg_0r);
AND2 I553 (rd_0r1[13:13], dt_0[13:13], rg_0r);
AND2 I554 (rd_0r1[14:14], dt_0[14:14], rg_0r);
AND2 I555 (rd_0r1[15:15], dt_0[15:15], rg_0r);
AND2 I556 (rd_0r1[16:16], dt_0[16:16], rg_0r);
AND2 I557 (rd_0r1[17:17], dt_0[17:17], rg_0r);
AND2 I558 (rd_0r1[18:18], dt_0[18:18], rg_0r);
AND2 I559 (rd_0r1[19:19], dt_0[19:19], rg_0r);
AND2 I560 (rd_0r1[20:20], dt_0[20:20], rg_0r);
AND2 I561 (rd_0r1[21:21], dt_0[21:21], rg_0r);
AND2 I562 (rd_0r1[22:22], dt_0[22:22], rg_0r);
AND2 I563 (rd_0r1[23:23], dt_0[23:23], rg_0r);
AND2 I564 (rd_0r1[24:24], dt_0[24:24], rg_0r);
AND2 I565 (rd_0r1[25:25], dt_0[25:25], rg_0r);
AND2 I566 (rd_0r1[26:26], dt_0[26:26], rg_0r);
AND2 I567 (rd_0r1[27:27], dt_0[27:27], rg_0r);
AND2 I568 (rd_0r1[28:28], dt_0[28:28], rg_0r);
AND2 I569 (rd_0r1[29:29], dt_0[29:29], rg_0r);
AND2 I570 (rd_0r1[30:30], dt_0[30:30], rg_0r);
AND2 I571 (rd_0r1[31:31], dt_0[31:31], rg_0r);
AND2 I572 (rd_1r1[0:0], dt_0[0:0], rg_1r);
AND2 I573 (rd_1r1[1:1], dt_0[1:1], rg_1r);
AND2 I574 (rd_1r1[2:2], dt_0[2:2], rg_1r);
AND2 I575 (rd_1r1[3:3], dt_0[3:3], rg_1r);
AND2 I576 (rd_1r1[4:4], dt_0[4:4], rg_1r);
AND2 I577 (rd_1r1[5:5], dt_0[5:5], rg_1r);
AND2 I578 (rd_1r1[6:6], dt_0[6:6], rg_1r);
AND2 I579 (rd_1r1[7:7], dt_0[7:7], rg_1r);
AND2 I580 (rd_1r1[8:8], dt_0[8:8], rg_1r);
AND2 I581 (rd_1r1[9:9], dt_0[9:9], rg_1r);
AND2 I582 (rd_1r1[10:10], dt_0[10:10], rg_1r);
AND2 I583 (rd_1r1[11:11], dt_0[11:11], rg_1r);
AND2 I584 (rd_1r1[12:12], dt_0[12:12], rg_1r);
AND2 I585 (rd_1r1[13:13], dt_0[13:13], rg_1r);
AND2 I586 (rd_1r1[14:14], dt_0[14:14], rg_1r);
AND2 I587 (rd_1r1[15:15], dt_0[15:15], rg_1r);
AND2 I588 (rd_1r1[16:16], dt_0[16:16], rg_1r);
AND2 I589 (rd_1r1[17:17], dt_0[17:17], rg_1r);
AND2 I590 (rd_1r1[18:18], dt_0[18:18], rg_1r);
AND2 I591 (rd_1r1[19:19], dt_0[19:19], rg_1r);
AND2 I592 (rd_1r1[20:20], dt_0[20:20], rg_1r);
AND2 I593 (rd_1r1[21:21], dt_0[21:21], rg_1r);
AND2 I594 (rd_1r1[22:22], dt_0[22:22], rg_1r);
AND2 I595 (rd_1r1[23:23], dt_0[23:23], rg_1r);
AND2 I596 (rd_1r1[24:24], dt_0[24:24], rg_1r);
AND2 I597 (rd_1r1[25:25], dt_0[25:25], rg_1r);
AND2 I598 (rd_1r1[26:26], dt_0[26:26], rg_1r);
AND2 I599 (rd_1r1[27:27], dt_0[27:27], rg_1r);
AND2 I600 (rd_2r1[0:0], dt_0[4:4], rg_2r);
AND2 I601 (rd_2r1[1:1], dt_0[5:5], rg_2r);
AND2 I602 (rd_2r1[2:2], dt_0[6:6], rg_2r);
AND2 I603 (rd_2r1[3:3], dt_0[7:7], rg_2r);
AND2 I604 (rd_2r1[4:4], dt_0[8:8], rg_2r);
AND2 I605 (rd_2r1[5:5], dt_0[9:9], rg_2r);
AND2 I606 (rd_2r1[6:6], dt_0[10:10], rg_2r);
AND2 I607 (rd_2r1[7:7], dt_0[11:11], rg_2r);
AND2 I608 (rd_2r1[8:8], dt_0[12:12], rg_2r);
AND2 I609 (rd_2r1[9:9], dt_0[13:13], rg_2r);
AND2 I610 (rd_2r1[10:10], dt_0[14:14], rg_2r);
AND2 I611 (rd_2r1[11:11], dt_0[15:15], rg_2r);
AND2 I612 (rd_2r1[12:12], dt_0[16:16], rg_2r);
AND2 I613 (rd_2r1[13:13], dt_0[17:17], rg_2r);
AND2 I614 (rd_2r1[14:14], dt_0[18:18], rg_2r);
AND2 I615 (rd_2r1[15:15], dt_0[19:19], rg_2r);
AND2 I616 (rd_2r1[16:16], dt_0[20:20], rg_2r);
AND2 I617 (rd_2r1[17:17], dt_0[21:21], rg_2r);
AND2 I618 (rd_2r1[18:18], dt_0[22:22], rg_2r);
AND2 I619 (rd_2r1[19:19], dt_0[23:23], rg_2r);
AND2 I620 (rd_2r1[20:20], dt_0[24:24], rg_2r);
AND2 I621 (rd_2r1[21:21], dt_0[25:25], rg_2r);
AND2 I622 (rd_2r1[22:22], dt_0[26:26], rg_2r);
AND2 I623 (rd_2r1[23:23], dt_0[27:27], rg_2r);
AND2 I624 (rd_2r1[24:24], dt_0[28:28], rg_2r);
AND2 I625 (rd_2r1[25:25], dt_0[29:29], rg_2r);
AND2 I626 (rd_2r1[26:26], dt_0[30:30], rg_2r);
AND2 I627 (rd_2r1[27:27], dt_0[31:31], rg_2r);
AND2 I628 (rd_3r1[0:0], dt_0[4:4], rg_3r);
AND2 I629 (rd_3r1[1:1], dt_0[5:5], rg_3r);
AND2 I630 (rd_3r1[2:2], dt_0[6:6], rg_3r);
AND2 I631 (rd_3r1[3:3], dt_0[7:7], rg_3r);
AND2 I632 (rd_3r1[4:4], dt_0[8:8], rg_3r);
AND2 I633 (rd_3r1[5:5], dt_0[9:9], rg_3r);
AND2 I634 (rd_3r1[6:6], dt_0[10:10], rg_3r);
AND2 I635 (rd_3r1[7:7], dt_0[11:11], rg_3r);
AND2 I636 (rd_3r1[8:8], dt_0[12:12], rg_3r);
AND2 I637 (rd_3r1[9:9], dt_0[13:13], rg_3r);
AND2 I638 (rd_3r1[10:10], dt_0[14:14], rg_3r);
AND2 I639 (rd_3r1[11:11], dt_0[15:15], rg_3r);
AND2 I640 (rd_3r1[12:12], dt_0[16:16], rg_3r);
AND2 I641 (rd_3r1[13:13], dt_0[17:17], rg_3r);
AND2 I642 (rd_3r1[14:14], dt_0[18:18], rg_3r);
AND2 I643 (rd_3r1[15:15], dt_0[19:19], rg_3r);
AND2 I644 (rd_3r1[16:16], dt_0[20:20], rg_3r);
AND2 I645 (rd_3r1[17:17], dt_0[21:21], rg_3r);
AND2 I646 (rd_3r1[18:18], dt_0[22:22], rg_3r);
AND2 I647 (rd_3r1[19:19], dt_0[23:23], rg_3r);
AND2 I648 (rd_3r1[20:20], dt_0[24:24], rg_3r);
AND2 I649 (rd_3r1[21:21], dt_0[25:25], rg_3r);
AND2 I650 (rd_3r1[22:22], dt_0[26:26], rg_3r);
AND2 I651 (rd_3r1[23:23], dt_0[27:27], rg_3r);
AND2 I652 (rd_3r1[24:24], dt_0[28:28], rg_3r);
AND2 I653 (rd_3r1[25:25], dt_0[29:29], rg_3r);
AND2 I654 (rd_3r1[26:26], dt_0[30:30], rg_3r);
AND2 I655 (rd_3r1[27:27], dt_0[31:31], rg_3r);
NOR3 I656 (simp6401_0[0:0], rg_0r, rg_1r, rg_2r);
NOR3 I657 (simp6401_0[1:1], rg_3r, rg_0a, rg_1a);
NOR2 I658 (simp6401_0[2:2], rg_2a, rg_3a);
NAND3 I659 (anyread_0, simp6401_0[0:0], simp6401_0[1:1], simp6401_0[2:2]);
BUFF I660 (wg_0a, wd_0a);
BUFF I661 (rg_0a, rd_0a);
BUFF I662 (rg_1a, rd_1a);
BUFF I663 (rg_2a, rd_2a);
BUFF I664 (rg_3a, rd_3a);
endmodule
// tko24m32_1nm8b0_2apt1o0w8bi0w24b TeakO [
// (1,TeakOConstant 8 0),
// (2,TeakOAppend 1 [(1,0+:8),(0,0+:24)])] [One 24,One 32]
module tko24m32_1nm8b0_2apt1o0w8bi0w24b (i_0r0, i_0r1, i_0a, o_0r0, o_0r1, o_0a, reset);
input [23:0] i_0r0;
input [23:0] i_0r1;
output i_0a;
output [31:0] o_0r0;
output [31:0] o_0r1;
input o_0a;
input reset;
wire go_0;
wire [23:0] gocomp_0;
wire [7:0] simp261_0;
wire [2:0] simp262_0;
wire [7:0] termf_1;
wire [7:0] termt_1;
OR2 I0 (gocomp_0[0:0], i_0r0[0:0], i_0r1[0:0]);
OR2 I1 (gocomp_0[1:1], i_0r0[1:1], i_0r1[1:1]);
OR2 I2 (gocomp_0[2:2], i_0r0[2:2], i_0r1[2:2]);
OR2 I3 (gocomp_0[3:3], i_0r0[3:3], i_0r1[3:3]);
OR2 I4 (gocomp_0[4:4], i_0r0[4:4], i_0r1[4:4]);
OR2 I5 (gocomp_0[5:5], i_0r0[5:5], i_0r1[5:5]);
OR2 I6 (gocomp_0[6:6], i_0r0[6:6], i_0r1[6:6]);
OR2 I7 (gocomp_0[7:7], i_0r0[7:7], i_0r1[7:7]);
OR2 I8 (gocomp_0[8:8], i_0r0[8:8], i_0r1[8:8]);
OR2 I9 (gocomp_0[9:9], i_0r0[9:9], i_0r1[9:9]);
OR2 I10 (gocomp_0[10:10], i_0r0[10:10], i_0r1[10:10]);
OR2 I11 (gocomp_0[11:11], i_0r0[11:11], i_0r1[11:11]);
OR2 I12 (gocomp_0[12:12], i_0r0[12:12], i_0r1[12:12]);
OR2 I13 (gocomp_0[13:13], i_0r0[13:13], i_0r1[13:13]);
OR2 I14 (gocomp_0[14:14], i_0r0[14:14], i_0r1[14:14]);
OR2 I15 (gocomp_0[15:15], i_0r0[15:15], i_0r1[15:15]);
OR2 I16 (gocomp_0[16:16], i_0r0[16:16], i_0r1[16:16]);
OR2 I17 (gocomp_0[17:17], i_0r0[17:17], i_0r1[17:17]);
OR2 I18 (gocomp_0[18:18], i_0r0[18:18], i_0r1[18:18]);
OR2 I19 (gocomp_0[19:19], i_0r0[19:19], i_0r1[19:19]);
OR2 I20 (gocomp_0[20:20], i_0r0[20:20], i_0r1[20:20]);
OR2 I21 (gocomp_0[21:21], i_0r0[21:21], i_0r1[21:21]);
OR2 I22 (gocomp_0[22:22], i_0r0[22:22], i_0r1[22:22]);
OR2 I23 (gocomp_0[23:23], i_0r0[23:23], i_0r1[23:23]);
C3 I24 (simp261_0[0:0], gocomp_0[0:0], gocomp_0[1:1], gocomp_0[2:2]);
C3 I25 (simp261_0[1:1], gocomp_0[3:3], gocomp_0[4:4], gocomp_0[5:5]);
C3 I26 (simp261_0[2:2], gocomp_0[6:6], gocomp_0[7:7], gocomp_0[8:8]);
C3 I27 (simp261_0[3:3], gocomp_0[9:9], gocomp_0[10:10], gocomp_0[11:11]);
C3 I28 (simp261_0[4:4], gocomp_0[12:12], gocomp_0[13:13], gocomp_0[14:14]);
C3 I29 (simp261_0[5:5], gocomp_0[15:15], gocomp_0[16:16], gocomp_0[17:17]);
C3 I30 (simp261_0[6:6], gocomp_0[18:18], gocomp_0[19:19], gocomp_0[20:20]);
C3 I31 (simp261_0[7:7], gocomp_0[21:21], gocomp_0[22:22], gocomp_0[23:23]);
C3 I32 (simp262_0[0:0], simp261_0[0:0], simp261_0[1:1], simp261_0[2:2]);
C3 I33 (simp262_0[1:1], simp261_0[3:3], simp261_0[4:4], simp261_0[5:5]);
C2 I34 (simp262_0[2:2], simp261_0[6:6], simp261_0[7:7]);
C3 I35 (go_0, simp262_0[0:0], simp262_0[1:1], simp262_0[2:2]);
BUFF I36 (termf_1[0:0], go_0);
BUFF I37 (termf_1[1:1], go_0);
BUFF I38 (termf_1[2:2], go_0);
BUFF I39 (termf_1[3:3], go_0);
BUFF I40 (termf_1[4:4], go_0);
BUFF I41 (termf_1[5:5], go_0);
BUFF I42 (termf_1[6:6], go_0);
BUFF I43 (termf_1[7:7], go_0);
GND I44 (termt_1[0:0]);
GND I45 (termt_1[1:1]);
GND I46 (termt_1[2:2]);
GND I47 (termt_1[3:3]);
GND I48 (termt_1[4:4]);
GND I49 (termt_1[5:5]);
GND I50 (termt_1[6:6]);
GND I51 (termt_1[7:7]);
BUFF I52 (o_0r0[0:0], termf_1[0:0]);
BUFF I53 (o_0r0[1:1], termf_1[1:1]);
BUFF I54 (o_0r0[2:2], termf_1[2:2]);
BUFF I55 (o_0r0[3:3], termf_1[3:3]);
BUFF I56 (o_0r0[4:4], termf_1[4:4]);
BUFF I57 (o_0r0[5:5], termf_1[5:5]);
BUFF I58 (o_0r0[6:6], termf_1[6:6]);
BUFF I59 (o_0r0[7:7], termf_1[7:7]);
BUFF I60 (o_0r0[8:8], i_0r0[0:0]);
BUFF I61 (o_0r0[9:9], i_0r0[1:1]);
BUFF I62 (o_0r0[10:10], i_0r0[2:2]);
BUFF I63 (o_0r0[11:11], i_0r0[3:3]);
BUFF I64 (o_0r0[12:12], i_0r0[4:4]);
BUFF I65 (o_0r0[13:13], i_0r0[5:5]);
BUFF I66 (o_0r0[14:14], i_0r0[6:6]);
BUFF I67 (o_0r0[15:15], i_0r0[7:7]);
BUFF I68 (o_0r0[16:16], i_0r0[8:8]);
BUFF I69 (o_0r0[17:17], i_0r0[9:9]);
BUFF I70 (o_0r0[18:18], i_0r0[10:10]);
BUFF I71 (o_0r0[19:19], i_0r0[11:11]);
BUFF I72 (o_0r0[20:20], i_0r0[12:12]);
BUFF I73 (o_0r0[21:21], i_0r0[13:13]);
BUFF I74 (o_0r0[22:22], i_0r0[14:14]);
BUFF I75 (o_0r0[23:23], i_0r0[15:15]);
BUFF I76 (o_0r0[24:24], i_0r0[16:16]);
BUFF I77 (o_0r0[25:25], i_0r0[17:17]);
BUFF I78 (o_0r0[26:26], i_0r0[18:18]);
BUFF I79 (o_0r0[27:27], i_0r0[19:19]);
BUFF I80 (o_0r0[28:28], i_0r0[20:20]);
BUFF I81 (o_0r0[29:29], i_0r0[21:21]);
BUFF I82 (o_0r0[30:30], i_0r0[22:22]);
BUFF I83 (o_0r0[31:31], i_0r0[23:23]);
BUFF I84 (o_0r1[0:0], termt_1[0:0]);
BUFF I85 (o_0r1[1:1], termt_1[1:1]);
BUFF I86 (o_0r1[2:2], termt_1[2:2]);
BUFF I87 (o_0r1[3:3], termt_1[3:3]);
BUFF I88 (o_0r1[4:4], termt_1[4:4]);
BUFF I89 (o_0r1[5:5], termt_1[5:5]);
BUFF I90 (o_0r1[6:6], termt_1[6:6]);
BUFF I91 (o_0r1[7:7], termt_1[7:7]);
BUFF I92 (o_0r1[8:8], i_0r1[0:0]);
BUFF I93 (o_0r1[9:9], i_0r1[1:1]);
BUFF I94 (o_0r1[10:10], i_0r1[2:2]);
BUFF I95 (o_0r1[11:11], i_0r1[3:3]);
BUFF I96 (o_0r1[12:12], i_0r1[4:4]);
BUFF I97 (o_0r1[13:13], i_0r1[5:5]);
BUFF I98 (o_0r1[14:14], i_0r1[6:6]);
BUFF I99 (o_0r1[15:15], i_0r1[7:7]);
BUFF I100 (o_0r1[16:16], i_0r1[8:8]);
BUFF I101 (o_0r1[17:17], i_0r1[9:9]);
BUFF I102 (o_0r1[18:18], i_0r1[10:10]);
BUFF I103 (o_0r1[19:19], i_0r1[11:11]);
BUFF I104 (o_0r1[20:20], i_0r1[12:12]);
BUFF I105 (o_0r1[21:21], i_0r1[13:13]);
BUFF I106 (o_0r1[22:22], i_0r1[14:14]);
BUFF I107 (o_0r1[23:23], i_0r1[15:15]);
BUFF I108 (o_0r1[24:24], i_0r1[16:16]);
BUFF I109 (o_0r1[25:25], i_0r1[17:17]);
BUFF I110 (o_0r1[26:26], i_0r1[18:18]);
BUFF I111 (o_0r1[27:27], i_0r1[19:19]);
BUFF I112 (o_0r1[28:28], i_0r1[20:20]);
BUFF I113 (o_0r1[29:29], i_0r1[21:21]);
BUFF I114 (o_0r1[30:30], i_0r1[22:22]);
BUFF I115 (o_0r1[31:31], i_0r1[23:23]);
BUFF I116 (i_0a, o_0a);
endmodule
// tko24m32_1nm8b0_2api0w24bt1o0w8b TeakO [
// (1,TeakOConstant 8 0),
// (2,TeakOAppend 1 [(0,0+:24),(1,0+:8)])] [One 24,One 32]
module tko24m32_1nm8b0_2api0w24bt1o0w8b (i_0r0, i_0r1, i_0a, o_0r0, o_0r1, o_0a, reset);
input [23:0] i_0r0;
input [23:0] i_0r1;
output i_0a;
output [31:0] o_0r0;
output [31:0] o_0r1;
input o_0a;
input reset;
wire go_0;
wire [23:0] gocomp_0;
wire [7:0] simp261_0;
wire [2:0] simp262_0;
wire [7:0] termf_1;
wire [7:0] termt_1;
OR2 I0 (gocomp_0[0:0], i_0r0[0:0], i_0r1[0:0]);
OR2 I1 (gocomp_0[1:1], i_0r0[1:1], i_0r1[1:1]);
OR2 I2 (gocomp_0[2:2], i_0r0[2:2], i_0r1[2:2]);
OR2 I3 (gocomp_0[3:3], i_0r0[3:3], i_0r1[3:3]);
OR2 I4 (gocomp_0[4:4], i_0r0[4:4], i_0r1[4:4]);
OR2 I5 (gocomp_0[5:5], i_0r0[5:5], i_0r1[5:5]);
OR2 I6 (gocomp_0[6:6], i_0r0[6:6], i_0r1[6:6]);
OR2 I7 (gocomp_0[7:7], i_0r0[7:7], i_0r1[7:7]);
OR2 I8 (gocomp_0[8:8], i_0r0[8:8], i_0r1[8:8]);
OR2 I9 (gocomp_0[9:9], i_0r0[9:9], i_0r1[9:9]);
OR2 I10 (gocomp_0[10:10], i_0r0[10:10], i_0r1[10:10]);
OR2 I11 (gocomp_0[11:11], i_0r0[11:11], i_0r1[11:11]);
OR2 I12 (gocomp_0[12:12], i_0r0[12:12], i_0r1[12:12]);
OR2 I13 (gocomp_0[13:13], i_0r0[13:13], i_0r1[13:13]);
OR2 I14 (gocomp_0[14:14], i_0r0[14:14], i_0r1[14:14]);
OR2 I15 (gocomp_0[15:15], i_0r0[15:15], i_0r1[15:15]);
OR2 I16 (gocomp_0[16:16], i_0r0[16:16], i_0r1[16:16]);
OR2 I17 (gocomp_0[17:17], i_0r0[17:17], i_0r1[17:17]);
OR2 I18 (gocomp_0[18:18], i_0r0[18:18], i_0r1[18:18]);
OR2 I19 (gocomp_0[19:19], i_0r0[19:19], i_0r1[19:19]);
OR2 I20 (gocomp_0[20:20], i_0r0[20:20], i_0r1[20:20]);
OR2 I21 (gocomp_0[21:21], i_0r0[21:21], i_0r1[21:21]);
OR2 I22 (gocomp_0[22:22], i_0r0[22:22], i_0r1[22:22]);
OR2 I23 (gocomp_0[23:23], i_0r0[23:23], i_0r1[23:23]);
C3 I24 (simp261_0[0:0], gocomp_0[0:0], gocomp_0[1:1], gocomp_0[2:2]);
C3 I25 (simp261_0[1:1], gocomp_0[3:3], gocomp_0[4:4], gocomp_0[5:5]);
C3 I26 (simp261_0[2:2], gocomp_0[6:6], gocomp_0[7:7], gocomp_0[8:8]);
C3 I27 (simp261_0[3:3], gocomp_0[9:9], gocomp_0[10:10], gocomp_0[11:11]);
C3 I28 (simp261_0[4:4], gocomp_0[12:12], gocomp_0[13:13], gocomp_0[14:14]);
C3 I29 (simp261_0[5:5], gocomp_0[15:15], gocomp_0[16:16], gocomp_0[17:17]);
C3 I30 (simp261_0[6:6], gocomp_0[18:18], gocomp_0[19:19], gocomp_0[20:20]);
C3 I31 (simp261_0[7:7], gocomp_0[21:21], gocomp_0[22:22], gocomp_0[23:23]);
C3 I32 (simp262_0[0:0], simp261_0[0:0], simp261_0[1:1], simp261_0[2:2]);
C3 I33 (simp262_0[1:1], simp261_0[3:3], simp261_0[4:4], simp261_0[5:5]);
C2 I34 (simp262_0[2:2], simp261_0[6:6], simp261_0[7:7]);
C3 I35 (go_0, simp262_0[0:0], simp262_0[1:1], simp262_0[2:2]);
BUFF I36 (termf_1[0:0], go_0);
BUFF I37 (termf_1[1:1], go_0);
BUFF I38 (termf_1[2:2], go_0);
BUFF I39 (termf_1[3:3], go_0);
BUFF I40 (termf_1[4:4], go_0);
BUFF I41 (termf_1[5:5], go_0);
BUFF I42 (termf_1[6:6], go_0);
BUFF I43 (termf_1[7:7], go_0);
GND I44 (termt_1[0:0]);
GND I45 (termt_1[1:1]);
GND I46 (termt_1[2:2]);
GND I47 (termt_1[3:3]);
GND I48 (termt_1[4:4]);
GND I49 (termt_1[5:5]);
GND I50 (termt_1[6:6]);
GND I51 (termt_1[7:7]);
BUFF I52 (o_0r0[0:0], i_0r0[0:0]);
BUFF I53 (o_0r0[1:1], i_0r0[1:1]);
BUFF I54 (o_0r0[2:2], i_0r0[2:2]);
BUFF I55 (o_0r0[3:3], i_0r0[3:3]);
BUFF I56 (o_0r0[4:4], i_0r0[4:4]);
BUFF I57 (o_0r0[5:5], i_0r0[5:5]);
BUFF I58 (o_0r0[6:6], i_0r0[6:6]);
BUFF I59 (o_0r0[7:7], i_0r0[7:7]);
BUFF I60 (o_0r0[8:8], i_0r0[8:8]);
BUFF I61 (o_0r0[9:9], i_0r0[9:9]);
BUFF I62 (o_0r0[10:10], i_0r0[10:10]);
BUFF I63 (o_0r0[11:11], i_0r0[11:11]);
BUFF I64 (o_0r0[12:12], i_0r0[12:12]);
BUFF I65 (o_0r0[13:13], i_0r0[13:13]);
BUFF I66 (o_0r0[14:14], i_0r0[14:14]);
BUFF I67 (o_0r0[15:15], i_0r0[15:15]);
BUFF I68 (o_0r0[16:16], i_0r0[16:16]);
BUFF I69 (o_0r0[17:17], i_0r0[17:17]);
BUFF I70 (o_0r0[18:18], i_0r0[18:18]);
BUFF I71 (o_0r0[19:19], i_0r0[19:19]);
BUFF I72 (o_0r0[20:20], i_0r0[20:20]);
BUFF I73 (o_0r0[21:21], i_0r0[21:21]);
BUFF I74 (o_0r0[22:22], i_0r0[22:22]);
BUFF I75 (o_0r0[23:23], i_0r0[23:23]);
BUFF I76 (o_0r0[24:24], termf_1[0:0]);
BUFF I77 (o_0r0[25:25], termf_1[1:1]);
BUFF I78 (o_0r0[26:26], termf_1[2:2]);
BUFF I79 (o_0r0[27:27], termf_1[3:3]);
BUFF I80 (o_0r0[28:28], termf_1[4:4]);
BUFF I81 (o_0r0[29:29], termf_1[5:5]);
BUFF I82 (o_0r0[30:30], termf_1[6:6]);
BUFF I83 (o_0r0[31:31], termf_1[7:7]);
BUFF I84 (o_0r1[0:0], i_0r1[0:0]);
BUFF I85 (o_0r1[1:1], i_0r1[1:1]);
BUFF I86 (o_0r1[2:2], i_0r1[2:2]);
BUFF I87 (o_0r1[3:3], i_0r1[3:3]);
BUFF I88 (o_0r1[4:4], i_0r1[4:4]);
BUFF I89 (o_0r1[5:5], i_0r1[5:5]);
BUFF I90 (o_0r1[6:6], i_0r1[6:6]);
BUFF I91 (o_0r1[7:7], i_0r1[7:7]);
BUFF I92 (o_0r1[8:8], i_0r1[8:8]);
BUFF I93 (o_0r1[9:9], i_0r1[9:9]);
BUFF I94 (o_0r1[10:10], i_0r1[10:10]);
BUFF I95 (o_0r1[11:11], i_0r1[11:11]);
BUFF I96 (o_0r1[12:12], i_0r1[12:12]);
BUFF I97 (o_0r1[13:13], i_0r1[13:13]);
BUFF I98 (o_0r1[14:14], i_0r1[14:14]);
BUFF I99 (o_0r1[15:15], i_0r1[15:15]);
BUFF I100 (o_0r1[16:16], i_0r1[16:16]);
BUFF I101 (o_0r1[17:17], i_0r1[17:17]);
BUFF I102 (o_0r1[18:18], i_0r1[18:18]);
BUFF I103 (o_0r1[19:19], i_0r1[19:19]);
BUFF I104 (o_0r1[20:20], i_0r1[20:20]);
BUFF I105 (o_0r1[21:21], i_0r1[21:21]);
BUFF I106 (o_0r1[22:22], i_0r1[22:22]);
BUFF I107 (o_0r1[23:23], i_0r1[23:23]);
BUFF I108 (o_0r1[24:24], termt_1[0:0]);
BUFF I109 (o_0r1[25:25], termt_1[1:1]);
BUFF I110 (o_0r1[26:26], termt_1[2:2]);
BUFF I111 (o_0r1[27:27], termt_1[3:3]);
BUFF I112 (o_0r1[28:28], termt_1[4:4]);
BUFF I113 (o_0r1[29:29], termt_1[5:5]);
BUFF I114 (o_0r1[30:30], termt_1[6:6]);
BUFF I115 (o_0r1[31:31], termt_1[7:7]);
BUFF I116 (i_0a, o_0a);
endmodule
// tko24m32_1nm8bff_2api0w24bt1o0w8b TeakO [
// (1,TeakOConstant 8 255),
// (2,TeakOAppend 1 [(0,0+:24),(1,0+:8)])] [One 24,One 32]
module tko24m32_1nm8bff_2api0w24bt1o0w8b (i_0r0, i_0r1, i_0a, o_0r0, o_0r1, o_0a, reset);
input [23:0] i_0r0;
input [23:0] i_0r1;
output i_0a;
output [31:0] o_0r0;
output [31:0] o_0r1;
input o_0a;
input reset;
wire go_0;
wire [23:0] gocomp_0;
wire [7:0] simp261_0;
wire [2:0] simp262_0;
wire [7:0] termf_1;
wire [7:0] termt_1;
OR2 I0 (gocomp_0[0:0], i_0r0[0:0], i_0r1[0:0]);
OR2 I1 (gocomp_0[1:1], i_0r0[1:1], i_0r1[1:1]);
OR2 I2 (gocomp_0[2:2], i_0r0[2:2], i_0r1[2:2]);
OR2 I3 (gocomp_0[3:3], i_0r0[3:3], i_0r1[3:3]);
OR2 I4 (gocomp_0[4:4], i_0r0[4:4], i_0r1[4:4]);
OR2 I5 (gocomp_0[5:5], i_0r0[5:5], i_0r1[5:5]);
OR2 I6 (gocomp_0[6:6], i_0r0[6:6], i_0r1[6:6]);
OR2 I7 (gocomp_0[7:7], i_0r0[7:7], i_0r1[7:7]);
OR2 I8 (gocomp_0[8:8], i_0r0[8:8], i_0r1[8:8]);
OR2 I9 (gocomp_0[9:9], i_0r0[9:9], i_0r1[9:9]);
OR2 I10 (gocomp_0[10:10], i_0r0[10:10], i_0r1[10:10]);
OR2 I11 (gocomp_0[11:11], i_0r0[11:11], i_0r1[11:11]);
OR2 I12 (gocomp_0[12:12], i_0r0[12:12], i_0r1[12:12]);
OR2 I13 (gocomp_0[13:13], i_0r0[13:13], i_0r1[13:13]);
OR2 I14 (gocomp_0[14:14], i_0r0[14:14], i_0r1[14:14]);
OR2 I15 (gocomp_0[15:15], i_0r0[15:15], i_0r1[15:15]);
OR2 I16 (gocomp_0[16:16], i_0r0[16:16], i_0r1[16:16]);
OR2 I17 (gocomp_0[17:17], i_0r0[17:17], i_0r1[17:17]);
OR2 I18 (gocomp_0[18:18], i_0r0[18:18], i_0r1[18:18]);
OR2 I19 (gocomp_0[19:19], i_0r0[19:19], i_0r1[19:19]);
OR2 I20 (gocomp_0[20:20], i_0r0[20:20], i_0r1[20:20]);
OR2 I21 (gocomp_0[21:21], i_0r0[21:21], i_0r1[21:21]);
OR2 I22 (gocomp_0[22:22], i_0r0[22:22], i_0r1[22:22]);
OR2 I23 (gocomp_0[23:23], i_0r0[23:23], i_0r1[23:23]);
C3 I24 (simp261_0[0:0], gocomp_0[0:0], gocomp_0[1:1], gocomp_0[2:2]);
C3 I25 (simp261_0[1:1], gocomp_0[3:3], gocomp_0[4:4], gocomp_0[5:5]);
C3 I26 (simp261_0[2:2], gocomp_0[6:6], gocomp_0[7:7], gocomp_0[8:8]);
C3 I27 (simp261_0[3:3], gocomp_0[9:9], gocomp_0[10:10], gocomp_0[11:11]);
C3 I28 (simp261_0[4:4], gocomp_0[12:12], gocomp_0[13:13], gocomp_0[14:14]);
C3 I29 (simp261_0[5:5], gocomp_0[15:15], gocomp_0[16:16], gocomp_0[17:17]);
C3 I30 (simp261_0[6:6], gocomp_0[18:18], gocomp_0[19:19], gocomp_0[20:20]);
C3 I31 (simp261_0[7:7], gocomp_0[21:21], gocomp_0[22:22], gocomp_0[23:23]);
C3 I32 (simp262_0[0:0], simp261_0[0:0], simp261_0[1:1], simp261_0[2:2]);
C3 I33 (simp262_0[1:1], simp261_0[3:3], simp261_0[4:4], simp261_0[5:5]);
C2 I34 (simp262_0[2:2], simp261_0[6:6], simp261_0[7:7]);
C3 I35 (go_0, simp262_0[0:0], simp262_0[1:1], simp262_0[2:2]);
BUFF I36 (termt_1[0:0], go_0);
BUFF I37 (termt_1[1:1], go_0);
BUFF I38 (termt_1[2:2], go_0);
BUFF I39 (termt_1[3:3], go_0);
BUFF I40 (termt_1[4:4], go_0);
BUFF I41 (termt_1[5:5], go_0);
BUFF I42 (termt_1[6:6], go_0);
BUFF I43 (termt_1[7:7], go_0);
GND I44 (termf_1[0:0]);
GND I45 (termf_1[1:1]);
GND I46 (termf_1[2:2]);
GND I47 (termf_1[3:3]);
GND I48 (termf_1[4:4]);
GND I49 (termf_1[5:5]);
GND I50 (termf_1[6:6]);
GND I51 (termf_1[7:7]);
BUFF I52 (o_0r0[0:0], i_0r0[0:0]);
BUFF I53 (o_0r0[1:1], i_0r0[1:1]);
BUFF I54 (o_0r0[2:2], i_0r0[2:2]);
BUFF I55 (o_0r0[3:3], i_0r0[3:3]);
BUFF I56 (o_0r0[4:4], i_0r0[4:4]);
BUFF I57 (o_0r0[5:5], i_0r0[5:5]);
BUFF I58 (o_0r0[6:6], i_0r0[6:6]);
BUFF I59 (o_0r0[7:7], i_0r0[7:7]);
BUFF I60 (o_0r0[8:8], i_0r0[8:8]);
BUFF I61 (o_0r0[9:9], i_0r0[9:9]);
BUFF I62 (o_0r0[10:10], i_0r0[10:10]);
BUFF I63 (o_0r0[11:11], i_0r0[11:11]);
BUFF I64 (o_0r0[12:12], i_0r0[12:12]);
BUFF I65 (o_0r0[13:13], i_0r0[13:13]);
BUFF I66 (o_0r0[14:14], i_0r0[14:14]);
BUFF I67 (o_0r0[15:15], i_0r0[15:15]);
BUFF I68 (o_0r0[16:16], i_0r0[16:16]);
BUFF I69 (o_0r0[17:17], i_0r0[17:17]);
BUFF I70 (o_0r0[18:18], i_0r0[18:18]);
BUFF I71 (o_0r0[19:19], i_0r0[19:19]);
BUFF I72 (o_0r0[20:20], i_0r0[20:20]);
BUFF I73 (o_0r0[21:21], i_0r0[21:21]);
BUFF I74 (o_0r0[22:22], i_0r0[22:22]);
BUFF I75 (o_0r0[23:23], i_0r0[23:23]);
BUFF I76 (o_0r0[24:24], termf_1[0:0]);
BUFF I77 (o_0r0[25:25], termf_1[1:1]);
BUFF I78 (o_0r0[26:26], termf_1[2:2]);
BUFF I79 (o_0r0[27:27], termf_1[3:3]);
BUFF I80 (o_0r0[28:28], termf_1[4:4]);
BUFF I81 (o_0r0[29:29], termf_1[5:5]);
BUFF I82 (o_0r0[30:30], termf_1[6:6]);
BUFF I83 (o_0r0[31:31], termf_1[7:7]);
BUFF I84 (o_0r1[0:0], i_0r1[0:0]);
BUFF I85 (o_0r1[1:1], i_0r1[1:1]);
BUFF I86 (o_0r1[2:2], i_0r1[2:2]);
BUFF I87 (o_0r1[3:3], i_0r1[3:3]);
BUFF I88 (o_0r1[4:4], i_0r1[4:4]);
BUFF I89 (o_0r1[5:5], i_0r1[5:5]);
BUFF I90 (o_0r1[6:6], i_0r1[6:6]);
BUFF I91 (o_0r1[7:7], i_0r1[7:7]);
BUFF I92 (o_0r1[8:8], i_0r1[8:8]);
BUFF I93 (o_0r1[9:9], i_0r1[9:9]);
BUFF I94 (o_0r1[10:10], i_0r1[10:10]);
BUFF I95 (o_0r1[11:11], i_0r1[11:11]);
BUFF I96 (o_0r1[12:12], i_0r1[12:12]);
BUFF I97 (o_0r1[13:13], i_0r1[13:13]);
BUFF I98 (o_0r1[14:14], i_0r1[14:14]);
BUFF I99 (o_0r1[15:15], i_0r1[15:15]);
BUFF I100 (o_0r1[16:16], i_0r1[16:16]);
BUFF I101 (o_0r1[17:17], i_0r1[17:17]);
BUFF I102 (o_0r1[18:18], i_0r1[18:18]);
BUFF I103 (o_0r1[19:19], i_0r1[19:19]);
BUFF I104 (o_0r1[20:20], i_0r1[20:20]);
BUFF I105 (o_0r1[21:21], i_0r1[21:21]);
BUFF I106 (o_0r1[22:22], i_0r1[22:22]);
BUFF I107 (o_0r1[23:23], i_0r1[23:23]);
BUFF I108 (o_0r1[24:24], termt_1[0:0]);
BUFF I109 (o_0r1[25:25], termt_1[1:1]);
BUFF I110 (o_0r1[26:26], termt_1[2:2]);
BUFF I111 (o_0r1[27:27], termt_1[3:3]);
BUFF I112 (o_0r1[28:28], termt_1[4:4]);
BUFF I113 (o_0r1[29:29], termt_1[5:5]);
BUFF I114 (o_0r1[30:30], termt_1[6:6]);
BUFF I115 (o_0r1[31:31], termt_1[7:7]);
BUFF I116 (i_0a, o_0a);
endmodule
// tkvi32_wo0w32_ro0w32o0w24o8w24o8w24 TeakV "i" 32 [] [0] [0,0,8,8] [Many [32],Many [0],Many [0,0,0,0]
// ,Many [32,24,24,24]]
module tkvi32_wo0w32_ro0w32o0w24o8w24o8w24 (wg_0r0, wg_0r1, wg_0a, wd_0r, wd_0a, rg_0r, rg_0a, rg_1r, rg_1a, rg_2r, rg_2a, rg_3r, rg_3a, rd_0r0, rd_0r1, rd_0a, rd_1r0, rd_1r1, rd_1a, rd_2r0, rd_2r1, rd_2a, rd_3r0, rd_3r1, rd_3a, reset);
input [31:0] wg_0r0;
input [31:0] wg_0r1;
output wg_0a;
output wd_0r;
input wd_0a;
input rg_0r;
output rg_0a;
input rg_1r;
output rg_1a;
input rg_2r;
output rg_2a;
input rg_3r;
output rg_3a;
output [31:0] rd_0r0;
output [31:0] rd_0r1;
input rd_0a;
output [23:0] rd_1r0;
output [23:0] rd_1r1;
input rd_1a;
output [23:0] rd_2r0;
output [23:0] rd_2r1;
input rd_2a;
output [23:0] rd_3r0;
output [23:0] rd_3r1;
input rd_3a;
input reset;
wire [31:0] wf_0;
wire [31:0] wt_0;
wire [31:0] df_0;
wire [31:0] dt_0;
wire wc_0;
wire [31:0] wacks_0;
wire [31:0] wenr_0;
wire [31:0] wen_0;
wire anyread_0;
wire nreset_0;
wire [31:0] drlgf_0;
wire [31:0] drlgt_0;
wire [31:0] comp0_0;
wire [10:0] simp2381_0;
wire [3:0] simp2382_0;
wire [1:0] simp2383_0;
wire conwigc_0;
wire conwigcanw_0;
wire [31:0] conwgit_0;
wire [31:0] conwgif_0;
wire conwig_0;
wire [10:0] simp4071_0;
wire [3:0] simp4072_0;
wire [1:0] simp4073_0;
wire [2:0] simp6161_0;
INV I0 (nreset_0, reset);
AND2 I1 (wen_0[0:0], wenr_0[0:0], nreset_0);
AND2 I2 (wen_0[1:1], wenr_0[1:1], nreset_0);
AND2 I3 (wen_0[2:2], wenr_0[2:2], nreset_0);
AND2 I4 (wen_0[3:3], wenr_0[3:3], nreset_0);
AND2 I5 (wen_0[4:4], wenr_0[4:4], nreset_0);
AND2 I6 (wen_0[5:5], wenr_0[5:5], nreset_0);
AND2 I7 (wen_0[6:6], wenr_0[6:6], nreset_0);
AND2 I8 (wen_0[7:7], wenr_0[7:7], nreset_0);
AND2 I9 (wen_0[8:8], wenr_0[8:8], nreset_0);
AND2 I10 (wen_0[9:9], wenr_0[9:9], nreset_0);
AND2 I11 (wen_0[10:10], wenr_0[10:10], nreset_0);
AND2 I12 (wen_0[11:11], wenr_0[11:11], nreset_0);
AND2 I13 (wen_0[12:12], wenr_0[12:12], nreset_0);
AND2 I14 (wen_0[13:13], wenr_0[13:13], nreset_0);
AND2 I15 (wen_0[14:14], wenr_0[14:14], nreset_0);
AND2 I16 (wen_0[15:15], wenr_0[15:15], nreset_0);
AND2 I17 (wen_0[16:16], wenr_0[16:16], nreset_0);
AND2 I18 (wen_0[17:17], wenr_0[17:17], nreset_0);
AND2 I19 (wen_0[18:18], wenr_0[18:18], nreset_0);
AND2 I20 (wen_0[19:19], wenr_0[19:19], nreset_0);
AND2 I21 (wen_0[20:20], wenr_0[20:20], nreset_0);
AND2 I22 (wen_0[21:21], wenr_0[21:21], nreset_0);
AND2 I23 (wen_0[22:22], wenr_0[22:22], nreset_0);
AND2 I24 (wen_0[23:23], wenr_0[23:23], nreset_0);
AND2 I25 (wen_0[24:24], wenr_0[24:24], nreset_0);
AND2 I26 (wen_0[25:25], wenr_0[25:25], nreset_0);
AND2 I27 (wen_0[26:26], wenr_0[26:26], nreset_0);
AND2 I28 (wen_0[27:27], wenr_0[27:27], nreset_0);
AND2 I29 (wen_0[28:28], wenr_0[28:28], nreset_0);
AND2 I30 (wen_0[29:29], wenr_0[29:29], nreset_0);
AND2 I31 (wen_0[30:30], wenr_0[30:30], nreset_0);
AND2 I32 (wen_0[31:31], wenr_0[31:31], nreset_0);
AND2 I33 (drlgf_0[0:0], wf_0[0:0], wen_0[0:0]);
AND2 I34 (drlgf_0[1:1], wf_0[1:1], wen_0[1:1]);
AND2 I35 (drlgf_0[2:2], wf_0[2:2], wen_0[2:2]);
AND2 I36 (drlgf_0[3:3], wf_0[3:3], wen_0[3:3]);
AND2 I37 (drlgf_0[4:4], wf_0[4:4], wen_0[4:4]);
AND2 I38 (drlgf_0[5:5], wf_0[5:5], wen_0[5:5]);
AND2 I39 (drlgf_0[6:6], wf_0[6:6], wen_0[6:6]);
AND2 I40 (drlgf_0[7:7], wf_0[7:7], wen_0[7:7]);
AND2 I41 (drlgf_0[8:8], wf_0[8:8], wen_0[8:8]);
AND2 I42 (drlgf_0[9:9], wf_0[9:9], wen_0[9:9]);
AND2 I43 (drlgf_0[10:10], wf_0[10:10], wen_0[10:10]);
AND2 I44 (drlgf_0[11:11], wf_0[11:11], wen_0[11:11]);
AND2 I45 (drlgf_0[12:12], wf_0[12:12], wen_0[12:12]);
AND2 I46 (drlgf_0[13:13], wf_0[13:13], wen_0[13:13]);
AND2 I47 (drlgf_0[14:14], wf_0[14:14], wen_0[14:14]);
AND2 I48 (drlgf_0[15:15], wf_0[15:15], wen_0[15:15]);
AND2 I49 (drlgf_0[16:16], wf_0[16:16], wen_0[16:16]);
AND2 I50 (drlgf_0[17:17], wf_0[17:17], wen_0[17:17]);
AND2 I51 (drlgf_0[18:18], wf_0[18:18], wen_0[18:18]);
AND2 I52 (drlgf_0[19:19], wf_0[19:19], wen_0[19:19]);
AND2 I53 (drlgf_0[20:20], wf_0[20:20], wen_0[20:20]);
AND2 I54 (drlgf_0[21:21], wf_0[21:21], wen_0[21:21]);
AND2 I55 (drlgf_0[22:22], wf_0[22:22], wen_0[22:22]);
AND2 I56 (drlgf_0[23:23], wf_0[23:23], wen_0[23:23]);
AND2 I57 (drlgf_0[24:24], wf_0[24:24], wen_0[24:24]);
AND2 I58 (drlgf_0[25:25], wf_0[25:25], wen_0[25:25]);
AND2 I59 (drlgf_0[26:26], wf_0[26:26], wen_0[26:26]);
AND2 I60 (drlgf_0[27:27], wf_0[27:27], wen_0[27:27]);
AND2 I61 (drlgf_0[28:28], wf_0[28:28], wen_0[28:28]);
AND2 I62 (drlgf_0[29:29], wf_0[29:29], wen_0[29:29]);
AND2 I63 (drlgf_0[30:30], wf_0[30:30], wen_0[30:30]);
AND2 I64 (drlgf_0[31:31], wf_0[31:31], wen_0[31:31]);
AND2 I65 (drlgt_0[0:0], wt_0[0:0], wen_0[0:0]);
AND2 I66 (drlgt_0[1:1], wt_0[1:1], wen_0[1:1]);
AND2 I67 (drlgt_0[2:2], wt_0[2:2], wen_0[2:2]);
AND2 I68 (drlgt_0[3:3], wt_0[3:3], wen_0[3:3]);
AND2 I69 (drlgt_0[4:4], wt_0[4:4], wen_0[4:4]);
AND2 I70 (drlgt_0[5:5], wt_0[5:5], wen_0[5:5]);
AND2 I71 (drlgt_0[6:6], wt_0[6:6], wen_0[6:6]);
AND2 I72 (drlgt_0[7:7], wt_0[7:7], wen_0[7:7]);
AND2 I73 (drlgt_0[8:8], wt_0[8:8], wen_0[8:8]);
AND2 I74 (drlgt_0[9:9], wt_0[9:9], wen_0[9:9]);
AND2 I75 (drlgt_0[10:10], wt_0[10:10], wen_0[10:10]);
AND2 I76 (drlgt_0[11:11], wt_0[11:11], wen_0[11:11]);
AND2 I77 (drlgt_0[12:12], wt_0[12:12], wen_0[12:12]);
AND2 I78 (drlgt_0[13:13], wt_0[13:13], wen_0[13:13]);
AND2 I79 (drlgt_0[14:14], wt_0[14:14], wen_0[14:14]);
AND2 I80 (drlgt_0[15:15], wt_0[15:15], wen_0[15:15]);
AND2 I81 (drlgt_0[16:16], wt_0[16:16], wen_0[16:16]);
AND2 I82 (drlgt_0[17:17], wt_0[17:17], wen_0[17:17]);
AND2 I83 (drlgt_0[18:18], wt_0[18:18], wen_0[18:18]);
AND2 I84 (drlgt_0[19:19], wt_0[19:19], wen_0[19:19]);
AND2 I85 (drlgt_0[20:20], wt_0[20:20], wen_0[20:20]);
AND2 I86 (drlgt_0[21:21], wt_0[21:21], wen_0[21:21]);
AND2 I87 (drlgt_0[22:22], wt_0[22:22], wen_0[22:22]);
AND2 I88 (drlgt_0[23:23], wt_0[23:23], wen_0[23:23]);
AND2 I89 (drlgt_0[24:24], wt_0[24:24], wen_0[24:24]);
AND2 I90 (drlgt_0[25:25], wt_0[25:25], wen_0[25:25]);
AND2 I91 (drlgt_0[26:26], wt_0[26:26], wen_0[26:26]);
AND2 I92 (drlgt_0[27:27], wt_0[27:27], wen_0[27:27]);
AND2 I93 (drlgt_0[28:28], wt_0[28:28], wen_0[28:28]);
AND2 I94 (drlgt_0[29:29], wt_0[29:29], wen_0[29:29]);
AND2 I95 (drlgt_0[30:30], wt_0[30:30], wen_0[30:30]);
AND2 I96 (drlgt_0[31:31], wt_0[31:31], wen_0[31:31]);
NOR2 I97 (df_0[0:0], dt_0[0:0], drlgt_0[0:0]);
NOR2 I98 (df_0[1:1], dt_0[1:1], drlgt_0[1:1]);
NOR2 I99 (df_0[2:2], dt_0[2:2], drlgt_0[2:2]);
NOR2 I100 (df_0[3:3], dt_0[3:3], drlgt_0[3:3]);
NOR2 I101 (df_0[4:4], dt_0[4:4], drlgt_0[4:4]);
NOR2 I102 (df_0[5:5], dt_0[5:5], drlgt_0[5:5]);
NOR2 I103 (df_0[6:6], dt_0[6:6], drlgt_0[6:6]);
NOR2 I104 (df_0[7:7], dt_0[7:7], drlgt_0[7:7]);
NOR2 I105 (df_0[8:8], dt_0[8:8], drlgt_0[8:8]);
NOR2 I106 (df_0[9:9], dt_0[9:9], drlgt_0[9:9]);
NOR2 I107 (df_0[10:10], dt_0[10:10], drlgt_0[10:10]);
NOR2 I108 (df_0[11:11], dt_0[11:11], drlgt_0[11:11]);
NOR2 I109 (df_0[12:12], dt_0[12:12], drlgt_0[12:12]);
NOR2 I110 (df_0[13:13], dt_0[13:13], drlgt_0[13:13]);
NOR2 I111 (df_0[14:14], dt_0[14:14], drlgt_0[14:14]);
NOR2 I112 (df_0[15:15], dt_0[15:15], drlgt_0[15:15]);
NOR2 I113 (df_0[16:16], dt_0[16:16], drlgt_0[16:16]);
NOR2 I114 (df_0[17:17], dt_0[17:17], drlgt_0[17:17]);
NOR2 I115 (df_0[18:18], dt_0[18:18], drlgt_0[18:18]);
NOR2 I116 (df_0[19:19], dt_0[19:19], drlgt_0[19:19]);
NOR2 I117 (df_0[20:20], dt_0[20:20], drlgt_0[20:20]);
NOR2 I118 (df_0[21:21], dt_0[21:21], drlgt_0[21:21]);
NOR2 I119 (df_0[22:22], dt_0[22:22], drlgt_0[22:22]);
NOR2 I120 (df_0[23:23], dt_0[23:23], drlgt_0[23:23]);
NOR2 I121 (df_0[24:24], dt_0[24:24], drlgt_0[24:24]);
NOR2 I122 (df_0[25:25], dt_0[25:25], drlgt_0[25:25]);
NOR2 I123 (df_0[26:26], dt_0[26:26], drlgt_0[26:26]);
NOR2 I124 (df_0[27:27], dt_0[27:27], drlgt_0[27:27]);
NOR2 I125 (df_0[28:28], dt_0[28:28], drlgt_0[28:28]);
NOR2 I126 (df_0[29:29], dt_0[29:29], drlgt_0[29:29]);
NOR2 I127 (df_0[30:30], dt_0[30:30], drlgt_0[30:30]);
NOR2 I128 (df_0[31:31], dt_0[31:31], drlgt_0[31:31]);
NOR3 I129 (dt_0[0:0], df_0[0:0], drlgf_0[0:0], reset);
NOR3 I130 (dt_0[1:1], df_0[1:1], drlgf_0[1:1], reset);
NOR3 I131 (dt_0[2:2], df_0[2:2], drlgf_0[2:2], reset);
NOR3 I132 (dt_0[3:3], df_0[3:3], drlgf_0[3:3], reset);
NOR3 I133 (dt_0[4:4], df_0[4:4], drlgf_0[4:4], reset);
NOR3 I134 (dt_0[5:5], df_0[5:5], drlgf_0[5:5], reset);
NOR3 I135 (dt_0[6:6], df_0[6:6], drlgf_0[6:6], reset);
NOR3 I136 (dt_0[7:7], df_0[7:7], drlgf_0[7:7], reset);
NOR3 I137 (dt_0[8:8], df_0[8:8], drlgf_0[8:8], reset);
NOR3 I138 (dt_0[9:9], df_0[9:9], drlgf_0[9:9], reset);
NOR3 I139 (dt_0[10:10], df_0[10:10], drlgf_0[10:10], reset);
NOR3 I140 (dt_0[11:11], df_0[11:11], drlgf_0[11:11], reset);
NOR3 I141 (dt_0[12:12], df_0[12:12], drlgf_0[12:12], reset);
NOR3 I142 (dt_0[13:13], df_0[13:13], drlgf_0[13:13], reset);
NOR3 I143 (dt_0[14:14], df_0[14:14], drlgf_0[14:14], reset);
NOR3 I144 (dt_0[15:15], df_0[15:15], drlgf_0[15:15], reset);
NOR3 I145 (dt_0[16:16], df_0[16:16], drlgf_0[16:16], reset);
NOR3 I146 (dt_0[17:17], df_0[17:17], drlgf_0[17:17], reset);
NOR3 I147 (dt_0[18:18], df_0[18:18], drlgf_0[18:18], reset);
NOR3 I148 (dt_0[19:19], df_0[19:19], drlgf_0[19:19], reset);
NOR3 I149 (dt_0[20:20], df_0[20:20], drlgf_0[20:20], reset);
NOR3 I150 (dt_0[21:21], df_0[21:21], drlgf_0[21:21], reset);
NOR3 I151 (dt_0[22:22], df_0[22:22], drlgf_0[22:22], reset);
NOR3 I152 (dt_0[23:23], df_0[23:23], drlgf_0[23:23], reset);
NOR3 I153 (dt_0[24:24], df_0[24:24], drlgf_0[24:24], reset);
NOR3 I154 (dt_0[25:25], df_0[25:25], drlgf_0[25:25], reset);
NOR3 I155 (dt_0[26:26], df_0[26:26], drlgf_0[26:26], reset);
NOR3 I156 (dt_0[27:27], df_0[27:27], drlgf_0[27:27], reset);
NOR3 I157 (dt_0[28:28], df_0[28:28], drlgf_0[28:28], reset);
NOR3 I158 (dt_0[29:29], df_0[29:29], drlgf_0[29:29], reset);
NOR3 I159 (dt_0[30:30], df_0[30:30], drlgf_0[30:30], reset);
NOR3 I160 (dt_0[31:31], df_0[31:31], drlgf_0[31:31], reset);
AO22 I161 (wacks_0[0:0], drlgf_0[0:0], df_0[0:0], drlgt_0[0:0], dt_0[0:0]);
AO22 I162 (wacks_0[1:1], drlgf_0[1:1], df_0[1:1], drlgt_0[1:1], dt_0[1:1]);
AO22 I163 (wacks_0[2:2], drlgf_0[2:2], df_0[2:2], drlgt_0[2:2], dt_0[2:2]);
AO22 I164 (wacks_0[3:3], drlgf_0[3:3], df_0[3:3], drlgt_0[3:3], dt_0[3:3]);
AO22 I165 (wacks_0[4:4], drlgf_0[4:4], df_0[4:4], drlgt_0[4:4], dt_0[4:4]);
AO22 I166 (wacks_0[5:5], drlgf_0[5:5], df_0[5:5], drlgt_0[5:5], dt_0[5:5]);
AO22 I167 (wacks_0[6:6], drlgf_0[6:6], df_0[6:6], drlgt_0[6:6], dt_0[6:6]);
AO22 I168 (wacks_0[7:7], drlgf_0[7:7], df_0[7:7], drlgt_0[7:7], dt_0[7:7]);
AO22 I169 (wacks_0[8:8], drlgf_0[8:8], df_0[8:8], drlgt_0[8:8], dt_0[8:8]);
AO22 I170 (wacks_0[9:9], drlgf_0[9:9], df_0[9:9], drlgt_0[9:9], dt_0[9:9]);
AO22 I171 (wacks_0[10:10], drlgf_0[10:10], df_0[10:10], drlgt_0[10:10], dt_0[10:10]);
AO22 I172 (wacks_0[11:11], drlgf_0[11:11], df_0[11:11], drlgt_0[11:11], dt_0[11:11]);
AO22 I173 (wacks_0[12:12], drlgf_0[12:12], df_0[12:12], drlgt_0[12:12], dt_0[12:12]);
AO22 I174 (wacks_0[13:13], drlgf_0[13:13], df_0[13:13], drlgt_0[13:13], dt_0[13:13]);
AO22 I175 (wacks_0[14:14], drlgf_0[14:14], df_0[14:14], drlgt_0[14:14], dt_0[14:14]);
AO22 I176 (wacks_0[15:15], drlgf_0[15:15], df_0[15:15], drlgt_0[15:15], dt_0[15:15]);
AO22 I177 (wacks_0[16:16], drlgf_0[16:16], df_0[16:16], drlgt_0[16:16], dt_0[16:16]);
AO22 I178 (wacks_0[17:17], drlgf_0[17:17], df_0[17:17], drlgt_0[17:17], dt_0[17:17]);
AO22 I179 (wacks_0[18:18], drlgf_0[18:18], df_0[18:18], drlgt_0[18:18], dt_0[18:18]);
AO22 I180 (wacks_0[19:19], drlgf_0[19:19], df_0[19:19], drlgt_0[19:19], dt_0[19:19]);
AO22 I181 (wacks_0[20:20], drlgf_0[20:20], df_0[20:20], drlgt_0[20:20], dt_0[20:20]);
AO22 I182 (wacks_0[21:21], drlgf_0[21:21], df_0[21:21], drlgt_0[21:21], dt_0[21:21]);
AO22 I183 (wacks_0[22:22], drlgf_0[22:22], df_0[22:22], drlgt_0[22:22], dt_0[22:22]);
AO22 I184 (wacks_0[23:23], drlgf_0[23:23], df_0[23:23], drlgt_0[23:23], dt_0[23:23]);
AO22 I185 (wacks_0[24:24], drlgf_0[24:24], df_0[24:24], drlgt_0[24:24], dt_0[24:24]);
AO22 I186 (wacks_0[25:25], drlgf_0[25:25], df_0[25:25], drlgt_0[25:25], dt_0[25:25]);
AO22 I187 (wacks_0[26:26], drlgf_0[26:26], df_0[26:26], drlgt_0[26:26], dt_0[26:26]);
AO22 I188 (wacks_0[27:27], drlgf_0[27:27], df_0[27:27], drlgt_0[27:27], dt_0[27:27]);
AO22 I189 (wacks_0[28:28], drlgf_0[28:28], df_0[28:28], drlgt_0[28:28], dt_0[28:28]);
AO22 I190 (wacks_0[29:29], drlgf_0[29:29], df_0[29:29], drlgt_0[29:29], dt_0[29:29]);
AO22 I191 (wacks_0[30:30], drlgf_0[30:30], df_0[30:30], drlgt_0[30:30], dt_0[30:30]);
AO22 I192 (wacks_0[31:31], drlgf_0[31:31], df_0[31:31], drlgt_0[31:31], dt_0[31:31]);
OR2 I193 (comp0_0[0:0], wg_0r0[0:0], wg_0r1[0:0]);
OR2 I194 (comp0_0[1:1], wg_0r0[1:1], wg_0r1[1:1]);
OR2 I195 (comp0_0[2:2], wg_0r0[2:2], wg_0r1[2:2]);
OR2 I196 (comp0_0[3:3], wg_0r0[3:3], wg_0r1[3:3]);
OR2 I197 (comp0_0[4:4], wg_0r0[4:4], wg_0r1[4:4]);
OR2 I198 (comp0_0[5:5], wg_0r0[5:5], wg_0r1[5:5]);
OR2 I199 (comp0_0[6:6], wg_0r0[6:6], wg_0r1[6:6]);
OR2 I200 (comp0_0[7:7], wg_0r0[7:7], wg_0r1[7:7]);
OR2 I201 (comp0_0[8:8], wg_0r0[8:8], wg_0r1[8:8]);
OR2 I202 (comp0_0[9:9], wg_0r0[9:9], wg_0r1[9:9]);
OR2 I203 (comp0_0[10:10], wg_0r0[10:10], wg_0r1[10:10]);
OR2 I204 (comp0_0[11:11], wg_0r0[11:11], wg_0r1[11:11]);
OR2 I205 (comp0_0[12:12], wg_0r0[12:12], wg_0r1[12:12]);
OR2 I206 (comp0_0[13:13], wg_0r0[13:13], wg_0r1[13:13]);
OR2 I207 (comp0_0[14:14], wg_0r0[14:14], wg_0r1[14:14]);
OR2 I208 (comp0_0[15:15], wg_0r0[15:15], wg_0r1[15:15]);
OR2 I209 (comp0_0[16:16], wg_0r0[16:16], wg_0r1[16:16]);
OR2 I210 (comp0_0[17:17], wg_0r0[17:17], wg_0r1[17:17]);
OR2 I211 (comp0_0[18:18], wg_0r0[18:18], wg_0r1[18:18]);
OR2 I212 (comp0_0[19:19], wg_0r0[19:19], wg_0r1[19:19]);
OR2 I213 (comp0_0[20:20], wg_0r0[20:20], wg_0r1[20:20]);
OR2 I214 (comp0_0[21:21], wg_0r0[21:21], wg_0r1[21:21]);
OR2 I215 (comp0_0[22:22], wg_0r0[22:22], wg_0r1[22:22]);
OR2 I216 (comp0_0[23:23], wg_0r0[23:23], wg_0r1[23:23]);
OR2 I217 (comp0_0[24:24], wg_0r0[24:24], wg_0r1[24:24]);
OR2 I218 (comp0_0[25:25], wg_0r0[25:25], wg_0r1[25:25]);
OR2 I219 (comp0_0[26:26], wg_0r0[26:26], wg_0r1[26:26]);
OR2 I220 (comp0_0[27:27], wg_0r0[27:27], wg_0r1[27:27]);
OR2 I221 (comp0_0[28:28], wg_0r0[28:28], wg_0r1[28:28]);
OR2 I222 (comp0_0[29:29], wg_0r0[29:29], wg_0r1[29:29]);
OR2 I223 (comp0_0[30:30], wg_0r0[30:30], wg_0r1[30:30]);
OR2 I224 (comp0_0[31:31], wg_0r0[31:31], wg_0r1[31:31]);
C3 I225 (simp2381_0[0:0], comp0_0[0:0], comp0_0[1:1], comp0_0[2:2]);
C3 I226 (simp2381_0[1:1], comp0_0[3:3], comp0_0[4:4], comp0_0[5:5]);
C3 I227 (simp2381_0[2:2], comp0_0[6:6], comp0_0[7:7], comp0_0[8:8]);
C3 I228 (simp2381_0[3:3], comp0_0[9:9], comp0_0[10:10], comp0_0[11:11]);
C3 I229 (simp2381_0[4:4], comp0_0[12:12], comp0_0[13:13], comp0_0[14:14]);
C3 I230 (simp2381_0[5:5], comp0_0[15:15], comp0_0[16:16], comp0_0[17:17]);
C3 I231 (simp2381_0[6:6], comp0_0[18:18], comp0_0[19:19], comp0_0[20:20]);
C3 I232 (simp2381_0[7:7], comp0_0[21:21], comp0_0[22:22], comp0_0[23:23]);
C3 I233 (simp2381_0[8:8], comp0_0[24:24], comp0_0[25:25], comp0_0[26:26]);
C3 I234 (simp2381_0[9:9], comp0_0[27:27], comp0_0[28:28], comp0_0[29:29]);
C2 I235 (simp2381_0[10:10], comp0_0[30:30], comp0_0[31:31]);
C3 I236 (simp2382_0[0:0], simp2381_0[0:0], simp2381_0[1:1], simp2381_0[2:2]);
C3 I237 (simp2382_0[1:1], simp2381_0[3:3], simp2381_0[4:4], simp2381_0[5:5]);
C3 I238 (simp2382_0[2:2], simp2381_0[6:6], simp2381_0[7:7], simp2381_0[8:8]);
C2 I239 (simp2382_0[3:3], simp2381_0[9:9], simp2381_0[10:10]);
C3 I240 (simp2383_0[0:0], simp2382_0[0:0], simp2382_0[1:1], simp2382_0[2:2]);
BUFF I241 (simp2383_0[1:1], simp2382_0[3:3]);
C2 I242 (wc_0, simp2383_0[0:0], simp2383_0[1:1]);
AND2 I243 (conwgif_0[0:0], wg_0r0[0:0], conwig_0);
AND2 I244 (conwgif_0[1:1], wg_0r0[1:1], conwig_0);
AND2 I245 (conwgif_0[2:2], wg_0r0[2:2], conwig_0);
AND2 I246 (conwgif_0[3:3], wg_0r0[3:3], conwig_0);
AND2 I247 (conwgif_0[4:4], wg_0r0[4:4], conwig_0);
AND2 I248 (conwgif_0[5:5], wg_0r0[5:5], conwig_0);
AND2 I249 (conwgif_0[6:6], wg_0r0[6:6], conwig_0);
AND2 I250 (conwgif_0[7:7], wg_0r0[7:7], conwig_0);
AND2 I251 (conwgif_0[8:8], wg_0r0[8:8], conwig_0);
AND2 I252 (conwgif_0[9:9], wg_0r0[9:9], conwig_0);
AND2 I253 (conwgif_0[10:10], wg_0r0[10:10], conwig_0);
AND2 I254 (conwgif_0[11:11], wg_0r0[11:11], conwig_0);
AND2 I255 (conwgif_0[12:12], wg_0r0[12:12], conwig_0);
AND2 I256 (conwgif_0[13:13], wg_0r0[13:13], conwig_0);
AND2 I257 (conwgif_0[14:14], wg_0r0[14:14], conwig_0);
AND2 I258 (conwgif_0[15:15], wg_0r0[15:15], conwig_0);
AND2 I259 (conwgif_0[16:16], wg_0r0[16:16], conwig_0);
AND2 I260 (conwgif_0[17:17], wg_0r0[17:17], conwig_0);
AND2 I261 (conwgif_0[18:18], wg_0r0[18:18], conwig_0);
AND2 I262 (conwgif_0[19:19], wg_0r0[19:19], conwig_0);
AND2 I263 (conwgif_0[20:20], wg_0r0[20:20], conwig_0);
AND2 I264 (conwgif_0[21:21], wg_0r0[21:21], conwig_0);
AND2 I265 (conwgif_0[22:22], wg_0r0[22:22], conwig_0);
AND2 I266 (conwgif_0[23:23], wg_0r0[23:23], conwig_0);
AND2 I267 (conwgif_0[24:24], wg_0r0[24:24], conwig_0);
AND2 I268 (conwgif_0[25:25], wg_0r0[25:25], conwig_0);
AND2 I269 (conwgif_0[26:26], wg_0r0[26:26], conwig_0);
AND2 I270 (conwgif_0[27:27], wg_0r0[27:27], conwig_0);
AND2 I271 (conwgif_0[28:28], wg_0r0[28:28], conwig_0);
AND2 I272 (conwgif_0[29:29], wg_0r0[29:29], conwig_0);
AND2 I273 (conwgif_0[30:30], wg_0r0[30:30], conwig_0);
AND2 I274 (conwgif_0[31:31], wg_0r0[31:31], conwig_0);
AND2 I275 (conwgit_0[0:0], wg_0r1[0:0], conwig_0);
AND2 I276 (conwgit_0[1:1], wg_0r1[1:1], conwig_0);
AND2 I277 (conwgit_0[2:2], wg_0r1[2:2], conwig_0);
AND2 I278 (conwgit_0[3:3], wg_0r1[3:3], conwig_0);
AND2 I279 (conwgit_0[4:4], wg_0r1[4:4], conwig_0);
AND2 I280 (conwgit_0[5:5], wg_0r1[5:5], conwig_0);
AND2 I281 (conwgit_0[6:6], wg_0r1[6:6], conwig_0);
AND2 I282 (conwgit_0[7:7], wg_0r1[7:7], conwig_0);
AND2 I283 (conwgit_0[8:8], wg_0r1[8:8], conwig_0);
AND2 I284 (conwgit_0[9:9], wg_0r1[9:9], conwig_0);
AND2 I285 (conwgit_0[10:10], wg_0r1[10:10], conwig_0);
AND2 I286 (conwgit_0[11:11], wg_0r1[11:11], conwig_0);
AND2 I287 (conwgit_0[12:12], wg_0r1[12:12], conwig_0);
AND2 I288 (conwgit_0[13:13], wg_0r1[13:13], conwig_0);
AND2 I289 (conwgit_0[14:14], wg_0r1[14:14], conwig_0);
AND2 I290 (conwgit_0[15:15], wg_0r1[15:15], conwig_0);
AND2 I291 (conwgit_0[16:16], wg_0r1[16:16], conwig_0);
AND2 I292 (conwgit_0[17:17], wg_0r1[17:17], conwig_0);
AND2 I293 (conwgit_0[18:18], wg_0r1[18:18], conwig_0);
AND2 I294 (conwgit_0[19:19], wg_0r1[19:19], conwig_0);
AND2 I295 (conwgit_0[20:20], wg_0r1[20:20], conwig_0);
AND2 I296 (conwgit_0[21:21], wg_0r1[21:21], conwig_0);
AND2 I297 (conwgit_0[22:22], wg_0r1[22:22], conwig_0);
AND2 I298 (conwgit_0[23:23], wg_0r1[23:23], conwig_0);
AND2 I299 (conwgit_0[24:24], wg_0r1[24:24], conwig_0);
AND2 I300 (conwgit_0[25:25], wg_0r1[25:25], conwig_0);
AND2 I301 (conwgit_0[26:26], wg_0r1[26:26], conwig_0);
AND2 I302 (conwgit_0[27:27], wg_0r1[27:27], conwig_0);
AND2 I303 (conwgit_0[28:28], wg_0r1[28:28], conwig_0);
AND2 I304 (conwgit_0[29:29], wg_0r1[29:29], conwig_0);
AND2 I305 (conwgit_0[30:30], wg_0r1[30:30], conwig_0);
AND2 I306 (conwgit_0[31:31], wg_0r1[31:31], conwig_0);
BUFF I307 (conwigc_0, wc_0);
AO22 I308 (conwig_0, conwigc_0, conwigcanw_0, conwigc_0, conwig_0);
NOR2 I309 (conwigcanw_0, anyread_0, conwig_0);
BUFF I310 (wf_0[0:0], conwgif_0[0:0]);
BUFF I311 (wt_0[0:0], conwgit_0[0:0]);
BUFF I312 (wenr_0[0:0], wc_0);
BUFF I313 (wf_0[1:1], conwgif_0[1:1]);
BUFF I314 (wt_0[1:1], conwgit_0[1:1]);
BUFF I315 (wenr_0[1:1], wc_0);
BUFF I316 (wf_0[2:2], conwgif_0[2:2]);
BUFF I317 (wt_0[2:2], conwgit_0[2:2]);
BUFF I318 (wenr_0[2:2], wc_0);
BUFF I319 (wf_0[3:3], conwgif_0[3:3]);
BUFF I320 (wt_0[3:3], conwgit_0[3:3]);
BUFF I321 (wenr_0[3:3], wc_0);
BUFF I322 (wf_0[4:4], conwgif_0[4:4]);
BUFF I323 (wt_0[4:4], conwgit_0[4:4]);
BUFF I324 (wenr_0[4:4], wc_0);
BUFF I325 (wf_0[5:5], conwgif_0[5:5]);
BUFF I326 (wt_0[5:5], conwgit_0[5:5]);
BUFF I327 (wenr_0[5:5], wc_0);
BUFF I328 (wf_0[6:6], conwgif_0[6:6]);
BUFF I329 (wt_0[6:6], conwgit_0[6:6]);
BUFF I330 (wenr_0[6:6], wc_0);
BUFF I331 (wf_0[7:7], conwgif_0[7:7]);
BUFF I332 (wt_0[7:7], conwgit_0[7:7]);
BUFF I333 (wenr_0[7:7], wc_0);
BUFF I334 (wf_0[8:8], conwgif_0[8:8]);
BUFF I335 (wt_0[8:8], conwgit_0[8:8]);
BUFF I336 (wenr_0[8:8], wc_0);
BUFF I337 (wf_0[9:9], conwgif_0[9:9]);
BUFF I338 (wt_0[9:9], conwgit_0[9:9]);
BUFF I339 (wenr_0[9:9], wc_0);
BUFF I340 (wf_0[10:10], conwgif_0[10:10]);
BUFF I341 (wt_0[10:10], conwgit_0[10:10]);
BUFF I342 (wenr_0[10:10], wc_0);
BUFF I343 (wf_0[11:11], conwgif_0[11:11]);
BUFF I344 (wt_0[11:11], conwgit_0[11:11]);
BUFF I345 (wenr_0[11:11], wc_0);
BUFF I346 (wf_0[12:12], conwgif_0[12:12]);
BUFF I347 (wt_0[12:12], conwgit_0[12:12]);
BUFF I348 (wenr_0[12:12], wc_0);
BUFF I349 (wf_0[13:13], conwgif_0[13:13]);
BUFF I350 (wt_0[13:13], conwgit_0[13:13]);
BUFF I351 (wenr_0[13:13], wc_0);
BUFF I352 (wf_0[14:14], conwgif_0[14:14]);
BUFF I353 (wt_0[14:14], conwgit_0[14:14]);
BUFF I354 (wenr_0[14:14], wc_0);
BUFF I355 (wf_0[15:15], conwgif_0[15:15]);
BUFF I356 (wt_0[15:15], conwgit_0[15:15]);
BUFF I357 (wenr_0[15:15], wc_0);
BUFF I358 (wf_0[16:16], conwgif_0[16:16]);
BUFF I359 (wt_0[16:16], conwgit_0[16:16]);
BUFF I360 (wenr_0[16:16], wc_0);
BUFF I361 (wf_0[17:17], conwgif_0[17:17]);
BUFF I362 (wt_0[17:17], conwgit_0[17:17]);
BUFF I363 (wenr_0[17:17], wc_0);
BUFF I364 (wf_0[18:18], conwgif_0[18:18]);
BUFF I365 (wt_0[18:18], conwgit_0[18:18]);
BUFF I366 (wenr_0[18:18], wc_0);
BUFF I367 (wf_0[19:19], conwgif_0[19:19]);
BUFF I368 (wt_0[19:19], conwgit_0[19:19]);
BUFF I369 (wenr_0[19:19], wc_0);
BUFF I370 (wf_0[20:20], conwgif_0[20:20]);
BUFF I371 (wt_0[20:20], conwgit_0[20:20]);
BUFF I372 (wenr_0[20:20], wc_0);
BUFF I373 (wf_0[21:21], conwgif_0[21:21]);
BUFF I374 (wt_0[21:21], conwgit_0[21:21]);
BUFF I375 (wenr_0[21:21], wc_0);
BUFF I376 (wf_0[22:22], conwgif_0[22:22]);
BUFF I377 (wt_0[22:22], conwgit_0[22:22]);
BUFF I378 (wenr_0[22:22], wc_0);
BUFF I379 (wf_0[23:23], conwgif_0[23:23]);
BUFF I380 (wt_0[23:23], conwgit_0[23:23]);
BUFF I381 (wenr_0[23:23], wc_0);
BUFF I382 (wf_0[24:24], conwgif_0[24:24]);
BUFF I383 (wt_0[24:24], conwgit_0[24:24]);
BUFF I384 (wenr_0[24:24], wc_0);
BUFF I385 (wf_0[25:25], conwgif_0[25:25]);
BUFF I386 (wt_0[25:25], conwgit_0[25:25]);
BUFF I387 (wenr_0[25:25], wc_0);
BUFF I388 (wf_0[26:26], conwgif_0[26:26]);
BUFF I389 (wt_0[26:26], conwgit_0[26:26]);
BUFF I390 (wenr_0[26:26], wc_0);
BUFF I391 (wf_0[27:27], conwgif_0[27:27]);
BUFF I392 (wt_0[27:27], conwgit_0[27:27]);
BUFF I393 (wenr_0[27:27], wc_0);
BUFF I394 (wf_0[28:28], conwgif_0[28:28]);
BUFF I395 (wt_0[28:28], conwgit_0[28:28]);
BUFF I396 (wenr_0[28:28], wc_0);
BUFF I397 (wf_0[29:29], conwgif_0[29:29]);
BUFF I398 (wt_0[29:29], conwgit_0[29:29]);
BUFF I399 (wenr_0[29:29], wc_0);
BUFF I400 (wf_0[30:30], conwgif_0[30:30]);
BUFF I401 (wt_0[30:30], conwgit_0[30:30]);
BUFF I402 (wenr_0[30:30], wc_0);
BUFF I403 (wf_0[31:31], conwgif_0[31:31]);
BUFF I404 (wt_0[31:31], conwgit_0[31:31]);
BUFF I405 (wenr_0[31:31], wc_0);
C3 I406 (simp4071_0[0:0], conwig_0, wacks_0[0:0], wacks_0[1:1]);
C3 I407 (simp4071_0[1:1], wacks_0[2:2], wacks_0[3:3], wacks_0[4:4]);
C3 I408 (simp4071_0[2:2], wacks_0[5:5], wacks_0[6:6], wacks_0[7:7]);
C3 I409 (simp4071_0[3:3], wacks_0[8:8], wacks_0[9:9], wacks_0[10:10]);
C3 I410 (simp4071_0[4:4], wacks_0[11:11], wacks_0[12:12], wacks_0[13:13]);
C3 I411 (simp4071_0[5:5], wacks_0[14:14], wacks_0[15:15], wacks_0[16:16]);
C3 I412 (simp4071_0[6:6], wacks_0[17:17], wacks_0[18:18], wacks_0[19:19]);
C3 I413 (simp4071_0[7:7], wacks_0[20:20], wacks_0[21:21], wacks_0[22:22]);
C3 I414 (simp4071_0[8:8], wacks_0[23:23], wacks_0[24:24], wacks_0[25:25]);
C3 I415 (simp4071_0[9:9], wacks_0[26:26], wacks_0[27:27], wacks_0[28:28]);
C3 I416 (simp4071_0[10:10], wacks_0[29:29], wacks_0[30:30], wacks_0[31:31]);
C3 I417 (simp4072_0[0:0], simp4071_0[0:0], simp4071_0[1:1], simp4071_0[2:2]);
C3 I418 (simp4072_0[1:1], simp4071_0[3:3], simp4071_0[4:4], simp4071_0[5:5]);
C3 I419 (simp4072_0[2:2], simp4071_0[6:6], simp4071_0[7:7], simp4071_0[8:8]);
C2 I420 (simp4072_0[3:3], simp4071_0[9:9], simp4071_0[10:10]);
C3 I421 (simp4073_0[0:0], simp4072_0[0:0], simp4072_0[1:1], simp4072_0[2:2]);
BUFF I422 (simp4073_0[1:1], simp4072_0[3:3]);
C2 I423 (wd_0r, simp4073_0[0:0], simp4073_0[1:1]);
AND2 I424 (rd_0r0[0:0], df_0[0:0], rg_0r);
AND2 I425 (rd_0r0[1:1], df_0[1:1], rg_0r);
AND2 I426 (rd_0r0[2:2], df_0[2:2], rg_0r);
AND2 I427 (rd_0r0[3:3], df_0[3:3], rg_0r);
AND2 I428 (rd_0r0[4:4], df_0[4:4], rg_0r);
AND2 I429 (rd_0r0[5:5], df_0[5:5], rg_0r);
AND2 I430 (rd_0r0[6:6], df_0[6:6], rg_0r);
AND2 I431 (rd_0r0[7:7], df_0[7:7], rg_0r);
AND2 I432 (rd_0r0[8:8], df_0[8:8], rg_0r);
AND2 I433 (rd_0r0[9:9], df_0[9:9], rg_0r);
AND2 I434 (rd_0r0[10:10], df_0[10:10], rg_0r);
AND2 I435 (rd_0r0[11:11], df_0[11:11], rg_0r);
AND2 I436 (rd_0r0[12:12], df_0[12:12], rg_0r);
AND2 I437 (rd_0r0[13:13], df_0[13:13], rg_0r);
AND2 I438 (rd_0r0[14:14], df_0[14:14], rg_0r);
AND2 I439 (rd_0r0[15:15], df_0[15:15], rg_0r);
AND2 I440 (rd_0r0[16:16], df_0[16:16], rg_0r);
AND2 I441 (rd_0r0[17:17], df_0[17:17], rg_0r);
AND2 I442 (rd_0r0[18:18], df_0[18:18], rg_0r);
AND2 I443 (rd_0r0[19:19], df_0[19:19], rg_0r);
AND2 I444 (rd_0r0[20:20], df_0[20:20], rg_0r);
AND2 I445 (rd_0r0[21:21], df_0[21:21], rg_0r);
AND2 I446 (rd_0r0[22:22], df_0[22:22], rg_0r);
AND2 I447 (rd_0r0[23:23], df_0[23:23], rg_0r);
AND2 I448 (rd_0r0[24:24], df_0[24:24], rg_0r);
AND2 I449 (rd_0r0[25:25], df_0[25:25], rg_0r);
AND2 I450 (rd_0r0[26:26], df_0[26:26], rg_0r);
AND2 I451 (rd_0r0[27:27], df_0[27:27], rg_0r);
AND2 I452 (rd_0r0[28:28], df_0[28:28], rg_0r);
AND2 I453 (rd_0r0[29:29], df_0[29:29], rg_0r);
AND2 I454 (rd_0r0[30:30], df_0[30:30], rg_0r);
AND2 I455 (rd_0r0[31:31], df_0[31:31], rg_0r);
AND2 I456 (rd_1r0[0:0], df_0[0:0], rg_1r);
AND2 I457 (rd_1r0[1:1], df_0[1:1], rg_1r);
AND2 I458 (rd_1r0[2:2], df_0[2:2], rg_1r);
AND2 I459 (rd_1r0[3:3], df_0[3:3], rg_1r);
AND2 I460 (rd_1r0[4:4], df_0[4:4], rg_1r);
AND2 I461 (rd_1r0[5:5], df_0[5:5], rg_1r);
AND2 I462 (rd_1r0[6:6], df_0[6:6], rg_1r);
AND2 I463 (rd_1r0[7:7], df_0[7:7], rg_1r);
AND2 I464 (rd_1r0[8:8], df_0[8:8], rg_1r);
AND2 I465 (rd_1r0[9:9], df_0[9:9], rg_1r);
AND2 I466 (rd_1r0[10:10], df_0[10:10], rg_1r);
AND2 I467 (rd_1r0[11:11], df_0[11:11], rg_1r);
AND2 I468 (rd_1r0[12:12], df_0[12:12], rg_1r);
AND2 I469 (rd_1r0[13:13], df_0[13:13], rg_1r);
AND2 I470 (rd_1r0[14:14], df_0[14:14], rg_1r);
AND2 I471 (rd_1r0[15:15], df_0[15:15], rg_1r);
AND2 I472 (rd_1r0[16:16], df_0[16:16], rg_1r);
AND2 I473 (rd_1r0[17:17], df_0[17:17], rg_1r);
AND2 I474 (rd_1r0[18:18], df_0[18:18], rg_1r);
AND2 I475 (rd_1r0[19:19], df_0[19:19], rg_1r);
AND2 I476 (rd_1r0[20:20], df_0[20:20], rg_1r);
AND2 I477 (rd_1r0[21:21], df_0[21:21], rg_1r);
AND2 I478 (rd_1r0[22:22], df_0[22:22], rg_1r);
AND2 I479 (rd_1r0[23:23], df_0[23:23], rg_1r);
AND2 I480 (rd_2r0[0:0], df_0[8:8], rg_2r);
AND2 I481 (rd_2r0[1:1], df_0[9:9], rg_2r);
AND2 I482 (rd_2r0[2:2], df_0[10:10], rg_2r);
AND2 I483 (rd_2r0[3:3], df_0[11:11], rg_2r);
AND2 I484 (rd_2r0[4:4], df_0[12:12], rg_2r);
AND2 I485 (rd_2r0[5:5], df_0[13:13], rg_2r);
AND2 I486 (rd_2r0[6:6], df_0[14:14], rg_2r);
AND2 I487 (rd_2r0[7:7], df_0[15:15], rg_2r);
AND2 I488 (rd_2r0[8:8], df_0[16:16], rg_2r);
AND2 I489 (rd_2r0[9:9], df_0[17:17], rg_2r);
AND2 I490 (rd_2r0[10:10], df_0[18:18], rg_2r);
AND2 I491 (rd_2r0[11:11], df_0[19:19], rg_2r);
AND2 I492 (rd_2r0[12:12], df_0[20:20], rg_2r);
AND2 I493 (rd_2r0[13:13], df_0[21:21], rg_2r);
AND2 I494 (rd_2r0[14:14], df_0[22:22], rg_2r);
AND2 I495 (rd_2r0[15:15], df_0[23:23], rg_2r);
AND2 I496 (rd_2r0[16:16], df_0[24:24], rg_2r);
AND2 I497 (rd_2r0[17:17], df_0[25:25], rg_2r);
AND2 I498 (rd_2r0[18:18], df_0[26:26], rg_2r);
AND2 I499 (rd_2r0[19:19], df_0[27:27], rg_2r);
AND2 I500 (rd_2r0[20:20], df_0[28:28], rg_2r);
AND2 I501 (rd_2r0[21:21], df_0[29:29], rg_2r);
AND2 I502 (rd_2r0[22:22], df_0[30:30], rg_2r);
AND2 I503 (rd_2r0[23:23], df_0[31:31], rg_2r);
AND2 I504 (rd_3r0[0:0], df_0[8:8], rg_3r);
AND2 I505 (rd_3r0[1:1], df_0[9:9], rg_3r);
AND2 I506 (rd_3r0[2:2], df_0[10:10], rg_3r);
AND2 I507 (rd_3r0[3:3], df_0[11:11], rg_3r);
AND2 I508 (rd_3r0[4:4], df_0[12:12], rg_3r);
AND2 I509 (rd_3r0[5:5], df_0[13:13], rg_3r);
AND2 I510 (rd_3r0[6:6], df_0[14:14], rg_3r);
AND2 I511 (rd_3r0[7:7], df_0[15:15], rg_3r);
AND2 I512 (rd_3r0[8:8], df_0[16:16], rg_3r);
AND2 I513 (rd_3r0[9:9], df_0[17:17], rg_3r);
AND2 I514 (rd_3r0[10:10], df_0[18:18], rg_3r);
AND2 I515 (rd_3r0[11:11], df_0[19:19], rg_3r);
AND2 I516 (rd_3r0[12:12], df_0[20:20], rg_3r);
AND2 I517 (rd_3r0[13:13], df_0[21:21], rg_3r);
AND2 I518 (rd_3r0[14:14], df_0[22:22], rg_3r);
AND2 I519 (rd_3r0[15:15], df_0[23:23], rg_3r);
AND2 I520 (rd_3r0[16:16], df_0[24:24], rg_3r);
AND2 I521 (rd_3r0[17:17], df_0[25:25], rg_3r);
AND2 I522 (rd_3r0[18:18], df_0[26:26], rg_3r);
AND2 I523 (rd_3r0[19:19], df_0[27:27], rg_3r);
AND2 I524 (rd_3r0[20:20], df_0[28:28], rg_3r);
AND2 I525 (rd_3r0[21:21], df_0[29:29], rg_3r);
AND2 I526 (rd_3r0[22:22], df_0[30:30], rg_3r);
AND2 I527 (rd_3r0[23:23], df_0[31:31], rg_3r);
AND2 I528 (rd_0r1[0:0], dt_0[0:0], rg_0r);
AND2 I529 (rd_0r1[1:1], dt_0[1:1], rg_0r);
AND2 I530 (rd_0r1[2:2], dt_0[2:2], rg_0r);
AND2 I531 (rd_0r1[3:3], dt_0[3:3], rg_0r);
AND2 I532 (rd_0r1[4:4], dt_0[4:4], rg_0r);
AND2 I533 (rd_0r1[5:5], dt_0[5:5], rg_0r);
AND2 I534 (rd_0r1[6:6], dt_0[6:6], rg_0r);
AND2 I535 (rd_0r1[7:7], dt_0[7:7], rg_0r);
AND2 I536 (rd_0r1[8:8], dt_0[8:8], rg_0r);
AND2 I537 (rd_0r1[9:9], dt_0[9:9], rg_0r);
AND2 I538 (rd_0r1[10:10], dt_0[10:10], rg_0r);
AND2 I539 (rd_0r1[11:11], dt_0[11:11], rg_0r);
AND2 I540 (rd_0r1[12:12], dt_0[12:12], rg_0r);
AND2 I541 (rd_0r1[13:13], dt_0[13:13], rg_0r);
AND2 I542 (rd_0r1[14:14], dt_0[14:14], rg_0r);
AND2 I543 (rd_0r1[15:15], dt_0[15:15], rg_0r);
AND2 I544 (rd_0r1[16:16], dt_0[16:16], rg_0r);
AND2 I545 (rd_0r1[17:17], dt_0[17:17], rg_0r);
AND2 I546 (rd_0r1[18:18], dt_0[18:18], rg_0r);
AND2 I547 (rd_0r1[19:19], dt_0[19:19], rg_0r);
AND2 I548 (rd_0r1[20:20], dt_0[20:20], rg_0r);
AND2 I549 (rd_0r1[21:21], dt_0[21:21], rg_0r);
AND2 I550 (rd_0r1[22:22], dt_0[22:22], rg_0r);
AND2 I551 (rd_0r1[23:23], dt_0[23:23], rg_0r);
AND2 I552 (rd_0r1[24:24], dt_0[24:24], rg_0r);
AND2 I553 (rd_0r1[25:25], dt_0[25:25], rg_0r);
AND2 I554 (rd_0r1[26:26], dt_0[26:26], rg_0r);
AND2 I555 (rd_0r1[27:27], dt_0[27:27], rg_0r);
AND2 I556 (rd_0r1[28:28], dt_0[28:28], rg_0r);
AND2 I557 (rd_0r1[29:29], dt_0[29:29], rg_0r);
AND2 I558 (rd_0r1[30:30], dt_0[30:30], rg_0r);
AND2 I559 (rd_0r1[31:31], dt_0[31:31], rg_0r);
AND2 I560 (rd_1r1[0:0], dt_0[0:0], rg_1r);
AND2 I561 (rd_1r1[1:1], dt_0[1:1], rg_1r);
AND2 I562 (rd_1r1[2:2], dt_0[2:2], rg_1r);
AND2 I563 (rd_1r1[3:3], dt_0[3:3], rg_1r);
AND2 I564 (rd_1r1[4:4], dt_0[4:4], rg_1r);
AND2 I565 (rd_1r1[5:5], dt_0[5:5], rg_1r);
AND2 I566 (rd_1r1[6:6], dt_0[6:6], rg_1r);
AND2 I567 (rd_1r1[7:7], dt_0[7:7], rg_1r);
AND2 I568 (rd_1r1[8:8], dt_0[8:8], rg_1r);
AND2 I569 (rd_1r1[9:9], dt_0[9:9], rg_1r);
AND2 I570 (rd_1r1[10:10], dt_0[10:10], rg_1r);
AND2 I571 (rd_1r1[11:11], dt_0[11:11], rg_1r);
AND2 I572 (rd_1r1[12:12], dt_0[12:12], rg_1r);
AND2 I573 (rd_1r1[13:13], dt_0[13:13], rg_1r);
AND2 I574 (rd_1r1[14:14], dt_0[14:14], rg_1r);
AND2 I575 (rd_1r1[15:15], dt_0[15:15], rg_1r);
AND2 I576 (rd_1r1[16:16], dt_0[16:16], rg_1r);
AND2 I577 (rd_1r1[17:17], dt_0[17:17], rg_1r);
AND2 I578 (rd_1r1[18:18], dt_0[18:18], rg_1r);
AND2 I579 (rd_1r1[19:19], dt_0[19:19], rg_1r);
AND2 I580 (rd_1r1[20:20], dt_0[20:20], rg_1r);
AND2 I581 (rd_1r1[21:21], dt_0[21:21], rg_1r);
AND2 I582 (rd_1r1[22:22], dt_0[22:22], rg_1r);
AND2 I583 (rd_1r1[23:23], dt_0[23:23], rg_1r);
AND2 I584 (rd_2r1[0:0], dt_0[8:8], rg_2r);
AND2 I585 (rd_2r1[1:1], dt_0[9:9], rg_2r);
AND2 I586 (rd_2r1[2:2], dt_0[10:10], rg_2r);
AND2 I587 (rd_2r1[3:3], dt_0[11:11], rg_2r);
AND2 I588 (rd_2r1[4:4], dt_0[12:12], rg_2r);
AND2 I589 (rd_2r1[5:5], dt_0[13:13], rg_2r);
AND2 I590 (rd_2r1[6:6], dt_0[14:14], rg_2r);
AND2 I591 (rd_2r1[7:7], dt_0[15:15], rg_2r);
AND2 I592 (rd_2r1[8:8], dt_0[16:16], rg_2r);
AND2 I593 (rd_2r1[9:9], dt_0[17:17], rg_2r);
AND2 I594 (rd_2r1[10:10], dt_0[18:18], rg_2r);
AND2 I595 (rd_2r1[11:11], dt_0[19:19], rg_2r);
AND2 I596 (rd_2r1[12:12], dt_0[20:20], rg_2r);
AND2 I597 (rd_2r1[13:13], dt_0[21:21], rg_2r);
AND2 I598 (rd_2r1[14:14], dt_0[22:22], rg_2r);
AND2 I599 (rd_2r1[15:15], dt_0[23:23], rg_2r);
AND2 I600 (rd_2r1[16:16], dt_0[24:24], rg_2r);
AND2 I601 (rd_2r1[17:17], dt_0[25:25], rg_2r);
AND2 I602 (rd_2r1[18:18], dt_0[26:26], rg_2r);
AND2 I603 (rd_2r1[19:19], dt_0[27:27], rg_2r);
AND2 I604 (rd_2r1[20:20], dt_0[28:28], rg_2r);
AND2 I605 (rd_2r1[21:21], dt_0[29:29], rg_2r);
AND2 I606 (rd_2r1[22:22], dt_0[30:30], rg_2r);
AND2 I607 (rd_2r1[23:23], dt_0[31:31], rg_2r);
AND2 I608 (rd_3r1[0:0], dt_0[8:8], rg_3r);
AND2 I609 (rd_3r1[1:1], dt_0[9:9], rg_3r);
AND2 I610 (rd_3r1[2:2], dt_0[10:10], rg_3r);
AND2 I611 (rd_3r1[3:3], dt_0[11:11], rg_3r);
AND2 I612 (rd_3r1[4:4], dt_0[12:12], rg_3r);
AND2 I613 (rd_3r1[5:5], dt_0[13:13], rg_3r);
AND2 I614 (rd_3r1[6:6], dt_0[14:14], rg_3r);
AND2 I615 (rd_3r1[7:7], dt_0[15:15], rg_3r);
AND2 I616 (rd_3r1[8:8], dt_0[16:16], rg_3r);
AND2 I617 (rd_3r1[9:9], dt_0[17:17], rg_3r);
AND2 I618 (rd_3r1[10:10], dt_0[18:18], rg_3r);
AND2 I619 (rd_3r1[11:11], dt_0[19:19], rg_3r);
AND2 I620 (rd_3r1[12:12], dt_0[20:20], rg_3r);
AND2 I621 (rd_3r1[13:13], dt_0[21:21], rg_3r);
AND2 I622 (rd_3r1[14:14], dt_0[22:22], rg_3r);
AND2 I623 (rd_3r1[15:15], dt_0[23:23], rg_3r);
AND2 I624 (rd_3r1[16:16], dt_0[24:24], rg_3r);
AND2 I625 (rd_3r1[17:17], dt_0[25:25], rg_3r);
AND2 I626 (rd_3r1[18:18], dt_0[26:26], rg_3r);
AND2 I627 (rd_3r1[19:19], dt_0[27:27], rg_3r);
AND2 I628 (rd_3r1[20:20], dt_0[28:28], rg_3r);
AND2 I629 (rd_3r1[21:21], dt_0[29:29], rg_3r);
AND2 I630 (rd_3r1[22:22], dt_0[30:30], rg_3r);
AND2 I631 (rd_3r1[23:23], dt_0[31:31], rg_3r);
NOR3 I632 (simp6161_0[0:0], rg_0r, rg_1r, rg_2r);
NOR3 I633 (simp6161_0[1:1], rg_3r, rg_0a, rg_1a);
NOR2 I634 (simp6161_0[2:2], rg_2a, rg_3a);
NAND3 I635 (anyread_0, simp6161_0[0:0], simp6161_0[1:1], simp6161_0[2:2]);
BUFF I636 (wg_0a, wd_0a);
BUFF I637 (rg_0a, rd_0a);
BUFF I638 (rg_1a, rd_1a);
BUFF I639 (rg_2a, rd_2a);
BUFF I640 (rg_3a, rd_3a);
endmodule
// tko16m32_1nm16b0_2apt1o0w16bi0w16b TeakO [
// (1,TeakOConstant 16 0),
// (2,TeakOAppend 1 [(1,0+:16),(0,0+:16)])] [One 16,One 32]
module tko16m32_1nm16b0_2apt1o0w16bi0w16b (i_0r0, i_0r1, i_0a, o_0r0, o_0r1, o_0a, reset);
input [15:0] i_0r0;
input [15:0] i_0r1;
output i_0a;
output [31:0] o_0r0;
output [31:0] o_0r1;
input o_0a;
input reset;
wire go_0;
wire [15:0] gocomp_0;
wire [5:0] simp181_0;
wire [1:0] simp182_0;
wire [15:0] termf_1;
wire [15:0] termt_1;
OR2 I0 (gocomp_0[0:0], i_0r0[0:0], i_0r1[0:0]);
OR2 I1 (gocomp_0[1:1], i_0r0[1:1], i_0r1[1:1]);
OR2 I2 (gocomp_0[2:2], i_0r0[2:2], i_0r1[2:2]);
OR2 I3 (gocomp_0[3:3], i_0r0[3:3], i_0r1[3:3]);
OR2 I4 (gocomp_0[4:4], i_0r0[4:4], i_0r1[4:4]);
OR2 I5 (gocomp_0[5:5], i_0r0[5:5], i_0r1[5:5]);
OR2 I6 (gocomp_0[6:6], i_0r0[6:6], i_0r1[6:6]);
OR2 I7 (gocomp_0[7:7], i_0r0[7:7], i_0r1[7:7]);
OR2 I8 (gocomp_0[8:8], i_0r0[8:8], i_0r1[8:8]);
OR2 I9 (gocomp_0[9:9], i_0r0[9:9], i_0r1[9:9]);
OR2 I10 (gocomp_0[10:10], i_0r0[10:10], i_0r1[10:10]);
OR2 I11 (gocomp_0[11:11], i_0r0[11:11], i_0r1[11:11]);
OR2 I12 (gocomp_0[12:12], i_0r0[12:12], i_0r1[12:12]);
OR2 I13 (gocomp_0[13:13], i_0r0[13:13], i_0r1[13:13]);
OR2 I14 (gocomp_0[14:14], i_0r0[14:14], i_0r1[14:14]);
OR2 I15 (gocomp_0[15:15], i_0r0[15:15], i_0r1[15:15]);
C3 I16 (simp181_0[0:0], gocomp_0[0:0], gocomp_0[1:1], gocomp_0[2:2]);
C3 I17 (simp181_0[1:1], gocomp_0[3:3], gocomp_0[4:4], gocomp_0[5:5]);
C3 I18 (simp181_0[2:2], gocomp_0[6:6], gocomp_0[7:7], gocomp_0[8:8]);
C3 I19 (simp181_0[3:3], gocomp_0[9:9], gocomp_0[10:10], gocomp_0[11:11]);
C3 I20 (simp181_0[4:4], gocomp_0[12:12], gocomp_0[13:13], gocomp_0[14:14]);
BUFF I21 (simp181_0[5:5], gocomp_0[15:15]);
C3 I22 (simp182_0[0:0], simp181_0[0:0], simp181_0[1:1], simp181_0[2:2]);
C3 I23 (simp182_0[1:1], simp181_0[3:3], simp181_0[4:4], simp181_0[5:5]);
C2 I24 (go_0, simp182_0[0:0], simp182_0[1:1]);
BUFF I25 (termf_1[0:0], go_0);
BUFF I26 (termf_1[1:1], go_0);
BUFF I27 (termf_1[2:2], go_0);
BUFF I28 (termf_1[3:3], go_0);
BUFF I29 (termf_1[4:4], go_0);
BUFF I30 (termf_1[5:5], go_0);
BUFF I31 (termf_1[6:6], go_0);
BUFF I32 (termf_1[7:7], go_0);
BUFF I33 (termf_1[8:8], go_0);
BUFF I34 (termf_1[9:9], go_0);
BUFF I35 (termf_1[10:10], go_0);
BUFF I36 (termf_1[11:11], go_0);
BUFF I37 (termf_1[12:12], go_0);
BUFF I38 (termf_1[13:13], go_0);
BUFF I39 (termf_1[14:14], go_0);
BUFF I40 (termf_1[15:15], go_0);
GND I41 (termt_1[0:0]);
GND I42 (termt_1[1:1]);
GND I43 (termt_1[2:2]);
GND I44 (termt_1[3:3]);
GND I45 (termt_1[4:4]);
GND I46 (termt_1[5:5]);
GND I47 (termt_1[6:6]);
GND I48 (termt_1[7:7]);
GND I49 (termt_1[8:8]);
GND I50 (termt_1[9:9]);
GND I51 (termt_1[10:10]);
GND I52 (termt_1[11:11]);
GND I53 (termt_1[12:12]);
GND I54 (termt_1[13:13]);
GND I55 (termt_1[14:14]);
GND I56 (termt_1[15:15]);
BUFF I57 (o_0r0[0:0], termf_1[0:0]);
BUFF I58 (o_0r0[1:1], termf_1[1:1]);
BUFF I59 (o_0r0[2:2], termf_1[2:2]);
BUFF I60 (o_0r0[3:3], termf_1[3:3]);
BUFF I61 (o_0r0[4:4], termf_1[4:4]);
BUFF I62 (o_0r0[5:5], termf_1[5:5]);
BUFF I63 (o_0r0[6:6], termf_1[6:6]);
BUFF I64 (o_0r0[7:7], termf_1[7:7]);
BUFF I65 (o_0r0[8:8], termf_1[8:8]);
BUFF I66 (o_0r0[9:9], termf_1[9:9]);
BUFF I67 (o_0r0[10:10], termf_1[10:10]);
BUFF I68 (o_0r0[11:11], termf_1[11:11]);
BUFF I69 (o_0r0[12:12], termf_1[12:12]);
BUFF I70 (o_0r0[13:13], termf_1[13:13]);
BUFF I71 (o_0r0[14:14], termf_1[14:14]);
BUFF I72 (o_0r0[15:15], termf_1[15:15]);
BUFF I73 (o_0r0[16:16], i_0r0[0:0]);
BUFF I74 (o_0r0[17:17], i_0r0[1:1]);
BUFF I75 (o_0r0[18:18], i_0r0[2:2]);
BUFF I76 (o_0r0[19:19], i_0r0[3:3]);
BUFF I77 (o_0r0[20:20], i_0r0[4:4]);
BUFF I78 (o_0r0[21:21], i_0r0[5:5]);
BUFF I79 (o_0r0[22:22], i_0r0[6:6]);
BUFF I80 (o_0r0[23:23], i_0r0[7:7]);
BUFF I81 (o_0r0[24:24], i_0r0[8:8]);
BUFF I82 (o_0r0[25:25], i_0r0[9:9]);
BUFF I83 (o_0r0[26:26], i_0r0[10:10]);
BUFF I84 (o_0r0[27:27], i_0r0[11:11]);
BUFF I85 (o_0r0[28:28], i_0r0[12:12]);
BUFF I86 (o_0r0[29:29], i_0r0[13:13]);
BUFF I87 (o_0r0[30:30], i_0r0[14:14]);
BUFF I88 (o_0r0[31:31], i_0r0[15:15]);
BUFF I89 (o_0r1[0:0], termt_1[0:0]);
BUFF I90 (o_0r1[1:1], termt_1[1:1]);
BUFF I91 (o_0r1[2:2], termt_1[2:2]);
BUFF I92 (o_0r1[3:3], termt_1[3:3]);
BUFF I93 (o_0r1[4:4], termt_1[4:4]);
BUFF I94 (o_0r1[5:5], termt_1[5:5]);
BUFF I95 (o_0r1[6:6], termt_1[6:6]);
BUFF I96 (o_0r1[7:7], termt_1[7:7]);
BUFF I97 (o_0r1[8:8], termt_1[8:8]);
BUFF I98 (o_0r1[9:9], termt_1[9:9]);
BUFF I99 (o_0r1[10:10], termt_1[10:10]);
BUFF I100 (o_0r1[11:11], termt_1[11:11]);
BUFF I101 (o_0r1[12:12], termt_1[12:12]);
BUFF I102 (o_0r1[13:13], termt_1[13:13]);
BUFF I103 (o_0r1[14:14], termt_1[14:14]);
BUFF I104 (o_0r1[15:15], termt_1[15:15]);
BUFF I105 (o_0r1[16:16], i_0r1[0:0]);
BUFF I106 (o_0r1[17:17], i_0r1[1:1]);
BUFF I107 (o_0r1[18:18], i_0r1[2:2]);
BUFF I108 (o_0r1[19:19], i_0r1[3:3]);
BUFF I109 (o_0r1[20:20], i_0r1[4:4]);
BUFF I110 (o_0r1[21:21], i_0r1[5:5]);
BUFF I111 (o_0r1[22:22], i_0r1[6:6]);
BUFF I112 (o_0r1[23:23], i_0r1[7:7]);
BUFF I113 (o_0r1[24:24], i_0r1[8:8]);
BUFF I114 (o_0r1[25:25], i_0r1[9:9]);
BUFF I115 (o_0r1[26:26], i_0r1[10:10]);
BUFF I116 (o_0r1[27:27], i_0r1[11:11]);
BUFF I117 (o_0r1[28:28], i_0r1[12:12]);
BUFF I118 (o_0r1[29:29], i_0r1[13:13]);
BUFF I119 (o_0r1[30:30], i_0r1[14:14]);
BUFF I120 (o_0r1[31:31], i_0r1[15:15]);
BUFF I121 (i_0a, o_0a);
endmodule
// tko16m32_1nm16b0_2api0w16bt1o0w16b TeakO [
// (1,TeakOConstant 16 0),
// (2,TeakOAppend 1 [(0,0+:16),(1,0+:16)])] [One 16,One 32]
module tko16m32_1nm16b0_2api0w16bt1o0w16b (i_0r0, i_0r1, i_0a, o_0r0, o_0r1, o_0a, reset);
input [15:0] i_0r0;
input [15:0] i_0r1;
output i_0a;
output [31:0] o_0r0;
output [31:0] o_0r1;
input o_0a;
input reset;
wire go_0;
wire [15:0] gocomp_0;
wire [5:0] simp181_0;
wire [1:0] simp182_0;
wire [15:0] termf_1;
wire [15:0] termt_1;
OR2 I0 (gocomp_0[0:0], i_0r0[0:0], i_0r1[0:0]);
OR2 I1 (gocomp_0[1:1], i_0r0[1:1], i_0r1[1:1]);
OR2 I2 (gocomp_0[2:2], i_0r0[2:2], i_0r1[2:2]);
OR2 I3 (gocomp_0[3:3], i_0r0[3:3], i_0r1[3:3]);
OR2 I4 (gocomp_0[4:4], i_0r0[4:4], i_0r1[4:4]);
OR2 I5 (gocomp_0[5:5], i_0r0[5:5], i_0r1[5:5]);
OR2 I6 (gocomp_0[6:6], i_0r0[6:6], i_0r1[6:6]);
OR2 I7 (gocomp_0[7:7], i_0r0[7:7], i_0r1[7:7]);
OR2 I8 (gocomp_0[8:8], i_0r0[8:8], i_0r1[8:8]);
OR2 I9 (gocomp_0[9:9], i_0r0[9:9], i_0r1[9:9]);
OR2 I10 (gocomp_0[10:10], i_0r0[10:10], i_0r1[10:10]);
OR2 I11 (gocomp_0[11:11], i_0r0[11:11], i_0r1[11:11]);
OR2 I12 (gocomp_0[12:12], i_0r0[12:12], i_0r1[12:12]);
OR2 I13 (gocomp_0[13:13], i_0r0[13:13], i_0r1[13:13]);
OR2 I14 (gocomp_0[14:14], i_0r0[14:14], i_0r1[14:14]);
OR2 I15 (gocomp_0[15:15], i_0r0[15:15], i_0r1[15:15]);
C3 I16 (simp181_0[0:0], gocomp_0[0:0], gocomp_0[1:1], gocomp_0[2:2]);
C3 I17 (simp181_0[1:1], gocomp_0[3:3], gocomp_0[4:4], gocomp_0[5:5]);
C3 I18 (simp181_0[2:2], gocomp_0[6:6], gocomp_0[7:7], gocomp_0[8:8]);
C3 I19 (simp181_0[3:3], gocomp_0[9:9], gocomp_0[10:10], gocomp_0[11:11]);
C3 I20 (simp181_0[4:4], gocomp_0[12:12], gocomp_0[13:13], gocomp_0[14:14]);
BUFF I21 (simp181_0[5:5], gocomp_0[15:15]);
C3 I22 (simp182_0[0:0], simp181_0[0:0], simp181_0[1:1], simp181_0[2:2]);
C3 I23 (simp182_0[1:1], simp181_0[3:3], simp181_0[4:4], simp181_0[5:5]);
C2 I24 (go_0, simp182_0[0:0], simp182_0[1:1]);
BUFF I25 (termf_1[0:0], go_0);
BUFF I26 (termf_1[1:1], go_0);
BUFF I27 (termf_1[2:2], go_0);
BUFF I28 (termf_1[3:3], go_0);
BUFF I29 (termf_1[4:4], go_0);
BUFF I30 (termf_1[5:5], go_0);
BUFF I31 (termf_1[6:6], go_0);
BUFF I32 (termf_1[7:7], go_0);
BUFF I33 (termf_1[8:8], go_0);
BUFF I34 (termf_1[9:9], go_0);
BUFF I35 (termf_1[10:10], go_0);
BUFF I36 (termf_1[11:11], go_0);
BUFF I37 (termf_1[12:12], go_0);
BUFF I38 (termf_1[13:13], go_0);
BUFF I39 (termf_1[14:14], go_0);
BUFF I40 (termf_1[15:15], go_0);
GND I41 (termt_1[0:0]);
GND I42 (termt_1[1:1]);
GND I43 (termt_1[2:2]);
GND I44 (termt_1[3:3]);
GND I45 (termt_1[4:4]);
GND I46 (termt_1[5:5]);
GND I47 (termt_1[6:6]);
GND I48 (termt_1[7:7]);
GND I49 (termt_1[8:8]);
GND I50 (termt_1[9:9]);
GND I51 (termt_1[10:10]);
GND I52 (termt_1[11:11]);
GND I53 (termt_1[12:12]);
GND I54 (termt_1[13:13]);
GND I55 (termt_1[14:14]);
GND I56 (termt_1[15:15]);
BUFF I57 (o_0r0[0:0], i_0r0[0:0]);
BUFF I58 (o_0r0[1:1], i_0r0[1:1]);
BUFF I59 (o_0r0[2:2], i_0r0[2:2]);
BUFF I60 (o_0r0[3:3], i_0r0[3:3]);
BUFF I61 (o_0r0[4:4], i_0r0[4:4]);
BUFF I62 (o_0r0[5:5], i_0r0[5:5]);
BUFF I63 (o_0r0[6:6], i_0r0[6:6]);
BUFF I64 (o_0r0[7:7], i_0r0[7:7]);
BUFF I65 (o_0r0[8:8], i_0r0[8:8]);
BUFF I66 (o_0r0[9:9], i_0r0[9:9]);
BUFF I67 (o_0r0[10:10], i_0r0[10:10]);
BUFF I68 (o_0r0[11:11], i_0r0[11:11]);
BUFF I69 (o_0r0[12:12], i_0r0[12:12]);
BUFF I70 (o_0r0[13:13], i_0r0[13:13]);
BUFF I71 (o_0r0[14:14], i_0r0[14:14]);
BUFF I72 (o_0r0[15:15], i_0r0[15:15]);
BUFF I73 (o_0r0[16:16], termf_1[0:0]);
BUFF I74 (o_0r0[17:17], termf_1[1:1]);
BUFF I75 (o_0r0[18:18], termf_1[2:2]);
BUFF I76 (o_0r0[19:19], termf_1[3:3]);
BUFF I77 (o_0r0[20:20], termf_1[4:4]);
BUFF I78 (o_0r0[21:21], termf_1[5:5]);
BUFF I79 (o_0r0[22:22], termf_1[6:6]);
BUFF I80 (o_0r0[23:23], termf_1[7:7]);
BUFF I81 (o_0r0[24:24], termf_1[8:8]);
BUFF I82 (o_0r0[25:25], termf_1[9:9]);
BUFF I83 (o_0r0[26:26], termf_1[10:10]);
BUFF I84 (o_0r0[27:27], termf_1[11:11]);
BUFF I85 (o_0r0[28:28], termf_1[12:12]);
BUFF I86 (o_0r0[29:29], termf_1[13:13]);
BUFF I87 (o_0r0[30:30], termf_1[14:14]);
BUFF I88 (o_0r0[31:31], termf_1[15:15]);
BUFF I89 (o_0r1[0:0], i_0r1[0:0]);
BUFF I90 (o_0r1[1:1], i_0r1[1:1]);
BUFF I91 (o_0r1[2:2], i_0r1[2:2]);
BUFF I92 (o_0r1[3:3], i_0r1[3:3]);
BUFF I93 (o_0r1[4:4], i_0r1[4:4]);
BUFF I94 (o_0r1[5:5], i_0r1[5:5]);
BUFF I95 (o_0r1[6:6], i_0r1[6:6]);
BUFF I96 (o_0r1[7:7], i_0r1[7:7]);
BUFF I97 (o_0r1[8:8], i_0r1[8:8]);
BUFF I98 (o_0r1[9:9], i_0r1[9:9]);
BUFF I99 (o_0r1[10:10], i_0r1[10:10]);
BUFF I100 (o_0r1[11:11], i_0r1[11:11]);
BUFF I101 (o_0r1[12:12], i_0r1[12:12]);
BUFF I102 (o_0r1[13:13], i_0r1[13:13]);
BUFF I103 (o_0r1[14:14], i_0r1[14:14]);
BUFF I104 (o_0r1[15:15], i_0r1[15:15]);
BUFF I105 (o_0r1[16:16], termt_1[0:0]);
BUFF I106 (o_0r1[17:17], termt_1[1:1]);
BUFF I107 (o_0r1[18:18], termt_1[2:2]);
BUFF I108 (o_0r1[19:19], termt_1[3:3]);
BUFF I109 (o_0r1[20:20], termt_1[4:4]);
BUFF I110 (o_0r1[21:21], termt_1[5:5]);
BUFF I111 (o_0r1[22:22], termt_1[6:6]);
BUFF I112 (o_0r1[23:23], termt_1[7:7]);
BUFF I113 (o_0r1[24:24], termt_1[8:8]);
BUFF I114 (o_0r1[25:25], termt_1[9:9]);
BUFF I115 (o_0r1[26:26], termt_1[10:10]);
BUFF I116 (o_0r1[27:27], termt_1[11:11]);
BUFF I117 (o_0r1[28:28], termt_1[12:12]);
BUFF I118 (o_0r1[29:29], termt_1[13:13]);
BUFF I119 (o_0r1[30:30], termt_1[14:14]);
BUFF I120 (o_0r1[31:31], termt_1[15:15]);
BUFF I121 (i_0a, o_0a);
endmodule
// tko16m32_1nm16bffff_2api0w16bt1o0w16b TeakO [
// (1,TeakOConstant 16 65535),
// (2,TeakOAppend 1 [(0,0+:16),(1,0+:16)])] [One 16,One 32]
module tko16m32_1nm16bffff_2api0w16bt1o0w16b (i_0r0, i_0r1, i_0a, o_0r0, o_0r1, o_0a, reset);
input [15:0] i_0r0;
input [15:0] i_0r1;
output i_0a;
output [31:0] o_0r0;
output [31:0] o_0r1;
input o_0a;
input reset;
wire go_0;
wire [15:0] gocomp_0;
wire [5:0] simp181_0;
wire [1:0] simp182_0;
wire [15:0] termf_1;
wire [15:0] termt_1;
OR2 I0 (gocomp_0[0:0], i_0r0[0:0], i_0r1[0:0]);
OR2 I1 (gocomp_0[1:1], i_0r0[1:1], i_0r1[1:1]);
OR2 I2 (gocomp_0[2:2], i_0r0[2:2], i_0r1[2:2]);
OR2 I3 (gocomp_0[3:3], i_0r0[3:3], i_0r1[3:3]);
OR2 I4 (gocomp_0[4:4], i_0r0[4:4], i_0r1[4:4]);
OR2 I5 (gocomp_0[5:5], i_0r0[5:5], i_0r1[5:5]);
OR2 I6 (gocomp_0[6:6], i_0r0[6:6], i_0r1[6:6]);
OR2 I7 (gocomp_0[7:7], i_0r0[7:7], i_0r1[7:7]);
OR2 I8 (gocomp_0[8:8], i_0r0[8:8], i_0r1[8:8]);
OR2 I9 (gocomp_0[9:9], i_0r0[9:9], i_0r1[9:9]);
OR2 I10 (gocomp_0[10:10], i_0r0[10:10], i_0r1[10:10]);
OR2 I11 (gocomp_0[11:11], i_0r0[11:11], i_0r1[11:11]);
OR2 I12 (gocomp_0[12:12], i_0r0[12:12], i_0r1[12:12]);
OR2 I13 (gocomp_0[13:13], i_0r0[13:13], i_0r1[13:13]);
OR2 I14 (gocomp_0[14:14], i_0r0[14:14], i_0r1[14:14]);
OR2 I15 (gocomp_0[15:15], i_0r0[15:15], i_0r1[15:15]);
C3 I16 (simp181_0[0:0], gocomp_0[0:0], gocomp_0[1:1], gocomp_0[2:2]);
C3 I17 (simp181_0[1:1], gocomp_0[3:3], gocomp_0[4:4], gocomp_0[5:5]);
C3 I18 (simp181_0[2:2], gocomp_0[6:6], gocomp_0[7:7], gocomp_0[8:8]);
C3 I19 (simp181_0[3:3], gocomp_0[9:9], gocomp_0[10:10], gocomp_0[11:11]);
C3 I20 (simp181_0[4:4], gocomp_0[12:12], gocomp_0[13:13], gocomp_0[14:14]);
BUFF I21 (simp181_0[5:5], gocomp_0[15:15]);
C3 I22 (simp182_0[0:0], simp181_0[0:0], simp181_0[1:1], simp181_0[2:2]);
C3 I23 (simp182_0[1:1], simp181_0[3:3], simp181_0[4:4], simp181_0[5:5]);
C2 I24 (go_0, simp182_0[0:0], simp182_0[1:1]);
BUFF I25 (termt_1[0:0], go_0);
BUFF I26 (termt_1[1:1], go_0);
BUFF I27 (termt_1[2:2], go_0);
BUFF I28 (termt_1[3:3], go_0);
BUFF I29 (termt_1[4:4], go_0);
BUFF I30 (termt_1[5:5], go_0);
BUFF I31 (termt_1[6:6], go_0);
BUFF I32 (termt_1[7:7], go_0);
BUFF I33 (termt_1[8:8], go_0);
BUFF I34 (termt_1[9:9], go_0);
BUFF I35 (termt_1[10:10], go_0);
BUFF I36 (termt_1[11:11], go_0);
BUFF I37 (termt_1[12:12], go_0);
BUFF I38 (termt_1[13:13], go_0);
BUFF I39 (termt_1[14:14], go_0);
BUFF I40 (termt_1[15:15], go_0);
GND I41 (termf_1[0:0]);
GND I42 (termf_1[1:1]);
GND I43 (termf_1[2:2]);
GND I44 (termf_1[3:3]);
GND I45 (termf_1[4:4]);
GND I46 (termf_1[5:5]);
GND I47 (termf_1[6:6]);
GND I48 (termf_1[7:7]);
GND I49 (termf_1[8:8]);
GND I50 (termf_1[9:9]);
GND I51 (termf_1[10:10]);
GND I52 (termf_1[11:11]);
GND I53 (termf_1[12:12]);
GND I54 (termf_1[13:13]);
GND I55 (termf_1[14:14]);
GND I56 (termf_1[15:15]);
BUFF I57 (o_0r0[0:0], i_0r0[0:0]);
BUFF I58 (o_0r0[1:1], i_0r0[1:1]);
BUFF I59 (o_0r0[2:2], i_0r0[2:2]);
BUFF I60 (o_0r0[3:3], i_0r0[3:3]);
BUFF I61 (o_0r0[4:4], i_0r0[4:4]);
BUFF I62 (o_0r0[5:5], i_0r0[5:5]);
BUFF I63 (o_0r0[6:6], i_0r0[6:6]);
BUFF I64 (o_0r0[7:7], i_0r0[7:7]);
BUFF I65 (o_0r0[8:8], i_0r0[8:8]);
BUFF I66 (o_0r0[9:9], i_0r0[9:9]);
BUFF I67 (o_0r0[10:10], i_0r0[10:10]);
BUFF I68 (o_0r0[11:11], i_0r0[11:11]);
BUFF I69 (o_0r0[12:12], i_0r0[12:12]);
BUFF I70 (o_0r0[13:13], i_0r0[13:13]);
BUFF I71 (o_0r0[14:14], i_0r0[14:14]);
BUFF I72 (o_0r0[15:15], i_0r0[15:15]);
BUFF I73 (o_0r0[16:16], termf_1[0:0]);
BUFF I74 (o_0r0[17:17], termf_1[1:1]);
BUFF I75 (o_0r0[18:18], termf_1[2:2]);
BUFF I76 (o_0r0[19:19], termf_1[3:3]);
BUFF I77 (o_0r0[20:20], termf_1[4:4]);
BUFF I78 (o_0r0[21:21], termf_1[5:5]);
BUFF I79 (o_0r0[22:22], termf_1[6:6]);
BUFF I80 (o_0r0[23:23], termf_1[7:7]);
BUFF I81 (o_0r0[24:24], termf_1[8:8]);
BUFF I82 (o_0r0[25:25], termf_1[9:9]);
BUFF I83 (o_0r0[26:26], termf_1[10:10]);
BUFF I84 (o_0r0[27:27], termf_1[11:11]);
BUFF I85 (o_0r0[28:28], termf_1[12:12]);
BUFF I86 (o_0r0[29:29], termf_1[13:13]);
BUFF I87 (o_0r0[30:30], termf_1[14:14]);
BUFF I88 (o_0r0[31:31], termf_1[15:15]);
BUFF I89 (o_0r1[0:0], i_0r1[0:0]);
BUFF I90 (o_0r1[1:1], i_0r1[1:1]);
BUFF I91 (o_0r1[2:2], i_0r1[2:2]);
BUFF I92 (o_0r1[3:3], i_0r1[3:3]);
BUFF I93 (o_0r1[4:4], i_0r1[4:4]);
BUFF I94 (o_0r1[5:5], i_0r1[5:5]);
BUFF I95 (o_0r1[6:6], i_0r1[6:6]);
BUFF I96 (o_0r1[7:7], i_0r1[7:7]);
BUFF I97 (o_0r1[8:8], i_0r1[8:8]);
BUFF I98 (o_0r1[9:9], i_0r1[9:9]);
BUFF I99 (o_0r1[10:10], i_0r1[10:10]);
BUFF I100 (o_0r1[11:11], i_0r1[11:11]);
BUFF I101 (o_0r1[12:12], i_0r1[12:12]);
BUFF I102 (o_0r1[13:13], i_0r1[13:13]);
BUFF I103 (o_0r1[14:14], i_0r1[14:14]);
BUFF I104 (o_0r1[15:15], i_0r1[15:15]);
BUFF I105 (o_0r1[16:16], termt_1[0:0]);
BUFF I106 (o_0r1[17:17], termt_1[1:1]);
BUFF I107 (o_0r1[18:18], termt_1[2:2]);
BUFF I108 (o_0r1[19:19], termt_1[3:3]);
BUFF I109 (o_0r1[20:20], termt_1[4:4]);
BUFF I110 (o_0r1[21:21], termt_1[5:5]);
BUFF I111 (o_0r1[22:22], termt_1[6:6]);
BUFF I112 (o_0r1[23:23], termt_1[7:7]);
BUFF I113 (o_0r1[24:24], termt_1[8:8]);
BUFF I114 (o_0r1[25:25], termt_1[9:9]);
BUFF I115 (o_0r1[26:26], termt_1[10:10]);
BUFF I116 (o_0r1[27:27], termt_1[11:11]);
BUFF I117 (o_0r1[28:28], termt_1[12:12]);
BUFF I118 (o_0r1[29:29], termt_1[13:13]);
BUFF I119 (o_0r1[30:30], termt_1[14:14]);
BUFF I120 (o_0r1[31:31], termt_1[15:15]);
BUFF I121 (i_0a, o_0a);
endmodule
// tkvi32_wo0w32_ro0w32o0w16o16w16o16w16 TeakV "i" 32 [] [0] [0,0,16,16] [Many [32],Many [0],Many [0,0,
// 0,0],Many [32,16,16,16]]
module tkvi32_wo0w32_ro0w32o0w16o16w16o16w16 (wg_0r0, wg_0r1, wg_0a, wd_0r, wd_0a, rg_0r, rg_0a, rg_1r, rg_1a, rg_2r, rg_2a, rg_3r, rg_3a, rd_0r0, rd_0r1, rd_0a, rd_1r0, rd_1r1, rd_1a, rd_2r0, rd_2r1, rd_2a, rd_3r0, rd_3r1, rd_3a, reset);
input [31:0] wg_0r0;
input [31:0] wg_0r1;
output wg_0a;
output wd_0r;
input wd_0a;
input rg_0r;
output rg_0a;
input rg_1r;
output rg_1a;
input rg_2r;
output rg_2a;
input rg_3r;
output rg_3a;
output [31:0] rd_0r0;
output [31:0] rd_0r1;
input rd_0a;
output [15:0] rd_1r0;
output [15:0] rd_1r1;
input rd_1a;
output [15:0] rd_2r0;
output [15:0] rd_2r1;
input rd_2a;
output [15:0] rd_3r0;
output [15:0] rd_3r1;
input rd_3a;
input reset;
wire [31:0] wf_0;
wire [31:0] wt_0;
wire [31:0] df_0;
wire [31:0] dt_0;
wire wc_0;
wire [31:0] wacks_0;
wire [31:0] wenr_0;
wire [31:0] wen_0;
wire anyread_0;
wire nreset_0;
wire [31:0] drlgf_0;
wire [31:0] drlgt_0;
wire [31:0] comp0_0;
wire [10:0] simp2381_0;
wire [3:0] simp2382_0;
wire [1:0] simp2383_0;
wire conwigc_0;
wire conwigcanw_0;
wire [31:0] conwgit_0;
wire [31:0] conwgif_0;
wire conwig_0;
wire [10:0] simp4071_0;
wire [3:0] simp4072_0;
wire [1:0] simp4073_0;
wire [2:0] simp5681_0;
INV I0 (nreset_0, reset);
AND2 I1 (wen_0[0:0], wenr_0[0:0], nreset_0);
AND2 I2 (wen_0[1:1], wenr_0[1:1], nreset_0);
AND2 I3 (wen_0[2:2], wenr_0[2:2], nreset_0);
AND2 I4 (wen_0[3:3], wenr_0[3:3], nreset_0);
AND2 I5 (wen_0[4:4], wenr_0[4:4], nreset_0);
AND2 I6 (wen_0[5:5], wenr_0[5:5], nreset_0);
AND2 I7 (wen_0[6:6], wenr_0[6:6], nreset_0);
AND2 I8 (wen_0[7:7], wenr_0[7:7], nreset_0);
AND2 I9 (wen_0[8:8], wenr_0[8:8], nreset_0);
AND2 I10 (wen_0[9:9], wenr_0[9:9], nreset_0);
AND2 I11 (wen_0[10:10], wenr_0[10:10], nreset_0);
AND2 I12 (wen_0[11:11], wenr_0[11:11], nreset_0);
AND2 I13 (wen_0[12:12], wenr_0[12:12], nreset_0);
AND2 I14 (wen_0[13:13], wenr_0[13:13], nreset_0);
AND2 I15 (wen_0[14:14], wenr_0[14:14], nreset_0);
AND2 I16 (wen_0[15:15], wenr_0[15:15], nreset_0);
AND2 I17 (wen_0[16:16], wenr_0[16:16], nreset_0);
AND2 I18 (wen_0[17:17], wenr_0[17:17], nreset_0);
AND2 I19 (wen_0[18:18], wenr_0[18:18], nreset_0);
AND2 I20 (wen_0[19:19], wenr_0[19:19], nreset_0);
AND2 I21 (wen_0[20:20], wenr_0[20:20], nreset_0);
AND2 I22 (wen_0[21:21], wenr_0[21:21], nreset_0);
AND2 I23 (wen_0[22:22], wenr_0[22:22], nreset_0);
AND2 I24 (wen_0[23:23], wenr_0[23:23], nreset_0);
AND2 I25 (wen_0[24:24], wenr_0[24:24], nreset_0);
AND2 I26 (wen_0[25:25], wenr_0[25:25], nreset_0);
AND2 I27 (wen_0[26:26], wenr_0[26:26], nreset_0);
AND2 I28 (wen_0[27:27], wenr_0[27:27], nreset_0);
AND2 I29 (wen_0[28:28], wenr_0[28:28], nreset_0);
AND2 I30 (wen_0[29:29], wenr_0[29:29], nreset_0);
AND2 I31 (wen_0[30:30], wenr_0[30:30], nreset_0);
AND2 I32 (wen_0[31:31], wenr_0[31:31], nreset_0);
AND2 I33 (drlgf_0[0:0], wf_0[0:0], wen_0[0:0]);
AND2 I34 (drlgf_0[1:1], wf_0[1:1], wen_0[1:1]);
AND2 I35 (drlgf_0[2:2], wf_0[2:2], wen_0[2:2]);
AND2 I36 (drlgf_0[3:3], wf_0[3:3], wen_0[3:3]);
AND2 I37 (drlgf_0[4:4], wf_0[4:4], wen_0[4:4]);
AND2 I38 (drlgf_0[5:5], wf_0[5:5], wen_0[5:5]);
AND2 I39 (drlgf_0[6:6], wf_0[6:6], wen_0[6:6]);
AND2 I40 (drlgf_0[7:7], wf_0[7:7], wen_0[7:7]);
AND2 I41 (drlgf_0[8:8], wf_0[8:8], wen_0[8:8]);
AND2 I42 (drlgf_0[9:9], wf_0[9:9], wen_0[9:9]);
AND2 I43 (drlgf_0[10:10], wf_0[10:10], wen_0[10:10]);
AND2 I44 (drlgf_0[11:11], wf_0[11:11], wen_0[11:11]);
AND2 I45 (drlgf_0[12:12], wf_0[12:12], wen_0[12:12]);
AND2 I46 (drlgf_0[13:13], wf_0[13:13], wen_0[13:13]);
AND2 I47 (drlgf_0[14:14], wf_0[14:14], wen_0[14:14]);
AND2 I48 (drlgf_0[15:15], wf_0[15:15], wen_0[15:15]);
AND2 I49 (drlgf_0[16:16], wf_0[16:16], wen_0[16:16]);
AND2 I50 (drlgf_0[17:17], wf_0[17:17], wen_0[17:17]);
AND2 I51 (drlgf_0[18:18], wf_0[18:18], wen_0[18:18]);
AND2 I52 (drlgf_0[19:19], wf_0[19:19], wen_0[19:19]);
AND2 I53 (drlgf_0[20:20], wf_0[20:20], wen_0[20:20]);
AND2 I54 (drlgf_0[21:21], wf_0[21:21], wen_0[21:21]);
AND2 I55 (drlgf_0[22:22], wf_0[22:22], wen_0[22:22]);
AND2 I56 (drlgf_0[23:23], wf_0[23:23], wen_0[23:23]);
AND2 I57 (drlgf_0[24:24], wf_0[24:24], wen_0[24:24]);
AND2 I58 (drlgf_0[25:25], wf_0[25:25], wen_0[25:25]);
AND2 I59 (drlgf_0[26:26], wf_0[26:26], wen_0[26:26]);
AND2 I60 (drlgf_0[27:27], wf_0[27:27], wen_0[27:27]);
AND2 I61 (drlgf_0[28:28], wf_0[28:28], wen_0[28:28]);
AND2 I62 (drlgf_0[29:29], wf_0[29:29], wen_0[29:29]);
AND2 I63 (drlgf_0[30:30], wf_0[30:30], wen_0[30:30]);
AND2 I64 (drlgf_0[31:31], wf_0[31:31], wen_0[31:31]);
AND2 I65 (drlgt_0[0:0], wt_0[0:0], wen_0[0:0]);
AND2 I66 (drlgt_0[1:1], wt_0[1:1], wen_0[1:1]);
AND2 I67 (drlgt_0[2:2], wt_0[2:2], wen_0[2:2]);
AND2 I68 (drlgt_0[3:3], wt_0[3:3], wen_0[3:3]);
AND2 I69 (drlgt_0[4:4], wt_0[4:4], wen_0[4:4]);
AND2 I70 (drlgt_0[5:5], wt_0[5:5], wen_0[5:5]);
AND2 I71 (drlgt_0[6:6], wt_0[6:6], wen_0[6:6]);
AND2 I72 (drlgt_0[7:7], wt_0[7:7], wen_0[7:7]);
AND2 I73 (drlgt_0[8:8], wt_0[8:8], wen_0[8:8]);
AND2 I74 (drlgt_0[9:9], wt_0[9:9], wen_0[9:9]);
AND2 I75 (drlgt_0[10:10], wt_0[10:10], wen_0[10:10]);
AND2 I76 (drlgt_0[11:11], wt_0[11:11], wen_0[11:11]);
AND2 I77 (drlgt_0[12:12], wt_0[12:12], wen_0[12:12]);
AND2 I78 (drlgt_0[13:13], wt_0[13:13], wen_0[13:13]);
AND2 I79 (drlgt_0[14:14], wt_0[14:14], wen_0[14:14]);
AND2 I80 (drlgt_0[15:15], wt_0[15:15], wen_0[15:15]);
AND2 I81 (drlgt_0[16:16], wt_0[16:16], wen_0[16:16]);
AND2 I82 (drlgt_0[17:17], wt_0[17:17], wen_0[17:17]);
AND2 I83 (drlgt_0[18:18], wt_0[18:18], wen_0[18:18]);
AND2 I84 (drlgt_0[19:19], wt_0[19:19], wen_0[19:19]);
AND2 I85 (drlgt_0[20:20], wt_0[20:20], wen_0[20:20]);
AND2 I86 (drlgt_0[21:21], wt_0[21:21], wen_0[21:21]);
AND2 I87 (drlgt_0[22:22], wt_0[22:22], wen_0[22:22]);
AND2 I88 (drlgt_0[23:23], wt_0[23:23], wen_0[23:23]);
AND2 I89 (drlgt_0[24:24], wt_0[24:24], wen_0[24:24]);
AND2 I90 (drlgt_0[25:25], wt_0[25:25], wen_0[25:25]);
AND2 I91 (drlgt_0[26:26], wt_0[26:26], wen_0[26:26]);
AND2 I92 (drlgt_0[27:27], wt_0[27:27], wen_0[27:27]);
AND2 I93 (drlgt_0[28:28], wt_0[28:28], wen_0[28:28]);
AND2 I94 (drlgt_0[29:29], wt_0[29:29], wen_0[29:29]);
AND2 I95 (drlgt_0[30:30], wt_0[30:30], wen_0[30:30]);
AND2 I96 (drlgt_0[31:31], wt_0[31:31], wen_0[31:31]);
NOR2 I97 (df_0[0:0], dt_0[0:0], drlgt_0[0:0]);
NOR2 I98 (df_0[1:1], dt_0[1:1], drlgt_0[1:1]);
NOR2 I99 (df_0[2:2], dt_0[2:2], drlgt_0[2:2]);
NOR2 I100 (df_0[3:3], dt_0[3:3], drlgt_0[3:3]);
NOR2 I101 (df_0[4:4], dt_0[4:4], drlgt_0[4:4]);
NOR2 I102 (df_0[5:5], dt_0[5:5], drlgt_0[5:5]);
NOR2 I103 (df_0[6:6], dt_0[6:6], drlgt_0[6:6]);
NOR2 I104 (df_0[7:7], dt_0[7:7], drlgt_0[7:7]);
NOR2 I105 (df_0[8:8], dt_0[8:8], drlgt_0[8:8]);
NOR2 I106 (df_0[9:9], dt_0[9:9], drlgt_0[9:9]);
NOR2 I107 (df_0[10:10], dt_0[10:10], drlgt_0[10:10]);
NOR2 I108 (df_0[11:11], dt_0[11:11], drlgt_0[11:11]);
NOR2 I109 (df_0[12:12], dt_0[12:12], drlgt_0[12:12]);
NOR2 I110 (df_0[13:13], dt_0[13:13], drlgt_0[13:13]);
NOR2 I111 (df_0[14:14], dt_0[14:14], drlgt_0[14:14]);
NOR2 I112 (df_0[15:15], dt_0[15:15], drlgt_0[15:15]);
NOR2 I113 (df_0[16:16], dt_0[16:16], drlgt_0[16:16]);
NOR2 I114 (df_0[17:17], dt_0[17:17], drlgt_0[17:17]);
NOR2 I115 (df_0[18:18], dt_0[18:18], drlgt_0[18:18]);
NOR2 I116 (df_0[19:19], dt_0[19:19], drlgt_0[19:19]);
NOR2 I117 (df_0[20:20], dt_0[20:20], drlgt_0[20:20]);
NOR2 I118 (df_0[21:21], dt_0[21:21], drlgt_0[21:21]);
NOR2 I119 (df_0[22:22], dt_0[22:22], drlgt_0[22:22]);
NOR2 I120 (df_0[23:23], dt_0[23:23], drlgt_0[23:23]);
NOR2 I121 (df_0[24:24], dt_0[24:24], drlgt_0[24:24]);
NOR2 I122 (df_0[25:25], dt_0[25:25], drlgt_0[25:25]);
NOR2 I123 (df_0[26:26], dt_0[26:26], drlgt_0[26:26]);
NOR2 I124 (df_0[27:27], dt_0[27:27], drlgt_0[27:27]);
NOR2 I125 (df_0[28:28], dt_0[28:28], drlgt_0[28:28]);
NOR2 I126 (df_0[29:29], dt_0[29:29], drlgt_0[29:29]);
NOR2 I127 (df_0[30:30], dt_0[30:30], drlgt_0[30:30]);
NOR2 I128 (df_0[31:31], dt_0[31:31], drlgt_0[31:31]);
NOR3 I129 (dt_0[0:0], df_0[0:0], drlgf_0[0:0], reset);
NOR3 I130 (dt_0[1:1], df_0[1:1], drlgf_0[1:1], reset);
NOR3 I131 (dt_0[2:2], df_0[2:2], drlgf_0[2:2], reset);
NOR3 I132 (dt_0[3:3], df_0[3:3], drlgf_0[3:3], reset);
NOR3 I133 (dt_0[4:4], df_0[4:4], drlgf_0[4:4], reset);
NOR3 I134 (dt_0[5:5], df_0[5:5], drlgf_0[5:5], reset);
NOR3 I135 (dt_0[6:6], df_0[6:6], drlgf_0[6:6], reset);
NOR3 I136 (dt_0[7:7], df_0[7:7], drlgf_0[7:7], reset);
NOR3 I137 (dt_0[8:8], df_0[8:8], drlgf_0[8:8], reset);
NOR3 I138 (dt_0[9:9], df_0[9:9], drlgf_0[9:9], reset);
NOR3 I139 (dt_0[10:10], df_0[10:10], drlgf_0[10:10], reset);
NOR3 I140 (dt_0[11:11], df_0[11:11], drlgf_0[11:11], reset);
NOR3 I141 (dt_0[12:12], df_0[12:12], drlgf_0[12:12], reset);
NOR3 I142 (dt_0[13:13], df_0[13:13], drlgf_0[13:13], reset);
NOR3 I143 (dt_0[14:14], df_0[14:14], drlgf_0[14:14], reset);
NOR3 I144 (dt_0[15:15], df_0[15:15], drlgf_0[15:15], reset);
NOR3 I145 (dt_0[16:16], df_0[16:16], drlgf_0[16:16], reset);
NOR3 I146 (dt_0[17:17], df_0[17:17], drlgf_0[17:17], reset);
NOR3 I147 (dt_0[18:18], df_0[18:18], drlgf_0[18:18], reset);
NOR3 I148 (dt_0[19:19], df_0[19:19], drlgf_0[19:19], reset);
NOR3 I149 (dt_0[20:20], df_0[20:20], drlgf_0[20:20], reset);
NOR3 I150 (dt_0[21:21], df_0[21:21], drlgf_0[21:21], reset);
NOR3 I151 (dt_0[22:22], df_0[22:22], drlgf_0[22:22], reset);
NOR3 I152 (dt_0[23:23], df_0[23:23], drlgf_0[23:23], reset);
NOR3 I153 (dt_0[24:24], df_0[24:24], drlgf_0[24:24], reset);
NOR3 I154 (dt_0[25:25], df_0[25:25], drlgf_0[25:25], reset);
NOR3 I155 (dt_0[26:26], df_0[26:26], drlgf_0[26:26], reset);
NOR3 I156 (dt_0[27:27], df_0[27:27], drlgf_0[27:27], reset);
NOR3 I157 (dt_0[28:28], df_0[28:28], drlgf_0[28:28], reset);
NOR3 I158 (dt_0[29:29], df_0[29:29], drlgf_0[29:29], reset);
NOR3 I159 (dt_0[30:30], df_0[30:30], drlgf_0[30:30], reset);
NOR3 I160 (dt_0[31:31], df_0[31:31], drlgf_0[31:31], reset);
AO22 I161 (wacks_0[0:0], drlgf_0[0:0], df_0[0:0], drlgt_0[0:0], dt_0[0:0]);
AO22 I162 (wacks_0[1:1], drlgf_0[1:1], df_0[1:1], drlgt_0[1:1], dt_0[1:1]);
AO22 I163 (wacks_0[2:2], drlgf_0[2:2], df_0[2:2], drlgt_0[2:2], dt_0[2:2]);
AO22 I164 (wacks_0[3:3], drlgf_0[3:3], df_0[3:3], drlgt_0[3:3], dt_0[3:3]);
AO22 I165 (wacks_0[4:4], drlgf_0[4:4], df_0[4:4], drlgt_0[4:4], dt_0[4:4]);
AO22 I166 (wacks_0[5:5], drlgf_0[5:5], df_0[5:5], drlgt_0[5:5], dt_0[5:5]);
AO22 I167 (wacks_0[6:6], drlgf_0[6:6], df_0[6:6], drlgt_0[6:6], dt_0[6:6]);
AO22 I168 (wacks_0[7:7], drlgf_0[7:7], df_0[7:7], drlgt_0[7:7], dt_0[7:7]);
AO22 I169 (wacks_0[8:8], drlgf_0[8:8], df_0[8:8], drlgt_0[8:8], dt_0[8:8]);
AO22 I170 (wacks_0[9:9], drlgf_0[9:9], df_0[9:9], drlgt_0[9:9], dt_0[9:9]);
AO22 I171 (wacks_0[10:10], drlgf_0[10:10], df_0[10:10], drlgt_0[10:10], dt_0[10:10]);
AO22 I172 (wacks_0[11:11], drlgf_0[11:11], df_0[11:11], drlgt_0[11:11], dt_0[11:11]);
AO22 I173 (wacks_0[12:12], drlgf_0[12:12], df_0[12:12], drlgt_0[12:12], dt_0[12:12]);
AO22 I174 (wacks_0[13:13], drlgf_0[13:13], df_0[13:13], drlgt_0[13:13], dt_0[13:13]);
AO22 I175 (wacks_0[14:14], drlgf_0[14:14], df_0[14:14], drlgt_0[14:14], dt_0[14:14]);
AO22 I176 (wacks_0[15:15], drlgf_0[15:15], df_0[15:15], drlgt_0[15:15], dt_0[15:15]);
AO22 I177 (wacks_0[16:16], drlgf_0[16:16], df_0[16:16], drlgt_0[16:16], dt_0[16:16]);
AO22 I178 (wacks_0[17:17], drlgf_0[17:17], df_0[17:17], drlgt_0[17:17], dt_0[17:17]);
AO22 I179 (wacks_0[18:18], drlgf_0[18:18], df_0[18:18], drlgt_0[18:18], dt_0[18:18]);
AO22 I180 (wacks_0[19:19], drlgf_0[19:19], df_0[19:19], drlgt_0[19:19], dt_0[19:19]);
AO22 I181 (wacks_0[20:20], drlgf_0[20:20], df_0[20:20], drlgt_0[20:20], dt_0[20:20]);
AO22 I182 (wacks_0[21:21], drlgf_0[21:21], df_0[21:21], drlgt_0[21:21], dt_0[21:21]);
AO22 I183 (wacks_0[22:22], drlgf_0[22:22], df_0[22:22], drlgt_0[22:22], dt_0[22:22]);
AO22 I184 (wacks_0[23:23], drlgf_0[23:23], df_0[23:23], drlgt_0[23:23], dt_0[23:23]);
AO22 I185 (wacks_0[24:24], drlgf_0[24:24], df_0[24:24], drlgt_0[24:24], dt_0[24:24]);
AO22 I186 (wacks_0[25:25], drlgf_0[25:25], df_0[25:25], drlgt_0[25:25], dt_0[25:25]);
AO22 I187 (wacks_0[26:26], drlgf_0[26:26], df_0[26:26], drlgt_0[26:26], dt_0[26:26]);
AO22 I188 (wacks_0[27:27], drlgf_0[27:27], df_0[27:27], drlgt_0[27:27], dt_0[27:27]);
AO22 I189 (wacks_0[28:28], drlgf_0[28:28], df_0[28:28], drlgt_0[28:28], dt_0[28:28]);
AO22 I190 (wacks_0[29:29], drlgf_0[29:29], df_0[29:29], drlgt_0[29:29], dt_0[29:29]);
AO22 I191 (wacks_0[30:30], drlgf_0[30:30], df_0[30:30], drlgt_0[30:30], dt_0[30:30]);
AO22 I192 (wacks_0[31:31], drlgf_0[31:31], df_0[31:31], drlgt_0[31:31], dt_0[31:31]);
OR2 I193 (comp0_0[0:0], wg_0r0[0:0], wg_0r1[0:0]);
OR2 I194 (comp0_0[1:1], wg_0r0[1:1], wg_0r1[1:1]);
OR2 I195 (comp0_0[2:2], wg_0r0[2:2], wg_0r1[2:2]);
OR2 I196 (comp0_0[3:3], wg_0r0[3:3], wg_0r1[3:3]);
OR2 I197 (comp0_0[4:4], wg_0r0[4:4], wg_0r1[4:4]);
OR2 I198 (comp0_0[5:5], wg_0r0[5:5], wg_0r1[5:5]);
OR2 I199 (comp0_0[6:6], wg_0r0[6:6], wg_0r1[6:6]);
OR2 I200 (comp0_0[7:7], wg_0r0[7:7], wg_0r1[7:7]);
OR2 I201 (comp0_0[8:8], wg_0r0[8:8], wg_0r1[8:8]);
OR2 I202 (comp0_0[9:9], wg_0r0[9:9], wg_0r1[9:9]);
OR2 I203 (comp0_0[10:10], wg_0r0[10:10], wg_0r1[10:10]);
OR2 I204 (comp0_0[11:11], wg_0r0[11:11], wg_0r1[11:11]);
OR2 I205 (comp0_0[12:12], wg_0r0[12:12], wg_0r1[12:12]);
OR2 I206 (comp0_0[13:13], wg_0r0[13:13], wg_0r1[13:13]);
OR2 I207 (comp0_0[14:14], wg_0r0[14:14], wg_0r1[14:14]);
OR2 I208 (comp0_0[15:15], wg_0r0[15:15], wg_0r1[15:15]);
OR2 I209 (comp0_0[16:16], wg_0r0[16:16], wg_0r1[16:16]);
OR2 I210 (comp0_0[17:17], wg_0r0[17:17], wg_0r1[17:17]);
OR2 I211 (comp0_0[18:18], wg_0r0[18:18], wg_0r1[18:18]);
OR2 I212 (comp0_0[19:19], wg_0r0[19:19], wg_0r1[19:19]);
OR2 I213 (comp0_0[20:20], wg_0r0[20:20], wg_0r1[20:20]);
OR2 I214 (comp0_0[21:21], wg_0r0[21:21], wg_0r1[21:21]);
OR2 I215 (comp0_0[22:22], wg_0r0[22:22], wg_0r1[22:22]);
OR2 I216 (comp0_0[23:23], wg_0r0[23:23], wg_0r1[23:23]);
OR2 I217 (comp0_0[24:24], wg_0r0[24:24], wg_0r1[24:24]);
OR2 I218 (comp0_0[25:25], wg_0r0[25:25], wg_0r1[25:25]);
OR2 I219 (comp0_0[26:26], wg_0r0[26:26], wg_0r1[26:26]);
OR2 I220 (comp0_0[27:27], wg_0r0[27:27], wg_0r1[27:27]);
OR2 I221 (comp0_0[28:28], wg_0r0[28:28], wg_0r1[28:28]);
OR2 I222 (comp0_0[29:29], wg_0r0[29:29], wg_0r1[29:29]);
OR2 I223 (comp0_0[30:30], wg_0r0[30:30], wg_0r1[30:30]);
OR2 I224 (comp0_0[31:31], wg_0r0[31:31], wg_0r1[31:31]);
C3 I225 (simp2381_0[0:0], comp0_0[0:0], comp0_0[1:1], comp0_0[2:2]);
C3 I226 (simp2381_0[1:1], comp0_0[3:3], comp0_0[4:4], comp0_0[5:5]);
C3 I227 (simp2381_0[2:2], comp0_0[6:6], comp0_0[7:7], comp0_0[8:8]);
C3 I228 (simp2381_0[3:3], comp0_0[9:9], comp0_0[10:10], comp0_0[11:11]);
C3 I229 (simp2381_0[4:4], comp0_0[12:12], comp0_0[13:13], comp0_0[14:14]);
C3 I230 (simp2381_0[5:5], comp0_0[15:15], comp0_0[16:16], comp0_0[17:17]);
C3 I231 (simp2381_0[6:6], comp0_0[18:18], comp0_0[19:19], comp0_0[20:20]);
C3 I232 (simp2381_0[7:7], comp0_0[21:21], comp0_0[22:22], comp0_0[23:23]);
C3 I233 (simp2381_0[8:8], comp0_0[24:24], comp0_0[25:25], comp0_0[26:26]);
C3 I234 (simp2381_0[9:9], comp0_0[27:27], comp0_0[28:28], comp0_0[29:29]);
C2 I235 (simp2381_0[10:10], comp0_0[30:30], comp0_0[31:31]);
C3 I236 (simp2382_0[0:0], simp2381_0[0:0], simp2381_0[1:1], simp2381_0[2:2]);
C3 I237 (simp2382_0[1:1], simp2381_0[3:3], simp2381_0[4:4], simp2381_0[5:5]);
C3 I238 (simp2382_0[2:2], simp2381_0[6:6], simp2381_0[7:7], simp2381_0[8:8]);
C2 I239 (simp2382_0[3:3], simp2381_0[9:9], simp2381_0[10:10]);
C3 I240 (simp2383_0[0:0], simp2382_0[0:0], simp2382_0[1:1], simp2382_0[2:2]);
BUFF I241 (simp2383_0[1:1], simp2382_0[3:3]);
C2 I242 (wc_0, simp2383_0[0:0], simp2383_0[1:1]);
AND2 I243 (conwgif_0[0:0], wg_0r0[0:0], conwig_0);
AND2 I244 (conwgif_0[1:1], wg_0r0[1:1], conwig_0);
AND2 I245 (conwgif_0[2:2], wg_0r0[2:2], conwig_0);
AND2 I246 (conwgif_0[3:3], wg_0r0[3:3], conwig_0);
AND2 I247 (conwgif_0[4:4], wg_0r0[4:4], conwig_0);
AND2 I248 (conwgif_0[5:5], wg_0r0[5:5], conwig_0);
AND2 I249 (conwgif_0[6:6], wg_0r0[6:6], conwig_0);
AND2 I250 (conwgif_0[7:7], wg_0r0[7:7], conwig_0);
AND2 I251 (conwgif_0[8:8], wg_0r0[8:8], conwig_0);
AND2 I252 (conwgif_0[9:9], wg_0r0[9:9], conwig_0);
AND2 I253 (conwgif_0[10:10], wg_0r0[10:10], conwig_0);
AND2 I254 (conwgif_0[11:11], wg_0r0[11:11], conwig_0);
AND2 I255 (conwgif_0[12:12], wg_0r0[12:12], conwig_0);
AND2 I256 (conwgif_0[13:13], wg_0r0[13:13], conwig_0);
AND2 I257 (conwgif_0[14:14], wg_0r0[14:14], conwig_0);
AND2 I258 (conwgif_0[15:15], wg_0r0[15:15], conwig_0);
AND2 I259 (conwgif_0[16:16], wg_0r0[16:16], conwig_0);
AND2 I260 (conwgif_0[17:17], wg_0r0[17:17], conwig_0);
AND2 I261 (conwgif_0[18:18], wg_0r0[18:18], conwig_0);
AND2 I262 (conwgif_0[19:19], wg_0r0[19:19], conwig_0);
AND2 I263 (conwgif_0[20:20], wg_0r0[20:20], conwig_0);
AND2 I264 (conwgif_0[21:21], wg_0r0[21:21], conwig_0);
AND2 I265 (conwgif_0[22:22], wg_0r0[22:22], conwig_0);
AND2 I266 (conwgif_0[23:23], wg_0r0[23:23], conwig_0);
AND2 I267 (conwgif_0[24:24], wg_0r0[24:24], conwig_0);
AND2 I268 (conwgif_0[25:25], wg_0r0[25:25], conwig_0);
AND2 I269 (conwgif_0[26:26], wg_0r0[26:26], conwig_0);
AND2 I270 (conwgif_0[27:27], wg_0r0[27:27], conwig_0);
AND2 I271 (conwgif_0[28:28], wg_0r0[28:28], conwig_0);
AND2 I272 (conwgif_0[29:29], wg_0r0[29:29], conwig_0);
AND2 I273 (conwgif_0[30:30], wg_0r0[30:30], conwig_0);
AND2 I274 (conwgif_0[31:31], wg_0r0[31:31], conwig_0);
AND2 I275 (conwgit_0[0:0], wg_0r1[0:0], conwig_0);
AND2 I276 (conwgit_0[1:1], wg_0r1[1:1], conwig_0);
AND2 I277 (conwgit_0[2:2], wg_0r1[2:2], conwig_0);
AND2 I278 (conwgit_0[3:3], wg_0r1[3:3], conwig_0);
AND2 I279 (conwgit_0[4:4], wg_0r1[4:4], conwig_0);
AND2 I280 (conwgit_0[5:5], wg_0r1[5:5], conwig_0);
AND2 I281 (conwgit_0[6:6], wg_0r1[6:6], conwig_0);
AND2 I282 (conwgit_0[7:7], wg_0r1[7:7], conwig_0);
AND2 I283 (conwgit_0[8:8], wg_0r1[8:8], conwig_0);
AND2 I284 (conwgit_0[9:9], wg_0r1[9:9], conwig_0);
AND2 I285 (conwgit_0[10:10], wg_0r1[10:10], conwig_0);
AND2 I286 (conwgit_0[11:11], wg_0r1[11:11], conwig_0);
AND2 I287 (conwgit_0[12:12], wg_0r1[12:12], conwig_0);
AND2 I288 (conwgit_0[13:13], wg_0r1[13:13], conwig_0);
AND2 I289 (conwgit_0[14:14], wg_0r1[14:14], conwig_0);
AND2 I290 (conwgit_0[15:15], wg_0r1[15:15], conwig_0);
AND2 I291 (conwgit_0[16:16], wg_0r1[16:16], conwig_0);
AND2 I292 (conwgit_0[17:17], wg_0r1[17:17], conwig_0);
AND2 I293 (conwgit_0[18:18], wg_0r1[18:18], conwig_0);
AND2 I294 (conwgit_0[19:19], wg_0r1[19:19], conwig_0);
AND2 I295 (conwgit_0[20:20], wg_0r1[20:20], conwig_0);
AND2 I296 (conwgit_0[21:21], wg_0r1[21:21], conwig_0);
AND2 I297 (conwgit_0[22:22], wg_0r1[22:22], conwig_0);
AND2 I298 (conwgit_0[23:23], wg_0r1[23:23], conwig_0);
AND2 I299 (conwgit_0[24:24], wg_0r1[24:24], conwig_0);
AND2 I300 (conwgit_0[25:25], wg_0r1[25:25], conwig_0);
AND2 I301 (conwgit_0[26:26], wg_0r1[26:26], conwig_0);
AND2 I302 (conwgit_0[27:27], wg_0r1[27:27], conwig_0);
AND2 I303 (conwgit_0[28:28], wg_0r1[28:28], conwig_0);
AND2 I304 (conwgit_0[29:29], wg_0r1[29:29], conwig_0);
AND2 I305 (conwgit_0[30:30], wg_0r1[30:30], conwig_0);
AND2 I306 (conwgit_0[31:31], wg_0r1[31:31], conwig_0);
BUFF I307 (conwigc_0, wc_0);
AO22 I308 (conwig_0, conwigc_0, conwigcanw_0, conwigc_0, conwig_0);
NOR2 I309 (conwigcanw_0, anyread_0, conwig_0);
BUFF I310 (wf_0[0:0], conwgif_0[0:0]);
BUFF I311 (wt_0[0:0], conwgit_0[0:0]);
BUFF I312 (wenr_0[0:0], wc_0);
BUFF I313 (wf_0[1:1], conwgif_0[1:1]);
BUFF I314 (wt_0[1:1], conwgit_0[1:1]);
BUFF I315 (wenr_0[1:1], wc_0);
BUFF I316 (wf_0[2:2], conwgif_0[2:2]);
BUFF I317 (wt_0[2:2], conwgit_0[2:2]);
BUFF I318 (wenr_0[2:2], wc_0);
BUFF I319 (wf_0[3:3], conwgif_0[3:3]);
BUFF I320 (wt_0[3:3], conwgit_0[3:3]);
BUFF I321 (wenr_0[3:3], wc_0);
BUFF I322 (wf_0[4:4], conwgif_0[4:4]);
BUFF I323 (wt_0[4:4], conwgit_0[4:4]);
BUFF I324 (wenr_0[4:4], wc_0);
BUFF I325 (wf_0[5:5], conwgif_0[5:5]);
BUFF I326 (wt_0[5:5], conwgit_0[5:5]);
BUFF I327 (wenr_0[5:5], wc_0);
BUFF I328 (wf_0[6:6], conwgif_0[6:6]);
BUFF I329 (wt_0[6:6], conwgit_0[6:6]);
BUFF I330 (wenr_0[6:6], wc_0);
BUFF I331 (wf_0[7:7], conwgif_0[7:7]);
BUFF I332 (wt_0[7:7], conwgit_0[7:7]);
BUFF I333 (wenr_0[7:7], wc_0);
BUFF I334 (wf_0[8:8], conwgif_0[8:8]);
BUFF I335 (wt_0[8:8], conwgit_0[8:8]);
BUFF I336 (wenr_0[8:8], wc_0);
BUFF I337 (wf_0[9:9], conwgif_0[9:9]);
BUFF I338 (wt_0[9:9], conwgit_0[9:9]);
BUFF I339 (wenr_0[9:9], wc_0);
BUFF I340 (wf_0[10:10], conwgif_0[10:10]);
BUFF I341 (wt_0[10:10], conwgit_0[10:10]);
BUFF I342 (wenr_0[10:10], wc_0);
BUFF I343 (wf_0[11:11], conwgif_0[11:11]);
BUFF I344 (wt_0[11:11], conwgit_0[11:11]);
BUFF I345 (wenr_0[11:11], wc_0);
BUFF I346 (wf_0[12:12], conwgif_0[12:12]);
BUFF I347 (wt_0[12:12], conwgit_0[12:12]);
BUFF I348 (wenr_0[12:12], wc_0);
BUFF I349 (wf_0[13:13], conwgif_0[13:13]);
BUFF I350 (wt_0[13:13], conwgit_0[13:13]);
BUFF I351 (wenr_0[13:13], wc_0);
BUFF I352 (wf_0[14:14], conwgif_0[14:14]);
BUFF I353 (wt_0[14:14], conwgit_0[14:14]);
BUFF I354 (wenr_0[14:14], wc_0);
BUFF I355 (wf_0[15:15], conwgif_0[15:15]);
BUFF I356 (wt_0[15:15], conwgit_0[15:15]);
BUFF I357 (wenr_0[15:15], wc_0);
BUFF I358 (wf_0[16:16], conwgif_0[16:16]);
BUFF I359 (wt_0[16:16], conwgit_0[16:16]);
BUFF I360 (wenr_0[16:16], wc_0);
BUFF I361 (wf_0[17:17], conwgif_0[17:17]);
BUFF I362 (wt_0[17:17], conwgit_0[17:17]);
BUFF I363 (wenr_0[17:17], wc_0);
BUFF I364 (wf_0[18:18], conwgif_0[18:18]);
BUFF I365 (wt_0[18:18], conwgit_0[18:18]);
BUFF I366 (wenr_0[18:18], wc_0);
BUFF I367 (wf_0[19:19], conwgif_0[19:19]);
BUFF I368 (wt_0[19:19], conwgit_0[19:19]);
BUFF I369 (wenr_0[19:19], wc_0);
BUFF I370 (wf_0[20:20], conwgif_0[20:20]);
BUFF I371 (wt_0[20:20], conwgit_0[20:20]);
BUFF I372 (wenr_0[20:20], wc_0);
BUFF I373 (wf_0[21:21], conwgif_0[21:21]);
BUFF I374 (wt_0[21:21], conwgit_0[21:21]);
BUFF I375 (wenr_0[21:21], wc_0);
BUFF I376 (wf_0[22:22], conwgif_0[22:22]);
BUFF I377 (wt_0[22:22], conwgit_0[22:22]);
BUFF I378 (wenr_0[22:22], wc_0);
BUFF I379 (wf_0[23:23], conwgif_0[23:23]);
BUFF I380 (wt_0[23:23], conwgit_0[23:23]);
BUFF I381 (wenr_0[23:23], wc_0);
BUFF I382 (wf_0[24:24], conwgif_0[24:24]);
BUFF I383 (wt_0[24:24], conwgit_0[24:24]);
BUFF I384 (wenr_0[24:24], wc_0);
BUFF I385 (wf_0[25:25], conwgif_0[25:25]);
BUFF I386 (wt_0[25:25], conwgit_0[25:25]);
BUFF I387 (wenr_0[25:25], wc_0);
BUFF I388 (wf_0[26:26], conwgif_0[26:26]);
BUFF I389 (wt_0[26:26], conwgit_0[26:26]);
BUFF I390 (wenr_0[26:26], wc_0);
BUFF I391 (wf_0[27:27], conwgif_0[27:27]);
BUFF I392 (wt_0[27:27], conwgit_0[27:27]);
BUFF I393 (wenr_0[27:27], wc_0);
BUFF I394 (wf_0[28:28], conwgif_0[28:28]);
BUFF I395 (wt_0[28:28], conwgit_0[28:28]);
BUFF I396 (wenr_0[28:28], wc_0);
BUFF I397 (wf_0[29:29], conwgif_0[29:29]);
BUFF I398 (wt_0[29:29], conwgit_0[29:29]);
BUFF I399 (wenr_0[29:29], wc_0);
BUFF I400 (wf_0[30:30], conwgif_0[30:30]);
BUFF I401 (wt_0[30:30], conwgit_0[30:30]);
BUFF I402 (wenr_0[30:30], wc_0);
BUFF I403 (wf_0[31:31], conwgif_0[31:31]);
BUFF I404 (wt_0[31:31], conwgit_0[31:31]);
BUFF I405 (wenr_0[31:31], wc_0);
C3 I406 (simp4071_0[0:0], conwig_0, wacks_0[0:0], wacks_0[1:1]);
C3 I407 (simp4071_0[1:1], wacks_0[2:2], wacks_0[3:3], wacks_0[4:4]);
C3 I408 (simp4071_0[2:2], wacks_0[5:5], wacks_0[6:6], wacks_0[7:7]);
C3 I409 (simp4071_0[3:3], wacks_0[8:8], wacks_0[9:9], wacks_0[10:10]);
C3 I410 (simp4071_0[4:4], wacks_0[11:11], wacks_0[12:12], wacks_0[13:13]);
C3 I411 (simp4071_0[5:5], wacks_0[14:14], wacks_0[15:15], wacks_0[16:16]);
C3 I412 (simp4071_0[6:6], wacks_0[17:17], wacks_0[18:18], wacks_0[19:19]);
C3 I413 (simp4071_0[7:7], wacks_0[20:20], wacks_0[21:21], wacks_0[22:22]);
C3 I414 (simp4071_0[8:8], wacks_0[23:23], wacks_0[24:24], wacks_0[25:25]);
C3 I415 (simp4071_0[9:9], wacks_0[26:26], wacks_0[27:27], wacks_0[28:28]);
C3 I416 (simp4071_0[10:10], wacks_0[29:29], wacks_0[30:30], wacks_0[31:31]);
C3 I417 (simp4072_0[0:0], simp4071_0[0:0], simp4071_0[1:1], simp4071_0[2:2]);
C3 I418 (simp4072_0[1:1], simp4071_0[3:3], simp4071_0[4:4], simp4071_0[5:5]);
C3 I419 (simp4072_0[2:2], simp4071_0[6:6], simp4071_0[7:7], simp4071_0[8:8]);
C2 I420 (simp4072_0[3:3], simp4071_0[9:9], simp4071_0[10:10]);
C3 I421 (simp4073_0[0:0], simp4072_0[0:0], simp4072_0[1:1], simp4072_0[2:2]);
BUFF I422 (simp4073_0[1:1], simp4072_0[3:3]);
C2 I423 (wd_0r, simp4073_0[0:0], simp4073_0[1:1]);
AND2 I424 (rd_0r0[0:0], df_0[0:0], rg_0r);
AND2 I425 (rd_0r0[1:1], df_0[1:1], rg_0r);
AND2 I426 (rd_0r0[2:2], df_0[2:2], rg_0r);
AND2 I427 (rd_0r0[3:3], df_0[3:3], rg_0r);
AND2 I428 (rd_0r0[4:4], df_0[4:4], rg_0r);
AND2 I429 (rd_0r0[5:5], df_0[5:5], rg_0r);
AND2 I430 (rd_0r0[6:6], df_0[6:6], rg_0r);
AND2 I431 (rd_0r0[7:7], df_0[7:7], rg_0r);
AND2 I432 (rd_0r0[8:8], df_0[8:8], rg_0r);
AND2 I433 (rd_0r0[9:9], df_0[9:9], rg_0r);
AND2 I434 (rd_0r0[10:10], df_0[10:10], rg_0r);
AND2 I435 (rd_0r0[11:11], df_0[11:11], rg_0r);
AND2 I436 (rd_0r0[12:12], df_0[12:12], rg_0r);
AND2 I437 (rd_0r0[13:13], df_0[13:13], rg_0r);
AND2 I438 (rd_0r0[14:14], df_0[14:14], rg_0r);
AND2 I439 (rd_0r0[15:15], df_0[15:15], rg_0r);
AND2 I440 (rd_0r0[16:16], df_0[16:16], rg_0r);
AND2 I441 (rd_0r0[17:17], df_0[17:17], rg_0r);
AND2 I442 (rd_0r0[18:18], df_0[18:18], rg_0r);
AND2 I443 (rd_0r0[19:19], df_0[19:19], rg_0r);
AND2 I444 (rd_0r0[20:20], df_0[20:20], rg_0r);
AND2 I445 (rd_0r0[21:21], df_0[21:21], rg_0r);
AND2 I446 (rd_0r0[22:22], df_0[22:22], rg_0r);
AND2 I447 (rd_0r0[23:23], df_0[23:23], rg_0r);
AND2 I448 (rd_0r0[24:24], df_0[24:24], rg_0r);
AND2 I449 (rd_0r0[25:25], df_0[25:25], rg_0r);
AND2 I450 (rd_0r0[26:26], df_0[26:26], rg_0r);
AND2 I451 (rd_0r0[27:27], df_0[27:27], rg_0r);
AND2 I452 (rd_0r0[28:28], df_0[28:28], rg_0r);
AND2 I453 (rd_0r0[29:29], df_0[29:29], rg_0r);
AND2 I454 (rd_0r0[30:30], df_0[30:30], rg_0r);
AND2 I455 (rd_0r0[31:31], df_0[31:31], rg_0r);
AND2 I456 (rd_1r0[0:0], df_0[0:0], rg_1r);
AND2 I457 (rd_1r0[1:1], df_0[1:1], rg_1r);
AND2 I458 (rd_1r0[2:2], df_0[2:2], rg_1r);
AND2 I459 (rd_1r0[3:3], df_0[3:3], rg_1r);
AND2 I460 (rd_1r0[4:4], df_0[4:4], rg_1r);
AND2 I461 (rd_1r0[5:5], df_0[5:5], rg_1r);
AND2 I462 (rd_1r0[6:6], df_0[6:6], rg_1r);
AND2 I463 (rd_1r0[7:7], df_0[7:7], rg_1r);
AND2 I464 (rd_1r0[8:8], df_0[8:8], rg_1r);
AND2 I465 (rd_1r0[9:9], df_0[9:9], rg_1r);
AND2 I466 (rd_1r0[10:10], df_0[10:10], rg_1r);
AND2 I467 (rd_1r0[11:11], df_0[11:11], rg_1r);
AND2 I468 (rd_1r0[12:12], df_0[12:12], rg_1r);
AND2 I469 (rd_1r0[13:13], df_0[13:13], rg_1r);
AND2 I470 (rd_1r0[14:14], df_0[14:14], rg_1r);
AND2 I471 (rd_1r0[15:15], df_0[15:15], rg_1r);
AND2 I472 (rd_2r0[0:0], df_0[16:16], rg_2r);
AND2 I473 (rd_2r0[1:1], df_0[17:17], rg_2r);
AND2 I474 (rd_2r0[2:2], df_0[18:18], rg_2r);
AND2 I475 (rd_2r0[3:3], df_0[19:19], rg_2r);
AND2 I476 (rd_2r0[4:4], df_0[20:20], rg_2r);
AND2 I477 (rd_2r0[5:5], df_0[21:21], rg_2r);
AND2 I478 (rd_2r0[6:6], df_0[22:22], rg_2r);
AND2 I479 (rd_2r0[7:7], df_0[23:23], rg_2r);
AND2 I480 (rd_2r0[8:8], df_0[24:24], rg_2r);
AND2 I481 (rd_2r0[9:9], df_0[25:25], rg_2r);
AND2 I482 (rd_2r0[10:10], df_0[26:26], rg_2r);
AND2 I483 (rd_2r0[11:11], df_0[27:27], rg_2r);
AND2 I484 (rd_2r0[12:12], df_0[28:28], rg_2r);
AND2 I485 (rd_2r0[13:13], df_0[29:29], rg_2r);
AND2 I486 (rd_2r0[14:14], df_0[30:30], rg_2r);
AND2 I487 (rd_2r0[15:15], df_0[31:31], rg_2r);
AND2 I488 (rd_3r0[0:0], df_0[16:16], rg_3r);
AND2 I489 (rd_3r0[1:1], df_0[17:17], rg_3r);
AND2 I490 (rd_3r0[2:2], df_0[18:18], rg_3r);
AND2 I491 (rd_3r0[3:3], df_0[19:19], rg_3r);
AND2 I492 (rd_3r0[4:4], df_0[20:20], rg_3r);
AND2 I493 (rd_3r0[5:5], df_0[21:21], rg_3r);
AND2 I494 (rd_3r0[6:6], df_0[22:22], rg_3r);
AND2 I495 (rd_3r0[7:7], df_0[23:23], rg_3r);
AND2 I496 (rd_3r0[8:8], df_0[24:24], rg_3r);
AND2 I497 (rd_3r0[9:9], df_0[25:25], rg_3r);
AND2 I498 (rd_3r0[10:10], df_0[26:26], rg_3r);
AND2 I499 (rd_3r0[11:11], df_0[27:27], rg_3r);
AND2 I500 (rd_3r0[12:12], df_0[28:28], rg_3r);
AND2 I501 (rd_3r0[13:13], df_0[29:29], rg_3r);
AND2 I502 (rd_3r0[14:14], df_0[30:30], rg_3r);
AND2 I503 (rd_3r0[15:15], df_0[31:31], rg_3r);
AND2 I504 (rd_0r1[0:0], dt_0[0:0], rg_0r);
AND2 I505 (rd_0r1[1:1], dt_0[1:1], rg_0r);
AND2 I506 (rd_0r1[2:2], dt_0[2:2], rg_0r);
AND2 I507 (rd_0r1[3:3], dt_0[3:3], rg_0r);
AND2 I508 (rd_0r1[4:4], dt_0[4:4], rg_0r);
AND2 I509 (rd_0r1[5:5], dt_0[5:5], rg_0r);
AND2 I510 (rd_0r1[6:6], dt_0[6:6], rg_0r);
AND2 I511 (rd_0r1[7:7], dt_0[7:7], rg_0r);
AND2 I512 (rd_0r1[8:8], dt_0[8:8], rg_0r);
AND2 I513 (rd_0r1[9:9], dt_0[9:9], rg_0r);
AND2 I514 (rd_0r1[10:10], dt_0[10:10], rg_0r);
AND2 I515 (rd_0r1[11:11], dt_0[11:11], rg_0r);
AND2 I516 (rd_0r1[12:12], dt_0[12:12], rg_0r);
AND2 I517 (rd_0r1[13:13], dt_0[13:13], rg_0r);
AND2 I518 (rd_0r1[14:14], dt_0[14:14], rg_0r);
AND2 I519 (rd_0r1[15:15], dt_0[15:15], rg_0r);
AND2 I520 (rd_0r1[16:16], dt_0[16:16], rg_0r);
AND2 I521 (rd_0r1[17:17], dt_0[17:17], rg_0r);
AND2 I522 (rd_0r1[18:18], dt_0[18:18], rg_0r);
AND2 I523 (rd_0r1[19:19], dt_0[19:19], rg_0r);
AND2 I524 (rd_0r1[20:20], dt_0[20:20], rg_0r);
AND2 I525 (rd_0r1[21:21], dt_0[21:21], rg_0r);
AND2 I526 (rd_0r1[22:22], dt_0[22:22], rg_0r);
AND2 I527 (rd_0r1[23:23], dt_0[23:23], rg_0r);
AND2 I528 (rd_0r1[24:24], dt_0[24:24], rg_0r);
AND2 I529 (rd_0r1[25:25], dt_0[25:25], rg_0r);
AND2 I530 (rd_0r1[26:26], dt_0[26:26], rg_0r);
AND2 I531 (rd_0r1[27:27], dt_0[27:27], rg_0r);
AND2 I532 (rd_0r1[28:28], dt_0[28:28], rg_0r);
AND2 I533 (rd_0r1[29:29], dt_0[29:29], rg_0r);
AND2 I534 (rd_0r1[30:30], dt_0[30:30], rg_0r);
AND2 I535 (rd_0r1[31:31], dt_0[31:31], rg_0r);
AND2 I536 (rd_1r1[0:0], dt_0[0:0], rg_1r);
AND2 I537 (rd_1r1[1:1], dt_0[1:1], rg_1r);
AND2 I538 (rd_1r1[2:2], dt_0[2:2], rg_1r);
AND2 I539 (rd_1r1[3:3], dt_0[3:3], rg_1r);
AND2 I540 (rd_1r1[4:4], dt_0[4:4], rg_1r);
AND2 I541 (rd_1r1[5:5], dt_0[5:5], rg_1r);
AND2 I542 (rd_1r1[6:6], dt_0[6:6], rg_1r);
AND2 I543 (rd_1r1[7:7], dt_0[7:7], rg_1r);
AND2 I544 (rd_1r1[8:8], dt_0[8:8], rg_1r);
AND2 I545 (rd_1r1[9:9], dt_0[9:9], rg_1r);
AND2 I546 (rd_1r1[10:10], dt_0[10:10], rg_1r);
AND2 I547 (rd_1r1[11:11], dt_0[11:11], rg_1r);
AND2 I548 (rd_1r1[12:12], dt_0[12:12], rg_1r);
AND2 I549 (rd_1r1[13:13], dt_0[13:13], rg_1r);
AND2 I550 (rd_1r1[14:14], dt_0[14:14], rg_1r);
AND2 I551 (rd_1r1[15:15], dt_0[15:15], rg_1r);
AND2 I552 (rd_2r1[0:0], dt_0[16:16], rg_2r);
AND2 I553 (rd_2r1[1:1], dt_0[17:17], rg_2r);
AND2 I554 (rd_2r1[2:2], dt_0[18:18], rg_2r);
AND2 I555 (rd_2r1[3:3], dt_0[19:19], rg_2r);
AND2 I556 (rd_2r1[4:4], dt_0[20:20], rg_2r);
AND2 I557 (rd_2r1[5:5], dt_0[21:21], rg_2r);
AND2 I558 (rd_2r1[6:6], dt_0[22:22], rg_2r);
AND2 I559 (rd_2r1[7:7], dt_0[23:23], rg_2r);
AND2 I560 (rd_2r1[8:8], dt_0[24:24], rg_2r);
AND2 I561 (rd_2r1[9:9], dt_0[25:25], rg_2r);
AND2 I562 (rd_2r1[10:10], dt_0[26:26], rg_2r);
AND2 I563 (rd_2r1[11:11], dt_0[27:27], rg_2r);
AND2 I564 (rd_2r1[12:12], dt_0[28:28], rg_2r);
AND2 I565 (rd_2r1[13:13], dt_0[29:29], rg_2r);
AND2 I566 (rd_2r1[14:14], dt_0[30:30], rg_2r);
AND2 I567 (rd_2r1[15:15], dt_0[31:31], rg_2r);
AND2 I568 (rd_3r1[0:0], dt_0[16:16], rg_3r);
AND2 I569 (rd_3r1[1:1], dt_0[17:17], rg_3r);
AND2 I570 (rd_3r1[2:2], dt_0[18:18], rg_3r);
AND2 I571 (rd_3r1[3:3], dt_0[19:19], rg_3r);
AND2 I572 (rd_3r1[4:4], dt_0[20:20], rg_3r);
AND2 I573 (rd_3r1[5:5], dt_0[21:21], rg_3r);
AND2 I574 (rd_3r1[6:6], dt_0[22:22], rg_3r);
AND2 I575 (rd_3r1[7:7], dt_0[23:23], rg_3r);
AND2 I576 (rd_3r1[8:8], dt_0[24:24], rg_3r);
AND2 I577 (rd_3r1[9:9], dt_0[25:25], rg_3r);
AND2 I578 (rd_3r1[10:10], dt_0[26:26], rg_3r);
AND2 I579 (rd_3r1[11:11], dt_0[27:27], rg_3r);
AND2 I580 (rd_3r1[12:12], dt_0[28:28], rg_3r);
AND2 I581 (rd_3r1[13:13], dt_0[29:29], rg_3r);
AND2 I582 (rd_3r1[14:14], dt_0[30:30], rg_3r);
AND2 I583 (rd_3r1[15:15], dt_0[31:31], rg_3r);
NOR3 I584 (simp5681_0[0:0], rg_0r, rg_1r, rg_2r);
NOR3 I585 (simp5681_0[1:1], rg_3r, rg_0a, rg_1a);
NOR2 I586 (simp5681_0[2:2], rg_2a, rg_3a);
NAND3 I587 (anyread_0, simp5681_0[0:0], simp5681_0[1:1], simp5681_0[2:2]);
BUFF I588 (wg_0a, wd_0a);
BUFF I589 (rg_0a, rd_0a);
BUFF I590 (rg_1a, rd_1a);
BUFF I591 (rg_2a, rd_2a);
BUFF I592 (rg_3a, rd_3a);
endmodule
// tkj0m0_0_0_0_0_0 TeakJ [Many [0,0,0,0,0,0],One 0]
module tkj0m0_0_0_0_0_0 (i_0r, i_0a, i_1r, i_1a, i_2r, i_2a, i_3r, i_3a, i_4r, i_4a, i_5r, i_5a, o_0r, o_0a, reset);
input i_0r;
output i_0a;
input i_1r;
output i_1a;
input i_2r;
output i_2a;
input i_3r;
output i_3a;
input i_4r;
output i_4a;
input i_5r;
output i_5a;
output o_0r;
input o_0a;
input reset;
wire [1:0] simp01_0;
C3 I0 (simp01_0[0:0], i_0r, i_1r, i_2r);
C3 I1 (simp01_0[1:1], i_3r, i_4r, i_5r);
C2 I2 (o_0r, simp01_0[0:0], simp01_0[1:1]);
BUFF I3 (i_0a, o_0a);
BUFF I4 (i_1a, o_0a);
BUFF I5 (i_2a, o_0a);
BUFF I6 (i_3a, o_0a);
BUFF I7 (i_4a, o_0a);
BUFF I8 (i_5a, o_0a);
endmodule
// tkf32mo0w0_o0w32 TeakF [0,0] [One 32,Many [0,32]]
module tkf32mo0w0_o0w32 (i_0r0, i_0r1, i_0a, o_0r, o_0a, o_1r0, o_1r1, o_1a, reset);
input [31:0] i_0r0;
input [31:0] i_0r1;
output i_0a;
output o_0r;
input o_0a;
output [31:0] o_1r0;
output [31:0] o_1r1;
input o_1a;
input reset;
wire acomplete_0;
wire icomplete_0;
OR2 I0 (icomplete_0, i_0r0[0:0], i_0r1[0:0]);
BUFF I1 (acomplete_0, icomplete_0);
BUFF I2 (o_1r0[0:0], i_0r0[0:0]);
BUFF I3 (o_1r0[1:1], i_0r0[1:1]);
BUFF I4 (o_1r0[2:2], i_0r0[2:2]);
BUFF I5 (o_1r0[3:3], i_0r0[3:3]);
BUFF I6 (o_1r0[4:4], i_0r0[4:4]);
BUFF I7 (o_1r0[5:5], i_0r0[5:5]);
BUFF I8 (o_1r0[6:6], i_0r0[6:6]);
BUFF I9 (o_1r0[7:7], i_0r0[7:7]);
BUFF I10 (o_1r0[8:8], i_0r0[8:8]);
BUFF I11 (o_1r0[9:9], i_0r0[9:9]);
BUFF I12 (o_1r0[10:10], i_0r0[10:10]);
BUFF I13 (o_1r0[11:11], i_0r0[11:11]);
BUFF I14 (o_1r0[12:12], i_0r0[12:12]);
BUFF I15 (o_1r0[13:13], i_0r0[13:13]);
BUFF I16 (o_1r0[14:14], i_0r0[14:14]);
BUFF I17 (o_1r0[15:15], i_0r0[15:15]);
BUFF I18 (o_1r0[16:16], i_0r0[16:16]);
BUFF I19 (o_1r0[17:17], i_0r0[17:17]);
BUFF I20 (o_1r0[18:18], i_0r0[18:18]);
BUFF I21 (o_1r0[19:19], i_0r0[19:19]);
BUFF I22 (o_1r0[20:20], i_0r0[20:20]);
BUFF I23 (o_1r0[21:21], i_0r0[21:21]);
BUFF I24 (o_1r0[22:22], i_0r0[22:22]);
BUFF I25 (o_1r0[23:23], i_0r0[23:23]);
BUFF I26 (o_1r0[24:24], i_0r0[24:24]);
BUFF I27 (o_1r0[25:25], i_0r0[25:25]);
BUFF I28 (o_1r0[26:26], i_0r0[26:26]);
BUFF I29 (o_1r0[27:27], i_0r0[27:27]);
BUFF I30 (o_1r0[28:28], i_0r0[28:28]);
BUFF I31 (o_1r0[29:29], i_0r0[29:29]);
BUFF I32 (o_1r0[30:30], i_0r0[30:30]);
BUFF I33 (o_1r0[31:31], i_0r0[31:31]);
BUFF I34 (o_1r1[0:0], i_0r1[0:0]);
BUFF I35 (o_1r1[1:1], i_0r1[1:1]);
BUFF I36 (o_1r1[2:2], i_0r1[2:2]);
BUFF I37 (o_1r1[3:3], i_0r1[3:3]);
BUFF I38 (o_1r1[4:4], i_0r1[4:4]);
BUFF I39 (o_1r1[5:5], i_0r1[5:5]);
BUFF I40 (o_1r1[6:6], i_0r1[6:6]);
BUFF I41 (o_1r1[7:7], i_0r1[7:7]);
BUFF I42 (o_1r1[8:8], i_0r1[8:8]);
BUFF I43 (o_1r1[9:9], i_0r1[9:9]);
BUFF I44 (o_1r1[10:10], i_0r1[10:10]);
BUFF I45 (o_1r1[11:11], i_0r1[11:11]);
BUFF I46 (o_1r1[12:12], i_0r1[12:12]);
BUFF I47 (o_1r1[13:13], i_0r1[13:13]);
BUFF I48 (o_1r1[14:14], i_0r1[14:14]);
BUFF I49 (o_1r1[15:15], i_0r1[15:15]);
BUFF I50 (o_1r1[16:16], i_0r1[16:16]);
BUFF I51 (o_1r1[17:17], i_0r1[17:17]);
BUFF I52 (o_1r1[18:18], i_0r1[18:18]);
BUFF I53 (o_1r1[19:19], i_0r1[19:19]);
BUFF I54 (o_1r1[20:20], i_0r1[20:20]);
BUFF I55 (o_1r1[21:21], i_0r1[21:21]);
BUFF I56 (o_1r1[22:22], i_0r1[22:22]);
BUFF I57 (o_1r1[23:23], i_0r1[23:23]);
BUFF I58 (o_1r1[24:24], i_0r1[24:24]);
BUFF I59 (o_1r1[25:25], i_0r1[25:25]);
BUFF I60 (o_1r1[26:26], i_0r1[26:26]);
BUFF I61 (o_1r1[27:27], i_0r1[27:27]);
BUFF I62 (o_1r1[28:28], i_0r1[28:28]);
BUFF I63 (o_1r1[29:29], i_0r1[29:29]);
BUFF I64 (o_1r1[30:30], i_0r1[30:30]);
BUFF I65 (o_1r1[31:31], i_0r1[31:31]);
BUFF I66 (o_0r, icomplete_0);
C3 I67 (i_0a, acomplete_0, o_0a, o_1a);
endmodule
// tkj7m5_2_0 TeakJ [Many [5,2,0],One 7]
module tkj7m5_2_0 (i_0r0, i_0r1, i_0a, i_1r0, i_1r1, i_1a, i_2r, i_2a, o_0r0, o_0r1, o_0a, reset);
input [4:0] i_0r0;
input [4:0] i_0r1;
output i_0a;
input [1:0] i_1r0;
input [1:0] i_1r1;
output i_1a;
input i_2r;
output i_2a;
output [6:0] o_0r0;
output [6:0] o_0r1;
input o_0a;
input reset;
wire icomplete_0;
wire [6:0] joinf_0;
wire [6:0] joint_0;
wire dcomplete_0;
BUFF I0 (joinf_0[0:0], i_0r0[0:0]);
BUFF I1 (joinf_0[1:1], i_0r0[1:1]);
BUFF I2 (joinf_0[2:2], i_0r0[2:2]);
BUFF I3 (joinf_0[3:3], i_0r0[3:3]);
BUFF I4 (joinf_0[4:4], i_0r0[4:4]);
BUFF I5 (joinf_0[5:5], i_1r0[0:0]);
BUFF I6 (joinf_0[6:6], i_1r0[1:1]);
BUFF I7 (joint_0[0:0], i_0r1[0:0]);
BUFF I8 (joint_0[1:1], i_0r1[1:1]);
BUFF I9 (joint_0[2:2], i_0r1[2:2]);
BUFF I10 (joint_0[3:3], i_0r1[3:3]);
BUFF I11 (joint_0[4:4], i_0r1[4:4]);
BUFF I12 (joint_0[5:5], i_1r1[0:0]);
BUFF I13 (joint_0[6:6], i_1r1[1:1]);
OR2 I14 (dcomplete_0, i_1r0[0:0], i_1r1[0:0]);
C2 I15 (icomplete_0, i_2r, dcomplete_0);
C2 I16 (o_0r0[0:0], joinf_0[0:0], icomplete_0);
C2 I17 (o_0r1[0:0], joint_0[0:0], icomplete_0);
BUFF I18 (o_0r0[1:1], joinf_0[1:1]);
BUFF I19 (o_0r0[2:2], joinf_0[2:2]);
BUFF I20 (o_0r0[3:3], joinf_0[3:3]);
BUFF I21 (o_0r0[4:4], joinf_0[4:4]);
BUFF I22 (o_0r0[5:5], joinf_0[5:5]);
BUFF I23 (o_0r0[6:6], joinf_0[6:6]);
BUFF I24 (o_0r1[1:1], joint_0[1:1]);
BUFF I25 (o_0r1[2:2], joint_0[2:2]);
BUFF I26 (o_0r1[3:3], joint_0[3:3]);
BUFF I27 (o_0r1[4:4], joint_0[4:4]);
BUFF I28 (o_0r1[5:5], joint_0[5:5]);
BUFF I29 (o_0r1[6:6], joint_0[6:6]);
BUFF I30 (i_0a, o_0a);
BUFF I31 (i_1a, o_0a);
BUFF I32 (i_2a, o_0a);
endmodule
// tkvdistanceIshift7_wo0w7_ro5w2o5w2o5w2o5w2o5w2 TeakV "distanceI-shift" 7 [] [0] [5,5,5,5,5] [Many [7
// ],Many [0],Many [0,0,0,0,0],Many [2,2,2,2,2]]
module tkvdistanceIshift7_wo0w7_ro5w2o5w2o5w2o5w2o5w2 (wg_0r0, wg_0r1, wg_0a, wd_0r, wd_0a, rg_0r, rg_0a, rg_1r, rg_1a, rg_2r, rg_2a, rg_3r, rg_3a, rg_4r, rg_4a, rd_0r0, rd_0r1, rd_0a, rd_1r0, rd_1r1, rd_1a, rd_2r0, rd_2r1, rd_2a, rd_3r0, rd_3r1, rd_3a, rd_4r0, rd_4r1, rd_4a, reset);
input [6:0] wg_0r0;
input [6:0] wg_0r1;
output wg_0a;
output wd_0r;
input wd_0a;
input rg_0r;
output rg_0a;
input rg_1r;
output rg_1a;
input rg_2r;
output rg_2a;
input rg_3r;
output rg_3a;
input rg_4r;
output rg_4a;
output [1:0] rd_0r0;
output [1:0] rd_0r1;
input rd_0a;
output [1:0] rd_1r0;
output [1:0] rd_1r1;
input rd_1a;
output [1:0] rd_2r0;
output [1:0] rd_2r1;
input rd_2a;
output [1:0] rd_3r0;
output [1:0] rd_3r1;
input rd_3a;
output [1:0] rd_4r0;
output [1:0] rd_4r1;
input rd_4a;
input reset;
wire [6:0] wf_0;
wire [6:0] wt_0;
wire [6:0] df_0;
wire [6:0] dt_0;
wire wc_0;
wire [6:0] wacks_0;
wire [6:0] wenr_0;
wire [6:0] wen_0;
wire anyread_0;
wire nreset_0;
wire [6:0] drlgf_0;
wire [6:0] drlgt_0;
wire [6:0] comp0_0;
wire [2:0] simp631_0;
wire conwigc_0;
wire conwigcanw_0;
wire [6:0] conwgit_0;
wire [6:0] conwgif_0;
wire conwig_0;
wire [2:0] simp1071_0;
wire [3:0] simp1281_0;
wire [1:0] simp1282_0;
INV I0 (nreset_0, reset);
AND2 I1 (wen_0[0:0], wenr_0[0:0], nreset_0);
AND2 I2 (wen_0[1:1], wenr_0[1:1], nreset_0);
AND2 I3 (wen_0[2:2], wenr_0[2:2], nreset_0);
AND2 I4 (wen_0[3:3], wenr_0[3:3], nreset_0);
AND2 I5 (wen_0[4:4], wenr_0[4:4], nreset_0);
AND2 I6 (wen_0[5:5], wenr_0[5:5], nreset_0);
AND2 I7 (wen_0[6:6], wenr_0[6:6], nreset_0);
AND2 I8 (drlgf_0[0:0], wf_0[0:0], wen_0[0:0]);
AND2 I9 (drlgf_0[1:1], wf_0[1:1], wen_0[1:1]);
AND2 I10 (drlgf_0[2:2], wf_0[2:2], wen_0[2:2]);
AND2 I11 (drlgf_0[3:3], wf_0[3:3], wen_0[3:3]);
AND2 I12 (drlgf_0[4:4], wf_0[4:4], wen_0[4:4]);
AND2 I13 (drlgf_0[5:5], wf_0[5:5], wen_0[5:5]);
AND2 I14 (drlgf_0[6:6], wf_0[6:6], wen_0[6:6]);
AND2 I15 (drlgt_0[0:0], wt_0[0:0], wen_0[0:0]);
AND2 I16 (drlgt_0[1:1], wt_0[1:1], wen_0[1:1]);
AND2 I17 (drlgt_0[2:2], wt_0[2:2], wen_0[2:2]);
AND2 I18 (drlgt_0[3:3], wt_0[3:3], wen_0[3:3]);
AND2 I19 (drlgt_0[4:4], wt_0[4:4], wen_0[4:4]);
AND2 I20 (drlgt_0[5:5], wt_0[5:5], wen_0[5:5]);
AND2 I21 (drlgt_0[6:6], wt_0[6:6], wen_0[6:6]);
NOR2 I22 (df_0[0:0], dt_0[0:0], drlgt_0[0:0]);
NOR2 I23 (df_0[1:1], dt_0[1:1], drlgt_0[1:1]);
NOR2 I24 (df_0[2:2], dt_0[2:2], drlgt_0[2:2]);
NOR2 I25 (df_0[3:3], dt_0[3:3], drlgt_0[3:3]);
NOR2 I26 (df_0[4:4], dt_0[4:4], drlgt_0[4:4]);
NOR2 I27 (df_0[5:5], dt_0[5:5], drlgt_0[5:5]);
NOR2 I28 (df_0[6:6], dt_0[6:6], drlgt_0[6:6]);
NOR3 I29 (dt_0[0:0], df_0[0:0], drlgf_0[0:0], reset);
NOR3 I30 (dt_0[1:1], df_0[1:1], drlgf_0[1:1], reset);
NOR3 I31 (dt_0[2:2], df_0[2:2], drlgf_0[2:2], reset);
NOR3 I32 (dt_0[3:3], df_0[3:3], drlgf_0[3:3], reset);
NOR3 I33 (dt_0[4:4], df_0[4:4], drlgf_0[4:4], reset);
NOR3 I34 (dt_0[5:5], df_0[5:5], drlgf_0[5:5], reset);
NOR3 I35 (dt_0[6:6], df_0[6:6], drlgf_0[6:6], reset);
AO22 I36 (wacks_0[0:0], drlgf_0[0:0], df_0[0:0], drlgt_0[0:0], dt_0[0:0]);
AO22 I37 (wacks_0[1:1], drlgf_0[1:1], df_0[1:1], drlgt_0[1:1], dt_0[1:1]);
AO22 I38 (wacks_0[2:2], drlgf_0[2:2], df_0[2:2], drlgt_0[2:2], dt_0[2:2]);
AO22 I39 (wacks_0[3:3], drlgf_0[3:3], df_0[3:3], drlgt_0[3:3], dt_0[3:3]);
AO22 I40 (wacks_0[4:4], drlgf_0[4:4], df_0[4:4], drlgt_0[4:4], dt_0[4:4]);
AO22 I41 (wacks_0[5:5], drlgf_0[5:5], df_0[5:5], drlgt_0[5:5], dt_0[5:5]);
AO22 I42 (wacks_0[6:6], drlgf_0[6:6], df_0[6:6], drlgt_0[6:6], dt_0[6:6]);
OR2 I43 (comp0_0[0:0], wg_0r0[0:0], wg_0r1[0:0]);
OR2 I44 (comp0_0[1:1], wg_0r0[1:1], wg_0r1[1:1]);
OR2 I45 (comp0_0[2:2], wg_0r0[2:2], wg_0r1[2:2]);
OR2 I46 (comp0_0[3:3], wg_0r0[3:3], wg_0r1[3:3]);
OR2 I47 (comp0_0[4:4], wg_0r0[4:4], wg_0r1[4:4]);
OR2 I48 (comp0_0[5:5], wg_0r0[5:5], wg_0r1[5:5]);
OR2 I49 (comp0_0[6:6], wg_0r0[6:6], wg_0r1[6:6]);
C3 I50 (simp631_0[0:0], comp0_0[0:0], comp0_0[1:1], comp0_0[2:2]);
C3 I51 (simp631_0[1:1], comp0_0[3:3], comp0_0[4:4], comp0_0[5:5]);
BUFF I52 (simp631_0[2:2], comp0_0[6:6]);
C3 I53 (wc_0, simp631_0[0:0], simp631_0[1:1], simp631_0[2:2]);
AND2 I54 (conwgif_0[0:0], wg_0r0[0:0], conwig_0);
AND2 I55 (conwgif_0[1:1], wg_0r0[1:1], conwig_0);
AND2 I56 (conwgif_0[2:2], wg_0r0[2:2], conwig_0);
AND2 I57 (conwgif_0[3:3], wg_0r0[3:3], conwig_0);
AND2 I58 (conwgif_0[4:4], wg_0r0[4:4], conwig_0);
AND2 I59 (conwgif_0[5:5], wg_0r0[5:5], conwig_0);
AND2 I60 (conwgif_0[6:6], wg_0r0[6:6], conwig_0);
AND2 I61 (conwgit_0[0:0], wg_0r1[0:0], conwig_0);
AND2 I62 (conwgit_0[1:1], wg_0r1[1:1], conwig_0);
AND2 I63 (conwgit_0[2:2], wg_0r1[2:2], conwig_0);
AND2 I64 (conwgit_0[3:3], wg_0r1[3:3], conwig_0);
AND2 I65 (conwgit_0[4:4], wg_0r1[4:4], conwig_0);
AND2 I66 (conwgit_0[5:5], wg_0r1[5:5], conwig_0);
AND2 I67 (conwgit_0[6:6], wg_0r1[6:6], conwig_0);
BUFF I68 (conwigc_0, wc_0);
AO22 I69 (conwig_0, conwigc_0, conwigcanw_0, conwigc_0, conwig_0);
NOR2 I70 (conwigcanw_0, anyread_0, conwig_0);
BUFF I71 (wf_0[0:0], conwgif_0[0:0]);
BUFF I72 (wt_0[0:0], conwgit_0[0:0]);
BUFF I73 (wenr_0[0:0], wc_0);
BUFF I74 (wf_0[1:1], conwgif_0[1:1]);
BUFF I75 (wt_0[1:1], conwgit_0[1:1]);
BUFF I76 (wenr_0[1:1], wc_0);
BUFF I77 (wf_0[2:2], conwgif_0[2:2]);
BUFF I78 (wt_0[2:2], conwgit_0[2:2]);
BUFF I79 (wenr_0[2:2], wc_0);
BUFF I80 (wf_0[3:3], conwgif_0[3:3]);
BUFF I81 (wt_0[3:3], conwgit_0[3:3]);
BUFF I82 (wenr_0[3:3], wc_0);
BUFF I83 (wf_0[4:4], conwgif_0[4:4]);
BUFF I84 (wt_0[4:4], conwgit_0[4:4]);
BUFF I85 (wenr_0[4:4], wc_0);
BUFF I86 (wf_0[5:5], conwgif_0[5:5]);
BUFF I87 (wt_0[5:5], conwgit_0[5:5]);
BUFF I88 (wenr_0[5:5], wc_0);
BUFF I89 (wf_0[6:6], conwgif_0[6:6]);
BUFF I90 (wt_0[6:6], conwgit_0[6:6]);
BUFF I91 (wenr_0[6:6], wc_0);
C3 I92 (simp1071_0[0:0], conwig_0, wacks_0[0:0], wacks_0[1:1]);
C3 I93 (simp1071_0[1:1], wacks_0[2:2], wacks_0[3:3], wacks_0[4:4]);
C2 I94 (simp1071_0[2:2], wacks_0[5:5], wacks_0[6:6]);
C3 I95 (wd_0r, simp1071_0[0:0], simp1071_0[1:1], simp1071_0[2:2]);
AND2 I96 (rd_0r0[0:0], df_0[5:5], rg_0r);
AND2 I97 (rd_0r0[1:1], df_0[6:6], rg_0r);
AND2 I98 (rd_1r0[0:0], df_0[5:5], rg_1r);
AND2 I99 (rd_1r0[1:1], df_0[6:6], rg_1r);
AND2 I100 (rd_2r0[0:0], df_0[5:5], rg_2r);
AND2 I101 (rd_2r0[1:1], df_0[6:6], rg_2r);
AND2 I102 (rd_3r0[0:0], df_0[5:5], rg_3r);
AND2 I103 (rd_3r0[1:1], df_0[6:6], rg_3r);
AND2 I104 (rd_4r0[0:0], df_0[5:5], rg_4r);
AND2 I105 (rd_4r0[1:1], df_0[6:6], rg_4r);
AND2 I106 (rd_0r1[0:0], dt_0[5:5], rg_0r);
AND2 I107 (rd_0r1[1:1], dt_0[6:6], rg_0r);
AND2 I108 (rd_1r1[0:0], dt_0[5:5], rg_1r);
AND2 I109 (rd_1r1[1:1], dt_0[6:6], rg_1r);
AND2 I110 (rd_2r1[0:0], dt_0[5:5], rg_2r);
AND2 I111 (rd_2r1[1:1], dt_0[6:6], rg_2r);
AND2 I112 (rd_3r1[0:0], dt_0[5:5], rg_3r);
AND2 I113 (rd_3r1[1:1], dt_0[6:6], rg_3r);
AND2 I114 (rd_4r1[0:0], dt_0[5:5], rg_4r);
AND2 I115 (rd_4r1[1:1], dt_0[6:6], rg_4r);
NOR3 I116 (simp1281_0[0:0], rg_0r, rg_1r, rg_2r);
NOR3 I117 (simp1281_0[1:1], rg_3r, rg_4r, rg_0a);
NOR3 I118 (simp1281_0[2:2], rg_1a, rg_2a, rg_3a);
INV I119 (simp1281_0[3:3], rg_4a);
NAND3 I120 (simp1282_0[0:0], simp1281_0[0:0], simp1281_0[1:1], simp1281_0[2:2]);
INV I121 (simp1282_0[1:1], simp1281_0[3:3]);
OR2 I122 (anyread_0, simp1282_0[0:0], simp1282_0[1:1]);
BUFF I123 (wg_0a, wd_0a);
BUFF I124 (rg_0a, rd_0a);
BUFF I125 (rg_1a, rd_1a);
BUFF I126 (rg_2a, rd_2a);
BUFF I127 (rg_3a, rd_3a);
BUFF I128 (rg_4a, rd_4a);
endmodule
// tkf7mo0w7_o4w1_o3w1_o2w1_o1w1_o0w1 TeakF [0,4,3,2,1,0] [One 7,Many [7,1,1,1,1,1]]
module tkf7mo0w7_o4w1_o3w1_o2w1_o1w1_o0w1 (i_0r0, i_0r1, i_0a, o_0r0, o_0r1, o_0a, o_1r0, o_1r1, o_1a, o_2r0, o_2r1, o_2a, o_3r0, o_3r1, o_3a, o_4r0, o_4r1, o_4a, o_5r0, o_5r1, o_5a, reset);
input [6:0] i_0r0;
input [6:0] i_0r1;
output i_0a;
output [6:0] o_0r0;
output [6:0] o_0r1;
input o_0a;
output o_1r0;
output o_1r1;
input o_1a;
output o_2r0;
output o_2r1;
input o_2a;
output o_3r0;
output o_3r1;
input o_3a;
output o_4r0;
output o_4r1;
input o_4a;
output o_5r0;
output o_5r1;
input o_5a;
input reset;
wire acomplete_0;
wire icomplete_0;
wire [2:0] simp291_0;
OR2 I0 (icomplete_0, i_0r0[0:0], i_0r1[0:0]);
BUFF I1 (acomplete_0, icomplete_0);
BUFF I2 (o_0r0[0:0], i_0r0[0:0]);
BUFF I3 (o_0r0[1:1], i_0r0[1:1]);
BUFF I4 (o_0r0[2:2], i_0r0[2:2]);
BUFF I5 (o_0r0[3:3], i_0r0[3:3]);
BUFF I6 (o_0r0[4:4], i_0r0[4:4]);
BUFF I7 (o_0r0[5:5], i_0r0[5:5]);
BUFF I8 (o_0r0[6:6], i_0r0[6:6]);
C2 I9 (o_1r0, i_0r0[4:4], icomplete_0);
C2 I10 (o_2r0, i_0r0[3:3], icomplete_0);
C2 I11 (o_3r0, i_0r0[2:2], icomplete_0);
C2 I12 (o_4r0, i_0r0[1:1], icomplete_0);
C2 I13 (o_5r0, i_0r0[0:0], icomplete_0);
BUFF I14 (o_0r1[0:0], i_0r1[0:0]);
BUFF I15 (o_0r1[1:1], i_0r1[1:1]);
BUFF I16 (o_0r1[2:2], i_0r1[2:2]);
BUFF I17 (o_0r1[3:3], i_0r1[3:3]);
BUFF I18 (o_0r1[4:4], i_0r1[4:4]);
BUFF I19 (o_0r1[5:5], i_0r1[5:5]);
BUFF I20 (o_0r1[6:6], i_0r1[6:6]);
C2 I21 (o_1r1, i_0r1[4:4], icomplete_0);
C2 I22 (o_2r1, i_0r1[3:3], icomplete_0);
C2 I23 (o_3r1, i_0r1[2:2], icomplete_0);
C2 I24 (o_4r1, i_0r1[1:1], icomplete_0);
C2 I25 (o_5r1, i_0r1[0:0], icomplete_0);
C3 I26 (simp291_0[0:0], acomplete_0, o_0a, o_1a);
C3 I27 (simp291_0[1:1], o_2a, o_3a, o_4a);
BUFF I28 (simp291_0[2:2], o_5a);
C3 I29 (i_0a, simp291_0[0:0], simp291_0[1:1], simp291_0[2:2]);
endmodule
// tkj1m1_0 TeakJ [Many [1,0],One 1]
module tkj1m1_0 (i_0r0, i_0r1, i_0a, i_1r, i_1a, o_0r0, o_0r1, o_0a, reset);
input i_0r0;
input i_0r1;
output i_0a;
input i_1r;
output i_1a;
output o_0r0;
output o_0r1;
input o_0a;
input reset;
wire icomplete_0;
wire joinf_0;
wire joint_0;
BUFF I0 (joinf_0, i_0r0);
BUFF I1 (joint_0, i_0r1);
BUFF I2 (icomplete_0, i_1r);
C2 I3 (o_0r0, joinf_0, icomplete_0);
C2 I4 (o_0r1, joint_0, icomplete_0);
BUFF I5 (i_0a, o_0a);
BUFF I6 (i_1a, o_0a);
endmodule
// tkf0mo0w0_o0w0_o0w0_o0w0_o0w0 TeakF [0,0,0,0,0] [One 0,Many [0,0,0,0,0]]
module tkf0mo0w0_o0w0_o0w0_o0w0_o0w0 (i_0r, i_0a, o_0r, o_0a, o_1r, o_1a, o_2r, o_2a, o_3r, o_3a, o_4r, o_4a, reset);
input i_0r;
output i_0a;
output o_0r;
input o_0a;
output o_1r;
input o_1a;
output o_2r;
input o_2a;
output o_3r;
input o_3a;
output o_4r;
input o_4a;
input reset;
wire [1:0] simp11_0;
BUFF I0 (o_0r, i_0r);
BUFF I1 (o_1r, i_0r);
BUFF I2 (o_2r, i_0r);
BUFF I3 (o_3r, i_0r);
BUFF I4 (o_4r, i_0r);
C3 I5 (simp11_0[0:0], o_0a, o_1a, o_2a);
C2 I6 (simp11_0[1:1], o_3a, o_4a);
C2 I7 (i_0a, simp11_0[0:0], simp11_0[1:1]);
endmodule
// tks2_o0w2_3o0w0_0c2o0w0_1o0w0 TeakS (0+:2) [([Imp 3 0],0),([Imp 0 2],0),([Imp 1 0],0)] [One 2,Many [
// 0,0,0]]
module tks2_o0w2_3o0w0_0c2o0w0_1o0w0 (i_0r0, i_0r1, i_0a, o_0r, o_0a, o_1r, o_1a, o_2r, o_2a, reset);
input [1:0] i_0r0;
input [1:0] i_0r1;
output i_0a;
output o_0r;
input o_0a;
output o_1r;
input o_1a;
output o_2r;
input o_2a;
input reset;
wire icomplete_0;
wire sel_0;
wire sel_1;
wire sel_2;
wire gsel_0;
wire gsel_1;
wire gsel_2;
wire oack_0;
wire match0_0;
wire match1_0;
wire match2_0;
wire [1:0] comp_0;
BUFF I0 (sel_0, match0_0);
C2 I1 (match0_0, i_0r1[0:0], i_0r1[1:1]);
BUFF I2 (sel_1, match1_0);
BUFF I3 (match1_0, i_0r0[0:0]);
BUFF I4 (sel_2, match2_0);
C2 I5 (match2_0, i_0r1[0:0], i_0r0[1:1]);
C2 I6 (gsel_0, sel_0, icomplete_0);
C2 I7 (gsel_1, sel_1, icomplete_0);
C2 I8 (gsel_2, sel_2, icomplete_0);
OR2 I9 (comp_0[0:0], i_0r0[0:0], i_0r1[0:0]);
OR2 I10 (comp_0[1:1], i_0r0[1:1], i_0r1[1:1]);
C2 I11 (icomplete_0, comp_0[0:0], comp_0[1:1]);
BUFF I12 (o_0r, gsel_0);
BUFF I13 (o_1r, gsel_1);
BUFF I14 (o_2r, gsel_2);
OR3 I15 (oack_0, o_0a, o_1a, o_2a);
C2 I16 (i_0a, oack_0, icomplete_0);
endmodule
// tkf1mo0w1_o0w0 TeakF [0,0] [One 1,Many [1,0]]
module tkf1mo0w1_o0w0 (i_0r0, i_0r1, i_0a, o_0r0, o_0r1, o_0a, o_1r, o_1a, reset);
input i_0r0;
input i_0r1;
output i_0a;
output o_0r0;
output o_0r1;
input o_0a;
output o_1r;
input o_1a;
input reset;
wire acomplete_0;
wire icomplete_0;
OR2 I0 (icomplete_0, i_0r0, i_0r1);
BUFF I1 (acomplete_0, icomplete_0);
BUFF I2 (o_0r0, i_0r0);
BUFF I3 (o_0r1, i_0r1);
BUFF I4 (o_1r, icomplete_0);
C3 I5 (i_0a, acomplete_0, o_0a, o_1a);
endmodule
// tks1_o0w1_0o0w0_1o0w0 TeakS (0+:1) [([Imp 0 0],0),([Imp 1 0],0)] [One 1,Many [0,0]]
module tks1_o0w1_0o0w0_1o0w0 (i_0r0, i_0r1, i_0a, o_0r, o_0a, o_1r, o_1a, reset);
input i_0r0;
input i_0r1;
output i_0a;
output o_0r;
input o_0a;
output o_1r;
input o_1a;
input reset;
wire icomplete_0;
wire sel_0;
wire sel_1;
wire gsel_0;
wire gsel_1;
wire oack_0;
wire match0_0;
wire match1_0;
wire comp_0;
BUFF I0 (sel_0, match0_0);
BUFF I1 (match0_0, i_0r0);
BUFF I2 (sel_1, match1_0);
BUFF I3 (match1_0, i_0r1);
C2 I4 (gsel_0, sel_0, icomplete_0);
C2 I5 (gsel_1, sel_1, icomplete_0);
OR2 I6 (comp_0, i_0r0, i_0r1);
BUFF I7 (icomplete_0, comp_0);
BUFF I8 (o_0r, gsel_0);
BUFF I9 (o_1r, gsel_1);
OR2 I10 (oack_0, o_0a, o_1a);
C2 I11 (i_0a, oack_0, icomplete_0);
endmodule
// tki TeakI [One 0,One 0]
module tki (i_0r, i_0a, o_0r, o_0a, reset);
input i_0r;
output i_0a;
output o_0r;
input o_0a;
input reset;
wire nreset_0;
wire firsthsa_0;
wire nfirsthsa_0;
wire firsthsd_0;
wire noa_0;
INV I0 (nreset_0, reset);
INV I1 (nfirsthsa_0, firsthsa_0);
INV I2 (noa_0, o_0a);
AO22 I3 (o_0r, nreset_0, nfirsthsa_0, i_0r, firsthsd_0);
AO22 I4 (firsthsa_0, nreset_0, o_0a, nreset_0, firsthsa_0);
AO22 I5 (firsthsd_0, firsthsa_0, noa_0, firsthsa_0, firsthsd_0);
AND2 I6 (i_0a, o_0a, firsthsd_0);
endmodule
// latch tkl0x1 width = 0, depth = 1
module tkl0x1 (i_0r, i_0a, o_0r, o_0a, reset);
input i_0r;
output i_0a;
output o_0r;
input o_0a;
input reset;
wire b_0;
C2R I0 (o_0r, i_0r, b_0, reset);
INV I1 (b_0, o_0a);
BUFF I2 (i_0a, o_0r);
endmodule
// latch tkl32x1 width = 32, depth = 1
module tkl32x1 (i_0r0, i_0r1, i_0a, o_0r0, o_0r1, o_0a, reset);
input [31:0] i_0r0;
input [31:0] i_0r1;
output i_0a;
output [31:0] o_0r0;
output [31:0] o_0r1;
input o_0a;
input reset;
wire bna_0;
wire [31:0] bcomp_0;
wire [10:0] simp991_0;
wire [3:0] simp992_0;
wire [1:0] simp993_0;
C2R I0 (o_0r0[0:0], i_0r0[0:0], bna_0, reset);
C2R I1 (o_0r0[1:1], i_0r0[1:1], bna_0, reset);
C2R I2 (o_0r0[2:2], i_0r0[2:2], bna_0, reset);
C2R I3 (o_0r0[3:3], i_0r0[3:3], bna_0, reset);
C2R I4 (o_0r0[4:4], i_0r0[4:4], bna_0, reset);
C2R I5 (o_0r0[5:5], i_0r0[5:5], bna_0, reset);
C2R I6 (o_0r0[6:6], i_0r0[6:6], bna_0, reset);
C2R I7 (o_0r0[7:7], i_0r0[7:7], bna_0, reset);
C2R I8 (o_0r0[8:8], i_0r0[8:8], bna_0, reset);
C2R I9 (o_0r0[9:9], i_0r0[9:9], bna_0, reset);
C2R I10 (o_0r0[10:10], i_0r0[10:10], bna_0, reset);
C2R I11 (o_0r0[11:11], i_0r0[11:11], bna_0, reset);
C2R I12 (o_0r0[12:12], i_0r0[12:12], bna_0, reset);
C2R I13 (o_0r0[13:13], i_0r0[13:13], bna_0, reset);
C2R I14 (o_0r0[14:14], i_0r0[14:14], bna_0, reset);
C2R I15 (o_0r0[15:15], i_0r0[15:15], bna_0, reset);
C2R I16 (o_0r0[16:16], i_0r0[16:16], bna_0, reset);
C2R I17 (o_0r0[17:17], i_0r0[17:17], bna_0, reset);
C2R I18 (o_0r0[18:18], i_0r0[18:18], bna_0, reset);
C2R I19 (o_0r0[19:19], i_0r0[19:19], bna_0, reset);
C2R I20 (o_0r0[20:20], i_0r0[20:20], bna_0, reset);
C2R I21 (o_0r0[21:21], i_0r0[21:21], bna_0, reset);
C2R I22 (o_0r0[22:22], i_0r0[22:22], bna_0, reset);
C2R I23 (o_0r0[23:23], i_0r0[23:23], bna_0, reset);
C2R I24 (o_0r0[24:24], i_0r0[24:24], bna_0, reset);
C2R I25 (o_0r0[25:25], i_0r0[25:25], bna_0, reset);
C2R I26 (o_0r0[26:26], i_0r0[26:26], bna_0, reset);
C2R I27 (o_0r0[27:27], i_0r0[27:27], bna_0, reset);
C2R I28 (o_0r0[28:28], i_0r0[28:28], bna_0, reset);
C2R I29 (o_0r0[29:29], i_0r0[29:29], bna_0, reset);
C2R I30 (o_0r0[30:30], i_0r0[30:30], bna_0, reset);
C2R I31 (o_0r0[31:31], i_0r0[31:31], bna_0, reset);
C2R I32 (o_0r1[0:0], i_0r1[0:0], bna_0, reset);
C2R I33 (o_0r1[1:1], i_0r1[1:1], bna_0, reset);
C2R I34 (o_0r1[2:2], i_0r1[2:2], bna_0, reset);
C2R I35 (o_0r1[3:3], i_0r1[3:3], bna_0, reset);
C2R I36 (o_0r1[4:4], i_0r1[4:4], bna_0, reset);
C2R I37 (o_0r1[5:5], i_0r1[5:5], bna_0, reset);
C2R I38 (o_0r1[6:6], i_0r1[6:6], bna_0, reset);
C2R I39 (o_0r1[7:7], i_0r1[7:7], bna_0, reset);
C2R I40 (o_0r1[8:8], i_0r1[8:8], bna_0, reset);
C2R I41 (o_0r1[9:9], i_0r1[9:9], bna_0, reset);
C2R I42 (o_0r1[10:10], i_0r1[10:10], bna_0, reset);
C2R I43 (o_0r1[11:11], i_0r1[11:11], bna_0, reset);
C2R I44 (o_0r1[12:12], i_0r1[12:12], bna_0, reset);
C2R I45 (o_0r1[13:13], i_0r1[13:13], bna_0, reset);
C2R I46 (o_0r1[14:14], i_0r1[14:14], bna_0, reset);
C2R I47 (o_0r1[15:15], i_0r1[15:15], bna_0, reset);
C2R I48 (o_0r1[16:16], i_0r1[16:16], bna_0, reset);
C2R I49 (o_0r1[17:17], i_0r1[17:17], bna_0, reset);
C2R I50 (o_0r1[18:18], i_0r1[18:18], bna_0, reset);
C2R I51 (o_0r1[19:19], i_0r1[19:19], bna_0, reset);
C2R I52 (o_0r1[20:20], i_0r1[20:20], bna_0, reset);
C2R I53 (o_0r1[21:21], i_0r1[21:21], bna_0, reset);
C2R I54 (o_0r1[22:22], i_0r1[22:22], bna_0, reset);
C2R I55 (o_0r1[23:23], i_0r1[23:23], bna_0, reset);
C2R I56 (o_0r1[24:24], i_0r1[24:24], bna_0, reset);
C2R I57 (o_0r1[25:25], i_0r1[25:25], bna_0, reset);
C2R I58 (o_0r1[26:26], i_0r1[26:26], bna_0, reset);
C2R I59 (o_0r1[27:27], i_0r1[27:27], bna_0, reset);
C2R I60 (o_0r1[28:28], i_0r1[28:28], bna_0, reset);
C2R I61 (o_0r1[29:29], i_0r1[29:29], bna_0, reset);
C2R I62 (o_0r1[30:30], i_0r1[30:30], bna_0, reset);
C2R I63 (o_0r1[31:31], i_0r1[31:31], bna_0, reset);
INV I64 (bna_0, o_0a);
OR2 I65 (bcomp_0[0:0], o_0r0[0:0], o_0r1[0:0]);
OR2 I66 (bcomp_0[1:1], o_0r0[1:1], o_0r1[1:1]);
OR2 I67 (bcomp_0[2:2], o_0r0[2:2], o_0r1[2:2]);
OR2 I68 (bcomp_0[3:3], o_0r0[3:3], o_0r1[3:3]);
OR2 I69 (bcomp_0[4:4], o_0r0[4:4], o_0r1[4:4]);
OR2 I70 (bcomp_0[5:5], o_0r0[5:5], o_0r1[5:5]);
OR2 I71 (bcomp_0[6:6], o_0r0[6:6], o_0r1[6:6]);
OR2 I72 (bcomp_0[7:7], o_0r0[7:7], o_0r1[7:7]);
OR2 I73 (bcomp_0[8:8], o_0r0[8:8], o_0r1[8:8]);
OR2 I74 (bcomp_0[9:9], o_0r0[9:9], o_0r1[9:9]);
OR2 I75 (bcomp_0[10:10], o_0r0[10:10], o_0r1[10:10]);
OR2 I76 (bcomp_0[11:11], o_0r0[11:11], o_0r1[11:11]);
OR2 I77 (bcomp_0[12:12], o_0r0[12:12], o_0r1[12:12]);
OR2 I78 (bcomp_0[13:13], o_0r0[13:13], o_0r1[13:13]);
OR2 I79 (bcomp_0[14:14], o_0r0[14:14], o_0r1[14:14]);
OR2 I80 (bcomp_0[15:15], o_0r0[15:15], o_0r1[15:15]);
OR2 I81 (bcomp_0[16:16], o_0r0[16:16], o_0r1[16:16]);
OR2 I82 (bcomp_0[17:17], o_0r0[17:17], o_0r1[17:17]);
OR2 I83 (bcomp_0[18:18], o_0r0[18:18], o_0r1[18:18]);
OR2 I84 (bcomp_0[19:19], o_0r0[19:19], o_0r1[19:19]);
OR2 I85 (bcomp_0[20:20], o_0r0[20:20], o_0r1[20:20]);
OR2 I86 (bcomp_0[21:21], o_0r0[21:21], o_0r1[21:21]);
OR2 I87 (bcomp_0[22:22], o_0r0[22:22], o_0r1[22:22]);
OR2 I88 (bcomp_0[23:23], o_0r0[23:23], o_0r1[23:23]);
OR2 I89 (bcomp_0[24:24], o_0r0[24:24], o_0r1[24:24]);
OR2 I90 (bcomp_0[25:25], o_0r0[25:25], o_0r1[25:25]);
OR2 I91 (bcomp_0[26:26], o_0r0[26:26], o_0r1[26:26]);
OR2 I92 (bcomp_0[27:27], o_0r0[27:27], o_0r1[27:27]);
OR2 I93 (bcomp_0[28:28], o_0r0[28:28], o_0r1[28:28]);
OR2 I94 (bcomp_0[29:29], o_0r0[29:29], o_0r1[29:29]);
OR2 I95 (bcomp_0[30:30], o_0r0[30:30], o_0r1[30:30]);
OR2 I96 (bcomp_0[31:31], o_0r0[31:31], o_0r1[31:31]);
C3 I97 (simp991_0[0:0], bcomp_0[0:0], bcomp_0[1:1], bcomp_0[2:2]);
C3 I98 (simp991_0[1:1], bcomp_0[3:3], bcomp_0[4:4], bcomp_0[5:5]);
C3 I99 (simp991_0[2:2], bcomp_0[6:6], bcomp_0[7:7], bcomp_0[8:8]);
C3 I100 (simp991_0[3:3], bcomp_0[9:9], bcomp_0[10:10], bcomp_0[11:11]);
C3 I101 (simp991_0[4:4], bcomp_0[12:12], bcomp_0[13:13], bcomp_0[14:14]);
C3 I102 (simp991_0[5:5], bcomp_0[15:15], bcomp_0[16:16], bcomp_0[17:17]);
C3 I103 (simp991_0[6:6], bcomp_0[18:18], bcomp_0[19:19], bcomp_0[20:20]);
C3 I104 (simp991_0[7:7], bcomp_0[21:21], bcomp_0[22:22], bcomp_0[23:23]);
C3 I105 (simp991_0[8:8], bcomp_0[24:24], bcomp_0[25:25], bcomp_0[26:26]);
C3 I106 (simp991_0[9:9], bcomp_0[27:27], bcomp_0[28:28], bcomp_0[29:29]);
C2 I107 (simp991_0[10:10], bcomp_0[30:30], bcomp_0[31:31]);
C3 I108 (simp992_0[0:0], simp991_0[0:0], simp991_0[1:1], simp991_0[2:2]);
C3 I109 (simp992_0[1:1], simp991_0[3:3], simp991_0[4:4], simp991_0[5:5]);
C3 I110 (simp992_0[2:2], simp991_0[6:6], simp991_0[7:7], simp991_0[8:8]);
C2 I111 (simp992_0[3:3], simp991_0[9:9], simp991_0[10:10]);
C3 I112 (simp993_0[0:0], simp992_0[0:0], simp992_0[1:1], simp992_0[2:2]);
BUFF I113 (simp993_0[1:1], simp992_0[3:3]);
C2 I114 (i_0a, simp993_0[0:0], simp993_0[1:1]);
endmodule
// latch tkl2x1 width = 2, depth = 1
module tkl2x1 (i_0r0, i_0r1, i_0a, o_0r0, o_0r1, o_0a, reset);
input [1:0] i_0r0;
input [1:0] i_0r1;
output i_0a;
output [1:0] o_0r0;
output [1:0] o_0r1;
input o_0a;
input reset;
wire bna_0;
wire [1:0] bcomp_0;
C2R I0 (o_0r0[0:0], i_0r0[0:0], bna_0, reset);
C2R I1 (o_0r0[1:1], i_0r0[1:1], bna_0, reset);
C2R I2 (o_0r1[0:0], i_0r1[0:0], bna_0, reset);
C2R I3 (o_0r1[1:1], i_0r1[1:1], bna_0, reset);
INV I4 (bna_0, o_0a);
OR2 I5 (bcomp_0[0:0], o_0r0[0:0], o_0r1[0:0]);
OR2 I6 (bcomp_0[1:1], o_0r0[1:1], o_0r1[1:1]);
C2 I7 (i_0a, bcomp_0[0:0], bcomp_0[1:1]);
endmodule
// latch tkl5x1 width = 5, depth = 1
module tkl5x1 (i_0r0, i_0r1, i_0a, o_0r0, o_0r1, o_0a, reset);
input [4:0] i_0r0;
input [4:0] i_0r1;
output i_0a;
output [4:0] o_0r0;
output [4:0] o_0r1;
input o_0a;
input reset;
wire bna_0;
wire [4:0] bcomp_0;
wire [1:0] simp181_0;
C2R I0 (o_0r0[0:0], i_0r0[0:0], bna_0, reset);
C2R I1 (o_0r0[1:1], i_0r0[1:1], bna_0, reset);
C2R I2 (o_0r0[2:2], i_0r0[2:2], bna_0, reset);
C2R I3 (o_0r0[3:3], i_0r0[3:3], bna_0, reset);
C2R I4 (o_0r0[4:4], i_0r0[4:4], bna_0, reset);
C2R I5 (o_0r1[0:0], i_0r1[0:0], bna_0, reset);
C2R I6 (o_0r1[1:1], i_0r1[1:1], bna_0, reset);
C2R I7 (o_0r1[2:2], i_0r1[2:2], bna_0, reset);
C2R I8 (o_0r1[3:3], i_0r1[3:3], bna_0, reset);
C2R I9 (o_0r1[4:4], i_0r1[4:4], bna_0, reset);
INV I10 (bna_0, o_0a);
OR2 I11 (bcomp_0[0:0], o_0r0[0:0], o_0r1[0:0]);
OR2 I12 (bcomp_0[1:1], o_0r0[1:1], o_0r1[1:1]);
OR2 I13 (bcomp_0[2:2], o_0r0[2:2], o_0r1[2:2]);
OR2 I14 (bcomp_0[3:3], o_0r0[3:3], o_0r1[3:3]);
OR2 I15 (bcomp_0[4:4], o_0r0[4:4], o_0r1[4:4]);
C3 I16 (simp181_0[0:0], bcomp_0[0:0], bcomp_0[1:1], bcomp_0[2:2]);
C2 I17 (simp181_0[1:1], bcomp_0[3:3], bcomp_0[4:4]);
C2 I18 (i_0a, simp181_0[0:0], simp181_0[1:1]);
endmodule
// latch tkl7x1 width = 7, depth = 1
module tkl7x1 (i_0r0, i_0r1, i_0a, o_0r0, o_0r1, o_0a, reset);
input [6:0] i_0r0;
input [6:0] i_0r1;
output i_0a;
output [6:0] o_0r0;
output [6:0] o_0r1;
input o_0a;
input reset;
wire bna_0;
wire [6:0] bcomp_0;
wire [2:0] simp241_0;
C2R I0 (o_0r0[0:0], i_0r0[0:0], bna_0, reset);
C2R I1 (o_0r0[1:1], i_0r0[1:1], bna_0, reset);
C2R I2 (o_0r0[2:2], i_0r0[2:2], bna_0, reset);
C2R I3 (o_0r0[3:3], i_0r0[3:3], bna_0, reset);
C2R I4 (o_0r0[4:4], i_0r0[4:4], bna_0, reset);
C2R I5 (o_0r0[5:5], i_0r0[5:5], bna_0, reset);
C2R I6 (o_0r0[6:6], i_0r0[6:6], bna_0, reset);
C2R I7 (o_0r1[0:0], i_0r1[0:0], bna_0, reset);
C2R I8 (o_0r1[1:1], i_0r1[1:1], bna_0, reset);
C2R I9 (o_0r1[2:2], i_0r1[2:2], bna_0, reset);
C2R I10 (o_0r1[3:3], i_0r1[3:3], bna_0, reset);
C2R I11 (o_0r1[4:4], i_0r1[4:4], bna_0, reset);
C2R I12 (o_0r1[5:5], i_0r1[5:5], bna_0, reset);
C2R I13 (o_0r1[6:6], i_0r1[6:6], bna_0, reset);
INV I14 (bna_0, o_0a);
OR2 I15 (bcomp_0[0:0], o_0r0[0:0], o_0r1[0:0]);
OR2 I16 (bcomp_0[1:1], o_0r0[1:1], o_0r1[1:1]);
OR2 I17 (bcomp_0[2:2], o_0r0[2:2], o_0r1[2:2]);
OR2 I18 (bcomp_0[3:3], o_0r0[3:3], o_0r1[3:3]);
OR2 I19 (bcomp_0[4:4], o_0r0[4:4], o_0r1[4:4]);
OR2 I20 (bcomp_0[5:5], o_0r0[5:5], o_0r1[5:5]);
OR2 I21 (bcomp_0[6:6], o_0r0[6:6], o_0r1[6:6]);
C3 I22 (simp241_0[0:0], bcomp_0[0:0], bcomp_0[1:1], bcomp_0[2:2]);
C3 I23 (simp241_0[1:1], bcomp_0[3:3], bcomp_0[4:4], bcomp_0[5:5]);
BUFF I24 (simp241_0[2:2], bcomp_0[6:6]);
C3 I25 (i_0a, simp241_0[0:0], simp241_0[1:1], simp241_0[2:2]);
endmodule
// latch tkl31x1 width = 31, depth = 1
module tkl31x1 (i_0r0, i_0r1, i_0a, o_0r0, o_0r1, o_0a, reset);
input [30:0] i_0r0;
input [30:0] i_0r1;
output i_0a;
output [30:0] o_0r0;
output [30:0] o_0r1;
input o_0a;
input reset;
wire bna_0;
wire [30:0] bcomp_0;
wire [10:0] simp961_0;
wire [3:0] simp962_0;
wire [1:0] simp963_0;
C2R I0 (o_0r0[0:0], i_0r0[0:0], bna_0, reset);
C2R I1 (o_0r0[1:1], i_0r0[1:1], bna_0, reset);
C2R I2 (o_0r0[2:2], i_0r0[2:2], bna_0, reset);
C2R I3 (o_0r0[3:3], i_0r0[3:3], bna_0, reset);
C2R I4 (o_0r0[4:4], i_0r0[4:4], bna_0, reset);
C2R I5 (o_0r0[5:5], i_0r0[5:5], bna_0, reset);
C2R I6 (o_0r0[6:6], i_0r0[6:6], bna_0, reset);
C2R I7 (o_0r0[7:7], i_0r0[7:7], bna_0, reset);
C2R I8 (o_0r0[8:8], i_0r0[8:8], bna_0, reset);
C2R I9 (o_0r0[9:9], i_0r0[9:9], bna_0, reset);
C2R I10 (o_0r0[10:10], i_0r0[10:10], bna_0, reset);
C2R I11 (o_0r0[11:11], i_0r0[11:11], bna_0, reset);
C2R I12 (o_0r0[12:12], i_0r0[12:12], bna_0, reset);
C2R I13 (o_0r0[13:13], i_0r0[13:13], bna_0, reset);
C2R I14 (o_0r0[14:14], i_0r0[14:14], bna_0, reset);
C2R I15 (o_0r0[15:15], i_0r0[15:15], bna_0, reset);
C2R I16 (o_0r0[16:16], i_0r0[16:16], bna_0, reset);
C2R I17 (o_0r0[17:17], i_0r0[17:17], bna_0, reset);
C2R I18 (o_0r0[18:18], i_0r0[18:18], bna_0, reset);
C2R I19 (o_0r0[19:19], i_0r0[19:19], bna_0, reset);
C2R I20 (o_0r0[20:20], i_0r0[20:20], bna_0, reset);
C2R I21 (o_0r0[21:21], i_0r0[21:21], bna_0, reset);
C2R I22 (o_0r0[22:22], i_0r0[22:22], bna_0, reset);
C2R I23 (o_0r0[23:23], i_0r0[23:23], bna_0, reset);
C2R I24 (o_0r0[24:24], i_0r0[24:24], bna_0, reset);
C2R I25 (o_0r0[25:25], i_0r0[25:25], bna_0, reset);
C2R I26 (o_0r0[26:26], i_0r0[26:26], bna_0, reset);
C2R I27 (o_0r0[27:27], i_0r0[27:27], bna_0, reset);
C2R I28 (o_0r0[28:28], i_0r0[28:28], bna_0, reset);
C2R I29 (o_0r0[29:29], i_0r0[29:29], bna_0, reset);
C2R I30 (o_0r0[30:30], i_0r0[30:30], bna_0, reset);
C2R I31 (o_0r1[0:0], i_0r1[0:0], bna_0, reset);
C2R I32 (o_0r1[1:1], i_0r1[1:1], bna_0, reset);
C2R I33 (o_0r1[2:2], i_0r1[2:2], bna_0, reset);
C2R I34 (o_0r1[3:3], i_0r1[3:3], bna_0, reset);
C2R I35 (o_0r1[4:4], i_0r1[4:4], bna_0, reset);
C2R I36 (o_0r1[5:5], i_0r1[5:5], bna_0, reset);
C2R I37 (o_0r1[6:6], i_0r1[6:6], bna_0, reset);
C2R I38 (o_0r1[7:7], i_0r1[7:7], bna_0, reset);
C2R I39 (o_0r1[8:8], i_0r1[8:8], bna_0, reset);
C2R I40 (o_0r1[9:9], i_0r1[9:9], bna_0, reset);
C2R I41 (o_0r1[10:10], i_0r1[10:10], bna_0, reset);
C2R I42 (o_0r1[11:11], i_0r1[11:11], bna_0, reset);
C2R I43 (o_0r1[12:12], i_0r1[12:12], bna_0, reset);
C2R I44 (o_0r1[13:13], i_0r1[13:13], bna_0, reset);
C2R I45 (o_0r1[14:14], i_0r1[14:14], bna_0, reset);
C2R I46 (o_0r1[15:15], i_0r1[15:15], bna_0, reset);
C2R I47 (o_0r1[16:16], i_0r1[16:16], bna_0, reset);
C2R I48 (o_0r1[17:17], i_0r1[17:17], bna_0, reset);
C2R I49 (o_0r1[18:18], i_0r1[18:18], bna_0, reset);
C2R I50 (o_0r1[19:19], i_0r1[19:19], bna_0, reset);
C2R I51 (o_0r1[20:20], i_0r1[20:20], bna_0, reset);
C2R I52 (o_0r1[21:21], i_0r1[21:21], bna_0, reset);
C2R I53 (o_0r1[22:22], i_0r1[22:22], bna_0, reset);
C2R I54 (o_0r1[23:23], i_0r1[23:23], bna_0, reset);
C2R I55 (o_0r1[24:24], i_0r1[24:24], bna_0, reset);
C2R I56 (o_0r1[25:25], i_0r1[25:25], bna_0, reset);
C2R I57 (o_0r1[26:26], i_0r1[26:26], bna_0, reset);
C2R I58 (o_0r1[27:27], i_0r1[27:27], bna_0, reset);
C2R I59 (o_0r1[28:28], i_0r1[28:28], bna_0, reset);
C2R I60 (o_0r1[29:29], i_0r1[29:29], bna_0, reset);
C2R I61 (o_0r1[30:30], i_0r1[30:30], bna_0, reset);
INV I62 (bna_0, o_0a);
OR2 I63 (bcomp_0[0:0], o_0r0[0:0], o_0r1[0:0]);
OR2 I64 (bcomp_0[1:1], o_0r0[1:1], o_0r1[1:1]);
OR2 I65 (bcomp_0[2:2], o_0r0[2:2], o_0r1[2:2]);
OR2 I66 (bcomp_0[3:3], o_0r0[3:3], o_0r1[3:3]);
OR2 I67 (bcomp_0[4:4], o_0r0[4:4], o_0r1[4:4]);
OR2 I68 (bcomp_0[5:5], o_0r0[5:5], o_0r1[5:5]);
OR2 I69 (bcomp_0[6:6], o_0r0[6:6], o_0r1[6:6]);
OR2 I70 (bcomp_0[7:7], o_0r0[7:7], o_0r1[7:7]);
OR2 I71 (bcomp_0[8:8], o_0r0[8:8], o_0r1[8:8]);
OR2 I72 (bcomp_0[9:9], o_0r0[9:9], o_0r1[9:9]);
OR2 I73 (bcomp_0[10:10], o_0r0[10:10], o_0r1[10:10]);
OR2 I74 (bcomp_0[11:11], o_0r0[11:11], o_0r1[11:11]);
OR2 I75 (bcomp_0[12:12], o_0r0[12:12], o_0r1[12:12]);
OR2 I76 (bcomp_0[13:13], o_0r0[13:13], o_0r1[13:13]);
OR2 I77 (bcomp_0[14:14], o_0r0[14:14], o_0r1[14:14]);
OR2 I78 (bcomp_0[15:15], o_0r0[15:15], o_0r1[15:15]);
OR2 I79 (bcomp_0[16:16], o_0r0[16:16], o_0r1[16:16]);
OR2 I80 (bcomp_0[17:17], o_0r0[17:17], o_0r1[17:17]);
OR2 I81 (bcomp_0[18:18], o_0r0[18:18], o_0r1[18:18]);
OR2 I82 (bcomp_0[19:19], o_0r0[19:19], o_0r1[19:19]);
OR2 I83 (bcomp_0[20:20], o_0r0[20:20], o_0r1[20:20]);
OR2 I84 (bcomp_0[21:21], o_0r0[21:21], o_0r1[21:21]);
OR2 I85 (bcomp_0[22:22], o_0r0[22:22], o_0r1[22:22]);
OR2 I86 (bcomp_0[23:23], o_0r0[23:23], o_0r1[23:23]);
OR2 I87 (bcomp_0[24:24], o_0r0[24:24], o_0r1[24:24]);
OR2 I88 (bcomp_0[25:25], o_0r0[25:25], o_0r1[25:25]);
OR2 I89 (bcomp_0[26:26], o_0r0[26:26], o_0r1[26:26]);
OR2 I90 (bcomp_0[27:27], o_0r0[27:27], o_0r1[27:27]);
OR2 I91 (bcomp_0[28:28], o_0r0[28:28], o_0r1[28:28]);
OR2 I92 (bcomp_0[29:29], o_0r0[29:29], o_0r1[29:29]);
OR2 I93 (bcomp_0[30:30], o_0r0[30:30], o_0r1[30:30]);
C3 I94 (simp961_0[0:0], bcomp_0[0:0], bcomp_0[1:1], bcomp_0[2:2]);
C3 I95 (simp961_0[1:1], bcomp_0[3:3], bcomp_0[4:4], bcomp_0[5:5]);
C3 I96 (simp961_0[2:2], bcomp_0[6:6], bcomp_0[7:7], bcomp_0[8:8]);
C3 I97 (simp961_0[3:3], bcomp_0[9:9], bcomp_0[10:10], bcomp_0[11:11]);
C3 I98 (simp961_0[4:4], bcomp_0[12:12], bcomp_0[13:13], bcomp_0[14:14]);
C3 I99 (simp961_0[5:5], bcomp_0[15:15], bcomp_0[16:16], bcomp_0[17:17]);
C3 I100 (simp961_0[6:6], bcomp_0[18:18], bcomp_0[19:19], bcomp_0[20:20]);
C3 I101 (simp961_0[7:7], bcomp_0[21:21], bcomp_0[22:22], bcomp_0[23:23]);
C3 I102 (simp961_0[8:8], bcomp_0[24:24], bcomp_0[25:25], bcomp_0[26:26]);
C3 I103 (simp961_0[9:9], bcomp_0[27:27], bcomp_0[28:28], bcomp_0[29:29]);
BUFF I104 (simp961_0[10:10], bcomp_0[30:30]);
C3 I105 (simp962_0[0:0], simp961_0[0:0], simp961_0[1:1], simp961_0[2:2]);
C3 I106 (simp962_0[1:1], simp961_0[3:3], simp961_0[4:4], simp961_0[5:5]);
C3 I107 (simp962_0[2:2], simp961_0[6:6], simp961_0[7:7], simp961_0[8:8]);
C2 I108 (simp962_0[3:3], simp961_0[9:9], simp961_0[10:10]);
C3 I109 (simp963_0[0:0], simp962_0[0:0], simp962_0[1:1], simp962_0[2:2]);
BUFF I110 (simp963_0[1:1], simp962_0[3:3]);
C2 I111 (i_0a, simp963_0[0:0], simp963_0[1:1]);
endmodule
// latch tkl30x1 width = 30, depth = 1
module tkl30x1 (i_0r0, i_0r1, i_0a, o_0r0, o_0r1, o_0a, reset);
input [29:0] i_0r0;
input [29:0] i_0r1;
output i_0a;
output [29:0] o_0r0;
output [29:0] o_0r1;
input o_0a;
input reset;
wire bna_0;
wire [29:0] bcomp_0;
wire [9:0] simp931_0;
wire [3:0] simp932_0;
wire [1:0] simp933_0;
C2R I0 (o_0r0[0:0], i_0r0[0:0], bna_0, reset);
C2R I1 (o_0r0[1:1], i_0r0[1:1], bna_0, reset);
C2R I2 (o_0r0[2:2], i_0r0[2:2], bna_0, reset);
C2R I3 (o_0r0[3:3], i_0r0[3:3], bna_0, reset);
C2R I4 (o_0r0[4:4], i_0r0[4:4], bna_0, reset);
C2R I5 (o_0r0[5:5], i_0r0[5:5], bna_0, reset);
C2R I6 (o_0r0[6:6], i_0r0[6:6], bna_0, reset);
C2R I7 (o_0r0[7:7], i_0r0[7:7], bna_0, reset);
C2R I8 (o_0r0[8:8], i_0r0[8:8], bna_0, reset);
C2R I9 (o_0r0[9:9], i_0r0[9:9], bna_0, reset);
C2R I10 (o_0r0[10:10], i_0r0[10:10], bna_0, reset);
C2R I11 (o_0r0[11:11], i_0r0[11:11], bna_0, reset);
C2R I12 (o_0r0[12:12], i_0r0[12:12], bna_0, reset);
C2R I13 (o_0r0[13:13], i_0r0[13:13], bna_0, reset);
C2R I14 (o_0r0[14:14], i_0r0[14:14], bna_0, reset);
C2R I15 (o_0r0[15:15], i_0r0[15:15], bna_0, reset);
C2R I16 (o_0r0[16:16], i_0r0[16:16], bna_0, reset);
C2R I17 (o_0r0[17:17], i_0r0[17:17], bna_0, reset);
C2R I18 (o_0r0[18:18], i_0r0[18:18], bna_0, reset);
C2R I19 (o_0r0[19:19], i_0r0[19:19], bna_0, reset);
C2R I20 (o_0r0[20:20], i_0r0[20:20], bna_0, reset);
C2R I21 (o_0r0[21:21], i_0r0[21:21], bna_0, reset);
C2R I22 (o_0r0[22:22], i_0r0[22:22], bna_0, reset);
C2R I23 (o_0r0[23:23], i_0r0[23:23], bna_0, reset);
C2R I24 (o_0r0[24:24], i_0r0[24:24], bna_0, reset);
C2R I25 (o_0r0[25:25], i_0r0[25:25], bna_0, reset);
C2R I26 (o_0r0[26:26], i_0r0[26:26], bna_0, reset);
C2R I27 (o_0r0[27:27], i_0r0[27:27], bna_0, reset);
C2R I28 (o_0r0[28:28], i_0r0[28:28], bna_0, reset);
C2R I29 (o_0r0[29:29], i_0r0[29:29], bna_0, reset);
C2R I30 (o_0r1[0:0], i_0r1[0:0], bna_0, reset);
C2R I31 (o_0r1[1:1], i_0r1[1:1], bna_0, reset);
C2R I32 (o_0r1[2:2], i_0r1[2:2], bna_0, reset);
C2R I33 (o_0r1[3:3], i_0r1[3:3], bna_0, reset);
C2R I34 (o_0r1[4:4], i_0r1[4:4], bna_0, reset);
C2R I35 (o_0r1[5:5], i_0r1[5:5], bna_0, reset);
C2R I36 (o_0r1[6:6], i_0r1[6:6], bna_0, reset);
C2R I37 (o_0r1[7:7], i_0r1[7:7], bna_0, reset);
C2R I38 (o_0r1[8:8], i_0r1[8:8], bna_0, reset);
C2R I39 (o_0r1[9:9], i_0r1[9:9], bna_0, reset);
C2R I40 (o_0r1[10:10], i_0r1[10:10], bna_0, reset);
C2R I41 (o_0r1[11:11], i_0r1[11:11], bna_0, reset);
C2R I42 (o_0r1[12:12], i_0r1[12:12], bna_0, reset);
C2R I43 (o_0r1[13:13], i_0r1[13:13], bna_0, reset);
C2R I44 (o_0r1[14:14], i_0r1[14:14], bna_0, reset);
C2R I45 (o_0r1[15:15], i_0r1[15:15], bna_0, reset);
C2R I46 (o_0r1[16:16], i_0r1[16:16], bna_0, reset);
C2R I47 (o_0r1[17:17], i_0r1[17:17], bna_0, reset);
C2R I48 (o_0r1[18:18], i_0r1[18:18], bna_0, reset);
C2R I49 (o_0r1[19:19], i_0r1[19:19], bna_0, reset);
C2R I50 (o_0r1[20:20], i_0r1[20:20], bna_0, reset);
C2R I51 (o_0r1[21:21], i_0r1[21:21], bna_0, reset);
C2R I52 (o_0r1[22:22], i_0r1[22:22], bna_0, reset);
C2R I53 (o_0r1[23:23], i_0r1[23:23], bna_0, reset);
C2R I54 (o_0r1[24:24], i_0r1[24:24], bna_0, reset);
C2R I55 (o_0r1[25:25], i_0r1[25:25], bna_0, reset);
C2R I56 (o_0r1[26:26], i_0r1[26:26], bna_0, reset);
C2R I57 (o_0r1[27:27], i_0r1[27:27], bna_0, reset);
C2R I58 (o_0r1[28:28], i_0r1[28:28], bna_0, reset);
C2R I59 (o_0r1[29:29], i_0r1[29:29], bna_0, reset);
INV I60 (bna_0, o_0a);
OR2 I61 (bcomp_0[0:0], o_0r0[0:0], o_0r1[0:0]);
OR2 I62 (bcomp_0[1:1], o_0r0[1:1], o_0r1[1:1]);
OR2 I63 (bcomp_0[2:2], o_0r0[2:2], o_0r1[2:2]);
OR2 I64 (bcomp_0[3:3], o_0r0[3:3], o_0r1[3:3]);
OR2 I65 (bcomp_0[4:4], o_0r0[4:4], o_0r1[4:4]);
OR2 I66 (bcomp_0[5:5], o_0r0[5:5], o_0r1[5:5]);
OR2 I67 (bcomp_0[6:6], o_0r0[6:6], o_0r1[6:6]);
OR2 I68 (bcomp_0[7:7], o_0r0[7:7], o_0r1[7:7]);
OR2 I69 (bcomp_0[8:8], o_0r0[8:8], o_0r1[8:8]);
OR2 I70 (bcomp_0[9:9], o_0r0[9:9], o_0r1[9:9]);
OR2 I71 (bcomp_0[10:10], o_0r0[10:10], o_0r1[10:10]);
OR2 I72 (bcomp_0[11:11], o_0r0[11:11], o_0r1[11:11]);
OR2 I73 (bcomp_0[12:12], o_0r0[12:12], o_0r1[12:12]);
OR2 I74 (bcomp_0[13:13], o_0r0[13:13], o_0r1[13:13]);
OR2 I75 (bcomp_0[14:14], o_0r0[14:14], o_0r1[14:14]);
OR2 I76 (bcomp_0[15:15], o_0r0[15:15], o_0r1[15:15]);
OR2 I77 (bcomp_0[16:16], o_0r0[16:16], o_0r1[16:16]);
OR2 I78 (bcomp_0[17:17], o_0r0[17:17], o_0r1[17:17]);
OR2 I79 (bcomp_0[18:18], o_0r0[18:18], o_0r1[18:18]);
OR2 I80 (bcomp_0[19:19], o_0r0[19:19], o_0r1[19:19]);
OR2 I81 (bcomp_0[20:20], o_0r0[20:20], o_0r1[20:20]);
OR2 I82 (bcomp_0[21:21], o_0r0[21:21], o_0r1[21:21]);
OR2 I83 (bcomp_0[22:22], o_0r0[22:22], o_0r1[22:22]);
OR2 I84 (bcomp_0[23:23], o_0r0[23:23], o_0r1[23:23]);
OR2 I85 (bcomp_0[24:24], o_0r0[24:24], o_0r1[24:24]);
OR2 I86 (bcomp_0[25:25], o_0r0[25:25], o_0r1[25:25]);
OR2 I87 (bcomp_0[26:26], o_0r0[26:26], o_0r1[26:26]);
OR2 I88 (bcomp_0[27:27], o_0r0[27:27], o_0r1[27:27]);
OR2 I89 (bcomp_0[28:28], o_0r0[28:28], o_0r1[28:28]);
OR2 I90 (bcomp_0[29:29], o_0r0[29:29], o_0r1[29:29]);
C3 I91 (simp931_0[0:0], bcomp_0[0:0], bcomp_0[1:1], bcomp_0[2:2]);
C3 I92 (simp931_0[1:1], bcomp_0[3:3], bcomp_0[4:4], bcomp_0[5:5]);
C3 I93 (simp931_0[2:2], bcomp_0[6:6], bcomp_0[7:7], bcomp_0[8:8]);
C3 I94 (simp931_0[3:3], bcomp_0[9:9], bcomp_0[10:10], bcomp_0[11:11]);
C3 I95 (simp931_0[4:4], bcomp_0[12:12], bcomp_0[13:13], bcomp_0[14:14]);
C3 I96 (simp931_0[5:5], bcomp_0[15:15], bcomp_0[16:16], bcomp_0[17:17]);
C3 I97 (simp931_0[6:6], bcomp_0[18:18], bcomp_0[19:19], bcomp_0[20:20]);
C3 I98 (simp931_0[7:7], bcomp_0[21:21], bcomp_0[22:22], bcomp_0[23:23]);
C3 I99 (simp931_0[8:8], bcomp_0[24:24], bcomp_0[25:25], bcomp_0[26:26]);
C3 I100 (simp931_0[9:9], bcomp_0[27:27], bcomp_0[28:28], bcomp_0[29:29]);
C3 I101 (simp932_0[0:0], simp931_0[0:0], simp931_0[1:1], simp931_0[2:2]);
C3 I102 (simp932_0[1:1], simp931_0[3:3], simp931_0[4:4], simp931_0[5:5]);
C3 I103 (simp932_0[2:2], simp931_0[6:6], simp931_0[7:7], simp931_0[8:8]);
BUFF I104 (simp932_0[3:3], simp931_0[9:9]);
C3 I105 (simp933_0[0:0], simp932_0[0:0], simp932_0[1:1], simp932_0[2:2]);
BUFF I106 (simp933_0[1:1], simp932_0[3:3]);
C2 I107 (i_0a, simp933_0[0:0], simp933_0[1:1]);
endmodule
// latch tkl28x1 width = 28, depth = 1
module tkl28x1 (i_0r0, i_0r1, i_0a, o_0r0, o_0r1, o_0a, reset);
input [27:0] i_0r0;
input [27:0] i_0r1;
output i_0a;
output [27:0] o_0r0;
output [27:0] o_0r1;
input o_0a;
input reset;
wire bna_0;
wire [27:0] bcomp_0;
wire [9:0] simp871_0;
wire [3:0] simp872_0;
wire [1:0] simp873_0;
C2R I0 (o_0r0[0:0], i_0r0[0:0], bna_0, reset);
C2R I1 (o_0r0[1:1], i_0r0[1:1], bna_0, reset);
C2R I2 (o_0r0[2:2], i_0r0[2:2], bna_0, reset);
C2R I3 (o_0r0[3:3], i_0r0[3:3], bna_0, reset);
C2R I4 (o_0r0[4:4], i_0r0[4:4], bna_0, reset);
C2R I5 (o_0r0[5:5], i_0r0[5:5], bna_0, reset);
C2R I6 (o_0r0[6:6], i_0r0[6:6], bna_0, reset);
C2R I7 (o_0r0[7:7], i_0r0[7:7], bna_0, reset);
C2R I8 (o_0r0[8:8], i_0r0[8:8], bna_0, reset);
C2R I9 (o_0r0[9:9], i_0r0[9:9], bna_0, reset);
C2R I10 (o_0r0[10:10], i_0r0[10:10], bna_0, reset);
C2R I11 (o_0r0[11:11], i_0r0[11:11], bna_0, reset);
C2R I12 (o_0r0[12:12], i_0r0[12:12], bna_0, reset);
C2R I13 (o_0r0[13:13], i_0r0[13:13], bna_0, reset);
C2R I14 (o_0r0[14:14], i_0r0[14:14], bna_0, reset);
C2R I15 (o_0r0[15:15], i_0r0[15:15], bna_0, reset);
C2R I16 (o_0r0[16:16], i_0r0[16:16], bna_0, reset);
C2R I17 (o_0r0[17:17], i_0r0[17:17], bna_0, reset);
C2R I18 (o_0r0[18:18], i_0r0[18:18], bna_0, reset);
C2R I19 (o_0r0[19:19], i_0r0[19:19], bna_0, reset);
C2R I20 (o_0r0[20:20], i_0r0[20:20], bna_0, reset);
C2R I21 (o_0r0[21:21], i_0r0[21:21], bna_0, reset);
C2R I22 (o_0r0[22:22], i_0r0[22:22], bna_0, reset);
C2R I23 (o_0r0[23:23], i_0r0[23:23], bna_0, reset);
C2R I24 (o_0r0[24:24], i_0r0[24:24], bna_0, reset);
C2R I25 (o_0r0[25:25], i_0r0[25:25], bna_0, reset);
C2R I26 (o_0r0[26:26], i_0r0[26:26], bna_0, reset);
C2R I27 (o_0r0[27:27], i_0r0[27:27], bna_0, reset);
C2R I28 (o_0r1[0:0], i_0r1[0:0], bna_0, reset);
C2R I29 (o_0r1[1:1], i_0r1[1:1], bna_0, reset);
C2R I30 (o_0r1[2:2], i_0r1[2:2], bna_0, reset);
C2R I31 (o_0r1[3:3], i_0r1[3:3], bna_0, reset);
C2R I32 (o_0r1[4:4], i_0r1[4:4], bna_0, reset);
C2R I33 (o_0r1[5:5], i_0r1[5:5], bna_0, reset);
C2R I34 (o_0r1[6:6], i_0r1[6:6], bna_0, reset);
C2R I35 (o_0r1[7:7], i_0r1[7:7], bna_0, reset);
C2R I36 (o_0r1[8:8], i_0r1[8:8], bna_0, reset);
C2R I37 (o_0r1[9:9], i_0r1[9:9], bna_0, reset);
C2R I38 (o_0r1[10:10], i_0r1[10:10], bna_0, reset);
C2R I39 (o_0r1[11:11], i_0r1[11:11], bna_0, reset);
C2R I40 (o_0r1[12:12], i_0r1[12:12], bna_0, reset);
C2R I41 (o_0r1[13:13], i_0r1[13:13], bna_0, reset);
C2R I42 (o_0r1[14:14], i_0r1[14:14], bna_0, reset);
C2R I43 (o_0r1[15:15], i_0r1[15:15], bna_0, reset);
C2R I44 (o_0r1[16:16], i_0r1[16:16], bna_0, reset);
C2R I45 (o_0r1[17:17], i_0r1[17:17], bna_0, reset);
C2R I46 (o_0r1[18:18], i_0r1[18:18], bna_0, reset);
C2R I47 (o_0r1[19:19], i_0r1[19:19], bna_0, reset);
C2R I48 (o_0r1[20:20], i_0r1[20:20], bna_0, reset);
C2R I49 (o_0r1[21:21], i_0r1[21:21], bna_0, reset);
C2R I50 (o_0r1[22:22], i_0r1[22:22], bna_0, reset);
C2R I51 (o_0r1[23:23], i_0r1[23:23], bna_0, reset);
C2R I52 (o_0r1[24:24], i_0r1[24:24], bna_0, reset);
C2R I53 (o_0r1[25:25], i_0r1[25:25], bna_0, reset);
C2R I54 (o_0r1[26:26], i_0r1[26:26], bna_0, reset);
C2R I55 (o_0r1[27:27], i_0r1[27:27], bna_0, reset);
INV I56 (bna_0, o_0a);
OR2 I57 (bcomp_0[0:0], o_0r0[0:0], o_0r1[0:0]);
OR2 I58 (bcomp_0[1:1], o_0r0[1:1], o_0r1[1:1]);
OR2 I59 (bcomp_0[2:2], o_0r0[2:2], o_0r1[2:2]);
OR2 I60 (bcomp_0[3:3], o_0r0[3:3], o_0r1[3:3]);
OR2 I61 (bcomp_0[4:4], o_0r0[4:4], o_0r1[4:4]);
OR2 I62 (bcomp_0[5:5], o_0r0[5:5], o_0r1[5:5]);
OR2 I63 (bcomp_0[6:6], o_0r0[6:6], o_0r1[6:6]);
OR2 I64 (bcomp_0[7:7], o_0r0[7:7], o_0r1[7:7]);
OR2 I65 (bcomp_0[8:8], o_0r0[8:8], o_0r1[8:8]);
OR2 I66 (bcomp_0[9:9], o_0r0[9:9], o_0r1[9:9]);
OR2 I67 (bcomp_0[10:10], o_0r0[10:10], o_0r1[10:10]);
OR2 I68 (bcomp_0[11:11], o_0r0[11:11], o_0r1[11:11]);
OR2 I69 (bcomp_0[12:12], o_0r0[12:12], o_0r1[12:12]);
OR2 I70 (bcomp_0[13:13], o_0r0[13:13], o_0r1[13:13]);
OR2 I71 (bcomp_0[14:14], o_0r0[14:14], o_0r1[14:14]);
OR2 I72 (bcomp_0[15:15], o_0r0[15:15], o_0r1[15:15]);
OR2 I73 (bcomp_0[16:16], o_0r0[16:16], o_0r1[16:16]);
OR2 I74 (bcomp_0[17:17], o_0r0[17:17], o_0r1[17:17]);
OR2 I75 (bcomp_0[18:18], o_0r0[18:18], o_0r1[18:18]);
OR2 I76 (bcomp_0[19:19], o_0r0[19:19], o_0r1[19:19]);
OR2 I77 (bcomp_0[20:20], o_0r0[20:20], o_0r1[20:20]);
OR2 I78 (bcomp_0[21:21], o_0r0[21:21], o_0r1[21:21]);
OR2 I79 (bcomp_0[22:22], o_0r0[22:22], o_0r1[22:22]);
OR2 I80 (bcomp_0[23:23], o_0r0[23:23], o_0r1[23:23]);
OR2 I81 (bcomp_0[24:24], o_0r0[24:24], o_0r1[24:24]);
OR2 I82 (bcomp_0[25:25], o_0r0[25:25], o_0r1[25:25]);
OR2 I83 (bcomp_0[26:26], o_0r0[26:26], o_0r1[26:26]);
OR2 I84 (bcomp_0[27:27], o_0r0[27:27], o_0r1[27:27]);
C3 I85 (simp871_0[0:0], bcomp_0[0:0], bcomp_0[1:1], bcomp_0[2:2]);
C3 I86 (simp871_0[1:1], bcomp_0[3:3], bcomp_0[4:4], bcomp_0[5:5]);
C3 I87 (simp871_0[2:2], bcomp_0[6:6], bcomp_0[7:7], bcomp_0[8:8]);
C3 I88 (simp871_0[3:3], bcomp_0[9:9], bcomp_0[10:10], bcomp_0[11:11]);
C3 I89 (simp871_0[4:4], bcomp_0[12:12], bcomp_0[13:13], bcomp_0[14:14]);
C3 I90 (simp871_0[5:5], bcomp_0[15:15], bcomp_0[16:16], bcomp_0[17:17]);
C3 I91 (simp871_0[6:6], bcomp_0[18:18], bcomp_0[19:19], bcomp_0[20:20]);
C3 I92 (simp871_0[7:7], bcomp_0[21:21], bcomp_0[22:22], bcomp_0[23:23]);
C3 I93 (simp871_0[8:8], bcomp_0[24:24], bcomp_0[25:25], bcomp_0[26:26]);
BUFF I94 (simp871_0[9:9], bcomp_0[27:27]);
C3 I95 (simp872_0[0:0], simp871_0[0:0], simp871_0[1:1], simp871_0[2:2]);
C3 I96 (simp872_0[1:1], simp871_0[3:3], simp871_0[4:4], simp871_0[5:5]);
C3 I97 (simp872_0[2:2], simp871_0[6:6], simp871_0[7:7], simp871_0[8:8]);
BUFF I98 (simp872_0[3:3], simp871_0[9:9]);
C3 I99 (simp873_0[0:0], simp872_0[0:0], simp872_0[1:1], simp872_0[2:2]);
BUFF I100 (simp873_0[1:1], simp872_0[3:3]);
C2 I101 (i_0a, simp873_0[0:0], simp873_0[1:1]);
endmodule
// latch tkl24x1 width = 24, depth = 1
module tkl24x1 (i_0r0, i_0r1, i_0a, o_0r0, o_0r1, o_0a, reset);
input [23:0] i_0r0;
input [23:0] i_0r1;
output i_0a;
output [23:0] o_0r0;
output [23:0] o_0r1;
input o_0a;
input reset;
wire bna_0;
wire [23:0] bcomp_0;
wire [7:0] simp751_0;
wire [2:0] simp752_0;
C2R I0 (o_0r0[0:0], i_0r0[0:0], bna_0, reset);
C2R I1 (o_0r0[1:1], i_0r0[1:1], bna_0, reset);
C2R I2 (o_0r0[2:2], i_0r0[2:2], bna_0, reset);
C2R I3 (o_0r0[3:3], i_0r0[3:3], bna_0, reset);
C2R I4 (o_0r0[4:4], i_0r0[4:4], bna_0, reset);
C2R I5 (o_0r0[5:5], i_0r0[5:5], bna_0, reset);
C2R I6 (o_0r0[6:6], i_0r0[6:6], bna_0, reset);
C2R I7 (o_0r0[7:7], i_0r0[7:7], bna_0, reset);
C2R I8 (o_0r0[8:8], i_0r0[8:8], bna_0, reset);
C2R I9 (o_0r0[9:9], i_0r0[9:9], bna_0, reset);
C2R I10 (o_0r0[10:10], i_0r0[10:10], bna_0, reset);
C2R I11 (o_0r0[11:11], i_0r0[11:11], bna_0, reset);
C2R I12 (o_0r0[12:12], i_0r0[12:12], bna_0, reset);
C2R I13 (o_0r0[13:13], i_0r0[13:13], bna_0, reset);
C2R I14 (o_0r0[14:14], i_0r0[14:14], bna_0, reset);
C2R I15 (o_0r0[15:15], i_0r0[15:15], bna_0, reset);
C2R I16 (o_0r0[16:16], i_0r0[16:16], bna_0, reset);
C2R I17 (o_0r0[17:17], i_0r0[17:17], bna_0, reset);
C2R I18 (o_0r0[18:18], i_0r0[18:18], bna_0, reset);
C2R I19 (o_0r0[19:19], i_0r0[19:19], bna_0, reset);
C2R I20 (o_0r0[20:20], i_0r0[20:20], bna_0, reset);
C2R I21 (o_0r0[21:21], i_0r0[21:21], bna_0, reset);
C2R I22 (o_0r0[22:22], i_0r0[22:22], bna_0, reset);
C2R I23 (o_0r0[23:23], i_0r0[23:23], bna_0, reset);
C2R I24 (o_0r1[0:0], i_0r1[0:0], bna_0, reset);
C2R I25 (o_0r1[1:1], i_0r1[1:1], bna_0, reset);
C2R I26 (o_0r1[2:2], i_0r1[2:2], bna_0, reset);
C2R I27 (o_0r1[3:3], i_0r1[3:3], bna_0, reset);
C2R I28 (o_0r1[4:4], i_0r1[4:4], bna_0, reset);
C2R I29 (o_0r1[5:5], i_0r1[5:5], bna_0, reset);
C2R I30 (o_0r1[6:6], i_0r1[6:6], bna_0, reset);
C2R I31 (o_0r1[7:7], i_0r1[7:7], bna_0, reset);
C2R I32 (o_0r1[8:8], i_0r1[8:8], bna_0, reset);
C2R I33 (o_0r1[9:9], i_0r1[9:9], bna_0, reset);
C2R I34 (o_0r1[10:10], i_0r1[10:10], bna_0, reset);
C2R I35 (o_0r1[11:11], i_0r1[11:11], bna_0, reset);
C2R I36 (o_0r1[12:12], i_0r1[12:12], bna_0, reset);
C2R I37 (o_0r1[13:13], i_0r1[13:13], bna_0, reset);
C2R I38 (o_0r1[14:14], i_0r1[14:14], bna_0, reset);
C2R I39 (o_0r1[15:15], i_0r1[15:15], bna_0, reset);
C2R I40 (o_0r1[16:16], i_0r1[16:16], bna_0, reset);
C2R I41 (o_0r1[17:17], i_0r1[17:17], bna_0, reset);
C2R I42 (o_0r1[18:18], i_0r1[18:18], bna_0, reset);
C2R I43 (o_0r1[19:19], i_0r1[19:19], bna_0, reset);
C2R I44 (o_0r1[20:20], i_0r1[20:20], bna_0, reset);
C2R I45 (o_0r1[21:21], i_0r1[21:21], bna_0, reset);
C2R I46 (o_0r1[22:22], i_0r1[22:22], bna_0, reset);
C2R I47 (o_0r1[23:23], i_0r1[23:23], bna_0, reset);
INV I48 (bna_0, o_0a);
OR2 I49 (bcomp_0[0:0], o_0r0[0:0], o_0r1[0:0]);
OR2 I50 (bcomp_0[1:1], o_0r0[1:1], o_0r1[1:1]);
OR2 I51 (bcomp_0[2:2], o_0r0[2:2], o_0r1[2:2]);
OR2 I52 (bcomp_0[3:3], o_0r0[3:3], o_0r1[3:3]);
OR2 I53 (bcomp_0[4:4], o_0r0[4:4], o_0r1[4:4]);
OR2 I54 (bcomp_0[5:5], o_0r0[5:5], o_0r1[5:5]);
OR2 I55 (bcomp_0[6:6], o_0r0[6:6], o_0r1[6:6]);
OR2 I56 (bcomp_0[7:7], o_0r0[7:7], o_0r1[7:7]);
OR2 I57 (bcomp_0[8:8], o_0r0[8:8], o_0r1[8:8]);
OR2 I58 (bcomp_0[9:9], o_0r0[9:9], o_0r1[9:9]);
OR2 I59 (bcomp_0[10:10], o_0r0[10:10], o_0r1[10:10]);
OR2 I60 (bcomp_0[11:11], o_0r0[11:11], o_0r1[11:11]);
OR2 I61 (bcomp_0[12:12], o_0r0[12:12], o_0r1[12:12]);
OR2 I62 (bcomp_0[13:13], o_0r0[13:13], o_0r1[13:13]);
OR2 I63 (bcomp_0[14:14], o_0r0[14:14], o_0r1[14:14]);
OR2 I64 (bcomp_0[15:15], o_0r0[15:15], o_0r1[15:15]);
OR2 I65 (bcomp_0[16:16], o_0r0[16:16], o_0r1[16:16]);
OR2 I66 (bcomp_0[17:17], o_0r0[17:17], o_0r1[17:17]);
OR2 I67 (bcomp_0[18:18], o_0r0[18:18], o_0r1[18:18]);
OR2 I68 (bcomp_0[19:19], o_0r0[19:19], o_0r1[19:19]);
OR2 I69 (bcomp_0[20:20], o_0r0[20:20], o_0r1[20:20]);
OR2 I70 (bcomp_0[21:21], o_0r0[21:21], o_0r1[21:21]);
OR2 I71 (bcomp_0[22:22], o_0r0[22:22], o_0r1[22:22]);
OR2 I72 (bcomp_0[23:23], o_0r0[23:23], o_0r1[23:23]);
C3 I73 (simp751_0[0:0], bcomp_0[0:0], bcomp_0[1:1], bcomp_0[2:2]);
C3 I74 (simp751_0[1:1], bcomp_0[3:3], bcomp_0[4:4], bcomp_0[5:5]);
C3 I75 (simp751_0[2:2], bcomp_0[6:6], bcomp_0[7:7], bcomp_0[8:8]);
C3 I76 (simp751_0[3:3], bcomp_0[9:9], bcomp_0[10:10], bcomp_0[11:11]);
C3 I77 (simp751_0[4:4], bcomp_0[12:12], bcomp_0[13:13], bcomp_0[14:14]);
C3 I78 (simp751_0[5:5], bcomp_0[15:15], bcomp_0[16:16], bcomp_0[17:17]);
C3 I79 (simp751_0[6:6], bcomp_0[18:18], bcomp_0[19:19], bcomp_0[20:20]);
C3 I80 (simp751_0[7:7], bcomp_0[21:21], bcomp_0[22:22], bcomp_0[23:23]);
C3 I81 (simp752_0[0:0], simp751_0[0:0], simp751_0[1:1], simp751_0[2:2]);
C3 I82 (simp752_0[1:1], simp751_0[3:3], simp751_0[4:4], simp751_0[5:5]);
C2 I83 (simp752_0[2:2], simp751_0[6:6], simp751_0[7:7]);
C3 I84 (i_0a, simp752_0[0:0], simp752_0[1:1], simp752_0[2:2]);
endmodule
// latch tkl16x1 width = 16, depth = 1
module tkl16x1 (i_0r0, i_0r1, i_0a, o_0r0, o_0r1, o_0a, reset);
input [15:0] i_0r0;
input [15:0] i_0r1;
output i_0a;
output [15:0] o_0r0;
output [15:0] o_0r1;
input o_0a;
input reset;
wire bna_0;
wire [15:0] bcomp_0;
wire [5:0] simp511_0;
wire [1:0] simp512_0;
C2R I0 (o_0r0[0:0], i_0r0[0:0], bna_0, reset);
C2R I1 (o_0r0[1:1], i_0r0[1:1], bna_0, reset);
C2R I2 (o_0r0[2:2], i_0r0[2:2], bna_0, reset);
C2R I3 (o_0r0[3:3], i_0r0[3:3], bna_0, reset);
C2R I4 (o_0r0[4:4], i_0r0[4:4], bna_0, reset);
C2R I5 (o_0r0[5:5], i_0r0[5:5], bna_0, reset);
C2R I6 (o_0r0[6:6], i_0r0[6:6], bna_0, reset);
C2R I7 (o_0r0[7:7], i_0r0[7:7], bna_0, reset);
C2R I8 (o_0r0[8:8], i_0r0[8:8], bna_0, reset);
C2R I9 (o_0r0[9:9], i_0r0[9:9], bna_0, reset);
C2R I10 (o_0r0[10:10], i_0r0[10:10], bna_0, reset);
C2R I11 (o_0r0[11:11], i_0r0[11:11], bna_0, reset);
C2R I12 (o_0r0[12:12], i_0r0[12:12], bna_0, reset);
C2R I13 (o_0r0[13:13], i_0r0[13:13], bna_0, reset);
C2R I14 (o_0r0[14:14], i_0r0[14:14], bna_0, reset);
C2R I15 (o_0r0[15:15], i_0r0[15:15], bna_0, reset);
C2R I16 (o_0r1[0:0], i_0r1[0:0], bna_0, reset);
C2R I17 (o_0r1[1:1], i_0r1[1:1], bna_0, reset);
C2R I18 (o_0r1[2:2], i_0r1[2:2], bna_0, reset);
C2R I19 (o_0r1[3:3], i_0r1[3:3], bna_0, reset);
C2R I20 (o_0r1[4:4], i_0r1[4:4], bna_0, reset);
C2R I21 (o_0r1[5:5], i_0r1[5:5], bna_0, reset);
C2R I22 (o_0r1[6:6], i_0r1[6:6], bna_0, reset);
C2R I23 (o_0r1[7:7], i_0r1[7:7], bna_0, reset);
C2R I24 (o_0r1[8:8], i_0r1[8:8], bna_0, reset);
C2R I25 (o_0r1[9:9], i_0r1[9:9], bna_0, reset);
C2R I26 (o_0r1[10:10], i_0r1[10:10], bna_0, reset);
C2R I27 (o_0r1[11:11], i_0r1[11:11], bna_0, reset);
C2R I28 (o_0r1[12:12], i_0r1[12:12], bna_0, reset);
C2R I29 (o_0r1[13:13], i_0r1[13:13], bna_0, reset);
C2R I30 (o_0r1[14:14], i_0r1[14:14], bna_0, reset);
C2R I31 (o_0r1[15:15], i_0r1[15:15], bna_0, reset);
INV I32 (bna_0, o_0a);
OR2 I33 (bcomp_0[0:0], o_0r0[0:0], o_0r1[0:0]);
OR2 I34 (bcomp_0[1:1], o_0r0[1:1], o_0r1[1:1]);
OR2 I35 (bcomp_0[2:2], o_0r0[2:2], o_0r1[2:2]);
OR2 I36 (bcomp_0[3:3], o_0r0[3:3], o_0r1[3:3]);
OR2 I37 (bcomp_0[4:4], o_0r0[4:4], o_0r1[4:4]);
OR2 I38 (bcomp_0[5:5], o_0r0[5:5], o_0r1[5:5]);
OR2 I39 (bcomp_0[6:6], o_0r0[6:6], o_0r1[6:6]);
OR2 I40 (bcomp_0[7:7], o_0r0[7:7], o_0r1[7:7]);
OR2 I41 (bcomp_0[8:8], o_0r0[8:8], o_0r1[8:8]);
OR2 I42 (bcomp_0[9:9], o_0r0[9:9], o_0r1[9:9]);
OR2 I43 (bcomp_0[10:10], o_0r0[10:10], o_0r1[10:10]);
OR2 I44 (bcomp_0[11:11], o_0r0[11:11], o_0r1[11:11]);
OR2 I45 (bcomp_0[12:12], o_0r0[12:12], o_0r1[12:12]);
OR2 I46 (bcomp_0[13:13], o_0r0[13:13], o_0r1[13:13]);
OR2 I47 (bcomp_0[14:14], o_0r0[14:14], o_0r1[14:14]);
OR2 I48 (bcomp_0[15:15], o_0r0[15:15], o_0r1[15:15]);
C3 I49 (simp511_0[0:0], bcomp_0[0:0], bcomp_0[1:1], bcomp_0[2:2]);
C3 I50 (simp511_0[1:1], bcomp_0[3:3], bcomp_0[4:4], bcomp_0[5:5]);
C3 I51 (simp511_0[2:2], bcomp_0[6:6], bcomp_0[7:7], bcomp_0[8:8]);
C3 I52 (simp511_0[3:3], bcomp_0[9:9], bcomp_0[10:10], bcomp_0[11:11]);
C3 I53 (simp511_0[4:4], bcomp_0[12:12], bcomp_0[13:13], bcomp_0[14:14]);
BUFF I54 (simp511_0[5:5], bcomp_0[15:15]);
C3 I55 (simp512_0[0:0], simp511_0[0:0], simp511_0[1:1], simp511_0[2:2]);
C3 I56 (simp512_0[1:1], simp511_0[3:3], simp511_0[4:4], simp511_0[5:5]);
C2 I57 (i_0a, simp512_0[0:0], simp512_0[1:1]);
endmodule
// latch tkl1x1 width = 1, depth = 1
module tkl1x1 (i_0r0, i_0r1, i_0a, o_0r0, o_0r1, o_0a, reset);
input i_0r0;
input i_0r1;
output i_0a;
output o_0r0;
output o_0r1;
input o_0a;
input reset;
wire bna_0;
wire bcomp_0;
C2R I0 (o_0r0, i_0r0, bna_0, reset);
C2R I1 (o_0r1, i_0r1, bna_0, reset);
INV I2 (bna_0, o_0a);
OR2 I3 (bcomp_0, o_0r0, o_0r1);
BUFF I4 (i_0a, bcomp_0);
endmodule
module teak_Shifter (shift_0r0, shift_0r1, shift_0a, distanceI_0r0, distanceI_0r1, distanceI_0a, result_0r0, result_0r1, result_0a, arg_0r0, arg_0r1, arg_0a, reset);
input [1:0] shift_0r0;
input [1:0] shift_0r1;
output shift_0a;
input [4:0] distanceI_0r0;
input [4:0] distanceI_0r1;
output distanceI_0a;
output [31:0] result_0r0;
output [31:0] result_0r1;
input result_0a;
input [31:0] arg_0r0;
input [31:0] arg_0r1;
output arg_0a;
input reset;
wire L1P_0r;
wire L1P_0a;
wire L1A_0r;
wire L1A_0a;
wire [31:0] L35P_0r0;
wire [31:0] L35P_0r1;
wire L35P_0a;
wire [31:0] L35A_0r0;
wire [31:0] L35A_0r1;
wire L35A_0a;
wire L37P_0r;
wire L37P_0a;
wire L37A_0r;
wire L37A_0a;
wire L38P_0r;
wire L38P_0a;
wire L38A_0r;
wire L38A_0a;
wire [31:0] L72P_0r0;
wire [31:0] L72P_0r1;
wire L72P_0a;
wire [31:0] L72A_0r0;
wire [31:0] L72A_0r1;
wire L72A_0a;
wire L74P_0r;
wire L74P_0a;
wire L74A_0r;
wire L74A_0a;
wire [31:0] L78P_0r0;
wire [31:0] L78P_0r1;
wire L78P_0a;
wire [31:0] L78A_0r0;
wire [31:0] L78A_0r1;
wire L78A_0a;
wire [31:0] L80P_0r0;
wire [31:0] L80P_0r1;
wire L80P_0a;
wire [31:0] L80A_0r0;
wire [31:0] L80A_0r1;
wire L80A_0a;
wire [31:0] L82P_0r0;
wire [31:0] L82P_0r1;
wire L82P_0a;
wire [31:0] L82A_0r0;
wire [31:0] L82A_0r1;
wire L82A_0a;
wire [31:0] L84P_0r0;
wire [31:0] L84P_0r1;
wire L84P_0a;
wire [31:0] L84A_0r0;
wire [31:0] L84A_0r1;
wire L84A_0a;
wire [31:0] L87P_0r0;
wire [31:0] L87P_0r1;
wire L87P_0a;
wire [31:0] L87A_0r0;
wire [31:0] L87A_0r1;
wire L87A_0a;
wire L94P_0r;
wire L94P_0a;
wire L94A_0r;
wire L94A_0a;
wire [31:0] L128P_0r0;
wire [31:0] L128P_0r1;
wire L128P_0a;
wire [31:0] L128A_0r0;
wire [31:0] L128A_0r1;
wire L128A_0a;
wire L130P_0r;
wire L130P_0a;
wire L130A_0r;
wire L130A_0a;
wire [31:0] L134P_0r0;
wire [31:0] L134P_0r1;
wire L134P_0a;
wire [31:0] L134A_0r0;
wire [31:0] L134A_0r1;
wire L134A_0a;
wire [31:0] L136P_0r0;
wire [31:0] L136P_0r1;
wire L136P_0a;
wire [31:0] L136A_0r0;
wire [31:0] L136A_0r1;
wire L136A_0a;
wire [31:0] L138P_0r0;
wire [31:0] L138P_0r1;
wire L138P_0a;
wire [31:0] L138A_0r0;
wire [31:0] L138A_0r1;
wire L138A_0a;
wire [31:0] L140P_0r0;
wire [31:0] L140P_0r1;
wire L140P_0a;
wire [31:0] L140A_0r0;
wire [31:0] L140A_0r1;
wire L140A_0a;
wire [31:0] L143P_0r0;
wire [31:0] L143P_0r1;
wire L143P_0a;
wire [31:0] L143A_0r0;
wire [31:0] L143A_0r1;
wire L143A_0a;
wire L150P_0r;
wire L150P_0a;
wire L150A_0r;
wire L150A_0a;
wire [31:0] L184P_0r0;
wire [31:0] L184P_0r1;
wire L184P_0a;
wire [31:0] L184A_0r0;
wire [31:0] L184A_0r1;
wire L184A_0a;
wire L186P_0r;
wire L186P_0a;
wire L186A_0r;
wire L186A_0a;
wire [31:0] L190P_0r0;
wire [31:0] L190P_0r1;
wire L190P_0a;
wire [31:0] L190A_0r0;
wire [31:0] L190A_0r1;
wire L190A_0a;
wire [31:0] L192P_0r0;
wire [31:0] L192P_0r1;
wire L192P_0a;
wire [31:0] L192A_0r0;
wire [31:0] L192A_0r1;
wire L192A_0a;
wire [31:0] L194P_0r0;
wire [31:0] L194P_0r1;
wire L194P_0a;
wire [31:0] L194A_0r0;
wire [31:0] L194A_0r1;
wire L194A_0a;
wire [31:0] L196P_0r0;
wire [31:0] L196P_0r1;
wire L196P_0a;
wire [31:0] L196A_0r0;
wire [31:0] L196A_0r1;
wire L196A_0a;
wire [31:0] L199P_0r0;
wire [31:0] L199P_0r1;
wire L199P_0a;
wire [31:0] L199A_0r0;
wire [31:0] L199A_0r1;
wire L199A_0a;
wire L206P_0r;
wire L206P_0a;
wire L206A_0r;
wire L206A_0a;
wire [31:0] L240P_0r0;
wire [31:0] L240P_0r1;
wire L240P_0a;
wire [31:0] L240A_0r0;
wire [31:0] L240A_0r1;
wire L240A_0a;
wire L242P_0r;
wire L242P_0a;
wire L242A_0r;
wire L242A_0a;
wire L244P_0r;
wire L244P_0a;
wire L244A_0r;
wire L244A_0a;
wire [31:0] L246P_0r0;
wire [31:0] L246P_0r1;
wire L246P_0a;
wire [31:0] L246A_0r0;
wire [31:0] L246A_0r1;
wire L246A_0a;
wire [31:0] L248P_0r0;
wire [31:0] L248P_0r1;
wire L248P_0a;
wire [31:0] L248A_0r0;
wire [31:0] L248A_0r1;
wire L248A_0a;
wire [31:0] L250P_0r0;
wire [31:0] L250P_0r1;
wire L250P_0a;
wire [31:0] L250A_0r0;
wire [31:0] L250A_0r1;
wire L250A_0a;
wire [31:0] L252P_0r0;
wire [31:0] L252P_0r1;
wire L252P_0a;
wire [31:0] L252A_0r0;
wire [31:0] L252A_0r1;
wire L252A_0a;
wire [31:0] L255P_0r0;
wire [31:0] L255P_0r1;
wire L255P_0a;
wire [31:0] L255A_0r0;
wire [31:0] L255A_0r1;
wire L255A_0a;
wire L268P_0r;
wire L268P_0a;
wire L268A_0r;
wire L268A_0a;
wire [1:0] L271_0r0;
wire [1:0] L271_0r1;
wire L271_0a;
wire [4:0] L272_0r0;
wire [4:0] L272_0r1;
wire L272_0a;
wire [31:0] L274P_0r0;
wire [31:0] L274P_0r1;
wire L274P_0a;
wire [31:0] L274A_0r0;
wire [31:0] L274A_0r1;
wire L274A_0a;
wire [31:0] L276P_0r0;
wire [31:0] L276P_0r1;
wire L276P_0a;
wire [31:0] L276A_0r0;
wire [31:0] L276A_0r1;
wire L276A_0a;
wire [31:0] L278P_0r0;
wire [31:0] L278P_0r1;
wire L278P_0a;
wire [31:0] L278A_0r0;
wire [31:0] L278A_0r1;
wire L278A_0a;
wire [31:0] L280P_0r0;
wire [31:0] L280P_0r1;
wire L280P_0a;
wire [31:0] L280A_0r0;
wire [31:0] L280A_0r1;
wire L280A_0a;
wire [31:0] L281P_0r0;
wire [31:0] L281P_0r1;
wire L281P_0a;
wire [31:0] L281A_0r0;
wire [31:0] L281A_0r1;
wire L281A_0a;
wire L282P_0r;
wire L282P_0a;
wire L282A_0r;
wire L282A_0a;
wire [31:0] L283_0r0;
wire [31:0] L283_0r1;
wire L283_0a;
wire [31:0] L290_0r0;
wire [31:0] L290_0r1;
wire L290_0a;
wire [6:0] L306P_0r0;
wire [6:0] L306P_0r1;
wire L306P_0a;
wire [6:0] L306A_0r0;
wire [6:0] L306A_0r1;
wire L306A_0a;
wire [30:0] L323P_0r0;
wire [30:0] L323P_0r1;
wire L323P_0a;
wire [30:0] L323A_0r0;
wire [30:0] L323A_0r1;
wire L323A_0a;
wire [30:0] L324P_0r0;
wire [30:0] L324P_0r1;
wire L324P_0a;
wire [30:0] L324A_0r0;
wire [30:0] L324A_0r1;
wire L324A_0a;
wire [30:0] L325P_0r0;
wire [30:0] L325P_0r1;
wire L325P_0a;
wire [30:0] L325A_0r0;
wire [30:0] L325A_0r1;
wire L325A_0a;
wire [29:0] L326P_0r0;
wire [29:0] L326P_0r1;
wire L326P_0a;
wire [29:0] L326A_0r0;
wire [29:0] L326A_0r1;
wire L326A_0a;
wire [29:0] L327P_0r0;
wire [29:0] L327P_0r1;
wire L327P_0a;
wire [29:0] L327A_0r0;
wire [29:0] L327A_0r1;
wire L327A_0a;
wire [29:0] L328P_0r0;
wire [29:0] L328P_0r1;
wire L328P_0a;
wire [29:0] L328A_0r0;
wire [29:0] L328A_0r1;
wire L328A_0a;
wire [27:0] L329P_0r0;
wire [27:0] L329P_0r1;
wire L329P_0a;
wire [27:0] L329A_0r0;
wire [27:0] L329A_0r1;
wire L329A_0a;
wire [27:0] L330P_0r0;
wire [27:0] L330P_0r1;
wire L330P_0a;
wire [27:0] L330A_0r0;
wire [27:0] L330A_0r1;
wire L330A_0a;
wire [27:0] L331P_0r0;
wire [27:0] L331P_0r1;
wire L331P_0a;
wire [27:0] L331A_0r0;
wire [27:0] L331A_0r1;
wire L331A_0a;
wire [23:0] L332P_0r0;
wire [23:0] L332P_0r1;
wire L332P_0a;
wire [23:0] L332A_0r0;
wire [23:0] L332A_0r1;
wire L332A_0a;
wire [23:0] L333P_0r0;
wire [23:0] L333P_0r1;
wire L333P_0a;
wire [23:0] L333A_0r0;
wire [23:0] L333A_0r1;
wire L333A_0a;
wire [23:0] L334P_0r0;
wire [23:0] L334P_0r1;
wire L334P_0a;
wire [23:0] L334A_0r0;
wire [23:0] L334A_0r1;
wire L334A_0a;
wire [15:0] L335P_0r0;
wire [15:0] L335P_0r1;
wire L335P_0a;
wire [15:0] L335A_0r0;
wire [15:0] L335A_0r1;
wire L335A_0a;
wire [15:0] L336P_0r0;
wire [15:0] L336P_0r1;
wire L336P_0a;
wire [15:0] L336A_0r0;
wire [15:0] L336A_0r1;
wire L336A_0a;
wire [15:0] L337P_0r0;
wire [15:0] L337P_0r1;
wire L337P_0a;
wire [15:0] L337A_0r0;
wire [15:0] L337A_0r1;
wire L337A_0a;
wire L338P_0r;
wire L338P_0a;
wire L338A_0r;
wire L338A_0a;
wire L339P_0r;
wire L339P_0a;
wire L339A_0r;
wire L339A_0a;
wire L340P_0r;
wire L340P_0a;
wire L340A_0r;
wire L340A_0a;
wire L341P_0r;
wire L341P_0a;
wire L341A_0r;
wire L341A_0a;
wire L342P_0r;
wire L342P_0a;
wire L342A_0r;
wire L342A_0a;
wire L346P_0r0;
wire L346P_0r1;
wire L346P_0a;
wire L346A_0r0;
wire L346A_0r1;
wire L346A_0a;
wire L350P_0r0;
wire L350P_0r1;
wire L350P_0a;
wire L350A_0r0;
wire L350A_0r1;
wire L350A_0a;
wire L354P_0r0;
wire L354P_0r1;
wire L354P_0a;
wire L354A_0r0;
wire L354A_0r1;
wire L354A_0a;
wire L358P_0r0;
wire L358P_0r1;
wire L358P_0a;
wire L358A_0r0;
wire L358A_0r1;
wire L358A_0a;
wire L359P_0r;
wire L359P_0a;
wire L359A_0r;
wire L359A_0a;
wire [6:0] L361P_0r0;
wire [6:0] L361P_0r1;
wire L361P_0a;
wire [6:0] L361A_0r0;
wire [6:0] L361A_0r1;
wire L361A_0a;
wire L362P_0r0;
wire L362P_0r1;
wire L362P_0a;
wire L362A_0r0;
wire L362A_0r1;
wire L362A_0a;
wire L364P_0r;
wire L364P_0a;
wire L364A_0r;
wire L364A_0a;
wire L366P_0r;
wire L366P_0a;
wire L366A_0r;
wire L366A_0a;
wire L368P_0r;
wire L368P_0a;
wire L368A_0r;
wire L368A_0a;
wire L370P_0r;
wire L370P_0a;
wire L370A_0r;
wire L370A_0a;
wire L372P_0r;
wire L372P_0a;
wire L372A_0r;
wire L372A_0a;
wire L373P_0r;
wire L373P_0a;
wire L373A_0r;
wire L373A_0a;
wire L374P_0r;
wire L374P_0a;
wire L374A_0r;
wire L374A_0a;
wire L375P_0r;
wire L375P_0a;
wire L375A_0r;
wire L375A_0a;
wire L376P_0r;
wire L376P_0a;
wire L376A_0r;
wire L376A_0a;
wire L377P_0r;
wire L377P_0a;
wire L377A_0r;
wire L377A_0a;
wire L378P_0r;
wire L378P_0a;
wire L378A_0r;
wire L378A_0a;
wire L379P_0r;
wire L379P_0a;
wire L379A_0r;
wire L379A_0a;
wire L380P_0r;
wire L380P_0a;
wire L380A_0r;
wire L380A_0a;
wire L381P_0r;
wire L381P_0a;
wire L381A_0r;
wire L381A_0a;
wire L382P_0r;
wire L382P_0a;
wire L382A_0r;
wire L382A_0a;
wire L383P_0r;
wire L383P_0a;
wire L383A_0r;
wire L383A_0a;
wire L384P_0r;
wire L384P_0a;
wire L384A_0r;
wire L384A_0a;
wire L385P_0r;
wire L385P_0a;
wire L385A_0r;
wire L385A_0a;
wire L386P_0r;
wire L386P_0a;
wire L386A_0r;
wire L386A_0a;
wire L387P_0r;
wire L387P_0a;
wire L387A_0r;
wire L387A_0a;
wire [1:0] L412P_0r0;
wire [1:0] L412P_0r1;
wire L412P_0a;
wire [1:0] L412A_0r0;
wire [1:0] L412A_0r1;
wire L412A_0a;
wire [1:0] L418P_0r0;
wire [1:0] L418P_0r1;
wire L418P_0a;
wire [1:0] L418A_0r0;
wire [1:0] L418A_0r1;
wire L418A_0a;
wire [1:0] L424P_0r0;
wire [1:0] L424P_0r1;
wire L424P_0a;
wire [1:0] L424A_0r0;
wire [1:0] L424A_0r1;
wire L424A_0a;
wire [1:0] L430P_0r0;
wire [1:0] L430P_0r1;
wire L430P_0a;
wire [1:0] L430A_0r0;
wire [1:0] L430A_0r1;
wire L430A_0a;
wire [1:0] L436P_0r0;
wire [1:0] L436P_0r1;
wire L436P_0a;
wire [1:0] L436A_0r0;
wire [1:0] L436A_0r1;
wire L436A_0a;
wire L438P_0r;
wire L438P_0a;
wire L438A_0r;
wire L438A_0a;
wire L439P_0r;
wire L439P_0a;
wire L439A_0r;
wire L439A_0a;
wire L440P_0r;
wire L440P_0a;
wire L440A_0r;
wire L440A_0a;
wire L441P_0r;
wire L441P_0a;
wire L441A_0r;
wire L441A_0a;
wire L442P_0r;
wire L442P_0a;
wire L442A_0r;
wire L442A_0a;
wire L443P_0r0;
wire L443P_0r1;
wire L443P_0a;
wire L443A_0r0;
wire L443A_0r1;
wire L443A_0a;
wire L444P_0r0;
wire L444P_0r1;
wire L444P_0a;
wire L444A_0r0;
wire L444A_0r1;
wire L444A_0a;
wire L446P_0r0;
wire L446P_0r1;
wire L446P_0a;
wire L446A_0r0;
wire L446A_0r1;
wire L446A_0a;
wire L447P_0r0;
wire L447P_0r1;
wire L447P_0a;
wire L447A_0r0;
wire L447A_0r1;
wire L447A_0a;
wire L449P_0r0;
wire L449P_0r1;
wire L449P_0a;
wire L449A_0r0;
wire L449A_0r1;
wire L449A_0a;
wire L450P_0r0;
wire L450P_0r1;
wire L450P_0a;
wire L450A_0r0;
wire L450A_0r1;
wire L450A_0a;
wire L452P_0r0;
wire L452P_0r1;
wire L452P_0a;
wire L452A_0r0;
wire L452A_0r1;
wire L452A_0a;
wire L453P_0r0;
wire L453P_0r1;
wire L453P_0a;
wire L453A_0r0;
wire L453A_0r1;
wire L453A_0a;
wire L455P_0r0;
wire L455P_0r1;
wire L455P_0a;
wire L455A_0r0;
wire L455A_0r1;
wire L455A_0a;
wire L456P_0r0;
wire L456P_0r1;
wire L456P_0a;
wire L456A_0r0;
wire L456A_0r1;
wire L456A_0a;
tko31m32_1nm1b0_2apt1o0w1bi0w31b I0 (L323P_0r0[30:0], L323P_0r1[30:0], L323P_0a, L276A_0r0[31:0], L276A_0r1[31:0], L276A_0a, reset);
tko31m32_1nm1b0_2api0w31bt1o0w1b I1 (L324P_0r0[30:0], L324P_0r1[30:0], L324P_0a, L278A_0r0[31:0], L278A_0r1[31:0], L278A_0a, reset);
tko31m32_1nm1b1_2api0w31bt1o0w1b I2 (L325P_0r0[30:0], L325P_0r1[30:0], L325P_0a, L280A_0r0[31:0], L280A_0r1[31:0], L280A_0a, reset);
tkvi32_wo0w32_ro0w32o0w31o1w31o1w31 I3 (L35P_0r0[31:0], L35P_0r1[31:0], L35P_0a, L1A_0r, L1A_0a, L342P_0r, L342P_0a, L385P_0r, L385P_0a, L386P_0r, L386P_0a, L387P_0r, L387P_0a, L274A_0r0[31:0], L274A_0r1[31:0], L274A_0a, L323A_0r0[30:0], L323A_0r1[30:0], L323A_0a, L324A_0r0[30:0], L324A_0r1[30:0], L324A_0a, L325A_0r0[30:0], L325A_0r1[30:0], L325A_0a, reset);
tko30m32_1nm2b0_2apt1o0w2bi0w30b I4 (L326P_0r0[29:0], L326P_0r1[29:0], L326P_0a, L80A_0r0[31:0], L80A_0r1[31:0], L80A_0a, reset);
tko30m32_1nm2b0_2api0w30bt1o0w2b I5 (L327P_0r0[29:0], L327P_0r1[29:0], L327P_0a, L82A_0r0[31:0], L82A_0r1[31:0], L82A_0a, reset);
tko30m32_1nm2b3_2api0w30bt1o0w2b I6 (L328P_0r0[29:0], L328P_0r1[29:0], L328P_0a, L84A_0r0[31:0], L84A_0r1[31:0], L84A_0a, reset);
tkvi32_wo0w32_ro0w32o0w30o2w30o2w30 I7 (L72P_0r0[31:0], L72P_0r1[31:0], L72P_0a, L38A_0r, L38A_0a, L338P_0r, L338P_0a, L373P_0r, L373P_0a, L374P_0r, L374P_0a, L375P_0r, L375P_0a, L78A_0r0[31:0], L78A_0r1[31:0], L78A_0a, L326A_0r0[29:0], L326A_0r1[29:0], L326A_0a, L327A_0r0[29:0], L327A_0r1[29:0], L327A_0a, L328A_0r0[29:0], L328A_0r1[29:0], L328A_0a, reset);
tkm4x32b I8 (L78P_0r0[31:0], L78P_0r1[31:0], L78P_0a, L80P_0r0[31:0], L80P_0r1[31:0], L80P_0a, L82P_0r0[31:0], L82P_0r1[31:0], L82P_0a, L84P_0r0[31:0], L84P_0r1[31:0], L84P_0a, L87A_0r0[31:0], L87A_0r1[31:0], L87A_0a, reset);
tkj32m32_0 I9 (L87P_0r0[31:0], L87P_0r1[31:0], L87P_0a, L37P_0r, L37P_0a, L35A_0r0[31:0], L35A_0r1[31:0], L35A_0a, reset);
tko28m32_1nm4b0_2apt1o0w4bi0w28b I10 (L329P_0r0[27:0], L329P_0r1[27:0], L329P_0a, L136A_0r0[31:0], L136A_0r1[31:0], L136A_0a, reset);
tko28m32_1nm4b0_2api0w28bt1o0w4b I11 (L330P_0r0[27:0], L330P_0r1[27:0], L330P_0a, L138A_0r0[31:0], L138A_0r1[31:0], L138A_0a, reset);
tko28m32_1nm4bf_2api0w28bt1o0w4b I12 (L331P_0r0[27:0], L331P_0r1[27:0], L331P_0a, L140A_0r0[31:0], L140A_0r1[31:0], L140A_0a, reset);
tkvi32_wo0w32_ro0w32o0w28o4w28o4w28 I13 (L128P_0r0[31:0], L128P_0r1[31:0], L128P_0a, L94A_0r, L94A_0a, L339P_0r, L339P_0a, L376P_0r, L376P_0a, L377P_0r, L377P_0a, L378P_0r, L378P_0a, L134A_0r0[31:0], L134A_0r1[31:0], L134A_0a, L329A_0r0[27:0], L329A_0r1[27:0], L329A_0a, L330A_0r0[27:0], L330A_0r1[27:0], L330A_0a, L331A_0r0[27:0], L331A_0r1[27:0], L331A_0a, reset);
tkm4x32b I14 (L134P_0r0[31:0], L134P_0r1[31:0], L134P_0a, L136P_0r0[31:0], L136P_0r1[31:0], L136P_0a, L138P_0r0[31:0], L138P_0r1[31:0], L138P_0a, L140P_0r0[31:0], L140P_0r1[31:0], L140P_0a, L143A_0r0[31:0], L143A_0r1[31:0], L143A_0a, reset);
tkj32m32_0 I15 (L143P_0r0[31:0], L143P_0r1[31:0], L143P_0a, L74P_0r, L74P_0a, L72A_0r0[31:0], L72A_0r1[31:0], L72A_0a, reset);
tko24m32_1nm8b0_2apt1o0w8bi0w24b I16 (L332P_0r0[23:0], L332P_0r1[23:0], L332P_0a, L192A_0r0[31:0], L192A_0r1[31:0], L192A_0a, reset);
tko24m32_1nm8b0_2api0w24bt1o0w8b I17 (L333P_0r0[23:0], L333P_0r1[23:0], L333P_0a, L194A_0r0[31:0], L194A_0r1[31:0], L194A_0a, reset);
tko24m32_1nm8bff_2api0w24bt1o0w8b I18 (L334P_0r0[23:0], L334P_0r1[23:0], L334P_0a, L196A_0r0[31:0], L196A_0r1[31:0], L196A_0a, reset);
tkvi32_wo0w32_ro0w32o0w24o8w24o8w24 I19 (L184P_0r0[31:0], L184P_0r1[31:0], L184P_0a, L150A_0r, L150A_0a, L340P_0r, L340P_0a, L379P_0r, L379P_0a, L380P_0r, L380P_0a, L381P_0r, L381P_0a, L190A_0r0[31:0], L190A_0r1[31:0], L190A_0a, L332A_0r0[23:0], L332A_0r1[23:0], L332A_0a, L333A_0r0[23:0], L333A_0r1[23:0], L333A_0a, L334A_0r0[23:0], L334A_0r1[23:0], L334A_0a, reset);
tkm4x32b I20 (L190P_0r0[31:0], L190P_0r1[31:0], L190P_0a, L192P_0r0[31:0], L192P_0r1[31:0], L192P_0a, L194P_0r0[31:0], L194P_0r1[31:0], L194P_0a, L196P_0r0[31:0], L196P_0r1[31:0], L196P_0a, L199A_0r0[31:0], L199A_0r1[31:0], L199A_0a, reset);
tkj32m32_0 I21 (L199P_0r0[31:0], L199P_0r1[31:0], L199P_0a, L130P_0r, L130P_0a, L128A_0r0[31:0], L128A_0r1[31:0], L128A_0a, reset);
tko16m32_1nm16b0_2apt1o0w16bi0w16b I22 (L335P_0r0[15:0], L335P_0r1[15:0], L335P_0a, L248A_0r0[31:0], L248A_0r1[31:0], L248A_0a, reset);
tko16m32_1nm16b0_2api0w16bt1o0w16b I23 (L336P_0r0[15:0], L336P_0r1[15:0], L336P_0a, L250A_0r0[31:0], L250A_0r1[31:0], L250A_0a, reset);
tko16m32_1nm16bffff_2api0w16bt1o0w16b I24 (L337P_0r0[15:0], L337P_0r1[15:0], L337P_0a, L252A_0r0[31:0], L252A_0r1[31:0], L252A_0a, reset);
tkvi32_wo0w32_ro0w32o0w16o16w16o16w16 I25 (L240P_0r0[31:0], L240P_0r1[31:0], L240P_0a, L206A_0r, L206A_0a, L341P_0r, L341P_0a, L382P_0r, L382P_0a, L383P_0r, L383P_0a, L384P_0r, L384P_0a, L246A_0r0[31:0], L246A_0r1[31:0], L246A_0a, L335A_0r0[15:0], L335A_0r1[15:0], L335A_0a, L336A_0r0[15:0], L336A_0r1[15:0], L336A_0a, L337A_0r0[15:0], L337A_0r1[15:0], L337A_0a, reset);
tkj0m0_0_0_0_0_0 I26 (L282P_0r, L282P_0a, L372P_0r, L372P_0a, L364P_0r, L364P_0a, L366P_0r, L366P_0a, L368P_0r, L368P_0a, L370P_0r, L370P_0a, L244A_0r, L244A_0a, reset);
tkm4x32b I27 (L246P_0r0[31:0], L246P_0r1[31:0], L246P_0a, L248P_0r0[31:0], L248P_0r1[31:0], L248P_0a, L250P_0r0[31:0], L250P_0r1[31:0], L250P_0a, L252P_0r0[31:0], L252P_0r1[31:0], L252P_0a, L255A_0r0[31:0], L255A_0r1[31:0], L255A_0a, reset);
tkj32m32_0 I28 (L255P_0r0[31:0], L255P_0r1[31:0], L255P_0a, L186P_0r, L186P_0a, L184A_0r0[31:0], L184A_0r1[31:0], L184A_0a, reset);
tkm4x32b I29 (L274P_0r0[31:0], L274P_0r1[31:0], L274P_0a, L276P_0r0[31:0], L276P_0r1[31:0], L276P_0a, L278P_0r0[31:0], L278P_0r1[31:0], L278P_0a, L280P_0r0[31:0], L280P_0r1[31:0], L280P_0a, L281A_0r0[31:0], L281A_0r1[31:0], L281A_0a, reset);
tkf32mo0w0_o0w32 I30 (L281P_0r0[31:0], L281P_0r1[31:0], L281P_0a, L282A_0r, L282A_0a, L283_0r0[31:0], L283_0r1[31:0], L283_0a, reset);
tkj32m32_0 I31 (L290_0r0[31:0], L290_0r1[31:0], L290_0a, L242P_0r, L242P_0a, L240A_0r0[31:0], L240A_0r1[31:0], L240A_0a, reset);
tkj7m5_2_0 I32 (L272_0r0[4:0], L272_0r1[4:0], L272_0a, L271_0r0[1:0], L271_0r1[1:0], L271_0a, L268P_0r, L268P_0a, L306A_0r0[6:0], L306A_0r1[6:0], L306A_0a, reset);
tkvdistanceIshift7_wo0w7_ro5w2o5w2o5w2o5w2o5w2 I33 (L361P_0r0[6:0], L361P_0r1[6:0], L361P_0a, L359A_0r, L359A_0a, L438P_0r, L438P_0a, L439P_0r, L439P_0a, L440P_0r, L440P_0a, L441P_0r, L441P_0a, L442P_0r, L442P_0a, L412A_0r0[1:0], L412A_0r1[1:0], L412A_0a, L418A_0r0[1:0], L418A_0r1[1:0], L418A_0a, L424A_0r0[1:0], L424A_0r1[1:0], L424A_0a, L430A_0r0[1:0], L430A_0r1[1:0], L430A_0a, L436A_0r0[1:0], L436A_0r1[1:0], L436A_0a, reset);
tkf7mo0w7_o4w1_o3w1_o2w1_o1w1_o0w1 I34 (L306P_0r0[6:0], L306P_0r1[6:0], L306P_0a, L361A_0r0[6:0], L361A_0r1[6:0], L361A_0a, L362A_0r0, L362A_0r1, L362A_0a, L358A_0r0, L358A_0r1, L358A_0a, L354A_0r0, L354A_0r1, L354A_0a, L350A_0r0, L350A_0r1, L350A_0a, L346A_0r0, L346A_0r1, L346A_0a, reset);
tkj1m1_0 I35 (L346P_0r0, L346P_0r1, L346P_0a, L1P_0r, L1P_0a, L443A_0r0, L443A_0r1, L443A_0a, reset);
tkj1m1_0 I36 (L350P_0r0, L350P_0r1, L350P_0a, L38P_0r, L38P_0a, L446A_0r0, L446A_0r1, L446A_0a, reset);
tkj1m1_0 I37 (L354P_0r0, L354P_0r1, L354P_0a, L94P_0r, L94P_0a, L449A_0r0, L449A_0r1, L449A_0a, reset);
tkj1m1_0 I38 (L358P_0r0, L358P_0r1, L358P_0a, L150P_0r, L150P_0a, L452A_0r0, L452A_0r1, L452A_0a, reset);
tkj1m1_0 I39 (L362P_0r0, L362P_0r1, L362P_0a, L206P_0r, L206P_0a, L455A_0r0, L455A_0r1, L455A_0a, reset);
tkf0mo0w0_o0w0_o0w0_o0w0_o0w0 I40 (L359P_0r, L359P_0a, L242A_0r, L242A_0a, L186A_0r, L186A_0a, L130A_0r, L130A_0a, L74A_0r, L74A_0a, L37A_0r, L37A_0a, reset);
tks2_o0w2_3o0w0_0c2o0w0_1o0w0 I41 (L412P_0r0[1:0], L412P_0r1[1:0], L412P_0a, L387A_0r, L387A_0a, L385A_0r, L385A_0a, L386A_0r, L386A_0a, reset);
tks2_o0w2_3o0w0_0c2o0w0_1o0w0 I42 (L418P_0r0[1:0], L418P_0r1[1:0], L418P_0a, L375A_0r, L375A_0a, L373A_0r, L373A_0a, L374A_0r, L374A_0a, reset);
tks2_o0w2_3o0w0_0c2o0w0_1o0w0 I43 (L424P_0r0[1:0], L424P_0r1[1:0], L424P_0a, L378A_0r, L378A_0a, L376A_0r, L376A_0a, L377A_0r, L377A_0a, reset);
tks2_o0w2_3o0w0_0c2o0w0_1o0w0 I44 (L430P_0r0[1:0], L430P_0r1[1:0], L430P_0a, L381A_0r, L381A_0a, L379A_0r, L379A_0a, L380A_0r, L380A_0a, reset);
tks2_o0w2_3o0w0_0c2o0w0_1o0w0 I45 (L436P_0r0[1:0], L436P_0r1[1:0], L436P_0a, L384A_0r, L384A_0a, L382A_0r, L382A_0a, L383A_0r, L383A_0a, reset);
tkf1mo0w1_o0w0 I46 (L443P_0r0, L443P_0r1, L443P_0a, L444A_0r0, L444A_0r1, L444A_0a, L372A_0r, L372A_0a, reset);
tks1_o0w1_0o0w0_1o0w0 I47 (L444P_0r0, L444P_0r1, L444P_0a, L342A_0r, L342A_0a, L438A_0r, L438A_0a, reset);
tkf1mo0w1_o0w0 I48 (L446P_0r0, L446P_0r1, L446P_0a, L447A_0r0, L447A_0r1, L447A_0a, L364A_0r, L364A_0a, reset);
tks1_o0w1_0o0w0_1o0w0 I49 (L447P_0r0, L447P_0r1, L447P_0a, L338A_0r, L338A_0a, L439A_0r, L439A_0a, reset);
tkf1mo0w1_o0w0 I50 (L449P_0r0, L449P_0r1, L449P_0a, L450A_0r0, L450A_0r1, L450A_0a, L366A_0r, L366A_0a, reset);
tks1_o0w1_0o0w0_1o0w0 I51 (L450P_0r0, L450P_0r1, L450P_0a, L339A_0r, L339A_0a, L440A_0r, L440A_0a, reset);
tkf1mo0w1_o0w0 I52 (L452P_0r0, L452P_0r1, L452P_0a, L453A_0r0, L453A_0r1, L453A_0a, L368A_0r, L368A_0a, reset);
tks1_o0w1_0o0w0_1o0w0 I53 (L453P_0r0, L453P_0r1, L453P_0a, L340A_0r, L340A_0a, L441A_0r, L441A_0a, reset);
tkf1mo0w1_o0w0 I54 (L455P_0r0, L455P_0r1, L455P_0a, L456A_0r0, L456A_0r1, L456A_0a, L370A_0r, L370A_0a, reset);
tks1_o0w1_0o0w0_1o0w0 I55 (L456P_0r0, L456P_0r1, L456P_0a, L341A_0r, L341A_0a, L442A_0r, L442A_0a, reset);
tki I56 (L244P_0r, L244P_0a, L268A_0r, L268A_0a, reset);
tkl0x1 I57 (L1A_0r, L1A_0a, L1P_0r, L1P_0a, reset);
tkl32x1 I58 (L35A_0r0[31:0], L35A_0r1[31:0], L35A_0a, L35P_0r0[31:0], L35P_0r1[31:0], L35P_0a, reset);
tkl0x1 I59 (L37A_0r, L37A_0a, L37P_0r, L37P_0a, reset);
tkl0x1 I60 (L38A_0r, L38A_0a, L38P_0r, L38P_0a, reset);
tkl32x1 I61 (L72A_0r0[31:0], L72A_0r1[31:0], L72A_0a, L72P_0r0[31:0], L72P_0r1[31:0], L72P_0a, reset);
tkl0x1 I62 (L74A_0r, L74A_0a, L74P_0r, L74P_0a, reset);
tkl32x1 I63 (L78A_0r0[31:0], L78A_0r1[31:0], L78A_0a, L78P_0r0[31:0], L78P_0r1[31:0], L78P_0a, reset);
tkl32x1 I64 (L80A_0r0[31:0], L80A_0r1[31:0], L80A_0a, L80P_0r0[31:0], L80P_0r1[31:0], L80P_0a, reset);
tkl32x1 I65 (L82A_0r0[31:0], L82A_0r1[31:0], L82A_0a, L82P_0r0[31:0], L82P_0r1[31:0], L82P_0a, reset);
tkl32x1 I66 (L84A_0r0[31:0], L84A_0r1[31:0], L84A_0a, L84P_0r0[31:0], L84P_0r1[31:0], L84P_0a, reset);
tkl32x1 I67 (L87A_0r0[31:0], L87A_0r1[31:0], L87A_0a, L87P_0r0[31:0], L87P_0r1[31:0], L87P_0a, reset);
tkl0x1 I68 (L94A_0r, L94A_0a, L94P_0r, L94P_0a, reset);
tkl32x1 I69 (L128A_0r0[31:0], L128A_0r1[31:0], L128A_0a, L128P_0r0[31:0], L128P_0r1[31:0], L128P_0a, reset);
tkl0x1 I70 (L130A_0r, L130A_0a, L130P_0r, L130P_0a, reset);
tkl32x1 I71 (L134A_0r0[31:0], L134A_0r1[31:0], L134A_0a, L134P_0r0[31:0], L134P_0r1[31:0], L134P_0a, reset);
tkl32x1 I72 (L136A_0r0[31:0], L136A_0r1[31:0], L136A_0a, L136P_0r0[31:0], L136P_0r1[31:0], L136P_0a, reset);
tkl32x1 I73 (L138A_0r0[31:0], L138A_0r1[31:0], L138A_0a, L138P_0r0[31:0], L138P_0r1[31:0], L138P_0a, reset);
tkl32x1 I74 (L140A_0r0[31:0], L140A_0r1[31:0], L140A_0a, L140P_0r0[31:0], L140P_0r1[31:0], L140P_0a, reset);
tkl32x1 I75 (L143A_0r0[31:0], L143A_0r1[31:0], L143A_0a, L143P_0r0[31:0], L143P_0r1[31:0], L143P_0a, reset);
tkl0x1 I76 (L150A_0r, L150A_0a, L150P_0r, L150P_0a, reset);
tkl32x1 I77 (L184A_0r0[31:0], L184A_0r1[31:0], L184A_0a, L184P_0r0[31:0], L184P_0r1[31:0], L184P_0a, reset);
tkl0x1 I78 (L186A_0r, L186A_0a, L186P_0r, L186P_0a, reset);
tkl32x1 I79 (L190A_0r0[31:0], L190A_0r1[31:0], L190A_0a, L190P_0r0[31:0], L190P_0r1[31:0], L190P_0a, reset);
tkl32x1 I80 (L192A_0r0[31:0], L192A_0r1[31:0], L192A_0a, L192P_0r0[31:0], L192P_0r1[31:0], L192P_0a, reset);
tkl32x1 I81 (L194A_0r0[31:0], L194A_0r1[31:0], L194A_0a, L194P_0r0[31:0], L194P_0r1[31:0], L194P_0a, reset);
tkl32x1 I82 (L196A_0r0[31:0], L196A_0r1[31:0], L196A_0a, L196P_0r0[31:0], L196P_0r1[31:0], L196P_0a, reset);
tkl32x1 I83 (L199A_0r0[31:0], L199A_0r1[31:0], L199A_0a, L199P_0r0[31:0], L199P_0r1[31:0], L199P_0a, reset);
tkl0x1 I84 (L206A_0r, L206A_0a, L206P_0r, L206P_0a, reset);
tkl32x1 I85 (L240A_0r0[31:0], L240A_0r1[31:0], L240A_0a, L240P_0r0[31:0], L240P_0r1[31:0], L240P_0a, reset);
tkl0x1 I86 (L242A_0r, L242A_0a, L242P_0r, L242P_0a, reset);
tkl0x1 I87 (L244A_0r, L244A_0a, L244P_0r, L244P_0a, reset);
tkl32x1 I88 (L246A_0r0[31:0], L246A_0r1[31:0], L246A_0a, L246P_0r0[31:0], L246P_0r1[31:0], L246P_0a, reset);
tkl32x1 I89 (L248A_0r0[31:0], L248A_0r1[31:0], L248A_0a, L248P_0r0[31:0], L248P_0r1[31:0], L248P_0a, reset);
tkl32x1 I90 (L250A_0r0[31:0], L250A_0r1[31:0], L250A_0a, L250P_0r0[31:0], L250P_0r1[31:0], L250P_0a, reset);
tkl32x1 I91 (L252A_0r0[31:0], L252A_0r1[31:0], L252A_0a, L252P_0r0[31:0], L252P_0r1[31:0], L252P_0a, reset);
tkl32x1 I92 (L255A_0r0[31:0], L255A_0r1[31:0], L255A_0a, L255P_0r0[31:0], L255P_0r1[31:0], L255P_0a, reset);
tkl0x1 I93 (L268A_0r, L268A_0a, L268P_0r, L268P_0a, reset);
tkl2x1 I94 (shift_0r0[1:0], shift_0r1[1:0], shift_0a, L271_0r0[1:0], L271_0r1[1:0], L271_0a, reset);
tkl5x1 I95 (distanceI_0r0[4:0], distanceI_0r1[4:0], distanceI_0a, L272_0r0[4:0], L272_0r1[4:0], L272_0a, reset);
tkl32x1 I96 (L274A_0r0[31:0], L274A_0r1[31:0], L274A_0a, L274P_0r0[31:0], L274P_0r1[31:0], L274P_0a, reset);
tkl32x1 I97 (L276A_0r0[31:0], L276A_0r1[31:0], L276A_0a, L276P_0r0[31:0], L276P_0r1[31:0], L276P_0a, reset);
tkl32x1 I98 (L278A_0r0[31:0], L278A_0r1[31:0], L278A_0a, L278P_0r0[31:0], L278P_0r1[31:0], L278P_0a, reset);
tkl32x1 I99 (L280A_0r0[31:0], L280A_0r1[31:0], L280A_0a, L280P_0r0[31:0], L280P_0r1[31:0], L280P_0a, reset);
tkl32x1 I100 (L281A_0r0[31:0], L281A_0r1[31:0], L281A_0a, L281P_0r0[31:0], L281P_0r1[31:0], L281P_0a, reset);
tkl0x1 I101 (L282A_0r, L282A_0a, L282P_0r, L282P_0a, reset);
tkl32x1 I102 (L283_0r0[31:0], L283_0r1[31:0], L283_0a, result_0r0[31:0], result_0r1[31:0], result_0a, reset);
tkl32x1 I103 (arg_0r0[31:0], arg_0r1[31:0], arg_0a, L290_0r0[31:0], L290_0r1[31:0], L290_0a, reset);
tkl7x1 I104 (L306A_0r0[6:0], L306A_0r1[6:0], L306A_0a, L306P_0r0[6:0], L306P_0r1[6:0], L306P_0a, reset);
tkl31x1 I105 (L323A_0r0[30:0], L323A_0r1[30:0], L323A_0a, L323P_0r0[30:0], L323P_0r1[30:0], L323P_0a, reset);
tkl31x1 I106 (L324A_0r0[30:0], L324A_0r1[30:0], L324A_0a, L324P_0r0[30:0], L324P_0r1[30:0], L324P_0a, reset);
tkl31x1 I107 (L325A_0r0[30:0], L325A_0r1[30:0], L325A_0a, L325P_0r0[30:0], L325P_0r1[30:0], L325P_0a, reset);
tkl30x1 I108 (L326A_0r0[29:0], L326A_0r1[29:0], L326A_0a, L326P_0r0[29:0], L326P_0r1[29:0], L326P_0a, reset);
tkl30x1 I109 (L327A_0r0[29:0], L327A_0r1[29:0], L327A_0a, L327P_0r0[29:0], L327P_0r1[29:0], L327P_0a, reset);
tkl30x1 I110 (L328A_0r0[29:0], L328A_0r1[29:0], L328A_0a, L328P_0r0[29:0], L328P_0r1[29:0], L328P_0a, reset);
tkl28x1 I111 (L329A_0r0[27:0], L329A_0r1[27:0], L329A_0a, L329P_0r0[27:0], L329P_0r1[27:0], L329P_0a, reset);
tkl28x1 I112 (L330A_0r0[27:0], L330A_0r1[27:0], L330A_0a, L330P_0r0[27:0], L330P_0r1[27:0], L330P_0a, reset);
tkl28x1 I113 (L331A_0r0[27:0], L331A_0r1[27:0], L331A_0a, L331P_0r0[27:0], L331P_0r1[27:0], L331P_0a, reset);
tkl24x1 I114 (L332A_0r0[23:0], L332A_0r1[23:0], L332A_0a, L332P_0r0[23:0], L332P_0r1[23:0], L332P_0a, reset);
tkl24x1 I115 (L333A_0r0[23:0], L333A_0r1[23:0], L333A_0a, L333P_0r0[23:0], L333P_0r1[23:0], L333P_0a, reset);
tkl24x1 I116 (L334A_0r0[23:0], L334A_0r1[23:0], L334A_0a, L334P_0r0[23:0], L334P_0r1[23:0], L334P_0a, reset);
tkl16x1 I117 (L335A_0r0[15:0], L335A_0r1[15:0], L335A_0a, L335P_0r0[15:0], L335P_0r1[15:0], L335P_0a, reset);
tkl16x1 I118 (L336A_0r0[15:0], L336A_0r1[15:0], L336A_0a, L336P_0r0[15:0], L336P_0r1[15:0], L336P_0a, reset);
tkl16x1 I119 (L337A_0r0[15:0], L337A_0r1[15:0], L337A_0a, L337P_0r0[15:0], L337P_0r1[15:0], L337P_0a, reset);
tkl0x1 I120 (L338A_0r, L338A_0a, L338P_0r, L338P_0a, reset);
tkl0x1 I121 (L339A_0r, L339A_0a, L339P_0r, L339P_0a, reset);
tkl0x1 I122 (L340A_0r, L340A_0a, L340P_0r, L340P_0a, reset);
tkl0x1 I123 (L341A_0r, L341A_0a, L341P_0r, L341P_0a, reset);
tkl0x1 I124 (L342A_0r, L342A_0a, L342P_0r, L342P_0a, reset);
tkl1x1 I125 (L346A_0r0, L346A_0r1, L346A_0a, L346P_0r0, L346P_0r1, L346P_0a, reset);
tkl1x1 I126 (L350A_0r0, L350A_0r1, L350A_0a, L350P_0r0, L350P_0r1, L350P_0a, reset);
tkl1x1 I127 (L354A_0r0, L354A_0r1, L354A_0a, L354P_0r0, L354P_0r1, L354P_0a, reset);
tkl1x1 I128 (L358A_0r0, L358A_0r1, L358A_0a, L358P_0r0, L358P_0r1, L358P_0a, reset);
tkl0x1 I129 (L359A_0r, L359A_0a, L359P_0r, L359P_0a, reset);
tkl7x1 I130 (L361A_0r0[6:0], L361A_0r1[6:0], L361A_0a, L361P_0r0[6:0], L361P_0r1[6:0], L361P_0a, reset);
tkl1x1 I131 (L362A_0r0, L362A_0r1, L362A_0a, L362P_0r0, L362P_0r1, L362P_0a, reset);
tkl0x1 I132 (L364A_0r, L364A_0a, L364P_0r, L364P_0a, reset);
tkl0x1 I133 (L366A_0r, L366A_0a, L366P_0r, L366P_0a, reset);
tkl0x1 I134 (L368A_0r, L368A_0a, L368P_0r, L368P_0a, reset);
tkl0x1 I135 (L370A_0r, L370A_0a, L370P_0r, L370P_0a, reset);
tkl0x1 I136 (L372A_0r, L372A_0a, L372P_0r, L372P_0a, reset);
tkl0x1 I137 (L373A_0r, L373A_0a, L373P_0r, L373P_0a, reset);
tkl0x1 I138 (L374A_0r, L374A_0a, L374P_0r, L374P_0a, reset);
tkl0x1 I139 (L375A_0r, L375A_0a, L375P_0r, L375P_0a, reset);
tkl0x1 I140 (L376A_0r, L376A_0a, L376P_0r, L376P_0a, reset);
tkl0x1 I141 (L377A_0r, L377A_0a, L377P_0r, L377P_0a, reset);
tkl0x1 I142 (L378A_0r, L378A_0a, L378P_0r, L378P_0a, reset);
tkl0x1 I143 (L379A_0r, L379A_0a, L379P_0r, L379P_0a, reset);
tkl0x1 I144 (L380A_0r, L380A_0a, L380P_0r, L380P_0a, reset);
tkl0x1 I145 (L381A_0r, L381A_0a, L381P_0r, L381P_0a, reset);
tkl0x1 I146 (L382A_0r, L382A_0a, L382P_0r, L382P_0a, reset);
tkl0x1 I147 (L383A_0r, L383A_0a, L383P_0r, L383P_0a, reset);
tkl0x1 I148 (L384A_0r, L384A_0a, L384P_0r, L384P_0a, reset);
tkl0x1 I149 (L385A_0r, L385A_0a, L385P_0r, L385P_0a, reset);
tkl0x1 I150 (L386A_0r, L386A_0a, L386P_0r, L386P_0a, reset);
tkl0x1 I151 (L387A_0r, L387A_0a, L387P_0r, L387P_0a, reset);
tkl2x1 I152 (L412A_0r0[1:0], L412A_0r1[1:0], L412A_0a, L412P_0r0[1:0], L412P_0r1[1:0], L412P_0a, reset);
tkl2x1 I153 (L418A_0r0[1:0], L418A_0r1[1:0], L418A_0a, L418P_0r0[1:0], L418P_0r1[1:0], L418P_0a, reset);
tkl2x1 I154 (L424A_0r0[1:0], L424A_0r1[1:0], L424A_0a, L424P_0r0[1:0], L424P_0r1[1:0], L424P_0a, reset);
tkl2x1 I155 (L430A_0r0[1:0], L430A_0r1[1:0], L430A_0a, L430P_0r0[1:0], L430P_0r1[1:0], L430P_0a, reset);
tkl2x1 I156 (L436A_0r0[1:0], L436A_0r1[1:0], L436A_0a, L436P_0r0[1:0], L436P_0r1[1:0], L436P_0a, reset);
tkl0x1 I157 (L438A_0r, L438A_0a, L438P_0r, L438P_0a, reset);
tkl0x1 I158 (L439A_0r, L439A_0a, L439P_0r, L439P_0a, reset);
tkl0x1 I159 (L440A_0r, L440A_0a, L440P_0r, L440P_0a, reset);
tkl0x1 I160 (L441A_0r, L441A_0a, L441P_0r, L441P_0a, reset);
tkl0x1 I161 (L442A_0r, L442A_0a, L442P_0r, L442P_0a, reset);
tkl1x1 I162 (L443A_0r0, L443A_0r1, L443A_0a, L443P_0r0, L443P_0r1, L443P_0a, reset);
tkl1x1 I163 (L444A_0r0, L444A_0r1, L444A_0a, L444P_0r0, L444P_0r1, L444P_0a, reset);
tkl1x1 I164 (L446A_0r0, L446A_0r1, L446A_0a, L446P_0r0, L446P_0r1, L446P_0a, reset);
tkl1x1 I165 (L447A_0r0, L447A_0r1, L447A_0a, L447P_0r0, L447P_0r1, L447P_0a, reset);
tkl1x1 I166 (L449A_0r0, L449A_0r1, L449A_0a, L449P_0r0, L449P_0r1, L449P_0a, reset);
tkl1x1 I167 (L450A_0r0, L450A_0r1, L450A_0a, L450P_0r0, L450P_0r1, L450P_0a, reset);
tkl1x1 I168 (L452A_0r0, L452A_0r1, L452A_0a, L452P_0r0, L452P_0r1, L452P_0a, reset);
tkl1x1 I169 (L453A_0r0, L453A_0r1, L453A_0a, L453P_0r0, L453P_0r1, L453P_0a, reset);
tkl1x1 I170 (L455A_0r0, L455A_0r1, L455A_0a, L455P_0r0, L455P_0r1, L455P_0a, reset);
tkl1x1 I171 (L456A_0r0, L456A_0r1, L456A_0a, L456P_0r0, L456P_0r1, L456P_0a, reset);
endmodule
// Netlist costs:
// teak_Shifter: AND2*3230 AO22*176 BUFF*2660 C2*312 C2R*2998 C3*1252 GND*93 INV*451 NAND2*325 NAND3*6 NOR2*183 NOR3*505 OR2*2680 OR3*5
// tkf0mo0w0_o0w0_o0w0_o0w0_o0w0: BUFF*5 C2*2 C3*1
// tkf1mo0w1_o0w0: BUFF*4 C3*1 OR2*1
// tkf32mo0w0_o0w32: BUFF*66 C3*1 OR2*1
// tkf7mo0w7_o4w1_o3w1_o2w1_o1w1_o0w1: BUFF*16 C2*10 C3*3 OR2*1
// tki: AND2*1 AO22*3 INV*3
// tkj0m0_0_0_0_0_0: BUFF*6 C2*1 C3*2
// tkj1m1_0: BUFF*5 C2*2
// tkj32m32_0: BUFF*129 C2*2
// tkj7m5_2_0: BUFF*29 C2*3 OR2*1
// tkl0x1: BUFF*1 C2R*1 INV*1
// tkl16x1: BUFF*1 C2*1 C2R*32 C3*7 INV*1 OR2*16
// tkl1x1: BUFF*1 C2R*2 INV*1 OR2*1
// tkl24x1: C2*1 C2R*48 C3*11 INV*1 OR2*24
// tkl28x1: BUFF*3 C2*1 C2R*56 C3*13 INV*1 OR2*28
// tkl2x1: C2*1 C2R*4 INV*1 OR2*2
// tkl30x1: BUFF*2 C2*1 C2R*60 C3*14 INV*1 OR2*30
// tkl31x1: BUFF*2 C2*2 C2R*62 C3*14 INV*1 OR2*31
// tkl32x1: BUFF*1 C2*3 C2R*64 C3*14 INV*1 OR2*32
// tkl5x1: C2*2 C2R*10 C3*1 INV*1 OR2*5
// tkl7x1: BUFF*1 C2R*14 C3*3 INV*1 OR2*7
// tkm4x32b: AND2*256 BUFF*4 C2*12 C2R*8 C3*56 INV*65 NAND2*65 NOR2*1 NOR3*65 OR2*128
// tko16m32_1nm16b0_2api0w16bt1o0w16b: BUFF*82 C2*1 C3*7 GND*16 OR2*16
// tko16m32_1nm16b0_2apt1o0w16bi0w16b: BUFF*82 C2*1 C3*7 GND*16 OR2*16
// tko16m32_1nm16bffff_2api0w16bt1o0w16b: BUFF*82 C2*1 C3*7 GND*16 OR2*16
// tko24m32_1nm8b0_2api0w24bt1o0w8b: BUFF*73 C2*1 C3*11 GND*8 OR2*24
// tko24m32_1nm8b0_2apt1o0w8bi0w24b: BUFF*73 C2*1 C3*11 GND*8 OR2*24
// tko24m32_1nm8bff_2api0w24bt1o0w8b: BUFF*73 C2*1 C3*11 GND*8 OR2*24
// tko28m32_1nm4b0_2api0w28bt1o0w4b: BUFF*72 C2*1 C3*13 GND*4 OR2*28
// tko28m32_1nm4b0_2apt1o0w4bi0w28b: BUFF*72 C2*1 C3*13 GND*4 OR2*28
// tko28m32_1nm4bf_2api0w28bt1o0w4b: BUFF*72 C2*1 C3*13 GND*4 OR2*28
// tko30m32_1nm2b0_2api0w30bt1o0w2b: BUFF*69 C2*1 C3*14 GND*2 OR2*30
// tko30m32_1nm2b0_2apt1o0w2bi0w30b: BUFF*69 C2*1 C3*14 GND*2 OR2*30
// tko30m32_1nm2b3_2api0w30bt1o0w2b: BUFF*69 C2*1 C3*14 GND*2 OR2*30
// tko31m32_1nm1b0_2api0w31bt1o0w1b: BUFF*68 C2*2 C3*14 GND*1 OR2*31
// tko31m32_1nm1b0_2apt1o0w1bi0w31b: BUFF*68 C2*2 C3*14 GND*1 OR2*31
// tko31m32_1nm1b1_2api0w31bt1o0w1b: BUFF*68 C2*2 C3*14 GND*1 OR2*31
// tks1_o0w1_0o0w0_1o0w0: BUFF*7 C2*3 OR2*2
// tks2_o0w2_3o0w0_0c2o0w0_1o0w0: BUFF*7 C2*7 OR2*2 OR3*1
// tkvdistanceIshift7_wo0w7_ro5w2o5w2o5w2o5w2o5w2: AND2*55 AO22*8 BUFF*29 C2*1 C3*6 INV*3 NAND3*1 NOR2*8 NOR3*10 OR2*8
// tkvi32_wo0w32_ro0w32o0w16o16w16o16w16: AND2*320 AO22*33 BUFF*104 C2*5 C3*29 INV*1 NAND3*1 NOR2*34 NOR3*34 OR2*32
// tkvi32_wo0w32_ro0w32o0w24o8w24o8w24: AND2*368 AO22*33 BUFF*104 C2*5 C3*29 INV*1 NAND3*1 NOR2*34 NOR3*34 OR2*32
// tkvi32_wo0w32_ro0w32o0w28o4w28o4w28: AND2*392 AO22*33 BUFF*104 C2*5 C3*29 INV*1 NAND3*1 NOR2*34 NOR3*34 OR2*32
// tkvi32_wo0w32_ro0w32o0w30o2w30o2w30: AND2*404 AO22*33 BUFF*104 C2*5 C3*29 INV*1 NAND3*1 NOR2*34 NOR3*34 OR2*32
// tkvi32_wo0w32_ro0w32o0w31o1w31o1w31: AND2*410 AO22*33 BUFF*104 C2*5 C3*29 INV*1 NAND3*1 NOR2*34 NOR3*34 OR2*32
|
module top;
reg pass;
real a, b;
integer i;
wire real b1 = 42.0 + 10/100;
wire real b2 = a + 10/100;
wire real b3 = 42.0 + i/100;
wire real b4 = a + i/100;
initial begin
pass = 1'b1;
// Check the compiler for the whole expression.
b = 42.0 + 10/100;
if (b != 42.0) begin
$display("FAILED: compiler constant, expected 42.0, got %6.1f", b);
pass = 1'b0;
end
// Check the compiler for just the division.
a = 42;
b = a + 10/100;
if (b != 42.0) begin
$display("FAILED: compiler constant div., expected 42.0, got %6.1f", b);
pass = 1'b0;
end
// Check the run time with a constant sum value (just the division).
i = 10;
b = 42.0 + i/100;
if (b != 42.0) begin
$display("FAILED: runtime constant real, expected 42.0, got %6.1f", b);
pass = 1'b0;
end
// Check the original expression.
b = a + i/100;
if (b != 42.0) begin
$display("FAILED: runtime, expected 42.0, got %6.1f", b);
pass = 1'b0;
end
// Check the ternary operator with one clause needing to be converted.
b = (i === 10) ? i/100 : 1.0;
if (b != 0.0) begin
$display("FAILED: runtime (ternary), expected 0.0, got %6.1f", b);
pass = 1'b0;
end
b = |i;
if (b != 1.0) begin
$display("FAILED: runtime (reduction), expected 1.0, got %6.1f", b);
pass = 1'b0;
end
// Check the continuous assigns.
#1;
if (b1 != 42.0) begin
$display("FAILED: CA test 1, expected 42.0, got %6.1f", b1);
pass = 1'b0;
end
if (b2 != 42.0) begin
$display("FAILED: CA test 2, expected 42.0, got %6.1f", b2);
pass = 1'b0;
end
if (b3 != 42.0) begin
$display("FAILED: CA test 3, expected 42.0, got %6.1f", b3);
pass = 1'b0;
end
if (b4 != 42.0) begin
$display("FAILED: CA test 4, expected 42.0, got %6.1f", b4);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
//////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2012 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 14.5
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Configuration Simulation Model
// /___/ /\ Filename : SIM_CONFIGE3.v
// \ \ / \ Timestamp :
// \___\/\___\
//
// Revision:
// 10/31/12 - Initial version
// 09/09/13 - Fixed output IDCODE (CR 727695).
// 10/23/13 - Fixed IDCODE when ICAP_WIDTH = X16 (CR 737079).
// 02/14/14 - Fixed Non-Continous data loading problem (CR 690809).
// 05/28/14 - New simulation library message format.
// End Revision
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module SIM_CONFIGE3 (
AVAIL,
CSOB,
PRDONE,
PRERROR,
DONE,
CCLK,
CSB,
D,
INITB,
M,
PROGB,
RDWRB
);
output AVAIL;
output CSOB;
output PRDONE;
output PRERROR;
inout DONE;
input CCLK;
input CSB;
inout [31:0] D;
inout INITB;
input [2:0] M;
input PROGB;
input RDWRB;
parameter DEVICE_ID = 32'h0;
parameter ICAP_SUPPORT = "FALSE";
parameter ICAP_WIDTH = "X8";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif //
localparam FRAME_RBT_OUT_FILENAME = "frame_data_e2_rbt_out.txt";
localparam cfg_Tprog = 250000; // min PROG must be low
localparam cfg_Tpl = 100000; // max program latency us.
localparam STARTUP_PH0 = 3'b000;
localparam STARTUP_PH1 = 3'b001;
localparam STARTUP_PH2 = 3'b010;
localparam STARTUP_PH3 = 3'b011;
localparam STARTUP_PH4 = 3'b100;
localparam STARTUP_PH5 = 3'b101;
localparam STARTUP_PH6 = 3'b110;
localparam STARTUP_PH7 = 3'b111;
// tri0 GSR, GTS, GWE;
wire GSR;
wire GTS;
wire GWE;
wire cclk_in;
wire init_b_in;
wire prog_b_in;
wire rdwr_b_in;
reg rdwr_b_in1;
reg checka_en = 0;
reg init_b_out = 1;
reg [3:0] done_o = 4'b0;
integer frame_data_fd;
integer farn = 0;
integer ib, ib_skp, ci, bi;
reg frame_data_wen = 0;
tri1 p_up;
reg por_b;
wire [2:0] m_in;
wire [31:0] d_in;
wire [31:0] d_out;
wire busy_out;
wire cso_b_out;
wire csi_b_in;
reg csi_b_ins = 1;
wire d_out_en;
wire pll_locked;
reg pll_lockwt;
wire init_b_t;
wire prog_b_t;
wire bus_en;
wire [3:0] desync_flag;
wire [3:0] crc_rst;
reg [3:0] crc_bypass = 0;
reg icap_on = 0;
reg icap_clr = 0;
reg icap_sync = 0;
reg icap_desynch = 0;
reg rd_desynch = 0;
reg rd_desynch_tmp = 0;
reg icap_init_done = 0;
reg icap_init_done_dly = 0;
wire [3:0] desynch_set1;
reg [1:0] icap_bw = 2'b00;
assign DONE = p_up;
assign INITB = p_up;
assign glbl.GSR = GSR;
assign glbl.GTS = GTS;
assign glbl.PROGB_GLBL = PROGB;
assign pll_locked = (glbl.PLL_LOCKG === 0) ? 0 : 1;
buf buf_cso (CSOB, cso_b_out);
buf buf_cclk (cclk_in, CCLK);
buf buf_cs (csi_b_in, CSB);
buf buf_din[31:0] (d_in, D);
bufif1 buf_dout[31:0] (D, d_out, d_out_en);
buf buf_init (init_b_in, INITB);
buf buf_m_0 (m_in[0], M[0]);
buf buf_m_1 (m_in[1], M[1]);
buf buf_m_2 (m_in[2], M[2]);
buf buf_prog (prog_b_in, PROGB);
buf buf_rw (rdwr_b_in, RDWRB);
time prog_pulse_low_edge = 0;
time prog_pulse_low = 0;
reg mode_sample_flag = 0;
reg [3:0] buswid_flag_init = 4'b0;
reg [3:0] buswid_flag = 4'b0;
reg [1:0] buswidth[3:0];
wire [1:0] buswidth_ibtmp;
reg [1:0] buswidth_tmp[3:0];
reg [31:0] pack_in_reg[3:0];
reg [31:0] pack_in_reg_tmp0 = 32'b0;
reg [31:0] pack_in_reg_tmps0 = 32'b0;
reg [31:0] pack_in_reg_tmp = 32'b0;
reg [4:0] reg_addr[3:0];
reg [4:0] reg_addr_tmp;
reg [3:0] new_data_in_flag = 4'b0;
reg [3:0] wr_flag = 4'b0;
reg [3:0] rd_flag = 4'b0;
reg [3:0] cmd_wr_flag = 4'b0;
reg [3:0] cmd_reg_new_flag = 4'b0;
reg [3:0] cmd_rd_flag = 4'b0;
reg [3:0] bus_sync_flag = 4'b0;
reg [3:0] conti_data_flag = 4'b0;
integer wr_cnt[3:0];
integer conti_data_cnt[3:0];
integer rd_data_cnt[3:0];
integer abort_cnt;
reg [2:0] st_state0 = STARTUP_PH0;
reg [2:0] st_state1 = STARTUP_PH0;
reg [2:0] st_state2 = STARTUP_PH0;
reg [2:0] st_state3 = STARTUP_PH0;
reg [2:0] st_state0i = STARTUP_PH0;
reg [2:0] st_state1i = STARTUP_PH0;
reg [2:0] st_state2i = STARTUP_PH0;
reg [2:0] st_state3i = STARTUP_PH0;
reg startup_begin_flag0 = 0;
reg startup_end_flag0 = 0;
reg startup_begin_flag1 = 0;
reg startup_end_flag1 = 0;
reg startup_begin_flag2 = 0;
reg startup_end_flag2 = 0;
reg startup_begin_flag3 = 0;
reg startup_end_flag3 = 0;
reg [3:0] crc_ck = 4'b0;
reg [3:0] crc_ck_en = 4'b1111;
reg [3:0] crc_err_flag = 4'b0;
wire [3:0] crc_err_flag_tot;
reg [3:0] crc_err_flag_reg = 4'b0;
wire [3:0] crc_en;
reg [31:0] crc_curr[3:0];
reg [31:0] crc_curr_tmp;
wire [31:0] crc_curr_cktmp;
reg [31:0] crc_new;
reg [36:0] crc_input;
reg [31:0] rbcrc_curr[3:0];
reg [31:0] rbcrc_new;
reg [36:0] rbcrc_input;
reg [3:0] gwe_out = 4'b0;
reg [3:0] gts_out = 4'b1111;
reg [31:0] d_o = 32'h0;
reg [31:0] outbus = 32'h0;
reg [31:0] outbus_dly = 32'h0;
reg [31:0] outbus_dly1 = 32'h0;
reg busy_o = 0;
reg [31:0] tmp_val1;
reg [31:0] tmp_val2;
reg [31:0] crc_reg[3:0];
reg [31:0] crc_reg_tmp;
wire [31:0] crc_reg_cktmp;
reg [31:0] far_reg[3:0];
reg [31:0] far_addr;
reg [31:0] fdri_reg[3:0];
reg [31:0] fdro_reg[3:0];
reg [4:0] cmd_reg[3:0];
reg [31:0] ctl0_reg[3:0];
reg [31:0] mask_reg[3:0];
wire [31:0] stat_reg[3:0];
wire [31:0] stat_reg_tmp0;
wire [31:0] stat_reg_tmp1;
wire [31:0] stat_reg_tmp2;
wire [31:0] stat_reg_tmp3;
reg [31:0] lout_reg[3:0];
reg [31:0] cor0_reg[3:0];
reg [31:0] cor0_reg_tmp0 = 32'b00000000000000000011111111101100;
reg [31:0] cor0_reg_tmp1 = 32'b00000000000000000011111111101100;
reg [31:0] cor0_reg_tmp2 = 32'b00000000000000000011111111101100;
reg [31:0] cor0_reg_tmp3 = 32'b00000000000000000011111111101100;
reg [31:0] mfwr_reg[3:0];
reg [31:0] cbc_reg[3:0];
reg [31:0] idcode_reg[3:0];
reg [31:0] axss_reg[3:0];
reg [31:0] cor1_reg[3:0];
reg [31:0] cor1_reg_tmp0 = 32'b0;
reg [31:0] cor1_reg_tmp1 = 32'b0;
reg [31:0] cor1_reg_tmp2 = 32'b0;
reg [31:0] cor1_reg_tmp3 = 32'b0;
reg [31:0] csob_reg[3:0];
reg [31:0] wbstar_reg[3:0];
reg [31:0] timer_reg[3:0];
reg [31:0] rbcrc_hw_reg[3:0];
reg [31:0] rbcrc_sw_reg[3:0];
reg [31:0] rbcrc_live_reg[3:0];
reg [31:0] efar_reg[3:0];
reg [31:0] bootsts_reg[3:0];
reg [31:0] ctl1_reg[3:0];
reg [31:0] testmode_reg[3:0];
reg [31:0] memrd_param_reg[3:0];
reg [31:0] dwc_reg[3:0];
reg [31:0] trim_reg[3:0];
reg [31:0] bout_reg[3:0];
reg [31:0] bspi_reg[3:0];
reg [2:0] mode_pin_in = 3'b0;
reg [2:0] mode_reg;
reg [3:0] crc_reset = 4'b0;
reg [3:0] gsr_set = 4'b0;
reg [3:0] gts_usr_b = 4'b111;
reg [3:0] done_pin_drv = 4'b0;
reg [3:0] shutdown_set = 4'b0;
reg [3:0] desynch_set = 4'b0;
reg [2:0] done_cycle_reg0 = 3'b011;
reg [2:0] done_cycle_reg1 = 3'b011;
reg [2:0] done_cycle_reg2 = 3'b011;
reg [2:0] done_cycle_reg3 = 3'b011;
reg [2:0] gts_cycle_reg0 = 3'b101;
reg [2:0] gts_cycle_reg1 = 3'b101;
reg [2:0] gts_cycle_reg2 = 3'b101;
reg [2:0] gts_cycle_reg3 = 3'b101;
reg [2:0] gwe_cycle_reg0 = 3'b100;
reg [2:0] gwe_cycle_reg1 = 3'b100;
reg [2:0] gwe_cycle_reg2 = 3'b100;
reg [2:0] gwe_cycle_reg3 = 3'b100;
reg init_pin;
reg init_rst = 0;
reg [2:0] nx_st_state0 = 3'b0;
reg [2:0] nx_st_state1 = 3'b0;
reg [2:0] nx_st_state2 = 3'b0;
reg [2:0] nx_st_state3 = 3'b0;
reg [3:0] ghigh_b = 4'b0;
reg [3:0] gts_cfg_b = 4'b0;
reg [3:0] eos_startup = 4'b0;
reg [3:0] startup_set = 4'b0;
reg [1:0] startup_set_pulse0 = 2'b0;
reg [1:0] startup_set_pulse1 = 2'b0;
reg [1:0] startup_set_pulse2 = 2'b0;
reg [1:0] startup_set_pulse3 = 2'b0;
reg abort_out_en = 0;
reg [31:0] tmp_dword;
reg [15:0] tmp_word;
reg [7:0] tmp_byte;
reg [3:0] id_error_flag = 4'b0;
wire id_error_flag_t;
reg [3:0] iprog_b = 4'b1111;
wire iprog_b_t;
reg [3:0] i_init_b_cmd = 4'b1111;
wire i_init_b_cmd_t;
reg i_init_b = 0;
reg [7:0] abort_status = 8'b0;
reg [3:0] persist_en = 0;
reg [3:0] rst_sync = 0;
reg [3:0] abort_dis = 0;
reg [2:0] lock_cycle_reg0 = 3'b0;
reg [2:0] lock_cycle_reg1 = 3'b0;
reg [2:0] lock_cycle_reg2 = 3'b0;
reg [2:0] lock_cycle_reg3 = 3'b0;
reg [3:0] rbcrc_no_pin = 4'b0;
reg abort_flag_rst = 0;
reg [3:0] gsr_st_out = 4'b1111;
reg [3:0] gsr_cmd_out = 4'b0;
reg [3:0] gsr_cmd_out_pulse = 4'b0;
reg d_o_en = 0;
wire rst_intl;
wire rw_en_tmp1;
wire [3:0] rw_en;
wire [3:0] gsr_out;
wire [3:0] cfgerr_b_flag;
reg [3:0] abort_flag = 4'b0;
integer downcont_cnt = 0;
reg rst_en = 0;
reg prog_b_a = 1;
reg [3:0] csbo_flag = 4'b0;
reg [3:0] bout_flag = 4'b0;
reg [3:0] bout_flags = 4'b0;
reg [3:0] bout_bf = 4'b0;
reg [3:0] bout_en = 4'b0001;
reg rd_sw_en = 0;
integer csbo_cnt[3:0];
integer bout_cnt[3:0];
integer bout_cnt_tmp;
reg [4:0] rd_reg_addr[3:0];
reg done_release = 0;
triand (weak1, strong0) INITB=(mode_sample_flag) ? ~crc_err_flag_tot[ib] : init_b_out;
triand (weak1, strong0) DONE= done_o[0];
assign DONE= (bout_en[1] == 1) ? done_o[1] : p_up;
assign DONE= (bout_en[2] == 1) ? done_o[2] : p_up;
assign DONE= (bout_en[3] == 1) ? done_o[3] : p_up;
reg PRDONE = 0;
reg fdri_rst_prdone_flag = 0;
localparam MODULE_NAME = "SIM_CONFIGE3";
always @(fdri_rst_prdone_flag)
PRDONE = 1'b0;
always @(desync_flag or eos_startup)
if ((&desync_flag) & (&eos_startup)) begin
PRDONE = 1'b1;
end
assign PRERROR = (|rw_en) & (|crc_err_flag_tot);
initial begin
if (DEVICE_ID == "036A2093" || DEVICE_ID == "03702093")
bout_en = 4'b0011;
else if (DEVICE_ID == "036A4093" || DEVICE_ID == "03704093")
bout_en = 4'b0111;
else if (DEVICE_ID == "036A6093")
bout_en = 4'b1111;
end
initial begin
buswidth_tmp[0] = 2'b00;
buswidth_tmp[1] = 2'b00;
buswidth_tmp[2] = 2'b00;
buswidth_tmp[3] = 2'b00;
pack_in_reg[0] = 32'b0;
pack_in_reg[1] = 32'b0;
pack_in_reg[2] = 32'b0;
pack_in_reg[3] = 32'b0;
pack_in_reg_tmp0 = 32'b0;
pack_in_reg_tmps0 = 32'b0;
pack_in_reg_tmp = 32'b0;
crc_curr[0] = 32'b0;
crc_curr[1] = 32'b0;
crc_curr[2] = 32'b0;
crc_curr[3] = 32'b0;
rbcrc_curr[0] = 32'b0;
rbcrc_curr[1] = 32'b0;
rbcrc_curr[2] = 32'b0;
rbcrc_curr[3] = 32'b0;
ctl0_reg[0] = 32'b000xxxxxxxxxxxxxx000000100000xx1;
ctl0_reg[1] = 32'b000xxxxxxxxxxxxxx000000100000xx1;
ctl0_reg[2] = 32'b000xxxxxxxxxxxxxx000000100000xx1;
ctl0_reg[3] = 32'b000xxxxxxxxxxxxxx000000100000xx1;
cor0_reg[0] = 32'b00000000000000000011111111101100;
cor0_reg[1] = 32'b00000000000000000011111111101100;
cor0_reg[2] = 32'b00000000000000000011111111101100;
cor0_reg[3] = 32'b00000000000000000011111111101100;
cor0_reg_tmp0 = cor0_reg[0];
done_cycle_reg0 = cor0_reg_tmp0[14:12];
lock_cycle_reg0 = cor0_reg_tmp0[8:6];
done_cycle_reg1 = cor0_reg_tmp0[14:12];
lock_cycle_reg1 = cor0_reg_tmp0[8:6];
done_cycle_reg2 = cor0_reg_tmp0[14:12];
lock_cycle_reg2 = cor0_reg_tmp0[8:6];
done_cycle_reg3 = cor0_reg_tmp0[14:12];
lock_cycle_reg3 = cor0_reg_tmp0[8:6];
cor1_reg[0] = 32'b0;
cor1_reg[1] = 32'b0;
cor1_reg[2] = 32'b0;
cor1_reg[3] = 32'b0;
wbstar_reg[0] = 32'b0;
wbstar_reg[1] = 32'b0;
wbstar_reg[2] = 32'b0;
wbstar_reg[3] = 32'b0;
timer_reg[0] = 32'b0;
timer_reg[1] = 32'b0;
timer_reg[2] = 32'b0;
timer_reg[3] = 32'b0;
bootsts_reg[0] = 32'b0;
bootsts_reg[1] = 32'b0;
bootsts_reg[2] = 32'b0;
bootsts_reg[3] = 32'b0;
ctl1_reg[0] = 32'b0;
ctl1_reg[1] = 32'b0;
ctl1_reg[2] = 32'b0;
ctl1_reg[3] = 32'b0;
testmode_reg[0] = 32'b0;
testmode_reg[1] = 32'b0;
testmode_reg[2] = 32'b0;
testmode_reg[3] = 32'b0;
memrd_param_reg[0] = 32'b0;
memrd_param_reg[1] = 32'b0;
memrd_param_reg[2] = 32'b0;
memrd_param_reg[3] = 32'b0;
dwc_reg[0] = 32'b0;
dwc_reg[1] = 32'b0;
dwc_reg[2] = 32'b0;
dwc_reg[3] = 32'b0;
trim_reg[0] = 32'b0;
trim_reg[1] = 32'b0;
trim_reg[2] = 32'b0;
trim_reg[3] = 32'b0;
bout_reg[0] = 32'b0;
bout_reg[1] = 32'b0;
bout_reg[2] = 32'b0;
bout_reg[3] = 32'b0;
bspi_reg[0] = 32'h000B;
bspi_reg[1] = 32'h000B;
bspi_reg[2] = 32'h000B;
bspi_reg[3] = 32'h000B;
rd_reg_addr[0] = 5'b0;
rd_reg_addr[1] = 5'b0;
rd_reg_addr[2] = 5'b0;
rd_reg_addr[3] = 5'b0;
wr_cnt[0] = 0;
wr_cnt[1] = 0;
wr_cnt[2] = 0;
wr_cnt[3] = 0;
bout_cnt[0] = 0;
bout_cnt[1] = 0;
bout_cnt[2] = 0;
bout_cnt[3] = 0;
done_o = 4'b0;
end
initial begin
case (ICAP_SUPPORT)
"FALSE" : icap_on = 0;
"TRUE" : icap_on = 1;
default : icap_on = 0;
endcase
if (DEVICE_ID == 32'h0 && icap_on == 0) begin
$display("Error: [Unisim %s-1] DEVICE_ID attribute is not set. Instance: %m", MODULE_NAME);
end
if (ICAP_SUPPORT == "TRUE") begin
case (ICAP_WIDTH)
"X8" : icap_bw = 2'b01;
"X16" : icap_bw = 2'b10;
"X32" : icap_bw = 2'b11;
default : icap_bw = 2'b01;
endcase
frame_data_fd = $fopen(FRAME_RBT_OUT_FILENAME, "w");
if (frame_data_fd != 0) begin
frame_data_wen = 1;
$fwriteh(frame_data_fd, "frame_address frame_data readback_crc_value\n");
end
end
else begin
icap_bw = 2'b00;
frame_data_wen = 0;
end
icap_sync = 0;
end
assign GSR = gsr_out[0];
assign GTS = gts_out[0];
assign GWE = gwe_out[0];
assign busy_out = busy_o;
assign cfgerr_b_flag[0] = rw_en[0] & ~crc_err_flag_tot[0];
assign cfgerr_b_flag[1] = rw_en[1] & ~crc_err_flag_tot[1];
assign cfgerr_b_flag[2] = rw_en[2] & ~crc_err_flag_tot[2];
assign cfgerr_b_flag[3] = rw_en[3] & ~crc_err_flag_tot[3];
assign crc_err_flag_tot[0] = id_error_flag[0] | crc_err_flag_reg[0];
assign crc_err_flag_tot[1] = id_error_flag[1] | crc_err_flag_reg[1];
assign crc_err_flag_tot[2] = id_error_flag[2] | crc_err_flag_reg[2];
assign crc_err_flag_tot[3] = id_error_flag[3] | crc_err_flag_reg[3];
assign d_out[7:0] = (abort_out_en ) ? abort_status : outbus_dly[7:0];
assign d_out[31:8] = (abort_out_en ) ? 24'b0 : outbus_dly[31:8];
assign d_out_en = d_o_en;
assign cso_b_out = (csbo_flag[0] == 1) ? 0 : 1;
assign crc_en = (icap_init_done) ? 4'b0 : 4'b1111;
always @(posedge cclk_in) begin
outbus_dly <= outbus_dly1;
outbus_dly1 <= outbus;
end
always @(posedge cclk_in or csi_b_in)
if (csi_b_in == 1)
csi_b_ins <= csi_b_in;
else begin
if (cclk_in != 1)
csi_b_ins <= csi_b_in;
else
@(negedge cclk_in)
csi_b_ins <= csi_b_in;
end
always @(abort_out_en or csi_b_in or rdwr_b_in && rd_flag[ib] )
if (abort_out_en == 1)
d_o_en = 1;
else
d_o_en = rdwr_b_in & ~csi_b_in & rd_flag[ib];
assign init_b_t = init_b_in & i_init_b_cmd_t;
always @( negedge prog_b_in) begin
rst_en = 0;
rst_en <= #cfg_Tprog 1;
end
assign iprog_b_0 = iprog_b[0];
assign iprog_b_1 = (bout_en[1] == 1) ? iprog_b[1] : 1;
assign iprog_b_2 = (bout_en[2] == 1) ? iprog_b[2] : 1;
assign iprog_b_3 = (bout_en[3] == 1) ? iprog_b[3] : 1;
assign iprog_b_t = iprog_b_3 & iprog_b_2 & iprog_b_1 & iprog_b_0;
assign i_init_b_cmd_0 = i_init_b_cmd[0];
assign i_init_b_cmd_1 = (bout_en[1] == 1) ? i_init_b_cmd[1] : 1;
assign i_init_b_cmd_2 = (bout_en[2] == 1) ? i_init_b_cmd[2] : 1;
assign i_init_b_cmd_3 = (bout_en[3] == 1) ? i_init_b_cmd[3] : 1;
assign i_init_b_cmd_t = i_init_b_cmd_0 & i_init_b_cmd_1 & i_init_b_cmd_2
& i_init_b_cmd_3;
always @( rst_en or init_rst or prog_b_in or iprog_b_t )
if (icap_on == 0) begin
if (init_rst == 1)
init_b_out <= 0;
else begin
if ((prog_b_in == 0 ) && (rst_en == 1) || (iprog_b_t == 0))
init_b_out <= 0;
else if ((prog_b_in == 1 ) && (rst_en == 1) || (iprog_b_t == 1))
init_b_out <= #(cfg_Tpl) 1;
end
end
assign id_error_flag_t = &id_error_flag;
always @(posedge id_error_flag_t) begin
init_rst <= 1;
init_rst <= #cfg_Tprog 0;
end
always @( rst_en or prog_b_in or prog_pulse_low)
if (rst_en == 1) begin
if (prog_pulse_low==cfg_Tprog) begin
prog_b_a = 0;
prog_b_a <= #500 1;
end
else
prog_b_a = prog_b_in;
end
else
prog_b_a = 1;
initial begin
por_b = 0;
por_b = #400000 1;
end
assign prog_b_t = prog_b_a & iprog_b_t & por_b;
assign rst_intl = (prog_b_t==0 ) ? 0 : 1;
always @( init_b_t or prog_b_t)
if (prog_b_t == 0)
mode_sample_flag <= 0;
else if (init_b_t && mode_sample_flag == 0) begin
if (prog_b_t == 1) begin
mode_pin_in <= m_in;
if (m_in !== 3'b110) begin
mode_sample_flag <= 0;
if ( icap_on == 0)
$display("Error: [Unisim %s-2] Input M is %h. Only Slave SelectMAP mode M=110 is supported. Instance %m.", MODULE_NAME, m_in);
end
else
mode_sample_flag <= #1 1;
end
end
always @(posedge init_b_t )
if (prog_b_t != 1) begin
if ($time != 0 && icap_on == 0)
$display("Error: [Unisim %s-3] PROGB is not high when INITB goes high at time %t. Instance %m.", MODULE_NAME, $time);
end
always @(m_in)
if (mode_sample_flag == 1 && persist_en[0] == 1 && icap_on == 0)
$display("Error: [Unisim %s-4] Mode pine M[2:0] changed after rising edge of INITB at time %t. Instance %m.", MODULE_NAME, $time);
always @(posedge prog_b_in or negedge prog_b_in)
if (prog_b_in == 0)
prog_pulse_low_edge <= $time;
else if (prog_b_in == 1 && $time > 0) begin
prog_pulse_low = $time - prog_pulse_low_edge;
if (prog_pulse_low < cfg_Tprog && icap_on == 0)
$display("Error: [Unisim %s-5] Low time of PROGB is less than required minimum Tprogram time %d at time %t. Instance %m.", MODULE_NAME, cfg_Tprog, $time);
end
assign bus_en = (mode_sample_flag == 1 && csi_b_in ==0) ? 1 : 0;
always @(posedge cclk_in or negedge rst_intl )
if (rst_intl == 0 ) begin
buswid_flag_init <= 4'b0;
buswid_flag <= 4'b0;
buswidth_tmp[0] <= 2'b00;
buswidth_tmp[1] <= 2'b00;
buswidth_tmp[2] <= 2'b00;
buswidth_tmp[3] <= 2'b00;
end
else
if (buswid_flag[ib] == 0) begin
if (bus_en == 1 && rdwr_b_in == 0) begin
tmp_byte = bit_revers8(d_in[7:0]);
if (buswid_flag_init[ib] == 0) begin
if (tmp_byte == 8'hBB)
buswid_flag_init[ib] <= 1;
end
else begin
if (tmp_byte == 8'h11) begin // x8
buswid_flag[ib] <= 1;
buswidth_tmp[ib] <= 2'b01;
end
else if (tmp_byte == 8'h22) begin // x16
buswid_flag[ib] <= 1;
buswidth_tmp[ib] <= 2'b10;
end
else if (tmp_byte == 8'h44) begin // x32
buswid_flag[ib] <= 1;
buswidth_tmp[ib] <= 2'b11;
end
else begin
buswid_flag[ib] <= 0;
buswidth_tmp[ib] <= 2'b00;
buswid_flag_init[ib] <= 0;
if (icap_on == 0)
$display("Error: [Unisim %s-6] BUS Width Auto Dection did not find 0x11 or 0x22 or 0x44 on D[7:0] followed 0xBB at time %t. Instance %m.", MODULE_NAME, $time);
else
$display("Error: [Unisim %s-7] BUS Width Auto Dection did not find 0x11 or 0x22 or 0x44 on dix[7:0] followed 0xBB on ICAPE3 instance at time %t. Instance %m.", MODULE_NAME, $time);
end
end
end
end
assign buswidth_ibtmp = (icap_on == 1 && icap_init_done == 1) ? icap_bw[1:0] : buswidth_tmp[ib];
always @(buswidth_ibtmp)
buswidth[ib] = buswidth_ibtmp;
assign rw_en_tmp = (bus_en == 1 ) ? 1 : 0;
assign rw_en[0] = ( buswid_flag[0] == 1) ? rw_en_tmp : 0;
assign rw_en[1] = ( buswid_flag[1] == 1) ? rw_en_tmp : 0;
assign rw_en[2] = ( buswid_flag[2] == 1) ? rw_en_tmp : 0;
assign rw_en[3] = ( buswid_flag[3] == 1) ? rw_en_tmp : 0;
assign desynch_set1[0] = desynch_set[0] | icap_desynch | rd_desynch;
assign desynch_set1[1] = desynch_set[1] | icap_desynch | rd_desynch;
assign desynch_set1[2] = desynch_set[2] | icap_desynch | rd_desynch;
assign desynch_set1[3] = desynch_set[3] | icap_desynch | rd_desynch;
assign desync_flag[0] = ~rst_intl | desynch_set1[0] | crc_err_flag[0] | id_error_flag[0];
assign desync_flag[1] = ~rst_intl | desynch_set1[1] | crc_err_flag[1] | id_error_flag[1];
assign desync_flag[2] = ~rst_intl | desynch_set1[2] | crc_err_flag[2] | id_error_flag[2];
assign desync_flag[3] = ~rst_intl | desynch_set1[3] | crc_err_flag[3] | id_error_flag[3];
always @(posedge eos_startup[0])
if (icap_on == 1) begin
$fclose(frame_data_fd);
icap_init_done <= 1;
@(posedge cclk_in);
@(posedge cclk_in)
if (icap_init_done_dly == 0)
icap_desynch <= 1;
@(posedge cclk_in);
@(posedge cclk_in) begin
icap_desynch <= 0;
icap_init_done_dly <= 1;
end
@(posedge cclk_in);
@(posedge cclk_in);
@(posedge cclk_in);
end
else begin
icap_clr <= 0;
icap_desynch <= 0;
end
always @(posedge cclk_in or negedge rdwr_b_in)
if (rdwr_b_in == 0)
rd_sw_en <= 0;
else begin
if (csi_b_in == 1 && rdwr_b_in ==1)
rd_sw_en <= 1;
end
assign desync_flag_t = |desync_flag;
always @(posedge cclk_in or posedge desync_flag_t or negedge csi_b_in) begin
if (desync_flag[ib] == 1) begin
pack_in_reg_tmp0 = 32'b0;
pack_in_reg_tmps0 = 32'b0;
end
if (desync_flag[0] == 1 ) begin
new_data_in_flag[0] = 0;
bus_sync_flag[0] = 0;
wr_cnt[0] = 0;
wr_flag[0] = 0;
rd_flag[0] = 0;
end
if (desync_flag[1] == 1 ) begin
new_data_in_flag[1] = 0;
bus_sync_flag[1] = 0;
wr_cnt[1] = 0;
wr_flag[1] = 0;
rd_flag[1] = 0;
end
if (desync_flag[2] == 1 ) begin
new_data_in_flag[2] = 0;
bus_sync_flag[2] = 0;
wr_cnt[2] = 0;
wr_flag[2] = 0;
rd_flag[2] = 0;
end
if (desync_flag[3] == 1 ) begin
new_data_in_flag[3] = 0;
bus_sync_flag[3] = 0;
wr_cnt[3] = 0;
wr_flag[3] = 0;
rd_flag[3] = 0;
end
if (icap_init_done == 1 && csi_b_in == 1 && rdwr_b_in == 0) begin
new_data_in_flag = 4'b0;
wr_cnt[0] = 0;
wr_cnt[1] = 0;
wr_cnt[2] = 0;
wr_cnt[3] = 0;
pack_in_reg_tmp0 = 32'b0;
pack_in_reg_tmps0 = 32'b0;
end
else begin
if (icap_clr == 1) begin
new_data_in_flag <= 4'b0;
wr_cnt[0] <= 0;
wr_cnt[1] <= 0;
wr_cnt[2] <= 0;
wr_cnt[3] <= 0;
wr_flag <= 4'b0;
rd_flag <= 4'b0;
pack_in_reg_tmp0 = 32'b0;
pack_in_reg_tmps0 = 32'b0;
end
else if (rw_en[ib] == 1 && desync_flag[ib] == 0) begin
if (rdwr_b_in == 0) begin
wr_flag[ib] <= 1;
rd_flag[ib] <= 0;
if (buswidth[ib] == 2'b01 || (icap_sync == 1 && bus_sync_flag[ib] == 0)) begin
tmp_byte = bit_revers8(d_in[7:0]);
if (bus_sync_flag[ib] == 0) begin
pack_in_reg_tmp0 = pack_in_reg[ib];
if (pack_in_reg_tmp0[23:16] == 8'hAA && pack_in_reg_tmp0[15:8] == 8'h99
&& pack_in_reg_tmp0[7:0] == 8'h55 && tmp_byte == 8'h66) begin
bus_sync_flag[ib] <= 1;
new_data_in_flag[ib] <= 0;
wr_cnt[ib] <= 0;
end
else begin
pack_in_reg_tmp0[31:24] = pack_in_reg_tmp0[23:16];
pack_in_reg_tmp0[23:16] = pack_in_reg_tmp0[15:8];
pack_in_reg_tmp0[15:8] = pack_in_reg_tmp0[7:0];
pack_in_reg_tmp0[7:0] = tmp_byte;
pack_in_reg_tmps0 <= pack_in_reg_tmp0;
end
end
else begin
if (wr_cnt[ib] == 0) begin
pack_in_reg_tmp0 = pack_in_reg[ib];
pack_in_reg_tmp0[31:24] = tmp_byte;
pack_in_reg_tmps0 <= pack_in_reg_tmp0;
new_data_in_flag[ib] <= 0;
wr_cnt[ib] <= 1;
end
else if (wr_cnt[ib] == 1) begin
pack_in_reg_tmp0 = pack_in_reg[ib];
pack_in_reg_tmp0[23:16] = tmp_byte;
pack_in_reg_tmps0 <= pack_in_reg_tmp0;
new_data_in_flag[ib] <= 0;
wr_cnt[ib] <= 2;
end
else if (wr_cnt[ib] == 2) begin
pack_in_reg_tmp0 = pack_in_reg[ib];
pack_in_reg_tmp0[15:8] = tmp_byte;
pack_in_reg_tmps0 <= pack_in_reg_tmp0;
new_data_in_flag[ib] <= 0;
wr_cnt[ib] <= 3;
end
else if (wr_cnt[ib] == 3) begin
pack_in_reg_tmp0 = pack_in_reg[ib];
pack_in_reg_tmp0[7:0] = tmp_byte;
pack_in_reg_tmps0 <= pack_in_reg_tmp0;
new_data_in_flag[ib] <= 1;
wr_cnt[ib] <= 0;
end
end
end
else if (buswidth[ib] == 2'b10) begin
tmp_word = {bit_revers8(d_in[15:8]), bit_revers8(d_in[7:0])};
if (bus_sync_flag[ib] == 0) begin
pack_in_reg_tmp0 = pack_in_reg[ib];
if (pack_in_reg_tmp0[15:0] == 16'hAA99 && tmp_word ==16'h5566) begin
wr_cnt[ib] <= 0;
bus_sync_flag[ib] <= 1;
new_data_in_flag[ib] <= 0;
end
else begin
pack_in_reg_tmp0[31:16] = pack_in_reg_tmp0[15:0];
pack_in_reg_tmp0[15:0] = tmp_word;
pack_in_reg_tmps0 <= pack_in_reg_tmp0;
new_data_in_flag[ib] <= 0;
wr_cnt[ib] <= 0;
end
end
else begin
pack_in_reg_tmp0 = pack_in_reg[ib];
if (wr_cnt[ib] == 0) begin
pack_in_reg_tmp0[31:16] = tmp_word;
pack_in_reg_tmps0 <= pack_in_reg_tmp0;
new_data_in_flag[ib] <= 0;
wr_cnt[ib] <= 1;
end
else if (wr_cnt[ib] == 1) begin
pack_in_reg_tmp0[15:0] = tmp_word;
pack_in_reg_tmps0 <= pack_in_reg_tmp0;
new_data_in_flag[ib] <= 1;
wr_cnt[ib] <= 0;
end
end
end
else if (buswidth[ib] == 2'b11 ) begin
tmp_dword = {bit_revers8(d_in[31:24]), bit_revers8(d_in[23:16]), bit_revers8(d_in[15:8]),
bit_revers8(d_in[7:0])};
pack_in_reg_tmp0 <= tmp_dword;
pack_in_reg_tmps0 <= tmp_dword;
if (bus_sync_flag[ib] == 0) begin
if (tmp_dword == 32'hAA995566) begin
bus_sync_flag[ib] <= 1;
new_data_in_flag[ib] <= 0;
end
end
else begin
pack_in_reg_tmp0 <= tmp_dword;
pack_in_reg_tmps0 <= tmp_dword;
new_data_in_flag[ib] <= 1;
end
end
end
else begin
wr_flag[ib] <= 0;
new_data_in_flag[ib] <= 0;
if (rd_sw_en ==1)
rd_flag[ib] <= 1;
end
end
else begin
wr_flag[ib] <= 0;
rd_flag[ib] <= 0;
new_data_in_flag[ib] <= 0;
end
end
end
always @(pack_in_reg_tmps0 or desync_flag or icap_clr)
begin
if (desync_flag[0] == 1 || icap_clr == 1)
pack_in_reg[0] = 32'b0;
if (desync_flag[1] == 1 || icap_clr == 1)
pack_in_reg[1] = 32'b0;
if (desync_flag[2] == 1 || icap_clr == 1)
pack_in_reg[2] = 32'b0;
if (desync_flag[3] == 1 || icap_clr == 1)
pack_in_reg[3] = 32'b0;
if (ib == 0 && desync_flag[0] == 0 && icap_clr == 0) begin
pack_in_reg[0] = pack_in_reg_tmps0;
end
else if (ib == 1 && desync_flag[1] == 0 && icap_clr == 0)
pack_in_reg[1] = pack_in_reg_tmps0;
else if (ib == 2 && desync_flag[2] == 0 && icap_clr == 0)
pack_in_reg[2] = pack_in_reg_tmps0;
else if (ib == 3 && desync_flag[3] == 0 && icap_clr == 0)
pack_in_reg[3] = pack_in_reg_tmps0;
end
task rst_pack_dec;
input ib_d;
begin
conti_data_flag[ib_d] <= 0;
conti_data_cnt[ib_d] <= 0;
cmd_wr_flag[ib_d] <= 0;
cmd_rd_flag[ib_d] <= 0;
id_error_flag[ib_d] <= 0;
crc_curr[ib_d] <= 32'b0;
crc_ck[ib_d] <= 0;
csbo_cnt[ib_d] <= 0;
csbo_flag[ib_d] <= 0;
downcont_cnt <= 0;
rd_data_cnt[ib_d] <= 0;
end
endtask
always @(negedge cclk_in or negedge rst_intl)
if (rst_intl == 0) begin
rst_pack_dec(0);
rst_pack_dec(1);
rst_pack_dec(2);
rst_pack_dec(3);
bout_flag <= 4'b0;
bout_cnt[0] <= 0;
bout_cnt[1] <= 0;
bout_cnt[2] <= 0;
bout_cnt[3] <= 0;
end
else begin
if (icap_clr == 1) begin
rst_pack_dec(0);
rst_pack_dec(1);
rst_pack_dec(2);
rst_pack_dec(3);
bout_flag <= 4'b0;
bout_cnt[0] <= 0;
bout_cnt[1] <= 0;
bout_cnt[2] <= 0;
bout_cnt[3] <= 0;
end
if (crc_reset[ib] == 1 ) begin
crc_reg[ib] <= 32'b0;
crc_ck[ib] <= 0;
crc_curr[ib] <= 32'b0;
end
if (crc_ck[ib] == 1) begin
crc_curr[ib] <= 32'b0;
crc_ck[ib] <= 0;
end
if (desynch_set1[0] == 1 || crc_err_flag[0] == 1) begin
bout_flag[0] <= 0;
bout_cnt[0] <= 0;
rst_pack_dec(0);
end
if (desynch_set1[1] == 1 || crc_err_flag[1] == 1) begin
bout_flag[1] <= 0;
bout_cnt[1] <= 0;
rst_pack_dec(1);
end
if (desynch_set1[2] == 1 || crc_err_flag[2] == 1) begin
bout_flag[2] <= 0;
bout_cnt[2] <= 0;
rst_pack_dec(2);
end
if (desynch_set1[3] == 1 || crc_err_flag[3] == 1) begin
bout_flag[3] <= 0;
bout_cnt[3] <= 0;
rst_pack_dec(3);
end
if (new_data_in_flag[ib] == 1 && wr_flag[ib] == 1 && csi_b_ins == 0
&& desynch_set1[ib] == 0 && crc_err_flag[ib] == 0 && icap_clr == 0) begin
pack_in_reg_tmp = pack_in_reg[ib];
if (conti_data_flag[ib] == 1 ) begin
reg_addr_tmp = reg_addr[ib];
case (reg_addr_tmp)
5'b00000 : begin
crc_reg[ib] <= pack_in_reg[ib];
crc_reg_tmp <= pack_in_reg[ib];
crc_ck[ib] <= 1;
end
5'b00001 : far_reg[ib] <= {6'b0, pack_in_reg_tmp[25:0]};
// 5'b00010 : fdri_reg[ib] <= pack_in_reg[ib];
5'b00010 : begin
fdri_reg[ib] <= pack_in_reg[ib];
fdri_rst_prdone_flag <= ~fdri_rst_prdone_flag;
end
5'b00100 : cmd_reg[ib] <= pack_in_reg_tmp[4:0];
5'b00101 : ctl0_reg[ib] <= (pack_in_reg[ib] & mask_reg[ib]) | (ctl0_reg[ib] & ~mask_reg[ib]);
5'b00110 : mask_reg[ib] <= pack_in_reg[ib];
5'b01000 : lout_reg[ib] <= pack_in_reg[ib];
5'b01001 : cor0_reg[ib] <= pack_in_reg[ib];
5'b01010 : mfwr_reg[ib] <= pack_in_reg[ib];
5'b01011 : cbc_reg[ib] <= pack_in_reg[ib];
5'b01100 : begin
idcode_reg[ib] <= pack_in_reg[ib];
if (pack_in_reg_tmp[27:0] != DEVICE_ID[27:0]) begin
id_error_flag[ib] <= 1;
if (icap_on == 0)
$display("Error: [Unisim %s-8] Written value to IDCODE register is %h which does not match with DEVICE ID %h on %s at time %t. Instance %m", MODULE_NAME, pack_in_reg[ib], DEVICE_ID, MODULE_NAME, $time);
else
$display("Error: [Unisim %s-9] Written value to IDCODE register is %h which does not match with DEVICE ID %h on ICAPE3 at time %t. Instance %m", MODULE_NAME, pack_in_reg[ib], DEVICE_ID, $time);
end
else
id_error_flag[ib] <= 0;
end
5'b01101 : axss_reg[ib] <= pack_in_reg[ib];
5'b01110 : cor1_reg[ib] <= pack_in_reg[ib];
5'b01111 : csob_reg[ib] <= pack_in_reg[ib];
5'b10000 : wbstar_reg[ib] <= pack_in_reg[ib];
5'b10001 : timer_reg[ib] <= pack_in_reg[ib];
5'b10011 : rbcrc_sw_reg[ib] <= pack_in_reg[ib];
5'b10111 : testmode_reg[ib] <= pack_in_reg[ib];
5'b11000 : ctl1_reg[ib] <= (pack_in_reg[ib] & mask_reg[ib]) | (ctl1_reg[ib] & ~mask_reg[ib]);
5'b11001 : memrd_param_reg[ib] <= {4'b0, pack_in_reg_tmp[27:0]};
5'b11010 : dwc_reg[ib] <= {4'b0, pack_in_reg_tmp[27:0]};
5'b11011 : trim_reg[ib] <= pack_in_reg[ib];
5'b11110 : bout_reg[ib] <= pack_in_reg[ib];
5'b11111 : bspi_reg[ib] <= pack_in_reg[ib];
endcase
if (reg_addr[ib] != 5'b00000)
crc_ck[ib] <= 0;
if (reg_addr_tmp == 5'b00100)
cmd_reg_new_flag[ib] <= 1;
else
cmd_reg_new_flag[ib] <= 0;
if (crc_en[ib] == 1) begin
if (reg_addr[ib] == 5'h04 && pack_in_reg_tmp[4:0] == 5'b00111)
crc_curr[ib] = 32'b0;
else begin
if ( reg_addr[ib] != 5'h0f && reg_addr[ib] != 5'h12 && reg_addr[ib] != 5'h14
&& reg_addr[ib] != 5'h15 && reg_addr[ib] != 5'h16 && reg_addr[ib] != 5'h00) begin
crc_input = {reg_addr[ib], pack_in_reg_tmp};
crc_curr_tmp = crc_curr[ib];
crc_new = bcc_next(crc_curr_tmp, crc_input);
crc_curr[ib] <= crc_new;
end
end
end
if (conti_data_cnt[ib] <= 1) begin
conti_data_cnt[ib] <= 0;
end
else
conti_data_cnt[ib] <= conti_data_cnt[ib] - 1;
end
else if (conti_data_flag[ib] == 0 ) begin
if ( downcont_cnt >= 1) begin
if (crc_en[ib] == 1) begin
crc_input[36:0] = {5'b00010, pack_in_reg[ib]};
crc_new = bcc_next(crc_curr[ib], crc_input);
crc_curr[ib] <= crc_new;
end
if (ib == 0) begin
if (farn <= 80)
farn <= farn + 1;
else begin
far_addr <= far_addr + 1;
farn <= 0;
end
if (frame_data_wen == 1 && icap_init_done == 0) begin
rbcrc_input[36:0] = {5'b00011, pack_in_reg[ib]};
rbcrc_new[31:0] = bcc_next(rbcrc_curr[ib], rbcrc_input);
rbcrc_curr[ib] <= rbcrc_new;
$fwriteh(frame_data_fd, far_addr);
$fwriteh(frame_data_fd, "\t");
$fwriteh(frame_data_fd, pack_in_reg[ib]);
$fwriteh(frame_data_fd, "\t");
$fwriteh(frame_data_fd, rbcrc_new);
$fwriteh(frame_data_fd, "\n");
end
end
end
if (pack_in_reg_tmp[31:29] == 3'b010 ) begin
bout_cnt_tmp = bout_cnt[ib];
if (reg_addr[ib] == 5'b00010 && downcont_cnt == 0 ) begin
cmd_rd_flag[ib] <= 0;
cmd_wr_flag[ib] <= 0;
conti_data_flag[ib] <= 0;
conti_data_cnt[ib] <= 0;
downcont_cnt <= pack_in_reg_tmp[26:0];
far_addr <= far_reg[ib];
end
else if (reg_addr_tmp == 5'b11110 && bout_cnt_tmp == 0) begin
cmd_rd_flag[ib] <= 0;
cmd_wr_flag[ib] <= 0;
conti_data_flag[ib] <= 0;
conti_data_cnt[ib] <= 0;
bout_flag[ib] <= 1;
bout_cnt[ib] <= pack_in_reg_tmp[26:0];
end
else if (reg_addr[ib] == 5'b01000 && csbo_cnt[ib] == 0) begin
cmd_rd_flag[ib] <= 0;
cmd_wr_flag[ib] <= 0;
conti_data_flag[ib] <= 0;
conti_data_cnt[ib] <= 0;
csbo_flag[ib] <= 1;
csbo_cnt[ib] <= pack_in_reg_tmp[26:0];
end
end
else if (pack_in_reg_tmp[31:29] == 3'b001) begin // type 1 package
if (pack_in_reg_tmp[28:27] == 2'b01 && downcont_cnt == 0) begin
if (pack_in_reg_tmp[10:0] != 11'b0) begin
cmd_rd_flag[ib] <= 1;
cmd_wr_flag[ib] <= 0;
rd_data_cnt[ib] <= 4;
conti_data_cnt[ib] <= 0;
conti_data_flag[ib] <= 0;
rd_reg_addr[ib] <= pack_in_reg_tmp[17:13];
end
end
else if (pack_in_reg_tmp[28:27] == 2'b10 && downcont_cnt == 0) begin
if (pack_in_reg_tmp[17:13] == 5'b01000) begin // lout reg
lout_reg[ib] <= pack_in_reg_tmp;
conti_data_flag[ib] = 0;
reg_addr[ib] <= pack_in_reg_tmp[17:13];
reg_addr_tmp <= pack_in_reg_tmp[17:13];
cmd_wr_flag[ib] <= 1;
conti_data_cnt[ib] <= 5'b0;
end
else if (pack_in_reg_tmp[17:13] == 5'b11110) begin // bout reg
bout_reg[ib] <= pack_in_reg_tmp;
bout_flags[ib] <= 1;
conti_data_flag[ib] = 0;
reg_addr[ib] <= pack_in_reg_tmp[17:13];
reg_addr_tmp <= pack_in_reg_tmp[17:13];
cmd_wr_flag[ib] <= 1;
conti_data_cnt[ib]<= 5'b0;
end
else begin
if (pack_in_reg_tmp[10:0] != 10'b0) begin
cmd_rd_flag[ib] <= 0;
cmd_wr_flag[ib] <= 1;
conti_data_flag[ib] <= 1;
conti_data_cnt[ib] <= pack_in_reg_tmp[10:0];
reg_addr[ib] <= pack_in_reg_tmp[17:13];
reg_addr_tmp <= pack_in_reg_tmp[17:13];
end
else begin
cmd_rd_flag[ib] <= 0;
cmd_wr_flag[ib] <= 1;
conti_data_flag[ib] <= 0;
conti_data_cnt[ib] <= 0;
reg_addr[ib] <= pack_in_reg_tmp[17:13];
reg_addr_tmp <= pack_in_reg_tmp[17:13];
end
end
end
else begin
cmd_wr_flag[ib] <= 0;
conti_data_flag[ib] <= 0;
conti_data_cnt[ib] <= 0;
end
end
end // if (conti_data_flag == 0 )
if (csbo_cnt[ib] != 0 ) begin
if (csbo_flag[ib] == 1)
csbo_cnt[ib] <= csbo_cnt[ib] - 1;
end
else
csbo_flag[ib] <= 0;
if (bout_cnt[0] != 0 && bout_flag[0] == 1) begin
if (bout_cnt[0] == 1) begin
bout_cnt[0] <= 0;
bout_flag[0] <= 0;
end
else
bout_cnt[0] <= bout_cnt[0] - 1;
end
if (bout_cnt[1] != 0 && bout_flag[1] == 1) begin
if (bout_cnt[1] == 1) begin
bout_cnt[1] <= 0;
bout_flag[1] <= 0;
end
else
bout_cnt[1] <= bout_cnt[1] - 1;
end
if (bout_cnt[2] != 0 && bout_flag[2] == 1) begin
bout_cnt[2] <= bout_cnt[2] - 1;
if (bout_cnt[2] == 1) begin
bout_cnt[2] <= 0;
bout_flag[2] <= 0;
end
else
bout_cnt[2] <= bout_cnt[2] - 1;
end
if (bout_cnt[3] != 0 && bout_flag[3] == 1 ) begin
if (bout_cnt[3] == 1) begin
bout_cnt[3] <= 0;
bout_flag[3] <= 0;
end
else
bout_cnt[3] <= bout_cnt[3] - 1;
end
if (conti_data_cnt[ib] == 5'b00001 )
conti_data_flag[ib] <= 0;
if (crc_ck[ib] == 1 || icap_init_done == 1)
crc_ck[ib] <= 0;
end
if (rw_en[ib] == 1 && csi_b_ins == 0) begin
if (rd_data_cnt[ib] == 1 && rd_flag[ib] == 1)
rd_data_cnt[ib] <= 0;
else if (rd_data_cnt[ib] == 0 && rd_flag[ib] == 1) begin
cmd_rd_flag[ib] <= 0;
end
else if (cmd_rd_flag[ib] ==1 && rd_flag[ib] == 1)
rd_data_cnt[ib] <= rd_data_cnt[ib] - 1;
if (downcont_cnt >= 1 && conti_data_flag[ib] == 0 && new_data_in_flag[ib] == 1 && wr_flag[ib] == 1)
downcont_cnt <= downcont_cnt - 1;
end
if (cmd_reg_new_flag[ib] == 1 )
cmd_reg_new_flag[ib] <= 0;
end
always @(bout_flag)
if (bout_flag[3] == 1) begin
ib = 3;
ib_skp = 1;
end
else if (bout_flag[2] == 1) begin
ib = 3;
ib_skp = 0;
end
else if (bout_flag[1] == 1) begin
ib = 2;
ib_skp = 0;
end
else if (bout_flag[0] == 1) begin
ib = 1;
ib_skp = 0;
end
else begin
ib = 0;
ib_skp = 0;
end
always @(posedge cclk_in or negedge rst_intl)
if (rst_intl == 0) begin
outbus <= 32'b0;
end
else begin
if (cmd_rd_flag[ib] == 1 && rdwr_b_in == 1 && csi_b_in == 0) begin
case (rd_reg_addr[ib])
5'b00000 : if (buswidth[ib] == 2'b01)
rdbk_byte(crc_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(crc_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(crc_reg[ib], rd_data_cnt[ib]);
5'b00001 : if (buswidth[ib] == 2'b01)
rdbk_byte(far_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(far_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(far_reg[ib], rd_data_cnt[ib]);
5'b00011 : if (buswidth[ib] == 2'b01)
rdbk_byte(fdro_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(fdro_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(fdro_reg[ib], rd_data_cnt[ib]);
5'b00100 : if (buswidth[ib] == 2'b01)
rdbk_byte(cmd_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(cmd_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(cmd_reg[ib], rd_data_cnt[ib]);
5'b00101 : if (buswidth[ib] == 2'b01)
rdbk_byte(ctl0_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(ctl0_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(ctl0_reg[ib], rd_data_cnt[ib]);
5'b00110 : if (buswidth[ib] == 2'b01)
rdbk_byte(mask_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(mask_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(mask_reg[ib], rd_data_cnt[ib]);
5'b00111 : if (buswidth[ib] == 2'b01)
rdbk_byte(stat_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(stat_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(stat_reg[ib], rd_data_cnt[ib]);
5'b01001 : if (buswidth[ib] == 2'b01)
rdbk_byte(cor0_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(cor0_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(cor0_reg[ib], rd_data_cnt[ib]);
5'b01100 : if (buswidth[ib] == 2'b01)
rdbk_byte(DEVICE_ID, rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(DEVICE_ID, rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(DEVICE_ID, rd_data_cnt[ib]);
5'b01101 : if (buswidth[ib] == 2'b01)
rdbk_byte(axss_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(axss_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(axss_reg[ib], rd_data_cnt[ib]);
5'b01110 : if (buswidth[ib] == 2'b01)
rdbk_byte(cor1_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(cor1_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(cor1_reg[ib], rd_data_cnt[ib]);
5'b10000 : if (buswidth[ib] == 2'b01)
rdbk_byte(wbstar_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(wbstar_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(wbstar_reg[ib], rd_data_cnt[ib]);
5'b10001 : if (buswidth[ib] == 2'b01)
rdbk_byte(timer_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(timer_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(timer_reg[ib], rd_data_cnt[ib]);
5'b10010 : if (buswidth[ib] == 2'b01)
rdbk_byte(rbcrc_hw_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(rbcrc_hw_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(rbcrc_hw_reg[ib], rd_data_cnt[ib]);
5'b10011 : if (buswidth[ib] == 2'b01)
rdbk_byte(rbcrc_sw_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(rbcrc_sw_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(rbcrc_sw_reg[ib], rd_data_cnt[ib]);
5'b10100 : if (buswidth[ib] == 2'b01)
rdbk_byte(rbcrc_live_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(rbcrc_live_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(rbcrc_live_reg[ib], rd_data_cnt[ib]);
5'b10101 : if (buswidth[ib] == 2'b01)
rdbk_byte(efar_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(efar_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(efar_reg[ib], rd_data_cnt[ib]);
5'b10110 : if (buswidth[ib] == 2'b01)
rdbk_byte(bootsts_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(bootsts_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(bootsts_reg[ib], rd_data_cnt[ib]);
5'b11000 : if (buswidth[ib] == 2'b01)
rdbk_byte(ctl1_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(ctl1_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(ctl1_reg[ib], rd_data_cnt[ib]);
5'b11001 : if (buswidth[ib] == 2'b01)
rdbk_byte(memrd_param_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(memrd_param_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(memrd_param_reg[ib], rd_data_cnt[ib]);
5'b11010 : if (buswidth[ib] == 2'b01)
rdbk_byte( dwc_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd( dwc_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(dwc_reg[ib], rd_data_cnt[ib]);
5'b11011 : if (buswidth[ib] == 2'b01)
rdbk_byte(trim_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(trim_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(trim_reg[ib], rd_data_cnt[ib]);
5'b11111 : if (buswidth[ib] == 2'b01)
rdbk_byte(bspi_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(bspi_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(bspi_reg[ib], rd_data_cnt[ib]);
endcase
if (ib != 0) begin
if (rd_data_cnt[ib] == 1)
rd_desynch_tmp <= 1;
end
end
else begin
outbus <= 32'b0;
rd_desynch <= rd_desynch_tmp;
rd_desynch_tmp <= 0;
end
end
assign crc_rst[0] = crc_reset[0] | ~rst_intl;
assign crc_rst[1] = crc_reset[1] | ~rst_intl;
assign crc_rst[2] = crc_reset[2] | ~rst_intl;
assign crc_rst[3] = crc_reset[3] | ~rst_intl;
assign crc_curr_cktmp = crc_curr[0];
assign crc_reg_cktmp = crc_reg[0];
always @(posedge cclk_in or posedge crc_rst[0] )
if (crc_rst[0] == 1) begin
crc_err_flag[0] <= 0;
crc_ck_en[0] <= 1;
end
else
if (crc_ck[0] == 1 && crc_ck_en[0] == 1 ) begin
if (crc_curr[0] != crc_reg[0])
crc_err_flag[0] <= 1;
else
crc_err_flag[0] <= 0;
crc_ck_en[0] <= 0;
end
else begin
crc_err_flag[0] <= 0;
crc_ck_en[0] <= 1;
end
always @(posedge cclk_in or posedge crc_rst[1] )
if (crc_rst[1] == 1) begin
crc_err_flag[1] <= 0;
crc_ck_en[1] <= 1;
end
else
if (crc_ck[1] == 1 && crc_ck_en[1] == 1 ) begin
if (crc_curr[1] != crc_reg[1])
crc_err_flag[1] <= 1;
else
crc_err_flag[1] <= 0;
crc_ck_en[1] <= 0;
end
else begin
crc_err_flag[1] <= 0;
crc_ck_en[1] <= 1;
end
always @(posedge cclk_in or posedge crc_rst[2] )
if (crc_rst[2] == 1) begin
crc_err_flag[2] <= 0;
crc_ck_en[2] <= 1;
end
else
if (crc_ck[2] == 1 && crc_ck_en[2] == 1) begin
if (crc_curr[2] != crc_reg[2])
crc_err_flag[2] <= 1;
else
crc_err_flag[2] <= 0;
crc_ck_en[2] <= 0;
end
else begin
crc_err_flag[2] <= 0;
crc_ck_en[2] <= 1;
end
always @(posedge cclk_in or posedge crc_rst[3] )
if (crc_rst[3] == 1) begin
crc_err_flag[3] <= 0;
crc_ck_en[3] <= 1;
end
else
if (crc_ck[3] == 1 && crc_ck_en[3] == 1) begin
if (crc_curr[3] != crc_reg[3])
crc_err_flag[3] <= 1;
else
crc_err_flag[3] <= 0;
crc_ck_en[3] <= 0;
end
else begin
crc_err_flag[3] <= 0;
crc_ck_en[3] <= 1;
end
always @(posedge crc_err_flag[0] or negedge rst_intl or posedge bus_sync_flag[0])
if (rst_intl == 0)
crc_err_flag_reg[0] <= 0;
else if (crc_err_flag[0] == 1)
crc_err_flag_reg[0] <= 1;
else
crc_err_flag_reg[0] <= 0;
always @(posedge crc_err_flag[1] or negedge rst_intl or posedge bus_sync_flag[1])
if (rst_intl == 0)
crc_err_flag_reg[1] <= 0;
else if (crc_err_flag[1] == 1)
crc_err_flag_reg[1] <= 1;
else
crc_err_flag_reg[1] <= 0;
always @(posedge crc_err_flag[2] or negedge rst_intl or posedge bus_sync_flag[2])
if (rst_intl == 0)
crc_err_flag_reg[2] <= 0;
else if (crc_err_flag[2] == 1)
crc_err_flag_reg[2] <= 1;
else
crc_err_flag_reg[2] <= 0;
always @(posedge crc_err_flag[3] or negedge rst_intl or posedge bus_sync_flag[3])
if (rst_intl == 0)
crc_err_flag_reg[3] <= 0;
else if (crc_err_flag[3] == 1)
crc_err_flag_reg[3] <= 1;
else
crc_err_flag_reg[3] <= 0;
always @(posedge cclk_in or negedge rst_intl)
if (rst_intl == 0) begin
startup_set <= 4'b0;
crc_reset <= 4'b0;
gsr_cmd_out <= 4'b0;
shutdown_set <= 4'b0;
desynch_set <= 4'b0;
ghigh_b <= 4'b0;
end
else
for (ci = 0; ci <=3; ci = ci+1) begin
if (cmd_reg_new_flag[ci] == 1) begin
if (cmd_reg[ci] == 5'b00011)
ghigh_b[ci] <= 1;
else if (cmd_reg[ci] == 5'b01000)
ghigh_b[ci] <= 0;
if (cmd_reg[ci] == 5'b00101)
startup_set[ci] <= 1;
else
startup_set[ci] <= 0;
if (cmd_reg[ci] == 5'b00111)
crc_reset[ci] <= 1;
else
crc_reset[ci] <= 0;
if (cmd_reg[ci] == 5'b01010)
gsr_cmd_out[ci] <= 1;
else
gsr_cmd_out[ci] <= 0;
if (cmd_reg[ci] == 5'b01011)
shutdown_set[ci] <= 1;
else
shutdown_set[ci] <= 0;
if (cmd_reg[ci] == 5'b01101)
desynch_set[ci] <= 1;
else
desynch_set[ci] <= 0;
if (cmd_reg[ci] == 5'b01111) begin
iprog_b[ci] <= 0;
i_init_b_cmd[ci] <= 0;
iprog_b[ci] <= #cfg_Tprog 1;
i_init_b_cmd[ci] <=#(cfg_Tprog + cfg_Tpl) 1;
end
end
else begin
startup_set[ci] <= 0;
crc_reset[ci] <= 0;
gsr_cmd_out[ci] <= 0;
shutdown_set[ci] <= 0;
desynch_set[ci] <= 0;
end
end
always @(posedge startup_set[0] or posedge desynch_set[0] or posedge rw_en[0] )
if (rw_en[0] == 1 || desynch_set[0] == 1)
begin
if (startup_set_pulse0 == 2'b00 && startup_set[0] ==1) begin
if (icap_on == 0)
startup_set_pulse0 <= 2'b01;
else begin
startup_set_pulse0 <= 2'b11;
@(posedge cclk_in )
startup_set_pulse0 <= 2'b00;
end
end
else if (desynch_set[0] == 1 && startup_set_pulse0 == 2'b01) begin
startup_set_pulse0 <= 2'b11;
@(posedge cclk_in )
startup_set_pulse0 <= 2'b00;
end
end
always @(posedge startup_set[1] or posedge desynch_set[1] or posedge rw_en[1] )
if (rw_en[1] == 1 || desynch_set[1] == 1)
begin
if (startup_set_pulse1 == 2'b00 && startup_set[1] ==1) begin
if (icap_on == 0)
startup_set_pulse1 <= 2'b01;
else begin
startup_set_pulse1 <= 2'b11;
@(posedge cclk_in )
startup_set_pulse1 <= 2'b00;
end
end
else if (desynch_set[1] == 1 && startup_set_pulse1 == 2'b01) begin
startup_set_pulse1 <= 2'b11;
@(posedge cclk_in )
startup_set_pulse1 <= 2'b00;
end
end
always @(posedge startup_set[2] or posedge desynch_set[2] or posedge rw_en[2])
if (rw_en[2] == 1 || desynch_set[2] == 1)
begin
if (startup_set_pulse2 == 2'b00 && startup_set[2] ==1) begin
if (icap_on == 0)
startup_set_pulse2 <= 2'b01;
else begin
startup_set_pulse2 <= 2'b11;
@(posedge cclk_in )
startup_set_pulse2 <= 2'b00;
end
end
else if (desynch_set[2] == 1 && startup_set_pulse2 == 2'b01) begin
startup_set_pulse2 <= 2'b11;
@(posedge cclk_in )
startup_set_pulse2 <= 2'b00;
end
end
always @(posedge startup_set[3] or posedge desynch_set[3] or posedge rw_en[3])
if (rw_en[3] == 1 || desynch_set[3] == 1)
begin
if (startup_set_pulse3 == 2'b00 && startup_set[3] ==1) begin
if (icap_on == 0)
startup_set_pulse3 <= 2'b01;
else begin
startup_set_pulse3 <= 2'b11;
@(posedge cclk_in )
startup_set_pulse3 <= 2'b00;
end
end
else if (desynch_set[3] == 1 && startup_set_pulse3 == 2'b01) begin
startup_set_pulse3 <= 2'b11;
@(posedge cclk_in )
startup_set_pulse3 <= 2'b00;
end
end
always @(posedge gsr_cmd_out[0] or negedge rw_en[0])
if (rw_en[0] == 0)
gsr_cmd_out_pulse[0] <= 0;
else
begin
gsr_cmd_out_pulse[0] <= 1;
@(posedge cclk_in );
@(posedge cclk_in )
gsr_cmd_out_pulse[0] <= 0;
end
always @(posedge gsr_cmd_out[1] or negedge rw_en[1])
if (rw_en[1] == 0)
gsr_cmd_out_pulse[1] <= 0;
else
begin
gsr_cmd_out_pulse[1] <= 1;
@(posedge cclk_in );
@(posedge cclk_in )
gsr_cmd_out_pulse[1] <= 0;
end
always @(posedge gsr_cmd_out[2] or negedge rw_en[2])
if (rw_en[2] == 0)
gsr_cmd_out_pulse[2] <= 0;
else
begin
gsr_cmd_out_pulse[2] <= 1;
@(posedge cclk_in );
@(posedge cclk_in )
gsr_cmd_out_pulse[2] <= 0;
end
always @(posedge gsr_cmd_out[3] or negedge rw_en[3])
if (rw_en[3] == 0)
gsr_cmd_out_pulse[3] <= 0;
else
begin
gsr_cmd_out_pulse[3] <= 1;
@(posedge cclk_in );
@(posedge cclk_in )
gsr_cmd_out_pulse[3] <= 0;
end
reg [31:0] ctl0_reg_tmp0, ctl0_reg_tmp1, ctl0_reg_tmp2, ctl0_reg_tmp3;
always @(ctl0_reg[0]) begin
ctl0_reg_tmp0 = ctl0_reg[0];
if (ctl0_reg_tmp0[9] == 1)
abort_dis[0] = 1;
else
abort_dis[0] = 0;
if (ctl0_reg_tmp0[3] == 1)
persist_en[0] = 1;
else
persist_en[0] = 0;
if (ctl0_reg_tmp0[0] == 1)
gts_usr_b[0] = 1;
else
gts_usr_b[0] = 0;
end
always @(ctl0_reg[1]) begin
ctl0_reg_tmp1 = ctl0_reg[1];
if (ctl0_reg_tmp1[9] == 1)
abort_dis[1] = 1;
else
abort_dis[1] = 0;
if (ctl0_reg_tmp1[3] == 1)
persist_en[1] = 1;
else
persist_en[1] = 0;
if (ctl0_reg_tmp1[0] == 1)
gts_usr_b[1] = 1;
else
gts_usr_b[1] = 0;
end
always @(ctl0_reg[2]) begin
ctl0_reg_tmp2 = ctl0_reg[2];
if (ctl0_reg_tmp2[9] == 1)
abort_dis[2] = 1;
else
abort_dis[2] = 0;
if (ctl0_reg_tmp2[3] == 1)
persist_en[2] = 1;
else
persist_en[2] = 0;
if (ctl0_reg_tmp0[2] == 1)
gts_usr_b[2] = 1;
else
gts_usr_b[2] = 0;
end
always @(ctl0_reg[3]) begin
ctl0_reg_tmp3 = ctl0_reg[3];
if (ctl0_reg_tmp3[9] == 1)
abort_dis[3] = 1;
else
abort_dis[3] = 0;
if (ctl0_reg_tmp3[3] == 1)
persist_en[3] = 1;
else
persist_en[3] = 0;
if (ctl0_reg_tmp3[0] == 1)
gts_usr_b[3] = 1;
else
gts_usr_b[3] = 0;
end
always @(cor0_reg[0])
begin
cor0_reg_tmp0 = cor0_reg[0];
done_cycle_reg0 = cor0_reg_tmp0[14:12];
lock_cycle_reg0 = cor0_reg_tmp0[8:6];
gts_cycle_reg0 = cor0_reg_tmp0[5:3];
gwe_cycle_reg0 = cor0_reg_tmp0[2:0];
if (cor0_reg_tmp0[24] == 1'b1)
done_pin_drv[0] = 1;
else
done_pin_drv[0] = 0;
if (cor0_reg_tmp0[28] == 1'b1)
crc_bypass[0] = 1;
else
crc_bypass[0] = 0;
end
always @(cor0_reg[1])
begin
cor0_reg_tmp1 = cor0_reg[1];
done_cycle_reg1 = cor0_reg_tmp1[14:12];
lock_cycle_reg1 = cor0_reg_tmp1[8:6];
gts_cycle_reg1 = cor0_reg_tmp1[5:3];
gwe_cycle_reg1 = cor0_reg_tmp1[2:0];
if (cor0_reg_tmp1[24] == 1'b1)
done_pin_drv[1] = 1;
else
done_pin_drv[1] = 0;
if (cor0_reg_tmp1[28] == 1'b1)
crc_bypass[1] = 1;
else
crc_bypass[1] = 0;
end
always @(cor0_reg[2])
begin
cor0_reg_tmp2 = cor0_reg[2];
done_cycle_reg2 = cor0_reg_tmp2[14:12];
lock_cycle_reg2 = cor0_reg_tmp2[8:6];
gts_cycle_reg2 = cor0_reg_tmp2[5:3];
gwe_cycle_reg2 = cor0_reg_tmp2[2:0];
if (cor0_reg_tmp2[24] == 1'b1)
done_pin_drv[2] = 1;
else
done_pin_drv[2] = 0;
if (cor0_reg_tmp2[28] == 1'b1)
crc_bypass[2] = 1;
else
crc_bypass[2] = 0;
end
always @(cor0_reg[3])
begin
cor0_reg_tmp3 = cor0_reg[3];
done_cycle_reg3 = cor0_reg_tmp3[14:12];
lock_cycle_reg3 = cor0_reg_tmp3[8:6];
gts_cycle_reg3 = cor0_reg_tmp3[5:3];
gwe_cycle_reg3 = cor0_reg_tmp3[2:0];
if (cor0_reg_tmp3[24] == 1'b1)
done_pin_drv[3] = 1;
else
done_pin_drv[3] = 0;
if (cor0_reg_tmp3[28] == 1'b1)
crc_bypass[3] = 1;
else
crc_bypass[3] = 0;
end
always @(cor1_reg[0]) begin
cor1_reg_tmp0 = cor1_reg[0];
rbcrc_no_pin[0] = cor1_reg_tmp0[8];
end
always @(cor1_reg[1]) begin
cor1_reg_tmp1 = cor1_reg[1];
rbcrc_no_pin[1] = cor1_reg_tmp1[8];
end
always @(cor1_reg[2]) begin
cor1_reg_tmp2 = cor1_reg[2];
rbcrc_no_pin[2] = cor1_reg_tmp2[8];
end
always @(cor1_reg[3]) begin
cor1_reg_tmp3 = cor1_reg[3];
rbcrc_no_pin[3] = cor1_reg_tmp3[8];
end
assign stat_reg_tmp0[31:27] = 5'b00000;
assign stat_reg_tmp1[31:27] = 5'b00000;
assign stat_reg_tmp2[31:27] = 5'b00000;
assign stat_reg_tmp3[31:27] = 5'b00000;
assign stat_reg_tmp0[24:21] = 4'bxxx0;
assign stat_reg_tmp1[24:21] = 4'bxxx0;
assign stat_reg_tmp2[24:21] = 4'bxxx0;
assign stat_reg_tmp3[24:21] = 4'bxxx0;
assign stat_reg_tmp0[17:16] = 2'b0;
assign stat_reg_tmp1[17:16] = 2'b0;
assign stat_reg_tmp2[17:16] = 2'b0;
assign stat_reg_tmp3[17:16] = 2'b0;
assign stat_reg_tmp0[14] = DONE;
assign stat_reg_tmp1[14] = DONE;
assign stat_reg_tmp2[14] = DONE;
assign stat_reg_tmp3[14] = DONE;
assign stat_reg_tmp0[13] = (done_o[0] !== 0) ? 1 : 0;
assign stat_reg_tmp1[13] = (done_o[1] !== 0) ? 1 : 0;
assign stat_reg_tmp2[13] = (done_o[2] !== 0) ? 1 : 0;
assign stat_reg_tmp3[13] = (done_o[3] !== 0) ? 1 : 0;
assign stat_reg_tmp0[12] = INITB;
assign stat_reg_tmp1[12] = INITB;
assign stat_reg_tmp2[12] = INITB;
assign stat_reg_tmp3[12] = INITB;
assign stat_reg_tmp0[11] = mode_sample_flag;
assign stat_reg_tmp1[11] = mode_sample_flag;
assign stat_reg_tmp2[11] = mode_sample_flag;
assign stat_reg_tmp3[11] = mode_sample_flag;
assign stat_reg_tmp0[10:8] = mode_pin_in;
assign stat_reg_tmp1[10:8] = mode_pin_in;
assign stat_reg_tmp2[10:8] = mode_pin_in;
assign stat_reg_tmp3[10:8] = mode_pin_in;
assign stat_reg_tmp0[3] = 1'b1;
assign stat_reg_tmp1[3] = 1'b1;
assign stat_reg_tmp2[3] = 1'b1;
assign stat_reg_tmp3[3] = 1'b1;
assign stat_reg_tmp0[2] = pll_locked;
assign stat_reg_tmp1[2] = pll_locked;
assign stat_reg_tmp2[2] = pll_locked;
assign stat_reg_tmp3[2] = pll_locked;
assign stat_reg_tmp0[1] = 1'b0;
assign stat_reg_tmp1[1] = 1'b0;
assign stat_reg_tmp2[1] = 1'b0;
assign stat_reg_tmp3[1] = 1'b0;
assign stat_reg_tmp0[26:25] = buswidth[0];
assign stat_reg_tmp0[20:18] = st_state0;
assign stat_reg_tmp0[15] = id_error_flag[0];
assign stat_reg_tmp0[7] = ghigh_b[0];
assign stat_reg_tmp0[6] = gwe_out[0];
assign stat_reg_tmp0[5] = gts_cfg_b[0];
assign stat_reg_tmp0[4] = eos_startup[0];
assign stat_reg_tmp0[0] = crc_err_flag_reg[0];
assign stat_reg_tmp1[26:25] = buswidth[1];
assign stat_reg_tmp1[20:18] = st_state1;
assign stat_reg_tmp1[15] = id_error_flag[1];
assign stat_reg_tmp1[7] = ghigh_b[1];
assign stat_reg_tmp1[6] = gwe_out[1];
assign stat_reg_tmp1[5] = gts_cfg_b[1];
assign stat_reg_tmp1[4] = eos_startup[1];
assign stat_reg_tmp1[0] = crc_err_flag_reg[1];
assign stat_reg_tmp2[26:25] = buswidth[2];
assign stat_reg_tmp2[20:18] = st_state2;
assign stat_reg_tmp2[15] = id_error_flag[2];
assign stat_reg_tmp2[7] = ghigh_b[2];
assign stat_reg_tmp2[6] = gwe_out[2];
assign stat_reg_tmp2[5] = gts_cfg_b[2];
assign stat_reg_tmp2[4] = eos_startup[2];
assign stat_reg_tmp2[0] = crc_err_flag_reg[2];
assign stat_reg_tmp3[26:25] = buswidth[3];
assign stat_reg_tmp3[20:18] = st_state3;
assign stat_reg_tmp3[15] = id_error_flag[3];
assign stat_reg_tmp3[7] = ghigh_b[3];
assign stat_reg_tmp3[6] = gwe_out[3];
assign stat_reg_tmp3[5] = gts_cfg_b[3];
assign stat_reg_tmp3[4] = eos_startup[3];
assign stat_reg_tmp3[0] = crc_err_flag_reg[3];
assign stat_reg[0] = stat_reg_tmp0;
assign stat_reg[1] = stat_reg_tmp1;
assign stat_reg[2] = stat_reg_tmp2;
assign stat_reg[3] = stat_reg_tmp3;
always @(posedge cclk_in or negedge rst_intl)
if (rst_intl == 0) begin
st_state0 <= STARTUP_PH0;
st_state1 <= STARTUP_PH0;
st_state2 <= STARTUP_PH0;
st_state3 <= STARTUP_PH0;
startup_begin_flag0 <= 0;
startup_begin_flag1 <= 0;
startup_begin_flag2 <= 0;
startup_begin_flag3 <= 0;
startup_end_flag0 <= 0;
startup_end_flag1 <= 0;
startup_end_flag2 <= 0;
startup_end_flag3 <= 0;
end
else begin
st_state0i = st_state0;
cur_st_tsk(startup_begin_flag0, startup_end_flag0, st_state0,
st_state0i, nx_st_state0,lock_cycle_reg0);
st_state1i = st_state1;
cur_st_tsk(startup_begin_flag1, startup_end_flag1, st_state1,
st_state1i, nx_st_state1,lock_cycle_reg1);
st_state2i = st_state2;
cur_st_tsk(startup_begin_flag2, startup_end_flag2, st_state2,
st_state2i, nx_st_state2,lock_cycle_reg2);
st_state3i = st_state3;
cur_st_tsk(startup_begin_flag3, startup_end_flag3, st_state3,
st_state3i, nx_st_state3,lock_cycle_reg3);
end
task cur_st_tsk;
output stup_bflag;
output stup_eflag;
output [2:0] cst_o;
input [2:0] cst_in;
input [2:0] nst_in;
input [2:0] lock_cycle_in;
begin
if (nst_in == STARTUP_PH1) begin
stup_bflag = 1;
stup_eflag = 0;
end
else if (cst_in == STARTUP_PH7) begin
stup_eflag = 1;
stup_bflag = 0;
end
if ((lock_cycle_in == 3'b111) || (pll_locked == 1) || (pll_locked == 0 && cst_in != lock_cycle_in)) begin
cst_o = nst_in;
end
else
cst_o = cst_in;
end
endtask
always @(st_state0 or startup_set_pulse0 or DONE ) begin
nx_st_tsk(nx_st_state0,st_state0, startup_set_pulse0, done_cycle_reg0);
end
always @(st_state1 or startup_set_pulse1 or DONE ) begin
nx_st_tsk(nx_st_state1,st_state1, startup_set_pulse1, done_cycle_reg1);
end
always @(st_state2 or startup_set_pulse2 or DONE ) begin
nx_st_tsk(nx_st_state2,st_state2, startup_set_pulse2, done_cycle_reg2);
end
always @(st_state3 or startup_set_pulse3 or DONE ) begin
nx_st_tsk(nx_st_state3,st_state3, startup_set_pulse3, done_cycle_reg3);
end
task nx_st_tsk;
output [2:0] nx_st;
input [2:0] cur_st;
input [1:0] stup_pulse;
input [2:0] done_cycle_in;
begin
if (((cur_st == done_cycle_in) && (DONE !== 0)) || (cur_st != done_cycle_in))
case (cur_st)
STARTUP_PH0 : if (stup_pulse == 2'b11 )
nx_st = STARTUP_PH1;
else
nx_st = STARTUP_PH0;
STARTUP_PH1 : nx_st = STARTUP_PH2;
STARTUP_PH2 : nx_st = STARTUP_PH3;
STARTUP_PH3 : nx_st = STARTUP_PH4;
STARTUP_PH4 : nx_st = STARTUP_PH5;
STARTUP_PH5 : nx_st = STARTUP_PH6;
STARTUP_PH6 : nx_st = STARTUP_PH7;
STARTUP_PH7 : nx_st = STARTUP_PH0;
endcase
end
endtask
always @(posedge cclk_in or negedge rst_intl )
if (rst_intl == 0) begin
gwe_out <= 4'b0;
gts_out <= 4'b1111;
eos_startup <= 4'b0;
gsr_st_out <= 4'b1111;
done_o <= 4'b0;
end
else begin
if (nx_st_state0 == done_cycle_reg0 || st_state0 == done_cycle_reg0) begin
if (DONE !== 0 || done_pin_drv[0] === 1)
done_o[0] <= 1'b1;
else
done_o[0] <= 1'bz;
end
if (nx_st_state1 == done_cycle_reg1 || st_state1 == done_cycle_reg1) begin
if (DONE !== 0 || done_pin_drv[1] == 1)
done_o[1] <= 1'b1;
else
done_o[1] <= 1'bz;
end
if (nx_st_state2 == done_cycle_reg2 || st_state2 == done_cycle_reg2) begin
if (DONE !== 0 || done_pin_drv[2] == 1)
done_o[2] <= 1'b1;
else
done_o[2] <= 1'bz;
end
if (nx_st_state3 == done_cycle_reg3 || st_state3 == done_cycle_reg3) begin
if (DONE !== 0 || done_pin_drv[3] == 1)
done_o[3] <= 1'b1;
else
done_o[3] <= 1'bz;
end
if (st_state0 == gwe_cycle_reg0)
gwe_out[0] <= 1;
if (st_state1 == gwe_cycle_reg1)
gwe_out[1] <= 1;
if (st_state2 == gwe_cycle_reg2)
gwe_out[2] <= 1;
if (st_state3 == gwe_cycle_reg3)
gwe_out[3] <= 1;
if (st_state0 == gts_cycle_reg0 )
gts_out[0] <= 0;
if (st_state1 == gts_cycle_reg1 )
gts_out[1] <= 0;
if (st_state2 == gts_cycle_reg2 )
gts_out[2] <= 0;
if (st_state3 == gts_cycle_reg3 )
gts_out[3] <= 0;
if (st_state0 == STARTUP_PH6 )
gsr_st_out[0] <= 0;
if (st_state1 == STARTUP_PH6 )
gsr_st_out[1] <= 0;
if (st_state2 == STARTUP_PH6 )
gsr_st_out[2] <= 0;
if (st_state3 == STARTUP_PH6 )
gsr_st_out[3] <= 0;
if (st_state0 == STARTUP_PH7 )
eos_startup[0] <= 1;
if (st_state1 == STARTUP_PH7 )
eos_startup[1] <= 1;
if (st_state2 == STARTUP_PH7 )
eos_startup[2] <= 1;
if (st_state3 == STARTUP_PH7 )
eos_startup[3] <= 1;
end
assign gsr_out[0] = gsr_st_out[0] | gsr_cmd_out[0];
assign gsr_out[1] = gsr_st_out[1] | gsr_cmd_out[1];
assign gsr_out[2] = gsr_st_out[2] | gsr_cmd_out[2];
assign gsr_out[3] = gsr_st_out[3] | gsr_cmd_out[3];
assign abort_dis_bi = abort_dis[ib];
always @(posedge cclk_in or negedge rst_intl or
posedge abort_flag_rst or posedge csi_b_in)
if (rst_intl == 0 || abort_flag_rst == 1 || csi_b_in == 1) begin
abort_flag[ib] <= 0;
checka_en <= 0;
rdwr_b_in1 <= rdwr_b_in;
end
else begin
if ( abort_dis_bi == 0 && csi_b_in == 0) begin
if ((rdwr_b_in1 != rdwr_b_in) && checka_en != 0) begin
abort_flag[ib] <= 1;
if (icap_on == 0)
$display("Warning: [Unisim %s-10]Warning : RDWRB changes when CSB low, which causes Configuration abort at time %t. Instance %m", MODULE_NAME, $time);
end
end
else
abort_flag[ib] <= 0;
rdwr_b_in1 <= rdwr_b_in;
checka_en <= 1;
end
always @(posedge abort_flag[ib])
begin
abort_out_en <= 1;
abort_status <= {cfgerr_b_flag[ib], bus_sync_flag[ib], 1'b0, 1'b1, 4'b1111};
@(posedge cclk_in)
abort_status <= {cfgerr_b_flag[ib], 1'b1, 1'b0, 1'b0, 4'b1111};
@(posedge cclk_in)
abort_status <= {cfgerr_b_flag[ib], 1'b0, 1'b0, 1'b0, 4'b1111};
@(posedge cclk_in)
abort_status <= {cfgerr_b_flag[ib], 1'b0, 1'b0, 1'b1, 4'b1111};
@(posedge cclk_in) begin
abort_out_en <= 0;
abort_flag_rst <= 1;
end
@(posedge cclk_in)
abort_flag_rst <= 0;
end
function [31:0] bcc_next;
input [31:0] bcc;
input [36:0] in;
reg [31:0] x;
reg [36:0] m;
begin
m = in;
x = in[31:0] ^ bcc;
bcc_next[31] = m[32]^m[36]^x[31]^x[30]^x[29]^x[28]^x[27]^x[24]^x[20]^x[19]^x[18]^x[15]^x[13]^x[11]^x[10]^x[9]^x[8]^x[6]^x[5]^x[1]^x[0];
bcc_next[30] = m[35]^x[31]^x[30]^x[29]^x[28]^x[27]^x[26]^x[23]^x[19]^x[18]^x[17]^x[14]^x[12]^x[10]^x[9]^x[8]^x[7]^x[5]^x[4]^x[0];
bcc_next[29] = m[34]^x[30]^x[29]^x[28]^x[27]^x[26]^x[25]^x[22]^x[18]^x[17]^x[16]^x[13]^x[11]^x[9]^x[8]^x[7]^x[6]^x[4]^x[3];
bcc_next[28] = m[33]^x[29]^x[28]^x[27]^x[26]^x[25]^x[24]^x[21]^x[17]^x[16]^x[15]^x[12]^x[10]^x[8]^x[7]^x[6]^x[5]^x[3]^x[2];
bcc_next[27] = m[32]^x[28]^x[27]^x[26]^x[25]^x[24]^x[23]^x[20]^x[16]^x[15]^x[14]^x[11]^x[9]^x[7]^x[6]^x[5]^x[4]^x[2]^x[1];
bcc_next[26] = x[31]^x[27]^x[26]^x[25]^x[24]^x[23]^x[22]^x[19]^x[15]^x[14]^x[13]^x[10]^x[8]^x[6]^x[5]^x[4]^x[3]^x[1]^x[0];
bcc_next[25] = m[32]^m[36]^x[31]^x[29]^x[28]^x[27]^x[26]^x[25]^x[23]^x[22]^x[21]^x[20]^x[19]^x[15]^x[14]^x[12]^x[11]^x[10]^x[8]^x[7]^x[6]^x[4]^x[3]^x[2]^x[1];
bcc_next[24] = m[35]^x[31]^x[30]^x[28]^x[27]^x[26]^x[25]^x[24]^x[22]^x[21]^x[20]^x[19]^x[18]^x[14]^x[13]^x[11]^x[10]^x[9]^x[7]^x[6]^x[5]^x[3]^x[2]^x[1]^x[0];
bcc_next[23] = m[32]^m[34]^m[36]^x[31]^x[28]^x[26]^x[25]^x[23]^x[21]^x[17]^x[15]^x[12]^x[11]^x[4]^x[2];
bcc_next[22] = m[32]^m[33]^m[35]^m[36]^x[29]^x[28]^x[25]^x[22]^x[19]^x[18]^x[16]^x[15]^x[14]^x[13]^x[9]^x[8]^x[6]^x[5]^x[3]^x[0];
bcc_next[21] = m[34]^m[35]^m[36]^x[30]^x[29]^x[21]^x[20]^x[19]^x[17]^x[14]^x[12]^x[11]^x[10]^x[9]^x[7]^x[6]^x[4]^x[2]^x[1]^x[0];
bcc_next[20] = m[32]^m[33]^m[34]^m[35]^m[36]^x[31]^x[30]^x[27]^x[24]^x[16]^x[15]^x[3];
bcc_next[19] = m[32]^m[33]^m[34]^m[35]^x[31]^x[30]^x[29]^x[26]^x[23]^x[15]^x[14]^x[2];
bcc_next[18] = m[33]^m[34]^m[36]^x[27]^x[25]^x[24]^x[22]^x[20]^x[19]^x[18]^x[15]^x[14]^x[11]^x[10]^x[9]^x[8]^x[6]^x[5]^x[0];
bcc_next[17] = m[33]^m[35]^m[36]^x[31]^x[30]^x[29]^x[28]^x[27]^x[26]^x[23]^x[21]^x[20]^x[17]^x[15]^x[14]^x[11]^x[7]^x[6]^x[4]^x[1]^x[0];
bcc_next[16] = m[32]^m[34]^m[35]^x[30]^x[29]^x[28]^x[27]^x[26]^x[25]^x[22]^x[20]^x[19]^x[16]^x[14]^x[13]^x[10]^x[6]^x[5]^x[3]^x[0];
bcc_next[15] = m[33]^m[34]^x[31]^x[29]^x[28]^x[27]^x[26]^x[25]^x[24]^x[21]^x[19]^x[18]^x[15]^x[13]^x[12]^x[9]^x[5]^x[4]^x[2];
bcc_next[14] = m[32]^m[33]^x[30]^x[28]^x[27]^x[26]^x[25]^x[24]^x[23]^x[20]^x[18]^x[17]^x[14]^x[12]^x[11]^x[8]^x[4]^x[3]^x[1];
bcc_next[13] = m[36]^x[30]^x[28]^x[26]^x[25]^x[23]^x[22]^x[20]^x[18]^x[17]^x[16]^x[15]^x[9]^x[8]^x[7]^x[6]^x[5]^x[3]^x[2]^x[1];
bcc_next[12] = m[32]^m[35]^m[36]^x[31]^x[30]^x[28]^x[25]^x[22]^x[21]^x[20]^x[18]^x[17]^x[16]^x[14]^x[13]^x[11]^x[10]^x[9]^x[7]^x[4]^x[2];
bcc_next[11] = m[32]^m[34]^m[35]^m[36]^x[28]^x[21]^x[18]^x[17]^x[16]^x[12]^x[11]^x[5]^x[3]^x[0];
bcc_next[10] = m[33]^m[34]^m[35]^x[31]^x[27]^x[20]^x[17]^x[16]^x[15]^x[11]^x[10]^x[4]^x[2];
bcc_next[9] = m[33]^m[34]^m[36]^x[31]^x[29]^x[28]^x[27]^x[26]^x[24]^x[20]^x[18]^x[16]^x[14]^x[13]^x[11]^x[8]^x[6]^x[5]^x[3]^x[0];
bcc_next[8] = m[33]^m[35]^m[36]^x[31]^x[29]^x[26]^x[25]^x[24]^x[23]^x[20]^x[18]^x[17]^x[12]^x[11]^x[9]^x[8]^x[7]^x[6]^x[4]^x[2]^x[1]^x[0];
bcc_next[7] = m[32]^m[34]^m[35]^x[30]^x[28]^x[25]^x[24]^x[23]^x[22]^x[19]^x[17]^x[16]^x[11]^x[10]^x[8]^x[7]^x[6]^x[5]^x[3]^x[1]^x[0];
bcc_next[6] = m[32]^m[33]^m[34]^m[36]^x[30]^x[28]^x[23]^x[22]^x[21]^x[20]^x[19]^x[16]^x[13]^x[11]^x[8]^x[7]^x[4]^x[2]^x[1];
bcc_next[5] = m[33]^m[35]^m[36]^x[30]^x[28]^x[24]^x[22]^x[21]^x[13]^x[12]^x[11]^x[9]^x[8]^x[7]^x[5]^x[3];
bcc_next[4] = m[34]^m[35]^m[36]^x[31]^x[30]^x[28]^x[24]^x[23]^x[21]^x[19]^x[18]^x[15]^x[13]^x[12]^x[9]^x[7]^x[5]^x[4]^x[2]^x[1]^x[0];
bcc_next[3] = m[32]^m[33]^m[34]^m[35]^m[36]^x[31]^x[28]^x[24]^x[23]^x[22]^x[19]^x[17]^x[15]^x[14]^x[13]^x[12]^x[10]^x[9]^x[5]^x[4]^x[3];
bcc_next[2] = m[32]^m[33]^m[34]^m[35]^x[31]^x[30]^x[27]^x[23]^x[22]^x[21]^x[18]^x[16]^x[14]^x[13]^x[12]^x[11]^x[9]^x[8]^x[4]^x[3]^x[2];
bcc_next[1] = m[32]^m[33]^m[34]^x[31]^x[30]^x[29]^x[26]^x[22]^x[21]^x[20]^x[17]^x[15]^x[13]^x[12]^x[11]^x[10]^x[8]^x[7]^x[3]^x[2]^x[1];
bcc_next[0] = m[32]^m[33]^x[31]^x[30]^x[29]^x[28]^x[25]^x[21]^x[20]^x[19]^x[16]^x[14]^x[12]^x[11]^x[10]^x[9]^x[7]^x[6]^x[2]^x[1]^x[0];
end
endfunction
function [7:0] bit_revers8;
input [7:0] din8;
begin
bit_revers8[0] = din8[7];
bit_revers8[1] = din8[6];
bit_revers8[2] = din8[5];
bit_revers8[3] = din8[4];
bit_revers8[4] = din8[3];
bit_revers8[5] = din8[2];
bit_revers8[6] = din8[1];
bit_revers8[7] = din8[0];
end
endfunction
task rdbk_byte;
input [31:0] rdbk_reg;
input integer rd_dcnt;
begin
outbus[31:8] <= 24'b0;
if (rd_dcnt==1)
outbus[7:0] <= bit_revers8(rdbk_reg[7:0]);
else if (rd_dcnt==2)
outbus[7:0] <= bit_revers8(rdbk_reg[15:8]);
else if (rd_dcnt==3)
outbus[7:0] <= bit_revers8(rdbk_reg[23:16]);
else if (rd_dcnt==4)
outbus[7:0] <= bit_revers8(rdbk_reg[31:24]);
end
endtask
task rdbk_wd;
input [31:0] rdbk_reg;
input integer rd_dcnt;
begin
outbus[31:16] <= 16'b0;
if (rd_dcnt==1)
outbus[15:0] <= 16'b0;
else if (rd_dcnt==2)
outbus[15:0] <= 16'b0;
else if (rd_dcnt==3) begin
outbus[7:0] <= bit_revers8(rdbk_reg[7:0]);
outbus[15:8] <= bit_revers8(rdbk_reg[15:8]);
end
else if (rd_dcnt==4) begin
outbus[7:0] <= bit_revers8(rdbk_reg[23:16]);
outbus[15:8] <= bit_revers8(rdbk_reg[31:24]);
end
end
endtask
task rdbk_2wd;
input [31:0] rdbk_reg;
input integer rd_dcnt;
begin
if (rd_dcnt==1)
outbus <= 32'b0;
else if (rd_dcnt==2)
outbus <= 32'b0;
else if (rd_dcnt==3)
outbus <= 32'b0;
else if (rd_dcnt==4) begin
outbus[7:0] <= bit_revers8(rdbk_reg[7:0]);
outbus[15:8] <= bit_revers8(rdbk_reg[15:8]);
outbus[23:16] <= bit_revers8(rdbk_reg[23:16]);
outbus[31:24] <= bit_revers8(rdbk_reg[31:24]);
end
end
endtask
specify
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
/******************************************************************************
-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
*****************************************************************************
*
* Filename: blk_mem_gen_v8_3_5.v
*
* Description:
* This file is the Verilog behvarial model for the
* Block Memory Generator Core.
*
*****************************************************************************
* Author: Xilinx
*
* History: Jan 11, 2006 Initial revision
* Jun 11, 2007 Added independent register stages for
* Port A and Port B (IP1_Jm/v2.5)
* Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)
* Mar 13, 2008 Behavioral model optimizations
* April 07, 2009 : Added support for Spartan-6 and Virtex-6
* features, including the following:
* (i) error injection, detection and/or correction
* (ii) reset priority
* (iii) special reset behavior
*
*****************************************************************************/
`timescale 1ps/1ps
module STATE_LOGIC_v8_3 (O, I0, I1, I2, I3, I4, I5);
parameter INIT = 64'h0000000000000000;
input I0, I1, I2, I3, I4, I5;
output O;
reg O;
reg tmp;
always @( I5 or I4 or I3 or I2 or I1 or I0 ) begin
tmp = I0 ^ I1 ^ I2 ^ I3 ^ I4 ^ I5;
if ( tmp == 0 || tmp == 1)
O = INIT[{I5, I4, I3, I2, I1, I0}];
end
endmodule
module beh_vlog_muxf7_v8_3 (O, I0, I1, S);
output O;
reg O;
input I0, I1, S;
always @(I0 or I1 or S)
if (S)
O = I1;
else
O = I0;
endmodule
module beh_vlog_ff_clr_v8_3 (Q, C, CLR, D);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, CLR, D;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (CLR)
Q<= 1'b0;
else
Q<= #FLOP_DELAY D;
endmodule
module beh_vlog_ff_pre_v8_3 (Q, C, D, PRE);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, D, PRE;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (PRE)
Q <= 1'b1;
else
Q <= #FLOP_DELAY D;
endmodule
module beh_vlog_ff_ce_clr_v8_3 (Q, C, CE, CLR, D);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, CE, CLR, D;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (CLR)
Q <= 1'b0;
else if (CE)
Q <= #FLOP_DELAY D;
endmodule
module write_netlist_v8_3
#(
parameter C_AXI_TYPE = 0
)
(
S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,
w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,
S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c
);
input S_ACLK;
input S_ARESETN;
input S_AXI_AWVALID;
input S_AXI_WVALID;
input S_AXI_BREADY;
input w_last_c;
input bready_timeout_c;
output aw_ready_r;
output S_AXI_WREADY;
output S_AXI_BVALID;
output S_AXI_WR_EN;
output addr_en_c;
output incr_addr_c;
output bvalid_c;
//-------------------------------------------------------------------------
//AXI LITE
//-------------------------------------------------------------------------
generate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm
wire w_ready_r_7;
wire w_ready_c;
wire aw_ready_c;
wire NlwRenamedSignal_bvalid_c;
wire NlwRenamedSignal_incr_addr_c;
wire present_state_FSM_FFd3_13;
wire present_state_FSM_FFd2_14;
wire present_state_FSM_FFd1_15;
wire present_state_FSM_FFd4_16;
wire present_state_FSM_FFd4_In;
wire present_state_FSM_FFd3_In;
wire present_state_FSM_FFd2_In;
wire present_state_FSM_FFd1_In;
wire present_state_FSM_FFd4_In1_21;
wire [0:0] Mmux_aw_ready_c ;
begin
assign
S_AXI_WREADY = w_ready_r_7,
S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,
S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,
incr_addr_c = NlwRenamedSignal_incr_addr_c,
bvalid_c = NlwRenamedSignal_bvalid_c;
assign NlwRenamedSignal_incr_addr_c = 1'b0;
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
aw_ready_r_2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( aw_ready_c),
.Q ( aw_ready_r)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
w_ready_r (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( w_ready_c),
.Q ( w_ready_r_7)
);
beh_vlog_ff_pre_v8_3 #(
.INIT (1'b1))
present_state_FSM_FFd4 (
.C ( S_ACLK),
.D ( present_state_FSM_FFd4_In),
.PRE ( S_ARESETN),
.Q ( present_state_FSM_FFd4_16)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd3 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd3_In),
.Q ( present_state_FSM_FFd3_13)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_14)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd1 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd1_In),
.Q ( present_state_FSM_FFd1_15)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000055554440))
present_state_FSM_FFd3_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( S_AXI_AWVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd4_16),
.I4 ( present_state_FSM_FFd3_13),
.I5 (1'b0),
.O ( present_state_FSM_FFd3_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000088880800))
present_state_FSM_FFd2_In1 (
.I0 ( S_AXI_AWVALID),
.I1 ( S_AXI_WVALID),
.I2 ( bready_timeout_c),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( present_state_FSM_FFd4_16),
.I5 (1'b0),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000AAAA2000))
Mmux_addr_en_c_0_1 (
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( S_AXI_WVALID),
.I4 ( present_state_FSM_FFd4_16),
.I5 (1'b0),
.O ( addr_en_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hF5F07570F5F05500))
Mmux_w_ready_c_0_1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_13),
.I4 ( present_state_FSM_FFd4_16),
.I5 ( present_state_FSM_FFd2_14),
.O ( w_ready_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h88808880FFFF8880))
present_state_FSM_FFd1_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd3_13),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( present_state_FSM_FFd1_15),
.I5 ( S_AXI_BREADY),
.O ( present_state_FSM_FFd1_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000A8))
Mmux_S_AXI_WR_EN_0_1 (
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd2_14),
.I2 ( present_state_FSM_FFd3_13),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( NlwRenamedSignal_bvalid_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h2F0F27072F0F2200))
present_state_FSM_FFd4_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_13),
.I4 ( present_state_FSM_FFd4_16),
.I5 ( present_state_FSM_FFd2_14),
.O ( present_state_FSM_FFd4_In1_21)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000F8))
present_state_FSM_FFd4_In2 (
.I0 ( present_state_FSM_FFd1_15),
.I1 ( S_AXI_BREADY),
.I2 ( present_state_FSM_FFd4_In1_21),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd4_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h7535753575305500))
Mmux_aw_ready_c_0_1 (
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_WVALID),
.I3 ( present_state_FSM_FFd4_16),
.I4 ( present_state_FSM_FFd3_13),
.I5 ( present_state_FSM_FFd2_14),
.O ( Mmux_aw_ready_c[0])
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000F8))
Mmux_aw_ready_c_0_2 (
.I0 ( present_state_FSM_FFd1_15),
.I1 ( S_AXI_BREADY),
.I2 ( Mmux_aw_ready_c[0]),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( aw_ready_c)
);
end
end
endgenerate
//---------------------------------------------------------------------
// AXI FULL
//---------------------------------------------------------------------
generate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm
wire w_ready_r_8;
wire w_ready_c;
wire aw_ready_c;
wire NlwRenamedSig_OI_bvalid_c;
wire present_state_FSM_FFd1_16;
wire present_state_FSM_FFd4_17;
wire present_state_FSM_FFd3_18;
wire present_state_FSM_FFd2_19;
wire present_state_FSM_FFd4_In;
wire present_state_FSM_FFd3_In;
wire present_state_FSM_FFd2_In;
wire present_state_FSM_FFd1_In;
wire present_state_FSM_FFd2_In1_24;
wire present_state_FSM_FFd4_In1_25;
wire N2;
wire N4;
begin
assign
S_AXI_WREADY = w_ready_r_8,
bvalid_c = NlwRenamedSig_OI_bvalid_c,
S_AXI_BVALID = 1'b0;
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
aw_ready_r_2
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( aw_ready_c),
.Q ( aw_ready_r)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
w_ready_r
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( w_ready_c),
.Q ( w_ready_r_8)
);
beh_vlog_ff_pre_v8_3 #(
.INIT (1'b1))
present_state_FSM_FFd4
(
.C ( S_ACLK),
.D ( present_state_FSM_FFd4_In),
.PRE ( S_ARESETN),
.Q ( present_state_FSM_FFd4_17)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd3
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd3_In),
.Q ( present_state_FSM_FFd3_18)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd2
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_19)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd1
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd1_In),
.Q ( present_state_FSM_FFd1_16)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000005540))
present_state_FSM_FFd3_In1
(
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd4_17),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd3_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hBF3FBB33AF0FAA00))
Mmux_aw_ready_c_0_2
(
.I0 ( S_AXI_BREADY),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd1_16),
.I4 ( present_state_FSM_FFd4_17),
.I5 ( NlwRenamedSig_OI_bvalid_c),
.O ( aw_ready_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hAAAAAAAA20000000))
Mmux_addr_en_c_0_1
(
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( S_AXI_WVALID),
.I4 ( w_last_c),
.I5 ( present_state_FSM_FFd4_17),
.O ( addr_en_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000A8))
Mmux_S_AXI_WR_EN_0_1
(
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd2_19),
.I2 ( present_state_FSM_FFd3_18),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( S_AXI_WR_EN)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000002220))
Mmux_incr_addr_c_0_1
(
.I0 ( S_AXI_WVALID),
.I1 ( w_last_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( incr_addr_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000008880))
Mmux_aw_ready_c_0_11
(
.I0 ( S_AXI_WVALID),
.I1 ( w_last_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( NlwRenamedSig_OI_bvalid_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h000000000000D5C0))
present_state_FSM_FFd2_In1
(
.I0 ( w_last_c),
.I1 ( S_AXI_AWVALID),
.I2 ( present_state_FSM_FFd4_17),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd2_In1_24)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hFFFFAAAA08AAAAAA))
present_state_FSM_FFd2_In2
(
.I0 ( present_state_FSM_FFd2_19),
.I1 ( S_AXI_AWVALID),
.I2 ( bready_timeout_c),
.I3 ( w_last_c),
.I4 ( S_AXI_WVALID),
.I5 ( present_state_FSM_FFd2_In1_24),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00C0004000C00000))
present_state_FSM_FFd4_In1
(
.I0 ( S_AXI_AWVALID),
.I1 ( w_last_c),
.I2 ( S_AXI_WVALID),
.I3 ( bready_timeout_c),
.I4 ( present_state_FSM_FFd3_18),
.I5 ( present_state_FSM_FFd2_19),
.O ( present_state_FSM_FFd4_In1_25)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000FFFF88F8))
present_state_FSM_FFd4_In2
(
.I0 ( present_state_FSM_FFd1_16),
.I1 ( S_AXI_BREADY),
.I2 ( present_state_FSM_FFd4_17),
.I3 ( S_AXI_AWVALID),
.I4 ( present_state_FSM_FFd4_In1_25),
.I5 (1'b0),
.O ( present_state_FSM_FFd4_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000007))
Mmux_w_ready_c_0_SW0
(
.I0 ( w_last_c),
.I1 ( S_AXI_WVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( N2)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hFABAFABAFAAAF000))
Mmux_w_ready_c_0_Q
(
.I0 ( N2),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd4_17),
.I4 ( present_state_FSM_FFd3_18),
.I5 ( present_state_FSM_FFd2_19),
.O ( w_ready_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000008))
Mmux_aw_ready_c_0_11_SW0
(
.I0 ( bready_timeout_c),
.I1 ( S_AXI_WVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( N4)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h88808880FFFF8880))
present_state_FSM_FFd1_In1
(
.I0 ( w_last_c),
.I1 ( N4),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 ( present_state_FSM_FFd1_16),
.I5 ( S_AXI_BREADY),
.O ( present_state_FSM_FFd1_In)
);
end
end
endgenerate
endmodule
module read_netlist_v8_3 #(
parameter C_AXI_TYPE = 1,
parameter C_ADDRB_WIDTH = 12
) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,
S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,
S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,
S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);
input S_AXI_R_LAST_INT;
input S_ACLK;
input S_ARESETN;
input S_AXI_ARVALID;
input S_AXI_RREADY;
output S_AXI_INCR_ADDR;
output S_AXI_ADDR_EN;
output S_AXI_SINGLE_TRANS;
output S_AXI_MUX_SEL;
output S_AXI_R_LAST;
output S_AXI_ARREADY;
output S_AXI_RLAST;
output S_AXI_RVALID;
output S_AXI_RD_EN;
input [7:0] S_AXI_ARLEN;
wire present_state_FSM_FFd1_13 ;
wire present_state_FSM_FFd2_14 ;
wire gaxi_full_sm_outstanding_read_r_15 ;
wire gaxi_full_sm_ar_ready_r_16 ;
wire gaxi_full_sm_r_last_r_17 ;
wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ;
wire gaxi_full_sm_r_valid_c ;
wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ;
wire gaxi_full_sm_ar_ready_c ;
wire gaxi_full_sm_outstanding_read_c ;
wire NlwRenamedSig_OI_S_AXI_R_LAST ;
wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ;
wire present_state_FSM_FFd2_In ;
wire present_state_FSM_FFd1_In ;
wire Mmux_S_AXI_R_LAST13 ;
wire N01 ;
wire N2 ;
wire Mmux_gaxi_full_sm_ar_ready_c11 ;
wire N4 ;
wire N8 ;
wire N9 ;
wire N10 ;
wire N11 ;
wire N12 ;
wire N13 ;
assign
S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,
S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,
S_AXI_RLAST = gaxi_full_sm_r_last_r_17,
S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
gaxi_full_sm_outstanding_read_r (
.C (S_ACLK),
.CLR(S_ARESETN),
.D(gaxi_full_sm_outstanding_read_c),
.Q(gaxi_full_sm_outstanding_read_r_15)
);
beh_vlog_ff_ce_clr_v8_3 #(
.INIT (1'b0))
gaxi_full_sm_r_valid_r (
.C (S_ACLK),
.CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.CLR (S_ARESETN),
.D (gaxi_full_sm_r_valid_c),
.Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
gaxi_full_sm_ar_ready_r (
.C (S_ACLK),
.CLR (S_ARESETN),
.D (gaxi_full_sm_ar_ready_c),
.Q (gaxi_full_sm_ar_ready_r_16)
);
beh_vlog_ff_ce_clr_v8_3 #(
.INIT(1'b0))
gaxi_full_sm_r_last_r (
.C (S_ACLK),
.CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.CLR (S_ARESETN),
.D (NlwRenamedSig_OI_S_AXI_R_LAST),
.Q (gaxi_full_sm_r_last_r_17)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_14)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd1 (
.C (S_ACLK),
.CLR (S_ARESETN),
.D (present_state_FSM_FFd1_In),
.Q (present_state_FSM_FFd1_13)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h000000000000000B))
S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (
.I0 ( S_AXI_RREADY),
.I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000008))
Mmux_S_AXI_SINGLE_TRANS11 (
.I0 (S_AXI_ARVALID),
.I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_SINGLE_TRANS)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000004))
Mmux_S_AXI_ADDR_EN11 (
.I0 (present_state_FSM_FFd1_13),
.I1 (S_AXI_ARVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_ADDR_EN)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hECEE2022EEEE2022))
present_state_FSM_FFd2_In1 (
.I0 ( S_AXI_ARVALID),
.I1 ( present_state_FSM_FFd1_13),
.I2 ( S_AXI_RREADY),
.I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I4 ( present_state_FSM_FFd2_14),
.I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000044440444))
Mmux_S_AXI_R_LAST131 (
.I0 ( present_state_FSM_FFd1_13),
.I1 ( S_AXI_ARVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( S_AXI_RREADY),
.I5 (1'b0),
.O ( Mmux_S_AXI_R_LAST13)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h4000FFFF40004000))
Mmux_S_AXI_INCR_ADDR11 (
.I0 ( S_AXI_R_LAST_INT),
.I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd1_13),
.I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I5 ( Mmux_S_AXI_R_LAST13),
.O ( S_AXI_INCR_ADDR)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000FE))
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (
.I0 ( S_AXI_ARLEN[2]),
.I1 ( S_AXI_ARLEN[1]),
.I2 ( S_AXI_ARLEN[0]),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N01)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000001))
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (
.I0 ( S_AXI_ARLEN[7]),
.I1 ( S_AXI_ARLEN[6]),
.I2 ( S_AXI_ARLEN[5]),
.I3 ( S_AXI_ARLEN[4]),
.I4 ( S_AXI_ARLEN[3]),
.I5 ( N01),
.O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000007))
Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (
.I0 ( S_AXI_ARVALID),
.I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I2 ( 1'b0),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N2)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0020000002200200))
Mmux_gaxi_full_sm_outstanding_read_c1 (
.I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd1_13),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( gaxi_full_sm_outstanding_read_r_15),
.I5 ( N2),
.O ( gaxi_full_sm_outstanding_read_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000004555))
Mmux_gaxi_full_sm_ar_ready_c12 (
.I0 ( S_AXI_ARVALID),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( Mmux_gaxi_full_sm_ar_ready_c11)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000EF))
Mmux_S_AXI_R_LAST11_SW0 (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_RREADY),
.I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N4)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hFCAAFC0A00AA000A))
Mmux_S_AXI_R_LAST11 (
.I0 ( S_AXI_ARVALID),
.I1 ( gaxi_full_sm_outstanding_read_r_15),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd1_13),
.I4 ( N4),
.I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.O ( gaxi_full_sm_r_valid_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000AAAAAA08))
S_AXI_MUX_SEL1 (
.I0 (present_state_FSM_FFd1_13),
.I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 (S_AXI_RREADY),
.I3 (present_state_FSM_FFd2_14),
.I4 (gaxi_full_sm_outstanding_read_r_15),
.I5 (1'b0),
.O (S_AXI_MUX_SEL)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hF3F3F755A2A2A200))
Mmux_S_AXI_RD_EN11 (
.I0 ( present_state_FSM_FFd1_13),
.I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 ( S_AXI_RREADY),
.I3 ( gaxi_full_sm_outstanding_read_r_15),
.I4 ( present_state_FSM_FFd2_14),
.I5 ( S_AXI_ARVALID),
.O ( S_AXI_RD_EN)
);
beh_vlog_muxf7_v8_3 present_state_FSM_FFd1_In3 (
.I0 ( N8),
.I1 ( N9),
.S ( present_state_FSM_FFd1_13),
.O ( present_state_FSM_FFd1_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h000000005410F4F0))
present_state_FSM_FFd1_In3_F (
.I0 ( S_AXI_RREADY),
.I1 ( present_state_FSM_FFd2_14),
.I2 ( S_AXI_ARVALID),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I5 ( 1'b0),
.O ( N8)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000072FF7272))
present_state_FSM_FFd1_In3_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( S_AXI_R_LAST_INT),
.I2 ( gaxi_full_sm_outstanding_read_r_15),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N9)
);
beh_vlog_muxf7_v8_3 Mmux_gaxi_full_sm_ar_ready_c14 (
.I0 ( N10),
.I1 ( N11),
.S ( present_state_FSM_FFd1_13),
.O ( gaxi_full_sm_ar_ready_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000FFFF88A8))
Mmux_gaxi_full_sm_ar_ready_c14_F (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( Mmux_gaxi_full_sm_ar_ready_c11),
.I5 ( 1'b0),
.O ( N10)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h000000008D008D8D))
Mmux_gaxi_full_sm_ar_ready_c14_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( S_AXI_R_LAST_INT),
.I2 ( gaxi_full_sm_outstanding_read_r_15),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N11)
);
beh_vlog_muxf7_v8_3 Mmux_S_AXI_R_LAST1 (
.I0 ( N12),
.I1 ( N13),
.S ( present_state_FSM_FFd1_13),
.O ( NlwRenamedSig_OI_S_AXI_R_LAST)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000088088888))
Mmux_S_AXI_R_LAST1_F (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_ARVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N12)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000E400E4E4))
Mmux_S_AXI_R_LAST1_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( gaxi_full_sm_outstanding_read_r_15),
.I2 ( S_AXI_R_LAST_INT),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N13)
);
endmodule
module blk_mem_axi_write_wrapper_beh_v8_3
# (
// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0, // 0: Native Interface; 1: AXI Interface
parameter C_AXI_TYPE = 0, // 0: AXI Lite; 1: AXI Full;
parameter C_AXI_SLAVE_TYPE = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
parameter C_MEMORY_TYPE = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
parameter C_WRITE_DEPTH_A = 0,
parameter C_AXI_AWADDR_WIDTH = 32,
parameter C_ADDRA_WIDTH = 12,
parameter C_AXI_WDATA_WIDTH = 32,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
// AXI OUTSTANDING WRITES
parameter C_AXI_OS_WR = 2
)
(
// AXI Global Signals
input S_ACLK,
input S_ARESETN,
// AXI Full/Lite Slave Write Channel (write side)
input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,
input [8-1:0] S_AXI_AWLEN,
input [2:0] S_AXI_AWSIZE,
input [1:0] S_AXI_AWBURST,
input S_AXI_AWVALID,
output S_AXI_AWREADY,
input S_AXI_WVALID,
output S_AXI_WREADY,
output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,
output S_AXI_BVALID,
input S_AXI_BREADY,
// Signals for BMG interface
output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,
output S_AXI_WR_EN
);
localparam FLOP_DELAY = 100; // 100 ps
localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:
((C_AXI_WDATA_WIDTH==16)?1:
((C_AXI_WDATA_WIDTH==32)?2:
((C_AXI_WDATA_WIDTH==64)?3:
((C_AXI_WDATA_WIDTH==128)?4:
((C_AXI_WDATA_WIDTH==256)?5:0))))));
wire bvalid_c ;
reg bready_timeout_c = 0;
wire [1:0] bvalid_rd_cnt_c;
reg bvalid_r = 0;
reg [2:0] bvalid_count_r = 0;
reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;
reg [1:0] bvalid_wr_cnt_r = 0;
reg [1:0] bvalid_rd_cnt_r = 0;
wire w_last_c ;
wire addr_en_c ;
wire incr_addr_c ;
wire aw_ready_r ;
wire dec_alen_c ;
reg bvalid_d1_c = 0;
reg [7:0] awlen_cntr_r = 0;
reg [7:0] awlen_int = 0;
reg [1:0] awburst_int = 0;
integer total_bytes = 0;
integer wrap_boundary = 0;
integer wrap_base_addr = 0;
integer num_of_bytes_c = 0;
integer num_of_bytes_r = 0;
// Array to store BIDs
reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;
wire S_AXI_BVALID_axi_wr_fsm;
//-------------------------------------
//AXI WRITE FSM COMPONENT INSTANTIATION
//-------------------------------------
write_netlist_v8_3 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm
(
.S_ACLK(S_ACLK),
.S_ARESETN(S_ARESETN),
.S_AXI_AWVALID(S_AXI_AWVALID),
.aw_ready_r(aw_ready_r),
.S_AXI_WVALID(S_AXI_WVALID),
.S_AXI_WREADY(S_AXI_WREADY),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_WR_EN(S_AXI_WR_EN),
.w_last_c(w_last_c),
.bready_timeout_c(bready_timeout_c),
.addr_en_c(addr_en_c),
.incr_addr_c(incr_addr_c),
.bvalid_c(bvalid_c),
.S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm)
);
//Wrap Address boundary calculation
always@(*) begin
num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);
total_bytes = (num_of_bytes_r)*(awlen_int+1);
wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);
wrap_boundary = wrap_base_addr+total_bytes;
end
//-------------------------------------------------------------------------
// BMG address generation
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
awaddr_reg <= 0;
num_of_bytes_r <= 0;
awburst_int <= 0;
end else begin
if (addr_en_c == 1'b1) begin
awaddr_reg <= #FLOP_DELAY S_AXI_AWADDR ;
num_of_bytes_r <= num_of_bytes_c;
awburst_int <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);
end else if (incr_addr_c == 1'b1) begin
if (awburst_int == 2'b10) begin
if(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin
awaddr_reg <= wrap_base_addr;
end else begin
awaddr_reg <= awaddr_reg + num_of_bytes_r;
end
end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin
awaddr_reg <= awaddr_reg + num_of_bytes_r;
end
end
end
end
assign S_AXI_AWADDR_OUT = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);
//-------------------------------------------------------------------------
// AXI wlast generation
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
awlen_cntr_r <= 0;
awlen_int <= 0;
end else begin
if (addr_en_c == 1'b1) begin
awlen_int <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;
awlen_cntr_r <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;
end else if (dec_alen_c == 1'b1) begin
awlen_cntr_r <= #FLOP_DELAY awlen_cntr_r - 1 ;
end
end
end
assign w_last_c = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;
assign dec_alen_c = (incr_addr_c | w_last_c);
//-------------------------------------------------------------------------
// Generation of bvalid counter for outstanding transactions
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_count_r <= 0;
end else begin
// bvalid_count_r generation
if (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r ;
end else if (bvalid_c == 1'b1) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r + 1 ;
end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r - 1 ;
end
end
end
//-------------------------------------------------------------------------
// Generation of bvalid when BID is used
//-------------------------------------------------------------------------
generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_r <= 0;
bvalid_d1_c <= 0;
end else begin
// Delay the generation o bvalid_r for generation for BID
bvalid_d1_c <= bvalid_c;
//external bvalid signal generation
if (bvalid_d1_c == 1'b1) begin
bvalid_r <= #FLOP_DELAY 1'b1 ;
end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin
bvalid_r <= #FLOP_DELAY 0 ;
end
end
end
end
endgenerate
//-------------------------------------------------------------------------
// Generation of bvalid when BID is not used
//-------------------------------------------------------------------------
generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_r <= 0;
end else begin
//external bvalid signal generation
if (bvalid_c == 1'b1) begin
bvalid_r <= #FLOP_DELAY 1'b1 ;
end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin
bvalid_r <= #FLOP_DELAY 0 ;
end
end
end
end
endgenerate
//-------------------------------------------------------------------------
// Generation of Bready timeout
//-------------------------------------------------------------------------
always @(bvalid_count_r) begin
// bready_timeout_c generation
if(bvalid_count_r == C_AXI_OS_WR-1) begin
bready_timeout_c <= 1'b1;
end else begin
bready_timeout_c <= 1'b0;
end
end
//-------------------------------------------------------------------------
// Generation of BID
//-------------------------------------------------------------------------
generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_wr_cnt_r <= 0;
bvalid_rd_cnt_r <= 0;
end else begin
// STORE AWID IN AN ARRAY
if(bvalid_c == 1'b1) begin
bvalid_wr_cnt_r <= bvalid_wr_cnt_r + 1;
end
// generate BID FROM AWID ARRAY
bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;
S_AXI_BID <= axi_bid_array[bvalid_rd_cnt_c];
end
end
assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;
//-------------------------------------------------------------------------
// Storing AWID for generation of BID
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if(S_ARESETN == 1'b1) begin
axi_bid_array[0] = 0;
axi_bid_array[1] = 0;
axi_bid_array[2] = 0;
axi_bid_array[3] = 0;
end else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin
axi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;
end
end
end
endgenerate
assign S_AXI_BVALID = bvalid_r;
assign S_AXI_AWREADY = aw_ready_r;
endmodule
module blk_mem_axi_read_wrapper_beh_v8_3
# (
//// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0,
parameter C_AXI_TYPE = 0,
parameter C_AXI_SLAVE_TYPE = 0,
parameter C_MEMORY_TYPE = 0,
parameter C_WRITE_WIDTH_A = 4,
parameter C_WRITE_DEPTH_A = 32,
parameter C_ADDRA_WIDTH = 12,
parameter C_AXI_PIPELINE_STAGES = 0,
parameter C_AXI_ARADDR_WIDTH = 12,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
parameter C_ADDRB_WIDTH = 12
)
(
//// AXI Global Signals
input S_ACLK,
input S_ARESETN,
//// AXI Full/Lite Slave Read (Read side)
input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,
input [7:0] S_AXI_ARLEN,
input [2:0] S_AXI_ARSIZE,
input [1:0] S_AXI_ARBURST,
input S_AXI_ARVALID,
output S_AXI_ARREADY,
output S_AXI_RLAST,
output S_AXI_RVALID,
input S_AXI_RREADY,
input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,
//// AXI Full/Lite Read Address Signals to BRAM
output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,
output S_AXI_RD_EN
);
localparam FLOP_DELAY = 100; // 100 ps
localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:
((C_WRITE_WIDTH_A==16)?1:
((C_WRITE_WIDTH_A==32)?2:
((C_WRITE_WIDTH_A==64)?3:
((C_WRITE_WIDTH_A==128)?4:
((C_WRITE_WIDTH_A==256)?5:0))))));
reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;
wire addr_en_c;
wire rd_en_c;
wire incr_addr_c;
wire single_trans_c;
wire dec_alen_c;
wire mux_sel_c;
wire r_last_c;
wire r_last_int_c;
wire [C_ADDRB_WIDTH-1 : 0] araddr_out;
reg [7:0] arlen_int_r=0;
reg [7:0] arlen_cntr=8'h01;
reg [1:0] arburst_int_c=0;
reg [1:0] arburst_int_r=0;
reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;
integer num_of_bytes_c = 0;
integer total_bytes = 0;
integer num_of_bytes_r = 0;
integer wrap_base_addr_r = 0;
integer wrap_boundary_r = 0;
reg [7:0] arlen_int_c=0;
integer total_bytes_c = 0;
integer wrap_base_addr_c = 0;
integer wrap_boundary_c = 0;
assign dec_alen_c = incr_addr_c | r_last_int_c;
read_netlist_v8_3
#(.C_AXI_TYPE (1),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH))
axi_read_fsm (
.S_AXI_INCR_ADDR(incr_addr_c),
.S_AXI_ADDR_EN(addr_en_c),
.S_AXI_SINGLE_TRANS(single_trans_c),
.S_AXI_MUX_SEL(mux_sel_c),
.S_AXI_R_LAST(r_last_c),
.S_AXI_R_LAST_INT(r_last_int_c),
//// AXI Global Signals
.S_ACLK(S_ACLK),
.S_ARESETN(S_ARESETN),
//// AXI Full/Lite Slave Read (Read side)
.S_AXI_ARLEN(S_AXI_ARLEN),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_RLAST(S_AXI_RLAST),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_RREADY(S_AXI_RREADY),
//// AXI Full/Lite Read Address Signals to BRAM
.S_AXI_RD_EN(rd_en_c)
);
always@(*) begin
num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);
total_bytes = (num_of_bytes_r)*(arlen_int_r+1);
wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);
wrap_boundary_r = wrap_base_addr_r+total_bytes;
//////// combinatorial from interface
arlen_int_c = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);
total_bytes_c = (num_of_bytes_c)*(arlen_int_c+1);
wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);
wrap_boundary_c = wrap_base_addr_c+total_bytes_c;
arburst_int_c = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1);
end
////-------------------------------------------------------------------------
//// BMG address generation
////-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
araddr_reg <= 0;
arburst_int_r <= 0;
num_of_bytes_r <= 0;
end else begin
if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin
arburst_int_r <= arburst_int_c;
num_of_bytes_r <= num_of_bytes_c;
if (arburst_int_c == 2'b10) begin
if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin
araddr_reg <= wrap_base_addr_c;
end else begin
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
end
end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
end
end else if (addr_en_c == 1'b1) begin
araddr_reg <= S_AXI_ARADDR;
num_of_bytes_r <= num_of_bytes_c;
arburst_int_r <= arburst_int_c;
end else if (incr_addr_c == 1'b1) begin
if (arburst_int_r == 2'b10) begin
if(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin
araddr_reg <= wrap_base_addr_r;
end else begin
araddr_reg <= araddr_reg + num_of_bytes_r;
end
end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin
araddr_reg <= araddr_reg + num_of_bytes_r;
end
end
end
end
assign araddr_out = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);
////-----------------------------------------------------------------------
//// Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM
////-----------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
arlen_cntr <= 8'h01;
arlen_int_r <= 0;
end else begin
if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin
arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
arlen_cntr <= S_AXI_ARLEN - 1'b1;
end else if (addr_en_c == 1'b1) begin
arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
arlen_cntr <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
end else if (dec_alen_c == 1'b1) begin
arlen_cntr <= arlen_cntr - 1'b1 ;
end
else begin
arlen_cntr <= arlen_cntr;
end
end
end
assign r_last_int_c = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;
////------------------------------------------------------------------------
//// AXI FULL FSM
//// Mux Selection of ARADDR
//// ARADDR is driven out from the read fsm based on the mux_sel_c
//// Based on mux_sel either ARADDR is given out or the latched ARADDR is
//// given out to BRAM
////------------------------------------------------------------------------
assign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;
////------------------------------------------------------------------------
//// Assign output signals - AXI FULL FSM
////------------------------------------------------------------------------
assign S_AXI_RD_EN = rd_en_c;
generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
S_AXI_RID <= 0;
ar_id_r <= 0;
end else begin
if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin
S_AXI_RID <= S_AXI_ARID;
ar_id_r <= S_AXI_ARID;
end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin
ar_id_r <= S_AXI_ARID;
end else if (rd_en_c == 1'b1) begin
S_AXI_RID <= ar_id_r;
end
end
end
end
endgenerate
endmodule
module blk_mem_axi_regs_fwd_v8_3
#(parameter C_DATA_WIDTH = 8
)(
input ACLK,
input ARESET,
input S_VALID,
output S_READY,
input [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
output M_VALID,
input M_READY,
output reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA
);
reg [C_DATA_WIDTH-1:0] STORAGE_DATA;
wire S_READY_I;
reg M_VALID_I;
reg [1:0] ARESET_D;
//assign local signal to its output signal
assign S_READY = S_READY_I;
assign M_VALID = M_VALID_I;
always @(posedge ACLK) begin
ARESET_D <= {ARESET_D[0], ARESET};
end
//Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK or ARESET) begin
if (ARESET == 1'b1) begin
STORAGE_DATA <= 0;
end else begin
if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin
STORAGE_DATA <= S_PAYLOAD_DATA;
end
end
end
always @(posedge ACLK) begin
M_PAYLOAD_DATA = STORAGE_DATA;
end
//M_Valid set to high when we have a completed transfer on slave side
//Is removed on a M_READY except if we have a new transfer on the slave side
always @(posedge ACLK or ARESET_D) begin
if (ARESET_D != 2'b00) begin
M_VALID_I <= 1'b0;
end else begin
if (S_VALID == 1'b1) begin
//Always set M_VALID_I when slave side is valid
M_VALID_I <= 1'b1;
end else if (M_READY == 1'b1 ) begin
//Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= 1'b0;
end
end
end
//Slave Ready is either when Master side drives M_READY or we have space in our storage data
assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));
endmodule
//*****************************************************************************
// Output Register Stage module
//
// This module builds the output register stages of the memory. This module is
// instantiated in the main memory module (blk_mem_gen_v8_3_5) which is
// declared/implemented further down in this file.
//*****************************************************************************
module blk_mem_gen_v8_3_5_output_stage
#(parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RST = 0,
parameter C_RSTRAM = 0,
parameter C_RST_PRIORITY = "CE",
parameter C_INIT_VAL = "0",
parameter C_HAS_EN = 0,
parameter C_HAS_REGCE = 0,
parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_MEM_OUTPUT_REGS = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter NUM_STAGES = 1,
parameter C_EN_ECC_PIPE = 0,
parameter FLOP_DELAY = 100
)
(
input CLK,
input RST,
input EN,
input REGCE,
input [C_DATA_WIDTH-1:0] DIN_I,
output reg [C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN_I,
input DBITERR_IN_I,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN_I,
input ECCPIPECE,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RST : Determines the presence of the RST port
// C_RSTRAM : Determines if special reset behavior is used
// C_RST_PRIORITY : Determines the priority between CE and SR
// C_INIT_VAL : Initialization value
// C_HAS_EN : Determines the presence of the EN port
// C_HAS_REGCE : Determines the presence of the REGCE port
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// NUM_STAGES : Determines the number of output stages
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// RST : Reset input to reset memory outputs to a user-defined
// reset state
// EN : Enable all read and write operations
// REGCE : Register Clock Enable to control each pipeline output
// register stages
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
// Fix for CR-509792
localparam REG_STAGES = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;
// Declare the pipeline registers
// (includes mem output reg, mux pipeline stages, and mux output reg)
reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;
reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;
reg [REG_STAGES-1:0] sbiterr_regs;
reg [REG_STAGES-1:0] dbiterr_regs;
reg [C_DATA_WIDTH*8-1:0] init_str = C_INIT_VAL;
reg [C_DATA_WIDTH-1:0] init_val ;
//*********************************************
// Wire off optional inputs based on parameters
//*********************************************
wire en_i;
wire regce_i;
wire rst_i;
// Internal signals
reg [C_DATA_WIDTH-1:0] DIN;
reg [C_ADDRB_WIDTH-1:0] RDADDRECC_IN;
reg SBITERR_IN;
reg DBITERR_IN;
// Internal enable for output registers is tied to user EN or '1' depending
// on parameters
assign en_i = (C_HAS_EN==0 || EN);
// Internal register enable for output registers is tied to user REGCE, EN or
// '1' depending on parameters
// For V4 ECC, REGCE is always 1
// Virtex-4 ECC Not Yet Supported
assign regce_i = ((C_HAS_REGCE==1) && REGCE) ||
((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));
//Internal SRR is tied to user RST or '0' depending on parameters
assign rst_i = (C_HAS_RST==1) && RST;
//****************************************************
// Power on: load up the output registers and latches
//****************************************************
initial begin
if (!($sscanf(init_str, "%h", init_val))) begin
init_val = 0;
end
DOUT = init_val;
RDADDRECC = 0;
SBITERR = 1'b0;
DBITERR = 1'b0;
DIN = {(C_DATA_WIDTH){1'b0}};
RDADDRECC_IN = 0;
SBITERR_IN = 0;
DBITERR_IN = 0;
// This will be one wider than need, but 0 is an error
out_regs = {(REG_STAGES+1){init_val}};
rdaddrecc_regs = 0;
sbiterr_regs = {(REG_STAGES+1){1'b0}};
dbiterr_regs = {(REG_STAGES+1){1'b0}};
end
//***********************************************
// NUM_STAGES = 0 (No output registers. RAM only)
//***********************************************
generate if (NUM_STAGES == 0) begin : zero_stages
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg
always @* begin
DIN = DIN_I;
SBITERR_IN = SBITERR_IN_I;
DBITERR_IN = DBITERR_IN_I;
RDADDRECC_IN = RDADDRECC_IN_I;
end
end
endgenerate
generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg
always @(posedge CLK) begin
if(ECCPIPECE == 1) begin
DIN <= #FLOP_DELAY DIN_I;
SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;
DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;
RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;
end
end
end
endgenerate
//***********************************************
// NUM_STAGES = 1
// (Mem Output Reg only or Mux Output Reg only)
//***********************************************
// Possible valid combinations:
// Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)
// +-----------------------------------------+
// | C_RSTRAM_* | Reset Behavior |
// +----------------+------------------------+
// | 0 | Normal Behavior |
// +----------------+------------------------+
// | 1 | Special Behavior |
// +----------------+------------------------+
//
// Normal = REGCE gates reset, as in the case of all families except S3ADSP.
// Special = EN gates reset, as in the case of S3ADSP.
generate if (NUM_STAGES == 1 &&
(C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != "spartan3adsp" && C_XDEVICEFAMILY != "aspartan3adsp" )) ||
C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))
begin : one_stages_norm
always @(posedge CLK) begin
if (C_RST_PRIORITY == "CE") begin //REGCE has priority
if (regce_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY DIN;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY SBITERR_IN;
DBITERR <= #FLOP_DELAY DBITERR_IN;
end //Output signal assignments
end else begin //RST has priority
if (rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY DIN;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY SBITERR_IN;
DBITERR <= #FLOP_DELAY DBITERR_IN;
end //Output signal assignments
end //end Priority conditions
end //end RST Type conditions
end //end one_stages_norm generate statement
endgenerate
// Special Reset Behavior for S3ADSP
generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY =="spartan3adsp" || C_XDEVICEFAMILY =="aspartan3adsp"))
begin : one_stage_splbhv
always @(posedge CLK) begin
if (en_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
end else if (regce_i && !rst_i) begin
DOUT <= #FLOP_DELAY DIN;
end //Output signal assignments
end //end CLK
end //end one_stage_splbhv generate statement
endgenerate
//************************************************************
// NUM_STAGES > 1
// Mem Output Reg + Mux Output Reg
// or
// Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg
// or
// Mux Pipeline Stages (>0) + Mux Output Reg
//*************************************************************
generate if (NUM_STAGES > 1) begin : multi_stage
//Asynchronous Reset
always @(posedge CLK) begin
if (C_RST_PRIORITY == "CE") begin //REGCE has priority
if (regce_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY
out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];
RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];
SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];
DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];
end //Output signal assignments
end else begin //RST has priority
if (rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY
out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];
RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];
SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];
DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];
end //Output signal assignments
end //end Priority conditions
// Shift the data through the output stages
if (en_i) begin
out_regs <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;
rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;
sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;
dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;
end
end //end CLK
end //end multi_stage generate statement
endgenerate
endmodule
module blk_mem_gen_v8_3_5_softecc_output_reg_stage
#(parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_USE_SOFTECC = 0,
parameter FLOP_DELAY = 100
)
(
input CLK,
input [C_DATA_WIDTH-1:0] DIN,
output reg [C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN,
input DBITERR_IN,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_SOFTECC_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
reg [C_DATA_WIDTH-1:0] dout_i = 0;
reg sbiterr_i = 0;
reg dbiterr_i = 0;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_i = 0;
//***********************************************
// NO OUTPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
//***********************************************
// WITH OUTPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage
always @(posedge CLK) begin
dout_i <= #FLOP_DELAY DIN;
rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;
sbiterr_i <= #FLOP_DELAY SBITERR_IN;
dbiterr_i <= #FLOP_DELAY DBITERR_IN;
end
always @* begin
DOUT = dout_i;
RDADDRECC = rdaddrecc_i;
SBITERR = sbiterr_i;
DBITERR = dbiterr_i;
end //end always
end //end in_or_out_stage generate statement
endgenerate
endmodule
//*****************************************************************************
// Main Memory module
//
// This module is the top-level behavioral model and this implements the RAM
//*****************************************************************************
module blk_mem_gen_v8_3_5_mem_module
#(parameter C_CORENAME = "blk_mem_gen_v8_3_5",
parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_MEM_TYPE = 2,
parameter C_BYTE_SIZE = 9,
parameter C_USE_BRAM_BLOCK = 0,
parameter C_ALGORITHM = 1,
parameter C_PRIM_TYPE = 3,
parameter C_LOAD_INIT_FILE = 0,
parameter C_INIT_FILE_NAME = "",
parameter C_INIT_FILE = "",
parameter C_USE_DEFAULT_DATA = 0,
parameter C_DEFAULT_DATA = "0",
parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RSTA = 0,
parameter C_RST_PRIORITY_A = "CE",
parameter C_RSTRAM_A = 0,
parameter C_INITA_VAL = "0",
parameter C_HAS_ENA = 1,
parameter C_HAS_REGCEA = 0,
parameter C_USE_BYTE_WEA = 0,
parameter C_WEA_WIDTH = 1,
parameter C_WRITE_MODE_A = "WRITE_FIRST",
parameter C_WRITE_WIDTH_A = 32,
parameter C_READ_WIDTH_A = 32,
parameter C_WRITE_DEPTH_A = 64,
parameter C_READ_DEPTH_A = 64,
parameter C_ADDRA_WIDTH = 5,
parameter C_HAS_RSTB = 0,
parameter C_RST_PRIORITY_B = "CE",
parameter C_RSTRAM_B = 0,
parameter C_INITB_VAL = "",
parameter C_HAS_ENB = 1,
parameter C_HAS_REGCEB = 0,
parameter C_USE_BYTE_WEB = 0,
parameter C_WEB_WIDTH = 1,
parameter C_WRITE_MODE_B = "WRITE_FIRST",
parameter C_WRITE_WIDTH_B = 32,
parameter C_READ_WIDTH_B = 32,
parameter C_WRITE_DEPTH_B = 64,
parameter C_READ_DEPTH_B = 64,
parameter C_ADDRB_WIDTH = 5,
parameter C_HAS_MEM_OUTPUT_REGS_A = 0,
parameter C_HAS_MEM_OUTPUT_REGS_B = 0,
parameter C_HAS_MUX_OUTPUT_REGS_A = 0,
parameter C_HAS_MUX_OUTPUT_REGS_B = 0,
parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_MUX_PIPELINE_STAGES = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter C_HAS_INJECTERR = 0,
parameter C_SIM_COLLISION_CHECK = "NONE",
parameter C_COMMON_CLK = 1,
parameter FLOP_DELAY = 100,
parameter C_DISABLE_WARN_BHV_COLL = 0,
parameter C_EN_ECC_PIPE = 0,
parameter C_DISABLE_WARN_BHV_RANGE = 0
)
(input CLKA,
input RSTA,
input ENA,
input REGCEA,
input [C_WEA_WIDTH-1:0] WEA,
input [C_ADDRA_WIDTH-1:0] ADDRA,
input [C_WRITE_WIDTH_A-1:0] DINA,
output [C_READ_WIDTH_A-1:0] DOUTA,
input CLKB,
input RSTB,
input ENB,
input REGCEB,
input [C_WEB_WIDTH-1:0] WEB,
input [C_ADDRB_WIDTH-1:0] ADDRB,
input [C_WRITE_WIDTH_B-1:0] DINB,
output [C_READ_WIDTH_B-1:0] DOUTB,
input INJECTSBITERR,
input INJECTDBITERR,
input ECCPIPECE,
input SLEEP,
output SBITERR,
output DBITERR,
output [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_CORENAME : Instance name of the Block Memory Generator core
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_MEM_TYPE : Designates memory type.
// It can be
// 0 - Single Port Memory
// 1 - Simple Dual Port Memory
// 2 - True Dual Port Memory
// 3 - Single Port Read Only Memory
// 4 - Dual Port Read Only Memory
// C_BYTE_SIZE : Size of a byte (8 or 9 bits)
// C_ALGORITHM : Designates the algorithm method used
// for constructing the memory.
// It can be Fixed_Primitives, Minimum_Area or
// Low_Power
// C_PRIM_TYPE : Designates the user selected primitive used to
// construct the memory.
//
// C_LOAD_INIT_FILE : Designates the use of an initialization file to
// initialize memory contents.
// C_INIT_FILE_NAME : Memory initialization file name.
// C_USE_DEFAULT_DATA : Designates whether to fill remaining
// initialization space with default data
// C_DEFAULT_DATA : Default value of all memory locations
// not initialized by the memory
// initialization file.
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RSTA : Determines the presence of the RSTA port
// C_RST_PRIORITY_A : Determines the priority between CE and SR for
// Port A.
// C_RSTRAM_A : Determines if special reset behavior is used for
// Port A
// C_INITA_VAL : The initialization value for Port A
// C_HAS_ENA : Determines the presence of the ENA port
// C_HAS_REGCEA : Determines the presence of the REGCEA port
// C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
// C_WEA_WIDTH : The width of the WEA port
// C_WRITE_MODE_A : Configurable write mode for Port A. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_A : Memory write width for Port A.
// C_READ_WIDTH_A : Memory read width for Port A.
// C_WRITE_DEPTH_A : Memory write depth for Port A.
// C_READ_DEPTH_A : Memory read depth for Port A.
// C_ADDRA_WIDTH : Width of the ADDRA input port
// C_HAS_RSTB : Determines the presence of the RSTB port
// C_RST_PRIORITY_B : Determines the priority between CE and SR for
// Port B.
// C_RSTRAM_B : Determines if special reset behavior is used for
// Port B
// C_INITB_VAL : The initialization value for Port B
// C_HAS_ENB : Determines the presence of the ENB port
// C_HAS_REGCEB : Determines the presence of the REGCEB port
// C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
// C_WEB_WIDTH : The width of the WEB port
// C_WRITE_MODE_B : Configurable write mode for Port B. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_B : Memory write width for Port B.
// C_READ_WIDTH_B : Memory read width for Port B.
// C_WRITE_DEPTH_B : Memory write depth for Port B.
// C_READ_DEPTH_B : Memory read depth for Port B.
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
// of the RAM primitive for Port A.
// C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive for Port B.
// C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
// of the MUX for Port A.
// C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
// of the MUX for Port B.
// C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
// between the muxes.
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// C_HAS_INJECTERR : Determines if the error injection pins
// are present or not. If the ECC feature
// is not used, this value is defaulted to
// 0, else the following are the allowed
// values:
// 0 : No INJECTSBITERR or INJECTDBITERR pins
// 1 : Only INJECTSBITERR pin exists
// 2 : Only INJECTDBITERR pin exists
// 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
// C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
// warnings. It can be "ALL", "NONE",
// "Warnings_Only" or "Generate_X_Only".
// C_COMMON_CLK : Determins if the core has a single CLK input.
// C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
// C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
// warnings
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLKA : Clock to synchronize all read and write operations of Port A.
// RSTA : Reset input to reset memory outputs to a user-defined
// reset state for Port A.
// ENA : Enable all read and write operations of Port A.
// REGCEA : Register Clock Enable to control each pipeline output
// register stages for Port A.
// WEA : Write Enable to enable all write operations of Port A.
// ADDRA : Address of Port A.
// DINA : Data input of Port A.
// DOUTA : Data output of Port A.
// CLKB : Clock to synchronize all read and write operations of Port B.
// RSTB : Reset input to reset memory outputs to a user-defined
// reset state for Port B.
// ENB : Enable all read and write operations of Port B.
// REGCEB : Register Clock Enable to control each pipeline output
// register stages for Port B.
// WEB : Write Enable to enable all write operations of Port B.
// ADDRB : Address of Port B.
// DINB : Data input of Port B.
// DOUTB : Data output of Port B.
// INJECTSBITERR : Single Bit ECC Error Injection Pin.
// INJECTDBITERR : Double Bit ECC Error Injection Pin.
// SBITERR : Output signal indicating that a Single Bit ECC Error has been
// detected and corrected.
// DBITERR : Output signal indicating that a Double Bit ECC Error has been
// detected.
// RDADDRECC : Read Address Output signal indicating address at which an
// ECC error has occurred.
//////////////////////////////////////////////////////////////////////////
// Note: C_CORENAME parameter is hard-coded to "blk_mem_gen_v8_3_5" and it is
// only used by this module to print warning messages. It is neither passed
// down from blk_mem_gen_v8_3_5_xst.v nor present in the instantiation template
// coregen generates
//***************************************************************************
// constants for the core behavior
//***************************************************************************
// file handles for logging
//--------------------------------------------------
localparam ADDRFILE = 32'h8000_0001; //stdout for addr out of range
localparam COLLFILE = 32'h8000_0001; //stdout for coll detection
localparam ERRFILE = 32'h8000_0001; //stdout for file I/O errors
// other constants
//--------------------------------------------------
localparam COLL_DELAY = 100; // 100 ps
// locally derived parameters to determine memory shape
//-----------------------------------------------------
localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0)))));
localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?
C_WRITE_WIDTH_A : C_READ_WIDTH_A;
localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?
C_WRITE_WIDTH_B : C_READ_WIDTH_B;
localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?
MIN_WIDTH_A : MIN_WIDTH_B;
localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?
C_WRITE_DEPTH_A : C_READ_DEPTH_A;
localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?
C_WRITE_DEPTH_B : C_READ_DEPTH_B;
localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?
MAX_DEPTH_A : MAX_DEPTH_B;
// locally derived parameters to assist memory access
//----------------------------------------------------
// Calculate the width ratios of each port with respect to the narrowest
// port
localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;
localparam READ_WIDTH_RATIO_A = C_READ_WIDTH_A/MIN_WIDTH;
localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;
localparam READ_WIDTH_RATIO_B = C_READ_WIDTH_B/MIN_WIDTH;
// To modify the LSBs of the 'wider' data to the actual
// address value
//----------------------------------------------------
localparam WRITE_ADDR_A_DIV = C_WRITE_WIDTH_A/MIN_WIDTH_A;
localparam READ_ADDR_A_DIV = C_READ_WIDTH_A/MIN_WIDTH_A;
localparam WRITE_ADDR_B_DIV = C_WRITE_WIDTH_B/MIN_WIDTH_B;
localparam READ_ADDR_B_DIV = C_READ_WIDTH_B/MIN_WIDTH_B;
// If byte writes aren't being used, make sure BYTE_SIZE is not
// wider than the memory elements to avoid compilation warnings
localparam BYTE_SIZE = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;
// The memory
reg [MIN_WIDTH-1:0] memory [0:MAX_DEPTH-1];
reg [MIN_WIDTH-1:0] temp_mem_array [0:MAX_DEPTH-1];
reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;
// ECC error arrays
reg sbiterr_arr [0:MAX_DEPTH-1];
reg dbiterr_arr [0:MAX_DEPTH-1];
reg softecc_sbiterr_arr [0:MAX_DEPTH-1];
reg softecc_dbiterr_arr [0:MAX_DEPTH-1];
// Memory output 'latches'
reg [C_READ_WIDTH_A-1:0] memory_out_a;
reg [C_READ_WIDTH_B-1:0] memory_out_b;
// ECC error inputs and outputs from output_stage module:
reg sbiterr_in;
wire sbiterr_sdp;
reg dbiterr_in;
wire dbiterr_sdp;
wire [C_READ_WIDTH_B-1:0] dout_i;
wire dbiterr_i;
wire sbiterr_i;
wire [C_ADDRB_WIDTH-1:0] rdaddrecc_i;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_in;
wire [C_ADDRB_WIDTH-1:0] rdaddrecc_sdp;
// Reset values
reg [C_READ_WIDTH_A-1:0] inita_val;
reg [C_READ_WIDTH_B-1:0] initb_val;
// Collision detect
reg is_collision;
reg is_collision_a, is_collision_delay_a;
reg is_collision_b, is_collision_delay_b;
// Temporary variables for initialization
//---------------------------------------
integer status;
integer initfile;
integer meminitfile;
// data input buffer
reg [C_WRITE_WIDTH_A-1:0] mif_data;
reg [C_WRITE_WIDTH_A-1:0] mem_data;
// string values in hex
reg [C_READ_WIDTH_A*8-1:0] inita_str = C_INITA_VAL;
reg [C_READ_WIDTH_B*8-1:0] initb_str = C_INITB_VAL;
reg [C_WRITE_WIDTH_A*8-1:0] default_data_str = C_DEFAULT_DATA;
// initialization filename
reg [1023*8-1:0] init_file_str = C_INIT_FILE_NAME;
reg [1023*8-1:0] mem_init_file_str = C_INIT_FILE;
//Constants used to calculate the effective address widths for each of the
//four ports.
integer cnt = 1;
integer write_addr_a_width, read_addr_a_width;
integer write_addr_b_width, read_addr_b_width;
localparam C_FAMILY_LOCALPARAM = (C_FAMILY=="zynquplus"?"virtex7":(C_FAMILY=="kintexuplus"?"virtex7":(C_FAMILY=="virtexuplus"?"virtex7":(C_FAMILY=="virtexu"?"virtex7":(C_FAMILY=="kintexu" ? "virtex7":(C_FAMILY=="virtex7" ? "virtex7" : (C_FAMILY=="virtex7l" ? "virtex7" : (C_FAMILY=="qvirtex7" ? "virtex7" : (C_FAMILY=="qvirtex7l" ? "virtex7" : (C_FAMILY=="kintex7" ? "virtex7" : (C_FAMILY=="kintex7l" ? "virtex7" : (C_FAMILY=="qkintex7" ? "virtex7" : (C_FAMILY=="qkintex7l" ? "virtex7" : (C_FAMILY=="artix7" ? "virtex7" : (C_FAMILY=="artix7l" ? "virtex7" : (C_FAMILY=="qartix7" ? "virtex7" : (C_FAMILY=="qartix7l" ? "virtex7" : (C_FAMILY=="aartix7" ? "virtex7" : (C_FAMILY=="zynq" ? "virtex7" : (C_FAMILY=="azynq" ? "virtex7" : (C_FAMILY=="qzynq" ? "virtex7" : C_FAMILY)))))))))))))))))))));
// Internal configuration parameters
//---------------------------------------------
localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);
localparam IS_ROM = (C_MEM_TYPE==3 || C_MEM_TYPE==4);
localparam HAS_A_WRITE = (!IS_ROM);
localparam HAS_B_WRITE = (C_MEM_TYPE==2);
localparam HAS_A_READ = (C_MEM_TYPE!=1);
localparam HAS_B_READ = (!SINGLE_PORT);
localparam HAS_B_PORT = (HAS_B_READ || HAS_B_WRITE);
// Calculate the mux pipeline register stages for Port A and Port B
//------------------------------------------------------------------
localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?
C_MUX_PIPELINE_STAGES : 0;
localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?
C_MUX_PIPELINE_STAGES : 0;
// Calculate total number of register stages in the core
// -----------------------------------------------------
localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);
localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);
wire ena_i;
wire enb_i;
wire reseta_i;
wire resetb_i;
wire [C_WEA_WIDTH-1:0] wea_i;
wire [C_WEB_WIDTH-1:0] web_i;
wire rea_i;
wire reb_i;
wire rsta_outp_stage;
wire rstb_outp_stage;
// ECC SBITERR/DBITERR Outputs
// The ECC Behavior is modeled by the behavioral models only for Virtex-6.
// For Virtex-5, these outputs will be tied to 0.
assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;
assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;
assign RDADDRECC = (((C_FAMILY_LOCALPARAM == "virtex7") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;
// This effectively wires off optional inputs
assign ena_i = (C_HAS_ENA==0) || ENA;
assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;
// To match RTL : In RTL, write enable of the primitive is tied to all 1's and
// the enable of the primitive is ANDing of wea(0) and ena. so eventually, the
// write operation depends on both enable and write enable. So, the below code
// which is actually doing the write operation only on enable ignoring the wea
// is removed to be in consistent with RTL.
// To Fix CR855535 (The fix to this CR is reverted to match RTL)
//assign wea_i = (HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 1 && ENA == 1) ? 'b1 :(HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 0) ? WEA : (HAS_A_WRITE && ena_i && C_USE_ECC == 0) ? WEA : 'b0;
assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0;
assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0;
assign rea_i = (HAS_A_READ) ? ena_i : 'b0;
assign reb_i = (HAS_B_READ) ? enb_i : 'b0;
// These signals reset the memory latches
assign reseta_i =
((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||
(C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));
assign resetb_i =
((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||
(C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));
// Tasks to access the memory
//---------------------------
//**************
// write_a
//**************
task write_a
(input reg [C_ADDRA_WIDTH-1:0] addr,
input reg [C_WEA_WIDTH-1:0] byte_en,
input reg [C_WRITE_WIDTH_A-1:0] data,
input inj_sbiterr,
input inj_dbiterr);
reg [C_WRITE_WIDTH_A-1:0] current_contents;
reg [C_ADDRA_WIDTH-1:0] address;
integer i;
begin
// Shift the address by the ratio
address = (addr/WRITE_ADDR_A_DIV);
if (address >= C_WRITE_DEPTH_A) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for A Write",
C_CORENAME, addr);
end
// valid address
end else begin
// Combine w/ byte writes
if (C_USE_BYTE_WEA) begin
// Get the current memory contents
if (WRITE_WIDTH_RATIO_A == 1) begin
// Workaround for IUS 5.5 part-select issue
current_contents = memory[address];
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin
current_contents[MIN_WIDTH*i+:MIN_WIDTH]
= memory[address*WRITE_WIDTH_RATIO_A + i];
end
end
// Apply incoming bytes
if (C_WEA_WIDTH == 1) begin
// Workaround for IUS 5.5 part-select issue
if (byte_en[0]) begin
current_contents = data;
end
end else begin
for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin
if (byte_en[i]) begin
current_contents[BYTE_SIZE*i+:BYTE_SIZE]
= data[BYTE_SIZE*i+:BYTE_SIZE];
end
end
end
// No byte-writes, overwrite the whole word
end else begin
current_contents = data;
end
// Insert double bit errors:
if (C_USE_ECC == 1) begin
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
// Modified for Implementing CR_859399
current_contents[0] = !(current_contents[30]);
current_contents[1] = !(current_contents[62]);
/*current_contents[0] = !(current_contents[0]);
current_contents[1] = !(current_contents[1]);*/
end
end
// Insert softecc double bit errors:
if (C_USE_SOFTECC == 1) begin
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];
doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];
doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];
current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];
end
end
// Write data to memory
if (WRITE_WIDTH_RATIO_A == 1) begin
// Workaround for IUS 5.5 part-select issue
memory[address*WRITE_WIDTH_RATIO_A] = current_contents;
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin
memory[address*WRITE_WIDTH_RATIO_A + i]
= current_contents[MIN_WIDTH*i+:MIN_WIDTH];
end
end
// Store the address at which error is injected:
if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin
if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) ||
(C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))
begin
sbiterr_arr[addr] = 1;
end else begin
sbiterr_arr[addr] = 0;
end
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
dbiterr_arr[addr] = 1;
end else begin
dbiterr_arr[addr] = 0;
end
end
// Store the address at which softecc error is injected:
if (C_USE_SOFTECC == 1) begin
if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) ||
(C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))
begin
softecc_sbiterr_arr[addr] = 1;
end else begin
softecc_sbiterr_arr[addr] = 0;
end
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
softecc_dbiterr_arr[addr] = 1;
end else begin
softecc_dbiterr_arr[addr] = 0;
end
end
end
end
endtask
//**************
// write_b
//**************
task write_b
(input reg [C_ADDRB_WIDTH-1:0] addr,
input reg [C_WEB_WIDTH-1:0] byte_en,
input reg [C_WRITE_WIDTH_B-1:0] data);
reg [C_WRITE_WIDTH_B-1:0] current_contents;
reg [C_ADDRB_WIDTH-1:0] address;
integer i;
begin
// Shift the address by the ratio
address = (addr/WRITE_ADDR_B_DIV);
if (address >= C_WRITE_DEPTH_B) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for B Write",
C_CORENAME, addr);
end
// valid address
end else begin
// Combine w/ byte writes
if (C_USE_BYTE_WEB) begin
// Get the current memory contents
if (WRITE_WIDTH_RATIO_B == 1) begin
// Workaround for IUS 5.5 part-select issue
current_contents = memory[address];
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin
current_contents[MIN_WIDTH*i+:MIN_WIDTH]
= memory[address*WRITE_WIDTH_RATIO_B + i];
end
end
// Apply incoming bytes
if (C_WEB_WIDTH == 1) begin
// Workaround for IUS 5.5 part-select issue
if (byte_en[0]) begin
current_contents = data;
end
end else begin
for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin
if (byte_en[i]) begin
current_contents[BYTE_SIZE*i+:BYTE_SIZE]
= data[BYTE_SIZE*i+:BYTE_SIZE];
end
end
end
// No byte-writes, overwrite the whole word
end else begin
current_contents = data;
end
// Write data to memory
if (WRITE_WIDTH_RATIO_B == 1) begin
// Workaround for IUS 5.5 part-select issue
memory[address*WRITE_WIDTH_RATIO_B] = current_contents;
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin
memory[address*WRITE_WIDTH_RATIO_B + i]
= current_contents[MIN_WIDTH*i+:MIN_WIDTH];
end
end
end
end
endtask
//**************
// read_a
//**************
task read_a
(input reg [C_ADDRA_WIDTH-1:0] addr,
input reg reset);
reg [C_ADDRA_WIDTH-1:0] address;
integer i;
begin
if (reset) begin
memory_out_a <= #FLOP_DELAY inita_val;
end else begin
// Shift the address by the ratio
address = (addr/READ_ADDR_A_DIV);
if (address >= C_READ_DEPTH_A) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for A Read",
C_CORENAME, addr);
end
memory_out_a <= #FLOP_DELAY 'bX;
// valid address
end else begin
if (READ_WIDTH_RATIO_A==1) begin
memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];
end else begin
// Increment through the 'partial' words in the memory
for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin
memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]
<= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];
end
end //end READ_WIDTH_RATIO_A==1 loop
end //end valid address loop
end //end reset-data assignment loops
end
endtask
//**************
// read_b
//**************
task read_b
(input reg [C_ADDRB_WIDTH-1:0] addr,
input reg reset);
reg [C_ADDRB_WIDTH-1:0] address;
integer i;
begin
if (reset) begin
memory_out_b <= #FLOP_DELAY initb_val;
sbiterr_in <= #FLOP_DELAY 1'b0;
dbiterr_in <= #FLOP_DELAY 1'b0;
rdaddrecc_in <= #FLOP_DELAY 0;
end else begin
// Shift the address
address = (addr/READ_ADDR_B_DIV);
if (address >= C_READ_DEPTH_B) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for B Read",
C_CORENAME, addr);
end
memory_out_b <= #FLOP_DELAY 'bX;
sbiterr_in <= #FLOP_DELAY 1'bX;
dbiterr_in <= #FLOP_DELAY 1'bX;
rdaddrecc_in <= #FLOP_DELAY 'bX;
// valid address
end else begin
if (READ_WIDTH_RATIO_B==1) begin
memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];
end else begin
// Increment through the 'partial' words in the memory
for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin
memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]
<= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];
end
end
if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin
rdaddrecc_in <= #FLOP_DELAY addr;
if (sbiterr_arr[addr] == 1) begin
sbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
sbiterr_in <= #FLOP_DELAY 1'b0;
end
if (dbiterr_arr[addr] == 1) begin
dbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
dbiterr_in <= #FLOP_DELAY 1'b0;
end
end else if (C_USE_SOFTECC == 1) begin
rdaddrecc_in <= #FLOP_DELAY addr;
if (softecc_sbiterr_arr[addr] == 1) begin
sbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
sbiterr_in <= #FLOP_DELAY 1'b0;
end
if (softecc_dbiterr_arr[addr] == 1) begin
dbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
dbiterr_in <= #FLOP_DELAY 1'b0;
end
end else begin
rdaddrecc_in <= #FLOP_DELAY 0;
dbiterr_in <= #FLOP_DELAY 1'b0;
sbiterr_in <= #FLOP_DELAY 1'b0;
end //end SOFTECC Loop
end //end Valid address loop
end //end reset-data assignment loops
end
endtask
//**************
// reset_a
//**************
task reset_a (input reg reset);
begin
if (reset) memory_out_a <= #FLOP_DELAY inita_val;
end
endtask
//**************
// reset_b
//**************
task reset_b (input reg reset);
begin
if (reset) memory_out_b <= #FLOP_DELAY initb_val;
end
endtask
//**************
// init_memory
//**************
task init_memory;
integer i, j, addr_step;
integer status;
reg [C_WRITE_WIDTH_A-1:0] default_data;
begin
default_data = 0;
//Display output message indicating that the behavioral model is being
//initialized
if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(" Block Memory Generator module loading initial data...");
// Convert the default to hex
if (C_USE_DEFAULT_DATA) begin
if (default_data_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_DEFAULT_DATA is empty!", C_CORENAME);
$finish;
end else begin
status = $sscanf(default_data_str, "%h", default_data);
if (status == 0) begin
$fdisplay(ERRFILE, {"%0s ERROR: Unsuccessful hexadecimal read",
"from C_DEFAULT_DATA: %0s"},
C_CORENAME, C_DEFAULT_DATA);
$finish;
end
end
end
// Step by WRITE_ADDR_A_DIV through the memory via the
// Port A write interface to hit every location once
addr_step = WRITE_ADDR_A_DIV;
// 'write' to every location with default (or 0)
for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin
write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0);
end
// Get specialized data from the MIF file
if (C_LOAD_INIT_FILE) begin
if (init_file_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE_NAME is empty!",
C_CORENAME);
$finish;
end else begin
initfile = $fopen(init_file_str, "r");
if (initfile == 0) begin
$fdisplay(ERRFILE, {"%0s, ERROR: Problem opening",
"C_INIT_FILE_NAME: %0s!"},
C_CORENAME, init_file_str);
$finish;
end else begin
// loop through the mif file, loading in the data
for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin
status = $fscanf(initfile, "%b", mif_data);
if (status > 0) begin
write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0);
end
end
$fclose(initfile);
end //initfile
end //init_file_str
end //C_LOAD_INIT_FILE
if (C_USE_BRAM_BLOCK) begin
// Get specialized data from the MIF file
if (C_INIT_FILE != "NONE") begin
if (mem_init_file_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE is empty!",
C_CORENAME);
$finish;
end else begin
meminitfile = $fopen(mem_init_file_str, "r");
if (meminitfile == 0) begin
$fdisplay(ERRFILE, {"%0s, ERROR: Problem opening",
"C_INIT_FILE: %0s!"},
C_CORENAME, mem_init_file_str);
$finish;
end else begin
// loop through the mif file, loading in the data
$readmemh(mem_init_file_str, memory );
for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin
end
$fclose(meminitfile);
end //meminitfile
end //mem_init_file_str
end //C_INIT_FILE
end //C_USE_BRAM_BLOCK
//Display output message indicating that the behavioral model is done
//initializing
if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE)
$display(" Block Memory Generator data initialization complete.");
end
endtask
//**************
// log2roundup
//**************
function integer log2roundup (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
if (data_value > 1) begin
for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin
width = width + 1;
end //loop
end //if
log2roundup = width;
end //log2roundup
endfunction
//*******************
// collision_check
//*******************
function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,
input integer iswrite_a,
input reg [C_ADDRB_WIDTH-1:0] addr_b,
input integer iswrite_b);
reg c_aw_bw, c_aw_br, c_ar_bw;
integer scaled_addra_to_waddrb_width;
integer scaled_addrb_to_waddrb_width;
integer scaled_addra_to_waddra_width;
integer scaled_addrb_to_waddra_width;
integer scaled_addra_to_raddrb_width;
integer scaled_addrb_to_raddrb_width;
integer scaled_addra_to_raddra_width;
integer scaled_addrb_to_raddra_width;
begin
c_aw_bw = 0;
c_aw_br = 0;
c_ar_bw = 0;
//If write_addr_b_width is smaller, scale both addresses to that width for
//comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to write_addr_b_width. Once both are scaled to
//write_addr_b_width, compare.
scaled_addra_to_waddrb_width = ((addr_a)/
2**(C_ADDRA_WIDTH-write_addr_b_width));
scaled_addrb_to_waddrb_width = ((addr_b)/
2**(C_ADDRB_WIDTH-write_addr_b_width));
//If write_addr_a_width is smaller, scale both addresses to that width for
//comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to write_addr_a_width. Once both are scaled to
//write_addr_a_width, compare.
scaled_addra_to_waddra_width = ((addr_a)/
2**(C_ADDRA_WIDTH-write_addr_a_width));
scaled_addrb_to_waddra_width = ((addr_b)/
2**(C_ADDRB_WIDTH-write_addr_a_width));
//If read_addr_b_width is smaller, scale both addresses to that width for
//comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to read_addr_b_width. Once both are scaled to
//read_addr_b_width, compare.
scaled_addra_to_raddrb_width = ((addr_a)/
2**(C_ADDRA_WIDTH-read_addr_b_width));
scaled_addrb_to_raddrb_width = ((addr_b)/
2**(C_ADDRB_WIDTH-read_addr_b_width));
//If read_addr_a_width is smaller, scale both addresses to that width for
//comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to read_addr_a_width. Once both are scaled to
//read_addr_a_width, compare.
scaled_addra_to_raddra_width = ((addr_a)/
2**(C_ADDRA_WIDTH-read_addr_a_width));
scaled_addrb_to_raddra_width = ((addr_b)/
2**(C_ADDRB_WIDTH-read_addr_a_width));
//Look for a write-write collision. In order for a write-write
//collision to exist, both ports must have a write transaction.
if (iswrite_a && iswrite_b) begin
if (write_addr_a_width > write_addr_b_width) begin
if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin
c_aw_bw = 1;
end else begin
c_aw_bw = 0;
end
end else begin
if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin
c_aw_bw = 1;
end else begin
c_aw_bw = 0;
end
end //width
end //iswrite_a and iswrite_b
//If the B port is reading (which means it is enabled - so could be
//a TX_WRITE or TX_READ), then check for a write-read collision).
//This could happen whether or not a write-write collision exists due
//to asymmetric write/read ports.
if (iswrite_a) begin
if (write_addr_a_width > read_addr_b_width) begin
if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin
c_aw_br = 1;
end else begin
c_aw_br = 0;
end
end else begin
if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin
c_aw_br = 1;
end else begin
c_aw_br = 0;
end
end //width
end //iswrite_a
//If the A port is reading (which means it is enabled - so could be
// a TX_WRITE or TX_READ), then check for a write-read collision).
//This could happen whether or not a write-write collision exists due
// to asymmetric write/read ports.
if (iswrite_b) begin
if (read_addr_a_width > write_addr_b_width) begin
if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin
c_ar_bw = 1;
end else begin
c_ar_bw = 0;
end
end else begin
if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin
c_ar_bw = 1;
end else begin
c_ar_bw = 0;
end
end //width
end //iswrite_b
collision_check = c_aw_bw | c_aw_br | c_ar_bw;
end
endfunction
//*******************************
// power on values
//*******************************
initial begin
// Load up the memory
init_memory;
// Load up the output registers and latches
if ($sscanf(inita_str, "%h", inita_val)) begin
memory_out_a = inita_val;
end else begin
memory_out_a = 0;
end
if ($sscanf(initb_str, "%h", initb_val)) begin
memory_out_b = initb_val;
end else begin
memory_out_b = 0;
end
sbiterr_in = 1'b0;
dbiterr_in = 1'b0;
rdaddrecc_in = 0;
// Determine the effective address widths for each of the 4 ports
write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);
read_addr_a_width = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);
write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);
read_addr_b_width = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);
$display("Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.");
end
//***************************************************************************
// These are the main blocks which schedule read and write operations
// Note that the reset priority feature at the latch stage is only supported
// for Spartan-6. For other families, the default priority at the latch stage
// is "CE"
//***************************************************************************
// Synchronous clocks: schedule port operations with respect to
// both write operating modes
generate
if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_wf_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_rf_wf
always @(posedge CLKA) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_wf_rf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_rf_rf
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="WRITE_FIRST") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_wf_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="READ_FIRST") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_rf_nc
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_nc_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_nc_rf
always @(posedge CLKA) begin
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_nc_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
end
end
else if(C_COMMON_CLK) begin: com_clk_sched_default
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
endgenerate
// Asynchronous clocks: port operation is independent
generate
if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "WRITE_FIRST")) begin : async_clk_sched_clka_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
end
end
else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "READ_FIRST")) begin : async_clk_sched_clka_rf
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
end
end
else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "NO_CHANGE")) begin : async_clk_sched_clka_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
end
end
endgenerate
generate
if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "WRITE_FIRST")) begin: async_clk_sched_clkb_wf
always @(posedge CLKB) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "READ_FIRST")) begin: async_clk_sched_clkb_rf
always @(posedge CLKB) begin
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "NO_CHANGE")) begin: async_clk_sched_clkb_nc
always @(posedge CLKB) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
end
end
endgenerate
//***************************************************************
// Instantiate the variable depth output register stage module
//***************************************************************
// Port A
assign rsta_outp_stage = RSTA & (~SLEEP);
blk_mem_gen_v8_3_5_output_stage
#(.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_RST_TYPE ("SYNC"),
.C_HAS_RST (C_HAS_RSTA),
.C_RSTRAM (C_RSTRAM_A),
.C_RST_PRIORITY (C_RST_PRIORITY_A),
.C_INIT_VAL (C_INITA_VAL),
.C_HAS_EN (C_HAS_ENA),
.C_HAS_REGCE (C_HAS_REGCEA),
.C_DATA_WIDTH (C_READ_WIDTH_A),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_A),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.NUM_STAGES (NUM_OUTPUT_STAGES_A),
.C_EN_ECC_PIPE (0),
.FLOP_DELAY (FLOP_DELAY))
reg_a
(.CLK (CLKA),
.RST (rsta_outp_stage),//(RSTA),
.EN (ENA),
.REGCE (REGCEA),
.DIN_I (memory_out_a),
.DOUT (DOUTA),
.SBITERR_IN_I (1'b0),
.DBITERR_IN_I (1'b0),
.SBITERR (),
.DBITERR (),
.RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}),
.ECCPIPECE (1'b0),
.RDADDRECC ()
);
assign rstb_outp_stage = RSTB & (~SLEEP);
// Port B
blk_mem_gen_v8_3_5_output_stage
#(.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_RST_TYPE ("SYNC"),
.C_HAS_RST (C_HAS_RSTB),
.C_RSTRAM (C_RSTRAM_B),
.C_RST_PRIORITY (C_RST_PRIORITY_B),
.C_INIT_VAL (C_INITB_VAL),
.C_HAS_EN (C_HAS_ENB),
.C_HAS_REGCE (C_HAS_REGCEB),
.C_DATA_WIDTH (C_READ_WIDTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_B),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.NUM_STAGES (NUM_OUTPUT_STAGES_B),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.FLOP_DELAY (FLOP_DELAY))
reg_b
(.CLK (CLKB),
.RST (rstb_outp_stage),//(RSTB),
.EN (ENB),
.REGCE (REGCEB),
.DIN_I (memory_out_b),
.DOUT (dout_i),
.SBITERR_IN_I (sbiterr_in),
.DBITERR_IN_I (dbiterr_in),
.SBITERR (sbiterr_i),
.DBITERR (dbiterr_i),
.RDADDRECC_IN_I (rdaddrecc_in),
.ECCPIPECE (ECCPIPECE),
.RDADDRECC (rdaddrecc_i)
);
//***************************************************************
// Instantiate the Input and Output register stages
//***************************************************************
blk_mem_gen_v8_3_5_softecc_output_reg_stage
#(.C_DATA_WIDTH (C_READ_WIDTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_USE_SOFTECC (C_USE_SOFTECC),
.FLOP_DELAY (FLOP_DELAY))
has_softecc_output_reg_stage
(.CLK (CLKB),
.DIN (dout_i),
.DOUT (DOUTB),
.SBITERR_IN (sbiterr_i),
.DBITERR_IN (dbiterr_i),
.SBITERR (sbiterr_sdp),
.DBITERR (dbiterr_sdp),
.RDADDRECC_IN (rdaddrecc_i),
.RDADDRECC (rdaddrecc_sdp)
);
//****************************************************
// Synchronous collision checks
//****************************************************
// CR 780544 : To make verilog model's collison warnings in consistant with
// vhdl model, the non-blocking assignments are replaced with blocking
// assignments.
generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll
always @(posedge CLKA) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision = 0;
end
end else begin
is_collision = 0;
end
// If the write port is in READ_FIRST mode, there is no collision
if (C_WRITE_MODE_A=="READ_FIRST" && wea_i && !web_i) begin
is_collision = 0;
end
if (C_WRITE_MODE_B=="READ_FIRST" && web_i && !wea_i) begin
is_collision = 0;
end
// Only flag if one of the accesses is a write
if (is_collision && (wea_i || web_i)) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B %0s address: %0h\n",
wea_i ? "write" : "read", ADDRA,
web_i ? "write" : "read", ADDRB);
end
end
//****************************************************
// Asynchronous collision checks
//****************************************************
end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll
// Delay A and B addresses in order to mimic setup/hold times
wire [C_ADDRA_WIDTH-1:0] #COLL_DELAY addra_delay = ADDRA;
wire [0:0] #COLL_DELAY wea_delay = wea_i;
wire #COLL_DELAY ena_delay = ena_i;
wire [C_ADDRB_WIDTH-1:0] #COLL_DELAY addrb_delay = ADDRB;
wire [0:0] #COLL_DELAY web_delay = web_i;
wire #COLL_DELAY enb_delay = enb_i;
// Do the checks w/rt A
always @(posedge CLKA) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision_a = 0;
end
end else begin
is_collision_a = 0;
end
if (ena_i && enb_delay) begin
if(wea_i || web_delay) begin
is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,
web_delay);
end else begin
is_collision_delay_a = 0;
end
end else begin
is_collision_delay_a = 0;
end
// Only flag if B access is a write
if (is_collision_a && web_i) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n",
wea_i ? "write" : "read", ADDRA, ADDRB);
end else if (is_collision_delay_a && web_delay) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n",
wea_i ? "write" : "read", ADDRA, addrb_delay);
end
end
// Do the checks w/rt B
always @(posedge CLKB) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision_b = 0;
end
end else begin
is_collision_b = 0;
end
if (ena_delay && enb_i) begin
if (wea_delay || web_i) begin
is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,
web_i);
end else begin
is_collision_delay_b = 0;
end
end else begin
is_collision_delay_b = 0;
end
// Only flag if A access is a write
if (is_collision_b && wea_i) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n",
ADDRA, web_i ? "write" : "read", ADDRB);
end else if (is_collision_delay_b && wea_delay) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n",
addra_delay, web_i ? "write" : "read", ADDRB);
end
end
end
endgenerate
endmodule
//*****************************************************************************
// Top module wraps Input register and Memory module
//
// This module is the top-level behavioral model and this implements the memory
// module and the input registers
//*****************************************************************************
module blk_mem_gen_v8_3_5
#(parameter C_CORENAME = "blk_mem_gen_v8_3_5",
parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_ELABORATION_DIR = "",
parameter C_INTERFACE_TYPE = 0,
parameter C_USE_BRAM_BLOCK = 0,
parameter C_CTRL_ECC_ALGO = "NONE",
parameter C_ENABLE_32BIT_ADDRESS = 0,
parameter C_AXI_TYPE = 0,
parameter C_AXI_SLAVE_TYPE = 0,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
parameter C_MEM_TYPE = 2,
parameter C_BYTE_SIZE = 9,
parameter C_ALGORITHM = 1,
parameter C_PRIM_TYPE = 3,
parameter C_LOAD_INIT_FILE = 0,
parameter C_INIT_FILE_NAME = "",
parameter C_INIT_FILE = "",
parameter C_USE_DEFAULT_DATA = 0,
parameter C_DEFAULT_DATA = "0",
//parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RSTA = 0,
parameter C_RST_PRIORITY_A = "CE",
parameter C_RSTRAM_A = 0,
parameter C_INITA_VAL = "0",
parameter C_HAS_ENA = 1,
parameter C_HAS_REGCEA = 0,
parameter C_USE_BYTE_WEA = 0,
parameter C_WEA_WIDTH = 1,
parameter C_WRITE_MODE_A = "WRITE_FIRST",
parameter C_WRITE_WIDTH_A = 32,
parameter C_READ_WIDTH_A = 32,
parameter C_WRITE_DEPTH_A = 64,
parameter C_READ_DEPTH_A = 64,
parameter C_ADDRA_WIDTH = 5,
parameter C_HAS_RSTB = 0,
parameter C_RST_PRIORITY_B = "CE",
parameter C_RSTRAM_B = 0,
parameter C_INITB_VAL = "",
parameter C_HAS_ENB = 1,
parameter C_HAS_REGCEB = 0,
parameter C_USE_BYTE_WEB = 0,
parameter C_WEB_WIDTH = 1,
parameter C_WRITE_MODE_B = "WRITE_FIRST",
parameter C_WRITE_WIDTH_B = 32,
parameter C_READ_WIDTH_B = 32,
parameter C_WRITE_DEPTH_B = 64,
parameter C_READ_DEPTH_B = 64,
parameter C_ADDRB_WIDTH = 5,
parameter C_HAS_MEM_OUTPUT_REGS_A = 0,
parameter C_HAS_MEM_OUTPUT_REGS_B = 0,
parameter C_HAS_MUX_OUTPUT_REGS_A = 0,
parameter C_HAS_MUX_OUTPUT_REGS_B = 0,
parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_MUX_PIPELINE_STAGES = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter C_EN_ECC_PIPE = 0,
parameter C_HAS_INJECTERR = 0,
parameter C_SIM_COLLISION_CHECK = "NONE",
parameter C_COMMON_CLK = 1,
parameter C_DISABLE_WARN_BHV_COLL = 0,
parameter C_EN_SLEEP_PIN = 0,
parameter C_USE_URAM = 0,
parameter C_EN_RDADDRA_CHG = 0,
parameter C_EN_RDADDRB_CHG = 0,
parameter C_EN_DEEPSLEEP_PIN = 0,
parameter C_EN_SHUTDOWN_PIN = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_COUNT_36K_BRAM = "",
parameter C_COUNT_18K_BRAM = "",
parameter C_EST_POWER_SUMMARY = "",
parameter C_DISABLE_WARN_BHV_RANGE = 0
)
(input clka,
input rsta,
input ena,
input regcea,
input [C_WEA_WIDTH-1:0] wea,
input [C_ADDRA_WIDTH-1:0] addra,
input [C_WRITE_WIDTH_A-1:0] dina,
output [C_READ_WIDTH_A-1:0] douta,
input clkb,
input rstb,
input enb,
input regceb,
input [C_WEB_WIDTH-1:0] web,
input [C_ADDRB_WIDTH-1:0] addrb,
input [C_WRITE_WIDTH_B-1:0] dinb,
output [C_READ_WIDTH_B-1:0] doutb,
input injectsbiterr,
input injectdbiterr,
output sbiterr,
output dbiterr,
output [C_ADDRB_WIDTH-1:0] rdaddrecc,
input eccpipece,
input sleep,
input deepsleep,
input shutdown,
output rsta_busy,
output rstb_busy,
//AXI BMG Input and Output Port Declarations
//AXI Global Signals
input s_aclk,
input s_aresetn,
//AXI Full/lite slave write (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input [31:0] s_axi_awaddr,
input [7:0] s_axi_awlen,
input [2:0] s_axi_awsize,
input [1:0] s_axi_awburst,
input s_axi_awvalid,
output s_axi_awready,
input [C_WRITE_WIDTH_A-1:0] s_axi_wdata,
input [C_WEA_WIDTH-1:0] s_axi_wstrb,
input s_axi_wlast,
input s_axi_wvalid,
output s_axi_wready,
output [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output [1:0] s_axi_bresp,
output s_axi_bvalid,
input s_axi_bready,
//AXI Full/lite slave read (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input [31:0] s_axi_araddr,
input [7:0] s_axi_arlen,
input [2:0] s_axi_arsize,
input [1:0] s_axi_arburst,
input s_axi_arvalid,
output s_axi_arready,
output [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output [C_WRITE_WIDTH_B-1:0] s_axi_rdata,
output [1:0] s_axi_rresp,
output s_axi_rlast,
output s_axi_rvalid,
input s_axi_rready,
//AXI Full/lite sideband signals
input s_axi_injectsbiterr,
input s_axi_injectdbiterr,
output s_axi_sbiterr,
output s_axi_dbiterr,
output [C_ADDRB_WIDTH-1:0] s_axi_rdaddrecc
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_CORENAME : Instance name of the Block Memory Generator core
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_MEM_TYPE : Designates memory type.
// It can be
// 0 - Single Port Memory
// 1 - Simple Dual Port Memory
// 2 - True Dual Port Memory
// 3 - Single Port Read Only Memory
// 4 - Dual Port Read Only Memory
// C_BYTE_SIZE : Size of a byte (8 or 9 bits)
// C_ALGORITHM : Designates the algorithm method used
// for constructing the memory.
// It can be Fixed_Primitives, Minimum_Area or
// Low_Power
// C_PRIM_TYPE : Designates the user selected primitive used to
// construct the memory.
//
// C_LOAD_INIT_FILE : Designates the use of an initialization file to
// initialize memory contents.
// C_INIT_FILE_NAME : Memory initialization file name.
// C_USE_DEFAULT_DATA : Designates whether to fill remaining
// initialization space with default data
// C_DEFAULT_DATA : Default value of all memory locations
// not initialized by the memory
// initialization file.
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RSTA : Determines the presence of the RSTA port
// C_RST_PRIORITY_A : Determines the priority between CE and SR for
// Port A.
// C_RSTRAM_A : Determines if special reset behavior is used for
// Port A
// C_INITA_VAL : The initialization value for Port A
// C_HAS_ENA : Determines the presence of the ENA port
// C_HAS_REGCEA : Determines the presence of the REGCEA port
// C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
// C_WEA_WIDTH : The width of the WEA port
// C_WRITE_MODE_A : Configurable write mode for Port A. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_A : Memory write width for Port A.
// C_READ_WIDTH_A : Memory read width for Port A.
// C_WRITE_DEPTH_A : Memory write depth for Port A.
// C_READ_DEPTH_A : Memory read depth for Port A.
// C_ADDRA_WIDTH : Width of the ADDRA input port
// C_HAS_RSTB : Determines the presence of the RSTB port
// C_RST_PRIORITY_B : Determines the priority between CE and SR for
// Port B.
// C_RSTRAM_B : Determines if special reset behavior is used for
// Port B
// C_INITB_VAL : The initialization value for Port B
// C_HAS_ENB : Determines the presence of the ENB port
// C_HAS_REGCEB : Determines the presence of the REGCEB port
// C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
// C_WEB_WIDTH : The width of the WEB port
// C_WRITE_MODE_B : Configurable write mode for Port B. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_B : Memory write width for Port B.
// C_READ_WIDTH_B : Memory read width for Port B.
// C_WRITE_DEPTH_B : Memory write depth for Port B.
// C_READ_DEPTH_B : Memory read depth for Port B.
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
// of the RAM primitive for Port A.
// C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive for Port B.
// C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
// of the MUX for Port A.
// C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
// of the MUX for Port B.
// C_HAS_SOFTECC_INPUT_REGS_A :
// C_HAS_SOFTECC_OUTPUT_REGS_B :
// C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
// between the muxes.
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// C_HAS_INJECTERR : Determines if the error injection pins
// are present or not. If the ECC feature
// is not used, this value is defaulted to
// 0, else the following are the allowed
// values:
// 0 : No INJECTSBITERR or INJECTDBITERR pins
// 1 : Only INJECTSBITERR pin exists
// 2 : Only INJECTDBITERR pin exists
// 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
// C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
// warnings. It can be "ALL", "NONE",
// "Warnings_Only" or "Generate_X_Only".
// C_COMMON_CLK : Determins if the core has a single CLK input.
// C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
// C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
// warnings
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLKA : Clock to synchronize all read and write operations of Port A.
// RSTA : Reset input to reset memory outputs to a user-defined
// reset state for Port A.
// ENA : Enable all read and write operations of Port A.
// REGCEA : Register Clock Enable to control each pipeline output
// register stages for Port A.
// WEA : Write Enable to enable all write operations of Port A.
// ADDRA : Address of Port A.
// DINA : Data input of Port A.
// DOUTA : Data output of Port A.
// CLKB : Clock to synchronize all read and write operations of Port B.
// RSTB : Reset input to reset memory outputs to a user-defined
// reset state for Port B.
// ENB : Enable all read and write operations of Port B.
// REGCEB : Register Clock Enable to control each pipeline output
// register stages for Port B.
// WEB : Write Enable to enable all write operations of Port B.
// ADDRB : Address of Port B.
// DINB : Data input of Port B.
// DOUTB : Data output of Port B.
// INJECTSBITERR : Single Bit ECC Error Injection Pin.
// INJECTDBITERR : Double Bit ECC Error Injection Pin.
// SBITERR : Output signal indicating that a Single Bit ECC Error has been
// detected and corrected.
// DBITERR : Output signal indicating that a Double Bit ECC Error has been
// detected.
// RDADDRECC : Read Address Output signal indicating address at which an
// ECC error has occurred.
//////////////////////////////////////////////////////////////////////////
wire SBITERR;
wire DBITERR;
wire S_AXI_AWREADY;
wire S_AXI_WREADY;
wire S_AXI_BVALID;
wire S_AXI_ARREADY;
wire S_AXI_RLAST;
wire S_AXI_RVALID;
wire S_AXI_SBITERR;
wire S_AXI_DBITERR;
wire [C_WEA_WIDTH-1:0] WEA = wea;
wire [C_ADDRA_WIDTH-1:0] ADDRA = addra;
wire [C_WRITE_WIDTH_A-1:0] DINA = dina;
wire [C_READ_WIDTH_A-1:0] DOUTA;
wire [C_WEB_WIDTH-1:0] WEB = web;
wire [C_ADDRB_WIDTH-1:0] ADDRB = addrb;
wire [C_WRITE_WIDTH_B-1:0] DINB = dinb;
wire [C_READ_WIDTH_B-1:0] DOUTB;
wire [C_ADDRB_WIDTH-1:0] RDADDRECC;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID = s_axi_awid;
wire [31:0] S_AXI_AWADDR = s_axi_awaddr;
wire [7:0] S_AXI_AWLEN = s_axi_awlen;
wire [2:0] S_AXI_AWSIZE = s_axi_awsize;
wire [1:0] S_AXI_AWBURST = s_axi_awburst;
wire [C_WRITE_WIDTH_A-1:0] S_AXI_WDATA = s_axi_wdata;
wire [C_WEA_WIDTH-1:0] S_AXI_WSTRB = s_axi_wstrb;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID;
wire [1:0] S_AXI_BRESP;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID = s_axi_arid;
wire [31:0] S_AXI_ARADDR = s_axi_araddr;
wire [7:0] S_AXI_ARLEN = s_axi_arlen;
wire [2:0] S_AXI_ARSIZE = s_axi_arsize;
wire [1:0] S_AXI_ARBURST = s_axi_arburst;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID;
wire [C_WRITE_WIDTH_B-1:0] S_AXI_RDATA;
wire [1:0] S_AXI_RRESP;
wire [C_ADDRB_WIDTH-1:0] S_AXI_RDADDRECC;
// Added to fix the simulation warning #CR731605
wire [C_WEB_WIDTH-1:0] WEB_parameterized = 0;
wire ECCPIPECE;
wire SLEEP;
reg RSTA_BUSY = 0;
reg RSTB_BUSY = 0;
// Declaration of internal signals to avoid warnings #927399
wire CLKA;
wire RSTA;
wire ENA;
wire REGCEA;
wire CLKB;
wire RSTB;
wire ENB;
wire REGCEB;
wire INJECTSBITERR;
wire INJECTDBITERR;
wire S_ACLK;
wire S_ARESETN;
wire S_AXI_AWVALID;
wire S_AXI_WLAST;
wire S_AXI_WVALID;
wire S_AXI_BREADY;
wire S_AXI_ARVALID;
wire S_AXI_RREADY;
wire S_AXI_INJECTSBITERR;
wire S_AXI_INJECTDBITERR;
assign CLKA = clka;
assign RSTA = rsta;
assign ENA = ena;
assign REGCEA = regcea;
assign CLKB = clkb;
assign RSTB = rstb;
assign ENB = enb;
assign REGCEB = regceb;
assign INJECTSBITERR = injectsbiterr;
assign INJECTDBITERR = injectdbiterr;
assign ECCPIPECE = eccpipece;
assign SLEEP = sleep;
assign sbiterr = SBITERR;
assign dbiterr = DBITERR;
assign S_ACLK = s_aclk;
assign S_ARESETN = s_aresetn;
assign S_AXI_AWVALID = s_axi_awvalid;
assign s_axi_awready = S_AXI_AWREADY;
assign S_AXI_WLAST = s_axi_wlast;
assign S_AXI_WVALID = s_axi_wvalid;
assign s_axi_wready = S_AXI_WREADY;
assign s_axi_bvalid = S_AXI_BVALID;
assign S_AXI_BREADY = s_axi_bready;
assign S_AXI_ARVALID = s_axi_arvalid;
assign s_axi_arready = S_AXI_ARREADY;
assign s_axi_rlast = S_AXI_RLAST;
assign s_axi_rvalid = S_AXI_RVALID;
assign S_AXI_RREADY = s_axi_rready;
assign S_AXI_INJECTSBITERR = s_axi_injectsbiterr;
assign S_AXI_INJECTDBITERR = s_axi_injectdbiterr;
assign s_axi_sbiterr = S_AXI_SBITERR;
assign s_axi_dbiterr = S_AXI_DBITERR;
assign rsta_busy = RSTA_BUSY;
assign rstb_busy = RSTB_BUSY;
assign doutb = DOUTB;
assign douta = DOUTA;
assign rdaddrecc = RDADDRECC;
assign s_axi_bid = S_AXI_BID;
assign s_axi_bresp = S_AXI_BRESP;
assign s_axi_rid = S_AXI_RID;
assign s_axi_rdata = S_AXI_RDATA;
assign s_axi_rresp = S_AXI_RRESP;
assign s_axi_rdaddrecc = S_AXI_RDADDRECC;
localparam FLOP_DELAY = 100; // 100 ps
reg injectsbiterr_in;
reg injectdbiterr_in;
reg rsta_in;
reg ena_in;
reg regcea_in;
reg [C_WEA_WIDTH-1:0] wea_in;
reg [C_ADDRA_WIDTH-1:0] addra_in;
reg [C_WRITE_WIDTH_A-1:0] dina_in;
wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;
wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;
wire s_axi_wr_en_c;
wire s_axi_rd_en_c;
wire s_aresetn_a_c;
wire [7:0] s_axi_arlen_c ;
wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;
wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;
wire [1:0] s_axi_rresp_c;
wire s_axi_rlast_c;
wire s_axi_rvalid_c;
wire s_axi_rready_c;
wire regceb_c;
localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;
wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;
wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;
// Safety logic related signals
reg [4:0] RSTA_SHFT_REG = 0;
reg POR_A = 0;
reg [4:0] RSTB_SHFT_REG = 0;
reg POR_B = 0;
reg ENA_dly = 0;
reg ENA_dly_D = 0;
reg ENB_dly = 0;
reg ENB_dly_D = 0;
wire RSTA_I_SAFE;
wire RSTB_I_SAFE;
wire ENA_I_SAFE;
wire ENB_I_SAFE;
reg ram_rstram_a_busy = 0;
reg ram_rstreg_a_busy = 0;
reg ram_rstram_b_busy = 0;
reg ram_rstreg_b_busy = 0;
reg ENA_dly_reg = 0;
reg ENB_dly_reg = 0;
reg ENA_dly_reg_D = 0;
reg ENB_dly_reg_D = 0;
//**************
// log2roundup
//**************
function integer log2roundup (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
if (data_value > 1) begin
for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin
width = width + 1;
end //loop
end //if
log2roundup = width;
end //log2roundup
endfunction
//**************
// log2int
//**************
function integer log2int (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
cnt= data_value;
for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin
width = width + 1;
end //loop
log2int = width;
end //log2int
endfunction
//**************************************************************************
// FUNCTION : divroundup
// Returns the ceiling value of the division
// Data_value - the quantity to be divided, dividend
// Divisor - the value to divide the data_value by
//**************************************************************************
function integer divroundup (input integer data_value,input integer divisor);
integer div;
begin
div = data_value/divisor;
if ((data_value % divisor) != 0) begin
div = div+1;
end //if
divroundup = div;
end //if
endfunction
localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);
localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);
localparam C_AXI_ADDR_WIDTH = C_AXI_ADDR_WIDTH_MSB;
//Data Width Number of LSB address bits to be discarded
//1 to 16 1
//17 to 32 2
//33 to 64 3
//65 to 128 4
//129 to 256 5
//257 to 512 6
//513 to 1024 7
// The following two constants determine this.
localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));
localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);
localparam C_AXI_OS_WR = 2;
//***********************************************
// INPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage
always @* begin
injectsbiterr_in = INJECTSBITERR;
injectdbiterr_in = INJECTDBITERR;
rsta_in = RSTA;
ena_in = ENA;
regcea_in = REGCEA;
wea_in = WEA;
addra_in = ADDRA;
dina_in = DINA;
end //end always
end //end no_softecc_input_reg_stage
endgenerate
generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage
always @(posedge CLKA) begin
injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;
injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;
rsta_in <= #FLOP_DELAY RSTA;
ena_in <= #FLOP_DELAY ENA;
regcea_in <= #FLOP_DELAY REGCEA;
wea_in <= #FLOP_DELAY WEA;
addra_in <= #FLOP_DELAY ADDRA;
dina_in <= #FLOP_DELAY DINA;
end //end always
end //end input_reg_stages generate statement
endgenerate
//**************************************************************************
// NO SAFETY LOGIC
//**************************************************************************
generate
if (C_EN_SAFETY_CKT == 0) begin : NO_SAFETY_CKT_GEN
assign ENA_I_SAFE = ena_in;
assign ENB_I_SAFE = ENB;
assign RSTA_I_SAFE = rsta_in;
assign RSTB_I_SAFE = RSTB;
end
endgenerate
//***************************************************************************
// SAFETY LOGIC
// Power-ON Reset Generation
//***************************************************************************
generate
if (C_EN_SAFETY_CKT == 1) begin
always @(posedge clka) RSTA_SHFT_REG <= #FLOP_DELAY {RSTA_SHFT_REG[3:0],1'b1} ;
always @(posedge clka) POR_A <= #FLOP_DELAY RSTA_SHFT_REG[4] ^ RSTA_SHFT_REG[0];
always @(posedge clkb) RSTB_SHFT_REG <= #FLOP_DELAY {RSTB_SHFT_REG[3:0],1'b1} ;
always @(posedge clkb) POR_B <= #FLOP_DELAY RSTB_SHFT_REG[4] ^ RSTB_SHFT_REG[0];
assign RSTA_I_SAFE = rsta_in | POR_A;
assign RSTB_I_SAFE = (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) ? 1'b0 : (RSTB | POR_B);
end
endgenerate
//-----------------------------------------------------------------------------
// -- RSTA/B_BUSY Generation
//-----------------------------------------------------------------------------
generate
if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && (C_EN_SAFETY_CKT == 1)) begin : RSTA_BUSY_NO_REG
always @(*) ram_rstram_a_busy = RSTA_I_SAFE | ENA_dly | ENA_dly_D;
always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstram_a_busy;
end
endgenerate
generate
if (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0 && C_EN_SAFETY_CKT == 1) begin : RSTA_BUSY_WITH_REG
always @(*) ram_rstreg_a_busy = RSTA_I_SAFE | ENA_dly_reg | ENA_dly_reg_D;
always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstreg_a_busy;
end
endgenerate
generate
if ( (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) && C_EN_SAFETY_CKT == 1) begin : SPRAM_RST_BUSY
always @(*) RSTB_BUSY = 1'b0;
end
endgenerate
generate
if ( (C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && (C_MEM_TYPE != 0 && C_MEM_TYPE != 3) && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_NO_REG
always @(*) ram_rstram_b_busy = RSTB_I_SAFE | ENB_dly | ENB_dly_D;
always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstram_b_busy;
end
endgenerate
generate
if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_WITH_REG
always @(*) ram_rstreg_b_busy = RSTB_I_SAFE | ENB_dly_reg | ENB_dly_reg_D;
always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstreg_b_busy;
end
endgenerate
//-----------------------------------------------------------------------------
// -- ENA/ENB Generation
//-----------------------------------------------------------------------------
generate
if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && C_EN_SAFETY_CKT == 1) begin : ENA_NO_REG
always @(posedge clka) begin
ENA_dly <= #FLOP_DELAY RSTA_I_SAFE;
ENA_dly_D <= #FLOP_DELAY ENA_dly;
end
assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_D | ena_in);
end
endgenerate
generate
if ( (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0) && C_EN_SAFETY_CKT == 1) begin : ENA_WITH_REG
always @(posedge clka) begin
ENA_dly_reg <= #FLOP_DELAY RSTA_I_SAFE;
ENA_dly_reg_D <= #FLOP_DELAY ENA_dly_reg;
end
assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_reg_D | ena_in);
end
endgenerate
generate
if (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) begin : SPRAM_ENB
assign ENB_I_SAFE = 1'b0;
end
endgenerate
generate
if ((C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : ENB_NO_REG
always @(posedge clkb) begin : PROC_ENB_GEN
ENB_dly <= #FLOP_DELAY RSTB_I_SAFE;
ENB_dly_D <= #FLOP_DELAY ENB_dly;
end
assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_D | ENB);
end
endgenerate
generate
if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1)begin : ENB_WITH_REG
always @(posedge clkb) begin : PROC_ENB_GEN
ENB_dly_reg <= #FLOP_DELAY RSTB_I_SAFE;
ENB_dly_reg_D <= #FLOP_DELAY ENB_dly_reg;
end
assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_reg_D | ENB);
end
endgenerate
generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module
blk_mem_gen_v8_3_5_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_ALGORITHM (C_ALGORITHM),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (C_HAS_ENA),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (C_USE_BYTE_WEA),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (C_HAS_ENB),
.C_HAS_REGCEB (C_HAS_REGCEB),
.C_USE_BYTE_WEB (C_USE_BYTE_WEB),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A),
.C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_3_5_inst
(.CLKA (CLKA),
.RSTA (RSTA_I_SAFE),//(rsta_in),
.ENA (ENA_I_SAFE),//(ena_in),
.REGCEA (regcea_in),
.WEA (wea_in),
.ADDRA (addra_in),
.DINA (dina_in),
.DOUTA (DOUTA),
.CLKB (CLKB),
.RSTB (RSTB_I_SAFE),//(RSTB),
.ENB (ENB_I_SAFE),//(ENB),
.REGCEB (REGCEB),
.WEB (WEB),
.ADDRB (ADDRB),
.DINB (DINB),
.DOUTB (DOUTB),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.ECCPIPECE (ECCPIPECE),
.SLEEP (SLEEP),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.RDADDRECC (RDADDRECC)
);
end
endgenerate
generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module
localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);
localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);
localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);
localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);
// localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);
// localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);
localparam C_MEM_MAP_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_MSB;
localparam C_MEM_MAP_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_MSB;
// Data Width Number of LSB address bits to be discarded
// 1 to 16 1
// 17 to 32 2
// 33 to 64 3
// 65 to 128 4
// 129 to 256 5
// 257 to 512 6
// 513 to 1024 7
// The following two constants determine this.
localparam MEM_MAP_LOWER_BOUND_VAL_A = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));
localparam MEM_MAP_LOWER_BOUND_VAL_B = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));
localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;
localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;
wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;
wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;
wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;
assign msb_zero_i = 0;
assign lsb_zero_i = 0;
assign RDADDRECC = {msb_zero_i,rdaddrecc_i,lsb_zero_i};
blk_mem_gen_v8_3_5_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_ALGORITHM (C_ALGORITHM),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (C_HAS_ENA),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (C_USE_BYTE_WEA),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH_ACTUAL),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (C_HAS_ENB),
.C_HAS_REGCEB (C_HAS_REGCEB),
.C_USE_BYTE_WEB (C_USE_BYTE_WEB),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH_ACTUAL),
.C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A),
.C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_3_5_inst
(.CLKA (CLKA),
.RSTA (RSTA_I_SAFE),//(rsta_in),
.ENA (ENA_I_SAFE),//(ena_in),
.REGCEA (regcea_in),
.WEA (wea_in),
.ADDRA (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),
.DINA (dina_in),
.DOUTA (DOUTA),
.CLKB (CLKB),
.RSTB (RSTB_I_SAFE),//(RSTB),
.ENB (ENB_I_SAFE),//(ENB),
.REGCEB (REGCEB),
.WEB (WEB),
.ADDRB (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),
.DINB (DINB),
.DOUTB (DOUTB),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.ECCPIPECE (ECCPIPECE),
.SLEEP (SLEEP),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.RDADDRECC (rdaddrecc_i)
);
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs
assign S_AXI_RDATA = s_axi_rdata_c;
assign S_AXI_RLAST = s_axi_rlast_c;
assign S_AXI_RVALID = s_axi_rvalid_c;
assign S_AXI_RID = s_axi_rid_c;
assign S_AXI_RRESP = s_axi_rresp_c;
assign s_axi_rready_c = S_AXI_RREADY;
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb
assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb
assign regceb_c = REGCEB;
end
endgenerate
generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs
assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};
assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];
assign S_AXI_RDATA = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];
assign S_AXI_RRESP = m_axi_payload_c[2:1];
assign S_AXI_RLAST = m_axi_payload_c[0];
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs
assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};
assign S_AXI_RDATA = s_axi_rdata_c;
assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];
assign S_AXI_RRESP = m_axi_payload_c[2:1];
assign S_AXI_RLAST = m_axi_payload_c[0];
end
endgenerate
generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd
blk_mem_axi_regs_fwd_v8_3
#(.C_DATA_WIDTH (C_AXI_PAYLOAD))
axi_regs_inst (
.ACLK (S_ACLK),
.ARESET (s_aresetn_a_c),
.S_VALID (s_axi_rvalid_c),
.S_READY (s_axi_rready_c),
.S_PAYLOAD_DATA (s_axi_payload_c),
.M_VALID (S_AXI_RVALID),
.M_READY (S_AXI_RREADY),
.M_PAYLOAD_DATA (m_axi_payload_c)
);
end
endgenerate
generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module
assign s_aresetn_a_c = !S_ARESETN;
assign S_AXI_BRESP = 2'b00;
assign s_axi_rresp_c = 2'b00;
assign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;
blk_mem_axi_write_wrapper_beh_v8_3
#(.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE),
.C_MEMORY_TYPE (C_MEM_TYPE),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_AXI_AWADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
.C_HAS_AXI_ID (C_HAS_AXI_ID),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_AXI_WDATA_WIDTH (C_WRITE_WIDTH_A),
.C_AXI_OS_WR (C_AXI_OS_WR))
axi_wr_fsm (
// AXI Global Signals
.S_ACLK (S_ACLK),
.S_ARESETN (s_aresetn_a_c),
// AXI Full/Lite Slave Write interface
.S_AXI_AWADDR (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
.S_AXI_BID (S_AXI_BID),
// Signals for BRAM interfac(
.S_AXI_AWADDR_OUT (s_axi_awaddr_out_c),
.S_AXI_WR_EN (s_axi_wr_en_c)
);
blk_mem_axi_read_wrapper_beh_v8_3
#(.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE),
.C_MEMORY_TYPE (C_MEM_TYPE),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_AXI_PIPELINE_STAGES (1),
.C_AXI_ARADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
.C_HAS_AXI_ID (C_HAS_AXI_ID),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH))
axi_rd_sm(
//AXI Global Signals
.S_ACLK (S_ACLK),
.S_ARESETN (s_aresetn_a_c),
//AXI Full/Lite Read Side
.S_AXI_ARADDR (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),
.S_AXI_ARLEN (s_axi_arlen_c),
.S_AXI_ARSIZE (S_AXI_ARSIZE),
.S_AXI_ARBURST (S_AXI_ARBURST),
.S_AXI_ARVALID (S_AXI_ARVALID),
.S_AXI_ARREADY (S_AXI_ARREADY),
.S_AXI_RLAST (s_axi_rlast_c),
.S_AXI_RVALID (s_axi_rvalid_c),
.S_AXI_RREADY (s_axi_rready_c),
.S_AXI_ARID (S_AXI_ARID),
.S_AXI_RID (s_axi_rid_c),
//AXI Full/Lite Read FSM Outputs
.S_AXI_ARADDR_OUT (s_axi_araddr_out_c),
.S_AXI_RD_EN (s_axi_rd_en_c)
);
blk_mem_gen_v8_3_5_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_ALGORITHM (C_ALGORITHM),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (1),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (1),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (1),
.C_HAS_REGCEB (C_HAS_MEM_OUTPUT_REGS_B),
.C_USE_BYTE_WEB (1),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS_A (0),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (0),
.C_HAS_MUX_OUTPUT_REGS_B (0),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (0),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_3_5_inst
(.CLKA (S_ACLK),
.RSTA (s_aresetn_a_c),
.ENA (s_axi_wr_en_c),
.REGCEA (regcea_in),
.WEA (S_AXI_WSTRB),
.ADDRA (s_axi_awaddr_out_c),
.DINA (S_AXI_WDATA),
.DOUTA (DOUTA),
.CLKB (S_ACLK),
.RSTB (s_aresetn_a_c),
.ENB (s_axi_rd_en_c),
.REGCEB (regceb_c),
.WEB (WEB_parameterized),
.ADDRB (s_axi_araddr_out_c),
.DINB (DINB),
.DOUTB (s_axi_rdata_c),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.ECCPIPECE (1'b0),
.SLEEP (1'b0),
.RDADDRECC (RDADDRECC)
);
end
endgenerate
endmodule
|
/*
* Copyright (c) 2001 Stephan Boettcher <[email protected]>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// $Id: eeq.v,v 1.1 2001/06/26 01:07:15 sib4 Exp $
// $Log: eeq.v,v $
// Revision 1.1 2001/06/26 01:07:15 sib4
// new test for === and !==
//
//
// Test for === amd !== in structural context.
module eeq;
reg [3:0] a, b;
wire eeq = a === b;
`ifdef DONT_TEST_NEE
wire nee = ~(a === b);
`else
wire nee = a !== b;
`endif
reg err;
always
begin
#2;
$display("%b %b ===%b !==%b", a, b, eeq, nee);
if (((a === b) !== eeq) || ((a !== b) !== nee)) err = 1;
end
initial
begin
err = 0;
#1 a = 4'b zx10; b = 4'b zx10; #1;
#1 a = 4'b 1x10; b = 4'b zx10; #1;
#1 a = 4'b xz10; b = 4'b zx10; #1;
#1 a = 4'b xz01; b = 4'b zx10; #1;
#1 a = 4'b 0000; b = 4'b 0000; #1;
#1 a = 4'b 1111; b = 4'b 1111; #1;
#1 a = 4'b xxxx; b = 4'b xxxx; #1;
#1 a = 4'b zzzz; b = 4'b zzzz; #1;
#1;
if (err)
$display("FAILED");
else
$display("PASSED");
$finish;
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:32:43 09/11/2015
// Design Name: WB_intercon
// Module Name: Z:/share/ISE/CPUFly/tests/WB_intercon_test.v
// Project Name: CPUFly
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: WB_intercon
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module WB_intercon_test;
// Inputs
reg master_STB;
reg [31:0] master_DAT_I;
reg master_WE;
reg [31:0] master_ADDR;
reg [15:0] slave_ACK;
reg [511:0] slave_DAT_I;
// Outputs
wire [31:0] master_DAT_O;
wire master_ACK;
wire [15:0] slave_STB;
wire slave_WE;
wire [31:0] slave_DAT_O;
wire [31:0] slave_ADDR;
// Instantiate the Unit Under Test (UUT)
WB_intercon uut (
.master_STB(master_STB),
.master_DAT_I(master_DAT_I),
.master_DAT_O(master_DAT_O),
.master_ACK(master_ACK),
.master_WE(master_WE),
.master_ADDR(master_ADDR),
.slave_STB(slave_STB),
.slave_ACK(slave_ACK),
.slave_WE(slave_WE),
.slave_DAT_I(slave_DAT_I),
.slave_DAT_O(slave_DAT_O),
.slave_ADDR(slave_ADDR)
);
initial begin
// Initialize Inputs
master_STB = 0;
master_DAT_I = 0;
master_WE = 0;
master_ADDR = 0;
slave_ACK = 0;
slave_DAT_I = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
master_STB = 1;
master_DAT_I = 16'h2333;
master_WE = 1;
master_ADDR = 32'h10000000;
slave_ACK = 1;
slave_DAT_I = 32'h00002333;
end
endmodule
|
//bug844
module device(
input clk,
output logic [7:0] Q, out0,
output logic pass, fail
input [7:0] D, in0,in1 );
enum logic [2:0] {IDLE, START, RUN, PASS, FAIL } state, next_state;
logic ready, next_ready;
logic next_pass, next_fail;
always_ff @(posedge clk, negedge rstn)
if (!rstn) begin
state <= IDLE;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
fail <= 1'h0;
pass <= 1'h0;
ready <= 1'h0;
// End of automatics
end
else begin
state <= next_state;
ready <= next_ready;
pass <= next_pass;
fail <= next_fail;
end
always @* begin
if (!ready) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
out0 = 8'h0;
// End of automatics
end
else begin
out0 = sel ? in1 : in0;
end
end
always_comb begin
next_state = state;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
next_fail = 1'h0;
next_pass = 1'h0;
next_ready = 1'h0;
// End of automatics
case (state)
IDLE : begin
// stuff ...
end
/* Other states */
PASS: begin
next_state = IDLE;
// stuff ...
next_pass = 1'b1;
next_ready = 1'b1;
end
FAIL: begin
next_state = IDLE;
// stuff ...
next_fail = 1'b1;
end
endcase
end
always_latch begin
if (!rstn) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
Q <= 8'h0;
// End of automatics
end
else if (clk) begin
Q <= D;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__PROBE_P_TB_V
`define SKY130_FD_SC_HDLL__PROBE_P_TB_V
/**
* probe_p: Virtual voltage probe point.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__probe_p.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hdll__probe_p dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__PROBE_P_TB_V
|
// Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2013.4 (lin64) Build 353583 Mon Dec 9 17:26:26 MST 2013
// Date : Sat Mar 15 17:18:29 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode funcsim
// /home/keith/Documents/VHDL-lib/top/lab_2/part_1/build/lab2_part1.srcs/sources_1/ip/clk_base/clk_base_funcsim.v
// Design : clk_base
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* core_generation_info = "clk_base,clk_wiz_v5_1,{component_name=clk_base,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
(* NotValidForBitStream *)
module clk_base
(clk_raw,
clk_100MHz,
clk_250MHz,
locked);
input clk_raw;
output clk_100MHz;
output clk_250MHz;
output locked;
wire clk_100MHz;
wire clk_250MHz;
(* IBUF_LOW_PWR *) wire clk_raw;
wire locked;
clk_baseclk_base_clk_wiz U0
(.clk_100MHz(clk_100MHz),
.clk_250MHz(clk_250MHz),
.clk_raw(clk_raw),
.locked(locked));
endmodule
module clk_baseclk_base_clk_wiz
(clk_raw,
clk_100MHz,
clk_250MHz,
locked);
input clk_raw;
output clk_100MHz;
output clk_250MHz;
output locked;
wire \<const0> ;
wire \<const1> ;
wire clk_100MHz;
wire clk_100MHz_clk_base;
wire clk_250MHz;
wire clk_250MHz_clk_base;
(* IBUF_LOW_PWR *) wire clk_raw;
wire clk_raw_clk_base;
wire clkfbout_buf_clk_base;
wire clkfbout_clk_base;
wire locked;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
(* box_type = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_clk_base),
.O(clkfbout_buf_clk_base));
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
(* box_type = "PRIMITIVE" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_ibufg
(.I(clk_raw),
.O(clk_raw_clk_base));
(* box_type = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_100MHz_clk_base),
.O(clk_100MHz));
(* box_type = "PRIMITIVE" *)
BUFG clkout2_buf
(.I(clk_250MHz_clk_base),
.O(clk_250MHz));
(* box_type = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(10.000000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(10.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(10.000000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(4),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(1),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.000000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_buf_clk_base),
.CLKFBOUT(clkfbout_clk_base),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(clk_raw_clk_base),
.CLKIN2(\<const0> ),
.CLKINSEL(\<const1> ),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(clk_100MHz_clk_base),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(clk_250MHz_clk_base),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
.DCLK(\<const0> ),
.DEN(\<const0> ),
.DI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(\<const0> ),
.LOCKED(locked),
.PSCLK(\<const0> ),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(\<const0> ),
.PSINCDEC(\<const0> ),
.PWRDWN(\<const0> ),
.RST(\<const0> ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2012 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(** Properties of decidable propositions *)
Definition decidable (P:Prop) := P \/ ~ P.
Theorem dec_not_not : forall P:Prop, decidable P -> (~ P -> False) -> P.
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_True : decidable True.
Proof.
unfold decidable; auto.
Qed.
Theorem dec_False : decidable False.
Proof.
unfold decidable, not; auto.
Qed.
Theorem dec_or :
forall A B:Prop, decidable A -> decidable B -> decidable (A \/ B).
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_and :
forall A B:Prop, decidable A -> decidable B -> decidable (A /\ B).
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_not : forall A:Prop, decidable A -> decidable (~ A).
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_imp :
forall A B:Prop, decidable A -> decidable B -> decidable (A -> B).
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_iff :
forall A B:Prop, decidable A -> decidable B -> decidable (A<->B).
Proof.
unfold decidable; tauto.
Qed.
Theorem not_not : forall P:Prop, decidable P -> ~ ~ P -> P.
Proof.
unfold decidable; tauto.
Qed.
Theorem not_or : forall A B:Prop, ~ (A \/ B) -> ~ A /\ ~ B.
Proof.
tauto.
Qed.
Theorem not_and : forall A B:Prop, decidable A -> ~ (A /\ B) -> ~ A \/ ~ B.
Proof.
unfold decidable; tauto.
Qed.
Theorem not_imp : forall A B:Prop, decidable A -> ~ (A -> B) -> A /\ ~ B.
Proof.
unfold decidable; tauto.
Qed.
Theorem imp_simp : forall A B:Prop, decidable A -> (A -> B) -> ~ A \/ B.
Proof.
unfold decidable; tauto.
Qed.
Theorem not_iff :
forall A B:Prop, decidable A -> decidable B ->
~ (A <-> B) -> (A /\ ~ B) \/ (~ A /\ B).
Proof.
unfold decidable; tauto.
Qed.
(** Results formulated with iff, used in FSetDecide.
Negation are expanded since it is unclear whether setoid rewrite
will always perform conversion. *)
(** We begin with lemmas that, when read from left to right,
can be understood as ways to eliminate uses of [not]. *)
Theorem not_true_iff : (True -> False) <-> False.
Proof.
tauto.
Qed.
Theorem not_false_iff : (False -> False) <-> True.
Proof.
tauto.
Qed.
Theorem not_not_iff : forall A:Prop, decidable A ->
(((A -> False) -> False) <-> A).
Proof.
unfold decidable; tauto.
Qed.
Theorem contrapositive : forall A B:Prop, decidable A ->
(((A -> False) -> (B -> False)) <-> (B -> A)).
Proof.
unfold decidable; tauto.
Qed.
Lemma or_not_l_iff_1 : forall A B: Prop, decidable A ->
((A -> False) \/ B <-> (A -> B)).
Proof.
unfold decidable. tauto.
Qed.
Lemma or_not_l_iff_2 : forall A B: Prop, decidable B ->
((A -> False) \/ B <-> (A -> B)).
Proof.
unfold decidable. tauto.
Qed.
Lemma or_not_r_iff_1 : forall A B: Prop, decidable A ->
(A \/ (B -> False) <-> (B -> A)).
Proof.
unfold decidable. tauto.
Qed.
Lemma or_not_r_iff_2 : forall A B: Prop, decidable B ->
(A \/ (B -> False) <-> (B -> A)).
Proof.
unfold decidable. tauto.
Qed.
Lemma imp_not_l : forall A B: Prop, decidable A ->
(((A -> False) -> B) <-> (A \/ B)).
Proof.
unfold decidable. tauto.
Qed.
(** Moving Negations Around:
We have four lemmas that, when read from left to right,
describe how to push negations toward the leaves of a
proposition and, when read from right to left, describe
how to pull negations toward the top of a proposition. *)
Theorem not_or_iff : forall A B:Prop,
(A \/ B -> False) <-> (A -> False) /\ (B -> False).
Proof.
tauto.
Qed.
Lemma not_and_iff : forall A B:Prop,
(A /\ B -> False) <-> (A -> B -> False).
Proof.
tauto.
Qed.
Lemma not_imp_iff : forall A B:Prop, decidable A ->
(((A -> B) -> False) <-> A /\ (B -> False)).
Proof.
unfold decidable. tauto.
Qed.
Lemma not_imp_rev_iff : forall A B : Prop, decidable A ->
(((A -> B) -> False) <-> (B -> False) /\ A).
Proof.
unfold decidable. tauto.
Qed.
(* Functional relations on decidable co-domains are decidable *)
Theorem dec_functional_relation :
forall (X Y : Type) (A:X->Y->Prop), (forall y y' : Y, decidable (y=y')) ->
(forall x, exists! y, A x y) -> forall x y, decidable (A x y).
Proof.
intros X Y A Hdec H x y.
destruct (H x) as (y',(Hex,Huniq)).
destruct (Hdec y y') as [->|Hnot]; firstorder.
Qed.
(** With the following hint database, we can leverage [auto] to check
decidability of propositions. *)
Hint Resolve dec_True dec_False dec_or dec_and dec_imp dec_not dec_iff
: decidable_prop.
(** [solve_decidable using lib] will solve goals about the
decidability of a proposition, assisted by an auxiliary
database of lemmas. The database is intended to contain
lemmas stating the decidability of base propositions,
(e.g., the decidability of equality on a particular
inductive type). *)
Tactic Notation "solve_decidable" "using" ident(db) :=
match goal with
| |- decidable _ =>
solve [ auto 100 with decidable_prop db ]
end.
Tactic Notation "solve_decidable" :=
solve_decidable using core.
|
// ****************************************************************************
// Copyright : NUDT.
// ============================================================================
// FILE NAME : SGMII_RX.v
// CREATE DATE : 2013-12-03
// AUTHOR : ZengQiang
// AUTHOR'S EMAIL : [email protected]
// AUTHOR'S TEL :
// ============================================================================
// RELEASE HISTORY -------------------------------------------------------
// VERSION DATE AUTHOR DESCRIPTION
// 1.0 2013-12-03 ZengQiang Original Verison
// ============================================================================
// KEYWORDS : N/A
// ----------------------------------------------------------------------------
// PURPOSE : MAC core output 8bit pkt format transform 134bit pkt format
// ----------------------------------------------------------------------------
// ============================================================================
// REUSE ISSUES
// Reset Strategy : Async clear,active high
// Clock Domains : ff_rx_clk
// Critical TiminG : N/A
// Instantiations : N/A
// Synthesizable : N/A
// Others : N/A
// ****************************************************************************
module SGMII_RX1
(reset,
ff_rx_clk,
ff_rx_rdy,
ff_rx_data,
ff_rx_sop,
ff_rx_eop,
rx_err,
rx_err_stat,
rx_frm_type,
ff_rx_dsav,
ff_rx_dval,
ff_rx_a_full,
ff_rx_a_empty,
pkt_receive_add,
pkt_discard_add,
out_pkt_wrreq,
out_pkt,
out_pkt_almostfull,
out_valid_wrreq,
out_valid
);
input reset;
input ff_rx_clk;
output ff_rx_rdy;
input [7:0] ff_rx_data;
input ff_rx_sop;
input ff_rx_eop;
input [5:0] rx_err;
input [17:0] rx_err_stat;
input [3:0] rx_frm_type;
input ff_rx_dsav;
input ff_rx_dval;
input ff_rx_a_full;
input ff_rx_a_empty;
output pkt_receive_add;
output pkt_discard_add;
output out_pkt_wrreq;
output [133:0] out_pkt;
input out_pkt_almostfull;
output out_valid_wrreq;
output out_valid;
reg ff_rx_rdy;
reg pkt_receive_add;
reg pkt_discard_add;
reg out_pkt_wrreq;
reg [133:0] out_pkt;
reg out_valid_wrreq;
reg out_valid;
reg [4:0]current_state;
parameter //idle_s = 5'b00000,
transmit_byte0_s = 5'b00001,
transmit_byte1_s = 5'b00010,
transmit_byte2_s = 5'b00011,
transmit_byte3_s = 5'b00100,
transmit_byte4_s = 5'b00101,
transmit_byte5_s = 5'b00110,
transmit_byte6_s = 5'b00111,
transmit_byte7_s = 5'b01000,
transmit_byte8_s = 5'b01001,
transmit_byte9_s = 5'b01010,
transmit_byte10_s = 5'b01011,
transmit_byte11_s = 5'b01100,
transmit_byte12_s = 5'b01101,
transmit_byte13_s = 5'b01110,
transmit_byte14_s = 5'b01111,
transmit_byte15_s = 5'b10000,
discard_s = 5'b10001;
always@(posedge ff_rx_clk or negedge reset)
if(!reset) begin
ff_rx_rdy <= 1'b0;
out_pkt_wrreq <= 1'b0;
out_pkt <= 134'b0;
out_valid_wrreq <= 1'b0;
out_valid <= 1'b0;
pkt_receive_add <= 1'b0;
pkt_discard_add <= 1'b0;
current_state <= transmit_byte0_s;
end
else begin
ff_rx_rdy <= 1'b1;
case(current_state)
transmit_byte0_s: begin
out_valid_wrreq <= 1'b0;
out_valid <= 1'b0;
out_pkt_wrreq <= 1'b0;
if(ff_rx_dval == 1'b1) begin//data valid
out_pkt[127:120] <= ff_rx_data;
if(ff_rx_sop == 1'b1) begin //pkt head
if(!out_pkt_almostfull) begin//FIFO can receive a 1518B pkt
out_pkt[133:132] <= 2'b01;
pkt_receive_add <= 1'b1;
current_state <= transmit_byte1_s;
end
else begin
pkt_discard_add <= 1'b1;
current_state <= discard_s;
end
end
else if(ff_rx_eop == 1'b1) begin//pkt tail
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= 4'b1111;
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin//pkt error
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte1_s;
end
end
else begin
current_state <= transmit_byte0_s;
end
end
transmit_byte1_s: begin
out_pkt_wrreq <= 1'b0;
pkt_receive_add <= 1'b0;
if(ff_rx_dval == 1'b1) begin//data valid
out_pkt[119:112] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin//pkt head
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= 4'b1110;
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin//pkt error
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
//out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte2_s;
end
end
else begin
current_state <= transmit_byte1_s;
end
end
transmit_byte2_s: begin
out_pkt_wrreq <= 1'b0;
if(ff_rx_dval == 1'b1) begin
out_pkt[111:104] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= 4'b1101;
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
//out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte3_s;
end
end
else begin
current_state <= transmit_byte2_s;
end
end
transmit_byte3_s: begin
out_pkt_wrreq <= 1'b0;
if(ff_rx_dval == 1'b1) begin
out_pkt[103:96] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= 4'b1100;
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
//out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte4_s;
end
end
else begin
current_state <= transmit_byte3_s;
end
end
transmit_byte4_s: begin
out_pkt_wrreq <= 1'b0;
if(ff_rx_dval == 1'b1) begin
out_pkt[95:88] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= 4'b1011;
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
//out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte5_s;
end
end
else begin
current_state <= transmit_byte4_s;
end
end
transmit_byte5_s: begin
out_pkt_wrreq <= 1'b0;
if(ff_rx_dval == 1'b1) begin
out_pkt[87:80] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= 4'b1010;
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
//out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte6_s;
end
end
else begin
current_state <= transmit_byte5_s;
end
end
transmit_byte6_s: begin
out_pkt_wrreq <= 1'b0;
if(ff_rx_dval == 1'b1) begin
out_pkt[79:72] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= 4'b1001;
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
//out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte7_s;
end
end
else begin
current_state <= transmit_byte6_s;
end
end
transmit_byte7_s: begin
out_pkt_wrreq <= 1'b0;
if(ff_rx_dval == 1'b1) begin
out_pkt[71:64] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= 4'b1000;
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
//out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte8_s;
end
end
else begin
current_state <= transmit_byte7_s;
end
end
transmit_byte8_s: begin
out_pkt_wrreq <= 1'b0;
if(ff_rx_dval == 1'b1) begin
out_pkt[63:56] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= 4'b0111;
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
//out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte9_s;
end
end
else begin
current_state <= transmit_byte8_s;
end
end
transmit_byte9_s: begin
out_pkt_wrreq <= 1'b0;
if(ff_rx_dval == 1'b1) begin
out_pkt[55:48] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= 4'b0110;
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
//out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte10_s;
end
end
else begin
current_state <= transmit_byte9_s;
end
end
transmit_byte10_s: begin
out_pkt_wrreq <= 1'b0;
if(ff_rx_dval == 1'b1) begin
out_pkt[47:40] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= 4'b0101;
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
//out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte11_s;
end
end
else begin
current_state <= transmit_byte10_s;
end
end
transmit_byte11_s: begin
out_pkt_wrreq <= 1'b0;
if(ff_rx_dval == 1'b1) begin
out_pkt[39:32] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= 4'b0100;
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
//out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte12_s;
end
end
else begin
current_state <= transmit_byte11_s;
end
end
transmit_byte12_s: begin
out_pkt_wrreq <= 1'b0;
if(ff_rx_dval == 1'b1) begin
out_pkt[31:24] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= 4'b0011;
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
//out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte13_s;
end
end
else begin
current_state <= transmit_byte12_s;
end
end
transmit_byte13_s: begin
out_pkt_wrreq <= 1'b0;
if(ff_rx_dval == 1'b1) begin
out_pkt[23:16] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= 4'b0010;
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
//out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte14_s;
end
end
else begin
current_state <= transmit_byte13_s;
end
end
transmit_byte14_s: begin
out_pkt_wrreq <= 1'b0;
if(ff_rx_dval == 1'b1) begin
out_pkt[15:8] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= 4'b0001;
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
//out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte15_s;
end
end
else begin
current_state <= transmit_byte14_s;
end
end
transmit_byte15_s: begin
if(ff_rx_dval == 1'b1) begin
out_pkt_wrreq <= 1'b1;
out_pkt[7:0] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= 4'b0000;
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
//out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte0_s;
end
end
else begin
current_state <= transmit_byte15_s;
end
end
discard_s:begin
out_pkt_wrreq <= 1'b0;
pkt_discard_add <= 1'b0;
if((ff_rx_dval == 1'b1)&&(ff_rx_eop == 1'b1))begin
current_state <= transmit_byte0_s;
end
else begin
current_state <= discard_s;
end
end
endcase
end
endmodule |
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.20131013
// \ \ Application: netgen
// / / Filename: sub9.v
// /___/ /\ Timestamp: Sun Apr 19 20:46:16 2015
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog /home/vka/Programming/VHDL/workspace/sysrek/skin_color_segm/ipcore_dir/tmp/_cg/sub9.ngc /home/vka/Programming/VHDL/workspace/sysrek/skin_color_segm/ipcore_dir/tmp/_cg/sub9.v
// Device : 6slx45csg324-2
// Input file : /home/vka/Programming/VHDL/workspace/sysrek/skin_color_segm/ipcore_dir/tmp/_cg/sub9.ngc
// Output file : /home/vka/Programming/VHDL/workspace/sysrek/skin_color_segm/ipcore_dir/tmp/_cg/sub9.v
// # of Modules : 1
// Design Name : sub9
// Xilinx : /mnt/data/Xilinx/14.7/ISE_DS/ISE/
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module sub9 (
clk, ce, a, b, s
)/* synthesis syn_black_box syn_noprune=1 */;
input clk;
input ce;
input [8 : 0] a;
input [8 : 0] b;
output [8 : 0] s;
// synthesis translate_off
wire \blk00000001/sig00000051 ;
wire \blk00000001/sig00000050 ;
wire \blk00000001/sig0000004f ;
wire \blk00000001/sig0000004e ;
wire \blk00000001/sig0000004d ;
wire \blk00000001/sig0000004c ;
wire \blk00000001/sig0000004b ;
wire \blk00000001/sig0000004a ;
wire \blk00000001/sig00000049 ;
wire \blk00000001/sig00000048 ;
wire \blk00000001/sig00000047 ;
wire \blk00000001/sig00000046 ;
wire \blk00000001/sig00000045 ;
wire \blk00000001/sig00000044 ;
wire \blk00000001/sig00000043 ;
wire \blk00000001/sig00000042 ;
wire \blk00000001/sig00000041 ;
wire \blk00000001/sig00000040 ;
wire \blk00000001/sig0000003f ;
wire \blk00000001/sig0000003e ;
wire \blk00000001/sig0000003d ;
wire \blk00000001/sig0000003c ;
wire \blk00000001/sig0000003b ;
wire \blk00000001/sig0000003a ;
wire \blk00000001/sig00000039 ;
wire \blk00000001/sig00000038 ;
wire \blk00000001/sig00000037 ;
wire \blk00000001/sig00000036 ;
wire \blk00000001/sig00000035 ;
wire \blk00000001/sig00000034 ;
wire \blk00000001/sig00000033 ;
wire \blk00000001/sig00000032 ;
wire \blk00000001/sig00000031 ;
wire \blk00000001/sig00000030 ;
wire \blk00000001/sig0000002f ;
wire \blk00000001/sig0000002e ;
wire \blk00000001/sig0000002d ;
wire \blk00000001/sig0000002c ;
wire \blk00000001/sig0000002b ;
wire \blk00000001/sig0000002a ;
wire \blk00000001/sig00000029 ;
wire \blk00000001/sig00000028 ;
wire \blk00000001/sig00000027 ;
wire \blk00000001/sig00000026 ;
wire \blk00000001/sig00000025 ;
wire \blk00000001/sig00000024 ;
wire \blk00000001/sig00000023 ;
wire \blk00000001/sig00000022 ;
wire \blk00000001/sig00000021 ;
wire \blk00000001/sig00000020 ;
wire \blk00000001/sig0000001f ;
wire \blk00000001/sig0000001e ;
wire \NLW_blk00000001/blk0000003e_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003c_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003a_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000038_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000021_O_UNCONNECTED ;
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000003f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000051 ),
.Q(s[0])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000003e (
.A0(\blk00000001/sig0000004d ),
.A1(\blk00000001/sig0000004d ),
.A2(\blk00000001/sig0000004d ),
.A3(\blk00000001/sig0000004d ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000025 ),
.Q(\blk00000001/sig00000051 ),
.Q15(\NLW_blk00000001/blk0000003e_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000003d (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000050 ),
.Q(s[1])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000003c (
.A0(\blk00000001/sig0000004d ),
.A1(\blk00000001/sig0000004d ),
.A2(\blk00000001/sig0000004d ),
.A3(\blk00000001/sig0000004d ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000028 ),
.Q(\blk00000001/sig00000050 ),
.Q15(\NLW_blk00000001/blk0000003c_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000003b (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000004f ),
.Q(s[2])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000003a (
.A0(\blk00000001/sig0000004d ),
.A1(\blk00000001/sig0000004d ),
.A2(\blk00000001/sig0000004d ),
.A3(\blk00000001/sig0000004d ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000027 ),
.Q(\blk00000001/sig0000004f ),
.Q15(\NLW_blk00000001/blk0000003a_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000039 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000004e ),
.Q(s[3])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000038 (
.A0(\blk00000001/sig0000004d ),
.A1(\blk00000001/sig0000004d ),
.A2(\blk00000001/sig0000004d ),
.A3(\blk00000001/sig0000004d ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000026 ),
.Q(\blk00000001/sig0000004e ),
.Q15(\NLW_blk00000001/blk00000038_Q15_UNCONNECTED )
);
GND \blk00000001/blk00000037 (
.G(\blk00000001/sig0000004d )
);
INV \blk00000001/blk00000036 (
.I(\blk00000001/sig00000023 ),
.O(\blk00000001/sig00000049 )
);
INV \blk00000001/blk00000035 (
.I(\blk00000001/sig00000022 ),
.O(\blk00000001/sig00000046 )
);
INV \blk00000001/blk00000034 (
.I(\blk00000001/sig00000021 ),
.O(\blk00000001/sig00000047 )
);
INV \blk00000001/blk00000033 (
.I(\blk00000001/sig00000020 ),
.O(\blk00000001/sig00000048 )
);
INV \blk00000001/blk00000032 (
.I(\blk00000001/sig0000001f ),
.O(\blk00000001/sig0000004a )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk00000031 (
.I0(a[8]),
.I1(b[8]),
.O(\blk00000001/sig00000039 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk00000030 (
.I0(a[7]),
.I1(b[7]),
.O(\blk00000001/sig00000036 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk0000002f (
.I0(a[6]),
.I1(b[6]),
.O(\blk00000001/sig00000037 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk0000002e (
.I0(a[5]),
.I1(b[5]),
.O(\blk00000001/sig00000038 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk0000002d (
.I0(a[4]),
.I1(b[4]),
.O(\blk00000001/sig0000003a )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk0000002c (
.I0(a[3]),
.I1(b[3]),
.O(\blk00000001/sig0000002b )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk0000002b (
.I0(a[2]),
.I1(b[2]),
.O(\blk00000001/sig00000029 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk0000002a (
.I0(a[1]),
.I1(b[1]),
.O(\blk00000001/sig0000002a )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk00000029 (
.I0(a[0]),
.I1(b[0]),
.O(\blk00000001/sig0000002c )
);
MUXCY \blk00000001/blk00000028 (
.CI(\blk00000001/sig00000024 ),
.DI(\blk00000001/sig0000001e ),
.S(\blk00000001/sig0000004a ),
.O(\blk00000001/sig0000004c )
);
XORCY \blk00000001/blk00000027 (
.CI(\blk00000001/sig00000024 ),
.LI(\blk00000001/sig0000004a ),
.O(\blk00000001/sig0000004b )
);
MUXCY \blk00000001/blk00000026 (
.CI(\blk00000001/sig0000004c ),
.DI(\blk00000001/sig0000001e ),
.S(\blk00000001/sig00000048 ),
.O(\blk00000001/sig00000045 )
);
XORCY \blk00000001/blk00000025 (
.CI(\blk00000001/sig0000004c ),
.LI(\blk00000001/sig00000048 ),
.O(\blk00000001/sig00000044 )
);
MUXCY \blk00000001/blk00000024 (
.CI(\blk00000001/sig00000045 ),
.DI(\blk00000001/sig0000001e ),
.S(\blk00000001/sig00000047 ),
.O(\blk00000001/sig00000043 )
);
XORCY \blk00000001/blk00000023 (
.CI(\blk00000001/sig00000045 ),
.LI(\blk00000001/sig00000047 ),
.O(\blk00000001/sig00000042 )
);
XORCY \blk00000001/blk00000022 (
.CI(\blk00000001/sig00000040 ),
.LI(\blk00000001/sig00000049 ),
.O(\blk00000001/sig00000041 )
);
MUXCY \blk00000001/blk00000021 (
.CI(\blk00000001/sig00000040 ),
.DI(\blk00000001/sig0000001e ),
.S(\blk00000001/sig00000049 ),
.O(\NLW_blk00000001/blk00000021_O_UNCONNECTED )
);
MUXCY \blk00000001/blk00000020 (
.CI(\blk00000001/sig00000043 ),
.DI(\blk00000001/sig0000001e ),
.S(\blk00000001/sig00000046 ),
.O(\blk00000001/sig00000040 )
);
XORCY \blk00000001/blk0000001f (
.CI(\blk00000001/sig00000043 ),
.LI(\blk00000001/sig00000046 ),
.O(\blk00000001/sig0000003f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000041 ),
.Q(s[8])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001d (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000003f ),
.Q(s[7])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000042 ),
.Q(s[6])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001b (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000044 ),
.Q(s[5])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000004b ),
.Q(s[4])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000019 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000031 ),
.Q(\blk00000001/sig0000001f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000018 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000035 ),
.Q(\blk00000001/sig00000020 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000017 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000034 ),
.Q(\blk00000001/sig00000021 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000016 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000033 ),
.Q(\blk00000001/sig00000022 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000015 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000032 ),
.Q(\blk00000001/sig00000023 )
);
MUXCY \blk00000001/blk00000014 (
.CI(\blk00000001/sig0000001e ),
.DI(a[4]),
.S(\blk00000001/sig0000003a ),
.O(\blk00000001/sig0000003e )
);
MUXCY \blk00000001/blk00000013 (
.CI(\blk00000001/sig0000003e ),
.DI(a[5]),
.S(\blk00000001/sig00000038 ),
.O(\blk00000001/sig0000003d )
);
MUXCY \blk00000001/blk00000012 (
.CI(\blk00000001/sig0000003d ),
.DI(a[6]),
.S(\blk00000001/sig00000037 ),
.O(\blk00000001/sig0000003c )
);
MUXCY \blk00000001/blk00000011 (
.CI(\blk00000001/sig0000003c ),
.DI(a[7]),
.S(\blk00000001/sig00000036 ),
.O(\blk00000001/sig0000003b )
);
XORCY \blk00000001/blk00000010 (
.CI(\blk00000001/sig0000003e ),
.LI(\blk00000001/sig00000038 ),
.O(\blk00000001/sig00000035 )
);
XORCY \blk00000001/blk0000000f (
.CI(\blk00000001/sig0000003d ),
.LI(\blk00000001/sig00000037 ),
.O(\blk00000001/sig00000034 )
);
XORCY \blk00000001/blk0000000e (
.CI(\blk00000001/sig0000003c ),
.LI(\blk00000001/sig00000036 ),
.O(\blk00000001/sig00000033 )
);
XORCY \blk00000001/blk0000000d (
.CI(\blk00000001/sig0000003b ),
.LI(\blk00000001/sig00000039 ),
.O(\blk00000001/sig00000032 )
);
XORCY \blk00000001/blk0000000c (
.CI(\blk00000001/sig0000001e ),
.LI(\blk00000001/sig0000003a ),
.O(\blk00000001/sig00000031 )
);
FDE #(
.INIT ( 1'b1 ))
\blk00000001/blk0000000b (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000002f ),
.Q(\blk00000001/sig00000024 )
);
MUXCY \blk00000001/blk0000000a (
.CI(\blk00000001/sig0000001e ),
.DI(a[0]),
.S(\blk00000001/sig0000002c ),
.O(\blk00000001/sig00000030 )
);
MUXCY \blk00000001/blk00000009 (
.CI(\blk00000001/sig0000002d ),
.DI(a[3]),
.S(\blk00000001/sig0000002b ),
.O(\blk00000001/sig0000002f )
);
MUXCY \blk00000001/blk00000008 (
.CI(\blk00000001/sig00000030 ),
.DI(a[1]),
.S(\blk00000001/sig0000002a ),
.O(\blk00000001/sig0000002e )
);
MUXCY \blk00000001/blk00000007 (
.CI(\blk00000001/sig0000002e ),
.DI(a[2]),
.S(\blk00000001/sig00000029 ),
.O(\blk00000001/sig0000002d )
);
XORCY \blk00000001/blk00000006 (
.CI(\blk00000001/sig00000030 ),
.LI(\blk00000001/sig0000002a ),
.O(\blk00000001/sig00000028 )
);
XORCY \blk00000001/blk00000005 (
.CI(\blk00000001/sig0000002e ),
.LI(\blk00000001/sig00000029 ),
.O(\blk00000001/sig00000027 )
);
XORCY \blk00000001/blk00000004 (
.CI(\blk00000001/sig0000002d ),
.LI(\blk00000001/sig0000002b ),
.O(\blk00000001/sig00000026 )
);
XORCY \blk00000001/blk00000003 (
.CI(\blk00000001/sig0000001e ),
.LI(\blk00000001/sig0000002c ),
.O(\blk00000001/sig00000025 )
);
VCC \blk00000001/blk00000002 (
.P(\blk00000001/sig0000001e )
);
// synthesis translate_on
endmodule
// synthesis translate_off
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
// synthesis translate_on
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: digilentinc.com:ip:pmod_bridge:1.0
// IP Revision: 6
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module PmodJSTK_pmod_bridge_0_0 (
in0_I,
in1_I,
in2_I,
in3_I,
in0_O,
in1_O,
in2_O,
in3_O,
in0_T,
in1_T,
in2_T,
in3_T,
out0_I,
out1_I,
out2_I,
out3_I,
out4_I,
out5_I,
out6_I,
out7_I,
out0_O,
out1_O,
out2_O,
out3_O,
out4_O,
out5_O,
out6_O,
out7_O,
out0_T,
out1_T,
out2_T,
out3_T,
out4_T,
out5_T,
out6_T,
out7_T
);
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row SS_I" *)
output wire in0_I;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row IO0_I" *)
output wire in1_I;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row IO1_I" *)
output wire in2_I;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row SCK_I" *)
output wire in3_I;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row SS_O" *)
input wire in0_O;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row IO0_O" *)
input wire in1_O;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row IO1_O" *)
input wire in2_O;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row SCK_O" *)
input wire in3_O;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row SS_T" *)
input wire in0_T;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row IO0_T" *)
input wire in1_T;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row IO1_T" *)
input wire in2_T;
(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_Top_Row SCK_T" *)
input wire in3_T;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN1_I" *)
input wire out0_I;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN2_I" *)
input wire out1_I;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN3_I" *)
input wire out2_I;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN4_I" *)
input wire out3_I;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN7_I" *)
input wire out4_I;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN8_I" *)
input wire out5_I;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN9_I" *)
input wire out6_I;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN10_I" *)
input wire out7_I;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN1_O" *)
output wire out0_O;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN2_O" *)
output wire out1_O;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN3_O" *)
output wire out2_O;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN4_O" *)
output wire out3_O;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN7_O" *)
output wire out4_O;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN8_O" *)
output wire out5_O;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN9_O" *)
output wire out6_O;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN10_O" *)
output wire out7_O;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN1_T" *)
output wire out0_T;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN2_T" *)
output wire out1_T;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN3_T" *)
output wire out2_T;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN4_T" *)
output wire out3_T;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN7_T" *)
output wire out4_T;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN8_T" *)
output wire out5_T;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN9_T" *)
output wire out6_T;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out PIN10_T" *)
output wire out7_T;
pmod_concat #(
.Top_Row_Interface("SPI"),
.Bottom_Row_Interface("Disabled")
) inst (
.in_top_bus_I(),
.in_top_bus_O(4'B0),
.in_top_bus_T(4'B0),
.in_top_uart_gpio_bus_I(),
.in_top_uart_gpio_bus_O(2'B1),
.in_top_uart_gpio_bus_T(2'B1),
.in_top_i2c_gpio_bus_I(),
.in_top_i2c_gpio_bus_O(2'B1),
.in_top_i2c_gpio_bus_T(2'B1),
.in_bottom_bus_I(),
.in_bottom_bus_O(4'B1),
.in_bottom_bus_T(4'B1),
.in_bottom_uart_gpio_bus_I(),
.in_bottom_uart_gpio_bus_O(2'B1),
.in_bottom_uart_gpio_bus_T(2'B1),
.in_bottom_i2c_gpio_bus_I(),
.in_bottom_i2c_gpio_bus_O(2'B1),
.in_bottom_i2c_gpio_bus_T(2'B1),
.in0_I(in0_I),
.in1_I(in1_I),
.in2_I(in2_I),
.in3_I(in3_I),
.in4_I(),
.in5_I(),
.in6_I(),
.in7_I(),
.in0_O(in0_O),
.in1_O(in1_O),
.in2_O(in2_O),
.in3_O(in3_O),
.in4_O(1'B1),
.in5_O(1'B1),
.in6_O(1'B1),
.in7_O(1'B1),
.in0_T(in0_T),
.in1_T(in1_T),
.in2_T(in2_T),
.in3_T(in3_T),
.in4_T(1'B1),
.in5_T(1'B1),
.in6_T(1'B1),
.in7_T(1'B1),
.out0_I(out0_I),
.out1_I(out1_I),
.out2_I(out2_I),
.out3_I(out3_I),
.out4_I(out4_I),
.out5_I(out5_I),
.out6_I(out6_I),
.out7_I(out7_I),
.out0_O(out0_O),
.out1_O(out1_O),
.out2_O(out2_O),
.out3_O(out3_O),
.out4_O(out4_O),
.out5_O(out5_O),
.out6_O(out6_O),
.out7_O(out7_O),
.out0_T(out0_T),
.out1_T(out1_T),
.out2_T(out2_T),
.out3_T(out3_T),
.out4_T(out4_T),
.out5_T(out5_T),
.out6_T(out6_T),
.out7_T(out7_T)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A22OI_4_V
`define SKY130_FD_SC_HD__A22OI_4_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a22oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a22oi_4 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a22oi_4 (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A22OI_4_V
|
/******************************************************************************
-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
*****************************************************************************
*
* Filename: BLK_MEM_GEN_v8_2.v
*
* Description:
* This file is the Verilog behvarial model for the
* Block Memory Generator Core.
*
*****************************************************************************
* Author: Xilinx
*
* History: Jan 11, 2006 Initial revision
* Jun 11, 2007 Added independent register stages for
* Port A and Port B (IP1_Jm/v2.5)
* Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)
* Mar 13, 2008 Behavioral model optimizations
* April 07, 2009 : Added support for Spartan-6 and Virtex-6
* features, including the following:
* (i) error injection, detection and/or correction
* (ii) reset priority
* (iii) special reset behavior
*
*****************************************************************************/
`timescale 1ps/1ps
module STATE_LOGIC_v8_2 (O, I0, I1, I2, I3, I4, I5);
parameter INIT = 64'h0000000000000000;
input I0, I1, I2, I3, I4, I5;
output O;
reg O;
reg tmp;
always @( I5 or I4 or I3 or I2 or I1 or I0 ) begin
tmp = I0 ^ I1 ^ I2 ^ I3 ^ I4 ^ I5;
if ( tmp == 0 || tmp == 1)
O = INIT[{I5, I4, I3, I2, I1, I0}];
end
endmodule
module beh_vlog_muxf7_v8_2 (O, I0, I1, S);
output O;
reg O;
input I0, I1, S;
always @(I0 or I1 or S)
if (S)
O = I1;
else
O = I0;
endmodule
module beh_vlog_ff_clr_v8_2 (Q, C, CLR, D);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, CLR, D;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (CLR)
Q<= 1'b0;
else
Q<= #FLOP_DELAY D;
endmodule
module beh_vlog_ff_pre_v8_2 (Q, C, D, PRE);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, D, PRE;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (PRE)
Q <= 1'b1;
else
Q <= #FLOP_DELAY D;
endmodule
module beh_vlog_ff_ce_clr_v8_2 (Q, C, CE, CLR, D);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, CE, CLR, D;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (CLR)
Q <= 1'b0;
else if (CE)
Q <= #FLOP_DELAY D;
endmodule
module write_netlist_v8_2
#(
parameter C_AXI_TYPE = 0
)
(
S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,
w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,
S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c
);
input S_ACLK;
input S_ARESETN;
input S_AXI_AWVALID;
input S_AXI_WVALID;
input S_AXI_BREADY;
input w_last_c;
input bready_timeout_c;
output aw_ready_r;
output S_AXI_WREADY;
output S_AXI_BVALID;
output S_AXI_WR_EN;
output addr_en_c;
output incr_addr_c;
output bvalid_c;
//-------------------------------------------------------------------------
//AXI LITE
//-------------------------------------------------------------------------
generate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm
wire w_ready_r_7;
wire w_ready_c;
wire aw_ready_c;
wire NlwRenamedSignal_bvalid_c;
wire NlwRenamedSignal_incr_addr_c;
wire present_state_FSM_FFd3_13;
wire present_state_FSM_FFd2_14;
wire present_state_FSM_FFd1_15;
wire present_state_FSM_FFd4_16;
wire present_state_FSM_FFd4_In;
wire present_state_FSM_FFd3_In;
wire present_state_FSM_FFd2_In;
wire present_state_FSM_FFd1_In;
wire present_state_FSM_FFd4_In1_21;
wire [0:0] Mmux_aw_ready_c ;
begin
assign
S_AXI_WREADY = w_ready_r_7,
S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,
S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,
incr_addr_c = NlwRenamedSignal_incr_addr_c,
bvalid_c = NlwRenamedSignal_bvalid_c;
assign NlwRenamedSignal_incr_addr_c = 1'b0;
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
aw_ready_r_2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( aw_ready_c),
.Q ( aw_ready_r)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
w_ready_r (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( w_ready_c),
.Q ( w_ready_r_7)
);
beh_vlog_ff_pre_v8_2 #(
.INIT (1'b1))
present_state_FSM_FFd4 (
.C ( S_ACLK),
.D ( present_state_FSM_FFd4_In),
.PRE ( S_ARESETN),
.Q ( present_state_FSM_FFd4_16)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd3 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd3_In),
.Q ( present_state_FSM_FFd3_13)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_14)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd1 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd1_In),
.Q ( present_state_FSM_FFd1_15)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000055554440))
present_state_FSM_FFd3_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( S_AXI_AWVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd4_16),
.I4 ( present_state_FSM_FFd3_13),
.I5 (1'b0),
.O ( present_state_FSM_FFd3_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000088880800))
present_state_FSM_FFd2_In1 (
.I0 ( S_AXI_AWVALID),
.I1 ( S_AXI_WVALID),
.I2 ( bready_timeout_c),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( present_state_FSM_FFd4_16),
.I5 (1'b0),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000AAAA2000))
Mmux_addr_en_c_0_1 (
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( S_AXI_WVALID),
.I4 ( present_state_FSM_FFd4_16),
.I5 (1'b0),
.O ( addr_en_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hF5F07570F5F05500))
Mmux_w_ready_c_0_1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_13),
.I4 ( present_state_FSM_FFd4_16),
.I5 ( present_state_FSM_FFd2_14),
.O ( w_ready_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h88808880FFFF8880))
present_state_FSM_FFd1_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd3_13),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( present_state_FSM_FFd1_15),
.I5 ( S_AXI_BREADY),
.O ( present_state_FSM_FFd1_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000000000A8))
Mmux_S_AXI_WR_EN_0_1 (
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd2_14),
.I2 ( present_state_FSM_FFd3_13),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( NlwRenamedSignal_bvalid_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h2F0F27072F0F2200))
present_state_FSM_FFd4_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_13),
.I4 ( present_state_FSM_FFd4_16),
.I5 ( present_state_FSM_FFd2_14),
.O ( present_state_FSM_FFd4_In1_21)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000000000F8))
present_state_FSM_FFd4_In2 (
.I0 ( present_state_FSM_FFd1_15),
.I1 ( S_AXI_BREADY),
.I2 ( present_state_FSM_FFd4_In1_21),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd4_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h7535753575305500))
Mmux_aw_ready_c_0_1 (
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_WVALID),
.I3 ( present_state_FSM_FFd4_16),
.I4 ( present_state_FSM_FFd3_13),
.I5 ( present_state_FSM_FFd2_14),
.O ( Mmux_aw_ready_c[0])
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000000000F8))
Mmux_aw_ready_c_0_2 (
.I0 ( present_state_FSM_FFd1_15),
.I1 ( S_AXI_BREADY),
.I2 ( Mmux_aw_ready_c[0]),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( aw_ready_c)
);
end
end
endgenerate
//---------------------------------------------------------------------
// AXI FULL
//---------------------------------------------------------------------
generate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm
wire w_ready_r_8;
wire w_ready_c;
wire aw_ready_c;
wire NlwRenamedSig_OI_bvalid_c;
wire present_state_FSM_FFd1_16;
wire present_state_FSM_FFd4_17;
wire present_state_FSM_FFd3_18;
wire present_state_FSM_FFd2_19;
wire present_state_FSM_FFd4_In;
wire present_state_FSM_FFd3_In;
wire present_state_FSM_FFd2_In;
wire present_state_FSM_FFd1_In;
wire present_state_FSM_FFd2_In1_24;
wire present_state_FSM_FFd4_In1_25;
wire N2;
wire N4;
begin
assign
S_AXI_WREADY = w_ready_r_8,
bvalid_c = NlwRenamedSig_OI_bvalid_c,
S_AXI_BVALID = 1'b0;
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
aw_ready_r_2
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( aw_ready_c),
.Q ( aw_ready_r)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
w_ready_r
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( w_ready_c),
.Q ( w_ready_r_8)
);
beh_vlog_ff_pre_v8_2 #(
.INIT (1'b1))
present_state_FSM_FFd4
(
.C ( S_ACLK),
.D ( present_state_FSM_FFd4_In),
.PRE ( S_ARESETN),
.Q ( present_state_FSM_FFd4_17)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd3
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd3_In),
.Q ( present_state_FSM_FFd3_18)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd2
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_19)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd1
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd1_In),
.Q ( present_state_FSM_FFd1_16)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000005540))
present_state_FSM_FFd3_In1
(
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd4_17),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd3_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hBF3FBB33AF0FAA00))
Mmux_aw_ready_c_0_2
(
.I0 ( S_AXI_BREADY),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd1_16),
.I4 ( present_state_FSM_FFd4_17),
.I5 ( NlwRenamedSig_OI_bvalid_c),
.O ( aw_ready_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hAAAAAAAA20000000))
Mmux_addr_en_c_0_1
(
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( S_AXI_WVALID),
.I4 ( w_last_c),
.I5 ( present_state_FSM_FFd4_17),
.O ( addr_en_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000000000A8))
Mmux_S_AXI_WR_EN_0_1
(
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd2_19),
.I2 ( present_state_FSM_FFd3_18),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( S_AXI_WR_EN)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000002220))
Mmux_incr_addr_c_0_1
(
.I0 ( S_AXI_WVALID),
.I1 ( w_last_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( incr_addr_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000008880))
Mmux_aw_ready_c_0_11
(
.I0 ( S_AXI_WVALID),
.I1 ( w_last_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( NlwRenamedSig_OI_bvalid_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h000000000000D5C0))
present_state_FSM_FFd2_In1
(
.I0 ( w_last_c),
.I1 ( S_AXI_AWVALID),
.I2 ( present_state_FSM_FFd4_17),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd2_In1_24)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hFFFFAAAA08AAAAAA))
present_state_FSM_FFd2_In2
(
.I0 ( present_state_FSM_FFd2_19),
.I1 ( S_AXI_AWVALID),
.I2 ( bready_timeout_c),
.I3 ( w_last_c),
.I4 ( S_AXI_WVALID),
.I5 ( present_state_FSM_FFd2_In1_24),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00C0004000C00000))
present_state_FSM_FFd4_In1
(
.I0 ( S_AXI_AWVALID),
.I1 ( w_last_c),
.I2 ( S_AXI_WVALID),
.I3 ( bready_timeout_c),
.I4 ( present_state_FSM_FFd3_18),
.I5 ( present_state_FSM_FFd2_19),
.O ( present_state_FSM_FFd4_In1_25)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000FFFF88F8))
present_state_FSM_FFd4_In2
(
.I0 ( present_state_FSM_FFd1_16),
.I1 ( S_AXI_BREADY),
.I2 ( present_state_FSM_FFd4_17),
.I3 ( S_AXI_AWVALID),
.I4 ( present_state_FSM_FFd4_In1_25),
.I5 (1'b0),
.O ( present_state_FSM_FFd4_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000000007))
Mmux_w_ready_c_0_SW0
(
.I0 ( w_last_c),
.I1 ( S_AXI_WVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( N2)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hFABAFABAFAAAF000))
Mmux_w_ready_c_0_Q
(
.I0 ( N2),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd4_17),
.I4 ( present_state_FSM_FFd3_18),
.I5 ( present_state_FSM_FFd2_19),
.O ( w_ready_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000000008))
Mmux_aw_ready_c_0_11_SW0
(
.I0 ( bready_timeout_c),
.I1 ( S_AXI_WVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( N4)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h88808880FFFF8880))
present_state_FSM_FFd1_In1
(
.I0 ( w_last_c),
.I1 ( N4),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 ( present_state_FSM_FFd1_16),
.I5 ( S_AXI_BREADY),
.O ( present_state_FSM_FFd1_In)
);
end
end
endgenerate
endmodule
module read_netlist_v8_2 #(
parameter C_AXI_TYPE = 1,
parameter C_ADDRB_WIDTH = 12
) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,
S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,
S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,
S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);
input S_AXI_R_LAST_INT;
input S_ACLK;
input S_ARESETN;
input S_AXI_ARVALID;
input S_AXI_RREADY;
output S_AXI_INCR_ADDR;
output S_AXI_ADDR_EN;
output S_AXI_SINGLE_TRANS;
output S_AXI_MUX_SEL;
output S_AXI_R_LAST;
output S_AXI_ARREADY;
output S_AXI_RLAST;
output S_AXI_RVALID;
output S_AXI_RD_EN;
input [7:0] S_AXI_ARLEN;
wire present_state_FSM_FFd1_13 ;
wire present_state_FSM_FFd2_14 ;
wire gaxi_full_sm_outstanding_read_r_15 ;
wire gaxi_full_sm_ar_ready_r_16 ;
wire gaxi_full_sm_r_last_r_17 ;
wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ;
wire gaxi_full_sm_r_valid_c ;
wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ;
wire gaxi_full_sm_ar_ready_c ;
wire gaxi_full_sm_outstanding_read_c ;
wire NlwRenamedSig_OI_S_AXI_R_LAST ;
wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ;
wire present_state_FSM_FFd2_In ;
wire present_state_FSM_FFd1_In ;
wire Mmux_S_AXI_R_LAST13 ;
wire N01 ;
wire N2 ;
wire Mmux_gaxi_full_sm_ar_ready_c11 ;
wire N4 ;
wire N8 ;
wire N9 ;
wire N10 ;
wire N11 ;
wire N12 ;
wire N13 ;
assign
S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,
S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,
S_AXI_RLAST = gaxi_full_sm_r_last_r_17,
S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
gaxi_full_sm_outstanding_read_r (
.C (S_ACLK),
.CLR(S_ARESETN),
.D(gaxi_full_sm_outstanding_read_c),
.Q(gaxi_full_sm_outstanding_read_r_15)
);
beh_vlog_ff_ce_clr_v8_2 #(
.INIT (1'b0))
gaxi_full_sm_r_valid_r (
.C (S_ACLK),
.CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.CLR (S_ARESETN),
.D (gaxi_full_sm_r_valid_c),
.Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
gaxi_full_sm_ar_ready_r (
.C (S_ACLK),
.CLR (S_ARESETN),
.D (gaxi_full_sm_ar_ready_c),
.Q (gaxi_full_sm_ar_ready_r_16)
);
beh_vlog_ff_ce_clr_v8_2 #(
.INIT(1'b0))
gaxi_full_sm_r_last_r (
.C (S_ACLK),
.CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.CLR (S_ARESETN),
.D (NlwRenamedSig_OI_S_AXI_R_LAST),
.Q (gaxi_full_sm_r_last_r_17)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_14)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd1 (
.C (S_ACLK),
.CLR (S_ARESETN),
.D (present_state_FSM_FFd1_In),
.Q (present_state_FSM_FFd1_13)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h000000000000000B))
S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (
.I0 ( S_AXI_RREADY),
.I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000000008))
Mmux_S_AXI_SINGLE_TRANS11 (
.I0 (S_AXI_ARVALID),
.I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_SINGLE_TRANS)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000000004))
Mmux_S_AXI_ADDR_EN11 (
.I0 (present_state_FSM_FFd1_13),
.I1 (S_AXI_ARVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_ADDR_EN)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hECEE2022EEEE2022))
present_state_FSM_FFd2_In1 (
.I0 ( S_AXI_ARVALID),
.I1 ( present_state_FSM_FFd1_13),
.I2 ( S_AXI_RREADY),
.I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I4 ( present_state_FSM_FFd2_14),
.I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000044440444))
Mmux_S_AXI_R_LAST131 (
.I0 ( present_state_FSM_FFd1_13),
.I1 ( S_AXI_ARVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( S_AXI_RREADY),
.I5 (1'b0),
.O ( Mmux_S_AXI_R_LAST13)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h4000FFFF40004000))
Mmux_S_AXI_INCR_ADDR11 (
.I0 ( S_AXI_R_LAST_INT),
.I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd1_13),
.I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I5 ( Mmux_S_AXI_R_LAST13),
.O ( S_AXI_INCR_ADDR)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000000000FE))
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (
.I0 ( S_AXI_ARLEN[2]),
.I1 ( S_AXI_ARLEN[1]),
.I2 ( S_AXI_ARLEN[0]),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N01)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000000001))
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (
.I0 ( S_AXI_ARLEN[7]),
.I1 ( S_AXI_ARLEN[6]),
.I2 ( S_AXI_ARLEN[5]),
.I3 ( S_AXI_ARLEN[4]),
.I4 ( S_AXI_ARLEN[3]),
.I5 ( N01),
.O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000000007))
Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (
.I0 ( S_AXI_ARVALID),
.I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I2 ( 1'b0),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N2)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0020000002200200))
Mmux_gaxi_full_sm_outstanding_read_c1 (
.I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd1_13),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( gaxi_full_sm_outstanding_read_r_15),
.I5 ( N2),
.O ( gaxi_full_sm_outstanding_read_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000004555))
Mmux_gaxi_full_sm_ar_ready_c12 (
.I0 ( S_AXI_ARVALID),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( Mmux_gaxi_full_sm_ar_ready_c11)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000000000EF))
Mmux_S_AXI_R_LAST11_SW0 (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_RREADY),
.I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N4)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hFCAAFC0A00AA000A))
Mmux_S_AXI_R_LAST11 (
.I0 ( S_AXI_ARVALID),
.I1 ( gaxi_full_sm_outstanding_read_r_15),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd1_13),
.I4 ( N4),
.I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.O ( gaxi_full_sm_r_valid_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000AAAAAA08))
S_AXI_MUX_SEL1 (
.I0 (present_state_FSM_FFd1_13),
.I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 (S_AXI_RREADY),
.I3 (present_state_FSM_FFd2_14),
.I4 (gaxi_full_sm_outstanding_read_r_15),
.I5 (1'b0),
.O (S_AXI_MUX_SEL)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hF3F3F755A2A2A200))
Mmux_S_AXI_RD_EN11 (
.I0 ( present_state_FSM_FFd1_13),
.I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 ( S_AXI_RREADY),
.I3 ( gaxi_full_sm_outstanding_read_r_15),
.I4 ( present_state_FSM_FFd2_14),
.I5 ( S_AXI_ARVALID),
.O ( S_AXI_RD_EN)
);
beh_vlog_muxf7_v8_2 present_state_FSM_FFd1_In3 (
.I0 ( N8),
.I1 ( N9),
.S ( present_state_FSM_FFd1_13),
.O ( present_state_FSM_FFd1_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h000000005410F4F0))
present_state_FSM_FFd1_In3_F (
.I0 ( S_AXI_RREADY),
.I1 ( present_state_FSM_FFd2_14),
.I2 ( S_AXI_ARVALID),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I5 ( 1'b0),
.O ( N8)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000072FF7272))
present_state_FSM_FFd1_In3_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( S_AXI_R_LAST_INT),
.I2 ( gaxi_full_sm_outstanding_read_r_15),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N9)
);
beh_vlog_muxf7_v8_2 Mmux_gaxi_full_sm_ar_ready_c14 (
.I0 ( N10),
.I1 ( N11),
.S ( present_state_FSM_FFd1_13),
.O ( gaxi_full_sm_ar_ready_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000FFFF88A8))
Mmux_gaxi_full_sm_ar_ready_c14_F (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( Mmux_gaxi_full_sm_ar_ready_c11),
.I5 ( 1'b0),
.O ( N10)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h000000008D008D8D))
Mmux_gaxi_full_sm_ar_ready_c14_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( S_AXI_R_LAST_INT),
.I2 ( gaxi_full_sm_outstanding_read_r_15),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N11)
);
beh_vlog_muxf7_v8_2 Mmux_S_AXI_R_LAST1 (
.I0 ( N12),
.I1 ( N13),
.S ( present_state_FSM_FFd1_13),
.O ( NlwRenamedSig_OI_S_AXI_R_LAST)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000088088888))
Mmux_S_AXI_R_LAST1_F (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_ARVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N12)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000E400E4E4))
Mmux_S_AXI_R_LAST1_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( gaxi_full_sm_outstanding_read_r_15),
.I2 ( S_AXI_R_LAST_INT),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N13)
);
endmodule
module blk_mem_axi_write_wrapper_beh_v8_2
# (
// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0, // 0: Native Interface; 1: AXI Interface
parameter C_AXI_TYPE = 0, // 0: AXI Lite; 1: AXI Full;
parameter C_AXI_SLAVE_TYPE = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
parameter C_MEMORY_TYPE = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
parameter C_WRITE_DEPTH_A = 0,
parameter C_AXI_AWADDR_WIDTH = 32,
parameter C_ADDRA_WIDTH = 12,
parameter C_AXI_WDATA_WIDTH = 32,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
// AXI OUTSTANDING WRITES
parameter C_AXI_OS_WR = 2
)
(
// AXI Global Signals
input S_ACLK,
input S_ARESETN,
// AXI Full/Lite Slave Write Channel (write side)
input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,
input [8-1:0] S_AXI_AWLEN,
input [2:0] S_AXI_AWSIZE,
input [1:0] S_AXI_AWBURST,
input S_AXI_AWVALID,
output S_AXI_AWREADY,
input S_AXI_WVALID,
output S_AXI_WREADY,
output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,
output S_AXI_BVALID,
input S_AXI_BREADY,
// Signals for BMG interface
output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,
output S_AXI_WR_EN
);
localparam FLOP_DELAY = 100; // 100 ps
localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:
((C_AXI_WDATA_WIDTH==16)?1:
((C_AXI_WDATA_WIDTH==32)?2:
((C_AXI_WDATA_WIDTH==64)?3:
((C_AXI_WDATA_WIDTH==128)?4:
((C_AXI_WDATA_WIDTH==256)?5:0))))));
wire bvalid_c ;
reg bready_timeout_c = 0;
wire [1:0] bvalid_rd_cnt_c;
reg bvalid_r = 0;
reg [2:0] bvalid_count_r = 0;
reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;
reg [1:0] bvalid_wr_cnt_r = 0;
reg [1:0] bvalid_rd_cnt_r = 0;
wire w_last_c ;
wire addr_en_c ;
wire incr_addr_c ;
wire aw_ready_r ;
wire dec_alen_c ;
reg bvalid_d1_c = 0;
reg [7:0] awlen_cntr_r = 0;
reg [7:0] awlen_int = 0;
reg [1:0] awburst_int = 0;
integer total_bytes = 0;
integer wrap_boundary = 0;
integer wrap_base_addr = 0;
integer num_of_bytes_c = 0;
integer num_of_bytes_r = 0;
// Array to store BIDs
reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;
wire S_AXI_BVALID_axi_wr_fsm;
//-------------------------------------
//AXI WRITE FSM COMPONENT INSTANTIATION
//-------------------------------------
write_netlist_v8_2 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm
(
.S_ACLK(S_ACLK),
.S_ARESETN(S_ARESETN),
.S_AXI_AWVALID(S_AXI_AWVALID),
.aw_ready_r(aw_ready_r),
.S_AXI_WVALID(S_AXI_WVALID),
.S_AXI_WREADY(S_AXI_WREADY),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_WR_EN(S_AXI_WR_EN),
.w_last_c(w_last_c),
.bready_timeout_c(bready_timeout_c),
.addr_en_c(addr_en_c),
.incr_addr_c(incr_addr_c),
.bvalid_c(bvalid_c),
.S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm)
);
//Wrap Address boundary calculation
always@(*) begin
num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);
total_bytes = (num_of_bytes_r)*(awlen_int+1);
wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);
wrap_boundary = wrap_base_addr+total_bytes;
end
//-------------------------------------------------------------------------
// BMG address generation
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
awaddr_reg <= 0;
num_of_bytes_r <= 0;
awburst_int <= 0;
end else begin
if (addr_en_c == 1'b1) begin
awaddr_reg <= #FLOP_DELAY S_AXI_AWADDR ;
num_of_bytes_r <= num_of_bytes_c;
awburst_int <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);
end else if (incr_addr_c == 1'b1) begin
if (awburst_int == 2'b10) begin
if(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin
awaddr_reg <= wrap_base_addr;
end else begin
awaddr_reg <= awaddr_reg + num_of_bytes_r;
end
end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin
awaddr_reg <= awaddr_reg + num_of_bytes_r;
end
end
end
end
assign S_AXI_AWADDR_OUT = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);
//-------------------------------------------------------------------------
// AXI wlast generation
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
awlen_cntr_r <= 0;
awlen_int <= 0;
end else begin
if (addr_en_c == 1'b1) begin
awlen_int <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;
awlen_cntr_r <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;
end else if (dec_alen_c == 1'b1) begin
awlen_cntr_r <= #FLOP_DELAY awlen_cntr_r - 1 ;
end
end
end
assign w_last_c = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;
assign dec_alen_c = (incr_addr_c | w_last_c);
//-------------------------------------------------------------------------
// Generation of bvalid counter for outstanding transactions
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_count_r <= 0;
end else begin
// bvalid_count_r generation
if (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r ;
end else if (bvalid_c == 1'b1) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r + 1 ;
end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r - 1 ;
end
end
end
//-------------------------------------------------------------------------
// Generation of bvalid when BID is used
//-------------------------------------------------------------------------
generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_r <= 0;
bvalid_d1_c <= 0;
end else begin
// Delay the generation o bvalid_r for generation for BID
bvalid_d1_c <= bvalid_c;
//external bvalid signal generation
if (bvalid_d1_c == 1'b1) begin
bvalid_r <= #FLOP_DELAY 1'b1 ;
end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin
bvalid_r <= #FLOP_DELAY 0 ;
end
end
end
end
endgenerate
//-------------------------------------------------------------------------
// Generation of bvalid when BID is not used
//-------------------------------------------------------------------------
generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_r <= 0;
end else begin
//external bvalid signal generation
if (bvalid_c == 1'b1) begin
bvalid_r <= #FLOP_DELAY 1'b1 ;
end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin
bvalid_r <= #FLOP_DELAY 0 ;
end
end
end
end
endgenerate
//-------------------------------------------------------------------------
// Generation of Bready timeout
//-------------------------------------------------------------------------
always @(bvalid_count_r) begin
// bready_timeout_c generation
if(bvalid_count_r == C_AXI_OS_WR-1) begin
bready_timeout_c <= 1'b1;
end else begin
bready_timeout_c <= 1'b0;
end
end
//-------------------------------------------------------------------------
// Generation of BID
//-------------------------------------------------------------------------
generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_wr_cnt_r <= 0;
bvalid_rd_cnt_r <= 0;
end else begin
// STORE AWID IN AN ARRAY
if(bvalid_c == 1'b1) begin
bvalid_wr_cnt_r <= bvalid_wr_cnt_r + 1;
end
// generate BID FROM AWID ARRAY
bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;
S_AXI_BID <= axi_bid_array[bvalid_rd_cnt_c];
end
end
assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;
//-------------------------------------------------------------------------
// Storing AWID for generation of BID
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if(S_ARESETN == 1'b1) begin
axi_bid_array[0] = 0;
axi_bid_array[1] = 0;
axi_bid_array[2] = 0;
axi_bid_array[3] = 0;
end else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin
axi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;
end
end
end
endgenerate
assign S_AXI_BVALID = bvalid_r;
assign S_AXI_AWREADY = aw_ready_r;
endmodule
module blk_mem_axi_read_wrapper_beh_v8_2
# (
//// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0,
parameter C_AXI_TYPE = 0,
parameter C_AXI_SLAVE_TYPE = 0,
parameter C_MEMORY_TYPE = 0,
parameter C_WRITE_WIDTH_A = 4,
parameter C_WRITE_DEPTH_A = 32,
parameter C_ADDRA_WIDTH = 12,
parameter C_AXI_PIPELINE_STAGES = 0,
parameter C_AXI_ARADDR_WIDTH = 12,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
parameter C_ADDRB_WIDTH = 12
)
(
//// AXI Global Signals
input S_ACLK,
input S_ARESETN,
//// AXI Full/Lite Slave Read (Read side)
input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,
input [7:0] S_AXI_ARLEN,
input [2:0] S_AXI_ARSIZE,
input [1:0] S_AXI_ARBURST,
input S_AXI_ARVALID,
output S_AXI_ARREADY,
output S_AXI_RLAST,
output S_AXI_RVALID,
input S_AXI_RREADY,
input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,
//// AXI Full/Lite Read Address Signals to BRAM
output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,
output S_AXI_RD_EN
);
localparam FLOP_DELAY = 100; // 100 ps
localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:
((C_WRITE_WIDTH_A==16)?1:
((C_WRITE_WIDTH_A==32)?2:
((C_WRITE_WIDTH_A==64)?3:
((C_WRITE_WIDTH_A==128)?4:
((C_WRITE_WIDTH_A==256)?5:0))))));
reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;
wire addr_en_c;
wire rd_en_c;
wire incr_addr_c;
wire single_trans_c;
wire dec_alen_c;
wire mux_sel_c;
wire r_last_c;
wire r_last_int_c;
wire [C_ADDRB_WIDTH-1 : 0] araddr_out;
reg [7:0] arlen_int_r=0;
reg [7:0] arlen_cntr=8'h01;
reg [1:0] arburst_int_c=0;
reg [1:0] arburst_int_r=0;
reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;
integer num_of_bytes_c = 0;
integer total_bytes = 0;
integer num_of_bytes_r = 0;
integer wrap_base_addr_r = 0;
integer wrap_boundary_r = 0;
reg [7:0] arlen_int_c=0;
integer total_bytes_c = 0;
integer wrap_base_addr_c = 0;
integer wrap_boundary_c = 0;
assign dec_alen_c = incr_addr_c | r_last_int_c;
read_netlist_v8_2
#(.C_AXI_TYPE (1),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH))
axi_read_fsm (
.S_AXI_INCR_ADDR(incr_addr_c),
.S_AXI_ADDR_EN(addr_en_c),
.S_AXI_SINGLE_TRANS(single_trans_c),
.S_AXI_MUX_SEL(mux_sel_c),
.S_AXI_R_LAST(r_last_c),
.S_AXI_R_LAST_INT(r_last_int_c),
//// AXI Global Signals
.S_ACLK(S_ACLK),
.S_ARESETN(S_ARESETN),
//// AXI Full/Lite Slave Read (Read side)
.S_AXI_ARLEN(S_AXI_ARLEN),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_RLAST(S_AXI_RLAST),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_RREADY(S_AXI_RREADY),
//// AXI Full/Lite Read Address Signals to BRAM
.S_AXI_RD_EN(rd_en_c)
);
always@(*) begin
num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);
total_bytes = (num_of_bytes_r)*(arlen_int_r+1);
wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);
wrap_boundary_r = wrap_base_addr_r+total_bytes;
//////// combinatorial from interface
arlen_int_c = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);
total_bytes_c = (num_of_bytes_c)*(arlen_int_c+1);
wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);
wrap_boundary_c = wrap_base_addr_c+total_bytes_c;
arburst_int_c = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1);
end
////-------------------------------------------------------------------------
//// BMG address generation
////-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
araddr_reg <= 0;
arburst_int_r <= 0;
num_of_bytes_r <= 0;
end else begin
if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin
arburst_int_r <= arburst_int_c;
num_of_bytes_r <= num_of_bytes_c;
if (arburst_int_c == 2'b10) begin
if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin
araddr_reg <= wrap_base_addr_c;
end else begin
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
end
end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
end
end else if (addr_en_c == 1'b1) begin
araddr_reg <= S_AXI_ARADDR;
num_of_bytes_r <= num_of_bytes_c;
arburst_int_r <= arburst_int_c;
end else if (incr_addr_c == 1'b1) begin
if (arburst_int_r == 2'b10) begin
if(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin
araddr_reg <= wrap_base_addr_r;
end else begin
araddr_reg <= araddr_reg + num_of_bytes_r;
end
end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin
araddr_reg <= araddr_reg + num_of_bytes_r;
end
end
end
end
assign araddr_out = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);
////-----------------------------------------------------------------------
//// Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM
////-----------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
arlen_cntr <= 8'h01;
arlen_int_r <= 0;
end else begin
if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin
arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
arlen_cntr <= S_AXI_ARLEN - 1'b1;
end else if (addr_en_c == 1'b1) begin
arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
arlen_cntr <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
end else if (dec_alen_c == 1'b1) begin
arlen_cntr <= arlen_cntr - 1'b1 ;
end
else begin
arlen_cntr <= arlen_cntr;
end
end
end
assign r_last_int_c = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;
////------------------------------------------------------------------------
//// AXI FULL FSM
//// Mux Selection of ARADDR
//// ARADDR is driven out from the read fsm based on the mux_sel_c
//// Based on mux_sel either ARADDR is given out or the latched ARADDR is
//// given out to BRAM
////------------------------------------------------------------------------
assign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;
////------------------------------------------------------------------------
//// Assign output signals - AXI FULL FSM
////------------------------------------------------------------------------
assign S_AXI_RD_EN = rd_en_c;
generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
S_AXI_RID <= 0;
ar_id_r <= 0;
end else begin
if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin
S_AXI_RID <= S_AXI_ARID;
ar_id_r <= S_AXI_ARID;
end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin
ar_id_r <= S_AXI_ARID;
end else if (rd_en_c == 1'b1) begin
S_AXI_RID <= ar_id_r;
end
end
end
end
endgenerate
endmodule
module blk_mem_axi_regs_fwd_v8_2
#(parameter C_DATA_WIDTH = 8
)(
input ACLK,
input ARESET,
input S_VALID,
output S_READY,
input [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
output M_VALID,
input M_READY,
output reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA
);
reg [C_DATA_WIDTH-1:0] STORAGE_DATA;
wire S_READY_I;
reg M_VALID_I;
reg [1:0] ARESET_D;
//assign local signal to its output signal
assign S_READY = S_READY_I;
assign M_VALID = M_VALID_I;
always @(posedge ACLK) begin
ARESET_D <= {ARESET_D[0], ARESET};
end
//Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK or ARESET) begin
if (ARESET == 1'b1) begin
STORAGE_DATA <= 0;
end else begin
if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin
STORAGE_DATA <= S_PAYLOAD_DATA;
end
end
end
always @(posedge ACLK) begin
M_PAYLOAD_DATA = STORAGE_DATA;
end
//M_Valid set to high when we have a completed transfer on slave side
//Is removed on a M_READY except if we have a new transfer on the slave side
always @(posedge ACLK or ARESET_D) begin
if (ARESET_D != 2'b00) begin
M_VALID_I <= 1'b0;
end else begin
if (S_VALID == 1'b1) begin
//Always set M_VALID_I when slave side is valid
M_VALID_I <= 1'b1;
end else if (M_READY == 1'b1 ) begin
//Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= 1'b0;
end
end
end
//Slave Ready is either when Master side drives M_READY or we have space in our storage data
assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));
endmodule
//*****************************************************************************
// Output Register Stage module
//
// This module builds the output register stages of the memory. This module is
// instantiated in the main memory module (BLK_MEM_GEN_v8_2) which is
// declared/implemented further down in this file.
//*****************************************************************************
module BLK_MEM_GEN_v8_2_output_stage
#(parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RST = 0,
parameter C_RSTRAM = 0,
parameter C_RST_PRIORITY = "CE",
parameter C_INIT_VAL = "0",
parameter C_HAS_EN = 0,
parameter C_HAS_REGCE = 0,
parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_MEM_OUTPUT_REGS = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter NUM_STAGES = 1,
parameter C_EN_ECC_PIPE = 0,
parameter FLOP_DELAY = 100
)
(
input CLK,
input RST,
input EN,
input REGCE,
input [C_DATA_WIDTH-1:0] DIN_I,
output reg [C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN_I,
input DBITERR_IN_I,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN_I,
input ECCPIPECE,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RST : Determines the presence of the RST port
// C_RSTRAM : Determines if special reset behavior is used
// C_RST_PRIORITY : Determines the priority between CE and SR
// C_INIT_VAL : Initialization value
// C_HAS_EN : Determines the presence of the EN port
// C_HAS_REGCE : Determines the presence of the REGCE port
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// NUM_STAGES : Determines the number of output stages
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// RST : Reset input to reset memory outputs to a user-defined
// reset state
// EN : Enable all read and write operations
// REGCE : Register Clock Enable to control each pipeline output
// register stages
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
// Fix for CR-509792
localparam REG_STAGES = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;
// Declare the pipeline registers
// (includes mem output reg, mux pipeline stages, and mux output reg)
reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;
reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;
reg [REG_STAGES-1:0] sbiterr_regs;
reg [REG_STAGES-1:0] dbiterr_regs;
reg [C_DATA_WIDTH*8-1:0] init_str = C_INIT_VAL;
reg [C_DATA_WIDTH-1:0] init_val ;
//*********************************************
// Wire off optional inputs based on parameters
//*********************************************
wire en_i;
wire regce_i;
wire rst_i;
// Internal signals
reg [C_DATA_WIDTH-1:0] DIN;
reg [C_ADDRB_WIDTH-1:0] RDADDRECC_IN;
reg SBITERR_IN;
reg DBITERR_IN;
// Internal enable for output registers is tied to user EN or '1' depending
// on parameters
assign en_i = (C_HAS_EN==0 || EN);
// Internal register enable for output registers is tied to user REGCE, EN or
// '1' depending on parameters
// For V4 ECC, REGCE is always 1
// Virtex-4 ECC Not Yet Supported
assign regce_i = ((C_HAS_REGCE==1) && REGCE) ||
((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));
//Internal SRR is tied to user RST or '0' depending on parameters
assign rst_i = (C_HAS_RST==1) && RST;
//****************************************************
// Power on: load up the output registers and latches
//****************************************************
initial begin
if (!($sscanf(init_str, "%h", init_val))) begin
init_val = 0;
end
DOUT = init_val;
RDADDRECC = 0;
SBITERR = 1'b0;
DBITERR = 1'b0;
DIN = {(C_DATA_WIDTH){1'b0}};
RDADDRECC_IN = 0;
SBITERR_IN = 0;
DBITERR_IN = 0;
// This will be one wider than need, but 0 is an error
out_regs = {(REG_STAGES+1){init_val}};
rdaddrecc_regs = 0;
sbiterr_regs = {(REG_STAGES+1){1'b0}};
dbiterr_regs = {(REG_STAGES+1){1'b0}};
end
//***********************************************
// NUM_STAGES = 0 (No output registers. RAM only)
//***********************************************
generate if (NUM_STAGES == 0) begin : zero_stages
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg
always @* begin
DIN = DIN_I;
SBITERR_IN = SBITERR_IN_I;
DBITERR_IN = DBITERR_IN_I;
RDADDRECC_IN = RDADDRECC_IN_I;
end
end
endgenerate
generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg
always @(posedge CLK) begin
if(ECCPIPECE == 1) begin
DIN <= #FLOP_DELAY DIN_I;
SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;
DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;
RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;
end
end
end
endgenerate
//***********************************************
// NUM_STAGES = 1
// (Mem Output Reg only or Mux Output Reg only)
//***********************************************
// Possible valid combinations:
// Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)
// +-----------------------------------------+
// | C_RSTRAM_* | Reset Behavior |
// +----------------+------------------------+
// | 0 | Normal Behavior |
// +----------------+------------------------+
// | 1 | Special Behavior |
// +----------------+------------------------+
//
// Normal = REGCE gates reset, as in the case of all families except S3ADSP.
// Special = EN gates reset, as in the case of S3ADSP.
generate if (NUM_STAGES == 1 &&
(C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != "spartan3adsp" && C_XDEVICEFAMILY != "aspartan3adsp" )) ||
C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))
begin : one_stages_norm
always @(posedge CLK) begin
if (C_RST_PRIORITY == "CE") begin //REGCE has priority
if (regce_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY DIN;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY SBITERR_IN;
DBITERR <= #FLOP_DELAY DBITERR_IN;
end //Output signal assignments
end else begin //RST has priority
if (rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY DIN;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY SBITERR_IN;
DBITERR <= #FLOP_DELAY DBITERR_IN;
end //Output signal assignments
end //end Priority conditions
end //end RST Type conditions
end //end one_stages_norm generate statement
endgenerate
// Special Reset Behavior for S3ADSP
generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY =="spartan3adsp" || C_XDEVICEFAMILY =="aspartan3adsp"))
begin : one_stage_splbhv
always @(posedge CLK) begin
if (en_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
end else if (regce_i && !rst_i) begin
DOUT <= #FLOP_DELAY DIN;
end //Output signal assignments
end //end CLK
end //end one_stage_splbhv generate statement
endgenerate
//************************************************************
// NUM_STAGES > 1
// Mem Output Reg + Mux Output Reg
// or
// Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg
// or
// Mux Pipeline Stages (>0) + Mux Output Reg
//*************************************************************
generate if (NUM_STAGES > 1) begin : multi_stage
//Asynchronous Reset
always @(posedge CLK) begin
if (C_RST_PRIORITY == "CE") begin //REGCE has priority
if (regce_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY
out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];
RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];
SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];
DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];
end //Output signal assignments
end else begin //RST has priority
if (rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY
out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];
RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];
SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];
DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];
end //Output signal assignments
end //end Priority conditions
// Shift the data through the output stages
if (en_i) begin
out_regs <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;
rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;
sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;
dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;
end
end //end CLK
end //end multi_stage generate statement
endgenerate
endmodule
module BLK_MEM_GEN_v8_2_softecc_output_reg_stage
#(parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_USE_SOFTECC = 0,
parameter FLOP_DELAY = 100
)
(
input CLK,
input [C_DATA_WIDTH-1:0] DIN,
output reg [C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN,
input DBITERR_IN,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_SOFTECC_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
reg [C_DATA_WIDTH-1:0] dout_i = 0;
reg sbiterr_i = 0;
reg dbiterr_i = 0;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_i = 0;
//***********************************************
// NO OUTPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
//***********************************************
// WITH OUTPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage
always @(posedge CLK) begin
dout_i <= #FLOP_DELAY DIN;
rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;
sbiterr_i <= #FLOP_DELAY SBITERR_IN;
dbiterr_i <= #FLOP_DELAY DBITERR_IN;
end
always @* begin
DOUT = dout_i;
RDADDRECC = rdaddrecc_i;
SBITERR = sbiterr_i;
DBITERR = dbiterr_i;
end //end always
end //end in_or_out_stage generate statement
endgenerate
endmodule
//*****************************************************************************
// Main Memory module
//
// This module is the top-level behavioral model and this implements the RAM
//*****************************************************************************
module BLK_MEM_GEN_v8_2_mem_module
#(parameter C_CORENAME = "blk_mem_gen_v8_2",
parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_MEM_TYPE = 2,
parameter C_BYTE_SIZE = 9,
parameter C_USE_BRAM_BLOCK = 0,
parameter C_ALGORITHM = 1,
parameter C_PRIM_TYPE = 3,
parameter C_LOAD_INIT_FILE = 0,
parameter C_INIT_FILE_NAME = "",
parameter C_INIT_FILE = "",
parameter C_USE_DEFAULT_DATA = 0,
parameter C_DEFAULT_DATA = "0",
parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RSTA = 0,
parameter C_RST_PRIORITY_A = "CE",
parameter C_RSTRAM_A = 0,
parameter C_INITA_VAL = "0",
parameter C_HAS_ENA = 1,
parameter C_HAS_REGCEA = 0,
parameter C_USE_BYTE_WEA = 0,
parameter C_WEA_WIDTH = 1,
parameter C_WRITE_MODE_A = "WRITE_FIRST",
parameter C_WRITE_WIDTH_A = 32,
parameter C_READ_WIDTH_A = 32,
parameter C_WRITE_DEPTH_A = 64,
parameter C_READ_DEPTH_A = 64,
parameter C_ADDRA_WIDTH = 5,
parameter C_HAS_RSTB = 0,
parameter C_RST_PRIORITY_B = "CE",
parameter C_RSTRAM_B = 0,
parameter C_INITB_VAL = "",
parameter C_HAS_ENB = 1,
parameter C_HAS_REGCEB = 0,
parameter C_USE_BYTE_WEB = 0,
parameter C_WEB_WIDTH = 1,
parameter C_WRITE_MODE_B = "WRITE_FIRST",
parameter C_WRITE_WIDTH_B = 32,
parameter C_READ_WIDTH_B = 32,
parameter C_WRITE_DEPTH_B = 64,
parameter C_READ_DEPTH_B = 64,
parameter C_ADDRB_WIDTH = 5,
parameter C_HAS_MEM_OUTPUT_REGS_A = 0,
parameter C_HAS_MEM_OUTPUT_REGS_B = 0,
parameter C_HAS_MUX_OUTPUT_REGS_A = 0,
parameter C_HAS_MUX_OUTPUT_REGS_B = 0,
parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_MUX_PIPELINE_STAGES = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter C_HAS_INJECTERR = 0,
parameter C_SIM_COLLISION_CHECK = "NONE",
parameter C_COMMON_CLK = 1,
parameter FLOP_DELAY = 100,
parameter C_DISABLE_WARN_BHV_COLL = 0,
parameter C_EN_ECC_PIPE = 0,
parameter C_DISABLE_WARN_BHV_RANGE = 0
)
(input CLKA,
input RSTA,
input ENA,
input REGCEA,
input [C_WEA_WIDTH-1:0] WEA,
input [C_ADDRA_WIDTH-1:0] ADDRA,
input [C_WRITE_WIDTH_A-1:0] DINA,
output [C_READ_WIDTH_A-1:0] DOUTA,
input CLKB,
input RSTB,
input ENB,
input REGCEB,
input [C_WEB_WIDTH-1:0] WEB,
input [C_ADDRB_WIDTH-1:0] ADDRB,
input [C_WRITE_WIDTH_B-1:0] DINB,
output [C_READ_WIDTH_B-1:0] DOUTB,
input INJECTSBITERR,
input INJECTDBITERR,
input ECCPIPECE,
input SLEEP,
output SBITERR,
output DBITERR,
output [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_CORENAME : Instance name of the Block Memory Generator core
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_MEM_TYPE : Designates memory type.
// It can be
// 0 - Single Port Memory
// 1 - Simple Dual Port Memory
// 2 - True Dual Port Memory
// 3 - Single Port Read Only Memory
// 4 - Dual Port Read Only Memory
// C_BYTE_SIZE : Size of a byte (8 or 9 bits)
// C_ALGORITHM : Designates the algorithm method used
// for constructing the memory.
// It can be Fixed_Primitives, Minimum_Area or
// Low_Power
// C_PRIM_TYPE : Designates the user selected primitive used to
// construct the memory.
//
// C_LOAD_INIT_FILE : Designates the use of an initialization file to
// initialize memory contents.
// C_INIT_FILE_NAME : Memory initialization file name.
// C_USE_DEFAULT_DATA : Designates whether to fill remaining
// initialization space with default data
// C_DEFAULT_DATA : Default value of all memory locations
// not initialized by the memory
// initialization file.
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RSTA : Determines the presence of the RSTA port
// C_RST_PRIORITY_A : Determines the priority between CE and SR for
// Port A.
// C_RSTRAM_A : Determines if special reset behavior is used for
// Port A
// C_INITA_VAL : The initialization value for Port A
// C_HAS_ENA : Determines the presence of the ENA port
// C_HAS_REGCEA : Determines the presence of the REGCEA port
// C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
// C_WEA_WIDTH : The width of the WEA port
// C_WRITE_MODE_A : Configurable write mode for Port A. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_A : Memory write width for Port A.
// C_READ_WIDTH_A : Memory read width for Port A.
// C_WRITE_DEPTH_A : Memory write depth for Port A.
// C_READ_DEPTH_A : Memory read depth for Port A.
// C_ADDRA_WIDTH : Width of the ADDRA input port
// C_HAS_RSTB : Determines the presence of the RSTB port
// C_RST_PRIORITY_B : Determines the priority between CE and SR for
// Port B.
// C_RSTRAM_B : Determines if special reset behavior is used for
// Port B
// C_INITB_VAL : The initialization value for Port B
// C_HAS_ENB : Determines the presence of the ENB port
// C_HAS_REGCEB : Determines the presence of the REGCEB port
// C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
// C_WEB_WIDTH : The width of the WEB port
// C_WRITE_MODE_B : Configurable write mode for Port B. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_B : Memory write width for Port B.
// C_READ_WIDTH_B : Memory read width for Port B.
// C_WRITE_DEPTH_B : Memory write depth for Port B.
// C_READ_DEPTH_B : Memory read depth for Port B.
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
// of the RAM primitive for Port A.
// C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive for Port B.
// C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
// of the MUX for Port A.
// C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
// of the MUX for Port B.
// C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
// between the muxes.
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// C_HAS_INJECTERR : Determines if the error injection pins
// are present or not. If the ECC feature
// is not used, this value is defaulted to
// 0, else the following are the allowed
// values:
// 0 : No INJECTSBITERR or INJECTDBITERR pins
// 1 : Only INJECTSBITERR pin exists
// 2 : Only INJECTDBITERR pin exists
// 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
// C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
// warnings. It can be "ALL", "NONE",
// "Warnings_Only" or "Generate_X_Only".
// C_COMMON_CLK : Determins if the core has a single CLK input.
// C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
// C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
// warnings
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLKA : Clock to synchronize all read and write operations of Port A.
// RSTA : Reset input to reset memory outputs to a user-defined
// reset state for Port A.
// ENA : Enable all read and write operations of Port A.
// REGCEA : Register Clock Enable to control each pipeline output
// register stages for Port A.
// WEA : Write Enable to enable all write operations of Port A.
// ADDRA : Address of Port A.
// DINA : Data input of Port A.
// DOUTA : Data output of Port A.
// CLKB : Clock to synchronize all read and write operations of Port B.
// RSTB : Reset input to reset memory outputs to a user-defined
// reset state for Port B.
// ENB : Enable all read and write operations of Port B.
// REGCEB : Register Clock Enable to control each pipeline output
// register stages for Port B.
// WEB : Write Enable to enable all write operations of Port B.
// ADDRB : Address of Port B.
// DINB : Data input of Port B.
// DOUTB : Data output of Port B.
// INJECTSBITERR : Single Bit ECC Error Injection Pin.
// INJECTDBITERR : Double Bit ECC Error Injection Pin.
// SBITERR : Output signal indicating that a Single Bit ECC Error has been
// detected and corrected.
// DBITERR : Output signal indicating that a Double Bit ECC Error has been
// detected.
// RDADDRECC : Read Address Output signal indicating address at which an
// ECC error has occurred.
//////////////////////////////////////////////////////////////////////////
// Note: C_CORENAME parameter is hard-coded to "blk_mem_gen_v8_2" and it is
// only used by this module to print warning messages. It is neither passed
// down from blk_mem_gen_v8_2_xst.v nor present in the instantiation template
// coregen generates
//***************************************************************************
// constants for the core behavior
//***************************************************************************
// file handles for logging
//--------------------------------------------------
localparam ADDRFILE = 32'h8000_0001; //stdout for addr out of range
localparam COLLFILE = 32'h8000_0001; //stdout for coll detection
localparam ERRFILE = 32'h8000_0001; //stdout for file I/O errors
// other constants
//--------------------------------------------------
localparam COLL_DELAY = 100; // 100 ps
// locally derived parameters to determine memory shape
//-----------------------------------------------------
localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0)))));
localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?
C_WRITE_WIDTH_A : C_READ_WIDTH_A;
localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?
C_WRITE_WIDTH_B : C_READ_WIDTH_B;
localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?
MIN_WIDTH_A : MIN_WIDTH_B;
localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?
C_WRITE_DEPTH_A : C_READ_DEPTH_A;
localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?
C_WRITE_DEPTH_B : C_READ_DEPTH_B;
localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?
MAX_DEPTH_A : MAX_DEPTH_B;
// locally derived parameters to assist memory access
//----------------------------------------------------
// Calculate the width ratios of each port with respect to the narrowest
// port
localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;
localparam READ_WIDTH_RATIO_A = C_READ_WIDTH_A/MIN_WIDTH;
localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;
localparam READ_WIDTH_RATIO_B = C_READ_WIDTH_B/MIN_WIDTH;
// To modify the LSBs of the 'wider' data to the actual
// address value
//----------------------------------------------------
localparam WRITE_ADDR_A_DIV = C_WRITE_WIDTH_A/MIN_WIDTH_A;
localparam READ_ADDR_A_DIV = C_READ_WIDTH_A/MIN_WIDTH_A;
localparam WRITE_ADDR_B_DIV = C_WRITE_WIDTH_B/MIN_WIDTH_B;
localparam READ_ADDR_B_DIV = C_READ_WIDTH_B/MIN_WIDTH_B;
// If byte writes aren't being used, make sure BYTE_SIZE is not
// wider than the memory elements to avoid compilation warnings
localparam BYTE_SIZE = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;
// The memory
reg [MIN_WIDTH-1:0] memory [0:MAX_DEPTH-1];
reg [MIN_WIDTH-1:0] temp_mem_array [0:MAX_DEPTH-1];
reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;
// ECC error arrays
reg sbiterr_arr [0:MAX_DEPTH-1];
reg dbiterr_arr [0:MAX_DEPTH-1];
reg softecc_sbiterr_arr [0:MAX_DEPTH-1];
reg softecc_dbiterr_arr [0:MAX_DEPTH-1];
// Memory output 'latches'
reg [C_READ_WIDTH_A-1:0] memory_out_a;
reg [C_READ_WIDTH_B-1:0] memory_out_b;
// ECC error inputs and outputs from output_stage module:
reg sbiterr_in;
wire sbiterr_sdp;
reg dbiterr_in;
wire dbiterr_sdp;
wire [C_READ_WIDTH_B-1:0] dout_i;
wire dbiterr_i;
wire sbiterr_i;
wire [C_ADDRB_WIDTH-1:0] rdaddrecc_i;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_in;
wire [C_ADDRB_WIDTH-1:0] rdaddrecc_sdp;
// Reset values
reg [C_READ_WIDTH_A-1:0] inita_val;
reg [C_READ_WIDTH_B-1:0] initb_val;
// Collision detect
reg is_collision;
reg is_collision_a, is_collision_delay_a;
reg is_collision_b, is_collision_delay_b;
// Temporary variables for initialization
//---------------------------------------
integer status;
integer initfile;
integer meminitfile;
// data input buffer
reg [C_WRITE_WIDTH_A-1:0] mif_data;
reg [C_WRITE_WIDTH_A-1:0] mem_data;
// string values in hex
reg [C_READ_WIDTH_A*8-1:0] inita_str = C_INITA_VAL;
reg [C_READ_WIDTH_B*8-1:0] initb_str = C_INITB_VAL;
reg [C_WRITE_WIDTH_A*8-1:0] default_data_str = C_DEFAULT_DATA;
// initialization filename
reg [1023*8-1:0] init_file_str = C_INIT_FILE_NAME;
reg [1023*8-1:0] mem_init_file_str = C_INIT_FILE;
//Constants used to calculate the effective address widths for each of the
//four ports.
integer cnt = 1;
integer write_addr_a_width, read_addr_a_width;
integer write_addr_b_width, read_addr_b_width;
localparam C_FAMILY_LOCALPARAM = (C_FAMILY=="virtexu"?"virtex7":(C_FAMILY=="kintexu" ? "virtex7":(C_FAMILY=="virtex7" ? "virtex7" : (C_FAMILY=="virtex7l" ? "virtex7" : (C_FAMILY=="qvirtex7" ? "virtex7" : (C_FAMILY=="qvirtex7l" ? "virtex7" : (C_FAMILY=="kintex7" ? "virtex7" : (C_FAMILY=="kintex7l" ? "virtex7" : (C_FAMILY=="qkintex7" ? "virtex7" : (C_FAMILY=="qkintex7l" ? "virtex7" : (C_FAMILY=="artix7" ? "virtex7" : (C_FAMILY=="artix7l" ? "virtex7" : (C_FAMILY=="qartix7" ? "virtex7" : (C_FAMILY=="qartix7l" ? "virtex7" : (C_FAMILY=="aartix7" ? "virtex7" : (C_FAMILY=="zynq" ? "virtex7" : (C_FAMILY=="azynq" ? "virtex7" : (C_FAMILY=="qzynq" ? "virtex7" : C_FAMILY))))))))))))))))));
// Internal configuration parameters
//---------------------------------------------
localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);
localparam IS_ROM = (C_MEM_TYPE==3 || C_MEM_TYPE==4);
localparam HAS_A_WRITE = (!IS_ROM);
localparam HAS_B_WRITE = (C_MEM_TYPE==2);
localparam HAS_A_READ = (C_MEM_TYPE!=1);
localparam HAS_B_READ = (!SINGLE_PORT);
localparam HAS_B_PORT = (HAS_B_READ || HAS_B_WRITE);
// Calculate the mux pipeline register stages for Port A and Port B
//------------------------------------------------------------------
localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?
C_MUX_PIPELINE_STAGES : 0;
localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?
C_MUX_PIPELINE_STAGES : 0;
// Calculate total number of register stages in the core
// -----------------------------------------------------
localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);
localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);
wire ena_i;
wire enb_i;
wire reseta_i;
wire resetb_i;
wire [C_WEA_WIDTH-1:0] wea_i;
wire [C_WEB_WIDTH-1:0] web_i;
wire rea_i;
wire reb_i;
wire rsta_outp_stage;
wire rstb_outp_stage;
// ECC SBITERR/DBITERR Outputs
// The ECC Behavior is modeled by the behavioral models only for Virtex-6.
// For Virtex-5, these outputs will be tied to 0.
assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;
assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;
assign RDADDRECC = (((C_FAMILY_LOCALPARAM == "virtex7") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;
// This effectively wires off optional inputs
assign ena_i = (C_HAS_ENA==0) || ENA;
assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;
assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0;
assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0;
assign rea_i = (HAS_A_READ) ? ena_i : 'b0;
assign reb_i = (HAS_B_READ) ? enb_i : 'b0;
// These signals reset the memory latches
assign reseta_i =
((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||
(C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));
assign resetb_i =
((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||
(C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));
// Tasks to access the memory
//---------------------------
//**************
// write_a
//**************
task write_a
(input reg [C_ADDRA_WIDTH-1:0] addr,
input reg [C_WEA_WIDTH-1:0] byte_en,
input reg [C_WRITE_WIDTH_A-1:0] data,
input inj_sbiterr,
input inj_dbiterr);
reg [C_WRITE_WIDTH_A-1:0] current_contents;
reg [C_ADDRA_WIDTH-1:0] address;
integer i;
begin
// Shift the address by the ratio
address = (addr/WRITE_ADDR_A_DIV);
if (address >= C_WRITE_DEPTH_A) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for A Write",
C_CORENAME, addr);
end
// valid address
end else begin
// Combine w/ byte writes
if (C_USE_BYTE_WEA) begin
// Get the current memory contents
if (WRITE_WIDTH_RATIO_A == 1) begin
// Workaround for IUS 5.5 part-select issue
current_contents = memory[address];
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin
current_contents[MIN_WIDTH*i+:MIN_WIDTH]
= memory[address*WRITE_WIDTH_RATIO_A + i];
end
end
// Apply incoming bytes
if (C_WEA_WIDTH == 1) begin
// Workaround for IUS 5.5 part-select issue
if (byte_en[0]) begin
current_contents = data;
end
end else begin
for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin
if (byte_en[i]) begin
current_contents[BYTE_SIZE*i+:BYTE_SIZE]
= data[BYTE_SIZE*i+:BYTE_SIZE];
end
end
end
// No byte-writes, overwrite the whole word
end else begin
current_contents = data;
end
// Insert double bit errors:
if (C_USE_ECC == 1) begin
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
current_contents[0] = !(current_contents[0]);
current_contents[1] = !(current_contents[1]);
end
end
// Insert softecc double bit errors:
if (C_USE_SOFTECC == 1) begin
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];
doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];
doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];
current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];
end
end
// Write data to memory
if (WRITE_WIDTH_RATIO_A == 1) begin
// Workaround for IUS 5.5 part-select issue
memory[address*WRITE_WIDTH_RATIO_A] = current_contents;
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin
memory[address*WRITE_WIDTH_RATIO_A + i]
= current_contents[MIN_WIDTH*i+:MIN_WIDTH];
end
end
// Store the address at which error is injected:
if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin
if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) ||
(C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))
begin
sbiterr_arr[addr] = 1;
end else begin
sbiterr_arr[addr] = 0;
end
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
dbiterr_arr[addr] = 1;
end else begin
dbiterr_arr[addr] = 0;
end
end
// Store the address at which softecc error is injected:
if (C_USE_SOFTECC == 1) begin
if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) ||
(C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))
begin
softecc_sbiterr_arr[addr] = 1;
end else begin
softecc_sbiterr_arr[addr] = 0;
end
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
softecc_dbiterr_arr[addr] = 1;
end else begin
softecc_dbiterr_arr[addr] = 0;
end
end
end
end
endtask
//**************
// write_b
//**************
task write_b
(input reg [C_ADDRB_WIDTH-1:0] addr,
input reg [C_WEB_WIDTH-1:0] byte_en,
input reg [C_WRITE_WIDTH_B-1:0] data);
reg [C_WRITE_WIDTH_B-1:0] current_contents;
reg [C_ADDRB_WIDTH-1:0] address;
integer i;
begin
// Shift the address by the ratio
address = (addr/WRITE_ADDR_B_DIV);
if (address >= C_WRITE_DEPTH_B) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for B Write",
C_CORENAME, addr);
end
// valid address
end else begin
// Combine w/ byte writes
if (C_USE_BYTE_WEB) begin
// Get the current memory contents
if (WRITE_WIDTH_RATIO_B == 1) begin
// Workaround for IUS 5.5 part-select issue
current_contents = memory[address];
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin
current_contents[MIN_WIDTH*i+:MIN_WIDTH]
= memory[address*WRITE_WIDTH_RATIO_B + i];
end
end
// Apply incoming bytes
if (C_WEB_WIDTH == 1) begin
// Workaround for IUS 5.5 part-select issue
if (byte_en[0]) begin
current_contents = data;
end
end else begin
for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin
if (byte_en[i]) begin
current_contents[BYTE_SIZE*i+:BYTE_SIZE]
= data[BYTE_SIZE*i+:BYTE_SIZE];
end
end
end
// No byte-writes, overwrite the whole word
end else begin
current_contents = data;
end
// Write data to memory
if (WRITE_WIDTH_RATIO_B == 1) begin
// Workaround for IUS 5.5 part-select issue
memory[address*WRITE_WIDTH_RATIO_B] = current_contents;
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin
memory[address*WRITE_WIDTH_RATIO_B + i]
= current_contents[MIN_WIDTH*i+:MIN_WIDTH];
end
end
end
end
endtask
//**************
// read_a
//**************
task read_a
(input reg [C_ADDRA_WIDTH-1:0] addr,
input reg reset);
reg [C_ADDRA_WIDTH-1:0] address;
integer i;
begin
if (reset) begin
memory_out_a <= #FLOP_DELAY inita_val;
end else begin
// Shift the address by the ratio
address = (addr/READ_ADDR_A_DIV);
if (address >= C_READ_DEPTH_A) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for A Read",
C_CORENAME, addr);
end
memory_out_a <= #FLOP_DELAY 'bX;
// valid address
end else begin
if (READ_WIDTH_RATIO_A==1) begin
memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];
end else begin
// Increment through the 'partial' words in the memory
for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin
memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]
<= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];
end
end //end READ_WIDTH_RATIO_A==1 loop
end //end valid address loop
end //end reset-data assignment loops
end
endtask
//**************
// read_b
//**************
task read_b
(input reg [C_ADDRB_WIDTH-1:0] addr,
input reg reset);
reg [C_ADDRB_WIDTH-1:0] address;
integer i;
begin
if (reset) begin
memory_out_b <= #FLOP_DELAY initb_val;
sbiterr_in <= #FLOP_DELAY 1'b0;
dbiterr_in <= #FLOP_DELAY 1'b0;
rdaddrecc_in <= #FLOP_DELAY 0;
end else begin
// Shift the address
address = (addr/READ_ADDR_B_DIV);
if (address >= C_READ_DEPTH_B) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for B Read",
C_CORENAME, addr);
end
memory_out_b <= #FLOP_DELAY 'bX;
sbiterr_in <= #FLOP_DELAY 1'bX;
dbiterr_in <= #FLOP_DELAY 1'bX;
rdaddrecc_in <= #FLOP_DELAY 'bX;
// valid address
end else begin
if (READ_WIDTH_RATIO_B==1) begin
memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];
end else begin
// Increment through the 'partial' words in the memory
for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin
memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]
<= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];
end
end
if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin
rdaddrecc_in <= #FLOP_DELAY addr;
if (sbiterr_arr[addr] == 1) begin
sbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
sbiterr_in <= #FLOP_DELAY 1'b0;
end
if (dbiterr_arr[addr] == 1) begin
dbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
dbiterr_in <= #FLOP_DELAY 1'b0;
end
end else if (C_USE_SOFTECC == 1) begin
rdaddrecc_in <= #FLOP_DELAY addr;
if (softecc_sbiterr_arr[addr] == 1) begin
sbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
sbiterr_in <= #FLOP_DELAY 1'b0;
end
if (softecc_dbiterr_arr[addr] == 1) begin
dbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
dbiterr_in <= #FLOP_DELAY 1'b0;
end
end else begin
rdaddrecc_in <= #FLOP_DELAY 0;
dbiterr_in <= #FLOP_DELAY 1'b0;
sbiterr_in <= #FLOP_DELAY 1'b0;
end //end SOFTECC Loop
end //end Valid address loop
end //end reset-data assignment loops
end
endtask
//**************
// reset_a
//**************
task reset_a (input reg reset);
begin
if (reset) memory_out_a <= #FLOP_DELAY inita_val;
end
endtask
//**************
// reset_b
//**************
task reset_b (input reg reset);
begin
if (reset) memory_out_b <= #FLOP_DELAY initb_val;
end
endtask
//**************
// init_memory
//**************
task init_memory;
integer i, j, addr_step;
integer status;
reg [C_WRITE_WIDTH_A-1:0] default_data;
begin
default_data = 0;
//Display output message indicating that the behavioral model is being
//initialized
if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(" Block Memory Generator module loading initial data...");
// Convert the default to hex
if (C_USE_DEFAULT_DATA) begin
if (default_data_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_DEFAULT_DATA is empty!", C_CORENAME);
$finish;
end else begin
status = $sscanf(default_data_str, "%h", default_data);
if (status == 0) begin
$fdisplay(ERRFILE, {"%0s ERROR: Unsuccessful hexadecimal read",
"from C_DEFAULT_DATA: %0s"},
C_CORENAME, C_DEFAULT_DATA);
$finish;
end
end
end
// Step by WRITE_ADDR_A_DIV through the memory via the
// Port A write interface to hit every location once
addr_step = WRITE_ADDR_A_DIV;
// 'write' to every location with default (or 0)
for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin
write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0);
end
// Get specialized data from the MIF file
if (C_LOAD_INIT_FILE) begin
if (init_file_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE_NAME is empty!",
C_CORENAME);
$finish;
end else begin
initfile = $fopen(init_file_str, "r");
if (initfile == 0) begin
$fdisplay(ERRFILE, {"%0s, ERROR: Problem opening",
"C_INIT_FILE_NAME: %0s!"},
C_CORENAME, init_file_str);
$finish;
end else begin
// loop through the mif file, loading in the data
for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin
status = $fscanf(initfile, "%b", mif_data);
if (status > 0) begin
write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0);
end
end
$fclose(initfile);
end //initfile
end //init_file_str
end //C_LOAD_INIT_FILE
if (C_USE_BRAM_BLOCK) begin
// Get specialized data from the MIF file
if (C_INIT_FILE != "NONE") begin
if (mem_init_file_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE is empty!",
C_CORENAME);
$finish;
end else begin
meminitfile = $fopen(mem_init_file_str, "r");
if (meminitfile == 0) begin
$fdisplay(ERRFILE, {"%0s, ERROR: Problem opening",
"C_INIT_FILE: %0s!"},
C_CORENAME, mem_init_file_str);
$finish;
end else begin
// loop through the mif file, loading in the data
$readmemh(mem_init_file_str, memory );
for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin
end
$fclose(meminitfile);
end //meminitfile
end //mem_init_file_str
end //C_INIT_FILE
end //C_USE_BRAM_BLOCK
//Display output message indicating that the behavioral model is done
//initializing
if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE)
$display(" Block Memory Generator data initialization complete.");
end
endtask
//**************
// log2roundup
//**************
function integer log2roundup (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
if (data_value > 1) begin
for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin
width = width + 1;
end //loop
end //if
log2roundup = width;
end //log2roundup
endfunction
//*******************
// collision_check
//*******************
function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,
input integer iswrite_a,
input reg [C_ADDRB_WIDTH-1:0] addr_b,
input integer iswrite_b);
reg c_aw_bw, c_aw_br, c_ar_bw;
integer scaled_addra_to_waddrb_width;
integer scaled_addrb_to_waddrb_width;
integer scaled_addra_to_waddra_width;
integer scaled_addrb_to_waddra_width;
integer scaled_addra_to_raddrb_width;
integer scaled_addrb_to_raddrb_width;
integer scaled_addra_to_raddra_width;
integer scaled_addrb_to_raddra_width;
begin
c_aw_bw = 0;
c_aw_br = 0;
c_ar_bw = 0;
//If write_addr_b_width is smaller, scale both addresses to that width for
//comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to write_addr_b_width. Once both are scaled to
//write_addr_b_width, compare.
scaled_addra_to_waddrb_width = ((addr_a)/
2**(C_ADDRA_WIDTH-write_addr_b_width));
scaled_addrb_to_waddrb_width = ((addr_b)/
2**(C_ADDRB_WIDTH-write_addr_b_width));
//If write_addr_a_width is smaller, scale both addresses to that width for
//comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to write_addr_a_width. Once both are scaled to
//write_addr_a_width, compare.
scaled_addra_to_waddra_width = ((addr_a)/
2**(C_ADDRA_WIDTH-write_addr_a_width));
scaled_addrb_to_waddra_width = ((addr_b)/
2**(C_ADDRB_WIDTH-write_addr_a_width));
//If read_addr_b_width is smaller, scale both addresses to that width for
//comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to read_addr_b_width. Once both are scaled to
//read_addr_b_width, compare.
scaled_addra_to_raddrb_width = ((addr_a)/
2**(C_ADDRA_WIDTH-read_addr_b_width));
scaled_addrb_to_raddrb_width = ((addr_b)/
2**(C_ADDRB_WIDTH-read_addr_b_width));
//If read_addr_a_width is smaller, scale both addresses to that width for
//comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to read_addr_a_width. Once both are scaled to
//read_addr_a_width, compare.
scaled_addra_to_raddra_width = ((addr_a)/
2**(C_ADDRA_WIDTH-read_addr_a_width));
scaled_addrb_to_raddra_width = ((addr_b)/
2**(C_ADDRB_WIDTH-read_addr_a_width));
//Look for a write-write collision. In order for a write-write
//collision to exist, both ports must have a write transaction.
if (iswrite_a && iswrite_b) begin
if (write_addr_a_width > write_addr_b_width) begin
if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin
c_aw_bw = 1;
end else begin
c_aw_bw = 0;
end
end else begin
if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin
c_aw_bw = 1;
end else begin
c_aw_bw = 0;
end
end //width
end //iswrite_a and iswrite_b
//If the B port is reading (which means it is enabled - so could be
//a TX_WRITE or TX_READ), then check for a write-read collision).
//This could happen whether or not a write-write collision exists due
//to asymmetric write/read ports.
if (iswrite_a) begin
if (write_addr_a_width > read_addr_b_width) begin
if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin
c_aw_br = 1;
end else begin
c_aw_br = 0;
end
end else begin
if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin
c_aw_br = 1;
end else begin
c_aw_br = 0;
end
end //width
end //iswrite_a
//If the A port is reading (which means it is enabled - so could be
// a TX_WRITE or TX_READ), then check for a write-read collision).
//This could happen whether or not a write-write collision exists due
// to asymmetric write/read ports.
if (iswrite_b) begin
if (read_addr_a_width > write_addr_b_width) begin
if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin
c_ar_bw = 1;
end else begin
c_ar_bw = 0;
end
end else begin
if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin
c_ar_bw = 1;
end else begin
c_ar_bw = 0;
end
end //width
end //iswrite_b
collision_check = c_aw_bw | c_aw_br | c_ar_bw;
end
endfunction
//*******************************
// power on values
//*******************************
initial begin
// Load up the memory
init_memory;
// Load up the output registers and latches
if ($sscanf(inita_str, "%h", inita_val)) begin
memory_out_a = inita_val;
end else begin
memory_out_a = 0;
end
if ($sscanf(initb_str, "%h", initb_val)) begin
memory_out_b = initb_val;
end else begin
memory_out_b = 0;
end
sbiterr_in = 1'b0;
dbiterr_in = 1'b0;
rdaddrecc_in = 0;
// Determine the effective address widths for each of the 4 ports
write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);
read_addr_a_width = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);
write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);
read_addr_b_width = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);
$display("Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.");
end
//***************************************************************************
// These are the main blocks which schedule read and write operations
// Note that the reset priority feature at the latch stage is only supported
// for Spartan-6. For other families, the default priority at the latch stage
// is "CE"
//***************************************************************************
// Synchronous clocks: schedule port operations with respect to
// both write operating modes
generate
if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_wf_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_rf_wf
always @(posedge CLKA) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_wf_rf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_rf_rf
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="WRITE_FIRST") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_wf_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="READ_FIRST") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_rf_nc
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_nc_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_nc_rf
always @(posedge CLKA) begin
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_nc_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
end
end
else if(C_COMMON_CLK) begin: com_clk_sched_default
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
endgenerate
// Asynchronous clocks: port operation is independent
generate
if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "WRITE_FIRST")) begin : async_clk_sched_clka_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
end
end
else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "READ_FIRST")) begin : async_clk_sched_clka_rf
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
end
end
else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "NO_CHANGE")) begin : async_clk_sched_clka_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
end
end
endgenerate
generate
if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "WRITE_FIRST")) begin: async_clk_sched_clkb_wf
always @(posedge CLKB) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "READ_FIRST")) begin: async_clk_sched_clkb_rf
always @(posedge CLKB) begin
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "NO_CHANGE")) begin: async_clk_sched_clkb_nc
always @(posedge CLKB) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
end
end
endgenerate
//***************************************************************
// Instantiate the variable depth output register stage module
//***************************************************************
// Port A
assign rsta_outp_stage = RSTA & (~SLEEP);
BLK_MEM_GEN_v8_2_output_stage
#(.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_RST_TYPE ("SYNC"),
.C_HAS_RST (C_HAS_RSTA),
.C_RSTRAM (C_RSTRAM_A),
.C_RST_PRIORITY (C_RST_PRIORITY_A),
.C_INIT_VAL (C_INITA_VAL),
.C_HAS_EN (C_HAS_ENA),
.C_HAS_REGCE (C_HAS_REGCEA),
.C_DATA_WIDTH (C_READ_WIDTH_A),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_A),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.NUM_STAGES (NUM_OUTPUT_STAGES_A),
.C_EN_ECC_PIPE (0),
.FLOP_DELAY (FLOP_DELAY))
reg_a
(.CLK (CLKA),
.RST (rsta_outp_stage),//(RSTA),
.EN (ENA),
.REGCE (REGCEA),
.DIN_I (memory_out_a),
.DOUT (DOUTA),
.SBITERR_IN_I (1'b0),
.DBITERR_IN_I (1'b0),
.SBITERR (),
.DBITERR (),
.RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}),
.ECCPIPECE (1'b0),
.RDADDRECC ()
);
assign rstb_outp_stage = RSTB & (~SLEEP);
// Port B
BLK_MEM_GEN_v8_2_output_stage
#(.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_RST_TYPE ("SYNC"),
.C_HAS_RST (C_HAS_RSTB),
.C_RSTRAM (C_RSTRAM_B),
.C_RST_PRIORITY (C_RST_PRIORITY_B),
.C_INIT_VAL (C_INITB_VAL),
.C_HAS_EN (C_HAS_ENB),
.C_HAS_REGCE (C_HAS_REGCEB),
.C_DATA_WIDTH (C_READ_WIDTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_B),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.NUM_STAGES (NUM_OUTPUT_STAGES_B),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.FLOP_DELAY (FLOP_DELAY))
reg_b
(.CLK (CLKB),
.RST (rstb_outp_stage),//(RSTB),
.EN (ENB),
.REGCE (REGCEB),
.DIN_I (memory_out_b),
.DOUT (dout_i),
.SBITERR_IN_I (sbiterr_in),
.DBITERR_IN_I (dbiterr_in),
.SBITERR (sbiterr_i),
.DBITERR (dbiterr_i),
.RDADDRECC_IN_I (rdaddrecc_in),
.ECCPIPECE (ECCPIPECE),
.RDADDRECC (rdaddrecc_i)
);
//***************************************************************
// Instantiate the Input and Output register stages
//***************************************************************
BLK_MEM_GEN_v8_2_softecc_output_reg_stage
#(.C_DATA_WIDTH (C_READ_WIDTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_USE_SOFTECC (C_USE_SOFTECC),
.FLOP_DELAY (FLOP_DELAY))
has_softecc_output_reg_stage
(.CLK (CLKB),
.DIN (dout_i),
.DOUT (DOUTB),
.SBITERR_IN (sbiterr_i),
.DBITERR_IN (dbiterr_i),
.SBITERR (sbiterr_sdp),
.DBITERR (dbiterr_sdp),
.RDADDRECC_IN (rdaddrecc_i),
.RDADDRECC (rdaddrecc_sdp)
);
//****************************************************
// Synchronous collision checks
//****************************************************
// CR 780544 : To make verilog model's collison warnings in consistant with
// vhdl model, the non-blocking assignments are replaced with blocking
// assignments.
generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll
always @(posedge CLKA) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision = 0;
end
end else begin
is_collision = 0;
end
// If the write port is in READ_FIRST mode, there is no collision
if (C_WRITE_MODE_A=="READ_FIRST" && wea_i && !web_i) begin
is_collision = 0;
end
if (C_WRITE_MODE_B=="READ_FIRST" && web_i && !wea_i) begin
is_collision = 0;
end
// Only flag if one of the accesses is a write
if (is_collision && (wea_i || web_i)) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B %0s address: %0h\n",
wea_i ? "write" : "read", ADDRA,
web_i ? "write" : "read", ADDRB);
end
end
//****************************************************
// Asynchronous collision checks
//****************************************************
end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll
// Delay A and B addresses in order to mimic setup/hold times
wire [C_ADDRA_WIDTH-1:0] #COLL_DELAY addra_delay = ADDRA;
wire [0:0] #COLL_DELAY wea_delay = wea_i;
wire #COLL_DELAY ena_delay = ena_i;
wire [C_ADDRB_WIDTH-1:0] #COLL_DELAY addrb_delay = ADDRB;
wire [0:0] #COLL_DELAY web_delay = web_i;
wire #COLL_DELAY enb_delay = enb_i;
// Do the checks w/rt A
always @(posedge CLKA) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision_a = 0;
end
end else begin
is_collision_a = 0;
end
if (ena_i && enb_delay) begin
if(wea_i || web_delay) begin
is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,
web_delay);
end else begin
is_collision_delay_a = 0;
end
end else begin
is_collision_delay_a = 0;
end
// Only flag if B access is a write
if (is_collision_a && web_i) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n",
wea_i ? "write" : "read", ADDRA, ADDRB);
end else if (is_collision_delay_a && web_delay) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n",
wea_i ? "write" : "read", ADDRA, addrb_delay);
end
end
// Do the checks w/rt B
always @(posedge CLKB) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision_b = 0;
end
end else begin
is_collision_b = 0;
end
if (ena_delay && enb_i) begin
if (wea_delay || web_i) begin
is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,
web_i);
end else begin
is_collision_delay_b = 0;
end
end else begin
is_collision_delay_b = 0;
end
// Only flag if A access is a write
if (is_collision_b && wea_i) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n",
ADDRA, web_i ? "write" : "read", ADDRB);
end else if (is_collision_delay_b && wea_delay) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n",
addra_delay, web_i ? "write" : "read", ADDRB);
end
end
end
endgenerate
endmodule
//*****************************************************************************
// Top module wraps Input register and Memory module
//
// This module is the top-level behavioral model and this implements the memory
// module and the input registers
//*****************************************************************************
module blk_mem_gen_v8_2
#(parameter C_CORENAME = "blk_mem_gen_v8_2",
parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_ELABORATION_DIR = "",
parameter C_INTERFACE_TYPE = 0,
parameter C_USE_BRAM_BLOCK = 0,
parameter C_CTRL_ECC_ALGO = "NONE",
parameter C_ENABLE_32BIT_ADDRESS = 0,
parameter C_AXI_TYPE = 0,
parameter C_AXI_SLAVE_TYPE = 0,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
parameter C_MEM_TYPE = 2,
parameter C_BYTE_SIZE = 9,
parameter C_ALGORITHM = 1,
parameter C_PRIM_TYPE = 3,
parameter C_LOAD_INIT_FILE = 0,
parameter C_INIT_FILE_NAME = "",
parameter C_INIT_FILE = "",
parameter C_USE_DEFAULT_DATA = 0,
parameter C_DEFAULT_DATA = "0",
//parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RSTA = 0,
parameter C_RST_PRIORITY_A = "CE",
parameter C_RSTRAM_A = 0,
parameter C_INITA_VAL = "0",
parameter C_HAS_ENA = 1,
parameter C_HAS_REGCEA = 0,
parameter C_USE_BYTE_WEA = 0,
parameter C_WEA_WIDTH = 1,
parameter C_WRITE_MODE_A = "WRITE_FIRST",
parameter C_WRITE_WIDTH_A = 32,
parameter C_READ_WIDTH_A = 32,
parameter C_WRITE_DEPTH_A = 64,
parameter C_READ_DEPTH_A = 64,
parameter C_ADDRA_WIDTH = 5,
parameter C_HAS_RSTB = 0,
parameter C_RST_PRIORITY_B = "CE",
parameter C_RSTRAM_B = 0,
parameter C_INITB_VAL = "",
parameter C_HAS_ENB = 1,
parameter C_HAS_REGCEB = 0,
parameter C_USE_BYTE_WEB = 0,
parameter C_WEB_WIDTH = 1,
parameter C_WRITE_MODE_B = "WRITE_FIRST",
parameter C_WRITE_WIDTH_B = 32,
parameter C_READ_WIDTH_B = 32,
parameter C_WRITE_DEPTH_B = 64,
parameter C_READ_DEPTH_B = 64,
parameter C_ADDRB_WIDTH = 5,
parameter C_HAS_MEM_OUTPUT_REGS_A = 0,
parameter C_HAS_MEM_OUTPUT_REGS_B = 0,
parameter C_HAS_MUX_OUTPUT_REGS_A = 0,
parameter C_HAS_MUX_OUTPUT_REGS_B = 0,
parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_MUX_PIPELINE_STAGES = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter C_EN_ECC_PIPE = 0,
parameter C_HAS_INJECTERR = 0,
parameter C_SIM_COLLISION_CHECK = "NONE",
parameter C_COMMON_CLK = 1,
parameter C_DISABLE_WARN_BHV_COLL = 0,
parameter C_EN_SLEEP_PIN = 0,
parameter C_USE_URAM = 0,
parameter C_EN_RDADDRA_CHG = 0,
parameter C_EN_RDADDRB_CHG = 0,
parameter C_EN_DEEPSLEEP_PIN = 0,
parameter C_EN_SHUTDOWN_PIN = 0,
parameter C_DISABLE_WARN_BHV_RANGE = 0,
parameter C_COUNT_36K_BRAM = "",
parameter C_COUNT_18K_BRAM = "",
parameter C_EST_POWER_SUMMARY = ""
)
(input clka,
input rsta,
input ena,
input regcea,
input [C_WEA_WIDTH-1:0] wea,
input [C_ADDRA_WIDTH-1:0] addra,
input [C_WRITE_WIDTH_A-1:0] dina,
output [C_READ_WIDTH_A-1:0] douta,
input clkb,
input rstb,
input enb,
input regceb,
input [C_WEB_WIDTH-1:0] web,
input [C_ADDRB_WIDTH-1:0] addrb,
input [C_WRITE_WIDTH_B-1:0] dinb,
output [C_READ_WIDTH_B-1:0] doutb,
input injectsbiterr,
input injectdbiterr,
output sbiterr,
output dbiterr,
output [C_ADDRB_WIDTH-1:0] rdaddrecc,
input eccpipece,
input sleep,
input deepsleep,
input shutdown,
//AXI BMG Input and Output Port Declarations
//AXI Global Signals
input s_aclk,
input s_aresetn,
//AXI Full/lite slave write (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input [31:0] s_axi_awaddr,
input [7:0] s_axi_awlen,
input [2:0] s_axi_awsize,
input [1:0] s_axi_awburst,
input s_axi_awvalid,
output s_axi_awready,
input [C_WRITE_WIDTH_A-1:0] s_axi_wdata,
input [C_WEA_WIDTH-1:0] s_axi_wstrb,
input s_axi_wlast,
input s_axi_wvalid,
output s_axi_wready,
output [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output [1:0] s_axi_bresp,
output s_axi_bvalid,
input s_axi_bready,
//AXI Full/lite slave read (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input [31:0] s_axi_araddr,
input [7:0] s_axi_arlen,
input [2:0] s_axi_arsize,
input [1:0] s_axi_arburst,
input s_axi_arvalid,
output s_axi_arready,
output [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output [C_WRITE_WIDTH_B-1:0] s_axi_rdata,
output [1:0] s_axi_rresp,
output s_axi_rlast,
output s_axi_rvalid,
input s_axi_rready,
//AXI Full/lite sideband signals
input s_axi_injectsbiterr,
input s_axi_injectdbiterr,
output s_axi_sbiterr,
output s_axi_dbiterr,
output [C_ADDRB_WIDTH-1:0] s_axi_rdaddrecc
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_CORENAME : Instance name of the Block Memory Generator core
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_MEM_TYPE : Designates memory type.
// It can be
// 0 - Single Port Memory
// 1 - Simple Dual Port Memory
// 2 - True Dual Port Memory
// 3 - Single Port Read Only Memory
// 4 - Dual Port Read Only Memory
// C_BYTE_SIZE : Size of a byte (8 or 9 bits)
// C_ALGORITHM : Designates the algorithm method used
// for constructing the memory.
// It can be Fixed_Primitives, Minimum_Area or
// Low_Power
// C_PRIM_TYPE : Designates the user selected primitive used to
// construct the memory.
//
// C_LOAD_INIT_FILE : Designates the use of an initialization file to
// initialize memory contents.
// C_INIT_FILE_NAME : Memory initialization file name.
// C_USE_DEFAULT_DATA : Designates whether to fill remaining
// initialization space with default data
// C_DEFAULT_DATA : Default value of all memory locations
// not initialized by the memory
// initialization file.
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RSTA : Determines the presence of the RSTA port
// C_RST_PRIORITY_A : Determines the priority between CE and SR for
// Port A.
// C_RSTRAM_A : Determines if special reset behavior is used for
// Port A
// C_INITA_VAL : The initialization value for Port A
// C_HAS_ENA : Determines the presence of the ENA port
// C_HAS_REGCEA : Determines the presence of the REGCEA port
// C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
// C_WEA_WIDTH : The width of the WEA port
// C_WRITE_MODE_A : Configurable write mode for Port A. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_A : Memory write width for Port A.
// C_READ_WIDTH_A : Memory read width for Port A.
// C_WRITE_DEPTH_A : Memory write depth for Port A.
// C_READ_DEPTH_A : Memory read depth for Port A.
// C_ADDRA_WIDTH : Width of the ADDRA input port
// C_HAS_RSTB : Determines the presence of the RSTB port
// C_RST_PRIORITY_B : Determines the priority between CE and SR for
// Port B.
// C_RSTRAM_B : Determines if special reset behavior is used for
// Port B
// C_INITB_VAL : The initialization value for Port B
// C_HAS_ENB : Determines the presence of the ENB port
// C_HAS_REGCEB : Determines the presence of the REGCEB port
// C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
// C_WEB_WIDTH : The width of the WEB port
// C_WRITE_MODE_B : Configurable write mode for Port B. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_B : Memory write width for Port B.
// C_READ_WIDTH_B : Memory read width for Port B.
// C_WRITE_DEPTH_B : Memory write depth for Port B.
// C_READ_DEPTH_B : Memory read depth for Port B.
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
// of the RAM primitive for Port A.
// C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive for Port B.
// C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
// of the MUX for Port A.
// C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
// of the MUX for Port B.
// C_HAS_SOFTECC_INPUT_REGS_A :
// C_HAS_SOFTECC_OUTPUT_REGS_B :
// C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
// between the muxes.
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// C_HAS_INJECTERR : Determines if the error injection pins
// are present or not. If the ECC feature
// is not used, this value is defaulted to
// 0, else the following are the allowed
// values:
// 0 : No INJECTSBITERR or INJECTDBITERR pins
// 1 : Only INJECTSBITERR pin exists
// 2 : Only INJECTDBITERR pin exists
// 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
// C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
// warnings. It can be "ALL", "NONE",
// "Warnings_Only" or "Generate_X_Only".
// C_COMMON_CLK : Determins if the core has a single CLK input.
// C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
// C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
// warnings
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLKA : Clock to synchronize all read and write operations of Port A.
// RSTA : Reset input to reset memory outputs to a user-defined
// reset state for Port A.
// ENA : Enable all read and write operations of Port A.
// REGCEA : Register Clock Enable to control each pipeline output
// register stages for Port A.
// WEA : Write Enable to enable all write operations of Port A.
// ADDRA : Address of Port A.
// DINA : Data input of Port A.
// DOUTA : Data output of Port A.
// CLKB : Clock to synchronize all read and write operations of Port B.
// RSTB : Reset input to reset memory outputs to a user-defined
// reset state for Port B.
// ENB : Enable all read and write operations of Port B.
// REGCEB : Register Clock Enable to control each pipeline output
// register stages for Port B.
// WEB : Write Enable to enable all write operations of Port B.
// ADDRB : Address of Port B.
// DINB : Data input of Port B.
// DOUTB : Data output of Port B.
// INJECTSBITERR : Single Bit ECC Error Injection Pin.
// INJECTDBITERR : Double Bit ECC Error Injection Pin.
// SBITERR : Output signal indicating that a Single Bit ECC Error has been
// detected and corrected.
// DBITERR : Output signal indicating that a Double Bit ECC Error has been
// detected.
// RDADDRECC : Read Address Output signal indicating address at which an
// ECC error has occurred.
//////////////////////////////////////////////////////////////////////////
wire SBITERR;
wire DBITERR;
wire S_AXI_AWREADY;
wire S_AXI_WREADY;
wire S_AXI_BVALID;
wire S_AXI_ARREADY;
wire S_AXI_RLAST;
wire S_AXI_RVALID;
wire S_AXI_SBITERR;
wire S_AXI_DBITERR;
wire [C_WEA_WIDTH-1:0] WEA = wea;
wire [C_ADDRA_WIDTH-1:0] ADDRA = addra;
wire [C_WRITE_WIDTH_A-1:0] DINA = dina;
wire [C_READ_WIDTH_A-1:0] DOUTA;
wire [C_WEB_WIDTH-1:0] WEB = web;
wire [C_ADDRB_WIDTH-1:0] ADDRB = addrb;
wire [C_WRITE_WIDTH_B-1:0] DINB = dinb;
wire [C_READ_WIDTH_B-1:0] DOUTB;
wire [C_ADDRB_WIDTH-1:0] RDADDRECC;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID = s_axi_awid;
wire [31:0] S_AXI_AWADDR = s_axi_awaddr;
wire [7:0] S_AXI_AWLEN = s_axi_awlen;
wire [2:0] S_AXI_AWSIZE = s_axi_awsize;
wire [1:0] S_AXI_AWBURST = s_axi_awburst;
wire [C_WRITE_WIDTH_A-1:0] S_AXI_WDATA = s_axi_wdata;
wire [C_WEA_WIDTH-1:0] S_AXI_WSTRB = s_axi_wstrb;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID;
wire [1:0] S_AXI_BRESP;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID = s_axi_arid;
wire [31:0] S_AXI_ARADDR = s_axi_araddr;
wire [7:0] S_AXI_ARLEN = s_axi_arlen;
wire [2:0] S_AXI_ARSIZE = s_axi_arsize;
wire [1:0] S_AXI_ARBURST = s_axi_arburst;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID;
wire [C_WRITE_WIDTH_B-1:0] S_AXI_RDATA;
wire [1:0] S_AXI_RRESP;
wire [C_ADDRB_WIDTH-1:0] S_AXI_RDADDRECC;
// Added to fix the simulation warning #CR731605
wire [C_WEB_WIDTH-1:0] WEB_parameterized = 0;
wire ECCPIPECE;
wire SLEEP;
assign CLKA = clka;
assign RSTA = rsta;
assign ENA = ena;
assign REGCEA = regcea;
assign CLKB = clkb;
assign RSTB = rstb;
assign ENB = enb;
assign REGCEB = regceb;
assign INJECTSBITERR = injectsbiterr;
assign INJECTDBITERR = injectdbiterr;
assign ECCPIPECE = eccpipece;
assign SLEEP = sleep;
assign sbiterr = SBITERR;
assign dbiterr = DBITERR;
assign S_ACLK = s_aclk;
assign S_ARESETN = s_aresetn;
assign S_AXI_AWVALID = s_axi_awvalid;
assign s_axi_awready = S_AXI_AWREADY;
assign S_AXI_WLAST = s_axi_wlast;
assign S_AXI_WVALID = s_axi_wvalid;
assign s_axi_wready = S_AXI_WREADY;
assign s_axi_bvalid = S_AXI_BVALID;
assign S_AXI_BREADY = s_axi_bready;
assign S_AXI_ARVALID = s_axi_arvalid;
assign s_axi_arready = S_AXI_ARREADY;
assign s_axi_rlast = S_AXI_RLAST;
assign s_axi_rvalid = S_AXI_RVALID;
assign S_AXI_RREADY = s_axi_rready;
assign S_AXI_INJECTSBITERR = s_axi_injectsbiterr;
assign S_AXI_INJECTDBITERR = s_axi_injectdbiterr;
assign s_axi_sbiterr = S_AXI_SBITERR;
assign s_axi_dbiterr = S_AXI_DBITERR;
assign doutb = DOUTB;
assign douta = DOUTA;
assign rdaddrecc = RDADDRECC;
assign s_axi_bid = S_AXI_BID;
assign s_axi_bresp = S_AXI_BRESP;
assign s_axi_rid = S_AXI_RID;
assign s_axi_rdata = S_AXI_RDATA;
assign s_axi_rresp = S_AXI_RRESP;
assign s_axi_rdaddrecc = S_AXI_RDADDRECC;
localparam FLOP_DELAY = 100; // 100 ps
reg injectsbiterr_in;
reg injectdbiterr_in;
reg rsta_in;
reg ena_in;
reg regcea_in;
reg [C_WEA_WIDTH-1:0] wea_in;
reg [C_ADDRA_WIDTH-1:0] addra_in;
reg [C_WRITE_WIDTH_A-1:0] dina_in;
wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;
wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;
wire s_axi_wr_en_c;
wire s_axi_rd_en_c;
wire s_aresetn_a_c;
wire [7:0] s_axi_arlen_c ;
wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;
wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;
wire [1:0] s_axi_rresp_c;
wire s_axi_rlast_c;
wire s_axi_rvalid_c;
wire s_axi_rready_c;
wire regceb_c;
localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;
wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;
wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;
//**************
// log2roundup
//**************
function integer log2roundup (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
if (data_value > 1) begin
for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin
width = width + 1;
end //loop
end //if
log2roundup = width;
end //log2roundup
endfunction
//**************
// log2int
//**************
function integer log2int (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
cnt= data_value;
for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin
width = width + 1;
end //loop
log2int = width;
end //log2int
endfunction
//**************************************************************************
// FUNCTION : divroundup
// Returns the ceiling value of the division
// Data_value - the quantity to be divided, dividend
// Divisor - the value to divide the data_value by
//**************************************************************************
function integer divroundup (input integer data_value,input integer divisor);
integer div;
begin
div = data_value/divisor;
if ((data_value % divisor) != 0) begin
div = div+1;
end //if
divroundup = div;
end //if
endfunction
localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);
localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);
localparam C_AXI_ADDR_WIDTH = C_AXI_ADDR_WIDTH_MSB;
//Data Width Number of LSB address bits to be discarded
//1 to 16 1
//17 to 32 2
//33 to 64 3
//65 to 128 4
//129 to 256 5
//257 to 512 6
//513 to 1024 7
// The following two constants determine this.
localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));
localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);
localparam C_AXI_OS_WR = 2;
//***********************************************
// INPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage
always @* begin
injectsbiterr_in = INJECTSBITERR;
injectdbiterr_in = INJECTDBITERR;
rsta_in = RSTA;
ena_in = ENA;
regcea_in = REGCEA;
wea_in = WEA;
addra_in = ADDRA;
dina_in = DINA;
end //end always
end //end no_softecc_input_reg_stage
endgenerate
generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage
always @(posedge CLKA) begin
injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;
injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;
rsta_in <= #FLOP_DELAY RSTA;
ena_in <= #FLOP_DELAY ENA;
regcea_in <= #FLOP_DELAY REGCEA;
wea_in <= #FLOP_DELAY WEA;
addra_in <= #FLOP_DELAY ADDRA;
dina_in <= #FLOP_DELAY DINA;
end //end always
end //end input_reg_stages generate statement
endgenerate
generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module
BLK_MEM_GEN_v8_2_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_ALGORITHM (C_ALGORITHM),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (C_HAS_ENA),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (C_USE_BYTE_WEA),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (C_HAS_ENB),
.C_HAS_REGCEB (C_HAS_REGCEB),
.C_USE_BYTE_WEB (C_USE_BYTE_WEB),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A),
.C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_2_inst
(.CLKA (CLKA),
.RSTA (rsta_in),
.ENA (ena_in),
.REGCEA (regcea_in),
.WEA (wea_in),
.ADDRA (addra_in),
.DINA (dina_in),
.DOUTA (DOUTA),
.CLKB (CLKB),
.RSTB (RSTB),
.ENB (ENB),
.REGCEB (REGCEB),
.WEB (WEB),
.ADDRB (ADDRB),
.DINB (DINB),
.DOUTB (DOUTB),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.ECCPIPECE (ECCPIPECE),
.SLEEP (SLEEP),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.RDADDRECC (RDADDRECC)
);
end
endgenerate
generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module
localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);
localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);
localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);
localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);
// localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);
// localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);
localparam C_MEM_MAP_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_MSB;
localparam C_MEM_MAP_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_MSB;
// Data Width Number of LSB address bits to be discarded
// 1 to 16 1
// 17 to 32 2
// 33 to 64 3
// 65 to 128 4
// 129 to 256 5
// 257 to 512 6
// 513 to 1024 7
// The following two constants determine this.
localparam MEM_MAP_LOWER_BOUND_VAL_A = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));
localparam MEM_MAP_LOWER_BOUND_VAL_B = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));
localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;
localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;
wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;
wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;
wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;
assign msb_zero_i = 0;
assign lsb_zero_i = 0;
assign RDADDRECC = {msb_zero_i,rdaddrecc_i,lsb_zero_i};
BLK_MEM_GEN_v8_2_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_ALGORITHM (C_ALGORITHM),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (C_HAS_ENA),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (C_USE_BYTE_WEA),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH_ACTUAL),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (C_HAS_ENB),
.C_HAS_REGCEB (C_HAS_REGCEB),
.C_USE_BYTE_WEB (C_USE_BYTE_WEB),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH_ACTUAL),
.C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A),
.C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_2_inst
(.CLKA (CLKA),
.RSTA (rsta_in),
.ENA (ena_in),
.REGCEA (regcea_in),
.WEA (wea_in),
.ADDRA (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),
.DINA (dina_in),
.DOUTA (DOUTA),
.CLKB (CLKB),
.RSTB (RSTB),
.ENB (ENB),
.REGCEB (REGCEB),
.WEB (WEB),
.ADDRB (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),
.DINB (DINB),
.DOUTB (DOUTB),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.ECCPIPECE (ECCPIPECE),
.SLEEP (SLEEP),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.RDADDRECC (rdaddrecc_i)
);
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs
assign S_AXI_RDATA = s_axi_rdata_c;
assign S_AXI_RLAST = s_axi_rlast_c;
assign S_AXI_RVALID = s_axi_rvalid_c;
assign S_AXI_RID = s_axi_rid_c;
assign S_AXI_RRESP = s_axi_rresp_c;
assign s_axi_rready_c = S_AXI_RREADY;
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb
assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb
assign regceb_c = REGCEB;
end
endgenerate
generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs
assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};
assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];
assign S_AXI_RDATA = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];
assign S_AXI_RRESP = m_axi_payload_c[2:1];
assign S_AXI_RLAST = m_axi_payload_c[0];
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs
assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};
assign S_AXI_RDATA = s_axi_rdata_c;
assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];
assign S_AXI_RRESP = m_axi_payload_c[2:1];
assign S_AXI_RLAST = m_axi_payload_c[0];
end
endgenerate
generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd
blk_mem_axi_regs_fwd_v8_2
#(.C_DATA_WIDTH (C_AXI_PAYLOAD))
axi_regs_inst (
.ACLK (S_ACLK),
.ARESET (s_aresetn_a_c),
.S_VALID (s_axi_rvalid_c),
.S_READY (s_axi_rready_c),
.S_PAYLOAD_DATA (s_axi_payload_c),
.M_VALID (S_AXI_RVALID),
.M_READY (S_AXI_RREADY),
.M_PAYLOAD_DATA (m_axi_payload_c)
);
end
endgenerate
generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module
assign s_aresetn_a_c = !S_ARESETN;
assign S_AXI_BRESP = 2'b00;
assign s_axi_rresp_c = 2'b00;
assign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;
blk_mem_axi_write_wrapper_beh_v8_2
#(.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE),
.C_MEMORY_TYPE (C_MEM_TYPE),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_AXI_AWADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
.C_HAS_AXI_ID (C_HAS_AXI_ID),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_AXI_WDATA_WIDTH (C_WRITE_WIDTH_A),
.C_AXI_OS_WR (C_AXI_OS_WR))
axi_wr_fsm (
// AXI Global Signals
.S_ACLK (S_ACLK),
.S_ARESETN (s_aresetn_a_c),
// AXI Full/Lite Slave Write interface
.S_AXI_AWADDR (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
.S_AXI_BID (S_AXI_BID),
// Signals for BRAM interfac(
.S_AXI_AWADDR_OUT (s_axi_awaddr_out_c),
.S_AXI_WR_EN (s_axi_wr_en_c)
);
blk_mem_axi_read_wrapper_beh_v8_2
#(.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE),
.C_MEMORY_TYPE (C_MEM_TYPE),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_AXI_PIPELINE_STAGES (1),
.C_AXI_ARADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
.C_HAS_AXI_ID (C_HAS_AXI_ID),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH))
axi_rd_sm(
//AXI Global Signals
.S_ACLK (S_ACLK),
.S_ARESETN (s_aresetn_a_c),
//AXI Full/Lite Read Side
.S_AXI_ARADDR (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),
.S_AXI_ARLEN (s_axi_arlen_c),
.S_AXI_ARSIZE (S_AXI_ARSIZE),
.S_AXI_ARBURST (S_AXI_ARBURST),
.S_AXI_ARVALID (S_AXI_ARVALID),
.S_AXI_ARREADY (S_AXI_ARREADY),
.S_AXI_RLAST (s_axi_rlast_c),
.S_AXI_RVALID (s_axi_rvalid_c),
.S_AXI_RREADY (s_axi_rready_c),
.S_AXI_ARID (S_AXI_ARID),
.S_AXI_RID (s_axi_rid_c),
//AXI Full/Lite Read FSM Outputs
.S_AXI_ARADDR_OUT (s_axi_araddr_out_c),
.S_AXI_RD_EN (s_axi_rd_en_c)
);
BLK_MEM_GEN_v8_2_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_ALGORITHM (C_ALGORITHM),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (1),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (1),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (1),
.C_HAS_REGCEB (C_HAS_MEM_OUTPUT_REGS_B),
.C_USE_BYTE_WEB (1),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS_A (0),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (0),
.C_HAS_MUX_OUTPUT_REGS_B (0),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (0),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_2_inst
(.CLKA (S_ACLK),
.RSTA (s_aresetn_a_c),
.ENA (s_axi_wr_en_c),
.REGCEA (regcea_in),
.WEA (S_AXI_WSTRB),
.ADDRA (s_axi_awaddr_out_c),
.DINA (S_AXI_WDATA),
.DOUTA (DOUTA),
.CLKB (S_ACLK),
.RSTB (s_aresetn_a_c),
.ENB (s_axi_rd_en_c),
.REGCEB (regceb_c),
.WEB (WEB_parameterized),
.ADDRB (s_axi_araddr_out_c),
.DINB (DINB),
.DOUTB (s_axi_rdata_c),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.ECCPIPECE (1'b0),
.SLEEP (1'b0),
.RDADDRECC (RDADDRECC)
);
end
endgenerate
endmodule
|
// This is a component of pluto_servo, a PWM servo driver and quadrature
// counter for emc2
// Copyright 2006 Jeff Epler <[email protected]>
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
module main(clk, led, nConfig, epp_nReset, pport_data, nWrite, nWait, nDataStr,
nAddrStr, dout, din, step, dir);
parameter W=10;
parameter F=11;
parameter T=4;
input clk;
output led, nConfig;
inout [7:0] pport_data;
input nWrite;
output nWait;
input nDataStr, nAddrStr, epp_nReset;
input [15:0] din;
reg Spolarity;
reg[13:0] real_dout; output [13:0] dout = do_tristate ? 14'bZ : real_dout;
wire[3:0] real_step; output [3:0] step = do_tristate ? 4'bZ : real_step ^ {4{Spolarity}};
wire[3:0] real_dir; output [3:0] dir = do_tristate ? 4'bZ : real_dir;
wire [W+F-1:0] pos0, pos1, pos2, pos3;
reg [F:0] vel0, vel1, vel2, vel3;
reg [T-1:0] dirtime, steptime;
reg [1:0] tap;
reg [10:0] div2048;
wire stepcnt = ~|(div2048[5:0]);
always @(posedge clk) begin
div2048 <= div2048 + 1'd1;
end
wire do_enable_wdt, do_tristate;
wdt w(clk, do_enable_wdt, &div2048, do_tristate);
stepgen #(W,F,T) s0(clk, stepcnt, pos0, vel0, dirtime, steptime, real_step[0], real_dir[0], tap);
stepgen #(W,F,T) s1(clk, stepcnt, pos1, vel1, dirtime, steptime, real_step[1], real_dir[1], tap);
stepgen #(W,F,T) s2(clk, stepcnt, pos2, vel2, dirtime, steptime, real_step[2], real_dir[2], tap);
stepgen #(W,F,T) s3(clk, stepcnt, pos3, vel3, dirtime, steptime, real_step[3], real_dir[3], tap);
// EPP stuff
wire EPP_write = ~nWrite;
wire EPP_read = nWrite;
wire EPP_addr_strobe = ~nAddrStr;
wire EPP_data_strobe = ~nDataStr;
wire EPP_strobe = EPP_data_strobe | EPP_addr_strobe;
wire EPP_wait; assign nWait = ~EPP_wait;
wire [7:0] EPP_datain = pport_data;
wire [7:0] EPP_dataout; assign pport_data = EPP_dataout;
reg [4:0] EPP_strobe_reg;
always @(posedge clk) EPP_strobe_reg <= {EPP_strobe_reg[3:0], EPP_strobe};
wire EPP_strobe_edge1 = (EPP_strobe_reg[2:1]==2'b01);
// reg led;
assign EPP_wait = EPP_strobe_reg[4];
wire[15:0] EPP_dataword = {EPP_datain, lowbyte};
reg[4:0] addr_reg;
reg[7:0] lowbyte;
always @(posedge clk)
if(EPP_strobe_edge1 & EPP_write & EPP_addr_strobe) begin
addr_reg <= EPP_datain[4:0];
end
else if(EPP_strobe_edge1 & !EPP_addr_strobe) addr_reg <= addr_reg + 4'd1;
always @(posedge clk) begin
if(EPP_strobe_edge1 & EPP_write & EPP_data_strobe) begin
if(addr_reg[3:0] == 4'd1) vel0 <= EPP_dataword[F:0];
else if(addr_reg[3:0] == 4'd3) vel1 <= EPP_dataword[F:0];
else if(addr_reg[3:0] == 4'd5) vel2 <= EPP_dataword[F:0];
else if(addr_reg[3:0] == 4'd7) vel3 <= EPP_dataword[F:0];
else if(addr_reg[3:0] == 4'd9) begin
real_dout <= { EPP_datain[5:0], lowbyte };
end
else if(addr_reg[3:0] == 4'd11) begin
tap <= lowbyte[7:6];
steptime <= lowbyte[T-1:0];
Spolarity <= EPP_datain[7];
// EPP_datain[6] is do_enable_wdt
dirtime <= EPP_datain[T-1:0];
end
else lowbyte <= EPP_datain;
end
end
reg [31:0] data_buf;
always @(posedge clk) begin
if(EPP_strobe_edge1 & EPP_read && addr_reg[1:0] == 2'd0) begin
if(addr_reg[4:2] == 3'd0) data_buf <= pos0;
else if(addr_reg[4:2] == 3'd1) data_buf <= pos1;
else if(addr_reg[4:2] == 3'd2) data_buf <= pos2;
else if(addr_reg[4:2] == 3'd3) data_buf <= pos3;
else if(addr_reg[4:2] == 3'd4)
data_buf <= din;
end
end
// the addr_reg test looks funny because it is auto-incremented in an always
// block so "1" reads the low byte, "2 and "3" read middle bytes, and "0"
// reads the high byte I have a feeling that I'm doing this in the wrong way.
wire [7:0] data_reg = addr_reg[1:0] == 2'd1 ? data_buf[7:0] :
(addr_reg[1:0] == 2'd2 ? data_buf[15:8] :
(addr_reg[1:0] == 2'd3 ? data_buf[23:16] :
data_buf[31:24]));
wire [7:0] EPP_data_mux = data_reg;
assign EPP_dataout = (EPP_read & EPP_wait) ? EPP_data_mux : 8'hZZ;
// assign do_enable_wdt = EPP_strobe_edge1 & EPP_write & EPP_data_strobe & (addr_reg[3:0] == 4'd9) & EPP_datain[6];
// assign led = do_tristate ? 1'BZ : (real_step[0] ^ real_dir[0]);
assign led = do_tristate ? 1'bZ : (real_step[0] ^ real_dir[0]);
assign nConfig = epp_nReset; // 1'b1;
assign do_enable_wdt = EPP_strobe_edge1 & EPP_write & EPP_data_strobe & (addr_reg[3:0] == 4'd9) & EPP_datain[6];
endmodule
|
//Com2DocHDL
/*
:Project
FPGA-Imaging-Library
:Design
VGA
:Function
Show with VGA.
:Module
Main module
:Version
1.0
:Modified
2015-05-12
Copyright (C) 2015 Tianyu Dai (dtysky) <[email protected]>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
http://fil.dtysky.moe
Sources for this project:
https://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
[email protected]
My blog:
http://dtysky.moe
*/
`timescale 1ns / 1ps
module VGA640x480(
clk_25m,
rst_n,
in_data,
vga_red,
vga_green,
vga_blue,
vga_hsync,
vga_vsync,
frame_addr
);
input clk_25m;
input rst_n;
input [15 : 0] in_data;
output reg[4:0] vga_red;
output reg[5:0] vga_green;
output reg[4:0] vga_blue;
output reg vga_hsync;
output reg vga_vsync;
output [16:0] frame_addr;
reg[9:0] con_h;
reg[9:0] con_v;
reg[16:0] address;
reg blank;
parameter hRez = 640;
parameter hStartSync = 640+16;
parameter hEndSync = 640+16+96;
parameter hMaxCount = 800;
parameter vRez = 480;
parameter vStartSync = 480+10;
parameter vEndSync = 480+10+2;
parameter vMaxCount = 480+10+2+33;
parameter hsync_active =0;
parameter vsync_active = 0;
assign frame_addr = address;
always @(posedge clk_25m or negedge rst_n) begin
if(~rst_n) begin
con_h <= 0;
con_v <= 0;
end else if(con_h == hMaxCount-1) begin
con_h <= 10'b0;
if (con_v == vMaxCount-1 )
con_v <= 10'b0;
else
con_v <= con_v+1;
end else
con_h <= con_h+1;
end
always @(posedge clk_25m or negedge rst_n) begin
if(~rst_n) begin
vga_red <= 0;
vga_green <= 0;
vga_blue <= 0;
end else if (blank ==0) begin
vga_red <= in_data[15:11];
vga_green <= in_data[10:5];
vga_blue <= in_data[4:0];
end else begin
vga_red <= 0;
vga_green <= 0;
vga_blue <= 0;
end;
end
always @(posedge clk_25m or negedge rst_n) begin
if(~rst_n) begin
address <= 17'b0;
blank <= 1;
end else if (con_v >= 360 || con_v < 120) begin
address <= 17'b0;
blank <= 1;
end else begin
if (con_h < 480 && con_h >= 160) begin
blank <= 0;
address <= address+1;
end else blank <= 1;
end;
end
always @(posedge clk_25m) begin
if( con_h > hStartSync && con_h <= hEndSync)
vga_hsync <= hsync_active;
else
vga_hsync <= ~ hsync_active;
end
always @(posedge clk_25m) begin
if( con_v >= vStartSync && con_v < vEndSync )
vga_vsync <= vsync_active;
else
vga_vsync <= ~ vsync_active;
end
endmodule |
module k_nns_seq_td
#
(
parameter W = 32,
parameter K = 10
)
(
clk,
rst,
g_input,
e_input,
o
);
function integer log2;
input [31:0] value;
reg [31:0] temp;
begin
temp = value;
for (log2=0; temp>0; log2=log2+1)
temp = temp>>1;
end
endfunction
localparam LOGW = log2(W);
input clk;
input rst;
input [2*W-1:0] g_input, e_input;
output [2*W*K-1:0] o;
wire [W-1:0] x1, y1, x2, y2;
wire [2*W*K-1:0] min_val_out;
assign x1 = e_input[2*W-1:W];
assign y1 = e_input[W-1:0];
assign x2 = g_input[2*W-1:W];
assign y2 = g_input[W-1:0];
assign min_val_out = o;
wire [W+1:0] dist;
wire [2*W-1:0] min_val [K-1:0];
wire [W+1:0] min_dist [K-1:0];
reg [2*W-1:0] min_val_reg [K-1:0];
reg [W+1:0] min_dist_reg [K-1:0];
wire gt_dist_1 [K-1:0];
wire gt_dist_2 [K-1:0];
wire [W-1:0] local_min_val_x [K:0];
wire [W-1:0] local_min_val_y [K:0];
wire [W+1:0] local_min_dist [K:0];
genvar i;
generate
for (i=0;i<K;i=i+1)
begin:D_ASN
assign min_val_out[2*W*(i+1)-1:2*W*i] = min_val[i];
end
endgenerate
taxicab_distance
#(
.N(W)
)
taxicab_distance_
(
.x1(x1), .y1(y1), .x2(x2), .y2(y2),
.dist(dist)
);
generate
for (i=0;i<K;i=i+1)
begin:COMP_ASN
COMP
#(
.N(W+2)
)
COMP_1
(
.A(min_dist_reg[i]),
.B(local_min_dist[i+1]),
.O(gt_dist_1[i])
);
if(i>0)
begin
COMP
#(
.N(W+2)
)
COMP_2
(
.A(min_dist_reg[i-1]),
.B(local_min_dist[i]),
.O(gt_dist_2[i])
);
end
else
begin
assign gt_dist_2[i] = 0;
end
end
endgenerate
generate
for (i=0;i<K;i=i+1)
begin:MUX_ASN
MUX
#(
.N(W+2)
)
MUX_1
(
.A(min_dist_reg[i]),
.B(local_min_dist[i+1]),
.S(gt_dist_1[i]),
.O(local_min_dist[i])
);
if(i>0)
begin
MUX
#(
.N(W+2)
)
MUX_2
(
.A(local_min_dist[i]),
.B(min_dist_reg[i-1]),
.S(gt_dist_2[i]),
.O(min_dist[i])
);
end
else
begin
assign min_dist[i] = local_min_dist[i];
end
MUX
#(
.N(2*W)
)
MUX_3
(
.A(min_val_reg[i]),
.B({local_min_val_x[i+1], local_min_val_y[i+1]}),
.S(gt_dist_1[i]),
.O({local_min_val_x[i], local_min_val_y[i]})
);
if(i>0)
begin
MUX
#(
.N(2*W)
)
MUX_4
(
.A({local_min_val_x[i], local_min_val_y[i]}),
.B(min_val_reg[i-1]),
.S(gt_dist_2[i]),
.O(min_val[i])
);
end
else
begin
assign min_val[i] = {local_min_val_x[i], local_min_val_y[i]};
end
end
endgenerate
assign local_min_dist[K] = dist;
assign local_min_val_x[K] = x2;
assign local_min_val_y[K] = y2;
integer j;
always@(posedge clk or posedge rst)
begin
if(rst)
begin
for(j=0;j<K;j=j+1)
begin
min_val_reg[j] <= 0;
min_dist_reg[j] <= {(W+2){1'b1}};
end
end
else
begin
for(j=0;j<K;j=j+1)
begin
min_val_reg[j] <= min_val[j];
min_dist_reg[j] <= min_dist[j];
end
end
end
endmodule
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
//////////////////////////////////////////////////////////////////////////////////
// Company: Microsoft Research Asia
// Engineer: Jiansong Zhang
//
// Create Date: 21:39:39 06/01/2009
// Design Name:
// Module Name: rx_trn_data_fsm
// Project Name: Sora
// Target Devices: Virtex5 LX50T
// Tool versions: ISE10.1.03
// Description:
// Purpose: Receive TRN Data FSM. This module interfaces to the Block Plus RX
// TRN. It presents the 64-bit data from completer and and forwards that
// data with a data_valid signal. This block also decodes packet header info
// and forwards it to the rx_trn_monitor block.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module rx_trn_data_fsm(
input wire clk,
input wire rst,
// Rx Local-Link
input wire [63:0] trn_rd,
input wire [7:0] trn_rrem_n,
input wire trn_rsof_n,
input wire trn_reof_n,
input wire trn_rsrc_rdy_n,
input wire trn_rsrc_dsc_n,
output reg trn_rdst_rdy_n,
input wire trn_rerrfwd_n,
output wire trn_rnp_ok_n,
input wire [6:0] trn_rbar_hit_n,
input wire [11:0] trn_rfc_npd_av,
input wire [7:0] trn_rfc_nph_av,
input wire [11:0] trn_rfc_pd_av,
input wire [7:0] trn_rfc_ph_av,
input wire [11:0] trn_rfc_cpld_av,
input wire [7:0] trn_rfc_cplh_av,
output wire trn_rcpl_streaming_n,
//DATA FIFO SIGNALS
output reg [63:0] data_out,
output wire [7:0] data_out_be,
output reg data_valid,
input wire data_fifo_status,
//END DATA FIFO SIGNALS
//HEADER FIELD SIGNALS
//The following are registered from the header fields of the current packet
//See the PCIe Base Specification for definitions of these headers
output reg fourdw_n_threedw, //fourdw = 1'b1; 3dw = 1'b0;
output reg payload,
output reg [2:0] tc, //traffic class
output reg td, //digest
output reg ep, //poisoned bit
output reg [1:0] attr, //attribute field
output reg [9:0] dw_length, //DWORD Length
//the following fields are dependent on the type of TLP being received
//regs with MEM prefix are valid for memory TLPS and regs with CMP prefix
//are valid for completion TLPS
output reg [15:0] MEM_req_id, //requester ID for memory TLPs
output reg [7:0] MEM_tag, //tag for non-posted memory read request
output reg [15:0] CMP_comp_id, //completer id for completion TLPs
output reg [2:0]CMP_compl_stat, //status for completion TLPs
output reg CMP_bcm, //byte count modified field for completions TLPs
output reg [11:0] CMP_byte_count, //remaining byte count for completion TLPs
output reg [63:0] MEM_addr, //address field for memory TLPs
output reg [15:0] CMP_req_id, //requester if for completions TLPs
output reg [7:0] CMP_tag, //tag field for completion TLPs
output reg [6:0] CMP_lower_addr, //lower address field for completion TLPs
//decode of the format field
output wire MRd, //Mem read
output wire MWr, //Mem write
output wire CplD, //Completion w/ data
output wire Msg, //Message TLP
output wire UR, //Unsupported request TLP i.e. IO, CPL,etc..
output reg [6:0] bar_hit, //valid when a BAR is hit
output reg header_fields_valid//valid signal to qualify the above header fields
//END HEADER FIELD SIGNALS
);
//state machine states
localparam IDLE = 3'b000;
localparam NOT_READY = 3'b001;
localparam SOF = 3'b010;
localparam HEAD2 = 3'b011;
localparam BODY = 3'b100;
localparam EOF = 3'b101;
//additional pipelines regs for RX TRN interface
reg [63:0] trn_rd_d1;
reg [7:0] trn_rrem_d1_n;
reg trn_rsof_d1_n;
reg trn_reof_d1_n;
reg trn_rsrc_rdy_d1_n;
reg trn_rsrc_dsc_d1_n;
reg trn_rerrfwd_d1_n;
reg [6:0] trn_rbar_hit_d1_n;
reg [11:0] trn_rfc_npd_av_d1;
reg [7:0] trn_rfc_nph_av_d1;
reg [11:0] trn_rfc_pd_av_d1;
reg [7:0] trn_rfc_ph_av_d1;
reg [11:0] trn_rfc_cpld_av_d1;
reg [7:0] trn_rfc_cplh_av_d1;
//second pipeline
reg [63:0] trn_rd_d2;
reg [7:0] trn_rrem_d2_n;
reg trn_rsof_d2_n;
reg trn_reof_d2_n;
reg trn_rsrc_rdy_d2_n;
reg trn_rsrc_dsc_d2_n;
reg trn_rerrfwd_d2_n;
reg [6:0] trn_rbar_hit_d2_n;
reg [11:0] trn_rfc_npd_av_d2;
reg [7:0] trn_rfc_nph_av_d2;
reg [11:0] trn_rfc_pd_av_d2;
reg [7:0] trn_rfc_ph_av_d2;
reg [11:0] trn_rfc_cpld_av_d2;
reg [7:0] trn_rfc_cplh_av_d2;
reg [4:0] rx_packet_type;
reg [2:0] trn_state;
wire [63:0] data_out_mux;
wire [7:0] data_out_be_mux;
reg data_valid_early;
reg rst_reg;
always@(posedge clk) rst_reg <= rst;
// TIE constant signals here
assign trn_rnp_ok_n = 1'b0;
assign trn_rcpl_streaming_n = 1'b0; //use completion streaming mode
//all the outputs of the endpoint should be pipelined
//to help meet required timing of an 8 lane design
always @ (posedge clk)
begin
trn_rd_d1[63:0] <= trn_rd[63:0] ;
trn_rrem_d1_n[7:0] <= trn_rrem_n[7:0] ;
trn_rsof_d1_n <= trn_rsof_n ;
trn_reof_d1_n <= trn_reof_n ;
trn_rsrc_rdy_d1_n <= trn_rsrc_rdy_n ;
trn_rsrc_dsc_d1_n <= trn_rsrc_dsc_n ;
trn_rerrfwd_d1_n <= trn_rerrfwd_n ;
trn_rbar_hit_d1_n[6:0] <= trn_rbar_hit_n[6:0] ;
trn_rfc_npd_av_d1[11:0] <= trn_rfc_npd_av[11:0] ;
trn_rfc_nph_av_d1[7:0] <= trn_rfc_nph_av[7:0] ;
trn_rfc_pd_av_d1[11:0] <= trn_rfc_pd_av[11:0] ;
trn_rfc_ph_av_d1[7:0] <= trn_rfc_ph_av[7:0] ;
trn_rfc_cpld_av_d1[11:0] <= trn_rfc_cpld_av[11:0];
trn_rfc_cplh_av_d1[7:0] <= trn_rfc_cplh_av[7:0] ;
trn_rd_d2[63:0] <= trn_rd_d1[63:0] ;
trn_rrem_d2_n[7:0] <= trn_rrem_d1_n[7:0] ;
trn_rsof_d2_n <= trn_rsof_d1_n ;
trn_reof_d2_n <= trn_reof_d1_n ;
trn_rsrc_rdy_d2_n <= trn_rsrc_rdy_d1_n ;
trn_rsrc_dsc_d2_n <= trn_rsrc_dsc_d1_n ;
trn_rerrfwd_d2_n <= trn_rerrfwd_d1_n ;
trn_rbar_hit_d2_n[6:0] <= trn_rbar_hit_d1_n[6:0] ;
trn_rfc_npd_av_d2[11:0] <= trn_rfc_npd_av_d1[11:0] ;
trn_rfc_nph_av_d2[7:0] <= trn_rfc_nph_av_d1[7:0] ;
trn_rfc_pd_av_d2[11:0] <= trn_rfc_pd_av_d1[11:0] ;
trn_rfc_ph_av_d2[7:0] <= trn_rfc_ph_av_d1[7:0] ;
trn_rfc_cpld_av_d2[11:0] <= trn_rfc_cpld_av_d1[11:0];
trn_rfc_cplh_av_d2[7:0] <= trn_rfc_cplh_av_d1[7:0] ;
end
assign rx_sof_d1 = ~trn_rsof_d1_n & ~trn_rsrc_rdy_d1_n;
// Assign packet type information about the current RX Packet
// rx_packet_type is decoded in always block directly below these assigns
assign MRd = rx_packet_type[4];
assign MWr = rx_packet_type[3];
assign CplD = rx_packet_type[2];
assign Msg = rx_packet_type[1];
assign UR = rx_packet_type[0];
//register the packet header fields and decode the packet type
//both memory and completion TLP header fields are registered for each
//received packet, however, only the fields for the incoming type will be
//valid
always@(posedge clk )
begin
if(rst_reg)begin
rx_packet_type[4:0] <= 5'b00000;
fourdw_n_threedw <= 0;
payload <= 0;
tc[2:0] <= 0; //traffic class
td <= 0; //digest
ep <= 0; //poisoned bit
attr[1:0] <= 0;
dw_length[9:0] <= 0;
MEM_req_id[15:0] <= 0;
MEM_tag[7:0] <= 0;
CMP_comp_id[15:0] <= 0;
CMP_compl_stat[2:0] <= 0;
CMP_bcm <= 0;
CMP_byte_count[11:0] <= 0;
end else begin
if(rx_sof_d1)begin
//these fields same for all TLPs
fourdw_n_threedw <= trn_rd_d1[61];
payload <= trn_rd_d1[62];
tc[2:0] <= trn_rd_d1[54:52]; //traffic class
td <= trn_rd_d1[47]; //digest
ep <= trn_rd_d1[46]; //poisoned bit
attr[1:0] <= trn_rd_d1[45:44];
dw_length[9:0] <= trn_rd_d1[41:32];
//also latch bar_hit
bar_hit[6:0] <= ~trn_rbar_hit_d1_n[6:0];
//these following fields dependent on packet type
//i.e. memory packet fields are only valid for mem packet types
//and completer packet fields are only valid for completer packet type;
//memory packet fields
MEM_req_id[15:0] <= trn_rd_d1[31:16];
MEM_tag[7:0] <= trn_rd_d1[15:8];
//first and last byte enables not needed because plus core delivers
//completer packet fields
CMP_comp_id[15:0] <= trn_rd_d1[31:16];
CMP_compl_stat[2:0] <= trn_rd_d1[15:13];
CMP_bcm <= trn_rd_d1[12];
CMP_byte_count[11:0] <= trn_rd_d1[11:0];
//add message fields here if needed
//decode the packet type and register in rx_packet_type
casex({trn_rd_d1[62],trn_rd_d1[60:56]})
6'b000000: begin //mem read
rx_packet_type[4:0] <= 5'b10000;
end
6'b100000: begin //mem write
rx_packet_type[4:0] <= 5'b01000;
end
6'b101010: begin //completer with data
rx_packet_type[4:0] <= 5'b00100;
end
6'bx10xxx: begin //message
rx_packet_type[4:0] <= 5'b00010;
end
default: begin //all other packet types are unsupported for this design
rx_packet_type[4:0] <= 5'b00001;
end
endcase
end
end
end
// Now do the same for the second header of the current packet
always@(posedge clk )begin
if(rst_reg)begin
MEM_addr[63:0] <= 0;
CMP_req_id[15:0] <= 0;
CMP_tag[7:0] <= 0;
CMP_lower_addr[6:0] <= 0;
end else begin
if(trn_state == SOF & ~trn_rsrc_rdy_d1_n)begin //packet is in process of
//reading out second header
if(fourdw_n_threedw)
MEM_addr[63:0] <= trn_rd_d1[63:0];
else
MEM_addr[63:0] <= {32'h00000000,trn_rd_d1[63:32]};
CMP_req_id[15:0] <= trn_rd_d1[63:48];
CMP_tag[7:0] <= trn_rd_d1[47:40];
CMP_lower_addr[6:0] <= trn_rd_d1[48:32];
end
end
end
// generate a valid signal for the headers field
always@(posedge clk)begin
if(rst_reg)
header_fields_valid <= 0;
else
header_fields_valid <= ~trn_rsrc_rdy_d2_n & trn_rsof_d1_n;
end
//This state machine keeps track of what state the RX TRN interface
//is currently in
always @ (posedge clk )
begin
if(rst_reg)
begin
trn_state <= IDLE;
trn_rdst_rdy_n <= 1'b0;
end
else
begin
case(trn_state)
IDLE: begin
trn_rdst_rdy_n <= 1'b0;
if(rx_sof_d1)
trn_state <= SOF;
else
trn_state <= IDLE;
end
/// Jiansong: notice, completion streaming here
NOT_READY: begin // This state is a placeholder only - it is currently not
// entered from any other state
// This state could be used for throttling the PCIe
// Endpoint Block Plus RX TRN interface, however, this
// should not be done when using completion streaming
// mode as this reference design does
trn_rdst_rdy_n <= 1'b1;
trn_state <= IDLE;
end
SOF: begin
if(~trn_reof_d1_n & ~trn_rsrc_rdy_d1_n)
trn_state <= EOF;
else if(trn_reof_d1_n & ~trn_rsrc_rdy_d1_n)
trn_state <= HEAD2;
else
trn_state <= SOF;
end
HEAD2: begin
if(~trn_reof_d1_n & ~trn_rsrc_rdy_d1_n)
trn_state <= EOF;
else if(trn_reof_d1_n & ~trn_rsrc_rdy_d1_n)
trn_state <= BODY;
else
trn_state <= HEAD2;
end
BODY: begin
if(~trn_reof_d1_n & ~trn_rsrc_rdy_d1_n)
trn_state <= EOF;
else
trn_state <= BODY;
end
EOF: begin
if(~trn_rsof_d1_n & ~trn_rsrc_rdy_d1_n)
trn_state <= SOF;
else if(trn_rsof_d1_n & trn_rsrc_rdy_d1_n)
trn_state <= IDLE;
else if(~trn_reof_d1_n & ~trn_rsrc_rdy_d1_n)
trn_state <= EOF;
else
trn_state <= IDLE;
end
default: begin
trn_state <= IDLE;
end
endcase
end
end
//data shifter logic
//need to shift the data depending if we receive a four DWORD or three DWORD
//TLP type - Note that completion packets will always be 3DW TLPs
assign data_out_mux[63:0] = (fourdw_n_threedw)
? trn_rd_d2[63:0]
: {trn_rd_d2[31:0],trn_rd_d1[63:32]};
/// Jiansong: notice, why? 64bit data? likely should be modified
//swap the byte ordering to little endian
//e.g. data_out = B7,B6,B5,B4,B3,B2,B1,B0
always@(posedge clk)
data_out[63:0] <= {data_out_mux[7:0],data_out_mux[15:8],
data_out_mux[23:16],data_out_mux[31:24],
data_out_mux[39:32],data_out_mux[47:40],
data_out_mux[55:48],data_out_mux[63:56]};
//Data byte enable logic:
//Need to add byte enable logic for incoming memory transactions if desired
//to allow memory transaction granularity smaller than DWORD.
//
//This design always requests data on 128 byte boundaries so for
//completion TLPs the byte enables would always be asserted
//
//Note that the endpoint block plus uses negative logic, however,
//I decided to use positive logic for the user application.
assign data_out_be = 8'hff;
//data_valid generation logic
//Generally, data_valid should be asserted the same amount of cycles
//that trn_rsrc_rdy_n is asserted (minus the cycles that sof and
//eof are asserted).
//There are two exceptions to this:
// - 3DW TLPs with odd number of DW without Digest
// In this case an extra cycle is required
// - eof is used to generate this extra cycle
// - 4DW TLPs with even number of DW with Digest
// In this case an extra cycle needs to be removed
// - the last cycle is removed
// Jiansong: fix Mrd data to fifo bug
always@(*)begin
case({fourdw_n_threedw, dw_length[0], td})
3'b010: data_valid_early = ~trn_rsrc_rdy_d2_n
& trn_rsof_d2_n
& ~trn_reof_d2_n
& payload;
3'b101: data_valid_early = ~trn_rsrc_rdy_d2_n
& trn_reof_d1_n
& payload;
default: data_valid_early = ~trn_rsrc_rdy_d2_n
& trn_rsof_d2_n
& trn_reof_d2_n
& payload;
endcase
end
//delay by one clock to match data_out (and presumably data_out_be)
always@(posedge clk)
if(rst_reg)
data_valid <= 1'b0;
else
data_valid <= data_valid_early;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003-2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg check;
initial check = 1'b0;
Genit g (.clk(clk), .check(check));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d %x %x\n",$time, cyc, check, out);
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
check <= 1'b0;
end
else if (cyc==1) begin
check <= 1'b1;
end
else if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
//`define WAVES
`ifdef WAVES
initial begin
$dumpfile("obj_dir/t_gen_intdot2/t_gen_intdot.vcd");
$dumpvars(12, t);
end
`endif
endmodule
module One;
wire one = 1'b1;
endmodule
module Genit (
input clk,
input check);
// ARRAY
One cellarray1[1:0] (); //cellarray[0..1][0..1]
always @ (posedge clk) if (cellarray1[0].one !== 1'b1) $stop;
always @ (posedge clk) if (cellarray1[1].one !== 1'b1) $stop;
// IF
generate
// genblk1 refers to the if's name, not the "generate" itself.
if (1'b1) // IMPLIED begin: genblk1
One ifcell1(); // genblk1.ifcell1
else
One ifcell1(); // genblk1.ifcell1
endgenerate
// On compliant simulators "Implicit name" not allowed here; IE we can't use "genblk1" etc
`ifdef verilator
always @ (posedge clk) if (genblk1.ifcell1.one !== 1'b1) $stop;
//`else // NOT SUPPORTED accoring to spec - generic block references
`endif
generate
begin : namedif2
if (1'b1)
One ifcell2(); // namedif2.genblk1.ifcell2
end
endgenerate
`ifdef verilator
always @ (posedge clk) if (namedif2.genblk1.ifcell2.one !== 1'b1) $stop;
//`else // NOT SUPPORTED accoring to spec - generic block references
`endif
generate
if (1'b1)
begin : namedif3
One ifcell3(); // namedif3.ifcell3
end
endgenerate
always @ (posedge clk) if (namedif3.ifcell3.one !== 1'b1) $stop;
// CASE
generate
case (1'b1)
1'b1 :
One casecell10(); // genblk3.casecell10
endcase
endgenerate
`ifdef verilator
always @ (posedge clk) if (genblk3.casecell10.one !== 1'b1) $stop;
//`else // NOT SUPPORTED accoring to spec - generic block references
`endif
generate
case (1'b1)
1'b1 : begin : namedcase11
One casecell11();
end
endcase
endgenerate
always @ (posedge clk) if (namedcase11.casecell11.one !== 1'b1) $stop;
genvar i;
genvar j;
// IF
generate
for (i = 0; i < 2; i = i + 1)
One cellfor20 (); // genblk4[0..1].cellfor20
endgenerate
`ifdef verilator
always @ (posedge clk) if (genblk4[0].cellfor20.one !== 1'b1) $stop;
always @ (posedge clk) if (genblk4[1].cellfor20.one !== 1'b1) $stop;
//`else // NOT SUPPORTED accoring to spec - generic block references
`endif
// COMBO
generate
for (i = 0; i < 2; i = i + 1)
begin : namedfor21
One cellfor21 (); // namedfor21[0..1].cellfor21
end
endgenerate
always @ (posedge clk) if (namedfor21[0].cellfor21.one !== 1'b1) $stop;
always @ (posedge clk) if (namedfor21[1].cellfor21.one !== 1'b1) $stop;
generate
for (i = 0; i < 2; i = i + 1)
begin : namedfor30
for (j = 0; j < 2; j = j + 1)
begin : forb30
if (j == 0)
begin : forif30
One cellfor30a (); // namedfor30[0..1].forb30[0].forif30.cellfor30a
end
else
`ifdef verilator
begin : forif30b
`else
begin : forif30 // forif30 seems to work on some simulators, not verilator yet
`endif
One cellfor30b (); // namedfor30[0..1].forb30[1].forif30.cellfor30b
end
end
end
endgenerate
always @ (posedge clk) if (namedfor30[0].forb30[0].forif30.cellfor30a.one !== 1'b1) $stop;
always @ (posedge clk) if (namedfor30[1].forb30[0].forif30.cellfor30a.one !== 1'b1) $stop;
`ifdef verilator
always @ (posedge clk) if (namedfor30[0].forb30[1].forif30b.cellfor30b.one !== 1'b1) $stop;
always @ (posedge clk) if (namedfor30[1].forb30[1].forif30b.cellfor30b.one !== 1'b1) $stop;
`else
always @ (posedge clk) if (namedfor30[0].forb30[1].forif30.cellfor30b.one !== 1'b1) $stop;
always @ (posedge clk) if (namedfor30[1].forb30[1].forif30.cellfor30b.one !== 1'b1) $stop;
`endif
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PCIeGen2x8If128_core_top.v
// Version : 3.2
//
// Description: 7-series solution wrapper : Endpoint for PCI Express
//
//
//
//--------------------------------------------------------------------------------
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "PCIeGen2x8If128,pcie_7x_v3_2_1,{LINK_CAP_MAX_LINK_SPEED=2,LINK_CAP_MAX_LINK_WIDTH=8,PCIE_CAP_DEVICE_PORT_TYPE=0000,DEV_CAP_MAX_PAYLOAD_SUPPORTED=1,USER_CLK_FREQ=4,REF_CLK_FREQ=0,MSI_CAP_ON=TRUE,MSI_CAP_MULTIMSGCAP=0,MSI_CAP_MULTIMSG_EXTENSION=0,MSIX_CAP_ON=FALSE,TL_TX_RAM_RADDR_LATENCY=0,TL_TX_RAM_RDATA_LATENCY=2,TL_RX_RAM_RADDR_LATENCY=0,TL_RX_RAM_RDATA_LATENCY=2,TL_RX_RAM_WRITE_LATENCY=0,VC0_TX_LASTPACKET=28,VC0_RX_RAM_LIMIT=3FF,VC0_TOTAL_CREDITS_PH=4,VC0_TOTAL_CREDITS_PD=32,VC0_TOTAL_CREDITS_NPH=4,VC0_TOTAL_CREDITS_NPD=8,VC0_TOTAL_CREDITS_CH=72,VC0_TOTAL_CREDITS_CD=370,VC0_CPL_INFINITE=TRUE,DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT=0,DEV_CAP_EXT_TAG_SUPPORTED=TRUE,LINK_STATUS_SLOT_CLOCK_CONFIG=TRUE,DISABLE_LANE_REVERSAL=TRUE,DISABLE_SCRAMBLING=FALSE,DSN_CAP_ON=TRUE,REVISION_ID=00,VC_CAP_ON=FALSE}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module PCIeGen2x8If128_core_top # (
parameter CFG_VEND_ID = 16'h10EE,
parameter CFG_DEV_ID = 16'h7028,
parameter CFG_REV_ID = 8'h00,
parameter CFG_SUBSYS_VEND_ID = 16'h10EE,
parameter CFG_SUBSYS_ID = 16'h0007,
parameter EXT_PIPE_SIM = "FALSE",
parameter ALLOW_X8_GEN2 = "TRUE",
parameter PIPE_PIPELINE_STAGES = 1,
parameter [11:0] AER_BASE_PTR = 12'h000,
parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE",
parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE",
parameter AER_CAP_MULTIHEADER = "FALSE",
parameter [11:0] AER_CAP_NEXTPTR = 12'h000,
parameter [23:0] AER_CAP_OPTIONAL_ERR_SUPPORT = 24'h000000,
parameter AER_CAP_ON = "FALSE",
parameter AER_CAP_PERMIT_ROOTERR_UPDATE = "FALSE",
parameter [31:0] BAR0 = 32'hFFFFFC00,
parameter [31:0] BAR1 = 32'h00000000,
parameter [31:0] BAR2 = 32'h00000000,
parameter [31:0] BAR3 = 32'h00000000,
parameter [31:0] BAR4 = 32'h00000000,
parameter [31:0] BAR5 = 32'h00000000,
parameter C_DATA_WIDTH = 128,
parameter [31:0] CARDBUS_CIS_POINTER = 32'h00000000,
parameter [23:0] CLASS_CODE = 24'h058000,
parameter CMD_INTX_IMPLEMENTED = "FALSE",
parameter CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE",
parameter [3:0] CPL_TIMEOUT_RANGES_SUPPORTED = 4'h2,
parameter integer DEV_CAP_ENDPOINT_L0S_LATENCY = 0,
parameter integer DEV_CAP_ENDPOINT_L1_LATENCY = 7,
parameter DEV_CAP_EXT_TAG_SUPPORTED = "TRUE",
parameter integer DEV_CAP_MAX_PAYLOAD_SUPPORTED = 1,
parameter integer DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0,
parameter DEV_CAP2_ARI_FORWARDING_SUPPORTED = "FALSE",
parameter DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED = "FALSE",
parameter DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED = "FALSE",
parameter DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED = "FALSE",
parameter DEV_CAP2_CAS128_COMPLETER_SUPPORTED = "FALSE",
parameter [1:0] DEV_CAP2_TPH_COMPLETER_SUPPORTED = 2'b00,
parameter DEV_CONTROL_EXT_TAG_DEFAULT = "FALSE",
parameter DISABLE_LANE_REVERSAL = "TRUE",
parameter DISABLE_RX_POISONED_RESP = "FALSE",
parameter DISABLE_SCRAMBLING = "FALSE",
parameter [11:0] DSN_BASE_PTR = 12'h100,
parameter [11:0] DSN_CAP_NEXTPTR = 12'h000,
parameter DSN_CAP_ON = "TRUE",
parameter [10:0] ENABLE_MSG_ROUTE = 11'b00000000000,
parameter ENABLE_RX_TD_ECRC_TRIM = "FALSE",
parameter [31:0] EXPANSION_ROM = 32'h00000000,
parameter [5:0] EXT_CFG_CAP_PTR = 6'h3F,
parameter [9:0] EXT_CFG_XP_CAP_PTR = 10'h3FF,
parameter [7:0] HEADER_TYPE = 8'h00,
parameter [7:0] INTERRUPT_PIN = 8'h0,
parameter [9:0] LAST_CONFIG_DWORD = 10'h3FF,
parameter LINK_CAP_ASPM_OPTIONALITY = "FALSE",
parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE",
parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE",
parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h2,
parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h8,
parameter LINK_CTRL2_DEEMPHASIS = "FALSE",
parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE",
parameter [3:0] LINK_CTRL2_TARGET_LINK_SPEED = 4'h2,
parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE",
parameter [14:0] LL_ACK_TIMEOUT = 15'h0000,
parameter LL_ACK_TIMEOUT_EN = "FALSE",
parameter integer LL_ACK_TIMEOUT_FUNC = 0,
parameter [14:0] LL_REPLAY_TIMEOUT = 15'h0000,
parameter LL_REPLAY_TIMEOUT_EN = "FALSE",
parameter integer LL_REPLAY_TIMEOUT_FUNC = 1,
parameter [5:0] LTSSM_MAX_LINK_WIDTH = 6'h8,
parameter MSI_CAP_MULTIMSGCAP = 0,
parameter MSI_CAP_MULTIMSG_EXTENSION = 0,
parameter MSI_CAP_ON = "TRUE",
parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "FALSE",
parameter MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE",
parameter MSIX_CAP_ON = "FALSE",
parameter MSIX_CAP_PBA_BIR = 0,
parameter [28:0] MSIX_CAP_PBA_OFFSET = 29'h0,
parameter MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] MSIX_CAP_TABLE_OFFSET = 29'h0,
parameter [10:0] MSIX_CAP_TABLE_SIZE = 11'h000,
parameter [3:0] PCIE_CAP_DEVICE_PORT_TYPE = 4'h0,
parameter [7:0] PCIE_CAP_NEXTPTR = 8'h00,
parameter PM_CAP_DSI = "FALSE",
parameter PM_CAP_D1SUPPORT = "FALSE",
parameter PM_CAP_D2SUPPORT = "FALSE",
parameter [7:0] PM_CAP_NEXTPTR = 8'h48,
parameter [4:0] PM_CAP_PMESUPPORT = 5'h0F,
parameter PM_CSR_NOSOFTRST = "TRUE",
parameter [1:0] PM_DATA_SCALE0 = 2'h0,
parameter [1:0] PM_DATA_SCALE1 = 2'h0,
parameter [1:0] PM_DATA_SCALE2 = 2'h0,
parameter [1:0] PM_DATA_SCALE3 = 2'h0,
parameter [1:0] PM_DATA_SCALE4 = 2'h0,
parameter [1:0] PM_DATA_SCALE5 = 2'h0,
parameter [1:0] PM_DATA_SCALE6 = 2'h0,
parameter [1:0] PM_DATA_SCALE7 = 2'h0,
parameter [7:0] PM_DATA0 = 8'h00,
parameter [7:0] PM_DATA1 = 8'h00,
parameter [7:0] PM_DATA2 = 8'h00,
parameter [7:0] PM_DATA3 = 8'h00,
parameter [7:0] PM_DATA4 = 8'h00,
parameter [7:0] PM_DATA5 = 8'h00,
parameter [7:0] PM_DATA6 = 8'h00,
parameter [7:0] PM_DATA7 = 8'h00,
parameter [11:0] RBAR_BASE_PTR = 12'h000,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR0 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR1 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR2 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR3 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR4 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR5 = 5'h00,
parameter [2:0] RBAR_CAP_INDEX0 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX1 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX2 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX3 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX4 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX5 = 3'h0,
parameter RBAR_CAP_ON = "FALSE",
parameter [31:0] RBAR_CAP_SUP0 = 32'h00001,
parameter [31:0] RBAR_CAP_SUP1 = 32'h00001,
parameter [31:0] RBAR_CAP_SUP2 = 32'h00001,
parameter [31:0] RBAR_CAP_SUP3 = 32'h00001,
parameter [31:0] RBAR_CAP_SUP4 = 32'h00001,
parameter [31:0] RBAR_CAP_SUP5 = 32'h00001,
parameter [2:0] RBAR_NUM = 3'h0,
parameter RECRC_CHK = 0,
parameter RECRC_CHK_TRIM = "FALSE",
parameter REF_CLK_FREQ = 0, // 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1,
parameter KEEP_WIDTH = C_DATA_WIDTH / 8,
parameter TL_RX_RAM_RADDR_LATENCY = 0,
parameter TL_RX_RAM_WRITE_LATENCY = 0,
parameter TL_TX_RAM_RADDR_LATENCY = 0,
parameter TL_TX_RAM_WRITE_LATENCY = 0,
parameter TL_RX_RAM_RDATA_LATENCY = 2,
parameter TL_TX_RAM_RDATA_LATENCY = 2,
parameter TRN_NP_FC = "TRUE",
parameter TRN_DW = "TRUE",
parameter UPCONFIG_CAPABLE = "TRUE",
parameter UPSTREAM_FACING = "TRUE",
parameter UR_ATOMIC = "FALSE",
parameter UR_INV_REQ = "TRUE",
parameter UR_PRS_RESPONSE = "TRUE",
parameter USER_CLK_FREQ = 4,
parameter USER_CLK2_DIV2 = "TRUE",
parameter [11:0] VC_BASE_PTR = 12'h000,
parameter [11:0] VC_CAP_NEXTPTR = 12'h000,
parameter VC_CAP_ON = "FALSE",
parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE",
parameter VC0_CPL_INFINITE = "TRUE",
parameter [12:0] VC0_RX_RAM_LIMIT = 13'h3FF,
parameter VC0_TOTAL_CREDITS_CD = 370,
parameter VC0_TOTAL_CREDITS_CH = 72,
parameter VC0_TOTAL_CREDITS_NPH = 4,
parameter VC0_TOTAL_CREDITS_NPD = 8,
parameter VC0_TOTAL_CREDITS_PD = 32,
parameter VC0_TOTAL_CREDITS_PH = 4,
parameter VC0_TX_LASTPACKET = 28,
parameter [11:0] VSEC_BASE_PTR = 12'h000,
parameter [11:0] VSEC_CAP_NEXTPTR = 12'h000,
parameter VSEC_CAP_ON = "FALSE",
parameter DISABLE_ASPM_L1_TIMER = "FALSE",
parameter DISABLE_BAR_FILTERING = "FALSE",
parameter DISABLE_ID_CHECK = "FALSE",
parameter DISABLE_RX_TC_FILTER = "FALSE",
parameter [7:0] DNSTREAM_LINK_NUM = 8'h00,
parameter [15:0] DSN_CAP_ID = 16'h0003,
parameter [3:0] DSN_CAP_VERSION = 4'h1,
parameter ENTER_RVRY_EI_L0 = "TRUE",
parameter [4:0] INFER_EI = 5'h00,
parameter IS_SWITCH = "FALSE",
parameter LINK_CAP_ASPM_SUPPORT = 1,
parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE",
parameter LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7,
parameter LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7,
parameter LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7,
parameter LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7,
parameter LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7,
parameter LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7,
parameter LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7,
parameter LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7,
parameter LINK_CAP_RSVD_23 = 0,
parameter LINK_CONTROL_RCB = 0,
parameter [7:0] MSI_BASE_PTR = 8'h48,
parameter [7:0] MSI_CAP_ID = 8'h05,
parameter [7:0] MSI_CAP_NEXTPTR = 8'h60,
parameter [7:0] MSIX_BASE_PTR = 8'h9C,
parameter [7:0] MSIX_CAP_ID = 8'h11,
parameter [7:0] MSIX_CAP_NEXTPTR =8'h00,
parameter N_FTS_COMCLK_GEN1 = 255,
parameter N_FTS_COMCLK_GEN2 = 255,
parameter N_FTS_GEN1 = 255,
parameter N_FTS_GEN2 = 255,
parameter [7:0] PCIE_BASE_PTR = 8'h60,
parameter [7:0] PCIE_CAP_CAPABILITY_ID = 8'h10,
parameter [3:0] PCIE_CAP_CAPABILITY_VERSION = 4'h2,
parameter PCIE_CAP_ON = "TRUE",
parameter PCIE_CAP_RSVD_15_14 = 0,
parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE",
parameter PCIE_REVISION = 2,
parameter PL_AUTO_CONFIG = 0,
parameter PL_FAST_TRAIN = "FALSE",
parameter PCIE_EXT_CLK = "FALSE",
parameter PCIE_EXT_GT_COMMON = "FALSE",
parameter EXT_CH_GT_DRP = "FALSE",
parameter TRANSCEIVER_CTRL_STATUS_PORTS = "FALSE",
parameter SHARED_LOGIC_IN_CORE = "FALSE",
parameter [7:0] PM_BASE_PTR = 8'h40,
parameter PM_CAP_AUXCURRENT = 0,
parameter [7:0] PM_CAP_ID = 8'h01,
parameter PM_CAP_ON = "TRUE",
parameter PM_CAP_PME_CLOCK = "FALSE",
parameter PM_CAP_RSVD_04 = 0,
parameter PM_CAP_VERSION = 3,
parameter PM_CSR_BPCCEN = "FALSE",
parameter PM_CSR_B2B3 = "FALSE",
parameter ROOT_CAP_CRS_SW_VISIBILITY = "FALSE",
parameter SELECT_DLL_IF = "FALSE",
parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE",
parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE",
parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE",
parameter SLOT_CAP_HOTPLUG_CAPABLE = "FALSE",
parameter SLOT_CAP_HOTPLUG_SURPRISE = "FALSE",
parameter SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE",
parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE",
parameter [12:0] SLOT_CAP_PHYSICAL_SLOT_NUM = 13'h0000,
parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE",
parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE",
parameter SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0,
parameter [7:0] SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'h00,
parameter integer SPARE_BIT0 = 0,
parameter integer SPARE_BIT1 = 0,
parameter integer SPARE_BIT2 = 0,
parameter integer SPARE_BIT3 = 0,
parameter integer SPARE_BIT4 = 0,
parameter integer SPARE_BIT5 = 0,
parameter integer SPARE_BIT6 = 0,
parameter integer SPARE_BIT7 = 0,
parameter integer SPARE_BIT8 = 0,
parameter [7:0] SPARE_BYTE0 = 8'h00,
parameter [7:0] SPARE_BYTE1 = 8'h00,
parameter [7:0] SPARE_BYTE2 = 8'h00,
parameter [7:0] SPARE_BYTE3 = 8'h00,
parameter [31:0] SPARE_WORD0 = 32'h00000000,
parameter [31:0] SPARE_WORD1 = 32'h00000000,
parameter [31:0] SPARE_WORD2 = 32'h00000000,
parameter [31:0] SPARE_WORD3 = 32'h00000000,
parameter TL_RBYPASS = "FALSE",
parameter TL_TFC_DISABLE = "FALSE",
parameter TL_TX_CHECKS_DISABLE = "FALSE",
parameter EXIT_LOOPBACK_ON_EI = "TRUE",
parameter CFG_ECRC_ERR_CPLSTAT = 0,
parameter [7:0] CAPABILITIES_PTR = 8'h40,
parameter [6:0] CRM_MODULE_RSTS = 7'h00,
parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "TRUE",
parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "TRUE",
parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE",
parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE",
parameter DEV_CAP_RSVD_14_12 = 0,
parameter DEV_CAP_RSVD_17_16 = 0,
parameter DEV_CAP_RSVD_31_29 = 0,
parameter DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE",
parameter [15:0] VC_CAP_ID = 16'h0002,
parameter [3:0] VC_CAP_VERSION = 4'h1,
parameter [15:0] VSEC_CAP_HDR_ID = 16'h1234,
parameter [11:0] VSEC_CAP_HDR_LENGTH = 12'h018,
parameter [3:0] VSEC_CAP_HDR_REVISION = 4'h1,
parameter [15:0] VSEC_CAP_ID = 16'h000B,
parameter VSEC_CAP_IS_LINK_VISIBLE = "TRUE",
parameter [3:0] VSEC_CAP_VERSION = 4'h1,
parameter DISABLE_ERR_MSG = "FALSE",
parameter DISABLE_LOCKED_FILTER = "FALSE",
parameter DISABLE_PPM_FILTER = "FALSE",
parameter ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED = "FALSE",
parameter INTERRUPT_STAT_AUTO = "TRUE",
parameter MPS_FORCE = "FALSE",
parameter [14:0] PM_ASPML0S_TIMEOUT = 15'h0000,
parameter PM_ASPML0S_TIMEOUT_EN = "FALSE",
parameter PM_ASPML0S_TIMEOUT_FUNC = 0,
parameter PM_ASPM_FASTEXIT = "FALSE",
parameter PM_MF = "FALSE",
parameter [1:0] RP_AUTO_SPD = 2'h1,
parameter [4:0] RP_AUTO_SPD_LOOPCNT = 5'h1f,
parameter SIM_VERSION = "1.0",
parameter SSL_MESSAGE_AUTO = "FALSE",
parameter TECRC_EP_INV = "FALSE",
parameter UR_CFG1 = "TRUE",
parameter USE_RID_PINS = "FALSE",
// New Parameters
parameter DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED = "FALSE",
parameter DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED = "FALSE",
parameter DEV_CAP2_LTR_MECHANISM_SUPPORTED = "FALSE",
parameter [1:0] DEV_CAP2_MAX_ENDEND_TLP_PREFIXES = 2'h0,
parameter DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING = "FALSE",
parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE",
parameter [15:0] AER_CAP_ID = 16'h0001,
parameter [3:0] AER_CAP_VERSION = 4'h1,
parameter [15:0] RBAR_CAP_ID = 16'h0015,
parameter [11:0] RBAR_CAP_NEXTPTR = 12'h000,
parameter [3:0] RBAR_CAP_VERSION = 4'h1,
parameter PCIE_USE_MODE = "3.0",
parameter PCIE_GT_DEVICE = "GTX",
parameter PCIE_CHAN_BOND = 0,
parameter PCIE_PLL_SEL = "CPLL",
parameter PCIE_ASYNC_EN = "FALSE",
parameter PCIE_TXBUF_EN = "FALSE",
parameter PL_INTERFACE = "FALSE",
parameter CFG_MGMT_IF = "FALSE",
parameter CFG_CTL_IF = "TRUE",
parameter CFG_STATUS_IF = "TRUE",
parameter RCV_MSG_IF = "FALSE",
parameter CFG_FC_IF = "TRUE",
parameter EXT_PIPE_INTERFACE = "FALSE",
parameter TX_MARGIN_FULL_0 = 7'b1001111,
parameter TX_MARGIN_FULL_1 = 7'b1001110,
parameter TX_MARGIN_FULL_2 = 7'b1001101,
parameter TX_MARGIN_FULL_3 = 7'b1001100,
parameter TX_MARGIN_FULL_4 = 7'b1000011,
parameter TX_MARGIN_LOW_0 = 7'b1000101,
parameter TX_MARGIN_LOW_1 = 7'b1000110,
parameter TX_MARGIN_LOW_2 = 7'b1000011,
parameter TX_MARGIN_LOW_3 = 7'b1000010,
parameter TX_MARGIN_LOW_4 = 7'b1000000
)
(
//----------------------------------------------------------------------------------------------------------------//
// 1. PCI Express (pci_exp) Interface //
//----------------------------------------------------------------------------------------------------------------//
// Tx
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_txn,
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_txp,
// Rx
input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_rxn,
input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_rxp,
//----------------------------------------------------------------------------------------------------------------//
// 2. Clock & GT COMMON Sharing Interface //
//----------------------------------------------------------------------------------------------------------------//
// Shared Logic Internal
output int_pclk_out_slave,
output int_pipe_rxusrclk_out,
output [(LINK_CAP_MAX_LINK_WIDTH-1):0] int_rxoutclk_out,
output int_dclk_out,
output int_userclk1_out,
output int_userclk2_out,
output int_oobclk_out,
output int_mmcm_lock_out,
output [1:0] int_qplllock_out,
output [1:0] int_qplloutclk_out,
output [1:0] int_qplloutrefclk_out,
input [(LINK_CAP_MAX_LINK_WIDTH-1):0] int_pclk_sel_slave,
// Shared Logic External - Clocks
input pipe_pclk_in,
input pipe_rxusrclk_in,
input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pipe_rxoutclk_in,
input pipe_dclk_in,
input pipe_userclk1_in,
input pipe_userclk2_in,
input pipe_oobclk_in,
input pipe_mmcm_lock_in,
output pipe_txoutclk_out,
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pipe_rxoutclk_out,
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pipe_pclk_sel_out,
output pipe_gen3_out,
// Shared Logic External - GT COMMON
input [11:0] qpll_drp_crscode,
input [17:0] qpll_drp_fsm,
input [1:0] qpll_drp_done,
input [1:0] qpll_drp_reset,
input [1:0] qpll_qplllock,
input [1:0] qpll_qplloutclk,
input [1:0] qpll_qplloutrefclk,
output qpll_qplld,
output [1:0] qpll_qpllreset,
output qpll_drp_clk,
output qpll_drp_rst_n,
output qpll_drp_ovrd,
output qpll_drp_gen3,
output qpll_drp_start,
//----------------------------------------------------------------------------------------------------------------//
// 3. AXI-S Interface //
//----------------------------------------------------------------------------------------------------------------//
// Common
output user_clk_out,
output reg user_reset_out,
output user_lnk_up,
output wire user_app_rdy,
// AXI TX
//-----------
output [5:0] tx_buf_av,
output tx_err_drop,
output tx_cfg_req,
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata,
input s_axis_tx_tvalid,
output s_axis_tx_tready,
input [KEEP_WIDTH-1:0] s_axis_tx_tkeep,
input s_axis_tx_tlast,
input [3:0] s_axis_tx_tuser,
input tx_cfg_gnt,
// AXI RX
//-----------
output [C_DATA_WIDTH-1:0] m_axis_rx_tdata,
output m_axis_rx_tvalid,
input m_axis_rx_tready,
output [KEEP_WIDTH-1:0] m_axis_rx_tkeep,
output m_axis_rx_tlast,
output [21:0] m_axis_rx_tuser,
input rx_np_ok,
input rx_np_req,
// Flow Control
output [11:0] fc_cpld,
output [7:0] fc_cplh,
output [11:0] fc_npd,
output [7:0] fc_nph,
output [11:0] fc_pd,
output [7:0] fc_ph,
input [2:0] fc_sel,
//----------------------------------------------------------------------------------------------------------------//
// 4. Configuration (CFG) Interface //
//----------------------------------------------------------------------------------------------------------------//
//------------------------------------------------//
// EP and RP //
//------------------------------------------------//
output wire [31:0] cfg_mgmt_do,
output wire cfg_mgmt_rd_wr_done,
output wire [15:0] cfg_status,
output wire [15:0] cfg_command,
output wire [15:0] cfg_dstatus,
output wire [15:0] cfg_dcommand,
output wire [15:0] cfg_lstatus,
output wire [15:0] cfg_lcommand,
output wire [15:0] cfg_dcommand2,
output [2:0] cfg_pcie_link_state,
output wire cfg_pmcsr_pme_en,
output wire [1:0] cfg_pmcsr_powerstate,
output wire cfg_pmcsr_pme_status,
output wire cfg_received_func_lvl_rst,
// Management Interface
input wire [31:0] cfg_mgmt_di,
input wire [3:0] cfg_mgmt_byte_en,
input wire [9:0] cfg_mgmt_dwaddr,
input wire cfg_mgmt_wr_en,
input wire cfg_mgmt_rd_en,
input wire cfg_mgmt_wr_readonly,
// Error Reporting Interface
input wire cfg_err_ecrc,
input wire cfg_err_ur,
input wire cfg_err_cpl_timeout,
input wire cfg_err_cpl_unexpect,
input wire cfg_err_cpl_abort,
input wire cfg_err_posted,
input wire cfg_err_cor,
input wire cfg_err_atomic_egress_blocked,
input wire cfg_err_internal_cor,
input wire cfg_err_malformed,
input wire cfg_err_mc_blocked,
input wire cfg_err_poisoned,
input wire cfg_err_norecovery,
input wire [47:0] cfg_err_tlp_cpl_header,
output wire cfg_err_cpl_rdy,
input wire cfg_err_locked,
input wire cfg_err_acs,
input wire cfg_err_internal_uncor,
input wire cfg_trn_pending,
input wire cfg_pm_halt_aspm_l0s,
input wire cfg_pm_halt_aspm_l1,
input wire cfg_pm_force_state_en,
input wire [1:0] cfg_pm_force_state,
input wire [63:0] cfg_dsn,
output cfg_msg_received,
output [15:0] cfg_msg_data,
//------------------------------------------------//
// EP Only //
//------------------------------------------------//
// Interrupt Interface Signals
input wire cfg_interrupt,
output wire cfg_interrupt_rdy,
input wire cfg_interrupt_assert,
input wire [7:0] cfg_interrupt_di,
output wire [7:0] cfg_interrupt_do,
output wire [2:0] cfg_interrupt_mmenable,
output wire cfg_interrupt_msienable,
output wire cfg_interrupt_msixenable,
output wire cfg_interrupt_msixfm,
input wire cfg_interrupt_stat,
input wire [4:0] cfg_pciecap_interrupt_msgnum,
output cfg_to_turnoff,
input wire cfg_turnoff_ok,
output wire [7:0] cfg_bus_number,
output wire [4:0] cfg_device_number,
output wire [2:0] cfg_function_number,
input wire cfg_pm_wake,
output wire cfg_msg_received_pm_as_nak,
output wire cfg_msg_received_setslotpowerlimit,
//------------------------------------------------//
// RP Only //
//------------------------------------------------//
input wire cfg_pm_send_pme_to,
input wire [7:0] cfg_ds_bus_number,
input wire [4:0] cfg_ds_device_number,
input wire [2:0] cfg_ds_function_number,
input wire cfg_mgmt_wr_rw1c_as_rw,
output wire cfg_bridge_serr_en,
output wire cfg_slot_control_electromech_il_ctl_pulse,
output wire cfg_root_control_syserr_corr_err_en,
output wire cfg_root_control_syserr_non_fatal_err_en,
output wire cfg_root_control_syserr_fatal_err_en,
output wire cfg_root_control_pme_int_en,
output wire cfg_aer_rooterr_corr_err_reporting_en,
output wire cfg_aer_rooterr_non_fatal_err_reporting_en,
output wire cfg_aer_rooterr_fatal_err_reporting_en,
output wire cfg_aer_rooterr_corr_err_received,
output wire cfg_aer_rooterr_non_fatal_err_received,
output wire cfg_aer_rooterr_fatal_err_received,
output wire cfg_msg_received_err_cor,
output wire cfg_msg_received_err_non_fatal,
output wire cfg_msg_received_err_fatal,
output wire cfg_msg_received_pm_pme,
output wire cfg_msg_received_pme_to_ack,
output wire cfg_msg_received_assert_int_a,
output wire cfg_msg_received_assert_int_b,
output wire cfg_msg_received_assert_int_c,
output wire cfg_msg_received_assert_int_d,
output wire cfg_msg_received_deassert_int_a,
output wire cfg_msg_received_deassert_int_b,
output wire cfg_msg_received_deassert_int_c,
output wire cfg_msg_received_deassert_int_d,
//----------------------------------------------------------------------------------------------------------------//
// 5. Physical Layer Control and Status (PL) Interface //
//----------------------------------------------------------------------------------------------------------------//
//------------------------------------------------//
// EP and RP //
//------------------------------------------------//
input wire [1:0] pl_directed_link_change,
input wire [1:0] pl_directed_link_width,
input wire pl_directed_link_speed,
input wire pl_directed_link_auton,
input wire pl_upstream_prefer_deemph,
output wire pl_sel_lnk_rate,
output wire [1:0] pl_sel_lnk_width,
output wire [5:0] pl_ltssm_state,
output wire [1:0] pl_lane_reversal_mode,
output wire pl_phy_lnk_up,
output wire [2:0] pl_tx_pm_state,
output wire [1:0] pl_rx_pm_state,
output wire pl_link_upcfg_cap,
output wire pl_link_gen2_cap,
output wire pl_link_partner_gen2_supported,
output wire [2:0] pl_initial_link_width,
output wire pl_directed_change_done,
//------------------------------------------------//
// EP Only //
//------------------------------------------------//
output wire pl_received_hot_rst,
//------------------------------------------------//
// RP Only //
//------------------------------------------------//
input wire pl_transmit_hot_rst,
input wire pl_downstream_deemph_source,
//----------------------------------------------------------------------------------------------------------------//
// 6. AER interface //
//----------------------------------------------------------------------------------------------------------------//
input wire [127:0] cfg_err_aer_headerlog,
input wire [4:0] cfg_aer_interrupt_msgnum,
output wire cfg_err_aer_headerlog_set,
output wire cfg_aer_ecrc_check_en,
output wire cfg_aer_ecrc_gen_en,
//----------------------------------------------------------------------------------------------------------------//
// 7. VC interface //
//----------------------------------------------------------------------------------------------------------------//
output wire [6:0] cfg_vc_tcvc_map,
//----------------------------------------------------------------------------------------------------------------//
// PCIe Fast Config: ICAP primitive Interface //
//----------------------------------------------------------------------------------------------------------------//
input wire icap_clk,
input wire icap_csib,
input wire icap_rdwrb,
input wire [31:0] icap_i,
output wire [31:0] icap_o,
input [ 2:0] pipe_txprbssel,
input [ 2:0] pipe_rxprbssel,
input pipe_txprbsforceerr,
input pipe_rxprbscntreset,
input [ 2:0] pipe_loopback,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_rxprbserr,
input [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_txinhibit,
output [4:0] pipe_rst_fsm,
output [11:0] pipe_qrst_fsm,
output [(LINK_CAP_MAX_LINK_WIDTH*5)-1:0] pipe_rate_fsm,
output [(LINK_CAP_MAX_LINK_WIDTH*6)-1:0] pipe_sync_fsm_tx,
output [(LINK_CAP_MAX_LINK_WIDTH*7)-1:0] pipe_sync_fsm_rx,
output [(LINK_CAP_MAX_LINK_WIDTH*7)-1:0] pipe_drp_fsm,
output pipe_rst_idle,
output pipe_qrst_idle,
output pipe_rate_idle,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_eyescandataerror,
output [(LINK_CAP_MAX_LINK_WIDTH*3)-1:0] pipe_rxstatus,
output [(LINK_CAP_MAX_LINK_WIDTH*15)-1:0] pipe_dmonitorout,
output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_cpll_lock,
output [(LINK_CAP_MAX_LINK_WIDTH-1)>>2:0] pipe_qpll_lock,
output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_rxpmaresetdone,
output [(LINK_CAP_MAX_LINK_WIDTH*3)-1:0] pipe_rxbufstatus,
output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_txphaligndone,
output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_txphinitdone,
output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_txdlysresetdone,
output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_rxphaligndone,
output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_rxdlysresetdone,
output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_rxsyncdone,
output [(LINK_CAP_MAX_LINK_WIDTH*8)-1:0] pipe_rxdisperr,
output [(LINK_CAP_MAX_LINK_WIDTH*8)-1:0] pipe_rxnotintable,
output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_rxcommadet,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] gt_ch_drp_rdy,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_0,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_1,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_2,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_3,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_4,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_5,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_6,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_7,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_8,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_9,
output [31:0] pipe_debug,
//--------------Channel DRP---------------------------------
output ext_ch_gt_drpclk,
input [(LINK_CAP_MAX_LINK_WIDTH*9)-1:0] ext_ch_gt_drpaddr,
input [LINK_CAP_MAX_LINK_WIDTH-1:0] ext_ch_gt_drpen,
input [(LINK_CAP_MAX_LINK_WIDTH*16)-1:0] ext_ch_gt_drpdi,
input [LINK_CAP_MAX_LINK_WIDTH-1:0] ext_ch_gt_drpwe,
output [(LINK_CAP_MAX_LINK_WIDTH*16)-1:0] ext_ch_gt_drpdo,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] ext_ch_gt_drprdy,
//----------------------------------------------------------------------------------------------------------------//
// PCIe Fast Config: STARTUP primitive Interface //
//----------------------------------------------------------------------------------------------------------------//
// This input should be used when the startup block is generated exteranl to the PCI Express Core
input startup_eos_in, // 1-bit input: This signal should be driven by the EOS output of the STARTUP primitive.
// These inputs and outputs may be use when the startup block is generated internal to the PCI Express Core.
output startup_cfgclk, // 1-bit output: Configuration main clock output
output startup_cfgmclk, // 1-bit output: Configuration internal oscillator clock output
output startup_eos, // 1-bit output: Active high output signal indicating the End Of Startup
output startup_preq, // 1-bit output: PROGRAM request to fabric output
input startup_clk, // 1-bit input: User start-up clock input
input startup_gsr, // 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
input startup_gts, // 1-bit input: Global 3-state input (GTS cannot be used for the port name)
input startup_keyclearb, // 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
input startup_pack, // 1-bit input: PROGRAM acknowledge input
input startup_usrcclko, // 1-bit input: User CCLK input
input startup_usrcclkts, // 1-bit input: User CCLK 3-state enable input
input startup_usrdoneo, // 1-bit input: User DONE pin output control
input startup_usrdonets, // 1-bit input: User DONE 3-state enable output
//----------------------------------------------------------------------------------------------------------------//
// 8. PCIe DRP (PCIe DRP) Interface //
//----------------------------------------------------------------------------------------------------------------//
input wire pcie_drp_clk,
input wire pcie_drp_en,
input wire pcie_drp_we,
input wire [8:0] pcie_drp_addr,
input wire [15:0] pcie_drp_di,
output wire pcie_drp_rdy,
output wire [15:0] pcie_drp_do,
//----------------------------------------------------------------------------------------------------------------//
// PIPE PORTS to TOP Level For PIPE SIMULATION with 3rd Party IP/BFM/Xilinx BFM
//----------------------------------------------------------------------------------------------------------------//
input wire [ 3:0] common_commands_in,
input wire [24:0] pipe_rx_0_sigs,
input wire [24:0] pipe_rx_1_sigs,
input wire [24:0] pipe_rx_2_sigs,
input wire [24:0] pipe_rx_3_sigs,
input wire [24:0] pipe_rx_4_sigs,
input wire [24:0] pipe_rx_5_sigs,
input wire [24:0] pipe_rx_6_sigs,
input wire [24:0] pipe_rx_7_sigs,
output wire [11:0] common_commands_out,
output wire [22:0] pipe_tx_0_sigs,
output wire [22:0] pipe_tx_1_sigs,
output wire [22:0] pipe_tx_2_sigs,
output wire [22:0] pipe_tx_3_sigs,
output wire [22:0] pipe_tx_4_sigs,
output wire [22:0] pipe_tx_5_sigs,
output wire [22:0] pipe_tx_6_sigs,
output wire [22:0] pipe_tx_7_sigs,
//----------------------------------------------------------------------------------------------------------------//
// 9. System(SYS) Interface //
//----------------------------------------------------------------------------------------------------------------//
input wire pipe_mmcm_rst_n, // Async | Async
input wire sys_clk,
input wire sys_rst_n
);
wire user_clk;
wire user_clk2;
wire pipe_clk;
wire [15:0] cfg_vend_id = CFG_VEND_ID;
wire [15:0] cfg_dev_id = CFG_DEV_ID;
wire [7:0] cfg_rev_id = CFG_REV_ID;
wire [15:0] cfg_subsys_vend_id = CFG_SUBSYS_VEND_ID;
wire [15:0] cfg_subsys_id = CFG_SUBSYS_ID;
// PIPE Interface Wires
wire phy_rdy_n;
wire pipe_rx0_polarity_gt;
wire pipe_rx1_polarity_gt;
wire pipe_rx2_polarity_gt;
wire pipe_rx3_polarity_gt;
wire pipe_rx4_polarity_gt;
wire pipe_rx5_polarity_gt;
wire pipe_rx6_polarity_gt;
wire pipe_rx7_polarity_gt;
wire pipe_tx_deemph_gt;
wire [2:0] pipe_tx_margin_gt;
wire pipe_tx_rate_gt;
wire pipe_tx_rcvr_det_gt;
wire [1:0] pipe_tx0_char_is_k_gt;
wire pipe_tx0_compliance_gt;
wire [15:0] pipe_tx0_data_gt;
wire pipe_tx0_elec_idle_gt;
wire [1:0] pipe_tx0_powerdown_gt;
wire [1:0] pipe_tx1_char_is_k_gt;
wire pipe_tx1_compliance_gt;
wire [15:0] pipe_tx1_data_gt;
wire pipe_tx1_elec_idle_gt;
wire [1:0] pipe_tx1_powerdown_gt;
wire [1:0] pipe_tx2_char_is_k_gt;
wire pipe_tx2_compliance_gt;
wire [15:0] pipe_tx2_data_gt;
wire pipe_tx2_elec_idle_gt;
wire [1:0] pipe_tx2_powerdown_gt;
wire [1:0] pipe_tx3_char_is_k_gt;
wire pipe_tx3_compliance_gt;
wire [15:0] pipe_tx3_data_gt;
wire pipe_tx3_elec_idle_gt;
wire [1:0] pipe_tx3_powerdown_gt;
wire [1:0] pipe_tx4_char_is_k_gt;
wire pipe_tx4_compliance_gt;
wire [15:0] pipe_tx4_data_gt;
wire pipe_tx4_elec_idle_gt;
wire [1:0] pipe_tx4_powerdown_gt;
wire [1:0] pipe_tx5_char_is_k_gt;
wire pipe_tx5_compliance_gt;
wire [15:0] pipe_tx5_data_gt;
wire pipe_tx5_elec_idle_gt;
wire [1:0] pipe_tx5_powerdown_gt;
wire [1:0] pipe_tx6_char_is_k_gt;
wire pipe_tx6_compliance_gt;
wire [15:0] pipe_tx6_data_gt;
wire pipe_tx6_elec_idle_gt;
wire [1:0] pipe_tx6_powerdown_gt;
wire [1:0] pipe_tx7_char_is_k_gt;
wire pipe_tx7_compliance_gt;
wire [15:0] pipe_tx7_data_gt;
wire pipe_tx7_elec_idle_gt;
wire [1:0] pipe_tx7_powerdown_gt;
wire pipe_rx0_chanisaligned_gt;
wire [1:0] pipe_rx0_char_is_k_gt;
wire [15:0] pipe_rx0_data_gt;
wire pipe_rx0_elec_idle_gt;
wire pipe_rx0_phy_status_gt;
wire [2:0] pipe_rx0_status_gt;
wire pipe_rx0_valid_gt;
wire pipe_rx1_chanisaligned_gt;
wire [1:0] pipe_rx1_char_is_k_gt;
wire [15:0] pipe_rx1_data_gt;
wire pipe_rx1_elec_idle_gt;
wire pipe_rx1_phy_status_gt;
wire [2:0] pipe_rx1_status_gt;
wire pipe_rx1_valid_gt;
wire pipe_rx2_chanisaligned_gt;
wire [1:0] pipe_rx2_char_is_k_gt;
wire [15:0] pipe_rx2_data_gt;
wire pipe_rx2_elec_idle_gt;
wire pipe_rx2_phy_status_gt;
wire [2:0] pipe_rx2_status_gt;
wire pipe_rx2_valid_gt;
wire pipe_rx3_chanisaligned_gt;
wire [1:0] pipe_rx3_char_is_k_gt;
wire [15:0] pipe_rx3_data_gt;
wire pipe_rx3_elec_idle_gt;
wire pipe_rx3_phy_status_gt;
wire [2:0] pipe_rx3_status_gt;
wire pipe_rx3_valid_gt;
wire pipe_rx4_chanisaligned_gt;
wire [1:0] pipe_rx4_char_is_k_gt;
wire [15:0] pipe_rx4_data_gt;
wire pipe_rx4_elec_idle_gt;
wire pipe_rx4_phy_status_gt;
wire [2:0] pipe_rx4_status_gt;
wire pipe_rx4_valid_gt;
wire pipe_rx5_chanisaligned_gt;
wire [1:0] pipe_rx5_char_is_k_gt;
wire [15:0] pipe_rx5_data_gt;
wire pipe_rx5_elec_idle_gt;
wire pipe_rx5_phy_status_gt;
wire [2:0] pipe_rx5_status_gt;
wire pipe_rx5_valid_gt;
wire pipe_rx6_chanisaligned_gt;
wire [1:0] pipe_rx6_char_is_k_gt;
wire [15:0] pipe_rx6_data_gt;
wire pipe_rx6_elec_idle_gt;
wire pipe_rx6_phy_status_gt;
wire [2:0] pipe_rx6_status_gt;
wire pipe_rx6_valid_gt;
wire pipe_rx7_chanisaligned_gt;
wire [1:0] pipe_rx7_char_is_k_gt;
wire [15:0] pipe_rx7_data_gt;
wire pipe_rx7_elec_idle_gt;
wire pipe_rx7_phy_status_gt;
wire [2:0] pipe_rx7_status_gt;
wire pipe_rx7_valid_gt;
(* ASYNC_REG = "TRUE" *) reg user_lnk_up_mux;
(* KEEP = "TRUE", ASYNC_REG = "TRUE" *) reg user_lnk_up_int;
reg user_reset_int;
reg bridge_reset_int;
reg bridge_reset_d;
wire user_rst_n;
reg pl_received_hot_rst_q;
wire pl_received_hot_rst_wire;
reg pl_phy_lnk_up_q;
wire pl_phy_lnk_up_wire;
wire sys_or_hot_rst;
wire trn_lnk_up;
wire [5:0] pl_ltssm_state_int;
wire user_app_rdy_req;
localparam TCQ = 100;
localparam ENABLE_FAST_SIM_TRAINING = "TRUE";
assign user_lnk_up = user_lnk_up_int;
assign user_app_rdy = 1'b1;
assign pl_ltssm_state = pl_ltssm_state_int;
assign pl_phy_lnk_up = pl_phy_lnk_up_q;
assign pl_received_hot_rst = pl_received_hot_rst_q;
// Register block outputs pl_received_hot_rst and phy_lnk_up to ease timing on block output
assign sys_or_hot_rst = !sys_rst_n || pl_received_hot_rst_q;
always @(posedge user_clk_out)
begin
if (!sys_rst_n) begin
pl_received_hot_rst_q <= #TCQ 1'b0;
pl_phy_lnk_up_q <= #TCQ 1'b0;
end else begin
pl_received_hot_rst_q <= #TCQ pl_received_hot_rst_wire;
pl_phy_lnk_up_q <= #TCQ pl_phy_lnk_up_wire;
end
end
// Generate user_lnk_up_mux
always @(posedge user_clk_out)
begin
if (!sys_rst_n) begin
user_lnk_up_mux <= #TCQ 1'b0;
end else begin
user_lnk_up_mux <= #TCQ user_lnk_up_int;
end
end
always @(posedge user_clk_out)
begin
if (!sys_rst_n) begin
user_lnk_up_int <= #TCQ 1'b0;
end else begin
user_lnk_up_int <= #TCQ trn_lnk_up;
end
end
// Generate user_reset_out //
// Once user reset output of PCIE and Phy Layer is active, de-assert reset //
// Only assert reset if system reset or hot reset is seen. Keep AXI backend/user application alive otherwise //
//------------------------------------------------------------------------------------------------------------------//
always @(posedge user_clk_out or posedge sys_or_hot_rst)
begin
if (sys_or_hot_rst) begin
user_reset_int <= #TCQ 1'b1;
end else if (user_rst_n && pl_phy_lnk_up_q) begin
user_reset_int <= #TCQ 1'b0;
end
end
// Invert active low reset to active high AXI reset
always @(posedge user_clk_out or posedge sys_or_hot_rst)
begin
if (sys_or_hot_rst) begin
user_reset_out <= #TCQ 1'b1;
end else begin
user_reset_out <= #TCQ user_reset_int;
end
end
always @(posedge user_clk_out or posedge sys_or_hot_rst)
begin
if (sys_or_hot_rst) begin
bridge_reset_int <= #TCQ 1'b1;
end else if (user_rst_n && pl_phy_lnk_up_q) begin
bridge_reset_int <= #TCQ 1'b0;
end
end
// Invert active low reset to active high AXI reset
always @(posedge user_clk_out or posedge sys_or_hot_rst)
begin
if (sys_or_hot_rst) begin
bridge_reset_d <= #TCQ 1'b1;
end else begin
bridge_reset_d <= #TCQ bridge_reset_int;
end
end
//------------------------------------------------------------------------------------------------------------------//
// **** PCI Express Core Wrapper **** //
// The PCI Express Core Wrapper includes the following: //
// 1) AXI Streaming Bridge //
// 2) PCIE 2_1 Hard Block //
// 3) PCIE PIPE Interface Pipeline //
//------------------------------------------------------------------------------------------------------------------//
PCIeGen2x8If128_pcie_top # (
.PIPE_PIPELINE_STAGES ( PIPE_PIPELINE_STAGES ),
.AER_BASE_PTR ( AER_BASE_PTR ),
.AER_CAP_ECRC_CHECK_CAPABLE ( AER_CAP_ECRC_CHECK_CAPABLE ),
.AER_CAP_ECRC_GEN_CAPABLE ( AER_CAP_ECRC_GEN_CAPABLE ),
.AER_CAP_ID ( AER_CAP_ID ),
.AER_CAP_MULTIHEADER ( AER_CAP_MULTIHEADER ),
.AER_CAP_NEXTPTR ( AER_CAP_NEXTPTR ),
.AER_CAP_ON ( AER_CAP_ON ),
.AER_CAP_OPTIONAL_ERR_SUPPORT ( AER_CAP_OPTIONAL_ERR_SUPPORT ),
.AER_CAP_PERMIT_ROOTERR_UPDATE ( AER_CAP_PERMIT_ROOTERR_UPDATE ),
.AER_CAP_VERSION ( AER_CAP_VERSION ),
.ALLOW_X8_GEN2 ( ALLOW_X8_GEN2 ),
.BAR0 ( BAR0 ),
.BAR1 ( BAR1 ),
.BAR2 ( BAR2 ),
.BAR3 ( BAR3 ),
.BAR4 ( BAR4 ),
.BAR5 ( BAR5 ),
.C_DATA_WIDTH ( C_DATA_WIDTH ),
.CAPABILITIES_PTR ( CAPABILITIES_PTR ),
.CARDBUS_CIS_POINTER ( CARDBUS_CIS_POINTER ),
.CFG_ECRC_ERR_CPLSTAT ( CFG_ECRC_ERR_CPLSTAT ),
.CLASS_CODE ( CLASS_CODE ),
.CMD_INTX_IMPLEMENTED ( CMD_INTX_IMPLEMENTED ),
.CPL_TIMEOUT_DISABLE_SUPPORTED ( CPL_TIMEOUT_DISABLE_SUPPORTED ),
.CPL_TIMEOUT_RANGES_SUPPORTED ( CPL_TIMEOUT_RANGES_SUPPORTED ),
.CRM_MODULE_RSTS ( CRM_MODULE_RSTS ),
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ),
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ),
.DEV_CAP_ENDPOINT_L0S_LATENCY ( DEV_CAP_ENDPOINT_L0S_LATENCY ),
.DEV_CAP_ENDPOINT_L1_LATENCY ( DEV_CAP_ENDPOINT_L1_LATENCY ),
.DEV_CAP_EXT_TAG_SUPPORTED ( DEV_CAP_EXT_TAG_SUPPORTED ),
.DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ( DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ),
.DEV_CAP_MAX_PAYLOAD_SUPPORTED ( DEV_CAP_MAX_PAYLOAD_SUPPORTED ),
.DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ( DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ),
.DEV_CAP_ROLE_BASED_ERROR ( DEV_CAP_ROLE_BASED_ERROR ),
.DEV_CAP_RSVD_14_12 ( DEV_CAP_RSVD_14_12 ),
.DEV_CAP_RSVD_17_16 ( DEV_CAP_RSVD_17_16 ),
.DEV_CAP_RSVD_31_29 ( DEV_CAP_RSVD_31_29 ),
.DEV_CONTROL_AUX_POWER_SUPPORTED ( DEV_CONTROL_AUX_POWER_SUPPORTED ),
.DEV_CONTROL_EXT_TAG_DEFAULT ( DEV_CONTROL_EXT_TAG_DEFAULT ),
.DISABLE_ASPM_L1_TIMER ( DISABLE_ASPM_L1_TIMER ),
.DISABLE_BAR_FILTERING ( DISABLE_BAR_FILTERING ),
.DISABLE_ID_CHECK ( DISABLE_ID_CHECK ),
.DISABLE_LANE_REVERSAL ( DISABLE_LANE_REVERSAL ),
.DISABLE_RX_POISONED_RESP ( DISABLE_RX_POISONED_RESP ),
.DISABLE_RX_TC_FILTER ( DISABLE_RX_TC_FILTER ),
.DISABLE_SCRAMBLING ( DISABLE_SCRAMBLING ),
.DNSTREAM_LINK_NUM ( DNSTREAM_LINK_NUM ),
.DSN_BASE_PTR ( DSN_BASE_PTR ),
.DSN_CAP_ID ( DSN_CAP_ID ),
.DSN_CAP_NEXTPTR ( DSN_CAP_NEXTPTR ),
.DSN_CAP_ON ( DSN_CAP_ON ),
.DSN_CAP_VERSION ( DSN_CAP_VERSION ),
.DEV_CAP2_ARI_FORWARDING_SUPPORTED ( DEV_CAP2_ARI_FORWARDING_SUPPORTED ),
.DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED ( DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED ),
.DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED ( DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED ),
.DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED ( DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED ),
.DEV_CAP2_CAS128_COMPLETER_SUPPORTED ( DEV_CAP2_CAS128_COMPLETER_SUPPORTED ),
.DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED ( DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED ),
.DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED ( DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED ),
.DEV_CAP2_LTR_MECHANISM_SUPPORTED ( DEV_CAP2_LTR_MECHANISM_SUPPORTED ),
.DEV_CAP2_MAX_ENDEND_TLP_PREFIXES ( DEV_CAP2_MAX_ENDEND_TLP_PREFIXES ),
.DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING ( DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING ),
.DEV_CAP2_TPH_COMPLETER_SUPPORTED ( DEV_CAP2_TPH_COMPLETER_SUPPORTED ),
.DISABLE_ERR_MSG ( DISABLE_ERR_MSG ),
.DISABLE_LOCKED_FILTER ( DISABLE_LOCKED_FILTER ),
.DISABLE_PPM_FILTER ( DISABLE_PPM_FILTER ),
.ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED ( ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED ),
.ENABLE_MSG_ROUTE ( ENABLE_MSG_ROUTE ),
.ENABLE_RX_TD_ECRC_TRIM ( ENABLE_RX_TD_ECRC_TRIM ),
.ENTER_RVRY_EI_L0 ( ENTER_RVRY_EI_L0 ),
.EXIT_LOOPBACK_ON_EI ( EXIT_LOOPBACK_ON_EI ),
.EXPANSION_ROM ( EXPANSION_ROM ),
.EXT_CFG_CAP_PTR ( EXT_CFG_CAP_PTR ),
.EXT_CFG_XP_CAP_PTR ( EXT_CFG_XP_CAP_PTR ),
.HEADER_TYPE ( HEADER_TYPE ),
.INFER_EI ( INFER_EI ),
.INTERRUPT_PIN ( INTERRUPT_PIN ),
.INTERRUPT_STAT_AUTO ( INTERRUPT_STAT_AUTO ),
.IS_SWITCH ( IS_SWITCH ),
.LAST_CONFIG_DWORD ( LAST_CONFIG_DWORD ),
.LINK_CAP_ASPM_OPTIONALITY ( LINK_CAP_ASPM_OPTIONALITY ),
.LINK_CAP_ASPM_SUPPORT ( LINK_CAP_ASPM_SUPPORT ),
.LINK_CAP_CLOCK_POWER_MANAGEMENT ( LINK_CAP_CLOCK_POWER_MANAGEMENT ),
.LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ( LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ),
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ),
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ),
.LINK_CAP_L0S_EXIT_LATENCY_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_GEN1 ),
.LINK_CAP_L0S_EXIT_LATENCY_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_GEN2 ),
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ),
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ),
.LINK_CAP_L1_EXIT_LATENCY_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_GEN1 ),
.LINK_CAP_L1_EXIT_LATENCY_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_GEN2 ),
.LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ( LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ),
.LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ),
.LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
.LINK_CAP_RSVD_23 ( LINK_CAP_RSVD_23 ),
.LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ( LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ),
.LINK_CONTROL_RCB ( LINK_CONTROL_RCB ),
.LINK_CTRL2_DEEMPHASIS ( LINK_CTRL2_DEEMPHASIS ),
.LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ( LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ),
.LINK_CTRL2_TARGET_LINK_SPEED ( LINK_CTRL2_TARGET_LINK_SPEED ),
.LINK_STATUS_SLOT_CLOCK_CONFIG ( LINK_STATUS_SLOT_CLOCK_CONFIG ),
.LL_ACK_TIMEOUT ( LL_ACK_TIMEOUT ),
.LL_ACK_TIMEOUT_EN ( LL_ACK_TIMEOUT_EN ),
.LL_ACK_TIMEOUT_FUNC ( LL_ACK_TIMEOUT_FUNC ),
.LL_REPLAY_TIMEOUT ( LL_REPLAY_TIMEOUT ),
.LL_REPLAY_TIMEOUT_EN ( LL_REPLAY_TIMEOUT_EN ),
.LL_REPLAY_TIMEOUT_FUNC ( LL_REPLAY_TIMEOUT_FUNC ),
.LTSSM_MAX_LINK_WIDTH ( LTSSM_MAX_LINK_WIDTH ),
.MPS_FORCE ( MPS_FORCE),
.MSI_BASE_PTR ( MSI_BASE_PTR ),
.MSI_CAP_ID ( MSI_CAP_ID ),
.MSI_CAP_MULTIMSGCAP ( MSI_CAP_MULTIMSGCAP ),
.MSI_CAP_MULTIMSG_EXTENSION ( MSI_CAP_MULTIMSG_EXTENSION ),
.MSI_CAP_NEXTPTR ( MSI_CAP_NEXTPTR ),
.MSI_CAP_ON ( MSI_CAP_ON ),
.MSI_CAP_PER_VECTOR_MASKING_CAPABLE ( MSI_CAP_PER_VECTOR_MASKING_CAPABLE ),
.MSI_CAP_64_BIT_ADDR_CAPABLE ( MSI_CAP_64_BIT_ADDR_CAPABLE ),
.MSIX_BASE_PTR ( MSIX_BASE_PTR ),
.MSIX_CAP_ID ( MSIX_CAP_ID ),
.MSIX_CAP_NEXTPTR ( MSIX_CAP_NEXTPTR ),
.MSIX_CAP_ON ( MSIX_CAP_ON ),
.MSIX_CAP_PBA_BIR ( MSIX_CAP_PBA_BIR ),
.MSIX_CAP_PBA_OFFSET ( MSIX_CAP_PBA_OFFSET ),
.MSIX_CAP_TABLE_BIR ( MSIX_CAP_TABLE_BIR ),
.MSIX_CAP_TABLE_OFFSET ( MSIX_CAP_TABLE_OFFSET ),
.MSIX_CAP_TABLE_SIZE ( MSIX_CAP_TABLE_SIZE ),
.N_FTS_COMCLK_GEN1 ( N_FTS_COMCLK_GEN1 ),
.N_FTS_COMCLK_GEN2 ( N_FTS_COMCLK_GEN2 ),
.N_FTS_GEN1 ( N_FTS_GEN1 ),
.N_FTS_GEN2 ( N_FTS_GEN2 ),
.PCIE_BASE_PTR ( PCIE_BASE_PTR ),
.PCIE_CAP_CAPABILITY_ID ( PCIE_CAP_CAPABILITY_ID ),
.PCIE_CAP_CAPABILITY_VERSION ( PCIE_CAP_CAPABILITY_VERSION ),
.PCIE_CAP_DEVICE_PORT_TYPE ( PCIE_CAP_DEVICE_PORT_TYPE ),
.PCIE_CAP_NEXTPTR ( PCIE_CAP_NEXTPTR ),
.PCIE_CAP_ON ( PCIE_CAP_ON ),
.PCIE_CAP_RSVD_15_14 ( PCIE_CAP_RSVD_15_14 ),
.PCIE_CAP_SLOT_IMPLEMENTED ( PCIE_CAP_SLOT_IMPLEMENTED ),
.PCIE_REVISION ( PCIE_REVISION ),
.PL_AUTO_CONFIG ( PL_AUTO_CONFIG ),
// synthesis translate_off
.PL_FAST_TRAIN ( ENABLE_FAST_SIM_TRAINING ),
// synthesis translate_on
.PM_ASPML0S_TIMEOUT ( PM_ASPML0S_TIMEOUT ),
.PM_ASPML0S_TIMEOUT_EN ( PM_ASPML0S_TIMEOUT_EN ),
.PM_ASPML0S_TIMEOUT_FUNC ( PM_ASPML0S_TIMEOUT_FUNC ),
.PM_ASPM_FASTEXIT ( PM_ASPM_FASTEXIT ),
.PM_BASE_PTR ( PM_BASE_PTR ),
.PM_CAP_AUXCURRENT ( PM_CAP_AUXCURRENT ),
.PM_CAP_D1SUPPORT ( PM_CAP_D1SUPPORT ),
.PM_CAP_D2SUPPORT ( PM_CAP_D2SUPPORT ),
.PM_CAP_DSI ( PM_CAP_DSI ),
.PM_CAP_ID ( PM_CAP_ID ),
.PM_CAP_NEXTPTR ( PM_CAP_NEXTPTR ),
.PM_CAP_ON ( PM_CAP_ON ),
.PM_CAP_PME_CLOCK ( PM_CAP_PME_CLOCK ),
.PM_CAP_PMESUPPORT ( PM_CAP_PMESUPPORT ),
.PM_CAP_RSVD_04 ( PM_CAP_RSVD_04 ),
.PM_CAP_VERSION ( PM_CAP_VERSION ),
.PM_CSR_B2B3 ( PM_CSR_B2B3 ),
.PM_CSR_BPCCEN ( PM_CSR_BPCCEN ),
.PM_CSR_NOSOFTRST ( PM_CSR_NOSOFTRST ),
.PM_DATA0 ( PM_DATA0 ),
.PM_DATA1 ( PM_DATA1 ),
.PM_DATA2 ( PM_DATA2 ),
.PM_DATA3 ( PM_DATA3 ),
.PM_DATA4 ( PM_DATA4 ),
.PM_DATA5 ( PM_DATA5 ),
.PM_DATA6 ( PM_DATA6 ),
.PM_DATA7 ( PM_DATA7 ),
.PM_DATA_SCALE0 ( PM_DATA_SCALE0 ),
.PM_DATA_SCALE1 ( PM_DATA_SCALE1 ),
.PM_DATA_SCALE2 ( PM_DATA_SCALE2 ),
.PM_DATA_SCALE3 ( PM_DATA_SCALE3 ),
.PM_DATA_SCALE4 ( PM_DATA_SCALE4 ),
.PM_DATA_SCALE5 ( PM_DATA_SCALE5 ),
.PM_DATA_SCALE6 ( PM_DATA_SCALE6 ),
.PM_DATA_SCALE7 ( PM_DATA_SCALE7 ),
.PM_MF ( PM_MF ),
.RBAR_BASE_PTR ( RBAR_BASE_PTR ),
.RBAR_CAP_CONTROL_ENCODEDBAR0 ( RBAR_CAP_CONTROL_ENCODEDBAR0 ),
.RBAR_CAP_CONTROL_ENCODEDBAR1 ( RBAR_CAP_CONTROL_ENCODEDBAR1 ),
.RBAR_CAP_CONTROL_ENCODEDBAR2 ( RBAR_CAP_CONTROL_ENCODEDBAR2 ),
.RBAR_CAP_CONTROL_ENCODEDBAR3 ( RBAR_CAP_CONTROL_ENCODEDBAR3 ),
.RBAR_CAP_CONTROL_ENCODEDBAR4 ( RBAR_CAP_CONTROL_ENCODEDBAR4 ),
.RBAR_CAP_CONTROL_ENCODEDBAR5 ( RBAR_CAP_CONTROL_ENCODEDBAR5 ),
.RBAR_CAP_ID ( RBAR_CAP_ID),
.RBAR_CAP_INDEX0 ( RBAR_CAP_INDEX0 ),
.RBAR_CAP_INDEX1 ( RBAR_CAP_INDEX1 ),
.RBAR_CAP_INDEX2 ( RBAR_CAP_INDEX2 ),
.RBAR_CAP_INDEX3 ( RBAR_CAP_INDEX3 ),
.RBAR_CAP_INDEX4 ( RBAR_CAP_INDEX4 ),
.RBAR_CAP_INDEX5 ( RBAR_CAP_INDEX5 ),
.RBAR_CAP_NEXTPTR ( RBAR_CAP_NEXTPTR ),
.RBAR_CAP_ON ( RBAR_CAP_ON ),
.RBAR_CAP_SUP0 ( RBAR_CAP_SUP0 ),
.RBAR_CAP_SUP1 ( RBAR_CAP_SUP1 ),
.RBAR_CAP_SUP2 ( RBAR_CAP_SUP2 ),
.RBAR_CAP_SUP3 ( RBAR_CAP_SUP3 ),
.RBAR_CAP_SUP4 ( RBAR_CAP_SUP4 ),
.RBAR_CAP_SUP5 ( RBAR_CAP_SUP5 ),
.RBAR_CAP_VERSION ( RBAR_CAP_VERSION ),
.RBAR_NUM ( RBAR_NUM ),
.RECRC_CHK ( RECRC_CHK ),
.RECRC_CHK_TRIM ( RECRC_CHK_TRIM ),
.ROOT_CAP_CRS_SW_VISIBILITY ( ROOT_CAP_CRS_SW_VISIBILITY ),
.RP_AUTO_SPD ( RP_AUTO_SPD ),
.RP_AUTO_SPD_LOOPCNT ( RP_AUTO_SPD_LOOPCNT ),
.SELECT_DLL_IF ( SELECT_DLL_IF ),
.SLOT_CAP_ATT_BUTTON_PRESENT ( SLOT_CAP_ATT_BUTTON_PRESENT ),
.SLOT_CAP_ATT_INDICATOR_PRESENT ( SLOT_CAP_ATT_INDICATOR_PRESENT ),
.SLOT_CAP_ELEC_INTERLOCK_PRESENT ( SLOT_CAP_ELEC_INTERLOCK_PRESENT ),
.SLOT_CAP_HOTPLUG_CAPABLE ( SLOT_CAP_HOTPLUG_CAPABLE ),
.SLOT_CAP_HOTPLUG_SURPRISE ( SLOT_CAP_HOTPLUG_SURPRISE ),
.SLOT_CAP_MRL_SENSOR_PRESENT ( SLOT_CAP_MRL_SENSOR_PRESENT ),
.SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ( SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ),
.SLOT_CAP_PHYSICAL_SLOT_NUM ( SLOT_CAP_PHYSICAL_SLOT_NUM ),
.SLOT_CAP_POWER_CONTROLLER_PRESENT ( SLOT_CAP_POWER_CONTROLLER_PRESENT ),
.SLOT_CAP_POWER_INDICATOR_PRESENT ( SLOT_CAP_POWER_INDICATOR_PRESENT ),
.SLOT_CAP_SLOT_POWER_LIMIT_SCALE ( SLOT_CAP_SLOT_POWER_LIMIT_SCALE ),
.SLOT_CAP_SLOT_POWER_LIMIT_VALUE ( SLOT_CAP_SLOT_POWER_LIMIT_VALUE ),
.SPARE_BIT0 ( SPARE_BIT0 ),
.SPARE_BIT1 ( SPARE_BIT1 ),
.SPARE_BIT2 ( SPARE_BIT2 ),
.SPARE_BIT3 ( SPARE_BIT3 ),
.SPARE_BIT4 ( SPARE_BIT4 ),
.SPARE_BIT5 ( SPARE_BIT5 ),
.SPARE_BIT6 ( SPARE_BIT6 ),
.SPARE_BIT7 ( SPARE_BIT7 ),
.SPARE_BIT8 ( SPARE_BIT8 ),
.SPARE_BYTE0 ( SPARE_BYTE0 ),
.SPARE_BYTE1 ( SPARE_BYTE1 ),
.SPARE_BYTE2 ( SPARE_BYTE2 ),
.SPARE_BYTE3 ( SPARE_BYTE3 ),
.SPARE_WORD0 ( SPARE_WORD0 ),
.SPARE_WORD1 ( SPARE_WORD1 ),
.SPARE_WORD2 ( SPARE_WORD2 ),
.SPARE_WORD3 ( SPARE_WORD3 ),
.SSL_MESSAGE_AUTO ( SSL_MESSAGE_AUTO ),
.TECRC_EP_INV ( TECRC_EP_INV ),
.TL_RBYPASS ( TL_RBYPASS ),
.TL_RX_RAM_RADDR_LATENCY ( TL_RX_RAM_RADDR_LATENCY ),
.TL_RX_RAM_RDATA_LATENCY ( TL_RX_RAM_RDATA_LATENCY ),
.TL_RX_RAM_WRITE_LATENCY ( TL_RX_RAM_WRITE_LATENCY ),
.TL_TFC_DISABLE ( TL_TFC_DISABLE ),
.TL_TX_CHECKS_DISABLE ( TL_TX_CHECKS_DISABLE ),
.TL_TX_RAM_RADDR_LATENCY ( TL_TX_RAM_RADDR_LATENCY ),
.TL_TX_RAM_RDATA_LATENCY ( TL_TX_RAM_RDATA_LATENCY ),
.TL_TX_RAM_WRITE_LATENCY ( TL_TX_RAM_WRITE_LATENCY ),
.TRN_DW ( TRN_DW ),
.TRN_NP_FC ( TRN_NP_FC ),
.UPCONFIG_CAPABLE ( UPCONFIG_CAPABLE ),
.UPSTREAM_FACING ( UPSTREAM_FACING ),
.UR_ATOMIC ( UR_ATOMIC ),
.UR_CFG1 ( UR_CFG1 ),
.UR_INV_REQ ( UR_INV_REQ ),
.UR_PRS_RESPONSE ( UR_PRS_RESPONSE ),
.USER_CLK2_DIV2 ( USER_CLK2_DIV2 ),
.USER_CLK_FREQ ( USER_CLK_FREQ ),
.USE_RID_PINS ( USE_RID_PINS ),
.VC0_CPL_INFINITE ( VC0_CPL_INFINITE ),
.VC0_RX_RAM_LIMIT ( VC0_RX_RAM_LIMIT ),
.VC0_TOTAL_CREDITS_CD ( VC0_TOTAL_CREDITS_CD ),
.VC0_TOTAL_CREDITS_CH ( VC0_TOTAL_CREDITS_CH ),
.VC0_TOTAL_CREDITS_NPD ( VC0_TOTAL_CREDITS_NPD),
.VC0_TOTAL_CREDITS_NPH ( VC0_TOTAL_CREDITS_NPH ),
.VC0_TOTAL_CREDITS_PD ( VC0_TOTAL_CREDITS_PD ),
.VC0_TOTAL_CREDITS_PH ( VC0_TOTAL_CREDITS_PH ),
.VC0_TX_LASTPACKET ( VC0_TX_LASTPACKET ),
.VC_BASE_PTR ( VC_BASE_PTR ),
.VC_CAP_ID ( VC_CAP_ID ),
.VC_CAP_NEXTPTR ( VC_CAP_NEXTPTR ),
.VC_CAP_ON ( VC_CAP_ON ),
.VC_CAP_REJECT_SNOOP_TRANSACTIONS ( VC_CAP_REJECT_SNOOP_TRANSACTIONS ),
.VC_CAP_VERSION ( VC_CAP_VERSION ),
.VSEC_BASE_PTR ( VSEC_BASE_PTR ),
.VSEC_CAP_HDR_ID ( VSEC_CAP_HDR_ID ),
.VSEC_CAP_HDR_LENGTH ( VSEC_CAP_HDR_LENGTH ),
.VSEC_CAP_HDR_REVISION ( VSEC_CAP_HDR_REVISION ),
.VSEC_CAP_ID ( VSEC_CAP_ID ),
.VSEC_CAP_IS_LINK_VISIBLE ( VSEC_CAP_IS_LINK_VISIBLE ),
.VSEC_CAP_NEXTPTR ( VSEC_CAP_NEXTPTR ),
.VSEC_CAP_ON ( VSEC_CAP_ON ),
.VSEC_CAP_VERSION ( VSEC_CAP_VERSION )
// I/O
) pcie_top_i (
// AXI Interface
.user_clk_out ( user_clk_out ),
.user_reset ( bridge_reset_d ),
.user_lnk_up ( user_lnk_up ),
.user_rst_n ( user_rst_n ),
.trn_lnk_up ( trn_lnk_up ),
.tx_buf_av ( tx_buf_av ),
.tx_err_drop ( tx_err_drop ),
.tx_cfg_req ( tx_cfg_req ),
.s_axis_tx_tready ( s_axis_tx_tready ),
.s_axis_tx_tdata ( s_axis_tx_tdata ),
.s_axis_tx_tkeep ( s_axis_tx_tkeep ),
.s_axis_tx_tuser ( s_axis_tx_tuser ),
.s_axis_tx_tlast ( s_axis_tx_tlast ),
.s_axis_tx_tvalid ( s_axis_tx_tvalid ),
.tx_cfg_gnt ( tx_cfg_gnt ),
.m_axis_rx_tdata ( m_axis_rx_tdata ),
.m_axis_rx_tkeep ( m_axis_rx_tkeep ),
.m_axis_rx_tlast ( m_axis_rx_tlast ),
.m_axis_rx_tvalid ( m_axis_rx_tvalid ),
.m_axis_rx_tready ( m_axis_rx_tready ),
.m_axis_rx_tuser ( m_axis_rx_tuser ),
.rx_np_ok ( rx_np_ok ),
.rx_np_req ( rx_np_req ),
.fc_cpld ( fc_cpld ),
.fc_cplh ( fc_cplh ),
.fc_npd ( fc_npd ),
.fc_nph ( fc_nph ),
.fc_pd ( fc_pd ),
.fc_ph ( fc_ph ),
.fc_sel ( fc_sel ),
.cfg_turnoff_ok ( cfg_turnoff_ok ),
.cfg_received_func_lvl_rst ( cfg_received_func_lvl_rst ),
.cm_rst_n ( 1'b1 ),
.func_lvl_rst_n ( 1'b1 ),
.lnk_clk_en ( ),
.cfg_dev_id ( cfg_dev_id ),
.cfg_vend_id ( cfg_vend_id ),
.cfg_rev_id ( cfg_rev_id ),
.cfg_subsys_id ( cfg_subsys_id ),
.cfg_subsys_vend_id ( cfg_subsys_vend_id ),
.cfg_pciecap_interrupt_msgnum ( cfg_pciecap_interrupt_msgnum ),
.cfg_bridge_serr_en ( cfg_bridge_serr_en ),
.cfg_command_bus_master_enable ( ),
.cfg_command_interrupt_disable ( ),
.cfg_command_io_enable ( ),
.cfg_command_mem_enable ( ),
.cfg_command_serr_en ( ),
.cfg_dev_control_aux_power_en ( ),
.cfg_dev_control_corr_err_reporting_en ( ),
.cfg_dev_control_enable_ro ( ),
.cfg_dev_control_ext_tag_en ( ),
.cfg_dev_control_fatal_err_reporting_en ( ),
.cfg_dev_control_max_payload ( ),
.cfg_dev_control_max_read_req ( ),
.cfg_dev_control_non_fatal_reporting_en ( ),
.cfg_dev_control_no_snoop_en ( ),
.cfg_dev_control_phantom_en ( ),
.cfg_dev_control_ur_err_reporting_en ( ),
.cfg_dev_control2_cpl_timeout_dis ( ),
.cfg_dev_control2_cpl_timeout_val ( ),
.cfg_dev_control2_ari_forward_en ( ),
.cfg_dev_control2_atomic_requester_en ( ),
.cfg_dev_control2_atomic_egress_block ( ),
.cfg_dev_control2_ido_req_en ( ),
.cfg_dev_control2_ido_cpl_en ( ),
.cfg_dev_control2_ltr_en ( ),
.cfg_dev_control2_tlp_prefix_block ( ),
.cfg_dev_status_corr_err_detected ( ),
.cfg_dev_status_fatal_err_detected ( ),
.cfg_dev_status_non_fatal_err_detected ( ),
.cfg_dev_status_ur_detected ( ),
.cfg_mgmt_do ( cfg_mgmt_do ),
.cfg_err_aer_headerlog_set ( cfg_err_aer_headerlog_set ),
.cfg_err_aer_headerlog ( cfg_err_aer_headerlog ),
.cfg_err_cpl_rdy ( cfg_err_cpl_rdy ),
.cfg_interrupt_do ( cfg_interrupt_do ),
.cfg_interrupt_mmenable ( cfg_interrupt_mmenable ),
.cfg_interrupt_msienable ( cfg_interrupt_msienable ),
.cfg_interrupt_msixenable ( cfg_interrupt_msixenable ),
.cfg_interrupt_msixfm ( cfg_interrupt_msixfm ),
.cfg_interrupt_rdy ( cfg_interrupt_rdy ),
.cfg_link_control_rcb ( ),
.cfg_link_control_aspm_control ( ),
.cfg_link_control_auto_bandwidth_int_en ( ),
.cfg_link_control_bandwidth_int_en ( ),
.cfg_link_control_clock_pm_en ( ),
.cfg_link_control_common_clock ( ),
.cfg_link_control_extended_sync ( ),
.cfg_link_control_hw_auto_width_dis ( ),
.cfg_link_control_link_disable ( ),
.cfg_link_control_retrain_link ( ),
.cfg_link_status_auto_bandwidth_status ( ),
.cfg_link_status_bandwidth_status ( ),
.cfg_link_status_current_speed ( ),
.cfg_link_status_dll_active ( ),
.cfg_link_status_link_training ( ),
.cfg_link_status_negotiated_width ( ),
.cfg_msg_data ( cfg_msg_data ),
.cfg_msg_received ( cfg_msg_received ),
.cfg_msg_received_assert_int_a ( cfg_msg_received_assert_int_a ),
.cfg_msg_received_assert_int_b ( cfg_msg_received_assert_int_b ),
.cfg_msg_received_assert_int_c ( cfg_msg_received_assert_int_c ),
.cfg_msg_received_assert_int_d ( cfg_msg_received_assert_int_d ),
.cfg_msg_received_deassert_int_a ( cfg_msg_received_deassert_int_a ),
.cfg_msg_received_deassert_int_b ( cfg_msg_received_deassert_int_b ),
.cfg_msg_received_deassert_int_c ( cfg_msg_received_deassert_int_c ),
.cfg_msg_received_deassert_int_d ( cfg_msg_received_deassert_int_d ),
.cfg_msg_received_err_cor ( cfg_msg_received_err_cor ),
.cfg_msg_received_err_fatal ( cfg_msg_received_err_fatal ),
.cfg_msg_received_err_non_fatal ( cfg_msg_received_err_non_fatal ),
.cfg_msg_received_pm_as_nak ( cfg_msg_received_pm_as_nak ),
.cfg_msg_received_pme_to ( ),
.cfg_msg_received_pme_to_ack ( cfg_msg_received_pme_to_ack ),
.cfg_msg_received_pm_pme ( cfg_msg_received_pm_pme ),
.cfg_msg_received_setslotpowerlimit ( cfg_msg_received_setslotpowerlimit ),
.cfg_msg_received_unlock ( ),
.cfg_to_turnoff ( cfg_to_turnoff ),
.cfg_status ( cfg_status ),
.cfg_command ( cfg_command ),
.cfg_dstatus ( cfg_dstatus ),
.cfg_dcommand ( cfg_dcommand ),
.cfg_lstatus ( cfg_lstatus ),
.cfg_lcommand ( cfg_lcommand ),
.cfg_dcommand2 ( cfg_dcommand2 ),
.cfg_pcie_link_state ( cfg_pcie_link_state ),
.cfg_pmcsr_pme_en ( cfg_pmcsr_pme_en ),
.cfg_pmcsr_powerstate ( cfg_pmcsr_powerstate ),
.cfg_pmcsr_pme_status ( cfg_pmcsr_pme_status ),
.cfg_pm_rcv_as_req_l1_n ( ),
.cfg_pm_rcv_enter_l1_n ( ),
.cfg_pm_rcv_enter_l23_n ( ),
.cfg_pm_rcv_req_ack_n ( ),
.cfg_mgmt_rd_wr_done ( cfg_mgmt_rd_wr_done ),
.cfg_slot_control_electromech_il_ctl_pulse ( cfg_slot_control_electromech_il_ctl_pulse ),
.cfg_root_control_syserr_corr_err_en ( cfg_root_control_syserr_corr_err_en ),
.cfg_root_control_syserr_non_fatal_err_en ( cfg_root_control_syserr_non_fatal_err_en ),
.cfg_root_control_syserr_fatal_err_en ( cfg_root_control_syserr_fatal_err_en ),
.cfg_root_control_pme_int_en ( cfg_root_control_pme_int_en),
.cfg_aer_ecrc_check_en ( cfg_aer_ecrc_check_en ),
.cfg_aer_ecrc_gen_en ( cfg_aer_ecrc_gen_en ),
.cfg_aer_rooterr_corr_err_reporting_en ( cfg_aer_rooterr_corr_err_reporting_en ),
.cfg_aer_rooterr_non_fatal_err_reporting_en ( cfg_aer_rooterr_non_fatal_err_reporting_en ),
.cfg_aer_rooterr_fatal_err_reporting_en ( cfg_aer_rooterr_fatal_err_reporting_en ),
.cfg_aer_rooterr_corr_err_received ( cfg_aer_rooterr_corr_err_received ),
.cfg_aer_rooterr_non_fatal_err_received ( cfg_aer_rooterr_non_fatal_err_received ),
.cfg_aer_rooterr_fatal_err_received ( cfg_aer_rooterr_fatal_err_received ),
.cfg_aer_interrupt_msgnum ( cfg_aer_interrupt_msgnum ),
.cfg_transaction ( ),
.cfg_transaction_addr ( ),
.cfg_transaction_type ( ),
.cfg_vc_tcvc_map ( cfg_vc_tcvc_map ),
.cfg_mgmt_byte_en_n ( ~cfg_mgmt_byte_en ),
.cfg_mgmt_di ( cfg_mgmt_di ),
.cfg_dsn ( cfg_dsn ),
.cfg_mgmt_dwaddr ( cfg_mgmt_dwaddr ),
.cfg_err_acs_n ( 1'b1 ),
.cfg_err_cor_n ( ~cfg_err_cor ),
.cfg_err_cpl_abort_n ( ~cfg_err_cpl_abort ),
.cfg_err_cpl_timeout_n ( ~cfg_err_cpl_timeout ),
.cfg_err_cpl_unexpect_n ( ~cfg_err_cpl_unexpect ),
.cfg_err_ecrc_n ( ~cfg_err_ecrc ),
.cfg_err_locked_n ( ~cfg_err_locked ),
.cfg_err_posted_n ( ~cfg_err_posted ),
.cfg_err_tlp_cpl_header ( cfg_err_tlp_cpl_header ),
.cfg_err_ur_n ( ~cfg_err_ur ),
.cfg_err_malformed_n ( ~cfg_err_malformed ),
.cfg_err_poisoned_n ( ~cfg_err_poisoned ),
.cfg_err_atomic_egress_blocked_n ( ~cfg_err_atomic_egress_blocked ),
.cfg_err_mc_blocked_n ( ~cfg_err_mc_blocked ),
.cfg_err_internal_uncor_n ( ~cfg_err_internal_uncor ),
.cfg_err_internal_cor_n ( ~cfg_err_internal_cor ),
.cfg_err_norecovery_n ( ~cfg_err_norecovery ),
.cfg_interrupt_assert_n ( ~cfg_interrupt_assert ),
.cfg_interrupt_di ( cfg_interrupt_di ),
.cfg_interrupt_n ( ~cfg_interrupt ),
.cfg_interrupt_stat_n ( ~cfg_interrupt_stat ),
.cfg_bus_number ( cfg_bus_number ),
.cfg_device_number ( cfg_device_number ),
.cfg_function_number ( cfg_function_number ),
.cfg_ds_bus_number ( cfg_ds_bus_number ),
.cfg_ds_device_number ( cfg_ds_device_number ),
.cfg_ds_function_number ( cfg_ds_function_number ),
.cfg_pm_send_pme_to_n ( 1'b1 ),
.cfg_pm_wake_n ( ~cfg_pm_wake ),
.cfg_pm_halt_aspm_l0s_n ( ~cfg_pm_halt_aspm_l0s ),
.cfg_pm_halt_aspm_l1_n ( ~cfg_pm_halt_aspm_l1 ),
.cfg_pm_force_state_en_n ( ~cfg_pm_force_state_en),
.cfg_pm_force_state ( cfg_pm_force_state ),
.cfg_force_mps ( 3'b0 ),
.cfg_force_common_clock_off ( 1'b0 ),
.cfg_force_extended_sync_on ( 1'b0 ),
.cfg_port_number ( 8'b0 ),
.cfg_mgmt_rd_en_n ( ~cfg_mgmt_rd_en ),
.cfg_trn_pending ( cfg_trn_pending ),
.cfg_mgmt_wr_en_n ( ~cfg_mgmt_wr_en ),
.cfg_mgmt_wr_readonly_n ( ~cfg_mgmt_wr_readonly ),
.cfg_mgmt_wr_rw1c_as_rw_n ( ~cfg_mgmt_wr_rw1c_as_rw ),
.pl_initial_link_width ( pl_initial_link_width ),
.pl_lane_reversal_mode ( pl_lane_reversal_mode ),
.pl_link_gen2_cap ( pl_link_gen2_cap ),
.pl_link_partner_gen2_supported ( pl_link_partner_gen2_supported ),
.pl_link_upcfg_cap ( pl_link_upcfg_cap ),
.pl_ltssm_state ( pl_ltssm_state_int ),
.pl_phy_lnk_up ( pl_phy_lnk_up_wire ),
.pl_received_hot_rst ( pl_received_hot_rst_wire ),
.pl_rx_pm_state ( pl_rx_pm_state ),
.pl_sel_lnk_rate ( pl_sel_lnk_rate ),
.pl_sel_lnk_width ( pl_sel_lnk_width ),
.pl_tx_pm_state ( pl_tx_pm_state ),
.pl_directed_link_auton ( pl_directed_link_auton ),
.pl_directed_link_change ( pl_directed_link_change ),
.pl_directed_link_speed ( pl_directed_link_speed ),
.pl_directed_link_width ( pl_directed_link_width ),
.pl_downstream_deemph_source ( pl_downstream_deemph_source ),
.pl_upstream_prefer_deemph ( pl_upstream_prefer_deemph ),
.pl_transmit_hot_rst ( pl_transmit_hot_rst ),
.pl_directed_ltssm_new_vld ( 1'b0 ),
.pl_directed_ltssm_new ( 6'b0 ),
.pl_directed_ltssm_stall ( 1'b0 ),
.pl_directed_change_done ( pl_directed_change_done ),
.phy_rdy_n ( phy_rdy_n ),
.dbg_sclr_a ( ),
.dbg_sclr_b ( ),
.dbg_sclr_c ( ),
.dbg_sclr_d ( ),
.dbg_sclr_e ( ),
.dbg_sclr_f ( ),
.dbg_sclr_g ( ),
.dbg_sclr_h ( ),
.dbg_sclr_i ( ),
.dbg_sclr_j ( ),
.dbg_sclr_k ( ),
.dbg_vec_a ( ),
.dbg_vec_b ( ),
.dbg_vec_c ( ),
.pl_dbg_vec ( ),
.trn_rdllp_data ( ),
.trn_rdllp_src_rdy ( ),
.dbg_mode ( 2'b0 ),
.dbg_sub_mode ( 1'b0 ),
.pl_dbg_mode ( 3'b0 ),
.drp_clk ( pcie_drp_clk ),
.drp_do ( pcie_drp_do ),
.drp_rdy ( pcie_drp_rdy ),
.drp_addr ( pcie_drp_addr ),
.drp_en ( pcie_drp_en ),
.drp_di ( pcie_drp_di ),
.drp_we ( pcie_drp_we ),
// Pipe Interface
.pipe_clk ( pipe_clk ),
.user_clk ( user_clk ),
.user_clk2 ( user_clk2 ),
.pipe_rx0_polarity_gt ( pipe_rx0_polarity_gt ),
.pipe_rx1_polarity_gt ( pipe_rx1_polarity_gt ),
.pipe_rx2_polarity_gt ( pipe_rx2_polarity_gt ),
.pipe_rx3_polarity_gt ( pipe_rx3_polarity_gt ),
.pipe_rx4_polarity_gt ( pipe_rx4_polarity_gt ),
.pipe_rx5_polarity_gt ( pipe_rx5_polarity_gt ),
.pipe_rx6_polarity_gt ( pipe_rx6_polarity_gt ),
.pipe_rx7_polarity_gt ( pipe_rx7_polarity_gt ),
.pipe_tx_deemph_gt ( pipe_tx_deemph_gt ),
.pipe_tx_margin_gt ( pipe_tx_margin_gt ),
.pipe_tx_rate_gt ( pipe_tx_rate_gt ),
.pipe_tx_rcvr_det_gt ( pipe_tx_rcvr_det_gt ),
.pipe_tx0_char_is_k_gt ( pipe_tx0_char_is_k_gt ),
.pipe_tx0_compliance_gt ( pipe_tx0_compliance_gt ),
.pipe_tx0_data_gt ( pipe_tx0_data_gt ),
.pipe_tx0_elec_idle_gt ( pipe_tx0_elec_idle_gt ),
.pipe_tx0_powerdown_gt ( pipe_tx0_powerdown_gt ),
.pipe_tx1_char_is_k_gt ( pipe_tx1_char_is_k_gt ),
.pipe_tx1_compliance_gt ( pipe_tx1_compliance_gt ),
.pipe_tx1_data_gt ( pipe_tx1_data_gt ),
.pipe_tx1_elec_idle_gt ( pipe_tx1_elec_idle_gt ),
.pipe_tx1_powerdown_gt ( pipe_tx1_powerdown_gt ),
.pipe_tx2_char_is_k_gt ( pipe_tx2_char_is_k_gt ),
.pipe_tx2_compliance_gt ( pipe_tx2_compliance_gt ),
.pipe_tx2_data_gt ( pipe_tx2_data_gt ),
.pipe_tx2_elec_idle_gt ( pipe_tx2_elec_idle_gt ),
.pipe_tx2_powerdown_gt ( pipe_tx2_powerdown_gt ),
.pipe_tx3_char_is_k_gt ( pipe_tx3_char_is_k_gt ),
.pipe_tx3_compliance_gt ( pipe_tx3_compliance_gt ),
.pipe_tx3_data_gt ( pipe_tx3_data_gt ),
.pipe_tx3_elec_idle_gt ( pipe_tx3_elec_idle_gt ),
.pipe_tx3_powerdown_gt ( pipe_tx3_powerdown_gt ),
.pipe_tx4_char_is_k_gt ( pipe_tx4_char_is_k_gt ),
.pipe_tx4_compliance_gt ( pipe_tx4_compliance_gt ),
.pipe_tx4_data_gt ( pipe_tx4_data_gt ),
.pipe_tx4_elec_idle_gt ( pipe_tx4_elec_idle_gt ),
.pipe_tx4_powerdown_gt ( pipe_tx4_powerdown_gt ),
.pipe_tx5_char_is_k_gt ( pipe_tx5_char_is_k_gt ),
.pipe_tx5_compliance_gt ( pipe_tx5_compliance_gt ),
.pipe_tx5_data_gt ( pipe_tx5_data_gt ),
.pipe_tx5_elec_idle_gt ( pipe_tx5_elec_idle_gt ),
.pipe_tx5_powerdown_gt ( pipe_tx5_powerdown_gt ),
.pipe_tx6_char_is_k_gt ( pipe_tx6_char_is_k_gt ),
.pipe_tx6_compliance_gt ( pipe_tx6_compliance_gt ),
.pipe_tx6_data_gt ( pipe_tx6_data_gt ),
.pipe_tx6_elec_idle_gt ( pipe_tx6_elec_idle_gt ),
.pipe_tx6_powerdown_gt ( pipe_tx6_powerdown_gt ),
.pipe_tx7_char_is_k_gt ( pipe_tx7_char_is_k_gt ),
.pipe_tx7_compliance_gt ( pipe_tx7_compliance_gt ),
.pipe_tx7_data_gt ( pipe_tx7_data_gt ),
.pipe_tx7_elec_idle_gt ( pipe_tx7_elec_idle_gt ),
.pipe_tx7_powerdown_gt ( pipe_tx7_powerdown_gt ),
.pipe_rx0_chanisaligned_gt ( pipe_rx0_chanisaligned_gt ),
.pipe_rx0_char_is_k_gt ( pipe_rx0_char_is_k_gt ),
.pipe_rx0_data_gt ( pipe_rx0_data_gt ),
.pipe_rx0_elec_idle_gt ( pipe_rx0_elec_idle_gt ),
.pipe_rx0_phy_status_gt ( pipe_rx0_phy_status_gt ),
.pipe_rx0_status_gt ( pipe_rx0_status_gt ),
.pipe_rx0_valid_gt ( pipe_rx0_valid_gt ),
.pipe_rx1_chanisaligned_gt ( pipe_rx1_chanisaligned_gt ),
.pipe_rx1_char_is_k_gt ( pipe_rx1_char_is_k_gt ),
.pipe_rx1_data_gt ( pipe_rx1_data_gt ),
.pipe_rx1_elec_idle_gt ( pipe_rx1_elec_idle_gt ),
.pipe_rx1_phy_status_gt ( pipe_rx1_phy_status_gt ),
.pipe_rx1_status_gt ( pipe_rx1_status_gt ),
.pipe_rx1_valid_gt ( pipe_rx1_valid_gt ),
.pipe_rx2_chanisaligned_gt ( pipe_rx2_chanisaligned_gt ),
.pipe_rx2_char_is_k_gt ( pipe_rx2_char_is_k_gt ),
.pipe_rx2_data_gt ( pipe_rx2_data_gt ),
.pipe_rx2_elec_idle_gt ( pipe_rx2_elec_idle_gt ),
.pipe_rx2_phy_status_gt ( pipe_rx2_phy_status_gt ),
.pipe_rx2_status_gt ( pipe_rx2_status_gt ),
.pipe_rx2_valid_gt ( pipe_rx2_valid_gt ),
.pipe_rx3_chanisaligned_gt ( pipe_rx3_chanisaligned_gt ),
.pipe_rx3_char_is_k_gt ( pipe_rx3_char_is_k_gt ),
.pipe_rx3_data_gt ( pipe_rx3_data_gt ),
.pipe_rx3_elec_idle_gt ( pipe_rx3_elec_idle_gt ),
.pipe_rx3_phy_status_gt ( pipe_rx3_phy_status_gt ),
.pipe_rx3_status_gt ( pipe_rx3_status_gt ),
.pipe_rx3_valid_gt ( pipe_rx3_valid_gt ),
.pipe_rx4_chanisaligned_gt ( pipe_rx4_chanisaligned_gt ),
.pipe_rx4_char_is_k_gt ( pipe_rx4_char_is_k_gt ),
.pipe_rx4_data_gt ( pipe_rx4_data_gt ),
.pipe_rx4_elec_idle_gt ( pipe_rx4_elec_idle_gt ),
.pipe_rx4_phy_status_gt ( pipe_rx4_phy_status_gt ),
.pipe_rx4_status_gt ( pipe_rx4_status_gt ),
.pipe_rx4_valid_gt ( pipe_rx4_valid_gt ),
.pipe_rx5_chanisaligned_gt ( pipe_rx5_chanisaligned_gt ),
.pipe_rx5_char_is_k_gt ( pipe_rx5_char_is_k_gt ),
.pipe_rx5_data_gt ( pipe_rx5_data_gt ),
.pipe_rx5_elec_idle_gt ( pipe_rx5_elec_idle_gt ),
.pipe_rx5_phy_status_gt ( pipe_rx5_phy_status_gt ),
.pipe_rx5_status_gt ( pipe_rx5_status_gt ),
.pipe_rx5_valid_gt ( pipe_rx5_valid_gt ),
.pipe_rx6_chanisaligned_gt ( pipe_rx6_chanisaligned_gt ),
.pipe_rx6_char_is_k_gt ( pipe_rx6_char_is_k_gt ),
.pipe_rx6_data_gt ( pipe_rx6_data_gt ),
.pipe_rx6_elec_idle_gt ( pipe_rx6_elec_idle_gt ),
.pipe_rx6_phy_status_gt ( pipe_rx6_phy_status_gt ),
.pipe_rx6_status_gt ( pipe_rx6_status_gt ),
.pipe_rx6_valid_gt ( pipe_rx6_valid_gt ),
.pipe_rx7_chanisaligned_gt ( pipe_rx7_chanisaligned_gt ),
.pipe_rx7_char_is_k_gt ( pipe_rx7_char_is_k_gt ),
.pipe_rx7_data_gt ( pipe_rx7_data_gt ),
.pipe_rx7_elec_idle_gt ( pipe_rx7_elec_idle_gt ),
.pipe_rx7_phy_status_gt ( pipe_rx7_phy_status_gt ),
.pipe_rx7_status_gt ( pipe_rx7_status_gt ),
.pipe_rx7_valid_gt ( pipe_rx7_valid_gt )
);
assign common_commands_out = 12'b0;
assign pipe_tx_0_sigs = 23'b0;
assign pipe_tx_1_sigs = 23'b0;
assign pipe_tx_2_sigs = 23'b0;
assign pipe_tx_3_sigs = 23'b0;
assign pipe_tx_4_sigs = 23'b0;
assign pipe_tx_5_sigs = 23'b0;
assign pipe_tx_6_sigs = 23'b0;
assign pipe_tx_7_sigs = 23'b0;
//------------------------------------------------------------------------------------------------------------------//
// **** V7/K7/A7 GTX Wrapper **** //
// The 7-Series GTX Wrapper includes the following: //
// 1) Virtex-7 GTX //
// 2) Kintex-7 GTX //
// 3) Artix-7 GTP //
//------------------------------------------------------------------------------------------------------------------//
PCIeGen2x8If128_gt_top #(
.LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
.REF_CLK_FREQ ( REF_CLK_FREQ ),
.USER_CLK_FREQ ( USER_CLK_FREQ ),
.USER_CLK2_DIV2 ( USER_CLK2_DIV2 ),
// synthesis translate_off
.PL_FAST_TRAIN ( ENABLE_FAST_SIM_TRAINING ),
// synthesis translate_on
.PCIE_EXT_CLK ( PCIE_EXT_CLK ),
.PCIE_USE_MODE ( PCIE_USE_MODE ),
.PCIE_GT_DEVICE ( PCIE_GT_DEVICE ),
.PCIE_PLL_SEL ( PCIE_PLL_SEL ),
.PCIE_ASYNC_EN ( PCIE_ASYNC_EN ),
.PCIE_TXBUF_EN ( PCIE_TXBUF_EN ),
.PCIE_EXT_GT_COMMON ( PCIE_EXT_GT_COMMON ),
.EXT_CH_GT_DRP ( EXT_CH_GT_DRP ),
.TX_MARGIN_FULL_0 ( TX_MARGIN_FULL_0 ),
.TX_MARGIN_FULL_1 ( TX_MARGIN_FULL_1 ),
.TX_MARGIN_FULL_2 ( TX_MARGIN_FULL_2 ),
.TX_MARGIN_FULL_3 ( TX_MARGIN_FULL_3 ),
.TX_MARGIN_FULL_4 ( TX_MARGIN_FULL_4 ),
.TX_MARGIN_LOW_0 ( TX_MARGIN_LOW_0 ),
.TX_MARGIN_LOW_1 ( TX_MARGIN_LOW_1 ),
.TX_MARGIN_LOW_2 ( TX_MARGIN_LOW_2 ),
.TX_MARGIN_LOW_3 ( TX_MARGIN_LOW_3 ),
.TX_MARGIN_LOW_4 ( TX_MARGIN_LOW_4 ),
.PCIE_CHAN_BOND ( PCIE_CHAN_BOND )
) gt_top_i (
// pl ltssm
.pl_ltssm_state ( pl_ltssm_state_int ),
// Pipe Common Signals
.pipe_tx_rcvr_det ( pipe_tx_rcvr_det_gt ),
.pipe_tx_reset ( 1'b0 ),
.pipe_tx_rate ( pipe_tx_rate_gt ),
.pipe_tx_deemph ( pipe_tx_deemph_gt ),
.pipe_tx_margin ( pipe_tx_margin_gt ),
.pipe_tx_swing ( 1'b0 ),
// Pipe Per-Lane Signals - Lane 0
.pipe_rx0_char_is_k ( pipe_rx0_char_is_k_gt),
.pipe_rx0_data ( pipe_rx0_data_gt ),
.pipe_rx0_valid ( pipe_rx0_valid_gt ),
.pipe_rx0_chanisaligned ( pipe_rx0_chanisaligned_gt ),
.pipe_rx0_status ( pipe_rx0_status_gt ),
.pipe_rx0_phy_status ( pipe_rx0_phy_status_gt ),
.pipe_rx0_elec_idle ( pipe_rx0_elec_idle_gt ),
.pipe_rx0_polarity ( pipe_rx0_polarity_gt ),
.pipe_tx0_compliance ( pipe_tx0_compliance_gt ),
.pipe_tx0_char_is_k ( pipe_tx0_char_is_k_gt ),
.pipe_tx0_data ( pipe_tx0_data_gt ),
.pipe_tx0_elec_idle ( pipe_tx0_elec_idle_gt ),
.pipe_tx0_powerdown ( pipe_tx0_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 1
.pipe_rx1_char_is_k ( pipe_rx1_char_is_k_gt),
.pipe_rx1_data ( pipe_rx1_data_gt ),
.pipe_rx1_valid ( pipe_rx1_valid_gt ),
.pipe_rx1_chanisaligned ( pipe_rx1_chanisaligned_gt ),
.pipe_rx1_status ( pipe_rx1_status_gt ),
.pipe_rx1_phy_status ( pipe_rx1_phy_status_gt ),
.pipe_rx1_elec_idle ( pipe_rx1_elec_idle_gt ),
.pipe_rx1_polarity ( pipe_rx1_polarity_gt ),
.pipe_tx1_compliance ( pipe_tx1_compliance_gt ),
.pipe_tx1_char_is_k ( pipe_tx1_char_is_k_gt ),
.pipe_tx1_data ( pipe_tx1_data_gt ),
.pipe_tx1_elec_idle ( pipe_tx1_elec_idle_gt ),
.pipe_tx1_powerdown ( pipe_tx1_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 2
.pipe_rx2_char_is_k ( pipe_rx2_char_is_k_gt),
.pipe_rx2_data ( pipe_rx2_data_gt ),
.pipe_rx2_valid ( pipe_rx2_valid_gt ),
.pipe_rx2_chanisaligned ( pipe_rx2_chanisaligned_gt ),
.pipe_rx2_status ( pipe_rx2_status_gt ),
.pipe_rx2_phy_status ( pipe_rx2_phy_status_gt ),
.pipe_rx2_elec_idle ( pipe_rx2_elec_idle_gt ),
.pipe_rx2_polarity ( pipe_rx2_polarity_gt ),
.pipe_tx2_compliance ( pipe_tx2_compliance_gt ),
.pipe_tx2_char_is_k ( pipe_tx2_char_is_k_gt ),
.pipe_tx2_data ( pipe_tx2_data_gt ),
.pipe_tx2_elec_idle ( pipe_tx2_elec_idle_gt ),
.pipe_tx2_powerdown ( pipe_tx2_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 3
.pipe_rx3_char_is_k ( pipe_rx3_char_is_k_gt),
.pipe_rx3_data ( pipe_rx3_data_gt ),
.pipe_rx3_valid ( pipe_rx3_valid_gt ),
.pipe_rx3_chanisaligned ( pipe_rx3_chanisaligned_gt ),
.pipe_rx3_status ( pipe_rx3_status_gt ),
.pipe_rx3_phy_status ( pipe_rx3_phy_status_gt ),
.pipe_rx3_elec_idle ( pipe_rx3_elec_idle_gt ),
.pipe_rx3_polarity ( pipe_rx3_polarity_gt ),
.pipe_tx3_compliance ( pipe_tx3_compliance_gt ),
.pipe_tx3_char_is_k ( pipe_tx3_char_is_k_gt ),
.pipe_tx3_data ( pipe_tx3_data_gt ),
.pipe_tx3_elec_idle ( pipe_tx3_elec_idle_gt ),
.pipe_tx3_powerdown ( pipe_tx3_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 4
.pipe_rx4_char_is_k ( pipe_rx4_char_is_k_gt),
.pipe_rx4_data ( pipe_rx4_data_gt ),
.pipe_rx4_valid ( pipe_rx4_valid_gt ),
.pipe_rx4_chanisaligned ( pipe_rx4_chanisaligned_gt ),
.pipe_rx4_status ( pipe_rx4_status_gt ),
.pipe_rx4_phy_status ( pipe_rx4_phy_status_gt ),
.pipe_rx4_elec_idle ( pipe_rx4_elec_idle_gt ),
.pipe_rx4_polarity ( pipe_rx4_polarity_gt ),
.pipe_tx4_compliance ( pipe_tx4_compliance_gt ),
.pipe_tx4_char_is_k ( pipe_tx4_char_is_k_gt ),
.pipe_tx4_data ( pipe_tx4_data_gt ),
.pipe_tx4_elec_idle ( pipe_tx4_elec_idle_gt ),
.pipe_tx4_powerdown ( pipe_tx4_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 5
.pipe_rx5_char_is_k ( pipe_rx5_char_is_k_gt),
.pipe_rx5_data ( pipe_rx5_data_gt ),
.pipe_rx5_valid ( pipe_rx5_valid_gt ),
.pipe_rx5_chanisaligned ( pipe_rx5_chanisaligned_gt ),
.pipe_rx5_status ( pipe_rx5_status_gt ),
.pipe_rx5_phy_status ( pipe_rx5_phy_status_gt ),
.pipe_rx5_elec_idle ( pipe_rx5_elec_idle_gt ),
.pipe_rx5_polarity ( pipe_rx5_polarity_gt ),
.pipe_tx5_compliance ( pipe_tx5_compliance_gt ),
.pipe_tx5_char_is_k ( pipe_tx5_char_is_k_gt ),
.pipe_tx5_data ( pipe_tx5_data_gt ),
.pipe_tx5_elec_idle ( pipe_tx5_elec_idle_gt ),
.pipe_tx5_powerdown ( pipe_tx5_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 6
.pipe_rx6_char_is_k ( pipe_rx6_char_is_k_gt),
.pipe_rx6_data ( pipe_rx6_data_gt ),
.pipe_rx6_valid ( pipe_rx6_valid_gt ),
.pipe_rx6_chanisaligned ( pipe_rx6_chanisaligned_gt ),
.pipe_rx6_status ( pipe_rx6_status_gt ),
.pipe_rx6_phy_status ( pipe_rx6_phy_status_gt ),
.pipe_rx6_elec_idle ( pipe_rx6_elec_idle_gt ),
.pipe_rx6_polarity ( pipe_rx6_polarity_gt ),
.pipe_tx6_compliance ( pipe_tx6_compliance_gt ),
.pipe_tx6_char_is_k ( pipe_tx6_char_is_k_gt ),
.pipe_tx6_data ( pipe_tx6_data_gt ),
.pipe_tx6_elec_idle ( pipe_tx6_elec_idle_gt ),
.pipe_tx6_powerdown ( pipe_tx6_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 7
.pipe_rx7_char_is_k ( pipe_rx7_char_is_k_gt),
.pipe_rx7_data ( pipe_rx7_data_gt ),
.pipe_rx7_valid ( pipe_rx7_valid_gt ),
.pipe_rx7_chanisaligned ( pipe_rx7_chanisaligned_gt ),
.pipe_rx7_status ( pipe_rx7_status_gt ),
.pipe_rx7_phy_status ( pipe_rx7_phy_status_gt ),
.pipe_rx7_elec_idle ( pipe_rx7_elec_idle_gt ),
.pipe_rx7_polarity ( pipe_rx7_polarity_gt ),
.pipe_tx7_compliance ( pipe_tx7_compliance_gt ),
.pipe_tx7_char_is_k ( pipe_tx7_char_is_k_gt ),
.pipe_tx7_data ( pipe_tx7_data_gt ),
.pipe_tx7_elec_idle ( pipe_tx7_elec_idle_gt ),
.pipe_tx7_powerdown ( pipe_tx7_powerdown_gt ),
// PCI Express Signals
.pci_exp_txn ( pci_exp_txn ),
.pci_exp_txp ( pci_exp_txp ),
.pci_exp_rxn ( pci_exp_rxn ),
.pci_exp_rxp ( pci_exp_rxp ),
// Non PIPE Signals
.sys_clk ( sys_clk ),
.sys_rst_n ( sys_rst_n ),
.PIPE_MMCM_RST_N ( pipe_mmcm_rst_n ), // Async | Async
.pipe_clk ( pipe_clk ),
.user_clk ( user_clk ),
.user_clk2 ( user_clk2 ),
.phy_rdy_n ( phy_rdy_n ),
// ---------- Shared Logic Internal------------------
.INT_PCLK_OUT_SLAVE ( int_pclk_out_slave ),
.INT_RXUSRCLK_OUT ( int_pipe_rxusrclk_out ),
.INT_RXOUTCLK_OUT ( int_rxoutclk_out ),
.INT_DCLK_OUT ( int_dclk_out ),
.INT_USERCLK1_OUT ( int_userclk1_out ),
.INT_USERCLK2_OUT ( int_userclk2_out),
.INT_OOBCLK_OUT ( int_oobclk_out),
.INT_MMCM_LOCK_OUT ( int_mmcm_lock_out ),
.INT_QPLLLOCK_OUT ( int_qplllock_out ),
.INT_QPLLOUTCLK_OUT ( int_qplloutclk_out ),
.INT_QPLLOUTREFCLK_OUT ( int_qplloutrefclk_out ),
.INT_PCLK_SEL_SLAVE ( int_pclk_sel_slave ),
// ---------- Shared Logic External------------------
//External Clock Ports
.PIPE_PCLK_IN ( pipe_pclk_in ),
.PIPE_RXUSRCLK_IN ( pipe_rxusrclk_in ),
.PIPE_RXOUTCLK_IN ( pipe_rxoutclk_in ),
.PIPE_DCLK_IN ( pipe_dclk_in ),
.PIPE_USERCLK1_IN ( pipe_userclk1_in ),
.PIPE_USERCLK2_IN ( pipe_userclk2_in ),
.PIPE_OOBCLK_IN ( pipe_oobclk_in ),
.PIPE_MMCM_LOCK_IN ( pipe_mmcm_lock_in ),
.PIPE_TXOUTCLK_OUT ( pipe_txoutclk_out ),
.PIPE_RXOUTCLK_OUT ( pipe_rxoutclk_out ),
.PIPE_PCLK_SEL_OUT ( pipe_pclk_sel_out ),
.PIPE_GEN3_OUT ( pipe_gen3_out ),
//External GT COMMON Ports
.qpll_drp_crscode ( qpll_drp_crscode ),
.qpll_drp_fsm ( qpll_drp_fsm ),
.qpll_drp_done ( qpll_drp_done ),
.qpll_drp_reset ( qpll_drp_reset ),
.qpll_qplllock ( qpll_qplllock ),
.qpll_qplloutclk ( qpll_qplloutclk ),
.qpll_qplloutrefclk ( qpll_qplloutrefclk ),
.qpll_qplld ( qpll_qplld ),
.qpll_qpllreset ( qpll_qpllreset ),
.qpll_drp_clk ( qpll_drp_clk ),
.qpll_drp_rst_n ( qpll_drp_rst_n ),
.qpll_drp_ovrd ( qpll_drp_ovrd ),
.qpll_drp_gen3 ( qpll_drp_gen3),
.qpll_drp_start ( qpll_drp_start ),
//TRANSCEIVER DEBUG EOU
.ext_ch_gt_drpclk ( ext_ch_gt_drpclk ),
.ext_ch_gt_drpaddr ( ext_ch_gt_drpaddr ),
.ext_ch_gt_drpen ( ext_ch_gt_drpen ),
.ext_ch_gt_drpdi ( ext_ch_gt_drpdi ),
.ext_ch_gt_drpwe ( ext_ch_gt_drpwe ),
.ext_ch_gt_drpdo ( ext_ch_gt_drpdo ),
.ext_ch_gt_drprdy ( ext_ch_gt_drprdy ),
//---------- PRBS/Loopback Ports -----------------------
.PIPE_TXPRBSSEL ( pipe_txprbssel ),
.PIPE_RXPRBSSEL ( pipe_rxprbssel ),
.PIPE_TXPRBSFORCEERR ( pipe_txprbsforceerr ),
.PIPE_RXPRBSCNTRESET ( pipe_rxprbscntreset ),
.PIPE_LOOPBACK ( pipe_loopback ),
.PIPE_RXPRBSERR ( pipe_rxprbserr ),
.PIPE_TXINHIBIT ( pipe_txinhibit ),
//---------- Transceiver Debug FSM Ports ---------------------------------
.PIPE_RST_FSM ( pipe_rst_fsm ),
.PIPE_QRST_FSM ( pipe_qrst_fsm ),
.PIPE_RATE_FSM ( pipe_rate_fsm ),
.PIPE_SYNC_FSM_TX ( pipe_sync_fsm_tx ),
.PIPE_SYNC_FSM_RX ( pipe_sync_fsm_rx ),
.PIPE_DRP_FSM ( pipe_drp_fsm ),
.PIPE_RST_IDLE ( pipe_rst_idle ),
.PIPE_QRST_IDLE ( pipe_qrst_idle ),
.PIPE_RATE_IDLE ( pipe_rate_idle ),
.PIPE_EYESCANDATAERROR ( pipe_eyescandataerror ),
.PIPE_RXSTATUS ( pipe_rxstatus ),
.PIPE_DMONITOROUT ( pipe_dmonitorout ),
.PIPE_CPLL_LOCK ( pipe_cpll_lock ),
.PIPE_QPLL_LOCK ( pipe_qpll_lock ),
.PIPE_RXPMARESETDONE ( pipe_rxpmaresetdone ),
.PIPE_RXBUFSTATUS ( pipe_rxbufstatus ),
.PIPE_TXPHALIGNDONE ( pipe_txphaligndone ),
.PIPE_TXPHINITDONE ( pipe_txphinitdone ),
.PIPE_TXDLYSRESETDONE ( pipe_txdlysresetdone ),
.PIPE_RXPHALIGNDONE ( pipe_rxphaligndone ),
.PIPE_RXDLYSRESETDONE ( pipe_rxdlysresetdone ),
.PIPE_RXSYNCDONE ( pipe_rxsyncdone ),
.PIPE_RXDISPERR ( pipe_rxdisperr ),
.PIPE_RXNOTINTABLE ( pipe_rxnotintable ),
.PIPE_RXCOMMADET ( pipe_rxcommadet ),
//---------- JTAG Ports --------------------------------
.PIPE_JTAG_RDY (gt_ch_drp_rdy ),
//---------- Debug Ports -------------------------------
.PIPE_DEBUG_0 ( pipe_debug_0 ),
.PIPE_DEBUG_1 ( pipe_debug_1 ),
.PIPE_DEBUG_2 ( pipe_debug_2 ),
.PIPE_DEBUG_3 ( pipe_debug_3 ),
.PIPE_DEBUG_4 ( pipe_debug_4 ),
.PIPE_DEBUG_5 ( pipe_debug_5 ),
.PIPE_DEBUG_6 ( pipe_debug_6 ),
.PIPE_DEBUG_7 ( pipe_debug_7 ),
.PIPE_DEBUG_8 ( pipe_debug_8 ),
.PIPE_DEBUG_9 ( pipe_debug_9 ),
.PIPE_DEBUG ( pipe_debug )
);
assign common_commands_out = 12'b0;
assign pipe_tx_0_sigs = 23'b0;
assign pipe_tx_1_sigs = 23'b0;
assign pipe_tx_2_sigs = 23'b0;
assign pipe_tx_3_sigs = 23'b0;
assign pipe_tx_4_sigs = 23'b0;
assign pipe_tx_5_sigs = 23'b0;
assign pipe_tx_6_sigs = 23'b0;
assign pipe_tx_7_sigs = 23'b0;
//------------------------------------------------------------------------------------------------------------------//
// Tie-Off Unused Tandem Outputs
assign icap_o = 32'b0;
assign startup_cfgclk = 1'b0;
assign startup_cfgmclk = 1'b0;
assign startup_eos = 1'b0;
assign startup_preq = 1'b0;
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2012 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(** * Int31 numbers defines indeed a cyclic structure : Z/(2^31)Z *)
(**
Author: Arnaud Spiwack (+ Pierre Letouzey)
*)
Require Import List.
Require Import Min.
Require Export Int31.
Require Import Znumtheory.
Require Import Zgcd_alt.
Require Import Zpow_facts.
Require Import BigNumPrelude.
Require Import CyclicAxioms.
Require Import ROmega.
Local Open Scope nat_scope.
Local Open Scope int31_scope.
Section Basics.
(** * Basic results about [iszero], [shiftl], [shiftr] *)
Lemma iszero_eq0 : forall x, iszero x = true -> x=0.
Proof.
destruct x; simpl; intros.
repeat
match goal with H:(if ?d then _ else _) = true |- _ =>
destruct d; try discriminate
end.
reflexivity.
Qed.
Lemma iszero_not_eq0 : forall x, iszero x = false -> x<>0.
Proof.
intros x H Eq; rewrite Eq in H; simpl in *; discriminate.
Qed.
Lemma sneakl_shiftr : forall x,
x = sneakl (firstr x) (shiftr x).
Proof.
destruct x; simpl; auto.
Qed.
Lemma sneakr_shiftl : forall x,
x = sneakr (firstl x) (shiftl x).
Proof.
destruct x; simpl; auto.
Qed.
Lemma twice_zero : forall x,
twice x = 0 <-> twice_plus_one x = 1.
Proof.
destruct x; simpl in *; split;
intro H; injection H; intros; subst; auto.
Qed.
Lemma twice_or_twice_plus_one : forall x,
x = twice (shiftr x) \/ x = twice_plus_one (shiftr x).
Proof.
intros; case_eq (firstr x); intros.
destruct x; simpl in *; rewrite H; auto.
destruct x; simpl in *; rewrite H; auto.
Qed.
(** * Iterated shift to the right *)
Definition nshiftr x := nat_rect _ x (fun _ => shiftr).
Lemma nshiftr_S :
forall n x, nshiftr x (S n) = shiftr (nshiftr x n).
Proof.
reflexivity.
Qed.
Lemma nshiftr_S_tail :
forall n x, nshiftr x (S n) = nshiftr (shiftr x) n.
Proof.
intros n; elim n; simpl; auto.
intros; now f_equal.
Qed.
Lemma nshiftr_n_0 : forall n, nshiftr 0 n = 0.
Proof.
induction n; simpl; auto.
rewrite IHn; auto.
Qed.
Lemma nshiftr_size : forall x, nshiftr x size = 0.
Proof.
destruct x; simpl; auto.
Qed.
Lemma nshiftr_above_size : forall k x, size<=k ->
nshiftr x k = 0.
Proof.
intros.
replace k with ((k-size)+size)%nat by omega.
induction (k-size)%nat; auto.
rewrite nshiftr_size; auto.
simpl; rewrite IHn; auto.
Qed.
(** * Iterated shift to the left *)
Definition nshiftl x := nat_rect _ x (fun _ => shiftl).
Lemma nshiftl_S :
forall n x, nshiftl x (S n) = shiftl (nshiftl x n).
Proof.
reflexivity.
Qed.
Lemma nshiftl_S_tail :
forall n x, nshiftl x (S n) = nshiftl (shiftl x) n.
Proof.
intros n; elim n; simpl; intros; now f_equal.
Qed.
Lemma nshiftl_n_0 : forall n, nshiftl 0 n = 0.
Proof.
induction n; simpl; auto.
rewrite IHn; auto.
Qed.
Lemma nshiftl_size : forall x, nshiftl x size = 0.
Proof.
destruct x; simpl; auto.
Qed.
Lemma nshiftl_above_size : forall k x, size<=k ->
nshiftl x k = 0.
Proof.
intros.
replace k with ((k-size)+size)%nat by omega.
induction (k-size)%nat; auto.
rewrite nshiftl_size; auto.
simpl; rewrite IHn; auto.
Qed.
Lemma firstr_firstl :
forall x, firstr x = firstl (nshiftl x (pred size)).
Proof.
destruct x; simpl; auto.
Qed.
Lemma firstl_firstr :
forall x, firstl x = firstr (nshiftr x (pred size)).
Proof.
destruct x; simpl; auto.
Qed.
(** More advanced results about [nshiftr] *)
Lemma nshiftr_predsize_0_firstl : forall x,
nshiftr x (pred size) = 0 -> firstl x = D0.
Proof.
destruct x; compute; intros H; injection H; intros; subst; auto.
Qed.
Lemma nshiftr_0_propagates : forall n p x, n <= p ->
nshiftr x n = 0 -> nshiftr x p = 0.
Proof.
intros.
replace p with ((p-n)+n)%nat by omega.
induction (p-n)%nat.
simpl; auto.
simpl; rewrite IHn0; auto.
Qed.
Lemma nshiftr_0_firstl : forall n x, n < size ->
nshiftr x n = 0 -> firstl x = D0.
Proof.
intros.
apply nshiftr_predsize_0_firstl.
apply nshiftr_0_propagates with n; auto; omega.
Qed.
(** * Some induction principles over [int31] *)
(** Not used for the moment. Are they really useful ? *)
Lemma int31_ind_sneakl : forall P : int31->Prop,
P 0 ->
(forall x d, P x -> P (sneakl d x)) ->
forall x, P x.
Proof.
intros.
assert (forall n, n<=size -> P (nshiftr x (size - n))).
induction n; intros.
rewrite nshiftr_size; auto.
rewrite sneakl_shiftr.
apply H0.
change (P (nshiftr x (S (size - S n)))).
replace (S (size - S n))%nat with (size - n)%nat by omega.
apply IHn; omega.
change x with (nshiftr x (size-size)); auto.
Qed.
Lemma int31_ind_twice : forall P : int31->Prop,
P 0 ->
(forall x, P x -> P (twice x)) ->
(forall x, P x -> P (twice_plus_one x)) ->
forall x, P x.
Proof.
induction x using int31_ind_sneakl; auto.
destruct d; auto.
Qed.
(** * Some generic results about [recr] *)
Section Recr.
(** [recr] satisfies the fixpoint equation used for its definition. *)
Variable (A:Type)(case0:A)(caserec:digits->int31->A->A).
Lemma recr_aux_eqn : forall n x, iszero x = false ->
recr_aux (S n) A case0 caserec x =
caserec (firstr x) (shiftr x) (recr_aux n A case0 caserec (shiftr x)).
Proof.
intros; simpl; rewrite H; auto.
Qed.
Lemma recr_aux_converges :
forall n p x, n <= size -> n <= p ->
recr_aux n A case0 caserec (nshiftr x (size - n)) =
recr_aux p A case0 caserec (nshiftr x (size - n)).
Proof.
induction n.
simpl minus; intros.
rewrite nshiftr_size; destruct p; simpl; auto.
intros.
destruct p.
inversion H0.
unfold recr_aux; fold recr_aux.
destruct (iszero (nshiftr x (size - S n))); auto.
f_equal.
change (shiftr (nshiftr x (size - S n))) with (nshiftr x (S (size - S n))).
replace (S (size - S n))%nat with (size - n)%nat by omega.
apply IHn; auto with arith.
Qed.
Lemma recr_eqn : forall x, iszero x = false ->
recr A case0 caserec x =
caserec (firstr x) (shiftr x) (recr A case0 caserec (shiftr x)).
Proof.
intros.
unfold recr.
change x with (nshiftr x (size - size)).
rewrite (recr_aux_converges size (S size)); auto with arith.
rewrite recr_aux_eqn; auto.
Qed.
(** [recr] is usually equivalent to a variant [recrbis]
written without [iszero] check. *)
Fixpoint recrbis_aux (n:nat)(A:Type)(case0:A)(caserec:digits->int31->A->A)
(i:int31) : A :=
match n with
| O => case0
| S next =>
let si := shiftr i in
caserec (firstr i) si (recrbis_aux next A case0 caserec si)
end.
Definition recrbis := recrbis_aux size.
Hypothesis case0_caserec : caserec D0 0 case0 = case0.
Lemma recrbis_aux_equiv : forall n x,
recrbis_aux n A case0 caserec x = recr_aux n A case0 caserec x.
Proof.
induction n; simpl; auto; intros.
case_eq (iszero x); intros; [ | f_equal; auto ].
rewrite (iszero_eq0 _ H); simpl; auto.
replace (recrbis_aux n A case0 caserec 0) with case0; auto.
clear H IHn; induction n; simpl; congruence.
Qed.
Lemma recrbis_equiv : forall x,
recrbis A case0 caserec x = recr A case0 caserec x.
Proof.
intros; apply recrbis_aux_equiv; auto.
Qed.
End Recr.
(** * Incrementation *)
Section Incr.
(** Variant of [incr] via [recrbis] *)
Let Incr (b : digits) (si rec : int31) :=
match b with
| D0 => sneakl D1 si
| D1 => sneakl D0 rec
end.
Definition incrbis_aux n x := recrbis_aux n _ In Incr x.
Lemma incrbis_aux_equiv : forall x, incrbis_aux size x = incr x.
Proof.
unfold incr, recr, incrbis_aux; fold Incr; intros.
apply recrbis_aux_equiv; auto.
Qed.
(** Recursive equations satisfied by [incr] *)
Lemma incr_eqn1 :
forall x, firstr x = D0 -> incr x = twice_plus_one (shiftr x).
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H0); simpl; auto.
unfold incr; rewrite recr_eqn; fold incr; auto.
rewrite H; auto.
Qed.
Lemma incr_eqn2 :
forall x, firstr x = D1 -> incr x = twice (incr (shiftr x)).
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H0) in H; simpl in H; discriminate.
unfold incr; rewrite recr_eqn; fold incr; auto.
rewrite H; auto.
Qed.
Lemma incr_twice : forall x, incr (twice x) = twice_plus_one x.
Proof.
intros.
rewrite incr_eqn1; destruct x; simpl; auto.
Qed.
Lemma incr_twice_plus_one_firstl :
forall x, firstl x = D0 -> incr (twice_plus_one x) = twice (incr x).
Proof.
intros.
rewrite incr_eqn2; [ | destruct x; simpl; auto ].
f_equal; f_equal.
destruct x; simpl in *; rewrite H; auto.
Qed.
(** The previous result is actually true even without the
constraint on [firstl], but this is harder to prove
(see later). *)
End Incr.
(** * Conversion to [Z] : the [phi] function *)
Section Phi.
(** Variant of [phi] via [recrbis] *)
Let Phi := fun b (_:int31) =>
match b with D0 => Z.double | D1 => Z.succ_double end.
Definition phibis_aux n x := recrbis_aux n _ Z0 Phi x.
Lemma phibis_aux_equiv : forall x, phibis_aux size x = phi x.
Proof.
unfold phi, recr, phibis_aux; fold Phi; intros.
apply recrbis_aux_equiv; auto.
Qed.
(** Recursive equations satisfied by [phi] *)
Lemma phi_eqn1 : forall x, firstr x = D0 ->
phi x = Z.double (phi (shiftr x)).
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H0); simpl; auto.
intros; unfold phi; rewrite recr_eqn; fold phi; auto.
rewrite H; auto.
Qed.
Lemma phi_eqn2 : forall x, firstr x = D1 ->
phi x = Z.succ_double (phi (shiftr x)).
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H0) in H; simpl in H; discriminate.
intros; unfold phi; rewrite recr_eqn; fold phi; auto.
rewrite H; auto.
Qed.
Lemma phi_twice_firstl : forall x, firstl x = D0 ->
phi (twice x) = Z.double (phi x).
Proof.
intros.
rewrite phi_eqn1; auto; [ | destruct x; auto ].
f_equal; f_equal.
destruct x; simpl in *; rewrite H; auto.
Qed.
Lemma phi_twice_plus_one_firstl : forall x, firstl x = D0 ->
phi (twice_plus_one x) = Z.succ_double (phi x).
Proof.
intros.
rewrite phi_eqn2; auto; [ | destruct x; auto ].
f_equal; f_equal.
destruct x; simpl in *; rewrite H; auto.
Qed.
End Phi.
(** [phi x] is positive and lower than [2^31] *)
Lemma phibis_aux_pos : forall n x, (0 <= phibis_aux n x)%Z.
Proof.
induction n.
simpl; unfold phibis_aux; simpl; auto with zarith.
intros.
unfold phibis_aux, recrbis_aux; fold recrbis_aux;
fold (phibis_aux n (shiftr x)).
destruct (firstr x).
specialize IHn with (shiftr x); rewrite Z.double_spec; omega.
specialize IHn with (shiftr x); rewrite Z.succ_double_spec; omega.
Qed.
Lemma phibis_aux_bounded :
forall n x, n <= size ->
(phibis_aux n (nshiftr x (size-n)) < 2 ^ (Z.of_nat n))%Z.
Proof.
induction n.
simpl minus; unfold phibis_aux; simpl; auto with zarith.
intros.
unfold phibis_aux, recrbis_aux; fold recrbis_aux;
fold (phibis_aux n (shiftr (nshiftr x (size - S n)))).
assert (shiftr (nshiftr x (size - S n)) = nshiftr x (size-n)).
replace (size - n)%nat with (S (size - (S n))) by omega.
simpl; auto.
rewrite H0.
assert (H1 : n <= size) by omega.
specialize (IHn x H1).
set (y:=phibis_aux n (nshiftr x (size - n))) in *.
rewrite Nat2Z.inj_succ, Z.pow_succ_r; auto with zarith.
case_eq (firstr (nshiftr x (size - S n))); intros.
rewrite Z.double_spec; auto with zarith.
rewrite Z.succ_double_spec; auto with zarith.
Qed.
Lemma phi_bounded : forall x, (0 <= phi x < 2 ^ (Z.of_nat size))%Z.
Proof.
intros.
rewrite <- phibis_aux_equiv.
split.
apply phibis_aux_pos.
change x with (nshiftr x (size-size)).
apply phibis_aux_bounded; auto.
Qed.
Lemma phibis_aux_lowerbound :
forall n x, firstr (nshiftr x n) = D1 ->
(2 ^ Z.of_nat n <= phibis_aux (S n) x)%Z.
Proof.
induction n.
intros.
unfold nshiftr in H; simpl in *.
unfold phibis_aux, recrbis_aux.
rewrite H, Z.succ_double_spec; omega.
intros.
remember (S n) as m.
unfold phibis_aux, recrbis_aux; fold recrbis_aux;
fold (phibis_aux m (shiftr x)).
subst m.
rewrite Nat2Z.inj_succ, Z.pow_succ_r; auto with zarith.
assert (2^(Z.of_nat n) <= phibis_aux (S n) (shiftr x))%Z.
apply IHn.
rewrite <- nshiftr_S_tail; auto.
destruct (firstr x).
change (Z.double (phibis_aux (S n) (shiftr x))) with
(2*(phibis_aux (S n) (shiftr x)))%Z.
omega.
rewrite Z.succ_double_spec; omega.
Qed.
Lemma phi_lowerbound :
forall x, firstl x = D1 -> (2^(Z.of_nat (pred size)) <= phi x)%Z.
Proof.
intros.
generalize (phibis_aux_lowerbound (pred size) x).
rewrite <- firstl_firstr.
change (S (pred size)) with size; auto.
rewrite phibis_aux_equiv; auto.
Qed.
(** * Equivalence modulo [2^n] *)
Section EqShiftL.
(** After killing [n] bits at the left, are the numbers equal ?*)
Definition EqShiftL n x y :=
nshiftl x n = nshiftl y n.
Lemma EqShiftL_zero : forall x y, EqShiftL O x y <-> x = y.
Proof.
unfold EqShiftL; intros; unfold nshiftl; simpl; split; auto.
Qed.
Lemma EqShiftL_size : forall k x y, size<=k -> EqShiftL k x y.
Proof.
red; intros; rewrite 2 nshiftl_above_size; auto.
Qed.
Lemma EqShiftL_le : forall k k' x y, k <= k' ->
EqShiftL k x y -> EqShiftL k' x y.
Proof.
unfold EqShiftL; intros.
replace k' with ((k'-k)+k)%nat by omega.
remember (k'-k)%nat as n.
clear Heqn H k'.
induction n; simpl; auto.
f_equal; auto.
Qed.
Lemma EqShiftL_firstr : forall k x y, k < size ->
EqShiftL k x y -> firstr x = firstr y.
Proof.
intros.
rewrite 2 firstr_firstl.
f_equal.
apply EqShiftL_le with k; auto.
unfold size.
auto with arith.
Qed.
Lemma EqShiftL_twice : forall k x y,
EqShiftL k (twice x) (twice y) <-> EqShiftL (S k) x y.
Proof.
intros; unfold EqShiftL.
rewrite 2 nshiftl_S_tail; split; auto.
Qed.
(** * From int31 to list of digits. *)
(** Lower (=rightmost) bits comes first. *)
Definition i2l := recrbis _ nil (fun d _ rec => d::rec).
Lemma i2l_length : forall x, length (i2l x) = size.
Proof.
intros; reflexivity.
Qed.
Fixpoint lshiftl l x :=
match l with
| nil => x
| d::l => sneakl d (lshiftl l x)
end.
Definition l2i l := lshiftl l On.
Lemma l2i_i2l : forall x, l2i (i2l x) = x.
Proof.
destruct x; compute; auto.
Qed.
Lemma i2l_sneakr : forall x d,
i2l (sneakr d x) = tail (i2l x) ++ d::nil.
Proof.
destruct x; compute; auto.
Qed.
Lemma i2l_sneakl : forall x d,
i2l (sneakl d x) = d :: removelast (i2l x).
Proof.
destruct x; compute; auto.
Qed.
Lemma i2l_l2i : forall l, length l = size ->
i2l (l2i l) = l.
Proof.
repeat (destruct l as [ |? l]; [intros; discriminate | ]).
destruct l; [ | intros; discriminate].
intros _; compute; auto.
Qed.
Fixpoint cstlist (A:Type)(a:A) n :=
match n with
| O => nil
| S n => a::cstlist _ a n
end.
Lemma i2l_nshiftl : forall n x, n<=size ->
i2l (nshiftl x n) = cstlist _ D0 n ++ firstn (size-n) (i2l x).
Proof.
induction n.
intros.
assert (firstn (size-0) (i2l x) = i2l x).
rewrite <- minus_n_O, <- (i2l_length x).
induction (i2l x); simpl; f_equal; auto.
rewrite H0; clear H0.
reflexivity.
intros.
rewrite nshiftl_S.
unfold shiftl; rewrite i2l_sneakl.
simpl cstlist.
rewrite <- app_comm_cons; f_equal.
rewrite IHn; [ | omega].
rewrite removelast_app.
apply f_equal.
replace (size-n)%nat with (S (size - S n))%nat by omega.
rewrite removelast_firstn; auto.
rewrite i2l_length; omega.
generalize (firstn_length (size-n) (i2l x)).
rewrite i2l_length.
intros H0 H1. rewrite H1 in H0.
rewrite min_l in H0 by omega.
simpl length in H0.
omega.
Qed.
(** [i2l] can be used to define a relation equivalent to [EqShiftL] *)
Lemma EqShiftL_i2l : forall k x y,
EqShiftL k x y <-> firstn (size-k) (i2l x) = firstn (size-k) (i2l y).
Proof.
intros.
destruct (le_lt_dec size k) as [Hle|Hlt].
split; intros.
replace (size-k)%nat with O by omega.
unfold firstn; auto.
apply EqShiftL_size; auto.
unfold EqShiftL.
assert (k <= size) by omega.
split; intros.
assert (i2l (nshiftl x k) = i2l (nshiftl y k)) by (f_equal; auto).
rewrite 2 i2l_nshiftl in H1; auto.
eapply app_inv_head; eauto.
assert (i2l (nshiftl x k) = i2l (nshiftl y k)).
rewrite 2 i2l_nshiftl; auto.
f_equal; auto.
rewrite <- (l2i_i2l (nshiftl x k)), <- (l2i_i2l (nshiftl y k)).
f_equal; auto.
Qed.
(** This equivalence allows proving easily the following delicate
result *)
Lemma EqShiftL_twice_plus_one : forall k x y,
EqShiftL k (twice_plus_one x) (twice_plus_one y) <-> EqShiftL (S k) x y.
Proof.
intros.
destruct (le_lt_dec size k) as [Hle|Hlt].
split; intros; apply EqShiftL_size; auto.
rewrite 2 EqShiftL_i2l.
unfold twice_plus_one.
rewrite 2 i2l_sneakl.
replace (size-k)%nat with (S (size - S k))%nat by omega.
remember (size - S k)%nat as n.
remember (i2l x) as lx.
remember (i2l y) as ly.
simpl.
rewrite 2 firstn_removelast.
split; intros.
injection H; auto.
f_equal; auto.
subst ly n; rewrite i2l_length; omega.
subst lx n; rewrite i2l_length; omega.
Qed.
Lemma EqShiftL_shiftr : forall k x y, EqShiftL k x y ->
EqShiftL (S k) (shiftr x) (shiftr y).
Proof.
intros.
destruct (le_lt_dec size (S k)) as [Hle|Hlt].
apply EqShiftL_size; auto.
case_eq (firstr x); intros.
rewrite <- EqShiftL_twice.
unfold twice; rewrite <- H0.
rewrite <- sneakl_shiftr.
rewrite (EqShiftL_firstr k x y); auto.
rewrite <- sneakl_shiftr; auto.
omega.
rewrite <- EqShiftL_twice_plus_one.
unfold twice_plus_one; rewrite <- H0.
rewrite <- sneakl_shiftr.
rewrite (EqShiftL_firstr k x y); auto.
rewrite <- sneakl_shiftr; auto.
omega.
Qed.
Lemma EqShiftL_incrbis : forall n k x y, n<=size ->
(n+k=S size)%nat ->
EqShiftL k x y ->
EqShiftL k (incrbis_aux n x) (incrbis_aux n y).
Proof.
induction n; simpl; intros.
red; auto.
destruct (eq_nat_dec k size).
subst k; apply EqShiftL_size; auto.
unfold incrbis_aux; simpl;
fold (incrbis_aux n (shiftr x)); fold (incrbis_aux n (shiftr y)).
rewrite (EqShiftL_firstr k x y); auto; try omega.
case_eq (firstr y); intros.
rewrite EqShiftL_twice_plus_one.
apply EqShiftL_shiftr; auto.
rewrite EqShiftL_twice.
apply IHn; try omega.
apply EqShiftL_shiftr; auto.
Qed.
Lemma EqShiftL_incr : forall x y,
EqShiftL 1 x y -> EqShiftL 1 (incr x) (incr y).
Proof.
intros.
rewrite <- 2 incrbis_aux_equiv.
apply EqShiftL_incrbis; auto.
Qed.
End EqShiftL.
(** * More equations about [incr] *)
Lemma incr_twice_plus_one :
forall x, incr (twice_plus_one x) = twice (incr x).
Proof.
intros.
rewrite incr_eqn2; [ | destruct x; simpl; auto].
apply EqShiftL_incr.
red; destruct x; simpl; auto.
Qed.
Lemma incr_firstr : forall x, firstr (incr x) <> firstr x.
Proof.
intros.
case_eq (firstr x); intros.
rewrite incr_eqn1; auto.
destruct (shiftr x); simpl; discriminate.
rewrite incr_eqn2; auto.
destruct (incr (shiftr x)); simpl; discriminate.
Qed.
Lemma incr_inv : forall x y,
incr x = twice_plus_one y -> x = twice y.
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H0) in *; simpl in *.
change (incr 0) with 1 in H.
symmetry; rewrite twice_zero; auto.
case_eq (firstr x); intros.
rewrite incr_eqn1 in H; auto.
clear H0; destruct x; destruct y; simpl in *.
injection H; intros; subst; auto.
elim (incr_firstr x).
rewrite H1, H; destruct y; simpl; auto.
Qed.
(** * Conversion from [Z] : the [phi_inv] function *)
(** First, recursive equations *)
Lemma phi_inv_double_plus_one : forall z,
phi_inv (Z.succ_double z) = twice_plus_one (phi_inv z).
Proof.
destruct z; simpl; auto.
induction p; simpl.
rewrite 2 incr_twice; auto.
rewrite incr_twice, incr_twice_plus_one.
f_equal.
apply incr_inv; auto.
auto.
Qed.
Lemma phi_inv_double : forall z,
phi_inv (Z.double z) = twice (phi_inv z).
Proof.
destruct z; simpl; auto.
rewrite incr_twice_plus_one; auto.
Qed.
Lemma phi_inv_incr : forall z,
phi_inv (Z.succ z) = incr (phi_inv z).
Proof.
destruct z.
simpl; auto.
simpl; auto.
induction p; simpl; auto.
rewrite <- Pos.add_1_r, IHp, incr_twice_plus_one; auto.
rewrite incr_twice; auto.
simpl; auto.
destruct p; simpl; auto.
rewrite incr_twice; auto.
f_equal.
rewrite incr_twice_plus_one; auto.
induction p; simpl; auto.
rewrite incr_twice; auto.
f_equal.
rewrite incr_twice_plus_one; auto.
Qed.
(** [phi_inv o inv], the always-exact and easy-to-prove trip :
from int31 to Z and then back to int31. *)
Lemma phi_inv_phi_aux :
forall n x, n <= size ->
phi_inv (phibis_aux n (nshiftr x (size-n))) =
nshiftr x (size-n).
Proof.
induction n.
intros; simpl minus.
rewrite nshiftr_size; auto.
intros.
unfold phibis_aux, recrbis_aux; fold recrbis_aux;
fold (phibis_aux n (shiftr (nshiftr x (size-S n)))).
assert (shiftr (nshiftr x (size - S n)) = nshiftr x (size-n)).
replace (size - n)%nat with (S (size - (S n))); auto; omega.
rewrite H0.
case_eq (firstr (nshiftr x (size - S n))); intros.
rewrite phi_inv_double.
rewrite IHn by omega.
rewrite <- H0.
remember (nshiftr x (size - S n)) as y.
destruct y; simpl in H1; rewrite H1; auto.
rewrite phi_inv_double_plus_one.
rewrite IHn by omega.
rewrite <- H0.
remember (nshiftr x (size - S n)) as y.
destruct y; simpl in H1; rewrite H1; auto.
Qed.
Lemma phi_inv_phi : forall x, phi_inv (phi x) = x.
Proof.
intros.
rewrite <- phibis_aux_equiv.
replace x with (nshiftr x (size - size)) by auto.
apply phi_inv_phi_aux; auto.
Qed.
(** The other composition [phi o phi_inv] is harder to prove correct.
In particular, an overflow can happen, so a modulo is needed.
For the moment, we proceed via several steps, the first one
being a detour to [positive_to_in31]. *)
(** * [positive_to_int31] *)
(** A variant of [p2i] with [twice] and [twice_plus_one] instead of
[2*i] and [2*i+1] *)
Fixpoint p2ibis n p : (N*int31)%type :=
match n with
| O => (Npos p, On)
| S n => match p with
| xO p => let (r,i) := p2ibis n p in (r, twice i)
| xI p => let (r,i) := p2ibis n p in (r, twice_plus_one i)
| xH => (N0, In)
end
end.
Lemma p2ibis_bounded : forall n p,
nshiftr (snd (p2ibis n p)) n = 0.
Proof.
induction n.
simpl; intros; auto.
simpl p2ibis; intros.
destruct p; simpl snd.
specialize IHn with p.
destruct (p2ibis n p). simpl @snd in *.
rewrite nshiftr_S_tail.
destruct (le_lt_dec size n) as [Hle|Hlt].
rewrite nshiftr_above_size; auto.
assert (H:=nshiftr_0_firstl _ _ Hlt IHn).
replace (shiftr (twice_plus_one i)) with i; auto.
destruct i; simpl in *. rewrite H; auto.
specialize IHn with p.
destruct (p2ibis n p); simpl @snd in *.
rewrite nshiftr_S_tail.
destruct (le_lt_dec size n) as [Hle|Hlt].
rewrite nshiftr_above_size; auto.
assert (H:=nshiftr_0_firstl _ _ Hlt IHn).
replace (shiftr (twice i)) with i; auto.
destruct i; simpl in *; rewrite H; auto.
rewrite nshiftr_S_tail; auto.
replace (shiftr In) with 0; auto.
apply nshiftr_n_0.
Qed.
Local Open Scope Z_scope.
Lemma p2ibis_spec : forall n p, (n<=size)%nat ->
Zpos p = (Z.of_N (fst (p2ibis n p)))*2^(Z.of_nat n) +
phi (snd (p2ibis n p)).
Proof.
induction n; intros.
simpl; rewrite Pos.mul_1_r; auto.
replace (2^(Z.of_nat (S n)))%Z with (2*2^(Z.of_nat n))%Z by
(rewrite <- Z.pow_succ_r, <- Zpos_P_of_succ_nat;
auto with zarith).
rewrite (Z.mul_comm 2).
assert (n<=size)%nat by omega.
destruct p; simpl; [ | | auto];
specialize (IHn p H0);
generalize (p2ibis_bounded n p);
destruct (p2ibis n p) as (r,i); simpl in *; intros.
change (Zpos p~1) with (2*Zpos p + 1)%Z.
rewrite phi_twice_plus_one_firstl, Z.succ_double_spec.
rewrite IHn; ring.
apply (nshiftr_0_firstl n); auto; try omega.
change (Zpos p~0) with (2*Zpos p)%Z.
rewrite phi_twice_firstl.
change (Z.double (phi i)) with (2*(phi i))%Z.
rewrite IHn; ring.
apply (nshiftr_0_firstl n); auto; try omega.
Qed.
(** We now prove that this [p2ibis] is related to [phi_inv_positive] *)
Lemma phi_inv_positive_p2ibis : forall n p, (n<=size)%nat ->
EqShiftL (size-n) (phi_inv_positive p) (snd (p2ibis n p)).
Proof.
induction n.
intros.
apply EqShiftL_size; auto.
intros.
simpl p2ibis; destruct p; [ | | red; auto];
specialize IHn with p;
destruct (p2ibis n p); simpl @snd in *; simpl phi_inv_positive;
rewrite ?EqShiftL_twice_plus_one, ?EqShiftL_twice;
replace (S (size - S n))%nat with (size - n)%nat by omega;
apply IHn; omega.
Qed.
(** This gives the expected result about [phi o phi_inv], at least
for the positive case. *)
Lemma phi_phi_inv_positive : forall p,
phi (phi_inv_positive p) = (Zpos p) mod (2^(Z.of_nat size)).
Proof.
intros.
replace (phi_inv_positive p) with (snd (p2ibis size p)).
rewrite (p2ibis_spec size p) by auto.
rewrite Z.add_comm, Z_mod_plus.
symmetry; apply Zmod_small.
apply phi_bounded.
auto with zarith.
symmetry.
rewrite <- EqShiftL_zero.
apply (phi_inv_positive_p2ibis size p); auto.
Qed.
(** Moreover, [p2ibis] is also related with [p2i] and hence with
[positive_to_int31]. *)
Lemma double_twice_firstl : forall x, firstl x = D0 ->
(Twon*x = twice x)%int31.
Proof.
intros.
unfold mul31.
rewrite <- Z.double_spec, <- phi_twice_firstl, phi_inv_phi; auto.
Qed.
Lemma double_twice_plus_one_firstl : forall x, firstl x = D0 ->
(Twon*x+In = twice_plus_one x)%int31.
Proof.
intros.
rewrite double_twice_firstl; auto.
unfold add31.
rewrite phi_twice_firstl, <- Z.succ_double_spec,
<- phi_twice_plus_one_firstl, phi_inv_phi; auto.
Qed.
Lemma p2i_p2ibis : forall n p, (n<=size)%nat ->
p2i n p = p2ibis n p.
Proof.
induction n; simpl; auto; intros.
destruct p; auto; specialize IHn with p;
generalize (p2ibis_bounded n p);
rewrite IHn; try omega; destruct (p2ibis n p); simpl; intros;
f_equal; auto.
apply double_twice_plus_one_firstl.
apply (nshiftr_0_firstl n); auto; omega.
apply double_twice_firstl.
apply (nshiftr_0_firstl n); auto; omega.
Qed.
Lemma positive_to_int31_phi_inv_positive : forall p,
snd (positive_to_int31 p) = phi_inv_positive p.
Proof.
intros; unfold positive_to_int31.
rewrite p2i_p2ibis; auto.
symmetry.
rewrite <- EqShiftL_zero.
apply (phi_inv_positive_p2ibis size); auto.
Qed.
Lemma positive_to_int31_spec : forall p,
Zpos p = (Z.of_N (fst (positive_to_int31 p)))*2^(Z.of_nat size) +
phi (snd (positive_to_int31 p)).
Proof.
unfold positive_to_int31.
intros; rewrite p2i_p2ibis; auto.
apply p2ibis_spec; auto.
Qed.
(** Thanks to the result about [phi o phi_inv_positive], we can
now establish easily the most general results about
[phi o twice] and so one. *)
Lemma phi_twice : forall x,
phi (twice x) = (Z.double (phi x)) mod 2^(Z.of_nat size).
Proof.
intros.
pattern x at 1; rewrite <- (phi_inv_phi x).
rewrite <- phi_inv_double.
assert (0 <= Z.double (phi x)).
rewrite Z.double_spec; generalize (phi_bounded x); omega.
destruct (Z.double (phi x)).
simpl; auto.
apply phi_phi_inv_positive.
compute in H; elim H; auto.
Qed.
Lemma phi_twice_plus_one : forall x,
phi (twice_plus_one x) = (Z.succ_double (phi x)) mod 2^(Z.of_nat size).
Proof.
intros.
pattern x at 1; rewrite <- (phi_inv_phi x).
rewrite <- phi_inv_double_plus_one.
assert (0 <= Z.succ_double (phi x)).
rewrite Z.succ_double_spec; generalize (phi_bounded x); omega.
destruct (Z.succ_double (phi x)).
simpl; auto.
apply phi_phi_inv_positive.
compute in H; elim H; auto.
Qed.
Lemma phi_incr : forall x,
phi (incr x) = (Z.succ (phi x)) mod 2^(Z.of_nat size).
Proof.
intros.
pattern x at 1; rewrite <- (phi_inv_phi x).
rewrite <- phi_inv_incr.
assert (0 <= Z.succ (phi x)).
change (Z.succ (phi x)) with ((phi x)+1)%Z;
generalize (phi_bounded x); omega.
destruct (Z.succ (phi x)).
simpl; auto.
apply phi_phi_inv_positive.
compute in H; elim H; auto.
Qed.
(** With the previous results, we can deal with [phi o phi_inv] even
in the negative case *)
Lemma phi_phi_inv_negative :
forall p, phi (incr (complement_negative p)) = (Zneg p) mod 2^(Z.of_nat size).
Proof.
induction p.
simpl complement_negative.
rewrite phi_incr in IHp.
rewrite incr_twice, phi_twice_plus_one.
remember (phi (complement_negative p)) as q.
rewrite Z.succ_double_spec.
replace (2*q+1) with (2*(Z.succ q)-1) by omega.
rewrite <- Zminus_mod_idemp_l, <- Zmult_mod_idemp_r, IHp.
rewrite Zmult_mod_idemp_r, Zminus_mod_idemp_l; auto with zarith.
simpl complement_negative.
rewrite incr_twice_plus_one, phi_twice.
remember (phi (incr (complement_negative p))) as q.
rewrite Z.double_spec, IHp, Zmult_mod_idemp_r; auto with zarith.
simpl; auto.
Qed.
Lemma phi_phi_inv :
forall z, phi (phi_inv z) = z mod 2 ^ (Z.of_nat size).
Proof.
destruct z.
simpl; auto.
apply phi_phi_inv_positive.
apply phi_phi_inv_negative.
Qed.
End Basics.
Instance int31_ops : ZnZ.Ops int31 :=
{
digits := 31%positive; (* number of digits *)
zdigits := 31; (* number of digits *)
to_Z := phi; (* conversion to Z *)
of_pos := positive_to_int31; (* positive -> N*int31 : p => N,i
where p = N*2^31+phi i *)
head0 := head031; (* number of head 0 *)
tail0 := tail031; (* number of tail 0 *)
zero := 0;
one := 1;
minus_one := Tn; (* 2^31 - 1 *)
compare := compare31;
eq0 := fun i => match i ?= 0 with Eq => true | _ => false end;
opp_c := fun i => 0 -c i;
opp := opp31;
opp_carry := fun i => 0-i-1;
succ_c := fun i => i +c 1;
add_c := add31c;
add_carry_c := add31carryc;
succ := fun i => i + 1;
add := add31;
add_carry := fun i j => i + j + 1;
pred_c := fun i => i -c 1;
sub_c := sub31c;
sub_carry_c := sub31carryc;
pred := fun i => i - 1;
sub := sub31;
sub_carry := fun i j => i - j - 1;
mul_c := mul31c;
mul := mul31;
square_c := fun x => x *c x;
div21 := div3121;
div_gt := div31; (* this is supposed to be the special case of
division a/b where a > b *)
div := div31;
modulo_gt := fun i j => let (_,r) := i/j in r;
modulo := fun i j => let (_,r) := i/j in r;
gcd_gt := gcd31;
gcd := gcd31;
add_mul_div := addmuldiv31;
pos_mod := (* modulo 2^p *)
fun p i =>
match p ?= 31 with
| Lt => addmuldiv31 p 0 (addmuldiv31 (31-p) i 0)
| _ => i
end;
is_even :=
fun i => let (_,r) := i/2 in
match r ?= 0 with Eq => true | _ => false end;
sqrt2 := sqrt312;
sqrt := sqrt31;
lor := lor31;
land := land31;
lxor := lxor31
}.
Section Int31_Specs.
Local Open Scope Z_scope.
Notation "[| x |]" := (phi x) (at level 0, x at level 99).
Local Notation wB := (2 ^ (Z.of_nat size)).
Lemma wB_pos : wB > 0.
Proof.
auto with zarith.
Qed.
Notation "[+| c |]" :=
(interp_carry 1 wB phi c) (at level 0, x at level 99).
Notation "[-| c |]" :=
(interp_carry (-1) wB phi c) (at level 0, x at level 99).
Notation "[|| x ||]" :=
(zn2z_to_Z wB phi x) (at level 0, x at level 99).
Lemma spec_zdigits : [| 31 |] = 31.
Proof.
reflexivity.
Qed.
Lemma spec_more_than_1_digit: 1 < 31.
Proof.
auto with zarith.
Qed.
Lemma spec_0 : [| 0 |] = 0.
Proof.
reflexivity.
Qed.
Lemma spec_1 : [| 1 |] = 1.
Proof.
reflexivity.
Qed.
Lemma spec_m1 : [| Tn |] = wB - 1.
Proof.
reflexivity.
Qed.
Lemma spec_compare : forall x y,
(x ?= y)%int31 = ([|x|] ?= [|y|]).
Proof. reflexivity. Qed.
(** Addition *)
Lemma spec_add_c : forall x y, [+|add31c x y|] = [|x|] + [|y|].
Proof.
intros; unfold add31c, add31, interp_carry; rewrite phi_phi_inv.
generalize (phi_bounded x)(phi_bounded y); intros.
set (X:=[|x|]) in *; set (Y:=[|y|]) in *; clearbody X Y.
assert ((X+Y) mod wB ?= X+Y <> Eq -> [+|C1 (phi_inv (X+Y))|] = X+Y).
unfold interp_carry; rewrite phi_phi_inv, Z.compare_eq_iff; intros.
destruct (Z_lt_le_dec (X+Y) wB).
contradict H1; auto using Zmod_small with zarith.
rewrite <- (Z_mod_plus_full (X+Y) (-1) wB).
rewrite Zmod_small; romega.
generalize (Z.compare_eq ((X+Y) mod wB) (X+Y)); intros Heq.
destruct Z.compare; intros;
[ rewrite phi_phi_inv; auto | now apply H1 | now apply H1].
Qed.
Lemma spec_succ_c : forall x, [+|add31c x 1|] = [|x|] + 1.
Proof.
intros; apply spec_add_c.
Qed.
Lemma spec_add_carry_c : forall x y, [+|add31carryc x y|] = [|x|] + [|y|] + 1.
Proof.
intros.
unfold add31carryc, interp_carry; rewrite phi_phi_inv.
generalize (phi_bounded x)(phi_bounded y); intros.
set (X:=[|x|]) in *; set (Y:=[|y|]) in *; clearbody X Y.
assert ((X+Y+1) mod wB ?= X+Y+1 <> Eq -> [+|C1 (phi_inv (X+Y+1))|] = X+Y+1).
unfold interp_carry; rewrite phi_phi_inv, Z.compare_eq_iff; intros.
destruct (Z_lt_le_dec (X+Y+1) wB).
contradict H1; auto using Zmod_small with zarith.
rewrite <- (Z_mod_plus_full (X+Y+1) (-1) wB).
rewrite Zmod_small; romega.
generalize (Z.compare_eq ((X+Y+1) mod wB) (X+Y+1)); intros Heq.
destruct Z.compare; intros;
[ rewrite phi_phi_inv; auto | now apply H1 | now apply H1].
Qed.
Lemma spec_add : forall x y, [|x+y|] = ([|x|] + [|y|]) mod wB.
Proof.
intros; apply phi_phi_inv.
Qed.
Lemma spec_add_carry :
forall x y, [|x+y+1|] = ([|x|] + [|y|] + 1) mod wB.
Proof.
unfold add31; intros.
repeat rewrite phi_phi_inv.
apply Zplus_mod_idemp_l.
Qed.
Lemma spec_succ : forall x, [|x+1|] = ([|x|] + 1) mod wB.
Proof.
intros; rewrite <- spec_1; apply spec_add.
Qed.
(** Substraction *)
Lemma spec_sub_c : forall x y, [-|sub31c x y|] = [|x|] - [|y|].
Proof.
unfold sub31c, sub31, interp_carry; intros.
rewrite phi_phi_inv.
generalize (phi_bounded x)(phi_bounded y); intros.
set (X:=[|x|]) in *; set (Y:=[|y|]) in *; clearbody X Y.
assert ((X-Y) mod wB ?= X-Y <> Eq -> [-|C1 (phi_inv (X-Y))|] = X-Y).
unfold interp_carry; rewrite phi_phi_inv, Z.compare_eq_iff; intros.
destruct (Z_lt_le_dec (X-Y) 0).
rewrite <- (Z_mod_plus_full (X-Y) 1 wB).
rewrite Zmod_small; romega.
contradict H1; apply Zmod_small; romega.
generalize (Z.compare_eq ((X-Y) mod wB) (X-Y)); intros Heq.
destruct Z.compare; intros;
[ rewrite phi_phi_inv; auto | now apply H1 | now apply H1].
Qed.
Lemma spec_sub_carry_c : forall x y, [-|sub31carryc x y|] = [|x|] - [|y|] - 1.
Proof.
unfold sub31carryc, sub31, interp_carry; intros.
rewrite phi_phi_inv.
generalize (phi_bounded x)(phi_bounded y); intros.
set (X:=[|x|]) in *; set (Y:=[|y|]) in *; clearbody X Y.
assert ((X-Y-1) mod wB ?= X-Y-1 <> Eq -> [-|C1 (phi_inv (X-Y-1))|] = X-Y-1).
unfold interp_carry; rewrite phi_phi_inv, Z.compare_eq_iff; intros.
destruct (Z_lt_le_dec (X-Y-1) 0).
rewrite <- (Z_mod_plus_full (X-Y-1) 1 wB).
rewrite Zmod_small; romega.
contradict H1; apply Zmod_small; romega.
generalize (Z.compare_eq ((X-Y-1) mod wB) (X-Y-1)); intros Heq.
destruct Z.compare; intros;
[ rewrite phi_phi_inv; auto | now apply H1 | now apply H1].
Qed.
Lemma spec_sub : forall x y, [|x-y|] = ([|x|] - [|y|]) mod wB.
Proof.
intros; apply phi_phi_inv.
Qed.
Lemma spec_sub_carry :
forall x y, [|x-y-1|] = ([|x|] - [|y|] - 1) mod wB.
Proof.
unfold sub31; intros.
repeat rewrite phi_phi_inv.
apply Zminus_mod_idemp_l.
Qed.
Lemma spec_opp_c : forall x, [-|sub31c 0 x|] = -[|x|].
Proof.
intros; apply spec_sub_c.
Qed.
Lemma spec_opp : forall x, [|0 - x|] = (-[|x|]) mod wB.
Proof.
intros; apply phi_phi_inv.
Qed.
Lemma spec_opp_carry : forall x, [|0 - x - 1|] = wB - [|x|] - 1.
Proof.
unfold sub31; intros.
repeat rewrite phi_phi_inv.
change [|1|] with 1; change [|0|] with 0.
rewrite <- (Z_mod_plus_full (0-[|x|]) 1 wB).
rewrite Zminus_mod_idemp_l.
rewrite Zmod_small; generalize (phi_bounded x); romega.
Qed.
Lemma spec_pred_c : forall x, [-|sub31c x 1|] = [|x|] - 1.
Proof.
intros; apply spec_sub_c.
Qed.
Lemma spec_pred : forall x, [|x-1|] = ([|x|] - 1) mod wB.
Proof.
intros; apply spec_sub.
Qed.
(** Multiplication *)
Lemma phi2_phi_inv2 : forall x, [||phi_inv2 x||] = x mod (wB^2).
Proof.
assert (forall z, (z / wB) mod wB * wB + z mod wB = z mod wB ^ 2).
intros.
assert ((z/wB) mod wB = z/wB - (z/wB/wB)*wB).
rewrite (Z_div_mod_eq (z/wB) wB wB_pos) at 2; ring.
assert (z mod wB = z - (z/wB)*wB).
rewrite (Z_div_mod_eq z wB wB_pos) at 2; ring.
rewrite H.
rewrite H0 at 1.
ring_simplify.
rewrite Zdiv_Zdiv; auto with zarith.
rewrite (Z_div_mod_eq z (wB*wB)) at 2; auto with zarith.
change (wB*wB) with (wB^2); ring.
unfold phi_inv2.
destruct x; unfold zn2z_to_Z; rewrite ?phi_phi_inv;
change base with wB; auto.
Qed.
Lemma spec_mul_c : forall x y, [|| mul31c x y ||] = [|x|] * [|y|].
Proof.
unfold mul31c; intros.
rewrite phi2_phi_inv2.
apply Zmod_small.
generalize (phi_bounded x)(phi_bounded y); intros.
change (wB^2) with (wB * wB).
auto using Z.mul_lt_mono_nonneg with zarith.
Qed.
Lemma spec_mul : forall x y, [|x*y|] = ([|x|] * [|y|]) mod wB.
Proof.
intros; apply phi_phi_inv.
Qed.
Lemma spec_square_c : forall x, [|| mul31c x x ||] = [|x|] * [|x|].
Proof.
intros; apply spec_mul_c.
Qed.
(** Division *)
Lemma spec_div21 : forall a1 a2 b,
wB/2 <= [|b|] ->
[|a1|] < [|b|] ->
let (q,r) := div3121 a1 a2 b in
[|a1|] *wB+ [|a2|] = [|q|] * [|b|] + [|r|] /\
0 <= [|r|] < [|b|].
Proof.
unfold div3121; intros.
generalize (phi_bounded a1)(phi_bounded a2)(phi_bounded b); intros.
assert ([|b|]>0) by (auto with zarith).
generalize (Z_div_mod (phi2 a1 a2) [|b|] H4) (Z_div_pos (phi2 a1 a2) [|b|] H4).
unfold Z.div; destruct (Z.div_eucl (phi2 a1 a2) [|b|]).
rewrite ?phi_phi_inv.
destruct 1; intros.
unfold phi2 in *.
change base with wB; change base with wB in H5.
change (Z.pow_pos 2 31) with wB; change (Z.pow_pos 2 31) with wB in H.
rewrite H5, Z.mul_comm.
replace (z0 mod wB) with z0 by (symmetry; apply Zmod_small; omega).
replace (z mod wB) with z; auto with zarith.
symmetry; apply Zmod_small.
split.
apply H7; change base with wB; auto with zarith.
apply Z.mul_lt_mono_pos_r with [|b|]; [omega| ].
rewrite Z.mul_comm.
apply Z.le_lt_trans with ([|b|]*z+z0); [omega| ].
rewrite <- H5.
apply Z.le_lt_trans with ([|a1|]*wB+(wB-1)); [omega | ].
replace ([|a1|]*wB+(wB-1)) with (wB*([|a1|]+1)-1) by ring.
assert (wB*([|a1|]+1) <= wB*[|b|]); try omega.
apply Z.mul_le_mono_nonneg; omega.
Qed.
Lemma spec_div : forall a b, 0 < [|b|] ->
let (q,r) := div31 a b in
[|a|] = [|q|] * [|b|] + [|r|] /\
0 <= [|r|] < [|b|].
Proof.
unfold div31; intros.
assert ([|b|]>0) by (auto with zarith).
generalize (Z_div_mod [|a|] [|b|] H0) (Z_div_pos [|a|] [|b|] H0).
unfold Z.div; destruct (Z.div_eucl [|a|] [|b|]).
rewrite ?phi_phi_inv.
destruct 1; intros.
rewrite H1, Z.mul_comm.
generalize (phi_bounded a)(phi_bounded b); intros.
replace (z0 mod wB) with z0 by (symmetry; apply Zmod_small; omega).
replace (z mod wB) with z; auto with zarith.
symmetry; apply Zmod_small.
split; auto with zarith.
apply Z.le_lt_trans with [|a|]; auto with zarith.
rewrite H1.
apply Z.le_trans with ([|b|]*z); try omega.
rewrite <- (Z.mul_1_l z) at 1.
apply Z.mul_le_mono_nonneg; auto with zarith.
Qed.
Lemma spec_mod : forall a b, 0 < [|b|] ->
[|let (_,r) := (a/b)%int31 in r|] = [|a|] mod [|b|].
Proof.
unfold div31; intros.
assert ([|b|]>0) by (auto with zarith).
unfold Z.modulo.
generalize (Z_div_mod [|a|] [|b|] H0).
destruct (Z.div_eucl [|a|] [|b|]).
rewrite ?phi_phi_inv.
destruct 1; intros.
generalize (phi_bounded b); intros.
apply Zmod_small; omega.
Qed.
Lemma phi_gcd : forall i j,
[|gcd31 i j|] = Zgcdn (2*size) [|j|] [|i|].
Proof.
unfold gcd31.
induction (2*size)%nat; intros.
reflexivity.
simpl euler.
unfold compare31.
change [|On|] with 0.
generalize (phi_bounded j)(phi_bounded i); intros.
case_eq [|j|]; intros.
simpl; intros.
generalize (Zabs_spec [|i|]); omega.
simpl. rewrite IHn, H1; f_equal.
rewrite spec_mod, H1; auto.
rewrite H1; compute; auto.
rewrite H1 in H; destruct H as [H _]; compute in H; elim H; auto.
Qed.
Lemma spec_gcd : forall a b, Zis_gcd [|a|] [|b|] [|gcd31 a b|].
Proof.
intros.
rewrite phi_gcd.
apply Zis_gcd_sym.
apply Zgcdn_is_gcd.
unfold Zgcd_bound.
generalize (phi_bounded b).
destruct [|b|].
unfold size; auto with zarith.
intros (_,H).
cut (Pos.size_nat p <= size)%nat; [ omega | rewrite <- Zpower2_Psize; auto].
intros (H,_); compute in H; elim H; auto.
Qed.
Lemma iter_int31_iter_nat : forall A f i a,
iter_int31 i A f a = iter_nat (Z.abs_nat [|i|]) A f a.
Proof.
intros.
unfold iter_int31.
rewrite <- recrbis_equiv; auto; unfold recrbis.
rewrite <- phibis_aux_equiv.
revert i a; induction size.
simpl; auto.
simpl; intros.
case_eq (firstr i); intros H; rewrite 2 IHn;
unfold phibis_aux; simpl; rewrite ?H; fold (phibis_aux n (shiftr i));
generalize (phibis_aux_pos n (shiftr i)); intros;
set (z := phibis_aux n (shiftr i)) in *; clearbody z;
rewrite <- nat_rect_plus.
f_equal.
rewrite Z.double_spec, <- Z.add_diag.
symmetry; apply Zabs2Nat.inj_add; auto with zarith.
change (iter_nat (S (Z.abs_nat z) + (Z.abs_nat z))%nat A f a =
iter_nat (Z.abs_nat (Z.succ_double z)) A f a); f_equal.
rewrite Z.succ_double_spec, <- Z.add_diag.
rewrite Zabs2Nat.inj_add; auto with zarith.
rewrite Zabs2Nat.inj_add; auto with zarith.
change (Z.abs_nat 1) with 1%nat; omega.
Qed.
Fixpoint addmuldiv31_alt n i j :=
match n with
| O => i
| S n => addmuldiv31_alt n (sneakl (firstl j) i) (shiftl j)
end.
Lemma addmuldiv31_equiv : forall p x y,
addmuldiv31 p x y = addmuldiv31_alt (Z.abs_nat [|p|]) x y.
Proof.
intros.
unfold addmuldiv31.
rewrite iter_int31_iter_nat.
set (n:=Z.abs_nat [|p|]); clearbody n; clear p.
revert x y; induction n.
simpl; auto.
intros.
simpl addmuldiv31_alt.
replace (S n) with (n+1)%nat by (rewrite plus_comm; auto).
rewrite nat_rect_plus; simpl; auto.
Qed.
Lemma spec_add_mul_div : forall x y p, [|p|] <= Zpos 31 ->
[| addmuldiv31 p x y |] =
([|x|] * (2 ^ [|p|]) + [|y|] / (2 ^ ((Zpos 31) - [|p|]))) mod wB.
Proof.
intros.
rewrite addmuldiv31_equiv.
assert ([|p|] = Z.of_nat (Z.abs_nat [|p|])).
rewrite Zabs2Nat.id_abs; symmetry; apply Z.abs_eq.
destruct (phi_bounded p); auto.
rewrite H0; rewrite H0 in H; clear H0; rewrite Zabs2Nat.id.
set (n := Z.abs_nat [|p|]) in *; clearbody n.
assert (n <= 31)%nat.
rewrite Nat2Z.inj_le; auto with zarith.
clear p H; revert x y.
induction n.
simpl Z.of_nat; intros.
rewrite Z.mul_1_r.
replace ([|y|] / 2^(31-0)) with 0.
rewrite Z.add_0_r.
symmetry; apply Zmod_small; apply phi_bounded.
symmetry; apply Zdiv_small; apply phi_bounded.
simpl addmuldiv31_alt; intros.
rewrite IHn; [ | omega ].
case_eq (firstl y); intros.
rewrite phi_twice, Z.double_spec.
rewrite phi_twice_firstl; auto.
change (Z.double [|y|]) with (2*[|y|]).
rewrite Nat2Z.inj_succ, Z.pow_succ_r; auto with zarith.
rewrite Zplus_mod; rewrite Zmult_mod_idemp_l; rewrite <- Zplus_mod.
f_equal.
f_equal.
ring.
replace (31-Z.of_nat n) with (Z.succ(31-Z.succ(Z.of_nat n))) by ring.
rewrite Z.pow_succ_r, <- Zdiv_Zdiv; auto with zarith.
rewrite Z.mul_comm, Z_div_mult; auto with zarith.
rewrite phi_twice_plus_one, Z.succ_double_spec.
rewrite phi_twice; auto.
change (Z.double [|y|]) with (2*[|y|]).
rewrite Nat2Z.inj_succ, Z.pow_succ_r; auto with zarith.
rewrite Zplus_mod; rewrite Zmult_mod_idemp_l; rewrite <- Zplus_mod.
rewrite Z.mul_add_distr_r, Z.mul_1_l, <- Z.add_assoc.
f_equal.
f_equal.
ring.
assert ((2*[|y|]) mod wB = 2*[|y|] - wB).
clear - H. symmetry. apply Zmod_unique with 1; [ | ring ].
generalize (phi_lowerbound _ H) (phi_bounded y).
set (wB' := 2^Z.of_nat (pred size)).
replace wB with (2*wB'); [ omega | ].
unfold wB'. rewrite <- Z.pow_succ_r, <- Nat2Z.inj_succ by (auto with zarith).
f_equal.
rewrite H1.
replace wB with (2^(Z.of_nat n)*2^(31-Z.of_nat n)) by
(rewrite <- Zpower_exp; auto with zarith; f_equal; unfold size; ring).
unfold Z.sub; rewrite <- Z.mul_opp_l.
rewrite Z_div_plus; auto with zarith.
ring_simplify.
replace (31+-Z.of_nat n) with (Z.succ(31-Z.succ(Z.of_nat n))) by ring.
rewrite Z.pow_succ_r, <- Zdiv_Zdiv; auto with zarith.
rewrite Z.mul_comm, Z_div_mult; auto with zarith.
Qed.
Lemma spec_pos_mod : forall w p,
[|ZnZ.pos_mod p w|] = [|w|] mod (2 ^ [|p|]).
Proof.
unfold int31_ops, ZnZ.pos_mod, compare31.
change [|31|] with 31%Z.
assert (forall w p, 31<=p -> [|w|] = [|w|] mod 2^p).
intros.
generalize (phi_bounded w).
symmetry; apply Zmod_small.
split; auto with zarith.
apply Z.lt_le_trans with wB; auto with zarith.
apply Zpower_le_monotone; auto with zarith.
intros.
case_eq ([|p|] ?= 31); intros;
[ apply H; rewrite (Z.compare_eq _ _ H0); auto with zarith | |
apply H; change ([|p|]>31)%Z in H0; auto with zarith ].
change ([|p|]<31) in H0.
rewrite spec_add_mul_div by auto with zarith.
change [|0|] with 0%Z; rewrite Z.mul_0_l, Z.add_0_l.
generalize (phi_bounded p)(phi_bounded w); intros.
assert (31-[|p|]<wB).
apply Z.le_lt_trans with 31%Z; auto with zarith.
compute; auto.
assert ([|31-p|]=31-[|p|]).
unfold sub31; rewrite phi_phi_inv.
change [|31|] with 31%Z.
apply Zmod_small; auto with zarith.
rewrite spec_add_mul_div by (rewrite H4; auto with zarith).
change [|0|] with 0%Z; rewrite Zdiv_0_l, Z.add_0_r.
rewrite H4.
apply shift_unshift_mod_2; auto with zarith.
Qed.
(** Shift operations *)
Lemma spec_head00: forall x, [|x|] = 0 -> [|head031 x|] = Zpos 31.
Proof.
intros.
generalize (phi_inv_phi x).
rewrite H; simpl phi_inv.
intros H'; rewrite <- H'.
simpl; auto.
Qed.
Fixpoint head031_alt n x :=
match n with
| O => 0%nat
| S n => match firstl x with
| D0 => S (head031_alt n (shiftl x))
| D1 => 0%nat
end
end.
Lemma head031_equiv :
forall x, [|head031 x|] = Z.of_nat (head031_alt size x).
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H).
simpl; auto.
unfold head031, recl.
change On with (phi_inv (Z.of_nat (31-size))).
replace (head031_alt size x) with
(head031_alt size x + (31 - size))%nat by auto.
assert (size <= 31)%nat by auto with arith.
revert x H; induction size; intros.
simpl; auto.
unfold recl_aux; fold recl_aux.
unfold head031_alt; fold head031_alt.
rewrite H.
assert ([|phi_inv (Z.of_nat (31-S n))|] = Z.of_nat (31 - S n)).
rewrite phi_phi_inv.
apply Zmod_small.
split.
change 0 with (Z.of_nat O); apply inj_le; omega.
apply Z.le_lt_trans with (Z.of_nat 31).
apply inj_le; omega.
compute; auto.
case_eq (firstl x); intros; auto.
rewrite plus_Sn_m, plus_n_Sm.
replace (S (31 - S n)) with (31 - n)%nat by omega.
rewrite <- IHn; [ | omega | ].
f_equal; f_equal.
unfold add31.
rewrite H1.
f_equal.
change [|In|] with 1.
replace (31-n)%nat with (S (31 - S n))%nat by omega.
rewrite Nat2Z.inj_succ; ring.
clear - H H2.
rewrite (sneakr_shiftl x) in H.
rewrite H2 in H.
case_eq (iszero (shiftl x)); intros; auto.
rewrite (iszero_eq0 _ H0) in H; discriminate.
Qed.
Lemma phi_nz : forall x, 0 < [|x|] <-> x <> 0%int31.
Proof.
split; intros.
red; intro; subst x; discriminate.
assert ([|x|]<>0%Z).
contradict H.
rewrite <- (phi_inv_phi x); rewrite H; auto.
generalize (phi_bounded x); auto with zarith.
Qed.
Lemma spec_head0 : forall x, 0 < [|x|] ->
wB/ 2 <= 2 ^ ([|head031 x|]) * [|x|] < wB.
Proof.
intros.
rewrite head031_equiv.
assert (nshiftl x size = 0%int31).
apply nshiftl_size.
revert x H H0.
unfold size at 2 5.
induction size.
simpl Z.of_nat.
intros.
compute in H0; rewrite H0 in H; discriminate.
intros.
simpl head031_alt.
case_eq (firstl x); intros.
rewrite (Nat2Z.inj_succ (head031_alt n (shiftl x))), Z.pow_succ_r; auto with zarith.
rewrite <- Z.mul_assoc, Z.mul_comm, <- Z.mul_assoc, <-(Z.mul_comm 2).
rewrite <- Z.double_spec, <- (phi_twice_firstl _ H1).
apply IHn.
rewrite phi_nz; rewrite phi_nz in H; contradict H.
change twice with shiftl in H.
rewrite (sneakr_shiftl x), H1, H; auto.
rewrite <- nshiftl_S_tail; auto.
change (2^(Z.of_nat 0)) with 1; rewrite Z.mul_1_l.
generalize (phi_bounded x); unfold size; split; auto with zarith.
change (2^(Z.of_nat 31)/2) with (2^(Z.of_nat (pred size))).
apply phi_lowerbound; auto.
Qed.
Lemma spec_tail00: forall x, [|x|] = 0 -> [|tail031 x|] = Zpos 31.
Proof.
intros.
generalize (phi_inv_phi x).
rewrite H; simpl phi_inv.
intros H'; rewrite <- H'.
simpl; auto.
Qed.
Fixpoint tail031_alt n x :=
match n with
| O => 0%nat
| S n => match firstr x with
| D0 => S (tail031_alt n (shiftr x))
| D1 => 0%nat
end
end.
Lemma tail031_equiv :
forall x, [|tail031 x|] = Z.of_nat (tail031_alt size x).
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H).
simpl; auto.
unfold tail031, recr.
change On with (phi_inv (Z.of_nat (31-size))).
replace (tail031_alt size x) with
(tail031_alt size x + (31 - size))%nat by auto.
assert (size <= 31)%nat by auto with arith.
revert x H; induction size; intros.
simpl; auto.
unfold recr_aux; fold recr_aux.
unfold tail031_alt; fold tail031_alt.
rewrite H.
assert ([|phi_inv (Z.of_nat (31-S n))|] = Z.of_nat (31 - S n)).
rewrite phi_phi_inv.
apply Zmod_small.
split.
change 0 with (Z.of_nat O); apply inj_le; omega.
apply Z.le_lt_trans with (Z.of_nat 31).
apply inj_le; omega.
compute; auto.
case_eq (firstr x); intros; auto.
rewrite plus_Sn_m, plus_n_Sm.
replace (S (31 - S n)) with (31 - n)%nat by omega.
rewrite <- IHn; [ | omega | ].
f_equal; f_equal.
unfold add31.
rewrite H1.
f_equal.
change [|In|] with 1.
replace (31-n)%nat with (S (31 - S n))%nat by omega.
rewrite Nat2Z.inj_succ; ring.
clear - H H2.
rewrite (sneakl_shiftr x) in H.
rewrite H2 in H.
case_eq (iszero (shiftr x)); intros; auto.
rewrite (iszero_eq0 _ H0) in H; discriminate.
Qed.
Lemma spec_tail0 : forall x, 0 < [|x|] ->
exists y, 0 <= y /\ [|x|] = (2 * y + 1) * (2 ^ [|tail031 x|]).
Proof.
intros.
rewrite tail031_equiv.
assert (nshiftr x size = 0%int31).
apply nshiftr_size.
revert x H H0.
induction size.
simpl Z.of_nat.
intros.
compute in H0; rewrite H0 in H; discriminate.
intros.
simpl tail031_alt.
case_eq (firstr x); intros.
rewrite (Nat2Z.inj_succ (tail031_alt n (shiftr x))), Z.pow_succ_r; auto with zarith.
destruct (IHn (shiftr x)) as (y & Hy1 & Hy2).
rewrite phi_nz; rewrite phi_nz in H; contradict H.
rewrite (sneakl_shiftr x), H1, H; auto.
rewrite <- nshiftr_S_tail; auto.
exists y; split; auto.
rewrite phi_eqn1; auto.
rewrite Z.double_spec, Hy2; ring.
exists [|shiftr x|].
split.
generalize (phi_bounded (shiftr x)); auto with zarith.
rewrite phi_eqn2; auto.
rewrite Z.succ_double_spec; simpl; ring.
Qed.
(* Sqrt *)
(* Direct transcription of an old proof
of a fortran program in boyer-moore *)
Lemma quotient_by_2 a: a - 1 <= (a/2) + (a/2).
Proof.
case (Z_mod_lt a 2); auto with zarith.
intros H1; rewrite Zmod_eq_full; auto with zarith.
Qed.
Lemma sqrt_main_trick j k: 0 <= j -> 0 <= k ->
(j * k) + j <= ((j + k)/2 + 1) ^ 2.
Proof.
intros Hj; generalize Hj k; pattern j; apply natlike_ind;
auto; clear k j Hj.
intros _ k Hk; repeat rewrite Z.add_0_l.
apply Z.mul_nonneg_nonneg; generalize (Z_div_pos k 2); auto with zarith.
intros j Hj Hrec _ k Hk; pattern k; apply natlike_ind; auto; clear k Hk.
rewrite Z.mul_0_r, Z.add_0_r, Z.add_0_l.
generalize (sqr_pos (Z.succ j / 2)) (quotient_by_2 (Z.succ j));
unfold Z.succ.
rewrite Z.pow_2_r, Z.mul_add_distr_r; repeat rewrite Z.mul_add_distr_l.
auto with zarith.
intros k Hk _.
replace ((Z.succ j + Z.succ k) / 2) with ((j + k)/2 + 1).
generalize (Hrec Hj k Hk) (quotient_by_2 (j + k)).
unfold Z.succ; repeat rewrite Z.pow_2_r;
repeat rewrite Z.mul_add_distr_r; repeat rewrite Z.mul_add_distr_l.
repeat rewrite Z.mul_1_l; repeat rewrite Z.mul_1_r.
auto with zarith.
rewrite Z.add_comm, <- Z_div_plus_full_l; auto with zarith.
apply f_equal2 with (f := Z.div); auto with zarith.
Qed.
Lemma sqrt_main i j: 0 <= i -> 0 < j -> i < ((j + (i/j))/2 + 1) ^ 2.
Proof.
intros Hi Hj.
assert (Hij: 0 <= i/j) by (apply Z_div_pos; auto with zarith).
apply Z.lt_le_trans with (2 := sqrt_main_trick _ _ (Z.lt_le_incl _ _ Hj) Hij).
pattern i at 1; rewrite (Z_div_mod_eq i j); case (Z_mod_lt i j); auto with zarith.
Qed.
Lemma sqrt_init i: 1 < i -> i < (i/2 + 1) ^ 2.
Proof.
intros Hi.
assert (H1: 0 <= i - 2) by auto with zarith.
assert (H2: 1 <= (i / 2) ^ 2); auto with zarith.
replace i with (1* 2 + (i - 2)); auto with zarith.
rewrite Z.pow_2_r, Z_div_plus_full_l; auto with zarith.
generalize (sqr_pos ((i - 2)/ 2)) (Z_div_pos (i - 2) 2).
rewrite Z.mul_add_distr_r; repeat rewrite Z.mul_add_distr_l.
auto with zarith.
generalize (quotient_by_2 i).
rewrite Z.pow_2_r in H2 |- *;
repeat (rewrite Z.mul_add_distr_r ||
rewrite Z.mul_add_distr_l ||
rewrite Z.mul_1_l || rewrite Z.mul_1_r).
auto with zarith.
Qed.
Lemma sqrt_test_true i j: 0 <= i -> 0 < j -> i/j >= j -> j ^ 2 <= i.
Proof.
intros Hi Hj Hd; rewrite Z.pow_2_r.
apply Z.le_trans with (j * (i/j)); auto with zarith.
apply Z_mult_div_ge; auto with zarith.
Qed.
Lemma sqrt_test_false i j: 0 <= i -> 0 < j -> i/j < j -> (j + (i/j))/2 < j.
Proof.
intros Hi Hj H; case (Z.le_gt_cases j ((j + (i/j))/2)); auto.
intros H1; contradict H; apply Z.le_ngt.
assert (2 * j <= j + (i/j)); auto with zarith.
apply Z.le_trans with (2 * ((j + (i/j))/2)); auto with zarith.
apply Z_mult_div_ge; auto with zarith.
Qed.
Lemma sqrt31_step_def rec i j:
sqrt31_step rec i j =
match (fst (i/j) ?= j)%int31 with
Lt => rec i (fst ((j + fst(i/j))/2))%int31
| _ => j
end.
Proof.
unfold sqrt31_step; case div31; intros.
simpl; case compare31; auto.
Qed.
Lemma div31_phi i j: 0 < [|j|] -> [|fst (i/j)%int31|] = [|i|]/[|j|].
intros Hj; generalize (spec_div i j Hj).
case div31; intros q r; simpl @fst.
intros (H1,H2); apply Zdiv_unique with [|r|]; auto with zarith.
rewrite H1; ring.
Qed.
Lemma sqrt31_step_correct rec i j:
0 < [|i|] -> 0 < [|j|] -> [|i|] < ([|j|] + 1) ^ 2 ->
2 * [|j|] < wB ->
(forall j1 : int31,
0 < [|j1|] < [|j|] -> [|i|] < ([|j1|] + 1) ^ 2 ->
[|rec i j1|] ^ 2 <= [|i|] < ([|rec i j1|] + 1) ^ 2) ->
[|sqrt31_step rec i j|] ^ 2 <= [|i|] < ([|sqrt31_step rec i j|] + 1) ^ 2.
Proof.
assert (Hp2: 0 < [|2|]) by exact (eq_refl Lt).
intros Hi Hj Hij H31 Hrec; rewrite sqrt31_step_def.
rewrite spec_compare, div31_phi; auto.
case Z.compare_spec; auto; intros Hc;
try (split; auto; apply sqrt_test_true; auto with zarith; fail).
apply Hrec; repeat rewrite div31_phi; auto with zarith.
replace [|(j + fst (i / j)%int31)|] with ([|j|] + [|i|] / [|j|]).
split.
apply Z.le_succ_l in Hj. change (1 <= [|j|]) in Hj.
Z.le_elim Hj.
replace ([|j|] + [|i|]/[|j|]) with
(1 * 2 + (([|j|] - 2) + [|i|] / [|j|])); try ring.
rewrite Z_div_plus_full_l; auto with zarith.
assert (0 <= [|i|]/ [|j|]) by (apply Z_div_pos; auto with zarith).
assert (0 <= ([|j|] - 2 + [|i|] / [|j|]) / [|2|]) ; auto with zarith.
rewrite <- Hj, Zdiv_1_r.
replace (1 + [|i|])%Z with (1 * 2 + ([|i|] - 1))%Z; try ring.
rewrite Z_div_plus_full_l; auto with zarith.
assert (0 <= ([|i|] - 1) /2)%Z by (apply Z_div_pos; auto with zarith).
change ([|2|]) with 2%Z; auto with zarith.
apply sqrt_test_false; auto with zarith.
rewrite spec_add, div31_phi; auto.
symmetry; apply Zmod_small.
split; auto with zarith.
replace [|j + fst (i / j)%int31|] with ([|j|] + [|i|] / [|j|]).
apply sqrt_main; auto with zarith.
rewrite spec_add, div31_phi; auto.
symmetry; apply Zmod_small.
split; auto with zarith.
Qed.
Lemma iter31_sqrt_correct n rec i j: 0 < [|i|] -> 0 < [|j|] ->
[|i|] < ([|j|] + 1) ^ 2 -> 2 * [|j|] < 2 ^ (Z.of_nat size) ->
(forall j1, 0 < [|j1|] -> 2^(Z.of_nat n) + [|j1|] <= [|j|] ->
[|i|] < ([|j1|] + 1) ^ 2 -> 2 * [|j1|] < 2 ^ (Z.of_nat size) ->
[|rec i j1|] ^ 2 <= [|i|] < ([|rec i j1|] + 1) ^ 2) ->
[|iter31_sqrt n rec i j|] ^ 2 <= [|i|] < ([|iter31_sqrt n rec i j|] + 1) ^ 2.
Proof.
revert rec i j; elim n; unfold iter31_sqrt; fold iter31_sqrt; clear n.
intros rec i j Hi Hj Hij H31 Hrec; apply sqrt31_step_correct; auto with zarith.
intros; apply Hrec; auto with zarith.
rewrite Z.pow_0_r; auto with zarith.
intros n Hrec rec i j Hi Hj Hij H31 HHrec.
apply sqrt31_step_correct; auto.
intros j1 Hj1 Hjp1; apply Hrec; auto with zarith.
intros j2 Hj2 H2j2 Hjp2 Hj31; apply Hrec; auto with zarith.
intros j3 Hj3 Hpj3.
apply HHrec; auto.
rewrite Nat2Z.inj_succ, Z.pow_succ_r.
apply Z.le_trans with (2 ^Z.of_nat n + [|j2|]); auto with zarith.
apply Nat2Z.is_nonneg.
Qed.
Lemma spec_sqrt : forall x,
[|sqrt31 x|] ^ 2 <= [|x|] < ([|sqrt31 x|] + 1) ^ 2.
Proof.
intros i; unfold sqrt31.
rewrite spec_compare. case Z.compare_spec; change [|1|] with 1;
intros Hi; auto with zarith.
repeat rewrite Z.pow_2_r; auto with zarith.
apply iter31_sqrt_correct; auto with zarith.
rewrite div31_phi; change ([|2|]) with 2; auto with zarith.
replace ([|i|]) with (1 * 2 + ([|i|] - 2))%Z; try ring.
assert (0 <= ([|i|] - 2)/2)%Z by (apply Z_div_pos; auto with zarith).
rewrite Z_div_plus_full_l; auto with zarith.
rewrite div31_phi; change ([|2|]) with 2; auto with zarith.
apply sqrt_init; auto.
rewrite div31_phi; change ([|2|]) with 2; auto with zarith.
apply Z.le_lt_trans with ([|i|]).
apply Z_mult_div_ge; auto with zarith.
case (phi_bounded i); auto.
intros j2 H1 H2; contradict H2; apply Z.lt_nge.
rewrite div31_phi; change ([|2|]) with 2; auto with zarith.
apply Z.le_lt_trans with ([|i|]); auto with zarith.
assert (0 <= [|i|]/2)%Z by (apply Z_div_pos; auto with zarith).
apply Z.le_trans with (2 * ([|i|]/2)); auto with zarith.
apply Z_mult_div_ge; auto with zarith.
case (phi_bounded i); unfold size; auto with zarith.
change [|0|] with 0; auto with zarith.
case (phi_bounded i); repeat rewrite Z.pow_2_r; auto with zarith.
Qed.
Lemma sqrt312_step_def rec ih il j:
sqrt312_step rec ih il j =
match (ih ?= j)%int31 with
Eq => j
| Gt => j
| _ =>
match (fst (div3121 ih il j) ?= j)%int31 with
Lt => let m := match j +c fst (div3121 ih il j) with
C0 m1 => fst (m1/2)%int31
| C1 m1 => (fst (m1/2) + v30)%int31
end in rec ih il m
| _ => j
end
end.
Proof.
unfold sqrt312_step; case div3121; intros.
simpl; case compare31; auto.
Qed.
Lemma sqrt312_lower_bound ih il j:
phi2 ih il < ([|j|] + 1) ^ 2 -> [|ih|] <= [|j|].
Proof.
intros H1.
case (phi_bounded j); intros Hbj _.
case (phi_bounded il); intros Hbil _.
case (phi_bounded ih); intros Hbih Hbih1.
assert (([|ih|] < [|j|] + 1)%Z); auto with zarith.
apply Z.square_lt_simpl_nonneg; auto with zarith.
repeat rewrite <-Z.pow_2_r; apply Z.le_lt_trans with (2 := H1).
apply Z.le_trans with ([|ih|] * base)%Z; unfold phi2, base;
try rewrite Z.pow_2_r; auto with zarith.
Qed.
Lemma div312_phi ih il j: (2^30 <= [|j|] -> [|ih|] < [|j|] ->
[|fst (div3121 ih il j)|] = phi2 ih il/[|j|])%Z.
Proof.
intros Hj Hj1.
generalize (spec_div21 ih il j Hj Hj1).
case div3121; intros q r (Hq, Hr).
apply Zdiv_unique with (phi r); auto with zarith.
simpl @fst; apply eq_trans with (1 := Hq); ring.
Qed.
Lemma sqrt312_step_correct rec ih il j:
2 ^ 29 <= [|ih|] -> 0 < [|j|] -> phi2 ih il < ([|j|] + 1) ^ 2 ->
(forall j1, 0 < [|j1|] < [|j|] -> phi2 ih il < ([|j1|] + 1) ^ 2 ->
[|rec ih il j1|] ^ 2 <= phi2 ih il < ([|rec ih il j1|] + 1) ^ 2) ->
[|sqrt312_step rec ih il j|] ^ 2 <= phi2 ih il
< ([|sqrt312_step rec ih il j|] + 1) ^ 2.
Proof.
assert (Hp2: (0 < [|2|])%Z) by exact (eq_refl Lt).
intros Hih Hj Hij Hrec; rewrite sqrt312_step_def.
assert (H1: ([|ih|] <= [|j|])%Z) by (apply sqrt312_lower_bound with il; auto).
case (phi_bounded ih); intros Hih1 _.
case (phi_bounded il); intros Hil1 _.
case (phi_bounded j); intros _ Hj1.
assert (Hp3: (0 < phi2 ih il)).
unfold phi2; apply Z.lt_le_trans with ([|ih|] * base)%Z; auto with zarith.
apply Z.mul_pos_pos; auto with zarith.
apply Z.lt_le_trans with (2:= Hih); auto with zarith.
rewrite spec_compare. case Z.compare_spec; intros Hc1.
split; auto.
apply sqrt_test_true; auto.
unfold phi2, base; auto with zarith.
unfold phi2; rewrite Hc1.
assert (0 <= [|il|]/[|j|]) by (apply Z_div_pos; auto with zarith).
rewrite Z.mul_comm, Z_div_plus_full_l; unfold base; auto with zarith.
simpl wB in Hj1. unfold Z.pow_pos in Hj1. simpl in Hj1. auto with zarith.
case (Z.le_gt_cases (2 ^ 30) [|j|]); intros Hjj.
rewrite spec_compare; case Z.compare_spec;
rewrite div312_phi; auto; intros Hc;
try (split; auto; apply sqrt_test_true; auto with zarith; fail).
apply Hrec.
assert (Hf1: 0 <= phi2 ih il/ [|j|]) by (apply Z_div_pos; auto with zarith).
apply Z.le_succ_l in Hj. change (1 <= [|j|]) in Hj.
Z.le_elim Hj.
2: contradict Hc; apply Z.le_ngt; rewrite <- Hj, Zdiv_1_r; auto with zarith.
assert (Hf3: 0 < ([|j|] + phi2 ih il / [|j|]) / 2).
replace ([|j|] + phi2 ih il/ [|j|])%Z with
(1 * 2 + (([|j|] - 2) + phi2 ih il / [|j|])); try ring.
rewrite Z_div_plus_full_l; auto with zarith.
assert (0 <= ([|j|] - 2 + phi2 ih il / [|j|]) / 2) ; auto with zarith.
assert (Hf4: ([|j|] + phi2 ih il / [|j|]) / 2 < [|j|]).
apply sqrt_test_false; auto with zarith.
generalize (spec_add_c j (fst (div3121 ih il j))).
unfold interp_carry; case add31c; intros r;
rewrite div312_phi; auto with zarith.
rewrite div31_phi; change [|2|] with 2%Z; auto with zarith.
intros HH; rewrite HH; clear HH; auto with zarith.
rewrite spec_add, div31_phi; change [|2|] with 2%Z; auto.
rewrite Z.mul_1_l; intros HH.
rewrite Z.add_comm, <- Z_div_plus_full_l; auto with zarith.
change (phi v30 * 2) with (2 ^ Z.of_nat size).
rewrite HH, Zmod_small; auto with zarith.
replace (phi
match j +c fst (div3121 ih il j) with
| C0 m1 => fst (m1 / 2)%int31
| C1 m1 => fst (m1 / 2)%int31 + v30
end) with ((([|j|] + (phi2 ih il)/([|j|]))/2)).
apply sqrt_main; auto with zarith.
generalize (spec_add_c j (fst (div3121 ih il j))).
unfold interp_carry; case add31c; intros r;
rewrite div312_phi; auto with zarith.
rewrite div31_phi; auto with zarith.
intros HH; rewrite HH; auto with zarith.
intros HH; rewrite <- HH.
change (1 * 2 ^ Z.of_nat size) with (phi (v30) * 2).
rewrite Z_div_plus_full_l; auto with zarith.
rewrite Z.add_comm.
rewrite spec_add, Zmod_small.
rewrite div31_phi; auto.
split; auto with zarith.
case (phi_bounded (fst (r/2)%int31));
case (phi_bounded v30); auto with zarith.
rewrite div31_phi; change (phi 2) with 2%Z; auto.
change (2 ^Z.of_nat size) with (base/2 + phi v30).
assert (phi r / 2 < base/2); auto with zarith.
apply Z.mul_lt_mono_pos_r with 2; auto with zarith.
change (base/2 * 2) with base.
apply Z.le_lt_trans with (phi r).
rewrite Z.mul_comm; apply Z_mult_div_ge; auto with zarith.
case (phi_bounded r); auto with zarith.
contradict Hij; apply Z.le_ngt.
assert ((1 + [|j|]) <= 2 ^ 30); auto with zarith.
apply Z.le_trans with ((2 ^ 30) * (2 ^ 30)); auto with zarith.
assert (0 <= 1 + [|j|]); auto with zarith.
apply Z.mul_le_mono_nonneg; auto with zarith.
change ((2 ^ 30) * (2 ^ 30)) with ((2 ^ 29) * base).
apply Z.le_trans with ([|ih|] * base); auto with zarith.
unfold phi2, base; auto with zarith.
split; auto.
apply sqrt_test_true; auto.
unfold phi2, base; auto with zarith.
apply Z.le_ge; apply Z.le_trans with (([|j|] * base)/[|j|]).
rewrite Z.mul_comm, Z_div_mult; auto with zarith.
apply Z.ge_le; apply Z_div_ge; auto with zarith.
Qed.
Lemma iter312_sqrt_correct n rec ih il j:
2^29 <= [|ih|] -> 0 < [|j|] -> phi2 ih il < ([|j|] + 1) ^ 2 ->
(forall j1, 0 < [|j1|] -> 2^(Z.of_nat n) + [|j1|] <= [|j|] ->
phi2 ih il < ([|j1|] + 1) ^ 2 ->
[|rec ih il j1|] ^ 2 <= phi2 ih il < ([|rec ih il j1|] + 1) ^ 2) ->
[|iter312_sqrt n rec ih il j|] ^ 2 <= phi2 ih il
< ([|iter312_sqrt n rec ih il j|] + 1) ^ 2.
Proof.
revert rec ih il j; elim n; unfold iter312_sqrt; fold iter312_sqrt; clear n.
intros rec ih il j Hi Hj Hij Hrec; apply sqrt312_step_correct; auto with zarith.
intros; apply Hrec; auto with zarith.
rewrite Z.pow_0_r; auto with zarith.
intros n Hrec rec ih il j Hi Hj Hij HHrec.
apply sqrt312_step_correct; auto.
intros j1 Hj1 Hjp1; apply Hrec; auto with zarith.
intros j2 Hj2 H2j2 Hjp2; apply Hrec; auto with zarith.
intros j3 Hj3 Hpj3.
apply HHrec; auto.
rewrite Nat2Z.inj_succ, Z.pow_succ_r.
apply Z.le_trans with (2 ^Z.of_nat n + [|j2|])%Z; auto with zarith.
apply Nat2Z.is_nonneg.
Qed.
(* Avoid expanding [iter312_sqrt] before variables in the context. *)
Strategy 1 [iter312_sqrt].
Lemma spec_sqrt2 : forall x y,
wB/ 4 <= [|x|] ->
let (s,r) := sqrt312 x y in
[||WW x y||] = [|s|] ^ 2 + [+|r|] /\
[+|r|] <= 2 * [|s|].
Proof.
intros ih il Hih; unfold sqrt312.
change [||WW ih il||] with (phi2 ih il).
assert (Hbin: forall s, s * s + 2* s + 1 = (s + 1) ^ 2) by
(intros s; ring).
assert (Hb: 0 <= base) by (red; intros HH; discriminate).
assert (Hi2: phi2 ih il < (phi Tn + 1) ^ 2).
{ change ((phi Tn + 1) ^ 2) with (2^62).
apply Z.le_lt_trans with ((2^31 -1) * base + (2^31 - 1)); auto with zarith.
2: simpl; unfold Z.pow_pos; simpl; auto with zarith.
case (phi_bounded ih); case (phi_bounded il); intros H1 H2 H3 H4.
unfold base, Z.pow, Z.pow_pos in H2,H4; simpl in H2,H4.
unfold phi2. cbn [Z.pow Z.pow_pos Pos.iter]. auto with zarith. }
case (iter312_sqrt_correct 31 (fun _ _ j => j) ih il Tn); auto with zarith.
change [|Tn|] with 2147483647; auto with zarith.
intros j1 _ HH; contradict HH.
apply Z.lt_nge.
change [|Tn|] with 2147483647; auto with zarith.
change (2 ^ Z.of_nat 31) with 2147483648; auto with zarith.
case (phi_bounded j1); auto with zarith.
set (s := iter312_sqrt 31 (fun _ _ j : int31 => j) ih il Tn).
intros Hs1 Hs2.
generalize (spec_mul_c s s); case mul31c.
simpl zn2z_to_Z; intros HH.
assert ([|s|] = 0).
{ symmetry in HH. rewrite Z.mul_eq_0 in HH. destruct HH; auto. }
contradict Hs2; apply Z.le_ngt; rewrite H.
change ((0 + 1) ^ 2) with 1.
apply Z.le_trans with (2 ^ Z.of_nat size / 4 * base).
simpl; auto with zarith.
apply Z.le_trans with ([|ih|] * base); auto with zarith.
unfold phi2; case (phi_bounded il); auto with zarith.
intros ih1 il1.
change [||WW ih1 il1||] with (phi2 ih1 il1).
intros Hihl1.
generalize (spec_sub_c il il1).
case sub31c; intros il2 Hil2.
rewrite spec_compare; case Z.compare_spec.
unfold interp_carry in *.
intros H1; split.
rewrite Z.pow_2_r, <- Hihl1.
unfold phi2; ring[Hil2 H1].
replace [|il2|] with (phi2 ih il - phi2 ih1 il1).
rewrite Hihl1.
rewrite <-Hbin in Hs2; auto with zarith.
unfold phi2; rewrite H1, Hil2; ring.
unfold interp_carry.
intros H1; contradict Hs1.
apply Z.lt_nge; rewrite Z.pow_2_r, <-Hihl1.
unfold phi2.
case (phi_bounded il); intros _ H2.
apply Z.lt_le_trans with (([|ih|] + 1) * base + 0).
rewrite Z.mul_add_distr_r, Z.add_0_r; auto with zarith.
case (phi_bounded il1); intros H3 _.
apply Z.add_le_mono; auto with zarith.
unfold interp_carry in *; change (1 * 2 ^ Z.of_nat size) with base.
rewrite Z.pow_2_r, <- Hihl1, Hil2.
intros H1.
rewrite <- Z.le_succ_l, <- Z.add_1_r in H1.
Z.le_elim H1.
contradict Hs2; apply Z.le_ngt.
replace (([|s|] + 1) ^ 2) with (phi2 ih1 il1 + 2 * [|s|] + 1).
unfold phi2.
case (phi_bounded il); intros Hpil _.
assert (Hl1l: [|il1|] <= [|il|]).
{ case (phi_bounded il2); rewrite Hil2; auto with zarith. }
assert ([|ih1|] * base + 2 * [|s|] + 1 <= [|ih|] * base); auto with zarith.
case (phi_bounded s); change (2 ^ Z.of_nat size) with base; intros _ Hps.
case (phi_bounded ih1); intros Hpih1 _; auto with zarith.
apply Z.le_trans with (([|ih1|] + 2) * base); auto with zarith.
rewrite Z.mul_add_distr_r.
assert (2 * [|s|] + 1 <= 2 * base); auto with zarith.
rewrite Hihl1, Hbin; auto.
split.
unfold phi2; rewrite <- H1; ring.
replace (base + ([|il|] - [|il1|])) with (phi2 ih il - ([|s|] * [|s|])).
rewrite <-Hbin in Hs2; auto with zarith.
rewrite <- Hihl1; unfold phi2; rewrite <- H1; ring.
unfold interp_carry in Hil2 |- *.
unfold interp_carry; change (1 * 2 ^ Z.of_nat size) with base.
assert (Hsih: [|ih - 1|] = [|ih|] - 1).
{ rewrite spec_sub, Zmod_small; auto; change [|1|] with 1.
case (phi_bounded ih); intros H1 H2.
generalize Hih; change (2 ^ Z.of_nat size / 4) with 536870912.
split; auto with zarith. }
rewrite spec_compare; case Z.compare_spec.
rewrite Hsih.
intros H1; split.
rewrite Z.pow_2_r, <- Hihl1.
unfold phi2; rewrite <-H1.
transitivity ([|ih|] * base + [|il1|] + ([|il|] - [|il1|])).
ring.
rewrite <-Hil2.
change (2 ^ Z.of_nat size) with base; ring.
replace [|il2|] with (phi2 ih il - phi2 ih1 il1).
rewrite Hihl1.
rewrite <-Hbin in Hs2; auto with zarith.
unfold phi2.
rewrite <-H1.
ring_simplify.
transitivity (base + ([|il|] - [|il1|])).
ring.
rewrite <-Hil2.
change (2 ^ Z.of_nat size) with base; ring.
rewrite Hsih; intros H1.
assert (He: [|ih|] = [|ih1|]).
{ apply Z.le_antisymm; auto with zarith.
case (Z.le_gt_cases [|ih1|] [|ih|]); auto; intros H2.
contradict Hs1; apply Z.lt_nge; rewrite Z.pow_2_r, <-Hihl1.
unfold phi2.
case (phi_bounded il); change (2 ^ Z.of_nat size) with base;
intros _ Hpil1.
apply Z.lt_le_trans with (([|ih|] + 1) * base).
rewrite Z.mul_add_distr_r, Z.mul_1_l; auto with zarith.
case (phi_bounded il1); intros Hpil2 _.
apply Z.le_trans with (([|ih1|]) * base); auto with zarith. }
rewrite Z.pow_2_r, <-Hihl1; unfold phi2; rewrite <-He.
contradict Hs1; apply Z.lt_nge; rewrite Z.pow_2_r, <-Hihl1.
unfold phi2; rewrite He.
assert (phi il - phi il1 < 0); auto with zarith.
rewrite <-Hil2.
case (phi_bounded il2); auto with zarith.
intros H1.
rewrite Z.pow_2_r, <-Hihl1.
assert (H2 : [|ih1|]+2 <= [|ih|]); auto with zarith.
Z.le_elim H2.
contradict Hs2; apply Z.le_ngt.
replace (([|s|] + 1) ^ 2) with (phi2 ih1 il1 + 2 * [|s|] + 1).
unfold phi2.
assert ([|ih1|] * base + 2 * phi s + 1 <= [|ih|] * base + ([|il|] - [|il1|]));
auto with zarith.
rewrite <-Hil2.
change (-1 * 2 ^ Z.of_nat size) with (-base).
case (phi_bounded il2); intros Hpil2 _.
apply Z.le_trans with ([|ih|] * base + - base); auto with zarith.
case (phi_bounded s); change (2 ^ Z.of_nat size) with base; intros _ Hps.
assert (2 * [|s|] + 1 <= 2 * base); auto with zarith.
apply Z.le_trans with ([|ih1|] * base + 2 * base); auto with zarith.
assert (Hi: ([|ih1|] + 3) * base <= [|ih|] * base); auto with zarith.
rewrite Z.mul_add_distr_r in Hi; auto with zarith.
rewrite Hihl1, Hbin; auto.
unfold phi2; rewrite <-H2.
split.
replace [|il|] with (([|il|] - [|il1|]) + [|il1|]); try ring.
rewrite <-Hil2.
change (-1 * 2 ^ Z.of_nat size) with (-base); ring.
replace (base + [|il2|]) with (phi2 ih il - phi2 ih1 il1).
rewrite Hihl1.
rewrite <-Hbin in Hs2; auto with zarith.
unfold phi2; rewrite <-H2.
replace [|il|] with (([|il|] - [|il1|]) + [|il1|]); try ring.
rewrite <-Hil2.
change (-1 * 2 ^ Z.of_nat size) with (-base); ring.
Qed.
(** [iszero] *)
Lemma spec_eq0 : forall x, ZnZ.eq0 x = true -> [|x|] = 0.
Proof.
clear; unfold ZnZ.eq0, int31_ops.
unfold compare31; intros.
change [|0|] with 0 in H.
apply Z.compare_eq.
now destruct ([|x|] ?= 0).
Qed.
(* Even *)
Lemma spec_is_even : forall x,
if ZnZ.is_even x then [|x|] mod 2 = 0 else [|x|] mod 2 = 1.
Proof.
unfold ZnZ.is_even, int31_ops; intros.
generalize (spec_div x 2).
destruct (x/2)%int31 as (q,r); intros.
unfold compare31.
change [|2|] with 2 in H.
change [|0|] with 0.
destruct H; auto with zarith.
replace ([|x|] mod 2) with [|r|].
destruct H; auto with zarith.
case Z.compare_spec; auto with zarith.
apply Zmod_unique with [|q|]; auto with zarith.
Qed.
(* Bitwise *)
Lemma log2_phi_bounded x : Z.log2 [|x|] < Z.of_nat size.
Proof.
destruct (phi_bounded x) as (H,H').
Z.le_elim H.
- now apply Z.log2_lt_pow2.
- now rewrite <- H.
Qed.
Lemma spec_lor x y : [| ZnZ.lor x y |] = Z.lor [|x|] [|y|].
Proof.
unfold ZnZ.lor,int31_ops. unfold lor31.
rewrite phi_phi_inv.
apply Z.mod_small; split; trivial.
- apply Z.lor_nonneg; split; apply phi_bounded.
- apply Z.log2_lt_cancel. rewrite Z.log2_pow2 by easy.
rewrite Z.log2_lor; try apply phi_bounded.
apply Z.max_lub_lt; apply log2_phi_bounded.
Qed.
Lemma spec_land x y : [| ZnZ.land x y |] = Z.land [|x|] [|y|].
Proof.
unfold ZnZ.land, int31_ops. unfold land31.
rewrite phi_phi_inv.
apply Z.mod_small; split; trivial.
- apply Z.land_nonneg; left; apply phi_bounded.
- apply Z.log2_lt_cancel. rewrite Z.log2_pow2 by easy.
eapply Z.le_lt_trans.
apply Z.log2_land; try apply phi_bounded.
apply Z.min_lt_iff; left; apply log2_phi_bounded.
Qed.
Lemma spec_lxor x y : [| ZnZ.lxor x y |] = Z.lxor [|x|] [|y|].
Proof.
unfold ZnZ.lxor, int31_ops. unfold lxor31.
rewrite phi_phi_inv.
apply Z.mod_small; split; trivial.
- apply Z.lxor_nonneg; split; intros; apply phi_bounded.
- apply Z.log2_lt_cancel. rewrite Z.log2_pow2 by easy.
eapply Z.le_lt_trans.
apply Z.log2_lxor; try apply phi_bounded.
apply Z.max_lub_lt; apply log2_phi_bounded.
Qed.
Global Instance int31_specs : ZnZ.Specs int31_ops := {
spec_to_Z := phi_bounded;
spec_of_pos := positive_to_int31_spec;
spec_zdigits := spec_zdigits;
spec_more_than_1_digit := spec_more_than_1_digit;
spec_0 := spec_0;
spec_1 := spec_1;
spec_m1 := spec_m1;
spec_compare := spec_compare;
spec_eq0 := spec_eq0;
spec_opp_c := spec_opp_c;
spec_opp := spec_opp;
spec_opp_carry := spec_opp_carry;
spec_succ_c := spec_succ_c;
spec_add_c := spec_add_c;
spec_add_carry_c := spec_add_carry_c;
spec_succ := spec_succ;
spec_add := spec_add;
spec_add_carry := spec_add_carry;
spec_pred_c := spec_pred_c;
spec_sub_c := spec_sub_c;
spec_sub_carry_c := spec_sub_carry_c;
spec_pred := spec_pred;
spec_sub := spec_sub;
spec_sub_carry := spec_sub_carry;
spec_mul_c := spec_mul_c;
spec_mul := spec_mul;
spec_square_c := spec_square_c;
spec_div21 := spec_div21;
spec_div_gt := fun a b _ => spec_div a b;
spec_div := spec_div;
spec_modulo_gt := fun a b _ => spec_mod a b;
spec_modulo := spec_mod;
spec_gcd_gt := fun a b _ => spec_gcd a b;
spec_gcd := spec_gcd;
spec_head00 := spec_head00;
spec_head0 := spec_head0;
spec_tail00 := spec_tail00;
spec_tail0 := spec_tail0;
spec_add_mul_div := spec_add_mul_div;
spec_pos_mod := spec_pos_mod;
spec_is_even := spec_is_even;
spec_sqrt2 := spec_sqrt2;
spec_sqrt := spec_sqrt;
spec_lor := spec_lor;
spec_land := spec_land;
spec_lxor := spec_lxor }.
End Int31_Specs.
Module Int31Cyclic <: CyclicType.
Definition t := int31.
Definition ops := int31_ops.
Definition specs := int31_specs.
End Int31Cyclic.
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Jeremy Bennett.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
wire [19:10] bitout;
wire [29:24] short_bitout;
wire [7:0] allbits;
wire [15:0] twobits;
sub
i_sub1 [7:4] (.allbits (allbits),
.twobits (twobits[15:8]),
.bitout (bitout[17:14])),
i_sub2 [3:0] (.allbits (allbits),
.twobits (twobits[7:0]),
.bitout (bitout[13:10]));
sub
i_sub3 [7:4] (.allbits (allbits),
.twobits (twobits[15:8]),
.bitout (bitout[17:14]));
sub
i_sub4 [7:4] (.allbits (allbits),
.twobits (twobits[15:8]),
.bitout (short_bitout[27:24]));
sub
i_sub5 [7:0] (.allbits (allbits),
.twobits (twobits),
.bitout (bitout[17:10]));
sub
i_sub6 [7:4] (.allbits (allbits),
.twobits (twobits[15:8]),
.bitout ({bitout[18+:2],short_bitout[28+:2]}));
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Signals under test
assign allbits = crc[7:0];
assign twobits = crc[15:0];
wire [63:0] result = {48'h0, short_bitout, bitout};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'ha1da9ff8082a4ff6
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule // t
module sub
( input wire [7:0] allbits,
input wire [1:0] twobits,
output wire bitout);
assign bitout = (^ twobits) ^ (^ allbits);
endmodule // sub
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A221O_BEHAVIORAL_V
`define SKY130_FD_SC_HS__A221O_BEHAVIORAL_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a221o (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
// Local signals
wire B2 and0_out ;
wire B2 and1_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X , and1_out, and0_out, C1);
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND );
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A221O_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR2_TB_V
`define SKY130_FD_SC_HDLL__NOR2_TB_V
/**
* nor2: 2-input NOR.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nor2.v"
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hdll__nor2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR2_TB_V
|
// megafunction wizard: %ALTFP_LOG%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTFP_LOG
// ============================================================
// File Name: acl_fp_log_double.v
// Megafunction Name(s):
// ALTFP_LOG
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
// ************************************************************
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altfp_log CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" PIPELINE=34 WIDTH_EXP=11 WIDTH_MAN=52 clk_en clock data result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_log 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_altsquare 2010:08:18:21:07:10:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" PIPELINE=1 SHIFTDIR="LEFT" WIDTH=64 WIDTHDIST=6 aclr clk_en clock data distance result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//synthesis_resources = reg 65
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_double_altbarrel_shift_32e
(
aclr,
clk_en,
clock,
data,
distance,
result) ;
input aclr;
input clk_en;
input clock;
input [63:0] data;
input [5:0] distance;
output [63:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clk_en;
tri0 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [0:0] dir_pipe;
reg [63:0] sbit_piper1d;
wire [6:0] dir_w;
wire direction_w;
wire [31:0] pad_w;
wire [447:0] sbit_w;
wire [5:0] sel_w;
wire [383:0] smux_w;
// synopsys translate_off
initial
dir_pipe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) dir_pipe <= 1'b0;
else if (clk_en == 1'b1) dir_pipe <= {dir_w[5]};
// synopsys translate_off
initial
sbit_piper1d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sbit_piper1d <= 64'b0;
else if (clk_en == 1'b1) sbit_piper1d <= smux_w[383:320];
assign
dir_w = {dir_pipe[0], dir_w[4:0], direction_w},
direction_w = 1'b0,
pad_w = {32{1'b0}},
result = sbit_w[447:384],
sbit_w = {sbit_piper1d, smux_w[319:0], data},
sel_w = {distance[5:0]},
smux_w = {((({64{(sel_w[5] & (~ dir_w[5]))}} & {sbit_w[351:320], pad_w[31:0]}) | ({64{(sel_w[5] & dir_w[5])}} & {pad_w[31:0], sbit_w[383:352]})) | ({64{(~ sel_w[5])}} & sbit_w[383:320])), ((({64{(sel_w[4] & (~ dir_w[4]))}} & {sbit_w[303:256], pad_w[15:0]}) | ({64{(sel_w[4] & dir_w[4])}} & {pad_w[15:0], sbit_w[319:272]})) | ({64{(~ sel_w[4])}} & sbit_w[319:256])), ((({64{(sel_w[3] & (~ dir_w[3]))}} & {sbit_w[247:192], pad_w[7:0]}) | ({64{(sel_w[3] & dir_w[3])}} & {pad_w[7:0], sbit_w[255:200]})) | ({64{(~ sel_w[3])}} & sbit_w[255:192])), ((({64{(sel_w[2] & (~ dir_w[2]))}} & {sbit_w[187:128], pad_w[3:0]}) | ({64{(sel_w[2] & dir_w[2])}} & {pad_w[3:0], sbit_w[191:132]})) | ({64{(~ sel_w[2])}} & sbit_w[191:128])), ((({64{(sel_w[1] & (~ dir_w[1]))}} & {sbit_w[125:64], pad_w[1:0]}) | ({64{(sel_w[1] & dir_w[1])}} & {pad_w[1:0], sbit_w[127:66]})) | ({64{(~ sel_w[1])}} & sbit_w[127:64])), ((({64{(sel_w[0] & (~ dir_w[0]))}} & {sbit_w[62:0], pad_w[0]}) | ({64{(sel_w[0] & dir_w[0])}} & {pad_w[0], sbit_w[63:1]})) | ({64{(~ sel_w[0])}} & sbit_w[63:0]))};
endmodule //acl_fp_log_double_altbarrel_shift_32e
//altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" SHIFTDIR="LEFT" WIDTH=128 WIDTHDIST=7 data distance result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_double_altbarrel_shift_ngb
(
data,
distance,
result) ;
input [127:0] data;
input [6:0] distance;
output [127:0] result;
wire [7:0] dir_w;
wire direction_w;
wire [63:0] pad_w;
wire [1023:0] sbit_w;
wire [6:0] sel_w;
wire [895:0] smux_w;
assign
dir_w = {dir_w[6:0], direction_w},
direction_w = 1'b0,
pad_w = {64{1'b0}},
result = sbit_w[1023:896],
sbit_w = {smux_w[895:0], data},
sel_w = {distance[6:0]},
smux_w = {((({128{(sel_w[6] & (~ dir_w[6]))}} & {sbit_w[831:768], pad_w[63:0]}) | ({128{(sel_w[6] & dir_w[6])}} & {pad_w[63:0], sbit_w[895:832]})) | ({128{(~ sel_w[6])}} & sbit_w[895:768])), ((({128{(sel_w[5] & (~ dir_w[5]))}} & {sbit_w[735:640], pad_w[31:0]}) | ({128{(sel_w[5] & dir_w[5])}} & {pad_w[31:0], sbit_w[767:672]})) | ({128{(~ sel_w[5])}} & sbit_w[767:640])), ((({128{(sel_w[4] & (~ dir_w[4]))}} & {sbit_w[623:512], pad_w[15:0]}) | ({128{(sel_w[4] & dir_w[4])}} & {pad_w[15:0], sbit_w[639:528]})) | ({128{(~ sel_w[4])}} & sbit_w[639:512])), ((({128{(sel_w[3] & (~ dir_w[3]))}} & {sbit_w[503:384], pad_w[7:0]}) | ({128{(sel_w[3] & dir_w[3])}} & {pad_w[7:0], sbit_w[511:392]})) | ({128{(~ sel_w[3])}} & sbit_w[511:384])), ((({128{(sel_w[2] & (~ dir_w[2]))}} & {sbit_w[379:256], pad_w[3:0]}) | ({128{(sel_w[2] & dir_w[2])}} & {pad_w[3:0], sbit_w[383:260]})) | ({128{(~ sel_w[2])}} & sbit_w[383:256])), ((({128{(sel_w[1] & (~ dir_w[1]))}} & {sbit_w[253:128], pad_w[1:0]}) | ({128{(sel_w[1] & dir_w[1])}} & {pad_w[1:0], sbit_w[255:130]})) | ({128{(~ sel_w[1])}} & sbit_w[255:128])), ((({128{(sel_w[0] & (~ dir_w[0]))}} & {sbit_w[126:0], pad_w[0]}) | ({128{(sel_w[0] & dir_w[0])}} & {pad_w[0], sbit_w[127:1]})) | ({128{(~ sel_w[0])}} & sbit_w[127:0]))};
endmodule //acl_fp_log_double_altbarrel_shift_ngb
//altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" PIPELINE=1 SHIFTDIR="RIGHT" WIDTH=64 WIDTHDIST=6 aclr clk_en clock data distance result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//synthesis_resources = reg 65
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_double_altbarrel_shift_m5e
(
aclr,
clk_en,
clock,
data,
distance,
result) ;
input aclr;
input clk_en;
input clock;
input [63:0] data;
input [5:0] distance;
output [63:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clk_en;
tri0 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [0:0] dir_pipe;
reg [63:0] sbit_piper1d;
wire [6:0] dir_w;
wire direction_w;
wire [31:0] pad_w;
wire [447:0] sbit_w;
wire [5:0] sel_w;
wire [383:0] smux_w;
// synopsys translate_off
initial
dir_pipe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) dir_pipe <= 1'b0;
else if (clk_en == 1'b1) dir_pipe <= {dir_w[5]};
// synopsys translate_off
initial
sbit_piper1d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sbit_piper1d <= 64'b0;
else if (clk_en == 1'b1) sbit_piper1d <= smux_w[383:320];
assign
dir_w = {dir_pipe[0], dir_w[4:0], direction_w},
direction_w = 1'b1,
pad_w = {32{1'b0}},
result = sbit_w[447:384],
sbit_w = {sbit_piper1d, smux_w[319:0], data},
sel_w = {distance[5:0]},
smux_w = {((({64{(sel_w[5] & (~ dir_w[5]))}} & {sbit_w[351:320], pad_w[31:0]}) | ({64{(sel_w[5] & dir_w[5])}} & {pad_w[31:0], sbit_w[383:352]})) | ({64{(~ sel_w[5])}} & sbit_w[383:320])), ((({64{(sel_w[4] & (~ dir_w[4]))}} & {sbit_w[303:256], pad_w[15:0]}) | ({64{(sel_w[4] & dir_w[4])}} & {pad_w[15:0], sbit_w[319:272]})) | ({64{(~ sel_w[4])}} & sbit_w[319:256])), ((({64{(sel_w[3] & (~ dir_w[3]))}} & {sbit_w[247:192], pad_w[7:0]}) | ({64{(sel_w[3] & dir_w[3])}} & {pad_w[7:0], sbit_w[255:200]})) | ({64{(~ sel_w[3])}} & sbit_w[255:192])), ((({64{(sel_w[2] & (~ dir_w[2]))}} & {sbit_w[187:128], pad_w[3:0]}) | ({64{(sel_w[2] & dir_w[2])}} & {pad_w[3:0], sbit_w[191:132]})) | ({64{(~ sel_w[2])}} & sbit_w[191:128])), ((({64{(sel_w[1] & (~ dir_w[1]))}} & {sbit_w[125:64], pad_w[1:0]}) | ({64{(sel_w[1] & dir_w[1])}} & {pad_w[1:0], sbit_w[127:66]})) | ({64{(~ sel_w[1])}} & sbit_w[127:64])), ((({64{(sel_w[0] & (~ dir_w[0]))}} & {sbit_w[62:0], pad_w[0]}) | ({64{(sel_w[0] & dir_w[0])}} & {pad_w[0], sbit_w[63:1]})) | ({64{(~ sel_w[0])}} & sbit_w[63:0]))};
endmodule //acl_fp_log_double_altbarrel_shift_m5e
//altfp_log_and_or CBX_AUTO_BLACKBOX="ALL" LUT_INPUT_COUNT=6 OPERATION="AND" PIPELINE=3 WIDTH=11 aclr clken clock data result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_log 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_altsquare 2010:08:18:21:07:10:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//synthesis_resources = reg 4
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_double_altfp_log_and_or_rab
(
aclr,
clken,
clock,
data,
result) ;
input aclr;
input clken;
input clock;
input [10:0] data;
output result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [10:0] data;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [1:0] connection_dffe0;
reg [0:0] connection_dffe1;
reg connection_dffe2;
wire [10:0] connection_r0_w;
wire [1:0] connection_r1_w;
wire [0:0] connection_r2_w;
wire [10:0] operation_r1_w;
wire [1:0] operation_r2_w;
// synopsys translate_off
initial
connection_dffe0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) connection_dffe0 <= 2'b0;
else if (clken == 1'b1) connection_dffe0 <= {operation_r1_w[10], operation_r1_w[5]};
// synopsys translate_off
initial
connection_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) connection_dffe1 <= 1'b0;
else if (clken == 1'b1) connection_dffe1 <= {operation_r2_w[1]};
// synopsys translate_off
initial
connection_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) connection_dffe2 <= 1'b0;
else if (clken == 1'b1) connection_dffe2 <= connection_r2_w[0];
assign
connection_r0_w = data,
connection_r1_w = connection_dffe0,
connection_r2_w = connection_dffe1,
operation_r1_w = {(operation_r1_w[9] & connection_r0_w[10]), (operation_r1_w[8] & connection_r0_w[9]), (operation_r1_w[7] & connection_r0_w[8]), (operation_r1_w[6] & connection_r0_w[7]), connection_r0_w[6], (operation_r1_w[4] & connection_r0_w[5]), (operation_r1_w[3] & connection_r0_w[4]), (operation_r1_w[2] & connection_r0_w[3]), (operation_r1_w[1] & connection_r0_w[2]), (operation_r1_w[0] & connection_r0_w[1]), connection_r0_w[0]},
operation_r2_w = {(operation_r2_w[0] & connection_r1_w[1]), connection_r1_w[0]},
result = connection_dffe2;
endmodule //acl_fp_log_double_altfp_log_and_or_rab
//altfp_log_and_or CBX_AUTO_BLACKBOX="ALL" LUT_INPUT_COUNT=6 OPERATION="OR" PIPELINE=3 WIDTH=11 aclr clken clock data result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_log 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_altsquare 2010:08:18:21:07:10:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//synthesis_resources = reg 4
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_double_altfp_log_and_or_98b
(
aclr,
clken,
clock,
data,
result) ;
input aclr;
input clken;
input clock;
input [10:0] data;
output result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [10:0] data;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [1:0] connection_dffe0;
reg [0:0] connection_dffe1;
reg connection_dffe2;
wire [10:0] connection_r0_w;
wire [1:0] connection_r1_w;
wire [0:0] connection_r2_w;
wire [10:0] operation_r1_w;
wire [1:0] operation_r2_w;
// synopsys translate_off
initial
connection_dffe0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) connection_dffe0 <= 2'b0;
else if (clken == 1'b1) connection_dffe0 <= {operation_r1_w[10], operation_r1_w[5]};
// synopsys translate_off
initial
connection_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) connection_dffe1 <= 1'b0;
else if (clken == 1'b1) connection_dffe1 <= {operation_r2_w[1]};
// synopsys translate_off
initial
connection_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) connection_dffe2 <= 1'b0;
else if (clken == 1'b1) connection_dffe2 <= connection_r2_w[0];
assign
connection_r0_w = data,
connection_r1_w = connection_dffe0,
connection_r2_w = connection_dffe1,
operation_r1_w = {(operation_r1_w[9] | connection_r0_w[10]), (operation_r1_w[8] | connection_r0_w[9]), (operation_r1_w[7] | connection_r0_w[8]), (operation_r1_w[6] | connection_r0_w[7]), connection_r0_w[6], (operation_r1_w[4] | connection_r0_w[5]), (operation_r1_w[3] | connection_r0_w[4]), (operation_r1_w[2] | connection_r0_w[3]), (operation_r1_w[1] | connection_r0_w[2]), (operation_r1_w[0] | connection_r0_w[1]), connection_r0_w[0]},
operation_r2_w = {(operation_r2_w[0] | connection_r1_w[1]), connection_r1_w[0]},
result = connection_dffe2;
endmodule //acl_fp_log_double_altfp_log_and_or_98b
//altfp_log_and_or CBX_AUTO_BLACKBOX="ALL" LUT_INPUT_COUNT=6 OPERATION="OR" PIPELINE=3 WIDTH=52 aclr clken clock data result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_log 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_altsquare 2010:08:18:21:07:10:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//synthesis_resources = reg 12
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_double_altfp_log_and_or_e8b
(
aclr,
clken,
clock,
data,
result) ;
input aclr;
input clken;
input clock;
input [51:0] data;
output result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [51:0] data;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [8:0] connection_dffe0;
reg [1:0] connection_dffe1;
reg [0:0] connection_dffe2;
wire [51:0] connection_r0_w;
wire [8:0] connection_r1_w;
wire [1:0] connection_r2_w;
wire [0:0] connection_r3_w;
wire [51:0] operation_r1_w;
wire [8:0] operation_r2_w;
wire [1:0] operation_r3_w;
// synopsys translate_off
initial
connection_dffe0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) connection_dffe0 <= 9'b0;
else if (clken == 1'b1) connection_dffe0 <= {operation_r1_w[51], operation_r1_w[47], operation_r1_w[41], operation_r1_w[35], operation_r1_w[29], operation_r1_w[23], operation_r1_w[17], operation_r1_w[11], operation_r1_w[5]};
// synopsys translate_off
initial
connection_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) connection_dffe1 <= 2'b0;
else if (clken == 1'b1) connection_dffe1 <= {operation_r2_w[8], operation_r2_w[5]};
// synopsys translate_off
initial
connection_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) connection_dffe2 <= 1'b0;
else if (clken == 1'b1) connection_dffe2 <= {operation_r3_w[1]};
assign
connection_r0_w = data,
connection_r1_w = connection_dffe0,
connection_r2_w = connection_dffe1,
connection_r3_w = connection_dffe2,
operation_r1_w = {(operation_r1_w[50] | connection_r0_w[51]), (operation_r1_w[49] | connection_r0_w[50]), (operation_r1_w[48] | connection_r0_w[49]), connection_r0_w[48], (operation_r1_w[46] | connection_r0_w[47]), (operation_r1_w[45] | connection_r0_w[46]), (operation_r1_w[44] | connection_r0_w[45]), (operation_r1_w[43] | connection_r0_w[44]), (operation_r1_w[42] | connection_r0_w[43]), connection_r0_w[42], (operation_r1_w[40] | connection_r0_w[41]), (operation_r1_w[39] | connection_r0_w[40]), (operation_r1_w[38] | connection_r0_w[39]), (operation_r1_w[37] | connection_r0_w[38]), (operation_r1_w[36] | connection_r0_w[37]), connection_r0_w[36], (operation_r1_w[34] | connection_r0_w[35]), (operation_r1_w[33] | connection_r0_w[34]), (operation_r1_w[32] | connection_r0_w[33]), (operation_r1_w[31] | connection_r0_w[32]), (operation_r1_w[30] | connection_r0_w[31]), connection_r0_w[30], (operation_r1_w[28] | connection_r0_w[29]), (operation_r1_w[27] | connection_r0_w[28]), (operation_r1_w[26] | connection_r0_w[27]), (operation_r1_w[25] | connection_r0_w[26]), (operation_r1_w[24] | connection_r0_w[25]), connection_r0_w[24], (operation_r1_w[22] | connection_r0_w[23]), (operation_r1_w[21] | connection_r0_w[22]), (operation_r1_w[20] | connection_r0_w[21]), (operation_r1_w[19] | connection_r0_w[20]), (operation_r1_w[18] | connection_r0_w[19]), connection_r0_w[18], (operation_r1_w[16] | connection_r0_w[17]), (operation_r1_w[15] | connection_r0_w[16]), (operation_r1_w[14] | connection_r0_w[15]), (operation_r1_w[13] | connection_r0_w[14]), (operation_r1_w[12] | connection_r0_w[13]), connection_r0_w[12], (operation_r1_w[10] | connection_r0_w[11]), (operation_r1_w[9] | connection_r0_w[10]), (operation_r1_w[8] | connection_r0_w[9]), (operation_r1_w[7] | connection_r0_w[8]), (operation_r1_w[6] | connection_r0_w[7]), connection_r0_w[6], (operation_r1_w[4] | connection_r0_w[5]), (operation_r1_w[3] | connection_r0_w[4]), (operation_r1_w[2] | connection_r0_w[3]), (operation_r1_w[1] | connection_r0_w[2]), (operation_r1_w[0] | connection_r0_w[1]
), connection_r0_w[0]},
operation_r2_w = {(operation_r2_w[7] | connection_r1_w[8]), (operation_r2_w[6] | connection_r1_w[7]), connection_r1_w[6], (operation_r2_w[4] | connection_r1_w[5]), (operation_r2_w[3] | connection_r1_w[4]), (operation_r2_w[2] | connection_r1_w[3]), (operation_r2_w[1] | connection_r1_w[2]), (operation_r2_w[0] | connection_r1_w[1]), connection_r1_w[0]},
operation_r3_w = {(operation_r3_w[0] | connection_r2_w[1]), connection_r2_w[0]},
result = connection_r3_w[0];
endmodule //acl_fp_log_double_altfp_log_and_or_e8b
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="ADD" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=83 aclr clken clock dataa datab result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_log 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_altsquare 2010:08:18:21:07:10:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_double_altfp_log_csa_r0e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [82:0] dataa;
input [82:0] datab;
output [82:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [82:0] dataa;
tri0 [82:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [41:0] wire_csa_lower_result;
wire [40:0] wire_csa_upper0_result;
wire [40:0] wire_csa_upper1_result;
wire [82:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[41:0]),
.datab(datab[41:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "ADD",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 42,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[82:42]),
.datab(datab[82:42]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "ADD",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 41,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[82:42]),
.datab(datab[82:42]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "ADD",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 41,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({41{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({41{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_double_altfp_log_csa_r0e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="ADD" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=63 aclr clken clock dataa datab result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_log 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_altsquare 2010:08:18:21:07:10:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_double_altfp_log_csa_p0e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [62:0] dataa;
input [62:0] datab;
output [62:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [62:0] dataa;
tri0 [62:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [31:0] wire_csa_lower_result;
wire [30:0] wire_csa_upper0_result;
wire [30:0] wire_csa_upper1_result;
wire [62:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[31:0]),
.datab(datab[31:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "ADD",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 32,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[62:32]),
.datab(datab[62:32]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "ADD",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 31,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[62:32]),
.datab(datab[62:32]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "ADD",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 31,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({31{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({31{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_double_altfp_log_csa_p0e
//altfp_log_csa CARRY_SELECT="NO" CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=11 dataa datab result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_log 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_altsquare 2010:08:18:21:07:10:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//synthesis_resources = lpm_add_sub 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_double_altfp_log_csa_aoc
(
dataa,
datab,
result) ;
input [10:0] dataa;
input [10:0] datab;
output [10:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [10:0] dataa;
tri0 [10:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [10:0] wire_add_sub1_result;
wire [10:0] result_w;
lpm_add_sub add_sub1
(
.cout(),
.dataa(dataa),
.datab(datab),
.overflow(),
.result(wire_add_sub1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub1.lpm_direction = "SUB",
add_sub1.lpm_representation = "UNSIGNED",
add_sub1.lpm_width = 11,
add_sub1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = wire_add_sub1_result;
endmodule //acl_fp_log_double_altfp_log_csa_aoc
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=26 dataa datab result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_log 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_altsquare 2010:08:18:21:07:10:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_double_altfp_log_csa_i4b
(
dataa,
datab,
result) ;
input [25:0] dataa;
input [25:0] datab;
output [25:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [25:0] dataa;
tri0 [25:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [12:0] wire_csa_lower_result;
wire [12:0] wire_csa_upper0_result;
wire [12:0] wire_csa_upper1_result;
wire [25:0] result_w;
lpm_add_sub csa_lower
(
.cout(wire_csa_lower_cout),
.dataa(dataa[12:0]),
.datab(datab[12:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "SUB",
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 13,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.cin(1'b0),
.cout(),
.dataa(dataa[25:13]),
.datab(datab[25:13]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "SUB",
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 13,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.cin(1'b1),
.cout(),
.dataa(dataa[25:13]),
.datab(datab[25:13]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "SUB",
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 13,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({13{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({13{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_double_altfp_log_csa_i4b
//altfp_log_csa CARRY_SELECT="NO" CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=7 dataa datab result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_log 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_altsquare 2010:08:18:21:07:10:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//synthesis_resources = lpm_add_sub 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_double_altfp_log_csa_vmc
(
dataa,
datab,
result) ;
input [6:0] dataa;
input [6:0] datab;
output [6:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [6:0] dataa;
tri0 [6:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [6:0] wire_add_sub2_result;
wire [6:0] result_w;
lpm_add_sub add_sub2
(
.cout(),
.dataa(dataa),
.datab(datab),
.overflow(),
.result(wire_add_sub2_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub2.lpm_direction = "SUB",
add_sub2.lpm_representation = "UNSIGNED",
add_sub2.lpm_width = 7,
add_sub2.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = wire_add_sub2_result;
endmodule //acl_fp_log_double_altfp_log_csa_vmc
//altfp_log_csa CARRY_SELECT="NO" CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=55 aclr clken clock dataa datab result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_log 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_altsquare 2010:08:18:21:07:10:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//synthesis_resources = lpm_add_sub 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_double_altfp_log_csa_plf
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [54:0] dataa;
input [54:0] datab;
output [54:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [54:0] dataa;
tri0 [54:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [54:0] wire_add_sub3_result;
wire [54:0] result_w;
lpm_add_sub add_sub3
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa),
.datab(datab),
.overflow(),
.result(wire_add_sub3_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub3.lpm_direction = "SUB",
add_sub3.lpm_pipeline = 1,
add_sub3.lpm_representation = "UNSIGNED",
add_sub3.lpm_width = 55,
add_sub3.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = wire_add_sub3_result;
endmodule //acl_fp_log_double_altfp_log_csa_plf
//altfp_log_csa CARRY_SELECT="NO" CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_PIPELINE=2 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=11 aclr clken clock dataa datab result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_log 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_altsquare 2010:08:18:21:07:10:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//synthesis_resources = lpm_add_sub 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_double_altfp_log_csa_ilf
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [10:0] dataa;
input [10:0] datab;
output [10:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [10:0] dataa;
tri0 [10:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [10:0] wire_add_sub4_result;
wire [10:0] result_w;
lpm_add_sub add_sub4
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa),
.datab(datab),
.overflow(),
.result(wire_add_sub4_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub4.lpm_direction = "SUB",
add_sub4.lpm_pipeline = 2,
add_sub4.lpm_representation = "UNSIGNED",
add_sub4.lpm_width = 11,
add_sub4.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = wire_add_sub4_result;
endmodule //acl_fp_log_double_altfp_log_csa_ilf
//altfp_log_rr_block CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" WIDTH_ALMOSTLOG=83 WIDTH_Y0=54 WIDTH_Z=55 a0_in aclr almostlog clk_en clock y0_in z
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_log 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_altsquare 2010:08:18:21:07:10:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="ADD" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=60 aclr clken clock dataa datab result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_log 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_altsquare 2010:08:18:21:07:10:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_double_altfp_log_csa_m0e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [59:0] dataa;
input [59:0] datab;
output [59:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [59:0] dataa;
tri0 [59:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [29:0] wire_csa_lower_result;
wire [29:0] wire_csa_upper0_result;
wire [29:0] wire_csa_upper1_result;
wire [59:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[29:0]),
.datab(datab[29:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "ADD",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 30,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[59:30]),
.datab(datab[59:30]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "ADD",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 30,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[59:30]),
.datab(datab[59:30]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "ADD",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 30,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({30{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({30{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_double_altfp_log_csa_m0e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="ADD" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=69 aclr clken clock dataa datab result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_log 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_altsquare 2010:08:18:21:07:10:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_double_altfp_log_csa_v0e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [68:0] dataa;
input [68:0] datab;
output [68:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [68:0] dataa;
tri0 [68:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [34:0] wire_csa_lower_result;
wire [33:0] wire_csa_upper0_result;
wire [33:0] wire_csa_upper1_result;
wire [68:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[34:0]),
.datab(datab[34:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "ADD",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 35,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[68:35]),
.datab(datab[68:35]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "ADD",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 34,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[68:35]),
.datab(datab[68:35]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "ADD",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 34,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({34{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({34{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_double_altfp_log_csa_v0e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="ADD" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=70 aclr clken clock dataa datab result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_log 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_altsquare 2010:08:18:21:07:10:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_double_altfp_log_csa_n0e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [69:0] dataa;
input [69:0] datab;
output [69:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [69:0] dataa;
tri0 [69:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [34:0] wire_csa_lower_result;
wire [34:0] wire_csa_upper0_result;
wire [34:0] wire_csa_upper1_result;
wire [69:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[34:0]),
.datab(datab[34:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "ADD",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 35,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[69:35]),
.datab(datab[69:35]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "ADD",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 35,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[69:35]),
.datab(datab[69:35]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "ADD",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 35,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({35{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({35{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_double_altfp_log_csa_n0e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="ADD" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=67 aclr clken clock dataa datab result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_log 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_altsquare 2010:08:18:21:07:10:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_double_altfp_log_csa_t0e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [66:0] dataa;
input [66:0] datab;
output [66:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [66:0] dataa;
tri0 [66:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [33:0] wire_csa_lower_result;
wire [32:0] wire_csa_upper0_result;
wire [32:0] wire_csa_upper1_result;
wire [66:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[33:0]),
.datab(datab[33:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "ADD",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 34,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[66:34]),
.datab(datab[66:34]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "ADD",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 33,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[66:34]),
.datab(datab[66:34]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "ADD",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 33,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({33{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({33{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_double_altfp_log_csa_t0e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="ADD" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=64 aclr clken clock dataa datab result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_log 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_altsquare 2010:08:18:21:07:10:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_double_altfp_log_csa_q0e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [63:0] dataa;
input [63:0] datab;
output [63:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [63:0] dataa;
tri0 [63:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [31:0] wire_csa_lower_result;
wire [31:0] wire_csa_upper0_result;
wire [31:0] wire_csa_upper1_result;
wire [63:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[31:0]),
.datab(datab[31:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "ADD",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 32,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[63:32]),
.datab(datab[63:32]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "ADD",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 32,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[63:32]),
.datab(datab[63:32]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "ADD",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 32,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({32{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({32{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_double_altfp_log_csa_q0e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="ADD" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=61 aclr clken clock dataa datab result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_log 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_altsquare 2010:08:18:21:07:10:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_double_altfp_log_csa_o0e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [60:0] dataa;
input [60:0] datab;
output [60:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [60:0] dataa;
tri0 [60:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [30:0] wire_csa_lower_result;
wire [29:0] wire_csa_upper0_result;
wire [29:0] wire_csa_upper1_result;
wire [60:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[30:0]),
.datab(datab[30:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "ADD",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 31,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[60:31]),
.datab(datab[60:31]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "ADD",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 30,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[60:31]),
.datab(datab[60:31]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "ADD",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 30,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({30{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({30{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_double_altfp_log_csa_o0e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="ADD" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=58 aclr clken clock dataa datab result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_log 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_altsquare 2010:08:18:21:07:10:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_double_altfp_log_csa_u0e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [57:0] dataa;
input [57:0] datab;
output [57:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [57:0] dataa;
tri0 [57:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [28:0] wire_csa_lower_result;
wire [28:0] wire_csa_upper0_result;
wire [28:0] wire_csa_upper1_result;
wire [57:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[28:0]),
.datab(datab[28:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "ADD",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 29,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[57:29]),
.datab(datab[57:29]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "ADD",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 29,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[57:29]),
.datab(datab[57:29]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "ADD",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 29,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({29{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({29{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_double_altfp_log_csa_u0e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="ADD" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=55 aclr clken clock dataa datab result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_log 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_altsquare 2010:08:18:21:07:10:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_double_altfp_log_csa_s0e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [54:0] dataa;
input [54:0] datab;
output [54:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [54:0] dataa;
tri0 [54:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [27:0] wire_csa_lower_result;
wire [26:0] wire_csa_upper0_result;
wire [26:0] wire_csa_upper1_result;
wire [54:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[27:0]),
.datab(datab[27:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "ADD",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 28,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[54:28]),
.datab(datab[54:28]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "ADD",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 27,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[54:28]),
.datab(datab[54:28]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "ADD",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 27,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({27{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({27{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_double_altfp_log_csa_s0e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=60 aclr clken clock dataa datab result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_log 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_altsquare 2010:08:18:21:07:10:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_double_altfp_log_csa_n1e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [59:0] dataa;
input [59:0] datab;
output [59:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [59:0] dataa;
tri0 [59:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [29:0] wire_csa_lower_result;
wire [29:0] wire_csa_upper0_result;
wire [29:0] wire_csa_upper1_result;
wire [59:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[29:0]),
.datab(datab[29:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "SUB",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 30,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[59:30]),
.datab(datab[59:30]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "SUB",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 30,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[59:30]),
.datab(datab[59:30]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "SUB",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 30,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({30{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({30{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_double_altfp_log_csa_n1e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=69 aclr clken clock dataa datab result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_log 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_altsquare 2010:08:18:21:07:10:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_double_altfp_log_csa_02e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [68:0] dataa;
input [68:0] datab;
output [68:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [68:0] dataa;
tri0 [68:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [34:0] wire_csa_lower_result;
wire [33:0] wire_csa_upper0_result;
wire [33:0] wire_csa_upper1_result;
wire [68:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[34:0]),
.datab(datab[34:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "SUB",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 35,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[68:35]),
.datab(datab[68:35]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "SUB",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 34,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[68:35]),
.datab(datab[68:35]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "SUB",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 34,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({34{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({34{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_double_altfp_log_csa_02e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=70 aclr clken clock dataa datab result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_log 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_altsquare 2010:08:18:21:07:10:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_double_altfp_log_csa_o1e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [69:0] dataa;
input [69:0] datab;
output [69:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [69:0] dataa;
tri0 [69:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [34:0] wire_csa_lower_result;
wire [34:0] wire_csa_upper0_result;
wire [34:0] wire_csa_upper1_result;
wire [69:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[34:0]),
.datab(datab[34:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "SUB",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 35,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[69:35]),
.datab(datab[69:35]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "SUB",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 35,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[69:35]),
.datab(datab[69:35]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "SUB",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 35,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({35{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({35{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_double_altfp_log_csa_o1e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=67 aclr clken clock dataa datab result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_log 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_altsquare 2010:08:18:21:07:10:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_double_altfp_log_csa_u1e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [66:0] dataa;
input [66:0] datab;
output [66:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [66:0] dataa;
tri0 [66:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [33:0] wire_csa_lower_result;
wire [32:0] wire_csa_upper0_result;
wire [32:0] wire_csa_upper1_result;
wire [66:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[33:0]),
.datab(datab[33:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "SUB",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 34,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[66:34]),
.datab(datab[66:34]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "SUB",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 33,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[66:34]),
.datab(datab[66:34]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "SUB",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 33,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({33{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({33{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_double_altfp_log_csa_u1e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=64 aclr clken clock dataa datab result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_log 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_altsquare 2010:08:18:21:07:10:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_double_altfp_log_csa_r1e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [63:0] dataa;
input [63:0] datab;
output [63:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [63:0] dataa;
tri0 [63:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [31:0] wire_csa_lower_result;
wire [31:0] wire_csa_upper0_result;
wire [31:0] wire_csa_upper1_result;
wire [63:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[31:0]),
.datab(datab[31:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "SUB",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 32,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[63:32]),
.datab(datab[63:32]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "SUB",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 32,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[63:32]),
.datab(datab[63:32]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "SUB",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 32,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({32{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({32{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_double_altfp_log_csa_r1e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=61 aclr clken clock dataa datab result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_log 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_altsquare 2010:08:18:21:07:10:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_double_altfp_log_csa_p1e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [60:0] dataa;
input [60:0] datab;
output [60:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [60:0] dataa;
tri0 [60:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [30:0] wire_csa_lower_result;
wire [29:0] wire_csa_upper0_result;
wire [29:0] wire_csa_upper1_result;
wire [60:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[30:0]),
.datab(datab[30:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "SUB",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 31,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[60:31]),
.datab(datab[60:31]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "SUB",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 30,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[60:31]),
.datab(datab[60:31]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "SUB",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 30,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({30{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({30{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_double_altfp_log_csa_p1e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=58 aclr clken clock dataa datab result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_log 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_altsquare 2010:08:18:21:07:10:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_double_altfp_log_csa_v1e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [57:0] dataa;
input [57:0] datab;
output [57:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [57:0] dataa;
tri0 [57:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [28:0] wire_csa_lower_result;
wire [28:0] wire_csa_upper0_result;
wire [28:0] wire_csa_upper1_result;
wire [57:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[28:0]),
.datab(datab[28:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "SUB",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 29,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[57:29]),
.datab(datab[57:29]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "SUB",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 29,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[57:29]),
.datab(datab[57:29]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "SUB",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 29,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({29{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({29{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_double_altfp_log_csa_v1e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=55 aclr clken clock dataa datab result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_log 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_altsquare 2010:08:18:21:07:10:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_double_altfp_log_csa_s1e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [54:0] dataa;
input [54:0] datab;
output [54:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [54:0] dataa;
tri0 [54:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [27:0] wire_csa_lower_result;
wire [26:0] wire_csa_upper0_result;
wire [26:0] wire_csa_upper1_result;
wire [54:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[27:0]),
.datab(datab[27:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "SUB",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 28,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[54:28]),
.datab(datab[54:28]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "SUB",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 27,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[54:28]),
.datab(datab[54:28]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "SUB",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 27,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({27{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({27{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_double_altfp_log_csa_s1e
//synthesis_resources = lpm_add_sub 72 lpm_mult 9 lpm_mux 10 reg 2344
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_double_range_reduction_cvd
(
a0_in,
aclr,
almostlog,
clk_en,
clock,
y0_in,
z) ;
input [4:0] a0_in;
input aclr;
output [82:0] almostlog;
input clk_en;
input clock;
input [53:0] y0_in;
output [54:0] z;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clk_en;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [82:0] wire_add0_1_result;
wire [82:0] wire_add0_2_result;
wire [82:0] wire_add0_3_result;
wire [82:0] wire_add0_4_result;
wire [82:0] wire_add0_5_result;
wire [82:0] wire_add0_6_result;
wire [82:0] wire_add0_7_result;
wire [82:0] wire_add0_8_result;
wire [59:0] wire_add1_1_result;
wire [68:0] wire_add1_2_result;
wire [69:0] wire_add1_3_result;
wire [66:0] wire_add1_4_result;
wire [63:0] wire_add1_5_result;
wire [60:0] wire_add1_6_result;
wire [57:0] wire_add1_7_result;
wire [54:0] wire_add1_8_result;
wire [59:0] wire_sub1_1_result;
wire [68:0] wire_sub1_2_result;
wire [69:0] wire_sub1_3_result;
wire [66:0] wire_sub1_4_result;
wire [63:0] wire_sub1_5_result;
wire [60:0] wire_sub1_6_result;
wire [57:0] wire_sub1_7_result;
wire [54:0] wire_sub1_8_result;
reg [4:0] A_pipe0_reg0;
reg [4:0] A_pipe0_reg1;
reg [3:0] A_wire1_reg0;
reg [3:0] A_wire2_reg0;
reg [3:0] A_wire3_reg0;
reg [3:0] A_wire4_reg0;
reg [3:0] A_wire5_reg0;
reg [3:0] A_wire6_reg0;
reg [3:0] A_wire7_reg0;
reg [3:0] A_wire8_reg0;
reg [49:0] B_wire1_reg0;
reg [55:0] B_wire2_reg0;
reg [64:0] B_wire3_reg0;
reg [65:0] B_wire4_reg0;
reg [62:0] B_wire5_reg0;
reg [59:0] B_wire6_reg0;
reg [56:0] B_wire7_reg0;
reg [53:0] B_wire8_reg0;
reg [82:0] S_pipe22_reg0;
reg [82:0] S_pipe23_reg0;
reg [82:0] S_pipe24_reg0;
reg [82:0] S_pipe25_reg0;
reg [82:0] S_pipe26_reg0;
reg [82:0] S_pipe27_reg0;
reg [82:0] S_pipe28_reg0;
reg [82:0] S_pipe29_reg0;
reg [82:0] S_wire1_reg0;
reg [82:0] S_wire2_reg0;
reg [82:0] S_wire3_reg0;
reg [82:0] S_wire4_reg0;
reg [82:0] S_wire5_reg0;
reg [82:0] S_wire6_reg0;
reg [82:0] S_wire7_reg0;
reg [82:0] S_wire8_reg0;
reg [53:0] Z_wire1_reg0;
reg [59:0] Z_wire2_reg0;
reg [68:0] Z_wire3_reg0;
reg [69:0] Z_wire4_reg0;
reg [66:0] Z_wire5_reg0;
reg [63:0] Z_wire6_reg0;
reg [60:0] Z_wire7_reg0;
reg [57:0] Z_wire8_reg0;
wire [59:0] wire_mult0_result;
wire [57:0] wire_mult1_result;
wire [63:0] wire_mult2_result;
wire [66:0] wire_mult3_result;
wire [60:0] wire_mult4_result;
wire [54:0] wire_mult5_result;
wire [48:0] wire_mult6_result;
wire [42:0] wire_mult7_result;
wire [36:0] wire_mult8_result;
wire [5:0] wire_InvTable0_result;
wire [82:0] wire_LogTable0_result;
wire [78:0] wire_LogTable1_result;
wire [75:0] wire_LogTable2_result;
wire [72:0] wire_LogTable3_result;
wire [69:0] wire_LogTable4_result;
wire [66:0] wire_LogTable5_result;
wire [63:0] wire_LogTable6_result;
wire [60:0] wire_LogTable7_result;
wire [57:0] wire_LogTable8_result;
wire [3:0] A1_is_all_zero;
wire [3:0] A1_is_not_zero;
wire [3:0] A_all_zero2;
wire [3:0] A_all_zero3;
wire [3:0] A_all_zero4;
wire [3:0] A_all_zero5;
wire [3:0] A_all_zero6;
wire [3:0] A_all_zero7;
wire [3:0] A_all_zero8;
wire [4:0] A_pipe0;
wire [3:0] A_pipe11;
wire [3:0] A_pipe12;
wire [3:0] A_pipe13;
wire [3:0] A_pipe14;
wire [3:0] A_pipe15;
wire [3:0] A_pipe16;
wire [3:0] A_pipe17;
wire [3:0] A_pipe18;
wire [4:0] A_wire0;
wire [3:0] A_wire1;
wire [3:0] A_wire2;
wire [3:0] A_wire3;
wire [3:0] A_wire4;
wire [3:0] A_wire5;
wire [3:0] A_wire6;
wire [3:0] A_wire7;
wire [3:0] A_wire8;
wire [59:0] B_pad_wire1;
wire [68:0] B_pad_wire2;
wire [69:0] B_pad_wire3;
wire [66:0] B_pad_wire4;
wire [63:0] B_pad_wire5;
wire [60:0] B_pad_wire6;
wire [57:0] B_pad_wire7;
wire [54:0] B_pad_wire8;
wire [49:0] B_pipe1;
wire [55:0] B_pipe2;
wire [64:0] B_pipe3;
wire [65:0] B_pipe4;
wire [62:0] B_pipe5;
wire [59:0] B_pipe6;
wire [56:0] B_pipe7;
wire [53:0] B_pipe8;
wire [49:0] B_wire1;
wire [55:0] B_wire2;
wire [64:0] B_wire3;
wire [65:0] B_wire4;
wire [62:0] B_wire5;
wire [59:0] B_wire6;
wire [56:0] B_wire7;
wire [53:0] B_wire8;
wire [59:0] epsZ_pad_wire1;
wire [68:0] epsZ_pad_wire2;
wire [69:0] epsZ_pad_wire3;
wire [66:0] epsZ_pad_wire4;
wire [63:0] epsZ_pad_wire5;
wire [60:0] epsZ_pad_wire6;
wire [57:0] epsZ_pad_wire7;
wire [54:0] epsZ_pad_wire8;
wire [59:0] epsZ_wire1;
wire [68:0] epsZ_wire2;
wire [80:0] epsZ_wire3;
wire [84:0] epsZ_wire4;
wire [84:0] epsZ_wire5;
wire [84:0] epsZ_wire6;
wire [84:0] epsZ_wire7;
wire [84:0] epsZ_wire8;
wire [5:0] InvA0;
wire [82:0] L_wire0;
wire [78:0] L_wire1;
wire [75:0] L_wire2;
wire [72:0] L_wire3;
wire [69:0] L_wire4;
wire [66:0] L_wire5;
wire [63:0] L_wire6;
wire [60:0] L_wire7;
wire [57:0] L_wire8;
wire [59:0] mux0_data0;
wire [59:0] mux0_data1;
wire [59:0] P_pad_wire1;
wire [68:0] P_pad_wire2;
wire [69:0] P_pad_wire3;
wire [66:0] P_pad_wire4;
wire [63:0] P_pad_wire5;
wire [60:0] P_pad_wire6;
wire [57:0] P_pad_wire7;
wire [54:0] P_pad_wire8;
wire [59:0] P_wire0;
wire [57:0] P_wire1;
wire [63:0] P_wire2;
wire [66:0] P_wire3;
wire [60:0] P_wire4;
wire [54:0] P_wire5;
wire [48:0] P_wire6;
wire [42:0] P_wire7;
wire [36:0] P_wire8;
wire [82:0] S_pipe11;
wire [82:0] S_pipe12;
wire [82:0] S_pipe13;
wire [82:0] S_pipe14;
wire [82:0] S_pipe15;
wire [82:0] S_pipe16;
wire [82:0] S_pipe17;
wire [82:0] S_pipe18;
wire [82:0] S_pipe22;
wire [82:0] S_pipe23;
wire [82:0] S_pipe24;
wire [82:0] S_pipe25;
wire [82:0] S_pipe26;
wire [82:0] S_pipe27;
wire [82:0] S_pipe28;
wire [82:0] S_pipe29;
wire [82:0] S_wire1;
wire [82:0] S_wire2;
wire [82:0] S_wire3;
wire [82:0] S_wire4;
wire [82:0] S_wire5;
wire [82:0] S_wire6;
wire [82:0] S_wire7;
wire [82:0] S_wire8;
wire [82:0] S_wire9;
wire [53:0] Z_pipe1;
wire [59:0] Z_pipe2;
wire [68:0] Z_pipe3;
wire [69:0] Z_pipe4;
wire [66:0] Z_pipe5;
wire [63:0] Z_pipe6;
wire [60:0] Z_pipe7;
wire [57:0] Z_pipe8;
wire [53:0] Z_wire1;
wire [59:0] Z_wire2;
wire [68:0] Z_wire3;
wire [69:0] Z_wire4;
wire [66:0] Z_wire5;
wire [63:0] Z_wire6;
wire [60:0] Z_wire7;
wire [57:0] Z_wire8;
wire [54:0] Z_wire9;
wire [53:0] ZM_wire1;
wire [59:0] ZM_wire2;
wire [62:0] ZM_wire3;
wire [56:0] ZM_wire4;
wire [50:0] ZM_wire5;
wire [44:0] ZM_wire6;
wire [38:0] ZM_wire7;
wire [32:0] ZM_wire8;
acl_fp_log_double_altfp_log_csa_r0e add0_1
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(S_pipe11),
.datab({{4{1'b0}}, L_wire1}),
.result(wire_add0_1_result));
acl_fp_log_double_altfp_log_csa_r0e add0_2
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(S_pipe12),
.datab({{7{1'b0}}, L_wire2}),
.result(wire_add0_2_result));
acl_fp_log_double_altfp_log_csa_r0e add0_3
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(S_pipe13),
.datab({{10{1'b0}}, L_wire3}),
.result(wire_add0_3_result));
acl_fp_log_double_altfp_log_csa_r0e add0_4
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(S_pipe14),
.datab({{13{1'b0}}, L_wire4}),
.result(wire_add0_4_result));
acl_fp_log_double_altfp_log_csa_r0e add0_5
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(S_pipe15),
.datab({{16{1'b0}}, L_wire5}),
.result(wire_add0_5_result));
acl_fp_log_double_altfp_log_csa_r0e add0_6
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(S_pipe16),
.datab({{19{1'b0}}, L_wire6}),
.result(wire_add0_6_result));
acl_fp_log_double_altfp_log_csa_r0e add0_7
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(S_pipe17),
.datab({{22{1'b0}}, L_wire7}),
.result(wire_add0_7_result));
acl_fp_log_double_altfp_log_csa_r0e add0_8
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(S_pipe18),
.datab({{25{1'b0}}, L_wire8}),
.result(wire_add0_8_result));
acl_fp_log_double_altfp_log_csa_m0e add1_1
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(B_pad_wire1),
.datab(epsZ_pad_wire1),
.result(wire_add1_1_result));
acl_fp_log_double_altfp_log_csa_v0e add1_2
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(B_pad_wire2),
.datab(epsZ_pad_wire2),
.result(wire_add1_2_result));
acl_fp_log_double_altfp_log_csa_n0e add1_3
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(B_pad_wire3),
.datab(epsZ_pad_wire3),
.result(wire_add1_3_result));
acl_fp_log_double_altfp_log_csa_t0e add1_4
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(B_pad_wire4),
.datab(epsZ_pad_wire4),
.result(wire_add1_4_result));
acl_fp_log_double_altfp_log_csa_q0e add1_5
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(B_pad_wire5),
.datab(epsZ_pad_wire5),
.result(wire_add1_5_result));
acl_fp_log_double_altfp_log_csa_o0e add1_6
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(B_pad_wire6),
.datab(epsZ_pad_wire6),
.result(wire_add1_6_result));
acl_fp_log_double_altfp_log_csa_u0e add1_7
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(B_pad_wire7),
.datab(epsZ_pad_wire7),
.result(wire_add1_7_result));
acl_fp_log_double_altfp_log_csa_s0e add1_8
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(B_pad_wire8),
.datab(epsZ_pad_wire8),
.result(wire_add1_8_result));
acl_fp_log_double_altfp_log_csa_n1e sub1_1
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(wire_add1_1_result),
.datab(P_pad_wire1),
.result(wire_sub1_1_result));
acl_fp_log_double_altfp_log_csa_02e sub1_2
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(wire_add1_2_result),
.datab(P_pad_wire2),
.result(wire_sub1_2_result));
acl_fp_log_double_altfp_log_csa_o1e sub1_3
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(wire_add1_3_result),
.datab(P_pad_wire3),
.result(wire_sub1_3_result));
acl_fp_log_double_altfp_log_csa_u1e sub1_4
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(wire_add1_4_result),
.datab(P_pad_wire4),
.result(wire_sub1_4_result));
acl_fp_log_double_altfp_log_csa_r1e sub1_5
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(wire_add1_5_result),
.datab(P_pad_wire5),
.result(wire_sub1_5_result));
acl_fp_log_double_altfp_log_csa_p1e sub1_6
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(wire_add1_6_result),
.datab(P_pad_wire6),
.result(wire_sub1_6_result));
acl_fp_log_double_altfp_log_csa_v1e sub1_7
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(wire_add1_7_result),
.datab(P_pad_wire7),
.result(wire_sub1_7_result));
acl_fp_log_double_altfp_log_csa_s1e sub1_8
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(wire_add1_8_result),
.datab(P_pad_wire8),
.result(wire_sub1_8_result));
// synopsys translate_off
initial
A_pipe0_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) A_pipe0_reg0 <= 5'b0;
else if (clk_en == 1'b1) A_pipe0_reg0 <= A_pipe0;
// synopsys translate_off
initial
A_pipe0_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) A_pipe0_reg1 <= 5'b0;
else if (clk_en == 1'b1) A_pipe0_reg1 <= A_pipe0_reg0;
// synopsys translate_off
initial
A_wire1_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) A_wire1_reg0 <= 4'b0;
else if (clk_en == 1'b1) A_wire1_reg0 <= A_wire1;
// synopsys translate_off
initial
A_wire2_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) A_wire2_reg0 <= 4'b0;
else if (clk_en == 1'b1) A_wire2_reg0 <= A_wire2;
// synopsys translate_off
initial
A_wire3_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) A_wire3_reg0 <= 4'b0;
else if (clk_en == 1'b1) A_wire3_reg0 <= A_wire3;
// synopsys translate_off
initial
A_wire4_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) A_wire4_reg0 <= 4'b0;
else if (clk_en == 1'b1) A_wire4_reg0 <= A_wire4;
// synopsys translate_off
initial
A_wire5_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) A_wire5_reg0 <= 4'b0;
else if (clk_en == 1'b1) A_wire5_reg0 <= A_wire5;
// synopsys translate_off
initial
A_wire6_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) A_wire6_reg0 <= 4'b0;
else if (clk_en == 1'b1) A_wire6_reg0 <= A_wire6;
// synopsys translate_off
initial
A_wire7_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) A_wire7_reg0 <= 4'b0;
else if (clk_en == 1'b1) A_wire7_reg0 <= A_wire7;
// synopsys translate_off
initial
A_wire8_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) A_wire8_reg0 <= 4'b0;
else if (clk_en == 1'b1) A_wire8_reg0 <= A_wire8;
// synopsys translate_off
initial
B_wire1_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) B_wire1_reg0 <= 50'b0;
else if (clk_en == 1'b1) B_wire1_reg0 <= B_wire1;
// synopsys translate_off
initial
B_wire2_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) B_wire2_reg0 <= 56'b0;
else if (clk_en == 1'b1) B_wire2_reg0 <= B_wire2;
// synopsys translate_off
initial
B_wire3_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) B_wire3_reg0 <= 65'b0;
else if (clk_en == 1'b1) B_wire3_reg0 <= B_wire3;
// synopsys translate_off
initial
B_wire4_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) B_wire4_reg0 <= 66'b0;
else if (clk_en == 1'b1) B_wire4_reg0 <= B_wire4;
// synopsys translate_off
initial
B_wire5_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) B_wire5_reg0 <= 63'b0;
else if (clk_en == 1'b1) B_wire5_reg0 <= B_wire5;
// synopsys translate_off
initial
B_wire6_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) B_wire6_reg0 <= 60'b0;
else if (clk_en == 1'b1) B_wire6_reg0 <= B_wire6;
// synopsys translate_off
initial
B_wire7_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) B_wire7_reg0 <= 57'b0;
else if (clk_en == 1'b1) B_wire7_reg0 <= B_wire7;
// synopsys translate_off
initial
B_wire8_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) B_wire8_reg0 <= 54'b0;
else if (clk_en == 1'b1) B_wire8_reg0 <= B_wire8;
// synopsys translate_off
initial
S_pipe22_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_pipe22_reg0 <= 83'b0;
else if (clk_en == 1'b1) S_pipe22_reg0 <= S_pipe22;
// synopsys translate_off
initial
S_pipe23_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_pipe23_reg0 <= 83'b0;
else if (clk_en == 1'b1) S_pipe23_reg0 <= S_pipe23;
// synopsys translate_off
initial
S_pipe24_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_pipe24_reg0 <= 83'b0;
else if (clk_en == 1'b1) S_pipe24_reg0 <= S_pipe24;
// synopsys translate_off
initial
S_pipe25_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_pipe25_reg0 <= 83'b0;
else if (clk_en == 1'b1) S_pipe25_reg0 <= S_pipe25;
// synopsys translate_off
initial
S_pipe26_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_pipe26_reg0 <= 83'b0;
else if (clk_en == 1'b1) S_pipe26_reg0 <= S_pipe26;
// synopsys translate_off
initial
S_pipe27_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_pipe27_reg0 <= 83'b0;
else if (clk_en == 1'b1) S_pipe27_reg0 <= S_pipe27;
// synopsys translate_off
initial
S_pipe28_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_pipe28_reg0 <= 83'b0;
else if (clk_en == 1'b1) S_pipe28_reg0 <= S_pipe28;
// synopsys translate_off
initial
S_pipe29_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_pipe29_reg0 <= 83'b0;
else if (clk_en == 1'b1) S_pipe29_reg0 <= S_pipe29;
// synopsys translate_off
initial
S_wire1_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_wire1_reg0 <= 83'b0;
else if (clk_en == 1'b1) S_wire1_reg0 <= S_wire1;
// synopsys translate_off
initial
S_wire2_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_wire2_reg0 <= 83'b0;
else if (clk_en == 1'b1) S_wire2_reg0 <= S_wire2;
// synopsys translate_off
initial
S_wire3_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_wire3_reg0 <= 83'b0;
else if (clk_en == 1'b1) S_wire3_reg0 <= S_wire3;
// synopsys translate_off
initial
S_wire4_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_wire4_reg0 <= 83'b0;
else if (clk_en == 1'b1) S_wire4_reg0 <= S_wire4;
// synopsys translate_off
initial
S_wire5_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_wire5_reg0 <= 83'b0;
else if (clk_en == 1'b1) S_wire5_reg0 <= S_wire5;
// synopsys translate_off
initial
S_wire6_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_wire6_reg0 <= 83'b0;
else if (clk_en == 1'b1) S_wire6_reg0 <= S_wire6;
// synopsys translate_off
initial
S_wire7_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_wire7_reg0 <= 83'b0;
else if (clk_en == 1'b1) S_wire7_reg0 <= S_wire7;
// synopsys translate_off
initial
S_wire8_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_wire8_reg0 <= 83'b0;
else if (clk_en == 1'b1) S_wire8_reg0 <= S_wire8;
// synopsys translate_off
initial
Z_wire1_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Z_wire1_reg0 <= 54'b0;
else if (clk_en == 1'b1) Z_wire1_reg0 <= Z_wire1;
// synopsys translate_off
initial
Z_wire2_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Z_wire2_reg0 <= 60'b0;
else if (clk_en == 1'b1) Z_wire2_reg0 <= Z_wire2;
// synopsys translate_off
initial
Z_wire3_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Z_wire3_reg0 <= 69'b0;
else if (clk_en == 1'b1) Z_wire3_reg0 <= Z_wire3;
// synopsys translate_off
initial
Z_wire4_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Z_wire4_reg0 <= 70'b0;
else if (clk_en == 1'b1) Z_wire4_reg0 <= Z_wire4;
// synopsys translate_off
initial
Z_wire5_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Z_wire5_reg0 <= 67'b0;
else if (clk_en == 1'b1) Z_wire5_reg0 <= Z_wire5;
// synopsys translate_off
initial
Z_wire6_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Z_wire6_reg0 <= 64'b0;
else if (clk_en == 1'b1) Z_wire6_reg0 <= Z_wire6;
// synopsys translate_off
initial
Z_wire7_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Z_wire7_reg0 <= 61'b0;
else if (clk_en == 1'b1) Z_wire7_reg0 <= Z_wire7;
// synopsys translate_off
initial
Z_wire8_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Z_wire8_reg0 <= 58'b0;
else if (clk_en == 1'b1) Z_wire8_reg0 <= Z_wire8;
lpm_mult mult0
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(InvA0),
.datab(y0_in),
.result(wire_mult0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
mult0.lpm_pipeline = 2,
mult0.lpm_representation = "UNSIGNED",
mult0.lpm_widtha = 6,
mult0.lpm_widthb = 54,
mult0.lpm_widthp = 60,
mult0.lpm_type = "lpm_mult";
lpm_mult mult1
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(A_wire1),
.datab(ZM_wire1),
.result(wire_mult1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
mult1.lpm_pipeline = 2,
mult1.lpm_representation = "UNSIGNED",
mult1.lpm_widtha = 4,
mult1.lpm_widthb = 54,
mult1.lpm_widthp = 58,
mult1.lpm_type = "lpm_mult";
lpm_mult mult2
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(A_wire2),
.datab(ZM_wire2),
.result(wire_mult2_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
mult2.lpm_pipeline = 2,
mult2.lpm_representation = "UNSIGNED",
mult2.lpm_widtha = 4,
mult2.lpm_widthb = 60,
mult2.lpm_widthp = 64,
mult2.lpm_type = "lpm_mult";
lpm_mult mult3
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(A_wire3),
.datab(ZM_wire3),
.result(wire_mult3_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
mult3.lpm_pipeline = 2,
mult3.lpm_representation = "UNSIGNED",
mult3.lpm_widtha = 4,
mult3.lpm_widthb = 63,
mult3.lpm_widthp = 67,
mult3.lpm_type = "lpm_mult";
lpm_mult mult4
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(A_wire4),
.datab(ZM_wire4),
.result(wire_mult4_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
mult4.lpm_pipeline = 2,
mult4.lpm_representation = "UNSIGNED",
mult4.lpm_widtha = 4,
mult4.lpm_widthb = 57,
mult4.lpm_widthp = 61,
mult4.lpm_type = "lpm_mult";
lpm_mult mult5
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(A_wire5),
.datab(ZM_wire5),
.result(wire_mult5_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
mult5.lpm_pipeline = 2,
mult5.lpm_representation = "UNSIGNED",
mult5.lpm_widtha = 4,
mult5.lpm_widthb = 51,
mult5.lpm_widthp = 55,
mult5.lpm_type = "lpm_mult";
lpm_mult mult6
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(A_wire6),
.datab(ZM_wire6),
.result(wire_mult6_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
mult6.lpm_pipeline = 2,
mult6.lpm_representation = "UNSIGNED",
mult6.lpm_widtha = 4,
mult6.lpm_widthb = 45,
mult6.lpm_widthp = 49,
mult6.lpm_type = "lpm_mult";
lpm_mult mult7
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(A_wire7),
.datab(ZM_wire7),
.result(wire_mult7_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
mult7.lpm_pipeline = 2,
mult7.lpm_representation = "UNSIGNED",
mult7.lpm_widtha = 4,
mult7.lpm_widthb = 39,
mult7.lpm_widthp = 43,
mult7.lpm_type = "lpm_mult";
lpm_mult mult8
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(A_wire8),
.datab(ZM_wire8),
.result(wire_mult8_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
mult8.lpm_pipeline = 2,
mult8.lpm_representation = "UNSIGNED",
mult8.lpm_widtha = 4,
mult8.lpm_widthb = 33,
mult8.lpm_widthp = 37,
mult8.lpm_type = "lpm_mult";
lpm_mux InvTable0
(
.data({6'b100001, {2{6'b100010}}, {2{6'b100011}}, {2{6'b100100}}, 6'b100101, {2{6'b100110}}, 6'b100111, 6'b101000, {2{6'b101001}}, 6'b101010, 6'b101011, 6'b010110, {2{6'b010111}}, {2{6'b011000}}, {2{6'b011001}}, 6'b011010, {2{6'b011011}}, 6'b011100, 6'b011101, 6'b011110, 6'b011111, {2{6'b100000}}}),
.result(wire_InvTable0_result),
.sel(a0_in)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
InvTable0.lpm_size = 32,
InvTable0.lpm_width = 6,
InvTable0.lpm_widths = 5,
InvTable0.lpm_type = "lpm_mux";
lpm_mux LogTable0
(
.data({83'b11111000000111110101100100111100011000011111001100111111111011001100000111000001000, {2{83'b11110000011110101110011110011111111101110100111010101100110011110100000110011011011}}, {2{83'b11101001000011110010110101110101000110101001010010110100011001000001101101100110011}}, {2{83'b11100001110110001111100010010001110101010000110100011010000101100001010101111000001}}, 83'b11011010110101010101101000001111110000000001010110111001011001111111010001000111001, {2{83'b11010100000000011001111100011110101100001101100001011000011011110001100000111100000}}, 83'b11001101010110110100101011000110000101110101001010010111000100110111110110011111001, 83'b11000110111000000001000001110000110010101100101110111100101001111011010001001111111, {2{83'b11000000100011011100111100100101010000111000001110101010111001010101010101110011010}}, 83'b10111010011000101000110101010001010100010110011111000111111100011000110011100000110, 83'b10110100010111000111010100010100011110111000101100111101100011110100110011011011101, 83'b01011111111010111110100011101111011000000101010001101111101101111001101111110110110, {2{83'b01010100100010101011100000011100111000101000111101011111001110000100000010110010011}}, {2{83'b01001001101001011000100001000100110100110110111001001001111000001110111110101101110}}, {2{83'b00111111001100100011100011011001011001110110011011110010111110110011001010000011001}}, 83'b00110101001001111101101001111001000101011011001111000110110111100101011111010100111, {2{83'b00101011011111101000000011010110101010000111101101100011111101110000010100100101110}}, 83'b00100010001011110001110100000100010011111100100011110111101111000110011100010110100, 83'b00011001001100110101111001011101010110010100100110001000101011100001110101011110101, 83'b00010000100001011001100010110101100111100011101000000110100010001010001111111101100, 83'b00001000001000001010111011000100111100111010001000100010001110000000101110011110001, {2{{83{1'b0}}}}}),
.result(wire_LogTable0_result),
.sel(A_wire0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
LogTable0.lpm_size = 32,
LogTable0.lpm_width = 83,
LogTable0.lpm_widths = 5,
LogTable0.lpm_type = "lpm_mux";
lpm_mux LogTable1
(
.data({79'b1110011001011011100111100110111011101101100101100101110000110110111000001001111, 79'b1101010101110111100101101000011111011000100001111110000011010001101010011101110, 79'b1100010010100101010100001010010011111101100110100001100110101000101111101001011, 79'b1011001111100100101001111001011010100101110110101100001000001000001001111100110, 79'b1010001100110101011101101010000101101111000111110100110001100100010100100001000, 79'b1001001010010111100110010111110001101000110000011111010011010111000000010000110, 79'b1000001000001010111011000100111100111010001000100010001110000000101110011110001, 79'b0111000110001111010010111011000001010010101010111100011000110001111111001111010, 79'b0110100101010111110101010010001100010111000100001111110001111011000001101001011, 79'b0101100011110101100001011110000110100100001011110101011111100111000100101011001, 79'b0100100010100011111011000111111110101000101110001001111100011001010000100100110, 79'b0011100001100010111001110000100110001110101111100000110011000000001100010000010, 79'b0010100000110010010100111111001011010000011001011101111100011101010101110100000, 79'b0001100000010010000100100001010001011000011010110101010000001110000010100101110, 79'b0000100000000010000000001010101011101010110001000100111011110011100000110011100, {79{1'b0}}}),
.result(wire_LogTable1_result),
.sel(A_pipe11)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
LogTable1.lpm_size = 16,
LogTable1.lpm_width = 79,
LogTable1.lpm_widths = 4,
LogTable1.lpm_type = "lpm_mux";
lpm_mux LogTable2
(
.data({76'b1110100011010011001111110110100010100111001100001111110101111111001001110100, 76'b1101100010110111000011100000110011011110011000000001100101010100010111011111, 76'b1100100010011100111000111000001001010110011011011110010110000111001001101001, 76'b1011100010000100101111110100011010010111010101011001111111111010110110101110, 76'b1010100001101110101000001101011101011010010000110010101110000000011000110100, 76'b1001100001011010100001111011001010001001011110100101100010011110100100010001, 76'b1000100001001000011100110101011001000000001111100011110111011110011100000010, 76'b0111100000111000011000110100000011001010101110001001111110001111111000010011, 76'b0110100000101010010101101111000010100101111000010110011011111010110110000100, 76'b0101100000011110010011011110010001111111011001100010100011110001101001010111, 76'b0100100000010100010001111001101100110101100100011011101110111000101110000001, 76'b0011100000001100010000111001001111010111001100111101110000111000010101010011, 76'b0010100000000110010000010100110110100011100010001110001001101100110001111100, 76'b0001100000000010010000000100100000001010001000011000010100001001100101101001, 76'b0000100000000000010000000000001010101010110010101010110001000100010110011001, {76{1'b0}}}),
.result(wire_LogTable2_result),
.sel(A_pipe12)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
LogTable2.lpm_size = 16,
LogTable2.lpm_width = 76,
LogTable2.lpm_widths = 4,
LogTable2.lpm_type = "lpm_mux";
lpm_mux LogTable3
(
.data({73'b1110100000011010010010111111100011100010001000011011011101101010000110000, 73'b1101100000010110110010110011010010100001110101001111100011100100101010000, 73'b1100100000010011100010101000101101101010000101111010001111001010011101000, 73'b1011100000010000100010011111101100111001101100010011100100000000010101011, 73'b1010100000001101110010011000001000001111100000010100110000110100010101011, 73'b1001100000001011010010010001110111101010011111111000001001011100010001010, 73'b1000100000001001000010001100110011001001101110111001000000110100011100100, 73'b0111100000000111000010001000110010101100010111010011100010111110011110101, 73'b0110100000000101010010000101101110010001101001000100101111000000001111101, 73'b0101100000000011110010000011011101111000111010001010010001000010111100001, 73'b0100100000000010100010000001111001100001100110100010011100010010010000000, 73'b0011100000000001100010000000111001001011010000001100000100111011101010100, 73'b0010100000000000110010000000010100110101011111000110011010001101110111111, 73'b0001100000000000010010000000000100100000000001010001000000011000010011010, 73'b0000100000000000000010000000000000001010101010101011101010101010110001000, {73{1'b0}}}),
.result(wire_LogTable3_result),
.sel(A_pipe13)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
LogTable3.lpm_size = 16,
LogTable3.lpm_width = 73,
LogTable3.lpm_widths = 4,
LogTable3.lpm_type = "lpm_mux";
lpm_mux LogTable4
(
.data({70'b1110100000000011010010010000111111100001001010111010110111010010001000, 70'b1101100000000010110110010000110011010000110000001110000011100110010110, 70'b1100100000000010011100010000101000101100010110100101101010100001000110, 70'b1011100000000010000100010000011111101011111101110111111011111010011110, 70'b1010100000000001101110010000011000000111100101111011110111101011101101, 70'b1001100000000001011010010000010001110111001110101001001101101111000111, 70'b1000100000000001001000010000001100110010110111111000011101111111111111, 70'b0111100000000000111000010000001000110010100001100010111000011010100010, 70'b0110100000000000101010010000000101101110001011100010011100111011101110, 70'b0101100000000000011110010000000011011101110101110001111011100001010000, 70'b0100100000000000010100010000000001111001100000001100110100001001011100, 70'b0011100000000000001100010000000000111001001010101111010110110011000100, 70'b0010100000000000000110010000000000010100110101010110100011011101011010, 70'b0001100000000000000010010000000000000100100000000000001010001000000000, 70'b0000100000000000000000010000000000000000001010101010101010110010101010, {70{1'b0}}}),
.result(wire_LogTable4_result),
.sel(A_pipe14)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
LogTable4.lpm_size = 16,
LogTable4.lpm_width = 70,
LogTable4.lpm_widths = 4,
LogTable4.lpm_type = "lpm_mux";
lpm_mux LogTable5
(
.data({67'b1110100000000000011010010010000000111111100000111000000010000000101, 67'b1101100000000000010110110010000000110011010000100010000001101111110, 67'b1100100000000000010011100010000000101000101100001100001010000010001, 67'b1011100000000000010000100010000000011111101011110110011001101001111, 67'b1010100000000000001101110010000000011000000111100000101111011110110, 67'b1001100000000000001011010010000000010001110111001011001010011110111, 67'b1000100000000000001001000010000000001100110010110101101001101110010, 67'b0111100000000000000111000010000000001000110010100000001100010111000, 67'b0110100000000000000101010010000000000101101110001010110001101000111, 67'b0101100000000000000011110010000000000011011101110101011000111010000, 67'b0100100000000000000010100010000000000001111001100000000001100110100, 67'b0011100000000000000001100010000000000000111001001010101011010000001, 67'b0010100000000000000000110010000000000000010100110101010101011111000, 67'b0001100000000000000000010010000000000000000100100000000000000001010, 67'b0000100000000000000000000010000000000000000000001010101010101010101, {67{1'b0}}}),
.result(wire_LogTable5_result),
.sel(A_pipe15)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
LogTable5.lpm_size = 16,
LogTable5.lpm_width = 67,
LogTable5.lpm_widths = 4,
LogTable5.lpm_type = "lpm_mux";
lpm_mux LogTable6
(
.data({64'b1110100000000000000011010010010000000000111111100000110101101010, 64'b1101100000000000000010110110010000000000110011010000100000010000, 64'b1100100000000000000010011100010000000000101000101100001010110110, 64'b1011100000000000000010000100010000000000011111101011110101011101, 64'b1010100000000000000001101110010000000000011000000111100000000101, 64'b1001100000000000000001011010010000000000010001110111001010101110, 64'b1000100000000000000001001000010000000000001100110010110101010111, 64'b0111100000000000000000111000010000000000001000110010100000000001, 64'b0110100000000000000000101010010000000000000101101110001010101011, 64'b0101100000000000000000011110010000000000000011011101110101010101, 64'b0100100000000000000000010100010000000000000001111001100000000000, 64'b0011100000000000000000001100010000000000000000111001001010101010, 64'b0010100000000000000000000110010000000000000000010100110101010101, 64'b0001100000000000000000000010010000000000000000000100100000000000, 64'b0000100000000000000000000000010000000000000000000000001010101010, {64{1'b0}}}),
.result(wire_LogTable6_result),
.sel(A_pipe16)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
LogTable6.lpm_size = 16,
LogTable6.lpm_width = 64,
LogTable6.lpm_widths = 4,
LogTable6.lpm_type = "lpm_mux";
lpm_mux LogTable7
(
.data({61'b1110100000000000000000011010010010000000000000111111100000110, 61'b1101100000000000000000010110110010000000000000110011010000100, 61'b1100100000000000000000010011100010000000000000101000101100001, 61'b1011100000000000000000010000100010000000000000011111101011110, 61'b1010100000000000000000001101110010000000000000011000000111100, 61'b1001100000000000000000001011010010000000000000010001110111001, 61'b1000100000000000000000001001000010000000000000001100110010110, 61'b0111100000000000000000000111000010000000000000001000110010100, 61'b0110100000000000000000000101010010000000000000000101101110001, 61'b0101100000000000000000000011110010000000000000000011011101110, 61'b0100100000000000000000000010100010000000000000000001111001100, 61'b0011100000000000000000000001100010000000000000000000111001001, 61'b0010100000000000000000000000110010000000000000000000010100110, 61'b0001100000000000000000000000010010000000000000000000000100100, 61'b0000100000000000000000000000000010000000000000000000000000001, {61{1'b0}}}),
.result(wire_LogTable7_result),
.sel(A_pipe17)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
LogTable7.lpm_size = 16,
LogTable7.lpm_width = 61,
LogTable7.lpm_widths = 4,
LogTable7.lpm_type = "lpm_mux";
lpm_mux LogTable8
(
.data({58'b1110100000000000000000000011010010010000000000000000111111, 58'b1101100000000000000000000010110110010000000000000000110011, 58'b1100100000000000000000000010011100010000000000000000101000, 58'b1011100000000000000000000010000100010000000000000000011111, 58'b1010100000000000000000000001101110010000000000000000011000, 58'b1001100000000000000000000001011010010000000000000000010001, 58'b1000100000000000000000000001001000010000000000000000001100, 58'b0111100000000000000000000000111000010000000000000000001000, 58'b0110100000000000000000000000101010010000000000000000000101, 58'b0101100000000000000000000000011110010000000000000000000011, 58'b0100100000000000000000000000010100010000000000000000000001, 58'b0011100000000000000000000000001100010000000000000000000000, 58'b0010100000000000000000000000000110010000000000000000000000, 58'b0001100000000000000000000000000010010000000000000000000000, 58'b0000100000000000000000000000000000010000000000000000000000, {58{1'b0}}}),
.result(wire_LogTable8_result),
.sel(A_pipe18)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
LogTable8.lpm_size = 16,
LogTable8.lpm_width = 58,
LogTable8.lpm_widths = 4,
LogTable8.lpm_type = "lpm_mux";
assign
A1_is_all_zero = {(A_pipe11[3] | A1_is_all_zero[2]), (A_pipe11[2] | A1_is_all_zero[1]), (A_pipe11[1] | A1_is_all_zero[0]), A_pipe11[0]},
A1_is_not_zero = {((~ A_pipe11[3]) & A1_is_not_zero[2]), (A_pipe11[2] | A1_is_not_zero[1]), (A_pipe11[1] | A1_is_not_zero[0]), A_pipe11[0]},
A_all_zero2 = {((~ A_pipe12[3]) & A_all_zero2[2]), ((~ A_pipe12[2]) & A_all_zero2[1]), ((~ A_pipe12[1]) & A_all_zero2[0]), (~ A_pipe12[0])},
A_all_zero3 = {((~ A_pipe13[3]) & A_all_zero3[2]), ((~ A_pipe13[2]) & A_all_zero3[1]), ((~ A_pipe13[1]) & A_all_zero3[0]), (~ A_pipe13[0])},
A_all_zero4 = {((~ A_pipe14[3]) & A_all_zero4[2]), ((~ A_pipe14[2]) & A_all_zero4[1]), ((~ A_pipe14[1]) & A_all_zero4[0]), (~ A_pipe14[0])},
A_all_zero5 = {((~ A_pipe15[3]) & A_all_zero5[2]), ((~ A_pipe15[2]) & A_all_zero5[1]), ((~ A_pipe15[1]) & A_all_zero5[0]), (~ A_pipe15[0])},
A_all_zero6 = {((~ A_pipe16[3]) & A_all_zero6[2]), ((~ A_pipe16[2]) & A_all_zero6[1]), ((~ A_pipe16[1]) & A_all_zero6[0]), (~ A_pipe16[0])},
A_all_zero7 = {((~ A_pipe17[3]) & A_all_zero7[2]), ((~ A_pipe17[2]) & A_all_zero7[1]), ((~ A_pipe17[1]) & A_all_zero7[0]), (~ A_pipe17[0])},
A_all_zero8 = {((~ A_pipe18[3]) & A_all_zero8[2]), ((~ A_pipe18[2]) & A_all_zero8[1]), ((~ A_pipe18[1]) & A_all_zero8[0]), (~ A_pipe18[0])},
A_pipe0 = a0_in,
A_pipe11 = A_wire1_reg0,
A_pipe12 = A_wire2_reg0,
A_pipe13 = A_wire3_reg0,
A_pipe14 = A_wire4_reg0,
A_pipe15 = A_wire5_reg0,
A_pipe16 = A_wire6_reg0,
A_pipe17 = A_wire7_reg0,
A_pipe18 = A_wire8_reg0,
A_wire0 = A_pipe0_reg1,
A_wire1 = Z_wire1[53:50],
A_wire2 = Z_wire2[59:56],
A_wire3 = Z_wire3[68:65],
A_wire4 = Z_wire4[69:66],
A_wire5 = Z_wire5[66:63],
A_wire6 = Z_wire6[63:60],
A_wire7 = Z_wire7[60:57],
A_wire8 = Z_wire8[57:54],
almostlog = S_wire9,
B_pad_wire1 = {1'b0, B_pipe1, {9{1'b0}}},
B_pad_wire2 = {1'b0, B_pipe2, {12{1'b0}}},
B_pad_wire3 = {1'b0, B_pipe3, {4{1'b0}}},
B_pad_wire4 = {1'b0, B_pipe4},
B_pad_wire5 = {1'b0, B_pipe5},
B_pad_wire6 = {1'b0, B_pipe6},
B_pad_wire7 = {1'b0, B_pipe7},
B_pad_wire8 = {1'b0, B_pipe8},
B_pipe1 = B_wire1_reg0,
B_pipe2 = B_wire2_reg0,
B_pipe3 = B_wire3_reg0,
B_pipe4 = B_wire4_reg0,
B_pipe5 = B_wire5_reg0,
B_pipe6 = B_wire6_reg0,
B_pipe7 = B_wire7_reg0,
B_pipe8 = B_wire8_reg0,
B_wire1 = Z_wire1[49:0],
B_wire2 = Z_wire2[55:0],
B_wire3 = Z_wire3[64:0],
B_wire4 = Z_wire4[65:0],
B_wire5 = Z_wire5[62:0],
B_wire6 = Z_wire6[59:0],
B_wire7 = Z_wire7[56:0],
B_wire8 = Z_wire8[53:0],
epsZ_pad_wire1 = epsZ_wire1[59:0],
epsZ_pad_wire2 = epsZ_wire2[68:0],
epsZ_pad_wire3 = epsZ_wire3[80:11],
epsZ_pad_wire4 = epsZ_wire4[84:18],
epsZ_pad_wire5 = epsZ_wire5[84:21],
epsZ_pad_wire6 = epsZ_wire6[84:24],
epsZ_pad_wire7 = epsZ_wire7[84:27],
epsZ_pad_wire8 = epsZ_wire8[84:30],
epsZ_wire1 = ({60{A1_is_all_zero[3]}} & (({60{(~ A1_is_not_zero[3])}} & mux0_data0) | ({60{A1_is_not_zero[3]}} & mux0_data1))),
epsZ_wire2 = {1'b0, (~ A_all_zero2[3]), {7{1'b0}}, ({60{(~ A_all_zero2[3])}} & Z_pipe2)},
epsZ_wire3 = {1'b0, (~ A_all_zero3[3]), {10{1'b0}}, ({69{(~ A_all_zero3[3])}} & Z_pipe3)},
epsZ_wire4 = {1'b0, (~ A_all_zero4[3]), {13{1'b0}}, ({70{(~ A_all_zero4[3])}} & Z_pipe4)},
epsZ_wire5 = {1'b0, (~ A_all_zero5[3]), {16{1'b0}}, ({67{(~ A_all_zero5[3])}} & Z_pipe5)},
epsZ_wire6 = {1'b0, (~ A_all_zero6[3]), {19{1'b0}}, ({64{(~ A_all_zero6[3])}} & Z_pipe6)},
epsZ_wire7 = {1'b0, (~ A_all_zero7[3]), {22{1'b0}}, ({61{(~ A_all_zero7[3])}} & Z_pipe7)},
epsZ_wire8 = {1'b0, (~ A_all_zero8[3]), {25{1'b0}}, ({58{(~ A_all_zero8[3])}} & Z_pipe8)},
InvA0 = wire_InvTable0_result,
L_wire0 = wire_LogTable0_result,
L_wire1 = wire_LogTable1_result,
L_wire2 = wire_LogTable2_result,
L_wire3 = wire_LogTable3_result,
L_wire4 = wire_LogTable4_result,
L_wire5 = wire_LogTable5_result,
L_wire6 = wire_LogTable6_result,
L_wire7 = wire_LogTable7_result,
L_wire8 = wire_LogTable8_result,
mux0_data0 = {1'b1, {4{1'b0}}, Z_pipe1, 1'b0},
mux0_data1 = {1'b0, 1'b1, {4{1'b0}}, Z_pipe1},
P_pad_wire1 = {1'b0, P_wire1, 1'b0},
P_pad_wire2 = {{4{1'b0}}, P_wire2, 1'b0},
P_pad_wire3 = {{7{1'b0}}, P_wire3[66:4]},
P_pad_wire4 = {{10{1'b0}}, P_wire4[60:4]},
P_pad_wire5 = {{13{1'b0}}, P_wire5[54:4]},
P_pad_wire6 = {{16{1'b0}}, P_wire6[48:4]},
P_pad_wire7 = {{19{1'b0}}, P_wire7[42:4]},
P_pad_wire8 = {{22{1'b0}}, P_wire8[36:4]},
P_wire0 = wire_mult0_result,
P_wire1 = wire_mult1_result,
P_wire2 = wire_mult2_result,
P_wire3 = wire_mult3_result,
P_wire4 = wire_mult4_result,
P_wire5 = wire_mult5_result,
P_wire6 = wire_mult6_result,
P_wire7 = wire_mult7_result,
P_wire8 = wire_mult8_result,
S_pipe11 = S_wire1_reg0,
S_pipe12 = S_wire2_reg0,
S_pipe13 = S_wire3_reg0,
S_pipe14 = S_wire4_reg0,
S_pipe15 = S_wire5_reg0,
S_pipe16 = S_wire6_reg0,
S_pipe17 = S_wire7_reg0,
S_pipe18 = S_wire8_reg0,
S_pipe22 = wire_add0_1_result,
S_pipe23 = wire_add0_2_result,
S_pipe24 = wire_add0_3_result,
S_pipe25 = wire_add0_4_result,
S_pipe26 = wire_add0_5_result,
S_pipe27 = wire_add0_6_result,
S_pipe28 = wire_add0_7_result,
S_pipe29 = wire_add0_8_result,
S_wire1 = L_wire0,
S_wire2 = S_pipe22_reg0,
S_wire3 = S_pipe23_reg0,
S_wire4 = S_pipe24_reg0,
S_wire5 = S_pipe25_reg0,
S_wire6 = S_pipe26_reg0,
S_wire7 = S_pipe27_reg0,
S_wire8 = S_pipe28_reg0,
S_wire9 = S_pipe29_reg0,
z = Z_wire9,
Z_pipe1 = Z_wire1_reg0,
Z_pipe2 = Z_wire2_reg0,
Z_pipe3 = Z_wire3_reg0,
Z_pipe4 = Z_wire4_reg0,
Z_pipe5 = Z_wire5_reg0,
Z_pipe6 = Z_wire6_reg0,
Z_pipe7 = Z_wire7_reg0,
Z_pipe8 = Z_wire8_reg0,
Z_wire1 = P_wire0[53:0],
Z_wire2 = wire_sub1_1_result,
Z_wire3 = wire_sub1_2_result,
Z_wire4 = wire_sub1_3_result,
Z_wire5 = wire_sub1_4_result,
Z_wire6 = wire_sub1_5_result,
Z_wire7 = wire_sub1_6_result,
Z_wire8 = wire_sub1_7_result,
Z_wire9 = wire_sub1_8_result,
ZM_wire1 = Z_wire1,
ZM_wire2 = Z_wire2,
ZM_wire3 = Z_wire3[68:6],
ZM_wire4 = Z_wire4[69:13],
ZM_wire5 = Z_wire5[66:16],
ZM_wire6 = Z_wire6[63:19],
ZM_wire7 = Z_wire7[60:22],
ZM_wire8 = Z_wire8[57:25];
endmodule //acl_fp_log_double_range_reduction_cvd
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" PIPELINE=1 WIDTH=128 WIDTHAD=7 aclr clk_en clock data q
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" PIPELINE=0 WIDTH=64 WIDTHAD=6 data q
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=32 WIDTHAD=5 data q
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=16 WIDTHAD=4 data q zero
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q zero
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q zero
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q zero
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_double_altpriority_encoder_3e8
(
data,
q,
zero) ;
input [1:0] data;
output [0:0] q;
output zero;
assign
q = {data[1]},
zero = (~ (data[0] | data[1]));
endmodule //acl_fp_log_double_altpriority_encoder_3e8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_double_altpriority_encoder_6e8
(
data,
q,
zero) ;
input [3:0] data;
output [1:0] q;
output zero;
wire [0:0] wire_altpriority_encoder15_q;
wire wire_altpriority_encoder15_zero;
wire [0:0] wire_altpriority_encoder16_q;
wire wire_altpriority_encoder16_zero;
acl_fp_log_double_altpriority_encoder_3e8 altpriority_encoder15
(
.data(data[1:0]),
.q(wire_altpriority_encoder15_q),
.zero(wire_altpriority_encoder15_zero));
acl_fp_log_double_altpriority_encoder_3e8 altpriority_encoder16
(
.data(data[3:2]),
.q(wire_altpriority_encoder16_q),
.zero(wire_altpriority_encoder16_zero));
assign
q = {(~ wire_altpriority_encoder16_zero), ((wire_altpriority_encoder16_zero & wire_altpriority_encoder15_q) | ((~ wire_altpriority_encoder16_zero) & wire_altpriority_encoder16_q))},
zero = (wire_altpriority_encoder15_zero & wire_altpriority_encoder16_zero);
endmodule //acl_fp_log_double_altpriority_encoder_6e8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_double_altpriority_encoder_be8
(
data,
q,
zero) ;
input [7:0] data;
output [2:0] q;
output zero;
wire [1:0] wire_altpriority_encoder13_q;
wire wire_altpriority_encoder13_zero;
wire [1:0] wire_altpriority_encoder14_q;
wire wire_altpriority_encoder14_zero;
acl_fp_log_double_altpriority_encoder_6e8 altpriority_encoder13
(
.data(data[3:0]),
.q(wire_altpriority_encoder13_q),
.zero(wire_altpriority_encoder13_zero));
acl_fp_log_double_altpriority_encoder_6e8 altpriority_encoder14
(
.data(data[7:4]),
.q(wire_altpriority_encoder14_q),
.zero(wire_altpriority_encoder14_zero));
assign
q = {(~ wire_altpriority_encoder14_zero), (({2{wire_altpriority_encoder14_zero}} & wire_altpriority_encoder13_q) | ({2{(~ wire_altpriority_encoder14_zero)}} & wire_altpriority_encoder14_q))},
zero = (wire_altpriority_encoder13_zero & wire_altpriority_encoder14_zero);
endmodule //acl_fp_log_double_altpriority_encoder_be8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_double_altpriority_encoder_rf8
(
data,
q,
zero) ;
input [15:0] data;
output [3:0] q;
output zero;
wire [2:0] wire_altpriority_encoder11_q;
wire wire_altpriority_encoder11_zero;
wire [2:0] wire_altpriority_encoder12_q;
wire wire_altpriority_encoder12_zero;
acl_fp_log_double_altpriority_encoder_be8 altpriority_encoder11
(
.data(data[7:0]),
.q(wire_altpriority_encoder11_q),
.zero(wire_altpriority_encoder11_zero));
acl_fp_log_double_altpriority_encoder_be8 altpriority_encoder12
(
.data(data[15:8]),
.q(wire_altpriority_encoder12_q),
.zero(wire_altpriority_encoder12_zero));
assign
q = {(~ wire_altpriority_encoder12_zero), (({3{wire_altpriority_encoder12_zero}} & wire_altpriority_encoder11_q) | ({3{(~ wire_altpriority_encoder12_zero)}} & wire_altpriority_encoder12_q))},
zero = (wire_altpriority_encoder11_zero & wire_altpriority_encoder12_zero);
endmodule //acl_fp_log_double_altpriority_encoder_rf8
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=16 WIDTHAD=4 data q
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_double_altpriority_encoder_3v7
(
data,
q) ;
input [1:0] data;
output [0:0] q;
assign
q = {data[1]};
endmodule //acl_fp_log_double_altpriority_encoder_3v7
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_double_altpriority_encoder_6v7
(
data,
q) ;
input [3:0] data;
output [1:0] q;
wire [0:0] wire_altpriority_encoder21_q;
wire [0:0] wire_altpriority_encoder22_q;
wire wire_altpriority_encoder22_zero;
acl_fp_log_double_altpriority_encoder_3v7 altpriority_encoder21
(
.data(data[1:0]),
.q(wire_altpriority_encoder21_q));
acl_fp_log_double_altpriority_encoder_3e8 altpriority_encoder22
(
.data(data[3:2]),
.q(wire_altpriority_encoder22_q),
.zero(wire_altpriority_encoder22_zero));
assign
q = {(~ wire_altpriority_encoder22_zero), ((wire_altpriority_encoder22_zero & wire_altpriority_encoder21_q) | ((~ wire_altpriority_encoder22_zero) & wire_altpriority_encoder22_q))};
endmodule //acl_fp_log_double_altpriority_encoder_6v7
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_double_altpriority_encoder_bv7
(
data,
q) ;
input [7:0] data;
output [2:0] q;
wire [1:0] wire_altpriority_encoder19_q;
wire [1:0] wire_altpriority_encoder20_q;
wire wire_altpriority_encoder20_zero;
acl_fp_log_double_altpriority_encoder_6v7 altpriority_encoder19
(
.data(data[3:0]),
.q(wire_altpriority_encoder19_q));
acl_fp_log_double_altpriority_encoder_6e8 altpriority_encoder20
(
.data(data[7:4]),
.q(wire_altpriority_encoder20_q),
.zero(wire_altpriority_encoder20_zero));
assign
q = {(~ wire_altpriority_encoder20_zero), (({2{wire_altpriority_encoder20_zero}} & wire_altpriority_encoder19_q) | ({2{(~ wire_altpriority_encoder20_zero)}} & wire_altpriority_encoder20_q))};
endmodule //acl_fp_log_double_altpriority_encoder_bv7
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_double_altpriority_encoder_r08
(
data,
q) ;
input [15:0] data;
output [3:0] q;
wire [2:0] wire_altpriority_encoder17_q;
wire [2:0] wire_altpriority_encoder18_q;
wire wire_altpriority_encoder18_zero;
acl_fp_log_double_altpriority_encoder_bv7 altpriority_encoder17
(
.data(data[7:0]),
.q(wire_altpriority_encoder17_q));
acl_fp_log_double_altpriority_encoder_be8 altpriority_encoder18
(
.data(data[15:8]),
.q(wire_altpriority_encoder18_q),
.zero(wire_altpriority_encoder18_zero));
assign
q = {(~ wire_altpriority_encoder18_zero), (({3{wire_altpriority_encoder18_zero}} & wire_altpriority_encoder17_q) | ({3{(~ wire_altpriority_encoder18_zero)}} & wire_altpriority_encoder18_q))};
endmodule //acl_fp_log_double_altpriority_encoder_r08
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_double_altpriority_encoder_q08
(
data,
q) ;
input [31:0] data;
output [4:0] q;
wire [3:0] wire_altpriority_encoder10_q;
wire wire_altpriority_encoder10_zero;
wire [3:0] wire_altpriority_encoder9_q;
acl_fp_log_double_altpriority_encoder_rf8 altpriority_encoder10
(
.data(data[31:16]),
.q(wire_altpriority_encoder10_q),
.zero(wire_altpriority_encoder10_zero));
acl_fp_log_double_altpriority_encoder_r08 altpriority_encoder9
(
.data(data[15:0]),
.q(wire_altpriority_encoder9_q));
assign
q = {(~ wire_altpriority_encoder10_zero), (({4{wire_altpriority_encoder10_zero}} & wire_altpriority_encoder9_q) | ({4{(~ wire_altpriority_encoder10_zero)}} & wire_altpriority_encoder10_q))};
endmodule //acl_fp_log_double_altpriority_encoder_q08
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=32 WIDTHAD=5 data q zero
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_double_altpriority_encoder_qf8
(
data,
q,
zero) ;
input [31:0] data;
output [4:0] q;
output zero;
wire [3:0] wire_altpriority_encoder23_q;
wire wire_altpriority_encoder23_zero;
wire [3:0] wire_altpriority_encoder24_q;
wire wire_altpriority_encoder24_zero;
acl_fp_log_double_altpriority_encoder_rf8 altpriority_encoder23
(
.data(data[15:0]),
.q(wire_altpriority_encoder23_q),
.zero(wire_altpriority_encoder23_zero));
acl_fp_log_double_altpriority_encoder_rf8 altpriority_encoder24
(
.data(data[31:16]),
.q(wire_altpriority_encoder24_q),
.zero(wire_altpriority_encoder24_zero));
assign
q = {(~ wire_altpriority_encoder24_zero), (({4{wire_altpriority_encoder24_zero}} & wire_altpriority_encoder23_q) | ({4{(~ wire_altpriority_encoder24_zero)}} & wire_altpriority_encoder24_q))},
zero = (wire_altpriority_encoder23_zero & wire_altpriority_encoder24_zero);
endmodule //acl_fp_log_double_altpriority_encoder_qf8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_double_altpriority_encoder_309
(
data,
q) ;
input [63:0] data;
output [5:0] q;
wire [4:0] wire_altpriority_encoder7_q;
wire [4:0] wire_altpriority_encoder8_q;
wire wire_altpriority_encoder8_zero;
acl_fp_log_double_altpriority_encoder_q08 altpriority_encoder7
(
.data(data[31:0]),
.q(wire_altpriority_encoder7_q));
acl_fp_log_double_altpriority_encoder_qf8 altpriority_encoder8
(
.data(data[63:32]),
.q(wire_altpriority_encoder8_q),
.zero(wire_altpriority_encoder8_zero));
assign
q = {(~ wire_altpriority_encoder8_zero), (({5{wire_altpriority_encoder8_zero}} & wire_altpriority_encoder7_q) | ({5{(~ wire_altpriority_encoder8_zero)}} & wire_altpriority_encoder8_q))};
endmodule //acl_fp_log_double_altpriority_encoder_309
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" PIPELINE=0 WIDTH=64 WIDTHAD=6 data q zero
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_double_altpriority_encoder_3f9
(
data,
q,
zero) ;
input [63:0] data;
output [5:0] q;
output zero;
wire [4:0] wire_altpriority_encoder25_q;
wire wire_altpriority_encoder25_zero;
wire [4:0] wire_altpriority_encoder26_q;
wire wire_altpriority_encoder26_zero;
acl_fp_log_double_altpriority_encoder_qf8 altpriority_encoder25
(
.data(data[31:0]),
.q(wire_altpriority_encoder25_q),
.zero(wire_altpriority_encoder25_zero));
acl_fp_log_double_altpriority_encoder_qf8 altpriority_encoder26
(
.data(data[63:32]),
.q(wire_altpriority_encoder26_q),
.zero(wire_altpriority_encoder26_zero));
assign
q = {(~ wire_altpriority_encoder26_zero), (({5{wire_altpriority_encoder26_zero}} & wire_altpriority_encoder25_q) | ({5{(~ wire_altpriority_encoder26_zero)}} & wire_altpriority_encoder26_q))},
zero = (wire_altpriority_encoder25_zero & wire_altpriority_encoder26_zero);
endmodule //acl_fp_log_double_altpriority_encoder_3f9
//synthesis_resources = reg 7
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_double_altpriority_encoder_gla
(
aclr,
clk_en,
clock,
data,
q) ;
input aclr;
input clk_en;
input clock;
input [127:0] data;
output [6:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clk_en;
tri0 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [5:0] wire_altpriority_encoder5_q;
wire [5:0] wire_altpriority_encoder6_q;
wire wire_altpriority_encoder6_zero;
reg [6:0] pipeline_q_dffe;
wire [6:0] tmp_q_wire;
acl_fp_log_double_altpriority_encoder_309 altpriority_encoder5
(
.data(data[63:0]),
.q(wire_altpriority_encoder5_q));
acl_fp_log_double_altpriority_encoder_3f9 altpriority_encoder6
(
.data(data[127:64]),
.q(wire_altpriority_encoder6_q),
.zero(wire_altpriority_encoder6_zero));
// synopsys translate_off
initial
pipeline_q_dffe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) pipeline_q_dffe <= 7'b0;
else if (clk_en == 1'b1) pipeline_q_dffe <= tmp_q_wire;
assign
q = pipeline_q_dffe,
tmp_q_wire = {(~ wire_altpriority_encoder6_zero), (({6{wire_altpriority_encoder6_zero}} & wire_altpriority_encoder5_q) | ({6{(~ wire_altpriority_encoder6_zero)}} & wire_altpriority_encoder6_q))};
endmodule //acl_fp_log_double_altpriority_encoder_gla
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=64 WIDTHAD=6 data q
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_double_altpriority_encoder_018
(
data,
q) ;
input [63:0] data;
output [5:0] q;
wire [4:0] wire_altpriority_encoder27_q;
wire [4:0] wire_altpriority_encoder28_q;
wire wire_altpriority_encoder28_zero;
acl_fp_log_double_altpriority_encoder_q08 altpriority_encoder27
(
.data(data[31:0]),
.q(wire_altpriority_encoder27_q));
acl_fp_log_double_altpriority_encoder_qf8 altpriority_encoder28
(
.data(data[63:32]),
.q(wire_altpriority_encoder28_q),
.zero(wire_altpriority_encoder28_zero));
assign
q = {(~ wire_altpriority_encoder28_zero), (({5{wire_altpriority_encoder28_zero}} & wire_altpriority_encoder27_q) | ({5{(~ wire_altpriority_encoder28_zero)}} & wire_altpriority_encoder28_q))};
endmodule //acl_fp_log_double_altpriority_encoder_018
//synthesis_resources = altsquare 1 lpm_add_sub 89 lpm_mult 10 lpm_mux 10 mux21 63 reg 4847
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_double_altfp_log_17b
(
clk_en,
clock,
data,
result) ;
input clk_en;
input clock;
input [63:0] data;
output [63:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clk_en;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [63:0] wire_Lshiftsmall_result;
wire [127:0] wire_lzc_norm_L_result;
wire [63:0] wire_Rshiftsmall_result;
wire wire_exp_nan_result;
wire wire_exp_zero_result;
wire wire_man_inf_result;
wire wire_man_nan_result;
wire [82:0] wire_add1_result;
wire [62:0] wire_add2_result;
wire [10:0] wire_exp_biase_sub_result;
wire [25:0] wire_sub1_result;
wire [10:0] wire_sub2_result;
wire [6:0] wire_sub3_result;
wire [54:0] wire_sub4_result;
wire [10:0] wire_sub5_result;
wire [10:0] wire_sub6_result;
wire [82:0] wire_range_reduction_almostlog;
wire [54:0] wire_range_reduction_z;
wire [6:0] wire_lzc_norm_E_q;
wire [5:0] wire_lzoc_q;
wire [27:0] wire_squarer_result;
reg [67:0] absELog2_pipe_reg0;
reg [67:0] absELog2_pipe_reg1;
reg [67:0] absELog2_pipe_reg2;
reg [25:0] absZ0_pipe_reg0;
reg [25:0] absZ0_pipe_reg1;
reg [25:0] absZ0_pipe_reg10;
reg [25:0] absZ0_pipe_reg11;
reg [25:0] absZ0_pipe_reg12;
reg [25:0] absZ0_pipe_reg13;
reg [25:0] absZ0_pipe_reg14;
reg [25:0] absZ0_pipe_reg15;
reg [25:0] absZ0_pipe_reg16;
reg [25:0] absZ0_pipe_reg17;
reg [25:0] absZ0_pipe_reg18;
reg [25:0] absZ0_pipe_reg19;
reg [25:0] absZ0_pipe_reg2;
reg [25:0] absZ0_pipe_reg20;
reg [25:0] absZ0_pipe_reg21;
reg [25:0] absZ0_pipe_reg22;
reg [25:0] absZ0_pipe_reg23;
reg [25:0] absZ0_pipe_reg3;
reg [25:0] absZ0_pipe_reg4;
reg [25:0] absZ0_pipe_reg5;
reg [25:0] absZ0_pipe_reg6;
reg [25:0] absZ0_pipe_reg7;
reg [25:0] absZ0_pipe_reg8;
reg [25:0] absZ0_pipe_reg9;
reg [25:0] absZ0s_pipe1_reg0;
reg [25:0] absZ0s_pipe1_reg1;
reg [25:0] absZ0s_pipe1_reg2;
reg [25:0] absZ0s_pipe1_reg3;
reg [25:0] absZ0s_reg0;
reg [82:0] almostLog_pipe_reg0;
reg [82:0] almostLog_pipe_reg1;
reg [82:0] almostLog_pipe_reg2;
reg [0:0] doRR_reg0;
reg [0:0] doRR_reg1;
reg [10:0] E0_pipe_reg0;
reg [10:0] E0_pipe_reg1;
reg [10:0] E0_pipe_reg10;
reg [10:0] E0_pipe_reg11;
reg [10:0] E0_pipe_reg12;
reg [10:0] E0_pipe_reg13;
reg [10:0] E0_pipe_reg14;
reg [10:0] E0_pipe_reg15;
reg [10:0] E0_pipe_reg16;
reg [10:0] E0_pipe_reg17;
reg [10:0] E0_pipe_reg18;
reg [10:0] E0_pipe_reg19;
reg [10:0] E0_pipe_reg2;
reg [10:0] E0_pipe_reg20;
reg [10:0] E0_pipe_reg21;
reg [10:0] E0_pipe_reg22;
reg [10:0] E0_pipe_reg23;
reg [10:0] E0_pipe_reg3;
reg [10:0] E0_pipe_reg4;
reg [10:0] E0_pipe_reg5;
reg [10:0] E0_pipe_reg6;
reg [10:0] E0_pipe_reg7;
reg [10:0] E0_pipe_reg8;
reg [10:0] E0_pipe_reg9;
reg [5:0] E_normal_pipe_reg0;
reg [0:0] exp_is_ebiase_pipe_reg0;
reg [0:0] exp_is_ebiase_pipe_reg1;
reg [0:0] exp_is_ebiase_pipe_reg2;
reg [0:0] input_is_infinity_pipe_reg0;
reg [0:0] input_is_infinity_pipe_reg1;
reg [0:0] input_is_infinity_pipe_reg10;
reg [0:0] input_is_infinity_pipe_reg11;
reg [0:0] input_is_infinity_pipe_reg12;
reg [0:0] input_is_infinity_pipe_reg13;
reg [0:0] input_is_infinity_pipe_reg14;
reg [0:0] input_is_infinity_pipe_reg15;
reg [0:0] input_is_infinity_pipe_reg16;
reg [0:0] input_is_infinity_pipe_reg17;
reg [0:0] input_is_infinity_pipe_reg18;
reg [0:0] input_is_infinity_pipe_reg19;
reg [0:0] input_is_infinity_pipe_reg2;
reg [0:0] input_is_infinity_pipe_reg20;
reg [0:0] input_is_infinity_pipe_reg21;
reg [0:0] input_is_infinity_pipe_reg22;
reg [0:0] input_is_infinity_pipe_reg23;
reg [0:0] input_is_infinity_pipe_reg24;
reg [0:0] input_is_infinity_pipe_reg25;
reg [0:0] input_is_infinity_pipe_reg26;
reg [0:0] input_is_infinity_pipe_reg27;
reg [0:0] input_is_infinity_pipe_reg28;
reg [0:0] input_is_infinity_pipe_reg29;
reg [0:0] input_is_infinity_pipe_reg3;
reg [0:0] input_is_infinity_pipe_reg30;
reg [0:0] input_is_infinity_pipe_reg4;
reg [0:0] input_is_infinity_pipe_reg5;
reg [0:0] input_is_infinity_pipe_reg6;
reg [0:0] input_is_infinity_pipe_reg7;
reg [0:0] input_is_infinity_pipe_reg8;
reg [0:0] input_is_infinity_pipe_reg9;
reg [0:0] input_is_nan_pipe_reg0;
reg [0:0] input_is_nan_pipe_reg1;
reg [0:0] input_is_nan_pipe_reg10;
reg [0:0] input_is_nan_pipe_reg11;
reg [0:0] input_is_nan_pipe_reg12;
reg [0:0] input_is_nan_pipe_reg13;
reg [0:0] input_is_nan_pipe_reg14;
reg [0:0] input_is_nan_pipe_reg15;
reg [0:0] input_is_nan_pipe_reg16;
reg [0:0] input_is_nan_pipe_reg17;
reg [0:0] input_is_nan_pipe_reg18;
reg [0:0] input_is_nan_pipe_reg19;
reg [0:0] input_is_nan_pipe_reg2;
reg [0:0] input_is_nan_pipe_reg20;
reg [0:0] input_is_nan_pipe_reg21;
reg [0:0] input_is_nan_pipe_reg22;
reg [0:0] input_is_nan_pipe_reg23;
reg [0:0] input_is_nan_pipe_reg24;
reg [0:0] input_is_nan_pipe_reg25;
reg [0:0] input_is_nan_pipe_reg26;
reg [0:0] input_is_nan_pipe_reg27;
reg [0:0] input_is_nan_pipe_reg28;
reg [0:0] input_is_nan_pipe_reg29;
reg [0:0] input_is_nan_pipe_reg3;
reg [0:0] input_is_nan_pipe_reg30;
reg [0:0] input_is_nan_pipe_reg4;
reg [0:0] input_is_nan_pipe_reg5;
reg [0:0] input_is_nan_pipe_reg6;
reg [0:0] input_is_nan_pipe_reg7;
reg [0:0] input_is_nan_pipe_reg8;
reg [0:0] input_is_nan_pipe_reg9;
reg [0:0] input_is_one_pipe_reg0;
reg [0:0] input_is_one_pipe_reg1;
reg [0:0] input_is_one_pipe_reg10;
reg [0:0] input_is_one_pipe_reg11;
reg [0:0] input_is_one_pipe_reg12;
reg [0:0] input_is_one_pipe_reg13;
reg [0:0] input_is_one_pipe_reg14;
reg [0:0] input_is_one_pipe_reg15;
reg [0:0] input_is_one_pipe_reg16;
reg [0:0] input_is_one_pipe_reg17;
reg [0:0] input_is_one_pipe_reg18;
reg [0:0] input_is_one_pipe_reg19;
reg [0:0] input_is_one_pipe_reg2;
reg [0:0] input_is_one_pipe_reg20;
reg [0:0] input_is_one_pipe_reg21;
reg [0:0] input_is_one_pipe_reg22;
reg [0:0] input_is_one_pipe_reg23;
reg [0:0] input_is_one_pipe_reg24;
reg [0:0] input_is_one_pipe_reg25;
reg [0:0] input_is_one_pipe_reg26;
reg [0:0] input_is_one_pipe_reg27;
reg [0:0] input_is_one_pipe_reg28;
reg [0:0] input_is_one_pipe_reg29;
reg [0:0] input_is_one_pipe_reg3;
reg [0:0] input_is_one_pipe_reg30;
reg [0:0] input_is_one_pipe_reg4;
reg [0:0] input_is_one_pipe_reg5;
reg [0:0] input_is_one_pipe_reg6;
reg [0:0] input_is_one_pipe_reg7;
reg [0:0] input_is_one_pipe_reg8;
reg [0:0] input_is_one_pipe_reg9;
reg [0:0] input_is_zero_pipe_reg0;
reg [0:0] input_is_zero_pipe_reg1;
reg [0:0] input_is_zero_pipe_reg10;
reg [0:0] input_is_zero_pipe_reg11;
reg [0:0] input_is_zero_pipe_reg12;
reg [0:0] input_is_zero_pipe_reg13;
reg [0:0] input_is_zero_pipe_reg14;
reg [0:0] input_is_zero_pipe_reg15;
reg [0:0] input_is_zero_pipe_reg16;
reg [0:0] input_is_zero_pipe_reg17;
reg [0:0] input_is_zero_pipe_reg18;
reg [0:0] input_is_zero_pipe_reg19;
reg [0:0] input_is_zero_pipe_reg2;
reg [0:0] input_is_zero_pipe_reg20;
reg [0:0] input_is_zero_pipe_reg21;
reg [0:0] input_is_zero_pipe_reg22;
reg [0:0] input_is_zero_pipe_reg23;
reg [0:0] input_is_zero_pipe_reg24;
reg [0:0] input_is_zero_pipe_reg25;
reg [0:0] input_is_zero_pipe_reg26;
reg [0:0] input_is_zero_pipe_reg27;
reg [0:0] input_is_zero_pipe_reg28;
reg [0:0] input_is_zero_pipe_reg29;
reg [0:0] input_is_zero_pipe_reg3;
reg [0:0] input_is_zero_pipe_reg30;
reg [0:0] input_is_zero_pipe_reg4;
reg [0:0] input_is_zero_pipe_reg5;
reg [0:0] input_is_zero_pipe_reg6;
reg [0:0] input_is_zero_pipe_reg7;
reg [0:0] input_is_zero_pipe_reg8;
reg [0:0] input_is_zero_pipe_reg9;
reg [93:0] Log_normal_normd_pipe_reg0;
reg [93:0] Log_normal_reg0;
reg [56:0] Log_small_normd_pipe_reg0;
reg [56:0] Log_small_normd_pipe_reg1;
reg [6:0] Lshiftval_reg0;
reg [6:0] Lshiftval_reg1;
reg [6:0] Lshiftval_reg2;
reg [6:0] Lshiftval_reg3;
reg [5:0] lzo_pipe1_reg0;
reg [5:0] lzo_pipe1_reg1;
reg [5:0] lzo_pipe1_reg10;
reg [5:0] lzo_pipe1_reg11;
reg [5:0] lzo_pipe1_reg12;
reg [5:0] lzo_pipe1_reg13;
reg [5:0] lzo_pipe1_reg14;
reg [5:0] lzo_pipe1_reg15;
reg [5:0] lzo_pipe1_reg16;
reg [5:0] lzo_pipe1_reg17;
reg [5:0] lzo_pipe1_reg18;
reg [5:0] lzo_pipe1_reg19;
reg [5:0] lzo_pipe1_reg2;
reg [5:0] lzo_pipe1_reg20;
reg [5:0] lzo_pipe1_reg21;
reg [5:0] lzo_pipe1_reg22;
reg [5:0] lzo_pipe1_reg23;
reg [5:0] lzo_pipe1_reg3;
reg [5:0] lzo_pipe1_reg4;
reg [5:0] lzo_pipe1_reg5;
reg [5:0] lzo_pipe1_reg6;
reg [5:0] lzo_pipe1_reg7;
reg [5:0] lzo_pipe1_reg8;
reg [5:0] lzo_pipe1_reg9;
reg [5:0] lzo_reg0;
reg [5:0] lzo_reg1;
reg [5:0] lzo_reg2;
reg [5:0] lzo_reg3;
reg [5:0] lzo_reg4;
reg [5:0] lzo_reg5;
reg [5:0] lzo_reg6;
reg [0:0] sign_data_reg0;
reg [0:0] sign_data_reg1;
reg [0:0] sign_data_reg2;
reg [0:0] small_flag_pipe_reg0;
reg [0:0] small_flag_pipe_reg1;
reg [0:0] small_flag_pipe_reg2;
reg [0:0] small_flag_pipe_reg3;
reg [0:0] small_flag_pipe_reg4;
reg [0:0] small_flag_pipe_reg5;
reg [0:0] small_flag_pipe_reg6;
reg [0:0] small_flag_pipe_reg7;
reg [0:0] small_flag_pipe_reg8;
reg [0:0] sR_pipe1_reg0;
reg [0:0] sR_pipe1_reg1;
reg [0:0] sR_pipe1_reg10;
reg [0:0] sR_pipe1_reg11;
reg [0:0] sR_pipe1_reg12;
reg [0:0] sR_pipe1_reg13;
reg [0:0] sR_pipe1_reg14;
reg [0:0] sR_pipe1_reg15;
reg [0:0] sR_pipe1_reg16;
reg [0:0] sR_pipe1_reg17;
reg [0:0] sR_pipe1_reg18;
reg [0:0] sR_pipe1_reg19;
reg [0:0] sR_pipe1_reg2;
reg [0:0] sR_pipe1_reg20;
reg [0:0] sR_pipe1_reg21;
reg [0:0] sR_pipe1_reg22;
reg [0:0] sR_pipe1_reg23;
reg [0:0] sR_pipe1_reg3;
reg [0:0] sR_pipe1_reg4;
reg [0:0] sR_pipe1_reg5;
reg [0:0] sR_pipe1_reg6;
reg [0:0] sR_pipe1_reg7;
reg [0:0] sR_pipe1_reg8;
reg [0:0] sR_pipe1_reg9;
reg [0:0] sR_pipe2_reg0;
reg [0:0] sR_pipe2_reg1;
reg [0:0] sR_pipe2_reg2;
reg [0:0] sR_pipe2_reg3;
reg [0:0] sR_pipe2_reg4;
reg [0:0] sR_pipe2_reg5;
reg [0:0] sR_pipe3_reg0;
reg [0:0] sR_pipe3_reg1;
reg [0:0] sR_pipe3_reg2;
reg [0:0] sR_pipe3_reg3;
reg [27:0] Z2o2_pipe_reg0;
reg [27:0] Z2o2_small_s_pipe_reg0;
reg [54:0] Zfinal_reg0;
reg [54:0] Zfinal_reg1;
wire [58:0] wire_addsub1_result;
wire [93:0] wire_addsub2_result;
wire [67:0] wire_mult1_result;
wire [62:0]wire_mux_result0a_dataout;
wire [10:0] absE;
wire [67:0] absELog2;
wire [93:0] absELog2_pad;
wire [67:0] absELog2_pipe;
wire [25:0] absZ0;
wire [25:0] absZ0_pipe;
wire [25:0] absZ0s;
wire [25:0] absZ0s_pipe1;
wire [25:0] absZ0s_pipe2;
wire aclr;
wire [82:0] almostLog;
wire [82:0] almostLog_pipe;
wire [10:0] data_exp_is_ebiase;
wire doRR;
wire doRR_pipe;
wire [10:0] E0;
wire [10:0] E0_is_zero;
wire [10:0] E0_pipe;
wire [1:0] E0_sub;
wire [10:0] E0offset;
wire [5:0] E_normal;
wire [5:0] E_normal_pipe;
wire [10:0] E_small;
wire [62:0] EFR;
wire [10:0] ER;
wire exp_all_one;
wire exp_all_zero;
wire [10:0] exp_biase;
wire [10:0] exp_data;
wire exp_is_ebiase;
wire exp_is_ebiase_pipe;
wire First_bit;
wire input_is_infinity;
wire input_is_infinity_pipe;
wire input_is_nan;
wire input_is_nan_pipe;
wire input_is_one;
wire input_is_one_pipe;
wire input_is_zero;
wire input_is_zero_pipe;
wire [54:0] Log1p_normal;
wire [56:0] Log2;
wire [56:0] Log_g;
wire [93:0] Log_normal;
wire [93:0] Log_normal_normd;
wire [93:0] Log_normal_normd_pipe;
wire [93:0] Log_normal_pipe;
wire [58:0] Log_small;
wire [56:0] Log_small1;
wire [56:0] Log_small2;
wire [56:0] Log_small_normd;
wire [56:0] Log_small_normd_pipe;
wire [82:0] LogF_normal;
wire [93:0] LogF_normal_pad;
wire [6:0] Lshiftval;
wire [5:0] lzo;
wire [5:0] lzo_pipe1;
wire [5:0] lzo_pipe2;
wire [53:0] man_above_half;
wire man_all_zero;
wire [53:0] man_below_half;
wire [51:0] man_data;
wire man_not_zero;
wire [5:0] pfinal_s;
wire round;
wire [6:0] Rshiftval;
wire sign_data;
wire sign_data_pipe;
wire small_flag;
wire small_flag_pipe;
wire [26:0] squarerIn;
wire [26:0] squarerIn0;
wire [26:0] squarerIn1;
wire sR;
wire sR_pipe1;
wire sR_pipe2;
wire sR_pipe3;
wire [3:0] sticky;
wire [53:0] Y0;
wire [27:0] Z2o2;
wire [27:0] Z2o2_pipe;
wire [58:0] Z2o2_small;
wire [27:0] Z2o2_small_s;
wire [27:0] Z2o2_small_s_pipe;
wire [58:0] Z_small;
wire [54:0] Zfinal;
wire [54:0] Zfinal_pipe;
acl_fp_log_double_altbarrel_shift_32e Lshiftsmall
(
.aclr(aclr),
.clk_en(clk_en),
.clock(clock),
.data({absZ0, {38{1'b0}}}),
.distance(Lshiftval[5:0]),
.result(wire_Lshiftsmall_result));
acl_fp_log_double_altbarrel_shift_ngb lzc_norm_L
(
.data({Log_normal_pipe, {34{1'b0}}}),
.distance((~ wire_lzc_norm_E_q)),
.result(wire_lzc_norm_L_result));
acl_fp_log_double_altbarrel_shift_m5e Rshiftsmall
(
.aclr(aclr),
.clk_en(clk_en),
.clock(clock),
.data({Z2o2, {36{1'b0}}}),
.distance(Rshiftval[5:0]),
.result(wire_Rshiftsmall_result));
acl_fp_log_double_altfp_log_and_or_rab exp_nan
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.data(exp_data),
.result(wire_exp_nan_result));
acl_fp_log_double_altfp_log_and_or_98b exp_zero
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.data(exp_data),
.result(wire_exp_zero_result));
acl_fp_log_double_altfp_log_and_or_e8b man_inf
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.data(man_data),
.result(wire_man_inf_result));
acl_fp_log_double_altfp_log_and_or_e8b man_nan
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.data(man_data),
.result(wire_man_nan_result));
acl_fp_log_double_altfp_log_csa_r0e add1
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa({{28{1'b0}}, Log1p_normal}),
.datab(almostLog),
.result(wire_add1_result));
acl_fp_log_double_altfp_log_csa_p0e add2
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa({ER, Log_g[56:5]}),
.datab({{62{1'b0}}, round}),
.result(wire_add2_result));
acl_fp_log_double_altfp_log_csa_aoc exp_biase_sub
(
.dataa(exp_data),
.datab(exp_biase),
.result(wire_exp_biase_sub_result));
acl_fp_log_double_altfp_log_csa_i4b sub1
(
.dataa({26{1'b0}}),
.datab(Y0[25:0]),
.result(wire_sub1_result));
acl_fp_log_double_altfp_log_csa_aoc sub2
(
.dataa({11{1'b0}}),
.datab(E0),
.result(wire_sub2_result));
acl_fp_log_double_altfp_log_csa_vmc sub3
(
.dataa({1'b0, lzo}),
.datab({1'b0, pfinal_s}),
.result(wire_sub3_result));
acl_fp_log_double_altfp_log_csa_plf sub4
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(Zfinal_pipe),
.datab({{29{1'b0}}, Z2o2[27:2]}),
.result(wire_sub4_result));
acl_fp_log_double_altfp_log_csa_ilf sub5
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa({1'b0, {8{1'b1}}, E0_sub}),
.datab({{5{1'b0}}, lzo_pipe2}),
.result(wire_sub5_result));
acl_fp_log_double_altfp_log_csa_aoc sub6
(
.dataa(E0offset),
.datab({{5{1'b0}}, (~ E_normal)}),
.result(wire_sub6_result));
acl_fp_log_double_range_reduction_cvd range_reduction
(
.a0_in(man_data[51:47]),
.aclr(aclr),
.almostlog(wire_range_reduction_almostlog),
.clk_en(clk_en),
.clock(clock),
.y0_in(Y0),
.z(wire_range_reduction_z));
acl_fp_log_double_altpriority_encoder_gla lzc_norm_E
(
.aclr(aclr),
.clk_en(clk_en),
.clock(clock),
.data({Log_normal, 34'b0000000000000000000000000000000001}),
.q(wire_lzc_norm_E_q));
acl_fp_log_double_altpriority_encoder_018 lzoc
(
.data({({52{First_bit}} ^ Y0[52:1]), 12'b000000000001}),
.q(wire_lzoc_q));
altsquare squarer
(
.aclr(aclr),
.clock(clock),
.data(squarerIn),
.ena(clk_en),
.result(wire_squarer_result));
defparam
squarer.data_width = 27,
squarer.pipeline = 1,
squarer.representation = "UNSIGNED",
squarer.result_alignment = "MSB",
squarer.result_width = 28,
squarer.lpm_type = "altsquare";
// synopsys translate_off
initial
absELog2_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absELog2_pipe_reg0 <= 68'b0;
else if (clk_en == 1'b1) absELog2_pipe_reg0 <= absELog2_pipe;
// synopsys translate_off
initial
absELog2_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absELog2_pipe_reg1 <= 68'b0;
else if (clk_en == 1'b1) absELog2_pipe_reg1 <= absELog2_pipe_reg0;
// synopsys translate_off
initial
absELog2_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absELog2_pipe_reg2 <= 68'b0;
else if (clk_en == 1'b1) absELog2_pipe_reg2 <= absELog2_pipe_reg1;
// synopsys translate_off
initial
absZ0_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg0 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg0 <= absZ0_pipe;
// synopsys translate_off
initial
absZ0_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg1 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg1 <= absZ0_pipe_reg0;
// synopsys translate_off
initial
absZ0_pipe_reg10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg10 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg10 <= absZ0_pipe_reg9;
// synopsys translate_off
initial
absZ0_pipe_reg11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg11 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg11 <= absZ0_pipe_reg10;
// synopsys translate_off
initial
absZ0_pipe_reg12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg12 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg12 <= absZ0_pipe_reg11;
// synopsys translate_off
initial
absZ0_pipe_reg13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg13 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg13 <= absZ0_pipe_reg12;
// synopsys translate_off
initial
absZ0_pipe_reg14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg14 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg14 <= absZ0_pipe_reg13;
// synopsys translate_off
initial
absZ0_pipe_reg15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg15 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg15 <= absZ0_pipe_reg14;
// synopsys translate_off
initial
absZ0_pipe_reg16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg16 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg16 <= absZ0_pipe_reg15;
// synopsys translate_off
initial
absZ0_pipe_reg17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg17 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg17 <= absZ0_pipe_reg16;
// synopsys translate_off
initial
absZ0_pipe_reg18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg18 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg18 <= absZ0_pipe_reg17;
// synopsys translate_off
initial
absZ0_pipe_reg19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg19 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg19 <= absZ0_pipe_reg18;
// synopsys translate_off
initial
absZ0_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg2 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg2 <= absZ0_pipe_reg1;
// synopsys translate_off
initial
absZ0_pipe_reg20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg20 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg20 <= absZ0_pipe_reg19;
// synopsys translate_off
initial
absZ0_pipe_reg21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg21 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg21 <= absZ0_pipe_reg20;
// synopsys translate_off
initial
absZ0_pipe_reg22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg22 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg22 <= absZ0_pipe_reg21;
// synopsys translate_off
initial
absZ0_pipe_reg23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg23 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg23 <= absZ0_pipe_reg22;
// synopsys translate_off
initial
absZ0_pipe_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg3 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg3 <= absZ0_pipe_reg2;
// synopsys translate_off
initial
absZ0_pipe_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg4 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg4 <= absZ0_pipe_reg3;
// synopsys translate_off
initial
absZ0_pipe_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg5 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg5 <= absZ0_pipe_reg4;
// synopsys translate_off
initial
absZ0_pipe_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg6 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg6 <= absZ0_pipe_reg5;
// synopsys translate_off
initial
absZ0_pipe_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg7 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg7 <= absZ0_pipe_reg6;
// synopsys translate_off
initial
absZ0_pipe_reg8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg8 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg8 <= absZ0_pipe_reg7;
// synopsys translate_off
initial
absZ0_pipe_reg9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg9 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg9 <= absZ0_pipe_reg8;
// synopsys translate_off
initial
absZ0s_pipe1_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0s_pipe1_reg0 <= 26'b0;
else if (clk_en == 1'b1) absZ0s_pipe1_reg0 <= absZ0s_pipe1;
// synopsys translate_off
initial
absZ0s_pipe1_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0s_pipe1_reg1 <= 26'b0;
else if (clk_en == 1'b1) absZ0s_pipe1_reg1 <= absZ0s_pipe1_reg0;
// synopsys translate_off
initial
absZ0s_pipe1_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0s_pipe1_reg2 <= 26'b0;
else if (clk_en == 1'b1) absZ0s_pipe1_reg2 <= absZ0s_pipe1_reg1;
// synopsys translate_off
initial
absZ0s_pipe1_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0s_pipe1_reg3 <= 26'b0;
else if (clk_en == 1'b1) absZ0s_pipe1_reg3 <= absZ0s_pipe1_reg2;
// synopsys translate_off
initial
absZ0s_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0s_reg0 <= 26'b0;
else if (clk_en == 1'b1) absZ0s_reg0 <= absZ0s;
// synopsys translate_off
initial
almostLog_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) almostLog_pipe_reg0 <= 83'b0;
else if (clk_en == 1'b1) almostLog_pipe_reg0 <= almostLog_pipe;
// synopsys translate_off
initial
almostLog_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) almostLog_pipe_reg1 <= 83'b0;
else if (clk_en == 1'b1) almostLog_pipe_reg1 <= almostLog_pipe_reg0;
// synopsys translate_off
initial
almostLog_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) almostLog_pipe_reg2 <= 83'b0;
else if (clk_en == 1'b1) almostLog_pipe_reg2 <= almostLog_pipe_reg1;
// synopsys translate_off
initial
doRR_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) doRR_reg0 <= 1'b0;
else if (clk_en == 1'b1) doRR_reg0 <= doRR;
// synopsys translate_off
initial
doRR_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) doRR_reg1 <= 1'b0;
else if (clk_en == 1'b1) doRR_reg1 <= doRR_reg0;
// synopsys translate_off
initial
E0_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg0 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg0 <= E0_pipe;
// synopsys translate_off
initial
E0_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg1 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg1 <= E0_pipe_reg0;
// synopsys translate_off
initial
E0_pipe_reg10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg10 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg10 <= E0_pipe_reg9;
// synopsys translate_off
initial
E0_pipe_reg11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg11 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg11 <= E0_pipe_reg10;
// synopsys translate_off
initial
E0_pipe_reg12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg12 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg12 <= E0_pipe_reg11;
// synopsys translate_off
initial
E0_pipe_reg13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg13 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg13 <= E0_pipe_reg12;
// synopsys translate_off
initial
E0_pipe_reg14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg14 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg14 <= E0_pipe_reg13;
// synopsys translate_off
initial
E0_pipe_reg15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg15 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg15 <= E0_pipe_reg14;
// synopsys translate_off
initial
E0_pipe_reg16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg16 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg16 <= E0_pipe_reg15;
// synopsys translate_off
initial
E0_pipe_reg17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg17 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg17 <= E0_pipe_reg16;
// synopsys translate_off
initial
E0_pipe_reg18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg18 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg18 <= E0_pipe_reg17;
// synopsys translate_off
initial
E0_pipe_reg19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg19 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg19 <= E0_pipe_reg18;
// synopsys translate_off
initial
E0_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg2 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg2 <= E0_pipe_reg1;
// synopsys translate_off
initial
E0_pipe_reg20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg20 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg20 <= E0_pipe_reg19;
// synopsys translate_off
initial
E0_pipe_reg21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg21 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg21 <= E0_pipe_reg20;
// synopsys translate_off
initial
E0_pipe_reg22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg22 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg22 <= E0_pipe_reg21;
// synopsys translate_off
initial
E0_pipe_reg23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg23 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg23 <= E0_pipe_reg22;
// synopsys translate_off
initial
E0_pipe_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg3 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg3 <= E0_pipe_reg2;
// synopsys translate_off
initial
E0_pipe_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg4 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg4 <= E0_pipe_reg3;
// synopsys translate_off
initial
E0_pipe_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg5 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg5 <= E0_pipe_reg4;
// synopsys translate_off
initial
E0_pipe_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg6 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg6 <= E0_pipe_reg5;
// synopsys translate_off
initial
E0_pipe_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg7 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg7 <= E0_pipe_reg6;
// synopsys translate_off
initial
E0_pipe_reg8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg8 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg8 <= E0_pipe_reg7;
// synopsys translate_off
initial
E0_pipe_reg9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg9 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg9 <= E0_pipe_reg8;
// synopsys translate_off
initial
E_normal_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E_normal_pipe_reg0 <= 6'b0;
else if (clk_en == 1'b1) E_normal_pipe_reg0 <= E_normal_pipe;
// synopsys translate_off
initial
exp_is_ebiase_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_is_ebiase_pipe_reg0 <= 1'b0;
else if (clk_en == 1'b1) exp_is_ebiase_pipe_reg0 <= exp_is_ebiase_pipe;
// synopsys translate_off
initial
exp_is_ebiase_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_is_ebiase_pipe_reg1 <= 1'b0;
else if (clk_en == 1'b1) exp_is_ebiase_pipe_reg1 <= exp_is_ebiase_pipe_reg0;
// synopsys translate_off
initial
exp_is_ebiase_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_is_ebiase_pipe_reg2 <= 1'b0;
else if (clk_en == 1'b1) exp_is_ebiase_pipe_reg2 <= exp_is_ebiase_pipe_reg1;
// synopsys translate_off
initial
input_is_infinity_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg0 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg0 <= input_is_infinity_pipe;
// synopsys translate_off
initial
input_is_infinity_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg1 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg1 <= input_is_infinity_pipe_reg0;
// synopsys translate_off
initial
input_is_infinity_pipe_reg10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg10 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg10 <= input_is_infinity_pipe_reg9;
// synopsys translate_off
initial
input_is_infinity_pipe_reg11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg11 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg11 <= input_is_infinity_pipe_reg10;
// synopsys translate_off
initial
input_is_infinity_pipe_reg12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg12 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg12 <= input_is_infinity_pipe_reg11;
// synopsys translate_off
initial
input_is_infinity_pipe_reg13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg13 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg13 <= input_is_infinity_pipe_reg12;
// synopsys translate_off
initial
input_is_infinity_pipe_reg14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg14 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg14 <= input_is_infinity_pipe_reg13;
// synopsys translate_off
initial
input_is_infinity_pipe_reg15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg15 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg15 <= input_is_infinity_pipe_reg14;
// synopsys translate_off
initial
input_is_infinity_pipe_reg16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg16 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg16 <= input_is_infinity_pipe_reg15;
// synopsys translate_off
initial
input_is_infinity_pipe_reg17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg17 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg17 <= input_is_infinity_pipe_reg16;
// synopsys translate_off
initial
input_is_infinity_pipe_reg18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg18 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg18 <= input_is_infinity_pipe_reg17;
// synopsys translate_off
initial
input_is_infinity_pipe_reg19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg19 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg19 <= input_is_infinity_pipe_reg18;
// synopsys translate_off
initial
input_is_infinity_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg2 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg2 <= input_is_infinity_pipe_reg1;
// synopsys translate_off
initial
input_is_infinity_pipe_reg20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg20 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg20 <= input_is_infinity_pipe_reg19;
// synopsys translate_off
initial
input_is_infinity_pipe_reg21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg21 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg21 <= input_is_infinity_pipe_reg20;
// synopsys translate_off
initial
input_is_infinity_pipe_reg22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg22 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg22 <= input_is_infinity_pipe_reg21;
// synopsys translate_off
initial
input_is_infinity_pipe_reg23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg23 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg23 <= input_is_infinity_pipe_reg22;
// synopsys translate_off
initial
input_is_infinity_pipe_reg24 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg24 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg24 <= input_is_infinity_pipe_reg23;
// synopsys translate_off
initial
input_is_infinity_pipe_reg25 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg25 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg25 <= input_is_infinity_pipe_reg24;
// synopsys translate_off
initial
input_is_infinity_pipe_reg26 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg26 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg26 <= input_is_infinity_pipe_reg25;
// synopsys translate_off
initial
input_is_infinity_pipe_reg27 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg27 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg27 <= input_is_infinity_pipe_reg26;
// synopsys translate_off
initial
input_is_infinity_pipe_reg28 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg28 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg28 <= input_is_infinity_pipe_reg27;
// synopsys translate_off
initial
input_is_infinity_pipe_reg29 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg29 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg29 <= input_is_infinity_pipe_reg28;
// synopsys translate_off
initial
input_is_infinity_pipe_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg3 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg3 <= input_is_infinity_pipe_reg2;
// synopsys translate_off
initial
input_is_infinity_pipe_reg30 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg30 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg30 <= input_is_infinity_pipe_reg29;
// synopsys translate_off
initial
input_is_infinity_pipe_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg4 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg4 <= input_is_infinity_pipe_reg3;
// synopsys translate_off
initial
input_is_infinity_pipe_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg5 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg5 <= input_is_infinity_pipe_reg4;
// synopsys translate_off
initial
input_is_infinity_pipe_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg6 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg6 <= input_is_infinity_pipe_reg5;
// synopsys translate_off
initial
input_is_infinity_pipe_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg7 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg7 <= input_is_infinity_pipe_reg6;
// synopsys translate_off
initial
input_is_infinity_pipe_reg8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg8 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg8 <= input_is_infinity_pipe_reg7;
// synopsys translate_off
initial
input_is_infinity_pipe_reg9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg9 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg9 <= input_is_infinity_pipe_reg8;
// synopsys translate_off
initial
input_is_nan_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg0 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg0 <= input_is_nan_pipe;
// synopsys translate_off
initial
input_is_nan_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg1 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg1 <= input_is_nan_pipe_reg0;
// synopsys translate_off
initial
input_is_nan_pipe_reg10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg10 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg10 <= input_is_nan_pipe_reg9;
// synopsys translate_off
initial
input_is_nan_pipe_reg11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg11 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg11 <= input_is_nan_pipe_reg10;
// synopsys translate_off
initial
input_is_nan_pipe_reg12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg12 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg12 <= input_is_nan_pipe_reg11;
// synopsys translate_off
initial
input_is_nan_pipe_reg13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg13 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg13 <= input_is_nan_pipe_reg12;
// synopsys translate_off
initial
input_is_nan_pipe_reg14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg14 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg14 <= input_is_nan_pipe_reg13;
// synopsys translate_off
initial
input_is_nan_pipe_reg15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg15 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg15 <= input_is_nan_pipe_reg14;
// synopsys translate_off
initial
input_is_nan_pipe_reg16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg16 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg16 <= input_is_nan_pipe_reg15;
// synopsys translate_off
initial
input_is_nan_pipe_reg17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg17 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg17 <= input_is_nan_pipe_reg16;
// synopsys translate_off
initial
input_is_nan_pipe_reg18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg18 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg18 <= input_is_nan_pipe_reg17;
// synopsys translate_off
initial
input_is_nan_pipe_reg19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg19 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg19 <= input_is_nan_pipe_reg18;
// synopsys translate_off
initial
input_is_nan_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg2 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg2 <= input_is_nan_pipe_reg1;
// synopsys translate_off
initial
input_is_nan_pipe_reg20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg20 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg20 <= input_is_nan_pipe_reg19;
// synopsys translate_off
initial
input_is_nan_pipe_reg21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg21 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg21 <= input_is_nan_pipe_reg20;
// synopsys translate_off
initial
input_is_nan_pipe_reg22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg22 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg22 <= input_is_nan_pipe_reg21;
// synopsys translate_off
initial
input_is_nan_pipe_reg23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg23 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg23 <= input_is_nan_pipe_reg22;
// synopsys translate_off
initial
input_is_nan_pipe_reg24 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg24 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg24 <= input_is_nan_pipe_reg23;
// synopsys translate_off
initial
input_is_nan_pipe_reg25 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg25 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg25 <= input_is_nan_pipe_reg24;
// synopsys translate_off
initial
input_is_nan_pipe_reg26 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg26 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg26 <= input_is_nan_pipe_reg25;
// synopsys translate_off
initial
input_is_nan_pipe_reg27 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg27 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg27 <= input_is_nan_pipe_reg26;
// synopsys translate_off
initial
input_is_nan_pipe_reg28 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg28 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg28 <= input_is_nan_pipe_reg27;
// synopsys translate_off
initial
input_is_nan_pipe_reg29 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg29 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg29 <= input_is_nan_pipe_reg28;
// synopsys translate_off
initial
input_is_nan_pipe_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg3 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg3 <= input_is_nan_pipe_reg2;
// synopsys translate_off
initial
input_is_nan_pipe_reg30 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg30 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg30 <= input_is_nan_pipe_reg29;
// synopsys translate_off
initial
input_is_nan_pipe_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg4 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg4 <= input_is_nan_pipe_reg3;
// synopsys translate_off
initial
input_is_nan_pipe_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg5 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg5 <= input_is_nan_pipe_reg4;
// synopsys translate_off
initial
input_is_nan_pipe_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg6 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg6 <= input_is_nan_pipe_reg5;
// synopsys translate_off
initial
input_is_nan_pipe_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg7 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg7 <= input_is_nan_pipe_reg6;
// synopsys translate_off
initial
input_is_nan_pipe_reg8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg8 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg8 <= input_is_nan_pipe_reg7;
// synopsys translate_off
initial
input_is_nan_pipe_reg9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg9 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg9 <= input_is_nan_pipe_reg8;
// synopsys translate_off
initial
input_is_one_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg0 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg0 <= input_is_one_pipe;
// synopsys translate_off
initial
input_is_one_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg1 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg1 <= input_is_one_pipe_reg0;
// synopsys translate_off
initial
input_is_one_pipe_reg10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg10 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg10 <= input_is_one_pipe_reg9;
// synopsys translate_off
initial
input_is_one_pipe_reg11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg11 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg11 <= input_is_one_pipe_reg10;
// synopsys translate_off
initial
input_is_one_pipe_reg12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg12 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg12 <= input_is_one_pipe_reg11;
// synopsys translate_off
initial
input_is_one_pipe_reg13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg13 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg13 <= input_is_one_pipe_reg12;
// synopsys translate_off
initial
input_is_one_pipe_reg14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg14 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg14 <= input_is_one_pipe_reg13;
// synopsys translate_off
initial
input_is_one_pipe_reg15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg15 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg15 <= input_is_one_pipe_reg14;
// synopsys translate_off
initial
input_is_one_pipe_reg16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg16 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg16 <= input_is_one_pipe_reg15;
// synopsys translate_off
initial
input_is_one_pipe_reg17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg17 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg17 <= input_is_one_pipe_reg16;
// synopsys translate_off
initial
input_is_one_pipe_reg18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg18 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg18 <= input_is_one_pipe_reg17;
// synopsys translate_off
initial
input_is_one_pipe_reg19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg19 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg19 <= input_is_one_pipe_reg18;
// synopsys translate_off
initial
input_is_one_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg2 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg2 <= input_is_one_pipe_reg1;
// synopsys translate_off
initial
input_is_one_pipe_reg20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg20 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg20 <= input_is_one_pipe_reg19;
// synopsys translate_off
initial
input_is_one_pipe_reg21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg21 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg21 <= input_is_one_pipe_reg20;
// synopsys translate_off
initial
input_is_one_pipe_reg22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg22 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg22 <= input_is_one_pipe_reg21;
// synopsys translate_off
initial
input_is_one_pipe_reg23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg23 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg23 <= input_is_one_pipe_reg22;
// synopsys translate_off
initial
input_is_one_pipe_reg24 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg24 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg24 <= input_is_one_pipe_reg23;
// synopsys translate_off
initial
input_is_one_pipe_reg25 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg25 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg25 <= input_is_one_pipe_reg24;
// synopsys translate_off
initial
input_is_one_pipe_reg26 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg26 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg26 <= input_is_one_pipe_reg25;
// synopsys translate_off
initial
input_is_one_pipe_reg27 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg27 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg27 <= input_is_one_pipe_reg26;
// synopsys translate_off
initial
input_is_one_pipe_reg28 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg28 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg28 <= input_is_one_pipe_reg27;
// synopsys translate_off
initial
input_is_one_pipe_reg29 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg29 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg29 <= input_is_one_pipe_reg28;
// synopsys translate_off
initial
input_is_one_pipe_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg3 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg3 <= input_is_one_pipe_reg2;
// synopsys translate_off
initial
input_is_one_pipe_reg30 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg30 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg30 <= input_is_one_pipe_reg29;
// synopsys translate_off
initial
input_is_one_pipe_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg4 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg4 <= input_is_one_pipe_reg3;
// synopsys translate_off
initial
input_is_one_pipe_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg5 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg5 <= input_is_one_pipe_reg4;
// synopsys translate_off
initial
input_is_one_pipe_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg6 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg6 <= input_is_one_pipe_reg5;
// synopsys translate_off
initial
input_is_one_pipe_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg7 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg7 <= input_is_one_pipe_reg6;
// synopsys translate_off
initial
input_is_one_pipe_reg8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg8 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg8 <= input_is_one_pipe_reg7;
// synopsys translate_off
initial
input_is_one_pipe_reg9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg9 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg9 <= input_is_one_pipe_reg8;
// synopsys translate_off
initial
input_is_zero_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg0 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg0 <= input_is_zero_pipe;
// synopsys translate_off
initial
input_is_zero_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg1 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg1 <= input_is_zero_pipe_reg0;
// synopsys translate_off
initial
input_is_zero_pipe_reg10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg10 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg10 <= input_is_zero_pipe_reg9;
// synopsys translate_off
initial
input_is_zero_pipe_reg11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg11 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg11 <= input_is_zero_pipe_reg10;
// synopsys translate_off
initial
input_is_zero_pipe_reg12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg12 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg12 <= input_is_zero_pipe_reg11;
// synopsys translate_off
initial
input_is_zero_pipe_reg13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg13 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg13 <= input_is_zero_pipe_reg12;
// synopsys translate_off
initial
input_is_zero_pipe_reg14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg14 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg14 <= input_is_zero_pipe_reg13;
// synopsys translate_off
initial
input_is_zero_pipe_reg15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg15 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg15 <= input_is_zero_pipe_reg14;
// synopsys translate_off
initial
input_is_zero_pipe_reg16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg16 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg16 <= input_is_zero_pipe_reg15;
// synopsys translate_off
initial
input_is_zero_pipe_reg17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg17 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg17 <= input_is_zero_pipe_reg16;
// synopsys translate_off
initial
input_is_zero_pipe_reg18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg18 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg18 <= input_is_zero_pipe_reg17;
// synopsys translate_off
initial
input_is_zero_pipe_reg19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg19 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg19 <= input_is_zero_pipe_reg18;
// synopsys translate_off
initial
input_is_zero_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg2 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg2 <= input_is_zero_pipe_reg1;
// synopsys translate_off
initial
input_is_zero_pipe_reg20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg20 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg20 <= input_is_zero_pipe_reg19;
// synopsys translate_off
initial
input_is_zero_pipe_reg21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg21 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg21 <= input_is_zero_pipe_reg20;
// synopsys translate_off
initial
input_is_zero_pipe_reg22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg22 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg22 <= input_is_zero_pipe_reg21;
// synopsys translate_off
initial
input_is_zero_pipe_reg23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg23 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg23 <= input_is_zero_pipe_reg22;
// synopsys translate_off
initial
input_is_zero_pipe_reg24 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg24 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg24 <= input_is_zero_pipe_reg23;
// synopsys translate_off
initial
input_is_zero_pipe_reg25 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg25 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg25 <= input_is_zero_pipe_reg24;
// synopsys translate_off
initial
input_is_zero_pipe_reg26 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg26 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg26 <= input_is_zero_pipe_reg25;
// synopsys translate_off
initial
input_is_zero_pipe_reg27 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg27 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg27 <= input_is_zero_pipe_reg26;
// synopsys translate_off
initial
input_is_zero_pipe_reg28 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg28 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg28 <= input_is_zero_pipe_reg27;
// synopsys translate_off
initial
input_is_zero_pipe_reg29 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg29 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg29 <= input_is_zero_pipe_reg28;
// synopsys translate_off
initial
input_is_zero_pipe_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg3 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg3 <= input_is_zero_pipe_reg2;
// synopsys translate_off
initial
input_is_zero_pipe_reg30 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg30 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg30 <= input_is_zero_pipe_reg29;
// synopsys translate_off
initial
input_is_zero_pipe_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg4 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg4 <= input_is_zero_pipe_reg3;
// synopsys translate_off
initial
input_is_zero_pipe_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg5 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg5 <= input_is_zero_pipe_reg4;
// synopsys translate_off
initial
input_is_zero_pipe_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg6 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg6 <= input_is_zero_pipe_reg5;
// synopsys translate_off
initial
input_is_zero_pipe_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg7 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg7 <= input_is_zero_pipe_reg6;
// synopsys translate_off
initial
input_is_zero_pipe_reg8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg8 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg8 <= input_is_zero_pipe_reg7;
// synopsys translate_off
initial
input_is_zero_pipe_reg9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg9 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg9 <= input_is_zero_pipe_reg8;
// synopsys translate_off
initial
Log_normal_normd_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Log_normal_normd_pipe_reg0 <= 94'b0;
else if (clk_en == 1'b1) Log_normal_normd_pipe_reg0 <= Log_normal_normd_pipe;
// synopsys translate_off
initial
Log_normal_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Log_normal_reg0 <= 94'b0;
else if (clk_en == 1'b1) Log_normal_reg0 <= Log_normal;
// synopsys translate_off
initial
Log_small_normd_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Log_small_normd_pipe_reg0 <= 57'b0;
else if (clk_en == 1'b1) Log_small_normd_pipe_reg0 <= Log_small_normd_pipe;
// synopsys translate_off
initial
Log_small_normd_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Log_small_normd_pipe_reg1 <= 57'b0;
else if (clk_en == 1'b1) Log_small_normd_pipe_reg1 <= Log_small_normd_pipe_reg0;
// synopsys translate_off
initial
Lshiftval_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Lshiftval_reg0 <= 7'b0;
else if (clk_en == 1'b1) Lshiftval_reg0 <= Lshiftval;
// synopsys translate_off
initial
Lshiftval_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Lshiftval_reg1 <= 7'b0;
else if (clk_en == 1'b1) Lshiftval_reg1 <= Lshiftval_reg0;
// synopsys translate_off
initial
Lshiftval_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Lshiftval_reg2 <= 7'b0;
else if (clk_en == 1'b1) Lshiftval_reg2 <= Lshiftval_reg1;
// synopsys translate_off
initial
Lshiftval_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Lshiftval_reg3 <= 7'b0;
else if (clk_en == 1'b1) Lshiftval_reg3 <= Lshiftval_reg2;
// synopsys translate_off
initial
lzo_pipe1_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg0 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg0 <= lzo_pipe1;
// synopsys translate_off
initial
lzo_pipe1_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg1 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg1 <= lzo_pipe1_reg0;
// synopsys translate_off
initial
lzo_pipe1_reg10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg10 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg10 <= lzo_pipe1_reg9;
// synopsys translate_off
initial
lzo_pipe1_reg11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg11 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg11 <= lzo_pipe1_reg10;
// synopsys translate_off
initial
lzo_pipe1_reg12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg12 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg12 <= lzo_pipe1_reg11;
// synopsys translate_off
initial
lzo_pipe1_reg13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg13 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg13 <= lzo_pipe1_reg12;
// synopsys translate_off
initial
lzo_pipe1_reg14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg14 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg14 <= lzo_pipe1_reg13;
// synopsys translate_off
initial
lzo_pipe1_reg15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg15 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg15 <= lzo_pipe1_reg14;
// synopsys translate_off
initial
lzo_pipe1_reg16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg16 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg16 <= lzo_pipe1_reg15;
// synopsys translate_off
initial
lzo_pipe1_reg17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg17 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg17 <= lzo_pipe1_reg16;
// synopsys translate_off
initial
lzo_pipe1_reg18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg18 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg18 <= lzo_pipe1_reg17;
// synopsys translate_off
initial
lzo_pipe1_reg19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg19 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg19 <= lzo_pipe1_reg18;
// synopsys translate_off
initial
lzo_pipe1_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg2 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg2 <= lzo_pipe1_reg1;
// synopsys translate_off
initial
lzo_pipe1_reg20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg20 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg20 <= lzo_pipe1_reg19;
// synopsys translate_off
initial
lzo_pipe1_reg21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg21 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg21 <= lzo_pipe1_reg20;
// synopsys translate_off
initial
lzo_pipe1_reg22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg22 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg22 <= lzo_pipe1_reg21;
// synopsys translate_off
initial
lzo_pipe1_reg23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg23 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg23 <= lzo_pipe1_reg22;
// synopsys translate_off
initial
lzo_pipe1_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg3 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg3 <= lzo_pipe1_reg2;
// synopsys translate_off
initial
lzo_pipe1_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg4 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg4 <= lzo_pipe1_reg3;
// synopsys translate_off
initial
lzo_pipe1_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg5 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg5 <= lzo_pipe1_reg4;
// synopsys translate_off
initial
lzo_pipe1_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg6 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg6 <= lzo_pipe1_reg5;
// synopsys translate_off
initial
lzo_pipe1_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg7 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg7 <= lzo_pipe1_reg6;
// synopsys translate_off
initial
lzo_pipe1_reg8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg8 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg8 <= lzo_pipe1_reg7;
// synopsys translate_off
initial
lzo_pipe1_reg9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg9 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg9 <= lzo_pipe1_reg8;
// synopsys translate_off
initial
lzo_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_reg0 <= 6'b0;
else if (clk_en == 1'b1) lzo_reg0 <= lzo;
// synopsys translate_off
initial
lzo_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_reg1 <= 6'b0;
else if (clk_en == 1'b1) lzo_reg1 <= lzo_reg0;
// synopsys translate_off
initial
lzo_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_reg2 <= 6'b0;
else if (clk_en == 1'b1) lzo_reg2 <= lzo_reg1;
// synopsys translate_off
initial
lzo_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_reg3 <= 6'b0;
else if (clk_en == 1'b1) lzo_reg3 <= lzo_reg2;
// synopsys translate_off
initial
lzo_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_reg4 <= 6'b0;
else if (clk_en == 1'b1) lzo_reg4 <= lzo_reg3;
// synopsys translate_off
initial
lzo_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_reg5 <= 6'b0;
else if (clk_en == 1'b1) lzo_reg5 <= lzo_reg4;
// synopsys translate_off
initial
lzo_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_reg6 <= 6'b0;
else if (clk_en == 1'b1) lzo_reg6 <= lzo_reg5;
// synopsys translate_off
initial
sign_data_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_data_reg0 <= 1'b0;
else if (clk_en == 1'b1) sign_data_reg0 <= sign_data;
// synopsys translate_off
initial
sign_data_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_data_reg1 <= 1'b0;
else if (clk_en == 1'b1) sign_data_reg1 <= sign_data_reg0;
// synopsys translate_off
initial
sign_data_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_data_reg2 <= 1'b0;
else if (clk_en == 1'b1) sign_data_reg2 <= sign_data_reg1;
// synopsys translate_off
initial
small_flag_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) small_flag_pipe_reg0 <= 1'b0;
else if (clk_en == 1'b1) small_flag_pipe_reg0 <= small_flag_pipe;
// synopsys translate_off
initial
small_flag_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) small_flag_pipe_reg1 <= 1'b0;
else if (clk_en == 1'b1) small_flag_pipe_reg1 <= small_flag_pipe_reg0;
// synopsys translate_off
initial
small_flag_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) small_flag_pipe_reg2 <= 1'b0;
else if (clk_en == 1'b1) small_flag_pipe_reg2 <= small_flag_pipe_reg1;
// synopsys translate_off
initial
small_flag_pipe_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) small_flag_pipe_reg3 <= 1'b0;
else if (clk_en == 1'b1) small_flag_pipe_reg3 <= small_flag_pipe_reg2;
// synopsys translate_off
initial
small_flag_pipe_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) small_flag_pipe_reg4 <= 1'b0;
else if (clk_en == 1'b1) small_flag_pipe_reg4 <= small_flag_pipe_reg3;
// synopsys translate_off
initial
small_flag_pipe_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) small_flag_pipe_reg5 <= 1'b0;
else if (clk_en == 1'b1) small_flag_pipe_reg5 <= small_flag_pipe_reg4;
// synopsys translate_off
initial
small_flag_pipe_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) small_flag_pipe_reg6 <= 1'b0;
else if (clk_en == 1'b1) small_flag_pipe_reg6 <= small_flag_pipe_reg5;
// synopsys translate_off
initial
small_flag_pipe_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) small_flag_pipe_reg7 <= 1'b0;
else if (clk_en == 1'b1) small_flag_pipe_reg7 <= small_flag_pipe_reg6;
// synopsys translate_off
initial
small_flag_pipe_reg8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) small_flag_pipe_reg8 <= 1'b0;
else if (clk_en == 1'b1) small_flag_pipe_reg8 <= small_flag_pipe_reg7;
// synopsys translate_off
initial
sR_pipe1_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg0 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg0 <= sR_pipe1;
// synopsys translate_off
initial
sR_pipe1_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg1 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg1 <= sR_pipe1_reg0;
// synopsys translate_off
initial
sR_pipe1_reg10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg10 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg10 <= sR_pipe1_reg9;
// synopsys translate_off
initial
sR_pipe1_reg11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg11 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg11 <= sR_pipe1_reg10;
// synopsys translate_off
initial
sR_pipe1_reg12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg12 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg12 <= sR_pipe1_reg11;
// synopsys translate_off
initial
sR_pipe1_reg13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg13 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg13 <= sR_pipe1_reg12;
// synopsys translate_off
initial
sR_pipe1_reg14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg14 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg14 <= sR_pipe1_reg13;
// synopsys translate_off
initial
sR_pipe1_reg15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg15 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg15 <= sR_pipe1_reg14;
// synopsys translate_off
initial
sR_pipe1_reg16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg16 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg16 <= sR_pipe1_reg15;
// synopsys translate_off
initial
sR_pipe1_reg17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg17 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg17 <= sR_pipe1_reg16;
// synopsys translate_off
initial
sR_pipe1_reg18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg18 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg18 <= sR_pipe1_reg17;
// synopsys translate_off
initial
sR_pipe1_reg19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg19 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg19 <= sR_pipe1_reg18;
// synopsys translate_off
initial
sR_pipe1_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg2 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg2 <= sR_pipe1_reg1;
// synopsys translate_off
initial
sR_pipe1_reg20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg20 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg20 <= sR_pipe1_reg19;
// synopsys translate_off
initial
sR_pipe1_reg21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg21 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg21 <= sR_pipe1_reg20;
// synopsys translate_off
initial
sR_pipe1_reg22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg22 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg22 <= sR_pipe1_reg21;
// synopsys translate_off
initial
sR_pipe1_reg23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg23 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg23 <= sR_pipe1_reg22;
// synopsys translate_off
initial
sR_pipe1_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg3 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg3 <= sR_pipe1_reg2;
// synopsys translate_off
initial
sR_pipe1_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg4 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg4 <= sR_pipe1_reg3;
// synopsys translate_off
initial
sR_pipe1_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg5 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg5 <= sR_pipe1_reg4;
// synopsys translate_off
initial
sR_pipe1_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg6 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg6 <= sR_pipe1_reg5;
// synopsys translate_off
initial
sR_pipe1_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg7 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg7 <= sR_pipe1_reg6;
// synopsys translate_off
initial
sR_pipe1_reg8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg8 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg8 <= sR_pipe1_reg7;
// synopsys translate_off
initial
sR_pipe1_reg9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg9 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg9 <= sR_pipe1_reg8;
// synopsys translate_off
initial
sR_pipe2_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe2_reg0 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe2_reg0 <= sR_pipe2;
// synopsys translate_off
initial
sR_pipe2_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe2_reg1 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe2_reg1 <= sR_pipe2_reg0;
// synopsys translate_off
initial
sR_pipe2_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe2_reg2 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe2_reg2 <= sR_pipe2_reg1;
// synopsys translate_off
initial
sR_pipe2_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe2_reg3 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe2_reg3 <= sR_pipe2_reg2;
// synopsys translate_off
initial
sR_pipe2_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe2_reg4 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe2_reg4 <= sR_pipe2_reg3;
// synopsys translate_off
initial
sR_pipe2_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe2_reg5 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe2_reg5 <= sR_pipe2_reg4;
// synopsys translate_off
initial
sR_pipe3_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe3_reg0 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe3_reg0 <= sR_pipe3;
// synopsys translate_off
initial
sR_pipe3_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe3_reg1 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe3_reg1 <= sR_pipe3_reg0;
// synopsys translate_off
initial
sR_pipe3_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe3_reg2 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe3_reg2 <= sR_pipe3_reg1;
// synopsys translate_off
initial
sR_pipe3_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe3_reg3 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe3_reg3 <= sR_pipe3_reg2;
// synopsys translate_off
initial
Z2o2_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Z2o2_pipe_reg0 <= 28'b0;
else if (clk_en == 1'b1) Z2o2_pipe_reg0 <= Z2o2_pipe;
// synopsys translate_off
initial
Z2o2_small_s_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Z2o2_small_s_pipe_reg0 <= 28'b0;
else if (clk_en == 1'b1) Z2o2_small_s_pipe_reg0 <= Z2o2_small_s_pipe;
// synopsys translate_off
initial
Zfinal_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Zfinal_reg0 <= 55'b0;
else if (clk_en == 1'b1) Zfinal_reg0 <= Zfinal;
// synopsys translate_off
initial
Zfinal_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Zfinal_reg1 <= 55'b0;
else if (clk_en == 1'b1) Zfinal_reg1 <= Zfinal_reg0;
lpm_add_sub addsub1
(
.add_sub(sR_pipe3),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa(Z_small),
.datab(Z2o2_small),
.overflow(),
.result(wire_addsub1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
addsub1.lpm_pipeline = 1,
addsub1.lpm_representation = "UNSIGNED",
addsub1.lpm_width = 59,
addsub1.lpm_type = "lpm_add_sub";
lpm_add_sub addsub2
(
.add_sub((~ sR_pipe3)),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa(absELog2_pad),
.datab(LogF_normal_pad),
.overflow(),
.result(wire_addsub2_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
addsub2.lpm_pipeline = 1,
addsub2.lpm_representation = "UNSIGNED",
addsub2.lpm_width = 94,
addsub2.lpm_type = "lpm_add_sub";
lpm_mult mult1
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(absE),
.datab(Log2),
.result(wire_mult1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
mult1.lpm_pipeline = 3,
mult1.lpm_representation = "UNSIGNED",
mult1.lpm_widtha = 11,
mult1.lpm_widthb = 57,
mult1.lpm_widthp = 68,
mult1.lpm_type = "lpm_mult";
assign wire_mux_result0a_dataout = ((((input_is_zero | input_is_infinity) | input_is_nan) | input_is_one) === 1'b1) ? {{11{((~ input_is_one) | input_is_nan)}}, input_is_nan, {51{1'b0}}} : EFR;
assign
absE = (({11{(~ sR_pipe2)}} & E0) | ({11{sR_pipe2}} & wire_sub2_result)),
absELog2 = absELog2_pipe_reg2,
absELog2_pad = {absELog2, {26{1'b0}}},
absELog2_pipe = wire_mult1_result,
absZ0 = absZ0_pipe_reg23,
absZ0_pipe = (({26{(~ sR_pipe1)}} & Y0[25:0]) | ({26{sR_pipe1}} & wire_sub1_result)),
absZ0s = wire_Lshiftsmall_result[63:38],
absZ0s_pipe1 = absZ0s_reg0,
absZ0s_pipe2 = absZ0s_pipe1_reg3,
aclr = 1'b0,
almostLog = almostLog_pipe_reg2,
almostLog_pipe = wire_range_reduction_almostlog,
data_exp_is_ebiase = {((~ exp_data[10]) & data_exp_is_ebiase[9]), (exp_data[9] & data_exp_is_ebiase[8]), (exp_data[8] & data_exp_is_ebiase[7]), (exp_data[7] & data_exp_is_ebiase[6]), (exp_data[6] & data_exp_is_ebiase[5]), (exp_data[5] & data_exp_is_ebiase[4]), (exp_data[4] & data_exp_is_ebiase[3]), (exp_data[3] & data_exp_is_ebiase[2]), (exp_data[2] & data_exp_is_ebiase[1]), (exp_data[1] & data_exp_is_ebiase[0]), exp_data[0]},
doRR = Lshiftval[6],
doRR_pipe = doRR_reg1,
E0 = E0_pipe_reg23,
E0_is_zero = {((~ E0[10]) & E0_is_zero[9]), ((~ E0[9]) & E0_is_zero[8]), ((~ E0[8]) & E0_is_zero[7]), ((~ E0[7]) & E0_is_zero[6]), ((~ E0[6]) & E0_is_zero[5]), ((~ E0[5]) & E0_is_zero[4]), ((~ E0[4]) & E0_is_zero[3]), ((~ E0[3]) & E0_is_zero[2]), ((~ E0[2]) & E0_is_zero[1]), ((~ E0[1]) & E0_is_zero[0]), (~ E0[0])},
E0_pipe = wire_exp_biase_sub_result,
E0_sub = {(Log_small[58] | Log_small[57]), (Log_small[58] | (~ Log_small[57]))},
E0offset = 11'b10000001001,
E_normal = E_normal_pipe_reg0,
E_normal_pipe = wire_lzc_norm_E_q[5:0],
E_small = wire_sub5_result,
EFR = wire_add2_result,
ER = (({11{(~ small_flag)}} & wire_sub6_result) | ({11{small_flag}} & E_small)),
exp_all_one = wire_exp_nan_result,
exp_all_zero = wire_exp_zero_result,
exp_biase = {10'b0111111111, (~ First_bit)},
exp_data = data[62:52],
exp_is_ebiase = exp_is_ebiase_pipe_reg2,
exp_is_ebiase_pipe = data_exp_is_ebiase[10],
First_bit = man_data[51],
input_is_infinity = input_is_infinity_pipe_reg30,
input_is_infinity_pipe = (exp_all_one & (~ man_all_zero)),
input_is_nan = input_is_nan_pipe_reg30,
input_is_nan_pipe = ((exp_all_one & man_not_zero) | sign_data_pipe),
input_is_one = input_is_one_pipe_reg30,
input_is_one_pipe = (exp_is_ebiase & (~ man_all_zero)),
input_is_zero = input_is_zero_pipe_reg30,
input_is_zero_pipe = (~ exp_all_zero),
Log1p_normal = wire_sub4_result,
Log2 = 57'b101100010111001000010111111101111101000111001111011110011,
Log_g = (({57{(~ small_flag)}} & Log_normal_normd[92:36]) | ({57{small_flag}} & {Log_small_normd[55:0], 1'b0})),
Log_normal = wire_addsub2_result,
Log_normal_normd = Log_normal_normd_pipe_reg0,
Log_normal_normd_pipe = wire_lzc_norm_L_result[127:34],
Log_normal_pipe = Log_normal_reg0,
Log_small = wire_addsub1_result,
Log_small1 = (({57{(~ Log_small[57])}} & Log_small[56:0]) | ({57{Log_small[57]}} & Log_small[57:1])),
Log_small2 = (({57{(~ Log_small[58])}} & Log_small1) | ({57{Log_small[58]}} & Log_small[58:2])),
Log_small_normd = Log_small_normd_pipe_reg1,
Log_small_normd_pipe = Log_small2,
LogF_normal = wire_add1_result,
LogF_normal_pad = {{11{LogF_normal[82]}}, LogF_normal},
Lshiftval = wire_sub3_result,
lzo = lzo_pipe1_reg23,
lzo_pipe1 = (~ wire_lzoc_q),
lzo_pipe2 = lzo_reg6,
man_above_half = {1'b0, 1'b1, man_data},
man_all_zero = wire_man_inf_result,
man_below_half = {1'b1, man_data, 1'b0},
man_data = data[51:0],
man_not_zero = wire_man_nan_result,
pfinal_s = 6'b011100,
result = {(((sR | input_is_zero) | input_is_nan) & (~ input_is_one)), wire_mux_result0a_dataout},
round = (Log_g[4] & (Log_g[5] | sticky[3])),
Rshiftval = Lshiftval_reg3,
sign_data = data[63],
sign_data_pipe = sign_data_reg2,
small_flag = small_flag_pipe_reg8,
small_flag_pipe = ((~ doRR) & E0_is_zero[10]),
squarerIn = (({27{(~ doRR_pipe)}} & squarerIn0) | ({27{doRR_pipe}} & squarerIn1)),
squarerIn0 = {absZ0s_pipe1, 1'b0},
squarerIn1 = Zfinal[54:28],
sR = sR_pipe3_reg3,
sR_pipe1 = (~ (data_exp_is_ebiase[10] | exp_data[10])),
sR_pipe2 = sR_pipe1_reg23,
sR_pipe3 = sR_pipe2_reg5,
sticky = {(Log_g[3] | sticky[2]), (Log_g[2] | sticky[1]), (Log_g[1] | sticky[0]), Log_g[0]},
Y0 = (({54{(~ First_bit)}} & man_below_half) | ({54{First_bit}} & man_above_half)),
Z2o2 = Z2o2_pipe_reg0,
Z2o2_pipe = wire_squarer_result,
Z2o2_small = {{28{1'b0}}, Z2o2_small_s, {3{1'b0}}},
Z2o2_small_s = Z2o2_small_s_pipe_reg0,
Z2o2_small_s_pipe = wire_Rshiftsmall_result[63:36],
Z_small = {absZ0s_pipe2, {33{1'b0}}},
Zfinal = wire_range_reduction_z,
Zfinal_pipe = Zfinal_reg1;
endmodule //acl_fp_log_double_altfp_log_17b
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_log_double (
enable,
clock,
dataa,
result);
input enable;
input clock;
input [63:0] dataa;
output [63:0] result;
wire [63:0] sub_wire0;
wire [63:0] result = sub_wire0[63:0];
acl_fp_log_double_altfp_log_17b acl_fp_log_double_altfp_log_17b_component (
.clk_en (enable),
.clock (clock),
.data (dataa),
.result (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altfp_log"
// Retrieval info: CONSTANT: PIPELINE NUMERIC "34"
// Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "52"
// Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en"
// Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: USED_PORT: data 0 0 64 0 INPUT NODEFVAL "data[63..0]"
// Retrieval info: CONNECT: @data 0 0 64 0 data 0 0 64 0
// Retrieval info: USED_PORT: result 0 0 64 0 OUTPUT NODEFVAL "result[63..0]"
// Retrieval info: CONNECT: result 0 0 64 0 @result 0 0 64 0
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_log_double.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_log_double.qip TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_log_double.bsf FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_log_double_inst.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_log_double_bb.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_log_double.inc FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_log_double.cmp FALSE TRUE
// Retrieval info: LIB_FILE: lpm
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2005 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
localparam // synopsys enum En_State
EP_State_IDLE = {3'b000,5'd00},
EP_State_CMDSHIFT0 = {3'b001,5'd00},
EP_State_CMDSHIFT13 = {3'b001,5'd13},
EP_State_CMDSHIFT14 = {3'b001,5'd14},
EP_State_CMDSHIFT15 = {3'b001,5'd15},
EP_State_CMDSHIFT16 = {3'b001,5'd16},
EP_State_DWAIT = {3'b010,5'd00},
EP_State_DSHIFT0 = {3'b100,5'd00},
EP_State_DSHIFT1 = {3'b100,5'd01},
EP_State_DSHIFT15 = {3'b100,5'd15};
reg [7:0] /* synopsys enum En_State */
m_state_xr; // Last command, for debugging
/*AUTOASCIIENUM("m_state_xr", "m_stateAscii_xr", "EP_State_")*/
// Beginning of automatic ASCII enum decoding
reg [79:0] m_stateAscii_xr; // Decode of m_state_xr
always @(m_state_xr) begin
case ({m_state_xr})
EP_State_IDLE: m_stateAscii_xr = "idle ";
EP_State_CMDSHIFT0: m_stateAscii_xr = "cmdshift0 ";
EP_State_CMDSHIFT13: m_stateAscii_xr = "cmdshift13";
EP_State_CMDSHIFT14: m_stateAscii_xr = "cmdshift14";
EP_State_CMDSHIFT15: m_stateAscii_xr = "cmdshift15";
EP_State_CMDSHIFT16: m_stateAscii_xr = "cmdshift16";
EP_State_DWAIT: m_stateAscii_xr = "dwait ";
EP_State_DSHIFT0: m_stateAscii_xr = "dshift0 ";
EP_State_DSHIFT1: m_stateAscii_xr = "dshift1 ";
EP_State_DSHIFT15: m_stateAscii_xr = "dshift15 ";
default: m_stateAscii_xr = "%Error ";
endcase
end
// End of automatics
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
//$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b);
if (cyc==1) begin
m_state_xr <= EP_State_IDLE;
end
if (cyc==2) begin
if (m_stateAscii_xr != "idle ") $stop;
m_state_xr <= EP_State_CMDSHIFT13;
end
if (cyc==3) begin
if (m_stateAscii_xr != "cmdshift13") $stop;
m_state_xr <= EP_State_CMDSHIFT16;
end
if (cyc==4) begin
if (m_stateAscii_xr != "cmdshift16") $stop;
m_state_xr <= EP_State_DWAIT;
end
if (cyc==9) begin
if (m_stateAscii_xr != "dwait ") $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
/*
* Copyright (C) 2009 Onno Kortmann <[email protected]>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*
* THIS FILE HAS BEEN AUTOMATICALLY GENERATED FROM avr_tmpl.v.
* --- DO NOT EDIT MANUALLY! ---
*/
module ATtiny25(clk, PB);
parameter progfile="UNSPECIFIED";
input clk;
inout [7:0] PB;
integer handle;
defparam core.progfile=progfile;
defparam core.name="attiny25";
AVRCORE core(clk);
avr_pin #("B0") pb0(PB[0]);
avr_pin #("B1") pb1(PB[1]);
avr_pin #("B2") pb2(PB[2]);
avr_pin #("B3") pb3(PB[3]);
avr_pin #("B4") pb4(PB[4]);
avr_pin #("B5") pb5(PB[5]);
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_fifo.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core receiver FIFO ////
//// ////
//// Known problems (limits): ////
//// Note that the same FIFO is used for both transmission and ////
//// reception but the error bit generation is ignored in tx. ////
//// ////
//// To Do: ////
//// Nothing. ////
//// ////
//// Author(s): ////
//// - [email protected] ////
//// - Jacob Gorban ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2001/05/17 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Jacob Gorban, [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: uart_fifo.v,v $
// Revision 1.3 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.3 2001/05/27 17:37:48 gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.2 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:12+02 jacob
// Initial revision
//
//
`include "timescale.v"
`include "uart_defines.v"
module uart_fifo (clk,
wb_rst_i, data_in, data_out,
// Control signals
push, // push strobe, active high
pop, // pop strobe, active high
// status signals
underrun,
overrun,
count,
error_bit,
fifo_reset,
reset_status
);
// FIFO parameters
parameter fifo_width = `UART_FIFO_WIDTH;
parameter fifo_depth = `UART_FIFO_DEPTH;
parameter fifo_pointer_w = `UART_FIFO_POINTER_W;
parameter fifo_counter_w = `UART_FIFO_COUNTER_W;
input clk;
input wb_rst_i;
input push;
input pop;
input [fifo_width-1:0] data_in;
input fifo_reset;
input reset_status;
output [fifo_width-1:0] data_out;
output overrun;
output underrun;
output [fifo_counter_w-1:0] count;
output error_bit;
wire [fifo_width-1:0] data_out;
// FIFO itself
reg [fifo_width-1:0] fifo[fifo_depth-1:0];
// FIFO pointers
reg [fifo_pointer_w-1:0] top;
reg [fifo_pointer_w-1:0] bottom;
reg [fifo_counter_w-1:0] count;
reg overrun;
reg underrun;
// These registers and signals are to detect rise of of the signals.
// Not that it slows the maximum rate by 2, meaning you must reset the signals and then
// assert them again for the operation to repeat
// This is done to accomodate wait states
reg push_delay;
reg pop_delay;
wire push_rise = push_delay & push;
wire pop_rise = pop_delay & pop;
wire [fifo_pointer_w-1:0] top_plus_1 = top + 1;
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
push_delay <= #1 1'b0;
else
push_delay <= #1 ~push;
end
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
pop_delay <= #1 1'b0;
else
pop_delay <= #1 ~pop;
end
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
begin
if (wb_rst_i)
begin
top <= #1 0;
// bottom <= #1 1; igor
bottom <= #1 1'b0;
underrun <= #1 1'b0;
overrun <= #1 1'b0;
count <= #1 0;
fifo[0] <= #1 0;
fifo[1] <= #1 0;
fifo[2] <= #1 0;
fifo[3] <= #1 0;
fifo[4] <= #1 0;
fifo[5] <= #1 0;
fifo[6] <= #1 0;
fifo[7] <= #1 0;
fifo[8] <= #1 0;
fifo[9] <= #1 0;
fifo[10] <= #1 0;
fifo[11] <= #1 0;
fifo[12] <= #1 0;
fifo[13] <= #1 0;
fifo[14] <= #1 0;
fifo[15] <= #1 0;
end
else
if (fifo_reset) begin
top <= #1 0;
// bottom <= #1 1; igor
bottom <= #1 1'b0;
underrun <= #1 1'b0;
overrun <= #1 1'b0;
count <= #1 0;
end
else
if(reset_status)
begin
underrun <= #1 1'b0;
overrun <= #1 1'b0;
end
else
begin
case ({push_rise, pop_rise})
2'b00 : begin
underrun <= #1 1'b0;
// overrun <= #1 1'b0;// Igor Ko se postavita ostaneta aktivna tako dolgo, dokler se ne naredi read LSR registra
end
2'b10 : if (count==fifo_depth) // overrun condition
begin
overrun <= #1 1'b1;
underrun <= #1 1'b0;
end
else
begin
top <= #1 top_plus_1;
// fifo[top_plus_1] <= #1 data_in; igor
fifo[top] <= #1 data_in;
// overrun <= #1 0;// Igor Ko se postavita ostaneta aktivna tako dolgo, dokler se ne naredi read LSR registra
overrun <= #1 0;
count <= #1 count + 1;
end
2'b01 : if (~|count)
begin
// overrun <= #1 1'b0; Igor Ko se postavita ostaneta aktivna tako dolgo, dokler se ne naredi read LSR registra
overrun <= #1 1'b0;
end
else
begin
bottom <= #1 bottom + 1;
// overrun <= #1 1'b0; Igor Ko se postavita ostaneta aktivna tako dolgo, dokler se ne naredi read LSR registra
overrun <= #1 1'b0;
count <= #1 count - 1;
end
2'b11 : begin
bottom <= #1 bottom + 1;
top <= #1 top_plus_1;
// fifo[top_plus_1] <= #1 data_in; igor
fifo[top] <= #1 data_in;
underrun <= #1 1'b0;
// overrun <= #1 1'b0; Igor Ko se postavita ostaneta aktivna tako dolgo, dokler se ne naredi read LSR registra
end
endcase
end
end // always
// please note though that data_out is only valid one clock after pop signal
assign data_out = fifo[bottom];
// Additional logic for detection of error conditions (parity and framing) inside the FIFO
// for the Line Status Register bit 7
wire [fifo_width-1:0] word0 = fifo[0];
wire [fifo_width-1:0] word1 = fifo[1];
wire [fifo_width-1:0] word2 = fifo[2];
wire [fifo_width-1:0] word3 = fifo[3];
wire [fifo_width-1:0] word4 = fifo[4];
wire [fifo_width-1:0] word5 = fifo[5];
wire [fifo_width-1:0] word6 = fifo[6];
wire [fifo_width-1:0] word7 = fifo[7];
wire [fifo_width-1:0] word8 = fifo[8];
wire [fifo_width-1:0] word9 = fifo[9];
wire [fifo_width-1:0] word10 = fifo[10];
wire [fifo_width-1:0] word11 = fifo[11];
wire [fifo_width-1:0] word12 = fifo[12];
wire [fifo_width-1:0] word13 = fifo[13];
wire [fifo_width-1:0] word14 = fifo[14];
wire [fifo_width-1:0] word15 = fifo[15];
// a 1 is returned if any of the error bits in the fifo is 1
assign error_bit = |(word0[1:0] | word1[1:0] | word2[1:0] | word3[1:0] |
word4[1:0] | word5[1:0] | word6[1:0] | word7[1:0] |
word8[1:0] | word9[1:0] | word10[1:0] | word11[1:0] |
word12[1:0] | word13[1:0] | word14[1:0] | word15[1:0] );
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_IO__TOP_GPIOV2_SYMBOL_V
`define SKY130_FD_IO__TOP_GPIOV2_SYMBOL_V
/**
* top_gpiov2: General Purpose I/0.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_io__top_gpiov2 (
//# {{data|Data Signals}}
input SLOW ,
output IN ,
input INP_DIS ,
output IN_H ,
input OUT ,
inout PAD ,
inout PAD_A_ESD_0_H ,
inout PAD_A_ESD_1_H ,
inout PAD_A_NOESD_H ,
//# {{control|Control Signals}}
inout AMUXBUS_A ,
inout AMUXBUS_B ,
input ANALOG_EN ,
input ANALOG_POL ,
input ANALOG_SEL ,
input [2:0] DM ,
input ENABLE_H ,
input ENABLE_INP_H ,
input ENABLE_VDDA_H ,
input ENABLE_VDDIO ,
input ENABLE_VSWITCH_H,
input HLD_H_N ,
input HLD_OVR ,
input IB_MODE_SEL ,
input OE_N ,
//# {{power|Power}}
input VTRIP_SEL ,
output TIE_HI_ESD ,
output TIE_LO_ESD
);
// Voltage supply signals
supply1 VDDIO ;
supply1 VDDIO_Q;
supply1 VDDA ;
supply1 VCCD ;
supply1 VSWITCH;
supply1 VCCHIB ;
supply0 VSSA ;
supply0 VSSD ;
supply0 VSSIO_Q;
supply0 VSSIO ;
endmodule
`default_nettype wire
`endif // SKY130_FD_IO__TOP_GPIOV2_SYMBOL_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg signed [64+15:0] data;
integer i;
integer b;
reg signed [64+15:0] srs;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==2) begin
data <= 80'h0;
data[75] <= 1'b1;
data[10] <= 1'b1;
end
if (cyc==3) begin
for (i=0; i<85; i=i+1) begin
srs = data>>>i;
//$write (" %x >>> %d == %x\n",data,i,srs);
for (b=0; b<80; b=b+1) begin
if (srs[b] != (b==(75-i) || b==(10-i))) $stop;
end
end
end
if (cyc==10) begin
data <= 80'h0;
data[79] <= 1'b1;
data[10] <= 1'b1;
end
if (cyc==12) begin
for (i=0; i<85; i=i+1) begin
srs = data>>>i;
//$write (" %x >>> %d == %x\n",data,i,srs);
for (b=0; b<80; b=b+1) begin
if (srs[b] != (b>=(79-i) || b==(10-i))) $stop;
end
end
end
if (cyc==20) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_convert_with_rounding_8(clock, resetn, dataa, result, valid_in, valid_out, stall_in, stall_out, enable);
// Latency = 4.
parameter UNSIGNED = 1;
parameter ROUNDING_MODE = 0;
parameter HIGH_CAPACITY = 1;
// Rounding mode values are:
// 0 - round to nearest even
// 1 - round to nearest with ties away from zero
// 2 - round towards zero (truncation)
// 3 - round up
// 4 - round down
input clock;
input enable, resetn;
input [31:0] dataa;
output [7:0] result;
input valid_in, stall_in;
output stall_out, valid_out;
// STAGE 0 - extract input data into format we can work with.
wire sign_0;
wire [7:0] exp_0;
wire [22:0] man_0;
wire [23:0] implied_man_0;
assign {sign_0, exp_0, man_0} = dataa;
assign implied_man_0 = (|exp_0) ? {1'b1, man_0} : 24'd0;
// STAGE 1
reg sign_c1;
reg [10:0] man_c1;
reg [8:0] shift_amount_c1;
reg [7:0] exp_c1;
reg valid_c1;
wire stall_c1;
wire enable_c1;
assign stall_out = stall_c1 & valid_c1;
assign enable_c1 = (HIGH_CAPACITY == 1) ? (~stall_c1 | ~valid_c1) : enable;
always @( posedge clock or negedge resetn)
begin
if( ~resetn )
begin
sign_c1 <= 1'bx;
man_c1 <= 11'dx;
shift_amount_c1 <= 9'dx;
exp_c1 <= 8'dx;
valid_c1 <= 1'b0;
end
else if (enable_c1)
begin
sign_c1 <= sign_0;
valid_c1 <= valid_in;
if (UNSIGNED == 1)
begin
man_c1 <= {implied_man_0[23:14], |implied_man_0[13:0]};
shift_amount_c1 <= 9'd134 - exp_0;
end
else
begin
man_c1 <= {1'b0, implied_man_0[23:15], |implied_man_0[14:0]};
shift_amount_c1 <= 9'd133 - exp_0;
end
exp_c1 <= exp_0;
end
end
// STAGE 2
reg sign_c2;
reg [10:0] extended_mantissa_c2;
reg [2:0] shift_amount_c2;
reg valid_c2;
wire stall_c2;
wire enable_c2 = (HIGH_CAPACITY == 1) ? (~stall_c2 | ~valid_c2) : enable;
assign stall_c1 = stall_c2 & valid_c2;
always @( posedge clock or negedge resetn)
begin
if (~resetn)
begin
sign_c2 <= 1'bx;
extended_mantissa_c2 <= 11'dx;
shift_amount_c2 <= 3'dx;
valid_c2 <= 1'b0;
end
else if (enable_c2)
begin
sign_c2 <= sign_c1;
valid_c2 <= valid_c1;
shift_amount_c2 <= (shift_amount_c1[2:0]) & {3{(~(&exp_c1)) & ~shift_amount_c1[8]}};
// Now handle the corner cases of NaN and INF. Make it maximum positive or negative integer depending on the sign.
// Then handle overflow and regular shifting.
if ((UNSIGNED == 1) && (exp_c1 == 8'hff))
extended_mantissa_c2 <= {8'hff, 3'd0};
else if ((UNSIGNED == 0) && (exp_c1 == 8'hff))
extended_mantissa_c2 <= {8'h7f + sign_c1, 3'd0};
else if (shift_amount_c1[8])
extended_mantissa_c2 <= {(UNSIGNED == 0) ? 8'h7f + sign_c1 : 8'hff, 3'd0}; // Overflow/Saturation.
else if (|shift_amount_c1[7:4])
begin
// Shift by more than 16+
sign_c2 <= sign_c1 & (|man_c1);
extended_mantissa_c2 <= {10'd0, |man_c1};
end
else if (|shift_amount_c1[3])
begin
// Shift by 8+
extended_mantissa_c2 <= {8'd0, man_c1[10:9], |man_c1[8:0]};
end
else
extended_mantissa_c2 <= man_c1;
end
end
// STAGE 3
reg [10:0] extended_mantissa_c3;
reg valid_c3;
reg sign_c3;
wire stall_c3;
wire enable_c3 = (HIGH_CAPACITY == 1) ? (~valid_c3 | ~stall_c3) : enable;
assign stall_c2 = valid_c3 & stall_c3;
always @( posedge clock or negedge resetn)
begin
if (~resetn)
begin
extended_mantissa_c3 <= 35'dx;
sign_c3 <= 1'bx;
valid_c3 <= 1'b0;
end
else if (enable_c3)
begin
valid_c3 <= valid_c2;
sign_c3 <= sign_c2;
case (shift_amount_c2)
3'b111: extended_mantissa_c3 <= {7'd0, extended_mantissa_c2[10:8], |extended_mantissa_c2[7:0]};
3'b110: extended_mantissa_c3 <= {6'd0, extended_mantissa_c2[10:7], |extended_mantissa_c2[6:0]};
3'b101: extended_mantissa_c3 <= {5'd0, extended_mantissa_c2[10:6], |extended_mantissa_c2[5:0]};
3'b100: extended_mantissa_c3 <= {4'd0, extended_mantissa_c2[10:5], |extended_mantissa_c2[4:0]};
3'b011: extended_mantissa_c3 <= {3'd0, extended_mantissa_c2[10:4], |extended_mantissa_c2[3:0]};
3'b010: extended_mantissa_c3 <= {2'd0, extended_mantissa_c2[10:3], |extended_mantissa_c2[2:0]};
3'b001: extended_mantissa_c3 <= {1'd0, extended_mantissa_c2[10:2], |extended_mantissa_c2[1:0]};
3'b000: extended_mantissa_c3 <= extended_mantissa_c2;
endcase
end
end
// STAGE 4
reg [8:0] result_c4;
reg valid_c4;
wire stall_c4;
wire enable_c4 = (HIGH_CAPACITY == 1) ? (~valid_c4 | ~stall_c4) : enable;
assign stall_c3 = valid_c4 & stall_c4;
assign stall_c4 = stall_in;
always @( posedge clock or negedge resetn)
begin
if (~resetn)
begin
result_c4 <= 9'dx;
valid_c4 <= 1'b0;
end
else if (enable_c4)
begin
valid_c4 <= valid_c3;
case(ROUNDING_MODE)
2:
begin // 2 is round to zero
if (UNSIGNED == 0)
begin
result_c4 <= ({9{sign_c3}} ^ (extended_mantissa_c3[10:3])) + sign_c3;
end
else
begin
result_c4 <= (sign_c3) ? 8'd0 : extended_mantissa_c3[10:3];
end
end
4:
begin // 4 is round down
if (|extended_mantissa_c3[2:0])
begin
if (UNSIGNED == 0)
begin
result_c4 <= (sign_c3) ? (({9{sign_c3}} ^ (extended_mantissa_c3[10:3] + 1'b1)) + 1'b1) : extended_mantissa_c3[10:3];
end
else
begin
result_c4 <= (sign_c3) ? 8'd0 : extended_mantissa_c3[10:3];
end
end
else
begin
if (UNSIGNED == 0)
result_c4 <= ({9{sign_c3}} ^ extended_mantissa_c3[10:3]) + sign_c3;
else
result_c4 <= {8{~sign_c3}} & extended_mantissa_c3[10:3];
end
end
3:
begin // 3 is round up
if (|extended_mantissa_c3[2:0])
begin
if (UNSIGNED == 0)
begin
result_c4 <= (sign_c3) ? (({9{sign_c3}} ^ extended_mantissa_c3[10:3]) + 1'b1) : (extended_mantissa_c3[10:3] + 1'b1);
end
else
begin
result_c4 <= (sign_c3) ? 8'd0 : extended_mantissa_c3[10:3] + 1'b1;
end
end
else
begin
if (UNSIGNED == 0)
result_c4 <= ({9{sign_c3}} ^ extended_mantissa_c3[10:3]) + sign_c3;
else
result_c4 <= {8{~sign_c3}} & extended_mantissa_c3[10:3];
end
end
1:
begin // 1 is round to nearest with ties rounded away from zero.
if (extended_mantissa_c3[2])
begin
if (UNSIGNED == 0)
begin
result_c4 <= ({9{sign_c3}} ^ (extended_mantissa_c3[10:3] + 1'b1)) + sign_c3;
end
else
begin
result_c4 <= (sign_c3) ? 8'd0 : extended_mantissa_c3[10:3] + 1'b1;
end
end
else
begin
if (UNSIGNED == 0)
result_c4 <= ({9{sign_c3}} ^ extended_mantissa_c3[10:3]) + sign_c3;
else
result_c4 <= {8{~sign_c3}} & extended_mantissa_c3[10:3];
end
end
default:
begin // 0 and default are round to nearest even
if ((extended_mantissa_c3[3:0] == 4'hc) | (extended_mantissa_c3[2] & (|extended_mantissa_c3[1:0])))
begin
if (UNSIGNED == 0)
begin
result_c4 <= ({9{sign_c3}} ^ (extended_mantissa_c3[10:3] + 1'b1)) + sign_c3;
end
else
begin
result_c4 <= (sign_c3) ? 8'd0 : extended_mantissa_c3[10:3] + 1'b1;
end
end
else
begin
if (UNSIGNED == 0)
result_c4 <= ({9{sign_c3}} ^ extended_mantissa_c3[10:3]) + sign_c3;
else
result_c4 <= {8{~sign_c3}} & extended_mantissa_c3[10:3];
end
end
endcase
end
end
// handle saturation here too, just in case rounding went over the limit of the expected range.
assign result = (UNSIGNED == 1) ? ({8{result_c4[8]}} | result_c4) : ((result_c4[8] ^ result_c4[7]) ? {result_c4[8], {7{~result_c4[8]}}} : result_c4[7:0]);
assign valid_out = valid_c4;
endmodule
|
// $Id: c_prefix_arbiter_base.v 5188 2012-08-30 00:31:31Z dub $
/*
Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// prefix tree based round-robin arbiter basic block
//==============================================================================
module c_prefix_arbiter_base
(prio_port, req, gnt);
// number of input ports
parameter num_ports = 32;
// port priority pointer
input [0:num_ports-1] prio_port;
// vector of requests
input [0:num_ports-1] req;
// vector of grants
output [0:num_ports-1] gnt;
wire [0:num_ports-1] gnt;
wire [0:num_ports-1] g_in;
assign g_in = prio_port;
wire [0:num_ports-1] p_in;
assign p_in = ~{req[num_ports-1], req[0:num_ports-2]};
wire [0:num_ports-1] g_out;
wire [0:num_ports-1] p_out;
c_prefix_net
#(.width(num_ports),
.enable_wraparound(1))
g_out_pn
(.g_in(g_in),
.p_in(p_in),
.g_out(g_out),
.p_out(p_out));
assign gnt = req & g_out;
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/15.0/ip/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_handshake_clock_crosser.v $
// $Revision: #1 $
// $Date: 2015/02/08 $
// $Author: swbranch $
//------------------------------------------------------------------------------
// Clock crosser module with handshaking mechanism
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_handshake_clock_crosser
#(
parameter DATA_WIDTH = 8,
BITS_PER_SYMBOL = 8,
USE_PACKETS = 0,
// ------------------------------
// Optional signal widths
// ------------------------------
USE_CHANNEL = 0,
CHANNEL_WIDTH = 1,
USE_ERROR = 0,
ERROR_WIDTH = 1,
VALID_SYNC_DEPTH = 2,
READY_SYNC_DEPTH = 2,
USE_OUTPUT_PIPELINE = 1,
// ------------------------------
// Derived parameters
// ------------------------------
SYMBOLS_PER_BEAT = DATA_WIDTH / BITS_PER_SYMBOL,
EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
input in_clk,
input in_reset,
input out_clk,
input out_reset,
output in_ready,
input in_valid,
input [DATA_WIDTH - 1 : 0] in_data,
input [CHANNEL_WIDTH - 1 : 0] in_channel,
input [ERROR_WIDTH - 1 : 0] in_error,
input in_startofpacket,
input in_endofpacket,
input [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] in_empty,
input out_ready,
output out_valid,
output [DATA_WIDTH - 1 : 0] out_data,
output [CHANNEL_WIDTH - 1 : 0] out_channel,
output [ERROR_WIDTH - 1 : 0] out_error,
output out_startofpacket,
output out_endofpacket,
output [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] out_empty
);
// ------------------------------
// Payload-specific widths
// ------------------------------
localparam PACKET_WIDTH = (USE_PACKETS) ? 2 + EMPTY_WIDTH : 0;
localparam PCHANNEL_W = (USE_CHANNEL) ? CHANNEL_WIDTH : 0;
localparam PERROR_W = (USE_ERROR) ? ERROR_WIDTH : 0;
localparam PAYLOAD_WIDTH = DATA_WIDTH +
PACKET_WIDTH +
PCHANNEL_W +
EMPTY_WIDTH +
PERROR_W;
wire [PAYLOAD_WIDTH - 1: 0] in_payload;
wire [PAYLOAD_WIDTH - 1: 0] out_payload;
// ------------------------------
// Assign in_data and other optional sink interface
// signals to in_payload.
// ------------------------------
assign in_payload[DATA_WIDTH - 1 : 0] = in_data;
generate
// optional packet inputs
if (PACKET_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH - 1 :
DATA_WIDTH
] = {in_startofpacket, in_endofpacket};
end
// optional channel input
if (USE_CHANNEL) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W - 1 :
DATA_WIDTH + PACKET_WIDTH
] = in_channel;
end
// optional empty input
if (EMPTY_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W
] = in_empty;
end
// optional error input
if (USE_ERROR) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH + PERROR_W - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH
] = in_error;
end
endgenerate
// --------------------------------------------------
// Pipe the input payload to our inner module which handles the
// actual clock crossing
// --------------------------------------------------
altera_avalon_st_clock_crosser
#(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (PAYLOAD_WIDTH),
.FORWARD_SYNC_DEPTH (VALID_SYNC_DEPTH),
.BACKWARD_SYNC_DEPTH (READY_SYNC_DEPTH),
.USE_OUTPUT_PIPELINE (USE_OUTPUT_PIPELINE)
) clock_xer (
.in_clk (in_clk ),
.in_reset (in_reset ),
.in_ready (in_ready ),
.in_valid (in_valid ),
.in_data (in_payload ),
.out_clk (out_clk ),
.out_reset (out_reset ),
.out_ready (out_ready ),
.out_valid (out_valid ),
.out_data (out_payload )
);
// --------------------------------------------------
// Split out_payload into the output signals.
// --------------------------------------------------
assign out_data = out_payload[DATA_WIDTH - 1 : 0];
generate
// optional packet outputs
if (USE_PACKETS) begin
assign {out_startofpacket, out_endofpacket} =
out_payload[DATA_WIDTH + PACKET_WIDTH - 1 : DATA_WIDTH];
end else begin
// avoid a "has no driver" warning.
assign {out_startofpacket, out_endofpacket} = 2'b0;
end
// optional channel output
if (USE_CHANNEL) begin
assign out_channel = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W - 1 :
DATA_WIDTH + PACKET_WIDTH
];
end else begin
// avoid a "has no driver" warning.
assign out_channel = 1'b0;
end
// optional empty output
if (EMPTY_WIDTH) begin
assign out_empty = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W
];
end else begin
// avoid a "has no driver" warning.
assign out_empty = 1'b0;
end
// optional error output
if (USE_ERROR) begin
assign out_error = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH + PERROR_W - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH
];
end else begin
// avoid a "has no driver" warning.
assign out_error = 1'b0;
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value.
// --------------------------------------------------
function integer log2ceil;
input integer val;
integer i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
|
// MBT 7-28-2014
//
// Test source synchronous link.
//
// We model here two cores that have different clocks and are
// communicating over an I/O channel which has a third clock.
//
// Includes model reset logic with synchronizers and delayed
// communication after reset.
//
`include "bsg_defines.v"
module test_bsg_source_sync_input;
initial begin
$vcdpluson;
end
// three separate clocks: I/O, and the two cores communicating with each other
localparam core_0_half_period_lp = 5;
localparam io_master_half_period_lp = 7;
localparam core_1_half_period_lp = 6;
// across all frequency combinations, we need a little over 20 fifo slots
// so we round up to 32.
localparam lg_input_fifo_depth_lp = 5;
// for DDR at 500 mbps, we make token go at / 8 = 66 mbps
// this will keep the token clock nice and slow
localparam lg_credit_to_token_decimation_lp=3;
// number of bits width of a channel
localparam channel_width_lp=8;
// *************************************************
// independent clocks
//
//
logic core_0_clk, core_1_clk, io_master_clk;
initial core_0_clk = 0;
always #(core_0_half_period_lp) core_0_clk = ~core_0_clk;
initial io_master_clk = 0;
always #(io_master_half_period_lp) io_master_clk = ~io_master_clk;
initial core_1_clk = 0;
always #(core_1_half_period_lp) core_1_clk = ~core_1_clk;
// *************************************************
// master resets
//
logic core_0_reset, core_1_reset;
localparam core_reset_cycles_hi_lp = 256;
localparam core_reset_cycles_lo_lp = 16;
// we model this as if the FPGA is driving this with an unknown clock.
initial
begin
core_0_reset = 0;
core_1_reset = 0;
// simple hack to wait based on maximum of clock periods
repeat (core_reset_cycles_lo_lp)
begin
@(negedge core_0_clk);
@(negedge core_1_clk);
@(negedge io_master_clk);
end
core_0_reset = 1;
core_1_reset = 1;
// simple hack to wait based on maximum of clock periods
repeat (core_reset_cycles_hi_lp)
begin
@(negedge core_0_clk);
@(negedge core_1_clk);
@(negedge io_master_clk);
end
core_0_reset = 0;
core_1_reset = 0;
$display("__________ ___________ _______________________________");
$display("\\______ \\\\_ _____/ / _____/\\_ _____/\\__ ___/");
$display(" | _/ | __)_ \\_____ \\ | __)_ | | ");
$display(" | | \\ | \\ / \\ | \\ | | ");
$display(" |____|_ //_______ //_______ //_______ / |____| ");
$display(" \\/ \\/ \\/ \\/ ");
end
// *****************************************
// * CORE 0 (sender)
// *
// *
// *
wire core_0_reset_sync, io_master_reset_sync, token_reset_sync;
// reset synchronizer: core clock reset
bsg_sync_sync #(.width_p(1)) bss_core_reset
(.oclk_i(core_0_clk)
,.iclk_data_i(core_0_reset)
,.oclk_data_o(core_0_reset_sync)
);
// reset synchronizer: master clock reset
bsg_sync_sync #(.width_p(1)) bss_io_master_reset
(.oclk_i(io_master_clk)
,.iclk_data_i(core_0_reset)
,.oclk_data_o(io_master_reset_sync)
);
// reset synchronizer: token reset
bsg_sync_sync #(.width_p(1)) bss_token_reset
(.oclk_i(io_master_clk)
,.iclk_data_i(core_0_reset)
,.oclk_data_o(token_reset_sync)
);
logic [channel_width_lp-1:0] core_0_data_r;
logic core_0_valid_r;
// wait a certain number of cycles after reset before restarting
localparam lg_wait_cycles_activate_lp = 4;
wire core_reset_ready;
bsg_wait_after_reset #(.lg_wait_cycles_p(lg_wait_cycles_activate_lp)) bwar
(.reset_i(core_0_reset_sync)
,.clk_i(core_0_clk)
,.ready_r_o(core_reset_ready)
);
// only start sending after a certain number of cycles
assign core_0_valid_r = core_reset_ready;
wire core_0_yumi;
// transmit sequence of data values
always @(posedge core_0_clk)
if (core_0_reset_sync)
core_0_data_r <= 0;
else
if (core_0_yumi)
core_0_data_r <= core_0_data_r + 1;
// ***********************************************
// TOKEN RESET LOGIC
//
// reset logic for clearing output channel's
// token-clocked logic.
//
logic io_override_en;
logic [channel_width_lp+1-1:0] io_override_valid_data;
logic io_master_reset_sync_r;
logic [10:0] io_reset_counter_r;
always @(posedge io_master_clk)
begin
io_master_reset_sync_r <= io_master_reset_sync;
// on positive edge of reset, we initialize the counter
// the counter continuously counts during reset
// and is zero'd when not in reset
if (io_master_reset_sync)
begin
if (~io_master_reset_sync_r)
io_reset_counter_r <= 1;
else
io_reset_counter_r <= io_reset_counter_r + 1;
end
else
io_reset_counter_r <= 0;
end
// this asserts the override data while the reset counter
// is in its active portion
always_comb
begin
io_override_en = io_master_reset_sync;
io_override_valid_data = { 0'b0, 0'h00 };
// for 2^6 cycles, assert the "token reset code"
if (io_reset_counter_r[10:6] == 5'b00001)
io_override_valid_data = { 1'b1, 8'h80 };
end
// ***********************************************
// declare signals going out over transmission lines
// between input and output channel
//
wire io_clk_tline, io_valid_tline;
wire [channel_width_lp-1:0] io_data_tline;
wire token_clk_tline;
bsg_source_sync_output #(.lg_start_credits_p(lg_input_fifo_depth_lp)
,.lg_credit_to_token_decimation_p(lg_credit_to_token_decimation_lp)
,.channel_width_p(channel_width_lp)
) bsso_o1
(.core_clk_i(core_0_clk)
,.core_reset_i(core_0_reset_sync)
// core 0 side logical signals
,.core_data_i(core_0_data_r)
,.core_valid_i(core_0_valid_r)
,.core_yumi_o(core_0_yumi)
,.io_master_clk_i(io_master_clk)
,.io_reset_i(io_master_reset_sync)
,.io_override_en_i(io_override_en)
,.io_override_valid_data_i(io_override_valid_data)
,.io_clk_r_o(io_clk_tline) // output to other node
,.io_data_r_o(io_data_tline) // output to other node
,.io_valid_r_o(io_valid_tline) // output to other node
,.token_clk_i(token_clk_tline) // input from other node
,.token_reset_i(token_reset_sync) // from core 0
);
// *****************************************
// * CORE 1 (input side)
// *
// *
// *
localparam lg_io_delay_reset_lp = 6;
wire io_1_reset_sync, core_1_reset_sync;
bsg_sync_sync #(.width_p(1)) bss_core_1_reset
(.oclk_i(core_1_clk)
,.iclk_data_i(core_1_reset)
,.oclk_data_o(core_1_reset_sync)
);
bsg_sync_sync #(.width_p(1)) bss_io_1_reset
(.oclk_i(io_clk_tline)
,.iclk_data_i(core_1_reset)
,.oclk_data_o(io_1_reset_sync)
);
wire core_1_yumi;
wire core_1_valid;
wire [channel_width_lp-1:0] core_1_data;
bsg_source_sync_input #(.lg_fifo_depth_p(lg_input_fifo_depth_lp)
,.lg_credit_to_token_decimation_p(lg_credit_to_token_decimation_lp)
,.channel_width_p(channel_width_lp)
) bssi_i1
(.io_clk_i(io_clk_tline) // input from other node; starts on reset
,.io_reset_i(io_1_reset_sync)
,.io_data_i(io_data_tline) // input from other node
,.io_valid_i(io_valid_tline) // input from other node
,.io_edge_i(2'b11) // latch on both edges
,.io_token_r_o(token_clk_tline) // output to other node
,.io_snoop_r_o() // snoop input channel;
// for establishing calibration state
// on reset
,.io_trigger_mode_en_i(1'b0) // enable loop-back trigger mode
,.io_trigger_mode_alt_en_i(1'b0) // enable loop-back trigger mode: alternate trigger
,.core_clk_i(core_1_clk)
,.core_reset_i(core_1_reset_sync)
// core 1 side logical signals
,.core_data_o(core_1_data)
,.core_valid_o(core_1_valid)
,.core_yumi_i(core_1_yumi)
);
// consume all data
assign core_1_yumi = core_1_valid;
localparam cycle_counter_width_lp=32;
logic [cycle_counter_width_lp-1:0] core_0_ctr;
bsg_cycle_counter #(.width_p(cycle_counter_width_lp)) bcc_core0 (core_0_clk, core_0_reset_sync, core_0_ctr);
logic [cycle_counter_width_lp-1:0] core_1_ctr;
bsg_cycle_counter #(.width_p(cycle_counter_width_lp)) bcc_core1 (core_1_clk, core_1_reset_sync, core_1_ctr);
logic [cycle_counter_width_lp-1:0] io_ctr;
bsg_cycle_counter #(.width_p(cycle_counter_width_lp)) bcc_io (io_master_clk, io_master_reset_sync, io_ctr);
// non-synthesizable, TEST ONLY
logic [7:0] core_1_last_n, core_1_last_r = -1;
logic [5:0] top_bits = 0;
assign core_1_last_n = core_1_last_r+8'b1;
// *******************************************************
// *
// * Logging.
// *
// * These statements allow you to see, in time, when values are transmitted and received.
// *
// *
// * For this test, the number of cycles on the slowest clock should match the number of words
// * transmitted plus a small constant.
// *
// *
always @(negedge core_1_clk)
if (core_1_valid)
begin
$display("## ", core_0_ctr, io_ctr, core_1_ctr, " ## core 1 recv %d, %d",top_bits*256,core_1_data);
assert (core_1_last_n == core_1_data) else $error("##transmission error", core_1_last_r, core_1_data);
core_1_last_r <= core_1_last_n;
if (core_1_data == 8'hff)
begin
if (top_bits == 6'b000_111)
$finish("## DONE");
top_bits = top_bits+1;
end
end
always @(negedge core_0_clk)
if (core_0_yumi)
$display("## ", core_0_ctr, io_ctr, core_1_ctr, " ## core 0 sent %d",core_0_data_r);
always @(negedge io_master_clk)
if (io_valid_tline)
$display("## ", core_0_ctr, io_ctr, core_1_ctr, " ## io xmit %d",io_data_tline);
endmodule
|
// *****************************************************************************
// Cadence C-to-Silicon Compiler
// Version 14.10-p100 (32 bit), build 50398 Tue, 27 May 2014
//
// File created on Sat Oct 11 22:26:53 2014
//
// The code contained herein is generated for Cadences customer and third
// parties authorized by customer. It may be used in accordance with a
// previously executed license agreement between Cadence and that customer.
// Absolutely no disassembling, decompiling, reverse-translations or
// reverse-engineering of the generated code is allowed.
//
//*****************************************************************************
module dflipflop_post_build(din, clk, reset, dout);
input din;
input clk;
input reset;
output reg dout;
always begin : dflipflop_behaviour
reg state_dflipflop;
reg joins_dflipflop;
reg read_dflipflop_din_ln8;
joins_dflipflop = 1'b0;
if (reset) begin
dout <= 1'b0;
joins_dflipflop = 1'b1;
end
else begin
read_dflipflop_din_ln8 = din;
dout <= read_dflipflop_din_ln8;
joins_dflipflop = 1'b1;
end
// proc_ln4
if (joins_dflipflop == 1'b1) begin
joins_dflipflop = 1'b0;
state_dflipflop <= 1'b0;
end
@(posedge clk);
end
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 09:40:17 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_auto_pc_1_stub.v
// Design : zynq_design_1_auto_pc_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wid, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize,
m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awregion, m_axi_awqos,
m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wvalid,
m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_arid, m_axi_araddr,
m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache, m_axi_arprot,
m_axi_arregion, m_axi_arqos, m_axi_arvalid, m_axi_arready, m_axi_rid, m_axi_rdata,
m_axi_rresp, m_axi_rlast, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awid[11:0],m_axi_awaddr[31:0],m_axi_awlen[7:0],m_axi_awsize[2:0],m_axi_awburst[1:0],m_axi_awlock[0:0],m_axi_awcache[3:0],m_axi_awprot[2:0],m_axi_awregion[3:0],m_axi_awqos[3:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wlast,m_axi_wvalid,m_axi_wready,m_axi_bid[11:0],m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_arid[11:0],m_axi_araddr[31:0],m_axi_arlen[7:0],m_axi_arsize[2:0],m_axi_arburst[1:0],m_axi_arlock[0:0],m_axi_arcache[3:0],m_axi_arprot[2:0],m_axi_arregion[3:0],m_axi_arqos[3:0],m_axi_arvalid,m_axi_arready,m_axi_rid[11:0],m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rlast,m_axi_rvalid,m_axi_rready" */;
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [3:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [3:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [11:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awregion;
output [3:0]m_axi_awqos;
output m_axi_awvalid;
input m_axi_awready;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wlast;
output m_axi_wvalid;
input m_axi_wready;
input [11:0]m_axi_bid;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [11:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arregion;
output [3:0]m_axi_arqos;
output m_axi_arvalid;
input m_axi_arready;
input [11:0]m_axi_rid;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_img_0_rows_V_channel_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_img_0_rows_V_channel (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_img_0_rows_V_channel_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_img_0_rows_V_channel_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
`timescale 1ns/100ps
// -----------------------------------------------------------------------------
// One-level up Hierarchical module
// -----------------------------------------------------------------------------
module a_h
// Verilog 2001 style
#(parameter M=5, N=3)
(
// Outputs
output [N-1:0] [M-1:0]a_o1 // From Ia of autoinst_sv_kulkarni_base.v
// End of automatics
// AUTOINPUT*/
);
/*AUTOWIRE*/
autoinst_sv_kulkarni_base
#(/*AUTOINSTPARAM*/)
Ia
(/*AUTOINST*/); // <---- BUG?
endmodule
// -----------------------------------------------------------------------------
// Top-level module or Testbench
// -----------------------------------------------------------------------------
module top;
parameter M=4;
parameter N=2;
wire [N-1:0] a_o1;
logic [N-1:0][M-1:0] a_i1;
logic temp;
/*AUTOWIRE*/
// Workaround to fix multi-dimensional port problem
// a) Set "verilog-auto-inst-vector = nil"
// b) ----> a_h AUTO_TEMPLATE ( .\(.*\) (\1), ); */
a_h #(/*AUTOINSTPARAM*/)
Ua_h
(/*AUTOINST*/); // <---- BUG?
// Stimulus
initial begin
a_i1 = { 4'h0, 4'h2 };
#5;
$display("Loop Init: a_i1 = { %h, %h } a_o1 = %h\n",
a_i1[1], a_i1[0], a_o1);
#5;
for (int i=0; i<1; i++) begin
for (int j=0; j<N; j++) begin
temp = 1'b0;
for (int k=0; k<M; k++) begin
a_i1[j][k] = temp;
temp = ~temp;
end
end
#5;
$display("Loop %0d: a_i1 = { %h, %h } a_o1 = %h\n",
i, a_i1[1], a_i1[0], a_o1);
#5;
end
end
endmodule
|
// megafunction wizard: %ALTGX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: alt4gxb
// ============================================================
// File Name: altpcie_serdes_4sgx_x8d_gen2_08p.v
// Megafunction Name(s):
// alt4gxb
//
// Simulation Library Files(s):
// stratixiv_hssi
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.1 Internal Build 134 10/13/2010 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//alt4gxb CBX_AUTO_BLACKBOX="ALL" coreclkout_control_width=1 device_family="Stratix IV" effective_data_rate="5000 Mbps" elec_idle_infer_enable="false" enable_0ppm="false" enable_lc_tx_pll="false" equalizer_ctrl_a_setting=0 equalizer_ctrl_b_setting=0 equalizer_ctrl_c_setting=0 equalizer_ctrl_d_setting=0 equalizer_ctrl_v_setting=0 equalizer_dcgain_setting=1 gen_reconfig_pll="false" gx_channel_type="auto" gxb_analog_power="3.0v" gxb_powerdown_width=1 input_clock_frequency="100.0 MHz" intended_device_speed_grade="2" intended_device_variant="GX" loopback_mode="none" number_of_channels=8 number_of_quads=2 operation_mode="duplex" pll_control_width=1 pll_pfd_fb_mode="internal" preemphasis_ctrl_1stposttap_setting=0 protocol="pcie2" rateswitch_control_width=1 receiver_termination="OCT_100_OHMS" reconfig_calibration="true" reconfig_dprio_mode=1 reconfig_fromgxb_port_width=34 reconfig_togxb_port_width=4 rx_8b_10b_mode="normal" rx_align_pattern="0101111100" rx_align_pattern_length=10 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="true" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_cdrctrl_enable="true" rx_channel_bonding="x8" rx_channel_width=16 rx_common_mode="0.82v" rx_cru_bandwidth_type="auto" rx_cru_inclock0_period=10000 rx_cru_m_divider=25 rx_cru_n_divider=1 rx_cru_vco_post_scale_divider=1 rx_data_rate=5000 rx_data_rate_remainder=0 rx_datapath_protocol="pipe" rx_digitalreset_port_width=1 rx_dwidth_factor=2 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_enable_self_test_mode="false" rx_force_signal_detect="true" rx_ppmselect=32 rx_rate_match_fifo_mode="normal" rx_rate_match_pattern1="11010000111010000011" rx_rate_match_pattern2="00101111000101111100" rx_rate_match_pattern_size=20 rx_run_length=40 rx_run_length_enable="true" rx_signal_detect_loss_threshold=3 rx_signal_detect_threshold=4 rx_signal_detect_valid_threshold=14 rx_use_align_state_machine="true" rx_use_clkout="false" rx_use_coreclk="false" rx_use_cruclk="true" rx_use_deserializer_double_data_mode="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="true" rx_use_external_termination="false" rx_use_pipe8b10binvpolarity="true" rx_use_rate_match_pattern1_only="false" rx_word_aligner_num_byte=1 starting_channel_number=0 transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_analog_power="auto" tx_channel_bonding="x8" tx_channel_width=16 tx_clkout_width=8 tx_common_mode="0.65v" tx_data_rate=5000 tx_data_rate_remainder=0 tx_digitalreset_port_width=1 tx_dwidth_factor=2 tx_enable_bit_reversal="false" tx_enable_self_test_mode="false" tx_pll_bandwidth_type="high" tx_pll_clock_post_divider=1 tx_pll_inclk0_period=10000 tx_pll_m_divider=25 tx_pll_n_divider=1 tx_pll_type="CMU" tx_pll_vco_post_scale_divider=1 tx_slew_rate="off" tx_transmit_protocol="pipe" tx_use_coreclk="false" tx_use_double_data_mode="true" tx_use_external_termination="false" tx_use_serializer_double_data_mode="false" use_calibration_block="true" vod_ctrl_setting=3 cal_blk_clk coreclkout gxb_powerdown pipe8b10binvpolarity pipedatavalid pipeelecidle pipephydonestatus pipestatus pll_inclk pll_locked powerdn rateswitch reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_cruclk rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_freqlocked rx_patterndetect rx_pll_locked rx_syncstatus tx_ctrlenable tx_datain tx_dataout tx_detectrxloop tx_digitalreset tx_forcedispcompliance tx_forceelecidle tx_pipedeemph tx_pipemargin
//VERSION_BEGIN 10.1 cbx_alt4gxb 2010:10:13:21:30:47:SJ cbx_mgl 2010:10:13:21:32:12:SJ cbx_tgx 2010:10:13:21:30:47:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = reg 6 stratixiv_hssi_calibration_block 2 stratixiv_hssi_clock_divider 2 stratixiv_hssi_cmu 2 stratixiv_hssi_pll 9 stratixiv_hssi_rx_pcs 8 stratixiv_hssi_rx_pma 8 stratixiv_hssi_tx_pcs 8 stratixiv_hssi_tx_pma 8
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module altpcie_serdes_4sgx_x8d_gen2_08p_alt4gxb_q0ea
(
cal_blk_clk,
coreclkout,
gxb_powerdown,
pipe8b10binvpolarity,
pipedatavalid,
pipeelecidle,
pipephydonestatus,
pipestatus,
pll_inclk,
pll_locked,
powerdn,
rateswitch,
reconfig_clk,
reconfig_fromgxb,
reconfig_togxb,
rx_analogreset,
rx_cruclk,
rx_ctrldetect,
rx_datain,
rx_dataout,
rx_digitalreset,
rx_freqlocked,
rx_patterndetect,
rx_pll_locked,
rx_syncstatus,
tx_ctrlenable,
tx_datain,
tx_dataout,
tx_detectrxloop,
tx_digitalreset,
tx_forcedispcompliance,
tx_forceelecidle,
tx_pipedeemph,
tx_pipemargin) ;
input cal_blk_clk;
output [0:0] coreclkout;
input [0:0] gxb_powerdown;
input [7:0] pipe8b10binvpolarity;
output [7:0] pipedatavalid;
output [7:0] pipeelecidle;
output [7:0] pipephydonestatus;
output [23:0] pipestatus;
input pll_inclk;
output [0:0] pll_locked;
input [15:0] powerdn;
input [0:0] rateswitch;
input reconfig_clk;
output [33:0] reconfig_fromgxb;
input [3:0] reconfig_togxb;
input [0:0] rx_analogreset;
input [7:0] rx_cruclk;
output [15:0] rx_ctrldetect;
input [7:0] rx_datain;
output [127:0] rx_dataout;
input [0:0] rx_digitalreset;
output [7:0] rx_freqlocked;
output [15:0] rx_patterndetect;
output [7:0] rx_pll_locked;
output [15:0] rx_syncstatus;
input [15:0] tx_ctrlenable;
input [127:0] tx_datain;
output [7:0] tx_dataout;
input [7:0] tx_detectrxloop;
input [0:0] tx_digitalreset;
input [7:0] tx_forcedispcompliance;
input [7:0] tx_forceelecidle;
input [7:0] tx_pipedeemph;
input [23:0] tx_pipemargin;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 cal_blk_clk;
tri0 [0:0] gxb_powerdown;
tri0 [7:0] pipe8b10binvpolarity;
tri0 pll_inclk;
tri0 [15:0] powerdn;
tri0 [0:0] rateswitch;
tri0 reconfig_clk;
tri0 [0:0] rx_analogreset;
tri0 [7:0] rx_cruclk;
tri0 [0:0] rx_digitalreset;
tri0 [15:0] tx_ctrlenable;
tri0 [127:0] tx_datain;
tri0 [7:0] tx_detectrxloop;
tri0 [0:0] tx_digitalreset;
tri0 [7:0] tx_forcedispcompliance;
tri0 [7:0] tx_forceelecidle;
tri0 [7:0] tx_pipedeemph;
tri0 [23:0] tx_pipemargin;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
parameter starting_channel_number = 0;
wire [2:0] wire_rx_digitalreset_reg0c_d;
reg [2:0] rx_digitalreset_reg0c;
wire [2:0] wire_rx_digitalreset_reg0c_clk;
wire [2:0] wire_tx_digitalreset_reg0c_d;
reg [2:0] tx_digitalreset_reg0c;
wire [2:0] wire_tx_digitalreset_reg0c_clk;
wire wire_cal_blk0_nonusertocmu;
wire wire_cal_blk1_nonusertocmu;
wire [1:0] wire_central_clk_div0_analogfastrefclkout;
wire [1:0] wire_central_clk_div0_analogrefclkout;
wire wire_central_clk_div0_analogrefclkpulse;
wire wire_central_clk_div0_coreclkout;
wire [99:0] wire_central_clk_div0_dprioout;
wire wire_central_clk_div0_rateswitchdone;
wire wire_central_clk_div0_refclkout;
wire [1:0] wire_central_clk_div1_analogfastrefclkout;
wire [1:0] wire_central_clk_div1_analogrefclkout;
wire wire_central_clk_div1_analogrefclkpulse;
wire wire_central_clk_div1_coreclkout;
wire [99:0] wire_central_clk_div1_dprioout;
wire wire_central_clk_div1_rateswitchdone;
wire wire_central_clk_div1_refclkout;
wire wire_cent_unit0_autospdx4configsel;
wire wire_cent_unit0_autospdx4rateswitchout;
wire wire_cent_unit0_autospdx4spdchg;
wire [1:0] wire_cent_unit0_clkdivpowerdn;
wire [599:0] wire_cent_unit0_cmudividerdprioout;
wire [1799:0] wire_cent_unit0_cmuplldprioout;
wire wire_cent_unit0_dpriodisableout;
wire wire_cent_unit0_dprioout;
wire wire_cent_unit0_phfifiox4ptrsreset;
wire [1:0] wire_cent_unit0_pllpowerdn;
wire [1:0] wire_cent_unit0_pllresetout;
wire wire_cent_unit0_quadresetout;
wire [5:0] wire_cent_unit0_rxanalogresetout;
wire [5:0] wire_cent_unit0_rxcrupowerdown;
wire [5:0] wire_cent_unit0_rxcruresetout;
wire [3:0] wire_cent_unit0_rxdigitalresetout;
wire [5:0] wire_cent_unit0_rxibpowerdown;
wire [1599:0] wire_cent_unit0_rxpcsdprioout;
wire wire_cent_unit0_rxphfifox4byteselout;
wire wire_cent_unit0_rxphfifox4rdenableout;
wire wire_cent_unit0_rxphfifox4wrclkout;
wire wire_cent_unit0_rxphfifox4wrenableout;
wire [1799:0] wire_cent_unit0_rxpmadprioout;
wire [5:0] wire_cent_unit0_txanalogresetout;
wire [3:0] wire_cent_unit0_txctrlout;
wire [31:0] wire_cent_unit0_txdataout;
wire [5:0] wire_cent_unit0_txdetectrxpowerdown;
wire [3:0] wire_cent_unit0_txdigitalresetout;
wire [5:0] wire_cent_unit0_txobpowerdown;
wire [599:0] wire_cent_unit0_txpcsdprioout;
wire wire_cent_unit0_txphfifox4byteselout;
wire wire_cent_unit0_txphfifox4rdclkout;
wire wire_cent_unit0_txphfifox4rdenableout;
wire wire_cent_unit0_txphfifox4wrenableout;
wire [1799:0] wire_cent_unit0_txpmadprioout;
wire wire_cent_unit1_autospdx4configsel;
wire wire_cent_unit1_autospdx4rateswitchout;
wire wire_cent_unit1_autospdx4spdchg;
wire [1:0] wire_cent_unit1_clkdivpowerdn;
wire [599:0] wire_cent_unit1_cmudividerdprioout;
wire [1799:0] wire_cent_unit1_cmuplldprioout;
wire wire_cent_unit1_dpriodisableout;
wire wire_cent_unit1_dprioout;
wire wire_cent_unit1_phfifiox4ptrsreset;
wire [1:0] wire_cent_unit1_pllpowerdn;
wire [1:0] wire_cent_unit1_pllresetout;
wire wire_cent_unit1_quadresetout;
wire [5:0] wire_cent_unit1_rxanalogresetout;
wire [5:0] wire_cent_unit1_rxcrupowerdown;
wire [5:0] wire_cent_unit1_rxcruresetout;
wire [3:0] wire_cent_unit1_rxdigitalresetout;
wire [5:0] wire_cent_unit1_rxibpowerdown;
wire [1599:0] wire_cent_unit1_rxpcsdprioout;
wire wire_cent_unit1_rxphfifox4byteselout;
wire wire_cent_unit1_rxphfifox4rdenableout;
wire wire_cent_unit1_rxphfifox4wrclkout;
wire wire_cent_unit1_rxphfifox4wrenableout;
wire [1799:0] wire_cent_unit1_rxpmadprioout;
wire [5:0] wire_cent_unit1_txanalogresetout;
wire [3:0] wire_cent_unit1_txctrlout;
wire [31:0] wire_cent_unit1_txdataout;
wire [5:0] wire_cent_unit1_txdetectrxpowerdown;
wire [3:0] wire_cent_unit1_txdigitalresetout;
wire [5:0] wire_cent_unit1_txobpowerdown;
wire [599:0] wire_cent_unit1_txpcsdprioout;
wire wire_cent_unit1_txphfifox4byteselout;
wire wire_cent_unit1_txphfifox4rdclkout;
wire wire_cent_unit1_txphfifox4rdenableout;
wire wire_cent_unit1_txphfifox4wrenableout;
wire [1799:0] wire_cent_unit1_txpmadprioout;
wire [3:0] wire_rx_cdr_pll0_clk;
wire [1:0] wire_rx_cdr_pll0_dataout;
wire [299:0] wire_rx_cdr_pll0_dprioout;
wire wire_rx_cdr_pll0_freqlocked;
wire wire_rx_cdr_pll0_locked;
wire wire_rx_cdr_pll0_pfdrefclkout;
wire [3:0] wire_rx_cdr_pll1_clk;
wire [1:0] wire_rx_cdr_pll1_dataout;
wire [299:0] wire_rx_cdr_pll1_dprioout;
wire wire_rx_cdr_pll1_freqlocked;
wire wire_rx_cdr_pll1_locked;
wire wire_rx_cdr_pll1_pfdrefclkout;
wire [3:0] wire_rx_cdr_pll2_clk;
wire [1:0] wire_rx_cdr_pll2_dataout;
wire [299:0] wire_rx_cdr_pll2_dprioout;
wire wire_rx_cdr_pll2_freqlocked;
wire wire_rx_cdr_pll2_locked;
wire wire_rx_cdr_pll2_pfdrefclkout;
wire [3:0] wire_rx_cdr_pll3_clk;
wire [1:0] wire_rx_cdr_pll3_dataout;
wire [299:0] wire_rx_cdr_pll3_dprioout;
wire wire_rx_cdr_pll3_freqlocked;
wire wire_rx_cdr_pll3_locked;
wire wire_rx_cdr_pll3_pfdrefclkout;
wire [3:0] wire_rx_cdr_pll4_clk;
wire [1:0] wire_rx_cdr_pll4_dataout;
wire [299:0] wire_rx_cdr_pll4_dprioout;
wire wire_rx_cdr_pll4_freqlocked;
wire wire_rx_cdr_pll4_locked;
wire wire_rx_cdr_pll4_pfdrefclkout;
wire [3:0] wire_rx_cdr_pll5_clk;
wire [1:0] wire_rx_cdr_pll5_dataout;
wire [299:0] wire_rx_cdr_pll5_dprioout;
wire wire_rx_cdr_pll5_freqlocked;
wire wire_rx_cdr_pll5_locked;
wire wire_rx_cdr_pll5_pfdrefclkout;
wire [3:0] wire_rx_cdr_pll6_clk;
wire [1:0] wire_rx_cdr_pll6_dataout;
wire [299:0] wire_rx_cdr_pll6_dprioout;
wire wire_rx_cdr_pll6_freqlocked;
wire wire_rx_cdr_pll6_locked;
wire wire_rx_cdr_pll6_pfdrefclkout;
wire [3:0] wire_rx_cdr_pll7_clk;
wire [1:0] wire_rx_cdr_pll7_dataout;
wire [299:0] wire_rx_cdr_pll7_dprioout;
wire wire_rx_cdr_pll7_freqlocked;
wire wire_rx_cdr_pll7_locked;
wire wire_rx_cdr_pll7_pfdrefclkout;
wire [3:0] wire_tx_pll0_clk;
wire [299:0] wire_tx_pll0_dprioout;
wire wire_tx_pll0_locked;
wire wire_receive_pcs0_autospdrateswitchout;
wire wire_receive_pcs0_autospdspdchgout;
wire wire_receive_pcs0_cdrctrlearlyeios;
wire wire_receive_pcs0_cdrctrllocktorefclkout;
wire wire_receive_pcs0_coreclkout;
wire [3:0] wire_receive_pcs0_ctrldetect;
wire [39:0] wire_receive_pcs0_dataout;
wire [399:0] wire_receive_pcs0_dprioout;
wire wire_receive_pcs0_iqpphfifobyteselout;
wire wire_receive_pcs0_iqpphfifoptrsresetout;
wire wire_receive_pcs0_iqpphfifordenableout;
wire wire_receive_pcs0_iqpphfifowrclkout;
wire wire_receive_pcs0_iqpphfifowrenableout;
wire [3:0] wire_receive_pcs0_patterndetect;
wire wire_receive_pcs0_phfifobyteserdisableout;
wire wire_receive_pcs0_phfifoptrsresetout;
wire wire_receive_pcs0_phfifordenableout;
wire wire_receive_pcs0_phfiforesetout;
wire wire_receive_pcs0_phfifowrdisableout;
wire wire_receive_pcs0_pipedatavalid;
wire wire_receive_pcs0_pipeelecidle;
wire wire_receive_pcs0_pipephydonestatus;
wire wire_receive_pcs0_pipestatetransdoneout;
wire [2:0] wire_receive_pcs0_pipestatus;
wire wire_receive_pcs0_rateswitchout;
wire [19:0] wire_receive_pcs0_revparallelfdbkdata;
wire wire_receive_pcs0_signaldetect;
wire [3:0] wire_receive_pcs0_syncstatus;
wire wire_receive_pcs1_autospdrateswitchout;
wire wire_receive_pcs1_autospdspdchgout;
wire wire_receive_pcs1_cdrctrlearlyeios;
wire wire_receive_pcs1_cdrctrllocktorefclkout;
wire wire_receive_pcs1_coreclkout;
wire [3:0] wire_receive_pcs1_ctrldetect;
wire [39:0] wire_receive_pcs1_dataout;
wire [399:0] wire_receive_pcs1_dprioout;
wire wire_receive_pcs1_iqpphfifobyteselout;
wire wire_receive_pcs1_iqpphfifoptrsresetout;
wire wire_receive_pcs1_iqpphfifordenableout;
wire wire_receive_pcs1_iqpphfifowrclkout;
wire wire_receive_pcs1_iqpphfifowrenableout;
wire [3:0] wire_receive_pcs1_patterndetect;
wire wire_receive_pcs1_phfifobyteserdisableout;
wire wire_receive_pcs1_phfifoptrsresetout;
wire wire_receive_pcs1_phfifordenableout;
wire wire_receive_pcs1_phfiforesetout;
wire wire_receive_pcs1_phfifowrdisableout;
wire wire_receive_pcs1_pipedatavalid;
wire wire_receive_pcs1_pipeelecidle;
wire wire_receive_pcs1_pipephydonestatus;
wire wire_receive_pcs1_pipestatetransdoneout;
wire [2:0] wire_receive_pcs1_pipestatus;
wire wire_receive_pcs1_rateswitchout;
wire [19:0] wire_receive_pcs1_revparallelfdbkdata;
wire wire_receive_pcs1_signaldetect;
wire [3:0] wire_receive_pcs1_syncstatus;
wire wire_receive_pcs2_autospdrateswitchout;
wire wire_receive_pcs2_autospdspdchgout;
wire wire_receive_pcs2_cdrctrlearlyeios;
wire wire_receive_pcs2_cdrctrllocktorefclkout;
wire wire_receive_pcs2_coreclkout;
wire [3:0] wire_receive_pcs2_ctrldetect;
wire [39:0] wire_receive_pcs2_dataout;
wire [399:0] wire_receive_pcs2_dprioout;
wire wire_receive_pcs2_iqpphfifobyteselout;
wire wire_receive_pcs2_iqpphfifoptrsresetout;
wire wire_receive_pcs2_iqpphfifordenableout;
wire wire_receive_pcs2_iqpphfifowrclkout;
wire wire_receive_pcs2_iqpphfifowrenableout;
wire [3:0] wire_receive_pcs2_patterndetect;
wire wire_receive_pcs2_phfifobyteserdisableout;
wire wire_receive_pcs2_phfifoptrsresetout;
wire wire_receive_pcs2_phfifordenableout;
wire wire_receive_pcs2_phfiforesetout;
wire wire_receive_pcs2_phfifowrdisableout;
wire wire_receive_pcs2_pipedatavalid;
wire wire_receive_pcs2_pipeelecidle;
wire wire_receive_pcs2_pipephydonestatus;
wire wire_receive_pcs2_pipestatetransdoneout;
wire [2:0] wire_receive_pcs2_pipestatus;
wire wire_receive_pcs2_rateswitchout;
wire [19:0] wire_receive_pcs2_revparallelfdbkdata;
wire wire_receive_pcs2_signaldetect;
wire [3:0] wire_receive_pcs2_syncstatus;
wire wire_receive_pcs3_autospdrateswitchout;
wire wire_receive_pcs3_autospdspdchgout;
wire wire_receive_pcs3_cdrctrlearlyeios;
wire wire_receive_pcs3_cdrctrllocktorefclkout;
wire wire_receive_pcs3_coreclkout;
wire [3:0] wire_receive_pcs3_ctrldetect;
wire [39:0] wire_receive_pcs3_dataout;
wire [399:0] wire_receive_pcs3_dprioout;
wire wire_receive_pcs3_iqpphfifobyteselout;
wire wire_receive_pcs3_iqpphfifoptrsresetout;
wire wire_receive_pcs3_iqpphfifordenableout;
wire wire_receive_pcs3_iqpphfifowrclkout;
wire wire_receive_pcs3_iqpphfifowrenableout;
wire [3:0] wire_receive_pcs3_patterndetect;
wire wire_receive_pcs3_phfifobyteserdisableout;
wire wire_receive_pcs3_phfifoptrsresetout;
wire wire_receive_pcs3_phfifordenableout;
wire wire_receive_pcs3_phfiforesetout;
wire wire_receive_pcs3_phfifowrdisableout;
wire wire_receive_pcs3_pipedatavalid;
wire wire_receive_pcs3_pipeelecidle;
wire wire_receive_pcs3_pipephydonestatus;
wire wire_receive_pcs3_pipestatetransdoneout;
wire [2:0] wire_receive_pcs3_pipestatus;
wire wire_receive_pcs3_rateswitchout;
wire [19:0] wire_receive_pcs3_revparallelfdbkdata;
wire wire_receive_pcs3_signaldetect;
wire [3:0] wire_receive_pcs3_syncstatus;
wire wire_receive_pcs4_autospdrateswitchout;
wire wire_receive_pcs4_autospdspdchgout;
wire wire_receive_pcs4_cdrctrlearlyeios;
wire wire_receive_pcs4_cdrctrllocktorefclkout;
wire wire_receive_pcs4_coreclkout;
wire [3:0] wire_receive_pcs4_ctrldetect;
wire [39:0] wire_receive_pcs4_dataout;
wire [399:0] wire_receive_pcs4_dprioout;
wire wire_receive_pcs4_iqpphfifobyteselout;
wire wire_receive_pcs4_iqpphfifoptrsresetout;
wire wire_receive_pcs4_iqpphfifordenableout;
wire wire_receive_pcs4_iqpphfifowrclkout;
wire wire_receive_pcs4_iqpphfifowrenableout;
wire [3:0] wire_receive_pcs4_patterndetect;
wire wire_receive_pcs4_phfifobyteserdisableout;
wire wire_receive_pcs4_phfifoptrsresetout;
wire wire_receive_pcs4_phfifordenableout;
wire wire_receive_pcs4_phfiforesetout;
wire wire_receive_pcs4_phfifowrdisableout;
wire wire_receive_pcs4_pipedatavalid;
wire wire_receive_pcs4_pipeelecidle;
wire wire_receive_pcs4_pipephydonestatus;
wire wire_receive_pcs4_pipestatetransdoneout;
wire [2:0] wire_receive_pcs4_pipestatus;
wire wire_receive_pcs4_rateswitchout;
wire [19:0] wire_receive_pcs4_revparallelfdbkdata;
wire wire_receive_pcs4_signaldetect;
wire [3:0] wire_receive_pcs4_syncstatus;
wire wire_receive_pcs5_autospdrateswitchout;
wire wire_receive_pcs5_autospdspdchgout;
wire wire_receive_pcs5_cdrctrlearlyeios;
wire wire_receive_pcs5_cdrctrllocktorefclkout;
wire wire_receive_pcs5_coreclkout;
wire [3:0] wire_receive_pcs5_ctrldetect;
wire [39:0] wire_receive_pcs5_dataout;
wire [399:0] wire_receive_pcs5_dprioout;
wire wire_receive_pcs5_iqpphfifobyteselout;
wire wire_receive_pcs5_iqpphfifoptrsresetout;
wire wire_receive_pcs5_iqpphfifordenableout;
wire wire_receive_pcs5_iqpphfifowrclkout;
wire wire_receive_pcs5_iqpphfifowrenableout;
wire [3:0] wire_receive_pcs5_patterndetect;
wire wire_receive_pcs5_phfifobyteserdisableout;
wire wire_receive_pcs5_phfifoptrsresetout;
wire wire_receive_pcs5_phfifordenableout;
wire wire_receive_pcs5_phfiforesetout;
wire wire_receive_pcs5_phfifowrdisableout;
wire wire_receive_pcs5_pipedatavalid;
wire wire_receive_pcs5_pipeelecidle;
wire wire_receive_pcs5_pipephydonestatus;
wire wire_receive_pcs5_pipestatetransdoneout;
wire [2:0] wire_receive_pcs5_pipestatus;
wire wire_receive_pcs5_rateswitchout;
wire [19:0] wire_receive_pcs5_revparallelfdbkdata;
wire wire_receive_pcs5_signaldetect;
wire [3:0] wire_receive_pcs5_syncstatus;
wire wire_receive_pcs6_autospdrateswitchout;
wire wire_receive_pcs6_autospdspdchgout;
wire wire_receive_pcs6_cdrctrlearlyeios;
wire wire_receive_pcs6_cdrctrllocktorefclkout;
wire wire_receive_pcs6_coreclkout;
wire [3:0] wire_receive_pcs6_ctrldetect;
wire [39:0] wire_receive_pcs6_dataout;
wire [399:0] wire_receive_pcs6_dprioout;
wire wire_receive_pcs6_iqpphfifobyteselout;
wire wire_receive_pcs6_iqpphfifoptrsresetout;
wire wire_receive_pcs6_iqpphfifordenableout;
wire wire_receive_pcs6_iqpphfifowrclkout;
wire wire_receive_pcs6_iqpphfifowrenableout;
wire [3:0] wire_receive_pcs6_patterndetect;
wire wire_receive_pcs6_phfifobyteserdisableout;
wire wire_receive_pcs6_phfifoptrsresetout;
wire wire_receive_pcs6_phfifordenableout;
wire wire_receive_pcs6_phfiforesetout;
wire wire_receive_pcs6_phfifowrdisableout;
wire wire_receive_pcs6_pipedatavalid;
wire wire_receive_pcs6_pipeelecidle;
wire wire_receive_pcs6_pipephydonestatus;
wire wire_receive_pcs6_pipestatetransdoneout;
wire [2:0] wire_receive_pcs6_pipestatus;
wire wire_receive_pcs6_rateswitchout;
wire [19:0] wire_receive_pcs6_revparallelfdbkdata;
wire wire_receive_pcs6_signaldetect;
wire [3:0] wire_receive_pcs6_syncstatus;
wire wire_receive_pcs7_autospdrateswitchout;
wire wire_receive_pcs7_autospdspdchgout;
wire wire_receive_pcs7_cdrctrlearlyeios;
wire wire_receive_pcs7_cdrctrllocktorefclkout;
wire wire_receive_pcs7_coreclkout;
wire [3:0] wire_receive_pcs7_ctrldetect;
wire [39:0] wire_receive_pcs7_dataout;
wire [399:0] wire_receive_pcs7_dprioout;
wire wire_receive_pcs7_iqpphfifobyteselout;
wire wire_receive_pcs7_iqpphfifoptrsresetout;
wire wire_receive_pcs7_iqpphfifordenableout;
wire wire_receive_pcs7_iqpphfifowrclkout;
wire wire_receive_pcs7_iqpphfifowrenableout;
wire [3:0] wire_receive_pcs7_patterndetect;
wire wire_receive_pcs7_phfifobyteserdisableout;
wire wire_receive_pcs7_phfifoptrsresetout;
wire wire_receive_pcs7_phfifordenableout;
wire wire_receive_pcs7_phfiforesetout;
wire wire_receive_pcs7_phfifowrdisableout;
wire wire_receive_pcs7_pipedatavalid;
wire wire_receive_pcs7_pipeelecidle;
wire wire_receive_pcs7_pipephydonestatus;
wire wire_receive_pcs7_pipestatetransdoneout;
wire [2:0] wire_receive_pcs7_pipestatus;
wire wire_receive_pcs7_rateswitchout;
wire [19:0] wire_receive_pcs7_revparallelfdbkdata;
wire wire_receive_pcs7_signaldetect;
wire [3:0] wire_receive_pcs7_syncstatus;
wire [7:0] wire_receive_pma0_analogtestbus;
wire wire_receive_pma0_clockout;
wire wire_receive_pma0_dataout;
wire [299:0] wire_receive_pma0_dprioout;
wire wire_receive_pma0_locktorefout;
wire [63:0] wire_receive_pma0_recoverdataout;
wire wire_receive_pma0_signaldetect;
wire [7:0] wire_receive_pma1_analogtestbus;
wire wire_receive_pma1_clockout;
wire wire_receive_pma1_dataout;
wire [299:0] wire_receive_pma1_dprioout;
wire wire_receive_pma1_locktorefout;
wire [63:0] wire_receive_pma1_recoverdataout;
wire wire_receive_pma1_signaldetect;
wire [7:0] wire_receive_pma2_analogtestbus;
wire wire_receive_pma2_clockout;
wire wire_receive_pma2_dataout;
wire [299:0] wire_receive_pma2_dprioout;
wire wire_receive_pma2_locktorefout;
wire [63:0] wire_receive_pma2_recoverdataout;
wire wire_receive_pma2_signaldetect;
wire [7:0] wire_receive_pma3_analogtestbus;
wire wire_receive_pma3_clockout;
wire wire_receive_pma3_dataout;
wire [299:0] wire_receive_pma3_dprioout;
wire wire_receive_pma3_locktorefout;
wire [63:0] wire_receive_pma3_recoverdataout;
wire wire_receive_pma3_signaldetect;
wire [7:0] wire_receive_pma4_analogtestbus;
wire wire_receive_pma4_clockout;
wire wire_receive_pma4_dataout;
wire [299:0] wire_receive_pma4_dprioout;
wire wire_receive_pma4_locktorefout;
wire [63:0] wire_receive_pma4_recoverdataout;
wire wire_receive_pma4_signaldetect;
wire [7:0] wire_receive_pma5_analogtestbus;
wire wire_receive_pma5_clockout;
wire wire_receive_pma5_dataout;
wire [299:0] wire_receive_pma5_dprioout;
wire wire_receive_pma5_locktorefout;
wire [63:0] wire_receive_pma5_recoverdataout;
wire wire_receive_pma5_signaldetect;
wire [7:0] wire_receive_pma6_analogtestbus;
wire wire_receive_pma6_clockout;
wire wire_receive_pma6_dataout;
wire [299:0] wire_receive_pma6_dprioout;
wire wire_receive_pma6_locktorefout;
wire [63:0] wire_receive_pma6_recoverdataout;
wire wire_receive_pma6_signaldetect;
wire [7:0] wire_receive_pma7_analogtestbus;
wire wire_receive_pma7_clockout;
wire wire_receive_pma7_dataout;
wire [299:0] wire_receive_pma7_dprioout;
wire wire_receive_pma7_locktorefout;
wire [63:0] wire_receive_pma7_recoverdataout;
wire wire_receive_pma7_signaldetect;
wire wire_transmit_pcs0_coreclkout;
wire [19:0] wire_transmit_pcs0_dataout;
wire [149:0] wire_transmit_pcs0_dprioout;
wire wire_transmit_pcs0_forceelecidleout;
wire [2:0] wire_transmit_pcs0_grayelecidleinferselout;
wire wire_transmit_pcs0_iqpphfifobyteselout;
wire wire_transmit_pcs0_iqpphfifordclkout;
wire wire_transmit_pcs0_iqpphfifordenableout;
wire wire_transmit_pcs0_iqpphfifowrenableout;
wire wire_transmit_pcs0_phfiforddisableout;
wire wire_transmit_pcs0_phfiforesetout;
wire wire_transmit_pcs0_phfifowrenableout;
wire wire_transmit_pcs0_pipeenrevparallellpbkout;
wire [1:0] wire_transmit_pcs0_pipepowerdownout;
wire [3:0] wire_transmit_pcs0_pipepowerstateout;
wire wire_transmit_pcs0_txdetectrx;
wire wire_transmit_pcs1_coreclkout;
wire [19:0] wire_transmit_pcs1_dataout;
wire [149:0] wire_transmit_pcs1_dprioout;
wire wire_transmit_pcs1_forceelecidleout;
wire [2:0] wire_transmit_pcs1_grayelecidleinferselout;
wire wire_transmit_pcs1_iqpphfifobyteselout;
wire wire_transmit_pcs1_iqpphfifordclkout;
wire wire_transmit_pcs1_iqpphfifordenableout;
wire wire_transmit_pcs1_iqpphfifowrenableout;
wire wire_transmit_pcs1_phfiforddisableout;
wire wire_transmit_pcs1_phfiforesetout;
wire wire_transmit_pcs1_phfifowrenableout;
wire wire_transmit_pcs1_pipeenrevparallellpbkout;
wire [1:0] wire_transmit_pcs1_pipepowerdownout;
wire [3:0] wire_transmit_pcs1_pipepowerstateout;
wire wire_transmit_pcs1_txdetectrx;
wire wire_transmit_pcs2_coreclkout;
wire [19:0] wire_transmit_pcs2_dataout;
wire [149:0] wire_transmit_pcs2_dprioout;
wire wire_transmit_pcs2_forceelecidleout;
wire [2:0] wire_transmit_pcs2_grayelecidleinferselout;
wire wire_transmit_pcs2_iqpphfifobyteselout;
wire wire_transmit_pcs2_iqpphfifordclkout;
wire wire_transmit_pcs2_iqpphfifordenableout;
wire wire_transmit_pcs2_iqpphfifowrenableout;
wire wire_transmit_pcs2_phfiforddisableout;
wire wire_transmit_pcs2_phfiforesetout;
wire wire_transmit_pcs2_phfifowrenableout;
wire wire_transmit_pcs2_pipeenrevparallellpbkout;
wire [1:0] wire_transmit_pcs2_pipepowerdownout;
wire [3:0] wire_transmit_pcs2_pipepowerstateout;
wire wire_transmit_pcs2_txdetectrx;
wire wire_transmit_pcs3_coreclkout;
wire [19:0] wire_transmit_pcs3_dataout;
wire [149:0] wire_transmit_pcs3_dprioout;
wire wire_transmit_pcs3_forceelecidleout;
wire [2:0] wire_transmit_pcs3_grayelecidleinferselout;
wire wire_transmit_pcs3_iqpphfifobyteselout;
wire wire_transmit_pcs3_iqpphfifordclkout;
wire wire_transmit_pcs3_iqpphfifordenableout;
wire wire_transmit_pcs3_iqpphfifowrenableout;
wire wire_transmit_pcs3_phfiforddisableout;
wire wire_transmit_pcs3_phfiforesetout;
wire wire_transmit_pcs3_phfifowrenableout;
wire wire_transmit_pcs3_pipeenrevparallellpbkout;
wire [1:0] wire_transmit_pcs3_pipepowerdownout;
wire [3:0] wire_transmit_pcs3_pipepowerstateout;
wire wire_transmit_pcs3_txdetectrx;
wire wire_transmit_pcs4_coreclkout;
wire [19:0] wire_transmit_pcs4_dataout;
wire [149:0] wire_transmit_pcs4_dprioout;
wire wire_transmit_pcs4_forceelecidleout;
wire [2:0] wire_transmit_pcs4_grayelecidleinferselout;
wire wire_transmit_pcs4_iqpphfifobyteselout;
wire wire_transmit_pcs4_iqpphfifordclkout;
wire wire_transmit_pcs4_iqpphfifordenableout;
wire wire_transmit_pcs4_iqpphfifowrenableout;
wire wire_transmit_pcs4_phfiforddisableout;
wire wire_transmit_pcs4_phfiforesetout;
wire wire_transmit_pcs4_phfifowrenableout;
wire wire_transmit_pcs4_pipeenrevparallellpbkout;
wire [1:0] wire_transmit_pcs4_pipepowerdownout;
wire [3:0] wire_transmit_pcs4_pipepowerstateout;
wire wire_transmit_pcs4_txdetectrx;
wire wire_transmit_pcs5_coreclkout;
wire [19:0] wire_transmit_pcs5_dataout;
wire [149:0] wire_transmit_pcs5_dprioout;
wire wire_transmit_pcs5_forceelecidleout;
wire [2:0] wire_transmit_pcs5_grayelecidleinferselout;
wire wire_transmit_pcs5_iqpphfifobyteselout;
wire wire_transmit_pcs5_iqpphfifordclkout;
wire wire_transmit_pcs5_iqpphfifordenableout;
wire wire_transmit_pcs5_iqpphfifowrenableout;
wire wire_transmit_pcs5_phfiforddisableout;
wire wire_transmit_pcs5_phfiforesetout;
wire wire_transmit_pcs5_phfifowrenableout;
wire wire_transmit_pcs5_pipeenrevparallellpbkout;
wire [1:0] wire_transmit_pcs5_pipepowerdownout;
wire [3:0] wire_transmit_pcs5_pipepowerstateout;
wire wire_transmit_pcs5_txdetectrx;
wire wire_transmit_pcs6_coreclkout;
wire [19:0] wire_transmit_pcs6_dataout;
wire [149:0] wire_transmit_pcs6_dprioout;
wire wire_transmit_pcs6_forceelecidleout;
wire [2:0] wire_transmit_pcs6_grayelecidleinferselout;
wire wire_transmit_pcs6_iqpphfifobyteselout;
wire wire_transmit_pcs6_iqpphfifordclkout;
wire wire_transmit_pcs6_iqpphfifordenableout;
wire wire_transmit_pcs6_iqpphfifowrenableout;
wire wire_transmit_pcs6_phfiforddisableout;
wire wire_transmit_pcs6_phfiforesetout;
wire wire_transmit_pcs6_phfifowrenableout;
wire wire_transmit_pcs6_pipeenrevparallellpbkout;
wire [1:0] wire_transmit_pcs6_pipepowerdownout;
wire [3:0] wire_transmit_pcs6_pipepowerstateout;
wire wire_transmit_pcs6_txdetectrx;
wire wire_transmit_pcs7_coreclkout;
wire [19:0] wire_transmit_pcs7_dataout;
wire [149:0] wire_transmit_pcs7_dprioout;
wire wire_transmit_pcs7_forceelecidleout;
wire [2:0] wire_transmit_pcs7_grayelecidleinferselout;
wire wire_transmit_pcs7_iqpphfifobyteselout;
wire wire_transmit_pcs7_iqpphfifordclkout;
wire wire_transmit_pcs7_iqpphfifordenableout;
wire wire_transmit_pcs7_iqpphfifowrenableout;
wire wire_transmit_pcs7_phfiforddisableout;
wire wire_transmit_pcs7_phfiforesetout;
wire wire_transmit_pcs7_phfifowrenableout;
wire wire_transmit_pcs7_pipeenrevparallellpbkout;
wire [1:0] wire_transmit_pcs7_pipepowerdownout;
wire [3:0] wire_transmit_pcs7_pipepowerstateout;
wire wire_transmit_pcs7_txdetectrx;
wire wire_transmit_pma0_clockout;
wire wire_transmit_pma0_dataout;
wire [299:0] wire_transmit_pma0_dprioout;
wire wire_transmit_pma0_rxdetectvalidout;
wire wire_transmit_pma0_rxfoundout;
wire wire_transmit_pma1_clockout;
wire wire_transmit_pma1_dataout;
wire [299:0] wire_transmit_pma1_dprioout;
wire wire_transmit_pma1_rxdetectvalidout;
wire wire_transmit_pma1_rxfoundout;
wire wire_transmit_pma2_clockout;
wire wire_transmit_pma2_dataout;
wire [299:0] wire_transmit_pma2_dprioout;
wire wire_transmit_pma2_rxdetectvalidout;
wire wire_transmit_pma2_rxfoundout;
wire wire_transmit_pma3_clockout;
wire wire_transmit_pma3_dataout;
wire [299:0] wire_transmit_pma3_dprioout;
wire wire_transmit_pma3_rxdetectvalidout;
wire wire_transmit_pma3_rxfoundout;
wire wire_transmit_pma4_clockout;
wire wire_transmit_pma4_dataout;
wire [299:0] wire_transmit_pma4_dprioout;
wire wire_transmit_pma4_rxdetectvalidout;
wire wire_transmit_pma4_rxfoundout;
wire wire_transmit_pma5_clockout;
wire wire_transmit_pma5_dataout;
wire [299:0] wire_transmit_pma5_dprioout;
wire wire_transmit_pma5_rxdetectvalidout;
wire wire_transmit_pma5_rxfoundout;
wire wire_transmit_pma6_clockout;
wire wire_transmit_pma6_dataout;
wire [299:0] wire_transmit_pma6_dprioout;
wire wire_transmit_pma6_rxdetectvalidout;
wire wire_transmit_pma6_rxfoundout;
wire wire_transmit_pma7_clockout;
wire wire_transmit_pma7_dataout;
wire [299:0] wire_transmit_pma7_dprioout;
wire wire_transmit_pma7_rxdetectvalidout;
wire wire_transmit_pma7_rxfoundout;
wire cal_blk_powerdown;
wire [1:0] cent_unit_clkdivpowerdn;
wire [1199:0] cent_unit_cmudividerdprioout;
wire [3599:0] cent_unit_cmuplldprioout;
wire [3:0] cent_unit_pllpowerdn;
wire [3:0] cent_unit_pllresetout;
wire [1:0] cent_unit_quadresetout;
wire [11:0] cent_unit_rxcrupowerdn;
wire [11:0] cent_unit_rxibpowerdn;
wire [3199:0] cent_unit_rxpcsdprioin;
wire [3199:0] cent_unit_rxpcsdprioout;
wire [3599:0] cent_unit_rxpmadprioin;
wire [3599:0] cent_unit_rxpmadprioout;
wire [2399:0] cent_unit_tx_dprioin;
wire [63:0] cent_unit_tx_xgmdataout;
wire [7:0] cent_unit_txctrlout;
wire [11:0] cent_unit_txdetectrxpowerdn;
wire [1199:0] cent_unit_txdprioout;
wire [11:0] cent_unit_txobpowerdn;
wire [3599:0] cent_unit_txpmadprioin;
wire [3599:0] cent_unit_txpmadprioout;
wire [7:0] clk_div_clk0in;
wire [1199:0] clk_div_cmudividerdprioin;
wire [1:0] clk_div_pclkin;
wire [3:0] cmu_analogfastrefclkout;
wire [3:0] cmu_analogrefclkout;
wire [1:0] cmu_analogrefclkpulse;
wire [0:0] coreclkout_bi_quad_wire;
wire [1:0] coreclkout_wire;
wire [11:0] fixedclk_to_cmu;
wire [23:0] grayelecidleinfersel_from_tx;
wire [1:0] int_autospdx4configsel;
wire [1:0] int_autospdx4rateswitchout;
wire [1:0] int_autospdx4spdchg;
wire [7:0] int_hipautospdrateswitchout;
wire [1:0] int_hiprateswtichdone;
wire [1:0] int_phfifiox4ptrsreset;
wire [7:0] int_pipeenrevparallellpbkfromtx;
wire [1:0] int_rateswitch;
wire [7:0] int_rx_autospdspdchgout;
wire [23:0] int_rx_autospdxnconfigsel;
wire [23:0] int_rx_autospdxnspdchg;
wire [7:0] int_rx_coreclkout;
wire [0:0] int_rx_digitalreset_reg;
wire [15:0] int_rx_iqpautospdxnspgchg;
wire [7:0] int_rx_iqpphfifobyteselout;
wire [7:0] int_rx_iqpphfifoptrsresetout;
wire [7:0] int_rx_iqpphfifordenableout;
wire [7:0] int_rx_iqpphfifowrclkout;
wire [7:0] int_rx_iqpphfifowrenableout;
wire [15:0] int_rx_iqpphfifoxnbytesel;
wire [15:0] int_rx_iqpphfifoxnptrsreset;
wire [15:0] int_rx_iqpphfifoxnrdenable;
wire [15:0] int_rx_iqpphfifoxnwrclk;
wire [15:0] int_rx_iqpphfifoxnwrenable;
wire [23:0] int_rx_phfifioxnptrsreset;
wire [7:0] int_rx_phfifobyteserdisable;
wire [7:0] int_rx_phfifoptrsresetout;
wire [7:0] int_rx_phfifordenableout;
wire [7:0] int_rx_phfiforesetout;
wire [7:0] int_rx_phfifowrdisableout;
wire [23:0] int_rx_phfifoxnbytesel;
wire [23:0] int_rx_phfifoxnrdenable;
wire [23:0] int_rx_phfifoxnwrclk;
wire [23:0] int_rx_phfifoxnwrenable;
wire [7:0] int_rx_rateswitchout;
wire [1:0] int_rxcoreclk;
wire [7:0] int_rxpcs_cdrctrlearlyeios;
wire [1:0] int_rxphfifordenable;
wire [1:0] int_rxphfiforeset;
wire [1:0] int_rxphfifox4byteselout;
wire [1:0] int_rxphfifox4rdenableout;
wire [1:0] int_rxphfifox4wrclkout;
wire [1:0] int_rxphfifox4wrenableout;
wire [7:0] int_tx_coreclkout;
wire [0:0] int_tx_digitalreset_reg;
wire [7:0] int_tx_iqpphfifobyteselout;
wire [7:0] int_tx_iqpphfifordclkout;
wire [7:0] int_tx_iqpphfifordenableout;
wire [7:0] int_tx_iqpphfifowrenableout;
wire [15:0] int_tx_iqpphfifoxnbytesel;
wire [15:0] int_tx_iqpphfifoxnrdclk;
wire [15:0] int_tx_iqpphfifoxnrdenable;
wire [15:0] int_tx_iqpphfifoxnwrenable;
wire [23:0] int_tx_phfifioxnptrsreset;
wire [7:0] int_tx_phfiforddisableout;
wire [7:0] int_tx_phfiforesetout;
wire [7:0] int_tx_phfifowrenableout;
wire [23:0] int_tx_phfifoxnbytesel;
wire [23:0] int_tx_phfifoxnrdclk;
wire [23:0] int_tx_phfifoxnrdenable;
wire [23:0] int_tx_phfifoxnwrenable;
wire [1:0] int_txcoreclk;
wire [1:0] int_txphfiforddisable;
wire [1:0] int_txphfiforeset;
wire [1:0] int_txphfifowrenable;
wire [1:0] int_txphfifox4byteselout;
wire [1:0] int_txphfifox4rdclkout;
wire [1:0] int_txphfifox4rdenableout;
wire [1:0] int_txphfifox4wrenableout;
wire [1:0] nonusertocmu_out;
wire [7:0] pipedatavalid_out;
wire [7:0] pipeelecidle_out;
wire [19:0] pll0_clkin;
wire [599:0] pll0_dprioin;
wire [599:0] pll0_dprioout;
wire [7:0] pll0_out;
wire [15:0] pll_ch_dataout_wire;
wire [2399:0] pll_ch_dprioout;
wire [3599:0] pll_cmuplldprioout;
wire [0:0] pll_inclk_wire;
wire [1:0] pll_locked_out;
wire [0:0] pll_powerdown;
wire [3:0] pllpowerdn_in;
wire [3:0] pllreset_in;
wire [0:0] reconfig_togxb_busy;
wire [0:0] reconfig_togxb_disable;
wire [0:0] reconfig_togxb_in;
wire [0:0] reconfig_togxb_load;
wire [1:0] refclk_pma;
wire [11:0] rx_analogreset_in;
wire [11:0] rx_analogreset_out;
wire [7:0] rx_coreclk_in;
wire [79:0] rx_cruclk_in;
wire [31:0] rx_deserclock_in;
wire [7:0] rx_digitalreset_in;
wire [7:0] rx_digitalreset_out;
wire [23:0] rx_elecidleinfersel;
wire [7:0] rx_enapatternalign;
wire [7:0] rx_freqlocked_wire;
wire [7:0] rx_locktodata;
wire [7:0] rx_locktodata_wire;
wire [7:0] rx_locktorefclk_wire;
wire [127:0] rx_out_wire;
wire [15:0] rx_pcs_rxfound_wire;
wire [3199:0] rx_pcsdprioin_wire;
wire [3199:0] rx_pcsdprioout;
wire [7:0] rx_phfifordenable;
wire [7:0] rx_phfiforeset;
wire [7:0] rx_phfifowrdisable;
wire [7:0] rx_pipestatetransdoneout;
wire [7:0] rx_pldcruclk_in;
wire [31:0] rx_pll_clkout;
wire [7:0] rx_pll_pfdrefclkout_wire;
wire [7:0] rx_plllocked_wire;
wire [135:0] rx_pma_analogtestbus;
wire [7:0] rx_pma_clockout;
wire [7:0] rx_pma_dataout;
wire [7:0] rx_pma_locktorefout;
wire [159:0] rx_pma_recoverdataout_wire;
wire [3599:0] rx_pmadprioin_wire;
wire [3599:0] rx_pmadprioout;
wire [7:0] rx_powerdown;
wire [11:0] rx_powerdown_in;
wire [7:0] rx_prbscidenable;
wire [159:0] rx_revparallelfdbkdata;
wire [7:0] rx_rmfiforeset;
wire [11:0] rx_rxcruresetout;
wire [7:0] rx_signaldetect_wire;
wire [1:0] rxphfifowrdisable;
wire [3599:0] rxpll_dprioin;
wire [11:0] tx_analogreset_out;
wire [7:0] tx_clkout_int_wire;
wire [7:0] tx_coreclk_in;
wire [127:0] tx_datain_wire;
wire [159:0] tx_dataout_pcs_to_pma;
wire [7:0] tx_digitalreset_in;
wire [7:0] tx_digitalreset_out;
wire [2399:0] tx_dprioin_wire;
wire [15:0] tx_forcedisp_wire;
wire [7:0] tx_invpolarity;
wire [7:0] tx_localrefclk;
wire [7:0] tx_pcs_forceelecidleout;
wire [7:0] tx_phfiforeset;
wire [15:0] tx_pipepowerdownout;
wire [31:0] tx_pipepowerstateout;
wire [7:0] tx_pipeswing;
wire [3599:0] tx_pmadprioin_wire;
wire [3599:0] tx_pmadprioout;
wire [7:0] tx_revparallellpbken;
wire [7:0] tx_rxdetectvalidout;
wire [7:0] tx_rxfoundout;
wire [1199:0] tx_txdprioout;
wire [7:0] txdetectrxout;
wire [1:0] w_cent_unit_dpriodisableout1w;
// synopsys translate_off
initial
rx_digitalreset_reg0c[0:0] = 0;
// synopsys translate_on
always @ ( posedge wire_rx_digitalreset_reg0c_clk[0:0])
rx_digitalreset_reg0c[0:0] <= wire_rx_digitalreset_reg0c_d[0:0];
// synopsys translate_off
initial
rx_digitalreset_reg0c[1:1] = 0;
// synopsys translate_on
always @ ( posedge wire_rx_digitalreset_reg0c_clk[1:1])
rx_digitalreset_reg0c[1:1] <= wire_rx_digitalreset_reg0c_d[1:1];
// synopsys translate_off
initial
rx_digitalreset_reg0c[2:2] = 0;
// synopsys translate_on
always @ ( posedge wire_rx_digitalreset_reg0c_clk[2:2])
rx_digitalreset_reg0c[2:2] <= wire_rx_digitalreset_reg0c_d[2:2];
assign
wire_rx_digitalreset_reg0c_d = {rx_digitalreset_reg0c[1:0], rx_digitalreset[0]};
assign
wire_rx_digitalreset_reg0c_clk = {3{coreclkout_wire[0]}};
// synopsys translate_off
initial
tx_digitalreset_reg0c[0:0] = 0;
// synopsys translate_on
always @ ( posedge wire_tx_digitalreset_reg0c_clk[0:0])
tx_digitalreset_reg0c[0:0] <= wire_tx_digitalreset_reg0c_d[0:0];
// synopsys translate_off
initial
tx_digitalreset_reg0c[1:1] = 0;
// synopsys translate_on
always @ ( posedge wire_tx_digitalreset_reg0c_clk[1:1])
tx_digitalreset_reg0c[1:1] <= wire_tx_digitalreset_reg0c_d[1:1];
// synopsys translate_off
initial
tx_digitalreset_reg0c[2:2] = 0;
// synopsys translate_on
always @ ( posedge wire_tx_digitalreset_reg0c_clk[2:2])
tx_digitalreset_reg0c[2:2] <= wire_tx_digitalreset_reg0c_d[2:2];
assign
wire_tx_digitalreset_reg0c_d = {tx_digitalreset_reg0c[1:0], tx_digitalreset[0]};
assign
wire_tx_digitalreset_reg0c_clk = {3{coreclkout_wire[0]}};
stratixiv_hssi_calibration_block cal_blk0
(
.calibrationstatus(),
.clk(cal_blk_clk),
.enabletestbus(1'b1),
.nonusertocmu(wire_cal_blk0_nonusertocmu),
.powerdn(cal_blk_powerdown)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.testctrl(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
stratixiv_hssi_calibration_block cal_blk1
(
.calibrationstatus(),
.clk(cal_blk_clk),
.enabletestbus(1'b1),
.nonusertocmu(wire_cal_blk1_nonusertocmu),
.powerdn(cal_blk_powerdown)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.testctrl(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
stratixiv_hssi_clock_divider central_clk_div0
(
.analogfastrefclkout(wire_central_clk_div0_analogfastrefclkout),
.analogfastrefclkoutshifted(),
.analogrefclkout(wire_central_clk_div0_analogrefclkout),
.analogrefclkoutshifted(),
.analogrefclkpulse(wire_central_clk_div0_analogrefclkpulse),
.analogrefclkpulseshifted(),
.clk0in(clk_div_clk0in[3:0]),
.coreclkout(wire_central_clk_div0_coreclkout),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(cent_unit_cmudividerdprioout[499:400]),
.dprioout(wire_central_clk_div0_dprioout),
.powerdn(cent_unit_clkdivpowerdn[0]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitch(int_autospdx4rateswitchout[0]),
.rateswitchbaseclock(),
.rateswitchdone(wire_central_clk_div0_rateswitchdone),
.rateswitchout(),
.refclkout(wire_central_clk_div0_refclkout)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk1in({4{1'b0}}),
.rateswitchbaseclkin({2{1'b0}}),
.rateswitchdonein({2{1'b0}}),
.refclkdig(1'b0),
.refclkin({2{1'b0}}),
.vcobypassin(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
central_clk_div0.divide_by = 5,
central_clk_div0.divider_type = "CENTRAL_ENHANCED",
central_clk_div0.effective_data_rate = "5000 Mbps",
central_clk_div0.enable_dynamic_divider = "true",
central_clk_div0.enable_refclk_out = "true",
central_clk_div0.inclk_select = 0,
central_clk_div0.logical_channel_address = 0,
central_clk_div0.pre_divide_by = 1,
central_clk_div0.refclkin_select = 0,
central_clk_div0.select_local_rate_switch_base_clock = "true",
central_clk_div0.select_local_rate_switch_done = "true",
central_clk_div0.select_local_refclk = "true",
central_clk_div0.sim_analogfastrefclkout_phase_shift = 0,
central_clk_div0.sim_analogrefclkout_phase_shift = 0,
central_clk_div0.sim_coreclkout_phase_shift = 0,
central_clk_div0.sim_refclkout_phase_shift = 0,
central_clk_div0.use_coreclk_out_post_divider = "true",
central_clk_div0.use_refclk_post_divider = "false",
central_clk_div0.use_vco_bypass = "false",
central_clk_div0.lpm_type = "stratixiv_hssi_clock_divider";
stratixiv_hssi_clock_divider central_clk_div1
(
.analogfastrefclkout(wire_central_clk_div1_analogfastrefclkout),
.analogfastrefclkoutshifted(),
.analogrefclkout(wire_central_clk_div1_analogrefclkout),
.analogrefclkoutshifted(),
.analogrefclkpulse(wire_central_clk_div1_analogrefclkpulse),
.analogrefclkpulseshifted(),
.clk0in(clk_div_clk0in[7:4]),
.coreclkout(wire_central_clk_div1_coreclkout),
.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
.dprioin(cent_unit_cmudividerdprioout[1099:1000]),
.dprioout(wire_central_clk_div1_dprioout),
.powerdn(cent_unit_clkdivpowerdn[1]),
.quadreset(cent_unit_quadresetout[1]),
.rateswitchbaseclock(),
.rateswitchdone(wire_central_clk_div1_rateswitchdone),
.rateswitchdonein({{1{1'b0}}, int_hiprateswtichdone[0]}),
.rateswitchout(),
.refclkin({{1{1'b0}}, clk_div_pclkin[1]}),
.refclkout(wire_central_clk_div1_refclkout)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk1in({4{1'b0}}),
.rateswitch(1'b0),
.rateswitchbaseclkin({2{1'b0}}),
.refclkdig(1'b0),
.vcobypassin(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
central_clk_div1.divide_by = 5,
central_clk_div1.divider_type = "CENTRAL_ENHANCED",
central_clk_div1.effective_data_rate = "5000 Mbps",
central_clk_div1.enable_dynamic_divider = "true",
central_clk_div1.enable_refclk_out = "true",
central_clk_div1.inclk_select = 0,
central_clk_div1.logical_channel_address = 0,
central_clk_div1.pre_divide_by = 1,
central_clk_div1.refclkin_select = 0,
central_clk_div1.select_local_rate_switch_done = "false",
central_clk_div1.select_local_refclk = "false",
central_clk_div1.sim_analogfastrefclkout_phase_shift = 0,
central_clk_div1.sim_analogrefclkout_phase_shift = 0,
central_clk_div1.sim_coreclkout_phase_shift = 0,
central_clk_div1.sim_refclkout_phase_shift = 0,
central_clk_div1.use_coreclk_out_post_divider = "true",
central_clk_div1.use_refclk_post_divider = "false",
central_clk_div1.use_vco_bypass = "false",
central_clk_div1.lpm_type = "stratixiv_hssi_clock_divider";
stratixiv_hssi_cmu cent_unit0
(
.adet({4{1'b0}}),
.alignstatus(),
.autospdx4configsel(wire_cent_unit0_autospdx4configsel),
.autospdx4rateswitchout(wire_cent_unit0_autospdx4rateswitchout),
.autospdx4spdchg(wire_cent_unit0_autospdx4spdchg),
.clkdivpowerdn(wire_cent_unit0_clkdivpowerdn),
.cmudividerdprioin({clk_div_cmudividerdprioin[599:0]}),
.cmudividerdprioout(wire_cent_unit0_cmudividerdprioout),
.cmuplldprioin(pll_cmuplldprioout[1799:0]),
.cmuplldprioout(wire_cent_unit0_cmuplldprioout),
.digitaltestout(),
.dpclk(reconfig_clk),
.dpriodisable(reconfig_togxb_disable),
.dpriodisableout(wire_cent_unit0_dpriodisableout),
.dprioin(reconfig_togxb_in),
.dprioload(reconfig_togxb_load),
.dpriooe(),
.dprioout(wire_cent_unit0_dprioout),
.enabledeskew(),
.extra10gout(),
.fiforesetrd(),
.fixedclk({{2{1'b0}}, fixedclk_to_cmu[3:0]}),
.lccmutestbus(),
.nonuserfromcal(nonusertocmu_out[0]),
.phfifiox4ptrsreset(wire_cent_unit0_phfifiox4ptrsreset),
.pllpowerdn(wire_cent_unit0_pllpowerdn),
.pllresetout(wire_cent_unit0_pllresetout),
.quadreset(gxb_powerdown[0]),
.quadresetout(wire_cent_unit0_quadresetout),
.rateswitch(int_rateswitch[0]),
.rateswitchdonein(int_hiprateswtichdone[0]),
.rdalign({4{1'b0}}),
.rdenablesync(1'b0),
.recovclk(1'b0),
.refclkdividerdprioin({2{1'b0}}),
.refclkdividerdprioout(),
.rxadcepowerdown(),
.rxadceresetout(),
.rxanalogreset({{2{1'b0}}, rx_analogreset_in[3:0]}),
.rxanalogresetout(wire_cent_unit0_rxanalogresetout),
.rxclk(refclk_pma[0]),
.rxcoreclk(int_rxcoreclk[0]),
.rxcrupowerdown(wire_cent_unit0_rxcrupowerdown),
.rxcruresetout(wire_cent_unit0_rxcruresetout),
.rxctrl({4{1'b0}}),
.rxctrlout(),
.rxdatain({32{1'b0}}),
.rxdataout(),
.rxdatavalid({4{1'b0}}),
.rxdigitalreset({rx_digitalreset_in[3:0]}),
.rxdigitalresetout(wire_cent_unit0_rxdigitalresetout),
.rxibpowerdown(wire_cent_unit0_rxibpowerdown),
.rxpcsdprioin({cent_unit_rxpcsdprioin[1599:0]}),
.rxpcsdprioout(wire_cent_unit0_rxpcsdprioout),
.rxphfifordenable(int_rxphfifordenable[0]),
.rxphfiforeset(int_rxphfiforeset[0]),
.rxphfifowrdisable(rxphfifowrdisable[0]),
.rxphfifox4byteselout(wire_cent_unit0_rxphfifox4byteselout),
.rxphfifox4rdenableout(wire_cent_unit0_rxphfifox4rdenableout),
.rxphfifox4wrclkout(wire_cent_unit0_rxphfifox4wrclkout),
.rxphfifox4wrenableout(wire_cent_unit0_rxphfifox4wrenableout),
.rxpmadprioin({cent_unit_rxpmadprioin[1799:0]}),
.rxpmadprioout(wire_cent_unit0_rxpmadprioout),
.rxpowerdown({{2{1'b0}}, rx_powerdown_in[3:0]}),
.rxrunningdisp({4{1'b0}}),
.scanout(),
.syncstatus({4{1'b0}}),
.testout(),
.txanalogresetout(wire_cent_unit0_txanalogresetout),
.txclk(refclk_pma[0]),
.txcoreclk(int_txcoreclk[0]),
.txctrl({4{1'b0}}),
.txctrlout(wire_cent_unit0_txctrlout),
.txdatain({32{1'b0}}),
.txdataout(wire_cent_unit0_txdataout),
.txdetectrxpowerdown(wire_cent_unit0_txdetectrxpowerdown),
.txdigitalreset({tx_digitalreset_in[3:0]}),
.txdigitalresetout(wire_cent_unit0_txdigitalresetout),
.txdividerpowerdown(),
.txobpowerdown(wire_cent_unit0_txobpowerdown),
.txpcsdprioin({cent_unit_tx_dprioin[599:0]}),
.txpcsdprioout(wire_cent_unit0_txpcsdprioout),
.txphfiforddisable(int_txphfiforddisable[0]),
.txphfiforeset(int_txphfiforeset[0]),
.txphfifowrenable(int_txphfifowrenable[0]),
.txphfifox4byteselout(wire_cent_unit0_txphfifox4byteselout),
.txphfifox4rdclkout(wire_cent_unit0_txphfifox4rdclkout),
.txphfifox4rdenableout(wire_cent_unit0_txphfifox4rdenableout),
.txphfifox4wrenableout(wire_cent_unit0_txphfifox4wrenableout),
.txpllreset({{1{1'b0}}, pll_powerdown[0]}),
.txpmadprioin({cent_unit_txpmadprioin[1799:0]}),
.txpmadprioout(wire_cent_unit0_txpmadprioout)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.extra10gin({7{1'b0}}),
.lccmurtestbussel({3{1'b0}}),
.pmacramtest(1'b0),
.scanclk(1'b0),
.scanin({23{1'b0}}),
.scanmode(1'b0),
.scanshift(1'b0),
.testin({10000{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cent_unit0.auto_spd_deassert_ph_fifo_rst_count = 8,
cent_unit0.auto_spd_phystatus_notify_count = 14,
cent_unit0.bonded_quad_mode = "driver",
cent_unit0.devaddr = ((((starting_channel_number / 4) + 0) % 32) + 1),
cent_unit0.in_xaui_mode = "false",
cent_unit0.offset_all_errors_align = "false",
cent_unit0.pipe_auto_speed_nego_enable = "true",
cent_unit0.pipe_freq_scale_mode = "Frequency",
cent_unit0.pma_done_count = 249950,
cent_unit0.portaddr = (((starting_channel_number + 0) / 128) + 1),
cent_unit0.rx0_auto_spd_self_switch_enable = "true",
cent_unit0.rx0_channel_bonding = "x8",
cent_unit0.rx0_clk1_mux_select = "recovered clock",
cent_unit0.rx0_clk2_mux_select = "digital reference clock",
cent_unit0.rx0_ph_fifo_reg_mode = "false",
cent_unit0.rx0_rd_clk_mux_select = "core clock",
cent_unit0.rx0_recovered_clk_mux_select = "recovered clock",
cent_unit0.rx0_reset_clock_output_during_digital_reset = "false",
cent_unit0.rx0_use_double_data_mode = "true",
cent_unit0.tx0_auto_spd_self_switch_enable = "true",
cent_unit0.tx0_channel_bonding = "x8",
cent_unit0.tx0_ph_fifo_reg_mode = "false",
cent_unit0.tx0_rd_clk_mux_select = "cmu_clock_divider",
cent_unit0.tx0_use_double_data_mode = "true",
cent_unit0.tx0_wr_clk_mux_select = "core_clk",
cent_unit0.use_deskew_fifo = "false",
cent_unit0.vcceh_voltage = "3.0V",
cent_unit0.lpm_type = "stratixiv_hssi_cmu";
stratixiv_hssi_cmu cent_unit1
(
.adet({4{1'b0}}),
.alignstatus(),
.autospdx4configsel(wire_cent_unit1_autospdx4configsel),
.autospdx4rateswitchout(wire_cent_unit1_autospdx4rateswitchout),
.autospdx4spdchg(wire_cent_unit1_autospdx4spdchg),
.clkdivpowerdn(wire_cent_unit1_clkdivpowerdn),
.cmudividerdprioin({clk_div_cmudividerdprioin[1199:600]}),
.cmudividerdprioout(wire_cent_unit1_cmudividerdprioout),
.cmuplldprioin(pll_cmuplldprioout[3599:1800]),
.cmuplldprioout(wire_cent_unit1_cmuplldprioout),
.digitaltestout(),
.dpclk(reconfig_clk),
.dpriodisable(reconfig_togxb_disable),
.dpriodisableout(wire_cent_unit1_dpriodisableout),
.dprioin(reconfig_togxb_in),
.dprioload(reconfig_togxb_load),
.dpriooe(),
.dprioout(wire_cent_unit1_dprioout),
.enabledeskew(),
.extra10gout(),
.fiforesetrd(),
.fixedclk({{2{1'b0}}, fixedclk_to_cmu[9:6]}),
.lccmutestbus(),
.nonuserfromcal(nonusertocmu_out[1]),
.phfifiox4ptrsreset(wire_cent_unit1_phfifiox4ptrsreset),
.pllpowerdn(wire_cent_unit1_pllpowerdn),
.pllresetout(wire_cent_unit1_pllresetout),
.quadreset(gxb_powerdown[0]),
.quadresetout(wire_cent_unit1_quadresetout),
.rateswitch(int_rateswitch[1]),
.rateswitchdonein(int_hiprateswtichdone[1]),
.rdalign({4{1'b0}}),
.rdenablesync(1'b0),
.recovclk(1'b0),
.refclkdividerdprioin({2{1'b0}}),
.refclkdividerdprioout(),
.rxadcepowerdown(),
.rxadceresetout(),
.rxanalogreset({{2{1'b0}}, rx_analogreset_in[7:4]}),
.rxanalogresetout(wire_cent_unit1_rxanalogresetout),
.rxclk(refclk_pma[1]),
.rxcoreclk(int_rxcoreclk[1]),
.rxcrupowerdown(wire_cent_unit1_rxcrupowerdown),
.rxcruresetout(wire_cent_unit1_rxcruresetout),
.rxctrl({4{1'b0}}),
.rxctrlout(),
.rxdatain({32{1'b0}}),
.rxdataout(),
.rxdatavalid({4{1'b0}}),
.rxdigitalreset({rx_digitalreset_in[7:4]}),
.rxdigitalresetout(wire_cent_unit1_rxdigitalresetout),
.rxibpowerdown(wire_cent_unit1_rxibpowerdown),
.rxpcsdprioin({cent_unit_rxpcsdprioin[3199:1600]}),
.rxpcsdprioout(wire_cent_unit1_rxpcsdprioout),
.rxphfifordenable(int_rxphfifordenable[1]),
.rxphfiforeset(int_rxphfiforeset[1]),
.rxphfifowrdisable(rxphfifowrdisable[1]),
.rxphfifox4byteselout(wire_cent_unit1_rxphfifox4byteselout),
.rxphfifox4rdenableout(wire_cent_unit1_rxphfifox4rdenableout),
.rxphfifox4wrclkout(wire_cent_unit1_rxphfifox4wrclkout),
.rxphfifox4wrenableout(wire_cent_unit1_rxphfifox4wrenableout),
.rxpmadprioin({cent_unit_rxpmadprioin[3599:1800]}),
.rxpmadprioout(wire_cent_unit1_rxpmadprioout),
.rxpowerdown({{2{1'b0}}, rx_powerdown_in[7:4]}),
.rxrunningdisp({4{1'b0}}),
.scanout(),
.syncstatus({4{1'b0}}),
.testout(),
.txanalogresetout(wire_cent_unit1_txanalogresetout),
.txclk(refclk_pma[1]),
.txcoreclk(int_txcoreclk[1]),
.txctrl({4{1'b0}}),
.txctrlout(wire_cent_unit1_txctrlout),
.txdatain({32{1'b0}}),
.txdataout(wire_cent_unit1_txdataout),
.txdetectrxpowerdown(wire_cent_unit1_txdetectrxpowerdown),
.txdigitalreset({tx_digitalreset_in[7:4]}),
.txdigitalresetout(wire_cent_unit1_txdigitalresetout),
.txdividerpowerdown(),
.txobpowerdown(wire_cent_unit1_txobpowerdown),
.txpcsdprioin({cent_unit_tx_dprioin[1199:600]}),
.txpcsdprioout(wire_cent_unit1_txpcsdprioout),
.txphfiforddisable(int_txphfiforddisable[1]),
.txphfiforeset(int_txphfiforeset[1]),
.txphfifowrenable(int_txphfifowrenable[1]),
.txphfifox4byteselout(wire_cent_unit1_txphfifox4byteselout),
.txphfifox4rdclkout(wire_cent_unit1_txphfifox4rdclkout),
.txphfifox4rdenableout(wire_cent_unit1_txphfifox4rdenableout),
.txphfifox4wrenableout(wire_cent_unit1_txphfifox4wrenableout),
.txpmadprioin({cent_unit_txpmadprioin[3599:1800]}),
.txpmadprioout(wire_cent_unit1_txpmadprioout)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.extra10gin({7{1'b0}}),
.lccmurtestbussel({3{1'b0}}),
.pmacramtest(1'b0),
.scanclk(1'b0),
.scanin({23{1'b0}}),
.scanmode(1'b0),
.scanshift(1'b0),
.testin({10000{1'b0}}),
.txpllreset({2{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cent_unit1.auto_spd_deassert_ph_fifo_rst_count = 8,
cent_unit1.auto_spd_phystatus_notify_count = 14,
cent_unit1.bonded_quad_mode = "receiver",
cent_unit1.devaddr = ((((starting_channel_number / 4) + 1) % 32) + 1),
cent_unit1.in_xaui_mode = "false",
cent_unit1.offset_all_errors_align = "false",
cent_unit1.pipe_auto_speed_nego_enable = "true",
cent_unit1.pipe_freq_scale_mode = "Frequency",
cent_unit1.pma_done_count = 249950,
cent_unit1.portaddr = (((starting_channel_number + 4) / 128) + 1),
cent_unit1.rx0_auto_spd_self_switch_enable = "true",
cent_unit1.rx0_channel_bonding = "x8",
cent_unit1.rx0_clk1_mux_select = "recovered clock",
cent_unit1.rx0_clk2_mux_select = "digital reference clock",
cent_unit1.rx0_ph_fifo_reg_mode = "false",
cent_unit1.rx0_rd_clk_mux_select = "core clock",
cent_unit1.rx0_recovered_clk_mux_select = "recovered clock",
cent_unit1.rx0_reset_clock_output_during_digital_reset = "false",
cent_unit1.rx0_use_double_data_mode = "true",
cent_unit1.tx0_auto_spd_self_switch_enable = "true",
cent_unit1.tx0_channel_bonding = "x8",
cent_unit1.tx0_ph_fifo_reg_mode = "false",
cent_unit1.tx0_rd_clk_mux_select = "cmu_clock_divider",
cent_unit1.tx0_use_double_data_mode = "true",
cent_unit1.tx0_wr_clk_mux_select = "core_clk",
cent_unit1.use_deskew_fifo = "false",
cent_unit1.vcceh_voltage = "3.0V",
cent_unit1.lpm_type = "stratixiv_hssi_cmu";
stratixiv_hssi_pll rx_cdr_pll0
(
.areset(rx_rxcruresetout[0]),
.clk(wire_rx_cdr_pll0_clk),
.datain(rx_pma_dataout[0]),
.dataout(wire_rx_cdr_pll0_dataout),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rxpll_dprioin[299:0]),
.dprioout(wire_rx_cdr_pll0_dprioout),
.earlyeios(int_rxpcs_cdrctrlearlyeios[0]),
.freqlocked(wire_rx_cdr_pll0_freqlocked),
.inclk({rx_cruclk_in[9:0]}),
.locked(wire_rx_cdr_pll0_locked),
.locktorefclk(rx_pma_locktorefout[0]),
.pfdfbclkout(),
.pfdrefclkout(wire_rx_cdr_pll0_pfdrefclkout),
.powerdown(cent_unit_rxcrupowerdn[0]),
.rateswitch(int_hipautospdrateswitchout[0]),
.vcobypassout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.extra10gin({6{1'b0}}),
.pfdfbclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
rx_cdr_pll0.bandwidth_type = "Auto",
rx_cdr_pll0.channel_num = ((starting_channel_number + 0) % 4),
rx_cdr_pll0.dprio_config_mode = 6'h00,
rx_cdr_pll0.effective_data_rate = "5000 Mbps",
rx_cdr_pll0.enable_dynamic_divider = "true",
rx_cdr_pll0.fast_lock_control = "false",
rx_cdr_pll0.inclk0_input_period = 10000,
rx_cdr_pll0.input_clock_frequency = "100.0 MHz",
rx_cdr_pll0.m = 25,
rx_cdr_pll0.n = 1,
rx_cdr_pll0.pfd_clk_select = 0,
rx_cdr_pll0.pll_type = "RX CDR",
rx_cdr_pll0.use_refclk_pin = "false",
rx_cdr_pll0.vco_post_scale = 1,
rx_cdr_pll0.lpm_type = "stratixiv_hssi_pll";
stratixiv_hssi_pll rx_cdr_pll1
(
.areset(rx_rxcruresetout[1]),
.clk(wire_rx_cdr_pll1_clk),
.datain(rx_pma_dataout[1]),
.dataout(wire_rx_cdr_pll1_dataout),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rxpll_dprioin[599:300]),
.dprioout(wire_rx_cdr_pll1_dprioout),
.earlyeios(int_rxpcs_cdrctrlearlyeios[1]),
.freqlocked(wire_rx_cdr_pll1_freqlocked),
.inclk({rx_cruclk_in[19:10]}),
.locked(wire_rx_cdr_pll1_locked),
.locktorefclk(rx_pma_locktorefout[1]),
.pfdfbclkout(),
.pfdrefclkout(wire_rx_cdr_pll1_pfdrefclkout),
.powerdown(cent_unit_rxcrupowerdn[1]),
.rateswitch(int_hipautospdrateswitchout[1]),
.vcobypassout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.extra10gin({6{1'b0}}),
.pfdfbclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
rx_cdr_pll1.bandwidth_type = "Auto",
rx_cdr_pll1.channel_num = ((starting_channel_number + 1) % 4),
rx_cdr_pll1.dprio_config_mode = 6'h00,
rx_cdr_pll1.effective_data_rate = "5000 Mbps",
rx_cdr_pll1.enable_dynamic_divider = "true",
rx_cdr_pll1.fast_lock_control = "false",
rx_cdr_pll1.inclk0_input_period = 10000,
rx_cdr_pll1.input_clock_frequency = "100.0 MHz",
rx_cdr_pll1.m = 25,
rx_cdr_pll1.n = 1,
rx_cdr_pll1.pfd_clk_select = 0,
rx_cdr_pll1.pll_type = "RX CDR",
rx_cdr_pll1.use_refclk_pin = "false",
rx_cdr_pll1.vco_post_scale = 1,
rx_cdr_pll1.lpm_type = "stratixiv_hssi_pll";
stratixiv_hssi_pll rx_cdr_pll2
(
.areset(rx_rxcruresetout[2]),
.clk(wire_rx_cdr_pll2_clk),
.datain(rx_pma_dataout[2]),
.dataout(wire_rx_cdr_pll2_dataout),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rxpll_dprioin[899:600]),
.dprioout(wire_rx_cdr_pll2_dprioout),
.earlyeios(int_rxpcs_cdrctrlearlyeios[2]),
.freqlocked(wire_rx_cdr_pll2_freqlocked),
.inclk({rx_cruclk_in[29:20]}),
.locked(wire_rx_cdr_pll2_locked),
.locktorefclk(rx_pma_locktorefout[2]),
.pfdfbclkout(),
.pfdrefclkout(wire_rx_cdr_pll2_pfdrefclkout),
.powerdown(cent_unit_rxcrupowerdn[2]),
.rateswitch(int_hipautospdrateswitchout[2]),
.vcobypassout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.extra10gin({6{1'b0}}),
.pfdfbclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
rx_cdr_pll2.bandwidth_type = "Auto",
rx_cdr_pll2.channel_num = ((starting_channel_number + 2) % 4),
rx_cdr_pll2.dprio_config_mode = 6'h00,
rx_cdr_pll2.effective_data_rate = "5000 Mbps",
rx_cdr_pll2.enable_dynamic_divider = "true",
rx_cdr_pll2.fast_lock_control = "false",
rx_cdr_pll2.inclk0_input_period = 10000,
rx_cdr_pll2.input_clock_frequency = "100.0 MHz",
rx_cdr_pll2.m = 25,
rx_cdr_pll2.n = 1,
rx_cdr_pll2.pfd_clk_select = 0,
rx_cdr_pll2.pll_type = "RX CDR",
rx_cdr_pll2.use_refclk_pin = "false",
rx_cdr_pll2.vco_post_scale = 1,
rx_cdr_pll2.lpm_type = "stratixiv_hssi_pll";
stratixiv_hssi_pll rx_cdr_pll3
(
.areset(rx_rxcruresetout[3]),
.clk(wire_rx_cdr_pll3_clk),
.datain(rx_pma_dataout[3]),
.dataout(wire_rx_cdr_pll3_dataout),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rxpll_dprioin[1199:900]),
.dprioout(wire_rx_cdr_pll3_dprioout),
.earlyeios(int_rxpcs_cdrctrlearlyeios[3]),
.freqlocked(wire_rx_cdr_pll3_freqlocked),
.inclk({rx_cruclk_in[39:30]}),
.locked(wire_rx_cdr_pll3_locked),
.locktorefclk(rx_pma_locktorefout[3]),
.pfdfbclkout(),
.pfdrefclkout(wire_rx_cdr_pll3_pfdrefclkout),
.powerdown(cent_unit_rxcrupowerdn[3]),
.rateswitch(int_hipautospdrateswitchout[3]),
.vcobypassout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.extra10gin({6{1'b0}}),
.pfdfbclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
rx_cdr_pll3.bandwidth_type = "Auto",
rx_cdr_pll3.channel_num = ((starting_channel_number + 3) % 4),
rx_cdr_pll3.dprio_config_mode = 6'h00,
rx_cdr_pll3.effective_data_rate = "5000 Mbps",
rx_cdr_pll3.enable_dynamic_divider = "true",
rx_cdr_pll3.fast_lock_control = "false",
rx_cdr_pll3.inclk0_input_period = 10000,
rx_cdr_pll3.input_clock_frequency = "100.0 MHz",
rx_cdr_pll3.m = 25,
rx_cdr_pll3.n = 1,
rx_cdr_pll3.pfd_clk_select = 0,
rx_cdr_pll3.pll_type = "RX CDR",
rx_cdr_pll3.use_refclk_pin = "false",
rx_cdr_pll3.vco_post_scale = 1,
rx_cdr_pll3.lpm_type = "stratixiv_hssi_pll";
stratixiv_hssi_pll rx_cdr_pll4
(
.areset(rx_rxcruresetout[6]),
.clk(wire_rx_cdr_pll4_clk),
.datain(rx_pma_dataout[4]),
.dataout(wire_rx_cdr_pll4_dataout),
.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
.dprioin(rxpll_dprioin[2099:1800]),
.dprioout(wire_rx_cdr_pll4_dprioout),
.earlyeios(int_rxpcs_cdrctrlearlyeios[4]),
.freqlocked(wire_rx_cdr_pll4_freqlocked),
.inclk({rx_cruclk_in[49:40]}),
.locked(wire_rx_cdr_pll4_locked),
.locktorefclk(rx_pma_locktorefout[4]),
.pfdfbclkout(),
.pfdrefclkout(wire_rx_cdr_pll4_pfdrefclkout),
.powerdown(cent_unit_rxcrupowerdn[6]),
.rateswitch(int_hipautospdrateswitchout[4]),
.vcobypassout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.extra10gin({6{1'b0}}),
.pfdfbclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
rx_cdr_pll4.bandwidth_type = "Auto",
rx_cdr_pll4.channel_num = ((starting_channel_number + 4) % 4),
rx_cdr_pll4.dprio_config_mode = 6'h00,
rx_cdr_pll4.effective_data_rate = "5000 Mbps",
rx_cdr_pll4.enable_dynamic_divider = "true",
rx_cdr_pll4.fast_lock_control = "false",
rx_cdr_pll4.inclk0_input_period = 10000,
rx_cdr_pll4.input_clock_frequency = "100.0 MHz",
rx_cdr_pll4.m = 25,
rx_cdr_pll4.n = 1,
rx_cdr_pll4.pfd_clk_select = 0,
rx_cdr_pll4.pll_type = "RX CDR",
rx_cdr_pll4.use_refclk_pin = "false",
rx_cdr_pll4.vco_post_scale = 1,
rx_cdr_pll4.lpm_type = "stratixiv_hssi_pll";
stratixiv_hssi_pll rx_cdr_pll5
(
.areset(rx_rxcruresetout[7]),
.clk(wire_rx_cdr_pll5_clk),
.datain(rx_pma_dataout[5]),
.dataout(wire_rx_cdr_pll5_dataout),
.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
.dprioin(rxpll_dprioin[2399:2100]),
.dprioout(wire_rx_cdr_pll5_dprioout),
.earlyeios(int_rxpcs_cdrctrlearlyeios[5]),
.freqlocked(wire_rx_cdr_pll5_freqlocked),
.inclk({rx_cruclk_in[59:50]}),
.locked(wire_rx_cdr_pll5_locked),
.locktorefclk(rx_pma_locktorefout[5]),
.pfdfbclkout(),
.pfdrefclkout(wire_rx_cdr_pll5_pfdrefclkout),
.powerdown(cent_unit_rxcrupowerdn[7]),
.rateswitch(int_hipautospdrateswitchout[5]),
.vcobypassout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.extra10gin({6{1'b0}}),
.pfdfbclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
rx_cdr_pll5.bandwidth_type = "Auto",
rx_cdr_pll5.channel_num = ((starting_channel_number + 5) % 4),
rx_cdr_pll5.dprio_config_mode = 6'h00,
rx_cdr_pll5.effective_data_rate = "5000 Mbps",
rx_cdr_pll5.enable_dynamic_divider = "true",
rx_cdr_pll5.fast_lock_control = "false",
rx_cdr_pll5.inclk0_input_period = 10000,
rx_cdr_pll5.input_clock_frequency = "100.0 MHz",
rx_cdr_pll5.m = 25,
rx_cdr_pll5.n = 1,
rx_cdr_pll5.pfd_clk_select = 0,
rx_cdr_pll5.pll_type = "RX CDR",
rx_cdr_pll5.use_refclk_pin = "false",
rx_cdr_pll5.vco_post_scale = 1,
rx_cdr_pll5.lpm_type = "stratixiv_hssi_pll";
stratixiv_hssi_pll rx_cdr_pll6
(
.areset(rx_rxcruresetout[8]),
.clk(wire_rx_cdr_pll6_clk),
.datain(rx_pma_dataout[6]),
.dataout(wire_rx_cdr_pll6_dataout),
.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
.dprioin(rxpll_dprioin[2699:2400]),
.dprioout(wire_rx_cdr_pll6_dprioout),
.earlyeios(int_rxpcs_cdrctrlearlyeios[6]),
.freqlocked(wire_rx_cdr_pll6_freqlocked),
.inclk({rx_cruclk_in[69:60]}),
.locked(wire_rx_cdr_pll6_locked),
.locktorefclk(rx_pma_locktorefout[6]),
.pfdfbclkout(),
.pfdrefclkout(wire_rx_cdr_pll6_pfdrefclkout),
.powerdown(cent_unit_rxcrupowerdn[8]),
.rateswitch(int_hipautospdrateswitchout[6]),
.vcobypassout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.extra10gin({6{1'b0}}),
.pfdfbclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
rx_cdr_pll6.bandwidth_type = "Auto",
rx_cdr_pll6.channel_num = ((starting_channel_number + 6) % 4),
rx_cdr_pll6.dprio_config_mode = 6'h00,
rx_cdr_pll6.effective_data_rate = "5000 Mbps",
rx_cdr_pll6.enable_dynamic_divider = "true",
rx_cdr_pll6.fast_lock_control = "false",
rx_cdr_pll6.inclk0_input_period = 10000,
rx_cdr_pll6.input_clock_frequency = "100.0 MHz",
rx_cdr_pll6.m = 25,
rx_cdr_pll6.n = 1,
rx_cdr_pll6.pfd_clk_select = 0,
rx_cdr_pll6.pll_type = "RX CDR",
rx_cdr_pll6.use_refclk_pin = "false",
rx_cdr_pll6.vco_post_scale = 1,
rx_cdr_pll6.lpm_type = "stratixiv_hssi_pll";
stratixiv_hssi_pll rx_cdr_pll7
(
.areset(rx_rxcruresetout[9]),
.clk(wire_rx_cdr_pll7_clk),
.datain(rx_pma_dataout[7]),
.dataout(wire_rx_cdr_pll7_dataout),
.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
.dprioin(rxpll_dprioin[2999:2700]),
.dprioout(wire_rx_cdr_pll7_dprioout),
.earlyeios(int_rxpcs_cdrctrlearlyeios[7]),
.freqlocked(wire_rx_cdr_pll7_freqlocked),
.inclk({rx_cruclk_in[79:70]}),
.locked(wire_rx_cdr_pll7_locked),
.locktorefclk(rx_pma_locktorefout[7]),
.pfdfbclkout(),
.pfdrefclkout(wire_rx_cdr_pll7_pfdrefclkout),
.powerdown(cent_unit_rxcrupowerdn[9]),
.rateswitch(int_hipautospdrateswitchout[7]),
.vcobypassout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.extra10gin({6{1'b0}}),
.pfdfbclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
rx_cdr_pll7.bandwidth_type = "Auto",
rx_cdr_pll7.channel_num = ((starting_channel_number + 7) % 4),
rx_cdr_pll7.dprio_config_mode = 6'h00,
rx_cdr_pll7.effective_data_rate = "5000 Mbps",
rx_cdr_pll7.enable_dynamic_divider = "true",
rx_cdr_pll7.fast_lock_control = "false",
rx_cdr_pll7.inclk0_input_period = 10000,
rx_cdr_pll7.input_clock_frequency = "100.0 MHz",
rx_cdr_pll7.m = 25,
rx_cdr_pll7.n = 1,
rx_cdr_pll7.pfd_clk_select = 0,
rx_cdr_pll7.pll_type = "RX CDR",
rx_cdr_pll7.use_refclk_pin = "false",
rx_cdr_pll7.vco_post_scale = 1,
rx_cdr_pll7.lpm_type = "stratixiv_hssi_pll";
stratixiv_hssi_pll tx_pll0
(
.areset(pllreset_in[0]),
.clk(wire_tx_pll0_clk),
.dataout(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(pll0_dprioin[299:0]),
.dprioout(wire_tx_pll0_dprioout),
.freqlocked(),
.inclk({pll0_clkin[9:0]}),
.locked(wire_tx_pll0_locked),
.pfdfbclkout(),
.pfdrefclkout(),
.powerdown(pllpowerdn_in[0]),
.vcobypassout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.datain(1'b0),
.earlyeios(1'b0),
.extra10gin({6{1'b0}}),
.locktorefclk(1'b1),
.pfdfbclk(1'b0),
.rateswitch(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
tx_pll0.bandwidth_type = "High",
tx_pll0.channel_num = 4,
tx_pll0.dprio_config_mode = 6'h00,
tx_pll0.inclk0_input_period = 10000,
tx_pll0.input_clock_frequency = "100.0 MHz",
tx_pll0.logical_tx_pll_number = 0,
tx_pll0.m = 25,
tx_pll0.n = 1,
tx_pll0.pfd_clk_select = 0,
tx_pll0.pfd_fb_select = "internal",
tx_pll0.pll_type = "CMU",
tx_pll0.use_refclk_pin = "false",
tx_pll0.vco_post_scale = 1,
tx_pll0.lpm_type = "stratixiv_hssi_pll";
stratixiv_hssi_rx_pcs receive_pcs0
(
.a1a2size(1'b0),
.a1a2sizeout(),
.a1detect(),
.a2detect(),
.adetectdeskew(),
.alignstatus(1'b0),
.alignstatussync(1'b0),
.alignstatussyncout(),
.autospdrateswitchout(wire_receive_pcs0_autospdrateswitchout),
.autospdspdchgout(wire_receive_pcs0_autospdspdchgout),
.autospdxnconfigsel(int_rx_autospdxnconfigsel[2:0]),
.autospdxnspdchg(int_rx_autospdxnspdchg[2:0]),
.bistdone(),
.bisterr(),
.bitslipboundaryselectout(),
.byteorderalignstatus(),
.cdrctrlearlyeios(wire_receive_pcs0_cdrctrlearlyeios),
.cdrctrllocktorefclkout(wire_receive_pcs0_cdrctrllocktorefclkout),
.clkout(),
.coreclk(rx_coreclk_in[0]),
.coreclkout(wire_receive_pcs0_coreclkout),
.ctrldetect(wire_receive_pcs0_ctrldetect),
.datain(rx_pma_recoverdataout_wire[19:0]),
.dataout(wire_receive_pcs0_dataout),
.dataoutfull(),
.digitalreset(rx_digitalreset_out[0]),
.digitaltestout(),
.disablefifordin(1'b0),
.disablefifordout(),
.disablefifowrin(1'b0),
.disablefifowrout(),
.disperr(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pcsdprioin_wire[399:0]),
.dprioout(wire_receive_pcs0_dprioout),
.elecidleinfersel({3{1'b0}}),
.enabledeskew(1'b0),
.enabyteord(1'b0),
.enapatternalign(rx_enapatternalign[0]),
.errdetect(),
.fifordin(1'b0),
.fifordout(),
.fiforesetrd(1'b0),
.grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[2:0]),
.hipdataout(),
.hipdatavalid(),
.hipelecidle(),
.hipphydonestatus(),
.hipstatus(),
.invpol(1'b0),
.iqpautospdxnspgchg(int_rx_iqpautospdxnspgchg[1:0]),
.iqpphfifobyteselout(wire_receive_pcs0_iqpphfifobyteselout),
.iqpphfifoptrsresetout(wire_receive_pcs0_iqpphfifoptrsresetout),
.iqpphfifordenableout(wire_receive_pcs0_iqpphfifordenableout),
.iqpphfifowrclkout(wire_receive_pcs0_iqpphfifowrclkout),
.iqpphfifowrenableout(wire_receive_pcs0_iqpphfifowrenableout),
.iqpphfifoxnbytesel(int_rx_iqpphfifoxnbytesel[1:0]),
.iqpphfifoxnptrsreset(int_rx_iqpphfifoxnptrsreset[1:0]),
.iqpphfifoxnrdenable(int_rx_iqpphfifoxnrdenable[1:0]),
.iqpphfifoxnwrclk(int_rx_iqpphfifoxnwrclk[1:0]),
.iqpphfifoxnwrenable(int_rx_iqpphfifoxnwrenable[1:0]),
.k1detect(),
.k2detect(),
.localrefclk(1'b0),
.masterclk(1'b0),
.parallelfdbk({20{1'b0}}),
.patterndetect(wire_receive_pcs0_patterndetect),
.phfifobyteselout(),
.phfifobyteserdisableout(wire_receive_pcs0_phfifobyteserdisableout),
.phfifooverflow(),
.phfifoptrsresetout(wire_receive_pcs0_phfifoptrsresetout),
.phfifordenable(rx_phfifordenable[0]),
.phfifordenableout(wire_receive_pcs0_phfifordenableout),
.phfiforeset(rx_phfiforeset[0]),
.phfiforesetout(wire_receive_pcs0_phfiforesetout),
.phfifounderflow(),
.phfifowrclkout(),
.phfifowrdisable(rx_phfifowrdisable[0]),
.phfifowrdisableout(wire_receive_pcs0_phfifowrdisableout),
.phfifowrenableout(),
.phfifoxnbytesel(int_rx_phfifoxnbytesel[2:0]),
.phfifoxnptrsreset(int_rx_phfifioxnptrsreset[2:0]),
.phfifoxnrdenable(int_rx_phfifoxnrdenable[2:0]),
.phfifoxnwrclk(int_rx_phfifoxnwrclk[2:0]),
.phfifoxnwrenable(int_rx_phfifoxnwrenable[2:0]),
.pipe8b10binvpolarity(pipe8b10binvpolarity[0]),
.pipebufferstat(),
.pipedatavalid(wire_receive_pcs0_pipedatavalid),
.pipeelecidle(wire_receive_pcs0_pipeelecidle),
.pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[0]),
.pipephydonestatus(wire_receive_pcs0_pipephydonestatus),
.pipepowerdown(tx_pipepowerdownout[1:0]),
.pipepowerstate(tx_pipepowerstateout[3:0]),
.pipestatetransdoneout(wire_receive_pcs0_pipestatetransdoneout),
.pipestatus(wire_receive_pcs0_pipestatus),
.powerdn(powerdn[1:0]),
.prbscidenable(rx_prbscidenable[0]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitch(rateswitch[0]),
.rateswitchout(wire_receive_pcs0_rateswitchout),
.rateswitchxndone(int_hiprateswtichdone[0]),
.rdalign(),
.recoveredclk(rx_pma_clockout[0]),
.refclk(refclk_pma[0]),
.revbitorderwa(1'b0),
.revbyteorderwa(1'b0),
.revparallelfdbkdata(wire_receive_pcs0_revparallelfdbkdata),
.rlv(),
.rmfifoalmostempty(),
.rmfifoalmostfull(),
.rmfifodatadeleted(),
.rmfifodatainserted(),
.rmfifoempty(),
.rmfifofull(),
.rmfifordena(1'b0),
.rmfiforeset(rx_rmfiforeset[0]),
.rmfifowrena(1'b0),
.runningdisp(),
.rxdetectvalid(tx_rxdetectvalidout[0]),
.rxfound(rx_pcs_rxfound_wire[1:0]),
.signaldetect(wire_receive_pcs0_signaldetect),
.signaldetected(rx_signaldetect_wire[0]),
.syncstatus(wire_receive_pcs0_syncstatus),
.syncstatusdeskew(),
.xauidelcondmetout(),
.xauififoovrout(),
.xauiinsertincompleteout(),
.xauilatencycompout(),
.xgmctrldet(),
.xgmctrlin(1'b0),
.xgmdatain({8{1'b0}}),
.xgmdataout(),
.xgmdatavalid(),
.xgmrunningdisp()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslip(1'b0),
.cdrctrllocktorefcl(1'b0),
.hip8b10binvpolarity(1'b0),
.hipelecidleinfersel({3{1'b0}}),
.hippowerdown({2{1'b0}}),
.hiprateswitch(1'b0),
.phfifox4bytesel(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrclk(1'b0),
.phfifox4wrenable(1'b0),
.phfifox8bytesel(1'b0),
.phfifox8rdenable(1'b0),
.phfifox8wrclk(1'b0),
.phfifox8wrenable(1'b0),
.pmatestbusin({8{1'b0}}),
.ppmdetectdividedclk(1'b0),
.ppmdetectrefclk(1'b0),
.rateswitchisdone(1'b0),
.rxelecidlerateswitch(1'b0),
.wareset(1'b0),
.xauidelcondmet(1'b0),
.xauififoovr(1'b0),
.xauiinsertincomplete(1'b0),
.xauilatencycomp(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pcs0.align_pattern = "0101111100",
receive_pcs0.align_pattern_length = 10,
receive_pcs0.align_to_deskew_pattern_pos_disp_only = "false",
receive_pcs0.allow_align_polarity_inversion = "false",
receive_pcs0.allow_pipe_polarity_inversion = "true",
receive_pcs0.auto_spd_deassert_ph_fifo_rst_count = 8,
receive_pcs0.auto_spd_phystatus_notify_count = 14,
receive_pcs0.auto_spd_self_switch_enable = "true",
receive_pcs0.bit_slip_enable = "false",
receive_pcs0.byte_order_double_data_mode_mask_enable = "false",
receive_pcs0.byte_order_invalid_code_or_run_disp_error = "true",
receive_pcs0.byte_order_mode = "none",
receive_pcs0.byte_order_pad_pattern = "0",
receive_pcs0.byte_order_pattern = "0",
receive_pcs0.byte_order_pld_ctrl_enable = "false",
receive_pcs0.cdrctrl_bypass_ppm_detector_cycle = 1000,
receive_pcs0.cdrctrl_cid_mode_enable = "true",
receive_pcs0.cdrctrl_enable = "true",
receive_pcs0.cdrctrl_rxvalid_mask = "true",
receive_pcs0.channel_bonding = "x8",
receive_pcs0.channel_number = ((starting_channel_number + 0) % 4),
receive_pcs0.channel_width = 16,
receive_pcs0.clk1_mux_select = "recovered clock",
receive_pcs0.clk2_mux_select = "digital reference clock",
receive_pcs0.core_clock_0ppm = "false",
receive_pcs0.datapath_low_latency_mode = "false",
receive_pcs0.datapath_protocol = "pipe",
receive_pcs0.dec_8b_10b_compatibility_mode = "true",
receive_pcs0.dec_8b_10b_mode = "normal",
receive_pcs0.dec_8b_10b_polarity_inv_enable = "true",
receive_pcs0.deskew_pattern = "0",
receive_pcs0.disable_auto_idle_insertion = "false",
receive_pcs0.disable_running_disp_in_word_align = "false",
receive_pcs0.disallow_kchar_after_pattern_ordered_set = "false",
receive_pcs0.dprio_config_mode = 6'h01,
receive_pcs0.elec_idle_gen1_sigdet_enable = "true",
receive_pcs0.elec_idle_infer_enable = "false",
receive_pcs0.elec_idle_num_com_detect = 3,
receive_pcs0.enable_bit_reversal = "false",
receive_pcs0.enable_deep_align = "false",
receive_pcs0.enable_deep_align_byte_swap = "false",
receive_pcs0.enable_self_test_mode = "false",
receive_pcs0.enable_true_complement_match_in_word_align = "false",
receive_pcs0.force_signal_detect_dig = "true",
receive_pcs0.hip_enable = "false",
receive_pcs0.infiniband_invalid_code = 0,
receive_pcs0.insert_pad_on_underflow = "false",
receive_pcs0.logical_channel_address = (starting_channel_number + 0),
receive_pcs0.num_align_code_groups_in_ordered_set = 0,
receive_pcs0.num_align_cons_good_data = 16,
receive_pcs0.num_align_cons_pat = 4,
receive_pcs0.num_align_loss_sync_error = 17,
receive_pcs0.ph_fifo_low_latency_enable = "true",
receive_pcs0.ph_fifo_reg_mode = "false",
receive_pcs0.ph_fifo_xn_mapping0 = "none",
receive_pcs0.ph_fifo_xn_mapping1 = "none",
receive_pcs0.ph_fifo_xn_mapping2 = "central",
receive_pcs0.ph_fifo_xn_select = 2,
receive_pcs0.pipe_auto_speed_nego_enable = "true",
receive_pcs0.pipe_freq_scale_mode = "Frequency",
receive_pcs0.pma_done_count = 249950,
receive_pcs0.protocol_hint = "pcie2",
receive_pcs0.rate_match_almost_empty_threshold = 11,
receive_pcs0.rate_match_almost_full_threshold = 13,
receive_pcs0.rate_match_back_to_back = "false",
receive_pcs0.rate_match_delete_threshold = 13,
receive_pcs0.rate_match_empty_threshold = 5,
receive_pcs0.rate_match_fifo_mode = "true",
receive_pcs0.rate_match_full_threshold = 20,
receive_pcs0.rate_match_insert_threshold = 11,
receive_pcs0.rate_match_ordered_set_based = "false",
receive_pcs0.rate_match_pattern1 = "11010000111010000011",
receive_pcs0.rate_match_pattern2 = "00101111000101111100",
receive_pcs0.rate_match_pattern_size = 20,
receive_pcs0.rate_match_pipe_enable = "true",
receive_pcs0.rate_match_reset_enable = "false",
receive_pcs0.rate_match_skip_set_based = "true",
receive_pcs0.rate_match_start_threshold = 7,
receive_pcs0.rd_clk_mux_select = "core clock",
receive_pcs0.recovered_clk_mux_select = "recovered clock",
receive_pcs0.run_length = 40,
receive_pcs0.run_length_enable = "true",
receive_pcs0.rx_detect_bypass = "false",
receive_pcs0.rx_phfifo_wait_cnt = 32,
receive_pcs0.rxstatus_error_report_mode = 1,
receive_pcs0.self_test_mode = "incremental",
receive_pcs0.use_alignment_state_machine = "true",
receive_pcs0.use_deserializer_double_data_mode = "false",
receive_pcs0.use_deskew_fifo = "false",
receive_pcs0.use_double_data_mode = "true",
receive_pcs0.use_parallel_loopback = "false",
receive_pcs0.use_rising_edge_triggered_pattern_align = "false",
receive_pcs0.lpm_type = "stratixiv_hssi_rx_pcs";
stratixiv_hssi_rx_pcs receive_pcs1
(
.a1a2size(1'b0),
.a1a2sizeout(),
.a1detect(),
.a2detect(),
.adetectdeskew(),
.alignstatus(1'b0),
.alignstatussync(1'b0),
.alignstatussyncout(),
.autospdrateswitchout(wire_receive_pcs1_autospdrateswitchout),
.autospdspdchgout(wire_receive_pcs1_autospdspdchgout),
.autospdxnconfigsel(int_rx_autospdxnconfigsel[5:3]),
.autospdxnspdchg(int_rx_autospdxnspdchg[5:3]),
.bistdone(),
.bisterr(),
.bitslipboundaryselectout(),
.byteorderalignstatus(),
.cdrctrlearlyeios(wire_receive_pcs1_cdrctrlearlyeios),
.cdrctrllocktorefclkout(wire_receive_pcs1_cdrctrllocktorefclkout),
.clkout(),
.coreclk(rx_coreclk_in[1]),
.coreclkout(wire_receive_pcs1_coreclkout),
.ctrldetect(wire_receive_pcs1_ctrldetect),
.datain(rx_pma_recoverdataout_wire[39:20]),
.dataout(wire_receive_pcs1_dataout),
.dataoutfull(),
.digitalreset(rx_digitalreset_out[1]),
.digitaltestout(),
.disablefifordin(1'b0),
.disablefifordout(),
.disablefifowrin(1'b0),
.disablefifowrout(),
.disperr(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pcsdprioin_wire[799:400]),
.dprioout(wire_receive_pcs1_dprioout),
.elecidleinfersel({3{1'b0}}),
.enabledeskew(1'b0),
.enabyteord(1'b0),
.enapatternalign(rx_enapatternalign[1]),
.errdetect(),
.fifordin(1'b0),
.fifordout(),
.fiforesetrd(1'b0),
.grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[5:3]),
.hipdataout(),
.hipdatavalid(),
.hipelecidle(),
.hipphydonestatus(),
.hipstatus(),
.invpol(1'b0),
.iqpautospdxnspgchg(int_rx_iqpautospdxnspgchg[3:2]),
.iqpphfifobyteselout(wire_receive_pcs1_iqpphfifobyteselout),
.iqpphfifoptrsresetout(wire_receive_pcs1_iqpphfifoptrsresetout),
.iqpphfifordenableout(wire_receive_pcs1_iqpphfifordenableout),
.iqpphfifowrclkout(wire_receive_pcs1_iqpphfifowrclkout),
.iqpphfifowrenableout(wire_receive_pcs1_iqpphfifowrenableout),
.iqpphfifoxnbytesel(int_rx_iqpphfifoxnbytesel[3:2]),
.iqpphfifoxnptrsreset(int_rx_iqpphfifoxnptrsreset[3:2]),
.iqpphfifoxnrdenable(int_rx_iqpphfifoxnrdenable[3:2]),
.iqpphfifoxnwrclk(int_rx_iqpphfifoxnwrclk[3:2]),
.iqpphfifoxnwrenable(int_rx_iqpphfifoxnwrenable[3:2]),
.k1detect(),
.k2detect(),
.localrefclk(1'b0),
.masterclk(1'b0),
.parallelfdbk({20{1'b0}}),
.patterndetect(wire_receive_pcs1_patterndetect),
.phfifobyteselout(),
.phfifobyteserdisableout(wire_receive_pcs1_phfifobyteserdisableout),
.phfifooverflow(),
.phfifoptrsresetout(wire_receive_pcs1_phfifoptrsresetout),
.phfifordenable(rx_phfifordenable[1]),
.phfifordenableout(wire_receive_pcs1_phfifordenableout),
.phfiforeset(rx_phfiforeset[1]),
.phfiforesetout(wire_receive_pcs1_phfiforesetout),
.phfifounderflow(),
.phfifowrclkout(),
.phfifowrdisable(rx_phfifowrdisable[1]),
.phfifowrdisableout(wire_receive_pcs1_phfifowrdisableout),
.phfifowrenableout(),
.phfifoxnbytesel(int_rx_phfifoxnbytesel[5:3]),
.phfifoxnptrsreset(int_rx_phfifioxnptrsreset[5:3]),
.phfifoxnrdenable(int_rx_phfifoxnrdenable[5:3]),
.phfifoxnwrclk(int_rx_phfifoxnwrclk[5:3]),
.phfifoxnwrenable(int_rx_phfifoxnwrenable[5:3]),
.pipe8b10binvpolarity(pipe8b10binvpolarity[1]),
.pipebufferstat(),
.pipedatavalid(wire_receive_pcs1_pipedatavalid),
.pipeelecidle(wire_receive_pcs1_pipeelecidle),
.pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[1]),
.pipephydonestatus(wire_receive_pcs1_pipephydonestatus),
.pipepowerdown(tx_pipepowerdownout[3:2]),
.pipepowerstate(tx_pipepowerstateout[7:4]),
.pipestatetransdoneout(wire_receive_pcs1_pipestatetransdoneout),
.pipestatus(wire_receive_pcs1_pipestatus),
.powerdn(powerdn[3:2]),
.prbscidenable(rx_prbscidenable[1]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitch(rateswitch[0]),
.rateswitchout(wire_receive_pcs1_rateswitchout),
.rateswitchxndone(int_hiprateswtichdone[0]),
.rdalign(),
.recoveredclk(rx_pma_clockout[1]),
.refclk(refclk_pma[0]),
.revbitorderwa(1'b0),
.revbyteorderwa(1'b0),
.revparallelfdbkdata(wire_receive_pcs1_revparallelfdbkdata),
.rlv(),
.rmfifoalmostempty(),
.rmfifoalmostfull(),
.rmfifodatadeleted(),
.rmfifodatainserted(),
.rmfifoempty(),
.rmfifofull(),
.rmfifordena(1'b0),
.rmfiforeset(rx_rmfiforeset[1]),
.rmfifowrena(1'b0),
.runningdisp(),
.rxdetectvalid(tx_rxdetectvalidout[1]),
.rxfound(rx_pcs_rxfound_wire[3:2]),
.signaldetect(wire_receive_pcs1_signaldetect),
.signaldetected(rx_signaldetect_wire[1]),
.syncstatus(wire_receive_pcs1_syncstatus),
.syncstatusdeskew(),
.xauidelcondmetout(),
.xauififoovrout(),
.xauiinsertincompleteout(),
.xauilatencycompout(),
.xgmctrldet(),
.xgmctrlin(1'b0),
.xgmdatain({8{1'b0}}),
.xgmdataout(),
.xgmdatavalid(),
.xgmrunningdisp()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslip(1'b0),
.cdrctrllocktorefcl(1'b0),
.hip8b10binvpolarity(1'b0),
.hipelecidleinfersel({3{1'b0}}),
.hippowerdown({2{1'b0}}),
.hiprateswitch(1'b0),
.phfifox4bytesel(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrclk(1'b0),
.phfifox4wrenable(1'b0),
.phfifox8bytesel(1'b0),
.phfifox8rdenable(1'b0),
.phfifox8wrclk(1'b0),
.phfifox8wrenable(1'b0),
.pmatestbusin({8{1'b0}}),
.ppmdetectdividedclk(1'b0),
.ppmdetectrefclk(1'b0),
.rateswitchisdone(1'b0),
.rxelecidlerateswitch(1'b0),
.wareset(1'b0),
.xauidelcondmet(1'b0),
.xauififoovr(1'b0),
.xauiinsertincomplete(1'b0),
.xauilatencycomp(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pcs1.align_pattern = "0101111100",
receive_pcs1.align_pattern_length = 10,
receive_pcs1.align_to_deskew_pattern_pos_disp_only = "false",
receive_pcs1.allow_align_polarity_inversion = "false",
receive_pcs1.allow_pipe_polarity_inversion = "true",
receive_pcs1.auto_spd_deassert_ph_fifo_rst_count = 8,
receive_pcs1.auto_spd_phystatus_notify_count = 14,
receive_pcs1.auto_spd_self_switch_enable = "true",
receive_pcs1.bit_slip_enable = "false",
receive_pcs1.byte_order_double_data_mode_mask_enable = "false",
receive_pcs1.byte_order_invalid_code_or_run_disp_error = "true",
receive_pcs1.byte_order_mode = "none",
receive_pcs1.byte_order_pad_pattern = "0",
receive_pcs1.byte_order_pattern = "0",
receive_pcs1.byte_order_pld_ctrl_enable = "false",
receive_pcs1.cdrctrl_bypass_ppm_detector_cycle = 1000,
receive_pcs1.cdrctrl_cid_mode_enable = "true",
receive_pcs1.cdrctrl_enable = "true",
receive_pcs1.cdrctrl_rxvalid_mask = "true",
receive_pcs1.channel_bonding = "x8",
receive_pcs1.channel_number = ((starting_channel_number + 1) % 4),
receive_pcs1.channel_width = 16,
receive_pcs1.clk1_mux_select = "recovered clock",
receive_pcs1.clk2_mux_select = "digital reference clock",
receive_pcs1.core_clock_0ppm = "false",
receive_pcs1.datapath_low_latency_mode = "false",
receive_pcs1.datapath_protocol = "pipe",
receive_pcs1.dec_8b_10b_compatibility_mode = "true",
receive_pcs1.dec_8b_10b_mode = "normal",
receive_pcs1.dec_8b_10b_polarity_inv_enable = "true",
receive_pcs1.deskew_pattern = "0",
receive_pcs1.disable_auto_idle_insertion = "false",
receive_pcs1.disable_running_disp_in_word_align = "false",
receive_pcs1.disallow_kchar_after_pattern_ordered_set = "false",
receive_pcs1.dprio_config_mode = 6'h01,
receive_pcs1.elec_idle_gen1_sigdet_enable = "true",
receive_pcs1.elec_idle_infer_enable = "false",
receive_pcs1.elec_idle_num_com_detect = 3,
receive_pcs1.enable_bit_reversal = "false",
receive_pcs1.enable_deep_align = "false",
receive_pcs1.enable_deep_align_byte_swap = "false",
receive_pcs1.enable_self_test_mode = "false",
receive_pcs1.enable_true_complement_match_in_word_align = "false",
receive_pcs1.force_signal_detect_dig = "true",
receive_pcs1.hip_enable = "false",
receive_pcs1.infiniband_invalid_code = 0,
receive_pcs1.insert_pad_on_underflow = "false",
receive_pcs1.logical_channel_address = (starting_channel_number + 1),
receive_pcs1.num_align_code_groups_in_ordered_set = 0,
receive_pcs1.num_align_cons_good_data = 16,
receive_pcs1.num_align_cons_pat = 4,
receive_pcs1.num_align_loss_sync_error = 17,
receive_pcs1.ph_fifo_low_latency_enable = "true",
receive_pcs1.ph_fifo_reg_mode = "false",
receive_pcs1.ph_fifo_xn_mapping0 = "none",
receive_pcs1.ph_fifo_xn_mapping1 = "none",
receive_pcs1.ph_fifo_xn_mapping2 = "central",
receive_pcs1.ph_fifo_xn_select = 2,
receive_pcs1.pipe_auto_speed_nego_enable = "true",
receive_pcs1.pipe_freq_scale_mode = "Frequency",
receive_pcs1.pma_done_count = 249950,
receive_pcs1.protocol_hint = "pcie2",
receive_pcs1.rate_match_almost_empty_threshold = 11,
receive_pcs1.rate_match_almost_full_threshold = 13,
receive_pcs1.rate_match_back_to_back = "false",
receive_pcs1.rate_match_delete_threshold = 13,
receive_pcs1.rate_match_empty_threshold = 5,
receive_pcs1.rate_match_fifo_mode = "true",
receive_pcs1.rate_match_full_threshold = 20,
receive_pcs1.rate_match_insert_threshold = 11,
receive_pcs1.rate_match_ordered_set_based = "false",
receive_pcs1.rate_match_pattern1 = "11010000111010000011",
receive_pcs1.rate_match_pattern2 = "00101111000101111100",
receive_pcs1.rate_match_pattern_size = 20,
receive_pcs1.rate_match_pipe_enable = "true",
receive_pcs1.rate_match_reset_enable = "false",
receive_pcs1.rate_match_skip_set_based = "true",
receive_pcs1.rate_match_start_threshold = 7,
receive_pcs1.rd_clk_mux_select = "core clock",
receive_pcs1.recovered_clk_mux_select = "recovered clock",
receive_pcs1.run_length = 40,
receive_pcs1.run_length_enable = "true",
receive_pcs1.rx_detect_bypass = "false",
receive_pcs1.rx_phfifo_wait_cnt = 32,
receive_pcs1.rxstatus_error_report_mode = 1,
receive_pcs1.self_test_mode = "incremental",
receive_pcs1.use_alignment_state_machine = "true",
receive_pcs1.use_deserializer_double_data_mode = "false",
receive_pcs1.use_deskew_fifo = "false",
receive_pcs1.use_double_data_mode = "true",
receive_pcs1.use_parallel_loopback = "false",
receive_pcs1.use_rising_edge_triggered_pattern_align = "false",
receive_pcs1.lpm_type = "stratixiv_hssi_rx_pcs";
stratixiv_hssi_rx_pcs receive_pcs2
(
.a1a2size(1'b0),
.a1a2sizeout(),
.a1detect(),
.a2detect(),
.adetectdeskew(),
.alignstatus(1'b0),
.alignstatussync(1'b0),
.alignstatussyncout(),
.autospdrateswitchout(wire_receive_pcs2_autospdrateswitchout),
.autospdspdchgout(wire_receive_pcs2_autospdspdchgout),
.autospdxnconfigsel(int_rx_autospdxnconfigsel[8:6]),
.autospdxnspdchg(int_rx_autospdxnspdchg[8:6]),
.bistdone(),
.bisterr(),
.bitslipboundaryselectout(),
.byteorderalignstatus(),
.cdrctrlearlyeios(wire_receive_pcs2_cdrctrlearlyeios),
.cdrctrllocktorefclkout(wire_receive_pcs2_cdrctrllocktorefclkout),
.clkout(),
.coreclk(rx_coreclk_in[2]),
.coreclkout(wire_receive_pcs2_coreclkout),
.ctrldetect(wire_receive_pcs2_ctrldetect),
.datain(rx_pma_recoverdataout_wire[59:40]),
.dataout(wire_receive_pcs2_dataout),
.dataoutfull(),
.digitalreset(rx_digitalreset_out[2]),
.digitaltestout(),
.disablefifordin(1'b0),
.disablefifordout(),
.disablefifowrin(1'b0),
.disablefifowrout(),
.disperr(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pcsdprioin_wire[1199:800]),
.dprioout(wire_receive_pcs2_dprioout),
.elecidleinfersel({3{1'b0}}),
.enabledeskew(1'b0),
.enabyteord(1'b0),
.enapatternalign(rx_enapatternalign[2]),
.errdetect(),
.fifordin(1'b0),
.fifordout(),
.fiforesetrd(1'b0),
.grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[8:6]),
.hipdataout(),
.hipdatavalid(),
.hipelecidle(),
.hipphydonestatus(),
.hipstatus(),
.invpol(1'b0),
.iqpautospdxnspgchg(int_rx_iqpautospdxnspgchg[5:4]),
.iqpphfifobyteselout(wire_receive_pcs2_iqpphfifobyteselout),
.iqpphfifoptrsresetout(wire_receive_pcs2_iqpphfifoptrsresetout),
.iqpphfifordenableout(wire_receive_pcs2_iqpphfifordenableout),
.iqpphfifowrclkout(wire_receive_pcs2_iqpphfifowrclkout),
.iqpphfifowrenableout(wire_receive_pcs2_iqpphfifowrenableout),
.iqpphfifoxnbytesel(int_rx_iqpphfifoxnbytesel[5:4]),
.iqpphfifoxnptrsreset(int_rx_iqpphfifoxnptrsreset[5:4]),
.iqpphfifoxnrdenable(int_rx_iqpphfifoxnrdenable[5:4]),
.iqpphfifoxnwrclk(int_rx_iqpphfifoxnwrclk[5:4]),
.iqpphfifoxnwrenable(int_rx_iqpphfifoxnwrenable[5:4]),
.k1detect(),
.k2detect(),
.localrefclk(1'b0),
.masterclk(1'b0),
.parallelfdbk({20{1'b0}}),
.patterndetect(wire_receive_pcs2_patterndetect),
.phfifobyteselout(),
.phfifobyteserdisableout(wire_receive_pcs2_phfifobyteserdisableout),
.phfifooverflow(),
.phfifoptrsresetout(wire_receive_pcs2_phfifoptrsresetout),
.phfifordenable(rx_phfifordenable[2]),
.phfifordenableout(wire_receive_pcs2_phfifordenableout),
.phfiforeset(rx_phfiforeset[2]),
.phfiforesetout(wire_receive_pcs2_phfiforesetout),
.phfifounderflow(),
.phfifowrclkout(),
.phfifowrdisable(rx_phfifowrdisable[2]),
.phfifowrdisableout(wire_receive_pcs2_phfifowrdisableout),
.phfifowrenableout(),
.phfifoxnbytesel(int_rx_phfifoxnbytesel[8:6]),
.phfifoxnptrsreset(int_rx_phfifioxnptrsreset[8:6]),
.phfifoxnrdenable(int_rx_phfifoxnrdenable[8:6]),
.phfifoxnwrclk(int_rx_phfifoxnwrclk[8:6]),
.phfifoxnwrenable(int_rx_phfifoxnwrenable[8:6]),
.pipe8b10binvpolarity(pipe8b10binvpolarity[2]),
.pipebufferstat(),
.pipedatavalid(wire_receive_pcs2_pipedatavalid),
.pipeelecidle(wire_receive_pcs2_pipeelecidle),
.pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[2]),
.pipephydonestatus(wire_receive_pcs2_pipephydonestatus),
.pipepowerdown(tx_pipepowerdownout[5:4]),
.pipepowerstate(tx_pipepowerstateout[11:8]),
.pipestatetransdoneout(wire_receive_pcs2_pipestatetransdoneout),
.pipestatus(wire_receive_pcs2_pipestatus),
.powerdn(powerdn[5:4]),
.prbscidenable(rx_prbscidenable[2]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitch(rateswitch[0]),
.rateswitchout(wire_receive_pcs2_rateswitchout),
.rateswitchxndone(int_hiprateswtichdone[0]),
.rdalign(),
.recoveredclk(rx_pma_clockout[2]),
.refclk(refclk_pma[0]),
.revbitorderwa(1'b0),
.revbyteorderwa(1'b0),
.revparallelfdbkdata(wire_receive_pcs2_revparallelfdbkdata),
.rlv(),
.rmfifoalmostempty(),
.rmfifoalmostfull(),
.rmfifodatadeleted(),
.rmfifodatainserted(),
.rmfifoempty(),
.rmfifofull(),
.rmfifordena(1'b0),
.rmfiforeset(rx_rmfiforeset[2]),
.rmfifowrena(1'b0),
.runningdisp(),
.rxdetectvalid(tx_rxdetectvalidout[2]),
.rxfound(rx_pcs_rxfound_wire[5:4]),
.signaldetect(wire_receive_pcs2_signaldetect),
.signaldetected(rx_signaldetect_wire[2]),
.syncstatus(wire_receive_pcs2_syncstatus),
.syncstatusdeskew(),
.xauidelcondmetout(),
.xauififoovrout(),
.xauiinsertincompleteout(),
.xauilatencycompout(),
.xgmctrldet(),
.xgmctrlin(1'b0),
.xgmdatain({8{1'b0}}),
.xgmdataout(),
.xgmdatavalid(),
.xgmrunningdisp()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslip(1'b0),
.cdrctrllocktorefcl(1'b0),
.hip8b10binvpolarity(1'b0),
.hipelecidleinfersel({3{1'b0}}),
.hippowerdown({2{1'b0}}),
.hiprateswitch(1'b0),
.phfifox4bytesel(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrclk(1'b0),
.phfifox4wrenable(1'b0),
.phfifox8bytesel(1'b0),
.phfifox8rdenable(1'b0),
.phfifox8wrclk(1'b0),
.phfifox8wrenable(1'b0),
.pmatestbusin({8{1'b0}}),
.ppmdetectdividedclk(1'b0),
.ppmdetectrefclk(1'b0),
.rateswitchisdone(1'b0),
.rxelecidlerateswitch(1'b0),
.wareset(1'b0),
.xauidelcondmet(1'b0),
.xauififoovr(1'b0),
.xauiinsertincomplete(1'b0),
.xauilatencycomp(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pcs2.align_pattern = "0101111100",
receive_pcs2.align_pattern_length = 10,
receive_pcs2.align_to_deskew_pattern_pos_disp_only = "false",
receive_pcs2.allow_align_polarity_inversion = "false",
receive_pcs2.allow_pipe_polarity_inversion = "true",
receive_pcs2.auto_spd_deassert_ph_fifo_rst_count = 8,
receive_pcs2.auto_spd_phystatus_notify_count = 14,
receive_pcs2.auto_spd_self_switch_enable = "true",
receive_pcs2.bit_slip_enable = "false",
receive_pcs2.byte_order_double_data_mode_mask_enable = "false",
receive_pcs2.byte_order_invalid_code_or_run_disp_error = "true",
receive_pcs2.byte_order_mode = "none",
receive_pcs2.byte_order_pad_pattern = "0",
receive_pcs2.byte_order_pattern = "0",
receive_pcs2.byte_order_pld_ctrl_enable = "false",
receive_pcs2.cdrctrl_bypass_ppm_detector_cycle = 1000,
receive_pcs2.cdrctrl_cid_mode_enable = "true",
receive_pcs2.cdrctrl_enable = "true",
receive_pcs2.cdrctrl_rxvalid_mask = "true",
receive_pcs2.channel_bonding = "x8",
receive_pcs2.channel_number = ((starting_channel_number + 2) % 4),
receive_pcs2.channel_width = 16,
receive_pcs2.clk1_mux_select = "recovered clock",
receive_pcs2.clk2_mux_select = "digital reference clock",
receive_pcs2.core_clock_0ppm = "false",
receive_pcs2.datapath_low_latency_mode = "false",
receive_pcs2.datapath_protocol = "pipe",
receive_pcs2.dec_8b_10b_compatibility_mode = "true",
receive_pcs2.dec_8b_10b_mode = "normal",
receive_pcs2.dec_8b_10b_polarity_inv_enable = "true",
receive_pcs2.deskew_pattern = "0",
receive_pcs2.disable_auto_idle_insertion = "false",
receive_pcs2.disable_running_disp_in_word_align = "false",
receive_pcs2.disallow_kchar_after_pattern_ordered_set = "false",
receive_pcs2.dprio_config_mode = 6'h01,
receive_pcs2.elec_idle_gen1_sigdet_enable = "true",
receive_pcs2.elec_idle_infer_enable = "false",
receive_pcs2.elec_idle_num_com_detect = 3,
receive_pcs2.enable_bit_reversal = "false",
receive_pcs2.enable_deep_align = "false",
receive_pcs2.enable_deep_align_byte_swap = "false",
receive_pcs2.enable_self_test_mode = "false",
receive_pcs2.enable_true_complement_match_in_word_align = "false",
receive_pcs2.force_signal_detect_dig = "true",
receive_pcs2.hip_enable = "false",
receive_pcs2.infiniband_invalid_code = 0,
receive_pcs2.insert_pad_on_underflow = "false",
receive_pcs2.logical_channel_address = (starting_channel_number + 2),
receive_pcs2.num_align_code_groups_in_ordered_set = 0,
receive_pcs2.num_align_cons_good_data = 16,
receive_pcs2.num_align_cons_pat = 4,
receive_pcs2.num_align_loss_sync_error = 17,
receive_pcs2.ph_fifo_low_latency_enable = "true",
receive_pcs2.ph_fifo_reg_mode = "false",
receive_pcs2.ph_fifo_xn_mapping0 = "none",
receive_pcs2.ph_fifo_xn_mapping1 = "none",
receive_pcs2.ph_fifo_xn_mapping2 = "central",
receive_pcs2.ph_fifo_xn_select = 2,
receive_pcs2.pipe_auto_speed_nego_enable = "true",
receive_pcs2.pipe_freq_scale_mode = "Frequency",
receive_pcs2.pma_done_count = 249950,
receive_pcs2.protocol_hint = "pcie2",
receive_pcs2.rate_match_almost_empty_threshold = 11,
receive_pcs2.rate_match_almost_full_threshold = 13,
receive_pcs2.rate_match_back_to_back = "false",
receive_pcs2.rate_match_delete_threshold = 13,
receive_pcs2.rate_match_empty_threshold = 5,
receive_pcs2.rate_match_fifo_mode = "true",
receive_pcs2.rate_match_full_threshold = 20,
receive_pcs2.rate_match_insert_threshold = 11,
receive_pcs2.rate_match_ordered_set_based = "false",
receive_pcs2.rate_match_pattern1 = "11010000111010000011",
receive_pcs2.rate_match_pattern2 = "00101111000101111100",
receive_pcs2.rate_match_pattern_size = 20,
receive_pcs2.rate_match_pipe_enable = "true",
receive_pcs2.rate_match_reset_enable = "false",
receive_pcs2.rate_match_skip_set_based = "true",
receive_pcs2.rate_match_start_threshold = 7,
receive_pcs2.rd_clk_mux_select = "core clock",
receive_pcs2.recovered_clk_mux_select = "recovered clock",
receive_pcs2.run_length = 40,
receive_pcs2.run_length_enable = "true",
receive_pcs2.rx_detect_bypass = "false",
receive_pcs2.rx_phfifo_wait_cnt = 32,
receive_pcs2.rxstatus_error_report_mode = 1,
receive_pcs2.self_test_mode = "incremental",
receive_pcs2.use_alignment_state_machine = "true",
receive_pcs2.use_deserializer_double_data_mode = "false",
receive_pcs2.use_deskew_fifo = "false",
receive_pcs2.use_double_data_mode = "true",
receive_pcs2.use_parallel_loopback = "false",
receive_pcs2.use_rising_edge_triggered_pattern_align = "false",
receive_pcs2.lpm_type = "stratixiv_hssi_rx_pcs";
stratixiv_hssi_rx_pcs receive_pcs3
(
.a1a2size(1'b0),
.a1a2sizeout(),
.a1detect(),
.a2detect(),
.adetectdeskew(),
.alignstatus(1'b0),
.alignstatussync(1'b0),
.alignstatussyncout(),
.autospdrateswitchout(wire_receive_pcs3_autospdrateswitchout),
.autospdspdchgout(wire_receive_pcs3_autospdspdchgout),
.autospdxnconfigsel(int_rx_autospdxnconfigsel[11:9]),
.autospdxnspdchg(int_rx_autospdxnspdchg[11:9]),
.bistdone(),
.bisterr(),
.bitslipboundaryselectout(),
.byteorderalignstatus(),
.cdrctrlearlyeios(wire_receive_pcs3_cdrctrlearlyeios),
.cdrctrllocktorefclkout(wire_receive_pcs3_cdrctrllocktorefclkout),
.clkout(),
.coreclk(rx_coreclk_in[3]),
.coreclkout(wire_receive_pcs3_coreclkout),
.ctrldetect(wire_receive_pcs3_ctrldetect),
.datain(rx_pma_recoverdataout_wire[79:60]),
.dataout(wire_receive_pcs3_dataout),
.dataoutfull(),
.digitalreset(rx_digitalreset_out[3]),
.digitaltestout(),
.disablefifordin(1'b0),
.disablefifordout(),
.disablefifowrin(1'b0),
.disablefifowrout(),
.disperr(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pcsdprioin_wire[1599:1200]),
.dprioout(wire_receive_pcs3_dprioout),
.elecidleinfersel({3{1'b0}}),
.enabledeskew(1'b0),
.enabyteord(1'b0),
.enapatternalign(rx_enapatternalign[3]),
.errdetect(),
.fifordin(1'b0),
.fifordout(),
.fiforesetrd(1'b0),
.grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[11:9]),
.hipdataout(),
.hipdatavalid(),
.hipelecidle(),
.hipphydonestatus(),
.hipstatus(),
.invpol(1'b0),
.iqpautospdxnspgchg(int_rx_iqpautospdxnspgchg[7:6]),
.iqpphfifobyteselout(wire_receive_pcs3_iqpphfifobyteselout),
.iqpphfifoptrsresetout(wire_receive_pcs3_iqpphfifoptrsresetout),
.iqpphfifordenableout(wire_receive_pcs3_iqpphfifordenableout),
.iqpphfifowrclkout(wire_receive_pcs3_iqpphfifowrclkout),
.iqpphfifowrenableout(wire_receive_pcs3_iqpphfifowrenableout),
.iqpphfifoxnbytesel(int_rx_iqpphfifoxnbytesel[7:6]),
.iqpphfifoxnptrsreset(int_rx_iqpphfifoxnptrsreset[7:6]),
.iqpphfifoxnrdenable(int_rx_iqpphfifoxnrdenable[7:6]),
.iqpphfifoxnwrclk(int_rx_iqpphfifoxnwrclk[7:6]),
.iqpphfifoxnwrenable(int_rx_iqpphfifoxnwrenable[7:6]),
.k1detect(),
.k2detect(),
.localrefclk(1'b0),
.masterclk(1'b0),
.parallelfdbk({20{1'b0}}),
.patterndetect(wire_receive_pcs3_patterndetect),
.phfifobyteselout(),
.phfifobyteserdisableout(wire_receive_pcs3_phfifobyteserdisableout),
.phfifooverflow(),
.phfifoptrsresetout(wire_receive_pcs3_phfifoptrsresetout),
.phfifordenable(rx_phfifordenable[3]),
.phfifordenableout(wire_receive_pcs3_phfifordenableout),
.phfiforeset(rx_phfiforeset[3]),
.phfiforesetout(wire_receive_pcs3_phfiforesetout),
.phfifounderflow(),
.phfifowrclkout(),
.phfifowrdisable(rx_phfifowrdisable[3]),
.phfifowrdisableout(wire_receive_pcs3_phfifowrdisableout),
.phfifowrenableout(),
.phfifoxnbytesel(int_rx_phfifoxnbytesel[11:9]),
.phfifoxnptrsreset(int_rx_phfifioxnptrsreset[11:9]),
.phfifoxnrdenable(int_rx_phfifoxnrdenable[11:9]),
.phfifoxnwrclk(int_rx_phfifoxnwrclk[11:9]),
.phfifoxnwrenable(int_rx_phfifoxnwrenable[11:9]),
.pipe8b10binvpolarity(pipe8b10binvpolarity[3]),
.pipebufferstat(),
.pipedatavalid(wire_receive_pcs3_pipedatavalid),
.pipeelecidle(wire_receive_pcs3_pipeelecidle),
.pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[3]),
.pipephydonestatus(wire_receive_pcs3_pipephydonestatus),
.pipepowerdown(tx_pipepowerdownout[7:6]),
.pipepowerstate(tx_pipepowerstateout[15:12]),
.pipestatetransdoneout(wire_receive_pcs3_pipestatetransdoneout),
.pipestatus(wire_receive_pcs3_pipestatus),
.powerdn(powerdn[7:6]),
.prbscidenable(rx_prbscidenable[3]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitch(rateswitch[0]),
.rateswitchout(wire_receive_pcs3_rateswitchout),
.rateswitchxndone(int_hiprateswtichdone[0]),
.rdalign(),
.recoveredclk(rx_pma_clockout[3]),
.refclk(refclk_pma[0]),
.revbitorderwa(1'b0),
.revbyteorderwa(1'b0),
.revparallelfdbkdata(wire_receive_pcs3_revparallelfdbkdata),
.rlv(),
.rmfifoalmostempty(),
.rmfifoalmostfull(),
.rmfifodatadeleted(),
.rmfifodatainserted(),
.rmfifoempty(),
.rmfifofull(),
.rmfifordena(1'b0),
.rmfiforeset(rx_rmfiforeset[3]),
.rmfifowrena(1'b0),
.runningdisp(),
.rxdetectvalid(tx_rxdetectvalidout[3]),
.rxfound(rx_pcs_rxfound_wire[7:6]),
.signaldetect(wire_receive_pcs3_signaldetect),
.signaldetected(rx_signaldetect_wire[3]),
.syncstatus(wire_receive_pcs3_syncstatus),
.syncstatusdeskew(),
.xauidelcondmetout(),
.xauififoovrout(),
.xauiinsertincompleteout(),
.xauilatencycompout(),
.xgmctrldet(),
.xgmctrlin(1'b0),
.xgmdatain({8{1'b0}}),
.xgmdataout(),
.xgmdatavalid(),
.xgmrunningdisp()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslip(1'b0),
.cdrctrllocktorefcl(1'b0),
.hip8b10binvpolarity(1'b0),
.hipelecidleinfersel({3{1'b0}}),
.hippowerdown({2{1'b0}}),
.hiprateswitch(1'b0),
.phfifox4bytesel(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrclk(1'b0),
.phfifox4wrenable(1'b0),
.phfifox8bytesel(1'b0),
.phfifox8rdenable(1'b0),
.phfifox8wrclk(1'b0),
.phfifox8wrenable(1'b0),
.pmatestbusin({8{1'b0}}),
.ppmdetectdividedclk(1'b0),
.ppmdetectrefclk(1'b0),
.rateswitchisdone(1'b0),
.rxelecidlerateswitch(1'b0),
.wareset(1'b0),
.xauidelcondmet(1'b0),
.xauififoovr(1'b0),
.xauiinsertincomplete(1'b0),
.xauilatencycomp(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pcs3.align_pattern = "0101111100",
receive_pcs3.align_pattern_length = 10,
receive_pcs3.align_to_deskew_pattern_pos_disp_only = "false",
receive_pcs3.allow_align_polarity_inversion = "false",
receive_pcs3.allow_pipe_polarity_inversion = "true",
receive_pcs3.auto_spd_deassert_ph_fifo_rst_count = 8,
receive_pcs3.auto_spd_phystatus_notify_count = 14,
receive_pcs3.auto_spd_self_switch_enable = "true",
receive_pcs3.bit_slip_enable = "false",
receive_pcs3.byte_order_double_data_mode_mask_enable = "false",
receive_pcs3.byte_order_invalid_code_or_run_disp_error = "true",
receive_pcs3.byte_order_mode = "none",
receive_pcs3.byte_order_pad_pattern = "0",
receive_pcs3.byte_order_pattern = "0",
receive_pcs3.byte_order_pld_ctrl_enable = "false",
receive_pcs3.cdrctrl_bypass_ppm_detector_cycle = 1000,
receive_pcs3.cdrctrl_cid_mode_enable = "true",
receive_pcs3.cdrctrl_enable = "true",
receive_pcs3.cdrctrl_rxvalid_mask = "true",
receive_pcs3.channel_bonding = "x8",
receive_pcs3.channel_number = ((starting_channel_number + 3) % 4),
receive_pcs3.channel_width = 16,
receive_pcs3.clk1_mux_select = "recovered clock",
receive_pcs3.clk2_mux_select = "digital reference clock",
receive_pcs3.core_clock_0ppm = "false",
receive_pcs3.datapath_low_latency_mode = "false",
receive_pcs3.datapath_protocol = "pipe",
receive_pcs3.dec_8b_10b_compatibility_mode = "true",
receive_pcs3.dec_8b_10b_mode = "normal",
receive_pcs3.dec_8b_10b_polarity_inv_enable = "true",
receive_pcs3.deskew_pattern = "0",
receive_pcs3.disable_auto_idle_insertion = "false",
receive_pcs3.disable_running_disp_in_word_align = "false",
receive_pcs3.disallow_kchar_after_pattern_ordered_set = "false",
receive_pcs3.dprio_config_mode = 6'h01,
receive_pcs3.elec_idle_gen1_sigdet_enable = "true",
receive_pcs3.elec_idle_infer_enable = "false",
receive_pcs3.elec_idle_num_com_detect = 3,
receive_pcs3.enable_bit_reversal = "false",
receive_pcs3.enable_deep_align = "false",
receive_pcs3.enable_deep_align_byte_swap = "false",
receive_pcs3.enable_self_test_mode = "false",
receive_pcs3.enable_true_complement_match_in_word_align = "false",
receive_pcs3.force_signal_detect_dig = "true",
receive_pcs3.hip_enable = "false",
receive_pcs3.infiniband_invalid_code = 0,
receive_pcs3.insert_pad_on_underflow = "false",
receive_pcs3.logical_channel_address = (starting_channel_number + 3),
receive_pcs3.num_align_code_groups_in_ordered_set = 0,
receive_pcs3.num_align_cons_good_data = 16,
receive_pcs3.num_align_cons_pat = 4,
receive_pcs3.num_align_loss_sync_error = 17,
receive_pcs3.ph_fifo_low_latency_enable = "true",
receive_pcs3.ph_fifo_reg_mode = "false",
receive_pcs3.ph_fifo_xn_mapping0 = "none",
receive_pcs3.ph_fifo_xn_mapping1 = "none",
receive_pcs3.ph_fifo_xn_mapping2 = "central",
receive_pcs3.ph_fifo_xn_select = 2,
receive_pcs3.pipe_auto_speed_nego_enable = "true",
receive_pcs3.pipe_freq_scale_mode = "Frequency",
receive_pcs3.pma_done_count = 249950,
receive_pcs3.protocol_hint = "pcie2",
receive_pcs3.rate_match_almost_empty_threshold = 11,
receive_pcs3.rate_match_almost_full_threshold = 13,
receive_pcs3.rate_match_back_to_back = "false",
receive_pcs3.rate_match_delete_threshold = 13,
receive_pcs3.rate_match_empty_threshold = 5,
receive_pcs3.rate_match_fifo_mode = "true",
receive_pcs3.rate_match_full_threshold = 20,
receive_pcs3.rate_match_insert_threshold = 11,
receive_pcs3.rate_match_ordered_set_based = "false",
receive_pcs3.rate_match_pattern1 = "11010000111010000011",
receive_pcs3.rate_match_pattern2 = "00101111000101111100",
receive_pcs3.rate_match_pattern_size = 20,
receive_pcs3.rate_match_pipe_enable = "true",
receive_pcs3.rate_match_reset_enable = "false",
receive_pcs3.rate_match_skip_set_based = "true",
receive_pcs3.rate_match_start_threshold = 7,
receive_pcs3.rd_clk_mux_select = "core clock",
receive_pcs3.recovered_clk_mux_select = "recovered clock",
receive_pcs3.run_length = 40,
receive_pcs3.run_length_enable = "true",
receive_pcs3.rx_detect_bypass = "false",
receive_pcs3.rx_phfifo_wait_cnt = 32,
receive_pcs3.rxstatus_error_report_mode = 1,
receive_pcs3.self_test_mode = "incremental",
receive_pcs3.use_alignment_state_machine = "true",
receive_pcs3.use_deserializer_double_data_mode = "false",
receive_pcs3.use_deskew_fifo = "false",
receive_pcs3.use_double_data_mode = "true",
receive_pcs3.use_parallel_loopback = "false",
receive_pcs3.use_rising_edge_triggered_pattern_align = "false",
receive_pcs3.lpm_type = "stratixiv_hssi_rx_pcs";
stratixiv_hssi_rx_pcs receive_pcs4
(
.a1a2size(1'b0),
.a1a2sizeout(),
.a1detect(),
.a2detect(),
.adetectdeskew(),
.alignstatus(1'b0),
.alignstatussync(1'b0),
.alignstatussyncout(),
.autospdrateswitchout(wire_receive_pcs4_autospdrateswitchout),
.autospdspdchgout(wire_receive_pcs4_autospdspdchgout),
.autospdxnconfigsel(int_rx_autospdxnconfigsel[14:12]),
.autospdxnspdchg(int_rx_autospdxnspdchg[14:12]),
.bistdone(),
.bisterr(),
.bitslipboundaryselectout(),
.byteorderalignstatus(),
.cdrctrlearlyeios(wire_receive_pcs4_cdrctrlearlyeios),
.cdrctrllocktorefclkout(wire_receive_pcs4_cdrctrllocktorefclkout),
.clkout(),
.coreclk(rx_coreclk_in[4]),
.coreclkout(wire_receive_pcs4_coreclkout),
.ctrldetect(wire_receive_pcs4_ctrldetect),
.datain(rx_pma_recoverdataout_wire[99:80]),
.dataout(wire_receive_pcs4_dataout),
.dataoutfull(),
.digitalreset(rx_digitalreset_out[4]),
.digitaltestout(),
.disablefifordin(1'b0),
.disablefifordout(),
.disablefifowrin(1'b0),
.disablefifowrout(),
.disperr(),
.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
.dprioin(rx_pcsdprioin_wire[1999:1600]),
.dprioout(wire_receive_pcs4_dprioout),
.elecidleinfersel({3{1'b0}}),
.enabledeskew(1'b0),
.enabyteord(1'b0),
.enapatternalign(rx_enapatternalign[4]),
.errdetect(),
.fifordin(1'b0),
.fifordout(),
.fiforesetrd(1'b0),
.grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[14:12]),
.hipdataout(),
.hipdatavalid(),
.hipelecidle(),
.hipphydonestatus(),
.hipstatus(),
.invpol(1'b0),
.iqpautospdxnspgchg(int_rx_iqpautospdxnspgchg[9:8]),
.iqpphfifobyteselout(wire_receive_pcs4_iqpphfifobyteselout),
.iqpphfifoptrsresetout(wire_receive_pcs4_iqpphfifoptrsresetout),
.iqpphfifordenableout(wire_receive_pcs4_iqpphfifordenableout),
.iqpphfifowrclkout(wire_receive_pcs4_iqpphfifowrclkout),
.iqpphfifowrenableout(wire_receive_pcs4_iqpphfifowrenableout),
.iqpphfifoxnbytesel(int_rx_iqpphfifoxnbytesel[9:8]),
.iqpphfifoxnptrsreset(int_rx_iqpphfifoxnptrsreset[9:8]),
.iqpphfifoxnrdenable(int_rx_iqpphfifoxnrdenable[9:8]),
.iqpphfifoxnwrclk(int_rx_iqpphfifoxnwrclk[9:8]),
.iqpphfifoxnwrenable(int_rx_iqpphfifoxnwrenable[9:8]),
.k1detect(),
.k2detect(),
.localrefclk(1'b0),
.masterclk(1'b0),
.parallelfdbk({20{1'b0}}),
.patterndetect(wire_receive_pcs4_patterndetect),
.phfifobyteselout(),
.phfifobyteserdisableout(wire_receive_pcs4_phfifobyteserdisableout),
.phfifooverflow(),
.phfifoptrsresetout(wire_receive_pcs4_phfifoptrsresetout),
.phfifordenable(rx_phfifordenable[4]),
.phfifordenableout(wire_receive_pcs4_phfifordenableout),
.phfiforeset(rx_phfiforeset[4]),
.phfiforesetout(wire_receive_pcs4_phfiforesetout),
.phfifounderflow(),
.phfifowrclkout(),
.phfifowrdisable(rx_phfifowrdisable[4]),
.phfifowrdisableout(wire_receive_pcs4_phfifowrdisableout),
.phfifowrenableout(),
.phfifoxnbytesel(int_rx_phfifoxnbytesel[14:12]),
.phfifoxnptrsreset(int_rx_phfifioxnptrsreset[14:12]),
.phfifoxnrdenable(int_rx_phfifoxnrdenable[14:12]),
.phfifoxnwrclk(int_rx_phfifoxnwrclk[14:12]),
.phfifoxnwrenable(int_rx_phfifoxnwrenable[14:12]),
.pipe8b10binvpolarity(pipe8b10binvpolarity[4]),
.pipebufferstat(),
.pipedatavalid(wire_receive_pcs4_pipedatavalid),
.pipeelecidle(wire_receive_pcs4_pipeelecidle),
.pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[4]),
.pipephydonestatus(wire_receive_pcs4_pipephydonestatus),
.pipepowerdown(tx_pipepowerdownout[9:8]),
.pipepowerstate(tx_pipepowerstateout[19:16]),
.pipestatetransdoneout(wire_receive_pcs4_pipestatetransdoneout),
.pipestatus(wire_receive_pcs4_pipestatus),
.powerdn(powerdn[9:8]),
.prbscidenable(rx_prbscidenable[4]),
.quadreset(cent_unit_quadresetout[1]),
.rateswitch(rateswitch[0]),
.rateswitchout(wire_receive_pcs4_rateswitchout),
.rateswitchxndone(int_hiprateswtichdone[1]),
.rdalign(),
.recoveredclk(rx_pma_clockout[4]),
.refclk(refclk_pma[1]),
.revbitorderwa(1'b0),
.revbyteorderwa(1'b0),
.revparallelfdbkdata(wire_receive_pcs4_revparallelfdbkdata),
.rlv(),
.rmfifoalmostempty(),
.rmfifoalmostfull(),
.rmfifodatadeleted(),
.rmfifodatainserted(),
.rmfifoempty(),
.rmfifofull(),
.rmfifordena(1'b0),
.rmfiforeset(rx_rmfiforeset[4]),
.rmfifowrena(1'b0),
.runningdisp(),
.rxdetectvalid(tx_rxdetectvalidout[4]),
.rxfound(rx_pcs_rxfound_wire[9:8]),
.signaldetect(wire_receive_pcs4_signaldetect),
.signaldetected(rx_signaldetect_wire[4]),
.syncstatus(wire_receive_pcs4_syncstatus),
.syncstatusdeskew(),
.xauidelcondmetout(),
.xauififoovrout(),
.xauiinsertincompleteout(),
.xauilatencycompout(),
.xgmctrldet(),
.xgmctrlin(1'b0),
.xgmdatain({8{1'b0}}),
.xgmdataout(),
.xgmdatavalid(),
.xgmrunningdisp()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslip(1'b0),
.cdrctrllocktorefcl(1'b0),
.hip8b10binvpolarity(1'b0),
.hipelecidleinfersel({3{1'b0}}),
.hippowerdown({2{1'b0}}),
.hiprateswitch(1'b0),
.phfifox4bytesel(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrclk(1'b0),
.phfifox4wrenable(1'b0),
.phfifox8bytesel(1'b0),
.phfifox8rdenable(1'b0),
.phfifox8wrclk(1'b0),
.phfifox8wrenable(1'b0),
.pmatestbusin({8{1'b0}}),
.ppmdetectdividedclk(1'b0),
.ppmdetectrefclk(1'b0),
.rateswitchisdone(1'b0),
.rxelecidlerateswitch(1'b0),
.wareset(1'b0),
.xauidelcondmet(1'b0),
.xauififoovr(1'b0),
.xauiinsertincomplete(1'b0),
.xauilatencycomp(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pcs4.align_pattern = "0101111100",
receive_pcs4.align_pattern_length = 10,
receive_pcs4.align_to_deskew_pattern_pos_disp_only = "false",
receive_pcs4.allow_align_polarity_inversion = "false",
receive_pcs4.allow_pipe_polarity_inversion = "true",
receive_pcs4.auto_spd_deassert_ph_fifo_rst_count = 8,
receive_pcs4.auto_spd_phystatus_notify_count = 14,
receive_pcs4.auto_spd_self_switch_enable = "true",
receive_pcs4.bit_slip_enable = "false",
receive_pcs4.byte_order_double_data_mode_mask_enable = "false",
receive_pcs4.byte_order_invalid_code_or_run_disp_error = "true",
receive_pcs4.byte_order_mode = "none",
receive_pcs4.byte_order_pad_pattern = "0",
receive_pcs4.byte_order_pattern = "0",
receive_pcs4.byte_order_pld_ctrl_enable = "false",
receive_pcs4.cdrctrl_bypass_ppm_detector_cycle = 1000,
receive_pcs4.cdrctrl_cid_mode_enable = "true",
receive_pcs4.cdrctrl_enable = "true",
receive_pcs4.cdrctrl_rxvalid_mask = "true",
receive_pcs4.channel_bonding = "x8",
receive_pcs4.channel_number = ((starting_channel_number + 4) % 4),
receive_pcs4.channel_width = 16,
receive_pcs4.clk1_mux_select = "recovered clock",
receive_pcs4.clk2_mux_select = "digital reference clock",
receive_pcs4.core_clock_0ppm = "false",
receive_pcs4.datapath_low_latency_mode = "false",
receive_pcs4.datapath_protocol = "pipe",
receive_pcs4.dec_8b_10b_compatibility_mode = "true",
receive_pcs4.dec_8b_10b_mode = "normal",
receive_pcs4.dec_8b_10b_polarity_inv_enable = "true",
receive_pcs4.deskew_pattern = "0",
receive_pcs4.disable_auto_idle_insertion = "false",
receive_pcs4.disable_running_disp_in_word_align = "false",
receive_pcs4.disallow_kchar_after_pattern_ordered_set = "false",
receive_pcs4.dprio_config_mode = 6'h01,
receive_pcs4.elec_idle_gen1_sigdet_enable = "true",
receive_pcs4.elec_idle_infer_enable = "false",
receive_pcs4.elec_idle_num_com_detect = 3,
receive_pcs4.enable_bit_reversal = "false",
receive_pcs4.enable_deep_align = "false",
receive_pcs4.enable_deep_align_byte_swap = "false",
receive_pcs4.enable_self_test_mode = "false",
receive_pcs4.enable_true_complement_match_in_word_align = "false",
receive_pcs4.force_signal_detect_dig = "true",
receive_pcs4.hip_enable = "false",
receive_pcs4.infiniband_invalid_code = 0,
receive_pcs4.insert_pad_on_underflow = "false",
receive_pcs4.iqp_ph_fifo_xn_select = 1,
receive_pcs4.logical_channel_address = (starting_channel_number + 4),
receive_pcs4.num_align_code_groups_in_ordered_set = 0,
receive_pcs4.num_align_cons_good_data = 16,
receive_pcs4.num_align_cons_pat = 4,
receive_pcs4.num_align_loss_sync_error = 17,
receive_pcs4.ph_fifo_low_latency_enable = "true",
receive_pcs4.ph_fifo_reg_mode = "false",
receive_pcs4.ph_fifo_xn_mapping0 = "none",
receive_pcs4.ph_fifo_xn_mapping1 = "up",
receive_pcs4.ph_fifo_xn_mapping2 = "none",
receive_pcs4.ph_fifo_xn_select = 1,
receive_pcs4.pipe_auto_speed_nego_enable = "true",
receive_pcs4.pipe_freq_scale_mode = "Frequency",
receive_pcs4.pma_done_count = 249950,
receive_pcs4.protocol_hint = "pcie2",
receive_pcs4.rate_match_almost_empty_threshold = 11,
receive_pcs4.rate_match_almost_full_threshold = 13,
receive_pcs4.rate_match_back_to_back = "false",
receive_pcs4.rate_match_delete_threshold = 13,
receive_pcs4.rate_match_empty_threshold = 5,
receive_pcs4.rate_match_fifo_mode = "true",
receive_pcs4.rate_match_full_threshold = 20,
receive_pcs4.rate_match_insert_threshold = 11,
receive_pcs4.rate_match_ordered_set_based = "false",
receive_pcs4.rate_match_pattern1 = "11010000111010000011",
receive_pcs4.rate_match_pattern2 = "00101111000101111100",
receive_pcs4.rate_match_pattern_size = 20,
receive_pcs4.rate_match_pipe_enable = "true",
receive_pcs4.rate_match_reset_enable = "false",
receive_pcs4.rate_match_skip_set_based = "true",
receive_pcs4.rate_match_start_threshold = 7,
receive_pcs4.rd_clk_mux_select = "core clock",
receive_pcs4.recovered_clk_mux_select = "recovered clock",
receive_pcs4.run_length = 40,
receive_pcs4.run_length_enable = "true",
receive_pcs4.rx_detect_bypass = "false",
receive_pcs4.rx_phfifo_wait_cnt = 32,
receive_pcs4.rxstatus_error_report_mode = 1,
receive_pcs4.self_test_mode = "incremental",
receive_pcs4.use_alignment_state_machine = "true",
receive_pcs4.use_deserializer_double_data_mode = "false",
receive_pcs4.use_deskew_fifo = "false",
receive_pcs4.use_double_data_mode = "true",
receive_pcs4.use_parallel_loopback = "false",
receive_pcs4.use_rising_edge_triggered_pattern_align = "false",
receive_pcs4.lpm_type = "stratixiv_hssi_rx_pcs";
stratixiv_hssi_rx_pcs receive_pcs5
(
.a1a2size(1'b0),
.a1a2sizeout(),
.a1detect(),
.a2detect(),
.adetectdeskew(),
.alignstatus(1'b0),
.alignstatussync(1'b0),
.alignstatussyncout(),
.autospdrateswitchout(wire_receive_pcs5_autospdrateswitchout),
.autospdspdchgout(wire_receive_pcs5_autospdspdchgout),
.autospdxnconfigsel(int_rx_autospdxnconfigsel[17:15]),
.autospdxnspdchg(int_rx_autospdxnspdchg[17:15]),
.bistdone(),
.bisterr(),
.bitslipboundaryselectout(),
.byteorderalignstatus(),
.cdrctrlearlyeios(wire_receive_pcs5_cdrctrlearlyeios),
.cdrctrllocktorefclkout(wire_receive_pcs5_cdrctrllocktorefclkout),
.clkout(),
.coreclk(rx_coreclk_in[5]),
.coreclkout(wire_receive_pcs5_coreclkout),
.ctrldetect(wire_receive_pcs5_ctrldetect),
.datain(rx_pma_recoverdataout_wire[119:100]),
.dataout(wire_receive_pcs5_dataout),
.dataoutfull(),
.digitalreset(rx_digitalreset_out[5]),
.digitaltestout(),
.disablefifordin(1'b0),
.disablefifordout(),
.disablefifowrin(1'b0),
.disablefifowrout(),
.disperr(),
.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
.dprioin(rx_pcsdprioin_wire[2399:2000]),
.dprioout(wire_receive_pcs5_dprioout),
.elecidleinfersel({3{1'b0}}),
.enabledeskew(1'b0),
.enabyteord(1'b0),
.enapatternalign(rx_enapatternalign[5]),
.errdetect(),
.fifordin(1'b0),
.fifordout(),
.fiforesetrd(1'b0),
.grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[17:15]),
.hipdataout(),
.hipdatavalid(),
.hipelecidle(),
.hipphydonestatus(),
.hipstatus(),
.invpol(1'b0),
.iqpautospdxnspgchg(int_rx_iqpautospdxnspgchg[11:10]),
.iqpphfifobyteselout(wire_receive_pcs5_iqpphfifobyteselout),
.iqpphfifoptrsresetout(wire_receive_pcs5_iqpphfifoptrsresetout),
.iqpphfifordenableout(wire_receive_pcs5_iqpphfifordenableout),
.iqpphfifowrclkout(wire_receive_pcs5_iqpphfifowrclkout),
.iqpphfifowrenableout(wire_receive_pcs5_iqpphfifowrenableout),
.iqpphfifoxnbytesel(int_rx_iqpphfifoxnbytesel[11:10]),
.iqpphfifoxnptrsreset(int_rx_iqpphfifoxnptrsreset[11:10]),
.iqpphfifoxnrdenable(int_rx_iqpphfifoxnrdenable[11:10]),
.iqpphfifoxnwrclk(int_rx_iqpphfifoxnwrclk[11:10]),
.iqpphfifoxnwrenable(int_rx_iqpphfifoxnwrenable[11:10]),
.k1detect(),
.k2detect(),
.localrefclk(1'b0),
.masterclk(1'b0),
.parallelfdbk({20{1'b0}}),
.patterndetect(wire_receive_pcs5_patterndetect),
.phfifobyteselout(),
.phfifobyteserdisableout(wire_receive_pcs5_phfifobyteserdisableout),
.phfifooverflow(),
.phfifoptrsresetout(wire_receive_pcs5_phfifoptrsresetout),
.phfifordenable(rx_phfifordenable[5]),
.phfifordenableout(wire_receive_pcs5_phfifordenableout),
.phfiforeset(rx_phfiforeset[5]),
.phfiforesetout(wire_receive_pcs5_phfiforesetout),
.phfifounderflow(),
.phfifowrclkout(),
.phfifowrdisable(rx_phfifowrdisable[5]),
.phfifowrdisableout(wire_receive_pcs5_phfifowrdisableout),
.phfifowrenableout(),
.phfifoxnbytesel(int_rx_phfifoxnbytesel[17:15]),
.phfifoxnptrsreset(int_rx_phfifioxnptrsreset[17:15]),
.phfifoxnrdenable(int_rx_phfifoxnrdenable[17:15]),
.phfifoxnwrclk(int_rx_phfifoxnwrclk[17:15]),
.phfifoxnwrenable(int_rx_phfifoxnwrenable[17:15]),
.pipe8b10binvpolarity(pipe8b10binvpolarity[5]),
.pipebufferstat(),
.pipedatavalid(wire_receive_pcs5_pipedatavalid),
.pipeelecidle(wire_receive_pcs5_pipeelecidle),
.pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[5]),
.pipephydonestatus(wire_receive_pcs5_pipephydonestatus),
.pipepowerdown(tx_pipepowerdownout[11:10]),
.pipepowerstate(tx_pipepowerstateout[23:20]),
.pipestatetransdoneout(wire_receive_pcs5_pipestatetransdoneout),
.pipestatus(wire_receive_pcs5_pipestatus),
.powerdn(powerdn[11:10]),
.prbscidenable(rx_prbscidenable[5]),
.quadreset(cent_unit_quadresetout[1]),
.rateswitch(rateswitch[0]),
.rateswitchout(wire_receive_pcs5_rateswitchout),
.rateswitchxndone(int_hiprateswtichdone[1]),
.rdalign(),
.recoveredclk(rx_pma_clockout[5]),
.refclk(refclk_pma[1]),
.revbitorderwa(1'b0),
.revbyteorderwa(1'b0),
.revparallelfdbkdata(wire_receive_pcs5_revparallelfdbkdata),
.rlv(),
.rmfifoalmostempty(),
.rmfifoalmostfull(),
.rmfifodatadeleted(),
.rmfifodatainserted(),
.rmfifoempty(),
.rmfifofull(),
.rmfifordena(1'b0),
.rmfiforeset(rx_rmfiforeset[5]),
.rmfifowrena(1'b0),
.runningdisp(),
.rxdetectvalid(tx_rxdetectvalidout[5]),
.rxfound(rx_pcs_rxfound_wire[11:10]),
.signaldetect(wire_receive_pcs5_signaldetect),
.signaldetected(rx_signaldetect_wire[5]),
.syncstatus(wire_receive_pcs5_syncstatus),
.syncstatusdeskew(),
.xauidelcondmetout(),
.xauififoovrout(),
.xauiinsertincompleteout(),
.xauilatencycompout(),
.xgmctrldet(),
.xgmctrlin(1'b0),
.xgmdatain({8{1'b0}}),
.xgmdataout(),
.xgmdatavalid(),
.xgmrunningdisp()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslip(1'b0),
.cdrctrllocktorefcl(1'b0),
.hip8b10binvpolarity(1'b0),
.hipelecidleinfersel({3{1'b0}}),
.hippowerdown({2{1'b0}}),
.hiprateswitch(1'b0),
.phfifox4bytesel(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrclk(1'b0),
.phfifox4wrenable(1'b0),
.phfifox8bytesel(1'b0),
.phfifox8rdenable(1'b0),
.phfifox8wrclk(1'b0),
.phfifox8wrenable(1'b0),
.pmatestbusin({8{1'b0}}),
.ppmdetectdividedclk(1'b0),
.ppmdetectrefclk(1'b0),
.rateswitchisdone(1'b0),
.rxelecidlerateswitch(1'b0),
.wareset(1'b0),
.xauidelcondmet(1'b0),
.xauififoovr(1'b0),
.xauiinsertincomplete(1'b0),
.xauilatencycomp(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pcs5.align_pattern = "0101111100",
receive_pcs5.align_pattern_length = 10,
receive_pcs5.align_to_deskew_pattern_pos_disp_only = "false",
receive_pcs5.allow_align_polarity_inversion = "false",
receive_pcs5.allow_pipe_polarity_inversion = "true",
receive_pcs5.auto_spd_deassert_ph_fifo_rst_count = 8,
receive_pcs5.auto_spd_phystatus_notify_count = 14,
receive_pcs5.auto_spd_self_switch_enable = "true",
receive_pcs5.bit_slip_enable = "false",
receive_pcs5.byte_order_double_data_mode_mask_enable = "false",
receive_pcs5.byte_order_invalid_code_or_run_disp_error = "true",
receive_pcs5.byte_order_mode = "none",
receive_pcs5.byte_order_pad_pattern = "0",
receive_pcs5.byte_order_pattern = "0",
receive_pcs5.byte_order_pld_ctrl_enable = "false",
receive_pcs5.cdrctrl_bypass_ppm_detector_cycle = 1000,
receive_pcs5.cdrctrl_cid_mode_enable = "true",
receive_pcs5.cdrctrl_enable = "true",
receive_pcs5.cdrctrl_rxvalid_mask = "true",
receive_pcs5.channel_bonding = "x8",
receive_pcs5.channel_number = ((starting_channel_number + 5) % 4),
receive_pcs5.channel_width = 16,
receive_pcs5.clk1_mux_select = "recovered clock",
receive_pcs5.clk2_mux_select = "digital reference clock",
receive_pcs5.core_clock_0ppm = "false",
receive_pcs5.datapath_low_latency_mode = "false",
receive_pcs5.datapath_protocol = "pipe",
receive_pcs5.dec_8b_10b_compatibility_mode = "true",
receive_pcs5.dec_8b_10b_mode = "normal",
receive_pcs5.dec_8b_10b_polarity_inv_enable = "true",
receive_pcs5.deskew_pattern = "0",
receive_pcs5.disable_auto_idle_insertion = "false",
receive_pcs5.disable_running_disp_in_word_align = "false",
receive_pcs5.disallow_kchar_after_pattern_ordered_set = "false",
receive_pcs5.dprio_config_mode = 6'h01,
receive_pcs5.elec_idle_gen1_sigdet_enable = "true",
receive_pcs5.elec_idle_infer_enable = "false",
receive_pcs5.elec_idle_num_com_detect = 3,
receive_pcs5.enable_bit_reversal = "false",
receive_pcs5.enable_deep_align = "false",
receive_pcs5.enable_deep_align_byte_swap = "false",
receive_pcs5.enable_self_test_mode = "false",
receive_pcs5.enable_true_complement_match_in_word_align = "false",
receive_pcs5.force_signal_detect_dig = "true",
receive_pcs5.hip_enable = "false",
receive_pcs5.infiniband_invalid_code = 0,
receive_pcs5.insert_pad_on_underflow = "false",
receive_pcs5.logical_channel_address = (starting_channel_number + 5),
receive_pcs5.num_align_code_groups_in_ordered_set = 0,
receive_pcs5.num_align_cons_good_data = 16,
receive_pcs5.num_align_cons_pat = 4,
receive_pcs5.num_align_loss_sync_error = 17,
receive_pcs5.ph_fifo_low_latency_enable = "true",
receive_pcs5.ph_fifo_reg_mode = "false",
receive_pcs5.ph_fifo_xn_mapping0 = "none",
receive_pcs5.ph_fifo_xn_mapping1 = "up",
receive_pcs5.ph_fifo_xn_mapping2 = "none",
receive_pcs5.ph_fifo_xn_select = 1,
receive_pcs5.pipe_auto_speed_nego_enable = "true",
receive_pcs5.pipe_freq_scale_mode = "Frequency",
receive_pcs5.pma_done_count = 249950,
receive_pcs5.protocol_hint = "pcie2",
receive_pcs5.rate_match_almost_empty_threshold = 11,
receive_pcs5.rate_match_almost_full_threshold = 13,
receive_pcs5.rate_match_back_to_back = "false",
receive_pcs5.rate_match_delete_threshold = 13,
receive_pcs5.rate_match_empty_threshold = 5,
receive_pcs5.rate_match_fifo_mode = "true",
receive_pcs5.rate_match_full_threshold = 20,
receive_pcs5.rate_match_insert_threshold = 11,
receive_pcs5.rate_match_ordered_set_based = "false",
receive_pcs5.rate_match_pattern1 = "11010000111010000011",
receive_pcs5.rate_match_pattern2 = "00101111000101111100",
receive_pcs5.rate_match_pattern_size = 20,
receive_pcs5.rate_match_pipe_enable = "true",
receive_pcs5.rate_match_reset_enable = "false",
receive_pcs5.rate_match_skip_set_based = "true",
receive_pcs5.rate_match_start_threshold = 7,
receive_pcs5.rd_clk_mux_select = "core clock",
receive_pcs5.recovered_clk_mux_select = "recovered clock",
receive_pcs5.run_length = 40,
receive_pcs5.run_length_enable = "true",
receive_pcs5.rx_detect_bypass = "false",
receive_pcs5.rx_phfifo_wait_cnt = 32,
receive_pcs5.rxstatus_error_report_mode = 1,
receive_pcs5.self_test_mode = "incremental",
receive_pcs5.use_alignment_state_machine = "true",
receive_pcs5.use_deserializer_double_data_mode = "false",
receive_pcs5.use_deskew_fifo = "false",
receive_pcs5.use_double_data_mode = "true",
receive_pcs5.use_parallel_loopback = "false",
receive_pcs5.use_rising_edge_triggered_pattern_align = "false",
receive_pcs5.lpm_type = "stratixiv_hssi_rx_pcs";
stratixiv_hssi_rx_pcs receive_pcs6
(
.a1a2size(1'b0),
.a1a2sizeout(),
.a1detect(),
.a2detect(),
.adetectdeskew(),
.alignstatus(1'b0),
.alignstatussync(1'b0),
.alignstatussyncout(),
.autospdrateswitchout(wire_receive_pcs6_autospdrateswitchout),
.autospdspdchgout(wire_receive_pcs6_autospdspdchgout),
.autospdxnconfigsel(int_rx_autospdxnconfigsel[20:18]),
.autospdxnspdchg(int_rx_autospdxnspdchg[20:18]),
.bistdone(),
.bisterr(),
.bitslipboundaryselectout(),
.byteorderalignstatus(),
.cdrctrlearlyeios(wire_receive_pcs6_cdrctrlearlyeios),
.cdrctrllocktorefclkout(wire_receive_pcs6_cdrctrllocktorefclkout),
.clkout(),
.coreclk(rx_coreclk_in[6]),
.coreclkout(wire_receive_pcs6_coreclkout),
.ctrldetect(wire_receive_pcs6_ctrldetect),
.datain(rx_pma_recoverdataout_wire[139:120]),
.dataout(wire_receive_pcs6_dataout),
.dataoutfull(),
.digitalreset(rx_digitalreset_out[6]),
.digitaltestout(),
.disablefifordin(1'b0),
.disablefifordout(),
.disablefifowrin(1'b0),
.disablefifowrout(),
.disperr(),
.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
.dprioin(rx_pcsdprioin_wire[2799:2400]),
.dprioout(wire_receive_pcs6_dprioout),
.elecidleinfersel({3{1'b0}}),
.enabledeskew(1'b0),
.enabyteord(1'b0),
.enapatternalign(rx_enapatternalign[6]),
.errdetect(),
.fifordin(1'b0),
.fifordout(),
.fiforesetrd(1'b0),
.grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[20:18]),
.hipdataout(),
.hipdatavalid(),
.hipelecidle(),
.hipphydonestatus(),
.hipstatus(),
.invpol(1'b0),
.iqpautospdxnspgchg(int_rx_iqpautospdxnspgchg[13:12]),
.iqpphfifobyteselout(wire_receive_pcs6_iqpphfifobyteselout),
.iqpphfifoptrsresetout(wire_receive_pcs6_iqpphfifoptrsresetout),
.iqpphfifordenableout(wire_receive_pcs6_iqpphfifordenableout),
.iqpphfifowrclkout(wire_receive_pcs6_iqpphfifowrclkout),
.iqpphfifowrenableout(wire_receive_pcs6_iqpphfifowrenableout),
.iqpphfifoxnbytesel(int_rx_iqpphfifoxnbytesel[13:12]),
.iqpphfifoxnptrsreset(int_rx_iqpphfifoxnptrsreset[13:12]),
.iqpphfifoxnrdenable(int_rx_iqpphfifoxnrdenable[13:12]),
.iqpphfifoxnwrclk(int_rx_iqpphfifoxnwrclk[13:12]),
.iqpphfifoxnwrenable(int_rx_iqpphfifoxnwrenable[13:12]),
.k1detect(),
.k2detect(),
.localrefclk(1'b0),
.masterclk(1'b0),
.parallelfdbk({20{1'b0}}),
.patterndetect(wire_receive_pcs6_patterndetect),
.phfifobyteselout(),
.phfifobyteserdisableout(wire_receive_pcs6_phfifobyteserdisableout),
.phfifooverflow(),
.phfifoptrsresetout(wire_receive_pcs6_phfifoptrsresetout),
.phfifordenable(rx_phfifordenable[6]),
.phfifordenableout(wire_receive_pcs6_phfifordenableout),
.phfiforeset(rx_phfiforeset[6]),
.phfiforesetout(wire_receive_pcs6_phfiforesetout),
.phfifounderflow(),
.phfifowrclkout(),
.phfifowrdisable(rx_phfifowrdisable[6]),
.phfifowrdisableout(wire_receive_pcs6_phfifowrdisableout),
.phfifowrenableout(),
.phfifoxnbytesel(int_rx_phfifoxnbytesel[20:18]),
.phfifoxnptrsreset(int_rx_phfifioxnptrsreset[20:18]),
.phfifoxnrdenable(int_rx_phfifoxnrdenable[20:18]),
.phfifoxnwrclk(int_rx_phfifoxnwrclk[20:18]),
.phfifoxnwrenable(int_rx_phfifoxnwrenable[20:18]),
.pipe8b10binvpolarity(pipe8b10binvpolarity[6]),
.pipebufferstat(),
.pipedatavalid(wire_receive_pcs6_pipedatavalid),
.pipeelecidle(wire_receive_pcs6_pipeelecidle),
.pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[6]),
.pipephydonestatus(wire_receive_pcs6_pipephydonestatus),
.pipepowerdown(tx_pipepowerdownout[13:12]),
.pipepowerstate(tx_pipepowerstateout[27:24]),
.pipestatetransdoneout(wire_receive_pcs6_pipestatetransdoneout),
.pipestatus(wire_receive_pcs6_pipestatus),
.powerdn(powerdn[13:12]),
.prbscidenable(rx_prbscidenable[6]),
.quadreset(cent_unit_quadresetout[1]),
.rateswitch(rateswitch[0]),
.rateswitchout(wire_receive_pcs6_rateswitchout),
.rateswitchxndone(int_hiprateswtichdone[1]),
.rdalign(),
.recoveredclk(rx_pma_clockout[6]),
.refclk(refclk_pma[1]),
.revbitorderwa(1'b0),
.revbyteorderwa(1'b0),
.revparallelfdbkdata(wire_receive_pcs6_revparallelfdbkdata),
.rlv(),
.rmfifoalmostempty(),
.rmfifoalmostfull(),
.rmfifodatadeleted(),
.rmfifodatainserted(),
.rmfifoempty(),
.rmfifofull(),
.rmfifordena(1'b0),
.rmfiforeset(rx_rmfiforeset[6]),
.rmfifowrena(1'b0),
.runningdisp(),
.rxdetectvalid(tx_rxdetectvalidout[6]),
.rxfound(rx_pcs_rxfound_wire[13:12]),
.signaldetect(wire_receive_pcs6_signaldetect),
.signaldetected(rx_signaldetect_wire[6]),
.syncstatus(wire_receive_pcs6_syncstatus),
.syncstatusdeskew(),
.xauidelcondmetout(),
.xauififoovrout(),
.xauiinsertincompleteout(),
.xauilatencycompout(),
.xgmctrldet(),
.xgmctrlin(1'b0),
.xgmdatain({8{1'b0}}),
.xgmdataout(),
.xgmdatavalid(),
.xgmrunningdisp()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslip(1'b0),
.cdrctrllocktorefcl(1'b0),
.hip8b10binvpolarity(1'b0),
.hipelecidleinfersel({3{1'b0}}),
.hippowerdown({2{1'b0}}),
.hiprateswitch(1'b0),
.phfifox4bytesel(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrclk(1'b0),
.phfifox4wrenable(1'b0),
.phfifox8bytesel(1'b0),
.phfifox8rdenable(1'b0),
.phfifox8wrclk(1'b0),
.phfifox8wrenable(1'b0),
.pmatestbusin({8{1'b0}}),
.ppmdetectdividedclk(1'b0),
.ppmdetectrefclk(1'b0),
.rateswitchisdone(1'b0),
.rxelecidlerateswitch(1'b0),
.wareset(1'b0),
.xauidelcondmet(1'b0),
.xauififoovr(1'b0),
.xauiinsertincomplete(1'b0),
.xauilatencycomp(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pcs6.align_pattern = "0101111100",
receive_pcs6.align_pattern_length = 10,
receive_pcs6.align_to_deskew_pattern_pos_disp_only = "false",
receive_pcs6.allow_align_polarity_inversion = "false",
receive_pcs6.allow_pipe_polarity_inversion = "true",
receive_pcs6.auto_spd_deassert_ph_fifo_rst_count = 8,
receive_pcs6.auto_spd_phystatus_notify_count = 14,
receive_pcs6.auto_spd_self_switch_enable = "true",
receive_pcs6.bit_slip_enable = "false",
receive_pcs6.byte_order_double_data_mode_mask_enable = "false",
receive_pcs6.byte_order_invalid_code_or_run_disp_error = "true",
receive_pcs6.byte_order_mode = "none",
receive_pcs6.byte_order_pad_pattern = "0",
receive_pcs6.byte_order_pattern = "0",
receive_pcs6.byte_order_pld_ctrl_enable = "false",
receive_pcs6.cdrctrl_bypass_ppm_detector_cycle = 1000,
receive_pcs6.cdrctrl_cid_mode_enable = "true",
receive_pcs6.cdrctrl_enable = "true",
receive_pcs6.cdrctrl_rxvalid_mask = "true",
receive_pcs6.channel_bonding = "x8",
receive_pcs6.channel_number = ((starting_channel_number + 6) % 4),
receive_pcs6.channel_width = 16,
receive_pcs6.clk1_mux_select = "recovered clock",
receive_pcs6.clk2_mux_select = "digital reference clock",
receive_pcs6.core_clock_0ppm = "false",
receive_pcs6.datapath_low_latency_mode = "false",
receive_pcs6.datapath_protocol = "pipe",
receive_pcs6.dec_8b_10b_compatibility_mode = "true",
receive_pcs6.dec_8b_10b_mode = "normal",
receive_pcs6.dec_8b_10b_polarity_inv_enable = "true",
receive_pcs6.deskew_pattern = "0",
receive_pcs6.disable_auto_idle_insertion = "false",
receive_pcs6.disable_running_disp_in_word_align = "false",
receive_pcs6.disallow_kchar_after_pattern_ordered_set = "false",
receive_pcs6.dprio_config_mode = 6'h01,
receive_pcs6.elec_idle_gen1_sigdet_enable = "true",
receive_pcs6.elec_idle_infer_enable = "false",
receive_pcs6.elec_idle_num_com_detect = 3,
receive_pcs6.enable_bit_reversal = "false",
receive_pcs6.enable_deep_align = "false",
receive_pcs6.enable_deep_align_byte_swap = "false",
receive_pcs6.enable_self_test_mode = "false",
receive_pcs6.enable_true_complement_match_in_word_align = "false",
receive_pcs6.force_signal_detect_dig = "true",
receive_pcs6.hip_enable = "false",
receive_pcs6.infiniband_invalid_code = 0,
receive_pcs6.insert_pad_on_underflow = "false",
receive_pcs6.logical_channel_address = (starting_channel_number + 6),
receive_pcs6.num_align_code_groups_in_ordered_set = 0,
receive_pcs6.num_align_cons_good_data = 16,
receive_pcs6.num_align_cons_pat = 4,
receive_pcs6.num_align_loss_sync_error = 17,
receive_pcs6.ph_fifo_low_latency_enable = "true",
receive_pcs6.ph_fifo_reg_mode = "false",
receive_pcs6.ph_fifo_xn_mapping0 = "none",
receive_pcs6.ph_fifo_xn_mapping1 = "up",
receive_pcs6.ph_fifo_xn_mapping2 = "none",
receive_pcs6.ph_fifo_xn_select = 1,
receive_pcs6.pipe_auto_speed_nego_enable = "true",
receive_pcs6.pipe_freq_scale_mode = "Frequency",
receive_pcs6.pma_done_count = 249950,
receive_pcs6.protocol_hint = "pcie2",
receive_pcs6.rate_match_almost_empty_threshold = 11,
receive_pcs6.rate_match_almost_full_threshold = 13,
receive_pcs6.rate_match_back_to_back = "false",
receive_pcs6.rate_match_delete_threshold = 13,
receive_pcs6.rate_match_empty_threshold = 5,
receive_pcs6.rate_match_fifo_mode = "true",
receive_pcs6.rate_match_full_threshold = 20,
receive_pcs6.rate_match_insert_threshold = 11,
receive_pcs6.rate_match_ordered_set_based = "false",
receive_pcs6.rate_match_pattern1 = "11010000111010000011",
receive_pcs6.rate_match_pattern2 = "00101111000101111100",
receive_pcs6.rate_match_pattern_size = 20,
receive_pcs6.rate_match_pipe_enable = "true",
receive_pcs6.rate_match_reset_enable = "false",
receive_pcs6.rate_match_skip_set_based = "true",
receive_pcs6.rate_match_start_threshold = 7,
receive_pcs6.rd_clk_mux_select = "core clock",
receive_pcs6.recovered_clk_mux_select = "recovered clock",
receive_pcs6.run_length = 40,
receive_pcs6.run_length_enable = "true",
receive_pcs6.rx_detect_bypass = "false",
receive_pcs6.rx_phfifo_wait_cnt = 32,
receive_pcs6.rxstatus_error_report_mode = 1,
receive_pcs6.self_test_mode = "incremental",
receive_pcs6.use_alignment_state_machine = "true",
receive_pcs6.use_deserializer_double_data_mode = "false",
receive_pcs6.use_deskew_fifo = "false",
receive_pcs6.use_double_data_mode = "true",
receive_pcs6.use_parallel_loopback = "false",
receive_pcs6.use_rising_edge_triggered_pattern_align = "false",
receive_pcs6.lpm_type = "stratixiv_hssi_rx_pcs";
stratixiv_hssi_rx_pcs receive_pcs7
(
.a1a2size(1'b0),
.a1a2sizeout(),
.a1detect(),
.a2detect(),
.adetectdeskew(),
.alignstatus(1'b0),
.alignstatussync(1'b0),
.alignstatussyncout(),
.autospdrateswitchout(wire_receive_pcs7_autospdrateswitchout),
.autospdspdchgout(wire_receive_pcs7_autospdspdchgout),
.autospdxnconfigsel(int_rx_autospdxnconfigsel[23:21]),
.autospdxnspdchg(int_rx_autospdxnspdchg[23:21]),
.bistdone(),
.bisterr(),
.bitslipboundaryselectout(),
.byteorderalignstatus(),
.cdrctrlearlyeios(wire_receive_pcs7_cdrctrlearlyeios),
.cdrctrllocktorefclkout(wire_receive_pcs7_cdrctrllocktorefclkout),
.clkout(),
.coreclk(rx_coreclk_in[7]),
.coreclkout(wire_receive_pcs7_coreclkout),
.ctrldetect(wire_receive_pcs7_ctrldetect),
.datain(rx_pma_recoverdataout_wire[159:140]),
.dataout(wire_receive_pcs7_dataout),
.dataoutfull(),
.digitalreset(rx_digitalreset_out[7]),
.digitaltestout(),
.disablefifordin(1'b0),
.disablefifordout(),
.disablefifowrin(1'b0),
.disablefifowrout(),
.disperr(),
.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
.dprioin(rx_pcsdprioin_wire[3199:2800]),
.dprioout(wire_receive_pcs7_dprioout),
.elecidleinfersel({3{1'b0}}),
.enabledeskew(1'b0),
.enabyteord(1'b0),
.enapatternalign(rx_enapatternalign[7]),
.errdetect(),
.fifordin(1'b0),
.fifordout(),
.fiforesetrd(1'b0),
.grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[23:21]),
.hipdataout(),
.hipdatavalid(),
.hipelecidle(),
.hipphydonestatus(),
.hipstatus(),
.invpol(1'b0),
.iqpautospdxnspgchg(int_rx_iqpautospdxnspgchg[15:14]),
.iqpphfifobyteselout(wire_receive_pcs7_iqpphfifobyteselout),
.iqpphfifoptrsresetout(wire_receive_pcs7_iqpphfifoptrsresetout),
.iqpphfifordenableout(wire_receive_pcs7_iqpphfifordenableout),
.iqpphfifowrclkout(wire_receive_pcs7_iqpphfifowrclkout),
.iqpphfifowrenableout(wire_receive_pcs7_iqpphfifowrenableout),
.iqpphfifoxnbytesel(int_rx_iqpphfifoxnbytesel[15:14]),
.iqpphfifoxnptrsreset(int_rx_iqpphfifoxnptrsreset[15:14]),
.iqpphfifoxnrdenable(int_rx_iqpphfifoxnrdenable[15:14]),
.iqpphfifoxnwrclk(int_rx_iqpphfifoxnwrclk[15:14]),
.iqpphfifoxnwrenable(int_rx_iqpphfifoxnwrenable[15:14]),
.k1detect(),
.k2detect(),
.localrefclk(1'b0),
.masterclk(1'b0),
.parallelfdbk({20{1'b0}}),
.patterndetect(wire_receive_pcs7_patterndetect),
.phfifobyteselout(),
.phfifobyteserdisableout(wire_receive_pcs7_phfifobyteserdisableout),
.phfifooverflow(),
.phfifoptrsresetout(wire_receive_pcs7_phfifoptrsresetout),
.phfifordenable(rx_phfifordenable[7]),
.phfifordenableout(wire_receive_pcs7_phfifordenableout),
.phfiforeset(rx_phfiforeset[7]),
.phfiforesetout(wire_receive_pcs7_phfiforesetout),
.phfifounderflow(),
.phfifowrclkout(),
.phfifowrdisable(rx_phfifowrdisable[7]),
.phfifowrdisableout(wire_receive_pcs7_phfifowrdisableout),
.phfifowrenableout(),
.phfifoxnbytesel(int_rx_phfifoxnbytesel[23:21]),
.phfifoxnptrsreset(int_rx_phfifioxnptrsreset[23:21]),
.phfifoxnrdenable(int_rx_phfifoxnrdenable[23:21]),
.phfifoxnwrclk(int_rx_phfifoxnwrclk[23:21]),
.phfifoxnwrenable(int_rx_phfifoxnwrenable[23:21]),
.pipe8b10binvpolarity(pipe8b10binvpolarity[7]),
.pipebufferstat(),
.pipedatavalid(wire_receive_pcs7_pipedatavalid),
.pipeelecidle(wire_receive_pcs7_pipeelecidle),
.pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[7]),
.pipephydonestatus(wire_receive_pcs7_pipephydonestatus),
.pipepowerdown(tx_pipepowerdownout[15:14]),
.pipepowerstate(tx_pipepowerstateout[31:28]),
.pipestatetransdoneout(wire_receive_pcs7_pipestatetransdoneout),
.pipestatus(wire_receive_pcs7_pipestatus),
.powerdn(powerdn[15:14]),
.prbscidenable(rx_prbscidenable[7]),
.quadreset(cent_unit_quadresetout[1]),
.rateswitch(rateswitch[0]),
.rateswitchout(wire_receive_pcs7_rateswitchout),
.rateswitchxndone(int_hiprateswtichdone[1]),
.rdalign(),
.recoveredclk(rx_pma_clockout[7]),
.refclk(refclk_pma[1]),
.revbitorderwa(1'b0),
.revbyteorderwa(1'b0),
.revparallelfdbkdata(wire_receive_pcs7_revparallelfdbkdata),
.rlv(),
.rmfifoalmostempty(),
.rmfifoalmostfull(),
.rmfifodatadeleted(),
.rmfifodatainserted(),
.rmfifoempty(),
.rmfifofull(),
.rmfifordena(1'b0),
.rmfiforeset(rx_rmfiforeset[7]),
.rmfifowrena(1'b0),
.runningdisp(),
.rxdetectvalid(tx_rxdetectvalidout[7]),
.rxfound(rx_pcs_rxfound_wire[15:14]),
.signaldetect(wire_receive_pcs7_signaldetect),
.signaldetected(rx_signaldetect_wire[7]),
.syncstatus(wire_receive_pcs7_syncstatus),
.syncstatusdeskew(),
.xauidelcondmetout(),
.xauififoovrout(),
.xauiinsertincompleteout(),
.xauilatencycompout(),
.xgmctrldet(),
.xgmctrlin(1'b0),
.xgmdatain({8{1'b0}}),
.xgmdataout(),
.xgmdatavalid(),
.xgmrunningdisp()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslip(1'b0),
.cdrctrllocktorefcl(1'b0),
.hip8b10binvpolarity(1'b0),
.hipelecidleinfersel({3{1'b0}}),
.hippowerdown({2{1'b0}}),
.hiprateswitch(1'b0),
.phfifox4bytesel(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrclk(1'b0),
.phfifox4wrenable(1'b0),
.phfifox8bytesel(1'b0),
.phfifox8rdenable(1'b0),
.phfifox8wrclk(1'b0),
.phfifox8wrenable(1'b0),
.pmatestbusin({8{1'b0}}),
.ppmdetectdividedclk(1'b0),
.ppmdetectrefclk(1'b0),
.rateswitchisdone(1'b0),
.rxelecidlerateswitch(1'b0),
.wareset(1'b0),
.xauidelcondmet(1'b0),
.xauififoovr(1'b0),
.xauiinsertincomplete(1'b0),
.xauilatencycomp(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pcs7.align_pattern = "0101111100",
receive_pcs7.align_pattern_length = 10,
receive_pcs7.align_to_deskew_pattern_pos_disp_only = "false",
receive_pcs7.allow_align_polarity_inversion = "false",
receive_pcs7.allow_pipe_polarity_inversion = "true",
receive_pcs7.auto_spd_deassert_ph_fifo_rst_count = 8,
receive_pcs7.auto_spd_phystatus_notify_count = 14,
receive_pcs7.auto_spd_self_switch_enable = "true",
receive_pcs7.bit_slip_enable = "false",
receive_pcs7.byte_order_double_data_mode_mask_enable = "false",
receive_pcs7.byte_order_invalid_code_or_run_disp_error = "true",
receive_pcs7.byte_order_mode = "none",
receive_pcs7.byte_order_pad_pattern = "0",
receive_pcs7.byte_order_pattern = "0",
receive_pcs7.byte_order_pld_ctrl_enable = "false",
receive_pcs7.cdrctrl_bypass_ppm_detector_cycle = 1000,
receive_pcs7.cdrctrl_cid_mode_enable = "true",
receive_pcs7.cdrctrl_enable = "true",
receive_pcs7.cdrctrl_rxvalid_mask = "true",
receive_pcs7.channel_bonding = "x8",
receive_pcs7.channel_number = ((starting_channel_number + 7) % 4),
receive_pcs7.channel_width = 16,
receive_pcs7.clk1_mux_select = "recovered clock",
receive_pcs7.clk2_mux_select = "digital reference clock",
receive_pcs7.core_clock_0ppm = "false",
receive_pcs7.datapath_low_latency_mode = "false",
receive_pcs7.datapath_protocol = "pipe",
receive_pcs7.dec_8b_10b_compatibility_mode = "true",
receive_pcs7.dec_8b_10b_mode = "normal",
receive_pcs7.dec_8b_10b_polarity_inv_enable = "true",
receive_pcs7.deskew_pattern = "0",
receive_pcs7.disable_auto_idle_insertion = "false",
receive_pcs7.disable_running_disp_in_word_align = "false",
receive_pcs7.disallow_kchar_after_pattern_ordered_set = "false",
receive_pcs7.dprio_config_mode = 6'h01,
receive_pcs7.elec_idle_gen1_sigdet_enable = "true",
receive_pcs7.elec_idle_infer_enable = "false",
receive_pcs7.elec_idle_num_com_detect = 3,
receive_pcs7.enable_bit_reversal = "false",
receive_pcs7.enable_deep_align = "false",
receive_pcs7.enable_deep_align_byte_swap = "false",
receive_pcs7.enable_self_test_mode = "false",
receive_pcs7.enable_true_complement_match_in_word_align = "false",
receive_pcs7.force_signal_detect_dig = "true",
receive_pcs7.hip_enable = "false",
receive_pcs7.infiniband_invalid_code = 0,
receive_pcs7.insert_pad_on_underflow = "false",
receive_pcs7.logical_channel_address = (starting_channel_number + 7),
receive_pcs7.num_align_code_groups_in_ordered_set = 0,
receive_pcs7.num_align_cons_good_data = 16,
receive_pcs7.num_align_cons_pat = 4,
receive_pcs7.num_align_loss_sync_error = 17,
receive_pcs7.ph_fifo_low_latency_enable = "true",
receive_pcs7.ph_fifo_reg_mode = "false",
receive_pcs7.ph_fifo_xn_mapping0 = "none",
receive_pcs7.ph_fifo_xn_mapping1 = "up",
receive_pcs7.ph_fifo_xn_mapping2 = "none",
receive_pcs7.ph_fifo_xn_select = 1,
receive_pcs7.pipe_auto_speed_nego_enable = "true",
receive_pcs7.pipe_freq_scale_mode = "Frequency",
receive_pcs7.pma_done_count = 249950,
receive_pcs7.protocol_hint = "pcie2",
receive_pcs7.rate_match_almost_empty_threshold = 11,
receive_pcs7.rate_match_almost_full_threshold = 13,
receive_pcs7.rate_match_back_to_back = "false",
receive_pcs7.rate_match_delete_threshold = 13,
receive_pcs7.rate_match_empty_threshold = 5,
receive_pcs7.rate_match_fifo_mode = "true",
receive_pcs7.rate_match_full_threshold = 20,
receive_pcs7.rate_match_insert_threshold = 11,
receive_pcs7.rate_match_ordered_set_based = "false",
receive_pcs7.rate_match_pattern1 = "11010000111010000011",
receive_pcs7.rate_match_pattern2 = "00101111000101111100",
receive_pcs7.rate_match_pattern_size = 20,
receive_pcs7.rate_match_pipe_enable = "true",
receive_pcs7.rate_match_reset_enable = "false",
receive_pcs7.rate_match_skip_set_based = "true",
receive_pcs7.rate_match_start_threshold = 7,
receive_pcs7.rd_clk_mux_select = "core clock",
receive_pcs7.recovered_clk_mux_select = "recovered clock",
receive_pcs7.run_length = 40,
receive_pcs7.run_length_enable = "true",
receive_pcs7.rx_detect_bypass = "false",
receive_pcs7.rx_phfifo_wait_cnt = 32,
receive_pcs7.rxstatus_error_report_mode = 1,
receive_pcs7.self_test_mode = "incremental",
receive_pcs7.use_alignment_state_machine = "true",
receive_pcs7.use_deserializer_double_data_mode = "false",
receive_pcs7.use_deskew_fifo = "false",
receive_pcs7.use_double_data_mode = "true",
receive_pcs7.use_parallel_loopback = "false",
receive_pcs7.use_rising_edge_triggered_pattern_align = "false",
receive_pcs7.lpm_type = "stratixiv_hssi_rx_pcs";
stratixiv_hssi_rx_pma receive_pma0
(
.adaptdone(),
.analogtestbus(wire_receive_pma0_analogtestbus),
.clockout(wire_receive_pma0_clockout),
.datain(rx_datain[0]),
.dataout(wire_receive_pma0_dataout),
.dataoutfull(),
.deserclock(rx_deserclock_in[3:0]),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pmadprioin_wire[299:0]),
.dprioout(wire_receive_pma0_dprioout),
.freqlock(1'b0),
.ignorephslck(1'b0),
.locktodata(rx_locktodata_wire[0]),
.locktoref(rx_locktorefclk_wire[0]),
.locktorefout(wire_receive_pma0_locktorefout),
.offsetcancellationen(1'b0),
.plllocked(rx_plllocked_wire[0]),
.powerdn(cent_unit_rxibpowerdn[0]),
.ppmdetectclkrel(),
.ppmdetectrefclk(rx_pll_pfdrefclkout_wire[0]),
.recoverdatain(pll_ch_dataout_wire[1:0]),
.recoverdataout(wire_receive_pma0_recoverdataout),
.reverselpbkout(),
.revserialfdbkout(),
.rxpmareset(rx_analogreset_out[0]),
.seriallpbken(1'b0),
.seriallpbkin(1'b0),
.signaldetect(wire_receive_pma0_signaldetect),
.testbussel(4'b0110)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.adaptcapture(1'b0),
.adcepowerdn(1'b0),
.adcereset(1'b0),
.adcestandby(1'b0),
.extra10gin({38{1'b0}}),
.ppmdetectdividedclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pma0.adaptive_equalization_mode = "none",
receive_pma0.allow_serial_loopback = "false",
receive_pma0.channel_number = ((starting_channel_number + 0) % 4),
receive_pma0.channel_type = "auto",
receive_pma0.common_mode = "0.82V",
receive_pma0.deserialization_factor = 10,
receive_pma0.dprio_config_mode = 6'h01,
receive_pma0.enable_ltd = "false",
receive_pma0.enable_ltr = "true",
receive_pma0.eq_dc_gain = 3,
receive_pma0.eqa_ctrl = 0,
receive_pma0.eqb_ctrl = 0,
receive_pma0.eqc_ctrl = 0,
receive_pma0.eqd_ctrl = 0,
receive_pma0.eqv_ctrl = 0,
receive_pma0.eyemon_bandwidth = 0,
receive_pma0.force_signal_detect = "true",
receive_pma0.logical_channel_address = (starting_channel_number + 0),
receive_pma0.low_speed_test_select = 0,
receive_pma0.offset_cancellation = 1,
receive_pma0.ppmselect = 32,
receive_pma0.protocol_hint = "pcie2",
receive_pma0.send_direct_reverse_serial_loopback = "None",
receive_pma0.signal_detect_hysteresis = 4,
receive_pma0.signal_detect_hysteresis_valid_threshold = 14,
receive_pma0.signal_detect_loss_threshold = 3,
receive_pma0.termination = "OCT 100 Ohms",
receive_pma0.use_deser_double_data_width = "false",
receive_pma0.use_external_termination = "false",
receive_pma0.use_pma_direct = "false",
receive_pma0.lpm_type = "stratixiv_hssi_rx_pma";
stratixiv_hssi_rx_pma receive_pma1
(
.adaptdone(),
.analogtestbus(wire_receive_pma1_analogtestbus),
.clockout(wire_receive_pma1_clockout),
.datain(rx_datain[1]),
.dataout(wire_receive_pma1_dataout),
.dataoutfull(),
.deserclock(rx_deserclock_in[7:4]),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pmadprioin_wire[599:300]),
.dprioout(wire_receive_pma1_dprioout),
.freqlock(1'b0),
.ignorephslck(1'b0),
.locktodata(rx_locktodata_wire[1]),
.locktoref(rx_locktorefclk_wire[1]),
.locktorefout(wire_receive_pma1_locktorefout),
.offsetcancellationen(1'b0),
.plllocked(rx_plllocked_wire[1]),
.powerdn(cent_unit_rxibpowerdn[1]),
.ppmdetectclkrel(),
.ppmdetectrefclk(rx_pll_pfdrefclkout_wire[1]),
.recoverdatain(pll_ch_dataout_wire[3:2]),
.recoverdataout(wire_receive_pma1_recoverdataout),
.reverselpbkout(),
.revserialfdbkout(),
.rxpmareset(rx_analogreset_out[1]),
.seriallpbken(1'b0),
.seriallpbkin(1'b0),
.signaldetect(wire_receive_pma1_signaldetect),
.testbussel(4'b0110)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.adaptcapture(1'b0),
.adcepowerdn(1'b0),
.adcereset(1'b0),
.adcestandby(1'b0),
.extra10gin({38{1'b0}}),
.ppmdetectdividedclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pma1.adaptive_equalization_mode = "none",
receive_pma1.allow_serial_loopback = "false",
receive_pma1.channel_number = ((starting_channel_number + 1) % 4),
receive_pma1.channel_type = "auto",
receive_pma1.common_mode = "0.82V",
receive_pma1.deserialization_factor = 10,
receive_pma1.dprio_config_mode = 6'h01,
receive_pma1.enable_ltd = "false",
receive_pma1.enable_ltr = "true",
receive_pma1.eq_dc_gain = 3,
receive_pma1.eqa_ctrl = 0,
receive_pma1.eqb_ctrl = 0,
receive_pma1.eqc_ctrl = 0,
receive_pma1.eqd_ctrl = 0,
receive_pma1.eqv_ctrl = 0,
receive_pma1.eyemon_bandwidth = 0,
receive_pma1.force_signal_detect = "true",
receive_pma1.logical_channel_address = (starting_channel_number + 1),
receive_pma1.low_speed_test_select = 0,
receive_pma1.offset_cancellation = 1,
receive_pma1.ppmselect = 32,
receive_pma1.protocol_hint = "pcie2",
receive_pma1.send_direct_reverse_serial_loopback = "None",
receive_pma1.signal_detect_hysteresis = 4,
receive_pma1.signal_detect_hysteresis_valid_threshold = 14,
receive_pma1.signal_detect_loss_threshold = 3,
receive_pma1.termination = "OCT 100 Ohms",
receive_pma1.use_deser_double_data_width = "false",
receive_pma1.use_external_termination = "false",
receive_pma1.use_pma_direct = "false",
receive_pma1.lpm_type = "stratixiv_hssi_rx_pma";
stratixiv_hssi_rx_pma receive_pma2
(
.adaptdone(),
.analogtestbus(wire_receive_pma2_analogtestbus),
.clockout(wire_receive_pma2_clockout),
.datain(rx_datain[2]),
.dataout(wire_receive_pma2_dataout),
.dataoutfull(),
.deserclock(rx_deserclock_in[11:8]),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pmadprioin_wire[899:600]),
.dprioout(wire_receive_pma2_dprioout),
.freqlock(1'b0),
.ignorephslck(1'b0),
.locktodata(rx_locktodata_wire[2]),
.locktoref(rx_locktorefclk_wire[2]),
.locktorefout(wire_receive_pma2_locktorefout),
.offsetcancellationen(1'b0),
.plllocked(rx_plllocked_wire[2]),
.powerdn(cent_unit_rxibpowerdn[2]),
.ppmdetectclkrel(),
.ppmdetectrefclk(rx_pll_pfdrefclkout_wire[2]),
.recoverdatain(pll_ch_dataout_wire[5:4]),
.recoverdataout(wire_receive_pma2_recoverdataout),
.reverselpbkout(),
.revserialfdbkout(),
.rxpmareset(rx_analogreset_out[2]),
.seriallpbken(1'b0),
.seriallpbkin(1'b0),
.signaldetect(wire_receive_pma2_signaldetect),
.testbussel(4'b0110)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.adaptcapture(1'b0),
.adcepowerdn(1'b0),
.adcereset(1'b0),
.adcestandby(1'b0),
.extra10gin({38{1'b0}}),
.ppmdetectdividedclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pma2.adaptive_equalization_mode = "none",
receive_pma2.allow_serial_loopback = "false",
receive_pma2.channel_number = ((starting_channel_number + 2) % 4),
receive_pma2.channel_type = "auto",
receive_pma2.common_mode = "0.82V",
receive_pma2.deserialization_factor = 10,
receive_pma2.dprio_config_mode = 6'h01,
receive_pma2.enable_ltd = "false",
receive_pma2.enable_ltr = "true",
receive_pma2.eq_dc_gain = 3,
receive_pma2.eqa_ctrl = 0,
receive_pma2.eqb_ctrl = 0,
receive_pma2.eqc_ctrl = 0,
receive_pma2.eqd_ctrl = 0,
receive_pma2.eqv_ctrl = 0,
receive_pma2.eyemon_bandwidth = 0,
receive_pma2.force_signal_detect = "true",
receive_pma2.logical_channel_address = (starting_channel_number + 2),
receive_pma2.low_speed_test_select = 0,
receive_pma2.offset_cancellation = 1,
receive_pma2.ppmselect = 32,
receive_pma2.protocol_hint = "pcie2",
receive_pma2.send_direct_reverse_serial_loopback = "None",
receive_pma2.signal_detect_hysteresis = 4,
receive_pma2.signal_detect_hysteresis_valid_threshold = 14,
receive_pma2.signal_detect_loss_threshold = 3,
receive_pma2.termination = "OCT 100 Ohms",
receive_pma2.use_deser_double_data_width = "false",
receive_pma2.use_external_termination = "false",
receive_pma2.use_pma_direct = "false",
receive_pma2.lpm_type = "stratixiv_hssi_rx_pma";
stratixiv_hssi_rx_pma receive_pma3
(
.adaptdone(),
.analogtestbus(wire_receive_pma3_analogtestbus),
.clockout(wire_receive_pma3_clockout),
.datain(rx_datain[3]),
.dataout(wire_receive_pma3_dataout),
.dataoutfull(),
.deserclock(rx_deserclock_in[15:12]),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pmadprioin_wire[1199:900]),
.dprioout(wire_receive_pma3_dprioout),
.freqlock(1'b0),
.ignorephslck(1'b0),
.locktodata(rx_locktodata_wire[3]),
.locktoref(rx_locktorefclk_wire[3]),
.locktorefout(wire_receive_pma3_locktorefout),
.offsetcancellationen(1'b0),
.plllocked(rx_plllocked_wire[3]),
.powerdn(cent_unit_rxibpowerdn[3]),
.ppmdetectclkrel(),
.ppmdetectrefclk(rx_pll_pfdrefclkout_wire[3]),
.recoverdatain(pll_ch_dataout_wire[7:6]),
.recoverdataout(wire_receive_pma3_recoverdataout),
.reverselpbkout(),
.revserialfdbkout(),
.rxpmareset(rx_analogreset_out[3]),
.seriallpbken(1'b0),
.seriallpbkin(1'b0),
.signaldetect(wire_receive_pma3_signaldetect),
.testbussel(4'b0110)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.adaptcapture(1'b0),
.adcepowerdn(1'b0),
.adcereset(1'b0),
.adcestandby(1'b0),
.extra10gin({38{1'b0}}),
.ppmdetectdividedclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pma3.adaptive_equalization_mode = "none",
receive_pma3.allow_serial_loopback = "false",
receive_pma3.channel_number = ((starting_channel_number + 3) % 4),
receive_pma3.channel_type = "auto",
receive_pma3.common_mode = "0.82V",
receive_pma3.deserialization_factor = 10,
receive_pma3.dprio_config_mode = 6'h01,
receive_pma3.enable_ltd = "false",
receive_pma3.enable_ltr = "true",
receive_pma3.eq_dc_gain = 3,
receive_pma3.eqa_ctrl = 0,
receive_pma3.eqb_ctrl = 0,
receive_pma3.eqc_ctrl = 0,
receive_pma3.eqd_ctrl = 0,
receive_pma3.eqv_ctrl = 0,
receive_pma3.eyemon_bandwidth = 0,
receive_pma3.force_signal_detect = "true",
receive_pma3.logical_channel_address = (starting_channel_number + 3),
receive_pma3.low_speed_test_select = 0,
receive_pma3.offset_cancellation = 1,
receive_pma3.ppmselect = 32,
receive_pma3.protocol_hint = "pcie2",
receive_pma3.send_direct_reverse_serial_loopback = "None",
receive_pma3.signal_detect_hysteresis = 4,
receive_pma3.signal_detect_hysteresis_valid_threshold = 14,
receive_pma3.signal_detect_loss_threshold = 3,
receive_pma3.termination = "OCT 100 Ohms",
receive_pma3.use_deser_double_data_width = "false",
receive_pma3.use_external_termination = "false",
receive_pma3.use_pma_direct = "false",
receive_pma3.lpm_type = "stratixiv_hssi_rx_pma";
stratixiv_hssi_rx_pma receive_pma4
(
.adaptdone(),
.analogtestbus(wire_receive_pma4_analogtestbus),
.clockout(wire_receive_pma4_clockout),
.datain(rx_datain[4]),
.dataout(wire_receive_pma4_dataout),
.dataoutfull(),
.deserclock(rx_deserclock_in[19:16]),
.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
.dprioin(rx_pmadprioin_wire[2099:1800]),
.dprioout(wire_receive_pma4_dprioout),
.freqlock(1'b0),
.ignorephslck(1'b0),
.locktodata(rx_locktodata_wire[4]),
.locktoref(rx_locktorefclk_wire[4]),
.locktorefout(wire_receive_pma4_locktorefout),
.offsetcancellationen(1'b0),
.plllocked(rx_plllocked_wire[4]),
.powerdn(cent_unit_rxibpowerdn[6]),
.ppmdetectclkrel(),
.ppmdetectrefclk(rx_pll_pfdrefclkout_wire[4]),
.recoverdatain(pll_ch_dataout_wire[9:8]),
.recoverdataout(wire_receive_pma4_recoverdataout),
.reverselpbkout(),
.revserialfdbkout(),
.rxpmareset(rx_analogreset_out[6]),
.seriallpbken(1'b0),
.seriallpbkin(1'b0),
.signaldetect(wire_receive_pma4_signaldetect),
.testbussel(4'b0110)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.adaptcapture(1'b0),
.adcepowerdn(1'b0),
.adcereset(1'b0),
.adcestandby(1'b0),
.extra10gin({38{1'b0}}),
.ppmdetectdividedclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pma4.adaptive_equalization_mode = "none",
receive_pma4.allow_serial_loopback = "false",
receive_pma4.channel_number = ((starting_channel_number + 4) % 4),
receive_pma4.channel_type = "auto",
receive_pma4.common_mode = "0.82V",
receive_pma4.deserialization_factor = 10,
receive_pma4.dprio_config_mode = 6'h01,
receive_pma4.enable_ltd = "false",
receive_pma4.enable_ltr = "true",
receive_pma4.eq_dc_gain = 3,
receive_pma4.eqa_ctrl = 0,
receive_pma4.eqb_ctrl = 0,
receive_pma4.eqc_ctrl = 0,
receive_pma4.eqd_ctrl = 0,
receive_pma4.eqv_ctrl = 0,
receive_pma4.eyemon_bandwidth = 0,
receive_pma4.force_signal_detect = "true",
receive_pma4.logical_channel_address = (starting_channel_number + 4),
receive_pma4.low_speed_test_select = 0,
receive_pma4.offset_cancellation = 1,
receive_pma4.ppmselect = 32,
receive_pma4.protocol_hint = "pcie2",
receive_pma4.send_direct_reverse_serial_loopback = "None",
receive_pma4.signal_detect_hysteresis = 4,
receive_pma4.signal_detect_hysteresis_valid_threshold = 14,
receive_pma4.signal_detect_loss_threshold = 3,
receive_pma4.termination = "OCT 100 Ohms",
receive_pma4.use_deser_double_data_width = "false",
receive_pma4.use_external_termination = "false",
receive_pma4.use_pma_direct = "false",
receive_pma4.lpm_type = "stratixiv_hssi_rx_pma";
stratixiv_hssi_rx_pma receive_pma5
(
.adaptdone(),
.analogtestbus(wire_receive_pma5_analogtestbus),
.clockout(wire_receive_pma5_clockout),
.datain(rx_datain[5]),
.dataout(wire_receive_pma5_dataout),
.dataoutfull(),
.deserclock(rx_deserclock_in[23:20]),
.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
.dprioin(rx_pmadprioin_wire[2399:2100]),
.dprioout(wire_receive_pma5_dprioout),
.freqlock(1'b0),
.ignorephslck(1'b0),
.locktodata(rx_locktodata_wire[5]),
.locktoref(rx_locktorefclk_wire[5]),
.locktorefout(wire_receive_pma5_locktorefout),
.offsetcancellationen(1'b0),
.plllocked(rx_plllocked_wire[5]),
.powerdn(cent_unit_rxibpowerdn[7]),
.ppmdetectclkrel(),
.ppmdetectrefclk(rx_pll_pfdrefclkout_wire[5]),
.recoverdatain(pll_ch_dataout_wire[11:10]),
.recoverdataout(wire_receive_pma5_recoverdataout),
.reverselpbkout(),
.revserialfdbkout(),
.rxpmareset(rx_analogreset_out[7]),
.seriallpbken(1'b0),
.seriallpbkin(1'b0),
.signaldetect(wire_receive_pma5_signaldetect),
.testbussel(4'b0110)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.adaptcapture(1'b0),
.adcepowerdn(1'b0),
.adcereset(1'b0),
.adcestandby(1'b0),
.extra10gin({38{1'b0}}),
.ppmdetectdividedclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pma5.adaptive_equalization_mode = "none",
receive_pma5.allow_serial_loopback = "false",
receive_pma5.channel_number = ((starting_channel_number + 5) % 4),
receive_pma5.channel_type = "auto",
receive_pma5.common_mode = "0.82V",
receive_pma5.deserialization_factor = 10,
receive_pma5.dprio_config_mode = 6'h01,
receive_pma5.enable_ltd = "false",
receive_pma5.enable_ltr = "true",
receive_pma5.eq_dc_gain = 3,
receive_pma5.eqa_ctrl = 0,
receive_pma5.eqb_ctrl = 0,
receive_pma5.eqc_ctrl = 0,
receive_pma5.eqd_ctrl = 0,
receive_pma5.eqv_ctrl = 0,
receive_pma5.eyemon_bandwidth = 0,
receive_pma5.force_signal_detect = "true",
receive_pma5.logical_channel_address = (starting_channel_number + 5),
receive_pma5.low_speed_test_select = 0,
receive_pma5.offset_cancellation = 1,
receive_pma5.ppmselect = 32,
receive_pma5.protocol_hint = "pcie2",
receive_pma5.send_direct_reverse_serial_loopback = "None",
receive_pma5.signal_detect_hysteresis = 4,
receive_pma5.signal_detect_hysteresis_valid_threshold = 14,
receive_pma5.signal_detect_loss_threshold = 3,
receive_pma5.termination = "OCT 100 Ohms",
receive_pma5.use_deser_double_data_width = "false",
receive_pma5.use_external_termination = "false",
receive_pma5.use_pma_direct = "false",
receive_pma5.lpm_type = "stratixiv_hssi_rx_pma";
stratixiv_hssi_rx_pma receive_pma6
(
.adaptdone(),
.analogtestbus(wire_receive_pma6_analogtestbus),
.clockout(wire_receive_pma6_clockout),
.datain(rx_datain[6]),
.dataout(wire_receive_pma6_dataout),
.dataoutfull(),
.deserclock(rx_deserclock_in[27:24]),
.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
.dprioin(rx_pmadprioin_wire[2699:2400]),
.dprioout(wire_receive_pma6_dprioout),
.freqlock(1'b0),
.ignorephslck(1'b0),
.locktodata(rx_locktodata_wire[6]),
.locktoref(rx_locktorefclk_wire[6]),
.locktorefout(wire_receive_pma6_locktorefout),
.offsetcancellationen(1'b0),
.plllocked(rx_plllocked_wire[6]),
.powerdn(cent_unit_rxibpowerdn[8]),
.ppmdetectclkrel(),
.ppmdetectrefclk(rx_pll_pfdrefclkout_wire[6]),
.recoverdatain(pll_ch_dataout_wire[13:12]),
.recoverdataout(wire_receive_pma6_recoverdataout),
.reverselpbkout(),
.revserialfdbkout(),
.rxpmareset(rx_analogreset_out[8]),
.seriallpbken(1'b0),
.seriallpbkin(1'b0),
.signaldetect(wire_receive_pma6_signaldetect),
.testbussel(4'b0110)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.adaptcapture(1'b0),
.adcepowerdn(1'b0),
.adcereset(1'b0),
.adcestandby(1'b0),
.extra10gin({38{1'b0}}),
.ppmdetectdividedclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pma6.adaptive_equalization_mode = "none",
receive_pma6.allow_serial_loopback = "false",
receive_pma6.channel_number = ((starting_channel_number + 6) % 4),
receive_pma6.channel_type = "auto",
receive_pma6.common_mode = "0.82V",
receive_pma6.deserialization_factor = 10,
receive_pma6.dprio_config_mode = 6'h01,
receive_pma6.enable_ltd = "false",
receive_pma6.enable_ltr = "true",
receive_pma6.eq_dc_gain = 3,
receive_pma6.eqa_ctrl = 0,
receive_pma6.eqb_ctrl = 0,
receive_pma6.eqc_ctrl = 0,
receive_pma6.eqd_ctrl = 0,
receive_pma6.eqv_ctrl = 0,
receive_pma6.eyemon_bandwidth = 0,
receive_pma6.force_signal_detect = "true",
receive_pma6.logical_channel_address = (starting_channel_number + 6),
receive_pma6.low_speed_test_select = 0,
receive_pma6.offset_cancellation = 1,
receive_pma6.ppmselect = 32,
receive_pma6.protocol_hint = "pcie2",
receive_pma6.send_direct_reverse_serial_loopback = "None",
receive_pma6.signal_detect_hysteresis = 4,
receive_pma6.signal_detect_hysteresis_valid_threshold = 14,
receive_pma6.signal_detect_loss_threshold = 3,
receive_pma6.termination = "OCT 100 Ohms",
receive_pma6.use_deser_double_data_width = "false",
receive_pma6.use_external_termination = "false",
receive_pma6.use_pma_direct = "false",
receive_pma6.lpm_type = "stratixiv_hssi_rx_pma";
stratixiv_hssi_rx_pma receive_pma7
(
.adaptdone(),
.analogtestbus(wire_receive_pma7_analogtestbus),
.clockout(wire_receive_pma7_clockout),
.datain(rx_datain[7]),
.dataout(wire_receive_pma7_dataout),
.dataoutfull(),
.deserclock(rx_deserclock_in[31:28]),
.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
.dprioin(rx_pmadprioin_wire[2999:2700]),
.dprioout(wire_receive_pma7_dprioout),
.freqlock(1'b0),
.ignorephslck(1'b0),
.locktodata(rx_locktodata_wire[7]),
.locktoref(rx_locktorefclk_wire[7]),
.locktorefout(wire_receive_pma7_locktorefout),
.offsetcancellationen(1'b0),
.plllocked(rx_plllocked_wire[7]),
.powerdn(cent_unit_rxibpowerdn[9]),
.ppmdetectclkrel(),
.ppmdetectrefclk(rx_pll_pfdrefclkout_wire[7]),
.recoverdatain(pll_ch_dataout_wire[15:14]),
.recoverdataout(wire_receive_pma7_recoverdataout),
.reverselpbkout(),
.revserialfdbkout(),
.rxpmareset(rx_analogreset_out[9]),
.seriallpbken(1'b0),
.seriallpbkin(1'b0),
.signaldetect(wire_receive_pma7_signaldetect),
.testbussel(4'b0110)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.adaptcapture(1'b0),
.adcepowerdn(1'b0),
.adcereset(1'b0),
.adcestandby(1'b0),
.extra10gin({38{1'b0}}),
.ppmdetectdividedclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pma7.adaptive_equalization_mode = "none",
receive_pma7.allow_serial_loopback = "false",
receive_pma7.channel_number = ((starting_channel_number + 7) % 4),
receive_pma7.channel_type = "auto",
receive_pma7.common_mode = "0.82V",
receive_pma7.deserialization_factor = 10,
receive_pma7.dprio_config_mode = 6'h01,
receive_pma7.enable_ltd = "false",
receive_pma7.enable_ltr = "true",
receive_pma7.eq_dc_gain = 3,
receive_pma7.eqa_ctrl = 0,
receive_pma7.eqb_ctrl = 0,
receive_pma7.eqc_ctrl = 0,
receive_pma7.eqd_ctrl = 0,
receive_pma7.eqv_ctrl = 0,
receive_pma7.eyemon_bandwidth = 0,
receive_pma7.force_signal_detect = "true",
receive_pma7.logical_channel_address = (starting_channel_number + 7),
receive_pma7.low_speed_test_select = 0,
receive_pma7.offset_cancellation = 1,
receive_pma7.ppmselect = 32,
receive_pma7.protocol_hint = "pcie2",
receive_pma7.send_direct_reverse_serial_loopback = "None",
receive_pma7.signal_detect_hysteresis = 4,
receive_pma7.signal_detect_hysteresis_valid_threshold = 14,
receive_pma7.signal_detect_loss_threshold = 3,
receive_pma7.termination = "OCT 100 Ohms",
receive_pma7.use_deser_double_data_width = "false",
receive_pma7.use_external_termination = "false",
receive_pma7.use_pma_direct = "false",
receive_pma7.lpm_type = "stratixiv_hssi_rx_pma";
stratixiv_hssi_tx_pcs transmit_pcs0
(
.clkout(),
.coreclk(tx_coreclk_in[0]),
.coreclkout(wire_transmit_pcs0_coreclkout),
.ctrlenable({{2{1'b0}}, tx_ctrlenable[1:0]}),
.datain({{24{1'b0}}, tx_datain_wire[15:0]}),
.dataout(wire_transmit_pcs0_dataout),
.detectrxloop(tx_detectrxloop[0]),
.digitalreset(tx_digitalreset_out[0]),
.dispval({{2{1'b0}}, {2{tx_forceelecidle[0]}}}),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_dprioin_wire[149:0]),
.dprioout(wire_transmit_pcs0_dprioout),
.elecidleinfersel(rx_elecidleinfersel[2:0]),
.enrevparallellpbk(tx_revparallellpbken[0]),
.forcedisp({{2{1'b0}}, tx_forcedisp_wire[1:0]}),
.forcedispcompliance(1'b0),
.forceelecidle(tx_forceelecidle[0]),
.forceelecidleout(wire_transmit_pcs0_forceelecidleout),
.grayelecidleinferselout(wire_transmit_pcs0_grayelecidleinferselout),
.hiptxclkout(),
.invpol(tx_invpolarity[0]),
.iqpphfifobyteselout(wire_transmit_pcs0_iqpphfifobyteselout),
.iqpphfifordclkout(wire_transmit_pcs0_iqpphfifordclkout),
.iqpphfifordenableout(wire_transmit_pcs0_iqpphfifordenableout),
.iqpphfifowrenableout(wire_transmit_pcs0_iqpphfifowrenableout),
.iqpphfifoxnbytesel(int_tx_iqpphfifoxnbytesel[1:0]),
.iqpphfifoxnrdclk(int_tx_iqpphfifoxnrdclk[1:0]),
.iqpphfifoxnrdenable(int_tx_iqpphfifoxnrdenable[1:0]),
.iqpphfifoxnwrenable(int_tx_iqpphfifoxnwrenable[1:0]),
.localrefclk(tx_localrefclk[0]),
.parallelfdbkout(),
.phfifobyteselout(),
.phfifobyteserdisable(int_rx_phfifobyteserdisable[0]),
.phfifooverflow(),
.phfifoptrsreset(int_rx_phfifoptrsresetout[0]),
.phfifordclkout(),
.phfiforddisable(1'b0),
.phfiforddisableout(wire_transmit_pcs0_phfiforddisableout),
.phfifordenableout(),
.phfiforeset(tx_phfiforeset[0]),
.phfiforesetout(wire_transmit_pcs0_phfiforesetout),
.phfifounderflow(),
.phfifowrenable(1'b1),
.phfifowrenableout(wire_transmit_pcs0_phfifowrenableout),
.phfifoxnbytesel(int_tx_phfifoxnbytesel[2:0]),
.phfifoxnptrsreset(int_tx_phfifioxnptrsreset[2:0]),
.phfifoxnrdclk(int_tx_phfifoxnrdclk[2:0]),
.phfifoxnrdenable(int_tx_phfifoxnrdenable[2:0]),
.phfifoxnwrenable(int_tx_phfifoxnwrenable[2:0]),
.pipeenrevparallellpbkout(wire_transmit_pcs0_pipeenrevparallellpbkout),
.pipepowerdownout(wire_transmit_pcs0_pipepowerdownout),
.pipepowerstateout(wire_transmit_pcs0_pipepowerstateout),
.pipestatetransdone(rx_pipestatetransdoneout[0]),
.pipetxdeemph(tx_pipedeemph[0]),
.pipetxmargin(tx_pipemargin[2:0]),
.pipetxswing(tx_pipeswing[0]),
.powerdn(powerdn[1:0]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitchout(),
.rdenablesync(),
.refclk(refclk_pma[0]),
.revparallelfdbk(rx_revparallelfdbkdata[19:0]),
.txdetectrx(wire_transmit_pcs0_txdetectrx),
.xgmctrl(cent_unit_txctrlout[0]),
.xgmctrlenable(),
.xgmdatain(cent_unit_tx_xgmdataout[7:0]),
.xgmdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslipboundaryselect({5{1'b0}}),
.datainfull({44{1'b0}}),
.freezptr(1'b0),
.hipdatain({10{1'b0}}),
.hipdetectrxloop(1'b0),
.hipelecidleinfersel({3{1'b0}}),
.hipforceelecidle(1'b0),
.hippowerdn({2{1'b0}}),
.hiptxdeemph(1'b0),
.hiptxmargin({3{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdclk(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrenable(1'b0),
.phfifoxnbottombytesel(1'b0),
.phfifoxnbottomrdclk(1'b0),
.phfifoxnbottomrdenable(1'b0),
.phfifoxnbottomwrenable(1'b0),
.phfifoxntopbytesel(1'b0),
.phfifoxntoprdclk(1'b0),
.phfifoxntoprdenable(1'b0),
.phfifoxntopwrenable(1'b0),
.prbscidenable(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rateswitchxndone(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pcs0.allow_polarity_inversion = "false",
transmit_pcs0.auto_spd_self_switch_enable = "true",
transmit_pcs0.bitslip_enable = "false",
transmit_pcs0.channel_bonding = "x8",
transmit_pcs0.channel_number = ((starting_channel_number + 0) % 4),
transmit_pcs0.channel_width = 16,
transmit_pcs0.core_clock_0ppm = "false",
transmit_pcs0.datapath_low_latency_mode = "false",
transmit_pcs0.datapath_protocol = "pipe",
transmit_pcs0.disable_ph_low_latency_mode = "false",
transmit_pcs0.disparity_mode = "new",
transmit_pcs0.dprio_config_mode = 6'h01,
transmit_pcs0.elec_idle_delay = 6,
transmit_pcs0.enable_bit_reversal = "false",
transmit_pcs0.enable_idle_selection = "false",
transmit_pcs0.enable_reverse_parallel_loopback = "true",
transmit_pcs0.enable_self_test_mode = "false",
transmit_pcs0.enable_symbol_swap = "false",
transmit_pcs0.enc_8b_10b_compatibility_mode = "true",
transmit_pcs0.enc_8b_10b_mode = "normal",
transmit_pcs0.force_echar = "false",
transmit_pcs0.force_kchar = "false",
transmit_pcs0.hip_enable = "false",
transmit_pcs0.logical_channel_address = (starting_channel_number + 0),
transmit_pcs0.ph_fifo_reg_mode = "false",
transmit_pcs0.ph_fifo_xn_mapping0 = "none",
transmit_pcs0.ph_fifo_xn_mapping1 = "none",
transmit_pcs0.ph_fifo_xn_mapping2 = "central",
transmit_pcs0.ph_fifo_xn_select = 2,
transmit_pcs0.pipe_auto_speed_nego_enable = "true",
transmit_pcs0.pipe_freq_scale_mode = "Frequency",
transmit_pcs0.pipe_voltage_swing_control = "false",
transmit_pcs0.prbs_cid_pattern = "false",
transmit_pcs0.protocol_hint = "pcie2",
transmit_pcs0.refclk_select = "cmu_clock_divider",
transmit_pcs0.self_test_mode = "incremental",
transmit_pcs0.use_double_data_mode = "true",
transmit_pcs0.use_serializer_double_data_mode = "false",
transmit_pcs0.wr_clk_mux_select = "core_clk",
transmit_pcs0.lpm_type = "stratixiv_hssi_tx_pcs";
stratixiv_hssi_tx_pcs transmit_pcs1
(
.clkout(),
.coreclk(tx_coreclk_in[1]),
.coreclkout(wire_transmit_pcs1_coreclkout),
.ctrlenable({{2{1'b0}}, tx_ctrlenable[3:2]}),
.datain({{24{1'b0}}, tx_datain_wire[31:16]}),
.dataout(wire_transmit_pcs1_dataout),
.detectrxloop(tx_detectrxloop[1]),
.digitalreset(tx_digitalreset_out[1]),
.dispval({{2{1'b0}}, {2{tx_forceelecidle[1]}}}),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_dprioin_wire[299:150]),
.dprioout(wire_transmit_pcs1_dprioout),
.elecidleinfersel(rx_elecidleinfersel[5:3]),
.enrevparallellpbk(tx_revparallellpbken[1]),
.forcedisp({{2{1'b0}}, tx_forcedisp_wire[3:2]}),
.forcedispcompliance(1'b0),
.forceelecidle(tx_forceelecidle[1]),
.forceelecidleout(wire_transmit_pcs1_forceelecidleout),
.grayelecidleinferselout(wire_transmit_pcs1_grayelecidleinferselout),
.hiptxclkout(),
.invpol(tx_invpolarity[1]),
.iqpphfifobyteselout(wire_transmit_pcs1_iqpphfifobyteselout),
.iqpphfifordclkout(wire_transmit_pcs1_iqpphfifordclkout),
.iqpphfifordenableout(wire_transmit_pcs1_iqpphfifordenableout),
.iqpphfifowrenableout(wire_transmit_pcs1_iqpphfifowrenableout),
.iqpphfifoxnbytesel(int_tx_iqpphfifoxnbytesel[3:2]),
.iqpphfifoxnrdclk(int_tx_iqpphfifoxnrdclk[3:2]),
.iqpphfifoxnrdenable(int_tx_iqpphfifoxnrdenable[3:2]),
.iqpphfifoxnwrenable(int_tx_iqpphfifoxnwrenable[3:2]),
.localrefclk(tx_localrefclk[1]),
.parallelfdbkout(),
.phfifobyteselout(),
.phfifobyteserdisable(int_rx_phfifobyteserdisable[1]),
.phfifooverflow(),
.phfifoptrsreset(int_rx_phfifoptrsresetout[1]),
.phfifordclkout(),
.phfiforddisable(1'b0),
.phfiforddisableout(wire_transmit_pcs1_phfiforddisableout),
.phfifordenableout(),
.phfiforeset(tx_phfiforeset[1]),
.phfiforesetout(wire_transmit_pcs1_phfiforesetout),
.phfifounderflow(),
.phfifowrenable(1'b1),
.phfifowrenableout(wire_transmit_pcs1_phfifowrenableout),
.phfifoxnbytesel(int_tx_phfifoxnbytesel[5:3]),
.phfifoxnptrsreset(int_tx_phfifioxnptrsreset[5:3]),
.phfifoxnrdclk(int_tx_phfifoxnrdclk[5:3]),
.phfifoxnrdenable(int_tx_phfifoxnrdenable[5:3]),
.phfifoxnwrenable(int_tx_phfifoxnwrenable[5:3]),
.pipeenrevparallellpbkout(wire_transmit_pcs1_pipeenrevparallellpbkout),
.pipepowerdownout(wire_transmit_pcs1_pipepowerdownout),
.pipepowerstateout(wire_transmit_pcs1_pipepowerstateout),
.pipestatetransdone(rx_pipestatetransdoneout[1]),
.pipetxdeemph(tx_pipedeemph[1]),
.pipetxmargin(tx_pipemargin[5:3]),
.pipetxswing(tx_pipeswing[1]),
.powerdn(powerdn[3:2]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitchout(),
.rdenablesync(),
.refclk(refclk_pma[0]),
.revparallelfdbk(rx_revparallelfdbkdata[39:20]),
.txdetectrx(wire_transmit_pcs1_txdetectrx),
.xgmctrl(cent_unit_txctrlout[1]),
.xgmctrlenable(),
.xgmdatain(cent_unit_tx_xgmdataout[15:8]),
.xgmdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslipboundaryselect({5{1'b0}}),
.datainfull({44{1'b0}}),
.freezptr(1'b0),
.hipdatain({10{1'b0}}),
.hipdetectrxloop(1'b0),
.hipelecidleinfersel({3{1'b0}}),
.hipforceelecidle(1'b0),
.hippowerdn({2{1'b0}}),
.hiptxdeemph(1'b0),
.hiptxmargin({3{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdclk(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrenable(1'b0),
.phfifoxnbottombytesel(1'b0),
.phfifoxnbottomrdclk(1'b0),
.phfifoxnbottomrdenable(1'b0),
.phfifoxnbottomwrenable(1'b0),
.phfifoxntopbytesel(1'b0),
.phfifoxntoprdclk(1'b0),
.phfifoxntoprdenable(1'b0),
.phfifoxntopwrenable(1'b0),
.prbscidenable(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rateswitchxndone(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pcs1.allow_polarity_inversion = "false",
transmit_pcs1.auto_spd_self_switch_enable = "true",
transmit_pcs1.bitslip_enable = "false",
transmit_pcs1.channel_bonding = "x8",
transmit_pcs1.channel_number = ((starting_channel_number + 1) % 4),
transmit_pcs1.channel_width = 16,
transmit_pcs1.core_clock_0ppm = "false",
transmit_pcs1.datapath_low_latency_mode = "false",
transmit_pcs1.datapath_protocol = "pipe",
transmit_pcs1.disable_ph_low_latency_mode = "false",
transmit_pcs1.disparity_mode = "new",
transmit_pcs1.dprio_config_mode = 6'h01,
transmit_pcs1.elec_idle_delay = 6,
transmit_pcs1.enable_bit_reversal = "false",
transmit_pcs1.enable_idle_selection = "false",
transmit_pcs1.enable_reverse_parallel_loopback = "true",
transmit_pcs1.enable_self_test_mode = "false",
transmit_pcs1.enable_symbol_swap = "false",
transmit_pcs1.enc_8b_10b_compatibility_mode = "true",
transmit_pcs1.enc_8b_10b_mode = "normal",
transmit_pcs1.force_echar = "false",
transmit_pcs1.force_kchar = "false",
transmit_pcs1.hip_enable = "false",
transmit_pcs1.logical_channel_address = (starting_channel_number + 1),
transmit_pcs1.ph_fifo_reg_mode = "false",
transmit_pcs1.ph_fifo_xn_mapping0 = "none",
transmit_pcs1.ph_fifo_xn_mapping1 = "none",
transmit_pcs1.ph_fifo_xn_mapping2 = "central",
transmit_pcs1.ph_fifo_xn_select = 2,
transmit_pcs1.pipe_auto_speed_nego_enable = "true",
transmit_pcs1.pipe_freq_scale_mode = "Frequency",
transmit_pcs1.pipe_voltage_swing_control = "false",
transmit_pcs1.prbs_cid_pattern = "false",
transmit_pcs1.protocol_hint = "pcie2",
transmit_pcs1.refclk_select = "cmu_clock_divider",
transmit_pcs1.self_test_mode = "incremental",
transmit_pcs1.use_double_data_mode = "true",
transmit_pcs1.use_serializer_double_data_mode = "false",
transmit_pcs1.wr_clk_mux_select = "core_clk",
transmit_pcs1.lpm_type = "stratixiv_hssi_tx_pcs";
stratixiv_hssi_tx_pcs transmit_pcs2
(
.clkout(),
.coreclk(tx_coreclk_in[2]),
.coreclkout(wire_transmit_pcs2_coreclkout),
.ctrlenable({{2{1'b0}}, tx_ctrlenable[5:4]}),
.datain({{24{1'b0}}, tx_datain_wire[47:32]}),
.dataout(wire_transmit_pcs2_dataout),
.detectrxloop(tx_detectrxloop[2]),
.digitalreset(tx_digitalreset_out[2]),
.dispval({{2{1'b0}}, {2{tx_forceelecidle[2]}}}),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_dprioin_wire[449:300]),
.dprioout(wire_transmit_pcs2_dprioout),
.elecidleinfersel(rx_elecidleinfersel[8:6]),
.enrevparallellpbk(tx_revparallellpbken[2]),
.forcedisp({{2{1'b0}}, tx_forcedisp_wire[5:4]}),
.forcedispcompliance(1'b0),
.forceelecidle(tx_forceelecidle[2]),
.forceelecidleout(wire_transmit_pcs2_forceelecidleout),
.grayelecidleinferselout(wire_transmit_pcs2_grayelecidleinferselout),
.hiptxclkout(),
.invpol(tx_invpolarity[2]),
.iqpphfifobyteselout(wire_transmit_pcs2_iqpphfifobyteselout),
.iqpphfifordclkout(wire_transmit_pcs2_iqpphfifordclkout),
.iqpphfifordenableout(wire_transmit_pcs2_iqpphfifordenableout),
.iqpphfifowrenableout(wire_transmit_pcs2_iqpphfifowrenableout),
.iqpphfifoxnbytesel(int_tx_iqpphfifoxnbytesel[5:4]),
.iqpphfifoxnrdclk(int_tx_iqpphfifoxnrdclk[5:4]),
.iqpphfifoxnrdenable(int_tx_iqpphfifoxnrdenable[5:4]),
.iqpphfifoxnwrenable(int_tx_iqpphfifoxnwrenable[5:4]),
.localrefclk(tx_localrefclk[2]),
.parallelfdbkout(),
.phfifobyteselout(),
.phfifobyteserdisable(int_rx_phfifobyteserdisable[2]),
.phfifooverflow(),
.phfifoptrsreset(int_rx_phfifoptrsresetout[2]),
.phfifordclkout(),
.phfiforddisable(1'b0),
.phfiforddisableout(wire_transmit_pcs2_phfiforddisableout),
.phfifordenableout(),
.phfiforeset(tx_phfiforeset[2]),
.phfiforesetout(wire_transmit_pcs2_phfiforesetout),
.phfifounderflow(),
.phfifowrenable(1'b1),
.phfifowrenableout(wire_transmit_pcs2_phfifowrenableout),
.phfifoxnbytesel(int_tx_phfifoxnbytesel[8:6]),
.phfifoxnptrsreset(int_tx_phfifioxnptrsreset[8:6]),
.phfifoxnrdclk(int_tx_phfifoxnrdclk[8:6]),
.phfifoxnrdenable(int_tx_phfifoxnrdenable[8:6]),
.phfifoxnwrenable(int_tx_phfifoxnwrenable[8:6]),
.pipeenrevparallellpbkout(wire_transmit_pcs2_pipeenrevparallellpbkout),
.pipepowerdownout(wire_transmit_pcs2_pipepowerdownout),
.pipepowerstateout(wire_transmit_pcs2_pipepowerstateout),
.pipestatetransdone(rx_pipestatetransdoneout[2]),
.pipetxdeemph(tx_pipedeemph[2]),
.pipetxmargin(tx_pipemargin[8:6]),
.pipetxswing(tx_pipeswing[2]),
.powerdn(powerdn[5:4]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitchout(),
.rdenablesync(),
.refclk(refclk_pma[0]),
.revparallelfdbk(rx_revparallelfdbkdata[59:40]),
.txdetectrx(wire_transmit_pcs2_txdetectrx),
.xgmctrl(cent_unit_txctrlout[2]),
.xgmctrlenable(),
.xgmdatain(cent_unit_tx_xgmdataout[23:16]),
.xgmdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslipboundaryselect({5{1'b0}}),
.datainfull({44{1'b0}}),
.freezptr(1'b0),
.hipdatain({10{1'b0}}),
.hipdetectrxloop(1'b0),
.hipelecidleinfersel({3{1'b0}}),
.hipforceelecidle(1'b0),
.hippowerdn({2{1'b0}}),
.hiptxdeemph(1'b0),
.hiptxmargin({3{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdclk(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrenable(1'b0),
.phfifoxnbottombytesel(1'b0),
.phfifoxnbottomrdclk(1'b0),
.phfifoxnbottomrdenable(1'b0),
.phfifoxnbottomwrenable(1'b0),
.phfifoxntopbytesel(1'b0),
.phfifoxntoprdclk(1'b0),
.phfifoxntoprdenable(1'b0),
.phfifoxntopwrenable(1'b0),
.prbscidenable(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rateswitchxndone(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pcs2.allow_polarity_inversion = "false",
transmit_pcs2.auto_spd_self_switch_enable = "true",
transmit_pcs2.bitslip_enable = "false",
transmit_pcs2.channel_bonding = "x8",
transmit_pcs2.channel_number = ((starting_channel_number + 2) % 4),
transmit_pcs2.channel_width = 16,
transmit_pcs2.core_clock_0ppm = "false",
transmit_pcs2.datapath_low_latency_mode = "false",
transmit_pcs2.datapath_protocol = "pipe",
transmit_pcs2.disable_ph_low_latency_mode = "false",
transmit_pcs2.disparity_mode = "new",
transmit_pcs2.dprio_config_mode = 6'h01,
transmit_pcs2.elec_idle_delay = 6,
transmit_pcs2.enable_bit_reversal = "false",
transmit_pcs2.enable_idle_selection = "false",
transmit_pcs2.enable_reverse_parallel_loopback = "true",
transmit_pcs2.enable_self_test_mode = "false",
transmit_pcs2.enable_symbol_swap = "false",
transmit_pcs2.enc_8b_10b_compatibility_mode = "true",
transmit_pcs2.enc_8b_10b_mode = "normal",
transmit_pcs2.force_echar = "false",
transmit_pcs2.force_kchar = "false",
transmit_pcs2.hip_enable = "false",
transmit_pcs2.logical_channel_address = (starting_channel_number + 2),
transmit_pcs2.ph_fifo_reg_mode = "false",
transmit_pcs2.ph_fifo_xn_mapping0 = "none",
transmit_pcs2.ph_fifo_xn_mapping1 = "none",
transmit_pcs2.ph_fifo_xn_mapping2 = "central",
transmit_pcs2.ph_fifo_xn_select = 2,
transmit_pcs2.pipe_auto_speed_nego_enable = "true",
transmit_pcs2.pipe_freq_scale_mode = "Frequency",
transmit_pcs2.pipe_voltage_swing_control = "false",
transmit_pcs2.prbs_cid_pattern = "false",
transmit_pcs2.protocol_hint = "pcie2",
transmit_pcs2.refclk_select = "cmu_clock_divider",
transmit_pcs2.self_test_mode = "incremental",
transmit_pcs2.use_double_data_mode = "true",
transmit_pcs2.use_serializer_double_data_mode = "false",
transmit_pcs2.wr_clk_mux_select = "core_clk",
transmit_pcs2.lpm_type = "stratixiv_hssi_tx_pcs";
stratixiv_hssi_tx_pcs transmit_pcs3
(
.clkout(),
.coreclk(tx_coreclk_in[3]),
.coreclkout(wire_transmit_pcs3_coreclkout),
.ctrlenable({{2{1'b0}}, tx_ctrlenable[7:6]}),
.datain({{24{1'b0}}, tx_datain_wire[63:48]}),
.dataout(wire_transmit_pcs3_dataout),
.detectrxloop(tx_detectrxloop[3]),
.digitalreset(tx_digitalreset_out[3]),
.dispval({{2{1'b0}}, {2{tx_forceelecidle[3]}}}),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_dprioin_wire[599:450]),
.dprioout(wire_transmit_pcs3_dprioout),
.elecidleinfersel(rx_elecidleinfersel[11:9]),
.enrevparallellpbk(tx_revparallellpbken[3]),
.forcedisp({{2{1'b0}}, tx_forcedisp_wire[7:6]}),
.forcedispcompliance(1'b0),
.forceelecidle(tx_forceelecidle[3]),
.forceelecidleout(wire_transmit_pcs3_forceelecidleout),
.grayelecidleinferselout(wire_transmit_pcs3_grayelecidleinferselout),
.hiptxclkout(),
.invpol(tx_invpolarity[3]),
.iqpphfifobyteselout(wire_transmit_pcs3_iqpphfifobyteselout),
.iqpphfifordclkout(wire_transmit_pcs3_iqpphfifordclkout),
.iqpphfifordenableout(wire_transmit_pcs3_iqpphfifordenableout),
.iqpphfifowrenableout(wire_transmit_pcs3_iqpphfifowrenableout),
.iqpphfifoxnbytesel(int_tx_iqpphfifoxnbytesel[7:6]),
.iqpphfifoxnrdclk(int_tx_iqpphfifoxnrdclk[7:6]),
.iqpphfifoxnrdenable(int_tx_iqpphfifoxnrdenable[7:6]),
.iqpphfifoxnwrenable(int_tx_iqpphfifoxnwrenable[7:6]),
.localrefclk(tx_localrefclk[3]),
.parallelfdbkout(),
.phfifobyteselout(),
.phfifobyteserdisable(int_rx_phfifobyteserdisable[3]),
.phfifooverflow(),
.phfifoptrsreset(int_rx_phfifoptrsresetout[3]),
.phfifordclkout(),
.phfiforddisable(1'b0),
.phfiforddisableout(wire_transmit_pcs3_phfiforddisableout),
.phfifordenableout(),
.phfiforeset(tx_phfiforeset[3]),
.phfiforesetout(wire_transmit_pcs3_phfiforesetout),
.phfifounderflow(),
.phfifowrenable(1'b1),
.phfifowrenableout(wire_transmit_pcs3_phfifowrenableout),
.phfifoxnbytesel(int_tx_phfifoxnbytesel[11:9]),
.phfifoxnptrsreset(int_tx_phfifioxnptrsreset[11:9]),
.phfifoxnrdclk(int_tx_phfifoxnrdclk[11:9]),
.phfifoxnrdenable(int_tx_phfifoxnrdenable[11:9]),
.phfifoxnwrenable(int_tx_phfifoxnwrenable[11:9]),
.pipeenrevparallellpbkout(wire_transmit_pcs3_pipeenrevparallellpbkout),
.pipepowerdownout(wire_transmit_pcs3_pipepowerdownout),
.pipepowerstateout(wire_transmit_pcs3_pipepowerstateout),
.pipestatetransdone(rx_pipestatetransdoneout[3]),
.pipetxdeemph(tx_pipedeemph[3]),
.pipetxmargin(tx_pipemargin[11:9]),
.pipetxswing(tx_pipeswing[3]),
.powerdn(powerdn[7:6]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitchout(),
.rdenablesync(),
.refclk(refclk_pma[0]),
.revparallelfdbk(rx_revparallelfdbkdata[79:60]),
.txdetectrx(wire_transmit_pcs3_txdetectrx),
.xgmctrl(cent_unit_txctrlout[3]),
.xgmctrlenable(),
.xgmdatain(cent_unit_tx_xgmdataout[31:24]),
.xgmdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslipboundaryselect({5{1'b0}}),
.datainfull({44{1'b0}}),
.freezptr(1'b0),
.hipdatain({10{1'b0}}),
.hipdetectrxloop(1'b0),
.hipelecidleinfersel({3{1'b0}}),
.hipforceelecidle(1'b0),
.hippowerdn({2{1'b0}}),
.hiptxdeemph(1'b0),
.hiptxmargin({3{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdclk(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrenable(1'b0),
.phfifoxnbottombytesel(1'b0),
.phfifoxnbottomrdclk(1'b0),
.phfifoxnbottomrdenable(1'b0),
.phfifoxnbottomwrenable(1'b0),
.phfifoxntopbytesel(1'b0),
.phfifoxntoprdclk(1'b0),
.phfifoxntoprdenable(1'b0),
.phfifoxntopwrenable(1'b0),
.prbscidenable(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rateswitchxndone(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pcs3.allow_polarity_inversion = "false",
transmit_pcs3.auto_spd_self_switch_enable = "true",
transmit_pcs3.bitslip_enable = "false",
transmit_pcs3.channel_bonding = "x8",
transmit_pcs3.channel_number = ((starting_channel_number + 3) % 4),
transmit_pcs3.channel_width = 16,
transmit_pcs3.core_clock_0ppm = "false",
transmit_pcs3.datapath_low_latency_mode = "false",
transmit_pcs3.datapath_protocol = "pipe",
transmit_pcs3.disable_ph_low_latency_mode = "false",
transmit_pcs3.disparity_mode = "new",
transmit_pcs3.dprio_config_mode = 6'h01,
transmit_pcs3.elec_idle_delay = 6,
transmit_pcs3.enable_bit_reversal = "false",
transmit_pcs3.enable_idle_selection = "false",
transmit_pcs3.enable_reverse_parallel_loopback = "true",
transmit_pcs3.enable_self_test_mode = "false",
transmit_pcs3.enable_symbol_swap = "false",
transmit_pcs3.enc_8b_10b_compatibility_mode = "true",
transmit_pcs3.enc_8b_10b_mode = "normal",
transmit_pcs3.force_echar = "false",
transmit_pcs3.force_kchar = "false",
transmit_pcs3.hip_enable = "false",
transmit_pcs3.logical_channel_address = (starting_channel_number + 3),
transmit_pcs3.ph_fifo_reg_mode = "false",
transmit_pcs3.ph_fifo_xn_mapping0 = "none",
transmit_pcs3.ph_fifo_xn_mapping1 = "none",
transmit_pcs3.ph_fifo_xn_mapping2 = "central",
transmit_pcs3.ph_fifo_xn_select = 2,
transmit_pcs3.pipe_auto_speed_nego_enable = "true",
transmit_pcs3.pipe_freq_scale_mode = "Frequency",
transmit_pcs3.pipe_voltage_swing_control = "false",
transmit_pcs3.prbs_cid_pattern = "false",
transmit_pcs3.protocol_hint = "pcie2",
transmit_pcs3.refclk_select = "cmu_clock_divider",
transmit_pcs3.self_test_mode = "incremental",
transmit_pcs3.use_double_data_mode = "true",
transmit_pcs3.use_serializer_double_data_mode = "false",
transmit_pcs3.wr_clk_mux_select = "core_clk",
transmit_pcs3.lpm_type = "stratixiv_hssi_tx_pcs";
stratixiv_hssi_tx_pcs transmit_pcs4
(
.clkout(),
.coreclk(tx_coreclk_in[4]),
.coreclkout(wire_transmit_pcs4_coreclkout),
.ctrlenable({{2{1'b0}}, tx_ctrlenable[9:8]}),
.datain({{24{1'b0}}, tx_datain_wire[79:64]}),
.dataout(wire_transmit_pcs4_dataout),
.detectrxloop(tx_detectrxloop[4]),
.digitalreset(tx_digitalreset_out[4]),
.dispval({{2{1'b0}}, {2{tx_forceelecidle[4]}}}),
.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
.dprioin(tx_dprioin_wire[749:600]),
.dprioout(wire_transmit_pcs4_dprioout),
.elecidleinfersel(rx_elecidleinfersel[14:12]),
.enrevparallellpbk(tx_revparallellpbken[4]),
.forcedisp({{2{1'b0}}, tx_forcedisp_wire[9:8]}),
.forcedispcompliance(1'b0),
.forceelecidle(tx_forceelecidle[4]),
.forceelecidleout(wire_transmit_pcs4_forceelecidleout),
.grayelecidleinferselout(wire_transmit_pcs4_grayelecidleinferselout),
.hiptxclkout(),
.invpol(tx_invpolarity[4]),
.iqpphfifobyteselout(wire_transmit_pcs4_iqpphfifobyteselout),
.iqpphfifordclkout(wire_transmit_pcs4_iqpphfifordclkout),
.iqpphfifordenableout(wire_transmit_pcs4_iqpphfifordenableout),
.iqpphfifowrenableout(wire_transmit_pcs4_iqpphfifowrenableout),
.iqpphfifoxnbytesel(int_tx_iqpphfifoxnbytesel[9:8]),
.iqpphfifoxnrdclk(int_tx_iqpphfifoxnrdclk[9:8]),
.iqpphfifoxnrdenable(int_tx_iqpphfifoxnrdenable[9:8]),
.iqpphfifoxnwrenable(int_tx_iqpphfifoxnwrenable[9:8]),
.localrefclk(tx_localrefclk[4]),
.parallelfdbkout(),
.phfifobyteselout(),
.phfifobyteserdisable(int_rx_phfifobyteserdisable[4]),
.phfifooverflow(),
.phfifoptrsreset(int_rx_phfifoptrsresetout[4]),
.phfifordclkout(),
.phfiforddisable(1'b0),
.phfiforddisableout(wire_transmit_pcs4_phfiforddisableout),
.phfifordenableout(),
.phfiforeset(tx_phfiforeset[4]),
.phfiforesetout(wire_transmit_pcs4_phfiforesetout),
.phfifounderflow(),
.phfifowrenable(1'b1),
.phfifowrenableout(wire_transmit_pcs4_phfifowrenableout),
.phfifoxnbytesel(int_tx_phfifoxnbytesel[14:12]),
.phfifoxnptrsreset(int_tx_phfifioxnptrsreset[14:12]),
.phfifoxnrdclk(int_tx_phfifoxnrdclk[14:12]),
.phfifoxnrdenable(int_tx_phfifoxnrdenable[14:12]),
.phfifoxnwrenable(int_tx_phfifoxnwrenable[14:12]),
.pipeenrevparallellpbkout(wire_transmit_pcs4_pipeenrevparallellpbkout),
.pipepowerdownout(wire_transmit_pcs4_pipepowerdownout),
.pipepowerstateout(wire_transmit_pcs4_pipepowerstateout),
.pipestatetransdone(rx_pipestatetransdoneout[4]),
.pipetxdeemph(tx_pipedeemph[4]),
.pipetxmargin(tx_pipemargin[14:12]),
.pipetxswing(tx_pipeswing[4]),
.powerdn(powerdn[9:8]),
.quadreset(cent_unit_quadresetout[1]),
.rateswitchout(),
.rdenablesync(),
.refclk(refclk_pma[1]),
.revparallelfdbk(rx_revparallelfdbkdata[99:80]),
.txdetectrx(wire_transmit_pcs4_txdetectrx),
.xgmctrl(cent_unit_txctrlout[4]),
.xgmctrlenable(),
.xgmdatain(cent_unit_tx_xgmdataout[39:32]),
.xgmdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslipboundaryselect({5{1'b0}}),
.datainfull({44{1'b0}}),
.freezptr(1'b0),
.hipdatain({10{1'b0}}),
.hipdetectrxloop(1'b0),
.hipelecidleinfersel({3{1'b0}}),
.hipforceelecidle(1'b0),
.hippowerdn({2{1'b0}}),
.hiptxdeemph(1'b0),
.hiptxmargin({3{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdclk(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrenable(1'b0),
.phfifoxnbottombytesel(1'b0),
.phfifoxnbottomrdclk(1'b0),
.phfifoxnbottomrdenable(1'b0),
.phfifoxnbottomwrenable(1'b0),
.phfifoxntopbytesel(1'b0),
.phfifoxntoprdclk(1'b0),
.phfifoxntoprdenable(1'b0),
.phfifoxntopwrenable(1'b0),
.prbscidenable(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rateswitchxndone(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pcs4.allow_polarity_inversion = "false",
transmit_pcs4.auto_spd_self_switch_enable = "true",
transmit_pcs4.bitslip_enable = "false",
transmit_pcs4.channel_bonding = "x8",
transmit_pcs4.channel_number = ((starting_channel_number + 4) % 4),
transmit_pcs4.channel_width = 16,
transmit_pcs4.core_clock_0ppm = "false",
transmit_pcs4.datapath_low_latency_mode = "false",
transmit_pcs4.datapath_protocol = "pipe",
transmit_pcs4.disable_ph_low_latency_mode = "false",
transmit_pcs4.disparity_mode = "new",
transmit_pcs4.dprio_config_mode = 6'h01,
transmit_pcs4.elec_idle_delay = 6,
transmit_pcs4.enable_bit_reversal = "false",
transmit_pcs4.enable_idle_selection = "false",
transmit_pcs4.enable_reverse_parallel_loopback = "true",
transmit_pcs4.enable_self_test_mode = "false",
transmit_pcs4.enable_symbol_swap = "false",
transmit_pcs4.enc_8b_10b_compatibility_mode = "true",
transmit_pcs4.enc_8b_10b_mode = "normal",
transmit_pcs4.force_echar = "false",
transmit_pcs4.force_kchar = "false",
transmit_pcs4.hip_enable = "false",
transmit_pcs4.iqp_ph_fifo_xn_select = 1,
transmit_pcs4.logical_channel_address = (starting_channel_number + 4),
transmit_pcs4.ph_fifo_reg_mode = "false",
transmit_pcs4.ph_fifo_xn_mapping0 = "none",
transmit_pcs4.ph_fifo_xn_mapping1 = "up",
transmit_pcs4.ph_fifo_xn_mapping2 = "none",
transmit_pcs4.ph_fifo_xn_select = 1,
transmit_pcs4.pipe_auto_speed_nego_enable = "true",
transmit_pcs4.pipe_freq_scale_mode = "Frequency",
transmit_pcs4.pipe_voltage_swing_control = "false",
transmit_pcs4.prbs_cid_pattern = "false",
transmit_pcs4.protocol_hint = "pcie2",
transmit_pcs4.refclk_select = "cmu_clock_divider",
transmit_pcs4.self_test_mode = "incremental",
transmit_pcs4.use_double_data_mode = "true",
transmit_pcs4.use_serializer_double_data_mode = "false",
transmit_pcs4.wr_clk_mux_select = "core_clk",
transmit_pcs4.lpm_type = "stratixiv_hssi_tx_pcs";
stratixiv_hssi_tx_pcs transmit_pcs5
(
.clkout(),
.coreclk(tx_coreclk_in[5]),
.coreclkout(wire_transmit_pcs5_coreclkout),
.ctrlenable({{2{1'b0}}, tx_ctrlenable[11:10]}),
.datain({{24{1'b0}}, tx_datain_wire[95:80]}),
.dataout(wire_transmit_pcs5_dataout),
.detectrxloop(tx_detectrxloop[5]),
.digitalreset(tx_digitalreset_out[5]),
.dispval({{2{1'b0}}, {2{tx_forceelecidle[5]}}}),
.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
.dprioin(tx_dprioin_wire[899:750]),
.dprioout(wire_transmit_pcs5_dprioout),
.elecidleinfersel(rx_elecidleinfersel[17:15]),
.enrevparallellpbk(tx_revparallellpbken[5]),
.forcedisp({{2{1'b0}}, tx_forcedisp_wire[11:10]}),
.forcedispcompliance(1'b0),
.forceelecidle(tx_forceelecidle[5]),
.forceelecidleout(wire_transmit_pcs5_forceelecidleout),
.grayelecidleinferselout(wire_transmit_pcs5_grayelecidleinferselout),
.hiptxclkout(),
.invpol(tx_invpolarity[5]),
.iqpphfifobyteselout(wire_transmit_pcs5_iqpphfifobyteselout),
.iqpphfifordclkout(wire_transmit_pcs5_iqpphfifordclkout),
.iqpphfifordenableout(wire_transmit_pcs5_iqpphfifordenableout),
.iqpphfifowrenableout(wire_transmit_pcs5_iqpphfifowrenableout),
.iqpphfifoxnbytesel(int_tx_iqpphfifoxnbytesel[11:10]),
.iqpphfifoxnrdclk(int_tx_iqpphfifoxnrdclk[11:10]),
.iqpphfifoxnrdenable(int_tx_iqpphfifoxnrdenable[11:10]),
.iqpphfifoxnwrenable(int_tx_iqpphfifoxnwrenable[11:10]),
.localrefclk(tx_localrefclk[5]),
.parallelfdbkout(),
.phfifobyteselout(),
.phfifobyteserdisable(int_rx_phfifobyteserdisable[5]),
.phfifooverflow(),
.phfifoptrsreset(int_rx_phfifoptrsresetout[5]),
.phfifordclkout(),
.phfiforddisable(1'b0),
.phfiforddisableout(wire_transmit_pcs5_phfiforddisableout),
.phfifordenableout(),
.phfiforeset(tx_phfiforeset[5]),
.phfiforesetout(wire_transmit_pcs5_phfiforesetout),
.phfifounderflow(),
.phfifowrenable(1'b1),
.phfifowrenableout(wire_transmit_pcs5_phfifowrenableout),
.phfifoxnbytesel(int_tx_phfifoxnbytesel[17:15]),
.phfifoxnptrsreset(int_tx_phfifioxnptrsreset[17:15]),
.phfifoxnrdclk(int_tx_phfifoxnrdclk[17:15]),
.phfifoxnrdenable(int_tx_phfifoxnrdenable[17:15]),
.phfifoxnwrenable(int_tx_phfifoxnwrenable[17:15]),
.pipeenrevparallellpbkout(wire_transmit_pcs5_pipeenrevparallellpbkout),
.pipepowerdownout(wire_transmit_pcs5_pipepowerdownout),
.pipepowerstateout(wire_transmit_pcs5_pipepowerstateout),
.pipestatetransdone(rx_pipestatetransdoneout[5]),
.pipetxdeemph(tx_pipedeemph[5]),
.pipetxmargin(tx_pipemargin[17:15]),
.pipetxswing(tx_pipeswing[5]),
.powerdn(powerdn[11:10]),
.quadreset(cent_unit_quadresetout[1]),
.rateswitchout(),
.rdenablesync(),
.refclk(refclk_pma[1]),
.revparallelfdbk(rx_revparallelfdbkdata[119:100]),
.txdetectrx(wire_transmit_pcs5_txdetectrx),
.xgmctrl(cent_unit_txctrlout[5]),
.xgmctrlenable(),
.xgmdatain(cent_unit_tx_xgmdataout[47:40]),
.xgmdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslipboundaryselect({5{1'b0}}),
.datainfull({44{1'b0}}),
.freezptr(1'b0),
.hipdatain({10{1'b0}}),
.hipdetectrxloop(1'b0),
.hipelecidleinfersel({3{1'b0}}),
.hipforceelecidle(1'b0),
.hippowerdn({2{1'b0}}),
.hiptxdeemph(1'b0),
.hiptxmargin({3{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdclk(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrenable(1'b0),
.phfifoxnbottombytesel(1'b0),
.phfifoxnbottomrdclk(1'b0),
.phfifoxnbottomrdenable(1'b0),
.phfifoxnbottomwrenable(1'b0),
.phfifoxntopbytesel(1'b0),
.phfifoxntoprdclk(1'b0),
.phfifoxntoprdenable(1'b0),
.phfifoxntopwrenable(1'b0),
.prbscidenable(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rateswitchxndone(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pcs5.allow_polarity_inversion = "false",
transmit_pcs5.auto_spd_self_switch_enable = "true",
transmit_pcs5.bitslip_enable = "false",
transmit_pcs5.channel_bonding = "x8",
transmit_pcs5.channel_number = ((starting_channel_number + 5) % 4),
transmit_pcs5.channel_width = 16,
transmit_pcs5.core_clock_0ppm = "false",
transmit_pcs5.datapath_low_latency_mode = "false",
transmit_pcs5.datapath_protocol = "pipe",
transmit_pcs5.disable_ph_low_latency_mode = "false",
transmit_pcs5.disparity_mode = "new",
transmit_pcs5.dprio_config_mode = 6'h01,
transmit_pcs5.elec_idle_delay = 6,
transmit_pcs5.enable_bit_reversal = "false",
transmit_pcs5.enable_idle_selection = "false",
transmit_pcs5.enable_reverse_parallel_loopback = "true",
transmit_pcs5.enable_self_test_mode = "false",
transmit_pcs5.enable_symbol_swap = "false",
transmit_pcs5.enc_8b_10b_compatibility_mode = "true",
transmit_pcs5.enc_8b_10b_mode = "normal",
transmit_pcs5.force_echar = "false",
transmit_pcs5.force_kchar = "false",
transmit_pcs5.hip_enable = "false",
transmit_pcs5.logical_channel_address = (starting_channel_number + 5),
transmit_pcs5.ph_fifo_reg_mode = "false",
transmit_pcs5.ph_fifo_xn_mapping0 = "none",
transmit_pcs5.ph_fifo_xn_mapping1 = "up",
transmit_pcs5.ph_fifo_xn_mapping2 = "none",
transmit_pcs5.ph_fifo_xn_select = 1,
transmit_pcs5.pipe_auto_speed_nego_enable = "true",
transmit_pcs5.pipe_freq_scale_mode = "Frequency",
transmit_pcs5.pipe_voltage_swing_control = "false",
transmit_pcs5.prbs_cid_pattern = "false",
transmit_pcs5.protocol_hint = "pcie2",
transmit_pcs5.refclk_select = "cmu_clock_divider",
transmit_pcs5.self_test_mode = "incremental",
transmit_pcs5.use_double_data_mode = "true",
transmit_pcs5.use_serializer_double_data_mode = "false",
transmit_pcs5.wr_clk_mux_select = "core_clk",
transmit_pcs5.lpm_type = "stratixiv_hssi_tx_pcs";
stratixiv_hssi_tx_pcs transmit_pcs6
(
.clkout(),
.coreclk(tx_coreclk_in[6]),
.coreclkout(wire_transmit_pcs6_coreclkout),
.ctrlenable({{2{1'b0}}, tx_ctrlenable[13:12]}),
.datain({{24{1'b0}}, tx_datain_wire[111:96]}),
.dataout(wire_transmit_pcs6_dataout),
.detectrxloop(tx_detectrxloop[6]),
.digitalreset(tx_digitalreset_out[6]),
.dispval({{2{1'b0}}, {2{tx_forceelecidle[6]}}}),
.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
.dprioin(tx_dprioin_wire[1049:900]),
.dprioout(wire_transmit_pcs6_dprioout),
.elecidleinfersel(rx_elecidleinfersel[20:18]),
.enrevparallellpbk(tx_revparallellpbken[6]),
.forcedisp({{2{1'b0}}, tx_forcedisp_wire[13:12]}),
.forcedispcompliance(1'b0),
.forceelecidle(tx_forceelecidle[6]),
.forceelecidleout(wire_transmit_pcs6_forceelecidleout),
.grayelecidleinferselout(wire_transmit_pcs6_grayelecidleinferselout),
.hiptxclkout(),
.invpol(tx_invpolarity[6]),
.iqpphfifobyteselout(wire_transmit_pcs6_iqpphfifobyteselout),
.iqpphfifordclkout(wire_transmit_pcs6_iqpphfifordclkout),
.iqpphfifordenableout(wire_transmit_pcs6_iqpphfifordenableout),
.iqpphfifowrenableout(wire_transmit_pcs6_iqpphfifowrenableout),
.iqpphfifoxnbytesel(int_tx_iqpphfifoxnbytesel[13:12]),
.iqpphfifoxnrdclk(int_tx_iqpphfifoxnrdclk[13:12]),
.iqpphfifoxnrdenable(int_tx_iqpphfifoxnrdenable[13:12]),
.iqpphfifoxnwrenable(int_tx_iqpphfifoxnwrenable[13:12]),
.localrefclk(tx_localrefclk[6]),
.parallelfdbkout(),
.phfifobyteselout(),
.phfifobyteserdisable(int_rx_phfifobyteserdisable[6]),
.phfifooverflow(),
.phfifoptrsreset(int_rx_phfifoptrsresetout[6]),
.phfifordclkout(),
.phfiforddisable(1'b0),
.phfiforddisableout(wire_transmit_pcs6_phfiforddisableout),
.phfifordenableout(),
.phfiforeset(tx_phfiforeset[6]),
.phfiforesetout(wire_transmit_pcs6_phfiforesetout),
.phfifounderflow(),
.phfifowrenable(1'b1),
.phfifowrenableout(wire_transmit_pcs6_phfifowrenableout),
.phfifoxnbytesel(int_tx_phfifoxnbytesel[20:18]),
.phfifoxnptrsreset(int_tx_phfifioxnptrsreset[20:18]),
.phfifoxnrdclk(int_tx_phfifoxnrdclk[20:18]),
.phfifoxnrdenable(int_tx_phfifoxnrdenable[20:18]),
.phfifoxnwrenable(int_tx_phfifoxnwrenable[20:18]),
.pipeenrevparallellpbkout(wire_transmit_pcs6_pipeenrevparallellpbkout),
.pipepowerdownout(wire_transmit_pcs6_pipepowerdownout),
.pipepowerstateout(wire_transmit_pcs6_pipepowerstateout),
.pipestatetransdone(rx_pipestatetransdoneout[6]),
.pipetxdeemph(tx_pipedeemph[6]),
.pipetxmargin(tx_pipemargin[20:18]),
.pipetxswing(tx_pipeswing[6]),
.powerdn(powerdn[13:12]),
.quadreset(cent_unit_quadresetout[1]),
.rateswitchout(),
.rdenablesync(),
.refclk(refclk_pma[1]),
.revparallelfdbk(rx_revparallelfdbkdata[139:120]),
.txdetectrx(wire_transmit_pcs6_txdetectrx),
.xgmctrl(cent_unit_txctrlout[6]),
.xgmctrlenable(),
.xgmdatain(cent_unit_tx_xgmdataout[55:48]),
.xgmdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslipboundaryselect({5{1'b0}}),
.datainfull({44{1'b0}}),
.freezptr(1'b0),
.hipdatain({10{1'b0}}),
.hipdetectrxloop(1'b0),
.hipelecidleinfersel({3{1'b0}}),
.hipforceelecidle(1'b0),
.hippowerdn({2{1'b0}}),
.hiptxdeemph(1'b0),
.hiptxmargin({3{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdclk(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrenable(1'b0),
.phfifoxnbottombytesel(1'b0),
.phfifoxnbottomrdclk(1'b0),
.phfifoxnbottomrdenable(1'b0),
.phfifoxnbottomwrenable(1'b0),
.phfifoxntopbytesel(1'b0),
.phfifoxntoprdclk(1'b0),
.phfifoxntoprdenable(1'b0),
.phfifoxntopwrenable(1'b0),
.prbscidenable(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rateswitchxndone(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pcs6.allow_polarity_inversion = "false",
transmit_pcs6.auto_spd_self_switch_enable = "true",
transmit_pcs6.bitslip_enable = "false",
transmit_pcs6.channel_bonding = "x8",
transmit_pcs6.channel_number = ((starting_channel_number + 6) % 4),
transmit_pcs6.channel_width = 16,
transmit_pcs6.core_clock_0ppm = "false",
transmit_pcs6.datapath_low_latency_mode = "false",
transmit_pcs6.datapath_protocol = "pipe",
transmit_pcs6.disable_ph_low_latency_mode = "false",
transmit_pcs6.disparity_mode = "new",
transmit_pcs6.dprio_config_mode = 6'h01,
transmit_pcs6.elec_idle_delay = 6,
transmit_pcs6.enable_bit_reversal = "false",
transmit_pcs6.enable_idle_selection = "false",
transmit_pcs6.enable_reverse_parallel_loopback = "true",
transmit_pcs6.enable_self_test_mode = "false",
transmit_pcs6.enable_symbol_swap = "false",
transmit_pcs6.enc_8b_10b_compatibility_mode = "true",
transmit_pcs6.enc_8b_10b_mode = "normal",
transmit_pcs6.force_echar = "false",
transmit_pcs6.force_kchar = "false",
transmit_pcs6.hip_enable = "false",
transmit_pcs6.logical_channel_address = (starting_channel_number + 6),
transmit_pcs6.ph_fifo_reg_mode = "false",
transmit_pcs6.ph_fifo_xn_mapping0 = "none",
transmit_pcs6.ph_fifo_xn_mapping1 = "up",
transmit_pcs6.ph_fifo_xn_mapping2 = "none",
transmit_pcs6.ph_fifo_xn_select = 1,
transmit_pcs6.pipe_auto_speed_nego_enable = "true",
transmit_pcs6.pipe_freq_scale_mode = "Frequency",
transmit_pcs6.pipe_voltage_swing_control = "false",
transmit_pcs6.prbs_cid_pattern = "false",
transmit_pcs6.protocol_hint = "pcie2",
transmit_pcs6.refclk_select = "cmu_clock_divider",
transmit_pcs6.self_test_mode = "incremental",
transmit_pcs6.use_double_data_mode = "true",
transmit_pcs6.use_serializer_double_data_mode = "false",
transmit_pcs6.wr_clk_mux_select = "core_clk",
transmit_pcs6.lpm_type = "stratixiv_hssi_tx_pcs";
stratixiv_hssi_tx_pcs transmit_pcs7
(
.clkout(),
.coreclk(tx_coreclk_in[7]),
.coreclkout(wire_transmit_pcs7_coreclkout),
.ctrlenable({{2{1'b0}}, tx_ctrlenable[15:14]}),
.datain({{24{1'b0}}, tx_datain_wire[127:112]}),
.dataout(wire_transmit_pcs7_dataout),
.detectrxloop(tx_detectrxloop[7]),
.digitalreset(tx_digitalreset_out[7]),
.dispval({{2{1'b0}}, {2{tx_forceelecidle[7]}}}),
.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
.dprioin(tx_dprioin_wire[1199:1050]),
.dprioout(wire_transmit_pcs7_dprioout),
.elecidleinfersel(rx_elecidleinfersel[23:21]),
.enrevparallellpbk(tx_revparallellpbken[7]),
.forcedisp({{2{1'b0}}, tx_forcedisp_wire[15:14]}),
.forcedispcompliance(1'b0),
.forceelecidle(tx_forceelecidle[7]),
.forceelecidleout(wire_transmit_pcs7_forceelecidleout),
.grayelecidleinferselout(wire_transmit_pcs7_grayelecidleinferselout),
.hiptxclkout(),
.invpol(tx_invpolarity[7]),
.iqpphfifobyteselout(wire_transmit_pcs7_iqpphfifobyteselout),
.iqpphfifordclkout(wire_transmit_pcs7_iqpphfifordclkout),
.iqpphfifordenableout(wire_transmit_pcs7_iqpphfifordenableout),
.iqpphfifowrenableout(wire_transmit_pcs7_iqpphfifowrenableout),
.iqpphfifoxnbytesel(int_tx_iqpphfifoxnbytesel[15:14]),
.iqpphfifoxnrdclk(int_tx_iqpphfifoxnrdclk[15:14]),
.iqpphfifoxnrdenable(int_tx_iqpphfifoxnrdenable[15:14]),
.iqpphfifoxnwrenable(int_tx_iqpphfifoxnwrenable[15:14]),
.localrefclk(tx_localrefclk[7]),
.parallelfdbkout(),
.phfifobyteselout(),
.phfifobyteserdisable(int_rx_phfifobyteserdisable[7]),
.phfifooverflow(),
.phfifoptrsreset(int_rx_phfifoptrsresetout[7]),
.phfifordclkout(),
.phfiforddisable(1'b0),
.phfiforddisableout(wire_transmit_pcs7_phfiforddisableout),
.phfifordenableout(),
.phfiforeset(tx_phfiforeset[7]),
.phfiforesetout(wire_transmit_pcs7_phfiforesetout),
.phfifounderflow(),
.phfifowrenable(1'b1),
.phfifowrenableout(wire_transmit_pcs7_phfifowrenableout),
.phfifoxnbytesel(int_tx_phfifoxnbytesel[23:21]),
.phfifoxnptrsreset(int_tx_phfifioxnptrsreset[23:21]),
.phfifoxnrdclk(int_tx_phfifoxnrdclk[23:21]),
.phfifoxnrdenable(int_tx_phfifoxnrdenable[23:21]),
.phfifoxnwrenable(int_tx_phfifoxnwrenable[23:21]),
.pipeenrevparallellpbkout(wire_transmit_pcs7_pipeenrevparallellpbkout),
.pipepowerdownout(wire_transmit_pcs7_pipepowerdownout),
.pipepowerstateout(wire_transmit_pcs7_pipepowerstateout),
.pipestatetransdone(rx_pipestatetransdoneout[7]),
.pipetxdeemph(tx_pipedeemph[7]),
.pipetxmargin(tx_pipemargin[23:21]),
.pipetxswing(tx_pipeswing[7]),
.powerdn(powerdn[15:14]),
.quadreset(cent_unit_quadresetout[1]),
.rateswitchout(),
.rdenablesync(),
.refclk(refclk_pma[1]),
.revparallelfdbk(rx_revparallelfdbkdata[159:140]),
.txdetectrx(wire_transmit_pcs7_txdetectrx),
.xgmctrl(cent_unit_txctrlout[7]),
.xgmctrlenable(),
.xgmdatain(cent_unit_tx_xgmdataout[63:56]),
.xgmdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslipboundaryselect({5{1'b0}}),
.datainfull({44{1'b0}}),
.freezptr(1'b0),
.hipdatain({10{1'b0}}),
.hipdetectrxloop(1'b0),
.hipelecidleinfersel({3{1'b0}}),
.hipforceelecidle(1'b0),
.hippowerdn({2{1'b0}}),
.hiptxdeemph(1'b0),
.hiptxmargin({3{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdclk(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrenable(1'b0),
.phfifoxnbottombytesel(1'b0),
.phfifoxnbottomrdclk(1'b0),
.phfifoxnbottomrdenable(1'b0),
.phfifoxnbottomwrenable(1'b0),
.phfifoxntopbytesel(1'b0),
.phfifoxntoprdclk(1'b0),
.phfifoxntoprdenable(1'b0),
.phfifoxntopwrenable(1'b0),
.prbscidenable(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rateswitchxndone(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pcs7.allow_polarity_inversion = "false",
transmit_pcs7.auto_spd_self_switch_enable = "true",
transmit_pcs7.bitslip_enable = "false",
transmit_pcs7.channel_bonding = "x8",
transmit_pcs7.channel_number = ((starting_channel_number + 7) % 4),
transmit_pcs7.channel_width = 16,
transmit_pcs7.core_clock_0ppm = "false",
transmit_pcs7.datapath_low_latency_mode = "false",
transmit_pcs7.datapath_protocol = "pipe",
transmit_pcs7.disable_ph_low_latency_mode = "false",
transmit_pcs7.disparity_mode = "new",
transmit_pcs7.dprio_config_mode = 6'h01,
transmit_pcs7.elec_idle_delay = 6,
transmit_pcs7.enable_bit_reversal = "false",
transmit_pcs7.enable_idle_selection = "false",
transmit_pcs7.enable_reverse_parallel_loopback = "true",
transmit_pcs7.enable_self_test_mode = "false",
transmit_pcs7.enable_symbol_swap = "false",
transmit_pcs7.enc_8b_10b_compatibility_mode = "true",
transmit_pcs7.enc_8b_10b_mode = "normal",
transmit_pcs7.force_echar = "false",
transmit_pcs7.force_kchar = "false",
transmit_pcs7.hip_enable = "false",
transmit_pcs7.logical_channel_address = (starting_channel_number + 7),
transmit_pcs7.ph_fifo_reg_mode = "false",
transmit_pcs7.ph_fifo_xn_mapping0 = "none",
transmit_pcs7.ph_fifo_xn_mapping1 = "up",
transmit_pcs7.ph_fifo_xn_mapping2 = "none",
transmit_pcs7.ph_fifo_xn_select = 1,
transmit_pcs7.pipe_auto_speed_nego_enable = "true",
transmit_pcs7.pipe_freq_scale_mode = "Frequency",
transmit_pcs7.pipe_voltage_swing_control = "false",
transmit_pcs7.prbs_cid_pattern = "false",
transmit_pcs7.protocol_hint = "pcie2",
transmit_pcs7.refclk_select = "cmu_clock_divider",
transmit_pcs7.self_test_mode = "incremental",
transmit_pcs7.use_double_data_mode = "true",
transmit_pcs7.use_serializer_double_data_mode = "false",
transmit_pcs7.wr_clk_mux_select = "core_clk",
transmit_pcs7.lpm_type = "stratixiv_hssi_tx_pcs";
stratixiv_hssi_tx_pma transmit_pma0
(
.clockout(wire_transmit_pma0_clockout),
.datain({{44{1'b0}}, tx_dataout_pcs_to_pma[19:0]}),
.dataout(wire_transmit_pma0_dataout),
.detectrxpowerdown(cent_unit_txdetectrxpowerdn[0]),
.dftout(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_pmadprioin_wire[299:0]),
.dprioout(wire_transmit_pma0_dprioout),
.fastrefclk0in({2{1'b0}}),
.fastrefclk1in(cmu_analogfastrefclkout[1:0]),
.fastrefclk2in({2{1'b0}}),
.fastrefclk4in({2{1'b0}}),
.forceelecidle(tx_pcs_forceelecidleout[0]),
.powerdn(cent_unit_txobpowerdn[0]),
.refclk0in({2{1'b0}}),
.refclk0inpulse(1'b0),
.refclk1in(cmu_analogrefclkout[1:0]),
.refclk1inpulse(cmu_analogrefclkpulse[0]),
.refclk2in({2{1'b0}}),
.refclk2inpulse(1'b0),
.refclk4in({2{1'b0}}),
.refclk4inpulse(1'b0),
.revserialfdbk(1'b0),
.rxdetecten(txdetectrxout[0]),
.rxdetectvalidout(wire_transmit_pma0_rxdetectvalidout),
.rxfoundout(wire_transmit_pma0_rxfoundout),
.seriallpbkout(),
.txpmareset(tx_analogreset_out[0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.datainfull({20{1'b0}}),
.extra10gin({11{1'b0}}),
.fastrefclk3in({2{1'b0}}),
.pclk({5{1'b0}}),
.refclk3in({2{1'b0}}),
.refclk3inpulse(1'b0),
.rxdetectclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pma0.analog_power = "auto",
transmit_pma0.channel_number = ((starting_channel_number + 0) % 4),
transmit_pma0.channel_type = "auto",
transmit_pma0.clkin_select = 1,
transmit_pma0.clkmux_delay = "false",
transmit_pma0.common_mode = "0.65V",
transmit_pma0.dprio_config_mode = 6'h01,
transmit_pma0.enable_reverse_serial_loopback = "false",
transmit_pma0.logical_channel_address = (starting_channel_number + 0),
transmit_pma0.logical_protocol_hint_0 = "pcie2",
transmit_pma0.low_speed_test_select = 0,
transmit_pma0.physical_clkin1_mapping = "x4",
transmit_pma0.preemp_pretap = 0,
transmit_pma0.preemp_pretap_inv = "false",
transmit_pma0.preemp_tap_1 = 0,
transmit_pma0.preemp_tap_1_a = 28,
transmit_pma0.preemp_tap_1_b = 22,
transmit_pma0.preemp_tap_1_c = 7,
transmit_pma0.preemp_tap_2 = 0,
transmit_pma0.preemp_tap_2_inv = "false",
transmit_pma0.protocol_hint = "pcie2",
transmit_pma0.rx_detect = 0,
transmit_pma0.serialization_factor = 10,
transmit_pma0.slew_rate = "off",
transmit_pma0.termination = "OCT 100 Ohms",
transmit_pma0.use_external_termination = "false",
transmit_pma0.use_pma_direct = "false",
transmit_pma0.use_ser_double_data_mode = "false",
transmit_pma0.vod_selection = 3,
transmit_pma0.vod_selection_a = 6,
transmit_pma0.vod_selection_c = 1,
transmit_pma0.lpm_type = "stratixiv_hssi_tx_pma";
stratixiv_hssi_tx_pma transmit_pma1
(
.clockout(wire_transmit_pma1_clockout),
.datain({{44{1'b0}}, tx_dataout_pcs_to_pma[39:20]}),
.dataout(wire_transmit_pma1_dataout),
.detectrxpowerdown(cent_unit_txdetectrxpowerdn[1]),
.dftout(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_pmadprioin_wire[599:300]),
.dprioout(wire_transmit_pma1_dprioout),
.fastrefclk0in({2{1'b0}}),
.fastrefclk1in(cmu_analogfastrefclkout[1:0]),
.fastrefclk2in({2{1'b0}}),
.fastrefclk4in({2{1'b0}}),
.forceelecidle(tx_pcs_forceelecidleout[1]),
.powerdn(cent_unit_txobpowerdn[1]),
.refclk0in({2{1'b0}}),
.refclk0inpulse(1'b0),
.refclk1in(cmu_analogrefclkout[1:0]),
.refclk1inpulse(cmu_analogrefclkpulse[0]),
.refclk2in({2{1'b0}}),
.refclk2inpulse(1'b0),
.refclk4in({2{1'b0}}),
.refclk4inpulse(1'b0),
.revserialfdbk(1'b0),
.rxdetecten(txdetectrxout[1]),
.rxdetectvalidout(wire_transmit_pma1_rxdetectvalidout),
.rxfoundout(wire_transmit_pma1_rxfoundout),
.seriallpbkout(),
.txpmareset(tx_analogreset_out[1])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.datainfull({20{1'b0}}),
.extra10gin({11{1'b0}}),
.fastrefclk3in({2{1'b0}}),
.pclk({5{1'b0}}),
.refclk3in({2{1'b0}}),
.refclk3inpulse(1'b0),
.rxdetectclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pma1.analog_power = "auto",
transmit_pma1.channel_number = ((starting_channel_number + 1) % 4),
transmit_pma1.channel_type = "auto",
transmit_pma1.clkin_select = 1,
transmit_pma1.clkmux_delay = "false",
transmit_pma1.common_mode = "0.65V",
transmit_pma1.dprio_config_mode = 6'h01,
transmit_pma1.enable_reverse_serial_loopback = "false",
transmit_pma1.logical_channel_address = (starting_channel_number + 1),
transmit_pma1.logical_protocol_hint_0 = "pcie2",
transmit_pma1.low_speed_test_select = 0,
transmit_pma1.physical_clkin1_mapping = "x4",
transmit_pma1.preemp_pretap = 0,
transmit_pma1.preemp_pretap_inv = "false",
transmit_pma1.preemp_tap_1 = 0,
transmit_pma1.preemp_tap_1_a = 28,
transmit_pma1.preemp_tap_1_b = 22,
transmit_pma1.preemp_tap_1_c = 7,
transmit_pma1.preemp_tap_2 = 0,
transmit_pma1.preemp_tap_2_inv = "false",
transmit_pma1.protocol_hint = "pcie2",
transmit_pma1.rx_detect = 0,
transmit_pma1.serialization_factor = 10,
transmit_pma1.slew_rate = "off",
transmit_pma1.termination = "OCT 100 Ohms",
transmit_pma1.use_external_termination = "false",
transmit_pma1.use_pma_direct = "false",
transmit_pma1.use_ser_double_data_mode = "false",
transmit_pma1.vod_selection = 3,
transmit_pma1.vod_selection_a = 6,
transmit_pma1.vod_selection_c = 1,
transmit_pma1.lpm_type = "stratixiv_hssi_tx_pma";
stratixiv_hssi_tx_pma transmit_pma2
(
.clockout(wire_transmit_pma2_clockout),
.datain({{44{1'b0}}, tx_dataout_pcs_to_pma[59:40]}),
.dataout(wire_transmit_pma2_dataout),
.detectrxpowerdown(cent_unit_txdetectrxpowerdn[2]),
.dftout(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_pmadprioin_wire[899:600]),
.dprioout(wire_transmit_pma2_dprioout),
.fastrefclk0in({2{1'b0}}),
.fastrefclk1in(cmu_analogfastrefclkout[1:0]),
.fastrefclk2in({2{1'b0}}),
.fastrefclk4in({2{1'b0}}),
.forceelecidle(tx_pcs_forceelecidleout[2]),
.powerdn(cent_unit_txobpowerdn[2]),
.refclk0in({2{1'b0}}),
.refclk0inpulse(1'b0),
.refclk1in(cmu_analogrefclkout[1:0]),
.refclk1inpulse(cmu_analogrefclkpulse[0]),
.refclk2in({2{1'b0}}),
.refclk2inpulse(1'b0),
.refclk4in({2{1'b0}}),
.refclk4inpulse(1'b0),
.revserialfdbk(1'b0),
.rxdetecten(txdetectrxout[2]),
.rxdetectvalidout(wire_transmit_pma2_rxdetectvalidout),
.rxfoundout(wire_transmit_pma2_rxfoundout),
.seriallpbkout(),
.txpmareset(tx_analogreset_out[2])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.datainfull({20{1'b0}}),
.extra10gin({11{1'b0}}),
.fastrefclk3in({2{1'b0}}),
.pclk({5{1'b0}}),
.refclk3in({2{1'b0}}),
.refclk3inpulse(1'b0),
.rxdetectclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pma2.analog_power = "auto",
transmit_pma2.channel_number = ((starting_channel_number + 2) % 4),
transmit_pma2.channel_type = "auto",
transmit_pma2.clkin_select = 1,
transmit_pma2.clkmux_delay = "false",
transmit_pma2.common_mode = "0.65V",
transmit_pma2.dprio_config_mode = 6'h01,
transmit_pma2.enable_reverse_serial_loopback = "false",
transmit_pma2.logical_channel_address = (starting_channel_number + 2),
transmit_pma2.logical_protocol_hint_0 = "pcie2",
transmit_pma2.low_speed_test_select = 0,
transmit_pma2.physical_clkin1_mapping = "x4",
transmit_pma2.preemp_pretap = 0,
transmit_pma2.preemp_pretap_inv = "false",
transmit_pma2.preemp_tap_1 = 0,
transmit_pma2.preemp_tap_1_a = 28,
transmit_pma2.preemp_tap_1_b = 22,
transmit_pma2.preemp_tap_1_c = 7,
transmit_pma2.preemp_tap_2 = 0,
transmit_pma2.preemp_tap_2_inv = "false",
transmit_pma2.protocol_hint = "pcie2",
transmit_pma2.rx_detect = 0,
transmit_pma2.serialization_factor = 10,
transmit_pma2.slew_rate = "off",
transmit_pma2.termination = "OCT 100 Ohms",
transmit_pma2.use_external_termination = "false",
transmit_pma2.use_pma_direct = "false",
transmit_pma2.use_ser_double_data_mode = "false",
transmit_pma2.vod_selection = 3,
transmit_pma2.vod_selection_a = 6,
transmit_pma2.vod_selection_c = 1,
transmit_pma2.lpm_type = "stratixiv_hssi_tx_pma";
stratixiv_hssi_tx_pma transmit_pma3
(
.clockout(wire_transmit_pma3_clockout),
.datain({{44{1'b0}}, tx_dataout_pcs_to_pma[79:60]}),
.dataout(wire_transmit_pma3_dataout),
.detectrxpowerdown(cent_unit_txdetectrxpowerdn[3]),
.dftout(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_pmadprioin_wire[1199:900]),
.dprioout(wire_transmit_pma3_dprioout),
.fastrefclk0in({2{1'b0}}),
.fastrefclk1in(cmu_analogfastrefclkout[1:0]),
.fastrefclk2in({2{1'b0}}),
.fastrefclk4in({2{1'b0}}),
.forceelecidle(tx_pcs_forceelecidleout[3]),
.powerdn(cent_unit_txobpowerdn[3]),
.refclk0in({2{1'b0}}),
.refclk0inpulse(1'b0),
.refclk1in(cmu_analogrefclkout[1:0]),
.refclk1inpulse(cmu_analogrefclkpulse[0]),
.refclk2in({2{1'b0}}),
.refclk2inpulse(1'b0),
.refclk4in({2{1'b0}}),
.refclk4inpulse(1'b0),
.revserialfdbk(1'b0),
.rxdetecten(txdetectrxout[3]),
.rxdetectvalidout(wire_transmit_pma3_rxdetectvalidout),
.rxfoundout(wire_transmit_pma3_rxfoundout),
.seriallpbkout(),
.txpmareset(tx_analogreset_out[3])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.datainfull({20{1'b0}}),
.extra10gin({11{1'b0}}),
.fastrefclk3in({2{1'b0}}),
.pclk({5{1'b0}}),
.refclk3in({2{1'b0}}),
.refclk3inpulse(1'b0),
.rxdetectclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pma3.analog_power = "auto",
transmit_pma3.channel_number = ((starting_channel_number + 3) % 4),
transmit_pma3.channel_type = "auto",
transmit_pma3.clkin_select = 1,
transmit_pma3.clkmux_delay = "false",
transmit_pma3.common_mode = "0.65V",
transmit_pma3.dprio_config_mode = 6'h01,
transmit_pma3.enable_reverse_serial_loopback = "false",
transmit_pma3.logical_channel_address = (starting_channel_number + 3),
transmit_pma3.logical_protocol_hint_0 = "pcie2",
transmit_pma3.low_speed_test_select = 0,
transmit_pma3.physical_clkin1_mapping = "x4",
transmit_pma3.preemp_pretap = 0,
transmit_pma3.preemp_pretap_inv = "false",
transmit_pma3.preemp_tap_1 = 0,
transmit_pma3.preemp_tap_1_a = 28,
transmit_pma3.preemp_tap_1_b = 22,
transmit_pma3.preemp_tap_1_c = 7,
transmit_pma3.preemp_tap_2 = 0,
transmit_pma3.preemp_tap_2_inv = "false",
transmit_pma3.protocol_hint = "pcie2",
transmit_pma3.rx_detect = 0,
transmit_pma3.serialization_factor = 10,
transmit_pma3.slew_rate = "off",
transmit_pma3.termination = "OCT 100 Ohms",
transmit_pma3.use_external_termination = "false",
transmit_pma3.use_pma_direct = "false",
transmit_pma3.use_ser_double_data_mode = "false",
transmit_pma3.vod_selection = 3,
transmit_pma3.vod_selection_a = 6,
transmit_pma3.vod_selection_c = 1,
transmit_pma3.lpm_type = "stratixiv_hssi_tx_pma";
stratixiv_hssi_tx_pma transmit_pma4
(
.clockout(wire_transmit_pma4_clockout),
.datain({{44{1'b0}}, tx_dataout_pcs_to_pma[99:80]}),
.dataout(wire_transmit_pma4_dataout),
.detectrxpowerdown(cent_unit_txdetectrxpowerdn[6]),
.dftout(),
.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
.dprioin(tx_pmadprioin_wire[2099:1800]),
.dprioout(wire_transmit_pma4_dprioout),
.fastrefclk0in({2{1'b0}}),
.fastrefclk1in({2{1'b0}}),
.fastrefclk2in(cmu_analogfastrefclkout[1:0]),
.fastrefclk4in({2{1'b0}}),
.forceelecidle(tx_pcs_forceelecidleout[4]),
.powerdn(cent_unit_txobpowerdn[6]),
.refclk0in({2{1'b0}}),
.refclk0inpulse(1'b0),
.refclk1in({2{1'b0}}),
.refclk1inpulse(1'b0),
.refclk2in(cmu_analogrefclkout[1:0]),
.refclk2inpulse(cmu_analogrefclkpulse[0]),
.refclk4in({2{1'b0}}),
.refclk4inpulse(1'b0),
.revserialfdbk(1'b0),
.rxdetecten(txdetectrxout[4]),
.rxdetectvalidout(wire_transmit_pma4_rxdetectvalidout),
.rxfoundout(wire_transmit_pma4_rxfoundout),
.seriallpbkout(),
.txpmareset(tx_analogreset_out[6])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.datainfull({20{1'b0}}),
.extra10gin({11{1'b0}}),
.fastrefclk3in({2{1'b0}}),
.pclk({5{1'b0}}),
.refclk3in({2{1'b0}}),
.refclk3inpulse(1'b0),
.rxdetectclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pma4.analog_power = "auto",
transmit_pma4.channel_number = ((starting_channel_number + 4) % 4),
transmit_pma4.channel_type = "auto",
transmit_pma4.clkin_select = 2,
transmit_pma4.clkmux_delay = "false",
transmit_pma4.common_mode = "0.65V",
transmit_pma4.dprio_config_mode = 6'h01,
transmit_pma4.enable_reverse_serial_loopback = "false",
transmit_pma4.logical_channel_address = (starting_channel_number + 4),
transmit_pma4.logical_protocol_hint_0 = "pcie2",
transmit_pma4.low_speed_test_select = 0,
transmit_pma4.physical_clkin2_mapping = "xn_top",
transmit_pma4.preemp_pretap = 0,
transmit_pma4.preemp_pretap_inv = "false",
transmit_pma4.preemp_tap_1 = 0,
transmit_pma4.preemp_tap_1_a = 28,
transmit_pma4.preemp_tap_1_b = 22,
transmit_pma4.preemp_tap_1_c = 7,
transmit_pma4.preemp_tap_2 = 0,
transmit_pma4.preemp_tap_2_inv = "false",
transmit_pma4.protocol_hint = "pcie2",
transmit_pma4.rx_detect = 0,
transmit_pma4.serialization_factor = 10,
transmit_pma4.slew_rate = "off",
transmit_pma4.termination = "OCT 100 Ohms",
transmit_pma4.use_external_termination = "false",
transmit_pma4.use_pma_direct = "false",
transmit_pma4.use_ser_double_data_mode = "false",
transmit_pma4.vod_selection = 3,
transmit_pma4.vod_selection_a = 6,
transmit_pma4.vod_selection_c = 1,
transmit_pma4.lpm_type = "stratixiv_hssi_tx_pma";
stratixiv_hssi_tx_pma transmit_pma5
(
.clockout(wire_transmit_pma5_clockout),
.datain({{44{1'b0}}, tx_dataout_pcs_to_pma[119:100]}),
.dataout(wire_transmit_pma5_dataout),
.detectrxpowerdown(cent_unit_txdetectrxpowerdn[7]),
.dftout(),
.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
.dprioin(tx_pmadprioin_wire[2399:2100]),
.dprioout(wire_transmit_pma5_dprioout),
.fastrefclk0in({2{1'b0}}),
.fastrefclk1in({2{1'b0}}),
.fastrefclk2in(cmu_analogfastrefclkout[1:0]),
.fastrefclk4in({2{1'b0}}),
.forceelecidle(tx_pcs_forceelecidleout[5]),
.powerdn(cent_unit_txobpowerdn[7]),
.refclk0in({2{1'b0}}),
.refclk0inpulse(1'b0),
.refclk1in({2{1'b0}}),
.refclk1inpulse(1'b0),
.refclk2in(cmu_analogrefclkout[1:0]),
.refclk2inpulse(cmu_analogrefclkpulse[0]),
.refclk4in({2{1'b0}}),
.refclk4inpulse(1'b0),
.revserialfdbk(1'b0),
.rxdetecten(txdetectrxout[5]),
.rxdetectvalidout(wire_transmit_pma5_rxdetectvalidout),
.rxfoundout(wire_transmit_pma5_rxfoundout),
.seriallpbkout(),
.txpmareset(tx_analogreset_out[7])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.datainfull({20{1'b0}}),
.extra10gin({11{1'b0}}),
.fastrefclk3in({2{1'b0}}),
.pclk({5{1'b0}}),
.refclk3in({2{1'b0}}),
.refclk3inpulse(1'b0),
.rxdetectclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pma5.analog_power = "auto",
transmit_pma5.channel_number = ((starting_channel_number + 5) % 4),
transmit_pma5.channel_type = "auto",
transmit_pma5.clkin_select = 2,
transmit_pma5.clkmux_delay = "false",
transmit_pma5.common_mode = "0.65V",
transmit_pma5.dprio_config_mode = 6'h01,
transmit_pma5.enable_reverse_serial_loopback = "false",
transmit_pma5.logical_channel_address = (starting_channel_number + 5),
transmit_pma5.logical_protocol_hint_0 = "pcie2",
transmit_pma5.low_speed_test_select = 0,
transmit_pma5.physical_clkin2_mapping = "xn_top",
transmit_pma5.preemp_pretap = 0,
transmit_pma5.preemp_pretap_inv = "false",
transmit_pma5.preemp_tap_1 = 0,
transmit_pma5.preemp_tap_1_a = 28,
transmit_pma5.preemp_tap_1_b = 22,
transmit_pma5.preemp_tap_1_c = 7,
transmit_pma5.preemp_tap_2 = 0,
transmit_pma5.preemp_tap_2_inv = "false",
transmit_pma5.protocol_hint = "pcie2",
transmit_pma5.rx_detect = 0,
transmit_pma5.serialization_factor = 10,
transmit_pma5.slew_rate = "off",
transmit_pma5.termination = "OCT 100 Ohms",
transmit_pma5.use_external_termination = "false",
transmit_pma5.use_pma_direct = "false",
transmit_pma5.use_ser_double_data_mode = "false",
transmit_pma5.vod_selection = 3,
transmit_pma5.vod_selection_a = 6,
transmit_pma5.vod_selection_c = 1,
transmit_pma5.lpm_type = "stratixiv_hssi_tx_pma";
stratixiv_hssi_tx_pma transmit_pma6
(
.clockout(wire_transmit_pma6_clockout),
.datain({{44{1'b0}}, tx_dataout_pcs_to_pma[139:120]}),
.dataout(wire_transmit_pma6_dataout),
.detectrxpowerdown(cent_unit_txdetectrxpowerdn[8]),
.dftout(),
.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
.dprioin(tx_pmadprioin_wire[2699:2400]),
.dprioout(wire_transmit_pma6_dprioout),
.fastrefclk0in({2{1'b0}}),
.fastrefclk1in({2{1'b0}}),
.fastrefclk2in(cmu_analogfastrefclkout[1:0]),
.fastrefclk4in({2{1'b0}}),
.forceelecidle(tx_pcs_forceelecidleout[6]),
.powerdn(cent_unit_txobpowerdn[8]),
.refclk0in({2{1'b0}}),
.refclk0inpulse(1'b0),
.refclk1in({2{1'b0}}),
.refclk1inpulse(1'b0),
.refclk2in(cmu_analogrefclkout[1:0]),
.refclk2inpulse(cmu_analogrefclkpulse[0]),
.refclk4in({2{1'b0}}),
.refclk4inpulse(1'b0),
.revserialfdbk(1'b0),
.rxdetecten(txdetectrxout[6]),
.rxdetectvalidout(wire_transmit_pma6_rxdetectvalidout),
.rxfoundout(wire_transmit_pma6_rxfoundout),
.seriallpbkout(),
.txpmareset(tx_analogreset_out[8])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.datainfull({20{1'b0}}),
.extra10gin({11{1'b0}}),
.fastrefclk3in({2{1'b0}}),
.pclk({5{1'b0}}),
.refclk3in({2{1'b0}}),
.refclk3inpulse(1'b0),
.rxdetectclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pma6.analog_power = "auto",
transmit_pma6.channel_number = ((starting_channel_number + 6) % 4),
transmit_pma6.channel_type = "auto",
transmit_pma6.clkin_select = 2,
transmit_pma6.clkmux_delay = "false",
transmit_pma6.common_mode = "0.65V",
transmit_pma6.dprio_config_mode = 6'h01,
transmit_pma6.enable_reverse_serial_loopback = "false",
transmit_pma6.logical_channel_address = (starting_channel_number + 6),
transmit_pma6.logical_protocol_hint_0 = "pcie2",
transmit_pma6.low_speed_test_select = 0,
transmit_pma6.physical_clkin2_mapping = "xn_top",
transmit_pma6.preemp_pretap = 0,
transmit_pma6.preemp_pretap_inv = "false",
transmit_pma6.preemp_tap_1 = 0,
transmit_pma6.preemp_tap_1_a = 28,
transmit_pma6.preemp_tap_1_b = 22,
transmit_pma6.preemp_tap_1_c = 7,
transmit_pma6.preemp_tap_2 = 0,
transmit_pma6.preemp_tap_2_inv = "false",
transmit_pma6.protocol_hint = "pcie2",
transmit_pma6.rx_detect = 0,
transmit_pma6.serialization_factor = 10,
transmit_pma6.slew_rate = "off",
transmit_pma6.termination = "OCT 100 Ohms",
transmit_pma6.use_external_termination = "false",
transmit_pma6.use_pma_direct = "false",
transmit_pma6.use_ser_double_data_mode = "false",
transmit_pma6.vod_selection = 3,
transmit_pma6.vod_selection_a = 6,
transmit_pma6.vod_selection_c = 1,
transmit_pma6.lpm_type = "stratixiv_hssi_tx_pma";
stratixiv_hssi_tx_pma transmit_pma7
(
.clockout(wire_transmit_pma7_clockout),
.datain({{44{1'b0}}, tx_dataout_pcs_to_pma[159:140]}),
.dataout(wire_transmit_pma7_dataout),
.detectrxpowerdown(cent_unit_txdetectrxpowerdn[9]),
.dftout(),
.dpriodisable(w_cent_unit_dpriodisableout1w[1]),
.dprioin(tx_pmadprioin_wire[2999:2700]),
.dprioout(wire_transmit_pma7_dprioout),
.fastrefclk0in({2{1'b0}}),
.fastrefclk1in({2{1'b0}}),
.fastrefclk2in(cmu_analogfastrefclkout[1:0]),
.fastrefclk4in({2{1'b0}}),
.forceelecidle(tx_pcs_forceelecidleout[7]),
.powerdn(cent_unit_txobpowerdn[9]),
.refclk0in({2{1'b0}}),
.refclk0inpulse(1'b0),
.refclk1in({2{1'b0}}),
.refclk1inpulse(1'b0),
.refclk2in(cmu_analogrefclkout[1:0]),
.refclk2inpulse(cmu_analogrefclkpulse[0]),
.refclk4in({2{1'b0}}),
.refclk4inpulse(1'b0),
.revserialfdbk(1'b0),
.rxdetecten(txdetectrxout[7]),
.rxdetectvalidout(wire_transmit_pma7_rxdetectvalidout),
.rxfoundout(wire_transmit_pma7_rxfoundout),
.seriallpbkout(),
.txpmareset(tx_analogreset_out[9])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.datainfull({20{1'b0}}),
.extra10gin({11{1'b0}}),
.fastrefclk3in({2{1'b0}}),
.pclk({5{1'b0}}),
.refclk3in({2{1'b0}}),
.refclk3inpulse(1'b0),
.rxdetectclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pma7.analog_power = "auto",
transmit_pma7.channel_number = ((starting_channel_number + 7) % 4),
transmit_pma7.channel_type = "auto",
transmit_pma7.clkin_select = 2,
transmit_pma7.clkmux_delay = "false",
transmit_pma7.common_mode = "0.65V",
transmit_pma7.dprio_config_mode = 6'h01,
transmit_pma7.enable_reverse_serial_loopback = "false",
transmit_pma7.logical_channel_address = (starting_channel_number + 7),
transmit_pma7.logical_protocol_hint_0 = "pcie2",
transmit_pma7.low_speed_test_select = 0,
transmit_pma7.physical_clkin2_mapping = "xn_top",
transmit_pma7.preemp_pretap = 0,
transmit_pma7.preemp_pretap_inv = "false",
transmit_pma7.preemp_tap_1 = 0,
transmit_pma7.preemp_tap_1_a = 28,
transmit_pma7.preemp_tap_1_b = 22,
transmit_pma7.preemp_tap_1_c = 7,
transmit_pma7.preemp_tap_2 = 0,
transmit_pma7.preemp_tap_2_inv = "false",
transmit_pma7.protocol_hint = "pcie2",
transmit_pma7.rx_detect = 0,
transmit_pma7.serialization_factor = 10,
transmit_pma7.slew_rate = "off",
transmit_pma7.termination = "OCT 100 Ohms",
transmit_pma7.use_external_termination = "false",
transmit_pma7.use_pma_direct = "false",
transmit_pma7.use_ser_double_data_mode = "false",
transmit_pma7.vod_selection = 3,
transmit_pma7.vod_selection_a = 6,
transmit_pma7.vod_selection_c = 1,
transmit_pma7.lpm_type = "stratixiv_hssi_tx_pma";
assign
cal_blk_powerdown = 1'b0,
cent_unit_clkdivpowerdn = {wire_cent_unit1_clkdivpowerdn[0], wire_cent_unit0_clkdivpowerdn[0]},
cent_unit_cmudividerdprioout = {wire_cent_unit1_cmudividerdprioout, wire_cent_unit0_cmudividerdprioout},
cent_unit_cmuplldprioout = {wire_cent_unit1_cmuplldprioout, wire_cent_unit0_cmuplldprioout},
cent_unit_pllpowerdn = {wire_cent_unit1_pllpowerdn[1:0], wire_cent_unit0_pllpowerdn[1:0]},
cent_unit_pllresetout = {wire_cent_unit1_pllresetout[1:0], wire_cent_unit0_pllresetout[1:0]},
cent_unit_quadresetout = {wire_cent_unit1_quadresetout, wire_cent_unit0_quadresetout},
cent_unit_rxcrupowerdn = {wire_cent_unit1_rxcrupowerdown[5:0], wire_cent_unit0_rxcrupowerdown[5:0]},
cent_unit_rxibpowerdn = {wire_cent_unit1_rxibpowerdown[5:0], wire_cent_unit0_rxibpowerdown[5:0]},
cent_unit_rxpcsdprioin = {rx_pcsdprioout[3199:0]},
cent_unit_rxpcsdprioout = {wire_cent_unit1_rxpcsdprioout[1599:0], wire_cent_unit0_rxpcsdprioout[1599:0]},
cent_unit_rxpmadprioin = {{2{{300{1'b0}}}}, rx_pmadprioout[2999:1800], {2{{300{1'b0}}}}, rx_pmadprioout[1199:0]},
cent_unit_rxpmadprioout = {wire_cent_unit1_rxpmadprioout[1799:0], wire_cent_unit0_rxpmadprioout[1799:0]},
cent_unit_tx_dprioin = {{1200{1'b0}}, tx_txdprioout[1199:0]},
cent_unit_tx_xgmdataout = {wire_cent_unit1_txdataout[31:0], wire_cent_unit0_txdataout[31:0]},
cent_unit_txctrlout = {wire_cent_unit1_txctrlout, wire_cent_unit0_txctrlout},
cent_unit_txdetectrxpowerdn = {wire_cent_unit1_txdetectrxpowerdown[5:0], wire_cent_unit0_txdetectrxpowerdown[5:0]},
cent_unit_txdprioout = {wire_cent_unit1_txpcsdprioout[599:0], wire_cent_unit0_txpcsdprioout[599:0]},
cent_unit_txobpowerdn = {wire_cent_unit1_txobpowerdown[5:0], wire_cent_unit0_txobpowerdown[5:0]},
cent_unit_txpmadprioin = {{2{{300{1'b0}}}}, tx_pmadprioout[2999:1800], {2{{300{1'b0}}}}, tx_pmadprioout[1199:0]},
cent_unit_txpmadprioout = {wire_cent_unit1_txpmadprioout[1799:0], wire_cent_unit0_txpmadprioout[1799:0]},
clk_div_clk0in = {pll0_out[7:0]},
clk_div_cmudividerdprioin = {{100{1'b0}}, wire_central_clk_div1_dprioout, {400{1'b0}}, {100{1'b0}}, wire_central_clk_div0_dprioout, {400{1'b0}}},
clk_div_pclkin = {refclk_pma[0], 1'b0},
cmu_analogfastrefclkout = {wire_central_clk_div1_analogfastrefclkout, wire_central_clk_div0_analogfastrefclkout},
cmu_analogrefclkout = {wire_central_clk_div1_analogrefclkout, wire_central_clk_div0_analogrefclkout},
cmu_analogrefclkpulse = {wire_central_clk_div1_analogrefclkpulse, wire_central_clk_div0_analogrefclkpulse},
coreclkout = {coreclkout_wire[0]},
coreclkout_bi_quad_wire = {coreclkout_wire[0]},
coreclkout_wire = {wire_central_clk_div1_coreclkout, wire_central_clk_div0_coreclkout},
fixedclk_to_cmu = {12{reconfig_clk}},
grayelecidleinfersel_from_tx = {wire_transmit_pcs7_grayelecidleinferselout, wire_transmit_pcs6_grayelecidleinferselout, wire_transmit_pcs5_grayelecidleinferselout, wire_transmit_pcs4_grayelecidleinferselout, wire_transmit_pcs3_grayelecidleinferselout, wire_transmit_pcs2_grayelecidleinferselout, wire_transmit_pcs1_grayelecidleinferselout, wire_transmit_pcs0_grayelecidleinferselout},
int_autospdx4configsel = {wire_cent_unit1_autospdx4configsel, wire_cent_unit0_autospdx4configsel},
int_autospdx4rateswitchout = {wire_cent_unit1_autospdx4rateswitchout, wire_cent_unit0_autospdx4rateswitchout},
int_autospdx4spdchg = {wire_cent_unit1_autospdx4spdchg, wire_cent_unit0_autospdx4spdchg},
int_hipautospdrateswitchout = {wire_receive_pcs7_autospdrateswitchout, wire_receive_pcs6_autospdrateswitchout, wire_receive_pcs5_autospdrateswitchout, wire_receive_pcs4_autospdrateswitchout, wire_receive_pcs3_autospdrateswitchout, wire_receive_pcs2_autospdrateswitchout, wire_receive_pcs1_autospdrateswitchout, wire_receive_pcs0_autospdrateswitchout},
int_hiprateswtichdone = {wire_central_clk_div1_rateswitchdone, wire_central_clk_div0_rateswitchdone},
int_phfifiox4ptrsreset = {wire_cent_unit1_phfifiox4ptrsreset, wire_cent_unit0_phfifiox4ptrsreset},
int_pipeenrevparallellpbkfromtx = {wire_transmit_pcs7_pipeenrevparallellpbkout, wire_transmit_pcs6_pipeenrevparallellpbkout, wire_transmit_pcs5_pipeenrevparallellpbkout, wire_transmit_pcs4_pipeenrevparallellpbkout, wire_transmit_pcs3_pipeenrevparallellpbkout, wire_transmit_pcs2_pipeenrevparallellpbkout, wire_transmit_pcs1_pipeenrevparallellpbkout, wire_transmit_pcs0_pipeenrevparallellpbkout},
int_rateswitch = {int_rx_rateswitchout[4], int_rx_rateswitchout[0]},
int_rx_autospdspdchgout = {wire_receive_pcs7_autospdspdchgout, wire_receive_pcs6_autospdspdchgout, wire_receive_pcs5_autospdspdchgout, wire_receive_pcs4_autospdspdchgout, wire_receive_pcs3_autospdspdchgout, wire_receive_pcs2_autospdspdchgout, wire_receive_pcs1_autospdspdchgout, wire_receive_pcs0_autospdspdchgout},
int_rx_autospdxnconfigsel = {1'b0, int_autospdx4configsel[0], {2{1'b0}}, int_autospdx4configsel[0], {2{1'b0}}, int_autospdx4configsel[0], {2{1'b0}}, int_autospdx4configsel[0], 1'b0, int_autospdx4configsel[0], {2{1'b0}}, int_autospdx4configsel[0], {2{1'b0}}, int_autospdx4configsel[0], {2{1'b0}}, int_autospdx4configsel[0], {2{1'b0}}},
int_rx_autospdxnspdchg = {1'b0, int_rx_autospdspdchgout[4], {2{1'b0}}, int_rx_autospdspdchgout[4], {2{1'b0}}, int_rx_autospdspdchgout[4], {2{1'b0}}, int_rx_autospdspdchgout[4], 1'b0, int_autospdx4spdchg[0], {2{1'b0}}, int_autospdx4spdchg[0], {2{1'b0}}, int_autospdx4spdchg[0], {2{1'b0}}, int_autospdx4spdchg[0], {2{1'b0}}},
int_rx_coreclkout = {wire_receive_pcs7_coreclkout, wire_receive_pcs6_coreclkout, wire_receive_pcs5_coreclkout, wire_receive_pcs4_coreclkout, wire_receive_pcs3_coreclkout, wire_receive_pcs2_coreclkout, wire_receive_pcs1_coreclkout, wire_receive_pcs0_coreclkout},
int_rx_digitalreset_reg = {rx_digitalreset_reg0c[2]},
int_rx_iqpautospdxnspgchg = {{3{{2{1'b0}}}}, int_rx_autospdspdchgout[3], 1'b0, {4{{2{1'b0}}}}},
int_rx_iqpphfifobyteselout = {wire_receive_pcs7_iqpphfifobyteselout, wire_receive_pcs6_iqpphfifobyteselout, wire_receive_pcs5_iqpphfifobyteselout, wire_receive_pcs4_iqpphfifobyteselout, wire_receive_pcs3_iqpphfifobyteselout, wire_receive_pcs2_iqpphfifobyteselout, wire_receive_pcs1_iqpphfifobyteselout, wire_receive_pcs0_iqpphfifobyteselout},
int_rx_iqpphfifoptrsresetout = {wire_receive_pcs7_iqpphfifoptrsresetout, wire_receive_pcs6_iqpphfifoptrsresetout, wire_receive_pcs5_iqpphfifoptrsresetout, wire_receive_pcs4_iqpphfifoptrsresetout, wire_receive_pcs3_iqpphfifoptrsresetout, wire_receive_pcs2_iqpphfifoptrsresetout, wire_receive_pcs1_iqpphfifoptrsresetout, wire_receive_pcs0_iqpphfifoptrsresetout},
int_rx_iqpphfifordenableout = {wire_receive_pcs7_iqpphfifordenableout, wire_receive_pcs6_iqpphfifordenableout, wire_receive_pcs5_iqpphfifordenableout, wire_receive_pcs4_iqpphfifordenableout, wire_receive_pcs3_iqpphfifordenableout, wire_receive_pcs2_iqpphfifordenableout, wire_receive_pcs1_iqpphfifordenableout, wire_receive_pcs0_iqpphfifordenableout},
int_rx_iqpphfifowrclkout = {wire_receive_pcs7_iqpphfifowrclkout, wire_receive_pcs6_iqpphfifowrclkout, wire_receive_pcs5_iqpphfifowrclkout, wire_receive_pcs4_iqpphfifowrclkout, wire_receive_pcs3_iqpphfifowrclkout, wire_receive_pcs2_iqpphfifowrclkout, wire_receive_pcs1_iqpphfifowrclkout, wire_receive_pcs0_iqpphfifowrclkout},
int_rx_iqpphfifowrenableout = {wire_receive_pcs7_iqpphfifowrenableout, wire_receive_pcs6_iqpphfifowrenableout, wire_receive_pcs5_iqpphfifowrenableout, wire_receive_pcs4_iqpphfifowrenableout, wire_receive_pcs3_iqpphfifowrenableout, wire_receive_pcs2_iqpphfifowrenableout, wire_receive_pcs1_iqpphfifowrenableout, wire_receive_pcs0_iqpphfifowrenableout},
int_rx_iqpphfifoxnbytesel = {{3{{2{1'b0}}}}, int_rx_iqpphfifobyteselout[3], 1'b0, {4{{2{1'b0}}}}},
int_rx_iqpphfifoxnptrsreset = {{3{{2{1'b0}}}}, int_rx_iqpphfifoptrsresetout[3], 1'b0, {4{{2{1'b0}}}}},
int_rx_iqpphfifoxnrdenable = {{3{{2{1'b0}}}}, int_rx_iqpphfifordenableout[3], 1'b0, {4{{2{1'b0}}}}},
int_rx_iqpphfifoxnwrclk = {{3{{2{1'b0}}}}, int_rx_iqpphfifowrclkout[3], 1'b0, {4{{2{1'b0}}}}},
int_rx_iqpphfifoxnwrenable = {{3{{2{1'b0}}}}, int_rx_iqpphfifowrenableout[3], 1'b0, {4{{2{1'b0}}}}},
int_rx_phfifioxnptrsreset = {1'b0, int_rx_iqpphfifoptrsresetout[4], {2{1'b0}}, int_rx_iqpphfifoptrsresetout[4], {2{1'b0}}, int_rx_iqpphfifoptrsresetout[4], {2{1'b0}}, int_rx_iqpphfifoptrsresetout[4], 1'b0, int_phfifiox4ptrsreset[0], {2{1'b0}}, int_phfifiox4ptrsreset[0], {2{1'b0}}, int_phfifiox4ptrsreset[0], {2{1'b0}}, int_phfifiox4ptrsreset[0], {2{1'b0}}},
int_rx_phfifobyteserdisable = {wire_receive_pcs7_phfifobyteserdisableout, wire_receive_pcs6_phfifobyteserdisableout, wire_receive_pcs5_phfifobyteserdisableout, wire_receive_pcs4_phfifobyteserdisableout, wire_receive_pcs3_phfifobyteserdisableout, wire_receive_pcs2_phfifobyteserdisableout, wire_receive_pcs1_phfifobyteserdisableout, wire_receive_pcs0_phfifobyteserdisableout},
int_rx_phfifoptrsresetout = {wire_receive_pcs7_phfifoptrsresetout, wire_receive_pcs6_phfifoptrsresetout, wire_receive_pcs5_phfifoptrsresetout, wire_receive_pcs4_phfifoptrsresetout, wire_receive_pcs3_phfifoptrsresetout, wire_receive_pcs2_phfifoptrsresetout, wire_receive_pcs1_phfifoptrsresetout, wire_receive_pcs0_phfifoptrsresetout},
int_rx_phfifordenableout = {wire_receive_pcs7_phfifordenableout, wire_receive_pcs6_phfifordenableout, wire_receive_pcs5_phfifordenableout, wire_receive_pcs4_phfifordenableout, wire_receive_pcs3_phfifordenableout, wire_receive_pcs2_phfifordenableout, wire_receive_pcs1_phfifordenableout, wire_receive_pcs0_phfifordenableout},
int_rx_phfiforesetout = {wire_receive_pcs7_phfiforesetout, wire_receive_pcs6_phfiforesetout, wire_receive_pcs5_phfiforesetout, wire_receive_pcs4_phfiforesetout, wire_receive_pcs3_phfiforesetout, wire_receive_pcs2_phfiforesetout, wire_receive_pcs1_phfiforesetout, wire_receive_pcs0_phfiforesetout},
int_rx_phfifowrdisableout = {wire_receive_pcs7_phfifowrdisableout, wire_receive_pcs6_phfifowrdisableout, wire_receive_pcs5_phfifowrdisableout, wire_receive_pcs4_phfifowrdisableout, wire_receive_pcs3_phfifowrdisableout, wire_receive_pcs2_phfifowrdisableout, wire_receive_pcs1_phfifowrdisableout, wire_receive_pcs0_phfifowrdisableout},
int_rx_phfifoxnbytesel = {1'b0, int_rx_iqpphfifobyteselout[4], {2{1'b0}}, int_rx_iqpphfifobyteselout[4], {2{1'b0}}, int_rx_iqpphfifobyteselout[4], {2{1'b0}}, int_rx_iqpphfifobyteselout[4], 1'b0, int_rxphfifox4byteselout[0], {2{1'b0}}, int_rxphfifox4byteselout[0], {2{1'b0}}, int_rxphfifox4byteselout[0], {2{1'b0}}, int_rxphfifox4byteselout[0], {2{1'b0}}},
int_rx_phfifoxnrdenable = {1'b0, int_rx_iqpphfifordenableout[4], {2{1'b0}}, int_rx_iqpphfifordenableout[4], {2{1'b0}}, int_rx_iqpphfifordenableout[4], {2{1'b0}}, int_rx_iqpphfifordenableout[4], 1'b0, int_rxphfifox4rdenableout[0], {2{1'b0}}, int_rxphfifox4rdenableout[0], {2{1'b0}}, int_rxphfifox4rdenableout[0], {2{1'b0}}, int_rxphfifox4rdenableout[0], {2{1'b0}}},
int_rx_phfifoxnwrclk = {1'b0, int_rx_iqpphfifowrclkout[4], {2{1'b0}}, int_rx_iqpphfifowrclkout[4], {2{1'b0}}, int_rx_iqpphfifowrclkout[4], {2{1'b0}}, int_rx_iqpphfifowrclkout[4], 1'b0, int_rxphfifox4wrclkout[0], {2{1'b0}}, int_rxphfifox4wrclkout[0], {2{1'b0}}, int_rxphfifox4wrclkout[0], {2{1'b0}}, int_rxphfifox4wrclkout[0], {2{1'b0}}},
int_rx_phfifoxnwrenable = {1'b0, int_rx_iqpphfifowrenableout[4], {2{1'b0}}, int_rx_iqpphfifowrenableout[4], {2{1'b0}}, int_rx_iqpphfifowrenableout[4], {2{1'b0}}, int_rx_iqpphfifowrenableout[4], 1'b0, int_rxphfifox4wrenableout[0], {2{1'b0}}, int_rxphfifox4wrenableout[0], {2{1'b0}}, int_rxphfifox4wrenableout[0], {2{1'b0}}, int_rxphfifox4wrenableout[0], {2{1'b0}}},
int_rx_rateswitchout = {wire_receive_pcs7_rateswitchout, wire_receive_pcs6_rateswitchout, wire_receive_pcs5_rateswitchout, wire_receive_pcs4_rateswitchout, wire_receive_pcs3_rateswitchout, wire_receive_pcs2_rateswitchout, wire_receive_pcs1_rateswitchout, wire_receive_pcs0_rateswitchout},
int_rxcoreclk = {1'b0, int_rx_coreclkout[0]},
int_rxpcs_cdrctrlearlyeios = {wire_receive_pcs7_cdrctrlearlyeios, wire_receive_pcs6_cdrctrlearlyeios, wire_receive_pcs5_cdrctrlearlyeios, wire_receive_pcs4_cdrctrlearlyeios, wire_receive_pcs3_cdrctrlearlyeios, wire_receive_pcs2_cdrctrlearlyeios, wire_receive_pcs1_cdrctrlearlyeios, wire_receive_pcs0_cdrctrlearlyeios},
int_rxphfifordenable = {1'b0, int_rx_phfifordenableout[0]},
int_rxphfiforeset = {1'b0, int_rx_phfiforesetout[0]},
int_rxphfifox4byteselout = {wire_cent_unit1_rxphfifox4byteselout, wire_cent_unit0_rxphfifox4byteselout},
int_rxphfifox4rdenableout = {wire_cent_unit1_rxphfifox4rdenableout, wire_cent_unit0_rxphfifox4rdenableout},
int_rxphfifox4wrclkout = {wire_cent_unit1_rxphfifox4wrclkout, wire_cent_unit0_rxphfifox4wrclkout},
int_rxphfifox4wrenableout = {wire_cent_unit1_rxphfifox4wrenableout, wire_cent_unit0_rxphfifox4wrenableout},
int_tx_coreclkout = {wire_transmit_pcs7_coreclkout, wire_transmit_pcs6_coreclkout, wire_transmit_pcs5_coreclkout, wire_transmit_pcs4_coreclkout, wire_transmit_pcs3_coreclkout, wire_transmit_pcs2_coreclkout, wire_transmit_pcs1_coreclkout, wire_transmit_pcs0_coreclkout},
int_tx_digitalreset_reg = {tx_digitalreset_reg0c[2]},
int_tx_iqpphfifobyteselout = {wire_transmit_pcs7_iqpphfifobyteselout, wire_transmit_pcs6_iqpphfifobyteselout, wire_transmit_pcs5_iqpphfifobyteselout, wire_transmit_pcs4_iqpphfifobyteselout, wire_transmit_pcs3_iqpphfifobyteselout, wire_transmit_pcs2_iqpphfifobyteselout, wire_transmit_pcs1_iqpphfifobyteselout, wire_transmit_pcs0_iqpphfifobyteselout},
int_tx_iqpphfifordclkout = {wire_transmit_pcs7_iqpphfifordclkout, wire_transmit_pcs6_iqpphfifordclkout, wire_transmit_pcs5_iqpphfifordclkout, wire_transmit_pcs4_iqpphfifordclkout, wire_transmit_pcs3_iqpphfifordclkout, wire_transmit_pcs2_iqpphfifordclkout, wire_transmit_pcs1_iqpphfifordclkout, wire_transmit_pcs0_iqpphfifordclkout},
int_tx_iqpphfifordenableout = {wire_transmit_pcs7_iqpphfifordenableout, wire_transmit_pcs6_iqpphfifordenableout, wire_transmit_pcs5_iqpphfifordenableout, wire_transmit_pcs4_iqpphfifordenableout, wire_transmit_pcs3_iqpphfifordenableout, wire_transmit_pcs2_iqpphfifordenableout, wire_transmit_pcs1_iqpphfifordenableout, wire_transmit_pcs0_iqpphfifordenableout},
int_tx_iqpphfifowrenableout = {wire_transmit_pcs7_iqpphfifowrenableout, wire_transmit_pcs6_iqpphfifowrenableout, wire_transmit_pcs5_iqpphfifowrenableout, wire_transmit_pcs4_iqpphfifowrenableout, wire_transmit_pcs3_iqpphfifowrenableout, wire_transmit_pcs2_iqpphfifowrenableout, wire_transmit_pcs1_iqpphfifowrenableout, wire_transmit_pcs0_iqpphfifowrenableout},
int_tx_iqpphfifoxnbytesel = {{3{{2{1'b0}}}}, int_tx_iqpphfifobyteselout[3], 1'b0, {4{{2{1'b0}}}}},
int_tx_iqpphfifoxnrdclk = {{3{{2{1'b0}}}}, int_tx_iqpphfifordclkout[3], 1'b0, {4{{2{1'b0}}}}},
int_tx_iqpphfifoxnrdenable = {{3{{2{1'b0}}}}, int_tx_iqpphfifordenableout[3], 1'b0, {4{{2{1'b0}}}}},
int_tx_iqpphfifoxnwrenable = {{3{{2{1'b0}}}}, int_tx_iqpphfifowrenableout[3], 1'b0, {4{{2{1'b0}}}}},
int_tx_phfifioxnptrsreset = {1'b0, int_rx_iqpphfifoptrsresetout[4], {2{1'b0}}, int_rx_iqpphfifoptrsresetout[4], {2{1'b0}}, int_rx_iqpphfifoptrsresetout[4], {2{1'b0}}, int_rx_iqpphfifoptrsresetout[4], 1'b0, int_phfifiox4ptrsreset[0], {2{1'b0}}, int_phfifiox4ptrsreset[0], {2{1'b0}}, int_phfifiox4ptrsreset[0], {2{1'b0}}, int_phfifiox4ptrsreset[0], {2{1'b0}}},
int_tx_phfiforddisableout = {wire_transmit_pcs7_phfiforddisableout, wire_transmit_pcs6_phfiforddisableout, wire_transmit_pcs5_phfiforddisableout, wire_transmit_pcs4_phfiforddisableout, wire_transmit_pcs3_phfiforddisableout, wire_transmit_pcs2_phfiforddisableout, wire_transmit_pcs1_phfiforddisableout, wire_transmit_pcs0_phfiforddisableout},
int_tx_phfiforesetout = {wire_transmit_pcs7_phfiforesetout, wire_transmit_pcs6_phfiforesetout, wire_transmit_pcs5_phfiforesetout, wire_transmit_pcs4_phfiforesetout, wire_transmit_pcs3_phfiforesetout, wire_transmit_pcs2_phfiforesetout, wire_transmit_pcs1_phfiforesetout, wire_transmit_pcs0_phfiforesetout},
int_tx_phfifowrenableout = {wire_transmit_pcs7_phfifowrenableout, wire_transmit_pcs6_phfifowrenableout, wire_transmit_pcs5_phfifowrenableout, wire_transmit_pcs4_phfifowrenableout, wire_transmit_pcs3_phfifowrenableout, wire_transmit_pcs2_phfifowrenableout, wire_transmit_pcs1_phfifowrenableout, wire_transmit_pcs0_phfifowrenableout},
int_tx_phfifoxnbytesel = {1'b0, int_tx_iqpphfifobyteselout[4], {2{1'b0}}, int_tx_iqpphfifobyteselout[4], {2{1'b0}}, int_tx_iqpphfifobyteselout[4], {2{1'b0}}, int_tx_iqpphfifobyteselout[4], 1'b0, int_txphfifox4byteselout[0], {2{1'b0}}, int_txphfifox4byteselout[0], {2{1'b0}}, int_txphfifox4byteselout[0], {2{1'b0}}, int_txphfifox4byteselout[0], {2{1'b0}}},
int_tx_phfifoxnrdclk = {1'b0, int_tx_iqpphfifordclkout[4], {2{1'b0}}, int_tx_iqpphfifordclkout[4], {2{1'b0}}, int_tx_iqpphfifordclkout[4], {2{1'b0}}, int_tx_iqpphfifordclkout[4], 1'b0, int_txphfifox4rdclkout[0], {2{1'b0}}, int_txphfifox4rdclkout[0], {2{1'b0}}, int_txphfifox4rdclkout[0], {2{1'b0}}, int_txphfifox4rdclkout[0], {2{1'b0}}},
int_tx_phfifoxnrdenable = {1'b0, int_tx_iqpphfifordenableout[4], {2{1'b0}}, int_tx_iqpphfifordenableout[4], {2{1'b0}}, int_tx_iqpphfifordenableout[4], {2{1'b0}}, int_tx_iqpphfifordenableout[4], 1'b0, int_txphfifox4rdenableout[0], {2{1'b0}}, int_txphfifox4rdenableout[0], {2{1'b0}}, int_txphfifox4rdenableout[0], {2{1'b0}}, int_txphfifox4rdenableout[0], {2{1'b0}}},
int_tx_phfifoxnwrenable = {1'b0, int_tx_iqpphfifowrenableout[4], {2{1'b0}}, int_tx_iqpphfifowrenableout[4], {2{1'b0}}, int_tx_iqpphfifowrenableout[4], {2{1'b0}}, int_tx_iqpphfifowrenableout[4], 1'b0, int_txphfifox4wrenableout[0], {2{1'b0}}, int_txphfifox4wrenableout[0], {2{1'b0}}, int_txphfifox4wrenableout[0], {2{1'b0}}, int_txphfifox4wrenableout[0], {2{1'b0}}},
int_txcoreclk = {1'b0, int_tx_coreclkout[0]},
int_txphfiforddisable = {1'b0, int_tx_phfiforddisableout[0]},
int_txphfiforeset = {1'b0, int_tx_phfiforesetout[0]},
int_txphfifowrenable = {1'b0, int_tx_phfifowrenableout[0]},
int_txphfifox4byteselout = {wire_cent_unit1_txphfifox4byteselout, wire_cent_unit0_txphfifox4byteselout},
int_txphfifox4rdclkout = {wire_cent_unit1_txphfifox4rdclkout, wire_cent_unit0_txphfifox4rdclkout},
int_txphfifox4rdenableout = {wire_cent_unit1_txphfifox4rdenableout, wire_cent_unit0_txphfifox4rdenableout},
int_txphfifox4wrenableout = {wire_cent_unit1_txphfifox4wrenableout, wire_cent_unit0_txphfifox4wrenableout},
nonusertocmu_out = {wire_cal_blk1_nonusertocmu, wire_cal_blk0_nonusertocmu},
pipedatavalid = {pipedatavalid_out[7:0]},
pipedatavalid_out = {wire_receive_pcs7_pipedatavalid, wire_receive_pcs6_pipedatavalid, wire_receive_pcs5_pipedatavalid, wire_receive_pcs4_pipedatavalid, wire_receive_pcs3_pipedatavalid, wire_receive_pcs2_pipedatavalid, wire_receive_pcs1_pipedatavalid, wire_receive_pcs0_pipedatavalid},
pipeelecidle = {pipeelecidle_out[7:0]},
pipeelecidle_out = {wire_receive_pcs7_pipeelecidle, wire_receive_pcs6_pipeelecidle, wire_receive_pcs5_pipeelecidle, wire_receive_pcs4_pipeelecidle, wire_receive_pcs3_pipeelecidle, wire_receive_pcs2_pipeelecidle, wire_receive_pcs1_pipeelecidle, wire_receive_pcs0_pipeelecidle},
pipephydonestatus = {wire_receive_pcs7_pipephydonestatus, wire_receive_pcs6_pipephydonestatus, wire_receive_pcs5_pipephydonestatus, wire_receive_pcs4_pipephydonestatus, wire_receive_pcs3_pipephydonestatus, wire_receive_pcs2_pipephydonestatus, wire_receive_pcs1_pipephydonestatus, wire_receive_pcs0_pipephydonestatus},
pipestatus = {wire_receive_pcs7_pipestatus, wire_receive_pcs6_pipestatus, wire_receive_pcs5_pipestatus, wire_receive_pcs4_pipestatus, wire_receive_pcs3_pipestatus, wire_receive_pcs2_pipestatus, wire_receive_pcs1_pipestatus, wire_receive_pcs0_pipestatus},
pll0_clkin = {{10{1'b0}}, {9{1'b0}}, pll_inclk_wire[0]},
pll0_dprioin = {{300{1'b0}}, cent_unit_cmuplldprioout[1499:1200]},
pll0_dprioout = {{300{1'b0}}, wire_tx_pll0_dprioout},
pll0_out = {{4{1'b0}}, wire_tx_pll0_clk[3:0]},
pll_ch_dataout_wire = {wire_rx_cdr_pll7_dataout, wire_rx_cdr_pll6_dataout, wire_rx_cdr_pll5_dataout, wire_rx_cdr_pll4_dataout, wire_rx_cdr_pll3_dataout, wire_rx_cdr_pll2_dataout, wire_rx_cdr_pll1_dataout, wire_rx_cdr_pll0_dataout},
pll_ch_dprioout = {wire_rx_cdr_pll7_dprioout, wire_rx_cdr_pll6_dprioout, wire_rx_cdr_pll5_dprioout, wire_rx_cdr_pll4_dprioout, wire_rx_cdr_pll3_dprioout, wire_rx_cdr_pll2_dprioout, wire_rx_cdr_pll1_dprioout, wire_rx_cdr_pll0_dprioout},
pll_cmuplldprioout = {{600{1'b0}}, pll_ch_dprioout[2399:1200], {300{1'b0}}, pll0_dprioout[299:0], pll_ch_dprioout[1199:0]},
pll_inclk_wire = {pll_inclk},
pll_locked = {pll_locked_out[0]},
pll_locked_out = {1'b0, wire_tx_pll0_locked},
pll_powerdown = 1'b0,
pllpowerdn_in = {{2{1'b0}}, 1'b0, cent_unit_pllpowerdn[0]},
pllreset_in = {{2{1'b0}}, 1'b0, cent_unit_pllresetout[0]},
reconfig_fromgxb = {rx_pma_analogtestbus[33:18], wire_cent_unit1_dprioout, rx_pma_analogtestbus[16:1], wire_cent_unit0_dprioout},
reconfig_togxb_busy = reconfig_togxb[3],
reconfig_togxb_disable = reconfig_togxb[1],
reconfig_togxb_in = reconfig_togxb[0],
reconfig_togxb_load = reconfig_togxb[2],
refclk_pma = {wire_central_clk_div1_refclkout, wire_central_clk_div0_refclkout},
rx_analogreset_in = {{4{1'b0}}, {8{((~ reconfig_togxb_busy) & rx_analogreset[0])}}},
rx_analogreset_out = {wire_cent_unit1_rxanalogresetout[5:0], wire_cent_unit0_rxanalogresetout[5:0]},
rx_coreclk_in = {8{coreclkout_bi_quad_wire[0]}},
rx_cruclk_in = {{9{1'b0}}, rx_pldcruclk_in[7], {9{1'b0}}, rx_pldcruclk_in[6], {9{1'b0}}, rx_pldcruclk_in[5], {9{1'b0}}, rx_pldcruclk_in[4], {9{1'b0}}, rx_pldcruclk_in[3], {9{1'b0}}, rx_pldcruclk_in[2], {9{1'b0}}, rx_pldcruclk_in[1], {9{1'b0}}, rx_pldcruclk_in[0]},
rx_ctrldetect = {wire_receive_pcs7_ctrldetect[1:0], wire_receive_pcs6_ctrldetect[1:0], wire_receive_pcs5_ctrldetect[1:0], wire_receive_pcs4_ctrldetect[1:0], wire_receive_pcs3_ctrldetect[1:0], wire_receive_pcs2_ctrldetect[1:0], wire_receive_pcs1_ctrldetect[1:0], wire_receive_pcs0_ctrldetect[1:0]},
rx_dataout = {rx_out_wire[127:0]},
rx_deserclock_in = {rx_pll_clkout[31:0]},
rx_digitalreset_in = {8{int_rx_digitalreset_reg[0]}},
rx_digitalreset_out = {wire_cent_unit1_rxdigitalresetout[3:0], wire_cent_unit0_rxdigitalresetout[3:0]},
rx_elecidleinfersel = {24{1'b0}},
rx_enapatternalign = {8{1'b0}},
rx_freqlocked = {(rx_freqlocked_wire[7] & (~ rx_analogreset[0])), (rx_freqlocked_wire[6] & (~ rx_analogreset[0])), (rx_freqlocked_wire[5] & (~ rx_analogreset[0])), (rx_freqlocked_wire[4] & (~ rx_analogreset[0])), (rx_freqlocked_wire[3] & (~ rx_analogreset[0])), (rx_freqlocked_wire[2] & (~ rx_analogreset[0])), (rx_freqlocked_wire[1] & (~ rx_analogreset[0])), (rx_freqlocked_wire[0] & (~ rx_analogreset[0]))},
rx_freqlocked_wire = {wire_rx_cdr_pll7_freqlocked, wire_rx_cdr_pll6_freqlocked, wire_rx_cdr_pll5_freqlocked, wire_rx_cdr_pll4_freqlocked, wire_rx_cdr_pll3_freqlocked, wire_rx_cdr_pll2_freqlocked, wire_rx_cdr_pll1_freqlocked, wire_rx_cdr_pll0_freqlocked},
rx_locktodata = {8{1'b0}},
rx_locktodata_wire = {((~ reconfig_togxb_busy) & rx_locktodata[7]), ((~ reconfig_togxb_busy) & rx_locktodata[6]), ((~ reconfig_togxb_busy) & rx_locktodata[5]), ((~ reconfig_togxb_busy) & rx_locktodata[4]), ((~ reconfig_togxb_busy) & rx_locktodata[3]), ((~ reconfig_togxb_busy) & rx_locktodata[2]), ((~ reconfig_togxb_busy) & rx_locktodata[1]), ((~ reconfig_togxb_busy) & rx_locktodata[0])},
rx_locktorefclk_wire = {wire_receive_pcs7_cdrctrllocktorefclkout, wire_receive_pcs6_cdrctrllocktorefclkout, wire_receive_pcs5_cdrctrllocktorefclkout, wire_receive_pcs4_cdrctrllocktorefclkout, wire_receive_pcs3_cdrctrllocktorefclkout, wire_receive_pcs2_cdrctrllocktorefclkout, wire_receive_pcs1_cdrctrllocktorefclkout, wire_receive_pcs0_cdrctrllocktorefclkout},
rx_out_wire = {wire_receive_pcs7_dataout[15:0], wire_receive_pcs6_dataout[15:0], wire_receive_pcs5_dataout[15:0], wire_receive_pcs4_dataout[15:0], wire_receive_pcs3_dataout[15:0], wire_receive_pcs2_dataout[15:0], wire_receive_pcs1_dataout[15:0], wire_receive_pcs0_dataout[15:0]},
rx_patterndetect = {wire_receive_pcs7_patterndetect[1:0], wire_receive_pcs6_patterndetect[1:0], wire_receive_pcs5_patterndetect[1:0], wire_receive_pcs4_patterndetect[1:0], wire_receive_pcs3_patterndetect[1:0], wire_receive_pcs2_patterndetect[1:0], wire_receive_pcs1_patterndetect[1:0], wire_receive_pcs0_patterndetect[1:0]},
rx_pcs_rxfound_wire = {txdetectrxout[7], tx_rxfoundout[7], txdetectrxout[6], tx_rxfoundout[6], txdetectrxout[5], tx_rxfoundout[5], txdetectrxout[4], tx_rxfoundout[4], txdetectrxout[3], tx_rxfoundout[3], txdetectrxout[2], tx_rxfoundout[2], txdetectrxout[1], tx_rxfoundout[1], txdetectrxout[0], tx_rxfoundout[0]},
rx_pcsdprioin_wire = {cent_unit_rxpcsdprioout[3199:0]},
rx_pcsdprioout = {wire_receive_pcs7_dprioout, wire_receive_pcs6_dprioout, wire_receive_pcs5_dprioout, wire_receive_pcs4_dprioout, wire_receive_pcs3_dprioout, wire_receive_pcs2_dprioout, wire_receive_pcs1_dprioout, wire_receive_pcs0_dprioout},
rx_phfifordenable = {8{1'b1}},
rx_phfiforeset = {8{1'b0}},
rx_phfifowrdisable = {8{1'b0}},
rx_pipestatetransdoneout = {wire_receive_pcs7_pipestatetransdoneout, wire_receive_pcs6_pipestatetransdoneout, wire_receive_pcs5_pipestatetransdoneout, wire_receive_pcs4_pipestatetransdoneout, wire_receive_pcs3_pipestatetransdoneout, wire_receive_pcs2_pipestatetransdoneout, wire_receive_pcs1_pipestatetransdoneout, wire_receive_pcs0_pipestatetransdoneout},
rx_pldcruclk_in = {rx_cruclk[7:0]},
rx_pll_clkout = {wire_rx_cdr_pll7_clk, wire_rx_cdr_pll6_clk, wire_rx_cdr_pll5_clk, wire_rx_cdr_pll4_clk, wire_rx_cdr_pll3_clk, wire_rx_cdr_pll2_clk, wire_rx_cdr_pll1_clk, wire_rx_cdr_pll0_clk},
rx_pll_locked = {(rx_plllocked_wire[7] & (~ rx_analogreset[0])), (rx_plllocked_wire[6] & (~ rx_analogreset[0])), (rx_plllocked_wire[5] & (~ rx_analogreset[0])), (rx_plllocked_wire[4] & (~ rx_analogreset[0])), (rx_plllocked_wire[3] & (~ rx_analogreset[0])), (rx_plllocked_wire[2] & (~ rx_analogreset[0])), (rx_plllocked_wire[1] & (~ rx_analogreset[0])), (rx_plllocked_wire[0] & (~ rx_analogreset[0]))},
rx_pll_pfdrefclkout_wire = {wire_rx_cdr_pll7_pfdrefclkout, wire_rx_cdr_pll6_pfdrefclkout, wire_rx_cdr_pll5_pfdrefclkout, wire_rx_cdr_pll4_pfdrefclkout, wire_rx_cdr_pll3_pfdrefclkout, wire_rx_cdr_pll2_pfdrefclkout, wire_rx_cdr_pll1_pfdrefclkout, wire_rx_cdr_pll0_pfdrefclkout},
rx_plllocked_wire = {wire_rx_cdr_pll7_locked, wire_rx_cdr_pll6_locked, wire_rx_cdr_pll5_locked, wire_rx_cdr_pll4_locked, wire_rx_cdr_pll3_locked, wire_rx_cdr_pll2_locked, wire_rx_cdr_pll1_locked, wire_rx_cdr_pll0_locked},
rx_pma_analogtestbus = {{102{1'b0}}, wire_receive_pma7_analogtestbus[5:2], wire_receive_pma6_analogtestbus[5:2], wire_receive_pma5_analogtestbus[5:2], wire_receive_pma4_analogtestbus[5:2], 1'b0, wire_receive_pma3_analogtestbus[5:2], wire_receive_pma2_analogtestbus[5:2], wire_receive_pma1_analogtestbus[5:2], wire_receive_pma0_analogtestbus[5:2], 1'b0},
rx_pma_clockout = {wire_receive_pma7_clockout, wire_receive_pma6_clockout, wire_receive_pma5_clockout, wire_receive_pma4_clockout, wire_receive_pma3_clockout, wire_receive_pma2_clockout, wire_receive_pma1_clockout, wire_receive_pma0_clockout},
rx_pma_dataout = {wire_receive_pma7_dataout, wire_receive_pma6_dataout, wire_receive_pma5_dataout, wire_receive_pma4_dataout, wire_receive_pma3_dataout, wire_receive_pma2_dataout, wire_receive_pma1_dataout, wire_receive_pma0_dataout},
rx_pma_locktorefout = {wire_receive_pma7_locktorefout, wire_receive_pma6_locktorefout, wire_receive_pma5_locktorefout, wire_receive_pma4_locktorefout, wire_receive_pma3_locktorefout, wire_receive_pma2_locktorefout, wire_receive_pma1_locktorefout, wire_receive_pma0_locktorefout},
rx_pma_recoverdataout_wire = {wire_receive_pma7_recoverdataout[19:0], wire_receive_pma6_recoverdataout[19:0], wire_receive_pma5_recoverdataout[19:0], wire_receive_pma4_recoverdataout[19:0], wire_receive_pma3_recoverdataout[19:0], wire_receive_pma2_recoverdataout[19:0], wire_receive_pma1_recoverdataout[19:0], wire_receive_pma0_recoverdataout[19:0]},
rx_pmadprioin_wire = {{2{{300{1'b0}}}}, cent_unit_rxpmadprioout[2999:1800], {2{{300{1'b0}}}}, cent_unit_rxpmadprioout[1199:0]},
rx_pmadprioout = {{2{{300{1'b0}}}}, wire_receive_pma7_dprioout, wire_receive_pma6_dprioout, wire_receive_pma5_dprioout, wire_receive_pma4_dprioout, {2{{300{1'b0}}}}, wire_receive_pma3_dprioout, wire_receive_pma2_dprioout, wire_receive_pma1_dprioout, wire_receive_pma0_dprioout},
rx_powerdown = {8{1'b0}},
rx_powerdown_in = {{4{1'b0}}, rx_powerdown[7:0]},
rx_prbscidenable = {8{1'b0}},
rx_revparallelfdbkdata = {wire_receive_pcs7_revparallelfdbkdata, wire_receive_pcs6_revparallelfdbkdata, wire_receive_pcs5_revparallelfdbkdata, wire_receive_pcs4_revparallelfdbkdata, wire_receive_pcs3_revparallelfdbkdata, wire_receive_pcs2_revparallelfdbkdata, wire_receive_pcs1_revparallelfdbkdata, wire_receive_pcs0_revparallelfdbkdata},
rx_rmfiforeset = {8{1'b0}},
rx_rxcruresetout = {wire_cent_unit1_rxcruresetout[5:0], wire_cent_unit0_rxcruresetout[5:0]},
rx_signaldetect_wire = {wire_receive_pma7_signaldetect, wire_receive_pma6_signaldetect, wire_receive_pma5_signaldetect, wire_receive_pma4_signaldetect, wire_receive_pma3_signaldetect, wire_receive_pma2_signaldetect, wire_receive_pma1_signaldetect, wire_receive_pma0_signaldetect},
rx_syncstatus = {wire_receive_pcs7_syncstatus[1:0], wire_receive_pcs6_syncstatus[1:0], wire_receive_pcs5_syncstatus[1:0], wire_receive_pcs4_syncstatus[1:0], wire_receive_pcs3_syncstatus[1:0], wire_receive_pcs2_syncstatus[1:0], wire_receive_pcs1_syncstatus[1:0], wire_receive_pcs0_syncstatus[1:0]},
rxphfifowrdisable = {1'b0, int_rx_phfifowrdisableout[0]},
rxpll_dprioin = {{2{{300{1'b0}}}}, cent_unit_cmuplldprioout[2999:1800], {2{{300{1'b0}}}}, cent_unit_cmuplldprioout[1199:0]},
tx_analogreset_out = {wire_cent_unit1_txanalogresetout[5:0], wire_cent_unit0_txanalogresetout[5:0]},
tx_coreclk_in = {8{coreclkout_bi_quad_wire[0]}},
tx_datain_wire = {tx_datain[127:0]},
tx_dataout = {wire_transmit_pma7_dataout, wire_transmit_pma6_dataout, wire_transmit_pma5_dataout, wire_transmit_pma4_dataout, wire_transmit_pma3_dataout, wire_transmit_pma2_dataout, wire_transmit_pma1_dataout, wire_transmit_pma0_dataout},
tx_dataout_pcs_to_pma = {wire_transmit_pcs7_dataout, wire_transmit_pcs6_dataout, wire_transmit_pcs5_dataout, wire_transmit_pcs4_dataout, wire_transmit_pcs3_dataout, wire_transmit_pcs2_dataout, wire_transmit_pcs1_dataout, wire_transmit_pcs0_dataout},
tx_digitalreset_in = {8{int_tx_digitalreset_reg[0]}},
tx_digitalreset_out = {wire_cent_unit1_txdigitalresetout[3:0], wire_cent_unit0_txdigitalresetout[3:0]},
tx_dprioin_wire = {{1200{1'b0}}, cent_unit_txdprioout[1199:0]},
tx_forcedisp_wire = {1'b0, tx_forcedispcompliance[7], 1'b0, tx_forcedispcompliance[6], 1'b0, tx_forcedispcompliance[5], 1'b0, tx_forcedispcompliance[4], 1'b0, tx_forcedispcompliance[3], 1'b0, tx_forcedispcompliance[2], 1'b0, tx_forcedispcompliance[1], 1'b0, tx_forcedispcompliance[0]},
tx_invpolarity = {8{1'b0}},
tx_localrefclk = {wire_transmit_pma7_clockout, wire_transmit_pma6_clockout, wire_transmit_pma5_clockout, wire_transmit_pma4_clockout, wire_transmit_pma3_clockout, wire_transmit_pma2_clockout, wire_transmit_pma1_clockout, wire_transmit_pma0_clockout},
tx_pcs_forceelecidleout = {wire_transmit_pcs7_forceelecidleout, wire_transmit_pcs6_forceelecidleout, wire_transmit_pcs5_forceelecidleout, wire_transmit_pcs4_forceelecidleout, wire_transmit_pcs3_forceelecidleout, wire_transmit_pcs2_forceelecidleout, wire_transmit_pcs1_forceelecidleout, wire_transmit_pcs0_forceelecidleout},
tx_phfiforeset = {8{1'b0}},
tx_pipepowerdownout = {wire_transmit_pcs7_pipepowerdownout, wire_transmit_pcs6_pipepowerdownout, wire_transmit_pcs5_pipepowerdownout, wire_transmit_pcs4_pipepowerdownout, wire_transmit_pcs3_pipepowerdownout, wire_transmit_pcs2_pipepowerdownout, wire_transmit_pcs1_pipepowerdownout, wire_transmit_pcs0_pipepowerdownout},
tx_pipepowerstateout = {wire_transmit_pcs7_pipepowerstateout, wire_transmit_pcs6_pipepowerstateout, wire_transmit_pcs5_pipepowerstateout, wire_transmit_pcs4_pipepowerstateout, wire_transmit_pcs3_pipepowerstateout, wire_transmit_pcs2_pipepowerstateout, wire_transmit_pcs1_pipepowerstateout, wire_transmit_pcs0_pipepowerstateout},
tx_pipeswing = {8{1'b0}},
tx_pmadprioin_wire = {{2{{300{1'b0}}}}, cent_unit_txpmadprioout[2999:1800], {2{{300{1'b0}}}}, cent_unit_txpmadprioout[1199:0]},
tx_pmadprioout = {{2{{300{1'b0}}}}, wire_transmit_pma7_dprioout, wire_transmit_pma6_dprioout, wire_transmit_pma5_dprioout, wire_transmit_pma4_dprioout, {2{{300{1'b0}}}}, wire_transmit_pma3_dprioout, wire_transmit_pma2_dprioout, wire_transmit_pma1_dprioout, wire_transmit_pma0_dprioout},
tx_revparallellpbken = {8{1'b0}},
tx_rxdetectvalidout = {wire_transmit_pma7_rxdetectvalidout, wire_transmit_pma6_rxdetectvalidout, wire_transmit_pma5_rxdetectvalidout, wire_transmit_pma4_rxdetectvalidout, wire_transmit_pma3_rxdetectvalidout, wire_transmit_pma2_rxdetectvalidout, wire_transmit_pma1_rxdetectvalidout, wire_transmit_pma0_rxdetectvalidout},
tx_rxfoundout = {wire_transmit_pma7_rxfoundout, wire_transmit_pma6_rxfoundout, wire_transmit_pma5_rxfoundout, wire_transmit_pma4_rxfoundout, wire_transmit_pma3_rxfoundout, wire_transmit_pma2_rxfoundout, wire_transmit_pma1_rxfoundout, wire_transmit_pma0_rxfoundout},
tx_txdprioout = {wire_transmit_pcs7_dprioout, wire_transmit_pcs6_dprioout, wire_transmit_pcs5_dprioout, wire_transmit_pcs4_dprioout, wire_transmit_pcs3_dprioout, wire_transmit_pcs2_dprioout, wire_transmit_pcs1_dprioout, wire_transmit_pcs0_dprioout},
txdetectrxout = {wire_transmit_pcs7_txdetectrx, wire_transmit_pcs6_txdetectrx, wire_transmit_pcs5_txdetectrx, wire_transmit_pcs4_txdetectrx, wire_transmit_pcs3_txdetectrx, wire_transmit_pcs2_txdetectrx, wire_transmit_pcs1_txdetectrx, wire_transmit_pcs0_txdetectrx},
w_cent_unit_dpriodisableout1w = {wire_cent_unit1_dpriodisableout, wire_cent_unit0_dpriodisableout};
endmodule //altpcie_serdes_4sgx_x8d_gen2_08p_alt4gxb_q0ea
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altpcie_serdes_4sgx_x8d_gen2_08p (
cal_blk_clk,
gxb_powerdown,
pipe8b10binvpolarity,
pll_inclk,
powerdn,
rateswitch,
reconfig_clk,
reconfig_togxb,
rx_analogreset,
rx_cruclk,
rx_datain,
rx_digitalreset,
tx_ctrlenable,
tx_datain,
tx_detectrxloop,
tx_digitalreset,
tx_forcedispcompliance,
tx_forceelecidle,
tx_pipedeemph,
tx_pipemargin,
coreclkout,
pipedatavalid,
pipeelecidle,
pipephydonestatus,
pipestatus,
pll_locked,
reconfig_fromgxb,
rx_ctrldetect,
rx_dataout,
rx_freqlocked,
rx_patterndetect,
rx_pll_locked,
rx_syncstatus,
tx_dataout);
input cal_blk_clk;
input [0:0] gxb_powerdown;
input [7:0] pipe8b10binvpolarity;
input pll_inclk;
input [15:0] powerdn;
input [0:0] rateswitch;
input reconfig_clk;
input [3:0] reconfig_togxb;
input [0:0] rx_analogreset;
input [7:0] rx_cruclk;
input [7:0] rx_datain;
input [0:0] rx_digitalreset;
input [15:0] tx_ctrlenable;
input [127:0] tx_datain;
input [7:0] tx_detectrxloop;
input [0:0] tx_digitalreset;
input [7:0] tx_forcedispcompliance;
input [7:0] tx_forceelecidle;
input [7:0] tx_pipedeemph;
input [23:0] tx_pipemargin;
output [0:0] coreclkout;
output [7:0] pipedatavalid;
output [7:0] pipeelecidle;
output [7:0] pipephydonestatus;
output [23:0] pipestatus;
output [0:0] pll_locked;
output [33:0] reconfig_fromgxb;
output [15:0] rx_ctrldetect;
output [127:0] rx_dataout;
output [7:0] rx_freqlocked;
output [15:0] rx_patterndetect;
output [7:0] rx_pll_locked;
output [15:0] rx_syncstatus;
output [7:0] tx_dataout;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [7:0] rx_cruclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
parameter starting_channel_number = 0;
wire [15:0] sub_wire0;
wire [7:0] sub_wire1;
wire [0:0] sub_wire2;
wire [33:0] sub_wire3;
wire [7:0] sub_wire4;
wire [23:0] sub_wire5;
wire [7:0] sub_wire6;
wire [15:0] sub_wire7;
wire [0:0] sub_wire8;
wire [127:0] sub_wire9;
wire [7:0] sub_wire10;
wire [7:0] sub_wire11;
wire [15:0] sub_wire12;
wire [7:0] sub_wire13;
wire [15:0] rx_patterndetect = sub_wire0[15:0];
wire [7:0] pipephydonestatus = sub_wire1[7:0];
wire [0:0] pll_locked = sub_wire2[0:0];
wire [33:0] reconfig_fromgxb = sub_wire3[33:0];
wire [7:0] rx_freqlocked = sub_wire4[7:0];
wire [23:0] pipestatus = sub_wire5[23:0];
wire [7:0] rx_pll_locked = sub_wire6[7:0];
wire [15:0] rx_syncstatus = sub_wire7[15:0];
wire [0:0] coreclkout = sub_wire8[0:0];
wire [127:0] rx_dataout = sub_wire9[127:0];
wire [7:0] pipeelecidle = sub_wire10[7:0];
wire [7:0] tx_dataout = sub_wire11[7:0];
wire [15:0] rx_ctrldetect = sub_wire12[15:0];
wire [7:0] pipedatavalid = sub_wire13[7:0];
altpcie_serdes_4sgx_x8d_gen2_08p_alt4gxb_q0ea altpcie_serdes_4sgx_x8d_gen2_08p_alt4gxb_q0ea_component (
.reconfig_togxb (reconfig_togxb),
.cal_blk_clk (cal_blk_clk),
.tx_forceelecidle (tx_forceelecidle),
.rx_datain (rx_datain),
.rx_digitalreset (rx_digitalreset),
.pipe8b10binvpolarity (pipe8b10binvpolarity),
.tx_datain (tx_datain),
.tx_digitalreset (tx_digitalreset),
.tx_pipedeemph (tx_pipedeemph),
.gxb_powerdown (gxb_powerdown),
.rx_cruclk (rx_cruclk),
.tx_forcedispcompliance (tx_forcedispcompliance),
.rateswitch (rateswitch),
.reconfig_clk (reconfig_clk),
.rx_analogreset (rx_analogreset),
.powerdn (powerdn),
.tx_ctrlenable (tx_ctrlenable),
.tx_pipemargin (tx_pipemargin),
.pll_inclk (pll_inclk),
.tx_detectrxloop (tx_detectrxloop),
.rx_patterndetect (sub_wire0),
.pipephydonestatus (sub_wire1),
.pll_locked (sub_wire2),
.reconfig_fromgxb (sub_wire3),
.rx_freqlocked (sub_wire4),
.pipestatus (sub_wire5),
.rx_pll_locked (sub_wire6),
.rx_syncstatus (sub_wire7),
.coreclkout (sub_wire8),
.rx_dataout (sub_wire9),
.pipeelecidle (sub_wire10),
.tx_dataout (sub_wire11),
.rx_ctrldetect (sub_wire12),
.pipedatavalid (sub_wire13));
defparam
altpcie_serdes_4sgx_x8d_gen2_08p_alt4gxb_q0ea_component.starting_channel_number = starting_channel_number;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: NUM_KEYS NUMERIC "0"
// Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
// Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
// Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE STRING "5000.0"
// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE_ENABLE STRING "0"
// Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "5000"
// Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2000"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "100"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "100"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "PCI Express (PIPE)"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "100.0"
// Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "100.0"
// Retrieval info: PRIVATE: WIZ_INPUT_A STRING "5000"
// Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
// Retrieval info: PRIVATE: WIZ_INPUT_B STRING "100.0"
// Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
// Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "PCI Express (PIPE)"
// Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "Gen 2-x8"
// Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
// Retrieval info: PARAMETER: STARTING_CHANNEL_NUMBER NUMERIC "0"
// Retrieval info: CONSTANT: EFFECTIVE_DATA_RATE STRING "5000 Mbps"
// Retrieval info: CONSTANT: ENABLE_LC_TX_PLL STRING "false"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_A_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_B_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_C_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_D_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_V_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "1"
// Retrieval info: CONSTANT: GEN_RECONFIG_PLL STRING "false"
// Retrieval info: CONSTANT: GXB_ANALOG_POWER STRING "3.0v"
// Retrieval info: CONSTANT: GX_CHANNEL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: INPUT_CLOCK_FREQUENCY STRING "100.0 MHz"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: INTENDED_DEVICE_SPEED_GRADE STRING "2"
// Retrieval info: CONSTANT: INTENDED_DEVICE_VARIANT STRING "GX"
// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "none"
// Retrieval info: CONSTANT: LPM_TYPE STRING "alt4gxb"
// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "8"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
// Retrieval info: CONSTANT: PLL_CONTROL_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: PLL_PFD_FB_MODE STRING "internal"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: PROTOCOL STRING "pcie2"
// Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "1"
// Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal"
// Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100"
// Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10"
// Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
// Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "true"
// Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
// Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "NONE"
// Retrieval info: CONSTANT: RX_CHANNEL_BONDING STRING "x8"
// Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.82v"
// Retrieval info: CONSTANT: RX_CRU_BANDWIDTH_TYPE STRING "Auto"
// Retrieval info: CONSTANT: RX_CRU_INCLOCK0_PERIOD NUMERIC "10000"
// Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "pipe"
// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "5000"
// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
// Retrieval info: CONSTANT: RX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_SELF_TEST_MODE STRING "false"
// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "true"
// Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "32"
// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "11010000111010000011"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "00101111000101111100"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "20"
// Retrieval info: CONSTANT: RX_RUN_LENGTH NUMERIC "40"
// Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "true"
// Retrieval info: CONSTANT: RX_SIGNAL_DETECT_THRESHOLD NUMERIC "4"
// Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true"
// Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "false"
// Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false"
// Retrieval info: CONSTANT: RX_USE_CRUCLK STRING "true"
// Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false"
// Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "true"
// Retrieval info: CONSTANT: RX_USE_PIPE8B10BINVPOLARITY STRING "true"
// Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false"
// Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
// Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal"
// Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false"
// Retrieval info: CONSTANT: TX_ANALOG_POWER STRING "AUTO"
// Retrieval info: CONSTANT: TX_CHANNEL_BONDING STRING "x8"
// Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: TX_CLKOUT_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.65v"
// Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "5000"
// Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
// Retrieval info: CONSTANT: TX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
// Retrieval info: CONSTANT: TX_ENABLE_SELF_TEST_MODE STRING "false"
// Retrieval info: CONSTANT: TX_PLL_BANDWIDTH_TYPE STRING "High"
// Retrieval info: CONSTANT: TX_PLL_INCLK0_PERIOD NUMERIC "10000"
// Retrieval info: CONSTANT: TX_PLL_TYPE STRING "CMU"
// Retrieval info: CONSTANT: TX_SLEW_RATE STRING "off"
// Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "pipe"
// Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false"
// Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "true"
// Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "3"
// Retrieval info: CONSTANT: coreclkout_control_width NUMERIC "1"
// Retrieval info: CONSTANT: elec_idle_infer_enable STRING "false"
// Retrieval info: CONSTANT: enable_0ppm STRING "false"
// Retrieval info: CONSTANT: gxb_powerdown_width NUMERIC "1"
// Retrieval info: CONSTANT: number_of_quads NUMERIC "2"
// Retrieval info: CONSTANT: rateswitch_control_width NUMERIC "1"
// Retrieval info: CONSTANT: reconfig_calibration STRING "true"
// Retrieval info: CONSTANT: reconfig_fromgxb_port_width NUMERIC "34"
// Retrieval info: CONSTANT: reconfig_togxb_port_width NUMERIC "4"
// Retrieval info: CONSTANT: rx_cdrctrl_enable STRING "true"
// Retrieval info: CONSTANT: rx_cru_m_divider NUMERIC "25"
// Retrieval info: CONSTANT: rx_cru_n_divider NUMERIC "1"
// Retrieval info: CONSTANT: rx_cru_vco_post_scale_divider NUMERIC "1"
// Retrieval info: CONSTANT: rx_dwidth_factor NUMERIC "2"
// Retrieval info: CONSTANT: rx_signal_detect_loss_threshold STRING "3"
// Retrieval info: CONSTANT: rx_signal_detect_valid_threshold STRING "14"
// Retrieval info: CONSTANT: rx_use_external_termination STRING "false"
// Retrieval info: CONSTANT: rx_word_aligner_num_byte NUMERIC "1"
// Retrieval info: CONSTANT: tx_dwidth_factor NUMERIC "2"
// Retrieval info: CONSTANT: tx_pll_clock_post_divider NUMERIC "1"
// Retrieval info: CONSTANT: tx_pll_m_divider NUMERIC "25"
// Retrieval info: CONSTANT: tx_pll_n_divider NUMERIC "1"
// Retrieval info: CONSTANT: tx_pll_vco_post_scale_divider NUMERIC "1"
// Retrieval info: CONSTANT: tx_use_external_termination STRING "false"
// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
// Retrieval info: USED_PORT: coreclkout 0 0 1 0 OUTPUT NODEFVAL "coreclkout[0..0]"
// Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
// Retrieval info: USED_PORT: pipe8b10binvpolarity 0 0 8 0 INPUT NODEFVAL "pipe8b10binvpolarity[7..0]"
// Retrieval info: USED_PORT: pipedatavalid 0 0 8 0 OUTPUT NODEFVAL "pipedatavalid[7..0]"
// Retrieval info: USED_PORT: pipeelecidle 0 0 8 0 OUTPUT NODEFVAL "pipeelecidle[7..0]"
// Retrieval info: USED_PORT: pipephydonestatus 0 0 8 0 OUTPUT NODEFVAL "pipephydonestatus[7..0]"
// Retrieval info: USED_PORT: pipestatus 0 0 24 0 OUTPUT NODEFVAL "pipestatus[23..0]"
// Retrieval info: USED_PORT: pll_inclk 0 0 0 0 INPUT NODEFVAL "pll_inclk"
// Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
// Retrieval info: USED_PORT: powerdn 0 0 16 0 INPUT NODEFVAL "powerdn[15..0]"
// Retrieval info: USED_PORT: rateswitch 0 0 1 0 INPUT NODEFVAL "rateswitch[0..0]"
// Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
// Retrieval info: USED_PORT: reconfig_fromgxb 0 0 34 0 OUTPUT NODEFVAL "reconfig_fromgxb[33..0]"
// Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 INPUT NODEFVAL "reconfig_togxb[3..0]"
// Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
// Retrieval info: USED_PORT: rx_cruclk 0 0 8 0 INPUT GND "rx_cruclk[7..0]"
// Retrieval info: USED_PORT: rx_ctrldetect 0 0 16 0 OUTPUT NODEFVAL "rx_ctrldetect[15..0]"
// Retrieval info: USED_PORT: rx_datain 0 0 8 0 INPUT NODEFVAL "rx_datain[7..0]"
// Retrieval info: USED_PORT: rx_dataout 0 0 128 0 OUTPUT NODEFVAL "rx_dataout[127..0]"
// Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
// Retrieval info: USED_PORT: rx_freqlocked 0 0 8 0 OUTPUT NODEFVAL "rx_freqlocked[7..0]"
// Retrieval info: USED_PORT: rx_patterndetect 0 0 16 0 OUTPUT NODEFVAL "rx_patterndetect[15..0]"
// Retrieval info: USED_PORT: rx_pll_locked 0 0 8 0 OUTPUT NODEFVAL "rx_pll_locked[7..0]"
// Retrieval info: USED_PORT: rx_syncstatus 0 0 16 0 OUTPUT NODEFVAL "rx_syncstatus[15..0]"
// Retrieval info: USED_PORT: tx_ctrlenable 0 0 16 0 INPUT NODEFVAL "tx_ctrlenable[15..0]"
// Retrieval info: USED_PORT: tx_datain 0 0 128 0 INPUT NODEFVAL "tx_datain[127..0]"
// Retrieval info: USED_PORT: tx_dataout 0 0 8 0 OUTPUT NODEFVAL "tx_dataout[7..0]"
// Retrieval info: USED_PORT: tx_detectrxloop 0 0 8 0 INPUT NODEFVAL "tx_detectrxloop[7..0]"
// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
// Retrieval info: USED_PORT: tx_forcedispcompliance 0 0 8 0 INPUT NODEFVAL "tx_forcedispcompliance[7..0]"
// Retrieval info: USED_PORT: tx_forceelecidle 0 0 8 0 INPUT NODEFVAL "tx_forceelecidle[7..0]"
// Retrieval info: USED_PORT: tx_pipedeemph 0 0 8 0 INPUT NODEFVAL "tx_pipedeemph[7..0]"
// Retrieval info: USED_PORT: tx_pipemargin 0 0 24 0 INPUT NODEFVAL "tx_pipemargin[23..0]"
// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
// Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
// Retrieval info: CONNECT: @pipe8b10binvpolarity 0 0 8 0 pipe8b10binvpolarity 0 0 8 0
// Retrieval info: CONNECT: @pll_inclk 0 0 0 0 pll_inclk 0 0 0 0
// Retrieval info: CONNECT: @powerdn 0 0 16 0 powerdn 0 0 16 0
// Retrieval info: CONNECT: @rateswitch 0 0 1 0 rateswitch 0 0 1 0
// Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
// Retrieval info: CONNECT: @reconfig_togxb 0 0 4 0 reconfig_togxb 0 0 4 0
// Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
// Retrieval info: CONNECT: @rx_cruclk 0 0 8 0 rx_cruclk 0 0 8 0
// Retrieval info: CONNECT: @rx_datain 0 0 8 0 rx_datain 0 0 8 0
// Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
// Retrieval info: CONNECT: @tx_ctrlenable 0 0 16 0 tx_ctrlenable 0 0 16 0
// Retrieval info: CONNECT: @tx_datain 0 0 128 0 tx_datain 0 0 128 0
// Retrieval info: CONNECT: @tx_detectrxloop 0 0 8 0 tx_detectrxloop 0 0 8 0
// Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
// Retrieval info: CONNECT: @tx_forcedispcompliance 0 0 8 0 tx_forcedispcompliance 0 0 8 0
// Retrieval info: CONNECT: @tx_forceelecidle 0 0 8 0 tx_forceelecidle 0 0 8 0
// Retrieval info: CONNECT: @tx_pipedeemph 0 0 8 0 tx_pipedeemph 0 0 8 0
// Retrieval info: CONNECT: @tx_pipemargin 0 0 24 0 tx_pipemargin 0 0 24 0
// Retrieval info: CONNECT: coreclkout 0 0 1 0 @coreclkout 0 0 1 0
// Retrieval info: CONNECT: pipedatavalid 0 0 8 0 @pipedatavalid 0 0 8 0
// Retrieval info: CONNECT: pipeelecidle 0 0 8 0 @pipeelecidle 0 0 8 0
// Retrieval info: CONNECT: pipephydonestatus 0 0 8 0 @pipephydonestatus 0 0 8 0
// Retrieval info: CONNECT: pipestatus 0 0 24 0 @pipestatus 0 0 24 0
// Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
// Retrieval info: CONNECT: reconfig_fromgxb 0 0 34 0 @reconfig_fromgxb 0 0 34 0
// Retrieval info: CONNECT: rx_ctrldetect 0 0 16 0 @rx_ctrldetect 0 0 16 0
// Retrieval info: CONNECT: rx_dataout 0 0 128 0 @rx_dataout 0 0 128 0
// Retrieval info: CONNECT: rx_freqlocked 0 0 8 0 @rx_freqlocked 0 0 8 0
// Retrieval info: CONNECT: rx_patterndetect 0 0 16 0 @rx_patterndetect 0 0 16 0
// Retrieval info: CONNECT: rx_pll_locked 0 0 8 0 @rx_pll_locked 0 0 8 0
// Retrieval info: CONNECT: rx_syncstatus 0 0 16 0 @rx_syncstatus 0 0 16 0
// Retrieval info: CONNECT: tx_dataout 0 0 8 0 @tx_dataout 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x8d_gen2_08p.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x8d_gen2_08p.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x8d_gen2_08p.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x8d_gen2_08p.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x8d_gen2_08p.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x8d_gen2_08p_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_4sgx_x8d_gen2_08p_bb.v TRUE
// Retrieval info: LIB_FILE: stratixiv_hssi
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFSBP_LP_V
`define SKY130_FD_SC_LP__SDFSBP_LP_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog wrapper for sdfsbp with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sdfsbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfsbp_lp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__sdfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfsbp_lp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__sdfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFSBP_LP_V
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge ([email protected])
// button_debounce.v
// Created: 4.5.2012
// Modified: 4.5.2012
//
// Testbench for button_debounce.v.
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module t_button_debounce();
parameter
CLK_FREQUENCY = 66000000,
DEBOUNCE_HZ = 2;
reg clk, reset_n, button;
wire debounce;
button_debounce
#(
.CLK_FREQUENCY(CLK_FREQUENCY),
.DEBOUNCE_HZ(DEBOUNCE_HZ)
)
button_debounce
(
.clk(clk),
.reset_n(reset_n),
.button(button),
.debounce(debounce)
);
initial begin
clk = 1'bx; reset_n = 1'bx; button = 1'bx;
#10 reset_n = 1;
#10 reset_n = 0; clk = 0;
#10 reset_n = 1;
#10 button = 0;
end
always
#5 clk = ~clk;
always begin
#100 button = ~button;
#0.1 button = ~button;
#0.1 button = ~button;
#0.1 button = ~button;
#0.1 button = ~button;
#0.1 button = ~button;
#0.1 button = ~button;
#0.1 button = ~button;
#0.1 button = ~button;
end
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module ddr3_s4_uniphy_p0_read_valid_selector(
reset_n,
pll_afi_clk,
latency_shifter,
latency_counter,
read_enable,
read_valid
);
parameter MAX_LATENCY_COUNT_WIDTH = "";
localparam LATENCY_NUM = 2**MAX_LATENCY_COUNT_WIDTH;
input reset_n;
input pll_afi_clk;
input [LATENCY_NUM-1:0] latency_shifter;
input [MAX_LATENCY_COUNT_WIDTH-1:0] latency_counter;
output read_enable;
output read_valid;
wire [LATENCY_NUM-1:0] selector;
reg [LATENCY_NUM-1:0] selector_reg;
reg read_enable;
reg reading_data;
reg read_valid;
wire [LATENCY_NUM-1:0] valid_select;
lpm_decode uvalid_select(
.data (latency_counter),
.eq (selector)
// synopsys translate_off
,
.aclr (),
.clken (),
.clock (),
.enable ()
// synopsys translate_on
);
defparam uvalid_select.lpm_decodes = LATENCY_NUM;
defparam uvalid_select.lpm_type = "LPM_DECODE";
defparam uvalid_select.lpm_width = MAX_LATENCY_COUNT_WIDTH;
always @(posedge pll_afi_clk or negedge reset_n)
begin
if (~reset_n)
selector_reg <= {LATENCY_NUM{1'b0}};
else
selector_reg <= selector;
end
assign valid_select = selector_reg & latency_shifter;
always @(posedge pll_afi_clk or negedge reset_n)
begin
if (~reset_n)
begin
read_enable <= 1'b0;
read_valid <= 1'b0;
end
else
begin
read_enable <= |valid_select;
read_valid <= |valid_select;
end
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.68d
// \ \ Application: netgen
// / / Filename: uart_tx_timesim.v
// /___/ /\ Timestamp: Mon Oct 20 14:19:35 2014
// \ \ / \
// \___\/\___\
//
// Command : -intstyle ise -s 5 -pcf uart_tx.pcf -sdf_anno true -sdf_path netgen/par -insert_glbl true -insert_pp_buffers true -w -dir netgen/par -ofmt verilog -sim uart_tx.ncd uart_tx_timesim.v
// Device : 3s100ecp132-5 (PRODUCTION 1.27 2013-06-08)
// Input file : uart_tx.ncd
// Output file : C:\Users\James\Desktop\iDriveSync\IDrive-Sync\DSD LAB\lab8\netgen\par\uart_tx_timesim.v
// # of Modules : 1
// Design Name : uart_tx
// Xilinx : C:\Xilinx\14.6\ISE_DS\ISE\
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module uart_tx (
clk, rden, wren, reset, txout, dout, addr, din
);
input clk;
input rden;
input wren;
input reset;
output txout;
output [7 : 0] dout;
input [2 : 0] addr;
input [7 : 0] din;
wire addr_2_IBUF_853;
wire din_2_IBUF_854;
wire wren_IBUF_855;
wire din_3_IBUF_856;
wire din_4_IBUF_857;
wire din_5_IBUF_858;
wire rden_IBUF_859;
wire din_6_IBUF_860;
wire din_7_IBUF_861;
wire reset_IBUF_872;
wire addr_0_IBUF_873;
wire din_0_IBUF_874;
wire addr_1_IBUF_875;
wire din_1_IBUF_876;
wire clk_BUFGP;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en_0 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en_0 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg[0] ;
wire \baud1/baud_cmp_eq0000_0 ;
wire N36;
wire pstate_FSM_FFd2_907;
wire empty;
wire N14;
wire pstate_FSM_FFd1_910;
wire \baud1/baud_911 ;
wire N27_0;
wire shift_out_not0001_0;
wire \baud1/baud_cmp_eq0000826/O ;
wire \baud1/baud_cmp_eq0000853_0 ;
wire \baud1/baud_cmp_eq0000893_0 ;
wire \baud1/baud_cmp_eq00008120_0 ;
wire control_1_not00017_0;
wire \control_1_not000121/O ;
wire \bitcounter_not0001_SW0/O ;
wire bitcounter_not0001_0;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rst_d2_928 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb5_0 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en_0 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb84_SW0/O ;
wire \fifo1/N8_0 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb40_0 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb67_0 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_937 ;
wire \pstate_FSM_FFd1-In3_SW0/O ;
wire N16_0;
wire \baud1/Madd_timer_addsub0000_cy[3] ;
wire N44_0;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or00003168_SW0/O ;
wire \fifo1/N6_0 ;
wire \baud1/Madd_timer_addsub0000_cy[5] ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg[2] ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_951 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or000079/O ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or000062_0 ;
wire \fifo1/N01_0 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or000014_0 ;
wire N46_0;
wire N47_0;
wire N34_0;
wire N42_0;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_979 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_980 ;
wire pstate_FSM_FFd2_1_981;
wire ld_shift;
wire bittime_0;
wire wr_baud_0;
wire N2;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_987 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en_0 ;
wire N3;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_1004 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_1005 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_1008 ;
wire wr_fifo;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_1011 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_1012 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_1013 ;
wire N25;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rst_d1_1015 ;
wire full;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rst_d3_1017 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_1018 ;
wire N30_0;
wire N29;
wire \addr<2>/INBUF ;
wire \din<2>/INBUF ;
wire \wren/INBUF ;
wire \din<3>/INBUF ;
wire \din<4>/INBUF ;
wire \din<5>/INBUF ;
wire \rden/INBUF ;
wire \din<6>/INBUF ;
wire \din<7>/INBUF ;
wire \clk/INBUF ;
wire \dout<0>/O ;
wire \dout<1>/O ;
wire \dout<2>/O ;
wire \dout<3>/O ;
wire \dout<4>/O ;
wire \dout<5>/O ;
wire \dout<6>/O ;
wire \dout<7>/O ;
wire \txout/O ;
wire \reset/INBUF ;
wire \addr<0>/INBUF ;
wire \din<0>/INBUF ;
wire \addr<1>/INBUF ;
wire \din<1>/INBUF ;
wire \clk_BUFGP/BUFG/S_INVNOT ;
wire \clk_BUFGP/BUFG/I0_INV ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPB3 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPB2 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPB1 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPB0 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB31 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB30 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB29 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB28 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB27 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB26 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB23 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB22 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB21 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB20 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB19 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB18 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB15 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB14 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB13 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB12 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB11 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB10 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB7 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB6 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB5 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB4 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB3 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB2 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPA3 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPA2 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPA1 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPA0 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA31 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA30 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA29 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA28 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA27 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA26 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA25 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA24 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA23 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA22 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA21 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA20 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA19 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA18 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA17 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA16 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA15 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA14 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA13 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA12 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA11 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA10 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA9 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA8 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA7 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA6 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA5 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA4 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA3 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA2 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA1 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA0 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIPB3 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIPB2 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIPB1 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIPB0 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB31 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB30 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB29 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB28 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB27 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB26 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB25 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB24 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB23 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB22 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB21 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB20 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB19 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB18 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB17 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB16 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB15 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB14 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB13 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB12 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB11 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB10 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB9 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB8 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB7 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB6 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB5 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB4 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB3 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB2 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB1 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB0 ;
wire \dout_1_OBUF/F5MUX_1382 ;
wire \dout<1>1_1380 ;
wire \dout_1_OBUF/BXINV_1375 ;
wire \dout<1>2_1373 ;
wire \dout_0_OBUF/F5MUX_1407 ;
wire \dout<0>1_1405 ;
wire \dout_0_OBUF/BXINV_1400 ;
wire \dout<0>2_1398 ;
wire \baud1/timer<1>/DXMUX_1437 ;
wire N36_pack_2;
wire \baud1/timer<1>/CLKINV_1419 ;
wire shift_out_not0001;
wire N14_pack_1;
wire \baud1/baud_cmp_eq0000 ;
wire \baud1/baud_cmp_eq0000826/O_pack_1 ;
wire control_1_not0001;
wire \control_1_not000121/O_pack_1 ;
wire bitcounter_not0001_1537;
wire \bitcounter_not0001_SW0/O_pack_1 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i/DXMUX_1569 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i/FXMUX_1568 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb84_SW0/O_pack_1 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i/CLKINV_1553 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i/FFX/SET ;
wire N16;
wire \pstate_FSM_FFd1-In3_SW0/O_pack_1 ;
wire N44;
wire \baud1/Madd_timer_addsub0000_cy<3>_pack_1 ;
wire \fifo1/N8 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or00003168_SW0/O_pack_1 ;
wire \baud1/timer<6>/DXMUX_1675 ;
wire \baud1/Madd_timer_addsub0000_cy<5>_pack_2 ;
wire \baud1/timer<6>/CLKINV_1658 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/DXMUX_1710 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or0000 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or000079/O_pack_2 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/CLKINV_1694 ;
wire \shift_out<5>/DXMUX_1753 ;
wire \shift_out<5>/DYMUX_1739 ;
wire \shift_out<5>/SRINV_1731 ;
wire \shift_out<5>/CLKINV_1730 ;
wire \shift_out<5>/CEINV_1729 ;
wire \shift_out<7>/DXMUX_1797 ;
wire \shift_out<7>/DYMUX_1783 ;
wire \shift_out<7>/SRINV_1775 ;
wire \shift_out<7>/CLKINV_1774 ;
wire \shift_out<7>/CEINV_1773 ;
wire N46;
wire \shift_out<8>/DYMUX_1826 ;
wire \shift_out<8>/CLKINV_1816 ;
wire \shift_out<8>/CEINV_1815 ;
wire \shift_out<8>/FFY/SET ;
wire N47;
wire \baud1/timer<0>/DYMUX_1862 ;
wire \baud1/timer<0>/CLKINV_1853 ;
wire \baud1/timer<3>/FFX/RST ;
wire \baud1/timer<3>/DXMUX_1911 ;
wire \baud1/timer<3>/DYMUX_1897 ;
wire \baud1/timer<3>/SRINV_1889 ;
wire \baud1/timer<3>/CLKINV_1888 ;
wire \baud1/timer<5>/DXMUX_1953 ;
wire \baud1/timer<5>/DYMUX_1939 ;
wire \baud1/timer<5>/SRINV_1931 ;
wire \baud1/timer<5>/CLKINV_1930 ;
wire \baud1/timer<7>/DYMUX_1976 ;
wire \baud1/timer<7>/CLKINV_1967 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/DXMUX_2021 ;
wire \fifo1/Result<3>1 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/DYMUX_2006 ;
wire \fifo1/Result<2>1 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/SRINV_1997 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/CLKINV_1996 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/CEINV_1995 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/FFY/RST ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/DXMUX_2067 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/DYMUX_2052 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/SRINV_2043 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/CLKINV_2042 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/CEINV_2041 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/DXMUX_2110 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2-In ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/DYMUX_2096 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/SRINV_2088 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/CLKINV_2087 ;
wire bittime;
wire \pstate_FSM_FFd2_1/DYMUX_2137 ;
wire \pstate_FSM_FFd2_1/GYMUX_2136 ;
wire \pstate_FSM_FFd2-In ;
wire \pstate_FSM_FFd2_1/CLKINV_2128 ;
wire wr_baud;
wire \control<1>/DYMUX_2176 ;
wire control_1_mux0000;
wire \control<1>/CLKINV_2167 ;
wire \control<1>/CEINV_2166 ;
wire \bitcounter<2>/DXMUX_2229 ;
wire Mcount_bitcounter2;
wire \bitcounter<2>/DYMUX_2213 ;
wire Mcount_bitcounter1;
wire \bitcounter<2>/SRINV_2204 ;
wire \bitcounter<2>/CLKINV_2203 ;
wire \bitcounter<2>/CEINV_2202 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/DYMUX_2259 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/GYMUX_2258 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_or0000 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/CLKINV_2250 ;
wire \bittimer<3>/DXMUX_2310 ;
wire \bittimer<3>/DYMUX_2295 ;
wire \bittimer<3>/SRINV_2286 ;
wire \bittimer<3>/CLKINV_2285 ;
wire \bittimer<3>/CEINV_2284 ;
wire \shift_out<1>/DXMUX_2355 ;
wire \shift_out<1>/DYMUX_2341 ;
wire \shift_out<1>/SRINV_2332 ;
wire \shift_out<1>/CLKINV_2331 ;
wire \shift_out<1>/CEINV_2330 ;
wire \shift_out<3>/DXMUX_2399 ;
wire \shift_out<3>/DYMUX_2385 ;
wire \shift_out<3>/SRINV_2377 ;
wire \shift_out<3>/CLKINV_2376 ;
wire \shift_out<3>/CEINV_2375 ;
wire dout_2_OBUF_2427;
wire dout_3_OBUF_2419;
wire dout_5_OBUF_2451;
wire dout_4_OBUF_2443;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg/DYMUX_2463 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg/BYINV_2462 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg/CLKINV_2460 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg/CEINV_2459 ;
wire \baud1/period<1>/DXMUX_2490 ;
wire \baud1/period<1>/DYMUX_2481 ;
wire \baud1/period<1>/SRINV_2479 ;
wire \baud1/period<1>/CLKINV_2478 ;
wire \baud1/period<1>/CEINV_2477 ;
wire \baud1/period<3>/DXMUX_2517 ;
wire \baud1/period<3>/DYMUX_2508 ;
wire \baud1/period<3>/SRINV_2506 ;
wire \baud1/period<3>/CLKINV_2505 ;
wire \baud1/period<3>/CEINV_2504 ;
wire \baud1/baud_cmp_eq00008120_2545 ;
wire dout_6_OBUF_2538;
wire \baud1/period<5>/DXMUX_2567 ;
wire \baud1/period<5>/DYMUX_2559 ;
wire \baud1/period<5>/SRINV_2557 ;
wire \baud1/period<5>/CLKINV_2556 ;
wire \baud1/period<5>/CEINV_2555 ;
wire \bitcounter<0>/DXMUX_2605 ;
wire Mcount_bitcounter;
wire N2_pack_2;
wire \bitcounter<0>/CLKINV_2588 ;
wire \bitcounter<0>/CEINV_2587 ;
wire \baud1/period<7>/DXMUX_2633 ;
wire \baud1/period<7>/DYMUX_2624 ;
wire \baud1/period<7>/SRINV_2622 ;
wire \baud1/period<7>/CLKINV_2621 ;
wire \baud1/period<7>/CEINV_2620 ;
wire \baud1/baud/DYMUX_2650 ;
wire \baud1/baud/CLKINV_2647 ;
wire \baud1/baud/CEINV_2646 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2/DXMUX_2670 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2/DYMUX_2665 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2/CLKINV_2663 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ;
wire ld_shift_pack_1;
wire dout_7_OBUF_2719;
wire N3_pack_1;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<0>/DXMUX_2775 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb40_2772 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<0>/DYMUX_2759 ;
wire \fifo1/Result<1>1 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<0>/SRINV_2749 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<0>/CLKINV_2748 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<0>/CEINV_2747 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/DXMUX_2823 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or000014_2820 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/DYMUX_2805 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/SRINV_2795 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/CLKINV_2794 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/CEINV_2793 ;
wire \fifo1/N01 ;
wire wr_fifo_pack_1;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb67_2875 ;
wire \fifo1/N6 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg/DYMUX_2887 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg/BYINV_2886 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg/CLKINV_2884 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg/CEINV_2883 ;
wire \to_shift<1>/DXMUX_2912 ;
wire \to_shift<1>/DYMUX_2905 ;
wire \to_shift<1>/SRINV_2903 ;
wire \to_shift<1>/CLKINV_2902 ;
wire \to_shift<1>/CEINV_2901 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ;
wire \to_shift<3>/DXMUX_2948 ;
wire \to_shift<3>/DYMUX_2941 ;
wire \to_shift<3>/SRINV_2939 ;
wire \to_shift<3>/CLKINV_2938 ;
wire \to_shift<3>/CEINV_2937 ;
wire \to_shift<5>/DXMUX_2972 ;
wire \to_shift<5>/DYMUX_2965 ;
wire \to_shift<5>/SRINV_2963 ;
wire \to_shift<5>/CLKINV_2962 ;
wire \to_shift<5>/CEINV_2961 ;
wire \to_shift<7>/DXMUX_2996 ;
wire \to_shift<7>/DYMUX_2989 ;
wire \to_shift<7>/SRINV_2987 ;
wire \to_shift<7>/CLKINV_2986 ;
wire \to_shift<7>/CEINV_2985 ;
wire N34;
wire \baud1/baud_cmp_eq0000853_3016 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb5_3038 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<1>/DXMUX_3070 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<1>/DYMUX_3061 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<1>/SRINV_3059 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<1>/CLKINV_3058 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<1>/CEINV_3057 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/FFY/RST ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/FFX/RST ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/DXMUX_3098 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/DYMUX_3089 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/SRINV_3087 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/CLKINV_3086 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/CEINV_3085 ;
wire \pstate_FSM_FFd1/FFY/RST ;
wire \pstate_FSM_FFd1/FFX/RST ;
wire \pstate_FSM_FFd1/DXMUX_3144 ;
wire \pstate_FSM_FFd1-In_3141 ;
wire \pstate_FSM_FFd1/DYMUX_3130 ;
wire N25_pack_2;
wire \pstate_FSM_FFd1/SRINV_3121 ;
wire \pstate_FSM_FFd1/CLKINV_3120 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/FFY/RST ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/FFX/RST ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/DXMUX_3171 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/DYMUX_3162 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/SRINV_3160 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/CLKINV_3159 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/CEINV_3158 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/DXMUX_3199 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/DYMUX_3190 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/SRINV_3188 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/CLKINV_3187 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/CEINV_3186 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rst_d2/DXMUX_3223 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rst_d2/DYMUX_3216 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rst_d2/BYINV_3215 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rst_d2/SRINV_3214 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rst_d2/CLKINV_3213 ;
wire \control<0>/DYMUX_3236 ;
wire \control<0>/CLKINV_3233 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg<2>/DXMUX_3258 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg<2>/BXINV_3257 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg<2>/DYMUX_3251 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg<2>/BYINV_3250 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg<2>/SRINV_3249 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg<2>/CLKINV_3248 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rst_d3/DYMUX_3271 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rst_d3/CLKINV_3268 ;
wire \baud1/baud_cmp_eq0000893_3286 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ;
wire N42;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN/DYMUX_3320 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN/CLKINV_3317 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2/DXMUX_3339 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2/DYMUX_3334 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2/CLKINV_3332 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or000062_3352 ;
wire \bittimer<0>/DXMUX_3396 ;
wire N27;
wire \bittimer<0>/DYMUX_3379 ;
wire \bittimer<0>/SRINV_3369 ;
wire \bittimer<0>/CLKINV_3368 ;
wire \bittimer<0>/CEINV_3367 ;
wire \full/DYMUX_3411 ;
wire \full/CLKINV_3408 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_reg<1>/DYMUX_3424 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_reg<1>/BYINV_3423 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_reg<1>/CLKINV_3421 ;
wire \empty/DYMUX_3437 ;
wire \empty/CLKINV_3434 ;
wire \bitcounter<3>/DXMUX_3473 ;
wire Mcount_bitcounter3;
wire N29_pack_2;
wire \bitcounter<3>/CLKINV_3457 ;
wire \bitcounter<3>/CEINV_3456 ;
wire N30;
wire control_1_not00017_3502;
wire \baud1/timer<7>/FFY/RSTAND_1981 ;
wire \baud1/timer<1>/FFX/RSTAND_1442 ;
wire \baud1/timer<6>/FFX/RSTAND_1680 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/FFX/SET ;
wire \baud1/timer<0>/FFY/RSTAND_1867 ;
wire \pstate_FSM_FFd2_1/FFY/RSTAND_2142 ;
wire \control<1>/FFY/RSTAND_2182 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/FFY/SET ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg/FFY/SET ;
wire \bitcounter<0>/FFX/RSTAND_2611 ;
wire \baud1/baud/FFY/RSTAND_2656 ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg/FFY/SET ;
wire \control<0>/FFY/SET ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rst_d3/FFY/SET ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN/FFY/RSTAND_3325 ;
wire \full/FFY/SET ;
wire \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_reg<1>/FFY/SET ;
wire \empty/FFY/SET ;
wire \bitcounter<3>/FFX/RSTAND_3479 ;
wire \NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRA<3> ;
wire \NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRA<2> ;
wire \NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRA<1> ;
wire \NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRA<0> ;
wire \NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<3> ;
wire \NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<2> ;
wire \NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<1> ;
wire \NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<0> ;
wire \NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<0> ;
wire \NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<1> ;
wire \NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<8> ;
wire \NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<9> ;
wire \NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<16> ;
wire \NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<17> ;
wire \NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<24> ;
wire \NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<25> ;
wire GND;
wire VCC;
wire [8 : 0] shift_out;
wire [3 : 0] \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 ;
wire [3 : 0] \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 ;
wire [7 : 0] \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem ;
wire [1 : 0] control;
wire [7 : 0] \baud1/period ;
wire [7 : 0] \baud1/timer ;
wire [3 : 0] bittimer;
wire [3 : 0] bitcounter;
wire [3 : 0] \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count ;
wire [7 : 0] to_shift;
wire [1 : 1] \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_reg ;
wire [3 : 0] \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count ;
wire [7 : 0] \baud1/timer_mux0000 ;
wire [8 : 0] shift_out_mux0000;
wire [3 : 1] \fifo1/Result ;
wire [3 : 1] Result;
initial $sdf_annotate("netgen/par/uart_tx_timesim.sdf");
X_IPAD #(
.LOC ( "PAD54" ))
\addr<2>/PAD (
.PAD(addr[2])
);
X_BUF #(
.LOC ( "PAD54" ))
addr_2_IBUF (
.I(addr[2]),
.O(\addr<2>/INBUF )
);
X_IPAD #(
.LOC ( "PAD34" ))
\din<2>/PAD (
.PAD(din[2])
);
X_BUF #(
.LOC ( "PAD34" ))
din_2_IBUF (
.I(din[2]),
.O(\din<2>/INBUF )
);
X_IPAD #(
.LOC ( "PAD43" ))
\wren/PAD (
.PAD(wren)
);
X_BUF #(
.LOC ( "PAD43" ))
wren_IBUF (
.I(wren),
.O(\wren/INBUF )
);
X_IPAD #(
.LOC ( "PAD39" ))
\din<3>/PAD (
.PAD(din[3])
);
X_BUF #(
.LOC ( "PAD39" ))
din_3_IBUF (
.I(din[3]),
.O(\din<3>/INBUF )
);
X_BUF #(
.LOC ( "PAD39" ))
\din<3>/IFF/IMUX (
.I(\din<3>/INBUF ),
.O(din_3_IBUF_856)
);
X_IPAD #(
.LOC ( "PAD31" ))
\din<4>/PAD (
.PAD(din[4])
);
X_BUF #(
.LOC ( "PAD31" ))
din_4_IBUF (
.I(din[4]),
.O(\din<4>/INBUF )
);
X_IPAD #(
.LOC ( "PAD35" ))
\din<5>/PAD (
.PAD(din[5])
);
X_BUF #(
.LOC ( "PAD35" ))
din_5_IBUF (
.I(din[5]),
.O(\din<5>/INBUF )
);
X_IPAD #(
.LOC ( "PAD28" ))
\rden/PAD (
.PAD(rden)
);
X_BUF #(
.LOC ( "PAD28" ))
rden_IBUF (
.I(rden),
.O(\rden/INBUF )
);
X_IPAD #(
.LOC ( "PAD30" ))
\din<6>/PAD (
.PAD(din[6])
);
X_BUF #(
.LOC ( "PAD30" ))
din_6_IBUF (
.I(din[6]),
.O(\din<6>/INBUF )
);
X_IPAD #(
.LOC ( "PAD33" ))
\din<7>/PAD (
.PAD(din[7])
);
X_BUF #(
.LOC ( "PAD33" ))
din_7_IBUF (
.I(din[7]),
.O(\din<7>/INBUF )
);
X_IPAD #(
.LOC ( "IPAD12" ))
\clk/PAD (
.PAD(clk)
);
X_BUF #(
.LOC ( "IPAD12" ))
\clk_BUFGP/IBUFG (
.I(clk),
.O(\clk/INBUF )
);
X_OPAD #(
.LOC ( "PAD45" ))
\dout<0>/PAD (
.PAD(dout[0])
);
X_OBUF #(
.LOC ( "PAD45" ))
dout_0_OBUF (
.I(\dout<0>/O ),
.O(dout[0])
);
X_OPAD #(
.LOC ( "PAD51" ))
\dout<1>/PAD (
.PAD(dout[1])
);
X_OBUF #(
.LOC ( "PAD51" ))
dout_1_OBUF (
.I(\dout<1>/O ),
.O(dout[1])
);
X_OPAD #(
.LOC ( "PAD52" ))
\dout<2>/PAD (
.PAD(dout[2])
);
X_OBUF #(
.LOC ( "PAD52" ))
dout_2_OBUF (
.I(\dout<2>/O ),
.O(dout[2])
);
X_OPAD #(
.LOC ( "PAD49" ))
\dout<3>/PAD (
.PAD(dout[3])
);
X_OBUF #(
.LOC ( "PAD49" ))
dout_3_OBUF (
.I(\dout<3>/O ),
.O(dout[3])
);
X_OPAD #(
.LOC ( "PAD44" ))
\dout<4>/PAD (
.PAD(dout[4])
);
X_OBUF #(
.LOC ( "PAD44" ))
dout_4_OBUF (
.I(\dout<4>/O ),
.O(dout[4])
);
X_OPAD #(
.LOC ( "PAD48" ))
\dout<5>/PAD (
.PAD(dout[5])
);
X_OBUF #(
.LOC ( "PAD48" ))
dout_5_OBUF (
.I(\dout<5>/O ),
.O(dout[5])
);
X_OPAD #(
.LOC ( "PAD38" ))
\dout<6>/PAD (
.PAD(dout[6])
);
X_OBUF #(
.LOC ( "PAD38" ))
dout_6_OBUF (
.I(\dout<6>/O ),
.O(dout[6])
);
X_OPAD #(
.LOC ( "PAD42" ))
\dout<7>/PAD (
.PAD(dout[7])
);
X_OBUF #(
.LOC ( "PAD42" ))
dout_7_OBUF (
.I(\dout<7>/O ),
.O(dout[7])
);
X_OPAD #(
.LOC ( "PAD37" ))
\txout/PAD (
.PAD(txout)
);
X_OBUF #(
.LOC ( "PAD37" ))
txout_OBUF (
.I(\txout/O ),
.O(txout)
);
X_IPAD #(
.LOC ( "PAD29" ))
\reset/PAD (
.PAD(reset)
);
X_BUF #(
.LOC ( "PAD29" ))
reset_IBUF (
.I(reset),
.O(\reset/INBUF )
);
X_IPAD #(
.LOC ( "PAD53" ))
\addr<0>/PAD (
.PAD(addr[0])
);
X_BUF #(
.LOC ( "PAD53" ))
addr_0_IBUF (
.I(addr[0]),
.O(\addr<0>/INBUF )
);
X_IPAD #(
.LOC ( "PAD40" ))
\din<0>/PAD (
.PAD(din[0])
);
X_BUF #(
.LOC ( "PAD40" ))
din_0_IBUF (
.I(din[0]),
.O(\din<0>/INBUF )
);
X_IPAD #(
.LOC ( "PAD47" ))
\addr<1>/PAD (
.PAD(addr[1])
);
X_BUF #(
.LOC ( "PAD47" ))
addr_1_IBUF (
.I(addr[1]),
.O(\addr<1>/INBUF )
);
X_IPAD #(
.LOC ( "IPAD36" ))
\din<1>/PAD (
.PAD(din[1])
);
X_BUF #(
.LOC ( "IPAD36" ))
din_1_IBUF (
.I(din[1]),
.O(\din<1>/INBUF )
);
X_BUFGMUX #(
.LOC ( "BUFGMUX_X2Y10" ))
\clk_BUFGP/BUFG (
.I0(\clk_BUFGP/BUFG/I0_INV ),
.I1(GND),
.S(\clk_BUFGP/BUFG/S_INVNOT ),
.O(clk_BUFGP)
);
X_INV #(
.LOC ( "BUFGMUX_X2Y10" ))
\clk_BUFGP/BUFG/SINV (
.I(1'b1),
.O(\clk_BUFGP/BUFG/S_INVNOT )
);
X_BUF #(
.LOC ( "BUFGMUX_X2Y10" ))
\clk_BUFGP/BUFG/I0_USED (
.I(\clk/INBUF ),
.O(\clk_BUFGP/BUFG/I0_INV )
);
X_RAMB16_S36_S36 #(
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.SRVAL_A ( 36'h000000000 ),
.SRVAL_B ( 36'h000000000 ),
.SIM_COLLISION_CHECK ( "ALL" ),
.WRITE_MODE_A ( "NO_CHANGE" ),
.WRITE_MODE_B ( "NO_CHANGE" ),
.INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.LOC ( "RAMB16_X0Y3" ),
.SETUP_ALL ( 227 ),
.SETUP_READ_FIRST ( 227 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram (
.CLKA(clk_BUFGP),
.CLKB(clk_BUFGP),
.ENA(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en_0 ),
.ENB(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en_0 ),
.SSRA(1'b0),
.SSRB(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg[0] ),
.WEA(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en_0 ),
.WEB(1'b0),
.ADDRA({1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRA<3>
,
\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRA<2>
,
\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRA<1>
,
\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRA<0>
}),
.ADDRB({1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<3>
,
\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<2>
,
\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<1>
,
\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<0>
}),
.DIA({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<25>
,
\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<24>
, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<17>
,
\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<16>
, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<9>
,
\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<8>
, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<1>
,
\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<0>
}),
.DIPA({1'b0, 1'b0, 1'b0, 1'b0}),
.DIB({
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB31
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB30
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB29
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB28
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB27
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB26
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB25
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB24
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB23
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB22
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB21
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB20
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB19
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB18
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB17
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB16
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB15
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB14
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB13
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB12
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB11
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB10
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB9
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB8
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB7
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB6
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB5
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB4
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB3
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB2
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB1
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB0
}),
.DIPB({
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIPB3
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIPB2
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIPB1
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIPB0
}),
.DOA({
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA31
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA30
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA29
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA28
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA27
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA26
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA25
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA24
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA23
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA22
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA21
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA20
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA19
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA18
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA17
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA16
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA15
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA14
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA13
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA12
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA11
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA10
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA9
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA8
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA7
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA6
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA5
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA4
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA3
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA2
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA1
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA0
}),
.DOPA({
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPA3
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPA2
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPA1
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPA0
}),
.DOB({
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB31
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB30
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB29
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB28
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB27
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB26
, \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [7],
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [6],
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB23
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB22
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB21
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB20
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB19
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB18
, \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [5],
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [4],
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB15
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB14
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB13
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB12
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB11
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB10
, \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [3],
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [2],
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB7
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB6
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB5
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB4
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB3
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB2
, \fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [1],
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [0]}),
.DOPB({
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPB3
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPB2
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPB1
,
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPB0
})
);
X_MUX2 #(
.LOC ( "SLICE_X31Y20" ))
\dout_1_OBUF/F5MUX (
.IA(\dout<1>2_1373 ),
.IB(\dout<1>1_1380 ),
.SEL(\dout_1_OBUF/BXINV_1375 ),
.O(\dout_1_OBUF/F5MUX_1382 )
);
X_BUF #(
.LOC ( "SLICE_X31Y20" ))
\dout_1_OBUF/BXINV (
.I(addr_1_IBUF_875),
.O(\dout_1_OBUF/BXINV_1375 )
);
X_LUT4 #(
.INIT ( 16'h0080 ),
.LOC ( "SLICE_X29Y21" ))
\dout<0>1 (
.ADR0(addr_0_IBUF_873),
.ADR1(control[0]),
.ADR2(rden_IBUF_859),
.ADR3(addr_2_IBUF_853),
.O(\dout<0>1_1405 )
);
X_MUX2 #(
.LOC ( "SLICE_X29Y21" ))
\dout_0_OBUF/F5MUX (
.IA(\dout<0>2_1398 ),
.IB(\dout<0>1_1405 ),
.SEL(\dout_0_OBUF/BXINV_1400 ),
.O(\dout_0_OBUF/F5MUX_1407 )
);
X_BUF #(
.LOC ( "SLICE_X29Y21" ))
\dout_0_OBUF/BXINV (
.I(addr_1_IBUF_875),
.O(\dout_0_OBUF/BXINV_1400 )
);
X_LUT4 #(
.INIT ( 16'h1000 ),
.LOC ( "SLICE_X29Y21" ))
\dout<0>2 (
.ADR0(addr_0_IBUF_873),
.ADR1(addr_2_IBUF_853),
.ADR2(rden_IBUF_859),
.ADR3(\baud1/period [0]),
.O(\dout<0>2_1398 )
);
X_BUF #(
.LOC ( "SLICE_X27Y27" ))
\baud1/timer<1>/DXMUX (
.I(\baud1/timer_mux0000 [6]),
.O(\baud1/timer<1>/DXMUX_1437 )
);
X_BUF #(
.LOC ( "SLICE_X27Y27" ))
\baud1/timer<1>/YUSED (
.I(N36_pack_2),
.O(N36)
);
X_BUF #(
.LOC ( "SLICE_X27Y27" ))
\baud1/timer<1>/CLKINV (
.I(clk_BUFGP),
.O(\baud1/timer<1>/CLKINV_1419 )
);
X_BUF #(
.LOC ( "SLICE_X18Y26" ))
\shift_out_not0001/XUSED (
.I(shift_out_not0001),
.O(shift_out_not0001_0)
);
X_BUF #(
.LOC ( "SLICE_X18Y26" ))
\shift_out_not0001/YUSED (
.I(N14_pack_1),
.O(N14)
);
X_LUT4 #(
.INIT ( 16'h8000 ),
.LOC ( "SLICE_X27Y25" ))
\baud1/baud_cmp_eq00008136 (
.ADR0(\baud1/baud_cmp_eq0000826/O ),
.ADR1(\baud1/baud_cmp_eq0000893_0 ),
.ADR2(\baud1/baud_cmp_eq00008120_0 ),
.ADR3(\baud1/baud_cmp_eq0000853_0 ),
.O(\baud1/baud_cmp_eq0000 )
);
X_BUF #(
.LOC ( "SLICE_X27Y25" ))
\baud1/baud_cmp_eq0000/XUSED (
.I(\baud1/baud_cmp_eq0000 ),
.O(\baud1/baud_cmp_eq0000_0 )
);
X_BUF #(
.LOC ( "SLICE_X27Y25" ))
\baud1/baud_cmp_eq0000/YUSED (
.I(\baud1/baud_cmp_eq0000826/O_pack_1 ),
.O(\baud1/baud_cmp_eq0000826/O )
);
X_LUT4 #(
.INIT ( 16'h9009 ),
.LOC ( "SLICE_X27Y25" ))
\baud1/baud_cmp_eq0000826 (
.ADR0(\baud1/timer [1]),
.ADR1(\baud1/period [1]),
.ADR2(\baud1/period [0]),
.ADR3(\baud1/timer [0]),
.O(\baud1/baud_cmp_eq0000826/O_pack_1 )
);
X_BUF #(
.LOC ( "SLICE_X24Y22" ))
\control_1_not0001/YUSED (
.I(\control_1_not000121/O_pack_1 ),
.O(\control_1_not000121/O )
);
X_BUF #(
.LOC ( "SLICE_X18Y24" ))
\bitcounter_not0001/XUSED (
.I(bitcounter_not0001_1537),
.O(bitcounter_not0001_0)
);
X_BUF #(
.LOC ( "SLICE_X18Y24" ))
\bitcounter_not0001/YUSED (
.I(\bitcounter_not0001_SW0/O_pack_1 ),
.O(\bitcounter_not0001_SW0/O )
);
X_BUF #(
.LOC ( "SLICE_X15Y23" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i/DXMUX (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i/FXMUX_1568 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i/DXMUX_1569 )
);
X_BUF #(
.LOC ( "SLICE_X15Y23" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i/FXMUX (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i/FXMUX_1568 )
);
X_BUF #(
.LOC ( "SLICE_X15Y23" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i/YUSED (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb84_SW0/O_pack_1 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb84_SW0/O )
);
X_BUF #(
.LOC ( "SLICE_X15Y23" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i/CLKINV (
.I(clk_BUFGP),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i/CLKINV_1553 )
);
X_FF #(
.LOC ( "SLICE_X15Y23" ),
.INIT ( 1'b1 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i/DXMUX_1569 ),
.CE(VCC),
.CLK(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i/CLKINV_1553 ),
.SET(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i/FFX/SET ),
.RST(GND),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_937 )
);
X_BUF #(
.LOC ( "SLICE_X15Y23" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i/FFX/SETOR (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rst_d2_928 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i/FFX/SET )
);
X_BUF #(
.LOC ( "SLICE_X16Y24" ))
\N16/XUSED (
.I(N16),
.O(N16_0)
);
X_BUF #(
.LOC ( "SLICE_X16Y24" ))
\N16/YUSED (
.I(\pstate_FSM_FFd1-In3_SW0/O_pack_1 ),
.O(\pstate_FSM_FFd1-In3_SW0/O )
);
X_BUF #(
.LOC ( "SLICE_X26Y25" ))
\N44/XUSED (
.I(N44),
.O(N44_0)
);
X_BUF #(
.LOC ( "SLICE_X26Y25" ))
\N44/YUSED (
.I(\baud1/Madd_timer_addsub0000_cy<3>_pack_1 ),
.O(\baud1/Madd_timer_addsub0000_cy[3] )
);
X_BUF #(
.LOC ( "SLICE_X12Y22" ))
\fifo1/N8/XUSED (
.I(\fifo1/N8 ),
.O(\fifo1/N8_0 )
);
X_BUF #(
.LOC ( "SLICE_X12Y22" ))
\fifo1/N8/YUSED (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or00003168_SW0/O_pack_1 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or00003168_SW0/O )
);
X_LUT4 #(
.INIT ( 16'hA000 ),
.LOC ( "SLICE_X26Y26" ))
\baud1/Madd_timer_addsub0000_cy<5>11 (
.ADR0(\baud1/Madd_timer_addsub0000_cy[3] ),
.ADR1(VCC),
.ADR2(\baud1/timer [5]),
.ADR3(\baud1/timer [4]),
.O(\baud1/Madd_timer_addsub0000_cy<5>_pack_2 )
);
X_BUF #(
.LOC ( "SLICE_X26Y26" ))
\baud1/timer<6>/DXMUX (
.I(\baud1/timer_mux0000 [1]),
.O(\baud1/timer<6>/DXMUX_1675 )
);
X_BUF #(
.LOC ( "SLICE_X26Y26" ))
\baud1/timer<6>/YUSED (
.I(\baud1/Madd_timer_addsub0000_cy<5>_pack_2 ),
.O(\baud1/Madd_timer_addsub0000_cy[5] )
);
X_BUF #(
.LOC ( "SLICE_X26Y26" ))
\baud1/timer<6>/CLKINV (
.I(clk_BUFGP),
.O(\baud1/timer<6>/CLKINV_1658 )
);
X_BUF #(
.LOC ( "SLICE_X14Y23" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/DXMUX (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or0000 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/DXMUX_1710 )
);
X_BUF #(
.LOC ( "SLICE_X14Y23" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/YUSED (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or000079/O_pack_2 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or000079/O )
);
X_BUF #(
.LOC ( "SLICE_X14Y23" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/CLKINV (
.I(clk_BUFGP),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/CLKINV_1694 )
);
X_FF #(
.LOC ( "SLICE_X15Y25" ),
.INIT ( 1'b1 ))
shift_out_5 (
.I(\shift_out<5>/DXMUX_1753 ),
.CE(\shift_out<5>/CEINV_1729 ),
.CLK(\shift_out<5>/CLKINV_1730 ),
.SET(\shift_out<5>/SRINV_1731 ),
.RST(GND),
.O(shift_out[5])
);
X_BUF #(
.LOC ( "SLICE_X15Y25" ))
\shift_out<5>/DXMUX (
.I(shift_out_mux0000[5]),
.O(\shift_out<5>/DXMUX_1753 )
);
X_BUF #(
.LOC ( "SLICE_X15Y25" ))
\shift_out<5>/DYMUX (
.I(shift_out_mux0000[4]),
.O(\shift_out<5>/DYMUX_1739 )
);
X_BUF #(
.LOC ( "SLICE_X15Y25" ))
\shift_out<5>/SRINV (
.I(reset_IBUF_872),
.O(\shift_out<5>/SRINV_1731 )
);
X_BUF #(
.LOC ( "SLICE_X15Y25" ))
\shift_out<5>/CLKINV (
.I(clk_BUFGP),
.O(\shift_out<5>/CLKINV_1730 )
);
X_BUF #(
.LOC ( "SLICE_X15Y25" ))
\shift_out<5>/CEINV (
.I(shift_out_not0001_0),
.O(\shift_out<5>/CEINV_1729 )
);
X_LUT4 #(
.INIT ( 16'hFE02 ),
.LOC ( "SLICE_X15Y25" ))
\shift_out_mux0000<5>1 (
.ADR0(to_shift[4]),
.ADR1(empty),
.ADR2(pstate_FSM_FFd2_907),
.ADR3(shift_out[6]),
.O(shift_out_mux0000[5])
);
X_BUF #(
.LOC ( "SLICE_X16Y26" ))
\shift_out<7>/DXMUX (
.I(shift_out_mux0000[7]),
.O(\shift_out<7>/DXMUX_1797 )
);
X_BUF #(
.LOC ( "SLICE_X16Y26" ))
\shift_out<7>/DYMUX (
.I(shift_out_mux0000[6]),
.O(\shift_out<7>/DYMUX_1783 )
);
X_BUF #(
.LOC ( "SLICE_X16Y26" ))
\shift_out<7>/SRINV (
.I(reset_IBUF_872),
.O(\shift_out<7>/SRINV_1775 )
);
X_BUF #(
.LOC ( "SLICE_X16Y26" ))
\shift_out<7>/CLKINV (
.I(clk_BUFGP),
.O(\shift_out<7>/CLKINV_1774 )
);
X_BUF #(
.LOC ( "SLICE_X16Y26" ))
\shift_out<7>/CEINV (
.I(shift_out_not0001_0),
.O(\shift_out<7>/CEINV_1773 )
);
X_LUT4 #(
.INIT ( 16'h30FF ),
.LOC ( "SLICE_X19Y26" ))
\baud1/timer_mux0000<0>11_SW6 (
.ADR0(VCC),
.ADR1(pstate_FSM_FFd2_907),
.ADR2(empty),
.ADR3(\baud1/timer [7]),
.O(N46)
);
X_BUF #(
.LOC ( "SLICE_X19Y26" ))
\shift_out<8>/XUSED (
.I(N46),
.O(N46_0)
);
X_BUF #(
.LOC ( "SLICE_X19Y26" ))
\shift_out<8>/DYMUX (
.I(shift_out_mux0000[8]),
.O(\shift_out<8>/DYMUX_1826 )
);
X_BUF #(
.LOC ( "SLICE_X19Y26" ))
\shift_out<8>/CLKINV (
.I(clk_BUFGP),
.O(\shift_out<8>/CLKINV_1816 )
);
X_BUF #(
.LOC ( "SLICE_X19Y26" ))
\shift_out<8>/CEINV (
.I(shift_out_not0001_0),
.O(\shift_out<8>/CEINV_1815 )
);
X_FF #(
.LOC ( "SLICE_X19Y26" ),
.INIT ( 1'b1 ))
shift_out_8 (
.I(\shift_out<8>/DYMUX_1826 ),
.CE(\shift_out<8>/CEINV_1815 ),
.CLK(\shift_out<8>/CLKINV_1816 ),
.SET(\shift_out<8>/FFY/SET ),
.RST(GND),
.O(shift_out[8])
);
X_BUF #(
.LOC ( "SLICE_X19Y26" ))
\shift_out<8>/FFY/SETOR (
.I(reset_IBUF_872),
.O(\shift_out<8>/FFY/SET )
);
X_BUF #(
.LOC ( "SLICE_X26Y27" ))
\baud1/timer<0>/XUSED (
.I(N47),
.O(N47_0)
);
X_BUF #(
.LOC ( "SLICE_X26Y27" ))
\baud1/timer<0>/DYMUX (
.I(\baud1/timer_mux0000 [7]),
.O(\baud1/timer<0>/DYMUX_1862 )
);
X_BUF #(
.LOC ( "SLICE_X26Y27" ))
\baud1/timer<0>/CLKINV (
.I(clk_BUFGP),
.O(\baud1/timer<0>/CLKINV_1853 )
);
X_BUF #(
.LOC ( "SLICE_X27Y23" ))
\baud1/timer<3>/FFX/RSTOR (
.I(\baud1/timer<3>/SRINV_1889 ),
.O(\baud1/timer<3>/FFX/RST )
);
X_FF #(
.LOC ( "SLICE_X27Y23" ),
.INIT ( 1'b0 ))
\baud1/timer_3 (
.I(\baud1/timer<3>/DXMUX_1911 ),
.CE(VCC),
.CLK(\baud1/timer<3>/CLKINV_1888 ),
.SET(GND),
.RST(\baud1/timer<3>/FFX/RST ),
.O(\baud1/timer [3])
);
X_BUF #(
.LOC ( "SLICE_X27Y23" ))
\baud1/timer<3>/DXMUX (
.I(\baud1/timer_mux0000 [4]),
.O(\baud1/timer<3>/DXMUX_1911 )
);
X_BUF #(
.LOC ( "SLICE_X27Y23" ))
\baud1/timer<3>/DYMUX (
.I(\baud1/timer_mux0000 [5]),
.O(\baud1/timer<3>/DYMUX_1897 )
);
X_BUF #(
.LOC ( "SLICE_X27Y23" ))
\baud1/timer<3>/SRINV (
.I(reset_IBUF_872),
.O(\baud1/timer<3>/SRINV_1889 )
);
X_BUF #(
.LOC ( "SLICE_X27Y23" ))
\baud1/timer<3>/CLKINV (
.I(clk_BUFGP),
.O(\baud1/timer<3>/CLKINV_1888 )
);
X_BUF #(
.LOC ( "SLICE_X26Y24" ))
\baud1/timer<5>/DXMUX (
.I(\baud1/timer_mux0000 [2]),
.O(\baud1/timer<5>/DXMUX_1953 )
);
X_BUF #(
.LOC ( "SLICE_X26Y24" ))
\baud1/timer<5>/DYMUX (
.I(\baud1/timer_mux0000 [3]),
.O(\baud1/timer<5>/DYMUX_1939 )
);
X_BUF #(
.LOC ( "SLICE_X26Y24" ))
\baud1/timer<5>/SRINV (
.I(reset_IBUF_872),
.O(\baud1/timer<5>/SRINV_1931 )
);
X_BUF #(
.LOC ( "SLICE_X26Y24" ))
\baud1/timer<5>/CLKINV (
.I(clk_BUFGP),
.O(\baud1/timer<5>/CLKINV_1930 )
);
X_BUF #(
.LOC ( "SLICE_X27Y26" ))
\baud1/timer<7>/DYMUX (
.I(\baud1/timer_mux0000 [0]),
.O(\baud1/timer<7>/DYMUX_1976 )
);
X_BUF #(
.LOC ( "SLICE_X27Y26" ))
\baud1/timer<7>/CLKINV (
.I(clk_BUFGP),
.O(\baud1/timer<7>/CLKINV_1967 )
);
X_BUF #(
.LOC ( "SLICE_X12Y25" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/DXMUX (
.I(\fifo1/Result<3>1 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/DXMUX_2021 )
);
X_BUF #(
.LOC ( "SLICE_X12Y25" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/DYMUX (
.I(\fifo1/Result<2>1 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/DYMUX_2006 )
);
X_BUF #(
.LOC ( "SLICE_X12Y25" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/SRINV (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_reg [1]),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/SRINV_1997 )
);
X_BUF #(
.LOC ( "SLICE_X12Y25" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/CLKINV (
.I(clk_BUFGP),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/CLKINV_1996 )
);
X_BUF #(
.LOC ( "SLICE_X12Y25" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/CEINV (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en_0 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/CEINV_1995 )
);
X_LUT4 #(
.INIT ( 16'h78F0 ),
.LOC ( "SLICE_X13Y27" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<3>11 (
.ADR0(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [2]),
.ADR1(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1]),
.ADR2(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [3]),
.ADR3(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0]),
.O(\fifo1/Result [3])
);
X_BUF #(
.LOC ( "SLICE_X13Y27" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/FFY/RSTOR (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/SRINV_2043 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/FFY/RST )
);
X_FF #(
.LOC ( "SLICE_X13Y27" ),
.INIT ( 1'b0 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_2 (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/DYMUX_2052 ),
.CE(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/CEINV_2041 ),
.CLK(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/CLKINV_2042 ),
.SET(GND),
.RST(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/FFY/RST ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [2])
);
X_BUF #(
.LOC ( "SLICE_X13Y27" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/DXMUX (
.I(\fifo1/Result [3]),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/DXMUX_2067 )
);
X_BUF #(
.LOC ( "SLICE_X13Y27" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/DYMUX (
.I(\fifo1/Result [2]),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/DYMUX_2052 )
);
X_BUF #(
.LOC ( "SLICE_X13Y27" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/SRINV (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg[2] ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/SRINV_2043 )
);
X_BUF #(
.LOC ( "SLICE_X13Y27" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/CLKINV (
.I(clk_BUFGP),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/CLKINV_2042 )
);
X_BUF #(
.LOC ( "SLICE_X13Y27" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/CEINV (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en_0 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/CEINV_2041 )
);
X_BUF #(
.LOC ( "SLICE_X14Y25" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/DXMUX (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2-In ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/DXMUX_2110 )
);
X_BUF #(
.LOC ( "SLICE_X14Y25" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/DYMUX (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/DYMUX_2096 )
);
X_BUF #(
.LOC ( "SLICE_X14Y25" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/SRINV (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg[2] ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/SRINV_2088 )
);
X_BUF #(
.LOC ( "SLICE_X14Y25" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/CLKINV (
.I(clk_BUFGP),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/CLKINV_2087 )
);
X_LUT4 #(
.INIT ( 16'hFFAB ),
.LOC ( "SLICE_X17Y25" ))
\pstate_FSM_FFd2-In1 (
.ADR0(pstate_FSM_FFd1_910),
.ADR1(empty),
.ADR2(pstate_FSM_FFd2_907),
.ADR3(N16_0),
.O(\pstate_FSM_FFd2-In )
);
X_BUF #(
.LOC ( "SLICE_X17Y25" ))
\pstate_FSM_FFd2_1/XUSED (
.I(bittime),
.O(bittime_0)
);
X_BUF #(
.LOC ( "SLICE_X17Y25" ))
\pstate_FSM_FFd2_1/DYMUX (
.I(\pstate_FSM_FFd2_1/GYMUX_2136 ),
.O(\pstate_FSM_FFd2_1/DYMUX_2137 )
);
X_BUF #(
.LOC ( "SLICE_X17Y25" ))
\pstate_FSM_FFd2_1/GYMUX (
.I(\pstate_FSM_FFd2-In ),
.O(\pstate_FSM_FFd2_1/GYMUX_2136 )
);
X_BUF #(
.LOC ( "SLICE_X17Y25" ))
\pstate_FSM_FFd2_1/CLKINV (
.I(clk_BUFGP),
.O(\pstate_FSM_FFd2_1/CLKINV_2128 )
);
X_BUF #(
.LOC ( "SLICE_X26Y20" ))
\control<1>/XUSED (
.I(wr_baud),
.O(wr_baud_0)
);
X_BUF #(
.LOC ( "SLICE_X26Y20" ))
\control<1>/DYMUX (
.I(control_1_mux0000),
.O(\control<1>/DYMUX_2176 )
);
X_BUF #(
.LOC ( "SLICE_X26Y20" ))
\control<1>/CLKINV (
.I(clk_BUFGP),
.O(\control<1>/CLKINV_2167 )
);
X_BUF #(
.LOC ( "SLICE_X26Y20" ))
\control<1>/CEINV (
.I(control_1_not0001),
.O(\control<1>/CEINV_2166 )
);
X_BUF #(
.LOC ( "SLICE_X19Y25" ))
\bitcounter<2>/DXMUX (
.I(Mcount_bitcounter2),
.O(\bitcounter<2>/DXMUX_2229 )
);
X_BUF #(
.LOC ( "SLICE_X19Y25" ))
\bitcounter<2>/DYMUX (
.I(Mcount_bitcounter1),
.O(\bitcounter<2>/DYMUX_2213 )
);
X_BUF #(
.LOC ( "SLICE_X19Y25" ))
\bitcounter<2>/SRINV (
.I(reset_IBUF_872),
.O(\bitcounter<2>/SRINV_2204 )
);
X_BUF #(
.LOC ( "SLICE_X19Y25" ))
\bitcounter<2>/CLKINV (
.I(clk_BUFGP),
.O(\bitcounter<2>/CLKINV_2203 )
);
X_BUF #(
.LOC ( "SLICE_X19Y25" ))
\bitcounter<2>/CEINV (
.I(bitcounter_not0001_0),
.O(\bitcounter<2>/CEINV_2202 )
);
X_BUF #(
.LOC ( "SLICE_X15Y24" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/XUSED (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en_0 )
);
X_BUF #(
.LOC ( "SLICE_X15Y24" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/DYMUX (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/GYMUX_2258 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/DYMUX_2259 )
);
X_BUF #(
.LOC ( "SLICE_X15Y24" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/GYMUX (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_or0000 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/GYMUX_2258 )
);
X_BUF #(
.LOC ( "SLICE_X15Y24" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/CLKINV (
.I(clk_BUFGP),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/CLKINV_2250 )
);
X_BUF #(
.LOC ( "SLICE_X17Y31" ))
\bittimer<3>/DXMUX (
.I(Result[3]),
.O(\bittimer<3>/DXMUX_2310 )
);
X_BUF #(
.LOC ( "SLICE_X17Y31" ))
\bittimer<3>/DYMUX (
.I(Result[2]),
.O(\bittimer<3>/DYMUX_2295 )
);
X_BUF #(
.LOC ( "SLICE_X17Y31" ))
\bittimer<3>/SRINV (
.I(reset_IBUF_872),
.O(\bittimer<3>/SRINV_2286 )
);
X_BUF #(
.LOC ( "SLICE_X17Y31" ))
\bittimer<3>/CLKINV (
.I(\baud1/baud_911 ),
.O(\bittimer<3>/CLKINV_2285 )
);
X_BUF #(
.LOC ( "SLICE_X17Y31" ))
\bittimer<3>/CEINV (
.I(bittime_0),
.O(\bittimer<3>/CEINV_2284 )
);
X_BUF #(
.LOC ( "SLICE_X17Y27" ))
\shift_out<1>/DXMUX (
.I(shift_out_mux0000[1]),
.O(\shift_out<1>/DXMUX_2355 )
);
X_BUF #(
.LOC ( "SLICE_X17Y27" ))
\shift_out<1>/DYMUX (
.I(shift_out_mux0000[0]),
.O(\shift_out<1>/DYMUX_2341 )
);
X_BUF #(
.LOC ( "SLICE_X17Y27" ))
\shift_out<1>/SRINV (
.I(reset_IBUF_872),
.O(\shift_out<1>/SRINV_2332 )
);
X_BUF #(
.LOC ( "SLICE_X17Y27" ))
\shift_out<1>/CLKINV (
.I(clk_BUFGP),
.O(\shift_out<1>/CLKINV_2331 )
);
X_BUF #(
.LOC ( "SLICE_X17Y27" ))
\shift_out<1>/CEINV (
.I(shift_out_not0001_0),
.O(\shift_out<1>/CEINV_2330 )
);
X_BUF #(
.LOC ( "SLICE_X14Y27" ))
\shift_out<3>/DXMUX (
.I(shift_out_mux0000[3]),
.O(\shift_out<3>/DXMUX_2399 )
);
X_BUF #(
.LOC ( "SLICE_X14Y27" ))
\shift_out<3>/DYMUX (
.I(shift_out_mux0000[2]),
.O(\shift_out<3>/DYMUX_2385 )
);
X_BUF #(
.LOC ( "SLICE_X14Y27" ))
\shift_out<3>/SRINV (
.I(reset_IBUF_872),
.O(\shift_out<3>/SRINV_2377 )
);
X_BUF #(
.LOC ( "SLICE_X14Y27" ))
\shift_out<3>/CLKINV (
.I(clk_BUFGP),
.O(\shift_out<3>/CLKINV_2376 )
);
X_BUF #(
.LOC ( "SLICE_X14Y27" ))
\shift_out<3>/CEINV (
.I(shift_out_not0001_0),
.O(\shift_out<3>/CEINV_2375 )
);
X_BUF #(
.LOC ( "SLICE_X14Y30" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg/DYMUX (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg/BYINV_2462 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg/DYMUX_2463 )
);
X_BUF #(
.LOC ( "SLICE_X14Y30" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg/BYINV (
.I(1'b0),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg/BYINV_2462 )
);
X_BUF #(
.LOC ( "SLICE_X14Y30" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg/CLKINV (
.I(clk_BUFGP),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg/CLKINV_2460 )
);
X_BUF #(
.LOC ( "SLICE_X14Y30" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg/CEINV (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_1004 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg/CEINV_2459 )
);
X_BUF #(
.LOC ( "SLICE_X26Y23" ))
\baud1/period<1>/DXMUX (
.I(din_1_IBUF_876),
.O(\baud1/period<1>/DXMUX_2490 )
);
X_BUF #(
.LOC ( "SLICE_X26Y23" ))
\baud1/period<1>/DYMUX (
.I(din_0_IBUF_874),
.O(\baud1/period<1>/DYMUX_2481 )
);
X_BUF #(
.LOC ( "SLICE_X26Y23" ))
\baud1/period<1>/SRINV (
.I(reset_IBUF_872),
.O(\baud1/period<1>/SRINV_2479 )
);
X_BUF #(
.LOC ( "SLICE_X26Y23" ))
\baud1/period<1>/CLKINV (
.I(clk_BUFGP),
.O(\baud1/period<1>/CLKINV_2478 )
);
X_BUF #(
.LOC ( "SLICE_X26Y23" ))
\baud1/period<1>/CEINV (
.I(wr_baud_0),
.O(\baud1/period<1>/CEINV_2477 )
);
X_BUF #(
.LOC ( "SLICE_X30Y22" ))
\baud1/period<3>/DXMUX (
.I(din_3_IBUF_856),
.O(\baud1/period<3>/DXMUX_2517 )
);
X_BUF #(
.LOC ( "SLICE_X30Y22" ))
\baud1/period<3>/DYMUX (
.I(din_2_IBUF_854),
.O(\baud1/period<3>/DYMUX_2508 )
);
X_BUF #(
.LOC ( "SLICE_X30Y22" ))
\baud1/period<3>/SRINV (
.I(reset_IBUF_872),
.O(\baud1/period<3>/SRINV_2506 )
);
X_BUF #(
.LOC ( "SLICE_X30Y22" ))
\baud1/period<3>/CLKINV (
.I(clk_BUFGP),
.O(\baud1/period<3>/CLKINV_2505 )
);
X_BUF #(
.LOC ( "SLICE_X30Y22" ))
\baud1/period<3>/CEINV (
.I(wr_baud_0),
.O(\baud1/period<3>/CEINV_2504 )
);
X_BUF #(
.LOC ( "SLICE_X28Y24" ))
\baud1/baud_cmp_eq00008120/XUSED (
.I(\baud1/baud_cmp_eq00008120_2545 ),
.O(\baud1/baud_cmp_eq00008120_0 )
);
X_BUF #(
.LOC ( "SLICE_X31Y23" ))
\baud1/period<5>/DXMUX (
.I(din_5_IBUF_858),
.O(\baud1/period<5>/DXMUX_2567 )
);
X_BUF #(
.LOC ( "SLICE_X31Y23" ))
\baud1/period<5>/DYMUX (
.I(din_4_IBUF_857),
.O(\baud1/period<5>/DYMUX_2559 )
);
X_BUF #(
.LOC ( "SLICE_X31Y23" ))
\baud1/period<5>/SRINV (
.I(reset_IBUF_872),
.O(\baud1/period<5>/SRINV_2557 )
);
X_BUF #(
.LOC ( "SLICE_X31Y23" ))
\baud1/period<5>/CLKINV (
.I(clk_BUFGP),
.O(\baud1/period<5>/CLKINV_2556 )
);
X_BUF #(
.LOC ( "SLICE_X31Y23" ))
\baud1/period<5>/CEINV (
.I(wr_baud_0),
.O(\baud1/period<5>/CEINV_2555 )
);
X_BUF #(
.LOC ( "SLICE_X16Y25" ))
\bitcounter<0>/DXMUX (
.I(Mcount_bitcounter),
.O(\bitcounter<0>/DXMUX_2605 )
);
X_BUF #(
.LOC ( "SLICE_X16Y25" ))
\bitcounter<0>/YUSED (
.I(N2_pack_2),
.O(N2)
);
X_BUF #(
.LOC ( "SLICE_X16Y25" ))
\bitcounter<0>/CLKINV (
.I(clk_BUFGP),
.O(\bitcounter<0>/CLKINV_2588 )
);
X_BUF #(
.LOC ( "SLICE_X16Y25" ))
\bitcounter<0>/CEINV (
.I(bitcounter_not0001_0),
.O(\bitcounter<0>/CEINV_2587 )
);
X_BUF #(
.LOC ( "SLICE_X29Y23" ))
\baud1/period<7>/DXMUX (
.I(din_7_IBUF_861),
.O(\baud1/period<7>/DXMUX_2633 )
);
X_BUF #(
.LOC ( "SLICE_X29Y23" ))
\baud1/period<7>/DYMUX (
.I(din_6_IBUF_860),
.O(\baud1/period<7>/DYMUX_2624 )
);
X_BUF #(
.LOC ( "SLICE_X29Y23" ))
\baud1/period<7>/SRINV (
.I(reset_IBUF_872),
.O(\baud1/period<7>/SRINV_2622 )
);
X_BUF #(
.LOC ( "SLICE_X29Y23" ))
\baud1/period<7>/CLKINV (
.I(clk_BUFGP),
.O(\baud1/period<7>/CLKINV_2621 )
);
X_BUF #(
.LOC ( "SLICE_X29Y23" ))
\baud1/period<7>/CEINV (
.I(wr_baud_0),
.O(\baud1/period<7>/CEINV_2620 )
);
X_INV #(
.LOC ( "SLICE_X20Y26" ))
\baud1/baud/DYMUX (
.I(\baud1/baud_911 ),
.O(\baud1/baud/DYMUX_2650 )
);
X_BUF #(
.LOC ( "SLICE_X20Y26" ))
\baud1/baud/CLKINV (
.I(clk_BUFGP),
.O(\baud1/baud/CLKINV_2647 )
);
X_BUF #(
.LOC ( "SLICE_X20Y26" ))
\baud1/baud/CEINV (
.I(\baud1/baud_cmp_eq0000_0 ),
.O(\baud1/baud/CEINV_2646 )
);
X_BUF #(
.LOC ( "SLICE_X12Y30" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2/DXMUX (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_1004 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2/DXMUX_2670 )
);
X_BUF #(
.LOC ( "SLICE_X12Y30" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2/DYMUX (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_1005 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2/DYMUX_2665 )
);
X_BUF #(
.LOC ( "SLICE_X12Y30" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2/CLKINV (
.I(clk_BUFGP),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2/CLKINV_2663 )
);
X_BUF #(
.LOC ( "SLICE_X15Y26" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en/XUSED (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en_0 )
);
X_BUF #(
.LOC ( "SLICE_X15Y26" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en/YUSED (
.I(ld_shift_pack_1),
.O(ld_shift)
);
X_BUF #(
.LOC ( "SLICE_X31Y18" ))
\dout_7_OBUF/YUSED (
.I(N3_pack_1),
.O(N3)
);
X_INV #(
.LOC ( "SLICE_X15Y22" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<0>/DXMUX (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [0]),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<0>/DXMUX_2775 )
);
X_BUF #(
.LOC ( "SLICE_X15Y22" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<0>/XUSED (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb40_2772 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb40_0 )
);
X_BUF #(
.LOC ( "SLICE_X15Y22" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<0>/DYMUX (
.I(\fifo1/Result<1>1 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<0>/DYMUX_2759 )
);
X_BUF #(
.LOC ( "SLICE_X15Y22" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<0>/SRINV (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_reg [1]),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<0>/SRINV_2749 )
);
X_BUF #(
.LOC ( "SLICE_X15Y22" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<0>/CLKINV (
.I(clk_BUFGP),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<0>/CLKINV_2748 )
);
X_BUF #(
.LOC ( "SLICE_X15Y22" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<0>/CEINV (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en_0 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<0>/CEINV_2747 )
);
X_INV #(
.LOC ( "SLICE_X13Y23" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/DXMUX (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0]),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/DXMUX_2823 )
);
X_BUF #(
.LOC ( "SLICE_X13Y23" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/XUSED (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or000014_2820 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or000014_0 )
);
X_BUF #(
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\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_reg<1>/CLKINV (
.I(clk_BUFGP),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_reg<1>/CLKINV_3421 )
);
X_BUF #(
.LOC ( "SLICE_X14Y28" ))
\empty/DYMUX (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/GYMUX_2258 ),
.O(\empty/DYMUX_3437 )
);
X_BUF #(
.LOC ( "SLICE_X14Y28" ))
\empty/CLKINV (
.I(clk_BUFGP),
.O(\empty/CLKINV_3434 )
);
X_BUF #(
.LOC ( "SLICE_X19Y27" ))
\bitcounter<3>/DXMUX (
.I(Mcount_bitcounter3),
.O(\bitcounter<3>/DXMUX_3473 )
);
X_BUF #(
.LOC ( "SLICE_X19Y27" ))
\bitcounter<3>/YUSED (
.I(N29_pack_2),
.O(N29)
);
X_BUF #(
.LOC ( "SLICE_X19Y27" ))
\bitcounter<3>/CLKINV (
.I(clk_BUFGP),
.O(\bitcounter<3>/CLKINV_3457 )
);
X_BUF #(
.LOC ( "SLICE_X19Y27" ))
\bitcounter<3>/CEINV (
.I(bitcounter_not0001_0),
.O(\bitcounter<3>/CEINV_3456 )
);
X_BUF #(
.LOC ( "SLICE_X18Y27" ))
\N30/XUSED (
.I(N30),
.O(N30_0)
);
X_BUF #(
.LOC ( "SLICE_X29Y20" ))
\control_1_not00017/XUSED (
.I(control_1_not00017_3502),
.O(control_1_not00017_0)
);
X_LUT4 #(
.INIT ( 16'h1020 ),
.LOC ( "SLICE_X26Y26" ))
\baud1/timer_mux0000<1>1 (
.ADR0(\baud1/timer [6]),
.ADR1(\baud1/baud_cmp_eq0000_0 ),
.ADR2(N36),
.ADR3(\baud1/Madd_timer_addsub0000_cy[5] ),
.O(\baud1/timer_mux0000 [1])
);
X_LUT4 #(
.INIT ( 16'h0203 ),
.LOC ( "SLICE_X27Y23" ))
\baud1/timer_mux0000<4> (
.ADR0(pstate_FSM_FFd2_907),
.ADR1(N34_0),
.ADR2(\baud1/baud_cmp_eq0000_0 ),
.ADR3(empty),
.O(\baud1/timer_mux0000 [4])
);
X_FF #(
.LOC ( "SLICE_X27Y26" ),
.INIT ( 1'b0 ))
\baud1/timer_7 (
.I(\baud1/timer<7>/DYMUX_1976 ),
.CE(VCC),
.CLK(\baud1/timer<7>/CLKINV_1967 ),
.SET(GND),
.RST(\baud1/timer<7>/FFY/RSTAND_1981 ),
.O(\baud1/timer [7])
);
X_BUF #(
.LOC ( "SLICE_X27Y26" ))
\baud1/timer<7>/FFY/RSTAND (
.I(reset_IBUF_872),
.O(\baud1/timer<7>/FFY/RSTAND_1981 )
);
X_BUF #(
.LOC ( "PAD54" ))
\addr<2>/IFF/IMUX (
.I(\addr<2>/INBUF ),
.O(addr_2_IBUF_853)
);
X_BUF #(
.LOC ( "PAD34" ))
\din<2>/IFF/IMUX (
.I(\din<2>/INBUF ),
.O(din_2_IBUF_854)
);
X_BUF #(
.LOC ( "PAD43" ))
\wren/IFF/IMUX (
.I(\wren/INBUF ),
.O(wren_IBUF_855)
);
X_BUF #(
.LOC ( "PAD31" ))
\din<4>/IFF/IMUX (
.I(\din<4>/INBUF ),
.O(din_4_IBUF_857)
);
X_BUF #(
.LOC ( "PAD35" ))
\din<5>/IFF/IMUX (
.I(\din<5>/INBUF ),
.O(din_5_IBUF_858)
);
X_BUF #(
.LOC ( "PAD28" ))
\rden/IFF/IMUX (
.I(\rden/INBUF ),
.O(rden_IBUF_859)
);
X_BUF #(
.LOC ( "PAD30" ))
\din<6>/IFF/IMUX (
.I(\din<6>/INBUF ),
.O(din_6_IBUF_860)
);
X_BUF #(
.LOC ( "PAD33" ))
\din<7>/IFF/IMUX (
.I(\din<7>/INBUF ),
.O(din_7_IBUF_861)
);
X_BUF #(
.LOC ( "PAD29" ))
\reset/IFF/IMUX (
.I(\reset/INBUF ),
.O(reset_IBUF_872)
);
X_BUF #(
.LOC ( "PAD53" ))
\addr<0>/IFF/IMUX (
.I(\addr<0>/INBUF ),
.O(addr_0_IBUF_873)
);
X_BUF #(
.LOC ( "PAD40" ))
\din<0>/IFF/IMUX (
.I(\din<0>/INBUF ),
.O(din_0_IBUF_874)
);
X_BUF #(
.LOC ( "PAD47" ))
\addr<1>/IFF/IMUX (
.I(\addr<1>/INBUF ),
.O(addr_1_IBUF_875)
);
X_BUF #(
.LOC ( "IPAD36" ))
\din<1>/IFF/IMUX (
.I(\din<1>/INBUF ),
.O(din_1_IBUF_876)
);
X_LUT4 #(
.INIT ( 16'h0200 ),
.LOC ( "SLICE_X31Y20" ))
\dout<1>2 (
.ADR0(rden_IBUF_859),
.ADR1(addr_0_IBUF_873),
.ADR2(addr_2_IBUF_853),
.ADR3(\baud1/period [1]),
.O(\dout<1>2_1373 )
);
X_LUT4 #(
.INIT ( 16'h0080 ),
.LOC ( "SLICE_X31Y20" ))
\dout<1>1 (
.ADR0(addr_0_IBUF_873),
.ADR1(control[1]),
.ADR2(rden_IBUF_859),
.ADR3(addr_2_IBUF_853),
.O(\dout<1>1_1380 )
);
X_LUT4 #(
.INIT ( 16'hF0FF ),
.LOC ( "SLICE_X27Y27" ))
\baud1/timer_mux0000<0>11_SW1 (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(pstate_FSM_FFd2_907),
.ADR3(empty),
.O(N36_pack_2)
);
X_LUT4 #(
.INIT ( 16'h0408 ),
.LOC ( "SLICE_X27Y27" ))
\baud1/timer_mux0000<6>1 (
.ADR0(\baud1/timer [1]),
.ADR1(N36),
.ADR2(\baud1/baud_cmp_eq0000_0 ),
.ADR3(\baud1/timer [0]),
.O(\baud1/timer_mux0000 [6])
);
X_FF #(
.LOC ( "SLICE_X27Y27" ),
.INIT ( 1'b0 ))
\baud1/timer_1 (
.I(\baud1/timer<1>/DXMUX_1437 ),
.CE(VCC),
.CLK(\baud1/timer<1>/CLKINV_1419 ),
.SET(GND),
.RST(\baud1/timer<1>/FFX/RSTAND_1442 ),
.O(\baud1/timer [1])
);
X_BUF #(
.LOC ( "SLICE_X27Y27" ))
\baud1/timer<1>/FFX/RSTAND (
.I(reset_IBUF_872),
.O(\baud1/timer<1>/FFX/RSTAND_1442 )
);
X_LUT4 #(
.INIT ( 16'h0002 ),
.LOC ( "SLICE_X18Y26" ))
bitcounter_not00012 (
.ADR0(pstate_FSM_FFd1_910),
.ADR1(bittimer[2]),
.ADR2(N27_0),
.ADR3(\baud1/baud_911 ),
.O(N14_pack_1)
);
X_LUT4 #(
.INIT ( 16'hFF03 ),
.LOC ( "SLICE_X18Y26" ))
shift_out_not00012 (
.ADR0(VCC),
.ADR1(empty),
.ADR2(pstate_FSM_FFd2_907),
.ADR3(N14),
.O(shift_out_not0001)
);
X_LUT4 #(
.INIT ( 16'h0040 ),
.LOC ( "SLICE_X24Y22" ))
control_1_not000121 (
.ADR0(bitcounter[2]),
.ADR1(bitcounter[3]),
.ADR2(bitcounter[1]),
.ADR3(pstate_FSM_FFd1_910),
.O(\control_1_not000121/O_pack_1 )
);
X_LUT4 #(
.INIT ( 16'hAEAA ),
.LOC ( "SLICE_X24Y22" ))
control_1_not000131 (
.ADR0(control_1_not00017_0),
.ADR1(pstate_FSM_FFd2_907),
.ADR2(bitcounter[0]),
.ADR3(\control_1_not000121/O ),
.O(control_1_not0001)
);
X_LUT4 #(
.INIT ( 16'hFFDF ),
.LOC ( "SLICE_X18Y24" ))
bitcounter_not0001_SW0 (
.ADR0(bitcounter[1]),
.ADR1(bitcounter[0]),
.ADR2(bitcounter[3]),
.ADR3(bitcounter[2]),
.O(\bitcounter_not0001_SW0/O_pack_1 )
);
X_LUT4 #(
.INIT ( 16'hCCDC ),
.LOC ( "SLICE_X18Y24" ))
bitcounter_not0001 (
.ADR0(pstate_FSM_FFd1_910),
.ADR1(N14),
.ADR2(pstate_FSM_FFd2_907),
.ADR3(\bitcounter_not0001_SW0/O ),
.O(bitcounter_not0001_1537)
);
X_LUT4 #(
.INIT ( 16'h8400 ),
.LOC ( "SLICE_X15Y23" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb84_SW0 (
.ADR0(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1]),
.ADR1(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb40_0 ),
.ADR2(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [1]),
.ADR3(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb67_0 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb84_SW0/O_pack_1 )
);
X_LUT4 #(
.INIT ( 16'hB3A2 ),
.LOC ( "SLICE_X15Y23" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb97 (
.ADR0(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb5_0 ),
.ADR1(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en_0 ),
.ADR2(\fifo1/N8_0 ),
.ADR3(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb84_SW0/O ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb )
);
X_LUT4 #(
.INIT ( 16'hAAFF ),
.LOC ( "SLICE_X16Y24" ))
\pstate_FSM_FFd1-In3_SW0 (
.ADR0(bitcounter[0]),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(bitcounter[1]),
.O(\pstate_FSM_FFd1-In3_SW0/O_pack_1 )
);
X_LUT4 #(
.INIT ( 16'hCC8C ),
.LOC ( "SLICE_X16Y24" ))
\pstate_FSM_FFd1-In3 (
.ADR0(bitcounter[2]),
.ADR1(pstate_FSM_FFd2_907),
.ADR2(bitcounter[3]),
.ADR3(\pstate_FSM_FFd1-In3_SW0/O ),
.O(N16)
);
X_LUT4 #(
.INIT ( 16'h8000 ),
.LOC ( "SLICE_X26Y25" ))
\baud1/Madd_timer_addsub0000_cy<3>11 (
.ADR0(\baud1/timer [2]),
.ADR1(\baud1/timer [1]),
.ADR2(\baud1/timer [0]),
.ADR3(\baud1/timer [3]),
.O(\baud1/Madd_timer_addsub0000_cy<3>_pack_1 )
);
X_LUT4 #(
.INIT ( 16'hC03F ),
.LOC ( "SLICE_X26Y25" ))
\baud1/timer_mux0000<0>11_SW5 (
.ADR0(VCC),
.ADR1(\baud1/timer [4]),
.ADR2(\baud1/Madd_timer_addsub0000_cy[3] ),
.ADR3(\baud1/timer [5]),
.O(N44)
);
X_LUT4 #(
.INIT ( 16'h7BDE ),
.LOC ( "SLICE_X12Y22" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or00003168_SW0 (
.ADR0(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1]),
.ADR1(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0]),
.ADR2(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1]),
.ADR3(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0]),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or00003168_SW0/O_pack_1 )
);
X_LUT4 #(
.INIT ( 16'hFFDE ),
.LOC ( "SLICE_X12Y22" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or00003168 (
.ADR0(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3]),
.ADR1(\fifo1/N6_0 ),
.ADR2(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3]),
.ADR3(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or00003168_SW0/O ),
.O(\fifo1/N8 )
);
X_FF #(
.LOC ( "SLICE_X26Y26" ),
.INIT ( 1'b0 ))
\baud1/timer_6 (
.I(\baud1/timer<6>/DXMUX_1675 ),
.CE(VCC),
.CLK(\baud1/timer<6>/CLKINV_1658 ),
.SET(GND),
.RST(\baud1/timer<6>/FFX/RSTAND_1680 ),
.O(\baud1/timer [6])
);
X_BUF #(
.LOC ( "SLICE_X26Y26" ))
\baud1/timer<6>/FFX/RSTAND (
.I(reset_IBUF_872),
.O(\baud1/timer<6>/FFX/RSTAND_1680 )
);
X_LUT4 #(
.INIT ( 16'h8000 ),
.LOC ( "SLICE_X14Y23" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or000079 (
.ADR0(\fifo1/N01_0 ),
.ADR1(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or000014_0 ),
.ADR2(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en_0 ),
.ADR3(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or000062_0 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or000079/O_pack_2 )
);
X_LUT4 #(
.INIT ( 16'hF8FA ),
.LOC ( "SLICE_X14Y23" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or000092 (
.ADR0(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_951 ),
.ADR1(\fifo1/N8_0 ),
.ADR2(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or000079/O ),
.ADR3(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en_0 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or0000 )
);
X_FF #(
.LOC ( "SLICE_X14Y23" ),
.INIT ( 1'b1 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/DXMUX_1710 ),
.CE(VCC),
.CLK(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/CLKINV_1694 ),
.SET(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/FFX/SET ),
.RST(GND),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_951 )
);
X_BUF #(
.LOC ( "SLICE_X14Y23" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/FFX/SETOR (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg[2] ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/FFX/SET )
);
X_LUT4 #(
.INIT ( 16'hFE02 ),
.LOC ( "SLICE_X15Y25" ))
\shift_out_mux0000<4>1 (
.ADR0(to_shift[3]),
.ADR1(empty),
.ADR2(pstate_FSM_FFd2_907),
.ADR3(shift_out[5]),
.O(shift_out_mux0000[4])
);
X_FF #(
.LOC ( "SLICE_X15Y25" ),
.INIT ( 1'b1 ))
shift_out_4 (
.I(\shift_out<5>/DYMUX_1739 ),
.CE(\shift_out<5>/CEINV_1729 ),
.CLK(\shift_out<5>/CLKINV_1730 ),
.SET(\shift_out<5>/SRINV_1731 ),
.RST(GND),
.O(shift_out[4])
);
X_LUT4 #(
.INIT ( 16'hAAB8 ),
.LOC ( "SLICE_X16Y26" ))
\shift_out_mux0000<6>1 (
.ADR0(shift_out[7]),
.ADR1(empty),
.ADR2(to_shift[5]),
.ADR3(pstate_FSM_FFd2_907),
.O(shift_out_mux0000[6])
);
X_FF #(
.LOC ( "SLICE_X16Y26" ),
.INIT ( 1'b1 ))
shift_out_6 (
.I(\shift_out<7>/DYMUX_1783 ),
.CE(\shift_out<7>/CEINV_1773 ),
.CLK(\shift_out<7>/CLKINV_1774 ),
.SET(\shift_out<7>/SRINV_1775 ),
.RST(GND),
.O(shift_out[6])
);
X_LUT4 #(
.INIT ( 16'hAAB8 ),
.LOC ( "SLICE_X16Y26" ))
\shift_out_mux0000<7>1 (
.ADR0(shift_out[8]),
.ADR1(empty),
.ADR2(to_shift[6]),
.ADR3(pstate_FSM_FFd2_907),
.O(shift_out_mux0000[7])
);
X_FF #(
.LOC ( "SLICE_X16Y26" ),
.INIT ( 1'b1 ))
shift_out_7 (
.I(\shift_out<7>/DXMUX_1797 ),
.CE(\shift_out<7>/CEINV_1773 ),
.CLK(\shift_out<7>/CLKINV_1774 ),
.SET(\shift_out<7>/SRINV_1775 ),
.RST(GND),
.O(shift_out[7])
);
X_LUT4 #(
.INIT ( 16'hFEFE ),
.LOC ( "SLICE_X19Y26" ))
\shift_out_mux0000<8>1 (
.ADR0(to_shift[7]),
.ADR1(pstate_FSM_FFd2_907),
.ADR2(empty),
.ADR3(VCC),
.O(shift_out_mux0000[8])
);
X_LUT4 #(
.INIT ( 16'h1101 ),
.LOC ( "SLICE_X26Y27" ))
\baud1/timer_mux0000<7>1 (
.ADR0(\baud1/timer [0]),
.ADR1(\baud1/baud_cmp_eq0000_0 ),
.ADR2(empty),
.ADR3(pstate_FSM_FFd2_907),
.O(\baud1/timer_mux0000 [7])
);
X_FF #(
.LOC ( "SLICE_X26Y27" ),
.INIT ( 1'b0 ))
\baud1/timer_0 (
.I(\baud1/timer<0>/DYMUX_1862 ),
.CE(VCC),
.CLK(\baud1/timer<0>/CLKINV_1853 ),
.SET(GND),
.RST(\baud1/timer<0>/FFY/RSTAND_1867 ),
.O(\baud1/timer [0])
);
X_BUF #(
.LOC ( "SLICE_X26Y27" ))
\baud1/timer<0>/FFY/RSTAND (
.I(reset_IBUF_872),
.O(\baud1/timer<0>/FFY/RSTAND_1867 )
);
X_LUT4 #(
.INIT ( 16'h99F9 ),
.LOC ( "SLICE_X26Y27" ))
\baud1/timer_mux0000<0>11_SW7 (
.ADR0(\baud1/timer [7]),
.ADR1(\baud1/timer [6]),
.ADR2(empty),
.ADR3(pstate_FSM_FFd2_907),
.O(N47)
);
X_FF #(
.LOC ( "SLICE_X27Y23" ),
.INIT ( 1'b0 ))
\baud1/timer_2 (
.I(\baud1/timer<3>/DYMUX_1897 ),
.CE(VCC),
.CLK(\baud1/timer<3>/CLKINV_1888 ),
.SET(GND),
.RST(\baud1/timer<3>/SRINV_1889 ),
.O(\baud1/timer [2])
);
X_LUT4 #(
.INIT ( 16'h000B ),
.LOC ( "SLICE_X27Y23" ))
\baud1/timer_mux0000<5>1 (
.ADR0(pstate_FSM_FFd2_907),
.ADR1(empty),
.ADR2(\baud1/baud_cmp_eq0000_0 ),
.ADR3(N42_0),
.O(\baud1/timer_mux0000 [5])
);
X_FF #(
.LOC ( "SLICE_X26Y24" ),
.INIT ( 1'b0 ))
\baud1/timer_4 (
.I(\baud1/timer<5>/DYMUX_1939 ),
.CE(VCC),
.CLK(\baud1/timer<5>/CLKINV_1930 ),
.SET(GND),
.RST(\baud1/timer<5>/SRINV_1931 ),
.O(\baud1/timer [4])
);
X_LUT4 #(
.INIT ( 16'h0048 ),
.LOC ( "SLICE_X26Y24" ))
\baud1/timer_mux0000<3>1 (
.ADR0(\baud1/timer [4]),
.ADR1(N36),
.ADR2(\baud1/Madd_timer_addsub0000_cy[3] ),
.ADR3(\baud1/baud_cmp_eq0000_0 ),
.O(\baud1/timer_mux0000 [3])
);
X_LUT4 #(
.INIT ( 16'h0031 ),
.LOC ( "SLICE_X26Y24" ))
\baud1/timer_mux0000<2>1 (
.ADR0(empty),
.ADR1(N44_0),
.ADR2(pstate_FSM_FFd2_907),
.ADR3(\baud1/baud_cmp_eq0000_0 ),
.O(\baud1/timer_mux0000 [2])
);
X_FF #(
.LOC ( "SLICE_X26Y24" ),
.INIT ( 1'b0 ))
\baud1/timer_5 (
.I(\baud1/timer<5>/DXMUX_1953 ),
.CE(VCC),
.CLK(\baud1/timer<5>/CLKINV_1930 ),
.SET(GND),
.RST(\baud1/timer<5>/SRINV_1931 ),
.O(\baud1/timer [5])
);
X_LUT4 #(
.INIT ( 16'h0213 ),
.LOC ( "SLICE_X27Y26" ))
\baud1/timer_mux0000<0>1 (
.ADR0(\baud1/Madd_timer_addsub0000_cy[5] ),
.ADR1(\baud1/baud_cmp_eq0000_0 ),
.ADR2(N47_0),
.ADR3(N46_0),
.O(\baud1/timer_mux0000 [0])
);
X_LUT4 #(
.INIT ( 16'h66AA ),
.LOC ( "SLICE_X13Y27" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<2>11 (
.ADR0(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [2]),
.ADR1(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1]),
.ADR2(VCC),
.ADR3(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0]),
.O(\fifo1/Result [2])
);
X_LUT4 #(
.INIT ( 16'h3CF0 ),
.LOC ( "SLICE_X12Y25" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<2>11 (
.ADR0(VCC),
.ADR1(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [0]),
.ADR2(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [2]),
.ADR3(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [1]),
.O(\fifo1/Result<2>1 )
);
X_FF #(
.LOC ( "SLICE_X12Y25" ),
.INIT ( 1'b0 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_2 (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/DYMUX_2006 ),
.CE(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/CEINV_1995 ),
.CLK(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/CLKINV_1996 ),
.SET(GND),
.RST(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/SRINV_1997 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [2])
);
X_LUT4 #(
.INIT ( 16'h78F0 ),
.LOC ( "SLICE_X12Y25" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<3>11 (
.ADR0(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [2]),
.ADR1(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [0]),
.ADR2(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [3]),
.ADR3(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [1]),
.O(\fifo1/Result<3>1 )
);
X_FF #(
.LOC ( "SLICE_X12Y25" ),
.INIT ( 1'b0 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_3 (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/DXMUX_2021 ),
.CE(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/CEINV_1995 ),
.CLK(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/CLKINV_1996 ),
.SET(GND),
.RST(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/SRINV_1997 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [3])
);
X_FF #(
.LOC ( "SLICE_X17Y25" ),
.INIT ( 1'b0 ))
pstate_FSM_FFd2_1 (
.I(\pstate_FSM_FFd2_1/DYMUX_2137 ),
.CE(VCC),
.CLK(\pstate_FSM_FFd2_1/CLKINV_2128 ),
.SET(GND),
.RST(\pstate_FSM_FFd2_1/FFY/RSTAND_2142 ),
.O(pstate_FSM_FFd2_1_981)
);
X_BUF #(
.LOC ( "SLICE_X17Y25" ))
\pstate_FSM_FFd2_1/FFY/RSTAND (
.I(reset_IBUF_872),
.O(\pstate_FSM_FFd2_1/FFY/RSTAND_2142 )
);
X_FF #(
.LOC ( "SLICE_X13Y27" ),
.INIT ( 1'b0 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_3 (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/DXMUX_2067 ),
.CE(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/CEINV_2041 ),
.CLK(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/CLKINV_2042 ),
.SET(GND),
.RST(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/SRINV_2043 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [3])
);
X_FF #(
.LOC ( "SLICE_X14Y25" ),
.INIT ( 1'b0 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1 (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/DYMUX_2096 ),
.CE(VCC),
.CLK(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/CLKINV_2087 ),
.SET(GND),
.RST(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/SRINV_2088 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_979 )
);
X_LUT4 #(
.INIT ( 16'h0F8F ),
.LOC ( "SLICE_X14Y25" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In1 (
.ADR0(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_980 ),
.ADR1(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_979 ),
.ADR2(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_951 ),
.ADR3(ld_shift),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In )
);
X_LUT4 #(
.INIT ( 16'hEEEC ),
.LOC ( "SLICE_X14Y25" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2-In1 (
.ADR0(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_980 ),
.ADR1(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_979 ),
.ADR2(empty),
.ADR3(pstate_FSM_FFd2_1_981),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2-In )
);
X_FF #(
.LOC ( "SLICE_X14Y25" ),
.INIT ( 1'b0 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2 (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/DXMUX_2110 ),
.CE(VCC),
.CLK(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/CLKINV_2087 ),
.SET(GND),
.RST(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/SRINV_2088 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_980 )
);
X_LUT4 #(
.INIT ( 16'hFFCC ),
.LOC ( "SLICE_X17Y25" ))
bittime1 (
.ADR0(VCC),
.ADR1(pstate_FSM_FFd1_910),
.ADR2(VCC),
.ADR3(N16_0),
.O(bittime)
);
X_LUT4 #(
.INIT ( 16'hFF7F ),
.LOC ( "SLICE_X26Y20" ))
control_1_mux00001 (
.ADR0(addr_1_IBUF_875),
.ADR1(wren_IBUF_855),
.ADR2(addr_0_IBUF_873),
.ADR3(addr_2_IBUF_853),
.O(control_1_mux0000)
);
X_FF #(
.LOC ( "SLICE_X26Y20" ),
.INIT ( 1'b0 ))
control_1 (
.I(\control<1>/DYMUX_2176 ),
.CE(\control<1>/CEINV_2166 ),
.CLK(\control<1>/CLKINV_2167 ),
.SET(GND),
.RST(\control<1>/FFY/RSTAND_2182 ),
.O(control[1])
);
X_BUF #(
.LOC ( "SLICE_X26Y20" ))
\control<1>/FFY/RSTAND (
.I(reset_IBUF_872),
.O(\control<1>/FFY/RSTAND_2182 )
);
X_LUT4 #(
.INIT ( 16'h0004 ),
.LOC ( "SLICE_X26Y20" ))
wr_baud1 (
.ADR0(addr_1_IBUF_875),
.ADR1(wren_IBUF_855),
.ADR2(addr_0_IBUF_873),
.ADR3(addr_2_IBUF_853),
.O(wr_baud)
);
X_LUT4 #(
.INIT ( 16'h0AF0 ),
.LOC ( "SLICE_X19Y25" ))
\Mcount_bitcounter_xor<1>12 (
.ADR0(N2),
.ADR1(VCC),
.ADR2(bitcounter[0]),
.ADR3(bitcounter[1]),
.O(Mcount_bitcounter1)
);
X_FF #(
.LOC ( "SLICE_X19Y25" ),
.INIT ( 1'b0 ))
bitcounter_1 (
.I(\bitcounter<2>/DYMUX_2213 ),
.CE(\bitcounter<2>/CEINV_2202 ),
.CLK(\bitcounter<2>/CLKINV_2203 ),
.SET(GND),
.RST(\bitcounter<2>/SRINV_2204 ),
.O(bitcounter[1])
);
X_LUT4 #(
.INIT ( 16'h5AAA ),
.LOC ( "SLICE_X19Y25" ))
\Mcount_bitcounter_xor<2>11 (
.ADR0(bitcounter[2]),
.ADR1(VCC),
.ADR2(bitcounter[0]),
.ADR3(bitcounter[1]),
.O(Mcount_bitcounter2)
);
X_FF #(
.LOC ( "SLICE_X19Y25" ),
.INIT ( 1'b0 ))
bitcounter_2 (
.I(\bitcounter<2>/DXMUX_2229 ),
.CE(\bitcounter<2>/CEINV_2202 ),
.CLK(\bitcounter<2>/CLKINV_2203 ),
.SET(GND),
.RST(\bitcounter<2>/SRINV_2204 ),
.O(bitcounter[2])
);
X_LUT4 #(
.INIT ( 16'hAE0A ),
.LOC ( "SLICE_X15Y24" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_or00001 (
.ADR0(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_987 ),
.ADR1(ld_shift),
.ADR2(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_979 ),
.ADR3(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_980 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_or0000 )
);
X_FF #(
.LOC ( "SLICE_X15Y24" ),
.INIT ( 1'b1 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/DYMUX_2259 ),
.CE(VCC),
.CLK(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/CLKINV_2250 ),
.SET(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/FFY/SET ),
.RST(GND),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_987 )
);
X_BUF #(
.LOC ( "SLICE_X15Y24" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/FFY/SETOR (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg[2] ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/FFY/SET )
);
X_LUT4 #(
.INIT ( 16'h10F0 ),
.LOC ( "SLICE_X15Y24" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/RAM_REGOUT_EN1 (
.ADR0(pstate_FSM_FFd2_1_981),
.ADR1(empty),
.ADR2(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_979 ),
.ADR3(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_980 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en )
);
X_LUT4 #(
.INIT ( 16'h66AA ),
.LOC ( "SLICE_X17Y31" ))
\Mcount_bittimer_xor<2>11 (
.ADR0(bittimer[2]),
.ADR1(bittimer[1]),
.ADR2(VCC),
.ADR3(bittimer[0]),
.O(Result[2])
);
X_FF #(
.LOC ( "SLICE_X17Y31" ),
.INIT ( 1'b0 ))
bittimer_2 (
.I(\bittimer<3>/DYMUX_2295 ),
.CE(\bittimer<3>/CEINV_2284 ),
.CLK(\bittimer<3>/CLKINV_2285 ),
.SET(GND),
.RST(\bittimer<3>/SRINV_2286 ),
.O(bittimer[2])
);
X_LUT4 #(
.INIT ( 16'h78F0 ),
.LOC ( "SLICE_X17Y31" ))
\Mcount_bittimer_xor<3>11 (
.ADR0(bittimer[2]),
.ADR1(bittimer[1]),
.ADR2(bittimer[3]),
.ADR3(bittimer[0]),
.O(Result[3])
);
X_FF #(
.LOC ( "SLICE_X17Y31" ),
.INIT ( 1'b0 ))
bittimer_3 (
.I(\bittimer<3>/DXMUX_2310 ),
.CE(\bittimer<3>/CEINV_2284 ),
.CLK(\bittimer<3>/CLKINV_2285 ),
.SET(GND),
.RST(\bittimer<3>/SRINV_2286 ),
.O(bittimer[3])
);
X_LUT4 #(
.INIT ( 16'hEE00 ),
.LOC ( "SLICE_X17Y27" ))
\shift_out_mux0000<0>1 (
.ADR0(empty),
.ADR1(pstate_FSM_FFd2_907),
.ADR2(VCC),
.ADR3(shift_out[1]),
.O(shift_out_mux0000[0])
);
X_FF #(
.LOC ( "SLICE_X17Y27" ),
.INIT ( 1'b1 ))
shift_out_0 (
.I(\shift_out<1>/DYMUX_2341 ),
.CE(\shift_out<1>/CEINV_2330 ),
.CLK(\shift_out<1>/CLKINV_2331 ),
.SET(\shift_out<1>/SRINV_2332 ),
.RST(GND),
.O(shift_out[0])
);
X_LUT4 #(
.INIT ( 16'hF0E2 ),
.LOC ( "SLICE_X17Y27" ))
\shift_out_mux0000<1>1 (
.ADR0(to_shift[0]),
.ADR1(empty),
.ADR2(shift_out[2]),
.ADR3(pstate_FSM_FFd2_907),
.O(shift_out_mux0000[1])
);
X_FF #(
.LOC ( "SLICE_X17Y27" ),
.INIT ( 1'b1 ))
shift_out_1 (
.I(\shift_out<1>/DXMUX_2355 ),
.CE(\shift_out<1>/CEINV_2330 ),
.CLK(\shift_out<1>/CLKINV_2331 ),
.SET(\shift_out<1>/SRINV_2332 ),
.RST(GND),
.O(shift_out[1])
);
X_LUT4 #(
.INIT ( 16'hAAAC ),
.LOC ( "SLICE_X14Y27" ))
\shift_out_mux0000<2>1 (
.ADR0(shift_out[3]),
.ADR1(to_shift[1]),
.ADR2(empty),
.ADR3(pstate_FSM_FFd2_907),
.O(shift_out_mux0000[2])
);
X_FF #(
.LOC ( "SLICE_X14Y27" ),
.INIT ( 1'b1 ))
shift_out_2 (
.I(\shift_out<3>/DYMUX_2385 ),
.CE(\shift_out<3>/CEINV_2375 ),
.CLK(\shift_out<3>/CLKINV_2376 ),
.SET(\shift_out<3>/SRINV_2377 ),
.RST(GND),
.O(shift_out[2])
);
X_LUT4 #(
.INIT ( 16'hAAAC ),
.LOC ( "SLICE_X14Y27" ))
\shift_out_mux0000<3>1 (
.ADR0(shift_out[4]),
.ADR1(to_shift[2]),
.ADR2(empty),
.ADR3(pstate_FSM_FFd2_907),
.O(shift_out_mux0000[3])
);
X_FF #(
.LOC ( "SLICE_X14Y27" ),
.INIT ( 1'b1 ))
shift_out_3 (
.I(\shift_out<3>/DXMUX_2399 ),
.CE(\shift_out<3>/CEINV_2375 ),
.CLK(\shift_out<3>/CLKINV_2376 ),
.SET(\shift_out<3>/SRINV_2377 ),
.RST(GND),
.O(shift_out[3])
);
X_LUT4 #(
.INIT ( 16'hA000 ),
.LOC ( "SLICE_X30Y14" ))
\dout<3>1 (
.ADR0(rden_IBUF_859),
.ADR1(VCC),
.ADR2(N3),
.ADR3(\baud1/period [3]),
.O(dout_3_OBUF_2419)
);
X_LUT4 #(
.INIT ( 16'h8080 ),
.LOC ( "SLICE_X30Y14" ))
\dout<2>1 (
.ADR0(\baud1/period [2]),
.ADR1(rden_IBUF_859),
.ADR2(N3),
.ADR3(VCC),
.O(dout_2_OBUF_2427)
);
X_LUT4 #(
.INIT ( 16'hA000 ),
.LOC ( "SLICE_X31Y15" ))
\dout<4>1 (
.ADR0(N3),
.ADR1(VCC),
.ADR2(\baud1/period [4]),
.ADR3(rden_IBUF_859),
.O(dout_4_OBUF_2443)
);
X_LUT4 #(
.INIT ( 16'h8800 ),
.LOC ( "SLICE_X31Y15" ))
\dout<5>1 (
.ADR0(N3),
.ADR1(\baud1/period [5]),
.ADR2(VCC),
.ADR3(rden_IBUF_859),
.O(dout_5_OBUF_2451)
);
X_FF #(
.MSGON ( "TRUE" ),
.LOC ( "SLICE_X14Y30" ),
.XON ( "FALSE" ),
.INIT ( 1'b1 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg/DYMUX_2463 ),
.CE(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg/CEINV_2459 ),
.CLK(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg/CLKINV_2460 ),
.SET(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg/FFY/SET ),
.RST(GND),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_1005 )
);
X_BUF #(
.LOC ( "SLICE_X14Y30" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg/FFY/SETOR (
.I(reset_IBUF_872),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg/FFY/SET )
);
X_FF #(
.LOC ( "SLICE_X26Y23" ),
.INIT ( 1'b0 ))
\baud1/period_0 (
.I(\baud1/period<1>/DYMUX_2481 ),
.CE(\baud1/period<1>/CEINV_2477 ),
.CLK(\baud1/period<1>/CLKINV_2478 ),
.SET(GND),
.RST(\baud1/period<1>/SRINV_2479 ),
.O(\baud1/period [0])
);
X_FF #(
.LOC ( "SLICE_X26Y23" ),
.INIT ( 1'b1 ))
\baud1/period_1 (
.I(\baud1/period<1>/DXMUX_2490 ),
.CE(\baud1/period<1>/CEINV_2477 ),
.CLK(\baud1/period<1>/CLKINV_2478 ),
.SET(\baud1/period<1>/SRINV_2479 ),
.RST(GND),
.O(\baud1/period [1])
);
X_FF #(
.LOC ( "SLICE_X30Y22" ),
.INIT ( 1'b0 ))
\baud1/period_2 (
.I(\baud1/period<3>/DYMUX_2508 ),
.CE(\baud1/period<3>/CEINV_2504 ),
.CLK(\baud1/period<3>/CLKINV_2505 ),
.SET(GND),
.RST(\baud1/period<3>/SRINV_2506 ),
.O(\baud1/period [2])
);
X_FF #(
.LOC ( "SLICE_X30Y22" ),
.INIT ( 1'b1 ))
\baud1/period_3 (
.I(\baud1/period<3>/DXMUX_2517 ),
.CE(\baud1/period<3>/CEINV_2504 ),
.CLK(\baud1/period<3>/CLKINV_2505 ),
.SET(\baud1/period<3>/SRINV_2506 ),
.RST(GND),
.O(\baud1/period [3])
);
X_LUT4 #(
.INIT ( 16'hA000 ),
.LOC ( "SLICE_X28Y24" ))
\dout<6>1 (
.ADR0(N3),
.ADR1(VCC),
.ADR2(\baud1/period [6]),
.ADR3(rden_IBUF_859),
.O(dout_6_OBUF_2538)
);
X_LUT4 #(
.INIT ( 16'h8241 ),
.LOC ( "SLICE_X28Y24" ))
\baud1/baud_cmp_eq00008120 (
.ADR0(\baud1/period [7]),
.ADR1(\baud1/timer [6]),
.ADR2(\baud1/period [6]),
.ADR3(\baud1/timer [7]),
.O(\baud1/baud_cmp_eq00008120_2545 )
);
X_FF #(
.LOC ( "SLICE_X31Y23" ),
.INIT ( 1'b1 ))
\baud1/period_4 (
.I(\baud1/period<5>/DYMUX_2559 ),
.CE(\baud1/period<5>/CEINV_2555 ),
.CLK(\baud1/period<5>/CLKINV_2556 ),
.SET(\baud1/period<5>/SRINV_2557 ),
.RST(GND),
.O(\baud1/period [4])
);
X_FF #(
.LOC ( "SLICE_X31Y23" ),
.INIT ( 1'b0 ))
\baud1/period_5 (
.I(\baud1/period<5>/DXMUX_2567 ),
.CE(\baud1/period<5>/CEINV_2555 ),
.CLK(\baud1/period<5>/CLKINV_2556 ),
.SET(GND),
.RST(\baud1/period<5>/SRINV_2557 ),
.O(\baud1/period [5])
);
X_LUT4 #(
.INIT ( 16'hFBFF ),
.LOC ( "SLICE_X16Y25" ))
\Mcount_bitcounter_xor<1>111 (
.ADR0(bitcounter[2]),
.ADR1(pstate_FSM_FFd2_907),
.ADR2(pstate_FSM_FFd1_910),
.ADR3(bitcounter[3]),
.O(N2_pack_2)
);
X_LUT4 #(
.INIT ( 16'h5055 ),
.LOC ( "SLICE_X16Y25" ))
\Mcount_bitcounter_xor<0>11 (
.ADR0(bitcounter[0]),
.ADR1(VCC),
.ADR2(N2),
.ADR3(bitcounter[1]),
.O(Mcount_bitcounter)
);
X_FF #(
.LOC ( "SLICE_X16Y25" ),
.INIT ( 1'b0 ))
bitcounter_0 (
.I(\bitcounter<0>/DXMUX_2605 ),
.CE(\bitcounter<0>/CEINV_2587 ),
.CLK(\bitcounter<0>/CLKINV_2588 ),
.SET(GND),
.RST(\bitcounter<0>/FFX/RSTAND_2611 ),
.O(bitcounter[0])
);
X_BUF #(
.LOC ( "SLICE_X16Y25" ))
\bitcounter<0>/FFX/RSTAND (
.I(reset_IBUF_872),
.O(\bitcounter<0>/FFX/RSTAND_2611 )
);
X_FF #(
.LOC ( "SLICE_X29Y23" ),
.INIT ( 1'b0 ))
\baud1/period_6 (
.I(\baud1/period<7>/DYMUX_2624 ),
.CE(\baud1/period<7>/CEINV_2620 ),
.CLK(\baud1/period<7>/CLKINV_2621 ),
.SET(GND),
.RST(\baud1/period<7>/SRINV_2622 ),
.O(\baud1/period [6])
);
X_FF #(
.LOC ( "SLICE_X29Y23" ),
.INIT ( 1'b0 ))
\baud1/period_7 (
.I(\baud1/period<7>/DXMUX_2633 ),
.CE(\baud1/period<7>/CEINV_2620 ),
.CLK(\baud1/period<7>/CLKINV_2621 ),
.SET(GND),
.RST(\baud1/period<7>/SRINV_2622 ),
.O(\baud1/period [7])
);
X_FF #(
.LOC ( "SLICE_X20Y26" ),
.INIT ( 1'b0 ))
\baud1/baud (
.I(\baud1/baud/DYMUX_2650 ),
.CE(\baud1/baud/CEINV_2646 ),
.CLK(\baud1/baud/CLKINV_2647 ),
.SET(GND),
.RST(\baud1/baud/FFY/RSTAND_2656 ),
.O(\baud1/baud_911 )
);
X_BUF #(
.LOC ( "SLICE_X20Y26" ))
\baud1/baud/FFY/RSTAND (
.I(reset_IBUF_872),
.O(\baud1/baud/FFY/RSTAND_2656 )
);
X_FF #(
.MSGON ( "TRUE" ),
.LOC ( "SLICE_X12Y30" ),
.XON ( "FALSE" ),
.INIT ( 1'b0 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1 (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2/DYMUX_2665 ),
.CE(VCC),
.CLK(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2/CLKINV_2663 ),
.SET(GND),
.RST(GND),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_1004 )
);
X_FF #(
.MSGON ( "TRUE" ),
.LOC ( "SLICE_X12Y30" ),
.XON ( "FALSE" ),
.INIT ( 1'b0 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2 (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2/DXMUX_2670 ),
.CE(VCC),
.CLK(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2/CLKINV_2663 ),
.SET(GND),
.RST(GND),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_1008 )
);
X_LUT4 #(
.INIT ( 16'h000F ),
.LOC ( "SLICE_X15Y26" ))
shift_out_not000111 (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(pstate_FSM_FFd2_1_981),
.ADR3(empty),
.O(ld_shift_pack_1)
);
X_LUT4 #(
.INIT ( 16'h00F7 ),
.LOC ( "SLICE_X15Y26" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/RAM_RD_EN_FWFT1 (
.ADR0(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_979 ),
.ADR1(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_980 ),
.ADR2(ld_shift),
.ADR3(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_951 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en )
);
X_LUT4 #(
.INIT ( 16'h0011 ),
.LOC ( "SLICE_X31Y18" ))
\dout<0>11 (
.ADR0(addr_0_IBUF_873),
.ADR1(addr_1_IBUF_875),
.ADR2(VCC),
.ADR3(addr_2_IBUF_853),
.O(N3_pack_1)
);
X_LUT4 #(
.INIT ( 16'hA000 ),
.LOC ( "SLICE_X31Y18" ))
\dout<7>1 (
.ADR0(rden_IBUF_859),
.ADR1(VCC),
.ADR2(N3),
.ADR3(\baud1/period [7]),
.O(dout_7_OBUF_2719)
);
X_LUT4 #(
.INIT ( 16'h00CC ),
.LOC ( "SLICE_X13Y30" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb1 (
.ADR0(VCC),
.ADR1(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_1005 ),
.ADR2(VCC),
.ADR3(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_1008 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb )
);
X_LUT4 #(
.INIT ( 16'h6666 ),
.LOC ( "SLICE_X15Y22" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<1>11 (
.ADR0(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [0]),
.ADR1(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [1]),
.ADR2(VCC),
.ADR3(VCC),
.O(\fifo1/Result<1>1 )
);
X_LUT4 #(
.INIT ( 16'h0FF0 ),
.LOC ( "SLICE_X13Y23" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<1>11 (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1]),
.ADR3(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0]),
.O(\fifo1/Result [1])
);
X_FF #(
.LOC ( "SLICE_X15Y22" ),
.INIT ( 1'b0 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_1 (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<0>/DYMUX_2759 ),
.CE(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<0>/CEINV_2747 ),
.CLK(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<0>/CLKINV_2748 ),
.SET(GND),
.RST(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<0>/SRINV_2749 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [1])
);
X_LUT4 #(
.INIT ( 16'h0084 ),
.LOC ( "SLICE_X15Y22" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb40 (
.ADR0(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0]),
.ADR1(wr_fifo),
.ADR2(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [0]),
.ADR3(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_937 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb40_2772 )
);
X_FF #(
.LOC ( "SLICE_X15Y22" ),
.INIT ( 1'b1 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_0 (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<0>/DXMUX_2775 ),
.CE(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<0>/CEINV_2747 ),
.CLK(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<0>/CLKINV_2748 ),
.SET(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<0>/SRINV_2749 ),
.RST(GND),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [0])
);
X_LUT4 #(
.INIT ( 16'h0008 ),
.LOC ( "SLICE_X14Y20" ))
wr_fifo1 (
.ADR0(addr_0_IBUF_873),
.ADR1(wren_IBUF_855),
.ADR2(addr_2_IBUF_853),
.ADR3(addr_1_IBUF_875),
.O(wr_fifo_pack_1)
);
X_FF #(
.LOC ( "SLICE_X13Y23" ),
.INIT ( 1'b0 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_1 (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/DYMUX_2805 ),
.CE(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/CEINV_2793 ),
.CLK(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/CLKINV_2794 ),
.SET(GND),
.RST(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/SRINV_2795 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1])
);
X_LUT4 #(
.INIT ( 16'hF00F ),
.LOC ( "SLICE_X13Y23" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or000014 (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0]),
.ADR3(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0]),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or000014_2820 )
);
X_FF #(
.LOC ( "SLICE_X13Y23" ),
.INIT ( 1'b1 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_0 (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/DXMUX_2823 ),
.CE(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/CEINV_2793 ),
.CLK(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/CLKINV_2794 ),
.SET(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/SRINV_2795 ),
.RST(GND),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0])
);
X_LUT4 #(
.INIT ( 16'hA521 ),
.LOC ( "SLICE_X14Y20" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or000079_SW0 (
.ADR0(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1]),
.ADR1(wr_fifo),
.ADR2(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1]),
.ADR3(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_937 ),
.O(\fifo1/N01 )
);
X_LUT4 #(
.INIT ( 16'h55AA ),
.LOC ( "SLICE_X12Y24" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or00003168_SW1 (
.ADR0(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2]),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2]),
.O(\fifo1/N6 )
);
X_LUT4 #(
.INIT ( 16'h8421 ),
.LOC ( "SLICE_X12Y24" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb67 (
.ADR0(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2]),
.ADR1(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [3]),
.ADR2(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [2]),
.ADR3(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3]),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb67_2875 )
);
X_FF #(
.MSGON ( "TRUE" ),
.LOC ( "SLICE_X14Y24" ),
.XON ( "FALSE" ),
.INIT ( 1'b1 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg/DYMUX_2887 ),
.CE(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg/CEINV_2883 ),
.CLK(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg/CLKINV_2884 ),
.SET(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg/FFY/SET ),
.RST(GND),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_1012 )
);
X_BUF #(
.LOC ( "SLICE_X14Y24" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg/FFY/SETOR (
.I(reset_IBUF_872),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg/FFY/SET )
);
X_SFF #(
.LOC ( "SLICE_X14Y26" ),
.INIT ( 1'b0 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0 (
.I(\to_shift<1>/DYMUX_2905 ),
.CE(\to_shift<1>/CEINV_2901 ),
.CLK(\to_shift<1>/CLKINV_2902 ),
.SET(GND),
.RST(GND),
.SSET(GND),
.SRST(\to_shift<1>/SRINV_2903 ),
.O(to_shift[0])
);
X_SFF #(
.LOC ( "SLICE_X14Y26" ),
.INIT ( 1'b0 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_1 (
.I(\to_shift<1>/DXMUX_2912 ),
.CE(\to_shift<1>/CEINV_2901 ),
.CLK(\to_shift<1>/CLKINV_2902 ),
.SET(GND),
.RST(GND),
.SSET(GND),
.SRST(\to_shift<1>/SRINV_2903 ),
.O(to_shift[1])
);
X_LUT4 #(
.INIT ( 16'hCCFC ),
.LOC ( "SLICE_X13Y29" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en1 (
.ADR0(VCC),
.ADR1(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg[0] ),
.ADR2(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en_0 ),
.ADR3(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_951 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en )
);
X_SFF #(
.LOC ( "SLICE_X15Y27" ),
.INIT ( 1'b0 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_2 (
.I(\to_shift<3>/DYMUX_2941 ),
.CE(\to_shift<3>/CEINV_2937 ),
.CLK(\to_shift<3>/CLKINV_2938 ),
.SET(GND),
.RST(GND),
.SSET(GND),
.SRST(\to_shift<3>/SRINV_2939 ),
.O(to_shift[2])
);
X_SFF #(
.LOC ( "SLICE_X15Y27" ),
.INIT ( 1'b0 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_3 (
.I(\to_shift<3>/DXMUX_2948 ),
.CE(\to_shift<3>/CEINV_2937 ),
.CLK(\to_shift<3>/CLKINV_2938 ),
.SET(GND),
.RST(GND),
.SSET(GND),
.SRST(\to_shift<3>/SRINV_2939 ),
.O(to_shift[3])
);
X_SFF #(
.LOC ( "SLICE_X13Y26" ),
.INIT ( 1'b0 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_4 (
.I(\to_shift<5>/DYMUX_2965 ),
.CE(\to_shift<5>/CEINV_2961 ),
.CLK(\to_shift<5>/CLKINV_2962 ),
.SET(GND),
.RST(GND),
.SSET(GND),
.SRST(\to_shift<5>/SRINV_2963 ),
.O(to_shift[4])
);
X_SFF #(
.LOC ( "SLICE_X13Y26" ),
.INIT ( 1'b0 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_5 (
.I(\to_shift<5>/DXMUX_2972 ),
.CE(\to_shift<5>/CEINV_2961 ),
.CLK(\to_shift<5>/CLKINV_2962 ),
.SET(GND),
.RST(GND),
.SSET(GND),
.SRST(\to_shift<5>/SRINV_2963 ),
.O(to_shift[5])
);
X_SFF #(
.LOC ( "SLICE_X12Y27" ),
.INIT ( 1'b0 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_6 (
.I(\to_shift<7>/DYMUX_2989 ),
.CE(\to_shift<7>/CEINV_2985 ),
.CLK(\to_shift<7>/CLKINV_2986 ),
.SET(GND),
.RST(GND),
.SSET(GND),
.SRST(\to_shift<7>/SRINV_2987 ),
.O(to_shift[6])
);
X_SFF #(
.LOC ( "SLICE_X12Y27" ),
.INIT ( 1'b0 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_7 (
.I(\to_shift<7>/DXMUX_2996 ),
.CE(\to_shift<7>/CEINV_2985 ),
.CLK(\to_shift<7>/CLKINV_2986 ),
.SET(GND),
.RST(GND),
.SSET(GND),
.SRST(\to_shift<7>/SRINV_2987 ),
.O(to_shift[7])
);
X_LUT4 #(
.INIT ( 16'h8421 ),
.LOC ( "SLICE_X27Y22" ))
\baud1/baud_cmp_eq0000853 (
.ADR0(\baud1/period [2]),
.ADR1(\baud1/timer [3]),
.ADR2(\baud1/timer [2]),
.ADR3(\baud1/period [3]),
.O(\baud1/baud_cmp_eq0000853_3016 )
);
X_LUT4 #(
.INIT ( 16'h9333 ),
.LOC ( "SLICE_X27Y22" ))
\baud1/timer_mux0000<0>11_SW0 (
.ADR0(\baud1/timer [1]),
.ADR1(\baud1/timer [3]),
.ADR2(\baud1/timer [2]),
.ADR3(\baud1/timer [0]),
.O(N34)
);
X_LUT4 #(
.INIT ( 16'h5500 ),
.LOC ( "SLICE_X14Y21" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb5 (
.ADR0(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_1013 ),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_937 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_comb5_3038 )
);
X_LUT4 #(
.INIT ( 16'h00CC ),
.LOC ( "SLICE_X14Y21" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/ram_wr_en_i1 (
.ADR0(VCC),
.ADR1(wr_fifo),
.ADR2(VCC),
.ADR3(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_937 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en )
);
X_FF #(
.LOC ( "SLICE_X13Y22" ),
.INIT ( 1'b0 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_0 (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<1>/DYMUX_3061 ),
.CE(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<1>/CEINV_3057 ),
.CLK(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<1>/CLKINV_3058 ),
.SET(GND),
.RST(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<1>/SRINV_3059 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0])
);
X_FF #(
.LOC ( "SLICE_X13Y22" ),
.INIT ( 1'b0 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_1 (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<1>/DXMUX_3070 ),
.CE(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<1>/CEINV_3057 ),
.CLK(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<1>/CLKINV_3058 ),
.SET(GND),
.RST(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<1>/SRINV_3059 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1])
);
X_FF #(
.LOC ( "SLICE_X13Y24" ),
.INIT ( 1'b0 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_2 (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/DYMUX_3190 ),
.CE(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/CEINV_3186 ),
.CLK(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/CLKINV_3187 ),
.SET(GND),
.RST(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/SRINV_3188 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2])
);
X_FF #(
.MSGON ( "TRUE" ),
.LOC ( "SLICE_X17Y23" ),
.XON ( "FALSE" ),
.INIT ( 1'b1 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rst_d1 (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rst_d2/DYMUX_3216 ),
.CE(VCC),
.CLK(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rst_d2/CLKINV_3213 ),
.SET(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rst_d2/SRINV_3214 ),
.RST(GND),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rst_d1_1015 )
);
X_FF #(
.MSGON ( "TRUE" ),
.LOC ( "SLICE_X17Y23" ),
.XON ( "FALSE" ),
.INIT ( 1'b1 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rst_d2 (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rst_d2/DXMUX_3223 ),
.CE(VCC),
.CLK(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rst_d2/CLKINV_3213 ),
.SET(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rst_d2/SRINV_3214 ),
.RST(GND),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rst_d2_928 )
);
X_FF #(
.LOC ( "SLICE_X26Y21" ),
.INIT ( 1'b1 ))
control_0 (
.I(\control<0>/DYMUX_3236 ),
.CE(VCC),
.CLK(\control<0>/CLKINV_3233 ),
.SET(\control<0>/FFY/SET ),
.RST(GND),
.O(control[0])
);
X_BUF #(
.LOC ( "SLICE_X26Y21" ))
\control<0>/FFY/SETOR (
.I(reset_IBUF_872),
.O(\control<0>/FFY/SET )
);
X_FF #(
.LOC ( "SLICE_X12Y28" ),
.INIT ( 1'b1 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg_0 (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg<2>/DYMUX_3251 ),
.CE(VCC),
.CLK(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg<2>/CLKINV_3248 ),
.SET(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg<2>/SRINV_3249 ),
.RST(GND),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg[0] )
);
X_FF #(
.LOC ( "SLICE_X12Y28" ),
.INIT ( 1'b1 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg_2 (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg<2>/DXMUX_3258 ),
.CE(VCC),
.CLK(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg<2>/CLKINV_3248 ),
.SET(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg<2>/SRINV_3249 ),
.RST(GND),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg[2] )
);
X_FF #(
.MSGON ( "TRUE" ),
.LOC ( "SLICE_X17Y22" ),
.XON ( "FALSE" ),
.INIT ( 1'b1 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rst_d3 (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rst_d3/DYMUX_3271 ),
.CE(VCC),
.CLK(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rst_d3/CLKINV_3268 ),
.SET(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rst_d3/FFY/SET ),
.RST(GND),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rst_d3_1017 )
);
X_BUF #(
.LOC ( "SLICE_X17Y22" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rst_d3/FFY/SETOR (
.I(reset_IBUF_872),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rst_d3/FFY/SET )
);
X_LUT4 #(
.INIT ( 16'h8421 ),
.LOC ( "SLICE_X27Y24" ))
\baud1/baud_cmp_eq0000893 (
.ADR0(\baud1/timer [5]),
.ADR1(\baud1/period [4]),
.ADR2(\baud1/period [5]),
.ADR3(\baud1/timer [4]),
.O(\baud1/baud_cmp_eq0000893_3286 )
);
X_LUT4 #(
.INIT ( 16'h00AA ),
.LOC ( "SLICE_X15Y29" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb1 (
.ADR0(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_1012 ),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_1018 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb )
);
X_LUT4 #(
.INIT ( 16'h9933 ),
.LOC ( "SLICE_X26Y22" ))
\baud1/timer_mux0000<0>11_SW4 (
.ADR0(\baud1/timer [0]),
.ADR1(\baud1/timer [2]),
.ADR2(VCC),
.ADR3(\baud1/timer [1]),
.O(N42)
);
X_FF #(
.LOC ( "SLICE_X16Y22" ),
.INIT ( 1'b0 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN/DYMUX_3320 ),
.CE(VCC),
.CLK(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN/CLKINV_3317 ),
.SET(GND),
.RST(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN/FFY/RSTAND_3325 ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN_1013 )
);
X_BUF #(
.LOC ( "SLICE_X16Y22" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN/FFY/RSTAND (
.I(reset_IBUF_872),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN/FFY/RSTAND_3325 )
);
X_FF #(
.MSGON ( "TRUE" ),
.LOC ( "SLICE_X14Y29" ),
.XON ( "FALSE" ),
.INIT ( 1'b0 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1 (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2/DYMUX_3334 ),
.CE(VCC),
.CLK(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2/CLKINV_3332 ),
.SET(GND),
.RST(GND),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1_1011 )
);
X_FF #(
.MSGON ( "TRUE" ),
.LOC ( "SLICE_X14Y29" ),
.XON ( "FALSE" ),
.INIT ( 1'b0 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2 (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2/DXMUX_3339 ),
.CE(VCC),
.CLK(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2/CLKINV_3332 ),
.SET(GND),
.RST(GND),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2_1018 )
);
X_LUT4 #(
.INIT ( 16'h9009 ),
.LOC ( "SLICE_X12Y26" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or000062 (
.ADR0(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [3]),
.ADR1(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3]),
.ADR2(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2]),
.ADR3(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [2]),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or000062_3352 )
);
X_LUT4 #(
.INIT ( 16'h33CC ),
.LOC ( "SLICE_X17Y29" ))
\Mcount_bittimer_xor<1>11 (
.ADR0(VCC),
.ADR1(bittimer[1]),
.ADR2(VCC),
.ADR3(bittimer[0]),
.O(Result[1])
);
X_FF #(
.LOC ( "SLICE_X17Y29" ),
.INIT ( 1'b0 ))
bittimer_1 (
.I(\bittimer<0>/DYMUX_3379 ),
.CE(\bittimer<0>/CEINV_3367 ),
.CLK(\bittimer<0>/CLKINV_3368 ),
.SET(GND),
.RST(\bittimer<0>/SRINV_3369 ),
.O(bittimer[1])
);
X_LUT4 #(
.INIT ( 16'hFEFE ),
.LOC ( "SLICE_X17Y29" ))
bitcounter_not00012_SW0 (
.ADR0(bittimer[1]),
.ADR1(bittimer[0]),
.ADR2(bittimer[3]),
.ADR3(VCC),
.O(N27)
);
X_FF #(
.LOC ( "SLICE_X17Y29" ),
.INIT ( 1'b0 ))
bittimer_0 (
.I(\bittimer<0>/DXMUX_3396 ),
.CE(\bittimer<0>/CEINV_3367 ),
.CLK(\bittimer<0>/CLKINV_3368 ),
.SET(GND),
.RST(\bittimer<0>/SRINV_3369 ),
.O(bittimer[0])
);
X_FF #(
.LOC ( "SLICE_X14Y22" ),
.INIT ( 1'b1 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i (
.I(\full/DYMUX_3411 ),
.CE(VCC),
.CLK(\full/CLKINV_3408 ),
.SET(\full/FFY/SET ),
.RST(GND),
.O(full)
);
X_BUF #(
.LOC ( "SLICE_X14Y22" ))
\full/FFY/SETOR (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rst_d2_928 ),
.O(\full/FFY/SET )
);
X_FF #(
.LOC ( "SLICE_X14Y31" ),
.INIT ( 1'b1 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_reg_1 (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_reg<1>/DYMUX_3424 ),
.CE(VCC),
.CLK(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_reg<1>/CLKINV_3421 ),
.SET(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_reg<1>/FFY/SET ),
.RST(GND),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_reg [1])
);
X_BUF #(
.LOC ( "SLICE_X14Y31" ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_reg<1>/FFY/SETOR (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_comb ),
.O(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_reg<1>/FFY/SET )
);
X_LUT4 #(
.INIT ( 16'h870F ),
.LOC ( "SLICE_X19Y27" ))
\Mcount_bitcounter_xor<3>1_SW0 (
.ADR0(bitcounter[1]),
.ADR1(bitcounter[0]),
.ADR2(bitcounter[3]),
.ADR3(bitcounter[2]),
.O(N29_pack_2)
);
X_FF #(
.LOC ( "SLICE_X14Y28" ),
.INIT ( 1'b1 ))
\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i (
.I(\empty/DYMUX_3437 ),
.CE(VCC),
.CLK(\empty/CLKINV_3434 ),
.SET(\empty/FFY/SET ),
.RST(GND),
.O(empty)
);
X_BUF #(
.LOC ( "SLICE_X14Y28" ))
\empty/FFY/SETOR (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg[2] ),
.O(\empty/FFY/SET )
);
X_LUT4 #(
.INIT ( 16'h04F7 ),
.LOC ( "SLICE_X19Y27" ))
\Mcount_bitcounter_xor<3>1 (
.ADR0(N30_0),
.ADR1(pstate_FSM_FFd2_907),
.ADR2(pstate_FSM_FFd1_910),
.ADR3(N29),
.O(Mcount_bitcounter3)
);
X_FF #(
.LOC ( "SLICE_X19Y27" ),
.INIT ( 1'b0 ))
bitcounter_3 (
.I(\bitcounter<3>/DXMUX_3473 ),
.CE(\bitcounter<3>/CEINV_3456 ),
.CLK(\bitcounter<3>/CLKINV_3457 ),
.SET(GND),
.RST(\bitcounter<3>/FFX/RSTAND_3479 ),
.O(bitcounter[3])
);
X_BUF #(
.LOC ( "SLICE_X19Y27" ))
\bitcounter<3>/FFX/RSTAND (
.I(reset_IBUF_872),
.O(\bitcounter<3>/FFX/RSTAND_3479 )
);
X_LUT4 #(
.INIT ( 16'h9733 ),
.LOC ( "SLICE_X18Y27" ))
\Mcount_bitcounter_xor<3>1_SW1 (
.ADR0(bitcounter[2]),
.ADR1(bitcounter[3]),
.ADR2(bitcounter[0]),
.ADR3(bitcounter[1]),
.O(N30)
);
X_LUT4 #(
.INIT ( 16'h0080 ),
.LOC ( "SLICE_X29Y20" ))
control_1_not00017 (
.ADR0(addr_1_IBUF_875),
.ADR1(addr_0_IBUF_873),
.ADR2(wren_IBUF_855),
.ADR3(addr_2_IBUF_853),
.O(control_1_not00017_3502)
);
X_BUF #(
.LOC ( "PAD45" ))
\dout<0>/OUTPUT/OFF/OMUX (
.I(\dout_0_OBUF/F5MUX_1407 ),
.O(\dout<0>/O )
);
X_BUF #(
.LOC ( "PAD51" ))
\dout<1>/OUTPUT/OFF/OMUX (
.I(\dout_1_OBUF/F5MUX_1382 ),
.O(\dout<1>/O )
);
X_BUF #(
.LOC ( "PAD52" ))
\dout<2>/OUTPUT/OFF/OMUX (
.I(dout_2_OBUF_2427),
.O(\dout<2>/O )
);
X_BUF #(
.LOC ( "PAD49" ))
\dout<3>/OUTPUT/OFF/OMUX (
.I(dout_3_OBUF_2419),
.O(\dout<3>/O )
);
X_BUF #(
.LOC ( "PAD44" ))
\dout<4>/OUTPUT/OFF/OMUX (
.I(dout_4_OBUF_2443),
.O(\dout<4>/O )
);
X_BUF #(
.LOC ( "PAD48" ))
\dout<5>/OUTPUT/OFF/OMUX (
.I(dout_5_OBUF_2451),
.O(\dout<5>/O )
);
X_BUF #(
.LOC ( "PAD38" ))
\dout<6>/OUTPUT/OFF/OMUX (
.I(dout_6_OBUF_2538),
.O(\dout<6>/O )
);
X_BUF #(
.LOC ( "PAD42" ))
\dout<7>/OUTPUT/OFF/OMUX (
.I(dout_7_OBUF_2719),
.O(\dout<7>/O )
);
X_BUF #(
.LOC ( "PAD37" ))
\txout/OUTPUT/OFF/OMUX (
.I(shift_out[0]),
.O(\txout/O )
);
X_BUF
\NlwBufferBlock_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRA<3> (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3]),
.O
(\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRA<3> )
);
X_BUF
\NlwBufferBlock_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRA<2> (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2]),
.O
(\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRA<2> )
);
X_BUF
\NlwBufferBlock_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRA<1> (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1]),
.O
(\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRA<1> )
);
X_BUF
\NlwBufferBlock_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRA<0> (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0]),
.O
(\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRA<0> )
);
X_BUF
\NlwBufferBlock_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<3> (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3]),
.O
(\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<3> )
);
X_BUF
\NlwBufferBlock_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<2> (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2]),
.O
(\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<2> )
);
X_BUF
\NlwBufferBlock_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<1> (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1]),
.O
(\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<1> )
);
X_BUF
\NlwBufferBlock_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<0> (
.I(\fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0]),
.O
(\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<0> )
);
X_BUF
\NlwBufferBlock_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<0> (
.I(din_0_IBUF_874),
.O
(\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<0> )
);
X_BUF
\NlwBufferBlock_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<1> (
.I(din_1_IBUF_876),
.O
(\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<1> )
);
X_BUF
\NlwBufferBlock_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<8> (
.I(din_2_IBUF_854),
.O
(\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<8> )
);
X_BUF
\NlwBufferBlock_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<9> (
.I(din_3_IBUF_856),
.O
(\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<9> )
);
X_BUF
\NlwBufferBlock_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<16> (
.I(din_4_IBUF_857),
.O
(\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<16> )
);
X_BUF
\NlwBufferBlock_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<17> (
.I(din_5_IBUF_858),
.O
(\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<17> )
);
X_BUF
\NlwBufferBlock_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<24> (
.I(din_6_IBUF_860),
.O
(\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<24> )
);
X_BUF
\NlwBufferBlock_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<25> (
.I(din_7_IBUF_861),
.O
(\NlwBufferSignal_fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<25> )
);
X_ZERO NlwBlock_uart_tx_GND (
.O(GND)
);
X_ONE NlwBlock_uart_tx_VCC (
.O(VCC)
);
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Load/Store unit ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Interface between CPU and DC. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_lsu(
// Internal i/f
addrbase, addrofs, lsu_op, lsu_datain, lsu_dataout, lsu_stall, lsu_unstall,
du_stall, except_align, except_dtlbmiss, except_dmmufault, except_dbuserr,
// External i/f to DC
dcpu_adr_o, dcpu_cycstb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o, dcpu_dat_o,
dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
//
// I/O
//
//
// Internal i/f
//
input [31:0] addrbase;
input [31:0] addrofs;
input [`OR1200_LSUOP_WIDTH-1:0] lsu_op;
input [dw-1:0] lsu_datain;
output [dw-1:0] lsu_dataout;
output lsu_stall;
output lsu_unstall;
input du_stall;
output except_align;
output except_dtlbmiss;
output except_dmmufault;
output except_dbuserr;
//
// External i/f to DC
//
output [31:0] dcpu_adr_o;
output dcpu_cycstb_o;
output dcpu_we_o;
output [3:0] dcpu_sel_o;
output [3:0] dcpu_tag_o;
output [31:0] dcpu_dat_o;
input [31:0] dcpu_dat_i;
input dcpu_ack_i;
input dcpu_rty_i;
input dcpu_err_i;
input [3:0] dcpu_tag_i;
//
// Internal wires/regs
//
reg [3:0] dcpu_sel_o;
//
// Internal I/F assignments
//
assign lsu_stall = dcpu_rty_i & dcpu_cycstb_o;
assign lsu_unstall = dcpu_ack_i;
assign except_align = ((lsu_op == `OR1200_LSUOP_SH) | (lsu_op == `OR1200_LSUOP_LHZ) | (lsu_op == `OR1200_LSUOP_LHS)) & dcpu_adr_o[0]
| ((lsu_op == `OR1200_LSUOP_SW) | (lsu_op == `OR1200_LSUOP_LWZ) | (lsu_op == `OR1200_LSUOP_LWS)) & |dcpu_adr_o[1:0];
assign except_dtlbmiss = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_TE);
assign except_dmmufault = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_PE);
assign except_dbuserr = dcpu_err_i & (dcpu_tag_i == `OR1200_DTAG_BE);
//
// External I/F assignments
//
assign dcpu_adr_o = addrbase + addrofs;
assign dcpu_cycstb_o = du_stall | lsu_unstall | except_align ? 1'b0 : |lsu_op;
assign dcpu_we_o = lsu_op[3];
assign dcpu_tag_o = dcpu_cycstb_o ? `OR1200_DTAG_ND : `OR1200_DTAG_IDLE;
always @(lsu_op or dcpu_adr_o)
casex({lsu_op, dcpu_adr_o[1:0]})
{`OR1200_LSUOP_SB, 2'b00} : dcpu_sel_o = 4'b1000;
{`OR1200_LSUOP_SB, 2'b01} : dcpu_sel_o = 4'b0100;
{`OR1200_LSUOP_SB, 2'b10} : dcpu_sel_o = 4'b0010;
{`OR1200_LSUOP_SB, 2'b11} : dcpu_sel_o = 4'b0001;
{`OR1200_LSUOP_SH, 2'b00} : dcpu_sel_o = 4'b1100;
{`OR1200_LSUOP_SH, 2'b10} : dcpu_sel_o = 4'b0011;
{`OR1200_LSUOP_SW, 2'b00} : dcpu_sel_o = 4'b1111;
{`OR1200_LSUOP_LBZ, 2'b00}, {`OR1200_LSUOP_LBS, 2'b00} : dcpu_sel_o = 4'b1000;
{`OR1200_LSUOP_LBZ, 2'b01}, {`OR1200_LSUOP_LBS, 2'b01} : dcpu_sel_o = 4'b0100;
{`OR1200_LSUOP_LBZ, 2'b10}, {`OR1200_LSUOP_LBS, 2'b10} : dcpu_sel_o = 4'b0010;
{`OR1200_LSUOP_LBZ, 2'b11}, {`OR1200_LSUOP_LBS, 2'b11} : dcpu_sel_o = 4'b0001;
{`OR1200_LSUOP_LHZ, 2'b00}, {`OR1200_LSUOP_LHS, 2'b00} : dcpu_sel_o = 4'b1100;
{`OR1200_LSUOP_LHZ, 2'b10}, {`OR1200_LSUOP_LHS, 2'b10} : dcpu_sel_o = 4'b0011;
{`OR1200_LSUOP_LWZ, 2'b00}, {`OR1200_LSUOP_LWS, 2'b00} : dcpu_sel_o = 4'b1111;
default : dcpu_sel_o = 4'b0000;
endcase
//
// Instantiation of Memory-to-regfile aligner
//
or1200_mem2reg or1200_mem2reg(
.addr(dcpu_adr_o[1:0]),
.lsu_op(lsu_op),
.memdata(dcpu_dat_i),
.regdata(lsu_dataout)
);
//
// Instantiation of Regfile-to-memory aligner
//
or1200_reg2mem or1200_reg2mem(
.addr(dcpu_adr_o[1:0]),
.lsu_op(lsu_op),
.regdata(lsu_datain),
.memdata(dcpu_dat_o)
);
endmodule
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