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/*
============================================================================
Name : displayYUV.c
Author : mpelcat & kdesnos & jheulot
Modified by : jserot (for use in the HoCL framework)
Version :
Copyright : CECILL-C
Description : Displaying YUV frames one next to another in a row
============================================================================
*/
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include "yuvDisplay.h"
//#include "clock.h"
#include <SDL.h>
#include <SDL_ttf.h>
#ifdef SYSTEMC_TARGET
#include <systemc.h>
#endif
//#define FPS_MEAN 49
int quitViewer = 0;
/**
* Structure representing one display
*/
typedef struct YuvDisplay
{
SDL_Texture* textures[NB_DISPLAY]; // One overlay per frame
SDL_Window *screen; // SDL surface where to display
SDL_Renderer *renderer;
TTF_Font *text_font;
int currentXMin; // Position for next display
int initialized; // Initialization done ?
int stampId;
int frameCnt;
} YuvDisplay;
// Initialize
static YuvDisplay display;
int exitCallBack(void* userdata, SDL_Event* event){
if (event->type == SDL_QUIT){
printf("Exit request from GUI.\n");
#ifdef SYSTEMC_TARGET
sc_stop();
#else
quitViewer = 1;
#endif
return 0;
}
return 1;
}
/**
* Initializes a display frame. Be careful, once a window size has been chosen,
* all videos must share the same window size
*
* @param id display unique identifier
* @param width width
* @param height heigth
*/
void yuvDisplayInit(int id, int width, int height)
{
if (display.initialized == 0)
{
display.currentXMin = 0;
}
if (height > DISPLAY_H)
{
fprintf(stderr, "SDL screen is not high enough for display %d.\n", id);
exit(1);
}
else if (id >= NB_DISPLAY)
{
fprintf(stderr, "The number of displays is limited to %d.\n", NB_DISPLAY);
exit(1);
}
else if (display.currentXMin + width > DISPLAY_W)
{
fprintf(stderr, "The number is not wide enough for display %d.\n", NB_DISPLAY);
exit(1);
}
#ifdef VERBOSE
printf("SDL screen height OK, width OK, number of displays OK.\n");
#endif
if (display.initialized == 0)
{
// Generating window name
char* name = "Display";
display.initialized = 1;
printf("SDL_Init_Start\n");
if (SDL_Init(SDL_INIT_VIDEO))
{
fprintf(stderr, "Could not initialize SDL - %s\n", SDL_GetError());
exit(1);
}
printf("SDL_Init_end\n");
/* Initialize SDL TTF for text display */
if (TTF_Init())
{
printf("TTF initialization failed: %s\n", TTF_GetError());
}
printf("TTF_Init\n");
/* Initialize Font for text display */
display.text_font = TTF_OpenFont(PATH_TTF, 20);
if (!display.text_font)
{
printf("TTF_OpenFont: %s\n", TTF_GetError());
}
display.screen = SDL_CreateWindow(name, SDL_WINDOWPOS_UNDEFINED, SDL_WINDOWPOS_UNDEFINED,
DISPLAY_W, DISPLAY_H, SDL_WINDOW_SHOWN);
if (!display.screen)
{
fprintf(stderr, "SDL: could not set video mode - exiting\n");
exit(1);
}
display.renderer = SDL_CreateRenderer(display.screen, -1, SDL_RENDERER_ACCELERATED);
if (!display.renderer)
{
fprintf(stderr, "SDL: could not create renderer - exiting\n");
exit(1);
}
}
if (display.textures[id] == NULL)
{
display.textures[id] = SDL_CreateTexture(display.renderer,
SDL_PIXELFORMAT_IYUV,
SDL_TEXTUREACCESS_STREAMING,
width, height);
if (!display.textures[id])
{
fprintf(stderr, "SDL: could not create texture - exiting\n");
exit(1);
}
display.currentXMin += width;
}
display.stampId = 0;
display.frameCnt = 0;
/* for (int i = 0; i<FPS_MEAN; i++){ */
/* startTiming(i + 1); */
/* } */
SDL_SetEventFilter(exitCallBack, NULL);
printf("yuvDisplayInit done\n");
}
void yuvDisplay(int id, int width, int height, unsigned char *y, unsigned char *u, unsigned char *v){
yuvDisplayWithNbSlice(id, -1, y, u, v);
display.frameCnt++;
}
void yuvDisplayWithNbSlice(int id, int nbSlice, unsigned char *y, unsigned char *u, unsigned char *v)
{
SDL_Texture* texture = display.textures[id];
int w, h;
// Retrieve texture attribute
SDL_QueryTexture(texture, NULL, NULL, &w, &h);
SDL_UpdateYUVTexture(
texture, NULL,
y, w,
u, w / 2,
v, w / 2
);
SDL_Rect screen_rect;
screen_rect.w = w;
screen_rect.h = h;
screen_rect.x = w*id;
screen_rect.y = 0;
SDL_RenderCopy(display.renderer, texture, NULL, &screen_rect);
SDL_Color colorWhite = { 255, 255, 255, 255 };
/* /\* Draw FPS text *\/ */
/* char fps_text[20]; */
/* int time = stopTiming(display.stampId + 1); */
/* sprintf(fps_text, "FPS: %.2f", 1. / (time / 1000000. / FPS_MEAN)); */
/* startTiming(display.stampId + 1); */
/* display.stampId = (display.stampId + 1) % FPS_MEAN; */
/* SDL_Surface* fpsText = TTF_RenderText_Blended(display.text_font, fps_text, colorWhite); */
/* SDL_Texture* fpsTexture = SDL_CreateTextureFromSurface(display.renderer, fpsText); */
/* int fpsWidth, fpsHeight; */
/* SDL_QueryTexture(fpsTexture, NULL, NULL, &fpsWidth, &fpsHeight); */
/* SDL_Rect fpsTextRect; */
/* fpsTextRect.x = 0; */
/* fpsTextRect.y = 0; */
/* fpsTextRect.w = fpsWidth; */
/* fpsTextRect.h = fpsHeight; */
/* SDL_RenderCopy(display.renderer, fpsTexture, NULL, &fpsTextRect); */
/* /\* Free resources *\/ */
/* SDL_FreeSurface(fpsText); */
/* SDL_DestroyTexture(fpsTexture); */
/* Draw frame cnt Text */
char frame_text[20];
sprintf(frame_text, "frame #%4d", display.frameCnt);
SDL_Surface* frameText = TTF_RenderText_Blended(display.text_font, frame_text, colorWhite);
SDL_Texture* frameTexture = SDL_CreateTextureFromSurface(display.renderer, frameText);
int frameWidth, frameHeight;
SDL_QueryTexture(frameTexture, NULL, NULL, &frameWidth, &frameHeight);
SDL_Rect frameTextRect;
frameTextRect.x = 0;
frameTextRect.y = 0;
frameTextRect.w = frameWidth;
frameTextRect.h = frameHeight;
SDL_RenderCopy(display.renderer, frameTexture, NULL, &frameTextRect);
/* Free resources */
SDL_FreeSurface(frameText);
SDL_DestroyTexture(frameTexture);
SDL_RenderPresent(display.renderer);
SDL_Event event;
// Grab all the events off the queue.
while (SDL_PollEvent(&event))
{
// printf("Goto SDL event %d\n", event.type);
switch (event.type)
{
default: break;
}
}
}
void yuvFinalize(int id)
{
SDL_DestroyTexture(display.textures[id]);
SDL_DestroyRenderer(display.renderer);
SDL_DestroyWindow(display.screen);
}
|
/*******************************************************************************
* tpencoder.cpp -- Copyright 2019 (c) Glenn Ramalho - RFIDo Design
*******************************************************************************
* Description:
* This is a testbench module to emulate a rotary quad encoder with a button.
* This encoder encodes the button by forcing pin B high.
*******************************************************************************
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
#include <systemc.h>
#include "tpencoder.h"
void tpencoder::press(bool pb) {
if (pb) {
pinA.write(GN_LOGIC_1);
buttonpressed = true;
}
else {
pinA.write(GN_LOGIC_Z);
buttonpressed = false;
}
}
void tpencoder::turnleft(int pulses, bool pressbutton) {
/* We start by raising the button, if requested. */
if (pressbutton) press(true);
/* If the last was a left turn, we need to do the direction change glitch.
* Note that if the button is pressed, we only toggle pin B. */
if (!lastwasright) {
wait(speed, SC_MS);
pinB.write(GN_LOGIC_1);
wait(speed, SC_MS);
pinB.write(GN_LOGIC_Z);
}
/* And we apply the pulses, again, watching for the button. */
wait(phase, SC_MS);
while(pulses > 0) {
wait(speed-phase, SC_MS);
if (!buttonpressed) pinA.write(GN_LOGIC_1);
wait(phase, SC_MS);
pinB.write(GN_LOGIC_1);
wait(speed-phase, SC_MS);
if (!buttonpressed) pinA.write(GN_LOGIC_Z);
if (edges == 2) wait(phase, SC_MS);
pinB.write(GN_LOGIC_Z);
if (edges != 2) wait(phase, SC_MS);
pulses = pulses - 1;
}
/* If the customer requested us to press the button with a turn, we release
* it now.
*/
if (pressbutton) {
wait(speed, SC_MS);
press(false);
}
/* And we tag that the last was a right turn as when we shift to the left
* we can have some odd behaviour.
*/
lastwasright = true;
}
void tpencoder::turnright(int pulses, bool pressbutton) {
/* We start by raising the button, if requested. */
if (pressbutton) press(true);
/* If the last was a right turn, we need to do the direction change glitch.
* Note that if the button is pressed, we only toggle pin A. */
if (lastwasright) {
wait(speed, SC_MS);
if (!buttonpressed) pinA.write(GN_LOGIC_1);
wait(speed, SC_MS);
pinB.write(GN_LOGIC_1);
wait(speed, SC_MS);
pinB.write(GN_LOGIC_Z);
wait(speed, SC_MS);
if (!buttonpressed) pinA.write(GN_LOGIC_Z);
}
/* And we apply the pulses, again, watching for the button. */
wait(phase, SC_MS);
while(pulses > 0) {
wait(speed-phase, SC_MS);
pinB.write(GN_LOGIC_1);
wait(phase, SC_MS);
if (!buttonpressed) pinA.write(GN_LOGIC_1);
wait(speed-phase, SC_MS);
pinB.write(GN_LOGIC_Z);
if (edges == 2) wait(phase, SC_MS);
if (!buttonpressed) pinA.write(GN_LOGIC_Z);
if (edges != 2) wait(phase, SC_MS);
pulses = pulses - 1;
}
/* If the customer requested us to press the button with a turn, we release
* it now.
*/
if (pressbutton) {
wait(speed, SC_MS);
press(false);
}
/* And we tag that the last was a left turn, so we can do the left turn to
* right turn glitch.
*/
lastwasright = false;
}
void tpencoder::start_of_simulation() {
pinA.write(GN_LOGIC_Z);
pinB.write(GN_LOGIC_Z);
}
void tpencoder::trace(sc_trace_file *tf) {
sc_trace(tf, buttonpressed, buttonpressed.name());
sc_trace(tf, pinA, pinA.name());
sc_trace(tf, pinB, pinB.name());
}
|
#include <systemc.h>
class sc_mutexx : public sc_prim_channel
{
public:
sc_event _free;
bool _locked;
// blocks until mutex could be locked
void lock()
{
while( _locked ) {
wait( _free );
}
_locked = true;
}
// returns false if mutex could not be locked
bool trylock()
{
if( _locked )
return false;
else
return true;
}
// unlocks mutex
void unlock()
{
_locked = false;
_free.notify();
}
// constructor
sc_mutexx(){
// _locked = false;
}
};
|
#include "systemc.h"
#include "../cnm_base.h"
SC_MODULE(cu_driver) {
#if MIXED_SIM
sc_out<sc_logic> rst;
sc_out<sc_logic> RD; // DRAM read command
sc_out<sc_logic> WR; // DRAM write command
sc_out<sc_logic> ACT; // DRAM activate command
// sc_out<sc_logic> RSTB; //
sc_out<sc_logic> AB_mode; // Signals if the All-Banks mode is enabled
sc_out<sc_logic> pim_mode; // Signals if the PIM mode is enabled
sc_out<sc_lv<BANK_BITS> > bank_addr; // Address of the bank
sc_out<sc_lv<ROW_BITS> > row_addr; // Address of the bank row
sc_out<sc_lv<COL_BITS> > col_addr; // Address of the bank column
sc_out<sc_lv<64> > DQ; // Data input from DRAM controller (output makes no sense
sc_out<sc_lv<32> > instr; // Instruction input from CRF
#else
sc_out<bool> rst;
sc_out<bool> RD; // DRAM read command
sc_out<bool> WR; // DRAM write command
sc_out<bool> ACT; // DRAM activate command
// sc_out<bool> RSTB; //
sc_out<bool> AB_mode; // Signals if the All-Banks mode is enabled
sc_out<bool> pim_mode; // Signals if the PIM mode is enabled
sc_out<sc_uint<BANK_BITS> > bank_addr; // Address of the bank
sc_out<sc_uint<ROW_BITS> > row_addr; // Address of the bank row
sc_out<sc_uint<COL_BITS> > col_addr; // Address of the bank column
sc_out<uint64_t> DQ; // Data input from DRAM controller (output makes no sense
sc_out<uint32_t> instr; // Instruction input from CRF
#endif
SC_CTOR(cu_driver) {
SC_THREAD(driver_thread);
}
void driver_thread();
};
|
/**************************************************************************
* *
* Catapult(R) Machine Learning Reference Design Library *
* *
* Software Version: 1.8 *
* *
* Release Date : Sun Jul 16 19:01:51 PDT 2023 *
* Release Type : Production Release *
* Release Build : 1.8.0 *
* *
* Copyright 2021 Siemens *
* *
**************************************************************************
* Licensed under the Apache License, Version 2.0 (the "License"); *
* you may not use this file except in compliance with the License. *
* You may obtain a copy of the License at *
* *
* http://www.apache.org/licenses/LICENSE-2.0 *
* *
* Unless required by applicable law or agreed to in writing, software *
* distributed under the License is distributed on an "AS IS" BASIS, *
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or *
* implied. *
* See the License for the specific language governing permissions and *
* limitations under the License. *
**************************************************************************
* *
* The most recent version of this package is available at github. *
* *
*************************************************************************/
#pragma once
#include <systemc.h>
#include "rocket_subsystem.h"
SC_MODULE(rocket_wrapper)
{
//== Ports
sc_in<bool> clock;
sc_in<bool> reset;
sc_out<sc_lv<44>> periph_aw_msg;
sc_out<bool> periph_aw_valid;
sc_in<bool> periph_aw_ready;
sc_out<sc_lv<37>> periph_w_msg;
sc_out<bool> periph_w_valid;
sc_in<bool> periph_w_ready;
sc_in<sc_lv<6>> periph_b_msg;
sc_in<bool> periph_b_valid;
sc_out<bool> periph_b_ready;
sc_out<sc_lv<44>> periph_ar_msg;
sc_out<bool> periph_ar_valid;
sc_in<bool> periph_ar_ready;
sc_in<sc_lv<39>> periph_r_msg;
sc_in<bool> periph_r_valid;
sc_out<bool> periph_r_ready;
//== Signals
sc_signal<sc_logic> my_sc_clock;
sc_signal<sc_logic> my_sc_reset;
sc_signal<sc_lv<44>> sc_periph_aw_msg;
sc_signal<sc_logic> sc_periph_aw_valid;
sc_signal<sc_logic> sc_periph_aw_ready;
sc_signal<sc_lv<37>> sc_periph_w_msg;
sc_signal<sc_logic> sc_periph_w_valid;
sc_signal<sc_logic> sc_periph_w_ready;
sc_signal<sc_lv<6>> sc_periph_b_msg;
sc_signal<sc_logic> sc_periph_b_valid;
sc_signal<sc_logic> sc_periph_b_ready;
sc_signal<sc_lv<44>> sc_periph_ar_msg;
sc_signal<sc_logic> sc_periph_ar_valid;
sc_signal<sc_logic> sc_periph_ar_ready;
sc_signal<sc_lv<39>> sc_periph_r_msg;
sc_signal<sc_logic> sc_periph_r_valid;
sc_signal<sc_logic> sc_periph_r_ready;
//sc_logic sc_periph_r_ready;
//== Instances
sc_module_name rocket_sc_module_name{"rocket"};
rocket_subsystem rocket{rocket_sc_module_name, "rocket_subsystem"};
//== Assignment routines
void set_clock() { sc_logic e = (sc_logic) clock.read(); my_sc_clock.write(e); }
void set_reset() { sc_logic e = (sc_logic) reset.read(); my_sc_reset.write(e); }
void set_aw_msg() { sc_lv<44> e = sc_periph_aw_msg.read(); periph_aw_msg.write(e); }
void set_aw_vld() { sc_logic e = sc_periph_aw_valid.read(); periph_aw_valid.write(e.to_bool()); }
void set_aw_rdy() { sc_logic e = (sc_logic) periph_aw_ready.read(); sc_periph_aw_ready.write(e); }
void set_w_msg() { sc_lv<37> e = sc_periph_w_msg.read(); periph_w_msg.write(e); }
void set_w_vld() { sc_logic e = sc_periph_w_valid.read(); periph_w_valid.write(e.to_bool()); }
void set_w_rdy() { sc_logic e = (sc_logic) periph_w_ready.read(); sc_periph_w_ready.write(e); }
void set_b_msg() { sc_lv<6> e = periph_b_msg.read(); sc_periph_b_msg.write(e); }
void set_b_vld() { sc_logic e = (sc_logic) periph_b_valid.read(); sc_periph_b_valid.write(e); }
void set_b_rdy() { sc_logic e = sc_periph_b_ready.read(); periph_b_ready.write(e.to_bool()); }
void set_ar_msg() { sc_lv<44> e = sc_periph_ar_msg.read(); periph_ar_msg.write(e); }
void set_ar_vld() { sc_logic e = sc_periph_ar_valid.read(); periph_ar_valid.write(e.to_bool()); }
void set_ar_rdy() { sc_logic e = (sc_logic) periph_ar_ready.read(); sc_periph_ar_ready.write(e); }
void set_r_msg() { sc_lv<39> e = periph_r_msg.read(); sc_periph_r_msg.write(e); }
void set_r_vld() { sc_logic e = (sc_logic) periph_r_valid.read(); sc_periph_r_valid.write(e); }
void set_r_rdy() { sc_logic e = sc_periph_r_ready.read(); periph_r_ready.write(e.to_bool()); }
//== Constructor
SC_CTOR(rocket_wrapper)
{
rocket.clock(my_sc_clock);
rocket.reset(my_sc_reset);
rocket.periph_aw_msg (sc_periph_aw_msg);
rocket.periph_aw_valid (sc_periph_aw_valid);
rocket.periph_aw_ready (sc_periph_aw_ready);
rocket.periph_w_msg (sc_periph_w_msg);
rocket.periph_w_valid (sc_periph_w_valid);
rocket.periph_w_ready (sc_periph_w_ready);
rocket.periph_b_msg (sc_periph_b_msg);
rocket.periph_b_valid (sc_periph_b_valid);
rocket.periph_b_ready (sc_periph_b_ready);
rocket.periph_ar_msg (sc_periph_ar_msg);
rocket.periph_ar_valid (sc_periph_ar_valid);
rocket.periph_ar_ready (sc_periph_ar_ready);
rocket.periph_r_msg (sc_periph_r_msg);
rocket.periph_r_valid (sc_periph_r_valid);
rocket.periph_r_ready (sc_periph_r_ready);
SC_THREAD(set_clock); sensitive << clock;
SC_THREAD(set_reset); sensitive << reset;
SC_THREAD(set_aw_msg); sensitive << periph_aw_msg;
SC_THREAD(set_aw_vld); sensitive << periph_aw_valid;
SC_THREAD(set_aw_rdy); sensitive << sc_periph_aw_ready;
SC_THREAD(set_w_msg); sensitive << periph_w_msg;
SC_THREAD(set_w_vld); sensitive << periph_w_valid;
SC_THREAD(set_w_rdy); sensitive << sc_periph_w_ready;
SC_THREAD(set_b_msg); sensitive << sc_periph_b_msg;
SC_THREAD(set_b_vld); sensitive << sc_periph_b_valid;
SC_THREAD(set_b_rdy); sensitive << periph_b_ready;
SC_THREAD(set_ar_msg); sensitive << periph_ar_msg;
SC_THREAD(set_ar_vld); sensitive << periph_ar_valid;
SC_THREAD(set_ar_rdy); sensitive << sc_periph_ar_ready;
SC_THREAD(set_r_msg); sensitive << sc_periph_r_msg;
SC_THREAD(set_r_vld); sensitive << sc_periph_r_valid;
SC_THREAD(set_r_rdy); sensitive << periph_r_ready;
}
};
|
/*******************************************************************************
Vendor: GoodKook, [email protected]
Associated Filename: sc_shifter_TB.cpp
Purpose: Testbench
Revision History: Aug. 1, 2024
*******************************************************************************/
#ifndef _SC_SHIFTER_TB_H_
#define _SC_SHIFTER_TB_H_
#include <systemc.h>
#include "Vshifter.h" // Verilated DUT
SC_MODULE(sc_shifter_TB)
{
sc_clock clk;
sc_signal<bool> rst,
sc_signal<sc_bv<7> > rst, din, qout;
Vshifter* u_Vshifter;
sc_trace_file* fp; // SystemC VCD file
SC_CTOR(sc_shifter_TB): // constructor
clk("clk", 100, SC_NS, 0.5, 0.0, SC_NS, false)
{
// instantiate DUT
u_Vshifter = new Vshifter("u_Vshifter");
// Binding
u_Vshifter->clk(clk);
u_Vshifter->rst(rst);
u_Vshifter->din(din);
u_Vshifter->qout(qout);
SC_THREAD(test_generator);
sensitive << clk;
// VCD Trace
fp = sc_create_vcd_trace_file("sc_shifter_TB");
sc_trace(fp, clk, "clk");
sc_trace(fp, rst, "rst");
sc_trace(fp, din, "din");
sc_trace(fp, qout, "qout");
}
void test_generator()
{
int test_count =0;
din.write(0);
rst.write(0);
wait(clk.posedge_event());
wait(clk.posedge_event());
rst.write(1);
wait(clk.posedge_event());
while(true)
{
din.write(1);
wait(clk.posedge_event());
if (test_count>6)
{
sc_close_vcd_trace_file(fp);
sc_stop();
}
else
test_count++;
}
}
};
#endif
|
/*
$Id: ticks.h,v 1.3 2010/11/23 22:42:02 scott Exp $
Description: Macros for timing
Usage: Define the timer call desired (e.g. #define FTIME, TIMEOFDAY, GETTIME)
before including "ticks.h"
Example:
#define TIMEOFDAY 1
#include "ticks.h"
void benchmark(void)
{
tick_t start, finish;
tget(start);
timed_section();
tget(finish);
printf("time in seconds:%f\n", tsec(finish, start));
}
$Log: ticks.h,v $
Revision 1.3 2010/11/23 22:42:02 scott
Add RDTSC (Read Time-Stamp Counter) option that uses the x86 instruction.
By default, use signed long for faster int to float conversion.
Change TICKS_SEC type to unsigned long (nUL).
Revision 1.2 2010/05/12 23:25:24 scott
Update comments for version control
*/
#ifndef _TICKS_H
#define _TICKS_H
/*
Casting the ticks to a signed value allows a more efficient
conversion to a float on x86 CPUs, but it limits the count to one
less high-order bit. Uncomment "unsigned" to use a full tick count.
*/
#define _uns /*unsigned*/
#if defined(FTIME)
/* deprecated */
#include <sys/timeb.h>
typedef struct timeb tick_t;
#define TICKS_SEC 1000U
#define tget(t) ftime(&(t))
#define tval(t) ((unsigned long long)t.time*TICKS_SEC+t.millitm)
#elif defined(TIMEOFDAY)
#include <sys/time.h>
typedef struct timeval tick_t;
#define TICKS_SEC 1000000UL
#define tget(t) gettimeofday(&(t),NULL)
#define tval(t) ((unsigned long long)t.tv_sec*TICKS_SEC+t.tv_usec)
#elif defined(GETTIME)
/* may need to link with lib -lrt */
#include <time.h>
typedef struct timespec tick_t;
#define TICKS_SEC 1000000000UL
#ifndef CLOCK_TYPE
#error CLOCK_TYPE must be defined as one of: \
CLOCK_REALTIME, CLOCK_MONOTONIC, CLOCK_PROCESS_CPUTIME_ID, CLOCK_THREAD_CPUTIME_ID
#endif
#define tget(t) clock_gettime(CLOCK_TYPE,&(t))
#define tval(t) ((unsigned long long)t.tv_sec*TICKS_SEC+t.tv_nsec)
#elif defined(RDTSC)
typedef union {
unsigned long long ui64;
struct {unsigned int lo, hi;} ui32;
} tick_t;
#ifndef TICKS_SEC
#error TICKS_SEC must be defined to match the CPU clock frequency
#endif
#define tget(t) __asm__ __volatile__ ("lfence\n\trdtsc" : "=a" ((t).ui32.lo), "=d"((t).ui32.hi))
#define tval(t) ((t).ui64)
#elif defined(XILTIME)
#include <xtime_l.h>
typedef XTime tick_t;
#ifndef TICKS_SEC
#define TICKS_SEC COUNTS_PER_SECOND
#endif
#define tget(t) XTime_GetTime(&(t))
#define tval(t) (t)
#elif defined(M5RPNS)
/* must link with m5op_<arch>.o */
#include <m5op.h>
typedef uint64_t tick_t;
#define TICKS_SEC 1000000000UL
#define tget(t) t = rpns()
#define tval(t) (t)
#elif defined(SYSTEMC)
#include <systemc.h>
typedef uint64 tick_t;
#define TICKS_SEC 1000000000000ULL
#define tget(t) t = sc_time_stamp().value()
#define tval(t) (t)
#else
#include <time.h>
typedef clock_t tick_t;
#define TICKS_SEC CLOCKS_PER_SEC
#define tget(t) t = clock()
#define tval(t) (t)
#endif
#define tinc(a,b) ((a) += (b))
#define tdec(a,b) ((a) -= (b))
#define tdiff(f,s) (tval(f)-tval(s))
#define tsec(f,s) ((_uns long long)tdiff(f,s)/(double)TICKS_SEC)
#define tvsec(v) ((_uns long long)(v)/(double)TICKS_SEC)
#endif /* _TICKS_H */
|
/**
#define meta ...
prInt32f("%s\n", meta);
**/
/*
All rights reserved to Alireza Poshtkohi (c) 1999-2023.
Email: [email protected]
Website: http://www.poshtkohi.info
*/
#ifndef DEFINE_H
#define DEFINE_H
#include "systemc.h"
//#include <iostream>
#include "stdio.h"
#define SIZE 16
#define NB 4
#define NBb 16
#define nk 4
#define nr 10
#define INFILENAME "aes_cipher_input.txt"
#define INFILENAME_KEY "aes_cipher_key.txt"
#define OUTFILENAME_GOLDEN "aes_cipher_output_golden.txt"
#define OUTFILENAME "aes_cipher_output.txt"
#define DIFFFILENAME "diff.txt"
//#define WAVE_DUMP // set do dump waveform or set as compile option -DWAVE_DUMP
#endif // DEFINE_H
|
// ================================================================
// NVDLA Open Source Project
//
// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
// NVDLA Open Hardware License; Check "LICENSE" which comes with
// this distribution for more information.
// ================================================================
// File Name: nvdla_accu2pp_if_iface.h
#if !defined(_nvdla_accu2pp_if_iface_H_)
#define _nvdla_accu2pp_if_iface_H_
#include <systemc.h>
#include <stdint.h>
#ifndef _nvdla_cc2pp_pkg_struct_H_
#define _nvdla_cc2pp_pkg_struct_H_
typedef struct nvdla_cc2pp_pkg_s {
sc_int<32> data [16];
uint8_t batch_end ;
uint8_t layer_end ;
} nvdla_cc2pp_pkg_t;
#endif
// union nvdla_accu2pp_if_u {
struct nvdla_accu2pp_if_u {
nvdla_cc2pp_pkg_t nvdla_cc2pp_pkg;
};
typedef struct nvdla_accu2pp_if_s {
// union nvdla_accu2pp_if_u pd ;
nvdla_accu2pp_if_u pd ;
} nvdla_accu2pp_if_t;
#endif // !defined(_nvdla_accu2pp_if_iface_H_)
|
// ================================================================
// NVDLA Open Source Project
//
// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
// NVDLA Open Hardware License; Check "LICENSE" which comes with
// this distribution for more information.
// ================================================================
// File Name: nvdla_accu2pp_if_iface.h
#if !defined(_nvdla_accu2pp_if_iface_H_)
#define _nvdla_accu2pp_if_iface_H_
#include <systemc.h>
#include <stdint.h>
#ifndef _nvdla_cc2pp_pkg_struct_H_
#define _nvdla_cc2pp_pkg_struct_H_
typedef struct nvdla_cc2pp_pkg_s {
sc_int<32> data [16];
uint8_t batch_end ;
uint8_t layer_end ;
} nvdla_cc2pp_pkg_t;
#endif
// union nvdla_accu2pp_if_u {
struct nvdla_accu2pp_if_u {
nvdla_cc2pp_pkg_t nvdla_cc2pp_pkg;
};
typedef struct nvdla_accu2pp_if_s {
// union nvdla_accu2pp_if_u pd ;
nvdla_accu2pp_if_u pd ;
} nvdla_accu2pp_if_t;
#endif // !defined(_nvdla_accu2pp_if_iface_H_)
|
/*****************************************************************************
Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
more contributor license agreements. See the NOTICE file distributed
with this work for additional information regarding copyright ownership.
Accellera licenses this file to you under the Apache License, Version 2.0
(the "License"); you may not use this file except in compliance with the
License. You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
implied. See the License for the specific language governing
permissions and limitations under the License.
*****************************************************************************/
/*****************************************************************************
sender.h - This is the interface file for the synchronous process "sender".
Original Author: Rashmi Goswami, Synopsys, Inc.
*****************************************************************************/
/*****************************************************************************
MODIFICATION LOG - modifiers, enter your name, affiliation, date and
changes you are making here.
Name, Affiliation, Date:
Description of Modification:
*****************************************************************************/
#ifndef SENDER_H_INCLUDED
#define SENDER_H_INCLUDED
#include "systemc.h"
#include "pkt.h"
struct sender: sc_module {
sc_out<pkt> pkt_out;
sc_in<sc_int<4> > source_id;
sc_in_clk CLK;
SC_CTOR(sender)
{
SC_CTHREAD(entry, CLK.pos());
}
void entry();
};
#endif // SENDER_H_INCLUDED
|
/*****************************************************************************
Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
more contributor license agreements. See the NOTICE file distributed
with this work for additional information regarding copyright ownership.
Accellera licenses this file to you under the Apache License, Version 2.0
(the "License"); you may not use this file except in compliance with the
License. You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
implied. See the License for the specific language governing
permissions and limitations under the License.
*****************************************************************************/
/*****************************************************************************
sender.h - This is the interface file for the synchronous process "sender".
Original Author: Rashmi Goswami, Synopsys, Inc.
*****************************************************************************/
/*****************************************************************************
MODIFICATION LOG - modifiers, enter your name, affiliation, date and
changes you are making here.
Name, Affiliation, Date:
Description of Modification:
*****************************************************************************/
#ifndef SENDER_H_INCLUDED
#define SENDER_H_INCLUDED
#include "systemc.h"
#include "pkt.h"
struct sender: sc_module {
sc_out<pkt> pkt_out;
sc_in<sc_int<4> > source_id;
sc_in_clk CLK;
SC_CTOR(sender)
{
SC_CTHREAD(entry, CLK.pos());
}
void entry();
};
#endif // SENDER_H_INCLUDED
|
/*****************************************************************************
Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
more contributor license agreements. See the NOTICE file distributed
with this work for additional information regarding copyright ownership.
Accellera licenses this file to you under the Apache License, Version 2.0
(the "License"); you may not use this file except in compliance with the
License. You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
implied. See the License for the specific language governing
permissions and limitations under the License.
*****************************************************************************/
/*****************************************************************************
sender.h - This is the interface file for the synchronous process "sender".
Original Author: Rashmi Goswami, Synopsys, Inc.
*****************************************************************************/
/*****************************************************************************
MODIFICATION LOG - modifiers, enter your name, affiliation, date and
changes you are making here.
Name, Affiliation, Date:
Description of Modification:
*****************************************************************************/
#ifndef SENDER_H_INCLUDED
#define SENDER_H_INCLUDED
#include "systemc.h"
#include "pkt.h"
struct sender: sc_module {
sc_out<pkt> pkt_out;
sc_in<sc_int<4> > source_id;
sc_in_clk CLK;
SC_CTOR(sender)
{
SC_CTHREAD(entry, CLK.pos());
}
void entry();
};
#endif // SENDER_H_INCLUDED
|
/*
Problem 3 Testbench
*/
#include<systemc.h>
#include<comm.cpp>
SC_MODULE(communicationInterfaceTB) {
sc_signal<sc_uint<12> > inData;
sc_signal<bool> clock , reset , clear;
sc_signal<sc_uint<4> > payloadOut;
sc_signal<sc_uint<8> > countOut , errorOut;
void clockSignal();
void clearSignal();
void resetSignal();
void inDataSignal();
communicationInterface* cI;
SC_CTOR(communicationInterfaceTB) {
cI = new communicationInterface ("CI");
cI->clock(clock);
cI->inData(inData);
cI->reset(reset);
cI->clear(clear);
cI->payloadOut(payloadOut);
cI->countOut(countOut);
cI->errorOut(errorOut);
SC_THREAD(clockSignal);
SC_THREAD(clearSignal);
SC_THREAD(resetSignal);
SC_THREAD(inDataSignal);
}
};
void communicationInterfaceTB::clockSignal() {
while (true){
wait(20 , SC_NS);
clock = false;
wait(20 , SC_NS);
clock = true;
}
}
void communicationInterfaceTB::clearSignal() {
while (true){
wait(10 , SC_NS);
clear = false;
wait(100 , SC_NS);
clear = true;
wait(10 , SC_NS);
clear = false;
wait(100 , SC_NS);
}
}
void communicationInterfaceTB::resetSignal() {
while (true) {
wait(10 , SC_NS);
reset = true;
wait(70 , SC_NS);
reset = false;
wait(10 , SC_NS);
reset = true;
wait(1000 , SC_NS);
}
}
void communicationInterfaceTB::inDataSignal() {
while (true) {
wait(10 , SC_NS);
inData = 497;
wait(30 , SC_NS);
inData = 224;
wait(50 , SC_NS);
inData = 369;
wait(30 , SC_NS);
inData = 224;
wait(30 , SC_NS);
}
}
int sc_main(int argc , char* argv[]) {
cout<<"@ "<<sc_time_stamp()<<"----------Start---------"<<endl;
communicationInterfaceTB* cITB = new communicationInterfaceTB ("CITB");
cout<<"@ "<<sc_time_stamp()<<"----------Testbench Instance Created---------"<<endl;
sc_trace_file* VCDFile;
VCDFile = sc_create_vcd_trace_file("communication-interface");
cout<<"@ "<<sc_time_stamp()<<"----------VCD File Created---------"<<endl;
sc_trace(VCDFile, cITB->clock, "Clock");
sc_trace(VCDFile, cITB->inData, "inData");
sc_trace(VCDFile, cITB->reset, "reset");
sc_trace(VCDFile, cITB->clear, "clear");
sc_trace(VCDFile, cITB->payloadOut, "payloadOut");
sc_trace(VCDFile, cITB->countOut, "countOut");
sc_trace(VCDFile, cITB->errorOut, "errorOut");
cout<<"@ "<<sc_time_stamp()<<"----------Start Simulation---------"<<endl;
sc_start(4000, SC_NS);
cout<<"@ "<<sc_time_stamp()<<"----------End Simulation---------"<<endl;
return 0;
}
|
/*****************************************************************************
Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
more contributor license agreements. See the NOTICE file distributed
with this work for additional information regarding copyright ownership.
Accellera licenses this file to you under the Apache License, Version 2.0
(the "License"); you may not use this file except in compliance with the
License. You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
implied. See the License for the specific language governing
permissions and limitations under the License.
*****************************************************************************/
/*****************************************************************************
sender.h - This is the interface file for the synchronous process "sender".
Original Author: Rashmi Goswami, Synopsys, Inc.
*****************************************************************************/
/*****************************************************************************
MODIFICATION LOG - modifiers, enter your name, affiliation, date and
changes you are making here.
Name, Affiliation, Date:
Description of Modification:
*****************************************************************************/
#ifndef SENDER_H_INCLUDED
#define SENDER_H_INCLUDED
#include "systemc.h"
#include "pkt.h"
struct sender: sc_module {
sc_out<pkt> pkt_out;
sc_in<sc_int<4> > source_id;
sc_in_clk CLK;
SC_CTOR(sender)
{
SC_CTHREAD(entry, CLK.pos());
}
void entry();
};
#endif // SENDER_H_INCLUDED
|
/*
* Copyright 2019 Google, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#include "../../systemc.h"
|
/*****************************************************************************
Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
more contributor license agreements. See the NOTICE file distributed
with this work for additional information regarding copyright ownership.
Accellera licenses this file to you under the Apache License, Version 2.0
(the "License"); you may not use this file except in compliance with the
License. You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
implied. See the License for the specific language governing
permissions and limitations under the License.
*****************************************************************************/
/*****************************************************************************
fir_top.h --
Original Author: Rocco Jonack, Synopsys, Inc.
*****************************************************************************/
/*****************************************************************************
MODIFICATION LOG - modifiers, enter your name, affiliation, date and
changes you are making here.
Name, Affiliation, Date:
Description of Modification:
*****************************************************************************/
#include <systemc.h>
#include "fir_fsm.h"
#include "fir_data.h"
SC_MODULE(fir_top) {
sc_in<bool> CLK;
sc_in<bool> RESET;
sc_in<bool> IN_VALID;
sc_in<int> SAMPLE;
sc_out<bool> OUTPUT_DATA_READY;
sc_out<int> RESULT;
sc_signal<unsigned> state_out;
fir_fsm *fir_fsm1;
fir_data *fir_data1;
SC_CTOR(fir_top) {
fir_fsm1 = new fir_fsm("FirFSM");
fir_fsm1->clock(CLK);
fir_fsm1->reset(RESET);
fir_fsm1->in_valid(IN_VALID);
fir_fsm1->state_out(state_out);
fir_data1 = new fir_data("FirData");
fir_data1 -> reset(RESET);
fir_data1 -> state_out(state_out);
fir_data1 -> sample(SAMPLE);
fir_data1 -> result(RESULT);
fir_data1 -> output_data_ready(OUTPUT_DATA_READY);
}
};
|
// ================================================================
// NVDLA Open Source Project
//
// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the
// NVDLA Open Hardware License; Check "LICENSE" which comes with
// this distribution for more information.
// ================================================================
// File Name: nvdla_container_number_8_bit_width_32_iface.h
#if !defined(_nvdla_container_number_8_bit_width_32_iface_H_)
#define _nvdla_container_number_8_bit_width_32_iface_H_
#include <systemc.h>
#include <stdint.h>
typedef struct nvdla_container_number_8_bit_width_32_s {
uint8_t mask ;
sc_uint<32> data [8];
uint8_t last ;
} nvdla_container_number_8_bit_width_32_t;
#endif // !defined(_nvdla_container_number_8_bit_width_32_iface_H_)
|
// -------------------------------------------------
// Contact: [email protected]
// Author: Tobias Ludwig, Michael Schwarz
// -------------------------------------------------
// SPDX-License-Identifier: Apache-2.0
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
#include "systemc.h"
#include "Interfaces.h"
#include "../hmac_core.h"
#include "sha_algo_masked.h"
#include "hmac_sha_join.h"
SC_MODULE(top)
{
HMAC hmc;
SHA512_masked sha384_1;
SHA512_masked sha384_2;
hmac_sha hmacsha;
blocking_in<block> top_hmac;
blocking_out<sc_biguint<KEY_WIDTH>> top_tag;
Blocking<block> hmac_msg;
Blocking<sc_biguint<KEY_WIDTH>> tag;
Blocking<sha_splitter> sha_msg_split_1, sha_msg_split_2;
Blocking<sc_biguint<DIGEST_WIDTH>> H1_setup_digest, hmac_1_digest, hmac_2_digest;
Blocking<sha_block> h_sha_msg_1, h_sha_msg_2;
Blocking<sc_biguint<DIGEST_WIDTH>> sha_1_digest, sha_2_digest;
SC_CTOR(top) : hmc("hmc"),
sha384_1("sha384_1"),
sha384_2("sha384_2"),
hmacsha("hmacsha"),
top_hmac("top_in"),
top_tag("top_out"),
hmac_msg("hmac_msg"),
tag("tag"),
sha_msg_split_1("sha_msg_split_1"),
sha_msg_split_2("sha_msg_split_2"),
//sha_msg_split_2("sha_msg_split_2"),
H1_setup_digest("H1_setup_digest"),
hmac_1_digest("hmac_1_digest"),
hmac_2_digest("hmac_2_digest"),
h_sha_msg_1("h_sha_msg_1"),
h_sha_msg_2("h_sha_msg_2"),
sha_1_digest("sha_1_digest"),
sha_2_digest("sha_2_digest")
{
hmc.hmac_msg(top_hmac);
hmc.sha_msg_1(sha_msg_split_1);
hmacsha.sha_msg_split_1(sha_msg_split_1);
hmacsha.h_sha_msg_1(h_sha_msg_1);
sha384_1.SHA_Input(h_sha_msg_1);
sha384_1.out(sha_1_digest);
hmacsha.hmac_setup_digest(H1_setup_digest);
hmc.H1_setup_digest(H1_setup_digest);
// hmc.sha_msg_2(sha_msg_split_2);
// hmacsha.sha_msg_split_2(sha_msg_split_2);
hmacsha.sha_1_digest(sha_1_digest);
hmacsha.hmac_1_digest(hmac_1_digest);
hmc.H1_digest(hmac_1_digest);
hmc.sha_msg_2(sha_msg_split_2);
hmacsha.sha_msg_split_2(sha_msg_split_2);
hmacsha.h_sha_msg_2(h_sha_msg_2);
sha384_2.SHA_Input(h_sha_msg_2);
sha384_2.out(sha_2_digest);
hmacsha.sha_2_digest(sha_2_digest);
hmacsha.hmac_2_digest(hmac_2_digest);
hmc.H2_digest(hmac_2_digest);
hmc.tag(top_tag);
}
}; |
/// \file transmitter.h
/// \brief File containing the entity of the transmitter component.
///
/// See also transmitter.cpp
#ifndef TRANSMITTER_H
#define TRANSMITTER_H
#include <systemc.h>
#include "NOC_package.h"
/*! \class transmitter
\brief SystemC description of the transmitter module.
It is the transmitter bolck of the GRLS wrapper.
*/
SC_MODULE(transmitter)
//class transmitter : public sc_module
{
/// Input port for datas from the switch
sc_in<Packet> datain;
/// reset port
sc_in<bool> rst_n;
/// clk port
sc_in<bool> clk;
/// full port. If it's set it indicates that the fifo of the transmitter is to small to contain all datas
sc_out<sc_bit> full;
/// strobe output port.It changes with datac
sc_out<sc_bit> strobe;
/// data to the receiver sub-block of the wrapper
sc_out<Packet> datac;
/// main process of the transmitter module
void evaluate();
//Packet FIFO[FIFO_TX_DIM];
/// fifo used to manage case of fast transmitter
Packet* FIFO;
int i,last_pos,c;
ofstream tx_file;
//SC_CTOR(transmitter)
/// constructor of the transmitter
SC_HAS_PROCESS(transmitter);
transmitter(sc_module_name name_ , int N_R , int N_T, int fifo_tx_dim) : sc_module(name_), m_N_R(N_R), m_N_T(N_T),m_fifo_tx_dim(fifo_tx_dim)
{
SC_METHOD(evaluate);
sensitive<<clk.pos()<<rst_n.neg();
FIFO= new Packet[m_fifo_tx_dim];
for (i=0;i<m_fifo_tx_dim;i++)
FIFO[i]=empty_NL_PDU;
last_pos=0;
if(m_N_R > m_N_T)
c=m_N_R;
tx_file.open ("tx_file.txt",ios::trunc);
tx_file << "SIMULATION STARTS NOW: "<<endl<<endl;
tx_file.close();
}
private:
int m_N_R,m_N_T,m_fifo_tx_dim;
};
#endif
|
/*
* breg_if.h
*
* Created on: 14 de mai de 2017
* Author: drcfts
*/
#ifndef BREG_IF_H_
#define BREG_IF_H_
#include "systemc.h"
#include <stdint.h>
struct breg_if : public sc_interface{
virtual int32_t
read(const unsigned address) = 0;
virtual void
write(const unsigned address, int32_t dado) = 0;
virtual void
dump_breg() = 0;
};
#endif /* BREG_IF_H_ */
|
/*******************************************************************************
* adc_types.h -- Copyright 2019 (c) Glenn Ramalho - RFIDo Design
*******************************************************************************
* Description:
* Defines types of ESP32 ADC being used.
*******************************************************************************
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
#ifndef _ADC_TYPES_H
#define _ADC_TYPES_H
#include <systemc.h>
#include "esp32adc1.h"
#include "esp32adc2.h"
typedef esp32adc1 adc1;
typedef esp32adc2 adc2;
extern adc1 *adc1ptr;
extern adc2 *adc2ptr;
#endif
|
//
// Created by tobias on 29.11.17.
//
#ifndef PROJECT_EXAMPLE2_H
#define PROJECT_EXAMPLE2_H
#include "systemc.h"
#include "Interfaces.h"
#include "types.h"
struct Example4 : public sc_module {
SC_HAS_PROCESS(Example4);
Example4(sc_module_name name) :
master_in1("master_in1"),
value_in("value_in"),
report_out("report_out"),
var(10),
section(idle),
value(false),
nextsection(idle){SC_THREAD(fsm); }
//Blocking interface
blocking_in<int> value_in;
master_in <bool> master_in1;
master_in <bool> master_in2;
master_out <bool> report_out;
//Variables
int var;
bool value;
bool succ;
//Sections
enum Sections{idle,reading};
Sections section,nextsection;
//Behavior
void fsm() {
while (true) {
section = nextsection;
if(section == idle){
report_out->write(false);
succ = value_in->nb_read(var);
nextsection = reading;
}
if(section == reading) {
if(var == 0) master_in1->read(value);
if(value == true){
report_out->write(true);
}
nextsection=idle;
}
}
};
};
#endif //PROJECT_EXAMPLE1_H
|
/**********************************************************************
Filename: sc_fir8.h
Purpose : Core of 8-Tab Systolic FIR filter
Author : [email protected]
History : Mar. 2024, First release
***********************************************************************/
#ifndef _SC_FIR8_H_
#define _SC_FIR8_H_
#include <systemc.h>
// Includes for accessing Arduino via serial port
#include <stdio.h>
#include <string.h>
#include <unistd.h>
#include <fcntl.h>
#include <termios.h>
#include "../c_untimed/fir8.h"
SC_MODULE(sc_fir8)
{
sc_in<bool> clk;
sc_in<sc_uint<8> > Xin;
sc_out<sc_uint<8> > Xout;
sc_in<sc_uint<16> > Yin;
sc_out<sc_uint<16> > Yout;
sc_signal<sc_uint<8> > X[FILTER_TAP_NUM]; // Shift Register X
void fir8_thread(void)
{
uint8_t x;
uint8_t yL, yH;
uint16_t y;
while(true)
{
wait(clk.posedge_event());
x = (uint8_t)Xin.read();
while(write(fd, &x, 1)<=0) // Send Byte
usleep(100);
for (int i=0; i<FILTER_TAP_NUM; i++)
{
while(read(fd, &x, 1)<=0) // Receive Byte: Shift Register of X
usleep(100);
X[i].write(sc_uint<8>(x));
}
while(read(fd, &yL, 1)<=0) // Receive Byte:LSB of y
usleep(100);
while(read(fd, &yH, 1)<=0) // Receive Byte:MSB of y
usleep(100);
y = (uint16_t)(yH<<8) | (uint16_t)(yL);
Yout.write(y);
}
}
// Arduino Serial IF
int fd; // Serial port file descriptor
struct termios options; // Serial port setting
#ifdef VCD_TRACE_FIR8
sc_trace_file* fp; // VCD file
#endif
SC_CTOR(sc_fir8):
clk("clk"),
Xin("Xin"),
Xout("Xout"),
Yin("Yin"),
Yout("Yout")
{
SC_THREAD(fir8_thread);
sensitive << clk;
// Arduino DUT
//fd = open("/dev/ttyACM0", O_RDWR | O_NDELAY | O_NOCTTY);
fd = open("/dev/ttyACM0", O_RDWR | O_NOCTTY);
if (fd < 0)
{
perror("Error opening serial port");
//return -1;
}
// Set up serial port
options.c_cflag = B9600 | CS8 | CLOCAL | CREAD;
options.c_iflag = IGNPAR;
options.c_oflag = 0;
options.c_lflag = 0;
// Apply the settings
tcflush(fd, TCIFLUSH);
tcsetattr(fd, TCSANOW, &options);
// Establish Contact
int len = 0;
char rx;
while(!len)
len = read(fd, &rx, 1);
if (rx=='A')
write(fd, &rx, 1);
printf("Connection established...\n");
#ifdef VCD_TRACE_FIR8
// WAVE
fp = sc_create_vcd_trace_file("sc_fir8");
fp->set_time_unit(100, SC_PS); // resolution (trace) ps
sc_trace(fp, clk, "clk");
sc_trace(fp, Xin, "Xin");
sc_trace(fp, Xout, "Xout");
sc_trace(fp, Yin, "Yin");
sc_trace(fp, Yout, "Yout");
char szTrace[8];
for (int i=0; i<FILTER_TAP_NUM; i++)
{
sprintf(szTrace, "X_%d", i);
sc_trace(fp, X[i], szTrace);
}
#endif
}
~sc_fir8(void)
{
close(fd);
}
};
#endif
|
/**************************************************************************
* *
* Catapult(R) Machine Learning Reference Design Library *
* *
* Software Version: 1.8 *
* *
* Release Date : Sun Jul 16 19:01:51 PDT 2023 *
* Release Type : Production Release *
* Release Build : 1.8.0 *
* *
* Copyright 2021 Siemens *
* *
**************************************************************************
* Licensed under the Apache License, Version 2.0 (the "License"); *
* you may not use this file except in compliance with the License. *
* You may obtain a copy of the License at *
* *
* http://www.apache.org/licenses/LICENSE-2.0 *
* *
* Unless required by applicable law or agreed to in writing, software *
* distributed under the License is distributed on an "AS IS" BASIS, *
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or *
* implied. *
* See the License for the specific language governing permissions and *
* limitations under the License. *
**************************************************************************
* *
* The most recent version of this package is available at github. *
* *
*************************************************************************/
#include <systemc.h>
#include "types.h"
#include "axi/axi4.h"
#include "axi4_segment.h"
#include "sysbus_axi_struct.h"
#include "systemc_subsystem.h"
class systemc_subsystem_wrapper : public sc_module, public sysbus_axi {
public:
//== Ports
sc_in <bool> clk;
sc_in <bool> reset_bar;
sc_in <sc_lv<44>> aw_msg_port;
sc_in <bool> aw_valid_port;
sc_out<bool> aw_ready_port;
sc_in <sc_lv<37>> w_msg_port;
sc_in <bool> w_valid_port;
sc_out<bool> w_ready_port;
sc_out<sc_lv<6>> b_msg_port;
sc_out<bool> b_valid_port;
sc_in <bool> b_ready_port;
sc_in <sc_lv<44>> ar_msg_port;
sc_in <bool> ar_valid_port;
sc_out<bool> ar_ready_port;
sc_out<sc_lv<39>> r_msg_port;
sc_out<bool> r_valid_port;
sc_in <bool> r_ready_port;
sc_clock connections_clk;
sc_event check_event;
virtual void start_of_simulation() {
Connections::get_sim_clk().add_clock_alias(
connections_clk.posedge_event(), clk.posedge_event());
}
void check_clock() { check_event.notify(2, SC_PS);} // Let SC and Vlog delta cycles settle.
void check_event_method() {
if (connections_clk.read() == clk.read()) return;
CCS_LOG("clocks misaligned!:" << connections_clk.read() << " " << clk.read());
}
systemc_subsystem CCS_INIT_S1(scs);
SC_CTOR(systemc_subsystem_wrapper)
: connections_clk("connections_clk", CLOCK_PERIOD, SC_NS, 0.5, 0, SC_NS, true)
{
SC_METHOD(check_clock);
sensitive << connections_clk;
sensitive << clk;
SC_METHOD(check_event_method);
sensitive << check_event;
scs.clk(connections_clk);
scs.reset_bar(reset_bar);
scs.w_cpu.aw.dat(aw_msg_port);
scs.w_cpu.aw.vld(aw_valid_port);
scs.w_cpu.aw.rdy(aw_ready_port);
scs.w_cpu.w.dat(w_msg_port);
scs.w_cpu.w.vld(w_valid_port);
scs.w_cpu.w.rdy(w_ready_port);
scs.w_cpu.b.dat(b_msg_port);
scs.w_cpu.b.vld(b_valid_port);
scs.w_cpu.b.rdy(b_ready_port);
scs.r_cpu.ar.dat(ar_msg_port);
scs.r_cpu.ar.vld(ar_valid_port);
scs.r_cpu.ar.rdy(ar_ready_port);
scs.r_cpu.r.dat(r_msg_port);
scs.r_cpu.r.vld(r_valid_port);
scs.r_cpu.r.rdy(r_ready_port);
}
};
#ifdef QUESTA
SC_MODULE_EXPORT(systemc_subsystem_wrapper);
#endif
|
#include <systemc.h>
SC_MODULE( fir ) {
sc_in<bool> clk;
sc_in<bool> rst;
sc_in<sc_int<16>> inp;
sc_out<sc_int<16>> out;
// Handshake signals
sc_in<bool> inp_vld;
sc_out<bool> inp_rdy;
sc_out<bool> out_vld;
sc_in<bool> out_rdy;
void fir_main();
SC_CTOR( fir ) {
SC_CTHREAD(fir_main, clk.pos());
reset_signal_is(rst, true);
}
}; |
#ifndef COUNTER_H
#define COUNTER_H
#include <systemc.h>
#include "constants.h"
SC_MODULE(CounterModule){
// Inputs
sc_in<bool> clk;
sc_in<bool> reset;
sc_in<bool> up_down_ctrl;
sc_in<bool> count_enable;
//Outputs
sc_out<sc_uint<N> > count_out;
sc_out<bool> overflow_intr;
sc_out<bool> underflow_intr;
// Variables
sc_uint<N> count;
// Main function of the module
void do_count();
SC_CTOR(CounterModule){
SC_METHOD(do_count);
sensitive << clk.pos();
}
};
#endif
|
#ifndef __I2C_CONTROLLER_TB_H
#define __I2C_CONTROLLER_TB_H
#include <systemc.h>
#include <i2c_controller.h>
#include <i2c_slave_controller.h>
SC_MODULE(i2c_controller_tb)
{
sc_clock *clk;
sc_signal<bool> rst;
sc_signal<sc_uint<7>> addr;
sc_signal<sc_uint<8>> data_in;
sc_signal<bool> enable;
sc_signal<bool> rw;
sc_signal<sc_lv<8>> data_out;
sc_signal<bool> ready;
sc_signal<sc_logic, SC_MANY_WRITERS> i2c_sda;
sc_signal<sc_logic> i2c_scl;
i2c_controller *master;
i2c_slave_controller *slave;
SC_CTOR(i2c_controller_tb)
{
clk = new sc_clock("clk",2,SC_NS);
master = new i2c_controller("i2c_controller");
master->clk(*clk);
master->rst(rst);
master->addr(addr);
master->data_in(data_in);
master->enable(enable);
master->rw(rw);
master->data_out(data_out);
master->ready(ready);
master->i2c_sda(i2c_sda);
master->i2c_scl(i2c_scl);
slave = new i2c_slave_controller("i2c_slave_controller");
slave->sda(i2c_sda);
slave->scl(i2c_scl);
SC_THREAD(stimuli);
sensitive << *clk << rst;
}
~i2c_controller_tb()
{
delete master;
delete slave;
}
void stimuli();
};
#endif
|
/*******************************************************************************
Poorman's Standard-Emulator
---------------------------
Vendor: GoodKook, [email protected]
Associated Filename: sc_DUT_TB.h
Purpose: Testbench for DUT
Revision History: Jun. 1, 2024
*******************************************************************************/
#ifndef _SC_DUT_TB_H_
#define _SC_DUT_TB_H_
#include <systemc.h>
#include "VDUT.h"
#ifdef CO_EMULATION
#include "DUT.h"
#endif
SC_MODULE(sc_DUT_TB)
{
sc_clock CLK;
sc_signal<bool> nCLR;
sc_signal<bool> nLOAD;
sc_signal<bool> ENP;
sc_signal<bool> ENT;
sc_signal<bool> RCO;
// Verilator treats all Verilog's vector as <uint32_t>
sc_signal<uint32_t> Digit;
sc_signal<uint32_t> Din;
sc_signal<uint32_t> Dout;
// Exact DUT ports' vector width
sc_signal<sc_uint<2> > Digit_n2;
sc_signal<sc_uint<4> > Din_n4;
sc_signal<sc_uint<16> > Dout_n16;
// Verilated DUT or Foreign Verilog
VDUT* u_VDUT;
#ifdef CO_EMULATION
// Emulator DUT
DUT* u_DUT;
sc_signal<sc_uint<16> > Dout_emu;
sc_signal<bool> RCO_emu;
#endif
// Convert Verilator's ports to DUT's ports
void conv_method()
{
Digit_n2.write((sc_uint<2>)Digit);
Din_n4.write((sc_uint<4>)Din);
Dout_n16.write((sc_uint<16>)Dout);
}
void test_generator();
void monitor();
sc_trace_file* fp; // VCD file
SC_CTOR(sc_DUT_TB) : // Constructor
CLK("CLK", 100, SC_NS, 0.5, 0.0, SC_NS, false)
{
SC_THREAD(test_generator);
sensitive << CLK;
SC_THREAD(monitor);
sensitive << CLK;
SC_METHOD(conv_method);
sensitive << Din << Dout << Digit;
// DUT Instantiation
u_VDUT = new VDUT("u_VDUT");
// Binding
u_VDUT->CLK(CLK);
u_VDUT->nCLR(nCLR);
u_VDUT->nLOAD(nLOAD);
u_VDUT->Digit(Digit);
u_VDUT->ENP(ENP);
u_VDUT->ENT(ENT);
u_VDUT->Din(Din);
u_VDUT->Dout(Dout);
u_VDUT->RCO(RCO);
#ifdef CO_EMULATION
u_DUT = new DUT("u_DUT");
// Binding
u_DUT->CLK(CLK);
u_DUT->nCLR(nCLR);
u_DUT->nLOAD(nLOAD);
u_DUT->Digit(Digit_n2);
u_DUT->Din(Din_n4);
u_DUT->Dout(Dout_emu);
u_DUT->RCO(RCO_emu);
#endif
// VCD Trace
fp = sc_create_vcd_trace_file("sc_DUT_TB");
fp->set_time_unit(100, SC_PS);
sc_trace(fp, CLK, "CLK");
sc_trace(fp, nCLR, "nCLR");
sc_trace(fp, nLOAD, "nLOAD");
sc_trace(fp, Digit_n2, "Digit");
sc_trace(fp, ENP, "ENP");
sc_trace(fp, ENT, "ENT");
sc_trace(fp, Din_n4, "Din");
sc_trace(fp, Dout_n16, "Dout");
sc_trace(fp, RCO, "RCO");
#ifdef CO_EMULATION
sc_trace(fp, Dout_emu, "Dout_emu");
sc_trace(fp, RCO_emu, "RCO_emu");
#endif
}
// Destructor
~sc_DUT_TB()
{}
};
#endif // _SC_DUT_H_
|
/****************************************************************************
*
* Copyright (c) 2015, Cadence Design Systems. All Rights Reserved.
*
* This file contains confidential information that may not be
* distributed under any circumstances without the written permision
* of Cadence Design Systems.
*
***************************************************************************/
#ifndef _DUT_CYCSIM_INCLUDED_
#define _DUT_CYCSIM_INCLUDED_
#include "systemc.h"
#include "cynthhl.h"
SC_MODULE(dut_cycsim)
{
// Port declarations.
sc_in< bool > clk;
sc_in< bool > rst;
sc_out< bool > din_busy;
sc_in< bool > din_vld;
sc_in< sc_uint< 8 > > din_data_a;
sc_in< sc_uint< 8 > > din_data_b;
sc_in< sc_uint< 8 > > din_data_c;
sc_in< sc_uint< 8 > > din_data_d;
sc_in< sc_uint< 8 > > din_data_e;
sc_in< sc_uint< 8 > > din_data_f;
sc_in< sc_uint< 8 > > din_data_g;
sc_in< sc_uint< 8 > > din_data_h;
sc_in< bool > dout_busy;
sc_out< bool > dout_vld;
sc_out< sc_uint< 32 > > dout_data;
dut_cycsim( sc_module_name in_name=sc_module_name(sc_gen_unique_name(" dut") ) )
: sc_module(in_name)
,clk("clk")
,rst("rst")
,din_busy("din_busy")
,din_vld("din_vld")
,din_data_a("din_data_a"),
din_data_b("din_data_b"),
din_data_c("din_data_c"),
din_data_d("din_data_d"),
din_data_e("din_data_e"),
din_data_f("din_data_f"),
din_data_g("din_data_g"),
din_data_h("din_data_h")
,dout_busy("dout_busy")
,dout_vld("dout_vld")
,dout_data("dout_data")
{
};
};
#endif
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2017 Cadence Design Systems, Inc. All rights reserved worldwide.
//
// The code contained herein is the proprietary and confidential information
// of Cadence or its licensors, and is supplied subject to a previously
// executed license and maintenance agreement between Cadence and customer.
// This code is intended for use with Cadence high-level synthesis tools and
// may not be used with other high-level synthesis tools. Permission is only
// granted to distribute the code as indicated. Cadence grants permission for
// customer to distribute a copy of this code to any partner to aid in designing
// or verifying the customer's intellectual property, as long as such
// distribution includes a restriction of no additional distributions from the
// partner, unless the partner receives permission directly from Cadence.
//
// ALL CODE FURNISHED BY CADENCE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY
// KIND, AND CADENCE SPECIFICALLY DISCLAIMS ANY WARRANTY OF NONINFRINGEMENT,
// FITNESS FOR A PARTICULAR PURPOSE OR MERCHANTABILITY. CADENCE SHALL NOT BE
// LIABLE FOR ANY COSTS OF PROCUREMENT OF SUBSTITUTES, LOSS OF PROFITS,
// INTERRUPTION OF BUSINESS, OR FOR ANY OTHER SPECIAL, CONSEQUENTIAL OR
// INCIDENTAL DAMAGES, HOWEVER CAUSED, WHETHER FOR BREACH OF WARRANTY,
// CONTRACT, TORT, NEGLIGENCE, STRICT LIABILITY OR OTHERWISE.
//
////////////////////////////////////////////////////////////////////////////////
#ifndef DUT_H
#define DUT_H
/* This file defines the module "dut", which is synthesizable. It is
instantiated in the top-level module System (see system.h). */
#include <systemc.h> /* SystemC definitions. */
#include <esc.h> /* Cadence ESC functions and utilities. */
#include <stratus_hls.h> /* Cadence Stratus definitions. */
#include <cynw_p2p.h> /* The cynw_p2p communication channel. */
#include "stream_16X8.h" /* Generated stream interface classes */
#include "defines.h" /* definitions common to the TB and DUT. */
#include "directives.h" /* Synthesis directives. */
SC_MODULE( dut )
{
sc_in_clk clk;
sc_in< bool > rst;
cynw_p2p< input_data, ioConfig >::in in;
cynw_p2p< output_data, ioConfig >::out out;
stream_16X8::in<ioConfig> streamin;
stream_16X8::out<ioConfig> streamout;
SC_CTOR( dut )
: clk( "clk" )
, rst( "rst" )
, in( "in" )
, out( "out" )
, streamin( "streamin" )
, streamout( "streamout" )
{
SC_CTHREAD( thread1, clk.pos() );
reset_signal_is( rst, false );
in.clk_rst( clk, rst );
out.clk_rst( clk, rst );
streamin.clk_rst( clk, rst );
streamout.clk_rst( clk, rst );
}
sc_uint<8> x[8];
sc_uint<8> y[4];
sc_uint<8> data[16];
void thread1();
};
#endif /* DUT_H */
|
#include <systemc.h>
SC_MODULE( tb )
{
sc_in<bool> clk;
sc_out<bool> rst;
sc_out< sc_int<16> > inp;
sc_out<bool> inp_vld;
sc_in<bool> inp_rdy;
sc_in< sc_int<16> > outp;
sc_in<bool> outp_vld;
sc_out<bool> outp_rdy;
void source();
void sink();
FILE *outfp;
sc_time start_time[64], end_time[64], clock_period;
SC_CTOR( tb ){
SC_CTHREAD( source, clk.pos() );
SC_CTHREAD( sink, clk.pos() );
}
};
|
/**
#define meta ...
prInt32f("%s\n", meta);
**/
/*
All rights reserved to Alireza Poshtkohi (c) 1999-2023.
Email: [email protected]
Website: http://www.poshtkohi.info
*/
#ifndef __s3_h__
#define __s3_h__
#include <systemc.h>
SC_MODULE(s3)
{
sc_in<sc_uint<6> > stage1_input;
sc_out<sc_uint<4> > stage1_output;
void s3_box();
SC_CTOR(s3)
{
SC_METHOD(s3_box);
sensitive << stage1_input;
}
};
#endif
|
#include <systemc.h>
SC_MODULE ( half_adder ) {
sc_in< sc_logic > augend;
sc_in< sc_logic > addend;
sc_out< sc_logic > sum;
sc_out< sc_logic > carry_out;
void func();
SC_CTOR ( half_adder ) {
SC_METHOD ( func );
sensitive << augend << addend;
};
};
|
/********************************************************************************
* University of L'Aquila - HEPSYCODE Source Code License *
* *
* *
* (c) 2018-2019 Centre of Excellence DEWS All rights reserved *
********************************************************************************
* <one line to give the program's name and a brief idea of what it does.> *
* Copyright (C) 2022 Vittoriano Muttillo, Luigi Pomante * *
* *
* This program is free software: you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation, either version 3 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
********************************************************************************
* *
* Created on: 09/May/2022 *
* Authors: Vittoriano Muttillo, Luigi Pomante *
* *
* email: [email protected] *
* [email protected] *
* *
********************************************************************************
* This code has been developed from an HEPSYCODE model used as demonstrator by *
* University of L'Aquila. *
* *
* The code is used as a working example in the 'Embedded Systems' course of *
* the Master in Conputer Science Engineering offered by the *
* University of L'Aquila *
*******************************************************************************/
/********************************************************************************
* display : FirFirGCD Display.
*
* Display: Display (feedback) file
*
********************************************************************************/
/*! \file display.h
\brief Display Documented file.
Display: Display (feedback) file
*/
/** @defgroup firfirgcd_display_group FirFirGCD Display.
*
* Display Implementation
*
* @author V. Muttillo, L. Pomante
* @date Apr. 2022
* @{
*/ // start firfirgcd_display_group
#ifndef __DISPLAY_H__
#define __DISPLAY_H__
/********************************************************************************
*** Includes ***
*******************************************************************************/
#include <systemc.h>
#include "sc_csp_channel_ifs.h"
/********************************************************************************
*** Functions ***
*******************************************************************************/
////////////////////////////
// SBM DEPENDENT
////////////////////////////
////////////////////////////
// DISPLAY: PRINTS TO THE SCREEN DATA FROM THE SYSTEM
////////////////////////////
SC_MODULE(display)
{
// Port for input by channel
sc_port< sc_csp_channel_in_if< sc_uint<8> > > result_channel_port;
SC_CTOR(display)
{
SC_THREAD(output);
}
// Main method
void output();
};
/** @} */ // end of firfirgcd_display_group
#endif
/********************************************************************************
*** EOF ***
********************************************************************************/
|
/********************************************************************************
* University of L'Aquila - HEPSYCODE Source Code License *
* *
* *
* (c) 2018-2019 Centre of Excellence DEWS All rights reserved *
********************************************************************************
* <one line to give the program's name and a brief idea of what it does.> *
* Copyright (C) 2022 Vittoriano Muttillo, Luigi Pomante * *
* *
* This program is free software: you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation, either version 3 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
********************************************************************************
* *
* Created on: 09/May/2022 *
* Authors: Vittoriano Muttillo, Luigi Pomante *
* *
* email: [email protected] *
* [email protected] *
* *
********************************************************************************
* This code has been developed from an HEPSYCODE model used as demonstrator by *
* University of L'Aquila. *
* *
* The code is used as a working example in the 'Embedded Systems' course of *
* the Master in Conputer Science Engineering offered by the *
* University of L'Aquila *
*******************************************************************************/
/********************************************************************************
* SystemManager : System Manager file.
*
* System Manager: HEPSIM System Manager
*
********************************************************************************/
/*! \file SystemManager.cpp
\brief System Manager Documented file.
System Manager: HEPSIM System Manager.
*/
/********************************************************************************
*** Includes ***
*******************************************************************************/
#include <systemc.h>
#include <iostream>
#include <stdlib.h>
#include <stdio.h>
#include <vector>
#include <string.h>
#include "tl.h"
#include "pugixml.hpp"
#include "SystemManager.h"
using namespace std;
using namespace pugi;
////////////////////////////
// SBM INDEPENDENT
////////////////////////////
/********************************************************************************
*** Functions ***
*******************************************************************************/
// Constructor
SystemManager::SystemManager()
{
VPS = generateProcessInstances();
VCH = generateChannelInstances();
VBB = generateBBInstances();
VPL = generatePhysicalLinkInstances();
mappingPS();
mappingCH();
}
// Fill process data structure VPS from xml file (application.xml)
vector<Process> SystemManager:: generateProcessInstances(){
vector<Process> vps2;
int exp_id = 0;
int processId;
pugi::xml_document doc;
pugi::xml_parse_result result = doc.load_file(APPLICATION);
xml_node instancesPS2 = doc.child("instancesPS");
for (pugi::xml_node xn_process = instancesPS2.first_child(); !xn_process.empty(); xn_process = xn_process.next_sibling()){
Process pi;
// Process Name
pi.setName(xn_process.child_value("name"));
// Process id
processId = atoi((char*) xn_process.child_value("id"));
pi.setId(processId);
// Process Priority
pi.setPriority(atoi((char*) xn_process.child_value("priority")));
// Process Criticality
pi.setCriticality(atoi((char*) xn_process.child_value("criticality")));
// Process eqGate (HW size)
xml_node eqGate = xn_process.child("eqGate");
pi.setEqGate((float)eqGate.attribute("value").as_int());
// Process dataType
pi.setDataType(atoi((char*) xn_process.child_value("dataType")));
// Process MemSize (SW Size)
xml_node memSize = xn_process.child("memSize");
xml_node codeSize = memSize.child("codeSize");
for (pugi::xml_node processorModel = codeSize.child("processorModel"); processorModel; processorModel = processorModel.next_sibling()) {
pi.setCodeSize( processorModel.attribute("name").as_string(), processorModel.attribute("value").as_int() );
}
xml_node dataSize = memSize.child("dataSize");
for (pugi::xml_node processorModel = dataSize.child("processorModel"); processorModel; processorModel = processorModel.next_sibling()) {
pi.setDataSize( processorModel.attribute("name").as_string(), processorModel.attribute("value").as_int() );
}
// Process Affinity
xml_node affinity = xn_process.child("affinity");
for (pugi::xml_node processorType = affinity.child("processorType"); processorType; processorType = processorType.next_sibling()) {
string processorType_name = processorType.attribute("name").as_string();
float affinity_value = processorType.attribute("value").as_float();
pi.setAffinity(processorType_name, affinity_value);
}
// Process Concurrency
xml_node concurrency = xn_process.child("concurrency");
for (pugi::xml_node xn_cprocessId = concurrency.child("processId"); xn_cprocessId; xn_cprocessId = xn_cprocessId.next_sibling()) {
unsigned int process_id_n = xn_cprocessId.attribute("id").as_int();
float process_concurrency_value = xn_cprocessId.attribute("value").as_float();
pi.setConcurrency(process_id_n, process_concurrency_value);
}
// Process Load
xml_node load = xn_process.child("load");
for (pugi::xml_node processorId = load.child("processorId"); processorId; processorId = processorId.next_sibling()) {
unsigned int processor_id_n = processorId.attribute("id").as_int();
float process_load_value = processorId.attribute("value").as_float();
pi.setLoad(processor_id_n, process_load_value);
}
// Process time (init)
pi.processTime = sc_time(0, SC_MS);
// Process energy (init)
pi.setEnergy(0);
// Process Communication
// TO DO
if(processId == exp_id){
vps2.push_back(pi);
exp_id++;
} else {
cout << "XML for application is corrupted\n";
exit(11);
}
}
if(exp_id != NPS){
cout << "XML for application is corrupted (NPS)\n";
exit(11);
}
doc.reset();
return vps2;
}
// Fill channel data structure VCH from xml file
vector<Channel> SystemManager:: generateChannelInstances()
{
vector<Channel> vch;
// parsing xml file
xml_document myDoc;
xml_parse_result myResult = myDoc.load_file(APPLICATION);
xml_node instancesLL = myDoc.child("instancesLL");
//channel parameters
xml_node_iterator seqChannel_it;
for (seqChannel_it=instancesLL.begin(); seqChannel_it!=instancesLL.end(); ++seqChannel_it){
xml_node_iterator channel_node_it = seqChannel_it->begin();
Channel ch;
char* temp;
// CH-NAME
string name = channel_node_it->child_value();
ch.setName(name);
// CH-ID
channel_node_it++;
temp = (char*) channel_node_it->child_value();
int id = atoi(temp);
ch.setId(id);
// writer ID
channel_node_it++;
temp = (char*) channel_node_it->child_value();
int w_id = atoi(temp);
ch.setW_id(w_id);
// reader ID
channel_node_it++;
temp = (char*) channel_node_it->child_value();
int r_id = atoi(temp);
ch.setR_id(r_id);
// CH-width (logical width)
channel_node_it++;
temp = (char*) channel_node_it->child_value();
int width = atoi(temp);
ch.setWidth(width);
ch.setNum(0);
vch.push_back(ch);
}
return vch;
}
/*
* for a given processID, increments the profiling variable
* (the number of "loops" executed by the process)
*/
void SystemManager::PS_Profiling(int processId)
{
VPS[processId].profiling++;
}
// Check if a process is allocated on a SPP
bool SystemManager::checkSPP(int processId)
{
return VBB[allocationPS_BB[processId]].getProcessors()[0].getProcessorType() == "SPP";
}
// Return a subset of allocationPS by considering only processes mapped to BB with ID equal to bb_unit_id
vector<int> SystemManager::getAllocationPS_BB(int bb_id)
{
vector<int> pu_alloc;
for (unsigned int j = 2; j < allocationPS_BB.size(); j++) // 0 and 1 are the testbench
{
if (allocationPS_BB[j] == bb_id) pu_alloc.push_back(j);
}
return pu_alloc;
}
///// UPDATE XML Concurrency and Communication
void SystemManager::deleteConcXmlConCom()
{
pugi::xml_document myDoc;
pugi::xml_parse_result myResult = myDoc.load_file("./XML/application.xml");
cout << "XML Delete result: " << myResult.description() << endl;
//method 2: use object/node structure
pugi::xml_node instancesPS = myDoc.child("instancesPS");
xml_node processes = instancesPS.child("process");
for (int i = 0; i < NPS; i++){
xml_node concom = processes.child("concurrency");
for (pugi::xml_node processorId = concom.child("processId"); processorId; processorId = processorId.next_sibling()) {
concom.remove_child(processorId);
}
xml_node concom2 = processes.child("comunication");
for (pugi::xml_node processorId = concom2.child("rec"); processorId; processorId = processorId.next_sibling()) {
concom2.remove_child(processorId);
}
processes = processes.next_sibling();
}
xml_node instancesCH = myDoc.child("instancesLL");
xml_node processesCH = instancesCH.child("logical_link");
for (int i = 0; i < NCH; i++){
xml_node concom3 = processesCH.child("concurrency");
for (pugi::xml_node processorId = concom3.child("channelId"); processorId; processorId = processorId.next_sibling()) {
concom3.remove_child(processorId);
}
processesCH = processesCH.next_sibling();
}
myDoc.save_file("./XML/application.xml");
cout << endl;
}
void SystemManager::updateXmlConCom(float matrixCONC_PS_N[NPS][NPS], unsigned int matrixCOM[NPS][NPS], float matrixCONC_CH_N[NCH][NCH])
{
pugi::xml_document myDoc;
pugi::xml_parse_result myResult = myDoc.load_file("./XML/application.xml");
cout << "XML result: " << myResult.description() << endl;
//method 2: use object/node structure
pugi::xml_node instancesPS = myDoc.child("instancesPS");
for (xml_node_iterator seqProcess_it = instancesPS.begin(); seqProcess_it != instancesPS.end(); ++seqProcess_it){
int Id = atoi(seqProcess_it->child_value("id"));
if (seqProcess_it->child("concurrency")){
pugi::xml_node concurrency = seqProcess_it->child("concurrency");
for (int i = 0; i<NPS; i++){
if (i != Id){
pugi::xml_node conc_it = concurrency.append_child("processId");
conc_it.append_attribute("id").set_value(i);
conc_it.append_attribute("value").set_value(matrixCONC_PS_N[Id][i]);
}
}
}
else{
pugi::xml_node concurrency = seqProcess_it->append_child("concurrency");
for (int i = 0; i<NPS; i++){
if (i != Id){
pugi::xml_node conc_it = concurrency.append_child("processId");
conc_it.append_attribute("id").set_value(i);
conc_it.append_attribute("value").set_value(matrixCONC_PS_N[Id][i]);
}
}
}
}
//method 2: use object/node structure
pugi::xml_node instancesCOM = myDoc.child("instancesPS");
for (pugi::xml_node_iterator seqProcess_it = instancesCOM.begin(); seqProcess_it != instancesCOM.end(); ++seqProcess_it){
int Id = atoi(seqProcess_it->child_value("id"));
if (seqProcess_it->child("comunication")){
pugi::xml_node comunication = seqProcess_it->child("comunication");
for (int i = 0; i<NPS; i++){
if (i != Id){
pugi::xml_node com_it = comunication.append_child("rec");
com_it.append_attribute("idRec").set_value(i);
com_it.append_attribute("value").set_value(matrixCOM[Id][i]);
}
}
}
else{
pugi::xml_node comunication = seqProcess_it->append_child("comunication");
for (int i = 0; i<NPS; i++){
if (i != Id){
pugi::xml_node com_it = comunication.append_child("rec");
com_it.append_attribute("idRec").set_value(i);
com_it.append_attribute("value").set_value(matrixCOM[Id][i]);
}
}
}
}
pugi::xml_node instancesLL = myDoc.child("instancesLL");
for (xml_node_iterator seqLink_it = instancesLL.begin(); seqLink_it != instancesLL.end(); ++seqLink_it){
int Id = atoi(seqLink_it->child_value("id"));
if (seqLink_it->child("concurrency")){
pugi::xml_node concurrencyL = seqLink_it->child("concurrency");
for (int i = 0; i<NCH; i++){
if (i != Id){
pugi::xml_node concL_it = concurrencyL.append_child("channelId");
concL_it.append_attribute("id").set_value(i);
concL_it.append_attribute("value").set_value(matrixCONC_CH_N[Id][i]);
}
}
}
else{
pugi::xml_node concurrencyL = seqLink_it->append_child("concurrency");
for (int i = 0; i<NCH; i++){
if (i != Id){
pugi::xml_node concL_it = concurrencyL.append_child("channelId");
concL_it.append_attribute("id").set_value(i);
concL_it.append_attribute("value").set_value(matrixCONC_CH_N[Id][i]);
}
}
}
}
cout << "Saving result: " << myDoc.save_file("./XML/application.xml") << endl;
myDoc.reset();
cout << endl;
}
#if defined(_TIMING_ENERGY_)
// Fill VBB data structure from xml file (instancesTL.xml)
vector<BasicBlock> SystemManager::generateBBInstances(){
/*****************************
* LOAD BASIC BLOCKS
*****************************/
char* temp;
vector<BasicBlock> vbb;
// parsing xml file
xml_document myDoc;
xml_parse_result myResult = myDoc.load_file("./XML/instancesTL.xml");
xml_node instancesBB = myDoc.child("instancesBB");
for (xml_node_iterator seqBB_it=instancesBB.begin(); seqBB_it!=instancesBB.end(); ++seqBB_it){
xml_node_iterator BB_it = seqBB_it->begin();
BasicBlock bb;
//BB-ID
int id = atoi(BB_it->child_value());
bb.setId(id);
//BB-NAME
BB_it++;
string BBname = BB_it->child_value();
bb.setName(BBname);
//BB-TYPE
BB_it++;
string type = BB_it->child_value();
bb.setType(type);
// PROCESSING UNIT
BB_it++;
vector<ProcessingUnit> vpu;
for(xml_node child = seqBB_it->child("processingUnit");child;child= child.next_sibling("processingUnit")){
xml_node_iterator pu_it = child.begin();
ProcessingUnit pu;
//PU-NAME
string puName = pu_it->child_value();
pu.setName(puName);
//PU-ID
pu_it++;
int idPU = atoi(pu_it->child_value());
pu.setId(idPU);
//Processor Type
pu_it++;
string puType = pu_it->child_value();
pu.setProcessorType(puType);
// PU-cost
pu_it++;
float idCost = (float) atof(pu_it->child_value());
pu.setCost(idCost);
//PU-ISA
pu_it++;
string puISA = pu_it->child_value();
pu.setISA(puISA);
// PU-Frequency (MHz)
pu_it++;
float idFreq = (float) atof(pu_it->child_value());
pu.setFrequency(idFreq);
// PU-CC4CS
float** array = new float*[5];
//Int8
pu_it++;
float idCC4CSminint8 = (float) atof(pu_it->child_value());
pu_it++;
float idCC4CSmaxint8 = (float) atof(pu_it->child_value());
//Int16
pu_it++;
float idCC4CSminint16 = (float) atof(pu_it->child_value());
pu_it++;
float idCC4CSmaxint16 = (float) atof(pu_it->child_value());
//Int32
pu_it++;
float idCC4CSminint32 = (float) atof(pu_it->child_value());
pu_it++;
float idCC4CSmaxint32 = (float) atof(pu_it->child_value());
//Float
pu_it++;
float idCC4CSminfloat = (float) atof(pu_it->child_value());
pu_it++;
float idCC4CSmaxfloat = (float) atof(pu_it->child_value());
//Tot
pu_it++;
float idCC4CSmin = (float) atof(pu_it->child_value());
pu_it++;
float idCC4CSmax = (float) atof(pu_it->child_value());
array[0] = new float[2];
array[0][0] = idCC4CSminint8;
array[0][1] = idCC4CSmaxint8;
array[1] = new float[2];
array[1][0] = idCC4CSminint16;
array[1][1] = idCC4CSmaxint16;
array[2] = new float[2];
array[2][0] = idCC4CSminint32;
array[2][1] = idCC4CSmaxint32;
array[3] = new float[2];
array[3][0] = idCC4CSminfloat;
array[3][1] = idCC4CSmaxfloat;
array[4] = new float[2];
array[4][0] = idCC4CSmin;
array[4][1] = idCC4CSmax;
pu.setCC4S(array);
// PU-Power (W)
pu_it++;
float idPow = (float) atof(pu_it->child_value());
pu.setPower(idPow);
// PU-MIPS
pu_it++;
float idMIPS = (float) atof(pu_it->child_value());
pu.setMIPS(idMIPS);
// PU-I4CS
pu_it++;
float idI4CSmin = (float) atof(pu_it->child_value());
pu.setI4CSmin(idI4CSmin);
pu_it++;
float idI4CSmax = (float) atof(pu_it->child_value());
pu.setI4CSmax(idI4CSmax);
// PU-Vdd (V)
pu_it++;
float idVdd = (float)atof(pu_it->child_value());
pu.setVdd(idVdd);
// PU-Idd (A)
pu_it++;
float idIdd = (float)atof(pu_it->child_value());
pu.setIdd(idIdd);
// PU-overheadCS (us)
pu_it++;
float idOver = (float)atof(pu_it->child_value());
pu.setOverheadCS(sc_time((int)idOver, SC_US));
vpu.push_back(pu);
}
// LOACL MEMORY
bb.setProcessor(vpu);
BB_it++;
xml_node instancesLM = seqBB_it->child("localMemory");
xml_node_iterator lm_it = instancesLM.begin();
//CODE SIZE
int lmCodeSize = (int)atof(lm_it->child_value());
bb.setCodeSize(lmCodeSize);
//DATA SIZE
lm_it++;
int lmDataSize = (int)atof(lm_it->child_value());
bb.setDataSize(lmDataSize);
//eQG
lm_it++;
temp = (char*)lm_it->child_value();
int lmEqG = (int)atof(temp);
bb.setEqG(lmEqG);
// Comunication
BB_it++;
xml_node instancesCU = seqBB_it->child("communicationUnit");
xml_node_iterator cu_it = instancesCU.begin();
// TO DO
// Free Running time
BB_it++;
xml_node instancesFRT = seqBB_it->child("loadEstimation");
xml_node_iterator frt_it = instancesFRT.begin();
float lmFreeRunningTime = frt_it->attribute("value").as_float();
bb.setFRT(lmFreeRunningTime);
vbb.push_back(bb);
}
return vbb;
}
#else
/*
This method generates a dummy instance of a basic block.
Each BB contains more than one processing unit inside.
*/
vector<BasicBlock> SystemManager::generateBBInstances(){
vector<BasicBlock> vbb;
for (int i = 0; i < NBB; i++){
BasicBlock bb;
//BB-ID
bb.setId(i);
//BB-NAME
bb.setName("dummy");
//BB-TYPE
bb.setType("dummy");
// PROCESSING UNIT
vector<ProcessingUnit> vpu;
for (int j = 0; j < 4; j++){ // each block contains at most 4 pu
ProcessingUnit pu;
//PU-NAME
pu.setName("dummy");
//PU-ID
int idPU = j;
pu.setId(idPU);
//Processor Type
pu.setProcessorType("dummy");
//// PU-cost
//pu.setCost(0);
//PU-ISA
pu.setISA("dummy");
// PU-Frequency (MHz)
pu.setFrequency(0);
// PU-CC4CS
float** |
array = new float*[5]; //TODO: eliminare **?
//Int8
float idCC4CSminint8 = 0;
float idCC4CSmaxint8 = 0;
//Int16
float idCC4CSminint16 = 0;
float idCC4CSmaxint16 = 0;
//Int32
float idCC4CSminint32 = 0;
float idCC4CSmaxint32 = 0;
//Float
float idCC4CSminfloat = 0;
float idCC4CSmaxfloat = 0;
//Tot
float idCC4CSmin = 0;
float idCC4CSmax = 0;
//TODO: ciclo con tutti 0!
array[0] = new float[2];
array[0][0] = idCC4CSminint8;
array[0][1] = idCC4CSmaxint8;
array[1] = new float[2];
array[1][0] = idCC4CSminint16;
array[1][1] = idCC4CSmaxint16;
array[2] = new float[2];
array[2][0] = idCC4CSminint32;
array[2][1] = idCC4CSmaxint32;
array[3] = new float[2];
array[3][0] = idCC4CSminfloat;
array[3][1] = idCC4CSmaxfloat;
array[4] = new float[2];
array[4][0] = idCC4CSmin;
array[4][1] = idCC4CSmax;
pu.setCC4S(array);
// PU-Power (W)
pu.setPower(0);
// PU-MIPS
float idMIPS = 0;
pu.setMIPS(idMIPS);
// PU-I4CS
float idI4CSmin = 0;
pu.setI4CSmin(idI4CSmin);
float idI4CSmax = 0;
pu.setI4CSmax(idI4CSmax);
// PU-Vdd (V)
float idVdd = 0;
pu.setVdd(idVdd);
// PU-Idd (A)
float idIdd = 0;
pu.setIdd(idIdd);
// PU-overheadCS (us)
float idOver = 0;
pu.setOverheadCS(sc_time((int)idOver, SC_US));
vpu.push_back(pu);
}
bb.setProcessor(vpu);
// LOCAL MEMORY
//CODE SIZE
bb.setCodeSize(0);
//DATA SIZE
bb.setDataSize(0);
//eQG
bb.setEqG(0);
// Free Running time
float lmFreeRunningTime = 0;
bb.setFRT(lmFreeRunningTime);
vbb.push_back(bb);
}
return vbb;
}
#endif
#if defined(_TIMING_ENERGY_)
// Fill link data structure VPL from xml file (instancesTL.xml)
vector<PhysicalLink> SystemManager:: generatePhysicalLinkInstances()
{
vector<PhysicalLink> VPL;
PhysicalLink l;
// parsing xml file
xml_document myDoc;
xml_parse_result myResult = myDoc.load_file("./XML/instancesTL.xml");
xml_node instancesPL = myDoc.child("instancesPL");
//link parameters
xml_node_iterator seqLink_it;
for (seqLink_it=instancesPL.begin(); seqLink_it!=instancesPL.end(); ++seqLink_it){
xml_node_iterator link_node_it = seqLink_it->begin();
char* temp;
// Link NAME
string name = link_node_it->child_value();
l.setName(name);
// Link ID
link_node_it++;
temp = (char*) link_node_it->child_value();
unsigned int id = atoi(temp);
l.setId(id);
// Link PHYSICAL WIDTH
link_node_it++;
temp = (char*) link_node_it->child_value();
unsigned int physical_width = atoi(temp);
l.setPhysicalWidth(physical_width);
// Link TCOMM
link_node_it++;
temp = (char*) link_node_it->child_value();
float tc = (float) atof(temp);
sc_time tcomm(tc, SC_MS);
l.setTcomm(tcomm);
// Link TACOMM
link_node_it++;
temp = (char*) link_node_it->child_value();
float tac = (float) atof(temp);
sc_time tacomm(tac, SC_MS);
l.setTAcomm(tacomm);
// Link BANDWIDTH
link_node_it++;
temp = (char*) link_node_it->child_value();
unsigned int bandwidth = atoi(temp);
l.setBandwidth(bandwidth);
// Link a2 (coefficient needed to compute energy of the communication)
link_node_it++;
temp = (char*) link_node_it->child_value();
float a2 = (float) atof(temp);
l.seta2(a2);
// Link a1 (coefficient needed to compute energy of the communication)
link_node_it++;
temp = (char*) link_node_it->child_value();
float a1 = (float) atof(temp);
l.seta1(a1);
VPL.push_back(l);
}
return VPL;
}
#else
vector<PhysicalLink> SystemManager::generatePhysicalLinkInstances()
{
vector<PhysicalLink> VPL;
for (int i = 0; i < NPL; i++){
PhysicalLink pl;
pl.setId(i);
pl.setName("dummy");
pl.physical_width=1; // width of the physical link
pl.tcomm=sc_time(0, SC_MS); // LP: (bandwidth / phisycal_widht = 1/sec=hz (inverto)) ( per 1000) (non sforare i 5 ms)
pl.tacomm=sc_time(0, SC_MS); // LP: tcomm * K (es:K=1)
pl.bandwidth=0; // bandwidth in bit/s
pl.a2=0; // a2 coefficient of energy curve
pl.a1=0; // a1 coefficient of energy curve
VPL.push_back(pl);
}
return VPL;
}
#endif
#if defined(_TIMING_ENERGY_)
// Fill allocationPS data structure from xml file
void SystemManager:: mappingPS()
{
int exp_id = 0;
// parsing xml file
xml_document myDoc;
xml_parse_result myResult = myDoc.load_file(MAPPING_PS_BB);
xml_node mapping = myDoc.child("mapping");
//mapping parameters (process to processor)
xml_node_iterator mapping_it;
for (mapping_it=mapping.begin(); mapping_it!=mapping.end(); ++mapping_it){
xml_node_iterator child_mapping_it = mapping_it->begin();
int processId = child_mapping_it->attribute("PSid").as_int();
//string processorName = child_mapping_it->attribute("PRname").as_string();
string bbName = child_mapping_it->attribute("BBname").as_string();
int bbId = child_mapping_it->attribute("value").as_int();
int processingunitID = child_mapping_it->attribute("PUid").as_int(); //added **************
int partitionID = child_mapping_it->attribute("PTid").as_int(); //added **************
if(processId == exp_id){
allocationPS_BB.push_back(bbId);
exp_id++;
} else {
cout << "XML for allocation is corrupted\n";
exit(11);
}
}
}
#else
void SystemManager::mappingPS(){
for (int j = 0; j<NPS; j++){
int bbId = 0;
allocationPS_BB.push_back(bbId);
}
}
#endif
#if defined(_TIMING_ENERGY_)
// Fill allocationCH_PL data structure from xml file
void SystemManager::mappingCH()
{
int exp_id = 0;
// parsing xml file
xml_document myDoc;
xml_parse_result myResult = myDoc.load_file(MAPPING_LC_PL);
xml_node mapping = myDoc.child("mapping");
//mapping parameters (channel to link)
xml_node_iterator mapping_it;
for (mapping_it=mapping.begin(); mapping_it!=mapping.end(); ++mapping_it){
xml_node_iterator child_mapping_it = mapping_it->begin();
int channelId = child_mapping_it->attribute("CHid").as_int();
string linkName = child_mapping_it->attribute("Lname").as_string();
int linkId = child_mapping_it->attribute("value").as_int();
if(channelId == exp_id){
allocationCH_PL.push_back(linkId);
exp_id++;
} else {
cout << "XML for allocation is corrupted\n";
exit(11);
}
}
}
#else
void SystemManager::mappingCH(){
for (int j = 0; j < NCH; j++){
int linkId = 0;
allocationCH_PL.push_back(linkId);
}
}
#endif
///// OTHER METHODS ////////
// Evaluate the simulated time for the execution of a statement
/*
* for a given processID, returns the simulated time
* (the time needed by processor, for the allocated process, to
* to execute a statement)
*/
sc_time SystemManager:: updateSimulatedTime(int processId)
{
// Id representing process dominant datatype
int dataType = VPS[processId].getDataType();
//*********************VPU WAS CHANGED IN VBB**********************
float CC4Smin = VBB[allocationPS_BB[processId]].getProcessors()[0].getCC4S()[dataType][0]; // Average/min number of clock cycles needed by the PU to execute a C statement
float CC4Smax = VBB[allocationPS_BB[processId]].getProcessors()[0].getCC4S()[dataType][1]; // Average/max number of clock cycles needed by the PU to execute a C statement
// Affinity-based interpolation and round up of CC4CSaff
unsigned int CC4Saff = (unsigned int) ceil(CC4Smin + ((CC4Smax-CC4Smin)*(1-VPS[processId].getAffinityByName(VBB[allocationPS_BB[processId]].getProcessors()[0].getProcessorType()))));
float frequency = VBB[allocationPS_BB[processId]].getProcessors()[0].getFrequency(); // Frequency of the processor (MHz)
sc_time value((CC4Saff/(frequency*1000)), SC_MS); // Average time (ms) needed to execute a C statement
return value;
}
// The computation depends on the value setted for energyComputation (EPI or EPC)
float SystemManager:: updateEstimatedEnergy(int processId)
{
float J4CS;
float P;
if(energyComputation == "EPC") {
// EPC --> J4CS = CC4CSaff * EPC = CC4CSaff * (P/f)
// Id representing process dominant datatype
int dataType = VPS[processId].getDataType();
//I HAVE TO ADD A LOOP IN ORDER TO TAKE THE PARAMETERS OF EACH PROCESSOR (?) **********************
float CC4Smin = VBB[allocationPS_BB[processId]].getProcessors()[0].getCC4S()[dataType][0]; // Average/min number of clock cycles needed by the PU to execute a C statement
//float CC4Smin = VBB[allocationPS_BB[processId]].getCC4S()[dataType][0]; // Average/min number of clock cycles needed by the PU to execute a C statement
//float CC4Smax = VBB[allocationPS_BB[processId]].getCC4S()[dataType][1];
float CC4Smax = VBB[allocationPS_BB[processId]].getProcessors()[0].getCC4S()[dataType][1];// Average/max number of clock cycles needed by the PU to execute a C statement
// Affinity-based interpolation
float CC4Saff = CC4Smin + ((CC4Smax-CC4Smin)*(1-VPS[processId].getAffinityByName(VBB[allocationPS_BB[processId]].getProcessors()[0].getProcessorType())));
if(this->checkSPP(processId)) {
// if the process is on a SPP (HW) --> P = Vdd * Idd (V*A = W)
P = VBB[allocationPS_BB[processId]].getProcessors()[0].getVdd() * VBB[allocationPS_BB[processId]].getProcessors()[0].getIdd();
} else {
// if the process is on a GPP/DSP (SW) --> P (W)
P = VBB[allocationPS_BB[processId]].getProcessors()[0].getPower();
}
// EPC = P/f (W/MHz = uJ)
float EPC = P / VBB[allocationPS_BB[processId]].getProcessors()[0].getFrequency();
J4CS = CC4Saff * EPC; // uJ
} else {
// EPI
if(this->checkSPP(processId)) {
// if the process is on a SPP (HW) --> J4CS = CC4CSaff * P * (1/f)
// Id representing process dominant datatype
int dataType = VPS[processId].getDataType();
float CC4Smin = VBB[allocationPS_BB[processId]].getProcessors()[0].getCC4S()[dataType][0]; // Average/min number of clock cycles needed by the PU to execute a C statement
float CC4Smax = VBB[allocationPS_BB[processId]].getProcessors()[0].getCC4S()[dataType][1]; // Average/max number of clock cycles needed by the PU to execute a C statement
// Affinity-based interpolation
float CC4Saff = CC4Smin + ((CC4Smax-CC4Smin)*(1-VPS[processId].getAffinityByName(VBB[allocationPS_BB[processId]].getProcessors()[0].getProcessorType())));
// P = Vdd * Idd (V*A = W)
P = VBB[allocationPS_BB[processId]].getProcessors()[0].getVdd() * VBB[allocationPS_BB[processId]].getProcessors()[0].getIdd();
J4CS = CC4Saff * (P / VBB[allocationPS_BB[processId]].getProcessors()[0].getFrequency()); // uJ
} else {
// if the process is on a GPP/DSP (SW) --> J4CS = I4CSaff * EPI = I4CSaff * (P/MIPS)
float I4CSmin = VBB[allocationPS_BB[processId]].getProcessors()[0].getI4CSmin(); // Average/min number of assembly instructions to execute a C statement
float I4CSmax = VBB[allocationPS_BB[processId]].getProcessors()[0].getI4CSmax(); // Average/max number of assembly instructions to execute a C statement
// Affinity-based interpolation
float I4CSaff = I4CSmin + ((I4CSmax-I4CSmin)*(1-VPS[processId].getAffinityByName(VBB[allocationPS_BB[processId]].getProcessors()[0].getProcessorType())));
P = VBB[allocationPS_BB[processId]].getProcessors()[0].getPower(); // Watt
// EPI = P/MIPS (uJ/instr)
float EPI = P / VBB[allocationPS_BB[processId]].getProcessors()[0].getMIPS();
J4CS = I4CSaff * EPI; // uJ
}
}
return J4CS;
}
// Increase processTime for each statement
void SystemManager:: increaseSimulatedTime(int processId)
{
VPS[processId].processTime += updateSimulatedTime(processId); // Cumulated sum of the statement execution time
}
// Increase energy for each statement
void SystemManager:: increaseEstimatedEnergy(int processId)
{
VPS[processId].energy += updateEstimatedEnergy(processId); // Cumulated sum of the statement execution energy
}
// Increase processTime for the wait of the timers
void SystemManager::increaseTimer(int processId, sc_time delta)
{
VPS[processId].processTime += delta; // Cumulated sum of the statement execution time
}
// Energy XML Updates
void SystemManager::deleteConcXmlEnergy(){
char* temp;
int Id;
pugi::xml_document myDoc;
pugi::xml_parse_result myResult = myDoc.load_file("./XML/application.xml");
cout << "XML Delete result: " << myResult.description() << endl;
//method 2: use object/node structure
pugi::xml_node instancesPS = myDoc.child("instancesPS");
xml_node processes = instancesPS.child("process");
for(int i = 0; i < NPS; i++){
temp = (char*) processes.child_value("id");
Id = atoi(temp); //id process
xml_node energy = processes.child("energy");
for (pugi::xml_node processorId = energy.child("processorId"); processorId; processorId = processorId.next_sibling()) {
unsigned int processor_id_n = processorId.attribute("id").as_int();//
float process_load_value = processorId.attribute("value").as_float();//
if(allocationPS_BB[Id] == processor_id_n){
energy.remove_child(processorId);
}
}
processes = processes.next_sibling();
}
myDoc.save_file("./XML/application.xml");
cout<<endl;
/////////////////////////////////////
pugi::xml_document myDoc2;
pugi::xml_parse_result myResult2 = myDoc2.load_file("./XML/instancesTL.xml");
cout << "XML result: " << myResult2.description() << endl;
pugi::xml_node instancesBB = myDoc2.child("instancesBB");
xml_node basicBlock = instancesBB.child("basicBlock");
for(int i = 0; i < NBB; i++){
temp = (char*) basicBlock.child_value("id");
Id = atoi(temp); //id process
xml_node energyEst = basicBlock.child("energyEstimation");
for (pugi::xml_node energyTOT = energyEst.child("energyTOT"); energyTOT; energyTOT = energyTOT.next_sibling()) {
unsigned int processor_id_n = energyTOT.attribute("id").as_int();//
float energy_value = energyTOT.attribute("value").as_float();//
if(Id == allocationPS_BB[2]){
energyEst.remove_child(energyTOT);
}
}
basicBlock = basicBlock.next_sibling();
}
cout << "Saving result: " << myDoc2.save_file("./XML/instancesTL.xml") << endl;
cout<<endl;
}
void SystemManager:: updateXmlEnergy()
{
pugi::xml_document myDoc;
pugi::xml_parse_result myResult = myDoc.load_file("./XML/application.xml");
cout << "XML result: " << myResult.description() << endl;
//method 2: use object/node structure
pugi::xml_node instancesPS = myDoc.child("instancesPS");
/////////////////////// ENERGY //////////////////////////////
pugi::xml_node instancesPS2 = myDoc.child("instancesPS");
float sumEnergyTot=0;
for (xml_node_iterator seqProcess_it2=instancesPS2.begin(); seqProcess_it2!=instancesPS2.end(); ++seqProcess_it2){
int Id = atoi(seqProcess_it2->child_value("id"));
if(seqProcess_it2->child("energy")){
pugi::xml_node energy = seqProcess_it2->child("energy");
pugi::xml_node energy_it = energy.append_child("processorId");
energy_it.append_attribute("id").set_value(allocationPS_BB[Id]);
energy_it.append_attribute("value").set_value(VPS[Id].getEnergy());
}else{
pugi::xml_node energy = seqProcess_it2->append_child("energy");
pugi::xml_node energy_it = energy.append_child("processorId");
energy_it.append_attribute("id").set_value(allocationPS_BB[Id]);
energy_it.append_attribute("value").set_value(VPS[Id].getEnergy());
}
sumEnergyTot+=VPS[Id].getEnergy();
}
cout << "Saving result: " << myDoc.save_file("./XML/application.xml") << endl;
myDoc.reset();
cout<<endl;
pugi::xml_document myDoc2;
pugi::xml_parse_result myResult2 = myDoc2.load_file("./XML/instancesTL.xml");
cout << "XML result: " << myResult2.description() << endl;
xml_node instancesBB = myDoc2.child("instancesBB");
for (xml_node_iterator seqBB_it=instancesBB.begin(); seqBB_it!=instancesBB.end(); ++seqBB_it){
int Id = atoi(seqBB_it->child_value("id"));
///////////////////// ENERGY ////////////////////////
if(Id == allocationPS_BB[2]){
if(seqBB_it->child("energyEstimation")){
pugi::xml_node energyEstimation = seqBB_it->child("energyEstimation");
xml_node entot_node = energyEstimation.append_child("energyTOT");
entot_node.append_attribute("id").set_value(allocationPS_BB[2]);
entot_node.append_attribute("value").set_value(sumEnergyTot);
}else{
pugi::xml_node energyEstimation = seqBB_it->append_child("energyEstimation");
xml_node entot_node = energyEstimation.append_child("energyTOT");
entot_node.append_attribute("id").set_value(allocationPS_BB[2]);
entot_node.append_attribute("value").set_value(sumEnergyTot);
}
}
}
cout << "Saving result: " << myDoc2.save_file("./XML/instancesTL.xml") << endl;
myDoc2.reset();
cout<<endl;
}
// Load Metrics
sc_time SystemManager::getFRT(){
return this->FRT;
}
void SystemManager::setFRT(sc_time x){
FRT = x;
}
float* SystemManager:: loadEst(sc_time FRT_n){
for(unsigned i =2; i<VPS.size(); i++){
FRL[i] = (float) ((VPS[i].processTime/VPS[i].profiling)/(FRT_n/VPS[i].profiling)); //
}
return FRL;
}
float* SystemManager:: getFRL(){
return this->FRL;
}
// Load XML Updates
void SystemManager::deleteConcXmlLoad(){
char* temp;
int Id;
pugi::xml_document myDoc;
pugi::xml_parse_result myResult = myDoc.load_file("./XML/application.xml");
cout << "XML Delete result: " << myResult.description() << endl;
//method 2: use object/node structure
pugi::xml_node instancesPS = myDoc.child("instancesPS");
xml_node processes = instancesPS.child("process");
for(int i = 0; i < NPS; i++){
temp = (char*) processes.child_value("id");
Id = atoi(temp); //id process
xml_node load = processes.child("load");
for (pugi::xml_node processorId = load.child("processorId"); processorId; processorId = processorId.next_sibling()) {
unsigned int processor_id_n = processorId.attribute("id").as_int();//
float process_load_value = processorId.attribute("value").as_float();//
if(allocationPS_BB[Id] == processor_id_n){
load.remove_child(processorId);
}
}
/* xml_node WCET = processes.child("WCET");
for (pugi::xml_node processorId = WCET.child("processorId"); processorId; processorId = processorId.next_sibling()) {
WCET.remove_child(processorId);
}
xml_node Period = processes.child("Period");
for (pugi::xml_node processorId = Period.child("processorId"); processorId; processorId = processorId.next_sibling()) {
Period.remove_child(processorId);
}
xml_node Deadline = processes.child("Deadline");
for (pugi::xml_node processorId = Deadline.child("processorId"); processorId; processorId = processorId.next_sibling()) {
Deadline.remove_child(processorId);
} */
processes = processes.next_sibling();
}
myDoc.save_file("./XML/application.xml");
cout<<endl;
pugi::xml_document myDoc2;
pugi::xml_parse_result myResult2 = myDoc2.load_file("./XML/instancesTL.xml");
cout << "XML result: " << myResult2.description() << endl;
pugi::xml_node instancesBB = myDoc2.child("instancesBB");
xml_node basicBlock = instancesBB.child("basicBlock");
for(int i = 0; i < NBB; i++){
temp = (char*) basicBlock.child_value("id");
Id = atoi(temp); //id process
xml_node loadEst = basicBlock.child("loadEstimation");
for (pugi::xml_node loadTOT = loadEst.child("FreeRunningTime"); loadTOT; loadTOT = loadTOT.next_sibling()) {
unsigned int processor_id_n = loadTOT.attribute("id").as_int();//
float energy_value = loadTOT.attribute("value").as_float();//
if(Id == allocationPS_BB[2]){
loadEst.remove_child(loadTOT);
}
}
basicBlock = basicBlock.next_sibling();
}
cout << "Saving result: " << myDoc2.save_file("./XML/instancesTL.xml") << endl;
myDoc2.reset();
cout<<endl;
}
void SystemManager:: updateXmlLoad()
{
pugi::xml_document myDoc;
pugi::xml_parse_result myResult = myDoc.load_file("./XML/application |
.xml");
cout << "XML result: " << myResult.description() << endl;
//method 2: use object/node structure
pugi::xml_node instancesPS = myDoc.child("instancesPS");
for (xml_node_iterator seqProcess_it=instancesPS.begin(); seqProcess_it!=instancesPS.end(); ++seqProcess_it){
int Id = atoi(seqProcess_it->child_value("id"));
///////////////////// LOAD ////////////////////////////
if(seqProcess_it->child("load")){
pugi::xml_node load = seqProcess_it->child("load");
pugi::xml_node load_it = load.append_child("processorId");
load_it.append_attribute("id").set_value(allocationPS_BB[Id]);
load_it.append_attribute("value").set_value(FRL[Id]);
}else{
pugi::xml_node load = seqProcess_it->append_child("load");
pugi::xml_node load_it = load.append_child("processorId");
load_it.append_attribute("id").set_value(allocationPS_BB[Id]);
load_it.append_attribute("value").set_value(FRL[Id]);
}
}
/////////////////////// WCET //////////////////////////////
////method 2: use object/node structure
//pugi::xml_node instancesPS2 = myDoc.child("instancesPS");
//for (pugi::xml_node_iterator seqProcess_it=instancesPS2.begin(); seqProcess_it!=instancesPS2.end(); ++seqProcess_it){
// int Id = atoi(seqProcess_it->child_value("id"));
//
// if(seqProcess_it->child("WCET")){
// pugi::xml_node comunication = seqProcess_it->child("WCET");
// for (int i=0; i<NPS; i++){
// if(i!=Id){
// pugi::xml_node wcet_it = comunication.append_child("processorId");
// double wcet_task = (VPS[Id].processTime.to_seconds());
// wcet_it.append_attribute("id").set_value(i);
// wcet_it.append_attribute("value").set_value((wcet_task/VPS[Id].profiling)*1000000.0);
// }
// }
// }else{
// pugi::xml_node WCET = seqProcess_it->append_child("WCET");
// for (int i=0; i<VPU.size(); i++){
// if(i!=Id){
// pugi::xml_node wcet_it = WCET.append_child("processorId");
// double wcet_task = (VPS[Id].processTime.to_seconds());
// wcet_it.append_attribute("id").set_value(i);
// wcet_it.append_attribute("value").set_value((wcet_task/VPS[Id].profiling)*1000000.0);
// }
// }
// }
//}
/////////////////////// PERIOD //////////////////////////////
//pugi::xml_node instancesPS3 = myDoc.child("instancesPS");
//for (xml_node_iterator seqLink_it=instancesPS3.begin(); seqLink_it!=instancesPS3.end(); ++seqLink_it){
// int Id = atoi(seqLink_it->child_value("id"));
//
// if(seqLink_it->child("Period")){
// pugi::xml_node Period = seqLink_it->child("Period");
// for (int i=0; i<NPS; i++){
// if(i!=Id){
// pugi::xml_node period_it = Period.append_child("processorId");
// period_it.append_attribute("id").set_value(i);
// double period_value = (FRT.to_seconds());
// period_it.append_attribute("value").set_value((period_value/VPS[Id].profiling)*1000000.0);
// }
// }
// }else{
// pugi::xml_node Period = seqLink_it->append_child("Period");
// for (int i=0; i<NPS; i++){
// if(i!=Id){
// pugi::xml_node period_it = Period.append_child("processorId");
// period_it.append_attribute("id").set_value(i);
// double period_value = (FRT.to_seconds());
// period_it.append_attribute("value").set_value((period_value/VPS[Id].profiling)*1000000.0);
// }
// }
// }
//}
///////////////////////// DEADLINE //////////////////////////////
// pugi::xml_node instancesPS4 = myDoc.child("instancesPS");
//for (xml_node_iterator seqLink_it=instancesPS4.begin(); seqLink_it!=instancesPS4.end(); ++seqLink_it){
// int Id = atoi(seqLink_it->child_value("id"));
// if(seqLink_it->child("Deadline")){
// pugi::xml_node Deadline = seqLink_it->child("Deadline");
// for (int i=0; i<NPS; i++){
// if(i!=Id){
// pugi::xml_node dead_it = Deadline.append_child("processorId");
// dead_it.append_attribute("id").set_value(i);
// double deadline_value = (FRT.to_seconds());
// double dead_tot = (deadline_value/VPS[Id].profiling)*1000000.0;
// cout<<"VPS["<<Id<<"].profiling --> "<<VPS[Id].profiling<<endl;
// dead_it.append_attribute("value").set_value(dead_tot);
// }
// }
// }else{
// pugi::xml_node Deadline = seqLink_it->append_child("Deadline");
// for (int i=0; i<NPS; i++){
// if(i!=Id){
// pugi::xml_node dead_it = Deadline.append_child("processorId");
// dead_it.append_attribute("id").set_value(i);
// double deadline_value = (FRT.to_seconds());
// double dead_tot = (deadline_value/VPS[Id].profiling)*1000000.0;
// dead_it.append_attribute("value").set_value(dead_tot);
// }
// }
// }
//}
cout << "Saving result: " << myDoc.save_file("./XML/application.xml") << endl;
myDoc.reset();
cout<<endl;
/* pugi::xml_document myDoc2;
pugi::xml_parse_result myResult2 = myDoc2.load_file("./XML/instancesTL.xml");
cout << "XML result: " << myResult2.description() << endl;
xml_node instancesBB = myDoc2.child("instancesBB");
for (xml_node_iterator seqBB_it=instancesBB.begin(); seqBB_it!=instancesBB.end(); ++seqBB_it){
int Id = atoi(seqBB_it->child_value("id"));
///////////////////// LOAD ////////////////////////////
if(seqBB_it->child("loadEstimation")){
pugi::xml_node loadEstimation = seqBB_it->child("loadEstimation");
xml_node frl_node = loadEstimation.child("FreeRunningTime");
if(!(allocationPS_BB[Id] != Id))
{
sc_time local_frt = FRT;
//frl_node.attribute("value")=(local_frt.to_double()*1000); //another solution for the number conversion
frl_node.attribute("value")=(local_frt.to_seconds()*1000);
}
}else{
pugi::xml_node loadEstimation = seqBB_it->append_child("loadEstimation");
xml_node frl_node = loadEstimation.append_child("FreeRunningTime");
if(allocationPS_BB[Id] == Id)
{
sc_time local_frt = FRT;
//frl_node.attribute("value")=(local_frt.to_double()*1000); //another solution for the number conversion
frl_node.attribute("value")=(local_frt.to_seconds()*1000);
}
}
}
cout << "Saving result: " << myDoc2.save_file("./XML/instancesTL.xml") << endl;
myDoc2.reset();
cout<<endl; */
///////////////////////////////////////////////////
pugi::xml_document myDoc2;
pugi::xml_parse_result myResult2 = myDoc2.load_file("./XML/instancesTL.xml");
cout << "XML result: " << myResult2.description() << endl;
xml_node instancesBB = myDoc2.child("instancesBB");
for (xml_node_iterator seqBB_it=instancesBB.begin(); seqBB_it!=instancesBB.end(); ++seqBB_it){
int Id = atoi(seqBB_it->child_value("id"));
///////////////////// ENERGY ////////////////////////
if(Id == allocationPS_BB[2]){
if(seqBB_it->child("loadEstimation")){
pugi::xml_node energyEstimation = seqBB_it->child("loadEstimation");
xml_node entot_node = energyEstimation.append_child("FreeRunningTime");
entot_node.append_attribute("id").set_value(allocationPS_BB[2]);
sc_time local_frt = FRT;
entot_node.append_attribute("value").set_value(local_frt.to_seconds()*1000);
}else{
pugi::xml_node energyEstimation = seqBB_it->append_child("energyEstimation");
xml_node entot_node = energyEstimation.append_child("energyTOT");
entot_node.append_attribute("id").set_value(allocationPS_BB[2]);
sc_time local_frt = FRT;
entot_node.append_attribute("value").set_value(local_frt.to_seconds()*1000);
}
}
}
cout << "Saving result: " << myDoc2.save_file("./XML/instancesTL.xml") << endl;
myDoc2.reset();
cout<<endl;
}
/********************************************************************************
*** EOF ***
********************************************************************************/
|
/****************************************************************************
*
* Copyright (c) 2015, Cadence Design Systems. All Rights Reserved.
*
* This file contains confidential information that may not be
* distributed under any circumstances without the written permision
* of Cadence Design Systems.
*
***************************************************************************/
#ifndef _DUT_CYCSIM_INCLUDED_
#define _DUT_CYCSIM_INCLUDED_
#include "systemc.h"
#include "cynthhl.h"
SC_MODULE(dut_cycsim)
{
// Port declarations.
sc_in< bool > clk;
sc_in< bool > rst;
sc_out< bool > din_1_busy;
sc_in< bool > din_1_vld;
sc_in< sc_uint< 8 > > din_1_data;
sc_out< bool > din_2_busy;
sc_in< bool > din_2_vld;
sc_in< sc_uint< 8 > > din_2_data;
sc_in< bool > dout_busy;
sc_out< bool > dout_vld;
sc_out< sc_uint< 9 > > dout_data;
dut_cycsim( sc_module_name in_name=sc_module_name(sc_gen_unique_name(" dut") ) )
: sc_module(in_name)
,clk("clk")
,rst("rst")
,din_1_busy("din_1_busy")
,din_1_vld("din_1_vld")
,din_1_data("din_1_data")
,din_2_busy("din_2_busy")
,din_2_vld("din_2_vld")
,din_2_data("din_2_data")
,dout_busy("dout_busy")
,dout_vld("dout_vld")
,dout_data("dout_data")
{
};
};
#endif
|
#include <memory>
#include <systemc.h>
#include "Vtop.h"
#include "bfm.h"
SC_MODULE(sc_top) {
sc_clock clk;
sc_signal<bool> reset;
sc_signal<bool> cs;
sc_signal<bool> rw;
sc_signal<bool> ready;
#ifdef VERILATOR
sc_signal<uint32_t> addr;
sc_signal<uint32_t> data_in;
sc_signal<uint32_t> data_out;
#else
sc_signal<sc_uint<16>> addr;
sc_signal<sc_uint<32>> data_in;
sc_signal<sc_uint<32>> data_out;
#endif
Vtop *u_top;
bfm *u_bfm;
SC_CTOR(sc_top) :
clk("clk", 10, SC_NS, 0.5, 5, SC_NS, true),
reset("reset"), cs("cs"), rw("rw"), addr("addr"), ready("ready"), data_in("data_in"), data_out("data_out") {
#ifdef VERILATOR
u_top = new Vtop{"top"};
#else
u_top = new Vtop{"top", "Vtop", 0, NULL};
#endif
u_top->clk(clk);
u_top->reset(reset);
u_top->cs(cs);
u_top->rw(rw);
u_top->addr(addr);
u_top->data_in(data_in);
u_top->ready(ready);
u_top->data_out(data_out);
u_bfm = new bfm("bfm");
u_bfm->clk(clk);
u_bfm->reset(reset);
u_bfm->cs(cs);
u_bfm->rw(rw);
u_bfm->addr(addr);
u_bfm->data_in(data_out);
u_bfm->ready(ready);
u_bfm->data_out(data_in);
}
~sc_top() {
#ifdef VERILATOR
u_top->final();
#endif
delete u_top;
delete u_bfm;
}
};
|
/**********************************************************************
Filename: sc_fir_pe.h
Purpose : Verilated PE of Systolic FIR filter
Author : [email protected]
History : Mar. 2024, First release
***********************************************************************/
#ifndef _V_FIR_PE_H_
#define _V_FIR_PE_H_
#include <systemc.h>
#include "./obj_dir/Vfir_pe.h"
SC_MODULE(V_fir_pe)
{
sc_in<bool> clk;
sc_in<bool> Rdy;
sc_out<bool> Vld;
sc_in<sc_uint<6> > Cin;
sc_in<sc_uint<4> > Xin;
sc_out<sc_uint<4> > Xout;
sc_in<sc_uint<4> > Yin;
sc_out<sc_uint<4> > Yout;
Vfir_pe* u_Vfir_pe;
sc_signal<uint32_t> _Cin;
sc_signal<uint32_t> _Xin;
sc_signal<uint32_t> _Xout;
sc_signal<uint32_t> _Yin;
sc_signal<uint32_t> _Yout;
sc_signal<bool> _Rdy;
sc_signal<bool> _Vld;
void pe_method(void)
{
_Cin = (uint32_t)Cin.read();
_Xin = (uint32_t)Xin.read();
_Yin = (uint32_t)Yin.read();
_Rdy = Rdy.read();
Xout.write(sc_uint<4>(_Xout));
Yout.write(sc_uint<4>(_Yout));
Vld.write(_Vld);
}
SC_CTOR(V_fir_pe):
clk("clk"),
Rdy("Rdy"), _Rdy("_Rdy"),
Vld("Vld"), _Vld("_Vld"),
Cin("Cin"), _Cin("_Cin"),
Xin("Xin"), _Xin("_Xin"),
Xout("Xout"), _Xout("_Xout"),
Yin("Yin"), _Yin("_Yin"),
Yout("Yout"), _Yout("_Yout")
{
SC_METHOD(pe_method);
sensitive << clk << Cin << Xin << Yin << Rdy;
// Instantiate Verilated PE
u_Vfir_pe = new Vfir_pe("u_Vfir_pe");
u_Vfir_pe->clk(clk);
u_Vfir_pe->Cin(_Cin);
u_Vfir_pe->Xin(_Xin);
u_Vfir_pe->Xout(_Xout);
u_Vfir_pe->Yin(_Yin);
u_Vfir_pe->Yout(_Yout);
u_Vfir_pe->Rdy(_Rdy);
u_Vfir_pe->Vld(_Vld);
}
~V_fir_pe(void)
{
}
};
#endif
|
// Generated by stratus_hls 17.20-p100 (88533.190925)
// Mon Nov 16 23:44:47 2020
// from dut.cc
#ifndef CYNTH_PART_dut_dut_rtl_h
#define CYNTH_PART_dut_dut_rtl_h
#include "systemc.h"
/* Include declarations of instantiated parts. */
/* Declaration of the synthesized module. */
struct dut : public sc_module {
sc_in<bool > clk;
sc_in<bool > rst;
sc_out<bool > din_busy;
sc_in<bool > din_vld;
sc_in<sc_uint<8> > din_data;
sc_in<bool > dout_busy;
sc_out<bool > dout_vld;
sc_out<sc_uint<11> > dout_data;
dut( sc_module_name name );
SC_HAS_PROCESS(dut);
sc_signal<bool > dout_m_req_m_prev_trig_req;
sc_signal<sc_uint<1> > dut_Xor_1Ux1U_1U_4_9_out1;
sc_signal<bool > dout_m_unacked_req;
sc_signal<sc_uint<1> > dut_Or_1Ux1U_1U_4_10_out1;
sc_signal<sc_uint<1> > dut_N_Muxb_1_2_0_4_1_out1;
sc_signal<sc_uint<1> > dut_And_1Ux1U_1U_4_5_out1;
sc_signal<sc_uint<1> > dut_Not_1U_1U_4_4_out1;
sc_signal<sc_uint<1> > dut_Or_1Ux1U_1U_4_2_out1;
sc_signal<bool > din_m_unvalidated_req;
sc_signal<sc_uint<1> > dut_And_1Ux1U_1U_4_3_out1;
sc_signal<sc_uint<2> > global_state_next;
sc_signal<sc_uint<1> > dut_Not_1U_1U_4_6_out1;
sc_signal<sc_uint<1> > dut_And_1Ux1U_1U_4_11_out1;
sc_signal<sc_uint<1> > dut_Not_1U_1U_4_12_out1;
sc_signal<bool > dout_m_req_m_trig_req;
sc_signal<sc_uint<2> > global_state;
sc_signal<bool > din_m_busy_req_0;
sc_signal<sc_uint<11> > dut_Mul_8Ux3U_11U_4_13_out1;
sc_signal<sc_uint<1> > stall0;
void drive_dout_data();
void drive_din_m_busy_req_0();
void drive_dout_m_req_m_trig_req();
void drive_stall0();
void dut_Mul_8Ux3U_11U_4_13();
void drive_global_state();
void drive_global_state_next();
void drive_din_busy();
void dut_Or_1Ux1U_1U_4_2();
void dut_And_1Ux1U_1U_4_3();
void dut_Not_1U_1U_4_4();
void dut_And_1Ux1U_1U_4_5();
void dut_Not_1U_1U_4_6();
void drive_din_m_unvalidated_req();
void dut_N_Muxb_1_2_0_4_1();
void drive_dout_vld();
void dut_Or_1Ux1U_1U_4_10();
void drive_dout_m_unacked_req();
void dut_And_1Ux1U_1U_4_11();
void dut_Xor_1Ux1U_1U_4_9();
void drive_dout_m_req_m_prev_trig_req();
void dut_Not_1U_1U_4_12();
};
#endif
|
// Generated by stratus_hls 17.20-p100 (88533.190925)
// Tue Nov 17 14:53:19 2020
// from dut.cc
#ifndef CYNTH_PART_dut_dut_rtl_h
#define CYNTH_PART_dut_dut_rtl_h
#include "systemc.h"
/* Include declarations of instantiated parts. */
/* Declaration of the synthesized module. */
struct dut : public sc_module {
sc_in<bool > clk;
sc_in<bool > rst;
sc_out<bool > din_busy;
sc_in<bool > din_vld;
sc_in<sc_uint<8> > din_data;
sc_in<bool > dout_busy;
sc_out<bool > dout_vld;
sc_out<sc_uint<11> > dout_data;
sc_out<bool > mem_WE0;
sc_out<sc_uint<8> > mem_DIN0;
sc_in<sc_uint<8> > mem_DOUT0;
sc_out<sc_uint<6> > mem_A0;
sc_out<bool > mem_REQ0;
dut( sc_module_name name );
SC_HAS_PROCESS(dut);
sc_signal<bool > dout_m_req_m_prev_trig_req;
sc_signal<sc_uint<1> > dut_Xor_1Ux1U_1U_4_9_out1;
sc_signal<bool > dout_m_unacked_req;
sc_signal<sc_uint<1> > dut_Or_1Ux1U_1U_4_10_out1;
sc_signal<sc_uint<1> > dut_N_Muxb_1_2_0_4_1_out1;
sc_signal<sc_uint<1> > dut_And_1Ux1U_1U_4_5_out1;
sc_signal<sc_uint<1> > dut_Not_1U_1U_4_4_out1;
sc_signal<sc_uint<1> > dut_Or_1Ux1U_1U_4_2_out1;
sc_signal<bool > din_m_unvalidated_req;
sc_signal<sc_uint<1> > dut_And_1Ux1U_1U_4_3_out1;
sc_signal<sc_uint<3> > global_state_next;
sc_signal<sc_int<7> > dut_Add_7Sx2S_8S_4_13_in2;
sc_signal<sc_uint<1> > gs_ctrl0;
sc_signal<sc_uint<6> > dut_Add_6Ux1U_6U_4_15_out1;
sc_signal<sc_uint<1> > dut_Not_1U_1U_4_6_out1;
sc_signal<sc_uint<1> > dut_And_1Ux1U_1U_4_11_out1;
sc_signal<sc_uint<1> > dut_Not_1U_1U_4_12_out1;
sc_signal<bool > dout_m_req_m_trig_req;
sc_signal<sc_uint<1> > dut_LessThan_8Sx8S_1U_4_14_out1;
sc_signal<bool > din_m_busy_req_0;
sc_signal<sc_uint<9> > dut_Add_8Ux8U_9U_4_16_out1;
sc_signal<sc_int<8> > dut_Add_7Sx2S_8S_4_13_out1;
sc_signal<sc_int<10> > dout_data_slice;
sc_signal<sc_uint<1> > stall0;
sc_signal<bool > mem_WE0_reg;
sc_signal<sc_uint<8> > s_reg_7;
sc_signal<sc_uint<3> > global_state;
sc_signal<bool > mem_REQ0_reg;
void drive_mem_REQ0();
void drive_mem_A0();
void drive_mem_DIN0();
void drive_mem_WE0();
void drive_dout_data();
void drive_din_m_busy_req_0();
void drive_dout_m_req_m_trig_req();
void drive_stall0();
void drive_mem_WE0_reg();
void drive_mem_REQ0_reg();
void drive_s_reg_7();
void drive_dut_Add_7Sx2S_8S_4_13_in2();
void dut_Add_7Sx2S_8S_4_13();
void dut_LessThan_8Sx8S_1U_4_14();
void dut_Add_6Ux1U_6U_4_15();
void dut_Add_8Ux8U_9U_4_16();
void drive_global_state();
void drive_global_state_next();
void drive_gs_ctrl0();
void drive_din_busy();
void dut_Or_1Ux1U_1U_4_2();
void dut_And_1Ux1U_1U_4_3();
void dut_Not_1U_1U_4_4();
void dut_And_1Ux1U_1U_4_5();
void dut_Not_1U_1U_4_6();
void drive_din_m_unvalidated_req();
void dut_N_Muxb_1_2_0_4_1();
void drive_dout_vld();
void dut_Or_1Ux1U_1U_4_10();
void drive_dout_m_unacked_req();
void dut_And_1Ux1U_1U_4_11();
void dut_Xor_1Ux1U_1U_4_9();
void drive_dout_m_req_m_prev_trig_req();
void dut_Not_1U_1U_4_12();
void thread_12();
};
#endif
|
#ifndef TESTBENCH_
#define TESTBENCH_
#include <systemc.h>
SC_MODULE (tbreg){
//l'horloge
sc_in <bool> clk;
sc_out < sc_uint<11> > din;
sc_in < sc_uint<15> > coded_dout;
sc_out < sc_uint<15> > coded_din;
sc_in < sc_uint<11> > dout;
//hand shake signals
sc_out < bool > din_vld;
sc_in < bool > din_rdy;
sc_in < bool > codedout_vld;
sc_out < bool > codedout_rdy;
sc_out < bool > codedin_vld;
sc_in < bool > codedin_rdy;
sc_in < bool > dout_vld;
sc_out < bool > dout_rdy;
void send();
void receive();
SC_CTOR(tbreg){
SC_CTHREAD(send,clk);
SC_CTHREAD(receive,clk);
sensitive << clk.pos();
}
};
#endif
|
#ifndef NEURON_H
#define NEURON_H
#include "systemc.h"
SC_MODULE(Neuron) {
sc_in<float> input1, input2;
sc_out<float> output;
float w1, w2, b, y;
float output_temp;
void neuron();
SC_CTOR(Neuron) {
SC_METHOD(neuron);
sensitive << input1 << input2;
}
};
#endif |
#include <systemc.h>
#ifndef ACC_H
#define ACC_H
//#define __SYNTHESIS__
//#define SYSC_ACC_DEBUG
//#define SYSC_ACC_DEBUG2
#ifndef __SYNTHESIS__
#define DWAIT(x) wait(x)
#else
#define DWAIT(x)
#endif
#define ACCNAME SA_INT8_V1_0
#define ACC_DTYPE sc_int
#define ACC_C_DTYPE int
#define MAX 2147483647
#define MIN -2147483648
#define POS 1073741824
#define NEG -1073741823
#define DIVMAX 2147483648
#define MAX8 127
#define MIN8 -128
typedef struct _DATA{
ACC_DTYPE<32> data;
bool tlast;
inline friend ostream& operator << (ostream& os, const _DATA &v){
cout << "data: " << v.data << " tlast: " << v.tlast;
return os;
}
} DATA;
typedef struct _HDATA{
bool rhs_take;
bool lhs_take;
sc_uint<8> rhs_count;
sc_uint<8> lhs_count;
sc_uint<16> dst_addr;
} HDATA;
typedef struct _ADATA{
ACC_DTYPE<32> d2;
ACC_DTYPE<32> d3;
ACC_DTYPE<32> d4;
ACC_DTYPE<32> d5;
ACC_DTYPE<32> d6;
ACC_DTYPE<32> d7;
ACC_DTYPE<32> d8;
ACC_DTYPE<32> d9;
ACC_DTYPE<32> d10;
ACC_DTYPE<32> d11;
ACC_DTYPE<32> d12;
ACC_DTYPE<32> d13;
ACC_DTYPE<32> d14;
ACC_DTYPE<32> d15;
ACC_DTYPE<32> d16;
ACC_DTYPE<32> d17;
inline friend ostream& operator << (ostream& os, const _ADATA &v){
return os;
}
} ADATA;
SC_MODULE(ACCNAME) {
//debug vars
bool print_po = false;
bool print_wo = false;
int simplecounter=0;
ACC_DTYPE<14> depth;
sc_in<bool> clock;
sc_in <bool> reset;
sc_fifo_in<DATA> din1;
sc_fifo_in<DATA> din2;
sc_fifo_in<DATA> din3;
sc_fifo_in<DATA> din4;
sc_fifo_out<DATA> dout1;
sc_fifo_out<DATA> dout2;
sc_fifo_out<DATA> dout3;
sc_fifo_out<DATA> dout4;
sc_signal<bool> read_inputs;
sc_signal<bool> rtake;
sc_signal<bool> ltake;
sc_signal<int> llen;
sc_signal<int> rlen;
sc_signal<int> lhs_block_max;
sc_signal<int> rhs_block_max;
#ifndef __SYNTHESIS__
sc_signal<bool,SC_MANY_WRITERS> d_in1;
sc_signal<bool,SC_MANY_WRITERS> d_in2;
sc_signal<bool,SC_MANY_WRITERS> d_in3;
sc_signal<bool,SC_MANY_WRITERS> d_in4;
sc_signal<bool,SC_MANY_WRITERS> schedule;
sc_signal<bool,SC_MANY_WRITERS> out_check;
sc_signal<bool,SC_MANY_WRITERS> gemm_unit_1_ready;
sc_signal<bool,SC_MANY_WRITERS> write1;
sc_signal<bool,SC_MANY_WRITERS> arrange1;
#else
sc_signal<bool> d_in1;
sc_signal<bool> d_in2;
sc_signal<bool> d_in3;
sc_signal<bool> d_in4;
sc_signal<bool> schedule;
sc_signal<bool> out_check;
sc_signal<bool> gemm_unit_1_ready;
sc_signal<bool> write1;
sc_signal<bool> arrange1;
#endif
sc_signal<int> gemm_unit_1_l_pointer;
sc_signal<bool> gemm_unit_1_iwuse;
ACC_DTYPE<32> g1 [256];
ACC_DTYPE<8> r1 [256];
//GEMM 1 Inputs
ACC_DTYPE<32> lhsdata1a[4096];
ACC_DTYPE<32> lhsdata2a[4096];
ACC_DTYPE<32> lhsdata3a[4096];
ACC_DTYPE<32> lhsdata4a[4096];
//Global Weights
ACC_DTYPE<32> rhsdata1[8192];
ACC_DTYPE<32> rhsdata2[8192];
ACC_DTYPE<32> rhsdata3[8192];
ACC_DTYPE<32> rhsdata4[8192];
// //new sums bram
// ACC_DTYPE<32> lhs_sum1[512];
// ACC_DTYPE<32> lhs_sum2[512];
// ACC_DTYPE<32> lhs_sum3[512];
// ACC_DTYPE<32> lhs_sum4[512];
//
// ACC_DTYPE<32> rhs_sum1[512];
// ACC_DTYPE<32> rhs_sum2[512];
// ACC_DTYPE<32> rhs_sum3[512];
// ACC_DTYPE<32> rhs_sum4[512];
//
// //crf & crx
// ACC_DTYPE<32> crf1[512];
// ACC_DTYPE<32> crf2[512];
// ACC_DTYPE<32> crf3[512];
// ACC_DTYPE<32> crf4[512];
// ACC_DTYPE<32> crx[512];
//new sums bram
ACC_DTYPE<32> lhs_sum1[1024];
ACC_DTYPE<32> lhs_sum2[1024];
ACC_DTYPE<32> lhs_sum3[1024];
ACC_DTYPE<32> lhs_sum4[1024];
ACC_DTYPE<32> rhs_sum1[1024];
ACC_DTYPE<32> rhs_sum2[1024];
ACC_DTYPE<32> rhs_sum3[1024];
ACC_DTYPE<32> rhs_sum4[1024];
//crf & crx
ACC_DTYPE<32> crf1[1024];
ACC_DTYPE<32> crf2[1024];
ACC_DTYPE<32> crf3[1024];
ACC_DTYPE<32> crf4[1024];
ACC_DTYPE<32> crx[1024];
int ra=0;
sc_fifo<int> WRQ1;
sc_fifo<int> WRQ2;
sc_fifo<int> WRQ3;
sc_fifo<char> sIs1;
sc_fifo<char> sIs2;
sc_fifo<char> sIs3;
sc_fifo<char> sIs4;
sc_fifo<char> sIs5;
sc_fifo<char> sIs6;
sc_fifo<char> sIs7;
sc_fifo<char> sIs8;
sc_fifo<char> sIs9;
sc_fifo<char> sIs10;
sc_fifo<char> sIs11;
sc_fifo<char> sIs12;
sc_fifo<char> sIs13;
sc_fifo<char> sIs14;
sc_fifo<char> sIs15;
sc_fifo<char> sIs16;
sc_fifo<char> sWs1;
sc_fifo<char> sWs2;
sc_fifo<char> sWs3;
sc_fifo<char> sWs4;
sc_fifo<char> sWs5;
sc_fifo<char> sWs6;
sc_fifo<char> sWs7;
sc_fifo<char> sWs8;
sc_fifo<char> sWs9;
sc_fifo<char> sWs10;
sc_fifo<char> sWs11;
sc_fifo<char> sWs12;
sc_fifo<char> sWs13;
sc_fifo<char> sWs14;
sc_fifo<char> sWs15;
sc_fifo<char> sWs16;
sc_signal<int> w1S;
sc_signal<int> w2S;
sc_signal<int> w3S;
sc_signal<int> w4S;
#ifndef __SYNTHESIS__
int weight_max_index=0;
int input_max_index=0;
int local_weight_max_index=0;
int g1_macs=0;
int g2_macs=0;
int g3_macs=0;
int g4_macs=0;
int g1_out_count=0;
int g2_out_count=0;
int g3_out_count=0;
int g4_out_count=0;
#endif
sc_out<int> inS;
sc_out<int> read_cycle_count;
sc_out<int> process_cycle_count;
sc_out<int> gemm_1_idle;
sc_out<int> gemm_2_idle;
sc_out<int> gemm_3_idle;
sc_out<int> gemm_4_idle;
sc_out<int> gemm_1_write;
sc_out<int> gemm_2_write;
sc_out<int> gemm_3_write;
sc_out<int> gemm_4_write;
sc_out<int> gemm_1;
sc_out<int> gemm_2;
sc_out<int> gemm_3;
sc_out<int> gemm_4;
sc_out<int> wstall_1;
sc_out<int> wstall_2;
sc_out<int> wstall_3;
sc_out<int> wstall_4;
sc_out<int> rmax;
sc_out<int> lmax;
sc_out<int> outS;
sc_out<int> w1SS;
sc_out<int> w2SS;
sc_out<int> w3SS;
sc_out<int> w4SS;
sc_out<int> schS;
sc_out<int> p1S;
void Input_Handler();
void Output_Handler();
void Worker1();
void Data_In1();
void Data_In2();
void Data_In3();
void Data_In4();
void Tracker();
void Scheduler();
void Post1();
void schedule_gemm_unit(int, int, int, int, int,int,int);
int SHR(int,int);
void Read_Cycle_Counter();
void Process_Cycle_Counter();
void Writer_Cycle_Counter();
SC_HAS_PROCESS(ACCNAME);
// Parameters for the DUT
ACCNAME(sc_module_name name_) :sc_module(name_),WRQ1(512),sIs1(2048),sIs2(2048),sIs3(2048),sIs4(2048),sIs5(2048),sIs6(2048),sIs7(2048),sIs8(2048),
sIs9(2048),sIs10(2048),sIs11(2048),sIs12(2048),sIs13(2048),sIs14(2048),sIs15(2048),sIs16(2048),
WRQ2(512),sWs1(2048),sWs2(2048),sWs3(2048),sWs4(2048),sWs5(2048),sWs6(2048),sWs7(2048),sWs8(2048),
sWs9(2048),sWs10(2048),sWs11(2048),sWs12(2048),sWs13(2048),sWs14(2048),sWs15(2048),sWs16(2048),WRQ3(512){
SC_CTHREAD(Input_Handler,clock.pos());
reset_signal_is(reset,true);
SC_CTHREAD(Worker1,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Output_Handler,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Data_In1,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Data_In2,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Data_In3,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Data_In4,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Scheduler,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Post1,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Read_Cycle_Counter,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Process_Cycle_Counter,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Writer_Cycle_Counter,clock);
reset_signal_is(reset,true);
#pragma HLS RESOURCE variable=din1 core=AXI4Stream metadata="-bus_bundle S_AXIS_DATA1" port_map={{din1_0 TDATA} {din1_1 TLAST}}
#pragma HLS RESOURCE variable=din2 core=AXI4Stream metadata="-bus_bundle S_AXIS_DATA2" port_map={{din2_0 TDATA} {din2_1 TLAST}}
#pragma HLS RESOURCE variable=din3 core=AXI4Stream metadata="-bus_bundle S_AXIS_DATA3" port_map={{din3_0 TDATA} {din3_1 TLAST}}
#pragma HLS RESOURCE variable=din4 core=AXI4Stream metadata="-bus_bundle S_AXIS_DATA4" port_map={{din4_0 TDATA} {din4_1 TLAST}}
#pragma HLS RESOURCE variable=dout1 core=AXI4Stream metadata="-bus_bundle M_AXIS_DATA1" port_map={{dout1_0 TDATA} {dout1_1 TLAST}}
#pragma HLS RESOURCE variable=dout2 core=AXI4Stream metadata="-bus_bundle M_AXIS_DATA2" port_map={{dout2_0 TDATA} {dout2_1 TLAST}}
#pragma HLS RESOURCE variable=dout3 core=AXI4Stream metadata="-bus_bundle M_AXIS_DATA3" port_map={{dout3_0 TDATA} {dout3_1 TLAST}}
#pragma HLS RESOURCE variable=dout4 core=AXI4Stream metadata="-bus_bundle M_AXIS_DATA4" port_map={{dout4_0 TDATA} {dout4_1 TLAST}}
#pragma HLS array_partition variable=g1 complete dim=0
#pragma HLS RESET variable=reset
}
};
#endif /* ACC_H */
|
/**
#define meta ...
prInt32f("%s\n", meta);
**/
/*
All rights reserved to Alireza Poshtkohi (c) 1999-2023.
Email: [email protected]
Website: http://www.poshtkohi.info
*/
#ifndef __s6_h__
#define __s6_h__
#include <systemc.h>
SC_MODULE(s6)
{
sc_in<sc_uint<6> > stage1_input;
sc_out<sc_uint<4> > stage1_output;
void s6_box();
SC_CTOR(s6)
{
SC_METHOD(s6_box);
sensitive << stage1_input;
}
};
#endif
|
/**********************************************************************
Filename: sc_fir8_tb.h
Purpose : Testbench of 8-Tab Systolic FIR filter
Author : [email protected]
History : Mar. 2024, First release
***********************************************************************/
#ifndef _SC_FIR8_TB_H_
#define _SC_FIR8_TB_H_
#include <systemc.h>
#include "sc_fir8.h"
SC_MODULE(sc_fir8_tb)
{
sc_clock clk;
sc_signal<sc_uint<8> > Xin;
sc_signal<sc_uint<8> > Xout;
sc_signal<sc_uint<16> > Yin;
sc_signal<sc_uint<16> > Yout;
#ifdef EMULATED
sc_signal<sc_uint<8> > E_Xout;
sc_signal<sc_uint<16> > E_Yout;
#endif
sc_fir8* u_sc_fir8;
// Test utilities
void Test_Gen();
void Test_Mon();
sc_uint<8> x[F_SAMPLE]; // Time seq. input
sc_uint<16> y[F_SAMPLE]; // Filter output
#ifdef VCD_TRACE_FIR8_TB
sc_trace_file* fp; // VCD file
#endif
SC_CTOR(sc_fir8_tb):
clk("clk", 100, SC_NS, 0.5, 0.0, SC_NS, false),
Xin("Xin"),
Xout("Xout"),
Yin("Yin"),
Yout("Yout")
{
SC_THREAD(Test_Gen);
sensitive << clk;
SC_THREAD(Test_Mon);
sensitive << clk;
// Instaltiate FIR8
u_sc_fir8 = new sc_fir8("u_sc_fir8");
u_sc_fir8->clk(clk);
u_sc_fir8->Xin(Xin);
u_sc_fir8->Xout(Xout);
u_sc_fir8->Yin(Yin);
u_sc_fir8->Yout(Yout);
#ifdef EMULATED
u_sc_fir8->E_Xout(E_Xout);
u_sc_fir8->E_Yout(E_Yout);
#endif
#ifdef VCD_TRACE_FIR8_TB
// WAVE
fp = sc_create_vcd_trace_file("sc_fir8_tb");
fp->set_time_unit(100, SC_PS); // resolution (trace) ps
sc_trace(fp, clk, "clk");
sc_trace(fp, Xin, "Xin");
sc_trace(fp, Xout, "Xout");
sc_trace(fp, Yin, "Yin");
sc_trace(fp, Yout, "Yout");
#endif
}
~sc_fir8_tb(void)
{
}
};
#endif |
/*******************************************************************************
* mux_in.cpp -- Copyright 2019 (c) Glenn Ramalho - RFIDo Design
*******************************************************************************
* Description:
* Model for the PCNT mux in the GPIO matrix.
*******************************************************************************
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
#include <systemc.h>
#include "info.h"
#include "mux_in.h"
void mux_in::mux(int gpiosel) {
if (gpiosel >= min_i.size()) {
PRINTF_WARN("MUXPCNT",
"Attempting to set GPIO Matrix to illegal pin %d.", gpiosel);
return;
}
function = gpiosel;
fchange_ev.notify();
}
void mux_in::transfer() {
bool nxval;
while(true) {
/* We simply copy the input onto the output. */
nxval = min_i[function]->read();
out_o.write(nxval);
if (debug) {
PRINTF_INFO("MUXIN", "mux_in %s is driving %c, function %d", name(),
(nxval)?'H':'L', function);
}
/* We wait for a function change or a signal change. */
wait(fchange_ev | min_i[function]->value_changed_event());
}
}
|
#include <systemc.h>
SC_MODULE(tb)
{
sc_in<bool> clk;
sc_out<bool> reset;
sc_out< sc_int<16> > input;
sc_out<bool> input_valid;
sc_in<bool> input_ready;
sc_in< sc_int<16> > output;
sc_in<bool> output_valid;
sc_out<bool> output_ready;
void source();
void sink();
SC_CTOR(tb){
SC_CTHREAD(source, clk.pos());
SC_CTHREAD(sink, clk.pos());
} |
#include "Neuron.h"
#include "systemc.h"
SC_MODULE(Neural_Network) {
sc_in<float> input1, input2;
sc_out<float> output;
sc_signal<float> c1, c2;
Neuron* N1;
Neuron* N2;
Neuron* N3;
SC_CTOR(Neural_Network) {
// vvvvv put your code here vvvvv
N1 = new Neuron("N1");
N2 = new Neuron("N2");
N3 = new Neuron("N3");
N1->input1(input1);
N1->input2(input2);
N1->output(c1);
N2->input1(input1);
N2->input2(input2);
N2->output(c2);
N3->input1(c1);
N3->input2(c2);
N3->output(output);
// ^^^^^ put your code here ^^^^^
N1->w1 = 10;
N1->w2 = -10;
N1->b = -5;
N2->w1 = -10;
N2->w2 = 10;
N2->b = -5;
N3->w1 = 10;
N3->w2 = 10;
N3->b = -5;
}
}; |
#include "systemc.h"
SC_MODULE(tb) {
sc_out < sc_uint<4> > OPa,OPb;
sc_out < sc_uint<4> > OP;
sc_in<bool> Clk;
void tbGen() {
OPa.write(0111);
OPb.write(0001);
OP.write(0);
wait(10,SC_NS);
OPa.write(0111);
OPb.write(0001);
OP.write(1);
wait(10,SC_NS);
OPa.write(0111);
OPb.write(0001);
OP.write(2);
wait(10,SC_NS);
OPa.write(0111);
OPb.write(0001);
OP.write(3);
wait(10,SC_NS);
OPa.write(0111);
OPb.write(0001);
OP.write(4);
wait(10,SC_NS);
OPa.write(0111);
OPb.write(0001);
OP.write(5);
wait(10,SC_NS);
sc_stop();
}
SC_CTOR(tb) {
SC_THREAD(tbGen);
}
};
|
// Generated by stratus_hls 17.20-p100 (88533.190925)
// Thu Nov 19 00:45:43 2020
// from dut.cc
#ifndef CYNTH_PART_dut_dut_rtl_h
#define CYNTH_PART_dut_dut_rtl_h
#include "systemc.h"
/* Include declarations of instantiated parts. */
#include "dut_Div_64Ux2U_32U_4.h"
/* Declaration of the synthesized module. */
struct dut : public sc_module {
sc_in<bool > clk;
sc_in<bool > rst;
sc_out<bool > din_busy;
sc_in<bool > din_vld;
sc_in<sc_uint<8> > din_data_a;
sc_in<sc_uint<8> > din_data_b;
sc_in<sc_uint<8> > din_data_c;
sc_in<sc_uint<8> > din_data_d;
sc_in<sc_uint<8> > din_data_e;
sc_in<sc_uint<8> > din_data_f;
sc_in<sc_uint<8> > din_data_g;
sc_in<sc_uint<8> > din_data_h;
sc_in<bool > dout_busy;
sc_out<bool > dout_vld;
sc_out<sc_uint<32> > dout_data;
dut( sc_module_name name );
SC_HAS_PROCESS(dut);
sc_signal<bool > dout_m_req_m_prev_trig_req;
sc_signal<sc_uint<1> > dut_Xor_1Ux1U_1U_4_14_out1;
sc_signal<bool > dout_m_unacked_req;
sc_signal<sc_uint<1> > dut_Or_1Ux1U_1U_4_15_out1;
sc_signal<sc_uint<1> > dut_And_1Ux1U_1U_4_12_out1;
sc_signal<sc_uint<1> > dut_And_1Ux1U_1U_4_10_out1;
sc_signal<sc_uint<1> > dut_Not_1U_1U_4_9_out1;
sc_signal<sc_uint<1> > dut_And_1Ux1U_1U_4_11_out1;
sc_signal<sc_uint<1> > dut_N_Muxb_1_2_1_4_1_out1;
sc_signal<sc_uint<1> > dut_And_1Ux1U_1U_4_5_out1;
sc_signal<sc_uint<1> > dut_Not_1U_1U_4_4_out1;
sc_signal<sc_uint<1> > dut_And_1Ux1U_1U_4_3_out1;
sc_signal<sc_uint<1> > dut_Or_1Ux1U_1U_4_2_out1;
sc_signal<bool > din_m_unvalidated_req;
sc_signal<sc_uint<1> > dut_Or_1Ux1U_1U_4_7_out1;
sc_signal<sc_uint<2> > global_state_next;
sc_signal<sc_uint<1> > cycle2_state;
sc_signal<sc_uint<32> > dut_Mul_32Ux9U_32U_4_42_out1;
sc_signal<sc_uint<9> > dut_Add_8Ux8U_9U_4_40_out1;
sc_signal<sc_uint<17> > dut_Add_32Ux17U_33U_1_36_in1;
sc_signal<sc_uint<32> > dut_Add_32Ux17U_33U_1_36_in2;
sc_signal<sc_uint<32> > dut_Mul_32Ux9U_32U_4_35_out1;
sc_signal<sc_uint<8> > dut_Mul_32Ux9U_32U_4_35_in1_slice;
sc_signal<sc_uint<29> > dut_Mul_32Ux9U_32U_4_35_in2_slice;
sc_signal<sc_uint<16> > dut_Mul_8Ux8U_16U_4_34_out1;
sc_signal<sc_uint<8> > dut_Mul_8Ux8U_16U_4_34_in1;
sc_signal<sc_uint<8> > dut_Mul_8Ux8U_16U_4_34_in2;
sc_signal<sc_uint<32> > dut_Mul_33Ux32U_64U_4_33_in1;
sc_signal<sc_uint<32> > dut_Add_32Ux32U_32U_4_44_out1;
sc_signal<sc_uint<33> > dut_Mul_33Ux32U_64U_4_33_in2;
sc_signal<sc_uint<33> > dut_Add_32Ux16U_33U_4_45_out1;
sc_signal<sc_uint<32> > dut_Mul_32Ux10U_32U_4_32_out1;
sc_signal<sc_uint<10> > dut_Mul_32Ux10U_32U_4_32_in1;
sc_signal<sc_uint<9> > dut_Add_8Ux8U_9U_4_39_out1;
sc_signal<sc_uint<29> > dut_Mul_32Ux10U_32U_4_32_in2_slice;
sc_signal<sc_uint<1> > gs_ctrl0;
sc_signal<sc_uint<9> > dut_Add_8Ux8U_9U_4_31_out1;
sc_signal<sc_uint<10> > dut_Add_9Ux8U_10U_4_30_out1;
sc_signal<sc_uint<10> > dut_Add_9Ux8U_10U_4_29_out1;
sc_signal<sc_uint<8> > din_m_stall_reg_h;
sc_signal<sc_uint<8> > din_m_stall_reg_g;
sc_signal<sc_uint<9> > dut_Add_8Ux8U_9U_4_26_out1;
sc_signal<sc_uint<9> > dut_Add_8Ux8U_9U_4_25_out1;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_24_out1;
sc_signal<sc_uint<8> > din_m_stall_reg_f;
sc_signal<sc_uint<8> > din_m_stall_reg_c;
sc_signal<sc_uint<8> > din_m_stall_reg_e;
sc_signal<sc_uint<8> > din_m_stall_reg_d;
sc_signal<sc_uint<8> > din_m_stall_reg_b;
sc_signal<bool > din_m_stall_reg_full;
sc_signal<sc_uint<8> > din_m_stall_reg_a;
sc_signal<sc_uint<33> > dut_Add_32Ux17U_33U_1_36_out1;
sc_signal<sc_uint<17> > s_reg_22;
sc_signal<sc_uint<64> > dut_Mul_33Ux32U_64U_4_33_out1;
sc_signal<sc_uint<29> > s_reg_21_slice11;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_28_out1;
sc_signal<sc_uint<8> > s_reg_20;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_27_out1;
sc_signal<sc_uint<8> > s_reg_19;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_23_out1;
sc_signal<sc_uint<8> > s_reg_18;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_22_out1;
sc_signal<sc_uint<8> > s_reg_17;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_21_out1;
sc_signal<sc_uint<8> > s_reg_16;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_20_out1;
sc_signal<sc_uint<8> > s_reg_15;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_19_out1;
sc_signal<sc_uint<8> > s_reg_14;
sc_signal<sc_uint<1> > dut_Or_1Ux1U_1U_4_6_out1;
sc_signal<sc_uint<1> > s_reg_13_stage1;
sc_signal<sc_uint<1> > cycle6_state;
sc_signal<sc_uint<1> > dut_And_1Ux1U_1U_4_16_out1;
sc_signal<sc_uint<1> > dut_Not_1U_1U_4_17_out1;
sc_signal<sc_uint<1> > cycle4_state;
sc_signal<sc_uint<1> > s_reg_13;
sc_signal<bool > dout_m_req_m_trig_req;
sc_signal<sc_uint<2> > global_state;
sc_signal<bool > din_m_busy_req_0;
sc_signal<sc_uint<64> > s_reg_21_stage1;
sc_signal<sc_uint<2> > dut_Div_64Ux2U_32U_4_47_in1;
sc_signal<sc_uint<32> > dut_Div_64Ux2U_32U_4_47_out1;
sc_signal<sc_uint<1> > stall0;
dut_Div_64Ux2U_32U_4 *dut_Div_64Ux2U_32U_4_47;
void drive_dout_data();
void drive_din_m_busy_req_0();
void drive_dout_m_req_m_trig_req();
void drive_stall0();
void drive_s_reg_13();
void drive_s_reg_14();
void drive_s_reg_15();
void drive_s_reg_16();
void drive_s_reg_17();
void drive_s_reg_18();
void drive_s_reg_19();
void drive_s_reg_20();
void drive_s_reg_21();
void drive_s_reg_22();
void dut_N_Mux_8_2_0_4_19();
void dut_N_Mux_8_2_0_4_20();
void dut_N_Mux_8_2_0_4_21();
void dut_N_Mux_8_2_0_4_22();
void dut_N_Mux_8_2_0_4_23();
void dut_N_Mux_8_2_0_4_24();
void dut_Add_8Ux8U_9U_4_25();
void dut_Add_8Ux8U_9U_4_26();
void dut_N_Mux_8_2_0_4_27();
void dut_N_Mux_8_2_0_4_28();
void dut_Add_9Ux8U_10U_4_29();
void dut_Add_9Ux8U_10U_4_30();
void dut_Add_8Ux8U_9U_4_31();
void drive_dut_Mul_32Ux10U_32U_4_32_in2();
void drive_dut_Mul_32Ux10U_32U_4_32_in1();
void dut_Mul_32Ux10U_32U_4_32();
void drive_dut_Mul_33Ux32U_64U_4_33_in2();
void drive_dut_Mul_33Ux32U_64U_4_33_in1();
void dut_Mul_33Ux32U_64U_4_33();
void drive_dut_Mul_8Ux8U_16U_4_34_in2();
void drive_dut_Mul_8Ux8U_16U_4_34_in1();
void dut_Mul_8Ux8U_16U_4_34();
void drive_dut_Mul_32Ux9U_32U_4_35_in2();
void drive_dut_Mul_32Ux9U_32U_4_35_in1();
void dut_Mul_32Ux9U_32U_4_35();
void drive_dut_Add_32Ux17U_33U_1_36_in2();
void drive_dut_Add_32Ux17U_33U_1_36_in1();
void dut_Add_32Ux17U_33U_1_36();
void dut_Add_8Ux8U_9U_4_39();
void dut_Add_8Ux8U_9U_4_40();
void dut_Mul_32Ux9U_32U_4_42();
void dut_Add_32Ux32U_32U_4_44();
void dut_Add_32Ux16U_33U_4_45();
void drive_dut_Div_64Ux2U_32U_4_47_in1();
void drive_s_reg_13_stage1();
void drive_s_reg_21_stage1();
void drive_cycle2_state();
void drive_cycle4_state();
void drive_cycle6_state();
void drive_global_state();
void drive_global_state_next();
void drive_gs_ctrl0();
void drive_din_busy();
void dut_Or_1Ux1U_1U_4_2();
void dut_And_1Ux1U_1U_4_3();
void dut_Not_1U_1U_4_4();
void dut_And_1Ux1U_1U_4_5();
void dut_Or_1Ux1U_1U_4_6();
void dut_Or_1Ux1U_1U_4_7();
void drive_din_m_unvalidated_req();
void dut_N_Muxb_1_2_1_4_1();
void drive_din_m_stall_reg_h();
void drive_din_m_stall_reg_g();
void drive_din_m_stall_reg_f();
void drive_din_m_stall_reg_e();
void drive_din_m_stall_reg_d();
void drive_din_m_stall_reg_c();
void drive_din_m_stall_reg_b();
void drive_din_m_stall_reg_a();
void dut_Not_1U_1U_4_9();
void dut_And_1Ux1U_1U_4_10();
void dut_And_1Ux1U_1U_4_11();
void drive_din_m_stall_reg_full();
void dut_And_1Ux1U_1U_4_12();
void drive_dout_vld();
void dut_Or_1Ux1U_1U_4_15();
void drive_dout_m_unacked_req();
void dut_And_1Ux1U_1U_4_16();
void dut_Xor_1Ux1U_1U_4_14();
void drive_dout_m_req_m_prev_trig_req();
void dut_Not_1U_1U_4_17();
};
#endif
|
/****************************************************************************
*
* Copyright (c) 2015, Cadence Design Systems. All Rights Reserved.
*
* This file contains confidential information that may not be
* distributed under any circumstances without the written permision
* of Cadence Design Systems.
*
***************************************************************************/
#ifndef _DUT_CYCSIM_INCLUDED_
#define _DUT_CYCSIM_INCLUDED_
#include "systemc.h"
#include "cynthhl.h"
SC_MODULE(dut_cycsim)
{
// Port declarations.
sc_in< bool > clk;
sc_in< bool > rst;
sc_out< bool > din_busy;
sc_in< bool > din_vld;
sc_in< sc_uint< 8 > > din_data_a;
sc_in< sc_uint< 8 > > din_data_b;
sc_in< sc_uint< 8 > > din_data_c;
sc_in< sc_uint< 8 > > din_data_d;
sc_in< sc_uint< 8 > > din_data_e;
sc_in< sc_uint< 8 > > din_data_f;
sc_in< sc_uint< 8 > > din_data_g;
sc_in< sc_uint< 8 > > din_data_h;
sc_in< bool > dout_busy;
sc_out< bool > dout_vld;
sc_out< sc_uint< 32 > > dout_data;
dut_cycsim( sc_module_name in_name=sc_module_name(sc_gen_unique_name(" dut") ) )
: sc_module(in_name)
,clk("clk")
,rst("rst")
,din_busy("din_busy")
,din_vld("din_vld")
,din_data_a("din_data_a"),
din_data_b("din_data_b"),
din_data_c("din_data_c"),
din_data_d("din_data_d"),
din_data_e("din_data_e"),
din_data_f("din_data_f"),
din_data_g("din_data_g"),
din_data_h("din_data_h")
,dout_busy("dout_busy")
,dout_vld("dout_vld")
,dout_data("dout_data")
{
};
};
#endif
|
#include <memory>
#include <systemc.h>
#include "Vtop.h"
#include "bfm.h"
SC_MODULE(sc_top) {
sc_clock clk;
sc_signal<bool> reset;
sc_signal<bool> cs;
sc_signal<bool> rw;
sc_signal<bool> ready;
#ifdef VERILATOR
sc_signal<uint32_t> addr;
sc_signal<uint32_t> data_in;
sc_signal<uint32_t> data_out;
#else
sc_signal<sc_uint<16>> addr;
sc_signal<sc_uint<32>> data_in;
sc_signal<sc_uint<32>> data_out;
#endif
Vtop *u_top;
bfm *u_bfm;
SC_CTOR(sc_top) :
clk("clk", 10, SC_NS, 0.5, 5, SC_NS, true),
reset("reset"), cs("cs"), rw("rw"), addr("addr"), ready("ready"), data_in("data_in"), data_out("data_out") {
#ifdef VERILATOR
u_top = new Vtop{"top"};
#else
u_top = new Vtop{"top", "Vtop", 0, NULL};
#endif
u_top->clk(clk);
u_top->reset(reset);
u_top->cs(cs);
u_top->rw(rw);
u_top->addr(addr);
u_top->data_in(data_in);
u_top->ready(ready);
u_top->data_out(data_out);
u_bfm = new bfm("bfm");
u_bfm->clk(clk);
u_bfm->reset(reset);
u_bfm->cs(cs);
u_bfm->rw(rw);
u_bfm->addr(addr);
u_bfm->data_in(data_out);
u_bfm->ready(ready);
u_bfm->data_out(data_in);
}
~sc_top() {
#ifdef VERILATOR
u_top->final();
#endif
delete u_top;
delete u_bfm;
}
};
|
/**********************************************************************
Filename: sc_fir_pe.h
Purpose : Verilated PE of Systolic FIR filter
Author : [email protected]
History : Mar. 2024, First release
***********************************************************************/
#ifndef _V_FIR_PE_H_
#define _V_FIR_PE_H_
#include <systemc.h>
#include "./obj_dir/Vfir_pe.h"
SC_MODULE(V_fir_pe)
{
sc_in<bool> clk;
sc_in<bool> Rdy;
sc_out<bool> Vld;
sc_in<sc_uint<6> > Cin;
sc_in<sc_uint<4> > Xin;
sc_out<sc_uint<4> > Xout;
sc_in<sc_uint<4> > Yin;
sc_out<sc_uint<4> > Yout;
Vfir_pe* u_Vfir_pe;
sc_signal<uint32_t> _Cin;
sc_signal<uint32_t> _Xin;
sc_signal<uint32_t> _Xout;
sc_signal<uint32_t> _Yin;
sc_signal<uint32_t> _Yout;
sc_signal<bool> _Rdy;
sc_signal<bool> _Vld;
void pe_method(void)
{
_Cin = (uint32_t)Cin.read();
_Xin = (uint32_t)Xin.read();
_Yin = (uint32_t)Yin.read();
_Rdy = Rdy.read();
Xout.write(sc_uint<4>(_Xout));
Yout.write(sc_uint<4>(_Yout));
Vld.write(_Vld);
}
SC_CTOR(V_fir_pe):
clk("clk"),
Rdy("Rdy"), _Rdy("_Rdy"),
Vld("Vld"), _Vld("_Vld"),
Cin("Cin"), _Cin("_Cin"),
Xin("Xin"), _Xin("_Xin"),
Xout("Xout"), _Xout("_Xout"),
Yin("Yin"), _Yin("_Yin"),
Yout("Yout"), _Yout("_Yout")
{
SC_METHOD(pe_method);
sensitive << clk << Cin << Xin << Yin << Rdy;
// Instantiate Verilated PE
u_Vfir_pe = new Vfir_pe("u_Vfir_pe");
u_Vfir_pe->clk(clk);
u_Vfir_pe->Cin(_Cin);
u_Vfir_pe->Xin(_Xin);
u_Vfir_pe->Xout(_Xout);
u_Vfir_pe->Yin(_Yin);
u_Vfir_pe->Yout(_Yout);
u_Vfir_pe->Rdy(_Rdy);
u_Vfir_pe->Vld(_Vld);
}
~V_fir_pe(void)
{
}
};
#endif
|
/******************************************************************************
* (C) Copyright 2014 AMIQ Consulting
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* NAME: amiq_eth.h
* PROJECT: amiq_eth
* Description: This file includes all the C++ files which are part of
* amiq_eth package.
*******************************************************************************/
#ifndef __AMIQ_ETH
//protection against multiple includes
#define __AMIQ_ETH
#include <systemc.h>
#include "sysc/utils/sc_report.h"
#include "amiq_eth_defines.cpp"
#include "amiq_eth_ethernet_protocols.cpp"
#include "amiq_eth_packer.cpp"
#include "amiq_eth_types.cpp"
#include "amiq_eth_packet.cpp"
#include "amiq_eth_packet_ether_type.cpp"
#include "amiq_eth_packet_length.cpp"
#include "amiq_eth_packet_pause.cpp"
#include "amiq_eth_packet_pfc_pause.cpp"
#include "amiq_eth_packet_snap.cpp"
#include "amiq_eth_packet_jumbo.cpp"
#include "amiq_eth_packet_magic.cpp"
#include "amiq_eth_packet_ethernet_configuration_testing.cpp"
#include "amiq_eth_packet_ipv4.cpp"
#include "amiq_eth_packet_hsr_base.cpp"
#include "amiq_eth_packet_hsr_standard.cpp"
#include "amiq_eth_packet_fcoe.cpp"
#include "amiq_eth_packet_arp.cpp"
#include "amiq_eth_packet_ptp.cpp"
#endif
|
/*
* Created on: 21. jun. 2019
* Author: Jonathan Horsted Schougaard
*/
#pragma once
#define SC_INCLUDE_FX
#include "hwcore/cnn/data_buffer.h"
#include "hwcore/cnn/pe.h"
#include "hwcore/cnn/top_cnn.h"
#include "hwcore/cnn/weight_buffer.h"
#include "hwcore/hw/statusreg.h"
#include "hwcore/pipes/pipes.h"
#include <systemc.h>
#ifdef __RTL_SIMULATION__
#include "syn/systemc/cnn.h"
#endif
#ifndef P_data_P
#define P_data_P 2
#warning Using defualt parameter!
#endif
#ifndef P_data_W
#define P_data_W 16
#warning Using defualt parameter!
#endif
#ifndef P_input_width
#define P_input_width 128
#warning Using defualt parameter!
#endif
#ifndef P_output_width
#define P_output_width 128
#warning Using defualt parameter!
#endif
// calculatd parameter
#define P_input_BW_N (P_input_width / P_data_W)
#define P_output_BW_N (P_output_width / P_data_W)
// end
#ifndef P_pe_n
#define P_pe_n 8
#warning Using defualt parameter!
#endif
#ifndef P_pe_bw_n
#define P_pe_bw_n P_input_BW_N
#warning Using defualt parameter!
#endif
#ifndef P_wbuf_size
#define P_wbuf_size 3072
#warning Using defualt parameter!
#endif
#ifndef P_data_buf_clb_size
#define P_data_buf_clb_size 8192
#warning Using defualt parameter!
#endif
#ifndef P_data_buf_clb_n
#define P_data_buf_clb_n 3
#warning Using defualt parameter!
#endif
#ifndef P_data_buf_shift_size
#define P_data_buf_shift_size 384
#warning Using defualt parameter!
#endif
#ifndef P_data_out_n
#define P_data_out_n 1
#warning Using defualt parameter!
#endif
#ifndef P_pool_size
#define P_pool_size 1024
#warning Using defualt parameter!
#endif
#if P_pool_size < 512
#error bad pool size!!!
#endif
#ifndef P_PE_pipeline_II
#define P_PE_pipeline_II 1
#warning Using defualt parameter!
#endif
#ifndef P_pe_pre_fifo_deep
#define P_pe_pre_fifo_deep 1
#warning Using defualt parameter!
#endif
#ifndef P_X_fifo_deep
#define P_X_fifo_deep 1
#warning Using defualt parameter!
#endif
#ifndef P_W_fifo_deep
#define P_W_fifo_deep 1
#warning Using defualt parameter!
#endif
#ifndef P_Y_fifo_deep
#define P_Y_fifo_deep 1
#warning Using defualt parameter!
#endif
#ifndef P_BUF_fifo_deep
#define P_BUF_fifo_deep 1
#warning Using defualt parameter!
#endif
SC_MODULE(cnn) {
// typedef
typedef hwcore::cnn::top_cnn<P_data_W, P_data_P, P_input_BW_N, P_output_BW_N, P_pe_n, P_pe_bw_n, P_wbuf_size,
P_data_buf_clb_size, P_data_buf_clb_n, P_data_buf_shift_size, P_data_out_n,
P_pool_size, P_PE_pipeline_II, P_pe_pre_fifo_deep>
top_cnn_t;
// interface
SC_MODULE_CLK_RESET_SIGNAL;
sc_fifo_in<hwcore::pipes::SC_DATA_T(P_input_width)> data_sink;
sc_fifo_in<hwcore::pipes::SC_DATA_T(P_input_width)> data_buf_sink;
sc_fifo_in<hwcore::pipes::SC_DATA_T(P_input_width)> w_sink;
sc_fifo_in<hwcore::pipes::SC_DATA_T(64)> ctrl_sink;
sc_fifo_out<hwcore::pipes::SC_DATA_T(P_output_width)> data_source;
#if __RTL_SIMULATION__
sc_status_module_create_interface_only(reg1);
ap_rtl::cnn rtl_wrapper_cnn;
SC_FIFO_IN_TRANS<P_input_width> data_sink_trans;
SC_FIFO_IN_TRANS<P_input_width> data_buf_sink_trans;
SC_FIFO_IN_TRANS<P_input_width> w_sink_trans;
SC_FIFO_IN_TRANS<64> ctrl_sink_trans;
SC_FIFO_OUT_TRANS<P_output_width> data_source_trans;
sc_signal<sc_logic> reset_s;
sc_signal<sc_lv<32> > status_add_s;
sc_signal<sc_lv<32> > status_val_s;
void signal_connection() {
sc_dt::sc_logic reset_tmp = (sc_dt::sc_logic)reset.read();
reset_s.write(reset_tmp);
status_add_s.write(status_add.read());
status_val.write(status_val_s.read().to_int());
}
SC_CTOR(cnn)
: rtl_wrapper_cnn("rtl_wrapper_cnn"), data_sink_trans("data_sink_trans"),
data_buf_sink_trans("data_buf_sink_trans"), data_source_trans("data_source_trans"),
w_sink_trans("w_sink_trans"), ctrl_sink_trans("ctrl_sink_trans") {
// SC_MODULE_LINK(rtl_wrapper_cnn);
SC_FIFO_IN_TRANS_CONNECT(rtl_wrapper_cnn, data_sink_trans, data_sink);
SC_FIFO_IN_TRANS_CONNECT(rtl_wrapper_cnn, data_buf_sink_trans, data_buf_sink);
SC_FIFO_IN_TRANS_CONNECT(rtl_wrapper_cnn, w_sink_trans, w_sink);
SC_FIFO_IN_TRANS_CONNECT(rtl_wrapper_cnn, ctrl_sink_trans, ctrl_sink);
SC_FIFO_OUT_TRANS_CONNECT(rtl_wrapper_cnn, data_source_trans, data_source);
rtl_wrapper_cnn.clk(clk);
rtl_wrapper_cnn.reset(reset_s);
rtl_wrapper_cnn.status_add(status_add_s);
rtl_wrapper_cnn.status_val(status_val_s);
SC_METHOD(signal_connection);
sensitive << status_add << status_val_s << reset;
}
#else
sc_status_module_create(reg1);
sc_status_reg_create(r0_dma_ingress);
sc_status_reg_create(r1_dma_egress);
sc_status_reg_create(r2_data_W);
sc_status_reg_create(r3_data_P);
sc_status_reg_create(r4_input_BW_N);
sc_status_reg_create(r5_output_BW_N);
sc_status_reg_create(r6_pe_n);
sc_status_reg_create(r7_pe_bw_n);
sc_status_reg_create(r8_wbuf_size);
sc_status_reg_create(r9_data_buf_clb_size);
sc_status_reg_create(r10_data_buf_clb_n);
sc_status_reg_create(r11_data_buf_shift_size);
sc_status_reg_create(r12_data_out_n);
sc_status_end_create(regend);
void status_reg_param_link() {
r2_data_W_status.write(P_data_W);
r3_data_P_status.write(P_data_P);
r4_input_BW_N_status.write(P_input_BW_N);
r5_output_BW_N_status.write(P_pool_size);
r6_pe_n_status.write(P_pe_n);
r7_pe_bw_n_status.write(P_pe_bw_n);
r8_wbuf_size_status.write(P_wbuf_size);
r9_data_buf_clb_size_status.write(P_data_buf_clb_size);
r10_data_buf_clb_n_status.write(P_data_buf_clb_n);
r11_data_buf_shift_size_status.write(P_data_buf_shift_size);
r12_data_out_n_status.write(P_data_out_n);
}
sc_fifo<hwcore::pipes::SC_DATA_T(P_input_width)> data_sink_forward;
sc_fifo<hwcore::pipes::SC_DATA_T(P_input_width)> data_buf_sink_forward;
sc_fifo<hwcore::pipes::SC_DATA_T(P_input_width)> w_sink_forward;
sc_fifo<hwcore::pipes::SC_DATA_T(P_output_width)> data_source_forward;
sc_fifo<sc_uint<31> > weight_ctrls_fifo;
sc_fifo<sc_uint<32> > ctrl_image_size_fifo;
sc_fifo<sc_uint<16> > ctrl_row_size_pkg_fifo;
sc_fifo<sc_uint<16> > ctrl_window_size_fifo;
sc_fifo<sc_uint<16> > ctrl_depth_fifo;
sc_fifo<sc_uint<16> > ctrl_stride_fifo;
sc_fifo<sc_uint<16> > ctrl_replay_fifo;
sc_fifo<sc_uint<16> > ctrl_zeropad_fifo;
sc_fifo<sc_uint<1> > ctrl_output_channel_fifo;
sc_fifo<sc_uint<16> > ctrl_stitch_depth_fifo;
sc_fifo<sc_uint<16> > ctrl_stitch_buf_depth_fifo;
sc_fifo<sc_uint<1> > ctrl_db_output_fifo;
sc_fifo<sc_uint<1> > ctrl_image_data_fifo;
sc_fifo<sc_uint<16> > ctrl_pool_depth_fifo;
sc_fifo<sc_uint<16> > ctrl_pool_type_fifo;
sc_fifo<sc_uint<16> > ctrl_pool_N_fifo;
sc_fifo<sc_uint<16> > ctrl_pool_size_fifo;
sc_fifo<sc_uint<16> > ctrl_row_N_fifo;
sc_fifo<sc_uint<16> > ctrl_acf_fifo;
// modules
hwcore::cnn::top_cnn<P_data_W, P_data_P, P_input_BW_N, P_output_BW_N, P_pe_n, P_pe_bw_n, P_wbuf_size,
P_data_buf_clb_size, P_data_buf_clb_n, P_data_buf_shift_size, P_data_out_n>
top_cnn;
sc_status_reg_create_dummy(top_cnn_reg);
SC_CTOR(cnn)
: data_sink_forward(P_X_fifo_deep), data_buf_sink_forward(P_BUF_fifo_deep), w_sink_forward(P_W_fifo_deep),
data_source_forward(P_Y_fifo_deep), weight_ctrls_fifo(16), ctrl_row_size_pkg_fifo(16),
ctrl_window_size_fifo(16), ctrl_depth_fifo(16), ctrl_stride_fifo(16), ctrl_replay_fifo(16),
ctrl_row_N_fifo(16), ctrl_acf_fifo(16), ctrl_zeropad_fifo(16), SC_INST(top_cnn), SC_INST(reg1),
SC_INST(regend), SC_INST(r0_dma_ingress), SC_INST(r1_dma_egress), SC_INST(r2_data_W), SC_INST(r3_data_P),
SC_INST(r4_input_BW_N), SC_INST(r5_output_BW_N), SC_INST(r6_pe_n), SC_INST(r7_pe_bw_n), SC_INST(r8_wbuf_size),
SC_INST(r9_data_buf_clb_size), SC_INST(r10_data_buf_clb_n), SC_INST(r11_data_buf_shift_size),
SC_INST(r12_data_out_n), ctrl_output_channel_fifo(16), ctrl_db_output_fifo(16), ctrl_pool_depth_fifo(16),
ctrl_pool_type_fifo(16), ctrl_pool_N_fifo(16), ctrl_pool_size_fifo(16), ctrl_stitch_depth_fifo(16),
ctrl_stitch_buf_depth_fifo(1), ctrl_image_data_fifo(16)
{
top_cnn.clk(clk);
top_cnn.reset(reset);
/*SC_METHOD(reset_logic);
sensitive << reset << iclear;
SC_CTHREAD(clear_reg, clk.pos());*/
top_cnn.data_sink(data_sink_forward);
top_cnn.data_buf_sink(data_buf_sink_forward);
top_cnn.w_sink(w_sink_forward);
top_cnn.data_source(data_source_forward);
top_cnn.weight_ctrls_in(weight_ctrls_fifo);
// top_cnn.data_ctrls_in(data_ctrls_fifo);
top_cnn.ctrl_row_N(ctrl_row_N_fifo);
top_cnn.ctrl_row_size_pkg(ctrl_row_size_pkg_fifo);
top_cnn.ctrl_window_size(ctrl_window_size_fifo);
top_cnn.ctrl_depth(ctrl_depth_fifo);
top_cnn.ctrl_stride(ctrl_stride_fifo);
top_cnn.ctrl_replay(ctrl_replay_fifo);
top_cnn.ctrl_image_size(ctrl_image_size_fifo);
top_cnn.ctrl_acf(ctrl_acf_fifo);
top_cnn.ctrl_zeropad(ctrl_zeropad_fifo);
top_cnn.ctrl_output_channel(ctrl_output_channel_fifo);
top_cnn.ctrl_stitch_depth(ctrl_stitch_depth_fifo);
top_cnn.ctrl_stitch_buf_depth(ctrl_stitch_buf_depth_fifo);
top_cnn.ctrl_db_output(ctrl_db_output_fifo);
top_cnn.ctrl_image_data(ctrl_image_data_fifo);
top_cnn.ctrl_pool_depth(ctrl_pool_depth_fifo);
top_cnn.ctrl_pool_type(ctrl_pool_type_fifo);
top_cnn.ctrl_pool_N(ctrl_pool_N_fifo);
top_cnn.ctrl_pool_size(ctrl_pool_size_fifo);
// status reg
sc_status_module_connect(reg1);
sc_status_reg_connect(r0_dma_ingress, reg1);
sc_status_reg_connect(r1_dma_egress, r0_dma_ingress);
sc_status_reg_connect(r2_data_W, r1_dma_egress);
sc_status_reg_connect(r3_data_P, r2_data_W);
sc_status_reg_connect(r4_input_BW_N, r3_data_P);
sc_status_reg_connect(r5_output_BW_N, r4_input_BW_N);
sc_status_reg_connect(r6_pe_n, r5_output_BW_N);
sc_status_reg_connect(r7_pe_bw_n, r6_pe_n);
sc_status_reg_connect(r8_wbuf_size, r7_pe_bw_n);
sc_status_reg_connect(r9_data_buf_clb_size, r8_wbuf_size);
sc_status_reg_connect(r10_data_buf_clb_n, r9_data_buf_clb_size);
sc_status_reg_connect(r11_data_buf_shift_size, r10_data_buf_clb_n);
sc_status_reg_connect(r12_data_out_n, r11_data_buf_shift_size);
sc_status_end_connect(regend, r12_data_out_n);
SC_CTHREAD(thread_cnn_stream_source, clk.pos());
reset_signal_is(reset, true);
SC_CTHREAD(thread_cnn_stream_sink, clk.pos());
reset_signal_is(reset, true);
SC_CTHREAD(thread_cnn_stream_buf_sink, clk.pos());
reset_signal_is(reset, true);
SC_CTHREAD(thread_cnn_stream_w_sink, clk.pos());
reset_signal_is(reset, true);
SC_CTHREAD(thread_cnn_ctrl, clk.pos());
reset_signal_is(reset, true);
}
void thread_cnn_stream_source() {
SC_STREAM_INTERFACE_CREATE_SOURCE(data_source, "-bus_bundle M_AXIS_Y")
int count = 0;
while (true) {
hls_pipeline(1);
hwcore::pipes::SC_DATA_T(P_output_width) tmp_out = data_source_forward.read();
data_source.write(tmp_out);
count++;
r0_dma_ingress_status.write(count);
}
}
void thread_cnn_stream_sink() {
SC_STREAM_INTERFACE_CREATE_SINK(data_sink, "-bus_bundle S_AXIS_X")
int count = 0;
while (true) {
hls_pipeline(1);
hwcore::pipes::SC_DATA_T(P_input_width) tmp_in = data_sink.read();
data_sink_forward.write(tmp_in);
count++;
r1_dma_egress_status.write(count);
}
}
void thread_cnn_stream_buf_sink() {
SC_STREAM_INTERFACE_CREATE_SINK(data_buf_sink, "-bus_bundle S_AXIS_BUF")
while (true) {
hls_pipeline(1);
hwcore::pipes::SC_DATA_T(P_input_width) tmp_in = data_buf_sink.read();
data_buf_sink_forward.write(tmp_in);
}
}
void thread_cnn_stream_w_sink() {
SC_STREAM_INTERFACE_CREATE_SINK(w_sink, "-bus_bundle S_AXIS_W")
while (true) {
hls_pipeline(1);
hwcore::pipes::SC_DATA_T(P_input_width) tmp_in = w_sink.read();
w_sink_forward.write(tmp_in);
}
}
void thread_cnn_ctrl() {
SC_STREAM_INTERFACE_CREATE_SINK(ctrl_sink, "-bus_bundle S_AXIS_CTRL")
hwcore::pipes::SC_DATA_T(64) tmp_in;
status_reg_param_link();
while (true) {
do {
hls_pipeline(1);
tmp_in = ctrl_sink.read();
sc_uint<64> raw = tmp_in.data;
sc_uint<56> value = raw(56 - 1, 0);
sc_uint<8> address;
if (tmp_in.tkeep == 0) {
address = -1;
} else {
address = raw(64 - 1, 56);
}
#define add_new_reg_interface(name_, nr_) \
case nr_: \
name_##_fifo.write(value); \
break;
switch (address) {
add_new_reg_interface(weight_ctrls, 0);
add_new_reg_interface(ctrl_row_N, 1);
add_new_reg_interface(ctrl_row_size_pkg, 2);
add_new_reg_interface(ctrl_window_size, 3);
add_new_reg_interface(ctrl_depth, 4);
add_new_reg_interface(ctrl_stride, 5);
add_new_reg_interface(ctrl_replay, 6);
add_new_reg_interface(ctrl_image_size, 7);
add_new_reg_interface(ctrl_acf, 8);
add_new_reg_interface(ctrl_zeropad, 9);
add_new_reg_interface(ctrl_output_channel, 10);
add_new_reg_interface(ctrl_stitch_depth, 11);
add_new_reg_interface(ctrl_stitch_buf_depth, 12);
add_new_reg_interface(ctrl_db_output, 13);
add_new_reg_interface(ctrl_image_data, 14);
add_new_reg_interface(ctrl_pool_depth, 15);
add_new_reg_interface(ctrl_pool_type, 16);
add_new_reg_interface(ctrl_pool_N, 17);
add_new_reg_interface(ctrl_pool_size, 18);
default:
break;
};
} while (tmp_in.tlast == 0);
}
}
#endif
};
|
//
// Created by tobias on 29.11.17.
//
#ifndef PROJECT_STIMULI2_H
#define PROJECT_STIMULI2_H
#include "systemc.h"
#include "Interfaces.h"
#include "types.h"
struct Stimuli2 : public sc_module {
SC_HAS_PROCESS(Stimuli2);
Stimuli2(sc_module_name name) :
value("value")
{ SC_THREAD(fsm); }
//Blocking interface
blocking_out <int> value;
//Variables
int cnt;
//Behavior
void fsm() {
while (true) {
if(cnt < 887) ++cnt;
else cnt=0;
//value->write(cnt);
value->write(cnt);
}
};
};
#endif //PROJECT_STIMULI_H
|
// ----------------------------------------------------------------------------
// SystemC SCVerify Flow -- sysc_sim_trans.cpp
//
// HLS version: 10.4b/841621 Production Release
// HLS date: Thu Oct 24 17:20:07 PDT 2019
// Flow Packages: HDL_Tcl 8.0a, SCVerify 10.4
//
// Generated by: [email protected]
// Generated date: Sun May 03 14:22:05 EDT 2020
//
// ----------------------------------------------------------------------------
//
// -------------------------------------
// sysc_sim_wrapper
// Represents a new SC_MODULE having the same interface as the original model SysArray_rtl
// -------------------------------------
//
#ifndef TO_QUOTED_STRING
#define TO_QUOTED_STRING(x) TO_QUOTED_STRING1(x)
#define TO_QUOTED_STRING1(x) #x
#endif
// Hold time for the SCVerify testbench to account for the gate delay after downstream synthesis in pico second(s)
// Hold time value is obtained from 'top_gate_constraints.cpp', which is generated at the end of RTL synthesis
#ifdef CCS_DUT_GATE
extern double __scv_hold_time;
#else
double __scv_hold_time = 0.0; // default for non-gate simulation is zero
#endif
#ifndef SC_USE_STD_STRING
#define SC_USE_STD_STRING
#endif
#include "../../../../../cmod/lab3/SysArray/SysArray.h"
#include <systemc.h>
#include <mc_scverify.h>
#include <mt19937ar.c>
#include "mc_dut_wrapper.h"
namespace CCS_RTL {
class sysc_sim_wrapper : public sc_module
{
public:
// Interface Ports
sc_core::sc_in<bool > clk;
sc_core::sc_in<bool > rst;
Connections::In<ac_int<8, true >, Connections::SYN_PORT > weight_in_vec[8];
Connections::In<ac_int<8, true >, Connections::SYN_PORT > act_in_vec[8];
Connections::Out<ac_int<32, true >, Connections::SYN_PORT > accum_out_vec[8];
// Data objects
sc_signal< bool > ccs_rtl_SIG_clk;
sc_signal< sc_logic > ccs_rtl_SIG_rst;
sc_signal< sc_logic > ccs_rtl_SIG_weight_in_vec_0_val;
sc_signal< sc_logic > ccs_rtl_SIG_weight_in_vec_1_val;
sc_signal< sc_logic > ccs_rtl_SIG_weight_in_vec_2_val;
sc_signal< sc_logic > ccs_rtl_SIG_weight_in_vec_3_val;
sc_signal< sc_logic > ccs_rtl_SIG_weight_in_vec_4_val;
sc_signal< sc_logic > ccs_rtl_SIG_weight_in_vec_5_val;
sc_signal< sc_logic > ccs_rtl_SIG_weight_in_vec_6_val;
sc_signal< sc_logic > ccs_rtl_SIG_weight_in_vec_7_val;
sc_signal< sc_logic > ccs_rtl_SIG_weight_in_vec_0_rdy;
sc_signal< sc_logic > ccs_rtl_SIG_weight_in_vec_1_rdy;
sc_signal< sc_logic > ccs_rtl_SIG_weight_in_vec_2_rdy;
sc_signal< sc_logic > ccs_rtl_SIG_weight_in_vec_3_rdy;
sc_signal< sc_logic > ccs_rtl_SIG_weight_in_vec_4_rdy;
sc_signal< sc_logic > ccs_rtl_SIG_weight_in_vec_5_rdy;
sc_signal< sc_logic > ccs_rtl_SIG_weight_in_vec_6_rdy;
sc_signal< sc_logic > ccs_rtl_SIG_weight_in_vec_7_rdy;
sc_signal< sc_lv<8> > ccs_rtl_SIG_weight_in_vec_0_msg;
sc_signal< sc_lv<8> > ccs_rtl_SIG_weight_in_vec_1_msg;
sc_signal< sc_lv<8> > ccs_rtl_SIG_weight_in_vec_2_msg;
sc_signal< sc_lv<8> > ccs_rtl_SIG_weight_in_vec_3_msg;
sc_signal< sc_lv<8> > ccs_rtl_SIG_weight_in_vec_4_msg;
sc_signal< sc_lv<8> > ccs_rtl_SIG_weight_in_vec_5_msg;
sc_signal< sc_lv<8> > ccs_rtl_SIG_weight_in_vec_6_msg;
sc_signal< sc_lv<8> > ccs_rtl_SIG_weight_in_vec_7_msg;
sc_signal< sc_logic > ccs_rtl_SIG_act_in_vec_0_val;
sc_signal< sc_logic > ccs_rtl_SIG_act_in_vec_1_val;
sc_signal< sc_logic > ccs_rtl_SIG_act_in_vec_2_val;
sc_signal< sc_logic > ccs_rtl_SIG_act_in_vec_3_val;
sc_signal< sc_logic > ccs_rtl_SIG_act_in_vec_4_val;
sc_signal< sc_logic > ccs_rtl_SIG_act_in_vec_5_val;
sc_signal< sc_logic > ccs_rtl_SIG_act_in_vec_6_val;
sc_signal< sc_logic > ccs_rtl_SIG_act_in_vec_7_val;
sc_signal< sc_logic > ccs_rtl_SIG_act_in_vec_0_rdy;
sc_signal< sc_logic > ccs_rtl_SIG_act_in_vec_1_rdy;
sc_signal< sc_logic > ccs_rtl_SIG_act_in_vec_2_rdy;
sc_signal< sc_logic > ccs_rtl_SIG_act_in_vec_3_rdy;
sc_signal< sc_logic > ccs_rtl_SIG_act_in_vec_4_rdy;
sc_signal< sc_logic > ccs_rtl_SIG_act_in_vec_5_rdy;
sc_signal< sc_logic > ccs_rtl_SIG_act_in_vec_6_rdy;
sc_signal< sc_logic > ccs_rtl_SIG_act_in_vec_7_rdy;
sc_signal< sc_lv<8> > ccs_rtl_SIG_act_in_vec_0_msg;
sc_signal< sc_lv<8> > ccs_rtl_SIG_act_in_vec_1_msg;
sc_signal< sc_lv<8> > ccs_rtl_SIG_act_in_vec_2_msg;
sc_signal< sc_lv<8> > ccs_rtl_SIG_act_in_vec_3_msg;
sc_signal< sc_lv<8> > ccs_rtl_SIG_act_in_vec_4_msg;
sc_signal< sc_lv<8> > ccs_rtl_SIG_act_in_vec_5_msg;
sc_signal< sc_lv<8> > ccs_rtl_SIG_act_in_vec_6_msg;
sc_signal< sc_lv<8> > ccs_rtl_SIG_act_in_vec_7_msg;
sc_signal< sc_logic > ccs_rtl_SIG_accum_out_vec_0_val;
sc_signal< sc_logic > ccs_rtl_SIG_accum_out_vec_1_val;
sc_signal< sc_logic > ccs_rtl_SIG_accum_out_vec_2_val;
sc_signal< sc_logic > ccs_rtl_SIG_accum_out_vec_3_val;
sc_signal< sc_logic > ccs_rtl_SIG_accum_out_vec_4_val;
sc_signal< sc_logic > ccs_rtl_SIG_accum_out_vec_5_val;
sc_signal< sc_logic > ccs_rtl_SIG_accum_out_vec_6_val;
sc_signal< sc_logic > ccs_rtl_SIG_accum_out_vec_7_val;
sc_signal< sc_logic > ccs_rtl_SIG_accum_out_vec_0_rdy;
sc_signal< sc_logic > ccs_rtl_SIG_accum_out_vec_1_rdy;
sc_signal< sc_logic > ccs_rtl_SIG_accum_out_vec_2_rdy;
sc_signal< sc_logic > ccs_rtl_SIG_accum_out_vec_3_rdy;
sc_signal< sc_logic > ccs_rtl_SIG_accum_out_vec_4_rdy;
sc_signal< sc_logic > ccs_rtl_SIG_accum_out_vec_5_rdy;
sc_signal< sc_logic > ccs_rtl_SIG_accum_out_vec_6_rdy;
sc_signal< sc_logic > ccs_rtl_SIG_accum_out_vec_7_rdy;
sc_signal< sc_lv<32> > ccs_rtl_SIG_accum_out_vec_0_msg;
sc_signal< sc_lv<32> > ccs_rtl_SIG_accum_out_vec_1_msg;
sc_signal< sc_lv<32> > ccs_rtl_SIG_accum_out_vec_2_msg;
sc_signal< sc_lv<32> > ccs_rtl_SIG_accum_out_vec_3_msg;
sc_signal< sc_lv<32> > ccs_rtl_SIG_accum_out_vec_4_msg;
sc_signal< sc_lv<32> > ccs_rtl_SIG_accum_out_vec_5_msg;
sc_signal< sc_lv<32> > ccs_rtl_SIG_accum_out_vec_6_msg;
sc_signal< sc_lv<32> > ccs_rtl_SIG_accum_out_vec_7_msg;
// Named Objects
// Module instance pointers
HDL::ccs_DUT_wrapper ccs_rtl;
// Declare processes (SC_METHOD and SC_THREAD)
void update_proc();
// Constructor
SC_HAS_PROCESS(sysc_sim_wrapper);
sysc_sim_wrapper(
const sc_module_name& nm
)
: ccs_rtl(
"ccs_rtl",
TO_QUOTED_STRING(TOP_HDL_ENTITY)
)
, clk("clk")
, rst("rst")
, weight_in_vec()
, act_in_vec()
, accum_out_vec()
, ccs_rtl_SIG_clk("ccs_rtl_SIG_clk")
, ccs_rtl_SIG_rst("ccs_rtl_SIG_rst")
, ccs_rtl_SIG_weight_in_vec_0_val("ccs_rtl_SIG_weight_in_vec_0_val")
, ccs_rtl_SIG_weight_in_vec_1_val("ccs_rtl_SIG_weight_in_vec_1_val")
, ccs_rtl_SIG_weight_in_vec_2_val("ccs_rtl_SIG_weight_in_vec_2_val")
, ccs_rtl_SIG_weight_in_vec_3_val("ccs_rtl_SIG_weight_in_vec_3_val")
, ccs_rtl_SIG_weight_in_vec_4_val("ccs_rtl_SIG_weight_in_vec_4_val")
, ccs_rtl_SIG_weight_in_vec_5_val("ccs_rtl_SIG_weight_in_vec_5_val")
, ccs_rtl_SIG_weight_in_vec_6_val("ccs_rtl_SIG_weight_in_vec_6_val")
, ccs_rtl_SIG_weight_in_vec_7_val("ccs_rtl_SIG_weight_in_vec_7_val")
, ccs_rtl_SIG_weight_in_vec_0_rdy("ccs_rtl_SIG_weight_in_vec_0_rdy")
, ccs_rtl_SIG_weight_in_vec_1_rdy("ccs_rtl_SIG_weight_in_vec_1_rdy")
, ccs_rtl_SIG_weight_in_vec_2_rdy("ccs_rtl_SIG_weight_in_vec_2_rdy")
, ccs_rtl_SIG_weight_in_vec_3_rdy("ccs_rtl_SIG_weight_in_vec_3_rdy")
, ccs_rtl_SIG_weight_in_vec_4_rdy("ccs_rtl_SIG_weight_in_vec_4_rdy")
, ccs_rtl_SIG_weight_in_vec_5_rdy("ccs_rtl_SIG_weight_in_vec_5_rdy")
, ccs_rtl_SIG_weight_in_vec_6_rdy("ccs_rtl_SIG_weight_in_vec_6_rdy")
, ccs_rtl_SIG_weight_in_vec_7_rdy("ccs_rtl_SIG_weight_in_vec_7_rdy")
, ccs_rtl_SIG_weight_in_vec_0_msg("ccs_rtl_SIG_weight_in_vec_0_msg")
, ccs_rtl_SIG_weight_in_vec_1_msg("ccs_rtl_SIG_weight_in_vec_1_msg")
, ccs_rtl_SIG_weight_in_vec_2_msg("ccs_rtl_SIG_weight_in_vec_2_msg")
, ccs_rtl_SIG_weight_in_vec_3_msg("ccs_rtl_SIG_weight_in_vec_3_msg")
, ccs_rtl_SIG_weight_in_vec_4_msg("ccs_rtl_SIG_weight_in_vec_4_msg")
, ccs_rtl_SIG_weight_in_vec_5_msg("ccs_rtl_SIG_weight_in_vec_5_msg")
, ccs_rtl_SIG_weight_in_vec_6_msg("ccs_rtl_SIG_weight_in_vec_6_msg")
, ccs_rtl_SIG_weight_in_vec_7_msg("ccs_rtl_SIG_weight_in_vec_7_msg")
, ccs_rtl_SIG_act_in_vec_0_val("ccs_rtl_SIG_act_in_vec_0_val")
, ccs_rtl_SIG_act_in_vec_1_val("ccs_rtl_SIG_act_in_vec_1_val")
, ccs_rtl_SIG_act_in_vec_2_val("ccs_rtl_SIG_act_in_vec_2_val")
, ccs_rtl_SIG_act_in_vec_3_val("ccs_rtl_SIG_act_in_vec_3_val")
, ccs_rtl_SIG_act_in_vec_4_val("ccs_rtl_SIG_act_in_vec_4_val")
, ccs_rtl_SIG_act_in_vec_5_val("ccs_rtl_SIG_act_in_vec_5_val")
, ccs_rtl_SIG_act_in_vec_6_val("ccs_rtl_SIG_act_in_vec_6_val")
, ccs_rtl_SIG_act_in_vec_7_val("ccs_rtl_SIG_act_in_vec_7_val")
, ccs_rtl_SIG_act_in_vec_0_rdy("ccs_rtl_SIG_act_in_vec_0_rdy")
, ccs_rtl_SIG_act_in_vec_1_rdy("ccs_rtl_SIG_act_in_vec_1_rdy")
, ccs_rtl_SIG_act_in_vec_2_rdy("ccs_rtl_SIG_act_in_vec_2_rdy")
, ccs_rtl_SIG_act_in_vec_3_rdy("ccs_rtl_SIG_act_in_vec_3_rdy")
, ccs_rtl_SIG_act_in_vec_4_rdy("ccs_rtl_SIG_act_in_vec_4_rdy")
, ccs_rtl_SIG_act_in_vec_5_rdy("ccs_rtl_SIG_act_in_vec_5_rdy")
, ccs_rtl_SIG_act_in_vec_6_rdy("ccs_rtl_SIG_act_in_vec_6_rdy")
, ccs_rtl_SIG_act_in_vec_7_rdy("ccs_rtl_SIG_act_in_vec_7_rdy")
, ccs_rtl_SIG_act_in_vec_0_msg("ccs_rtl_SIG_act_in_vec_0_msg")
, ccs_rtl_SIG_act_in_vec_1_msg("ccs_rtl_SIG_act_in_vec_1_msg")
, ccs_rtl_SIG_act_in_vec_2_msg("ccs_rtl_SIG_act_in_vec_2_msg")
, ccs_rtl_SIG_act_in_vec_3_msg("ccs_rtl_SIG_act_in_vec_3_msg")
, ccs_rtl_SIG_act_in_vec_4_msg("ccs_rtl_SIG_act_in_vec_4_msg")
, ccs_rtl_SIG_act_in_vec_5_msg("ccs_rtl_SIG_act_in_vec_5_msg")
, ccs_rtl_SIG_act_in_vec_6_msg("ccs_rtl_SIG_act_in_vec_6_msg")
, ccs_rtl_SIG_act_in_vec_7_msg("ccs_rtl_SIG_act_in_vec_7_msg")
, ccs_rtl_SIG_accum_out_vec_0_val("ccs_rtl_SIG_accum_out_vec_0_val")
, ccs_rtl_SIG_accum_out_vec_1_val("ccs_rtl_SIG_accum_out_vec_1_val")
, ccs_rtl_SIG_accum_out_vec_2_val("ccs_rtl_SIG_accum_out_vec_2_val")
, ccs_rtl_SIG_accum_out_vec_3_val("ccs_rtl_SIG_accum_out_vec_3_val")
, ccs_rtl_SIG_accum_out_vec_4_val("ccs_rtl_SIG_accum_out_vec_4_val")
, ccs_rtl_SIG_accum_out_vec_5_val("ccs_rtl_SIG_accum_out_vec_5_val")
, ccs_rtl_SIG_accum_out_vec_6_val("ccs_rtl_SIG_accum_out_vec_6_val")
, ccs_rtl_SIG_accum_out_vec_7_val("ccs_rtl_SIG_accum_out_vec_7_val")
, ccs_rtl_SIG_accum_out_vec_0_rdy("ccs_rtl_SIG_accum_out_vec_0_rdy")
, ccs_rtl_SIG_accum_out_vec_1_rdy("ccs_rtl_SIG_accum_out_vec_1_rdy")
, ccs_rtl_SIG_accum_out_vec_2_rdy("ccs_rtl_SIG_accum_out_vec_2_rdy")
, ccs_rtl_SIG_accum_out_vec_3_rdy("ccs_rtl_SIG_accum_out_vec_3_rdy")
, ccs_rtl_SIG_accum_out_vec_4_rdy("ccs_rtl_SIG_accum_out_vec_4_rdy")
, ccs_rtl_SIG_accum_out_vec_5_rdy("ccs_rtl_SIG_accum_out_vec_5_rdy")
, ccs_rtl_SIG_accum_out_vec_6_rdy("ccs_rtl_SIG_accum_out_vec_6_rdy")
, ccs_rtl_SIG_accum_out_vec_7_rdy("ccs_rtl_SIG_accum_out_vec_7_rdy")
, ccs_rtl_SIG_accum_out_vec_0_msg("ccs_rtl_SIG_accum_out_vec_0_msg")
, ccs_rtl_SIG_accum_out_vec_1_msg("ccs_rtl_SIG_accum_out_vec_1_msg")
, ccs_rtl_SIG_accum_out_vec_2_msg("ccs_rtl_SIG_accum_out_vec_2_msg")
, ccs_rtl_SIG_accum_out_vec_3_msg("ccs_rtl_SIG_accum_out_vec_3_msg")
, ccs_rtl_SIG_accum_out_vec_4_msg("ccs_rtl_SIG_accum_out_vec_4_msg")
, ccs_rtl_SIG_accum_out_vec_5_msg("ccs_rtl_SIG_accum_out_vec_5_msg")
, ccs_rtl_SIG_accum_out_vec_6_msg("ccs_rtl_SIG_accum_out_vec_6_msg")
, ccs_rtl_SIG_accum_out_vec_7_msg("ccs_rtl_SIG_accum_out_vec_7_msg")
{
// Instantiate other modules
ccs_rtl.clk(ccs_rtl_SIG_clk);
ccs_rtl.rst(ccs_rtl_SIG_rst);
ccs_rtl.weight_in_vec_0_val(ccs_rtl_SIG_weight_in_vec_0_val);
ccs_rtl.weight_in_vec_1_val(ccs_rtl_SIG_weight_in_vec_1_val);
ccs_rtl.weight_in_vec_2_val(ccs_rtl_SIG_weight_in_vec_2_val);
ccs_rtl.weight_in_vec_3_val(ccs_rtl_SIG_weight_in_vec_3_val);
ccs_rtl.weight_in_vec_4_val(ccs_rtl_SIG_weight_in_vec_4_val);
ccs_rtl.weight_in_vec_5_val(ccs_rtl_SIG_weight_in_vec_5_val);
ccs_rtl.weight_in_vec_6_val(ccs_rtl_SIG_weight_in_vec_6_val);
ccs_rtl.weight_in_vec_7_val(ccs_rtl_SIG_weight_in_vec_7_val);
ccs_rtl.weight_in_vec_0_rdy(ccs_rtl_SIG_weight_in_vec_0_rdy);
ccs_rtl.weight_in_vec_1_rdy(ccs_rtl_SIG_weight_in_vec_1_rdy);
ccs_rtl.weight_in_vec_2_rdy(ccs_rtl_SIG_weight_in_vec_2_rdy);
ccs_rtl.weight_in_vec_3_rdy(ccs_rtl_SIG_weight_in_vec_3_rdy);
ccs_rtl.weight_in_vec_4_rdy(ccs_rtl_SIG_weight_in_vec_4_rdy);
ccs_rtl.weight_in_vec_5_rdy(ccs_rtl_SIG_weight_in_vec_5_rdy);
ccs_rtl.weight_in_vec_6_rdy(ccs_rtl_SIG_weight_in_vec_6_rdy);
ccs_rtl.weight_in_vec_7_rdy(ccs_rtl_SIG_weight_in_vec_7_rdy);
ccs_rtl.weight_in_vec_0_msg(ccs_rtl_SIG_weight_in_vec_0_msg);
ccs_rtl.weight_in_vec_1_msg(ccs_rtl_SIG_weight_in_vec_1_msg);
ccs_rtl.weight_in_vec_2_msg(ccs_rtl_SIG_weight_in_vec_2_msg);
ccs_rtl.weight_in_vec_3_msg(ccs_rtl_SIG_weight_in_vec_3_msg);
ccs_rtl.weight_in_vec_4_msg(ccs_rtl_SIG_weight_in_vec_4_msg);
ccs_rtl.weight_in_vec_5_msg(ccs_rtl_SIG_weight_in_vec_5_msg);
ccs_rtl.weight_in_vec_6_msg(ccs_rtl_SIG_weight_in_vec_6_msg);
ccs_rtl.weight_in_vec_7_msg(ccs_rtl_SIG_weight_in_vec_7_msg);
ccs_rtl.act_in_vec_0_val(ccs_rtl_SIG_act_in_vec_0_val);
ccs_rtl.act_in_vec_1_val(ccs_rtl_SIG_act_in_vec_1_val);
ccs_rtl.act_in_vec_2_val(ccs_rtl_SIG_act_in_vec_2_val);
ccs_rtl.act_in_vec_3_val(ccs_rtl_SIG_act_in_vec_3_val);
ccs_rtl.act_in_vec_4_val(ccs_rtl_SIG_act_in_vec_4_val);
ccs_rtl.act_in_vec_5_val(ccs_rtl_SIG_act_in_vec_5_val);
ccs_rtl.act_in_vec_6_val(ccs_rtl_SIG_act_in_vec_6_val);
ccs_rtl.act_in_vec_7_val(ccs_rtl_SIG_act_in_vec_7_val);
ccs_rtl.act_in_vec_0_rdy(ccs_rtl_SIG_act_in_vec_0_rdy);
ccs_rtl.act_in_vec_1_rdy(ccs_rtl_SIG_act_in_vec_1_rdy);
ccs_rtl.act_in_vec_2_rdy(ccs_rtl_SIG_act_in_vec_2_rdy);
ccs_rtl.act_in_vec_3_rdy(ccs_rtl_SIG_act_in_vec_3_rdy);
ccs_rtl.act_in_vec_4_rdy(ccs_rtl_SIG_act_in_vec_4_rdy);
ccs_rtl.act_in_vec_5_rdy(ccs_rtl_SIG_act_in_vec_5_rdy);
ccs_rtl.act_in_vec_6_rdy(ccs_rtl_SIG_act_in_vec_6_rdy);
ccs_rtl.act_in_vec_7_rdy(ccs_rtl_SIG_act_in_vec_7_rdy);
ccs_rtl.act_in_vec_0_msg(ccs_rtl_SIG_act_in_vec_0_msg);
ccs_rtl.act_in_vec_1_msg(ccs_rtl_SIG_act_in_vec_1_msg);
ccs_rtl.act_in_vec_2_msg(ccs_rtl_SIG_act_in_vec_2_msg);
ccs_rtl.act_in_vec_3_msg(ccs_rtl_SIG_act_in_vec_3_msg);
ccs_rtl.act_in_vec_4_msg(ccs_rtl_SIG_act_in_vec_4_msg);
ccs_rtl.act_in_vec_5_msg(ccs_rtl_SIG_act_in_vec_5_msg);
ccs_rtl.act_in_vec_6_msg(ccs_rtl_SIG_act_in_vec_6_msg);
ccs_rtl.act_in_vec_7_msg(ccs_rtl_SIG_act_in_vec_7_msg);
ccs_rtl.accum_out_vec_0_val(ccs_rtl_SIG_accum_out_vec_0_val);
ccs_rtl.accum_out_vec_1_val(ccs_rtl_SIG_accum_out_vec_1_val);
ccs_rtl.accum_out_vec_2_val(ccs_rtl_SIG_accum_out_vec_2_val);
ccs_rtl.accum_out_vec_3_val(ccs_rtl_SIG_accum_out_vec_3_val);
ccs_rtl.accum_out_vec_4_val(ccs_rtl_SIG_accum_out_vec_4_val);
ccs_rtl.accum_out_vec_5_val(ccs_rtl_SIG_accum_out_vec_5_val);
ccs_rtl.accum_out_vec_6_val(ccs_rtl_SIG_accum_out_vec_6_val);
ccs_rtl.accum_out_vec_7_val(ccs_rtl_SIG_accum_out_vec_7_val);
ccs_rtl.accum_out_vec_0_rdy(ccs_rtl_SIG_accum_out_vec_0_rdy);
ccs_rtl.accum_out_vec_1_rdy(ccs_rtl_SIG_accum_out_vec_1_rdy);
ccs_rtl.accum_out_vec_2_rdy(ccs_rtl_SIG_accum_out_vec_2_rdy);
ccs_rtl.accum_out_vec_3_rdy(ccs_rtl_SIG_accum_out_vec_3_rdy);
ccs_rtl.accum_out_vec_4_rdy(ccs_rtl_SIG_accum_out_vec_4_rdy);
ccs_rtl.accum_out_vec_5_rdy(ccs_rtl_SIG_accum_out_vec_5_rdy);
ccs_rtl.accum_out_vec_6_rdy(ccs_rtl_SIG_accum_out_vec_6_rdy);
ccs_rtl.accum_out_vec_7_rdy(ccs_rtl_SIG_accum_out_vec_7_rdy);
ccs_rtl.accum_out_vec_0_msg(ccs_rtl_SIG_accum_out_vec_0_msg);
ccs_rtl.accum_out_vec_1_msg(ccs_rtl_SIG_accum_out_vec_1_msg);
ccs_rtl.accum_out_vec_2_msg(ccs_rtl_SIG_accum_out_vec_2_msg);
ccs_rtl.accum_out_vec_3_msg(ccs_rtl_SIG_accum_out_vec_3_msg);
ccs_rtl.accum_out_vec_4_msg(ccs_rtl_SIG_accum_out_vec_4_msg);
ccs_rtl.accum_out_vec_5_msg(ccs_rtl_SIG_accum_out_vec_5_msg);
ccs_rtl.accum_out_vec_6_msg(ccs_rtl_SIG_accum_out_vec_6_msg);
ccs_rtl.accum_out_vec_7_msg(ccs_rtl_SIG_accum_out_vec_7_msg);
// Register processes
SC_METHOD(update_proc);
sensitive << clk << rst << weight_in_vec[0].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val << weight_in_vec[1].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val << weight_in_vec[2].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val << weight_in_vec[3].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val << weight_in_vec[4].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val << weight_in_vec[5].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val << weight_in_vec[6].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val << weight_in_vec[7].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val << ccs_rtl_SIG_weight_in_vec_0_rdy << ccs_rtl_SIG_weight_in_vec_1_rdy << ccs_rtl_SIG_weight_in_vec_2_rdy << ccs_rtl_SIG_weight_in_vec_3_rdy << ccs_rtl_SIG_weight_in_vec_4_rdy << ccs_rtl_SIG_weight_in_vec_5_rdy << ccs_rtl_SIG_weight_in_vec_6_rdy << ccs_rtl_SIG_weight_in_vec_7_rdy << weight_in |
_vec[0].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg << weight_in_vec[1].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg << weight_in_vec[2].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg << weight_in_vec[3].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg << weight_in_vec[4].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg << weight_in_vec[5].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg << weight_in_vec[6].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg << weight_in_vec[7].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg << act_in_vec[0].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val << act_in_vec[1].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val << act_in_vec[2].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val << act_in_vec[3].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val << act_in_vec[4].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val << act_in_vec[5].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val << act_in_vec[6].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val << act_in_vec[7].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val << ccs_rtl_SIG_act_in_vec_0_rdy << ccs_rtl_SIG_act_in_vec_1_rdy << ccs_rtl_SIG_act_in_vec_2_rdy << ccs_rtl_SIG_act_in_vec_3_rdy << ccs_rtl_SIG_act_in_vec_4_rdy << ccs_rtl_SIG_act_in_vec_5_rdy << ccs_rtl_SIG_act_in_vec_6_rdy << ccs_rtl_SIG_act_in_vec_7_rdy << act_in_vec[0].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg << act_in_vec[1].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg << act_in_vec[2].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg << act_in_vec[3].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg << act_in_vec[4].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg << act_in_vec[5].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg << act_in_vec[6].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg << act_in_vec[7].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg << ccs_rtl_SIG_accum_out_vec_0_val << ccs_rtl_SIG_accum_out_vec_1_val << ccs_rtl_SIG_accum_out_vec_2_val << ccs_rtl_SIG_accum_out_vec_3_val << ccs_rtl_SIG_accum_out_vec_4_val << ccs_rtl_SIG_accum_out_vec_5_val << ccs_rtl_SIG_accum_out_vec_6_val << ccs_rtl_SIG_accum_out_vec_7_val << accum_out_vec[0].Connections::OutBlocking_Ports_abs<ac_int<32, true > >::rdy << accum_out_vec[1].Connections::OutBlocking_Ports_abs<ac_int<32, true > >::rdy << accum_out_vec[2].Connections::OutBlocking_Ports_abs<ac_int<32, true > >::rdy << accum_out_vec[3].Connections::OutBlocking_Ports_abs<ac_int<32, true > >::rdy << accum_out_vec[4].Connections::OutBlocking_Ports_abs<ac_int<32, true > >::rdy << accum_out_vec[5].Connections::OutBlocking_Ports_abs<ac_int<32, true > >::rdy << accum_out_vec[6].Connections::OutBlocking_Ports_abs<ac_int<32, true > >::rdy << accum_out_vec[7].Connections::OutBlocking_Ports_abs<ac_int<32, true > >::rdy << ccs_rtl_SIG_accum_out_vec_0_msg << ccs_rtl_SIG_accum_out_vec_1_msg << ccs_rtl_SIG_accum_out_vec_2_msg << ccs_rtl_SIG_accum_out_vec_3_msg << ccs_rtl_SIG_accum_out_vec_4_msg << ccs_rtl_SIG_accum_out_vec_5_msg << ccs_rtl_SIG_accum_out_vec_6_msg << ccs_rtl_SIG_accum_out_vec_7_msg;
// Other constructor statements
}
~sysc_sim_wrapper()
{
}
// C++ class functions
};
} // end namespace CCS_RTL
//
// -------------------------------------
// sysc_sim_wrapper
// Represents a new SC_MODULE having the same interface as the original model SysArray_rtl
// -------------------------------------
//
// ---------------------------------------------------------------
// Process: SC_METHOD update_proc
// Static sensitivity: sensitive << clk << rst << weight_in_vec[0].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val << weight_in_vec[1].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val << weight_in_vec[2].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val << weight_in_vec[3].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val << weight_in_vec[4].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val << weight_in_vec[5].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val << weight_in_vec[6].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val << weight_in_vec[7].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val << ccs_rtl_SIG_weight_in_vec_0_rdy << ccs_rtl_SIG_weight_in_vec_1_rdy << ccs_rtl_SIG_weight_in_vec_2_rdy << ccs_rtl_SIG_weight_in_vec_3_rdy << ccs_rtl_SIG_weight_in_vec_4_rdy << ccs_rtl_SIG_weight_in_vec_5_rdy << ccs_rtl_SIG_weight_in_vec_6_rdy << ccs_rtl_SIG_weight_in_vec_7_rdy << weight_in_vec[0].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg << weight_in_vec[1].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg << weight_in_vec[2].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg << weight_in_vec[3].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg << weight_in_vec[4].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg << weight_in_vec[5].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg << weight_in_vec[6].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg << weight_in_vec[7].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg << act_in_vec[0].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val << act_in_vec[1].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val << act_in_vec[2].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val << act_in_vec[3].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val << act_in_vec[4].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val << act_in_vec[5].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val << act_in_vec[6].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val << act_in_vec[7].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val << ccs_rtl_SIG_act_in_vec_0_rdy << ccs_rtl_SIG_act_in_vec_1_rdy << ccs_rtl_SIG_act_in_vec_2_rdy << ccs_rtl_SIG_act_in_vec_3_rdy << ccs_rtl_SIG_act_in_vec_4_rdy << ccs_rtl_SIG_act_in_vec_5_rdy << ccs_rtl_SIG_act_in_vec_6_rdy << ccs_rtl_SIG_act_in_vec_7_rdy << act_in_vec[0].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg << act_in_vec[1].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg << act_in_vec[2].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg << act_in_vec[3].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg << act_in_vec[4].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg << act_in_vec[5].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg << act_in_vec[6].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg << act_in_vec[7].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg << ccs_rtl_SIG_accum_out_vec_0_val << ccs_rtl_SIG_accum_out_vec_1_val << ccs_rtl_SIG_accum_out_vec_2_val << ccs_rtl_SIG_accum_out_vec_3_val << ccs_rtl_SIG_accum_out_vec_4_val << ccs_rtl_SIG_accum_out_vec_5_val << ccs_rtl_SIG_accum_out_vec_6_val << ccs_rtl_SIG_accum_out_vec_7_val << accum_out_vec[0].Connections::OutBlocking_Ports_abs<ac_int<32, true > >::rdy << accum_out_vec[1].Connections::OutBlocking_Ports_abs<ac_int<32, true > >::rdy << accum_out_vec[2].Connections::OutBlocking_Ports_abs<ac_int<32, true > >::rdy << accum_out_vec[3].Connections::OutBlocking_Ports_abs<ac_int<32, true > >::rdy << accum_out_vec[4].Connections::OutBlocking_Ports_abs<ac_int<32, true > >::rdy << accum_out_vec[5].Connections::OutBlocking_Ports_abs<ac_int<32, true > >::rdy << accum_out_vec[6].Connections::OutBlocking_Ports_abs<ac_int<32, true > >::rdy << accum_out_vec[7].Connections::OutBlocking_Ports_abs<ac_int<32, true > >::rdy << ccs_rtl_SIG_accum_out_vec_0_msg << ccs_rtl_SIG_accum_out_vec_1_msg << ccs_rtl_SIG_accum_out_vec_2_msg << ccs_rtl_SIG_accum_out_vec_3_msg << ccs_rtl_SIG_accum_out_vec_4_msg << ccs_rtl_SIG_accum_out_vec_5_msg << ccs_rtl_SIG_accum_out_vec_6_msg << ccs_rtl_SIG_accum_out_vec_7_msg;
void CCS_RTL::sysc_sim_wrapper::update_proc() {
// none.sc_in field_key=clk:b8493181-44ed-443f-beb1-e7f82e6a327d-373:clk:b8493181-44ed-443f-beb1-e7f82e6a327d-373
sc_logic t_b8493181_44ed_443f_beb1_e7f82e6a327d_373; // NPS - LV to hold field
ccs_rtl_SIG_clk.write(clk.read());
// none.sc_in field_key=rst:b8493181-44ed-443f-beb1-e7f82e6a327d-374:rst:b8493181-44ed-443f-beb1-e7f82e6a327d-374
sc_logic t_b8493181_44ed_443f_beb1_e7f82e6a327d_374; // NPS - LV to hold field
type_to_vector(rst.read(),1,t_b8493181_44ed_443f_beb1_e7f82e6a327d_374); // read orig port and type convert
ccs_rtl_SIG_rst.write(t_b8493181_44ed_443f_beb1_e7f82e6a327d_374); // then write to RTL port
// none.sc_in field_key=weight_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-388:val:b8493181-44ed-443f-beb1-e7f82e6a327d-417
sc_logic t_b8493181_44ed_443f_beb1_e7f82e6a327d_417; // NPS - LV to hold field
type_to_vector(weight_in_vec[0].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val.read(),1,t_b8493181_44ed_443f_beb1_e7f82e6a327d_417); // read orig port and type convert
ccs_rtl_SIG_weight_in_vec_0_val.write(t_b8493181_44ed_443f_beb1_e7f82e6a327d_417); // then write to RTL port
// none.sc_in field_key=weight_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-388:val:b8493181-44ed-443f-beb1-e7f82e6a327d-417
type_to_vector(weight_in_vec[1].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val.read(),1,t_b8493181_44ed_443f_beb1_e7f82e6a327d_417); // read orig port and type convert
ccs_rtl_SIG_weight_in_vec_1_val.write(t_b8493181_44ed_443f_beb1_e7f82e6a327d_417); // then write to RTL port
// none.sc_in field_key=weight_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-388:val:b8493181-44ed-443f-beb1-e7f82e6a327d-417
type_to_vector(weight_in_vec[2].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val.read(),1,t_b8493181_44ed_443f_beb1_e7f82e6a327d_417); // read orig port and type convert
ccs_rtl_SIG_weight_in_vec_2_val.write(t_b8493181_44ed_443f_beb1_e7f82e6a327d_417); // then write to RTL port
// none.sc_in field_key=weight_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-388:val:b8493181-44ed-443f-beb1-e7f82e6a327d-417
type_to_vector(weight_in_vec[3].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val.read(),1,t_b8493181_44ed_443f_beb1_e7f82e6a327d_417); // read orig port and type convert
ccs_rtl_SIG_weight_in_vec_3_val.write(t_b8493181_44ed_443f_beb1_e7f82e6a327d_417); // then write to RTL port
// none.sc_in field_key=weight_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-388:val:b8493181-44ed-443f-beb1-e7f82e6a327d-417
type_to_vector(weight_in_vec[4].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val.read(),1,t_b8493181_44ed_443f_beb1_e7f82e6a327d_417); // read orig port and type convert
ccs_rtl_SIG_weight_in_vec_4_val.write(t_b8493181_44ed_443f_beb1_e7f82e6a327d_417); // then write to RTL port
// none.sc_in field_key=weight_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-388:val:b8493181-44ed-443f-beb1-e7f82e6a327d-417
type_to_vector(weight_in_vec[5].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val.read(),1,t_b8493181_44ed_443f_beb1_e7f82e6a327d_417); // read orig port and type convert
ccs_rtl_SIG_weight_in_vec_5_val.write(t_b8493181_44ed_443f_beb1_e7f82e6a327d_417); // then write to RTL port
// none.sc_in field_key=weight_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-388:val:b8493181-44ed-443f-beb1-e7f82e6a327d-417
type_to_vector(weight_in_vec[6].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val.read(),1,t_b8493181_44ed_443f_beb1_e7f82e6a327d_417); // read orig port and type convert
ccs_rtl_SIG_weight_in_vec_6_val.write(t_b8493181_44ed_443f_beb1_e7f82e6a327d_417); // then write to RTL port
// none.sc_in field_key=weight_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-388:val:b8493181-44ed-443f-beb1-e7f82e6a327d-417
type_to_vector(weight_in_vec[7].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val.read(),1,t_b8493181_44ed_443f_beb1_e7f82e6a327d_417); // read orig port and type convert
ccs_rtl_SIG_weight_in_vec_7_val.write(t_b8493181_44ed_443f_beb1_e7f82e6a327d_417); // then write to RTL port
// none.sc_out field_key=weight_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-388:rdy:b8493181-44ed-443f-beb1-e7f82e6a327d-427
bool d_b8493181_44ed_443f_beb1_e7f82e6a327d_427;
vector_to_type(ccs_rtl_SIG_weight_in_vec_0_rdy.read(), 1, &d_b8493181_44ed_443f_beb1_e7f82e6a327d_427);
weight_in_vec[0].Connections::InBlocking_Ports_abs<ac_int<8, true > >::rdy.write(d_b8493181_44ed_443f_beb1_e7f82e6a327d_427);
// none.sc_out field_key=weight_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-388:rdy:b8493181-44ed-443f-beb1-e7f82e6a327d-427
vector_to_type(ccs_rtl_SIG_weight_in_vec_1_rdy.read(), 1, &d_b8493181_44ed_443f_beb1_e7f82e6a327d_427);
weight_in_vec[1].Connections::InBlocking_Ports_abs<ac_int<8, true > >::rdy.write(d_b8493181_44ed_443f_beb1_e7f82e6a327d_427);
// none.sc_out field_key=weight_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-388:rdy:b8493181-44ed-443f-beb1-e7f82e6a327d-427
vector_to_type(ccs_rtl_SIG_weight_in_vec_2_rdy.read(), 1, &d_b8493181_44ed_443f_beb1_e7f82e6a327d_427);
weight_in_vec[2].Connections::InBlocking_Ports_abs<ac_int<8, true > >::rdy.write(d_b8493181_44ed_443f_beb1_e7f82e6a327d_427);
// none.sc_out field_key=weight_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-388:rdy:b8493181-44ed-443f-beb1-e7f82e6a327d-427
vector_to_type(ccs_rtl_SIG_weight_in_vec_3_rdy.read(), 1, &d_b8493181_44ed_443f_beb1_e7f82e6a327d_427);
weight_in_vec[3].Connections::InBlocking_Ports_abs<ac_int<8, true > >::rdy.write(d_b8493181_44ed_443f_beb1_e7f82e6a327d_427);
// none.sc_out field_key=weight_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-388:rdy:b8493181-44ed-443f-beb1-e7f82e6a327d-427
vector_to_type(ccs_rtl_SIG_weight_in_vec_4_rdy.read(), 1, &d_b8493181_44ed_443f_beb1_e7f82e6a327d_427);
weight_in_vec[4].Connections::InBlocking_Ports_abs<ac_int<8, true > >::rdy.write(d_b8493181_44ed_443f_beb1_e7f82e6a327d_427);
// none.sc_out field_key=weight_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-388:rdy:b8493181-44ed-443f-beb1-e7f82e6a327d-427
vector_to_type(ccs_rtl_SIG_weight_in_vec_5_rdy.read(), 1, &d_b8493181_44ed_443f_beb1_e7f82e6a327d_427);
weight_in_vec[5].Connections::InBlocking_Ports_abs<ac_int<8, true > >::rdy.write(d_b8493181_44ed_443f_beb1_e7f82e6a327d_427);
// none.sc_out field_key=weight_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-388:rdy:b8493181-44ed-443f-beb1-e7f82e6a327d-427
vector_to_type(ccs_rtl_SIG_weight_in_vec_6_rdy.read(), 1, &d_b8493181_44ed_443f_beb1_e7f82e6a327d_427);
weight_in_vec[6].Connections::InBlocking_Ports_abs<ac_int<8, true > >::rdy.write(d_b8493181_44ed_443f_beb1_e7f82e6a327d_427);
// none.sc_out field_key=weight_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-388:rdy:b8493181-44ed-443f-beb1-e7f82e6a327d-427
vector_to_type(ccs_rtl_SIG_weight_in_vec_7_rdy.read(), 1, &d_b8493181_44ed_443f_beb1_e7f82e6a327d_427);
weight_in_vec[7].Connections::InBlocking_Ports_abs<ac_int<8, true > >::rdy.write(d_b8493181_44ed_443f_beb1_e7f82e6a327d_427);
// none.sc_in field_key=weight_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-388:msg:b8493181-44ed-443f-beb1-e7f82e6a327d-437
sc_lv< 8 > t_b8493181_44ed_443f_beb1_e7f82e6a327d_437; // NPS - LV to hold field
type_to_vector(weight_in_vec[0].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg.read(),8,t_b8493181_44ed_443f_beb1_e7f82e6a327d_437); // read orig port and type convert
ccs_rtl_SIG_weight_in_vec_0_msg.write(t_b8493181_44ed_443f_beb1_e7f82e6a327d_437); // then write to RTL port
// none.sc_in field_key=weight_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-388:msg:b8493181-44ed-443f-beb1-e7f82e6a327d-437
type_to_vector(weight_in_vec[1].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg.read(),8,t_b8493181_44ed_443f_beb1_e7f82e6a327d_437); // read orig port and type convert
ccs_rtl_SIG_weight_in_vec_1_msg.write(t_b8493181_44ed_443f_beb1_e7f82e6a327d_437); // then write to RTL port
// none.sc_in field_key=weight_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-388:msg:b8493181-44ed-443f-beb1-e7f82e6a327d-437
type_to_vector(weight_in_vec[2].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg.read(),8,t_b8493181_44ed_443f_beb1_e7f82e6a327d_437); // read orig port and type convert
ccs_rtl_SIG_weight_in_vec_2_msg.write(t_b8493181_44ed_443f_beb1_e7f82e6a327d_437); // then write to RTL port
// none.sc_in field_key=weight_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-388:msg:b8493181-44ed-443f-beb1-e7f82e6a327d-437
type_to_vector(weight_in_vec[3].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg.read(),8,t_b8493181_44ed_443f_beb1_e7f82e6a327d_437); // read orig port and type convert
ccs_rtl_SIG_weight_in_vec_3_msg.write(t_b8493181_44ed_443f_beb1_e7f82e6a327d_437); // then write to RTL port
// none.sc_in field_key=weight_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-388:msg:b8493181-44ed-443f-beb1-e7f82e6a327d-437
type_to_vector(weight_in_vec[4].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg.read(),8,t_b8493181_44ed_443f_beb1_e7f82e6a327d_437); // read orig port and type convert
ccs_rtl_SIG_weight_in_vec_4_msg.write(t_b8493181_44ed_443f_beb1_e7f82e6a327d_437); // then write to RTL port
// none.sc_in field_key=weight_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-388:msg:b8493181-44ed-443f-beb1-e7f82e6a327d-437
type_to_vector(weight_in_vec[5].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg.read(),8,t_b8493181_44ed_443f_beb1_e7f82e6a327d_437); // read orig port and type convert
ccs_rtl_SIG_weight_in_vec_5_msg.write(t_b8493181_44ed_443f_beb1_e7f82e6a327d_437); // then write to RTL port
// none.sc_in field_key=weight_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-388:msg:b8493181-44ed-443f-beb1-e7f82e6a327d-437
type_to_vector(weight_in_vec[6].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg.read(),8,t_b8493181_44ed_443f_beb1_e7f82e6a327d_437); // read orig port and type convert
ccs_rtl_SIG_weight_in_vec_6_msg.write(t_b8493181_44ed_443f_beb1_e7f82e6a327d_437); // then write to RTL port
// none.sc_in field_key=weight_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-388:msg:b8493181-44ed-443f-beb1-e7f82e6a327d-437
type_to_vector(weight_in_vec[7].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg.read(),8,t_b8493181_44ed_443f_beb1_e7f82e6a327d_437); // read orig port and type convert
ccs_rtl_SIG_weight_in_vec_7_msg.write(t_b8493181_44ed_443f_beb1_e7f82e6a327d_437); // then write to RTL port
// none.sc_in field_key=act_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-447:val:b8493181-44ed-443f-beb1-e7f82e6a327d-470
sc_logic t_b8493181_44ed_443f_beb1_e7f82e6a327d_470; // NPS - LV to hold field
type_to_vector(act_in_vec[0].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val.read(),1,t_b8493181_44ed_443f_beb1_e7f82e6a327d_470); // read orig port and type convert
ccs_rtl_SIG_act_in_vec_0_val.write(t_b8493181_44ed_443f_beb1_e7f82e6a327d_470); // then write to RTL port
// none.sc_in field_key=act_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-447:val:b8493181-44ed-443f-beb1-e7f82e6a327d-470
type_to_vector(act_in_vec[1].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val.read(),1,t_b8493181_44ed_443f_beb1_e7f82e6a327d_470); // read orig port and type convert
ccs_rtl_SIG_act_in_vec_1_val.write(t_b849 |
3181_44ed_443f_beb1_e7f82e6a327d_470); // then write to RTL port
// none.sc_in field_key=act_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-447:val:b8493181-44ed-443f-beb1-e7f82e6a327d-470
type_to_vector(act_in_vec[2].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val.read(),1,t_b8493181_44ed_443f_beb1_e7f82e6a327d_470); // read orig port and type convert
ccs_rtl_SIG_act_in_vec_2_val.write(t_b8493181_44ed_443f_beb1_e7f82e6a327d_470); // then write to RTL port
// none.sc_in field_key=act_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-447:val:b8493181-44ed-443f-beb1-e7f82e6a327d-470
type_to_vector(act_in_vec[3].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val.read(),1,t_b8493181_44ed_443f_beb1_e7f82e6a327d_470); // read orig port and type convert
ccs_rtl_SIG_act_in_vec_3_val.write(t_b8493181_44ed_443f_beb1_e7f82e6a327d_470); // then write to RTL port
// none.sc_in field_key=act_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-447:val:b8493181-44ed-443f-beb1-e7f82e6a327d-470
type_to_vector(act_in_vec[4].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val.read(),1,t_b8493181_44ed_443f_beb1_e7f82e6a327d_470); // read orig port and type convert
ccs_rtl_SIG_act_in_vec_4_val.write(t_b8493181_44ed_443f_beb1_e7f82e6a327d_470); // then write to RTL port
// none.sc_in field_key=act_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-447:val:b8493181-44ed-443f-beb1-e7f82e6a327d-470
type_to_vector(act_in_vec[5].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val.read(),1,t_b8493181_44ed_443f_beb1_e7f82e6a327d_470); // read orig port and type convert
ccs_rtl_SIG_act_in_vec_5_val.write(t_b8493181_44ed_443f_beb1_e7f82e6a327d_470); // then write to RTL port
// none.sc_in field_key=act_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-447:val:b8493181-44ed-443f-beb1-e7f82e6a327d-470
type_to_vector(act_in_vec[6].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val.read(),1,t_b8493181_44ed_443f_beb1_e7f82e6a327d_470); // read orig port and type convert
ccs_rtl_SIG_act_in_vec_6_val.write(t_b8493181_44ed_443f_beb1_e7f82e6a327d_470); // then write to RTL port
// none.sc_in field_key=act_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-447:val:b8493181-44ed-443f-beb1-e7f82e6a327d-470
type_to_vector(act_in_vec[7].Connections::InBlocking_Ports_abs<ac_int<8, true > >::val.read(),1,t_b8493181_44ed_443f_beb1_e7f82e6a327d_470); // read orig port and type convert
ccs_rtl_SIG_act_in_vec_7_val.write(t_b8493181_44ed_443f_beb1_e7f82e6a327d_470); // then write to RTL port
// none.sc_out field_key=act_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-447:rdy:b8493181-44ed-443f-beb1-e7f82e6a327d-480
bool d_b8493181_44ed_443f_beb1_e7f82e6a327d_480;
vector_to_type(ccs_rtl_SIG_act_in_vec_0_rdy.read(), 1, &d_b8493181_44ed_443f_beb1_e7f82e6a327d_480);
act_in_vec[0].Connections::InBlocking_Ports_abs<ac_int<8, true > >::rdy.write(d_b8493181_44ed_443f_beb1_e7f82e6a327d_480);
// none.sc_out field_key=act_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-447:rdy:b8493181-44ed-443f-beb1-e7f82e6a327d-480
vector_to_type(ccs_rtl_SIG_act_in_vec_1_rdy.read(), 1, &d_b8493181_44ed_443f_beb1_e7f82e6a327d_480);
act_in_vec[1].Connections::InBlocking_Ports_abs<ac_int<8, true > >::rdy.write(d_b8493181_44ed_443f_beb1_e7f82e6a327d_480);
// none.sc_out field_key=act_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-447:rdy:b8493181-44ed-443f-beb1-e7f82e6a327d-480
vector_to_type(ccs_rtl_SIG_act_in_vec_2_rdy.read(), 1, &d_b8493181_44ed_443f_beb1_e7f82e6a327d_480);
act_in_vec[2].Connections::InBlocking_Ports_abs<ac_int<8, true > >::rdy.write(d_b8493181_44ed_443f_beb1_e7f82e6a327d_480);
// none.sc_out field_key=act_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-447:rdy:b8493181-44ed-443f-beb1-e7f82e6a327d-480
vector_to_type(ccs_rtl_SIG_act_in_vec_3_rdy.read(), 1, &d_b8493181_44ed_443f_beb1_e7f82e6a327d_480);
act_in_vec[3].Connections::InBlocking_Ports_abs<ac_int<8, true > >::rdy.write(d_b8493181_44ed_443f_beb1_e7f82e6a327d_480);
// none.sc_out field_key=act_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-447:rdy:b8493181-44ed-443f-beb1-e7f82e6a327d-480
vector_to_type(ccs_rtl_SIG_act_in_vec_4_rdy.read(), 1, &d_b8493181_44ed_443f_beb1_e7f82e6a327d_480);
act_in_vec[4].Connections::InBlocking_Ports_abs<ac_int<8, true > >::rdy.write(d_b8493181_44ed_443f_beb1_e7f82e6a327d_480);
// none.sc_out field_key=act_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-447:rdy:b8493181-44ed-443f-beb1-e7f82e6a327d-480
vector_to_type(ccs_rtl_SIG_act_in_vec_5_rdy.read(), 1, &d_b8493181_44ed_443f_beb1_e7f82e6a327d_480);
act_in_vec[5].Connections::InBlocking_Ports_abs<ac_int<8, true > >::rdy.write(d_b8493181_44ed_443f_beb1_e7f82e6a327d_480);
// none.sc_out field_key=act_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-447:rdy:b8493181-44ed-443f-beb1-e7f82e6a327d-480
vector_to_type(ccs_rtl_SIG_act_in_vec_6_rdy.read(), 1, &d_b8493181_44ed_443f_beb1_e7f82e6a327d_480);
act_in_vec[6].Connections::InBlocking_Ports_abs<ac_int<8, true > >::rdy.write(d_b8493181_44ed_443f_beb1_e7f82e6a327d_480);
// none.sc_out field_key=act_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-447:rdy:b8493181-44ed-443f-beb1-e7f82e6a327d-480
vector_to_type(ccs_rtl_SIG_act_in_vec_7_rdy.read(), 1, &d_b8493181_44ed_443f_beb1_e7f82e6a327d_480);
act_in_vec[7].Connections::InBlocking_Ports_abs<ac_int<8, true > >::rdy.write(d_b8493181_44ed_443f_beb1_e7f82e6a327d_480);
// none.sc_in field_key=act_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-447:msg:b8493181-44ed-443f-beb1-e7f82e6a327d-490
sc_lv< 8 > t_b8493181_44ed_443f_beb1_e7f82e6a327d_490; // NPS - LV to hold field
type_to_vector(act_in_vec[0].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg.read(),8,t_b8493181_44ed_443f_beb1_e7f82e6a327d_490); // read orig port and type convert
ccs_rtl_SIG_act_in_vec_0_msg.write(t_b8493181_44ed_443f_beb1_e7f82e6a327d_490); // then write to RTL port
// none.sc_in field_key=act_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-447:msg:b8493181-44ed-443f-beb1-e7f82e6a327d-490
type_to_vector(act_in_vec[1].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg.read(),8,t_b8493181_44ed_443f_beb1_e7f82e6a327d_490); // read orig port and type convert
ccs_rtl_SIG_act_in_vec_1_msg.write(t_b8493181_44ed_443f_beb1_e7f82e6a327d_490); // then write to RTL port
// none.sc_in field_key=act_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-447:msg:b8493181-44ed-443f-beb1-e7f82e6a327d-490
type_to_vector(act_in_vec[2].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg.read(),8,t_b8493181_44ed_443f_beb1_e7f82e6a327d_490); // read orig port and type convert
ccs_rtl_SIG_act_in_vec_2_msg.write(t_b8493181_44ed_443f_beb1_e7f82e6a327d_490); // then write to RTL port
// none.sc_in field_key=act_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-447:msg:b8493181-44ed-443f-beb1-e7f82e6a327d-490
type_to_vector(act_in_vec[3].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg.read(),8,t_b8493181_44ed_443f_beb1_e7f82e6a327d_490); // read orig port and type convert
ccs_rtl_SIG_act_in_vec_3_msg.write(t_b8493181_44ed_443f_beb1_e7f82e6a327d_490); // then write to RTL port
// none.sc_in field_key=act_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-447:msg:b8493181-44ed-443f-beb1-e7f82e6a327d-490
type_to_vector(act_in_vec[4].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg.read(),8,t_b8493181_44ed_443f_beb1_e7f82e6a327d_490); // read orig port and type convert
ccs_rtl_SIG_act_in_vec_4_msg.write(t_b8493181_44ed_443f_beb1_e7f82e6a327d_490); // then write to RTL port
// none.sc_in field_key=act_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-447:msg:b8493181-44ed-443f-beb1-e7f82e6a327d-490
type_to_vector(act_in_vec[5].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg.read(),8,t_b8493181_44ed_443f_beb1_e7f82e6a327d_490); // read orig port and type convert
ccs_rtl_SIG_act_in_vec_5_msg.write(t_b8493181_44ed_443f_beb1_e7f82e6a327d_490); // then write to RTL port
// none.sc_in field_key=act_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-447:msg:b8493181-44ed-443f-beb1-e7f82e6a327d-490
type_to_vector(act_in_vec[6].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg.read(),8,t_b8493181_44ed_443f_beb1_e7f82e6a327d_490); // read orig port and type convert
ccs_rtl_SIG_act_in_vec_6_msg.write(t_b8493181_44ed_443f_beb1_e7f82e6a327d_490); // then write to RTL port
// none.sc_in field_key=act_in_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-447:msg:b8493181-44ed-443f-beb1-e7f82e6a327d-490
type_to_vector(act_in_vec[7].Connections::InBlocking<ac_int<8, true >, Connections::SYN_PORT >::msg.read(),8,t_b8493181_44ed_443f_beb1_e7f82e6a327d_490); // read orig port and type convert
ccs_rtl_SIG_act_in_vec_7_msg.write(t_b8493181_44ed_443f_beb1_e7f82e6a327d_490); // then write to RTL port
// none.sc_out field_key=accum_out_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-500:val:b8493181-44ed-443f-beb1-e7f82e6a327d-515
bool d_b8493181_44ed_443f_beb1_e7f82e6a327d_515;
vector_to_type(ccs_rtl_SIG_accum_out_vec_0_val.read(), 1, &d_b8493181_44ed_443f_beb1_e7f82e6a327d_515);
accum_out_vec[0].Connections::OutBlocking_Ports_abs<ac_int<32, true > >::val.write(d_b8493181_44ed_443f_beb1_e7f82e6a327d_515);
// none.sc_out field_key=accum_out_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-500:val:b8493181-44ed-443f-beb1-e7f82e6a327d-515
vector_to_type(ccs_rtl_SIG_accum_out_vec_1_val.read(), 1, &d_b8493181_44ed_443f_beb1_e7f82e6a327d_515);
accum_out_vec[1].Connections::OutBlocking_Ports_abs<ac_int<32, true > >::val.write(d_b8493181_44ed_443f_beb1_e7f82e6a327d_515);
// none.sc_out field_key=accum_out_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-500:val:b8493181-44ed-443f-beb1-e7f82e6a327d-515
vector_to_type(ccs_rtl_SIG_accum_out_vec_2_val.read(), 1, &d_b8493181_44ed_443f_beb1_e7f82e6a327d_515);
accum_out_vec[2].Connections::OutBlocking_Ports_abs<ac_int<32, true > >::val.write(d_b8493181_44ed_443f_beb1_e7f82e6a327d_515);
// none.sc_out field_key=accum_out_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-500:val:b8493181-44ed-443f-beb1-e7f82e6a327d-515
vector_to_type(ccs_rtl_SIG_accum_out_vec_3_val.read(), 1, &d_b8493181_44ed_443f_beb1_e7f82e6a327d_515);
accum_out_vec[3].Connections::OutBlocking_Ports_abs<ac_int<32, true > >::val.write(d_b8493181_44ed_443f_beb1_e7f82e6a327d_515);
// none.sc_out field_key=accum_out_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-500:val:b8493181-44ed-443f-beb1-e7f82e6a327d-515
vector_to_type(ccs_rtl_SIG_accum_out_vec_4_val.read(), 1, &d_b8493181_44ed_443f_beb1_e7f82e6a327d_515);
accum_out_vec[4].Connections::OutBlocking_Ports_abs<ac_int<32, true > >::val.write(d_b8493181_44ed_443f_beb1_e7f82e6a327d_515);
// none.sc_out field_key=accum_out_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-500:val:b8493181-44ed-443f-beb1-e7f82e6a327d-515
vector_to_type(ccs_rtl_SIG_accum_out_vec_5_val.read(), 1, &d_b8493181_44ed_443f_beb1_e7f82e6a327d_515);
accum_out_vec[5].Connections::OutBlocking_Ports_abs<ac_int<32, true > >::val.write(d_b8493181_44ed_443f_beb1_e7f82e6a327d_515);
// none.sc_out field_key=accum_out_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-500:val:b8493181-44ed-443f-beb1-e7f82e6a327d-515
vector_to_type(ccs_rtl_SIG_accum_out_vec_6_val.read(), 1, &d_b8493181_44ed_443f_beb1_e7f82e6a327d_515);
accum_out_vec[6].Connections::OutBlocking_Ports_abs<ac_int<32, true > >::val.write(d_b8493181_44ed_443f_beb1_e7f82e6a327d_515);
// none.sc_out field_key=accum_out_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-500:val:b8493181-44ed-443f-beb1-e7f82e6a327d-515
vector_to_type(ccs_rtl_SIG_accum_out_vec_7_val.read(), 1, &d_b8493181_44ed_443f_beb1_e7f82e6a327d_515);
accum_out_vec[7].Connections::OutBlocking_Ports_abs<ac_int<32, true > >::val.write(d_b8493181_44ed_443f_beb1_e7f82e6a327d_515);
// none.sc_in field_key=accum_out_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-500:rdy:b8493181-44ed-443f-beb1-e7f82e6a327d-519
sc_logic t_b8493181_44ed_443f_beb1_e7f82e6a327d_519; // NPS - LV to hold field
type_to_vector(accum_out_vec[0].Connections::OutBlocking_Ports_abs<ac_int<32, true > >::rdy.read(),1,t_b8493181_44ed_443f_beb1_e7f82e6a327d_519); // read orig port and type convert
ccs_rtl_SIG_accum_out_vec_0_rdy.write(t_b8493181_44ed_443f_beb1_e7f82e6a327d_519); // then write to RTL port
// none.sc_in field_key=accum_out_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-500:rdy:b8493181-44ed-443f-beb1-e7f82e6a327d-519
type_to_vector(accum_out_vec[1].Connections::OutBlocking_Ports_abs<ac_int<32, true > >::rdy.read(),1,t_b8493181_44ed_443f_beb1_e7f82e6a327d_519); // read orig port and type convert
ccs_rtl_SIG_accum_out_vec_1_rdy.write(t_b8493181_44ed_443f_beb1_e7f82e6a327d_519); // then write to RTL port
// none.sc_in field_key=accum_out_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-500:rdy:b8493181-44ed-443f-beb1-e7f82e6a327d-519
type_to_vector(accum_out_vec[2].Connections::OutBlocking_Ports_abs<ac_int<32, true > >::rdy.read(),1,t_b8493181_44ed_443f_beb1_e7f82e6a327d_519); // read orig port and type convert
ccs_rtl_SIG_accum_out_vec_2_rdy.write(t_b8493181_44ed_443f_beb1_e7f82e6a327d_519); // then write to RTL port
// none.sc_in field_key=accum_out_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-500:rdy:b8493181-44ed-443f-beb1-e7f82e6a327d-519
type_to_vector(accum_out_vec[3].Connections::OutBlocking_Ports_abs<ac_int<32, true > >::rdy.read(),1,t_b8493181_44ed_443f_beb1_e7f82e6a327d_519); // read orig port and type convert
ccs_rtl_SIG_accum_out_vec_3_rdy.write(t_b8493181_44ed_443f_beb1_e7f82e6a327d_519); // then write to RTL port
// none.sc_in field_key=accum_out_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-500:rdy:b8493181-44ed-443f-beb1-e7f82e6a327d-519
type_to_vector(accum_out_vec[4].Connections::OutBlocking_Ports_abs<ac_int<32, true > >::rdy.read(),1,t_b8493181_44ed_443f_beb1_e7f82e6a327d_519); // read orig port and type convert
ccs_rtl_SIG_accum_out_vec_4_rdy.write(t_b8493181_44ed_443f_beb1_e7f82e6a327d_519); // then write to RTL port
// none.sc_in field_key=accum_out_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-500:rdy:b8493181-44ed-443f-beb1-e7f82e6a327d-519
type_to_vector(accum_out_vec[5].Connections::OutBlocking_Ports_abs<ac_int<32, true > >::rdy.read(),1,t_b8493181_44ed_443f_beb1_e7f82e6a327d_519); // read orig port and type convert
ccs_rtl_SIG_accum_out_vec_5_rdy.write(t_b8493181_44ed_443f_beb1_e7f82e6a327d_519); // then write to RTL port
// none.sc_in field_key=accum_out_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-500:rdy:b8493181-44ed-443f-beb1-e7f82e6a327d-519
type_to_vector(accum_out_vec[6].Connections::OutBlocking_Ports_abs<ac_int<32, true > >::rdy.read(),1,t_b8493181_44ed_443f_beb1_e7f82e6a327d_519); // read orig port and type convert
ccs_rtl_SIG_accum_out_vec_6_rdy.write(t_b8493181_44ed_443f_beb1_e7f82e6a327d_519); // then write to RTL port
// none.sc_in field_key=accum_out_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-500:rdy:b8493181-44ed-443f-beb1-e7f82e6a327d-519
type_to_vector(accum_out_vec[7].Connections::OutBlocking_Ports_abs<ac_int<32, true > >::rdy.read(),1,t_b8493181_44ed_443f_beb1_e7f82e6a327d_519); // read orig port and type convert
ccs_rtl_SIG_accum_out_vec_7_rdy.write(t_b8493181_44ed_443f_beb1_e7f82e6a327d_519); // then write to RTL port
// none.sc_out field_key=accum_out_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-500:msg:b8493181-44ed-443f-beb1-e7f82e6a327d-523
sc_dt::sc_lv<32 > d_b8493181_44ed_443f_beb1_e7f82e6a327d_523;
vector_to_type(ccs_rtl_SIG_accum_out_vec_0_msg.read(), 32, &d_b8493181_44ed_443f_beb1_e7f82e6a327d_523);
accum_out_vec[0].Connections::OutBlocking<ac_int<32, true >, Connections::SYN_PORT >::msg.write(d_b8493181_44ed_443f_beb1_e7f82e6a327d_523);
// none.sc_out field_key=accum_out_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-500:msg:b8493181-44ed-443f-beb1-e7f82e6a327d-523
vector_to_type(ccs_rtl_SIG_accum_out_vec_1_msg.read(), 32, &d_b8493181_44ed_443f_beb1_e7f82e6a327d_523);
accum_out_vec[1].Connections::OutBlocking<ac_int<32, true >, Connections::SYN_PORT >::msg.write(d_b8493181_44ed_443f_beb1_e7f82e6a327d_523);
// none.sc_out field_key=accum_out_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-500:msg:b8493181-44ed-443f-beb1-e7f82e6a327d-523
vector_to_type(ccs_rtl_SIG_accum_out_vec_2_msg.read(), 32, &d_b8493181_44ed_443f_beb1_e7f82e6a327d_523);
accum_out_vec[2].Connections::OutBlocking<ac_int<32, true >, Connections::SYN_PORT >::msg.write(d_b8493181_44ed_443f_beb1_e7f82e6a327d_523);
// none.sc_out field_key=accum_out_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-500:msg:b8493181-44ed-443f-beb1-e7f82e6a327d-523
vector_to_type(ccs_rtl_SIG_accum_out_vec_3_msg.read(), 32, &d_b8493181_44ed_443f_beb1_e7f82e6a327d_523);
accum_out_vec[3].Connections::OutBlocking<ac_int<32, true >, Connections::SYN_PORT >::msg.write(d_b8493181_44ed_443f_beb1_e7f82e6a327d_523);
// none.sc_out field_key=accum_out_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-500:msg:b8493181-44ed-443f-beb1-e7f82e6a327d-523
vector_to_type(ccs_rtl_SIG_accum_out_vec_4_msg.read(), 32, &d_b8493181_44ed_443f_beb1_e7f82e6a327d_523);
accum_out_vec[4].Connections::OutBlocking<ac_int<32, true >, Connections::SYN_PORT >::msg.write(d_b8493181_44ed_443f_beb1_e7f82e6a327d_523);
// none.sc_out field_key=accum_out_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-500:msg:b8493181-44ed-443f-beb1-e7f82e6a327d-523
vector_to_type(ccs_rtl_SIG_accum_out_vec_5_msg.read(), 32, &d_b8493181_44ed_443f_beb1_e7f82e6a327d_523);
accum_out_vec[5].Connections::OutBlocking<ac_int<32, true >, Connections::SYN_PORT >::msg.write(d_b8493181_44ed_443f_beb1_e7f82e6a327d_523);
// none.sc_out field_key=accum_out_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-500:msg:b8493181-44ed-443f-beb1-e7f82e6a327d-523
vector_to_type(ccs_rtl_SIG_accum_out_vec_6_msg.read(), 32, &d_b8493181_44ed_443f_beb1_e7f82e6a327d_523);
accum_out_vec[6].Connections::OutBlocking<ac_int<32, true >, Connections::SYN_PORT >::msg.write(d_b8493181_44ed_443f_beb1_e7f82e6a327d_523);
// none.sc_out field_key=accum_out_vec:b8493181-44ed-443f-beb1-e7f82e6a327d-500:msg:b8493181-44ed-443f-beb1-e7f82e6a327d-523
vector_to_type(ccs_rtl_SIG_accum_out_vec_7_msg.read(), 32, &d_b8493181_44ed_443f_beb1_e7f82e6a327d_523);
accum_out_vec[7].Connections::OutBlocking<ac_int<32, true >, Connections::SYN_PORT >::msg.write(d_b8493181_44ed_443f_beb1_e7f82e6a327d_523);
}
// Include original testbench file(s)
#include "/home/billyk/cs148/hls/lab3/SysArray/../../../cmod/lab3/SysArray/testbench.cpp"
|
/*******************************************************************************
* mux_pcnt.h -- Copyright 2019 (c) Glenn Ramalho - RFIDo Design
*******************************************************************************
* Description:
* Model for the PCNT mux in the GPIO matrix.
*******************************************************************************
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
#ifndef _MUX_PCNT_H
#define _MUX_PCNT_H
#include <systemc.h>
#include "pcntbus.h"
SC_MODULE(mux_pcnt) {
sc_port<sc_signal_in_if<bool>,0> mout_i {"mout_i"};
sc_port<sc_signal_out_if<pcntbus_t>,8> pcntbus_o {"pcntbus_o"};
int function[8][4];
sc_event fchange_ev;
/* Functions */
void mux(int bit, int gpiosel);
void initialize();
/* Threads */
void transfer(int function);
SC_CTOR(mux_pcnt) { initialize(); }
};
#endif
|
#pragma once
#include <systemc.h>
//#include "../CORE/core.h"
#include "../../CORE/core.h"
#include "CACHES/icache.h"
#include "CACHES/dcache.h"
#include "wb_river_mc.h"
SC_MODULE(IP_RIVER)
{
sc_in_clk CLK;
sc_in<bool> RESET_N;
//interface bus
sc_in<bool> ACK;
sc_in<sc_uint<32>> DAT_I;
sc_in<bool> GRANT;
sc_in<sc_uint<32>> ADR_I;
sc_out<sc_uint<32>> ADR;
sc_out<sc_uint<32>> DAT_O;
sc_out<sc_uint<2>> SEL;
sc_out<bool> STB;
sc_out<bool> WE;
sc_out<bool> CYC;
// DCache-Core
sc_signal<sc_uint<32>> DATA_ADR_SM;
sc_signal<sc_uint<32>> DATA_SM;
sc_signal<bool> VALID_ADR_SM;
sc_signal<bool> STORE_SM;
sc_signal<bool> LOAD_SM;
sc_signal<sc_uint<2>> MEM_SIZE_SM;
sc_signal<sc_uint<32>> DATA_SDC;
sc_signal<bool> STALL_SDC;
// ICache-Core
sc_signal<sc_uint<32>> ADR_SI;
sc_signal<bool> ADR_VALID_SI;
sc_signal<sc_bv<32>> INST_SIC;
sc_signal<bool> STALL_SIC;
//DCache-Wrapper
sc_signal<bool> READ_SDC;
sc_signal<bool> WRITE_SDC;
sc_signal<bool> DTA_VALID_SDC;
sc_signal<sc_uint<32>> DCACHE_DT;
sc_signal<sc_uint<32>> A_SDC;
sc_signal<sc_uint<2>> SIZE_SDC;
sc_signal<sc_uint<32>> WRAPPER_DT;
sc_signal<bool> DCACHE_ACK;
sc_signal<bool> STALL_SW;
//ICache-Wrapper
sc_signal<bool> ICACHE_ACK;
sc_signal<sc_uint<32>> ICACHE_DT;
sc_signal<sc_uint<32>> A_SIC;
sc_signal<bool> DTA_VALID_SIC;
//Debug CORE
sc_in<sc_uint<32>> PC_RESET;
sc_out<sc_uint<32>> PC_VALUE;
sc_in<sc_uint<32>> PROC_ID;
void trace(sc_trace_file*);
core core_inst;
icache icache_inst;
dcache dcache_inst;
wb_river_mc wrapper_inst;
SC_CTOR(IP_RIVER):
core_inst("core"),
icache_inst("icache"),
dcache_inst("dcache"),
wrapper_inst("wb_river_mc")
{
//CORE map
core_inst.CLK(CLK);
core_inst.RESET(RESET_N);
core_inst.DEBUG_PC_READ(PC_VALUE);
core_inst.PC_INIT(PC_RESET);
core_inst.PROC_ID(PROC_ID);
core_inst.MCACHE_ADR_SM(DATA_ADR_SM);
core_inst.MCACHE_DATA_SM(DATA_SM);
core_inst.MCACHE_ADR_VALID_SM(VALID_ADR_SM);
core_inst.MCACHE_STORE_SM(STORE_SM);
core_inst.MCACHE_LOAD_SM(LOAD_SM);
core_inst.MCACHE_RESULT_SM(DATA_SDC);
core_inst.MCACHE_STALL_SM(STALL_SDC);
core_inst.MEM_SIZE_SM(MEM_SIZE_SM);
core_inst.ADR_SI(ADR_SI);
core_inst.ADR_VALID_SI(ADR_VALID_SI);
core_inst.INST_SIC(INST_SIC);
core_inst.STALL_SIC(STALL_SIC);
//DCache map
dcache_inst.CLK(CLK);
dcache_inst.RESET_N(RESET_N);
dcache_inst.DATA_ADR_SM(DATA_ADR_SM);
dcache_inst.DATA_SM(DATA_SM);
dcache_inst.LOAD_SM(LOAD_SM);
dcache_inst.STORE_SM(STORE_SM);
dcache_inst.VALID_ADR_SM(VALID_ADR_SM);
dcache_inst.MEM_SIZE_SM(MEM_SIZE_SM);
dcache_inst.DATA_SDC(DATA_SDC);
dcache_inst.STALL_SDC(STALL_SDC);
dcache_inst.DTA_VALID_SDC(DTA_VALID_SDC);
dcache_inst.READ_SDC(READ_SDC);
dcache_inst.WRITE_SDC(WRITE_SDC);
dcache_inst.SIZE_SDC(SIZE_SDC);
dcache_inst.DT_SDC(DCACHE_DT);
dcache_inst.A_SDC(A_SDC);
dcache_inst.DT_SW(WRAPPER_DT);
dcache_inst.ACK_SW(DCACHE_ACK);
dcache_inst.ADR_SW(ADR_I);
dcache_inst.GRANT(GRANT); // signal for snoopy control
dcache_inst.STALL_SW(STALL_SW);
//ICache map
icache_inst.CLK(CLK);
icache_inst.RESET_N(RESET_N);
icache_inst.ADR_SI(ADR_SI);
icache_inst.ADR_VALID_SI(ADR_VALID_SI);
icache_inst.INST_SIC(INST_SIC);
icache_inst.STALL_SIC(STALL_SIC);
icache_inst.DT_SW(ICACHE_DT);
icache_inst.A_SIC(A_SIC);
icache_inst.DTA_VALID_SIC(DTA_VALID_SIC);
icache_inst.ACK_SW(ICACHE_ACK);
icache_inst.STALL_SW(STALL_SW);
//Wrapper map
wrapper_inst.CLK(CLK);
wrapper_inst.RESET_N(RESET_N);
wrapper_inst.DAT_I(DAT_I);
wrapper_inst.ACK_I(ACK);
wrapper_inst.DAT_O(DAT_O);
wrapper_inst.ADR_O(ADR);
wrapper_inst.SEL_O(SEL);
wrapper_inst.WE_O(WE);
wrapper_inst.STB_O(STB);
wrapper_inst.A_IC(A_SIC);
wrapper_inst.DTA_VALID_IC(DTA_VALID_SIC);
wrapper_inst.DT_IC(ICACHE_DT);
wrapper_inst.ACK_IC(ICACHE_ACK);
wrapper_inst.DTA_VALID_DC(DTA_VALID_SDC);
wrapper_inst.READ_DC(READ_SDC);
wrapper_inst.WRITE_DC(WRITE_SDC);
wrapper_inst.SIZE_SEL_DC(SIZE_SDC);
wrapper_inst.DT_DC(DCACHE_DT);
wrapper_inst.A_DC(A_SDC);
wrapper_inst.DT_RM(WRAPPER_DT);
wrapper_inst.ACK_DC(DCACHE_ACK);
wrapper_inst.GRANT_I(GRANT);
wrapper_inst.CYC_O(CYC);
wrapper_inst.STALL_SW(STALL_SW);
}
}; |
#ifndef I_CACHE
#define I_CACHE
#include <systemc.h>
#include "../../../UTIL/debug_util.h"
SC_MODULE(icache)
{
// interface global
sc_in_clk CLK;
sc_in<bool> RESET_N;
// interface RiVer
sc_in<sc_uint<32> > ADR_SI;
sc_in<bool> ADR_VALID_SI;
sc_out<sc_bv<32> > INST_SIC;
sc_out<bool> STALL_SIC;
//interface wrapper
sc_in<sc_uint<32>> DT_SW;
sc_out<sc_uint<32>> A_SIC;
sc_out<bool> DTA_VALID_SIC;
sc_in<bool> ACK_SW;
sc_in<bool> STALL_SW;
//signals
sc_signal<sc_bv<32>> data[256][4];
sc_signal<sc_uint<20>> tag[256];
sc_signal<bool> data_validate[256];
sc_signal<sc_uint<20>> address_tag;
sc_signal<sc_uint<8>> address_index;
sc_signal<sc_uint<4>> address_offset;
sc_signal<sc_uint<20>> current_address_tag;
sc_signal<sc_uint<8>> current_address_index;
sc_signal<bool> hit;
sc_signal<sc_uint<3>> fsm_state;
void trace(sc_trace_file*);
void parse_adr();
void miss_detection();
void transition();
SC_CTOR(icache)
{
SC_METHOD(parse_adr);
sensitive << ADR_SI;
SC_METHOD(miss_detection);
sensitive << address_tag
<< address_index
<< address_offset
<< STALL_SIC;
for(int i=0; i < 256 ;i++){
sensitive << data[i][0]
<< data[i][1]
<< data[i][2]
<< data[i][3]
<< data_validate[i];
}
SC_THREAD(transition);
sensitive << CLK.neg();
reset_signal_is(RESET_N, false);
}
};
#endif |
#ifndef SC_CLK_H
#define SC_CLK_H
#include <systemc.h>
#include "sc_config.h"
#include "sc_run.h"
SC_MODULE (scClk) {
// --------------------- Ports ---------------------
sc_out<bool> clk{"clk_o"};
SC_CTOR(scClk) {
SC_THREAD(clockThread);
}
void clockThread () {
sc_time ustep = sc_getMicrostep();
int semiperiod_usteps = sc_getClkSemiperiodMicrosteps();
bool act_edge = sc_getClkActEdge();
while (1) {
clk.write(act_edge);
for (int i = 0; i < semiperiod_usteps; i++) {
wait(ustep);
}
clk.write(!act_edge);
for (int i = 0; i < semiperiod_usteps; i++) {
wait(ustep);
}
}
}
};
#endif // SC_CLK_H
|
#include <systemc.h>
SC_MODULE( tb )
{
sc_in<bool> clk;
sc_out<bool> rst;
sc_out< sc_int<16> > inp;
sc_out<bool> inp_vld;
sc_in<bool> inp_rdy;
sc_in< sc_int<16> > outp;
sc_in<bool> outp_vld;
sc_out<bool> outp_rdy;
void source();
void sink();
FILE *outfp;
sc_time start_time[64], end_time[64], clock_period;
SC_HAS_PROCESS( tb );
tb( sc_module_name nm );
};
|
#pragma once
#include <systemc.h>
#include "../../UTIL/debug_util.h"
#include "../../UTIL/fifo.h"
#define x12x2_size 130
SC_MODULE(x1_multiplier)
{
// input :
sc_in<sc_bv<320>> IN_RX0;
sc_in<bool> SELECT_HIGHER_BITS_RX0;
sc_in<bool> SIGNED_RES_RX0;
sc_in<bool> X02X1_EMPTY_SX0;
sc_in<bool> X12X2_POP_SX2;
// output :
sc_out<sc_bv<128>> RES_RX1;
sc_out<bool> SELECT_HIGHER_BITS_RX1;
sc_out<bool> SIGNED_RES_RX1;
sc_out<bool> X12X2_EMPTY_SX1;
sc_out<bool> X02X1_POP_SX1;
// General interace :
sc_in_clk CLK;
sc_in<bool> RESET;
//data from input
sc_signal<sc_bv<64>> M[5];
//Res from stage 6
sc_signal<sc_bv<64>> product_s6[4];
//Res from stage 7
sc_signal<sc_bv<64>> product_s7[2];
//Res from stage 8
sc_signal<sc_bv<64>> product_s8[2];
// fifo x12x2
sc_signal<sc_bv<x12x2_size>> x12x2_din_sx1;
sc_signal<sc_bv<x12x2_size>> x12x2_dout_sx1;
sc_signal<bool> x12x2_full_sx1;
sc_signal<bool> x12x2_push_sx1;
fifo<x12x2_size> fifo_inst;
void parse_data();
//stage 6 (2 CSA)
void CSA1();
void CSA2();
//stage 7 (1 CSA remind product_s6 M3)
void CSA3();
//stage 8 (1 CSA)
void CSA4();
void manage_fifo();
void fifo_concat();
void fifo_unconcat();
void trace(sc_trace_file* tf);
SC_CTOR(x1_multiplier) :
fifo_inst("x12x2")
{
fifo_inst.DIN_S(x12x2_din_sx1);
fifo_inst.DOUT_R(x12x2_dout_sx1);
fifo_inst.EMPTY_S(X12X2_EMPTY_SX1);
fifo_inst.FULL_S(x12x2_full_sx1);
fifo_inst.PUSH_S(x12x2_push_sx1);
fifo_inst.POP_S(X12X2_POP_SX2);
fifo_inst.CLK(CLK);
fifo_inst.RESET_N(RESET);
SC_METHOD(parse_data);
sensitive << IN_RX0;
SC_METHOD(CSA1);
sensitive << M[0] << M[1] << M[2];
SC_METHOD(CSA3);
sensitive << product_s6[0] << product_s6[1] << M[3];
SC_METHOD(CSA4);
sensitive << product_s7[0] << product_s7[1] << M[4];
SC_METHOD(manage_fifo);
sensitive << x12x2_full_sx1 << X02X1_EMPTY_SX0;
SC_METHOD(fifo_concat);
sensitive << SELECT_HIGHER_BITS_RX0 << product_s8[0] << product_s8[1] << SIGNED_RES_RX0;
SC_METHOD(fifo_unconcat);
sensitive << x12x2_dout_sx1;
}
}; |
#ifndef ACCNAME_H
#define ACCNAME_H
#include <systemc.h>
#include "tensorflow/lite/delegates/utils/secda_tflite/sysc_integrator/sysc_types.h"
#ifndef __SYNTHESIS__
#define DWAIT(x) wait(x)
#else
#define DWAIT(x)
#endif
#define ACCNAME TOY_ADD
#define ACC_DTYPE sc_uint
#define ACC_C_DTYPE unsigned int
#define STOPPER -1
#define IN_BUF_LEN 4096
#define WE_BUF_LEN 8192
#define SUMS_BUF_LEN 1024
#define MAX 2147483647
#define MIN -2147483648
#define POS 1073741824
#define NEG -1073741823
#define DIVMAX 2147483648
#define MAX8 127
#define MIN8 -128
SC_MODULE(ACCNAME) {
sc_in<bool> clock;
sc_in<bool> reset;
sc_fifo_in<DATA> din1;
sc_fifo_out<DATA> dout1;
// GEMM 1 Inputs
ACC_DTYPE<32> A1[IN_BUF_LEN];
ACC_DTYPE<32> A2[IN_BUF_LEN];
ACC_DTYPE<32> B1[IN_BUF_LEN];
ACC_DTYPE<32> B2[IN_BUF_LEN];
ACC_DTYPE<32> C1[IN_BUF_LEN * 4];
ACC_DTYPE<32> C2[IN_BUF_LEN * 4];
int qm;
sc_int<8> shift;
#ifndef __SYNTHESIS__
sc_signal<int, SC_MANY_WRITERS> lenX;
sc_signal<int, SC_MANY_WRITERS> lenY;
sc_signal<bool, SC_MANY_WRITERS> computeX;
sc_signal<bool, SC_MANY_WRITERS> computeY;
sc_signal<bool, SC_MANY_WRITERS> readX;
sc_signal<bool, SC_MANY_WRITERS> readY;
sc_signal<bool, SC_MANY_WRITERS> writeX;
sc_signal<bool, SC_MANY_WRITERS> writeY;
#else
sc_signal<int> lenX;
sc_signal<int> lenY;
sc_signal<bool> computeX;
sc_signal<bool> computeY;
sc_signal<bool> readX;
sc_signal<bool> readY;
sc_signal<bool> writeX;
sc_signal<bool> writeY;
#endif
void Control();
void Data_Read();
void PE_Add();
void Data_Write();
int Quantised_Multiplier(int, int, sc_int<8>);
SC_HAS_PROCESS(ACCNAME);
ACCNAME(sc_module_name name_) : sc_module(name_) {
SC_CTHREAD(Control, clock);
reset_signal_is(reset, true);
SC_CTHREAD(Data_Read, clock);
reset_signal_is(reset, true);
SC_CTHREAD(PE_Add, clock);
reset_signal_is(reset, true);
SC_CTHREAD(Data_Write, clock);
reset_signal_is(reset, true);
#pragma HLS RESOURCE variable = din1 core = AXI4Stream metadata = \
"-bus_bundle S_AXIS_DATA1" port_map = { \
{din1_0 TDATA } { \
din1_1 TLAST } }
#pragma HLS RESOURCE variable = dout1 core = AXI4Stream metadata = \
"-bus_bundle M_AXIS_DATA1" port_map = { \
{dout1_0 TDATA } { \
dout1_1 TLAST } }
}
};
#endif |
/**********************************************************************
Filename: E_fir_pe.h
Purpose : FPGA Emulated PE of Systolic FIR filter
Author : [email protected]
History : Mar. 2024, First release
***********************************************************************/
#ifndef _E_FIR_PE_H_
#define _E_FIR_PE_H_
#include <systemc.h>
// Includes for accessing Arduino via serial port
#include <stdio.h>
#include <string.h>
#include <unistd.h>
#include <fcntl.h>
#include <termios.h>
SC_MODULE(E_fir_pe)
{
sc_in<bool> clk;
sc_in<bool> Rdy;
sc_out<bool> Vld;
sc_in<sc_uint<8> > Cin;
sc_in<sc_uint<4> > Xin;
sc_out<sc_uint<4> > Xout;
sc_in<sc_uint<4> > Yin;
sc_out<sc_uint<4> > Yout;
#define N_TX 3
#define N_RX 2
void pe_thread(void)
{
uint8_t x, y, txPacket[N_TX], rxPacket[N_RX];
while(true)
{
// Positive edge Clock
wait(clk.posedge_event());
txPacket[0] = (uint8_t)Cin.read(); // Cin
txPacket[1] = (uint8_t)(Yin.read())<<4 | (uint8_t)(Xin.read()); // Yin | Xin
txPacket[2] = (uint8_t)Rdy.read();
// Send to Emulator
for (int i=0; i<N_TX; i++)
{
x = txPacket[i];
while(write(fd, &x, 1)<=0) usleep(1);
}
// Receive from Emulator
for (int i=0; i<N_RX; i++)
{
while(read(fd, &y, 1)<=0) usleep(1);
rxPacket[i] = y;
}
Yout.write((sc_uint<4>)(rxPacket[0]>>4));
Xout.write((sc_uint<4>)(rxPacket[0] & 0x0F));
Vld.write(rxPacket[1]? true:false);
}
}
// Arduino Serial IF
int fd; // Serial port file descriptor
struct termios options; // Serial port setting
SC_CTOR(E_fir_pe):
clk("clk"),
Cin("Cin"), Xin("Xin"), Xout("Xout"),
Yin("Yin"), Yout("Yout")
{
SC_THREAD(pe_thread);
sensitive << clk;
// Arduino DUT
//fd = open("/dev/ttyACM0", O_RDWR | O_NDELAY | O_NOCTTY);
fd = open("/dev/ttyACM0", O_RDWR | O_NOCTTY);
if (fd < 0)
{
perror("Error opening serial port");
return;
}
// Set up serial port
options.c_cflag = B115200 | CS8 | CLOCAL | CREAD;
options.c_iflag = IGNPAR;
options.c_oflag = 0;
options.c_lflag = 0;
// Apply the settings
tcflush(fd, TCIFLUSH);
tcsetattr(fd, TCSANOW, &options);
// Establish Contact
int len = 0;
char rx;
while(!len)
len = read(fd, &rx, 1);
if (rx=='A')
write(fd, &rx, 1);
printf("Connection established...\n");
}
~E_fir_pe(void)
{
}
};
#endif
|
/*******************************************************************************
Vendor: GoodKook, [email protected]
Associated Filename: sc_dffrs_TB.cpp
Purpose: Testbench
Revision History: Aug. 1, 2024
*******************************************************************************/
#ifndef _SC_DFFRS_TB_H_
#define _SC_DFFRS_TB_H_
#include <systemc.h>
#include "Vdffrs.h" // Verilated DUT
SC_MODULE(sc_dffrs_TB)
{
sc_clock clk;
sc_signal<bool> r, s, d, q;
Vdffrs* u_Vdffrs;
sc_trace_file* fp; // VCD file
SC_CTOR(sc_dffrs_TB): // constructor
clk("clk", 100, SC_NS, 0.5, 0.0, SC_NS, false)
{
// instantiate DUT
u_Vdffrs = new Vdffrs("u_Vdffrs");
// Binding
u_Vdffrs->clk(clk);
u_Vdffrs->r(r);
u_Vdffrs->s(s);
u_Vdffrs->d(d);
u_Vdffrs->q(q);
SC_THREAD(test_generator);
sensitive << clk;
// VCD Trace
fp = sc_create_vcd_trace_file("sc_dffrs_TB");
sc_trace(fp, clk, "clk");
sc_trace(fp, r, "r");
sc_trace(fp, s, "s");
sc_trace(fp, d, "d");
sc_trace(fp, q, "q");
}
void test_generator()
{
int test_count =0;
r.write(1);
s.write(1);
d.write(0);
while(true)
{
wait(clk.posedge_event());
wait(clk.negedge_event());
s.write(0);
wait(clk.posedge_event());
s.write(1);
wait(clk.negedge_event());
r.write(0);
wait(clk.posedge_event());
r.write(1);
wait(clk.posedge_event());
d = 1;
wait(clk.posedge_event());
d = false;
wait(clk.negedge_event());
d = 1;
wait(clk.posedge_event());
d = 0;
wait(clk.posedge_event());
d = 1;
wait(clk.posedge_event());
wait(clk.posedge_event());
r.write(1);
s.write(1);
d.write(1);
wait(clk.posedge_event());
r.write(0);
s.write(0);
//d.write(0);
wait(clk.posedge_event());
r.write(1);
s.write(1);
d.write(0);
wait(clk.posedge_event());
s.write(0);
wait(clk.posedge_event());
s.write(1);
wait(clk.posedge_event());
// Ending stimulus
wait(clk.posedge_event());
wait(clk.posedge_event());
sc_close_vcd_trace_file(fp);
sc_stop();
}
}
};
#endif
|
//---------------------------------------------------------------------------------------
//
// DISTRIBUTED HEMPS - version 5.0
//
// Research group: GAPH-PUCRS - contact [email protected]
//
// Distribution: September 2013
//
// Source name: queue.h
//
// Brief description: Methods of process control queue occupancy
//
//---------------------------------------------------------------------------------------
#ifndef _fila_h
#define _fila_h
#include <systemc.h>
#include "packet.h"
SC_MODULE(fila){
sc_in<bool > clock;
sc_in<bool > reset_n;
sc_in<regflit > data_in;
sc_in<bool > rx;
sc_out<bool > credit_o;
//sc_out<bool > ack_rx;
sc_out<bool > h;
sc_in<bool > ack_h;
sc_out<bool > data_av;
sc_out<regflit > data;
sc_in<bool > data_ack;
sc_out<bool > sender;
enum fila_out{S_INIT, S_PAYLOAD, S_SENDHEADER, S_HEADER, S_END, S_END2};
sc_signal<fila_out > EA, PE;
regflit buffer_in[BUFFER_TAM];
sc_signal<sc_uint<4> > first,last;
sc_signal<bool > tem_espaco_na_fila, auxack_rx;
sc_signal<regflit > counter_flit;
void in_proc_FSM();
void in_proc_updPtr();
void out_proc_data();
void out_proc_FSM();
void change_state_sequ();
void change_state_comb();
SC_CTOR(fila){
SC_METHOD(in_proc_FSM);
sensitive << reset_n.neg();
sensitive << clock.pos();
SC_METHOD(out_proc_data);
sensitive << first;
sensitive << last;
SC_METHOD(out_proc_FSM);
sensitive << reset_n.neg();
sensitive << clock.pos();
SC_METHOD(in_proc_updPtr);
sensitive << reset_n.neg();
sensitive << clock.neg();
}
};
#endif
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2017 Cadence Design Systems, Inc. All rights reserved worldwide.
//
// The code contained herein is the proprietary and confidential information
// of Cadence or its licensors, and is supplied subject to a previously
// executed license and maintenance agreement between Cadence and customer.
// This code is intended for use with Cadence high-level synthesis tools and
// may not be used with other high-level synthesis tools. Permission is only
// granted to distribute the code as indicated. Cadence grants permission for
// customer to distribute a copy of this code to any partner to aid in designing
// or verifying the customer's intellectual property, as long as such
// distribution includes a restriction of no additional distributions from the
// partner, unless the partner receives permission directly from Cadence.
//
// ALL CODE FURNISHED BY CADENCE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY
// KIND, AND CADENCE SPECIFICALLY DISCLAIMS ANY WARRANTY OF NONINFRINGEMENT,
// FITNESS FOR A PARTICULAR PURPOSE OR MERCHANTABILITY. CADENCE SHALL NOT BE
// LIABLE FOR ANY COSTS OF PROCUREMENT OF SUBSTITUTES, LOSS OF PROFITS,
// INTERRUPTION OF BUSINESS, OR FOR ANY OTHER SPECIAL, CONSEQUENTIAL OR
// INCIDENTAL DAMAGES, HOWEVER CAUSED, WHETHER FOR BREACH OF WARRANTY,
// CONTRACT, TORT, NEGLIGENCE, STRICT LIABILITY OR OTHERWISE.
//
////////////////////////////////////////////////////////////////////////////////
#include <systemc.h> // SystemC definitions
#include "system.h" // Top-level System module header file
static System * m_system = NULL; // The pointer that holds the top-level System module instance.
void esc_elaborate() // This function is required by Stratus to support SystemC-Verilog
{ // cosimulation. It instances the top-level module.
m_system = new System( "system" );
}
void esc_cleanup() // This function is called at the end of simulation by the
{ // Stratus co-simulation hub. It should delete the top-level
delete m_system; // module instance.
}
int sc_main( int argc, char ** argv ) // This function is called by the SystemC kernel for pure SystemC simulations
{
esc_initialize( argc, argv ); // esc_initialize() passes in the cmd-line args. This initializes the Stratus simulation
// environment (such as opening report files for later logging and analysis).
esc_elaborate(); // esc_elaborate() (defined above) creates the top-level module instance. In a SystemC-Verilog
// co-simulation, this is called during cosim initialization rather than from sc_main.
sc_start(); // Starts the simulation. Returns when a module calls esc_stop(), which finishes the simulation.
// esc_cleanup() (defined above) is automatically called before sc_start() returns.
return 0; // Returns the status of the simulation. Required by most C compilers.
}
|
// Generated by stratus_hls 17.20-p100 (88533.190925)
// Thu Nov 19 00:46:16 2020
// from dut.cc
#ifndef CYNTH_PART_dut_dut_rtl_h
#define CYNTH_PART_dut_dut_rtl_h
#include "systemc.h"
/* Include declarations of instantiated parts. */
#include "dut_Div_64Ux2U_32U_4.h"
/* Declaration of the synthesized module. */
struct dut : public sc_module {
sc_in<bool > clk;
sc_in<bool > rst;
sc_out<bool > din_busy;
sc_in<bool > din_vld;
sc_in<sc_uint<8> > din_data_a;
sc_in<sc_uint<8> > din_data_b;
sc_in<sc_uint<8> > din_data_c;
sc_in<sc_uint<8> > din_data_d;
sc_in<sc_uint<8> > din_data_e;
sc_in<sc_uint<8> > din_data_f;
sc_in<sc_uint<8> > din_data_g;
sc_in<sc_uint<8> > din_data_h;
sc_in<bool > dout_busy;
sc_out<bool > dout_vld;
sc_out<sc_uint<32> > dout_data;
dut( sc_module_name name );
SC_HAS_PROCESS(dut);
sc_signal<bool > dout_m_req_m_prev_trig_req;
sc_signal<sc_uint<1> > dut_Xor_1Ux1U_1U_4_14_out1;
sc_signal<bool > dout_m_unacked_req;
sc_signal<sc_uint<1> > dut_Or_1Ux1U_1U_4_15_out1;
sc_signal<sc_uint<1> > dut_And_1Ux1U_1U_4_12_out1;
sc_signal<sc_uint<1> > dut_And_1Ux1U_1U_4_10_out1;
sc_signal<sc_uint<1> > dut_Not_1U_1U_4_9_out1;
sc_signal<sc_uint<1> > dut_And_1Ux1U_1U_4_11_out1;
sc_signal<sc_uint<1> > dut_N_Muxb_1_2_1_4_1_out1;
sc_signal<sc_uint<1> > dut_And_1Ux1U_1U_4_5_out1;
sc_signal<sc_uint<1> > dut_Not_1U_1U_4_4_out1;
sc_signal<sc_uint<1> > dut_And_1Ux1U_1U_4_3_out1;
sc_signal<sc_uint<1> > dut_Or_1Ux1U_1U_4_2_out1;
sc_signal<bool > din_m_unvalidated_req;
sc_signal<sc_uint<1> > dut_Or_1Ux1U_1U_4_7_out1;
sc_signal<sc_uint<2> > global_state_next;
sc_signal<sc_uint<1> > dut_Or_1Ux1U_1U_4_6_out1;
sc_signal<sc_uint<16> > dut_Mul_8Ux8U_16U_4_35_out1;
sc_signal<sc_uint<8> > dut_Mul_8Ux8U_16U_4_35_in1;
sc_signal<sc_uint<8> > dut_Mul_8Ux8U_16U_4_35_in2;
sc_signal<sc_uint<9> > dut_Mul_32Ux9U_32U_4_34_in1;
sc_signal<sc_uint<9> > dut_Add_8Ux8U_9U_4_38_out1;
sc_signal<sc_uint<32> > dut_Mul_32Ux9U_32U_4_34_in2;
sc_signal<sc_uint<1> > gs_ctrl2;
sc_signal<sc_uint<32> > dut_Mul_33Ux32U_64U_4_33_in1;
sc_signal<sc_uint<32> > dut_Add_32Ux32U_32U_4_44_out1;
sc_signal<sc_uint<33> > dut_Mul_33Ux32U_64U_4_33_in2;
sc_signal<sc_uint<33> > dut_Add_32Ux16U_33U_4_45_out1;
sc_signal<sc_uint<32> > dut_Mul_32Ux10U_32U_4_32_out1;
sc_signal<sc_uint<10> > dut_Mul_32Ux10U_32U_4_32_in1;
sc_signal<sc_uint<32> > dut_Mul_32Ux10U_32U_4_32_in2;
sc_signal<sc_uint<1> > gs_ctrl0;
sc_signal<sc_uint<33> > dut_Add_32Ux17U_33U_4_41_out1;
sc_signal<sc_uint<9> > dut_Add_8Ux8U_9U_4_31_out1;
sc_signal<sc_uint<10> > dut_Add_9Ux8U_10U_4_30_out1;
sc_signal<sc_uint<10> > dut_Add_9Ux8U_10U_4_29_out1;
sc_signal<sc_uint<8> > din_m_stall_reg_h;
sc_signal<sc_uint<8> > din_m_stall_reg_g;
sc_signal<sc_uint<9> > dut_Add_8Ux8U_9U_4_26_out1;
sc_signal<sc_uint<9> > dut_Add_8Ux8U_9U_4_25_out1;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_24_out1;
sc_signal<sc_uint<8> > din_m_stall_reg_f;
sc_signal<sc_uint<8> > din_m_stall_reg_c;
sc_signal<sc_uint<8> > din_m_stall_reg_e;
sc_signal<sc_uint<8> > din_m_stall_reg_d;
sc_signal<sc_uint<8> > din_m_stall_reg_b;
sc_signal<bool > din_m_stall_reg_full;
sc_signal<sc_uint<8> > din_m_stall_reg_a;
sc_signal<sc_uint<64> > dut_Mul_33Ux32U_64U_4_33_out1;
sc_signal<sc_uint<32> > dut_Mul_32Ux9U_32U_4_34_out1;
sc_signal<sc_uint<32> > s_reg_29;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_28_out1;
sc_signal<sc_uint<8> > s_reg_28;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_27_out1;
sc_signal<sc_uint<8> > s_reg_27;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_23_out1;
sc_signal<sc_uint<8> > s_reg_26;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_22_out1;
sc_signal<sc_uint<8> > s_reg_25;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_21_out1;
sc_signal<sc_uint<8> > s_reg_24;
sc_signal<sc_uint<17> > dut_Add_16Ux16U_17U_4_36_out1;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_20_out1;
sc_signal<sc_uint<17> > s_reg_23;
sc_signal<sc_uint<9> > dut_Add_8Ux8U_9U_4_39_out1;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_19_out1;
sc_signal<sc_uint<9> > s_reg_22;
sc_signal<sc_uint<1> > s_reg_21_stage0;
sc_signal<sc_uint<1> > cycle6_state;
sc_signal<sc_uint<1> > dut_And_1Ux1U_1U_4_16_out1;
sc_signal<sc_uint<1> > dut_Not_1U_1U_4_17_out1;
sc_signal<sc_uint<1> > cycle3_state;
sc_signal<sc_uint<1> > s_reg_21;
sc_signal<bool > dout_m_req_m_trig_req;
sc_signal<sc_uint<2> > global_state;
sc_signal<bool > din_m_busy_req_0;
sc_signal<sc_uint<64> > s_reg_30;
sc_signal<sc_uint<2> > dut_Div_64Ux2U_32U_4_47_in1;
sc_signal<sc_uint<32> > dut_Div_64Ux2U_32U_4_47_out1;
sc_signal<sc_uint<1> > stall0;
dut_Div_64Ux2U_32U_4 *dut_Div_64Ux2U_32U_4_47;
void drive_dout_data();
void drive_din_m_busy_req_0();
void drive_dout_m_req_m_trig_req();
void drive_stall0();
void drive_s_reg_21();
void drive_s_reg_22();
void drive_s_reg_23();
void drive_s_reg_24();
void drive_s_reg_25();
void drive_s_reg_26();
void drive_s_reg_27();
void drive_s_reg_28();
void drive_s_reg_29();
void drive_s_reg_30();
void dut_N_Mux_8_2_0_4_19();
void dut_N_Mux_8_2_0_4_20();
void dut_N_Mux_8_2_0_4_21();
void dut_N_Mux_8_2_0_4_22();
void dut_N_Mux_8_2_0_4_23();
void dut_N_Mux_8_2_0_4_24();
void dut_Add_8Ux8U_9U_4_25();
void dut_Add_8Ux8U_9U_4_26();
void dut_N_Mux_8_2_0_4_27();
void dut_N_Mux_8_2_0_4_28();
void dut_Add_9Ux8U_10U_4_29();
void dut_Add_9Ux8U_10U_4_30();
void dut_Add_8Ux8U_9U_4_31();
void drive_dut_Mul_32Ux10U_32U_4_32_in2();
void drive_dut_Mul_32Ux10U_32U_4_32_in1();
void dut_Mul_32Ux10U_32U_4_32();
void drive_dut_Mul_33Ux32U_64U_4_33_in2();
void drive_dut_Mul_33Ux32U_64U_4_33_in1();
void dut_Mul_33Ux32U_64U_4_33();
void drive_dut_Mul_32Ux9U_32U_4_34_in2();
void drive_dut_Mul_32Ux9U_32U_4_34_in1();
void dut_Mul_32Ux9U_32U_4_34();
void drive_dut_Mul_8Ux8U_16U_4_35_in2();
void drive_dut_Mul_8Ux8U_16U_4_35_in1();
void dut_Mul_8Ux8U_16U_4_35();
void dut_Add_16Ux16U_17U_4_36();
void dut_Add_8Ux8U_9U_4_38();
void dut_Add_8Ux8U_9U_4_39();
void dut_Add_32Ux17U_33U_4_41();
void dut_Add_32Ux32U_32U_4_44();
void dut_Add_32Ux16U_33U_4_45();
void drive_dut_Div_64Ux2U_32U_4_47_in1();
void drive_s_reg_21_stage0();
void drive_cycle3_state();
void drive_cycle6_state();
void drive_global_state();
void drive_global_state_next();
void drive_gs_ctrl0();
void drive_gs_ctrl2();
void drive_din_busy();
void dut_Or_1Ux1U_1U_4_2();
void dut_And_1Ux1U_1U_4_3();
void dut_Not_1U_1U_4_4();
void dut_And_1Ux1U_1U_4_5();
void dut_Or_1Ux1U_1U_4_6();
void dut_Or_1Ux1U_1U_4_7();
void drive_din_m_unvalidated_req();
void dut_N_Muxb_1_2_1_4_1();
void drive_din_m_stall_reg_h();
void drive_din_m_stall_reg_g();
void drive_din_m_stall_reg_f();
void drive_din_m_stall_reg_e();
void drive_din_m_stall_reg_d();
void drive_din_m_stall_reg_c();
void drive_din_m_stall_reg_b();
void drive_din_m_stall_reg_a();
void dut_Not_1U_1U_4_9();
void dut_And_1Ux1U_1U_4_10();
void dut_And_1Ux1U_1U_4_11();
void drive_din_m_stall_reg_full();
void dut_And_1Ux1U_1U_4_12();
void drive_dout_vld();
void dut_Or_1Ux1U_1U_4_15();
void drive_dout_m_unacked_req();
void dut_And_1Ux1U_1U_4_16();
void dut_Xor_1Ux1U_1U_4_14();
void drive_dout_m_req_m_prev_trig_req();
void dut_Not_1U_1U_4_17();
};
#endif
|
/* Copyright 2017 Pedro Cuadra <[email protected]> & Meghadoot Gardi
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License. */
#ifndef DECODER_H_
#define DECODER_H_
#include<systemc.h>
SC_MODULE (decoder) {
sc_in<bool> a, b, carry_in;
sc_out<bool> sum, carry_out;
void prc_decoder();
SC_CTOR (decoder) {
SC_METHOD (prc_decoder);
sensitive << a << b << carry_in;
}
};
#endif
|
/**
#define meta ...
prInt32f("%s\n", meta);
**/
/*
All rights reserved to Alireza Poshtkohi (c) 1999-2023.
Email: [email protected]
Website: http://www.poshtkohi.info
*/
#ifndef __s8_h__
#define __s8_h__
#include <systemc.h>
SC_MODULE(s8)
{
sc_in<sc_uint<6> > stage1_input;
sc_out<sc_uint<4> > stage1_output;
void s8_box();
SC_CTOR(s8)
{
SC_METHOD(s8_box);
sensitive << stage1_input;
}
};
#endif
|
// Generated by stratus_hls 17.20-p100 (88533.190925)
// Tue Nov 17 14:07:23 2020
// from dut.cc
#ifndef CYNTH_PART_dut_dut_rtl_h
#define CYNTH_PART_dut_dut_rtl_h
#include "systemc.h"
/* Include declarations of instantiated parts. */
/* Declaration of the synthesized module. */
struct dut : public sc_module {
sc_in<bool > clk;
sc_in<bool > rst;
sc_out<bool > din_busy;
sc_in<bool > din_vld;
sc_in<sc_uint<8> > din_data;
sc_in<bool > dout_busy;
sc_out<bool > dout_vld;
sc_out<sc_uint<11> > dout_data;
dut( sc_module_name name );
SC_HAS_PROCESS(dut);
sc_signal<bool > dout_m_req_m_prev_trig_req;
sc_signal<sc_uint<1> > dut_Xor_1Ux1U_1U_4_9_out1;
sc_signal<bool > dout_m_unacked_req;
sc_signal<sc_uint<1> > dut_Or_1Ux1U_1U_4_10_out1;
sc_signal<sc_uint<1> > dut_N_Muxb_1_2_3_4_1_out1;
sc_signal<sc_uint<1> > dut_And_1Ux1U_1U_4_5_out1;
sc_signal<sc_uint<1> > dut_Not_1U_1U_4_4_out1;
sc_signal<sc_uint<1> > dut_Or_1Ux1U_1U_4_2_out1;
sc_signal<bool > din_m_unvalidated_req;
sc_signal<sc_uint<1> > dut_And_1Ux1U_1U_4_3_out1;
sc_signal<sc_uint<7> > global_state_next;
sc_signal<sc_uint<7> > sreg_1;
sc_signal<sc_uint<8> > dut_N_Mux_8_64_2_4_144_out1;
sc_signal<sc_uint<8> > dut_N_Mux_8_64_1_4_143_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux1U_1U_4_141_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux2U_1U_4_138_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux2U_1U_4_136_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux3U_1U_4_134_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux3U_1U_4_132_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux3U_1U_4_130_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux3U_1U_4_128_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux5U_1U_4_126_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux5U_1U_4_124_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux5U_1U_4_122_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux5U_1U_4_120_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux5U_1U_4_118_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux5U_1U_4_116_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux5U_1U_4_114_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux5U_1U_4_112_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux5U_1U_4_110_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux5U_1U_4_108_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux5U_1U_4_106_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux5U_1U_4_104_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux5U_1U_4_102_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux5U_1U_4_100_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux5U_1U_4_98_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux5U_1U_4_96_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux5U_1U_4_94_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux5U_1U_4_92_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux5U_1U_4_90_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux5U_1U_4_88_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux5U_1U_4_86_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux5U_1U_4_84_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux5U_1U_4_82_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux5U_1U_4_80_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux6U_1U_4_78_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux6U_1U_4_76_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux6U_1U_4_74_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux6U_1U_4_72_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux6U_1U_4_70_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux6U_1U_4_68_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux6U_1U_4_66_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux6U_1U_4_64_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux6U_1U_4_62_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux6U_1U_4_60_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux6U_1U_4_58_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux6U_1U_4_56_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux6U_1U_4_54_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux6U_1U_4_52_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux6U_1U_4_50_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux6U_1U_4_48_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux6U_1U_4_46_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux6U_1U_4_44_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux6U_1U_4_42_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux6U_1U_4_40_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux6U_1U_4_38_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux6U_1U_4_36_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux6U_1U_4_34_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux6U_1U_4_32_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux6U_1U_4_30_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux6U_1U_4_28_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux6U_1U_4_26_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux6U_1U_4_24_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux6U_1U_4_22_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux6U_1U_4_20_out1;
sc_signal<sc_uint<8> > s_reg_257;
sc_signal<sc_uint<1> > dut_Equal_6Ux6U_1U_4_18_out1;
sc_signal<sc_uint<6> > s_reg_256;
sc_signal<sc_int<7> > dut_Add_7Sx2S_8S_4_15_in2;
sc_signal<sc_uint<1> > dut_OrReduction_6U_1U_4_14_out1;
sc_signal<sc_uint<1> > dut_Equal_6Ux6U_1U_4_13_out1;
sc_signal<sc_uint<6> > dut_Equal_6Ux6U_1U_4_13_in2;
sc_signal<sc_uint<1> > gs_ctrl0;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_17_out1;
sc_signal<sc_uint<8> > s_reg_255;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_142_out1;
sc_signal<sc_uint<8> > s_reg_254;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_139_out1;
sc_signal<sc_uint<8> > s_reg_253;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_137_out1;
sc_signal<sc_uint<8> > s_reg_252;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_135_out1;
sc_signal<sc_uint<8> > s_reg_251;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_133_out1;
sc_signal<sc_uint<8> > s_reg_250;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_131_out1;
sc_signal<sc_uint<8> > s_reg_249;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_129_out1;
sc_signal<sc_uint<8> > s_reg_248;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_127_out1;
sc_signal<sc_uint<8> > s_reg_247;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_125_out1;
sc_signal<sc_uint<8> > s_reg_246;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_123_out1;
sc_signal<sc_uint<8> > s_reg_245;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_121_out1;
sc_signal<sc_uint<8> > s_reg_244;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_119_out1;
sc_signal<sc_uint<8> > s_reg_243;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_117_out1;
sc_signal<sc_uint<8> > s_reg_242;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_115_out1;
sc_signal<sc_uint<8> > s_reg_241;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_113_out1;
sc_signal<sc_uint<8> > s_reg_240;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_111_out1;
sc_signal<sc_uint<8> > s_reg_239;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_109_out1;
sc_signal<sc_uint<8> > s_reg_238;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_107_out1;
sc_signal<sc_uint<8> > s_reg_237;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_105_out1;
sc_signal<sc_uint<8> > s_reg_236;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_103_out1;
sc_signal<sc_uint<8> > s_reg_235;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_101_out1;
sc_signal<sc_uint<8> > s_reg_234;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_99_out1;
sc_signal<sc_uint<8> > s_reg_233;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_97_out1;
sc_signal<sc_uint<8> > s_reg_232;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_95_out1;
sc_signal<sc_uint<8> > s_reg_231;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_93_out1;
sc_signal<sc_uint<8> > s_reg_230;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_91_out1;
sc_signal<sc_uint<8> > s_reg_229;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_89_out1;
sc_signal<sc_uint<8> > s_reg_228;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_87_out1;
sc_signal<sc_uint<8> > s_reg_227;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_85_out1;
sc_signal<sc_uint<8> > s_reg_226;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_83_out1;
sc_signal<sc_uint<8> > s_reg_225;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_81_out1;
sc_signal<sc_uint<8> > s_reg_224;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_79_out1;
sc_signal<sc_uint<8> > s_reg_223;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_77_out1;
sc_signal<sc_uint<8> > s_reg_222;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_75_out1;
sc_signal<sc_uint<8> > s_reg_221;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_73_out1;
sc_signal<sc_uint<8> > s_reg_220;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_71_out1;
sc_signal<sc_uint<8> > s_reg_219;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_69_out1;
sc_signal<sc_uint<8> > s_reg_218;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_67_out1;
sc_signal<sc_uint<8> > s_reg_217;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_65_out1;
sc_signal<sc_uint<8> > s_reg_216;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_63_out1;
sc_signal<sc_uint<8> > s_reg_215;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_61_out1;
sc_signal<sc_uint<8> > s_reg_214;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_59_out1;
sc_signal<sc_uint<8> > s_reg_213;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_57_out1;
sc_signal<sc_uint<8> > s_reg_212;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_55_out1;
sc_signal<sc_uint<8> > s_reg_211;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_53_out1;
sc_signal<sc_uint<8> > s_reg_210;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_51_out1;
sc_signal<sc_uint<8> > s_reg_209;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_49_out1;
sc_signal<sc_uint<8> > s_reg_208;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_47_out1;
sc_signal<sc_uint<8> > s_reg_207;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_45_out1;
sc_signal<sc_uint<8> > s_reg_206;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_43_out1;
sc_signal<sc_uint<8> > s_reg_205;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_41_out1;
sc_signal<sc_uint<8> > s_reg_204;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_39_out1;
sc_signal<sc_uint<8> > s_reg_203;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_37_out1;
sc_signal<sc_uint<8> > s_reg_202;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_35_out1;
sc_signal<sc_uint<8> > s_reg_201;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_33_out1;
sc_signal<sc_uint<8> > s_reg_200;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_31_out1;
sc_signal<sc_uint<8> > s_reg_199;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_29_out1;
sc_signal<sc_uint<8> > s_reg_198;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_27_out1;
sc_signal<sc_uint<8> > s_reg_197;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_25_out1;
sc_signal<sc_uint<8> > s_reg_196;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_23_out1;
sc_signal<sc_uint<8> > s_reg_195;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_21_out1;
sc_signal<sc_uint<8> > s_reg_194;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_19_out1;
sc_signal<sc_uint<8> > s_reg_193;
sc_signal<sc_uint<8> > dut_N_Mux_8_2_0_4_16_out1;
sc_signal<sc_uint<8> > s_reg_192;
sc_signal<sc_uint<1> > dut_Not_1U_1U_4_6_out1;
sc_signal<sc_uint<1> > dut_And_1Ux1U_1U_4_11_out1;
sc_signal<sc_uint<1> > dut_Not_1U_1U_4_12_out1;
sc_signal<bool > dout_m_req_m_trig_req;
sc_signal<sc_uint<1> > dut_LessThan_8Sx8S_1U_4_140_out1;
sc_signal<bool > din_m_busy_req_0;
sc_signal<sc_uint<9> > dut_Add_8Ux8U_9U_4_145_out1;
sc_signal<sc_int<8> > dut_Add_7Sx2S_8S_4_15_out1;
sc_signal<sc_int<10> > dout_data_slice;
sc_signal<sc_uint<7> > global_state;
sc_signal<sc_uint<1> > stall0;
void drive_dout_data();
void drive_din_m_busy_req_0();
void drive_dout_m_req_m_trig_req();
void drive_stall0();
void drive_s_reg_192();
void drive_s_reg_193();
void drive_s_reg_194();
void drive_s_reg_195();
void drive_s_reg_196();
void drive_s_reg_197();
void drive_s_reg_198();
void drive_s_reg_199();
void drive_s_reg_200();
void drive_s_reg_201();
void drive_s_reg_202();
void drive_s_reg_203();
void drive_s_reg_204();
void drive_s_reg_205();
void drive_s_reg_206();
void drive_s_reg_207();
void drive_s_reg_208();
void drive_s_reg_209();
void drive_s_reg_210();
void drive_s_reg_211();
void drive_s_reg_212();
void drive_s_reg_213();
void drive_s_reg_214();
void drive_s_reg_215();
void drive_s_reg_216();
void drive_s_reg_217();
void drive_s_reg_218();
void drive_s_reg_219();
void drive_s_reg_220();
void drive_s_reg_221();
void drive_s_reg_222();
void drive_s_reg_223();
void drive_s_reg_224();
void drive_s_reg_225();
void drive_s_reg_226();
void drive_s_reg_227();
void drive_s_reg_228();
void drive_s_reg_229();
void drive_s_reg_230();
void drive_s_reg_231();
void drive_s_reg_232();
void drive_s_reg_233();
void drive_s_reg_234();
void drive_s_reg_235();
void drive_s_reg_236();
void drive_s_reg_237();
void drive_s_reg_238();
void drive_s_reg_239();
void drive_s_reg_240();
void drive_s_reg_241();
void drive_s_reg_242();
void drive_s_reg_243();
void drive_s_reg_244();
void drive_s_reg_245();
void drive_s_reg_246();
void drive_s_reg_247();
void drive_s_reg_248();
void drive_s_reg_249();
void drive_s_reg_250();
void drive_s_reg_251();
void drive_s_reg_252();
void drive_s_reg_253();
void drive_s_reg_254();
void drive_s_reg_255();
void drive_dut_Equal_6Ux6U_1U_4_13_in2();
void dut_Equal_6Ux6U_1U_4_13();
void dut_OrReduction_6U_1U_4_14();
void drive_dut_Add_7Sx2S_8S_4_15_in2();
void dut_Add_7Sx2S_8S_4_15();
void dut_N_Mux_8_2_0_4_16();
void dut_N_Mux_8_2_0_4_17();
void dut_Equal_6Ux6U_1U_4_18();
void dut_N_Mux_8_2_0_4_19();
void dut_Equal_6Ux6U_1U_4_20();
void dut_N_Mux_8_2_0_4_21();
void dut_Equal_6Ux6U_1U_4_22();
void dut_N_Mux_8_2_0_4_23();
void dut_Equal_6Ux6U_1U_4_24();
void dut_N_Mux_8_2_0_4_25();
void dut_Equal_6Ux6U_1U_4_26();
void dut_N_Mux_8_2_0_4_27();
void dut_Equal_6Ux6U_1U_4_28();
void dut_N_Mux_8_2_0_4_29();
void dut_Equal_6Ux6U_1U_4_30();
void dut_N_Mux_8_2_0_4_31();
void dut_Equal_6Ux6U_1U_4_32();
void dut_N_Mux_8_2_0_4_33();
void dut_Equal_6Ux6U_1U_4_34();
void dut_N_Mux_8_2_0_4_35();
void dut_Equal_6Ux6U_1U_4_36();
void dut_N_Mux_8_2_0_4_37();
void dut_Equal_6Ux6U_1U_4_38();
void dut_N_Mux_8_2_0_4_39();
void dut_Equal_6Ux6U_1U_4_40();
void dut_N_Mux_8_2_0_4_41();
void dut_Equal_6Ux6U_1U_4_42();
void dut_N_Mux_8_2_0_4_43();
void dut_Equal_6Ux6U_1U_4_44();
void dut_N_Mux_8_2_0_4_45();
void dut_Equal_6Ux6U_1U_4_46();
void dut_N_Mux_8_2_0_4_47();
void dut_Equal_6Ux6U_1U_4_48();
void dut_N_Mux_8_2_0_4_49();
void dut_Equal_6Ux6U_1U_4_50();
void dut_N_Mux_8_2_0_4_51();
void dut_Equal_6Ux6U_1U_4_52();
void dut_N_Mux_8_2_0_4_53();
void dut_Equal_6Ux6U_1U_4_54();
void dut_N_Mux_8_2_0_4_55();
void dut_Equal_6Ux6U_1U_4_56();
void dut_N_Mux_8_2_0_4_57();
void dut_Equal_6Ux6U_1U_4_58();
void dut_N_Mux_8_2_0_4_59();
void dut_Equal_6Ux6U_1U_4_60();
void dut_N_Mux_8_2_0_4_61();
void dut_Equal_6Ux6U_1U_4_62();
void dut_N_Mux_8_2_0_4_63();
void dut_Equal_6Ux6U_1U_4_64();
void dut_N_Mux_8_2_0_4_65();
void dut_Equal_6Ux6U_1U_4_66();
void dut_N_Mux_8_2_0_4_67();
void dut_Equal_6Ux6U_1U_4_68();
void dut_N_Mux_8_2_0_4_69();
void dut_Equal_6Ux6U_1U_4_70();
void dut_N_Mux_8_2_0_4_71();
void dut_Equal_6Ux6U_1U_4_72();
void dut_N_Mux_8_2_0_4_73();
void dut_Equal_6Ux6U_1U_4_74();
void dut_N_Mux_8_2_0_4_75();
void dut_Equal_6Ux6U_1U_4_76();
void dut_N_Mux_8_2_0_4_77();
void dut_Equal_6Ux6U_1U_4_78();
void dut_N_Mux_8_2_0_4_79();
void dut_Equal_6Ux5U_1U_4_80();
void dut_N_Mux_8_2_0_4_81();
void dut_Equal_6Ux5U_1U_4_82();
void dut_N_Mux_8_2_0_4_83();
void dut_Equal_6Ux5U_1U_4_84();
void dut_N_Mux_8_2_0_4_85();
void dut_Equal_6Ux5U_1U_4_86();
void dut_N_Mux_8_2_0_4_87();
void dut_Equal_6Ux5U_1U_4_88();
void dut_N_Mux_8_2_0_4_89();
void dut_Equal_6Ux5U_1U_4_90();
void dut_N_Mux_8_2_0_4_91();
void dut_Equal_6Ux5U_1U_4_92();
void dut_N_Mux_8_2_0_4_93();
void dut_Equal_6Ux5U_1U_4_94();
void dut_N_Mux_8_2_0_4_95();
void dut_Equal_6Ux5U_1U_4_96();
void dut_N_Mux_8_2_0_4_97();
void dut_Equal_6Ux5U_1U_4_98();
void dut_N_Mux_8_2_0_4_99();
void dut_Equal_6Ux5U_1U_4_100();
void dut_N_Mux_8_2_0_4_101();
void dut_Equal_6Ux5U_1U_4_102();
void dut_N_Mux_8_2_0_4_103();
void dut_Equal_6Ux5U_1U_4_104();
void dut_N_Mux_8_2_0_4_105();
void dut_Equal_6Ux5U_1U_4_106();
void dut_N_Mux_8_2_0_4_107();
void dut_Equal_6Ux5U_1U_4_108();
void dut_N_Mux_8_2_0_4_109();
void dut_Equal_6Ux5U_1U_4_110();
void dut_N_Mux_8_2_0_4_111();
void dut_Equal_6Ux5U_1U_4_112();
void dut_N_Mux_8_2_0_4_113();
void dut_Equal_6Ux5U_1U_4_114();
void dut_N_Mux_8_2_0_4_115();
void dut_Equal_6Ux5U_1U_4_116();
void dut_N_Mux_8_2_0_4_117();
void dut_Equal_6Ux5U_1U_4_118();
void dut_N_Mux_8_2_0_4_119();
void dut_Equal_6Ux5U_1U_4_120();
void dut_N_Mux_8_2_0_4_121();
void dut_Equal_6Ux5U_1U_4_122();
void dut_N_Mux_8_2_0_4_123();
void dut_Equal_6Ux5U_1U_4_124();
void dut_N_Mux_8_2_0_4_125();
void dut_Equal_6Ux5U_1U_4_126();
void dut_N_Mux_8_2_0_4_127();
void dut_Equal_6Ux3U_1U_4_128();
void dut_N_Mux_8_2_0_4_129();
void dut_Equal_6Ux3U_1U_4_130();
void dut_N_Mux_8_2_0_4_131();
void dut_Equal_6Ux3U_1U_4_132();
void dut_N_Mux_8_2_0_4_133();
void dut_Equal_6Ux3U_1U_4_134();
void dut_N_Mux_8_2_0_4_135();
void dut_Equal_6Ux2U_1U_4_136();
void dut_N_Mux_8_2_0_4_137();
void dut_Equal_6Ux2U_1U_4_138();
void dut_N_Mux_8_2_0_4_139();
void dut_LessThan_8Sx8S_1U_4_140();
void dut_Equal_6Ux1U_1U_4_141();
void dut_N_Mux_8_2_0_4_142();
void dut_N_Mux_8_64_1_4_143();
void dut_N_Mux_8_64_2_4_144();
void dut_Add_8Ux8U_9U_4_145();
void drive_sreg_1();
void drive_global_state();
void drive_global_state_next();
void drive_gs_ctrl0();
void drive_din_busy();
void dut_Or_1Ux1U_1U_4_2();
void dut_And_1Ux1U_1U_4_3();
void dut_Not_1U_1U_4_4();
void dut_And_1Ux1U_1U_4_5();
void dut_Not_1U_1U_4_6();
void drive_din_m_unvalidated_req();
void dut_N_Muxb_1_2_3_4_1();
void drive_dout_vld();
void dut_Or_1Ux1U_1U_4_10();
void drive_dout_m_unacked_req();
void dut_And_1Ux1U_1U_4_11();
void dut_Xor_1Ux1U_1U_4_9();
void drive_dout_m_req_m_prev_trig_req();
void dut_Not_1U_1U_4_12();
void thread_1();
void thread_13();
};
#endif
|
#include "systemc.h"
#include "../cnm_base.h"
#include "../half.hpp"
using half_float::half;
SC_MODULE(fpu_driver) {
#if MIXED_SIM
sc_out<sc_logic> rst;
sc_out<sc_logic> mult_en; // Signals that a multiply computation step should be performed
sc_out<sc_logic> add_en; // Signals that an add computation step should be performed
sc_out<sc_lv<16> > srf_in; // Scalar operand from SRF
sc_out<sc_lv<16> > grfa_in1[SIMD_WIDTH]; // Input 1 from GRF_A
sc_out<sc_lv<16> > grfa_in2[SIMD_WIDTH]; // Input 2 from GRF_A
sc_out<sc_lv<16> > grfb_in1[SIMD_WIDTH]; // Input 1 from GRF_B
sc_out<sc_lv<16> > grfb_in2[SIMD_WIDTH]; // Input 2 from GRF_B
// sc_out<sc_lv<16> > even_out[SIMD_WIDTH]; // Input from EVEN_BANK
// sc_out<sc_lv<16> > odd_out[SIMD_WIDTH]; // Input from ODD_BANK
sc_out<sc_lv<8> > mult_in1_sel; // Selects input 1 for addition
sc_out<sc_lv<8> > mult_in2_sel; // Selects input 2 for multiplication
sc_out<sc_lv<8> > add_in1_sel; // Selects input 1 for addition
sc_out<sc_lv<8> > add_in2_sel; // Selects input 2 for multiplication
sc_out<sc_logic> out_sel; // Selects the output: 0 for adder output, 1 for multiplier output
#else
sc_out<bool> rst;
sc_out<bool> mult_en; // Signals that a multiply computation step should be performed
sc_out<bool> add_en; // Signals that an add computation step should be performed
sc_out<half> srf_in; // Scalar operand from SRF
sc_out<half> grfa_in1[SIMD_WIDTH]; // Input 1 from GRF_A
sc_out<half> grfa_in2[SIMD_WIDTH]; // Input 2 from GRF_A
sc_out<half> grfb_in1[SIMD_WIDTH]; // Input 1 from GRF_B
sc_out<half> grfb_in2[SIMD_WIDTH]; // Input 2 from GRF_B
// sc_out<half> even_out[SIMD_WIDTH]; // Input from EVEN_BANK
// sc_out<half> odd_out[SIMD_WIDTH]; // Input from ODD_BANK
sc_out<uint8_t> mult_in1_sel; // Selects input 1 for addition
sc_out<uint8_t> mult_in2_sel; // Selects input 2 for multiplication
sc_out<uint8_t> add_in1_sel; // Selects input 1 for addition
sc_out<uint8_t> add_in2_sel; // Selects input 2 for multiplication
sc_out<bool> out_sel; // Selects the output: 0 for adder output, 1 for multiplier output
#endif
SC_CTOR(fpu_driver) {
SC_THREAD(driver_thread);
}
void driver_thread();
};
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2017 Cadence Design Systems, Inc. All rights reserved worldwide.
//
// The code contained herein is the proprietary and confidential information
// of Cadence or its licensors, and is supplied subject to a previously
// executed license and maintenance agreement between Cadence and customer.
// This code is intended for use with Cadence high-level synthesis tools and
// may not be used with other high-level synthesis tools. Permission is only
// granted to distribute the code as indicated. Cadence grants permission for
// customer to distribute a copy of this code to any partner to aid in designing
// or verifying the customer's intellectual property, as long as such
// distribution includes a restriction of no additional distributions from the
// partner, unless the partner receives permission directly from Cadence.
//
// ALL CODE FURNISHED BY CADENCE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY
// KIND, AND CADENCE SPECIFICALLY DISCLAIMS ANY WARRANTY OF NONINFRINGEMENT,
// FITNESS FOR A PARTICULAR PURPOSE OR MERCHANTABILITY. CADENCE SHALL NOT BE
// LIABLE FOR ANY COSTS OF PROCUREMENT OF SUBSTITUTES, LOSS OF PROFITS,
// INTERRUPTION OF BUSINESS, OR FOR ANY OTHER SPECIAL, CONSEQUENTIAL OR
// INCIDENTAL DAMAGES, HOWEVER CAUSED, WHETHER FOR BREACH OF WARRANTY,
// CONTRACT, TORT, NEGLIGENCE, STRICT LIABILITY OR OTHERWISE.
//
////////////////////////////////////////////////////////////////////////////////
#ifndef DUT_H
#define DUT_H
#include <systemc.h> // SystemC definitions.
#include <esc.h> // ESC functions and utilities.
#include <stratus_hls.h> // Cadence Stratus definitions.
#include <cynw_p2p.h> // The cynw_p2p communication channel.
#include "defines.h" // The type definitions for the input and output.
SC_MODULE( dut )
{
sc_in< bool > clk;
sc_in< bool > rst;
cynw_p2p< input_t >::in din; // TB to DUT, using struct input_t.
cynw_p2p< output_t >::out dout; // DUT to TB, using type output_t.
SC_CTOR( dut )
: clk( "clk" )
, rst( "rst" )
, din( "din" )
, dout( "dout" )
{
SC_CTHREAD( thread1, clk.pos() );
reset_signal_is( rst, false );
din.clk_rst( clk, rst );
dout.clk_rst( clk, rst );
}
void thread1();
};
#endif // DUT_H
|
/**
* @file sc_clk.h
* @brief This file contains the SystemC module for the clock
* @ingroup systemc_modules
*/
#ifndef SC_CLK_H
#define SC_CLK_H
#include <systemc.h>
#include "sc_config.h"
//#include "sc_run.h"
SC_MODULE(scClk)
{
sc_out<bool> clk{"clk_o"};
SC_CTOR(scClk)
{
SC_THREAD(clockThread);
}
void clockThread ()
{
sc_time ustep = sc_getMicrostep();
int semiperiod_usteps = sc_getClkSemiperiodMicrosteps();
bool act_edge = sc_getClkActEdge();
while(1)
{
clk.write(act_edge);
for (int i = 0; i < semiperiod_usteps; i++)
{
wait(ustep);
}
clk.write(!act_edge);
for (int i = 0; i < semiperiod_usteps; i++)
{
wait(ustep);
}
}
}
};
#endif // SC_CLK_H
|
//
// Created by ludwig on 30.01.17.
//
#include <Interfaces.h>
#include "systemc.h"
enum trans_t {
SINGLE_READ, SINGLE_WRITE
};
enum ack_t {
OK, RTY, ERR
};
enum addr_t {
SLAVE0, SLAVE1, SLAVE2, SLAVE3
};
struct bus_req_t{
addr_t addr;
trans_t trans_type;
bool data;
};
struct bus_resp_t{
bool data;
ack_t ack;
};
#ifndef PROJECT_BUS_H
#define PROJECT_BUS_H
struct Bus : public sc_module {
//In-port
blocking_in<bus_req_t> master_in;
blocking_in<bus_resp_t> slave_in0;
blocking_in<bus_resp_t> slave_in1;
blocking_in<bus_resp_t> slave_in2;
blocking_in<bus_resp_t> slave_in3;
//Out-por
blocking_out<bus_resp_t> master_out;
blocking_out<bus_req_t> slave_out0;
blocking_out<bus_req_t> slave_out1;
blocking_out<bus_req_t> slave_out2;
blocking_out<bus_req_t> slave_out3;
//Variables
bus_req_t req;
bus_resp_t resp;
//Constructor
SC_HAS_PROCESS(Bus);
Bus(sc_module_name name) :
master_in("master_in"),
master_out("master_out"),
slave_out0("slave_out0"),
slave_out1("slave_out1"),
slave_out2("slave_out2"),
slave_out3("slave_out3"),
slave_in0("slave_in0"),
slave_in1("slave_in1"),
slave_in2("slave_in2"),
slave_in3("slave_in3") {
SC_THREAD(fsm);
}
void fsm() {
while (true) {
/*
0 - 7 HEAT
8 - 15 MIX
16 - 23 TEMP_TOP
24 - 31 TEMP_BOT
*/
master_in->read(req);
if(SINGLE_READ == req.trans_type){
req.data = false;
}
if (req.addr == SLAVE0) {
slave_out0->write(req);
slave_in0->read(resp);
}
else if (req.addr == SLAVE1) {
slave_out1->write(req);
slave_in1->read(resp);
}
else if (req.addr == SLAVE2) {
slave_out2->write(req);
slave_in2->read(resp);
}
else if (req.addr == SLAVE3) {
slave_out3->write(req);
slave_in3->read(resp);
}
else {
resp.ack = OK;
resp.data = false;
}
if(SINGLE_WRITE== req.trans_type){
resp.data = false;
}
master_out->write(resp);
wait(SC_ZERO_TIME);
}
}
};
#endif //PROJECT_BUS_H
|
/**********************************************************************
Filename: E_fir_pe.h
Purpose : Emulated PE of Systolic FIR filter
Author : [email protected]
History : Mar. 2024, First release
***********************************************************************/
#ifndef _E_FIR_PE_H_
#define _E_FIR_PE_H_
#include <systemc.h>
// Includes for accessing Arduino via serial port
#include <stdio.h>
#include <string.h>
#include <unistd.h>
#include <fcntl.h>
#include <termios.h>
SC_MODULE(E_fir_pe)
{
sc_in<bool> clk;
sc_in<sc_uint<8> > Cin;
sc_in<sc_uint<8> > Xin;
sc_out<sc_uint<8> > Xout;
sc_in<sc_uint<16> > Yin;
sc_out<sc_uint<16> > Yout;
#define N_TX 4
#define N_RX 3
void pe_thread(void)
{
uint8_t x, y, txPacket[N_TX], rxPacket[N_RX];
while(true)
{
wait(clk.posedge_event());
txPacket[3] = (uint8_t)(Yin.read()); // LSB of Yin
txPacket[2] = (uint8_t)(Yin.read()>>8); // MSB of Yin
txPacket[1] = (uint8_t)Xin.read(); // Xin
txPacket[0] = (uint8_t)Cin.read(); // Cin
// Send to Emulator
for (int i=0; i<N_TX; i++)
{
x = txPacket[i];
while(write(fd, &x, 1)<=0) usleep(1);
}
// Receive from Emulator
for (int i=0; i<N_RX; i++)
{
while(read(fd, &y, 1)<=0) usleep(1);
rxPacket[i] = y;
}
Xout.write( (uint8_t)rxPacket[0]);
Yout.write((uint16_t)rxPacket[1]<<8 | (uint16_t)rxPacket[2]);
}
}
// Arduino Serial IF
int fd; // Serial port file descriptor
struct termios options; // Serial port setting
SC_CTOR(E_fir_pe):
clk("clk"),
Cin("Cin"), Xin("Xin"), Xout("Xout"),
Yin("Yin"), Yout("Yout")
{
SC_THREAD(pe_thread);
sensitive << clk;
// Arduino DUT
//fd = open("/dev/ttyACM0", O_RDWR | O_NDELAY | O_NOCTTY);
fd = open("/dev/ttyACM0", O_RDWR | O_NOCTTY);
if (fd < 0)
{
perror("Error opening serial port");
return;
}
// Set up serial port
options.c_cflag = B115200 | CS8 | CLOCAL | CREAD;
options.c_iflag = IGNPAR;
options.c_oflag = 0;
options.c_lflag = 0;
// Apply the settings
tcflush(fd, TCIFLUSH);
tcsetattr(fd, TCSANOW, &options);
// Establish Contact
int len = 0;
char rx;
while(!len)
len = read(fd, &rx, 1);
if (rx=='A')
write(fd, &rx, 1);
printf("Connection established...\n");
}
~E_fir_pe(void)
{
}
};
#endif
|
/**
* @file sc_config.h
* @brief This file contains the SystemC configuration
* @ingroup systemc_modules
*/
#ifndef SC_CONFIG_H
#define SC_CONFIG_H
#include <systemc.h>
typedef struct sc_thread_config_s
{
bool rst_act_level;
int rst_act_microsteps;
bool ena_act_level;
bool clk_act_edge;
sc_time clk_period;
sc_time microstep;
int clk_semiperiod_microsteps;
}sc_thread_config_t;
void sc_setConfig(sc_thread_config_t *theConfig);
bool sc_getRstActLevel(void);
int sc_getRstActMicrosteps(void);
bool sc_getEnaActLevel(void);
bool sc_getClkActEdge(void);
sc_time sc_getClkPeriod(void);
sc_time sc_getMicrostep(void);
int sc_getClkSemiperiodMicrosteps(void);
#endif // SC_CONFIG_H
|
//-----------------------------------------------------
#include <systemc.h>
/**
* @brief Enum that represents the main FPU operations
*
*/
typedef enum {
SC_FPU_ADD = 1,
SC_FPU_SUB = 2,
SC_FPU_MULT = 3,
SC_FPU_DIV = 4
} sc_fpu_op_t;
/**
* @brief Class the represent and FPU using PV model
*
*/
SC_MODULE (fpu_unit) {
protected:
//----------------------------Internal variables----------------------------
// Operation type
sc_fpu_op_t op_type;
// Events to trigger the operation execution
sc_event event_op;
//-----------------------------Internal methods-----------------------------
/**
* @brief Performs the operation between the operands
*
*/
void exec_op()
{
while (true)
{
wait(event_op);
// Perform the operations
switch (this->op_type)
{
case SC_FPU_ADD:
this->op_c.write(this->op_a.read() + this->op_b.read());
break;
case SC_FPU_SUB:
this->op_c.write(this->op_a.read() - this->op_b.read());
break;
case SC_FPU_MULT:
this->op_c.write(this->op_a.read() * this->op_b.read());
break;
case SC_FPU_DIV:
this->op_c.write(this->op_a.read() / this->op_b.read());
break;
default:
break;
}
}
}
public:
// First operand
sc_in<float> op_a;
// Second operand
sc_in<float> op_b;
// Result
sc_out<float> op_c;
SC_HAS_PROCESS(fpu_unit);
/**
* @brief Construct a new fpu unit object
*
* @param name - name of the module
*/
fpu_unit(sc_module_name name) : sc_module(name)
{
SC_THREAD(exec_op);
} // End of Constructor
//------------------------------Public methods------------------------------
/**
* @brief Adds two float numbers
*
*/
void add()
{
this->op_type = SC_FPU_ADD;
this->event_op.notify(1, SC_NS);
}
/**
* @brief Divides two float numbers
*/
void div()
{
this->op_type = SC_FPU_DIV;
this->event_op.notify(3, SC_NS);
}
/**
* @brief Multiplies two float numbers
*
*/
void mult() {
this->op_type = SC_FPU_MULT;
this->event_op.notify(3, SC_NS);
}
/**
* @brief Subtracts two float numbers
*
*/
void subs()
{
this->op_type = SC_FPU_SUB;
this->event_op.notify(1, SC_NS);
}
};
|
#ifndef ACC_H
#define ACC_H
#include <systemc.h>
// #define __SYNTHESIS__
#define SYSC_ACC_DEBUG
//#define SYSC_ACC_DEBUG2
#ifndef __SYNTHESIS__
#define DWAIT(x) wait(x)
#else
#define DWAIT(x)
#endif
#define ACCNAME VM_INT8_V1_0
#define ACC_DTYPE sc_int
#define ACC_C_DTYPE int
#define MAX 2147483647
#define MIN -2147483648
#define POS 1073741824
#define NEG -1073741823
#define DIVMAX 2147483648
#define MAX8 127
#define MIN8 -128
typedef struct _DATA{
ACC_DTYPE<32> data;
bool tlast;
inline friend ostream& operator << (ostream& os, const _DATA &v){
cout << "data: " << v.data << " tlast: " << v.tlast;
return os;
}
} DATA;
typedef struct _HDATA{
bool rhs_take;
bool lhs_take;
sc_uint<8> rhs_count;
sc_uint<8> lhs_count;
sc_uint<16> dst_addr;
} HDATA;
typedef struct _ADATA{
ACC_DTYPE<32> d2;
ACC_DTYPE<32> d3;
ACC_DTYPE<32> d4;
ACC_DTYPE<32> d5;
ACC_DTYPE<32> d6;
ACC_DTYPE<32> d7;
ACC_DTYPE<32> d8;
ACC_DTYPE<32> d9;
ACC_DTYPE<32> d10;
ACC_DTYPE<32> d11;
ACC_DTYPE<32> d12;
ACC_DTYPE<32> d13;
ACC_DTYPE<32> d14;
ACC_DTYPE<32> d15;
ACC_DTYPE<32> d16;
ACC_DTYPE<32> d17;
inline friend ostream& operator << (ostream& os, const _ADATA &v){
return os;
}
} ADATA;
SC_MODULE(ACCNAME) {
//debug vars
bool print_po = false;
bool print_wo = false;
int simplecounter=0;
// int rows=0;
ACC_DTYPE<14> depth;
sc_in<bool> clock;
sc_in <bool> reset;
sc_fifo_in<DATA> din1;
sc_fifo_in<DATA> din2;
sc_fifo_in<DATA> din3;
sc_fifo_in<DATA> din4;
sc_fifo_out<DATA> dout1;
sc_fifo_out<DATA> dout2;
sc_fifo_out<DATA> dout3;
sc_fifo_out<DATA> dout4;
sc_signal<bool> read_inputs;
sc_signal<bool> rtake;
sc_signal<bool> ltake;
sc_signal<int> llen;
sc_signal<int> rlen;
sc_signal<int> lhs_block_max;
sc_signal<int> rhs_block_max;
#ifndef __SYNTHESIS__
sc_signal<bool,SC_MANY_WRITERS> d_in1;
sc_signal<bool,SC_MANY_WRITERS> d_in2;
sc_signal<bool,SC_MANY_WRITERS> d_in3;
sc_signal<bool,SC_MANY_WRITERS> d_in4;
sc_signal<bool,SC_MANY_WRITERS> schedule;
sc_signal<bool,SC_MANY_WRITERS> out_check;
sc_signal<bool,SC_MANY_WRITERS> gemm_unit_1_ready;
sc_signal<bool,SC_MANY_WRITERS> gemm_unit_2_ready;
sc_signal<bool,SC_MANY_WRITERS> gemm_unit_3_ready;
sc_signal<bool,SC_MANY_WRITERS> gemm_unit_4_ready;
sc_signal<bool,SC_MANY_WRITERS> write1;
sc_signal<bool,SC_MANY_WRITERS> write2;
sc_signal<bool,SC_MANY_WRITERS> write3;
sc_signal<bool,SC_MANY_WRITERS> write4;
sc_signal<bool,SC_MANY_WRITERS> arrange1;
sc_signal<bool,SC_MANY_WRITERS> arrange2;
sc_signal<bool,SC_MANY_WRITERS> arrange3;
sc_signal<bool,SC_MANY_WRITERS> arrange4;
sc_signal<bool,SC_MANY_WRITERS> write1_1;
sc_signal<bool,SC_MANY_WRITERS> write1_2;
sc_signal<bool,SC_MANY_WRITERS> write1_3;
sc_signal<bool,SC_MANY_WRITERS> write1_4;
sc_signal<bool,SC_MANY_WRITERS> write2_1;
sc_signal<bool,SC_MANY_WRITERS> write2_2;
sc_signal<bool,SC_MANY_WRITERS> write2_3;
sc_signal<bool,SC_MANY_WRITERS> write2_4;
sc_signal<bool,SC_MANY_WRITERS> write3_1;
sc_signal<bool,SC_MANY_WRITERS> write3_2;
sc_signal<bool,SC_MANY_WRITERS> write3_3;
sc_signal<bool,SC_MANY_WRITERS> write3_4;
sc_signal<bool,SC_MANY_WRITERS> write4_1;
sc_signal<bool,SC_MANY_WRITERS> write4_2;
sc_signal<bool,SC_MANY_WRITERS> write4_3;
sc_signal<bool,SC_MANY_WRITERS> write4_4;
#else
sc_signal<bool> d_in1;
sc_signal<bool> d_in2;
sc_signal<bool> d_in3;
sc_signal<bool> d_in4;
sc_signal<bool> schedule;
sc_signal<bool> out_check;
sc_signal<bool> gemm_unit_1_ready;
sc_signal<bool> gemm_unit_2_ready;
sc_signal<bool> gemm_unit_3_ready;
sc_signal<bool> gemm_unit_4_ready;
sc_signal<bool> write1;
sc_signal<bool> write2;
sc_signal<bool> write3;
sc_signal<bool> write4;
sc_signal<bool> arrange1;
sc_signal<bool> arrange2;
sc_signal<bool> arrange3;
sc_signal<bool> arrange4;
sc_signal<bool> write1_1;
sc_signal<bool> write1_2;
sc_signal<bool> write1_3;
sc_signal<bool> write1_4;
sc_signal<bool> write2_1;
sc_signal<bool> write2_2;
sc_signal<bool> write2_3;
sc_signal<bool> write2_4;
sc_signal<bool> write3_1;
sc_signal<bool> write3_2;
sc_signal<bool> write3_3;
sc_signal<bool> write3_4;
sc_signal<bool> write4_1;
sc_signal<bool> write4_2;
sc_signal<bool> write4_3;
sc_signal<bool> write4_4;
#endif
sc_signal<int> gemm_unit_1_l_pointer;
sc_signal<int> gemm_unit_2_l_pointer;
sc_signal<int> gemm_unit_3_l_pointer;
sc_signal<int> gemm_unit_4_l_pointer;
sc_signal<bool> gemm_unit_1_iwuse;
sc_signal<bool> gemm_unit_2_iwuse;
sc_signal<bool> gemm_unit_3_iwuse;
sc_signal<bool> gemm_unit_4_iwuse;
ADATA g1;
ADATA g2;
ADATA g3;
ADATA g4;
ADATA r1;
ADATA r2;
ADATA r3;
ADATA r4;
//GEMM 1 Inputs
ACC_DTYPE<32> lhsdata1a[2048];
ACC_DTYPE<32> lhsdata2a[2048];
ACC_DTYPE<32> lhsdata3a[2048];
ACC_DTYPE<32> lhsdata4a[2048];
//GEMM 2 Inputs
ACC_DTYPE<32> lhsdata1b[2048];
ACC_DTYPE<32> lhsdata2b[2048];
ACC_DTYPE<32> lhsdata3b[2048];
ACC_DTYPE<32> lhsdata4b[2048];
//GEMM 3 Inputs
ACC_DTYPE<32> lhsdata1c[2048];
ACC_DTYPE<32> lhsdata2c[2048];
ACC_DTYPE<32> lhsdata3c[2048];
ACC_DTYPE<32> lhsdata4c[2048];
//GEMM 4 Inputs
ACC_DTYPE<32> lhsdata1d[2048];
ACC_DTYPE<32> lhsdata2d[2048];
ACC_DTYPE<32> lhsdata3d[2048];
ACC_DTYPE<32> lhsdata4d[2048];
// //GEMM 1 Inputs
// ACC_DTYPE<32> lhsdata1a[4096];
// ACC_DTYPE<32> lhsdata2a[4096];
// ACC_DTYPE<32> lhsdata3a[4096];
// ACC_DTYPE<32> lhsdata4a[4096];
//
// //GEMM 2 Inputs
// ACC_DTYPE<32> lhsdata1b[4096];
// ACC_DTYPE<32> lhsdata2b[4096];
// ACC_DTYPE<32> lhsdata3b[4096];
// ACC_DTYPE<32> lhsdata4b[4096];
//
// //GEMM 3 Inputs
// ACC_DTYPE<32> lhsdata1c[4096];
// ACC_DTYPE<32> lhsdata2c[4096];
// ACC_DTYPE<32> lhsdata3c[4096];
// ACC_DTYPE<32> lhsdata4c[4096];
//
// //GEMM 4 Inputs
// ACC_DTYPE<32> lhsdata1d[4096];
// ACC_DTYPE<32> lhsdata2d[4096];
// ACC_DTYPE<32> lhsdata3d[4096];
// ACC_DTYPE<32> lhsdata4d[4096];
//Global Weights
ACC_DTYPE<32> rhsdata1[8192];
ACC_DTYPE<32> rhsdata2[8192];
ACC_DTYPE<32> rhsdata3[8192];
ACC_DTYPE<32> rhsdata4[8192];
//First Set (A)
ACC_DTYPE<32> rhs1a_1[2048];
ACC_DTYPE<32> rhs1b_1[2048];
ACC_DTYPE<32> rhs1c_1[2048];
ACC_DTYPE<32> rhs1d_1[2048];
ACC_DTYPE<32> rhs2a_1[2048];
ACC_DTYPE<32> rhs2b_1[2048];
ACC_DTYPE<32> rhs2c_1[2048];
ACC_DTYPE<32> rhs2d_1[2048];
ACC_DTYPE<32> rhs3a_1[2048];
ACC_DTYPE<32> rhs3b_1[2048];
ACC_DTYPE<32> rhs3c_1[2048];
ACC_DTYPE<32> rhs3d_1[2048];
ACC_DTYPE<32> rhs4a_1[2048];
ACC_DTYPE<32> rhs4b_1[2048];
ACC_DTYPE<32> rhs4c_1[2048];
ACC_DTYPE<32> rhs4d_1[2048];
// //First Set (A)
// ACC_DTYPE<32> rhs1a_1[1024];
// ACC_DTYPE<32> rhs1b_1[1024];
// ACC_DTYPE<32> rhs1c_1[1024];
// ACC_DTYPE<32> rhs1d_1[1024];
//
// ACC_DTYPE<32> rhs2a_1[1024];
// ACC_DTYPE<32> rhs2b_1[1024];
// ACC_DTYPE<32> rhs2c_1[1024];
// ACC_DTYPE<32> rhs2d_1[1024];
//
// ACC_DTYPE<32> rhs3a_1[1024];
// ACC_DTYPE<32> rhs3b_1[1024];
// ACC_DTYPE<32> rhs3c_1[1024];
// ACC_DTYPE<32> rhs3d_1[1024];
//
// ACC_DTYPE<32> rhs4a_1[1024];
// ACC_DTYPE<32> rhs4b_1[1024];
// ACC_DTYPE<32> rhs4c_1[1024];
// ACC_DTYPE<32> rhs4d_1[1024];
//new sums bram
ACC_DTYPE<32> lhs_sum1[512];
ACC_DTYPE<32> lhs_sum2[512];
ACC_DTYPE<32> lhs_sum3[512];
ACC_DTYPE<32> lhs_sum4[512];
ACC_DTYPE<32> rhs_sum1[512];
ACC_DTYPE<32> rhs_sum2[512];
ACC_DTYPE<32> rhs_sum3[512];
ACC_DTYPE<32> rhs_sum4[512];
//crf & crx
ACC_DTYPE<32> crf1[512];
ACC_DTYPE<32> crf2[512];
ACC_DTYPE<32> crf3[512];
ACC_DTYPE<32> crf4[512];
ACC_DTYPE<32> crx[512];
int ra=0;
sc_fifo<int> WRQ1;
sc_fifo<int> WRQ2;
sc_fifo<int> WRQ3;
sc_fifo<int> WRQ4;
sc_signal<int> w1S;
sc_signal<int> w2S;
sc_signal<int> w3S;
sc_signal<int> w4S;
#ifndef __SYNTHESIS__
int weight_max_index=0;
int input_max_index=0;
int local_weight_max_index=0;
int g1_macs=0;
int g2_macs=0;
int g3_macs=0;
int g4_macs=0;
int g1_out_count=0;
int g2_out_count=0;
int g3_out_count=0;
int g4_out_count=0;
#endif
sc_out<int> inS;
sc_out<int> read_cycle_count;
sc_out<int> process_cycle_count;
sc_out<int> gemm_1_idle;
sc_out<int> gemm_2_idle;
sc_out<int> gemm_3_idle;
sc_out<int> gemm_4_idle;
sc_out<int> gemm_1_write;
sc_out<int> gemm_2_write;
sc_out<int> gemm_3_write;
sc_out<int> gemm_4_write;
sc_out<int> gemm_1;
sc_out<int> gemm_2;
sc_out<int> gemm_3;
sc_out<int> gemm_4;
sc_out<int> wstall_1;
sc_out<int> wstall_2;
sc_out<int> wstall_3;
sc_out<int> wstall_4;
sc_out<int> rmax;
sc_out<int> lmax;
sc_out<int> outS;
sc_out<int> w1SS;
sc_out<int> w2SS;
sc_out<int> w3SS;
sc_out<int> w4SS;
sc_out<int> schS;
sc_out<int> p1S;
void Input_Handler();
void Output_Handler();
void Worker1();
void Worker2();
void Worker3();
void Worker4();
void Data_In1();
void Data_In2();
void Data_In3();
void Data_In4();
void Tracker();
void Scheduler();
void Post1();
void Post2();
void Post3();
void Post4();
void Arranger1();
void Arranger2();
void Arranger3();
void Arranger4();
void WSync1();
void WSync2();
void WSync3();
void WSync4();
void load_weights(int,int);
void schedule_gemm_unit(int, int, int, int);
int SHR(int,int);
void overwrite_weights_check();
void Read_Cycle_Counter();
void Process_Cycle_Counter();
void Writer_Cycle_Counter();
SC_HAS_PROCESS(ACCNAME);
// Parameters for the DUT
ACCNAME(sc_module_name name_) :sc_module(name_),WRQ1(512), WRQ2(512), WRQ3(512), WRQ4(512){
SC_CTHREAD(Input_Handler,clock.pos());
reset_signal_is(reset,true);
SC_CTHREAD(Worker1,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Worker2,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Worker3,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Worker4,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Output_Handler,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Data_In1,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Data_In2,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Data_In3,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Data_In4,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Scheduler,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Post1,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Post2,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Post3,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Post4,clock);
reset_signal_is(reset,true);
SC_CTHREAD(WSync1,clock);
reset_signal_is(reset,true);
SC_CTHREAD(WSync2,clock);
reset_signal_is(reset,true);
SC_CTHREAD(WSync3,clock);
reset_signal_is(reset,true);
SC_CTHREAD(WSync4,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Arranger1,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Arranger2,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Arranger3,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Arranger4,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Read_Cycle_Counter,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Process_Cycle_Counter,clock);
reset_signal_is(reset,true);
SC_CTHREAD(Writer_Cycle_Counter,clock);
reset_signal_is(reset,true);
#pragma HLS RESOURCE variable=din1 core=AXI4Stream metadata="-bus_bundle S_AXIS_DATA1" port_map={{din1_0 TDATA} {din1_1 TLAST}}
#pragma HLS RESOURCE variable=din2 core=AXI4Stream metadata="-bus_bundle S_AXIS_DATA2" port_map={{din2_0 TDATA} {din2_1 TLAST}}
#pragma HLS RESOURCE variable=din3 core=AXI4Stream metadata="-bus_bundle S_AXIS_DATA3" port_map={{din3_0 TDATA} {din3_1 TLAST}}
#pragma HLS RESOURCE variable=din4 core=AXI4Stream metadata="-bus_bundle S_AXIS_DATA4" port_map={{din4_0 TDATA} {din4_1 TLAST}}
#pragma HLS RESOURCE variable=dout1 core=AXI4Stream metadata="-bus_bundle M_AXIS_DATA1" port_map={{dout1_0 TDATA} {dout1_1 TLAST}}
#pragma HLS RESOURCE variable=dout2 core=AXI4Stream metadata="-bus_bundle M_AXIS_DATA2" port_map={{dout2_0 TDATA} {dout2_1 TLAST}}
#pragma HLS RESOURCE variable=dout3 core=AXI4Stream metadata="-bus_bundle M_AXIS_DATA3" port_map={{dout3_0 TDATA} {dout3_1 TLAST}}
#pragma HLS RESOURCE variable=dout4 core=AXI4Stream metadata="-bus_bundle M_AXIS_DATA4" port_map={{dout4_0 TDATA} {dout4_1 TLAST}}
#pragma HLS RESET variable=reset
}
};
#endif /* ACC_H */
|
// TODO Generalise this code so it is easy for all new accelerators
#ifndef SYSTEMC_INTEGRATE
#define SYSTEMC_INTEGRATE
#include <systemc.h>
#include "../ap_sysc/hls_bus_if.h"
// #include "tb_driver.h"
int sc_main(int argc, char* argv[]) { return 0; }
void sysC_init() {
sc_report_handler::set_actions("/IEEE_Std_1666/deprecated", SC_DO_NOTHING);
sc_report_handler::set_actions(SC_ID_LOGIC_X_TO_BOOL_, SC_LOG);
sc_report_handler::set_actions(SC_ID_VECTOR_CONTAINS_LOGIC_VALUE_, SC_LOG);
}
// struct systemC_sigs {
// sc_clock clk_fast;
// sc_signal<bool> sig_reset;
// hls_bus_chn<unsigned long long> insn_mem;
// hls_bus_chn<unsigned long long> inp_mem;
// hls_bus_chn<unsigned long long> wgt_mem;
// hls_bus_chn<unsigned int> out_mem;
// hls_bus_chn<unsigned long long> bias_mem;
// sc_signal<unsigned int> sig_start_acc;
// sc_signal<unsigned int> sig_done_acc;
// sc_signal<unsigned int> sig_reset_acc;
// sc_signal<unsigned int> sig_insn_count;
// sc_signal<unsigned int> sig_insn_addr;
// sc_signal<unsigned int> sig_input_addr;
// sc_signal<unsigned int> sig_weight_addr;
// sc_signal<unsigned int> sig_bias_addr;
// sc_signal<unsigned int> sig_output_addr;
// sc_signal<int> sig_depth;
// sc_signal<int> sig_crf;
// sc_signal<int> sig_crx;
// sc_signal<int> sig_ra;
// int id;
// systemC_sigs(int _id)
// : insn_mem("insn_port", 0, 81920),
// inp_mem("input_port", 0, 409600),
// wgt_mem("weight_port", 0, 409600),
// bias_mem("bias_port", 0, 409600),
// out_mem("out_port", 0, 409600) {
// sc_clock clk_fast("ClkFast", 1, SC_NS);
// id = _id;
// }
// };
// void systemC_binder(ACCNAME* acc, TB_Driver* tb_driver, int _insns_mem_size,
// int _uops_mem_size, int _data_mem_size, systemC_sigs* scs) {
// acc->clock(scs->clk_fast);
// acc->reset(scs->sig_reset);
// acc->start_acc(scs->sig_start_acc);
// acc->done_acc(scs->sig_done_acc);
// acc->reset_acc(scs->sig_reset_acc);
// acc->insn_count(scs->sig_insn_count);
// acc->insn_addr(scs->sig_insn_addr);
// acc->input_addr(scs->sig_input_addr);
// acc->weight_addr(scs->sig_weight_addr);
// acc->bias_addr(scs->sig_bias_addr);
// acc->output_addr(scs->sig_output_addr);
// acc->depth(scs->sig_depth);
// acc->crf(scs->sig_crf);
// acc->crx(scs->sig_crx);
// acc->ra(scs->sig_ra);
// acc->insn_port(scs->insn_mem);
// acc->input_port(scs->inp_mem);
// acc->weight_port(scs->wgt_mem);
// acc->bias_port(scs->bias_mem);
// acc->out_port(scs->out_mem);
// tb_driver->clock(scs->clk_fast);
// tb_driver->reset(scs->sig_reset);
// }
#endif // SYSTEMC_INTEGRATE
|
// Generated by stratus_hls 17.20-p100 (88533.190925)
// Thu Nov 19 00:46:16 2020
// from dut.cc
#ifndef CYNTH_PART_dut_dut_Div_64Ux2U_32U_4_h
#define CYNTH_PART_dut_dut_Div_64Ux2U_32U_4_h
#include "systemc.h"
/* Include declarations of instantiated parts. */
/* Declaration of the synthesized module. */
struct dut_Div_64Ux2U_32U_4 : public sc_module {
sc_in<sc_uint<64> > in2;
sc_in<sc_uint<2> > in1;
sc_out<sc_uint<32> > out1;
sc_in<bool > clk;
sc_in<sc_uint<1> > stall;
dut_Div_64Ux2U_32U_4( sc_module_name name );
SC_HAS_PROCESS(dut_Div_64Ux2U_32U_4);
sc_uint<32> out1_0;
void dut_Div_64Ux2U_32U_4_thread_1();
};
#endif
|
//////////////////////////////////////////////////////////////////////
//// ////
//// AES subbytes module header ////
//// ////
//// This file is part of the SystemC AES ////
//// ////
//// Description: ////
//// Subbytes stage header for AES algorithm ////
//// ////
//// To Do: ////
//// - done ////
//// ////
//// Author(s): ////
//// - Javier Castillo, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2005/01/26 16:51:05 jcastillo
// New examples for 0.2.5 version
//
// Revision 1.2 2004/08/30 14:44:44 jcastillo
// Code Formater used to give better appearance to SystemC code
//
// Revision 1.1.1.1 2004/07/05 09:46:22 jcastillo
// First import
//
#include "systemc.h"
SC_MODULE(subbytes)
{
sc_in<bool> clk;
sc_in<bool> reset;
sc_in<bool> start_i;
sc_in<bool> decrypt_i;
sc_in<sc_biguint <128> > data_i;
sc_out<bool> ready_o;
sc_out<sc_biguint<128> > data_o;
//To sbox
sc_out<sc_uint<8> > sbox_data_o;
sc_in<sc_uint<8> > sbox_data_i;
sc_out<bool>sbox_decrypt_o;
void sub();
void registers();
sc_signal<sc_uint<5> > state, next_state;
sc_signal<sc_biguint<128> > data_reg, next_data_reg;
sc_signal<bool> next_ready_o;
SC_CTOR(subbytes)
{
SC_METHOD(registers);
sensitive << clk.pos();
sensitive << reset.neg();
SC_METHOD(sub);
sensitive << decrypt_i << start_i << state << data_i << sbox_data_i << data_reg;
}
};
|
#ifndef __full_adder_h__
#define __full_adder_h__
#include <systemc.h>
//---------------------------------------
SC_MODULE(full_adder)
{
public: sc_in<bool> a, b, cin;
public: sc_out<bool> sum, cout;
//---------------------------------------
public: SC_CTOR(full_adder)
{
SC_METHOD(process);
sensitive << a << b << cin;
}
//---------------------------------------
private: void process()
{
bool aANDb, aXORb, cinANDaXORb;
aANDb = a.read() & b.read();
aXORb = a.read() ^ b.read();
cinANDaXORb = cin.read() & aXORb;
//Calculate sum and carry out of the 1-BIT adder
sum = aXORb ^ cin.read();
cout = aANDb | cinANDaXORb;
//next_trigger(1, SC_NS);
}
//---------------------------------------
};
//---------------------------------------
#endif
|
#ifndef LOCAL_TEST_UTILS_H
#define LOCAL_TEST_UTILS_H
// Needed for all tests
#include <Gemmini.h>
static Gemmini g("g");
static sc_signal<sc_biguint<7>> funct_write;
static sc_signal<sc_biguint<64>> rs1;
static sc_signal<sc_biguint<64>> rs2;
static sc_signal<sc_biguint<7>> opcode;
#define FUNCT_CONFIG 0
#define FUNCT_LOAD1 2
#define CONFIG_TYPE_MVIN 0b01
#define ACC_MVIN_ACCTYPE 0
#define ACC_MVIN_INPUTTYPE 1
#define CONFIG_MVIN1 0
#define CONFIG_MVIN2 1
#define CONFIG_MVIN3 2
#define OPCODE_CUSTOM3 0b1111011
#define ARRAY_DIM 16
enum test_status {SUCCESS, FAIL, UNFINISHED};
#include <systemc.h>
#include <include/gemmini_testutils.h>
#include <endian.h>
#endif |
/**********************************************************************
Filename: sc_fir8_tb.h
Purpose : Testbench of 8-Tab Systolic FIR filter
Author : [email protected]
History : Mar. 2024, First release
***********************************************************************/
#ifndef _SC_FIR8_TB_H_
#define _SC_FIR8_TB_H_
#include <systemc.h>
#include "sc_fir8.h"
SC_MODULE(sc_fir8_tb)
{
sc_clock clk;
sc_signal<sc_uint<4> > Xin;
sc_signal<sc_uint<4> > Xout;
sc_signal<sc_uint<4> > Yin;
sc_signal<sc_uint<4> > Yout;
sc_signal<bool> Vld;
sc_signal<bool> Rdy;
#ifdef EMULATED
sc_signal<sc_uint<4> > E_Xout;
sc_signal<sc_uint<4> > E_Yout;
sc_signal<bool> E_Vld;
#endif
sc_fir8* u_sc_fir8;
// Test utilities
void Test_Gen();
void Test_Mon();
sc_uint<8> x[F_SAMPLE]; // Time seq. input
sc_uint<16> y[F_SAMPLE]; // Filter output
#ifdef VCD_TRACE_FIR8_TB
sc_trace_file* fp; // VCD file
#endif
SC_CTOR(sc_fir8_tb):
clk("clk", 100, SC_NS, 0.5, 0.0, SC_NS, false),
Vld("Vld"),
Rdy("Rdy"),
Xin("Xin"),
Xout("Xout"),
Yin("Yin"),
Yout("Yout")
{
SC_THREAD(Test_Gen);
sensitive << clk;
SC_THREAD(Test_Mon);
sensitive << clk;
// Instaltiate FIR8
u_sc_fir8 = new sc_fir8("u_sc_fir8");
u_sc_fir8->clk(clk);
u_sc_fir8->Xin(Xin);
u_sc_fir8->Xout(Xout);
u_sc_fir8->Yin(Yin);
u_sc_fir8->Yout(Yout);
u_sc_fir8->Rdy(Rdy);
u_sc_fir8->Vld(Vld);
#ifdef EMULATED
u_sc_fir8->E_Xout(E_Xout);
u_sc_fir8->E_Yout(E_Yout);
u_sc_fir8->E_Vld(E_Vld);
#endif
#ifdef VCD_TRACE_FIR8_TB
// WAVE
fp = sc_create_vcd_trace_file("sc_fir8_tb");
fp->set_time_unit(100, SC_PS); // resolution (trace) ps
sc_trace(fp, clk, "clk");
sc_trace(fp, Xin, "Xin");
sc_trace(fp, Xout, "Xout");
sc_trace(fp, Yin, "Yin");
sc_trace(fp, Yout, "Yout");
sc_trace(fp, Rdy, "Rdy");
sc_trace(fp, Vld, "Vld");
#endif
}
~sc_fir8_tb(void)
{
}
};
#endif |
#ifndef ACCNAME_H
#define ACCNAME_H
#include <systemc.h>
#include "tensorflow/lite/delegates/utils/secda_tflite/sysc_integrator/sysc_types.h"
#ifndef __SYNTHESIS__
#define DWAIT(x) wait(x)
#else
#define DWAIT(x)
#endif
#define ACCNAME TOY_ADD
#define ACC_DTYPE sc_uint
#define ACC_C_DTYPE unsigned int
#define STOPPER -1
#define IN_BUF_LEN 4096
#define WE_BUF_LEN 8192
#define SUMS_BUF_LEN 1024
#define MAX 2147483647
#define MIN -2147483648
#define POS 1073741824
#define NEG -1073741823
#define DIVMAX 2147483648
#define MAX8 127
#define MIN8 -128
SC_MODULE(ACCNAME) {
sc_in<bool> clock;
sc_in<bool> reset;
sc_fifo_in<DATA> din1;
sc_fifo_out<DATA> dout1;
// GEMM 1 Inputs
ACC_DTYPE<32> A1[IN_BUF_LEN];
ACC_DTYPE<32> A2[IN_BUF_LEN];
ACC_DTYPE<32> B1[IN_BUF_LEN];
ACC_DTYPE<32> B2[IN_BUF_LEN];
ACC_DTYPE<32> C1[IN_BUF_LEN * 4];
ACC_DTYPE<32> C2[IN_BUF_LEN * 4];
int qm;
sc_int<8> shift;
#ifndef __SYNTHESIS__
sc_signal<int, SC_MANY_WRITERS> lenX;
sc_signal<int, SC_MANY_WRITERS> lenY;
sc_signal<bool, SC_MANY_WRITERS> computeX;
sc_signal<bool, SC_MANY_WRITERS> computeY;
sc_signal<bool, SC_MANY_WRITERS> readX;
sc_signal<bool, SC_MANY_WRITERS> readY;
sc_signal<bool, SC_MANY_WRITERS> writeX;
sc_signal<bool, SC_MANY_WRITERS> writeY;
#else
sc_signal<int> lenX;
sc_signal<int> lenY;
sc_signal<bool> computeX;
sc_signal<bool> computeY;
sc_signal<bool> readX;
sc_signal<bool> readY;
sc_signal<bool> writeX;
sc_signal<bool> writeY;
#endif
void Control();
void Data_Read();
void PE_Add();
void Data_Write();
int Quantised_Multiplier(int, int, sc_int<8>);
SC_HAS_PROCESS(ACCNAME);
ACCNAME(sc_module_name name_) : sc_module(name_) {
SC_CTHREAD(Control, clock);
reset_signal_is(reset, true);
SC_CTHREAD(Data_Read, clock);
reset_signal_is(reset, true);
SC_CTHREAD(PE_Add, clock);
reset_signal_is(reset, true);
SC_CTHREAD(Data_Write, clock);
reset_signal_is(reset, true);
#pragma HLS RESOURCE variable = din1 core = AXI4Stream metadata = \
"-bus_bundle S_AXIS_DATA1" port_map = { \
{din1_0 TDATA } { \
din1_1 TLAST } }
#pragma HLS RESOURCE variable = dout1 core = AXI4Stream metadata = \
"-bus_bundle M_AXIS_DATA1" port_map = { \
{dout1_0 TDATA } { \
dout1_1 TLAST } }
}
};
#endif |
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2017 Cadence Design Systems, Inc. All rights reserved worldwide.
//
// The code contained herein is the proprietary and confidential information
// of Cadence or its licensors, and is supplied subject to a previously
// executed license and maintenance agreement between Cadence and customer.
// This code is intended for use with Cadence high-level synthesis tools and
// may not be used with other high-level synthesis tools. Permission is only
// granted to distribute the code as indicated. Cadence grants permission for
// customer to distribute a copy of this code to any partner to aid in designing
// or verifying the customer's intellectual property, as long as such
// distribution includes a restriction of no additional distributions from the
// partner, unless the partner receives permission directly from Cadence.
//
// ALL CODE FURNISHED BY CADENCE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY
// KIND, AND CADENCE SPECIFICALLY DISCLAIMS ANY WARRANTY OF NONINFRINGEMENT,
// FITNESS FOR A PARTICULAR PURPOSE OR MERCHANTABILITY. CADENCE SHALL NOT BE
// LIABLE FOR ANY COSTS OF PROCUREMENT OF SUBSTITUTES, LOSS OF PROFITS,
// INTERRUPTION OF BUSINESS, OR FOR ANY OTHER SPECIAL, CONSEQUENTIAL OR
// INCIDENTAL DAMAGES, HOWEVER CAUSED, WHETHER FOR BREACH OF WARRANTY,
// CONTRACT, TORT, NEGLIGENCE, STRICT LIABILITY OR OTHERWISE.
//
////////////////////////////////////////////////////////////////////////////////
#ifndef DUT_H
#define DUT_H
#include <systemc.h> // SystemC definitions.
#include <esc.h> // ESC functions and utilities.
#include <stratus_hls.h> // Cadence Stratus definitions.
#include <cynw_p2p.h> // The cynw_p2p communication channel.
#include "defines.h" // The type definitions for the input and output.
SC_MODULE( dut )
{
sc_in< bool > clk;
sc_in< bool > rst;
cynw_p2p< input_t >::in din; // TB to DUT, using struct input_t.
cynw_p2p< output_t >::out dout; // DUT to TB, using type output_t.
SC_CTOR( dut )
: clk( "clk" )
, rst( "rst" )
, din( "din" )
, dout( "dout" )
{
SC_CTHREAD( thread1, clk.pos() );
reset_signal_is( rst, false );
din.clk_rst( clk, rst );
dout.clk_rst( clk, rst );
}
void thread1();
};
#endif // DUT_H
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2017 Cadence Design Systems, Inc. All rights reserved worldwide.
//
// The code contained herein is the proprietary and confidential information
// of Cadence or its licensors, and is supplied subject to a previously
// executed license and maintenance agreement between Cadence and customer.
// This code is intended for use with Cadence high-level synthesis tools and
// may not be used with other high-level synthesis tools. Permission is only
// granted to distribute the code as indicated. Cadence grants permission for
// customer to distribute a copy of this code to any partner to aid in designing
// or verifying the customer's intellectual property, as long as such
// distribution includes a restriction of no additional distributions from the
// partner, unless the partner receives permission directly from Cadence.
//
// ALL CODE FURNISHED BY CADENCE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY
// KIND, AND CADENCE SPECIFICALLY DISCLAIMS ANY WARRANTY OF NONINFRINGEMENT,
// FITNESS FOR A PARTICULAR PURPOSE OR MERCHANTABILITY. CADENCE SHALL NOT BE
// LIABLE FOR ANY COSTS OF PROCUREMENT OF SUBSTITUTES, LOSS OF PROFITS,
// INTERRUPTION OF BUSINESS, OR FOR ANY OTHER SPECIAL, CONSEQUENTIAL OR
// INCIDENTAL DAMAGES, HOWEVER CAUSED, WHETHER FOR BREACH OF WARRANTY,
// CONTRACT, TORT, NEGLIGENCE, STRICT LIABILITY OR OTHERWISE.
//
////////////////////////////////////////////////////////////////////////////////
#ifndef DUT_H
#define DUT_H
#include <systemc.h> // SystemC definitions.
#include <esc.h> // ESC functions and utilities.
#include <stratus_hls.h> // Cadence Stratus definitions.
#include <cynw_p2p.h> // The cynw_p2p communication channel.
#include "defines.h" // The type definitions for the input and output.
SC_MODULE( dut )
{
sc_in< bool > clk;
sc_in< bool > rst;
cynw_p2p< input_t >::in din; // TB to DUT, using struct input_t.
cynw_p2p< output_t >::out dout; // DUT to TB, using type output_t.
SC_CTOR( dut )
: clk( "clk" )
, rst( "rst" )
, din( "din" )
, dout( "dout" )
{
SC_CTHREAD( thread1, clk.pos() );
reset_signal_is( rst, false );
din.clk_rst( clk, rst );
dout.clk_rst( clk, rst );
}
void thread1();
};
#endif // DUT_H
|
/*
* @ASCK
*/
#include <systemc.h>
SC_MODULE (Mux3) {
sc_in <bool> sel;
sc_in <sc_uint<3>> in0;
sc_in <sc_uint<3>> in1;
sc_out <sc_uint<3>> out;
/*
** module global variables
*/
SC_CTOR (Mux3){
SC_METHOD (process);
sensitive << in0 << in1 << sel;
}
void process () {
if(!sel.read()){
out.write(in0.read());
}
else{
out.write(in1.read());
}
}
}; |
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2017 Cadence Design Systems, Inc. All rights reserved worldwide.
//
// The code contained herein is the proprietary and confidential information
// of Cadence or its licensors, and is supplied subject to a previously
// executed license and maintenance agreement between Cadence and customer.
// This code is intended for use with Cadence high-level synthesis tools and
// may not be used with other high-level synthesis tools. Permission is only
// granted to distribute the code as indicated. Cadence grants permission for
// customer to distribute a copy of this code to any partner to aid in designing
// or verifying the customer's intellectual property, as long as such
// distribution includes a restriction of no additional distributions from the
// partner, unless the partner receives permission directly from Cadence.
//
// ALL CODE FURNISHED BY CADENCE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY
// KIND, AND CADENCE SPECIFICALLY DISCLAIMS ANY WARRANTY OF NONINFRINGEMENT,
// FITNESS FOR A PARTICULAR PURPOSE OR MERCHANTABILITY. CADENCE SHALL NOT BE
// LIABLE FOR ANY COSTS OF PROCUREMENT OF SUBSTITUTES, LOSS OF PROFITS,
// INTERRUPTION OF BUSINESS, OR FOR ANY OTHER SPECIAL, CONSEQUENTIAL OR
// INCIDENTAL DAMAGES, HOWEVER CAUSED, WHETHER FOR BREACH OF WARRANTY,
// CONTRACT, TORT, NEGLIGENCE, STRICT LIABILITY OR OTHERWISE.
//
////////////////////////////////////////////////////////////////////////////////
#ifndef DUT_H
#define DUT_H
#include <systemc.h> // SystemC definitions.
#include <esc.h> // ESC functions and utilities.
#include <stratus_hls.h> // Cadence Stratus definitions.
#include <cynw_p2p.h> // The cynw_p2p communication channel.
#include "defines.h" // The type definitions for the input and output.
SC_MODULE( dut )
{
sc_in< bool > clk;
sc_in< bool > rst;
cynw_p2p< input_t >::in din; // TB to DUT, using struct input_t.
cynw_p2p< output_t >::out dout; // DUT to TB, using type output_t.
SC_CTOR( dut )
: clk( "clk" )
, rst( "rst" )
, din( "din" )
, dout( "dout" )
{
SC_CTHREAD( thread1, clk.pos() );
reset_signal_is( rst, false );
din.clk_rst( clk, rst );
dout.clk_rst( clk, rst );
}
void thread1();
};
#endif // DUT_H
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2017 Cadence Design Systems, Inc. All rights reserved worldwide.
//
// The code contained herein is the proprietary and confidential information
// of Cadence or its licensors, and is supplied subject to a previously
// executed license and maintenance agreement between Cadence and customer.
// This code is intended for use with Cadence high-level synthesis tools and
// may not be used with other high-level synthesis tools. Permission is only
// granted to distribute the code as indicated. Cadence grants permission for
// customer to distribute a copy of this code to any partner to aid in designing
// or verifying the customer's intellectual property, as long as such
// distribution includes a restriction of no additional distributions from the
// partner, unless the partner receives permission directly from Cadence.
//
// ALL CODE FURNISHED BY CADENCE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY
// KIND, AND CADENCE SPECIFICALLY DISCLAIMS ANY WARRANTY OF NONINFRINGEMENT,
// FITNESS FOR A PARTICULAR PURPOSE OR MERCHANTABILITY. CADENCE SHALL NOT BE
// LIABLE FOR ANY COSTS OF PROCUREMENT OF SUBSTITUTES, LOSS OF PROFITS,
// INTERRUPTION OF BUSINESS, OR FOR ANY OTHER SPECIAL, CONSEQUENTIAL OR
// INCIDENTAL DAMAGES, HOWEVER CAUSED, WHETHER FOR BREACH OF WARRANTY,
// CONTRACT, TORT, NEGLIGENCE, STRICT LIABILITY OR OTHERWISE.
//
////////////////////////////////////////////////////////////////////////////////
#ifndef DUT_H
#define DUT_H
#include <systemc.h> // SystemC definitions.
#include <esc.h> // ESC functions and utilities.
#include <stratus_hls.h> // Cadence Stratus definitions.
#include <cynw_p2p.h> // The cynw_p2p communication channel.
#include "defines.h" // The type definitions for the input and output.
SC_MODULE( dut )
{
sc_in< bool > clk;
sc_in< bool > rst;
cynw_p2p< input_t >::in din; // TB to DUT, using struct input_t.
cynw_p2p< output_t >::out dout; // DUT to TB, using type output_t.
SC_CTOR( dut )
: clk( "clk" )
, rst( "rst" )
, din( "din" )
, dout( "dout" )
{
SC_CTHREAD( thread1, clk.pos() );
reset_signal_is( rst, false );
din.clk_rst( clk, rst );
dout.clk_rst( clk, rst );
}
void thread1();
};
#endif // DUT_H
|
//
// Copyright 2022 Sergey Khabarov, [email protected]
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
#pragma once
#include <systemc.h>
#include "ambalib/types_amba.h"
#include "ambalib/types_pnp.h"
#include "ambalib/types_bus0.h"
#include "ambalib/types_bus1.h"
#include "riverlib/river_cfg.h"
#include "../prj/impl/asic/target_cfg.h"
#include "ambalib/axictrl_bus0.h"
#include "ambalib/axi2apb_bus1.h"
#include "misclib/axi_rom.h"
#include "misclib/axi_sram.h"
#include "misclib/clint.h"
#include "misclib/plic.h"
#include "misclib/apb_uart.h"
#include "misclib/apb_gpio.h"
#include "sdctrl/sdctrl.h"
#include "misclib/apb_pnp.h"
#include "riverlib/workgroup.h"
#include "techmap/cdc_axi_sync/cdc_axi_sync_tech.h"
#include "sv_func.h"
namespace debugger {
SC_MODULE(riscv_soc) {
public:
sc_in<bool> i_sys_nrst; // Power-on system reset active LOW
sc_in<bool> i_sys_clk; // System/Bus clock
sc_in<bool> i_dbg_nrst; // Reset from Debug interface (DMI). Reset everything except DMI
sc_in<bool> i_ddr_nrst; // DDR related logic reset (AXI clock transformator)
sc_in<bool> i_ddr_clk; // DDR memoru clock
// GPIO signals:
sc_in<sc_uint<12>> i_gpio;
sc_out<sc_uint<12>> o_gpio;
sc_out<sc_uint<12>> o_gpio_dir;
// JTAG signals:
sc_in<bool> i_jtag_trst;
sc_in<bool> i_jtag_tck;
sc_in<bool> i_jtag_tms;
sc_in<bool> i_jtag_tdi;
sc_out<bool> o_jtag_tdo;
sc_out<bool> o_jtag_vref;
// UART1 signals
sc_in<bool> i_uart1_rd;
sc_out<bool> o_uart1_td;
// SD-card signals:
sc_out<bool> o_sd_sclk; // Clock up to 50 MHz
sc_in<bool> i_sd_cmd; // Command response;
sc_out<bool> o_sd_cmd; // Command request; DO in SPI mode
sc_out<bool> o_sd_cmd_dir; // Direction bit: 1=input; 0=output
sc_in<bool> i_sd_dat0; // Data Line[0] input; DI in SPI mode
sc_out<bool> o_sd_dat0; // Data Line[0] output
sc_out<bool> o_sd_dat0_dir; // Direction bit: 1=input; 0=output
sc_in<bool> i_sd_dat1; // Data Line[1] input
sc_out<bool> o_sd_dat1; // Data Line[1] output
sc_out<bool> o_sd_dat1_dir; // Direction bit: 1=input; 0=output
sc_in<bool> i_sd_dat2; // Data Line[2] input
sc_out<bool> o_sd_dat2; // Data Line[2] output
sc_out<bool> o_sd_dat2_dir; // Direction bit: 1=input; 0=output
sc_in<bool> i_sd_cd_dat3; // Card Detect / Data Line[3] input
sc_out<bool> o_sd_cd_dat3; // Card Detect / Data Line[3] output; CS output in SPI mode
sc_out<bool> o_sd_cd_dat3_dir; // Direction bit: 1=input; 0=output
sc_in<bool> i_sd_detected; // SD-card detected
sc_in<bool> i_sd_protect; // SD-card write protect
// PLL and Reset interfaces:
sc_out<bool> o_dmreset; // Debug reset request. Everything except DMI.
sc_out<mapinfo_type> o_prci_pmapinfo; // PRCI mapping information
sc_in<dev_config_type> i_prci_pdevcfg; // PRCI device descriptor
sc_out<apb_in_type> o_prci_apbi; // APB: PLL and Reset configuration interface
sc_in<apb_out_type> i_prci_apbo; // APB: PLL and Reset configuration interface
// DDR interfaces:
sc_out<mapinfo_type> o_ddr_pmapinfo; // DDR configuration mapping information
sc_in<dev_config_type> i_ddr_pdevcfg; // DDR configuration device descriptor
sc_out<apb_in_type> o_ddr_apbi; // APB: DDR configuration interface
sc_in<apb_out_type> i_ddr_apbo; // APB: DDR configuration interface
sc_out<mapinfo_type> o_ddr_xmapinfo; // DDR memory bank mapping information
sc_in<dev_config_type> i_ddr_xdevcfg; // DDR memory bank descriptor
sc_out<axi4_slave_in_type> o_ddr_xslvi; // AXI DDR memory interface
sc_in<axi4_slave_out_type> i_ddr_xslvo; // AXI DDR memory interface
void comb();
SC_HAS_PROCESS(riscv_soc);
riscv_soc(sc_module_name name,
bool async_reset,
int sim_uart_speedup_rate);
virtual ~riscv_soc();
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
bool async_reset_;
int sim_uart_speedup_rate_;
// Hardware SoC Identificator.
// Read Only unique platform identificator that could be read by FW
static const uint32_t SOC_HW_ID = 0x20220903;
// UARTx fifo log2(size) in bytes:
static const int SOC_UART1_LOG2_FIFOSZ = 4;
// Number of available generic IO pins:
static const int SOC_GPIO0_WIDTH = 12;
// SD-card in SPI mode buffer size. It should be at least log2(512) Bytes:
static const int SOC_SPI0_LOG2_FIFOSZ = 9;
// Number of contexts in PLIC controller.
// Example FU740: S7 Core0 (M) + 4xU74 Cores (M+S).
static const int SOC_PLIC_CONTEXT_TOTAL = 9;
// Any number up to 1024. Zero interrupt must be 0.
static const int SOC_PLIC_IRQ_TOTAL = 73;
sc_signal<axi4_master_out_type> acpo;
sc_signal<axi4_master_in_type> acpi;
bus0_mapinfo_vector bus0_mapinfo;
bus0_xmst_in_vector aximi;
bus0_xmst_out_vector aximo;
bus0_xslv_in_vector axisi;
bus0_xslv_out_vector axiso;
bus1_mapinfo_vector bus1_mapinfo;
bus1_apb_in_vector apbi;
bus1_apb_out_vector apbo;
soc_pnp_vector dev_pnp;
sc_signal<sc_uint<64>> wb_clint_mtimer;
sc_signal<sc_uint<CFG_CPU_MAX>> wb_clint_msip;
sc_signal<sc_uint<CFG_CPU_MAX>> wb_clint_mtip;
sc_signal<sc_uint<SOC_PLIC_CONTEXT_TOTAL>> wb_plic_xeip;
sc_signal<sc_uint<CFG_CPU_MAX>> wb_plic_meip;
sc_signal<sc_uint<CFG_CPU_MAX>> wb_plic_seip;
sc_signal<bool> w_irq_uart1;
sc_signal<sc_uint<SOC_GPIO0_WIDTH>> wb_irq_gpio;
sc_signal<bool> w_irq_pnp;
sc_signal<sc_biguint<SOC_PLIC_IRQ_TOTAL>> wb_ext_irqs;
axictrl_bus0 *bus0;
axi2apb_bus1 *bus1;
axi_rom<CFG_BOOTROM_LOG2_SIZE> *rom0;
axi_sram<CFG_SRAM_LOG2_SIZE> *sram0;
clint<CFG_CPU_MAX> *clint0;
plic<SOC_PLIC_CONTEXT_TOTAL, SOC_PLIC_IRQ_TOTAL> *plic0;
apb_uart<SOC_UART1_LOG2_FIFOSZ> *uart1;
apb_gpio<SOC_GPIO0_WIDTH> *gpio0;
sdctrl *sdctrl0;
apb_pnp<SOC_PNP_TOTAL> *pnp0;
Workgroup *group0;
cdc_axi_sync_tech *u_cdc_ddr0;
};
} // namespace debugger
|
/*******************************************************************************
* btclient.h -- Copyright 2019 (c) Glenn Ramalho - RFIDo Design
*******************************************************************************
* Description:
* This is a model for a net client. It can behave as a web client or server,
* a NTP server or a MQTT Broker. This file does not implement all the
* details of these protocols, it simply provides a way for a testbench to
* generate stimulus to emulate these protocols.
*******************************************************************************
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************
*/
#ifndef _BTCLIENT_H
#define _BTCLIENT_H
#include <systemc.h>
#include "cchan.h"
SC_MODULE(btclient) {
sc_in<unsigned int> rx {"rx"};
sc_out<unsigned int> tx {"tx"};
cchan i_btchan{"i_btchan", 256, 256};
SC_CTOR(btclient) {
i_btchan.tx(tx);
i_btchan.rx(rx);
}
/* Channel send */
void send(void *msg, int len);
void send(const char *msg) { send((void *)msg, strlen(msg)); }
void send(std::string msg) { send((void *)msg.c_str(), msg.length()); }
std::string get();
void expect(const char *string);
};
#endif
|
/************************************************/
// Copyright tlm_noc contributors.
// Author Mike
// SPDX-License-Identifier: Apache-2.0
/************************************************/
#ifndef __L2CACHE_H__
#define __L2CACHE_H__
#include <systemc.h>
#include <tlm.h>
// Convenience Sockets:
#include <tlm_utils/peq_with_cb_and_phase.h>
#include <tlm_utils/simple_target_socket.h>
#include "tlm_noc.h"
#include "noc_payload.h"
using namespace tlm;
class l2cache: public sc_core::sc_module {
SC_HAS_PROCESS(l2cache);
public:
// TLM interface
tlm_utils::simple_target_socket<l2cache> s_port;
// Constructor
l2cache(sc_core::sc_module_name name);
private:
void peq_callback(gp &trans, const tlm_phase &phase);
tlm_sync_enum slv_nb_transport_fw(gp& payload, tlm_phase& phase, sc_time& delay);
tlm_utils::peq_with_cb_and_phase<l2cache> peq;
uint8_t l2sram[L2_SRAM_BYTE];
double pkt_counter;
};
#endif
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