Initial

.gitattributes

@@ -33,3 +33,4 @@ saved_model/**/* filter=lfs diff=lfs merge=lfs -text
 *.zip filter=lfs diff=lfs merge=lfs -text
 *.zst filter=lfs diff=lfs merge=lfs -text
 *tfevents* filter=lfs diff=lfs merge=lfs -text
+*.jsonl filter=lfs diff=lfs merge=lfs -text

LICENSE

@@ -0,0 +1,21 @@
+Copyright (c) Microsoft Corporation.
+
+MIT License
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED *AS IS*, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.

README.md

@@ -0,0 +1,318 @@
+---
+pretty_name: "VEGA"
+language: 
+  - code
+tags:
+  - C++/C Code
+  - Compiler Backend
+license: "cc-by-4.0"
+---
+
+# VEGA: Automatically Generating Compiler Backends Using a Pre-Trained Transformer Model
+
+VEGA is an AI-driven system aimed at easing the development burden of compiler backends for new targets.
+
+This repository contains code and data for reproducing experimental results. 
+
+For detailed description of each script, please refer to the Artifact  Appendix  of our paper.
+
+
+## 1. Directory Structure
+```
+VEGA_AE
+|──dataset
+|──saved_models
+|   |──Fine_Tuned_Model
+|   |──New_Fine_Tuned_Model
+|   └──UnixCoder
+|——Scripts
+|   |──Exp
+|   |   |──Accuracy
+|   |   |──Correction
+|   |   |──ForkFlow
+|   |   |──Performance
+|   |   └──Time
+|   └──UnixCoder
+└──Fixed_VEGA_LLVM
+    |──llvm-riscv
+    |──llvm-ri5cy
+    └──llvm-xcore
+```
+## 2. Hardware Dependency
+
+- Intel(R)Xeon(R)Gold 6132 CPU @ 2.60GHz
+- 8 Nvidia Tesla V100 GPU, each with 16 GB Memory
+
+## 3. Software Dependency
+- CUDA == 11.4
+- python version == 3.8.1
+- pip install -r requirements.txt
+
+
+## 4. Fine-Tuning
+
+Run fine-tuning with:
+```
+$ bash run_fine_tuning.sh
+```
+Customize parameters for fine-tuning by modifying following options in the ```run_fine_tuning.sh```.
+```
+  --model_name_or_path ../../saved_models/UnixCoder \
+  --train_filename ../../dataset/train.jsonl \
+  --dev_filename ../../dataset/valid.jsonl \
+  --output_dir ../../saved_models/New_Fine_Tuned_Model \
+  --beam_size 4 \
+  --train_batch_size 96 \
+  --eval_batch_size 80 \
+  --learning_rate 6e-5 \
+  --num_train_epochs 50 \
+  --mse_loss_weight 0.9 \
+  --ce_loss_weight 0.1
+```
+The fine-tuned model will be saved in ```--output_dir```.
+
+## 5. Code Generation
+
+We have provided a fine-tuned model in ```./saved_models/Fine_Tuned_Model```.
+
+We have also provided a script fot function test, which only generates a single function for RI5CY, taking less than 3 minutes with 8 V100 GPU.
+
+
+
+Run function test with:
+
+```
+$ bash run_function_test.sh
+```
+
+When the ```run_function_test.sh``` script begins execution, the command line displays
+```
+$ " Start Function Inferencing !"
+```
+Upon completion of the code generation, the script outputs
+```
+$ " Finished Function Inferencing : xxx secs"
+``` 
+
+The inference result will be saved in ```--output_dir/result.jsonl```.
+
+Run code generation with:
+
+```
+$ bash run_test.sh
+```
+
+Customize parameters for inferencing by modifying following options in the ```run_test.sh```.
+```
+ --model_name_or_path ../../saved_models/UnixCoder \
+ --test_filename ../../dataset/test.jsonl \
+ --output_dir ../../saved_models/Fine_Tuned_Model \
+ --beam_size 4 \
+ --train_batch_size 256 \
+ --eval_batch_size 256 \
+ --learning_rate 6e-5 \
+ --gradient_accumulation_steps 2 \
+ --num_train_epochs 10 \
+ --mse_loss_weight 0.9  \
+ --ce_loss_weight 0.1
+```
+Users can inference with their own fine-tuned model by changing the ```--output_dir``` option.
+
+
+
+When the ```run_test.sh``` script begins execution, the command line displays
+```
+$ " Start Inferencing !"
+```
+Upon completion of the code generation, the script outputs
+```
+$ " Finished Inferencing : xxx secs"
+``` 
+
+The inference result will be saved in ```--output_dir/result.jsonl```.
+
+The ```--output_dir``` parameter specifies the directory where the fine-tuned model is saved, such as ```./saved_models/Fine_Tuned_Model```.
+
+## 6. Reproducing Results in the Experiment
+
+We provide the scripts to reproduce each Figure/Table from the paper, along with the corresponding output result files, in the following table:
+
+
+| Script | Description | Output | Figure/Table |
+| ---------------------------------------------- | ----------------------------------------------------------------------------------------------------------------------------------------- | ------------------------------------------------------ | -------------- |
+| ./Scripts/Exp/Time/calculate_time.py 	| Calculate the time overhead.                                                                                                            	| ./Scripts/Exp/Time/time_overhead.csv                 	| Fig.7        	|
+| ./Scripts/Exp/Accuracy/calculate_accuracy.py 	| Calculate the function-level accuracy.                                                                                                  	| ./Scripts/Exp/Accuracy/vega_result.csv               	| Fig.8        	|
+| ./Scripts/Exp/Accuracy/calculate_purple.py 	| Calculate the the percentage of functions accurately synthesized from the statements of various existing targets (Purple Bar in Fig.8). 	| ./Scripts/Exp/Accuracy/fig8_purple.csv          	| Fig.8        	|
+| ./Scripts/Exp/Accuracy/calculate_accuracy.py 	| Calculate the percentage of three types of error.                                                                                       	| ./Scripts/Exp/Accuracy/err_percentage.csv            	| Table.2      	|
+| ./Scripts/Exp/ForkFlow/calculate_forkflow.py 	| Calculate the statement-level accracy of VEGA and ForkFlow.                                                                             	| ./Scripts/Exp/ForkFlow/forkflow_result.csv           	| Fig.9        	|
+| ./Scripts/Exp/ForkFlow/calculate_forkflow.py 	| Calculate the number of accurate statements of VEGA and ForkFlow.                                                                       	| ./Scripts/Exp/ForkFlow/mod_lines.csv 	                | Table.3      	|
+| -                                            	| Recorded time required by Developer A and B to modify the VEGA-generated RISC-V backend.                                                	| ./Scripts/Exp/Correction/Correction_Time.xlsx        	| Table. 4     	|
+| -                                            	| Recorded time required for LLVM-Base (-O0), LLVM-Base (-O3), and LLVM-VEGA (-O3) to pass benchmarks.                                    	| ./Scripts/Exp/Performance/BenchMark.xlsx             	| Fig. 10      	|
+### 6.1 Results for Fig. 7 in Sec. 4.2
+
+In the code generation process, we set a batch size of 256 on 8 Nvidia Tesla V100 GPU (each with 16GB memory), meaning each batch contains 256 statements. Since each batch may include statements from different function modules, we did not directly measure the generation time for each function modules of three targets (RISC-V, RI5CY, xCORE) during execution. Instead, we calculated the average inference time of each batch (25 seconds) and then derived the inference time of each statement (25/256 seconds). With the total number of statements within each function module of each target, we subsequently calculated the total inference time required for each function module of each target.
+
+
+- Command:
+```
+$ python ./Scripts/Exp/Time/calculate_time.py
+```
+
+
+- Results:
+```
+./Scripts/Exp/Time/time_overhead.csv
+```
+
+### 6.2 Results for Fig. 8 in Sec. 4.2
+
+
+In our experiment, we employed the Pass@1 evaluation metric, which involves replacing each VEGA-generated function individually within the official LLVM (LLVM-Base), then running regression tests to verify the correctness of the replaced function. This process is highly time-intensive, as a single regression test run generally takes about half an hour. Thus, sequentially testing all 1,454 VEGA-generated functions across three targets would require approximately 727 hours.
+
+To simplify this process, we recorded the ground truth for each statement based on the Pass@1 experiment results. Additionally, we documented a list of functions containing Err-Def errors (i.e., errors due to missing necessary statements in the function template; functions with Err-Def can not pass all regression tests). This allowed us to transform the Pass@1 testing process into an Exact Match evaluation. 
+
+In this Exact Match evaluation, each statement is deemed correct if the VEGA-generated code matches the ground truth and the confidence score aligns. A function is considered correct if all statements within it are accurate and it is free from Err-Def errors.
+
+- Command:
+```
+$ cp --output_dir/result.jsonl ./Scripts/Exp/Accuracy
+$ python ./Scripts/Exp/Accuracy/calculate_accuracy.py
+```
+
+This script will automatically analyze the VEGA's output from "result.jsonl" and compare the generated code and confidence scores with the ground truth. Based on this comparison, it will determine whether each function is correct.
+
+- Accuracy Results:
+```
+./Scripts/Exp/Accuracy/vega_result.csv
+```
+
+
+We also provide a script for calculating the proportion of "Accurate Functions with Integrated Statements Across Multiple Targets". The value corresponding to the purple bar in Fig. 8.
+
+
+- Command:
+```
+$ python ./Scripts/Exp/Accuracy/calculate_purple.py
+```
+
+
+- Results:
+```
+./Scripts/Exp/Accuracy/fig8_purple.csv
+```
+
+
+We also provided manually fixed VEGA-generated RISC-V, RI5CY and xCORE backend, which can be used to run regression tests and pass@1 experiments. **Note that the compilation of llvm-riscv and llvm-ri5cy requires gcc-9.5.0 version, and the compilation of llvm-xcore requires gcc-4.0.0 version.**
+
+```
+Download from Google Drive: https://drive.google.com/file/d/1VD3H60vMvtnRtMkS6h0qZWTKkjcUzLsw/view?usp=drive_link
+$ unzip Fixed_VEGA_LLVM.zip
+```
+
+- Command for Running RISC-V Backend:
+```
+$ cd ./Fixed_VEGA_LLVM
+$ bash run_llvm_riscv.sh
+```
+- Results for Regression Tests of the RISC-V Backend:
+```
+$ Testing Time: xxx s
+$    Passed   : 16005
+```
+
+- Command for Running RI5CY Backend:
+```
+$ cd ./Fixed_VEGA_LLVM
+$ bash run_llvm_ri5cy.sh
+```
+- Results for Regression Tests of the RI5CY Backend:
+```
+$ Testing Time: xxx s
+$    Passed   : 16040
+```
+
+- Command for Running xCORE Backend:
+```
+$ cd ./Fixed_VEGA_LLVM
+$ vim run_llvm_xcore.sh
+$ Set the prefix option to the path where you want to install LLVM.
+$ Set the CC and llvmgccdir option to the path of gcc-4.0.0 version, change the CXX option to the path of g++-4.0.0 version.
+$ bash run_llvm_xcore.sh
+```
+- Results for Regression Tests of the xCORE Backend:
+```
+$ Testing Time: xxx s
+$    Passed   : 5466
+```
+
+### 6.3 Results for Table. 2 in Sec. 4.2
+
+Executing the script in (2) will also yield the proportion of the three types of errors for each target.
+
+
+- Command:
+```
+$ python ./Scripts/Exp/Accuracy/calculate_accuracy.py
+```
+
+
+- Results:
+```
+./Scripts/Exp/Accuracy/err_percentage.csv
+```
+
+
+### 6.4 Results for Fig. 9 in Sec. 4.2
+
+We modified the functions generated by VEGA and functions in the MIPS backend (ForkFlow) to ensure they can correctly run on the RISC-V, RI5CY, and xCORE backends respectively. By executing the following script, the proportion of accurate and modified statements of the VEGA-generated functions and ForkFlow processes will be automatically calculated.
+
+- Command:
+```
+$ python ./Scripts/Exp/ForkFlow/calculate_forkflow.py
+```
+
+
+- Results:
+```
+./Scripts/Exp/ForkFlow/forkflow_result.csv
+```
+
+### 6.5 Results for Table. 3 in Sec. 4.2
+
+Executing the script in 6.4 will also output the number of statements accurately generated and requiring manual correction by VEGA across seven function modules for RISC-V, RI5CY, and xCORE.
+
+
+- Command:
+```
+$ python ./Scripts/Exp/ForkFlow/calculate_forkflow.py
+```
+
+
+- Results:
+```
+./Scripts/Exp/ForkFlow/mod_lines.csv
+```
+
+
+### 6.6 Results for Table. 4 in Sec. 4.2
+
+The data in Table. 4 record the time required by two developers to modify the VEGA-generated RISC-V backend. As this is a human-based experiment, we can only provide the recorded time for modifying each function within the VEGA-generated RISC-V backend.
+
+- Results:
+```
+./Scripts/Exp/Correction/Correction_Time.xlsx
+```
+
+This file contains two sheets, each corresponding to the time required by Developer A and Developer B to modify the VEGA-generated RISC-V backend. Each sheet includes four columns: the first three indicate the function module, file, and function name of each function in the VEGA-generated RISC-V backend, while the final column specifies the time spent modifying each function, measured in seconds. By summing the data in each sheet according to function modules, we calculated the total time (in hours) that Developer A and Developer B spent on each module.
+
+### 6.7 Results for Fig. 10 in Sec. 4.3
+
+Due to restrictions associated with the commercial license, we are unable to provide the source code of the SPEC 2017 CPU benchmark directly used in this experiment. Furthermore, the testing duration for SPEC 2017 CPU is highly time-consuming, requiring approximately 565 hours. To address these constraints, we provide our recorded experimental data, which can be accessed at:
+
+
+- Results:
+```
+./Scripts/Exp/Performance/BenchMark.xlsx
+```
+
+Each sheet in this recorded data is named with the experimental target and benchmark tested, e.g., "RISCV (SPEC 2017CPU)". We recorded the time required for LLVM-Base (-O0), LLVM-Base (-O3), and LLVM-VEGA (-O3) to successfully pass each test case, and  calculated the corresponding speedup ratios respectively.

Scripts/Exp/Accuracy/Accurate_Func_Merged.csv

@@ -0,0 +1,171 @@
+Allocation,RegisterInfo,getCalleeSavedRegs,PULP
+Allocation,RegisterInfo,getFrameRegister,PULP
+Assembler,AsmParser,isRV64,PULP
+Assembler,AsmParser,isRV64-2,PULP
+Assembler,AsmParser,isSImm6NonZero,PULP
+Assembler,AsmParser,isSImm9Lsb0,PULP
+Assembler,AsmParser,parseImmediate,PULP
+Assembler,AsmParser,validateTargetOperandClass,PULP
+Assembler,AsmPrinter,isSImm12Lsb0,PULP
+Disassembler,Disassembler,addImplySP,PULP
+Disassembler,Disassembler,DecodePulpV2RegisterClass,PULP
+Disassembler,Disassembler,DecodePulpV4RegisterClass,PULP
+Disassembler,Disassembler,decodeSImmNonZeroOperand,PULP
+Disassembler,Disassembler,decodeUImmNonZeroOperand,PULP
+Disassembler,Disassembler,DecodeVRRegisterClass,PULP
+Disassembler,Disassembler,LLVMInitializeDisassembler,PULP
+Emission,AsmBackend,applyFixup,PULP
+Emission,AsmBackend,fixupNeedsRelaxationAdvanced,PULP
+Emission,AsmBackend,getFixupKind,PULP
+Emission,AsmBackend,getRelaxedOpcode,PULP
+Emission,AsmBackend,mayNeedRelaxation,PULP
+Emission,AsmInfo,MCAsmInfo,PULP
+Emission,BaseInfo,ABI,PULP
+Emission,BaseInfo,getTargetABI,PULP
+Emission,BaseInfo,stringToRoundingMode,PULP
+Emission,BaseInfo,VLMUL,PULP
+Emission,ELFObjectWriter,getRelocType,PULP
+Emission,ELFStreamer,calculateContentSize,PULP
+Emission,ELFStreamer,setAttributeItem1,PULP
+Emission,ELFStreamer,setAttributeItem2,PULP
+Emission,ELFStreamer,setAttributeItems,PULP
+Emission,FixupKind,enumFixups,PULP
+Emission,InstPrinter,printBranchOperand,PULP
+Emission,MCCodeEmitter,getVMaskReg,PULP
+Emission,MCExpr,enumVariantKind,PULP
+Emission,MCExpr,printImpl,PULP
+Emission,MCTargetDesc,evaluateBranch,PULP
+Emission,MCTargetDesc,LLVMInitializeTargetMC,PULP
+Optimization,CleanupVSETVLI,getRequiredProperties,PULP
+Optimization,MergeBaseOffset,getRequiredProperties,PULP
+Optimization,PULPHardWareLoops,containsInvalidInstruction,PULP
+Optimization,PULPHardWareLoops,getComparisonKind,PULP
+Optimization,PULPHardWareLoops,getNegatedComparison,PULP
+Optimization,PULPHardWareLoops,getSwappedComparison,PULP
+Optimization,SNITCHFrepLoops,getComparisonKind,PULP
+Scheduling,InstrInfo,isFunctionSafeToOutlineFrom,PULP
+Scheduling,InstrInfo,isLoadFromStackSlot,PULP
+Scheduling,InstrInfo,isMBBSafeToOutlineFrom,PULP
+Scheduling,InstrInfo,isStoreToStackSlot,PULP
+Scheduling,InstrInfo,loadRegFromStackSlot,PULP
+Scheduling,InstrInfo,storeRegToStackSlot,PULP
+Scheduling,MachineFunctionInfo,getUsedSSR,PULP
+Scheduling,Subtarget,enableLinkerRelax,PULP
+Scheduling,Subtarget,enableRVCHintInstrs,PULP
+Scheduling,Subtarget,enableSaveRestore,PULP
+Scheduling,Subtarget,getXLen,PULP
+Scheduling,Subtarget,getXLenVT,PULP
+Scheduling,Subtarget,is64Bit,PULP
+Scheduling,TargetInfo,LLVMInitializeTargetInfo,PULP
+Scheduling,TargetMachine,addPreEmitPass2,PULP
+Scheduling,TargetMachine,LLVMInitializeTarget,PULP
+Scheduling,TargetObjectFile,getSectionForConstant,PULP
+Scheduling,TargetTransformInfo,getIntImmCostIntrin,PULP
+Selection,FrameLowering,hasBP,PULP
+Selection,FrameLowering,hasFP,PULP
+Selection,FrameLowering,hasReservedCallFrame,PULP
+Selection,InstructionSelector,InstructionSelector,PULP
+Selection,ISelDAGToDAG,SelectAddrFI,PULP
+Selection,ISelLowering,getConstraintType,PULP
+Selection,ISelLowering,getInlineAsmMemConstraint,PULP
+Selection,ISelLowering,getPointerMemTy,PULP
+Selection,ISelLowering,getPointerTy,PULP
+Selection,ISelLowering,getScalarShiftAmountTy,PULP
+Selection,ISelLowering,getTargetNodeName,PULP
+Selection,ISelLowering,isLegalAddressingMode,PULP
+Selection,ISelLowering,LowerAsmOperandForConstraint,PULP
+Selection,ISelLowering,LowerGlobalAddress,PULP
+Selection,ISelLowering,LowerGlobalTLSAddress,PULP
+Selection,ISelLowering,lowerJumpTable,PULP
+Selection,ISelLowering,lowerSELECT,PULP
+Selection,ISelLowering,mayBeEmittedAsTailCall,PULP
+Selection,ISelLowering,NodeType,PULP
+Selection,ISelLowering,shouldExpandAtomicCmpXchgInIR,PULP
+Selection,ISelLowering,shouldExpandAtomicRMWInIR,PULP
+Selection,ISelLowering,shouldSignExtendTypeInLibCall,PULP
+Selection,MCInstLower,lowerMachineOperandToMCOperand,PULP
+Selection,MCInstLower,lowerSymbolOperand,PULP
+Allocation,RegisterInfo,getCalleeSavedRegs,RISCV
+Allocation,RegisterInfo,getFrameRegister,RISCV
+Allocation,RegisterInfo,getReservedRegs,RISCV
+Assembler,AsmParser,isRV64,RISCV
+Assembler,AsmParser,isRV64-2,RISCV
+Assembler,AsmParser,isSImm6NonZero,RISCV
+Assembler,AsmParser,isSImm9Lsb0,RISCV
+Assembler,AsmParser,parseImmediate,RISCV
+Assembler,AsmParser,parseOperand,RISCV
+Assembler,AsmParser,validateTargetOperandClass,RISCV
+Assembler,AsmPrinter,isSImm12Lsb0,RISCV
+Disassembler,Disassembler,addImplySP,RISCV
+Disassembler,Disassembler,decodeSImmNonZeroOperand,RISCV
+Disassembler,Disassembler,decodeUImmNonZeroOperand,RISCV
+Disassembler,Disassembler,DecodeVRRegisterClass,RISCV
+Disassembler,Disassembler,LLVMInitializeDisassembler,RISCV
+Emission,AsmBackend,applyFixup,RISCV
+Emission,AsmBackend,fixupNeedsRelaxationAdvanced,RISCV
+Emission,AsmBackend,getFixupKind,RISCV
+Emission,AsmBackend,getRelaxedOpcode,RISCV
+Emission,AsmBackend,mayNeedRelaxation,RISCV
+Emission,AsmInfo,MCAsmInfo,RISCV
+Emission,BaseInfo,ABI,RISCV
+Emission,BaseInfo,getTargetABI,RISCV
+Emission,BaseInfo,stringToRoundingMode,RISCV
+Emission,BaseInfo,VLMUL,RISCV
+Emission,ELFObjectWriter,getRelocType,RISCV
+Emission,ELFStreamer,calculateContentSize,RISCV
+Emission,ELFStreamer,setAttributeItem1,RISCV
+Emission,ELFStreamer,setAttributeItem2,RISCV
+Emission,ELFStreamer,setAttributeItems,RISCV
+Emission,InstPrinter,printBranchOperand,RISCV
+Emission,MCCodeEmitter,getVMaskReg,RISCV
+Emission,MCExpr,enumVariantKind,RISCV
+Emission,MCExpr,printImpl,RISCV
+Emission,MCTargetDesc,LLVMInitializeTargetMC,RISCV
+Optimization,CleanupVSETVLI,getRequiredProperties,RISCV
+Optimization,CleanupVSETVLI,runOnMachineFunction,RISCV
+Optimization,MergeBaseOffset,getRequiredProperties,RISCV
+Scheduling,InstrInfo,isFunctionSafeToOutlineFrom,RISCV
+Scheduling,InstrInfo,isLoadFromStackSlot,RISCV
+Scheduling,InstrInfo,isMBBSafeToOutlineFrom,RISCV
+Scheduling,InstrInfo,isStoreToStackSlot,RISCV
+Scheduling,InstrInfo,loadRegFromStackSlot,RISCV
+Scheduling,InstrInfo,storeRegToStackSlot,RISCV
+Scheduling,Subtarget,enableLinkerRelax,RISCV
+Scheduling,Subtarget,enableRVCHintInstrs,RISCV
+Scheduling,Subtarget,enableSaveRestore,RISCV
+Scheduling,Subtarget,getXLen,RISCV
+Scheduling,Subtarget,getXLenVT,RISCV
+Scheduling,Subtarget,is64Bit,RISCV
+Scheduling,TargetInfo,LLVMInitializeTargetInfo,RISCV
+Scheduling,TargetMachine,addPreEmitPass2,RISCV
+Scheduling,TargetMachine,LLVMInitializeTarget,RISCV
+Scheduling,TargetObjectFile,getSectionForConstant,RISCV
+Scheduling,TargetTransformInfo,getIntImmCostIntrin,RISCV
+Selection,FrameLowering,hasBP,RISCV
+Selection,FrameLowering,hasFP,RISCV
+Selection,FrameLowering,hasReservedCallFrame,RISCV
+Selection,InstructionSelector,InstructionSelector,RISCV
+Selection,ISelDAGToDAG,SelectAddrFI,RISCV
+Selection,ISelLowering,getConstraintType,RISCV
+Selection,ISelLowering,getInlineAsmMemConstraint,RISCV
+Selection,ISelLowering,getTargetNodeName,RISCV
+Selection,ISelLowering,isLegalAddressingMode,RISCV
+Selection,ISelLowering,LowerAsmOperandForConstraint,RISCV
+Selection,ISelLowering,LowerGlobalAddress,RISCV
+Selection,ISelLowering,LowerGlobalTLSAddress,RISCV
+Selection,ISelLowering,lowerJumpTable,RISCV
+Selection,ISelLowering,lowerSELECT,RISCV
+Selection,ISelLowering,mayBeEmittedAsTailCall,RISCV
+Selection,ISelLowering,NodeType,RISCV
+Selection,ISelLowering,shouldExpandAtomicCmpXchgInIR,RISCV
+Selection,ISelLowering,shouldExpandAtomicRMWInIR,RISCV
+Selection,ISelLowering,shouldSignExtendTypeInLibCall,RISCV
+Selection,MCInstLower,lowerMachineOperandToMCOperand,RISCV
+Selection,MCInstLower,lowerSymbolOperand,RISCV
+Emission,MCTargetDesc,LLVMInitializeTargetMC,XCore
+Scheduling,InstrInfo,GetCondBranchFromCond,XCore
+Scheduling,InstrInfo,GetOppositeBranchCondition,XCore
+Scheduling,InstrInfo,IsCondBranch,XCore
+Scheduling,TargetMachine,addPreEmitPass,XCore
+Selection,ISelLowering,enumNodeType,XCore
+Selection,ISelLowering,getTargetNodeName,XCore

Scripts/Exp/Accuracy/calculate_accuracy.py

@@ -0,0 +1,178 @@
+import os, sys,string,re,glob
+
+import json
+import csv
+import copy
+
+
+import pathlib
+import time
+
+folder = str(pathlib.Path(__file__).parent.resolve())
+#Total_encas
+
+func_num_dic = {
+    "riscv" : 568,
+    "pulp"  : 698,
+    "xcore" : 188
+}
+
+
+
+wrong_lis_all = []
+wrong_stmt = []
+err_def_dic = {}
+def get_wrong_list():
+    global wrong_stmt
+    global wrong_lis_all
+    global err_def_dic
+    with open(folder+"/wrong_func_list_def.csv", 'r', encoding='utf-8') as fcsv:
+        reader = csv.reader(fcsv)
+        for row in reader:
+            if row[0] == "idx":
+                continue
+            wrong_stmt.append(row[0].strip().lower() + " " + row[1].strip().lower() + " " + row[2].strip().lower())
+            wrong_lis_all.append(" ".join(row))
+            if " ".join([row[2], row[3]]) not in err_def_dic.keys():
+                err_def_dic[" ".join([row[2], row[3]])]= 1
+            else:
+                err_def_dic[" ".join([row[2], row[3]])] += 1
+
+def calculate_accuracy():
+    func_res = {}
+    stable_stmt_dic = {}
+    all_func_lis = []
+    global wrong_stmt
+    global wrong_lis_all
+    global err_def_dic
+    total_dic = {}
+    wrong_dic = {}
+    asm_file = []
+    for line in open(folder+"/result.jsonl", 'r', encoding="utf-8"):
+        dic = json.loads(line)
+        all_func_lis.append(dic["File"].strip().lower() + " " + dic["Func"].strip().lower() + " " + dic["Target"].strip().lower())
+        
+        if int(dic["vega_pre"]) == 1:
+            if " ".join([dic["Target"], dic["Module"], dic["File"], dic["Func"]]) not in func_res.keys():
+                func_res[" ".join([dic["Target"], dic["Module"], dic["File"], dic["Func"]])] = [dic["vega_code"].replace("zmtarzm", dic["Target"])]
+            else:
+                func_res[" ".join([dic["Target"], dic["Module"], dic["File"], dic["Func"]])].append(dic["vega_code"].replace("zmtarzm", dic["Target"]))
+            if " ".join([dic["Target"], dic["Module"]]) not in stable_stmt_dic.keys():
+                stable_stmt_dic[" ".join([dic["Target"], dic["Module"]])] = [0, 0]
+            if dic["Stable"].lower() == "true":
+                stable_stmt_dic[" ".join([dic["Target"], dic["Module"]])][0] += 1
+                stable_stmt_dic[" ".join([dic["Target"], dic["Module"]])][1] += 1
+            else:
+                stable_stmt_dic[" ".join([dic["Target"], dic["Module"]])][1] += 1
+
+        if dic["Target"] + " " + dic["Module"] not in total_dic.keys():
+            total_dic[dic["Target"] + " " + dic["Module"]] = [dic["File"].strip() + " " + dic["Func"].strip() + " " + dic["Target"].strip()]
+            wrong_dic[dic["Target"] + " " + dic["Module"]] = []
+        else:
+            total_dic[dic["Target"] + " " + dic["Module"]].append(dic["File"].strip() + " " + dic["Func"].strip() + " " + dic["Target"].strip())
+        if dic["File"].strip().lower() + " " + dic["Func"].strip().lower() + " " + dic["Target"].strip().lower() in wrong_stmt:
+            #print(dic["File"].strip() + " " + dic["Func"].strip() + " " + dic["Target"].strip())
+            wrong_dic[dic["Target"] + " " + dic["Module"]].append(dic["File"].strip() + " " + dic["Func"].strip() + " " + dic["Target"].strip())
+        if dic["ans_code"].replace(" ", "") != dic["vega_code"].replace(" ", "") or dic["ans_pre"] != dic["vega_pre"]:
+            wrong_dic[dic["Target"] + " " + dic["Module"]].append(dic["File"].strip() + " " + dic["Func"].strip() + " " + dic["Target"].strip())
+            if dic["ans_code"] != dic["vega_code"]:
+                wrong_lis_all.append(" ".join([dic["File"], dic["Func"], dic["Target"], dic["Module"], "Err_V"]))
+            if dic["ans_pre"] != dic["vega_pre"]:
+                wrong_lis_all.append(" ".join([dic["File"], dic["Func"], dic["Target"], dic["Module"], "Err_CS"]))
+                
+    all_func_lis = list(set(all_func_lis))
+
+    with open(folder+"/vega_result.csv", 'a', encoding='utf-8', newline="") as f:
+        f_csv = csv.writer(f)
+        avg_dic = {}
+        all_dic = {}
+        for k in total_dic.keys():
+            Correct_Func_Num = len(list(set(total_dic[k])))-len(list(set(wrong_dic[k])))
+            Total_Func_Num = len(list(set(total_dic[k])))
+            Accuracy_Func = 1-round(len(list(set(wrong_dic[k]))) * 1.0 / len(list(set(total_dic[k]))), 3)
+            Wrong_Func_Percentage = round(len(list(set(wrong_dic[k]))) * 1.0 / len(list(set(total_dic[k]))), 3)
+            Pre_Equal_1_Stmt_Percentage = round(stable_stmt_dic[k][0]/stable_stmt_dic[k][1], 3)
+            Pre_Less_1_Stmt_Percentage = 1 - round(stable_stmt_dic[k][0]/stable_stmt_dic[k][1], 3)
+            if k.split(" ")[0] not in avg_dic.keys():
+                avg_dic[k.split(" ")[0]] = Accuracy_Func
+                all_dic[k.split(" ")[0]] = Correct_Func_Num
+            else:
+                avg_dic[k.split(" ")[0]] += Accuracy_Func
+                all_dic[k.split(" ")[0]] += Correct_Func_Num
+            tem_k = k.replace("PULP", "RI5CY")
+            f_csv.writerow(tem_k.split(" ") + [Correct_Func_Num, Total_Func_Num,  Accuracy_Func, Wrong_Func_Percentage, Pre_Equal_1_Stmt_Percentage, Pre_Less_1_Stmt_Percentage])
+
+        for k in avg_dic:
+            if k.lower() == "riscv":
+                f_csv.writerow([k, "AVG", round(avg_dic[k] / 7.0, 3)])
+                f_csv.writerow([k, "ALL", round(all_dic[k] / func_num_dic[k.lower()], 3)])
+            elif k.lower() == "pulp":
+                f_csv.writerow(["RI5CY", "AVG", round(avg_dic[k] / 7.0, 3)])
+                f_csv.writerow(["RI5CY", "ALL", round(all_dic[k] / func_num_dic[k.lower()], 3)])
+            else:
+                f_csv.writerow([k, "AVG", round(avg_dic[k] / 6.0, 3)])
+                f_csv.writerow([k, "ALL", round(all_dic[k] / func_num_dic[k.lower()], 3)])
+
+    
+    
+    for k in func_res.keys():
+        Tar_Path = folder + "/../ForkFlow/VEGA_Code/" + "/".join(k.split(" ")) + ".cpp"
+        Tar_Path = Tar_Path.replace("enum/NodeType", "enum NodeType")
+        Tar_Path = Tar_Path.replace("enum/CondCode", "enum CondCode")
+        Tar_Path = Tar_Path.replace("ExpandSSRInsts/ExpandPseudo", "ExpandSSRInsts/ExpandSSRInsts")
+        if os.path.exists(Tar_Path):
+            with open(Tar_Path, 'w') as file:
+                for idx, l in enumerate(func_res[k]):
+                    if idx < len(func_res[k])-1:
+                        file.write(l)
+                        file.write("\n")
+                    else:
+                        file.write(l)
+        else:
+            print(Tar_Path)
+
+    return total_dic
+
+
+if __name__ == '__main__':
+    get_wrong_list()
+    with open(folder+"/vega_result.csv", 'w', encoding='utf-8', newline="") as f:
+        f_csv = csv.writer(f)
+        f_csv.writerow(["Target", "Module", "Correct", "Total", "Accurate", "Inaccurate", "Confidence Score≈1.00", "Confidence Score in [0.50, 1.00)"])
+    total_dic = calculate_accuracy()
+    wrong_lis_all = list(set(wrong_lis_all))
+    with open(folder+"/wrong_list_all.csv", 'w', encoding='utf-8', newline="") as f:
+        f_csv = csv.writer(f)
+        for err in wrong_lis_all:
+            f_csv.writerow(err.split(" "))
+    with open(folder+"/../ForkFlow/wrong_list_all.csv", 'w', encoding='utf-8', newline="") as f:
+        f_csv = csv.writer(f)
+        for err in wrong_lis_all:
+            f_csv.writerow(err.split(" "))
+    
+    wrong_dic = {}
+    with open(folder+"/wrong_list_all.csv", 'r', encoding='utf-8') as f:
+        f_csv = csv.reader(f)
+        for row in f_csv:
+            if " ".join([row[-3].lower(), row[-1].lower()]) not in wrong_dic.keys():
+                wrong_dic[" ".join([row[-3].lower(), row[-1].lower()])] = 1
+            else:
+                wrong_dic[" ".join([row[-3].lower(), row[-1].lower()])] += 1
+    #print(wrong_dic)
+    target_func_num_dic = {}
+    for k in total_dic:
+        if k.split(" ")[0].lower() not in target_func_num_dic:
+            target_func_num_dic[k.split(" ")[0].lower()] = len(list(set(total_dic[k])))
+        else:
+            target_func_num_dic[k.split(" ")[0].lower()] += len(list(set(total_dic[k])))
+    
+    with open(folder+"/err_percentage.csv", 'w', encoding='utf-8', newline = "") as f:
+        f_csv = csv.writer(f)
+        for k in target_func_num_dic:
+            #print(target_func_num_dic[k])
+            for err_type in ["err_v", "err_cs", "err_def"]:
+                if k + " " + err_type in wrong_dic.keys():
+                    
+                    f_csv.writerow([k.replace("pulp", "ri5cy"), err_type, round(float(wrong_dic[k + " " + err_type]) / float(target_func_num_dic[k]), 3)])
+                else:
+                    f_csv.writerow([k.replace("pulp", "ri5cy"), err_type, 0])

Scripts/Exp/Accuracy/calculate_purple.py

@@ -0,0 +1,42 @@
+import os, sys,string,re,glob
+
+import json
+import csv
+import copy
+
+
+import pathlib
+import time
+
+folder = str(pathlib.Path(__file__).parent.resolve())
+#Total_encas
+
+
+
+def calculate_template():
+    total_dic = {}
+    for line in open(folder+"/result.jsonl", 'r', encoding="utf-8"):
+        dic = json.loads(line)
+        if dic["Target"].lower() + " " + dic["Module"].lower() not in total_dic.keys():
+            total_dic[dic["Target"].lower() + " " + dic["Module"].lower()] = set()
+        total_dic[dic["Target"].lower() + " " + dic["Module"].lower()].add(dic["File"].strip() + " " + dic["Func"].strip() + " " + dic["Target"].strip())
+
+
+    res_dic = {}
+    with open(folder+"/Accurate_Func_Merged.csv", 'r', encoding='utf-8') as f:
+        f_csv = csv.reader(f)
+        for row in f_csv:
+            if " ".join([row[-1], row[0]]).lower() not in res_dic:
+                res_dic[" ".join([row[-1], row[0]]).lower()] = 1
+            else:
+                res_dic[" ".join([row[-1], row[0]]).lower()] += 1
+        with open(folder+"/fig8_purple.csv", 'w', encoding='utf-8', newline="") as f:
+            f_csv = csv.writer(f)
+            for k in res_dic.keys():
+                f_csv.writerow([k.split(' ')[0].replace("pulp", "ri5cy"), k.split(' ')[1], round(float(res_dic[k])/float(len(list(total_dic[k]))), 3)])
+
+
+
+if __name__ == '__main__':
+    calculate_template()
+    

Scripts/Exp/Accuracy/wrong_func_list_def.csv

@@ -0,0 +1,366 @@
+RegisterInfo,eliminateFrameIndex,PULP,Allocation,Err_Def
+RegisterInfo,getReservedRegs,PULP,Allocation,Err_Def
+RegisterInfo,hasReservedSpillSlot,PULP,Allocation,Err_Def
+AsmParser,addFenceArgOperands,PULP,Assembler,Err_Def
+AsmParser,AsmParser,PULP,Assembler,Err_Def
+AsmParser,classifySymbolRef,PULP,Assembler,Err_Def
+AsmParser,defaultMaskRegOp,PULP,Assembler,Err_Def
+AsmParser,getFeatureBits,PULP,Assembler,Err_Def
+AsmParser,getRoundingMode,PULP,Assembler,Err_Def
+AsmParser,isFenceArg,PULP,Assembler,Err_Def
+AsmParser,isFRMArg,PULP,Assembler,Err_Def
+AsmParser,MatchAndEmitInstruction,PULP,Assembler,Err_Def
+AsmParser,matchRegisterNameHelper,PULP,Assembler,Err_Def
+AsmParser,Operand2,PULP,Assembler,Err_Def
+AsmParser,parseAtomicMemOp,PULP,Assembler,Err_Def
+AsmParser,parseCallSymbol,PULP,Assembler,Err_Def
+AsmParser,parseCSRSyestemRegister,PULP,Assembler,Err_Def
+AsmParser,ParseDirective,PULP,Assembler,Err_Def
+AsmParser,ParseInstruction,PULP,Assembler,Err_Def
+AsmParser,parseJALOffset,PULP,Assembler,Err_Def
+AsmParser,parseMaskReg,PULP,Assembler,Err_Def
+AsmParser,parseMemOpBaseReg,PULP,Assembler,Err_Def
+AsmParser,parseOperand,PULP,Assembler,Err_Def
+AsmParser,parsePseudoJumpSymbol,PULP,Assembler,Err_Def
+AsmParser,parseRegister2,PULP,Assembler,Err_Def
+AsmParser,parseVTypeI,PULP,Assembler,Err_Def
+AsmParser,print,PULP,Assembler,Err_Def
+Disassembler,decodeFRMArg,PULP,Disassembler,Err_Def
+Disassembler,DecodeGPRRegisterClass,PULP,Disassembler,Err_Def
+Disassembler,decodeRVCInstrRdRs1UImm,PULP,Disassembler,Err_Def
+Disassembler,decodeRVCInstrRdSImm,PULP,Disassembler,Err_Def
+Disassembler,decodeRVCInstrSImm,PULP,Disassembler,Err_Def
+Disassembler,getInstruction,PULP,Disassembler,Err_Def
+AsmBackend,AsmBackend,PULP,Emission,Err_Def
+AsmBackend,evaluateTargetFixup,PULP,Emission,Err_Def
+AsmBackend,relaxInstruction,PULP,Emission,Err_Def
+AsmBackend,requiresDiffExpressionRelocations,PULP,Emission,Err_Def
+AsmBackend,shouldForceRelocation,PULP,Emission,Err_Def
+AsmBackend,shouldInsertExtraNopBytesForCodeAlign,PULP,Emission,Err_Def
+AsmBackend,shouldInsertFixupForCodeAlign,PULP,Emission,Err_Def
+AsmBackend,willForceRelocations,PULP,Emission,Err_Def
+BaseInfo,computeTargetABI,PULP,Emission,Err_Def
+BaseInfo,validate,PULP,Emission,Err_Def
+BaseInfo,VMTs,PULP,Emission,Err_Def
+ELFStreamer,TargetELFStreamer,PULP,Emission,Err_Def
+InstPrinter,printAtomicMemOp,PULP,Emission,Err_Def
+InstPrinter,printCSRSystemRegister,PULP,Emission,Err_Def
+InstPrinter,printFenceArg,PULP,Emission,Err_Def
+InstPrinter,printFRMArg,PULP,Emission,Err_Def
+InstPrinter,printInst,PULP,Emission,Err_Def
+InstPrinter,printVMaskReg,PULP,Emission,Err_Def
+InstPrinter,printVTypeI,PULP,Emission,Err_Def
+MatInt,generateInstSeq,PULP,Emission,Err_Def
+MatInt,getIntMatCost,PULP,Emission,Err_Def
+MCCodeEmitter,encodeInstruction,PULP,Emission,Err_Def
+MCCodeEmitter,getImmOpValue,PULP,Emission,Err_Def
+MCCodeEmitter,getImmOpValueAsr1,PULP,Emission,Err_Def
+MCCodeEmitter,getImmOpValueMinus1,PULP,Emission,Err_Def
+MCExpr,evaluateAsConstant,PULP,Emission,Err_Def
+MCExpr,getPCRelHiFixup,PULP,Emission,Err_Def
+TargetStreamer,emitTargetAttributes,PULP,Emission,Err_Def
+CleanupVSETVLI,runOnMachineBasicBlock,PULP,Optimization,Err_Def
+ExpandAtomicPseudoInsts,expandMI,PULP,Optimization,Err_Def
+ExpandPseudoInsts,expandMI,PULP,Optimization,Err_Def
+ExpandSDMAInsts,expandMI,PULP,Optimization,Err_Def
+ExpandSSRInsts,expandMI,PULP,Optimization,Err_Def
+ExpandSSRInsts,runOnMachineFunction,PULP,Optimization,Err_Def
+MergeBaseOffset,runOnMachineFunction,PULP,Optimization,Err_Def
+PULPFixupHwLoops,runOnMachineFunction,PULP,Optimization,Err_Def
+PULPHardwareLoops,checkForImmediate,PULP,Optimization,Err_Def
+PULPHardwareLoops,convertToHardwareLoop,PULP,Optimization,Err_Def
+PULPHardwareLoops,findInductionRegister,PULP,Optimization,Err_Def
+PULPHardwareLoops,getLoopTripCount,PULP,Optimization,Err_Def
+PULPHardwareLoops,isInvalidLoopOperation,PULP,Optimization,Err_Def
+PULPHardwareLoops,runOnMachineFunction,PULP,Optimization,Err_Def
+SNITCHFrepLoops,checkForImmediate,PULP,Optimization,Err_Def
+SNITCHFrepLoops,containsInvalidInstruction,PULP,Optimization,Err_Def
+SNITCHFrepLoops,convertToHardwareLoop,PULP,Optimization,Err_Def
+SNITCHFrepLoops,findBranchInstruction,PULP,Optimization,Err_Def
+SNITCHFrepLoops,findInductionRegister,PULP,Optimization,Err_Def
+SNITCHFrepLoops,getLoopTripCount,PULP,Optimization,Err_Def
+SNITCHFrepLoops,isInvalidLoopOperation,PULP,Optimization,Err_Def
+SNITCHFrepLoops,runOnMachineFunction,PULP,Optimization,Err_Def
+InstrInfo,buildOutlinedFrame,PULP,Scheduling,Err_Def
+InstrInfo,copyPhysReg,PULP,Scheduling,Err_Def
+InstrInfo,getInstSizeInBytes,PULP,Scheduling,Err_Def
+InstrInfo,getOutliningCandidateInfo,PULP,Scheduling,Err_Def
+InstrInfo,getOutliningType,PULP,Scheduling,Err_Def
+InstrInfo,insertIndirectBranch,PULP,Scheduling,Err_Def
+InstrInfo,insertOutlinedCall,PULP,Scheduling,Err_Def
+InstrInfo,isAsCheapAsAMove,PULP,Scheduling,Err_Def
+InstrInfo,isCopyInstrImpl,PULP,Scheduling,Err_Def
+InstrInfo,movImm,PULP,Scheduling,Err_Def
+InstrInfo,verifyInstruction,PULP,Scheduling,Err_Def
+MachineFunctionInfo,getMoveF64FrameIndex,PULP,Scheduling,Err_Def
+MachineFunctionInfo,useSaveRestoreLibCalls,PULP,Scheduling,Err_Def
+Subtarget,initializeSubtargetDependencies,PULP,Scheduling,Err_Def
+TargetMachine,addPreRegAlloc,PULP,Scheduling,Err_Def
+TargetMachine,setTargetOptionsWithModuleMetadata,PULP,Scheduling,Err_Def
+TargetMachine,TargetMachine,PULP,Scheduling,Err_Def
+TargetObjectFile,getModuleMetadata,PULP,Scheduling,Err_Def
+TargetObjectFile,isGlobalInSmallSection,PULP,Scheduling,Err_Def
+TargetTransformInfo,getIntImmCost,PULP,Scheduling,Err_Def
+TargetTransformInfo,getIntImmCostInst,PULP,Scheduling,Err_Def
+FrameLowering,canUseAsEpilogue,PULP,Selection,Err_Def
+FrameLowering,canUseAsPrologue,PULP,Selection,Err_Def
+FrameLowering,determineCalleeSaves,PULP,Selection,Err_Def
+FrameLowering,emitEpilogue,PULP,Selection,Err_Def
+FrameLowering,emitPrologue,PULP,Selection,Err_Def
+FrameLowering,getFrameIndexReference,PULP,Selection,Err_Def
+FrameLowering,restoreCalleeSavedRegisters,PULP,Selection,Err_Def
+FrameLowering,spillCalleeSavedRegisters,PULP,Selection,Err_Def
+ISelDAGtoDAG,MatchSLLIUW,PULP,Selection,Err_Def
+ISelDAGtoDAG,MatchSRLIUW,PULP,Selection,Err_Def
+ISelDAGtoDAG,PostprocessISelDAG,PULP,Selection,Err_Def
+ISelDAGtoDAG,Select,PULP,Selection,Err_Def
+ISelDAGtoDAG,selectVLOp,PULP,Selection,Err_Def
+ISelDAGtoDAG,selectVSplat,PULP,Selection,Err_Def
+ISelDAGtoDAG,selectVSplatSimm5,PULP,Selection,Err_Def
+ISelDAGtoDAG,selectVSplatUimm5,PULP,Selection,Err_Def
+ISelLowering,analyzeInputArgs,PULP,Selection,Err_Def
+ISelLowering,analyzeOutputArgs,PULP,Selection,Err_Def
+ISelLowering,CanLowerReturn,PULP,Selection,Err_Def
+ISelLowering,computeKnownBitsForTargetNode,PULP,Selection,Err_Def
+ISelLowering,ComputeNumSignBitsForTargetNode,PULP,Selection,Err_Def
+ISelLowering,decomposeMulByConstant,PULP,Selection,Err_Def
+ISelLowering,EmitInstrWithCustomInserter,PULP,Selection,Err_Def
+ISelLowering,emitLeadingFence,PULP,Selection,Err_Def
+ISelLowering,emitMaskedAtomicCmpXchgIntrinsic,PULP,Selection,Err_Def
+ISelLowering,emitMaskedAtomicRMWIntrinsic,PULP,Selection,Err_Def
+ISelLowering,emitTrailingFence,PULP,Selection,Err_Def
+ISelLowering,getAddr,PULP,Selection,Err_Def
+ISelLowering,getPostIndexedAddressParts,PULP,Selection,Err_Def
+ISelLowering,getRegForInlineAsmConstraint,PULP,Selection,Err_Def
+ISelLowering,getRegisterByName,PULP,Selection,Err_Def
+ISelLowering,getStaticTLSAddr,PULP,Selection,Err_Def
+ISelLowering,getTgtMemIntrinsic,PULP,Selection,Err_Def
+ISelLowering,isDesirableToCommuteWithShift,PULP,Selection,Err_Def
+ISelLowering,isEligibleForTailCallOptimization,PULP,Selection,Err_Def
+ISelLowering,isFPImmLegal,PULP,Selection,Err_Def
+ISelLowering,LowerCall,PULP,Selection,Err_Def
+ISelLowering,lowerEXTRACT_VECTOR_ELT,PULP,Selection,Err_Def
+ISelLowering,LowerFormalArguments,PULP,Selection,Err_Def
+ISelLowering,lowerINSERT_VECTOR_ELT,PULP,Selection,Err_Def
+ISelLowering,LowerINTRINSIC_W_CHAIN,PULP,Selection,Err_Def
+ISelLowering,LowerINTRINSIC_WO_CHAIN,PULP,Selection,Err_Def
+ISelLowering,LowerOperation,PULP,Selection,Err_Def
+ISelLowering,LowerReturn,PULP,Selection,Err_Def
+ISelLowering,lowerShiftLeftParts,PULP,Selection,Err_Def
+ISelLowering,lowerShiftRightParts,PULP,Selection,Err_Def
+ISelLowering,lowerSPLATVECTOR,PULP,Selection,Err_Def
+ISelLowering,lowerVectorMaskExt,PULP,Selection,Err_Def
+ISelLowering,lowerVectorMaskTrunc,PULP,Selection,Err_Def
+ISelLowering,PerformDAGCombine,PULP,Selection,Err_Def
+ISelLowering,ReplaceNodeResults,PULP,Selection,Err_Def
+ISelLowering,shouldExtendTypeInLibCall,PULP,Selection,Err_Def
+ISelLowering,TargetLowering,PULP,Selection,Err_Def
+ISelLowering,targetShrinkDemandedConstant,PULP,Selection,Err_Def
+ISelLowering,validateCCReservedRegs,PULP,Selection,Err_Def
+MCInstLower,lowerMachineInstrToMCInst,PULP,Selection,Err_Def
+RegisterInfo,eliminateFrameIndex,RISCV,Allocation,Err_Def
+RegisterInfo,hasReservedSpillSlot,RISCV,Allocation,Err_Def
+AsmParser,addFenceArgOperands,RISCV,Assembler,Err_Def
+AsmParser,AsmParser,RISCV,Assembler,Err_Def
+AsmParser,classifySymbolRef,RISCV,Assembler,Err_Def
+AsmParser,defaultMaskRegOp,RISCV,Assembler,Err_Def
+AsmParser,getFeatureBits,RISCV,Assembler,Err_Def
+AsmParser,getRoundingMode,RISCV,Assembler,Err_Def
+AsmParser,isFenceArg,RISCV,Assembler,Err_Def
+AsmParser,isFRMArg,RISCV,Assembler,Err_Def
+AsmParser,MatchAndEmitInstruction,RISCV,Assembler,Err_Def
+AsmParser,matchRegisterNameHelper,RISCV,Assembler,Err_Def
+AsmParser,Operand2,RISCV,Assembler,Err_Def
+AsmParser,parseAtomicMemOp,RISCV,Assembler,Err_Def
+AsmParser,parseCallSymbol,RISCV,Assembler,Err_Def
+AsmParser,parseCSRSyestemRegister,RISCV,Assembler,Err_Def
+AsmParser,ParseDirective,RISCV,Assembler,Err_Def
+AsmParser,ParseInstruction,RISCV,Assembler,Err_Def
+AsmParser,parseJALOffset,RISCV,Assembler,Err_Def
+AsmParser,parseMaskReg,RISCV,Assembler,Err_Def
+AsmParser,parsePseudoJumpSymbol,RISCV,Assembler,Err_Def
+AsmParser,parseRegister2,RISCV,Assembler,Err_Def
+AsmParser,parseVTypeI,RISCV,Assembler,Err_Def
+AsmParser,print,RISCV,Assembler,Err_Def
+Disassembler,decodeFRMArg,RISCV,Disassembler,Err_Def
+Disassembler,DecodeGPRRegisterClass,RISCV,Disassembler,Err_Def
+Disassembler,decodeRVCInstrRdRs1UImm,RISCV,Disassembler,Err_Def
+Disassembler,decodeRVCInstrRdSImm,RISCV,Disassembler,Err_Def
+Disassembler,decodeRVCInstrSImm,RISCV,Disassembler,Err_Def
+Disassembler,getInstruction,RISCV,Disassembler,Err_Def
+AsmBackend,AsmBackend,RISCV,Emission,Err_Def
+AsmBackend,evaluateTargetFixup,RISCV,Emission,Err_Def
+AsmBackend,relaxInstruction,RISCV,Emission,Err_Def
+AsmBackend,requiresDiffExpressionRelocations,RISCV,Emission,Err_Def
+AsmBackend,shouldForceRelocation,RISCV,Emission,Err_Def
+AsmBackend,shouldInsertExtraNopBytesForCodeAlign,RISCV,Emission,Err_Def
+AsmBackend,shouldInsertFixupForCodeAlign,RISCV,Emission,Err_Def
+AsmBackend,willForceRelocations,RISCV,Emission,Err_Def
+BaseInfo,computeTargetABI,RISCV,Emission,Err_Def
+BaseInfo,validate,RISCV,Emission,Err_Def
+BaseInfo,VMTs,RISCV,Emission,Err_Def
+ELFStreamer,TargetELFStreamer,RISCV,Emission,Err_Def
+InstPrinter,printAtomicMemOp,RISCV,Emission,Err_Def
+InstPrinter,printCSRSystemRegister,RISCV,Emission,Err_Def
+InstPrinter,printFenceArg,RISCV,Emission,Err_Def
+InstPrinter,printFRMArg,RISCV,Emission,Err_Def
+InstPrinter,printInst,RISCV,Emission,Err_Def
+InstPrinter,printVMaskReg,RISCV,Emission,Err_Def
+InstPrinter,printVTypeI,RISCV,Emission,Err_Def
+MatInt,generateInstSeq,RISCV,Emission,Err_Def
+MatInt,getIntMatCost,RISCV,Emission,Err_Def
+MCCodeEmitter,encodeInstruction,RISCV,Emission,Err_Def
+MCCodeEmitter,getImmOpValue,RISCV,Emission,Err_Def
+MCCodeEmitter,getImmOpValueAsr1,RISCV,Emission,Err_Def
+MCExpr,evaluateAsConstant,RISCV,Emission,Err_Def
+MCExpr,getPCRelHiFixup,RISCV,Emission,Err_Def
+TargetStreamer,emitTargetAttributes,RISCV,Emission,Err_Def
+CleanupVSETVLI,runOnMachineBasicBlock,RISCV,Optimization,Err_Def
+ExpandAtomicPseudoInsts,expandMI,RISCV,Optimization,Err_Def
+ExpandPseudoInsts,expandMI,RISCV,Optimization,Err_Def
+MergeBaseOffset,runOnMachineFunction,RISCV,Optimization,Err_Def
+InstrInfo,buildOutlinedFrame,RISCV,Scheduling,Err_Def
+InstrInfo,copyPhysReg,RISCV,Scheduling,Err_Def
+InstrInfo,getInstSizeInBytes,RISCV,Scheduling,Err_Def
+InstrInfo,getOutliningCandidateInfo,RISCV,Scheduling,Err_Def
+InstrInfo,getOutliningType,RISCV,Scheduling,Err_Def
+InstrInfo,insertIndirectBranch,RISCV,Scheduling,Err_Def
+InstrInfo,insertOutlinedCall,RISCV,Scheduling,Err_Def
+InstrInfo,isAsCheapAsAMove,RISCV,Scheduling,Err_Def
+InstrInfo,isCopyInstrImpl,RISCV,Scheduling,Err_Def
+InstrInfo,movImm,RISCV,Scheduling,Err_Def
+InstrInfo,verifyInstruction,RISCV,Scheduling,Err_Def
+MachineFunctionInfo,getMoveF64FrameIndex,RISCV,Scheduling,Err_Def
+MachineFunctionInfo,useSaveRestoreLibCalls,RISCV,Scheduling,Err_Def
+Subtarget,initializeSubtargetDependencies,RISCV,Scheduling,Err_Def
+TargetMachine,addPreRegAlloc,RISCV,Scheduling,Err_Def
+TargetMachine,TargetMachine,RISCV,Scheduling,Err_Def
+TargetObjectFile,getModuleMetadata,RISCV,Scheduling,Err_Def
+TargetObjectFile,isGlobalInSmallSection,RISCV,Scheduling,Err_Def
+TargetTransformInfo,getIntImmCost,RISCV,Scheduling,Err_Def
+TargetTransformInfo,getIntImmCostInst,RISCV,Scheduling,Err_Def
+FrameLowering,canUseAsEpilogue,RISCV,Selection,Err_Def
+FrameLowering,canUseAsPrologue,RISCV,Selection,Err_Def
+FrameLowering,determineCalleeSaves,RISCV,Selection,Err_Def
+FrameLowering,emitEpilogue,RISCV,Selection,Err_Def
+FrameLowering,emitPrologue,RISCV,Selection,Err_Def
+FrameLowering,getFrameIndexReference,RISCV,Selection,Err_Def
+FrameLowering,restoreCalleeSavedRegisters,RISCV,Selection,Err_Def
+FrameLowering,spillCalleeSavedRegisters,RISCV,Selection,Err_Def
+ISelDAGtoDAG,MatchSLLIUW,RISCV,Selection,Err_Def
+ISelDAGtoDAG,MatchSRLIUW,RISCV,Selection,Err_Def
+ISelDAGtoDAG,PostprocessISelDAG,RISCV,Selection,Err_Def
+ISelDAGtoDAG,Select,RISCV,Selection,Err_Def
+ISelDAGtoDAG,selectVLOp,RISCV,Selection,Err_Def
+ISelDAGtoDAG,selectVSplat,RISCV,Selection,Err_Def
+ISelDAGtoDAG,selectVSplatSimm5,RISCV,Selection,Err_Def
+ISelDAGtoDAG,selectVSplatUimm5,RISCV,Selection,Err_Def
+ISelLowering,analyzeInputArgs,RISCV,Selection,Err_Def
+ISelLowering,analyzeOutputArgs,RISCV,Selection,Err_Def
+ISelLowering,CanLowerReturn,RISCV,Selection,Err_Def
+ISelLowering,computeKnownBitsForTargetNode,RISCV,Selection,Err_Def
+ISelLowering,ComputeNumSignBitsForTargetNode,RISCV,Selection,Err_Def
+ISelLowering,decomposeMulByConstant,RISCV,Selection,Err_Def
+ISelLowering,EmitInstrWithCustomInserter,RISCV,Selection,Err_Def
+ISelLowering,emitLeadingFence,RISCV,Selection,Err_Def
+ISelLowering,emitMaskedAtomicCmpXchgIntrinsic,RISCV,Selection,Err_Def
+ISelLowering,emitMaskedAtomicRMWIntrinsic,RISCV,Selection,Err_Def
+ISelLowering,emitTrailingFence,RISCV,Selection,Err_Def
+ISelLowering,getAddr,RISCV,Selection,Err_Def
+ISelLowering,getRegForInlineAsmConstraint,RISCV,Selection,Err_Def
+ISelLowering,getRegisterByName,RISCV,Selection,Err_Def
+ISelLowering,getStaticTLSAddr,RISCV,Selection,Err_Def
+ISelLowering,getTgtMemIntrinsic,RISCV,Selection,Err_Def
+ISelLowering,isDesirableToCommuteWithShift,RISCV,Selection,Err_Def
+ISelLowering,isEligibleForTailCallOptimization,RISCV,Selection,Err_Def
+ISelLowering,isFPImmLegal,RISCV,Selection,Err_Def
+ISelLowering,LowerCall,RISCV,Selection,Err_Def
+ISelLowering,lowerEXTRACT_VECTOR_ELT,RISCV,Selection,Err_Def
+ISelLowering,LowerFormalArguments,RISCV,Selection,Err_Def
+ISelLowering,lowerINSERT_VECTOR_ELT,RISCV,Selection,Err_Def
+ISelLowering,LowerINTRINSIC_W_CHAIN,RISCV,Selection,Err_Def
+ISelLowering,LowerINTRINSIC_WO_CHAIN,RISCV,Selection,Err_Def
+ISelLowering,LowerOperation,RISCV,Selection,Err_Def
+ISelLowering,LowerReturn,RISCV,Selection,Err_Def
+ISelLowering,lowerShiftLeftParts,RISCV,Selection,Err_Def
+ISelLowering,lowerShiftRightParts,RISCV,Selection,Err_Def
+ISelLowering,lowerSPLATVECTOR,RISCV,Selection,Err_Def
+ISelLowering,lowerVectorMaskExt,RISCV,Selection,Err_Def
+ISelLowering,lowerVectorMaskTrunc,RISCV,Selection,Err_Def
+ISelLowering,PerformDAGCombine,RISCV,Selection,Err_Def
+ISelLowering,ReplaceNodeResults,RISCV,Selection,Err_Def
+ISelLowering,shouldExtendTypeInLibCall,RISCV,Selection,Err_Def
+ISelLowering,TargetLowering,RISCV,Selection,Err_Def
+ISelLowering,targetShrinkDemandedConstant,RISCV,Selection,Err_Def
+ISelLowering,validateCCReservedRegs,RISCV,Selection,Err_Def
+MCInstLower,lowerMachineInstrToMCInst,RISCV,Selection,Err_Def
+RegisterInfo,eliminateCallFramePseudoInstr,XCore,Allocation,Err_Def
+RegisterInfo,eliminateFrameIndex,XCore,Allocation,Err_Def
+RegisterInfo,getCalleeSavedRegs,XCore,Allocation,Err_Def
+AsmPrinter,AsmPrinter,XCore,Assembler,Err_Def
+AsmPrinter,EmitBasicBlockStart,XCore,Assembler,Err_Def
+AsmPrinter,EmitConstantPool,XCore,Assembler,Err_Def
+AsmPrinter,EmitEndOfAsmFile,XCore,Assembler,Err_Def
+AsmPrinter,EmitFunctionEntryLabel,XCore,Assembler,Err_Def
+AsmPrinter,EmitGlobalVariable,XCore,Assembler,Err_Def
+AsmPrinter,EmitInstruction,XCore,Assembler,Err_Def
+AsmPrinter,EmitStartOfAsmFile,XCore,Assembler,Err_Def
+AsmPrinter,printInlineJT,XCore,Assembler,Err_Def
+AsmPrinter,printInlineJT32,XCore,Assembler,Err_Def
+AsmPrinter,PrintSpecial,XCore,Assembler,Err_Def
+AsmPrinter,runOnMachineFunction,XCore,Assembler,Err_Def
+FrameToArgsOffsetElim,runOnMachineFunction,XCore,Optimization,Err_Def
+LoopMetadataLowering,runOnFunction,XCore,Optimization,Err_Def
+SimpleBranchOpt,runOnMachineFunction,XCore,Optimization,Err_Def
+StackAnalysisPrepare,runOnFunction,XCore,Optimization,Err_Def
+StackUsage,runOnMachineFunction,XCore,Optimization,Err_Def
+InstrInfo,analyzeBranch,XCore,Scheduling,Err_Def
+InstrInfo,copyPhysReg,XCore,Scheduling,Err_Def
+InstrInfo,GetInstSizeInBytes,XCore,Scheduling,Err_Def
+InstrInfo,insertBranch,XCore,Scheduling,Err_Def
+MachineFunctionInfo,~FunctionInfo,XCore,Scheduling,Err_Def
+MachineFunctionInfo,Call,XCore,Scheduling,Err_Def
+MachineFunctionInfo,ExternalSymbolCall,XCore,Scheduling,Err_Def
+MachineFunctionInfo,FunctionCall,XCore,Scheduling,Err_Def
+MachineFunctionInfo,FunctionInfo,XCore,Scheduling,Err_Def
+MachineFunctionInfo,FunctionInfo2,XCore,Scheduling,Err_Def
+TargetObjectFile,getExplicitSectionGlobal,XCore,Scheduling,Err_Def
+TargetObjectFile,getSectionForConstant,XCore,Scheduling,Err_Def
+TargetObjectFile,Initialize,XCore,Scheduling,Err_Def
+TargetObjectFile,SelectSectionForGlobal,XCore,Scheduling,Err_Def
+FrameLowering,emitEpilogue,XCore,Selection,Err_Def
+FrameLowering,emitPrologue,XCore,Selection,Err_Def
+FrameLowering,processFunctionBeforeCalleeSavedScan,XCore,Selection,Err_Def
+FrameLowering,restoreCalleeSavedRegisters,XCore,Selection,Err_Def
+FrameLowering,spillCalleeSavedRegisters,XCore,Selection,Err_Def
+ISelDAGToDAG,immBitp,XCore,Selection,Err_Def
+ISelDAGToDAG,immMskBitp,XCore,Selection,Err_Def
+ISelDAGToDAG,Select,XCore,Selection,Err_Def
+ISelDAGToDAG,SelectInlineAsmMemoryOperand,XCore,Selection,Err_Def
+ISelLowering,computeMaskedBitsForTargetNode,XCore,Selection,Err_Def
+ISelLowering,ExpandADDSUB,XCore,Selection,Err_Def
+ISelLowering,isLegalAddImmediate,XCore,Selection,Err_Def
+ISelLowering,isLegalAddressingMode,XCore,Selection,Err_Def
+ISelLowering,LowerBR_JT,XCore,Selection,Err_Def
+ISelLowering,LowerCall,XCore,Selection,Err_Def
+ISelLowering,LowerDYNAMIC_STACKALLOC,XCore,Selection,Err_Def
+ISelLowering,LowerEH_RETURN,XCore,Selection,Err_Def
+ISelLowering,LowerFormalArguments,XCore,Selection,Err_Def
+ISelLowering,LowerFRAME_TO_ARGS_OFFSET,XCore,Selection,Err_Def
+ISelLowering,LowerFRAMEADDR,XCore,Selection,Err_Def
+ISelLowering,LowerGlobalAddress,XCore,Selection,Err_Def
+ISelLowering,LowerGlobalTLSAddress,XCore,Selection,Err_Def
+ISelLowering,LowerINIT_TRAMPOLINE,XCore,Selection,Err_Def
+ISelLowering,LowerINTRINSIC_WO_CHAIN,XCore,Selection,Err_Def
+ISelLowering,LowerLOAD,XCore,Selection,Err_Def
+ISelLowering,LowerOperation,XCore,Selection,Err_Def
+ISelLowering,LowerReturn,XCore,Selection,Err_Def
+ISelLowering,LowerRETURNADDR,XCore,Selection,Err_Def
+ISelLowering,LowerSMUL_LOHI,XCore,Selection,Err_Def
+ISelLowering,LowerSTACKSAVE,XCore,Selection,Err_Def
+ISelLowering,LowerSTORE,XCore,Selection,Err_Def
+ISelLowering,LowerUMUL_LOHI,XCore,Selection,Err_Def
+ISelLowering,PerformDAGCombine,XCore,Selection,Err_Def
+ISelLowering,ReplaceNodeResults,XCore,Selection,Err_Def
+ISelLowering,TargetLowering,XCore,Selection,Err_Def
+SelectionDAGInfo,EmitTargetCodeForMemcpy,XCore,Selection,Err_Def

Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterBankInfo/RegisterBankInfo.cpp

@@ -0,0 +1,2 @@
+MipsRegisterBankInfo::MipsRegisterBankInfo(const TargetRegisterInfo &TRI) : MipsGenRegisterBankInfo() {
+}

Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/RegisterInfo.cpp

@@ -0,0 +1,2 @@
+MipsRegisterInfo::MipsRegisterInfo() : MipsGenRegisterInfo(Mips::RA) {
+}

Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/eliminateFrameIndex.cpp

@@ -0,0 +1,10 @@
+void MipsRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const {
+  MachineInstr &MI = *II;
+  MachineFunction &MF = *MI.getParent()->getParent();
+  LLVM_DEBUG(errs() << "\nFunction : " << MF.getName() << "\n"; errs() << "<--------->\n" << MI);
+  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
+  uint64_t stackSize = MF.getFrameInfo().getStackSize();
+  int64_t spOffset = MF.getFrameInfo().getObjectOffset(FrameIndex);
+  LLVM_DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n" << "spOffset   : " << spOffset << "\n" << "stackSize  : " << stackSize << "\n" << "alignment  : " << DebugStr(MF.getFrameInfo().getObjectAlign(FrameIndex)) << "\n");
+  eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset);
+}

Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/getCallPreservedMask.cpp

@@ -0,0 +1,14 @@
+const uint32_t *MipsRegisterInfo::getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const {
+  const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
+  if (Subtarget.isSingleFloat())
+    return CSR_SingleFloatOnly_RegMask;
+  if (Subtarget.isABI_N64())
+    return CSR_N64_RegMask;
+  if (Subtarget.isABI_N32())
+    return CSR_N32_RegMask;
+  if (Subtarget.isFP64bit())
+    return CSR_O32_FP64_RegMask;
+  if (Subtarget.isFPXX())
+    return CSR_O32_FPXX_RegMask;
+  return CSR_O32_RegMask;
+}

Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/getCalleeSavedRegs.cpp

@@ -0,0 +1,21 @@
+const MCPhysReg *MipsRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
+  const MipsSubtarget &Subtarget = MF->getSubtarget<MipsSubtarget>();
+  const Function &F = MF->getFunction();
+  if (F.hasFnAttribute("interrupt")) {
+    if (Subtarget.hasMips64())
+      return Subtarget.hasMips64r6() ? CSR_Interrupt_64R6_SaveList : CSR_Interrupt_64_SaveList;
+    else
+      return Subtarget.hasMips32r6() ? CSR_Interrupt_32R6_SaveList : CSR_Interrupt_32_SaveList;
+  }
+  if (Subtarget.isSingleFloat())
+    return CSR_SingleFloatOnly_SaveList;
+  if (Subtarget.isABI_N64())
+    return CSR_N64_SaveList;
+  if (Subtarget.isABI_N32())
+    return CSR_N32_SaveList;
+  if (Subtarget.isFP64bit())
+    return CSR_O32_FP64_SaveList;
+  if (Subtarget.isFPXX())
+    return CSR_O32_FPXX_SaveList;
+  return CSR_O32_SaveList;
+}

Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/getFrameRegister.cpp

@@ -0,0 +1,9 @@
+Register MipsRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
+  const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
+  const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
+  bool IsN64 = static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI().IsN64();
+  if (Subtarget.inMips16Mode())
+    return TFI->hasFP(MF) ? Mips::S0 : Mips::SP;
+  else
+    return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) : (IsN64 ? Mips::SP_64 : Mips::SP);
+}

Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/getNoPreservedMask.cpp

@@ -0,0 +1 @@
+None

Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/getPointerRegClass.cpp

@@ -0,0 +1,15 @@
+const TargetRegisterClass *MipsRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) const {
+  MipsABIInfo ABI = MF.getSubtarget<MipsSubtarget>().getABI();
+  MipsPtrClass PtrClassKind = static_cast<MipsPtrClass>(Kind);
+  switch (PtrClassKind) {
+  case MipsPtrClass::Default:
+    return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
+  case MipsPtrClass::GPR16MM:
+    return &Mips::GPRMM16RegClass;
+  case MipsPtrClass::StackPointer:
+    return ABI.ArePtrs64bit() ? &Mips::SP64RegClass : &Mips::SP32RegClass;
+  case MipsPtrClass::GlobalPointer:
+    return ABI.ArePtrs64bit() ? &Mips::GP64RegClass : &Mips::GP32RegClass;
+  }
+  llvm_unreachable("Unknown pointer kind");
+}

Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/getReservedRegs.cpp

@@ -0,0 +1,65 @@
+BitVector MipsRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
+  static const MCPhysReg ReservedGPR32[] = {
+    Mips::ZERO, Mips::K0, Mips::K1, Mips::SP
+  };
+  static const MCPhysReg ReservedGPR64[] = {
+    Mips::ZERO_64, Mips::K0_64, Mips::K1_64, Mips::SP_64
+  };
+  BitVector Reserved(getNumRegs());
+  const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
+  for (unsigned I = 0; I < array_lengthof(ReservedGPR32); ++I)
+    Reserved.set(ReservedGPR32[I]);
+  if (Subtarget.isTargetNaCl()) {
+    Reserved.set(Mips::T6);
+    Reserved.set(Mips::T7);
+    Reserved.set(Mips::T8);
+  }
+  for (unsigned I = 0; I < array_lengthof(ReservedGPR64); ++I)
+    Reserved.set(ReservedGPR64[I]);
+  if (!Subtarget.isABICalls()) {
+    Reserved.set(Mips::GP);
+    Reserved.set(Mips::GP_64);
+  }
+  if (Subtarget.isFP64bit()) {
+    for (MCPhysReg Reg : Mips::AFGR64RegClass)
+      Reserved.set(Reg);
+  } 
+  else {
+    for (MCPhysReg Reg : Mips::FGR64RegClass)
+      Reserved.set(Reg);
+  }
+  if (Subtarget.getFrameLowering()->hasFP(MF)) {
+    if (Subtarget.inMips16Mode())
+      Reserved.set(Mips::S0);
+    else {
+      Reserved.set(Mips::FP);
+      Reserved.set(Mips::FP_64);
+      if (needsStackRealignment(MF) &&  MF.getFrameInfo().hasVarSizedObjects()) {
+        Reserved.set(Mips::S7);
+        Reserved.set(Mips::S7_64);
+      }
+    }
+  }
+  Reserved.set(Mips::HWR29);
+  Reserved.set(Mips::DSPPos);
+  Reserved.set(Mips::DSPSCount);
+  Reserved.set(Mips::DSPCarry);
+  Reserved.set(Mips::DSPEFI);
+  Reserved.set(Mips::DSPOutFlag);
+  for (MCPhysReg Reg : Mips::MSACtrlRegClass)
+    Reserved.set(Reg);
+  if (Subtarget.inMips16Mode()) {
+    const MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
+    Reserved.set(Mips::RA);
+    Reserved.set(Mips::RA_64);
+    Reserved.set(Mips::T0);
+    Reserved.set(Mips::T1);
+    if (MF.getFunction().hasFnAttribute("saveS2") || MipsFI->hasSaveS2())
+      Reserved.set(Mips::S2);
+  }
+  if (Subtarget.useSmallSection()) {
+    Reserved.set(Mips::GP);
+    Reserved.set(Mips::GP_64);
+  }
+  return Reserved;
+}

Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/hasReservedSpillSlot.cpp

@@ -0,0 +1 @@
+None

Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/isAsmClobberable.cpp

@@ -0,0 +1 @@
+None

Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/isConstantPhysReg.cpp

@@ -0,0 +1 @@
+None

Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/requiresFrameIndexScavenging.cpp

@@ -0,0 +1,3 @@
+bool Mips16RegisterInfo::requiresFrameIndexScavenging(const MachineFunction &MF) const {
+  return false;
+}

Scripts/Exp/ForkFlow/Mips_Code/PULP/Allocation/RegisterInfo/requiresRegisterScavenging.cpp

@@ -0,0 +1,3 @@
+bool MipsRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
+  return true;
+}

Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/AsmParser.cpp

@@ -0,0 +1,24 @@
+MipsAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser, const MCInstrInfo &MII, const MCTargetOptions &Options) : MCTargetAsmParser(Options, sti, MII), ABI(MipsABIInfo::computeTargetABI(Triple(sti.getTargetTriple()), sti.getCPU(), Options)) {
+    MCAsmParserExtension::Initialize(parser);
+    parser.addAliasForDirective(".asciiz", ".asciz");
+    parser.addAliasForDirective(".hword", ".2byte");
+    parser.addAliasForDirective(".word", ".4byte");
+    parser.addAliasForDirective(".dword", ".8byte");
+    setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
+    AssemblerOptions.push_back(std::make_unique<MipsAssemblerOptions>(getSTI().getFeatureBits()));
+    AssemblerOptions.push_back(std::make_unique<MipsAssemblerOptions>(getSTI().getFeatureBits()));
+    getTargetStreamer().updateABIInfo(*this);
+    if (!isABI_O32() && !useOddSPReg() != 0)
+      report_fatal_error("-mno-odd-spreg requires the O32 ABI");
+    CurrentFn = nullptr;
+    IsPicEnabled = getContext().getObjectFileInfo()->isPositionIndependent();
+    IsCpRestoreSet = false;
+    CpRestoreOffset = -1;
+    GPReg = ABI.GetGlobalPtr();
+    const Triple &TheTriple = sti.getTargetTriple();
+    IsLittleEndian = TheTriple.isLittleEndian();
+    if (getSTI().getCPU() == "mips64r6" && inMicroMipsMode())
+      report_fatal_error("microMIPS64R6 is not supported", false);
+    if (!isABI_O32() && inMicroMipsMode())
+      report_fatal_error("microMIPS64 is not supported", false);
+  }

Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/KindTy.cpp

@@ -0,0 +1,7 @@
+enum KindTy {
+    k_Immediate,
+    k_Memory,
+    k_RegisterIndex,
+    k_Token,
+    k_RegList,
+} Kind;

Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/LLVMInitializeAsmParser.cpp

@@ -0,0 +1,6 @@
+extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsAsmParser() {
+  RegisterMCAsmParser<MipsAsmParser> X(getTheMipsTarget());
+  RegisterMCAsmParser<MipsAsmParser> Y(getTheMipselTarget());
+  RegisterMCAsmParser<MipsAsmParser> A(getTheMips64Target());
+  RegisterMCAsmParser<MipsAsmParser> B(getTheMips64elTarget());
+}

Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/MatchAndEmitInstruction.cpp

@@ -0,0 +1,142 @@
+bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm) {
+  MCInst Inst;
+  unsigned MatchResult =  MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm);
+  switch (MatchResult) {
+  case Match_Success:
+    if (processInstruction(Inst, IDLoc, Out, STI))
+      return true;
+    return false;
+  case Match_MissingFeature:
+    Error(IDLoc, "instruction requires a CPU feature not currently enabled");
+    return true;
+  case Match_InvalidOperand: {
+    SMLoc ErrorLoc = IDLoc;
+    if (ErrorInfo != ~0ULL) {
+      if (ErrorInfo >= Operands.size())
+        return Error(IDLoc, "too few operands for instruction");
+      ErrorLoc = Operands[ErrorInfo]->getStartLoc();
+      if (ErrorLoc == SMLoc())
+        ErrorLoc = IDLoc;
+    }
+    return Error(ErrorLoc, "invalid operand for instruction");
+  }
+  case Match_NonZeroOperandForSync:
+    return Error(IDLoc, "s-type must be zero or unspecified for pre-MIPS32 ISAs");
+  case Match_NonZeroOperandForMTCX:
+    return Error(IDLoc, "selector must be zero for pre-MIPS32 ISAs");
+  case Match_MnemonicFail:
+    return Error(IDLoc, "invalid instruction");
+  case Match_RequiresDifferentSrcAndDst:
+    return Error(IDLoc, "source and destination must be different");
+  case Match_RequiresDifferentOperands:
+    return Error(IDLoc, "registers must be different");
+  case Match_RequiresNoZeroRegister:
+    return Error(IDLoc, "invalid operand ($zero) for instruction");
+  case Match_RequiresSameSrcAndDst:
+    return Error(IDLoc, "source and destination must match");
+  case Match_NoFCCRegisterForCurrentISA:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "non-zero fcc register doesn't exist in current ISA level");
+  case Match_Immz:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected '0'");
+  case Match_UImm1_0:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 1-bit unsigned immediate");
+  case Match_UImm2_0:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 2-bit unsigned immediate");
+  case Match_UImm2_1:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected immediate in range 1 .. 4");
+  case Match_UImm3_0:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 3-bit unsigned immediate");
+  case Match_UImm4_0:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 4-bit unsigned immediate");
+  case Match_SImm4_0:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 4-bit signed immediate");
+  case Match_UImm5_0:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 5-bit unsigned immediate");
+  case Match_SImm5_0:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 5-bit signed immediate");
+  case Match_UImm5_1:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected immediate in range 1 .. 32");
+  case Match_UImm5_32:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected immediate in range 32 .. 63");
+  case Match_UImm5_33:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected immediate in range 33 .. 64");
+  case Match_UImm5_0_Report_UImm6:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 6-bit unsigned immediate");
+  case Match_UImm5_Lsl2:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected both 7-bit unsigned immediate and multiple of 4");
+  case Match_UImmRange2_64:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected immediate in range 2 .. 64");
+  case Match_UImm6_0:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 6-bit unsigned immediate");
+  case Match_UImm6_Lsl2:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected both 8-bit unsigned immediate and multiple of 4");
+  case Match_SImm6_0:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 6-bit signed immediate");
+  case Match_UImm7_0:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 7-bit unsigned immediate");
+  case Match_UImm7_N1:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected immediate in range -1 .. 126");
+  case Match_SImm7_Lsl2:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected both 9-bit signed immediate and multiple of 4");
+  case Match_UImm8_0:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 8-bit unsigned immediate");
+  case Match_UImm10_0:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 10-bit unsigned immediate");
+  case Match_SImm10_0:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 10-bit signed immediate");
+  case Match_SImm11_0:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 11-bit signed immediate");
+  case Match_UImm16:
+  case Match_UImm16_Relaxed:
+  case Match_UImm16_AltRelaxed:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 16-bit unsigned immediate");
+  case Match_SImm16:
+  case Match_SImm16_Relaxed:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 16-bit signed immediate");
+  case Match_SImm19_Lsl2:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected both 19-bit signed immediate and multiple of 4");
+  case Match_UImm20_0:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 20-bit unsigned immediate");
+  case Match_UImm26_0:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 26-bit unsigned immediate");
+  case Match_SImm32:
+  case Match_SImm32_Relaxed:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 32-bit signed immediate");
+  case Match_UImm32_Coerced:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 32-bit immediate");
+  case Match_MemSImm9:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected memory with 9-bit signed offset");
+  case Match_MemSImm10:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected memory with 10-bit signed offset");
+  case Match_MemSImm10Lsl1:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected memory with 11-bit signed offset and multiple of 2");
+  case Match_MemSImm10Lsl2:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected memory with 12-bit signed offset and multiple of 4");
+  case Match_MemSImm10Lsl3:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected memory with 13-bit signed offset and multiple of 8");
+  case Match_MemSImm11:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected memory with 11-bit signed offset");
+  case Match_MemSImm12:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected memory with 12-bit signed offset");
+  case Match_MemSImm16:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected memory with 16-bit signed offset");
+  case Match_MemSImmPtr:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected memory with 32-bit signed offset");
+  case Match_RequiresPosSizeRange0_32: {
+    SMLoc ErrorStart = Operands[3]->getStartLoc();
+    SMLoc ErrorEnd = Operands[4]->getEndLoc();
+    return Error(ErrorStart, "size plus position are not in the range 0 .. 32", SMRange(ErrorStart, ErrorEnd));
+  }
+  case Match_RequiresPosSizeUImm6: {
+    SMLoc ErrorStart = Operands[3]->getStartLoc();
+    SMLoc ErrorEnd = Operands[4]->getEndLoc();
+    return Error(ErrorStart, "size plus position are not in the range 1 .. 63", SMRange(ErrorStart, ErrorEnd));
+  }
+  case Match_RequiresPosSizeRange33_64: {
+    SMLoc ErrorStart = Operands[3]->getStartLoc();
+    SMLoc ErrorEnd = Operands[4]->getEndLoc();
+    return Error(ErrorStart, "size plus position are not in the range 33 .. 64", SMRange(ErrorStart, ErrorEnd));
+  }
+}
+  llvm_unreachable("Implement any new match types added!");
+}

Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/Operand.cpp

@@ -0,0 +1,2 @@
+MipsOperand(KindTy K, MipsAsmParser &Parser) : MCParsedAsmOperand(), Kind(K), AsmParser(Parser) {
+}

Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/Operand2.cpp

@@ -0,0 +1,2 @@
+MipsOperand(KindTy K, MipsAsmParser &Parser) : MCParsedAsmOperand(), Kind(K), AsmParser(Parser) {
+}

Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/ParseDirective.cpp

@@ -0,0 +1,243 @@
+bool MipsAsmParser::ParseDirective(AsmToken DirectiveID) {
+  MCAsmParser &Parser = getParser();
+  StringRef IDVal = DirectiveID.getString();
+  if (IDVal == ".cpadd") {
+    parseDirectiveCpAdd(DirectiveID.getLoc());
+    return false;
+  }
+  if (IDVal == ".cpload") {
+    parseDirectiveCpLoad(DirectiveID.getLoc());
+    return false;
+  }
+  if (IDVal == ".cprestore") {
+    parseDirectiveCpRestore(DirectiveID.getLoc());
+    return false;
+  }
+  if (IDVal == ".cplocal") {
+    parseDirectiveCpLocal(DirectiveID.getLoc());
+    return false;
+  }
+  if (IDVal == ".ent") {
+    StringRef SymbolName;
+    if (Parser.parseIdentifier(SymbolName)) {
+      reportParseError("expected identifier after .ent");
+      return false;
+    }
+    if (getLexer().isNot(AsmToken::EndOfStatement)) {
+      if (getLexer().isNot(AsmToken::Comma)) {
+        reportParseError("unexpected token, expected end of statement");
+        return false;
+      }
+      Parser.Lex();
+      const MCExpr *DummyNumber;
+      int64_t DummyNumberVal;
+      if (Parser.parseExpression(DummyNumber)) {
+        reportParseError("expected number after comma");
+        return false;
+      }
+      if (!DummyNumber->evaluateAsAbsolute(DummyNumberVal)) {
+        reportParseError("expected an absolute expression after comma");
+        return false;
+      }
+    }
+    if (getLexer().isNot(AsmToken::EndOfStatement)) {
+      reportParseError("unexpected token, expected end of statement");
+      return false;
+    }
+    MCSymbol *Sym = getContext().getOrCreateSymbol(SymbolName);
+    getTargetStreamer().emitDirectiveEnt(*Sym);
+    CurrentFn = Sym;
+    IsCpRestoreSet = false;
+    return false;
+  }
+  if (IDVal == ".end") {
+    StringRef SymbolName;
+    if (Parser.parseIdentifier(SymbolName)) {
+      reportParseError("expected identifier after .end");
+      return false;
+    }
+    if (getLexer().isNot(AsmToken::EndOfStatement)) {
+      reportParseError("unexpected token, expected end of statement");
+      return false;
+    }
+    if (CurrentFn == nullptr) {
+      reportParseError(".end used without .ent");
+      return false;
+    }
+    if ((SymbolName != CurrentFn->getName())) {
+      reportParseError(".end symbol does not match .ent symbol");
+      return false;
+    }
+    getTargetStreamer().emitDirectiveEnd(SymbolName);
+    CurrentFn = nullptr;
+    IsCpRestoreSet = false;
+    return false;
+  }
+  if (IDVal == ".frame") {
+    SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> TmpReg;
+    OperandMatchResultTy ResTy = parseAnyRegister(TmpReg);
+    if (ResTy == MatchOperand_NoMatch || ResTy == MatchOperand_ParseFail) {
+      reportParseError("expected stack register");
+      return false;
+    }
+    MipsOperand &StackRegOpnd = static_cast<MipsOperand &>(*TmpReg[0]);
+    if (!StackRegOpnd.isGPRAsmReg()) {
+      reportParseError(StackRegOpnd.getStartLoc(), "expected general purpose register");
+      return false;
+    }
+    unsigned StackReg = StackRegOpnd.getGPR32Reg();
+    if (Parser.getTok().is(AsmToken::Comma))
+      Parser.Lex();
+    else {
+      reportParseError("unexpected token, expected comma");
+      return false;
+    }
+    const MCExpr *FrameSize;
+    int64_t FrameSizeVal;
+    if (Parser.parseExpression(FrameSize)) {
+      reportParseError("expected frame size value");
+      return false;
+    }
+    if (!FrameSize->evaluateAsAbsolute(FrameSizeVal)) {
+      reportParseError("frame size not an absolute expression");
+      return false;
+    }
+    if (Parser.getTok().is(AsmToken::Comma))
+      Parser.Lex();
+    else {
+      reportParseError("unexpected token, expected comma");
+      return false;
+    }
+    TmpReg.clear();
+    ResTy = parseAnyRegister(TmpReg);
+    if (ResTy == MatchOperand_NoMatch || ResTy == MatchOperand_ParseFail) {
+      reportParseError("expected return register");
+      return false;
+    }
+    MipsOperand &ReturnRegOpnd = static_cast<MipsOperand &>(*TmpReg[0]);
+    if (!ReturnRegOpnd.isGPRAsmReg()) {
+      reportParseError(ReturnRegOpnd.getStartLoc(), "expected general purpose register");
+      return false;
+    }
+    if (getLexer().isNot(AsmToken::EndOfStatement)) {
+      reportParseError("unexpected token, expected end of statement");
+      return false;
+    }
+    getTargetStreamer().emitFrame(StackReg, FrameSizeVal, ReturnRegOpnd.getGPR32Reg());
+    IsCpRestoreSet = false;
+    return false;
+  }
+  if (IDVal == ".set") {
+    parseDirectiveSet();
+    return false;
+  }
+  if (IDVal == ".mask" || IDVal == ".fmask") {
+    const MCExpr *BitMask;
+    int64_t BitMaskVal;
+    if (Parser.parseExpression(BitMask)) {
+      reportParseError("expected bitmask value");
+      return false;
+    }
+    if (!BitMask->evaluateAsAbsolute(BitMaskVal)) {
+      reportParseError("bitmask not an absolute expression");
+      return false;
+    }
+    if (Parser.getTok().is(AsmToken::Comma))
+      Parser.Lex();
+    else {
+      reportParseError("unexpected token, expected comma");
+      return false;
+    }
+    const MCExpr *FrameOffset;
+    int64_t FrameOffsetVal;
+    if (Parser.parseExpression(FrameOffset)) {
+      reportParseError("expected frame offset value");
+      return false;
+    }
+    if (!FrameOffset->evaluateAsAbsolute(FrameOffsetVal)) {
+      reportParseError("frame offset not an absolute expression");
+      return false;
+    }
+    if (getLexer().isNot(AsmToken::EndOfStatement)) {
+      reportParseError("unexpected token, expected end of statement");
+      return false;
+    }
+    if (IDVal == ".mask")
+      getTargetStreamer().emitMask(BitMaskVal, FrameOffsetVal);
+    else
+      getTargetStreamer().emitFMask(BitMaskVal, FrameOffsetVal);
+    return false;
+  }
+  if (IDVal == ".nan")
+    return parseDirectiveNaN();
+
+  if (IDVal == ".gpword") {
+    parseDirectiveGpWord();
+    return false;
+  }
+  if (IDVal == ".gpdword") {
+    parseDirectiveGpDWord();
+    return false;
+  }
+
+  if (IDVal == ".dtprelword") {
+    parseDirectiveDtpRelWord();
+    return false;
+  }
+  if (IDVal == ".dtpreldword") {
+    parseDirectiveDtpRelDWord();
+    return false;
+  }
+  if (IDVal == ".tprelword") {
+    parseDirectiveTpRelWord();
+    return false;
+  }
+  if (IDVal == ".tpreldword") {
+    parseDirectiveTpRelDWord();
+    return false;
+  }
+  if (IDVal == ".option") {
+    parseDirectiveOption();
+    return false;
+  }
+  if (IDVal == ".abicalls") {
+    getTargetStreamer().emitDirectiveAbiCalls();
+    if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
+      Error(Parser.getTok().getLoc(), "unexpected token, expected end of statement");
+    }
+    return false;
+  }
+  if (IDVal == ".cpsetup") {
+    parseDirectiveCPSetup();
+    return false;
+  }
+  if (IDVal == ".cpreturn") {
+    parseDirectiveCPReturn();
+    return false;
+  }
+  if (IDVal == ".module") {
+    parseDirectiveModule();
+    return false;
+  }
+  if (IDVal == ".llvm_internal_mips_reallow_module_directive") {
+    parseInternalDirectiveReallowModule();
+    return false;
+  }
+  if (IDVal == ".insn") {
+    parseInsnDirective();
+    return false;
+  }
+  if (IDVal == ".rdata") {
+    parseRSectionDirective(".rodata");
+    return false;
+  }
+  if (IDVal == ".sbss") {
+    parseSSectionDirective(IDVal, ELF::SHT_NOBITS);
+    return false;
+  }
+  if (IDVal == ".sdata") {
+    parseSSectionDirective(IDVal, ELF::SHT_PROGBITS);
+    return false;
+  }
+  return true;
+}

Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/ParseInstruction.cpp

@@ -0,0 +1,38 @@
+bool MipsAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands) {
+  MCAsmParser &Parser = getParser();
+  LLVM_DEBUG(dbgs() << "ParseInstruction\n");
+  getTargetStreamer().forbidModuleDirective();
+  if (!mnemonicIsValid(Name, 0)) {
+    FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
+    std::string Suggestion = MipsMnemonicSpellCheck(Name, FBS);
+    return Error(NameLoc, "unknown instruction" + Suggestion);
+  }
+  Operands.push_back(MipsOperand::CreateToken(Name, NameLoc, *this));
+  if (getLexer().isNot(AsmToken::EndOfStatement)) {
+    if (parseOperand(Operands, Name)) {
+      SMLoc Loc = getLexer().getLoc();
+      return Error(Loc, "unexpected token in argument list");
+    }
+    if (getLexer().is(AsmToken::LBrac) && parseBracketSuffix(Name, Operands))
+      return true;
+    while (getLexer().is(AsmToken::Comma)) {
+      Parser.Lex();
+      if (parseOperand(Operands, Name)) {
+        SMLoc Loc = getLexer().getLoc();
+        return Error(Loc, "unexpected token in argument list");
+      }
+      if (getLexer().is(AsmToken::LBrac)) {
+        if (parseBracketSuffix(Name, Operands))
+          return true;
+      }
+      else if (getLexer().is(AsmToken::LParen) && parseParenSuffix(Name, Operands))
+        return true;
+    }
+  }
+  if (getLexer().isNot(AsmToken::EndOfStatement)) {
+    SMLoc Loc = getLexer().getLoc();
+    return Error(Loc, "unexpected token in argument list");
+  }
+  Parser.Lex();
+  return false;
+}

Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/ParseRegister.cpp

@@ -0,0 +1,3 @@
+bool MipsAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
+  return tryParseRegister(RegNo, StartLoc, EndLoc) != MatchOperand_Success;
+}

Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/addCSRSystemRegisterOperands.cpp

@@ -0,0 +1 @@
+None

Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/addExpr.cpp

@@ -0,0 +1,8 @@
+void addExpr(MCInst &Inst, const MCExpr *Expr) const {
+    if (!Expr)
+      Inst.addOperand(MCOperand::createImm(0));
+    else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
+      Inst.addOperand(MCOperand::createImm(CE->getValue()));
+    else
+      Inst.addOperand(MCOperand::createExpr(Expr));
+  }

Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/addFRMArgOperands.cpp

@@ -0,0 +1 @@
+None

Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/addFenceArgOperands.cpp

@@ -0,0 +1 @@
+None

Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/addImmOperands.cpp

@@ -0,0 +1,4 @@
+void addImmOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    addExpr(Inst, getImm());
+}

Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/addRegOperands.cpp

@@ -0,0 +1,3 @@
+void addRegOperands(MCInst &Inst, unsigned N) const {
+    llvm_unreachable("Use a custom parser instead");
+}

Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/addVTypeIOperands.cpp

@@ -0,0 +1 @@
+None

Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/classifySymbolRef.cpp

@@ -0,0 +1 @@
+None

Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/convertFPR64ToFPR16.cpp

@@ -0,0 +1 @@
+None

Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/convertFPR64ToFPR32.cpp

@@ -0,0 +1 @@
+None

Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/createImm.cpp

@@ -0,0 +1,7 @@
+static std::unique_ptr<MipsOperand> createImm(const MCExpr *Val, SMLoc S, SMLoc E, MipsAsmParser &Parser) {
+  auto Op = std::make_unique<MipsOperand>(k_Immediate, Parser);
+  Op->Imm.Val = Val;
+  Op->StartLoc = S;
+  Op->EndLoc = E;
+  return Op;
+}

Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/createReg.cpp

@@ -0,0 +1,11 @@
+static std::unique_ptr<MipsOperand> CreateReg(unsigned Index, StringRef Str, RegKind RegKind, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E, MipsAsmParser &Parser) {
+  auto Op = std::make_unique<MipsOperand>(k_RegisterIndex, Parser);
+  Op->RegIdx.Index = Index;
+  Op->RegIdx.RegInfo = RegInfo;
+  Op->RegIdx.Kind = RegKind;
+  Op->RegIdx.Tok.Data = Str.data();
+  Op->RegIdx.Tok.Length = Str.size();
+  Op->StartLoc = S;
+  Op->EndLoc = E;
+  return Op;
+}

Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/createSysReg.cpp

@@ -0,0 +1 @@
+None

Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/createToken.cpp

@@ -0,0 +1,8 @@
+static std::unique_ptr<MipsOperand> CreateToken(StringRef Str, SMLoc S, MipsAsmParser &Parser) {
+  auto Op = std::make_unique<MipsOperand>(k_Token, Parser);
+  Op->Tok.Data = Str.data();
+  Op->Tok.Length = Str.size();
+  Op->StartLoc = S;
+  Op->EndLoc = S;
+  return Op;
+}

Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/createVType.cpp

@@ -0,0 +1 @@
+None

Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/defaultMaskRegOp.cpp

@@ -0,0 +1 @@
+None

Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/emitToStreamer.cpp

@@ -0,0 +1 @@
+None

Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/evaluateConstantImm.cpp

@@ -0,0 +1 @@
+None

Scripts/Exp/ForkFlow/Mips_Code/PULP/Assembler/AsmParser/generateImmOutOfRangeError.cpp

@@ -0,0 +1 @@
+None